From 7076dd52ceb86eedd1527b5c2b6a23ccaf00409b Mon Sep 17 00:00:00 2001 From: Andrey Bondar Date: Mon, 24 Apr 2023 16:02:10 +0300 Subject: [PATCH 1/2] rtl8192cd: code cleanup (changing some files permissions, converting from DOS) --- package/kernel/rtl8192cd/8192c_reg.h | 4974 +- package/kernel/rtl8192cd/8192cd_11v.c | 2398 +- package/kernel/rtl8192cd/8192cd_11v.h | 148 +- package/kernel/rtl8192cd/8192cd_a4_sta.c | 1700 +- package/kernel/rtl8192cd/8192cd_comapi.c | 7352 +-- package/kernel/rtl8192cd/8192cd_comapi.h | 226 +- package/kernel/rtl8192cd/8192cd_debug.c | 514 +- package/kernel/rtl8192cd/8192cd_dfs_det.c | 2942 +- package/kernel/rtl8192cd/8192cd_dmem.c | 572 +- package/kernel/rtl8192cd/8192cd_dmem.h | 88 +- package/kernel/rtl8192cd/8192cd_hw.c | 0 package/kernel/rtl8192cd/8192cd_hw.h | 0 package/kernel/rtl8192cd/8192cd_ioctl.c | 0 package/kernel/rtl8192cd/8192cd_led.c | 0 package/kernel/rtl8192cd/8192cd_log.h | 90 +- package/kernel/rtl8192cd/8192cd_mib.c | 1120 +- package/kernel/rtl8192cd/8192cd_mib.h | 174 +- package/kernel/rtl8192cd/8192cd_net80211.c | 4010 +- package/kernel/rtl8192cd/8192cd_net80211.h | 72 +- package/kernel/rtl8192cd/8192cd_osdep.c | 26 +- package/kernel/rtl8192cd/8192cd_p2p.c | 0 package/kernel/rtl8192cd/8192cd_p2p.h | 1418 +- package/kernel/rtl8192cd/8192cd_phyreg.h | 2028 +- package/kernel/rtl8192cd/8192cd_proc.c | 0 package/kernel/rtl8192cd/8192cd_profile.h | 64 +- package/kernel/rtl8192cd/8192cd_psk.h | 6 +- .../kernel/rtl8192cd/8192cd_smart_roaming.c | 1602 +- package/kernel/rtl8192cd/8192cd_sme.c | 4 +- package/kernel/rtl8192cd/8192cd_sta_control.c | 4600 +- package/kernel/rtl8192cd/8192cd_tx.c | 0 package/kernel/rtl8192cd/8192cd_util.c | 0 package/kernel/rtl8192cd/8192cd_util.h | 0 package/kernel/rtl8192cd/8192d_hw.c | 1760 +- package/kernel/rtl8192cd/8192e_reg.h | 0 package/kernel/rtl8192cd/8723b_reg.h | 3530 +- package/kernel/rtl8192cd/8812_hw.c | 7598 +-- package/kernel/rtl8192cd/8812_reg.h | 0 package/kernel/rtl8192cd/8812_vht_gen.c | 0 package/kernel/rtl8192cd/8812_vht_gen.h | 0 package/kernel/rtl8192cd/Beamforming.c | 0 package/kernel/rtl8192cd/Beamforming.h | 446 +- package/kernel/rtl8192cd/EdcaTurboCheck.c | 0 package/kernel/rtl8192cd/EdcaTurboCheck.h | 70 +- package/kernel/rtl8192cd/Hal8188EPwrSeq.c | 206 +- package/kernel/rtl8192cd/Hal8188EPwrSeq.h | 328 +- package/kernel/rtl8192cd/Hal8192CDMOutSrc.c | 19262 ++++---- package/kernel/rtl8192cd/Hal8723BPwrSeq.c | 190 +- package/kernel/rtl8192cd/Hal8723BPwrSeq.h | 366 +- package/kernel/rtl8192cd/Hal8812PwrSeq.c | 200 +- package/kernel/rtl8192cd/Hal8812PwrSeq.h | 398 +- package/kernel/rtl8192cd/Hal8821APwrSeq.c | 194 +- package/kernel/rtl8192cd/Hal8821APwrSeq.h | 324 +- package/kernel/rtl8192cd/HalDMOutSrc.c | 0 package/kernel/rtl8192cd/HalPwrSeqCmd.c | 350 +- package/kernel/rtl8192cd/HalPwrSeqCmd.h | 218 +- package/kernel/rtl8192cd/Makefile.ecos | 0 package/kernel/rtl8192cd/RateAdaptive.c | 1162 +- .../rtl8192cd/WlanHAL/Config/HalCfg.h_8192EE | 212 +- .../rtl8192cd/WlanHAL/Config/HalCfg.h_8881A | 212 +- .../WlanHAL/Data/8192E/AGC_TAB_8192E.txt | 260 +- .../WlanHAL/Data/8192E/AGC_TAB_8192ES.txt | 264 +- .../Data/8192E/AGC_TAB_8192ES_extlna.txt | 266 +- .../Data/8192E/AGC_TAB_8192E_extlna.txt | 264 +- .../Data/8192E/AGC_TAB_8192E_extlna_type1.txt | 264 +- .../Data/8192E/AGC_TAB_8192E_extlna_type2.txt | 264 +- .../Data/8192E/AGC_TAB_8192E_extlna_type3.txt | 264 +- .../Data/8192E/AGC_TAB_8192E_extpa.txt | 264 +- .../WlanHAL/Data/8192E/AGC_TAB_8192E_hp.txt | 264 +- .../WlanHAL/Data/8192E/AGC_TAB_8192Emp.txt | 264 +- .../Data/8192E/MACDM_def_high_8192E.txt | 6 +- .../Data/8192E/MACDM_def_low_8192E.txt | 6 +- .../Data/8192E/MACDM_def_normal_8192E.txt | 6 +- .../Data/8192E/MACDM_gen_high_8192E.txt | 6 +- .../Data/8192E/MACDM_gen_low_8192E.txt | 6 +- .../Data/8192E/MACDM_gen_normal_8192E.txt | 6 +- .../Data/8192E/MACDM_state_criteria_8192E.txt | 68 +- .../Data/8192E/MACDM_txop_high_8192E.txt | 6 +- .../Data/8192E/MACDM_txop_low_8192E.txt | 6 +- .../Data/8192E/MACDM_txop_normal_8192E.txt | 6 +- .../WlanHAL/Data/8192E/MAC_REG_8192E.txt | 204 +- .../WlanHAL/Data/8192E/MAC_REG_8192Eb.txt | 192 +- .../WlanHAL/Data/8192E/MAC_REG_8192Emp.txt | 222 +- .../WlanHAL/Data/8192E/PHY_REG_8192E.txt | 468 +- .../Data/8192E/PHY_REG_8192ES_extlna.txt | 478 +- .../Data/8192E/PHY_REG_8192E_extlna.txt | 476 +- .../Data/8192E/PHY_REG_8192E_extpa.txt | 476 +- .../WlanHAL/Data/8192E/PHY_REG_8192E_hp.txt | 476 +- .../WlanHAL/Data/8192E/PHY_REG_8192Eb.txt | 468 +- .../WlanHAL/Data/8192E/PHY_REG_8192Emp.txt | 476 +- .../WlanHAL/Data/8192E/PHY_REG_MP_8192E.txt | 2 +- .../WlanHAL/Data/8192E/PHY_REG_MP_8192Emp.txt | 2 +- .../WlanHAL/Data/8192E/PHY_REG_PG_8192E.txt | 288 +- .../Data/8192E/PHY_REG_PG_8192E_new.txt | 42 +- .../WlanHAL/Data/8192E/PHY_REG_PG_8192Emp.txt | 42 +- .../Data/8192E/PHY_REG_PG_8192Emp_hp.txt | 42 +- .../WlanHAL/Data/8192E/RadioA_8192E.txt | 358 +- .../WlanHAL/Data/8192E/RadioA_8192ES.txt | 242 +- .../Data/8192E/RadioA_8192ES_extlna.txt | 254 +- .../Data/8192E/RadioA_8192E_extlna.txt | 252 +- .../WlanHAL/Data/8192E/RadioA_8192E_extpa.txt | 240 +- .../WlanHAL/Data/8192E/RadioA_8192E_hp.txt | 240 +- .../WlanHAL/Data/8192E/RadioA_8192Eb.txt | 354 +- .../WlanHAL/Data/8192E/RadioA_8192Emp.txt | 252 +- .../WlanHAL/Data/8192E/RadioA_8192EmpA.txt | 240 +- .../WlanHAL/Data/8192E/RadioB_8192E.txt | 336 +- .../WlanHAL/Data/8192E/RadioB_8192ES.txt | 184 +- .../Data/8192E/RadioB_8192ES_extlna.txt | 186 +- .../Data/8192E/RadioB_8192E_extlna.txt | 184 +- .../WlanHAL/Data/8192E/RadioB_8192E_extpa.txt | 184 +- .../WlanHAL/Data/8192E/RadioB_8192E_hp.txt | 184 +- .../WlanHAL/Data/8192E/RadioB_8192Eb.txt | 330 +- .../WlanHAL/Data/8192E/RadioB_8192Emp.txt | 184 +- .../WlanHAL/Data/8192E/RadioB_8192EmpA.txt | 184 +- .../WlanHAL/Data/8192E/TXPWR_LMT_92EE_hp.txt | 702 +- .../WlanHAL/Data/8192E/TXPWR_LMT_92EE_new.txt | 702 +- .../WlanHAL/Data/8192E/TxPowerTrack_AP.txt | 74 +- .../WlanHAL/Data/8192E/rtl8192Efw.bin | Bin .../WlanHAL/Data/8192E/rtl8192EfwMP.bin | Bin .../WlanHAL/Data/8197F/AGC_TAB_8197F.txt | 268 +- .../WlanHAL/Data/8197F/AGC_TAB_8197F_hp.txt | 276 +- .../WlanHAL/Data/8197F/AGC_TAB_8197Fmp.txt | 276 +- .../WlanHAL/Data/8197F/AGC_TAB_8197Fmp_hp.txt | 540 +- .../Data/8197F/MACDM_def_high_8197F.txt | 6 +- .../Data/8197F/MACDM_def_low_8197F.txt | 6 +- .../Data/8197F/MACDM_def_normal_8197F.txt | 6 +- .../Data/8197F/MACDM_gen_high_8197F.txt | 6 +- .../Data/8197F/MACDM_gen_low_8197F.txt | 6 +- .../Data/8197F/MACDM_gen_normal_8197F.txt | 6 +- .../Data/8197F/MACDM_state_criteria_8197F.txt | 68 +- .../Data/8197F/MACDM_txop_high_8197F.txt | 6 +- .../Data/8197F/MACDM_txop_low_8197F.txt | 6 +- .../Data/8197F/MACDM_txop_normal_8197F.txt | 6 +- .../WlanHAL/Data/8197F/MAC_REG_8197F.txt | 308 +- .../WlanHAL/Data/8197F/MAC_REG_8197Fmp.txt | 268 +- .../WlanHAL/Data/8197F/PHY_REG_8197F.txt | 984 +- .../WlanHAL/Data/8197F/PHY_REG_8197F_hp.txt | 1918 +- .../WlanHAL/Data/8197F/PHY_REG_8197Fmp.txt | 792 +- .../WlanHAL/Data/8197F/PHY_REG_8197Fmp_hp.txt | 3772 +- .../WlanHAL/Data/8197F/PHY_REG_MP_8197F.txt | 4 +- .../WlanHAL/Data/8197F/PHY_REG_MP_8197Fmp.txt | 6 +- .../WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type0.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type1.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type2.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type3.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type4.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type5.txt | 44 +- .../Data/8197F/PHY_REG_PG_8197Fmp_Type6.txt | 44 +- .../WlanHAL/Data/8197F/RadioA_8197F.txt | 158 +- .../WlanHAL/Data/8197F/RadioB_8197F.txt | 102 +- .../WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_TXBF.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type0.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type1.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type2.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type3.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type4.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type5.txt | 456 +- .../Data/8197F/TXPWR_LMT_8197Fmp_Type6.txt | 456 +- .../Data/8197F/TxPowerTrack_AP_8197Fmp.txt | 24 +- .../rtl8192cd/WlanHAL/Data/8197F/Version.txt | 2 +- .../WlanHAL/Data/8197F/rtl8197Ffw.bin | Bin .../WlanHAL/Data/8814A/AGC_TAB_8814A.txt | 276 +- .../WlanHAL/Data/8814A/AGC_TAB_8814A_hp.txt | 276 +- .../WlanHAL/Data/8814A/AGC_TAB_8814Amp.txt | 276 +- .../WlanHAL/Data/8814A/AGC_TAB_8814Amp_hp.txt | 540 +- .../Data/8814A/MACDM_def_high_8814A.txt | 6 +- .../Data/8814A/MACDM_def_low_8814A.txt | 6 +- .../Data/8814A/MACDM_def_normal_8814A.txt | 6 +- .../Data/8814A/MACDM_gen_high_8814A.txt | 6 +- .../Data/8814A/MACDM_gen_low_8814A.txt | 6 +- .../Data/8814A/MACDM_gen_normal_8814A.txt | 6 +- .../Data/8814A/MACDM_state_criteria_8814A.txt | 68 +- .../Data/8814A/MACDM_txop_high_8814A.txt | 6 +- .../Data/8814A/MACDM_txop_low_8814A.txt | 6 +- .../Data/8814A/MACDM_txop_normal_8814A.txt | 6 +- .../WlanHAL/Data/8814A/MAC_REG_8814A.txt | 264 +- .../WlanHAL/Data/8814A/MAC_REG_8814Amp.txt | 268 +- .../WlanHAL/Data/8814A/PHY_REG_8814A.txt | 1918 +- .../WlanHAL/Data/8814A/PHY_REG_8814A_hp.txt | 1918 +- .../WlanHAL/Data/8814A/PHY_REG_8814Amp.txt | 792 +- .../WlanHAL/Data/8814A/PHY_REG_8814Amp_hp.txt | 3772 +- .../WlanHAL/Data/8814A/PHY_REG_MP_8814A.txt | 4 +- .../WlanHAL/Data/8814A/PHY_REG_MP_8814Amp.txt | 6 +- .../WlanHAL/Data/8814A/PHY_REG_PG_8814A.txt | 220 +- .../WlanHAL/Data/8814A/PHY_REG_PG_8814Amp.txt | 302 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type0.txt | 302 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type2.txt | 302 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type3.txt | 302 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type4.txt | 302 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type5.txt | 304 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type7.txt | 304 +- .../Data/8814A/PHY_REG_PG_8814Amp_Type8.txt | 302 +- .../WlanHAL/Data/8814A/RadioA_8814A.txt | 646 +- .../WlanHAL/Data/8814A/RadioA_8814A_hp.txt | 642 +- .../WlanHAL/Data/8814A/RadioA_8814Amp.txt | 640 +- .../WlanHAL/Data/8814A/RadioA_8814Amp_hp.txt | 810 +- .../WlanHAL/Data/8814A/RadioB_8814A.txt | 480 +- .../WlanHAL/Data/8814A/RadioB_8814A_hp.txt | 476 +- .../WlanHAL/Data/8814A/RadioB_8814Amp.txt | 478 +- .../WlanHAL/Data/8814A/RadioB_8814Amp_hp.txt | 644 +- .../WlanHAL/Data/8814A/RadioC_8814A.txt | 480 +- .../WlanHAL/Data/8814A/RadioC_8814A_hp.txt | 476 +- .../WlanHAL/Data/8814A/RadioC_8814Amp.txt | 478 +- .../WlanHAL/Data/8814A/RadioC_8814Amp_hp.txt | 644 +- .../WlanHAL/Data/8814A/RadioD_8814A.txt | 480 +- .../WlanHAL/Data/8814A/RadioD_8814A_hp.txt | 476 +- .../WlanHAL/Data/8814A/RadioD_8814Amp.txt | 478 +- .../WlanHAL/Data/8814A/RadioD_8814Amp_hp.txt | 654 +- .../WlanHAL/Data/8814A/TXPWR_LMT_8814A.txt | 650 +- .../WlanHAL/Data/8814A/TXPWR_LMT_8814Amp.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_TXBF.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type0.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type2.txt | 1112 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type3.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type4.txt | 1112 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type5.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type7.txt | 1110 +- .../Data/8814A/TXPWR_LMT_8814Amp_Type8.txt | 1112 +- .../Data/8814A/TxPowerTrack_AP_8814A.txt | 86 +- .../Data/8814A/TxPowerTrack_AP_8814Amp.txt | 158 +- .../rtl8192cd/WlanHAL/Data/8814A/Version.txt | 2 +- .../WlanHAL/Data/8814A/rtl8814Afw.bin | Bin .../WlanHAL/Data/8814A/rtl8814AfwMP.bin | Bin .../WlanHAL/Data/8822B/AGC_TAB_8822B.txt | 276 +- .../WlanHAL/Data/8822B/AGC_TAB_8822B_hp.txt | 276 +- .../WlanHAL/Data/8822B/AGC_TAB_8822Bmp.txt | 276 +- .../WlanHAL/Data/8822B/AGC_TAB_8822Bmp_hp.txt | 662 +- .../Data/8822B/MACDM_def_high_8822B.txt | 6 +- .../Data/8822B/MACDM_def_low_8822B.txt | 6 +- .../Data/8822B/MACDM_def_normal_8822B.txt | 6 +- .../Data/8822B/MACDM_gen_high_8822B.txt | 6 +- .../Data/8822B/MACDM_gen_low_8822B.txt | 6 +- .../Data/8822B/MACDM_gen_normal_8822B.txt | 6 +- .../Data/8822B/MACDM_state_criteria_8822B.txt | 68 +- .../Data/8822B/MACDM_txop_high_8822B.txt | 6 +- .../Data/8822B/MACDM_txop_low_8822B.txt | 6 +- .../Data/8822B/MACDM_txop_normal_8822B.txt | 6 +- .../WlanHAL/Data/8822B/MAC_REG_8822B.txt | 264 +- .../WlanHAL/Data/8822B/MAC_REG_8822Bmp.txt | 270 +- .../WlanHAL/Data/8822B/PHY_REG_8822B.txt | 1918 +- .../WlanHAL/Data/8822B/PHY_REG_8822B_hp.txt | 1918 +- .../WlanHAL/Data/8822B/PHY_REG_8822Bmp.txt | 792 +- .../WlanHAL/Data/8822B/PHY_REG_8822Bmp_hp.txt | 2602 +- .../WlanHAL/Data/8822B/PHY_REG_MP_8822B.txt | 4 +- .../WlanHAL/Data/8822B/PHY_REG_MP_8822Bmp.txt | 6 +- .../WlanHAL/Data/8822B/PHY_REG_PG_8822B.txt | 220 +- .../WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type0.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type1.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type10.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type11.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type13.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type14.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type2.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type3.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type4.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type5.txt | 304 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type6.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type7.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type8.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_Type9.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_hp.txt | 302 +- .../Data/8822B/PHY_REG_PG_8822Bmp_intpa.txt | 302 +- .../WlanHAL/Data/8822B/RadioA_8822B.txt | 646 +- .../WlanHAL/Data/8822B/RadioA_8822B_hp.txt | 642 +- .../WlanHAL/Data/8822B/RadioA_8822Bmp.txt | 640 +- .../WlanHAL/Data/8822B/RadioA_8822Bmp_hp.txt | 878 +- .../WlanHAL/Data/8822B/RadioB_8822B.txt | 480 +- .../WlanHAL/Data/8822B/RadioB_8822B_hp.txt | 476 +- .../WlanHAL/Data/8822B/RadioB_8822Bmp.txt | 478 +- .../WlanHAL/Data/8822B/RadioB_8822Bmp_hp.txt | 792 +- .../WlanHAL/Data/8822B/RadioC_8822B.txt | 480 +- .../WlanHAL/Data/8822B/RadioC_8822B_hp.txt | 476 +- .../WlanHAL/Data/8822B/RadioC_8822Bmp.txt | 478 +- .../WlanHAL/Data/8822B/RadioC_8822Bmp_hp.txt | 644 +- .../WlanHAL/Data/8822B/RadioD_8822B.txt | 480 +- .../WlanHAL/Data/8822B/RadioD_8822B_hp.txt | 476 +- .../WlanHAL/Data/8822B/RadioD_8822Bmp.txt | 478 +- .../WlanHAL/Data/8822B/RadioD_8822Bmp_hp.txt | 654 +- .../WlanHAL/Data/8822B/TXPWR_LMT_8822B.txt | 650 +- .../WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_TXBF.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type0.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type1.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type10.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type11.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type13.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type14.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type2.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type3.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type4.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type5.txt | 1110 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type6.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type7.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type8.txt | 1112 +- .../Data/8822B/TXPWR_LMT_8822Bmp_Type9.txt | 1110 +- .../Data/8822B/TxPowerTrack_AP_8822B.txt | 86 +- .../Data/8822B/TxPowerTrack_AP_8822Bmp.txt | 52 +- .../rtl8192cd/WlanHAL/Data/8822B/Version.txt | 2 +- .../WlanHAL/Data/8822B/rtl8822Bfw.bin | Bin .../WlanHAL/Data/8822B/rtl8822BfwMP.bin | Bin .../WlanHAL/Data/8881A/V700/AGC_TAB_8881A.txt | 260 +- .../WlanHAL/Data/8881A/V700/MAC_REG_8881A.txt | 196 +- .../Data/8881A/V700/PHY_REG_1T_8881A.txt | 460 +- .../WlanHAL/Data/8881A/V700/PHY_REG_8881A.txt | 390 +- .../Data/8881A/V700/PHY_REG_MP_8881A.txt | 4 +- .../Data/8881A/V700/PHY_REG_PG_8881A.txt | 288 +- .../Data/8881A/V700/RTL8881FW_Test_T.BIN | Bin .../Data/8881A/V700/RTL8881TXBUF_Test_T.BIN | Bin .../WlanHAL/Data/8881A/V700/RadioA_8881A.txt | 612 +- .../Data/8881A/V702B/AGC_TAB_8881A.txt | 260 +- .../Data/8881A/V702B/MAC_REG_8881A.txt | 196 +- .../Data/8881A/V702B/PHY_REG_1T_8881A.txt | 460 +- .../Data/8881A/V702B/PHY_REG_8881A.txt | 390 +- .../Data/8881A/V702B/PHY_REG_MP_8881A.txt | 4 +- .../Data/8881A/V702B/PHY_REG_PG_8881A.txt | 288 +- .../Data/8881A/V702B/RTL8881FW_Test_T.BIN | Bin .../Data/8881A/V702B/RTL8881TXBUF_Test_T.BIN | Bin .../WlanHAL/Data/8881A/V702B/RadioA_8881A.txt | 612 +- .../Data/8881A/V702B_MP/AGC_TAB_8881ABP.txt | 524 +- .../8881A/V702B_MP/AGC_TAB_8881ABP_intpa.txt | 524 +- .../Data/8881A/V702B_MP/AGC_TAB_8881AMP.txt | 524 +- .../8881A/V702B_MP/AGC_TAB_8881AMP_2layer.txt | 524 +- .../8881A/V702B_MP/AGC_TAB_8881AMP_intpa.txt | 524 +- .../Data/8881A/V702B_MP/AGC_TAB_8881AN.txt | 524 +- .../8881A/V702B_MP/AGC_TAB_8881AN_extpa.txt | 524 +- .../Data/8881A/V702B_MP/AGC_TAB_8881Am.txt | 524 +- .../8881A/V702B_MP/MACDM_def_high_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_def_low_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_def_normal_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_gen_high_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_gen_low_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_gen_normal_8881A.txt | 6 +- .../V702B_MP/MACDM_state_criteria_8881A.txt | 28 +- .../8881A/V702B_MP/MACDM_txop_high_8881A.txt | 6 +- .../8881A/V702B_MP/MACDM_txop_low_8881A.txt | 6 +- .../V702B_MP/MACDM_txop_normal_8881A.txt | 6 +- .../Data/8881A/V702B_MP/MAC_REG_8881Am.txt | 202 +- .../Data/8881A/V702B_MP/PHY_REG_8881AMP.txt | 392 +- .../Data/8881A/V702B_MP/PHY_REG_8881Am.txt | 392 +- .../Data/8881A/V702B_MP/PHY_REG_MP_8881A.txt | 4 +- .../8881A/V702B_MP/PHY_REG_PG_8881ABP.txt | 104 +- .../V702B_MP/PHY_REG_PG_8881ABP_intpa.txt | 106 +- .../8881A/V702B_MP/PHY_REG_PG_8881AMP.txt | 104 +- .../V702B_MP/PHY_REG_PG_8881AMP_intpa.txt | 106 +- .../Data/8881A/V702B_MP/PHY_REG_PG_8881AN.txt | 106 +- .../V702B_MP/PHY_REG_PG_8881AN_extpa.txt | 104 +- .../8881A/V702B_MP/PHY_REG_PG_8881A_new.txt | 100 +- .../Data/8881A/V702B_MP/PHY_REG_PG_8881Am.txt | 100 +- .../Data/8881A/V702B_MP/RTL8881FW_A_CUT_T.BIN | Bin .../8881A/V702B_MP/RTL8881TXBUF_A_CUT_T.BIN | Bin .../Data/8881A/V702B_MP/RadioA_8881ABP.txt | 794 +- .../8881A/V702B_MP/RadioA_8881ABP_intpa.txt | 738 +- .../Data/8881A/V702B_MP/RadioA_8881AMP.txt | 740 +- .../8881A/V702B_MP/RadioA_8881AMP_2layer.txt | 740 +- .../8881A/V702B_MP/RadioA_8881AMP_intpa.txt | 738 +- .../Data/8881A/V702B_MP/RadioA_8881AN.txt | 738 +- .../8881A/V702B_MP/RadioA_8881AN_extpa.txt | 740 +- .../Data/8881A/V702B_MP/RadioA_8881Am.txt | 816 +- .../Data/8881A/V702B_MP/TXPWR_LMT_8881ABP.txt | 652 +- .../V702B_MP/TXPWR_LMT_8881ABP_intpa.txt | 652 +- .../Data/8881A/V702B_MP/TXPWR_LMT_8881AMP.txt | 652 +- .../V702B_MP/TXPWR_LMT_8881AMP_intpa.txt | 652 +- .../Data/8881A/V702B_MP/TXPWR_LMT_8881AN.txt | 652 +- .../8881A/V702B_MP/TXPWR_LMT_8881AN_extpa.txt | 652 +- .../8881A/V702B_MP/TXPWR_LMT_8881A_new.txt | 702 +- .../8881A/V702B_MP/TxPowerTrack_AP_8881A.txt | 48 +- .../V702B_MP/TxPowerTrack_AP_8881ABP.txt | 48 +- .../TxPowerTrack_AP_8881ABP_intpa.txt | 48 +- .../V702B_MP/TxPowerTrack_AP_8881AMP.txt | 50 +- .../TxPowerTrack_AP_8881AMP_intpa.txt | 48 +- .../8881A/V702B_MP/TxPowerTrack_AP_8881AN.txt | 48 +- .../V702B_MP/TxPowerTrack_AP_8881AN_extpa.txt | 48 +- .../8881A/V702B_Skyworth/AGC_TAB_8881A.txt | 260 +- .../8881A/V702B_Skyworth/MAC_REG_8881A.txt | 196 +- .../8881A/V702B_Skyworth/PHY_REG_1T_8881A.txt | 460 +- .../8881A/V702B_Skyworth/PHY_REG_8881A.txt | 390 +- .../8881A/V702B_Skyworth/PHY_REG_MP_8881A.txt | 4 +- .../8881A/V702B_Skyworth/PHY_REG_PG_8881A.txt | 288 +- .../8881A/V702B_Skyworth/RTL8881FW_Test_T.BIN | Bin .../V702B_Skyworth/RTL8881TXBUF_Test_T.BIN | Bin .../8881A/V702B_Skyworth/RadioA_8881A.txt | 612 +- package/kernel/rtl8192cd/WlanHAL/HalCfg.c | 0 package/kernel/rtl8192cd/WlanHAL/HalCfg.h | 0 package/kernel/rtl8192cd/WlanHAL/HalCommon.c | 0 package/kernel/rtl8192cd/WlanHAL/HalCommon.h | 326 +- package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.c | 0 package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.h | 0 package/kernel/rtl8192cd/WlanHAL/HalDef.h | 0 .../rtl8192cd/WlanHAL/HalHeader/HalComBit.h | 0 .../WlanHAL/HalHeader/HalComPhyBit.h | 1392 +- .../WlanHAL/HalHeader/HalComPhyReg.h | 1384 +- .../WlanHAL/HalHeader/HalComRXDesc.h | 0 .../rtl8192cd/WlanHAL/HalHeader/HalComReg.h | 3854 +- .../WlanHAL/HalHeader/HalComTXDesc.h | 0 .../rtl8192cd/WlanHAL/HalHeader/HalHWCfg.h | 0 .../WlanHAL/HalMac88XX/halmac_2_platform.h | 240 +- .../HalMac88XX/halmac_2_platform_temp.h | 0 .../halmac_8197f/halmac_8197f_cfg.h | 0 .../halmac_8197f/halmac_8197f_pwr_seq.c | 0 .../halmac_8197f/halmac_8197f_pwr_seq.h | 0 .../halmac_8197f/halmac_api_8197f.c | 0 .../halmac_8197f/halmac_api_8197f.h | 0 .../halmac_8197f/halmac_api_8197f_pcie.c | 0 .../halmac_8197f/halmac_api_8197f_pcie.h | 0 .../halmac_8197f/halmac_api_8197f_sdio.c | 0 .../halmac_8197f/halmac_api_8197f_sdio.h | 0 .../halmac_8197f/halmac_api_8197f_usb.c | 0 .../halmac_8197f/halmac_api_8197f_usb.h | 0 .../halmac_8197f/halmac_func_8197f.c | 0 .../halmac_8197f/halmac_func_8197f.h | 0 .../halmac_8821c/RTL8821Cfw_NIC.bin | Bin .../halmac_8821c/halmac_8821c_cfg.h | 0 .../halmac_8821c/halmac_8821c_pwr_seq.c | 0 .../halmac_8821c/halmac_8821c_pwr_seq.h | 0 .../halmac_8821c/halmac_api_8821c.c | 0 .../halmac_8821c/halmac_api_8821c.h | 0 .../halmac_8821c/halmac_api_8821c_pcie.c | 0 .../halmac_8821c/halmac_api_8821c_pcie.h | 0 .../halmac_8821c/halmac_api_8821c_sdio.c | 0 .../halmac_8821c/halmac_api_8821c_sdio.h | 0 .../halmac_8821c/halmac_api_8821c_usb.c | 0 .../halmac_8821c/halmac_api_8821c_usb.h | 0 .../halmac_8821c/halmac_func_8821c.c | 0 .../halmac_8821c/halmac_func_8821c.h | 0 .../halmac_8822b/RTL8822Bfw_NIC.bin | Bin .../halmac_8822b/halmac_8822b_cfg.h | 0 .../halmac_8822b/halmac_8822b_pwr_seq.c | 0 .../halmac_8822b/halmac_8822b_pwr_seq.h | 0 .../halmac_8822b/halmac_api_8822b.c | 0 .../halmac_8822b/halmac_api_8822b.h | 0 .../halmac_8822b/halmac_api_8822b_pcie.c | 0 .../halmac_8822b/halmac_api_8822b_pcie.h | 0 .../halmac_8822b/halmac_api_8822b_sdio.c | 0 .../halmac_8822b/halmac_api_8822b_sdio.h | 0 .../halmac_8822b/halmac_api_8822b_usb.c | 0 .../halmac_8822b/halmac_api_8822b_usb.h | 0 .../halmac_8822b/halmac_func_8822b.c | 0 .../halmac_8822b/halmac_func_8822b.h | 0 .../HalMac88XX/halmac_88xx/halmac_88xx_cfg.h | 0 .../HalMac88XX/halmac_88xx/halmac_api_88xx.c | 0 .../HalMac88XX/halmac_88xx/halmac_api_88xx.h | 0 .../halmac_88xx/halmac_api_88xx_pcie.c | 0 .../halmac_88xx/halmac_api_88xx_pcie.h | 0 .../halmac_88xx/halmac_api_88xx_sdio.c | 0 .../halmac_88xx/halmac_api_88xx_sdio.h | 0 .../halmac_88xx/halmac_api_88xx_usb.c | 0 .../halmac_88xx/halmac_api_88xx_usb.h | 0 .../HalMac88XX/halmac_88xx/halmac_func_88xx.c | 0 .../HalMac88XX/halmac_88xx/halmac_func_88xx.h | 0 .../rtl8192cd/WlanHAL/HalMac88XX/halmac_api.c | 0 .../rtl8192cd/WlanHAL/HalMac88XX/halmac_api.h | 0 .../WlanHAL/HalMac88XX/halmac_bit2.h | 0 .../WlanHAL/HalMac88XX/halmac_bit_8821c.h | 0 .../WlanHAL/HalMac88XX/halmac_bit_8822b.h | 0 .../WlanHAL/HalMac88XX/halmac_fw_info.h | 0 .../HalMac88XX/halmac_fw_offload_c2h_ap.h | 0 .../HalMac88XX/halmac_fw_offload_c2h_nic.h | 0 .../HalMac88XX/halmac_fw_offload_h2c_ap.h | 0 .../HalMac88XX/halmac_fw_offload_h2c_nic.h | 0 .../HalMac88XX/halmac_h2c_extra_info_ap.h | 0 .../HalMac88XX/halmac_h2c_extra_info_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_hw_cfg.h | 150 +- .../WlanHAL/HalMac88XX/halmac_hw_cfg_temp.h | 0 .../HalMac88XX/halmac_original_c2h_ap.h | 0 .../HalMac88XX/halmac_original_c2h_nic.h | 0 .../HalMac88XX/halmac_original_h2c_ap.h | 0 .../HalMac88XX/halmac_original_h2c_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_pcie_reg.h | 0 .../WlanHAL/HalMac88XX/halmac_pwr_seq_cmd.h | 0 .../WlanHAL/HalMac88XX/halmac_reg2.h | 0 .../WlanHAL/HalMac88XX/halmac_reg_8821c.h | 0 .../WlanHAL/HalMac88XX/halmac_reg_8822b.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_bd_ap.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_bd_chip.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_bd_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_desc_ap.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_desc_chip.h | 0 .../WlanHAL/HalMac88XX/halmac_rx_desc_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_sdio_reg.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_bd_ap.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_bd_chip.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_bd_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_desc_ap.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_desc_chip.h | 0 .../WlanHAL/HalMac88XX/halmac_tx_desc_nic.h | 0 .../WlanHAL/HalMac88XX/halmac_type.h | 0 .../WlanHAL/HalMac88XX/halmac_usb_reg.h | 0 .../WlanHAL/HalMac88XX/halmisc_bb_rf_bit.h | 1394 +- .../WlanHAL/HalMac88XX/halmisc_bb_rf_reg.h | 932 +- package/kernel/rtl8192cd/WlanHAL/HalMacAPI.c | 680 +- package/kernel/rtl8192cd/WlanHAL/HalMacAPI.h | 108 +- package/kernel/rtl8192cd/WlanHAL/HalMacFunc.c | 226 +- package/kernel/rtl8192cd/WlanHAL/HalMacFunc.h | 180 +- package/kernel/rtl8192cd/WlanHAL/HalPrecomp.h | 0 .../kernel/rtl8192cd/WlanHAL/HalPrecompInc.h | 0 .../rtl8192cd/WlanHAL/Include/GeneralDef.h | 0 .../rtl8192cd/WlanHAL/Include/PlatformDef.h | 0 .../rtl8192cd/WlanHAL/Include/StatusCode.h | 0 .../kernel/rtl8192cd/WlanHAL/Output/HalLib.h | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXCfg.h | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.c | 1422 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.h | 184 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXDebug.h | 130 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXDef.h | 572 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXDesc.h | 108 +- .../WlanHAL/RTL88XX/Hal88XXFirmware.c | 0 .../WlanHAL/RTL88XX/Hal88XXFirmware.h | 968 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXGen.c | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.c | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.h | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.c | 1674 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.h | 176 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.c | 10766 ++--- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.h | 734 +- .../WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.c | 0 .../WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h | 264 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXReg.h | 50 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.c | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.h | 354 +- .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.c | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.h | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.c | 0 .../rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.h | 0 .../WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h | 278 +- .../WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.c | 0 .../WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c | 38 +- .../WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h | 46 +- .../RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.c | 0 .../RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h | 402 +- .../RTL88XX/RTL8192E/RTL8192EE/Hal8192EEDef.h | 234 +- .../RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.c | 0 .../RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h | 238 +- .../WlanHAL/RTL88XX/RTL8197F/Hal8197FCfg.h | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FDef.h | 300 +- .../RTL88XX/RTL8197F/Hal8197FFirmware.c | 0 .../RTL88XX/RTL8197F/Hal8197FFirmware.h | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FGen.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.h | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FIsr.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.c | 204 +- .../WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.h | 112 +- .../RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.c | 0 .../RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.h | 392 +- .../WlanHAL/RTL88XX/RTL8197F/Hal8197FReg.h | 2 +- .../WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.h | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.h | 68 +- .../WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.c | 0 .../WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.h | 0 .../RTL88XX/RTL8197F/RTL8197FE/Hal8197FEDef.h | 82 +- .../RTL88XX/RTL8197F/RTL8197FE/Hal8197FEGen.c | 0 .../WlanHAL/RTL88XX/RTL8814A/Hal8814ADef.h | 294 +- .../RTL88XX/RTL8814A/Hal8814AFirmware.c | 0 .../RTL88XX/RTL8814A/Hal8814AFirmware.h | 88 +- .../WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.c | 0 .../WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.c | 762 +- .../WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.h | 96 +- .../RTL88XX/RTL8814A/Hal8814APwrSeqCmd.c | 0 .../RTL88XX/RTL8814A/Hal8814APwrSeqCmd.h | 352 +- .../RTL88XX/RTL8814A/RTL8814AE/Hal8814AEDef.h | 234 +- .../RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.c | 0 .../WlanHAL/RTL88XX/RTL8822B/Hal8822BDef.h | 294 +- .../RTL88XX/RTL8822B/Hal8822BFirmware.c | 0 .../RTL88XX/RTL8822B/Hal8822BFirmware.h | 88 +- .../WlanHAL/RTL88XX/RTL8822B/Hal8822BGen.c | 0 .../WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.c | 434 +- .../WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.h | 92 +- .../RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.c | 0 .../RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.h | 424 +- .../RTL88XX/RTL8822B/RTL8822BE/Hal8822BEDef.h | 224 +- .../RTL88XX/RTL8822B/RTL8822BE/Hal8822BEGen.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881ACfg.h | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881ADef.h | 270 +- .../RTL88XX/RTL8881A/Hal8881AFirmware.c | 0 .../RTL88XX/RTL8881A/Hal8881AFirmware.h | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.h | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.c | 60 +- .../WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.h | 62 +- .../RTL88XX/RTL8881A/Hal8881APwrSeqCmd.c | 0 .../RTL88XX/RTL8881A/Hal8881APwrSeqCmd.h | 268 +- .../WlanHAL/RTL88XX/RTL8881A/Hal8881AReg.h | 2 +- .../WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.h | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.h | 68 +- .../WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.c | 0 .../WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.h | 0 .../RTL88XX/RTL8881A/RTL8881AE/Hal8881AEDef.h | 38 +- package/kernel/rtl8192cd/Wlan_QoSType.h | 0 package/kernel/rtl8192cd/Wlan_TypeDef.h | 0 package/kernel/rtl8192cd/bin2c.pl | 0 .../hal/hal_btc/hal_btc_chip/hal_btc_8197f.c | 0 package/kernel/rtl8192cd/data/AGC_TAB.txt | 326 +- .../kernel/rtl8192cd/data/AGC_TAB_n_92C.txt | 326 +- .../kernel/rtl8192cd/data/AGC_TAB_n_hp.txt | 326 +- .../kernel/rtl8192cd/data/MACPHY_REG_92C.txt | 222 +- package/kernel/rtl8192cd/data/PHY_REG_1T.txt | 488 +- .../kernel/rtl8192cd/data/PHY_REG_1T_n.txt | 442 +- .../kernel/rtl8192cd/data/PHY_REG_1T_n_hp.txt | 444 +- package/kernel/rtl8192cd/data/PHY_REG_2T.txt | 542 +- .../kernel/rtl8192cd/data/PHY_REG_2T_n.txt | 438 +- .../kernel/rtl8192cd/data/PHY_REG_2T_n_hp.txt | 440 +- .../rtl8192cd/data/PHY_REG_2T_n_lna.txt | 440 +- .../rtl8192cd/data/PHY_REG_MP_n_92C.txt | 6 +- .../kernel/rtl8192cd/data/PHY_REG_PG_92C.txt | 52 +- .../kernel/rtl8192cd/data/PHY_REG_PG_hp.txt | 54 +- .../kernel/rtl8192cd/data/REG_TXPWR_TRK.txt | 80 +- .../rtl8192cd/data/REG_TXPWR_TRK_hp.txt | 80 +- .../kernel/rtl8192cd/data/TXPWR_LMT_92c.txt | 150 +- .../kernel/rtl8192cd/data/TXPWR_LMT_92c_1.txt | 150 +- .../kernel/rtl8192cd/data/TXPWR_LMT_92c_2.txt | 148 +- package/kernel/rtl8192cd/data/radio_a_1T.txt | 310 +- .../kernel/rtl8192cd/data/radio_a_1T_n.txt | 338 +- package/kernel/rtl8192cd/data/radio_a_2T.txt | 306 +- .../kernel/rtl8192cd/data/radio_a_2T_n.txt | 338 +- .../kernel/rtl8192cd/data/radio_a_2T_n_hp.txt | 314 +- .../rtl8192cd/data/radio_a_2T_n_lna.txt | 346 +- package/kernel/rtl8192cd/data/radio_b_2T.txt | 66 +- .../kernel/rtl8192cd/data/radio_b_2T_n.txt | 114 +- .../kernel/rtl8192cd/data/radio_b_2T_n_hp.txt | 94 +- .../rtl8192cd/data/radio_b_2T_n_lna.txt | 114 +- package/kernel/rtl8192cd/data/rtl8192cfwn.bin | Bin .../kernel/rtl8192cd/data/rtl8192cfwua.bin | Bin .../rtl8192cd/data_8723/PHY_REG_PG_8723.txt | 22 +- .../rtl8192cd/data_8723/TXPWR_LMT_8723.txt | 324 +- .../data_8723/TxPowerTrack_AP_8723.txt | 50 +- .../rtl8192cd/data_8812/AGC_TAB_8812.txt | 266 +- .../rtl8192cd/data_8812/AGC_TAB_8812_hp.txt | 266 +- .../data_8812/AGC_TAB_8812_n_default.txt | 270 +- .../data_8812/AGC_TAB_8812_n_extlna.txt | 270 +- .../data_8812/AGC_TAB_8812_n_extpa.txt | 270 +- .../rtl8192cd/data_8812/AGC_TAB_8812_n_hp.txt | 270 +- .../rtl8192cd/data_8812/MAC_REG_8812.txt | 196 +- .../rtl8192cd/data_8812/MAC_REG_8812_n.txt | 204 +- .../rtl8192cd/data_8812/PHY_REG_8812.txt | 482 +- .../data_8812/PHY_REG_8812_n_default.txt | 492 +- .../data_8812/PHY_REG_8812_n_extlna.txt | 492 +- .../data_8812/PHY_REG_8812_n_extpa.txt | 492 +- .../rtl8192cd/data_8812/PHY_REG_8812_n_hp.txt | 492 +- .../rtl8192cd/data_8812/PHY_REG_MP_8812.txt | 10 +- .../rtl8192cd/data_8812/PHY_REG_PG_8812.txt | 84 +- .../data_8812/PHY_REG_PG_8812_new.txt | 84 +- .../data_8812/REG_TXPWR_TRK_8812.txt | 80 +- .../data_8812/REG_TXPWR_TRK_8812_hp.txt | 80 +- .../rtl8192cd/data_8812/RadioA_8812.txt | 628 +- .../rtl8192cd/data_8812/RadioA_8812_hp.txt | 628 +- .../data_8812/RadioA_8812_n_default.txt | 556 +- .../data_8812/RadioA_8812_n_extlna.txt | 556 +- .../data_8812/RadioA_8812_n_extpa.txt | 556 +- .../rtl8192cd/data_8812/RadioA_8812_n_hp.txt | 556 +- .../data_8812/RadioA_8812_n_ultra_hp.txt | 556 +- .../rtl8192cd/data_8812/RadioB_8812.txt | 500 +- .../rtl8192cd/data_8812/RadioB_8812_hp.txt | 496 +- .../data_8812/RadioB_8812_n_default.txt | 498 +- .../data_8812/RadioB_8812_n_extlna.txt | 498 +- .../data_8812/RadioB_8812_n_extpa.txt | 498 +- .../rtl8192cd/data_8812/RadioB_8812_n_hp.txt | 498 +- .../data_8812/RadioB_8812_n_ultra_hp.txt | 498 +- .../data_8812/TXPWR_LMT_8812_new.txt | 654 +- .../kernel/rtl8192cd/data_8812/rtl8812fw.bin | Bin .../rtl8192cd/data_88e/PHY_REG_PG_88E.txt | 288 +- .../rtl8192cd/data_88e/PHY_REG_PG_88E_new.txt | 42 +- .../rtl8192cd/data_88e/TXPWR_LMT_88E_new.txt | 652 +- .../rtl8192cd/data_92d/AGC_TAB_2G_n.txt | 528 +- .../rtl8192cd/data_92d/AGC_TAB_5G_n.txt | 528 +- .../kernel/rtl8192cd/data_92d/AGC_TAB_n.txt | 528 +- .../rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt | 528 +- .../kernel/rtl8192cd/data_92d/MACPHY_REG.txt | 222 +- .../rtl8192cd/data_92d/PHY_REG_MP_n.txt | 16 +- .../kernel/rtl8192cd/data_92d/PHY_REG_PG.txt | 574 +- .../rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt | 574 +- .../rtl8192cd/data_92d/PHY_REG_PG_CE.txt | 574 +- .../rtl8192cd/data_92d/PHY_REG_PG_FCC.txt | 574 +- .../kernel/rtl8192cd/data_92d/PHY_REG_n.txt | 442 +- .../rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt | 444 +- .../data_92d/REG_TXPWR_TRK_n_92d.txt | 80 +- .../data_92d/REG_TXPWR_TRK_n_92d_hp.txt | 80 +- .../rtl8192cd/data_92d/TXPWR_LMT_92d.txt | 150 +- .../rtl8192cd/data_92d/TXPWR_LMT_92d_1.txt | 150 +- .../rtl8192cd/data_92d/TXPWR_LMT_92d_2.txt | 148 +- .../rtl8192cd/data_92d/radio_a_intPA.txt | 488 +- .../rtl8192cd/data_92d/radio_a_intPA_GM.txt | 488 +- .../data_92d/radio_a_intPA_GM_new.txt | 488 +- .../data_92d/radio_a_intPA_GM_new1.txt | 488 +- .../rtl8192cd/data_92d/radio_a_intPA_new.txt | 488 +- .../kernel/rtl8192cd/data_92d/radio_a_n.txt | 488 +- .../rtl8192cd/data_92d/radio_a_n_92d_hp.txt | 488 +- .../rtl8192cd/data_92d/radio_b_intPA.txt | 492 +- .../rtl8192cd/data_92d/radio_b_intPA_GM.txt | 492 +- .../data_92d/radio_b_intPA_GM_new.txt | 492 +- .../data_92d/radio_b_intPA_GM_new1.txt | 492 +- .../rtl8192cd/data_92d/radio_b_intPA_new.txt | 492 +- .../kernel/rtl8192cd/data_92d/radio_b_n.txt | 494 +- .../rtl8192cd/data_92d/radio_b_n_92d_hp.txt | 494 +- package/kernel/rtl8192cd/efuse_97f/common.h | 0 package/kernel/rtl8192cd/efuse_97f/efuse.c | 832 +- package/kernel/rtl8192cd/efuse_97f/efuse.h | 330 +- package/kernel/rtl8192cd/efuse_97f/rom_def.h | 0 package/kernel/rtl8192cd/efuse_97f/string.c | 0 package/kernel/rtl8192cd/efuse_97f/sys_reg.h | 0 package/kernel/rtl8192cd/ieee802_mib.h | 2262 +- .../kernel/rtl8192cd/mesh_ext/mesh_route.h | 344 +- .../kernel/rtl8192cd/mesh_ext/mesh_security.h | 56 +- package/kernel/rtl8192cd/mesh_ext/mesh_util.c | 806 +- package/kernel/rtl8192cd/odm_inc.h | 698 +- package/kernel/rtl8192cd/phydm/halhwimg.h | 246 +- package/kernel/rtl8192cd/phydm/halphyrf_ap.c | 5604 +-- package/kernel/rtl8192cd/phydm/halphyrf_ap.h | 358 +- package/kernel/rtl8192cd/phydm/halphyrf_ce.c | 1602 +- package/kernel/rtl8192cd/phydm/halphyrf_ce.h | 236 +- package/kernel/rtl8192cd/phydm/halphyrf_win.c | 1560 +- package/kernel/rtl8192cd/phydm/halphyrf_win.h | 240 +- package/kernel/rtl8192cd/phydm/mp_precomp.h | 40 +- package/kernel/rtl8192cd/phydm/phydm.c | 6694 +-- package/kernel/rtl8192cd/phydm/phydm.h | 3066 +- package/kernel/rtl8192cd/phydm/phydm_acs.c | 2452 +- package/kernel/rtl8192cd/phydm/phydm_acs.h | 210 +- .../kernel/rtl8192cd/phydm/phydm_adaptivity.h | 456 +- .../rtl8192cd/phydm/phydm_adc_sampling.c | 1528 +- .../rtl8192cd/phydm/phydm_adc_sampling.h | 296 +- .../kernel/rtl8192cd/phydm/phydm_antdect.c | 1928 +- .../kernel/rtl8192cd/phydm/phydm_antdect.h | 196 +- package/kernel/rtl8192cd/phydm/phydm_antdiv.c | 11222 ++--- package/kernel/rtl8192cd/phydm/phydm_antdiv.h | 1304 +- .../rtl8192cd/phydm/phydm_beamforming.c | 3918 +- .../rtl8192cd/phydm/phydm_beamforming.h | 766 +- package/kernel/rtl8192cd/phydm/phydm_ccx.c | 1258 +- package/kernel/rtl8192cd/phydm/phydm_ccx.h | 266 +- .../rtl8192cd/phydm/phydm_cfotracking.c | 774 +- .../rtl8192cd/phydm/phydm_cfotracking.h | 138 +- package/kernel/rtl8192cd/phydm/phydm_debug.c | 6046 +-- package/kernel/rtl8192cd/phydm/phydm_debug.h | 708 +- package/kernel/rtl8192cd/phydm/phydm_dfs.c | 146 +- package/kernel/rtl8192cd/phydm/phydm_dfs.h | 152 +- package/kernel/rtl8192cd/phydm/phydm_dig.c | 9038 ++-- package/kernel/rtl8192cd/phydm/phydm_dig.h | 1452 +- .../phydm/phydm_dynamicbbpowersaving.c | 248 +- .../phydm/phydm_dynamicbbpowersaving.h | 116 +- .../rtl8192cd/phydm/phydm_dynamictxpower.c | 1118 +- .../rtl8192cd/phydm/phydm_dynamictxpower.h | 220 +- .../rtl8192cd/phydm/phydm_edcaturbocheck.c | 1526 +- .../rtl8192cd/phydm/phydm_edcaturbocheck.h | 200 +- .../kernel/rtl8192cd/phydm/phydm_features.h | 338 +- .../kernel/rtl8192cd/phydm/phydm_hwconfig.c | 7338 +-- .../kernel/rtl8192cd/phydm/phydm_hwconfig.h | 1146 +- .../kernel/rtl8192cd/phydm/phydm_interface.c | 1916 +- .../kernel/rtl8192cd/phydm/phydm_interface.h | 852 +- package/kernel/rtl8192cd/phydm/phydm_iqk.h | 134 +- package/kernel/rtl8192cd/phydm/phydm_kfree.c | 382 +- package/kernel/rtl8192cd/phydm/phydm_kfree.h | 90 +- .../rtl8192cd/phydm/phydm_noisemonitor.c | 752 +- .../rtl8192cd/phydm/phydm_noisemonitor.h | 82 +- .../kernel/rtl8192cd/phydm/phydm_pathdiv.c | 1620 +- .../kernel/rtl8192cd/phydm/phydm_pathdiv.h | 648 +- .../rtl8192cd/phydm/phydm_powertracking_ap.c | 2508 +- .../rtl8192cd/phydm/phydm_powertracking_ap.h | 736 +- .../rtl8192cd/phydm/phydm_powertracking_ce.c | 1512 +- .../rtl8192cd/phydm/phydm_powertracking_ce.h | 668 +- .../rtl8192cd/phydm/phydm_powertracking_win.c | 1576 +- .../rtl8192cd/phydm/phydm_powertracking_win.h | 598 +- .../kernel/rtl8192cd/phydm/phydm_pre_define.h | 1306 +- .../kernel/rtl8192cd/phydm/phydm_precomp.h | 696 +- package/kernel/rtl8192cd/phydm/phydm_rainfo.c | 6822 +-- package/kernel/rtl8192cd/phydm/phydm_rainfo.h | 1168 +- package/kernel/rtl8192cd/phydm/phydm_reg.h | 430 +- .../rtl8192cd/phydm/phydm_regdefine11ac.h | 200 +- .../rtl8192cd/phydm/phydm_regdefine11n.h | 430 +- package/kernel/rtl8192cd/phydm/phydm_types.h | 522 +- package/kernel/rtl8192cd/phydm/rtchnlplan.c | 962 +- package/kernel/rtl8192cd/phydm/rtchnlplan.h | 1398 +- .../phydm/rtl8188e/hal8188erateadaptive.c | 2882 +- .../phydm/rtl8188e/hal8188erateadaptive.h | 222 +- .../rtl8192cd/phydm/rtl8188e/hal8188ereg.h | 130 +- .../phydm/rtl8188e/halhwimg8188e_bb.c | 2742 +- .../phydm/rtl8188e/halhwimg8188e_bb.h | 118 +- .../phydm/rtl8188e/halhwimg8188e_mac.c | 574 +- .../phydm/rtl8188e/halhwimg8188e_mac.h | 78 +- .../phydm/rtl8188e/halhwimg8188e_rf.c | 4298 +- .../phydm/rtl8188e/halhwimg8188e_rf.h | 258 +- .../phydm/rtl8188e/halhwimg8188e_s_fw.c | 7296 +-- .../phydm/rtl8188e/halhwimg8188e_s_fw.h | 124 +- .../phydm/rtl8188e/halhwimg8188e_t_fw.c | 7804 ++-- .../phydm/rtl8188e/halhwimg8188e_t_fw.h | 146 +- .../phydm/rtl8188e/halphyrf_8188e_ap.c | 6292 +-- .../phydm/rtl8188e/halphyrf_8188e_ap.h | 272 +- .../phydm/rtl8188e/halphyrf_8188e_ce.c | 6646 +-- .../phydm/rtl8188e/halphyrf_8188e_ce.h | 286 +- .../phydm/rtl8188e/halphyrf_8188e_win.c | 6742 +-- .../phydm/rtl8188e/halphyrf_8188e_win.h | 288 +- .../phydm/rtl8188e/phydm_regconfig8188e.c | 490 +- .../phydm/rtl8188e/phydm_regconfig8188e.h | 192 +- .../rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.c | 920 +- .../rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.h | 158 +- .../phydm/rtl8188e/version_rtl8188e.h | 20 +- .../rtl8192cd/phydm/rtl8188f/hal8188freg.h | 1726 +- .../phydm/rtl8188f/halhwimg8188f_bb.c | 1180 +- .../phydm/rtl8188f/halhwimg8188f_bb.h | 118 +- .../phydm/rtl8188f/halhwimg8188f_fw.c | 7974 ++-- .../phydm/rtl8188f/halhwimg8188f_fw.h | 124 +- .../phydm/rtl8188f/halhwimg8188f_mac.c | 576 +- .../phydm/rtl8188f/halhwimg8188f_mac.h | 78 +- .../phydm/rtl8188f/halhwimg8188f_rf.c | 2286 +- .../phydm/rtl8188f/halhwimg8188f_rf.h | 158 +- .../phydm/rtl8188f/version_rtl8188f.h | 20 +- .../rtl8192cd/phydm/rtl8192e/hal8192ereg.h | 2234 +- .../phydm/rtl8192e/halhwimg8192e_bb.c | 2846 +- .../phydm/rtl8192e/halhwimg8192e_bb.h | 118 +- .../phydm/rtl8192e/halhwimg8192e_fw.c | 14196 +++--- .../phydm/rtl8192e/halhwimg8192e_fw.h | 146 +- .../phydm/rtl8192e/halhwimg8192e_mac.c | 578 +- .../phydm/rtl8192e/halhwimg8192e_mac.h | 78 +- .../phydm/rtl8192e/halhwimg8192e_rf.c | 4480 +- .../phydm/rtl8192e/halhwimg8192e_rf.h | 218 +- .../phydm/rtl8192e/halphyrf_8192e_ap.c | 6630 +-- .../phydm/rtl8192e/halphyrf_8192e_ap.h | 292 +- .../phydm/rtl8192e/halphyrf_8192e_ce.c | 7348 +-- .../phydm/rtl8192e/halphyrf_8192e_ce.h | 292 +- .../phydm/rtl8192e/halphyrf_8192e_win.c | 7342 +-- .../phydm/rtl8192e/halphyrf_8192e_win.h | 292 +- .../phydm/rtl8192e/phydm_regconfig8192e.c | 466 +- .../phydm/rtl8192e/phydm_regconfig8192e.h | 196 +- .../rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.c | 910 +- .../rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.h | 134 +- .../phydm/rtl8192e/version_rtl8192e.h | 20 +- .../rtl8192cd/phydm/rtl8197f/Hal8197FPhyReg.h | 40 +- .../phydm/rtl8197f/halhwimg8197f_bb.c | 10840 ++--- .../phydm/rtl8197f/halhwimg8197f_bb.h | 88 +- .../phydm/rtl8197f/halhwimg8197f_mac.c | 632 +- .../phydm/rtl8197f/halhwimg8197f_mac.h | 68 +- .../phydm/rtl8197f/halhwimg8197f_rf.c | 3466 +- .../phydm/rtl8197f/halhwimg8197f_rf.h | 268 +- .../rtl8192cd/phydm/rtl8197f/halphyrf_8197f.c | 658 +- .../rtl8192cd/phydm/rtl8197f/halphyrf_8197f.h | 152 +- .../phydm/rtl8197f/phydm_hal_api8197f.c | 2360 +- .../phydm/rtl8197f/phydm_hal_api8197f.h | 230 +- .../phydm/rtl8197f/phydm_iqk_8197f.c | 8094 ++-- .../phydm/rtl8197f/phydm_iqk_8197f.h | 294 +- .../phydm/rtl8197f/phydm_regconfig8197f.c | 440 +- .../phydm/rtl8197f/phydm_regconfig8197f.h | 206 +- .../rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.c | 416 +- .../rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.h | 100 +- .../phydm/rtl8703b/halhwimg8703b_bb.c | 1666 +- .../phydm/rtl8703b/halhwimg8703b_bb.h | 118 +- .../phydm/rtl8703b/halhwimg8703b_fw.c | 7978 ++-- .../phydm/rtl8703b/halhwimg8703b_fw.h | 124 +- .../phydm/rtl8703b/halhwimg8703b_mac.c | 580 +- .../phydm/rtl8703b/halhwimg8703b_mac.h | 78 +- .../phydm/rtl8703b/halhwimg8703b_rf.c | 1994 +- .../phydm/rtl8703b/halhwimg8703b_rf.h | 158 +- .../rtl8192cd/phydm/rtl8703b/halphyrf_8703b.c | 4706 +- .../rtl8192cd/phydm/rtl8703b/halphyrf_8703b.h | 270 +- .../phydm/rtl8703b/phydm_regconfig8703b.c | 438 +- .../phydm/rtl8703b/phydm_regconfig8703b.h | 218 +- .../phydm/rtl8703b/version_rtl8703b.h | 20 +- .../rtl8192cd/phydm/rtl8723b/hal8723breg.h | 1724 +- .../phydm/rtl8723b/halhwimg8723b_bb.c | 1266 +- .../phydm/rtl8723b/halhwimg8723b_bb.h | 118 +- .../phydm/rtl8723b/halhwimg8723b_fw.c | 10538 ++--- .../phydm/rtl8723b/halhwimg8723b_fw.h | 124 +- .../phydm/rtl8723b/halhwimg8723b_mac.c | 580 +- .../phydm/rtl8723b/halhwimg8723b_mac.h | 78 +- .../phydm/rtl8723b/halhwimg8723b_mp.c | 5388 +-- .../phydm/rtl8723b/halhwimg8723b_mp.h | 90 +- .../phydm/rtl8723b/halhwimg8723b_rf.c | 1730 +- .../phydm/rtl8723b/halhwimg8723b_rf.h | 178 +- .../phydm/rtl8723b/halphyrf_8723b_ap.c | 5362 +-- .../phydm/rtl8723b/halphyrf_8723b_ap.h | 252 +- .../phydm/rtl8723b/halphyrf_8723b_ce.c | 7918 ++-- .../phydm/rtl8723b/halphyrf_8723b_ce.h | 268 +- .../phydm/rtl8723b/halphyrf_8723b_win.c | 7950 ++-- .../phydm/rtl8723b/halphyrf_8723b_win.h | 258 +- .../phydm/rtl8723b/phydm_regconfig8723b.c | 464 +- .../phydm/rtl8723b/phydm_regconfig8723b.h | 192 +- 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.../phydm/rtl8812a/halhwimg8812a_mac.h | 78 +- .../phydm/rtl8812a/halhwimg8812a_rf.c | 7618 +-- .../phydm/rtl8812a/halhwimg8812a_rf.h | 278 +- .../phydm/rtl8812a/halphyrf_8812a_ap.c | 7420 +-- .../phydm/rtl8812a/halphyrf_8812a_ap.h | 306 +- .../phydm/rtl8812a/halphyrf_8812a_ce.c | 4400 +- .../phydm/rtl8812a/halphyrf_8812a_ce.h | 212 +- .../phydm/rtl8812a/halphyrf_8812a_win.c | 5958 +-- .../phydm/rtl8812a/halphyrf_8812a_win.h | 212 +- .../phydm/rtl8812a/phydm_regconfig8812a.c | 390 +- .../phydm/rtl8812a/phydm_regconfig8812a.h | 192 +- .../rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.c | 320 +- .../rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.h | 90 +- .../phydm/rtl8812a/version_rtl8812a.h | 20 +- .../phydm/rtl8814a/hal8814areg_odm.h | 94 +- .../phydm/rtl8814a/halhwimg8814a_bb.c | 13894 +++--- .../phydm/rtl8814a/halhwimg8814a_bb.h | 328 +- .../phydm/rtl8814a/halhwimg8814a_fw.c | 15570 +++---- .../phydm/rtl8814a/halhwimg8814a_fw.h | 102 +- .../phydm/rtl8814a/halhwimg8814a_mac.c | 618 +- .../phydm/rtl8814a/halhwimg8814a_mac.h | 68 +- .../phydm/rtl8814a/halhwimg8814a_rf.c | 38808 ++++++++-------- .../phydm/rtl8814a/halhwimg8814a_rf.h | 588 +- .../phydm/rtl8814a/halphyrf_8814a_ap.c | 3508 +- .../phydm/rtl8814a/halphyrf_8814a_ap.h | 328 +- .../phydm/rtl8814a/halphyrf_8814a_ce.c | 3360 +- .../phydm/rtl8814a/halphyrf_8814a_ce.h | 304 +- .../phydm/rtl8814a/halphyrf_8814a_win.c | 3340 +- .../phydm/rtl8814a/halphyrf_8814a_win.h | 298 +- .../phydm/rtl8814a/phydm_iqk_8814a.c | 1160 +- .../phydm/rtl8814a/phydm_iqk_8814a.h | 140 +- .../phydm/rtl8814a/phydm_regconfig8814a.c | 438 +- .../phydm/rtl8814a/phydm_regconfig8814a.h | 218 +- .../rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.c | 580 +- .../rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.h | 130 +- .../phydm/rtl8821a/halhwimg8821a_bb.c | 1858 +- .../phydm/rtl8821a/halhwimg8821a_bb.h | 178 +- .../phydm/rtl8821a/halhwimg8821a_fw.c | 14014 +++--- .../phydm/rtl8821a/halhwimg8821a_fw.h | 146 +- .../phydm/rtl8821a/halhwimg8821a_mac.c | 570 +- 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package/kernel/rtl8192cd/efuse_97f/sys_reg.h mode change 100755 => 100644 package/kernel/rtl8192cd/odm_inc.h mode change 100755 => 100644 package/kernel/rtl8192cd/phydm/phydm_rainfo.c mode change 100755 => 100644 package/kernel/rtl8192cd/rtw_android.c mode change 100755 => 100644 package/kernel/rtl8192cd/rtw_android.h mode change 100755 => 100644 package/kernel/rtl8192cd/tplmt2h.pl mode change 100755 => 100644 package/kernel/rtl8192cd/typedef.h diff --git a/package/kernel/rtl8192cd/8192c_reg.h b/package/kernel/rtl8192cd/8192c_reg.h index 4d1a010665a..652d4b07ec1 100644 --- a/package/kernel/rtl8192cd/8192c_reg.h +++ b/package/kernel/rtl8192cd/8192c_reg.h @@ -1,2487 +1,2487 @@ -/* - * Header file of 8192C register - * - * $Id: 8192c_reg.h,v 1.7.2.2 2010/09/20 09:00:10 button Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _8192C_REG_H_ -#define _8192C_REG_H_ - -#ifndef WLAN_HAL_INTERNAL_USED - - -//============================================================ -// 8192C Regsiter offset definition -//============================================================ - - -// -// MAC register 0x000 - 0x6AFh -// 1. System Configure Register. (Offset 0x000 - 0x0FFh) -// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) -// General Purpose Timer. (Offset 0x150 - 0x16Fh) -// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) -// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) -// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) -// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) -// MACID Setting Register. (Offset 0x610 - 0x62Fh) -// Timing Control Register. (Offset 0x630 - 0x64Fh) -// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) -// Security Control Register. (Offset 0x670 - 0x68Fh) -// Power Save Control Register. (Offset 0x690 - 0x69Fh) -// General Purpose Register. (Offset 0x6A0 - 0x6AFh) -// - - -// -// 1. System Configure Register. (Offset 0x000 - 0x0FFh) -// -#define SYS_ISO_CTRL 0x000 // System Isolation Interface Control. -#define SYS_FUNC_EN 0x002 // System Function Enable. -#define APS_FSMCO 0x004 // Auto Power Sequence Control/Option. -#define SYS_CLKR 0x008 // System Clock. -#define CR9346 0x00A // 93C46 (93C56) Command. -#define EE_VPD 0x00C // EEPROM VPD Data. -#define AFE_MISC 0x010 // AFE Misc. -#define SPS0_CTRL 0x011 // Switching Power Supply 0 Control. -#define SPS_OCP_CFG 0x018 // SPS Over Current Protection Configuration. -#define RSV_CTRL0 0x01C // Reserved Control. -#define RF_CTRL 0x01F // RF Block Control. -#define LDOA15_CTRL 0x020 // V15 Digital LDO Control. -#define LDOV12D_CTRL 0x021 // V12 Digital LDO Control. -#define LDOHCI12_CTRL 0x022 // V12 Digital LDO Control. -#define LPLDO_CTRL 0x023 // Low Power LDO Control. -#define AFE_XTAL_CTRL 0x024 // AFE Crystal Control. -#define AFE_PLL_CTRL 0x028 // AFE_PLL_CTRL Enable. -#define RSV_CTRL1 0x02C // Reserved Control. -#define EFUSE_CTRL 0x030 // E-Fuse Control. -#define EFUSE_TEST 0x034 // E-Fuse Test Control. -#define PWR_DATA 0x038 // Power on Data. -#define CAL_TIMER 0x03C // Hardware Calibration Timer. -#define ACLK_MON 0x03E // Analog Clock Monitor. -#define GPIO_MUXCFG 0x040 // GPIO_MUX Configuration. -#define GPIO_PIN_CTRL 0x044 // GPIO[7:0] PIN Control. -#define GPIO_INTM 0x048 // GPIO Interrupt Monitor Register. -#define LEDCFG 0x04C // System PINMUX Configuration. -#define FSIMR 0x050 // Firmware System Interrupt Mask. -#define FSISR 0x054 // Firmware System Interrupt Status. -#define HSIMR 0x058 // Host System Interrupt Mask. -#define HSISR 0x05C // Host System Interrupt Status. - -#define MCUFWDL 0x080 // MCU Firmware Down Load Control. -#define MCUTSTCFG 0x084 // MCU Firmware Test Configuration. -#define MCUDMSG_I 0x088 // MCU Firmware Debug Message. -#define MCUDMSG_II 0x08C // MCU Firmware Debug Message. - -#define BIST_CTRL 0x0D0 // BIST/SCAN CONTROL -#define C_BIST_RPT 0x0D4 // BIST Report -#define BIST_ROM_RPT 0x0D8 // BIST ROM Report -#define USB_SIE_INTF 0x0E0 // USB SIE Access Interface -#define PCIE_MIO_INTF 0x0E4 // PCIE MIO Access Interface -#define PCIE_MIO_INTD 0x0E8 // PCIE MIO Access Interface DATA. -#define HPON_FSM 0x0EC // Power On FSM Monitor/Control. -#define SYS_CFG 0x0F0 // System Configuration Status - - -// -// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) -// -#define CR 0x100 // Command Register. -#define PBP 0x104 // Packet Buffer Page. -#define TRXDMA_CTRL 0x10C // TRXDMA Control. -#define TRXFF_BNDY 0x114 // TX/RX FIFO Boundary -#define TRXFF_STATUS 0x118 // PKTFF Status -#define RXFF_PTR 0x11C // RXFF Write/Read Pointer -#define HIMR 0x120 // Host Interrupt Mask. -#define HISR 0x124 // Host Interrupt Status. -#define HIMRE 0x128 // Host Interrupt Mask Extension. -#define HISRE 0x12C // Host Interrupt Status Extension. -#define CPWM 0x12F // Current Power Mode. -#define FWIMR 0x130 // Firmware WLAN Interrupt Mask. -#define FWISR 0x134 // Firmware WLAN Interrupt Status. -#define FTIMR 0x138 // Firmware Timer Interrupt Mask. -#define FTISR 0x13C // Firmware Timer Interrupt Status. -#define PKTBUF_DBG_CTRL 0x140 // TX/RX Packet Buffer Debug Control. -#define PKTBUF_DBG_DATA_L 0x144 // TX/RX Packet Buffer Debug Data. -#define PKTBUF_DBG_DATA_H 0x148 // TX/RX Packet Buffer Debug Data. -// General Purpose Timer. (Offset 0x150 - 0x16Fh) -#define TC0_CTRL 0x150 // Timer/Counter 0 Control. -#define TC1_CTRL 0x154 // Timer/Counter 1 Control. -#define TC2_CTRL 0x158 // Timer/Counter 2 Control. -#define TC3_CTRL 0x15C // Timer/Counter 3 Control. -#define TC4_CTRL 0x160 // Timer/Counter 4 Control. -#define TCUNIT_BASE 0x164 // Timer/Counter Unit Base. -// General Purpose Timer. (Offset 0x150 - 0x16Fh) -#define MBIST_START 0x174 // MACTOP BIST START Pulse. -#define MBIST_DONE 0x178 // MACTOP BIST DONE. -#define MBIST_FAIL 0x17C // MACTOP BIST FAIL. - -#define C2H_SYNC_BYTE 0x1AF // 8051 set to 0xFF, Driver set to 0x0 after read C2H content -#define MCUTST_I 0x1C0 // MCU Firmware TST-I. -#define MCUTST_II 0x1C4 // MCU Firmware TST-II. -#define MCU_UNLOCK 0x01C7 // is used for Unlock MCU infinite-loop -#define FMETHR 0x1C8 // Firmware Message Exchange to Host. -#define HMETFR 0x1CC // Host Message Interrupt to Firmware. -#define HMEBOX_0 0x1D0 // Host Message BOX_0 to Firmware. -#define HMEBOX_1 0x1D4 // Host Message BOX_1 to Firmware. -#define HMEBOX_2 0x1D8 // Host Message BOX_2 to Firmware. -#define HMEBOX_3 0x1DC // Host Message BOX_3 to Firmware. -#define LLT_INI 0x1E0 // LLT Entries Initial Indirect Access Control. -#define BB_ACCEESS_CTRL 0x1E8 // BB Indirect Access Control. -#define BB_ACCESS_DATA 0x1EC // BaseBand Indirect Access Data. -#define MREG_HCIDBG 0x1F0 // MAC REG for HCI debug. -#define MREG_CPUDBG 0x1F4 // MAC REG for CPU debug. - - -// -// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) -// -#define RQPN 0x200 // Reserved Queue Page Number. -#define FIFOPAGE 0x204 // Available FIFO Page Number. -#define TDECTRL 0x208 // Tx DMA Engine Control. -#define TXDMA_OFFSET_CHK 0x20C // TXDMA Offset Check. -#define TXDMA_STATUS 0x210 // TXDMA Status. -#define RQPN_NPQ 0x214 // RQPN for Normal Queue Register - -#define RXDMA_AGG_PG_TH 0x280 // RXDMA AGG PG Threshold. -#define RXPKT_NUM 0x284 // RX Packet Number. -#define RXDMA_STATUS 0x288 // RXDMA Status. - - -// -// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) -// -#define PCIE_CTRL_REG 0x300 // PCIE DMA Control. -#define INT_MIG 0x304 // Interrupt Migration. -#define BCNQ_DESA 0x308 // TX Beacon Descriptor Address. -#define HQ_DESA 0x310 // TX High Queue Descriptor. -#define MGQ_DESA 0x318 // TX Manage Queue Descriptor Address. -#define VOQ_DESA 0x320 // TX VO Queue Descriptor Address. -#define VIQ_DESA 0x328 // TX VI Queue Descriptor Address. -#define BEQ_DESA 0x330 // TX BE Queue Descriptor Address. -#define BKQ_DESA 0x338 // TX BK Queue Descriptor Address. -#define RX_DESA 0x340 // RX Queue Descriptor Address. -#define DBI 0x348 // Backdoor REG for Access Configuration SPACE. -#define MDIO 0x354 // MDIO for Access PCIE PHY. -#define DBG_SEL 0x360 // Debug Selection -#define UART_CTRL 0x364 // UART Control. -#define UART_TX_DESA 0x370 // UART TX Descriptor Address. -#define UART_RX_DESA 0x378 // UART RX Descriptor Address. - - -// -// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) -// -#define VOQ_INFO 0x400 // -#define VIQ_INFO 0x404 // -#define BEQ_INFO 0x408 // -#define BKQ_INFO 0x40C // -#define MGQ_INFO 0x410 // -#define HIQ_INFO 0x414 // -#define BCNQ_INFO 0x418 // -#define TXPKT_EMPTY 0x41B // TXPKTBUF Packet Empty. -#define CPU_MGQ_INFO 0x41C // TXPKTBUF Packet Empty. -#define FWHW_TXQ_CTRL 0x420 // FWHW TX Queue Control. -#define HWSEQ_CTRL 0x423 // HW Sequence Number Control. -#define TXPKTBUF_BCNQ_BDNY 0x424 // BCNQ Boundary. -#define TXPKTBUF_MGQ_BDNY 0x425 // MGQ Boundary. -#define MULTI_BCNQ_EN 0x426 // -#define MULTI_BCNQ_OFFSET 0x427 // -#define SPEC_SIFS_A 0x428 // -#define RL 0x42A // -#define DARFRC 0x430 // Data Auto Rate Fallback Retry Count. -#define RARFRC 0x438 // Response Auto Rate Fallback Retry Count. -#define RRSR 0x440 // Response Rate Set. -#define ARFR0 0x444 // Data Auto Rate Fallback 0. -#define ARFR1 0x448 // Auto Rate Fallback 1. -#define ARFR2 0x44C // Auto Rate Fallback 2. -#define ARFR3 0x450 // Auto Rate Fallback 3. -#define AGGLEN_LMT 0x458 // Aggregation Length. -#define AMPDU_MIN_SPACE 0x45C // AMPDU Min Space. -#define TXPKTBUF_WMAC_LBK_BF_HD 0x45D // LBK Buffer Head Page -#define FAST_EDCA_CTRL 0x460 // Fast EDCA Mode. -#define RD_RESP_PKT_TH 0x463 // RD Responder Packet Threshold. -#define INIRTS_RATE_SEL 0x480 // Initial RTS Rate SEL. -#define INIDATA_RATE_SEL 0x484 // Initial Data Rate SEL. -#define POWER_STATUS 0x4A4 // POWER STATUS. -#define POWER_STAGE1 0x4B4 // POWER STAGE1. -#define POWER_STAGE2 0x4B8 // POWER STAGE2.---------------??? -#define PKT_LIFE_TIME 0x4C0 // PKT LIFT TIME. -#define STBC_SETTING 0x4C4 // STBC. -#define PROT_MODE_CTRL 0x4C8 // PROTECT MODE Control. -#define BAR_MODE_CTRL 0x4CC // BAR MODE Control. -#define RA_TRY_RATE_AGG_LMT 0x4CF // Rate Adaptive Try Rate Aggregation Limit. -#define NQOS_SEQ 0x4DC // Non-QoS SEQ Number. -#define QOS_SEQ 0x4DE // QoS SEQ Number. -#define NEED_CPU_HANDLE 0x4E0 // Need CPU Handle. -#define PTCL_ERR_STATUS 0x4E1 // Protocol Function Error Status. -#define PKT_LOSE_RPT 0x4E2 // PKT Lose Report. -#define Dummy 0x4FC // Dummy. - -#define EDCA_VO_PARA 0x500 // EDCA Parameter. -#define EDCA_VI_PARA 0x504 // EDCA Parameter. -#define EDCA_BE_PARA 0x508 // EDCA Parameter. -#define EDCA_BK_PARA 0x50C // EDCA Parameter. -#define BCNTCFG 0x510 // Beacon Time Configuration. -#define PIFS 0x512 // PIFS. -#define RDG_PIFS 0x513 // RDG PIFS. -#define SIFS_CCK 0x514 // SIFS for CCK. -#define SIFS_OFDM 0x516 // SIFS for OFDM. -#define AGGR_BK_TIME 0x51A // AGGR BREAK TIME. -#define SLOT_TIME 0x51B // Slot Time. -#define TX_PTCL_CTRL 0x520 // TX Protocol Control. -#define TXPAUSE 0x522 // Transmission Pause. -#define DIS_TXREQ_CLR 0x523 // Disable TX Request Clear Function. -#define RD_CTRL 0x524 // RD Control. -#define REG_MBSSID_CTRL 0x526 // MBSSID Control. - -#define TBTT_PROHIBIT 0x540 // TBTT Prohibit. -#define RD_NAV_NXT 0x544 // RD NAV Protect Next Time. -#define NAV_PROT_LEN 0x546 // NAV Protection Length. -#define BCN_CTRL 0x550 // Bcnq Control. -#define BCN_CTRL1 0x551 -#define USTIME_TSF 0x551 // US Time Tuning for TSF. -#define MBID_NUM 0x552 // MBSSID Beacon Number. -#define DUAL_TSF_RST 0x553 -#define MBSSID_BCN_SPACE 0x554 // MBSSID Beacon Space. -#define DRVERLYINT 0x558 // Beacon Driver Early Interrupt. -#define BCNDMATIM 0x559 // BCN DMA and ATIM INT Time.-----------------??? -#define ATIMWND 0x55A // ATIM Window Time. -#define BCN_MAX_ERR 0x55D // BCN MAX ERROR. -#define RXTSF_OFFSET_CCK 0x55E // CCK BCN OFFSET. -#define RXTSF_OFFSET_OFDM 0x55F // OFDM BCN OFFSET. -#define TSFTR 0x560 // TSF Timer. -#define INIT_TSFTR 0x564 // TSF Timer Initial Value. -#define TSFTR1 0x568 // TSF Timer1. -#define PSTIMER 0x580 // PS TIMER and Timeout INT. -#define TIMER0 0x584 // TIMER0 INT. -#define TIMER1 0x588 // TIMER1 INT. -#define ACMHWCTRL 0x5C0 // ACM HW Control. -#define ACMRSTCTRL 0x5C1 // ACM RST. -#define ACMAVG 0x5C2 // ACM Average. -#define VO_ADMTIME 0x5C4 // VO Admission Time. -#define VI_ADMTIME 0x5C6 // VI Admission Time. -#define BE_ADMTIME 0x5C8 // BE Admission Time. -#define EDCA_RANDOM_GEN 0x5CC // EDCA Random Number Generator. -#define C_SCH_TXCMD 0x5D0 // TX_CMD. -#define NOA_PARAM 0x5E0 // P2P NoA Parameter - - -// -// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) -// -#define APSD_CTRL 0x600 // APSD Control. -#define BWOPMODE 0x603 // BW Operation Mode. -#define TCR 0x604 // Transmission Configuration. -#define RCR 0x608 // Receive Configuration. -#define RX_PKT_LIMIT 0x60C // RX Packet Length Limit. -#define RX_DLK_TIME 0x60D // RX Deadlock Time. -#define RX_DRVINFO_SZ 0x60F // RX Driver INFO Size Register. -// MACID Setting Register. (Offset 0x610 - 0x62Fh) -#define MACID 0x610 // MAC ID. -#define BSSIDR 0x618 // BSSID. -#define MAR 0x620 // Multicast Address. -#define MBIDCAMCFG 0x628 // MBSSID CAM Configuration. -// MACID Setting Register. (Offset 0x610 - 0x62Fh) - -// Timing Control Register. (Offset 0x630 - 0x64Fh) -#define USTIME_EDCA 0x638 // US Time Tuning for EDCA. -#define SPEC_SIFS_B 0x63A // Specification SIFS. -#define RESP_SIFS_CCK 0x63C // Response SIFS for CCK. -#define RESP_SIFS_OFDM 0x63E // Response SIFS for OFDM. -#define ACKTO 0x640 // ACK Timeout. -#define CTS2TO 0x641 // CTS2 Timeout. -#define EIFS 0x642 // EIFS. -// Timing Control Register. (Offset 0x630 - 0x64Fh) - -// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) -#define NAV_CTRL 0x650 // NAV Control. -#define BACAMCMD 0x654 // Block ACK CAM Command. -#define BACAMCONTENT 0x658 // Block ACK CAM Content. -#define LBDLY 0x660 // Loopback Delay. -#define FWDLY 0x661 // FW Delay. -#define RXERR_RPT 0x664 // RX Error Report. -#define WMAC_TRXPTCL_CTL 0x668 // WMAC TX/RX Protocol Control. -// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) - -// Security Control Register. (Offset 0x670 - 0x68Fh) -#define CAMCMD 0x670 // CAM Command. -#define CAMWRITE 0x674 // CAM Write. -#define CAMREAD 0x678 // CAM Read. -#define CAMDBG 0x67C // CAM Debug. -#define SECCFG 0x680 // Security Configuration. -// Security Control Register. (Offset 0x670 - 0x68Fh) - -// Power Save Control Register. (Offset 0x690 - 0x69Fh) -#define WOW_CTRL 0x690 // Wake On WLAN Control. -#define PSSTATUS 0x691 // Power Save Status. -#define PS_RX_INFO 0x692 // Power Save RX Information. -#define LPNAV_CTRL 0x694 // Low Power NAV Control. -#define WKFMCAM_CMD 0x698 // Wakeup Frame CAM Command. -#define WKFMCAM_RWD 0x69C // Wakeup Frame Read/Write Data. -// Power Save Control Register. (Offset 0x690 - 0x69Fh) - -// General Purpose Register. (Offset 0x6A0 - 0x6AFh) -#define RXFLTMAP0 0x6A0 // RX Filter Map Group 0. -#define RXFLTMAP1 0x6A2 // RX Filter Map Group 1. -#define RXFLTMAP2 0x6A4 // RX Filter Map Group 2. -#define BCN_PSR_RPT 0x6A8 // Beacon Parser Report. -#define CALB32K_CTRL 0x6AC // Calibration 32K Control. -// General Purpose Register. (Offset 0x6A0 - 0x6AFh) -#define PKT_MON_CTRL 0x6B4 // Packet Monitor Control. -#define BT_COEX_TABLE 0x6C0 // BT-Coexistence Control. -#define WMAC_RESP_TXINFO 0x6D8 // Response TXINFO. - -#define MACID1 0x700 // MAC ID1 Register (Offset 0700h~0705h) -#define BSSIDR1 0x708 - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_VID 0xFE60 -#define REG_USB_PID 0xFE62 -#define REG_USB_OPTIONAL 0xFE64 -#define REG_USB_CHIRP_K 0xFE65 -#define REG_USB_PHY 0xFE66 -#define REG_USB_MAC_ADDR 0xFE70 - -#define REG_USB_HRPWM 0xFE58 -#define REG_USB_HCPWM 0xFE57 - -// For test chip -#define REG_TEST_USB_TXQS 0xFE48 -#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 -#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 -#define REG_TEST_SIE_OPTIONAL 0xFE64 -#define REG_TEST_SIE_CHIRP_K 0xFE65 -#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B -#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 -#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 - - -// For normal chip -#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 -#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 -#define REG_NORMAL_SIE_OPTIONAL 0xFE64 -#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 -#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B -#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C -#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. -#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 -#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF - - - -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ - - -// -// 1. System Configure Register. (Offset 0x000 - 0x0FFh) -// -//---------------------------------------------------------------------------- -// 8192C SYS_ISO_CTRL bits (Offset 0x0, 16bit) -//---------------------------------------------------------------------------- -#define PWC_EV12V BIT(15) // Power Cut for eFuse 1.2V, 1: Power valid; 0: Power invalid. -#define PWC_EV25V BIT(14) // Power Cut for eFuse 2.5V, 1: force PSW open; 0: PSW turn on by efuse ctrl. -#define ISO_DIOR BIT(9) // RF Digital I/O to Power On, 1: isolation; 0: attach. -#define ISO_EB2CORE BIT(8) // eFuse cell output to Power On, 1: isolation; 0: attach. -#define ISO_DIOE BIT(7) // Extra Digital I/O to Power On, 1: isolation; 0: attach. -#define ISO_DIOP BIT(6) // PCIe Digital I/O to Power On, 1: isolation; 0: attach. -#define ISO_IP2MAC BIT(5) // Analog Ips to Digital 1.2V, 1: isolation; 0: attach (no used). -#define ISO_PD2CORE BIT(4) // PCIe Digital 1.2V to Power On/Core 1.2V, 1: isolation; 0: attach. -#define ISO_PA2PCIE BIT(3) // PCIe Analog 1.2V to PCIe 3.3V and Digital 1.2V, 1: isolation; 0: attach. -#define ISO_UD2CORE BIT(2) // USB Digital 1.2V to Power On/Core 1.2V, 1: isolation; 0: attach. -#define ISO_UA2USB BIT(1) // USB Analog 1.2V to USB 3.3V and Digital 1.2V, 1: isolation; 0: attach. -#define ISO_MD2PP BIT(0) // MACTOP/BB/PCIe Digital to Power On, 1: isolation; 0: attach. - -//---------------------------------------------------------------------------- -// 8192C SYS_FUNC_EN bits (Offset 0x2, 16bit) -//---------------------------------------------------------------------------- -#define FEN_MREGEN BIT(15) // MAC I/O Registers Enable. -#define FEN_HWPDN BIT(14) // 0 : force All analog blocks shutdown, 1 : keep Analog Blocks alive. -#define FEN_DIO_RF BIT(13) // Enable RF Digital I/O. -#define FEN_ELDR BIT(12) // Enable EEPROM Loader (Loader POR). -#define FEN_DCORE BIT(11) // enable Core Digital (MACTOP POR). -#define FEN_CPUEN BIT(10) // Enable MCU Core (CPU RST). -#define FEN_DIOE BIT(9) // Extra Debug I/O PAD Enable. -#define FEN_PCIED BIT(8) // enable PCIe eMAC. -#define FEN_PPLL BIT(7) // Enable PCIe PHY_PLL (no used). -#define FEN_PCIEA BIT(6) // Enable PCIe PHY. -#define FEN_DIO_PCIE BIT(5) // Enable PCIe Digital I/O (no used). -#define FEN_USBD BIT(4) // Enable USB_SIE. -#define FEN_UPLL BIT(3) // Enable USB PHY_PLL (no used). -#define FEN_USBA BIT(2) // Enable USB PHY. -#define FEN_BB_GLB_RST BIT(1) // When this bit is set to "0", whole BB is reset. When this bit is set, BB is enabled. -#define FEN_BBRSTB BIT(0) // When this bit is set to "0", CCK and OFDM are disabled, - // and clock are gated. Otherwise, CCK and OFDM are enabled. - -//---------------------------------------------------------------------------- -// 8192C APS_FSMCO bits (Offset 0x4, 32bit) -//---------------------------------------------------------------------------- -#define XOP_BTCK BIT(31) // BT Option for never turn off XTAL & SPS. -#define SOP_A8M BIT(30) // Suspend option not to turn analog Clock Mode to 500K Hz, 1: keep 8M, 0: 500K. -#define SOP_RCK BIT(29) // Suspend option not to turn off Hreg Clock (8M/500KHz), 1: clock on, 0: clock off. -#define SOP_AMB BIT(28) // Suspend option not to turn off AFE MB, 1: MB on, 0: MB off. -#define SOP_ABG BIT(27) // Suspend option not to turn off AFE BG, 1: BG on, 0: BG off. -#define SOP_FUSE BIT(26) // Suspend option to turn off Efuse Power or reset Loader, 1: Fuse Pwr Off, 0: Fuse Pwr On. -#define SOP_MRST BIT(25) // Suspend option not to turn off MAC Reset, 1: MAC not reset, 0: MaC reset. -#define SOP_CRST BIT(24) // Susoend option not to turn off 8051 clock, 1: 8051 clock on, 0:8051 clock off. -#define ROP_SPS BIT(22) // Resume option to skip turn On SPS. -#define ROP_PWR BIT(21) // Resume option to skip wait Power Ready, 1: pwr up no delay, 0: wait pwr stable. -#define ROP_ALD BIT(20) // Resume option to skip autoload, 1: not autoload, 0: autoload. -#define OP_SWRST BIT(19) // Option for Software Reset to Reset 8051. -#define SUS_HOST BIT(17) // Power FSM turn to HOST SUS. -#define RDY_MACON BIT(16) // Power FSM turn all power, clock ready for MAC. -#define APDM_HPDN BIT(15) // Auto Power Down to CHIP-off State (Power-Down). -#define APDM_HOST BIT(14) // Auto Power Down to HOST-off State (Card-Disable). -#define APDM_MAC BIT(13) // Auto Power Down to WLAN-Off State (Radio-off). -#define AFSM_PCIE BIT(12) // When this bit is set, PCIE suspends via HW FSM control flow. -#define AFSM_HSUS BIT(11) // 1: Host Suspend through FSM operation; 0: Host Suspend by gated. -#define APFM_RSM BIT(10) // Auto Power On State Machine Resume, auto clear when EE load done. -#define APFM_OFF BIT(9) // Auto FSM to Turn Off, include clock, isolation, power control. -#define APFM_ONMAC BIT(8) // Auto FSM to Turn On, include clock, isolation, power control for MAC only. -#define BT_SUSEN BIT(7) // Enable BT suspend control. -#define RDY_MACDIS BIT(6) // Disable MAC power Ready Output for Test Mode. -#define PDN_PL BIT(5) // PDn polarity control, 0: Low active, 1: High active. -#define PDN_EN BIT(4) // Enable GPIO-11 as Hardware PowerDown/Resume Source. -#define PFM_WOWL BIT(3) // Wake On Lan indicator for H/W FSM. -#define PFM_LDKP BIT(2) // Loader Initial data when re-enable loader. -#define PFM_ALDN BIT(1) // HCI Region load done, inform HCI block. -#define PFM_LDALL BIT(0) // EEPROM autoload 0x00~60h Enable. - -//---------------------------------------------------------------------------- -// 8192C SYS_CLKR bits (Offset 0x8, 16bit) -//---------------------------------------------------------------------------- -#define RING_CLK_EN BIT(13) // HPON Ring Clock Enable, 1: Enable; 0 : Disable. -#define SYS_CLK_EN BIT(12) // MCU Clock Enable, 1: Enable; 0 : Disable. -#define MAC_CLK_EN BIT(11) // MAC Clock Enable, 1: Enable, 0 : Disable. -#define SEC_CLK_EN BIT(10) // SEC Clock Enable, 1 :Enable, 0 :Disable. -#define PHY_SSC_RSTB BIT(9) // PHY SSC Enable (0: Disable, 1: Enable). -#define CLKR_80M_SSC_EN_HOLD_PHS0 BIT(8) // 80M Clock Hold phase 0. -#define CLKR_80M_SSC_DIS BIT(7) // 80M Clock SSC Disable. -#define LOADER_CLK_EN BIT(5) // Loader (eFuse/EEPROM) Clock Enable. -#define MACSLP BIT(4) // MAC SLEEP. -#define ROMD16V_EN BIT(2) // Analog Clock source Divide 16 Mode for EEPROM. -#define ANA8M BIT(1) // Analog Clock source rate, 1: 8M Hz, 0: 500K Hz. -#define CNTD16V_EN BIT(0) // Analog Clock source Divide 16 Mode for Hardware Timer. - -//---------------------------------------------------------------------------- -// 8192C CR9346 bits (Offset 0xA, 16bit) -//---------------------------------------------------------------------------- -#define VPDIDX_SHIFT 8 // VPD mode, EEPROM Index. -#define VPDIDX_Mask 0x0FF -#define EEM1_0_SHIFT 6 // Operating Mode. -#define EEM1_0_Mask 0x03 -#define EEPROM_EN BIT(5) // EEPROM/Efuse is found when set to 1. -#define EERPOMSEL BIT(4) // System EEPROM select (power on selected by GPIO-0). -#define EECS BIT(3) // reflect the state of the EECS. -#define EESK BIT(2) // reflect the state of the EESK. -#define EEDI BIT(1) // reflect the state of the EEDI. -#define EEDO BIT(0) // reflect the state of the EEDO. - - -#ifdef EN_EFUSE -#define CmdEEPROM_En BIT(5) // EEPROM enable when set 1 -#define CmdEERPOMSEL BIT(4) // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 -#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) -#define AutoLoadEFUSE CmdEEPROM_En - - -#ifdef CONFIG_RTL_92C_SUPPORT - -#ifdef CONFIG_PCI_HCI -#define EEPROM_VID 0x0A // SE Vendor ID.A-B -#define EEPROM_DID 0x0C // SE Device ID. C-D -#define EEPROM_SVID 0x0E // SE Vendor ID.E-F -#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11 -#endif -#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power base -#define EEPROM_TxPowerHT40_1S 0x60 // HT40 Tx Power base -#define EEPROM_TxPowerHT40_2SDiff 0x66 // HT40 Tx Power diff -#define EEPROM_TxPowerHT20Diff 0x69 // HT20 Tx Power diff -#define EEPROM_TxPowerOFDMDiff 0x6C // OFDM Tx Power diff -#define EEPROM_MACADDRESS 0x16 - -#define EEPROM_CHANNEL_PLAN 0x75 -#define EEPROM_TSSI_A 0x76 -#define EEPROM_TSSI_B 0x77 -#define EEPROM_THERMAL_METER 0x78 //[4:0] -#define EEPROM_RF_OPT1 0x79 -#define EEPROM_RF_OPT2 0x7A -#define EEPROM_RF_OPT3 0x7B -#define EEPROM_RF_OPT4 0x7C -#define EEPROM_VERSION 0x7E -#define EEPROM_CUSTOMER_ID 0x7F - -#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] - -#ifdef CONFIG_USB_HCI - -#define EEPROM_VID 0x0A -#define EEPROM_PID 0x0C -#define EEPROM_SUBCUSTOMER_ID 0x59 - -//should be renamed and moved to another file -typedef enum _BOARD_TYPE_8192CUSB{ - BOARD_USB_DONGLE = 0, // USB dongle - BOARD_USB_High_PA = 1, // USB dongle with high power PA - BOARD_MINICARD = 2, // Minicard - BOARD_USB_SOLO = 3, // USB solo-Slim module - BOARD_USB_COMBO = 4, // USB Combo-Slim module -} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB; - -#endif // CONFIG_USB_HCI -#endif // CONFIG_RTL_92C_SUPPORT - -#ifdef CONFIG_USB_HCI -#define BOARD_TYPE_NORMAL_MASK 0xE0 - -#define EEPROM_Default_PID 0x1234 -#define EEPROM_Default_VID 0x5678 -#define EEPROM_Default_CustomerID 0xAB -#define EEPROM_Default_SubCustomerID 0xCD -#endif // CONFIG_USB_HCI - -#endif // EN_EFUSE - - -//---------------------------------------------------------------------------- -// 8192S AFE_MISC bits (Offset 0x10, 8bits) -//---------------------------------------------------------------------------- -#define MAC_ID_EN BIT(7) // Reserved for RF_ID selection to be MAC. -#define AFE_MBEN BIT(1) // Enable AFE Macro Block's Mbias. -#define AFE_BGEN BIT(0) // Enable AFE Macro Block's Bandgap. - -//---------------------------------------------------------------------------- -// 8192C SPS0_CTRL bits (Offset 0x11-17, 56bits) -//---------------------------------------------------------------------------- -#define SW18_LDO_R BIT(19) // LDO_R_L1 = 1 => LDO resistor connect. -#define SW18_V15ADJ_SHIFT 16 // v15adj_L1<2:0> output. -#define SW18_V15ADJ_Mask 0x07 -#define SW18_VOL_SHIFT 12 // VOL_L1<3:0> output. -#define SW18_VOL_Mask 0x0F -#define SW18_IN_SHIFT 9 // IN_L1<2:0> output. -#define SW18_IN_Mask 0x07 -#define SW18_TBOX_SHIFT 7 // TBOC_L1<1:0> output. -#define SW18_TBOX_Mask 0x03 -#define SW18_SET_DELAY BIT(6) // SET_DELAY_L1=1=> nonoverlap delay increases. -#define SW18_SEL BIT(5) // SD_L1 = 1 => turn off quickly. -#define SW18_STD_SHIFT 3 // STD_L1<1:0> time. -#define SW18_STD_Mask 0x03 -#define SW18_SD BIT(2) // SD_L1 = 1 => turn off quickly. -#define SW18_AREN BIT(1) // 3.3->1.8 for PFM Anti-ring. -#define SW18_R3_B1 BIT(0) // - -#define SW18_R3_B0 BIT(31) // -#define SW18_R2_SHIFT 29 // -#define SW18_R2_Mask 0x03 -#define SW18_R1_SHIFT 27 // -#define SW18_R1_Mask 0x03 -#define SW18_C3_SHIFT 25 // -#define SW18_C3_Mask 0x03 -#define SW18_C2_SHIFT 23 // -#define SW18_C2_Mask 0x03 -#define SW18_C1_SHIFT 21 // -#define SW18_C1_Mask 0x03 -#define SW18_SCREF_SHIFT 19 // For FDUAL, tune reference frequency. -#define SW18_SCREF_Mask 0x03 -#define SW18_SCPFM_SHIFT 17 // For FDUAL, tune pfm frequency. -#define SW18_SCPFM_Mask 0x03 -#define SW18_PWFMTUNE_SHIFT 14 // -#define SW18_PWFMTUNE_Mask 0x07 -#define SW18_SELSTOP BIT(13) // SEL_STOP_L1 = 0 => no delay. -#define SW18_SELD_SHIFT 11 // Bit(1)=1 enable clamp maximum duty, bit(0)=1 enable clamp minimum duty -#define SW18_SELD_Mask 0x03 -#define SW18_POWOCP BIT(10) // POWOCP_L1=1=> enable over current protection. -#define SW18_OCP_SHIFT 7 // -#define SW18_OCP_Mask 0x07 -#define SW18_SFREQ_SHIFT 5 // -#define SW18_SFREQ_Mask 0x03 -#define SW18_SFREQC BIT(4) // -#define SW18_FPWM BIT(3) // FPWM_L1 = 1 => force PWM, FPWM_L1 = 0 => force PFM. -#define SW18_FDUAL BIT(2) // FDUAL_L1 =1 => PWM or PFM. -#define SW18_SWEN BIT(1) // Enable VSPS18_SW Macro Block. -#define SW18_LDEN BIT(0) // Enable VSPS18_LDO Macro Block. - -//---------------------------------------------------------------------------- -// 8192C SPS_OCP_CFG bits (Offset 0x18-1B, 32bits) -//---------------------------------------------------------------------------- -#define SPS18_OCP_DIS BIT(31) // sps18 ocp, 0:enable, 1:disable. -#define SPS18_OCP_TH_SHIFT 16 // Sps18 ocp threshold. -#define SPS18_OCP_TH_Mask 0x07FFF -#define OCP_WINDOW_SHIFT 0 // Ocp monitor window width configure, count on ana_clk/16. -#define OCP_WINDOW_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C RSV_CTRL0 bits (Offset 0x1C-1E, 24bits) -//---------------------------------------------------------------------------- -#define HREG_DBG_SHIFT 8 // HREG Access Debug. -#define HREG_DBG_Mask 0x0FFFF -#define LOCK_ALL_EN BIT(7) // 1:Enable 'Locked All' setting by Hardware, 0: Hardware Enable 'Locked All' denied. -#define R_DIS_PRST_1 BIT(6) // Control if PERST can reset MACCORE. -#define R_DIS_PRST_0 BIT(5) // Control if PERST can reset MACCORE. -#define WLOCK_40 BIT(4) // 1:Register Write Locked, 0: Register Accessible by SW/FW. -#define WLOCK_08 BIT(3) // 1:Register Write Locked, 0: Register Accessible by SW/FW. -#define WLOCK_04 BIT(2) // 1:Register Write Locked, 0: Register Accessible by SW/FW. -#define WLOCK_00 BIT(1) // 1:Register Write Locked, 0: Register Accessible by SW/FW. -#define WLOCK_ALL BIT(0) // 1:Register Write Locked, 0: Register Accessible by SW/FW. - -//---------------------------------------------------------------------------- -// 8192C RF_CTRL bits (Offset 0x1F, 8bits) -//---------------------------------------------------------------------------- -#define RF_SDMRSTB BIT(2) // Reset RF SDM Module (low active). -#define RF_RSTB BIT(1) // Reset RF Module (low active). -#define RF_EN BIT(0) // Enable RF Module. - -//---------------------------------------------------------------------------- -// 8192C LDOA15_CTRL bits (Offset 0x20, 8bits) -//---------------------------------------------------------------------------- -#define LDA15_VOADJ_SHIFT 4 // -#define LDA15_VOADJ_Mask 0x0F -#define LDA15_STBY BIT(3) // LDOA15 Standby Mode. -#define LDA15_OBUF BIT(2) // LDOA15 Output Buffered. -#define REG_VOS BIT(1) // LDOA15 Add Offset voltage. -#define LDA15_EN BIT(0) // Enable LDOA15 Macro Block. - -//---------------------------------------------------------------------------- -// 8192C LDOV12D_CTRL bits (Offset 0x21, 8bits) -//---------------------------------------------------------------------------- -#define LDV12_VADJ_SHIFT 4 // LDOVD12 voltage adjust. -#define LDV12_VADJ_Mask 0x0F -#define LDV12_BUFO BIT(2) // LDOVD12 buffer output Mode. -#define LDV12_SDBY BIT(1) // LDOVD12 standby mode. -#define LDV12_EN BIT(0) // Enable LDOA12 Macro Block. - -//---------------------------------------------------------------------------- -// 8192C LDOHCI12_CTRL bits (Offset 0x22, 8bits) -//---------------------------------------------------------------------------- -#define LDH12_SDBY BIT(5) // LDOHCI12 standby mode. -#define LDH12_OBUF BIT(4) // Enable LDOHCI12 Macro Block. -#define LDH12_VADJ_SHIFT 1 // LDOHCI12 voltage adjust. -#define LDH12_VADJ_Mask 0x07 -#define LDH12_EN BIT(0) // Enable LDOHCI12 Macro Block. - -//---------------------------------------------------------------------------- -// 8192C LPLDO_CTRL bits (Offset 0x23, 8bits) -//---------------------------------------------------------------------------- -#define LPLDH12_SLP BIT(4) // LPLDOH12 Sleep Mode. -#define LPLDH12_VADJ_SHIFT 0 // LPLDOH12 voltage adjust. -#define LPLDH12_VADJ_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C AFE_XTAL_CTRL bits (Offset 0x24-27, 32bits) -//---------------------------------------------------------------------------- -#define CKDLY_BT BIT(29) // Delay time of CLK_BT relate to CLK_DIG, 0: long time, 1: short time. -#define CKDLY_DIG BIT(28) // Delay time of CLK_DIG relate to CLK_AFE, 0: long time, 1: short time. -#define CKDLY_USB BIT(27) // Delay time of CLK_USB relate to CLK_AFE, 0: long time, 1: short time. -#define CKDLY_AFE BIT(26) // Delay time of CLK_AFE relate to CLK_RF, 0: long time, 1: short time. -#define XTAL_GPIO_SHIFT 23 // -#define XTAL_GPIO_Mask 0x07 -#define XTAL_BT_DRV_SHIFT 21 // BT clock source Driving current: 11:most current, 00: less current. -#define XTAL_BT_DRV_Mask 0x03 -#define XTAL_BT_GATE BIT(20) // Gated control: 1: BT Clock source gated, 0: clock enable (auto setting by trap data). -#define XTAL_DIG_DRV_SHIFT 18 // DIG clock source 11:most current, 00: less current. -#define XTAL_DIG_DRV_Mask 0x03 -#define XTAL_GATE_DIG BIT(17) // Gated control:1: DIG Clock source gated, 0: clock enable. -#define XTAL_RF_DRV_SHIFT 15 // RF PLL Driving current: 11:most current, 00: less current. -#define XTAL_RF_DRV_Mask 0x03 -#define XTAL_RF_GATE BIT(14) // Gated control: 1: RF Clock source gated, 0: clock enable. -#define XTAL_AFE_DRV_SHIFT 12 // AFE PLL Driving current: 11:most current, 00: less current. -#define XTAL_AFE_DRV_Mask 0x03 -#define XTAL_GATE_AFE BIT(11) // Gated control:1: USB Clock source gated, 0: clock enable. -#define XTAL_USB_DRV_SHIFT 9 // USB PLL Driving current: 11:most current, 00: less current. -#define XTAL_USB_DRV_Mask 0x03 -#define XTAL_GATE_USB BIT(8) // Gated control:1: USB Clock source gated, 0: clock enable. -#define XTAL_CADJ_XI_SHIFT 4 // 1:add cap, 0:degrade cap. -#define XTAL_CADJ_XI_Mask 0x0F -#define XTAL_BOSC_SHIFT 2 // The bias current control of VCO block. -#define XTAL_BOSC_Mask 0x03 -#define XTAL_BSEL BIT(1) // 1: schmitt trigger, 0:nand. -#define XTAL_EN BIT(0) // Enable XTAL Macro block. - -//---------------------------------------------------------------------------- -// 8192C AFE_PLL_CTRL bits (Offset 0x28-2B, 32bits) -//---------------------------------------------------------------------------- -#define AFE_DUMMY_SHIFT 25 // Dummy Registers. -#define AFE_DUMMY_Mask 0x07 -#define APLL_1MEN BIT(24) // 1:Enable 0:output "1". -#define APLL_40DRV_SHIFT 22 // clk diving 00: weak 11:strong. -#define APLL_40DRV_Mask 0x03 -#define APLL_PLLDRV_SHIFT 20 // clk diving 00: weak 11:strong. -#define APLL_PLLDRV_Mask 0x03 -#define APLL_88DRV_SHIFT 18 // clk diving 00: weak 11:strong. -#define APLL_88DRV_Mask 0x03 -#define APLL_80DRV_SHIFT 16 // clk diving 00: weak 11:strong. -#define APLL_80DRV_Mask 0x03 -#define APLL_80EN BIT(15) // 1:Enable 0:output "1". -#define APLL_320EN BIT(14) // 1:Enable 0:output "1". -#define APLL_320BIAS_SHIFT 11 // pll320 CP current selection. -#define APLL_320BIAS_Mask 0x07 -#define APLL_BIAS_SHIFT 8 // pll CP current selection. -#define APLL_BIAS_Mask 0x07 -#define APLL_KVCO_SHIFT 6 // pll VCO KVCO selection. -#define APLL_KVCO_Mask 0x03 -#define APLL_LPFEN BIT(5) // enable PLL Bias Current LPF. -#define APLL_WDOGB BIT(4) // enable watch dog 0: enable 1:disable. -#define APLL_EDGE_SEL BIT(3) // Reference clock: 1 : negative edge, 0 : positive edge. -#define APLL_FREF_SEL BIT(2) // Reference clock: 1 : 20MHz, 0 : 40MHz. -#define APLL_320_EN BIT(1) // Enable AFE 320 PLL Macro Block. -#define APLL_EN BIT(0) // Enable AFE PLL Macro Block. - -//---------------------------------------------------------------------------- -// 8192C EFUSE_CTRL bits (Offset 0x30-33, 32bits) -//---------------------------------------------------------------------------- -#define EF_FLAG BIT(31) // Access Flag. Write "1" for Program; Write "0" for Read Access. -#define EF_PGPD_SHIFT 28 // E-fuse program time. -#define EF_PGPD_Mask 0x07 -#define EF_RDT_SHIFT 24 // E-fuse read time: in the unit of cycle time. -#define EF_RDT_Mask 0x0F -#define EF_PGT_SHIFT 20 // Programming setup time. In the unit of cycle time.(125ns). -#define EF_PGT_Mask 0x0F -#define EF_PD BIT(19) // Efuse power down. -#define ALD_EN BIT(18) // Autoload Enable. -#define EF_ADDR_SHIFT 8 // Access Address. -#define EF_ADDR_Mask 0x03FF -#define EF_DATA_SHIFT 0 // Access Data. -#define EF_DATA_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C EFUSE_TEST bits (Offset 0x34-37, 32bits) -//---------------------------------------------------------------------------- -#define LDOE25_EN BIT(31) // Enable LDOE25 Macro Block. -#define LDOE25_VADJ_SHIFT 28 // LDOE25 voltage adjust. -#define LDOE25_VADJ_Mask 0x07 -#define ADDR_END_Shift 25 // 92D_REG, Scan effuse end (1023-addr_end) -#define ADDR_END_Mask 0x07 -#define ADDR_STR_Shift 18 // 92D_REG, Scan efuse from (addr_str*8) -#define ADDR_STR_Mask 0x07F -#define BYTE_CNT_EN BIT(17) // 92D_REG, 1: scan efuse in byte; 0: scan efuse in bit -#define EF_SCAN_EN BIT(16) // 92D_REG, 1: efuse in scan process. 0: not in scan process -#define EDATA1_SHIFT 8 // EEPROM offset 1 data (EE Byte-1). -#define EDATA1_Mask 0x0FF -#define EF_TRPT BIT(7) // Test Scan Report: 1 : Fail, 0 : OK. -#define EF_TTHD_SHIFT 0 // Bit number for all cells scan test. -#define EF_TTHD_Mask 0x07F - -//---------------------------------------------------------------------------- -// 8192C PWR_DATA bits (Offset 0x38-3B, 32bits) -//---------------------------------------------------------------------------- -#define EDATA0_SHIFT 24 // EEPROM offset 0 data (EE Byte-0). -#define EDATA0_Mask 0x0FF -#define HTEST_SEL_SHIFT 16 // TEST Mode Select (EE Byte-7). -#define HTEST_SEL_Mask 0x0FF -#define HPON_STBP2_SHIFT 8 // HPON Stable time parameter (EE Byte-5). -#define HPON_STBP2_Mask 0x0FF -#define HPON_STBP1_SHIFT 0 // HPON Stable time parameter (EE Byte-2). -#define HPON_STBP1_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C CAL_TIMER bits (Offset 0x3C-3D, 16bits) -//---------------------------------------------------------------------------- -#define MATCH_CNT_SHIFT 8 // match counter for sleep mode. -#define MATCH_CNT_Mask 0x0FF -#define CAL_SCAL_SHIFT 0 // scaler fine tune for sleep mode (tune in Time unit). -#define CAL_SCAL_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C ACLK_MON bits (Offset 0x3E-3F, 16bits) -//---------------------------------------------------------------------------- -#define RCLK_MON_SHIFT 5 // ring clock monitor (with DPSTU scale). -#define RCLK_MON_Mask 0x07FF -#define CAL_TIMER_EN BIT(4) // calibration timer enable. This shall be turned off before sleep mode enable. -#define DPSTU_SHIFT 2 // Deep Power Save Time Unit: 00: 64us, 01: 128us, 10: 192us, 11: 256 us. -#define DPSTU_Mask 0x03 -#define SUS_16X BIT(1) // Scale timer 16x when suspend mode, (~250 S). -#define RSM_EN BIT(0) // When Timer Expired, Resume Hardware StateMachine. - -//---------------------------------------------------------------------------- -// 8192C GPIO_MUXCFG bits (Offset 0x40-43, 32 bits) -//---------------------------------------------------------------------------- -#define GPIO_MOD_H_SHIFT 28 // When bit is zero, corresponding port configured to data port; - // otherwise, when a bit is set, and GPIO_IO_SEL is set to "0", - // then it is interrupt mode.. -#define GPIO_MOD_H_Mask 0x0F -#define GPIO_IO_SEL_H_SHIFT 24 // GPIO_IO_SEL[11:8], output when bit=1;input when bit=0. -#define GPIO_IO_SEL_H_Mask 0x0F -#define GPIO_OUT_H_SHIFT 20 // GPIO_OUT[11:8], GPIO pins output value. -#define GPIO_OUT_H_Mask 0x0F -#define GPIO_IN_H_SHIFT 16 // GPIO_IN[11:8], GPIO pins input value. -#define GPIO_IN_H_Mask 0x0F -#define SIC_LBK BIT(15) // Enable SIC_Loop_Back Mode, (auto set by ICFG). -#define HTP_EN BIT(14) // 0 : Enable as Host Debug Port, 1 : Enable as Host Test Port. -#define SIC_23 BIT(13) // Enable SIC at 0: GPIO 9,10 pins ; 1 : GPIO 2,3 pins. -#define SIC_EN BIT(12) // Enable GPIO Pins as SIC, (auto set by ICFG). -#define SIC_SWRST BIT(11) // 0 : Reset SIC by SW, prevent SIC Dead Lock. -#define PMAC_EN BIT(10) // PMAC Enable (auto set by ICFG). -#define UART_SEL BIT(9) // Enable UART at 0: GPIO 6,7 pins; 1 : GPIO 9,10 pins. -#define UART_EN BIT(8) // Enable GPIO Pins as UART. -#define BTMode_SHIFT 6 // Bluetooth Mode. -#define BTMode_Mask 0x03 -#define BT_EN BIT(5) // Enable GPIO0,1,2,3,8 Pins for Bluetooth. -#define EROM_EN BIT(4) // Enable GPIO6 for EEDO, GPIO7 for EEDI, default Enable when 9346 selected -#define TRSW1EN BIT(3) // Enable GPIO9,10 for TRSWN1, TRSWP1. -#define TRSW0EN BIT(2) // Enable GPIO8 for TRSWN0. -#define GPIOSEL_SHIFT 0 // GPIO Select. -#define GPIOSEL_Mask 0x03 - -//---------------------------------------------------------------------------- -// 8192C GPIO_PIN_CTRL bits (Offset 0x44-47, 32 bits) -//---------------------------------------------------------------------------- -#define GPIO_MOD_L_SHIFT 24 // When bit is 0, corresponding port set as data port; - // otherwise, when a bit=1, and GPIO_IO_SEL is set to "0", - // then it is interrupt mode.. -#define GPIO_MOD_L_Mask 0x0FF -#define GPIO_IO_SEL_L_SHIFT 16 // GPIO_IO_SEL[7:0], output when bit=1;input when bit=0. -#define GPIO_IO_SEL_L_Mask 0x0FF -#define GPIO_OUT_L_SHIFT 8 // GPIO_OUT[7:0], GPIO pins output value. -#define GPIO_OUT_L_Mask 0x0FF -#define GPIO_IN_L_SHIFT 0 // GPIO_IN[7:0], GPIO pins input value. -#define GPIO_IN_L_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C GPIO_INTM bits (Offset 0x48-4B, 32 bits) -//---------------------------------------------------------------------------- -#define MDBG_SEL_SHIFT 30 // -#define MDBG_SEL_Mask 0x03 -#define GPIO_EXT_WOL_SHIFT 12 // External WOL source control. -#define GPIO_EXT_WOL_Mask 0x0F -#define GPIOB_INT_MD BIT(11) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIOA_INT_MD BIT(10) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO9_INT_MD BIT(9) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO8_INT_MD BIT(8) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO7_INT_MD BIT(7) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO6_INT_MD BIT(6) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO5_INT_MD BIT(5) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO4_INT_MD BIT(4) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO3_INT_MD BIT(3) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO2_INT_MD BIT(2) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO1_INT_MD BIT(1) // 0=positive edge, 1=negative edge, is sensed as interrupt. -#define GPIO0_INT_MD BIT(0) // 0=positive edge, 1=negative edge, is sensed as interrupt. - -//---------------------------------------------------------------------------- -// 8192C LEDCFG bits (Offset 0x4C-4F, 32 bits) -//---------------------------------------------------------------------------- -#define GP8_LED BIT(22) // Enable GPIO-8 as LED2. -#define LED2EN BIT(21) // Enable GPIO-10/GPIO-8 as LED2. -#define LED2PL BIT(20) // LED2 polarity control. -#define LED2SV BIT(19) // LED2 software value. -#define LED2CM_SHIFT 16 // LED2 Control Mode. -#define LED2CM_Mask 0x07 -#define LED1DIS BIT(15) // LED1 Disabled for analog signal usage, - // 1: disable (input mode), 0:Enable (output mode). -#define LED1PL BIT(12) // LED1 polarity control (auto-load configurable). -#define LED1SV BIT(11) // LED1 software value. -#define LED1CM_SHIFT 8 // LED1 Control Mode. -#define LED1CM_Mask 0x07 -#define LED0DIS BIT(7) // LED1 Disabled for analog signal usage, - // 1: disable (input mode), 0:Enable (output mode). -#define LED0PL BIT(4) // LED0 polarity control (auto-load configurable). -#define LED0SV BIT(3) // LED0 software value. -#define LED0CM_SHIFT 0 // LED0 Control Mode. -#define LED0CM_Mask 0x07 - -#define LED_SW_CTRL 0 -#define LED_OFF 1 -#define LED_TX_RX_EVENT_ON 2 -#define LED_TX_RX_EVENT_OFF 3 -#define LED_TX_EVENT_ON 4 -#define LED_TX_EVENT_OFF 5 -#define LED_RX_EVENT_ON 6 -#define LED_RX_EVENT_OFF 7 - -//---------------------------------------------------------------------------- -// 8192C FSIMR bits (Offset 0x50-53, 32 bits) -//---------------------------------------------------------------------------- -#define PDNINT_EN BIT(31) // Enable Hardware Power Down interrupt source. -#define SYS_TIMER_EN BIT(30) // Enable Hardware System Timer interrupt source. -#define SPS_OCP_INT_EN BIT(29) // Enable SPS OCP alarm interrupt source. -#define HPON_WRE_EN BIT(28) // Enable Continue access HPON registers interrupt source. -#define GPIOB_INT_EN BIT(23) // Enable GPIOB interrupt source. -#define GPIOA_INT_EN BIT(22) // Enable GPIOA interrupt source. -#define GPIO9_INT_EN BIT(21) // Enable GPIO9 interrupt source. -#define GPIO8_INT_EN BIT(20) // Enable GPIO8 interrupt source. -#define GPIO7_INT_EN BIT(19) // Enable GPIO7 interrupt source. -#define GPIO6_INT_EN BIT(18) // Enable GPIO6 interrupt source. -#define GPIO5_INT_EN BIT(17) // Enable GPIO5 interrupt source. -#define GPIO4_INT_EN BIT(16) // Enable GPIO4 interrupt source. -#define GPIO3_INT_EN BIT(15) // Enable GPIO3 interrupt source. -#define GPIO2_INT_EN BIT(14) // Enable GPIO2 interrupt source. -#define GPIO1_INT_EN BIT(13) // Enable GPIO1 interrupt source. -#define GPIO0_INT_EN BIT(12) // Enable GPIO0 interrupt source. - -//---------------------------------------------------------------------------- -// 8192C FSISR bits (Offset 0x54-57, 32 bits) -//---------------------------------------------------------------------------- -#define PDNINT BIT(31) // Hardware Power Down interrupt. -#define HWSYS_TIMER_INT BIT(30) // Hardware System Timer interrupt. -#define SPS_OCP_INT BIT(29) // SPS OCP alarm interrupt. -#define HPON_WRE BIT(28) // Continue access HPON registers interrupt. Write 1 clear. -#define GPIOB_INT BIT(23) // GPIOB INT Status. Write 1 clear. -#define GPIOA_INT BIT(22) // GPIOA INT Status. Write 1 clear. -#define GPIO9_INT BIT(21) // GPIO9 INT Status. Write 1 clear. -#define GPIO8_INT BIT(20) // GPIO8 INT Status. Write 1 clear. -#define GPIO7_INT BIT(19) // GPIO7 INT Status. Write 1 clear. -#define GPIO6_INT BIT(18) // GPIO6 INT Status. Write 1 clear. -#define GPIO5_INT BIT(17) // GPIO5 INT Status. Write 1 clear. -#define GPIO4_INT BIT(16) // GPIO4 INT Status. Write 1 clear. -#define GPIO3_INT BIT(15) // GPIO3 INT Status. Write 1 clear. -#define GPIO2_INT BIT(14) // GPIO2 INT Status. Write 1 clear. -#define GPIO1_INT BIT(13) // GPIO1 INT Status. Write 1 clear. -#define GPIO0_INT BIT(12) // GPIO0 INT Status. Write 1 clear. - -//---------------------------------------------------------------------------- -// 8192C MCUFWDL bits (Offset 0x80-83, 32 bits) -//---------------------------------------------------------------------------- -#define RPWM_SHIFT 24 // Host Request Power State. -#define RPWM_Mask 0x0FF -#define CPRST BIT(23) // 8051 Reset Status. -#define ROM_DLEN BIT(19) // ROM Download Enable (8051 Core will be reseted) FPGA only. -#define ROM_PGE_SHIFT 16 // ROM Page (FPGA only). -#define ROM_PGE_Mask 0x07 -#define MAC1_RFINI_RDY BIT(10) // 92D_REG, MAC1 MCU Initial RF ready -#define MAC1_BBINI_RDY BIT(9) // 92D_REG, MAC1 MCU Initial BB ready -#define MAC1_MACINI_RDY BIT(8) // 92D_REG, MAC1 MCU Initial MAC ready -#define MCU_STATUS BIT(7) // 92D_REG, 1: SRAM, 0: ROM -#define WINTINI_RDY BIT(6) // WLAN Interrupt Initial ready. -#define MAC0_RFINI_RDY BIT(5) // MAC0 MCU Initial RF ready. -#define MAC0_BBINI_RDY BIT(4) // MAC0 MCU Initial BB ready. -#define MAC0_MACINI_RDY BIT(3) // MAC0 MCU Initial MAC ready. -#define FWDL_CHKSUM_RPT BIT(2) // FWDL CheckSum report, 1: OK, 0 : Faill. -#define MCUFWDL_RDY BIT(1) // Driver set this bit to notify MCU FW Download OK. -#define MCUFWDL_EN BIT(0) // MCU Firmware download enable. 1:Enable, 0:Disable. - -//---------------------------------------------------------------------------- -// 8192C MCUTSTCFG bits (Offset 0x84-87, 32 bits) -//---------------------------------------------------------------------------- -#define LBKTST_SHIFT 0 // LBK TST indicator. -#define LBKTST_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C BIST_CTRL bits (Offset 0xD0-D3, 32 bits) -//---------------------------------------------------------------------------- -#define BB_SPEED_SCAN BIT(31) // BB at speed scan mode Enable. -#define SCAN_PLL_BYPASS BIT(30) // 92D_REG -#define MBIST_RSTNI_Shift 8 // 92D_REG -#define MBIST_RSTNI_Mask 0x07FF -#define BIST_RESUME_PS BIT(5) -#define BIST_RESUME BIT(4) -#define BIST_DRF BIT(3) // 92D_REG -#define BIST_RETEN BIT(3) -#define BIST_NORMAL BIT(2) -#define BIST_RSTN BIT(1) -#define BIST_CLK_EN BIT(0) - -//---------------------------------------------------------------------------- -// 8192C C_BIST_RPT bits (Offset 0xD4-D7, 32 bits) -//---------------------------------------------------------------------------- -#define C_MAC_BIST_FAIL BIT(31) // MAC_BIST_FAIL. -#define C_USB_IRAM_FAIL BIT(26) // USB IRAM BIST FAIL. -#define C_USB_RAM1_FAIL BIT(25) // USB RAM1 BIST FAIL. -#define C_USB_PROM_FAIL BIT(24) // USB PROM BIST FAIL. -#define C_PCIE_RETRY_BIST_FAIL BIT(20) // PCIE RETRY RAM BIST FAIL. -#define C_PCIE_SOT_BIST_FAIL BIT(19) // PCIE RETRY SOT RAM BIST FAIL. -#define C_PCIE_PH1_BIST_FAIL BIT(18) // PCIE PHDR RAM1 BIST FAIL. -#define C_PCIE_PH0_BIST_FAIL BIT(17) // PCIE PHDR RAM0 BIST FAIL. -#define C_PCIE_PD_BIST_FAIL BIT(16) // PCIE PDATA RAM BIST FAIL. -#define C_MAC_BIST_RDY BIT(10) // MAC MBIST Test report Ready. -#define C_USB_BIST_RDY BIT(9) // USB MBIST Test report Ready. -#define C_PCIE_BIST_RDY BIT(8) // PCIE MBIST Test report Ready. -#define C_MAC_BIST_START BIT(2) // MAC MBIST START PULSE. -#define C_USB_BIST_START BIT(1) // USB MBIST START PULSE. -#define C_PCIE_BIST_START BIT(0) // PCIE MBIST START PULSE. - -//---------------------------------------------------------------------------- -// 8192C USB_SIE_INTF bits (Offset 0xE0-E3, 32 bits) -//---------------------------------------------------------------------------- -#define USB_SIE_INTF_WE BIT(25) // Write Enable of SIE interface. -#define USB_SIE_INTF_BYIOREG BIT(24) // SIE Bypass IOREG interface. -#define USB_SIE_INTF_ADDR_SHIFT 16 // The address of SIE register. -#define USB_SIE_INTF_ADDR_Mask 0x0FF -#define USB_SIE_INTF_RD_SHIFT 8 // The read data from USB SIE. -#define USB_SIE_INTF_RD_Mask 0x0FF -#define USB_SIE_INTF_WD_SHIFT 0 // The write data to USB SIE. -#define USB_SIE_INTF_WD_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C PCIE_MIO_INTF bits (Offset 0xE4-E7, 32 bits) -//---------------------------------------------------------------------------- -#define PCIE_MIO_BYIOREG BIT(13) // MIO bypass IOREG interface. -#define PCIE_MIO_RE BIT(12) // Read Enable of MIO interface. -#define PCIE_MIO_WE_SHIFT 8 // Write Byte Enable of MIO interface. -#define PCIE_MIO_WE_Mask 0x0F -#define PCIE_MIO_ADDR_SHIFT 0 // The address of PCIE MIO Access register. -#define PCIE_MIO_ADDR_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C HPON_FSM bits (Offset 0xEC-EF, 32 bits) -//---------------------------------------------------------------------------- -#define EVENT_FSM_SHIFT 16 // The State Machine Trigger Events. -#define EVENT_FSM_Mask 0x0FFFF -#define PMC_ADDR_SHIFT 8 // The Hardware Access HPON Register Addr. -#define PMC_ADDR_Mask 0x0FF -#define PMC_WR BIT(7) // The Hardware Access HPON Register Write Pulse. -#define PMC_DATA BIT(6) // The Hardware Access HPON Register Data. -#define FSM_STATE_SHIFT 0 // The State Machine Data. -#define FSM_STATE_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C SYS_CFG bits (Offset 0xF0-F3, 32 bits) -//---------------------------------------------------------------------------- -#define TRP_ICFG_SHIFT 28 // Trapped ICFG data value. -#define TRP_ICFG_Mask 0x0F -#define TYPE_ID BIT(27) // 1: 8191C/8192C ; 0: 8188C. -#define BD_HCI_SEL BIT(26) // Trapped HCI_SEL value. -#define BD_PKG_SEL BIT(25) // Trapped PKG_ENG_SEL value. -#define TRP_BT_EN BIT(24) // Trapped BT Chip Valid need XTAL & SPS resource. -#define TRP_VAUX_EN BIT(23) // Trapped VAUX_EN. -#define PAD_HWPD_IDN BIT(22) // HWPDN PAD status Indicator. -#define PSC_TESTCFG_SHIFT 20 // Test Pin configuration. -#define PSC_TESTCFG_Mask 0x03 -#define CHIP_VER_RL_SHIFT 16 // Chip version (RL6111). -#define CHIP_VER_RL_Mask 0x0F -#define CHIP_VER_RTL_SHIFT 12 // Test Chip version - 8188C (RLE0307) / 8191C (RLE0308). -#define CHIP_VER_RTL_Mask 0x0F -#define IC_MACPHY_MODE BIT(11) // 0: IC Normal Mode, 1: force IC PHY_ASIC Mode. -#define BD_MAC1 BIT(10) // Bonding option for MAC function-1 Enable. -#define BD_MAC2 BIT(9) // Bonding option for MAC function-2 Enable. -#define SIC_IDLE BIT(8) // Indicator of SIC idle state. -#define TRP_B15V_EN BIT(7) // Trapped option for 1.5V of board. -#define OCP_SHUTDN BIT(6) // SPS OCP shutdown Chip. -#define V15_VLD BIT(5) // 1.5V Power Ready, 1: Power Ready. -#define PCIRSTB BIT(4) // PCIE External PERST, Pin Status. -#define PCLK_VLD BIT(3) // PCIE PHY Clock Stable, 1: Clock Stable. -#define UCLK_VLD BIT(2) // USB PHY Clock Stable, 1: Clock Stable. -#define ACLK_VLD BIT(1) // AFE Clock Stable, 1: Clock Stable. -#define XCLK_VLD BIT(0) // Xtal Clock Stable, 1: Clock Stable. - - -// -// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) -// -//---------------------------------------------------------------------------- -// 8192C CR bits (Offset 0x100-103, 32 bits) -//---------------------------------------------------------------------------- -#define LBMODE_SHIFT 24 // Loopback mode. -#define LBMODE_Mask 0x0F -#define NETYPE_SHIFT 16 // Network Type. -#define NETYPE_SHIFT1 18 -#define NETYPE_Mask 0x03 -#define CALTMR_EN BIT(10) // for 8723 & 88E only -#define MAC_SEC_EN BIT(9) // Enable MAC security engine. -#define ENSWBCN BIT(8) // Enable SW TX beacon. -#define MACRXEN BIT(7) // MAC Receiver Enable. -#define MACTXEN BIT(6) // MAC Transmitter Enable. -#define SCHEDULE_EN BIT(5) // Schedule Enable. -#define PROTOCOL_EN BIT(4) // protocol Block Function Enable. -#define RXDMA_EN BIT(3) // RXDMA Function Enable. -#define TXDMA_EN BIT(2) // TXDMA Function Enable. -#define HCI_RXDMA_EN BIT(1) // HCI to RXDMA Interface Enable. -#define HCI_TXDMA_EN BIT(0) // HCI to TXDMA Interface Enable. -// Loopback mode. -#define LB_NORMAL 0x00 -#define LB_MAC 0x0B -#define LB_MAC_DLY 0x03 -#define LB_PHY 0x01 -#define LB_DMA 0x07 -#define LB_DUAL_MAC 0x1B // 92D_REG -// Network Type. -#define NETYPE_NOLINK 0x00 -#define NETYPE_ADHOC 0x01 -#define NETYPE_INFRA 0x02 -#define NETYPE_AP 0x03 - -//---------------------------------------------------------------------------- -// 8192C PBP bits (Offset 0x104-107, 32 bits) -//---------------------------------------------------------------------------- -#define PSTX_SHIFT 4 // Page size of transmit packet buffer. -#define PSTX_Mask 0x0F -#define PSRX_SHIFT 0 // Page size of receive packet buffer and C2HCMD buffer. -#define PSRX_Mask 0x0F -// Page size -#define PBP_64B 0x00 -#define PBP_128B 0x01 -#define PBP_256B 0x02 -#define PBP_512B 0x03 -#define PBP_1024B 0x04 - -//---------------------------------------------------------------------------- -// 8192C TRXDMA_CTRL bits (Offset 0x10C-10D, 16 bits) -//---------------------------------------------------------------------------- -#define HPQ_SEL_SHIFT 8 // High Priority Queue Selection. -#define HPQ_SEL_Mask 0x03F -#define RXDMA_AGG_EN BIT(2) // -#define RXSHFT_EN BIT(1) // When this bit is set, RX shift to fit alignment is enable. -#define RXDMA_ARBBW_EN BIT(0) // Enable RXDMA Arbitrator priority for Host interface. -// High Priority Queue Selection. -#define HPQ_SEL_VOQ BIT(0) -#define HPQ_SEL_VIQ BIT(1) -#define HPQ_SEL_BEQ BIT(2) -#define HPQ_SEL_BKQ BIT(3) -#define HPQ_SEL_MGQ BIT(4) -#define HPQ_SEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - -//---------------------------------------------------------------------------- -// 8192C TRXFF_BNDY bits (Offset 0x114-117, 32 bits) -//---------------------------------------------------------------------------- -#define RXFF0_BNDY_SHIFT 16 // upper boundary of RXFF0. -#define RXFF0_BNDY_Mask 0x0FFFF -#define TXPKTBUF_PGBNDY_SHIFT 0 // From FWHW offload, sets the max pages controlled by TXDMA. -#define TXPKTBUF_PGBNDY_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C TRXFF_STATUS bits (Offset 0x118-11B, 32 bits) -//---------------------------------------------------------------------------- -#define TXPKTFF_FULL BIT(16) // TXDMA block the current TX pkt due to TXPKTBUF full, status bit will be set. -#define RXFF1_OVF BIT(1) // When this bit is "1", RXFF1 is under overflow condition. -#define RXFF0_OVF BIT(0) // When this bit is "1", RXFF0 is under overflow condition. - -//---------------------------------------------------------------------------- -// 8192C RXFF_PTR bits (Offset 0x11C-11F, 32 bits) -//---------------------------------------------------------------------------- -#define RXFF0_RDPTR_SHIFT 16 // The read pointer address of RXFF0. -#define RXFF0_RDPTR_Mask 0x0FFFF -#define RXFF0_WTPTR_SHIFT 0 // The write pointer address of RXFF0. -#define RXFF0_WTPTR_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C HIMR bits (Offset 0x120-123, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C HISR bits (Offset 0x124-127, 32 bits) -//---------------------------------------------------------------------------- -#define HIMR_BCNDMA7 BIT(31) // Beacon DMA Interrupt 7. -#define HIMR_BCNDMA6 BIT(30) // Beacon DMA Interrupt 6. -#define HIMR_BCNDMA5 BIT(29) // Beacon DMA Interrupt 5. -#define HIMR_BCNDMA4 BIT(28) // Beacon DMA Interrupt 4. -#define HIMR_BCNDMA3 BIT(27) // Beacon DMA Interrupt 3. -#define HIMR_BCNDMA2 BIT(26) // Beacon DMA Interrupt 2. -#define HIMR_BCNDMA1 BIT(25) // Beacon DMA Interrupt 1. -#define HIMR_BCNDOK7 BIT(24) // Beacon Queue DMA OK Interrupt7. -#define HIMR_BCNDOK6 BIT(23) // Beacon Queue DMA OK Interrupt6. -#define HIMR_BCNDOK5 BIT(22) // Beacon Queue DMA OK Interrupt5. -#define HIMR_BCNDOK4 BIT(21) // Beacon Queue DMA OK Interrupt4. -#define HIMR_BCNDOK3 BIT(20) // Beacon Queue DMA OK Interrupt3. -#define HIMR_BCNDOK2 BIT(19) // Beacon Queue DMA OK Interrupt2. -#define HIMR_BCNDOK1 BIT(18) // Beacon Queue DMA OK Interrupt1. -#define HIMR_TIMEOUT2 BIT(17) // Time Out Interrupt 2. -#define HIMR_TIMEOUT1 BIT(16) // Time Out Interrupt 1. -#define HIMR_TXFOVW BIT(15) // Transmit packet buffer Overflow. -#define HIMR_PSTIMEOUT BIT(14) // Power Save Time Out Interrupt. -#define HIMR_BCNDMA0 BIT(13) // Beacon DMA Interrupt 0. -#define HIMR_RXFOVW BIT(12) // Receive packet buffer Overflow. -#define HIMR_RDU BIT(11) // Receive Descriptor Unavailable. -#define HIMR_ATIM_END BIT(10) // ATIM Window End Interrupt. -#define HIMR_BCNDOK0 BIT(9) // Beacon Queue DMA OK Interrupt0. -#define HIMR_HIGHDOK BIT(8) // High Queue DMA OK Interrupt. -#define HIMR_TXBCNOK BIT(7) // Transmit Beacon OK Interrupt. -#define HIMR_MGTDOK BIT(6) // Management Queue DMA OK Interrupt. -#define HIMR_TXBCNERR BIT(5) // Transmit Beacon Error Interrupt. -#define HIMR_BKDOK BIT(4) // AC_BK DMA OK Interrupt. -#define HIMR_BEDOK BIT(3) // AC_BE DMA OK Interrupt. -#define HIMR_VIDOK BIT(2) // AC_VI DMA OK Interrupt. -#define HIMR_VODOK BIT(1) // AC_VO DMA Interrupt. -#define HIMR_ROK BIT(0) // Receive DMA OK Interrupt. - -//---------------------------------------------------------------------------- -// 8192C HIMRE bits (Offset 0x128-12A, 24 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C HISRE bits (Offset 0x12C-12E, 24 bits) -//---------------------------------------------------------------------------- -#define HIMRE_TXERR BIT(11) // Enable Tx Error Flag Interrupt. -#define HIMRE_RXERR BIT(10) // Enable Rx Error Flag Interrupt. -#define HIMRE_C2HCMD BIT(9) // Enable CPU to Host Command Interrupt. -#define HIMRE_CPWM BIT(8) // Enable CPU power Mode exchange Interrupt. -#define HIMRE_HBT_CMD BIT(7) // 92D_REG, Host BT_CMD interrupt mask -#define HIMRE_OCPINT BIT(1) // Enable SPS_OCP Interrupt. -#define HIMRE_WLANOFF BIT(0) // Enable WLAN power down Interrupt. - -//---------------------------------------------------------------------------- -// 8192C CPWM bits (Offset 0x12F, 8 bits) -//---------------------------------------------------------------------------- -#define CPWM_TOGGLING BIT(7) // When this bit is toggled, interrtup is send to HISRE.CPWMINT. -#define CPWM_MOD_SHIFT 0 // The current power mode index. -#define CPWM_MOD_Mask 0x07F - -//---------------------------------------------------------------------------- -// 8192C FWIMR bits (Offset 0x130-133, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C FWISR bits (Offset 0x134-137, 32 bits) -//---------------------------------------------------------------------------- -#define FWIMR_VOQ BIT(31) // -#define FWIMR_VIQ BIT(30) // -#define FWIMR_BEQ BIT(29) // -#define FWIMR_BKQ BIT(28) // -#define FWIMR_MGTQ BIT(27) // -#define FWIMR_HIQ BIT(26) // -#define FWIMR_TXPKTIN BIT(25) // interrupt is issued to inform MCU. -#define FWIMR_TXBCNOK BIT(24) // interrupt is issued when a beacon frame is transmitted. -#define FWIMR_TXBCNERR BIT(23) // interrupt is issued when beacon in TXPKTBUF fails to send out. -#define FWIMR_RX_UMD0 BIT(22) // receiving unicast data frame with More Data=0. -#define FWIMR_RX_UMD1 BIT(21) // receiving unicast data frame with More Data=1. -#define FWIMR_RX_BMD0 BIT(20) // receiving broadcast data frame with More Data=0. -#define FWIMR_RX_BMD1 BIT(19) // receiving broadcast data frame with More Data=1. -#define FWIMR_BCN_RX BIT(18) // When receiving Beacon frame. -#define FWIMR_TBTT BIT(17) // The exact TBTT time interrupt. -#define FWIMR_BCNERLY BIT(16) // This interrupt is issue at the time set by DRVERLYINT register before TBTT time. -#define FWIMR_BCNDMA7 BIT(15) // When BCNDMA interval arrives before TBTT7, informs MCU to prepare beacon. -#define FWIMR_BCNDMA6 BIT(14) // When BCNDMA interval arrives before TBTT6, informs MCU to prepare beacon. -#define FWIMR_BCNDMA5 BIT(13) // When BCNDMA interval arrives before TBTT5, informs MCU to prepare beacon. -#define FWIMR_BCNDMA4 BIT(12) // When BCNDMA interval arrives before TBTT4, informs MCU to prepare beacon. -#define FWIMR_BCNDMA3 BIT(11) // When BCNDMA interval arrives before TBTT3, informs MCU to prepare beacon. -#define FWIMR_BCNDMA2 BIT(10) // When BCNDMA interval arrives before TBTT2, informs MCU to prepare beacon. -#define FWIMR_BCNDMA1 BIT(9) // When BCNDMA interval arrives before TBTT1, informs MCU to prepare beacon. -#define FWIMR_BCNDMA0 BIT(8) // When BCNDMA interval arrives before TBTT0, informs MCU to prepare beacon. -#define FWIMR_LP_STBY BIT(7) // Low Power Standby Wake interrupt. -#define FWIMR_ATIM BIT(6) // This interrupt is issued when it is at the time ATIM ms before ATIMWND expiring. -#define FWIMR_HRCV BIT(5) // Host Recover CPU Loop Instruction. -#define FWIMR_H2CCMD BIT(4) // Host To CPU Message Interrupt. -#define FWIMR_RXDONE BIT(3) // -#define FWIMR_ERRORHDL BIT(2) // FWHW/ TXDMA/ RXDMA/ WMAC error status interrupt. -#define FWIMR_TXCCX BIT(1) // -#define FWIMR_TXCLOSE BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C FTIMR bits (Offset 0x138-13B, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C FTISR bits (Offset 0x13C-13F, 32 bits) -//---------------------------------------------------------------------------- -#define FTIMR_FWBT_CMD BIT(18) // 92D_REG, FW BT_CMD interrupt mask -#define FTIMR_RPWM BIT(8) // RPWM INT Status. Write 1 clear. -#define FTIMR_PSTIMER BIT(7) // Enable PSTimer interrupt. -#define FTIMR_TIMEOUT1 BIT(6) // Enable Timer1 interrupt. -#define FTIMR_TIMEOUT0 BIT(5) // Enable Timer0 interrupt. -#define FTIMR_GT4 BIT(4) // Enable General Timer[4] interrupt. -#define FTIMR_GT3 BIT(3) // Enable General Timer[3] interrupt. -#define FTIMR_GT2 BIT(2) // Enable General Timer[2] interrupt. -#define FTIMR_GT1 BIT(1) // Enable General Timer[1] interrupt. -#define FTIMR_GT0 BIT(0) // Enable General Timer[0] interrupt. - -//---------------------------------------------------------------------------- -// 8192C PKTBUF_DBG_CTRL bits (Offset 0x140-143, 32 bits) -//---------------------------------------------------------------------------- -#define RXPKTBUF_DBG BIT(14) // 1: Enable RXPKTBUF debug mode. -#define TXPKTBUF_DBG BIT(13) // 1: Enable TXPKTBUF debug mode. -#define PKTBUF_DBG_ADDR_SHIFT 0 // The address of TRXPKTBUF to be read. -#define PKTBUF_DBG_ADDR_Mask 0x01FFF - -// General Purpose Timer. (Offset 0x150 - 0x16Fh) -//---------------------------------------------------------------------------- -// 8192C TC0_CTRL bits (Offset 0x150-153, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C TC1_CTRL bits (Offset 0x154-157, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C TC2_CTRL bits (Offset 0x158-15B, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C TC3_CTRL bits (Offset 0x15C-15F, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C TC4_CTRL bits (Offset 0x160-163, 32 bits) -//---------------------------------------------------------------------------- -#define TCINT_EN BIT(26) // When write "1" to this bit, Counter starts counting down. -#define TCMODE BIT(25) // Timer/Counter mode. -#define TCEN BIT(24) // Timer/Counter enable. -#define TCData_SHIFT 0 // Timer/Counter data register. It specifies the time-out duration. -#define TCData_Mask 0x0FFFFFF - -//---------------------------------------------------------------------------- -// 8192C TCUNIT_BASE bits (Offset 0x164-165, 16 bits) -//---------------------------------------------------------------------------- -#define TCUNIT_BASE_TIME_SHIFT 0 // num of clocks that equals to the base time unit of timer/counter. -#define TCUNIT_BASE_TIME_Mask 0x03FFF -// General Purpose Timer. (Offset 0x150 - 0x16Fh) - -//---------------------------------------------------------------------------- -// 8192C MBIST_START bits (Offset 0x174-177, 32 bits) -//---------------------------------------------------------------------------- -#define TXLLT_BISTP BIT(10) // TXLLT BIST Start Pulse. -#define TXOQT_BISTP BIT(9) // TXOQT BIST Start Pulse. -#define TXPKT_BISTP BIT(8) // TXPKT Buffer BIST Start Pulse. -#define RXPKT_BISTP BIT(7) // RXPKT Buffer BIST Start Pulse. -#define TXDBUF_BISTP BIT(6) // TXDBUF BIST Start Pulse. -#define TXFIFO_BISTP BIT(5) // TXFIFO BIST Start Pulse. -#define RXFIFO_BISTP BIT(4) // RXFIFO BIST Start Pulse. -#define WKEYLLT_BISTP BIT(3) // WKEY BIST Start Pulse. -#define WRXBA_BISTP BIT(2) // WRXBA BIST Start Pulse. - -//---------------------------------------------------------------------------- -// 8192C MBIST_DONE bits (Offset 0x178-17B, 32 bits) -//---------------------------------------------------------------------------- -#define TXLLT_BISTD BIT(10) // TXLLT BIST Done. -#define TXOQT_BISTD BIT(9) // TXOQT BIST Done. -#define TXPKT_BISTD BIT(8) // TXPKT Buffer BIST Done. -#define RXPKT_BISTD BIT(7) // RXPKT Buffer BIST Done. -#define TXDBUF_BISTD BIT(6) // TXDBUF BIST Done. -#define TXFIFO_BISTD BIT(5) // TXFIFO BIST Done. -#define RXFIFO_BISTD BIT(4) // RXFIFO BIST Done. -#define WKEYLLT_BISTD BIT(3) // WKEY BIST Done. -#define WRXBA_BISTD BIT(2) // WRXBA BIST Done. - -//---------------------------------------------------------------------------- -// 8192C MBIST_FAIL bits (Offset 0x17C-17F, 32 bits) -//---------------------------------------------------------------------------- -#define TXLLT_BISTF BIT(10) // TXLLT BIST Fail. -#define TXOQT_BISTF BIT(9) // TXOQT BIST Fail. -#define TXPKT_BISTF BIT(8) // TXPKT Buffer BIST Fail. -#define RXPKT_BISTF BIT(7) // RXPKT Buffer BIST Fail. -#define TXDBUF_BISTF BIT(6) // TXDBUF BIST Fail. -#define TXFIFO_BISTF BIT(5) // TXFIFO BIST Fail. -#define RXFIFO_BISTF BIT(4) // RXFIFO BIST Fail. -#define WKEYLLT_BISTF BIT(3) // WKEY BIST Fail. -#define WRXBA_BISTF BIT(2) // WRXBA BIST Fail. - -//---------------------------------------------------------------------------- -// 8192C FMETHR bits (Offset 0x1C8-1CB, 32 bits) -//---------------------------------------------------------------------------- -#define FMSG_INT BIT(31) // Toggle this bit will generate interrupt to Host. -#define FW_MSG_SHIFT 0 // User Defined Message. -#define FW_MSG_Mask 0x07FFFFFFF - -//---------------------------------------------------------------------------- -// 8192C HMETFR bits (Offset 0x1CC-1CF, 32 bits) -//---------------------------------------------------------------------------- -#define HRCV_MSG_SHIFT 24 // User Defined Message. -#define HRCV_MSG_Mask 0x0FF -#define INT_BOX3 BIT(3) // MSG_BOX_3 Valid. Enable when the Entry is write. -#define INT_BOX2 BIT(2) // MSG_BOX_2 Valid. Enable when the Entry is write. -#define INT_BOX1 BIT(1) // MSG_BOX_1 Valid. Enable when the Entry is write. -#define INT_BOX0 BIT(0) // MSG_BOX_0 Valid. Enable when the Entry is write. - -//---------------------------------------------------------------------------- -// 8192C LLT_INI bits (Offset 0x1E0-1E3, 32 bits) -//---------------------------------------------------------------------------- -#define LLTE_RWM_SHIFT 30 // -#define LLTE_RWM_Mask 0x03 -#define LLTINI_PDATA_SHIFT 16 // LLT Entry Write/Read DATA for MCU. -#define LLTINI_PDATA_Mask 0x0FF -#define LLTINI_ADDR_SHIFT 8 // LLT Entry Access Offset. -#define LLTINI_ADDR_Mask 0x0FF -#define LLTINI_HDATA_SHIFT 0 // LLT Entry Write/Read DATA for HCI. -#define LLTINI_HDATA_Mask 0x0FF -// LLTE_RWM -#define LLTE_RWM_NO_ACTIVE 0x00 -#define LLTE_RWM_WR 0x01 -#define LLTE_RWM_RD 0x03 - -//---------------------------------------------------------------------------- -// 8192C BB_ACCEESS_CTRL bits (Offset 0x1E8-1EB, 32 bits) -//---------------------------------------------------------------------------- -#define BB_WRITE_READ_SHIFT 30 // -#define BB_WRITE_READ_Mask 0x03 -#define BB_WRITE_EN_SHIFT 12 // Byte Write Enable. -#define BB_WRITE_EN_Mask 0x0F -#define BB_ADDR_SHIFT 2 // Baseband Access Write/Read Address (in DW unit). -#define BB_ADDR_Mask 0x03FF -#define BB_ERRACC BIT(0) // Duplicate Access when previous cycle pending (write one clear). - - -// -// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) -// -//---------------------------------------------------------------------------- -// 8192C RQPN bits (Offset 0x200-203, 32 bits) -//---------------------------------------------------------------------------- -#define LD_RQPN BIT(31) // Write 1 to set RQPN bit[79:0] value to page numbers for initialization. -#define LPQ_PUBLIC_DIS BIT(25) // bit=1, available Tx page size excludes the public queue. -#define HPQ_PUBLIC_DIS BIT(24) // bit=1, available Tx page size excludes the public queue. -#define PUBQ_SHIFT 16 // Public Reserved Page Number. -#define PUBQ_Mask 0x0FF -#define LPQ_SHIFT 8 // Low Priority Queue Reserved Page Number. -#define LPQ_Mask 0x0FF -#define HPQ_SHIFT 0 // High Priority Queue Reserved Page Number. -#define HPQ_Mask 0x0FF - -#define _HPQ(x) ((x) & HPQ_Mask) -#define _LPQ(x) (((x) & LPQ_Mask) << LPQ_SHIFT) -#define _PUBQ(x) (((x) & PUBQ_Mask) << PUBQ_SHIFT) -#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register - - -//---------------------------------------------------------------------------- -// 8192C FIFOPAGE bits (Offset 0x204-207, 32 bits) -//---------------------------------------------------------------------------- -#define TXPKTNUM_SHIFT 24 // Packet number in TXPKTBUF. -#define TXPKTNUM_Mask 0x0FF -#define PUB_AVAL_PG_SHIFT 16 // Available Public Queue Page Number. -#define PUB_AVAL_PG_Mask 0x0FF -#define LPQ_AVAL_PG_SHIFT 8 // Available Low Priority Queue Page Number. -#define LPQ_AVAL_PG_Mask 0x0FF -#define HPQ_AVAL_PG_SHIFT 0 // Available High Priority Queue Page Number. -#define HPQ_AVAL_PG_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C TDECTRL bits (Offset 0x208-20B, 32 bits) -//---------------------------------------------------------------------------- -#define LLT_FREE_PAGE_SHIFT 24 // LLT Free Page. -#define LLT_FREE_PAGE_Mask 0x0FF -#define BCN_VALID BIT(16) // bit=1, beacon packet has finished to write to txpktbuffer. -#define BCN_HEAD_SHIFT 8 // head page of Bcnq packet which is Tx DMA filled. -#define BCN_HEAD_Mask 0x0FF -#define BLK_DESC_NUM_SHIFT 4 // The Most Number of Tx Descriptor per Bulk Out Only for USB. -#define BLK_DESC_NUM_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C TXDMA_OFFSET_CHK bits (Offset 0x20C-20F, 32 bits) -//---------------------------------------------------------------------------- -#define PG_UNDER_TH_SHIFT 16 // Page threshold value is check by Tx DMA engine. -#define PG_UNDER_TH_Mask 0x0FF -#define CHK_PG_TH_EN BIT(10) // Enable Tx DMA to check total pages if it is under page threshold. -#define DROP_DATA_EN BIT(9) // Enable Tx DMA to drop the redundant data of packet. -#define CHECK_OFFSET_EN BIT(8) // Enable Tx DMA to check offset value. -#define CHECK_OFFSET_SHIFT 0 // Offset value is check by Tx DMA engine. -#define CHECK_OFFSET_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C TXDMA_STATUS bits (Offset 0x210-213, 32 bits) -//---------------------------------------------------------------------------- -#define PAYLOAD_UDN BIT(14) // Payload is under the packet length of Tx descriptor. -#define PAYLOAD_OVF BIT(13) // Payload is over the packet length of Tx descriptor. -#define DSC_CHKSUM_FAIL BIT(12) // Tx descriptor checksum error. -#define UNKNOWN_QSEL BIT(11) // An unknown QSEL of Tx descriptor is detected. -#define EP_QSEL_DIFF BIT(10) // Tx Endpoint is unmatched with the QSEL of descriptor. -#define TX_OFFS_UNMATCH BIT(9) // Tx offset is unmatched. -#define TXOQT_UDN BIT(8) // TXOQT Underflow. -#define TXOQT_OVF BIT(7) // TXOQT Overflow. -#define TXDMA_SFF_UDN BIT(6) // TXDMA Sync FIFO Underflow. -#define TXDMA_SFF_OVF BIT(5) // TXDMA Sync FIFO Overflow. -#define LLT_NULL_PG BIT(4) // TXDMA reads NULL page. -#define PAGE_UDN BIT(3) // Total pages included PTCL un-return pages under the total reserved pages. -#define PAGE_OVF BIT(2) // Total pages included PTCL un-return pages over the total reserved pages. -#define TXFF_PG_UDN BIT(1) // TXFF page underflow in TDE page controller. -#define TXFF_PG_OVF BIT(0) // TXFF page overflow in TDE page controller. - -//---------------------------------------------------------------------------- -// 8192C RXDMA_AGG_PG_TH bits (Offset 0x280-283, 32 bits) -//---------------------------------------------------------------------------- -#define RXDMA_AGG_PG_TH_LMT(x) ((x & 0x0FF)<<0) // DMA inform host to receive pkts, when exceeds the threshold. - -//---------------------------------------------------------------------------- -// 8192C RXPKT_NUM bits (Offset 0x284-287, 32 bits) -//---------------------------------------------------------------------------- -#define RXPKT_NUM_LMT_SHIFT 24 // number of packets in RXPKTBUF. -#define RXPKT_NUM_LMT_Mask 0x0FF -#define RW_RELEASE_EN BIT(18) // bit=1, RXDMA will enter this mode after RXDMA packet to host completed and stop. -#define RXDMA_IDLE BIT(17) // RXDMA finishes DMA will report idle state in this bit. -#define RXPKT_RELEASE_POLL BIT(16) // bit=1, RXDMA will decrease RX PKT counter by one. -#define FW_UPD_RDPTR_SHIFT 0 // FW updates before write RXPKT_RELEASE_POLL to 1. -#define FW_UPD_RDPTR_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C RXDMA_STATUS bits (Offset 0x288-28B, 32 bits) -//---------------------------------------------------------------------------- -#define FW_POLL_ISSUE BIT(5) // FW Release Poll Error. -#define RX_DATA_UDN BIT(4) // RX Data Underflow. Clear by SW. -#define RX_SFF_UDN BIT(3) // RX Sync FIFO Underflow. -#define RX_SFF_OVF BIT(2) // RX Sync FIFO Overflow. -#define USB_REQ_LEN_OVF BIT(1) // USB RXAGGEN Error due to RX length overflow. -#define RXPKT_OVF BIT(0) // When RX Packet is more than 255 packets remaining in FF. - - -// -// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) -// -//---------------------------------------------------------------------------- -// 8192C PCIE_CTRL_REG bits (Offset 0x300-303, 32 bits) -//---------------------------------------------------------------------------- -#define MAX_RXDMA_SHIFT 28 // RXDMA Burst Size selection. -#define MAX_RXDMA_Mask 0x07 -#define MAX_TXDMA_SHIFT 24 // TXDMA Burst Size selection. -#define MAX_TXDMA_Mask 0x07 -#define En_HWENTRL BIT(19) // Enable HW call EMAC to enter L23 actively. -#define EN_SWENTR_L23 BIT(17) // Enable SW call EMAC to enter L23. -#define EN_HWEXITL1 BIT(16) // Enable HW call EMAC to exit L1. -#define BCNQSTOP BIT(15) // BCNQ DMA STOP. -#define HQSTOP BIT(14) // HQ DMA STOP. -#define MGQSTOP BIT(13) // VOKQ DMA STOP. -#define VOQSTOP BIT(12) // VOKQ DMA STOP. -#define VIQSTOP BIT(11) // VIQ DMA STOP. -#define BEQSTOP BIT(10) // BEQ DMA STOP. -#define BKQSTOP BIT(9) // BKQ DMA STOP. -#define RXQSTOP BIT(8) // RX DMA STOP. -#define HQ_POLL BIT(7) // High Queue Polling bit, read result will be hpqflag. -#define MGQ_POLL BIT(6) // Manag Queue Polling bit, read result will be mgqflag. -#define BCNQ_POLL BIT(4) // BCNQ Polling bit, read result will be bpqflag. -#define VOQ_POLL BIT(3) // VOQ Polling bit, read result will be voqflag. -#define VIQ_POLL BIT(2) // VIQ Polling bit, read result will be viqflag. -#define BEQ_POLL BIT(1) // BEQ Polling bit, read result will be beqflag. -#define BKQ_POLL BIT(0) // BKQ Polling bit, read result will be bkqflag. - -//---------------------------------------------------------------------------- -// 8192C INT_MIG bits (Offset 0x304-307, 32 bits) -//---------------------------------------------------------------------------- -#define TTMRMIT_Shift 28 // 92D_REG, Tx timer mitigation -#define TTMRMIT_Mask 0x0F -#define TNUMMIT_Shift 24 // 92D_REG, Tx number mitigation -#define TNUMMIT_Mask 0x0F -#define RTMRMIT_Shift 20 // 92D_REG, Rx timer mitigation -#define RTMRMIT_Mask 0x0F -#define RNUMMIT_Shift 16 // 92D_REG, Rx number mitigation -#define RNUMMIT_Mask 0x0F -#define INTMT_SHIFT 16 // Interrupt Couter for setting Interrupt Migration. -#define INTMT_Mask 0x0FFFF -#define MIGRATE_TIMER_SHIFT 0 // Timer for setting Interrupt Migration. -#define MIGRATE_TIMER_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C DBI bits (Offset 0x348-353, 96 bits) -//---------------------------------------------------------------------------- -#define DBI_ACC_EXT BIT(19) // 92D_REG, DBI access external register on ELBI -#define DBI_MACSEL BIT(18) // 92D_REG, DBI access MAC1 select -#define DBI_RFLAG BIT(17) // DBI Read Flag. -#define DBI_WFLAG BIT(16) // DBI Write Flag. -#define DBI_WREN_SHIFT 12 // DBI Write Enable, High active. -#define DBI_WREN_Mask 0x0F -#define DBI_ADDR_SHIFT 0 // DBI Address. -#define DBI_ADDR_Mask 0x0FFF - -//----------------------------------------------------------------------------// -// 8192C MDIO bits (Offset 0x354-35B, 64 bits) -//---------------------------------------------------------------------------- -#define ECRC_EN BIT(7) // ECRC Enable. -#define MDIO_RFLAG BIT(6) // MDIO Read Flag. -#define MDIO_WFLAG BIT(5) // MDIO Write Flag. -#define MDIO_ADDR_SHIFT 0 // MDIO Address. -#define MDIO_ADDR_Mask 0x01F - -#define MDIO_RDATA_SHIFT 16 // MDIO Read Data. -#define MDIO_RDATA_Mask 0x0FFFF -#define MDIO_WDATA_SHIFT 0 // MDIO Write Data. -#define MDIO_WDATA_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C UART_CTRL bits (Offset 0x364-36B, 64 bits) -//---------------------------------------------------------------------------- -#define UART_WDATA_H_SHIFT 0 // UART Write Data [31:8], read will be UART Read Data[31:8]. -#define UART_WDATA_H_Mask 0x0FFFFFF - -#define UART_DMA_STS_SHIFT 24 // UART DMA Status. -#define UART_DMA_STS_Mask 0x07 -#define UART_DMA_MOD BIT(20) // UART DMA Mode. -#define UART_RDMA BIT(19) // UART RX DMA Flag. -#define UART_TDMA BIT(18) // UART TX DMA Flag. -#define UART_RCMD BIT(17) // UART Read Command. -#define UART_WCMD BIT(16) // UART Write Command. -#define UART_ADDR_SHIFT 10 // UART Address. -#define UART_ADDR_Mask 0x03F -#define UART_WDATA_L_SHIFT 0 // UART Write Data [7:0], read will be UART Read Data[7:0]. -#define UART_WDATA_L_Mask 0x0FF - - -// -// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) -// -//---------------------------------------------------------------------------- -// 8192C VOQ_INFO bits (Offset 0x400-403, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C VIQ_INFO bits (Offset 0x404-407, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C BEQ_INFO bits (Offset 0x408-40B, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C BKQ_INFO bits (Offset 0x40C-40F, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C MGQ_INFO bits (Offset 0x410-413, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C HIQ_INFO bits (Offset 0x414-417, 32 bits) -//---------------------------------------------------------------------------- -#define Q_CPU_HEAD_SHIFT 24 // MCU will handle q_pkt head. -#define Q_CPU_HEAD_Mask 0x0FF -#define Q_PKT_NUM_SHIFT 16 // total Q pkt number in TxPktbuffer. -#define Q_PKT_NUM_Mask 0x0FF -#define Q_FW_NUM_SHIFT 8 // total Q FW number in TxPktbuffer. -#define Q_FW_NUM_Mask 0x0FF -#define Q_HEAD_PG_SHIFT 0 // head page of the first packet of Q. -#define Q_HEAD_PG_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C BCNQ_INFO bits (Offset 0x418-41A, 24 bits) -//---------------------------------------------------------------------------- -#define BCNQ_PKT_NUM_SHIFT 16 // total BCNQ pkt number in TxPktbuffer. -#define BCNQ_PKT_NUM_Mask 0x0FF -#define BCNQ_FW_NUM_SHIFT 8 // total BCNQ FW number in TxPktbuffer. -#define BCNQ_FW_NUM_Mask 0x0FF -#define BCNQ_HEAD_PG_SHIFT 0 // head page of the first packet of BCNQ. -#define BCNQ_HEAD_PG_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C TXPKT_EMPTY bits (Offset 0x41B, 8 bits) -//---------------------------------------------------------------------------- -#define BCNQ_EMPTY BIT(7) // queue is empty. Report by MAC. -#define HQQ_EMPTY BIT(6) // queue is empty. Report by MAC. -#define HMGQ_EMPTY BIT(5) // queue is empty. Report by MAC. -#define CMGQ_EMPTY BIT(4) // queue is empty. Report by MAC. -#define BKQ_EMPTY BIT(3) // queue is empty. Report by MAC. -#define BEQ_EMPTY BIT(2) // queue is empty. Report by MAC. -#define VIQ_EMPTY BIT(1) // queue is empty. Report by MAC. -#define VOQ_EMPTY BIT(0) // queue is empty. Report by MAC. - -//---------------------------------------------------------------------------- -// 8192C CPU_MGQ_INFO bits (Offset 0x41C-41F, 32 bits) -//---------------------------------------------------------------------------- -#define CPUMGQ_FW_NUM_SHIFT 8 // total CPU MGQ fw number in TxPktbuffer. -#define CPUMGQ_FW_NUM_Mask 0x0FF -#define CPUMGQ_HEAD_PG_SHIFT 0 // head page of CPU MGQ. -#define CPUMGQ_HEAD_PG_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C FWHW_TXQ_CTRL bits (Offset 0x420-422, 24 bits) -//---------------------------------------------------------------------------- -#define RTS_LIMIT_IN_OFDM BIT(23) // 92D_REG, rts rate will not down to cck rate -#define EN_BCNQ_DL BIT(22) // 92D_REG, 1: ptcl consider there is bcn pkt in txbuf; 0: mask bcn pkt num in bcnq -#define EN_RD_RESP_NAV_BK BIT(21) // Control the RD responder NAV criteria for TX. -#define EN_WR_FREE_TAIL BIT(20) // 1:Drive wirte Bcnq_boundary,Hw set free_tail in Boundary-1; 0:no update. -#define CHK_LOSS_QSEL_SHIFT 17 // -#define CHK_LOSS_QSEL_Mask 0x07 -#define EN_CHECK_LOSS BIT(16) // bit=1, HW will monitor packet loss from TXDMA. -#define EN_QUEUE_RPT_SHIFT 8 // 1: HW will report tx_status 0: no report. -#define EN_QUEUE_RPT_Mask 0x07F -#define EN_AMPDU_RTY_NEW BIT(7) // AMPDU aggregation mode with retry MPDUs and new MPDUs. -#define LIFETIME_EN BIT(6) // Enable lift time drop. -#define EN_CPU_HANDLE_SHIFT 0 // PKT need cpu handle. -#define EN_CPU_HANDLE_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C HWSEQ_CTRL bits (Offset 0x423, 8 bits) -//---------------------------------------------------------------------------- -#define HWSEQ_BCN_EN BIT(6) // -#define HWSEQ_HI_EN BIT(5) // -#define HWSEQ_MGT_EN BIT(4) // -#define HWSEQ_BK_EN BIT(3) // -#define HWSEQ_BE_EN BIT(2) // -#define HWSEQ_VI_EN BIT(1) // -#define HWSEQ_VO_EN BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C MULTI_BCNQ_EN bits (Offset 0x426, 8 bits) -//---------------------------------------------------------------------------- -#define MBID_BCNQ7_EN BIT(7) // -#define MBID_BCNQ6_EN BIT(6) // -#define MBID_BCNQ5_EN BIT(5) // -#define MBID_BCNQ4_EN BIT(4) // -#define MBID_BCNQ3_EN BIT(3) // -#define MBID_BCNQ2_EN BIT(2) // -#define MBID_BCNQ1_EN BIT(1) // -#define MBID_BCNQ0_EN BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C MULTI_BCNQ_OFFSET bits (Offset 0x427, 8 bits) -//---------------------------------------------------------------------------- -#define MBCNQ_OFFSET_SHIFT 0 // page number between two consecutive BCNQ head page. -#define MBCNQ_OFFSET_Mask 0x03 - -//---------------------------------------------------------------------------- -// 8192C SPEC_SIFS bits (Offset 0x428-429, 16 bits) -//---------------------------------------------------------------------------- -#define SPEC_SIFS_OFDM_SHIFT 8 // spec SIFS value for duration calculation. -#define SPEC_SIFS_OFDM_Mask 0x0FF -#define SPEC_SIFS_CCK_SHIFT 0 // spec SIFS value for duration calculation. -#define SPEC_SIFS_CCK_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C RL bits (Offset 0x42A-42B, 16 bits) -//---------------------------------------------------------------------------- -#define SRL_SHIFT 8 // Short Retry Limit. -#define SRL_Mask 0x03F -#define LRL_SHIFT 0 // Long Retry Limit. -#define LRL_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C DARFRC bits (Offset 0x430-437, 64 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C RARFRC bits (Offset 0x438-43F, 64 bits) -//---------------------------------------------------------------------------- -#define ARF_RC8_SHIFT 24 // Response Auto Rate Fallback Retry Count. -#define ARF_RC8_Mask 0x01F -#define ARF_RC7_SHIFT 16 // Response Auto Rate Fallback Retry Count. -#define ARF_RC7_Mask 0x01F -#define ARF_RC6_SHIFT 8 // Response Auto Rate Fallback Retry Count. -#define ARF_RC6_Mask 0x01F -#define ARF_RC5_SHIFT 0 // Response Auto Rate Fallback Retry Count. -#define ARF_RC5_Mask 0x01F - -#define ARF_RC4_SHIFT 24 // Response Auto Rate Fallback Retry Count. -#define ARF_RC4_Mask 0x01F -#define ARF_RC3_SHIFT 16 // Response Auto Rate Fallback Retry Count. -#define ARF_RC3_Mask 0x01F -#define ARF_RC2_SHIFT 8 // Response Auto Rate Fallback Retry Count. -#define ARF_RC2_Mask 0x01F -#define ARF_RC1_SHIFT 0 // Response Auto Rate Fallback Retry Count. -#define ARF_RC1_Mask 0x01F - -//---------------------------------------------------------------------------- -// 8192C RRSR bits (Offset 0x440-442, 24 bits) -//---------------------------------------------------------------------------- -#define RRSR_SHORT BIT(23) // Respond with short preamble packet. Default is long preamble. -#define RRSR_RSC_SHIFT 21 // Response frame sub-channel configuration. -#define RRSR_RSC_Mask 0x03 -#define RRSC_BITMAP_SHIFT 0 // Response Auto Rate Fallback Retry Count. -#define RRSC_BITMAP_Mask 0x0FFFFF - -//---------------------------------------------------------------------------- -// 8192C AGGLEN_LMT bits (Offset 0x458-45B, 32 bits) -//---------------------------------------------------------------------------- -#define AGGLMT_MCS15S_SHIFT 28 // Aggregation Limit for MCS 15 SGI in the units of number of MPDUs. -#define AGGLMT_MCS15S_Mask 0x0F -#define AGGLMT_MCS15_SHIFT 24 // Aggregation Limit for MCS 13~15 in the units of number of MPDUs. -#define AGGLMT_MCS15_Mask 0x0F -#define AGGLMT_MCS12_SHIFT 20 // Aggregation Limit for MCS 11~12 in the units of number of MPDUs. -#define AGGLMT_MCS12_Mask 0x0F -#define AGGLMT_MCS10_SHIFT 16 // Aggregation Limit for MCS 8~10 in the units of number of MPDUs. -#define AGGLMT_MCS10_Mask 0x0F -#define AGGLMT_MCS7S_SHIFT 12 // Aggregation Limit for MCS 7 SGI in the units of number of MPDUs. -#define AGGLMT_MCS7S_Mask 0x0F -#define AGGLMT_MCS7_SHIFT 8 // Aggregation Limit for MCS 6~7 in the units of number of MPDUs. -#define AGGLMT_MCS7_Mask 0x0F -#define AGGLMT_MCS5_SHIFT 4 // Aggregation Limit for MCS 3~5 in the units of number of MPDUs. -#define AGGLMT_MCS5_Mask 0x0F -#define AGGLMT_MCS2_SHIFT 0 // Aggregation Limit for MCS 0~2 in the units of number of MPDUs. -#define AGGLMT_MCS2_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C AMPDU_MIN_SPACE bits (Offset 0x45C, 8 bits) -//---------------------------------------------------------------------------- -#define MIN_SPACE_SHIFT 0 // The spacing between sub-frame. -#define MIN_SPACE_Mask 0x07 - -//---------------------------------------------------------------------------- -// 8192C FAST_EDCA_CTRL bits (Offset 0x460-462, 24 bits) -//---------------------------------------------------------------------------- -#define FAST_EDCA_TO_SHIFT 16 // If pkt timeout, HW will contend channel using fast backoff. -#define FAST_EDCA_TO_Mask 0x01F -#define FAST_EDCA_PKT_TH_SHIFT 0 // If pkt in txpktbuffer over thrs. HW will fast backoff. -#define FAST_EDCA_PKT_TH_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C RD_RESP_PKT_TH bits (Offset 0x463, 8 bits) -//---------------------------------------------------------------------------- -#define RD_RESP_PKT_TH_LMT_SHIFT 0 // granted ACq pkt num beyond this, responder set More PPDU=1 & piggyback. -#define RD_RESP_PKT_TH_LMT_Mask 0x01F - -//---------------------------------------------------------------------------- -// 8192C INIRTS_RATE_SEL bits (Offset 0x480, 8 bits) -//---------------------------------------------------------------------------- -#define INIRTSMCS_SEL_SHIFT 0 // initial rate for Control type frame transmitted as EDCA originator. -#define INIRTSMCS_SEL_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C POWER_STAGE1 bits (Offset 0x4B4-4B6, 24 bits) -//---------------------------------------------------------------------------- -#define PWR_STAGE1_SHIFT 0 // User define Power Stage1. -#define PWR_STAGE1_Mask 0x0FFFFFF - -//---------------------------------------------------------------------------- -// 8192C POWER_STAGE2 bits (Offset 0x4B8-4BA, 24 bits) -//---------------------------------------------------------------------------- -#define PWR_STAGE2_SHIFT 0 // User define Power Stage2. -#define PWR_STAGE2_Mask 0x0FFFFFF - -//---------------------------------------------------------------------------- -// 8192C STBC_SETTING bits (Offset 0x4C4, 8 bits) -//---------------------------------------------------------------------------- -#define NESS_SHIFT 2 // -#define NESS_Mask 0x03 -#define STBC_CFEND_SHIFT 0 // CFEND STBC. -#define STBC_CFEND_Mask 0x03 - -//---------------------------------------------------------------------------- -// 8192C PROT_MODE_CTRL bits (Offset 0x4C8-4C9, 16 bits) -//---------------------------------------------------------------------------- -#define RTS_TXTIME_TH_SHIFT 8 // RTS pkt txtime thrs -#define RTS_TXTIME_TH_Mask 0x0FF -#define RTS_LEN_TH_SHIFT 0 // RTS Length thrs. -#define RTS_LEN_TH_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C BAR_MODE_CTRL bits (Offset 0x4CC-4CE, 24 bits) -//---------------------------------------------------------------------------- -#define BAR_RTY_LMT_SHIFT 16 // BAR retry limit. -#define BAR_RTY_LMT_Mask 0x03 -#define BAR_PKT_TXTIME_TH_SHIFT 8 // BAR pkt txtime thrs. -#define BAR_PKT_TXTIME_TH_Mask 0x0FF -#define BAR_PKTNUM_TH_SHIFT 0 // BAR Pktnum Thrs. -#define BAR_PKTNUM_TH_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C RA_TRY_RATE_AGG_LMT bits (Offset 0x4CF, 8 bits) -//---------------------------------------------------------------------------- -#define RA_BAR_RTY_LMT_SHIFT 5 // BAR retry limit. -#define RA_BAR_RTY_LMT_Mask 0x07 -#define RA_TRY_RATE_AGG_LMT_NUM_SHIFT 0 // aggr pkt num limit for try up rate of when desc try bit=1. -#define RA_TRY_RATE_AGG_LMT_NUM_Mask 0x01F - -//---------------------------------------------------------------------------- -// 8192C NQOS_SEQ bits (Offset 0x4DC-4DD, 16 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C QOS_SEQ bits (Offset 0x4DE-4DF, 16 bits) -//---------------------------------------------------------------------------- -#define N_QOS_SSN_SHIFT 0 // TXDESC HWSEQEN is set, MAC will overwrite SEQ control by this. - // TXDESC HWSEQEN is set and QoS field is also set, - // MAC will overwrite SEQ control by this. -#define N_QOS_SSN_Mask 0x0FFF - -//---------------------------------------------------------------------------- -// 8192C NEED_CPU_HANDLE bits (Offset 0x4E0, 8 bits) -//---------------------------------------------------------------------------- -#define NEED_CPU_HANDLE_Q_SHIFT 0 // 1:HW prepare ok, this q need cpu handle & poll. -#define NEED_CPU_HANDLE_Q_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C PTCL_ERR_STATUS bits (Offset 0x4E1, 8 bits) -//---------------------------------------------------------------------------- -#define PTCL_TL_PG_OVF BIT(7) // Protocol Total Page out of range. -#define TXHANG_ERR BIT(5) // TX time is greater than 32ms. -#define HW_RD_NULL_STATUS_ERR BIT(4) // HW read null page counter error. -#define HW_RD_NULL_CTN_ERR BIT(3) // HW Contention read null page counter error. -#define HW_RD_NULL_CNT_ERR BIT(2) // HW read null page counter error. -#define PTCL_TL_PG_ERR BIT(1) // Protocol Total page number error. -#define DESC_QSEL_ERR BIT(0) // TXDESC QSEL field mismatch error. - -//---------------------------------------------------------------------------- -// 8192C PKT_LOSE_RPT bits (Offset 0x4E2, 8 bits) -//---------------------------------------------------------------------------- -#define PKT_LOSE_BK BIT(3) // 1:queue happen pkt lose, 0:no lose. -#define PKT_LOSE_BE BIT(2) // 1:queue happen pkt lose, 0:no lose. -#define PKT_LOSE_VI BIT(1) // 1:queue happen pkt lose, 0:no lose. -#define PKT_LOSE_VO BIT(0) // 1:queue happen pkt lose, 0:no lose. - - -//---------------------------------------------------------------------------- -// 8192C EDCA_VO_PARA bits (Offset 0x500-503, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C EDCA_VI_PARA bits (Offset 0x504-507, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C EDCA_BE_PARA bits (Offset 0x508-50B, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C EDCA_BK_PARA bits (Offset 0x50C-50F, 32 bits) -//---------------------------------------------------------------------------- -#define TXOP_SHIFT 16 // TXOP Limit. -#define TXOP_Mask 0x0FFFF -#define CW_SHIFT 8 // ECWmax/ECWmin -#define CW_Mask 0x0FF -#define AIFS_SHIFT 0 // Arbitrary Inter frame space. -#define AIFS_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C BCNTCFG bits (Offset 0x510-511, 16 bits) -//---------------------------------------------------------------------------- -#define BCNECW_SHIFT 8 // Beacon Contention Window. -#define BCNECW_Mask 0x0F -#define BCNIFS_SHIFT 0 // Beacon Interframe Space. -#define BCNIFS_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C SIFS_CCK bits (Offset 0x514-515, 16 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C SIFS_OFDM bits (Offset 0x516-517, 16 bits) -//---------------------------------------------------------------------------- -#define SIFS_TRX_SHIFT 8 // SIFS time required for any immediate response. -#define SIFS_TRX_Mask 0x0FF -#define SIFS_CTX_SHIFT 0 // SIFS time required for consecutive TX events. -#define SIFS_CTX_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C TX_PTCL_CTRL bits (Offset 0x520-521, 16 bits) -//---------------------------------------------------------------------------- -#define DIS_CCA BIT(15) // bit=1, disable CCA. -#define SIFS_BK_EN BIT(12) // SIFS Break Check Criteria enable for AMPDU aggregation. -#define TXQ_NAV_MSK_SHIFT 8 // 1:Queue BKF must wait TX Nav finished, 0:Queue not need wait. -#define TXQ_NAV_MSK_Mask 0x0F -#define DIS_CW BIT(7) // bit=1, disable CW. -#define RDG_END_TXOP BIT(6) // 1:Nav protect all txop, 0:Nav protect to next pkt. -#define NAV_END_TXOP BIT(5) // 1:Nav protect all txop, 0:Nav protect to next pkt. -#define AC_INBCN_HOLD BIT(4) // bit=1, HI queue will be sent first, and then AC queue will be sent. -#define MGTQ_TXOP_EN BIT(3) // bit=1, MGTQ may sent packets by using ACQ TXOP. -#define MGTQ_RTSMF_HOLD BIT(2) // bit=1, MGTQ will be hold until RTS or MF transaction finished. -#define HIQ_RTSMF_HOLD BIT(1) // bit=1, HIQ will be hold until RTS or MF transaction finished. -#define BCN_RTSMF_HOLD BIT(0) // bit=1, BCNQ will be hold until RTS or MF transaction finished. - -//---------------------------------------------------------------------------- -// 8192C TXPAUSE bits (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- -#define STOP_BCN BIT(6) // Stop BCNQ Queue. -#define STOP_HI BIT(5) // Stop High Queue. -#define STOP_MGT BIT(4) // Stop Management Queue. -#define STOP_BK BIT(3) // Stop BK Queue. -#define STOP_BE BIT(2) // Stop BE Queue. -#define STOP_VI BIT(1) // Stop VI Queue. -#define STOP_VO BIT(0) // Stop VO Queue. - -//---------------------------------------------------------------------------- -// 8192C DIS_TXREQ_CLR bits (Offset 0x523, 8 bits) -//---------------------------------------------------------------------------- -#define DIS_TXREQ_CLR_BCN BIT(7) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_HI BIT(5) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_MGQ BIT(4) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_VO BIT(3) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_VI BIT(2) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_BE BIT(1) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. -#define DIS_TXREQ_CLR_BK BIT(0) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. - -//---------------------------------------------------------------------------- -// 8192C RD_CTRL bits (Offset 0x524-525, 16 bits) -//---------------------------------------------------------------------------- -#define HIQ_NO_LMT_EN BIT(12) -#define EDCCA_MSK_CNTDWN BIT(11) // 1: disable, 0: enable, EDCCA count down. -#define DIS_TXOP_CFE BIT(10) // Disable TXOP_CFE function. -#define DIS_LSIG_CFE BIT(9) // Disable LSIG_TXOP CF-END function. -#define DIS_STBC_CFE BIT(8) // Disable STBC CF-END function. -#define BKQ_RD_INIT_EN BIT(7) // -#define BEQ_RD_INIT_EN BIT(6) // -#define VIQ_RD_INIT_EN BIT(5) // -#define VOQ_RD_INIT_EN BIT(4) // -#define BKQ_RD_RESP_EN BIT(3) // -#define BEQ_RD_RESP_EN BIT(2) // -#define VIQ_RD_RESP_EN BIT(1) // -#define VOQ_RD_RESP_EN BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C TBTT_PROHIBIT bits (Offset 0x540-541, 16 bits) -//---------------------------------------------------------------------------- -#define TBTT_HOLD_TIME_SHIFT 8 // TBTT_prohibit_hold, unit is 32 us. -#define TBTT_HOLD_TIME_Mask 0xFFFFFF -#define TBTT_PROHIBIT_SETUP_SHIFT 0 // TBTT_prohibit_setup, unit is 32us. -#define TBTT_PROHIBIT_SETUP_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C BCN_CTRL bits (Offset 0x550, 8 bits) -//---------------------------------------------------------------------------- - -#define DIS_SUB_STATE BIT(4) -#define DIS_SUB_STATE_N BIT(1) -#define DIS_TSF_UPDATE BIT(5) -#define DIS_TSF_UPDATE_N BIT(4) -#define DIS_ATIM BIT(0) - - -#define BCN0_AUTO_SYNC BIT(5) // When this bit is set, TSFTR will update the timestamp in Beacon matched BSSID. -#define DIS_TSF_UPT BIT(4) // 92D_REG, When this bit is set, tsf will not update -#define EN_BCN_FUNCTION BIT(3) // bit=1, TSF and other beacon related functions are then enabled. -#define EN_TXBCN_RPT BIT(2) // -#define EN_MBSSID BIT(1) // -#define PBCNQSEL BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C USTIME_TSF bits (Offset 0x551, 8 bits) -//---------------------------------------------------------------------------- -#define USTIME_TSF_TIME_SHIFT 0 // Set the microsecond time unit used by MAC TSF clock. -#define USTIME_TSF_TIME_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C MBID_NUM bits (Offset 0x552, 8 bits) -//---------------------------------------------------------------------------- -#define MBID_BCN_NUM_SHIFT 0 // num of virtual interface num excluding the root. -#define MBID_BCN_NUM_Mask 0x07 - -//---------------------------------------------------------------------------- -// 8192C MBSSID_BCN_SPACE bits (Offset 0x554-557, 32 bits) -//---------------------------------------------------------------------------- -#define BCN_SPACE2_SHIFT 16 // -#define BCN_SPACE2_Mask 0x0FFFF -#define BCN_SPACE1_SHIFT 0 // -#define BCN_SPACE1_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C ACMHWCTRL bits (Offset 0x5C0, 8 bits) -//---------------------------------------------------------------------------- -#define VOQ_ACM_STATUS BIT(6) // indicates if the used_time >= admitted_time of AC VO when HW ACM. -#define VIQ_ACM_STATUS BIT(5) // indicates if the used_time >= admitted_time of AC VI when HW ACM. -#define BEQ_ACM_STATUS BIT(4) // indicates if the used_time >= admitted_time of AC BE when HW ACM. -#define VOQ_ACM_EN BIT(3) // enable ACM of VO queue. -#define VIQ_ACM_EN BIT(2) // enable ACM of VI queue. -#define BEQ_ACM_EN BIT(1) // enable ACM of BE queue. -#define ACMHWEN BIT(0) // enable hardware to take control of ACM. - -//---------------------------------------------------------------------------- -// 8192C ACMRSTCTRL bits (Offset 0x5C1, 8 bits) -//---------------------------------------------------------------------------- -#define VO_ACM_RST_USED_TIME BIT(2) // HwEn enabled, sw set this to inform hw to reset used_time. -#define BE_ACM_RST_USED_TIME BIT(1) // HwEn enabled, sw set this to inform hw to reset used_time. -#define VI_ACM_RST_USED_TIME BIT(0) // HwEn enabled, sw set this to inform hw to reset used_time. - - -// -// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) -// -//---------------------------------------------------------------------------- -// 8192C APSD_CTRL bits (Offset 0x600, 8 bits) -//---------------------------------------------------------------------------- -#define APSDOFF_STATUS BIT(7) // -#define APSDOFF BIT(6) // bit=1, MAC issue sleep signal to disable BB/AFE/RF TRX function. - -//---------------------------------------------------------------------------- -// 8192C BWOPMODE bits (Offset 0x603, 8 bits) -//---------------------------------------------------------------------------- -#define BW_20M BIT(2) // bit=1 indicate operating in 20Mhz bandwidth. - -//---------------------------------------------------------------------------- -// 8192C TCR bits (Offset 0x604-607, 32 bits) -//---------------------------------------------------------------------------- -#define TSFT_CMP_SHIFT 16 // TSFT insertion compensation value. -#define TSFT_CMP_Mask 0x0FF -#define WMAC_TCR_ERRSTEN3 BIT(15) // 92D_REG, Use phytxend_ps to reset mactx state machine -#define WMAC_TCR_ERRSTEN2 BIT(14) // 92D_REG, If txd fifo underflow when txtype is cmpba, reset mactx state machine -#define WMAC_TCR_ERRSTEN1 BIT(13) // 92D_REG, If txd fifo underflow, reset mactx state machine -#define WMAC_TCR_ERRSTEN0 BIT(12) // 92D_REG, Phytxend_ps comes but mactx still active, reset mactx state machine -#define WMAC_TCR_TXSK_PERPKT BIT(11) // 92D_REG, Serche key for each mpdu -#define ICV BIT(10) // Integrity Check Value. -#define CFE_FORM BIT(9) // CF-End Frame Format. -#define CRC BIT(8) // Append 32-bit Cyclic Redundancy Check. -#define PWRBIT_OW_EN BIT(7) // bit=1, MAC overwrite pwr bit according to PWR_ST for data frame. -#define PWR_ST BIT(6) // MAC will overwrite pwr bit accroding to PWR_ST for data frame. -#define PAD_SEL BIT(2) // AMPDU Padding pattern selection. -#define DIS_GCLK BIT(1) // Disable MACTX clock gating control. -#define TSFRST BIT(0) // Reset TSF Timer to zero. - -//---------------------------------------------------------------------------- -// 8192C RCR bits (Offset 0x608-60B, 32 bits) -//---------------------------------------------------------------------------- -#define RCR_APP_FCS BIT(31) // wmac RX will append FCS after payload. -#define RCR_APP_MIC BIT(30) // bit=1, MACRX will retain the MIC at the bottom of the packet. -#define RCR_APP_ICV BIT(29) // bit=1, MACRX will retain the ICV at the bottom of the packet. -#define RCR_APP_PHYSTS BIT(28) // Append RXFF0 PHY Status Enable. -#define RCR_APP_BASSN BIT(27) // Append SSN of previous TXBA Enable. -#define RCR_MBID_EN BIT(24) // Enable Multiple BssId. -#define RCR_LSIGEN BIT(23) // Enable LSIG TXOP Protection function. -#define RCR_MFBEN BIT(22) // Enable immediate MCS Feedback function. -#define RCR_BM_DATA_EN BIT(17) // BM_DATA_EN. -#define RCR_UC_DATA_EN BIT(16) // Unicast data packet interrupt enable. -#define RCR_HTC_LOC_CTRL BIT(14) // 1: HTC -> MFC, 0: MFC-> HTC. -#define RCR_AMF BIT(13) // Accept Management Frame. -#define RCR_ACF BIT(12) // Accept Control Frame. -#define RCR_ADF BIT(11) // Accept Data Frame. -#define RCR_AICV BIT(9) // Accept Integrity Check Value Error packets. -#define RCR_ACRC32 BIT(8) // Accept CRC32 Error packets. - -#define RCR_CBSSID_ADHOC (BIT(6)|BIT(7)) // Check BSSID. -#define RCR_CBSSID BIT(6) // Check BSSID. -#define RCR_APWRMGT BIT(5) // Accept Power Management Packet. -#define RCR_ADD3 BIT(4) // Accept Address 3 Match Packets. -#define RCR_AB BIT(3) // Accept Broadcast packets. -#define RCR_AM BIT(2) // Accept Multicast packets. -#define RCR_APM BIT(1) // Accept Physical Match packets. -#define RCR_AAP BIT(0) // Accept Destination Address packets. - -//---------------------------------------------------------------------------- -// 8192C RX_PKT_LIMIT bits (Offset 0x60C, 8 bits) -//---------------------------------------------------------------------------- -#define RXPKTLMT_SHIFT 0 // RX PKT Upper Limit. -#define RXPKTLMT_Mask 0x03F - -// MACID Setting Register. (Offset 0x610 - 0x62Fh) -//---------------------------------------------------------------------------- -// 8192C MBIDCAMCFG bits (Offset 0x628-62F, 64 bits) -//---------------------------------------------------------------------------- -#define MBIDCAM_POLL BIT(31) // Pooling bit. -#define MBIDWRITE_EN BIT(30) // Write Enable. -#define MBIDCAM_ADDR_SHIFT 24 // CAM Address. -#define MBIDCAM_ADDR_Mask 0x01F -#define MBIDCAM_VALID BIT(23) // CAM Valid bit. - -// MACID Setting Register. (Offset 0x610 - 0x62Fh) - -// Timing Control Register. (Offset 0x630 - 0x64Fh) -//---------------------------------------------------------------------------- -// 8192C SPEC_SIFS bits (Offset 0x63A-63B, 16 bits) -//---------------------------------------------------------------------------- -#define SPEC_SIFS_OFDM_SHIFT 8 // SIFS value for duration calculation. -#define SPEC_SIFS_OFDM_Mask 0x0FF -#define SPEC_SIFS_CCK_SHIFT 0 // SIFS value for duration calculation. -#define SPEC_SIFS_CCK_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C RESP_SIFS_CCK bits (Offset 0x63C-63D, 16 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8192C RESP_SIFS_OFDM bits (Offset 0x63E-63F, 16 bits) -//---------------------------------------------------------------------------- -#define SIFS_R2T_SHIFT 8 // SIFS time required for any immediate response. -#define SIFS_R2T_Mask 0x0FF -#define SIFS_T2T_SHIFT 0 // SIFS time required for consecutive TX events. -#define SIFS_T2T_Mask 0x0FF - -// Timing Control Register. (Offset 0x630 - 0x64Fh) - -// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) -//---------------------------------------------------------------------------- -// 8192C NAV_CTRL bits (Offset 0x650-651, 16 bits) -//---------------------------------------------------------------------------- -#define NAV_UPPER_SHIFT 8 // When NAV update is beyond this, then update is aborted. -#define NAV_UPPER_Mask 0x0FF -#define RTSRST_SHIFT 0 // RTS NAV Reset Time. -#define RTSRST_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C BACAMCMD bits (Offset 0x654-657, 32 bits) -//---------------------------------------------------------------------------- -#define BACAM_POLL BIT(31) // Polling bit BA CAM. -#define BACAM_RST BIT(17) // 1 to reset BA CAM. HW set invalid bit for all entries. -#define BACAM_RW BIT(16) // 1=Write, 0=Read. -#define BACAM_ADDR_SHIFT 0 // BA CAM address. Memory is double-word access. -#define BACAM_ADDR_Mask 0x03F - -//---------------------------------------------------------------------------- -// 8192C LBDLY bits (Offset 0x660, 8 bits) -//---------------------------------------------------------------------------- -#define LBDLY_LMT_SHIFT 0 // Loopback Delay. -#define LBDLY_LMT_Mask 0x01F - -//---------------------------------------------------------------------------- -// 8192C FWDLY bits (Offset 0x661, 8 bits) -//---------------------------------------------------------------------------- -#define FWDLY_LMT_SHIFT 0 // Firmware Delay. -#define FWDLY_LMT_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C RXERR_RPT bits (Offset 0x664-667, 32 bits) -//---------------------------------------------------------------------------- -#define RXERR_RPT_SEL_SHIFT 28 // -#define RXERR_RPT_SEL_Mask 0x0F -#define RXERR_RPT_RST BIT(27) // Write "one" to set the counter to zero. -#define RPT_COUNTER_SHIFT 0 // reported value corresponding to Report type selected. -#define RPT_COUNTER_Mask 0x0FFFFF - -//---------------------------------------------------------------------------- -// 8192C WMAC_TRXPTCL_CTL bits (Offset 0x668-66F, 64 bits) -//---------------------------------------------------------------------------- -#define ACKBA_TYPSEL_SHIFT 28 // Determine response type for RX BA. -#define ACKBA_TYPSEL_Mask 0x0F -#define ACKBA_ACKPCHK_SHIFT 24 // -#define ACKBA_ACKPCHK_Mask 0x0F -#define ACKBAR_ACKPCHK_SHIFT 12 // -#define ACKBAR_ACKPCHK_Mask 0x0F -#define DIS_TXBA_AMPDUFCSERR BIT(4) // Disable to send BA for responding RX AMPDU with FCS error subframe. -#define DIS_TXBA_RXBARINFULL BIT(3) // Disable send BA for responding RX control wrapper BAR dropped by rxpkbuffer full. -#define DIS_TXCFE_INFULL BIT(2) // Disable send CFE for responding RX control wrapper CFE dropped by rxpktbuffer full. -#define DIS_TXCTS_INFULL BIT(1) // Disable send CTS for responding RX control wrapper RTS dropped by rxpktbuffer full. -#define EN_TXCTS_INTXOP BIT(0) // Enable send CTS for responding RX RTS during our TXOP period. - -#define RESP_CHNBUSY_SHIFT 20 // Define channel busy condition in responder to determine RX busy. -#define RESP_CHNBUSY_Mask 0x03 -#define RESP_DCTS_EN BIT(19) // Enable responder send dual CTS for responding Rx RTS. -#define RESP_DCFE_EN BIT(18) // Enable responder send dual CF-END for responding RX CF-END. -#define RESP_SPLCPEN BIT(17) // Enable responder send SPLCP CCK rsp for acknowledging Rx SPLCP CCK. -#define RESP_SGIEN BIT(16) // Enable responder send SGI HT-OFDM rsp for acknowledging Rx SGI HT-OFDM pkt. - -// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) - -// Security Control Register. (Offset 0x670 - 0x68Fh) -//---------------------------------------------------------------------------- -// 8192C CAMCMD bits (Offset 0x670-673, 32 bits) -//---------------------------------------------------------------------------- -#define SECCAM_POLL BIT(31) // Security CAM Polling. -#define SECCAM_CLR BIT(30) // Set 1 to clear all valid bits in CAM. -#define MFBCAM_CLR BIT(29) // Write 1 to clear all MFB value in CAM. -#define SECCAM_WE BIT(16) // Security CAM Write Enable. -#define SECCAM_ADDR_SHIFT 0 // Security CAM Address Offset. -#define SECCAM_ADDR_Mask 0x0FF - -//---------------------------------------------------------------------------- -// 8192C CAMDBG bits (Offset 0x67C-67F, 32 bits) -//---------------------------------------------------------------------------- -#define SECCAM_INFO BIT(31) // Select TX/RX CAM Information. -#define SEC_KEYFOUND BIT(30) // Security Key Found in CAM. -#define SEC_CONFIG_SHIFT 24 // Security Configuration. -#define SEC_CONFIG_Mask 0x03F -#define SEC_KEYCONTENT_SHIFT 0 // Security CAM Address Offset. -#define SEC_KEYCONTENT_Mask 0x0FFFFFF - -//---------------------------------------------------------------------------- -// 8192C SECCFG bits (Offset 0x680, 8 bits) -//---------------------------------------------------------------------------- -#define CHK_KEYID BIT(8) // Key search engine need to check if key ID matched -#define RXBCUSEDK BIT(7) // Force RX Broadcast packets Use Default Key -#define TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key -#define NOSKMC BIT(5) // No Key Search for Multicast. -#define SKBYA2 BIT(4) // Search Key by A2. -#define RXDEC BIT(3) // Enable Rx Decryption. -#define TXENC BIT(2) // Enable Tx Encryption. -#define RXUSEDK BIT(1) // Force Rx Use Default Key. -#define TXUSEDK BIT(0) // Force Tx Use Default Key. - -// Security Control Register. (Offset 0x670 - 0x68Fh) - -// Power Save Control Register. (Offset 0x690 - 0x69Fh) -//---------------------------------------------------------------------------- -// 8192C WOW_CTRL bits (Offset 0x690, 8 bits) -//---------------------------------------------------------------------------- -#define FORCE_WAKEUP BIT(7) // Let Wakeup PIN be controllable by FW/Driver. -#define UWF BIT(3) // Unicast Wakeup Frame. -#define MAGIC BIT(2) // Magic Packet. -#define WOWEN BIT(1) // WoW function on or off. -#define PMEN BIT(0) // Power Management Enable. - -//---------------------------------------------------------------------------- -// 8192C PSSTATUS bits (Offset 0x691, 8 bits) -//---------------------------------------------------------------------------- -#define PSSTATUS_SEL_SHIFT 0 // Indicate the present power save mode. -#define PSSTATUS_SEL_Mask 0x0F - -//---------------------------------------------------------------------------- -// 8192C PS_RX_INFO bits (Offset 0x692, 8 bits) -//---------------------------------------------------------------------------- -#define RXCTRLIN0 BIT(4) // set to 1 if NIC received control frame with correct BSSID and DA. -#define RXMGTIN0 BIT(3) // set to 1 if NIC received management frame with correct BSSID and DA. -#define RXDATAIN2 BIT(2) // set to 1 if NIC received data frame with correct BSSID and DA. -#define RXDATAIN1 BIT(1) // set to 1 if NIC received data frame with correct BSSID and DA. -#define RXDATAIN0 BIT(0) // set to 1 if NIC received data frame with correct BSSID and DA. - -//---------------------------------------------------------------------------- -// 8192C LPNAV_CTRL bits (Offset 0x694-697, 32 bits) -//---------------------------------------------------------------------------- -#define LPNAV_EN BIT(31) // Low Power NAV Mode Enable. -#define LPNAV_EARLY_SHIFT 16 // in LPNAV mode, MAC will recall BB & RF into RX idle mode. -#define LPNAV_EARLY_Mask 0x07FFF -#define LPNAV_TH_SHIFT 0 // When NAV received is greater than this, then MAC enters LPNAV mode. -#define LPNAV_TH_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C WKFMCAM_CMD bits (Offset 0x698-69B, 32 bits) -//---------------------------------------------------------------------------- -#define WKFCAM_POLL BIT(31) // Wakeup Mask CAM Polling. -#define WKFCAM_CLR BIT(30) // Set to one to clear all valid bits in CAM. After reset will self clear to 0. -#define WKFCAM_WE BIT(16) // Wakeup Mask CAM Write Enable. -#define WKFCAM_ADDR_SHIFT 0 // Wakeup Mask CAM Address Offset. -#define WKFCAM_ADDR_Mask 0x03F - -// Power Save Control Register. (Offset 0x690 - 0x69Fh) - -// General Purpose Register. (Offset 0x6A0 - 0x6AFh) -//---------------------------------------------------------------------------- -// 8192C RXFLTMAP0 bits (Offset 0x6A0-6A1, 16 bits) -//---------------------------------------------------------------------------- -#define MGTFLTD_EN BIT(13) // -#define MGTFLTC_EN BIT(12) // -#define MGTFLTB_EN BIT(11) // -#define MGTFLTA_EN BIT(10) // -#define MGTFLT9_EN BIT(9) // -#define MGTFLT8_EN BIT(8) // -#define MGTFLT5_EN BIT(5) // -#define MGTFLT4_EN BIT(4) // -#define MGTFLT3_EN BIT(3) // -#define MGTFLT2_EN BIT(2) // -#define MGTFLT1_EN BIT(1) // -#define MGTFLT0_EN BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C RXFLTMAP1 bits (Offset 0x6A2-6A3, 16 bits) -//---------------------------------------------------------------------------- -#define CTRLFLTF_EN BIT(15) // -#define CTRLFLTE_EN BIT(14) // -#define CTRLFLTD_EN BIT(13) // -#define CTRLFLTC_EN BIT(12) // -#define CTRLFLTB_EN BIT(11) // -#define CTRLFLTA_EN BIT(10) // -#define CTRLFLT9_EN BIT(9) // -#define CTRLFLT8_EN BIT(8) // -#define CTRLFLT7_EN BIT(7) // -#define CTRLFLT6_EN BIT(6) // - -//---------------------------------------------------------------------------- -// 8192C RXFLTMAP2 bits (Offset 0x6A4-6A5, 16 bits) -//---------------------------------------------------------------------------- -#define DATAFLTF_EN BIT(15) // -#define DATAFLTE_EN BIT(14) // -#define DATAFLTD_EN BIT(13) // -#define DATAFLTC_EN BIT(12) // -#define DATAFLTB_EN BIT(11) // -#define DATAFLTA_EN BIT(10) // -#define DATAFLT9_EN BIT(9) // -#define DATAFLT8_EN BIT(8) // -#define DATAFLT7_EN BIT(7) // -#define DATAFLT6_EN BIT(6) // -#define DATAFLT5_EN BIT(5) // -#define DATAFLT4_EN BIT(4) // -#define DATAFLT3_EN BIT(3) // -#define DATAFLT2_EN BIT(2) // -#define DATAFLT1_EN BIT(1) // -#define DATAFLT0_EN BIT(0) // - -//---------------------------------------------------------------------------- -// 8192C BCN_PSR_RPT bits (Offset 0x6A8-6AB, 32 bits) -//---------------------------------------------------------------------------- -#define DTIM_CNT_SHIFT 24 // -#define DTIM_CNT_Mask 0x0FF -#define DTIM_PERIOD_SHIFT 16 // -#define DTIM_PERIOD_Mask 0x0FF -#define DTIM BIT(15) // -#define TIM BIT(14) // -#define PS_AID_SHIFT 0 // -#define PS_AID_Mask 0x07FF - -//---------------------------------------------------------------------------- -// 8192C CALB32K_CTRL bits (Offset 0x6AC-6AF, 32 bits) -//---------------------------------------------------------------------------- -#define CALB32K_POLL BIT(31) // -#define CALB32K_DONE BIT(30) // -#define CAL_TIME_SHIFT 20 // Calibration time. -#define CAL_TIME_Mask 0x03FF -#define CAL_REPORT_SHIFT 0 // -#define CAL_REPORT_Mask 0x0FFFFF - -// General Purpose Register. (Offset 0x6A0 - 0x6AFh) - -//---------------------------------------------------------------------------- -// 8192C BT_COEX_TABLE bits (Offset 0x6C0-6CF, 128 bits) -//---------------------------------------------------------------------------- -#define PRI_MASK_RX_RSP BIT(30) // Priority Mask for Rx Response Packet. -#define PRI_MASK_RX_OFDM BIT(29) // Priority Mask for Rx OFDM. -#define PRI_MASK_RX_CCK BIT(28) // Priority Mask for Rx CCK. -#define PRI_MASK_TX_Q_SHIFT 21 // Priority Mask for Tx Queue. -#define PRI_MASK_TX_Q_Mask 0x07F -#define PRI_MASK_TX_NAV_SHIFT 13 // Priority Mask for Tx NAV. -#define PRI_MASK_TX_NAV_Mask 0x0FF -#define PRI_MASK_TX_CCK BIT(12) // Priority Mask for Tx CCK. -#define PRI_MASK_TX_OFDM BIT(11) // Priority Mask for Tx OFDM. -#define PRI_MASK_TX_RTY BIT(10) // Priority Mask for Tx Retry packet. -#define PRI_MASK_TX_NUM_SHIFT 6 // Priority Mask for Tx packet num. -#define PRI_MASK_TX_NUM_Mask 0x0F -#define PRI_MASK_TX_TYPE_SHIFT 2 // Priority Mask for Tx packet type. -#define PRI_MASK_TX_TYPE_Mask 0x0F -#define C_OOB BIT(1) // out of band indication (0:in band,1:out of band). -#define ANT_SEL BIT(0) // single or dual antenna selection (0:single,1:dual). - -#define BREAK_TABLE2_SHIFT 16 // Table used to break WLAN activity. -#define BREAK_TABLE2_Mask 0x0FFFF -#define BREAK_TABLE1_SHIFT 0 // Table used to break BT activity. -#define BREAK_TABLE1_Mask 0x0FFFF - -//---------------------------------------------------------------------------- -// 8192C WMAC_RESP_TXINFO bits (Offset 0x6D8-6DA, 24 bits) -//---------------------------------------------------------------------------- -#define RESP_TXAGC_B_SHIFT 13 // -#define RESP_TXAGC_B_Mask 0x01F -#define RESP_TXAGC_A_SHIFT 8 // -#define RESP_TXAGC_A_Mask 0x01F -#define RESP_ANTSEL_B BIT(7) // -#define RESP_ANTSEL_A BIT(6) // -#define RESP_TXANT_CCK_SHIFT 4 // -#define RESP_TXANT_CCK_Mask 0x03 -#define RESP_TXANT_L_SHIFT 2 // -#define RESP_TXANT_L_Mask 0x03 -#define RESP_TXANT_HT_SHIFT 0 // -#define RESP_TXANT_HT_Mask 0x03 - -//======================================================== -// General definitions -//======================================================== - -#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- - -//2 USB Information (0xFE17) -#define USB_IS_HIGH_SPEED 0 -#define USB_IS_FULL_SPEED 1 -#define USB_SPEED_MASK BIT(5) - -#define USB_NORMAL_SIE_EP_MASK 0xF -#define USB_NORMAL_SIE_EP_SHIFT 4 - -#define USB_TEST_EP_MASK 0x30 -#define USB_TEST_EP_SHIFT 4 - -//2 Special Option -#define USB_AGG_EN BIT(3) - - -//2REG_C2HEVT_CLEAR -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - -/* -//---------------------------------------------------------------------------- -// 8192C Rate Definition -//---------------------------------------------------------------------------- -//CCK -#define RATR_1M 0x00000001 -#define RATR_2M 0x00000002 -#define RATR_55M 0x00000004 -#define RATR_11M 0x00000008 -//OFDM -#define RATR_6M 0x00000010 -#define RATR_9M 0x00000020 -#define RATR_12M 0x00000040 -#define RATR_18M 0x00000080 -#define RATR_24M 0x00000100 -#define RATR_36M 0x00000200 -#define RATR_48M 0x00000400 -#define RATR_54M 0x00000800 -//MCS 1 Spatial Stream -#define RATR_MCS0 0x00001000 -#define RATR_MCS1 0x00002000 -#define RATR_MCS2 0x00004000 -#define RATR_MCS3 0x00008000 -#define RATR_MCS4 0x00010000 -#define RATR_MCS5 0x00020000 -#define RATR_MCS6 0x00040000 -#define RATR_MCS7 0x00080000 -//MCS 2 Spatial Stream -#define RATR_MCS8 0x00100000 -#define RATR_MCS9 0x00200000 -#define RATR_MCS10 0x00400000 -#define RATR_MCS11 0x00800000 -#define RATR_MCS12 0x01000000 -#define RATR_MCS13 0x02000000 -#define RATR_MCS14 0x04000000 -#define RATR_MCS15 0x08000000 -// ALL CCK Rate -#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M -#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ - RATR_36M|RATR_48M|RATR_54M -#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ - RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 -#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ - RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 -*/ - -#endif //WLAN_HAL_INTERNAL_USED - -#endif // #ifndef __INC_HAL8192SEREG_H - +/* + * Header file of 8192C register + * + * $Id: 8192c_reg.h,v 1.7.2.2 2010/09/20 09:00:10 button Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _8192C_REG_H_ +#define _8192C_REG_H_ + +#ifndef WLAN_HAL_INTERNAL_USED + + +//============================================================ +// 8192C Regsiter offset definition +//============================================================ + + +// +// MAC register 0x000 - 0x6AFh +// 1. System Configure Register. (Offset 0x000 - 0x0FFh) +// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) +// General Purpose Timer. (Offset 0x150 - 0x16Fh) +// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) +// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) +// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) +// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) +// MACID Setting Register. (Offset 0x610 - 0x62Fh) +// Timing Control Register. (Offset 0x630 - 0x64Fh) +// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) +// Security Control Register. (Offset 0x670 - 0x68Fh) +// Power Save Control Register. (Offset 0x690 - 0x69Fh) +// General Purpose Register. (Offset 0x6A0 - 0x6AFh) +// + + +// +// 1. System Configure Register. (Offset 0x000 - 0x0FFh) +// +#define SYS_ISO_CTRL 0x000 // System Isolation Interface Control. +#define SYS_FUNC_EN 0x002 // System Function Enable. +#define APS_FSMCO 0x004 // Auto Power Sequence Control/Option. +#define SYS_CLKR 0x008 // System Clock. +#define CR9346 0x00A // 93C46 (93C56) Command. +#define EE_VPD 0x00C // EEPROM VPD Data. +#define AFE_MISC 0x010 // AFE Misc. +#define SPS0_CTRL 0x011 // Switching Power Supply 0 Control. +#define SPS_OCP_CFG 0x018 // SPS Over Current Protection Configuration. +#define RSV_CTRL0 0x01C // Reserved Control. +#define RF_CTRL 0x01F // RF Block Control. +#define LDOA15_CTRL 0x020 // V15 Digital LDO Control. +#define LDOV12D_CTRL 0x021 // V12 Digital LDO Control. +#define LDOHCI12_CTRL 0x022 // V12 Digital LDO Control. +#define LPLDO_CTRL 0x023 // Low Power LDO Control. +#define AFE_XTAL_CTRL 0x024 // AFE Crystal Control. +#define AFE_PLL_CTRL 0x028 // AFE_PLL_CTRL Enable. +#define RSV_CTRL1 0x02C // Reserved Control. +#define EFUSE_CTRL 0x030 // E-Fuse Control. +#define EFUSE_TEST 0x034 // E-Fuse Test Control. +#define PWR_DATA 0x038 // Power on Data. +#define CAL_TIMER 0x03C // Hardware Calibration Timer. +#define ACLK_MON 0x03E // Analog Clock Monitor. +#define GPIO_MUXCFG 0x040 // GPIO_MUX Configuration. +#define GPIO_PIN_CTRL 0x044 // GPIO[7:0] PIN Control. +#define GPIO_INTM 0x048 // GPIO Interrupt Monitor Register. +#define LEDCFG 0x04C // System PINMUX Configuration. +#define FSIMR 0x050 // Firmware System Interrupt Mask. +#define FSISR 0x054 // Firmware System Interrupt Status. +#define HSIMR 0x058 // Host System Interrupt Mask. +#define HSISR 0x05C // Host System Interrupt Status. + +#define MCUFWDL 0x080 // MCU Firmware Down Load Control. +#define MCUTSTCFG 0x084 // MCU Firmware Test Configuration. +#define MCUDMSG_I 0x088 // MCU Firmware Debug Message. +#define MCUDMSG_II 0x08C // MCU Firmware Debug Message. + +#define BIST_CTRL 0x0D0 // BIST/SCAN CONTROL +#define C_BIST_RPT 0x0D4 // BIST Report +#define BIST_ROM_RPT 0x0D8 // BIST ROM Report +#define USB_SIE_INTF 0x0E0 // USB SIE Access Interface +#define PCIE_MIO_INTF 0x0E4 // PCIE MIO Access Interface +#define PCIE_MIO_INTD 0x0E8 // PCIE MIO Access Interface DATA. +#define HPON_FSM 0x0EC // Power On FSM Monitor/Control. +#define SYS_CFG 0x0F0 // System Configuration Status + + +// +// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) +// +#define CR 0x100 // Command Register. +#define PBP 0x104 // Packet Buffer Page. +#define TRXDMA_CTRL 0x10C // TRXDMA Control. +#define TRXFF_BNDY 0x114 // TX/RX FIFO Boundary +#define TRXFF_STATUS 0x118 // PKTFF Status +#define RXFF_PTR 0x11C // RXFF Write/Read Pointer +#define HIMR 0x120 // Host Interrupt Mask. +#define HISR 0x124 // Host Interrupt Status. +#define HIMRE 0x128 // Host Interrupt Mask Extension. +#define HISRE 0x12C // Host Interrupt Status Extension. +#define CPWM 0x12F // Current Power Mode. +#define FWIMR 0x130 // Firmware WLAN Interrupt Mask. +#define FWISR 0x134 // Firmware WLAN Interrupt Status. +#define FTIMR 0x138 // Firmware Timer Interrupt Mask. +#define FTISR 0x13C // Firmware Timer Interrupt Status. +#define PKTBUF_DBG_CTRL 0x140 // TX/RX Packet Buffer Debug Control. +#define PKTBUF_DBG_DATA_L 0x144 // TX/RX Packet Buffer Debug Data. +#define PKTBUF_DBG_DATA_H 0x148 // TX/RX Packet Buffer Debug Data. +// General Purpose Timer. (Offset 0x150 - 0x16Fh) +#define TC0_CTRL 0x150 // Timer/Counter 0 Control. +#define TC1_CTRL 0x154 // Timer/Counter 1 Control. +#define TC2_CTRL 0x158 // Timer/Counter 2 Control. +#define TC3_CTRL 0x15C // Timer/Counter 3 Control. +#define TC4_CTRL 0x160 // Timer/Counter 4 Control. +#define TCUNIT_BASE 0x164 // Timer/Counter Unit Base. +// General Purpose Timer. (Offset 0x150 - 0x16Fh) +#define MBIST_START 0x174 // MACTOP BIST START Pulse. +#define MBIST_DONE 0x178 // MACTOP BIST DONE. +#define MBIST_FAIL 0x17C // MACTOP BIST FAIL. + +#define C2H_SYNC_BYTE 0x1AF // 8051 set to 0xFF, Driver set to 0x0 after read C2H content +#define MCUTST_I 0x1C0 // MCU Firmware TST-I. +#define MCUTST_II 0x1C4 // MCU Firmware TST-II. +#define MCU_UNLOCK 0x01C7 // is used for Unlock MCU infinite-loop +#define FMETHR 0x1C8 // Firmware Message Exchange to Host. +#define HMETFR 0x1CC // Host Message Interrupt to Firmware. +#define HMEBOX_0 0x1D0 // Host Message BOX_0 to Firmware. +#define HMEBOX_1 0x1D4 // Host Message BOX_1 to Firmware. +#define HMEBOX_2 0x1D8 // Host Message BOX_2 to Firmware. +#define HMEBOX_3 0x1DC // Host Message BOX_3 to Firmware. +#define LLT_INI 0x1E0 // LLT Entries Initial Indirect Access Control. +#define BB_ACCEESS_CTRL 0x1E8 // BB Indirect Access Control. +#define BB_ACCESS_DATA 0x1EC // BaseBand Indirect Access Data. +#define MREG_HCIDBG 0x1F0 // MAC REG for HCI debug. +#define MREG_CPUDBG 0x1F4 // MAC REG for CPU debug. + + +// +// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) +// +#define RQPN 0x200 // Reserved Queue Page Number. +#define FIFOPAGE 0x204 // Available FIFO Page Number. +#define TDECTRL 0x208 // Tx DMA Engine Control. +#define TXDMA_OFFSET_CHK 0x20C // TXDMA Offset Check. +#define TXDMA_STATUS 0x210 // TXDMA Status. +#define RQPN_NPQ 0x214 // RQPN for Normal Queue Register + +#define RXDMA_AGG_PG_TH 0x280 // RXDMA AGG PG Threshold. +#define RXPKT_NUM 0x284 // RX Packet Number. +#define RXDMA_STATUS 0x288 // RXDMA Status. + + +// +// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) +// +#define PCIE_CTRL_REG 0x300 // PCIE DMA Control. +#define INT_MIG 0x304 // Interrupt Migration. +#define BCNQ_DESA 0x308 // TX Beacon Descriptor Address. +#define HQ_DESA 0x310 // TX High Queue Descriptor. +#define MGQ_DESA 0x318 // TX Manage Queue Descriptor Address. +#define VOQ_DESA 0x320 // TX VO Queue Descriptor Address. +#define VIQ_DESA 0x328 // TX VI Queue Descriptor Address. +#define BEQ_DESA 0x330 // TX BE Queue Descriptor Address. +#define BKQ_DESA 0x338 // TX BK Queue Descriptor Address. +#define RX_DESA 0x340 // RX Queue Descriptor Address. +#define DBI 0x348 // Backdoor REG for Access Configuration SPACE. +#define MDIO 0x354 // MDIO for Access PCIE PHY. +#define DBG_SEL 0x360 // Debug Selection +#define UART_CTRL 0x364 // UART Control. +#define UART_TX_DESA 0x370 // UART TX Descriptor Address. +#define UART_RX_DESA 0x378 // UART RX Descriptor Address. + + +// +// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) +// +#define VOQ_INFO 0x400 // +#define VIQ_INFO 0x404 // +#define BEQ_INFO 0x408 // +#define BKQ_INFO 0x40C // +#define MGQ_INFO 0x410 // +#define HIQ_INFO 0x414 // +#define BCNQ_INFO 0x418 // +#define TXPKT_EMPTY 0x41B // TXPKTBUF Packet Empty. +#define CPU_MGQ_INFO 0x41C // TXPKTBUF Packet Empty. +#define FWHW_TXQ_CTRL 0x420 // FWHW TX Queue Control. +#define HWSEQ_CTRL 0x423 // HW Sequence Number Control. +#define TXPKTBUF_BCNQ_BDNY 0x424 // BCNQ Boundary. +#define TXPKTBUF_MGQ_BDNY 0x425 // MGQ Boundary. +#define MULTI_BCNQ_EN 0x426 // +#define MULTI_BCNQ_OFFSET 0x427 // +#define SPEC_SIFS_A 0x428 // +#define RL 0x42A // +#define DARFRC 0x430 // Data Auto Rate Fallback Retry Count. +#define RARFRC 0x438 // Response Auto Rate Fallback Retry Count. +#define RRSR 0x440 // Response Rate Set. +#define ARFR0 0x444 // Data Auto Rate Fallback 0. +#define ARFR1 0x448 // Auto Rate Fallback 1. +#define ARFR2 0x44C // Auto Rate Fallback 2. +#define ARFR3 0x450 // Auto Rate Fallback 3. +#define AGGLEN_LMT 0x458 // Aggregation Length. +#define AMPDU_MIN_SPACE 0x45C // AMPDU Min Space. +#define TXPKTBUF_WMAC_LBK_BF_HD 0x45D // LBK Buffer Head Page +#define FAST_EDCA_CTRL 0x460 // Fast EDCA Mode. +#define RD_RESP_PKT_TH 0x463 // RD Responder Packet Threshold. +#define INIRTS_RATE_SEL 0x480 // Initial RTS Rate SEL. +#define INIDATA_RATE_SEL 0x484 // Initial Data Rate SEL. +#define POWER_STATUS 0x4A4 // POWER STATUS. +#define POWER_STAGE1 0x4B4 // POWER STAGE1. +#define POWER_STAGE2 0x4B8 // POWER STAGE2.---------------??? +#define PKT_LIFE_TIME 0x4C0 // PKT LIFT TIME. +#define STBC_SETTING 0x4C4 // STBC. +#define PROT_MODE_CTRL 0x4C8 // PROTECT MODE Control. +#define BAR_MODE_CTRL 0x4CC // BAR MODE Control. +#define RA_TRY_RATE_AGG_LMT 0x4CF // Rate Adaptive Try Rate Aggregation Limit. +#define NQOS_SEQ 0x4DC // Non-QoS SEQ Number. +#define QOS_SEQ 0x4DE // QoS SEQ Number. +#define NEED_CPU_HANDLE 0x4E0 // Need CPU Handle. +#define PTCL_ERR_STATUS 0x4E1 // Protocol Function Error Status. +#define PKT_LOSE_RPT 0x4E2 // PKT Lose Report. +#define Dummy 0x4FC // Dummy. + +#define EDCA_VO_PARA 0x500 // EDCA Parameter. +#define EDCA_VI_PARA 0x504 // EDCA Parameter. +#define EDCA_BE_PARA 0x508 // EDCA Parameter. +#define EDCA_BK_PARA 0x50C // EDCA Parameter. +#define BCNTCFG 0x510 // Beacon Time Configuration. +#define PIFS 0x512 // PIFS. +#define RDG_PIFS 0x513 // RDG PIFS. +#define SIFS_CCK 0x514 // SIFS for CCK. +#define SIFS_OFDM 0x516 // SIFS for OFDM. +#define AGGR_BK_TIME 0x51A // AGGR BREAK TIME. +#define SLOT_TIME 0x51B // Slot Time. +#define TX_PTCL_CTRL 0x520 // TX Protocol Control. +#define TXPAUSE 0x522 // Transmission Pause. +#define DIS_TXREQ_CLR 0x523 // Disable TX Request Clear Function. +#define RD_CTRL 0x524 // RD Control. +#define REG_MBSSID_CTRL 0x526 // MBSSID Control. + +#define TBTT_PROHIBIT 0x540 // TBTT Prohibit. +#define RD_NAV_NXT 0x544 // RD NAV Protect Next Time. +#define NAV_PROT_LEN 0x546 // NAV Protection Length. +#define BCN_CTRL 0x550 // Bcnq Control. +#define BCN_CTRL1 0x551 +#define USTIME_TSF 0x551 // US Time Tuning for TSF. +#define MBID_NUM 0x552 // MBSSID Beacon Number. +#define DUAL_TSF_RST 0x553 +#define MBSSID_BCN_SPACE 0x554 // MBSSID Beacon Space. +#define DRVERLYINT 0x558 // Beacon Driver Early Interrupt. +#define BCNDMATIM 0x559 // BCN DMA and ATIM INT Time.-----------------??? +#define ATIMWND 0x55A // ATIM Window Time. +#define BCN_MAX_ERR 0x55D // BCN MAX ERROR. +#define RXTSF_OFFSET_CCK 0x55E // CCK BCN OFFSET. +#define RXTSF_OFFSET_OFDM 0x55F // OFDM BCN OFFSET. +#define TSFTR 0x560 // TSF Timer. +#define INIT_TSFTR 0x564 // TSF Timer Initial Value. +#define TSFTR1 0x568 // TSF Timer1. +#define PSTIMER 0x580 // PS TIMER and Timeout INT. +#define TIMER0 0x584 // TIMER0 INT. +#define TIMER1 0x588 // TIMER1 INT. +#define ACMHWCTRL 0x5C0 // ACM HW Control. +#define ACMRSTCTRL 0x5C1 // ACM RST. +#define ACMAVG 0x5C2 // ACM Average. +#define VO_ADMTIME 0x5C4 // VO Admission Time. +#define VI_ADMTIME 0x5C6 // VI Admission Time. +#define BE_ADMTIME 0x5C8 // BE Admission Time. +#define EDCA_RANDOM_GEN 0x5CC // EDCA Random Number Generator. +#define C_SCH_TXCMD 0x5D0 // TX_CMD. +#define NOA_PARAM 0x5E0 // P2P NoA Parameter + + +// +// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) +// +#define APSD_CTRL 0x600 // APSD Control. +#define BWOPMODE 0x603 // BW Operation Mode. +#define TCR 0x604 // Transmission Configuration. +#define RCR 0x608 // Receive Configuration. +#define RX_PKT_LIMIT 0x60C // RX Packet Length Limit. +#define RX_DLK_TIME 0x60D // RX Deadlock Time. +#define RX_DRVINFO_SZ 0x60F // RX Driver INFO Size Register. +// MACID Setting Register. (Offset 0x610 - 0x62Fh) +#define MACID 0x610 // MAC ID. +#define BSSIDR 0x618 // BSSID. +#define MAR 0x620 // Multicast Address. +#define MBIDCAMCFG 0x628 // MBSSID CAM Configuration. +// MACID Setting Register. (Offset 0x610 - 0x62Fh) + +// Timing Control Register. (Offset 0x630 - 0x64Fh) +#define USTIME_EDCA 0x638 // US Time Tuning for EDCA. +#define SPEC_SIFS_B 0x63A // Specification SIFS. +#define RESP_SIFS_CCK 0x63C // Response SIFS for CCK. +#define RESP_SIFS_OFDM 0x63E // Response SIFS for OFDM. +#define ACKTO 0x640 // ACK Timeout. +#define CTS2TO 0x641 // CTS2 Timeout. +#define EIFS 0x642 // EIFS. +// Timing Control Register. (Offset 0x630 - 0x64Fh) + +// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) +#define NAV_CTRL 0x650 // NAV Control. +#define BACAMCMD 0x654 // Block ACK CAM Command. +#define BACAMCONTENT 0x658 // Block ACK CAM Content. +#define LBDLY 0x660 // Loopback Delay. +#define FWDLY 0x661 // FW Delay. +#define RXERR_RPT 0x664 // RX Error Report. +#define WMAC_TRXPTCL_CTL 0x668 // WMAC TX/RX Protocol Control. +// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) + +// Security Control Register. (Offset 0x670 - 0x68Fh) +#define CAMCMD 0x670 // CAM Command. +#define CAMWRITE 0x674 // CAM Write. +#define CAMREAD 0x678 // CAM Read. +#define CAMDBG 0x67C // CAM Debug. +#define SECCFG 0x680 // Security Configuration. +// Security Control Register. (Offset 0x670 - 0x68Fh) + +// Power Save Control Register. (Offset 0x690 - 0x69Fh) +#define WOW_CTRL 0x690 // Wake On WLAN Control. +#define PSSTATUS 0x691 // Power Save Status. +#define PS_RX_INFO 0x692 // Power Save RX Information. +#define LPNAV_CTRL 0x694 // Low Power NAV Control. +#define WKFMCAM_CMD 0x698 // Wakeup Frame CAM Command. +#define WKFMCAM_RWD 0x69C // Wakeup Frame Read/Write Data. +// Power Save Control Register. (Offset 0x690 - 0x69Fh) + +// General Purpose Register. (Offset 0x6A0 - 0x6AFh) +#define RXFLTMAP0 0x6A0 // RX Filter Map Group 0. +#define RXFLTMAP1 0x6A2 // RX Filter Map Group 1. +#define RXFLTMAP2 0x6A4 // RX Filter Map Group 2. +#define BCN_PSR_RPT 0x6A8 // Beacon Parser Report. +#define CALB32K_CTRL 0x6AC // Calibration 32K Control. +// General Purpose Register. (Offset 0x6A0 - 0x6AFh) +#define PKT_MON_CTRL 0x6B4 // Packet Monitor Control. +#define BT_COEX_TABLE 0x6C0 // BT-Coexistence Control. +#define WMAC_RESP_TXINFO 0x6D8 // Response TXINFO. + +#define MACID1 0x700 // MAC ID1 Register (Offset 0700h~0705h) +#define BSSIDR1 0x708 + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_VID 0xFE60 +#define REG_USB_PID 0xFE62 +#define REG_USB_OPTIONAL 0xFE64 +#define REG_USB_CHIRP_K 0xFE65 +#define REG_USB_PHY 0xFE66 +#define REG_USB_MAC_ADDR 0xFE70 + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +// For test chip +#define REG_TEST_USB_TXQS 0xFE48 +#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_TEST_SIE_OPTIONAL 0xFE64 +#define REG_TEST_SIE_CHIRP_K 0xFE65 +#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B +#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 + + +// For normal chip +#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 +#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF + + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ + + +// +// 1. System Configure Register. (Offset 0x000 - 0x0FFh) +// +//---------------------------------------------------------------------------- +// 8192C SYS_ISO_CTRL bits (Offset 0x0, 16bit) +//---------------------------------------------------------------------------- +#define PWC_EV12V BIT(15) // Power Cut for eFuse 1.2V, 1: Power valid; 0: Power invalid. +#define PWC_EV25V BIT(14) // Power Cut for eFuse 2.5V, 1: force PSW open; 0: PSW turn on by efuse ctrl. +#define ISO_DIOR BIT(9) // RF Digital I/O to Power On, 1: isolation; 0: attach. +#define ISO_EB2CORE BIT(8) // eFuse cell output to Power On, 1: isolation; 0: attach. +#define ISO_DIOE BIT(7) // Extra Digital I/O to Power On, 1: isolation; 0: attach. +#define ISO_DIOP BIT(6) // PCIe Digital I/O to Power On, 1: isolation; 0: attach. +#define ISO_IP2MAC BIT(5) // Analog Ips to Digital 1.2V, 1: isolation; 0: attach (no used). +#define ISO_PD2CORE BIT(4) // PCIe Digital 1.2V to Power On/Core 1.2V, 1: isolation; 0: attach. +#define ISO_PA2PCIE BIT(3) // PCIe Analog 1.2V to PCIe 3.3V and Digital 1.2V, 1: isolation; 0: attach. +#define ISO_UD2CORE BIT(2) // USB Digital 1.2V to Power On/Core 1.2V, 1: isolation; 0: attach. +#define ISO_UA2USB BIT(1) // USB Analog 1.2V to USB 3.3V and Digital 1.2V, 1: isolation; 0: attach. +#define ISO_MD2PP BIT(0) // MACTOP/BB/PCIe Digital to Power On, 1: isolation; 0: attach. + +//---------------------------------------------------------------------------- +// 8192C SYS_FUNC_EN bits (Offset 0x2, 16bit) +//---------------------------------------------------------------------------- +#define FEN_MREGEN BIT(15) // MAC I/O Registers Enable. +#define FEN_HWPDN BIT(14) // 0 : force All analog blocks shutdown, 1 : keep Analog Blocks alive. +#define FEN_DIO_RF BIT(13) // Enable RF Digital I/O. +#define FEN_ELDR BIT(12) // Enable EEPROM Loader (Loader POR). +#define FEN_DCORE BIT(11) // enable Core Digital (MACTOP POR). +#define FEN_CPUEN BIT(10) // Enable MCU Core (CPU RST). +#define FEN_DIOE BIT(9) // Extra Debug I/O PAD Enable. +#define FEN_PCIED BIT(8) // enable PCIe eMAC. +#define FEN_PPLL BIT(7) // Enable PCIe PHY_PLL (no used). +#define FEN_PCIEA BIT(6) // Enable PCIe PHY. +#define FEN_DIO_PCIE BIT(5) // Enable PCIe Digital I/O (no used). +#define FEN_USBD BIT(4) // Enable USB_SIE. +#define FEN_UPLL BIT(3) // Enable USB PHY_PLL (no used). +#define FEN_USBA BIT(2) // Enable USB PHY. +#define FEN_BB_GLB_RST BIT(1) // When this bit is set to "0", whole BB is reset. When this bit is set, BB is enabled. +#define FEN_BBRSTB BIT(0) // When this bit is set to "0", CCK and OFDM are disabled, + // and clock are gated. Otherwise, CCK and OFDM are enabled. + +//---------------------------------------------------------------------------- +// 8192C APS_FSMCO bits (Offset 0x4, 32bit) +//---------------------------------------------------------------------------- +#define XOP_BTCK BIT(31) // BT Option for never turn off XTAL & SPS. +#define SOP_A8M BIT(30) // Suspend option not to turn analog Clock Mode to 500K Hz, 1: keep 8M, 0: 500K. +#define SOP_RCK BIT(29) // Suspend option not to turn off Hreg Clock (8M/500KHz), 1: clock on, 0: clock off. +#define SOP_AMB BIT(28) // Suspend option not to turn off AFE MB, 1: MB on, 0: MB off. +#define SOP_ABG BIT(27) // Suspend option not to turn off AFE BG, 1: BG on, 0: BG off. +#define SOP_FUSE BIT(26) // Suspend option to turn off Efuse Power or reset Loader, 1: Fuse Pwr Off, 0: Fuse Pwr On. +#define SOP_MRST BIT(25) // Suspend option not to turn off MAC Reset, 1: MAC not reset, 0: MaC reset. +#define SOP_CRST BIT(24) // Susoend option not to turn off 8051 clock, 1: 8051 clock on, 0:8051 clock off. +#define ROP_SPS BIT(22) // Resume option to skip turn On SPS. +#define ROP_PWR BIT(21) // Resume option to skip wait Power Ready, 1: pwr up no delay, 0: wait pwr stable. +#define ROP_ALD BIT(20) // Resume option to skip autoload, 1: not autoload, 0: autoload. +#define OP_SWRST BIT(19) // Option for Software Reset to Reset 8051. +#define SUS_HOST BIT(17) // Power FSM turn to HOST SUS. +#define RDY_MACON BIT(16) // Power FSM turn all power, clock ready for MAC. +#define APDM_HPDN BIT(15) // Auto Power Down to CHIP-off State (Power-Down). +#define APDM_HOST BIT(14) // Auto Power Down to HOST-off State (Card-Disable). +#define APDM_MAC BIT(13) // Auto Power Down to WLAN-Off State (Radio-off). +#define AFSM_PCIE BIT(12) // When this bit is set, PCIE suspends via HW FSM control flow. +#define AFSM_HSUS BIT(11) // 1: Host Suspend through FSM operation; 0: Host Suspend by gated. +#define APFM_RSM BIT(10) // Auto Power On State Machine Resume, auto clear when EE load done. +#define APFM_OFF BIT(9) // Auto FSM to Turn Off, include clock, isolation, power control. +#define APFM_ONMAC BIT(8) // Auto FSM to Turn On, include clock, isolation, power control for MAC only. +#define BT_SUSEN BIT(7) // Enable BT suspend control. +#define RDY_MACDIS BIT(6) // Disable MAC power Ready Output for Test Mode. +#define PDN_PL BIT(5) // PDn polarity control, 0: Low active, 1: High active. +#define PDN_EN BIT(4) // Enable GPIO-11 as Hardware PowerDown/Resume Source. +#define PFM_WOWL BIT(3) // Wake On Lan indicator for H/W FSM. +#define PFM_LDKP BIT(2) // Loader Initial data when re-enable loader. +#define PFM_ALDN BIT(1) // HCI Region load done, inform HCI block. +#define PFM_LDALL BIT(0) // EEPROM autoload 0x00~60h Enable. + +//---------------------------------------------------------------------------- +// 8192C SYS_CLKR bits (Offset 0x8, 16bit) +//---------------------------------------------------------------------------- +#define RING_CLK_EN BIT(13) // HPON Ring Clock Enable, 1: Enable; 0 : Disable. +#define SYS_CLK_EN BIT(12) // MCU Clock Enable, 1: Enable; 0 : Disable. +#define MAC_CLK_EN BIT(11) // MAC Clock Enable, 1: Enable, 0 : Disable. +#define SEC_CLK_EN BIT(10) // SEC Clock Enable, 1 :Enable, 0 :Disable. +#define PHY_SSC_RSTB BIT(9) // PHY SSC Enable (0: Disable, 1: Enable). +#define CLKR_80M_SSC_EN_HOLD_PHS0 BIT(8) // 80M Clock Hold phase 0. +#define CLKR_80M_SSC_DIS BIT(7) // 80M Clock SSC Disable. +#define LOADER_CLK_EN BIT(5) // Loader (eFuse/EEPROM) Clock Enable. +#define MACSLP BIT(4) // MAC SLEEP. +#define ROMD16V_EN BIT(2) // Analog Clock source Divide 16 Mode for EEPROM. +#define ANA8M BIT(1) // Analog Clock source rate, 1: 8M Hz, 0: 500K Hz. +#define CNTD16V_EN BIT(0) // Analog Clock source Divide 16 Mode for Hardware Timer. + +//---------------------------------------------------------------------------- +// 8192C CR9346 bits (Offset 0xA, 16bit) +//---------------------------------------------------------------------------- +#define VPDIDX_SHIFT 8 // VPD mode, EEPROM Index. +#define VPDIDX_Mask 0x0FF +#define EEM1_0_SHIFT 6 // Operating Mode. +#define EEM1_0_Mask 0x03 +#define EEPROM_EN BIT(5) // EEPROM/Efuse is found when set to 1. +#define EERPOMSEL BIT(4) // System EEPROM select (power on selected by GPIO-0). +#define EECS BIT(3) // reflect the state of the EECS. +#define EESK BIT(2) // reflect the state of the EESK. +#define EEDI BIT(1) // reflect the state of the EEDI. +#define EEDO BIT(0) // reflect the state of the EEDO. + + +#ifdef EN_EFUSE +#define CmdEEPROM_En BIT(5) // EEPROM enable when set 1 +#define CmdEERPOMSEL BIT(4) // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 +#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) +#define AutoLoadEFUSE CmdEEPROM_En + + +#ifdef CONFIG_RTL_92C_SUPPORT + +#ifdef CONFIG_PCI_HCI +#define EEPROM_VID 0x0A // SE Vendor ID.A-B +#define EEPROM_DID 0x0C // SE Device ID. C-D +#define EEPROM_SVID 0x0E // SE Vendor ID.E-F +#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11 +#endif +#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power base +#define EEPROM_TxPowerHT40_1S 0x60 // HT40 Tx Power base +#define EEPROM_TxPowerHT40_2SDiff 0x66 // HT40 Tx Power diff +#define EEPROM_TxPowerHT20Diff 0x69 // HT20 Tx Power diff +#define EEPROM_TxPowerOFDMDiff 0x6C // OFDM Tx Power diff +#define EEPROM_MACADDRESS 0x16 + +#define EEPROM_CHANNEL_PLAN 0x75 +#define EEPROM_TSSI_A 0x76 +#define EEPROM_TSSI_B 0x77 +#define EEPROM_THERMAL_METER 0x78 //[4:0] +#define EEPROM_RF_OPT1 0x79 +#define EEPROM_RF_OPT2 0x7A +#define EEPROM_RF_OPT3 0x7B +#define EEPROM_RF_OPT4 0x7C +#define EEPROM_VERSION 0x7E +#define EEPROM_CUSTOMER_ID 0x7F + +#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] + +#ifdef CONFIG_USB_HCI + +#define EEPROM_VID 0x0A +#define EEPROM_PID 0x0C +#define EEPROM_SUBCUSTOMER_ID 0x59 + +//should be renamed and moved to another file +typedef enum _BOARD_TYPE_8192CUSB{ + BOARD_USB_DONGLE = 0, // USB dongle + BOARD_USB_High_PA = 1, // USB dongle with high power PA + BOARD_MINICARD = 2, // Minicard + BOARD_USB_SOLO = 3, // USB solo-Slim module + BOARD_USB_COMBO = 4, // USB Combo-Slim module +} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB; + +#endif // CONFIG_USB_HCI +#endif // CONFIG_RTL_92C_SUPPORT + +#ifdef CONFIG_USB_HCI +#define BOARD_TYPE_NORMAL_MASK 0xE0 + +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_SubCustomerID 0xCD +#endif // CONFIG_USB_HCI + +#endif // EN_EFUSE + + +//---------------------------------------------------------------------------- +// 8192S AFE_MISC bits (Offset 0x10, 8bits) +//---------------------------------------------------------------------------- +#define MAC_ID_EN BIT(7) // Reserved for RF_ID selection to be MAC. +#define AFE_MBEN BIT(1) // Enable AFE Macro Block's Mbias. +#define AFE_BGEN BIT(0) // Enable AFE Macro Block's Bandgap. + +//---------------------------------------------------------------------------- +// 8192C SPS0_CTRL bits (Offset 0x11-17, 56bits) +//---------------------------------------------------------------------------- +#define SW18_LDO_R BIT(19) // LDO_R_L1 = 1 => LDO resistor connect. +#define SW18_V15ADJ_SHIFT 16 // v15adj_L1<2:0> output. +#define SW18_V15ADJ_Mask 0x07 +#define SW18_VOL_SHIFT 12 // VOL_L1<3:0> output. +#define SW18_VOL_Mask 0x0F +#define SW18_IN_SHIFT 9 // IN_L1<2:0> output. +#define SW18_IN_Mask 0x07 +#define SW18_TBOX_SHIFT 7 // TBOC_L1<1:0> output. +#define SW18_TBOX_Mask 0x03 +#define SW18_SET_DELAY BIT(6) // SET_DELAY_L1=1=> nonoverlap delay increases. +#define SW18_SEL BIT(5) // SD_L1 = 1 => turn off quickly. +#define SW18_STD_SHIFT 3 // STD_L1<1:0> time. +#define SW18_STD_Mask 0x03 +#define SW18_SD BIT(2) // SD_L1 = 1 => turn off quickly. +#define SW18_AREN BIT(1) // 3.3->1.8 for PFM Anti-ring. +#define SW18_R3_B1 BIT(0) // + +#define SW18_R3_B0 BIT(31) // +#define SW18_R2_SHIFT 29 // +#define SW18_R2_Mask 0x03 +#define SW18_R1_SHIFT 27 // +#define SW18_R1_Mask 0x03 +#define SW18_C3_SHIFT 25 // +#define SW18_C3_Mask 0x03 +#define SW18_C2_SHIFT 23 // +#define SW18_C2_Mask 0x03 +#define SW18_C1_SHIFT 21 // +#define SW18_C1_Mask 0x03 +#define SW18_SCREF_SHIFT 19 // For FDUAL, tune reference frequency. +#define SW18_SCREF_Mask 0x03 +#define SW18_SCPFM_SHIFT 17 // For FDUAL, tune pfm frequency. +#define SW18_SCPFM_Mask 0x03 +#define SW18_PWFMTUNE_SHIFT 14 // +#define SW18_PWFMTUNE_Mask 0x07 +#define SW18_SELSTOP BIT(13) // SEL_STOP_L1 = 0 => no delay. +#define SW18_SELD_SHIFT 11 // Bit(1)=1 enable clamp maximum duty, bit(0)=1 enable clamp minimum duty +#define SW18_SELD_Mask 0x03 +#define SW18_POWOCP BIT(10) // POWOCP_L1=1=> enable over current protection. +#define SW18_OCP_SHIFT 7 // +#define SW18_OCP_Mask 0x07 +#define SW18_SFREQ_SHIFT 5 // +#define SW18_SFREQ_Mask 0x03 +#define SW18_SFREQC BIT(4) // +#define SW18_FPWM BIT(3) // FPWM_L1 = 1 => force PWM, FPWM_L1 = 0 => force PFM. +#define SW18_FDUAL BIT(2) // FDUAL_L1 =1 => PWM or PFM. +#define SW18_SWEN BIT(1) // Enable VSPS18_SW Macro Block. +#define SW18_LDEN BIT(0) // Enable VSPS18_LDO Macro Block. + +//---------------------------------------------------------------------------- +// 8192C SPS_OCP_CFG bits (Offset 0x18-1B, 32bits) +//---------------------------------------------------------------------------- +#define SPS18_OCP_DIS BIT(31) // sps18 ocp, 0:enable, 1:disable. +#define SPS18_OCP_TH_SHIFT 16 // Sps18 ocp threshold. +#define SPS18_OCP_TH_Mask 0x07FFF +#define OCP_WINDOW_SHIFT 0 // Ocp monitor window width configure, count on ana_clk/16. +#define OCP_WINDOW_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C RSV_CTRL0 bits (Offset 0x1C-1E, 24bits) +//---------------------------------------------------------------------------- +#define HREG_DBG_SHIFT 8 // HREG Access Debug. +#define HREG_DBG_Mask 0x0FFFF +#define LOCK_ALL_EN BIT(7) // 1:Enable 'Locked All' setting by Hardware, 0: Hardware Enable 'Locked All' denied. +#define R_DIS_PRST_1 BIT(6) // Control if PERST can reset MACCORE. +#define R_DIS_PRST_0 BIT(5) // Control if PERST can reset MACCORE. +#define WLOCK_40 BIT(4) // 1:Register Write Locked, 0: Register Accessible by SW/FW. +#define WLOCK_08 BIT(3) // 1:Register Write Locked, 0: Register Accessible by SW/FW. +#define WLOCK_04 BIT(2) // 1:Register Write Locked, 0: Register Accessible by SW/FW. +#define WLOCK_00 BIT(1) // 1:Register Write Locked, 0: Register Accessible by SW/FW. +#define WLOCK_ALL BIT(0) // 1:Register Write Locked, 0: Register Accessible by SW/FW. + +//---------------------------------------------------------------------------- +// 8192C RF_CTRL bits (Offset 0x1F, 8bits) +//---------------------------------------------------------------------------- +#define RF_SDMRSTB BIT(2) // Reset RF SDM Module (low active). +#define RF_RSTB BIT(1) // Reset RF Module (low active). +#define RF_EN BIT(0) // Enable RF Module. + +//---------------------------------------------------------------------------- +// 8192C LDOA15_CTRL bits (Offset 0x20, 8bits) +//---------------------------------------------------------------------------- +#define LDA15_VOADJ_SHIFT 4 // +#define LDA15_VOADJ_Mask 0x0F +#define LDA15_STBY BIT(3) // LDOA15 Standby Mode. +#define LDA15_OBUF BIT(2) // LDOA15 Output Buffered. +#define REG_VOS BIT(1) // LDOA15 Add Offset voltage. +#define LDA15_EN BIT(0) // Enable LDOA15 Macro Block. + +//---------------------------------------------------------------------------- +// 8192C LDOV12D_CTRL bits (Offset 0x21, 8bits) +//---------------------------------------------------------------------------- +#define LDV12_VADJ_SHIFT 4 // LDOVD12 voltage adjust. +#define LDV12_VADJ_Mask 0x0F +#define LDV12_BUFO BIT(2) // LDOVD12 buffer output Mode. +#define LDV12_SDBY BIT(1) // LDOVD12 standby mode. +#define LDV12_EN BIT(0) // Enable LDOA12 Macro Block. + +//---------------------------------------------------------------------------- +// 8192C LDOHCI12_CTRL bits (Offset 0x22, 8bits) +//---------------------------------------------------------------------------- +#define LDH12_SDBY BIT(5) // LDOHCI12 standby mode. +#define LDH12_OBUF BIT(4) // Enable LDOHCI12 Macro Block. +#define LDH12_VADJ_SHIFT 1 // LDOHCI12 voltage adjust. +#define LDH12_VADJ_Mask 0x07 +#define LDH12_EN BIT(0) // Enable LDOHCI12 Macro Block. + +//---------------------------------------------------------------------------- +// 8192C LPLDO_CTRL bits (Offset 0x23, 8bits) +//---------------------------------------------------------------------------- +#define LPLDH12_SLP BIT(4) // LPLDOH12 Sleep Mode. +#define LPLDH12_VADJ_SHIFT 0 // LPLDOH12 voltage adjust. +#define LPLDH12_VADJ_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C AFE_XTAL_CTRL bits (Offset 0x24-27, 32bits) +//---------------------------------------------------------------------------- +#define CKDLY_BT BIT(29) // Delay time of CLK_BT relate to CLK_DIG, 0: long time, 1: short time. +#define CKDLY_DIG BIT(28) // Delay time of CLK_DIG relate to CLK_AFE, 0: long time, 1: short time. +#define CKDLY_USB BIT(27) // Delay time of CLK_USB relate to CLK_AFE, 0: long time, 1: short time. +#define CKDLY_AFE BIT(26) // Delay time of CLK_AFE relate to CLK_RF, 0: long time, 1: short time. +#define XTAL_GPIO_SHIFT 23 // +#define XTAL_GPIO_Mask 0x07 +#define XTAL_BT_DRV_SHIFT 21 // BT clock source Driving current: 11:most current, 00: less current. +#define XTAL_BT_DRV_Mask 0x03 +#define XTAL_BT_GATE BIT(20) // Gated control: 1: BT Clock source gated, 0: clock enable (auto setting by trap data). +#define XTAL_DIG_DRV_SHIFT 18 // DIG clock source 11:most current, 00: less current. +#define XTAL_DIG_DRV_Mask 0x03 +#define XTAL_GATE_DIG BIT(17) // Gated control:1: DIG Clock source gated, 0: clock enable. +#define XTAL_RF_DRV_SHIFT 15 // RF PLL Driving current: 11:most current, 00: less current. +#define XTAL_RF_DRV_Mask 0x03 +#define XTAL_RF_GATE BIT(14) // Gated control: 1: RF Clock source gated, 0: clock enable. +#define XTAL_AFE_DRV_SHIFT 12 // AFE PLL Driving current: 11:most current, 00: less current. +#define XTAL_AFE_DRV_Mask 0x03 +#define XTAL_GATE_AFE BIT(11) // Gated control:1: USB Clock source gated, 0: clock enable. +#define XTAL_USB_DRV_SHIFT 9 // USB PLL Driving current: 11:most current, 00: less current. +#define XTAL_USB_DRV_Mask 0x03 +#define XTAL_GATE_USB BIT(8) // Gated control:1: USB Clock source gated, 0: clock enable. +#define XTAL_CADJ_XI_SHIFT 4 // 1:add cap, 0:degrade cap. +#define XTAL_CADJ_XI_Mask 0x0F +#define XTAL_BOSC_SHIFT 2 // The bias current control of VCO block. +#define XTAL_BOSC_Mask 0x03 +#define XTAL_BSEL BIT(1) // 1: schmitt trigger, 0:nand. +#define XTAL_EN BIT(0) // Enable XTAL Macro block. + +//---------------------------------------------------------------------------- +// 8192C AFE_PLL_CTRL bits (Offset 0x28-2B, 32bits) +//---------------------------------------------------------------------------- +#define AFE_DUMMY_SHIFT 25 // Dummy Registers. +#define AFE_DUMMY_Mask 0x07 +#define APLL_1MEN BIT(24) // 1:Enable 0:output "1". +#define APLL_40DRV_SHIFT 22 // clk diving 00: weak 11:strong. +#define APLL_40DRV_Mask 0x03 +#define APLL_PLLDRV_SHIFT 20 // clk diving 00: weak 11:strong. +#define APLL_PLLDRV_Mask 0x03 +#define APLL_88DRV_SHIFT 18 // clk diving 00: weak 11:strong. +#define APLL_88DRV_Mask 0x03 +#define APLL_80DRV_SHIFT 16 // clk diving 00: weak 11:strong. +#define APLL_80DRV_Mask 0x03 +#define APLL_80EN BIT(15) // 1:Enable 0:output "1". +#define APLL_320EN BIT(14) // 1:Enable 0:output "1". +#define APLL_320BIAS_SHIFT 11 // pll320 CP current selection. +#define APLL_320BIAS_Mask 0x07 +#define APLL_BIAS_SHIFT 8 // pll CP current selection. +#define APLL_BIAS_Mask 0x07 +#define APLL_KVCO_SHIFT 6 // pll VCO KVCO selection. +#define APLL_KVCO_Mask 0x03 +#define APLL_LPFEN BIT(5) // enable PLL Bias Current LPF. +#define APLL_WDOGB BIT(4) // enable watch dog 0: enable 1:disable. +#define APLL_EDGE_SEL BIT(3) // Reference clock: 1 : negative edge, 0 : positive edge. +#define APLL_FREF_SEL BIT(2) // Reference clock: 1 : 20MHz, 0 : 40MHz. +#define APLL_320_EN BIT(1) // Enable AFE 320 PLL Macro Block. +#define APLL_EN BIT(0) // Enable AFE PLL Macro Block. + +//---------------------------------------------------------------------------- +// 8192C EFUSE_CTRL bits (Offset 0x30-33, 32bits) +//---------------------------------------------------------------------------- +#define EF_FLAG BIT(31) // Access Flag. Write "1" for Program; Write "0" for Read Access. +#define EF_PGPD_SHIFT 28 // E-fuse program time. +#define EF_PGPD_Mask 0x07 +#define EF_RDT_SHIFT 24 // E-fuse read time: in the unit of cycle time. +#define EF_RDT_Mask 0x0F +#define EF_PGT_SHIFT 20 // Programming setup time. In the unit of cycle time.(125ns). +#define EF_PGT_Mask 0x0F +#define EF_PD BIT(19) // Efuse power down. +#define ALD_EN BIT(18) // Autoload Enable. +#define EF_ADDR_SHIFT 8 // Access Address. +#define EF_ADDR_Mask 0x03FF +#define EF_DATA_SHIFT 0 // Access Data. +#define EF_DATA_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C EFUSE_TEST bits (Offset 0x34-37, 32bits) +//---------------------------------------------------------------------------- +#define LDOE25_EN BIT(31) // Enable LDOE25 Macro Block. +#define LDOE25_VADJ_SHIFT 28 // LDOE25 voltage adjust. +#define LDOE25_VADJ_Mask 0x07 +#define ADDR_END_Shift 25 // 92D_REG, Scan effuse end (1023-addr_end) +#define ADDR_END_Mask 0x07 +#define ADDR_STR_Shift 18 // 92D_REG, Scan efuse from (addr_str*8) +#define ADDR_STR_Mask 0x07F +#define BYTE_CNT_EN BIT(17) // 92D_REG, 1: scan efuse in byte; 0: scan efuse in bit +#define EF_SCAN_EN BIT(16) // 92D_REG, 1: efuse in scan process. 0: not in scan process +#define EDATA1_SHIFT 8 // EEPROM offset 1 data (EE Byte-1). +#define EDATA1_Mask 0x0FF +#define EF_TRPT BIT(7) // Test Scan Report: 1 : Fail, 0 : OK. +#define EF_TTHD_SHIFT 0 // Bit number for all cells scan test. +#define EF_TTHD_Mask 0x07F + +//---------------------------------------------------------------------------- +// 8192C PWR_DATA bits (Offset 0x38-3B, 32bits) +//---------------------------------------------------------------------------- +#define EDATA0_SHIFT 24 // EEPROM offset 0 data (EE Byte-0). +#define EDATA0_Mask 0x0FF +#define HTEST_SEL_SHIFT 16 // TEST Mode Select (EE Byte-7). +#define HTEST_SEL_Mask 0x0FF +#define HPON_STBP2_SHIFT 8 // HPON Stable time parameter (EE Byte-5). +#define HPON_STBP2_Mask 0x0FF +#define HPON_STBP1_SHIFT 0 // HPON Stable time parameter (EE Byte-2). +#define HPON_STBP1_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C CAL_TIMER bits (Offset 0x3C-3D, 16bits) +//---------------------------------------------------------------------------- +#define MATCH_CNT_SHIFT 8 // match counter for sleep mode. +#define MATCH_CNT_Mask 0x0FF +#define CAL_SCAL_SHIFT 0 // scaler fine tune for sleep mode (tune in Time unit). +#define CAL_SCAL_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C ACLK_MON bits (Offset 0x3E-3F, 16bits) +//---------------------------------------------------------------------------- +#define RCLK_MON_SHIFT 5 // ring clock monitor (with DPSTU scale). +#define RCLK_MON_Mask 0x07FF +#define CAL_TIMER_EN BIT(4) // calibration timer enable. This shall be turned off before sleep mode enable. +#define DPSTU_SHIFT 2 // Deep Power Save Time Unit: 00: 64us, 01: 128us, 10: 192us, 11: 256 us. +#define DPSTU_Mask 0x03 +#define SUS_16X BIT(1) // Scale timer 16x when suspend mode, (~250 S). +#define RSM_EN BIT(0) // When Timer Expired, Resume Hardware StateMachine. + +//---------------------------------------------------------------------------- +// 8192C GPIO_MUXCFG bits (Offset 0x40-43, 32 bits) +//---------------------------------------------------------------------------- +#define GPIO_MOD_H_SHIFT 28 // When bit is zero, corresponding port configured to data port; + // otherwise, when a bit is set, and GPIO_IO_SEL is set to "0", + // then it is interrupt mode.. +#define GPIO_MOD_H_Mask 0x0F +#define GPIO_IO_SEL_H_SHIFT 24 // GPIO_IO_SEL[11:8], output when bit=1;input when bit=0. +#define GPIO_IO_SEL_H_Mask 0x0F +#define GPIO_OUT_H_SHIFT 20 // GPIO_OUT[11:8], GPIO pins output value. +#define GPIO_OUT_H_Mask 0x0F +#define GPIO_IN_H_SHIFT 16 // GPIO_IN[11:8], GPIO pins input value. +#define GPIO_IN_H_Mask 0x0F +#define SIC_LBK BIT(15) // Enable SIC_Loop_Back Mode, (auto set by ICFG). +#define HTP_EN BIT(14) // 0 : Enable as Host Debug Port, 1 : Enable as Host Test Port. +#define SIC_23 BIT(13) // Enable SIC at 0: GPIO 9,10 pins ; 1 : GPIO 2,3 pins. +#define SIC_EN BIT(12) // Enable GPIO Pins as SIC, (auto set by ICFG). +#define SIC_SWRST BIT(11) // 0 : Reset SIC by SW, prevent SIC Dead Lock. +#define PMAC_EN BIT(10) // PMAC Enable (auto set by ICFG). +#define UART_SEL BIT(9) // Enable UART at 0: GPIO 6,7 pins; 1 : GPIO 9,10 pins. +#define UART_EN BIT(8) // Enable GPIO Pins as UART. +#define BTMode_SHIFT 6 // Bluetooth Mode. +#define BTMode_Mask 0x03 +#define BT_EN BIT(5) // Enable GPIO0,1,2,3,8 Pins for Bluetooth. +#define EROM_EN BIT(4) // Enable GPIO6 for EEDO, GPIO7 for EEDI, default Enable when 9346 selected +#define TRSW1EN BIT(3) // Enable GPIO9,10 for TRSWN1, TRSWP1. +#define TRSW0EN BIT(2) // Enable GPIO8 for TRSWN0. +#define GPIOSEL_SHIFT 0 // GPIO Select. +#define GPIOSEL_Mask 0x03 + +//---------------------------------------------------------------------------- +// 8192C GPIO_PIN_CTRL bits (Offset 0x44-47, 32 bits) +//---------------------------------------------------------------------------- +#define GPIO_MOD_L_SHIFT 24 // When bit is 0, corresponding port set as data port; + // otherwise, when a bit=1, and GPIO_IO_SEL is set to "0", + // then it is interrupt mode.. +#define GPIO_MOD_L_Mask 0x0FF +#define GPIO_IO_SEL_L_SHIFT 16 // GPIO_IO_SEL[7:0], output when bit=1;input when bit=0. +#define GPIO_IO_SEL_L_Mask 0x0FF +#define GPIO_OUT_L_SHIFT 8 // GPIO_OUT[7:0], GPIO pins output value. +#define GPIO_OUT_L_Mask 0x0FF +#define GPIO_IN_L_SHIFT 0 // GPIO_IN[7:0], GPIO pins input value. +#define GPIO_IN_L_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C GPIO_INTM bits (Offset 0x48-4B, 32 bits) +//---------------------------------------------------------------------------- +#define MDBG_SEL_SHIFT 30 // +#define MDBG_SEL_Mask 0x03 +#define GPIO_EXT_WOL_SHIFT 12 // External WOL source control. +#define GPIO_EXT_WOL_Mask 0x0F +#define GPIOB_INT_MD BIT(11) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIOA_INT_MD BIT(10) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO9_INT_MD BIT(9) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO8_INT_MD BIT(8) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO7_INT_MD BIT(7) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO6_INT_MD BIT(6) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO5_INT_MD BIT(5) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO4_INT_MD BIT(4) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO3_INT_MD BIT(3) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO2_INT_MD BIT(2) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO1_INT_MD BIT(1) // 0=positive edge, 1=negative edge, is sensed as interrupt. +#define GPIO0_INT_MD BIT(0) // 0=positive edge, 1=negative edge, is sensed as interrupt. + +//---------------------------------------------------------------------------- +// 8192C LEDCFG bits (Offset 0x4C-4F, 32 bits) +//---------------------------------------------------------------------------- +#define GP8_LED BIT(22) // Enable GPIO-8 as LED2. +#define LED2EN BIT(21) // Enable GPIO-10/GPIO-8 as LED2. +#define LED2PL BIT(20) // LED2 polarity control. +#define LED2SV BIT(19) // LED2 software value. +#define LED2CM_SHIFT 16 // LED2 Control Mode. +#define LED2CM_Mask 0x07 +#define LED1DIS BIT(15) // LED1 Disabled for analog signal usage, + // 1: disable (input mode), 0:Enable (output mode). +#define LED1PL BIT(12) // LED1 polarity control (auto-load configurable). +#define LED1SV BIT(11) // LED1 software value. +#define LED1CM_SHIFT 8 // LED1 Control Mode. +#define LED1CM_Mask 0x07 +#define LED0DIS BIT(7) // LED1 Disabled for analog signal usage, + // 1: disable (input mode), 0:Enable (output mode). +#define LED0PL BIT(4) // LED0 polarity control (auto-load configurable). +#define LED0SV BIT(3) // LED0 software value. +#define LED0CM_SHIFT 0 // LED0 Control Mode. +#define LED0CM_Mask 0x07 + +#define LED_SW_CTRL 0 +#define LED_OFF 1 +#define LED_TX_RX_EVENT_ON 2 +#define LED_TX_RX_EVENT_OFF 3 +#define LED_TX_EVENT_ON 4 +#define LED_TX_EVENT_OFF 5 +#define LED_RX_EVENT_ON 6 +#define LED_RX_EVENT_OFF 7 + +//---------------------------------------------------------------------------- +// 8192C FSIMR bits (Offset 0x50-53, 32 bits) +//---------------------------------------------------------------------------- +#define PDNINT_EN BIT(31) // Enable Hardware Power Down interrupt source. +#define SYS_TIMER_EN BIT(30) // Enable Hardware System Timer interrupt source. +#define SPS_OCP_INT_EN BIT(29) // Enable SPS OCP alarm interrupt source. +#define HPON_WRE_EN BIT(28) // Enable Continue access HPON registers interrupt source. +#define GPIOB_INT_EN BIT(23) // Enable GPIOB interrupt source. +#define GPIOA_INT_EN BIT(22) // Enable GPIOA interrupt source. +#define GPIO9_INT_EN BIT(21) // Enable GPIO9 interrupt source. +#define GPIO8_INT_EN BIT(20) // Enable GPIO8 interrupt source. +#define GPIO7_INT_EN BIT(19) // Enable GPIO7 interrupt source. +#define GPIO6_INT_EN BIT(18) // Enable GPIO6 interrupt source. +#define GPIO5_INT_EN BIT(17) // Enable GPIO5 interrupt source. +#define GPIO4_INT_EN BIT(16) // Enable GPIO4 interrupt source. +#define GPIO3_INT_EN BIT(15) // Enable GPIO3 interrupt source. +#define GPIO2_INT_EN BIT(14) // Enable GPIO2 interrupt source. +#define GPIO1_INT_EN BIT(13) // Enable GPIO1 interrupt source. +#define GPIO0_INT_EN BIT(12) // Enable GPIO0 interrupt source. + +//---------------------------------------------------------------------------- +// 8192C FSISR bits (Offset 0x54-57, 32 bits) +//---------------------------------------------------------------------------- +#define PDNINT BIT(31) // Hardware Power Down interrupt. +#define HWSYS_TIMER_INT BIT(30) // Hardware System Timer interrupt. +#define SPS_OCP_INT BIT(29) // SPS OCP alarm interrupt. +#define HPON_WRE BIT(28) // Continue access HPON registers interrupt. Write 1 clear. +#define GPIOB_INT BIT(23) // GPIOB INT Status. Write 1 clear. +#define GPIOA_INT BIT(22) // GPIOA INT Status. Write 1 clear. +#define GPIO9_INT BIT(21) // GPIO9 INT Status. Write 1 clear. +#define GPIO8_INT BIT(20) // GPIO8 INT Status. Write 1 clear. +#define GPIO7_INT BIT(19) // GPIO7 INT Status. Write 1 clear. +#define GPIO6_INT BIT(18) // GPIO6 INT Status. Write 1 clear. +#define GPIO5_INT BIT(17) // GPIO5 INT Status. Write 1 clear. +#define GPIO4_INT BIT(16) // GPIO4 INT Status. Write 1 clear. +#define GPIO3_INT BIT(15) // GPIO3 INT Status. Write 1 clear. +#define GPIO2_INT BIT(14) // GPIO2 INT Status. Write 1 clear. +#define GPIO1_INT BIT(13) // GPIO1 INT Status. Write 1 clear. +#define GPIO0_INT BIT(12) // GPIO0 INT Status. Write 1 clear. + +//---------------------------------------------------------------------------- +// 8192C MCUFWDL bits (Offset 0x80-83, 32 bits) +//---------------------------------------------------------------------------- +#define RPWM_SHIFT 24 // Host Request Power State. +#define RPWM_Mask 0x0FF +#define CPRST BIT(23) // 8051 Reset Status. +#define ROM_DLEN BIT(19) // ROM Download Enable (8051 Core will be reseted) FPGA only. +#define ROM_PGE_SHIFT 16 // ROM Page (FPGA only). +#define ROM_PGE_Mask 0x07 +#define MAC1_RFINI_RDY BIT(10) // 92D_REG, MAC1 MCU Initial RF ready +#define MAC1_BBINI_RDY BIT(9) // 92D_REG, MAC1 MCU Initial BB ready +#define MAC1_MACINI_RDY BIT(8) // 92D_REG, MAC1 MCU Initial MAC ready +#define MCU_STATUS BIT(7) // 92D_REG, 1: SRAM, 0: ROM +#define WINTINI_RDY BIT(6) // WLAN Interrupt Initial ready. +#define MAC0_RFINI_RDY BIT(5) // MAC0 MCU Initial RF ready. +#define MAC0_BBINI_RDY BIT(4) // MAC0 MCU Initial BB ready. +#define MAC0_MACINI_RDY BIT(3) // MAC0 MCU Initial MAC ready. +#define FWDL_CHKSUM_RPT BIT(2) // FWDL CheckSum report, 1: OK, 0 : Faill. +#define MCUFWDL_RDY BIT(1) // Driver set this bit to notify MCU FW Download OK. +#define MCUFWDL_EN BIT(0) // MCU Firmware download enable. 1:Enable, 0:Disable. + +//---------------------------------------------------------------------------- +// 8192C MCUTSTCFG bits (Offset 0x84-87, 32 bits) +//---------------------------------------------------------------------------- +#define LBKTST_SHIFT 0 // LBK TST indicator. +#define LBKTST_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C BIST_CTRL bits (Offset 0xD0-D3, 32 bits) +//---------------------------------------------------------------------------- +#define BB_SPEED_SCAN BIT(31) // BB at speed scan mode Enable. +#define SCAN_PLL_BYPASS BIT(30) // 92D_REG +#define MBIST_RSTNI_Shift 8 // 92D_REG +#define MBIST_RSTNI_Mask 0x07FF +#define BIST_RESUME_PS BIT(5) +#define BIST_RESUME BIT(4) +#define BIST_DRF BIT(3) // 92D_REG +#define BIST_RETEN BIT(3) +#define BIST_NORMAL BIT(2) +#define BIST_RSTN BIT(1) +#define BIST_CLK_EN BIT(0) + +//---------------------------------------------------------------------------- +// 8192C C_BIST_RPT bits (Offset 0xD4-D7, 32 bits) +//---------------------------------------------------------------------------- +#define C_MAC_BIST_FAIL BIT(31) // MAC_BIST_FAIL. +#define C_USB_IRAM_FAIL BIT(26) // USB IRAM BIST FAIL. +#define C_USB_RAM1_FAIL BIT(25) // USB RAM1 BIST FAIL. +#define C_USB_PROM_FAIL BIT(24) // USB PROM BIST FAIL. +#define C_PCIE_RETRY_BIST_FAIL BIT(20) // PCIE RETRY RAM BIST FAIL. +#define C_PCIE_SOT_BIST_FAIL BIT(19) // PCIE RETRY SOT RAM BIST FAIL. +#define C_PCIE_PH1_BIST_FAIL BIT(18) // PCIE PHDR RAM1 BIST FAIL. +#define C_PCIE_PH0_BIST_FAIL BIT(17) // PCIE PHDR RAM0 BIST FAIL. +#define C_PCIE_PD_BIST_FAIL BIT(16) // PCIE PDATA RAM BIST FAIL. +#define C_MAC_BIST_RDY BIT(10) // MAC MBIST Test report Ready. +#define C_USB_BIST_RDY BIT(9) // USB MBIST Test report Ready. +#define C_PCIE_BIST_RDY BIT(8) // PCIE MBIST Test report Ready. +#define C_MAC_BIST_START BIT(2) // MAC MBIST START PULSE. +#define C_USB_BIST_START BIT(1) // USB MBIST START PULSE. +#define C_PCIE_BIST_START BIT(0) // PCIE MBIST START PULSE. + +//---------------------------------------------------------------------------- +// 8192C USB_SIE_INTF bits (Offset 0xE0-E3, 32 bits) +//---------------------------------------------------------------------------- +#define USB_SIE_INTF_WE BIT(25) // Write Enable of SIE interface. +#define USB_SIE_INTF_BYIOREG BIT(24) // SIE Bypass IOREG interface. +#define USB_SIE_INTF_ADDR_SHIFT 16 // The address of SIE register. +#define USB_SIE_INTF_ADDR_Mask 0x0FF +#define USB_SIE_INTF_RD_SHIFT 8 // The read data from USB SIE. +#define USB_SIE_INTF_RD_Mask 0x0FF +#define USB_SIE_INTF_WD_SHIFT 0 // The write data to USB SIE. +#define USB_SIE_INTF_WD_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C PCIE_MIO_INTF bits (Offset 0xE4-E7, 32 bits) +//---------------------------------------------------------------------------- +#define PCIE_MIO_BYIOREG BIT(13) // MIO bypass IOREG interface. +#define PCIE_MIO_RE BIT(12) // Read Enable of MIO interface. +#define PCIE_MIO_WE_SHIFT 8 // Write Byte Enable of MIO interface. +#define PCIE_MIO_WE_Mask 0x0F +#define PCIE_MIO_ADDR_SHIFT 0 // The address of PCIE MIO Access register. +#define PCIE_MIO_ADDR_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C HPON_FSM bits (Offset 0xEC-EF, 32 bits) +//---------------------------------------------------------------------------- +#define EVENT_FSM_SHIFT 16 // The State Machine Trigger Events. +#define EVENT_FSM_Mask 0x0FFFF +#define PMC_ADDR_SHIFT 8 // The Hardware Access HPON Register Addr. +#define PMC_ADDR_Mask 0x0FF +#define PMC_WR BIT(7) // The Hardware Access HPON Register Write Pulse. +#define PMC_DATA BIT(6) // The Hardware Access HPON Register Data. +#define FSM_STATE_SHIFT 0 // The State Machine Data. +#define FSM_STATE_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C SYS_CFG bits (Offset 0xF0-F3, 32 bits) +//---------------------------------------------------------------------------- +#define TRP_ICFG_SHIFT 28 // Trapped ICFG data value. +#define TRP_ICFG_Mask 0x0F +#define TYPE_ID BIT(27) // 1: 8191C/8192C ; 0: 8188C. +#define BD_HCI_SEL BIT(26) // Trapped HCI_SEL value. +#define BD_PKG_SEL BIT(25) // Trapped PKG_ENG_SEL value. +#define TRP_BT_EN BIT(24) // Trapped BT Chip Valid need XTAL & SPS resource. +#define TRP_VAUX_EN BIT(23) // Trapped VAUX_EN. +#define PAD_HWPD_IDN BIT(22) // HWPDN PAD status Indicator. +#define PSC_TESTCFG_SHIFT 20 // Test Pin configuration. +#define PSC_TESTCFG_Mask 0x03 +#define CHIP_VER_RL_SHIFT 16 // Chip version (RL6111). +#define CHIP_VER_RL_Mask 0x0F +#define CHIP_VER_RTL_SHIFT 12 // Test Chip version - 8188C (RLE0307) / 8191C (RLE0308). +#define CHIP_VER_RTL_Mask 0x0F +#define IC_MACPHY_MODE BIT(11) // 0: IC Normal Mode, 1: force IC PHY_ASIC Mode. +#define BD_MAC1 BIT(10) // Bonding option for MAC function-1 Enable. +#define BD_MAC2 BIT(9) // Bonding option for MAC function-2 Enable. +#define SIC_IDLE BIT(8) // Indicator of SIC idle state. +#define TRP_B15V_EN BIT(7) // Trapped option for 1.5V of board. +#define OCP_SHUTDN BIT(6) // SPS OCP shutdown Chip. +#define V15_VLD BIT(5) // 1.5V Power Ready, 1: Power Ready. +#define PCIRSTB BIT(4) // PCIE External PERST, Pin Status. +#define PCLK_VLD BIT(3) // PCIE PHY Clock Stable, 1: Clock Stable. +#define UCLK_VLD BIT(2) // USB PHY Clock Stable, 1: Clock Stable. +#define ACLK_VLD BIT(1) // AFE Clock Stable, 1: Clock Stable. +#define XCLK_VLD BIT(0) // Xtal Clock Stable, 1: Clock Stable. + + +// +// 2. MACTOP General Configuration. (Offset 0x100 - 0x1FFh) +// +//---------------------------------------------------------------------------- +// 8192C CR bits (Offset 0x100-103, 32 bits) +//---------------------------------------------------------------------------- +#define LBMODE_SHIFT 24 // Loopback mode. +#define LBMODE_Mask 0x0F +#define NETYPE_SHIFT 16 // Network Type. +#define NETYPE_SHIFT1 18 +#define NETYPE_Mask 0x03 +#define CALTMR_EN BIT(10) // for 8723 & 88E only +#define MAC_SEC_EN BIT(9) // Enable MAC security engine. +#define ENSWBCN BIT(8) // Enable SW TX beacon. +#define MACRXEN BIT(7) // MAC Receiver Enable. +#define MACTXEN BIT(6) // MAC Transmitter Enable. +#define SCHEDULE_EN BIT(5) // Schedule Enable. +#define PROTOCOL_EN BIT(4) // protocol Block Function Enable. +#define RXDMA_EN BIT(3) // RXDMA Function Enable. +#define TXDMA_EN BIT(2) // TXDMA Function Enable. +#define HCI_RXDMA_EN BIT(1) // HCI to RXDMA Interface Enable. +#define HCI_TXDMA_EN BIT(0) // HCI to TXDMA Interface Enable. +// Loopback mode. +#define LB_NORMAL 0x00 +#define LB_MAC 0x0B +#define LB_MAC_DLY 0x03 +#define LB_PHY 0x01 +#define LB_DMA 0x07 +#define LB_DUAL_MAC 0x1B // 92D_REG +// Network Type. +#define NETYPE_NOLINK 0x00 +#define NETYPE_ADHOC 0x01 +#define NETYPE_INFRA 0x02 +#define NETYPE_AP 0x03 + +//---------------------------------------------------------------------------- +// 8192C PBP bits (Offset 0x104-107, 32 bits) +//---------------------------------------------------------------------------- +#define PSTX_SHIFT 4 // Page size of transmit packet buffer. +#define PSTX_Mask 0x0F +#define PSRX_SHIFT 0 // Page size of receive packet buffer and C2HCMD buffer. +#define PSRX_Mask 0x0F +// Page size +#define PBP_64B 0x00 +#define PBP_128B 0x01 +#define PBP_256B 0x02 +#define PBP_512B 0x03 +#define PBP_1024B 0x04 + +//---------------------------------------------------------------------------- +// 8192C TRXDMA_CTRL bits (Offset 0x10C-10D, 16 bits) +//---------------------------------------------------------------------------- +#define HPQ_SEL_SHIFT 8 // High Priority Queue Selection. +#define HPQ_SEL_Mask 0x03F +#define RXDMA_AGG_EN BIT(2) // +#define RXSHFT_EN BIT(1) // When this bit is set, RX shift to fit alignment is enable. +#define RXDMA_ARBBW_EN BIT(0) // Enable RXDMA Arbitrator priority for Host interface. +// High Priority Queue Selection. +#define HPQ_SEL_VOQ BIT(0) +#define HPQ_SEL_VIQ BIT(1) +#define HPQ_SEL_BEQ BIT(2) +#define HPQ_SEL_BKQ BIT(3) +#define HPQ_SEL_MGQ BIT(4) +#define HPQ_SEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + +//---------------------------------------------------------------------------- +// 8192C TRXFF_BNDY bits (Offset 0x114-117, 32 bits) +//---------------------------------------------------------------------------- +#define RXFF0_BNDY_SHIFT 16 // upper boundary of RXFF0. +#define RXFF0_BNDY_Mask 0x0FFFF +#define TXPKTBUF_PGBNDY_SHIFT 0 // From FWHW offload, sets the max pages controlled by TXDMA. +#define TXPKTBUF_PGBNDY_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C TRXFF_STATUS bits (Offset 0x118-11B, 32 bits) +//---------------------------------------------------------------------------- +#define TXPKTFF_FULL BIT(16) // TXDMA block the current TX pkt due to TXPKTBUF full, status bit will be set. +#define RXFF1_OVF BIT(1) // When this bit is "1", RXFF1 is under overflow condition. +#define RXFF0_OVF BIT(0) // When this bit is "1", RXFF0 is under overflow condition. + +//---------------------------------------------------------------------------- +// 8192C RXFF_PTR bits (Offset 0x11C-11F, 32 bits) +//---------------------------------------------------------------------------- +#define RXFF0_RDPTR_SHIFT 16 // The read pointer address of RXFF0. +#define RXFF0_RDPTR_Mask 0x0FFFF +#define RXFF0_WTPTR_SHIFT 0 // The write pointer address of RXFF0. +#define RXFF0_WTPTR_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C HIMR bits (Offset 0x120-123, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C HISR bits (Offset 0x124-127, 32 bits) +//---------------------------------------------------------------------------- +#define HIMR_BCNDMA7 BIT(31) // Beacon DMA Interrupt 7. +#define HIMR_BCNDMA6 BIT(30) // Beacon DMA Interrupt 6. +#define HIMR_BCNDMA5 BIT(29) // Beacon DMA Interrupt 5. +#define HIMR_BCNDMA4 BIT(28) // Beacon DMA Interrupt 4. +#define HIMR_BCNDMA3 BIT(27) // Beacon DMA Interrupt 3. +#define HIMR_BCNDMA2 BIT(26) // Beacon DMA Interrupt 2. +#define HIMR_BCNDMA1 BIT(25) // Beacon DMA Interrupt 1. +#define HIMR_BCNDOK7 BIT(24) // Beacon Queue DMA OK Interrupt7. +#define HIMR_BCNDOK6 BIT(23) // Beacon Queue DMA OK Interrupt6. +#define HIMR_BCNDOK5 BIT(22) // Beacon Queue DMA OK Interrupt5. +#define HIMR_BCNDOK4 BIT(21) // Beacon Queue DMA OK Interrupt4. +#define HIMR_BCNDOK3 BIT(20) // Beacon Queue DMA OK Interrupt3. +#define HIMR_BCNDOK2 BIT(19) // Beacon Queue DMA OK Interrupt2. +#define HIMR_BCNDOK1 BIT(18) // Beacon Queue DMA OK Interrupt1. +#define HIMR_TIMEOUT2 BIT(17) // Time Out Interrupt 2. +#define HIMR_TIMEOUT1 BIT(16) // Time Out Interrupt 1. +#define HIMR_TXFOVW BIT(15) // Transmit packet buffer Overflow. +#define HIMR_PSTIMEOUT BIT(14) // Power Save Time Out Interrupt. +#define HIMR_BCNDMA0 BIT(13) // Beacon DMA Interrupt 0. +#define HIMR_RXFOVW BIT(12) // Receive packet buffer Overflow. +#define HIMR_RDU BIT(11) // Receive Descriptor Unavailable. +#define HIMR_ATIM_END BIT(10) // ATIM Window End Interrupt. +#define HIMR_BCNDOK0 BIT(9) // Beacon Queue DMA OK Interrupt0. +#define HIMR_HIGHDOK BIT(8) // High Queue DMA OK Interrupt. +#define HIMR_TXBCNOK BIT(7) // Transmit Beacon OK Interrupt. +#define HIMR_MGTDOK BIT(6) // Management Queue DMA OK Interrupt. +#define HIMR_TXBCNERR BIT(5) // Transmit Beacon Error Interrupt. +#define HIMR_BKDOK BIT(4) // AC_BK DMA OK Interrupt. +#define HIMR_BEDOK BIT(3) // AC_BE DMA OK Interrupt. +#define HIMR_VIDOK BIT(2) // AC_VI DMA OK Interrupt. +#define HIMR_VODOK BIT(1) // AC_VO DMA Interrupt. +#define HIMR_ROK BIT(0) // Receive DMA OK Interrupt. + +//---------------------------------------------------------------------------- +// 8192C HIMRE bits (Offset 0x128-12A, 24 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C HISRE bits (Offset 0x12C-12E, 24 bits) +//---------------------------------------------------------------------------- +#define HIMRE_TXERR BIT(11) // Enable Tx Error Flag Interrupt. +#define HIMRE_RXERR BIT(10) // Enable Rx Error Flag Interrupt. +#define HIMRE_C2HCMD BIT(9) // Enable CPU to Host Command Interrupt. +#define HIMRE_CPWM BIT(8) // Enable CPU power Mode exchange Interrupt. +#define HIMRE_HBT_CMD BIT(7) // 92D_REG, Host BT_CMD interrupt mask +#define HIMRE_OCPINT BIT(1) // Enable SPS_OCP Interrupt. +#define HIMRE_WLANOFF BIT(0) // Enable WLAN power down Interrupt. + +//---------------------------------------------------------------------------- +// 8192C CPWM bits (Offset 0x12F, 8 bits) +//---------------------------------------------------------------------------- +#define CPWM_TOGGLING BIT(7) // When this bit is toggled, interrtup is send to HISRE.CPWMINT. +#define CPWM_MOD_SHIFT 0 // The current power mode index. +#define CPWM_MOD_Mask 0x07F + +//---------------------------------------------------------------------------- +// 8192C FWIMR bits (Offset 0x130-133, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C FWISR bits (Offset 0x134-137, 32 bits) +//---------------------------------------------------------------------------- +#define FWIMR_VOQ BIT(31) // +#define FWIMR_VIQ BIT(30) // +#define FWIMR_BEQ BIT(29) // +#define FWIMR_BKQ BIT(28) // +#define FWIMR_MGTQ BIT(27) // +#define FWIMR_HIQ BIT(26) // +#define FWIMR_TXPKTIN BIT(25) // interrupt is issued to inform MCU. +#define FWIMR_TXBCNOK BIT(24) // interrupt is issued when a beacon frame is transmitted. +#define FWIMR_TXBCNERR BIT(23) // interrupt is issued when beacon in TXPKTBUF fails to send out. +#define FWIMR_RX_UMD0 BIT(22) // receiving unicast data frame with More Data=0. +#define FWIMR_RX_UMD1 BIT(21) // receiving unicast data frame with More Data=1. +#define FWIMR_RX_BMD0 BIT(20) // receiving broadcast data frame with More Data=0. +#define FWIMR_RX_BMD1 BIT(19) // receiving broadcast data frame with More Data=1. +#define FWIMR_BCN_RX BIT(18) // When receiving Beacon frame. +#define FWIMR_TBTT BIT(17) // The exact TBTT time interrupt. +#define FWIMR_BCNERLY BIT(16) // This interrupt is issue at the time set by DRVERLYINT register before TBTT time. +#define FWIMR_BCNDMA7 BIT(15) // When BCNDMA interval arrives before TBTT7, informs MCU to prepare beacon. +#define FWIMR_BCNDMA6 BIT(14) // When BCNDMA interval arrives before TBTT6, informs MCU to prepare beacon. +#define FWIMR_BCNDMA5 BIT(13) // When BCNDMA interval arrives before TBTT5, informs MCU to prepare beacon. +#define FWIMR_BCNDMA4 BIT(12) // When BCNDMA interval arrives before TBTT4, informs MCU to prepare beacon. +#define FWIMR_BCNDMA3 BIT(11) // When BCNDMA interval arrives before TBTT3, informs MCU to prepare beacon. +#define FWIMR_BCNDMA2 BIT(10) // When BCNDMA interval arrives before TBTT2, informs MCU to prepare beacon. +#define FWIMR_BCNDMA1 BIT(9) // When BCNDMA interval arrives before TBTT1, informs MCU to prepare beacon. +#define FWIMR_BCNDMA0 BIT(8) // When BCNDMA interval arrives before TBTT0, informs MCU to prepare beacon. +#define FWIMR_LP_STBY BIT(7) // Low Power Standby Wake interrupt. +#define FWIMR_ATIM BIT(6) // This interrupt is issued when it is at the time ATIM ms before ATIMWND expiring. +#define FWIMR_HRCV BIT(5) // Host Recover CPU Loop Instruction. +#define FWIMR_H2CCMD BIT(4) // Host To CPU Message Interrupt. +#define FWIMR_RXDONE BIT(3) // +#define FWIMR_ERRORHDL BIT(2) // FWHW/ TXDMA/ RXDMA/ WMAC error status interrupt. +#define FWIMR_TXCCX BIT(1) // +#define FWIMR_TXCLOSE BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C FTIMR bits (Offset 0x138-13B, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C FTISR bits (Offset 0x13C-13F, 32 bits) +//---------------------------------------------------------------------------- +#define FTIMR_FWBT_CMD BIT(18) // 92D_REG, FW BT_CMD interrupt mask +#define FTIMR_RPWM BIT(8) // RPWM INT Status. Write 1 clear. +#define FTIMR_PSTIMER BIT(7) // Enable PSTimer interrupt. +#define FTIMR_TIMEOUT1 BIT(6) // Enable Timer1 interrupt. +#define FTIMR_TIMEOUT0 BIT(5) // Enable Timer0 interrupt. +#define FTIMR_GT4 BIT(4) // Enable General Timer[4] interrupt. +#define FTIMR_GT3 BIT(3) // Enable General Timer[3] interrupt. +#define FTIMR_GT2 BIT(2) // Enable General Timer[2] interrupt. +#define FTIMR_GT1 BIT(1) // Enable General Timer[1] interrupt. +#define FTIMR_GT0 BIT(0) // Enable General Timer[0] interrupt. + +//---------------------------------------------------------------------------- +// 8192C PKTBUF_DBG_CTRL bits (Offset 0x140-143, 32 bits) +//---------------------------------------------------------------------------- +#define RXPKTBUF_DBG BIT(14) // 1: Enable RXPKTBUF debug mode. +#define TXPKTBUF_DBG BIT(13) // 1: Enable TXPKTBUF debug mode. +#define PKTBUF_DBG_ADDR_SHIFT 0 // The address of TRXPKTBUF to be read. +#define PKTBUF_DBG_ADDR_Mask 0x01FFF + +// General Purpose Timer. (Offset 0x150 - 0x16Fh) +//---------------------------------------------------------------------------- +// 8192C TC0_CTRL bits (Offset 0x150-153, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C TC1_CTRL bits (Offset 0x154-157, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C TC2_CTRL bits (Offset 0x158-15B, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C TC3_CTRL bits (Offset 0x15C-15F, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C TC4_CTRL bits (Offset 0x160-163, 32 bits) +//---------------------------------------------------------------------------- +#define TCINT_EN BIT(26) // When write "1" to this bit, Counter starts counting down. +#define TCMODE BIT(25) // Timer/Counter mode. +#define TCEN BIT(24) // Timer/Counter enable. +#define TCData_SHIFT 0 // Timer/Counter data register. It specifies the time-out duration. +#define TCData_Mask 0x0FFFFFF + +//---------------------------------------------------------------------------- +// 8192C TCUNIT_BASE bits (Offset 0x164-165, 16 bits) +//---------------------------------------------------------------------------- +#define TCUNIT_BASE_TIME_SHIFT 0 // num of clocks that equals to the base time unit of timer/counter. +#define TCUNIT_BASE_TIME_Mask 0x03FFF +// General Purpose Timer. (Offset 0x150 - 0x16Fh) + +//---------------------------------------------------------------------------- +// 8192C MBIST_START bits (Offset 0x174-177, 32 bits) +//---------------------------------------------------------------------------- +#define TXLLT_BISTP BIT(10) // TXLLT BIST Start Pulse. +#define TXOQT_BISTP BIT(9) // TXOQT BIST Start Pulse. +#define TXPKT_BISTP BIT(8) // TXPKT Buffer BIST Start Pulse. +#define RXPKT_BISTP BIT(7) // RXPKT Buffer BIST Start Pulse. +#define TXDBUF_BISTP BIT(6) // TXDBUF BIST Start Pulse. +#define TXFIFO_BISTP BIT(5) // TXFIFO BIST Start Pulse. +#define RXFIFO_BISTP BIT(4) // RXFIFO BIST Start Pulse. +#define WKEYLLT_BISTP BIT(3) // WKEY BIST Start Pulse. +#define WRXBA_BISTP BIT(2) // WRXBA BIST Start Pulse. + +//---------------------------------------------------------------------------- +// 8192C MBIST_DONE bits (Offset 0x178-17B, 32 bits) +//---------------------------------------------------------------------------- +#define TXLLT_BISTD BIT(10) // TXLLT BIST Done. +#define TXOQT_BISTD BIT(9) // TXOQT BIST Done. +#define TXPKT_BISTD BIT(8) // TXPKT Buffer BIST Done. +#define RXPKT_BISTD BIT(7) // RXPKT Buffer BIST Done. +#define TXDBUF_BISTD BIT(6) // TXDBUF BIST Done. +#define TXFIFO_BISTD BIT(5) // TXFIFO BIST Done. +#define RXFIFO_BISTD BIT(4) // RXFIFO BIST Done. +#define WKEYLLT_BISTD BIT(3) // WKEY BIST Done. +#define WRXBA_BISTD BIT(2) // WRXBA BIST Done. + +//---------------------------------------------------------------------------- +// 8192C MBIST_FAIL bits (Offset 0x17C-17F, 32 bits) +//---------------------------------------------------------------------------- +#define TXLLT_BISTF BIT(10) // TXLLT BIST Fail. +#define TXOQT_BISTF BIT(9) // TXOQT BIST Fail. +#define TXPKT_BISTF BIT(8) // TXPKT Buffer BIST Fail. +#define RXPKT_BISTF BIT(7) // RXPKT Buffer BIST Fail. +#define TXDBUF_BISTF BIT(6) // TXDBUF BIST Fail. +#define TXFIFO_BISTF BIT(5) // TXFIFO BIST Fail. +#define RXFIFO_BISTF BIT(4) // RXFIFO BIST Fail. +#define WKEYLLT_BISTF BIT(3) // WKEY BIST Fail. +#define WRXBA_BISTF BIT(2) // WRXBA BIST Fail. + +//---------------------------------------------------------------------------- +// 8192C FMETHR bits (Offset 0x1C8-1CB, 32 bits) +//---------------------------------------------------------------------------- +#define FMSG_INT BIT(31) // Toggle this bit will generate interrupt to Host. +#define FW_MSG_SHIFT 0 // User Defined Message. +#define FW_MSG_Mask 0x07FFFFFFF + +//---------------------------------------------------------------------------- +// 8192C HMETFR bits (Offset 0x1CC-1CF, 32 bits) +//---------------------------------------------------------------------------- +#define HRCV_MSG_SHIFT 24 // User Defined Message. +#define HRCV_MSG_Mask 0x0FF +#define INT_BOX3 BIT(3) // MSG_BOX_3 Valid. Enable when the Entry is write. +#define INT_BOX2 BIT(2) // MSG_BOX_2 Valid. Enable when the Entry is write. +#define INT_BOX1 BIT(1) // MSG_BOX_1 Valid. Enable when the Entry is write. +#define INT_BOX0 BIT(0) // MSG_BOX_0 Valid. Enable when the Entry is write. + +//---------------------------------------------------------------------------- +// 8192C LLT_INI bits (Offset 0x1E0-1E3, 32 bits) +//---------------------------------------------------------------------------- +#define LLTE_RWM_SHIFT 30 // +#define LLTE_RWM_Mask 0x03 +#define LLTINI_PDATA_SHIFT 16 // LLT Entry Write/Read DATA for MCU. +#define LLTINI_PDATA_Mask 0x0FF +#define LLTINI_ADDR_SHIFT 8 // LLT Entry Access Offset. +#define LLTINI_ADDR_Mask 0x0FF +#define LLTINI_HDATA_SHIFT 0 // LLT Entry Write/Read DATA for HCI. +#define LLTINI_HDATA_Mask 0x0FF +// LLTE_RWM +#define LLTE_RWM_NO_ACTIVE 0x00 +#define LLTE_RWM_WR 0x01 +#define LLTE_RWM_RD 0x03 + +//---------------------------------------------------------------------------- +// 8192C BB_ACCEESS_CTRL bits (Offset 0x1E8-1EB, 32 bits) +//---------------------------------------------------------------------------- +#define BB_WRITE_READ_SHIFT 30 // +#define BB_WRITE_READ_Mask 0x03 +#define BB_WRITE_EN_SHIFT 12 // Byte Write Enable. +#define BB_WRITE_EN_Mask 0x0F +#define BB_ADDR_SHIFT 2 // Baseband Access Write/Read Address (in DW unit). +#define BB_ADDR_Mask 0x03FF +#define BB_ERRACC BIT(0) // Duplicate Access when previous cycle pending (write one clear). + + +// +// 3. TXDMA/RXDMA Configuration. (Offset 0x200 - 0x2FFh) +// +//---------------------------------------------------------------------------- +// 8192C RQPN bits (Offset 0x200-203, 32 bits) +//---------------------------------------------------------------------------- +#define LD_RQPN BIT(31) // Write 1 to set RQPN bit[79:0] value to page numbers for initialization. +#define LPQ_PUBLIC_DIS BIT(25) // bit=1, available Tx page size excludes the public queue. +#define HPQ_PUBLIC_DIS BIT(24) // bit=1, available Tx page size excludes the public queue. +#define PUBQ_SHIFT 16 // Public Reserved Page Number. +#define PUBQ_Mask 0x0FF +#define LPQ_SHIFT 8 // Low Priority Queue Reserved Page Number. +#define LPQ_Mask 0x0FF +#define HPQ_SHIFT 0 // High Priority Queue Reserved Page Number. +#define HPQ_Mask 0x0FF + +#define _HPQ(x) ((x) & HPQ_Mask) +#define _LPQ(x) (((x) & LPQ_Mask) << LPQ_SHIFT) +#define _PUBQ(x) (((x) & PUBQ_Mask) << PUBQ_SHIFT) +#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register + + +//---------------------------------------------------------------------------- +// 8192C FIFOPAGE bits (Offset 0x204-207, 32 bits) +//---------------------------------------------------------------------------- +#define TXPKTNUM_SHIFT 24 // Packet number in TXPKTBUF. +#define TXPKTNUM_Mask 0x0FF +#define PUB_AVAL_PG_SHIFT 16 // Available Public Queue Page Number. +#define PUB_AVAL_PG_Mask 0x0FF +#define LPQ_AVAL_PG_SHIFT 8 // Available Low Priority Queue Page Number. +#define LPQ_AVAL_PG_Mask 0x0FF +#define HPQ_AVAL_PG_SHIFT 0 // Available High Priority Queue Page Number. +#define HPQ_AVAL_PG_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C TDECTRL bits (Offset 0x208-20B, 32 bits) +//---------------------------------------------------------------------------- +#define LLT_FREE_PAGE_SHIFT 24 // LLT Free Page. +#define LLT_FREE_PAGE_Mask 0x0FF +#define BCN_VALID BIT(16) // bit=1, beacon packet has finished to write to txpktbuffer. +#define BCN_HEAD_SHIFT 8 // head page of Bcnq packet which is Tx DMA filled. +#define BCN_HEAD_Mask 0x0FF +#define BLK_DESC_NUM_SHIFT 4 // The Most Number of Tx Descriptor per Bulk Out Only for USB. +#define BLK_DESC_NUM_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C TXDMA_OFFSET_CHK bits (Offset 0x20C-20F, 32 bits) +//---------------------------------------------------------------------------- +#define PG_UNDER_TH_SHIFT 16 // Page threshold value is check by Tx DMA engine. +#define PG_UNDER_TH_Mask 0x0FF +#define CHK_PG_TH_EN BIT(10) // Enable Tx DMA to check total pages if it is under page threshold. +#define DROP_DATA_EN BIT(9) // Enable Tx DMA to drop the redundant data of packet. +#define CHECK_OFFSET_EN BIT(8) // Enable Tx DMA to check offset value. +#define CHECK_OFFSET_SHIFT 0 // Offset value is check by Tx DMA engine. +#define CHECK_OFFSET_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C TXDMA_STATUS bits (Offset 0x210-213, 32 bits) +//---------------------------------------------------------------------------- +#define PAYLOAD_UDN BIT(14) // Payload is under the packet length of Tx descriptor. +#define PAYLOAD_OVF BIT(13) // Payload is over the packet length of Tx descriptor. +#define DSC_CHKSUM_FAIL BIT(12) // Tx descriptor checksum error. +#define UNKNOWN_QSEL BIT(11) // An unknown QSEL of Tx descriptor is detected. +#define EP_QSEL_DIFF BIT(10) // Tx Endpoint is unmatched with the QSEL of descriptor. +#define TX_OFFS_UNMATCH BIT(9) // Tx offset is unmatched. +#define TXOQT_UDN BIT(8) // TXOQT Underflow. +#define TXOQT_OVF BIT(7) // TXOQT Overflow. +#define TXDMA_SFF_UDN BIT(6) // TXDMA Sync FIFO Underflow. +#define TXDMA_SFF_OVF BIT(5) // TXDMA Sync FIFO Overflow. +#define LLT_NULL_PG BIT(4) // TXDMA reads NULL page. +#define PAGE_UDN BIT(3) // Total pages included PTCL un-return pages under the total reserved pages. +#define PAGE_OVF BIT(2) // Total pages included PTCL un-return pages over the total reserved pages. +#define TXFF_PG_UDN BIT(1) // TXFF page underflow in TDE page controller. +#define TXFF_PG_OVF BIT(0) // TXFF page overflow in TDE page controller. + +//---------------------------------------------------------------------------- +// 8192C RXDMA_AGG_PG_TH bits (Offset 0x280-283, 32 bits) +//---------------------------------------------------------------------------- +#define RXDMA_AGG_PG_TH_LMT(x) ((x & 0x0FF)<<0) // DMA inform host to receive pkts, when exceeds the threshold. + +//---------------------------------------------------------------------------- +// 8192C RXPKT_NUM bits (Offset 0x284-287, 32 bits) +//---------------------------------------------------------------------------- +#define RXPKT_NUM_LMT_SHIFT 24 // number of packets in RXPKTBUF. +#define RXPKT_NUM_LMT_Mask 0x0FF +#define RW_RELEASE_EN BIT(18) // bit=1, RXDMA will enter this mode after RXDMA packet to host completed and stop. +#define RXDMA_IDLE BIT(17) // RXDMA finishes DMA will report idle state in this bit. +#define RXPKT_RELEASE_POLL BIT(16) // bit=1, RXDMA will decrease RX PKT counter by one. +#define FW_UPD_RDPTR_SHIFT 0 // FW updates before write RXPKT_RELEASE_POLL to 1. +#define FW_UPD_RDPTR_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C RXDMA_STATUS bits (Offset 0x288-28B, 32 bits) +//---------------------------------------------------------------------------- +#define FW_POLL_ISSUE BIT(5) // FW Release Poll Error. +#define RX_DATA_UDN BIT(4) // RX Data Underflow. Clear by SW. +#define RX_SFF_UDN BIT(3) // RX Sync FIFO Underflow. +#define RX_SFF_OVF BIT(2) // RX Sync FIFO Overflow. +#define USB_REQ_LEN_OVF BIT(1) // USB RXAGGEN Error due to RX length overflow. +#define RXPKT_OVF BIT(0) // When RX Packet is more than 255 packets remaining in FF. + + +// +// 4. PCIE EMAC Reserved Region. (Offset 0x300 - 0x3FFh) +// +//---------------------------------------------------------------------------- +// 8192C PCIE_CTRL_REG bits (Offset 0x300-303, 32 bits) +//---------------------------------------------------------------------------- +#define MAX_RXDMA_SHIFT 28 // RXDMA Burst Size selection. +#define MAX_RXDMA_Mask 0x07 +#define MAX_TXDMA_SHIFT 24 // TXDMA Burst Size selection. +#define MAX_TXDMA_Mask 0x07 +#define En_HWENTRL BIT(19) // Enable HW call EMAC to enter L23 actively. +#define EN_SWENTR_L23 BIT(17) // Enable SW call EMAC to enter L23. +#define EN_HWEXITL1 BIT(16) // Enable HW call EMAC to exit L1. +#define BCNQSTOP BIT(15) // BCNQ DMA STOP. +#define HQSTOP BIT(14) // HQ DMA STOP. +#define MGQSTOP BIT(13) // VOKQ DMA STOP. +#define VOQSTOP BIT(12) // VOKQ DMA STOP. +#define VIQSTOP BIT(11) // VIQ DMA STOP. +#define BEQSTOP BIT(10) // BEQ DMA STOP. +#define BKQSTOP BIT(9) // BKQ DMA STOP. +#define RXQSTOP BIT(8) // RX DMA STOP. +#define HQ_POLL BIT(7) // High Queue Polling bit, read result will be hpqflag. +#define MGQ_POLL BIT(6) // Manag Queue Polling bit, read result will be mgqflag. +#define BCNQ_POLL BIT(4) // BCNQ Polling bit, read result will be bpqflag. +#define VOQ_POLL BIT(3) // VOQ Polling bit, read result will be voqflag. +#define VIQ_POLL BIT(2) // VIQ Polling bit, read result will be viqflag. +#define BEQ_POLL BIT(1) // BEQ Polling bit, read result will be beqflag. +#define BKQ_POLL BIT(0) // BKQ Polling bit, read result will be bkqflag. + +//---------------------------------------------------------------------------- +// 8192C INT_MIG bits (Offset 0x304-307, 32 bits) +//---------------------------------------------------------------------------- +#define TTMRMIT_Shift 28 // 92D_REG, Tx timer mitigation +#define TTMRMIT_Mask 0x0F +#define TNUMMIT_Shift 24 // 92D_REG, Tx number mitigation +#define TNUMMIT_Mask 0x0F +#define RTMRMIT_Shift 20 // 92D_REG, Rx timer mitigation +#define RTMRMIT_Mask 0x0F +#define RNUMMIT_Shift 16 // 92D_REG, Rx number mitigation +#define RNUMMIT_Mask 0x0F +#define INTMT_SHIFT 16 // Interrupt Couter for setting Interrupt Migration. +#define INTMT_Mask 0x0FFFF +#define MIGRATE_TIMER_SHIFT 0 // Timer for setting Interrupt Migration. +#define MIGRATE_TIMER_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C DBI bits (Offset 0x348-353, 96 bits) +//---------------------------------------------------------------------------- +#define DBI_ACC_EXT BIT(19) // 92D_REG, DBI access external register on ELBI +#define DBI_MACSEL BIT(18) // 92D_REG, DBI access MAC1 select +#define DBI_RFLAG BIT(17) // DBI Read Flag. +#define DBI_WFLAG BIT(16) // DBI Write Flag. +#define DBI_WREN_SHIFT 12 // DBI Write Enable, High active. +#define DBI_WREN_Mask 0x0F +#define DBI_ADDR_SHIFT 0 // DBI Address. +#define DBI_ADDR_Mask 0x0FFF + +//----------------------------------------------------------------------------// +// 8192C MDIO bits (Offset 0x354-35B, 64 bits) +//---------------------------------------------------------------------------- +#define ECRC_EN BIT(7) // ECRC Enable. +#define MDIO_RFLAG BIT(6) // MDIO Read Flag. +#define MDIO_WFLAG BIT(5) // MDIO Write Flag. +#define MDIO_ADDR_SHIFT 0 // MDIO Address. +#define MDIO_ADDR_Mask 0x01F + +#define MDIO_RDATA_SHIFT 16 // MDIO Read Data. +#define MDIO_RDATA_Mask 0x0FFFF +#define MDIO_WDATA_SHIFT 0 // MDIO Write Data. +#define MDIO_WDATA_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C UART_CTRL bits (Offset 0x364-36B, 64 bits) +//---------------------------------------------------------------------------- +#define UART_WDATA_H_SHIFT 0 // UART Write Data [31:8], read will be UART Read Data[31:8]. +#define UART_WDATA_H_Mask 0x0FFFFFF + +#define UART_DMA_STS_SHIFT 24 // UART DMA Status. +#define UART_DMA_STS_Mask 0x07 +#define UART_DMA_MOD BIT(20) // UART DMA Mode. +#define UART_RDMA BIT(19) // UART RX DMA Flag. +#define UART_TDMA BIT(18) // UART TX DMA Flag. +#define UART_RCMD BIT(17) // UART Read Command. +#define UART_WCMD BIT(16) // UART Write Command. +#define UART_ADDR_SHIFT 10 // UART Address. +#define UART_ADDR_Mask 0x03F +#define UART_WDATA_L_SHIFT 0 // UART Write Data [7:0], read will be UART Read Data[7:0]. +#define UART_WDATA_L_Mask 0x0FF + + +// +// 5. PTCL/EDCA Configuration. (Offset 0x400 - 0x4FFh) +// +//---------------------------------------------------------------------------- +// 8192C VOQ_INFO bits (Offset 0x400-403, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C VIQ_INFO bits (Offset 0x404-407, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C BEQ_INFO bits (Offset 0x408-40B, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C BKQ_INFO bits (Offset 0x40C-40F, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C MGQ_INFO bits (Offset 0x410-413, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C HIQ_INFO bits (Offset 0x414-417, 32 bits) +//---------------------------------------------------------------------------- +#define Q_CPU_HEAD_SHIFT 24 // MCU will handle q_pkt head. +#define Q_CPU_HEAD_Mask 0x0FF +#define Q_PKT_NUM_SHIFT 16 // total Q pkt number in TxPktbuffer. +#define Q_PKT_NUM_Mask 0x0FF +#define Q_FW_NUM_SHIFT 8 // total Q FW number in TxPktbuffer. +#define Q_FW_NUM_Mask 0x0FF +#define Q_HEAD_PG_SHIFT 0 // head page of the first packet of Q. +#define Q_HEAD_PG_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C BCNQ_INFO bits (Offset 0x418-41A, 24 bits) +//---------------------------------------------------------------------------- +#define BCNQ_PKT_NUM_SHIFT 16 // total BCNQ pkt number in TxPktbuffer. +#define BCNQ_PKT_NUM_Mask 0x0FF +#define BCNQ_FW_NUM_SHIFT 8 // total BCNQ FW number in TxPktbuffer. +#define BCNQ_FW_NUM_Mask 0x0FF +#define BCNQ_HEAD_PG_SHIFT 0 // head page of the first packet of BCNQ. +#define BCNQ_HEAD_PG_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C TXPKT_EMPTY bits (Offset 0x41B, 8 bits) +//---------------------------------------------------------------------------- +#define BCNQ_EMPTY BIT(7) // queue is empty. Report by MAC. +#define HQQ_EMPTY BIT(6) // queue is empty. Report by MAC. +#define HMGQ_EMPTY BIT(5) // queue is empty. Report by MAC. +#define CMGQ_EMPTY BIT(4) // queue is empty. Report by MAC. +#define BKQ_EMPTY BIT(3) // queue is empty. Report by MAC. +#define BEQ_EMPTY BIT(2) // queue is empty. Report by MAC. +#define VIQ_EMPTY BIT(1) // queue is empty. Report by MAC. +#define VOQ_EMPTY BIT(0) // queue is empty. Report by MAC. + +//---------------------------------------------------------------------------- +// 8192C CPU_MGQ_INFO bits (Offset 0x41C-41F, 32 bits) +//---------------------------------------------------------------------------- +#define CPUMGQ_FW_NUM_SHIFT 8 // total CPU MGQ fw number in TxPktbuffer. +#define CPUMGQ_FW_NUM_Mask 0x0FF +#define CPUMGQ_HEAD_PG_SHIFT 0 // head page of CPU MGQ. +#define CPUMGQ_HEAD_PG_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C FWHW_TXQ_CTRL bits (Offset 0x420-422, 24 bits) +//---------------------------------------------------------------------------- +#define RTS_LIMIT_IN_OFDM BIT(23) // 92D_REG, rts rate will not down to cck rate +#define EN_BCNQ_DL BIT(22) // 92D_REG, 1: ptcl consider there is bcn pkt in txbuf; 0: mask bcn pkt num in bcnq +#define EN_RD_RESP_NAV_BK BIT(21) // Control the RD responder NAV criteria for TX. +#define EN_WR_FREE_TAIL BIT(20) // 1:Drive wirte Bcnq_boundary,Hw set free_tail in Boundary-1; 0:no update. +#define CHK_LOSS_QSEL_SHIFT 17 // +#define CHK_LOSS_QSEL_Mask 0x07 +#define EN_CHECK_LOSS BIT(16) // bit=1, HW will monitor packet loss from TXDMA. +#define EN_QUEUE_RPT_SHIFT 8 // 1: HW will report tx_status 0: no report. +#define EN_QUEUE_RPT_Mask 0x07F +#define EN_AMPDU_RTY_NEW BIT(7) // AMPDU aggregation mode with retry MPDUs and new MPDUs. +#define LIFETIME_EN BIT(6) // Enable lift time drop. +#define EN_CPU_HANDLE_SHIFT 0 // PKT need cpu handle. +#define EN_CPU_HANDLE_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C HWSEQ_CTRL bits (Offset 0x423, 8 bits) +//---------------------------------------------------------------------------- +#define HWSEQ_BCN_EN BIT(6) // +#define HWSEQ_HI_EN BIT(5) // +#define HWSEQ_MGT_EN BIT(4) // +#define HWSEQ_BK_EN BIT(3) // +#define HWSEQ_BE_EN BIT(2) // +#define HWSEQ_VI_EN BIT(1) // +#define HWSEQ_VO_EN BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C MULTI_BCNQ_EN bits (Offset 0x426, 8 bits) +//---------------------------------------------------------------------------- +#define MBID_BCNQ7_EN BIT(7) // +#define MBID_BCNQ6_EN BIT(6) // +#define MBID_BCNQ5_EN BIT(5) // +#define MBID_BCNQ4_EN BIT(4) // +#define MBID_BCNQ3_EN BIT(3) // +#define MBID_BCNQ2_EN BIT(2) // +#define MBID_BCNQ1_EN BIT(1) // +#define MBID_BCNQ0_EN BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C MULTI_BCNQ_OFFSET bits (Offset 0x427, 8 bits) +//---------------------------------------------------------------------------- +#define MBCNQ_OFFSET_SHIFT 0 // page number between two consecutive BCNQ head page. +#define MBCNQ_OFFSET_Mask 0x03 + +//---------------------------------------------------------------------------- +// 8192C SPEC_SIFS bits (Offset 0x428-429, 16 bits) +//---------------------------------------------------------------------------- +#define SPEC_SIFS_OFDM_SHIFT 8 // spec SIFS value for duration calculation. +#define SPEC_SIFS_OFDM_Mask 0x0FF +#define SPEC_SIFS_CCK_SHIFT 0 // spec SIFS value for duration calculation. +#define SPEC_SIFS_CCK_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C RL bits (Offset 0x42A-42B, 16 bits) +//---------------------------------------------------------------------------- +#define SRL_SHIFT 8 // Short Retry Limit. +#define SRL_Mask 0x03F +#define LRL_SHIFT 0 // Long Retry Limit. +#define LRL_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C DARFRC bits (Offset 0x430-437, 64 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C RARFRC bits (Offset 0x438-43F, 64 bits) +//---------------------------------------------------------------------------- +#define ARF_RC8_SHIFT 24 // Response Auto Rate Fallback Retry Count. +#define ARF_RC8_Mask 0x01F +#define ARF_RC7_SHIFT 16 // Response Auto Rate Fallback Retry Count. +#define ARF_RC7_Mask 0x01F +#define ARF_RC6_SHIFT 8 // Response Auto Rate Fallback Retry Count. +#define ARF_RC6_Mask 0x01F +#define ARF_RC5_SHIFT 0 // Response Auto Rate Fallback Retry Count. +#define ARF_RC5_Mask 0x01F + +#define ARF_RC4_SHIFT 24 // Response Auto Rate Fallback Retry Count. +#define ARF_RC4_Mask 0x01F +#define ARF_RC3_SHIFT 16 // Response Auto Rate Fallback Retry Count. +#define ARF_RC3_Mask 0x01F +#define ARF_RC2_SHIFT 8 // Response Auto Rate Fallback Retry Count. +#define ARF_RC2_Mask 0x01F +#define ARF_RC1_SHIFT 0 // Response Auto Rate Fallback Retry Count. +#define ARF_RC1_Mask 0x01F + +//---------------------------------------------------------------------------- +// 8192C RRSR bits (Offset 0x440-442, 24 bits) +//---------------------------------------------------------------------------- +#define RRSR_SHORT BIT(23) // Respond with short preamble packet. Default is long preamble. +#define RRSR_RSC_SHIFT 21 // Response frame sub-channel configuration. +#define RRSR_RSC_Mask 0x03 +#define RRSC_BITMAP_SHIFT 0 // Response Auto Rate Fallback Retry Count. +#define RRSC_BITMAP_Mask 0x0FFFFF + +//---------------------------------------------------------------------------- +// 8192C AGGLEN_LMT bits (Offset 0x458-45B, 32 bits) +//---------------------------------------------------------------------------- +#define AGGLMT_MCS15S_SHIFT 28 // Aggregation Limit for MCS 15 SGI in the units of number of MPDUs. +#define AGGLMT_MCS15S_Mask 0x0F +#define AGGLMT_MCS15_SHIFT 24 // Aggregation Limit for MCS 13~15 in the units of number of MPDUs. +#define AGGLMT_MCS15_Mask 0x0F +#define AGGLMT_MCS12_SHIFT 20 // Aggregation Limit for MCS 11~12 in the units of number of MPDUs. +#define AGGLMT_MCS12_Mask 0x0F +#define AGGLMT_MCS10_SHIFT 16 // Aggregation Limit for MCS 8~10 in the units of number of MPDUs. +#define AGGLMT_MCS10_Mask 0x0F +#define AGGLMT_MCS7S_SHIFT 12 // Aggregation Limit for MCS 7 SGI in the units of number of MPDUs. +#define AGGLMT_MCS7S_Mask 0x0F +#define AGGLMT_MCS7_SHIFT 8 // Aggregation Limit for MCS 6~7 in the units of number of MPDUs. +#define AGGLMT_MCS7_Mask 0x0F +#define AGGLMT_MCS5_SHIFT 4 // Aggregation Limit for MCS 3~5 in the units of number of MPDUs. +#define AGGLMT_MCS5_Mask 0x0F +#define AGGLMT_MCS2_SHIFT 0 // Aggregation Limit for MCS 0~2 in the units of number of MPDUs. +#define AGGLMT_MCS2_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C AMPDU_MIN_SPACE bits (Offset 0x45C, 8 bits) +//---------------------------------------------------------------------------- +#define MIN_SPACE_SHIFT 0 // The spacing between sub-frame. +#define MIN_SPACE_Mask 0x07 + +//---------------------------------------------------------------------------- +// 8192C FAST_EDCA_CTRL bits (Offset 0x460-462, 24 bits) +//---------------------------------------------------------------------------- +#define FAST_EDCA_TO_SHIFT 16 // If pkt timeout, HW will contend channel using fast backoff. +#define FAST_EDCA_TO_Mask 0x01F +#define FAST_EDCA_PKT_TH_SHIFT 0 // If pkt in txpktbuffer over thrs. HW will fast backoff. +#define FAST_EDCA_PKT_TH_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C RD_RESP_PKT_TH bits (Offset 0x463, 8 bits) +//---------------------------------------------------------------------------- +#define RD_RESP_PKT_TH_LMT_SHIFT 0 // granted ACq pkt num beyond this, responder set More PPDU=1 & piggyback. +#define RD_RESP_PKT_TH_LMT_Mask 0x01F + +//---------------------------------------------------------------------------- +// 8192C INIRTS_RATE_SEL bits (Offset 0x480, 8 bits) +//---------------------------------------------------------------------------- +#define INIRTSMCS_SEL_SHIFT 0 // initial rate for Control type frame transmitted as EDCA originator. +#define INIRTSMCS_SEL_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C POWER_STAGE1 bits (Offset 0x4B4-4B6, 24 bits) +//---------------------------------------------------------------------------- +#define PWR_STAGE1_SHIFT 0 // User define Power Stage1. +#define PWR_STAGE1_Mask 0x0FFFFFF + +//---------------------------------------------------------------------------- +// 8192C POWER_STAGE2 bits (Offset 0x4B8-4BA, 24 bits) +//---------------------------------------------------------------------------- +#define PWR_STAGE2_SHIFT 0 // User define Power Stage2. +#define PWR_STAGE2_Mask 0x0FFFFFF + +//---------------------------------------------------------------------------- +// 8192C STBC_SETTING bits (Offset 0x4C4, 8 bits) +//---------------------------------------------------------------------------- +#define NESS_SHIFT 2 // +#define NESS_Mask 0x03 +#define STBC_CFEND_SHIFT 0 // CFEND STBC. +#define STBC_CFEND_Mask 0x03 + +//---------------------------------------------------------------------------- +// 8192C PROT_MODE_CTRL bits (Offset 0x4C8-4C9, 16 bits) +//---------------------------------------------------------------------------- +#define RTS_TXTIME_TH_SHIFT 8 // RTS pkt txtime thrs +#define RTS_TXTIME_TH_Mask 0x0FF +#define RTS_LEN_TH_SHIFT 0 // RTS Length thrs. +#define RTS_LEN_TH_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C BAR_MODE_CTRL bits (Offset 0x4CC-4CE, 24 bits) +//---------------------------------------------------------------------------- +#define BAR_RTY_LMT_SHIFT 16 // BAR retry limit. +#define BAR_RTY_LMT_Mask 0x03 +#define BAR_PKT_TXTIME_TH_SHIFT 8 // BAR pkt txtime thrs. +#define BAR_PKT_TXTIME_TH_Mask 0x0FF +#define BAR_PKTNUM_TH_SHIFT 0 // BAR Pktnum Thrs. +#define BAR_PKTNUM_TH_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C RA_TRY_RATE_AGG_LMT bits (Offset 0x4CF, 8 bits) +//---------------------------------------------------------------------------- +#define RA_BAR_RTY_LMT_SHIFT 5 // BAR retry limit. +#define RA_BAR_RTY_LMT_Mask 0x07 +#define RA_TRY_RATE_AGG_LMT_NUM_SHIFT 0 // aggr pkt num limit for try up rate of when desc try bit=1. +#define RA_TRY_RATE_AGG_LMT_NUM_Mask 0x01F + +//---------------------------------------------------------------------------- +// 8192C NQOS_SEQ bits (Offset 0x4DC-4DD, 16 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C QOS_SEQ bits (Offset 0x4DE-4DF, 16 bits) +//---------------------------------------------------------------------------- +#define N_QOS_SSN_SHIFT 0 // TXDESC HWSEQEN is set, MAC will overwrite SEQ control by this. + // TXDESC HWSEQEN is set and QoS field is also set, + // MAC will overwrite SEQ control by this. +#define N_QOS_SSN_Mask 0x0FFF + +//---------------------------------------------------------------------------- +// 8192C NEED_CPU_HANDLE bits (Offset 0x4E0, 8 bits) +//---------------------------------------------------------------------------- +#define NEED_CPU_HANDLE_Q_SHIFT 0 // 1:HW prepare ok, this q need cpu handle & poll. +#define NEED_CPU_HANDLE_Q_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C PTCL_ERR_STATUS bits (Offset 0x4E1, 8 bits) +//---------------------------------------------------------------------------- +#define PTCL_TL_PG_OVF BIT(7) // Protocol Total Page out of range. +#define TXHANG_ERR BIT(5) // TX time is greater than 32ms. +#define HW_RD_NULL_STATUS_ERR BIT(4) // HW read null page counter error. +#define HW_RD_NULL_CTN_ERR BIT(3) // HW Contention read null page counter error. +#define HW_RD_NULL_CNT_ERR BIT(2) // HW read null page counter error. +#define PTCL_TL_PG_ERR BIT(1) // Protocol Total page number error. +#define DESC_QSEL_ERR BIT(0) // TXDESC QSEL field mismatch error. + +//---------------------------------------------------------------------------- +// 8192C PKT_LOSE_RPT bits (Offset 0x4E2, 8 bits) +//---------------------------------------------------------------------------- +#define PKT_LOSE_BK BIT(3) // 1:queue happen pkt lose, 0:no lose. +#define PKT_LOSE_BE BIT(2) // 1:queue happen pkt lose, 0:no lose. +#define PKT_LOSE_VI BIT(1) // 1:queue happen pkt lose, 0:no lose. +#define PKT_LOSE_VO BIT(0) // 1:queue happen pkt lose, 0:no lose. + + +//---------------------------------------------------------------------------- +// 8192C EDCA_VO_PARA bits (Offset 0x500-503, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C EDCA_VI_PARA bits (Offset 0x504-507, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C EDCA_BE_PARA bits (Offset 0x508-50B, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C EDCA_BK_PARA bits (Offset 0x50C-50F, 32 bits) +//---------------------------------------------------------------------------- +#define TXOP_SHIFT 16 // TXOP Limit. +#define TXOP_Mask 0x0FFFF +#define CW_SHIFT 8 // ECWmax/ECWmin +#define CW_Mask 0x0FF +#define AIFS_SHIFT 0 // Arbitrary Inter frame space. +#define AIFS_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C BCNTCFG bits (Offset 0x510-511, 16 bits) +//---------------------------------------------------------------------------- +#define BCNECW_SHIFT 8 // Beacon Contention Window. +#define BCNECW_Mask 0x0F +#define BCNIFS_SHIFT 0 // Beacon Interframe Space. +#define BCNIFS_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C SIFS_CCK bits (Offset 0x514-515, 16 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C SIFS_OFDM bits (Offset 0x516-517, 16 bits) +//---------------------------------------------------------------------------- +#define SIFS_TRX_SHIFT 8 // SIFS time required for any immediate response. +#define SIFS_TRX_Mask 0x0FF +#define SIFS_CTX_SHIFT 0 // SIFS time required for consecutive TX events. +#define SIFS_CTX_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C TX_PTCL_CTRL bits (Offset 0x520-521, 16 bits) +//---------------------------------------------------------------------------- +#define DIS_CCA BIT(15) // bit=1, disable CCA. +#define SIFS_BK_EN BIT(12) // SIFS Break Check Criteria enable for AMPDU aggregation. +#define TXQ_NAV_MSK_SHIFT 8 // 1:Queue BKF must wait TX Nav finished, 0:Queue not need wait. +#define TXQ_NAV_MSK_Mask 0x0F +#define DIS_CW BIT(7) // bit=1, disable CW. +#define RDG_END_TXOP BIT(6) // 1:Nav protect all txop, 0:Nav protect to next pkt. +#define NAV_END_TXOP BIT(5) // 1:Nav protect all txop, 0:Nav protect to next pkt. +#define AC_INBCN_HOLD BIT(4) // bit=1, HI queue will be sent first, and then AC queue will be sent. +#define MGTQ_TXOP_EN BIT(3) // bit=1, MGTQ may sent packets by using ACQ TXOP. +#define MGTQ_RTSMF_HOLD BIT(2) // bit=1, MGTQ will be hold until RTS or MF transaction finished. +#define HIQ_RTSMF_HOLD BIT(1) // bit=1, HIQ will be hold until RTS or MF transaction finished. +#define BCN_RTSMF_HOLD BIT(0) // bit=1, BCNQ will be hold until RTS or MF transaction finished. + +//---------------------------------------------------------------------------- +// 8192C TXPAUSE bits (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +#define STOP_BCN BIT(6) // Stop BCNQ Queue. +#define STOP_HI BIT(5) // Stop High Queue. +#define STOP_MGT BIT(4) // Stop Management Queue. +#define STOP_BK BIT(3) // Stop BK Queue. +#define STOP_BE BIT(2) // Stop BE Queue. +#define STOP_VI BIT(1) // Stop VI Queue. +#define STOP_VO BIT(0) // Stop VO Queue. + +//---------------------------------------------------------------------------- +// 8192C DIS_TXREQ_CLR bits (Offset 0x523, 8 bits) +//---------------------------------------------------------------------------- +#define DIS_TXREQ_CLR_BCN BIT(7) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_HI BIT(5) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_MGQ BIT(4) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_VO BIT(3) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_VI BIT(2) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_BE BIT(1) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. +#define DIS_TXREQ_CLR_BK BIT(0) // 1:if queue can't own channel ,txcmd will be cleared;0:Only TX_finish can clear txreq. + +//---------------------------------------------------------------------------- +// 8192C RD_CTRL bits (Offset 0x524-525, 16 bits) +//---------------------------------------------------------------------------- +#define HIQ_NO_LMT_EN BIT(12) +#define EDCCA_MSK_CNTDWN BIT(11) // 1: disable, 0: enable, EDCCA count down. +#define DIS_TXOP_CFE BIT(10) // Disable TXOP_CFE function. +#define DIS_LSIG_CFE BIT(9) // Disable LSIG_TXOP CF-END function. +#define DIS_STBC_CFE BIT(8) // Disable STBC CF-END function. +#define BKQ_RD_INIT_EN BIT(7) // +#define BEQ_RD_INIT_EN BIT(6) // +#define VIQ_RD_INIT_EN BIT(5) // +#define VOQ_RD_INIT_EN BIT(4) // +#define BKQ_RD_RESP_EN BIT(3) // +#define BEQ_RD_RESP_EN BIT(2) // +#define VIQ_RD_RESP_EN BIT(1) // +#define VOQ_RD_RESP_EN BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C TBTT_PROHIBIT bits (Offset 0x540-541, 16 bits) +//---------------------------------------------------------------------------- +#define TBTT_HOLD_TIME_SHIFT 8 // TBTT_prohibit_hold, unit is 32 us. +#define TBTT_HOLD_TIME_Mask 0xFFFFFF +#define TBTT_PROHIBIT_SETUP_SHIFT 0 // TBTT_prohibit_setup, unit is 32us. +#define TBTT_PROHIBIT_SETUP_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C BCN_CTRL bits (Offset 0x550, 8 bits) +//---------------------------------------------------------------------------- + +#define DIS_SUB_STATE BIT(4) +#define DIS_SUB_STATE_N BIT(1) +#define DIS_TSF_UPDATE BIT(5) +#define DIS_TSF_UPDATE_N BIT(4) +#define DIS_ATIM BIT(0) + + +#define BCN0_AUTO_SYNC BIT(5) // When this bit is set, TSFTR will update the timestamp in Beacon matched BSSID. +#define DIS_TSF_UPT BIT(4) // 92D_REG, When this bit is set, tsf will not update +#define EN_BCN_FUNCTION BIT(3) // bit=1, TSF and other beacon related functions are then enabled. +#define EN_TXBCN_RPT BIT(2) // +#define EN_MBSSID BIT(1) // +#define PBCNQSEL BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C USTIME_TSF bits (Offset 0x551, 8 bits) +//---------------------------------------------------------------------------- +#define USTIME_TSF_TIME_SHIFT 0 // Set the microsecond time unit used by MAC TSF clock. +#define USTIME_TSF_TIME_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C MBID_NUM bits (Offset 0x552, 8 bits) +//---------------------------------------------------------------------------- +#define MBID_BCN_NUM_SHIFT 0 // num of virtual interface num excluding the root. +#define MBID_BCN_NUM_Mask 0x07 + +//---------------------------------------------------------------------------- +// 8192C MBSSID_BCN_SPACE bits (Offset 0x554-557, 32 bits) +//---------------------------------------------------------------------------- +#define BCN_SPACE2_SHIFT 16 // +#define BCN_SPACE2_Mask 0x0FFFF +#define BCN_SPACE1_SHIFT 0 // +#define BCN_SPACE1_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C ACMHWCTRL bits (Offset 0x5C0, 8 bits) +//---------------------------------------------------------------------------- +#define VOQ_ACM_STATUS BIT(6) // indicates if the used_time >= admitted_time of AC VO when HW ACM. +#define VIQ_ACM_STATUS BIT(5) // indicates if the used_time >= admitted_time of AC VI when HW ACM. +#define BEQ_ACM_STATUS BIT(4) // indicates if the used_time >= admitted_time of AC BE when HW ACM. +#define VOQ_ACM_EN BIT(3) // enable ACM of VO queue. +#define VIQ_ACM_EN BIT(2) // enable ACM of VI queue. +#define BEQ_ACM_EN BIT(1) // enable ACM of BE queue. +#define ACMHWEN BIT(0) // enable hardware to take control of ACM. + +//---------------------------------------------------------------------------- +// 8192C ACMRSTCTRL bits (Offset 0x5C1, 8 bits) +//---------------------------------------------------------------------------- +#define VO_ACM_RST_USED_TIME BIT(2) // HwEn enabled, sw set this to inform hw to reset used_time. +#define BE_ACM_RST_USED_TIME BIT(1) // HwEn enabled, sw set this to inform hw to reset used_time. +#define VI_ACM_RST_USED_TIME BIT(0) // HwEn enabled, sw set this to inform hw to reset used_time. + + +// +// 6. WMAC Configuration. (Offset 0x600 - 0x7FFh) +// +//---------------------------------------------------------------------------- +// 8192C APSD_CTRL bits (Offset 0x600, 8 bits) +//---------------------------------------------------------------------------- +#define APSDOFF_STATUS BIT(7) // +#define APSDOFF BIT(6) // bit=1, MAC issue sleep signal to disable BB/AFE/RF TRX function. + +//---------------------------------------------------------------------------- +// 8192C BWOPMODE bits (Offset 0x603, 8 bits) +//---------------------------------------------------------------------------- +#define BW_20M BIT(2) // bit=1 indicate operating in 20Mhz bandwidth. + +//---------------------------------------------------------------------------- +// 8192C TCR bits (Offset 0x604-607, 32 bits) +//---------------------------------------------------------------------------- +#define TSFT_CMP_SHIFT 16 // TSFT insertion compensation value. +#define TSFT_CMP_Mask 0x0FF +#define WMAC_TCR_ERRSTEN3 BIT(15) // 92D_REG, Use phytxend_ps to reset mactx state machine +#define WMAC_TCR_ERRSTEN2 BIT(14) // 92D_REG, If txd fifo underflow when txtype is cmpba, reset mactx state machine +#define WMAC_TCR_ERRSTEN1 BIT(13) // 92D_REG, If txd fifo underflow, reset mactx state machine +#define WMAC_TCR_ERRSTEN0 BIT(12) // 92D_REG, Phytxend_ps comes but mactx still active, reset mactx state machine +#define WMAC_TCR_TXSK_PERPKT BIT(11) // 92D_REG, Serche key for each mpdu +#define ICV BIT(10) // Integrity Check Value. +#define CFE_FORM BIT(9) // CF-End Frame Format. +#define CRC BIT(8) // Append 32-bit Cyclic Redundancy Check. +#define PWRBIT_OW_EN BIT(7) // bit=1, MAC overwrite pwr bit according to PWR_ST for data frame. +#define PWR_ST BIT(6) // MAC will overwrite pwr bit accroding to PWR_ST for data frame. +#define PAD_SEL BIT(2) // AMPDU Padding pattern selection. +#define DIS_GCLK BIT(1) // Disable MACTX clock gating control. +#define TSFRST BIT(0) // Reset TSF Timer to zero. + +//---------------------------------------------------------------------------- +// 8192C RCR bits (Offset 0x608-60B, 32 bits) +//---------------------------------------------------------------------------- +#define RCR_APP_FCS BIT(31) // wmac RX will append FCS after payload. +#define RCR_APP_MIC BIT(30) // bit=1, MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT(29) // bit=1, MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYSTS BIT(28) // Append RXFF0 PHY Status Enable. +#define RCR_APP_BASSN BIT(27) // Append SSN of previous TXBA Enable. +#define RCR_MBID_EN BIT(24) // Enable Multiple BssId. +#define RCR_LSIGEN BIT(23) // Enable LSIG TXOP Protection function. +#define RCR_MFBEN BIT(22) // Enable immediate MCS Feedback function. +#define RCR_BM_DATA_EN BIT(17) // BM_DATA_EN. +#define RCR_UC_DATA_EN BIT(16) // Unicast data packet interrupt enable. +#define RCR_HTC_LOC_CTRL BIT(14) // 1: HTC -> MFC, 0: MFC-> HTC. +#define RCR_AMF BIT(13) // Accept Management Frame. +#define RCR_ACF BIT(12) // Accept Control Frame. +#define RCR_ADF BIT(11) // Accept Data Frame. +#define RCR_AICV BIT(9) // Accept Integrity Check Value Error packets. +#define RCR_ACRC32 BIT(8) // Accept CRC32 Error packets. + +#define RCR_CBSSID_ADHOC (BIT(6)|BIT(7)) // Check BSSID. +#define RCR_CBSSID BIT(6) // Check BSSID. +#define RCR_APWRMGT BIT(5) // Accept Power Management Packet. +#define RCR_ADD3 BIT(4) // Accept Address 3 Match Packets. +#define RCR_AB BIT(3) // Accept Broadcast packets. +#define RCR_AM BIT(2) // Accept Multicast packets. +#define RCR_APM BIT(1) // Accept Physical Match packets. +#define RCR_AAP BIT(0) // Accept Destination Address packets. + +//---------------------------------------------------------------------------- +// 8192C RX_PKT_LIMIT bits (Offset 0x60C, 8 bits) +//---------------------------------------------------------------------------- +#define RXPKTLMT_SHIFT 0 // RX PKT Upper Limit. +#define RXPKTLMT_Mask 0x03F + +// MACID Setting Register. (Offset 0x610 - 0x62Fh) +//---------------------------------------------------------------------------- +// 8192C MBIDCAMCFG bits (Offset 0x628-62F, 64 bits) +//---------------------------------------------------------------------------- +#define MBIDCAM_POLL BIT(31) // Pooling bit. +#define MBIDWRITE_EN BIT(30) // Write Enable. +#define MBIDCAM_ADDR_SHIFT 24 // CAM Address. +#define MBIDCAM_ADDR_Mask 0x01F +#define MBIDCAM_VALID BIT(23) // CAM Valid bit. + +// MACID Setting Register. (Offset 0x610 - 0x62Fh) + +// Timing Control Register. (Offset 0x630 - 0x64Fh) +//---------------------------------------------------------------------------- +// 8192C SPEC_SIFS bits (Offset 0x63A-63B, 16 bits) +//---------------------------------------------------------------------------- +#define SPEC_SIFS_OFDM_SHIFT 8 // SIFS value for duration calculation. +#define SPEC_SIFS_OFDM_Mask 0x0FF +#define SPEC_SIFS_CCK_SHIFT 0 // SIFS value for duration calculation. +#define SPEC_SIFS_CCK_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C RESP_SIFS_CCK bits (Offset 0x63C-63D, 16 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8192C RESP_SIFS_OFDM bits (Offset 0x63E-63F, 16 bits) +//---------------------------------------------------------------------------- +#define SIFS_R2T_SHIFT 8 // SIFS time required for any immediate response. +#define SIFS_R2T_Mask 0x0FF +#define SIFS_T2T_SHIFT 0 // SIFS time required for consecutive TX events. +#define SIFS_T2T_Mask 0x0FF + +// Timing Control Register. (Offset 0x630 - 0x64Fh) + +// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) +//---------------------------------------------------------------------------- +// 8192C NAV_CTRL bits (Offset 0x650-651, 16 bits) +//---------------------------------------------------------------------------- +#define NAV_UPPER_SHIFT 8 // When NAV update is beyond this, then update is aborted. +#define NAV_UPPER_Mask 0x0FF +#define RTSRST_SHIFT 0 // RTS NAV Reset Time. +#define RTSRST_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C BACAMCMD bits (Offset 0x654-657, 32 bits) +//---------------------------------------------------------------------------- +#define BACAM_POLL BIT(31) // Polling bit BA CAM. +#define BACAM_RST BIT(17) // 1 to reset BA CAM. HW set invalid bit for all entries. +#define BACAM_RW BIT(16) // 1=Write, 0=Read. +#define BACAM_ADDR_SHIFT 0 // BA CAM address. Memory is double-word access. +#define BACAM_ADDR_Mask 0x03F + +//---------------------------------------------------------------------------- +// 8192C LBDLY bits (Offset 0x660, 8 bits) +//---------------------------------------------------------------------------- +#define LBDLY_LMT_SHIFT 0 // Loopback Delay. +#define LBDLY_LMT_Mask 0x01F + +//---------------------------------------------------------------------------- +// 8192C FWDLY bits (Offset 0x661, 8 bits) +//---------------------------------------------------------------------------- +#define FWDLY_LMT_SHIFT 0 // Firmware Delay. +#define FWDLY_LMT_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C RXERR_RPT bits (Offset 0x664-667, 32 bits) +//---------------------------------------------------------------------------- +#define RXERR_RPT_SEL_SHIFT 28 // +#define RXERR_RPT_SEL_Mask 0x0F +#define RXERR_RPT_RST BIT(27) // Write "one" to set the counter to zero. +#define RPT_COUNTER_SHIFT 0 // reported value corresponding to Report type selected. +#define RPT_COUNTER_Mask 0x0FFFFF + +//---------------------------------------------------------------------------- +// 8192C WMAC_TRXPTCL_CTL bits (Offset 0x668-66F, 64 bits) +//---------------------------------------------------------------------------- +#define ACKBA_TYPSEL_SHIFT 28 // Determine response type for RX BA. +#define ACKBA_TYPSEL_Mask 0x0F +#define ACKBA_ACKPCHK_SHIFT 24 // +#define ACKBA_ACKPCHK_Mask 0x0F +#define ACKBAR_ACKPCHK_SHIFT 12 // +#define ACKBAR_ACKPCHK_Mask 0x0F +#define DIS_TXBA_AMPDUFCSERR BIT(4) // Disable to send BA for responding RX AMPDU with FCS error subframe. +#define DIS_TXBA_RXBARINFULL BIT(3) // Disable send BA for responding RX control wrapper BAR dropped by rxpkbuffer full. +#define DIS_TXCFE_INFULL BIT(2) // Disable send CFE for responding RX control wrapper CFE dropped by rxpktbuffer full. +#define DIS_TXCTS_INFULL BIT(1) // Disable send CTS for responding RX control wrapper RTS dropped by rxpktbuffer full. +#define EN_TXCTS_INTXOP BIT(0) // Enable send CTS for responding RX RTS during our TXOP period. + +#define RESP_CHNBUSY_SHIFT 20 // Define channel busy condition in responder to determine RX busy. +#define RESP_CHNBUSY_Mask 0x03 +#define RESP_DCTS_EN BIT(19) // Enable responder send dual CTS for responding Rx RTS. +#define RESP_DCFE_EN BIT(18) // Enable responder send dual CF-END for responding RX CF-END. +#define RESP_SPLCPEN BIT(17) // Enable responder send SPLCP CCK rsp for acknowledging Rx SPLCP CCK. +#define RESP_SGIEN BIT(16) // Enable responder send SGI HT-OFDM rsp for acknowledging Rx SGI HT-OFDM pkt. + +// WMAC, BA, CCX Related Register. (Offset 0x650 - 0x66Fh) + +// Security Control Register. (Offset 0x670 - 0x68Fh) +//---------------------------------------------------------------------------- +// 8192C CAMCMD bits (Offset 0x670-673, 32 bits) +//---------------------------------------------------------------------------- +#define SECCAM_POLL BIT(31) // Security CAM Polling. +#define SECCAM_CLR BIT(30) // Set 1 to clear all valid bits in CAM. +#define MFBCAM_CLR BIT(29) // Write 1 to clear all MFB value in CAM. +#define SECCAM_WE BIT(16) // Security CAM Write Enable. +#define SECCAM_ADDR_SHIFT 0 // Security CAM Address Offset. +#define SECCAM_ADDR_Mask 0x0FF + +//---------------------------------------------------------------------------- +// 8192C CAMDBG bits (Offset 0x67C-67F, 32 bits) +//---------------------------------------------------------------------------- +#define SECCAM_INFO BIT(31) // Select TX/RX CAM Information. +#define SEC_KEYFOUND BIT(30) // Security Key Found in CAM. +#define SEC_CONFIG_SHIFT 24 // Security Configuration. +#define SEC_CONFIG_Mask 0x03F +#define SEC_KEYCONTENT_SHIFT 0 // Security CAM Address Offset. +#define SEC_KEYCONTENT_Mask 0x0FFFFFF + +//---------------------------------------------------------------------------- +// 8192C SECCFG bits (Offset 0x680, 8 bits) +//---------------------------------------------------------------------------- +#define CHK_KEYID BIT(8) // Key search engine need to check if key ID matched +#define RXBCUSEDK BIT(7) // Force RX Broadcast packets Use Default Key +#define TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key +#define NOSKMC BIT(5) // No Key Search for Multicast. +#define SKBYA2 BIT(4) // Search Key by A2. +#define RXDEC BIT(3) // Enable Rx Decryption. +#define TXENC BIT(2) // Enable Tx Encryption. +#define RXUSEDK BIT(1) // Force Rx Use Default Key. +#define TXUSEDK BIT(0) // Force Tx Use Default Key. + +// Security Control Register. (Offset 0x670 - 0x68Fh) + +// Power Save Control Register. (Offset 0x690 - 0x69Fh) +//---------------------------------------------------------------------------- +// 8192C WOW_CTRL bits (Offset 0x690, 8 bits) +//---------------------------------------------------------------------------- +#define FORCE_WAKEUP BIT(7) // Let Wakeup PIN be controllable by FW/Driver. +#define UWF BIT(3) // Unicast Wakeup Frame. +#define MAGIC BIT(2) // Magic Packet. +#define WOWEN BIT(1) // WoW function on or off. +#define PMEN BIT(0) // Power Management Enable. + +//---------------------------------------------------------------------------- +// 8192C PSSTATUS bits (Offset 0x691, 8 bits) +//---------------------------------------------------------------------------- +#define PSSTATUS_SEL_SHIFT 0 // Indicate the present power save mode. +#define PSSTATUS_SEL_Mask 0x0F + +//---------------------------------------------------------------------------- +// 8192C PS_RX_INFO bits (Offset 0x692, 8 bits) +//---------------------------------------------------------------------------- +#define RXCTRLIN0 BIT(4) // set to 1 if NIC received control frame with correct BSSID and DA. +#define RXMGTIN0 BIT(3) // set to 1 if NIC received management frame with correct BSSID and DA. +#define RXDATAIN2 BIT(2) // set to 1 if NIC received data frame with correct BSSID and DA. +#define RXDATAIN1 BIT(1) // set to 1 if NIC received data frame with correct BSSID and DA. +#define RXDATAIN0 BIT(0) // set to 1 if NIC received data frame with correct BSSID and DA. + +//---------------------------------------------------------------------------- +// 8192C LPNAV_CTRL bits (Offset 0x694-697, 32 bits) +//---------------------------------------------------------------------------- +#define LPNAV_EN BIT(31) // Low Power NAV Mode Enable. +#define LPNAV_EARLY_SHIFT 16 // in LPNAV mode, MAC will recall BB & RF into RX idle mode. +#define LPNAV_EARLY_Mask 0x07FFF +#define LPNAV_TH_SHIFT 0 // When NAV received is greater than this, then MAC enters LPNAV mode. +#define LPNAV_TH_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C WKFMCAM_CMD bits (Offset 0x698-69B, 32 bits) +//---------------------------------------------------------------------------- +#define WKFCAM_POLL BIT(31) // Wakeup Mask CAM Polling. +#define WKFCAM_CLR BIT(30) // Set to one to clear all valid bits in CAM. After reset will self clear to 0. +#define WKFCAM_WE BIT(16) // Wakeup Mask CAM Write Enable. +#define WKFCAM_ADDR_SHIFT 0 // Wakeup Mask CAM Address Offset. +#define WKFCAM_ADDR_Mask 0x03F + +// Power Save Control Register. (Offset 0x690 - 0x69Fh) + +// General Purpose Register. (Offset 0x6A0 - 0x6AFh) +//---------------------------------------------------------------------------- +// 8192C RXFLTMAP0 bits (Offset 0x6A0-6A1, 16 bits) +//---------------------------------------------------------------------------- +#define MGTFLTD_EN BIT(13) // +#define MGTFLTC_EN BIT(12) // +#define MGTFLTB_EN BIT(11) // +#define MGTFLTA_EN BIT(10) // +#define MGTFLT9_EN BIT(9) // +#define MGTFLT8_EN BIT(8) // +#define MGTFLT5_EN BIT(5) // +#define MGTFLT4_EN BIT(4) // +#define MGTFLT3_EN BIT(3) // +#define MGTFLT2_EN BIT(2) // +#define MGTFLT1_EN BIT(1) // +#define MGTFLT0_EN BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C RXFLTMAP1 bits (Offset 0x6A2-6A3, 16 bits) +//---------------------------------------------------------------------------- +#define CTRLFLTF_EN BIT(15) // +#define CTRLFLTE_EN BIT(14) // +#define CTRLFLTD_EN BIT(13) // +#define CTRLFLTC_EN BIT(12) // +#define CTRLFLTB_EN BIT(11) // +#define CTRLFLTA_EN BIT(10) // +#define CTRLFLT9_EN BIT(9) // +#define CTRLFLT8_EN BIT(8) // +#define CTRLFLT7_EN BIT(7) // +#define CTRLFLT6_EN BIT(6) // + +//---------------------------------------------------------------------------- +// 8192C RXFLTMAP2 bits (Offset 0x6A4-6A5, 16 bits) +//---------------------------------------------------------------------------- +#define DATAFLTF_EN BIT(15) // +#define DATAFLTE_EN BIT(14) // +#define DATAFLTD_EN BIT(13) // +#define DATAFLTC_EN BIT(12) // +#define DATAFLTB_EN BIT(11) // +#define DATAFLTA_EN BIT(10) // +#define DATAFLT9_EN BIT(9) // +#define DATAFLT8_EN BIT(8) // +#define DATAFLT7_EN BIT(7) // +#define DATAFLT6_EN BIT(6) // +#define DATAFLT5_EN BIT(5) // +#define DATAFLT4_EN BIT(4) // +#define DATAFLT3_EN BIT(3) // +#define DATAFLT2_EN BIT(2) // +#define DATAFLT1_EN BIT(1) // +#define DATAFLT0_EN BIT(0) // + +//---------------------------------------------------------------------------- +// 8192C BCN_PSR_RPT bits (Offset 0x6A8-6AB, 32 bits) +//---------------------------------------------------------------------------- +#define DTIM_CNT_SHIFT 24 // +#define DTIM_CNT_Mask 0x0FF +#define DTIM_PERIOD_SHIFT 16 // +#define DTIM_PERIOD_Mask 0x0FF +#define DTIM BIT(15) // +#define TIM BIT(14) // +#define PS_AID_SHIFT 0 // +#define PS_AID_Mask 0x07FF + +//---------------------------------------------------------------------------- +// 8192C CALB32K_CTRL bits (Offset 0x6AC-6AF, 32 bits) +//---------------------------------------------------------------------------- +#define CALB32K_POLL BIT(31) // +#define CALB32K_DONE BIT(30) // +#define CAL_TIME_SHIFT 20 // Calibration time. +#define CAL_TIME_Mask 0x03FF +#define CAL_REPORT_SHIFT 0 // +#define CAL_REPORT_Mask 0x0FFFFF + +// General Purpose Register. (Offset 0x6A0 - 0x6AFh) + +//---------------------------------------------------------------------------- +// 8192C BT_COEX_TABLE bits (Offset 0x6C0-6CF, 128 bits) +//---------------------------------------------------------------------------- +#define PRI_MASK_RX_RSP BIT(30) // Priority Mask for Rx Response Packet. +#define PRI_MASK_RX_OFDM BIT(29) // Priority Mask for Rx OFDM. +#define PRI_MASK_RX_CCK BIT(28) // Priority Mask for Rx CCK. +#define PRI_MASK_TX_Q_SHIFT 21 // Priority Mask for Tx Queue. +#define PRI_MASK_TX_Q_Mask 0x07F +#define PRI_MASK_TX_NAV_SHIFT 13 // Priority Mask for Tx NAV. +#define PRI_MASK_TX_NAV_Mask 0x0FF +#define PRI_MASK_TX_CCK BIT(12) // Priority Mask for Tx CCK. +#define PRI_MASK_TX_OFDM BIT(11) // Priority Mask for Tx OFDM. +#define PRI_MASK_TX_RTY BIT(10) // Priority Mask for Tx Retry packet. +#define PRI_MASK_TX_NUM_SHIFT 6 // Priority Mask for Tx packet num. +#define PRI_MASK_TX_NUM_Mask 0x0F +#define PRI_MASK_TX_TYPE_SHIFT 2 // Priority Mask for Tx packet type. +#define PRI_MASK_TX_TYPE_Mask 0x0F +#define C_OOB BIT(1) // out of band indication (0:in band,1:out of band). +#define ANT_SEL BIT(0) // single or dual antenna selection (0:single,1:dual). + +#define BREAK_TABLE2_SHIFT 16 // Table used to break WLAN activity. +#define BREAK_TABLE2_Mask 0x0FFFF +#define BREAK_TABLE1_SHIFT 0 // Table used to break BT activity. +#define BREAK_TABLE1_Mask 0x0FFFF + +//---------------------------------------------------------------------------- +// 8192C WMAC_RESP_TXINFO bits (Offset 0x6D8-6DA, 24 bits) +//---------------------------------------------------------------------------- +#define RESP_TXAGC_B_SHIFT 13 // +#define RESP_TXAGC_B_Mask 0x01F +#define RESP_TXAGC_A_SHIFT 8 // +#define RESP_TXAGC_A_Mask 0x01F +#define RESP_ANTSEL_B BIT(7) // +#define RESP_ANTSEL_A BIT(6) // +#define RESP_TXANT_CCK_SHIFT 4 // +#define RESP_TXANT_CCK_Mask 0x03 +#define RESP_TXANT_L_SHIFT 2 // +#define RESP_TXANT_L_Mask 0x03 +#define RESP_TXANT_HT_SHIFT 0 // +#define RESP_TXANT_HT_Mask 0x03 + +//======================================================== +// General definitions +//======================================================== + +#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- + +//2 USB Information (0xFE17) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +#define USB_TEST_EP_MASK 0x30 +#define USB_TEST_EP_SHIFT 4 + +//2 Special Option +#define USB_AGG_EN BIT(3) + + +//2REG_C2HEVT_CLEAR +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + +/* +//---------------------------------------------------------------------------- +// 8192C Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 +*/ + +#endif //WLAN_HAL_INTERNAL_USED + +#endif // #ifndef __INC_HAL8192SEREG_H + diff --git a/package/kernel/rtl8192cd/8192cd_11v.c b/package/kernel/rtl8192cd/8192cd_11v.c index 040c775786f..34d39261e68 100644 --- a/package/kernel/rtl8192cd/8192cd_11v.c +++ b/package/kernel/rtl8192cd/8192cd_11v.c @@ -1,1199 +1,1199 @@ - - -#ifdef __KERNEL__ -#include -#include -#elif defined(__ECOS) -#include -#include -#include -#include -#endif - -#if !defined(__KERNEL__) && !defined(__ECOS) -#include "../sys-support.h" -#endif - -#ifdef __KERNEL__ -#include "../ieee802_mib.h" -#elif defined(__ECOS) -#include -#endif - -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" -#include "./8192cd.h" -#include "./8192cd_cfg.h" -#include "./8192cd_11v.h" - - -extern void qsort (void *base, int nel, int width, int (*comp)(const void *, const void *)); -extern unsigned int issue_assocreq(struct rtl8192cd_priv *priv); - -#define _8192CD_11V_C_ - - - -//++++++++ customized functions -typedef enum _PREFERENCE_ALGO_ { - ALGORITHM_0 = 0, - ALGORITHM_1 = 1 -} PREFERENCE_ALGO; - -inline unsigned char calculation_method0(bool excluded, unsigned char channel_utilization) -{ - if(excluded) - return 0; - return (MAX_PREFERRED_VAL - channel_utilization); -} - -unsigned char getPreferredVal(struct rtl8192cd_priv *priv, unsigned char channel_utilization, unsigned char rcpi, bool excluded) -{ - unsigned char retval = 0; - if(!priv->bssTransPara.FomUser) { - switch(priv->pmib->wnmEntry.algoType) - { - case ALGORITHM_0: - retval = calculation_method0(0, channel_utilization); - break; - default: - panic_printk("Undefined Algorithm Type! \n"); - break; - } - - return retval; - } -} - -#ifdef CONFIG_IEEE80211V_CLI - -static int validate_target_bssid(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int i = 0; - - for(i=priv->join_index+1; isite_survey->count_target; i++) { - if(!memcmp(pstat->wnm.target_bssid, priv->site_survey->bss_target[i].bssid, MACADDRLEN)) { - return 0; - } - } - return -1; -} - -#endif - -//--------- customized functions - -#ifdef CONFIG_RTL_PROC_NEW -int rtl8192cd_proc_transition_list_read(struct seq_file *s, void *data) -#else -int rtl8192cd_proc_transition_list_read(char *buf, char **start, off_t offset, - int length, int *eof, void *data) -#endif -{ - struct net_device *dev = PROC_GET_DEV(); - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - int pos = 0; - int i,j; - struct stat_info *pstat; - - if((OPMODE & WIFI_AP_STATE) == 0) { - panic_printk("\nwarning: invalid command!\n"); - return pos; - } - - PRINT_ONE(" --Target Transition List -- ", "%s", 1); - j = 1; - for (i = 0 ; i < MAX_TRANS_LIST_NUM; i++) - { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) - continue; - - pstat = get_stainfo(priv, priv->transition_list[i].addr); - if(pstat) { - PRINT_ONE(j, " [%d]", 0); - PRINT_ARRAY_ARG("STA:", priv->transition_list[i].addr, "%02x", MACADDRLEN); - PRINT_ONE(" BSS Trans Rejection Count:", "%s", 0); - PRINT_ONE(pstat->bssTransRejectionCount, "%d", 1); - PRINT_ONE(" BSS Trans Trans Expired Time:", "%s", 0); - PRINT_ONE(pstat->bssTransExpiredTime, "%d", 1); - } - j++; - } - - return pos; -} - -#ifdef __ECOS -int rtl8192cd_proc_transition_list_write(char *tmp, void *data) -#else -int rtl8192cd_proc_transition_list_write(struct file *file, const char *buffer, - unsigned long count, void *data) -#endif -{ -#ifdef __ECOS - return 0; -#else - struct net_device *dev = (struct net_device *)data; - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - unsigned char error_code = 0; - char * tokptr; - int command = 0; - int empty_slot; - int i; - char tmp[TRANS_LIST_PROC_LEN]; - char *tmpptr; - struct target_transition_list list; - - if((OPMODE & WIFI_AP_STATE) == 0) { - error_code = 1; - goto end; - } - if (count < 2 || count >= TRANS_LIST_PROC_LEN) { - return -EFAULT; - } - - if (buffer == NULL || copy_from_user(tmp, buffer, count)) - return -EFAULT; - - tmp[count] = 0; - tmpptr = tmp; - tmpptr = strsep((char **)&tmpptr, "\n"); - tokptr = strsep((char **)&tmpptr, " "); - if(!memcmp(tokptr, "add", 3)) - command = 1; - else if (!memcmp(tokptr, "delall", 6)) - command = 3; - else if(!memcmp(tokptr, "del", 3)) - command = 2; - - if(command) - { - if(command == 1 || command == 2) { - tokptr = strsep((char **)&tmpptr," "); - if(tokptr) - get_array_val(list.addr, tokptr, 12); - else { - error_code = 1; - goto end; - } - } - - if(command == 1) /*add*/ - { - for(i = 0, empty_slot = -1; i < MAX_TRANS_LIST_NUM; i++) - { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) { - if(empty_slot == -1) - empty_slot = i; - }else if(0 == memcmp(list.addr, priv->transition_list[i].addr, MACADDRLEN)) { - break; - } - } - - if(i == MAX_TRANS_LIST_NUM && empty_slot != -1) {/*not found, and has empty slot*/ - i = empty_slot; - } - memcpy(&priv->transition_list[i], &list, sizeof(struct target_transition_list)); - priv->transition_list_bitmask[i>>3] |= (1<<(i&7)); - } - else if(command == 3) /*delete all*/ - { - memset(priv->transition_list_bitmask, 0x00, sizeof(priv->transition_list_bitmask)); - } - else if(command == 2) /*delete*/ - { - for (i = 0 ; i < MAX_TRANS_LIST_NUM; i++) { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) - continue; - - if(0 == memcmp(list.addr, priv->transition_list[i].addr, MACADDRLEN)) { - priv->transition_list_bitmask[i>>3] &= ~(1<<(i&7)); - break; - } - } - } - } - else { - error_code = 1; - goto end; - } - - end: - if(error_code == 1) - panic_printk("\nwarning: invalid command!\n"); - else if(error_code == 2) - panic_printk("\nwarning: neighbor report table full!\n"); - return count; -#endif -} - - -unsigned char * construct_target_neighbor_report_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) -{ - int i; - unsigned int len = 16; - *pbuf = _NEIGHBOR_REPORT_IE_; //Information element ID - *(pbuf + 1) = len; - memset((pbuf + 2), 0,len); //Length - memcpy((pbuf + 2), &(priv->bssTransPara.bssid_mac), MACADDRLEN); //target BSSID - -/* printk("Target BSSID Mac: %02x%02x%02x%02x%02x%02x\n", - priv->bssTransPara.bssid_mac[0],priv->bssTransPara.bssid_mac[1],priv->bssTransPara.bssid_mac[2], - priv->bssTransPara.bssid_mac[3],priv->bssTransPara.bssid_mac[4],priv->bssTransPara.bssid_mac[5]); -*/ - //pbuf + 8 - BSSID Information - //pbuf + 12 - Regulatory class - *(pbuf + 13) = priv->bssTransPara.channel; //target channel number - *(pbuf + 14) = 0; //phy type - *(pbuf + 15) = _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_; //subelement id - *(pbuf + 16) = 1; //length - *(pbuf + 17) = 255; //target preference value: default 1 - *frlen = *frlen + (len + 2); - pbuf = pbuf + len + 2; - - return pbuf; -} - - -void send_bss_trans_event(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char i) -{ - if (priv->pmib->wnmEntry.dot11vDiassocDeadline) - pstat->expire_to = priv->pmib->wnmEntry.dot11vDiassocDeadline; - else - pstat->expire_to = MAX_FTREASSOC_DEADLINE; - - pstat->bssTransPktSent++; -#if 1 - if(issue_BSS_Trans_Req(priv, priv->bssTransPara.addr, NULL) == SUCCESS ) -#else - if(issue_BSS_Trans_Req(priv, priv->transition_list[i].addr, NULL) == SUCCESS) -#endif - { - pstat->bssTransExpiredTime = 0; - pstat->bssTransTriggered = TRUE; - priv->startCounting = TRUE; - - DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", - priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2], - priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); - } -} - -void process_BssTransReq(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat; - int i, j = 0; - unsigned long flags; - - SAVE_INT_AND_CLI(flags); -/* - for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) { - j++; - continue; - } -*/ -#if 1 - pstat = get_stainfo(priv, priv->bssTransPara.addr); -#else - pstat = get_stainfo(priv, priv->transition_list[i].addr); -#endif - if(pstat) { -/* - if(priv->pmib->wnmEntry.Is11kDaemonOn) { //collect neighbor report by dot11k daemon - if(pstat->rcvNeighborReport) - send_bss_trans_event(priv, pstat, i); - else - panic_printk("Target clients may not Ready yet!!\n"); - }else -*/ - send_bss_trans_event(priv, pstat, i); - }else - panic_printk("No such station(%d):[%02x][%02x][%02x][%02x][%02x][%02x] \n", i, - priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2], - priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); - -// } - RESTORE_INT(flags); - - if(j == MAX_TRANS_LIST_NUM) - panic_printk("Transition List is empty !!\n"); - -} - -void BssTrans_ExpiredTimer(struct rtl8192cd_priv *priv) -{ - int i; - unsigned long flags; - struct stat_info *pstat; - - SAVE_INT_AND_CLI(flags); - for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) - continue; - -#if 1 - pstat = get_stainfo(priv, priv->bssTransPara.addr); -#else - pstat = get_stainfo(priv, priv->transition_list[i].addr); -#endif - if(pstat) { - if(pstat->bssTransTriggered) // client does not reply bss trans request - pstat->bssTransExpiredTime++; - - if(pstat->bssTransExpiredTime == EVENT_TIMEOUT) - pstat->bssTransStatusCode = _TIMEOUT_STATUS_CODE_; - } - } - RESTORE_INT(flags); -} - -void BssTrans_DiassocTimer(struct rtl8192cd_priv *priv) -{ - int i; - struct stat_info *pstat; - unsigned long flags; - - if(!priv->pmib->wnmEntry.dot11vDiassocDeadline) - priv->startCounting = FALSE; - - if(priv->startCounting == TRUE && priv->pmib->wnmEntry.dot11vDiassocDeadline) { - priv->pmib->wnmEntry.dot11vDiassocDeadline--; - DOT11VDEBUG("Counting down= %d\n", priv->pmib->wnmEntry.dot11vDiassocDeadline); - if(!priv->pmib->wnmEntry.dot11vDiassocDeadline) { - SAVE_INT_AND_CLI(flags); - for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { - if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) - continue; - -#if 1 - pstat = get_stainfo(priv, priv->bssTransPara.addr); - if(!pstat) { - panic_printk("Cant find associated STA (%02x%02x%02x%02x%02x%02x)\n", - priv->bssTransPara.addr[0], priv->bssTransPara.addr[1], priv->bssTransPara.addr[2] - ,priv->bssTransPara.addr[3], priv->bssTransPara.addr[4], priv->bssTransPara.addr[5]); - } else { - // issue diassoc to trigger bss trans (802.11v) - priv->del_sta_info.branch_code = 15; - set_del_sta_info(priv, priv->bssTransPara.addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); - - panic_printk("issue diassoc to trigger bss transition!!\n"); - issue_disassoc(priv, priv->bssTransPara.addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); - del_station(priv, pstat, 0); - } -#else - pstat = get_stainfo(priv, priv->transition_list[i].addr); - if(!pstat) { - panic_printk("Cant find associated STA (%02x%02x%02x%02x%02x%02x)\n", - priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2] - ,priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); - } else { - panic_printk("issue diassoc to trigger bss transition!!\n"); - issue_disassoc(priv, priv->transition_list[i].addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); - del_station(priv, pstat, 0); - } -#endif - priv->startCounting = FALSE; - } - RESTORE_INT(flags); - } - } -} - -void reset_staBssTransStatus(struct stat_info *pstat) -{ - pstat->bssTransRejectionCount = 0; - pstat->bssTransPktSent = 0; - pstat->bssTransExpiredTime = 0; - pstat->rcvNeighborReport = 0; - pstat->bssTransTriggered = 0; - pstat->bssTransStatusCode = _DEFAULT_STATUS_CODE_; -} - -void set_staBssTransCap(struct stat_info *pstat, unsigned char *pframe, int frameLen, unsigned short ie_offset) -{ - int ie_len = 0; - unsigned char *ext_cap = NULL; - unsigned char *p = get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _EXTENDED_CAP_IE_, &ie_len, frameLen); - - ext_cap = (unsigned char *)kmalloc(ie_len, GFP_ATOMIC); - - if(p != NULL) { - memcpy(ext_cap, p+2, ie_len); - if(ext_cap[2] & _WNM_BSS_TRANS_SUPPORT_) { - pstat->bssTransSupport = TRUE; - }else { // when there are 2 extended Capabilities IE (IOT issue with Fujitsu) - p = p + ie_len + 2; - if(*p == _EXTENDED_CAP_IE_){ - ie_len = *(p+1); - memcpy(ext_cap, p+2, ie_len); - if(ext_cap[2] & _WNM_BSS_TRANS_SUPPORT_) - pstat->bssTransSupport = TRUE; - } - } - } - pstat->bssTransStatusCode = _DEFAULT_STATUS_CODE_; - kfree(ext_cap); - DOT11VDEBUG("pstat->dot11v_support %d\n", pstat->bssTransSupport); -} - -void set_BssTransPara(struct rtl8192cd_priv *priv, unsigned char *tmpbuf) -{ - int i, empty_slot; - - priv->bssTransPara.FomUser = TRUE; - - memcpy(priv->bssTransPara.addr, tmpbuf, MACADDRLEN); - memcpy(priv->bssTransPara.bssid_mac, tmpbuf+8, MACADDRLEN); - memcpy(&priv->bssTransPara.channel, tmpbuf+14, 1); - -#if 0 - priv->bssTransPara.chan_until = tmpbuf[MACADDRLEN]; - - for(i = 0, empty_slot = -1; i < MAX_NEIGHBOR_REPORT; i++) { - if((priv->rm_neighbor_bitmask[i>>3] & (1<<(i&7))) == 0) { - if(empty_slot == -1) - empty_slot = i; - } else if(0 == memcmp(priv->bssTransPara.addr, priv->rm_neighbor_report[i].bssid, MACADDRLEN)) { - break; - } - } - if(i == MAX_NEIGHBOR_REPORT && empty_slot != -1) /*not found, and has empty slot*/ - { - i = empty_slot; - } -#else - if(!priv->pmib->wnmEntry.Is11kDaemonOn && !(priv->bssTransPara.channel>0)){ - /*Cannot construct neighbor report if no 11k report to reference and channel number is 0*/ - DOT11VDEBUG("Channel number is 0 and 11k daemon not running!\n"); - return; - } -#endif - - DOT11VTRACE("(%s)line=%d, i = %d\n", __FUNCTION__, __LINE__, i); -#if 1 - process_BssTransReq(priv); -#endif -} - -int issue_BSS_Trans_Req(struct rtl8192cd_priv *priv, unsigned char *da, unsigned char dialog_token) -{ - int ret; - unsigned char *pbuf; - unsigned int frlen = 0; - int neighbor_size = 0, i =0; - int report_found = 0; - unsigned char req_mode = priv->pmib->wnmEntry.dot11vReqMode; - unsigned short diassoc_time = priv->pmib->wnmEntry.dot11vDiassocDeadline; - struct stat_info *pstat = get_stainfo(priv, da); - DECLARE_TXINSN(txinsn); - - DOT11VTRACE("Req mode=%x, diassoc_time = %d, %x\n", req_mode, diassoc_time, cpu_to_le16(diassoc_time)); - DOT11VTRACE("For station %02x%02x%02x%02x%02x%02x to target %02x%02x%02x%02x%02x%02x\n", - da[0], da[1], da[2], da[3],da[4], da[5], - priv->bssTransPara.bssid_mac[0],priv->bssTransPara.bssid_mac[1],priv->bssTransPara.bssid_mac[2], - priv->bssTransPara.bssid_mac[3],priv->bssTransPara.bssid_mac[4],priv->bssTransPara.bssid_mac[5]); - - txinsn.q_num = MANAGE_QUE_NUM; - txinsn.fr_type = _PRE_ALLOCMEM_; - txinsn.tx_rate = find_rate(priv, NULL, 0, 1); -#ifndef TX_LOWESTRATE - txinsn.lowest_tx_rate = txinsn.tx_rate; -#endif - txinsn.fixed_rate = 1; - -#ifdef CONFIG_IEEE80211W - if(pstat) - txinsn.isPMF = pstat->isPMF; - else - txinsn.isPMF = 0; -#endif - pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); - if (pbuf == NULL) - goto issue_wnm_bss_trans_fail; - - txinsn.phdr = get_wlanhdr_from_poll(priv); - if (txinsn.phdr == NULL) - goto issue_wnm_bss_trans_fail; - - memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); - - pbuf[frlen++]= _WNM_CATEGORY_ID_; - pbuf[frlen++] = _BSS_TSMREQ_ACTION_ID_; - - if (!(++pstat->dialog_token)) // dialog token set to a non-zero value - pstat->dialog_token++; - - //dialog_token(1): require mode field(1): dissoc timer(2): validity interval(1) - if(req_mode & (_WNM_PREFERRED_CANDIDATE_LIST_|_WNM_ABRIDGED_)) { - pbuf[frlen++] = pstat->dialog_token; - pbuf[frlen++] = req_mode; - *(unsigned short *)(pbuf + frlen) = cpu_to_le16(diassoc_time); - frlen += 2; - pbuf[frlen++] = 50; //validity interval - pbuf += frlen; -#ifdef DOT11K - if(priv->pmib->wnmEntry.Is11kDaemonOn){ - neighbor_size = sizeof(struct dot11k_neighbor_report); - for(i = 0; i < MAX_NEIGHBOR_REPORT; i++) { - if((priv->rm_neighbor_bitmask[i>>3] & (1<<(i&7))) == 0) - continue; - if(frlen + neighbor_size > MAX_REPORT_FRAME_SIZE) - break; - if(!memcmp(priv->rm_neighbor_report[i].bssid ,priv->bssTransPara.bssid_mac, MACADDRLEN)){ - pbuf = construct_neighbor_report_ie(pbuf, &frlen, &priv->rm_neighbor_report[i]); - report_found = 1; - DOT11VTRACE("Use existing 11k report\n"); - break; - } - } - } -#endif - if(!report_found) - pbuf = construct_target_neighbor_report_ie(priv, pbuf, &frlen); - - - }else { - panic_printk("Type2 : Bss Trans Req with no neighbor report \n"); - pbuf[frlen++] = pstat->dialog_token; - pbuf[frlen++] = 0; - *(unsigned short *)(pbuf + frlen) = cpu_to_le16(0); - frlen += 2; - pbuf[frlen++] = 1; - pbuf += frlen; - } - - txinsn.fr_len = frlen; - SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); -#ifdef CONFIG_IEEE80211W - if (txinsn.isPMF) - *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy -#endif - memcpy((void *)GetAddr1Ptr((txinsn.phdr)), da, MACADDRLEN); - memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); - memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); - -#if defined(WIFI_WMM) - ret = check_dz_mgmt(priv, pstat, &txinsn); - - if (ret < 0) - goto issue_wnm_bss_trans_fail; - else if (ret==1) - return 0; - else -#endif - if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) - return 0; - -issue_wnm_bss_trans_fail: - - if (txinsn.phdr) - release_wlanhdr_to_poll(priv, txinsn.phdr); - if (txinsn.pframe) - release_mgtbuf_to_poll(priv, txinsn.pframe); - return -1; -} - -#ifdef CONFIG_IEEE80211V_CLI -static void reset_nieghbor_list_pref_val(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int i = 0; - struct dot11k_neighbor_report *report; - - if(pstat->wnm.num_neighbor_report == 0) { - panic_printk("(%s)line=%d, Table is empty!! No need to update!! \n", __FUNCTION__, __LINE__); - return; - } - - DOT11VTRACE(" Candidate List valid timeout !!\n"); - for (i = 0 ; i < pstat->wnm.num_neighbor_report; i++) { - report = &pstat->wnm.neighbor_report[i]; - report->subelemnt.preference = priv->pmib->wnmEntry.defaultPrefVal; - } -} - -void BssTrans_ValidatePrefListTimer(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat; - pstat = get_stainfo(priv, priv->pmib->dot11StationConfigEntry.dot11Bssid); - if(pstat) { - if(pstat->wnm.candidate_valid_time > 0) { - DOT11VTRACE("candidate_valid_time = %d\n", pstat->wnm.candidate_valid_time); - pstat->wnm.candidate_valid_time--; - - if(pstat->wnm.candidate_valid_time == 0) - reset_nieghbor_list_pref_val(priv, pstat); - } - } -} - -void BssTrans_TerminationTimer(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat; - pstat = get_stainfo(priv, priv->pmib->dot11StationConfigEntry.dot11Bssid); - if(pstat) { - if(pstat->wnm.dissoc_timer > 0) { - DOT11VTRACE("bss_termination_duration = %d\n", pstat->wnm.dissoc_timer); - pstat->wnm.dissoc_timer--; - - if(pstat->wnm.candidate_valid_time == 0) { - DOT11VDEBUG("bss_termination_duration is time up, diassoc to current AP \n"); - //Assume the termination from the AP is collided, so client send diassoc to connecting AP - issue_disassoc(priv, pstat->hwaddr, _RSON_DISASSOC_DUE_BSS_TRANSITION); - del_station(priv, pstat, 0); - } - } - } -} - -// optional: can use function call this API. At present, it's useless -int issue_BSS_Trans_Query(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char reason) -{ - int ret; - unsigned char *pbuf; - unsigned int frlen = 0; - - DECLARE_TXINSN(txinsn); - txinsn.q_num = MANAGE_QUE_NUM; - txinsn.fr_type = _PRE_ALLOCMEM_; - txinsn.tx_rate = find_rate(priv, NULL, 0, 1); -#ifndef TX_LOWESTRATE - txinsn.lowest_tx_rate = txinsn.tx_rate; -#endif - txinsn.fixed_rate = 1; - -#ifdef CONFIG_IEEE80211W - if(pstat) - txinsn.isPMF = pstat->isPMF; - else - txinsn.isPMF = 0; -#endif - pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); - if (pbuf == NULL) - goto issue_bss_trans_query_fail; - - txinsn.phdr = get_wlanhdr_from_poll(priv); - if (txinsn.phdr == NULL) - goto issue_bss_trans_query_fail; - - memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); - - if (!(++pstat->dialog_token)) // dialog token set to a non-zero value - pstat->dialog_token++; - - pbuf[frlen++] = _WNM_CATEGORY_ID_; - pbuf[frlen++] = _WNM_TSMQUERY_ACTION_ID_; - pbuf[frlen++] = pstat->dialog_token; - pbuf[frlen++] = reason; - - txinsn.fr_len += frlen; - SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); -#ifdef CONFIG_IEEE80211W - if (txinsn.isPMF) - *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy -#endif - memcpy((void *)GetAddr1Ptr((txinsn.phdr)), pstat->hwaddr, MACADDRLEN); - memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); - memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); - -#if defined(WIFI_WMM) - ret = check_dz_mgmt(priv, pstat, &txinsn); - if (ret < 0) - goto issue_bss_trans_query_fail; - else if (ret==1) - return 0; - else -#endif - if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) - return 0; - -issue_bss_trans_query_fail: - if (txinsn.phdr) - release_wlanhdr_to_poll(priv, txinsn.phdr); - if (txinsn.pframe) - release_mgtbuf_to_poll(priv, txinsn.pframe); - - return -1; -} - -int issue_BSS_Trans_Rsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char dialog_token, enum bss_trans_mgmt_status_code status) -{ - int ret; - unsigned char *pbuf; - unsigned int frlen = 0; - - DECLARE_TXINSN(txinsn); - txinsn.q_num = MANAGE_QUE_NUM; - txinsn.fr_type = _PRE_ALLOCMEM_; - txinsn.tx_rate = find_rate(priv, NULL, 0, 1); -#ifndef TX_LOWESTRATE - txinsn.lowest_tx_rate = txinsn.tx_rate; -#endif - txinsn.fixed_rate = 1; - -#ifdef CONFIG_IEEE80211W - if(pstat) - txinsn.isPMF = pstat->isPMF; - else - txinsn.isPMF = 0; -#endif - pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); - if (pbuf == NULL) - goto issue_bss_trans_rsp_fail; - - txinsn.phdr = get_wlanhdr_from_poll(priv); - if (txinsn.phdr == NULL) - goto issue_bss_trans_rsp_fail; - - memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); - - pbuf[frlen++] = _WNM_CATEGORY_ID_; - pbuf[frlen++] = _BSS_TSMRSP_ACTION_ID_; - pbuf[frlen++] = dialog_token; - pbuf[frlen++] = status; - pbuf[frlen++] = 0; // BSS Termination Delay - - if(pstat->wnm.target_bssid) { - memcpy(pbuf+frlen, pstat->wnm.target_bssid, MACADDRLEN); - }else if(status == WNM_BSS_TM_ACCEPT) { - /* - * P802.11-REVmc clarifies that the Target BSSID field is always - * present when status code is zero, so use a fake value here if - * no BSSID is yet known. - */ - memset(pbuf+frlen, 0, MACADDRLEN); - } - - DOT11VDEBUG("Target bssid:[%02x]:[%02x]:[%02x]:[%02x]:[%02x]:[%02x] \n", - pstat->wnm.target_bssid[0], pstat->wnm.target_bssid[1], pstat->wnm.target_bssid[2], - pstat->wnm.target_bssid[3], pstat->wnm.target_bssid[4], pstat->wnm.target_bssid[5]); - - frlen += MACADDRLEN; - txinsn.fr_len += frlen; - SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); -#ifdef CONFIG_IEEE80211W - if (txinsn.isPMF) - *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy -#endif - memcpy((void *)GetAddr1Ptr((txinsn.phdr)), pstat->hwaddr, MACADDRLEN); - memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); - memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); - -#if defined(WIFI_WMM) - ret = check_dz_mgmt(priv, pstat, &txinsn); - if (ret < 0) - goto issue_bss_trans_rsp_fail; - else if (ret==1) - return 0; - else -#endif - if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) - return 0; - -issue_bss_trans_rsp_fail: - if (txinsn.phdr) - release_wlanhdr_to_poll(priv, txinsn.phdr); - if (txinsn.pframe) - release_mgtbuf_to_poll(priv, txinsn.pframe); - - return -1; -} - -static int cand_pref_compar(const void *a, const void *b) -{ - const struct dot11k_neighbor_report *aa = a; - const struct dot11k_neighbor_report *bb = b; - - if (!aa->subelemnt.preference && !bb->subelemnt.preference) { - return 0; - } - if (!aa->subelemnt.preference) { - return 1; - } - if (!bb->subelemnt.preference) { - return -1; - } - - if (bb->subelemnt.preference > aa->subelemnt.preference) - return 1; - if (bb->subelemnt.preference < aa->subelemnt.preference) - return -1; - - return 0; -} - -static void update_neighbor_report(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int i = 0, num_empty_report = 0; - unsigned char null_mac[] = {0,0,0,0,0,0}; - - if(pstat->wnm.num_neighbor_report == 0) { - panic_printk("(%s)line=%d, Table is empty!! No need to update!! \n", __FUNCTION__, __LINE__); - return; - } - - for(i = 0; i < pstat->wnm.num_neighbor_report; i++) { - if(!memcmp(pstat->wnm.neighbor_report[i].bssid, null_mac, MACADDRLEN)) { - num_empty_report++; - } - } - - pstat->wnm.num_neighbor_report -= num_empty_report; - DOT11VTRACE("wnm.num_neighbor_report = %d, num_empty_report = %d\n", pstat->wnm.num_neighbor_report, num_empty_report); -} - -static void start_bss_transition(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - if(!memcmp(pstat->wnm.target_bssid, pstat->hwaddr, MACADDRLEN)) { - DOT11VDEBUG("No need to roam!(The Same Bssid) \n"); - } else { - if(validate_target_bssid(priv, pstat) == 0) { - DOT11VDEBUG("start bss transition!\n"); - - // diassoc the present connecting AP - issue_disassoc(priv, pstat->hwaddr, _RSON_DISASSOC_DUE_BSS_TRANSITION); - del_station(priv, pstat, 0); - - // set the roaming target - memcpy(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid ,pstat->wnm.target_bssid, MACADDRLEN); - }else - DOT11VDEBUG("Validate NG: Client couldn't find target !\n"); - } -} - -static void set_target_bssid(struct stat_info *pstat) -{ - if (pstat->wnm.num_neighbor_report == 0) - return; - - memcpy(pstat->wnm.target_bssid, pstat->wnm.neighbor_report[0].bssid, MACADDRLEN); // preference highest one -} - -// for debug usage -static void dump_cand_list(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - unsigned char i; - struct dot11k_neighbor_report *report; - - for(i = 0; i < pstat->wnm.num_neighbor_report; i++) { - report = &pstat->wnm.neighbor_report[i]; - - panic_printk("(%d)=>[%02x][%02x][%02x][%02x][%02x][%02x], bssinfo=%u, op_class=%u chan=%u phy=%u, prf = %d \n", - i, report->bssid[0], report->bssid[1], report->bssid[2], report->bssid[3], report->bssid[4], report->bssid[5], - report->bssinfo.value, report->op_class, report->channel, report->phytype, report->subelemnt.preference); - } -} - -static void sort_candidate_list(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - DOT11VDEBUG("Candidate List num = %d\n",pstat->wnm.num_neighbor_report); - if (pstat->wnm.num_neighbor_report == 0) - return; - - qsort(pstat->wnm.neighbor_report, pstat->wnm.num_neighbor_report, sizeof(struct dot11k_neighbor_report), cand_pref_compar); - update_neighbor_report(priv, pstat); -} - -static void parse_subelement(struct rtl8192cd_priv *priv, unsigned char id - ,unsigned char *pos, unsigned char elen, struct dot11k_neighbor_report *report) -{ - report->subelemnt.subelement_id = id; - - switch(id) { - case _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_: - if(elen < 1) { - panic_printk("Too short BSS transition candidate \n"); - break; - } - report->subelemnt.len = elen; - report->subelemnt.preference = pos[0]; - break; - default: - panic_printk("Not implemented subelement id! \n"); - break; - } -} - -static void parse_neighbor_report(struct rtl8192cd_priv *priv, unsigned char *pos, unsigned char len, - struct dot11k_neighbor_report *report) -{ - unsigned char left = len; - if(left < NEIGHBOR_REPORT_SIZE) { - panic_printk("Too short neighbor report \n"); - return; - } - - memcpy(report->bssid, pos, MACADDRLEN); - pos += MACADDRLEN; - report->bssinfo.value = le32_to_cpu(*(unsigned int *)&pos[0]); - pos += sizeof(int); - report->op_class = *pos; - pos++; - report->channel = *pos; - pos++; - report->phytype = *pos; - pos++; - - left -= 13; - - DOT11VTRACE("[%02x][%02x][%02x][%02x][%02x][%02x], bssinfo=%u, op_class=%u chan=%u phy=%u \n", - report->bssid[0], report->bssid[1], report->bssid[2], report->bssid[3], report->bssid[4], report->bssid[5], - report->bssinfo.value, report->op_class, report->channel, report->phytype); - while(left >= 2) { - unsigned char id, elen; - id = *pos++; - elen = *pos++; - - left -= 2; - if(elen > left) { - DOT11VDEBUG("Truncated neighbor report subelement \n"); - break; - } - parse_subelement(priv, id, pos, elen, report); - left -= elen; - pos += elen; - } - -} - -void OnBSSTransReq(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len) -{ - int frlen = 0; - enum bss_trans_mgmt_status_code status; - unsigned char valid_int; - unsigned int beacon_int = 100; - unsigned char *pos = (pframe+2); - - if(frame_len <5) { - panic_printk(" Ignore too short BSS Transition Management Request!\n"); - return; - } - - pstat->wnm.dialog_token = pos[0]; - pstat->wnm.req_mode = pos[1]; - pstat->wnm.dissoc_timer = le16_to_cpu(*(unsigned short *) &pos[2]); - pstat->wnm.reply = TRUE; - valid_int = pos[4]; - - DOT11VDEBUG("BSS Trans Req: dialog_token=%u, req_mode=0x%x, dissoc_timer=%u, valid_int=%u, frame_len = %d \n", - pstat->wnm.dialog_token, pstat->wnm.req_mode, pstat->wnm.dissoc_timer, valid_int, frame_len); - - pos += 5; - frlen += 7; - if(pstat->wnm.req_mode & _WNM_BSS_TERMINATION_INCLUDED_) { - DOT11VTRACE("BSS termination included \n"); - if(frlen + 12 > frame_len) { //Bss Trans duration 0 or 12 - panic_printk("Too short BSS TM Request \n"); - return; - } - memcpy(pstat->wnm.bss_termination_duration, pos, BSS_TERMINATION_DURATION_LEN); - pos += BSS_TERMINATION_DURATION_LEN; - frlen += BSS_TERMINATION_DURATION_LEN; - } - - if(pstat->wnm.req_mode & _WNM_ESS_DIASSOC_IMMINENT_) { - unsigned char url[256]; - if (frlen + 1 > frame_len || frlen + 1 + pos[1] > frame_len) { - panic_printk("Invalid BSS Transition Management Request (URL)"); - return; - } - memcpy(url, pos+1, pos[0]); - url[pos[0]] ='\0'; - pos += 1 + pos[0]; - frlen += 1 + pos[0]; - DOT11VTRACE("ESS_DISASSOC_IMMINENT(disassoc_timer: %u, url: %s)", pstat->wnm.dissoc_timer * beacon_int * 128 / 125, url); - } - - if(pstat->wnm.req_mode & _WNM_DIASSOC_IMMINENT_) { - DOT11VTRACE("Disassociation Imminent: dissoc_timer:%u\n", pstat->wnm.dissoc_timer); - if(pstat->wnm.dissoc_timer) { - start_clnt_lookup(priv, 1); //start rescan(needed to check) - } - } - - if(pstat->wnm.req_mode & _WNM_PREFERRED_CANDIDATE_LIST_) { - DOT11VTRACE("PREFERRED_CANDIDATE_LIST: \n"); - unsigned int valid_ms; - - int neighbor_size = sizeof(struct dot11k_neighbor_report); - memset(pstat->wnm.neighbor_report, 0, neighbor_size * MAX_NEIGHBOR_REPORT); - - while((frlen + 2 <= frame_len) && - pstat->wnm.num_neighbor_report < MAX_NEIGHBOR_REPORT) - { - unsigned char tag = *pos++; - unsigned char len = *pos++; - frlen += 2; - - if(frlen + len > frame_len) { - panic_printk("Truncated request size"); - return; - } - - if(tag == _NEIGHBOR_REPORT_IE_) { - struct dot11k_neighbor_report *report; - report = &pstat->wnm.neighbor_report[pstat->wnm.num_neighbor_report]; - parse_neighbor_report(priv, pos, len, report); - } - - pos += len; - frlen += len; - pstat->wnm.num_neighbor_report++; - } - - sort_candidate_list(priv, pstat); -#ifdef DOT11V_DEBUG - dump_cand_list(priv, pstat); -#endif - set_target_bssid(pstat); - valid_ms = valid_int * beacon_int * 128 / 125; - pstat->wnm.candidate_valid_time = (valid_ms)/1000; - DOT11VTRACE("Candidate list valid for (%d) ms/(%d) sec\n", valid_ms, pstat->wnm.candidate_valid_time); - } - - if(pstat->wnm.reply) { - if(pstat->wnm.req_mode & _WNM_PREFERRED_CANDIDATE_LIST_) - status = WNM_BSS_TM_ACCEPT; - else { - DOT11VDEBUG("BSS Transition Request did not include candidates \n"); - status = WNM_BSS_TM_REJECT_UNSPECIFIED; - } - - if(issue_BSS_Trans_Rsp(priv, pstat, pstat->wnm.dialog_token, status) == 0) - start_bss_transition(priv, pstat); - } - return; -} - -#endif - -static void process_status_code( struct stat_info *pstat, unsigned char status_code) -{ - pstat->bssTransStatusCode = status_code; - - if(status_code) - pstat->bssTransRejectionCount++; - - switch(status_code) { - case WNM_BSS_TM_ACCEPT: - panic_printk("Accept: WNM_BSS_TM_ACCEPT![%02x][%02x][%02x][%02x][%02x][%02x] \n", - pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5]); - - pstat->bssTransRejectionCount = 0; - break; - case WNM_BSS_TM_REJECT_UNSPECIFIED: - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_UNSPECIFIED!\n"); - break; - case WNM_BSS_TM_REJECT_INSUFFICIENT_BEACON: - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_INSUFFICIENT_BEACON!\n"); - break; - case WNM_BSS_TM_REJECT_INSUFFICIENT_CAPABITY: - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_INSUFFICIENT_CAPABITY!\n"); - break; - case WNM_BSS_TM_REJECT_UNDESIRED : - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_UNDESIRED !\n"); - break; - case WNM_BSS_TM_REJECT_DELAY_REQUEST : - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_DELAY_REQUEST !\n"); - break; - case WNM_BSS_TM_REJECT_STA_CANDIDATE_LIST_PROVIDED : - panic_printk("Reject: WNM_BSS_TM_REJECT_STA_CANDIDATE_LIST_PROVIDED !\n"); - break; - case WNM_BSS_TM_REJECT_NO_SUITABLE_CANDIDATES: - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_NO_SUITABLE_CANDIDATES !\n"); - break; - case WNM_BSS_TM_REJECT_LEAVING_ESS: - DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_LEAVING_ESS !\n"); - break; - default: - DOT11VDEBUG("unknown type !\n"); - break; - } -} - -void OnBSSTransRsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char*pframe, int frame_len) -{ - int frlen = 0; - - if(frame_len < 3) { - panic_printk("Ignore too short BSS Trans Management RSP!\n"); - return; - } - - unsigned char dialog_token = pframe[2]; - unsigned char status_code = pframe[3]; - unsigned char bss_termination_delay = pframe[4]; //mins - frlen = 5; - - if((frame_len - frlen) > MAX_LIST_LEN) - return; - - DOT11VTRACE("dialog_token = %d, bss_termination_delay = %d\n", dialog_token, bss_termination_delay); - process_status_code(pstat, status_code); - pstat->bssTransExpiredTime = 0; - pstat->bssTransTriggered = 0; - - if((frame_len - frlen) > 0) { - if(status_code == WNM_BSS_TM_ACCEPT) { - debug_out("Target BSSID: ", &pframe[frlen], MACADDRLEN); - frlen += MACADDRLEN; - debug_out("Bss Trans Candidate List: ", &pframe[frlen], frame_len - frlen); - }else if(status_code == WNM_BSS_TM_REJECT_DELAY_REQUEST){ - priv->pmib->wnmEntry.dot11vDiassocDeadline = bss_termination_delay*60; - }else - debug_out("Bss Trans Candidate List: ", &pframe[frlen], frame_len - frlen); - }else { - DEBUG_ERR("WNM: no info in bss trans response!\n"); - } - - return; -} - -void OnBSSTransQuery(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char*pframe, int frame_len) -{ - int list_len; - - if(frame_len < 2) { - DEBUG_ERR("Ignore too short BSS Transition Management Query!\n"); - return; - } - - unsigned char dialog_token = pframe[2]; - unsigned char reason = pframe[3]; - - DOT11VTRACE("dialog_token = %d, reason = %d\n", dialog_token, reason); - - if(reason == _WNM_PREFERED_BSS_TRANS_LIST_INCLUDED_) { - list_len = frame_len - 4; - - if(list_len > MAX_LIST_LEN) - return; - debug_out("Bss List Len: ", &pframe[list_len], frame_len - list_len); - } else - panic_printk("WNM_PREFERED BSS TRANS LIST NOT INCLUDED!\n"); - - issue_BSS_Trans_Req(priv, pstat->hwaddr, dialog_token); -} - -void WNM_ActionHandler(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len) -{ - unsigned char action_field = pframe[1]; - - switch (action_field) { - case _WNM_TSMQUERY_ACTION_ID_: - OnBSSTransQuery(priv, pstat, pframe, frame_len); - break; - case _BSS_TSMRSP_ACTION_ID_: - OnBSSTransRsp(priv, pstat, pframe, frame_len); - break; - #ifdef CONFIG_IEEE80211V_CLI - case _BSS_TSMREQ_ACTION_ID_: - OnBSSTransReq(priv, pstat, pframe, frame_len); - break; - #endif - default: - DEBUG_INFO("Other WNM action: %d:\n", action_field); - break; - } -} - + + +#ifdef __KERNEL__ +#include +#include +#elif defined(__ECOS) +#include +#include +#include +#include +#endif + +#if !defined(__KERNEL__) && !defined(__ECOS) +#include "../sys-support.h" +#endif + +#ifdef __KERNEL__ +#include "../ieee802_mib.h" +#elif defined(__ECOS) +#include +#endif + +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" +#include "./8192cd.h" +#include "./8192cd_cfg.h" +#include "./8192cd_11v.h" + + +extern void qsort (void *base, int nel, int width, int (*comp)(const void *, const void *)); +extern unsigned int issue_assocreq(struct rtl8192cd_priv *priv); + +#define _8192CD_11V_C_ + + + +//++++++++ customized functions +typedef enum _PREFERENCE_ALGO_ { + ALGORITHM_0 = 0, + ALGORITHM_1 = 1 +} PREFERENCE_ALGO; + +inline unsigned char calculation_method0(bool excluded, unsigned char channel_utilization) +{ + if(excluded) + return 0; + return (MAX_PREFERRED_VAL - channel_utilization); +} + +unsigned char getPreferredVal(struct rtl8192cd_priv *priv, unsigned char channel_utilization, unsigned char rcpi, bool excluded) +{ + unsigned char retval = 0; + if(!priv->bssTransPara.FomUser) { + switch(priv->pmib->wnmEntry.algoType) + { + case ALGORITHM_0: + retval = calculation_method0(0, channel_utilization); + break; + default: + panic_printk("Undefined Algorithm Type! \n"); + break; + } + + return retval; + } +} + +#ifdef CONFIG_IEEE80211V_CLI + +static int validate_target_bssid(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int i = 0; + + for(i=priv->join_index+1; isite_survey->count_target; i++) { + if(!memcmp(pstat->wnm.target_bssid, priv->site_survey->bss_target[i].bssid, MACADDRLEN)) { + return 0; + } + } + return -1; +} + +#endif + +//--------- customized functions + +#ifdef CONFIG_RTL_PROC_NEW +int rtl8192cd_proc_transition_list_read(struct seq_file *s, void *data) +#else +int rtl8192cd_proc_transition_list_read(char *buf, char **start, off_t offset, + int length, int *eof, void *data) +#endif +{ + struct net_device *dev = PROC_GET_DEV(); + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + int pos = 0; + int i,j; + struct stat_info *pstat; + + if((OPMODE & WIFI_AP_STATE) == 0) { + panic_printk("\nwarning: invalid command!\n"); + return pos; + } + + PRINT_ONE(" --Target Transition List -- ", "%s", 1); + j = 1; + for (i = 0 ; i < MAX_TRANS_LIST_NUM; i++) + { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) + continue; + + pstat = get_stainfo(priv, priv->transition_list[i].addr); + if(pstat) { + PRINT_ONE(j, " [%d]", 0); + PRINT_ARRAY_ARG("STA:", priv->transition_list[i].addr, "%02x", MACADDRLEN); + PRINT_ONE(" BSS Trans Rejection Count:", "%s", 0); + PRINT_ONE(pstat->bssTransRejectionCount, "%d", 1); + PRINT_ONE(" BSS Trans Trans Expired Time:", "%s", 0); + PRINT_ONE(pstat->bssTransExpiredTime, "%d", 1); + } + j++; + } + + return pos; +} + +#ifdef __ECOS +int rtl8192cd_proc_transition_list_write(char *tmp, void *data) +#else +int rtl8192cd_proc_transition_list_write(struct file *file, const char *buffer, + unsigned long count, void *data) +#endif +{ +#ifdef __ECOS + return 0; +#else + struct net_device *dev = (struct net_device *)data; + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + unsigned char error_code = 0; + char * tokptr; + int command = 0; + int empty_slot; + int i; + char tmp[TRANS_LIST_PROC_LEN]; + char *tmpptr; + struct target_transition_list list; + + if((OPMODE & WIFI_AP_STATE) == 0) { + error_code = 1; + goto end; + } + if (count < 2 || count >= TRANS_LIST_PROC_LEN) { + return -EFAULT; + } + + if (buffer == NULL || copy_from_user(tmp, buffer, count)) + return -EFAULT; + + tmp[count] = 0; + tmpptr = tmp; + tmpptr = strsep((char **)&tmpptr, "\n"); + tokptr = strsep((char **)&tmpptr, " "); + if(!memcmp(tokptr, "add", 3)) + command = 1; + else if (!memcmp(tokptr, "delall", 6)) + command = 3; + else if(!memcmp(tokptr, "del", 3)) + command = 2; + + if(command) + { + if(command == 1 || command == 2) { + tokptr = strsep((char **)&tmpptr," "); + if(tokptr) + get_array_val(list.addr, tokptr, 12); + else { + error_code = 1; + goto end; + } + } + + if(command == 1) /*add*/ + { + for(i = 0, empty_slot = -1; i < MAX_TRANS_LIST_NUM; i++) + { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) { + if(empty_slot == -1) + empty_slot = i; + }else if(0 == memcmp(list.addr, priv->transition_list[i].addr, MACADDRLEN)) { + break; + } + } + + if(i == MAX_TRANS_LIST_NUM && empty_slot != -1) {/*not found, and has empty slot*/ + i = empty_slot; + } + memcpy(&priv->transition_list[i], &list, sizeof(struct target_transition_list)); + priv->transition_list_bitmask[i>>3] |= (1<<(i&7)); + } + else if(command == 3) /*delete all*/ + { + memset(priv->transition_list_bitmask, 0x00, sizeof(priv->transition_list_bitmask)); + } + else if(command == 2) /*delete*/ + { + for (i = 0 ; i < MAX_TRANS_LIST_NUM; i++) { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) + continue; + + if(0 == memcmp(list.addr, priv->transition_list[i].addr, MACADDRLEN)) { + priv->transition_list_bitmask[i>>3] &= ~(1<<(i&7)); + break; + } + } + } + } + else { + error_code = 1; + goto end; + } + + end: + if(error_code == 1) + panic_printk("\nwarning: invalid command!\n"); + else if(error_code == 2) + panic_printk("\nwarning: neighbor report table full!\n"); + return count; +#endif +} + + +unsigned char * construct_target_neighbor_report_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) +{ + int i; + unsigned int len = 16; + *pbuf = _NEIGHBOR_REPORT_IE_; //Information element ID + *(pbuf + 1) = len; + memset((pbuf + 2), 0,len); //Length + memcpy((pbuf + 2), &(priv->bssTransPara.bssid_mac), MACADDRLEN); //target BSSID + +/* printk("Target BSSID Mac: %02x%02x%02x%02x%02x%02x\n", + priv->bssTransPara.bssid_mac[0],priv->bssTransPara.bssid_mac[1],priv->bssTransPara.bssid_mac[2], + priv->bssTransPara.bssid_mac[3],priv->bssTransPara.bssid_mac[4],priv->bssTransPara.bssid_mac[5]); +*/ + //pbuf + 8 - BSSID Information + //pbuf + 12 - Regulatory class + *(pbuf + 13) = priv->bssTransPara.channel; //target channel number + *(pbuf + 14) = 0; //phy type + *(pbuf + 15) = _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_; //subelement id + *(pbuf + 16) = 1; //length + *(pbuf + 17) = 255; //target preference value: default 1 + *frlen = *frlen + (len + 2); + pbuf = pbuf + len + 2; + + return pbuf; +} + + +void send_bss_trans_event(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char i) +{ + if (priv->pmib->wnmEntry.dot11vDiassocDeadline) + pstat->expire_to = priv->pmib->wnmEntry.dot11vDiassocDeadline; + else + pstat->expire_to = MAX_FTREASSOC_DEADLINE; + + pstat->bssTransPktSent++; +#if 1 + if(issue_BSS_Trans_Req(priv, priv->bssTransPara.addr, NULL) == SUCCESS ) +#else + if(issue_BSS_Trans_Req(priv, priv->transition_list[i].addr, NULL) == SUCCESS) +#endif + { + pstat->bssTransExpiredTime = 0; + pstat->bssTransTriggered = TRUE; + priv->startCounting = TRUE; + + DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", + priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2], + priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); + } +} + +void process_BssTransReq(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat; + int i, j = 0; + unsigned long flags; + + SAVE_INT_AND_CLI(flags); +/* + for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) { + j++; + continue; + } +*/ +#if 1 + pstat = get_stainfo(priv, priv->bssTransPara.addr); +#else + pstat = get_stainfo(priv, priv->transition_list[i].addr); +#endif + if(pstat) { +/* + if(priv->pmib->wnmEntry.Is11kDaemonOn) { //collect neighbor report by dot11k daemon + if(pstat->rcvNeighborReport) + send_bss_trans_event(priv, pstat, i); + else + panic_printk("Target clients may not Ready yet!!\n"); + }else +*/ + send_bss_trans_event(priv, pstat, i); + }else + panic_printk("No such station(%d):[%02x][%02x][%02x][%02x][%02x][%02x] \n", i, + priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2], + priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); + +// } + RESTORE_INT(flags); + + if(j == MAX_TRANS_LIST_NUM) + panic_printk("Transition List is empty !!\n"); + +} + +void BssTrans_ExpiredTimer(struct rtl8192cd_priv *priv) +{ + int i; + unsigned long flags; + struct stat_info *pstat; + + SAVE_INT_AND_CLI(flags); + for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) + continue; + +#if 1 + pstat = get_stainfo(priv, priv->bssTransPara.addr); +#else + pstat = get_stainfo(priv, priv->transition_list[i].addr); +#endif + if(pstat) { + if(pstat->bssTransTriggered) // client does not reply bss trans request + pstat->bssTransExpiredTime++; + + if(pstat->bssTransExpiredTime == EVENT_TIMEOUT) + pstat->bssTransStatusCode = _TIMEOUT_STATUS_CODE_; + } + } + RESTORE_INT(flags); +} + +void BssTrans_DiassocTimer(struct rtl8192cd_priv *priv) +{ + int i; + struct stat_info *pstat; + unsigned long flags; + + if(!priv->pmib->wnmEntry.dot11vDiassocDeadline) + priv->startCounting = FALSE; + + if(priv->startCounting == TRUE && priv->pmib->wnmEntry.dot11vDiassocDeadline) { + priv->pmib->wnmEntry.dot11vDiassocDeadline--; + DOT11VDEBUG("Counting down= %d\n", priv->pmib->wnmEntry.dot11vDiassocDeadline); + if(!priv->pmib->wnmEntry.dot11vDiassocDeadline) { + SAVE_INT_AND_CLI(flags); + for (i = 0; i < MAX_TRANS_LIST_NUM; i++) { + if((priv->transition_list_bitmask[i>>3] & (1<<(i&7))) == 0) + continue; + +#if 1 + pstat = get_stainfo(priv, priv->bssTransPara.addr); + if(!pstat) { + panic_printk("Cant find associated STA (%02x%02x%02x%02x%02x%02x)\n", + priv->bssTransPara.addr[0], priv->bssTransPara.addr[1], priv->bssTransPara.addr[2] + ,priv->bssTransPara.addr[3], priv->bssTransPara.addr[4], priv->bssTransPara.addr[5]); + } else { + // issue diassoc to trigger bss trans (802.11v) + priv->del_sta_info.branch_code = 15; + set_del_sta_info(priv, priv->bssTransPara.addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); + + panic_printk("issue diassoc to trigger bss transition!!\n"); + issue_disassoc(priv, priv->bssTransPara.addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); + del_station(priv, pstat, 0); + } +#else + pstat = get_stainfo(priv, priv->transition_list[i].addr); + if(!pstat) { + panic_printk("Cant find associated STA (%02x%02x%02x%02x%02x%02x)\n", + priv->transition_list[i].addr[0], priv->transition_list[i].addr[1], priv->transition_list[i].addr[2] + ,priv->transition_list[i].addr[3], priv->transition_list[i].addr[4], priv->transition_list[i].addr[5]); + } else { + panic_printk("issue diassoc to trigger bss transition!!\n"); + issue_disassoc(priv, priv->transition_list[i].addr, _RSON_DISASSOC_DUE_BSS_TRANSITION); + del_station(priv, pstat, 0); + } +#endif + priv->startCounting = FALSE; + } + RESTORE_INT(flags); + } + } +} + +void reset_staBssTransStatus(struct stat_info *pstat) +{ + pstat->bssTransRejectionCount = 0; + pstat->bssTransPktSent = 0; + pstat->bssTransExpiredTime = 0; + pstat->rcvNeighborReport = 0; + pstat->bssTransTriggered = 0; + pstat->bssTransStatusCode = _DEFAULT_STATUS_CODE_; +} + +void set_staBssTransCap(struct stat_info *pstat, unsigned char *pframe, int frameLen, unsigned short ie_offset) +{ + int ie_len = 0; + unsigned char *ext_cap = NULL; + unsigned char *p = get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _EXTENDED_CAP_IE_, &ie_len, frameLen); + + ext_cap = (unsigned char *)kmalloc(ie_len, GFP_ATOMIC); + + if(p != NULL) { + memcpy(ext_cap, p+2, ie_len); + if(ext_cap[2] & _WNM_BSS_TRANS_SUPPORT_) { + pstat->bssTransSupport = TRUE; + }else { // when there are 2 extended Capabilities IE (IOT issue with Fujitsu) + p = p + ie_len + 2; + if(*p == _EXTENDED_CAP_IE_){ + ie_len = *(p+1); + memcpy(ext_cap, p+2, ie_len); + if(ext_cap[2] & _WNM_BSS_TRANS_SUPPORT_) + pstat->bssTransSupport = TRUE; + } + } + } + pstat->bssTransStatusCode = _DEFAULT_STATUS_CODE_; + kfree(ext_cap); + DOT11VDEBUG("pstat->dot11v_support %d\n", pstat->bssTransSupport); +} + +void set_BssTransPara(struct rtl8192cd_priv *priv, unsigned char *tmpbuf) +{ + int i, empty_slot; + + priv->bssTransPara.FomUser = TRUE; + + memcpy(priv->bssTransPara.addr, tmpbuf, MACADDRLEN); + memcpy(priv->bssTransPara.bssid_mac, tmpbuf+8, MACADDRLEN); + memcpy(&priv->bssTransPara.channel, tmpbuf+14, 1); + +#if 0 + priv->bssTransPara.chan_until = tmpbuf[MACADDRLEN]; + + for(i = 0, empty_slot = -1; i < MAX_NEIGHBOR_REPORT; i++) { + if((priv->rm_neighbor_bitmask[i>>3] & (1<<(i&7))) == 0) { + if(empty_slot == -1) + empty_slot = i; + } else if(0 == memcmp(priv->bssTransPara.addr, priv->rm_neighbor_report[i].bssid, MACADDRLEN)) { + break; + } + } + if(i == MAX_NEIGHBOR_REPORT && empty_slot != -1) /*not found, and has empty slot*/ + { + i = empty_slot; + } +#else + if(!priv->pmib->wnmEntry.Is11kDaemonOn && !(priv->bssTransPara.channel>0)){ + /*Cannot construct neighbor report if no 11k report to reference and channel number is 0*/ + DOT11VDEBUG("Channel number is 0 and 11k daemon not running!\n"); + return; + } +#endif + + DOT11VTRACE("(%s)line=%d, i = %d\n", __FUNCTION__, __LINE__, i); +#if 1 + process_BssTransReq(priv); +#endif +} + +int issue_BSS_Trans_Req(struct rtl8192cd_priv *priv, unsigned char *da, unsigned char dialog_token) +{ + int ret; + unsigned char *pbuf; + unsigned int frlen = 0; + int neighbor_size = 0, i =0; + int report_found = 0; + unsigned char req_mode = priv->pmib->wnmEntry.dot11vReqMode; + unsigned short diassoc_time = priv->pmib->wnmEntry.dot11vDiassocDeadline; + struct stat_info *pstat = get_stainfo(priv, da); + DECLARE_TXINSN(txinsn); + + DOT11VTRACE("Req mode=%x, diassoc_time = %d, %x\n", req_mode, diassoc_time, cpu_to_le16(diassoc_time)); + DOT11VTRACE("For station %02x%02x%02x%02x%02x%02x to target %02x%02x%02x%02x%02x%02x\n", + da[0], da[1], da[2], da[3],da[4], da[5], + priv->bssTransPara.bssid_mac[0],priv->bssTransPara.bssid_mac[1],priv->bssTransPara.bssid_mac[2], + priv->bssTransPara.bssid_mac[3],priv->bssTransPara.bssid_mac[4],priv->bssTransPara.bssid_mac[5]); + + txinsn.q_num = MANAGE_QUE_NUM; + txinsn.fr_type = _PRE_ALLOCMEM_; + txinsn.tx_rate = find_rate(priv, NULL, 0, 1); +#ifndef TX_LOWESTRATE + txinsn.lowest_tx_rate = txinsn.tx_rate; +#endif + txinsn.fixed_rate = 1; + +#ifdef CONFIG_IEEE80211W + if(pstat) + txinsn.isPMF = pstat->isPMF; + else + txinsn.isPMF = 0; +#endif + pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); + if (pbuf == NULL) + goto issue_wnm_bss_trans_fail; + + txinsn.phdr = get_wlanhdr_from_poll(priv); + if (txinsn.phdr == NULL) + goto issue_wnm_bss_trans_fail; + + memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); + + pbuf[frlen++]= _WNM_CATEGORY_ID_; + pbuf[frlen++] = _BSS_TSMREQ_ACTION_ID_; + + if (!(++pstat->dialog_token)) // dialog token set to a non-zero value + pstat->dialog_token++; + + //dialog_token(1): require mode field(1): dissoc timer(2): validity interval(1) + if(req_mode & (_WNM_PREFERRED_CANDIDATE_LIST_|_WNM_ABRIDGED_)) { + pbuf[frlen++] = pstat->dialog_token; + pbuf[frlen++] = req_mode; + *(unsigned short *)(pbuf + frlen) = cpu_to_le16(diassoc_time); + frlen += 2; + pbuf[frlen++] = 50; //validity interval + pbuf += frlen; +#ifdef DOT11K + if(priv->pmib->wnmEntry.Is11kDaemonOn){ + neighbor_size = sizeof(struct dot11k_neighbor_report); + for(i = 0; i < MAX_NEIGHBOR_REPORT; i++) { + if((priv->rm_neighbor_bitmask[i>>3] & (1<<(i&7))) == 0) + continue; + if(frlen + neighbor_size > MAX_REPORT_FRAME_SIZE) + break; + if(!memcmp(priv->rm_neighbor_report[i].bssid ,priv->bssTransPara.bssid_mac, MACADDRLEN)){ + pbuf = construct_neighbor_report_ie(pbuf, &frlen, &priv->rm_neighbor_report[i]); + report_found = 1; + DOT11VTRACE("Use existing 11k report\n"); + break; + } + } + } +#endif + if(!report_found) + pbuf = construct_target_neighbor_report_ie(priv, pbuf, &frlen); + + + }else { + panic_printk("Type2 : Bss Trans Req with no neighbor report \n"); + pbuf[frlen++] = pstat->dialog_token; + pbuf[frlen++] = 0; + *(unsigned short *)(pbuf + frlen) = cpu_to_le16(0); + frlen += 2; + pbuf[frlen++] = 1; + pbuf += frlen; + } + + txinsn.fr_len = frlen; + SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); +#ifdef CONFIG_IEEE80211W + if (txinsn.isPMF) + *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy +#endif + memcpy((void *)GetAddr1Ptr((txinsn.phdr)), da, MACADDRLEN); + memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); + memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); + +#if defined(WIFI_WMM) + ret = check_dz_mgmt(priv, pstat, &txinsn); + + if (ret < 0) + goto issue_wnm_bss_trans_fail; + else if (ret==1) + return 0; + else +#endif + if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) + return 0; + +issue_wnm_bss_trans_fail: + + if (txinsn.phdr) + release_wlanhdr_to_poll(priv, txinsn.phdr); + if (txinsn.pframe) + release_mgtbuf_to_poll(priv, txinsn.pframe); + return -1; +} + +#ifdef CONFIG_IEEE80211V_CLI +static void reset_nieghbor_list_pref_val(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int i = 0; + struct dot11k_neighbor_report *report; + + if(pstat->wnm.num_neighbor_report == 0) { + panic_printk("(%s)line=%d, Table is empty!! No need to update!! \n", __FUNCTION__, __LINE__); + return; + } + + DOT11VTRACE(" Candidate List valid timeout !!\n"); + for (i = 0 ; i < pstat->wnm.num_neighbor_report; i++) { + report = &pstat->wnm.neighbor_report[i]; + report->subelemnt.preference = priv->pmib->wnmEntry.defaultPrefVal; + } +} + +void BssTrans_ValidatePrefListTimer(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat; + pstat = get_stainfo(priv, priv->pmib->dot11StationConfigEntry.dot11Bssid); + if(pstat) { + if(pstat->wnm.candidate_valid_time > 0) { + DOT11VTRACE("candidate_valid_time = %d\n", pstat->wnm.candidate_valid_time); + pstat->wnm.candidate_valid_time--; + + if(pstat->wnm.candidate_valid_time == 0) + reset_nieghbor_list_pref_val(priv, pstat); + } + } +} + +void BssTrans_TerminationTimer(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat; + pstat = get_stainfo(priv, priv->pmib->dot11StationConfigEntry.dot11Bssid); + if(pstat) { + if(pstat->wnm.dissoc_timer > 0) { + DOT11VTRACE("bss_termination_duration = %d\n", pstat->wnm.dissoc_timer); + pstat->wnm.dissoc_timer--; + + if(pstat->wnm.candidate_valid_time == 0) { + DOT11VDEBUG("bss_termination_duration is time up, diassoc to current AP \n"); + //Assume the termination from the AP is collided, so client send diassoc to connecting AP + issue_disassoc(priv, pstat->hwaddr, _RSON_DISASSOC_DUE_BSS_TRANSITION); + del_station(priv, pstat, 0); + } + } + } +} + +// optional: can use function call this API. At present, it's useless +int issue_BSS_Trans_Query(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char reason) +{ + int ret; + unsigned char *pbuf; + unsigned int frlen = 0; + + DECLARE_TXINSN(txinsn); + txinsn.q_num = MANAGE_QUE_NUM; + txinsn.fr_type = _PRE_ALLOCMEM_; + txinsn.tx_rate = find_rate(priv, NULL, 0, 1); +#ifndef TX_LOWESTRATE + txinsn.lowest_tx_rate = txinsn.tx_rate; +#endif + txinsn.fixed_rate = 1; + +#ifdef CONFIG_IEEE80211W + if(pstat) + txinsn.isPMF = pstat->isPMF; + else + txinsn.isPMF = 0; +#endif + pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); + if (pbuf == NULL) + goto issue_bss_trans_query_fail; + + txinsn.phdr = get_wlanhdr_from_poll(priv); + if (txinsn.phdr == NULL) + goto issue_bss_trans_query_fail; + + memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); + + if (!(++pstat->dialog_token)) // dialog token set to a non-zero value + pstat->dialog_token++; + + pbuf[frlen++] = _WNM_CATEGORY_ID_; + pbuf[frlen++] = _WNM_TSMQUERY_ACTION_ID_; + pbuf[frlen++] = pstat->dialog_token; + pbuf[frlen++] = reason; + + txinsn.fr_len += frlen; + SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); +#ifdef CONFIG_IEEE80211W + if (txinsn.isPMF) + *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy +#endif + memcpy((void *)GetAddr1Ptr((txinsn.phdr)), pstat->hwaddr, MACADDRLEN); + memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); + memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); + +#if defined(WIFI_WMM) + ret = check_dz_mgmt(priv, pstat, &txinsn); + if (ret < 0) + goto issue_bss_trans_query_fail; + else if (ret==1) + return 0; + else +#endif + if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) + return 0; + +issue_bss_trans_query_fail: + if (txinsn.phdr) + release_wlanhdr_to_poll(priv, txinsn.phdr); + if (txinsn.pframe) + release_mgtbuf_to_poll(priv, txinsn.pframe); + + return -1; +} + +int issue_BSS_Trans_Rsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char dialog_token, enum bss_trans_mgmt_status_code status) +{ + int ret; + unsigned char *pbuf; + unsigned int frlen = 0; + + DECLARE_TXINSN(txinsn); + txinsn.q_num = MANAGE_QUE_NUM; + txinsn.fr_type = _PRE_ALLOCMEM_; + txinsn.tx_rate = find_rate(priv, NULL, 0, 1); +#ifndef TX_LOWESTRATE + txinsn.lowest_tx_rate = txinsn.tx_rate; +#endif + txinsn.fixed_rate = 1; + +#ifdef CONFIG_IEEE80211W + if(pstat) + txinsn.isPMF = pstat->isPMF; + else + txinsn.isPMF = 0; +#endif + pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv); + if (pbuf == NULL) + goto issue_bss_trans_rsp_fail; + + txinsn.phdr = get_wlanhdr_from_poll(priv); + if (txinsn.phdr == NULL) + goto issue_bss_trans_rsp_fail; + + memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr)); + + pbuf[frlen++] = _WNM_CATEGORY_ID_; + pbuf[frlen++] = _BSS_TSMRSP_ACTION_ID_; + pbuf[frlen++] = dialog_token; + pbuf[frlen++] = status; + pbuf[frlen++] = 0; // BSS Termination Delay + + if(pstat->wnm.target_bssid) { + memcpy(pbuf+frlen, pstat->wnm.target_bssid, MACADDRLEN); + }else if(status == WNM_BSS_TM_ACCEPT) { + /* + * P802.11-REVmc clarifies that the Target BSSID field is always + * present when status code is zero, so use a fake value here if + * no BSSID is yet known. + */ + memset(pbuf+frlen, 0, MACADDRLEN); + } + + DOT11VDEBUG("Target bssid:[%02x]:[%02x]:[%02x]:[%02x]:[%02x]:[%02x] \n", + pstat->wnm.target_bssid[0], pstat->wnm.target_bssid[1], pstat->wnm.target_bssid[2], + pstat->wnm.target_bssid[3], pstat->wnm.target_bssid[4], pstat->wnm.target_bssid[5]); + + frlen += MACADDRLEN; + txinsn.fr_len += frlen; + SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION); +#ifdef CONFIG_IEEE80211W + if (txinsn.isPMF) + *(unsigned char*)(txinsn.phdr+1) |= BIT(6); // enable privacy +#endif + memcpy((void *)GetAddr1Ptr((txinsn.phdr)), pstat->hwaddr, MACADDRLEN); + memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN); + memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN); + +#if defined(WIFI_WMM) + ret = check_dz_mgmt(priv, pstat, &txinsn); + if (ret < 0) + goto issue_bss_trans_rsp_fail; + else if (ret==1) + return 0; + else +#endif + if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS) + return 0; + +issue_bss_trans_rsp_fail: + if (txinsn.phdr) + release_wlanhdr_to_poll(priv, txinsn.phdr); + if (txinsn.pframe) + release_mgtbuf_to_poll(priv, txinsn.pframe); + + return -1; +} + +static int cand_pref_compar(const void *a, const void *b) +{ + const struct dot11k_neighbor_report *aa = a; + const struct dot11k_neighbor_report *bb = b; + + if (!aa->subelemnt.preference && !bb->subelemnt.preference) { + return 0; + } + if (!aa->subelemnt.preference) { + return 1; + } + if (!bb->subelemnt.preference) { + return -1; + } + + if (bb->subelemnt.preference > aa->subelemnt.preference) + return 1; + if (bb->subelemnt.preference < aa->subelemnt.preference) + return -1; + + return 0; +} + +static void update_neighbor_report(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int i = 0, num_empty_report = 0; + unsigned char null_mac[] = {0,0,0,0,0,0}; + + if(pstat->wnm.num_neighbor_report == 0) { + panic_printk("(%s)line=%d, Table is empty!! No need to update!! \n", __FUNCTION__, __LINE__); + return; + } + + for(i = 0; i < pstat->wnm.num_neighbor_report; i++) { + if(!memcmp(pstat->wnm.neighbor_report[i].bssid, null_mac, MACADDRLEN)) { + num_empty_report++; + } + } + + pstat->wnm.num_neighbor_report -= num_empty_report; + DOT11VTRACE("wnm.num_neighbor_report = %d, num_empty_report = %d\n", pstat->wnm.num_neighbor_report, num_empty_report); +} + +static void start_bss_transition(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + if(!memcmp(pstat->wnm.target_bssid, pstat->hwaddr, MACADDRLEN)) { + DOT11VDEBUG("No need to roam!(The Same Bssid) \n"); + } else { + if(validate_target_bssid(priv, pstat) == 0) { + DOT11VDEBUG("start bss transition!\n"); + + // diassoc the present connecting AP + issue_disassoc(priv, pstat->hwaddr, _RSON_DISASSOC_DUE_BSS_TRANSITION); + del_station(priv, pstat, 0); + + // set the roaming target + memcpy(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid ,pstat->wnm.target_bssid, MACADDRLEN); + }else + DOT11VDEBUG("Validate NG: Client couldn't find target !\n"); + } +} + +static void set_target_bssid(struct stat_info *pstat) +{ + if (pstat->wnm.num_neighbor_report == 0) + return; + + memcpy(pstat->wnm.target_bssid, pstat->wnm.neighbor_report[0].bssid, MACADDRLEN); // preference highest one +} + +// for debug usage +static void dump_cand_list(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + unsigned char i; + struct dot11k_neighbor_report *report; + + for(i = 0; i < pstat->wnm.num_neighbor_report; i++) { + report = &pstat->wnm.neighbor_report[i]; + + panic_printk("(%d)=>[%02x][%02x][%02x][%02x][%02x][%02x], bssinfo=%u, op_class=%u chan=%u phy=%u, prf = %d \n", + i, report->bssid[0], report->bssid[1], report->bssid[2], report->bssid[3], report->bssid[4], report->bssid[5], + report->bssinfo.value, report->op_class, report->channel, report->phytype, report->subelemnt.preference); + } +} + +static void sort_candidate_list(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + DOT11VDEBUG("Candidate List num = %d\n",pstat->wnm.num_neighbor_report); + if (pstat->wnm.num_neighbor_report == 0) + return; + + qsort(pstat->wnm.neighbor_report, pstat->wnm.num_neighbor_report, sizeof(struct dot11k_neighbor_report), cand_pref_compar); + update_neighbor_report(priv, pstat); +} + +static void parse_subelement(struct rtl8192cd_priv *priv, unsigned char id + ,unsigned char *pos, unsigned char elen, struct dot11k_neighbor_report *report) +{ + report->subelemnt.subelement_id = id; + + switch(id) { + case _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_: + if(elen < 1) { + panic_printk("Too short BSS transition candidate \n"); + break; + } + report->subelemnt.len = elen; + report->subelemnt.preference = pos[0]; + break; + default: + panic_printk("Not implemented subelement id! \n"); + break; + } +} + +static void parse_neighbor_report(struct rtl8192cd_priv *priv, unsigned char *pos, unsigned char len, + struct dot11k_neighbor_report *report) +{ + unsigned char left = len; + if(left < NEIGHBOR_REPORT_SIZE) { + panic_printk("Too short neighbor report \n"); + return; + } + + memcpy(report->bssid, pos, MACADDRLEN); + pos += MACADDRLEN; + report->bssinfo.value = le32_to_cpu(*(unsigned int *)&pos[0]); + pos += sizeof(int); + report->op_class = *pos; + pos++; + report->channel = *pos; + pos++; + report->phytype = *pos; + pos++; + + left -= 13; + + DOT11VTRACE("[%02x][%02x][%02x][%02x][%02x][%02x], bssinfo=%u, op_class=%u chan=%u phy=%u \n", + report->bssid[0], report->bssid[1], report->bssid[2], report->bssid[3], report->bssid[4], report->bssid[5], + report->bssinfo.value, report->op_class, report->channel, report->phytype); + while(left >= 2) { + unsigned char id, elen; + id = *pos++; + elen = *pos++; + + left -= 2; + if(elen > left) { + DOT11VDEBUG("Truncated neighbor report subelement \n"); + break; + } + parse_subelement(priv, id, pos, elen, report); + left -= elen; + pos += elen; + } + +} + +void OnBSSTransReq(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len) +{ + int frlen = 0; + enum bss_trans_mgmt_status_code status; + unsigned char valid_int; + unsigned int beacon_int = 100; + unsigned char *pos = (pframe+2); + + if(frame_len <5) { + panic_printk(" Ignore too short BSS Transition Management Request!\n"); + return; + } + + pstat->wnm.dialog_token = pos[0]; + pstat->wnm.req_mode = pos[1]; + pstat->wnm.dissoc_timer = le16_to_cpu(*(unsigned short *) &pos[2]); + pstat->wnm.reply = TRUE; + valid_int = pos[4]; + + DOT11VDEBUG("BSS Trans Req: dialog_token=%u, req_mode=0x%x, dissoc_timer=%u, valid_int=%u, frame_len = %d \n", + pstat->wnm.dialog_token, pstat->wnm.req_mode, pstat->wnm.dissoc_timer, valid_int, frame_len); + + pos += 5; + frlen += 7; + if(pstat->wnm.req_mode & _WNM_BSS_TERMINATION_INCLUDED_) { + DOT11VTRACE("BSS termination included \n"); + if(frlen + 12 > frame_len) { //Bss Trans duration 0 or 12 + panic_printk("Too short BSS TM Request \n"); + return; + } + memcpy(pstat->wnm.bss_termination_duration, pos, BSS_TERMINATION_DURATION_LEN); + pos += BSS_TERMINATION_DURATION_LEN; + frlen += BSS_TERMINATION_DURATION_LEN; + } + + if(pstat->wnm.req_mode & _WNM_ESS_DIASSOC_IMMINENT_) { + unsigned char url[256]; + if (frlen + 1 > frame_len || frlen + 1 + pos[1] > frame_len) { + panic_printk("Invalid BSS Transition Management Request (URL)"); + return; + } + memcpy(url, pos+1, pos[0]); + url[pos[0]] ='\0'; + pos += 1 + pos[0]; + frlen += 1 + pos[0]; + DOT11VTRACE("ESS_DISASSOC_IMMINENT(disassoc_timer: %u, url: %s)", pstat->wnm.dissoc_timer * beacon_int * 128 / 125, url); + } + + if(pstat->wnm.req_mode & _WNM_DIASSOC_IMMINENT_) { + DOT11VTRACE("Disassociation Imminent: dissoc_timer:%u\n", pstat->wnm.dissoc_timer); + if(pstat->wnm.dissoc_timer) { + start_clnt_lookup(priv, 1); //start rescan(needed to check) + } + } + + if(pstat->wnm.req_mode & _WNM_PREFERRED_CANDIDATE_LIST_) { + DOT11VTRACE("PREFERRED_CANDIDATE_LIST: \n"); + unsigned int valid_ms; + + int neighbor_size = sizeof(struct dot11k_neighbor_report); + memset(pstat->wnm.neighbor_report, 0, neighbor_size * MAX_NEIGHBOR_REPORT); + + while((frlen + 2 <= frame_len) && + pstat->wnm.num_neighbor_report < MAX_NEIGHBOR_REPORT) + { + unsigned char tag = *pos++; + unsigned char len = *pos++; + frlen += 2; + + if(frlen + len > frame_len) { + panic_printk("Truncated request size"); + return; + } + + if(tag == _NEIGHBOR_REPORT_IE_) { + struct dot11k_neighbor_report *report; + report = &pstat->wnm.neighbor_report[pstat->wnm.num_neighbor_report]; + parse_neighbor_report(priv, pos, len, report); + } + + pos += len; + frlen += len; + pstat->wnm.num_neighbor_report++; + } + + sort_candidate_list(priv, pstat); +#ifdef DOT11V_DEBUG + dump_cand_list(priv, pstat); +#endif + set_target_bssid(pstat); + valid_ms = valid_int * beacon_int * 128 / 125; + pstat->wnm.candidate_valid_time = (valid_ms)/1000; + DOT11VTRACE("Candidate list valid for (%d) ms/(%d) sec\n", valid_ms, pstat->wnm.candidate_valid_time); + } + + if(pstat->wnm.reply) { + if(pstat->wnm.req_mode & _WNM_PREFERRED_CANDIDATE_LIST_) + status = WNM_BSS_TM_ACCEPT; + else { + DOT11VDEBUG("BSS Transition Request did not include candidates \n"); + status = WNM_BSS_TM_REJECT_UNSPECIFIED; + } + + if(issue_BSS_Trans_Rsp(priv, pstat, pstat->wnm.dialog_token, status) == 0) + start_bss_transition(priv, pstat); + } + return; +} + +#endif + +static void process_status_code( struct stat_info *pstat, unsigned char status_code) +{ + pstat->bssTransStatusCode = status_code; + + if(status_code) + pstat->bssTransRejectionCount++; + + switch(status_code) { + case WNM_BSS_TM_ACCEPT: + panic_printk("Accept: WNM_BSS_TM_ACCEPT![%02x][%02x][%02x][%02x][%02x][%02x] \n", + pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5]); + + pstat->bssTransRejectionCount = 0; + break; + case WNM_BSS_TM_REJECT_UNSPECIFIED: + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_UNSPECIFIED!\n"); + break; + case WNM_BSS_TM_REJECT_INSUFFICIENT_BEACON: + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_INSUFFICIENT_BEACON!\n"); + break; + case WNM_BSS_TM_REJECT_INSUFFICIENT_CAPABITY: + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_INSUFFICIENT_CAPABITY!\n"); + break; + case WNM_BSS_TM_REJECT_UNDESIRED : + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_UNDESIRED !\n"); + break; + case WNM_BSS_TM_REJECT_DELAY_REQUEST : + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_DELAY_REQUEST !\n"); + break; + case WNM_BSS_TM_REJECT_STA_CANDIDATE_LIST_PROVIDED : + panic_printk("Reject: WNM_BSS_TM_REJECT_STA_CANDIDATE_LIST_PROVIDED !\n"); + break; + case WNM_BSS_TM_REJECT_NO_SUITABLE_CANDIDATES: + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_NO_SUITABLE_CANDIDATES !\n"); + break; + case WNM_BSS_TM_REJECT_LEAVING_ESS: + DOT11VDEBUG("Reject: WNM_BSS_TM_REJECT_LEAVING_ESS !\n"); + break; + default: + DOT11VDEBUG("unknown type !\n"); + break; + } +} + +void OnBSSTransRsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char*pframe, int frame_len) +{ + int frlen = 0; + + if(frame_len < 3) { + panic_printk("Ignore too short BSS Trans Management RSP!\n"); + return; + } + + unsigned char dialog_token = pframe[2]; + unsigned char status_code = pframe[3]; + unsigned char bss_termination_delay = pframe[4]; //mins + frlen = 5; + + if((frame_len - frlen) > MAX_LIST_LEN) + return; + + DOT11VTRACE("dialog_token = %d, bss_termination_delay = %d\n", dialog_token, bss_termination_delay); + process_status_code(pstat, status_code); + pstat->bssTransExpiredTime = 0; + pstat->bssTransTriggered = 0; + + if((frame_len - frlen) > 0) { + if(status_code == WNM_BSS_TM_ACCEPT) { + debug_out("Target BSSID: ", &pframe[frlen], MACADDRLEN); + frlen += MACADDRLEN; + debug_out("Bss Trans Candidate List: ", &pframe[frlen], frame_len - frlen); + }else if(status_code == WNM_BSS_TM_REJECT_DELAY_REQUEST){ + priv->pmib->wnmEntry.dot11vDiassocDeadline = bss_termination_delay*60; + }else + debug_out("Bss Trans Candidate List: ", &pframe[frlen], frame_len - frlen); + }else { + DEBUG_ERR("WNM: no info in bss trans response!\n"); + } + + return; +} + +void OnBSSTransQuery(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char*pframe, int frame_len) +{ + int list_len; + + if(frame_len < 2) { + DEBUG_ERR("Ignore too short BSS Transition Management Query!\n"); + return; + } + + unsigned char dialog_token = pframe[2]; + unsigned char reason = pframe[3]; + + DOT11VTRACE("dialog_token = %d, reason = %d\n", dialog_token, reason); + + if(reason == _WNM_PREFERED_BSS_TRANS_LIST_INCLUDED_) { + list_len = frame_len - 4; + + if(list_len > MAX_LIST_LEN) + return; + debug_out("Bss List Len: ", &pframe[list_len], frame_len - list_len); + } else + panic_printk("WNM_PREFERED BSS TRANS LIST NOT INCLUDED!\n"); + + issue_BSS_Trans_Req(priv, pstat->hwaddr, dialog_token); +} + +void WNM_ActionHandler(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len) +{ + unsigned char action_field = pframe[1]; + + switch (action_field) { + case _WNM_TSMQUERY_ACTION_ID_: + OnBSSTransQuery(priv, pstat, pframe, frame_len); + break; + case _BSS_TSMRSP_ACTION_ID_: + OnBSSTransRsp(priv, pstat, pframe, frame_len); + break; + #ifdef CONFIG_IEEE80211V_CLI + case _BSS_TSMREQ_ACTION_ID_: + OnBSSTransReq(priv, pstat, pframe, frame_len); + break; + #endif + default: + DEBUG_INFO("Other WNM action: %d:\n", action_field); + break; + } +} + diff --git a/package/kernel/rtl8192cd/8192cd_11v.h b/package/kernel/rtl8192cd/8192cd_11v.h index 895a42133d3..f0c63c22006 100644 --- a/package/kernel/rtl8192cd/8192cd_11v.h +++ b/package/kernel/rtl8192cd/8192cd_11v.h @@ -1,74 +1,74 @@ - -#ifndef _8192CD_11V_H_ -#define _8192CD_11V_H_ - - - -#ifdef DOT11V_DEBUG -#define DOT11VDEBUG(fmt, args...) panic_printk("[%s %d]"fmt,__FUNCTION__,__LINE__,## args) -#else -#define DOT11VDEBUG(fmt, args...) -#endif - -//#define DOT11V_TRACE -#ifdef DOT11V_TRACE -#define DOT11VTRACE(fmt, args...) panic_printk("[%s %d]"fmt,__FUNCTION__,__LINE__,## args) -#else -#define DOT11VTRACE(fmt, args...) -#endif - -#ifndef _8192CD_11V_C_ -#define EXTERN extern -#else -#define EXTERN -#endif - -#define _WNM_TSF_INFO_ 1 -#define _WNM_CONDENSED_COUNTRY_STRING_ 2 -#define _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_ 3 -#define _WNM_BSS_TERMINATION_DURATION_ 4 -#define _WNM_BEARING_ 5 -#define _WNM_MEASUREMENT_PILOT_ 66 -#define _WNM_RRM_ENABLED_CAPABILITIES_ 70 -#define _WNM_MULTIPLE_BSSID_ 71 - -#define TRANS_LIST_PROC_LEN 50 -#define MAX_PREFERRED_VAL 255 -#define NEIGHBOR_REPORT_SIZE 13 // size of neighbor report structure - - -EXTERN unsigned char getPreferredVal(struct rtl8192cd_priv *priv, unsigned char channel_utilization, unsigned char rcpi, bool excluded); -EXTERN void OnBSSTransQuery(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); -EXTERN void OnBSSTransRsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); -EXTERN int issue_BSS_Trans_Req(struct rtl8192cd_priv *priv, unsigned char *da, unsigned char dialog_token); -EXTERN unsigned char * construct_neighbor_report_ie(unsigned char *pbuf, unsigned int *frlen, struct dot11k_neighbor_report * report); -EXTERN void set_staBssTransCap(struct stat_info *pstat, unsigned char *pframe, int frameLen, unsigned short ie_offset); -EXTERN void reset_staBssTransStatus(struct stat_info *pstat); -EXTERN void WNM_ActionHandler(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); -EXTERN void set_BssTransPara(struct rtl8192cd_priv *priv, unsigned char *tmpbuf); -EXTERN void send_bss_trans_event(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char i); -EXTERN void process_BssTransReq(struct rtl8192cd_priv *priv); -EXTERN void BssTrans_DiassocTimer(struct rtl8192cd_priv *priv); -EXTERN void BssTrans_ExpiredTimer(struct rtl8192cd_priv *priv); -EXTERN void BssTrans_ValidatePrefListTimer(struct rtl8192cd_priv *priv); -EXTERN void BssTrans_TerminationTimer(struct rtl8192cd_priv *priv); - - -#ifdef CONFIG_RTL_PROC_NEW -EXTERN int rtl8192cd_proc_transition_list_read(struct seq_file *s, void *data); -#else -EXTERN int rtl8192cd_proc_transition_list_read(char *buf, char **start, off_t offset, int length, int *eof, void *data); -#endif - -#ifdef __ECOS -EXTERN int rtl8192cd_proc_transition_list_write(char *tmp, void *data) -#else -EXTERN int rtl8192cd_proc_transition_list_write(struct file *file, const char *buffer, unsigned long count, void *data); -#endif - -#ifdef CONFIG_IEEE80211V_CLI -EXTERN void OnBSSTransReq(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); -#endif - - -#endif + +#ifndef _8192CD_11V_H_ +#define _8192CD_11V_H_ + + + +#ifdef DOT11V_DEBUG +#define DOT11VDEBUG(fmt, args...) panic_printk("[%s %d]"fmt,__FUNCTION__,__LINE__,## args) +#else +#define DOT11VDEBUG(fmt, args...) +#endif + +//#define DOT11V_TRACE +#ifdef DOT11V_TRACE +#define DOT11VTRACE(fmt, args...) panic_printk("[%s %d]"fmt,__FUNCTION__,__LINE__,## args) +#else +#define DOT11VTRACE(fmt, args...) +#endif + +#ifndef _8192CD_11V_C_ +#define EXTERN extern +#else +#define EXTERN +#endif + +#define _WNM_TSF_INFO_ 1 +#define _WNM_CONDENSED_COUNTRY_STRING_ 2 +#define _WNM_BSS_TRANS_CANDIDATE_PREFRENCE_ 3 +#define _WNM_BSS_TERMINATION_DURATION_ 4 +#define _WNM_BEARING_ 5 +#define _WNM_MEASUREMENT_PILOT_ 66 +#define _WNM_RRM_ENABLED_CAPABILITIES_ 70 +#define _WNM_MULTIPLE_BSSID_ 71 + +#define TRANS_LIST_PROC_LEN 50 +#define MAX_PREFERRED_VAL 255 +#define NEIGHBOR_REPORT_SIZE 13 // size of neighbor report structure + + +EXTERN unsigned char getPreferredVal(struct rtl8192cd_priv *priv, unsigned char channel_utilization, unsigned char rcpi, bool excluded); +EXTERN void OnBSSTransQuery(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); +EXTERN void OnBSSTransRsp(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); +EXTERN int issue_BSS_Trans_Req(struct rtl8192cd_priv *priv, unsigned char *da, unsigned char dialog_token); +EXTERN unsigned char * construct_neighbor_report_ie(unsigned char *pbuf, unsigned int *frlen, struct dot11k_neighbor_report * report); +EXTERN void set_staBssTransCap(struct stat_info *pstat, unsigned char *pframe, int frameLen, unsigned short ie_offset); +EXTERN void reset_staBssTransStatus(struct stat_info *pstat); +EXTERN void WNM_ActionHandler(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); +EXTERN void set_BssTransPara(struct rtl8192cd_priv *priv, unsigned char *tmpbuf); +EXTERN void send_bss_trans_event(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char i); +EXTERN void process_BssTransReq(struct rtl8192cd_priv *priv); +EXTERN void BssTrans_DiassocTimer(struct rtl8192cd_priv *priv); +EXTERN void BssTrans_ExpiredTimer(struct rtl8192cd_priv *priv); +EXTERN void BssTrans_ValidatePrefListTimer(struct rtl8192cd_priv *priv); +EXTERN void BssTrans_TerminationTimer(struct rtl8192cd_priv *priv); + + +#ifdef CONFIG_RTL_PROC_NEW +EXTERN int rtl8192cd_proc_transition_list_read(struct seq_file *s, void *data); +#else +EXTERN int rtl8192cd_proc_transition_list_read(char *buf, char **start, off_t offset, int length, int *eof, void *data); +#endif + +#ifdef __ECOS +EXTERN int rtl8192cd_proc_transition_list_write(char *tmp, void *data) +#else +EXTERN int rtl8192cd_proc_transition_list_write(struct file *file, const char *buffer, unsigned long count, void *data); +#endif + +#ifdef CONFIG_IEEE80211V_CLI +EXTERN void OnBSSTransReq(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *pframe, int frame_len); +#endif + + +#endif diff --git a/package/kernel/rtl8192cd/8192cd_a4_sta.c b/package/kernel/rtl8192cd/8192cd_a4_sta.c index faed082b2d8..500950ff0d8 100644 --- a/package/kernel/rtl8192cd/8192cd_a4_sta.c +++ b/package/kernel/rtl8192cd/8192cd_a4_sta.c @@ -1,850 +1,850 @@ -/* - * a4 sta functions - * - * $Id: 8192cd_a4_sta.c,v 1.1 2010/10/13 06:38:58 davidhsu Exp $ - * - * Copyright (c) 2010 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define _8192CD_A4_STA_C_ - -#ifdef __KERNEL__ -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" -#include "./8192cd.h" -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" - -#ifdef A4_STA - -#define A4_VERSION 0x01 - -#if (A4_STA_OUI == A4_STA_OUT_REALTEK) -const unsigned char a4_oui[] = {0x00, 0xe0, 0x4c}; -#elif (A4_STA_OUI == A4_STA_OUT_CUSTOMER_1) -const unsigned char a4_oui[] = {0x00, 0x0d, 0x02}; -#define ENABLE_ECM_1_0 -#endif - -//#define A4_STA_DEBUG - -static struct a4_sta_db_entry *alloc_entry(struct rtl8192cd_priv *priv) -{ - int i; - - for (i=0; ia4_ent[i].used) - { - priv->a4_ent[i].used = 1; - return &priv->a4_ent[i].entry; - } - } - return NULL; -} - -static void free_entry(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *entry) -{ - int i; - - for (i=0; ia4_ent[i].used && (entry == &priv->a4_ent[i].entry)) - { - priv->a4_ent[i].used = 0; - break; - } - } -} - -static int mac_hash(unsigned char *networkAddr) -{ - unsigned long x; - - x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; - - return x & (A4_STA_HASH_SIZE - 1); -} - -static void mac_hash_link(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *ent, int hash) -{ - ent->next_hash = priv->machash[hash]; - - if (ent->next_hash != NULL) - ent->next_hash->pprev_hash = &ent->next_hash; - priv->machash[hash] = ent; - ent->pprev_hash = &priv->machash[hash]; -} - -static void mac_hash_unlink(struct a4_sta_db_entry *ent) -{ - *(ent->pprev_hash) = ent->next_hash; - if (ent->next_hash != NULL) - ent->next_hash->pprev_hash = ent->pprev_hash; - ent->next_hash = NULL; - ent->pprev_hash = NULL; -} - -static unsigned long _timeout(struct rtl8192cd_priv *priv) -{ - unsigned long timeout; - - timeout = jiffies - A4_STA_AGEING_TIME*HZ; - return timeout; -} - -static int has_expired(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *fdb) -{ - if (time_before_eq(fdb->ageing_timer, _timeout(priv))) - return 1; - - return 0; -} - -void a4_sta_del(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct a4_sta_db_entry *db; - int hash; - - ASSERT(mac); - - hash = mac_hash(mac); - db = priv->machash[hash]; - - while (db != NULL) - { - if (!memcmp(db->mac, mac, ETH_ALEN)) - { - #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) - release_brsc_cache(db->mac); - #endif - mac_hash_unlink(db); - free_entry(priv, db); -#ifdef A4_STA_DEBUG - panic_printk("%s A4 STA DEL emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", - priv->dev->name, - db->mac[0], - db->mac[1], - db->mac[2], - db->mac[3], - db->mac[4], - db->mac[5], - db->stat->hwaddr[0], - db->stat->hwaddr[1], - db->stat->hwaddr[2], - db->stat->hwaddr[3], - db->stat->hwaddr[4], - db->stat->hwaddr[5]); -#endif - return; - } - db = db->next_hash; - } -} - - -void a4_sta_update(struct rtl8192cd_priv *root_priv, struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct rtl8192cd_priv *current_priv; - int j; - -#ifdef A4_STA_DEBUG - panic_printk("A4 STA UPDATE emac:%02x%02x%02x%02x%02x%02x\n", - mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); -#endif - - current_priv = root_priv; - if(IS_DRV_OPEN(current_priv) && priv != current_priv) - { - a4_sta_del(current_priv, mac); - } - -#ifdef MBSSID - if (root_priv->pmib->miscEntry.vap_enable) - { - for (j=0; jpvap_priv[j]; - if(IS_DRV_OPEN(current_priv) && priv != current_priv) - { - a4_sta_del(current_priv, mac); - } - } - } -#endif -#ifdef UNIVERSAL_REPEATER - current_priv = GET_VXD_PRIV(root_priv); - if(IS_DRV_OPEN(current_priv) && priv != current_priv) - { - a4_sta_del(current_priv, mac); - } -#endif - -} - -void a4_sta_cleanup_all(struct rtl8192cd_priv *priv) -{ - int i; - - if (priv->pshare->rf_ft_var.a4_enable) - { - for (i=0; imachash[i]; - - while (f != NULL) - { - struct a4_sta_db_entry *g; - - g = f->next_hash; - mac_hash_unlink(f); - free_entry(priv, f); - f = g; - } - } - } -} - -void a4_sta_cleanup(struct rtl8192cd_priv *priv, struct stat_info * pstat) -{ - int i; - struct a4_sta_db_entry *f; - struct a4_sta_db_entry *g; - for (i=0; imachash[i]; - while (f != NULL) - { - g = f->next_hash; - if(f->stat == pstat) { - #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) - release_brsc_cache(f->mac); - #endif - mac_hash_unlink(f); - free_entry(priv, f); - } - f = g; - } - } -} - - -void a4_sta_expire(struct rtl8192cd_priv *priv) -{ - int i; - - if (priv->pshare->rf_ft_var.a4_enable) - { - for (i=0; imachash[i]; - - while (f != NULL) - { - struct a4_sta_db_entry *g; - g = f->next_hash; - - if (has_expired(priv, f)) - { -#ifdef A4_STA_DEBUG - panic_printk("%s A4 STA Expire (%02d) emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", - priv->dev->name, - i, - f->mac[0], - f->mac[1], - f->mac[2], - f->mac[3], - f->mac[4], - f->mac[5], - f->stat->hwaddr[0], - f->stat->hwaddr[1], - f->stat->hwaddr[2], - f->stat->hwaddr[3], - f->stat->hwaddr[4], - f->stat->hwaddr[5]); -#endif - - #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) - release_brsc_cache(f->mac); - #endif - mac_hash_unlink(f); - free_entry(priv, f); - } - f = g; - } - } - } -} - -void a4_sta_add(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *mac) -{ - struct a4_sta_db_entry *db; - int hash; - unsigned char tmpbuf[15]; - - ASSERT(mac); - - hash = mac_hash(mac); - db = priv->machash[hash]; - - while (db != NULL) - { - if (!memcmp(db->mac, mac, ETH_ALEN)) - { - db->stat = pstat; - db->ageing_timer = jiffies; - return; - } - db = db->next_hash; - } - - if(memcmp(pstat->hwaddr, mac, MACADDRLEN)) { - sprintf((char *)tmpbuf, "%02x%02x%02x%02x%02x%02xno", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - del_sta(priv, tmpbuf); - } - - db = alloc_entry(priv); - if (db == NULL) - { - DEBUG_ERR("alloc_entry() failed for a4_sta_db_entry!\n"); - return; - } - memcpy(db->mac, mac, ETH_ALEN); - db->stat = pstat; - db->ageing_timer = jiffies; - -#ifdef A4_STA_DEBUG - panic_printk("%s A4 STA Add emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", - priv->dev->name, - db->mac[0], - db->mac[1], - db->mac[2], - db->mac[3], - db->mac[4], - db->mac[5], - db->stat->hwaddr[0], - db->stat->hwaddr[1], - db->stat->hwaddr[2], - db->stat->hwaddr[3], - db->stat->hwaddr[4], - db->stat->hwaddr[5]); -#endif - - mac_hash_link(priv, db, hash); - - a4_sta_update(GET_ROOT(priv), priv, mac); - -} - -struct stat_info *a4_sta_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct a4_sta_db_entry *db; - - ASSERT(mac); - - db = priv->machash[mac_hash(mac)]; - - while (db != NULL) - { - if (!memcmp(db->mac, mac, ETH_ALEN)) - { - -#ifdef A4_STA_DEBUG - panic_printk("%s A4 STA LOOKUP emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", - priv->dev->name, - db->mac[0], - db->mac[1], - db->mac[2], - db->mac[3], - db->mac[4], - db->mac[5], - db->stat->hwaddr[0], - db->stat->hwaddr[1], - db->stat->hwaddr[2], - db->stat->hwaddr[3], - db->stat->hwaddr[4], - db->stat->hwaddr[5]); -#endif - return db->stat; - } - - db = db->next_hash; - } - return NULL; -} - -void add_a4_client(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - struct list_head *phead, *plist; - struct stat_info *sta; - - if (!netif_running(priv->dev)) - return; - - phead = &priv->a4_sta_list; - plist = phead->next; - - while (plist != phead) - { - sta = list_entry(plist, struct stat_info, a4_sta_list); - if (!memcmp(sta->hwaddr, pstat->hwaddr, WLAN_ADDR_LEN)) - { - ASSERT(pstat == sta); - break; - } - plist = plist->next; - } - - if (plist == phead) - list_add_tail(&pstat->a4_sta_list, &priv->a4_sta_list); - - pstat->state |= WIFI_A4_STA; -} - -unsigned char parse_a4_ie(struct rtl8192cd_priv *priv, unsigned char* p, int limit) -{ - - unsigned char * pframe = p; - int len = 0; - for (;;) - { - p = get_ie(p, _RSN_IE_1_, &len, - limit - (p - pframe)); - if (p != NULL) - { - if (!memcmp(p+2, a4_oui, 3)) - { - if(p[5] == 0x03 && (p[8] & BIT6)) /*check ECM 2.0*/ - { - return 1; - } - } - } - else - break; - - p = p + len + 2; - } - - return 0; -} - -void a4_tx_unknown_unicast(struct rtl8192cd_priv *priv, struct sk_buff *skb) -{ - struct list_head *phead, *plist; - struct stat_info *pstat, *sa_stat; - struct sk_buff *newskb; - - - sa_stat = get_stainfo(priv, skb->data+MACADDRLEN); - if(sa_stat == NULL) - { - sa_stat = a4_sta_lookup(priv, skb->data+MACADDRLEN); - } - - phead = &priv->a4_sta_list; - plist = phead->next; - while (phead && (plist != phead)) - { - pstat = list_entry(plist, struct stat_info, a4_sta_list); - plist = plist->next; - if(pstat != sa_stat) - { - newskb = skb_copy(skb, GFP_ATOMIC); - if (newskb) - { - newskb->cb[2] = (char)0xff; // not do aggregation - #if defined(CONFIG_RTK_MESH) - __rtl8192cd_start_xmit_out(newskb, pstat, NULL); - #else - __rtl8192cd_start_xmit_out(newskb, pstat); - #endif - } - else - { - return; - } - } - } - -} - -unsigned char a4_tx_mcast_to_unicast(struct rtl8192cd_priv *priv, struct sk_buff *skb) -{ - struct list_head *phead, *plist; - struct stat_info *pstat, *sa_stat; - struct sk_buff *newskb; - - int sta_count = 0; - - sa_stat = get_stainfo(priv, skb->data+MACADDRLEN); - if(sa_stat == NULL) - { - sa_stat = a4_sta_lookup(priv, skb->data+MACADDRLEN); - } - - phead = &priv->asoc_list; - plist = phead->next; - while (phead && (plist != phead)) - { - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - - if(pstat != sa_stat) - { - if(pstat->state & WIFI_A4_STA) - { - newskb = skb_copy(skb, GFP_ATOMIC); - if (newskb) - { - newskb->cb[2] = (char)0xff; // not do aggregation - - #if defined(CONFIG_RTK_MESH) - __rtl8192cd_start_xmit_out(newskb, pstat, NULL); - #else - __rtl8192cd_start_xmit_out(newskb, pstat); - #endif - } - else - { - continue; - } - } - else - { - sta_count++; - } - } - } - - if(sta_count == 0) - { - return 1; - } - return 0; -} - -int a4_rx_dispatch(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo -#ifdef MBSSID - ,int vap_idx -#endif - ) -{ - - unsigned int opmode; - unsigned char *pframe = get_pframe(pfrinfo); - int reuse = 1; - -#ifdef MBSSID - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable && (vap_idx >= 0)) - { - priv = priv->pvap_priv[vap_idx]; - } -#endif - - opmode = OPMODE; - -#ifdef CLIENT_MODE - if((opmode & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == - (WIFI_STATION_STATE | WIFI_ASOC_STATE)) - { - if (IS_BSSID(priv, GetAddr2Ptr(pframe))) - { - reuse = a4_rx_check_reuse(priv, pfrinfo, GET_MY_HWADDR); - } - } - else -#endif - if (opmode & WIFI_AP_STATE) - { -#ifdef UNIVERSAL_REPEATER - if(IS_DRV_OPEN(GET_VXD_PRIV(priv)) && IS_BSSID(GET_VXD_PRIV(priv), GetAddr2Ptr(pframe))) - { - reuse = a4_rx_check_reuse(GET_VXD_PRIV(priv), pfrinfo, GET_MY_HWADDR); - if (reuse == 0) - { - priv = GET_VXD_PRIV(priv); - } - } - else -#endif - if (IS_BSSID(priv, GetAddr1Ptr(pframe))) - { - reuse = 0; - } - - } - - if(reuse == 0) - { -#ifdef RTL8190_DIRECT_RX - rtl8192cd_rx_dataframe(priv, NULL, pfrinfo); -#else - SMP_LOCK_RX_DATA(x); - list_add_tail(&(pfrinfo->rx_list), &(priv->rx_datalist)); - SMP_UNLOCK_RX_DATA(x); -#endif - - } - - rx_sum_up(priv, NULL, pfrinfo); - - return reuse; -} - - -struct stat_info *a4_rx_check_reuse_ap(struct rtl8192cd_priv *priv, struct stat_info *pstat, struct rx_frinfo *pfrinfo) -{ - if(priv->pshare->rf_ft_var.a4_enable == 2) { - /*only recieve 4 address packet from A4 client when a4_enable = 2*/ - if(((pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds != 3) || - (!(pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds == 3) - ) { - return NULL; - } - } - else { - if(!(pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds == 3) - add_a4_client(priv, pstat); - } - - if(pfrinfo->to_fr_ds == 3 && (pstat->state & WIFI_A4_STA)) - { - a4_sta_add(priv, pstat, pfrinfo->sa); - } - - return pstat; -} - - -#ifdef CLIENT_MODE -unsigned char a4_rx_check_reuse(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo, unsigned char * myhwaddr) -{ - struct stat_info * pstat; - unsigned char reuse = 1; - unsigned char *pframe = get_pframe(pfrinfo); - struct net_bridge_fdb_entry *fdb; - - pstat = get_stainfo(priv, GetAddr2Ptr(pframe)); //bssid - if(pstat) - { - if(pstat->state & WIFI_A4_STA) /*A4 AP*/ - { - /* when a4_enable = 1, also recieve 3-address from an A4 AP*/ - if(pfrinfo->to_fr_ds == 1 && priv->pshare->rf_ft_var.a4_enable == 1) { - - if(IS_MCAST(pfrinfo->da)) { - /*filter*/ - reuse = 0; - fdb = fdb_find_for_driver(GET_BR_PORT(priv->dev)->br, pfrinfo->sa); - if(fdb) { - /*if sa is recorded in other interface, it may be a loop packet, drop it*/ - if(strcmp(fdb->dst->dev->name, priv->dev->name)) - reuse = 1; - } - } - else if(isEqualMACAddr(pfrinfo->da, myhwaddr)){ /*unicast*/ - reuse = 0; - } - - } - /*other case, only recieve 4 address packet*/ - else if(pfrinfo->to_fr_ds == 3 && isEqualMACAddr(GetAddr1Ptr(pframe), myhwaddr)) - { - a4_sta_add(priv, pstat, pfrinfo->sa); - if(!IS_MCAST(pfrinfo->da)) - a4_sta_del(priv, pfrinfo->da); - reuse = 0; - } - } - else /*legacy AP*/ - { - /*only recieve 3 address packet*/ - if (pfrinfo->to_fr_ds == 1 && (IS_MCAST(pfrinfo->da) || isEqualMACAddr(pfrinfo->da, myhwaddr))) - { - reuse = 0; - } - } - } - - return reuse; -} -#endif - -#ifndef __OSK__ -#ifdef CONFIG_RTL_PROC_NEW -int a4_dump_sta_info(struct seq_file *s, void *data) -#else -int a4_dump_sta_info(char *buf, char **start, off_t offset, - int length, int *eof, void *data) -#endif -{ - struct net_device *dev = PROC_GET_DEV(); - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct a4_sta_db_entry *db; - int i; - int pos = 0; - PRINT_ONE(" -- A4 STA info -- ", "%s", 1); - - for (i = 0 ; i < A4_STA_HASH_SIZE; i++) - { - db = priv->machash[i]; - while (db != NULL) - { - PRINT_ARRAY_ARG(" STA_MAC: ", db->mac, "%02x", MACADDRLEN); - PRINT_ARRAY_ARG(" OWNER_MAC: ", db->stat->hwaddr, "%02x", MACADDRLEN); - PRINT_ONE((jiffies - db->ageing_timer)/HZ, " Aging time: %ld", 1); - db = db->next_hash; - } - } - - - - return pos; -} -#endif - -#endif /* A4_STA */ - - -#if defined(TV_MODE) || defined(A4_STA) -unsigned char * construct_ecm_tvm_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen, unsigned char mode) -{ - unsigned char temp[7]; - memcpy(temp, a4_oui, 3); - *(unsigned short *)(temp + 4) = cpu_to_le16(A4_VERSION); - temp[6] = 0; - - if(mode & BIT0) /*ECM*/ - { -#ifdef ENABLE_ECM_1_0 - temp[3] = 0x02; /*OUI type */ - temp[6] = BIT7; /*ECM 1.0*/ - pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); -#endif - temp[6] = BIT6; /*ECM 2.0*/ - } - -#ifdef TV_MODE - if(mode & BIT1) /* TV mode*/ - { - if(priv->tv_mode_status & BIT0) /*tv mode is enabled*/ - { - temp[6] |= BIT7; - } - } -#endif - - temp[3] = 0x03; /*OUI type */ - pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); - return pbuf; -} -#endif - -#ifdef TV_MODE -unsigned char * construct_tv_mode_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) -{ - unsigned char temp[7]; - memcpy(temp, a4_oui, 3); - *(unsigned short *)(temp + 4) = cpu_to_le16(A4_VERSION); - - temp[3] = 0x04; /*OUI type */ - temp[6] = BIT7; /*TV Auto*/ - pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); - return pbuf; -} - -unsigned char parse_tv_mode_ie(struct rtl8192cd_priv *priv, unsigned char* p, int limit) -{ - - unsigned char * pframe = p; - int len = 0; - for (;;) - { - p = get_ie(p, _RSN_IE_1_, &len, - limit - (p - pframe)); - if (p != NULL) - { - if (!memcmp(p+2, a4_oui, 3)) - { - if(p[5] == 0x04 && (p[8] & BIT7)) /*check TV Auto*/ - { - return 1; - } - } - } - else - break; - - p = p + len + 2; - } - - return 0; -} - -void tv_mode_auto_support_check(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat; - struct list_head *phead, *plist; - //unsigned long flags; - - phead = &priv->asoc_list; - plist = phead->next; - - priv->tv_mode_status &= ~BIT0; - while(plist != phead) - { - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - - if(pstat->tv_auto_support && pstat->expire_to > 0) - { - priv->tv_mode_status|= BIT0; - break; - } - } -} - -#ifdef SUPPORT_TX_MCAST2UNI -/*return: 0: no client joint, 1: has client joint*/ -unsigned char tv_mode_igmp_group_check(struct rtl8192cd_priv *priv, struct sk_buff *skb) -{ - struct stat_info *pstat; - struct list_head *phead, *plist; - int i; - - phead = &priv->asoc_list; - plist = phead; - while ((plist = asoc_list_get_next(priv, plist)) != phead) - { - pstat = list_entry(plist, struct stat_info, asoc_list); - /* avoid come from STA1 and send back STA1 */ - if (!memcmp(pstat->hwaddr, &skb->data[6], 6)) - { - continue; - } - if(pstat->leave || pstat->expire_to==0) - continue; - for (i=0; iipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[0], skb->data, 6)) - { - return 1; - } - } - } - return 0; - -} -#endif -#endif +/* + * a4 sta functions + * + * $Id: 8192cd_a4_sta.c,v 1.1 2010/10/13 06:38:58 davidhsu Exp $ + * + * Copyright (c) 2010 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define _8192CD_A4_STA_C_ + +#ifdef __KERNEL__ +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" + +#ifdef A4_STA + +#define A4_VERSION 0x01 + +#if (A4_STA_OUI == A4_STA_OUT_REALTEK) +const unsigned char a4_oui[] = {0x00, 0xe0, 0x4c}; +#elif (A4_STA_OUI == A4_STA_OUT_CUSTOMER_1) +const unsigned char a4_oui[] = {0x00, 0x0d, 0x02}; +#define ENABLE_ECM_1_0 +#endif + +//#define A4_STA_DEBUG + +static struct a4_sta_db_entry *alloc_entry(struct rtl8192cd_priv *priv) +{ + int i; + + for (i=0; ia4_ent[i].used) + { + priv->a4_ent[i].used = 1; + return &priv->a4_ent[i].entry; + } + } + return NULL; +} + +static void free_entry(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *entry) +{ + int i; + + for (i=0; ia4_ent[i].used && (entry == &priv->a4_ent[i].entry)) + { + priv->a4_ent[i].used = 0; + break; + } + } +} + +static int mac_hash(unsigned char *networkAddr) +{ + unsigned long x; + + x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; + + return x & (A4_STA_HASH_SIZE - 1); +} + +static void mac_hash_link(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *ent, int hash) +{ + ent->next_hash = priv->machash[hash]; + + if (ent->next_hash != NULL) + ent->next_hash->pprev_hash = &ent->next_hash; + priv->machash[hash] = ent; + ent->pprev_hash = &priv->machash[hash]; +} + +static void mac_hash_unlink(struct a4_sta_db_entry *ent) +{ + *(ent->pprev_hash) = ent->next_hash; + if (ent->next_hash != NULL) + ent->next_hash->pprev_hash = ent->pprev_hash; + ent->next_hash = NULL; + ent->pprev_hash = NULL; +} + +static unsigned long _timeout(struct rtl8192cd_priv *priv) +{ + unsigned long timeout; + + timeout = jiffies - A4_STA_AGEING_TIME*HZ; + return timeout; +} + +static int has_expired(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *fdb) +{ + if (time_before_eq(fdb->ageing_timer, _timeout(priv))) + return 1; + + return 0; +} + +void a4_sta_del(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct a4_sta_db_entry *db; + int hash; + + ASSERT(mac); + + hash = mac_hash(mac); + db = priv->machash[hash]; + + while (db != NULL) + { + if (!memcmp(db->mac, mac, ETH_ALEN)) + { + #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) + release_brsc_cache(db->mac); + #endif + mac_hash_unlink(db); + free_entry(priv, db); +#ifdef A4_STA_DEBUG + panic_printk("%s A4 STA DEL emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", + priv->dev->name, + db->mac[0], + db->mac[1], + db->mac[2], + db->mac[3], + db->mac[4], + db->mac[5], + db->stat->hwaddr[0], + db->stat->hwaddr[1], + db->stat->hwaddr[2], + db->stat->hwaddr[3], + db->stat->hwaddr[4], + db->stat->hwaddr[5]); +#endif + return; + } + db = db->next_hash; + } +} + + +void a4_sta_update(struct rtl8192cd_priv *root_priv, struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct rtl8192cd_priv *current_priv; + int j; + +#ifdef A4_STA_DEBUG + panic_printk("A4 STA UPDATE emac:%02x%02x%02x%02x%02x%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); +#endif + + current_priv = root_priv; + if(IS_DRV_OPEN(current_priv) && priv != current_priv) + { + a4_sta_del(current_priv, mac); + } + +#ifdef MBSSID + if (root_priv->pmib->miscEntry.vap_enable) + { + for (j=0; jpvap_priv[j]; + if(IS_DRV_OPEN(current_priv) && priv != current_priv) + { + a4_sta_del(current_priv, mac); + } + } + } +#endif +#ifdef UNIVERSAL_REPEATER + current_priv = GET_VXD_PRIV(root_priv); + if(IS_DRV_OPEN(current_priv) && priv != current_priv) + { + a4_sta_del(current_priv, mac); + } +#endif + +} + +void a4_sta_cleanup_all(struct rtl8192cd_priv *priv) +{ + int i; + + if (priv->pshare->rf_ft_var.a4_enable) + { + for (i=0; imachash[i]; + + while (f != NULL) + { + struct a4_sta_db_entry *g; + + g = f->next_hash; + mac_hash_unlink(f); + free_entry(priv, f); + f = g; + } + } + } +} + +void a4_sta_cleanup(struct rtl8192cd_priv *priv, struct stat_info * pstat) +{ + int i; + struct a4_sta_db_entry *f; + struct a4_sta_db_entry *g; + for (i=0; imachash[i]; + while (f != NULL) + { + g = f->next_hash; + if(f->stat == pstat) { + #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) + release_brsc_cache(f->mac); + #endif + mac_hash_unlink(f); + free_entry(priv, f); + } + f = g; + } + } +} + + +void a4_sta_expire(struct rtl8192cd_priv *priv) +{ + int i; + + if (priv->pshare->rf_ft_var.a4_enable) + { + for (i=0; imachash[i]; + + while (f != NULL) + { + struct a4_sta_db_entry *g; + g = f->next_hash; + + if (has_expired(priv, f)) + { +#ifdef A4_STA_DEBUG + panic_printk("%s A4 STA Expire (%02d) emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", + priv->dev->name, + i, + f->mac[0], + f->mac[1], + f->mac[2], + f->mac[3], + f->mac[4], + f->mac[5], + f->stat->hwaddr[0], + f->stat->hwaddr[1], + f->stat->hwaddr[2], + f->stat->hwaddr[3], + f->stat->hwaddr[4], + f->stat->hwaddr[5]); +#endif + + #if defined(BR_SHORTCUT) && defined(RTL_CACHED_BR_STA) + release_brsc_cache(f->mac); + #endif + mac_hash_unlink(f); + free_entry(priv, f); + } + f = g; + } + } + } +} + +void a4_sta_add(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *mac) +{ + struct a4_sta_db_entry *db; + int hash; + unsigned char tmpbuf[15]; + + ASSERT(mac); + + hash = mac_hash(mac); + db = priv->machash[hash]; + + while (db != NULL) + { + if (!memcmp(db->mac, mac, ETH_ALEN)) + { + db->stat = pstat; + db->ageing_timer = jiffies; + return; + } + db = db->next_hash; + } + + if(memcmp(pstat->hwaddr, mac, MACADDRLEN)) { + sprintf((char *)tmpbuf, "%02x%02x%02x%02x%02x%02xno", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + del_sta(priv, tmpbuf); + } + + db = alloc_entry(priv); + if (db == NULL) + { + DEBUG_ERR("alloc_entry() failed for a4_sta_db_entry!\n"); + return; + } + memcpy(db->mac, mac, ETH_ALEN); + db->stat = pstat; + db->ageing_timer = jiffies; + +#ifdef A4_STA_DEBUG + panic_printk("%s A4 STA Add emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", + priv->dev->name, + db->mac[0], + db->mac[1], + db->mac[2], + db->mac[3], + db->mac[4], + db->mac[5], + db->stat->hwaddr[0], + db->stat->hwaddr[1], + db->stat->hwaddr[2], + db->stat->hwaddr[3], + db->stat->hwaddr[4], + db->stat->hwaddr[5]); +#endif + + mac_hash_link(priv, db, hash); + + a4_sta_update(GET_ROOT(priv), priv, mac); + +} + +struct stat_info *a4_sta_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct a4_sta_db_entry *db; + + ASSERT(mac); + + db = priv->machash[mac_hash(mac)]; + + while (db != NULL) + { + if (!memcmp(db->mac, mac, ETH_ALEN)) + { + +#ifdef A4_STA_DEBUG + panic_printk("%s A4 STA LOOKUP emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n", + priv->dev->name, + db->mac[0], + db->mac[1], + db->mac[2], + db->mac[3], + db->mac[4], + db->mac[5], + db->stat->hwaddr[0], + db->stat->hwaddr[1], + db->stat->hwaddr[2], + db->stat->hwaddr[3], + db->stat->hwaddr[4], + db->stat->hwaddr[5]); +#endif + return db->stat; + } + + db = db->next_hash; + } + return NULL; +} + +void add_a4_client(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + struct list_head *phead, *plist; + struct stat_info *sta; + + if (!netif_running(priv->dev)) + return; + + phead = &priv->a4_sta_list; + plist = phead->next; + + while (plist != phead) + { + sta = list_entry(plist, struct stat_info, a4_sta_list); + if (!memcmp(sta->hwaddr, pstat->hwaddr, WLAN_ADDR_LEN)) + { + ASSERT(pstat == sta); + break; + } + plist = plist->next; + } + + if (plist == phead) + list_add_tail(&pstat->a4_sta_list, &priv->a4_sta_list); + + pstat->state |= WIFI_A4_STA; +} + +unsigned char parse_a4_ie(struct rtl8192cd_priv *priv, unsigned char* p, int limit) +{ + + unsigned char * pframe = p; + int len = 0; + for (;;) + { + p = get_ie(p, _RSN_IE_1_, &len, + limit - (p - pframe)); + if (p != NULL) + { + if (!memcmp(p+2, a4_oui, 3)) + { + if(p[5] == 0x03 && (p[8] & BIT6)) /*check ECM 2.0*/ + { + return 1; + } + } + } + else + break; + + p = p + len + 2; + } + + return 0; +} + +void a4_tx_unknown_unicast(struct rtl8192cd_priv *priv, struct sk_buff *skb) +{ + struct list_head *phead, *plist; + struct stat_info *pstat, *sa_stat; + struct sk_buff *newskb; + + + sa_stat = get_stainfo(priv, skb->data+MACADDRLEN); + if(sa_stat == NULL) + { + sa_stat = a4_sta_lookup(priv, skb->data+MACADDRLEN); + } + + phead = &priv->a4_sta_list; + plist = phead->next; + while (phead && (plist != phead)) + { + pstat = list_entry(plist, struct stat_info, a4_sta_list); + plist = plist->next; + if(pstat != sa_stat) + { + newskb = skb_copy(skb, GFP_ATOMIC); + if (newskb) + { + newskb->cb[2] = (char)0xff; // not do aggregation + #if defined(CONFIG_RTK_MESH) + __rtl8192cd_start_xmit_out(newskb, pstat, NULL); + #else + __rtl8192cd_start_xmit_out(newskb, pstat); + #endif + } + else + { + return; + } + } + } + +} + +unsigned char a4_tx_mcast_to_unicast(struct rtl8192cd_priv *priv, struct sk_buff *skb) +{ + struct list_head *phead, *plist; + struct stat_info *pstat, *sa_stat; + struct sk_buff *newskb; + + int sta_count = 0; + + sa_stat = get_stainfo(priv, skb->data+MACADDRLEN); + if(sa_stat == NULL) + { + sa_stat = a4_sta_lookup(priv, skb->data+MACADDRLEN); + } + + phead = &priv->asoc_list; + plist = phead->next; + while (phead && (plist != phead)) + { + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + + if(pstat != sa_stat) + { + if(pstat->state & WIFI_A4_STA) + { + newskb = skb_copy(skb, GFP_ATOMIC); + if (newskb) + { + newskb->cb[2] = (char)0xff; // not do aggregation + + #if defined(CONFIG_RTK_MESH) + __rtl8192cd_start_xmit_out(newskb, pstat, NULL); + #else + __rtl8192cd_start_xmit_out(newskb, pstat); + #endif + } + else + { + continue; + } + } + else + { + sta_count++; + } + } + } + + if(sta_count == 0) + { + return 1; + } + return 0; +} + +int a4_rx_dispatch(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo +#ifdef MBSSID + ,int vap_idx +#endif + ) +{ + + unsigned int opmode; + unsigned char *pframe = get_pframe(pfrinfo); + int reuse = 1; + +#ifdef MBSSID + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable && (vap_idx >= 0)) + { + priv = priv->pvap_priv[vap_idx]; + } +#endif + + opmode = OPMODE; + +#ifdef CLIENT_MODE + if((opmode & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == + (WIFI_STATION_STATE | WIFI_ASOC_STATE)) + { + if (IS_BSSID(priv, GetAddr2Ptr(pframe))) + { + reuse = a4_rx_check_reuse(priv, pfrinfo, GET_MY_HWADDR); + } + } + else +#endif + if (opmode & WIFI_AP_STATE) + { +#ifdef UNIVERSAL_REPEATER + if(IS_DRV_OPEN(GET_VXD_PRIV(priv)) && IS_BSSID(GET_VXD_PRIV(priv), GetAddr2Ptr(pframe))) + { + reuse = a4_rx_check_reuse(GET_VXD_PRIV(priv), pfrinfo, GET_MY_HWADDR); + if (reuse == 0) + { + priv = GET_VXD_PRIV(priv); + } + } + else +#endif + if (IS_BSSID(priv, GetAddr1Ptr(pframe))) + { + reuse = 0; + } + + } + + if(reuse == 0) + { +#ifdef RTL8190_DIRECT_RX + rtl8192cd_rx_dataframe(priv, NULL, pfrinfo); +#else + SMP_LOCK_RX_DATA(x); + list_add_tail(&(pfrinfo->rx_list), &(priv->rx_datalist)); + SMP_UNLOCK_RX_DATA(x); +#endif + + } + + rx_sum_up(priv, NULL, pfrinfo); + + return reuse; +} + + +struct stat_info *a4_rx_check_reuse_ap(struct rtl8192cd_priv *priv, struct stat_info *pstat, struct rx_frinfo *pfrinfo) +{ + if(priv->pshare->rf_ft_var.a4_enable == 2) { + /*only recieve 4 address packet from A4 client when a4_enable = 2*/ + if(((pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds != 3) || + (!(pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds == 3) + ) { + return NULL; + } + } + else { + if(!(pstat->state & WIFI_A4_STA) && pfrinfo->to_fr_ds == 3) + add_a4_client(priv, pstat); + } + + if(pfrinfo->to_fr_ds == 3 && (pstat->state & WIFI_A4_STA)) + { + a4_sta_add(priv, pstat, pfrinfo->sa); + } + + return pstat; +} + + +#ifdef CLIENT_MODE +unsigned char a4_rx_check_reuse(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo, unsigned char * myhwaddr) +{ + struct stat_info * pstat; + unsigned char reuse = 1; + unsigned char *pframe = get_pframe(pfrinfo); + struct net_bridge_fdb_entry *fdb; + + pstat = get_stainfo(priv, GetAddr2Ptr(pframe)); //bssid + if(pstat) + { + if(pstat->state & WIFI_A4_STA) /*A4 AP*/ + { + /* when a4_enable = 1, also recieve 3-address from an A4 AP*/ + if(pfrinfo->to_fr_ds == 1 && priv->pshare->rf_ft_var.a4_enable == 1) { + + if(IS_MCAST(pfrinfo->da)) { + /*filter*/ + reuse = 0; + fdb = fdb_find_for_driver(GET_BR_PORT(priv->dev)->br, pfrinfo->sa); + if(fdb) { + /*if sa is recorded in other interface, it may be a loop packet, drop it*/ + if(strcmp(fdb->dst->dev->name, priv->dev->name)) + reuse = 1; + } + } + else if(isEqualMACAddr(pfrinfo->da, myhwaddr)){ /*unicast*/ + reuse = 0; + } + + } + /*other case, only recieve 4 address packet*/ + else if(pfrinfo->to_fr_ds == 3 && isEqualMACAddr(GetAddr1Ptr(pframe), myhwaddr)) + { + a4_sta_add(priv, pstat, pfrinfo->sa); + if(!IS_MCAST(pfrinfo->da)) + a4_sta_del(priv, pfrinfo->da); + reuse = 0; + } + } + else /*legacy AP*/ + { + /*only recieve 3 address packet*/ + if (pfrinfo->to_fr_ds == 1 && (IS_MCAST(pfrinfo->da) || isEqualMACAddr(pfrinfo->da, myhwaddr))) + { + reuse = 0; + } + } + } + + return reuse; +} +#endif + +#ifndef __OSK__ +#ifdef CONFIG_RTL_PROC_NEW +int a4_dump_sta_info(struct seq_file *s, void *data) +#else +int a4_dump_sta_info(char *buf, char **start, off_t offset, + int length, int *eof, void *data) +#endif +{ + struct net_device *dev = PROC_GET_DEV(); + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct a4_sta_db_entry *db; + int i; + int pos = 0; + PRINT_ONE(" -- A4 STA info -- ", "%s", 1); + + for (i = 0 ; i < A4_STA_HASH_SIZE; i++) + { + db = priv->machash[i]; + while (db != NULL) + { + PRINT_ARRAY_ARG(" STA_MAC: ", db->mac, "%02x", MACADDRLEN); + PRINT_ARRAY_ARG(" OWNER_MAC: ", db->stat->hwaddr, "%02x", MACADDRLEN); + PRINT_ONE((jiffies - db->ageing_timer)/HZ, " Aging time: %ld", 1); + db = db->next_hash; + } + } + + + + return pos; +} +#endif + +#endif /* A4_STA */ + + +#if defined(TV_MODE) || defined(A4_STA) +unsigned char * construct_ecm_tvm_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen, unsigned char mode) +{ + unsigned char temp[7]; + memcpy(temp, a4_oui, 3); + *(unsigned short *)(temp + 4) = cpu_to_le16(A4_VERSION); + temp[6] = 0; + + if(mode & BIT0) /*ECM*/ + { +#ifdef ENABLE_ECM_1_0 + temp[3] = 0x02; /*OUI type */ + temp[6] = BIT7; /*ECM 1.0*/ + pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); +#endif + temp[6] = BIT6; /*ECM 2.0*/ + } + +#ifdef TV_MODE + if(mode & BIT1) /* TV mode*/ + { + if(priv->tv_mode_status & BIT0) /*tv mode is enabled*/ + { + temp[6] |= BIT7; + } + } +#endif + + temp[3] = 0x03; /*OUI type */ + pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); + return pbuf; +} +#endif + +#ifdef TV_MODE +unsigned char * construct_tv_mode_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) +{ + unsigned char temp[7]; + memcpy(temp, a4_oui, 3); + *(unsigned short *)(temp + 4) = cpu_to_le16(A4_VERSION); + + temp[3] = 0x04; /*OUI type */ + temp[6] = BIT7; /*TV Auto*/ + pbuf = set_ie(pbuf, _RSN_IE_1_, 7, temp, frlen); + return pbuf; +} + +unsigned char parse_tv_mode_ie(struct rtl8192cd_priv *priv, unsigned char* p, int limit) +{ + + unsigned char * pframe = p; + int len = 0; + for (;;) + { + p = get_ie(p, _RSN_IE_1_, &len, + limit - (p - pframe)); + if (p != NULL) + { + if (!memcmp(p+2, a4_oui, 3)) + { + if(p[5] == 0x04 && (p[8] & BIT7)) /*check TV Auto*/ + { + return 1; + } + } + } + else + break; + + p = p + len + 2; + } + + return 0; +} + +void tv_mode_auto_support_check(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + //unsigned long flags; + + phead = &priv->asoc_list; + plist = phead->next; + + priv->tv_mode_status &= ~BIT0; + while(plist != phead) + { + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + + if(pstat->tv_auto_support && pstat->expire_to > 0) + { + priv->tv_mode_status|= BIT0; + break; + } + } +} + +#ifdef SUPPORT_TX_MCAST2UNI +/*return: 0: no client joint, 1: has client joint*/ +unsigned char tv_mode_igmp_group_check(struct rtl8192cd_priv *priv, struct sk_buff *skb) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + int i; + + phead = &priv->asoc_list; + plist = phead; + while ((plist = asoc_list_get_next(priv, plist)) != phead) + { + pstat = list_entry(plist, struct stat_info, asoc_list); + /* avoid come from STA1 and send back STA1 */ + if (!memcmp(pstat->hwaddr, &skb->data[6], 6)) + { + continue; + } + if(pstat->leave || pstat->expire_to==0) + continue; + for (i=0; iipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[0], skb->data, 6)) + { + return 1; + } + } + } + return 0; + +} +#endif +#endif diff --git a/package/kernel/rtl8192cd/8192cd_comapi.c b/package/kernel/rtl8192cd/8192cd_comapi.c old mode 100755 new mode 100644 index 55481d1fce8..19ed1c27b0d --- a/package/kernel/rtl8192cd/8192cd_comapi.c +++ b/package/kernel/rtl8192cd/8192cd_comapi.c @@ -1,3676 +1,3676 @@ -/* - * API-compatible handling routines - * - * - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define _8192CD_COMAPI_C_ - - -#ifdef __KERNEL__ -#include -#include -#include -#include -#include -#include -#include -#endif - -#ifdef __LINUX_2_6__ -#include -#include -#endif - -#include "./8192cd_debug.h" -#include "./8192cd_comapi.h" -#include "./8192cd_headers.h" - #ifdef SUPPORT_MONITOR -#include "./8192cd_util.h" -#endif -#ifdef CONFIG_RTL_COMAPI_WLTOOLS -#include -#include - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -#define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_A, _B, _C, _D, _E) -#define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_A, _B, _C, _D, _E) -#define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_A, _B, _C, _D, _E, _F) -#else -#define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_B, _C, _D, _E) -#define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_B, _C, _D, _E) -#define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_B, _C, _D, _E, _F) -#endif - -typedef struct _CH_FREQ_MAP_{ - UINT16 channel; - UINT16 freqKHz; -}CH_FREQ_MAP; - -CH_FREQ_MAP CH_HZ_ID_MAP[] = -{ - {1, 2412}, - {2, 2417}, - {3, 2422}, - {4, 2427}, - {5, 2432}, - {6, 2437}, - {7, 2442}, - {8, 2447}, - {9, 2452}, - {10, 2457}, - {11, 2462}, - {12, 2467}, - {13, 2472}, - {14, 2484}, - - /* UNII */ - {36, 5180}, - {40, 5200}, - {44, 5220}, - {48, 5240}, - {52, 5260}, - {56, 5280}, - {60, 5300}, - {64, 5320}, - {149, 5745}, - {153, 5765}, - {157, 5785}, - {161, 5805}, - {165, 5825}, - {167, 5835}, - {169, 5845}, - {171, 5855}, - {173, 5865}, - - /* HiperLAN2 */ - {100, 5500}, - {104, 5520}, - {108, 5540}, - {112, 5560}, - {116, 5580}, - {120, 5600}, - {124, 5620}, - {128, 5640}, - {132, 5660}, - {136, 5680}, - {140, 5700}, - - /* Japan MMAC */ - {34, 5170}, - {38, 5190}, - {42, 5210}, - {46, 5230}, - - /* Japan */ - {184, 4920}, - {188, 4940}, - {192, 4960}, - {196, 4980}, - - {208, 5040}, /* Japan, means J08 */ - {212, 5060}, /* Japan, means J12 */ - {216, 5080}, /* Japan, means J16 */ -}; - -int CH_HZ_ID_MAP_NUM = (sizeof(CH_HZ_ID_MAP)/sizeof(CH_FREQ_MAP)); - - -#define MAP_CHANNEL_ID_TO_KHZ(_ch, _khz) \ - do{ \ - int _chIdx; \ - for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++)\ - { \ - if ((_ch) == CH_HZ_ID_MAP[_chIdx].channel) \ - { \ - (_khz) = CH_HZ_ID_MAP[_chIdx].freqKHz * 1000; \ - break; \ - } \ - } \ - if (_chIdx == CH_HZ_ID_MAP_NUM) \ - (_khz) = 2412000; \ - }while(0) - -#define MAP_KHZ_TO_CHANNEL_ID(_khz, _ch) \ - do{ \ - int _chIdx; \ - for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++)\ - { \ - if ((_khz) == CH_HZ_ID_MAP[_chIdx].freqKHz) \ - { \ - (_ch) = CH_HZ_ID_MAP[_chIdx].channel; \ - break; \ - } \ - } \ - if (_chIdx == CH_HZ_ID_MAP_NUM) \ - (_ch) = 1; \ - }while(0) - -/* -struct iw_statistics *rtl8192cd_get_wireless_stats(struct net_device *net_dev) -{ - // client mode only - return NULL; -} -*/ - -#ifdef WIFI_WPAS_CLI -extern void clean_for_join(struct rtl8192cd_priv *priv); - -void use_ap_scan( RTL_PRIV *priv ) -{ - RTL_PRIV *r_priv; - - priv->pshare->bScanInProcess = FALSE; - - if ( IS_ROOT_INTERFACE(priv) ) { - printk("cliW: ss_req\n"); - priv->ss_req_ongoing = 1; - start_clnt_ss(priv); - } else { - printk("cliW: vxd req\n"); - r_priv = GET_ROOT(priv); - r_priv->ss_ssidlen = 0; - r_priv->ss_req_ongoing = SSFROM_WPAS; - start_clnt_ss(r_priv); - } -} - -#if 0 -void switch_chan(struct rtl8192cd_priv *priv, struct bss_desc *bss_desp) -{ - struct rtl8192cd_priv *root_priv; - u8 is_40m, channel, ch_offset; - int bw; - unsigned long flags; - - printk("vxd chan follows\n"); - - //RTL_W8(TXPAUSE, 0xff); - - channel = bss_desp->channel; - priv->pmib->dot11RFEntry.dot11channel = channel; - - if ((bss_desp->t_stamp[1] & (BIT(1) | BIT(2))) == (BIT(1) | BIT(2))) - ch_offset = HT_2NDCH_OFFSET_BELOW; - else if ((bss_desp->t_stamp[1] & (BIT(1)|BIT(2))) == BIT(1)) - ch_offset = HT_2NDCH_OFFSET_ABOVE; - else - ch_offset = HT_2NDCH_OFFSET_DONTCARE; - - if ( ch_offset != 0 ) - is_40m = 1; - - if ( IS_VXD_INTERFACE(priv) ) { - root_priv = GET_ROOT(priv); - bw = (root_priv->pmib->dot11nConfigEntry.dot11nUse40M && is_40m); - if (0 == bw) - ch_offset = HT_2NDCH_OFFSET_DONTCARE; - - priv->pshare->is_40m_bw = bw; - priv->pshare->CurrentChannelBW = bw; - priv->pshare->offset_2nd_chan = ch_offset; - - priv->pmib->dot11RFEntry.dot11channel = channel; - priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; - priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; - - root_priv->pmib->dot11RFEntry.dot11channel = channel; - root_priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; - root_priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; - root_priv->ht_cap_len = 0; // re-construct HT IE - init_beacon(root_priv); -#ifdef MBSSID - if (root_priv->pmib->miscEntry.vap_enable) { - struct rtl8192cd_priv *vap_priv; - int i; - - for (i = 0; i < RTL8192CD_NUM_VWLAN; i++) { - vap_priv = root_priv->pvap_priv[i]; - if (IS_DRV_OPEN(vap_priv)) { - vap_priv->pmib->dot11RFEntry.dot11channel = channel; - vap_priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; - vap_priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; - vap_priv->ht_cap_len = 0; // re-construct HT IE - init_beacon(vap_priv); - } - } - } -#endif // MBSSID - } else { - root_priv = priv; - - priv->pshare->is_40m_bw = is_40m; - priv->pshare->CurrentChannelBW = is_40m; - priv->pshare->offset_2nd_chan = ch_offset; - - priv->pmib->dot11RFEntry.dot11channel = channel; - priv->pmib->dot11nConfigEntry.dot11nUse40M = is_40m; - priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; -#ifdef UNIVERSAL_REPEATER - // TO DO ... -#endif - } - - SwBWMode(root_priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan); - SwChnl(root_priv, channel, priv->pshare->offset_2nd_chan); - - // RTL_W8(TXPAUSE, 0x00); - - // update_beacon -} -#endif - -int rtl_wx_dummy(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - return -1; -} - - -int rtl_wx_join(struct rtl8192cd_priv *priv, struct bss_desc *bss_desp) -{ - char tmpbuf[33]; - - printk("cliW: join opmode: %x res:%x \n", OPMODE, priv->join_res); - if (!netif_running(priv->dev)) - { - printk("WiFi driver is NOT open!!\n"); - return 1; - } - else if (priv->ss_req_ongoing) - { - printk("Site Survey is not finished yet!!\n"); - return 2; - } - - //if ( priv->join_res == STATE_Sta_No_Bss ) - // goto cnti_join; - - // memcpy((void *)&(priv->pmib->dot11Bss) , - // (void *)&priv->site_survey->bss_backup[bss_num] , sizeof(struct bss_desc)); - - memcpy(&(priv->pmib->dot11Bss), bss_desp, sizeof(struct bss_desc)); - -#if 0 - if ( priv->join_req_ongoing ) { - printk("cliW: no join under connecinting \n"); - return 0; - } -#endif - - if( ( priv->pmib->dot11Bss.ssidlen < 0) || (priv->pmib->dot11Bss.ssidlen > 32) ) { - printk("cliW: wrong ssid len\n"); - return 3; - } -#if 0 - if (priv->ss_req_ongoing || priv->join_req_ongoing ) { - printk("cliW: no join under scanning \n"); - return 0; - } -#endif - - if ( OPMODE & ( WIFI_AUTH_STATE1 | WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE) ) { - printk("cliW: no joining when in auth\n"); - return 4; - } - -#if 0 - if ( OPMODE & WIFI_ASOC_STATE || (priv->join_res == STATE_Sta_Bss) ) { - printk("cliW: no joining when in asso\n"); - return 0; - } -#endif - -#ifdef WIFI_SIMPLE_CONFIG - //_Eric if (priv->pmib->wscEntry.wsc_enable && (priv->pmib->dot11Bss.bsstype&WIFI_WPS)) - if (priv->pmib->wscEntry.wsc_enable) - { - //priv->pmib->dot11Bss.bsstype &= ~WIFI_WPS; - priv->wps_issue_join_req = 1; - } - else -#endif - { - if (check_bss_encrypt(priv) == FAIL) - { - printk("Encryption mismatch!\n"); - return 5; - } - } - - if ((priv->pmib->dot11Bss.ssidlen == 0) || (priv->pmib->dot11Bss.ssid[0] == '\0')) - { - printk("Error !! Join to a hidden AP!\n"); - return 6; - } - -#ifdef UNIVERSAL_REPEATER - disable_vxd_ap(GET_VXD_PRIV(priv)); -#endif - - memcpy(tmpbuf, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); - tmpbuf[priv->pmib->dot11Bss.ssidlen] = '\0'; - printk("going to join bss: %s\n", tmpbuf); - - memcpy(SSID2SCAN, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); - SSID2SCAN_LEN = priv->pmib->dot11Bss.ssidlen; - - SSID_LEN = SSID2SCAN_LEN; - memcpy(SSID, SSID2SCAN, SSID_LEN); - memset(BSSID, 0, MACADDRLEN); - -#ifdef INCLUDE_WPA_PSK //_Eric ?? - //if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) - //derivePSK(priv); -#endif - - priv->join_req_ongoing = 1; - priv->authModeRetry = 0; - - // switch_chan() is replaced with clnt_switch_chan_to_bss in start_clnt_auth - //switch_chan(priv, bss_desp); - - printk("cliw: start join... in ch:%d\n", bss_desp->channel); -#if defined(CONFIG_PCI_HCI) - start_clnt_join(priv); -#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - // avoid IQK handling race condition between start_clnt_auth and TXPowerTracking - // so we indicate WPAS_JOIN event to cmd_thread to do start_clnt_join() - notify_wpas_join(priv); -#endif - - return 0; -} - -int rtl_wx_get_name(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct stat_info *pstat; - struct wifi_mib *pmib; - char *p; - - DEBUG_INFO("cmd_code=%x\n", info->cmd); - - DBFENTER; - - pstat = priv->pstat_cache; - if (pstat == NULL) { - DEBUG_INFO("pstat is NULL\n"); - return 0; - } - - pmib = GET_MIB(priv); - - if ((pstat->state & (WIFI_ASOC_STATE | WIFI_AUTH_SUCCESS)) == ((WIFI_ASOC_STATE | WIFI_AUTH_SUCCESS))) - { - p = wrqu->name; - p += sprintf(p, "IEEE 802.11"); - - if (pmib->dot11BssType.net_work_type & WIRELESS_11A) { - p += sprintf(p, "a"); - } - - if (pmib->dot11BssType.net_work_type & WIRELESS_11B) { - p += sprintf(p, "b"); - } - - if (pmib->dot11BssType.net_work_type & WIRELESS_11G) { - p += sprintf(p, "g"); - } - - if (pmib->dot11BssType.net_work_type & WIRELESS_11N) { - p += sprintf(p, "n"); - } - - if (pmib->dot11BssType.net_work_type & WIRELESS_11AC) { - p += sprintf(p, "ac"); - } - } - else - { - //prates = &padapter->registrypriv.dev_network.SupportedRates; - //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); - snprintf(wrqu->name, IFNAMSIZ, "off/any"); - } - - DBFEXIT; - - return 0; -} - -int rtl_wx_set_mode(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - int ret = 0; - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - switch(wrqu->mode) - { - case IW_MODE_AUTO: - if (OPMODE & WIFI_STATION_STATE) { - OPMODE = WIFI_STATION_STATE; - printk("set_mode = IW_MODE_AUTO ==> WIFI_STATION_STATE\n"); - } else { - OPMODE = WIFI_AP_STATE; - printk("set_mode = IW_MODE_AUTO ==> WIFI_AP_STATE\n"); - } - break; - case IW_MODE_ADHOC: - OPMODE = WIFI_ADHOC_STATE; - printk("set_mode = IW_MODE_ADHOC\n"); - break; - case IW_MODE_MASTER: - OPMODE = WIFI_AP_STATE; - printk("set_mode = IW_MODE_MASTER\n"); - break; - case IW_MODE_INFRA: - OPMODE = WIFI_STATION_STATE; - printk("set_mode = IW_MODE_INFRA\n"); - break; - - default : - ret = -EINVAL; - DEBUG_WARN("Mode: %d is not supported\n", wrqu->mode); - break; - } - - // TODO: Active the Operation Mode - return ret; -} - -int rtl_wx_get_sens(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - wrqu->sens.value = 0; - wrqu->sens.fixed = 0; /* no auto select */ - wrqu->sens.disabled = 1; - return 0; -} - -void clean_conn_var(RTL_PRIV *priv) -{ - if (timer_pending(&priv->reauth_timer)) - del_timer_sync (&priv->reauth_timer); - - if (timer_pending(&priv->reassoc_timer)) - del_timer_sync (&priv->reassoc_timer); -#if 0 - priv->reauth_count = 0; - priv->reassoc_count = 0; - priv->auth_seq = 0; - - priv->join_res = STATE_Sta_No_Bss; - priv->reauth_count = 0; - priv->reassoc_count = 0; -#endif - priv->join_req_ongoing = 0; - priv->ss_req_ongoing = 0; - - clean_for_join(priv); -} - -#if WIRELESS_EXT >= 18 -int rtl_wx_set_mlme( - struct net_device *dev, - struct iw_request_info *info, - struct iw_point *erq, - char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_mlme *wextmlme = (struct iw_mlme *)extra; - struct stat_info *pstat; - - switch(wextmlme->cmd) { - case IW_MLME_DEAUTH: - printk("Set MLME: IW_MLME_DEAUTH, Reason=%d\n", wextmlme->reason_code); - - if (OPMODE & (WIFI_AUTH_SUCCESS)) - { - issue_deauth(priv,BSSID,wextmlme->reason_code); - delay_ms(50); //Give some time to wait TX done - OPMODE &= ~(WIFI_AUTH_SUCCESS|WIFI_ASOC_STATE) ; - - pstat = get_stainfo(priv, BSSID); - if (pstat != NULL) - { - if (asoc_list_del(priv, pstat)) - { - if (pstat->expire_to > 0) - { - cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); - check_sta_characteristic(priv, pstat, DECREASE); - } - } - - free_stainfo(priv, pstat); - } - - event_indicate_wpas(priv, NULL, WPAS_DISCON, NULL); - } - clean_conn_var(priv); - break; - - case IW_MLME_DISASSOC: - printk("Set MLME: IW_MLME_DISASSOC, Reason=%d\n", wextmlme->reason_code); - - if((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) - { - pstat = get_stainfo(priv, BSSID); - issue_disassoc(priv, BSSID, wextmlme->reason_code); - - if (pstat != NULL) - { - if (pstat->expire_to > 0) - { - cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); - check_sta_characteristic(priv, pstat, DECREASE); - } - - free_stainfo(priv, pstat); - -/* memset(&priv->pmib->dot11Bss, 0, sizeof(struct bss_desc)); - memset(priv->pmib->dot11StationConfigEntry.dot11Bssid, 0, MACADDRLEN); - memset(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); - priv->pmib->dot11StationConfigEntry.dot11DesiredSSIDLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11DefaultSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); - priv->pmib->dot11StationConfigEntry.dot11DefaultSSIDLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan)); - priv->pmib->dot11StationConfigEntry.dot11SSIDtoScanLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid, 0, 6); - - priv->wpas_manual_assoc = 1; //_Eric ?? when to let driver auto-connect ?? -*/ - priv->join_res = STATE_Sta_No_Bss; -// pstat->state &= (~WIFI_ASOC_STATE); - } - } - OPMODE &= ~(WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE); - event_indicate_wpas(priv, NULL, WPAS_DISCON, NULL); - clean_conn_var(priv); - break; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) - case IW_MLME_AUTH: - case IW_MLME_ASSOC: - break; -#endif - - default: - return -EINVAL; - } - - return 0; -} -#endif - -int rtl_wx_get_freq(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned int ch; - unsigned long khz; - - if (priv == NULL) { - /* if 1st open fail, pAd will be free; - * So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - ch = priv->pmib->dot11RFEntry.dot11channel; - - MAP_CHANNEL_ID_TO_KHZ(ch, khz); - wrqu->freq.m = khz * 100; - wrqu->freq.e = 1; - wrqu->freq.i = ch; - - return 0; -} -#endif // WIFI_WPAS_CLI - -int rtl_siwfreq(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned int chan=0; - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (wrqu->freq.e > 1) - return -EINVAL; - - if((wrqu->freq.e == 0) && (wrqu->freq.m <= 1000)) - chan = wrqu->freq.m; // Setting by channel number - else -#ifdef WIFI_WPAS_CLI - MAP_KHZ_TO_CHANNEL_ID( (wrqu->freq.m /100000) , chan); // Setting by frequency - search the table , like 2.412G, 2.422G, -#else - MAP_KHZ_TO_CHANNEL_ID( (wrqu->freq.m /100) , chan); // Setting by frequency - search the table , like 2.412G, 2.422G, -#endif - - priv->pmib->dot11RFEntry.dot11channel = chan; - -#ifdef WIFI_WPAS_CLI - printk("cliW: wrqu->freq.m: %d chan:%d \n", wrqu->freq.m, chan); -#else -#ifdef WIFI_HAPD - if (!netif_running(priv->dev)) - return 0; - else -#endif - SwChnl(priv, chan, priv->pshare->offset_2nd_chan); -#endif - - return 0; -} - -int rtl_giwfreq(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned int ch; - //unsigned long m = 2412000; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - ch = priv->pmib->dot11RFEntry.dot11channel; -/* - MAP_CHANNEL_ID_TO_KHZ(ch, m); - wrqu->freq.m = m * 100; - wrqu->freq.e = 1; - wrqu->freq.i = 0; -*/ - wrqu->freq.m = ch; - wrqu->freq.e = 0; - wrqu->freq.i = 0; - - return 0; -} - -int rtl_siwmode(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *b) -{ - int ret = 0; - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } -#ifndef SUPPORT_MONITOR -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif -#endif - - switch(wrqu->mode) - { - case IW_MODE_AUTO: // 0 -#ifdef WIFI_WPAS_CLI - if (OPMODE & WIFI_STATION_STATE) { - OPMODE_VAL(OPMODE & WIFI_STATION_STATE); - printk("set_mode = IW_MODE_AUTO ==> WIFI_STATION_STATE\n"); - } else { - OPMODE_VAL(OPMODE & WIFI_AP_STATE); - printk("set_mode = IW_MODE_AUTO ==> WIFI_AP_STATE\n"); - } -#else - OPMODE_VAL(OPMODE & WIFI_AP_STATE); - printk("set_mode = IW_MODE_AUTO\n"); -#endif - break; - case IW_MODE_ADHOC: // 1 - OPMODE_VAL(OPMODE & WIFI_ADHOC_STATE); - printk("set_mode = IW_MODE_ADHOC\n"); - break; - case IW_MODE_MASTER: // 3 - OPMODE_VAL(OPMODE & WIFI_AP_STATE); -#ifdef SUPPORT_MONITOR - stop_monitor_mode(priv); -#endif - printk("set_mode = IW_MODE_MASTER\n"); -// setopmode_cmd(padapter, networkType); - break; - case IW_MODE_INFRA: // 2 - OPMODE_VAL(OPMODE & WIFI_STATION_STATE); - printk("set_mode = IW_MODE_INFRA\n"); - break; -#ifdef SUPPORT_MONITOR - case IW_MODE_MONITOR: - OPMODE_VAL(OPMODE | WIFI_SITE_MONITOR); - start_monitor_mode(priv); - panic_printk("set_mode = IW_MODE_MONITOR\n"); - break; -#endif - default : - ret = -EINVAL; - } - - return ret; - -} - -int rtl_giwmode(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (OPMODE & WIFI_AP_STATE) - wrqu->mode = IW_MODE_MASTER; - else if (OPMODE & WIFI_STATION_STATE) - wrqu->mode = IW_MODE_INFRA; - else if (OPMODE & WIFI_ADHOC_STATE) - wrqu->mode = IW_MODE_ADHOC; -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) - else if (OPMODE & WIFI_SITE_MONITOR) - wrqu->mode = IW_MODE_MONITOR; -#endif - else - wrqu->mode = IW_MODE_AUTO; - - return 0; -} - -#define MAX_FRAG_THRESHOLD 2346 -#define MIN_FRAG_THRESHOLD 256 - -int rtl_giwrange(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - struct iw_range *range = (struct iw_range *)extra; - int i; - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL || range == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - wrqu->data.length = sizeof(*range); - memset(range, 0, sizeof(*range)); - - /* Let's try to keep this struct in the same order as in - * linux/include/wireless.h - */ - - /* TODO: See what values we can set, and remove the ones we can't - * set, or fill them with some default data. - */ - - /* ~5 Mb/s real (802.11b) */ - range->throughput = 5 * 1000 * 1000; - - // TODO: Not used in 802.11b? -// range->min_nwid; /* Minimal NWID we are able to set */ - // TODO: Not used in 802.11b? -// range->max_nwid; /* Maximal NWID we are able to set */ - - /* Old Frequency (backward compat - moved lower ) */ -// range->old_num_channels; -// range->old_num_frequency; -// range->old_freq[6]; /* Filler to keep "version" at the same offset */ - - /* signal level threshold range */ - - - //percent values between 0 and 100. - range->max_qual.qual = 100; - //range->max_qual.level = 100; - //range->max_qual.noise = 100; - range->max_qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; /* Updated only qual b'coz not sure */ - - - range->avg_qual.qual = 60; - /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ - //range->avg_qual.level = 20; - //range->avg_qual.noise = 0; - range->avg_qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; /* Updated only qual b'coz not sure */ - - range->num_bitrates = AP_BSSRATE_LEN; - - for(i=0; ibitrate[i] = (AP_BSSRATE[i]&0x7f)* 500000; - } - - range->min_frag = MIN_FRAG_THRESHOLD; - range->max_frag = MAX_FRAG_THRESHOLD; - - range->pm_capa = 0; - - range->we_version_compiled = WIRELESS_EXT; - range->we_version_source = 12; - -// range->retry_capa; /* What retry options are supported */ -// range->retry_flags; /* How to decode max/min retry limit */ -// range->r_time_flags; /* How to decode max/min retry life */ -// range->min_retry; /* Minimal number of retries */ -// range->max_retry; /* Maximal number of retries */ -// range->min_r_time; /* Minimal retry lifetime */ -// range->max_r_time; /* Maximal retry lifetime */ - - range->encoding_size[0]=5; - range->encoding_size[1]=13; - range->num_encoding_sizes = 2; - range->max_encoding_tokens = 4; - range->num_channels = priv->available_chnl_num; - range->num_frequency = priv->available_chnl_num; - - for (i = 0; i < priv->available_chnl_num && i < IW_MAX_FREQUENCIES; i++) { - u32 m = 0; - range->freq[i].i = i + 1; - //range->freq[val].m = CH_HZ_ID_MAP[i].freqKHz * 100000; - MAP_CHANNEL_ID_TO_KHZ(priv->available_chnl[i], m); - range->freq[i].m = m* 100; - range->freq[i].e = 1; - } - -// Commented by Albert 2009/10/13 -// The following code will proivde the security capability to network manager. -// If the driver doesn't provide this capability to network manager, -// the WPA/WPA2 routers can't be choosen in the network manager. - -/* -#define IW_SCAN_CAPA_NONE 0x00 -#define IW_SCAN_CAPA_ESSID 0x01 -#define IW_SCAN_CAPA_BSSID 0x02 -#define IW_SCAN_CAPA_CHANNEL 0x04 -#define IW_SCAN_CAPA_MODE 0x08 -#define IW_SCAN_CAPA_RATE 0x10 -#define IW_SCAN_CAPA_TYPE 0x20 -#define IW_SCAN_CAPA_TIME 0x40 -*/ - -#if WIRELESS_EXT > 17 - range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| - IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; -#endif - -#ifdef IW_SCAN_CAPA_ESSID - range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID| - IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE; -#endif - return 0; -} - -#ifdef WIFI_WPAS_CLI -int rtl_siwap(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) { - memset(&priv->pmib->dot11OperationEntry.hwaddr, 0, WLAN_ADDR_LEN); - memcpy(&priv->pmib->dot11OperationEntry.hwaddr, wrqu->ap_addr.sa_data, MACADDRLEN); - clean_for_join(priv); - return 0; - } -#if defined (WIFI_WPAS)//_Eric ?? - else if ( (priv->pmib->dot11OperationEntry.opmode & WIFI_STATION_STATE) || - (priv->pmib->dot11OperationEntry.opmode & WIFI_ADHOC_STATE) ) - { - unsigned char null_mac[] = {0,0,0,0,0,0}; - struct bss_desc bss_desp; - - if ( memcmp(wrqu->ap_addr.sa_data, null_mac, MACADDRLEN) ) { - int i, found=0, ret=0; - for(i = 0 ; i < priv->site_survey->count_backup ; i++) - { - if(!memcmp(priv->site_survey->bss_backup[i].bssid , wrqu->ap_addr.sa_data, MACADDRLEN)) - { - memcpy((void *)&bss_desp, - (void *)&priv->site_survey->bss_backup[i], sizeof(struct bss_desc)); - found = 1; - break; - } - } - - if(found == 0) { - printk("BSSID NOT Found !!\n"); - } else { - ret = rtl_wx_join(priv, &bss_desp); - if(ret != 0) - printk("cliW: rtl_wpas_join Failed: err:%d !!\n", ret); - } - } - return 0; - } -#endif - else - return -EOPNOTSUPP; -} - -#else // !WIFI_WPAS_CLI -int rtl_siwap(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) { - memset(&priv->pmib->dot11OperationEntry.hwaddr, 0, WLAN_ADDR_LEN); - memcpy(&priv->pmib->dot11OperationEntry.hwaddr, wrqu->ap_addr.sa_data, MACADDRLEN); - return 0; - } else { -#ifdef WIFI_WPAS //_Eric ?? - if ( (priv->pmib->dot11OperationEntry.opmode & WIFI_STATION_STATE) || - (priv->pmib->dot11OperationEntry.opmode & WIFI_ADHOC_STATE) ) - { - memset(&priv->pmib->dot11Bss.bssid, 0, WLAN_ADDR_LEN); - memcpy(&priv->pmib->dot11Bss.bssid, wrqu->ap_addr.sa_data, MACADDRLEN); - return 0; - } - else - return -EOPNOTSUPP; -#else - //memset(&priv->pmib->dot11Bss.bssid, 0, WLAN_ADDR_LEN); - //memcpy(&priv->pmib->dot11Bss.bssid, ap_addr->sa_data, MACADDRLEN); - return -EOPNOTSUPP; -#endif - } - -} -#endif // WIFI_WPAS_CLI - -int rtl_giwap(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - wrqu->ap_addr.sa_family = ARPHRD_ETHER; - if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) - memcpy(wrqu->ap_addr.sa_data, priv->pmib->dot11OperationEntry.hwaddr, MACADDRLEN); - else - memcpy(wrqu->ap_addr.sa_data, priv->pmib->dot11Bss.bssid, MACADDRLEN); - - return 0; -} - -int rtl_iwaplist(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *data, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - struct sockaddr addr[IW_MAX_AP]; - struct iw_quality qual[IW_MAX_AP]; - int i; - struct list_head *phead, *plist; - struct stat_info *pstat; -#ifdef SMP_SYNC - unsigned long flags = 0; -#endif - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - i = 0; - phead = &priv->asoc_list; - - SMP_LOCK_ASOC_LIST(flags); - - plist = phead->next; - while (plist != phead && i < IW_MAX_AP) { - pstat = list_entry(plist, struct stat_info, asoc_list); - addr[i].sa_family = ARPHRD_ETHER; - memcpy(addr[i].sa_data, &pstat->hwaddr, WLAN_ADDR_LEN); - - qual[i].qual = pstat->rssi; - //qual[i].level = pstat->sq; - //qual[i].noise = 0 - qual[i].updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; - - plist = plist->next; - i++; - } - - SMP_UNLOCK_ASOC_LIST(flags); - - data->length = i; - memcpy(extra, &addr, i*sizeof(addr[0])); - data->flags = 1; /* signal quality present (sort of) */ - memcpy(extra + i*sizeof(addr[0]), &qual, i*sizeof(qual[i])); - - return 0; -} - -int rtl_siwessid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *essid) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - char str[100]; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) - return -ENETDOWN; -#endif - -#ifdef WIFI_WPAS_CLI - if (!memcmp(priv->pmib->dot11Bss.bssid, NULL_MAC_ADDR, MACADDRLEN)) - return 0; -#endif - - snprintf(str, sizeof(str), "ssid=%s", essid); - return set_mib(priv, str); -} - -int rtl_giwessid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *essid) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - wrqu->essid.flags = 1; - wrqu->essid.length = SSID_LEN; - memcpy(essid, SSID, SSID_LEN); - - return 0; -} - -int rtl_siwrate(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - UINT32 rate = wrqu->bitrate.value, fixed = wrqu->bitrate.fixed; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - //printk("rtl_siwrate::(rate = %d, fixed = %d)\n", rate, fixed); - /* rate = -1 => auto rate - rate = X, fixed = 1 => (fixed rate X) - */ - - if (rate == -1) - { - //Auto Rate - priv->pmib->dot11StationConfigEntry.autoRate = TRUE; - priv->pmib->dot11StationConfigEntry.fixedTxRate = 0; - } - else - { - if (fixed) - { - unsigned int txRate = rate / 10000000; - int i, len; - unsigned char *rateset, *p; - rateset = AP_BSSRATE; - len = AP_BSSRATE_LEN; - - for(i=0,p=rateset; ipmib->dot11StationConfigEntry.autoRate = FALSE; - priv->pmib->dot11StationConfigEntry.fixedTxRate = *p; - return 0; - } - } - return -EOPNOTSUPP; - - } - else - { - // TODO: rate = X, fixed = 0 => (rates <= X) - return -EOPNOTSUPP; - } - } - - return 0; -} - -int rtl_giwrate(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned int txRate; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (priv->pmib->dot11StationConfigEntry.autoRate) - txRate = find_rate(priv, NULL, 1, 0); - else - txRate = get_rate_from_bit_value(priv->pmib->dot11StationConfigEntry.fixedTxRate); - - //printk ("txRate = %d\n", txRate); - wrqu->bitrate.value = txRate * 1000000; - wrqu->bitrate.disabled = 0; - - return 0; -} - -#define MAX_RTS_THRESHOLD 2347 - -int rtl_siwrts(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - u16 val; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (wrqu->rts.disabled) - val = MAX_RTS_THRESHOLD; - else if (wrqu->rts.value < 0 || wrqu->rts.value > MAX_RTS_THRESHOLD) - return -EINVAL; - else if (wrqu->rts.value == 0) - val = MAX_RTS_THRESHOLD; - else - val = wrqu->rts.value; - - if (val != RTSTHRSLD) - RTSTHRSLD = val; - - return 0; -} - -int rtl_giwrts(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - wrqu->rts.value = RTSTHRSLD; - wrqu->rts.disabled = (wrqu->rts.value == MAX_RTS_THRESHOLD); - wrqu->rts.fixed = 1; - - return 0; -} - -int rtl_siwfrag(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - u16 val; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if (wrqu->frag.disabled) - val = MAX_FRAG_THRESHOLD; - else if (wrqu->frag.value >= MIN_FRAG_THRESHOLD || wrqu->frag.value <= MAX_FRAG_THRESHOLD) - val = __cpu_to_le16(wrqu->frag.value & ~0x1); /* even numbers only */ - else if (wrqu->frag.value == 0) - val = MAX_FRAG_THRESHOLD; - else - return -EINVAL; - - FRAGTHRSLD = val; - - return 0; -} - -int rtl_giwfrag(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - - wrqu->frag.value = FRAGTHRSLD; - wrqu->frag.disabled = (wrqu->frag.value == MAX_FRAG_THRESHOLD); - wrqu->frag.fixed = 1; - - return 0; -} - - -int rtl_siwretry(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - priv->pmib->dot11OperationEntry.dot11ShortRetryLimit = wrqu->retry.value; - - return 0; -} - - -int rtl_giwretry(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - wrqu->retry.value = priv->pmib->dot11OperationEntry.dot11ShortRetryLimit; - wrqu->retry.fixed = 0; /* no auto select */ - wrqu->retry.flags |= (IW_RETRY_LIMIT |IW_RETRY_ON); - wrqu->retry.disabled = 0; - - return 0; -} - -int rtl_siwencode(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *keybuf) -{ - u32 key, ret = 0; - u32 keyindex_provided; - int i; -// NDIS_802_11_WEP wep; -// NDIS_802_11_AUTHENTICATION_MODE authmode; - - struct iw_point *erq = &(wrqu->encoding); - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - printk("rtl_siwencode: erq->flags=0x%x erq->length=%d keybuf=%02x%02x%02x%02x%02x\n", erq->flags, erq->length, - keybuf[0],keybuf[1],keybuf[2],keybuf[3],keybuf[4]); - - if (erq->flags & IW_ENCODE_DISABLED) - { - printk("rtl_siwencode: EncryptionDisabled\n"); - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - goto exit; - } - - key = erq->flags & IW_ENCODE_INDEX; - - if (key) { - if (key > 4) - return -EINVAL; - key--; - keyindex_provided = 1; - } - else - { - keyindex_provided = 0; - key = priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex; - printk("rtl_siwencode, key=%d\n", key); - } - - //set authentication mode - if (erq->flags & IW_ENCODE_OPEN) - { - printk("rtl_siwencode: IW_ENCODE_OPEN\n"); - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - } - else if (erq->flags & IW_ENCODE_RESTRICTED) - { - printk("rtl_siwencode: IW_ENCODE_RESTRICTED\n"); - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 1; //shared system - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - } - else - { - printk("rtl_siwencode: IW_ENCODE_OPEN\n"); - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - } - - priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex = key; - - if (erq->length > 0) { - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = erq->length <= 5 ? _WEP_40_PRIVACY_ : _WEP_104_PRIVACY_; - priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = erq->length <= 5 ? 8 : 16; - } else { - - if (keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0). - { - printk("rtl_siwencode: keyindex provided, keyid=%d, key_len=%d\n", key, erq->length); - - switch (priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen) - { - case 5: - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; - break; - case 13: - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; - break; - default: - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - break; - } - - goto exit; - } - } - -#ifdef WIFI_WPAS_CLI - memcpy(priv->pmib->dot11DefaultKeysTable.keytype[key].skey, keybuf, erq->length); - CamAddOneEntry(priv, priv->pmib->dot11Bss.bssid, key, - (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm)<<2, - 0, priv->pmib->dot11DefaultKeysTable.keytype[key].skey); -#else - for (i=0; i<4; i++) { - memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[i].skey[0], keybuf, erq->length); - } -#endif - -exit: - - return ret; -} - - -int rtl_giwencode(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *key) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_point *erq = &(wrqu->encoding); - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - -#ifndef WIFI_HAPD - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } -#endif - - if ((OPMODE & (WIFI_AP_STATE|WIFI_STATION_STATE|WIFI_ADHOC_STATE)) && - !priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm && - (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_ || - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_)) { - int key_len; - priv->pmib->dot11GroupKeysTable.dot11Privacy = priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm; - if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) - key_len = 5; - else - key_len = 13; - - // copy wep key - erq->flags = (priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex + 1) & IW_ENCODE_INDEX; - erq->length = key_len; - memcpy(key, &priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0], key_len); - - if (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm == 1) - erq->flags |= IW_ENCODE_RESTRICTED; /* XXX */ - else - erq->flags |= IW_ENCODE_OPEN; /* XXX */ - - erq->flags |= IW_ENCODE_ENABLED; /* XXX */ - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _NO_PRIVACY_) { - erq->length = 0; - erq->flags = IW_ENCODE_DISABLED; - } - - return 0; -} - -int rtl_giwpower(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - //_adapter *padapter = netdev_priv(dev); - - wrqu->power.value = 0; - wrqu->power.fixed = 0; /* no auto select */ - wrqu->power.disabled = 1; - - return 0; -} - -#ifdef WIFI_WPAS_CLI -int rtl_siwscan(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_point *data = &wrqu->data; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } - -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) - return -ENETDOWN; -#endif - - // TODO: If traffic is busy, we may need to skip this scanning - if ( OPMODE & WIFI_ASOC_STATE ) { - printk("cliW: try scanning in association\n"); - goto ind_done; - } - if ( OPMODE & ( WIFI_AUTH_STATE1 | WIFI_AUTH_SUCCESS) ) { - printk("cliW: no scanning when connecting\n"); - goto ind_done; - } - - if (data && (data->flags & IW_SCAN_THIS_ESSID)) { - struct iw_scan_req* req = (struct iw_scan_req*)extra; - - if (req->essid_len) - { - priv->ss_ssidlen = req->essid_len; - if (priv->ss_ssidlen > 32) - priv->ss_ssidlen = 32; - - memset(priv->ss_ssid, 0, 32); - memcpy(priv->ss_ssid, req->essid, priv->ss_ssidlen); - - SSID2SCAN_LEN = (req->essid_len > 32) ? 32 : req->essid_len; - memcpy(SSID2SCAN, req->essid, SSID2SCAN_LEN); - - use_ap_scan(priv); - } - } else { - printk("cliW: wildcard ssid \n"); - priv->ss_ssidlen = 0; - use_ap_scan(priv); - } -done: - return 0; - -ind_done: - event_indicate_wpas(priv, NULL, WPAS_SCAN_DONE, NULL); - return 0; -} -#else // !WIFI_WPAS_CLI -int rtl_siwscan(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - INT8 ret=-1; - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned long flags; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } - ret=rtl8192cd_ss_req(priv, (unsigned char *) &wrqu->data, 0); - if(0!=wrqu->data.length) - { - if(extra!=NULL && (!strcmp(extra,"rtl8192cd_ioctl")))//called from rtl8192cd_ioctl - { - #ifdef WIFI_WPAS //_Eric ?? - if (ioctl_copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) - memcpy(wrqu->data.pointer, &ret, 1); - #else - if (ioctl_copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) - return -1; - #endif - } - else //called from iwhandler. - { - #ifdef WIFI_WPAS //_Eric ?? - if (copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) - memcpy(wrqu->data.pointer, &ret, 1); - #else - if (copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) - return -1; - #endif - - } - } - - //wait ss done - wait_event_interruptible_timeout(priv->ss_wait,(!priv->ss_req_ongoing),RTL_SECONDS_TO_JIFFIES(5)); - return 0; -} -#endif // WIFI_WPAS_CLI - -#ifdef WIFI_WPAS //_Eric ?? AP mode (HAPD) will attemp to scan or not ?? -int rtl_giwscan(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - int i=0, j=0; - char * current_ev = extra; - char * previous_ev = extra; - char * end_buf; - char * current_val; -#ifndef IWEVGENIE - unsigned char idx; -#endif // IWEVGENIE // - struct iw_event iwe; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - //check if the interface is down - if (!netif_running(priv->dev)) - { - printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } - -#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) { - printk("cliw: driver shutdown now\n"); - return -ENETDOWN; - } -#endif - - if (priv->site_survey->count_backup== 0) - { - wrqu->data.length = 0; - return 0; - } - -#if WIRELESS_EXT >= 17 - if (wrqu->data.length > 0) - end_buf = extra + wrqu->data.length; - else - end_buf = extra + IW_SCAN_MAX_DATA; -#else - end_buf = extra + IW_SCAN_MAX_DATA; -#endif - - for (i = 0; i < priv->site_survey->count_backup; i++) - { - - if( (wrqu->data.length - (current_ev - extra)) <= 200) - break; //_Eric TEST - - if (current_ev >= end_buf) - { -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - - //MAC address - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWAP; - iwe.u.ap_addr.sa_family = ARPHRD_ETHER; - memcpy(iwe.u.ap_addr.sa_data, priv->site_survey->bss_backup[i].bssid, MACADDRLEN); - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - /* - Protocol: - it will show scanned AP's WirelessMode . - it might be - 802.11a - 802.11a/n - 802.11g/n - 802.11b/g/n - 802.11g - 802.11b/g - */ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWNAME; - - { - struct bss_desc *pBss=&priv->site_survey->bss_backup[i]; - //int rateCnt=0; - - if (pBss->network==WIRELESS_11B) - strcpy(iwe.u.name, "802.11b"); - else if (pBss->network==WIRELESS_11G) - strcpy(iwe.u.name, "802.11g"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11B)) - strcpy(iwe.u.name, "802.11b/g"); - else if (pBss->network==(WIRELESS_11N)) - strcpy(iwe.u.name, "802.11n"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11N)) - strcpy(iwe.u.name, "802.11g/n"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11B | WIRELESS_11N)) - strcpy(iwe.u.name, "802.11b/g/n"); - else if(pBss->network== WIRELESS_11A) - strcpy(iwe.u.name, "802.11a"); - else - strcpy(iwe.u.name, "---"); - } - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //ESSID - //================================ - memset(&iwe, 0, sizeof(iwe)); - - //printk("ESSID %s %d\n",priv->site_survey->bss_backup[i].ssid, priv->site_survey->bss_backup[i].ssidlen); - iwe.cmd = SIOCGIWESSID; - iwe.u.data.length = (priv->site_survey->bss_backup[i].ssidlen <= 32) ? priv->site_survey->bss_backup[i].ssidlen : 32; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].ssid); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //Network Type - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWMODE; - if (priv->site_survey->bss_backup[i].bsstype & WIFI_ADHOC_STATE) - { - iwe.u.mode = IW_MODE_ADHOC; - } - else if (priv->site_survey->bss_backup[i].bsstype & WIFI_STATION_STATE) - { - iwe.u.mode = IW_MODE_INFRA; - } - else if (priv->site_survey->bss_backup[i].bsstype & WIFI_AP_STATE) - { - iwe.u.mode = IW_MODE_MASTER; - } - else - { - iwe.u.mode = IW_MODE_AUTO; - } - iwe.len = IW_EV_UINT_LEN; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_UINT_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //Channel and Frequency - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWFREQ; - { - u8 ch = priv->site_survey->bss_backup[i].channel; - u32 m = 0; - - MAP_CHANNEL_ID_TO_KHZ(ch, m); - iwe.u.freq.m = m; - iwe.u.freq.e = 3; - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_FREQ_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - - //Add quality statistics - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVQUAL; - iwe.u.qual.level = priv->site_survey->bss_backup[i].rssi - 100; - iwe.u.qual.qual = priv->site_survey->bss_backup[i].sq; - iwe.u.qual.noise = 0; /* cliW */ - - // not sure about signal level and noise level - //iwe.u.qual.noise = signal_todbm((u8)(100-priv->site_survey->bss[i].rssi)) -25; -// iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; - iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED | IW_QUAL_NOISE_INVALID | IW_QUAL_DBM ; - - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - #define WLAN_CAPABILITY_PRIVACY (1<<4) - - // Encryption capability - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWENCODE; - if (priv->site_survey->bss_backup[i].capability & WLAN_CAPABILITY_PRIVACY) // if Privacy - iwe.u.data.flags =IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - else - iwe.u.data.flags = IW_ENCODE_DISABLED; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf,&iwe, (u8 *)&priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0]); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - // support rate - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWRATE; - iwe.u.bitrate.fixed = 0; - iwe.u.bitrate.disabled = 0; - iwe.u.bitrate.value = 0; - current_val = current_ev + IW_EV_LCP_LEN; - - for (j=0; dot11_rate_table[j]; j++) - { - if (priv->site_survey->bss_backup[i].supportrate & (BIT(j))) - { - iwe.u.bitrate.value = dot11_rate_table[j]*500000; - current_val = IWE_STREAM_ADD_VALUE(info, current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); - } - } - - if (priv->site_survey->bss_backup[i].network & WIRELESS_11N) - { - // TODO: Report MCS Rate - } - - /* remove fixed header if no rates were added */ - if ((current_val - current_ev) > IW_EV_LCP_LEN) - current_ev = current_val; - - - -//WIFI_WPAS ++ -//WPAIE - //================================ -/*cfg p2p cfg p2p*/ - if(priv->site_survey->bss_backup[i].wpa_ie_len > 0){ - memset(&iwe, 0, sizeof(iwe)); - - iwe.cmd = IWEVGENIE; - iwe.u.data.length = priv->site_survey->bss_backup[i].wpa_ie_len; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].wpa_ie); - if (current_ev == previous_ev) { -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - } -/*cfg p2p cfg p2p*/ -//RSNIE - //================================ - if(priv->site_survey->bss_backup[i].rsn_ie_len > 0) { - memset(&iwe, 0, sizeof(iwe)); - - iwe.cmd = IWEVGENIE; - iwe.u.data.length = priv->site_survey->bss_backup[i].rsn_ie_len; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].rsn_ie); - if (current_ev == previous_ev) { -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - } -/*cfg p2p cfg p2p*/ -#ifdef WIFI_SIMPLE_CONFIG - //WPSIE - //================================ - if (priv->site_survey->bss_backup[i].t_stamp[1] & BIT(8)) { - memset(&iwe, 0, sizeof(iwe)); - - iwe.cmd = IWEVGENIE; - iwe.u.data.length = priv->site_survey->wscie[i].wps_ie_len; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->wscie[i].data); - if (current_ev == previous_ev) { -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - } -#endif // WIFI_SIMPLE_CONFIG - -//WIFI_WPAS -- - - } - - wrqu->data.length = current_ev - extra; - - return 0; -} - -#else -int rtl_giwscan(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - int i=0; - char * current_ev = extra; - char * previous_ev = extra; - char * end_buf; - //char * current_val; -#ifndef IWEVGENIE - unsigned char idx; -#endif // IWEVGENIE // - struct iw_event iwe; - - if (priv == NULL) - { - /* if 1st open fail, pAd will be free; - So the net_dev->priv will be NULL in 2rd open */ - return -ENETDOWN; - } - - //check if the interface is down - if (!netif_running(priv->dev)) - { - //printk("\nFail: interface not opened\n"); - return -ENETDOWN; - } - - if (priv->site_survey->count == 0) - { - wrqu->data.length = 0; - return 0; - } - -#if WIRELESS_EXT >= 17 - if (wrqu->data.length > 0) - end_buf = extra + wrqu->data.length; - else - end_buf = extra + IW_SCAN_MAX_DATA; -#else - end_buf = extra + IW_SCAN_MAX_DATA; -#endif - - for (i = 0; i < priv->site_survey->count; i++) - { - if (current_ev >= end_buf) - { -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - - //MAC address - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWAP; - iwe.u.ap_addr.sa_family = ARPHRD_ETHER; - memcpy(iwe.u.ap_addr.sa_data, &priv->site_survey->bss[i].bssid, MACADDRLEN); - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - /* - Protocol: - it will show scanned AP's WirelessMode . - it might be - 802.11a - 802.11a/n - 802.11g/n - 802.11b/g/n - 802.11g - 802.11b/g - */ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWNAME; - - { - struct bss_desc *pBss=&priv->site_survey->bss[i]; - //int rateCnt=0; - - if (pBss->network==WIRELESS_11B) - strcpy(iwe.u.name, "802.11b"); - else if (pBss->network==WIRELESS_11G) - strcpy(iwe.u.name, "802.11g"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11B)) - strcpy(iwe.u.name, "802.11b/g"); - else if (pBss->network==(WIRELESS_11N)) - strcpy(iwe.u.name, "802.11n"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11N)) - strcpy(iwe.u.name, "802.11g/n"); - else if (pBss->network==(WIRELESS_11G|WIRELESS_11B | WIRELESS_11N)) - strcpy(iwe.u.name, "802.11b/g/n"); - else if(pBss->network== WIRELESS_11A) - strcpy(iwe.u.name, "802.11a"); - else - strcpy(iwe.u.name, "---"); - } - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //ESSID - //================================ - memset(&iwe, 0, sizeof(iwe)); - - //printk("ESSID %s %d\n",priv->site_survey->bss[i].ssid, priv->site_survey->bss[i].ssidlen); - iwe.cmd = SIOCGIWESSID; - iwe.u.data.length = priv->site_survey->bss[i].ssidlen; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].ssid); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //Network Type - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWMODE; - if (priv->site_survey->bss[i].bsstype & WIFI_ADHOC_STATE) - { - iwe.u.mode = IW_MODE_ADHOC; - } - else if (priv->site_survey->bss[i].bsstype & WIFI_STATION_STATE) - { - iwe.u.mode = IW_MODE_INFRA; - } - else if (priv->site_survey->bss[i].bsstype & WIFI_AP_STATE) - { - iwe.u.mode = IW_MODE_MASTER; - } - else - { - iwe.u.mode = IW_MODE_AUTO; - } - iwe.len = IW_EV_UINT_LEN; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_UINT_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - - //Channel and Frequency - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWFREQ; - { - u8 ch = priv->site_survey->bss[i].channel; - //u32 m = 0; - //MAP_CHANNEL_ID_TO_KHZ(ch, m); - //iwe.u.freq.m = m * 100; - //iwe.u.freq.e = 1; - iwe.u.freq.m = ch; - iwe.u.freq.e = 0; - iwe.u.freq.i = 0; - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_FREQ_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - - //Add quality statistics - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVQUAL; - iwe.u.qual.qual = priv->site_survey->bss[i].rssi; - - // not sure about signal level and noise level - //iwe.u.qual.level = (u8) priv->site_survey->bss[i].sq; - //iwe.u.qual.noise = signal_todbm((u8)(100-priv->site_survey->bss[i].rssi)) -25; - iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; - - current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif -#if 0 - //Encyption key - //================================ - memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = SIOCGIWENCODE; - if (priv->site_survey->bss[i].capability & 0x0010) - iwe.u.data.flags =IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - else - iwe.u.data.flags = IW_ENCODE_DISABLED; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf,&iwe, (u8 *)priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0]); - if (current_ev == previous_ev) -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif -#endif - //WPAIE - if(priv->site_survey->bss[i].wpa_ie_len > 0){ - memset(&iwe, 0, sizeof(iwe)); - - iwe.cmd = IWEVGENIE; - iwe.u.data.length = priv->site_survey->bss[i].wpa_ie_len; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].wpa_ie); - if (current_ev == previous_ev){ -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - } - //RSNIE - if(priv->site_survey->bss[i].rsn_ie_len > 0){ - memset(&iwe, 0, sizeof(iwe)); - - iwe.cmd = IWEVGENIE; - iwe.u.data.length = priv->site_survey->bss[i].rsn_ie_len; - iwe.u.data.flags = 1; - - previous_ev = current_ev; - current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].rsn_ie); - if (current_ev == previous_ev){ - panic_printk("Add point fail %s %d\n", __FUNCTION__, __LINE__); -#if WIRELESS_EXT >= 17 - return -E2BIG; -#else - break; -#endif - } - } - - } - - wrqu->data.length = current_ev - extra; - return 0; -} -#endif - -#ifdef WIFI_WPAS_CLI -const u1Byte WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; -const u1Byte WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; -const u1Byte WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; -const u1Byte WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; -const u1Byte WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; -const u1Byte WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; - -const u1Byte RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; -const u1Byte RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; -const u1Byte RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; -//const u1Byte RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; -const u1Byte RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; -const u1Byte RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; - -unsigned char rtw_get_wpa_cipher_suite(u1Byte *s) -{ - unsigned char cipher = 0; - - if (memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == 0) - cipher = _NO_PRIVACY_; - else if (memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == 0) - cipher = _WEP_40_PRIVACY_; - else if (memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == 0) - cipher = _TKIP_PRIVACY_; - else if (memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == 0) - cipher = _CCMP_PRIVACY_; - else if (memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == 0) - cipher = _WEP_104_PRIVACY_; - - return cipher; -} - -unsigned char rtw_get_wpa2_cipher_suite(u1Byte *s) -{ - unsigned char cipher = 0; - - if (memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == 0) - cipher = _NO_PRIVACY_; - else if (memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == 0) - cipher = _WEP_40_PRIVACY_; - else if (memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == 0) - cipher = _TKIP_PRIVACY_; - else if (memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == 0) - cipher = _CCMP_PRIVACY_; - else if (memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == 0) - cipher = _WEP_104_PRIVACY_; - - return cipher; -} - -int rtw_parse_wpa_ie(u1Byte* wpa_ie, int wpa_ie_len, unsigned char *group_cipher, unsigned char *pairwise_cipher) -{ - int i, ret=0; - int left, count; - pu1Byte pos; - - if (wpa_ie_len <= 0) { - /* No WPA IE - fail silently */ - return 1; - } - - if ((*wpa_ie != WPA_IE_ID) || (*(wpa_ie+1) != (u1Byte)(wpa_ie_len - 2)) || - (memcmp(wpa_ie+2, WPA_OUI_TYPE, WPA_SELECTOR_LEN) != 0) ) - { - return 1; - } - - pos = wpa_ie; - - pos += 8; - left = wpa_ie_len - 8; - - - //group_cipher - if (left >= WPA_SELECTOR_LEN) - { - *group_cipher = rtw_get_wpa_cipher_suite(pos); - - pos += WPA_SELECTOR_LEN; - left -= WPA_SELECTOR_LEN; - } - else if (left > 0) - { - DEBUG_INFO("%s: ie length mismatch, %u too much", __FUNCTION__, left); - return 1; - } - - - //pairwise_cipher - if (left >= 2) - { - count = le16_to_cpu(*(u2Byte*)pos);// - pos += 2; - left -= 2; - - if (count == 0 || left < count * WPA_SELECTOR_LEN) { - DEBUG_INFO("%s: ie count botch (pairwise), " - "count %u left %u", __FUNCTION__, count, left); - return 1; - } - - for (i = 0; i < count; i++) - { - *pairwise_cipher = rtw_get_wpa_cipher_suite(pos); - - pos += WPA_SELECTOR_LEN; - left -= WPA_SELECTOR_LEN; - } - - } - else if (left == 1) - { - DEBUG_INFO("%s: ie too short (for key mgmt)", __FUNCTION__); - return 1; - } - - - return ret; - -} - -int rtw_parse_wpa2_ie(u1Byte* rsn_ie, int rsn_ie_len, unsigned char *group_cipher, unsigned char *pairwise_cipher) -{ - int i, ret=0; - int left, count; - u1Byte *pos; - - if (rsn_ie_len <= 0) - { - /* No RSN IE - fail silently */ - return 1; - } - - - if ((*rsn_ie!= WPA2_IE_ID) || (*(rsn_ie+1) != (u1Byte)(rsn_ie_len - 2))) - { - return 1; - } - - pos = rsn_ie; - pos += 4; - left = rsn_ie_len - 4; - - //group_cipher - if (left >= RSN_SELECTOR_LEN) { - - *group_cipher = rtw_get_wpa2_cipher_suite(pos); - - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - - } else if (left > 0) { - DEBUG_INFO("%s: ie length mismatch, %u too much", __FUNCTION__, left); - return 1; - } - - //pairwise_cipher - if (left >= 2) - { - count = le16_to_cpu(*(u16*)pos);// - pos += 2; - left -= 2; - - if (count == 0 || left < count * RSN_SELECTOR_LEN) { - DEBUG_INFO("%s: ie count botch (pairwise), " - "count %u left %u", __FUNCTION__, count, left); - return 1; - } - - for (i = 0; i < count; i++) - { - *pairwise_cipher = rtw_get_wpa2_cipher_suite(pos); - - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - } - - } - else if (left == 1) - { - DEBUG_INFO("%s: ie too short (for key mgmt)", __FUNCTION__); - - return 1; - } - - return ret; - -} - -void rtw_set_wpa_cipher_bit(struct rtl8192cd_priv *priv, unsigned char enc_type) -{ - switch (enc_type) { - case _WEP_40_PRIVACY_: - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(0); - break; - - case _TKIP_PRIVACY_: - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(1); - break; - - case _WRAP_PRIVACY_: - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(2); - break; - - case _CCMP_PRIVACY_: - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(3); - break; - - case _WEP_104_PRIVACY_: - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(4); - break; - - default: - break; - } -} - - -int rtl_siwgenie(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - u1Byte *buf=NULL; - unsigned char group_cipher = 0, pairwise_cipher = 0; - int ret = 0; - u2Byte ielen; - WPA_GLOBAL_INFO *pGblInfo = priv->wpa_global_info; - - DEBUG_INFO("%s:IE_Len=%d\n", __FUNCTION__, wrqu->data.length); - - ielen = wrqu->data.length; - if((ielen > MAX_WPA_IE_LEN) || (extra == NULL)){ - priv->pmib->wscEntry.wsc_enable = 0; - priv->pmib->wscEntry.assoc_ielen = 0; - if(extra == NULL) - return ret; - else - return -EINVAL; - } - - printk("rtl_siwgenie\n"); - - if ( ielen == 0 ) { - priv->pmib->dot11RsnIE.rsnielen = 0; - } else { -#if 0 - if (wrqu->data.length < sizeof(DOT11_RSN_IE_HEADER)) - { - DEBUG_ERR("Invalid IE Length(%d) or Null data pointer\n", wrqu->data.length); - return -EINVAL; - } -#endif - buf = kzalloc(ielen, GFP_KERNEL); - if (buf == NULL){ - return -ENOMEM; - } - - memcpy(buf, extra, ielen); - if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher) == 0) - { - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = pairwise_cipher; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= 1 << (pairwise_cipher-1); - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; - priv->pmib->dot11GroupKeysTable.dot11Privacy = group_cipher; - pGblInfo->MulticastCipher = group_cipher ; - pGblInfo->UnicastCipher[0] = pairwise_cipher ; - - BUG_ON(sizeof(priv->pmib->dot11RsnIE.rsnie) < ielen); - memcpy(priv->pmib->dot11RsnIE.rsnie, &buf[0], ielen); - priv->pmib->dot11RsnIE.rsnielen = ielen; - } - else if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher) == 0) - { - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = pairwise_cipher; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA2; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; - priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= 1 << (pairwise_cipher-1); - priv->pmib->dot11GroupKeysTable.dot11Privacy = group_cipher; - pGblInfo->MulticastCipher = group_cipher ; - pGblInfo->UnicastCipherWPA2[0] = pairwise_cipher; - - BUG_ON(sizeof(priv->pmib->dot11RsnIE.rsnie) < ielen); - memcpy(priv->pmib->dot11RsnIE.rsnie, &buf[0], ielen); - priv->pmib->dot11RsnIE.rsnielen = ielen; - } - - {//set wps_ie - int cnt = 0; - unsigned char wps_ie_found=0; - unsigned char eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; - - while( cnt < ielen ) - { - eid = buf[cnt]; - - if((eid==VENDOR_SPECIFIC_IE)&&(memcmp(&buf[cnt+2], wps_oui, 4)==0)) - { - DEBUG_INFO("%s: SET WPS_IE\n",__FUNCTION__); - priv->pmib->wscEntry.wsc_enable = 1; - priv->pmib->wscEntry.assoc_ielen = ( (buf[cnt+1]+2) < (256)) ? (buf[cnt+1]+2):(256); - memset(priv->pmib->wscEntry.assoc_ie, 0x0, 256); - memcpy(priv->pmib->wscEntry.assoc_ie, &buf[cnt], priv->pmib->wscEntry.assoc_ielen); - wps_ie_found = 1; - break; - } - cnt += buf[cnt+1]+2; //goto next - } - - if (!wps_ie_found) - { - priv->pmib->wscEntry.wsc_enable = 0; - priv->pmib->wscEntry.assoc_ielen = 0; - } - } - - kfree(buf); - } - - return ret; -} - - -int rtl_siwauth(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_param *param = (struct iw_param*)&(wrqu->param); - int value = param->value; - int ret = 0; - - printk("rtl_siwauth : cmd:%d val:%d\n", (param->flags & IW_AUTH_INDEX), param->value); - - switch (param->flags & IW_AUTH_INDEX) { - - case IW_AUTH_WPA_VERSION: -#ifdef CONFIG_RTL_WAPI_SUPPORT - priv->pmib->wapiInfo.wapiType = wapiDisable; - if(value == IW_AUTH_WAPI_VERSION_1) - { - priv->pmib->wapiInfo.wapiType = wapiTypePSK; - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == 0; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; - } else -#endif - if (value == IW_AUTH_WPA_VERSION_DISABLED) { - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; - } - else if (value == IW_AUTH_WPA_VERSION_WPA) - { - priv->pmib->wapiInfo.wapiType = wapiDisable; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA; - } - else if (value == IW_AUTH_WPA_VERSION_WPA2) - { - priv->pmib->wapiInfo.wapiType = wapiDisable; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA2; - } - break; - - case IW_AUTH_CIPHER_PAIRWISE: - DEBUG_INFO("set_auth(IW_AUTH_CIPHER_PAIRWISE) value=%d\n", param->value); - if (param->value & IW_AUTH_CIPHER_WEP40) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; - else if (param->value & IW_AUTH_CIPHER_WEP104) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; - else if (param->value & IW_AUTH_CIPHER_TKIP) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _TKIP_PRIVACY_; - else if (param->value & IW_AUTH_CIPHER_CCMP) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _CCMP_PRIVACY_; - else if (param->value & IW_AUTH_CIPHER_NONE) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - else { - return -EINVAL; - } - break; - - case IW_AUTH_CIPHER_GROUP: - DEBUG_INFO("set_auth(IW_AUTH_CIPHER_GROUP) value=%d\n", value); - - if (value & IW_AUTH_CIPHER_WEP40) - priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_WEP40; - else if (value & IW_AUTH_CIPHER_WEP104) - priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_WEP104; - else if (value & IW_AUTH_CIPHER_TKIP) - priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_TKIP; - else if (value & IW_AUTH_CIPHER_CCMP) - priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_CCMP; - else if (value & IW_AUTH_CIPHER_NONE) - priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_NONE; - else { - return -EINVAL; - } - - break; - - case IW_AUTH_KEY_MGMT: -#ifdef CONFIG_RTL_WAPI_SUPPORT - if (priv->pmib->wapiInfo.wapiType != wapiDisable) - { - if(value == IW_AUTH_KEY_MGMT_WAPI_PSK) - priv->pmib->wapiInfo.wapiType = wapiTypePSK; - else - priv->pmib->wapiInfo.wapiType = wapiTypeCert; - DEBUG_INFO("%s: IW_AUTH_KEY_MGMT wapiType %d \n", __FUNCTION__, priv->pmib->wapiInfo.wapiType); - } else -#endif -#if 0 - if (value & IW_AUTH_KEY_MGMT_802_1X) - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; - else - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; -#endif - break; - - case IW_AUTH_TKIP_COUNTERMEASURES: - // TODO: TKIP countermeasures - break; - - case IW_AUTH_DROP_UNENCRYPTED: - break; - - case IW_AUTH_80211_AUTH_ALG: - if ((param->value & IW_AUTH_ALG_SHARED_KEY)&&(param->value & IW_AUTH_ALG_OPEN_SYSTEM)) - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; // Auto - else if(param->value & IW_AUTH_ALG_OPEN_SYSTEM) - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; // Open - else if (param->value & IW_AUTH_ALG_SHARED_KEY) - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 1; // Shared - else if (param->value & IW_AUTH_ALG_LEAP) - { - DEBUG_WARN("%s: wpa_set_auth_algs, AUTH_ALG_LEAP\n", __FUNCTION__); - } - else - ret = -EINVAL; - break; - - case IW_AUTH_WPA_ENABLED: - if ( param->value == 0 ) { - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = 0; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; - - priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; - priv->pmib->dot11GroupKeysTable.dot11Privacy = 0; - - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; - priv->pmib->dot11RsnIE.rsnielen = 0; - } - - break; - - case IW_AUTH_RX_UNENCRYPTED_EAPOL: - //ieee->ieee802_1x = param->value; - break; - - case IW_AUTH_PRIVACY_INVOKED: - //ieee->privacy_invoked = param->value; - break; - -#ifdef CONFIG_RTL_WAPI_SUPPORT - case IW_AUTH_WAPI_ENABLED: - break; -#endif - - default: - return -EOPNOTSUPP; - } - return ret; -} - - -int rtl_giwauth(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, - char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_param *param = (struct iw_param*)&(wrqu->param); - int ret = 0; - - - DEBUG_INFO("%s: get_auth: flags=0x%x authmode=%d\n", __FUNCTION__, wrq->flags, authmode); - param->value = 0; - - switch (param->flags & IW_AUTH_INDEX) { - case IW_AUTH_WPA_VERSION: -#ifdef CONFIG_RTL_WAPI_SUPPORT - if (priv->pmib->wapiInfo.wapiType != wapiDisable;) - { - param->value |= IW_AUTH_WAPI_VERSION_1; - } -#endif - if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK & PSK_WPA) - { - param->value |= IW_AUTH_WPA_VERSION_WPA; - } - - if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK & PSK_WPA2) - { - param->value |= IW_AUTH_WPA_VERSION_WPA2; - } - break; - - case IW_AUTH_CIPHER_PAIRWISE: - if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) - { - param->value |= IW_AUTH_CIPHER_WEP40; - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) - { - param->value |= IW_AUTH_CIPHER_WEP104; - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _TKIP_PRIVACY_) - { - param->value |= IW_AUTH_CIPHER_TKIP; - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _CCMP_PRIVACY_) - { - param->value |= IW_AUTH_CIPHER_CCMP; - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _NO_PRIVACY_) - { - param->value |= IW_AUTH_CIPHER_NONE; - } - break; - - case IW_AUTH_KEY_MGMT: -#ifdef CONFIG_RTL_WAPI_SUPPORT - if (priv->pmib->wapiInfo.wapiType != wapiDisable) - { - if (priv->pmib->wapiInfo.wapiType == wapiTypePSK) - param->value = IW_AUTH_KEY_MGMT_WAPI_PSK; - else - param->value = IW_AUTH_KEY_MGMT_WAPI_CERT; - } else -#endif - if (priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm) - { - if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) - param->value = IW_AUTH_KEY_MGMT_PSK; - else - param->value = IW_AUTH_KEY_MGMT_802_1X; - } - break; -// TODO:==> - case IW_AUTH_80211_AUTH_ALG: - switch (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm) { - case 0: - param->value = IW_AUTH_ALG_OPEN_SYSTEM; - break; - - case 1: - param->value = IW_AUTH_ALG_OPEN_SYSTEM; - break; - - default: - DEBUG_ERR("%s: invalid auth_alg(%d)\n", __FUNCTION__,priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm); - param->value = IW_AUTH_ALG_OPEN_SYSTEM; - break; - } - break; - - case IW_AUTH_WPA_ENABLED: - // TODO: - break; - - default: - ret = -EOPNOTSUPP; - } - DEBUG_INFO("%s: flags=0x%x value=%d ret=%d\n", __FUNCTION__, param->flags, param->value, ret); - - return ret; -} - - -int rtl_siwencodeext(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_point *encoding = &wrqu->encoding; - struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; - s4Byte alg = ext->alg; - u1Byte EncAlgorithm = DOT11_ENC_NONE; - s4Byte KeyIndex; - u4Byte KeyLength=0; - BOOLEAN IsDefaultKey = FALSE; - pu1Byte KeyMaterial = ext->key; - BOOLEAN IsGroupKey = FALSE; -// u8Byte KeyRSC; - int ret=0; - DOT11_SET_KEY Set_Key; - struct stat_info *pstat; - - memset((char *)&Set_Key, 0, sizeof(Set_Key)); - - if (encoding->flags & IW_ENCODE_DISABLED) { - alg = IW_ENCODE_ALG_NONE; - } - - /* Get Key Index and convet to our own defined key index */ - KeyIndex = (encoding->flags & IW_ENCODE_INDEX) - 1; - KeyLength = ext->key_len; - if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { - IsDefaultKey = TRUE; - } - - //if ((ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) || (IS_BCAST(ext->addr.sa_data))) { - if ( (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) ) { - IsGroupKey = TRUE; - } - - printk("siwencode alg:%x ext_flags:%x/ len:%u\n", (u4Byte)alg, ext->ext_flags, KeyLength); - - DEBUG_INFO("%s: \n", __FUNCTION__); - DEBUG_INFO("KeyIndex = %d\n", KeyIndex); - DEBUG_INFO("KeyLength = %u\n", KeyLength); - //DEBUG_INFO("KeyMaterial = %32s\n", KeyMaterial); - DEBUG_INFO("IsDefaultKey = %d\n", IsDefaultKey); - DEBUG_INFO("IsGroupKey = %d\n", IsGroupKey); - - switch (alg) { - case IW_ENCODE_ALG_NONE: - /* Clear all keys */ - EncAlgorithm = DOT11_ENC_NONE; - break; - - case IW_ENCODE_ALG_WEP: - if ((KeyIndex < 0) || (KeyIndex >= 4)) - { - ret = -EINVAL; - goto set_encodeext_end; - } - - if(KeyLength == 5){ - EncAlgorithm = DOT11_ENC_WEP40; - } - else if(KeyLength == 13) { - EncAlgorithm = DOT11_ENC_WEP104; - } - else - { - ret = -EINVAL; - goto set_encodeext_end; - } - - break; - - case IW_ENCODE_ALG_TKIP: - EncAlgorithm = DOT11_ENC_TKIP; - // Check key length for TKIP. - if(KeyLength != 32) { - if (IsGroupKey && (KeyLength == 5 || KeyLength == 13)) { - // 5 = WEP40 13 = WEP104 16 = CKIP - if(KeyLength == 5) { - EncAlgorithm = DOT11_ENC_WEP40; - } else { - EncAlgorithm = DOT11_ENC_WEP104; - } - DEBUG_WARN("%s: Check key length 5 or 13 for Mix-mode WEP.\n", __FUNCTION__); - } else { - DEBUG_ERR("TKIP KeyLength:%u != 32\n", KeyLength); - ret = -EINVAL; - goto set_encodeext_end; - } - } - - break; - - case IW_ENCODE_ALG_CCMP: - EncAlgorithm = DOT11_ENC_CCMP; - if(KeyLength != 16) { - // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. - if(KeyLength == 32) - KeyLength = 16; - } - - if((KeyLength != 16) && (KeyLength != 32)) { - if (IsGroupKey && (KeyLength == 5 || KeyLength == 13)) { - // 5 = WEP40 13 = WEP104 16 = CKIP - if(KeyLength == 5) { - EncAlgorithm = DOT11_ENC_WEP40; - } else { - EncAlgorithm = DOT11_ENC_WEP104; - } - DEBUG_WARN("%s: Check key length 5 or 13 for Mix-mode WEP.\n", __FUNCTION__); - } else { - DEBUG_ERR("AES_CCM KeyLength:%u != 16\n", KeyLength); - ret = -EINVAL; - goto set_encodeext_end; - } - } - break; - - default: - ret = -EINVAL; - goto set_encodeext_end; - } - - if (KeyLength > 0) { - if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { - memcpy(priv->pmib->dot11DefaultKeysTable.keytype[KeyIndex].skey, KeyMaterial, KeyLength); - } - - if (IsDefaultKey) { - if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = KeyLength <= 5 ? _WEP_40_PRIVACY_ : _WEP_104_PRIVACY_; - priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = KeyLength <= 5 ? 8 : 16; - priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex = KeyIndex; - - // don't setup PTK CAM because BSSID is unavailable before first join. - // PTK CAM will be set on set_keymapping_wep when association success. - if (IsGroupKey) { - struct Dot11EncryptKey *pEncryptKey; - - priv->pmib->dot11GroupKeysTable.dot11Privacy = EncAlgorithm; - priv->pmib->dot11GroupKeysTable.keyid = KeyIndex; - - pEncryptKey = &priv->pmib->dot11GroupKeysTable.dot11EncryptKey; - pEncryptKey->dot11TTKeyLen = KeyLength <= 5 ? 5 : 13; - pEncryptKey->dot11TMicKeyLen = 0; - memset(pEncryptKey->dot11TTKey.skey, 0, sizeof(pEncryptKey->dot11TTKey.skey)); - memcpy(pEncryptKey->dot11TTKey.skey, KeyMaterial, pEncryptKey->dot11TTKeyLen); - } - goto set_encodeext_end; - } - } - - if (IsGroupKey) { - /* cliW: not set group key in wep key */ - if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { - goto set_encodeext_end; - } - /* cliW: fix group key for wpa_supplicant rekey use toogle index */ - if ((EncAlgorithm == DOT11_ENC_TKIP) || (EncAlgorithm == DOT11_ENC_CCMP)) - KeyIndex = 1; - - priv->pmib->dot11GroupKeysTable.dot11Privacy = EncAlgorithm; - priv->pmib->dot11GroupKeysTable.keyid = KeyIndex; - } - - /* cliW test supplicant using [ len : tx : rx ] key format */ - if ( EncAlgorithm == DOT11_ENC_TKIP ) { - char tmp[8]; -#if 1 - WPA_GLOBAL_INFO *pGblInfo = priv->wpa_global_info; - - if ( IsDefaultKey ) { - pGblInfo->GkeyReady = TRUE; - pGblInfo->GN = KeyIndex; - } - pGblInfo->MulticastCipher = _TKIP_PRIVACY_; -#endif - memcpy(tmp, KeyMaterial+16, 8); - memcpy(KeyMaterial+16, KeyMaterial+24, 8); - memcpy(KeyMaterial+24, tmp, 8); - } - - memcpy(Set_Key.MACAddr, ext->addr.sa_data, MACADDRLEN); - if (IsDefaultKey) - Set_Key.KeyType = DOT11_KeyType_Pairwise; - else - Set_Key.KeyType = (IsGroupKey ? DOT11_KeyType_Group : DOT11_KeyType_Pairwise); - - Set_Key.EncType = EncAlgorithm; - Set_Key.KeyIndex = KeyIndex; - Set_Key.KeyLen = KeyLength; - ret = DOT11_Process_Set_Key(dev, NULL, &Set_Key, KeyMaterial); - - if ((EncAlgorithm == DOT11_ENC_TKIP) || (EncAlgorithm == DOT11_ENC_CCMP)) - { - pstat = get_stainfo(priv, ext->addr.sa_data); - if ((pstat != NULL) && (pstat->state & WIFI_ASOC_STATE)) - pstat->ieee8021x_ctrlport = 1; - } - } - else if (EncAlgorithm == DOT11_ENC_NONE) - { - // Remove Key - DOT11_DELETE_KEY Delete_Key; - struct iw_point wrq; - - if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) - { - memset(priv->pmib->dot11DefaultKeysTable.keytype[KeyIndex].skey, 0, 16); - } - - if (IsDefaultKey) - { - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = 0; - } - - wrq.pointer = (caddr_t)&Delete_Key; - wrq.length = sizeof(DOT11_DELETE_KEY); - - memset(&Delete_Key, 0, sizeof(Delete_Key)); - Delete_Key.EventId = DOT11_EVENT_DELETE_KEY; - Delete_Key.IsMoreEvent = FALSE; - - Delete_Key.KeyType = (IsGroupKey ? DOT11_KeyType_Group : DOT11_KeyType_Pairwise); - memcpy(Delete_Key.MACAddr, ext->addr.sa_data, MACADDRLEN); - - // check root intf is up before deleting key to avoid stuck in CAM_read_mac_config - if (IS_DRV_OPEN(GET_ROOT(priv))) - ret = DOT11_Process_Delete_Key(priv->dev, &wrq); - } - -set_encodeext_end: - return ret; -} - -int rtl_giwencodeext(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, - char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - struct iw_point *encoding = &wrqu->encoding; - struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; - s4Byte key_index; - s4Byte ret = 0; - s4Byte max_key_len; - char *pkey=NULL; -// char keybuf[32]; - int keylen=0; - - DEBUG_INFO("rtwlan_ioctl: rtioctl_get_encodeext: \n"); - - max_key_len = encoding->length - sizeof(struct iw_encode_ext); - if (max_key_len < 0) - return -EINVAL; - key_index = (encoding->flags & IW_ENCODE_INDEX) - 1; - - memset(ext, 0, sizeof(struct iw_encode_ext)); - - switch (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm) { - case _WEP_40_PRIVACY_: - case _WEP_104_PRIVACY_: - ext->alg = IW_ENCODE_ALG_WEP; - encoding->flags |= IW_ENCODE_ENABLED; - pkey = priv->pmib->dot11DefaultKeysTable.keytype[key_index].skey; - keylen = 16; - break; - - case _TKIP_PRIVACY_: - ext->alg = IW_ENCODE_ALG_TKIP; - encoding->flags |= IW_ENCODE_ENABLED; - // TODO: get key - break; - - case _CCMP_PRIVACY_: - ext->alg = IW_ENCODE_ALG_CCMP; - encoding->flags |= IW_ENCODE_ENABLED; - // TODO: get key - break; - - case _NO_PRIVACY_: - default: - ext->alg = IW_ENCODE_ALG_NONE; - encoding->flags |= IW_ENCODE_NOKEY; - break; - } - - if (!(encoding->flags & IW_ENCODE_NOKEY)) { - if (max_key_len < keylen) { - ret = -E2BIG; - goto out; - } - if (pkey) - memcpy (ext->key, pkey, keylen); - } - - out: - return ret; -} - -int rtl_siwpmkid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned char j,blInserted = _FALSE; - int ret=0; - -#if 0 - struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra; - unsigned char strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; - unsigned char strIssueBssid[ ETH_ALEN ] = { 0x00 }; - - /* - struct iw_pmksa - { - __u32 cmd; - struct sockaddr bssid; - __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16 - } - There are the BSSID information in the bssid.sa_data array. - If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information. - If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver. - If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver. - */ - - memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); - if ( pPMK->cmd == IW_PMKSA_ADD ) - { - DEBUG_INFO( "%s: IW_PMKSA_ADD!\n", __FUNCTION__ ); - if (!memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN )) - { - return (-EINVAL); - } - - blInserted = _FALSE; - - //overwrite PMKID - for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ) - { // BSSID is matched, the same AP => rewrite with new PMKID. - - DEBUG_INFO( "%s: BSSID exists in the PMKList.\n", __FUNCTION__ ); - - memcpy( priv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); - priv->PMKIDList[ j ].bUsed = _TRUE; - priv->PMKIDIndex = j+1; - blInserted = _TRUE; - break; - } - } - - if(!blInserted) - { - // Find a new entry - DEBUG_INFO( "[%s] Use the new entry index = %d for this PMKID.\n", __FUNCTION__, - priv->PMKIDIndex ); - - memcpy(priv->PMKIDList[priv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); - memcpy(priv->PMKIDList[priv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); - - priv->PMKIDList[priv->PMKIDIndex ].bUsed = _TRUE; - priv->PMKIDIndex++ ; - if(priv->PMKIDIndex == NUM_PMKID_CACHE) - { - priv->PMKIDIndex = 0; - } - } - } - else if ( pPMK->cmd == IW_PMKSA_REMOVE ) - { - DEBUG_INFO( "[%s] IW_PMKSA_REMOVE!\n", __FUNCTION__ ); - for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN)) - { // BSSID is matched, the same AP => Remove this PMKID information and reset it. - memset( priv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN ); - priv->PMKIDList[ j ].bUsed = _FALSE; - break; - } - } - } - else if ( pPMK->cmd == IW_PMKSA_FLUSH ) - { - DEBUG_INFO( "[%s] IW_PMKSA_FLUSH!\n", __FUNCTION__ ); - memset( &priv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); - priv->PMKIDIndex = 0; - } -#endif - return( ret ); -} -#endif // WIFI_WPAS_CLI -#endif // CONFIG_RTL_COMAPI_WLTOOLS - -#ifdef CONFIG_RTL_COMAPI_CFGFILE - -#define CFG_FILE_PATH "/etc/Wireless/RTL8192CD.dat" - -void del_mib_list(struct net_device *dev); -int CfgFileSetMib(struct net_device *dev, char *buf); - -int CfgFileProc(struct net_device *dev) -{ - //RTL_PRIV *priv = dev->priv; - unsigned char *mem_ptr; - int ret = 0; - - printk("-------> Set MIB from " CFG_FILE_PATH "\n"); - if((mem_ptr = (unsigned char *)kmalloc(MAX_CONFIG_FILE_SIZE, GFP_ATOMIC)) == NULL) { - printk("%s: not enough memory\n", __FUNCTION__); - return -1; - } - - memset(mem_ptr, 0, MAX_CONFIG_FILE_SIZE); - - ret = CfgFileRead(dev, mem_ptr); - - if (ret < 0) - { - printk("%s: ReadCfgFile failed (%d)\n", __FUNCTION__, ret); - goto proc_exit; - } - - //printk("%s\n", mem_ptr); - - del_mib_list(dev); - - CfgFileSetMib(dev, mem_ptr); - - printk("<------- Set MIB from " CFG_FILE_PATH " Success\n"); - -proc_exit: - kfree(mem_ptr); - return ret; - -} - -int CfgFileRead(struct net_device *dev, char *buf) -{ - //RTL_PRIV *priv = dev->priv; - struct file *fp; - mm_segment_t oldfs; - //size_t len; - - //int read_bytes = 0; - int ret = 0; - - oldfs = get_fs(); - set_fs(get_ds()); - fp = filp_open(CFG_FILE_PATH, O_RDONLY, 0); - if(IS_ERR(fp)) { - ret = PTR_ERR(fp); - printk("Fail to open configuration file. (%d)\n", ret); - goto err_exit; - } - - if (!(fp->f_op && fp->f_op->read)) { - printk("Fail to support file ops: read\n"); - ret = -1; - goto err_close; - } - - if ((ret = fp->f_op->read(fp, buf, MAX_CONFIG_FILE_SIZE, &fp->f_pos))< 0){ - printk("Fail to read file. (%d)\n", ret); - goto err_close; - } - -err_close: - filp_close(fp, NULL); -err_exit: - set_fs(oldfs); - return ret; - -} - -static int rewrite_line (unsigned char **dst, unsigned char **src) -{ - int cnt=0; - char *s = *src; - char *d = *dst; - char *loc=NULL, *vl_s=NULL, *vl_e=NULL; - unsigned char quoted = 0; - - //printk("src = %s(%d)\n", *src, strlen(*src)); - loc=strchr(s, '"'); - if (loc) { - unsigned int i = strlen(*src); - vl_s=loc; - while (i>0){ - char *t = (char *)((unsigned long)s+i-1); - if (*t=='"' && t > vl_s ){ - vl_e = t; - quoted = 1; - break; - } - i--; - } - } - - while (*s) { - u8 noop = 0; - if (quoted ==1 && (vl_s < s && s < vl_e)) - noop = 1; - - if ( noop == 0 ) { - if ((*s=='\r') || (*s=='\n') || (*s=='#') || (*s=='\0')) - break; - if ((*s == '\t')||(*s == ' ')||(*s == '"')){ - s++; - continue; - } - } - - *d = *s; - s++; - d++; - cnt++; - - } - *d = '\0'; - //printk(" dst = %s\n", *dst); - return cnt; -} - - -int CfgFileSetMib(struct net_device *dev, char *buf) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - unsigned char *line_head, *next_head; - unsigned char *cmd_buf, *mibstr, *valstr, *mibstart; - //struct mib_cfg_func *tmp_mibcfg; - int ret = 0; -#ifdef VENDOR_PARAM_COMPATIBLE - int arg_num = sizeof(RTL_SUPPORT_MIBCFG)/sizeof(struct mib_cfg_func); -#endif //VENDOR_PARAM_COMPATIBLE - - if((cmd_buf = (unsigned char *)kmalloc(MAX_PARAM_BUF_SIZE, GFP_ATOMIC)) == NULL) { - printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); - return -1; - } - - if((mibstr = (unsigned char *)kmalloc(20, GFP_ATOMIC)) == NULL) { - printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); - return -1; - } - - if((valstr = (unsigned char *)kmalloc(MAX_PARAM_BUF_SIZE, GFP_ATOMIC)) == NULL) { - printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); - return -1; - } - - next_head = buf; - - do { - char *loc; - int len = 0, miblen = 0, vallen = 0; - //int i=0; - - memset(cmd_buf, 0, MAX_PARAM_BUF_SIZE); - memset(mibstr, 0, 20); - memset(valstr, 0, MAX_PARAM_BUF_SIZE); - - line_head = next_head; - next_head = get_line(&line_head); - if (line_head == NULL) - break; - - if (line_head[0] == '#') - continue; - - len = rewrite_line(&cmd_buf, &line_head); - //printk("%s (%d)\n", cmd_buf, len); - -#ifdef VENDOR_PARAM_COMPATIBLE - /* To compatible with other vendor's parameters, each parameter must have its own process function - chris*/ - loc = strchr(mibstart, '='); - miblen = (u32)loc - (u32)mibstart; - vallen = len - miblen -1; - if (vallen>0) { - for (i=0; i>>>>>>> cmd=%s , %s, %c \n",cmd_buf, dev->name, cmd_buf[strlen(dev->name)]); - if (!strncmp(dev->name, cmd_buf, strlen(dev->name))&&(cmd_buf[strlen(dev->name)]!='-')) { - mibstart = cmd_buf + strlen(dev->name)+1; - } else - continue; - - loc = strchr(mibstart, '='); - miblen = (u32)loc - (u32)mibstart; - vallen = len - (strlen(dev->name)+1) - (miblen+1); - - if (vallen>0) { - - ret = set_mib(priv, mibstart); - if (ret < 0) { - strncpy(mibstr, mibstart, miblen); - strncpy(valstr, (char*)((u32)loc+1), vallen); - //printk("(%s) = (%s) (%d)\n", mibstr, valstr, vallen); - printk("CFGFILE set_mib \"%s\" failed \n", mibstart); - //return -1; - } - -#endif // VENDOR_PARAM_COMPATIBLE - } - - } while (1); - - kfree(cmd_buf); - kfree(mibstr); - kfree(valstr); - - return ret; -} - -void del_mib_list(struct net_device *dev) -{ - RTL_PRIV *priv = GET_DEV_PRIV(dev); - - - if (priv->pmib) { -#ifdef WDS - priv->pmib->dot11WdsInfo.wdsNum = 0; -#endif - priv->pmib->dot11StationConfigEntry.dot11AclNum=0; - } - -} - -#endif //CONFIG_RTL_COMAPI_CFGFILE - - - +/* + * API-compatible handling routines + * + * + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define _8192CD_COMAPI_C_ + + +#ifdef __KERNEL__ +#include +#include +#include +#include +#include +#include +#include +#endif + +#ifdef __LINUX_2_6__ +#include +#include +#endif + +#include "./8192cd_debug.h" +#include "./8192cd_comapi.h" +#include "./8192cd_headers.h" + #ifdef SUPPORT_MONITOR +#include "./8192cd_util.h" +#endif +#ifdef CONFIG_RTL_COMAPI_WLTOOLS +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) +#define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_A, _B, _C, _D, _E) +#define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_A, _B, _C, _D, _E) +#define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_A, _B, _C, _D, _E, _F) +#else +#define IWE_STREAM_ADD_EVENT(_A, _B, _C, _D, _E) iwe_stream_add_event(_B, _C, _D, _E) +#define IWE_STREAM_ADD_POINT(_A, _B, _C, _D, _E) iwe_stream_add_point(_B, _C, _D, _E) +#define IWE_STREAM_ADD_VALUE(_A, _B, _C, _D, _E, _F) iwe_stream_add_value(_B, _C, _D, _E, _F) +#endif + +typedef struct _CH_FREQ_MAP_{ + UINT16 channel; + UINT16 freqKHz; +}CH_FREQ_MAP; + +CH_FREQ_MAP CH_HZ_ID_MAP[] = +{ + {1, 2412}, + {2, 2417}, + {3, 2422}, + {4, 2427}, + {5, 2432}, + {6, 2437}, + {7, 2442}, + {8, 2447}, + {9, 2452}, + {10, 2457}, + {11, 2462}, + {12, 2467}, + {13, 2472}, + {14, 2484}, + + /* UNII */ + {36, 5180}, + {40, 5200}, + {44, 5220}, + {48, 5240}, + {52, 5260}, + {56, 5280}, + {60, 5300}, + {64, 5320}, + {149, 5745}, + {153, 5765}, + {157, 5785}, + {161, 5805}, + {165, 5825}, + {167, 5835}, + {169, 5845}, + {171, 5855}, + {173, 5865}, + + /* HiperLAN2 */ + {100, 5500}, + {104, 5520}, + {108, 5540}, + {112, 5560}, + {116, 5580}, + {120, 5600}, + {124, 5620}, + {128, 5640}, + {132, 5660}, + {136, 5680}, + {140, 5700}, + + /* Japan MMAC */ + {34, 5170}, + {38, 5190}, + {42, 5210}, + {46, 5230}, + + /* Japan */ + {184, 4920}, + {188, 4940}, + {192, 4960}, + {196, 4980}, + + {208, 5040}, /* Japan, means J08 */ + {212, 5060}, /* Japan, means J12 */ + {216, 5080}, /* Japan, means J16 */ +}; + +int CH_HZ_ID_MAP_NUM = (sizeof(CH_HZ_ID_MAP)/sizeof(CH_FREQ_MAP)); + + +#define MAP_CHANNEL_ID_TO_KHZ(_ch, _khz) \ + do{ \ + int _chIdx; \ + for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++)\ + { \ + if ((_ch) == CH_HZ_ID_MAP[_chIdx].channel) \ + { \ + (_khz) = CH_HZ_ID_MAP[_chIdx].freqKHz * 1000; \ + break; \ + } \ + } \ + if (_chIdx == CH_HZ_ID_MAP_NUM) \ + (_khz) = 2412000; \ + }while(0) + +#define MAP_KHZ_TO_CHANNEL_ID(_khz, _ch) \ + do{ \ + int _chIdx; \ + for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++)\ + { \ + if ((_khz) == CH_HZ_ID_MAP[_chIdx].freqKHz) \ + { \ + (_ch) = CH_HZ_ID_MAP[_chIdx].channel; \ + break; \ + } \ + } \ + if (_chIdx == CH_HZ_ID_MAP_NUM) \ + (_ch) = 1; \ + }while(0) + +/* +struct iw_statistics *rtl8192cd_get_wireless_stats(struct net_device *net_dev) +{ + // client mode only + return NULL; +} +*/ + +#ifdef WIFI_WPAS_CLI +extern void clean_for_join(struct rtl8192cd_priv *priv); + +void use_ap_scan( RTL_PRIV *priv ) +{ + RTL_PRIV *r_priv; + + priv->pshare->bScanInProcess = FALSE; + + if ( IS_ROOT_INTERFACE(priv) ) { + printk("cliW: ss_req\n"); + priv->ss_req_ongoing = 1; + start_clnt_ss(priv); + } else { + printk("cliW: vxd req\n"); + r_priv = GET_ROOT(priv); + r_priv->ss_ssidlen = 0; + r_priv->ss_req_ongoing = SSFROM_WPAS; + start_clnt_ss(r_priv); + } +} + +#if 0 +void switch_chan(struct rtl8192cd_priv *priv, struct bss_desc *bss_desp) +{ + struct rtl8192cd_priv *root_priv; + u8 is_40m, channel, ch_offset; + int bw; + unsigned long flags; + + printk("vxd chan follows\n"); + + //RTL_W8(TXPAUSE, 0xff); + + channel = bss_desp->channel; + priv->pmib->dot11RFEntry.dot11channel = channel; + + if ((bss_desp->t_stamp[1] & (BIT(1) | BIT(2))) == (BIT(1) | BIT(2))) + ch_offset = HT_2NDCH_OFFSET_BELOW; + else if ((bss_desp->t_stamp[1] & (BIT(1)|BIT(2))) == BIT(1)) + ch_offset = HT_2NDCH_OFFSET_ABOVE; + else + ch_offset = HT_2NDCH_OFFSET_DONTCARE; + + if ( ch_offset != 0 ) + is_40m = 1; + + if ( IS_VXD_INTERFACE(priv) ) { + root_priv = GET_ROOT(priv); + bw = (root_priv->pmib->dot11nConfigEntry.dot11nUse40M && is_40m); + if (0 == bw) + ch_offset = HT_2NDCH_OFFSET_DONTCARE; + + priv->pshare->is_40m_bw = bw; + priv->pshare->CurrentChannelBW = bw; + priv->pshare->offset_2nd_chan = ch_offset; + + priv->pmib->dot11RFEntry.dot11channel = channel; + priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; + priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; + + root_priv->pmib->dot11RFEntry.dot11channel = channel; + root_priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; + root_priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; + root_priv->ht_cap_len = 0; // re-construct HT IE + init_beacon(root_priv); +#ifdef MBSSID + if (root_priv->pmib->miscEntry.vap_enable) { + struct rtl8192cd_priv *vap_priv; + int i; + + for (i = 0; i < RTL8192CD_NUM_VWLAN; i++) { + vap_priv = root_priv->pvap_priv[i]; + if (IS_DRV_OPEN(vap_priv)) { + vap_priv->pmib->dot11RFEntry.dot11channel = channel; + vap_priv->pmib->dot11nConfigEntry.dot11nUse40M = bw; + vap_priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; + vap_priv->ht_cap_len = 0; // re-construct HT IE + init_beacon(vap_priv); + } + } + } +#endif // MBSSID + } else { + root_priv = priv; + + priv->pshare->is_40m_bw = is_40m; + priv->pshare->CurrentChannelBW = is_40m; + priv->pshare->offset_2nd_chan = ch_offset; + + priv->pmib->dot11RFEntry.dot11channel = channel; + priv->pmib->dot11nConfigEntry.dot11nUse40M = is_40m; + priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = ch_offset; +#ifdef UNIVERSAL_REPEATER + // TO DO ... +#endif + } + + SwBWMode(root_priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan); + SwChnl(root_priv, channel, priv->pshare->offset_2nd_chan); + + // RTL_W8(TXPAUSE, 0x00); + + // update_beacon +} +#endif + +int rtl_wx_dummy(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + return -1; +} + + +int rtl_wx_join(struct rtl8192cd_priv *priv, struct bss_desc *bss_desp) +{ + char tmpbuf[33]; + + printk("cliW: join opmode: %x res:%x \n", OPMODE, priv->join_res); + if (!netif_running(priv->dev)) + { + printk("WiFi driver is NOT open!!\n"); + return 1; + } + else if (priv->ss_req_ongoing) + { + printk("Site Survey is not finished yet!!\n"); + return 2; + } + + //if ( priv->join_res == STATE_Sta_No_Bss ) + // goto cnti_join; + + // memcpy((void *)&(priv->pmib->dot11Bss) , + // (void *)&priv->site_survey->bss_backup[bss_num] , sizeof(struct bss_desc)); + + memcpy(&(priv->pmib->dot11Bss), bss_desp, sizeof(struct bss_desc)); + +#if 0 + if ( priv->join_req_ongoing ) { + printk("cliW: no join under connecinting \n"); + return 0; + } +#endif + + if( ( priv->pmib->dot11Bss.ssidlen < 0) || (priv->pmib->dot11Bss.ssidlen > 32) ) { + printk("cliW: wrong ssid len\n"); + return 3; + } +#if 0 + if (priv->ss_req_ongoing || priv->join_req_ongoing ) { + printk("cliW: no join under scanning \n"); + return 0; + } +#endif + + if ( OPMODE & ( WIFI_AUTH_STATE1 | WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE) ) { + printk("cliW: no joining when in auth\n"); + return 4; + } + +#if 0 + if ( OPMODE & WIFI_ASOC_STATE || (priv->join_res == STATE_Sta_Bss) ) { + printk("cliW: no joining when in asso\n"); + return 0; + } +#endif + +#ifdef WIFI_SIMPLE_CONFIG + //_Eric if (priv->pmib->wscEntry.wsc_enable && (priv->pmib->dot11Bss.bsstype&WIFI_WPS)) + if (priv->pmib->wscEntry.wsc_enable) + { + //priv->pmib->dot11Bss.bsstype &= ~WIFI_WPS; + priv->wps_issue_join_req = 1; + } + else +#endif + { + if (check_bss_encrypt(priv) == FAIL) + { + printk("Encryption mismatch!\n"); + return 5; + } + } + + if ((priv->pmib->dot11Bss.ssidlen == 0) || (priv->pmib->dot11Bss.ssid[0] == '\0')) + { + printk("Error !! Join to a hidden AP!\n"); + return 6; + } + +#ifdef UNIVERSAL_REPEATER + disable_vxd_ap(GET_VXD_PRIV(priv)); +#endif + + memcpy(tmpbuf, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); + tmpbuf[priv->pmib->dot11Bss.ssidlen] = '\0'; + printk("going to join bss: %s\n", tmpbuf); + + memcpy(SSID2SCAN, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); + SSID2SCAN_LEN = priv->pmib->dot11Bss.ssidlen; + + SSID_LEN = SSID2SCAN_LEN; + memcpy(SSID, SSID2SCAN, SSID_LEN); + memset(BSSID, 0, MACADDRLEN); + +#ifdef INCLUDE_WPA_PSK //_Eric ?? + //if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) + //derivePSK(priv); +#endif + + priv->join_req_ongoing = 1; + priv->authModeRetry = 0; + + // switch_chan() is replaced with clnt_switch_chan_to_bss in start_clnt_auth + //switch_chan(priv, bss_desp); + + printk("cliw: start join... in ch:%d\n", bss_desp->channel); +#if defined(CONFIG_PCI_HCI) + start_clnt_join(priv); +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + // avoid IQK handling race condition between start_clnt_auth and TXPowerTracking + // so we indicate WPAS_JOIN event to cmd_thread to do start_clnt_join() + notify_wpas_join(priv); +#endif + + return 0; +} + +int rtl_wx_get_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct stat_info *pstat; + struct wifi_mib *pmib; + char *p; + + DEBUG_INFO("cmd_code=%x\n", info->cmd); + + DBFENTER; + + pstat = priv->pstat_cache; + if (pstat == NULL) { + DEBUG_INFO("pstat is NULL\n"); + return 0; + } + + pmib = GET_MIB(priv); + + if ((pstat->state & (WIFI_ASOC_STATE | WIFI_AUTH_SUCCESS)) == ((WIFI_ASOC_STATE | WIFI_AUTH_SUCCESS))) + { + p = wrqu->name; + p += sprintf(p, "IEEE 802.11"); + + if (pmib->dot11BssType.net_work_type & WIRELESS_11A) { + p += sprintf(p, "a"); + } + + if (pmib->dot11BssType.net_work_type & WIRELESS_11B) { + p += sprintf(p, "b"); + } + + if (pmib->dot11BssType.net_work_type & WIRELESS_11G) { + p += sprintf(p, "g"); + } + + if (pmib->dot11BssType.net_work_type & WIRELESS_11N) { + p += sprintf(p, "n"); + } + + if (pmib->dot11BssType.net_work_type & WIRELESS_11AC) { + p += sprintf(p, "ac"); + } + } + else + { + //prates = &padapter->registrypriv.dev_network.SupportedRates; + //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); + snprintf(wrqu->name, IFNAMSIZ, "off/any"); + } + + DBFEXIT; + + return 0; +} + +int rtl_wx_set_mode(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + switch(wrqu->mode) + { + case IW_MODE_AUTO: + if (OPMODE & WIFI_STATION_STATE) { + OPMODE = WIFI_STATION_STATE; + printk("set_mode = IW_MODE_AUTO ==> WIFI_STATION_STATE\n"); + } else { + OPMODE = WIFI_AP_STATE; + printk("set_mode = IW_MODE_AUTO ==> WIFI_AP_STATE\n"); + } + break; + case IW_MODE_ADHOC: + OPMODE = WIFI_ADHOC_STATE; + printk("set_mode = IW_MODE_ADHOC\n"); + break; + case IW_MODE_MASTER: + OPMODE = WIFI_AP_STATE; + printk("set_mode = IW_MODE_MASTER\n"); + break; + case IW_MODE_INFRA: + OPMODE = WIFI_STATION_STATE; + printk("set_mode = IW_MODE_INFRA\n"); + break; + + default : + ret = -EINVAL; + DEBUG_WARN("Mode: %d is not supported\n", wrqu->mode); + break; + } + + // TODO: Active the Operation Mode + return ret; +} + +int rtl_wx_get_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + wrqu->sens.value = 0; + wrqu->sens.fixed = 0; /* no auto select */ + wrqu->sens.disabled = 1; + return 0; +} + +void clean_conn_var(RTL_PRIV *priv) +{ + if (timer_pending(&priv->reauth_timer)) + del_timer_sync (&priv->reauth_timer); + + if (timer_pending(&priv->reassoc_timer)) + del_timer_sync (&priv->reassoc_timer); +#if 0 + priv->reauth_count = 0; + priv->reassoc_count = 0; + priv->auth_seq = 0; + + priv->join_res = STATE_Sta_No_Bss; + priv->reauth_count = 0; + priv->reassoc_count = 0; +#endif + priv->join_req_ongoing = 0; + priv->ss_req_ongoing = 0; + + clean_for_join(priv); +} + +#if WIRELESS_EXT >= 18 +int rtl_wx_set_mlme( + struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, + char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_mlme *wextmlme = (struct iw_mlme *)extra; + struct stat_info *pstat; + + switch(wextmlme->cmd) { + case IW_MLME_DEAUTH: + printk("Set MLME: IW_MLME_DEAUTH, Reason=%d\n", wextmlme->reason_code); + + if (OPMODE & (WIFI_AUTH_SUCCESS)) + { + issue_deauth(priv,BSSID,wextmlme->reason_code); + delay_ms(50); //Give some time to wait TX done + OPMODE &= ~(WIFI_AUTH_SUCCESS|WIFI_ASOC_STATE) ; + + pstat = get_stainfo(priv, BSSID); + if (pstat != NULL) + { + if (asoc_list_del(priv, pstat)) + { + if (pstat->expire_to > 0) + { + cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); + check_sta_characteristic(priv, pstat, DECREASE); + } + } + + free_stainfo(priv, pstat); + } + + event_indicate_wpas(priv, NULL, WPAS_DISCON, NULL); + } + clean_conn_var(priv); + break; + + case IW_MLME_DISASSOC: + printk("Set MLME: IW_MLME_DISASSOC, Reason=%d\n", wextmlme->reason_code); + + if((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) + { + pstat = get_stainfo(priv, BSSID); + issue_disassoc(priv, BSSID, wextmlme->reason_code); + + if (pstat != NULL) + { + if (pstat->expire_to > 0) + { + cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); + check_sta_characteristic(priv, pstat, DECREASE); + } + + free_stainfo(priv, pstat); + +/* memset(&priv->pmib->dot11Bss, 0, sizeof(struct bss_desc)); + memset(priv->pmib->dot11StationConfigEntry.dot11Bssid, 0, MACADDRLEN); + memset(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); + priv->pmib->dot11StationConfigEntry.dot11DesiredSSIDLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11DefaultSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); + priv->pmib->dot11StationConfigEntry.dot11DefaultSSIDLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan)); + priv->pmib->dot11StationConfigEntry.dot11SSIDtoScanLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid, 0, 6); + + priv->wpas_manual_assoc = 1; //_Eric ?? when to let driver auto-connect ?? +*/ + priv->join_res = STATE_Sta_No_Bss; +// pstat->state &= (~WIFI_ASOC_STATE); + } + } + OPMODE &= ~(WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE); + event_indicate_wpas(priv, NULL, WPAS_DISCON, NULL); + clean_conn_var(priv); + break; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + case IW_MLME_AUTH: + case IW_MLME_ASSOC: + break; +#endif + + default: + return -EINVAL; + } + + return 0; +} +#endif + +int rtl_wx_get_freq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned int ch; + unsigned long khz; + + if (priv == NULL) { + /* if 1st open fail, pAd will be free; + * So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + ch = priv->pmib->dot11RFEntry.dot11channel; + + MAP_CHANNEL_ID_TO_KHZ(ch, khz); + wrqu->freq.m = khz * 100; + wrqu->freq.e = 1; + wrqu->freq.i = ch; + + return 0; +} +#endif // WIFI_WPAS_CLI + +int rtl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned int chan=0; + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (wrqu->freq.e > 1) + return -EINVAL; + + if((wrqu->freq.e == 0) && (wrqu->freq.m <= 1000)) + chan = wrqu->freq.m; // Setting by channel number + else +#ifdef WIFI_WPAS_CLI + MAP_KHZ_TO_CHANNEL_ID( (wrqu->freq.m /100000) , chan); // Setting by frequency - search the table , like 2.412G, 2.422G, +#else + MAP_KHZ_TO_CHANNEL_ID( (wrqu->freq.m /100) , chan); // Setting by frequency - search the table , like 2.412G, 2.422G, +#endif + + priv->pmib->dot11RFEntry.dot11channel = chan; + +#ifdef WIFI_WPAS_CLI + printk("cliW: wrqu->freq.m: %d chan:%d \n", wrqu->freq.m, chan); +#else +#ifdef WIFI_HAPD + if (!netif_running(priv->dev)) + return 0; + else +#endif + SwChnl(priv, chan, priv->pshare->offset_2nd_chan); +#endif + + return 0; +} + +int rtl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned int ch; + //unsigned long m = 2412000; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + ch = priv->pmib->dot11RFEntry.dot11channel; +/* + MAP_CHANNEL_ID_TO_KHZ(ch, m); + wrqu->freq.m = m * 100; + wrqu->freq.e = 1; + wrqu->freq.i = 0; +*/ + wrqu->freq.m = ch; + wrqu->freq.e = 0; + wrqu->freq.i = 0; + + return 0; +} + +int rtl_siwmode(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret = 0; + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } +#ifndef SUPPORT_MONITOR +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif +#endif + + switch(wrqu->mode) + { + case IW_MODE_AUTO: // 0 +#ifdef WIFI_WPAS_CLI + if (OPMODE & WIFI_STATION_STATE) { + OPMODE_VAL(OPMODE & WIFI_STATION_STATE); + printk("set_mode = IW_MODE_AUTO ==> WIFI_STATION_STATE\n"); + } else { + OPMODE_VAL(OPMODE & WIFI_AP_STATE); + printk("set_mode = IW_MODE_AUTO ==> WIFI_AP_STATE\n"); + } +#else + OPMODE_VAL(OPMODE & WIFI_AP_STATE); + printk("set_mode = IW_MODE_AUTO\n"); +#endif + break; + case IW_MODE_ADHOC: // 1 + OPMODE_VAL(OPMODE & WIFI_ADHOC_STATE); + printk("set_mode = IW_MODE_ADHOC\n"); + break; + case IW_MODE_MASTER: // 3 + OPMODE_VAL(OPMODE & WIFI_AP_STATE); +#ifdef SUPPORT_MONITOR + stop_monitor_mode(priv); +#endif + printk("set_mode = IW_MODE_MASTER\n"); +// setopmode_cmd(padapter, networkType); + break; + case IW_MODE_INFRA: // 2 + OPMODE_VAL(OPMODE & WIFI_STATION_STATE); + printk("set_mode = IW_MODE_INFRA\n"); + break; +#ifdef SUPPORT_MONITOR + case IW_MODE_MONITOR: + OPMODE_VAL(OPMODE | WIFI_SITE_MONITOR); + start_monitor_mode(priv); + panic_printk("set_mode = IW_MODE_MONITOR\n"); + break; +#endif + default : + ret = -EINVAL; + } + + return ret; + +} + +int rtl_giwmode(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (OPMODE & WIFI_AP_STATE) + wrqu->mode = IW_MODE_MASTER; + else if (OPMODE & WIFI_STATION_STATE) + wrqu->mode = IW_MODE_INFRA; + else if (OPMODE & WIFI_ADHOC_STATE) + wrqu->mode = IW_MODE_ADHOC; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) + else if (OPMODE & WIFI_SITE_MONITOR) + wrqu->mode = IW_MODE_MONITOR; +#endif + else + wrqu->mode = IW_MODE_AUTO; + + return 0; +} + +#define MAX_FRAG_THRESHOLD 2346 +#define MIN_FRAG_THRESHOLD 256 + +int rtl_giwrange(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_range *range = (struct iw_range *)extra; + int i; + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL || range == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + wrqu->data.length = sizeof(*range); + memset(range, 0, sizeof(*range)); + + /* Let's try to keep this struct in the same order as in + * linux/include/wireless.h + */ + + /* TODO: See what values we can set, and remove the ones we can't + * set, or fill them with some default data. + */ + + /* ~5 Mb/s real (802.11b) */ + range->throughput = 5 * 1000 * 1000; + + // TODO: Not used in 802.11b? +// range->min_nwid; /* Minimal NWID we are able to set */ + // TODO: Not used in 802.11b? +// range->max_nwid; /* Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ +// range->old_num_channels; +// range->old_num_frequency; +// range->old_freq[6]; /* Filler to keep "version" at the same offset */ + + /* signal level threshold range */ + + + //percent values between 0 and 100. + range->max_qual.qual = 100; + //range->max_qual.level = 100; + //range->max_qual.noise = 100; + range->max_qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; /* Updated only qual b'coz not sure */ + + + range->avg_qual.qual = 60; + /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ + //range->avg_qual.level = 20; + //range->avg_qual.noise = 0; + range->avg_qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; /* Updated only qual b'coz not sure */ + + range->num_bitrates = AP_BSSRATE_LEN; + + for(i=0; ibitrate[i] = (AP_BSSRATE[i]&0x7f)* 500000; + } + + range->min_frag = MIN_FRAG_THRESHOLD; + range->max_frag = MAX_FRAG_THRESHOLD; + + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 12; + +// range->retry_capa; /* What retry options are supported */ +// range->retry_flags; /* How to decode max/min retry limit */ +// range->r_time_flags; /* How to decode max/min retry life */ +// range->min_retry; /* Minimal number of retries */ +// range->max_retry; /* Maximal number of retries */ +// range->min_r_time; /* Minimal retry lifetime */ +// range->max_r_time; /* Maximal retry lifetime */ + + range->encoding_size[0]=5; + range->encoding_size[1]=13; + range->num_encoding_sizes = 2; + range->max_encoding_tokens = 4; + range->num_channels = priv->available_chnl_num; + range->num_frequency = priv->available_chnl_num; + + for (i = 0; i < priv->available_chnl_num && i < IW_MAX_FREQUENCIES; i++) { + u32 m = 0; + range->freq[i].i = i + 1; + //range->freq[val].m = CH_HZ_ID_MAP[i].freqKHz * 100000; + MAP_CHANNEL_ID_TO_KHZ(priv->available_chnl[i], m); + range->freq[i].m = m* 100; + range->freq[i].e = 1; + } + +// Commented by Albert 2009/10/13 +// The following code will proivde the security capability to network manager. +// If the driver doesn't provide this capability to network manager, +// the WPA/WPA2 routers can't be choosen in the network manager. + +/* +#define IW_SCAN_CAPA_NONE 0x00 +#define IW_SCAN_CAPA_ESSID 0x01 +#define IW_SCAN_CAPA_BSSID 0x02 +#define IW_SCAN_CAPA_CHANNEL 0x04 +#define IW_SCAN_CAPA_MODE 0x08 +#define IW_SCAN_CAPA_RATE 0x10 +#define IW_SCAN_CAPA_TYPE 0x20 +#define IW_SCAN_CAPA_TIME 0x40 +*/ + +#if WIRELESS_EXT > 17 + range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| + IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; +#endif + +#ifdef IW_SCAN_CAPA_ESSID + range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID| + IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE; +#endif + return 0; +} + +#ifdef WIFI_WPAS_CLI +int rtl_siwap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) { + memset(&priv->pmib->dot11OperationEntry.hwaddr, 0, WLAN_ADDR_LEN); + memcpy(&priv->pmib->dot11OperationEntry.hwaddr, wrqu->ap_addr.sa_data, MACADDRLEN); + clean_for_join(priv); + return 0; + } +#if defined (WIFI_WPAS)//_Eric ?? + else if ( (priv->pmib->dot11OperationEntry.opmode & WIFI_STATION_STATE) || + (priv->pmib->dot11OperationEntry.opmode & WIFI_ADHOC_STATE) ) + { + unsigned char null_mac[] = {0,0,0,0,0,0}; + struct bss_desc bss_desp; + + if ( memcmp(wrqu->ap_addr.sa_data, null_mac, MACADDRLEN) ) { + int i, found=0, ret=0; + for(i = 0 ; i < priv->site_survey->count_backup ; i++) + { + if(!memcmp(priv->site_survey->bss_backup[i].bssid , wrqu->ap_addr.sa_data, MACADDRLEN)) + { + memcpy((void *)&bss_desp, + (void *)&priv->site_survey->bss_backup[i], sizeof(struct bss_desc)); + found = 1; + break; + } + } + + if(found == 0) { + printk("BSSID NOT Found !!\n"); + } else { + ret = rtl_wx_join(priv, &bss_desp); + if(ret != 0) + printk("cliW: rtl_wpas_join Failed: err:%d !!\n", ret); + } + } + return 0; + } +#endif + else + return -EOPNOTSUPP; +} + +#else // !WIFI_WPAS_CLI +int rtl_siwap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) { + memset(&priv->pmib->dot11OperationEntry.hwaddr, 0, WLAN_ADDR_LEN); + memcpy(&priv->pmib->dot11OperationEntry.hwaddr, wrqu->ap_addr.sa_data, MACADDRLEN); + return 0; + } else { +#ifdef WIFI_WPAS //_Eric ?? + if ( (priv->pmib->dot11OperationEntry.opmode & WIFI_STATION_STATE) || + (priv->pmib->dot11OperationEntry.opmode & WIFI_ADHOC_STATE) ) + { + memset(&priv->pmib->dot11Bss.bssid, 0, WLAN_ADDR_LEN); + memcpy(&priv->pmib->dot11Bss.bssid, wrqu->ap_addr.sa_data, MACADDRLEN); + return 0; + } + else + return -EOPNOTSUPP; +#else + //memset(&priv->pmib->dot11Bss.bssid, 0, WLAN_ADDR_LEN); + //memcpy(&priv->pmib->dot11Bss.bssid, ap_addr->sa_data, MACADDRLEN); + return -EOPNOTSUPP; +#endif + } + +} +#endif // WIFI_WPAS_CLI + +int rtl_giwap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + wrqu->ap_addr.sa_family = ARPHRD_ETHER; + if (priv->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) + memcpy(wrqu->ap_addr.sa_data, priv->pmib->dot11OperationEntry.hwaddr, MACADDRLEN); + else + memcpy(wrqu->ap_addr.sa_data, priv->pmib->dot11Bss.bssid, MACADDRLEN); + + return 0; +} + +int rtl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + struct sockaddr addr[IW_MAX_AP]; + struct iw_quality qual[IW_MAX_AP]; + int i; + struct list_head *phead, *plist; + struct stat_info *pstat; +#ifdef SMP_SYNC + unsigned long flags = 0; +#endif + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + i = 0; + phead = &priv->asoc_list; + + SMP_LOCK_ASOC_LIST(flags); + + plist = phead->next; + while (plist != phead && i < IW_MAX_AP) { + pstat = list_entry(plist, struct stat_info, asoc_list); + addr[i].sa_family = ARPHRD_ETHER; + memcpy(addr[i].sa_data, &pstat->hwaddr, WLAN_ADDR_LEN); + + qual[i].qual = pstat->rssi; + //qual[i].level = pstat->sq; + //qual[i].noise = 0 + qual[i].updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; + + plist = plist->next; + i++; + } + + SMP_UNLOCK_ASOC_LIST(flags); + + data->length = i; + memcpy(extra, &addr, i*sizeof(addr[0])); + data->flags = 1; /* signal quality present (sort of) */ + memcpy(extra + i*sizeof(addr[0]), &qual, i*sizeof(qual[i])); + + return 0; +} + +int rtl_siwessid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *essid) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + char str[100]; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) + return -ENETDOWN; +#endif + +#ifdef WIFI_WPAS_CLI + if (!memcmp(priv->pmib->dot11Bss.bssid, NULL_MAC_ADDR, MACADDRLEN)) + return 0; +#endif + + snprintf(str, sizeof(str), "ssid=%s", essid); + return set_mib(priv, str); +} + +int rtl_giwessid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *essid) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + wrqu->essid.flags = 1; + wrqu->essid.length = SSID_LEN; + memcpy(essid, SSID, SSID_LEN); + + return 0; +} + +int rtl_siwrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + UINT32 rate = wrqu->bitrate.value, fixed = wrqu->bitrate.fixed; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + //printk("rtl_siwrate::(rate = %d, fixed = %d)\n", rate, fixed); + /* rate = -1 => auto rate + rate = X, fixed = 1 => (fixed rate X) + */ + + if (rate == -1) + { + //Auto Rate + priv->pmib->dot11StationConfigEntry.autoRate = TRUE; + priv->pmib->dot11StationConfigEntry.fixedTxRate = 0; + } + else + { + if (fixed) + { + unsigned int txRate = rate / 10000000; + int i, len; + unsigned char *rateset, *p; + rateset = AP_BSSRATE; + len = AP_BSSRATE_LEN; + + for(i=0,p=rateset; ipmib->dot11StationConfigEntry.autoRate = FALSE; + priv->pmib->dot11StationConfigEntry.fixedTxRate = *p; + return 0; + } + } + return -EOPNOTSUPP; + + } + else + { + // TODO: rate = X, fixed = 0 => (rates <= X) + return -EOPNOTSUPP; + } + } + + return 0; +} + +int rtl_giwrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned int txRate; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (priv->pmib->dot11StationConfigEntry.autoRate) + txRate = find_rate(priv, NULL, 1, 0); + else + txRate = get_rate_from_bit_value(priv->pmib->dot11StationConfigEntry.fixedTxRate); + + //printk ("txRate = %d\n", txRate); + wrqu->bitrate.value = txRate * 1000000; + wrqu->bitrate.disabled = 0; + + return 0; +} + +#define MAX_RTS_THRESHOLD 2347 + +int rtl_siwrts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + u16 val; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (wrqu->rts.disabled) + val = MAX_RTS_THRESHOLD; + else if (wrqu->rts.value < 0 || wrqu->rts.value > MAX_RTS_THRESHOLD) + return -EINVAL; + else if (wrqu->rts.value == 0) + val = MAX_RTS_THRESHOLD; + else + val = wrqu->rts.value; + + if (val != RTSTHRSLD) + RTSTHRSLD = val; + + return 0; +} + +int rtl_giwrts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + wrqu->rts.value = RTSTHRSLD; + wrqu->rts.disabled = (wrqu->rts.value == MAX_RTS_THRESHOLD); + wrqu->rts.fixed = 1; + + return 0; +} + +int rtl_siwfrag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + u16 val; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if (wrqu->frag.disabled) + val = MAX_FRAG_THRESHOLD; + else if (wrqu->frag.value >= MIN_FRAG_THRESHOLD || wrqu->frag.value <= MAX_FRAG_THRESHOLD) + val = __cpu_to_le16(wrqu->frag.value & ~0x1); /* even numbers only */ + else if (wrqu->frag.value == 0) + val = MAX_FRAG_THRESHOLD; + else + return -EINVAL; + + FRAGTHRSLD = val; + + return 0; +} + +int rtl_giwfrag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + + wrqu->frag.value = FRAGTHRSLD; + wrqu->frag.disabled = (wrqu->frag.value == MAX_FRAG_THRESHOLD); + wrqu->frag.fixed = 1; + + return 0; +} + + +int rtl_siwretry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + priv->pmib->dot11OperationEntry.dot11ShortRetryLimit = wrqu->retry.value; + + return 0; +} + + +int rtl_giwretry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + wrqu->retry.value = priv->pmib->dot11OperationEntry.dot11ShortRetryLimit; + wrqu->retry.fixed = 0; /* no auto select */ + wrqu->retry.flags |= (IW_RETRY_LIMIT |IW_RETRY_ON); + wrqu->retry.disabled = 0; + + return 0; +} + +int rtl_siwencode(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + u32 key, ret = 0; + u32 keyindex_provided; + int i; +// NDIS_802_11_WEP wep; +// NDIS_802_11_AUTHENTICATION_MODE authmode; + + struct iw_point *erq = &(wrqu->encoding); + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + printk("rtl_siwencode: erq->flags=0x%x erq->length=%d keybuf=%02x%02x%02x%02x%02x\n", erq->flags, erq->length, + keybuf[0],keybuf[1],keybuf[2],keybuf[3],keybuf[4]); + + if (erq->flags & IW_ENCODE_DISABLED) + { + printk("rtl_siwencode: EncryptionDisabled\n"); + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + goto exit; + } + + key = erq->flags & IW_ENCODE_INDEX; + + if (key) { + if (key > 4) + return -EINVAL; + key--; + keyindex_provided = 1; + } + else + { + keyindex_provided = 0; + key = priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex; + printk("rtl_siwencode, key=%d\n", key); + } + + //set authentication mode + if (erq->flags & IW_ENCODE_OPEN) + { + printk("rtl_siwencode: IW_ENCODE_OPEN\n"); + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + } + else if (erq->flags & IW_ENCODE_RESTRICTED) + { + printk("rtl_siwencode: IW_ENCODE_RESTRICTED\n"); + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 1; //shared system + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + } + else + { + printk("rtl_siwencode: IW_ENCODE_OPEN\n"); + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; //open system + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + } + + priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex = key; + + if (erq->length > 0) { + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = erq->length <= 5 ? _WEP_40_PRIVACY_ : _WEP_104_PRIVACY_; + priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = erq->length <= 5 ? 8 : 16; + } else { + + if (keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0). + { + printk("rtl_siwencode: keyindex provided, keyid=%d, key_len=%d\n", key, erq->length); + + switch (priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen) + { + case 5: + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; + break; + case 13: + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; + break; + default: + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + break; + } + + goto exit; + } + } + +#ifdef WIFI_WPAS_CLI + memcpy(priv->pmib->dot11DefaultKeysTable.keytype[key].skey, keybuf, erq->length); + CamAddOneEntry(priv, priv->pmib->dot11Bss.bssid, key, + (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm)<<2, + 0, priv->pmib->dot11DefaultKeysTable.keytype[key].skey); +#else + for (i=0; i<4; i++) { + memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[i].skey[0], keybuf, erq->length); + } +#endif + +exit: + + return ret; +} + + +int rtl_giwencode(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_point *erq = &(wrqu->encoding); + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + +#ifndef WIFI_HAPD + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } +#endif + + if ((OPMODE & (WIFI_AP_STATE|WIFI_STATION_STATE|WIFI_ADHOC_STATE)) && + !priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm && + (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_ || + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_)) { + int key_len; + priv->pmib->dot11GroupKeysTable.dot11Privacy = priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm; + if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) + key_len = 5; + else + key_len = 13; + + // copy wep key + erq->flags = (priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex + 1) & IW_ENCODE_INDEX; + erq->length = key_len; + memcpy(key, &priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0], key_len); + + if (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm == 1) + erq->flags |= IW_ENCODE_RESTRICTED; /* XXX */ + else + erq->flags |= IW_ENCODE_OPEN; /* XXX */ + + erq->flags |= IW_ENCODE_ENABLED; /* XXX */ + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _NO_PRIVACY_) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } + + return 0; +} + +int rtl_giwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + //_adapter *padapter = netdev_priv(dev); + + wrqu->power.value = 0; + wrqu->power.fixed = 0; /* no auto select */ + wrqu->power.disabled = 1; + + return 0; +} + +#ifdef WIFI_WPAS_CLI +int rtl_siwscan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_point *data = &wrqu->data; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) + return -ENETDOWN; +#endif + + // TODO: If traffic is busy, we may need to skip this scanning + if ( OPMODE & WIFI_ASOC_STATE ) { + printk("cliW: try scanning in association\n"); + goto ind_done; + } + if ( OPMODE & ( WIFI_AUTH_STATE1 | WIFI_AUTH_SUCCESS) ) { + printk("cliW: no scanning when connecting\n"); + goto ind_done; + } + + if (data && (data->flags & IW_SCAN_THIS_ESSID)) { + struct iw_scan_req* req = (struct iw_scan_req*)extra; + + if (req->essid_len) + { + priv->ss_ssidlen = req->essid_len; + if (priv->ss_ssidlen > 32) + priv->ss_ssidlen = 32; + + memset(priv->ss_ssid, 0, 32); + memcpy(priv->ss_ssid, req->essid, priv->ss_ssidlen); + + SSID2SCAN_LEN = (req->essid_len > 32) ? 32 : req->essid_len; + memcpy(SSID2SCAN, req->essid, SSID2SCAN_LEN); + + use_ap_scan(priv); + } + } else { + printk("cliW: wildcard ssid \n"); + priv->ss_ssidlen = 0; + use_ap_scan(priv); + } +done: + return 0; + +ind_done: + event_indicate_wpas(priv, NULL, WPAS_SCAN_DONE, NULL); + return 0; +} +#else // !WIFI_WPAS_CLI +int rtl_siwscan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + INT8 ret=-1; + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned long flags; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } + ret=rtl8192cd_ss_req(priv, (unsigned char *) &wrqu->data, 0); + if(0!=wrqu->data.length) + { + if(extra!=NULL && (!strcmp(extra,"rtl8192cd_ioctl")))//called from rtl8192cd_ioctl + { + #ifdef WIFI_WPAS //_Eric ?? + if (ioctl_copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) + memcpy(wrqu->data.pointer, &ret, 1); + #else + if (ioctl_copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) + return -1; + #endif + } + else //called from iwhandler. + { + #ifdef WIFI_WPAS //_Eric ?? + if (copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) + memcpy(wrqu->data.pointer, &ret, 1); + #else + if (copy_to_user((void *)wrqu->data.pointer, (void *)&ret, 1)) + return -1; + #endif + + } + } + + //wait ss done + wait_event_interruptible_timeout(priv->ss_wait,(!priv->ss_req_ongoing),RTL_SECONDS_TO_JIFFIES(5)); + return 0; +} +#endif // WIFI_WPAS_CLI + +#ifdef WIFI_WPAS //_Eric ?? AP mode (HAPD) will attemp to scan or not ?? +int rtl_giwscan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + int i=0, j=0; + char * current_ev = extra; + char * previous_ev = extra; + char * end_buf; + char * current_val; +#ifndef IWEVGENIE + unsigned char idx; +#endif // IWEVGENIE // + struct iw_event iwe; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + //check if the interface is down + if (!netif_running(priv->dev)) + { + printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + if ((TRUE == priv->pshare->bDriverStopped) || (TRUE == priv->pshare->bSurpriseRemoved)) { + printk("cliw: driver shutdown now\n"); + return -ENETDOWN; + } +#endif + + if (priv->site_survey->count_backup== 0) + { + wrqu->data.length = 0; + return 0; + } + +#if WIRELESS_EXT >= 17 + if (wrqu->data.length > 0) + end_buf = extra + wrqu->data.length; + else + end_buf = extra + IW_SCAN_MAX_DATA; +#else + end_buf = extra + IW_SCAN_MAX_DATA; +#endif + + for (i = 0; i < priv->site_survey->count_backup; i++) + { + + if( (wrqu->data.length - (current_ev - extra)) <= 200) + break; //_Eric TEST + + if (current_ev >= end_buf) + { +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + + //MAC address + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + memcpy(iwe.u.ap_addr.sa_data, priv->site_survey->bss_backup[i].bssid, MACADDRLEN); + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + /* + Protocol: + it will show scanned AP's WirelessMode . + it might be + 802.11a + 802.11a/n + 802.11g/n + 802.11b/g/n + 802.11g + 802.11b/g + */ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; + + { + struct bss_desc *pBss=&priv->site_survey->bss_backup[i]; + //int rateCnt=0; + + if (pBss->network==WIRELESS_11B) + strcpy(iwe.u.name, "802.11b"); + else if (pBss->network==WIRELESS_11G) + strcpy(iwe.u.name, "802.11g"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11B)) + strcpy(iwe.u.name, "802.11b/g"); + else if (pBss->network==(WIRELESS_11N)) + strcpy(iwe.u.name, "802.11n"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11N)) + strcpy(iwe.u.name, "802.11g/n"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11B | WIRELESS_11N)) + strcpy(iwe.u.name, "802.11b/g/n"); + else if(pBss->network== WIRELESS_11A) + strcpy(iwe.u.name, "802.11a"); + else + strcpy(iwe.u.name, "---"); + } + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //ESSID + //================================ + memset(&iwe, 0, sizeof(iwe)); + + //printk("ESSID %s %d\n",priv->site_survey->bss_backup[i].ssid, priv->site_survey->bss_backup[i].ssidlen); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.length = (priv->site_survey->bss_backup[i].ssidlen <= 32) ? priv->site_survey->bss_backup[i].ssidlen : 32; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].ssid); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //Network Type + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + if (priv->site_survey->bss_backup[i].bsstype & WIFI_ADHOC_STATE) + { + iwe.u.mode = IW_MODE_ADHOC; + } + else if (priv->site_survey->bss_backup[i].bsstype & WIFI_STATION_STATE) + { + iwe.u.mode = IW_MODE_INFRA; + } + else if (priv->site_survey->bss_backup[i].bsstype & WIFI_AP_STATE) + { + iwe.u.mode = IW_MODE_MASTER; + } + else + { + iwe.u.mode = IW_MODE_AUTO; + } + iwe.len = IW_EV_UINT_LEN; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_UINT_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //Channel and Frequency + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + { + u8 ch = priv->site_survey->bss_backup[i].channel; + u32 m = 0; + + MAP_CHANNEL_ID_TO_KHZ(ch, m); + iwe.u.freq.m = m; + iwe.u.freq.e = 3; + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_FREQ_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + + //Add quality statistics + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + iwe.u.qual.level = priv->site_survey->bss_backup[i].rssi - 100; + iwe.u.qual.qual = priv->site_survey->bss_backup[i].sq; + iwe.u.qual.noise = 0; /* cliW */ + + // not sure about signal level and noise level + //iwe.u.qual.noise = signal_todbm((u8)(100-priv->site_survey->bss[i].rssi)) -25; +// iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; + iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED | IW_QUAL_NOISE_INVALID | IW_QUAL_DBM ; + + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + #define WLAN_CAPABILITY_PRIVACY (1<<4) + + // Encryption capability + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (priv->site_survey->bss_backup[i].capability & WLAN_CAPABILITY_PRIVACY) // if Privacy + iwe.u.data.flags =IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe.u.data.flags = IW_ENCODE_DISABLED; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf,&iwe, (u8 *)&priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0]); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + // support rate + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + + for (j=0; dot11_rate_table[j]; j++) + { + if (priv->site_survey->bss_backup[i].supportrate & (BIT(j))) + { + iwe.u.bitrate.value = dot11_rate_table[j]*500000; + current_val = IWE_STREAM_ADD_VALUE(info, current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); + } + } + + if (priv->site_survey->bss_backup[i].network & WIRELESS_11N) + { + // TODO: Report MCS Rate + } + + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + + + +//WIFI_WPAS ++ +//WPAIE + //================================ +/*cfg p2p cfg p2p*/ + if(priv->site_survey->bss_backup[i].wpa_ie_len > 0){ + memset(&iwe, 0, sizeof(iwe)); + + iwe.cmd = IWEVGENIE; + iwe.u.data.length = priv->site_survey->bss_backup[i].wpa_ie_len; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].wpa_ie); + if (current_ev == previous_ev) { +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + } +/*cfg p2p cfg p2p*/ +//RSNIE + //================================ + if(priv->site_survey->bss_backup[i].rsn_ie_len > 0) { + memset(&iwe, 0, sizeof(iwe)); + + iwe.cmd = IWEVGENIE; + iwe.u.data.length = priv->site_survey->bss_backup[i].rsn_ie_len; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss_backup[i].rsn_ie); + if (current_ev == previous_ev) { +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + } +/*cfg p2p cfg p2p*/ +#ifdef WIFI_SIMPLE_CONFIG + //WPSIE + //================================ + if (priv->site_survey->bss_backup[i].t_stamp[1] & BIT(8)) { + memset(&iwe, 0, sizeof(iwe)); + + iwe.cmd = IWEVGENIE; + iwe.u.data.length = priv->site_survey->wscie[i].wps_ie_len; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->wscie[i].data); + if (current_ev == previous_ev) { +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + } +#endif // WIFI_SIMPLE_CONFIG + +//WIFI_WPAS -- + + } + + wrqu->data.length = current_ev - extra; + + return 0; +} + +#else +int rtl_giwscan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + int i=0; + char * current_ev = extra; + char * previous_ev = extra; + char * end_buf; + //char * current_val; +#ifndef IWEVGENIE + unsigned char idx; +#endif // IWEVGENIE // + struct iw_event iwe; + + if (priv == NULL) + { + /* if 1st open fail, pAd will be free; + So the net_dev->priv will be NULL in 2rd open */ + return -ENETDOWN; + } + + //check if the interface is down + if (!netif_running(priv->dev)) + { + //printk("\nFail: interface not opened\n"); + return -ENETDOWN; + } + + if (priv->site_survey->count == 0) + { + wrqu->data.length = 0; + return 0; + } + +#if WIRELESS_EXT >= 17 + if (wrqu->data.length > 0) + end_buf = extra + wrqu->data.length; + else + end_buf = extra + IW_SCAN_MAX_DATA; +#else + end_buf = extra + IW_SCAN_MAX_DATA; +#endif + + for (i = 0; i < priv->site_survey->count; i++) + { + if (current_ev >= end_buf) + { +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + + //MAC address + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + memcpy(iwe.u.ap_addr.sa_data, &priv->site_survey->bss[i].bssid, MACADDRLEN); + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + /* + Protocol: + it will show scanned AP's WirelessMode . + it might be + 802.11a + 802.11a/n + 802.11g/n + 802.11b/g/n + 802.11g + 802.11b/g + */ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; + + { + struct bss_desc *pBss=&priv->site_survey->bss[i]; + //int rateCnt=0; + + if (pBss->network==WIRELESS_11B) + strcpy(iwe.u.name, "802.11b"); + else if (pBss->network==WIRELESS_11G) + strcpy(iwe.u.name, "802.11g"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11B)) + strcpy(iwe.u.name, "802.11b/g"); + else if (pBss->network==(WIRELESS_11N)) + strcpy(iwe.u.name, "802.11n"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11N)) + strcpy(iwe.u.name, "802.11g/n"); + else if (pBss->network==(WIRELESS_11G|WIRELESS_11B | WIRELESS_11N)) + strcpy(iwe.u.name, "802.11b/g/n"); + else if(pBss->network== WIRELESS_11A) + strcpy(iwe.u.name, "802.11a"); + else + strcpy(iwe.u.name, "---"); + } + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_ADDR_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //ESSID + //================================ + memset(&iwe, 0, sizeof(iwe)); + + //printk("ESSID %s %d\n",priv->site_survey->bss[i].ssid, priv->site_survey->bss[i].ssidlen); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.length = priv->site_survey->bss[i].ssidlen; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].ssid); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //Network Type + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + if (priv->site_survey->bss[i].bsstype & WIFI_ADHOC_STATE) + { + iwe.u.mode = IW_MODE_ADHOC; + } + else if (priv->site_survey->bss[i].bsstype & WIFI_STATION_STATE) + { + iwe.u.mode = IW_MODE_INFRA; + } + else if (priv->site_survey->bss[i].bsstype & WIFI_AP_STATE) + { + iwe.u.mode = IW_MODE_MASTER; + } + else + { + iwe.u.mode = IW_MODE_AUTO; + } + iwe.len = IW_EV_UINT_LEN; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_UINT_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + + //Channel and Frequency + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + { + u8 ch = priv->site_survey->bss[i].channel; + //u32 m = 0; + //MAP_CHANNEL_ID_TO_KHZ(ch, m); + //iwe.u.freq.m = m * 100; + //iwe.u.freq.e = 1; + iwe.u.freq.m = ch; + iwe.u.freq.e = 0; + iwe.u.freq.i = 0; + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev,end_buf, &iwe, IW_EV_FREQ_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + + //Add quality statistics + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + iwe.u.qual.qual = priv->site_survey->bss[i].rssi; + + // not sure about signal level and noise level + //iwe.u.qual.level = (u8) priv->site_survey->bss[i].sq; + //iwe.u.qual.noise = signal_todbm((u8)(100-priv->site_survey->bss[i].rssi)) -25; + iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_INVALID | IW_QUAL_NOISE_INVALID; + + current_ev = IWE_STREAM_ADD_EVENT(info, current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif +#if 0 + //Encyption key + //================================ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (priv->site_survey->bss[i].capability & 0x0010) + iwe.u.data.flags =IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe.u.data.flags = IW_ENCODE_DISABLED; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf,&iwe, (u8 *)priv->pmib->dot11DefaultKeysTable.keytype[priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex].skey[0]); + if (current_ev == previous_ev) +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif +#endif + //WPAIE + if(priv->site_survey->bss[i].wpa_ie_len > 0){ + memset(&iwe, 0, sizeof(iwe)); + + iwe.cmd = IWEVGENIE; + iwe.u.data.length = priv->site_survey->bss[i].wpa_ie_len; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].wpa_ie); + if (current_ev == previous_ev){ +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + } + //RSNIE + if(priv->site_survey->bss[i].rsn_ie_len > 0){ + memset(&iwe, 0, sizeof(iwe)); + + iwe.cmd = IWEVGENIE; + iwe.u.data.length = priv->site_survey->bss[i].rsn_ie_len; + iwe.u.data.flags = 1; + + previous_ev = current_ev; + current_ev = IWE_STREAM_ADD_POINT(info, current_ev, end_buf, &iwe, (char *)priv->site_survey->bss[i].rsn_ie); + if (current_ev == previous_ev){ + panic_printk("Add point fail %s %d\n", __FUNCTION__, __LINE__); +#if WIRELESS_EXT >= 17 + return -E2BIG; +#else + break; +#endif + } + } + + } + + wrqu->data.length = current_ev - extra; + return 0; +} +#endif + +#ifdef WIFI_WPAS_CLI +const u1Byte WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; +const u1Byte WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; +const u1Byte WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; +const u1Byte WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; +const u1Byte WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; +const u1Byte WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; + +const u1Byte RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; +const u1Byte RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; +const u1Byte RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; +//const u1Byte RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; +const u1Byte RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; +const u1Byte RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; + +unsigned char rtw_get_wpa_cipher_suite(u1Byte *s) +{ + unsigned char cipher = 0; + + if (memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == 0) + cipher = _NO_PRIVACY_; + else if (memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == 0) + cipher = _WEP_40_PRIVACY_; + else if (memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == 0) + cipher = _TKIP_PRIVACY_; + else if (memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == 0) + cipher = _CCMP_PRIVACY_; + else if (memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == 0) + cipher = _WEP_104_PRIVACY_; + + return cipher; +} + +unsigned char rtw_get_wpa2_cipher_suite(u1Byte *s) +{ + unsigned char cipher = 0; + + if (memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == 0) + cipher = _NO_PRIVACY_; + else if (memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == 0) + cipher = _WEP_40_PRIVACY_; + else if (memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == 0) + cipher = _TKIP_PRIVACY_; + else if (memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == 0) + cipher = _CCMP_PRIVACY_; + else if (memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == 0) + cipher = _WEP_104_PRIVACY_; + + return cipher; +} + +int rtw_parse_wpa_ie(u1Byte* wpa_ie, int wpa_ie_len, unsigned char *group_cipher, unsigned char *pairwise_cipher) +{ + int i, ret=0; + int left, count; + pu1Byte pos; + + if (wpa_ie_len <= 0) { + /* No WPA IE - fail silently */ + return 1; + } + + if ((*wpa_ie != WPA_IE_ID) || (*(wpa_ie+1) != (u1Byte)(wpa_ie_len - 2)) || + (memcmp(wpa_ie+2, WPA_OUI_TYPE, WPA_SELECTOR_LEN) != 0) ) + { + return 1; + } + + pos = wpa_ie; + + pos += 8; + left = wpa_ie_len - 8; + + + //group_cipher + if (left >= WPA_SELECTOR_LEN) + { + *group_cipher = rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + } + else if (left > 0) + { + DEBUG_INFO("%s: ie length mismatch, %u too much", __FUNCTION__, left); + return 1; + } + + + //pairwise_cipher + if (left >= 2) + { + count = le16_to_cpu(*(u2Byte*)pos);// + pos += 2; + left -= 2; + + if (count == 0 || left < count * WPA_SELECTOR_LEN) { + DEBUG_INFO("%s: ie count botch (pairwise), " + "count %u left %u", __FUNCTION__, count, left); + return 1; + } + + for (i = 0; i < count; i++) + { + *pairwise_cipher = rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + } + + } + else if (left == 1) + { + DEBUG_INFO("%s: ie too short (for key mgmt)", __FUNCTION__); + return 1; + } + + + return ret; + +} + +int rtw_parse_wpa2_ie(u1Byte* rsn_ie, int rsn_ie_len, unsigned char *group_cipher, unsigned char *pairwise_cipher) +{ + int i, ret=0; + int left, count; + u1Byte *pos; + + if (rsn_ie_len <= 0) + { + /* No RSN IE - fail silently */ + return 1; + } + + + if ((*rsn_ie!= WPA2_IE_ID) || (*(rsn_ie+1) != (u1Byte)(rsn_ie_len - 2))) + { + return 1; + } + + pos = rsn_ie; + pos += 4; + left = rsn_ie_len - 4; + + //group_cipher + if (left >= RSN_SELECTOR_LEN) { + + *group_cipher = rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + + } else if (left > 0) { + DEBUG_INFO("%s: ie length mismatch, %u too much", __FUNCTION__, left); + return 1; + } + + //pairwise_cipher + if (left >= 2) + { + count = le16_to_cpu(*(u16*)pos);// + pos += 2; + left -= 2; + + if (count == 0 || left < count * RSN_SELECTOR_LEN) { + DEBUG_INFO("%s: ie count botch (pairwise), " + "count %u left %u", __FUNCTION__, count, left); + return 1; + } + + for (i = 0; i < count; i++) + { + *pairwise_cipher = rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + } + + } + else if (left == 1) + { + DEBUG_INFO("%s: ie too short (for key mgmt)", __FUNCTION__); + + return 1; + } + + return ret; + +} + +void rtw_set_wpa_cipher_bit(struct rtl8192cd_priv *priv, unsigned char enc_type) +{ + switch (enc_type) { + case _WEP_40_PRIVACY_: + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(0); + break; + + case _TKIP_PRIVACY_: + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(1); + break; + + case _WRAP_PRIVACY_: + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(2); + break; + + case _CCMP_PRIVACY_: + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(3); + break; + + case _WEP_104_PRIVACY_: + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(4); + break; + + default: + break; + } +} + + +int rtl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + u1Byte *buf=NULL; + unsigned char group_cipher = 0, pairwise_cipher = 0; + int ret = 0; + u2Byte ielen; + WPA_GLOBAL_INFO *pGblInfo = priv->wpa_global_info; + + DEBUG_INFO("%s:IE_Len=%d\n", __FUNCTION__, wrqu->data.length); + + ielen = wrqu->data.length; + if((ielen > MAX_WPA_IE_LEN) || (extra == NULL)){ + priv->pmib->wscEntry.wsc_enable = 0; + priv->pmib->wscEntry.assoc_ielen = 0; + if(extra == NULL) + return ret; + else + return -EINVAL; + } + + printk("rtl_siwgenie\n"); + + if ( ielen == 0 ) { + priv->pmib->dot11RsnIE.rsnielen = 0; + } else { +#if 0 + if (wrqu->data.length < sizeof(DOT11_RSN_IE_HEADER)) + { + DEBUG_ERR("Invalid IE Length(%d) or Null data pointer\n", wrqu->data.length); + return -EINVAL; + } +#endif + buf = kzalloc(ielen, GFP_KERNEL); + if (buf == NULL){ + return -ENOMEM; + } + + memcpy(buf, extra, ielen); + if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher) == 0) + { + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = pairwise_cipher; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= 1 << (pairwise_cipher-1); + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; + priv->pmib->dot11GroupKeysTable.dot11Privacy = group_cipher; + pGblInfo->MulticastCipher = group_cipher ; + pGblInfo->UnicastCipher[0] = pairwise_cipher ; + + BUG_ON(sizeof(priv->pmib->dot11RsnIE.rsnie) < ielen); + memcpy(priv->pmib->dot11RsnIE.rsnie, &buf[0], ielen); + priv->pmib->dot11RsnIE.rsnielen = ielen; + } + else if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher) == 0) + { + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = pairwise_cipher; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA2; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; + priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= 1 << (pairwise_cipher-1); + priv->pmib->dot11GroupKeysTable.dot11Privacy = group_cipher; + pGblInfo->MulticastCipher = group_cipher ; + pGblInfo->UnicastCipherWPA2[0] = pairwise_cipher; + + BUG_ON(sizeof(priv->pmib->dot11RsnIE.rsnie) < ielen); + memcpy(priv->pmib->dot11RsnIE.rsnie, &buf[0], ielen); + priv->pmib->dot11RsnIE.rsnielen = ielen; + } + + {//set wps_ie + int cnt = 0; + unsigned char wps_ie_found=0; + unsigned char eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; + + while( cnt < ielen ) + { + eid = buf[cnt]; + + if((eid==VENDOR_SPECIFIC_IE)&&(memcmp(&buf[cnt+2], wps_oui, 4)==0)) + { + DEBUG_INFO("%s: SET WPS_IE\n",__FUNCTION__); + priv->pmib->wscEntry.wsc_enable = 1; + priv->pmib->wscEntry.assoc_ielen = ( (buf[cnt+1]+2) < (256)) ? (buf[cnt+1]+2):(256); + memset(priv->pmib->wscEntry.assoc_ie, 0x0, 256); + memcpy(priv->pmib->wscEntry.assoc_ie, &buf[cnt], priv->pmib->wscEntry.assoc_ielen); + wps_ie_found = 1; + break; + } + cnt += buf[cnt+1]+2; //goto next + } + + if (!wps_ie_found) + { + priv->pmib->wscEntry.wsc_enable = 0; + priv->pmib->wscEntry.assoc_ielen = 0; + } + } + + kfree(buf); + } + + return ret; +} + + +int rtl_siwauth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_param *param = (struct iw_param*)&(wrqu->param); + int value = param->value; + int ret = 0; + + printk("rtl_siwauth : cmd:%d val:%d\n", (param->flags & IW_AUTH_INDEX), param->value); + + switch (param->flags & IW_AUTH_INDEX) { + + case IW_AUTH_WPA_VERSION: +#ifdef CONFIG_RTL_WAPI_SUPPORT + priv->pmib->wapiInfo.wapiType = wapiDisable; + if(value == IW_AUTH_WAPI_VERSION_1) + { + priv->pmib->wapiInfo.wapiType = wapiTypePSK; + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == 0; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; + } else +#endif + if (value == IW_AUTH_WPA_VERSION_DISABLED) { + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; + } + else if (value == IW_AUTH_WPA_VERSION_WPA) + { + priv->pmib->wapiInfo.wapiType = wapiDisable; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA; + } + else if (value == IW_AUTH_WPA_VERSION_WPA2) + { + priv->pmib->wapiInfo.wapiType = wapiDisable; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = PSK_WPA2; + } + break; + + case IW_AUTH_CIPHER_PAIRWISE: + DEBUG_INFO("set_auth(IW_AUTH_CIPHER_PAIRWISE) value=%d\n", param->value); + if (param->value & IW_AUTH_CIPHER_WEP40) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; + else if (param->value & IW_AUTH_CIPHER_WEP104) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; + else if (param->value & IW_AUTH_CIPHER_TKIP) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _TKIP_PRIVACY_; + else if (param->value & IW_AUTH_CIPHER_CCMP) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _CCMP_PRIVACY_; + else if (param->value & IW_AUTH_CIPHER_NONE) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + else { + return -EINVAL; + } + break; + + case IW_AUTH_CIPHER_GROUP: + DEBUG_INFO("set_auth(IW_AUTH_CIPHER_GROUP) value=%d\n", value); + + if (value & IW_AUTH_CIPHER_WEP40) + priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_WEP40; + else if (value & IW_AUTH_CIPHER_WEP104) + priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_WEP104; + else if (value & IW_AUTH_CIPHER_TKIP) + priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_TKIP; + else if (value & IW_AUTH_CIPHER_CCMP) + priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_CCMP; + else if (value & IW_AUTH_CIPHER_NONE) + priv->pmib->dot11GroupKeysTable.dot11Privacy = DOT11_ENC_NONE; + else { + return -EINVAL; + } + + break; + + case IW_AUTH_KEY_MGMT: +#ifdef CONFIG_RTL_WAPI_SUPPORT + if (priv->pmib->wapiInfo.wapiType != wapiDisable) + { + if(value == IW_AUTH_KEY_MGMT_WAPI_PSK) + priv->pmib->wapiInfo.wapiType = wapiTypePSK; + else + priv->pmib->wapiInfo.wapiType = wapiTypeCert; + DEBUG_INFO("%s: IW_AUTH_KEY_MGMT wapiType %d \n", __FUNCTION__, priv->pmib->wapiInfo.wapiType); + } else +#endif +#if 0 + if (value & IW_AUTH_KEY_MGMT_802_1X) + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; + else + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; +#endif + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: + // TODO: TKIP countermeasures + break; + + case IW_AUTH_DROP_UNENCRYPTED: + break; + + case IW_AUTH_80211_AUTH_ALG: + if ((param->value & IW_AUTH_ALG_SHARED_KEY)&&(param->value & IW_AUTH_ALG_OPEN_SYSTEM)) + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 2; // Auto + else if(param->value & IW_AUTH_ALG_OPEN_SYSTEM) + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; // Open + else if (param->value & IW_AUTH_ALG_SHARED_KEY) + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 1; // Shared + else if (param->value & IW_AUTH_ALG_LEAP) + { + DEBUG_WARN("%s: wpa_set_auth_algs, AUTH_ALG_LEAP\n", __FUNCTION__); + } + else + ret = -EINVAL; + break; + + case IW_AUTH_WPA_ENABLED: + if ( param->value == 0 ) { + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = 0; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = 0; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 0; + + priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; + priv->pmib->dot11GroupKeysTable.dot11Privacy = 0; + + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; + priv->pmib->dot11RsnIE.rsnielen = 0; + } + + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + //ieee->ieee802_1x = param->value; + break; + + case IW_AUTH_PRIVACY_INVOKED: + //ieee->privacy_invoked = param->value; + break; + +#ifdef CONFIG_RTL_WAPI_SUPPORT + case IW_AUTH_WAPI_ENABLED: + break; +#endif + + default: + return -EOPNOTSUPP; + } + return ret; +} + + +int rtl_giwauth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_param *param = (struct iw_param*)&(wrqu->param); + int ret = 0; + + + DEBUG_INFO("%s: get_auth: flags=0x%x authmode=%d\n", __FUNCTION__, wrq->flags, authmode); + param->value = 0; + + switch (param->flags & IW_AUTH_INDEX) { + case IW_AUTH_WPA_VERSION: +#ifdef CONFIG_RTL_WAPI_SUPPORT + if (priv->pmib->wapiInfo.wapiType != wapiDisable;) + { + param->value |= IW_AUTH_WAPI_VERSION_1; + } +#endif + if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK & PSK_WPA) + { + param->value |= IW_AUTH_WPA_VERSION_WPA; + } + + if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK & PSK_WPA2) + { + param->value |= IW_AUTH_WPA_VERSION_WPA2; + } + break; + + case IW_AUTH_CIPHER_PAIRWISE: + if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) + { + param->value |= IW_AUTH_CIPHER_WEP40; + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) + { + param->value |= IW_AUTH_CIPHER_WEP104; + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _TKIP_PRIVACY_) + { + param->value |= IW_AUTH_CIPHER_TKIP; + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _CCMP_PRIVACY_) + { + param->value |= IW_AUTH_CIPHER_CCMP; + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _NO_PRIVACY_) + { + param->value |= IW_AUTH_CIPHER_NONE; + } + break; + + case IW_AUTH_KEY_MGMT: +#ifdef CONFIG_RTL_WAPI_SUPPORT + if (priv->pmib->wapiInfo.wapiType != wapiDisable) + { + if (priv->pmib->wapiInfo.wapiType == wapiTypePSK) + param->value = IW_AUTH_KEY_MGMT_WAPI_PSK; + else + param->value = IW_AUTH_KEY_MGMT_WAPI_CERT; + } else +#endif + if (priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm) + { + if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) + param->value = IW_AUTH_KEY_MGMT_PSK; + else + param->value = IW_AUTH_KEY_MGMT_802_1X; + } + break; +// TODO:==> + case IW_AUTH_80211_AUTH_ALG: + switch (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm) { + case 0: + param->value = IW_AUTH_ALG_OPEN_SYSTEM; + break; + + case 1: + param->value = IW_AUTH_ALG_OPEN_SYSTEM; + break; + + default: + DEBUG_ERR("%s: invalid auth_alg(%d)\n", __FUNCTION__,priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm); + param->value = IW_AUTH_ALG_OPEN_SYSTEM; + break; + } + break; + + case IW_AUTH_WPA_ENABLED: + // TODO: + break; + + default: + ret = -EOPNOTSUPP; + } + DEBUG_INFO("%s: flags=0x%x value=%d ret=%d\n", __FUNCTION__, param->flags, param->value, ret); + + return ret; +} + + +int rtl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + s4Byte alg = ext->alg; + u1Byte EncAlgorithm = DOT11_ENC_NONE; + s4Byte KeyIndex; + u4Byte KeyLength=0; + BOOLEAN IsDefaultKey = FALSE; + pu1Byte KeyMaterial = ext->key; + BOOLEAN IsGroupKey = FALSE; +// u8Byte KeyRSC; + int ret=0; + DOT11_SET_KEY Set_Key; + struct stat_info *pstat; + + memset((char *)&Set_Key, 0, sizeof(Set_Key)); + + if (encoding->flags & IW_ENCODE_DISABLED) { + alg = IW_ENCODE_ALG_NONE; + } + + /* Get Key Index and convet to our own defined key index */ + KeyIndex = (encoding->flags & IW_ENCODE_INDEX) - 1; + KeyLength = ext->key_len; + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + IsDefaultKey = TRUE; + } + + //if ((ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) || (IS_BCAST(ext->addr.sa_data))) { + if ( (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) ) { + IsGroupKey = TRUE; + } + + printk("siwencode alg:%x ext_flags:%x/ len:%u\n", (u4Byte)alg, ext->ext_flags, KeyLength); + + DEBUG_INFO("%s: \n", __FUNCTION__); + DEBUG_INFO("KeyIndex = %d\n", KeyIndex); + DEBUG_INFO("KeyLength = %u\n", KeyLength); + //DEBUG_INFO("KeyMaterial = %32s\n", KeyMaterial); + DEBUG_INFO("IsDefaultKey = %d\n", IsDefaultKey); + DEBUG_INFO("IsGroupKey = %d\n", IsGroupKey); + + switch (alg) { + case IW_ENCODE_ALG_NONE: + /* Clear all keys */ + EncAlgorithm = DOT11_ENC_NONE; + break; + + case IW_ENCODE_ALG_WEP: + if ((KeyIndex < 0) || (KeyIndex >= 4)) + { + ret = -EINVAL; + goto set_encodeext_end; + } + + if(KeyLength == 5){ + EncAlgorithm = DOT11_ENC_WEP40; + } + else if(KeyLength == 13) { + EncAlgorithm = DOT11_ENC_WEP104; + } + else + { + ret = -EINVAL; + goto set_encodeext_end; + } + + break; + + case IW_ENCODE_ALG_TKIP: + EncAlgorithm = DOT11_ENC_TKIP; + // Check key length for TKIP. + if(KeyLength != 32) { + if (IsGroupKey && (KeyLength == 5 || KeyLength == 13)) { + // 5 = WEP40 13 = WEP104 16 = CKIP + if(KeyLength == 5) { + EncAlgorithm = DOT11_ENC_WEP40; + } else { + EncAlgorithm = DOT11_ENC_WEP104; + } + DEBUG_WARN("%s: Check key length 5 or 13 for Mix-mode WEP.\n", __FUNCTION__); + } else { + DEBUG_ERR("TKIP KeyLength:%u != 32\n", KeyLength); + ret = -EINVAL; + goto set_encodeext_end; + } + } + + break; + + case IW_ENCODE_ALG_CCMP: + EncAlgorithm = DOT11_ENC_CCMP; + if(KeyLength != 16) { + // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. + if(KeyLength == 32) + KeyLength = 16; + } + + if((KeyLength != 16) && (KeyLength != 32)) { + if (IsGroupKey && (KeyLength == 5 || KeyLength == 13)) { + // 5 = WEP40 13 = WEP104 16 = CKIP + if(KeyLength == 5) { + EncAlgorithm = DOT11_ENC_WEP40; + } else { + EncAlgorithm = DOT11_ENC_WEP104; + } + DEBUG_WARN("%s: Check key length 5 or 13 for Mix-mode WEP.\n", __FUNCTION__); + } else { + DEBUG_ERR("AES_CCM KeyLength:%u != 16\n", KeyLength); + ret = -EINVAL; + goto set_encodeext_end; + } + } + break; + + default: + ret = -EINVAL; + goto set_encodeext_end; + } + + if (KeyLength > 0) { + if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { + memcpy(priv->pmib->dot11DefaultKeysTable.keytype[KeyIndex].skey, KeyMaterial, KeyLength); + } + + if (IsDefaultKey) { + if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = KeyLength <= 5 ? _WEP_40_PRIVACY_ : _WEP_104_PRIVACY_; + priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = KeyLength <= 5 ? 8 : 16; + priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyIndex = KeyIndex; + + // don't setup PTK CAM because BSSID is unavailable before first join. + // PTK CAM will be set on set_keymapping_wep when association success. + if (IsGroupKey) { + struct Dot11EncryptKey *pEncryptKey; + + priv->pmib->dot11GroupKeysTable.dot11Privacy = EncAlgorithm; + priv->pmib->dot11GroupKeysTable.keyid = KeyIndex; + + pEncryptKey = &priv->pmib->dot11GroupKeysTable.dot11EncryptKey; + pEncryptKey->dot11TTKeyLen = KeyLength <= 5 ? 5 : 13; + pEncryptKey->dot11TMicKeyLen = 0; + memset(pEncryptKey->dot11TTKey.skey, 0, sizeof(pEncryptKey->dot11TTKey.skey)); + memcpy(pEncryptKey->dot11TTKey.skey, KeyMaterial, pEncryptKey->dot11TTKeyLen); + } + goto set_encodeext_end; + } + } + + if (IsGroupKey) { + /* cliW: not set group key in wep key */ + if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) { + goto set_encodeext_end; + } + /* cliW: fix group key for wpa_supplicant rekey use toogle index */ + if ((EncAlgorithm == DOT11_ENC_TKIP) || (EncAlgorithm == DOT11_ENC_CCMP)) + KeyIndex = 1; + + priv->pmib->dot11GroupKeysTable.dot11Privacy = EncAlgorithm; + priv->pmib->dot11GroupKeysTable.keyid = KeyIndex; + } + + /* cliW test supplicant using [ len : tx : rx ] key format */ + if ( EncAlgorithm == DOT11_ENC_TKIP ) { + char tmp[8]; +#if 1 + WPA_GLOBAL_INFO *pGblInfo = priv->wpa_global_info; + + if ( IsDefaultKey ) { + pGblInfo->GkeyReady = TRUE; + pGblInfo->GN = KeyIndex; + } + pGblInfo->MulticastCipher = _TKIP_PRIVACY_; +#endif + memcpy(tmp, KeyMaterial+16, 8); + memcpy(KeyMaterial+16, KeyMaterial+24, 8); + memcpy(KeyMaterial+24, tmp, 8); + } + + memcpy(Set_Key.MACAddr, ext->addr.sa_data, MACADDRLEN); + if (IsDefaultKey) + Set_Key.KeyType = DOT11_KeyType_Pairwise; + else + Set_Key.KeyType = (IsGroupKey ? DOT11_KeyType_Group : DOT11_KeyType_Pairwise); + + Set_Key.EncType = EncAlgorithm; + Set_Key.KeyIndex = KeyIndex; + Set_Key.KeyLen = KeyLength; + ret = DOT11_Process_Set_Key(dev, NULL, &Set_Key, KeyMaterial); + + if ((EncAlgorithm == DOT11_ENC_TKIP) || (EncAlgorithm == DOT11_ENC_CCMP)) + { + pstat = get_stainfo(priv, ext->addr.sa_data); + if ((pstat != NULL) && (pstat->state & WIFI_ASOC_STATE)) + pstat->ieee8021x_ctrlport = 1; + } + } + else if (EncAlgorithm == DOT11_ENC_NONE) + { + // Remove Key + DOT11_DELETE_KEY Delete_Key; + struct iw_point wrq; + + if ((EncAlgorithm == DOT11_ENC_WEP40) || (EncAlgorithm == DOT11_ENC_WEP104)) + { + memset(priv->pmib->dot11DefaultKeysTable.keytype[KeyIndex].skey, 0, 16); + } + + if (IsDefaultKey) + { + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + priv->pmib->dot1180211AuthEntry.dot11PrivacyKeyLen = 0; + } + + wrq.pointer = (caddr_t)&Delete_Key; + wrq.length = sizeof(DOT11_DELETE_KEY); + + memset(&Delete_Key, 0, sizeof(Delete_Key)); + Delete_Key.EventId = DOT11_EVENT_DELETE_KEY; + Delete_Key.IsMoreEvent = FALSE; + + Delete_Key.KeyType = (IsGroupKey ? DOT11_KeyType_Group : DOT11_KeyType_Pairwise); + memcpy(Delete_Key.MACAddr, ext->addr.sa_data, MACADDRLEN); + + // check root intf is up before deleting key to avoid stuck in CAM_read_mac_config + if (IS_DRV_OPEN(GET_ROOT(priv))) + ret = DOT11_Process_Delete_Key(priv->dev, &wrq); + } + +set_encodeext_end: + return ret; +} + +int rtl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + s4Byte key_index; + s4Byte ret = 0; + s4Byte max_key_len; + char *pkey=NULL; +// char keybuf[32]; + int keylen=0; + + DEBUG_INFO("rtwlan_ioctl: rtioctl_get_encodeext: \n"); + + max_key_len = encoding->length - sizeof(struct iw_encode_ext); + if (max_key_len < 0) + return -EINVAL; + key_index = (encoding->flags & IW_ENCODE_INDEX) - 1; + + memset(ext, 0, sizeof(struct iw_encode_ext)); + + switch (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm) { + case _WEP_40_PRIVACY_: + case _WEP_104_PRIVACY_: + ext->alg = IW_ENCODE_ALG_WEP; + encoding->flags |= IW_ENCODE_ENABLED; + pkey = priv->pmib->dot11DefaultKeysTable.keytype[key_index].skey; + keylen = 16; + break; + + case _TKIP_PRIVACY_: + ext->alg = IW_ENCODE_ALG_TKIP; + encoding->flags |= IW_ENCODE_ENABLED; + // TODO: get key + break; + + case _CCMP_PRIVACY_: + ext->alg = IW_ENCODE_ALG_CCMP; + encoding->flags |= IW_ENCODE_ENABLED; + // TODO: get key + break; + + case _NO_PRIVACY_: + default: + ext->alg = IW_ENCODE_ALG_NONE; + encoding->flags |= IW_ENCODE_NOKEY; + break; + } + + if (!(encoding->flags & IW_ENCODE_NOKEY)) { + if (max_key_len < keylen) { + ret = -E2BIG; + goto out; + } + if (pkey) + memcpy (ext->key, pkey, keylen); + } + + out: + return ret; +} + +int rtl_siwpmkid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned char j,blInserted = _FALSE; + int ret=0; + +#if 0 + struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra; + unsigned char strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; + unsigned char strIssueBssid[ ETH_ALEN ] = { 0x00 }; + + /* + struct iw_pmksa + { + __u32 cmd; + struct sockaddr bssid; + __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16 + } + There are the BSSID information in the bssid.sa_data array. + If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information. + If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver. + If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver. + */ + + memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); + if ( pPMK->cmd == IW_PMKSA_ADD ) + { + DEBUG_INFO( "%s: IW_PMKSA_ADD!\n", __FUNCTION__ ); + if (!memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN )) + { + return (-EINVAL); + } + + blInserted = _FALSE; + + //overwrite PMKID + for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ) + { // BSSID is matched, the same AP => rewrite with new PMKID. + + DEBUG_INFO( "%s: BSSID exists in the PMKList.\n", __FUNCTION__ ); + + memcpy( priv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); + priv->PMKIDList[ j ].bUsed = _TRUE; + priv->PMKIDIndex = j+1; + blInserted = _TRUE; + break; + } + } + + if(!blInserted) + { + // Find a new entry + DEBUG_INFO( "[%s] Use the new entry index = %d for this PMKID.\n", __FUNCTION__, + priv->PMKIDIndex ); + + memcpy(priv->PMKIDList[priv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); + memcpy(priv->PMKIDList[priv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); + + priv->PMKIDList[priv->PMKIDIndex ].bUsed = _TRUE; + priv->PMKIDIndex++ ; + if(priv->PMKIDIndex == NUM_PMKID_CACHE) + { + priv->PMKIDIndex = 0; + } + } + } + else if ( pPMK->cmd == IW_PMKSA_REMOVE ) + { + DEBUG_INFO( "[%s] IW_PMKSA_REMOVE!\n", __FUNCTION__ ); + for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN)) + { // BSSID is matched, the same AP => Remove this PMKID information and reset it. + memset( priv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN ); + priv->PMKIDList[ j ].bUsed = _FALSE; + break; + } + } + } + else if ( pPMK->cmd == IW_PMKSA_FLUSH ) + { + DEBUG_INFO( "[%s] IW_PMKSA_FLUSH!\n", __FUNCTION__ ); + memset( &priv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + priv->PMKIDIndex = 0; + } +#endif + return( ret ); +} +#endif // WIFI_WPAS_CLI +#endif // CONFIG_RTL_COMAPI_WLTOOLS + +#ifdef CONFIG_RTL_COMAPI_CFGFILE + +#define CFG_FILE_PATH "/etc/Wireless/RTL8192CD.dat" + +void del_mib_list(struct net_device *dev); +int CfgFileSetMib(struct net_device *dev, char *buf); + +int CfgFileProc(struct net_device *dev) +{ + //RTL_PRIV *priv = dev->priv; + unsigned char *mem_ptr; + int ret = 0; + + printk("-------> Set MIB from " CFG_FILE_PATH "\n"); + if((mem_ptr = (unsigned char *)kmalloc(MAX_CONFIG_FILE_SIZE, GFP_ATOMIC)) == NULL) { + printk("%s: not enough memory\n", __FUNCTION__); + return -1; + } + + memset(mem_ptr, 0, MAX_CONFIG_FILE_SIZE); + + ret = CfgFileRead(dev, mem_ptr); + + if (ret < 0) + { + printk("%s: ReadCfgFile failed (%d)\n", __FUNCTION__, ret); + goto proc_exit; + } + + //printk("%s\n", mem_ptr); + + del_mib_list(dev); + + CfgFileSetMib(dev, mem_ptr); + + printk("<------- Set MIB from " CFG_FILE_PATH " Success\n"); + +proc_exit: + kfree(mem_ptr); + return ret; + +} + +int CfgFileRead(struct net_device *dev, char *buf) +{ + //RTL_PRIV *priv = dev->priv; + struct file *fp; + mm_segment_t oldfs; + //size_t len; + + //int read_bytes = 0; + int ret = 0; + + oldfs = get_fs(); + set_fs(get_ds()); + fp = filp_open(CFG_FILE_PATH, O_RDONLY, 0); + if(IS_ERR(fp)) { + ret = PTR_ERR(fp); + printk("Fail to open configuration file. (%d)\n", ret); + goto err_exit; + } + + if (!(fp->f_op && fp->f_op->read)) { + printk("Fail to support file ops: read\n"); + ret = -1; + goto err_close; + } + + if ((ret = fp->f_op->read(fp, buf, MAX_CONFIG_FILE_SIZE, &fp->f_pos))< 0){ + printk("Fail to read file. (%d)\n", ret); + goto err_close; + } + +err_close: + filp_close(fp, NULL); +err_exit: + set_fs(oldfs); + return ret; + +} + +static int rewrite_line (unsigned char **dst, unsigned char **src) +{ + int cnt=0; + char *s = *src; + char *d = *dst; + char *loc=NULL, *vl_s=NULL, *vl_e=NULL; + unsigned char quoted = 0; + + //printk("src = %s(%d)\n", *src, strlen(*src)); + loc=strchr(s, '"'); + if (loc) { + unsigned int i = strlen(*src); + vl_s=loc; + while (i>0){ + char *t = (char *)((unsigned long)s+i-1); + if (*t=='"' && t > vl_s ){ + vl_e = t; + quoted = 1; + break; + } + i--; + } + } + + while (*s) { + u8 noop = 0; + if (quoted ==1 && (vl_s < s && s < vl_e)) + noop = 1; + + if ( noop == 0 ) { + if ((*s=='\r') || (*s=='\n') || (*s=='#') || (*s=='\0')) + break; + if ((*s == '\t')||(*s == ' ')||(*s == '"')){ + s++; + continue; + } + } + + *d = *s; + s++; + d++; + cnt++; + + } + *d = '\0'; + //printk(" dst = %s\n", *dst); + return cnt; +} + + +int CfgFileSetMib(struct net_device *dev, char *buf) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + unsigned char *line_head, *next_head; + unsigned char *cmd_buf, *mibstr, *valstr, *mibstart; + //struct mib_cfg_func *tmp_mibcfg; + int ret = 0; +#ifdef VENDOR_PARAM_COMPATIBLE + int arg_num = sizeof(RTL_SUPPORT_MIBCFG)/sizeof(struct mib_cfg_func); +#endif //VENDOR_PARAM_COMPATIBLE + + if((cmd_buf = (unsigned char *)kmalloc(MAX_PARAM_BUF_SIZE, GFP_ATOMIC)) == NULL) { + printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); + return -1; + } + + if((mibstr = (unsigned char *)kmalloc(20, GFP_ATOMIC)) == NULL) { + printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); + return -1; + } + + if((valstr = (unsigned char *)kmalloc(MAX_PARAM_BUF_SIZE, GFP_ATOMIC)) == NULL) { + printk("%s(%d): not enough memory\n", __FUNCTION__, __LINE__); + return -1; + } + + next_head = buf; + + do { + char *loc; + int len = 0, miblen = 0, vallen = 0; + //int i=0; + + memset(cmd_buf, 0, MAX_PARAM_BUF_SIZE); + memset(mibstr, 0, 20); + memset(valstr, 0, MAX_PARAM_BUF_SIZE); + + line_head = next_head; + next_head = get_line(&line_head); + if (line_head == NULL) + break; + + if (line_head[0] == '#') + continue; + + len = rewrite_line(&cmd_buf, &line_head); + //printk("%s (%d)\n", cmd_buf, len); + +#ifdef VENDOR_PARAM_COMPATIBLE + /* To compatible with other vendor's parameters, each parameter must have its own process function - chris*/ + loc = strchr(mibstart, '='); + miblen = (u32)loc - (u32)mibstart; + vallen = len - miblen -1; + if (vallen>0) { + for (i=0; i>>>>>>> cmd=%s , %s, %c \n",cmd_buf, dev->name, cmd_buf[strlen(dev->name)]); + if (!strncmp(dev->name, cmd_buf, strlen(dev->name))&&(cmd_buf[strlen(dev->name)]!='-')) { + mibstart = cmd_buf + strlen(dev->name)+1; + } else + continue; + + loc = strchr(mibstart, '='); + miblen = (u32)loc - (u32)mibstart; + vallen = len - (strlen(dev->name)+1) - (miblen+1); + + if (vallen>0) { + + ret = set_mib(priv, mibstart); + if (ret < 0) { + strncpy(mibstr, mibstart, miblen); + strncpy(valstr, (char*)((u32)loc+1), vallen); + //printk("(%s) = (%s) (%d)\n", mibstr, valstr, vallen); + printk("CFGFILE set_mib \"%s\" failed \n", mibstart); + //return -1; + } + +#endif // VENDOR_PARAM_COMPATIBLE + } + + } while (1); + + kfree(cmd_buf); + kfree(mibstr); + kfree(valstr); + + return ret; +} + +void del_mib_list(struct net_device *dev) +{ + RTL_PRIV *priv = GET_DEV_PRIV(dev); + + + if (priv->pmib) { +#ifdef WDS + priv->pmib->dot11WdsInfo.wdsNum = 0; +#endif + priv->pmib->dot11StationConfigEntry.dot11AclNum=0; + } + +} + +#endif //CONFIG_RTL_COMAPI_CFGFILE + + + diff --git a/package/kernel/rtl8192cd/8192cd_comapi.h b/package/kernel/rtl8192cd/8192cd_comapi.h old mode 100755 new mode 100644 index 1c3e95c97c5..e7b838425c0 --- a/package/kernel/rtl8192cd/8192cd_comapi.h +++ b/package/kernel/rtl8192cd/8192cd_comapi.h @@ -1,113 +1,113 @@ -/* - * Header file for API-compatible handling routines - * - * - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#ifndef _8192CD_COMAPI_H_ -#define _8192CD_COMAPI_H_ - -#include "./8192cd.h" - -typedef struct rtl8192cd_priv RTL_PRIV; -#define MAX_CONFIG_FILE_SIZE (64*1024) // for 8192, added to 64k -#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k - -#ifdef CONFIG_RTL_COMAPI_CFGFILE - -/* Following is a example for PARAMETERs completely compatible to other vendors' - * configure file - chris 2010/02/01 */ -#undef VENDOR_PARAM_COMPATIBLE -#ifdef VENDOR_PARAM_COMPATIBLE - -int Set_CountryRegion_Proc (RTL_PRIV *priv, char *arg); -int Set_CountryRegionABand_Proc (RTL_PRIV *priv, char *arg); -int Set_SSID_Proc (RTL_PRIV *priv, char *arg); - - -struct mib_cfg_func{ - char name[20]; /*mib name*/ - int (*set_proc)(RTL_PRIV *priv, char *arg); -}; - -static struct mib_cfg_func *TMP_MIBCFG, RTL_SUPPORT_MIBCFG[] = { - {"CountryRegion", Set_CountryRegion_Proc}, - {"CountryRegionABand", Set_CountryRegionABand_Proc}, - {"SSID", Set_SSID_Proc} -}; - -int Set_CountryRegion_Proc(RTL_PRIV *priv, char *arg) -{ - int val = simple_strtol(arg, 0 ,10); - if (DOMAIN_FCC <= val && val <= DOMAIN_MAX ) { - priv->pmib->dot11StationConfigEntry.dot11RegDomain = val; - return TRUE; - } else { - printk("contry region out of range [%d-%d]\n", DOMAIN_FCC, DOMAIN_MAX); - return FALSE; - } -} - -int Set_CountryRegionABand_Proc(RTL_PRIV *priv, char *arg) -{ - int val = simple_strtol(arg, 0 ,10); - priv->pmib->dot11StationConfigEntry.dot11RegDomainABand = val; - return TRUE; -} - -int Set_SSID_Proc(RTL_PRIV *priv, char *arg) -{ - strcpy(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, arg); - return TRUE; -} - -#else -extern int set_mib(struct rtl8192cd_priv *priv, unsigned char *data); - -#endif //VENDOR_PARAM_COMPATIBLE - -#endif //CONFIG_RTL_COMAPI_CFGFILE - -#ifdef WIFI_WPAS_CLI - -#define WPA_IE_ID 0xdd -#define WPA2_IE_ID 0x30 -#define RSN_HEADER_LEN 4 -#define WPA_SELECTOR_LEN 4 -#define RSN_SELECTOR_LEN 4 -#define VENDOR_SPECIFIC_IE 221 - -#ifdef CONFIG_RTL_WAPI_SUPPORT -#ifndef IW_AUTH_WAPI_VERSION_1 -#define IW_AUTH_WAPI_VERSION_1 0x00000008 -#endif - -#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK -#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 -#endif - -#ifndef IW_AUTH_KEY_MGMT_WAPI_CERT -#define IW_AUTH_KEY_MGMT_WAPI_CERT 0x08 -#endif - -#ifndef IW_AUTH_WAPI_ENABLED -#define IW_AUTH_WAPI_ENABLED 0x20 -#endif - -#ifndef IW_ENCODE_ALG_SM4 -#define IW_ENCODE_ALG_SM4 0x20 -#endif -#endif // CONFIG_RTL_WAPI_SUPPORT -#endif // WIFI_WPAS_CLI - -#endif // _8192CD_COMAPI_H_ - - - +/* + * Header file for API-compatible handling routines + * + * + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#ifndef _8192CD_COMAPI_H_ +#define _8192CD_COMAPI_H_ + +#include "./8192cd.h" + +typedef struct rtl8192cd_priv RTL_PRIV; +#define MAX_CONFIG_FILE_SIZE (64*1024) // for 8192, added to 64k +#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k + +#ifdef CONFIG_RTL_COMAPI_CFGFILE + +/* Following is a example for PARAMETERs completely compatible to other vendors' + * configure file - chris 2010/02/01 */ +#undef VENDOR_PARAM_COMPATIBLE +#ifdef VENDOR_PARAM_COMPATIBLE + +int Set_CountryRegion_Proc (RTL_PRIV *priv, char *arg); +int Set_CountryRegionABand_Proc (RTL_PRIV *priv, char *arg); +int Set_SSID_Proc (RTL_PRIV *priv, char *arg); + + +struct mib_cfg_func{ + char name[20]; /*mib name*/ + int (*set_proc)(RTL_PRIV *priv, char *arg); +}; + +static struct mib_cfg_func *TMP_MIBCFG, RTL_SUPPORT_MIBCFG[] = { + {"CountryRegion", Set_CountryRegion_Proc}, + {"CountryRegionABand", Set_CountryRegionABand_Proc}, + {"SSID", Set_SSID_Proc} +}; + +int Set_CountryRegion_Proc(RTL_PRIV *priv, char *arg) +{ + int val = simple_strtol(arg, 0 ,10); + if (DOMAIN_FCC <= val && val <= DOMAIN_MAX ) { + priv->pmib->dot11StationConfigEntry.dot11RegDomain = val; + return TRUE; + } else { + printk("contry region out of range [%d-%d]\n", DOMAIN_FCC, DOMAIN_MAX); + return FALSE; + } +} + +int Set_CountryRegionABand_Proc(RTL_PRIV *priv, char *arg) +{ + int val = simple_strtol(arg, 0 ,10); + priv->pmib->dot11StationConfigEntry.dot11RegDomainABand = val; + return TRUE; +} + +int Set_SSID_Proc(RTL_PRIV *priv, char *arg) +{ + strcpy(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, arg); + return TRUE; +} + +#else +extern int set_mib(struct rtl8192cd_priv *priv, unsigned char *data); + +#endif //VENDOR_PARAM_COMPATIBLE + +#endif //CONFIG_RTL_COMAPI_CFGFILE + +#ifdef WIFI_WPAS_CLI + +#define WPA_IE_ID 0xdd +#define WPA2_IE_ID 0x30 +#define RSN_HEADER_LEN 4 +#define WPA_SELECTOR_LEN 4 +#define RSN_SELECTOR_LEN 4 +#define VENDOR_SPECIFIC_IE 221 + +#ifdef CONFIG_RTL_WAPI_SUPPORT +#ifndef IW_AUTH_WAPI_VERSION_1 +#define IW_AUTH_WAPI_VERSION_1 0x00000008 +#endif + +#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK +#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 +#endif + +#ifndef IW_AUTH_KEY_MGMT_WAPI_CERT +#define IW_AUTH_KEY_MGMT_WAPI_CERT 0x08 +#endif + +#ifndef IW_AUTH_WAPI_ENABLED +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif + +#ifndef IW_ENCODE_ALG_SM4 +#define IW_ENCODE_ALG_SM4 0x20 +#endif +#endif // CONFIG_RTL_WAPI_SUPPORT +#endif // WIFI_WPAS_CLI + +#endif // _8192CD_COMAPI_H_ + + + diff --git a/package/kernel/rtl8192cd/8192cd_debug.c b/package/kernel/rtl8192cd/8192cd_debug.c index c22517bb803..d834459f813 100644 --- a/package/kernel/rtl8192cd/8192cd_debug.c +++ b/package/kernel/rtl8192cd/8192cd_debug.c @@ -1,257 +1,257 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "./8192cd_cfg.h" -#include "./8192cd_headers.h" -#include "./8192cd.h" - - -#define MAX_ARGC 20 -#define MAX_ARGV 16 - -#define SPRINTT(buf, fmt, args...) sprintf(buf, "%s"fmt, buf, ##args) - -enum PHYDM_CMD_ID { - DRV_HELP, - DRV_DEBUG -}; - -struct _DRV_COMMAND { - char name[16]; - unsigned char id; -}; - - -struct _DRV_COMMAND drv_dm_ary[] = { - {"-h", DRV_HELP}, /*do not move this element to other position*/ - {"drvdbg", DRV_DEBUG} -}; - - -#ifdef CONFIG_STATISTICS_INFO -void stats_env_cnt( - struct rtl8192cd_priv *priv) -{ - unsigned char i; - unsigned int fa_cck_idx, fa_ofdm_idx; - unsigned char str[NUM_STATS_ENV_CNT*10]; - - - #if (PHYDM_TDMA_DIG_SUPPORT == 1) - if(ODMPTR->original_dig_restore == 0) { - fa_cck_idx = (ODMPTR->FalseAlmCnt_Acc.Cnt_Cck_fail_1sec[0] + ODMPTR->FalseAlmCnt_Acc.Cnt_Cck_fail_1sec[1]) >> 7; - fa_cck_idx = (fa_cck_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_cck_idx; - fa_ofdm_idx = (ODMPTR->FalseAlmCnt_Acc.Cnt_Ofdm_fail_1sec[0] + ODMPTR->FalseAlmCnt_Acc.Cnt_Ofdm_fail_1sec[1]) >> 7; - fa_ofdm_idx = (fa_ofdm_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_ofdm_idx; - - priv->ext_stats.stats_ofdm_fa[fa_ofdm_idx]++; - priv->ext_stats.stats_cck_fa[fa_cck_idx]++; - } else - #endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) - { - fa_cck_idx = (ODMPTR->FalseAlmCnt.Cnt_Cck_fail >> 7); - fa_cck_idx = (fa_cck_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_cck_idx; - fa_ofdm_idx = ODMPTR->FalseAlmCnt.Cnt_Ofdm_fail >> 7; - fa_ofdm_idx = (fa_ofdm_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_ofdm_idx; - - priv->ext_stats.stats_ofdm_fa[fa_ofdm_idx]++; - priv->ext_stats.stats_cck_fa[fa_cck_idx]++; - } - - if((priv->pshare->rf_ft_var.stats_int != 0) && !(priv->up_time % (priv->pshare->rf_ft_var.stats_int*60))) { - str[0] = '\0'; - for(i=0; iext_stats.stats_cck_fa[i]); - priv->ext_stats.stats_cck_fa[i] = 0; - } - DRV_RT_TRACE(priv, DRV_DBG_STATISTICS_INFO, DRV_DBG_SERIOUS, "cck_fa: %s\n", str); - - str[0] = '\0'; - for(i=0; iext_stats.stats_ofdm_fa[i]); - priv->ext_stats.stats_ofdm_fa[i] = 0; - } - DRV_RT_TRACE(priv, DRV_DBG_STATISTICS_INFO, DRV_DBG_SERIOUS, "ofdm_fa: %s\n", str); - } - - -} -#endif - -void drv_init_dbg_setting( - struct rtl8192cd_priv *priv -) -{ - priv->pshare->rf_ft_var.dbglevel = DRV_DBG_WARNING; - - priv->pshare->rf_ft_var.dbgcomp = \ - // DRV_DBG_CONN_INFO | - // DRV_DBG_SYS_INFO | - // DRV_DBG_STATISTICS_INFO | - 0; - -} - -void drv_debug_trace( - struct rtl8192cd_priv *priv, - unsigned int *const dm_value, - unsigned int *_used, - char *output, - unsigned int *_out_len -) -{ - unsigned int pre_debug_components, one = 1; - unsigned int used = *_used; - unsigned int out_len = *_out_len; - - pre_debug_components = priv->pshare->rf_ft_var.dbgcomp; - - SPRINTT(output, "\n================================\n"); - if (dm_value[0] == 100) { - SPRINTT(output, "[Debug Message] Driver Selection\n"); - SPRINTT(output, "================================\n"); - SPRINTT(output, "00. (( %s ))CONN INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_CONN_INFO) ? ("V") : ("."))); - SPRINTT(output, "01. (( %s ))SYSTEM INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_SYS_INFO) ? ("V") : ("."))); - SPRINTT(output, "02. (( %s ))STATISTICS INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_STATISTICS_INFO) ? ("V") : ("."))); - SPRINTT(output, "================================\n"); - - } else if (dm_value[0] == 101) { - priv->pshare->rf_ft_var.dbgcomp = 0; - SPRINTT(output, "Disable all debug components\n"); - } else { - if (dm_value[1] == 1) { /*enable*/ - priv->pshare->rf_ft_var.dbgcomp |= (one << dm_value[0]); - } else if (dm_value[1] == 2) { /*disable*/ - priv->pshare->rf_ft_var.dbgcomp &= ~(one << dm_value[0]); - } else - SPRINTT(output, "[Warning!!!] 1:enable, 2:disable\n"); - } - SPRINTT(output, "pre-DbgComponents = 0x%x\n", pre_debug_components); - SPRINTT(output, "Curr-DbgComponents = 0x%x\n", priv->pshare->rf_ft_var.dbgcomp); - SPRINTT(output, "================================\n"); -} - - -void drv_cmd_parser( - struct rtl8192cd_priv *priv, - char input[][MAX_ARGV], - unsigned int input_num, - char *output, - unsigned int out_len -) -{ - unsigned int used = 0; - unsigned char id = 0; - int var1[10] = {0}; - int i, input_idx = 0, drv_ary_size; - char help[] = "-h"; - - //Parsing Cmd ID - if (input_num) { - - drv_ary_size = sizeof(drv_dm_ary) / sizeof(struct _DRV_COMMAND); - for (i = 0; i < drv_ary_size; i++) { - if (strcmp(drv_dm_ary[i].name, input[0]) == 0) { - id = drv_dm_ary[i].id; - break; - } - } - if (i == drv_ary_size) { - SPRINTT(output, "SET, command not found!\n"); - return; - } - } - - switch (id) { - - case DRV_HELP: - { - SPRINTT(output, "drv cmd ==>\n"); - for (i=0; i < drv_ary_size-2; i++) { - - SPRINTT(output, " %-5d: %s\n", i, drv_dm_ary[i+2].name); - /**/ - } - } - break; - case DRV_DEBUG: - { - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - sscanf(input[i + 1], "%d", &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ - drv_debug_trace(priv, (unsigned int *)var1, &used, output, &out_len); - } - } - break; - - default: - SPRINTT(output, "SET, unknown command!\n"); - break; - - } -} - -void -drv_cmd( - struct rtl8192cd_priv *priv, - unsigned char *input, - char *output, - unsigned int out_len -) -{ - char *token; - unsigned int Argc = 0; - char Argv[MAX_ARGC][MAX_ARGV]; - unsigned char i; - - do { - token = strsep(&input, ", "); - if (token) { - strcpy(Argv[Argc], token); - Argc++; - } else - break; - } while (Argc < MAX_ARGC); - - for(i=0;ioriginal_dig_restore == 0) { + fa_cck_idx = (ODMPTR->FalseAlmCnt_Acc.Cnt_Cck_fail_1sec[0] + ODMPTR->FalseAlmCnt_Acc.Cnt_Cck_fail_1sec[1]) >> 7; + fa_cck_idx = (fa_cck_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_cck_idx; + fa_ofdm_idx = (ODMPTR->FalseAlmCnt_Acc.Cnt_Ofdm_fail_1sec[0] + ODMPTR->FalseAlmCnt_Acc.Cnt_Ofdm_fail_1sec[1]) >> 7; + fa_ofdm_idx = (fa_ofdm_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_ofdm_idx; + + priv->ext_stats.stats_ofdm_fa[fa_ofdm_idx]++; + priv->ext_stats.stats_cck_fa[fa_cck_idx]++; + } else + #endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) + { + fa_cck_idx = (ODMPTR->FalseAlmCnt.Cnt_Cck_fail >> 7); + fa_cck_idx = (fa_cck_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_cck_idx; + fa_ofdm_idx = ODMPTR->FalseAlmCnt.Cnt_Ofdm_fail >> 7; + fa_ofdm_idx = (fa_ofdm_idx > NUM_STATS_ENV_CNT-1) ? (NUM_STATS_ENV_CNT - 1) : fa_ofdm_idx; + + priv->ext_stats.stats_ofdm_fa[fa_ofdm_idx]++; + priv->ext_stats.stats_cck_fa[fa_cck_idx]++; + } + + if((priv->pshare->rf_ft_var.stats_int != 0) && !(priv->up_time % (priv->pshare->rf_ft_var.stats_int*60))) { + str[0] = '\0'; + for(i=0; iext_stats.stats_cck_fa[i]); + priv->ext_stats.stats_cck_fa[i] = 0; + } + DRV_RT_TRACE(priv, DRV_DBG_STATISTICS_INFO, DRV_DBG_SERIOUS, "cck_fa: %s\n", str); + + str[0] = '\0'; + for(i=0; iext_stats.stats_ofdm_fa[i]); + priv->ext_stats.stats_ofdm_fa[i] = 0; + } + DRV_RT_TRACE(priv, DRV_DBG_STATISTICS_INFO, DRV_DBG_SERIOUS, "ofdm_fa: %s\n", str); + } + + +} +#endif + +void drv_init_dbg_setting( + struct rtl8192cd_priv *priv +) +{ + priv->pshare->rf_ft_var.dbglevel = DRV_DBG_WARNING; + + priv->pshare->rf_ft_var.dbgcomp = \ + // DRV_DBG_CONN_INFO | + // DRV_DBG_SYS_INFO | + // DRV_DBG_STATISTICS_INFO | + 0; + +} + +void drv_debug_trace( + struct rtl8192cd_priv *priv, + unsigned int *const dm_value, + unsigned int *_used, + char *output, + unsigned int *_out_len +) +{ + unsigned int pre_debug_components, one = 1; + unsigned int used = *_used; + unsigned int out_len = *_out_len; + + pre_debug_components = priv->pshare->rf_ft_var.dbgcomp; + + SPRINTT(output, "\n================================\n"); + if (dm_value[0] == 100) { + SPRINTT(output, "[Debug Message] Driver Selection\n"); + SPRINTT(output, "================================\n"); + SPRINTT(output, "00. (( %s ))CONN INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_CONN_INFO) ? ("V") : ("."))); + SPRINTT(output, "01. (( %s ))SYSTEM INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_SYS_INFO) ? ("V") : ("."))); + SPRINTT(output, "02. (( %s ))STATISTICS INFO\n", ((priv->pshare->rf_ft_var.dbgcomp & DRV_DBG_STATISTICS_INFO) ? ("V") : ("."))); + SPRINTT(output, "================================\n"); + + } else if (dm_value[0] == 101) { + priv->pshare->rf_ft_var.dbgcomp = 0; + SPRINTT(output, "Disable all debug components\n"); + } else { + if (dm_value[1] == 1) { /*enable*/ + priv->pshare->rf_ft_var.dbgcomp |= (one << dm_value[0]); + } else if (dm_value[1] == 2) { /*disable*/ + priv->pshare->rf_ft_var.dbgcomp &= ~(one << dm_value[0]); + } else + SPRINTT(output, "[Warning!!!] 1:enable, 2:disable\n"); + } + SPRINTT(output, "pre-DbgComponents = 0x%x\n", pre_debug_components); + SPRINTT(output, "Curr-DbgComponents = 0x%x\n", priv->pshare->rf_ft_var.dbgcomp); + SPRINTT(output, "================================\n"); +} + + +void drv_cmd_parser( + struct rtl8192cd_priv *priv, + char input[][MAX_ARGV], + unsigned int input_num, + char *output, + unsigned int out_len +) +{ + unsigned int used = 0; + unsigned char id = 0; + int var1[10] = {0}; + int i, input_idx = 0, drv_ary_size; + char help[] = "-h"; + + //Parsing Cmd ID + if (input_num) { + + drv_ary_size = sizeof(drv_dm_ary) / sizeof(struct _DRV_COMMAND); + for (i = 0; i < drv_ary_size; i++) { + if (strcmp(drv_dm_ary[i].name, input[0]) == 0) { + id = drv_dm_ary[i].id; + break; + } + } + if (i == drv_ary_size) { + SPRINTT(output, "SET, command not found!\n"); + return; + } + } + + switch (id) { + + case DRV_HELP: + { + SPRINTT(output, "drv cmd ==>\n"); + for (i=0; i < drv_ary_size-2; i++) { + + SPRINTT(output, " %-5d: %s\n", i, drv_dm_ary[i+2].name); + /**/ + } + } + break; + case DRV_DEBUG: + { + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + sscanf(input[i + 1], "%d", &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ + drv_debug_trace(priv, (unsigned int *)var1, &used, output, &out_len); + } + } + break; + + default: + SPRINTT(output, "SET, unknown command!\n"); + break; + + } +} + +void +drv_cmd( + struct rtl8192cd_priv *priv, + unsigned char *input, + char *output, + unsigned int out_len +) +{ + char *token; + unsigned int Argc = 0; + char Argv[MAX_ARGC][MAX_ARGV]; + unsigned char i; + + do { + token = strsep(&input, ", "); + if (token) { + strcpy(Argv[Argc], token); + Argc++; + } else + break; + } while (Argc < MAX_ARGC); + + for(i=0;i= 8) - { - return (96); // maximum 96 dB - } - - for (j=0;j<12;j++) - { - if (Value <= dB_Invert_Table[i][j]) - { - break; - } - } - - dB = i*12 + j + 1; - - return (dB); -} - - -static int -GetPSDData_8812( - IN PDM_ODM_T pDM_Odm, - unsigned int point, - u1Byte initial_gain_psd) -{ - int psd_report; - struct rtl8192cd_priv *priv=pDM_Odm->priv; - - //Set DCO frequency index, offset=(40MHz/SamplePts)*point - ODM_SetBBReg(pDM_Odm, 0x910, 0x3FF, point); - - //Start PSD calculation, Reg808[22]=0->1 - ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 1); - - //Need to wait for HW PSD report - delay_us(priv->pshare->rf_ft_var.dfs_psd_delay); - - ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0); - - //Read PSD report, Reg8B4[15:0] - psd_report = (int)ODM_GetBBReg(pDM_Odm,0xf44, bMaskDWord) & 0x0000FFFF; - if(priv->pshare->rf_ft_var.psd_skip_lookup_table){ - if(psd_report >=14) - psd_report = 23; - else - psd_report = 8; - } - else{ - psd_report = (int)(ConvertTo_dB((u4Byte)psd_report)); - } - - return psd_report; - -} - - -void Scan_BB_PSD( - IN PDM_ODM_T pDM_Odm, - int *PSD_report_right, - int *PSD_report_left, - int len, - int initial_gain) -{ - struct rtl8192cd_priv *priv=pDM_Odm->priv; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte ST_TH_origin; - u1Byte idx[20]={//96,99,102,106,109,112,115,118,122,125, - 224,227,230,234,237,240,243,246,250,253, - 0,3,6,10,13,16,19,22,26,29}; - int tone_idx, channel_org, channel, i, BW_org; - - // set DFS ST_TH to max value - ST_TH_origin = RTL_R8(0x91c); - RTL_W8(0x91c, 0x4e); - - // Turn off CCK - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0); //808[28] - - // Turn off TX - // Pause TX Queue - if (!priv->pmib->dot11DFSEntry.disable_tx) - ODM_Write1Byte(pDM_Odm, 0x522, 0xFF); //REG_TXPAUSE §ï¬°0x522 - - // Turn off CCA - if((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)){ - ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0x1); //838[1] ³]¬°1 - } - else{ - ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0x1); //838[3] ³]¬°1 - } - - // PHYTXON while loop - PHY_SetBBReg(priv, 0x8fc, 0xfff, 0); - i = 0; - while (ODM_GetBBReg(pDM_Odm, 0xfa0, BIT18)) { - i++; - if (i > 1000000) { - panic_printk("Wait in %s() more than %d times!\n", __FUNCTION__, i); - break; - } - } - - // backup IGI_origin , set IGI = 0x3e; - pDM_DigTable->bPSDInProgress = TRUE; - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, initial_gain); - - // Turn off 3-wire - ODM_SetBBReg(pDM_Odm, 0xC00, BIT1|BIT0, 0x0); //c00[1:0] ¼g0 - - // pts value = 128, 256, 512, 1024 - ODM_SetBBReg(pDM_Odm, 0x910, BIT14|BIT15, 0x1); //910[15:14]³]¬°1, ¥Î256ÂI - ODM_SetBBReg(pDM_Odm, 0x910, BIT12|BIT13, 0x1); //910[13:12]³]¬°1, avg 8 ¦¸ - - // scan in-band PSD - channel_org = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF); - BW_org = priv->pshare->CurrentChannelBW; - if(priv->pshare->CurrentChannelBW != HT_CHANNEL_WIDTH_20){ - priv->pshare->No_RF_Write = 0; - SwBWMode(priv, HT_CHANNEL_WIDTH_20, 0); - priv->pshare->No_RF_Write = 1; - } - - if (priv->pshare->rf_ft_var.dfs_scan_inband) { - int PSD_report_inband[20]; - for (tone_idx=0;tone_idxpshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - channel = channel_org + 4; - else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) - channel = channel_org + 6; - else - channel = channel_org + 10; - delay_us(300); // for idle 20M, it will emit signal in right 20M channel - priv->pshare->No_RF_Write = 0; - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); - priv->pshare->No_RF_Write = 1; - - for (tone_idx=0;tone_idxpshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - channel = channel_org - 4; - else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) - channel = channel_org - 6; - else - channel = channel_org - 10; - priv->pshare->No_RF_Write = 0; - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); - priv->pshare->No_RF_Write = 1; - - for (tone_idx=0;tone_idxpshare->CurrentChannelBW){ - priv->pshare->No_RF_Write = 0; - SwBWMode(priv, BW_org, priv->pshare->offset_2nd_chan); - priv->pshare->No_RF_Write = 1; - } - priv->pshare->No_RF_Write = 0; - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel_org); - priv->pshare->No_RF_Write = 1; - - // Turn on 3-wire - ODM_SetBBReg(pDM_Odm, 0xc00, BIT1|BIT0, 0x3); //c00[1:0] ¼g3 - - // Restore Current Settings - // Resume DIG - pDM_DigTable->bPSDInProgress = FALSE; - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, NONE); - - //Turn on CCA - if((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)){ - ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0); //838[1] ³]¬°0 - } - else{ - ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0); //838[3] ³]¬°0 - } - - - // Turn on TX - // Resume TX Queue - if (!priv->pmib->dot11DFSEntry.disable_tx) - ODM_Write1Byte(pDM_Odm, 0x522, 0x00); //REG_TXPAUSE §ï¬°0x522 - - // CCK on - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 1); //808[28] - - // Resume DFS ST_TH - RTL_W8(0x91c, ST_TH_origin); -} - - -void rtl8192cd_dfs_det_chk(struct rtl8192cd_priv *priv) -{ - PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - unsigned int regf98_value; - unsigned int reg918_value; - unsigned int reg91c_value; - unsigned int reg920_value; - unsigned int reg924_value; - unsigned int reg19e4_value; - unsigned int FA_count_cur=0, FA_count_inc=0; - unsigned int CCA_count_cur=0, CCA_count_inc=0; - unsigned int VHT_CRC_ok_cnt_cur=0, VHT_CRC_ok_cnt_inc=0; - unsigned int HT_CRC_ok_cnt_cur=0, HT_CRC_ok_cnt_inc=0; - unsigned int LEG_CRC_ok_cnt_cur=0, LEG_CRC_ok_cnt_inc=0; - unsigned int Total_CRC_OK_cnt_inc=0, FA_CRCOK_ratio=0; - unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, fa_mask_mid_th=0, fa_mask_lower_th=0; - unsigned int short_pulse_cnt_cur=0, short_pulse_cnt_inc=0; - unsigned int long_pulse_cnt_cur=0, long_pulse_cnt_inc=0; - unsigned int total_pulse_count_inc=0, max_sht_pusle_cnt_th=0; - unsigned int sum, k, fa_flag=0; - unsigned int st_L2H_new=0, st_L2H_tmp, index=0, fault_flag_det, fault_flag_psd; - int j, flags=0; - unsigned long throughput = 0; - - int i, PSD_report_right[20], PSD_report_left[20]; - int max_right, max_left; - int max_fa_in_hist=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0; - - if (priv->det_asoc_clear > 0) { - priv->det_asoc_clear--; - priv->pmib->dot11DFSEntry.DFS_detected = 0; - priv->FA_count_pre = 0; - priv->CCA_count_pre = 0; - priv->VHT_CRC_ok_cnt_pre = 0; - priv->HT_CRC_ok_cnt_pre = 0; - priv->LEG_CRC_ok_cnt_pre = 0; - priv->mask_idx = 0; - priv->hist_idx = 0; - priv->mask_hist_checked = 0; - memset(priv->radar_det_mask_hist, 0, sizeof(priv->radar_det_mask_hist)); - memset(priv->pulse_flag_hist, 0, sizeof(priv->pulse_flag_hist)); - memset(priv->pulse_type_hist, 0, sizeof(priv->pulse_type_hist)); - mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10)); - return; - } - - throughput = priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage; -#ifdef UNIVERSAL_REPEATER - if (GET_VXD_PRIV(priv) && (GET_VXD_PRIV(priv)->drv_state & DRV_STATE_OPEN)) - throughput += (GET_VXD_PRIV(priv)->ext_stats.tx_avarage + GET_VXD_PRIV(priv)->ext_stats.rx_avarage); -#endif - -#ifdef MBSSID - if (priv->pmib->miscEntry.vap_enable) { - for (j=0; jpvap_priv[j])) { - throughput += priv->pvap_priv[j]->ext_stats.tx_avarage+priv->pvap_priv[j]->ext_stats.rx_avarage; - } - } - } -#endif - - // Get FA count during past 100ms - FA_count_cur = PHY_QueryBBReg(priv, 0xf48, 0x0000ffff); - CCA_count_cur = PHY_QueryBBReg(priv, 0xf08, 0xffff0000); - - if (priv->FA_count_pre == 0) - FA_count_inc = 0; - else if (FA_count_cur >= priv->FA_count_pre) - FA_count_inc = FA_count_cur - priv->FA_count_pre; - else - FA_count_inc = FA_count_cur; - priv->FA_count_pre = FA_count_cur; - - if (priv->CCA_count_pre == 0) - CCA_count_inc = 0; - else if (CCA_count_cur >= priv->CCA_count_pre) - CCA_count_inc = CCA_count_cur - priv->CCA_count_pre; - else - CCA_count_inc = CCA_count_cur; - priv->CCA_count_pre = CCA_count_cur; - - priv->fa_inc_hist[priv->mask_idx] = FA_count_inc; - for (i=0; i<5; i++) { - total_fa_in_hist = total_fa_in_hist + priv->fa_inc_hist[i]; - if (priv->fa_inc_hist[i] > max_fa_in_hist) - max_fa_in_hist = priv->fa_inc_hist[i]; - } - if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) - index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; - else - index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; - if (index == 0) - pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[4]; - else if (index == 4) - pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[0] + priv->fa_inc_hist[index-1]; - else - pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[index-1]; - - // Get VHT CRC32 ok count during past 100ms - VHT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf0c, 0x00003fff); - if (VHT_CRC_ok_cnt_cur >= priv->VHT_CRC_ok_cnt_pre) - VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur - priv->VHT_CRC_ok_cnt_pre; - else - VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur; - priv->VHT_CRC_ok_cnt_pre = VHT_CRC_ok_cnt_cur; - - // Get HT CRC32 ok count during past 100ms - HT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf10, 0x00003fff); - if (HT_CRC_ok_cnt_cur >= priv->HT_CRC_ok_cnt_pre) - HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur - priv->HT_CRC_ok_cnt_pre; - else - HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur; - priv->HT_CRC_ok_cnt_pre = HT_CRC_ok_cnt_cur; - - // Get Legacy CRC32 ok count during past 100ms - LEG_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf14, 0x00003fff); - if (LEG_CRC_ok_cnt_cur >= priv->LEG_CRC_ok_cnt_pre) - LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur - priv->LEG_CRC_ok_cnt_pre; - else - LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur; - priv->LEG_CRC_ok_cnt_pre = LEG_CRC_ok_cnt_cur; - - if ((VHT_CRC_ok_cnt_cur == 0x3fff) || - (HT_CRC_ok_cnt_cur == 0x3fff) || - (LEG_CRC_ok_cnt_cur == 0x3fff)) { - PHY_SetBBReg(priv, 0xb58, BIT(0), 1); - PHY_SetBBReg(priv, 0xb58, BIT(0), 0); - } - - Total_CRC_OK_cnt_inc = VHT_CRC_ok_cnt_inc + HT_CRC_ok_cnt_inc + LEG_CRC_ok_cnt_inc; - - // check if the FA occrus frequencly during 100ms - // FA_count_inc is divided by Total_CRC_OK_cnt_inc, which helps to distinguish normal trasmission from interference - if (Total_CRC_OK_cnt_inc > 0) - FA_CRCOK_ratio = FA_count_inc / Total_CRC_OK_cnt_inc; - - //=====dynamic power threshold (DPT) ======== - // Get short pulse count, need carefully handle the counter overflow - regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff); - short_pulse_cnt_cur = regf98_value & 0x000000ff; - if (short_pulse_cnt_cur >= priv->short_pulse_cnt_pre) - short_pulse_cnt_inc = short_pulse_cnt_cur - priv->short_pulse_cnt_pre; - else - short_pulse_cnt_inc = short_pulse_cnt_cur; - priv->short_pulse_cnt_pre = short_pulse_cnt_cur; - - // Get long pulse count, need carefully handle the counter overflow - long_pulse_cnt_cur = (regf98_value & 0x0000ff00) >> 8; - if (long_pulse_cnt_cur >= priv->long_pulse_cnt_pre) - long_pulse_cnt_inc = long_pulse_cnt_cur - priv->long_pulse_cnt_pre; - else - long_pulse_cnt_inc = long_pulse_cnt_cur; - priv->long_pulse_cnt_pre = long_pulse_cnt_cur; - - total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; - - if (priv->pshare->rf_ft_var.dfs_det_print) { - panic_printk("=====================================================================\n"); - panic_printk("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d] CCA_count_inc[%d] FA_CRCOK_ratio[%d]\n", - Total_CRC_OK_cnt_inc, VHT_CRC_ok_cnt_inc, HT_CRC_ok_cnt_inc, LEG_CRC_ok_cnt_inc, FA_count_inc, CCA_count_inc, FA_CRCOK_ratio); - panic_printk("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", - priv->ini_gain_cur, priv->st_L2H_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc); - panic_printk("Throughput: %luMbps\n", (throughput>>17)); - // panic_printk("nhm_duty_cycle = %d\n", (100-((CCX_INFO->NHM_result_total * 100) >> 8))); - reg918_value = PHY_QueryBBReg(priv, 0x918, 0xffffffff); - reg91c_value = PHY_QueryBBReg(priv, 0x91c, 0xffffffff); - reg920_value = PHY_QueryBBReg(priv, 0x920, 0xffffffff); - reg924_value = PHY_QueryBBReg(priv, 0x924, 0xffffffff); - reg19e4_value = PHY_QueryBBReg(priv, 0x19e4, 0xffffffff); - panic_printk("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x] 0x19e4[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value, reg19e4_value); - } - - // read hw dfs detection flag - DFS_tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; - DFS_tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; - - if (DFS_tri_short_pulse) { - //RTL_W32(0x920, RTL_R32(0x920) | BIT(24)); - //RTL_W32(0x920, RTL_R32(0x920) & ~BIT(24)); - //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); - //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); - } - if (DFS_tri_long_pulse) { - //RTL_W32(0x920, RTL_R32(0x920) | BIT(25)); - //RTL_W32(0x920, RTL_R32(0x920) & ~BIT(25)); - //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); - //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); - // MKK - if (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2) { - if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && - (priv->pmib->dot11RFEntry.dot11channel <= 64)) { - DFS_tri_long_pulse = 0; - } - } - // ETSI - if (priv->pshare->rf_ft_var.manual_dfs_regdomain == 3) { - DFS_tri_long_pulse = 0; - } - } - - st_L2H_new = priv->st_L2H_cur; - priv->pulse_flag_hist[priv->mask_idx] = DFS_tri_short_pulse | DFS_tri_long_pulse; - priv->pulse_type_hist[priv->mask_idx] = (DFS_tri_long_pulse)? 1 : 0; - - //max_sht_pusle_cnt_th = PHY_QueryBBReg(priv, 0x920, 0x000f0000)-1; //read 920[19:16] - max_sht_pusle_cnt_th = priv->pshare->rf_ft_var.dfs_max_sht_pusle_cnt_th; - if (priv->pshare->rf_ft_var.dfs_det_print3) - panic_printk("max_sht_pusle_cnt_th = %d\n", max_sht_pusle_cnt_th); - - if(priv->idle_flag == 1){ - if(priv->pshare->rf_ft_var.dfs_psd_idle_on == 1){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK(flags); - Scan_BB_PSD(ODMPTR, PSD_report_right, PSD_report_left, 20, 0x3e); - SMP_UNLOCK(flags); - RESTORE_INT(flags); - } - else{ - /*for (i=0; i<20; i++) { - PSD_report_right[i] = 0; - PSD_report_left[i] = 0; - }*/ - } - } - else{ - if(priv->pshare->rf_ft_var.dfs_psd_TP_on == 1){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK(flags); - Scan_BB_PSD(ODMPTR, PSD_report_right, PSD_report_left, 20, 0x3e); - SMP_UNLOCK(flags); - RESTORE_INT(flags); - } - else{ - for (i=0; i<20; i++) { - PSD_report_right[i] = 0; - PSD_report_left[i] = 0; - } - } - } - - for (i=0; i<20; i++) { - PSD_report_right[i] = (-110 + 0x3e) - 39 + PSD_report_right[i]; - PSD_report_left[i] = (-110 + 0x3e) - 39 + PSD_report_left[i]; - } - if (priv->pshare->rf_ft_var.dfs_det_print_psd) { - panic_printk("PSD right: "); - for (i=0; i<20; i++) - panic_printk("%d ", PSD_report_right[i]); - //panic_printk("\n"); - panic_printk(" PSD left: "); - for (i=0; i<20; i++) - panic_printk("%d ", PSD_report_left[i]); - panic_printk("\n"); - } - - fault_flag_det = 0; - fault_flag_psd = 0; - fa_flag = 0; - // ETSI - if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ - fa_mask_mid_th = priv->pshare->rf_ft_var.dfs_fa_cnt_mid + 20; - fa_mask_lower_th = priv->pshare->rf_ft_var.dfs_fa_cnt_lower + 40; - } - else{ - fa_mask_mid_th = priv->pshare->rf_ft_var.dfs_fa_cnt_mid; - fa_mask_lower_th = priv->pshare->rf_ft_var.dfs_fa_cnt_lower; - } - //if (max_fa_in_hist >= fa_mask_mid_th || total_fa_in_hist >= priv->pshare->rf_ft_var.dfs_fa_hist || pre_post_now_acc_fa_in_hist >= fa_mask_mid_th){ - /*if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) - index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; - else - index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; */ - /* priv->radar_det_mask_hist[index] = 1; - if (priv->pulse_flag_hist[index] == 1){ - priv->pulse_flag_hist[index] = 0; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("Radar is masked : FA mask case3\n"); - } - } - fa_flag = 1; - } - if (((FA_count_inc >= priv->pshare->rf_ft_var.dfs_dpt_fa_th_upper) && (short_pulse_cnt_inc > max_sht_pusle_cnt_th)) || - (priv->ini_gain_cur >= priv->pshare->rf_ft_var.dpt_ini_gain_th)) { - st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max; - if (priv->pshare->rf_ft_var.dfs_det_print3) - panic_printk("[1] st_L2H_new %x\n", st_L2H_new); - priv->radar_det_mask_hist[priv->mask_idx] = 1; - if (priv->pulse_flag_hist[priv->mask_idx] == 1){ - priv->pulse_flag_hist[priv->mask_idx] = 0; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("Radar is masked : FA mask case1\n"); - } - } - fa_flag = 1; - } - else if (((FA_count_inc >= fa_mask_mid_th) || - ((FA_count_inc >= fa_mask_lower_th) && - (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_inc_ratio * priv->FA_count_inc_pre))) - && (short_pulse_cnt_inc > max_sht_pusle_cnt_th)) { - if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) - st_L2H_new += 2; - if (priv->pshare->rf_ft_var.dfs_det_print3) - panic_printk("[2] st_L2H_new %x\n", st_L2H_new); - priv->radar_det_mask_hist[priv->mask_idx] = 1; - if (priv->pulse_flag_hist[priv->mask_idx] == 1){ - priv->pulse_flag_hist[priv->mask_idx] = 0; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("Radar is masked : FA mask case2\n"); - } - } - fa_flag = 1; - } - else - { - if (((FA_CRCOK_ratio > priv->pshare->rf_ft_var.dfs_fa_ratio_th) && - (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_lower) && - (Total_CRC_OK_cnt_inc > priv->pshare->rf_ft_var.dfs_crc32_cnt_lower)) || - ((short_pulse_cnt_inc <= max_sht_pusle_cnt_th) && (short_pulse_cnt_inc != 0) && - (priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) || - (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_upper)) - priv->radar_det_mask_hist[priv->mask_idx] = 1; - else - priv->radar_det_mask_hist[priv->mask_idx] = 0; - } -*/ - priv->radar_det_mask_hist[priv->mask_idx] = 0; - - if ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)){ - if (((CCX_INFO->NHM_result_total * 100) >> 8) >= priv->pshare->rf_ft_var.dfs_nhm_duty_cycle_th) { - if (priv->pulse_flag_hist[index] == 1) { - priv->pulse_flag_hist[index] = 0; - if (priv->pshare->rf_ft_var.dfs_det_print4) { - panic_printk("Radar is masked : NHM duty cycle over TH\n"); - } - } - } - } - if (priv->pshare->rf_ft_var.dfs_det_print2) { - panic_printk("mask_idx: %d\n", priv->mask_idx); - panic_printk("radar_det_mask_hist: "); - for (i=0; ipshare->rf_ft_var.dfs_det_hist_len; i++) - panic_printk("%d ", priv->radar_det_mask_hist[i]); - panic_printk("pulse_flag_hist: "); - for (i=0; ipshare->rf_ft_var.dfs_det_hist_len; i++) - panic_printk("%d ", priv->pulse_flag_hist[i]); - panic_printk("fa_inc_hist: "); - for (i=0; i<5; i++) - panic_printk("%d ", priv->fa_inc_hist[i]); - panic_printk("\n"); - panic_printk("max_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",max_fa_in_hist,pre_post_now_acc_fa_in_hist); - } - - /*memcpy(&priv->PSD_report_right[priv->mask_idx][0], PSD_report_right, 20*sizeof(int)); - memcpy(&priv->PSD_report_left[priv->mask_idx][0], PSD_report_left, 20*sizeof(int)); - - for (i=0; i<20; i++) { - priv->max_hold_right[i] = -1000; - priv->max_hold_left[i] = -1000; - } - - for (k=0; k<5; k++) { - for (i=0; i<20; i++) { - if (priv->PSD_report_right[k][i] > priv->max_hold_right[i]) - priv->max_hold_right[i] = priv->PSD_report_right[k][i]; - if (priv->PSD_report_left[k][i] > priv->max_hold_left[i]) - priv->max_hold_left[i] = priv->PSD_report_left[k][i]; - } - } - - if ((priv->pshare->rf_ft_var.dfs_psd_op == 1) && (priv->idle_flag == 0)) - { - int right_index_start, left_index_end; - int avg_1 = (priv->max_hold_right[0]+priv->max_hold_right[1]+priv->max_hold_right[2])/3; - int avg_2 = (priv->max_hold_right[17]+priv->max_hold_right[18]+priv->max_hold_right[19])/3; - max_right = -1000; - if(RTL_ABS(avg_1, avg_2) <= 3) - right_index_start=2; - else - right_index_start=11; - for (i=right_index_start; i<20; i++) { - if ((i != 10) && (max_right < priv->max_hold_right[i])) - max_right = priv->max_hold_right[i]; - } - - avg_1 = (priv->max_hold_left[0]+priv->max_hold_left[1]+priv->max_hold_left[2])/3; - avg_2 = (priv->max_hold_left[17]+priv->max_hold_left[18]+priv->max_hold_left[19])/3; - max_left = -1000; - if (RTL_ABS(avg_1, avg_2) <= 3) - left_index_end=20; - else - left_index_end=8; - for (i=0; imax_hold_left[i])) - max_left = priv->max_hold_left[i]; - } - if(max_right == 0){ - max_right = -99; - } - if(max_left == 0){ - max_left = -99; - } - } - else - { - max_right = -1000; - for (i=2; i<20; i++) { - if ((i != 10) && (max_right < priv->max_hold_right[i])) - max_right = priv->max_hold_right[i]; - } - max_left = -1000; - for (i=0; i<20; i++) { - if ((i != 10) && (max_left < priv->max_hold_left[i])) - max_left = priv->max_hold_left[i]; - } - if(max_right == 0){ - max_right = -99; - } - if(max_left == 0){ - max_left = -99; - } - }*/ - - max_right = -99; - max_left = -99; - - if (priv->pshare->rf_ft_var.dfs_det_print) - panic_printk("max_right %d, max_left %d\n", max_right, max_left); - - /*if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) - index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; - else - index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;*/ - - // use PSD detection result - if ((max_right > (0-(int)priv->pshare->rf_ft_var.dfs_psd_pw_th)) || (max_left > (0-(int)priv->pshare->rf_ft_var.dfs_psd_pw_th))) { - if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) { - st_L2H_tmp = 110 + ((max_right > max_left)? max_right:max_left) - priv->pshare->rf_ft_var.dfs_psd_fir_decay; - if (st_L2H_tmp > priv->st_L2H_cur) - st_L2H_new = st_L2H_tmp; - } - if (priv->pshare->rf_ft_var.dfs_det_print3) - panic_printk("[3] st_L2H_new %x\n", st_L2H_new); - - if (priv->pshare->rf_ft_var.dfs_det_print) - panic_printk("st_L2H_cur %x pwdb_th %x\n", st_L2H_new, priv->pwdb_th); - - fault_flag_psd = 1; - if (priv->pulse_flag_hist[index] == 1){ - priv->pulse_flag_hist[index] = 0; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("Radar is masked : PSD mask\n"); - } - } - priv->radar_det_mask_hist[index] = 1; - } - - sum = 0; - for (k=0; kpshare->rf_ft_var.dfs_det_hist_len; k++) { - if (priv->radar_det_mask_hist[k] == 1) - sum++; - } - - if (priv->mask_hist_checked <= priv->pshare->rf_ft_var.dfs_det_hist_len) - priv->mask_hist_checked++; - - //only the decision result of short pulse needs to refer the FA decision results - if ((priv->mask_hist_checked >= priv->pshare->rf_ft_var.dfs_det_hist_len) && - //(DFS_tri_long_pulse || DFS_tri_short_pulse) && - priv->pulse_flag_hist[index]) - { - //if ((sum <= priv->pshare->rf_ft_var.dfs_det_sum_th) && - // (fa_flag == 0)) - if (sum <= priv->pshare->rf_ft_var.dfs_det_sum_th) - { -#if defined(CONFIG_WLAN_HAL_8814AE) || defined(CONFIG_WLAN_HAL_8822BE) - if(((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)) - && priv->pshare->rf_ft_var.dfs_radar_diff_on) - { - if (priv->pulse_type_hist[index] == 0){ - priv->radar_type = 0; - if (priv->pulsewidth_flag && priv->pulseinterval_flag && priv->pri_type3_4_flag){ - priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("hist_idx= %d\n", (priv->hist_idx+3)%4); - for (j=0;j<4;j++){ - for (i=0;i<6;i++){ - panic_printk("pluseinterval_hold = %d ", priv->pluseinterval_hold[j][i]); - } - panic_printk("\n"); - } - panic_printk("\n"); - for (j=0;j<4;j++){ - for (i=0;i<6;i++){ - panic_printk("plusewidth_hold = %d ", priv->plusewidth_hold[j][i]); - } - panic_printk("\n"); - } - panic_printk("\n"); - panic_printk("idle_flag = %d\n",priv->idle_flag); - panic_printk("plusewidth_hold_sum = %d %d %d %d %d %d\n", - priv->plusewidth_hold_sum[0], priv->plusewidth_hold_sum[1],priv->plusewidth_hold_sum[2],priv->plusewidth_hold_sum[3],priv->plusewidth_hold_sum[4],priv->plusewidth_hold_sum[5]); - panic_printk("pluseinterval_hold_sum = %d %d %d %d %d %d\n", - priv->pluseinterval_hold_sum[0], priv->pluseinterval_hold_sum[1],priv->pluseinterval_hold_sum[2],priv->pluseinterval_hold_sum[3],priv->pluseinterval_hold_sum[4],priv->pluseinterval_hold_sum[5]); - } - } - else{ - if(priv->pshare->rf_ft_var.dfs_det_print4){ - if (priv->pulse_flag_hist[index] && (priv->pulseinterval_flag==0)){ - panic_printk("PRI criterion is not satisfied!\n"); - panic_printk("pulseinterval_variation = %d\n",priv->pri_std); - if(priv->pri_cond1 == 0) - panic_printk("pri_cond1 is not satisfied!\n"); - if(priv->pri_cond2 == 0) - panic_printk("pri_cond2 is not satisfied!\n"); - if(priv->pri_cond3 == 0){ - panic_printk("pri_cond3 is not satisfied!\n"); - } - if(priv->pri_cond4 == 0) - panic_printk("pri_cond4 is not satisfied!\n"); - if(priv->pri_cond5 == 0) - panic_printk("pri_cond5 is not satisfied!\n"); - } - if (priv->pulse_flag_hist[index] && (priv->pulsewidth_flag==0)){ - panic_printk("PW criterion is not satisfied!\n"); - panic_printk("pulsewidth_variation = %d\n",priv->pw_std); - if(priv->pw_cond1 == 0) - panic_printk("pw_cond1 is not satisfied!\n"); - if(priv->pw_cond2 == 0) - panic_printk("pw_cond2 is not satisfied!\n"); - if(priv->pw_cond3 == 0){ - panic_printk("pw_cond3 is not satisfied!\n"); - } - } - if (priv->pulse_flag_hist[index] && (priv->pri_type3_4_flag==0)){ - panic_printk("pri_type3_4 criterion is not satisfied!\n"); - if(priv->pri_type3_4_cond1 == 0) - panic_printk("pri_type3_4_cond1 is not satisfied!\n"); - if(priv->pri_type3_4_cond2 == 0) - panic_printk("pri_type3_4_cond2 is not satisfied!\n"); - } - panic_printk("hist_idx= %d\n", (priv->hist_idx+3)%4); - for (j=0;j<4;j++){ - for (i=0;i<6;i++){ - panic_printk("pluseinterval_hold = %d ", priv->pluseinterval_hold[j][i]); - } - panic_printk("\n"); - } - panic_printk("\n"); - for (j=0;j<4;j++){ - for (i=0;i<6;i++){ - panic_printk("plusewidth_hold = %d ", priv->plusewidth_hold[j][i]); - } - panic_printk("\n"); - } - panic_printk("\n"); - panic_printk("idle_flag = %d\n",priv->idle_flag); - panic_printk("plusewidth_hold_sum = %d %d %d %d %d %d\n", - priv->plusewidth_hold_sum[0], priv->plusewidth_hold_sum[1],priv->plusewidth_hold_sum[2],priv->plusewidth_hold_sum[3],priv->plusewidth_hold_sum[4],priv->plusewidth_hold_sum[5]); - panic_printk("pluseinterval_hold_sum = %d %d %d %d %d %d\n", - priv->pluseinterval_hold_sum[0], priv->pluseinterval_hold_sum[1],priv->pluseinterval_hold_sum[2],priv->pluseinterval_hold_sum[3],priv->pluseinterval_hold_sum[4],priv->pluseinterval_hold_sum[5]); - } - } - } - else{ - priv->radar_type = 1; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("\n"); - panic_printk("idle_flag = %d\n",priv->idle_flag); - panic_printk("long_radar_plusewidth_hold_sum = %d %d %d %d %d %d\n", - priv->plusewidth_long_hold_sum[0], priv->plusewidth_long_hold_sum[1],priv->plusewidth_long_hold_sum[2],priv->plusewidth_long_hold_sum[3],priv->plusewidth_long_hold_sum[4],priv->plusewidth_long_hold_sum[5]); - panic_printk("long_radar_pluseinterval_hold_sum = %d %d %d %d %d %d\n", - priv->pluseinterval_long_hold_sum[0], priv->pluseinterval_long_hold_sum[1],priv->pluseinterval_long_hold_sum[2],priv->pluseinterval_long_hold_sum[3],priv->pluseinterval_long_hold_sum[4],priv->pluseinterval_long_hold_sum[5]); - } - /* Long radar should satisfy three conditions */ - if(priv->long_radar_flag == 1){ - priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect - } - else{ - if (priv->pshare->rf_ft_var.dfs_det_print4){ - if(priv->pw_long_cond1 == 0) - panic_printk("--pw_long_cond1 is not satisfied!--\n"); - if(priv->pw_long_cond2 == 0) - panic_printk("--pw_long_cond2 is not satisfied!--\n"); - if(priv->pri_long_cond1 == 0) - panic_printk("--pri_long_cond1 is not satisfied!--\n"); - } - } - } - - } - else -#endif - { - if (priv->pulse_type_hist[index] == 0) - priv->radar_type = 0; - else if (priv->pulse_type_hist[index] == 1) - priv->radar_type = 1; - priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect - } - } - else { - fault_flag_det = 1; - if (priv->pshare->rf_ft_var.dfs_det_print4){ - panic_printk("Radar is masked : mask_hist large than thd\n"); - } - } - } - - priv->mask_idx++; - if (priv->mask_idx == priv->pshare->rf_ft_var.dfs_det_hist_len) - priv->mask_idx = 0; - - if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) { - //if (total_pulse_count_inc < priv->pshare->rf_ft_var.dfs_dpt_pulse_th_lower) { - // // limit the ST value to absoulte lower bound 0x1c - // st_L2H_new -= 4; - // if (priv->pshare->rf_ft_var.dfs_det_print3) - // panic_printk("[4] st_L2H_new %x\n", st_L2H_new); - //} - ///*else if (total_pulse_count_inc < priv->pshare->rf_ft_var.dfs_dpt_pulse_th_mid) { - // // limit the ST value to absoulte lower bound 0x1c - // st_L2H_new -= 2; - // if (priv->pshare->rf_ft_var.dfs_det_print3) - // panic_printk("[5] st_L2H_new %x\n", st_L2H_new); - //}*/ - //else if (ini_gain_inc < 0){ - // st_L2H_new += ini_gain_inc; - // if (priv->pshare->rf_ft_var.dfs_det_print3) - // panic_printk("[6] st_L2H_new %x\n", st_L2H_new); - //} - ///*else if ((total_pulse_count_inc < max_sht_pusle_cnt_th) && - // (((priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17) <= priv->pshare->rf_ft_var.dfs_psd_tp_th)) { - // st_L2H_new += priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_th; - //}*/ - if (priv->ini_gain_cur < priv->pshare->rf_ft_var.dpt_ini_gain_th) { - if ((priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) - st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min + priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_offset; - else - st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; - } - } - else{ - - - if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) - st_L2H_new += 2; - if (priv->pshare->rf_ft_var.dfs_det_print3) - panic_printk("[7] st_L2H_new %x\n", st_L2H_new); - - - if (DFS_tri_short_pulse) { - //RTL_W32(0x920, RTL_R32(0x920) | (BIT(24) | BIT(28))); - //RTL_W32(0x920, RTL_R32(0x920) & ~(BIT(24) | BIT(28))); - //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); - //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); - } - if (DFS_tri_long_pulse) { - //RTL_W32(0x920, RTL_R32(0x920) | (BIT(25) | BIT(28))); - //RTL_W32(0x920, RTL_R32(0x920) & ~(BIT(25) | BIT(28))); - //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); - //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); - } - } - - if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20){ - if(priv->pshare->highTP_found_pstat != NULL){ - if(priv->pshare->highTP_found_pstat->rf_info.mimorssi[0] >= 20 && priv->pshare->highTP_found_pstat->rf_info.mimorssi[0] <= 30) - st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min - 19 + priv->pshare->highTP_found_pstat->rf_info.mimorssi[0]; - } - } - - if ((st_L2H_new != priv->st_L2H_cur)) { - // limit the ST value to absoulte lower bound 0x22 - // limit the ST value to absoulte upper bound 0x4e - if (st_L2H_new < priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min) { - if ((priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) - priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min + priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_offset; - else - priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; - //priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; - } - else if (st_L2H_new > priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max) - priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max; - else - priv->st_L2H_cur = st_L2H_new; - RTL_W8(0x91c, priv->st_L2H_cur); - - priv->pwdb_th = ((int)priv->st_L2H_cur - (int)priv->ini_gain_cur)/2 + priv->pshare->rf_ft_var.dfs_pwdb_scalar_factor; - priv->pwdb_th = MAX_NUM(priv->pwdb_th, (int)priv->pshare->rf_ft_var.dfs_pwdb_th); // limit the pwdb value to absoulte lower bound 0xa - priv->pwdb_th = MIN_NUM(priv->pwdb_th, 0x1f); // limit the pwdb value to absoulte upper bound 0x1f - PHY_SetBBReg(priv, 0x918, 0x00001f00, priv->pwdb_th); - } - - if (priv->pshare->rf_ft_var.dfs_det_print2) { - panic_printk("fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",fault_flag_det, fault_flag_psd, priv->pmib->dot11DFSEntry.DFS_detected ); - } - - priv->FA_count_inc_pre = FA_count_inc; - if (PHY_QueryBBReg(priv, 0xf98, BIT(17)) || PHY_QueryBBReg(priv, 0xf98, BIT(19))){ - RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); - RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); - } -} - - -void rtl8192cd_dfs_dynamic_setting(struct rtl8192cd_priv *priv) -{ - unsigned char peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0; - unsigned char peak_window_cur=0, nb2wb_th_cur=0; - - if ((priv->idle_flag == 1)) { // idle (no traffic) - peak_th_cur = 3; - short_pulse_cnt_th_cur = 6; - long_pulse_cnt_th_cur = 9; - peak_window_cur = 2; - three_peak_opt_cur = 0; - three_peak_th2_cur = 2; - // MKK - if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2){ - if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && - (priv->pmib->dot11RFEntry.dot11channel <= 64)) { - short_pulse_cnt_th_cur = priv->pshare->rf_ft_var.dfs_pc0_th_idle_w53; - long_pulse_cnt_th_cur = 15; - three_peak_th2_cur = 0; - } - else { - short_pulse_cnt_th_cur = priv->pshare->rf_ft_var.dfs_pc0_th_idle_w56; - three_peak_th2_cur = 0; - long_pulse_cnt_th_cur = 10; - } - } - // FCC - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ - three_peak_th2_cur = 0; - } - // ETSI - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ - long_pulse_cnt_th_cur = 15; - if((priv->ch_120_132_CAC_end == 0) && IS_METEOROLOGY_CHANNEL(priv->pmib->dot11RFEntry.dot11channel)){ - peak_th_cur = 2; - three_peak_th2_cur = 0; - short_pulse_cnt_th_cur = 7; - } - else{ - three_peak_th2_cur = 0; - short_pulse_cnt_th_cur = 7; - } - } - else{ // default: FCC - } - } - else{ // in service (with TP) - peak_th_cur = 2; - short_pulse_cnt_th_cur = 6; - long_pulse_cnt_th_cur = 7; - peak_window_cur = 2; - three_peak_opt_cur = 0; - three_peak_th2_cur = 2; - // MKK - if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2){ - if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && - (priv->pmib->dot11RFEntry.dot11channel <= 64)) { - long_pulse_cnt_th_cur = 15; - short_pulse_cnt_th_cur = 5; // for high duty cycle - three_peak_th2_cur = 0; - } - else { - three_peak_opt_cur = 0; - three_peak_th2_cur = 0; - long_pulse_cnt_th_cur = 8; - } - } - // FCC - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ - } - // ETSI - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ - long_pulse_cnt_th_cur = 15; - short_pulse_cnt_th_cur = 5; - three_peak_opt_cur = 0; - } - else{ - } - } - if((priv->peak_th != peak_th_cur)){ - PHY_SetBBReg(priv, 0x918, 0x00030000, peak_th_cur); - } - if((priv->short_pulse_cnt_th != short_pulse_cnt_th_cur)){ - PHY_SetBBReg(priv, 0x920, 0x000f0000, short_pulse_cnt_th_cur); - } - if((priv->long_pulse_cnt_th != long_pulse_cnt_th_cur)){ - PHY_SetBBReg(priv, 0x920, 0x00f00000, long_pulse_cnt_th_cur); - } - if((priv->peak_window != peak_window_cur)){ - PHY_SetBBReg(priv, 0x920, 0x00000300, peak_window_cur); - } - if((priv->nb2wb_th != nb2wb_th_cur)){ - PHY_SetBBReg(priv, 0x920, 0x0000e000, nb2wb_th_cur); - } - if((priv->three_peak_opt != three_peak_opt_cur)){ - PHY_SetBBReg(priv, 0x924, 0x00000180, three_peak_opt_cur); - } - if((priv->three_peak_th2 != three_peak_th2_cur)){ - PHY_SetBBReg(priv, 0x924, 0x00007000, three_peak_th2_cur); - } - - priv->peak_th = peak_th_cur; - priv->short_pulse_cnt_th = short_pulse_cnt_th_cur; - priv->long_pulse_cnt_th = long_pulse_cnt_th_cur; - priv->peak_window = peak_window_cur; - priv->nb2wb_th = nb2wb_th_cur; - priv->three_peak_opt = three_peak_opt_cur; - priv->three_peak_th2 = three_peak_th2_cur; -} - -#if defined(CONFIG_WLAN_HAL_8814AE) || defined(CONFIG_WLAN_HAL_8822BE) - -void rtl8192cd_radar_type_differentiation(struct rtl8192cd_priv *priv) -{ - unsigned char i, need_reset, g_ti_cur[16], g_pw_cur[6], g_pri_cur[6], g_ti_inc[16], g_pw_inc[6], g_pri_inc[6]; // ti = tone index, pw = pulse width, pri = pulse repetition interval - unsigned int g_total, g0_ratio, g1_ratio, g2_ratio, g3_ratio, g4_ratio, g5_ratio; - unsigned int regf98_value; - unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, short_pulse_th; - unsigned char dfs_plusewidth_thd1, dfs_plusewidth_thd2, dfs_plusewidth_thd3, dfs_plusewidth_thd4, dfs_plusewidth_thd5; - unsigned int dfs_hist1_peak_index, dfs_hist2_peak_index, dfs_hist1_pulse_width, dfs_hist2_pulse_width, dfs_hist1_pulse_rep_intvl, dfs_hist2_pulse_rep_intvl; - unsigned char g_plusewidth[6],j,g_peakindex[16]; - unsigned int g_plusewidth_total,g_peakindex_total,g_mask_32; - - regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff); - DFS_tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; - DFS_tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; - short_pulse_th = PHY_QueryBBReg(priv, 0x920, 0x000f0000); - - PHY_SetBBReg(priv, 0x19b8, 0x40, 0); // switch 0xf5c & 0xf74 to DFS report - // read peak index hist report - PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 0); // report selection = 0 (peak index) - /*g_ti_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xf0000000); - if (g_ti_cur[0] >= priv->g_ti_pre[0]) - g_ti_inc[0] = g_ti_cur[0] - priv->g_ti_pre[0]; - else - g_ti_inc[0] = g_ti_cur[0]; - priv->g_ti_pre[0] = g_ti_cur[0]; - - g_ti_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x0f000000); - if (g_ti_cur[1] >= priv->g_ti_pre[1]) - g_ti_inc[1] = g_ti_cur[1] - priv->g_ti_pre[1]; - else - g_ti_inc[1] = g_ti_cur[1]; - priv->g_ti_pre[1] = g_ti_cur[1]; - - g_ti_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x00f00000); - if (g_ti_cur[2] >= priv->g_ti_pre[2]) - g_ti_inc[2] = g_ti_cur[2] - priv->g_ti_pre[2]; - else - g_ti_inc[2] = g_ti_cur[2]; - priv->g_ti_pre[2] = g_ti_cur[2]; - - g_ti_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000f0000); - if (g_ti_cur[3] >= priv->g_ti_pre[3]) - g_ti_inc[3] = g_ti_cur[3] - priv->g_ti_pre[3]; - else - g_ti_inc[3] = g_ti_cur[3]; - priv->g_ti_pre[3] = g_ti_cur[3]; - - g_ti_cur[4] = PHY_QueryBBReg(priv, 0xf74, 0x0000f000); - if (g_ti_cur[4] >= priv->g_ti_pre[4]) - g_ti_inc[4] = g_ti_cur[4] - priv->g_ti_pre[4]; - else - g_ti_inc[4] = g_ti_cur[4]; - priv->g_ti_pre[4] = g_ti_cur[4]; - - g_ti_cur[5] = PHY_QueryBBReg(priv, 0xf74, 0x00000f00); - if (g_ti_cur[5] >= priv->g_ti_pre[5]) - g_ti_inc[5] = g_ti_cur[5] - priv->g_ti_pre[5]; - else - g_ti_inc[5] = g_ti_cur[5]; - priv->g_ti_pre[5] = g_ti_cur[5]; - - g_ti_cur[6] = PHY_QueryBBReg(priv, 0xf74, 0x000000f0); - if (g_ti_cur[6] >= priv->g_ti_pre[6]) - g_ti_inc[6] = g_ti_cur[6] - priv->g_ti_pre[6]; - else - g_ti_inc[6] = g_ti_cur[6]; - priv->g_ti_pre[6] = g_ti_cur[6]; - - g_ti_cur[7] = PHY_QueryBBReg(priv, 0xf74, 0x0000000f); - if (g_ti_cur[7] >= priv->g_ti_pre[7]) - g_ti_inc[7] = g_ti_cur[7] - priv->g_ti_pre[7]; - else - g_ti_inc[7] = g_ti_cur[7]; - priv->g_ti_pre[7] = g_ti_cur[7]; - - g_ti_cur[8] = PHY_QueryBBReg(priv, 0xf5c, 0xf0000000); - if (g_ti_cur[8] >= priv->g_ti_pre[8]) - g_ti_inc[8] = g_ti_cur[8] - priv->g_ti_pre[8]; - else - g_ti_inc[8] = g_ti_cur[8]; - priv->g_ti_pre[8] = g_ti_cur[8]; - - g_ti_cur[9] = PHY_QueryBBReg(priv, 0xf5c, 0x0f000000); - if (g_ti_cur[9] >= priv->g_ti_pre[9]) - g_ti_inc[9] = g_ti_cur[9] - priv->g_ti_pre[9]; - else - g_ti_inc[9] = g_ti_cur[9]; - priv->g_ti_pre[9] = g_ti_cur[9]; - - g_ti_cur[10] = PHY_QueryBBReg(priv, 0xf5c, 0x00f00000); - if (g_ti_cur[10] >= priv->g_ti_pre[10]) - g_ti_inc[10] = g_ti_cur[10] - priv->g_ti_pre[10]; - else - g_ti_inc[10] = g_ti_cur[10]; - priv->g_ti_pre[10] = g_ti_cur[10]; - - g_ti_cur[11] = PHY_QueryBBReg(priv, 0xf5c, 0x000f0000); - if (g_ti_cur[11] >= priv->g_ti_pre[0]) - g_ti_inc[11] = g_ti_cur[11] - priv->g_ti_pre[11]; - else - g_ti_inc[11] = g_ti_cur[11]; - priv->g_ti_pre[11] = g_ti_cur[11]; - - g_ti_cur[12] = PHY_QueryBBReg(priv, 0xf5c, 0x0000f000); - if (g_ti_cur[12] >= priv->g_ti_pre[12]) - g_ti_inc[12] = g_ti_cur[12] - priv->g_ti_pre[12]; - else - g_ti_inc[12] = g_ti_cur[12]; - priv->g_ti_pre[12] = g_ti_cur[12]; - - g_ti_cur[13] = PHY_QueryBBReg(priv, 0xf5c, 0x00000f00); - if (g_ti_cur[13] >= priv->g_ti_pre[13]) - g_ti_inc[13] = g_ti_cur[13] - priv->g_ti_pre[13]; - else - g_ti_inc[13] = g_ti_cur[13]; - priv->g_ti_pre[13] = g_ti_cur[13]; - - g_ti_cur[14] = PHY_QueryBBReg(priv, 0xf5c, 0x000000f0); - if (g_ti_cur[14] >= priv->g_ti_pre[14]) - g_ti_inc[14] = g_ti_cur[14] - priv->g_ti_pre[14]; - else - g_ti_inc[14] = g_ti_cur[14]; - priv->g_ti_pre[14] = g_ti_cur[14]; - - g_ti_cur[15] = PHY_QueryBBReg(priv, 0xf5c, 0x0000000f); - if (g_ti_cur[15] >= priv->g_ti_pre[15]) - g_ti_inc[15] = g_ti_cur[15] - priv->g_ti_pre[15]; - else - g_ti_inc[15] = g_ti_cur[15]; - priv->g_ti_pre[15] = g_ti_cur[15]; - - // read pulse width hist report - PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 1); // report selection = 1 (pulse width) - - g_pw_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xff000000); - if (g_pw_cur[0] >= priv->g_pw_pre[0]) - g_pw_inc[0] = g_pw_cur[0] - priv->g_pw_pre[0]; - else - g_pw_inc[0] = g_pw_cur[0]; - priv->g_pw_pre[0] = g_pw_cur[0]; - - g_pw_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x00ff0000); - if (g_pw_cur[1] >= priv->g_pw_pre[1]) - g_pw_inc[1] = g_pw_cur[1] - priv->g_pw_pre[1]; - else - g_pw_inc[1] = g_pw_cur[1]; - priv->g_pw_pre[1] = g_pw_cur[1]; - - g_pw_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x0000ff00); - if (g_pw_cur[2] >= priv->g_pw_pre[2]) - g_pw_inc[2] = g_pw_cur[2] - priv->g_pw_pre[2]; - else - g_pw_inc[2] = g_pw_cur[2]; - priv->g_pw_pre[2] = g_pw_cur[2]; - - g_pw_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000000ff); - if (g_pw_cur[3] >= priv->g_pw_pre[3]) - g_pw_inc[3] = g_pw_cur[3] - priv->g_pw_pre[3]; - else - g_pw_inc[3] = g_pw_cur[3]; - priv->g_pw_pre[3] = g_pw_cur[3]; - - g_pw_cur[4] = PHY_QueryBBReg(priv, 0xf5c, 0xff000000); - if (g_pw_cur[4] >= priv->g_pw_pre[4]) - g_pw_inc[4] = g_pw_cur[4] - priv->g_pw_pre[4]; - else - g_pw_inc[4] = g_pw_cur[4]; - priv->g_pw_pre[4] = g_pw_cur[4]; - - g_pw_cur[5] = PHY_QueryBBReg(priv, 0xf5c, 0x00ff0000); - if (g_pw_cur[5] >= priv->g_pw_pre[5]) - g_pw_inc[5] = g_pw_cur[5] - priv->g_pw_pre[5]; - else - g_pw_inc[5] = g_pw_cur[5]; - priv->g_pw_pre[5] = g_pw_cur[5]; - - g_total = g_pw_inc[0] + g_pw_inc[1] + g_pw_inc[2] + g_pw_inc[3] + g_pw_inc[4] + g_pw_inc[5]; - if(g_pw_inc[0] == 0) g0_ratio = 0; - else g0_ratio = g_total / g_pw_inc[0]; - if(g_pw_inc[1] == 0) g1_ratio = 0; - else g1_ratio = g_total / g_pw_inc[1]; - if(g_pw_inc[2] == 0) g2_ratio = 0; - else g2_ratio = g_total / g_pw_inc[2]; - if(g_pw_inc[3]== 0) g3_ratio = 0; - else g3_ratio = g_total / g_pw_inc[3]; - if(g_pw_inc[4]== 0) g4_ratio = 0; - else g4_ratio = g_total / g_pw_inc[4]; - if(g_pw_inc[5] == 0) g5_ratio = 0; - else g5_ratio = g_total / g_pw_inc[5]; - - // read pulse repetition interval hist report - PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 3); // report selection = 3 (pulse repetition interval) - g_pri_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xff000000); - if (g_pri_cur[0] >= priv->g_pri_pre[0]) - g_pri_inc[0] = g_pri_cur[0] - priv->g_pri_pre[0]; - else - g_pri_inc[0] = g_pri_cur[0]; - priv->g_pri_pre[0] = g_pri_cur[0]; - - g_pri_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x00ff0000); - if (g_pri_cur[1] >= priv->g_pri_pre[1]) - g_pri_inc[1] = g_pri_cur[1] - priv->g_pri_pre[1]; - else - g_pri_inc[1] = g_pri_cur[1]; - priv->g_pri_pre[1] = g_pri_cur[1]; - - g_pri_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x0000ff00); - if (g_pri_cur[2] >= priv->g_pri_pre[2]) - g_pri_inc[2] = g_pri_cur[2] - priv->g_pri_pre[2]; - else - g_pri_inc[2] = g_pri_cur[2]; - priv->g_pri_pre[2] = g_pri_cur[2]; - - g_pri_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000000ff); - if (g_pri_cur[3] >= priv->g_pri_pre[3]) - g_pri_inc[3] = g_pri_cur[3] - priv->g_pri_pre[3]; - else - g_pri_inc[3] = g_pri_cur[3]; - priv->g_pri_pre[3] = g_pri_cur[3]; - - g_pri_cur[4] = PHY_QueryBBReg(priv, 0xf5c, 0xff000000); - if (g_pri_cur[4] >= priv->g_pri_pre[4]) - g_pri_inc[4] = g_pri_cur[4] - priv->g_pri_pre[4]; - else - g_pri_inc[4] = g_pri_cur[4]; - priv->g_pri_pre[4] = g_pri_cur[4]; - - g_pri_cur[5] = PHY_QueryBBReg(priv, 0xf5c, 0x00ff0000); - if (g_pri_cur[5] >= priv->g_pri_pre[5]) - g_pri_inc[5] = g_pri_cur[5] - priv->g_pri_pre[5]; - else - g_pri_inc[5] = g_pri_cur[5]; - priv->g_pri_pre[5] = g_pri_cur[5]; - - need_reset = 0; - for(i = 0; i < 6; i++){ - if((priv->g_pw_pre[i]==255) || (priv->g_pri_pre[i] == 255)){ - need_reset = 1; - } - } - if(1){ - PHY_SetBBReg(priv, 0x19b4, 0x10000000, 1); // reset histogram report - PHY_SetBBReg(priv, 0x19b4, 0x10000000, 0); // continue histogram report - for(i = 0; i < 6; i++){ - priv->g_pw_pre[i]=0; - priv->g_pri_pre[i]=0; - } - for(i = 0; i < 16; i++){ - priv->g_ti_pre[i]=0; - } - }*/ - - if(DFS_tri_short_pulse || DFS_tri_long_pulse){ - //if(1){ -/* if(priv->pshare->rf_ft_var.dfs_print_hist_report){ - dfs_plusewidth_thd1 = PHY_QueryBBReg(priv, 0x19e4, 0xff000000); - dfs_plusewidth_thd2 = PHY_QueryBBReg(priv, 0x19e8, 0x000000ff); - dfs_plusewidth_thd3 = PHY_QueryBBReg(priv, 0x19e8, 0x0000ff00); - dfs_plusewidth_thd4 = PHY_QueryBBReg(priv, 0x19e8, 0x00ff0000); - dfs_plusewidth_thd5 = PHY_QueryBBReg(priv, 0x19e8, 0xff000000); - PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x0); - dfs_hist1_peak_index = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); - dfs_hist2_peak_index = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); - PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x1); - dfs_hist1_pulse_width = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); - dfs_hist2_pulse_width = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); - g_plusewidth[0] = (unsigned char)(dfs_hist2_pulse_width & 0xff000000)>>24; - g_plusewidth[1] = (unsigned char)(dfs_hist2_pulse_width & 0x00ff0000)>>16; - g_plusewidth[2] = (unsigned char)(dfs_hist2_pulse_width & 0x0000ff00)>>8; - g_plusewidth[3] = (unsigned char)dfs_hist2_pulse_width & 0x000000ff; - g_plusewidth[4] = (unsigned char)(dfs_hist1_pulse_width & 0xff000000)>>24; - g_plusewidth[5] = (unsigned char)(dfs_hist1_pulse_width & 0x00ff0000)>>16; - g_plusewidth_total = 0; - - for (i=0; i<6 ; i++) - g_plusewidth_total += g_plusewidth[i]; - - PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x2); - dfs_hist1_pulse_rep_intvl = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); - dfs_hist2_pulse_rep_intvl = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); - PHY_SetBBReg(priv, 0x19b4, 0x10000000, 1); // reset histogram report - PHY_SetBBReg(priv, 0x19b4, 0x10000000, 0); // continue histogram report - panic_printk("dfs_plusewidth_thd=%d %d %d %d %d\n", - dfs_plusewidth_thd1, dfs_plusewidth_thd2, dfs_plusewidth_thd3, dfs_plusewidth_thd4, dfs_plusewidth_thd5); - panic_printk("peak index hist\n"); - panic_printk("dfs_hist_peak_index=%x %x\n", - dfs_hist1_peak_index, dfs_hist2_peak_index); - //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d, g6 = %d, g7 = %d\n", g_ti_inc[0], g_ti_inc[1], g_ti_inc[2], g_ti_inc[3], g_ti_inc[4], g_ti_inc[5], g_ti_inc[6], g_ti_inc[7]); - //panic_printk("g8 = %d, g9 = %d, g10 = %d, g11 = %d, g12 = %d, g13 = %d, g14 = %d, g15 = %d\n", g_ti_inc[8], g_ti_inc[9], g_ti_inc[10], g_ti_inc[11], g_ti_inc[12], g_ti_inc[13], g_ti_inc[14], g_ti_inc[15]); - panic_printk("pulse width hist\n"); - panic_printk("dfs_hist_pulse_width=%x %x\n", - dfs_hist1_pulse_width, dfs_hist2_pulse_width); - panic_printk("g_pulse_width_hist = %x %x %x %x %x %x, g_pulse_width_hist_total = %x\n", - g_plusewidth[0], g_plusewidth[1],g_plusewidth[2],g_plusewidth[3],g_plusewidth[4],g_plusewidth[5],g_plusewidth_total); - - //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d\n",g_pw_inc[0], g_pw_inc[1], g_pw_inc[2], g_pw_inc[3], g_pw_inc[4], g_pw_inc[5]); - //panic_printk("g0_ratio = %d, g1_ratio = %d, g2_ratio = %d, g3_ratio = %d, g4_ratio = %d, g5_ratio = %d\n", g0_ratio, g1_ratio, g2_ratio, g3_ratio, g4_ratio, g5_ratio); - //panic_printk("pulse repetition interval hist\n"); - //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d\n",g_pri_inc[0], g_pri_inc[1], g_pri_inc[2], g_pri_inc[3], g_pri_inc[4], g_pri_inc[5]); - }*/ - - // MKK - if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2) { - if((priv->pmib->dot11RFEntry.dot11channel >= 52) && (priv->pmib->dot11RFEntry.dot11channel <= 64)){ - // classify radar by pulse width hist - if(g_pw_inc[1] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w53 radar type1 is detected!\n"); - } - } - else if(g_pw_inc[3] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w53 radar type2 is detected!\n"); - } - } - else{ - DFS_tri_long_pulse = 0; - DFS_tri_short_pulse = 0; - } - } - else{ - if (DFS_tri_long_pulse){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type7 is detected!\n"); - } - } - else{ - if(g_pw_inc[0] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type1 is detected!\n"); - } - } - else if(g_pw_inc[1] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type2 or type8 is detected!\n"); - } - } - else if(g_pw_inc[2] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type3 is detected!\n"); - } - } - else if(g_pw_inc[1]+g_pw_inc[2]+g_pw_inc[3] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type4 is detected!\n"); - } - } - else if(g_pw_inc[4] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type5 is detected!\n"); - } - } - else if(g_pw_inc[5] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("MKK w56 radar type6 is detected!\n"); - } - } - else{ - DFS_tri_short_pulse = 0; - } - } - } - } - // ETSI - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ - } - // FCC - else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ - if (DFS_tri_long_pulse){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("FCC radar type5 is detected!\n"); - } - } - else{ - if(g_pw_inc[1] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("FCC radar type1 or type6 is detected!\n"); - } - } - else if(g_pw_inc[1] + g_pw_inc[2]>= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("FCC radar type2 is detected!\n"); - } - } - else if(g_pw_inc[3] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("FCC radar type3 is detected!\n"); - } - } - else if(g_pw_inc[4] >= short_pulse_th + 1){ - if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ - panic_printk("FCC radar type4 is detected!\n"); - } - } - else{ - DFS_tri_short_pulse = 0; - } - } - } - else{ - } - } - -} -#endif //#if defined(CONFIG_WLAN_HAL_8814AE) - -#endif - +/* + * Handling routines for DFS DET functions + * + * $Id: 8192cd_dfs_det.c,v 1.1 2012/05/04 12:49:07 jimmylin Exp $ + * + * Copyright (c) 2012 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define _8192CD_DFS_DET_C_ + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" + + +#if defined(DFS) && !defined(CONFIG_RTL_92D_SUPPORT) +extern u2Byte dB_Invert_Table[8][12]; + +static u4Byte +ConvertTo_dB( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte dB; + + Value = Value & 0xFFFF; + + for (i=0;i<8;i++) + { + if (Value <= dB_Invert_Table[i][11]) + { + break; + } + } + + if (i >= 8) + { + return (96); // maximum 96 dB + } + + for (j=0;j<12;j++) + { + if (Value <= dB_Invert_Table[i][j]) + { + break; + } + } + + dB = i*12 + j + 1; + + return (dB); +} + + +static int +GetPSDData_8812( + IN PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd) +{ + int psd_report; + struct rtl8192cd_priv *priv=pDM_Odm->priv; + + //Set DCO frequency index, offset=(40MHz/SamplePts)*point + ODM_SetBBReg(pDM_Odm, 0x910, 0x3FF, point); + + //Start PSD calculation, Reg808[22]=0->1 + ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 1); + + //Need to wait for HW PSD report + delay_us(priv->pshare->rf_ft_var.dfs_psd_delay); + + ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0); + + //Read PSD report, Reg8B4[15:0] + psd_report = (int)ODM_GetBBReg(pDM_Odm,0xf44, bMaskDWord) & 0x0000FFFF; + if(priv->pshare->rf_ft_var.psd_skip_lookup_table){ + if(psd_report >=14) + psd_report = 23; + else + psd_report = 8; + } + else{ + psd_report = (int)(ConvertTo_dB((u4Byte)psd_report)); + } + + return psd_report; + +} + + +void Scan_BB_PSD( + IN PDM_ODM_T pDM_Odm, + int *PSD_report_right, + int *PSD_report_left, + int len, + int initial_gain) +{ + struct rtl8192cd_priv *priv=pDM_Odm->priv; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte ST_TH_origin; + u1Byte idx[20]={//96,99,102,106,109,112,115,118,122,125, + 224,227,230,234,237,240,243,246,250,253, + 0,3,6,10,13,16,19,22,26,29}; + int tone_idx, channel_org, channel, i, BW_org; + + // set DFS ST_TH to max value + ST_TH_origin = RTL_R8(0x91c); + RTL_W8(0x91c, 0x4e); + + // Turn off CCK + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0); //808[28] + + // Turn off TX + // Pause TX Queue + if (!priv->pmib->dot11DFSEntry.disable_tx) + ODM_Write1Byte(pDM_Odm, 0x522, 0xFF); //REG_TXPAUSE §ï¬°0x522 + + // Turn off CCA + if((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)){ + ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0x1); //838[1] ³]¬°1 + } + else{ + ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0x1); //838[3] ³]¬°1 + } + + // PHYTXON while loop + PHY_SetBBReg(priv, 0x8fc, 0xfff, 0); + i = 0; + while (ODM_GetBBReg(pDM_Odm, 0xfa0, BIT18)) { + i++; + if (i > 1000000) { + panic_printk("Wait in %s() more than %d times!\n", __FUNCTION__, i); + break; + } + } + + // backup IGI_origin , set IGI = 0x3e; + pDM_DigTable->bPSDInProgress = TRUE; + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, initial_gain); + + // Turn off 3-wire + ODM_SetBBReg(pDM_Odm, 0xC00, BIT1|BIT0, 0x0); //c00[1:0] ¼g0 + + // pts value = 128, 256, 512, 1024 + ODM_SetBBReg(pDM_Odm, 0x910, BIT14|BIT15, 0x1); //910[15:14]³]¬°1, ¥Î256ÂI + ODM_SetBBReg(pDM_Odm, 0x910, BIT12|BIT13, 0x1); //910[13:12]³]¬°1, avg 8 ¦¸ + + // scan in-band PSD + channel_org = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF); + BW_org = priv->pshare->CurrentChannelBW; + if(priv->pshare->CurrentChannelBW != HT_CHANNEL_WIDTH_20){ + priv->pshare->No_RF_Write = 0; + SwBWMode(priv, HT_CHANNEL_WIDTH_20, 0); + priv->pshare->No_RF_Write = 1; + } + + if (priv->pshare->rf_ft_var.dfs_scan_inband) { + int PSD_report_inband[20]; + for (tone_idx=0;tone_idxpshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + channel = channel_org + 4; + else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + channel = channel_org + 6; + else + channel = channel_org + 10; + delay_us(300); // for idle 20M, it will emit signal in right 20M channel + priv->pshare->No_RF_Write = 0; + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + priv->pshare->No_RF_Write = 1; + + for (tone_idx=0;tone_idxpshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + channel = channel_org - 4; + else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + channel = channel_org - 6; + else + channel = channel_org - 10; + priv->pshare->No_RF_Write = 0; + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + priv->pshare->No_RF_Write = 1; + + for (tone_idx=0;tone_idxpshare->CurrentChannelBW){ + priv->pshare->No_RF_Write = 0; + SwBWMode(priv, BW_org, priv->pshare->offset_2nd_chan); + priv->pshare->No_RF_Write = 1; + } + priv->pshare->No_RF_Write = 0; + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel_org); + priv->pshare->No_RF_Write = 1; + + // Turn on 3-wire + ODM_SetBBReg(pDM_Odm, 0xc00, BIT1|BIT0, 0x3); //c00[1:0] ¼g3 + + // Restore Current Settings + // Resume DIG + pDM_DigTable->bPSDInProgress = FALSE; + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, NONE); + + //Turn on CCA + if((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)){ + ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0); //838[1] ³]¬°0 + } + else{ + ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0); //838[3] ³]¬°0 + } + + + // Turn on TX + // Resume TX Queue + if (!priv->pmib->dot11DFSEntry.disable_tx) + ODM_Write1Byte(pDM_Odm, 0x522, 0x00); //REG_TXPAUSE §ï¬°0x522 + + // CCK on + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 1); //808[28] + + // Resume DFS ST_TH + RTL_W8(0x91c, ST_TH_origin); +} + + +void rtl8192cd_dfs_det_chk(struct rtl8192cd_priv *priv) +{ + PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + unsigned int regf98_value; + unsigned int reg918_value; + unsigned int reg91c_value; + unsigned int reg920_value; + unsigned int reg924_value; + unsigned int reg19e4_value; + unsigned int FA_count_cur=0, FA_count_inc=0; + unsigned int CCA_count_cur=0, CCA_count_inc=0; + unsigned int VHT_CRC_ok_cnt_cur=0, VHT_CRC_ok_cnt_inc=0; + unsigned int HT_CRC_ok_cnt_cur=0, HT_CRC_ok_cnt_inc=0; + unsigned int LEG_CRC_ok_cnt_cur=0, LEG_CRC_ok_cnt_inc=0; + unsigned int Total_CRC_OK_cnt_inc=0, FA_CRCOK_ratio=0; + unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, fa_mask_mid_th=0, fa_mask_lower_th=0; + unsigned int short_pulse_cnt_cur=0, short_pulse_cnt_inc=0; + unsigned int long_pulse_cnt_cur=0, long_pulse_cnt_inc=0; + unsigned int total_pulse_count_inc=0, max_sht_pusle_cnt_th=0; + unsigned int sum, k, fa_flag=0; + unsigned int st_L2H_new=0, st_L2H_tmp, index=0, fault_flag_det, fault_flag_psd; + int j, flags=0; + unsigned long throughput = 0; + + int i, PSD_report_right[20], PSD_report_left[20]; + int max_right, max_left; + int max_fa_in_hist=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0; + + if (priv->det_asoc_clear > 0) { + priv->det_asoc_clear--; + priv->pmib->dot11DFSEntry.DFS_detected = 0; + priv->FA_count_pre = 0; + priv->CCA_count_pre = 0; + priv->VHT_CRC_ok_cnt_pre = 0; + priv->HT_CRC_ok_cnt_pre = 0; + priv->LEG_CRC_ok_cnt_pre = 0; + priv->mask_idx = 0; + priv->hist_idx = 0; + priv->mask_hist_checked = 0; + memset(priv->radar_det_mask_hist, 0, sizeof(priv->radar_det_mask_hist)); + memset(priv->pulse_flag_hist, 0, sizeof(priv->pulse_flag_hist)); + memset(priv->pulse_type_hist, 0, sizeof(priv->pulse_type_hist)); + mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10)); + return; + } + + throughput = priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage; +#ifdef UNIVERSAL_REPEATER + if (GET_VXD_PRIV(priv) && (GET_VXD_PRIV(priv)->drv_state & DRV_STATE_OPEN)) + throughput += (GET_VXD_PRIV(priv)->ext_stats.tx_avarage + GET_VXD_PRIV(priv)->ext_stats.rx_avarage); +#endif + +#ifdef MBSSID + if (priv->pmib->miscEntry.vap_enable) { + for (j=0; jpvap_priv[j])) { + throughput += priv->pvap_priv[j]->ext_stats.tx_avarage+priv->pvap_priv[j]->ext_stats.rx_avarage; + } + } + } +#endif + + // Get FA count during past 100ms + FA_count_cur = PHY_QueryBBReg(priv, 0xf48, 0x0000ffff); + CCA_count_cur = PHY_QueryBBReg(priv, 0xf08, 0xffff0000); + + if (priv->FA_count_pre == 0) + FA_count_inc = 0; + else if (FA_count_cur >= priv->FA_count_pre) + FA_count_inc = FA_count_cur - priv->FA_count_pre; + else + FA_count_inc = FA_count_cur; + priv->FA_count_pre = FA_count_cur; + + if (priv->CCA_count_pre == 0) + CCA_count_inc = 0; + else if (CCA_count_cur >= priv->CCA_count_pre) + CCA_count_inc = CCA_count_cur - priv->CCA_count_pre; + else + CCA_count_inc = CCA_count_cur; + priv->CCA_count_pre = CCA_count_cur; + + priv->fa_inc_hist[priv->mask_idx] = FA_count_inc; + for (i=0; i<5; i++) { + total_fa_in_hist = total_fa_in_hist + priv->fa_inc_hist[i]; + if (priv->fa_inc_hist[i] > max_fa_in_hist) + max_fa_in_hist = priv->fa_inc_hist[i]; + } + if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) + index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; + else + index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; + if (index == 0) + pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[4]; + else if (index == 4) + pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[0] + priv->fa_inc_hist[index-1]; + else + pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[index-1]; + + // Get VHT CRC32 ok count during past 100ms + VHT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf0c, 0x00003fff); + if (VHT_CRC_ok_cnt_cur >= priv->VHT_CRC_ok_cnt_pre) + VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur - priv->VHT_CRC_ok_cnt_pre; + else + VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur; + priv->VHT_CRC_ok_cnt_pre = VHT_CRC_ok_cnt_cur; + + // Get HT CRC32 ok count during past 100ms + HT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf10, 0x00003fff); + if (HT_CRC_ok_cnt_cur >= priv->HT_CRC_ok_cnt_pre) + HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur - priv->HT_CRC_ok_cnt_pre; + else + HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur; + priv->HT_CRC_ok_cnt_pre = HT_CRC_ok_cnt_cur; + + // Get Legacy CRC32 ok count during past 100ms + LEG_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf14, 0x00003fff); + if (LEG_CRC_ok_cnt_cur >= priv->LEG_CRC_ok_cnt_pre) + LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur - priv->LEG_CRC_ok_cnt_pre; + else + LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur; + priv->LEG_CRC_ok_cnt_pre = LEG_CRC_ok_cnt_cur; + + if ((VHT_CRC_ok_cnt_cur == 0x3fff) || + (HT_CRC_ok_cnt_cur == 0x3fff) || + (LEG_CRC_ok_cnt_cur == 0x3fff)) { + PHY_SetBBReg(priv, 0xb58, BIT(0), 1); + PHY_SetBBReg(priv, 0xb58, BIT(0), 0); + } + + Total_CRC_OK_cnt_inc = VHT_CRC_ok_cnt_inc + HT_CRC_ok_cnt_inc + LEG_CRC_ok_cnt_inc; + + // check if the FA occrus frequencly during 100ms + // FA_count_inc is divided by Total_CRC_OK_cnt_inc, which helps to distinguish normal trasmission from interference + if (Total_CRC_OK_cnt_inc > 0) + FA_CRCOK_ratio = FA_count_inc / Total_CRC_OK_cnt_inc; + + //=====dynamic power threshold (DPT) ======== + // Get short pulse count, need carefully handle the counter overflow + regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff); + short_pulse_cnt_cur = regf98_value & 0x000000ff; + if (short_pulse_cnt_cur >= priv->short_pulse_cnt_pre) + short_pulse_cnt_inc = short_pulse_cnt_cur - priv->short_pulse_cnt_pre; + else + short_pulse_cnt_inc = short_pulse_cnt_cur; + priv->short_pulse_cnt_pre = short_pulse_cnt_cur; + + // Get long pulse count, need carefully handle the counter overflow + long_pulse_cnt_cur = (regf98_value & 0x0000ff00) >> 8; + if (long_pulse_cnt_cur >= priv->long_pulse_cnt_pre) + long_pulse_cnt_inc = long_pulse_cnt_cur - priv->long_pulse_cnt_pre; + else + long_pulse_cnt_inc = long_pulse_cnt_cur; + priv->long_pulse_cnt_pre = long_pulse_cnt_cur; + + total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; + + if (priv->pshare->rf_ft_var.dfs_det_print) { + panic_printk("=====================================================================\n"); + panic_printk("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d] CCA_count_inc[%d] FA_CRCOK_ratio[%d]\n", + Total_CRC_OK_cnt_inc, VHT_CRC_ok_cnt_inc, HT_CRC_ok_cnt_inc, LEG_CRC_ok_cnt_inc, FA_count_inc, CCA_count_inc, FA_CRCOK_ratio); + panic_printk("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + priv->ini_gain_cur, priv->st_L2H_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc); + panic_printk("Throughput: %luMbps\n", (throughput>>17)); + // panic_printk("nhm_duty_cycle = %d\n", (100-((CCX_INFO->NHM_result_total * 100) >> 8))); + reg918_value = PHY_QueryBBReg(priv, 0x918, 0xffffffff); + reg91c_value = PHY_QueryBBReg(priv, 0x91c, 0xffffffff); + reg920_value = PHY_QueryBBReg(priv, 0x920, 0xffffffff); + reg924_value = PHY_QueryBBReg(priv, 0x924, 0xffffffff); + reg19e4_value = PHY_QueryBBReg(priv, 0x19e4, 0xffffffff); + panic_printk("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x] 0x19e4[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value, reg19e4_value); + } + + // read hw dfs detection flag + DFS_tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; + DFS_tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; + + if (DFS_tri_short_pulse) { + //RTL_W32(0x920, RTL_R32(0x920) | BIT(24)); + //RTL_W32(0x920, RTL_R32(0x920) & ~BIT(24)); + //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); + //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); + } + if (DFS_tri_long_pulse) { + //RTL_W32(0x920, RTL_R32(0x920) | BIT(25)); + //RTL_W32(0x920, RTL_R32(0x920) & ~BIT(25)); + //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); + //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); + // MKK + if (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2) { + if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && + (priv->pmib->dot11RFEntry.dot11channel <= 64)) { + DFS_tri_long_pulse = 0; + } + } + // ETSI + if (priv->pshare->rf_ft_var.manual_dfs_regdomain == 3) { + DFS_tri_long_pulse = 0; + } + } + + st_L2H_new = priv->st_L2H_cur; + priv->pulse_flag_hist[priv->mask_idx] = DFS_tri_short_pulse | DFS_tri_long_pulse; + priv->pulse_type_hist[priv->mask_idx] = (DFS_tri_long_pulse)? 1 : 0; + + //max_sht_pusle_cnt_th = PHY_QueryBBReg(priv, 0x920, 0x000f0000)-1; //read 920[19:16] + max_sht_pusle_cnt_th = priv->pshare->rf_ft_var.dfs_max_sht_pusle_cnt_th; + if (priv->pshare->rf_ft_var.dfs_det_print3) + panic_printk("max_sht_pusle_cnt_th = %d\n", max_sht_pusle_cnt_th); + + if(priv->idle_flag == 1){ + if(priv->pshare->rf_ft_var.dfs_psd_idle_on == 1){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK(flags); + Scan_BB_PSD(ODMPTR, PSD_report_right, PSD_report_left, 20, 0x3e); + SMP_UNLOCK(flags); + RESTORE_INT(flags); + } + else{ + /*for (i=0; i<20; i++) { + PSD_report_right[i] = 0; + PSD_report_left[i] = 0; + }*/ + } + } + else{ + if(priv->pshare->rf_ft_var.dfs_psd_TP_on == 1){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK(flags); + Scan_BB_PSD(ODMPTR, PSD_report_right, PSD_report_left, 20, 0x3e); + SMP_UNLOCK(flags); + RESTORE_INT(flags); + } + else{ + for (i=0; i<20; i++) { + PSD_report_right[i] = 0; + PSD_report_left[i] = 0; + } + } + } + + for (i=0; i<20; i++) { + PSD_report_right[i] = (-110 + 0x3e) - 39 + PSD_report_right[i]; + PSD_report_left[i] = (-110 + 0x3e) - 39 + PSD_report_left[i]; + } + if (priv->pshare->rf_ft_var.dfs_det_print_psd) { + panic_printk("PSD right: "); + for (i=0; i<20; i++) + panic_printk("%d ", PSD_report_right[i]); + //panic_printk("\n"); + panic_printk(" PSD left: "); + for (i=0; i<20; i++) + panic_printk("%d ", PSD_report_left[i]); + panic_printk("\n"); + } + + fault_flag_det = 0; + fault_flag_psd = 0; + fa_flag = 0; + // ETSI + if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ + fa_mask_mid_th = priv->pshare->rf_ft_var.dfs_fa_cnt_mid + 20; + fa_mask_lower_th = priv->pshare->rf_ft_var.dfs_fa_cnt_lower + 40; + } + else{ + fa_mask_mid_th = priv->pshare->rf_ft_var.dfs_fa_cnt_mid; + fa_mask_lower_th = priv->pshare->rf_ft_var.dfs_fa_cnt_lower; + } + //if (max_fa_in_hist >= fa_mask_mid_th || total_fa_in_hist >= priv->pshare->rf_ft_var.dfs_fa_hist || pre_post_now_acc_fa_in_hist >= fa_mask_mid_th){ + /*if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) + index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; + else + index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; */ + /* priv->radar_det_mask_hist[index] = 1; + if (priv->pulse_flag_hist[index] == 1){ + priv->pulse_flag_hist[index] = 0; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("Radar is masked : FA mask case3\n"); + } + } + fa_flag = 1; + } + if (((FA_count_inc >= priv->pshare->rf_ft_var.dfs_dpt_fa_th_upper) && (short_pulse_cnt_inc > max_sht_pusle_cnt_th)) || + (priv->ini_gain_cur >= priv->pshare->rf_ft_var.dpt_ini_gain_th)) { + st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max; + if (priv->pshare->rf_ft_var.dfs_det_print3) + panic_printk("[1] st_L2H_new %x\n", st_L2H_new); + priv->radar_det_mask_hist[priv->mask_idx] = 1; + if (priv->pulse_flag_hist[priv->mask_idx] == 1){ + priv->pulse_flag_hist[priv->mask_idx] = 0; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("Radar is masked : FA mask case1\n"); + } + } + fa_flag = 1; + } + else if (((FA_count_inc >= fa_mask_mid_th) || + ((FA_count_inc >= fa_mask_lower_th) && + (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_inc_ratio * priv->FA_count_inc_pre))) + && (short_pulse_cnt_inc > max_sht_pusle_cnt_th)) { + if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) + st_L2H_new += 2; + if (priv->pshare->rf_ft_var.dfs_det_print3) + panic_printk("[2] st_L2H_new %x\n", st_L2H_new); + priv->radar_det_mask_hist[priv->mask_idx] = 1; + if (priv->pulse_flag_hist[priv->mask_idx] == 1){ + priv->pulse_flag_hist[priv->mask_idx] = 0; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("Radar is masked : FA mask case2\n"); + } + } + fa_flag = 1; + } + else + { + if (((FA_CRCOK_ratio > priv->pshare->rf_ft_var.dfs_fa_ratio_th) && + (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_lower) && + (Total_CRC_OK_cnt_inc > priv->pshare->rf_ft_var.dfs_crc32_cnt_lower)) || + ((short_pulse_cnt_inc <= max_sht_pusle_cnt_th) && (short_pulse_cnt_inc != 0) && + (priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) || + (FA_count_inc >= priv->pshare->rf_ft_var.dfs_fa_cnt_upper)) + priv->radar_det_mask_hist[priv->mask_idx] = 1; + else + priv->radar_det_mask_hist[priv->mask_idx] = 0; + } +*/ + priv->radar_det_mask_hist[priv->mask_idx] = 0; + + if ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)){ + if (((CCX_INFO->NHM_result_total * 100) >> 8) >= priv->pshare->rf_ft_var.dfs_nhm_duty_cycle_th) { + if (priv->pulse_flag_hist[index] == 1) { + priv->pulse_flag_hist[index] = 0; + if (priv->pshare->rf_ft_var.dfs_det_print4) { + panic_printk("Radar is masked : NHM duty cycle over TH\n"); + } + } + } + } + if (priv->pshare->rf_ft_var.dfs_det_print2) { + panic_printk("mask_idx: %d\n", priv->mask_idx); + panic_printk("radar_det_mask_hist: "); + for (i=0; ipshare->rf_ft_var.dfs_det_hist_len; i++) + panic_printk("%d ", priv->radar_det_mask_hist[i]); + panic_printk("pulse_flag_hist: "); + for (i=0; ipshare->rf_ft_var.dfs_det_hist_len; i++) + panic_printk("%d ", priv->pulse_flag_hist[i]); + panic_printk("fa_inc_hist: "); + for (i=0; i<5; i++) + panic_printk("%d ", priv->fa_inc_hist[i]); + panic_printk("\n"); + panic_printk("max_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",max_fa_in_hist,pre_post_now_acc_fa_in_hist); + } + + /*memcpy(&priv->PSD_report_right[priv->mask_idx][0], PSD_report_right, 20*sizeof(int)); + memcpy(&priv->PSD_report_left[priv->mask_idx][0], PSD_report_left, 20*sizeof(int)); + + for (i=0; i<20; i++) { + priv->max_hold_right[i] = -1000; + priv->max_hold_left[i] = -1000; + } + + for (k=0; k<5; k++) { + for (i=0; i<20; i++) { + if (priv->PSD_report_right[k][i] > priv->max_hold_right[i]) + priv->max_hold_right[i] = priv->PSD_report_right[k][i]; + if (priv->PSD_report_left[k][i] > priv->max_hold_left[i]) + priv->max_hold_left[i] = priv->PSD_report_left[k][i]; + } + } + + if ((priv->pshare->rf_ft_var.dfs_psd_op == 1) && (priv->idle_flag == 0)) + { + int right_index_start, left_index_end; + int avg_1 = (priv->max_hold_right[0]+priv->max_hold_right[1]+priv->max_hold_right[2])/3; + int avg_2 = (priv->max_hold_right[17]+priv->max_hold_right[18]+priv->max_hold_right[19])/3; + max_right = -1000; + if(RTL_ABS(avg_1, avg_2) <= 3) + right_index_start=2; + else + right_index_start=11; + for (i=right_index_start; i<20; i++) { + if ((i != 10) && (max_right < priv->max_hold_right[i])) + max_right = priv->max_hold_right[i]; + } + + avg_1 = (priv->max_hold_left[0]+priv->max_hold_left[1]+priv->max_hold_left[2])/3; + avg_2 = (priv->max_hold_left[17]+priv->max_hold_left[18]+priv->max_hold_left[19])/3; + max_left = -1000; + if (RTL_ABS(avg_1, avg_2) <= 3) + left_index_end=20; + else + left_index_end=8; + for (i=0; imax_hold_left[i])) + max_left = priv->max_hold_left[i]; + } + if(max_right == 0){ + max_right = -99; + } + if(max_left == 0){ + max_left = -99; + } + } + else + { + max_right = -1000; + for (i=2; i<20; i++) { + if ((i != 10) && (max_right < priv->max_hold_right[i])) + max_right = priv->max_hold_right[i]; + } + max_left = -1000; + for (i=0; i<20; i++) { + if ((i != 10) && (max_left < priv->max_hold_left[i])) + max_left = priv->max_hold_left[i]; + } + if(max_right == 0){ + max_right = -99; + } + if(max_left == 0){ + max_left = -99; + } + }*/ + + max_right = -99; + max_left = -99; + + if (priv->pshare->rf_ft_var.dfs_det_print) + panic_printk("max_right %d, max_left %d\n", max_right, max_left); + + /*if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) + index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; + else + index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;*/ + + // use PSD detection result + if ((max_right > (0-(int)priv->pshare->rf_ft_var.dfs_psd_pw_th)) || (max_left > (0-(int)priv->pshare->rf_ft_var.dfs_psd_pw_th))) { + if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) { + st_L2H_tmp = 110 + ((max_right > max_left)? max_right:max_left) - priv->pshare->rf_ft_var.dfs_psd_fir_decay; + if (st_L2H_tmp > priv->st_L2H_cur) + st_L2H_new = st_L2H_tmp; + } + if (priv->pshare->rf_ft_var.dfs_det_print3) + panic_printk("[3] st_L2H_new %x\n", st_L2H_new); + + if (priv->pshare->rf_ft_var.dfs_det_print) + panic_printk("st_L2H_cur %x pwdb_th %x\n", st_L2H_new, priv->pwdb_th); + + fault_flag_psd = 1; + if (priv->pulse_flag_hist[index] == 1){ + priv->pulse_flag_hist[index] = 0; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("Radar is masked : PSD mask\n"); + } + } + priv->radar_det_mask_hist[index] = 1; + } + + sum = 0; + for (k=0; kpshare->rf_ft_var.dfs_det_hist_len; k++) { + if (priv->radar_det_mask_hist[k] == 1) + sum++; + } + + if (priv->mask_hist_checked <= priv->pshare->rf_ft_var.dfs_det_hist_len) + priv->mask_hist_checked++; + + //only the decision result of short pulse needs to refer the FA decision results + if ((priv->mask_hist_checked >= priv->pshare->rf_ft_var.dfs_det_hist_len) && + //(DFS_tri_long_pulse || DFS_tri_short_pulse) && + priv->pulse_flag_hist[index]) + { + //if ((sum <= priv->pshare->rf_ft_var.dfs_det_sum_th) && + // (fa_flag == 0)) + if (sum <= priv->pshare->rf_ft_var.dfs_det_sum_th) + { +#if defined(CONFIG_WLAN_HAL_8814AE) || defined(CONFIG_WLAN_HAL_8822BE) + if(((GET_CHIP_VER(priv) == VERSION_8814A) || (GET_CHIP_VER(priv) == VERSION_8822B)) + && priv->pshare->rf_ft_var.dfs_radar_diff_on) + { + if (priv->pulse_type_hist[index] == 0){ + priv->radar_type = 0; + if (priv->pulsewidth_flag && priv->pulseinterval_flag && priv->pri_type3_4_flag){ + priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("hist_idx= %d\n", (priv->hist_idx+3)%4); + for (j=0;j<4;j++){ + for (i=0;i<6;i++){ + panic_printk("pluseinterval_hold = %d ", priv->pluseinterval_hold[j][i]); + } + panic_printk("\n"); + } + panic_printk("\n"); + for (j=0;j<4;j++){ + for (i=0;i<6;i++){ + panic_printk("plusewidth_hold = %d ", priv->plusewidth_hold[j][i]); + } + panic_printk("\n"); + } + panic_printk("\n"); + panic_printk("idle_flag = %d\n",priv->idle_flag); + panic_printk("plusewidth_hold_sum = %d %d %d %d %d %d\n", + priv->plusewidth_hold_sum[0], priv->plusewidth_hold_sum[1],priv->plusewidth_hold_sum[2],priv->plusewidth_hold_sum[3],priv->plusewidth_hold_sum[4],priv->plusewidth_hold_sum[5]); + panic_printk("pluseinterval_hold_sum = %d %d %d %d %d %d\n", + priv->pluseinterval_hold_sum[0], priv->pluseinterval_hold_sum[1],priv->pluseinterval_hold_sum[2],priv->pluseinterval_hold_sum[3],priv->pluseinterval_hold_sum[4],priv->pluseinterval_hold_sum[5]); + } + } + else{ + if(priv->pshare->rf_ft_var.dfs_det_print4){ + if (priv->pulse_flag_hist[index] && (priv->pulseinterval_flag==0)){ + panic_printk("PRI criterion is not satisfied!\n"); + panic_printk("pulseinterval_variation = %d\n",priv->pri_std); + if(priv->pri_cond1 == 0) + panic_printk("pri_cond1 is not satisfied!\n"); + if(priv->pri_cond2 == 0) + panic_printk("pri_cond2 is not satisfied!\n"); + if(priv->pri_cond3 == 0){ + panic_printk("pri_cond3 is not satisfied!\n"); + } + if(priv->pri_cond4 == 0) + panic_printk("pri_cond4 is not satisfied!\n"); + if(priv->pri_cond5 == 0) + panic_printk("pri_cond5 is not satisfied!\n"); + } + if (priv->pulse_flag_hist[index] && (priv->pulsewidth_flag==0)){ + panic_printk("PW criterion is not satisfied!\n"); + panic_printk("pulsewidth_variation = %d\n",priv->pw_std); + if(priv->pw_cond1 == 0) + panic_printk("pw_cond1 is not satisfied!\n"); + if(priv->pw_cond2 == 0) + panic_printk("pw_cond2 is not satisfied!\n"); + if(priv->pw_cond3 == 0){ + panic_printk("pw_cond3 is not satisfied!\n"); + } + } + if (priv->pulse_flag_hist[index] && (priv->pri_type3_4_flag==0)){ + panic_printk("pri_type3_4 criterion is not satisfied!\n"); + if(priv->pri_type3_4_cond1 == 0) + panic_printk("pri_type3_4_cond1 is not satisfied!\n"); + if(priv->pri_type3_4_cond2 == 0) + panic_printk("pri_type3_4_cond2 is not satisfied!\n"); + } + panic_printk("hist_idx= %d\n", (priv->hist_idx+3)%4); + for (j=0;j<4;j++){ + for (i=0;i<6;i++){ + panic_printk("pluseinterval_hold = %d ", priv->pluseinterval_hold[j][i]); + } + panic_printk("\n"); + } + panic_printk("\n"); + for (j=0;j<4;j++){ + for (i=0;i<6;i++){ + panic_printk("plusewidth_hold = %d ", priv->plusewidth_hold[j][i]); + } + panic_printk("\n"); + } + panic_printk("\n"); + panic_printk("idle_flag = %d\n",priv->idle_flag); + panic_printk("plusewidth_hold_sum = %d %d %d %d %d %d\n", + priv->plusewidth_hold_sum[0], priv->plusewidth_hold_sum[1],priv->plusewidth_hold_sum[2],priv->plusewidth_hold_sum[3],priv->plusewidth_hold_sum[4],priv->plusewidth_hold_sum[5]); + panic_printk("pluseinterval_hold_sum = %d %d %d %d %d %d\n", + priv->pluseinterval_hold_sum[0], priv->pluseinterval_hold_sum[1],priv->pluseinterval_hold_sum[2],priv->pluseinterval_hold_sum[3],priv->pluseinterval_hold_sum[4],priv->pluseinterval_hold_sum[5]); + } + } + } + else{ + priv->radar_type = 1; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("\n"); + panic_printk("idle_flag = %d\n",priv->idle_flag); + panic_printk("long_radar_plusewidth_hold_sum = %d %d %d %d %d %d\n", + priv->plusewidth_long_hold_sum[0], priv->plusewidth_long_hold_sum[1],priv->plusewidth_long_hold_sum[2],priv->plusewidth_long_hold_sum[3],priv->plusewidth_long_hold_sum[4],priv->plusewidth_long_hold_sum[5]); + panic_printk("long_radar_pluseinterval_hold_sum = %d %d %d %d %d %d\n", + priv->pluseinterval_long_hold_sum[0], priv->pluseinterval_long_hold_sum[1],priv->pluseinterval_long_hold_sum[2],priv->pluseinterval_long_hold_sum[3],priv->pluseinterval_long_hold_sum[4],priv->pluseinterval_long_hold_sum[5]); + } + /* Long radar should satisfy three conditions */ + if(priv->long_radar_flag == 1){ + priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect + } + else{ + if (priv->pshare->rf_ft_var.dfs_det_print4){ + if(priv->pw_long_cond1 == 0) + panic_printk("--pw_long_cond1 is not satisfied!--\n"); + if(priv->pw_long_cond2 == 0) + panic_printk("--pw_long_cond2 is not satisfied!--\n"); + if(priv->pri_long_cond1 == 0) + panic_printk("--pri_long_cond1 is not satisfied!--\n"); + } + } + } + + } + else +#endif + { + if (priv->pulse_type_hist[index] == 0) + priv->radar_type = 0; + else if (priv->pulse_type_hist[index] == 1) + priv->radar_type = 1; + priv->pmib->dot11DFSEntry.DFS_detected = 1 ; // DFS detect + } + } + else { + fault_flag_det = 1; + if (priv->pshare->rf_ft_var.dfs_det_print4){ + panic_printk("Radar is masked : mask_hist large than thd\n"); + } + } + } + + priv->mask_idx++; + if (priv->mask_idx == priv->pshare->rf_ft_var.dfs_det_hist_len) + priv->mask_idx = 0; + + if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) { + //if (total_pulse_count_inc < priv->pshare->rf_ft_var.dfs_dpt_pulse_th_lower) { + // // limit the ST value to absoulte lower bound 0x1c + // st_L2H_new -= 4; + // if (priv->pshare->rf_ft_var.dfs_det_print3) + // panic_printk("[4] st_L2H_new %x\n", st_L2H_new); + //} + ///*else if (total_pulse_count_inc < priv->pshare->rf_ft_var.dfs_dpt_pulse_th_mid) { + // // limit the ST value to absoulte lower bound 0x1c + // st_L2H_new -= 2; + // if (priv->pshare->rf_ft_var.dfs_det_print3) + // panic_printk("[5] st_L2H_new %x\n", st_L2H_new); + //}*/ + //else if (ini_gain_inc < 0){ + // st_L2H_new += ini_gain_inc; + // if (priv->pshare->rf_ft_var.dfs_det_print3) + // panic_printk("[6] st_L2H_new %x\n", st_L2H_new); + //} + ///*else if ((total_pulse_count_inc < max_sht_pusle_cnt_th) && + // (((priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17) <= priv->pshare->rf_ft_var.dfs_psd_tp_th)) { + // st_L2H_new += priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_th; + //}*/ + if (priv->ini_gain_cur < priv->pshare->rf_ft_var.dpt_ini_gain_th) { + if ((priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) + st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min + priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_offset; + else + st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; + } + } + else{ + + + if (priv->pshare->rf_ft_var.dfs_dpt_st_l2h_add) + st_L2H_new += 2; + if (priv->pshare->rf_ft_var.dfs_det_print3) + panic_printk("[7] st_L2H_new %x\n", st_L2H_new); + + + if (DFS_tri_short_pulse) { + //RTL_W32(0x920, RTL_R32(0x920) | (BIT(24) | BIT(28))); + //RTL_W32(0x920, RTL_R32(0x920) & ~(BIT(24) | BIT(28))); + //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); + //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); + } + if (DFS_tri_long_pulse) { + //RTL_W32(0x920, RTL_R32(0x920) | (BIT(25) | BIT(28))); + //RTL_W32(0x920, RTL_R32(0x920) & ~(BIT(25) | BIT(28))); + //RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); + //RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); + } + } + + if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20){ + if(priv->pshare->highTP_found_pstat != NULL){ + if(priv->pshare->highTP_found_pstat->rf_info.mimorssi[0] >= 20 && priv->pshare->highTP_found_pstat->rf_info.mimorssi[0] <= 30) + st_L2H_new = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min - 19 + priv->pshare->highTP_found_pstat->rf_info.mimorssi[0]; + } + } + + if ((st_L2H_new != priv->st_L2H_cur)) { + // limit the ST value to absoulte lower bound 0x22 + // limit the ST value to absoulte upper bound 0x4e + if (st_L2H_new < priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min) { + if ((priv->idle_flag == 1) && (priv->pshare->rf_ft_var.manual_dfs_regdomain == 2)) + priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min + priv->pshare->rf_ft_var.dfs_dpt_st_l2h_idle_offset; + else + priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; + //priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_min; + } + else if (st_L2H_new > priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max) + priv->st_L2H_cur = priv->pshare->rf_ft_var.dfs_dpt_st_l2h_max; + else + priv->st_L2H_cur = st_L2H_new; + RTL_W8(0x91c, priv->st_L2H_cur); + + priv->pwdb_th = ((int)priv->st_L2H_cur - (int)priv->ini_gain_cur)/2 + priv->pshare->rf_ft_var.dfs_pwdb_scalar_factor; + priv->pwdb_th = MAX_NUM(priv->pwdb_th, (int)priv->pshare->rf_ft_var.dfs_pwdb_th); // limit the pwdb value to absoulte lower bound 0xa + priv->pwdb_th = MIN_NUM(priv->pwdb_th, 0x1f); // limit the pwdb value to absoulte upper bound 0x1f + PHY_SetBBReg(priv, 0x918, 0x00001f00, priv->pwdb_th); + } + + if (priv->pshare->rf_ft_var.dfs_det_print2) { + panic_printk("fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",fault_flag_det, fault_flag_psd, priv->pmib->dot11DFSEntry.DFS_detected ); + } + + priv->FA_count_inc_pre = FA_count_inc; + if (PHY_QueryBBReg(priv, 0xf98, BIT(17)) || PHY_QueryBBReg(priv, 0xf98, BIT(19))){ + RTL_W32(0x924, RTL_R32(0x924) & ~BIT(15)); + RTL_W32(0x924, RTL_R32(0x924) | BIT(15)); + } +} + + +void rtl8192cd_dfs_dynamic_setting(struct rtl8192cd_priv *priv) +{ + unsigned char peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0; + unsigned char peak_window_cur=0, nb2wb_th_cur=0; + + if ((priv->idle_flag == 1)) { // idle (no traffic) + peak_th_cur = 3; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 9; + peak_window_cur = 2; + three_peak_opt_cur = 0; + three_peak_th2_cur = 2; + // MKK + if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2){ + if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && + (priv->pmib->dot11RFEntry.dot11channel <= 64)) { + short_pulse_cnt_th_cur = priv->pshare->rf_ft_var.dfs_pc0_th_idle_w53; + long_pulse_cnt_th_cur = 15; + three_peak_th2_cur = 0; + } + else { + short_pulse_cnt_th_cur = priv->pshare->rf_ft_var.dfs_pc0_th_idle_w56; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 10; + } + } + // FCC + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ + three_peak_th2_cur = 0; + } + // ETSI + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ + long_pulse_cnt_th_cur = 15; + if((priv->ch_120_132_CAC_end == 0) && IS_METEOROLOGY_CHANNEL(priv->pmib->dot11RFEntry.dot11channel)){ + peak_th_cur = 2; + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + } + else{ + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + } + } + else{ // default: FCC + } + } + else{ // in service (with TP) + peak_th_cur = 2; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 7; + peak_window_cur = 2; + three_peak_opt_cur = 0; + three_peak_th2_cur = 2; + // MKK + if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2){ + if ((priv->pmib->dot11RFEntry.dot11channel >= 52) && + (priv->pmib->dot11RFEntry.dot11channel <= 64)) { + long_pulse_cnt_th_cur = 15; + short_pulse_cnt_th_cur = 5; // for high duty cycle + three_peak_th2_cur = 0; + } + else { + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 8; + } + } + // FCC + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ + } + // ETSI + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ + long_pulse_cnt_th_cur = 15; + short_pulse_cnt_th_cur = 5; + three_peak_opt_cur = 0; + } + else{ + } + } + if((priv->peak_th != peak_th_cur)){ + PHY_SetBBReg(priv, 0x918, 0x00030000, peak_th_cur); + } + if((priv->short_pulse_cnt_th != short_pulse_cnt_th_cur)){ + PHY_SetBBReg(priv, 0x920, 0x000f0000, short_pulse_cnt_th_cur); + } + if((priv->long_pulse_cnt_th != long_pulse_cnt_th_cur)){ + PHY_SetBBReg(priv, 0x920, 0x00f00000, long_pulse_cnt_th_cur); + } + if((priv->peak_window != peak_window_cur)){ + PHY_SetBBReg(priv, 0x920, 0x00000300, peak_window_cur); + } + if((priv->nb2wb_th != nb2wb_th_cur)){ + PHY_SetBBReg(priv, 0x920, 0x0000e000, nb2wb_th_cur); + } + if((priv->three_peak_opt != three_peak_opt_cur)){ + PHY_SetBBReg(priv, 0x924, 0x00000180, three_peak_opt_cur); + } + if((priv->three_peak_th2 != three_peak_th2_cur)){ + PHY_SetBBReg(priv, 0x924, 0x00007000, three_peak_th2_cur); + } + + priv->peak_th = peak_th_cur; + priv->short_pulse_cnt_th = short_pulse_cnt_th_cur; + priv->long_pulse_cnt_th = long_pulse_cnt_th_cur; + priv->peak_window = peak_window_cur; + priv->nb2wb_th = nb2wb_th_cur; + priv->three_peak_opt = three_peak_opt_cur; + priv->three_peak_th2 = three_peak_th2_cur; +} + +#if defined(CONFIG_WLAN_HAL_8814AE) || defined(CONFIG_WLAN_HAL_8822BE) + +void rtl8192cd_radar_type_differentiation(struct rtl8192cd_priv *priv) +{ + unsigned char i, need_reset, g_ti_cur[16], g_pw_cur[6], g_pri_cur[6], g_ti_inc[16], g_pw_inc[6], g_pri_inc[6]; // ti = tone index, pw = pulse width, pri = pulse repetition interval + unsigned int g_total, g0_ratio, g1_ratio, g2_ratio, g3_ratio, g4_ratio, g5_ratio; + unsigned int regf98_value; + unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, short_pulse_th; + unsigned char dfs_plusewidth_thd1, dfs_plusewidth_thd2, dfs_plusewidth_thd3, dfs_plusewidth_thd4, dfs_plusewidth_thd5; + unsigned int dfs_hist1_peak_index, dfs_hist2_peak_index, dfs_hist1_pulse_width, dfs_hist2_pulse_width, dfs_hist1_pulse_rep_intvl, dfs_hist2_pulse_rep_intvl; + unsigned char g_plusewidth[6],j,g_peakindex[16]; + unsigned int g_plusewidth_total,g_peakindex_total,g_mask_32; + + regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff); + DFS_tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; + DFS_tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; + short_pulse_th = PHY_QueryBBReg(priv, 0x920, 0x000f0000); + + PHY_SetBBReg(priv, 0x19b8, 0x40, 0); // switch 0xf5c & 0xf74 to DFS report + // read peak index hist report + PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 0); // report selection = 0 (peak index) + /*g_ti_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xf0000000); + if (g_ti_cur[0] >= priv->g_ti_pre[0]) + g_ti_inc[0] = g_ti_cur[0] - priv->g_ti_pre[0]; + else + g_ti_inc[0] = g_ti_cur[0]; + priv->g_ti_pre[0] = g_ti_cur[0]; + + g_ti_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x0f000000); + if (g_ti_cur[1] >= priv->g_ti_pre[1]) + g_ti_inc[1] = g_ti_cur[1] - priv->g_ti_pre[1]; + else + g_ti_inc[1] = g_ti_cur[1]; + priv->g_ti_pre[1] = g_ti_cur[1]; + + g_ti_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x00f00000); + if (g_ti_cur[2] >= priv->g_ti_pre[2]) + g_ti_inc[2] = g_ti_cur[2] - priv->g_ti_pre[2]; + else + g_ti_inc[2] = g_ti_cur[2]; + priv->g_ti_pre[2] = g_ti_cur[2]; + + g_ti_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000f0000); + if (g_ti_cur[3] >= priv->g_ti_pre[3]) + g_ti_inc[3] = g_ti_cur[3] - priv->g_ti_pre[3]; + else + g_ti_inc[3] = g_ti_cur[3]; + priv->g_ti_pre[3] = g_ti_cur[3]; + + g_ti_cur[4] = PHY_QueryBBReg(priv, 0xf74, 0x0000f000); + if (g_ti_cur[4] >= priv->g_ti_pre[4]) + g_ti_inc[4] = g_ti_cur[4] - priv->g_ti_pre[4]; + else + g_ti_inc[4] = g_ti_cur[4]; + priv->g_ti_pre[4] = g_ti_cur[4]; + + g_ti_cur[5] = PHY_QueryBBReg(priv, 0xf74, 0x00000f00); + if (g_ti_cur[5] >= priv->g_ti_pre[5]) + g_ti_inc[5] = g_ti_cur[5] - priv->g_ti_pre[5]; + else + g_ti_inc[5] = g_ti_cur[5]; + priv->g_ti_pre[5] = g_ti_cur[5]; + + g_ti_cur[6] = PHY_QueryBBReg(priv, 0xf74, 0x000000f0); + if (g_ti_cur[6] >= priv->g_ti_pre[6]) + g_ti_inc[6] = g_ti_cur[6] - priv->g_ti_pre[6]; + else + g_ti_inc[6] = g_ti_cur[6]; + priv->g_ti_pre[6] = g_ti_cur[6]; + + g_ti_cur[7] = PHY_QueryBBReg(priv, 0xf74, 0x0000000f); + if (g_ti_cur[7] >= priv->g_ti_pre[7]) + g_ti_inc[7] = g_ti_cur[7] - priv->g_ti_pre[7]; + else + g_ti_inc[7] = g_ti_cur[7]; + priv->g_ti_pre[7] = g_ti_cur[7]; + + g_ti_cur[8] = PHY_QueryBBReg(priv, 0xf5c, 0xf0000000); + if (g_ti_cur[8] >= priv->g_ti_pre[8]) + g_ti_inc[8] = g_ti_cur[8] - priv->g_ti_pre[8]; + else + g_ti_inc[8] = g_ti_cur[8]; + priv->g_ti_pre[8] = g_ti_cur[8]; + + g_ti_cur[9] = PHY_QueryBBReg(priv, 0xf5c, 0x0f000000); + if (g_ti_cur[9] >= priv->g_ti_pre[9]) + g_ti_inc[9] = g_ti_cur[9] - priv->g_ti_pre[9]; + else + g_ti_inc[9] = g_ti_cur[9]; + priv->g_ti_pre[9] = g_ti_cur[9]; + + g_ti_cur[10] = PHY_QueryBBReg(priv, 0xf5c, 0x00f00000); + if (g_ti_cur[10] >= priv->g_ti_pre[10]) + g_ti_inc[10] = g_ti_cur[10] - priv->g_ti_pre[10]; + else + g_ti_inc[10] = g_ti_cur[10]; + priv->g_ti_pre[10] = g_ti_cur[10]; + + g_ti_cur[11] = PHY_QueryBBReg(priv, 0xf5c, 0x000f0000); + if (g_ti_cur[11] >= priv->g_ti_pre[0]) + g_ti_inc[11] = g_ti_cur[11] - priv->g_ti_pre[11]; + else + g_ti_inc[11] = g_ti_cur[11]; + priv->g_ti_pre[11] = g_ti_cur[11]; + + g_ti_cur[12] = PHY_QueryBBReg(priv, 0xf5c, 0x0000f000); + if (g_ti_cur[12] >= priv->g_ti_pre[12]) + g_ti_inc[12] = g_ti_cur[12] - priv->g_ti_pre[12]; + else + g_ti_inc[12] = g_ti_cur[12]; + priv->g_ti_pre[12] = g_ti_cur[12]; + + g_ti_cur[13] = PHY_QueryBBReg(priv, 0xf5c, 0x00000f00); + if (g_ti_cur[13] >= priv->g_ti_pre[13]) + g_ti_inc[13] = g_ti_cur[13] - priv->g_ti_pre[13]; + else + g_ti_inc[13] = g_ti_cur[13]; + priv->g_ti_pre[13] = g_ti_cur[13]; + + g_ti_cur[14] = PHY_QueryBBReg(priv, 0xf5c, 0x000000f0); + if (g_ti_cur[14] >= priv->g_ti_pre[14]) + g_ti_inc[14] = g_ti_cur[14] - priv->g_ti_pre[14]; + else + g_ti_inc[14] = g_ti_cur[14]; + priv->g_ti_pre[14] = g_ti_cur[14]; + + g_ti_cur[15] = PHY_QueryBBReg(priv, 0xf5c, 0x0000000f); + if (g_ti_cur[15] >= priv->g_ti_pre[15]) + g_ti_inc[15] = g_ti_cur[15] - priv->g_ti_pre[15]; + else + g_ti_inc[15] = g_ti_cur[15]; + priv->g_ti_pre[15] = g_ti_cur[15]; + + // read pulse width hist report + PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 1); // report selection = 1 (pulse width) + + g_pw_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xff000000); + if (g_pw_cur[0] >= priv->g_pw_pre[0]) + g_pw_inc[0] = g_pw_cur[0] - priv->g_pw_pre[0]; + else + g_pw_inc[0] = g_pw_cur[0]; + priv->g_pw_pre[0] = g_pw_cur[0]; + + g_pw_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x00ff0000); + if (g_pw_cur[1] >= priv->g_pw_pre[1]) + g_pw_inc[1] = g_pw_cur[1] - priv->g_pw_pre[1]; + else + g_pw_inc[1] = g_pw_cur[1]; + priv->g_pw_pre[1] = g_pw_cur[1]; + + g_pw_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x0000ff00); + if (g_pw_cur[2] >= priv->g_pw_pre[2]) + g_pw_inc[2] = g_pw_cur[2] - priv->g_pw_pre[2]; + else + g_pw_inc[2] = g_pw_cur[2]; + priv->g_pw_pre[2] = g_pw_cur[2]; + + g_pw_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000000ff); + if (g_pw_cur[3] >= priv->g_pw_pre[3]) + g_pw_inc[3] = g_pw_cur[3] - priv->g_pw_pre[3]; + else + g_pw_inc[3] = g_pw_cur[3]; + priv->g_pw_pre[3] = g_pw_cur[3]; + + g_pw_cur[4] = PHY_QueryBBReg(priv, 0xf5c, 0xff000000); + if (g_pw_cur[4] >= priv->g_pw_pre[4]) + g_pw_inc[4] = g_pw_cur[4] - priv->g_pw_pre[4]; + else + g_pw_inc[4] = g_pw_cur[4]; + priv->g_pw_pre[4] = g_pw_cur[4]; + + g_pw_cur[5] = PHY_QueryBBReg(priv, 0xf5c, 0x00ff0000); + if (g_pw_cur[5] >= priv->g_pw_pre[5]) + g_pw_inc[5] = g_pw_cur[5] - priv->g_pw_pre[5]; + else + g_pw_inc[5] = g_pw_cur[5]; + priv->g_pw_pre[5] = g_pw_cur[5]; + + g_total = g_pw_inc[0] + g_pw_inc[1] + g_pw_inc[2] + g_pw_inc[3] + g_pw_inc[4] + g_pw_inc[5]; + if(g_pw_inc[0] == 0) g0_ratio = 0; + else g0_ratio = g_total / g_pw_inc[0]; + if(g_pw_inc[1] == 0) g1_ratio = 0; + else g1_ratio = g_total / g_pw_inc[1]; + if(g_pw_inc[2] == 0) g2_ratio = 0; + else g2_ratio = g_total / g_pw_inc[2]; + if(g_pw_inc[3]== 0) g3_ratio = 0; + else g3_ratio = g_total / g_pw_inc[3]; + if(g_pw_inc[4]== 0) g4_ratio = 0; + else g4_ratio = g_total / g_pw_inc[4]; + if(g_pw_inc[5] == 0) g5_ratio = 0; + else g5_ratio = g_total / g_pw_inc[5]; + + // read pulse repetition interval hist report + PHY_SetBBReg(priv, 0x19e4, 0x00c00000, 3); // report selection = 3 (pulse repetition interval) + g_pri_cur[0] = PHY_QueryBBReg(priv, 0xf74, 0xff000000); + if (g_pri_cur[0] >= priv->g_pri_pre[0]) + g_pri_inc[0] = g_pri_cur[0] - priv->g_pri_pre[0]; + else + g_pri_inc[0] = g_pri_cur[0]; + priv->g_pri_pre[0] = g_pri_cur[0]; + + g_pri_cur[1] = PHY_QueryBBReg(priv, 0xf74, 0x00ff0000); + if (g_pri_cur[1] >= priv->g_pri_pre[1]) + g_pri_inc[1] = g_pri_cur[1] - priv->g_pri_pre[1]; + else + g_pri_inc[1] = g_pri_cur[1]; + priv->g_pri_pre[1] = g_pri_cur[1]; + + g_pri_cur[2] = PHY_QueryBBReg(priv, 0xf74, 0x0000ff00); + if (g_pri_cur[2] >= priv->g_pri_pre[2]) + g_pri_inc[2] = g_pri_cur[2] - priv->g_pri_pre[2]; + else + g_pri_inc[2] = g_pri_cur[2]; + priv->g_pri_pre[2] = g_pri_cur[2]; + + g_pri_cur[3] = PHY_QueryBBReg(priv, 0xf74, 0x000000ff); + if (g_pri_cur[3] >= priv->g_pri_pre[3]) + g_pri_inc[3] = g_pri_cur[3] - priv->g_pri_pre[3]; + else + g_pri_inc[3] = g_pri_cur[3]; + priv->g_pri_pre[3] = g_pri_cur[3]; + + g_pri_cur[4] = PHY_QueryBBReg(priv, 0xf5c, 0xff000000); + if (g_pri_cur[4] >= priv->g_pri_pre[4]) + g_pri_inc[4] = g_pri_cur[4] - priv->g_pri_pre[4]; + else + g_pri_inc[4] = g_pri_cur[4]; + priv->g_pri_pre[4] = g_pri_cur[4]; + + g_pri_cur[5] = PHY_QueryBBReg(priv, 0xf5c, 0x00ff0000); + if (g_pri_cur[5] >= priv->g_pri_pre[5]) + g_pri_inc[5] = g_pri_cur[5] - priv->g_pri_pre[5]; + else + g_pri_inc[5] = g_pri_cur[5]; + priv->g_pri_pre[5] = g_pri_cur[5]; + + need_reset = 0; + for(i = 0; i < 6; i++){ + if((priv->g_pw_pre[i]==255) || (priv->g_pri_pre[i] == 255)){ + need_reset = 1; + } + } + if(1){ + PHY_SetBBReg(priv, 0x19b4, 0x10000000, 1); // reset histogram report + PHY_SetBBReg(priv, 0x19b4, 0x10000000, 0); // continue histogram report + for(i = 0; i < 6; i++){ + priv->g_pw_pre[i]=0; + priv->g_pri_pre[i]=0; + } + for(i = 0; i < 16; i++){ + priv->g_ti_pre[i]=0; + } + }*/ + + if(DFS_tri_short_pulse || DFS_tri_long_pulse){ + //if(1){ +/* if(priv->pshare->rf_ft_var.dfs_print_hist_report){ + dfs_plusewidth_thd1 = PHY_QueryBBReg(priv, 0x19e4, 0xff000000); + dfs_plusewidth_thd2 = PHY_QueryBBReg(priv, 0x19e8, 0x000000ff); + dfs_plusewidth_thd3 = PHY_QueryBBReg(priv, 0x19e8, 0x0000ff00); + dfs_plusewidth_thd4 = PHY_QueryBBReg(priv, 0x19e8, 0x00ff0000); + dfs_plusewidth_thd5 = PHY_QueryBBReg(priv, 0x19e8, 0xff000000); + PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x0); + dfs_hist1_peak_index = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); + dfs_hist2_peak_index = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); + PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x1); + dfs_hist1_pulse_width = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); + dfs_hist2_pulse_width = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); + g_plusewidth[0] = (unsigned char)(dfs_hist2_pulse_width & 0xff000000)>>24; + g_plusewidth[1] = (unsigned char)(dfs_hist2_pulse_width & 0x00ff0000)>>16; + g_plusewidth[2] = (unsigned char)(dfs_hist2_pulse_width & 0x0000ff00)>>8; + g_plusewidth[3] = (unsigned char)dfs_hist2_pulse_width & 0x000000ff; + g_plusewidth[4] = (unsigned char)(dfs_hist1_pulse_width & 0xff000000)>>24; + g_plusewidth[5] = (unsigned char)(dfs_hist1_pulse_width & 0x00ff0000)>>16; + g_plusewidth_total = 0; + + for (i=0; i<6 ; i++) + g_plusewidth_total += g_plusewidth[i]; + + PHY_SetBBReg(priv, 0x19e4, BIT(22)|BIT(23), 0x2); + dfs_hist1_pulse_rep_intvl = PHY_QueryBBReg(priv, 0xf5c, 0xffffffff); + dfs_hist2_pulse_rep_intvl = PHY_QueryBBReg(priv, 0xf74, 0xffffffff); + PHY_SetBBReg(priv, 0x19b4, 0x10000000, 1); // reset histogram report + PHY_SetBBReg(priv, 0x19b4, 0x10000000, 0); // continue histogram report + panic_printk("dfs_plusewidth_thd=%d %d %d %d %d\n", + dfs_plusewidth_thd1, dfs_plusewidth_thd2, dfs_plusewidth_thd3, dfs_plusewidth_thd4, dfs_plusewidth_thd5); + panic_printk("peak index hist\n"); + panic_printk("dfs_hist_peak_index=%x %x\n", + dfs_hist1_peak_index, dfs_hist2_peak_index); + //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d, g6 = %d, g7 = %d\n", g_ti_inc[0], g_ti_inc[1], g_ti_inc[2], g_ti_inc[3], g_ti_inc[4], g_ti_inc[5], g_ti_inc[6], g_ti_inc[7]); + //panic_printk("g8 = %d, g9 = %d, g10 = %d, g11 = %d, g12 = %d, g13 = %d, g14 = %d, g15 = %d\n", g_ti_inc[8], g_ti_inc[9], g_ti_inc[10], g_ti_inc[11], g_ti_inc[12], g_ti_inc[13], g_ti_inc[14], g_ti_inc[15]); + panic_printk("pulse width hist\n"); + panic_printk("dfs_hist_pulse_width=%x %x\n", + dfs_hist1_pulse_width, dfs_hist2_pulse_width); + panic_printk("g_pulse_width_hist = %x %x %x %x %x %x, g_pulse_width_hist_total = %x\n", + g_plusewidth[0], g_plusewidth[1],g_plusewidth[2],g_plusewidth[3],g_plusewidth[4],g_plusewidth[5],g_plusewidth_total); + + //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d\n",g_pw_inc[0], g_pw_inc[1], g_pw_inc[2], g_pw_inc[3], g_pw_inc[4], g_pw_inc[5]); + //panic_printk("g0_ratio = %d, g1_ratio = %d, g2_ratio = %d, g3_ratio = %d, g4_ratio = %d, g5_ratio = %d\n", g0_ratio, g1_ratio, g2_ratio, g3_ratio, g4_ratio, g5_ratio); + //panic_printk("pulse repetition interval hist\n"); + //panic_printk("g0 = %d, g1 = %d, g2 = %d, g3 = %d, g4 = %d, g5 = %d\n",g_pri_inc[0], g_pri_inc[1], g_pri_inc[2], g_pri_inc[3], g_pri_inc[4], g_pri_inc[5]); + }*/ + + // MKK + if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 2) { + if((priv->pmib->dot11RFEntry.dot11channel >= 52) && (priv->pmib->dot11RFEntry.dot11channel <= 64)){ + // classify radar by pulse width hist + if(g_pw_inc[1] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w53 radar type1 is detected!\n"); + } + } + else if(g_pw_inc[3] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w53 radar type2 is detected!\n"); + } + } + else{ + DFS_tri_long_pulse = 0; + DFS_tri_short_pulse = 0; + } + } + else{ + if (DFS_tri_long_pulse){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type7 is detected!\n"); + } + } + else{ + if(g_pw_inc[0] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type1 is detected!\n"); + } + } + else if(g_pw_inc[1] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type2 or type8 is detected!\n"); + } + } + else if(g_pw_inc[2] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type3 is detected!\n"); + } + } + else if(g_pw_inc[1]+g_pw_inc[2]+g_pw_inc[3] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type4 is detected!\n"); + } + } + else if(g_pw_inc[4] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type5 is detected!\n"); + } + } + else if(g_pw_inc[5] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("MKK w56 radar type6 is detected!\n"); + } + } + else{ + DFS_tri_short_pulse = 0; + } + } + } + } + // ETSI + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 3){ + } + // FCC + else if(priv->pshare->rf_ft_var.manual_dfs_regdomain == 1){ + if (DFS_tri_long_pulse){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("FCC radar type5 is detected!\n"); + } + } + else{ + if(g_pw_inc[1] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("FCC radar type1 or type6 is detected!\n"); + } + } + else if(g_pw_inc[1] + g_pw_inc[2]>= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("FCC radar type2 is detected!\n"); + } + } + else if(g_pw_inc[3] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("FCC radar type3 is detected!\n"); + } + } + else if(g_pw_inc[4] >= short_pulse_th + 1){ + if(priv->pshare->rf_ft_var.dfs_radar_diff_print){ + panic_printk("FCC radar type4 is detected!\n"); + } + } + else{ + DFS_tri_short_pulse = 0; + } + } + } + else{ + } + } + +} +#endif //#if defined(CONFIG_WLAN_HAL_8814AE) + +#endif + diff --git a/package/kernel/rtl8192cd/8192cd_dmem.c b/package/kernel/rtl8192cd/8192cd_dmem.c index 9993e8622d2..f0a5762957e 100644 --- a/package/kernel/rtl8192cd/8192cd_dmem.c +++ b/package/kernel/rtl8192cd/8192cd_dmem.c @@ -1,286 +1,286 @@ -/* - * D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform - * - * $Id: 8192cd_dmem.c,v 1.2 2010/01/19 06:04:03 jimmylin Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifdef __ECOS -#include -#include -#include -#include -#endif - -#ifndef _8192CD_DMEM_C_ -#define _8192CD_DMEM_C_ - -#include "./8192cd.h" -//#include "./8190n_fastExtDev.h" -#include "./8192cd_cfg.h" - -#ifdef RTL8192CD_VARIABLE_USED_DMEM -#include "./8192cd_dmem.h" - -#define RTL8192CD_MAX_SPEEDUP_STA 2 -#define RTL8192CD_SPEEDUP_PRIV_COUNT 1 - -/* ========================== All variables using D-MEM ========================== */ -static void rtl8192cd_dmem_AID_OBJ_init(void); -static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo); -static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo); - -static void rtl8192cd_dmem_pmib_init(void); -static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo); -static void rtl8192cd_dmem_pmib_free(void *miscInfo); - -#ifdef PRIV_STA_BUF - extern struct aid_obj *alloc_sta_obj(struct rtl8192cd_priv*); - extern void free_sta_obj(struct rtl8192cd_priv *priv, struct aid_obj *obj); -#endif - -static _rtl8192cd_dmem_callBack_t _8192cd_dmem_callBack_list[] = -{ - /* ID Init CallBack Allocate CallBack Free CallBack */ - { AID_OBJ, rtl8192cd_dmem_AID_OBJ_init, rtl8192cd_dmem_AID_OBJ_alloc, rtl8192cd_dmem_AID_OBJ_free}, - { PMIB, rtl8192cd_dmem_pmib_init, rtl8192cd_dmem_pmib_alloc, rtl8192cd_dmem_pmib_free}, - /* ==================================================================== */ - { _RTL8192CD_DMEM_ITEM_MAX, NULL, NULL}, -}; - -/* ========================== External APIs of D-MEM module ========================== */ - -/* - Initiation function for DMEM library -*/ -void rtl8192cd_dmem_init( void ) -{ - _rtl8192cd_dmem_callBack_t *ptr; - - ptr = &_8192cd_dmem_callBack_list[0]; - - while ( (ptr->id > _RTL8192CD_DMEM_ITEM_MIN) && - (ptr->id < _RTL8192CD_DMEM_ITEM_MAX)) - { - /* Call the Callback function to decide the memory of allocated */ - if (ptr->initCallBackFunc) - { - ((_dummyFunc_void_void)(ptr->initCallBackFunc))(); - } - - /* Next Entry */ - ptr ++; - } -} - -void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ) -{ - void *retval; - _rtl8192cd_dmem_callBack_t *ptr; - - retval = NULL; - - if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) || - (id >= _RTL8192CD_DMEM_ITEM_MAX)) - { - printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id); - goto out; - } - - ptr = &_8192cd_dmem_callBack_list[0]; - - while ( ptr->allcateCallBackFunc ) - { - if ( ptr->id == id ) - { - /* Call the Callback function to decide the memory of allocated */ - retval = ((_dummyFunc_voidStar_voidStar)(ptr->allcateCallBackFunc))(miscInfo); - goto out; - } - /* Next Entry */ - ptr ++; - } - -out: - return retval; -} - -void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ) -{ - _rtl8192cd_dmem_callBack_t *ptr; - - if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) || - (id >= _RTL8192CD_DMEM_ITEM_MAX)) - { - printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id); - goto out; - } - - ptr = &_8192cd_dmem_callBack_list[0]; - - while ( ptr->freeCallBackFunc ) - { - if ( ptr->id == id ) - { - /* Call the Callback function to decide the memory of allocated */ - ((_dummyFunc_void_voidStar)(ptr->freeCallBackFunc))(miscInfo); - goto out; - } - /* Next Entry */ - ptr ++; - } - -out: - return; -} - - -/* ========================== Internal APIs for per-variable of D-MEM module ========================== */ - -/* ============================================== - * - * AID_OBJ - * - * - * ============================================== */ -__DRAM_IN_865X struct aid_obj _rtl8192cd_aid_Array[RTL8192CD_MAX_SPEEDUP_STA]; -void *_rtl8192cd_aid_externalMem_Array[NUM_STAT]; - -static void rtl8192cd_dmem_AID_OBJ_init(void) -{ - memset(_rtl8192cd_aid_Array, 0, sizeof(struct aid_obj) * RTL8192CD_MAX_SPEEDUP_STA); - memset(_rtl8192cd_aid_externalMem_Array, 0, sizeof(_rtl8192cd_aid_externalMem_Array)); -} - -static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo) -{ - /* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to allocate */ - unsigned int index = *((unsigned int*)miscInfo); - - if ( (index < 0) || - (index >= NUM_STAT)) - { - printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index); - return NULL; - } - - /* Allocate from external memory */ - if ( index >= RTL8192CD_MAX_SPEEDUP_STA ) - { -#ifdef PRIV_STA_BUF - _rtl8192cd_aid_externalMem_Array[index] = alloc_sta_obj(NULL); -#else - _rtl8192cd_aid_externalMem_Array[index] = kmalloc(sizeof(struct aid_obj), GFP_ATOMIC); -#endif - if (_rtl8192cd_aid_externalMem_Array[index] == NULL) - { - printk("%s %d : Error : Allocation FAILED!\n", __FUNCTION__, __LINE__); - return NULL; - } - return _rtl8192cd_aid_externalMem_Array[index]; - } - - memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj)); - - return (void*)(&(_rtl8192cd_aid_Array[index])); -} - -static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo) -{ - /* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to free */ - unsigned int index = *((unsigned int*)miscInfo); - - if ( (index < 0) || - (index >= NUM_STAT)) - { - printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index); - return; - } - - /* Free memory to external memory module */ - if ( index >= RTL8192CD_MAX_SPEEDUP_STA ) - { - if ( _rtl8192cd_aid_externalMem_Array[index] ) - { -#ifdef PRIV_STA_BUF - free_sta_obj(NULL, _rtl8192cd_aid_externalMem_Array[index]); -#else - kfree(_rtl8192cd_aid_externalMem_Array[index]); -#endif - _rtl8192cd_aid_externalMem_Array[index] = NULL; - } - - return; - } - - memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj)); -} - - -/* =================== The following variable are mapped to PRIV =================== */ - -/* ============================================== - * - * PMIB - * - * - * ============================================== */ -__DRAM_IN_865X struct wifi_mib _rtl8192cd_pmib[RTL8192CD_SPEEDUP_PRIV_COUNT]; -int _rtl8192cd_pmib_usageMap[RTL8192CD_SPEEDUP_PRIV_COUNT]; - -static void rtl8192cd_dmem_pmib_init(void) -{ - memset(_rtl8192cd_pmib_usageMap, 0, sizeof(int) * RTL8192CD_SPEEDUP_PRIV_COUNT); - memset(_rtl8192cd_pmib, 0, sizeof(struct wifi_mib) * RTL8192CD_SPEEDUP_PRIV_COUNT); -} - -static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo) -{ - int idx ; - - /* miscInfo is useless */ - for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ ) - { - if ( _rtl8192cd_pmib_usageMap[idx] == 0 ) - { /* Unused entry : use it */ - _rtl8192cd_pmib_usageMap[idx] = 1; - memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib)); - return &(_rtl8192cd_pmib[idx]); - } - } - - /* Allocate from externel memory if speedup PMIB is exhausted */ - return kmalloc(sizeof(struct wifi_mib), GFP_ATOMIC); - -} - -static void rtl8192cd_dmem_pmib_free(void *miscInfo) -{ - int idx; - - /* miscInfo is pointed to the address of PMIB to free */ - - /* Free PMIB if it is speeded up by DMEM */ - for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ ) - { - if ( (unsigned long)(&(_rtl8192cd_pmib[idx])) == (unsigned long)miscInfo ) - { /* Entry is found : free it */ - memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib)); - _rtl8192cd_pmib_usageMap[idx] = 0; - return; - } - } - - /* It would be allocated from external memory: kfree it */ - kfree(miscInfo); - -} -#endif // RTL8192CD_VARIABLE_USED_DMEM - -#endif - +/* + * D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform + * + * $Id: 8192cd_dmem.c,v 1.2 2010/01/19 06:04:03 jimmylin Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifdef __ECOS +#include +#include +#include +#include +#endif + +#ifndef _8192CD_DMEM_C_ +#define _8192CD_DMEM_C_ + +#include "./8192cd.h" +//#include "./8190n_fastExtDev.h" +#include "./8192cd_cfg.h" + +#ifdef RTL8192CD_VARIABLE_USED_DMEM +#include "./8192cd_dmem.h" + +#define RTL8192CD_MAX_SPEEDUP_STA 2 +#define RTL8192CD_SPEEDUP_PRIV_COUNT 1 + +/* ========================== All variables using D-MEM ========================== */ +static void rtl8192cd_dmem_AID_OBJ_init(void); +static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo); +static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo); + +static void rtl8192cd_dmem_pmib_init(void); +static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo); +static void rtl8192cd_dmem_pmib_free(void *miscInfo); + +#ifdef PRIV_STA_BUF + extern struct aid_obj *alloc_sta_obj(struct rtl8192cd_priv*); + extern void free_sta_obj(struct rtl8192cd_priv *priv, struct aid_obj *obj); +#endif + +static _rtl8192cd_dmem_callBack_t _8192cd_dmem_callBack_list[] = +{ + /* ID Init CallBack Allocate CallBack Free CallBack */ + { AID_OBJ, rtl8192cd_dmem_AID_OBJ_init, rtl8192cd_dmem_AID_OBJ_alloc, rtl8192cd_dmem_AID_OBJ_free}, + { PMIB, rtl8192cd_dmem_pmib_init, rtl8192cd_dmem_pmib_alloc, rtl8192cd_dmem_pmib_free}, + /* ==================================================================== */ + { _RTL8192CD_DMEM_ITEM_MAX, NULL, NULL}, +}; + +/* ========================== External APIs of D-MEM module ========================== */ + +/* + Initiation function for DMEM library +*/ +void rtl8192cd_dmem_init( void ) +{ + _rtl8192cd_dmem_callBack_t *ptr; + + ptr = &_8192cd_dmem_callBack_list[0]; + + while ( (ptr->id > _RTL8192CD_DMEM_ITEM_MIN) && + (ptr->id < _RTL8192CD_DMEM_ITEM_MAX)) + { + /* Call the Callback function to decide the memory of allocated */ + if (ptr->initCallBackFunc) + { + ((_dummyFunc_void_void)(ptr->initCallBackFunc))(); + } + + /* Next Entry */ + ptr ++; + } +} + +void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ) +{ + void *retval; + _rtl8192cd_dmem_callBack_t *ptr; + + retval = NULL; + + if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) || + (id >= _RTL8192CD_DMEM_ITEM_MAX)) + { + printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id); + goto out; + } + + ptr = &_8192cd_dmem_callBack_list[0]; + + while ( ptr->allcateCallBackFunc ) + { + if ( ptr->id == id ) + { + /* Call the Callback function to decide the memory of allocated */ + retval = ((_dummyFunc_voidStar_voidStar)(ptr->allcateCallBackFunc))(miscInfo); + goto out; + } + /* Next Entry */ + ptr ++; + } + +out: + return retval; +} + +void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ) +{ + _rtl8192cd_dmem_callBack_t *ptr; + + if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) || + (id >= _RTL8192CD_DMEM_ITEM_MAX)) + { + printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id); + goto out; + } + + ptr = &_8192cd_dmem_callBack_list[0]; + + while ( ptr->freeCallBackFunc ) + { + if ( ptr->id == id ) + { + /* Call the Callback function to decide the memory of allocated */ + ((_dummyFunc_void_voidStar)(ptr->freeCallBackFunc))(miscInfo); + goto out; + } + /* Next Entry */ + ptr ++; + } + +out: + return; +} + + +/* ========================== Internal APIs for per-variable of D-MEM module ========================== */ + +/* ============================================== + * + * AID_OBJ + * + * + * ============================================== */ +__DRAM_IN_865X struct aid_obj _rtl8192cd_aid_Array[RTL8192CD_MAX_SPEEDUP_STA]; +void *_rtl8192cd_aid_externalMem_Array[NUM_STAT]; + +static void rtl8192cd_dmem_AID_OBJ_init(void) +{ + memset(_rtl8192cd_aid_Array, 0, sizeof(struct aid_obj) * RTL8192CD_MAX_SPEEDUP_STA); + memset(_rtl8192cd_aid_externalMem_Array, 0, sizeof(_rtl8192cd_aid_externalMem_Array)); +} + +static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo) +{ + /* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to allocate */ + unsigned int index = *((unsigned int*)miscInfo); + + if ( (index < 0) || + (index >= NUM_STAT)) + { + printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index); + return NULL; + } + + /* Allocate from external memory */ + if ( index >= RTL8192CD_MAX_SPEEDUP_STA ) + { +#ifdef PRIV_STA_BUF + _rtl8192cd_aid_externalMem_Array[index] = alloc_sta_obj(NULL); +#else + _rtl8192cd_aid_externalMem_Array[index] = kmalloc(sizeof(struct aid_obj), GFP_ATOMIC); +#endif + if (_rtl8192cd_aid_externalMem_Array[index] == NULL) + { + printk("%s %d : Error : Allocation FAILED!\n", __FUNCTION__, __LINE__); + return NULL; + } + return _rtl8192cd_aid_externalMem_Array[index]; + } + + memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj)); + + return (void*)(&(_rtl8192cd_aid_Array[index])); +} + +static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo) +{ + /* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to free */ + unsigned int index = *((unsigned int*)miscInfo); + + if ( (index < 0) || + (index >= NUM_STAT)) + { + printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index); + return; + } + + /* Free memory to external memory module */ + if ( index >= RTL8192CD_MAX_SPEEDUP_STA ) + { + if ( _rtl8192cd_aid_externalMem_Array[index] ) + { +#ifdef PRIV_STA_BUF + free_sta_obj(NULL, _rtl8192cd_aid_externalMem_Array[index]); +#else + kfree(_rtl8192cd_aid_externalMem_Array[index]); +#endif + _rtl8192cd_aid_externalMem_Array[index] = NULL; + } + + return; + } + + memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj)); +} + + +/* =================== The following variable are mapped to PRIV =================== */ + +/* ============================================== + * + * PMIB + * + * + * ============================================== */ +__DRAM_IN_865X struct wifi_mib _rtl8192cd_pmib[RTL8192CD_SPEEDUP_PRIV_COUNT]; +int _rtl8192cd_pmib_usageMap[RTL8192CD_SPEEDUP_PRIV_COUNT]; + +static void rtl8192cd_dmem_pmib_init(void) +{ + memset(_rtl8192cd_pmib_usageMap, 0, sizeof(int) * RTL8192CD_SPEEDUP_PRIV_COUNT); + memset(_rtl8192cd_pmib, 0, sizeof(struct wifi_mib) * RTL8192CD_SPEEDUP_PRIV_COUNT); +} + +static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo) +{ + int idx ; + + /* miscInfo is useless */ + for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ ) + { + if ( _rtl8192cd_pmib_usageMap[idx] == 0 ) + { /* Unused entry : use it */ + _rtl8192cd_pmib_usageMap[idx] = 1; + memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib)); + return &(_rtl8192cd_pmib[idx]); + } + } + + /* Allocate from externel memory if speedup PMIB is exhausted */ + return kmalloc(sizeof(struct wifi_mib), GFP_ATOMIC); + +} + +static void rtl8192cd_dmem_pmib_free(void *miscInfo) +{ + int idx; + + /* miscInfo is pointed to the address of PMIB to free */ + + /* Free PMIB if it is speeded up by DMEM */ + for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ ) + { + if ( (unsigned long)(&(_rtl8192cd_pmib[idx])) == (unsigned long)miscInfo ) + { /* Entry is found : free it */ + memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib)); + _rtl8192cd_pmib_usageMap[idx] = 0; + return; + } + } + + /* It would be allocated from external memory: kfree it */ + kfree(miscInfo); + +} +#endif // RTL8192CD_VARIABLE_USED_DMEM + +#endif + diff --git a/package/kernel/rtl8192cd/8192cd_dmem.h b/package/kernel/rtl8192cd/8192cd_dmem.h index 5754202ea75..7cbc0cbf16f 100644 --- a/package/kernel/rtl8192cd/8192cd_dmem.h +++ b/package/kernel/rtl8192cd/8192cd_dmem.h @@ -1,44 +1,44 @@ -/* - * Header of D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform - * - * $Id: 8192cd_dmem.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _8192CD_DMEM_H -#define _8192CD_DMEM_H - -/* ========================= External ========================= */ - -enum _RTL8192CD_DMEM_ITEM_ID { - _RTL8192CD_DMEM_ITEM_MIN, - /* ============================== Add here ============================== */ - AID_OBJ, - PMIB, - /* =================================================================== */ - _RTL8192CD_DMEM_ITEM_MAX, -}; - -void rtl8192cd_dmem_init( void ); -void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ); -void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ); - - -/* ========================= Internal ========================= */ -typedef void* (*_dummyFunc_voidStar_voidStar)(void*); -typedef void (*_dummyFunc_void_voidStar)(void*); -typedef void (*_dummyFunc_void_void)(void); -typedef struct _rtl8192cd_dmem_list_s -{ - int id; - void * initCallBackFunc; - void * allcateCallBackFunc; - void * freeCallBackFunc; -} _rtl8192cd_dmem_callBack_t; - -#endif /* _8192CD_DMEM_H */ +/* + * Header of D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform + * + * $Id: 8192cd_dmem.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _8192CD_DMEM_H +#define _8192CD_DMEM_H + +/* ========================= External ========================= */ + +enum _RTL8192CD_DMEM_ITEM_ID { + _RTL8192CD_DMEM_ITEM_MIN, + /* ============================== Add here ============================== */ + AID_OBJ, + PMIB, + /* =================================================================== */ + _RTL8192CD_DMEM_ITEM_MAX, +}; + +void rtl8192cd_dmem_init( void ); +void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ); +void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo ); + + +/* ========================= Internal ========================= */ +typedef void* (*_dummyFunc_voidStar_voidStar)(void*); +typedef void (*_dummyFunc_void_voidStar)(void*); +typedef void (*_dummyFunc_void_void)(void); +typedef struct _rtl8192cd_dmem_list_s +{ + int id; + void * initCallBackFunc; + void * allcateCallBackFunc; + void * freeCallBackFunc; +} _rtl8192cd_dmem_callBack_t; + +#endif /* _8192CD_DMEM_H */ diff --git a/package/kernel/rtl8192cd/8192cd_hw.c b/package/kernel/rtl8192cd/8192cd_hw.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_hw.h b/package/kernel/rtl8192cd/8192cd_hw.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_ioctl.c b/package/kernel/rtl8192cd/8192cd_ioctl.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_led.c b/package/kernel/rtl8192cd/8192cd_led.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_log.h b/package/kernel/rtl8192cd/8192cd_log.h old mode 100755 new mode 100644 index 9ce5a1d9c6b..214b66d4efc --- a/package/kernel/rtl8192cd/8192cd_log.h +++ b/package/kernel/rtl8192cd/8192cd_log.h @@ -1,45 +1,45 @@ - -#ifndef 8192CD_LOG_H -#define 8192CD_LOG_H - -#if defined(CONFIG_RTL_LOG_DEBUG) - - #if defined(LOG_ERROR) - #undef LOG_ERROR - #define LOG_ERROR(fmt, args...) do{ \ - if(RTL_LogTypeMask.ERROR&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-ERROR:"fmt, ## args); \ - }while(0) - #endif - - #if defined(LOG_MEM_ERROR) - #undef LOG_MEM_ERROR - #define LOG_MEM_ERROR(fmt, args...) do{ \ - if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.MEM&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-MEM-ERROR:"fmt, ## args); \ - }while(0) - #endif - - #if defined(LOG_SKB_ERROR) - #undef LOG_SKB_ERROR - #define LOG_SKB_ERROR(fmt, args...) do{ \ - if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.SKB&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-SKB-ERROR:"fmt, ## args); \ - }while(0) - #endif - - #if defined(LOG_WARN) - #undef LOG_WARN - #define LOG_WARN(fmt, args...) do{ \ - if(RTL_LogTypeMask.WARN&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-WARN:"fmt, ## args); \ - }while(0) - #endif - - #if defined(LOG_INFO) - #undef LOG_INFO - #define LOG_INFO(fmt, args...) do{ \ - if(RTL_LogTypeMask.INFO&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-INFO:"fmt, ## args); \ - }while(0) - #endif - -#endif - -#endif - + +#ifndef 8192CD_LOG_H +#define 8192CD_LOG_H + +#if defined(CONFIG_RTL_LOG_DEBUG) + + #if defined(LOG_ERROR) + #undef LOG_ERROR + #define LOG_ERROR(fmt, args...) do{ \ + if(RTL_LogTypeMask.ERROR&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-ERROR:"fmt, ## args); \ + }while(0) + #endif + + #if defined(LOG_MEM_ERROR) + #undef LOG_MEM_ERROR + #define LOG_MEM_ERROR(fmt, args...) do{ \ + if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.MEM&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-MEM-ERROR:"fmt, ## args); \ + }while(0) + #endif + + #if defined(LOG_SKB_ERROR) + #undef LOG_SKB_ERROR + #define LOG_SKB_ERROR(fmt, args...) do{ \ + if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.SKB&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-SKB-ERROR:"fmt, ## args); \ + }while(0) + #endif + + #if defined(LOG_WARN) + #undef LOG_WARN + #define LOG_WARN(fmt, args...) do{ \ + if(RTL_LogTypeMask.WARN&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-WARN:"fmt, ## args); \ + }while(0) + #endif + + #if defined(LOG_INFO) + #undef LOG_INFO + #define LOG_INFO(fmt, args...) do{ \ + if(RTL_LogTypeMask.INFO&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-INFO:"fmt, ## args); \ + }while(0) + #endif + +#endif + +#endif + diff --git a/package/kernel/rtl8192cd/8192cd_mib.c b/package/kernel/rtl8192cd/8192cd_mib.c index 2aa47f43952..d0d0a34b7eb 100644 --- a/package/kernel/rtl8192cd/8192cd_mib.c +++ b/package/kernel/rtl8192cd/8192cd_mib.c @@ -1,560 +1,560 @@ -/* - * SNMP MIB module - * - * $Id: 8192cd_mib.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#define _8192CD_MIB_C_ - -#ifdef __KERNEL__ -#include -#elif defined(__ECOS) -#include -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" - -#ifdef SUPPORT_SNMP_MIB - -#if defined(__KERNEL__) || defined(__OSK__) -#include "./ieee802_mib.h" -#elif defined(__ECOS) -#include -#endif -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" -#include "./8192cd_mib.h" - -extern int _convert_2_pwr_dot(char *s, int base); -extern int _atoi(char *s, int base); - -struct mib_val dot11_mib_table[]={ - //dot11StationConfigTable - { {1, 1, 1, 1, 1, -1}, "dot11StationID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)}, - { {1, 1, 1, 2, 1, -1}, "dot11MediumOccupancyLimit ", MIB_TYPE_VAL, 100, 1}, - { {1, 1, 1, 3, 1, -1}, "dot11CFPollable", MIB_TYPE_VAL, 0, 1}, - { {1, 1, 1, 4, 1, -1}, "dot11CFPPeriod", MIB_TYPE_VAL, 0, 1}, - { {1, 1, 1, 5, 1, -1}, "dot11CFPMaxDuration", MIB_TYPE_VAL, 0, 1}, - { {1, 1, 1, 6, 1, -1}, "dot11AuthenticationResponseTimeOut", MIB_TYPE_VAL, REAUTH_TO*10, 4}, - { {1, 1, 1, 7, 1, -1}, "dot11PrivacyOptionImplemented", MIB_TYPE_VAL, 1, 1}, - { {1, 1, 1, 8, 1, -1}, "dot11PowerManagementMode", MIB_TYPE_VAL, 1, 1}, - { {1, 1, 1, 9, 1, -1}, "dot11DesiredSSID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DesiredSSID), 0}, - { {1, 1, 1, 10, 1, -1}, "dot11DesiredBSSType", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DesiredBSSType), SNMP_SIZE(dot11DesiredBSSType)}, - { {1, 1, 1, 11, 1, -1}, "dot11OperationalRateSet", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11OperationalRateSet), SNMP_OFFSET(dot11SupportedDataRatesNum)}, - { {1, 1, 1, 12, 1, -1}, "dot11BeaconPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11BeaconPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11BeaconPeriod)}, - { {1, 1, 1, 13, 1, -1}, "dot11DTIMPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DTIMPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11DTIMPeriod)}, - { {1, 1, 1, 14, 1, -1}, "dot11AssociationResponseTimeOut", MIB_TYPE_VAL, REASSOC_TO*10, 4}, - { {1, 1, 1, 15, 1, -1}, "dot11DisassociateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateReason), SNMP_SIZE(dot11DisassociateReason)}, - { {1, 1, 1, 16, 1, -1}, "dot11DisassociateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateStation), SNMP_SIZE(dot11DisassociateStation)}, - { {1, 1, 1, 17, 1, -1}, "dot11DeauthenticateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateReason), SNMP_SIZE(dot11DeauthenticateReason)}, - { {1, 1, 1, 18, 1, -1}, "dot11DeauthenticateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateStation), SNMP_SIZE(dot11DeauthenticateStation)}, - { {1, 1, 1, 19, 1, -1}, "dot11AuthenticateFailStatus", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStatus), SNMP_SIZE(dot11AuthenticateFailStatus)}, - { {1, 1, 1, 20, 1, -1}, "dot11AuthenticateFailStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStation), SNMP_SIZE(dot11AuthenticateFailStation)}, - { {1, 1, 1, 24, 1, -1}, "dot11RegDomain", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11RegDomain), PRIV_SIZE(dot11StationConfigEntry.dot11RegDomain)}, - { {1, 1, 1, 25, 1, -1}, "dot11DataRate", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DataRate), SNMP_SIZE(dot11DataRate)}, - { {1, 1, 1, 26, 1, -1}, "dot11ProtectionDisabled", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.protectionDisabled), PRIV_SIZE(dot11StationConfigEntry.protectionDisabled)}, - { {1, 1, 1, 27, 1, -1}, "dot11nSTBC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nSTBC), PRIV_SIZE(dot11nConfigEntry.dot11nSTBC)}, - { {1, 1, 1, 28, 1, -1}, "dot11nCoexist", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nCoexist), PRIV_SIZE(dot11nConfigEntry.dot11nCoexist)}, - { {1, 1, 1, 29, 1, -1}, "dot11nUse40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nUse40M), PRIV_SIZE(dot11nConfigEntry.dot11nUse40M)}, - { {1, 1, 1, 30, 1, -1}, "dot11n2ndChOffset", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11n2ndChOffset), PRIV_SIZE(dot11nConfigEntry.dot11n2ndChOffset)}, - { {1, 1, 1, 31, 1, -1}, "dot11nShortGIfor20M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor20M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor20M)}, - { {1, 1, 1, 32, 1, -1}, "dot11nShortGIfor40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor40M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor40M)}, - { {1, 1, 1, 33, 1, -1}, "dot11nAMPDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMPDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMPDU)}, - { {1, 1, 1, 34, 1, -1}, "dot11nAMSDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMSDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMSDU)}, - { {1, 1, 1, 35, 1, -1}, "dot11nLDPC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nLDPC), PRIV_SIZE(dot11nConfigEntry.dot11nLDPC)}, - //dot11AuthenticationAlgorithmsTable - { {1, 2, 1, 1, 1, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 1, 1}, - { {1, 2, 1, 2, 1, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 1, 1}, - { {1, 2, 1, 3, 1, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableOpen), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableOpen)}, - { {1, 2, 1, 1, 2, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 2, 1}, - { {1, 2, 1, 2, 2, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 2, 1}, - { {1, 2, 1, 3, 2, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableShared), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableShared)}, - - //dot11WEPDefaultKeysTable - { {1, 3, 1, 1, 1, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 1, 1}, - { {1, 3, 1, 2, 1, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey1), SNMP_SIZE(dot11WEPDefaultKeyLen)}, - { {1, 3, 1, 1, 2, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 2, 1}, - { {1, 3, 1, 2, 2, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey2), SNMP_SIZE(dot11WEPDefaultKeyLen)}, - { {1, 3, 1, 1, 3, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 3, 1}, - { {1, 3, 1, 2, 3, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey3), SNMP_SIZE(dot11WEPDefaultKeyLen)}, - { {1, 3, 1, 1, 4, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 4, 1}, - { {1, 3, 1, 2, 4, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey4), SNMP_SIZE(dot11WEPDefaultKeyLen)}, - - //dot11WEPKeyMappingsTable - { {1, 4, 1, 1, 1, -1}, "dot11WEPKeyMappingIndex", MIB_TYPE_VAL, 1, 1}, - { {1, 4, 1, 2, 1, -1}, "dot11WEPKeyMappingAddress", 0}, - { {1, 4, 1, 3, 1, -1}, "dot11WEPKeyMappingWEPOn", 0}, - { {1, 4, 1, 4, 1, -1}, "dot11WEPKeyMappingValue", 0}, - { {1, 4, 1, 5, 1, -1}, "dot11WEPKeyMappingStatus", 0}, - - //dot11PrivacyTable - { {1, 5, 1, 1, 1, -1}, "dot11PrivacyInvoked", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)}, - { {1, 5, 1, 2, 1, -1}, "dot11WEPDefaultKeyID", MIB_TYPE_PRIV, PRIV_OFFSET(dot1180211AuthEntry.dot11PrivacyKeyIndex), PRIV_SIZE(dot1180211AuthEntry.dot11PrivacyKeyIndex)}, - { {1, 5, 1, 3, 1, -1}, "dot11WEPKeyMappingLength", MIB_TYPE_VAL, 10, 1}, - { {1, 5, 1, 4, 1, -1}, "dot11ExcludeUnencrypted", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)}, - { {1, 5, 1, 5, 1, -1}, "dot11WEPICVErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPICVErrorCount), SNMP_SIZE(dot11WEPICVErrorCount)}, - { {1, 5, 1, 6, 1, -1}, "dot11WEPExcludedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPExcludedCount), SNMP_SIZE(dot11WEPExcludedCount)}, - - { {1, 8, 1, 1, 1, -1}, "dot11WPAKeyIndex", MIB_TYPE_VAL, 1, 1}, - { {1, 8, 1, 2, 1, -1}, "dot11WPAKeyFormat", MIB_TYPE_VAL, 1, 1}, - { {1, 8, 1, 3, 1, -1}, "dot11WPAKeyValue", MIB_TYPE_VAL, 1, 1}, - { {1, 9, 1, 1, 1, -1}, "dot11WPA2KeyIndex", MIB_TYPE_VAL, 1, 1}, - { {1, 9, 1, 2, 1, -1}, "dot11WPA2KeyFormat", MIB_TYPE_VAL, 1, 1}, - { {1, 9, 1, 3, 1, -1}, "dot11WPA2KeyValue", MIB_TYPE_VAL, 1, 1}, - { {1, 10, 1, 1, 1, -1}, "dot11RadiusServerIPAddress", MIB_TYPE_VAL, 1, 1}, - { {1, 10, 1, 2, 1, -1}, "dot11RadiusServerPort", MIB_TYPE_VAL, 1, 1}, - { {1, 10, 1, 3, 1, -1}, "dot11RadiusServerPassword", MIB_TYPE_VAL, 1, 1}, - { {1, 10, 1, 4, 1, -1}, "dot11RadiusServerEnable", MIB_TYPE_VAL, 1, 1}, - //dot11OperationTable - { {2, 1, 1, 1, 1, -1}, "dot11MACAddress", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)}, - { {2, 1, 1, 2, 1, -1}, "dot11RTSThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11RTSThreshold), PRIV_SIZE(dot11OperationEntry.dot11RTSThreshold)}, - { {2, 1, 1, 3, 1, -1}, "dot11ShortRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11ShortRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11ShortRetryLimit)}, - { {2, 1, 1, 4, 1, -1}, "dot11LongRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11LongRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11LongRetryLimit)}, - { {2, 1, 1, 5, 1, -1}, "dot11FragmentationThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11FragmentationThreshold), PRIV_SIZE(dot11OperationEntry.dot11FragmentationThreshold)}, - { {2, 1, 1, 6, 1, -1}, "dot11MaxTransmitMSDULifetime", MIB_TYPE_VAL, 512, 1}, - { {2, 1, 1, 7, 1, -1}, "dot11MaxReceiveLifetime", MIB_TYPE_VAL, FRAG_TO*10, 4}, - { {2, 1, 1, 8, 1, -1}, "dot11ManufacturerID", MIB_TYPE_VAL, (int)"Realtek", 0}, - { {2, 1, 1, 9, 1, -1}, "dot11ProductID", MIB_TYPE_VAL, (int)"RTL8185/RTL8186", 0}, - { {2, 1, 1, 10, 1, -1}, "dot11IappEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.iapp_enable), PRIV_SIZE(dot11OperationEntry.iapp_enable)}, - { {2, 1, 1, 11, 1, -1}, "dot11BlockRelay", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.block_relay), PRIV_SIZE(dot11OperationEntry.block_relay)}, - { {2, 1, 1, 12, 1, -1}, "dot11WIFISpecific", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.wifi_specific), PRIV_SIZE(dot11OperationEntry.wifi_specific)}, - { {2, 1, 1, 13, 1, -1}, "dot11QosEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11QosEntry.dot11QosEnable), PRIV_SIZE(dot11QosEntry.dot11QosEnable)}, - { {2, 1, 1, 14, 1, -1}, "dot11NetworkType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11BssType.net_work_type), PRIV_SIZE(dot11BssType.net_work_type)}, - { {2, 1, 1, 15, 1, -1}, "dot11LedType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.ledtype), PRIV_SIZE(dot11OperationEntry.ledtype)}, - { {2, 1, 1, 16, 1, -1}, "dot11OperationMode", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.opmode), PRIV_SIZE(dot11OperationEntry.opmode)}, - { {2, 1, 1, 17, 1, -1}, "dot11BroadCastSSID", MIB_TYPE_PRIV,PRIV_OFFSET(miscEntry.show_hidden_bss), PRIV_SIZE(miscEntry.show_hidden_bss)}, - { {2, 1, 1, 18, 1, -1}, "dot11GuestAccess", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.guest_access), PRIV_SIZE(dot11OperationEntry.guest_access)}, - - //dot11CountersTable - { {2, 2, 1, 1, 1, -1}, "dot11TransmittedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFragmentCount), SNMP_SIZE(dot11TransmittedFragmentCount)}, - { {2, 2, 1, 2, 1, -1}, "dot11MulticastTransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastTransmittedFrameCount), SNMP_SIZE(dot11MulticastTransmittedFrameCount)}, - { {2, 2, 1, 3, 1, -1}, "dot11FailedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FailedCount), SNMP_SIZE(dot11FailedCount)}, - { {2, 2, 1, 4, 1, -1}, "dot11RetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RetryCount), SNMP_SIZE(dot11RetryCount)}, - { {2, 2, 1, 5, 1, -1}, "dot11MultipleRetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MultipleRetryCount), SNMP_SIZE(dot11MultipleRetryCount)}, - { {2, 2, 1, 6, 1, -1}, "dot11FrameDuplicateCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FrameDuplicateCount), SNMP_SIZE(dot11FrameDuplicateCount)}, - { {2, 2, 1, 7, 1, -1}, "dot11RTSSuccessCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSSuccessCount), SNMP_SIZE(dot11RTSSuccessCount)}, - { {2, 2, 1, 8, 1, -1}, "dot11RTSFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSFailureCount), SNMP_SIZE(dot11RTSFailureCount)}, - { {2, 2, 1, 9, 1, -1}, "dot11ACKFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ACKFailureCount), SNMP_SIZE(dot11ACKFailureCount)}, - { {2, 2, 1, 10, 1, -1}, "dot11ReceivedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ReceivedFragmentCount), SNMP_SIZE(dot11ReceivedFragmentCount)}, - { {2, 2, 1, 11, 1, -1}, "dot11MulticastReceivedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastReceivedFrameCount), SNMP_SIZE(dot11MulticastReceivedFrameCount)}, - { {2, 2, 1, 12, 1, -1}, "dot11FCSErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FCSErrorCount), SNMP_SIZE(dot11FCSErrorCount)}, - { {2, 2, 1, 13, 1, -1}, "dot11TransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFrameCount), SNMP_SIZE(dot11TransmittedFrameCount)}, - { {2, 2, 1, 14, 1, -1}, "dot11WEPUndecryptableCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPUndecryptableCount), SNMP_SIZE(dot11WEPUndecryptableCount)}, - - //dot11GroupAddressesTable - { {2, 3, 1, 1, 1, -1}, "dot11GroupAddressesIndex", MIB_TYPE_VAL, 1, 1}, - { {2, 3, 1, 2, 1, -1}, "dot11Address", 0}, - { {2, 3, 1, 3, 1, -1}, "dot11GroupAddressesStatus", 0}, - - { {3, 1, 1, 0, -1}, "dot11ResourceTypeIDName", MIB_TYPE_VAL, (int)"8185", 0}, - - //dot11ResourceInfoTable - { {3, 1, 2, 1, 1, 1, -1}, "dot11manufacturerOUI", MIB_TYPE_VAL, (int)"\x00\xE0\x4C", 3}, - { {3, 1, 2, 1, 2, 1, -1}, "dot11manufacturerName", MIB_TYPE_VAL, (int)"Realtek", 0}, - { {3, 1, 2, 1, 3, 1, -1}, "dot11manufacturerProductName", MIB_TYPE_VAL, (int)"Wireless 802.11 b/g", 0}, - { {3, 1, 2, 1, 4, 1, -1}, "dot11manufacturerProductVersion", MIB_TYPE_VAL, (int)"v1.00", 0}, - - //dot11PhyOperationTable - { {4, 1, 1, 1, 1, -1}, "dot11PHYType", MIB_TYPE_VAL, 2, 1}, - { {4, 1, 1, 2, 1, -1}, "dot11CurrentRegDomain", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentRegDomain), SNMP_SIZE(dot11CurrentRegDomain)}, - { {4, 1, 1, 3, 1, -1}, "dot11TempType", MIB_TYPE_VAL, 1, 1}, - { {4, 1, 1, 4, 1, -1}, "dot11ShortPreamble",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.shortpreamble), PRIV_SIZE(dot11RFEntry.shortpreamble)}, - { {4, 1, 1, 5, 1, -1}, "dot11PhyBandSelect",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.phyBandSelect), PRIV_SIZE(dot11RFEntry.phyBandSelect)}, - { {4, 1, 1, 6, 1, -1}, "dot11TrSwitch",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.trswitch), PRIV_SIZE(dot11RFEntry.trswitch)}, - { {4, 1, 1, 7, 1, -1}, "dot11PowerScale", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PowerScale), SNMP_SIZE(dot11PowerScale)}, - - //dot11PhyAntennaTable - { {4, 2, 1, 1, 1, -1}, "dot11CurrentTxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)}, - { {4, 2, 1, 2, 1, -1}, "dot11DiversitySupport", MIB_TYPE_VAL, 2, 1}, - { {4, 2, 1, 3, 1, -1}, "dot11CurrentRxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)}, - - //dot11PhyTxPowerTable - { {4, 3, 1, 1, 1, -1}, "dot11NumberSupportedPowerLevels", MIB_TYPE_VAL, 4, 1}, - { {4, 3, 1, 2, 1, -1}, "dot11TxPowerLevel1", MIB_TYPE_VAL, 25, 1}, - { {4, 3, 1, 3, 1, -1}, "dot11TxPowerLevel2", MIB_TYPE_VAL, 12, 1}, - { {4, 3, 1, 4, 1, -1}, "dot11TxPowerLevel3", MIB_TYPE_VAL, 6, 1}, - { {4, 3, 1, 5, 1, -1}, "dot11TxPowerLevel4", MIB_TYPE_VAL, 3, 1}, - { {4, 3, 1, 6, 1, -1}, "dot11TxPowerLevel5", MIB_TYPE_VAL, 0, 1}, - { {4, 3, 1, 7, 1, -1}, "dot11TxPowerLevel6", MIB_TYPE_VAL, 0, 1}, - { {4, 3, 1, 8, 1, -1}, "dot11TxPowerLevel7", MIB_TYPE_VAL, 0, 1}, - { {4, 3, 1, 9, 1, -1}, "dot11TxPowerLevel8", MIB_TYPE_VAL, 0, 1}, - { {4, 3, 1, 10, 1, -1}, "dot11CurrentTxPowerLevel", 0}, // NCTU - - //dot11PhyDSSSTable - { {4, 5, 1, 1, 1, -1}, "dot11CurrentChannel", MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.dot11channel), PRIV_SIZE(dot11RFEntry.dot11channel)}, - { {4, 5, 1, 2, 1, -1}, "dot11CCAModeSupported", MIB_TYPE_VAL, 4, 1}, - { {4, 5, 1, 3, 1, -1}, "dot11CurrentCCAMode", MIB_TYPE_VAL, 4, 1}, - { {4, 5, 1, 4, 1, -1}, "dot11EDThreshold", MIB_TYPE_VAL, 0, 1}, - - //dot11RegDomainsSupportedTable - { {4, 7, 1, 1, 1, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 1, 1}, - { {4, 7, 1, 2, 1, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 16, 1}, - { {4, 7, 1, 1, 2, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 2, 1}, - { {4, 7, 1, 2, 2, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 32, 1}, - { {4, 7, 1, 1, 3, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 3, 1}, - { {4, 7, 1, 2, 3, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 48, 1}, - { {4, 7, 1, 1, 4, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 4, 1}, - { {4, 7, 1, 2, 4, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 49, 1}, - { {4, 7, 1, 1, 5, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 5, 1}, - { {4, 7, 1, 2, 5, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 50, 1}, - { {4, 7, 1, 1, 6, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 6, 1}, - { {4, 7, 1, 2, 6, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 64, 1}, - - //dot11AntennasListTable - { {4, 8, 1, 1, 1, -1}, "dot11AntennaListIndex", MIB_TYPE_VAL, 1, 1}, - { {4, 8, 1, 2, 1, -1}, "dot11SupportedTxAntenna", MIB_TYPE_VAL, 1, 1}, - { {4, 8, 1, 3, 1, -1}, "dot11SupportedRxAntenna", MIB_TYPE_VAL, 1, 1}, - { {4, 8, 1, 4, 1, -1}, "dot11DiversitySelectionRx", MIB_TYPE_VAL, 1, 1}, - - //dot11SupportedDataRatesTxTable - { {4, 9, 1, 1, 1, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 1, 1}, - { {4, 9, 1, 2, 1, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4}, - { {4, 9, 1, 1, 2, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 2, 1}, - { {4, 9, 1, 2, 2, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4}, - { {4, 9, 1, 1, 3, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 3, 1}, - { {4, 9, 1, 2, 3, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4}, - { {4, 9, 1, 1, 4, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 4, 1}, - { {4, 9, 1, 2, 4, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4}, - { {4, 9, 1, 1, 5, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 5, 1}, - { {4, 9, 1, 2, 5, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4}, - { {4, 9, 1, 1, 6, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 6, 1}, - { {4, 9, 1, 2, 6, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4}, - { {4, 9, 1, 1, 7, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 7, 1}, - { {4, 9, 1, 2, 7, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4}, - { {4, 9, 1, 1, 8, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 8, 1}, - { {4, 9, 1, 2, 8, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4}, - { {4, 9, 1, 1, 9, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 9, 1}, - { {4, 9, 1, 2, 9, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4}, - { {4, 9, 1, 1, 10, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 10, 1}, - { {4, 9, 1, 2, 10, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4}, - { {4, 9, 1, 1, 11, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 11, 1}, - { {4, 9, 1, 2, 11, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4}, - { {4, 9, 1, 1, 12, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 12, 1}, - { {4, 9, 1, 2, 12, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4}, - - //dot11SupportedDataRatesRxTable - { {4, 10, 1, 1, 1, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 1, 1}, - { {4, 10, 1, 2, 1, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4}, - { {4, 10, 1, 1, 2, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 2, 1}, - { {4, 10, 1, 2, 2, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4}, - { {4, 10, 1, 1, 3, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 3, 1}, - { {4, 10, 1, 2, 3, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4}, - { {4, 10, 1, 1, 4, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 4, 1}, - { {4, 10, 1, 2, 4, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4}, - { {4, 10, 1, 1, 5, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 5, 1}, - { {4, 10, 1, 2, 5, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4}, - { {4, 10, 1, 1, 6, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 6, 1}, - { {4, 10, 1, 2, 6, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4}, - { {4, 10, 1, 1, 7, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 7, 1}, - { {4, 10, 1, 2, 7, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4}, - { {4, 10, 1, 1, 8, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 8, 1}, - { {4, 10, 1, 2, 8, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4}, - { {4, 10, 1, 1, 9, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 9, 1}, - { {4, 10, 1, 2, 9, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4}, - { {4, 10, 1, 1, 10, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 10, 1}, - { {4, 10, 1, 2, 10, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4}, - { {4, 10, 1, 1, 11, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 11, 1}, - { {4, 10, 1, 2, 11, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4}, - { {4, 10, 1, 1, 12, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 12, 1}, - { {4, 10, 1, 2, 12, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4}, - - // Number of table entry, Realtek proprietary - { {6, 1, -1}, "dot11StationConfigEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 2, -1}, "dot11AuthenticationAlgorithmsEntryNum", MIB_TYPE_VAL, 2, 1}, - { {6, 3, -1}, "dot11WEPDefaultKeysEntryNum", MIB_TYPE_VAL, 4, 1}, - { {6, 4, -1}, "dot11WEPKeyMappingsEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 5, -1}, "dot11PrivacyEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 6, -1}, "dot11OperationEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 7, -1}, "dot11CountersEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 8, -1}, "dot11GroupAddressesEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 9, -1}, "dot11ResourceInfoTableNum", MIB_TYPE_VAL, 1, 1}, - { {6, 10, -1}, "dot11PhyOperationEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 11, -1}, "dot11PhyAntennaEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 12, -1}, "dot11PhyTxPowerEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 13, -1}, "dot11PhyDSSSEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 14, -1}, "dot11RegDomainsSupportEntryNum", MIB_TYPE_VAL, 6, 1}, - { {6, 15, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 16, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 17, -1}, "dot11SupportedDataRatesTxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)}, - { {6, 18, -1}, "dot11SupportedDataRatesRxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)}, - { {6, 19, -1}, "dot11MultiDomainCapabilityEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 20, -1}, "dot11WPAKeysEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 21, -1}, "dot11WPA2KeysEntryNum", MIB_TYPE_VAL, 1, 1}, - { {6, 22, -1}, "dot11RadiusServerNum", MIB_TYPE_VAL, 1, 1}, - - { {-1}, NULL, 0} -}; - - -static int add_mib_entry(struct rtl8192cd_priv *priv, struct mib_val *ent) -{ - int i=0, round = 0; - struct mib_entry **mib=&priv->snmp_mib.mib_tree, *pre_mib=NULL; - - while(1) { - if (ent->oid[i] == -1) - break; - if (*mib == NULL) { - if (priv->snmp_mib.tree_used_index == MAX_MIB_TREE_NUM) { - printk("Exceed max mib tree number\n"); - return -1; - } - *mib = &priv->snmp_mib.mib_list[priv->snmp_mib.tree_used_index++]; - } - - if ((*mib)->id == -1 || ent->oid[i] == (*mib)->id) { - if ((*mib)->id == -1) - (*mib)->id = ent->oid[i]; - i++; - pre_mib = *mib; - mib = &((*mib)->next_level); - } - else - mib = &((*mib)->next_node); - - if (++round > 10000) { - panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); - break; - } - } - - if (pre_mib == NULL) { - printk("build mib tree error, no parent mib found!\n"); - return -1; - } - if (pre_mib->val) { - printk("build mib tree error, mib value has been assigned!\n"); - return -1; - } - pre_mib->val = ent; - return 0; -} - -static void name2oid(char *name, int *oid) -{ - int i=0; - char *src=name, *ptr; - while (*src) { - ptr = strstr(src, "."); - if (ptr) - *ptr = '\0'; - oid[i++] = _atoi(src, 10); - - if (ptr==NULL) - break; - src = ++ptr; - } - oid[i] = -1; -} - -static struct mib_val *search_mib(struct rtl8192cd_priv *priv, char *id) -{ - int i=0; - struct mib_entry *mib=priv->snmp_mib.mib_tree, *pre_mib=NULL; - int oid[100]; - - name2oid(id, oid); - - while (oid[i] != -1) { - if (mib == NULL || mib->id == -1) - return NULL; - if (mib->id == oid[i]) { - pre_mib = mib; - mib = mib->next_level; - i++; - } - else { - pre_mib = NULL; - mib = mib->next_node; - } - } - - if (pre_mib && pre_mib->val) - return pre_mib->val; - else - return NULL; -} - -static void build_tree(struct rtl8192cd_priv *priv) -{ - int i=0; - struct mib_val *tbl = dot11_mib_table; - - for (i=0; isnmp_mib.mib_list[i].id = -1; - - i=0; - while (tbl[i].name) { - if (add_mib_entry(priv, &tbl[i]) < 0) { - printk("Add mib entry failed [%s]!\n", tbl[i].name); - return; - } - i++; - } - -// printk("used mib num = %d\n", priv->snmp_mib.tree_used_index); - -} - -int mib_get(struct rtl8192cd_priv *priv, char *oid, unsigned char *data, int *pLen) -{ - int iVal; - unsigned char bVal, *pVal, *pVal_type=data++; - struct mib_val *mib; - - mib = search_mib(priv, oid); - if (mib == NULL) { - printk("search mib failed [oid=%s]!\n", oid); - return 0; - } - - *pVal_type = VAL_OCTET; - - switch (mib->type) { - case MIB_TYPE_PRIV: - if (mib->size) - *pLen = mib->size; - else { - *pLen = strlen(((unsigned char *)priv->pmib)+mib->offset)+1; - *pVal_type = VAL_STR; - } - memcpy(data, ((unsigned char *)priv->pmib)+mib->offset, *pLen); - break; - - case MIB_TYPE_SNMP: - case MIB_TYPE_SNMP1: - if (mib->type == MIB_TYPE_SNMP1) { - bVal = *(((unsigned char *)&priv->snmp_mib)+mib->size); - *pLen = (int)bVal; - } - else if (mib->size > 0) - *pLen = mib->size; - else if (mib->size == 0) { - *pLen = strlen(((unsigned char *)&priv->snmp_mib)+mib->offset) + 1; - *pVal_type = VAL_STR; - } - memcpy(data, ((unsigned char *)&priv->snmp_mib)+mib->offset, *pLen); - break; - - case MIB_TYPE_VAL: - if (mib->size == 0) { - pVal = (unsigned char *)mib->offset; - *pLen = strlen(pVal) + 1; - memcpy(data, pVal, *pLen); - *pVal_type = VAL_STR; - } else if (mib->size == 1) { - bVal = (unsigned char)mib->offset; - pVal = &bVal; - *pLen = sizeof(bVal); - } - else { - iVal = mib->offset; - pVal = (unsigned char *)&iVal; - *pLen = sizeof(iVal); - } - memcpy(data, pVal, *pLen); - break; - - default: -// printk("Invalid mib type [%d, %s]\n", mib->type, mib->name); - *pVal_type = VAL_NULL; - *pLen = 0; - break; - } - -#if 0 - { - int i; - printk("name=%s, val_type=%d, len=%d", mib->name, *pVal_type, *pLen); - if (*pVal_type == VAL_STR) - printk(", val=%s\n", data); - else { - printk(", val="); - for (i=0; i<*pLen; i++) { - printk("%02x ", data[i]); - } - printk("\n"); - } - } -#endif - *pLen += 1; - return 1; -} - -// build tree and mapping mib value from priv to dot11 -void mib_init(struct rtl8192cd_priv *priv) -{ - int val; - - memset(&priv->snmp_mib, '\0', sizeof(struct mib_snmp)); - build_tree(priv); - - if ((OPMODE & WIFI_AP_STATE) || (OPMODE & WIFI_STATION_STATE)) - SNMP_MIB_ASSIGN(dot11DesiredBSSType, 1); // infra - else - SNMP_MIB_ASSIGN(dot11DesiredBSSType, 2); // ad-hoc - - if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm > 0) - SNMP_MIB_ASSIGN(dot11PrivacyInvoked, 1); - - if (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm == 1) // shared key - SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableShared, 1); - else - SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableOpen, 1); - - if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) { - SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 5); - SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 5); - SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 5); - SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 5); - SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 5); - } - else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) { - SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 13); - SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 13); - SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 13); - SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 13); - SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 13); - } - get_oper_rate(priv); - - switch(priv->pmib->dot11StationConfigEntry.dot11RegDomain) { - case DOMAIN_FCC: - val = 16; - break; - case DOMAIN_IC: - val = 32; - break; - case DOMAIN_ETSI: - val = 48; - break; - case DOMAIN_SPAIN: - val = 49; - break; - case DOMAIN_FRANCE: - val = 50; - break; - case DOMAIN_MKK: - case DOMAIN_MKK1: - case DOMAIN_MKK2: - case DOMAIN_MKK3: - val = 64; - break; - default: - printk("Invalid dot11RegDomain [%d]!\n", priv->pmib->dot11StationConfigEntry.dot11RegDomain); - val = 16; - break; - } - SNMP_MIB_ASSIGN(dot11CurrentRegDomain, val); - SNMP_MIB_ASSIGN(dot11CurrentTxAntenna, priv->pmib->dot11RFEntry.defaultAntennaB+1); -} -#endif // SUPPORT_SNMP_MIB - +/* + * SNMP MIB module + * + * $Id: 8192cd_mib.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define _8192CD_MIB_C_ + +#ifdef __KERNEL__ +#include +#elif defined(__ECOS) +#include +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" + +#ifdef SUPPORT_SNMP_MIB + +#if defined(__KERNEL__) || defined(__OSK__) +#include "./ieee802_mib.h" +#elif defined(__ECOS) +#include +#endif +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" +#include "./8192cd_mib.h" + +extern int _convert_2_pwr_dot(char *s, int base); +extern int _atoi(char *s, int base); + +struct mib_val dot11_mib_table[]={ + //dot11StationConfigTable + { {1, 1, 1, 1, 1, -1}, "dot11StationID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)}, + { {1, 1, 1, 2, 1, -1}, "dot11MediumOccupancyLimit ", MIB_TYPE_VAL, 100, 1}, + { {1, 1, 1, 3, 1, -1}, "dot11CFPollable", MIB_TYPE_VAL, 0, 1}, + { {1, 1, 1, 4, 1, -1}, "dot11CFPPeriod", MIB_TYPE_VAL, 0, 1}, + { {1, 1, 1, 5, 1, -1}, "dot11CFPMaxDuration", MIB_TYPE_VAL, 0, 1}, + { {1, 1, 1, 6, 1, -1}, "dot11AuthenticationResponseTimeOut", MIB_TYPE_VAL, REAUTH_TO*10, 4}, + { {1, 1, 1, 7, 1, -1}, "dot11PrivacyOptionImplemented", MIB_TYPE_VAL, 1, 1}, + { {1, 1, 1, 8, 1, -1}, "dot11PowerManagementMode", MIB_TYPE_VAL, 1, 1}, + { {1, 1, 1, 9, 1, -1}, "dot11DesiredSSID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DesiredSSID), 0}, + { {1, 1, 1, 10, 1, -1}, "dot11DesiredBSSType", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DesiredBSSType), SNMP_SIZE(dot11DesiredBSSType)}, + { {1, 1, 1, 11, 1, -1}, "dot11OperationalRateSet", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11OperationalRateSet), SNMP_OFFSET(dot11SupportedDataRatesNum)}, + { {1, 1, 1, 12, 1, -1}, "dot11BeaconPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11BeaconPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11BeaconPeriod)}, + { {1, 1, 1, 13, 1, -1}, "dot11DTIMPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DTIMPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11DTIMPeriod)}, + { {1, 1, 1, 14, 1, -1}, "dot11AssociationResponseTimeOut", MIB_TYPE_VAL, REASSOC_TO*10, 4}, + { {1, 1, 1, 15, 1, -1}, "dot11DisassociateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateReason), SNMP_SIZE(dot11DisassociateReason)}, + { {1, 1, 1, 16, 1, -1}, "dot11DisassociateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateStation), SNMP_SIZE(dot11DisassociateStation)}, + { {1, 1, 1, 17, 1, -1}, "dot11DeauthenticateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateReason), SNMP_SIZE(dot11DeauthenticateReason)}, + { {1, 1, 1, 18, 1, -1}, "dot11DeauthenticateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateStation), SNMP_SIZE(dot11DeauthenticateStation)}, + { {1, 1, 1, 19, 1, -1}, "dot11AuthenticateFailStatus", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStatus), SNMP_SIZE(dot11AuthenticateFailStatus)}, + { {1, 1, 1, 20, 1, -1}, "dot11AuthenticateFailStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStation), SNMP_SIZE(dot11AuthenticateFailStation)}, + { {1, 1, 1, 24, 1, -1}, "dot11RegDomain", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11RegDomain), PRIV_SIZE(dot11StationConfigEntry.dot11RegDomain)}, + { {1, 1, 1, 25, 1, -1}, "dot11DataRate", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DataRate), SNMP_SIZE(dot11DataRate)}, + { {1, 1, 1, 26, 1, -1}, "dot11ProtectionDisabled", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.protectionDisabled), PRIV_SIZE(dot11StationConfigEntry.protectionDisabled)}, + { {1, 1, 1, 27, 1, -1}, "dot11nSTBC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nSTBC), PRIV_SIZE(dot11nConfigEntry.dot11nSTBC)}, + { {1, 1, 1, 28, 1, -1}, "dot11nCoexist", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nCoexist), PRIV_SIZE(dot11nConfigEntry.dot11nCoexist)}, + { {1, 1, 1, 29, 1, -1}, "dot11nUse40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nUse40M), PRIV_SIZE(dot11nConfigEntry.dot11nUse40M)}, + { {1, 1, 1, 30, 1, -1}, "dot11n2ndChOffset", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11n2ndChOffset), PRIV_SIZE(dot11nConfigEntry.dot11n2ndChOffset)}, + { {1, 1, 1, 31, 1, -1}, "dot11nShortGIfor20M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor20M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor20M)}, + { {1, 1, 1, 32, 1, -1}, "dot11nShortGIfor40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor40M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor40M)}, + { {1, 1, 1, 33, 1, -1}, "dot11nAMPDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMPDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMPDU)}, + { {1, 1, 1, 34, 1, -1}, "dot11nAMSDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMSDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMSDU)}, + { {1, 1, 1, 35, 1, -1}, "dot11nLDPC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nLDPC), PRIV_SIZE(dot11nConfigEntry.dot11nLDPC)}, + //dot11AuthenticationAlgorithmsTable + { {1, 2, 1, 1, 1, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 1, 1}, + { {1, 2, 1, 2, 1, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 1, 1}, + { {1, 2, 1, 3, 1, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableOpen), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableOpen)}, + { {1, 2, 1, 1, 2, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 2, 1}, + { {1, 2, 1, 2, 2, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 2, 1}, + { {1, 2, 1, 3, 2, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableShared), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableShared)}, + + //dot11WEPDefaultKeysTable + { {1, 3, 1, 1, 1, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 1, 1}, + { {1, 3, 1, 2, 1, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey1), SNMP_SIZE(dot11WEPDefaultKeyLen)}, + { {1, 3, 1, 1, 2, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 2, 1}, + { {1, 3, 1, 2, 2, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey2), SNMP_SIZE(dot11WEPDefaultKeyLen)}, + { {1, 3, 1, 1, 3, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 3, 1}, + { {1, 3, 1, 2, 3, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey3), SNMP_SIZE(dot11WEPDefaultKeyLen)}, + { {1, 3, 1, 1, 4, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 4, 1}, + { {1, 3, 1, 2, 4, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey4), SNMP_SIZE(dot11WEPDefaultKeyLen)}, + + //dot11WEPKeyMappingsTable + { {1, 4, 1, 1, 1, -1}, "dot11WEPKeyMappingIndex", MIB_TYPE_VAL, 1, 1}, + { {1, 4, 1, 2, 1, -1}, "dot11WEPKeyMappingAddress", 0}, + { {1, 4, 1, 3, 1, -1}, "dot11WEPKeyMappingWEPOn", 0}, + { {1, 4, 1, 4, 1, -1}, "dot11WEPKeyMappingValue", 0}, + { {1, 4, 1, 5, 1, -1}, "dot11WEPKeyMappingStatus", 0}, + + //dot11PrivacyTable + { {1, 5, 1, 1, 1, -1}, "dot11PrivacyInvoked", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)}, + { {1, 5, 1, 2, 1, -1}, "dot11WEPDefaultKeyID", MIB_TYPE_PRIV, PRIV_OFFSET(dot1180211AuthEntry.dot11PrivacyKeyIndex), PRIV_SIZE(dot1180211AuthEntry.dot11PrivacyKeyIndex)}, + { {1, 5, 1, 3, 1, -1}, "dot11WEPKeyMappingLength", MIB_TYPE_VAL, 10, 1}, + { {1, 5, 1, 4, 1, -1}, "dot11ExcludeUnencrypted", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)}, + { {1, 5, 1, 5, 1, -1}, "dot11WEPICVErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPICVErrorCount), SNMP_SIZE(dot11WEPICVErrorCount)}, + { {1, 5, 1, 6, 1, -1}, "dot11WEPExcludedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPExcludedCount), SNMP_SIZE(dot11WEPExcludedCount)}, + + { {1, 8, 1, 1, 1, -1}, "dot11WPAKeyIndex", MIB_TYPE_VAL, 1, 1}, + { {1, 8, 1, 2, 1, -1}, "dot11WPAKeyFormat", MIB_TYPE_VAL, 1, 1}, + { {1, 8, 1, 3, 1, -1}, "dot11WPAKeyValue", MIB_TYPE_VAL, 1, 1}, + { {1, 9, 1, 1, 1, -1}, "dot11WPA2KeyIndex", MIB_TYPE_VAL, 1, 1}, + { {1, 9, 1, 2, 1, -1}, "dot11WPA2KeyFormat", MIB_TYPE_VAL, 1, 1}, + { {1, 9, 1, 3, 1, -1}, "dot11WPA2KeyValue", MIB_TYPE_VAL, 1, 1}, + { {1, 10, 1, 1, 1, -1}, "dot11RadiusServerIPAddress", MIB_TYPE_VAL, 1, 1}, + { {1, 10, 1, 2, 1, -1}, "dot11RadiusServerPort", MIB_TYPE_VAL, 1, 1}, + { {1, 10, 1, 3, 1, -1}, "dot11RadiusServerPassword", MIB_TYPE_VAL, 1, 1}, + { {1, 10, 1, 4, 1, -1}, "dot11RadiusServerEnable", MIB_TYPE_VAL, 1, 1}, + //dot11OperationTable + { {2, 1, 1, 1, 1, -1}, "dot11MACAddress", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)}, + { {2, 1, 1, 2, 1, -1}, "dot11RTSThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11RTSThreshold), PRIV_SIZE(dot11OperationEntry.dot11RTSThreshold)}, + { {2, 1, 1, 3, 1, -1}, "dot11ShortRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11ShortRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11ShortRetryLimit)}, + { {2, 1, 1, 4, 1, -1}, "dot11LongRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11LongRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11LongRetryLimit)}, + { {2, 1, 1, 5, 1, -1}, "dot11FragmentationThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11FragmentationThreshold), PRIV_SIZE(dot11OperationEntry.dot11FragmentationThreshold)}, + { {2, 1, 1, 6, 1, -1}, "dot11MaxTransmitMSDULifetime", MIB_TYPE_VAL, 512, 1}, + { {2, 1, 1, 7, 1, -1}, "dot11MaxReceiveLifetime", MIB_TYPE_VAL, FRAG_TO*10, 4}, + { {2, 1, 1, 8, 1, -1}, "dot11ManufacturerID", MIB_TYPE_VAL, (int)"Realtek", 0}, + { {2, 1, 1, 9, 1, -1}, "dot11ProductID", MIB_TYPE_VAL, (int)"RTL8185/RTL8186", 0}, + { {2, 1, 1, 10, 1, -1}, "dot11IappEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.iapp_enable), PRIV_SIZE(dot11OperationEntry.iapp_enable)}, + { {2, 1, 1, 11, 1, -1}, "dot11BlockRelay", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.block_relay), PRIV_SIZE(dot11OperationEntry.block_relay)}, + { {2, 1, 1, 12, 1, -1}, "dot11WIFISpecific", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.wifi_specific), PRIV_SIZE(dot11OperationEntry.wifi_specific)}, + { {2, 1, 1, 13, 1, -1}, "dot11QosEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11QosEntry.dot11QosEnable), PRIV_SIZE(dot11QosEntry.dot11QosEnable)}, + { {2, 1, 1, 14, 1, -1}, "dot11NetworkType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11BssType.net_work_type), PRIV_SIZE(dot11BssType.net_work_type)}, + { {2, 1, 1, 15, 1, -1}, "dot11LedType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.ledtype), PRIV_SIZE(dot11OperationEntry.ledtype)}, + { {2, 1, 1, 16, 1, -1}, "dot11OperationMode", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.opmode), PRIV_SIZE(dot11OperationEntry.opmode)}, + { {2, 1, 1, 17, 1, -1}, "dot11BroadCastSSID", MIB_TYPE_PRIV,PRIV_OFFSET(miscEntry.show_hidden_bss), PRIV_SIZE(miscEntry.show_hidden_bss)}, + { {2, 1, 1, 18, 1, -1}, "dot11GuestAccess", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.guest_access), PRIV_SIZE(dot11OperationEntry.guest_access)}, + + //dot11CountersTable + { {2, 2, 1, 1, 1, -1}, "dot11TransmittedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFragmentCount), SNMP_SIZE(dot11TransmittedFragmentCount)}, + { {2, 2, 1, 2, 1, -1}, "dot11MulticastTransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastTransmittedFrameCount), SNMP_SIZE(dot11MulticastTransmittedFrameCount)}, + { {2, 2, 1, 3, 1, -1}, "dot11FailedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FailedCount), SNMP_SIZE(dot11FailedCount)}, + { {2, 2, 1, 4, 1, -1}, "dot11RetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RetryCount), SNMP_SIZE(dot11RetryCount)}, + { {2, 2, 1, 5, 1, -1}, "dot11MultipleRetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MultipleRetryCount), SNMP_SIZE(dot11MultipleRetryCount)}, + { {2, 2, 1, 6, 1, -1}, "dot11FrameDuplicateCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FrameDuplicateCount), SNMP_SIZE(dot11FrameDuplicateCount)}, + { {2, 2, 1, 7, 1, -1}, "dot11RTSSuccessCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSSuccessCount), SNMP_SIZE(dot11RTSSuccessCount)}, + { {2, 2, 1, 8, 1, -1}, "dot11RTSFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSFailureCount), SNMP_SIZE(dot11RTSFailureCount)}, + { {2, 2, 1, 9, 1, -1}, "dot11ACKFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ACKFailureCount), SNMP_SIZE(dot11ACKFailureCount)}, + { {2, 2, 1, 10, 1, -1}, "dot11ReceivedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ReceivedFragmentCount), SNMP_SIZE(dot11ReceivedFragmentCount)}, + { {2, 2, 1, 11, 1, -1}, "dot11MulticastReceivedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastReceivedFrameCount), SNMP_SIZE(dot11MulticastReceivedFrameCount)}, + { {2, 2, 1, 12, 1, -1}, "dot11FCSErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FCSErrorCount), SNMP_SIZE(dot11FCSErrorCount)}, + { {2, 2, 1, 13, 1, -1}, "dot11TransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFrameCount), SNMP_SIZE(dot11TransmittedFrameCount)}, + { {2, 2, 1, 14, 1, -1}, "dot11WEPUndecryptableCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPUndecryptableCount), SNMP_SIZE(dot11WEPUndecryptableCount)}, + + //dot11GroupAddressesTable + { {2, 3, 1, 1, 1, -1}, "dot11GroupAddressesIndex", MIB_TYPE_VAL, 1, 1}, + { {2, 3, 1, 2, 1, -1}, "dot11Address", 0}, + { {2, 3, 1, 3, 1, -1}, "dot11GroupAddressesStatus", 0}, + + { {3, 1, 1, 0, -1}, "dot11ResourceTypeIDName", MIB_TYPE_VAL, (int)"8185", 0}, + + //dot11ResourceInfoTable + { {3, 1, 2, 1, 1, 1, -1}, "dot11manufacturerOUI", MIB_TYPE_VAL, (int)"\x00\xE0\x4C", 3}, + { {3, 1, 2, 1, 2, 1, -1}, "dot11manufacturerName", MIB_TYPE_VAL, (int)"Realtek", 0}, + { {3, 1, 2, 1, 3, 1, -1}, "dot11manufacturerProductName", MIB_TYPE_VAL, (int)"Wireless 802.11 b/g", 0}, + { {3, 1, 2, 1, 4, 1, -1}, "dot11manufacturerProductVersion", MIB_TYPE_VAL, (int)"v1.00", 0}, + + //dot11PhyOperationTable + { {4, 1, 1, 1, 1, -1}, "dot11PHYType", MIB_TYPE_VAL, 2, 1}, + { {4, 1, 1, 2, 1, -1}, "dot11CurrentRegDomain", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentRegDomain), SNMP_SIZE(dot11CurrentRegDomain)}, + { {4, 1, 1, 3, 1, -1}, "dot11TempType", MIB_TYPE_VAL, 1, 1}, + { {4, 1, 1, 4, 1, -1}, "dot11ShortPreamble",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.shortpreamble), PRIV_SIZE(dot11RFEntry.shortpreamble)}, + { {4, 1, 1, 5, 1, -1}, "dot11PhyBandSelect",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.phyBandSelect), PRIV_SIZE(dot11RFEntry.phyBandSelect)}, + { {4, 1, 1, 6, 1, -1}, "dot11TrSwitch",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.trswitch), PRIV_SIZE(dot11RFEntry.trswitch)}, + { {4, 1, 1, 7, 1, -1}, "dot11PowerScale", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PowerScale), SNMP_SIZE(dot11PowerScale)}, + + //dot11PhyAntennaTable + { {4, 2, 1, 1, 1, -1}, "dot11CurrentTxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)}, + { {4, 2, 1, 2, 1, -1}, "dot11DiversitySupport", MIB_TYPE_VAL, 2, 1}, + { {4, 2, 1, 3, 1, -1}, "dot11CurrentRxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)}, + + //dot11PhyTxPowerTable + { {4, 3, 1, 1, 1, -1}, "dot11NumberSupportedPowerLevels", MIB_TYPE_VAL, 4, 1}, + { {4, 3, 1, 2, 1, -1}, "dot11TxPowerLevel1", MIB_TYPE_VAL, 25, 1}, + { {4, 3, 1, 3, 1, -1}, "dot11TxPowerLevel2", MIB_TYPE_VAL, 12, 1}, + { {4, 3, 1, 4, 1, -1}, "dot11TxPowerLevel3", MIB_TYPE_VAL, 6, 1}, + { {4, 3, 1, 5, 1, -1}, "dot11TxPowerLevel4", MIB_TYPE_VAL, 3, 1}, + { {4, 3, 1, 6, 1, -1}, "dot11TxPowerLevel5", MIB_TYPE_VAL, 0, 1}, + { {4, 3, 1, 7, 1, -1}, "dot11TxPowerLevel6", MIB_TYPE_VAL, 0, 1}, + { {4, 3, 1, 8, 1, -1}, "dot11TxPowerLevel7", MIB_TYPE_VAL, 0, 1}, + { {4, 3, 1, 9, 1, -1}, "dot11TxPowerLevel8", MIB_TYPE_VAL, 0, 1}, + { {4, 3, 1, 10, 1, -1}, "dot11CurrentTxPowerLevel", 0}, // NCTU + + //dot11PhyDSSSTable + { {4, 5, 1, 1, 1, -1}, "dot11CurrentChannel", MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.dot11channel), PRIV_SIZE(dot11RFEntry.dot11channel)}, + { {4, 5, 1, 2, 1, -1}, "dot11CCAModeSupported", MIB_TYPE_VAL, 4, 1}, + { {4, 5, 1, 3, 1, -1}, "dot11CurrentCCAMode", MIB_TYPE_VAL, 4, 1}, + { {4, 5, 1, 4, 1, -1}, "dot11EDThreshold", MIB_TYPE_VAL, 0, 1}, + + //dot11RegDomainsSupportedTable + { {4, 7, 1, 1, 1, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 1, 1}, + { {4, 7, 1, 2, 1, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 16, 1}, + { {4, 7, 1, 1, 2, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 2, 1}, + { {4, 7, 1, 2, 2, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 32, 1}, + { {4, 7, 1, 1, 3, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 3, 1}, + { {4, 7, 1, 2, 3, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 48, 1}, + { {4, 7, 1, 1, 4, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 4, 1}, + { {4, 7, 1, 2, 4, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 49, 1}, + { {4, 7, 1, 1, 5, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 5, 1}, + { {4, 7, 1, 2, 5, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 50, 1}, + { {4, 7, 1, 1, 6, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 6, 1}, + { {4, 7, 1, 2, 6, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 64, 1}, + + //dot11AntennasListTable + { {4, 8, 1, 1, 1, -1}, "dot11AntennaListIndex", MIB_TYPE_VAL, 1, 1}, + { {4, 8, 1, 2, 1, -1}, "dot11SupportedTxAntenna", MIB_TYPE_VAL, 1, 1}, + { {4, 8, 1, 3, 1, -1}, "dot11SupportedRxAntenna", MIB_TYPE_VAL, 1, 1}, + { {4, 8, 1, 4, 1, -1}, "dot11DiversitySelectionRx", MIB_TYPE_VAL, 1, 1}, + + //dot11SupportedDataRatesTxTable + { {4, 9, 1, 1, 1, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 1, 1}, + { {4, 9, 1, 2, 1, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4}, + { {4, 9, 1, 1, 2, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 2, 1}, + { {4, 9, 1, 2, 2, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4}, + { {4, 9, 1, 1, 3, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 3, 1}, + { {4, 9, 1, 2, 3, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4}, + { {4, 9, 1, 1, 4, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 4, 1}, + { {4, 9, 1, 2, 4, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4}, + { {4, 9, 1, 1, 5, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 5, 1}, + { {4, 9, 1, 2, 5, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4}, + { {4, 9, 1, 1, 6, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 6, 1}, + { {4, 9, 1, 2, 6, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4}, + { {4, 9, 1, 1, 7, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 7, 1}, + { {4, 9, 1, 2, 7, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4}, + { {4, 9, 1, 1, 8, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 8, 1}, + { {4, 9, 1, 2, 8, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4}, + { {4, 9, 1, 1, 9, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 9, 1}, + { {4, 9, 1, 2, 9, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4}, + { {4, 9, 1, 1, 10, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 10, 1}, + { {4, 9, 1, 2, 10, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4}, + { {4, 9, 1, 1, 11, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 11, 1}, + { {4, 9, 1, 2, 11, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4}, + { {4, 9, 1, 1, 12, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 12, 1}, + { {4, 9, 1, 2, 12, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4}, + + //dot11SupportedDataRatesRxTable + { {4, 10, 1, 1, 1, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 1, 1}, + { {4, 10, 1, 2, 1, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4}, + { {4, 10, 1, 1, 2, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 2, 1}, + { {4, 10, 1, 2, 2, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4}, + { {4, 10, 1, 1, 3, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 3, 1}, + { {4, 10, 1, 2, 3, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4}, + { {4, 10, 1, 1, 4, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 4, 1}, + { {4, 10, 1, 2, 4, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4}, + { {4, 10, 1, 1, 5, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 5, 1}, + { {4, 10, 1, 2, 5, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4}, + { {4, 10, 1, 1, 6, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 6, 1}, + { {4, 10, 1, 2, 6, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4}, + { {4, 10, 1, 1, 7, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 7, 1}, + { {4, 10, 1, 2, 7, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4}, + { {4, 10, 1, 1, 8, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 8, 1}, + { {4, 10, 1, 2, 8, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4}, + { {4, 10, 1, 1, 9, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 9, 1}, + { {4, 10, 1, 2, 9, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4}, + { {4, 10, 1, 1, 10, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 10, 1}, + { {4, 10, 1, 2, 10, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4}, + { {4, 10, 1, 1, 11, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 11, 1}, + { {4, 10, 1, 2, 11, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4}, + { {4, 10, 1, 1, 12, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 12, 1}, + { {4, 10, 1, 2, 12, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4}, + + // Number of table entry, Realtek proprietary + { {6, 1, -1}, "dot11StationConfigEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 2, -1}, "dot11AuthenticationAlgorithmsEntryNum", MIB_TYPE_VAL, 2, 1}, + { {6, 3, -1}, "dot11WEPDefaultKeysEntryNum", MIB_TYPE_VAL, 4, 1}, + { {6, 4, -1}, "dot11WEPKeyMappingsEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 5, -1}, "dot11PrivacyEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 6, -1}, "dot11OperationEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 7, -1}, "dot11CountersEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 8, -1}, "dot11GroupAddressesEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 9, -1}, "dot11ResourceInfoTableNum", MIB_TYPE_VAL, 1, 1}, + { {6, 10, -1}, "dot11PhyOperationEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 11, -1}, "dot11PhyAntennaEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 12, -1}, "dot11PhyTxPowerEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 13, -1}, "dot11PhyDSSSEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 14, -1}, "dot11RegDomainsSupportEntryNum", MIB_TYPE_VAL, 6, 1}, + { {6, 15, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 16, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 17, -1}, "dot11SupportedDataRatesTxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)}, + { {6, 18, -1}, "dot11SupportedDataRatesRxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)}, + { {6, 19, -1}, "dot11MultiDomainCapabilityEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 20, -1}, "dot11WPAKeysEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 21, -1}, "dot11WPA2KeysEntryNum", MIB_TYPE_VAL, 1, 1}, + { {6, 22, -1}, "dot11RadiusServerNum", MIB_TYPE_VAL, 1, 1}, + + { {-1}, NULL, 0} +}; + + +static int add_mib_entry(struct rtl8192cd_priv *priv, struct mib_val *ent) +{ + int i=0, round = 0; + struct mib_entry **mib=&priv->snmp_mib.mib_tree, *pre_mib=NULL; + + while(1) { + if (ent->oid[i] == -1) + break; + if (*mib == NULL) { + if (priv->snmp_mib.tree_used_index == MAX_MIB_TREE_NUM) { + printk("Exceed max mib tree number\n"); + return -1; + } + *mib = &priv->snmp_mib.mib_list[priv->snmp_mib.tree_used_index++]; + } + + if ((*mib)->id == -1 || ent->oid[i] == (*mib)->id) { + if ((*mib)->id == -1) + (*mib)->id = ent->oid[i]; + i++; + pre_mib = *mib; + mib = &((*mib)->next_level); + } + else + mib = &((*mib)->next_node); + + if (++round > 10000) { + panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); + break; + } + } + + if (pre_mib == NULL) { + printk("build mib tree error, no parent mib found!\n"); + return -1; + } + if (pre_mib->val) { + printk("build mib tree error, mib value has been assigned!\n"); + return -1; + } + pre_mib->val = ent; + return 0; +} + +static void name2oid(char *name, int *oid) +{ + int i=0; + char *src=name, *ptr; + while (*src) { + ptr = strstr(src, "."); + if (ptr) + *ptr = '\0'; + oid[i++] = _atoi(src, 10); + + if (ptr==NULL) + break; + src = ++ptr; + } + oid[i] = -1; +} + +static struct mib_val *search_mib(struct rtl8192cd_priv *priv, char *id) +{ + int i=0; + struct mib_entry *mib=priv->snmp_mib.mib_tree, *pre_mib=NULL; + int oid[100]; + + name2oid(id, oid); + + while (oid[i] != -1) { + if (mib == NULL || mib->id == -1) + return NULL; + if (mib->id == oid[i]) { + pre_mib = mib; + mib = mib->next_level; + i++; + } + else { + pre_mib = NULL; + mib = mib->next_node; + } + } + + if (pre_mib && pre_mib->val) + return pre_mib->val; + else + return NULL; +} + +static void build_tree(struct rtl8192cd_priv *priv) +{ + int i=0; + struct mib_val *tbl = dot11_mib_table; + + for (i=0; isnmp_mib.mib_list[i].id = -1; + + i=0; + while (tbl[i].name) { + if (add_mib_entry(priv, &tbl[i]) < 0) { + printk("Add mib entry failed [%s]!\n", tbl[i].name); + return; + } + i++; + } + +// printk("used mib num = %d\n", priv->snmp_mib.tree_used_index); + +} + +int mib_get(struct rtl8192cd_priv *priv, char *oid, unsigned char *data, int *pLen) +{ + int iVal; + unsigned char bVal, *pVal, *pVal_type=data++; + struct mib_val *mib; + + mib = search_mib(priv, oid); + if (mib == NULL) { + printk("search mib failed [oid=%s]!\n", oid); + return 0; + } + + *pVal_type = VAL_OCTET; + + switch (mib->type) { + case MIB_TYPE_PRIV: + if (mib->size) + *pLen = mib->size; + else { + *pLen = strlen(((unsigned char *)priv->pmib)+mib->offset)+1; + *pVal_type = VAL_STR; + } + memcpy(data, ((unsigned char *)priv->pmib)+mib->offset, *pLen); + break; + + case MIB_TYPE_SNMP: + case MIB_TYPE_SNMP1: + if (mib->type == MIB_TYPE_SNMP1) { + bVal = *(((unsigned char *)&priv->snmp_mib)+mib->size); + *pLen = (int)bVal; + } + else if (mib->size > 0) + *pLen = mib->size; + else if (mib->size == 0) { + *pLen = strlen(((unsigned char *)&priv->snmp_mib)+mib->offset) + 1; + *pVal_type = VAL_STR; + } + memcpy(data, ((unsigned char *)&priv->snmp_mib)+mib->offset, *pLen); + break; + + case MIB_TYPE_VAL: + if (mib->size == 0) { + pVal = (unsigned char *)mib->offset; + *pLen = strlen(pVal) + 1; + memcpy(data, pVal, *pLen); + *pVal_type = VAL_STR; + } else if (mib->size == 1) { + bVal = (unsigned char)mib->offset; + pVal = &bVal; + *pLen = sizeof(bVal); + } + else { + iVal = mib->offset; + pVal = (unsigned char *)&iVal; + *pLen = sizeof(iVal); + } + memcpy(data, pVal, *pLen); + break; + + default: +// printk("Invalid mib type [%d, %s]\n", mib->type, mib->name); + *pVal_type = VAL_NULL; + *pLen = 0; + break; + } + +#if 0 + { + int i; + printk("name=%s, val_type=%d, len=%d", mib->name, *pVal_type, *pLen); + if (*pVal_type == VAL_STR) + printk(", val=%s\n", data); + else { + printk(", val="); + for (i=0; i<*pLen; i++) { + printk("%02x ", data[i]); + } + printk("\n"); + } + } +#endif + *pLen += 1; + return 1; +} + +// build tree and mapping mib value from priv to dot11 +void mib_init(struct rtl8192cd_priv *priv) +{ + int val; + + memset(&priv->snmp_mib, '\0', sizeof(struct mib_snmp)); + build_tree(priv); + + if ((OPMODE & WIFI_AP_STATE) || (OPMODE & WIFI_STATION_STATE)) + SNMP_MIB_ASSIGN(dot11DesiredBSSType, 1); // infra + else + SNMP_MIB_ASSIGN(dot11DesiredBSSType, 2); // ad-hoc + + if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm > 0) + SNMP_MIB_ASSIGN(dot11PrivacyInvoked, 1); + + if (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm == 1) // shared key + SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableShared, 1); + else + SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableOpen, 1); + + if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) { + SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 5); + SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 5); + SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 5); + SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 5); + SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 5); + } + else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) { + SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 13); + SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 13); + SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 13); + SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 13); + SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 13); + } + get_oper_rate(priv); + + switch(priv->pmib->dot11StationConfigEntry.dot11RegDomain) { + case DOMAIN_FCC: + val = 16; + break; + case DOMAIN_IC: + val = 32; + break; + case DOMAIN_ETSI: + val = 48; + break; + case DOMAIN_SPAIN: + val = 49; + break; + case DOMAIN_FRANCE: + val = 50; + break; + case DOMAIN_MKK: + case DOMAIN_MKK1: + case DOMAIN_MKK2: + case DOMAIN_MKK3: + val = 64; + break; + default: + printk("Invalid dot11RegDomain [%d]!\n", priv->pmib->dot11StationConfigEntry.dot11RegDomain); + val = 16; + break; + } + SNMP_MIB_ASSIGN(dot11CurrentRegDomain, val); + SNMP_MIB_ASSIGN(dot11CurrentTxAntenna, priv->pmib->dot11RFEntry.defaultAntennaB+1); +} +#endif // SUPPORT_SNMP_MIB + diff --git a/package/kernel/rtl8192cd/8192cd_mib.h b/package/kernel/rtl8192cd/8192cd_mib.h index 2b6c1726c9d..0b6893c1b43 100644 --- a/package/kernel/rtl8192cd/8192cd_mib.h +++ b/package/kernel/rtl8192cd/8192cd_mib.h @@ -1,87 +1,87 @@ -/* - * Header files of SNMP MIB module - * - * $Id: 8192cd_mib.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _8192CD_MIB_H_ -#define _8192CD_MIB_H_ - -#define MAX_MIB_TREE_NUM 580 -#define MAX_OID_LEVEL 10 - -#define PRIV_OFFSET(field) ((int)(long *)&(((struct wifi_mib *)0)->field)) -#define PRIV_SIZE(field) sizeof(((struct wifi_mib *)0)->field) -#define SNMP_OFFSET(field) ((int)(long *)&(((struct mib_snmp *)0)->field)) -#define SNMP_SIZE(field) sizeof(((struct mib_snmp *)0)->field) - -enum { MIB_TYPE_VAL=1, MIB_TYPE_PRIV, MIB_TYPE_SNMP, MIB_TYPE_SNMP1 }; -enum { VAL_OCTET, VAL_STR, VAL_NULL }; - -struct mib_entry { - int id; - struct mib_entry *next_level; - struct mib_entry *next_node; - struct mib_val *val; -}; - -struct mib_val { - int oid[MAX_OID_LEVEL]; - char *name; - int type; - int offset; - int size; -}; - -struct mib_snmp { - unsigned char dot11AuthenticationAlgorithmsEnableOpen; - unsigned char dot11AuthenticationAlgorithmsEnableShared; - unsigned char dot11WEPDefaultKey1[13]; - unsigned char dot11WEPDefaultKey2[13]; - unsigned char dot11WEPDefaultKey3[13]; - unsigned char dot11WEPDefaultKey4[13]; - unsigned char dot11WEPDefaultKeyLen; - unsigned char dot11SupportedDataRatesNum; - unsigned int dot11SupportedDataRatesSet[12]; - unsigned char dot11OperationalRateSet[12]; - int dot11DesiredBSSType; - int dot11DisassociateReason; - unsigned char dot11DisassociateStation[6]; - int dot11DeauthenticateReason; - unsigned char dot11DeauthenticateStation[6]; - int dot11AuthenticateFailStatus; - unsigned char dot11AuthenticateFailStation[6]; - int dot11PrivacyInvoked; - int dot11WEPICVErrorCount; - int dot11WEPExcludedCount; - int dot11TransmittedFragmentCount; - int dot11MulticastTransmittedFrameCount; - int dot11FailedCount; - int dot11RetryCount; - int dot11MultipleRetryCount; - int dot11FrameDuplicateCount; - int dot11RTSSuccessCount; - int dot11RTSFailureCount; - int dot11ACKFailureCount; - int dot11ReceivedFragmentCount; - int dot11MulticastReceivedFrameCount; - int dot11FCSErrorCount; - int dot11TransmittedFrameCount; - int dot11WEPUndecryptableCount; - int dot11CurrentRegDomain; - int dot11CurrentTxAntenna; - int dot11DataRate; - int dot11PowerScale; - - struct mib_entry mib_list[MAX_MIB_TREE_NUM]; - int tree_used_index; - struct mib_entry *mib_tree; -}; -#endif // _8192CD_MIB_H_ - +/* + * Header files of SNMP MIB module + * + * $Id: 8192cd_mib.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _8192CD_MIB_H_ +#define _8192CD_MIB_H_ + +#define MAX_MIB_TREE_NUM 580 +#define MAX_OID_LEVEL 10 + +#define PRIV_OFFSET(field) ((int)(long *)&(((struct wifi_mib *)0)->field)) +#define PRIV_SIZE(field) sizeof(((struct wifi_mib *)0)->field) +#define SNMP_OFFSET(field) ((int)(long *)&(((struct mib_snmp *)0)->field)) +#define SNMP_SIZE(field) sizeof(((struct mib_snmp *)0)->field) + +enum { MIB_TYPE_VAL=1, MIB_TYPE_PRIV, MIB_TYPE_SNMP, MIB_TYPE_SNMP1 }; +enum { VAL_OCTET, VAL_STR, VAL_NULL }; + +struct mib_entry { + int id; + struct mib_entry *next_level; + struct mib_entry *next_node; + struct mib_val *val; +}; + +struct mib_val { + int oid[MAX_OID_LEVEL]; + char *name; + int type; + int offset; + int size; +}; + +struct mib_snmp { + unsigned char dot11AuthenticationAlgorithmsEnableOpen; + unsigned char dot11AuthenticationAlgorithmsEnableShared; + unsigned char dot11WEPDefaultKey1[13]; + unsigned char dot11WEPDefaultKey2[13]; + unsigned char dot11WEPDefaultKey3[13]; + unsigned char dot11WEPDefaultKey4[13]; + unsigned char dot11WEPDefaultKeyLen; + unsigned char dot11SupportedDataRatesNum; + unsigned int dot11SupportedDataRatesSet[12]; + unsigned char dot11OperationalRateSet[12]; + int dot11DesiredBSSType; + int dot11DisassociateReason; + unsigned char dot11DisassociateStation[6]; + int dot11DeauthenticateReason; + unsigned char dot11DeauthenticateStation[6]; + int dot11AuthenticateFailStatus; + unsigned char dot11AuthenticateFailStation[6]; + int dot11PrivacyInvoked; + int dot11WEPICVErrorCount; + int dot11WEPExcludedCount; + int dot11TransmittedFragmentCount; + int dot11MulticastTransmittedFrameCount; + int dot11FailedCount; + int dot11RetryCount; + int dot11MultipleRetryCount; + int dot11FrameDuplicateCount; + int dot11RTSSuccessCount; + int dot11RTSFailureCount; + int dot11ACKFailureCount; + int dot11ReceivedFragmentCount; + int dot11MulticastReceivedFrameCount; + int dot11FCSErrorCount; + int dot11TransmittedFrameCount; + int dot11WEPUndecryptableCount; + int dot11CurrentRegDomain; + int dot11CurrentTxAntenna; + int dot11DataRate; + int dot11PowerScale; + + struct mib_entry mib_list[MAX_MIB_TREE_NUM]; + int tree_used_index; + struct mib_entry *mib_tree; +}; +#endif // _8192CD_MIB_H_ + diff --git a/package/kernel/rtl8192cd/8192cd_net80211.c b/package/kernel/rtl8192cd/8192cd_net80211.c index 0f7426af8a6..3778a4b7acb 100644 --- a/package/kernel/rtl8192cd/8192cd_net80211.c +++ b/package/kernel/rtl8192cd/8192cd_net80211.c @@ -1,2005 +1,2005 @@ -/* - * API-compatible handling routines - * - * - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifdef __KERNEL__ -#include -#include -#include -#include -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" - -#if defined(WIFI_HAPD) || defined(RTK_NL80211) - -#ifdef __LINUX_2_6__ -#include -#include -#endif - -#include "./8192cd_debug.h" -#include "./8192cd_headers.h" - -#include -#include -#include -#include -#include -#include - -#include "./8192cd_net80211.h" - - -//#define HAPD_DEBUG - -void void_printk(const char *fmt, ...) -{ - ; -} - -#ifdef HAPD_DEBUG -#define HAPD_MSG printk -#else -#define HAPD_MSG void_printk -#endif - - - -const char* ether_sprintf(const u_int8_t *mac) -{ - static char etherbuf[18]; /* XXX */ - snprintf(etherbuf, sizeof(etherbuf), "%02x:%02x:%02x:%02x:%02x:%02x", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - return etherbuf; -} - -static __inline__ void set_ttkeylen(struct Dot11EncryptKey *pEncryptKey, UINT8 len) -{ - pEncryptKey->dot11TTKeyLen = len; -} - - -static __inline__ void set_tmickeylen(struct Dot11EncryptKey *pEncryptKey, UINT8 len) -{ - pEncryptKey->dot11TMicKeyLen = len; -} - -static __inline__ void set_tkip_key_for_wpas(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) -{ - memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); - - memcpy(pEncryptKey->dot11TMicKey2.skey, src + 16, pEncryptKey->dot11TMicKeyLen); - memcpy(pEncryptKey->dot11TMicKey1.skey, src + 24, pEncryptKey->dot11TMicKeyLen); - - memcpy(src + 16, pEncryptKey->dot11TMicKey2.skey, pEncryptKey->dot11TMicKeyLen); - memcpy(src + 24, pEncryptKey->dot11TMicKey1.skey, pEncryptKey->dot11TMicKeyLen); - - pEncryptKey->dot11TXPN48.val48 = 0; -} - -static __inline__ void set_tkip_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) -{ - memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); - - memcpy(pEncryptKey->dot11TMicKey1.skey, src + 16, pEncryptKey->dot11TMicKeyLen); - - memcpy(pEncryptKey->dot11TMicKey2.skey, src + 24, pEncryptKey->dot11TMicKeyLen); - - pEncryptKey->dot11TXPN48.val48 = 0; -} - - -static __inline__ void set_aes_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) -{ - memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); - - memcpy(pEncryptKey->dot11TMicKey1.skey, src, pEncryptKey->dot11TMicKeyLen); -} - - -static __inline__ void set_wep40_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) -{ - memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); -} - - -static __inline__ void set_wep104_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) -{ - memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); -} - - -static int HAPD_Process_Set_Port(struct net_device *dev, unsigned char *MACAddr, int PortStatus) -{ - struct stat_info *pstat; - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct wifi_mib *pmib = priv->pmib; - - HAPD_MSG("HAPD_Process_Set_Port +++ sta: %02X%02X%02X%02X%02X%02X Status %X\n", - MACAddr[0],MACAddr[1],MACAddr[2], - MACAddr[3],MACAddr[4],MACAddr[5], - PortStatus); - - // if driver is not opened, return immediately, david - if (!netif_running(priv->dev)) - return (-1); - - pstat = get_stainfo(priv, MACAddr); - - if ((pstat == NULL) || (!(pstat->state & WIFI_ASOC_STATE))) - return (-1); - - if (PortStatus) - pstat->ieee8021x_ctrlport = PortStatus; - else - pstat->ieee8021x_ctrlport = pmib->dot118021xAuthEntry.dot118021xDefaultPort; - - HAPD_MSG("HAPD_Process_Set_Port ---\n"); - - return 0; -} - -#if defined(WIFI_WPAS) || defined(RTK_NL80211) - -int rtl_wpas_join(struct rtl8192cd_priv *priv, int bss_num) -{ - char tmpbuf[33]; - - if (!netif_running(priv->dev)) { - printk("WiFi driver is NOT open!!\n"); - return -1; - } else if (priv->ss_req_ongoing) { - printk("Site Survey is not finished yet!!\n"); - return -1; - } - -#if defined(RTK_NL80211) - memcpy((void *)&(priv->pmib->dot11Bss) , - (void *)&priv->site_survey->bss_target[bss_num] , sizeof(struct bss_desc)); -#else - memcpy((void *)&(priv->pmib->dot11Bss) , - (void *)&priv->site_survey->bss_backup[bss_num] , sizeof(struct bss_desc)); -#endif - -#ifdef WIFI_SIMPLE_CONFIG - //_Eric if (priv->pmib->wscEntry.wsc_enable && (priv->pmib->dot11Bss.bsstype&WIFI_WPS)) - if (priv->pmib->wscEntry.wsc_enable) - { - //priv->pmib->dot11Bss.bsstype &= ~WIFI_WPS; - priv->wps_issue_join_req = 1; - } - else -#endif - { - if (check_bss_encrypt(priv) == FAIL) - { - printk("Encryption mismatch!\n"); - return -1; - } - } - - if ((priv->pmib->dot11Bss.ssidlen == 0) || (priv->pmib->dot11Bss.ssid[0] == '\0')) - { - printk("Error !! Join to a hidden AP!\n"); - return -1; - } - -#ifdef UNIVERSAL_REPEATER - disable_vxd_ap(GET_VXD_PRIV(priv)); -#endif - - memcpy(tmpbuf, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); - tmpbuf[priv->pmib->dot11Bss.ssidlen] = '\0'; - - NDEBUG3("[%s %d]going to join bss: [%s]\n",__FUNCTION__,__LINE__, tmpbuf); - - memcpy(SSID2SCAN, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); - SSID2SCAN_LEN = priv->pmib->dot11Bss.ssidlen; - - SSID_LEN = SSID2SCAN_LEN; - memcpy(SSID, SSID2SCAN, SSID_LEN); - memset(BSSID, 0, MACADDRLEN); - -#ifdef INCLUDE_WPA_PSK //_Eric ?? - //if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) - //derivePSK(priv); -#endif - priv->join_req_ongoing = 1; - priv->authModeRetry = 0; - - //mod_timer(&priv->WPAS_timer, jiffies + 300); - -#ifdef RTK_NL80211 - if(priv->pmib->dot11Bss.channel >=36) - { - if(GET_CHIP_VER(priv)==VERSION_8812E || GET_CHIP_VER(priv)==VERSION_8881A || GET_CHIP_VER(priv)==VERSION_8814A) - priv->pmib->dot11BssType.net_work_type = WIRELESS_11A|WIRELESS_11N|WIRELESS_11AC; - else - priv->pmib->dot11BssType.net_work_type = WIRELESS_11A|WIRELESS_11N; - } - else - { - #ifdef P2P_SUPPORT - if(rtk_p2p_is_enabled(priv)) - priv->pmib->dot11BssType.net_work_type = WIRELESS_11G|WIRELESS_11N; // p2p mode no included 11B - else - #endif - priv->pmib->dot11BssType.net_work_type = WIRELESS_11B|WIRELESS_11G|WIRELESS_11N; - - } - - priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; - - extern int is_support_ac(struct rtl8192cd_priv *priv); - - if(is_support_ac(priv)) - priv->pmib->dot11nConfigEntry.dot11nShortGIfor80M = 1; - -#ifdef CONFIG_WLAN_HAL_8814AE - if(GET_CHIP_VER(priv) == VERSION_8814A) - priv->pmib->dot11nConfigEntry.dot11nAMSDU=2; -#endif -#endif - - start_clnt_join(priv); - - return 0; -} - -#endif - - -void rtl_net80311_authmode(struct net_device *dev, int authtype, int encmode, - int pskenable, int dot11802_1x) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - - HAPD_MSG("rtl_net80311_authmode +++\n"); - HAPD_MSG("authtype=%d, encmode=%d, pskenable=%d, dot11802_1x=%d \n", authtype, encmode, pskenable, dot11802_1x); - - priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = authtype; - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = encmode; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = pskenable; - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = dot11802_1x; -} - -int rtl_net80211_setparam(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - - int *i = (int *) extra; - int param = wrqu->mode; /* parameter id is 1st */ - int value = 0; /* NB: most values are TYPE_INT */ - int ret = 0; - - int authtype = priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm; - int encmode = priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm; - int pskenable = priv->pmib->dot1180211AuthEntry.dot11EnablePSK; - int dot11802_1x = priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm; - - memcpy(&value, wrqu->name+sizeof(value), sizeof(value)); - - HAPD_MSG("rtl_net80211_setparam +++\n"); - HAPD_MSG("rtl8192cd_net80211_ioctl, param = %d, value =%d\n", param, value); - - - switch (param) { - case IEEE80211_PARAM_TURBO: /* turbo mode */ - break; - case IEEE80211_PARAM_MODE: /* phy mode (11a, 11b, etc.) */ - break; - case IEEE80211_PARAM_AUTHMODE: /* authentication mode */ - switch (value) { - case IEEE80211_AUTH_NONE: - {//Disable - authtype = 0; - encmode = 0; - pskenable = 0; - dot11802_1x = 0; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - case IEEE80211_AUTH_OPEN: - {//WEP Open - authtype = 0; - //WEP encmode depends on key length - //encmode = 1; - pskenable = 0; - dot11802_1x = 0; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - case IEEE80211_AUTH_SHARED: - {//WEP Shared - authtype = 1; - //WEP encmode depends on key length - //encmode = 1; - pskenable = 0; - dot11802_1x = 0; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - case IEEE80211_AUTH_AUTO: - {//WEP Auto - authtype = 2; - //WEP encmode depends on key length - //encmode = 1; - pskenable = 0; - dot11802_1x = 0; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - case IEEE80211_AUTH_WPA: - {//WPA-PSK-AES - //_Eric ?? if there is no valid passphrase ?? - authtype = 2; - encmode = 2; - //_Eric pskmode (WPA 0,1,2) will be set by IEEE80211_PARAM_WPA - //pskenable = 1; - dot11802_1x = 1; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - case IEEE80211_AUTH_8021X: - { - //8021x encmode depends on key length - if((encmode == _WEP_40_PRIVACY_) || (encmode == _WEP_104_PRIVACY_)) - authtype = 2; - else - authtype = 0; - - pskenable = 0; - dot11802_1x = 1; - rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); - break; - } - default: - return -EINVAL; - } - case IEEE80211_PARAM_PROTMODE: /* 802.11g protection */ - break; - case IEEE80211_PARAM_MCASTCIPHER: /* multicast/default cipher */ - break; - case IEEE80211_PARAM_MCASTKEYLEN: /* multicast key length */ - break; - case IEEE80211_PARAM_UCASTCIPHERS: /* unicast cipher suites */ - /* 1. Only support AES & TKIP for WPA1&WPA2 - 2. Set both wpa_cipher and wpa2_cipher, because IEEE80211_PARAM_WPA will clear unused cipher mode */ - HAPD_MSG("IEEE80211_PARAM_UCASTCIPHERS\n"); - - if(value & (1<pmib->dot11BssType.net_work_type & WIRELESS_11N)) || (OPMODE & WIFI_STATION_STATE)) - { - priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(1); - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= BIT(1); - } - else - return -EINVAL; - } - else - { - priv->pmib->dot1180211AuthEntry.dot11WPACipher &= ~(BIT(1)); - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher &= ~(BIT(1)); - } - - - if(value & (1<pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(3); - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= BIT(3); - } - else - { - priv->pmib->dot1180211AuthEntry.dot11WPACipher &= ~(BIT(3)); - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher &= ~(BIT(3)); - } - - priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; - - return 0; //_Eric if value > BIT(8) ? - - case IEEE80211_PARAM_UCASTCIPHER: /* unicast cipher */ - break; - case IEEE80211_PARAM_UCASTKEYLEN: /* unicast key length */ - if(value == 5) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; - else if(value == 13) - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; - else - priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; - break; - case IEEE80211_PARAM_WPA: /* WPA mode (0,1,2) */ - HAPD_MSG("IEEE80211_PARAM_WPA\n"); - if((value & BIT(0)) && (value & BIT(1))) - return 0; - else if((value & BIT(0))) - {//only WPA1, so clear mib of wpa2_cipher & wpa2_psk - priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK & ~(BIT(1)); - return 0; - } - else if((value & BIT(1))) - {//only WPA2, so clear mib of wpa_cipher & wps2_psk - priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; - priv->pmib->dot1180211AuthEntry.dot11EnablePSK & ~(BIT(0)); - return 0; - } - - case IEEE80211_PARAM_ROAMING: /* roaming mode */ -#ifdef WIFI_WPAS - if(value == IEEE80211_ROAMING_DEVICE) - priv->pmib->dot11StationConfigEntry.fastRoaming = 1; - else if(value == IEEE80211_ROAMING_MANUAL) - priv->pmib->dot11StationConfigEntry.fastRoaming = 0; - else - return -EINVAL; -#endif - break; - case IEEE80211_PARAM_PRIVACY: /* privacy invoked */ - ret =0; //It seems useless, just return status OK for hostapd. - break; - case IEEE80211_PARAM_COUNTERMEASURES: /* WPA/TKIP countermeasures */ - //_Eric ?? realtek do not have to support ?? - break; - case IEEE80211_PARAM_DROPUNENCRYPTED: /* discard unencrypted frames */ - break; - case IEEE80211_PARAM_DRIVER_CAPS: /* driver capabilities */ - break; - case IEEE80211_PARAM_MACCMD: /* MAC ACL operation */ - break; - case IEEE80211_PARAM_WMM: /* WMM mode (on, off) */ - break; - case IEEE80211_PARAM_HIDESSID: /* hide SSID mode (on, off) */ - break; - case IEEE80211_PARAM_APBRIDGE: /* AP inter-sta bridging */ - break; - case IEEE80211_PARAM_KEYMGTALGS: /* key management algorithms */ - HAPD_MSG("IEEE80211_PARAM_KEYMGTALGS\n"); - if((0<=value) && (value<=3)) - { - priv->pmib->dot1180211AuthEntry.dot11EnablePSK = value; - break; - } - else - return -EINVAL; - case IEEE80211_PARAM_RSNCAPS: /* RSN capabilities */ - break; - case IEEE80211_PARAM_INACT: /* station inactivity timeout */ - break; - case IEEE80211_PARAM_INACT_AUTH: /* station auth inact timeout */ - break; - case IEEE80211_PARAM_INACT_INIT: /* station init inact timeout */ - break; - case IEEE80211_PARAM_ABOLT: /* Atheros Adv. Capabilities */ - break; - case IEEE80211_PARAM_DTIM_PERIOD: /* DTIM period (beacons) */ - break; - case IEEE80211_PARAM_BEACON_INTERVAL: /* beacon interval (ms) */ - break; - case IEEE80211_PARAM_DOTH: /* 11.h is on/off */ - break; - case IEEE80211_PARAM_PWRTARGET: /* Current Channel Pwr Constraint */ - break; - case IEEE80211_PARAM_GENREASSOC: /* Generate a reassociation request */ - break; - case IEEE80211_PARAM_COMPRESSION: /* compression */ - break; - case IEEE80211_PARAM_FF: /* fast frames support */ - break; - case IEEE80211_PARAM_XR: /* XR support */ - break; - case IEEE80211_PARAM_BURST: /* burst mode */ - break; - case IEEE80211_PARAM_PUREG: /* pure 11g (no 11b stations) */ - break; - case IEEE80211_PARAM_AR: /* AR support */ - break; - case IEEE80211_PARAM_WDS: /* Enable 4 address processing */ - break; - case IEEE80211_PARAM_BGSCAN: /* bg scanning (on, off) */ - break; - case IEEE80211_PARAM_BGSCAN_IDLE: /* bg scan idle threshold */ - break; - case IEEE80211_PARAM_BGSCAN_INTERVAL: /* bg scan interval */ - break; - case IEEE80211_PARAM_MCAST_RATE: /* Multicast Tx Rate */ - break; - case IEEE80211_PARAM_COVERAGE_CLASS: /* coverage class */ - break; - case IEEE80211_PARAM_COUNTRY_IE: /* enable country IE */ - break; - case IEEE80211_PARAM_SCANVALID: /* scan cache valid threshold */ - break; - case IEEE80211_PARAM_ROAM_RSSI_11A: /* rssi threshold in 11a */ - break; - case IEEE80211_PARAM_ROAM_RSSI_11B: /* rssi threshold in 11b */ - break; - case IEEE80211_PARAM_ROAM_RSSI_11G: /* rssi threshold in 11g */ - break; - case IEEE80211_PARAM_ROAM_RATE_11A: /* tx rate threshold in 11a */ - break; - case IEEE80211_PARAM_ROAM_RATE_11B: /* tx rate threshold in 11b */ - break; - case IEEE80211_PARAM_ROAM_RATE_11G: /* tx rate threshold in 11g */ - break; - case IEEE80211_PARAM_UAPSDINFO: /* value for qos info field */ - break; - case IEEE80211_PARAM_SLEEP: /* force sleep/wake */ - break; - case IEEE80211_PARAM_QOSNULL: /* force sleep/wake */ - break; - case IEEE80211_PARAM_PSPOLL: /* force ps-poll generation (sta only) */ - break; - case IEEE80211_PARAM_EOSPDROP: /* force uapsd EOSP drop (ap only) */ - break; - case IEEE80211_PARAM_MARKDFS: /* mark a dfs interference channel when found */ - break; - case IEEE80211_PARAM_REGCLASS: /* enable regclass ids in country IE */ - break; - case IEEE80211_PARAM_DROPUNENC_EAPOL: /* drop unencrypted eapol frames */ - break; - case IEEE80211_PARAM_SHPREAMBLE: /* Short Preamble */ - break; - - } - - HAPD_MSG("rtl_net80211_setparam ---\n"); - return ret; - -} - -/* -Management frame type to which application IE is added -enum { - IEEE80211_APPIE_FRAME_BEACON = 0, - IEEE80211_APPIE_FRAME_PROBE_REQ = 1, - IEEE80211_APPIE_FRAME_PROBE_RESP = 2, - IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, - IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, - IEEE80211_APPIE_NUM_OF_FRAME = 5 -}; -*/ - -int rtl_net80211_setappiebuf(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct ieee80211req_getset_appiebuf * ie = (struct ieee80211req_getset_appiebuf *)wrqu->data.pointer; - int ret = 0; - - HAPD_MSG("rtl_net80211_setappiebuf +++\n"); - HAPD_MSG("frametype =%d, iebuflen=%d \n", ie->app_frmtype, ie->app_buflen); - - //_Eric ???? hostapd has no interface to set wsc_enable. - - if((ie->app_buflen == 0) && (ie->app_frmtype != IEEE80211_APPIE_FRAME_ASSOC_RESP)) - priv->pmib->wscEntry.wsc_enable = 0; - else if(ie->app_buflen <= 256) - priv->pmib->wscEntry.wsc_enable = 2; //Work as AP - else - return -EINVAL; - - if (ie->app_frmtype == IEEE80211_APPIE_FRAME_BEACON) { - HAPD_MSG("WSC: set beacon IE\n"); - priv->pmib->wscEntry.beacon_ielen = ie->app_buflen; - memcpy((void *)priv->pmib->wscEntry.beacon_ie, ie->app_buf, ie->app_buflen); - } - else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_PROBE_RESP) { - HAPD_MSG("WSC: set probe response IE\n"); - priv->pmib->wscEntry.probe_rsp_ielen = ie->app_buflen; - memcpy((void *)priv->pmib->wscEntry.probe_rsp_ie, ie->app_buf, ie->app_buflen); - } - else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_ASSOC_RESP) { - HAPD_MSG("WSC: set association response IE\n"); - priv->pmib->wscEntry.assoc_ielen = ie->app_buflen; - memcpy((void *)priv->pmib->wscEntry.assoc_ie, ie->app_buf, ie->app_buflen); - } -#ifdef WIFI_WPAS - else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_PROBE_REQ) { - HAPD_MSG("WSC: set probe request IE\n"); - priv->pmib->wscEntry.probe_req_ielen = ie->app_buflen; - memcpy((void *)priv->pmib->wscEntry.probe_req_ie, ie->app_buf, ie->app_buflen); - } -#endif - else - return -EINVAL; - - - HAPD_MSG("rtl_net80211_setappiebuf ---\n"); - return ret; - -} - - -#ifdef WIFI_WPAS - -int rtl_net80211_setoptie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - WPAS_ASSOCIATION_INFO Assoc_Info; - -//Check if WPS IE - UINT8 WSC_IE_OUI[4] = {0x00, 0x50, 0xf2, 0x04}; - int x; - unsigned char *ie = (unsigned char *)wrqu->data.pointer; - - if( ie[0] == _WPS_IE_) - if (!memcmp(ie+2, WSC_IE_OUI, 4)) - { - priv->pmib->wscEntry.assoc_ielen = wrqu->data.length; - memcpy((void *)priv->pmib->wscEntry.assoc_ie, wrqu->data.pointer, wrqu->data.length); - priv->pmib->wscEntry.wsc_enable = 1; - - return 0; - } - - priv->pmib->wscEntry.wsc_enable = 0; - - memset(priv->pmib->dot11RsnIE.rsnie, 0x0, 128); - memcpy(priv->pmib->dot11RsnIE.rsnie, wrqu->data.pointer, wrqu->data.length); - priv->pmib->dot11RsnIE.rsnielen = wrqu->data.length; - - memset((void *)&Assoc_Info, 0, sizeof(struct _WPAS_ASSOCIATION_INFO)); - Assoc_Info.ReqIELen = priv->pmib->dot11RsnIE.rsnie[1]+ 2; - memcpy(Assoc_Info.ReqIE, priv->pmib->dot11RsnIE.rsnie, Assoc_Info.ReqIELen); - //event_indicate_wpas(priv, NULL, WPAS_ASSOC_INFO, (UINT8 *)&Assoc_Info); - - return 0; - -} - -#endif - -int rtl_net80211_setmlme(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct ieee80211req_mlme *mlme = (struct ieee80211req_key *)wrqu->data.pointer; - struct stat_info *pstat = get_stainfo(priv, mlme->im_macaddr); - - int ret = 0; - - HAPD_MSG("rtl_net80211_setmlme +++\n"); - HAPD_MSG("auth_state =%d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" - , mlme->im_op, mlme->im_macaddr[0], mlme->im_macaddr[1], mlme->im_macaddr[2], - mlme->im_macaddr[3], mlme->im_macaddr[4], mlme->im_macaddr[5]); - - //_Eric ???? - - if(mlme->im_op == IEEE80211_MLME_AUTHORIZE) - { - - if (pstat == NULL){ - pstat = alloc_stainfo(priv, mlme->im_macaddr, -1); - if (pstat == NULL) { - printk("Exceed the upper limit of supported clients...\n"); - return -1; - } - init_stainfo(priv, pstat); - pstat->state |= (WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE); - pstat->expire_to = priv->assoc_to; - asoc_list_add(priv, pstat); - } - - HAPD_Process_Set_Port(dev, mlme->im_macaddr ,DOT11_PortStatus_Authorized); - - } - else if(mlme->im_op == IEEE80211_MLME_UNAUTHORIZE) - { - if (pstat == NULL) - return -EINVAL; - - //pstat->state |= WIFI_AUTH_NULL; - - HAPD_Process_Set_Port(dev, mlme->im_macaddr ,DOT11_PortStatus_Unauthorized); - - } - else if(mlme->im_op == IEEE80211_MLME_DISASSOC) - { - if (pstat == NULL) - return -EINVAL; - -#ifdef WIFI_WPAS - - if(OPMODE & WIFI_STATION_STATE) - { - HAPD_MSG("An AP is disconnected by WPAS \n"); - issue_disassoc(priv, mlme->im_macaddr, _RSON_UNSPECIFIED_); - - if (pstat->expire_to > 0) - { - cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); - check_sta_characteristic(priv, pstat, DECREASE); - } - - free_stainfo(priv, pstat); - memset(&priv->pmib->dot11Bss, 0, sizeof(struct bss_desc)); - memset(priv->pmib->dot11StationConfigEntry.dot11Bssid, 0, MACADDRLEN); - memset(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); - priv->pmib->dot11StationConfigEntry.dot11DesiredSSIDLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11DefaultSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); - priv->pmib->dot11StationConfigEntry.dot11DefaultSSIDLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan)); - priv->pmib->dot11StationConfigEntry.dot11SSIDtoScanLen = 0; - memset(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid, 0, 6); - - priv->wpas_manual_assoc = 1; //_Eric ?? when to let driver auto-connect ?? - - priv->join_res = STATE_Sta_No_Bss; - //pstat->state &= (~WIFI_ASOC_STATE); - return ret; - } - -#endif - - if (asoc_list_del(priv, pstat)) - { - if (pstat->expire_to > 0) - { - cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); - check_sta_characteristic(priv, pstat, DECREASE); - } - } - - // Need change state back to autehnticated - release_stainfo(priv, pstat); - init_stainfo(priv, pstat); - pstat->state |= WIFI_AUTH_SUCCESS; - pstat->expire_to = priv->assoc_to; - auth_list_add(priv, pstat); - } - else if(mlme->im_op == IEEE80211_MLME_DEAUTH) - { - unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; - - if(!memcmp(mlme->im_macaddr, MULTICAST_ADD, 6)) //_Eric ??How to free all stainfo?? - return 0; - - if (pstat == NULL) - return -EINVAL; - - if (asoc_list_del(priv, pstat)) - { - if (pstat->expire_to > 0) - { - cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); - check_sta_characteristic(priv, pstat, DECREASE); - } - } - - //release_stainfo(priv, pstat); - free_stainfo(priv, pstat); - - } -#ifdef WIFI_WPAS - else if(mlme->im_op == IEEE80211_MLME_ASSOC) - { - int ix = 0, found = 0; - - if((OPMODE & WIFI_STATION_STATE) == 0) - { - HAPD_MSG("NOT in Client Mode, can NOT Associate !!!\n"); - return -1; - } - - for(ix = 0 ; ix < priv->site_survey->count_backup ; ix++) //_Eric ?? will bss_backup be cleaned?? -> Not found in codes - { - if(!memcmp(priv->site_survey->bss_backup[ix].bssid , mlme->im_macaddr, 6)) - { - found = 1; - break; - } - } - - if(found == 0) - { - printk("BSSID NOT Found !!\n"); - return -EINVAL; - } - else - ret = rtl_wpas_join(priv, ix); - - if(ret != 0) - printk("rtl_wpas_join Failed !!\n"); - - } -#endif - else - { - HAPD_MSG("unknown auth_state !!!\n"); - return -EINVAL; - } - - HAPD_MSG("rtl_net80211_setmlme ---\n"); - return ret; - - -} - - -int rtl_net80211_setkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct ieee80211req_key *wk = (struct ieee80211req_key *)wrqu->data.pointer; - struct wifi_mib *pmib = priv->pmib; - struct Dot11EncryptKey *pEncryptKey = NULL; - struct stat_info *pstat = NULL; - unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; -#ifdef WIFI_WPAS - unsigned char GROUP_ADD[6]={0x0,0x0,0x0,0x0,0x0,0x0}; -#endif - int cipher =0; - int retVal = 0; - int group_key = 0; - - HAPD_MSG("rtl_net80211_setkey +++\n"); - - - HAPD_MSG("keyid = %d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" - , wk->ik_keyix, wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], - wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5]); - HAPD_MSG("type = 0x%x, flags = 0x%x, keylen = 0x%x \n" - , wk->ik_type, wk->ik_flags, wk->ik_keylen); - - - //check if the interface is down - if (!netif_running(priv->dev)) - { - if(wk->ik_type == IEEE80211_CIPHER_WEP) - { - HAPD_MSG("set WEP Key in driver DOWN\n"); - memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); - return 0; - } - - HAPD_MSG("\nFail: interface not opened\n"); - return 0; - } - - if(!memcmp(wk->ik_macaddr, MULTICAST_ADD, 6)) - group_key = 1; - -#ifdef WIFI_WPAS //_Eric ?? if oxff not group addr in wpas ?? - if(OPMODE & WIFI_STATION_STATE) - if(!memcmp(wk->ik_macaddr, GROUP_ADD, 6)) - group_key = 1; -#endif - - if(wk->ik_type == IEEE80211_CIPHER_WEP) - { - -#ifdef WIFI_WPAS - if(OPMODE & WIFI_STATION_STATE) - if(priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm == 0) - { - memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); - return 0; - } -#endif -#ifdef RTK_NL80211 - HAPD_MSG("set WEP Key for NL80211\n"); - memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); -#endif - if(priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) - cipher = (DOT11_ENC_WEP40); - else if(priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) - cipher = (DOT11_ENC_WEP104); - else - return -EINVAL; - } - else if(wk->ik_type == IEEE80211_CIPHER_TKIP) - cipher = (DOT11_ENC_TKIP); - else if(wk->ik_type == IEEE80211_CIPHER_AES_CCM) - cipher = (DOT11_ENC_CCMP); - else - { - HAPD_MSG("unknown encAlg !!!\n"); - return -EINVAL; - } - - //_Eric ?? if call DOT11_Process_Set_Key - //CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, cipher, 0, wk->ik_keydata); - - if(group_key) - { - int set_gkey_to_cam = 0; - HAPD_MSG("set group key !!\n"); - -#ifdef UNIVERSAL_REPEATER - if (IS_VXD_INTERFACE(priv)) - set_gkey_to_cam = 0; - else { - if (IS_ROOT_INTERFACE(priv)) { - if (IS_DRV_OPEN(GET_VXD_PRIV(priv))) - set_gkey_to_cam = 0; - } - } -#endif - -#ifdef MBSSID - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable) - { - // No matter root or vap, don't set key to cam if vap is enabled. - set_gkey_to_cam = 0; - } -#endif - -#ifdef CONFIG_RTK_MESH - //modify by Joule for SECURITY - if (dev == priv->mesh_dev) - { - pmib->dot11sKeysTable.dot11Privacy = cipher; - pEncryptKey = &pmib->dot11sKeysTable.dot11EncryptKey; - pmib->dot11sKeysTable.keyid = (UINT)wk->ik_keyix; - } - else -#endif - { - pmib->dot11GroupKeysTable.dot11Privacy = cipher; - pmib->dot11GroupKeysTable.keyid = (UINT)wk->ik_keyix; - - if (wk->ik_keyix == GKEY_ID_SECOND) - pEncryptKey = &pmib->dot11GroupKeysTable.dot11EncryptKey2; - else - pEncryptKey = &pmib->dot11GroupKeysTable.dot11EncryptKey; - } - - switch(cipher) - { - case DOT11_ENC_TKIP: - set_ttkeylen(pEncryptKey, 16); - set_tmickeylen(pEncryptKey, 8); -#ifdef RTK_NL80211 - if(OPMODE & WIFI_STATION_STATE) - set_tkip_key_for_wpas(pEncryptKey, wk->ik_keydata); - else -#endif - set_tkip_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set TKIP group key! id %X\n", (UINT)wk->ik_keyix); - if (!SWCRYPTO) { - if (set_gkey_to_cam) - { - retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - pmib->dot11GroupKeysTable.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_TKIP<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - pmib->dot11GroupKeysTable.keyInCam = TRUE; - } - } - } - break; - - case DOT11_ENC_WEP40: - set_ttkeylen(pEncryptKey, 5); - set_tmickeylen(pEncryptKey, 0); - set_wep40_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set WEP40 group key!\n"); - if (!SWCRYPTO) { - if (set_gkey_to_cam) - { - retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - pmib->dot11GroupKeysTable.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_WEP40<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - pmib->dot11GroupKeysTable.keyInCam = TRUE; - } - } - } - break; - - case DOT11_ENC_WEP104: - set_ttkeylen(pEncryptKey, 13); - set_tmickeylen(pEncryptKey, 0); - set_wep104_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set WEP104 group key!\n"); - if (!SWCRYPTO) { - if (set_gkey_to_cam) - { - retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - pmib->dot11GroupKeysTable.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_WEP104<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - pmib->dot11GroupKeysTable.keyInCam = TRUE; - } - } - } - break; - - case DOT11_ENC_CCMP: - set_ttkeylen(pEncryptKey, 16); - set_tmickeylen(pEncryptKey, 16); - set_aes_key(pEncryptKey, wk->ik_keydata); - pEncryptKey->dot11RXPN48.val48 = 0; - - HAPD_MSG("going to set CCMP-AES group key!\n"); -#ifdef CONFIG_RTK_MESH - if (dev == priv->mesh_dev) - pmib->dot11sKeysTable.keyInCam = TRUE; // keyInCam means key in driver - else -#endif - if (!SWCRYPTO) { - if (set_gkey_to_cam) - { - retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - pmib->dot11GroupKeysTable.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_CCMP<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - pmib->dot11GroupKeysTable.keyInCam = TRUE; - } - } - } - break; - - case DOT11_ENC_NONE: - default: - HAPD_MSG("No group encryption key is set!\n"); - set_ttkeylen(pEncryptKey, 0); - set_tmickeylen(pEncryptKey, 0); - break; - } - } - else - { - pstat = get_stainfo(priv, wk->ik_macaddr); - if (pstat == NULL) { - DEBUG_ERR("Set key failed, invalid mac address: %02x%02x%02x%02x%02x%02x\n", - wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], wk->ik_macaddr[3], - wk->ik_macaddr[4], wk->ik_macaddr[5]); - return (-1); - } - - pstat->dot11KeyMapping.dot11Privacy = cipher; - pEncryptKey = &pstat->dot11KeyMapping.dot11EncryptKey; - pstat->keyid = wk->ik_keyix; - -#if defined(__DRAYTEK_OS__) && defined(WDS) - if (pstat->state & WIFI_WDS) - priv->pmib->dot11WdsInfo.wdsPrivacy = cipher; -#endif - -#ifdef RTK_NL80211 //eric-ath - //printk(" +++ pstat->state=0x%x wps_join=%d \n", pstat->state, (pstat->state & WIFI_WPS_JOIN)); - - if(OPMODE & WIFI_STATION_STATE) - if(pstat->state & WIFI_WPS_JOIN) - { - //printk("REMOVE WIFI_WPS_JOIN State !!\n"); - pstat->state &= (~(WIFI_WPS_JOIN)); - } -#endif - - switch(cipher) - { - case DOT11_ENC_TKIP: - set_ttkeylen(pEncryptKey, 16); - set_tmickeylen(pEncryptKey, 8); - -#ifdef RTK_NL80211 - if(OPMODE & WIFI_STATION_STATE) - set_tkip_key_for_wpas(pEncryptKey, wk->ik_keydata); - else -#endif - set_tkip_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set TKIP Unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", - wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], - wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); - if (!SWCRYPTO) { - retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_TKIP<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; - } - else { - if (pstat->aggre_mthd != AGGRE_MTHD_NONE) - pstat->aggre_mthd = AGGRE_MTHD_NONE; - } - } - break; - - case DOT11_ENC_WEP40: - set_ttkeylen(pEncryptKey, 5); - set_tmickeylen(pEncryptKey, 0); - set_wep40_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set WEP40 unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", - wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], - wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); - if (!SWCRYPTO) { - retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_WEP40<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; - } - else { - if (pstat->aggre_mthd != AGGRE_MTHD_NONE) - pstat->aggre_mthd = AGGRE_MTHD_NONE; - } - } - break; - - case DOT11_ENC_WEP104: - set_ttkeylen(pEncryptKey, 13); - set_tmickeylen(pEncryptKey, 0); - set_wep104_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set WEP104 unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", - wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], - wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); - if (!SWCRYPTO) { - retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_WEP104<<2, 0, wk->ik_keydata); - if (retVal) { - priv->pshare->CamEntryOccupied++; - if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; - } - else { - if (pstat->aggre_mthd != AGGRE_MTHD_NONE) - pstat->aggre_mthd = AGGRE_MTHD_NONE; - } - } - break; - - case DOT11_ENC_CCMP: - set_ttkeylen(pEncryptKey, 16); - set_tmickeylen(pEncryptKey, 16); - set_aes_key(pEncryptKey, wk->ik_keydata); - - HAPD_MSG("going to set CCMP-AES unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", - wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], - wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); - if (!SWCRYPTO) { - retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); - if (retVal) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_CCMP<<2, 0, wk->ik_keydata); - if (retVal) { - HAPD_MSG("CamAddOneEntry of CCMP OK\n"); - priv->pshare->CamEntryOccupied++; - if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; - assign_aggre_mthod(priv, pstat); - } - else { - HAPD_MSG("CamAddOneEntry of CCMP FAIL\n"); - if (pstat->aggre_mthd != AGGRE_MTHD_NONE) - pstat->aggre_mthd = AGGRE_MTHD_NONE; - } - } - break; - - case DOT11_ENC_NONE: - default: - DEBUG_ERR("No pairewise encryption key is set!\n"); - set_ttkeylen(pEncryptKey, 0); - set_tmickeylen(pEncryptKey, 0); - break; - } - } - - - HAPD_MSG("rtl_net80211_setkey ---\n"); - - return 0; - - - -} - -int rtl_net80211_delkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - -#ifdef RTK_NL80211 - struct ieee80211req_del_key *wk = (struct ieee80211req_del_key *)wrqu->data.pointer; -#else - struct ieee80211req_del_key *wk = (struct ieee80211req_del_key *)wrqu->name; -#endif - struct stat_info *pstat = NULL; - struct wifi_mib *pmib = priv->pmib; - - unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; - int ret = 0; - - //check if the interface is down - if (!netif_running(priv->dev)) - { - HAPD_MSG("\nFail: interface not opened\n"); - return 0; - } - - HAPD_MSG("rtl_net80211_delkey +++ \n"); - HAPD_MSG("keyid = %d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" - , wk->idk_keyix, wk->idk_macaddr[0], wk->idk_macaddr[1], wk->idk_macaddr[2], - wk->idk_macaddr[3], wk->idk_macaddr[4], wk->idk_macaddr[5]); - - if(!memcmp(wk->idk_macaddr, "\x00\x00\x00\x00\x00\x00", 6)) - { - HAPD_MSG("reset ALL key !!!!!\n"); - CamResetAllEntry(priv); - } - - if (!memcmp(wk->idk_macaddr, MULTICAST_ADD, 6)) - { - pmib->dot11GroupKeysTable.dot11EncryptKey.dot11TTKeyLen = 0; - pmib->dot11GroupKeysTable.dot11EncryptKey.dot11TMicKeyLen = 0; - - HAPD_MSG("Delete Group Key\n"); - if (CamDeleteOneEntry(priv, MULTICAST_ADD, 1, 0)) - priv->pshare->CamEntryOccupied--; - #if defined(CONFIG_RTL_HW_WAPI_SUPPORT) - if (CamDeleteOneEntry(priv, MULTICAST_ADD, 1, 0)) - priv->pshare->CamEntryOccupied--; - #endif - - } - else - { - pstat = get_stainfo(priv, (UINT8 *)wk->idk_macaddr); - if (pstat == NULL) - return (-1); - - pstat->dot11KeyMapping.dot11EncryptKey.dot11TTKeyLen = 0; - pstat->dot11KeyMapping.dot11EncryptKey.dot11TMicKeyLen = 0; - - HAPD_MSG("Delete Unicast Key\n"); - if (pstat->dot11KeyMapping.keyInCam == TRUE) { - if (CamDeleteOneEntry(priv, (unsigned char *)wk->idk_macaddr, 0, 0)) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - #if defined(CONFIG_RTL_HW_WAPI_SUPPORT) - if (CamDeleteOneEntry(priv, (unsigned char *)wk->idk_macaddr, 0, 0)) { - priv->pshare->CamEntryOccupied--; - if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; - } - #endif - } - } - - HAPD_MSG("rtl_net80211_delkey --- \n"); - - return ret; - - -} - -int rtl_net80211_getwpaie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct ieee80211req_wpaie *ie = (struct ieee80211req_wpaie *)wrqu->data.pointer; - struct stat_info *pstat = get_stainfo(priv, ie->wpa_macaddr); - int ret = 0; - HAPD_MSG("rtl_net80211_getwpaie +++ \n"); - HAPD_MSG("mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", - ie->wpa_macaddr[0], ie->wpa_macaddr[1], ie->wpa_macaddr[2], - ie->wpa_macaddr[3], ie->wpa_macaddr[4], ie->wpa_macaddr[5]); - - if(pstat == NULL) - return -EINVAL; - -#ifndef HAPD_DRV_PSK_WPS - HAPD_MSG("RSNEnabled = %d\n" - "wpa_ie = 0x%02x 0x%02x 0x%02x \n" - "wps_ie = 0x%02x 0x%02x 0x%02x \n" - ,pstat->wpa_sta_info->RSNEnabled, - pstat->wpa_ie[0], pstat->wpa_ie[1], pstat->wpa_ie[2], - pstat->wps_ie[0], pstat->wps_ie[1], pstat->wps_ie[2] - ); -#else - HAPD_MSG("RSNEnabled = %d\n" - "wpa_ie = 0x%02x 0x%02x 0x%02x \n" - ,pstat->wpa_sta_info->RSNEnabled, - pstat->wpa_ie[0], pstat->wpa_ie[1], pstat->wpa_ie[2] - ); -#endif - - if(pstat->wpa_sta_info->RSNEnabled & BIT(0)) - memcpy(ie->wpa_ie, pstat->wpa_ie, pstat->wpa_ie[1]+2); - else if(pstat->wpa_sta_info->RSNEnabled & BIT(1)) - memcpy(ie->rsn_ie, pstat->wpa_ie, pstat->wpa_ie[1]+2); - -#ifndef HAPD_DRV_PSK_WPS - if((priv->pmib->wscEntry.wsc_enable & 2) && (pstat->wps_ie[1])) - memcpy(ie->wps_ie, pstat->wps_ie, pstat->wps_ie[1]+2); -#endif - - HAPD_MSG("rtl_net80211_getwpaie --- \n"); - return ret; - -} - - -#if ((defined(WIFI_HAPD) || defined(RTK_NL80211)) && defined(WDS)) && !defined(HAPD_DRV_PSK_WPS) -int rtl_net80211_wdsaddmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct rtk_wds_config *wds = (struct hapd_wds_info *)wrqu->data.pointer; - int ret = 0; - int num = 0; - - HAPD_MSG("rtl_net80211_wdsaddmac +++ \n"); - - if(wds->wdsEnabled == 0) - goto bad; - if(wds->wdsNum > NUM_WDS) - goto bad; - if( (wds->wdsPrivacy != _NO_PRIVACY_) && (wds->wdsPrivacy != _WEP_40_PRIVACY_) && - (wds->wdsPrivacy != _TKIP_PRIVACY_) && (wds->wdsPrivacy != _CCMP_PRIVACY_) && - (wds->wdsPrivacy != _WEP_104_PRIVACY_)) - goto bad; - - if((wds->wdsPrivacy == _WEP_40_PRIVACY_) && (wds->wdsWepKeyLen != 5)) - goto bad; - if((wds->wdsPrivacy == _WEP_104_PRIVACY_) && (wds->wdsWepKeyLen != 13)) - goto bad; - - priv->pmib->dot11WdsInfo.wdsEnabled = 1; - priv->pmib->dot11WdsInfo.wdsNum = wds->wdsNum; - - for(num=0 ; num < wds->wdsNum; num++) - memcpy(priv->pmib->dot11WdsInfo.entry[num].macAddr, wds->macAddr[num], MACADDRLEN); - - priv->pmib->dot11WdsInfo.wdsPrivacy = wds->wdsPrivacy; - - if((wds->wdsPrivacy == _WEP_40_PRIVACY_)||(wds->wdsPrivacy == _WEP_104_PRIVACY_)) - memcpy(priv->pmib->dot11WdsInfo.wdsWepKey, wds->wdsWepKey, wds->wdsWepKeyLen); - else if((wds->wdsPrivacy == _TKIP_PRIVACY_)||(wds->wdsPrivacy == _CCMP_PRIVACY_)) - hapd_set_wdskey(dev, wds->wdsPskPassPhrase, wds->ssid, wds->wdsNum); - - - HAPD_MSG("rtl_net80211_wdsaddmac --- \n"); - return 0; - -bad: - priv->pmib->dot11WdsInfo.wdsEnabled = 0; - return -EINVAL; - - -} - -int rtl_net80211_wdsdelmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct rtk_wds_config *wds = (struct rtk_wds_config *)wrqu->data.pointer; - HAPD_MSG("rtl_net80211_wdsdelmac +++ \n"); - - priv->pmib->dot11WdsInfo.wdsEnabled = 0; - priv->pmib->dot11WdsInfo.wdsNum = 0; - - HAPD_MSG("rtl_net80211_wdsdelmac --- \n"); - return 0; -} -#endif - - -int rtl_hapd_config(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct rtk_hapd_config *config = (struct rtk_hapd_config *)wrqu->data.pointer; - int size = 0; - - HAPD_MSG("rtl_hapd_config +++\n"); - - priv->pmib->dot11BssType.net_work_type = config->band; - priv->pmib->dot11RFEntry.dot11channel = config->channel; - priv->pmib->dot11StationConfigEntry.dot11BeaconPeriod = config->bcnint; - priv->pmib->dot11StationConfigEntry.dot11DTIMPeriod = config->dtimperiod; - - if(config->stanum <= NUM_STAT) - priv->pmib->dot11StationConfigEntry.supportedStaNum = config->stanum; - else - { - HAPD_MSG("Invalid Station Number!!!\n"); - return -1; - } - - priv->pmib->dot11OperationEntry.dot11RTSThreshold = config->rtsthres; - priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = config->fragthres; - priv->pmib->dot11StationConfigEntry.dot11SupportedRates = config->oprates; - priv->pmib->dot11StationConfigEntry.dot11BasicRates = config->basicrates; - priv->pmib->dot11RFEntry.shortpreamble = config->preamble; - priv->pmib->dot11StationConfigEntry.dot11AclMode = config->aclmode; - priv->pmib->dot11StationConfigEntry.dot11AclNum = config->aclnum; - - size = sizeof(priv->pmib->dot11StationConfigEntry.dot11AclAddr); - memcpy(priv->pmib->dot11StationConfigEntry.dot11AclAddr, config->acladdr, size); - - priv->pmib->dot11OperationEntry.hiddenAP = config->hiddenAP; -#ifdef WIFI_WMM - priv->pmib->dot11QosEntry.dot11QosEnable = config->qos_enable; -#endif - priv->pmib->dot11OperationEntry.expiretime = config->expired_time * 100; // 10ms unit vs 1s unit - priv->pmib->dot11OperationEntry.block_relay = config->block_relay; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = config->shortGI20M; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = config->shortGI40M; - - -//Above are for Hostapd owned configurations -//===================================================== -//Below are for RTK private configurations - - size = sizeof(priv->pmib->dot11RFEntry.pwrlevelCCK_A); - memcpy(priv->pmib->dot11RFEntry.pwrlevelCCK_A, config->pwrlevelCCK_A, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrlevelCCK_B); - memcpy(priv->pmib->dot11RFEntry.pwrlevelCCK_B, config->pwrlevelCCK_B, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A); - memcpy(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A, config->pwrlevelHT40_1S_A, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B); - memcpy(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B, config->pwrlevelHT40_1S_A, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrdiffHT40_2S); - memcpy(priv->pmib->dot11RFEntry.pwrdiffHT40_2S, config->pwrdiffHT40_2S, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrdiffHT20); - memcpy(priv->pmib->dot11RFEntry.pwrdiffHT20, config->pwrdiffHT20, size); - - size = sizeof(priv->pmib->dot11RFEntry.pwrdiffOFDM); - memcpy(priv->pmib->dot11RFEntry.pwrdiffOFDM, config->pwrdiffOFDM, size); - - priv->pmib->dot11RFEntry.ther = config->ther; - -#ifdef CONFIG_RTL_92D_SUPPORT - priv->pmib->dot11RFEntry.phyBandSelect = config->phyBandSelect; -#endif - - priv->pmib->dot11StationConfigEntry.dot11swcrypto = config->swcrypto; - priv->pmib->dot11StationConfigEntry.dot11RegDomain = config->regdomain; - priv->pmib->dot11StationConfigEntry.autoRate = config->autorate; - priv->pmib->dot11StationConfigEntry.fixedTxRate = config->fixrate; - priv->pmib->dot11StationConfigEntry.protectionDisabled = config->disable_protection; - priv->pmib->dot11StationConfigEntry.olbcDetectDisabled = config->disable_olbc; - priv->pmib->dot11StationConfigEntry.legacySTADeny = config->deny_legacy; - priv->pmib->dot11OperationEntry.opmode = config->opmode; - priv->pmib->dot11nConfigEntry.dot11nUse40M = config->use40M; - priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = config->_2ndchoffset; - priv->pmib->dot11nConfigEntry.dot11nAMPDU = config->ampdu; - priv->pmib->dot11OperationEntry.guest_access = config->guest_access; - - priv->pmib->dot11RFEntry.macPhyMode = config->macPhyMode; - -#ifdef WIFI_11N_2040_COEXIST - priv->pmib->dot11nConfigEntry.dot11nCoexist = config->coexist; -#endif - -#ifdef MBSSID - priv->pmib->miscEntry.vap_enable = config->vap_enable; -#endif - - priv->pshare->rf_ft_var.rssi_dump = config->rssi_dump; - -#ifdef MP_TEST - priv->pshare->rf_ft_var.mp_specific = config->mp_specific; -#endif - -#ifdef HIGH_POWER_EXT_PA - priv->pshare->rf_ft_var.use_ext_pa = config->use_ext_pa; -#endif - - HAPD_MSG("rtl_hapd_config ---\n"); - return 0; -} - - - -#ifdef WIFI_WPAS - -int rtl_wpas_config_2G(struct rtl8192cd_priv *priv) -{ - HAPD_MSG("wpas config wlan 2.4G\n"); - - priv->pmib->dot11BssType.net_work_type = 1 + 2 + 8; - priv->pmib->dot11RFEntry.dot11channel = 11; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; - priv->pmib->dot11StationConfigEntry.autoRate = 1; - priv->pmib->dot11nConfigEntry.dot11nUse40M = 1; - priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; - //priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; - priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pmib->dot11StationConfigEntry.dot11SupportedRates = 0xfff; - priv->pmib->dot11StationConfigEntry.dot11BasicRates = 0xf; - priv->pmib->dot11OperationEntry.wifi_specific = 2; //_Eric ?? - - priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = 2346; - -#ifdef CONFIG_RTL_92D_SUPPORT - priv->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_2G; -#endif - -#ifdef WIFI_WMM - priv->pmib->dot11QosEntry.dot11QosEnable = 1; -#endif - -} - -int rtl_wpas_config_5G(struct rtl8192cd_priv *priv) -{ - printk("wpas config wlan 5G\n"); - - priv->pmib->dot11BssType.net_work_type = 4 + 8; - priv->pmib->dot11RFEntry.dot11channel = 44; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; - priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; - priv->pmib->dot11StationConfigEntry.autoRate = 1; - priv->pmib->dot11nConfigEntry.dot11nUse40M = 1; - priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; - //priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; //_Eric ?? How to judge ?? - priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pmib->dot11StationConfigEntry.dot11SupportedRates = 0xff0; - priv->pmib->dot11StationConfigEntry.dot11BasicRates = 0xff0; - priv->pmib->dot11OperationEntry.wifi_specific = 2; - - priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = 2346; - -#ifdef CONFIG_RTL_92D_SUPPORT - priv->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_5G; -#endif - -#ifdef WIFI_WMM - priv->pmib->dot11QosEntry.dot11QosEnable = 1; -#endif - -} - - -int rtl_wpas_config(struct rtl8192cd_priv *priv, unsigned char bandmode, unsigned char phymode) -{ - HAPD_MSG("wpas config interface: %s\n", priv->dev->name); - - priv->pmib->dot11OperationEntry.opmode = WIFI_STATION_STATE; - - if(bandmode == SINGLEMAC_SINGLEPHY) - { - priv->pmib->dot11RFEntry.macPhyMode = SINGLEMAC_SINGLEPHY; - - if(phymode == PHY_BAND_5G) - rtl_wpas_config_5G(priv); - else if(phymode == PHY_BAND_2G) - rtl_wpas_config_2G(priv); - else - return -1; - - } -#if defined(CUSTOMIZE_WLAN_IF_NAME) - else if(!strcmp(priv->dev->name, ROOT_IFNAME_5G)) -#else - else if(!strcmp(priv->dev->name, "wlan0")) -#endif - { - priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; - rtl_wpas_config_5G(priv); - } -#if defined(CUSTOMIZE_WLAN_IF_NAME) - else if(!strcmp(priv->dev->name, ROOT_IFNAME_2G)) -#else - else if(!strcmp(priv->dev->name, "wlan1")) -#endif - { - priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; - rtl_wpas_config_2G(priv); - } - else - return -1; - - return 0; - - -} - - -int rtl_wpas_custom(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) -{ - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct rtk_wpas_config *config = (struct rtk_wpas_config *)wrqu->data.pointer; - - int ret = 0; - - switch (config->type) { - case WPAS_CONFIG_MIB: - HAPD_MSG("bandmode %d phymode %d \n", config->bandmode, config->phymode); - if((config->bandmode == SINGLEMAC_SINGLEPHY) || (config->bandmode == DUALMAC_DUALPHY)) - ret = rtl_wpas_config(priv, config->bandmode, config->phymode); - else - return -EINVAL; - break; - case WPAS_CONFIG_WEPKEY: - HAPD_MSG("WPAS_CONFIG_WEPKEY !!! \n"); - CTRL_LEN_CHECK(16,config->wep_keylen); - memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[config->wep_keyidx].skey[0], config->wep_key, config->wep_keylen); - break; - - } - - return ret; - -} -#endif - -static void Construct_RSNIE(struct rtl8192cd_priv *priv, unsigned char *pucOut, int *usOutLen) -{ - DOT11_RSN_IE_HEADER dot11RSNIEHeader = { 0 }; - DOT11_RSN_IE_SUITE dot11RSNGroupSuite; - DOT11_RSN_IE_COUNT_SUITE *pDot11RSNPairwiseSuite = NULL; - DOT11_RSN_IE_COUNT_SUITE *pDot11RSNAuthSuite = NULL; - unsigned short usSuitCount; - unsigned long ulIELength = 0; - unsigned long ulIndex = 0; - unsigned long ulPairwiseLength = 0; - unsigned long ulAuthLength = 0; - unsigned char *pucBlob; - DOT11_RSN_IE_COUNT_SUITE countSuite, authCountSuite; -#ifdef RTL_WPA2 - DOT11_RSN_CAPABILITY dot11RSNCapability = { 0 }; - unsigned long uCipherAlgo = 0; - int bCipherAlgoEnabled = FALSE; - unsigned long uAuthAlgo = 0; - int bAuthAlgoEnabled = FALSE; - unsigned long ulRSNCapabilityLength = 0; -#endif - - *usOutLen = 0; - if ( priv->pmib->dot1180211AuthEntry.dot11WPACipher != 0 ) { - // - // Construct Information Header - // - dot11RSNIEHeader.ElementID = RSN_ELEMENT_ID; - dot11RSNIEHeader.OUI[0] = 0x00; - dot11RSNIEHeader.OUI[1] = 0x50; - dot11RSNIEHeader.OUI[2] = 0xf2; - dot11RSNIEHeader.OUI[3] = 0x01; - dot11RSNIEHeader.Version = cpu_to_le16(RSN_VER1); - ulIELength += sizeof(DOT11_RSN_IE_HEADER); - - // Construct Cipher Suite: - // - Multicast Suite: - memset(&dot11RSNGroupSuite, 0, sizeof dot11RSNGroupSuite); - dot11RSNGroupSuite.OUI[0] = 0x00; - dot11RSNGroupSuite.OUI[1] = 0x50; - dot11RSNGroupSuite.OUI[2] = 0xF2; - dot11RSNGroupSuite.Type = priv->wpa_global_info->MulticastCipher; - ulIELength += sizeof(DOT11_RSN_IE_SUITE); - - // - UnicastSuite - pDot11RSNPairwiseSuite = &countSuite; - memset(pDot11RSNPairwiseSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); - usSuitCount = 0; - -#ifdef RTK_NL80211 - for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipher; ulIndex++) - { - int i = ulIndexwpa_global_info->NumOfUnicastCipher - ulIndex - 1; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipher[i]; - usSuitCount++; - } -#else - for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipher; ulIndex++) - { - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipher[ulIndex]; - usSuitCount++; - } -#endif - - pDot11RSNPairwiseSuite->SuiteCount = cpu_to_le16(usSuitCount); - ulPairwiseLength = sizeof(pDot11RSNPairwiseSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); - ulIELength += ulPairwiseLength; - - // - // Construction of Auth Algo List - // - pDot11RSNAuthSuite = &authCountSuite; - memset(pDot11RSNAuthSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); - usSuitCount = 0; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].Type = DOT11_AuthKeyType_RSN; - usSuitCount++; - - pDot11RSNAuthSuite->SuiteCount = cpu_to_le16(usSuitCount); - ulAuthLength = sizeof(pDot11RSNAuthSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); - ulIELength += ulAuthLength; - - pucBlob = pucOut; - pucBlob += sizeof(DOT11_RSN_IE_HEADER); - memcpy(pucBlob, &dot11RSNGroupSuite, sizeof(DOT11_RSN_IE_SUITE)); - pucBlob += sizeof(DOT11_RSN_IE_SUITE); - memcpy(pucBlob, pDot11RSNPairwiseSuite, ulPairwiseLength); - pucBlob += ulPairwiseLength; - memcpy(pucBlob, pDot11RSNAuthSuite, ulAuthLength); - pucBlob += ulAuthLength; - - *usOutLen = (int)ulIELength; - pucBlob = pucOut; - dot11RSNIEHeader.Length = (unsigned char)ulIELength - 2; //This -2 is to minus elementID and Length in OUI header - memcpy(pucBlob, &dot11RSNIEHeader, sizeof(DOT11_RSN_IE_HEADER)); - } - -#ifdef RTL_WPA2 - if ( priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher != 0 ) { - DOT11_WPA2_IE_HEADER dot11WPA2IEHeader = { 0 }; - ulIELength = 0; - ulIndex = 0; - ulPairwiseLength = 0; - uCipherAlgo = 0; - bCipherAlgoEnabled = FALSE; - ulAuthLength = 0; - uAuthAlgo = 0; - bAuthAlgoEnabled = FALSE; - ulRSNCapabilityLength = 0; - - // - // Construct Information Header - // - dot11WPA2IEHeader.ElementID = WPA2_ELEMENT_ID; - dot11WPA2IEHeader.Version = cpu_to_le16(RSN_VER1); - ulIELength += sizeof(DOT11_WPA2_IE_HEADER); - - // Construct Cipher Suite: - // - Multicast Suite: - // - memset(&dot11RSNGroupSuite, 0, sizeof(dot11RSNGroupSuite)); - dot11RSNGroupSuite.OUI[0] = 0x00; - dot11RSNGroupSuite.OUI[1] = 0x0F; - dot11RSNGroupSuite.OUI[2] = 0xAC; - dot11RSNGroupSuite.Type = priv->wpa_global_info->MulticastCipher;; - ulIELength += sizeof(DOT11_RSN_IE_SUITE); - - // - UnicastSuite - pDot11RSNPairwiseSuite = &countSuite; - memset(pDot11RSNPairwiseSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); - usSuitCount = 0; - -#ifdef RTK_NL80211 - for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipherWPA2; ulIndex++) - { - int i = priv->wpa_global_info->NumOfUnicastCipherWPA2 - ulIndex - 1; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipherWPA2[i]; - usSuitCount++; - } -#else - for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipherWPA2; ulIndex++) - { - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; - pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipherWPA2[ulIndex]; - usSuitCount++; - } -#endif - - pDot11RSNPairwiseSuite->SuiteCount = cpu_to_le16(usSuitCount); - ulPairwiseLength = sizeof(pDot11RSNPairwiseSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); - ulIELength += ulPairwiseLength; - - // - // Construction of Auth Algo List - // - pDot11RSNAuthSuite = &authCountSuite; - memset(pDot11RSNAuthSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); - usSuitCount = 0; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; - pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].Type = DOT11_AuthKeyType_RSN; - usSuitCount++; - - pDot11RSNAuthSuite->SuiteCount = cpu_to_le16(usSuitCount); - ulAuthLength = sizeof(pDot11RSNAuthSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); - ulIELength += ulAuthLength; - - //--------------------------------------------------------------------------------------------- - // Do not encapsulate capability field to solve TI WPA issue - //--------------------------------------------------------------------------------------------- - - dot11RSNCapability.field.PreAuthentication = 0; - - ulRSNCapabilityLength = sizeof(DOT11_RSN_CAPABILITY); - ulIELength += ulRSNCapabilityLength; - -#if (defined(WIFI_HAPD) & defined(WIFI_WMM)) || (defined(RTK_NL80211) & defined(WIFI_WMM)) //eric-eap - if(QOS_ENABLE){ - /* 4 PTKSA replay counters when using WMM consistent with hostapd code*/ - dot11RSNCapability.field.PtksaReplayCounter = 3; - } -#endif - - pucBlob = pucOut + *usOutLen; - pucBlob += sizeof(DOT11_WPA2_IE_HEADER); - memcpy(pucBlob, &dot11RSNGroupSuite, sizeof(DOT11_RSN_IE_SUITE)); - pucBlob += sizeof(DOT11_RSN_IE_SUITE); - memcpy(pucBlob, pDot11RSNPairwiseSuite, ulPairwiseLength); - pucBlob += ulPairwiseLength; - memcpy(pucBlob, pDot11RSNAuthSuite, ulAuthLength); - pucBlob += ulAuthLength; - memcpy(pucBlob, &dot11RSNCapability, ulRSNCapabilityLength); - - pucBlob = pucOut + *usOutLen; - dot11WPA2IEHeader.Length = (unsigned char)ulIELength - 2; //This -2 is to minus elementID and Length in OUI header - memcpy(pucBlob, &dot11WPA2IEHeader, sizeof(DOT11_WPA2_IE_HEADER)); - *usOutLen = *usOutLen + (int)ulIELength; - } -#endif // RTL_WPA2 - -} - - -static void ToDrv_SetRSNIE(struct rtl8192cd_priv *priv) -{ - struct iw_point wrq; - DOT11_SET_RSNIE Set_Rsnie; - - - debug_out("RSN: Set RSNIE", priv->wpa_global_info->AuthInfoElement.Octet, - priv->wpa_global_info->AuthInfoElement.Length); - - - wrq.pointer = (caddr_t)&Set_Rsnie; - wrq.length = sizeof(DOT11_SET_RSNIE); - Set_Rsnie.EventId = DOT11_EVENT_SET_RSNIE; - Set_Rsnie.IsMoreEvent = FALSE; - Set_Rsnie.Flag = DOT11_Ioctl_Set; - Set_Rsnie.RSNIELen = priv->wpa_global_info->AuthInfoElement.Length; - memcpy(&Set_Rsnie.RSNIE, - priv->wpa_global_info->AuthInfoElement.Octet, - priv->wpa_global_info->AuthInfoElement.Length); - - rtl8192cd_ioctl_priv_daemonreq(priv->dev, &wrq); -} - - -void rsn_init(struct rtl8192cd_priv *priv) -{ - WPA_GLOBAL_INFO *pGblInfo=priv->wpa_global_info; - int i, j, low_cipher=0; - - DEBUG_TRACE; - - HAPD_MSG("rsn_init\n"); - - memset((char *)pGblInfo, '\0', sizeof(WPA_GLOBAL_INFO)); - - if (priv->pmib->dot1180211AuthEntry.dot11WPACipher) { - for (i=0, j=0; i<_WEP_104_PRIVACY_; i++) { - if (priv->pmib->dot1180211AuthEntry.dot11WPACipher & (1<UnicastCipher[j] = i+1; - if (low_cipher == 0) - low_cipher = pGblInfo->UnicastCipher[j]; - else { - if (low_cipher == _WEP_104_PRIVACY_ && - pGblInfo->UnicastCipher[j] == _WEP_40_PRIVACY_) - low_cipher = pGblInfo->UnicastCipher[j]; - else if (low_cipher == _TKIP_PRIVACY_ && - (pGblInfo->UnicastCipher[j] == _WEP_40_PRIVACY_ || - pGblInfo->UnicastCipher[j] == _WEP_104_PRIVACY_)) - low_cipher = pGblInfo->UnicastCipher[j]; - else if (low_cipher == _CCMP_PRIVACY_) - low_cipher = pGblInfo->UnicastCipher[j]; - } - if (++j >= MAX_UNICAST_CIPHER) - break; - } - } - pGblInfo->NumOfUnicastCipher = j; - } - -#ifdef RTL_WPA2 - if (priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher) { - for (i=0, j=0; i<_WEP_104_PRIVACY_; i++) { - if (priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher & (1<UnicastCipherWPA2[j] = i+1; - if (low_cipher == 0) - low_cipher = pGblInfo->UnicastCipherWPA2[j]; - else { - if (low_cipher == _WEP_104_PRIVACY_ && - pGblInfo->UnicastCipherWPA2[j] == _WEP_40_PRIVACY_) - low_cipher = pGblInfo->UnicastCipherWPA2[j]; - else if (low_cipher == _TKIP_PRIVACY_ && - (pGblInfo->UnicastCipherWPA2[j] == _WEP_40_PRIVACY_ || - pGblInfo->UnicastCipherWPA2[j] == _WEP_104_PRIVACY_)) - low_cipher = pGblInfo->UnicastCipherWPA2[j]; - else if (low_cipher == _CCMP_PRIVACY_) - low_cipher = pGblInfo->UnicastCipherWPA2[j]; - } - if (++j >= MAX_UNICAST_CIPHER) - break; - } - } - pGblInfo->NumOfUnicastCipherWPA2= j; - } -#endif - - pGblInfo->MulticastCipher = low_cipher; - - HAPD_MSG("RSN: WPA unicast cipher= "); - for (i=0; iNumOfUnicastCipher; i++) - HAPD_MSG("%x ", pGblInfo->UnicastCipher[i]); - HAPD_MSG("\n"); - -#ifdef RTL_WPA2 - HAPD_MSG("RSN: WPA2 unicast cipher= "); - for (i=0; iNumOfUnicastCipherWPA2; i++) - HAPD_MSG("%x ", pGblInfo->UnicastCipherWPA2[i]); - HAPD_MSG("\n"); -#endif - - HAPD_MSG("RSN: multicast cipher= %x\n", pGblInfo->MulticastCipher); - - - pGblInfo->AuthInfoElement.Octet = pGblInfo->AuthInfoBuf; - - Construct_RSNIE(priv, pGblInfo->AuthInfoElement.Octet, - &pGblInfo->AuthInfoElement.Length); - - ToDrv_SetRSNIE(priv); -} - -#endif //WIFI_HAPD +/* + * API-compatible handling routines + * + * + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifdef __KERNEL__ +#include +#include +#include +#include +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" + +#if defined(WIFI_HAPD) || defined(RTK_NL80211) + +#ifdef __LINUX_2_6__ +#include +#include +#endif + +#include "./8192cd_debug.h" +#include "./8192cd_headers.h" + +#include +#include +#include +#include +#include +#include + +#include "./8192cd_net80211.h" + + +//#define HAPD_DEBUG + +void void_printk(const char *fmt, ...) +{ + ; +} + +#ifdef HAPD_DEBUG +#define HAPD_MSG printk +#else +#define HAPD_MSG void_printk +#endif + + + +const char* ether_sprintf(const u_int8_t *mac) +{ + static char etherbuf[18]; /* XXX */ + snprintf(etherbuf, sizeof(etherbuf), "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return etherbuf; +} + +static __inline__ void set_ttkeylen(struct Dot11EncryptKey *pEncryptKey, UINT8 len) +{ + pEncryptKey->dot11TTKeyLen = len; +} + + +static __inline__ void set_tmickeylen(struct Dot11EncryptKey *pEncryptKey, UINT8 len) +{ + pEncryptKey->dot11TMicKeyLen = len; +} + +static __inline__ void set_tkip_key_for_wpas(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) +{ + memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); + + memcpy(pEncryptKey->dot11TMicKey2.skey, src + 16, pEncryptKey->dot11TMicKeyLen); + memcpy(pEncryptKey->dot11TMicKey1.skey, src + 24, pEncryptKey->dot11TMicKeyLen); + + memcpy(src + 16, pEncryptKey->dot11TMicKey2.skey, pEncryptKey->dot11TMicKeyLen); + memcpy(src + 24, pEncryptKey->dot11TMicKey1.skey, pEncryptKey->dot11TMicKeyLen); + + pEncryptKey->dot11TXPN48.val48 = 0; +} + +static __inline__ void set_tkip_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) +{ + memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); + + memcpy(pEncryptKey->dot11TMicKey1.skey, src + 16, pEncryptKey->dot11TMicKeyLen); + + memcpy(pEncryptKey->dot11TMicKey2.skey, src + 24, pEncryptKey->dot11TMicKeyLen); + + pEncryptKey->dot11TXPN48.val48 = 0; +} + + +static __inline__ void set_aes_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) +{ + memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); + + memcpy(pEncryptKey->dot11TMicKey1.skey, src, pEncryptKey->dot11TMicKeyLen); +} + + +static __inline__ void set_wep40_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) +{ + memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); +} + + +static __inline__ void set_wep104_key(struct Dot11EncryptKey *pEncryptKey, UINT8 *src) +{ + memcpy(pEncryptKey->dot11TTKey.skey, src, pEncryptKey->dot11TTKeyLen); +} + + +static int HAPD_Process_Set_Port(struct net_device *dev, unsigned char *MACAddr, int PortStatus) +{ + struct stat_info *pstat; + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct wifi_mib *pmib = priv->pmib; + + HAPD_MSG("HAPD_Process_Set_Port +++ sta: %02X%02X%02X%02X%02X%02X Status %X\n", + MACAddr[0],MACAddr[1],MACAddr[2], + MACAddr[3],MACAddr[4],MACAddr[5], + PortStatus); + + // if driver is not opened, return immediately, david + if (!netif_running(priv->dev)) + return (-1); + + pstat = get_stainfo(priv, MACAddr); + + if ((pstat == NULL) || (!(pstat->state & WIFI_ASOC_STATE))) + return (-1); + + if (PortStatus) + pstat->ieee8021x_ctrlport = PortStatus; + else + pstat->ieee8021x_ctrlport = pmib->dot118021xAuthEntry.dot118021xDefaultPort; + + HAPD_MSG("HAPD_Process_Set_Port ---\n"); + + return 0; +} + +#if defined(WIFI_WPAS) || defined(RTK_NL80211) + +int rtl_wpas_join(struct rtl8192cd_priv *priv, int bss_num) +{ + char tmpbuf[33]; + + if (!netif_running(priv->dev)) { + printk("WiFi driver is NOT open!!\n"); + return -1; + } else if (priv->ss_req_ongoing) { + printk("Site Survey is not finished yet!!\n"); + return -1; + } + +#if defined(RTK_NL80211) + memcpy((void *)&(priv->pmib->dot11Bss) , + (void *)&priv->site_survey->bss_target[bss_num] , sizeof(struct bss_desc)); +#else + memcpy((void *)&(priv->pmib->dot11Bss) , + (void *)&priv->site_survey->bss_backup[bss_num] , sizeof(struct bss_desc)); +#endif + +#ifdef WIFI_SIMPLE_CONFIG + //_Eric if (priv->pmib->wscEntry.wsc_enable && (priv->pmib->dot11Bss.bsstype&WIFI_WPS)) + if (priv->pmib->wscEntry.wsc_enable) + { + //priv->pmib->dot11Bss.bsstype &= ~WIFI_WPS; + priv->wps_issue_join_req = 1; + } + else +#endif + { + if (check_bss_encrypt(priv) == FAIL) + { + printk("Encryption mismatch!\n"); + return -1; + } + } + + if ((priv->pmib->dot11Bss.ssidlen == 0) || (priv->pmib->dot11Bss.ssid[0] == '\0')) + { + printk("Error !! Join to a hidden AP!\n"); + return -1; + } + +#ifdef UNIVERSAL_REPEATER + disable_vxd_ap(GET_VXD_PRIV(priv)); +#endif + + memcpy(tmpbuf, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); + tmpbuf[priv->pmib->dot11Bss.ssidlen] = '\0'; + + NDEBUG3("[%s %d]going to join bss: [%s]\n",__FUNCTION__,__LINE__, tmpbuf); + + memcpy(SSID2SCAN, priv->pmib->dot11Bss.ssid, priv->pmib->dot11Bss.ssidlen); + SSID2SCAN_LEN = priv->pmib->dot11Bss.ssidlen; + + SSID_LEN = SSID2SCAN_LEN; + memcpy(SSID, SSID2SCAN, SSID_LEN); + memset(BSSID, 0, MACADDRLEN); + +#ifdef INCLUDE_WPA_PSK //_Eric ?? + //if (priv->pmib->dot1180211AuthEntry.dot11EnablePSK) + //derivePSK(priv); +#endif + priv->join_req_ongoing = 1; + priv->authModeRetry = 0; + + //mod_timer(&priv->WPAS_timer, jiffies + 300); + +#ifdef RTK_NL80211 + if(priv->pmib->dot11Bss.channel >=36) + { + if(GET_CHIP_VER(priv)==VERSION_8812E || GET_CHIP_VER(priv)==VERSION_8881A || GET_CHIP_VER(priv)==VERSION_8814A) + priv->pmib->dot11BssType.net_work_type = WIRELESS_11A|WIRELESS_11N|WIRELESS_11AC; + else + priv->pmib->dot11BssType.net_work_type = WIRELESS_11A|WIRELESS_11N; + } + else + { + #ifdef P2P_SUPPORT + if(rtk_p2p_is_enabled(priv)) + priv->pmib->dot11BssType.net_work_type = WIRELESS_11G|WIRELESS_11N; // p2p mode no included 11B + else + #endif + priv->pmib->dot11BssType.net_work_type = WIRELESS_11B|WIRELESS_11G|WIRELESS_11N; + + } + + priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; + + extern int is_support_ac(struct rtl8192cd_priv *priv); + + if(is_support_ac(priv)) + priv->pmib->dot11nConfigEntry.dot11nShortGIfor80M = 1; + +#ifdef CONFIG_WLAN_HAL_8814AE + if(GET_CHIP_VER(priv) == VERSION_8814A) + priv->pmib->dot11nConfigEntry.dot11nAMSDU=2; +#endif +#endif + + start_clnt_join(priv); + + return 0; +} + +#endif + + +void rtl_net80311_authmode(struct net_device *dev, int authtype, int encmode, + int pskenable, int dot11802_1x) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + + HAPD_MSG("rtl_net80311_authmode +++\n"); + HAPD_MSG("authtype=%d, encmode=%d, pskenable=%d, dot11802_1x=%d \n", authtype, encmode, pskenable, dot11802_1x); + + priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm = authtype; + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = encmode; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = pskenable; + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = dot11802_1x; +} + +int rtl_net80211_setparam(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + + int *i = (int *) extra; + int param = wrqu->mode; /* parameter id is 1st */ + int value = 0; /* NB: most values are TYPE_INT */ + int ret = 0; + + int authtype = priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm; + int encmode = priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm; + int pskenable = priv->pmib->dot1180211AuthEntry.dot11EnablePSK; + int dot11802_1x = priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm; + + memcpy(&value, wrqu->name+sizeof(value), sizeof(value)); + + HAPD_MSG("rtl_net80211_setparam +++\n"); + HAPD_MSG("rtl8192cd_net80211_ioctl, param = %d, value =%d\n", param, value); + + + switch (param) { + case IEEE80211_PARAM_TURBO: /* turbo mode */ + break; + case IEEE80211_PARAM_MODE: /* phy mode (11a, 11b, etc.) */ + break; + case IEEE80211_PARAM_AUTHMODE: /* authentication mode */ + switch (value) { + case IEEE80211_AUTH_NONE: + {//Disable + authtype = 0; + encmode = 0; + pskenable = 0; + dot11802_1x = 0; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + case IEEE80211_AUTH_OPEN: + {//WEP Open + authtype = 0; + //WEP encmode depends on key length + //encmode = 1; + pskenable = 0; + dot11802_1x = 0; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + case IEEE80211_AUTH_SHARED: + {//WEP Shared + authtype = 1; + //WEP encmode depends on key length + //encmode = 1; + pskenable = 0; + dot11802_1x = 0; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + case IEEE80211_AUTH_AUTO: + {//WEP Auto + authtype = 2; + //WEP encmode depends on key length + //encmode = 1; + pskenable = 0; + dot11802_1x = 0; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + case IEEE80211_AUTH_WPA: + {//WPA-PSK-AES + //_Eric ?? if there is no valid passphrase ?? + authtype = 2; + encmode = 2; + //_Eric pskmode (WPA 0,1,2) will be set by IEEE80211_PARAM_WPA + //pskenable = 1; + dot11802_1x = 1; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + case IEEE80211_AUTH_8021X: + { + //8021x encmode depends on key length + if((encmode == _WEP_40_PRIVACY_) || (encmode == _WEP_104_PRIVACY_)) + authtype = 2; + else + authtype = 0; + + pskenable = 0; + dot11802_1x = 1; + rtl_net80311_authmode(dev, authtype, encmode, pskenable, dot11802_1x); + break; + } + default: + return -EINVAL; + } + case IEEE80211_PARAM_PROTMODE: /* 802.11g protection */ + break; + case IEEE80211_PARAM_MCASTCIPHER: /* multicast/default cipher */ + break; + case IEEE80211_PARAM_MCASTKEYLEN: /* multicast key length */ + break; + case IEEE80211_PARAM_UCASTCIPHERS: /* unicast cipher suites */ + /* 1. Only support AES & TKIP for WPA1&WPA2 + 2. Set both wpa_cipher and wpa2_cipher, because IEEE80211_PARAM_WPA will clear unused cipher mode */ + HAPD_MSG("IEEE80211_PARAM_UCASTCIPHERS\n"); + + if(value & (1<pmib->dot11BssType.net_work_type & WIRELESS_11N)) || (OPMODE & WIFI_STATION_STATE)) + { + priv->pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(1); + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= BIT(1); + } + else + return -EINVAL; + } + else + { + priv->pmib->dot1180211AuthEntry.dot11WPACipher &= ~(BIT(1)); + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher &= ~(BIT(1)); + } + + + if(value & (1<pmib->dot1180211AuthEntry.dot11WPACipher |= BIT(3); + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher |= BIT(3); + } + else + { + priv->pmib->dot1180211AuthEntry.dot11WPACipher &= ~(BIT(3)); + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher &= ~(BIT(3)); + } + + priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm = 1; + + return 0; //_Eric if value > BIT(8) ? + + case IEEE80211_PARAM_UCASTCIPHER: /* unicast cipher */ + break; + case IEEE80211_PARAM_UCASTKEYLEN: /* unicast key length */ + if(value == 5) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_40_PRIVACY_; + else if(value == 13) + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _WEP_104_PRIVACY_; + else + priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm = _NO_PRIVACY_; + break; + case IEEE80211_PARAM_WPA: /* WPA mode (0,1,2) */ + HAPD_MSG("IEEE80211_PARAM_WPA\n"); + if((value & BIT(0)) && (value & BIT(1))) + return 0; + else if((value & BIT(0))) + {//only WPA1, so clear mib of wpa2_cipher & wpa2_psk + priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher = 0; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK & ~(BIT(1)); + return 0; + } + else if((value & BIT(1))) + {//only WPA2, so clear mib of wpa_cipher & wps2_psk + priv->pmib->dot1180211AuthEntry.dot11WPACipher = 0; + priv->pmib->dot1180211AuthEntry.dot11EnablePSK & ~(BIT(0)); + return 0; + } + + case IEEE80211_PARAM_ROAMING: /* roaming mode */ +#ifdef WIFI_WPAS + if(value == IEEE80211_ROAMING_DEVICE) + priv->pmib->dot11StationConfigEntry.fastRoaming = 1; + else if(value == IEEE80211_ROAMING_MANUAL) + priv->pmib->dot11StationConfigEntry.fastRoaming = 0; + else + return -EINVAL; +#endif + break; + case IEEE80211_PARAM_PRIVACY: /* privacy invoked */ + ret =0; //It seems useless, just return status OK for hostapd. + break; + case IEEE80211_PARAM_COUNTERMEASURES: /* WPA/TKIP countermeasures */ + //_Eric ?? realtek do not have to support ?? + break; + case IEEE80211_PARAM_DROPUNENCRYPTED: /* discard unencrypted frames */ + break; + case IEEE80211_PARAM_DRIVER_CAPS: /* driver capabilities */ + break; + case IEEE80211_PARAM_MACCMD: /* MAC ACL operation */ + break; + case IEEE80211_PARAM_WMM: /* WMM mode (on, off) */ + break; + case IEEE80211_PARAM_HIDESSID: /* hide SSID mode (on, off) */ + break; + case IEEE80211_PARAM_APBRIDGE: /* AP inter-sta bridging */ + break; + case IEEE80211_PARAM_KEYMGTALGS: /* key management algorithms */ + HAPD_MSG("IEEE80211_PARAM_KEYMGTALGS\n"); + if((0<=value) && (value<=3)) + { + priv->pmib->dot1180211AuthEntry.dot11EnablePSK = value; + break; + } + else + return -EINVAL; + case IEEE80211_PARAM_RSNCAPS: /* RSN capabilities */ + break; + case IEEE80211_PARAM_INACT: /* station inactivity timeout */ + break; + case IEEE80211_PARAM_INACT_AUTH: /* station auth inact timeout */ + break; + case IEEE80211_PARAM_INACT_INIT: /* station init inact timeout */ + break; + case IEEE80211_PARAM_ABOLT: /* Atheros Adv. Capabilities */ + break; + case IEEE80211_PARAM_DTIM_PERIOD: /* DTIM period (beacons) */ + break; + case IEEE80211_PARAM_BEACON_INTERVAL: /* beacon interval (ms) */ + break; + case IEEE80211_PARAM_DOTH: /* 11.h is on/off */ + break; + case IEEE80211_PARAM_PWRTARGET: /* Current Channel Pwr Constraint */ + break; + case IEEE80211_PARAM_GENREASSOC: /* Generate a reassociation request */ + break; + case IEEE80211_PARAM_COMPRESSION: /* compression */ + break; + case IEEE80211_PARAM_FF: /* fast frames support */ + break; + case IEEE80211_PARAM_XR: /* XR support */ + break; + case IEEE80211_PARAM_BURST: /* burst mode */ + break; + case IEEE80211_PARAM_PUREG: /* pure 11g (no 11b stations) */ + break; + case IEEE80211_PARAM_AR: /* AR support */ + break; + case IEEE80211_PARAM_WDS: /* Enable 4 address processing */ + break; + case IEEE80211_PARAM_BGSCAN: /* bg scanning (on, off) */ + break; + case IEEE80211_PARAM_BGSCAN_IDLE: /* bg scan idle threshold */ + break; + case IEEE80211_PARAM_BGSCAN_INTERVAL: /* bg scan interval */ + break; + case IEEE80211_PARAM_MCAST_RATE: /* Multicast Tx Rate */ + break; + case IEEE80211_PARAM_COVERAGE_CLASS: /* coverage class */ + break; + case IEEE80211_PARAM_COUNTRY_IE: /* enable country IE */ + break; + case IEEE80211_PARAM_SCANVALID: /* scan cache valid threshold */ + break; + case IEEE80211_PARAM_ROAM_RSSI_11A: /* rssi threshold in 11a */ + break; + case IEEE80211_PARAM_ROAM_RSSI_11B: /* rssi threshold in 11b */ + break; + case IEEE80211_PARAM_ROAM_RSSI_11G: /* rssi threshold in 11g */ + break; + case IEEE80211_PARAM_ROAM_RATE_11A: /* tx rate threshold in 11a */ + break; + case IEEE80211_PARAM_ROAM_RATE_11B: /* tx rate threshold in 11b */ + break; + case IEEE80211_PARAM_ROAM_RATE_11G: /* tx rate threshold in 11g */ + break; + case IEEE80211_PARAM_UAPSDINFO: /* value for qos info field */ + break; + case IEEE80211_PARAM_SLEEP: /* force sleep/wake */ + break; + case IEEE80211_PARAM_QOSNULL: /* force sleep/wake */ + break; + case IEEE80211_PARAM_PSPOLL: /* force ps-poll generation (sta only) */ + break; + case IEEE80211_PARAM_EOSPDROP: /* force uapsd EOSP drop (ap only) */ + break; + case IEEE80211_PARAM_MARKDFS: /* mark a dfs interference channel when found */ + break; + case IEEE80211_PARAM_REGCLASS: /* enable regclass ids in country IE */ + break; + case IEEE80211_PARAM_DROPUNENC_EAPOL: /* drop unencrypted eapol frames */ + break; + case IEEE80211_PARAM_SHPREAMBLE: /* Short Preamble */ + break; + + } + + HAPD_MSG("rtl_net80211_setparam ---\n"); + return ret; + +} + +/* +Management frame type to which application IE is added +enum { + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; +*/ + +int rtl_net80211_setappiebuf(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct ieee80211req_getset_appiebuf * ie = (struct ieee80211req_getset_appiebuf *)wrqu->data.pointer; + int ret = 0; + + HAPD_MSG("rtl_net80211_setappiebuf +++\n"); + HAPD_MSG("frametype =%d, iebuflen=%d \n", ie->app_frmtype, ie->app_buflen); + + //_Eric ???? hostapd has no interface to set wsc_enable. + + if((ie->app_buflen == 0) && (ie->app_frmtype != IEEE80211_APPIE_FRAME_ASSOC_RESP)) + priv->pmib->wscEntry.wsc_enable = 0; + else if(ie->app_buflen <= 256) + priv->pmib->wscEntry.wsc_enable = 2; //Work as AP + else + return -EINVAL; + + if (ie->app_frmtype == IEEE80211_APPIE_FRAME_BEACON) { + HAPD_MSG("WSC: set beacon IE\n"); + priv->pmib->wscEntry.beacon_ielen = ie->app_buflen; + memcpy((void *)priv->pmib->wscEntry.beacon_ie, ie->app_buf, ie->app_buflen); + } + else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_PROBE_RESP) { + HAPD_MSG("WSC: set probe response IE\n"); + priv->pmib->wscEntry.probe_rsp_ielen = ie->app_buflen; + memcpy((void *)priv->pmib->wscEntry.probe_rsp_ie, ie->app_buf, ie->app_buflen); + } + else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_ASSOC_RESP) { + HAPD_MSG("WSC: set association response IE\n"); + priv->pmib->wscEntry.assoc_ielen = ie->app_buflen; + memcpy((void *)priv->pmib->wscEntry.assoc_ie, ie->app_buf, ie->app_buflen); + } +#ifdef WIFI_WPAS + else if (ie->app_frmtype == IEEE80211_APPIE_FRAME_PROBE_REQ) { + HAPD_MSG("WSC: set probe request IE\n"); + priv->pmib->wscEntry.probe_req_ielen = ie->app_buflen; + memcpy((void *)priv->pmib->wscEntry.probe_req_ie, ie->app_buf, ie->app_buflen); + } +#endif + else + return -EINVAL; + + + HAPD_MSG("rtl_net80211_setappiebuf ---\n"); + return ret; + +} + + +#ifdef WIFI_WPAS + +int rtl_net80211_setoptie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + WPAS_ASSOCIATION_INFO Assoc_Info; + +//Check if WPS IE + UINT8 WSC_IE_OUI[4] = {0x00, 0x50, 0xf2, 0x04}; + int x; + unsigned char *ie = (unsigned char *)wrqu->data.pointer; + + if( ie[0] == _WPS_IE_) + if (!memcmp(ie+2, WSC_IE_OUI, 4)) + { + priv->pmib->wscEntry.assoc_ielen = wrqu->data.length; + memcpy((void *)priv->pmib->wscEntry.assoc_ie, wrqu->data.pointer, wrqu->data.length); + priv->pmib->wscEntry.wsc_enable = 1; + + return 0; + } + + priv->pmib->wscEntry.wsc_enable = 0; + + memset(priv->pmib->dot11RsnIE.rsnie, 0x0, 128); + memcpy(priv->pmib->dot11RsnIE.rsnie, wrqu->data.pointer, wrqu->data.length); + priv->pmib->dot11RsnIE.rsnielen = wrqu->data.length; + + memset((void *)&Assoc_Info, 0, sizeof(struct _WPAS_ASSOCIATION_INFO)); + Assoc_Info.ReqIELen = priv->pmib->dot11RsnIE.rsnie[1]+ 2; + memcpy(Assoc_Info.ReqIE, priv->pmib->dot11RsnIE.rsnie, Assoc_Info.ReqIELen); + //event_indicate_wpas(priv, NULL, WPAS_ASSOC_INFO, (UINT8 *)&Assoc_Info); + + return 0; + +} + +#endif + +int rtl_net80211_setmlme(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct ieee80211req_mlme *mlme = (struct ieee80211req_key *)wrqu->data.pointer; + struct stat_info *pstat = get_stainfo(priv, mlme->im_macaddr); + + int ret = 0; + + HAPD_MSG("rtl_net80211_setmlme +++\n"); + HAPD_MSG("auth_state =%d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" + , mlme->im_op, mlme->im_macaddr[0], mlme->im_macaddr[1], mlme->im_macaddr[2], + mlme->im_macaddr[3], mlme->im_macaddr[4], mlme->im_macaddr[5]); + + //_Eric ???? + + if(mlme->im_op == IEEE80211_MLME_AUTHORIZE) + { + + if (pstat == NULL){ + pstat = alloc_stainfo(priv, mlme->im_macaddr, -1); + if (pstat == NULL) { + printk("Exceed the upper limit of supported clients...\n"); + return -1; + } + init_stainfo(priv, pstat); + pstat->state |= (WIFI_AUTH_SUCCESS | WIFI_ASOC_STATE); + pstat->expire_to = priv->assoc_to; + asoc_list_add(priv, pstat); + } + + HAPD_Process_Set_Port(dev, mlme->im_macaddr ,DOT11_PortStatus_Authorized); + + } + else if(mlme->im_op == IEEE80211_MLME_UNAUTHORIZE) + { + if (pstat == NULL) + return -EINVAL; + + //pstat->state |= WIFI_AUTH_NULL; + + HAPD_Process_Set_Port(dev, mlme->im_macaddr ,DOT11_PortStatus_Unauthorized); + + } + else if(mlme->im_op == IEEE80211_MLME_DISASSOC) + { + if (pstat == NULL) + return -EINVAL; + +#ifdef WIFI_WPAS + + if(OPMODE & WIFI_STATION_STATE) + { + HAPD_MSG("An AP is disconnected by WPAS \n"); + issue_disassoc(priv, mlme->im_macaddr, _RSON_UNSPECIFIED_); + + if (pstat->expire_to > 0) + { + cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); + check_sta_characteristic(priv, pstat, DECREASE); + } + + free_stainfo(priv, pstat); + memset(&priv->pmib->dot11Bss, 0, sizeof(struct bss_desc)); + memset(priv->pmib->dot11StationConfigEntry.dot11Bssid, 0, MACADDRLEN); + memset(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); + priv->pmib->dot11StationConfigEntry.dot11DesiredSSIDLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11DefaultSSID, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID)); + priv->pmib->dot11StationConfigEntry.dot11DefaultSSIDLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan, 0, sizeof(priv->pmib->dot11StationConfigEntry.dot11SSIDtoScan)); + priv->pmib->dot11StationConfigEntry.dot11SSIDtoScanLen = 0; + memset(priv->pmib->dot11StationConfigEntry.dot11DesiredBssid, 0, 6); + + priv->wpas_manual_assoc = 1; //_Eric ?? when to let driver auto-connect ?? + + priv->join_res = STATE_Sta_No_Bss; + //pstat->state &= (~WIFI_ASOC_STATE); + return ret; + } + +#endif + + if (asoc_list_del(priv, pstat)) + { + if (pstat->expire_to > 0) + { + cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); + check_sta_characteristic(priv, pstat, DECREASE); + } + } + + // Need change state back to autehnticated + release_stainfo(priv, pstat); + init_stainfo(priv, pstat); + pstat->state |= WIFI_AUTH_SUCCESS; + pstat->expire_to = priv->assoc_to; + auth_list_add(priv, pstat); + } + else if(mlme->im_op == IEEE80211_MLME_DEAUTH) + { + unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + + if(!memcmp(mlme->im_macaddr, MULTICAST_ADD, 6)) //_Eric ??How to free all stainfo?? + return 0; + + if (pstat == NULL) + return -EINVAL; + + if (asoc_list_del(priv, pstat)) + { + if (pstat->expire_to > 0) + { + cnt_assoc_num(priv, pstat, DECREASE, (char *)__FUNCTION__); + check_sta_characteristic(priv, pstat, DECREASE); + } + } + + //release_stainfo(priv, pstat); + free_stainfo(priv, pstat); + + } +#ifdef WIFI_WPAS + else if(mlme->im_op == IEEE80211_MLME_ASSOC) + { + int ix = 0, found = 0; + + if((OPMODE & WIFI_STATION_STATE) == 0) + { + HAPD_MSG("NOT in Client Mode, can NOT Associate !!!\n"); + return -1; + } + + for(ix = 0 ; ix < priv->site_survey->count_backup ; ix++) //_Eric ?? will bss_backup be cleaned?? -> Not found in codes + { + if(!memcmp(priv->site_survey->bss_backup[ix].bssid , mlme->im_macaddr, 6)) + { + found = 1; + break; + } + } + + if(found == 0) + { + printk("BSSID NOT Found !!\n"); + return -EINVAL; + } + else + ret = rtl_wpas_join(priv, ix); + + if(ret != 0) + printk("rtl_wpas_join Failed !!\n"); + + } +#endif + else + { + HAPD_MSG("unknown auth_state !!!\n"); + return -EINVAL; + } + + HAPD_MSG("rtl_net80211_setmlme ---\n"); + return ret; + + +} + + +int rtl_net80211_setkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct ieee80211req_key *wk = (struct ieee80211req_key *)wrqu->data.pointer; + struct wifi_mib *pmib = priv->pmib; + struct Dot11EncryptKey *pEncryptKey = NULL; + struct stat_info *pstat = NULL; + unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; +#ifdef WIFI_WPAS + unsigned char GROUP_ADD[6]={0x0,0x0,0x0,0x0,0x0,0x0}; +#endif + int cipher =0; + int retVal = 0; + int group_key = 0; + + HAPD_MSG("rtl_net80211_setkey +++\n"); + + + HAPD_MSG("keyid = %d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" + , wk->ik_keyix, wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], + wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5]); + HAPD_MSG("type = 0x%x, flags = 0x%x, keylen = 0x%x \n" + , wk->ik_type, wk->ik_flags, wk->ik_keylen); + + + //check if the interface is down + if (!netif_running(priv->dev)) + { + if(wk->ik_type == IEEE80211_CIPHER_WEP) + { + HAPD_MSG("set WEP Key in driver DOWN\n"); + memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); + return 0; + } + + HAPD_MSG("\nFail: interface not opened\n"); + return 0; + } + + if(!memcmp(wk->ik_macaddr, MULTICAST_ADD, 6)) + group_key = 1; + +#ifdef WIFI_WPAS //_Eric ?? if oxff not group addr in wpas ?? + if(OPMODE & WIFI_STATION_STATE) + if(!memcmp(wk->ik_macaddr, GROUP_ADD, 6)) + group_key = 1; +#endif + + if(wk->ik_type == IEEE80211_CIPHER_WEP) + { + +#ifdef WIFI_WPAS + if(OPMODE & WIFI_STATION_STATE) + if(priv->pmib->dot118021xAuthEntry.dot118021xAlgrthm == 0) + { + memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); + return 0; + } +#endif +#ifdef RTK_NL80211 + HAPD_MSG("set WEP Key for NL80211\n"); + memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[wk->ik_keyix].skey[0], wk->ik_keydata, wk->ik_keylen); +#endif + if(priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) + cipher = (DOT11_ENC_WEP40); + else if(priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) + cipher = (DOT11_ENC_WEP104); + else + return -EINVAL; + } + else if(wk->ik_type == IEEE80211_CIPHER_TKIP) + cipher = (DOT11_ENC_TKIP); + else if(wk->ik_type == IEEE80211_CIPHER_AES_CCM) + cipher = (DOT11_ENC_CCMP); + else + { + HAPD_MSG("unknown encAlg !!!\n"); + return -EINVAL; + } + + //_Eric ?? if call DOT11_Process_Set_Key + //CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, cipher, 0, wk->ik_keydata); + + if(group_key) + { + int set_gkey_to_cam = 0; + HAPD_MSG("set group key !!\n"); + +#ifdef UNIVERSAL_REPEATER + if (IS_VXD_INTERFACE(priv)) + set_gkey_to_cam = 0; + else { + if (IS_ROOT_INTERFACE(priv)) { + if (IS_DRV_OPEN(GET_VXD_PRIV(priv))) + set_gkey_to_cam = 0; + } + } +#endif + +#ifdef MBSSID + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable) + { + // No matter root or vap, don't set key to cam if vap is enabled. + set_gkey_to_cam = 0; + } +#endif + +#ifdef CONFIG_RTK_MESH + //modify by Joule for SECURITY + if (dev == priv->mesh_dev) + { + pmib->dot11sKeysTable.dot11Privacy = cipher; + pEncryptKey = &pmib->dot11sKeysTable.dot11EncryptKey; + pmib->dot11sKeysTable.keyid = (UINT)wk->ik_keyix; + } + else +#endif + { + pmib->dot11GroupKeysTable.dot11Privacy = cipher; + pmib->dot11GroupKeysTable.keyid = (UINT)wk->ik_keyix; + + if (wk->ik_keyix == GKEY_ID_SECOND) + pEncryptKey = &pmib->dot11GroupKeysTable.dot11EncryptKey2; + else + pEncryptKey = &pmib->dot11GroupKeysTable.dot11EncryptKey; + } + + switch(cipher) + { + case DOT11_ENC_TKIP: + set_ttkeylen(pEncryptKey, 16); + set_tmickeylen(pEncryptKey, 8); +#ifdef RTK_NL80211 + if(OPMODE & WIFI_STATION_STATE) + set_tkip_key_for_wpas(pEncryptKey, wk->ik_keydata); + else +#endif + set_tkip_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set TKIP group key! id %X\n", (UINT)wk->ik_keyix); + if (!SWCRYPTO) { + if (set_gkey_to_cam) + { + retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + pmib->dot11GroupKeysTable.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_TKIP<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + pmib->dot11GroupKeysTable.keyInCam = TRUE; + } + } + } + break; + + case DOT11_ENC_WEP40: + set_ttkeylen(pEncryptKey, 5); + set_tmickeylen(pEncryptKey, 0); + set_wep40_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set WEP40 group key!\n"); + if (!SWCRYPTO) { + if (set_gkey_to_cam) + { + retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + pmib->dot11GroupKeysTable.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_WEP40<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + pmib->dot11GroupKeysTable.keyInCam = TRUE; + } + } + } + break; + + case DOT11_ENC_WEP104: + set_ttkeylen(pEncryptKey, 13); + set_tmickeylen(pEncryptKey, 0); + set_wep104_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set WEP104 group key!\n"); + if (!SWCRYPTO) { + if (set_gkey_to_cam) + { + retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + pmib->dot11GroupKeysTable.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_WEP104<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + pmib->dot11GroupKeysTable.keyInCam = TRUE; + } + } + } + break; + + case DOT11_ENC_CCMP: + set_ttkeylen(pEncryptKey, 16); + set_tmickeylen(pEncryptKey, 16); + set_aes_key(pEncryptKey, wk->ik_keydata); + pEncryptKey->dot11RXPN48.val48 = 0; + + HAPD_MSG("going to set CCMP-AES group key!\n"); +#ifdef CONFIG_RTK_MESH + if (dev == priv->mesh_dev) + pmib->dot11sKeysTable.keyInCam = TRUE; // keyInCam means key in driver + else +#endif + if (!SWCRYPTO) { + if (set_gkey_to_cam) + { + retVal = CamDeleteOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + pmib->dot11GroupKeysTable.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, MULTICAST_ADD, wk->ik_keyix, DOT11_ENC_CCMP<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + pmib->dot11GroupKeysTable.keyInCam = TRUE; + } + } + } + break; + + case DOT11_ENC_NONE: + default: + HAPD_MSG("No group encryption key is set!\n"); + set_ttkeylen(pEncryptKey, 0); + set_tmickeylen(pEncryptKey, 0); + break; + } + } + else + { + pstat = get_stainfo(priv, wk->ik_macaddr); + if (pstat == NULL) { + DEBUG_ERR("Set key failed, invalid mac address: %02x%02x%02x%02x%02x%02x\n", + wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], wk->ik_macaddr[3], + wk->ik_macaddr[4], wk->ik_macaddr[5]); + return (-1); + } + + pstat->dot11KeyMapping.dot11Privacy = cipher; + pEncryptKey = &pstat->dot11KeyMapping.dot11EncryptKey; + pstat->keyid = wk->ik_keyix; + +#if defined(__DRAYTEK_OS__) && defined(WDS) + if (pstat->state & WIFI_WDS) + priv->pmib->dot11WdsInfo.wdsPrivacy = cipher; +#endif + +#ifdef RTK_NL80211 //eric-ath + //printk(" +++ pstat->state=0x%x wps_join=%d \n", pstat->state, (pstat->state & WIFI_WPS_JOIN)); + + if(OPMODE & WIFI_STATION_STATE) + if(pstat->state & WIFI_WPS_JOIN) + { + //printk("REMOVE WIFI_WPS_JOIN State !!\n"); + pstat->state &= (~(WIFI_WPS_JOIN)); + } +#endif + + switch(cipher) + { + case DOT11_ENC_TKIP: + set_ttkeylen(pEncryptKey, 16); + set_tmickeylen(pEncryptKey, 8); + +#ifdef RTK_NL80211 + if(OPMODE & WIFI_STATION_STATE) + set_tkip_key_for_wpas(pEncryptKey, wk->ik_keydata); + else +#endif + set_tkip_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set TKIP Unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", + wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], + wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); + if (!SWCRYPTO) { + retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_TKIP<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; + } + else { + if (pstat->aggre_mthd != AGGRE_MTHD_NONE) + pstat->aggre_mthd = AGGRE_MTHD_NONE; + } + } + break; + + case DOT11_ENC_WEP40: + set_ttkeylen(pEncryptKey, 5); + set_tmickeylen(pEncryptKey, 0); + set_wep40_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set WEP40 unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", + wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], + wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); + if (!SWCRYPTO) { + retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_WEP40<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; + } + else { + if (pstat->aggre_mthd != AGGRE_MTHD_NONE) + pstat->aggre_mthd = AGGRE_MTHD_NONE; + } + } + break; + + case DOT11_ENC_WEP104: + set_ttkeylen(pEncryptKey, 13); + set_tmickeylen(pEncryptKey, 0); + set_wep104_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set WEP104 unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", + wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], + wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); + if (!SWCRYPTO) { + retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_WEP104<<2, 0, wk->ik_keydata); + if (retVal) { + priv->pshare->CamEntryOccupied++; + if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; + } + else { + if (pstat->aggre_mthd != AGGRE_MTHD_NONE) + pstat->aggre_mthd = AGGRE_MTHD_NONE; + } + } + break; + + case DOT11_ENC_CCMP: + set_ttkeylen(pEncryptKey, 16); + set_tmickeylen(pEncryptKey, 16); + set_aes_key(pEncryptKey, wk->ik_keydata); + + HAPD_MSG("going to set CCMP-AES unicast key for sta %02X%02X%02X%02X%02X%02X, id=%d\n", + wk->ik_macaddr[0], wk->ik_macaddr[1], wk->ik_macaddr[2], + wk->ik_macaddr[3], wk->ik_macaddr[4], wk->ik_macaddr[5], pstat->keyid); + if (!SWCRYPTO) { + retVal = CamDeleteOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, 0); + if (retVal) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + retVal = CamAddOneEntry(priv, wk->ik_macaddr, wk->ik_keyix, DOT11_ENC_CCMP<<2, 0, wk->ik_keydata); + if (retVal) { + HAPD_MSG("CamAddOneEntry of CCMP OK\n"); + priv->pshare->CamEntryOccupied++; + if (pstat) pstat->dot11KeyMapping.keyInCam = TRUE; + assign_aggre_mthod(priv, pstat); + } + else { + HAPD_MSG("CamAddOneEntry of CCMP FAIL\n"); + if (pstat->aggre_mthd != AGGRE_MTHD_NONE) + pstat->aggre_mthd = AGGRE_MTHD_NONE; + } + } + break; + + case DOT11_ENC_NONE: + default: + DEBUG_ERR("No pairewise encryption key is set!\n"); + set_ttkeylen(pEncryptKey, 0); + set_tmickeylen(pEncryptKey, 0); + break; + } + } + + + HAPD_MSG("rtl_net80211_setkey ---\n"); + + return 0; + + + +} + +int rtl_net80211_delkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + +#ifdef RTK_NL80211 + struct ieee80211req_del_key *wk = (struct ieee80211req_del_key *)wrqu->data.pointer; +#else + struct ieee80211req_del_key *wk = (struct ieee80211req_del_key *)wrqu->name; +#endif + struct stat_info *pstat = NULL; + struct wifi_mib *pmib = priv->pmib; + + unsigned char MULTICAST_ADD[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + int ret = 0; + + //check if the interface is down + if (!netif_running(priv->dev)) + { + HAPD_MSG("\nFail: interface not opened\n"); + return 0; + } + + HAPD_MSG("rtl_net80211_delkey +++ \n"); + HAPD_MSG("keyid = %d, mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" + , wk->idk_keyix, wk->idk_macaddr[0], wk->idk_macaddr[1], wk->idk_macaddr[2], + wk->idk_macaddr[3], wk->idk_macaddr[4], wk->idk_macaddr[5]); + + if(!memcmp(wk->idk_macaddr, "\x00\x00\x00\x00\x00\x00", 6)) + { + HAPD_MSG("reset ALL key !!!!!\n"); + CamResetAllEntry(priv); + } + + if (!memcmp(wk->idk_macaddr, MULTICAST_ADD, 6)) + { + pmib->dot11GroupKeysTable.dot11EncryptKey.dot11TTKeyLen = 0; + pmib->dot11GroupKeysTable.dot11EncryptKey.dot11TMicKeyLen = 0; + + HAPD_MSG("Delete Group Key\n"); + if (CamDeleteOneEntry(priv, MULTICAST_ADD, 1, 0)) + priv->pshare->CamEntryOccupied--; + #if defined(CONFIG_RTL_HW_WAPI_SUPPORT) + if (CamDeleteOneEntry(priv, MULTICAST_ADD, 1, 0)) + priv->pshare->CamEntryOccupied--; + #endif + + } + else + { + pstat = get_stainfo(priv, (UINT8 *)wk->idk_macaddr); + if (pstat == NULL) + return (-1); + + pstat->dot11KeyMapping.dot11EncryptKey.dot11TTKeyLen = 0; + pstat->dot11KeyMapping.dot11EncryptKey.dot11TMicKeyLen = 0; + + HAPD_MSG("Delete Unicast Key\n"); + if (pstat->dot11KeyMapping.keyInCam == TRUE) { + if (CamDeleteOneEntry(priv, (unsigned char *)wk->idk_macaddr, 0, 0)) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + #if defined(CONFIG_RTL_HW_WAPI_SUPPORT) + if (CamDeleteOneEntry(priv, (unsigned char *)wk->idk_macaddr, 0, 0)) { + priv->pshare->CamEntryOccupied--; + if (pstat) pstat->dot11KeyMapping.keyInCam = FALSE; + } + #endif + } + } + + HAPD_MSG("rtl_net80211_delkey --- \n"); + + return ret; + + +} + +int rtl_net80211_getwpaie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct ieee80211req_wpaie *ie = (struct ieee80211req_wpaie *)wrqu->data.pointer; + struct stat_info *pstat = get_stainfo(priv, ie->wpa_macaddr); + int ret = 0; + HAPD_MSG("rtl_net80211_getwpaie +++ \n"); + HAPD_MSG("mac = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", + ie->wpa_macaddr[0], ie->wpa_macaddr[1], ie->wpa_macaddr[2], + ie->wpa_macaddr[3], ie->wpa_macaddr[4], ie->wpa_macaddr[5]); + + if(pstat == NULL) + return -EINVAL; + +#ifndef HAPD_DRV_PSK_WPS + HAPD_MSG("RSNEnabled = %d\n" + "wpa_ie = 0x%02x 0x%02x 0x%02x \n" + "wps_ie = 0x%02x 0x%02x 0x%02x \n" + ,pstat->wpa_sta_info->RSNEnabled, + pstat->wpa_ie[0], pstat->wpa_ie[1], pstat->wpa_ie[2], + pstat->wps_ie[0], pstat->wps_ie[1], pstat->wps_ie[2] + ); +#else + HAPD_MSG("RSNEnabled = %d\n" + "wpa_ie = 0x%02x 0x%02x 0x%02x \n" + ,pstat->wpa_sta_info->RSNEnabled, + pstat->wpa_ie[0], pstat->wpa_ie[1], pstat->wpa_ie[2] + ); +#endif + + if(pstat->wpa_sta_info->RSNEnabled & BIT(0)) + memcpy(ie->wpa_ie, pstat->wpa_ie, pstat->wpa_ie[1]+2); + else if(pstat->wpa_sta_info->RSNEnabled & BIT(1)) + memcpy(ie->rsn_ie, pstat->wpa_ie, pstat->wpa_ie[1]+2); + +#ifndef HAPD_DRV_PSK_WPS + if((priv->pmib->wscEntry.wsc_enable & 2) && (pstat->wps_ie[1])) + memcpy(ie->wps_ie, pstat->wps_ie, pstat->wps_ie[1]+2); +#endif + + HAPD_MSG("rtl_net80211_getwpaie --- \n"); + return ret; + +} + + +#if ((defined(WIFI_HAPD) || defined(RTK_NL80211)) && defined(WDS)) && !defined(HAPD_DRV_PSK_WPS) +int rtl_net80211_wdsaddmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct rtk_wds_config *wds = (struct hapd_wds_info *)wrqu->data.pointer; + int ret = 0; + int num = 0; + + HAPD_MSG("rtl_net80211_wdsaddmac +++ \n"); + + if(wds->wdsEnabled == 0) + goto bad; + if(wds->wdsNum > NUM_WDS) + goto bad; + if( (wds->wdsPrivacy != _NO_PRIVACY_) && (wds->wdsPrivacy != _WEP_40_PRIVACY_) && + (wds->wdsPrivacy != _TKIP_PRIVACY_) && (wds->wdsPrivacy != _CCMP_PRIVACY_) && + (wds->wdsPrivacy != _WEP_104_PRIVACY_)) + goto bad; + + if((wds->wdsPrivacy == _WEP_40_PRIVACY_) && (wds->wdsWepKeyLen != 5)) + goto bad; + if((wds->wdsPrivacy == _WEP_104_PRIVACY_) && (wds->wdsWepKeyLen != 13)) + goto bad; + + priv->pmib->dot11WdsInfo.wdsEnabled = 1; + priv->pmib->dot11WdsInfo.wdsNum = wds->wdsNum; + + for(num=0 ; num < wds->wdsNum; num++) + memcpy(priv->pmib->dot11WdsInfo.entry[num].macAddr, wds->macAddr[num], MACADDRLEN); + + priv->pmib->dot11WdsInfo.wdsPrivacy = wds->wdsPrivacy; + + if((wds->wdsPrivacy == _WEP_40_PRIVACY_)||(wds->wdsPrivacy == _WEP_104_PRIVACY_)) + memcpy(priv->pmib->dot11WdsInfo.wdsWepKey, wds->wdsWepKey, wds->wdsWepKeyLen); + else if((wds->wdsPrivacy == _TKIP_PRIVACY_)||(wds->wdsPrivacy == _CCMP_PRIVACY_)) + hapd_set_wdskey(dev, wds->wdsPskPassPhrase, wds->ssid, wds->wdsNum); + + + HAPD_MSG("rtl_net80211_wdsaddmac --- \n"); + return 0; + +bad: + priv->pmib->dot11WdsInfo.wdsEnabled = 0; + return -EINVAL; + + +} + +int rtl_net80211_wdsdelmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct rtk_wds_config *wds = (struct rtk_wds_config *)wrqu->data.pointer; + HAPD_MSG("rtl_net80211_wdsdelmac +++ \n"); + + priv->pmib->dot11WdsInfo.wdsEnabled = 0; + priv->pmib->dot11WdsInfo.wdsNum = 0; + + HAPD_MSG("rtl_net80211_wdsdelmac --- \n"); + return 0; +} +#endif + + +int rtl_hapd_config(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct rtk_hapd_config *config = (struct rtk_hapd_config *)wrqu->data.pointer; + int size = 0; + + HAPD_MSG("rtl_hapd_config +++\n"); + + priv->pmib->dot11BssType.net_work_type = config->band; + priv->pmib->dot11RFEntry.dot11channel = config->channel; + priv->pmib->dot11StationConfigEntry.dot11BeaconPeriod = config->bcnint; + priv->pmib->dot11StationConfigEntry.dot11DTIMPeriod = config->dtimperiod; + + if(config->stanum <= NUM_STAT) + priv->pmib->dot11StationConfigEntry.supportedStaNum = config->stanum; + else + { + HAPD_MSG("Invalid Station Number!!!\n"); + return -1; + } + + priv->pmib->dot11OperationEntry.dot11RTSThreshold = config->rtsthres; + priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = config->fragthres; + priv->pmib->dot11StationConfigEntry.dot11SupportedRates = config->oprates; + priv->pmib->dot11StationConfigEntry.dot11BasicRates = config->basicrates; + priv->pmib->dot11RFEntry.shortpreamble = config->preamble; + priv->pmib->dot11StationConfigEntry.dot11AclMode = config->aclmode; + priv->pmib->dot11StationConfigEntry.dot11AclNum = config->aclnum; + + size = sizeof(priv->pmib->dot11StationConfigEntry.dot11AclAddr); + memcpy(priv->pmib->dot11StationConfigEntry.dot11AclAddr, config->acladdr, size); + + priv->pmib->dot11OperationEntry.hiddenAP = config->hiddenAP; +#ifdef WIFI_WMM + priv->pmib->dot11QosEntry.dot11QosEnable = config->qos_enable; +#endif + priv->pmib->dot11OperationEntry.expiretime = config->expired_time * 100; // 10ms unit vs 1s unit + priv->pmib->dot11OperationEntry.block_relay = config->block_relay; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = config->shortGI20M; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = config->shortGI40M; + + +//Above are for Hostapd owned configurations +//===================================================== +//Below are for RTK private configurations + + size = sizeof(priv->pmib->dot11RFEntry.pwrlevelCCK_A); + memcpy(priv->pmib->dot11RFEntry.pwrlevelCCK_A, config->pwrlevelCCK_A, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrlevelCCK_B); + memcpy(priv->pmib->dot11RFEntry.pwrlevelCCK_B, config->pwrlevelCCK_B, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A); + memcpy(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A, config->pwrlevelHT40_1S_A, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B); + memcpy(priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B, config->pwrlevelHT40_1S_A, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrdiffHT40_2S); + memcpy(priv->pmib->dot11RFEntry.pwrdiffHT40_2S, config->pwrdiffHT40_2S, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrdiffHT20); + memcpy(priv->pmib->dot11RFEntry.pwrdiffHT20, config->pwrdiffHT20, size); + + size = sizeof(priv->pmib->dot11RFEntry.pwrdiffOFDM); + memcpy(priv->pmib->dot11RFEntry.pwrdiffOFDM, config->pwrdiffOFDM, size); + + priv->pmib->dot11RFEntry.ther = config->ther; + +#ifdef CONFIG_RTL_92D_SUPPORT + priv->pmib->dot11RFEntry.phyBandSelect = config->phyBandSelect; +#endif + + priv->pmib->dot11StationConfigEntry.dot11swcrypto = config->swcrypto; + priv->pmib->dot11StationConfigEntry.dot11RegDomain = config->regdomain; + priv->pmib->dot11StationConfigEntry.autoRate = config->autorate; + priv->pmib->dot11StationConfigEntry.fixedTxRate = config->fixrate; + priv->pmib->dot11StationConfigEntry.protectionDisabled = config->disable_protection; + priv->pmib->dot11StationConfigEntry.olbcDetectDisabled = config->disable_olbc; + priv->pmib->dot11StationConfigEntry.legacySTADeny = config->deny_legacy; + priv->pmib->dot11OperationEntry.opmode = config->opmode; + priv->pmib->dot11nConfigEntry.dot11nUse40M = config->use40M; + priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = config->_2ndchoffset; + priv->pmib->dot11nConfigEntry.dot11nAMPDU = config->ampdu; + priv->pmib->dot11OperationEntry.guest_access = config->guest_access; + + priv->pmib->dot11RFEntry.macPhyMode = config->macPhyMode; + +#ifdef WIFI_11N_2040_COEXIST + priv->pmib->dot11nConfigEntry.dot11nCoexist = config->coexist; +#endif + +#ifdef MBSSID + priv->pmib->miscEntry.vap_enable = config->vap_enable; +#endif + + priv->pshare->rf_ft_var.rssi_dump = config->rssi_dump; + +#ifdef MP_TEST + priv->pshare->rf_ft_var.mp_specific = config->mp_specific; +#endif + +#ifdef HIGH_POWER_EXT_PA + priv->pshare->rf_ft_var.use_ext_pa = config->use_ext_pa; +#endif + + HAPD_MSG("rtl_hapd_config ---\n"); + return 0; +} + + + +#ifdef WIFI_WPAS + +int rtl_wpas_config_2G(struct rtl8192cd_priv *priv) +{ + HAPD_MSG("wpas config wlan 2.4G\n"); + + priv->pmib->dot11BssType.net_work_type = 1 + 2 + 8; + priv->pmib->dot11RFEntry.dot11channel = 11; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; + priv->pmib->dot11StationConfigEntry.autoRate = 1; + priv->pmib->dot11nConfigEntry.dot11nUse40M = 1; + priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; + //priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; + priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pmib->dot11StationConfigEntry.dot11SupportedRates = 0xfff; + priv->pmib->dot11StationConfigEntry.dot11BasicRates = 0xf; + priv->pmib->dot11OperationEntry.wifi_specific = 2; //_Eric ?? + + priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = 2346; + +#ifdef CONFIG_RTL_92D_SUPPORT + priv->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_2G; +#endif + +#ifdef WIFI_WMM + priv->pmib->dot11QosEntry.dot11QosEnable = 1; +#endif + +} + +int rtl_wpas_config_5G(struct rtl8192cd_priv *priv) +{ + printk("wpas config wlan 5G\n"); + + priv->pmib->dot11BssType.net_work_type = 4 + 8; + priv->pmib->dot11RFEntry.dot11channel = 44; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M = 1; + priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M = 1; + priv->pmib->dot11StationConfigEntry.autoRate = 1; + priv->pmib->dot11nConfigEntry.dot11nUse40M = 1; + priv->pmib->dot11nConfigEntry.dot11nAMPDU = 1; + //priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; //_Eric ?? How to judge ?? + priv->pmib->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pmib->dot11StationConfigEntry.dot11SupportedRates = 0xff0; + priv->pmib->dot11StationConfigEntry.dot11BasicRates = 0xff0; + priv->pmib->dot11OperationEntry.wifi_specific = 2; + + priv->pmib->dot11OperationEntry.dot11FragmentationThreshold = 2346; + +#ifdef CONFIG_RTL_92D_SUPPORT + priv->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_5G; +#endif + +#ifdef WIFI_WMM + priv->pmib->dot11QosEntry.dot11QosEnable = 1; +#endif + +} + + +int rtl_wpas_config(struct rtl8192cd_priv *priv, unsigned char bandmode, unsigned char phymode) +{ + HAPD_MSG("wpas config interface: %s\n", priv->dev->name); + + priv->pmib->dot11OperationEntry.opmode = WIFI_STATION_STATE; + + if(bandmode == SINGLEMAC_SINGLEPHY) + { + priv->pmib->dot11RFEntry.macPhyMode = SINGLEMAC_SINGLEPHY; + + if(phymode == PHY_BAND_5G) + rtl_wpas_config_5G(priv); + else if(phymode == PHY_BAND_2G) + rtl_wpas_config_2G(priv); + else + return -1; + + } +#if defined(CUSTOMIZE_WLAN_IF_NAME) + else if(!strcmp(priv->dev->name, ROOT_IFNAME_5G)) +#else + else if(!strcmp(priv->dev->name, "wlan0")) +#endif + { + priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; + rtl_wpas_config_5G(priv); + } +#if defined(CUSTOMIZE_WLAN_IF_NAME) + else if(!strcmp(priv->dev->name, ROOT_IFNAME_2G)) +#else + else if(!strcmp(priv->dev->name, "wlan1")) +#endif + { + priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY; + rtl_wpas_config_2G(priv); + } + else + return -1; + + return 0; + + +} + + +int rtl_wpas_custom(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct rtk_wpas_config *config = (struct rtk_wpas_config *)wrqu->data.pointer; + + int ret = 0; + + switch (config->type) { + case WPAS_CONFIG_MIB: + HAPD_MSG("bandmode %d phymode %d \n", config->bandmode, config->phymode); + if((config->bandmode == SINGLEMAC_SINGLEPHY) || (config->bandmode == DUALMAC_DUALPHY)) + ret = rtl_wpas_config(priv, config->bandmode, config->phymode); + else + return -EINVAL; + break; + case WPAS_CONFIG_WEPKEY: + HAPD_MSG("WPAS_CONFIG_WEPKEY !!! \n"); + CTRL_LEN_CHECK(16,config->wep_keylen); + memcpy(&priv->pmib->dot11DefaultKeysTable.keytype[config->wep_keyidx].skey[0], config->wep_key, config->wep_keylen); + break; + + } + + return ret; + +} +#endif + +static void Construct_RSNIE(struct rtl8192cd_priv *priv, unsigned char *pucOut, int *usOutLen) +{ + DOT11_RSN_IE_HEADER dot11RSNIEHeader = { 0 }; + DOT11_RSN_IE_SUITE dot11RSNGroupSuite; + DOT11_RSN_IE_COUNT_SUITE *pDot11RSNPairwiseSuite = NULL; + DOT11_RSN_IE_COUNT_SUITE *pDot11RSNAuthSuite = NULL; + unsigned short usSuitCount; + unsigned long ulIELength = 0; + unsigned long ulIndex = 0; + unsigned long ulPairwiseLength = 0; + unsigned long ulAuthLength = 0; + unsigned char *pucBlob; + DOT11_RSN_IE_COUNT_SUITE countSuite, authCountSuite; +#ifdef RTL_WPA2 + DOT11_RSN_CAPABILITY dot11RSNCapability = { 0 }; + unsigned long uCipherAlgo = 0; + int bCipherAlgoEnabled = FALSE; + unsigned long uAuthAlgo = 0; + int bAuthAlgoEnabled = FALSE; + unsigned long ulRSNCapabilityLength = 0; +#endif + + *usOutLen = 0; + if ( priv->pmib->dot1180211AuthEntry.dot11WPACipher != 0 ) { + // + // Construct Information Header + // + dot11RSNIEHeader.ElementID = RSN_ELEMENT_ID; + dot11RSNIEHeader.OUI[0] = 0x00; + dot11RSNIEHeader.OUI[1] = 0x50; + dot11RSNIEHeader.OUI[2] = 0xf2; + dot11RSNIEHeader.OUI[3] = 0x01; + dot11RSNIEHeader.Version = cpu_to_le16(RSN_VER1); + ulIELength += sizeof(DOT11_RSN_IE_HEADER); + + // Construct Cipher Suite: + // - Multicast Suite: + memset(&dot11RSNGroupSuite, 0, sizeof dot11RSNGroupSuite); + dot11RSNGroupSuite.OUI[0] = 0x00; + dot11RSNGroupSuite.OUI[1] = 0x50; + dot11RSNGroupSuite.OUI[2] = 0xF2; + dot11RSNGroupSuite.Type = priv->wpa_global_info->MulticastCipher; + ulIELength += sizeof(DOT11_RSN_IE_SUITE); + + // - UnicastSuite + pDot11RSNPairwiseSuite = &countSuite; + memset(pDot11RSNPairwiseSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); + usSuitCount = 0; + +#ifdef RTK_NL80211 + for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipher; ulIndex++) + { + int i = ulIndexwpa_global_info->NumOfUnicastCipher - ulIndex - 1; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipher[i]; + usSuitCount++; + } +#else + for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipher; ulIndex++) + { + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipher[ulIndex]; + usSuitCount++; + } +#endif + + pDot11RSNPairwiseSuite->SuiteCount = cpu_to_le16(usSuitCount); + ulPairwiseLength = sizeof(pDot11RSNPairwiseSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); + ulIELength += ulPairwiseLength; + + // + // Construction of Auth Algo List + // + pDot11RSNAuthSuite = &authCountSuite; + memset(pDot11RSNAuthSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); + usSuitCount = 0; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x50; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xF2; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].Type = DOT11_AuthKeyType_RSN; + usSuitCount++; + + pDot11RSNAuthSuite->SuiteCount = cpu_to_le16(usSuitCount); + ulAuthLength = sizeof(pDot11RSNAuthSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); + ulIELength += ulAuthLength; + + pucBlob = pucOut; + pucBlob += sizeof(DOT11_RSN_IE_HEADER); + memcpy(pucBlob, &dot11RSNGroupSuite, sizeof(DOT11_RSN_IE_SUITE)); + pucBlob += sizeof(DOT11_RSN_IE_SUITE); + memcpy(pucBlob, pDot11RSNPairwiseSuite, ulPairwiseLength); + pucBlob += ulPairwiseLength; + memcpy(pucBlob, pDot11RSNAuthSuite, ulAuthLength); + pucBlob += ulAuthLength; + + *usOutLen = (int)ulIELength; + pucBlob = pucOut; + dot11RSNIEHeader.Length = (unsigned char)ulIELength - 2; //This -2 is to minus elementID and Length in OUI header + memcpy(pucBlob, &dot11RSNIEHeader, sizeof(DOT11_RSN_IE_HEADER)); + } + +#ifdef RTL_WPA2 + if ( priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher != 0 ) { + DOT11_WPA2_IE_HEADER dot11WPA2IEHeader = { 0 }; + ulIELength = 0; + ulIndex = 0; + ulPairwiseLength = 0; + uCipherAlgo = 0; + bCipherAlgoEnabled = FALSE; + ulAuthLength = 0; + uAuthAlgo = 0; + bAuthAlgoEnabled = FALSE; + ulRSNCapabilityLength = 0; + + // + // Construct Information Header + // + dot11WPA2IEHeader.ElementID = WPA2_ELEMENT_ID; + dot11WPA2IEHeader.Version = cpu_to_le16(RSN_VER1); + ulIELength += sizeof(DOT11_WPA2_IE_HEADER); + + // Construct Cipher Suite: + // - Multicast Suite: + // + memset(&dot11RSNGroupSuite, 0, sizeof(dot11RSNGroupSuite)); + dot11RSNGroupSuite.OUI[0] = 0x00; + dot11RSNGroupSuite.OUI[1] = 0x0F; + dot11RSNGroupSuite.OUI[2] = 0xAC; + dot11RSNGroupSuite.Type = priv->wpa_global_info->MulticastCipher;; + ulIELength += sizeof(DOT11_RSN_IE_SUITE); + + // - UnicastSuite + pDot11RSNPairwiseSuite = &countSuite; + memset(pDot11RSNPairwiseSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); + usSuitCount = 0; + +#ifdef RTK_NL80211 + for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipherWPA2; ulIndex++) + { + int i = priv->wpa_global_info->NumOfUnicastCipherWPA2 - ulIndex - 1; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipherWPA2[i]; + usSuitCount++; + } +#else + for (ulIndex=0; ulIndexwpa_global_info->NumOfUnicastCipherWPA2; ulIndex++) + { + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; + pDot11RSNPairwiseSuite->dot11RSNIESuite[usSuitCount].Type = priv->wpa_global_info->UnicastCipherWPA2[ulIndex]; + usSuitCount++; + } +#endif + + pDot11RSNPairwiseSuite->SuiteCount = cpu_to_le16(usSuitCount); + ulPairwiseLength = sizeof(pDot11RSNPairwiseSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); + ulIELength += ulPairwiseLength; + + // + // Construction of Auth Algo List + // + pDot11RSNAuthSuite = &authCountSuite; + memset(pDot11RSNAuthSuite, 0, sizeof(DOT11_RSN_IE_COUNT_SUITE)); + usSuitCount = 0; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[0] = 0x00; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[1] = 0x0F; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].OUI[2] = 0xAC; + pDot11RSNAuthSuite->dot11RSNIESuite[usSuitCount].Type = DOT11_AuthKeyType_RSN; + usSuitCount++; + + pDot11RSNAuthSuite->SuiteCount = cpu_to_le16(usSuitCount); + ulAuthLength = sizeof(pDot11RSNAuthSuite->SuiteCount) + usSuitCount*sizeof(DOT11_RSN_IE_SUITE); + ulIELength += ulAuthLength; + + //--------------------------------------------------------------------------------------------- + // Do not encapsulate capability field to solve TI WPA issue + //--------------------------------------------------------------------------------------------- + + dot11RSNCapability.field.PreAuthentication = 0; + + ulRSNCapabilityLength = sizeof(DOT11_RSN_CAPABILITY); + ulIELength += ulRSNCapabilityLength; + +#if (defined(WIFI_HAPD) & defined(WIFI_WMM)) || (defined(RTK_NL80211) & defined(WIFI_WMM)) //eric-eap + if(QOS_ENABLE){ + /* 4 PTKSA replay counters when using WMM consistent with hostapd code*/ + dot11RSNCapability.field.PtksaReplayCounter = 3; + } +#endif + + pucBlob = pucOut + *usOutLen; + pucBlob += sizeof(DOT11_WPA2_IE_HEADER); + memcpy(pucBlob, &dot11RSNGroupSuite, sizeof(DOT11_RSN_IE_SUITE)); + pucBlob += sizeof(DOT11_RSN_IE_SUITE); + memcpy(pucBlob, pDot11RSNPairwiseSuite, ulPairwiseLength); + pucBlob += ulPairwiseLength; + memcpy(pucBlob, pDot11RSNAuthSuite, ulAuthLength); + pucBlob += ulAuthLength; + memcpy(pucBlob, &dot11RSNCapability, ulRSNCapabilityLength); + + pucBlob = pucOut + *usOutLen; + dot11WPA2IEHeader.Length = (unsigned char)ulIELength - 2; //This -2 is to minus elementID and Length in OUI header + memcpy(pucBlob, &dot11WPA2IEHeader, sizeof(DOT11_WPA2_IE_HEADER)); + *usOutLen = *usOutLen + (int)ulIELength; + } +#endif // RTL_WPA2 + +} + + +static void ToDrv_SetRSNIE(struct rtl8192cd_priv *priv) +{ + struct iw_point wrq; + DOT11_SET_RSNIE Set_Rsnie; + + + debug_out("RSN: Set RSNIE", priv->wpa_global_info->AuthInfoElement.Octet, + priv->wpa_global_info->AuthInfoElement.Length); + + + wrq.pointer = (caddr_t)&Set_Rsnie; + wrq.length = sizeof(DOT11_SET_RSNIE); + Set_Rsnie.EventId = DOT11_EVENT_SET_RSNIE; + Set_Rsnie.IsMoreEvent = FALSE; + Set_Rsnie.Flag = DOT11_Ioctl_Set; + Set_Rsnie.RSNIELen = priv->wpa_global_info->AuthInfoElement.Length; + memcpy(&Set_Rsnie.RSNIE, + priv->wpa_global_info->AuthInfoElement.Octet, + priv->wpa_global_info->AuthInfoElement.Length); + + rtl8192cd_ioctl_priv_daemonreq(priv->dev, &wrq); +} + + +void rsn_init(struct rtl8192cd_priv *priv) +{ + WPA_GLOBAL_INFO *pGblInfo=priv->wpa_global_info; + int i, j, low_cipher=0; + + DEBUG_TRACE; + + HAPD_MSG("rsn_init\n"); + + memset((char *)pGblInfo, '\0', sizeof(WPA_GLOBAL_INFO)); + + if (priv->pmib->dot1180211AuthEntry.dot11WPACipher) { + for (i=0, j=0; i<_WEP_104_PRIVACY_; i++) { + if (priv->pmib->dot1180211AuthEntry.dot11WPACipher & (1<UnicastCipher[j] = i+1; + if (low_cipher == 0) + low_cipher = pGblInfo->UnicastCipher[j]; + else { + if (low_cipher == _WEP_104_PRIVACY_ && + pGblInfo->UnicastCipher[j] == _WEP_40_PRIVACY_) + low_cipher = pGblInfo->UnicastCipher[j]; + else if (low_cipher == _TKIP_PRIVACY_ && + (pGblInfo->UnicastCipher[j] == _WEP_40_PRIVACY_ || + pGblInfo->UnicastCipher[j] == _WEP_104_PRIVACY_)) + low_cipher = pGblInfo->UnicastCipher[j]; + else if (low_cipher == _CCMP_PRIVACY_) + low_cipher = pGblInfo->UnicastCipher[j]; + } + if (++j >= MAX_UNICAST_CIPHER) + break; + } + } + pGblInfo->NumOfUnicastCipher = j; + } + +#ifdef RTL_WPA2 + if (priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher) { + for (i=0, j=0; i<_WEP_104_PRIVACY_; i++) { + if (priv->pmib->dot1180211AuthEntry.dot11WPA2Cipher & (1<UnicastCipherWPA2[j] = i+1; + if (low_cipher == 0) + low_cipher = pGblInfo->UnicastCipherWPA2[j]; + else { + if (low_cipher == _WEP_104_PRIVACY_ && + pGblInfo->UnicastCipherWPA2[j] == _WEP_40_PRIVACY_) + low_cipher = pGblInfo->UnicastCipherWPA2[j]; + else if (low_cipher == _TKIP_PRIVACY_ && + (pGblInfo->UnicastCipherWPA2[j] == _WEP_40_PRIVACY_ || + pGblInfo->UnicastCipherWPA2[j] == _WEP_104_PRIVACY_)) + low_cipher = pGblInfo->UnicastCipherWPA2[j]; + else if (low_cipher == _CCMP_PRIVACY_) + low_cipher = pGblInfo->UnicastCipherWPA2[j]; + } + if (++j >= MAX_UNICAST_CIPHER) + break; + } + } + pGblInfo->NumOfUnicastCipherWPA2= j; + } +#endif + + pGblInfo->MulticastCipher = low_cipher; + + HAPD_MSG("RSN: WPA unicast cipher= "); + for (i=0; iNumOfUnicastCipher; i++) + HAPD_MSG("%x ", pGblInfo->UnicastCipher[i]); + HAPD_MSG("\n"); + +#ifdef RTL_WPA2 + HAPD_MSG("RSN: WPA2 unicast cipher= "); + for (i=0; iNumOfUnicastCipherWPA2; i++) + HAPD_MSG("%x ", pGblInfo->UnicastCipherWPA2[i]); + HAPD_MSG("\n"); +#endif + + HAPD_MSG("RSN: multicast cipher= %x\n", pGblInfo->MulticastCipher); + + + pGblInfo->AuthInfoElement.Octet = pGblInfo->AuthInfoBuf; + + Construct_RSNIE(priv, pGblInfo->AuthInfoElement.Octet, + &pGblInfo->AuthInfoElement.Length); + + ToDrv_SetRSNIE(priv); +} + +#endif //WIFI_HAPD diff --git a/package/kernel/rtl8192cd/8192cd_net80211.h b/package/kernel/rtl8192cd/8192cd_net80211.h index c871ce4f937..f4e3bae8f9a 100644 --- a/package/kernel/rtl8192cd/8192cd_net80211.h +++ b/package/kernel/rtl8192cd/8192cd_net80211.h @@ -1,36 +1,36 @@ -/* - * Header file for Net80211-compatible handling routines - * - * - * - * Copyright (c) 2010 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -#ifndef _8192CD_NET80211_H_ -#define _8192CD_NET80211_H_ - - -#define MAX_CONFIG_FILE_SIZE (20*1024) // for 8192, added to 20k -#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k - - - int rtl_net80211_setparam(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_setappiebuf(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_setmlme(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_setkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_delkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_wdsaddmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_wdsdelmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_net80211_getwpaie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - int rtl_hapd_config(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); - void rsn_init(struct rtl8192cd_priv *priv); -#if defined(RTK_NL80211) - int rtl_wpas_join(struct rtl8192cd_priv *priv, int bss_num); -#endif - -#endif +/* + * Header file for Net80211-compatible handling routines + * + * + * + * Copyright (c) 2010 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +#ifndef _8192CD_NET80211_H_ +#define _8192CD_NET80211_H_ + + +#define MAX_CONFIG_FILE_SIZE (20*1024) // for 8192, added to 20k +#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k + + + int rtl_net80211_setparam(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_setappiebuf(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_setmlme(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_setkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_delkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_wdsaddmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_wdsdelmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_net80211_getwpaie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + int rtl_hapd_config(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); + void rsn_init(struct rtl8192cd_priv *priv); +#if defined(RTK_NL80211) + int rtl_wpas_join(struct rtl8192cd_priv *priv, int bss_num); +#endif + +#endif diff --git a/package/kernel/rtl8192cd/8192cd_osdep.c b/package/kernel/rtl8192cd/8192cd_osdep.c index 48331a14fd7..8ea19ef07bf 100644 --- a/package/kernel/rtl8192cd/8192cd_osdep.c +++ b/package/kernel/rtl8192cd/8192cd_osdep.c @@ -192,9 +192,10 @@ u32 if_priv_stactrl[NUM_WLAN_IFACE]; #include #endif #endif + +#ifdef BR_SHORTCUT #if defined(CONFIG_WIRELESS_LAN_MODULE) && !defined(NOT_RTK_BSP) extern int (*wirelessnet_hook)(void); -#ifdef BR_SHORTCUT extern struct net_device* (*wirelessnet_hook_shortcut)(unsigned char *da); #endif #ifdef PERF_DUMP @@ -14079,6 +14080,9 @@ void rtl8192cd_deinit_one(struct rtl8192cd_priv *priv) #ifdef MBSSID struct rtl8192cd_priv *vap_priv = NULL; #endif + + printk(KERN_ERR "Entering rtl8192cd_deinit_one()\n"); + if (NULL == priv) { panic_printk("%s: priv should NOT be a NULL pointer!\n", __func__); return; @@ -14928,18 +14932,18 @@ int MDL_INIT __rtl8192cd_init(unsigned long base_addr) //------------------------------------ #endif -#if defined(CONFIG_WIRELESS_LAN_MODULE) && !defined(NOT_RTK_BSP) -//// wirelessnet_hook = GetCpuCanSuspend; #ifdef BR_SHORTCUT -//// wirelessnet_hook_shortcut = get_shortcut_dev; +#if defined(CONFIG_WIRELESS_LAN_MODULE) && !defined(NOT_RTK_BSP) + wirelessnet_hook = GetCpuCanSuspend; + wirelessnet_hook_shortcut = get_shortcut_dev; #endif #ifdef PERF_DUMP Fn_rtl8651_romeperfEnterPoint = rtl8651_romeperfEnterPoint; Fn_rtl8651_romeperfExitPoint = rtl8651_romeperfExitPoint; #endif #ifdef CONFIG_RTL8190_PRIV_SKB -//// wirelessnet_hook_is_priv_buf = is_rtl8190_priv_buf; -//// wirelessnet_hook_free_priv_buf = free_rtl8190_priv_buf; + wirelessnet_hook_is_priv_buf = is_rtl8190_priv_buf; + wirelessnet_hook_free_priv_buf = free_rtl8190_priv_buf; #endif #endif // CONFIG_WIRELESS_LAN_MODULE && !NOT_RTK_BSP #endif // __KERNEL__ @@ -15205,18 +15209,18 @@ void MDL_EXIT rtl8192cd_exit (void) misc_deregister(&cma_dev_misc); #endif -#if defined(CONFIG_WIRELESS_LAN_MODULE) && !defined(NOT_RTK_BSP) -//// wirelessnet_hook = NULL; #ifdef BR_SHORTCUT -//// wirelessnet_hook_shortcut = NULL; +#if defined(CONFIG_WIRELESS_LAN_MODULE) && !defined(NOT_RTK_BSP) + wirelessnet_hook = NULL; + wirelessnet_hook_shortcut = NULL; #endif #ifdef PERF_DUMP Fn_rtl8651_romeperfEnterPoint = NULL; Fn_rtl8651_romeperfExitPoint = NULL; #endif #ifdef CONFIG_RTL8190_PRIV_SKB -//// wirelessnet_hook_is_priv_buf = NULL; -//// wirelessnet_hook_free_priv_buf = NULL; + wirelessnet_hook_is_priv_buf = NULL; + wirelessnet_hook_free_priv_buf = NULL; #endif #endif // CONFIG_WIRELESS_LAN_MODULE && !NOT_RTK_BSP diff --git a/package/kernel/rtl8192cd/8192cd_p2p.c b/package/kernel/rtl8192cd/8192cd_p2p.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_p2p.h b/package/kernel/rtl8192cd/8192cd_p2p.h old mode 100755 new mode 100644 index 86757d5faf1..1ab0f8b9005 --- a/package/kernel/rtl8192cd/8192cd_p2p.h +++ b/package/kernel/rtl8192cd/8192cd_p2p.h @@ -1,709 +1,709 @@ -/* - * Header file define some p2p struct define inline functions - * - * $Id: 8192cd_p2p.h,v 1.2 2010/12/21 - * - * Copyright (c) 2010 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _8192CD_P2P_H_ -#define _8192CD_P2P_H_ - -#include "./8192cd_cfg.h" -#include "./8192cd.h" -#if defined(P2P_SUPPORT) && defined(CONFIG_OPENWRT_SDK) -#include -#endif - -//#define P2PMODE ((GET_MIB(priv))->p2p_mib.p2p_role) -//#define P2P_STATE ((GET_MIB(priv))->p2p_mib.p2p_state) -#define P2P_EVENT_INDICATE (priv->p2pPtr->p2p_event_indiate) -#define P2P_PRE_MODE (priv->p2pPtr->p2p_pre_role) -#define P2P_DISCOVERY (priv->p2pPtr->p2p_on_discovery) -//#include "./wps/wsc.h" -/*============== will redeclare with wsc.h ==================*/ - - -#define P2P_WILDCARD_SSID_LEN 7 -#define P2P_IE_ID 221 - -#define MAC_LEN 6 -#define UUID_LEN 16 -#define MAX_MANUFACT_LEN 64 -#define MAX_MODEL_NAME_LEN 32 -#define MAX_MODEL_NUM_LEN 32 -#define MAX_SERIAL_NUM_LEN 32 -#define MAX_DEVICE_NAME_LEN 32 - -#define WSC_IE_ID 221 -#define WSC_VER 0x10 -#define TAG_SIMPLE_CONFIG_STATE 0x1044 -#define TAG_RESPONSE_TYPE2 0x103B -#define TAG_UUID_E 0x1047 -#define TAG_MANUFACTURER 0x1021 -#define TAG_MODEL_NAME 0x1023 -#define TAG_MODEL_NUMBER 0x1024 -#define TAG_SERIAL_NUM 0x1042 -#define TAG_PRIMARY_DEVICE_TYPE 0x1054 -#define TAG_DEVICE_NAME 0x1011 -#define TAG_CONFIG_METHODS 0x1008 -#define TAG_VERSION 0x104A -#define TAG_DEVICE_PASSWORD_ID 0x1012 -#define TAG_SEC_DEVICE_TYPE_LIST 0x1055 - -#define WFA_OUI_LEN 3 -#define WFA_OUI_PLUS_TYPE_LEN 4 -#define WFD_OUI_PLUS_TYPE_LEN 4 - -#define MAX_NOA_DESC_MUN 6 -#define MAX_P2P_CLIENT_MUN 5 -#define CLIENT_MODE_WAIT_TIME 30 -#define WSC_MODE_WAIT_TIME 30 - -#define P2P_CLIENT_ASSOC_EXPIRE 120 - -#define P2P_device_category_id_AP 6 -#define P2P_device_category_id_STA 1 -#define P2P_device_sub_category_id 1 - - - -/*for P2P IE attribute ID0 use*/ -enum p2p_status_code { - P2P_SC_SUCCESS = 0, - P2P_SC_FAIL_INFO_CURRENTLY_UNAVAILABLE = 1, - P2P_SC_FAIL_INCOMPATIBLE_PARAMS = 2, - P2P_SC_FAIL_LIMIT_REACHED = 3, - P2P_SC_FAIL_INVALID_PARAMS = 4, - P2P_SC_FAIL_UNABLE_TO_ACCOMMODATE = 5, - P2P_SC_FAIL_PREV_PROTOCOL_ERROR = 6, - P2P_SC_FAIL_NO_COMMON_CHANNELS = 7, - P2P_SC_FAIL_UNKNOWN_GROUP = 8, - P2P_SC_FAIL_BOTH_GO_INTENT_15 = 9, - P2P_SC_FAIL_INCOMPATIBLE_PROV_METHOD = 10, - P2P_SC_FAIL_REJECTED_BY_USER = 11, -}; - -/*for P2P IE attribute ID1 use*/ -enum p2p_minor_reason{ - minor_case1 =1, - minor_case2 =2, - minor_case3 =3, - minor_case4 =4 -}; - - -/* P2P public action frames ; - these type frames no need assoc we must process*/ -enum p2p_public_action_frame { - P2P_GO_NEG_REQ = 0, - P2P_GO_NEG_RESP = 1, - P2P_GO_NEG_CONF = 2, - P2P_INVITATION_REQ = 3, - P2P_INVITATION_RESP = 4, - P2P_DEV_DISC_REQ = 5, - P2P_DEV_DISC_RESP = 6, - P2P_PROV_DISC_REQ = 7, - P2P_PROV_DISC_RSP = 8 -}; - -/* P2P action frames ,we process these type frames after assoc*/ -enum p2p_action_frame{ - P2P_NOA = 0, - P2P_PRESENCE_REQ = 1, - P2P_PRESENCE_RSP = 2, - P2P_GO_DISCOVERY = 3 - /*4-255 reserved*/ -}; - -enum { - RSP_TYPE_ENR, - RSP_TYPE_ENR_1X, - RSP_TYPE_REG, - RSP_TYPE_AP -}; - -// wsc passwd ID -enum { - PASS_ID_DEFAULT, // 0 - PASS_ID_USER, // 1 - PASS_ID_MACHINE, // 2 - PASS_ID_REKEY, // 3 - PASS_ID_PB, // 4 - PASS_ID_REG, // 5 - PASS_ID_RESERVED // 6 -}; - - // need sync with wscd -enum { - GO_WPS_SUCCESS = 1, - GO_WPS_FAIL = 2 -}; - - - -enum { - CONFIG_METHOD_ETH=0x2, - CONFIG_METHOD_PIN=0x4, // label(PIN) - CONFIG_METHOD_DISPLAY=0x8 ,// (PISPLAY) - CONFIG_METHOD_PBC=0x80, - CONFIG_METHOD_KEYPAD=0x100, - /*add for wps2.x*/ - CONFIG_METHOD_VIRTUAL_PBC=0x280 , - CONFIG_METHOD_PHYSICAL_PBC=0x480, - CONFIG_METHOD_VIRTUAL_PIN=0x2008, - CONFIG_METHOD_PHYSICAL_PIN=0x4008 -}; - -enum p2p_role_s { - R_P2P_GO =1 , - R_P2P_DEVICE = 2, - R_P2P_CLIENT =3 -}; - - -/*note , 20140325 , cfg p2p - -under PROPERTY_P2P case, P2P_PRE_CLIENT,P2P_PRE_GO ,used for change the mode if FORMATION FAILURE - -under CFG80211_P2P case, seem don't care P2P_PRE_CLIENT,P2P_PRE_GO - - -*/ -enum p2p_role_more{ - P2P_DEVICE=1, - P2P_PRE_CLIENT=2, - P2P_CLIENT=3, - P2P_PRE_GO=4, // after GO nego , we are GO and proceed WSC exchange - P2P_TMP_GO=5 // after GO nego , we are GO and proceed WSC exchange is done -}; - -// need sync with web server utility.h -enum { - P2P_S_IDLE = 0, /* between state and state */ - - P2P_S_LISTEN , /*1 listen state */ - - P2P_S_SCAN , /*2 Scan state */ - - P2P_S_SEARCH , /*3 Search state*/ - - // 4~14 ; show status 4 in web page - P2P_S_PROVI_TX_REQ , /*4 send provision req*/ - P2P_S_PROVI_WAIT_RSP , /*5 wait provision rsp*/ - P2P_S_PROVI_RX_RSP , /*6 rx provision rsp*/ - - P2P_S_PROVI_RX_REQ , /*7 received provision req*/ - P2P_S_PROVI_TX_RSP , /*8 send provision rsp*/ - - - P2P_S_NEGO_TX_REQ , /*9 send NEGO req*/ - P2P_S_NEGO_WAIT_RSP , /*10 waiting for NEGO rsp*/ - P2P_S_NEGO_TX_CONF , /*11 send NEGO confirm*/ - - - P2P_S_NEGO_RX_REQ , /*12 rx NEGO req */ - P2P_S_NEGO_TX_RSP , /*13 send NEGO rsp */ - P2P_S_NEGO_WAIT_CONF , /*14 wait NEGO conf */ - - // 15~16 ; show status 5 in web page - P2P_S_CLIENT_CONNECTED_DHCPC , /*15 p2p client Rdy connected */ - P2P_S_CLIENT_CONNECTED_DHCPC_done, /*16 p2p client Rdy connected */ - - // 17~18 ; show status 6 in web page - P2P_S_preGO2GO_DHCPD , /*17 GO not start dhcpd yet */ - P2P_S_preGO2GO_DHCPD_done, /*18 GO rdy start dhcpd*/ - - P2P_S_back2dev /*exceed 20 seconds p2p client can't connected*/ -}; - - - -enum { - P2P_EVENT_RX_PROVI_REQ = 1 /* received provision req*/ -}; - - -enum { - WPS_MODE_NO_CHANGE=0, - MODE_AP_UNCONFIG=1, // AP unconfigured (enrollee) - MODE_CLIENT_UNCONFIG=2, // client unconfigured (enrollee) - MODE_CLIENT_CONFIG=3, // client configured (registrar) - MODE_AP_PROXY=4, // AP configured (proxy) - MODE_AP_PROXY_REGISTRAR=5, // AP configured (proxy and registrar) - MODE_CLIENT_UNCONFIG_REGISTRAR=6 // client unconfigured (registrar) -}; - -enum { - P2P_PIN_METHOD = 1, - P2P_PBC_METHOD = 2 -}; - -enum { - USE_TARGET_PIN = 1, - USE_MY_PIN = 2 -}; - -enum { - P2P_GO_PS_NONE, - P2P_GO_PS_OPPPS, - P2P_GO_PS_NP_NOA, - P2P_GO_PS_CONT_NOA, - P2P_GO_PS_NOA -}; - - -/*==================================================================*/ - -/*=====================commu with web UI start===========================*/ - -/* Any changed here MUST sync with web server utility.h */ -struct p2p_state_event{ - unsigned char p2p_status; - unsigned char p2p_event; - unsigned short p2p_wsc_method; - unsigned char p2p_role; -}; - -struct __p2p_wsc_confirm -{ - unsigned char dev_address[MAC_LEN]; - unsigned short wsc_config_method; - unsigned char pincode[9]; - -}; -/*=====================commu with web UI end===========================*/ - - - - -/*reg_class - Regulatory class (IEEE 802.11-2007, Annex J) - P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */ - -#define P2P_MAX_REG_CLASSES 10 - -/*P2P_MAX_REG_CLASS_CHANNELS - - Maximum number of channels per regulatory class */ -#define P2P_MAX_REG_CLASS_CHANNELS 20 - - -struct p2p_reg_class { - - /*reg_class - Regulatory class (IEEE 802.11-2007, Annex J)*/ - unsigned char reg_class; - - /* channels - Number of channel entries in use */ - unsigned char channel_mun; - - /* channel - Supported channels */ - unsigned char channel[P2P_MAX_REG_CLASS_CHANNELS]; - -}; - -/* struct p2p_channels - List of supported channels */ -struct p2p_channels { - unsigned short Id11_len; - char country[3]; - - /* reg_classes - Number of reg_class entries in use - corresponding to table 25(page 89) number of channels*/ - unsigned char reg_class_mun; - - /* struct p2p_reg_class - Supported regulatory class*/ - struct p2p_reg_class reg_class[P2P_MAX_REG_CLASSES]; - -}; - -/*============== will redeclare with wsc.h ==================*/ - - - - -/*P2P TAG*/ -#define TAG_STATUE 0 -#define TAG_MINOR_RES_CODE 1 -#define TAG_P2P_CAPABILITY 2 -#define TAG_DEVICE_ID 3 -#define TAG_GROUP_OWNER_INTENT 4 -#define TAG_CONFIG_TIMEOUT 5 -#define TAG_LISTEN_CHANNEL 6 -#define TAG_P2P_GROUP_BSSID 7 -#define TAG_EXT_LISTEN_TIMING 8 -#define TAG_INTEN_P2P_INTERFACE_ADDR 9 -#define TAG_P2P_MANAGEABILITY 10 -#define TAG_CHANNEL_LIST 11 -#define TAG_NOTICE_OF_ABSENCE 12 -#define TAG_P2P_DEVICE_INFO 13 -#define TAG_P2P_GROUP_INFO 14 -#define TAG_P2P_GROUP_ID 15 -#define TAG_P2P_INTERFACE 16 -#define TAG_OPERATION_CHANNEL 17 -#define TAG_INVITATION_FLAGS 18 - - - - -/* for P2P Capability attr*/ -/*dev cap*/ -#define SUPPORT_P2P_INVITATION (BIT(5)) -#define CLIENT_DISCOVERY (BIT(1)) - -/*group cap*/ -#define GCAP_GO (BIT(0)) -#define GCAP_PRESISTENT_GO (BIT(1)) -#define GCAP_GROUP_LIMIT (BIT(2)) -#define GCAP_IBSS_DIST (BIT(3)) -#define GCAP_GO_FORMATION (BIT(6)) - -struct provision_comm -{ - unsigned char dev_address[MAC_LEN]; - unsigned short wsc_config_method; - unsigned char channel; - -}; - - -#define MAX_SEC_DEV_TYPE 3 -struct device_info_s -{ - unsigned char dev_address[6] ; // - unsigned short config_method; /*which wsc config method can provided*/ - unsigned char pri_dev_type[8]; /*primary device type*/ - unsigned char sdv_mun; - unsigned char sec_dev_type[MAX_SEC_DEV_TYPE][8]; /*we keep 3 sets (second device type)*/ - char devname[33]; - -}; - - -/* need sync with wsc.h */ -typedef struct _DOT11_P2P_INDICATE_WSC{ - unsigned char EventId; - unsigned char IsMoreEvent; - - unsigned char modeSwitch ; - char network_key[65] ; - char gossid[33] ; - unsigned char trigger_method ; - - unsigned char whosPINuse ; - char PINCode[9] ; - unsigned char requestor; - char interfacename[16]; -}DOT11_P2P_INDICATE_WSC; - - - -typedef struct p2p_device_peer { - unsigned char inuse; - unsigned char dev_addr[6]; - - unsigned char dialog_token; - - int role; /* p2p is which role */ - - /*attribute ID 0 Status*/ - int status; /* enum p2p_status_code */ - - /*attribute ID 2*/ - unsigned char dev_capab; /* device capability*/ - unsigned char group_capab; /* group capability*/ - - /*attribute ID3 device ID*/ - //unsigned char device_address_to_find[6] ; - - /*attribute ID4 GO intent value*/ - unsigned char intent_value; - unsigned char TieBreak; - - /*attribute ID5 configure timeout*/ - unsigned char go_config_timeout; - unsigned char client_config_timeout; - - /*attribute ID6 configure timeout*/ - int operating_class; // frequency band - int listen_channle; // - - /*attribute ID7 group BSSID*/ - unsigned char go_bssid[6]; - - /*attribute ID8 extended listen timing*/ - unsigned short avail_period; - unsigned short avail_interval; - - /*attribute ID9 intented p2p interface address*/ - unsigned char p2p_interface_address[6] ; - - /*attribute ID10 manageability*/ - unsigned char manageability ; // bit(0)|bit(1)|bit(2)| - - /*attribute ID11 channel list*/ - /* Country code to use in P2P operations */ - - struct p2p_channels channels_list; - - - /*attribute ID 12 Notice of Absence*/ - unsigned char noa_index ; /* noa index */ - unsigned char noa_ct_oops ; /* noa ctwindows and oops */ - unsigned char noa_desc_count ; /* noa count of noa descriptor*/ - unsigned char noa_desc[2][13] ; /* noa descriptor ; a go max has two desc simultaneously*/ - - /*attribute ID 13 device info*/ - struct device_info_s peer_device_info; - - /*attribute ID 14 group info ; more Id14's attr can represent at ID13 */ - //unsigned short p2p_interface_address[6] ; // represent at ID9 - - /*attribute ID 15 group ID */ - unsigned char group_bssid[6]; - unsigned char group_ssid[33]; - unsigned char group_ssid_len; - - /*attribute ID 16 group ID */ - unsigned char interface_addr_num; - unsigned char p2p_interface_add_list[2][6] ; - - /*attribute ID 17 operating channel */ - unsigned char op_country[4]; - unsigned char op_class; - unsigned char op_channel; - - /*attribute ID 18 invitation flags*/ - unsigned char invitation_flag; - - - /*wsc IE */ - unsigned short wsc_config_method; - unsigned short device_pass_id; - - -}P2P_DEV_T, *P2P_DEV_Tp; - - -/* - in discovery phase , we can just recored the necessity info -*/ -struct assoc_peer -{ - - unsigned char inuse; - // ID2 - unsigned char dev_cap; - unsigned char group_cap; - - // ID13 - struct device_info_s devInfo; - unsigned char if_addr[6]; -}; - -struct noa_desc -{ - unsigned char count; - unsigned int duration; - unsigned int interval; - unsigned int starttime; -}; - -// ID12 -struct noa_list -{ - unsigned char index; - unsigned char CTWindow_OppPs; /*bit7 OppPS bit(0-6) CTWindows*/ - struct noa_desc noa_descs; - unsigned int go_ps_type; - unsigned int noa_counter; - unsigned int p2p_txpause_flag; -}; - -#define MAX_P2P_IE_LEN 128 -struct p2p_context { - struct timer_list p2p_search_timer_t; - struct timer_list p2p_find_timer_t; - - //unsigned int p2p_type; rename to role - //int p2p_role; - int p2p_state; - int p2p_on_discovery; - int p2p_event_indiate; - u8 use_6m_rate; - - /*=========remain on channel related========*/ - int pre_p2p_role; // keep pre p2p role 20140306 add - int pre_p2p_state; // keep pre p2p role 20140306 add - -#if defined(P2P_SUPPORT) && defined(CONFIG_OPENWRT_SDK) - /*=========remain on channel related========*/ - struct timer_list remain_on_ch_timer; - u8 restore_channel; - struct ieee80211_channel remain_on_ch_channel; - u64 remain_on_ch_cookie; - - /*=========remain on channel related========*/ - struct timer_list scan_deny_timer; - u64 send_action_id; - //struct cfg80211_wifidirect_info cfg80211_wdinfo; -#endif - //unsigned int Status; - - unsigned char wsc_ie_rsp[MAX_P2P_IE_LEN]; // full size maybe 32 + 8 + 8 - unsigned char wsc_ie_rsp_mun; // use for action frame (eg nego rsp) - - unsigned char wsc_ie_req[MAX_P2P_IE_LEN]; // full size maybe 32 + 8 + 8 - unsigned char wsc_ie_req_mun; // use for action frame (eg nego rsp) - - unsigned char p2p_probe_req_ie[MAX_P2P_IE_LEN]; - unsigned char p2p_probe_req_ie_len; - - unsigned char p2p_probe_rsp_ie[MAX_P2P_IE_LEN]; - unsigned char p2p_probe_rsp_ie_len; - - unsigned char p2p_beacon_ie[MAX_P2P_IE_LEN]; - unsigned char p2p_beacon_ie_len; - - unsigned char p2p_assocReq_ie[MAX_P2P_IE_LEN]; - unsigned char p2p_assocReq_ie_len; - - unsigned char p2p_assoc_RspIe[MAX_P2P_IE_LEN]; - unsigned char p2p_assoc_RspIe_len; - - unsigned char p2p_disass_ie[MAX_P2P_IE_LEN]; - unsigned char p2p_disass_ie_len; - - unsigned char wfd_probe_req_ie[MAX_P2P_IE_LEN]; - unsigned char wfd_probe_req_ie_len; - - - unsigned char wait2listenState; - - - unsigned char collect_type; // 1:from beacon ; 2:from probe_rsp - - /*when i am GO and some p2p client assoc to me ; recored here*/ - struct assoc_peer assocPeers[MAX_P2P_CLIENT_MUN]; - - /*when i am GO and some p2p dev probe_req me */ - unsigned char probe_rps_to_p2p_dev; - - /*when i am client record noa from beacon */ - struct noa_list noa_list_t; - - - int pre_client_timeout; - int pre_go_timeout; - - /*for handle client discovery req/rsp , GO discovery req related */ - unsigned char dev_dis_req_dialog_token; - unsigned char dev_dis_rsp_dialog_token; - // unsigned char provision_rx_dialog_token; - - /*for handle provision discovery related process*/ - unsigned char presence_tx_dialog_token; - unsigned char presence_rx_dialog_token; - - /*for handle provision discovery related process*/ - unsigned char provision_tx_dialog_token; - unsigned char provision_rx_dialog_token; - - /*for handle active send provision req and Nego Req*/ - unsigned char target_device_role; - unsigned char target_device_ssid[33]; - unsigned char target_device_addr[MAC_LEN]; - unsigned char target_device_channel; - unsigned short wsc_method_to_target_dev; - unsigned short dev_passwd_to_tar_dev; - unsigned char target_dev_pin_code[9]; - unsigned char wsc_method_match; - /* when receive provision req , record target dev wsc method*/ - unsigned short wsc_method_from_target_dev; - unsigned char passivemode_pbc_trigger_flag; - - /*for handle action frames*/ - unsigned char provision_req_timeout; - - unsigned char requestor; // i am requestor or not - - - - /*for handle go-nego related process*/ - unsigned char go_nego_tx_dialog_token; // my req token - unsigned char go_nego_rx_dialog_token; // target dev's req token - - unsigned char go_nego_on_going; // for lock this GO nego process - unsigned char go_nego_on_going_timeout; // for lock this GO nego process - - /*for handle action packets ; when receive go-nego req*/ - int wait_nego_conf_timeout; - - /*my GO Negotiation data */ - unsigned char my_GO_ssid[33]; /*should be DRIECT-xy+(0~23 assic)*/ - unsigned char my_GO_ssid_len; - unsigned char ssid_random[3]; // DIRETC-xy ; the xy - unsigned char go_PSK[65]; - - struct p2p_channels my_channel_list; - - /*my P2P capability*/ - - /*device capa 0~5*/ - unsigned char service_discover; - unsigned char p2p_client_discoverability; - unsigned char concurrent_operations; - unsigned char p2p_infrastructure_managed; - unsigned char p2p_device_limit; - unsigned char p2p_invitation; - /*group capa 0~6*/ - unsigned char p2p_go_role; - unsigned char persistent_go; - unsigned char p2p_go_limit; - unsigned char intra_bss_distribution; - unsigned char cross_conect; - unsigned char persistent_reconnect; - unsigned char go_formation; - - - unsigned char wps_is_ongoing; - - /*p2p discovery phase need related data ; no use now*/ - unsigned char spec_find_dev_addr[6]; /*the assigned p2p device address be find in probe_req */ - unsigned char spec_find_primary_dev_type; /*the assigned primary device type be find in probe_req*/ - - struct p2p_device_peer ongoing_nego_peer ; - - /*when i am on going with someone , reject another one*/ - struct p2p_device_peer others_nego_tar_device; - - unsigned char clientmode_try_connect; - unsigned char clientmode_connected; - int backup_orig_use40M; - int backup_orig_2ndchoffset; - unsigned char change_role_is_ongoing; // to avoid deadlock at 8192cd_close() -}; - -#if defined(CONFIG_OPENWRT_SDK) -typedef struct android_wifi_priv_cmd { - char *buf; - int used_len; - int total_len; -} android_wifi_priv_cmd_t; -#endif - -#define CFG80211_P2P 1 -#define PROPERTY_P2P 2 - - -struct report_ssid_psk{ - char ssid_report[33]; - char ssid_len; - char psk_report[65]; - char psk_len; -}; - - -#endif - +/* + * Header file define some p2p struct define inline functions + * + * $Id: 8192cd_p2p.h,v 1.2 2010/12/21 + * + * Copyright (c) 2010 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _8192CD_P2P_H_ +#define _8192CD_P2P_H_ + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#if defined(P2P_SUPPORT) && defined(CONFIG_OPENWRT_SDK) +#include +#endif + +//#define P2PMODE ((GET_MIB(priv))->p2p_mib.p2p_role) +//#define P2P_STATE ((GET_MIB(priv))->p2p_mib.p2p_state) +#define P2P_EVENT_INDICATE (priv->p2pPtr->p2p_event_indiate) +#define P2P_PRE_MODE (priv->p2pPtr->p2p_pre_role) +#define P2P_DISCOVERY (priv->p2pPtr->p2p_on_discovery) +//#include "./wps/wsc.h" +/*============== will redeclare with wsc.h ==================*/ + + +#define P2P_WILDCARD_SSID_LEN 7 +#define P2P_IE_ID 221 + +#define MAC_LEN 6 +#define UUID_LEN 16 +#define MAX_MANUFACT_LEN 64 +#define MAX_MODEL_NAME_LEN 32 +#define MAX_MODEL_NUM_LEN 32 +#define MAX_SERIAL_NUM_LEN 32 +#define MAX_DEVICE_NAME_LEN 32 + +#define WSC_IE_ID 221 +#define WSC_VER 0x10 +#define TAG_SIMPLE_CONFIG_STATE 0x1044 +#define TAG_RESPONSE_TYPE2 0x103B +#define TAG_UUID_E 0x1047 +#define TAG_MANUFACTURER 0x1021 +#define TAG_MODEL_NAME 0x1023 +#define TAG_MODEL_NUMBER 0x1024 +#define TAG_SERIAL_NUM 0x1042 +#define TAG_PRIMARY_DEVICE_TYPE 0x1054 +#define TAG_DEVICE_NAME 0x1011 +#define TAG_CONFIG_METHODS 0x1008 +#define TAG_VERSION 0x104A +#define TAG_DEVICE_PASSWORD_ID 0x1012 +#define TAG_SEC_DEVICE_TYPE_LIST 0x1055 + +#define WFA_OUI_LEN 3 +#define WFA_OUI_PLUS_TYPE_LEN 4 +#define WFD_OUI_PLUS_TYPE_LEN 4 + +#define MAX_NOA_DESC_MUN 6 +#define MAX_P2P_CLIENT_MUN 5 +#define CLIENT_MODE_WAIT_TIME 30 +#define WSC_MODE_WAIT_TIME 30 + +#define P2P_CLIENT_ASSOC_EXPIRE 120 + +#define P2P_device_category_id_AP 6 +#define P2P_device_category_id_STA 1 +#define P2P_device_sub_category_id 1 + + + +/*for P2P IE attribute ID0 use*/ +enum p2p_status_code { + P2P_SC_SUCCESS = 0, + P2P_SC_FAIL_INFO_CURRENTLY_UNAVAILABLE = 1, + P2P_SC_FAIL_INCOMPATIBLE_PARAMS = 2, + P2P_SC_FAIL_LIMIT_REACHED = 3, + P2P_SC_FAIL_INVALID_PARAMS = 4, + P2P_SC_FAIL_UNABLE_TO_ACCOMMODATE = 5, + P2P_SC_FAIL_PREV_PROTOCOL_ERROR = 6, + P2P_SC_FAIL_NO_COMMON_CHANNELS = 7, + P2P_SC_FAIL_UNKNOWN_GROUP = 8, + P2P_SC_FAIL_BOTH_GO_INTENT_15 = 9, + P2P_SC_FAIL_INCOMPATIBLE_PROV_METHOD = 10, + P2P_SC_FAIL_REJECTED_BY_USER = 11, +}; + +/*for P2P IE attribute ID1 use*/ +enum p2p_minor_reason{ + minor_case1 =1, + minor_case2 =2, + minor_case3 =3, + minor_case4 =4 +}; + + +/* P2P public action frames ; + these type frames no need assoc we must process*/ +enum p2p_public_action_frame { + P2P_GO_NEG_REQ = 0, + P2P_GO_NEG_RESP = 1, + P2P_GO_NEG_CONF = 2, + P2P_INVITATION_REQ = 3, + P2P_INVITATION_RESP = 4, + P2P_DEV_DISC_REQ = 5, + P2P_DEV_DISC_RESP = 6, + P2P_PROV_DISC_REQ = 7, + P2P_PROV_DISC_RSP = 8 +}; + +/* P2P action frames ,we process these type frames after assoc*/ +enum p2p_action_frame{ + P2P_NOA = 0, + P2P_PRESENCE_REQ = 1, + P2P_PRESENCE_RSP = 2, + P2P_GO_DISCOVERY = 3 + /*4-255 reserved*/ +}; + +enum { + RSP_TYPE_ENR, + RSP_TYPE_ENR_1X, + RSP_TYPE_REG, + RSP_TYPE_AP +}; + +// wsc passwd ID +enum { + PASS_ID_DEFAULT, // 0 + PASS_ID_USER, // 1 + PASS_ID_MACHINE, // 2 + PASS_ID_REKEY, // 3 + PASS_ID_PB, // 4 + PASS_ID_REG, // 5 + PASS_ID_RESERVED // 6 +}; + + // need sync with wscd +enum { + GO_WPS_SUCCESS = 1, + GO_WPS_FAIL = 2 +}; + + + +enum { + CONFIG_METHOD_ETH=0x2, + CONFIG_METHOD_PIN=0x4, // label(PIN) + CONFIG_METHOD_DISPLAY=0x8 ,// (PISPLAY) + CONFIG_METHOD_PBC=0x80, + CONFIG_METHOD_KEYPAD=0x100, + /*add for wps2.x*/ + CONFIG_METHOD_VIRTUAL_PBC=0x280 , + CONFIG_METHOD_PHYSICAL_PBC=0x480, + CONFIG_METHOD_VIRTUAL_PIN=0x2008, + CONFIG_METHOD_PHYSICAL_PIN=0x4008 +}; + +enum p2p_role_s { + R_P2P_GO =1 , + R_P2P_DEVICE = 2, + R_P2P_CLIENT =3 +}; + + +/*note , 20140325 , cfg p2p + +under PROPERTY_P2P case, P2P_PRE_CLIENT,P2P_PRE_GO ,used for change the mode if FORMATION FAILURE + +under CFG80211_P2P case, seem don't care P2P_PRE_CLIENT,P2P_PRE_GO + + +*/ +enum p2p_role_more{ + P2P_DEVICE=1, + P2P_PRE_CLIENT=2, + P2P_CLIENT=3, + P2P_PRE_GO=4, // after GO nego , we are GO and proceed WSC exchange + P2P_TMP_GO=5 // after GO nego , we are GO and proceed WSC exchange is done +}; + +// need sync with web server utility.h +enum { + P2P_S_IDLE = 0, /* between state and state */ + + P2P_S_LISTEN , /*1 listen state */ + + P2P_S_SCAN , /*2 Scan state */ + + P2P_S_SEARCH , /*3 Search state*/ + + // 4~14 ; show status 4 in web page + P2P_S_PROVI_TX_REQ , /*4 send provision req*/ + P2P_S_PROVI_WAIT_RSP , /*5 wait provision rsp*/ + P2P_S_PROVI_RX_RSP , /*6 rx provision rsp*/ + + P2P_S_PROVI_RX_REQ , /*7 received provision req*/ + P2P_S_PROVI_TX_RSP , /*8 send provision rsp*/ + + + P2P_S_NEGO_TX_REQ , /*9 send NEGO req*/ + P2P_S_NEGO_WAIT_RSP , /*10 waiting for NEGO rsp*/ + P2P_S_NEGO_TX_CONF , /*11 send NEGO confirm*/ + + + P2P_S_NEGO_RX_REQ , /*12 rx NEGO req */ + P2P_S_NEGO_TX_RSP , /*13 send NEGO rsp */ + P2P_S_NEGO_WAIT_CONF , /*14 wait NEGO conf */ + + // 15~16 ; show status 5 in web page + P2P_S_CLIENT_CONNECTED_DHCPC , /*15 p2p client Rdy connected */ + P2P_S_CLIENT_CONNECTED_DHCPC_done, /*16 p2p client Rdy connected */ + + // 17~18 ; show status 6 in web page + P2P_S_preGO2GO_DHCPD , /*17 GO not start dhcpd yet */ + P2P_S_preGO2GO_DHCPD_done, /*18 GO rdy start dhcpd*/ + + P2P_S_back2dev /*exceed 20 seconds p2p client can't connected*/ +}; + + + +enum { + P2P_EVENT_RX_PROVI_REQ = 1 /* received provision req*/ +}; + + +enum { + WPS_MODE_NO_CHANGE=0, + MODE_AP_UNCONFIG=1, // AP unconfigured (enrollee) + MODE_CLIENT_UNCONFIG=2, // client unconfigured (enrollee) + MODE_CLIENT_CONFIG=3, // client configured (registrar) + MODE_AP_PROXY=4, // AP configured (proxy) + MODE_AP_PROXY_REGISTRAR=5, // AP configured (proxy and registrar) + MODE_CLIENT_UNCONFIG_REGISTRAR=6 // client unconfigured (registrar) +}; + +enum { + P2P_PIN_METHOD = 1, + P2P_PBC_METHOD = 2 +}; + +enum { + USE_TARGET_PIN = 1, + USE_MY_PIN = 2 +}; + +enum { + P2P_GO_PS_NONE, + P2P_GO_PS_OPPPS, + P2P_GO_PS_NP_NOA, + P2P_GO_PS_CONT_NOA, + P2P_GO_PS_NOA +}; + + +/*==================================================================*/ + +/*=====================commu with web UI start===========================*/ + +/* Any changed here MUST sync with web server utility.h */ +struct p2p_state_event{ + unsigned char p2p_status; + unsigned char p2p_event; + unsigned short p2p_wsc_method; + unsigned char p2p_role; +}; + +struct __p2p_wsc_confirm +{ + unsigned char dev_address[MAC_LEN]; + unsigned short wsc_config_method; + unsigned char pincode[9]; + +}; +/*=====================commu with web UI end===========================*/ + + + + +/*reg_class - Regulatory class (IEEE 802.11-2007, Annex J) + P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */ + +#define P2P_MAX_REG_CLASSES 10 + +/*P2P_MAX_REG_CLASS_CHANNELS - + Maximum number of channels per regulatory class */ +#define P2P_MAX_REG_CLASS_CHANNELS 20 + + +struct p2p_reg_class { + + /*reg_class - Regulatory class (IEEE 802.11-2007, Annex J)*/ + unsigned char reg_class; + + /* channels - Number of channel entries in use */ + unsigned char channel_mun; + + /* channel - Supported channels */ + unsigned char channel[P2P_MAX_REG_CLASS_CHANNELS]; + +}; + +/* struct p2p_channels - List of supported channels */ +struct p2p_channels { + unsigned short Id11_len; + char country[3]; + + /* reg_classes - Number of reg_class entries in use + corresponding to table 25(page 89) number of channels*/ + unsigned char reg_class_mun; + + /* struct p2p_reg_class - Supported regulatory class*/ + struct p2p_reg_class reg_class[P2P_MAX_REG_CLASSES]; + +}; + +/*============== will redeclare with wsc.h ==================*/ + + + + +/*P2P TAG*/ +#define TAG_STATUE 0 +#define TAG_MINOR_RES_CODE 1 +#define TAG_P2P_CAPABILITY 2 +#define TAG_DEVICE_ID 3 +#define TAG_GROUP_OWNER_INTENT 4 +#define TAG_CONFIG_TIMEOUT 5 +#define TAG_LISTEN_CHANNEL 6 +#define TAG_P2P_GROUP_BSSID 7 +#define TAG_EXT_LISTEN_TIMING 8 +#define TAG_INTEN_P2P_INTERFACE_ADDR 9 +#define TAG_P2P_MANAGEABILITY 10 +#define TAG_CHANNEL_LIST 11 +#define TAG_NOTICE_OF_ABSENCE 12 +#define TAG_P2P_DEVICE_INFO 13 +#define TAG_P2P_GROUP_INFO 14 +#define TAG_P2P_GROUP_ID 15 +#define TAG_P2P_INTERFACE 16 +#define TAG_OPERATION_CHANNEL 17 +#define TAG_INVITATION_FLAGS 18 + + + + +/* for P2P Capability attr*/ +/*dev cap*/ +#define SUPPORT_P2P_INVITATION (BIT(5)) +#define CLIENT_DISCOVERY (BIT(1)) + +/*group cap*/ +#define GCAP_GO (BIT(0)) +#define GCAP_PRESISTENT_GO (BIT(1)) +#define GCAP_GROUP_LIMIT (BIT(2)) +#define GCAP_IBSS_DIST (BIT(3)) +#define GCAP_GO_FORMATION (BIT(6)) + +struct provision_comm +{ + unsigned char dev_address[MAC_LEN]; + unsigned short wsc_config_method; + unsigned char channel; + +}; + + +#define MAX_SEC_DEV_TYPE 3 +struct device_info_s +{ + unsigned char dev_address[6] ; // + unsigned short config_method; /*which wsc config method can provided*/ + unsigned char pri_dev_type[8]; /*primary device type*/ + unsigned char sdv_mun; + unsigned char sec_dev_type[MAX_SEC_DEV_TYPE][8]; /*we keep 3 sets (second device type)*/ + char devname[33]; + +}; + + +/* need sync with wsc.h */ +typedef struct _DOT11_P2P_INDICATE_WSC{ + unsigned char EventId; + unsigned char IsMoreEvent; + + unsigned char modeSwitch ; + char network_key[65] ; + char gossid[33] ; + unsigned char trigger_method ; + + unsigned char whosPINuse ; + char PINCode[9] ; + unsigned char requestor; + char interfacename[16]; +}DOT11_P2P_INDICATE_WSC; + + + +typedef struct p2p_device_peer { + unsigned char inuse; + unsigned char dev_addr[6]; + + unsigned char dialog_token; + + int role; /* p2p is which role */ + + /*attribute ID 0 Status*/ + int status; /* enum p2p_status_code */ + + /*attribute ID 2*/ + unsigned char dev_capab; /* device capability*/ + unsigned char group_capab; /* group capability*/ + + /*attribute ID3 device ID*/ + //unsigned char device_address_to_find[6] ; + + /*attribute ID4 GO intent value*/ + unsigned char intent_value; + unsigned char TieBreak; + + /*attribute ID5 configure timeout*/ + unsigned char go_config_timeout; + unsigned char client_config_timeout; + + /*attribute ID6 configure timeout*/ + int operating_class; // frequency band + int listen_channle; // + + /*attribute ID7 group BSSID*/ + unsigned char go_bssid[6]; + + /*attribute ID8 extended listen timing*/ + unsigned short avail_period; + unsigned short avail_interval; + + /*attribute ID9 intented p2p interface address*/ + unsigned char p2p_interface_address[6] ; + + /*attribute ID10 manageability*/ + unsigned char manageability ; // bit(0)|bit(1)|bit(2)| + + /*attribute ID11 channel list*/ + /* Country code to use in P2P operations */ + + struct p2p_channels channels_list; + + + /*attribute ID 12 Notice of Absence*/ + unsigned char noa_index ; /* noa index */ + unsigned char noa_ct_oops ; /* noa ctwindows and oops */ + unsigned char noa_desc_count ; /* noa count of noa descriptor*/ + unsigned char noa_desc[2][13] ; /* noa descriptor ; a go max has two desc simultaneously*/ + + /*attribute ID 13 device info*/ + struct device_info_s peer_device_info; + + /*attribute ID 14 group info ; more Id14's attr can represent at ID13 */ + //unsigned short p2p_interface_address[6] ; // represent at ID9 + + /*attribute ID 15 group ID */ + unsigned char group_bssid[6]; + unsigned char group_ssid[33]; + unsigned char group_ssid_len; + + /*attribute ID 16 group ID */ + unsigned char interface_addr_num; + unsigned char p2p_interface_add_list[2][6] ; + + /*attribute ID 17 operating channel */ + unsigned char op_country[4]; + unsigned char op_class; + unsigned char op_channel; + + /*attribute ID 18 invitation flags*/ + unsigned char invitation_flag; + + + /*wsc IE */ + unsigned short wsc_config_method; + unsigned short device_pass_id; + + +}P2P_DEV_T, *P2P_DEV_Tp; + + +/* + in discovery phase , we can just recored the necessity info +*/ +struct assoc_peer +{ + + unsigned char inuse; + // ID2 + unsigned char dev_cap; + unsigned char group_cap; + + // ID13 + struct device_info_s devInfo; + unsigned char if_addr[6]; +}; + +struct noa_desc +{ + unsigned char count; + unsigned int duration; + unsigned int interval; + unsigned int starttime; +}; + +// ID12 +struct noa_list +{ + unsigned char index; + unsigned char CTWindow_OppPs; /*bit7 OppPS bit(0-6) CTWindows*/ + struct noa_desc noa_descs; + unsigned int go_ps_type; + unsigned int noa_counter; + unsigned int p2p_txpause_flag; +}; + +#define MAX_P2P_IE_LEN 128 +struct p2p_context { + struct timer_list p2p_search_timer_t; + struct timer_list p2p_find_timer_t; + + //unsigned int p2p_type; rename to role + //int p2p_role; + int p2p_state; + int p2p_on_discovery; + int p2p_event_indiate; + u8 use_6m_rate; + + /*=========remain on channel related========*/ + int pre_p2p_role; // keep pre p2p role 20140306 add + int pre_p2p_state; // keep pre p2p role 20140306 add + +#if defined(P2P_SUPPORT) && defined(CONFIG_OPENWRT_SDK) + /*=========remain on channel related========*/ + struct timer_list remain_on_ch_timer; + u8 restore_channel; + struct ieee80211_channel remain_on_ch_channel; + u64 remain_on_ch_cookie; + + /*=========remain on channel related========*/ + struct timer_list scan_deny_timer; + u64 send_action_id; + //struct cfg80211_wifidirect_info cfg80211_wdinfo; +#endif + //unsigned int Status; + + unsigned char wsc_ie_rsp[MAX_P2P_IE_LEN]; // full size maybe 32 + 8 + 8 + unsigned char wsc_ie_rsp_mun; // use for action frame (eg nego rsp) + + unsigned char wsc_ie_req[MAX_P2P_IE_LEN]; // full size maybe 32 + 8 + 8 + unsigned char wsc_ie_req_mun; // use for action frame (eg nego rsp) + + unsigned char p2p_probe_req_ie[MAX_P2P_IE_LEN]; + unsigned char p2p_probe_req_ie_len; + + unsigned char p2p_probe_rsp_ie[MAX_P2P_IE_LEN]; + unsigned char p2p_probe_rsp_ie_len; + + unsigned char p2p_beacon_ie[MAX_P2P_IE_LEN]; + unsigned char p2p_beacon_ie_len; + + unsigned char p2p_assocReq_ie[MAX_P2P_IE_LEN]; + unsigned char p2p_assocReq_ie_len; + + unsigned char p2p_assoc_RspIe[MAX_P2P_IE_LEN]; + unsigned char p2p_assoc_RspIe_len; + + unsigned char p2p_disass_ie[MAX_P2P_IE_LEN]; + unsigned char p2p_disass_ie_len; + + unsigned char wfd_probe_req_ie[MAX_P2P_IE_LEN]; + unsigned char wfd_probe_req_ie_len; + + + unsigned char wait2listenState; + + + unsigned char collect_type; // 1:from beacon ; 2:from probe_rsp + + /*when i am GO and some p2p client assoc to me ; recored here*/ + struct assoc_peer assocPeers[MAX_P2P_CLIENT_MUN]; + + /*when i am GO and some p2p dev probe_req me */ + unsigned char probe_rps_to_p2p_dev; + + /*when i am client record noa from beacon */ + struct noa_list noa_list_t; + + + int pre_client_timeout; + int pre_go_timeout; + + /*for handle client discovery req/rsp , GO discovery req related */ + unsigned char dev_dis_req_dialog_token; + unsigned char dev_dis_rsp_dialog_token; + // unsigned char provision_rx_dialog_token; + + /*for handle provision discovery related process*/ + unsigned char presence_tx_dialog_token; + unsigned char presence_rx_dialog_token; + + /*for handle provision discovery related process*/ + unsigned char provision_tx_dialog_token; + unsigned char provision_rx_dialog_token; + + /*for handle active send provision req and Nego Req*/ + unsigned char target_device_role; + unsigned char target_device_ssid[33]; + unsigned char target_device_addr[MAC_LEN]; + unsigned char target_device_channel; + unsigned short wsc_method_to_target_dev; + unsigned short dev_passwd_to_tar_dev; + unsigned char target_dev_pin_code[9]; + unsigned char wsc_method_match; + /* when receive provision req , record target dev wsc method*/ + unsigned short wsc_method_from_target_dev; + unsigned char passivemode_pbc_trigger_flag; + + /*for handle action frames*/ + unsigned char provision_req_timeout; + + unsigned char requestor; // i am requestor or not + + + + /*for handle go-nego related process*/ + unsigned char go_nego_tx_dialog_token; // my req token + unsigned char go_nego_rx_dialog_token; // target dev's req token + + unsigned char go_nego_on_going; // for lock this GO nego process + unsigned char go_nego_on_going_timeout; // for lock this GO nego process + + /*for handle action packets ; when receive go-nego req*/ + int wait_nego_conf_timeout; + + /*my GO Negotiation data */ + unsigned char my_GO_ssid[33]; /*should be DRIECT-xy+(0~23 assic)*/ + unsigned char my_GO_ssid_len; + unsigned char ssid_random[3]; // DIRETC-xy ; the xy + unsigned char go_PSK[65]; + + struct p2p_channels my_channel_list; + + /*my P2P capability*/ + + /*device capa 0~5*/ + unsigned char service_discover; + unsigned char p2p_client_discoverability; + unsigned char concurrent_operations; + unsigned char p2p_infrastructure_managed; + unsigned char p2p_device_limit; + unsigned char p2p_invitation; + /*group capa 0~6*/ + unsigned char p2p_go_role; + unsigned char persistent_go; + unsigned char p2p_go_limit; + unsigned char intra_bss_distribution; + unsigned char cross_conect; + unsigned char persistent_reconnect; + unsigned char go_formation; + + + unsigned char wps_is_ongoing; + + /*p2p discovery phase need related data ; no use now*/ + unsigned char spec_find_dev_addr[6]; /*the assigned p2p device address be find in probe_req */ + unsigned char spec_find_primary_dev_type; /*the assigned primary device type be find in probe_req*/ + + struct p2p_device_peer ongoing_nego_peer ; + + /*when i am on going with someone , reject another one*/ + struct p2p_device_peer others_nego_tar_device; + + unsigned char clientmode_try_connect; + unsigned char clientmode_connected; + int backup_orig_use40M; + int backup_orig_2ndchoffset; + unsigned char change_role_is_ongoing; // to avoid deadlock at 8192cd_close() +}; + +#if defined(CONFIG_OPENWRT_SDK) +typedef struct android_wifi_priv_cmd { + char *buf; + int used_len; + int total_len; +} android_wifi_priv_cmd_t; +#endif + +#define CFG80211_P2P 1 +#define PROPERTY_P2P 2 + + +struct report_ssid_psk{ + char ssid_report[33]; + char ssid_len; + char psk_report[65]; + char psk_len; +}; + + +#endif + diff --git a/package/kernel/rtl8192cd/8192cd_phyreg.h b/package/kernel/rtl8192cd/8192cd_phyreg.h index 375e15530f4..35185b4869a 100644 --- a/package/kernel/rtl8192cd/8192cd_phyreg.h +++ b/package/kernel/rtl8192cd/8192cd_phyreg.h @@ -1,1014 +1,1014 @@ -/* - * Header file for 8190 Phy Register Definition - * - * $Id: 8192cd_phyreg.h,v 1.2.2.3 2010/09/01 07:07:58 button Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _8192CD_PHYREG_H_ -#define _8192CD_PHYREG_H_ - -#ifndef WLAN_HAL_INTERNAL_USED - - -/*--------------------------Define Parameters-------------------------------*/ - -//============================================================ -// 8192CD Register offset definition -//============================================================ - -// -// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 -// 3. RF register 0x00-2E -// 4. Bit Mask for BB/RF register -// 5. Other defintion for BB/RF R/W -// - -/* -// -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 1. Page1(0x100) -// -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c -*/ - - -// -// 2. BB Register Page8(0x800) -// -#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? -#define rFPGA0_TxInfo 0x804 // Status report?? -#define rFPGA0_PSDFunction 0x808 -#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? -#define rTXPATH_AC 0x80c -#define rFPGA0_RFTiming1 0x810 // Useless now -#define rFPGA0_RFTiming2 0x814 -/* -#define rFPGA0_XC_RFTiming 0x818 -#define rFPGA0_XD_RFTiming 0x81c -*/ -#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK5_1_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c -#define rFPGA0_RFWakeUpParameter 0x850 // Useless now -#define rFPGA0_RFSleepUpParameter 0x854 -#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch -#define rFPGA0_XCD_SwitchControl 0x85c -#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch -#define rFPGA0_XB_RFInterfaceOE 0x864 -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_A_CCK11_2_B_CCK11 0x86c -#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control -#define rFPGA0_XCD_RFInterfaceSW 0x874 -#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter -#define rFPGA0_XCD_RFParameter 0x87c -#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define rFPGA0_AnalogParameter2 0x884 -#if defined(CONFIG_RTL_92D_SUPPORT) -#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy -#else -#define rFPGA0_AnalogParameter3 0x888 // Useless now -#endif -#define rFPGA0_AnalogParameter4 0x88c -#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback -#define rFPGA0_XB_LSSIReadBack 0x8a4 -/* -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac -*/ -#define rFPGA0_PSDReport 0x8b4 // Useless now -#define TransceiverA_HSPI_Readback 0x8b8 -#define TransceiverB_HSPI_Readback 0x8bc -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value -//#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now - - -// -// 3. BB Register Page9(0x900) -// -#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? -#define rFPGA1_TxBlock 0x904 // Useless now -#define rFPGA1_DebugSelect 0x908 // Useless now -#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? -#define rTX_PATH_SEL_1 0x93c // Tx antenna path selection -#define rTX_PATH_SEL_2 0x940 // Tx antenna path selection2 - - -// -// 4. BB Register PageA(0xA00) -// -// Set Control channel to upper or lower. These settings are required only for 40MHz -#define rCCK0_System 0xa00 -#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI -#define rCCK_RX_AC 0xa04 -#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain -#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series -#define rCCK0_RxAGC2 0xa10 //AGC & DAGC -#define rCCK0_RxHP 0xa14 -#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold -#define rCCK0_DSPParameter2 0xa1c //SQ threshold -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 -#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 //0xa57 -#define rCCK0_FACounterLower 0xa5c //0xa5b -#define rCCK0_FACounterUpper 0xa58 //0xa5c - - -// -// 5. BB Register PageC(0xC00) -// -#define rOFDM0_LSTF 0xc00 -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c -#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -/* -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c -*/ -#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain -#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. -#define rOFDM0_RxDetector3 0xc38 //Frame Sync. -#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI -#define rOFDM0_RxDSP 0xc40 //Rx Sync Path -#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC -#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold -#define rOFDM0_ECCAThreshold 0xc4c // energy CCA -#define rOFDM0_XAAGCCore1 0xc50 // DIG -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -/* -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c -*/ -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c -#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c - - -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c -#define rOFDM0_RxIQExtAnta 0xca0 - - -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 - - -// -// 6. BB Register PageD(0xD00) -// -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 -#define rOFDM1_CFO 0xd08 // No setting now -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 -#define rOFDM_PHYCounter1 0xda0 //cca, parity fail -#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail -#define rOFDM_PHYCounter3 0xda8 //MCS not support -#define rOFDM_ShortCFOAB 0xdac // No setting now -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -// -// 6. BB Register PageE(0xE00) -// -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - - -// -// 7. RF Register 0x00-0x2E -// -//Zebra1 -#define rZebra1_HSSIEnable 0x0 // Useless now -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 // RF channel switch -#define rZebra1_TxGain 0x8 // Useless now -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc -#define rRfChannel 0x18 // RF channel switch For T65 RF 0222d - -//Zebra4 -#define rGlobalCtrl 0 // Useless now -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -//RTL8258 -#define rRTL8258_RSSILPF 0xa -#define rRTL8258_TxLPF 0x11 // Useless now -#define rRTL8258_RxLPF 0x13 - - -#define RF_RX_G1 0x1A // -#define RF_RX_G2 0x1B // - - -// -//Bit Mask -// -// 1. Page1(0x100) -/* -#define bBBResetB 0x100 // Useless now? -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 -*/ - - -// -// 2. Page8(0x800) -// -#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 // Useless now -#define bOFDMTxDACPhase 0x40000 - -#define bXATxAGC 0x3f -#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage -/* -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 -*/ - -#define bPAStart 0xf0000000 // Useless now -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf //Reg0x814 -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 //T2R -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 //chane gain at continue Tx -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 // Useless now -//#define bHWSISelect 0x8 -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW - -#define bRFSI_TRSW 0x20 // Useless now -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -//#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 -#define bLSSIReadAddress 0x7f800000 // T65 RF -#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal - -//#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack -#define bLSSIReadBackData 0xfffff // T65 RF - -#define bLSSIReadOKFlag 0x1000 // Useless now -#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ - -#define b80MClkDelay 0x18000000 // Useless -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 - -#define bIntDifClkEnable 0x400 // Useless -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - - -// -// 3. Page9(0x900) -// -#define bOFDMTxSC 0x30000000 // Useless -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff //reset debug page and also HWord, LWord -#define bDebugItem 0xff //reset debug page and LWord -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - - -// -// 4. PageA(0xA00) -// -#define bCCKBBMode 0x3 // Useless -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch - -#define bCCKScramble 0x8 // Useless -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 //r_rx_clk -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f //AGCsamp_dly -#define bCCKFixedRxAGC 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - - -// -// 5. PageC(0xC00) -// -#define bNumOfSTF 0x3 // Useless -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 //the threshold for high power -#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -//#define bRxMF_Hold 0x3800 -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -/* -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -*/ -#define bExtLNAGain 0x7c00 - - -// -// 6. PageE(0xE00) -// -#define bSTBCEn 0x4 // Useless -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bOFDMDisPwsavTx 0x400000 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -/* -#define bRxPath1 0x01 -#define bRxPath2 0x02 -#define bRxPath3 0x04 -#define bRxPath4 0x08 -#define bTxPath1 0x10 -#define bTxPath2 0x20 -*/ -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 //total -#define bShortCFOFLength 11 //fraction -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -/* -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -*/ -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf // Useless -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 // Useless -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 // Useless -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -#define bTxAGCRate18_06 0x7f7f7f7f // Useless -#define bTxAGCRate54_24 0x7f7f7f7f -#define bTxAGCRateMCS32 0x7f -#define bTxAGCRateCCK 0x7f00 -#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f -#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f -#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f -#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f - -//Rx Pseduo noise -#define bRxPesudoNoiseOn 0x20000000 // Useless -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -/* -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -*/ -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -/* -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 -*/ - - -// -//7. RF Register -// -//Zebra1 -#define bZebra1_HSSIEnable 0x8 // Useless -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -//Zebra4 -#define bRTL8256RegModeCtrl1 0x100 // Useless -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -//RTL8258 -#define bRTL8258_TxLPFBW 0xc // Useless -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -// -// Other Definition -// -//byte endable for sb_write -#define bByte0 0x1 // Useless -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -//for PutRegsetting & GetRegSetting BitMask -#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskL3Byte 0x00ffffff -#define bMaskH4Bits 0xf0000000 -#define bMaskH12Bits 0xfff00000 -#define bMaskH3Bytes 0xffffff00 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f -#define bMask4to7Bits 0x000000f0 -#define bMask4to15Bits 0x0000fff0 - - -//for PutRFRegsetting & GetRFRegSetting BitMask -#define bMask12Bits 0xfff // RF Reg mask bits -#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF - -#define bEnable 0x1 // Useless -#define bDisable 0x0 - -#define LeftAntenna 0x0 // Useless -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 //500ms // Useless -#define tUpdateRxCounter 100 //100ms - -#define rateCCK 0 // Useless -#define rateOFDM 1 -#define rateHT 2 - -//define Register-End -#define bPMAC_End 0x1ff // Useless -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff -/* -//define max debug item in each debug page -#define bMaxItem_FPGA_PHY0 0x9 -#define bMaxItem_FPGA_PHY1 0x3 -#define bMaxItem_PHY_11B 0x16 -#define bMaxItem_OFDM_PHY0 0x29 -#define bMaxItem_OFDM_PHY1 0x0 -*/ -#define bPMACControl 0x0 // Useless -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 // Useless -#define PathB 0x1 -/* -#define PathC 0x2 -#define PathD 0x3 -*/ - - -#define REG_SYS_FUNC_EN 0x2 -#define REG_AFE_PLL_CTRL 0x28 -#define REG_RF_CTRL 0x1f -#define REG_LDOHCI12_CTRL 0x22 -#define REG_AFE_XTAL_CTRL 0x24 -#define RF_T_METER 0x24 -#define REG_MCUFWDL 0x80 -#define REG_HMETFR 0x01CC - -#define RF_T_METER_92D 0x42 - -/*--------------------------Define Parameters-------------------------------*/ -//#endif - -#endif //#ifndef WLAN_HAL_INTERNAL_USED -#endif // _8192CD_PHYREG_H_ - +/* + * Header file for 8190 Phy Register Definition + * + * $Id: 8192cd_phyreg.h,v 1.2.2.3 2010/09/01 07:07:58 button Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _8192CD_PHYREG_H_ +#define _8192CD_PHYREG_H_ + +#ifndef WLAN_HAL_INTERNAL_USED + + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// 8192CD Register offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + +/* +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c +*/ + + +// +// 2. BB Register Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? +#define rTXPATH_AC 0x80c +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 +/* +#define rFPGA0_XC_RFTiming 0x818 +#define rFPGA0_XD_RFTiming 0x81c +*/ +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK5_1_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_A_CCK11_2_B_CCK11 0x86c +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#if defined(CONFIG_RTL_92D_SUPPORT) +#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy +#else +#define rFPGA0_AnalogParameter3 0x888 // Useless now +#endif +#define rFPGA0_AnalogParameter4 0x88c +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +/* +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac +*/ +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 +#define TransceiverB_HSPI_Readback 0x8bc +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +//#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + + +// +// 3. BB Register Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? +#define rTX_PATH_SEL_1 0x93c // Tx antenna path selection +#define rTX_PATH_SEL_2 0x940 // Tx antenna path selection2 + + +// +// 4. BB Register PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK_RX_AC 0xa04 +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC +#define rCCK0_RxHP 0xa14 +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + + +// +// 5. BB Register PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +/* +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c +*/ +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +/* +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c +*/ +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c + + +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxIQExtAnta 0xca0 + + +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +// +// 6. BB Register PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 6. BB Register PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + + +// +// 7. RF Register 0x00-0x2E +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 // RF channel switch +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc +#define rRfChannel 0x18 // RF channel switch For T65 RF 0222d + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_RSSILPF 0xa +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 + + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + + +// +//Bit Mask +// +// 1. Page1(0x100) +/* +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 +*/ + + +// +// 2. Page8(0x800) +// +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 + +#define bXATxAGC 0x3f +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +/* +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +*/ + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +//#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 +#define bLSSIReadAddress 0x7f800000 // T65 RF +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal + +//#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack +#define bLSSIReadBackData 0xfffff // T65 RF + +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + + +// +// 3. Page9(0x900) +// +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + + +// +// 4. PageA(0xA00) +// +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + + +// +// 5. PageC(0xC00) +// +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +/* +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +*/ +#define bExtLNAGain 0x7c00 + + +// +// 6. PageE(0xE00) +// +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bOFDMDisPwsavTx 0x400000 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +/* +#define bRxPath1 0x01 +#define bRxPath2 0x02 +#define bRxPath3 0x04 +#define bRxPath4 0x08 +#define bTxPath1 0x10 +#define bTxPath2 0x20 +*/ +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +/* +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +*/ +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +#define bTxAGCRate18_06 0x7f7f7f7f // Useless +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +/* +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +*/ +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +/* +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 +*/ + + +// +//7. RF Register +// +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskL3Byte 0x00ffffff +#define bMaskH4Bits 0xf0000000 +#define bMaskH12Bits 0xfff00000 +#define bMaskH3Bytes 0xffffff00 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f +#define bMask4to7Bits 0x000000f0 +#define bMask4to15Bits 0x0000fff0 + + +//for PutRFRegsetting & GetRFRegSetting BitMask +#define bMask12Bits 0xfff // RF Reg mask bits +#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF + +#define bEnable 0x1 // Useless +#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff +/* +//define max debug item in each debug page +#define bMaxItem_FPGA_PHY0 0x9 +#define bMaxItem_FPGA_PHY1 0x3 +#define bMaxItem_PHY_11B 0x16 +#define bMaxItem_OFDM_PHY0 0x29 +#define bMaxItem_OFDM_PHY1 0x0 +*/ +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 // Useless +#define PathB 0x1 +/* +#define PathC 0x2 +#define PathD 0x3 +*/ + + +#define REG_SYS_FUNC_EN 0x2 +#define REG_AFE_PLL_CTRL 0x28 +#define REG_RF_CTRL 0x1f +#define REG_LDOHCI12_CTRL 0x22 +#define REG_AFE_XTAL_CTRL 0x24 +#define RF_T_METER 0x24 +#define REG_MCUFWDL 0x80 +#define REG_HMETFR 0x01CC + +#define RF_T_METER_92D 0x42 + +/*--------------------------Define Parameters-------------------------------*/ +//#endif + +#endif //#ifndef WLAN_HAL_INTERNAL_USED +#endif // _8192CD_PHYREG_H_ + diff --git a/package/kernel/rtl8192cd/8192cd_proc.c b/package/kernel/rtl8192cd/8192cd_proc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_profile.h b/package/kernel/rtl8192cd/8192cd_profile.h old mode 100755 new mode 100644 index 81d01d9166f..3538032346a --- a/package/kernel/rtl8192cd/8192cd_profile.h +++ b/package/kernel/rtl8192cd/8192cd_profile.h @@ -1,32 +1,32 @@ -#define SC_ENABLED 1 -#define SC_DURATION_TIME 2 -#define SC_GET_SYNC_TIME 3 -#define SC_GET_PROFILE_TIME 4 -#define SC_VXD_RESCAN_TIME 5 -#define SC_PIN_ENABLED 6 -#define SC_STATUS 7 -#define SC_DEBUG 8 -#define SC_CHECK_LINK_TIME 9 -#define SC_SYNC_VXD_TO_ROOT 10 -#define SC_ACK_ROUND 11 -#define SC_CONTROL_IP 12 -#define SC_PRIV_STATUS 13 -#define SC_CONFIG_TIME 14 -#define SC_CHECK_LEVEL 16 -#define SC_IGNORE_OVERLAP 17 -#define SC_FIX_CHANNEL 18 -#define SC_FROM_TO_DS 19 - -#define SC_PIN 20 -#define SC_DEFAULT_PIN 21 -#define SC_PASSWORD 22 -#define SC_DEVICE_NAME 23 -#define SC_DEVICE_TYPE 24 -#define SC_SSID 25 -#define SC_BSSID 26 -#define SC_IF_NAME 27 - -#define SC_FIX_ENCRYPT 28 -#define SC_CONFIG_TYPE 29 - -#define SC_MAGIC_LEN 8 +#define SC_ENABLED 1 +#define SC_DURATION_TIME 2 +#define SC_GET_SYNC_TIME 3 +#define SC_GET_PROFILE_TIME 4 +#define SC_VXD_RESCAN_TIME 5 +#define SC_PIN_ENABLED 6 +#define SC_STATUS 7 +#define SC_DEBUG 8 +#define SC_CHECK_LINK_TIME 9 +#define SC_SYNC_VXD_TO_ROOT 10 +#define SC_ACK_ROUND 11 +#define SC_CONTROL_IP 12 +#define SC_PRIV_STATUS 13 +#define SC_CONFIG_TIME 14 +#define SC_CHECK_LEVEL 16 +#define SC_IGNORE_OVERLAP 17 +#define SC_FIX_CHANNEL 18 +#define SC_FROM_TO_DS 19 + +#define SC_PIN 20 +#define SC_DEFAULT_PIN 21 +#define SC_PASSWORD 22 +#define SC_DEVICE_NAME 23 +#define SC_DEVICE_TYPE 24 +#define SC_SSID 25 +#define SC_BSSID 26 +#define SC_IF_NAME 27 + +#define SC_FIX_ENCRYPT 28 +#define SC_CONFIG_TYPE 29 + +#define SC_MAGIC_LEN 8 diff --git a/package/kernel/rtl8192cd/8192cd_psk.h b/package/kernel/rtl8192cd/8192cd_psk.h index 7f709d4d063..8c8b5ff0bbb 100644 --- a/package/kernel/rtl8192cd/8192cd_psk.h +++ b/package/kernel/rtl8192cd/8192cd_psk.h @@ -181,10 +181,12 @@ typedef struct _wpa_global_info { OCTET_STRING AuthInfoElement; unsigned char AuthInfoBuf[INFO_ELEMENT_SIZE]; unsigned char MulticastCipher; - int NumOfUnicastCipher; + int NumOfUnicastCipher; unsigned char UnicastCipher[MAX_UNICAST_CIPHER]; + unsigned char GTK[NumGroupKey][GTK_LEN]; + int GN; #ifdef RTL_WPA2 - int NumOfUnicastCipherWPA2; + int NumOfUnicastCipherWPA2; unsigned char UnicastCipherWPA2[MAX_UNICAST_CIPHER]; #endif } WPA_GLOBAL_INFO; diff --git a/package/kernel/rtl8192cd/8192cd_smart_roaming.c b/package/kernel/rtl8192cd/8192cd_smart_roaming.c old mode 100755 new mode 100644 index c7dd542d26e..b6288299b96 --- a/package/kernel/rtl8192cd/8192cd_smart_roaming.c +++ b/package/kernel/rtl8192cd/8192cd_smart_roaming.c @@ -1,801 +1,801 @@ - -/* - * Software Smart Roaming routines - * - * $Id: rtl_smart_roaming.c, v 1.4.4.2 2016/04/30 05:27:28 Tracy Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define _8192CD_SMART_ROAMING_C_ - -#include -#include -#include -#include -#include -#include "8192cd.h" -#include "8192cd_util.h" -#include "8192cd_headers.h" - -#define NETLINK_RTK 31 -#define MAX_PAYLOAD 2048 - - -struct timer_list *timer_wlan0; -struct timer_list *timer_wlan1; - -struct sock *rtl_smart_roaming_nl = NULL; - -int wlan0_used,wlan1_used,wlan0_deleted,wlan1_deleted,msg_dropcounter; - -int pid = 0; - -static void sr_timer_rec_add() { - if (wlan0_used && wlan0_deleted ){ - add_timer(timer_wlan0); - wlan0_deleted = 0; - } - if (wlan1_used && wlan1_deleted) { - add_timer(timer_wlan1); - wlan1_deleted = 0; - } -} - - -static void sr_timer_rec_del(){ - if(wlan0_used && (wlan0_deleted == 0)){ - del_timer_sync(timer_wlan0); - wlan0_used = 0; - wlan0_deleted = 1; - } - if(wlan1_used && (wlan1_deleted == 0)){ - del_timer_sync(timer_wlan1); - wlan1_used = 0; - wlan1_deleted = 1; - } -} - -//init timer when wlan interface up -void timer_ready(struct rtl8192cd_priv *priv) -{ - if ((!strcmp(priv->dev->name, "wlan0")) && (wlan0_used != 1)){ - init_timer(&priv->send_timer_wlan0); - priv->send_timer_wlan0.expires = jiffies+RTL_SECONDS_TO_JIFFIES(5); - priv->send_timer_wlan0.data = (unsigned long) priv; - priv->send_timer_wlan0.function = send_roam_info; - priv->wlanid = 0; - timer_wlan0 = &(priv->send_timer_wlan0); - wlan0_used = 1; - wlan0_deleted = 1; - - /* 2GHz-30; 5GHz-20 */ - priv->pmib->sr_profile.load_min += 10; - } - - else if ((!strcmp(priv->dev->name, "wlan1")) && (wlan1_used != 1)){ - init_timer(&priv->send_timer_wlan1); - priv->send_timer_wlan1.expires = jiffies+RTL_SECONDS_TO_JIFFIES(4); - priv->send_timer_wlan1.data = (unsigned long) priv; - priv->send_timer_wlan1.function = send_roam_info; - priv->wlanid = 1; - timer_wlan1 = &(priv->send_timer_wlan1); - wlan1_used = 1; - wlan1_deleted = 1; - - /* 2GHz-30; 5GHz-25 */ - priv->pmib->sr_profile.signal_min += 5; - priv->pmib->sr_profile.signal_max += 10; - } - if(pid != 0){ - sr_timer_rec_add(); - } -} - -//delete timer when wlan interface down -void timer_del(struct rtl8192cd_priv *priv) -{ - if (!strcmp(priv->dev->name, "wlan0")){ - del_timer_sync(&priv->send_timer_wlan0); - wlan0_used = 0; - wlan0_deleted = 1; - } - else if (!strcmp(priv->dev->name, "wlan1")){ - del_timer_sync(&priv->send_timer_wlan1); - wlan1_used = 0; - wlan1_deleted = 1; - } -} - -//netlink send msg -void rtl_netlink_rcv(struct sk_buff *skb) -{ - struct nlmsghdr *nlh = NULL; - unsigned char *message; - - if(skb == NULL) { - panic_printk(KERN_INFO "%s: skb is NULL\n", __FUNCTION__); - return ; - } - - nlh=(struct nlmsghdr*)skb->data; - //printk(KERN_INFO "kernel received msg payload:%s\n",(unsigned char*)NLMSG_DATA(nlh)); - - message = NLMSG_DATA(nlh); - - if (*message == 'S') - { - pid = nlh->nlmsg_pid; //pid of sending process - sr_timer_rec_add(); - } - - - if (*message == 'F') - { - panic_printk("\nSR received delete!\n"); - sr_timer_rec_del(); - } - -} - -//netlink send msg -void rtl_netlink_sendmsg(int pid, struct sock *nl_sk,char *data, int data_len) -{ - struct nlmsghdr *nlh; - struct sk_buff *skb; - unsigned int skblen; - unsigned char *datab; - const char *fn; - int err; - - if(pid == 0) - return; - - if(data_len > MAX_PAYLOAD) - { - err = -ENOBUFS; - fn = "data_len"; - goto msg_fail; - } - - skblen = NLMSG_SPACE(data_len + 4); //+len - skb = alloc_skb(skblen, GFP_ATOMIC); - - if(!skb) - { - err = -ENOBUFS; - fn = "alloc_skb"; - goto msg_fail; - } - - nlh = nlmsg_put(skb,0,0,0,skblen-sizeof(*nlh),0); - - if(!nlh) - { - err = -ENOBUFS; - fn = "nlmsg_put"; - goto msg_fail_skb; - } - -#if defined(__LINUX_3_10__) - NETLINK_CB(skb).portid = 0; //from kernel -#else - NETLINK_CB(skb).pid = 0; //from kernel -#endif - NETLINK_CB(skb).dst_group = 0; //unicast - - datab = NLMSG_DATA(nlh); - memset(datab, 0, data_len+4); - memcpy(datab,&data_len,4); //+ total len - memcpy(datab+4,data, data_len); - - nlh->nlmsg_len = NLMSG_HDRLEN + data_len + 4; - - //printk("check data_len before send=%d\n",data_len); - err= netlink_unicast(nl_sk, skb, pid, MSG_DONTWAIT); - - if (err < 0) - { - fn = "nlmsg_unicast"; - goto msg_fail; //nlmsg_unicast already kfree_skb - } - - return; - -msg_fail_skb: - kfree_skb(skb); - -msg_fail: - if(msg_dropcounter < 3){ - msg_dropcounter++; - panic_printk("[%s] drop msg: pid=%d msglen=%d %s: err=%d\n",__FUNCTION__, pid, data_len, fn, err); - } - return; -} - -#ifdef STA_CONTROL -void notify_hidden_ap(struct rtl8192cd_priv *priv, int type) -{ - if(!priv->stactrl.stactrl_enable_hiddenAP ||priv->stactrl.stactrl_prefer) - return; - - int offset =0; - unsigned char send_buf[10]={0}; - - if (!strcmp(priv->dev->name, "wlan0")) - priv->wlanid = 0; - else if (!strcmp(priv->dev->name, "wlan1")) - priv->wlanid = 1; - - send_buf[offset] = type; - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->vap_id),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); -} -#endif - -void notify_new_sta(struct rtl8192cd_priv *priv, unsigned char *mac,int type, unsigned char rssi) -{ - int offset =0; - - unsigned char send_buf[10]={0}; - unsigned char channel_util; - - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - priv->wlanid = 0; - else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - priv->wlanid = 1; - - send_buf[offset] = type; - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->pmib->dot11RFEntry.dot11channel),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - channel_util = 255 - priv->ext_stats.ch_utilization; - memcpy(send_buf+offset,&(channel_util),sizeof(channel_util)); - offset+=sizeof(channel_util); - - memcpy(send_buf+offset, mac, MACADDRLEN); - offset += MACADDRLEN; - - memcpy(send_buf+offset,&(rssi),sizeof(rssi)); - offset+=sizeof(rssi); - - rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); -} - -//Get neighbor channel unicast Null data rssi -void add_neighbor_unicast_sta(struct rtl8192cd_priv *priv,unsigned char* addr, unsigned char rssi) -{ - int i, idx=-1, idx2 =0; - unsigned char rssi_input; - for (i = 0; i < MAX_NEIGHBOR_STA; i++) { - if (priv->neigbor_sta[i].used == 0) { - if (idx < 0) - idx = i; //search for empty entry - continue; - } - if (!memcmp(priv->neigbor_sta[i].addr, addr, MACADDRLEN)) { - idx2 = i; - break; // check if it is already in the list - } - } - if (idx >= 0){ - rssi_input = rssi; - memcpy(priv->neigbor_sta[idx].addr, addr, MACADDRLEN); - priv->neigbor_sta[idx].used = 1; - priv->neigbor_sta[idx].Entry = idx; //check which entry is the neighbor sta recorded - priv->neigbor_sta[idx].rssi = rssi_input; - priv->NeighborStaEntryOccupied++; - - } - else if (idx2){ - rssi_input = ((priv->neigbor_sta[idx2].rssi * 7)+(rssi * 3)) / 10; - priv->neigbor_sta[idx2].rssi = rssi_input; - - return; - } - else if (priv->NeighborStaEntryOccupied == MAX_NEIGHBOR_STA) {// sta list full, need to replace sta - idx = priv->NeighborStaEntryNum; - for (i = 0; i < MAX_NEIGHBOR_STA; i++) { - if (!memcmp(priv->neigbor_sta[i].addr, addr, MACADDRLEN)) - return; // check if it is already in the list - } - memcpy(priv->neigbor_sta[idx].addr, addr, MACADDRLEN); - priv->neigbor_sta[idx].used = 1; - priv->neigbor_sta[idx].Entry = idx; - priv->neigbor_sta[idx].rssi = rssi; - priv->NeighborStaEntryNum++; - if( priv->NeighborStaEntryNum == MAX_NEIGHBOR_STA) - priv->NeighborStaEntryNum = 0; // Reset entry counter; - return; - } -} - -//construct associated sta info -unsigned char construct_assoc_sta(struct rtl8192cd_priv *priv,unsigned char *send_buf, int * offset) -{ - struct stat_info *pstat; - struct list_head *phead, *plist; - unsigned char data_rate; - unsigned char assoc_num = 0; - unsigned int link_time = 0; - unsigned int tx_throughput = 0; - unsigned int rx_throughput = 0; - unsigned char dot11kv_flag = 0; - unsigned char dual_band = 0; - unsigned char btm_fail_count = 0; -#ifdef SMP_SYNC - unsigned long flags = 0; -#endif - - phead = &priv->asoc_list; - - if (list_empty(phead)) { - return 0; - } - - SMP_LOCK_ASOC_LIST(flags); - plist = phead->next; - - //construct associated sta info - while (plist != phead) { - - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - -#ifdef CONFIG_RTK_MESH - if( isMeshPoint(pstat)) - continue; -#endif -#ifdef WDS - if(pstat->state & WIFI_WDS) - continue; -#endif -//printk("pstat->IOTPeer=%d\n",pstat->IOTPeer); - if (pstat && pstat->IOTPeer == HT_IOT_PEER_RTK_APCLIENT) - continue; - - if(pstat->expire_to==0) // exclude expired STA - continue; - - memcpy(send_buf+*offset,&(pstat->hwaddr), MACADDRLEN); - *offset += MACADDRLEN; - - memcpy(send_buf+*offset,&(pstat->rssi),sizeof(unsigned char)); - *offset+=sizeof(unsigned char); - - //data rate only when tx pkts increase within 5s - if (pstat->tx_pkts > pstat->tx_pkts_pre) - data_rate = (pstat->current_tx_rate >= VHT_RATE_ID) ? ((pstat->current_tx_rate - VHT_RATE_ID)%10):((pstat->current_tx_rate >= HT_RATE_ID)? (pstat->current_tx_rate - HT_RATE_ID) : pstat->current_tx_rate/2); - else - data_rate = 255; //will not trigger data_rate threshold - - memcpy(send_buf+*offset,&data_rate,sizeof(unsigned char)); - *offset+=sizeof(unsigned char); - - //int link_time: host byte order convert to network byte order - link_time=htonl(pstat->link_time); - memcpy(send_buf+*offset,&(link_time),sizeof(link_time)); - *offset+=sizeof(link_time); - - //int tx_tp: host byte order convert to network byte order - tx_throughput = htonl(pstat->tx_avarage); - memcpy(send_buf+*offset, &(tx_throughput), sizeof(tx_throughput)); - *offset += sizeof(tx_throughput); - - //int rx_tp: host byte order convert to network byte order - rx_throughput = htonl(pstat->rx_avarage); - memcpy(send_buf+*offset, &(rx_throughput),sizeof(rx_throughput)); - *offset += sizeof(rx_throughput); - -#ifdef CONFIG_IEEE80211V - dual_band = pstat->dual_band_capable; -#endif - - //unsigned char dualBand_flag: indicate client support for dual band - memcpy(send_buf+*offset, &dual_band, sizeof(unsigned char)); - *offset += sizeof(unsigned char); - - //unsigned char dotkv_flag: indicate client support for 11k/11v - dot11kv_flag = 0; -#ifdef DOT11K - if(pstat->rm.rm_cap[0] & 0x10) - dot11kv_flag |= 1; //support 11k -#endif -#ifdef CONFIG_IEEE80211V - if(pstat->bssTransSupport){ - dot11kv_flag |= 2; //support 11v - //btm_fail_count = pstat->bssTransRejectionCount; - btm_fail_count = pstat->bssTransPktSent; - } -#endif - memcpy(send_buf+*offset, &dot11kv_flag, sizeof(unsigned char)); - *offset += sizeof(unsigned char); - - memcpy(send_buf+*offset, &btm_fail_count, sizeof(unsigned char)); - *offset += sizeof(unsigned char); - - assoc_num++; - } - SMP_UNLOCK_ASOC_LIST(flags); - return assoc_num; -} - -//construct 11k neighbor report info -int construct_neighbor_report(struct rtl8192cd_priv *priv,unsigned char *send_buf,int * offset) -{ - struct stat_info *pstat; - struct list_head *phead, *plist; - int i; - -#ifdef SMP_SYNC - unsigned long flags = 0; -#endif - - phead = &priv->asoc_list; - - if (list_empty(phead)) { - return 0; - } - - SMP_LOCK_ASOC_LIST(flags); - plist = phead->next; - - while (plist != phead) { - - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - -#ifdef CONFIG_RTK_MESH - if( isMeshPoint(pstat)) - continue; -#endif -#ifdef WDS - if(pstat->state & WIFI_WDS) - continue; -#endif - if (pstat && pstat->IOTPeer == HT_IOT_PEER_RTK_APCLIENT) - continue; - - if(pstat->expire_to==0) // exclude expired STA - continue; -#if defined(DOT11K) && defined(CONFIG_IEEE80211V) - if (pstat->rcvNeighborReport && pstat->rm.neighbor_ap_num) - { - //check assoc sta support 11k or 11v - priv->sta_flag = 0; - - if (pstat->rm.rm_cap[0] & 0x10){ -#if defined(CONFIG_IEEE80211V) - if(pstat->bssTransSupport) - priv->sta_flag |= 3; //set bit 1 and bit 0 - else -#endif - priv->sta_flag |= 1; //set bit 0 - } - - memcpy(send_buf+*offset,&(priv->sta_flag),sizeof(unsigned char)); - *offset+=sizeof(unsigned char); - - memcpy(send_buf+*offset,&(pstat->hwaddr),MACADDRLEN); - *offset+=MACADDRLEN; - - memcpy(send_buf+*offset,&(pstat->rm.neighbor_ap_num),sizeof(unsigned char)); - *offset+=sizeof(unsigned char); - - for (i = 0 ; i < pstat->rm.neighbor_ap_num; i++) - { - memcpy(send_buf+*offset,&(pstat->rm.beacon_report[i].info.bssid),6); - *offset+=MACADDRLEN; - - memcpy(send_buf+*offset,&(priv->rm_neighbor_report[i].subelemnt.preference),1); - *offset+=sizeof(unsigned char); - - memcpy(send_buf+*offset,&(pstat->rm.beacon_report[i].info.RCPI),1); - *offset+=sizeof(unsigned char); - } - pstat->rm.neighbor_ap_num=0; //reset to prevent duplicate sending - - } -#endif - } - SMP_UNLOCK_ASOC_LIST(flags); - - return 1; -} - -//clear all info after send -void clear_send_info(struct rtl8192cd_priv *priv) -{ - priv->NeighborStaEntryOccupied = 0; - memset(&priv->neigbor_sta, 0, sizeof(priv->neigbor_sta)); -} - -//construct all wlan info and send -void construct_netlink_send(struct rtl8192cd_priv *priv) -{ - int offset=0, assoc_offset, i; - unsigned int neighbor_sta_num, assoc_sta_num, sta_num; - unsigned char send_buf[2048]={0}; - unsigned char channel_util; - - send_buf[offset] = WLAN_STA_INFO; - offset+=sizeof(unsigned char); - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - priv->wlanid = 0; - else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - priv->wlanid = 1; - memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->auto_channel_backup),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - memcpy(send_buf+offset,&(priv->pmib->dot11RFEntry.dot11channel),sizeof(unsigned char)); - offset+=sizeof(unsigned char); - - channel_util = 255 - priv->ext_stats.ch_utilization; - memcpy(send_buf+offset,&(channel_util),sizeof(channel_util)); - offset+=sizeof(channel_util); - - neighbor_sta_num = priv->NeighborStaEntryOccupied; - sta_num = htonl(neighbor_sta_num); - memcpy(send_buf+offset,&sta_num,sizeof(neighbor_sta_num)); - offset+=sizeof(sta_num); - - //construct neighbor unicast table info - for (i = 0; i < neighbor_sta_num; i++) - { - memcpy(send_buf+offset,&(priv->neigbor_sta[i].addr) ,MACADDRLEN); - offset += MACADDRLEN; - - send_buf[offset] = priv->neigbor_sta[i].rssi; - offset++; - } - - assoc_offset = offset; - offset += sizeof(assoc_sta_num); - assoc_sta_num = construct_assoc_sta(priv,send_buf,&offset); - assoc_sta_num = htonl(assoc_sta_num); - memcpy(send_buf+assoc_offset,&assoc_sta_num,sizeof(unsigned int)); - - construct_neighbor_report(priv,send_buf,&offset); - - //send all wlan info via netlink - rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); -} - - -int rtl_netlink_init(void) -{ - -#if defined(__LINUX_3_10__) - struct netlink_kernel_cfg cfg = { - .input = rtl_netlink_rcv, - }; - - rtl_smart_roaming_nl = netlink_kernel_create(&init_net, NETLINK_RTK, &cfg); -#else - rtl_smart_roaming_nl = netlink_kernel_create(&init_net, NETLINK_RTK, 0, rtl_netlink_rcv, NULL, THIS_MODULE); -#endif - - if(!rtl_smart_roaming_nl) - { - panic_printk(KERN_ERR "rtl_smart_roaming_nl: Cannot create netlink socket"); - return -ENOMEM; - } - - return 0; -} - -void rtl_netlink_exit(void) -{ - netlink_kernel_release(rtl_smart_roaming_nl); - pid = 0; -} - -__inline__ static int smart_roaming_block_mac_hash(unsigned char *networkAddr, int hash_size) -{ - unsigned long x; - - x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; - - return x & (hash_size - 1); -} -__inline__ static void smart_roaming_block_mac_hash_link(struct smart_roaming_block_link_list *link, struct smart_roaming_block_link_list **head) -{ - link->next_hash = *head; - - if (link->next_hash != NULL) - link->next_hash->pprev_hash = &link->next_hash; - *head = link; - link->pprev_hash = head; -} -__inline__ static void smart_roaming_block_mac_hash_unlink(struct smart_roaming_block_link_list *link) -{ - *(link->pprev_hash) = link->next_hash; - if (link->next_hash != NULL) - link->next_hash->pprev_hash = link->pprev_hash; - link->next_hash = NULL; - link->pprev_hash = NULL; -} - - -void smart_roaming_block_init(struct rtl8192cd_priv *priv) -{ - priv->sr_block.sr_block_status = 1; - - /* memory allocated structure*/ - priv->sr_block.sr_block_ent = (struct smart_roaming_block_entry *) - kmalloc((sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM), GFP_ATOMIC); - if (!priv->sr_block.sr_block_ent) { - panic_printk(KERN_ERR "Can't kmalloc for smart_roaming_block_entry (size %d)\n", sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM); - goto err; - } - memset(priv->sr_block.sr_block_machash, 0, sizeof(priv->sr_block.sr_block_machash)); - memset(priv->sr_block.sr_block_ent, 0, sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM); - -#ifdef SMP_SYNC - spin_lock_init(&(priv->sr_block.sr_block_lock)); -#endif - - return; - -err: - if(priv->sr_block.sr_block_ent) - kfree(priv->sr_block.sr_block_ent); - - return; -} - -void smart_roaming_block_deinit(struct rtl8192cd_priv *priv) -{ - priv->sr_block.sr_block_status = 0; - - if(priv->sr_block.sr_block_ent) - kfree(priv->sr_block.sr_block_ent); -} - -static struct smart_roaming_block_entry *smart_roaming_block_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - unsigned long offset; - int hash; - struct smart_roaming_block_link_list *link; - struct smart_roaming_block_entry *ent; - - offset = (unsigned long)(&((struct smart_roaming_block_entry *)0)->link_list); - hash = smart_roaming_block_mac_hash(mac, SMART_ROAMING_BLOCK_HASH_SIZE); - link = priv->sr_block.sr_block_machash[hash]; - while (link != NULL) - { - ent = (struct smart_roaming_block_entry *)((unsigned long)link - offset); - if (ent->used && !memcmp(ent->mac, mac, MACADDRLEN)) - { - return ent; - } - link = link->next_hash; - } - - return NULL; -} - -void smart_roaming_block_add(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct smart_roaming_block_entry * ent = NULL; - int i, hash; - - unsigned long flags; - SAVE_INT_AND_CLI(flags); -#ifdef SMP_SYNC - SMP_LOCK_SR_BLOCK_LIST(flags); -#endif - for (i=0; isr_block.sr_block_ent[i].used) - { - ent = &(priv->sr_block.sr_block_ent[i]); - break; - } - } - - if(ent) - { - ent->used = 1; - memcpy(ent->mac, mac, MACADDRLEN); - ent->aging = priv->pmib->sr_profile.block_aging; - hash = smart_roaming_block_mac_hash(mac, SMART_ROAMING_BLOCK_HASH_SIZE); - smart_roaming_block_mac_hash_link(&(ent->link_list), &(priv->sr_block.sr_block_machash[hash])); -#ifdef SMP_SYNC - SMP_UNLOCK_SR_BLOCK_LIST(flags); -#endif - RESTORE_INT(flags); - return; - } -#ifdef SMP_SYNC - SMP_UNLOCK_SR_BLOCK_LIST(flags); -#endif - RESTORE_INT(flags); - return; -} - -void smart_roaming_block_expire(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - int i; - unsigned long offset; - struct smart_roaming_block_link_list *link, *temp_link; - struct smart_roaming_block_entry * ent; - - unsigned long flags = 0; - SAVE_INT_AND_CLI(flags); -#ifdef SMP_SYNC - SMP_LOCK_SR_BLOCK_LIST(flags); -#endif - offset = (unsigned long)(&((struct smart_roaming_block_entry *)0)->link_list); - - for (i=0; isr_block.sr_block_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct smart_roaming_block_entry *)((unsigned long)link - offset); - if(ent->used && !mac && ent->aging) - { - ent->aging -= 1; - if(ent->aging == 0) - { - ent->used = 0; - smart_roaming_block_mac_hash_unlink(link); - } - } - else if(ent->used && mac && !memcmp(ent->mac, mac, MACADDRLEN)){ - ent->used = 0; - smart_roaming_block_mac_hash_unlink(link); - } - link = temp_link; - } - } - - RESTORE_INT(flags); -#ifdef SMP_SYNC - SMP_UNLOCK_SR_BLOCK_LIST(flags); -#endif -} - -unsigned char smart_roaming_block_check_request(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct smart_roaming_block_entry *block_ent; - unsigned char ret = 0; - unsigned long flags = 0; - - SAVE_INT_AND_CLI(flags); -#ifdef SMP_SYNC - SMP_LOCK_SR_BLOCK_LIST(flags); -#endif - block_ent = smart_roaming_block_lookup(priv, mac); - if(block_ent && block_ent->used && block_ent->aging) - ret = 1; - - RESTORE_INT(flags); -#ifdef SMP_SYNC - SMP_UNLOCK_SR_BLOCK_LIST(flags); -#endif - return ret; -} - - + +/* + * Software Smart Roaming routines + * + * $Id: rtl_smart_roaming.c, v 1.4.4.2 2016/04/30 05:27:28 Tracy Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define _8192CD_SMART_ROAMING_C_ + +#include +#include +#include +#include +#include +#include "8192cd.h" +#include "8192cd_util.h" +#include "8192cd_headers.h" + +#define NETLINK_RTK 31 +#define MAX_PAYLOAD 2048 + + +struct timer_list *timer_wlan0; +struct timer_list *timer_wlan1; + +struct sock *rtl_smart_roaming_nl = NULL; + +int wlan0_used,wlan1_used,wlan0_deleted,wlan1_deleted,msg_dropcounter; + +int pid = 0; + +static void sr_timer_rec_add() { + if (wlan0_used && wlan0_deleted ){ + add_timer(timer_wlan0); + wlan0_deleted = 0; + } + if (wlan1_used && wlan1_deleted) { + add_timer(timer_wlan1); + wlan1_deleted = 0; + } +} + + +static void sr_timer_rec_del(){ + if(wlan0_used && (wlan0_deleted == 0)){ + del_timer_sync(timer_wlan0); + wlan0_used = 0; + wlan0_deleted = 1; + } + if(wlan1_used && (wlan1_deleted == 0)){ + del_timer_sync(timer_wlan1); + wlan1_used = 0; + wlan1_deleted = 1; + } +} + +//init timer when wlan interface up +void timer_ready(struct rtl8192cd_priv *priv) +{ + if ((!strcmp(priv->dev->name, "wlan0")) && (wlan0_used != 1)){ + init_timer(&priv->send_timer_wlan0); + priv->send_timer_wlan0.expires = jiffies+RTL_SECONDS_TO_JIFFIES(5); + priv->send_timer_wlan0.data = (unsigned long) priv; + priv->send_timer_wlan0.function = send_roam_info; + priv->wlanid = 0; + timer_wlan0 = &(priv->send_timer_wlan0); + wlan0_used = 1; + wlan0_deleted = 1; + + /* 2GHz-30; 5GHz-20 */ + priv->pmib->sr_profile.load_min += 10; + } + + else if ((!strcmp(priv->dev->name, "wlan1")) && (wlan1_used != 1)){ + init_timer(&priv->send_timer_wlan1); + priv->send_timer_wlan1.expires = jiffies+RTL_SECONDS_TO_JIFFIES(4); + priv->send_timer_wlan1.data = (unsigned long) priv; + priv->send_timer_wlan1.function = send_roam_info; + priv->wlanid = 1; + timer_wlan1 = &(priv->send_timer_wlan1); + wlan1_used = 1; + wlan1_deleted = 1; + + /* 2GHz-30; 5GHz-25 */ + priv->pmib->sr_profile.signal_min += 5; + priv->pmib->sr_profile.signal_max += 10; + } + if(pid != 0){ + sr_timer_rec_add(); + } +} + +//delete timer when wlan interface down +void timer_del(struct rtl8192cd_priv *priv) +{ + if (!strcmp(priv->dev->name, "wlan0")){ + del_timer_sync(&priv->send_timer_wlan0); + wlan0_used = 0; + wlan0_deleted = 1; + } + else if (!strcmp(priv->dev->name, "wlan1")){ + del_timer_sync(&priv->send_timer_wlan1); + wlan1_used = 0; + wlan1_deleted = 1; + } +} + +//netlink send msg +void rtl_netlink_rcv(struct sk_buff *skb) +{ + struct nlmsghdr *nlh = NULL; + unsigned char *message; + + if(skb == NULL) { + panic_printk(KERN_INFO "%s: skb is NULL\n", __FUNCTION__); + return ; + } + + nlh=(struct nlmsghdr*)skb->data; + //printk(KERN_INFO "kernel received msg payload:%s\n",(unsigned char*)NLMSG_DATA(nlh)); + + message = NLMSG_DATA(nlh); + + if (*message == 'S') + { + pid = nlh->nlmsg_pid; //pid of sending process + sr_timer_rec_add(); + } + + + if (*message == 'F') + { + panic_printk("\nSR received delete!\n"); + sr_timer_rec_del(); + } + +} + +//netlink send msg +void rtl_netlink_sendmsg(int pid, struct sock *nl_sk,char *data, int data_len) +{ + struct nlmsghdr *nlh; + struct sk_buff *skb; + unsigned int skblen; + unsigned char *datab; + const char *fn; + int err; + + if(pid == 0) + return; + + if(data_len > MAX_PAYLOAD) + { + err = -ENOBUFS; + fn = "data_len"; + goto msg_fail; + } + + skblen = NLMSG_SPACE(data_len + 4); //+len + skb = alloc_skb(skblen, GFP_ATOMIC); + + if(!skb) + { + err = -ENOBUFS; + fn = "alloc_skb"; + goto msg_fail; + } + + nlh = nlmsg_put(skb,0,0,0,skblen-sizeof(*nlh),0); + + if(!nlh) + { + err = -ENOBUFS; + fn = "nlmsg_put"; + goto msg_fail_skb; + } + +#if defined(__LINUX_3_10__) + NETLINK_CB(skb).portid = 0; //from kernel +#else + NETLINK_CB(skb).pid = 0; //from kernel +#endif + NETLINK_CB(skb).dst_group = 0; //unicast + + datab = NLMSG_DATA(nlh); + memset(datab, 0, data_len+4); + memcpy(datab,&data_len,4); //+ total len + memcpy(datab+4,data, data_len); + + nlh->nlmsg_len = NLMSG_HDRLEN + data_len + 4; + + //printk("check data_len before send=%d\n",data_len); + err= netlink_unicast(nl_sk, skb, pid, MSG_DONTWAIT); + + if (err < 0) + { + fn = "nlmsg_unicast"; + goto msg_fail; //nlmsg_unicast already kfree_skb + } + + return; + +msg_fail_skb: + kfree_skb(skb); + +msg_fail: + if(msg_dropcounter < 3){ + msg_dropcounter++; + panic_printk("[%s] drop msg: pid=%d msglen=%d %s: err=%d\n",__FUNCTION__, pid, data_len, fn, err); + } + return; +} + +#ifdef STA_CONTROL +void notify_hidden_ap(struct rtl8192cd_priv *priv, int type) +{ + if(!priv->stactrl.stactrl_enable_hiddenAP ||priv->stactrl.stactrl_prefer) + return; + + int offset =0; + unsigned char send_buf[10]={0}; + + if (!strcmp(priv->dev->name, "wlan0")) + priv->wlanid = 0; + else if (!strcmp(priv->dev->name, "wlan1")) + priv->wlanid = 1; + + send_buf[offset] = type; + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->vap_id),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); +} +#endif + +void notify_new_sta(struct rtl8192cd_priv *priv, unsigned char *mac,int type, unsigned char rssi) +{ + int offset =0; + + unsigned char send_buf[10]={0}; + unsigned char channel_util; + + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + priv->wlanid = 0; + else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + priv->wlanid = 1; + + send_buf[offset] = type; + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->pmib->dot11RFEntry.dot11channel),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + channel_util = 255 - priv->ext_stats.ch_utilization; + memcpy(send_buf+offset,&(channel_util),sizeof(channel_util)); + offset+=sizeof(channel_util); + + memcpy(send_buf+offset, mac, MACADDRLEN); + offset += MACADDRLEN; + + memcpy(send_buf+offset,&(rssi),sizeof(rssi)); + offset+=sizeof(rssi); + + rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); +} + +//Get neighbor channel unicast Null data rssi +void add_neighbor_unicast_sta(struct rtl8192cd_priv *priv,unsigned char* addr, unsigned char rssi) +{ + int i, idx=-1, idx2 =0; + unsigned char rssi_input; + for (i = 0; i < MAX_NEIGHBOR_STA; i++) { + if (priv->neigbor_sta[i].used == 0) { + if (idx < 0) + idx = i; //search for empty entry + continue; + } + if (!memcmp(priv->neigbor_sta[i].addr, addr, MACADDRLEN)) { + idx2 = i; + break; // check if it is already in the list + } + } + if (idx >= 0){ + rssi_input = rssi; + memcpy(priv->neigbor_sta[idx].addr, addr, MACADDRLEN); + priv->neigbor_sta[idx].used = 1; + priv->neigbor_sta[idx].Entry = idx; //check which entry is the neighbor sta recorded + priv->neigbor_sta[idx].rssi = rssi_input; + priv->NeighborStaEntryOccupied++; + + } + else if (idx2){ + rssi_input = ((priv->neigbor_sta[idx2].rssi * 7)+(rssi * 3)) / 10; + priv->neigbor_sta[idx2].rssi = rssi_input; + + return; + } + else if (priv->NeighborStaEntryOccupied == MAX_NEIGHBOR_STA) {// sta list full, need to replace sta + idx = priv->NeighborStaEntryNum; + for (i = 0; i < MAX_NEIGHBOR_STA; i++) { + if (!memcmp(priv->neigbor_sta[i].addr, addr, MACADDRLEN)) + return; // check if it is already in the list + } + memcpy(priv->neigbor_sta[idx].addr, addr, MACADDRLEN); + priv->neigbor_sta[idx].used = 1; + priv->neigbor_sta[idx].Entry = idx; + priv->neigbor_sta[idx].rssi = rssi; + priv->NeighborStaEntryNum++; + if( priv->NeighborStaEntryNum == MAX_NEIGHBOR_STA) + priv->NeighborStaEntryNum = 0; // Reset entry counter; + return; + } +} + +//construct associated sta info +unsigned char construct_assoc_sta(struct rtl8192cd_priv *priv,unsigned char *send_buf, int * offset) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + unsigned char data_rate; + unsigned char assoc_num = 0; + unsigned int link_time = 0; + unsigned int tx_throughput = 0; + unsigned int rx_throughput = 0; + unsigned char dot11kv_flag = 0; + unsigned char dual_band = 0; + unsigned char btm_fail_count = 0; +#ifdef SMP_SYNC + unsigned long flags = 0; +#endif + + phead = &priv->asoc_list; + + if (list_empty(phead)) { + return 0; + } + + SMP_LOCK_ASOC_LIST(flags); + plist = phead->next; + + //construct associated sta info + while (plist != phead) { + + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + +#ifdef CONFIG_RTK_MESH + if( isMeshPoint(pstat)) + continue; +#endif +#ifdef WDS + if(pstat->state & WIFI_WDS) + continue; +#endif +//printk("pstat->IOTPeer=%d\n",pstat->IOTPeer); + if (pstat && pstat->IOTPeer == HT_IOT_PEER_RTK_APCLIENT) + continue; + + if(pstat->expire_to==0) // exclude expired STA + continue; + + memcpy(send_buf+*offset,&(pstat->hwaddr), MACADDRLEN); + *offset += MACADDRLEN; + + memcpy(send_buf+*offset,&(pstat->rssi),sizeof(unsigned char)); + *offset+=sizeof(unsigned char); + + //data rate only when tx pkts increase within 5s + if (pstat->tx_pkts > pstat->tx_pkts_pre) + data_rate = (pstat->current_tx_rate >= VHT_RATE_ID) ? ((pstat->current_tx_rate - VHT_RATE_ID)%10):((pstat->current_tx_rate >= HT_RATE_ID)? (pstat->current_tx_rate - HT_RATE_ID) : pstat->current_tx_rate/2); + else + data_rate = 255; //will not trigger data_rate threshold + + memcpy(send_buf+*offset,&data_rate,sizeof(unsigned char)); + *offset+=sizeof(unsigned char); + + //int link_time: host byte order convert to network byte order + link_time=htonl(pstat->link_time); + memcpy(send_buf+*offset,&(link_time),sizeof(link_time)); + *offset+=sizeof(link_time); + + //int tx_tp: host byte order convert to network byte order + tx_throughput = htonl(pstat->tx_avarage); + memcpy(send_buf+*offset, &(tx_throughput), sizeof(tx_throughput)); + *offset += sizeof(tx_throughput); + + //int rx_tp: host byte order convert to network byte order + rx_throughput = htonl(pstat->rx_avarage); + memcpy(send_buf+*offset, &(rx_throughput),sizeof(rx_throughput)); + *offset += sizeof(rx_throughput); + +#ifdef CONFIG_IEEE80211V + dual_band = pstat->dual_band_capable; +#endif + + //unsigned char dualBand_flag: indicate client support for dual band + memcpy(send_buf+*offset, &dual_band, sizeof(unsigned char)); + *offset += sizeof(unsigned char); + + //unsigned char dotkv_flag: indicate client support for 11k/11v + dot11kv_flag = 0; +#ifdef DOT11K + if(pstat->rm.rm_cap[0] & 0x10) + dot11kv_flag |= 1; //support 11k +#endif +#ifdef CONFIG_IEEE80211V + if(pstat->bssTransSupport){ + dot11kv_flag |= 2; //support 11v + //btm_fail_count = pstat->bssTransRejectionCount; + btm_fail_count = pstat->bssTransPktSent; + } +#endif + memcpy(send_buf+*offset, &dot11kv_flag, sizeof(unsigned char)); + *offset += sizeof(unsigned char); + + memcpy(send_buf+*offset, &btm_fail_count, sizeof(unsigned char)); + *offset += sizeof(unsigned char); + + assoc_num++; + } + SMP_UNLOCK_ASOC_LIST(flags); + return assoc_num; +} + +//construct 11k neighbor report info +int construct_neighbor_report(struct rtl8192cd_priv *priv,unsigned char *send_buf,int * offset) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + int i; + +#ifdef SMP_SYNC + unsigned long flags = 0; +#endif + + phead = &priv->asoc_list; + + if (list_empty(phead)) { + return 0; + } + + SMP_LOCK_ASOC_LIST(flags); + plist = phead->next; + + while (plist != phead) { + + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + +#ifdef CONFIG_RTK_MESH + if( isMeshPoint(pstat)) + continue; +#endif +#ifdef WDS + if(pstat->state & WIFI_WDS) + continue; +#endif + if (pstat && pstat->IOTPeer == HT_IOT_PEER_RTK_APCLIENT) + continue; + + if(pstat->expire_to==0) // exclude expired STA + continue; +#if defined(DOT11K) && defined(CONFIG_IEEE80211V) + if (pstat->rcvNeighborReport && pstat->rm.neighbor_ap_num) + { + //check assoc sta support 11k or 11v + priv->sta_flag = 0; + + if (pstat->rm.rm_cap[0] & 0x10){ +#if defined(CONFIG_IEEE80211V) + if(pstat->bssTransSupport) + priv->sta_flag |= 3; //set bit 1 and bit 0 + else +#endif + priv->sta_flag |= 1; //set bit 0 + } + + memcpy(send_buf+*offset,&(priv->sta_flag),sizeof(unsigned char)); + *offset+=sizeof(unsigned char); + + memcpy(send_buf+*offset,&(pstat->hwaddr),MACADDRLEN); + *offset+=MACADDRLEN; + + memcpy(send_buf+*offset,&(pstat->rm.neighbor_ap_num),sizeof(unsigned char)); + *offset+=sizeof(unsigned char); + + for (i = 0 ; i < pstat->rm.neighbor_ap_num; i++) + { + memcpy(send_buf+*offset,&(pstat->rm.beacon_report[i].info.bssid),6); + *offset+=MACADDRLEN; + + memcpy(send_buf+*offset,&(priv->rm_neighbor_report[i].subelemnt.preference),1); + *offset+=sizeof(unsigned char); + + memcpy(send_buf+*offset,&(pstat->rm.beacon_report[i].info.RCPI),1); + *offset+=sizeof(unsigned char); + } + pstat->rm.neighbor_ap_num=0; //reset to prevent duplicate sending + + } +#endif + } + SMP_UNLOCK_ASOC_LIST(flags); + + return 1; +} + +//clear all info after send +void clear_send_info(struct rtl8192cd_priv *priv) +{ + priv->NeighborStaEntryOccupied = 0; + memset(&priv->neigbor_sta, 0, sizeof(priv->neigbor_sta)); +} + +//construct all wlan info and send +void construct_netlink_send(struct rtl8192cd_priv *priv) +{ + int offset=0, assoc_offset, i; + unsigned int neighbor_sta_num, assoc_sta_num, sta_num; + unsigned char send_buf[2048]={0}; + unsigned char channel_util; + + send_buf[offset] = WLAN_STA_INFO; + offset+=sizeof(unsigned char); + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + priv->wlanid = 0; + else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + priv->wlanid = 1; + memcpy(send_buf+offset,&(priv->wlanid),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->auto_channel_backup),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + memcpy(send_buf+offset,&(priv->pmib->dot11RFEntry.dot11channel),sizeof(unsigned char)); + offset+=sizeof(unsigned char); + + channel_util = 255 - priv->ext_stats.ch_utilization; + memcpy(send_buf+offset,&(channel_util),sizeof(channel_util)); + offset+=sizeof(channel_util); + + neighbor_sta_num = priv->NeighborStaEntryOccupied; + sta_num = htonl(neighbor_sta_num); + memcpy(send_buf+offset,&sta_num,sizeof(neighbor_sta_num)); + offset+=sizeof(sta_num); + + //construct neighbor unicast table info + for (i = 0; i < neighbor_sta_num; i++) + { + memcpy(send_buf+offset,&(priv->neigbor_sta[i].addr) ,MACADDRLEN); + offset += MACADDRLEN; + + send_buf[offset] = priv->neigbor_sta[i].rssi; + offset++; + } + + assoc_offset = offset; + offset += sizeof(assoc_sta_num); + assoc_sta_num = construct_assoc_sta(priv,send_buf,&offset); + assoc_sta_num = htonl(assoc_sta_num); + memcpy(send_buf+assoc_offset,&assoc_sta_num,sizeof(unsigned int)); + + construct_neighbor_report(priv,send_buf,&offset); + + //send all wlan info via netlink + rtl_netlink_sendmsg(pid,rtl_smart_roaming_nl,send_buf,offset); +} + + +int rtl_netlink_init(void) +{ + +#if defined(__LINUX_3_10__) + struct netlink_kernel_cfg cfg = { + .input = rtl_netlink_rcv, + }; + + rtl_smart_roaming_nl = netlink_kernel_create(&init_net, NETLINK_RTK, &cfg); +#else + rtl_smart_roaming_nl = netlink_kernel_create(&init_net, NETLINK_RTK, 0, rtl_netlink_rcv, NULL, THIS_MODULE); +#endif + + if(!rtl_smart_roaming_nl) + { + panic_printk(KERN_ERR "rtl_smart_roaming_nl: Cannot create netlink socket"); + return -ENOMEM; + } + + return 0; +} + +void rtl_netlink_exit(void) +{ + netlink_kernel_release(rtl_smart_roaming_nl); + pid = 0; +} + +__inline__ static int smart_roaming_block_mac_hash(unsigned char *networkAddr, int hash_size) +{ + unsigned long x; + + x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; + + return x & (hash_size - 1); +} +__inline__ static void smart_roaming_block_mac_hash_link(struct smart_roaming_block_link_list *link, struct smart_roaming_block_link_list **head) +{ + link->next_hash = *head; + + if (link->next_hash != NULL) + link->next_hash->pprev_hash = &link->next_hash; + *head = link; + link->pprev_hash = head; +} +__inline__ static void smart_roaming_block_mac_hash_unlink(struct smart_roaming_block_link_list *link) +{ + *(link->pprev_hash) = link->next_hash; + if (link->next_hash != NULL) + link->next_hash->pprev_hash = link->pprev_hash; + link->next_hash = NULL; + link->pprev_hash = NULL; +} + + +void smart_roaming_block_init(struct rtl8192cd_priv *priv) +{ + priv->sr_block.sr_block_status = 1; + + /* memory allocated structure*/ + priv->sr_block.sr_block_ent = (struct smart_roaming_block_entry *) + kmalloc((sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM), GFP_ATOMIC); + if (!priv->sr_block.sr_block_ent) { + panic_printk(KERN_ERR "Can't kmalloc for smart_roaming_block_entry (size %d)\n", sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM); + goto err; + } + memset(priv->sr_block.sr_block_machash, 0, sizeof(priv->sr_block.sr_block_machash)); + memset(priv->sr_block.sr_block_ent, 0, sizeof(struct smart_roaming_block_entry) * SMART_ROAMING_BLOCK_MAX_NUM); + +#ifdef SMP_SYNC + spin_lock_init(&(priv->sr_block.sr_block_lock)); +#endif + + return; + +err: + if(priv->sr_block.sr_block_ent) + kfree(priv->sr_block.sr_block_ent); + + return; +} + +void smart_roaming_block_deinit(struct rtl8192cd_priv *priv) +{ + priv->sr_block.sr_block_status = 0; + + if(priv->sr_block.sr_block_ent) + kfree(priv->sr_block.sr_block_ent); +} + +static struct smart_roaming_block_entry *smart_roaming_block_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + unsigned long offset; + int hash; + struct smart_roaming_block_link_list *link; + struct smart_roaming_block_entry *ent; + + offset = (unsigned long)(&((struct smart_roaming_block_entry *)0)->link_list); + hash = smart_roaming_block_mac_hash(mac, SMART_ROAMING_BLOCK_HASH_SIZE); + link = priv->sr_block.sr_block_machash[hash]; + while (link != NULL) + { + ent = (struct smart_roaming_block_entry *)((unsigned long)link - offset); + if (ent->used && !memcmp(ent->mac, mac, MACADDRLEN)) + { + return ent; + } + link = link->next_hash; + } + + return NULL; +} + +void smart_roaming_block_add(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct smart_roaming_block_entry * ent = NULL; + int i, hash; + + unsigned long flags; + SAVE_INT_AND_CLI(flags); +#ifdef SMP_SYNC + SMP_LOCK_SR_BLOCK_LIST(flags); +#endif + for (i=0; isr_block.sr_block_ent[i].used) + { + ent = &(priv->sr_block.sr_block_ent[i]); + break; + } + } + + if(ent) + { + ent->used = 1; + memcpy(ent->mac, mac, MACADDRLEN); + ent->aging = priv->pmib->sr_profile.block_aging; + hash = smart_roaming_block_mac_hash(mac, SMART_ROAMING_BLOCK_HASH_SIZE); + smart_roaming_block_mac_hash_link(&(ent->link_list), &(priv->sr_block.sr_block_machash[hash])); +#ifdef SMP_SYNC + SMP_UNLOCK_SR_BLOCK_LIST(flags); +#endif + RESTORE_INT(flags); + return; + } +#ifdef SMP_SYNC + SMP_UNLOCK_SR_BLOCK_LIST(flags); +#endif + RESTORE_INT(flags); + return; +} + +void smart_roaming_block_expire(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + int i; + unsigned long offset; + struct smart_roaming_block_link_list *link, *temp_link; + struct smart_roaming_block_entry * ent; + + unsigned long flags = 0; + SAVE_INT_AND_CLI(flags); +#ifdef SMP_SYNC + SMP_LOCK_SR_BLOCK_LIST(flags); +#endif + offset = (unsigned long)(&((struct smart_roaming_block_entry *)0)->link_list); + + for (i=0; isr_block.sr_block_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct smart_roaming_block_entry *)((unsigned long)link - offset); + if(ent->used && !mac && ent->aging) + { + ent->aging -= 1; + if(ent->aging == 0) + { + ent->used = 0; + smart_roaming_block_mac_hash_unlink(link); + } + } + else if(ent->used && mac && !memcmp(ent->mac, mac, MACADDRLEN)){ + ent->used = 0; + smart_roaming_block_mac_hash_unlink(link); + } + link = temp_link; + } + } + + RESTORE_INT(flags); +#ifdef SMP_SYNC + SMP_UNLOCK_SR_BLOCK_LIST(flags); +#endif +} + +unsigned char smart_roaming_block_check_request(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct smart_roaming_block_entry *block_ent; + unsigned char ret = 0; + unsigned long flags = 0; + + SAVE_INT_AND_CLI(flags); +#ifdef SMP_SYNC + SMP_LOCK_SR_BLOCK_LIST(flags); +#endif + block_ent = smart_roaming_block_lookup(priv, mac); + if(block_ent && block_ent->used && block_ent->aging) + ret = 1; + + RESTORE_INT(flags); +#ifdef SMP_SYNC + SMP_UNLOCK_SR_BLOCK_LIST(flags); +#endif + return ret; +} + + diff --git a/package/kernel/rtl8192cd/8192cd_sme.c b/package/kernel/rtl8192cd/8192cd_sme.c index 206a424a1e8..aac146be025 100644 --- a/package/kernel/rtl8192cd/8192cd_sme.c +++ b/package/kernel/rtl8192cd/8192cd_sme.c @@ -30569,8 +30569,8 @@ void clean_for_join(struct rtl8192cd_priv *priv) ((priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _TKIP_PRIVACY_) || (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _CCMP_PRIVACY_) || (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_WPA_MIXED_PRIVACY_))) { -/////// priv->wpa_global_info->GN = 0; -/////// memset(&priv->wpa_global_info->GTK, 0, NumGroupKey * GTK_LEN); + priv->wpa_global_info->GN = 0; + memset(&priv->wpa_global_info->GTK, 0, NumGroupKey * GTK_LEN); memset(&(priv->pmib->dot11GroupKeysTable), 0, sizeof(struct Dot11KeyMappingsEntry)); #ifdef UNIVERSAL_REPEATER if (IS_ROOT_INTERFACE(priv)) diff --git a/package/kernel/rtl8192cd/8192cd_sta_control.c b/package/kernel/rtl8192cd/8192cd_sta_control.c index 93f7db4ef4f..cf1f62acf70 100644 --- a/package/kernel/rtl8192cd/8192cd_sta_control.c +++ b/package/kernel/rtl8192cd/8192cd_sta_control.c @@ -1,2300 +1,2300 @@ -/* - * a4 sta functions - * - * $Id: 8192cd_a4_sta.c,v 1.1 2010/10/13 06:38:58 davidhsu Exp $ - * - * Copyright (c) 2010 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define _8192CD_STA_CONTROL_C_ - -#ifdef __KERNEL__ -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" -#include "./8192cd.h" -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" - -#ifdef STA_CONTROL -#define STA_CONTROL_DEBUGMSG -#ifdef STA_CONTROL_DEBUGMSG -unsigned char stactrl_debug_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; - -int DEBUG_TIME_INETRVAL = 5; - -#define STACTRL_DEBUG(mac, fmt, args...) \ - do { \ - if(memcmp(mac, stactrl_debug_mac, MACADDRLEN)==0) \ - panic_printk("[%s, %d][%s] "fmt" from %02x:%02x:%02x:%02x:%02x:%02x\n",__func__,__LINE__, priv->dev->name, ## args, mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]); \ - }while(0) - -#define STACTRL_INIT_DEBUG(fmt, args...) panic_printk("[%s, %d][%s] "fmt, __func__,__LINE__, priv->dev->name, ## args); - -#else -#define STACTRL_DEBUG(mac, fmt, args...) {} -#define STACTRL_INIT_DEBUG -#endif - -__inline__ static int stactrl_mac_hash(unsigned char *networkAddr, int hash_size) -{ - unsigned long x; - - x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; - - return x & (hash_size - 1); -} - -__inline__ static void stactrl_mac_hash_link(struct stactrl_link_list *link, struct stactrl_link_list **head) -{ - link->next_hash = *head; - - if (link->next_hash != NULL) - link->next_hash->pprev_hash = &link->next_hash; - *head = link; - link->pprev_hash = head; -} - -__inline__ static void stactrl_mac_hash_unlink(struct stactrl_link_list *link) -{ - *(link->pprev_hash) = link->next_hash; - if (link->next_hash != NULL) - link->next_hash->pprev_hash = link->pprev_hash; - link->next_hash = NULL; - link->pprev_hash = NULL; -} - - -#ifdef CONFIG_RTL_PROC_NEW -int stactrl_info_read(struct seq_file *s, void *data) -#else -int stactrl_info_read(char *buf, char **start, off_t offset, int length, int *eof, void *data) -#endif -{ - struct net_device *dev = PROC_GET_DEV(); - struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); - struct stactrl_preferband_entry * prefer_ent; - struct stactrl_block_entry * block_ent; - - - int i; - int pos = 0; - PRINT_ONE(" -- sta control info -- ", "%s", 1); - PRINT_ONE(priv->stactrl.stactrl_status, " sta control status: %d", 1); - PRINT_ONE(priv->stactrl.stactrl_prefer, " is prefer band: %d", 1); - PRINT_ONE(STA_CONTROL_ALGO, " algorithm: %d", 1); - - if(priv->stactrl.stactrl_status) { - if(priv->stactrl.stactrl_prefer) - { - PRINT_ONE(priv->stactrl.stactrl_priv_sc->dev->name, " non-prefer band: %s", 1); - PRINT_ONE(" -- prefer band capable client list -- ", "%s", 1); - for (i=0; istactrl.stactrl_preferband_ent[i]); - if (prefer_ent->used) - { - PRINT_ARRAY_ARG(" STA_MAC: ", prefer_ent->mac, "%02x", MACADDRLEN); - PRINT_ONE(prefer_ent->rssi, " rssi: %d", 1); - PRINT_ONE(prefer_ent->aging, " aging: %d", 1); -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - PRINT_ONE(prefer_ent->retry, " retry: %d", 1); - PRINT_ONE(prefer_ent->local, " local: %d", 1); - if(prefer_ent->kickoff > 0) - PRINT_ONE(prefer_ent->kickoff, " kickoff: %d", 1); - } - } - if(STACTRL_BLOCK_5G){ - /* prefer band block entry */ - PRINT_ONE(" -- prefer band blocklist -- ", "%s", 1); - for (i=0; istactrl.stactrl_block_ent[i]); - if (block_ent->used) - { - PRINT_ARRAY_ARG(" Block STA_MAC: ", block_ent->mac, "%02x", MACADDRLEN); - PRINT_ONE(block_ent->timerX, " timerX: %d", 1); - PRINT_ONE(block_ent->retryY, " retryY: %d", 1); - PRINT_ONE(block_ent->aging, " aging: %d", 1); - } - } - } -#endif - } - else - { - PRINT_ONE(priv->stactrl.stactrl_priv_sc->dev->name, " prefer band: %s", 1); - PRINT_ONE(" -- non-prefer band blocklist -- ", "%s", 1); - for (i=0; istactrl.stactrl_block_ent[i]); - if (block_ent->used) - { - PRINT_ARRAY_ARG(" STA_MAC: ", block_ent->mac, "%02x", MACADDRLEN); - PRINT_ONE(block_ent->timerX, " timerX: %d", 1); - PRINT_ONE(block_ent->retryY, " retryY: %d", 1); -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - PRINT_ONE(block_ent->aging, " aging: %d", 1); -#endif - } - } - - if(STACTRL_BLOCK_5G){ - PRINT_ONE(" -- non-prefer band prefer list -- ", "%s", 1); - for (i=0; istactrl.stactrl_preferband_ent[i]); - if (prefer_ent->used) - { - PRINT_ARRAY_ARG(" STA_MAC: ", prefer_ent->mac, "%02x", MACADDRLEN); - PRINT_ONE(prefer_ent->rssi, " rssi: %d", 1); - PRINT_ONE(prefer_ent->aging, " aging: %d", 1); - - PRINT_ONE(prefer_ent->retry, " retry: %d", 1); - PRINT_ONE(prefer_ent->local, " local: %d", 1); - if(prefer_ent->kickoff > 0) - PRINT_ONE(prefer_ent->kickoff, " kickoff: %d", 1); - } - } - } - } - } - -#ifdef STA_CONTROL_DEBUGMSG - PRINT_ONE(" -- debug mac -- ", "%s", 1); - PRINT_ARRAY_ARG(" STA_MAC: ", stactrl_debug_mac, "%02x", MACADDRLEN); -#endif - return pos; -} - -int stactrl_info_write(struct file *file, const char *buffer, - unsigned long count, void *data) -{ -#ifdef STA_CONTROL_DEBUGMSG - if (buffer) - { - get_array_val(stactrl_debug_mac, (char *)buffer, count); - } -#endif - return count; -} - - -void stactrl_init(struct rtl8192cd_priv *priv) -{ - struct rtl8192cd_priv *priv_sc; - struct rtl8192cd_priv *prefer_priv; - int i; - - STACTRL_INIT_DEBUG("groupID: %d\n", priv->pmib->staControl.stactrl_groupID); - - if(priv->pmib->staControl.stactrl_enable > 1) - priv->pmib->staControl.stactrl_enable = 1; - if(priv->pmib->staControl.stactrl_prefer_band > 1) - priv->pmib->staControl.stactrl_prefer_band = 1; - - priv->stactrl.stactrl_status = 0; - priv->stactrl.stactrl_priv_sc = NULL; - priv->stactrl.stactrl_block5G = 0; - priv->stactrl.stactrl_enable_hiddenAP = 0; - - if(!(OPMODE & WIFI_AP_STATE) || priv->pmib->staControl.stactrl_enable == 0) { - STACTRL_INIT_DEBUG("WARNING: not ap mode or not enabled\n"); - return; - } - - if(priv->pmib->staControl.stactrl_functions & BIT(0)){ - STACTRL_INIT_DEBUG("Enable block_5G feature\n"); - priv->stactrl.stactrl_block5G = 1; - } - else - STACTRL_INIT_DEBUG("Disable block_5G feature\n"); - - if(priv->pmib->staControl.stactrl_functions & BIT(1)){ - STACTRL_INIT_DEBUG("Enable hiddenAP feature\n"); - priv->stactrl.stactrl_enable_hiddenAP = 1; - } - else - STACTRL_INIT_DEBUG("Disable hiddenAP feature\n"); - - /*search other band to find the priv with same groupID*/ - for(i = 0; i < RTL8192CD_NUM_VWLAN+1; i++) { - if(i == 0) { - priv_sc = GET_ROOT(priv)->stactrl.stactrl_rootpriv_sc; - } - #ifdef MBSSID - else { /*search vap of other band*/ - priv_sc = GET_ROOT(priv)->stactrl.stactrl_rootpriv_sc->pvap_priv[i - 1]; - - } - #endif - if((priv_sc!=NULL) && priv_sc->pmib->staControl.stactrl_groupID == priv->pmib->staControl.stactrl_groupID && - IS_DRV_OPEN(priv_sc) && - priv_sc->pmib->staControl.stactrl_enable == 1 && - (priv_sc->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) && - priv_sc->stactrl.stactrl_status == 0) - { - priv->stactrl.stactrl_priv_sc = priv_sc; - break; - } - } - - - if(priv->stactrl.stactrl_priv_sc == NULL || priv_sc == NULL) { /*can not find other band with same groupID*/ - STACTRL_INIT_DEBUG("WARNING: not find available priv\n"); - return; - } - - STACTRL_INIT_DEBUG("find other band : %s\n", priv->stactrl.stactrl_priv_sc->dev->name); - priv_sc->stactrl.stactrl_priv_sc = priv; - - - /*find other band's priv with same groupID*/ - /*setting prefer band and non-prefer band*/ - priv->stactrl.stactrl_prefer = priv->pmib->staControl.stactrl_prefer_band; - priv->stactrl.stactrl_priv_sc->stactrl.stactrl_prefer = priv->pmib->staControl.stactrl_prefer_band?0:1; - - - /* memory allocated structure*/ - if(priv->stactrl.stactrl_prefer) { - prefer_priv = priv; - } - else { - prefer_priv = priv->stactrl.stactrl_priv_sc; - } - priv_sc = prefer_priv->stactrl.stactrl_priv_sc; - - - STACTRL_INIT_DEBUG("prefer band : %s, non-prefer band: %s\n", prefer_priv->dev->name, priv_sc->dev->name); - - /*check SSID of different bands */ - if(strcmp(prefer_priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, priv_sc->pmib->dot11StationConfigEntry.dot11DesiredSSID)){ - STACTRL_INIT_DEBUG("WARNING: different SSID of preferband(%s) and non-preferband(%s)\n", - prefer_priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, - priv_sc->pmib->dot11StationConfigEntry.dot11DesiredSSID); - return; - } - - prefer_priv->stactrl.stactrl_preferband_ent = (struct stactrl_preferband_entry *) - kmalloc((sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM), GFP_ATOMIC); - if (!prefer_priv->stactrl.stactrl_preferband_ent) { - printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); - goto err; - } - memset(prefer_priv->stactrl.stactrl_preferband_machash, 0, sizeof(prefer_priv->stactrl.stactrl_preferband_machash)); - memset(prefer_priv->stactrl.stactrl_preferband_ent, 0, sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); - - /* malloc prefrband_ent for non-prefer band */ - if(STACTRL_BLOCK_5G){ - priv_sc->stactrl.stactrl_preferband_ent = (struct stactrl_preferband_entry *) - kmalloc((sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM), GFP_ATOMIC); - if (!priv_sc->stactrl.stactrl_preferband_ent) { - printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); - goto err; - } - memset(priv_sc->stactrl.stactrl_preferband_machash, 0, sizeof(priv_sc->stactrl.stactrl_preferband_machash)); - memset(priv_sc->stactrl.stactrl_preferband_ent, 0, sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); - } - - priv_sc->stactrl.stactrl_block_ent = (struct stactrl_block_entry *) - kmalloc((sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM), GFP_ATOMIC); - if (!priv_sc->stactrl.stactrl_block_ent) { - printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); - goto err; - } - memset(priv_sc->stactrl.stactrl_block_machash, 0, sizeof(priv_sc->stactrl.stactrl_block_machash)); - memset(priv_sc->stactrl.stactrl_block_ent, 0, sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); - -/* malloc stactrl_block_ent for prefer band */ - if(STACTRL_BLOCK_5G){ - prefer_priv->stactrl.stactrl_block_ent = (struct stactrl_block_entry *) - kmalloc((sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM), GFP_ATOMIC); - if (!prefer_priv->stactrl.stactrl_block_ent) { - printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); - goto err; - } - memset(prefer_priv->stactrl.stactrl_block_machash, 0, sizeof(prefer_priv->stactrl.stactrl_block_machash)); - memset(prefer_priv->stactrl.stactrl_block_ent, 0, sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); - } - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 - init_timer(&priv_sc->stactrl.stactrl_timer); - priv_sc->stactrl.stactrl_timer.data = (unsigned long) priv_sc; - priv_sc->stactrl.stactrl_timer.function = stactrl_non_prefer_expire; - mod_timer(&priv_sc->stactrl.stactrl_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(STACTRL_NON_PREFER_TIMER)); -#endif - -#ifdef SMP_SYNC - spin_lock_init(&(prefer_priv->stactrl.stactrl_lock)); - spin_lock_init(&(priv_sc->stactrl.stactrl_lock)); -#endif - - /*start up sta control*/ - prefer_priv->stactrl.stactrl_status = 1; - priv_sc->stactrl.stactrl_status = 1; - priv_sc->stactrl.stactrl_hiddenAP_aging = 0; - return; - - -err: - if(prefer_priv->stactrl.stactrl_preferband_ent) - kfree(prefer_priv->stactrl.stactrl_preferband_ent); - if(priv_sc->stactrl.stactrl_block_ent) - kfree(priv_sc->stactrl.stactrl_block_ent); - if(STACTRL_BLOCK_5G){ - if(priv_sc->stactrl.stactrl_preferband_ent) - kfree(priv_sc->stactrl.stactrl_preferband_ent); - if(prefer_priv->stactrl.stactrl_block_ent) - kfree(prefer_priv->stactrl.stactrl_block_ent); - } - - - return; -} - - -void stactrl_deinit(struct rtl8192cd_priv *priv) -{ - struct rtl8192cd_priv *priv_sc; - struct rtl8192cd_priv *prefer_priv; - - STACTRL_INIT_DEBUG("\n"); - if(priv->stactrl.stactrl_status) { - if(priv->stactrl.stactrl_prefer) { - prefer_priv = priv; - } - else { - prefer_priv = priv->stactrl.stactrl_priv_sc; - } - priv_sc = prefer_priv->stactrl.stactrl_priv_sc; - - STACTRL_INIT_DEBUG("prefer band : %s, non-prefer band: %s\n", prefer_priv->dev->name, priv_sc->dev->name); - - if(prefer_priv->stactrl.stactrl_preferband_ent) - kfree(prefer_priv->stactrl.stactrl_preferband_ent); - if(priv_sc->stactrl.stactrl_block_ent) - kfree(priv_sc->stactrl.stactrl_block_ent); - - if(STACTRL_BLOCK_5G){ - if(priv_sc->stactrl.stactrl_preferband_ent) - kfree(priv_sc->stactrl.stactrl_preferband_ent); - if(prefer_priv->stactrl.stactrl_block_ent) - kfree(prefer_priv->stactrl.stactrl_block_ent); - } - - prefer_priv->stactrl.stactrl_status = 0; - priv_sc->stactrl.stactrl_status = 0; - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 - if (timer_pending(&priv_sc->stactrl.stactrl_timer)) - { - del_timer(&priv_sc->stactrl.stactrl_timer); - } -#endif - } -} - -static struct stactrl_block_entry *stactrl_block_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - unsigned long offset; - int hash; - struct stactrl_link_list *link; - struct stactrl_block_entry * ent; - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); - link = priv->stactrl.stactrl_block_machash[hash]; - while (link != NULL) - { - ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - if (!memcmp(ent->mac, mac, MACADDRLEN)) - { - return ent; - } - link = link->next_hash; - } - - return NULL; - -} - -/*return value: NULL: error, other:success*/ -static struct stactrl_block_entry * stactrl_block_add(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct stactrl_block_entry * ent = NULL; - int i, hash; - ASSERT(mac); - - //STACTRL_DEBUG(mac, "is added to [%s] blocklist",priv->dev->name); - - ent = stactrl_block_lookup(priv, mac); //Avoid exist mac to add again - if(ent != NULL) return ent; - - - /* find an empty entry*/ - for (i=0; istactrl.stactrl_block_ent[i].used) - { - ent = &(priv->stactrl.stactrl_block_ent[i]); - break; - } - } - - if(ent) - { - ent->used = 1; - memcpy(ent->mac, mac, MACADDRLEN); - ent->retryY = STACTRL_BLOCK_RETRY_Y; - ent->timerX = STACTRL_BLOCK_EXPIRE_X; - ent->timerZ = 0; -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - ent->aging = 0; -#endif - hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); - //panic_printk("[%s %d][%s]Target mac not existed. Add. aging:%d\n",__FUNCTION__,__LINE__,priv->dev->name, ent->aging); - stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_block_machash[hash])); - return ent; - } - - return NULL; -} - -/*return value: 0:success, other: error*/ -static int stactrl_block_delete(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - unsigned long offset; - int hash; - struct stactrl_link_list *link; - struct stactrl_block_entry * ent; - unsigned long flags; - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - panic_printk("[%s %d][%s]Taget mac:%02x:%02x:%02x:%02x:%02x:%02x\n", - __FUNCTION__,__LINE__,priv->dev->name, - mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); - link = priv->stactrl.stactrl_block_machash[hash]; - while (link != NULL) - { - ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - if (!memcmp(ent->mac, mac, MACADDRLEN)) - { - ent->used = 0; - stactrl_mac_hash_unlink(link); - panic_printk("[%s %d][%s]Delete existed mac:%02x:%02x:%02x:%02x:%02x:%02x\n", - __FUNCTION__,__LINE__,priv->dev->name, - ent->mac[0],ent->mac[1],ent->mac[2],ent->mac[3],ent->mac[4],ent->mac[5]); - - STACTRL_DEBUG(ent->mac, "block delete"); - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - return 0; - } - link = link->next_hash; - } - panic_printk("[%s %d][%s]Block list NULL.\n", __FUNCTION__,__LINE__,priv->dev->name); - - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - return 1; - -} - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 -//20170106 -static unsigned char stactrl_sta_in_the_other_band(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct rtl8192cd_priv *priv_tmp=NULL; - struct stat_info *pstat=NULL; - extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; - int i; - - if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; - else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; - - if(priv_tmp==NULL){ - panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); - return 0; - } - - for(i=0; ipshare->aidarray[i] && (priv_tmp->pshare->aidarray[i]->used == TRUE)) - { - pstat = &(priv_tmp->pshare->aidarray[i]->station); - if(pstat && !memcmp(pstat->hwaddr, mac, MACADDRLEN)) - { - //20170321, return current rssi to associated AP - return pstat->rssi; - } - } - } - - return 0; -} - -//20170106 -static unsigned long stactrl_sta_in_the_prefer_band(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct stat_info *pstat=NULL; - int i; - - for(i=0; ipshare->aidarray[i] && (priv->pshare->aidarray[i]->used == TRUE)) - { - pstat = &(priv->pshare->aidarray[i]->station); - if(pstat && !memcmp(pstat->hwaddr, mac, MACADDRLEN)) - { - return pstat->link_time; - } - } - } - - return 0; -} -#endif - -static struct stactrl_preferband_entry *stactrl_preferband_sta_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - unsigned long offset; - int hash; - struct stactrl_link_list *link; - struct stactrl_preferband_entry * ent; - - offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); - hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); - link = priv->stactrl.stactrl_preferband_machash[hash]; - while (link != NULL) - { - ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); - if (!memcmp(ent->mac, mac, MACADDRLEN)) - { - return ent; - } - link = link->next_hash; - } - - return NULL; - -} - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 -void stactrl_preferband_sta_add(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char rssi, unsigned int is_local) -{ - struct stactrl_preferband_entry * ent; - int i, hash; - int temp_aging, temp_index; - unsigned long flags = 0; - ASSERT(mac); -#if 0 - panic_printk("add prefer %02x%02x%02x%02x%02x%02x %s, %p\n", - mac[0], mac[1],mac[2],mac[3],mac[4],mac[5], priv->dev->name, __builtin_return_address(0)); - - if(is_local){ - STACTRL_DEBUG(mac, "receive notify, rssi %d", rssi);} - else{ - STACTRL_DEBUG(mac, "receive probe, rssi %d", rssi);} -#endif - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - ent = stactrl_preferband_sta_lookup(priv, mac); - if(ent) /*find existed entry*/ - { - //STACTRL_DEBUG(mac, "update"); - if(rssi == 0) - goto ret; - - ent->aging = 0; - //reset retry counter when STA connects to the blocking band after it consumes retry counter to zero - //or when STA connects to the non-blocking band instead of resetting here - //ent->retry = STACTRL_BLOCK_RETRY_Y; - ent->rssi = rssi; - - //201701015 - //update local - if(ent->local==0 && is_local==1) - ent->local = is_local; - - goto ret; - } - - - /* find an empty entry*/ - ent = NULL; - for (i=0; istactrl.stactrl_preferband_ent[i].used) - { - //STACTRL_DEBUG(mac, "stactrl_preferband_sta_add: add new\n"); - ent = &(priv->stactrl.stactrl_preferband_ent[i]); - break; - } - } - - /* not found, find a entry with max aging*/ - if(ent == NULL) - { - temp_aging = 0; - temp_index = 0; - for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) - { - if(!priv->stactrl.stactrl_preferband_ent[i].local){//20170105 - temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; - temp_index = i; - } - } - - } - ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); - - //20170105 - //if all stactrl list is local, choose one local sta that have max aging - if(temp_index==0 && temp_aging==0 && ent->local==1){ - for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) - { - temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; - temp_index = i; - } - - } - ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); - } - STACTRL_DEBUG(mac, "[%s]del old entry, add new", priv->dev->name); - - //panic_printk("[STA_CONTROL][%s] entry full, remove max aging mac:%02x:%02x:%02x:%02x:%02x:%02x, local=%d, temp_index:%d, temp_aging:%d\n", - // priv->dev->name, - // ent->mac[0],ent->mac[1],ent->mac[2],ent->mac[3],ent->mac[4],ent->mac[5], ent->local, temp_index, temp_aging); - - stactrl_mac_hash_unlink(&(ent->link_list)); - } - - //STACTRL_DEBUG(mac, "[%s]add new reset\n", priv->dev->name); - ent->used = 1; - memcpy(ent->mac, mac, MACADDRLEN); - ent->aging = 0; - ent->retry = STACTRL_BLOCK_RETRY_Y; - ent->rssi = rssi; - ent->local = is_local;//20170105 - ent->kickoff = 0;//20170106 - hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); - STACTRL_DEBUG(mac, "[%s]add new reset, hash:%d", priv->dev->name, hash); - stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_preferband_machash[hash])); - -ret: - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); -} - -//20170105 -void stactrl_preferband_sta_del(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct stactrl_preferband_entry * ent; - int i, hash; - int temp_aging, temp_index; - unsigned long flags = 0; - ASSERT(mac); -#if 0 - panic_printk("add prefer %02x%02x%02x%02x%02x%02x %s, %p\n", - mac[0], mac[1],mac[2],mac[3],mac[4],mac[5], priv->dev->name, __builtin_return_address(0)); -#endif - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - ent = stactrl_preferband_sta_lookup(priv, mac); - if(ent != NULL) /*find existed entry*/ - { - ent->used = 0; - stactrl_mac_hash_unlink(&(ent->link_list)); - } - - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); -} - -static struct stactrl_preferband_entry * stactrl_is_dualband(struct rtl8192cd_priv *priv, unsigned char *mac) -{ - struct stactrl_preferband_entry *prefer_ent, *ret=NULL; - unsigned long flags=0; - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - prefer_ent = stactrl_preferband_sta_lookup(priv, mac); - if(prefer_ent && priv->assoc_num < NUM_STAT) - { -//20170321, return prefer_ent to check retry counter at non-prefer band - ret = prefer_ent; - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - return ret; -} - -static unsigned char stactrl_is_kickoff(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - struct stactrl_preferband_entry * prefer_ent; - unsigned char ret = 0; - unsigned long flags=0; - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - prefer_ent = stactrl_preferband_sta_lookup(priv, pstat->hwaddr); - if(prefer_ent && priv->assoc_num < NUM_STAT) - { - if(pstat->link_time > STACTRL_KICKOFF_TIME && (pstat->tx_avarage + pstat->rx_avarage) < STACTRL_KICKOFF_TP) { - ret = 1; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - return ret; -} - - -#else -void stactrl_preferband_sta_add(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char rssi) -{ - struct stactrl_preferband_entry * ent; - int i, hash; - int temp_aging, temp_index; - unsigned long flags = 0; - ASSERT(mac); - - STACTRL_DEBUG(mac, "receive probe"); - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - ent = stactrl_preferband_sta_lookup(priv, mac); - if(ent) /*find existed entry*/ - { - if(rssi < STACTRL_PREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE) - { - stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac); - } - - ent->aging = 0; - ent->rssi = rssi; - - goto ret; - } - - - /* find an empty entry*/ - ent = NULL; - for (i=0; istactrl.stactrl_preferband_ent[i].used) - { - ent = &(priv->stactrl.stactrl_preferband_ent[i]); - break; - } - } - - /* not found, find a entry with max aging*/ - if(ent == NULL) - { - temp_aging = 0; - temp_index = 0; - for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) - { - temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; - temp_index = i; - } - - } - ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); - stactrl_mac_hash_unlink(&(ent->link_list)); - } - - ent->used = 1; - memcpy(ent->mac, mac, MACADDRLEN); - ent->aging = 0; - ent->rssi = rssi; - hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); - stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_preferband_machash[hash])); - -ret: - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); -} - -static unsigned char stactrl_is_need(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char checkRSSI) -{ - struct stactrl_preferband_entry * prefer_ent; - struct rtl8192cd_priv *priv_temp; - int assoc_num = 0; - int i; - unsigned char ret = 0; - unsigned long flags=0; - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - prefer_ent = stactrl_preferband_sta_lookup(priv, mac); - if(prefer_ent) - { - assoc_num = GET_ROOT(priv)->assoc_num; - #ifdef MBSSID - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ - for (i=0; ipvap_priv[i]; - if(priv_temp && IS_DRV_OPEN(priv_temp)) - assoc_num += priv_temp-> assoc_num; - } - } - #endif - #ifdef UNIVERSAL_REPEATER - priv_temp = GET_VXD_PRIV(GET_ROOT(priv)); - if (priv_temp && IS_DRV_OPEN(priv_temp)) - assoc_num += priv_temp-> assoc_num; - #endif - #ifdef WDS - if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) - assoc_num ++; - #endif - - if(assoc_num < NUM_STAT) - { - if(checkRSSI) { - if(prefer_ent->rssi > STACTRL_PREFERBAND_RSSI) - ret = 1; - } - else - ret = 1; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - return ret; -} -#endif - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 -//20170103 -static int stactrl_check_if_kickoff(struct rtl8192cd_priv *priv,unsigned char* kickoff_mac) -{ - struct rtl8192cd_priv *priv_tmp=NULL; - extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; - int i; - - if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; - else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; - - if(priv_tmp==NULL){ - panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); - return 0; - } - - for (i=0; istactrl.stactrl_preferband_ent[i].used) - { - if(!memcmp(priv_tmp->stactrl.stactrl_preferband_ent[i].mac, kickoff_mac, MACADDRLEN)) - { - if(priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff >= STACTRL_KICKOFF_TIMES) - { - //panic_printk("Hit %s mac: %02x:%02x:%02x:%02x:%02x:%02x, kickoff=%d\n", - // priv_tmp->dev->name, - // kickoff_mac[0],kickoff_mac[1],kickoff_mac[2], - // kickoff_mac[3],kickoff_mac[4],kickoff_mac[5], - // priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff); - return 1; - } - } - } - } - - return 0; -} - -//20170103 -static void stactrl_record_kickoff(struct rtl8192cd_priv *priv, unsigned char* kickoff_mac) -{ - struct rtl8192cd_priv *priv_tmp=NULL; - extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; - int i; - int no_kickoff_mac=1; - - if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; - else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 - priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; - - if(priv_tmp==NULL){ - panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); - return; - } - - for (i=0; istactrl.stactrl_preferband_ent[i].used){ - if(!memcmp(priv_tmp->stactrl.stactrl_preferband_ent[i].mac, kickoff_mac, MACADDRLEN)) - { - priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff++; - STACTRL_DEBUG(kickoff_mac, "[%s] kickoff=%d", - priv_tmp->dev->name, priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff); - no_kickoff_mac = 0; - break; - } - } - } - - if(no_kickoff_mac) - STACTRL_DEBUG(kickoff_mac, "[%s]is not in prefer entry",priv->dev->name); - - return; -} -#endif - -static void stactrl_preferband_expire(struct rtl8192cd_priv *priv) -{ - int i; - unsigned long offset; - struct stactrl_link_list *link, *temp_link; - struct stactrl_preferband_entry * ent; - unsigned long flags = 0; - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); - - for (i=0; istactrl.stactrl_preferband_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); - if(ent->used) - { - ent->aging++; -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - //20170106 - //reset kickoff - // 1. STA in preferband, reset kickoff after 60s - // 2. STA not connet to AP, reset kickoff after 30s - unsigned long preferband_linketime = 0; - unsigned char is_in_nonpreferband = 0 ; - preferband_linketime = stactrl_sta_in_the_prefer_band(priv, ent->mac); - is_in_nonpreferband = stactrl_sta_in_the_other_band(priv, ent->mac); - // check if in non prefer band and calc time - if(is_in_nonpreferband) - ent->sta_not_in_nonpreferband = 0; - else{ - if(ent->kickoff>0) - ent->sta_not_in_nonpreferband++;//sec - } - // STA connect to prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec - if(preferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && - ent->kickoff>0) - { - panic_printk("[STA_CONTROL][%s] remove %02x:%02x:%02x:%02x:%02x:%02x kickoff times, beacuse STA connect over %ds\n", - priv->dev->name, - ent->mac[0],ent->mac[1],ent->mac[2], - ent->mac[3],ent->mac[4],ent->mac[5], - STACTRL_KICKOFF_REMOVE_WHEN_LINK); - ent->kickoff = 0; - ent->sta_not_in_nonpreferband = 0; - } - // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec - if(preferband_linketime==0 && - ent->sta_not_in_nonpreferband>=STACTRL_KICKOFF_REMOVE && - ent->kickoff>0) - { - panic_printk("[STA_CONTROL][%s] remove %02x:%02x:%02x:%02x:%02x:%02x kickoff times, beacuse STA leave AP over %ds\n", - priv->dev->name, - ent->mac[0],ent->mac[1],ent->mac[2], - ent->mac[3],ent->mac[4],ent->mac[5], - STACTRL_KICKOFF_REMOVE); - ent->kickoff = 0; - ent->sta_not_in_nonpreferband = 0; - } - //update this client is local client - if(preferband_linketime>0) - ent->local = 1; -#else - if(ent->aging > STACTRL_PREFERBAND_EXPIRE) - { - ent->used = 0; - stactrl_mac_hash_unlink(link); - } -#endif - } - link = temp_link; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - -} - -/* timer: on prefer band */ -static void stactrl_preferband_expire_3_1(struct rtl8192cd_priv *priv) -{ - int i; - unsigned long offset; - struct stactrl_link_list *link, *temp_link; - struct stactrl_preferband_entry * ent, *ent1; - unsigned long flags = 0; - struct list_head *phead, *plist; - struct stat_info *pstat; - unsigned char kickoff_prefer; - struct stactrl_block_entry *block_ent; - unsigned long preferband_linketime = 0; - unsigned char is_in_nonpreferband = 0 ; - unsigned char sta_mac[16]; - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); - - for (i=0; istactrl.stactrl_preferband_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); - if(ent->used) - { - ent->aging++; - //20170106 - // reset kickoff, to make STA can be kickoff on non-prefer band - // 1. STA in preferband, reset kickoff after 60s - // 2. STA not connet to AP, reset kickoff after 30s - preferband_linketime = 0; - is_in_nonpreferband = 0 ; - preferband_linketime = stactrl_sta_in_the_prefer_band(priv, ent->mac); - is_in_nonpreferband = stactrl_sta_in_the_other_band(priv, ent->mac); - - // check if in non prefer band and calc time - if(is_in_nonpreferband){ - ent->sta_not_in_nonpreferband = 0; - if(ent->kickoff>0) - ent->sta_in_non_preferband++; - } - else{ - if(ent->kickoff>0) - ent->sta_not_in_nonpreferband++;//sec - } - - if( priv->up_time % DEBUG_TIME_INETRVAL==0 ) - STACTRL_DEBUG(ent->mac, "preferband_linketime:%d,not_in_nonpreferband:%d,in_nonpreferband:%d,kickoff:%d", - preferband_linketime, - ent->sta_not_in_nonpreferband, - is_in_nonpreferband, - ent->kickoff); - - // STA connect to prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec - if(preferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && ent->kickoff>0) - { - STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [prefer band] over %ds", - priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE_WHEN_LINK); - ent->kickoff = 0; - ent->sta_not_in_nonpreferband = 0; - } - - // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec - if(preferband_linketime==0 && - ent->sta_not_in_nonpreferband>=STACTRL_KICKOFF_REMOVE && ent->kickoff>0) - { - STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA leave AP over %ds", - priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE); - ent->kickoff = 0; - ent->sta_not_in_nonpreferband = 0; - } - - // STA connect to prefer-band, and kickoff is more than STACTRL_KICKOFF_TIMES - if(ent->kickoff >= STACTRL_KICKOFF_TIMES && ent->sta_in_non_preferband >=STACTRL_KICKOFF_REMOVE_WHEN_LINK){ - STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [non-prefer] band over %ds", - priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE_WHEN_LINK); - ent->kickoff= 0; - ent->sta_in_non_preferband = 0; - } - - //update this client is local client - if(preferband_linketime>0) - ent->local = 1; - } - link = temp_link; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - -#if 1 - // if block time more than STACTRL_PREFERBAND_EXPIRE_Z, then un-block - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - for (i=0; istactrl.stactrl_block_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - block_ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - block_ent->aging++; - - if(block_ent->aging > STACTRL_BLOCK_EXPIRE_Z) - { - block_ent->used = 0; - stactrl_record_kickoff(priv, block_ent->mac); - stactrl_mac_hash_unlink(link); - STACTRL_DEBUG(ent->mac, "[%s]block expire, aging:%d", priv->dev->name, block_ent->aging); - } - link = temp_link; - } - } - - RESTORE_INT(flags); - SMP_UNLOCK_STACONTROL_LIST(flags); -#endif - - /*kickoff prefer band station(eg: sta go away), to force it to go through sta control process*/ - phead = &priv->asoc_list; - plist = phead; - - /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ - if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) - && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ - return 0; - } - - while ((plist = asoc_list_get_next(priv, plist)) != phead) - { - kickoff_prefer= 0; - pstat = list_entry(plist, struct stat_info, asoc_list); - if( priv->up_time % 5==0 ) - STACTRL_DEBUG(pstat->hwaddr, "rssi:%d", pstat->rssi); -/* -#ifdef CONFIG_IEEE80211V - if(pstat->bssTransSupport == TRUE && pstat->bssTransRejectionCount < 5){ - STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); - continue; - } -#endif -*/ - if(pstat->rssi <= STACTRL_PREFERBAND_RSSI) - { -#ifdef CONFIG_IEEE80211V - if(pstat->bssTransSupport == TRUE && pstat->bssTransPktSent < 5){ - STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); - pstat->bssTransPktSent++; - memcpy(priv->bssTransPara.bssid_mac, priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.dot11Bssid, MACADDRLEN); - if(issue_BSS_Trans_Req(priv, pstat->hwaddr, NULL) == 0) - { - pstat->bssTransExpiredTime = 0; - pstat->bssTransTriggered = TRUE; - priv->startCounting = TRUE; - - DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", - pstat->hwaddr[0], - pstat->hwaddr[1], - pstat->hwaddr[2], - pstat->hwaddr[3], - pstat->hwaddr[4], - pstat->hwaddr[5]); - } - else - { - DOT11VDEBUG("BSS Trans Req for bandsteering failed! \n"); - } - continue; - } -#endif - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - ent1 = stactrl_preferband_sta_lookup(priv, pstat->hwaddr); - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - - if(ent1==NULL) - continue; - - if(kickoff_prefer == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) { - kickoff_prefer = 1; - } - - //check if this client is kickoff more than threshold times - if((kickoff_prefer == 1) && (stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1)){ - kickoff_prefer = 0; - STACTRL_DEBUG(pstat->hwaddr, "[%s]is kickoff %d times already, do not kickoff again !!", - priv->dev->name, STACTRL_KICKOFF_TIMES); - } - - if(kickoff_prefer){ - stactrl_hidden_ap(priv); - - STACTRL_DEBUG(pstat->hwaddr, "Deauth it on prefer band"); - - SMP_LOCK_STACONTROL_LIST(flags); - block_ent = stactrl_block_add(priv, pstat->hwaddr); - if(block_ent) /*add success*/ - { - STACTRL_DEBUG(pstat->hwaddr, "[%s]block add success, aging:%d", priv->dev->name, block_ent->aging); - } - else - { - STACTRL_DEBUG(pstat->hwaddr, "[%s]block add fail", priv->dev->name); - } - SMP_UNLOCK_STACONTROL_LIST(flags); - - /* if DUT not recv deauth from STA, then the sta_info is not clear, - DUT will always tx deauth */ - // issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); //marked by tesia - //del_sta(priv, pstat->hwaddr); - issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); - - pstat->prepare_to_free = 1; - } - } - if (plist == plist->next) - break; - } -} - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - -/* timer: on non-prefer band */ -static void stactrl_non_prefer_expire(struct rtl8192cd_priv *priv) -{ - if(priv->stactrl.stactrl_hiddenAP_aging > 0){ - //printk("%s: hiddenAP_aging = %d\n", __FUNCTION__, priv->stactrl.stactrl_hiddenAP_aging); - if(priv->stactrl.stactrl_hiddenAP_aging == 1){ - if(priv->pmib->dot11OperationEntry.hiddenAP){ - printk("%s: reset hiddenAP to recover ssid in Beacon\n", __FUNCTION__); - priv->pmib->dot11OperationEntry.hiddenAP = 0; - } - } - priv->stactrl.stactrl_hiddenAP_aging--; - } - - int i; - unsigned long offset; - struct stactrl_link_list *link, *temp_link; - struct stactrl_block_entry * ent; - unsigned long flags = 0; - struct stat_info *pstat; - struct list_head *phead, *plist; - unsigned char kickoff; - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - for (i=0; istactrl.stactrl_block_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - ent->aging++; - if(ent->aging > STACTRL_BLOCK_EXPIRE) - { - ent->used = 0; - //20170106 - stactrl_record_kickoff(priv, ent->mac); - stactrl_mac_hash_unlink(link); - STACTRL_DEBUG(ent->mac, "block expire"); - - } - - link = temp_link; - } - } - - RESTORE_INT(flags); - SMP_UNLOCK_STACONTROL_LIST(flags); - - - /*kick out non-prefer band station, to force it to go through sta control process*/ - phead = &priv->asoc_list; - plist = phead; - - while ((plist = asoc_list_get_next(priv, plist)) != phead) - { - kickoff= 0; - pstat = list_entry(plist, struct stat_info, asoc_list); - if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) { - if(pstat->stactrl_candidate == 1) { - kickoff = 1; - } - - if(kickoff == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) - kickoff = 1; - - //20170103 - //check if this client is kickoff again - if((stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1) && (kickoff == 1)){ - kickoff = 0; - //panic_printk("[STA_CONTROL] mac:%02x:%02x:%02x:%02x:%02x:%02x is kickoff %d times already, do not kickoff again !!\n", - //pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], - //pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5], - //STACTRL_KICKOFF_TIMES); - } - - if(kickoff) - { /*check if it is a dual-band client*/ - #ifdef RTK_SMART_ROAMING - notify_hidden_ap(priv, STACTRL_HIDDEN_AP); - #endif - stactrl_hidden_ap(priv); - - STACTRL_DEBUG(pstat->hwaddr, "Deauth it on non-prefer band"); - SMP_LOCK_STACONTROL_LIST(flags); - ent = stactrl_block_add(priv, pstat->hwaddr); - if(ent) /*add success*/ - { - STACTRL_DEBUG(pstat->hwaddr, "block add"); - } - else - { - STACTRL_DEBUG(pstat->hwaddr, "block add fail"); - } - SMP_UNLOCK_STACONTROL_LIST(flags); - - DRV_RT_TRACE(priv, DRV_DBG_CONN_INFO, DRV_DBG_SERIOUS, "issue_deauth - %02X:%02X:%02X:%02X:%02X:%02X, _RSON_DISAOC_STA_LEAVING_\n", - pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); - issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); - //#ifdef RTK_SMART_ROAMING - pstat->prepare_to_free = 1; - //#endif - } - } - - if (plist == plist->next) - break; - } - -} - -static void stactrl_non_prefer_expire_3_1(struct rtl8192cd_priv *priv) -{ - if(priv->stactrl.stactrl_hiddenAP_aging > 0){ - //printk("%s: hiddenAP_aging = %d\n", __FUNCTION__, priv->stactrl.stactrl_hiddenAP_aging); - if(priv->stactrl.stactrl_hiddenAP_aging == 1){ - if(priv->pmib->dot11OperationEntry.hiddenAP){ - printk("%s: reset hiddenAP to recover ssid in Beacon\n", __FUNCTION__); - priv->pmib->dot11OperationEntry.hiddenAP = 0; - } - } - priv->stactrl.stactrl_hiddenAP_aging--; - } - - int i; - unsigned long offset; - struct stactrl_link_list *link, *temp_link; - struct stactrl_block_entry * ent; - unsigned long flags = 0; - struct stat_info *pstat; - struct list_head *phead, *plist; - unsigned char kickoff; - unsigned long nonpreferband_linketime = 0; - unsigned char is_in_preferband = 0; - struct stactrl_preferband_entry *prefer_ent, *prefer_ent1; - unsigned char sta_mac[16]; - - offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - for (i=0; istactrl.stactrl_preferband_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - prefer_ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); - if(prefer_ent->used) - { - prefer_ent->aging++; - - //reset kickoff - // 1. STA in preferband, reset kickoff after 60s - // 2. STA not connet to AP, reset kickoff after 30s - nonpreferband_linketime = 0; - is_in_preferband = 0; - nonpreferband_linketime = stactrl_sta_in_the_prefer_band(priv, prefer_ent->mac); - is_in_preferband = stactrl_sta_in_the_other_band(priv, prefer_ent->mac); - - // check if in prefer band and calc time - if(is_in_preferband){ - prefer_ent->sta_not_in_preferband = 0; - - if(prefer_ent->kickoff>0) - prefer_ent->sta_in_prefer_band++; - } - else - if(prefer_ent->kickoff>0) - prefer_ent->sta_not_in_preferband++; - - if( priv->up_time % DEBUG_TIME_INETRVAL==0 ) - STACTRL_DEBUG(prefer_ent->mac, "nonpreferband_linketime:%d,not_in_preferband:%d,in_prefer_band:%d,kickoff:%d", - nonpreferband_linketime, - prefer_ent->sta_not_in_preferband, - prefer_ent->sta_in_prefer_band, - prefer_ent->kickoff); - - // STA connect to non-prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec - if(nonpreferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && prefer_ent->kickoff>0) - { - STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [non-prefer band] over %ds", - priv->dev->name,prefer_ent->kickoff,STACTRL_KICKOFF_REMOVE_WHEN_LINK); - prefer_ent->kickoff= 0; - prefer_ent->sta_not_in_preferband = 0; - } - - // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec - if(nonpreferband_linketime==0 && - prefer_ent->sta_not_in_preferband>=STACTRL_KICKOFF_REMOVE && prefer_ent->kickoff>0) - { - STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA leave AP over %ds", - priv->dev->name, prefer_ent->kickoff, STACTRL_KICKOFF_REMOVE); - prefer_ent->kickoff= 0; - prefer_ent->sta_not_in_preferband = 0; - } - - // STA connect to prefer-band, and kickoff is more than STACTRL_KICKOFF_TIMES - if(prefer_ent->kickoff >= STACTRL_KICKOFF_TIMES && prefer_ent->sta_in_prefer_band >=STACTRL_KICKOFF_REMOVE_WHEN_LINK){ - STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [prefer band] over %ds", - priv->dev->name,prefer_ent->kickoff,STACTRL_KICKOFF_REMOVE_WHEN_LINK); - prefer_ent->kickoff= 0; - prefer_ent->sta_in_prefer_band = 0; - } - - //update this client is local client - if(nonpreferband_linketime>0) - prefer_ent->local = 1; - } - link = temp_link; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - for (i=0; istactrl.stactrl_block_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - ent->aging++; - if(ent->aging > STACTRL_BLOCK_EXPIRE_Z) - { - ent->used = 0; - //20170106 - stactrl_record_kickoff(priv, ent->mac); - stactrl_mac_hash_unlink(link); - STACTRL_DEBUG(ent->mac, "[%s]block expire", priv->dev->name); - } - - link = temp_link; - } - } - - RESTORE_INT(flags); - SMP_UNLOCK_STACONTROL_LIST(flags); - - /*kickoff STA on non-prefer band. to force it to go through sta control process*/ - phead = &priv->asoc_list; - plist = phead; - - /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ - if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) - && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ - return 0; - } - - while ((plist = asoc_list_get_next(priv, plist)) != phead) - { - kickoff= 0; - pstat = list_entry(plist, struct stat_info, asoc_list); - - if(priv->up_time % 5==0) // just for debug - STACTRL_DEBUG(pstat->hwaddr, "rssi:%d", pstat->rssi); -/* -#ifdef CONFIG_IEEE80211V - if(pstat->bssTransSupport == TRUE && pstat->bssTransRejectionCount < 5){ - STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); - continue; - } -#endif -*/ - if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) - { -#ifdef CONFIG_IEEE80211V - if(pstat->bssTransSupport == TRUE && pstat->bssTransPktSent < 5){ - STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); - pstat->bssTransPktSent++; - memcpy(priv->bssTransPara.bssid_mac, priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.dot11Bssid, MACADDRLEN); - if(issue_BSS_Trans_Req(priv, pstat->hwaddr, NULL) == SUCCESS) - { - pstat->bssTransExpiredTime = 0; - pstat->bssTransTriggered = TRUE; - priv->startCounting = TRUE; - - DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", - pstat->hwaddr[0], - pstat->hwaddr[1], - pstat->hwaddr[2], - pstat->hwaddr[3], - pstat->hwaddr[4], - pstat->hwaddr[5]); - } - else - { - DOT11VDEBUG("BSS Trans Req for bandsteering failed! \n"); - } - continue; - } -#endif - - if(pstat->stactrl_candidate == 1) - kickoff = 1; - if(kickoff == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) - kickoff = 1; - - //20170103 - //check if this client is kickoff more than threshold times - if((stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1) && (kickoff == 1)){ - kickoff = 0; - panic_printk("[STA_CONTROL] mac:%02x:%02x:%02x:%02x:%02x:%02x is kickoff %d times already, do not kickoff again !!\n", - pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], - pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5], - STACTRL_KICKOFF_TIMES); - } - - if(kickoff) { /*check if it is a dual-band client*/ - #ifdef RTK_SMART_ROAMING - notify_hidden_ap(priv, STACTRL_HIDDEN_AP); - #endif - stactrl_hidden_ap(priv); - - STACTRL_DEBUG(pstat->hwaddr, "Deauth it on non-prefer band"); - SMP_LOCK_STACONTROL_LIST(flags); - ent = stactrl_block_add(priv, pstat->hwaddr); - if(ent) /*add success*/ - { - STACTRL_DEBUG(pstat->hwaddr, "block add success"); - } - else - { - STACTRL_DEBUG(pstat->hwaddr, "block add fail"); - } - SMP_UNLOCK_STACONTROL_LIST(flags); - - //issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); //marked by tesia - //del_sta(priv, pstat->hwaddr); - issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); - - pstat->prepare_to_free = 1; - } - } - - if (plist == plist->next) - break; - } -} - -void stactrl_expire(struct rtl8192cd_priv *priv) -{ - if(priv->stactrl.stactrl_prefer){ - if(!STACTRL_BLOCK_5G) - stactrl_preferband_expire(priv); - else - stactrl_preferband_expire_3_1(priv); - } - else{ - if(!STACTRL_BLOCK_5G) - stactrl_non_prefer_expire(priv); - else - stactrl_non_prefer_expire_3_1(priv); - } -} - -#else -void stactrl_non_prefer_expire(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - int i; - unsigned long offset; - struct stactrl_link_list *link, *temp_link; - struct stactrl_block_entry * ent; - unsigned long flags = 0; - - offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - for (i=0; istactrl.stactrl_block_machash[i]; - while (link != NULL) - { - temp_link = link->next_hash; - ent = (struct stactrl_block_entry *)((unsigned long)link - offset); - if(ent->timerZ) - { - ent->timerZ--; - if(ent->timerZ == 0) - { - ent->used = 0; - stactrl_mac_hash_unlink(link); - STACTRL_DEBUG(ent->mac, "block del"); - } - } - else if(ent->timerX) - { - ent->timerX--; - - if(ent->timerX == 0) - { - ent->timerZ = STACTRL_BLOCK_EXPIRE_Z; - STACTRL_DEBUG(ent->mac, "block Z stage"); - } - } - - link = temp_link; - } - } - - RESTORE_INT(flags); - SMP_UNLOCK_STACONTROL_LIST(flags); - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 - mod_timer(&priv->stactrl.stactrl_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(STACTRL_NON_PREFER_TIMER)); -#endif -} - - -void stactrl_expire(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat; - struct list_head *phead, *plist; - - if(priv->stactrl.stactrl_prefer) - { - stactrl_preferband_expire(priv); - } - - - if(priv->stactrl.stactrl_prefer == 0) - { - #if STA_CONTROL_ALGO == STA_CONTROL_ALGO1 - stactrl_non_prefer_expire((unsigned long)priv); - #endif - - - /*kick out non-prefer band station, to force it to go through sta control process*/ - phead = &priv->asoc_list; - plist = phead; - - while ((plist = asoc_list_get_next(priv, plist)) != phead) - { - pstat = list_entry(plist, struct stat_info, asoc_list); - if(pstat->stactrl_candidate) { - if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) { - if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, pstat->hwaddr, 0)) { /*check if it is a dual-band client*/ - STACTRL_DEBUG(pstat->hwaddr, "Dissasociate it on non-prefer band"); - unsigned char sta_mac[16]; - sprintf(sta_mac,"%02X%02X%02X%02X%02X%02X", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); - - DRV_RT_TRACE(priv, DRV_DBG_CONN_INFO, DRV_DBG_SERIOUS, "del_sta - %02X:%02X:%02X:%02X:%02X:%02X\n", - pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); - - del_sta(priv, sta_mac); - } - } - } - - if (plist == plist->next) - break; - - } - - - } -} -#endif - -#if STA_CONTROL_ALGO == STA_CONTROL_ALGO1 -/*return: 0: continu process(no stactrl), 1: ignore, 2: error code, 3: continue process(have done stactrl process)*/ -unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) -{ - struct stactrl_block_entry * block_ent; - unsigned char ret = 0; - unsigned long flags = 0; - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - block_ent = stactrl_block_lookup(priv, mac); - if(block_ent) - { - ret = 3; - if(block_ent->timerX && block_ent->retryY) - { - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - ret = 2; - block_ent->retryY--; - - if(block_ent->retryY == 0) - { - block_ent->timerZ = STACTRL_BLOCK_EXPIRE_Z; - STACTRL_DEBUG(block_ent->mac, "block Z stage"); - } - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - } - else - { - SMP_UNLOCK_STACONTROL_LIST(flags); - if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, mac, 1)) - { - ret = 1; - SMP_LOCK_STACONTROL_LIST(flags); - block_ent = stactrl_block_add(priv, mac); - if(block_ent) /*add success*/ - { - STACTRL_DEBUG(mac, "block add"); - } - else - { - STACTRL_DEBUG(mac, "block add fail"); - } - SMP_UNLOCK_STACONTROL_LIST(flags); - } - } - RESTORE_INT(flags); - - STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); - - return ret; -} - -#elif STA_CONTROL_ALGO == STA_CONTROL_ALGO2 -/*return: 0: continu process(no stactrl), 1: ignore, 2: error code, 3: continue process(have done stactrl process)*/ -unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) -{ - struct stactrl_block_entry * block_ent; - unsigned char ret = 0; - - unsigned long flags = 0; - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - block_ent = stactrl_block_lookup(priv, mac); - if(block_ent) - { - ret = 3; - if(block_ent->timerZ) - { - if(frame_type == WIFI_ASSOCREQ) - { - if(block_ent->retryY) - { - block_ent->retryY--; - ret = 2; - } - } - } - else - { - ret = 1; - } - } - else - { - if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, mac, 1)) - { - ret = 1; - if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ) - { - block_ent = stactrl_block_add(priv, mac); - if(block_ent) /*add success*/ - { - STACTRL_DEBUG(mac, "block add"); - } - else - { - STACTRL_DEBUG(mac, "block add fail"); - } - } - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - - STACTRL_DEBUG(mac, "receive %s drop: %d rssi: %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); - - return ret; -} -#elif STA_CONTROL_ALGO == STA_CONTROL_ALGO3 - -unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) - { - struct stactrl_block_entry * block_ent; - struct stactrl_preferband_entry *prefer_ent; - unsigned char ret = 0; - unsigned long flags = 0; - unsigned char delete_blockent = 0; - - if(priv->stactrl.stactrl_prefer){ - prefer_ent = stactrl_is_dualband(priv,mac); - if(prefer_ent){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - goto ret; - } - - prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); - if(prefer_ent){ - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - //20170321, associated at prefer band with a prefer band rssi - if(stactrl_sta_in_the_other_band(priv, mac) > STACTRL_PREFERBAND_RSSI){ - STACTRL_DEBUG(mac, "sta in the preferband with good rssi"); - ret = 1; - } - //20170321, initial connect with non-prefer band rssi - else if (rssi > STACTRL_NONPREFERBAND_RSSI){ - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - STACTRL_DEBUG(mac, "retry = %d", prefer_ent->retry); - if(prefer_ent->retry > 0){ - ret = 1; - prefer_ent->retry--; - } - else{ - //connect to non-preferband and reset the retry value - STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); - prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; - } - } - } - else{ - block_ent = stactrl_block_lookup(priv, mac); - if(block_ent) - { - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - if(block_ent->retryY) { - ret = 1; - block_ent->retryY--; - if(block_ent->retryY == 0) - { - delete_blockent = 1; - } - } - } - } - } - - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - - if(delete_blockent){ - panic_printk("%s: call stactrl_block_delete\n",__FUNCTION__); - if(stactrl_block_delete(priv, mac) == 0){ - //20170103 - //record STA is kickoff and on the other band's prefer table - stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); - } - } - } - ret: - STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); - - return ret; -} - -/*return: 0: continu process(no stactrl), 1: block*/ -/* in processing OnProbeReq or (onAuth ?) or OnAssocReq */ -unsigned char stactrl_check_request_on_nonpreferband(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) -{ - struct stactrl_block_entry *block_prefer_ent, *block_nonprefer; - struct stactrl_preferband_entry *prefer_ent, *own_ent; - unsigned char ret = 0; - unsigned long flags = 0; - unsigned char delete_blockent = 0; - unsigned char block_prefer = 0; - - prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); - own_ent = stactrl_is_dualband(priv,mac); - if(prefer_ent){ - /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ - if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) - && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ - return 0; - } - - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - -// if block prefer-band - block_prefer_ent = stactrl_block_lookup(priv->stactrl.stactrl_priv_sc, mac); - if(block_prefer_ent){ - ret = 0; - STACTRL_DEBUG(mac, "[%s]Sta in prefer-band block entry, Block prefer band !!!",(frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc"))); - block_prefer= 1; - if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ - if(own_ent){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - own_ent->retry = STACTRL_BLOCK_RETRY_Y; - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - } - }else - block_prefer = 0; - - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - -//20170321, associated at prefer band with a prefer band rssi - if(!block_prefer){ - if((stactrl_sta_in_the_other_band(priv, mac) > STACTRL_PREFERBAND_RSSI) && (frame_type != WIFI_AUTH)){ - ret = 1; - //panic_printk("[%s %d]associated at prefer band.\n", __FUNCTION__,__LINE__); - } -//20170321, initial connect with non-prefer band rssi - else if (rssi > STACTRL_NONPREFERBAND_RSSI){ // 35 - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - STACTRL_DEBUG(mac,"retry = %d", prefer_ent->retry); - if(prefer_ent->retry > 0){ - ret = 1; - prefer_ent->retry--; - } - else{ - //connect to non-preferband and reset the retry value - STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); - prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } -// initial connect with small rssi - else{ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - block_nonprefer = stactrl_block_lookup(priv, mac); - if(block_nonprefer) - { - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - if(block_nonprefer->retryY) { - ret = 1; - block_nonprefer->retryY--; - if(block_nonprefer->retryY == 0) - { - delete_blockent = 1; - } - } - } - }else{ - // reset the retry counter of 5G when 2G is better choice - if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ - if(own_ent){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - own_ent->retry = STACTRL_BLOCK_RETRY_Y; - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - } - if(frame_type == WIFI_ASSOCREQ) - STACTRL_DEBUG(mac, "RSSI is low and connect to 2G."); - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - } - - if(delete_blockent){ - STACTRL_DEBUG(mac, "[%s]Block del bcz STA try connect more than [%d] times. No block the STA again!", - priv->dev->name); - if(stactrl_block_delete(priv, mac) == 0){ - //20170103 - //record STA is kickoff and on the other band's prefer table - stactrl_record_kickoff(priv, mac); - } - } - } - /*else{ - STACTRL_DEBUG(mac, "single band."); - }*/ - - //STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); - return ret; -} - -unsigned char stactrl_check_request_on_preferband(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) -{ - struct stactrl_block_entry * block_ent; - unsigned char ret = 0; - unsigned long flags = 0; - unsigned char delete_blockent = 0; - struct stactrl_preferband_entry *prefer_ent; - - prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); - if(prefer_ent){ - /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ - if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) - && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ - return 0; - } - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - -// if block prefer-band - block_ent = stactrl_block_lookup(priv, mac); - if(block_ent){ - //STACTRL_DEBUG(mac, "in block list"); - /* if sta in prefer band block list, we should not always block prefer band */ - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - if(block_ent->retryY) { - ret = 1; - block_ent->retryY--; - if(block_ent->retryY == 0) - { - STACTRL_DEBUG(mac, "Block del bcz STA try connect more than [%d] times. No block the STA again!", STACTRL_BLOCK_RETRY_Y); - panic_printk("[%s %d]call stactrl_block_delete\n", __FUNCTION__,__LINE__); - if(stactrl_block_delete(priv, mac) == 0) - stactrl_record_kickoff(priv, mac); - } - } - } - //panic_printk("[%s %d]block prefer band\n", __FUNCTION__,__LINE__); - } - else{ - //STACTRL_DEBUG(mac, "not in block list"); - if((stactrl_sta_in_the_other_band(priv, mac) < STACTRL_NONPREFERBAND_RSSI) && - (stactrl_sta_in_the_other_band(priv, mac) > 0) && - (frame_type != WIFI_AUTH)){ - STACTRL_DEBUG(mac, "sta associates in 2G with low RSSI."); - ret = 1; - } - else if (rssi < STACTRL_PREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE){ - if(frame_type == WIFI_PROBEREQ) - { - ret = 1; - } - else if(frame_type == WIFI_ASSOCREQ) - { - STACTRL_DEBUG(mac, "retry = %d", prefer_ent->retry); - if(prefer_ent->retry > 0){ - ret = 1; - prefer_ent->retry--; - } - else{ - //connect to preferband and reset the retry value - STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); - prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; - } - } - } - else{ - // reset the retry counter of 1G when 5G is better choice - if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ - prefer_ent = stactrl_is_dualband(priv,mac); - if(prefer_ent){ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - } - if(frame_type == WIFI_ASSOCREQ) - STACTRL_DEBUG(mac, "RSSI is high and connect to 5G."); - } - } - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - } - /*else{ - STACTRL_DEBUG(mac, "single band."); - }*/ - - //STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); - return ret; -} - -/* return 0: success, 1: reject*/ -unsigned char stactrl_OnAssocReq(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi, unsigned char * candidate) { - unsigned short val16 = 0; - unsigned long flags = 0; - struct stactrl_block_entry *block_ent_prefer = NULL; - - if(priv->stactrl.stactrl_block5G){ - if(priv->stactrl.stactrl_prefer){ - /* check if block prefer band*/ - SAVE_INT_AND_CLI(flags); - SMP_LOCK_STACONTROL_LIST(flags); - - block_ent_prefer = stactrl_block_lookup(priv, mac); - if(block_ent_prefer){ - val16 = stactrl_check_request_on_preferband(priv, mac, WIFI_ASSOCREQ, rssi); - if(val16){ - STACTRL_DEBUG(mac, "recv assreq, block prefer"); - return 1; - }else{ - STACTRL_DEBUG(mac, "recv assreq, direct connect"); - } - }else{ - //STACTRL_DEBUG(mac, "prefer-band recv assreq, and not block prefer band. Connect..."); - //STACTRL_DEBUG(mac, "block del"); - //record STA is kickoff and on the other band's prefer table - if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac)==0){ - stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); - STACTRL_DEBUG(mac, "2G->5G"); - } - //STA not in either block list of 5G or block list of 2G - else{ - val16 = stactrl_check_request_on_preferband(priv, mac, WIFI_ASSOCREQ, rssi); - if(val16){ - STACTRL_DEBUG(mac, "recv assreq, block prefer"); - return 1; - }else{ - STACTRL_DEBUG(mac, "recv assreq, direct connect"); - } - } - } - - SMP_UNLOCK_STACONTROL_LIST(flags); - RESTORE_INT(flags); - }else { - /* check if block prefer band */ - panic_printk("[%s %d]call stactrl_block_delete\n", __FUNCTION__,__LINE__); - if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac)==0){ - STACTRL_DEBUG(mac, "5G->2G, recv assreq, block prefer, connect non-prefer"); - stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); - } - /* block non-prefer band or non block 2G/5G, prefer band first */ - else{ - STACTRL_DEBUG(mac, "check request when Asso()"); - val16 = stactrl_check_request_on_nonpreferband(priv, mac, WIFI_ASSOCREQ, rssi); - if(val16 == 1){ /*reject*/ - STACTRL_DEBUG(mac, "recv assreq, block 2G"); - return 1; - } - if(rssi < STACTRL_NONPREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE){ - *candidate = 1; - STACTRL_DEBUG(mac, "recv assreq, candidate"); - } - } - } - - return 0; - } - else{ - if(priv->stactrl.stactrl_prefer) { - //panic_printk("%s: call stactrl_block_delete\n",__FUNCTION__); - if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac) == 0){ - //20170103 - //record STA is kickoff and on the other band's prefer table - stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); - } - val16 = stactrl_check_request(priv, mac, WIFI_ASSOCREQ, rssi); - if(val16 == 1) /*reject*/ - return 1; - }else { - val16 = stactrl_check_request(priv, mac, WIFI_ASSOCREQ, rssi); - if(val16 == 1) /*reject*/ - return 1; - if(rssi < STACTRL_NONPREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE) - *candidate = 1; - } - return 0; - } - -} - -unsigned char stactrl_hidden_ap(struct rtl8192cd_priv *priv) -{ - if(!priv->stactrl.stactrl_enable_hiddenAP || priv->stactrl.stactrl_prefer) - return 1; - printk("[%s]\n", __FUNCTION__); - - if(!priv->pmib->dot11OperationEntry.hiddenAP) - priv->pmib->dot11OperationEntry.hiddenAP = 1; - - if(priv->stactrl.stactrl_hiddenAP_aging != STACTRL_HIDDENAP_EXPIRE) - priv->stactrl.stactrl_hiddenAP_aging = STACTRL_HIDDENAP_EXPIRE; - return 1; -} - -#endif -#endif /* STA_CONTROL */ +/* + * a4 sta functions + * + * $Id: 8192cd_a4_sta.c,v 1.1 2010/10/13 06:38:58 davidhsu Exp $ + * + * Copyright (c) 2010 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define _8192CD_STA_CONTROL_C_ + +#ifdef __KERNEL__ +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" + +#ifdef STA_CONTROL +#define STA_CONTROL_DEBUGMSG +#ifdef STA_CONTROL_DEBUGMSG +unsigned char stactrl_debug_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; + +int DEBUG_TIME_INETRVAL = 5; + +#define STACTRL_DEBUG(mac, fmt, args...) \ + do { \ + if(memcmp(mac, stactrl_debug_mac, MACADDRLEN)==0) \ + panic_printk("[%s, %d][%s] "fmt" from %02x:%02x:%02x:%02x:%02x:%02x\n",__func__,__LINE__, priv->dev->name, ## args, mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]); \ + }while(0) + +#define STACTRL_INIT_DEBUG(fmt, args...) panic_printk("[%s, %d][%s] "fmt, __func__,__LINE__, priv->dev->name, ## args); + +#else +#define STACTRL_DEBUG(mac, fmt, args...) {} +#define STACTRL_INIT_DEBUG +#endif + +__inline__ static int stactrl_mac_hash(unsigned char *networkAddr, int hash_size) +{ + unsigned long x; + + x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5]; + + return x & (hash_size - 1); +} + +__inline__ static void stactrl_mac_hash_link(struct stactrl_link_list *link, struct stactrl_link_list **head) +{ + link->next_hash = *head; + + if (link->next_hash != NULL) + link->next_hash->pprev_hash = &link->next_hash; + *head = link; + link->pprev_hash = head; +} + +__inline__ static void stactrl_mac_hash_unlink(struct stactrl_link_list *link) +{ + *(link->pprev_hash) = link->next_hash; + if (link->next_hash != NULL) + link->next_hash->pprev_hash = link->pprev_hash; + link->next_hash = NULL; + link->pprev_hash = NULL; +} + + +#ifdef CONFIG_RTL_PROC_NEW +int stactrl_info_read(struct seq_file *s, void *data) +#else +int stactrl_info_read(char *buf, char **start, off_t offset, int length, int *eof, void *data) +#endif +{ + struct net_device *dev = PROC_GET_DEV(); + struct rtl8192cd_priv *priv = GET_DEV_PRIV(dev); + struct stactrl_preferband_entry * prefer_ent; + struct stactrl_block_entry * block_ent; + + + int i; + int pos = 0; + PRINT_ONE(" -- sta control info -- ", "%s", 1); + PRINT_ONE(priv->stactrl.stactrl_status, " sta control status: %d", 1); + PRINT_ONE(priv->stactrl.stactrl_prefer, " is prefer band: %d", 1); + PRINT_ONE(STA_CONTROL_ALGO, " algorithm: %d", 1); + + if(priv->stactrl.stactrl_status) { + if(priv->stactrl.stactrl_prefer) + { + PRINT_ONE(priv->stactrl.stactrl_priv_sc->dev->name, " non-prefer band: %s", 1); + PRINT_ONE(" -- prefer band capable client list -- ", "%s", 1); + for (i=0; istactrl.stactrl_preferband_ent[i]); + if (prefer_ent->used) + { + PRINT_ARRAY_ARG(" STA_MAC: ", prefer_ent->mac, "%02x", MACADDRLEN); + PRINT_ONE(prefer_ent->rssi, " rssi: %d", 1); + PRINT_ONE(prefer_ent->aging, " aging: %d", 1); +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + PRINT_ONE(prefer_ent->retry, " retry: %d", 1); + PRINT_ONE(prefer_ent->local, " local: %d", 1); + if(prefer_ent->kickoff > 0) + PRINT_ONE(prefer_ent->kickoff, " kickoff: %d", 1); + } + } + if(STACTRL_BLOCK_5G){ + /* prefer band block entry */ + PRINT_ONE(" -- prefer band blocklist -- ", "%s", 1); + for (i=0; istactrl.stactrl_block_ent[i]); + if (block_ent->used) + { + PRINT_ARRAY_ARG(" Block STA_MAC: ", block_ent->mac, "%02x", MACADDRLEN); + PRINT_ONE(block_ent->timerX, " timerX: %d", 1); + PRINT_ONE(block_ent->retryY, " retryY: %d", 1); + PRINT_ONE(block_ent->aging, " aging: %d", 1); + } + } + } +#endif + } + else + { + PRINT_ONE(priv->stactrl.stactrl_priv_sc->dev->name, " prefer band: %s", 1); + PRINT_ONE(" -- non-prefer band blocklist -- ", "%s", 1); + for (i=0; istactrl.stactrl_block_ent[i]); + if (block_ent->used) + { + PRINT_ARRAY_ARG(" STA_MAC: ", block_ent->mac, "%02x", MACADDRLEN); + PRINT_ONE(block_ent->timerX, " timerX: %d", 1); + PRINT_ONE(block_ent->retryY, " retryY: %d", 1); +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + PRINT_ONE(block_ent->aging, " aging: %d", 1); +#endif + } + } + + if(STACTRL_BLOCK_5G){ + PRINT_ONE(" -- non-prefer band prefer list -- ", "%s", 1); + for (i=0; istactrl.stactrl_preferband_ent[i]); + if (prefer_ent->used) + { + PRINT_ARRAY_ARG(" STA_MAC: ", prefer_ent->mac, "%02x", MACADDRLEN); + PRINT_ONE(prefer_ent->rssi, " rssi: %d", 1); + PRINT_ONE(prefer_ent->aging, " aging: %d", 1); + + PRINT_ONE(prefer_ent->retry, " retry: %d", 1); + PRINT_ONE(prefer_ent->local, " local: %d", 1); + if(prefer_ent->kickoff > 0) + PRINT_ONE(prefer_ent->kickoff, " kickoff: %d", 1); + } + } + } + } + } + +#ifdef STA_CONTROL_DEBUGMSG + PRINT_ONE(" -- debug mac -- ", "%s", 1); + PRINT_ARRAY_ARG(" STA_MAC: ", stactrl_debug_mac, "%02x", MACADDRLEN); +#endif + return pos; +} + +int stactrl_info_write(struct file *file, const char *buffer, + unsigned long count, void *data) +{ +#ifdef STA_CONTROL_DEBUGMSG + if (buffer) + { + get_array_val(stactrl_debug_mac, (char *)buffer, count); + } +#endif + return count; +} + + +void stactrl_init(struct rtl8192cd_priv *priv) +{ + struct rtl8192cd_priv *priv_sc; + struct rtl8192cd_priv *prefer_priv; + int i; + + STACTRL_INIT_DEBUG("groupID: %d\n", priv->pmib->staControl.stactrl_groupID); + + if(priv->pmib->staControl.stactrl_enable > 1) + priv->pmib->staControl.stactrl_enable = 1; + if(priv->pmib->staControl.stactrl_prefer_band > 1) + priv->pmib->staControl.stactrl_prefer_band = 1; + + priv->stactrl.stactrl_status = 0; + priv->stactrl.stactrl_priv_sc = NULL; + priv->stactrl.stactrl_block5G = 0; + priv->stactrl.stactrl_enable_hiddenAP = 0; + + if(!(OPMODE & WIFI_AP_STATE) || priv->pmib->staControl.stactrl_enable == 0) { + STACTRL_INIT_DEBUG("WARNING: not ap mode or not enabled\n"); + return; + } + + if(priv->pmib->staControl.stactrl_functions & BIT(0)){ + STACTRL_INIT_DEBUG("Enable block_5G feature\n"); + priv->stactrl.stactrl_block5G = 1; + } + else + STACTRL_INIT_DEBUG("Disable block_5G feature\n"); + + if(priv->pmib->staControl.stactrl_functions & BIT(1)){ + STACTRL_INIT_DEBUG("Enable hiddenAP feature\n"); + priv->stactrl.stactrl_enable_hiddenAP = 1; + } + else + STACTRL_INIT_DEBUG("Disable hiddenAP feature\n"); + + /*search other band to find the priv with same groupID*/ + for(i = 0; i < RTL8192CD_NUM_VWLAN+1; i++) { + if(i == 0) { + priv_sc = GET_ROOT(priv)->stactrl.stactrl_rootpriv_sc; + } + #ifdef MBSSID + else { /*search vap of other band*/ + priv_sc = GET_ROOT(priv)->stactrl.stactrl_rootpriv_sc->pvap_priv[i - 1]; + + } + #endif + if((priv_sc!=NULL) && priv_sc->pmib->staControl.stactrl_groupID == priv->pmib->staControl.stactrl_groupID && + IS_DRV_OPEN(priv_sc) && + priv_sc->pmib->staControl.stactrl_enable == 1 && + (priv_sc->pmib->dot11OperationEntry.opmode & WIFI_AP_STATE) && + priv_sc->stactrl.stactrl_status == 0) + { + priv->stactrl.stactrl_priv_sc = priv_sc; + break; + } + } + + + if(priv->stactrl.stactrl_priv_sc == NULL || priv_sc == NULL) { /*can not find other band with same groupID*/ + STACTRL_INIT_DEBUG("WARNING: not find available priv\n"); + return; + } + + STACTRL_INIT_DEBUG("find other band : %s\n", priv->stactrl.stactrl_priv_sc->dev->name); + priv_sc->stactrl.stactrl_priv_sc = priv; + + + /*find other band's priv with same groupID*/ + /*setting prefer band and non-prefer band*/ + priv->stactrl.stactrl_prefer = priv->pmib->staControl.stactrl_prefer_band; + priv->stactrl.stactrl_priv_sc->stactrl.stactrl_prefer = priv->pmib->staControl.stactrl_prefer_band?0:1; + + + /* memory allocated structure*/ + if(priv->stactrl.stactrl_prefer) { + prefer_priv = priv; + } + else { + prefer_priv = priv->stactrl.stactrl_priv_sc; + } + priv_sc = prefer_priv->stactrl.stactrl_priv_sc; + + + STACTRL_INIT_DEBUG("prefer band : %s, non-prefer band: %s\n", prefer_priv->dev->name, priv_sc->dev->name); + + /*check SSID of different bands */ + if(strcmp(prefer_priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, priv_sc->pmib->dot11StationConfigEntry.dot11DesiredSSID)){ + STACTRL_INIT_DEBUG("WARNING: different SSID of preferband(%s) and non-preferband(%s)\n", + prefer_priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, + priv_sc->pmib->dot11StationConfigEntry.dot11DesiredSSID); + return; + } + + prefer_priv->stactrl.stactrl_preferband_ent = (struct stactrl_preferband_entry *) + kmalloc((sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM), GFP_ATOMIC); + if (!prefer_priv->stactrl.stactrl_preferband_ent) { + printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); + goto err; + } + memset(prefer_priv->stactrl.stactrl_preferband_machash, 0, sizeof(prefer_priv->stactrl.stactrl_preferband_machash)); + memset(prefer_priv->stactrl.stactrl_preferband_ent, 0, sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); + + /* malloc prefrband_ent for non-prefer band */ + if(STACTRL_BLOCK_5G){ + priv_sc->stactrl.stactrl_preferband_ent = (struct stactrl_preferband_entry *) + kmalloc((sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM), GFP_ATOMIC); + if (!priv_sc->stactrl.stactrl_preferband_ent) { + printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); + goto err; + } + memset(priv_sc->stactrl.stactrl_preferband_machash, 0, sizeof(priv_sc->stactrl.stactrl_preferband_machash)); + memset(priv_sc->stactrl.stactrl_preferband_ent, 0, sizeof(struct stactrl_preferband_entry) * MAX_STACTRL_PREFERBAND_NUM); + } + + priv_sc->stactrl.stactrl_block_ent = (struct stactrl_block_entry *) + kmalloc((sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM), GFP_ATOMIC); + if (!priv_sc->stactrl.stactrl_block_ent) { + printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); + goto err; + } + memset(priv_sc->stactrl.stactrl_block_machash, 0, sizeof(priv_sc->stactrl.stactrl_block_machash)); + memset(priv_sc->stactrl.stactrl_block_ent, 0, sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); + +/* malloc stactrl_block_ent for prefer band */ + if(STACTRL_BLOCK_5G){ + prefer_priv->stactrl.stactrl_block_ent = (struct stactrl_block_entry *) + kmalloc((sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM), GFP_ATOMIC); + if (!prefer_priv->stactrl.stactrl_block_ent) { + printk(KERN_ERR "Can't kmalloc for stactrl_preferband_entry (size %d)\n", sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); + goto err; + } + memset(prefer_priv->stactrl.stactrl_block_machash, 0, sizeof(prefer_priv->stactrl.stactrl_block_machash)); + memset(prefer_priv->stactrl.stactrl_block_ent, 0, sizeof(struct stactrl_block_entry) * MAX_STACTRL_BLOCK_NUM); + } + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 + init_timer(&priv_sc->stactrl.stactrl_timer); + priv_sc->stactrl.stactrl_timer.data = (unsigned long) priv_sc; + priv_sc->stactrl.stactrl_timer.function = stactrl_non_prefer_expire; + mod_timer(&priv_sc->stactrl.stactrl_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(STACTRL_NON_PREFER_TIMER)); +#endif + +#ifdef SMP_SYNC + spin_lock_init(&(prefer_priv->stactrl.stactrl_lock)); + spin_lock_init(&(priv_sc->stactrl.stactrl_lock)); +#endif + + /*start up sta control*/ + prefer_priv->stactrl.stactrl_status = 1; + priv_sc->stactrl.stactrl_status = 1; + priv_sc->stactrl.stactrl_hiddenAP_aging = 0; + return; + + +err: + if(prefer_priv->stactrl.stactrl_preferband_ent) + kfree(prefer_priv->stactrl.stactrl_preferband_ent); + if(priv_sc->stactrl.stactrl_block_ent) + kfree(priv_sc->stactrl.stactrl_block_ent); + if(STACTRL_BLOCK_5G){ + if(priv_sc->stactrl.stactrl_preferband_ent) + kfree(priv_sc->stactrl.stactrl_preferband_ent); + if(prefer_priv->stactrl.stactrl_block_ent) + kfree(prefer_priv->stactrl.stactrl_block_ent); + } + + + return; +} + + +void stactrl_deinit(struct rtl8192cd_priv *priv) +{ + struct rtl8192cd_priv *priv_sc; + struct rtl8192cd_priv *prefer_priv; + + STACTRL_INIT_DEBUG("\n"); + if(priv->stactrl.stactrl_status) { + if(priv->stactrl.stactrl_prefer) { + prefer_priv = priv; + } + else { + prefer_priv = priv->stactrl.stactrl_priv_sc; + } + priv_sc = prefer_priv->stactrl.stactrl_priv_sc; + + STACTRL_INIT_DEBUG("prefer band : %s, non-prefer band: %s\n", prefer_priv->dev->name, priv_sc->dev->name); + + if(prefer_priv->stactrl.stactrl_preferband_ent) + kfree(prefer_priv->stactrl.stactrl_preferband_ent); + if(priv_sc->stactrl.stactrl_block_ent) + kfree(priv_sc->stactrl.stactrl_block_ent); + + if(STACTRL_BLOCK_5G){ + if(priv_sc->stactrl.stactrl_preferband_ent) + kfree(priv_sc->stactrl.stactrl_preferband_ent); + if(prefer_priv->stactrl.stactrl_block_ent) + kfree(prefer_priv->stactrl.stactrl_block_ent); + } + + prefer_priv->stactrl.stactrl_status = 0; + priv_sc->stactrl.stactrl_status = 0; + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 + if (timer_pending(&priv_sc->stactrl.stactrl_timer)) + { + del_timer(&priv_sc->stactrl.stactrl_timer); + } +#endif + } +} + +static struct stactrl_block_entry *stactrl_block_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + unsigned long offset; + int hash; + struct stactrl_link_list *link; + struct stactrl_block_entry * ent; + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); + link = priv->stactrl.stactrl_block_machash[hash]; + while (link != NULL) + { + ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + if (!memcmp(ent->mac, mac, MACADDRLEN)) + { + return ent; + } + link = link->next_hash; + } + + return NULL; + +} + +/*return value: NULL: error, other:success*/ +static struct stactrl_block_entry * stactrl_block_add(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct stactrl_block_entry * ent = NULL; + int i, hash; + ASSERT(mac); + + //STACTRL_DEBUG(mac, "is added to [%s] blocklist",priv->dev->name); + + ent = stactrl_block_lookup(priv, mac); //Avoid exist mac to add again + if(ent != NULL) return ent; + + + /* find an empty entry*/ + for (i=0; istactrl.stactrl_block_ent[i].used) + { + ent = &(priv->stactrl.stactrl_block_ent[i]); + break; + } + } + + if(ent) + { + ent->used = 1; + memcpy(ent->mac, mac, MACADDRLEN); + ent->retryY = STACTRL_BLOCK_RETRY_Y; + ent->timerX = STACTRL_BLOCK_EXPIRE_X; + ent->timerZ = 0; +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + ent->aging = 0; +#endif + hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); + //panic_printk("[%s %d][%s]Target mac not existed. Add. aging:%d\n",__FUNCTION__,__LINE__,priv->dev->name, ent->aging); + stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_block_machash[hash])); + return ent; + } + + return NULL; +} + +/*return value: 0:success, other: error*/ +static int stactrl_block_delete(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + unsigned long offset; + int hash; + struct stactrl_link_list *link; + struct stactrl_block_entry * ent; + unsigned long flags; + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + panic_printk("[%s %d][%s]Taget mac:%02x:%02x:%02x:%02x:%02x:%02x\n", + __FUNCTION__,__LINE__,priv->dev->name, + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + hash = stactrl_mac_hash(mac, STACTRL_BLOCK_HASH_SIZE); + link = priv->stactrl.stactrl_block_machash[hash]; + while (link != NULL) + { + ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + if (!memcmp(ent->mac, mac, MACADDRLEN)) + { + ent->used = 0; + stactrl_mac_hash_unlink(link); + panic_printk("[%s %d][%s]Delete existed mac:%02x:%02x:%02x:%02x:%02x:%02x\n", + __FUNCTION__,__LINE__,priv->dev->name, + ent->mac[0],ent->mac[1],ent->mac[2],ent->mac[3],ent->mac[4],ent->mac[5]); + + STACTRL_DEBUG(ent->mac, "block delete"); + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + return 0; + } + link = link->next_hash; + } + panic_printk("[%s %d][%s]Block list NULL.\n", __FUNCTION__,__LINE__,priv->dev->name); + + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + return 1; + +} + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 +//20170106 +static unsigned char stactrl_sta_in_the_other_band(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct rtl8192cd_priv *priv_tmp=NULL; + struct stat_info *pstat=NULL; + extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; + int i; + + if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; + else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; + + if(priv_tmp==NULL){ + panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); + return 0; + } + + for(i=0; ipshare->aidarray[i] && (priv_tmp->pshare->aidarray[i]->used == TRUE)) + { + pstat = &(priv_tmp->pshare->aidarray[i]->station); + if(pstat && !memcmp(pstat->hwaddr, mac, MACADDRLEN)) + { + //20170321, return current rssi to associated AP + return pstat->rssi; + } + } + } + + return 0; +} + +//20170106 +static unsigned long stactrl_sta_in_the_prefer_band(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct stat_info *pstat=NULL; + int i; + + for(i=0; ipshare->aidarray[i] && (priv->pshare->aidarray[i]->used == TRUE)) + { + pstat = &(priv->pshare->aidarray[i]->station); + if(pstat && !memcmp(pstat->hwaddr, mac, MACADDRLEN)) + { + return pstat->link_time; + } + } + } + + return 0; +} +#endif + +static struct stactrl_preferband_entry *stactrl_preferband_sta_lookup(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + unsigned long offset; + int hash; + struct stactrl_link_list *link; + struct stactrl_preferband_entry * ent; + + offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); + hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); + link = priv->stactrl.stactrl_preferband_machash[hash]; + while (link != NULL) + { + ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); + if (!memcmp(ent->mac, mac, MACADDRLEN)) + { + return ent; + } + link = link->next_hash; + } + + return NULL; + +} + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 +void stactrl_preferband_sta_add(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char rssi, unsigned int is_local) +{ + struct stactrl_preferband_entry * ent; + int i, hash; + int temp_aging, temp_index; + unsigned long flags = 0; + ASSERT(mac); +#if 0 + panic_printk("add prefer %02x%02x%02x%02x%02x%02x %s, %p\n", + mac[0], mac[1],mac[2],mac[3],mac[4],mac[5], priv->dev->name, __builtin_return_address(0)); + + if(is_local){ + STACTRL_DEBUG(mac, "receive notify, rssi %d", rssi);} + else{ + STACTRL_DEBUG(mac, "receive probe, rssi %d", rssi);} +#endif + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + ent = stactrl_preferband_sta_lookup(priv, mac); + if(ent) /*find existed entry*/ + { + //STACTRL_DEBUG(mac, "update"); + if(rssi == 0) + goto ret; + + ent->aging = 0; + //reset retry counter when STA connects to the blocking band after it consumes retry counter to zero + //or when STA connects to the non-blocking band instead of resetting here + //ent->retry = STACTRL_BLOCK_RETRY_Y; + ent->rssi = rssi; + + //201701015 + //update local + if(ent->local==0 && is_local==1) + ent->local = is_local; + + goto ret; + } + + + /* find an empty entry*/ + ent = NULL; + for (i=0; istactrl.stactrl_preferband_ent[i].used) + { + //STACTRL_DEBUG(mac, "stactrl_preferband_sta_add: add new\n"); + ent = &(priv->stactrl.stactrl_preferband_ent[i]); + break; + } + } + + /* not found, find a entry with max aging*/ + if(ent == NULL) + { + temp_aging = 0; + temp_index = 0; + for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) + { + if(!priv->stactrl.stactrl_preferband_ent[i].local){//20170105 + temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; + temp_index = i; + } + } + + } + ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); + + //20170105 + //if all stactrl list is local, choose one local sta that have max aging + if(temp_index==0 && temp_aging==0 && ent->local==1){ + for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) + { + temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; + temp_index = i; + } + + } + ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); + } + STACTRL_DEBUG(mac, "[%s]del old entry, add new", priv->dev->name); + + //panic_printk("[STA_CONTROL][%s] entry full, remove max aging mac:%02x:%02x:%02x:%02x:%02x:%02x, local=%d, temp_index:%d, temp_aging:%d\n", + // priv->dev->name, + // ent->mac[0],ent->mac[1],ent->mac[2],ent->mac[3],ent->mac[4],ent->mac[5], ent->local, temp_index, temp_aging); + + stactrl_mac_hash_unlink(&(ent->link_list)); + } + + //STACTRL_DEBUG(mac, "[%s]add new reset\n", priv->dev->name); + ent->used = 1; + memcpy(ent->mac, mac, MACADDRLEN); + ent->aging = 0; + ent->retry = STACTRL_BLOCK_RETRY_Y; + ent->rssi = rssi; + ent->local = is_local;//20170105 + ent->kickoff = 0;//20170106 + hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); + STACTRL_DEBUG(mac, "[%s]add new reset, hash:%d", priv->dev->name, hash); + stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_preferband_machash[hash])); + +ret: + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); +} + +//20170105 +void stactrl_preferband_sta_del(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct stactrl_preferband_entry * ent; + int i, hash; + int temp_aging, temp_index; + unsigned long flags = 0; + ASSERT(mac); +#if 0 + panic_printk("add prefer %02x%02x%02x%02x%02x%02x %s, %p\n", + mac[0], mac[1],mac[2],mac[3],mac[4],mac[5], priv->dev->name, __builtin_return_address(0)); +#endif + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + ent = stactrl_preferband_sta_lookup(priv, mac); + if(ent != NULL) /*find existed entry*/ + { + ent->used = 0; + stactrl_mac_hash_unlink(&(ent->link_list)); + } + + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); +} + +static struct stactrl_preferband_entry * stactrl_is_dualband(struct rtl8192cd_priv *priv, unsigned char *mac) +{ + struct stactrl_preferband_entry *prefer_ent, *ret=NULL; + unsigned long flags=0; + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + prefer_ent = stactrl_preferband_sta_lookup(priv, mac); + if(prefer_ent && priv->assoc_num < NUM_STAT) + { +//20170321, return prefer_ent to check retry counter at non-prefer band + ret = prefer_ent; + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + return ret; +} + +static unsigned char stactrl_is_kickoff(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + struct stactrl_preferband_entry * prefer_ent; + unsigned char ret = 0; + unsigned long flags=0; + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + prefer_ent = stactrl_preferband_sta_lookup(priv, pstat->hwaddr); + if(prefer_ent && priv->assoc_num < NUM_STAT) + { + if(pstat->link_time > STACTRL_KICKOFF_TIME && (pstat->tx_avarage + pstat->rx_avarage) < STACTRL_KICKOFF_TP) { + ret = 1; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + return ret; +} + + +#else +void stactrl_preferband_sta_add(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char rssi) +{ + struct stactrl_preferband_entry * ent; + int i, hash; + int temp_aging, temp_index; + unsigned long flags = 0; + ASSERT(mac); + + STACTRL_DEBUG(mac, "receive probe"); + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + ent = stactrl_preferband_sta_lookup(priv, mac); + if(ent) /*find existed entry*/ + { + if(rssi < STACTRL_PREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE) + { + stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac); + } + + ent->aging = 0; + ent->rssi = rssi; + + goto ret; + } + + + /* find an empty entry*/ + ent = NULL; + for (i=0; istactrl.stactrl_preferband_ent[i].used) + { + ent = &(priv->stactrl.stactrl_preferband_ent[i]); + break; + } + } + + /* not found, find a entry with max aging*/ + if(ent == NULL) + { + temp_aging = 0; + temp_index = 0; + for (i=0; istactrl.stactrl_preferband_ent[i].used && temp_aging < priv->stactrl.stactrl_preferband_ent[i].aging) + { + temp_aging = priv->stactrl.stactrl_preferband_ent[i].aging; + temp_index = i; + } + + } + ent = &(priv->stactrl.stactrl_preferband_ent[temp_index]); + stactrl_mac_hash_unlink(&(ent->link_list)); + } + + ent->used = 1; + memcpy(ent->mac, mac, MACADDRLEN); + ent->aging = 0; + ent->rssi = rssi; + hash = stactrl_mac_hash(mac, STACTRL_PREFERBAND_HASH_SIZE); + stactrl_mac_hash_link(&(ent->link_list), &(priv->stactrl.stactrl_preferband_machash[hash])); + +ret: + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); +} + +static unsigned char stactrl_is_need(struct rtl8192cd_priv *priv, unsigned char *mac, unsigned char checkRSSI) +{ + struct stactrl_preferband_entry * prefer_ent; + struct rtl8192cd_priv *priv_temp; + int assoc_num = 0; + int i; + unsigned char ret = 0; + unsigned long flags=0; + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + prefer_ent = stactrl_preferband_sta_lookup(priv, mac); + if(prefer_ent) + { + assoc_num = GET_ROOT(priv)->assoc_num; + #ifdef MBSSID + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ + for (i=0; ipvap_priv[i]; + if(priv_temp && IS_DRV_OPEN(priv_temp)) + assoc_num += priv_temp-> assoc_num; + } + } + #endif + #ifdef UNIVERSAL_REPEATER + priv_temp = GET_VXD_PRIV(GET_ROOT(priv)); + if (priv_temp && IS_DRV_OPEN(priv_temp)) + assoc_num += priv_temp-> assoc_num; + #endif + #ifdef WDS + if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) + assoc_num ++; + #endif + + if(assoc_num < NUM_STAT) + { + if(checkRSSI) { + if(prefer_ent->rssi > STACTRL_PREFERBAND_RSSI) + ret = 1; + } + else + ret = 1; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + return ret; +} +#endif + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 +//20170103 +static int stactrl_check_if_kickoff(struct rtl8192cd_priv *priv,unsigned char* kickoff_mac) +{ + struct rtl8192cd_priv *priv_tmp=NULL; + extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; + int i; + + if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; + else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; + + if(priv_tmp==NULL){ + panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); + return 0; + } + + for (i=0; istactrl.stactrl_preferband_ent[i].used) + { + if(!memcmp(priv_tmp->stactrl.stactrl_preferband_ent[i].mac, kickoff_mac, MACADDRLEN)) + { + if(priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff >= STACTRL_KICKOFF_TIMES) + { + //panic_printk("Hit %s mac: %02x:%02x:%02x:%02x:%02x:%02x, kickoff=%d\n", + // priv_tmp->dev->name, + // kickoff_mac[0],kickoff_mac[1],kickoff_mac[2], + // kickoff_mac[3],kickoff_mac[4],kickoff_mac[5], + // priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff); + return 1; + } + } + } + } + + return 0; +} + +//20170103 +static void stactrl_record_kickoff(struct rtl8192cd_priv *priv, unsigned char* kickoff_mac) +{ + struct rtl8192cd_priv *priv_tmp=NULL; + extern u32 if_priv_stactrl[NUM_WLAN_IFACE]; + int i; + int no_kickoff_mac=1; + + if(priv->pshare->wlandev_idx == 0)//wlan0, check wlan1 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[1]; + else if(priv->pshare->wlandev_idx == 1)//wlan1, check wlan0 + priv_tmp = (struct rtl8192cd_priv *)if_priv_stactrl[0]; + + if(priv_tmp==NULL){ + panic_printk("[STA_CONTROL] Error, priv_tmp should not be NULL !!\n"); + return; + } + + for (i=0; istactrl.stactrl_preferband_ent[i].used){ + if(!memcmp(priv_tmp->stactrl.stactrl_preferband_ent[i].mac, kickoff_mac, MACADDRLEN)) + { + priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff++; + STACTRL_DEBUG(kickoff_mac, "[%s] kickoff=%d", + priv_tmp->dev->name, priv_tmp->stactrl.stactrl_preferband_ent[i].kickoff); + no_kickoff_mac = 0; + break; + } + } + } + + if(no_kickoff_mac) + STACTRL_DEBUG(kickoff_mac, "[%s]is not in prefer entry",priv->dev->name); + + return; +} +#endif + +static void stactrl_preferband_expire(struct rtl8192cd_priv *priv) +{ + int i; + unsigned long offset; + struct stactrl_link_list *link, *temp_link; + struct stactrl_preferband_entry * ent; + unsigned long flags = 0; + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); + + for (i=0; istactrl.stactrl_preferband_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); + if(ent->used) + { + ent->aging++; +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + //20170106 + //reset kickoff + // 1. STA in preferband, reset kickoff after 60s + // 2. STA not connet to AP, reset kickoff after 30s + unsigned long preferband_linketime = 0; + unsigned char is_in_nonpreferband = 0 ; + preferband_linketime = stactrl_sta_in_the_prefer_band(priv, ent->mac); + is_in_nonpreferband = stactrl_sta_in_the_other_band(priv, ent->mac); + // check if in non prefer band and calc time + if(is_in_nonpreferband) + ent->sta_not_in_nonpreferband = 0; + else{ + if(ent->kickoff>0) + ent->sta_not_in_nonpreferband++;//sec + } + // STA connect to prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec + if(preferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && + ent->kickoff>0) + { + panic_printk("[STA_CONTROL][%s] remove %02x:%02x:%02x:%02x:%02x:%02x kickoff times, beacuse STA connect over %ds\n", + priv->dev->name, + ent->mac[0],ent->mac[1],ent->mac[2], + ent->mac[3],ent->mac[4],ent->mac[5], + STACTRL_KICKOFF_REMOVE_WHEN_LINK); + ent->kickoff = 0; + ent->sta_not_in_nonpreferband = 0; + } + // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec + if(preferband_linketime==0 && + ent->sta_not_in_nonpreferband>=STACTRL_KICKOFF_REMOVE && + ent->kickoff>0) + { + panic_printk("[STA_CONTROL][%s] remove %02x:%02x:%02x:%02x:%02x:%02x kickoff times, beacuse STA leave AP over %ds\n", + priv->dev->name, + ent->mac[0],ent->mac[1],ent->mac[2], + ent->mac[3],ent->mac[4],ent->mac[5], + STACTRL_KICKOFF_REMOVE); + ent->kickoff = 0; + ent->sta_not_in_nonpreferband = 0; + } + //update this client is local client + if(preferband_linketime>0) + ent->local = 1; +#else + if(ent->aging > STACTRL_PREFERBAND_EXPIRE) + { + ent->used = 0; + stactrl_mac_hash_unlink(link); + } +#endif + } + link = temp_link; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + +} + +/* timer: on prefer band */ +static void stactrl_preferband_expire_3_1(struct rtl8192cd_priv *priv) +{ + int i; + unsigned long offset; + struct stactrl_link_list *link, *temp_link; + struct stactrl_preferband_entry * ent, *ent1; + unsigned long flags = 0; + struct list_head *phead, *plist; + struct stat_info *pstat; + unsigned char kickoff_prefer; + struct stactrl_block_entry *block_ent; + unsigned long preferband_linketime = 0; + unsigned char is_in_nonpreferband = 0 ; + unsigned char sta_mac[16]; + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); + + for (i=0; istactrl.stactrl_preferband_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); + if(ent->used) + { + ent->aging++; + //20170106 + // reset kickoff, to make STA can be kickoff on non-prefer band + // 1. STA in preferband, reset kickoff after 60s + // 2. STA not connet to AP, reset kickoff after 30s + preferband_linketime = 0; + is_in_nonpreferband = 0 ; + preferband_linketime = stactrl_sta_in_the_prefer_band(priv, ent->mac); + is_in_nonpreferband = stactrl_sta_in_the_other_band(priv, ent->mac); + + // check if in non prefer band and calc time + if(is_in_nonpreferband){ + ent->sta_not_in_nonpreferband = 0; + if(ent->kickoff>0) + ent->sta_in_non_preferband++; + } + else{ + if(ent->kickoff>0) + ent->sta_not_in_nonpreferband++;//sec + } + + if( priv->up_time % DEBUG_TIME_INETRVAL==0 ) + STACTRL_DEBUG(ent->mac, "preferband_linketime:%d,not_in_nonpreferband:%d,in_nonpreferband:%d,kickoff:%d", + preferband_linketime, + ent->sta_not_in_nonpreferband, + is_in_nonpreferband, + ent->kickoff); + + // STA connect to prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec + if(preferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && ent->kickoff>0) + { + STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [prefer band] over %ds", + priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE_WHEN_LINK); + ent->kickoff = 0; + ent->sta_not_in_nonpreferband = 0; + } + + // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec + if(preferband_linketime==0 && + ent->sta_not_in_nonpreferband>=STACTRL_KICKOFF_REMOVE && ent->kickoff>0) + { + STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA leave AP over %ds", + priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE); + ent->kickoff = 0; + ent->sta_not_in_nonpreferband = 0; + } + + // STA connect to prefer-band, and kickoff is more than STACTRL_KICKOFF_TIMES + if(ent->kickoff >= STACTRL_KICKOFF_TIMES && ent->sta_in_non_preferband >=STACTRL_KICKOFF_REMOVE_WHEN_LINK){ + STACTRL_DEBUG(ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [non-prefer] band over %ds", + priv->dev->name, ent->kickoff, STACTRL_KICKOFF_REMOVE_WHEN_LINK); + ent->kickoff= 0; + ent->sta_in_non_preferband = 0; + } + + //update this client is local client + if(preferband_linketime>0) + ent->local = 1; + } + link = temp_link; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + +#if 1 + // if block time more than STACTRL_PREFERBAND_EXPIRE_Z, then un-block + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + for (i=0; istactrl.stactrl_block_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + block_ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + block_ent->aging++; + + if(block_ent->aging > STACTRL_BLOCK_EXPIRE_Z) + { + block_ent->used = 0; + stactrl_record_kickoff(priv, block_ent->mac); + stactrl_mac_hash_unlink(link); + STACTRL_DEBUG(ent->mac, "[%s]block expire, aging:%d", priv->dev->name, block_ent->aging); + } + link = temp_link; + } + } + + RESTORE_INT(flags); + SMP_UNLOCK_STACONTROL_LIST(flags); +#endif + + /*kickoff prefer band station(eg: sta go away), to force it to go through sta control process*/ + phead = &priv->asoc_list; + plist = phead; + + /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ + if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) + && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ + return 0; + } + + while ((plist = asoc_list_get_next(priv, plist)) != phead) + { + kickoff_prefer= 0; + pstat = list_entry(plist, struct stat_info, asoc_list); + if( priv->up_time % 5==0 ) + STACTRL_DEBUG(pstat->hwaddr, "rssi:%d", pstat->rssi); +/* +#ifdef CONFIG_IEEE80211V + if(pstat->bssTransSupport == TRUE && pstat->bssTransRejectionCount < 5){ + STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); + continue; + } +#endif +*/ + if(pstat->rssi <= STACTRL_PREFERBAND_RSSI) + { +#ifdef CONFIG_IEEE80211V + if(pstat->bssTransSupport == TRUE && pstat->bssTransPktSent < 5){ + STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); + pstat->bssTransPktSent++; + memcpy(priv->bssTransPara.bssid_mac, priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.dot11Bssid, MACADDRLEN); + if(issue_BSS_Trans_Req(priv, pstat->hwaddr, NULL) == 0) + { + pstat->bssTransExpiredTime = 0; + pstat->bssTransTriggered = TRUE; + priv->startCounting = TRUE; + + DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", + pstat->hwaddr[0], + pstat->hwaddr[1], + pstat->hwaddr[2], + pstat->hwaddr[3], + pstat->hwaddr[4], + pstat->hwaddr[5]); + } + else + { + DOT11VDEBUG("BSS Trans Req for bandsteering failed! \n"); + } + continue; + } +#endif + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + ent1 = stactrl_preferband_sta_lookup(priv, pstat->hwaddr); + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + + if(ent1==NULL) + continue; + + if(kickoff_prefer == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) { + kickoff_prefer = 1; + } + + //check if this client is kickoff more than threshold times + if((kickoff_prefer == 1) && (stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1)){ + kickoff_prefer = 0; + STACTRL_DEBUG(pstat->hwaddr, "[%s]is kickoff %d times already, do not kickoff again !!", + priv->dev->name, STACTRL_KICKOFF_TIMES); + } + + if(kickoff_prefer){ + stactrl_hidden_ap(priv); + + STACTRL_DEBUG(pstat->hwaddr, "Deauth it on prefer band"); + + SMP_LOCK_STACONTROL_LIST(flags); + block_ent = stactrl_block_add(priv, pstat->hwaddr); + if(block_ent) /*add success*/ + { + STACTRL_DEBUG(pstat->hwaddr, "[%s]block add success, aging:%d", priv->dev->name, block_ent->aging); + } + else + { + STACTRL_DEBUG(pstat->hwaddr, "[%s]block add fail", priv->dev->name); + } + SMP_UNLOCK_STACONTROL_LIST(flags); + + /* if DUT not recv deauth from STA, then the sta_info is not clear, + DUT will always tx deauth */ + // issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); //marked by tesia + //del_sta(priv, pstat->hwaddr); + issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); + + pstat->prepare_to_free = 1; + } + } + if (plist == plist->next) + break; + } +} + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + +/* timer: on non-prefer band */ +static void stactrl_non_prefer_expire(struct rtl8192cd_priv *priv) +{ + if(priv->stactrl.stactrl_hiddenAP_aging > 0){ + //printk("%s: hiddenAP_aging = %d\n", __FUNCTION__, priv->stactrl.stactrl_hiddenAP_aging); + if(priv->stactrl.stactrl_hiddenAP_aging == 1){ + if(priv->pmib->dot11OperationEntry.hiddenAP){ + printk("%s: reset hiddenAP to recover ssid in Beacon\n", __FUNCTION__); + priv->pmib->dot11OperationEntry.hiddenAP = 0; + } + } + priv->stactrl.stactrl_hiddenAP_aging--; + } + + int i; + unsigned long offset; + struct stactrl_link_list *link, *temp_link; + struct stactrl_block_entry * ent; + unsigned long flags = 0; + struct stat_info *pstat; + struct list_head *phead, *plist; + unsigned char kickoff; + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + for (i=0; istactrl.stactrl_block_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + ent->aging++; + if(ent->aging > STACTRL_BLOCK_EXPIRE) + { + ent->used = 0; + //20170106 + stactrl_record_kickoff(priv, ent->mac); + stactrl_mac_hash_unlink(link); + STACTRL_DEBUG(ent->mac, "block expire"); + + } + + link = temp_link; + } + } + + RESTORE_INT(flags); + SMP_UNLOCK_STACONTROL_LIST(flags); + + + /*kick out non-prefer band station, to force it to go through sta control process*/ + phead = &priv->asoc_list; + plist = phead; + + while ((plist = asoc_list_get_next(priv, plist)) != phead) + { + kickoff= 0; + pstat = list_entry(plist, struct stat_info, asoc_list); + if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) { + if(pstat->stactrl_candidate == 1) { + kickoff = 1; + } + + if(kickoff == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) + kickoff = 1; + + //20170103 + //check if this client is kickoff again + if((stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1) && (kickoff == 1)){ + kickoff = 0; + //panic_printk("[STA_CONTROL] mac:%02x:%02x:%02x:%02x:%02x:%02x is kickoff %d times already, do not kickoff again !!\n", + //pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], + //pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5], + //STACTRL_KICKOFF_TIMES); + } + + if(kickoff) + { /*check if it is a dual-band client*/ + #ifdef RTK_SMART_ROAMING + notify_hidden_ap(priv, STACTRL_HIDDEN_AP); + #endif + stactrl_hidden_ap(priv); + + STACTRL_DEBUG(pstat->hwaddr, "Deauth it on non-prefer band"); + SMP_LOCK_STACONTROL_LIST(flags); + ent = stactrl_block_add(priv, pstat->hwaddr); + if(ent) /*add success*/ + { + STACTRL_DEBUG(pstat->hwaddr, "block add"); + } + else + { + STACTRL_DEBUG(pstat->hwaddr, "block add fail"); + } + SMP_UNLOCK_STACONTROL_LIST(flags); + + DRV_RT_TRACE(priv, DRV_DBG_CONN_INFO, DRV_DBG_SERIOUS, "issue_deauth - %02X:%02X:%02X:%02X:%02X:%02X, _RSON_DISAOC_STA_LEAVING_\n", + pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); + issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); + //#ifdef RTK_SMART_ROAMING + pstat->prepare_to_free = 1; + //#endif + } + } + + if (plist == plist->next) + break; + } + +} + +static void stactrl_non_prefer_expire_3_1(struct rtl8192cd_priv *priv) +{ + if(priv->stactrl.stactrl_hiddenAP_aging > 0){ + //printk("%s: hiddenAP_aging = %d\n", __FUNCTION__, priv->stactrl.stactrl_hiddenAP_aging); + if(priv->stactrl.stactrl_hiddenAP_aging == 1){ + if(priv->pmib->dot11OperationEntry.hiddenAP){ + printk("%s: reset hiddenAP to recover ssid in Beacon\n", __FUNCTION__); + priv->pmib->dot11OperationEntry.hiddenAP = 0; + } + } + priv->stactrl.stactrl_hiddenAP_aging--; + } + + int i; + unsigned long offset; + struct stactrl_link_list *link, *temp_link; + struct stactrl_block_entry * ent; + unsigned long flags = 0; + struct stat_info *pstat; + struct list_head *phead, *plist; + unsigned char kickoff; + unsigned long nonpreferband_linketime = 0; + unsigned char is_in_preferband = 0; + struct stactrl_preferband_entry *prefer_ent, *prefer_ent1; + unsigned char sta_mac[16]; + + offset = (unsigned long)(&((struct stactrl_preferband_entry *)0)->link_list); + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + for (i=0; istactrl.stactrl_preferband_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + prefer_ent = (struct stactrl_preferband_entry *)((unsigned long)link - offset); + if(prefer_ent->used) + { + prefer_ent->aging++; + + //reset kickoff + // 1. STA in preferband, reset kickoff after 60s + // 2. STA not connet to AP, reset kickoff after 30s + nonpreferband_linketime = 0; + is_in_preferband = 0; + nonpreferband_linketime = stactrl_sta_in_the_prefer_band(priv, prefer_ent->mac); + is_in_preferband = stactrl_sta_in_the_other_band(priv, prefer_ent->mac); + + // check if in prefer band and calc time + if(is_in_preferband){ + prefer_ent->sta_not_in_preferband = 0; + + if(prefer_ent->kickoff>0) + prefer_ent->sta_in_prefer_band++; + } + else + if(prefer_ent->kickoff>0) + prefer_ent->sta_not_in_preferband++; + + if( priv->up_time % DEBUG_TIME_INETRVAL==0 ) + STACTRL_DEBUG(prefer_ent->mac, "nonpreferband_linketime:%d,not_in_preferband:%d,in_prefer_band:%d,kickoff:%d", + nonpreferband_linketime, + prefer_ent->sta_not_in_preferband, + prefer_ent->sta_in_prefer_band, + prefer_ent->kickoff); + + // STA connect to non-prefer band for STACTRL_KICKOFF_REMOVE_WHEN_LINK sec + if(nonpreferband_linketime>=STACTRL_KICKOFF_REMOVE_WHEN_LINK && prefer_ent->kickoff>0) + { + STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [non-prefer band] over %ds", + priv->dev->name,prefer_ent->kickoff,STACTRL_KICKOFF_REMOVE_WHEN_LINK); + prefer_ent->kickoff= 0; + prefer_ent->sta_not_in_preferband = 0; + } + + // STA is leaving AP for STACTRL_KICKOFF_REMOVE sec + if(nonpreferband_linketime==0 && + prefer_ent->sta_not_in_preferband>=STACTRL_KICKOFF_REMOVE && prefer_ent->kickoff>0) + { + STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA leave AP over %ds", + priv->dev->name, prefer_ent->kickoff, STACTRL_KICKOFF_REMOVE); + prefer_ent->kickoff= 0; + prefer_ent->sta_not_in_preferband = 0; + } + + // STA connect to prefer-band, and kickoff is more than STACTRL_KICKOFF_TIMES + if(prefer_ent->kickoff >= STACTRL_KICKOFF_TIMES && prefer_ent->sta_in_prefer_band >=STACTRL_KICKOFF_REMOVE_WHEN_LINK){ + STACTRL_DEBUG(prefer_ent->mac, "[%s]remove kickoff [%d] times, beacuse STA connect [prefer band] over %ds", + priv->dev->name,prefer_ent->kickoff,STACTRL_KICKOFF_REMOVE_WHEN_LINK); + prefer_ent->kickoff= 0; + prefer_ent->sta_in_prefer_band = 0; + } + + //update this client is local client + if(nonpreferband_linketime>0) + prefer_ent->local = 1; + } + link = temp_link; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + for (i=0; istactrl.stactrl_block_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + ent->aging++; + if(ent->aging > STACTRL_BLOCK_EXPIRE_Z) + { + ent->used = 0; + //20170106 + stactrl_record_kickoff(priv, ent->mac); + stactrl_mac_hash_unlink(link); + STACTRL_DEBUG(ent->mac, "[%s]block expire", priv->dev->name); + } + + link = temp_link; + } + } + + RESTORE_INT(flags); + SMP_UNLOCK_STACONTROL_LIST(flags); + + /*kickoff STA on non-prefer band. to force it to go through sta control process*/ + phead = &priv->asoc_list; + plist = phead; + + /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ + if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) + && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ + return 0; + } + + while ((plist = asoc_list_get_next(priv, plist)) != phead) + { + kickoff= 0; + pstat = list_entry(plist, struct stat_info, asoc_list); + + if(priv->up_time % 5==0) // just for debug + STACTRL_DEBUG(pstat->hwaddr, "rssi:%d", pstat->rssi); +/* +#ifdef CONFIG_IEEE80211V + if(pstat->bssTransSupport == TRUE && pstat->bssTransRejectionCount < 5){ + STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); + continue; + } +#endif +*/ + if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) + { +#ifdef CONFIG_IEEE80211V + if(pstat->bssTransSupport == TRUE && pstat->bssTransPktSent < 5){ + STACTRL_DEBUG(pstat->hwaddr, "sta support 11v, no band steering."); + pstat->bssTransPktSent++; + memcpy(priv->bssTransPara.bssid_mac, priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.dot11Bssid, MACADDRLEN); + if(issue_BSS_Trans_Req(priv, pstat->hwaddr, NULL) == SUCCESS) + { + pstat->bssTransExpiredTime = 0; + pstat->bssTransTriggered = TRUE; + priv->startCounting = TRUE; + + DOT11VDEBUG("Send BSS Trans Req to STA [SUCCESS]:[%02x][%02x][%02x][%02x][%02x][%02x] \n", + pstat->hwaddr[0], + pstat->hwaddr[1], + pstat->hwaddr[2], + pstat->hwaddr[3], + pstat->hwaddr[4], + pstat->hwaddr[5]); + } + else + { + DOT11VDEBUG("BSS Trans Req for bandsteering failed! \n"); + } + continue; + } +#endif + + if(pstat->stactrl_candidate == 1) + kickoff = 1; + if(kickoff == 0 && stactrl_is_kickoff(priv->stactrl.stactrl_priv_sc, pstat)) + kickoff = 1; + + //20170103 + //check if this client is kickoff more than threshold times + if((stactrl_check_if_kickoff(priv, pstat->hwaddr) == 1) && (kickoff == 1)){ + kickoff = 0; + panic_printk("[STA_CONTROL] mac:%02x:%02x:%02x:%02x:%02x:%02x is kickoff %d times already, do not kickoff again !!\n", + pstat->hwaddr[0], pstat->hwaddr[1], pstat->hwaddr[2], + pstat->hwaddr[3], pstat->hwaddr[4], pstat->hwaddr[5], + STACTRL_KICKOFF_TIMES); + } + + if(kickoff) { /*check if it is a dual-band client*/ + #ifdef RTK_SMART_ROAMING + notify_hidden_ap(priv, STACTRL_HIDDEN_AP); + #endif + stactrl_hidden_ap(priv); + + STACTRL_DEBUG(pstat->hwaddr, "Deauth it on non-prefer band"); + SMP_LOCK_STACONTROL_LIST(flags); + ent = stactrl_block_add(priv, pstat->hwaddr); + if(ent) /*add success*/ + { + STACTRL_DEBUG(pstat->hwaddr, "block add success"); + } + else + { + STACTRL_DEBUG(pstat->hwaddr, "block add fail"); + } + SMP_UNLOCK_STACONTROL_LIST(flags); + + //issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); //marked by tesia + //del_sta(priv, pstat->hwaddr); + issue_deauth(priv, pstat->hwaddr, _RSON_DISAOC_STA_LEAVING_); + + pstat->prepare_to_free = 1; + } + } + + if (plist == plist->next) + break; + } +} + +void stactrl_expire(struct rtl8192cd_priv *priv) +{ + if(priv->stactrl.stactrl_prefer){ + if(!STACTRL_BLOCK_5G) + stactrl_preferband_expire(priv); + else + stactrl_preferband_expire_3_1(priv); + } + else{ + if(!STACTRL_BLOCK_5G) + stactrl_non_prefer_expire(priv); + else + stactrl_non_prefer_expire_3_1(priv); + } +} + +#else +void stactrl_non_prefer_expire(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + int i; + unsigned long offset; + struct stactrl_link_list *link, *temp_link; + struct stactrl_block_entry * ent; + unsigned long flags = 0; + + offset = (unsigned long)(&((struct stactrl_block_entry *)0)->link_list); + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + for (i=0; istactrl.stactrl_block_machash[i]; + while (link != NULL) + { + temp_link = link->next_hash; + ent = (struct stactrl_block_entry *)((unsigned long)link - offset); + if(ent->timerZ) + { + ent->timerZ--; + if(ent->timerZ == 0) + { + ent->used = 0; + stactrl_mac_hash_unlink(link); + STACTRL_DEBUG(ent->mac, "block del"); + } + } + else if(ent->timerX) + { + ent->timerX--; + + if(ent->timerX == 0) + { + ent->timerZ = STACTRL_BLOCK_EXPIRE_Z; + STACTRL_DEBUG(ent->mac, "block Z stage"); + } + } + + link = temp_link; + } + } + + RESTORE_INT(flags); + SMP_UNLOCK_STACONTROL_LIST(flags); + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO2 + mod_timer(&priv->stactrl.stactrl_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(STACTRL_NON_PREFER_TIMER)); +#endif +} + + +void stactrl_expire(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + + if(priv->stactrl.stactrl_prefer) + { + stactrl_preferband_expire(priv); + } + + + if(priv->stactrl.stactrl_prefer == 0) + { + #if STA_CONTROL_ALGO == STA_CONTROL_ALGO1 + stactrl_non_prefer_expire((unsigned long)priv); + #endif + + + /*kick out non-prefer band station, to force it to go through sta control process*/ + phead = &priv->asoc_list; + plist = phead; + + while ((plist = asoc_list_get_next(priv, plist)) != phead) + { + pstat = list_entry(plist, struct stat_info, asoc_list); + if(pstat->stactrl_candidate) { + if(pstat->rssi > STACTRL_NONPREFERBAND_RSSI) { + if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, pstat->hwaddr, 0)) { /*check if it is a dual-band client*/ + STACTRL_DEBUG(pstat->hwaddr, "Dissasociate it on non-prefer band"); + unsigned char sta_mac[16]; + sprintf(sta_mac,"%02X%02X%02X%02X%02X%02X", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); + + DRV_RT_TRACE(priv, DRV_DBG_CONN_INFO, DRV_DBG_SERIOUS, "del_sta - %02X:%02X:%02X:%02X:%02X:%02X\n", + pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); + + del_sta(priv, sta_mac); + } + } + } + + if (plist == plist->next) + break; + + } + + + } +} +#endif + +#if STA_CONTROL_ALGO == STA_CONTROL_ALGO1 +/*return: 0: continu process(no stactrl), 1: ignore, 2: error code, 3: continue process(have done stactrl process)*/ +unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) +{ + struct stactrl_block_entry * block_ent; + unsigned char ret = 0; + unsigned long flags = 0; + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + block_ent = stactrl_block_lookup(priv, mac); + if(block_ent) + { + ret = 3; + if(block_ent->timerX && block_ent->retryY) + { + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + ret = 2; + block_ent->retryY--; + + if(block_ent->retryY == 0) + { + block_ent->timerZ = STACTRL_BLOCK_EXPIRE_Z; + STACTRL_DEBUG(block_ent->mac, "block Z stage"); + } + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + } + else + { + SMP_UNLOCK_STACONTROL_LIST(flags); + if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, mac, 1)) + { + ret = 1; + SMP_LOCK_STACONTROL_LIST(flags); + block_ent = stactrl_block_add(priv, mac); + if(block_ent) /*add success*/ + { + STACTRL_DEBUG(mac, "block add"); + } + else + { + STACTRL_DEBUG(mac, "block add fail"); + } + SMP_UNLOCK_STACONTROL_LIST(flags); + } + } + RESTORE_INT(flags); + + STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); + + return ret; +} + +#elif STA_CONTROL_ALGO == STA_CONTROL_ALGO2 +/*return: 0: continu process(no stactrl), 1: ignore, 2: error code, 3: continue process(have done stactrl process)*/ +unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) +{ + struct stactrl_block_entry * block_ent; + unsigned char ret = 0; + + unsigned long flags = 0; + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + block_ent = stactrl_block_lookup(priv, mac); + if(block_ent) + { + ret = 3; + if(block_ent->timerZ) + { + if(frame_type == WIFI_ASSOCREQ) + { + if(block_ent->retryY) + { + block_ent->retryY--; + ret = 2; + } + } + } + else + { + ret = 1; + } + } + else + { + if(stactrl_is_need(priv->stactrl.stactrl_priv_sc, mac, 1)) + { + ret = 1; + if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ) + { + block_ent = stactrl_block_add(priv, mac); + if(block_ent) /*add success*/ + { + STACTRL_DEBUG(mac, "block add"); + } + else + { + STACTRL_DEBUG(mac, "block add fail"); + } + } + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + + STACTRL_DEBUG(mac, "receive %s drop: %d rssi: %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); + + return ret; +} +#elif STA_CONTROL_ALGO == STA_CONTROL_ALGO3 + +unsigned char stactrl_check_request(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) + { + struct stactrl_block_entry * block_ent; + struct stactrl_preferband_entry *prefer_ent; + unsigned char ret = 0; + unsigned long flags = 0; + unsigned char delete_blockent = 0; + + if(priv->stactrl.stactrl_prefer){ + prefer_ent = stactrl_is_dualband(priv,mac); + if(prefer_ent){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + goto ret; + } + + prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); + if(prefer_ent){ + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + //20170321, associated at prefer band with a prefer band rssi + if(stactrl_sta_in_the_other_band(priv, mac) > STACTRL_PREFERBAND_RSSI){ + STACTRL_DEBUG(mac, "sta in the preferband with good rssi"); + ret = 1; + } + //20170321, initial connect with non-prefer band rssi + else if (rssi > STACTRL_NONPREFERBAND_RSSI){ + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + STACTRL_DEBUG(mac, "retry = %d", prefer_ent->retry); + if(prefer_ent->retry > 0){ + ret = 1; + prefer_ent->retry--; + } + else{ + //connect to non-preferband and reset the retry value + STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); + prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; + } + } + } + else{ + block_ent = stactrl_block_lookup(priv, mac); + if(block_ent) + { + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + if(block_ent->retryY) { + ret = 1; + block_ent->retryY--; + if(block_ent->retryY == 0) + { + delete_blockent = 1; + } + } + } + } + } + + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + + if(delete_blockent){ + panic_printk("%s: call stactrl_block_delete\n",__FUNCTION__); + if(stactrl_block_delete(priv, mac) == 0){ + //20170103 + //record STA is kickoff and on the other band's prefer table + stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); + } + } + } + ret: + STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); + + return ret; +} + +/*return: 0: continu process(no stactrl), 1: block*/ +/* in processing OnProbeReq or (onAuth ?) or OnAssocReq */ +unsigned char stactrl_check_request_on_nonpreferband(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) +{ + struct stactrl_block_entry *block_prefer_ent, *block_nonprefer; + struct stactrl_preferband_entry *prefer_ent, *own_ent; + unsigned char ret = 0; + unsigned long flags = 0; + unsigned char delete_blockent = 0; + unsigned char block_prefer = 0; + + prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); + own_ent = stactrl_is_dualband(priv,mac); + if(prefer_ent){ + /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ + if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) + && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ + return 0; + } + + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + +// if block prefer-band + block_prefer_ent = stactrl_block_lookup(priv->stactrl.stactrl_priv_sc, mac); + if(block_prefer_ent){ + ret = 0; + STACTRL_DEBUG(mac, "[%s]Sta in prefer-band block entry, Block prefer band !!!",(frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc"))); + block_prefer= 1; + if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ + if(own_ent){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + own_ent->retry = STACTRL_BLOCK_RETRY_Y; + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + } + }else + block_prefer = 0; + + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + +//20170321, associated at prefer band with a prefer band rssi + if(!block_prefer){ + if((stactrl_sta_in_the_other_band(priv, mac) > STACTRL_PREFERBAND_RSSI) && (frame_type != WIFI_AUTH)){ + ret = 1; + //panic_printk("[%s %d]associated at prefer band.\n", __FUNCTION__,__LINE__); + } +//20170321, initial connect with non-prefer band rssi + else if (rssi > STACTRL_NONPREFERBAND_RSSI){ // 35 + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + STACTRL_DEBUG(mac,"retry = %d", prefer_ent->retry); + if(prefer_ent->retry > 0){ + ret = 1; + prefer_ent->retry--; + } + else{ + //connect to non-preferband and reset the retry value + STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); + prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } +// initial connect with small rssi + else{ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + block_nonprefer = stactrl_block_lookup(priv, mac); + if(block_nonprefer) + { + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + if(block_nonprefer->retryY) { + ret = 1; + block_nonprefer->retryY--; + if(block_nonprefer->retryY == 0) + { + delete_blockent = 1; + } + } + } + }else{ + // reset the retry counter of 5G when 2G is better choice + if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ + if(own_ent){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + own_ent->retry = STACTRL_BLOCK_RETRY_Y; + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + } + if(frame_type == WIFI_ASSOCREQ) + STACTRL_DEBUG(mac, "RSSI is low and connect to 2G."); + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + } + + if(delete_blockent){ + STACTRL_DEBUG(mac, "[%s]Block del bcz STA try connect more than [%d] times. No block the STA again!", + priv->dev->name); + if(stactrl_block_delete(priv, mac) == 0){ + //20170103 + //record STA is kickoff and on the other band's prefer table + stactrl_record_kickoff(priv, mac); + } + } + } + /*else{ + STACTRL_DEBUG(mac, "single band."); + }*/ + + //STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); + return ret; +} + +unsigned char stactrl_check_request_on_preferband(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi) +{ + struct stactrl_block_entry * block_ent; + unsigned char ret = 0; + unsigned long flags = 0; + unsigned char delete_blockent = 0; + struct stactrl_preferband_entry *prefer_ent; + + prefer_ent = stactrl_is_dualband(priv->stactrl.stactrl_priv_sc, mac); + if(prefer_ent){ + /*no need to block STAs if the number of associated STAs of the other band reaches the threshold*/ + if((priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum > 0) + && (get_assoc_sta_num(priv->stactrl.stactrl_priv_sc, 0) >= priv->stactrl.stactrl_priv_sc->pmib->dot11StationConfigEntry.supportedStaNum)){ + return 0; + } + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + +// if block prefer-band + block_ent = stactrl_block_lookup(priv, mac); + if(block_ent){ + //STACTRL_DEBUG(mac, "in block list"); + /* if sta in prefer band block list, we should not always block prefer band */ + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + if(block_ent->retryY) { + ret = 1; + block_ent->retryY--; + if(block_ent->retryY == 0) + { + STACTRL_DEBUG(mac, "Block del bcz STA try connect more than [%d] times. No block the STA again!", STACTRL_BLOCK_RETRY_Y); + panic_printk("[%s %d]call stactrl_block_delete\n", __FUNCTION__,__LINE__); + if(stactrl_block_delete(priv, mac) == 0) + stactrl_record_kickoff(priv, mac); + } + } + } + //panic_printk("[%s %d]block prefer band\n", __FUNCTION__,__LINE__); + } + else{ + //STACTRL_DEBUG(mac, "not in block list"); + if((stactrl_sta_in_the_other_band(priv, mac) < STACTRL_NONPREFERBAND_RSSI) && + (stactrl_sta_in_the_other_band(priv, mac) > 0) && + (frame_type != WIFI_AUTH)){ + STACTRL_DEBUG(mac, "sta associates in 2G with low RSSI."); + ret = 1; + } + else if (rssi < STACTRL_PREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE){ + if(frame_type == WIFI_PROBEREQ) + { + ret = 1; + } + else if(frame_type == WIFI_ASSOCREQ) + { + STACTRL_DEBUG(mac, "retry = %d", prefer_ent->retry); + if(prefer_ent->retry > 0){ + ret = 1; + prefer_ent->retry--; + } + else{ + //connect to preferband and reset the retry value + STACTRL_DEBUG(mac, "retry counter = 0, stop blocking."); + prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; + } + } + } + else{ + // reset the retry counter of 1G when 5G is better choice + if(frame_type == WIFI_AUTH || frame_type == WIFI_ASSOCREQ){ + prefer_ent = stactrl_is_dualband(priv,mac); + if(prefer_ent){ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + prefer_ent->retry = STACTRL_BLOCK_RETRY_Y; + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + } + if(frame_type == WIFI_ASSOCREQ) + STACTRL_DEBUG(mac, "RSSI is high and connect to 5G."); + } + } + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + } + /*else{ + STACTRL_DEBUG(mac, "single band."); + }*/ + + //STACTRL_DEBUG(mac, "receive %s drop: %d rssi %d", (frame_type == WIFI_PROBEREQ? "probe": (frame_type == WIFI_AUTH? "auth": "assoc")),ret, rssi); + return ret; +} + +/* return 0: success, 1: reject*/ +unsigned char stactrl_OnAssocReq(struct rtl8192cd_priv *priv, unsigned char *mac, int frame_type, unsigned char rssi, unsigned char * candidate) { + unsigned short val16 = 0; + unsigned long flags = 0; + struct stactrl_block_entry *block_ent_prefer = NULL; + + if(priv->stactrl.stactrl_block5G){ + if(priv->stactrl.stactrl_prefer){ + /* check if block prefer band*/ + SAVE_INT_AND_CLI(flags); + SMP_LOCK_STACONTROL_LIST(flags); + + block_ent_prefer = stactrl_block_lookup(priv, mac); + if(block_ent_prefer){ + val16 = stactrl_check_request_on_preferband(priv, mac, WIFI_ASSOCREQ, rssi); + if(val16){ + STACTRL_DEBUG(mac, "recv assreq, block prefer"); + return 1; + }else{ + STACTRL_DEBUG(mac, "recv assreq, direct connect"); + } + }else{ + //STACTRL_DEBUG(mac, "prefer-band recv assreq, and not block prefer band. Connect..."); + //STACTRL_DEBUG(mac, "block del"); + //record STA is kickoff and on the other band's prefer table + if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac)==0){ + stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); + STACTRL_DEBUG(mac, "2G->5G"); + } + //STA not in either block list of 5G or block list of 2G + else{ + val16 = stactrl_check_request_on_preferband(priv, mac, WIFI_ASSOCREQ, rssi); + if(val16){ + STACTRL_DEBUG(mac, "recv assreq, block prefer"); + return 1; + }else{ + STACTRL_DEBUG(mac, "recv assreq, direct connect"); + } + } + } + + SMP_UNLOCK_STACONTROL_LIST(flags); + RESTORE_INT(flags); + }else { + /* check if block prefer band */ + panic_printk("[%s %d]call stactrl_block_delete\n", __FUNCTION__,__LINE__); + if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac)==0){ + STACTRL_DEBUG(mac, "5G->2G, recv assreq, block prefer, connect non-prefer"); + stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); + } + /* block non-prefer band or non block 2G/5G, prefer band first */ + else{ + STACTRL_DEBUG(mac, "check request when Asso()"); + val16 = stactrl_check_request_on_nonpreferband(priv, mac, WIFI_ASSOCREQ, rssi); + if(val16 == 1){ /*reject*/ + STACTRL_DEBUG(mac, "recv assreq, block 2G"); + return 1; + } + if(rssi < STACTRL_NONPREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE){ + *candidate = 1; + STACTRL_DEBUG(mac, "recv assreq, candidate"); + } + } + } + + return 0; + } + else{ + if(priv->stactrl.stactrl_prefer) { + //panic_printk("%s: call stactrl_block_delete\n",__FUNCTION__); + if(stactrl_block_delete(priv->stactrl.stactrl_priv_sc, mac) == 0){ + //20170103 + //record STA is kickoff and on the other band's prefer table + stactrl_record_kickoff(priv->stactrl.stactrl_priv_sc, mac); + } + val16 = stactrl_check_request(priv, mac, WIFI_ASSOCREQ, rssi); + if(val16 == 1) /*reject*/ + return 1; + }else { + val16 = stactrl_check_request(priv, mac, WIFI_ASSOCREQ, rssi); + if(val16 == 1) /*reject*/ + return 1; + if(rssi < STACTRL_NONPREFERBAND_RSSI - STACTRL_PREFERBAND_RSSI_TOLERANCE) + *candidate = 1; + } + return 0; + } + +} + +unsigned char stactrl_hidden_ap(struct rtl8192cd_priv *priv) +{ + if(!priv->stactrl.stactrl_enable_hiddenAP || priv->stactrl.stactrl_prefer) + return 1; + printk("[%s]\n", __FUNCTION__); + + if(!priv->pmib->dot11OperationEntry.hiddenAP) + priv->pmib->dot11OperationEntry.hiddenAP = 1; + + if(priv->stactrl.stactrl_hiddenAP_aging != STACTRL_HIDDENAP_EXPIRE) + priv->stactrl.stactrl_hiddenAP_aging = STACTRL_HIDDENAP_EXPIRE; + return 1; +} + +#endif +#endif /* STA_CONTROL */ diff --git a/package/kernel/rtl8192cd/8192cd_tx.c b/package/kernel/rtl8192cd/8192cd_tx.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_util.c b/package/kernel/rtl8192cd/8192cd_util.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192cd_util.h b/package/kernel/rtl8192cd/8192cd_util.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8192d_hw.c b/package/kernel/rtl8192cd/8192d_hw.c index 0ab9cd7dee6..aab205af4ce 100644 --- a/package/kernel/rtl8192cd/8192d_hw.c +++ b/package/kernel/rtl8192cd/8192d_hw.c @@ -1,880 +1,880 @@ - -#define _8192D_HW_C_ - -#ifdef __KERNEL__ -#include -#include -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" -#include "./8192cd.h" -#include "./8192cd_hw.h" -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" - - -#ifdef CONFIG_RTL_92D_SUPPORT - -#if defined(CONFIG_RTL_819X) && defined(USE_RLX_BSP) -#if defined(CONFIG_OPENWRT_SDK) && !defined(CONFIG_ARCH_CPU_RLX) -#include -#else -#include -#endif //CONFIG_OPENWRT_SDK -#endif - -#ifndef USE_OUT_SRC -#define IQK_ADDA_REG_NUM 16 -#endif - - -#ifdef CONFIG_RTL_92D_DMDP - -extern u32 if_priv[]; - -__inline__ unsigned char DMDP_RTL_R8(unsigned int phy, unsigned int reg) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return -1; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - return RTL_R8(reg); -} - -__inline__ void DMDP_RTL_W8(unsigned int phy, unsigned int reg, unsigned char val8) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s(%x,%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val8); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - RTL_W8(reg, val8); -} - -__inline__ unsigned short DMDP_RTL_R16(unsigned int phy, unsigned int reg) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return -1; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - return RTL_R16(reg); -} - -__inline__ void DMDP_RTL_W16(unsigned int phy, unsigned int reg, unsigned short val16) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - RTL_W16(reg, val16); -} - -__inline__ unsigned int DMDP_RTL_R32(unsigned int phy, unsigned int reg) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return -1; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - return RTL_R32(reg); -} - -__inline__ void DMDP_RTL_W32(unsigned int phy, unsigned int reg, unsigned int val32) -{ - struct rtl8192cd_priv *priv; - //printk("++++++++++++++++++++++++++%s(%x, %x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val32); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return; - } - priv = (struct rtl8192cd_priv *)if_priv[phy]; - RTL_W32(reg, val32); -} - -unsigned int DMDP_PHY_QueryBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask) -{ - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return -1; - } - return PHY_QueryBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask); -} - -void DMDP_PHY_SetBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask, unsigned int Data) -{ - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return; - } - PHY_SetBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask, Data); -} - -unsigned int DMDP_PHY_QueryRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, - unsigned int RegAddr, unsigned int BitMask, unsigned int dbg_avoid) -{ - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return -1; - } - return PHY_QueryRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, dbg_avoid); -} - -void DMDP_PHY_SetRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, unsigned int RegAddr, - unsigned int BitMask, unsigned int Data) -{ - //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); - if (phy >= NUM_WLAN_IFACE || phy < 0) { - printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); - return; - } - PHY_SetRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, Data); -} - -#endif //CONFIG_RTL_92D_DMDP - -void SetSYN_para(struct rtl8192cd_priv *priv, unsigned char channel) -{ - unsigned int eRFPath, tmp=0; - unsigned int idx=-1, i; - unsigned int SYN_PARA[8][8] = { - {0xe43be, 0xfc638, 0x77c0a, 0xde471, 0xd7110, 0x8cb04, 0x00000, 0x00000}, // CH36-140 20MHz - {0xe43be, 0xfc078, 0xf7c1a, 0xe0c71, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH36-140 40MHz - {0xe43bf, 0xff038, 0xf7c0a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH149, 155, 161 - {0xe43bf, 0xff079, 0xf7c1a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH151, 153, 163, 165 - {0xe43bf, 0xff038, 0xf7c1a, 0xde471, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH157, 159 -#ifdef SW_LCK_92D - {0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH1,2,4,9,10,11,12 - {0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH3,13,14 - {0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x6128b, 0x0fc41} // CH5-8 -#else - {0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH1,2,4,9,10,11,12 - {0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH3,13,14 - {0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x4128b, 0x0fc41} // CH5-8 -#endif - }; - - - if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) - eRFPath = RF92CD_PATH_B; - else - eRFPath = RF92CD_PATH_A; - - if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ - if (channel >=36 && channel <=140){ - if (!priv->pshare->CurrentChannelBW) - idx = 0; - else - idx = 1; - } else if (channel == 149 || channel == 155 || channel == 161) - idx = 2; - else if (channel==151 || channel==153 || channel==163 || channel==165) - idx = 3; - else if (channel==157 || channel==159) - idx = 4; - } else { - if (channel==1 || channel==2 || channel==4 || channel==9 || channel==10 || channel==11 || channel==12) - idx = 5; - else if (channel==3 || channel==13 || channel==14) - idx = 6; - else if (channel>=5 && channel<=8) - idx = 7; - } - - if (idx==-1){ - DEBUG_ERR("No suitable channel (%d) for setting synthersizer parameter!\n", channel); - return; - } - - for (i=0;i<8;i++){ -#ifdef CONFIG_RTL_92D_DMDP - if (i==0 && (idx>=0 && idx <=4) && - (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) - tmp = 0xe439d; - else -#endif - tmp = SYN_PARA[idx][i]; - - if (tmp!=0) { - -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && eRFPath == RF92CD_PATH_B) { - DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, (0x25+i), bMask20Bits, tmp); - //DEBUG_INFO("DMDP_PHY_SetRFReg(1, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp); - } else -#endif - { - PHY_SetRFReg(priv, eRFPath, (0x25+i), bMask20Bits, tmp); - //DEBUG_INFO("PHY_SetRFReg(priv, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp); - } - if (i==3) - priv->pshare->RegRF28[eRFPath] = tmp; - } - } -} - -unsigned int IMR_SET_N[3][11] = { - {0x00ff0, 0x4400f, 0x00ff0, 0x00000, 0x00000, 0x00000, 0x00000, 0x00000, 0x64888, 0xe266c, 0x00090}, //G-mode - {0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 0x00000, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090}, //36-64 - {0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 0x00000, 0x880b0, 0x00000, 0x64b82, 0xe466c, 0x00090}, // 100-165 -}; - -void SetIMR_n(struct rtl8192cd_priv *priv, unsigned char channel) -{ - unsigned int eRFPath, curMaxRFPath; - int imr_idx = -1; - unsigned char temp_800; - -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else -#endif - curMaxRFPath = RF92CD_PATH_MAX; - - if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) - imr_idx = 0; - else { - if (channel>=36 && channel <=64) - imr_idx = 1; - else - imr_idx = 2; - } - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf); - temp_800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000); - PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0); - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - int i; - - PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x70000); - //DEBUG_INFO("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1)); - //delay_us(5); - - for (i=0;i<11;i++) { - PHY_SetRFReg(priv, eRFPath, (0x2f+i), bMask20Bits, IMR_SET_N[imr_idx][i]); - //DEBUG_INFO("IMR [0x%x] %05x\n", (0x2f+i), PHY_QueryRFReg(priv, eRFPath, (0x2f+i), bMask20Bits,1)); - //delay_us(5); - } - - if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) - PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32fff); - else - PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32c9a); - - //DEBUG_INFO("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1)); - //delay_us(5); - } - - PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_800); - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0); -} - - -/* - * Follow WS-20101228-Willis-xxxx dynamic parameter-R00 - */ -void Update92DRFbyChannel(struct rtl8192cd_priv *priv, unsigned char channel) -{ -#ifdef RTL8192D_INT_PA - u8 eRFPath = 0, curMaxRFPath; - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else - curMaxRFPath = RF92CD_PATH_MAX; - - if (priv->pshare->rf_ft_var.use_intpa92d){ - for(eRFPath = RF92CD_PATH_A; eRFPath pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ - if (channel>=36 && channel<=64){ - PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01a00); - PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0x40443); - PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00eb5); - //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); - PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x89bec); - //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); - PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12); - delay_us(10); - PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12); - PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12); - }else if (channel>=100 && channel<=140){ - PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800); - PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443); - PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730); - //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); - PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee); - //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); - PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a52); - delay_us(10); - PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a52); - PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a52); - }else if (channel>=149 && channel<=165){ - PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800); - PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443); - PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730); - //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); - PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee); - //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); - PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12); - delay_us(10); - PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12); - PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12); - } - }else{ - PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x1c000); - PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x18c63); - delay_us(10); - PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x18c63); - PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x18c67); - } - } - } -#endif - - if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ - //update fc_area - if (priv->pmib->dot11RFEntry.dot11channel<149) - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1); - else - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2); - // VCO_BF_LDO= 1.12V->1.27V for 40M spur issue - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x2A, BIT(13)|BIT(12), 2); - // RX Ch36 40M spurs - if (channel==36){ - priv->pshare->RegRF28[RF92CD_PATH_A] &= (~BIT(6)); - priv->pshare->RegRF28[RF92CD_PATH_A] |= BIT(5); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); - //PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(6)|BIT(5), 0); - } - } else { - //update fc_area - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0); - } - -} - -int Load_92D_Firmware(struct rtl8192cd_priv *priv) -{ - int fw_len, wait_cnt=0; - unsigned int CurPtr=0; - unsigned int WriteAddr; - unsigned int Temp; - unsigned char *ptmp; -#ifndef SMP_SYNC - unsigned long flags = 0; -#endif - -#ifdef CONFIG_RTL8672 - printk("val=%x\n",RTL_R8(0x80)); -#endif - -#ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) - return TRUE; -#endif - - printk("===> %s\n", __FUNCTION__); - - SAVE_INT_AND_CLI(flags); - - printk("Firmware check %x(%x)\n", RTL_R32(MCUFWDL), (RTL_R8(MCUFWDL) & MCUFWDL_RDY)); - if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ - printk("<=== Firmware Downloaded\n"); - goto check_fwdl_rdy; - } - - wait_cnt=0; - while(RTL_R8(RF_CTRL) & FW_DL_INPROC){ - wait_cnt++; - delay_ms(50); - } - -#ifdef CONFIG_RTL_92D_DMDP - if (wait_cnt==0) { - if (priv->pshare->wlandev_idx == 0) - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); - else { - if (RTL_R8(RSV_MAC0_CTRL) & MAC0_EN) - goto check_fwdl_rdy; - else - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); - } - } else { - if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ - printk("<=== Firmware Downloaded\n"); - RESTORE_INT(flags); - return TRUE; - }else{ - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); - } - } -#else - if (wait_cnt==0) { - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); - } else { - if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ - printk("<=== Firmware Downloaded\n"); - RESTORE_INT(flags); - return TRUE; - }else{ - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); - } - } - -#endif - - if ((priv->pshare->fw_signature & 0xfff0 ) == 0x92D0) - ptmp = data_rtl8192dfw_n_start + RT_8192CD_FIRMWARE_HDR_SIZE; - else - ptmp = data_rtl8192dfw_n_start; - - fw_len = (int)(data_rtl8192dfw_n_end - ptmp); - printk("[%s][rtl8192dfw_n]\n",__FUNCTION__); - - // Disable SIC - RTL_W16(GPIO_MUXCFG, (RTL_R16(GPIO_MUXCFG) & 0xff) | HTP_EN); - delay_ms(1); - - // Enable MCU - RTL_W16(SYS_FUNC_EN, (RTL_R16(SYS_FUNC_EN) & 0x0ff) | FEN_MREGEN - | FEN_HWPDN | FEN_DIO_RF | FEN_ELDR | FEN_DCORE |FEN_CPUEN | FEN_PCIED); - delay_ms(1); - -#ifdef CONFIG_RTL8672 - RTL_W8(APS_FSMCO, RTL_R8(APS_FSMCO) | PFM_ALDN); - delay_ms(1); //czyao -#endif - - // Load SRAM - WriteAddr = 0x1000; - RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) | MCUFWDL_EN); - delay_ms(1); - - RTL_W32(MCUFWDL, RTL_R32(MCUFWDL) & 0xfff0ffff); - - delay_ms(1); - - while (CurPtr < fw_len) { - if ((CurPtr+4) > fw_len) { - // Reach the end of file. - while (CurPtr < fw_len) { - Temp = *(ptmp + CurPtr); - RTL_W8(WriteAddr, (unsigned char)Temp); - WriteAddr++; - CurPtr++; - } - } else { - // Write FW content to memory. - Temp = *((unsigned int *)(ptmp + CurPtr)); - Temp = cpu_to_le32(Temp); - RTL_W32(WriteAddr, Temp); - WriteAddr += 4; - - if(WriteAddr == 0x2000) { - unsigned char tmp = RTL_R8(MCUFWDL+2); - tmp += 1; - WriteAddr = 0x1000; - RTL_W8(MCUFWDL+2, tmp) ; - delay_ms(10); -// printk("\n[CurPtr=%x, 0x82=%x]\n", CurPtr, RTL_R8(0x82)); - } - CurPtr += 4; - } - } - - watchdog_kick(); - - RTL_W8(TCR+3, 0x7f); - RTL_W8(MCUFWDL, (RTL_R8(MCUFWDL) & 0xfe) | MCUFWDL_RDY); - delay_ms(1); - //RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) | BIT(6)); - RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) & (~FW_DL_INPROC)); - delay_ms(1); - -check_fwdl_rdy: - - printk("<=== %s\n", __FUNCTION__); - // check if firmware is ready - wait_cnt = 0; -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pshare->wlandev_idx == 0) -#endif - { - while (!(RTL_R8(RSV_MAC0_FWCTRL) & MAC0_WINTINI_RDY)) { - if (++wait_cnt > 10) { - RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY)); - RESTORE_INT(flags); - DEBUG_ERR("8192d mac0 firmware not ready\n"); - return FALSE; - } - delay_ms(2*wait_cnt); - } - } -#ifdef CONFIG_RTL_92D_DMDP - else { - while (!(RTL_R8(RSV_MAC1_FWCTRL) & MAC1_WINTINI_RDY)) { - if (++wait_cnt > 10) { - RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY)); - RESTORE_INT(flags); - DEBUG_ERR("8192d mac1 firmware not ready\n"); - return FALSE; - } - delay_ms(2*wait_cnt); - - } - } -#endif - RESTORE_INT(flags); -#ifdef CONFIG_RTL8672 - printk("val=%x\n",RTL_R8(MCUFWDL)); -#endif - return TRUE; -} - - -/* - * 92DE Operation Mode - */ -void UpdateBBRFVal8192DE(struct rtl8192cd_priv *priv) -{ - u8 eRFPath = 0, curMaxRFPath; - //u32 u4RegValue=0; - - //Update BB - if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { - /* - * 5G - */ - //r_select_5G for path_A/B - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x1); - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0x1); - //rssi_table_select:index 0 for 2.4G.1~3 for 5G - PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x01); - //5G PA power on - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6); - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4); - - //TRSW.TRSWB and PAPE2G mode table - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){ - // TRSW_2, TRSWB_2 - PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 0); - // PAPE2G_2 - PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(7))>>7); - PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6); - } - // TRSW_1, TRSWB_1 - PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 0); - // PAPE2G_1 - PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(5))>>5); - PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4); -#ifdef RTL8192D_INT_PA - if (!priv->pshare->rf_ft_var.use_intpa92d) -#endif - { - //5G PA power on - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x1); - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x1); - } - // 5G LNA on - PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0x0); - //fc_area - if (priv->pmib->dot11RFEntry.dot11channel<149) - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1); - else - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2); - //cck_disable - PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x0); - //TX BB gain shift -#ifdef RTL8192D_INT_PA - if (priv->pshare->rf_ft_var.use_intpa92d){ - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x2d4000b5); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x2d4000b5); - } else -#endif - { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x20000080); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x20000080); - } - // Reset IQC - PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0); - //BB/DP IQC - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x010170b8); - - } else { - /* - * 2.4G - */ - // r_select_5G for path_A/B - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x0); - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0); - //rssi_table_select:index 0 for 2.4G.1~3 for 5G - PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x00); - //5G PA power on - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x0); - PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x0); - - //TRSW.TRSWB and PAPE2G mode table - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){ - // TRSW_2 - PHY_SetBBReg(priv, 0x870, BIT(21), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(7))>>7); - PHY_SetBBReg(priv, 0x864, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(6))>>6); - // TRSWB_2 - PHY_SetBBReg(priv, 0x870, BIT(22), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(5))>>5); - PHY_SetBBReg(priv, 0x864, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(4))>>4); - // PAPE2G_2 - PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(3))>>3); - PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(2))>>2); - } - // TRSW_1 - PHY_SetBBReg(priv, 0x870, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(3))>>3); - PHY_SetBBReg(priv, 0x860, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(2))>>2); - // TRSWB_1 - PHY_SetBBReg(priv, 0x870, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(1))>>1); - PHY_SetBBReg(priv, 0x860, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(0))>>0); - // PAPE2G_1 - PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(1))>>1); - PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(0))>>0); - - // 5G LNA on - PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0xa); - //fc_area - PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0x00); - //cck_enable - PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1); - //TX BB gain shift - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x40000100); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x40000100); - // Reset IQC - PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0); - //BB/DP IQC - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017038); - if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017038); - } - - //Update RF - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else - curMaxRFPath = RF92CD_PATH_MAX; - - for(eRFPath = RF92CD_PATH_A; eRFPath pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { - /* - * 5G - */ - priv->pshare->RegRF18[eRFPath] &= 0xffffff00; - priv->pshare->RegRF18[eRFPath] |= (BIT(16)|BIT(8)|0x24); //set channel 36 - PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]); - delay_ms(1); - // LDO_DIV - priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],BIT(7)|BIT(6),1,6); - //PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x01); - PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); - - delay_ms(30); - } else { - /* - * 2.4G - */ - priv->pshare->RegRF18[eRFPath] &= ~(BIT(16)|BIT(8)|0xFF); - priv->pshare->RegRF18[eRFPath] |= 1; //set channel 1. - PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]); - delay_ms(1); - // LDO_DIV - priv->pshare->RegRF28[eRFPath] &= (~(BIT(7)|BIT(6))); - //PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x00); - PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); - - delay_ms(30); - } - } - -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) { - //Use antenna 0 & 1 - PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x11); - PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x1); - - //disable ad/da clock1 - if (!(DMDP_RTL_R8(0,SYS_FUNC_EN)&(FEN_BB_GLB_RST|FEN_BBRSTB))){ - DMDP_RTL_W8(0, SYS_FUNC_EN, (DMDP_RTL_R8(0,SYS_FUNC_EN)|FEN_BB_GLB_RST|FEN_BBRSTB)); - } - DMDP_PHY_SetBBReg(0, rFPGA0_AdDaClockEn, BIT(13)|BIT(12), 3); - } else -#endif - { - //Use antenna 0 & 1 - PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x33); - PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x3); - - //disable ad/da clock1 - PHY_SetBBReg(priv, rFPGA0_AdDaClockEn, BIT(13) | BIT(12), 0); - } -} - - -#if 0 //def CLIENT_MODE -void clnt_save_IQK_res(struct rtl8192cd_priv *priv) -{ - priv->site_survey->bk_iqc[0] = PHY_QueryBBReg(priv,0xc80, bMaskDWord); - priv->site_survey->bk_iqc[1] = PHY_QueryBBReg(priv,0xc94, bMaskByte3); - priv->site_survey->bk_iqc[2] = PHY_QueryBBReg(priv,0xc4c, bMaskByte3); - priv->site_survey->bk_iqc[3] = PHY_QueryBBReg(priv,0xc88, bMaskDWord); - priv->site_survey->bk_iqc[4] = PHY_QueryBBReg(priv,0xc9c, bMaskByte3); - priv->site_survey->bk_iqc[5] = PHY_QueryBBReg(priv,0xc14, bMaskDWord); - priv->site_survey->bk_iqc[6] = PHY_QueryBBReg(priv,0xca0, bMaskByte3); - priv->site_survey->bk_iqc[7] = PHY_QueryBBReg(priv,0xc1c, bMaskDWord); - priv->site_survey->bk_iqc[8] = PHY_QueryBBReg(priv,0xc78, bMaskByte1); - priv->site_survey->bk_iqc[9] = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 1); - priv->site_survey->bk_iqc[10] = PHY_QueryRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 1); -} - - -void clnt_load_IQK_res(struct rtl8192cd_priv *priv) -{ - PHY_SetBBReg(priv,0xc80, bMaskDWord, priv->site_survey->bk_iqc[0]); - PHY_SetBBReg(priv,0xc94, bMaskByte3, priv->site_survey->bk_iqc[1]); - PHY_SetBBReg(priv,0xc4c, bMaskByte3, priv->site_survey->bk_iqc[2]); - PHY_SetBBReg(priv,0xc88, bMaskDWord, priv->site_survey->bk_iqc[3]); - PHY_SetBBReg(priv,0xc9c, bMaskByte3, priv->site_survey->bk_iqc[4]); - PHY_SetBBReg(priv,0xc14, bMaskDWord, priv->site_survey->bk_iqc[5]); - PHY_SetBBReg(priv,0xca0, bMaskByte3, priv->site_survey->bk_iqc[6]); - PHY_SetBBReg(priv,0xc1c, bMaskDWord, priv->site_survey->bk_iqc[7]); - PHY_SetBBReg(priv,0xc78, bMaskByte1, priv->site_survey->bk_iqc[8]); - PHY_SetRFReg(priv,RF92CD_PATH_A, 0x08, bMask20Bits, priv->site_survey->bk_iqc[9]); - PHY_SetRFReg(priv,RF92CD_PATH_B, 0x08, bMask20Bits, priv->site_survey->bk_iqc[10]); -} - -#endif - -#ifdef CONFIG_RTL_92D_DMDP -#if 0 //def CLIENT_MODE - -void clnt_92D_2T_AGSwitch(struct rtl8192cd_priv * priv, int target) -{ - unsigned int flags, i; - int rtStatus = 0; - unsigned char temp_0522, temp_0550, temp_0551, temp_0800; - unsigned char reg; - - SAVE_INT_AND_CLI(flags); - - /* - * Save MAC default value - */ - temp_0522 = RTL_R8(0x522); - temp_0550 = RTL_R8(0x550); - temp_0551 = RTL_R8(0x551); - - /* - * MAC register setting - */ - RTL_W8(0x522, 0x3f); - RTL_W8(0x550, temp_0550& (~BIT(3))); - RTL_W8(0x551, temp_0551& (~BIT(3))); - - // stop BB - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf); - temp_0800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000); - PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0); - - // 5G_PAPE Select & external PA power on - PHY_SetBBReg(priv, 0x878, BIT(0), 0); - PHY_SetBBReg(priv, 0x878, BIT(16), 0); - PHY_SetBBReg(priv, 0x878, BIT(15), 0); - PHY_SetBBReg(priv, 0x878, BIT(31), 0); - // RSSI Table Select - PHY_SetBBReg(priv, 0xc78, BIT(7)|BIT(6), 0); - // fc_area - PHY_SetBBReg(priv, 0xd2c, BIT(14)|BIT(13), 0); - // cck_enable - PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1); - // LDO_DIV - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 0); - PHY_SetRFReg(priv, RF92CD_PATH_B, 0x28, BIT(7)|BIT(6), 0); - // MOD_AG // Set channel number - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(16), 0); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(8), 0); - PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(16), 0); - PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(8), 0); - // CLOAD for path_A - PHY_SetRFReg(priv, RF92CD_PATH_A, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7); - PHY_SetRFReg(priv, RF92CD_PATH_B, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7); - - // IMR - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x70000); - for (i=0;i<11;i++) { - PHY_SetRFReg(priv, RF92CD_PATH_A, (0x2f+i), bMask20Bits, IMR_SET_N[0][i]); - } - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x32fff); - - // Enable BB - PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_0800); - // IQK - PHY_SetBBReg(priv, 0xc80, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xc94, bMaskByte3, 0); - PHY_SetBBReg(priv, 0xc4c, bMaskByte3, 0); - PHY_SetBBReg(priv, 0xc88, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xc9c, bMaskByte3, 0); - PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xca0, bMaskByte3, 0); - PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xc78, bMaskByte1, 0); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000); - PHY_SetRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 0x84000); - - //Set related registers for BW config - - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0); - - /* - * Reload MAC default value - */ - RTL_W8(0x550, temp_0550); - RTL_W8(0x551, temp_0551); - RTL_W8(0x522, temp_0522); - - RESTORE_INT(flags); -} - -#endif - -#endif //CONFIG_RTL_92D_DMDP - -#endif // CONFIG_RTL_92D_SUPPORT - - - + +#define _8192D_HW_C_ + +#ifdef __KERNEL__ +#include +#include +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#include "./8192cd_hw.h" +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" + + +#ifdef CONFIG_RTL_92D_SUPPORT + +#if defined(CONFIG_RTL_819X) && defined(USE_RLX_BSP) +#if defined(CONFIG_OPENWRT_SDK) && !defined(CONFIG_ARCH_CPU_RLX) +#include +#else +#include +#endif //CONFIG_OPENWRT_SDK +#endif + +#ifndef USE_OUT_SRC +#define IQK_ADDA_REG_NUM 16 +#endif + + +#ifdef CONFIG_RTL_92D_DMDP + +extern u32 if_priv[]; + +__inline__ unsigned char DMDP_RTL_R8(unsigned int phy, unsigned int reg) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return -1; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + return RTL_R8(reg); +} + +__inline__ void DMDP_RTL_W8(unsigned int phy, unsigned int reg, unsigned char val8) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s(%x,%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val8); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + RTL_W8(reg, val8); +} + +__inline__ unsigned short DMDP_RTL_R16(unsigned int phy, unsigned int reg) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return -1; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + return RTL_R16(reg); +} + +__inline__ void DMDP_RTL_W16(unsigned int phy, unsigned int reg, unsigned short val16) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + RTL_W16(reg, val16); +} + +__inline__ unsigned int DMDP_RTL_R32(unsigned int phy, unsigned int reg) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return -1; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + return RTL_R32(reg); +} + +__inline__ void DMDP_RTL_W32(unsigned int phy, unsigned int reg, unsigned int val32) +{ + struct rtl8192cd_priv *priv; + //printk("++++++++++++++++++++++++++%s(%x, %x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val32); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return; + } + priv = (struct rtl8192cd_priv *)if_priv[phy]; + RTL_W32(reg, val32); +} + +unsigned int DMDP_PHY_QueryBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask) +{ + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return -1; + } + return PHY_QueryBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask); +} + +void DMDP_PHY_SetBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask, unsigned int Data) +{ + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return; + } + PHY_SetBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask, Data); +} + +unsigned int DMDP_PHY_QueryRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, + unsigned int RegAddr, unsigned int BitMask, unsigned int dbg_avoid) +{ + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return -1; + } + return PHY_QueryRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, dbg_avoid); +} + +void DMDP_PHY_SetRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, unsigned int RegAddr, + unsigned int BitMask, unsigned int Data) +{ + //printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__); + if (phy >= NUM_WLAN_IFACE || phy < 0) { + printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); + return; + } + PHY_SetRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, Data); +} + +#endif //CONFIG_RTL_92D_DMDP + +void SetSYN_para(struct rtl8192cd_priv *priv, unsigned char channel) +{ + unsigned int eRFPath, tmp=0; + unsigned int idx=-1, i; + unsigned int SYN_PARA[8][8] = { + {0xe43be, 0xfc638, 0x77c0a, 0xde471, 0xd7110, 0x8cb04, 0x00000, 0x00000}, // CH36-140 20MHz + {0xe43be, 0xfc078, 0xf7c1a, 0xe0c71, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH36-140 40MHz + {0xe43bf, 0xff038, 0xf7c0a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH149, 155, 161 + {0xe43bf, 0xff079, 0xf7c1a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH151, 153, 163, 165 + {0xe43bf, 0xff038, 0xf7c1a, 0xde471, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH157, 159 +#ifdef SW_LCK_92D + {0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH1,2,4,9,10,11,12 + {0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH3,13,14 + {0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x6128b, 0x0fc41} // CH5-8 +#else + {0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH1,2,4,9,10,11,12 + {0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH3,13,14 + {0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x4128b, 0x0fc41} // CH5-8 +#endif + }; + + + if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) + eRFPath = RF92CD_PATH_B; + else + eRFPath = RF92CD_PATH_A; + + if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ + if (channel >=36 && channel <=140){ + if (!priv->pshare->CurrentChannelBW) + idx = 0; + else + idx = 1; + } else if (channel == 149 || channel == 155 || channel == 161) + idx = 2; + else if (channel==151 || channel==153 || channel==163 || channel==165) + idx = 3; + else if (channel==157 || channel==159) + idx = 4; + } else { + if (channel==1 || channel==2 || channel==4 || channel==9 || channel==10 || channel==11 || channel==12) + idx = 5; + else if (channel==3 || channel==13 || channel==14) + idx = 6; + else if (channel>=5 && channel<=8) + idx = 7; + } + + if (idx==-1){ + DEBUG_ERR("No suitable channel (%d) for setting synthersizer parameter!\n", channel); + return; + } + + for (i=0;i<8;i++){ +#ifdef CONFIG_RTL_92D_DMDP + if (i==0 && (idx>=0 && idx <=4) && + (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) + tmp = 0xe439d; + else +#endif + tmp = SYN_PARA[idx][i]; + + if (tmp!=0) { + +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && eRFPath == RF92CD_PATH_B) { + DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, (0x25+i), bMask20Bits, tmp); + //DEBUG_INFO("DMDP_PHY_SetRFReg(1, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp); + } else +#endif + { + PHY_SetRFReg(priv, eRFPath, (0x25+i), bMask20Bits, tmp); + //DEBUG_INFO("PHY_SetRFReg(priv, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp); + } + if (i==3) + priv->pshare->RegRF28[eRFPath] = tmp; + } + } +} + +unsigned int IMR_SET_N[3][11] = { + {0x00ff0, 0x4400f, 0x00ff0, 0x00000, 0x00000, 0x00000, 0x00000, 0x00000, 0x64888, 0xe266c, 0x00090}, //G-mode + {0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 0x00000, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090}, //36-64 + {0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 0x00000, 0x880b0, 0x00000, 0x64b82, 0xe466c, 0x00090}, // 100-165 +}; + +void SetIMR_n(struct rtl8192cd_priv *priv, unsigned char channel) +{ + unsigned int eRFPath, curMaxRFPath; + int imr_idx = -1; + unsigned char temp_800; + +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else +#endif + curMaxRFPath = RF92CD_PATH_MAX; + + if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) + imr_idx = 0; + else { + if (channel>=36 && channel <=64) + imr_idx = 1; + else + imr_idx = 2; + } + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf); + temp_800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000); + PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0); + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + int i; + + PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x70000); + //DEBUG_INFO("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1)); + //delay_us(5); + + for (i=0;i<11;i++) { + PHY_SetRFReg(priv, eRFPath, (0x2f+i), bMask20Bits, IMR_SET_N[imr_idx][i]); + //DEBUG_INFO("IMR [0x%x] %05x\n", (0x2f+i), PHY_QueryRFReg(priv, eRFPath, (0x2f+i), bMask20Bits,1)); + //delay_us(5); + } + + if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G) + PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32fff); + else + PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32c9a); + + //DEBUG_INFO("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1)); + //delay_us(5); + } + + PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_800); + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0); +} + + +/* + * Follow WS-20101228-Willis-xxxx dynamic parameter-R00 + */ +void Update92DRFbyChannel(struct rtl8192cd_priv *priv, unsigned char channel) +{ +#ifdef RTL8192D_INT_PA + u8 eRFPath = 0, curMaxRFPath; + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else + curMaxRFPath = RF92CD_PATH_MAX; + + if (priv->pshare->rf_ft_var.use_intpa92d){ + for(eRFPath = RF92CD_PATH_A; eRFPath pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ + if (channel>=36 && channel<=64){ + PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01a00); + PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0x40443); + PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00eb5); + //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); + PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x89bec); + //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); + PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12); + delay_us(10); + PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12); + PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12); + }else if (channel>=100 && channel<=140){ + PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800); + PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443); + PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730); + //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); + PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee); + //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); + PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a52); + delay_us(10); + PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a52); + PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a52); + }else if (channel>=149 && channel<=165){ + PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800); + PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443); + PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730); + //PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f); + PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee); + //PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded); + PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12); + delay_us(10); + PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12); + PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12); + } + }else{ + PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x1c000); + PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x18c63); + delay_us(10); + PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x18c63); + PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x18c67); + } + } + } +#endif + + if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){ + //update fc_area + if (priv->pmib->dot11RFEntry.dot11channel<149) + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1); + else + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2); + // VCO_BF_LDO= 1.12V->1.27V for 40M spur issue + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x2A, BIT(13)|BIT(12), 2); + // RX Ch36 40M spurs + if (channel==36){ + priv->pshare->RegRF28[RF92CD_PATH_A] &= (~BIT(6)); + priv->pshare->RegRF28[RF92CD_PATH_A] |= BIT(5); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); + //PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(6)|BIT(5), 0); + } + } else { + //update fc_area + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0); + } + +} + +int Load_92D_Firmware(struct rtl8192cd_priv *priv) +{ + int fw_len, wait_cnt=0; + unsigned int CurPtr=0; + unsigned int WriteAddr; + unsigned int Temp; + unsigned char *ptmp; +#ifndef SMP_SYNC + unsigned long flags = 0; +#endif + +#ifdef CONFIG_RTL8672 + printk("val=%x\n",RTL_R8(0x80)); +#endif + +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) + return TRUE; +#endif + + printk("===> %s\n", __FUNCTION__); + + SAVE_INT_AND_CLI(flags); + + printk("Firmware check %x(%x)\n", RTL_R32(MCUFWDL), (RTL_R8(MCUFWDL) & MCUFWDL_RDY)); + if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ + printk("<=== Firmware Downloaded\n"); + goto check_fwdl_rdy; + } + + wait_cnt=0; + while(RTL_R8(RF_CTRL) & FW_DL_INPROC){ + wait_cnt++; + delay_ms(50); + } + +#ifdef CONFIG_RTL_92D_DMDP + if (wait_cnt==0) { + if (priv->pshare->wlandev_idx == 0) + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); + else { + if (RTL_R8(RSV_MAC0_CTRL) & MAC0_EN) + goto check_fwdl_rdy; + else + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); + } + } else { + if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ + printk("<=== Firmware Downloaded\n"); + RESTORE_INT(flags); + return TRUE; + }else{ + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); + } + } +#else + if (wait_cnt==0) { + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); + } else { + if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){ + printk("<=== Firmware Downloaded\n"); + RESTORE_INT(flags); + return TRUE; + }else{ + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC); + } + } + +#endif + + if ((priv->pshare->fw_signature & 0xfff0 ) == 0x92D0) + ptmp = data_rtl8192dfw_n_start + RT_8192CD_FIRMWARE_HDR_SIZE; + else + ptmp = data_rtl8192dfw_n_start; + + fw_len = (int)(data_rtl8192dfw_n_end - ptmp); + printk("[%s][rtl8192dfw_n]\n",__FUNCTION__); + + // Disable SIC + RTL_W16(GPIO_MUXCFG, (RTL_R16(GPIO_MUXCFG) & 0xff) | HTP_EN); + delay_ms(1); + + // Enable MCU + RTL_W16(SYS_FUNC_EN, (RTL_R16(SYS_FUNC_EN) & 0x0ff) | FEN_MREGEN + | FEN_HWPDN | FEN_DIO_RF | FEN_ELDR | FEN_DCORE |FEN_CPUEN | FEN_PCIED); + delay_ms(1); + +#ifdef CONFIG_RTL8672 + RTL_W8(APS_FSMCO, RTL_R8(APS_FSMCO) | PFM_ALDN); + delay_ms(1); //czyao +#endif + + // Load SRAM + WriteAddr = 0x1000; + RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) | MCUFWDL_EN); + delay_ms(1); + + RTL_W32(MCUFWDL, RTL_R32(MCUFWDL) & 0xfff0ffff); + + delay_ms(1); + + while (CurPtr < fw_len) { + if ((CurPtr+4) > fw_len) { + // Reach the end of file. + while (CurPtr < fw_len) { + Temp = *(ptmp + CurPtr); + RTL_W8(WriteAddr, (unsigned char)Temp); + WriteAddr++; + CurPtr++; + } + } else { + // Write FW content to memory. + Temp = *((unsigned int *)(ptmp + CurPtr)); + Temp = cpu_to_le32(Temp); + RTL_W32(WriteAddr, Temp); + WriteAddr += 4; + + if(WriteAddr == 0x2000) { + unsigned char tmp = RTL_R8(MCUFWDL+2); + tmp += 1; + WriteAddr = 0x1000; + RTL_W8(MCUFWDL+2, tmp) ; + delay_ms(10); +// printk("\n[CurPtr=%x, 0x82=%x]\n", CurPtr, RTL_R8(0x82)); + } + CurPtr += 4; + } + } + + watchdog_kick(); + + RTL_W8(TCR+3, 0x7f); + RTL_W8(MCUFWDL, (RTL_R8(MCUFWDL) & 0xfe) | MCUFWDL_RDY); + delay_ms(1); + //RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) | BIT(6)); + RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) & (~FW_DL_INPROC)); + delay_ms(1); + +check_fwdl_rdy: + + printk("<=== %s\n", __FUNCTION__); + // check if firmware is ready + wait_cnt = 0; +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pshare->wlandev_idx == 0) +#endif + { + while (!(RTL_R8(RSV_MAC0_FWCTRL) & MAC0_WINTINI_RDY)) { + if (++wait_cnt > 10) { + RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY)); + RESTORE_INT(flags); + DEBUG_ERR("8192d mac0 firmware not ready\n"); + return FALSE; + } + delay_ms(2*wait_cnt); + } + } +#ifdef CONFIG_RTL_92D_DMDP + else { + while (!(RTL_R8(RSV_MAC1_FWCTRL) & MAC1_WINTINI_RDY)) { + if (++wait_cnt > 10) { + RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY)); + RESTORE_INT(flags); + DEBUG_ERR("8192d mac1 firmware not ready\n"); + return FALSE; + } + delay_ms(2*wait_cnt); + + } + } +#endif + RESTORE_INT(flags); +#ifdef CONFIG_RTL8672 + printk("val=%x\n",RTL_R8(MCUFWDL)); +#endif + return TRUE; +} + + +/* + * 92DE Operation Mode + */ +void UpdateBBRFVal8192DE(struct rtl8192cd_priv *priv) +{ + u8 eRFPath = 0, curMaxRFPath; + //u32 u4RegValue=0; + + //Update BB + if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { + /* + * 5G + */ + //r_select_5G for path_A/B + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x1); + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0x1); + //rssi_table_select:index 0 for 2.4G.1~3 for 5G + PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x01); + //5G PA power on + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6); + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4); + + //TRSW.TRSWB and PAPE2G mode table + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){ + // TRSW_2, TRSWB_2 + PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 0); + // PAPE2G_2 + PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(7))>>7); + PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6); + } + // TRSW_1, TRSWB_1 + PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 0); + // PAPE2G_1 + PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(5))>>5); + PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4); +#ifdef RTL8192D_INT_PA + if (!priv->pshare->rf_ft_var.use_intpa92d) +#endif + { + //5G PA power on + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x1); + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x1); + } + // 5G LNA on + PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0x0); + //fc_area + if (priv->pmib->dot11RFEntry.dot11channel<149) + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1); + else + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2); + //cck_disable + PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x0); + //TX BB gain shift +#ifdef RTL8192D_INT_PA + if (priv->pshare->rf_ft_var.use_intpa92d){ + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x2d4000b5); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x2d4000b5); + } else +#endif + { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x20000080); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x20000080); + } + // Reset IQC + PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0); + //BB/DP IQC + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x010170b8); + + } else { + /* + * 2.4G + */ + // r_select_5G for path_A/B + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x0); + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0); + //rssi_table_select:index 0 for 2.4G.1~3 for 5G + PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x00); + //5G PA power on + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x0); + PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x0); + + //TRSW.TRSWB and PAPE2G mode table + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){ + // TRSW_2 + PHY_SetBBReg(priv, 0x870, BIT(21), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(7))>>7); + PHY_SetBBReg(priv, 0x864, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(6))>>6); + // TRSWB_2 + PHY_SetBBReg(priv, 0x870, BIT(22), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(5))>>5); + PHY_SetBBReg(priv, 0x864, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(4))>>4); + // PAPE2G_2 + PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(3))>>3); + PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(2))>>2); + } + // TRSW_1 + PHY_SetBBReg(priv, 0x870, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(3))>>3); + PHY_SetBBReg(priv, 0x860, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(2))>>2); + // TRSWB_1 + PHY_SetBBReg(priv, 0x870, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(1))>>1); + PHY_SetBBReg(priv, 0x860, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(0))>>0); + // PAPE2G_1 + PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(1))>>1); + PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(0))>>0); + + // 5G LNA on + PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0xa); + //fc_area + PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0x00); + //cck_enable + PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1); + //TX BB gain shift + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x40000100); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x40000100); + // Reset IQC + PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0); + //BB/DP IQC + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017038); + if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017038); + } + + //Update RF + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else + curMaxRFPath = RF92CD_PATH_MAX; + + for(eRFPath = RF92CD_PATH_A; eRFPath pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { + /* + * 5G + */ + priv->pshare->RegRF18[eRFPath] &= 0xffffff00; + priv->pshare->RegRF18[eRFPath] |= (BIT(16)|BIT(8)|0x24); //set channel 36 + PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]); + delay_ms(1); + // LDO_DIV + priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],BIT(7)|BIT(6),1,6); + //PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x01); + PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); + + delay_ms(30); + } else { + /* + * 2.4G + */ + priv->pshare->RegRF18[eRFPath] &= ~(BIT(16)|BIT(8)|0xFF); + priv->pshare->RegRF18[eRFPath] |= 1; //set channel 1. + PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]); + delay_ms(1); + // LDO_DIV + priv->pshare->RegRF28[eRFPath] &= (~(BIT(7)|BIT(6))); + //PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x00); + PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); + + delay_ms(30); + } + } + +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) { + //Use antenna 0 & 1 + PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x11); + PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x1); + + //disable ad/da clock1 + if (!(DMDP_RTL_R8(0,SYS_FUNC_EN)&(FEN_BB_GLB_RST|FEN_BBRSTB))){ + DMDP_RTL_W8(0, SYS_FUNC_EN, (DMDP_RTL_R8(0,SYS_FUNC_EN)|FEN_BB_GLB_RST|FEN_BBRSTB)); + } + DMDP_PHY_SetBBReg(0, rFPGA0_AdDaClockEn, BIT(13)|BIT(12), 3); + } else +#endif + { + //Use antenna 0 & 1 + PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x33); + PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x3); + + //disable ad/da clock1 + PHY_SetBBReg(priv, rFPGA0_AdDaClockEn, BIT(13) | BIT(12), 0); + } +} + + +#if 0 //def CLIENT_MODE +void clnt_save_IQK_res(struct rtl8192cd_priv *priv) +{ + priv->site_survey->bk_iqc[0] = PHY_QueryBBReg(priv,0xc80, bMaskDWord); + priv->site_survey->bk_iqc[1] = PHY_QueryBBReg(priv,0xc94, bMaskByte3); + priv->site_survey->bk_iqc[2] = PHY_QueryBBReg(priv,0xc4c, bMaskByte3); + priv->site_survey->bk_iqc[3] = PHY_QueryBBReg(priv,0xc88, bMaskDWord); + priv->site_survey->bk_iqc[4] = PHY_QueryBBReg(priv,0xc9c, bMaskByte3); + priv->site_survey->bk_iqc[5] = PHY_QueryBBReg(priv,0xc14, bMaskDWord); + priv->site_survey->bk_iqc[6] = PHY_QueryBBReg(priv,0xca0, bMaskByte3); + priv->site_survey->bk_iqc[7] = PHY_QueryBBReg(priv,0xc1c, bMaskDWord); + priv->site_survey->bk_iqc[8] = PHY_QueryBBReg(priv,0xc78, bMaskByte1); + priv->site_survey->bk_iqc[9] = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 1); + priv->site_survey->bk_iqc[10] = PHY_QueryRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 1); +} + + +void clnt_load_IQK_res(struct rtl8192cd_priv *priv) +{ + PHY_SetBBReg(priv,0xc80, bMaskDWord, priv->site_survey->bk_iqc[0]); + PHY_SetBBReg(priv,0xc94, bMaskByte3, priv->site_survey->bk_iqc[1]); + PHY_SetBBReg(priv,0xc4c, bMaskByte3, priv->site_survey->bk_iqc[2]); + PHY_SetBBReg(priv,0xc88, bMaskDWord, priv->site_survey->bk_iqc[3]); + PHY_SetBBReg(priv,0xc9c, bMaskByte3, priv->site_survey->bk_iqc[4]); + PHY_SetBBReg(priv,0xc14, bMaskDWord, priv->site_survey->bk_iqc[5]); + PHY_SetBBReg(priv,0xca0, bMaskByte3, priv->site_survey->bk_iqc[6]); + PHY_SetBBReg(priv,0xc1c, bMaskDWord, priv->site_survey->bk_iqc[7]); + PHY_SetBBReg(priv,0xc78, bMaskByte1, priv->site_survey->bk_iqc[8]); + PHY_SetRFReg(priv,RF92CD_PATH_A, 0x08, bMask20Bits, priv->site_survey->bk_iqc[9]); + PHY_SetRFReg(priv,RF92CD_PATH_B, 0x08, bMask20Bits, priv->site_survey->bk_iqc[10]); +} + +#endif + +#ifdef CONFIG_RTL_92D_DMDP +#if 0 //def CLIENT_MODE + +void clnt_92D_2T_AGSwitch(struct rtl8192cd_priv * priv, int target) +{ + unsigned int flags, i; + int rtStatus = 0; + unsigned char temp_0522, temp_0550, temp_0551, temp_0800; + unsigned char reg; + + SAVE_INT_AND_CLI(flags); + + /* + * Save MAC default value + */ + temp_0522 = RTL_R8(0x522); + temp_0550 = RTL_R8(0x550); + temp_0551 = RTL_R8(0x551); + + /* + * MAC register setting + */ + RTL_W8(0x522, 0x3f); + RTL_W8(0x550, temp_0550& (~BIT(3))); + RTL_W8(0x551, temp_0551& (~BIT(3))); + + // stop BB + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf); + temp_0800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000); + PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0); + + // 5G_PAPE Select & external PA power on + PHY_SetBBReg(priv, 0x878, BIT(0), 0); + PHY_SetBBReg(priv, 0x878, BIT(16), 0); + PHY_SetBBReg(priv, 0x878, BIT(15), 0); + PHY_SetBBReg(priv, 0x878, BIT(31), 0); + // RSSI Table Select + PHY_SetBBReg(priv, 0xc78, BIT(7)|BIT(6), 0); + // fc_area + PHY_SetBBReg(priv, 0xd2c, BIT(14)|BIT(13), 0); + // cck_enable + PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1); + // LDO_DIV + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 0); + PHY_SetRFReg(priv, RF92CD_PATH_B, 0x28, BIT(7)|BIT(6), 0); + // MOD_AG // Set channel number + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(16), 0); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(8), 0); + PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(16), 0); + PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(8), 0); + // CLOAD for path_A + PHY_SetRFReg(priv, RF92CD_PATH_A, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7); + PHY_SetRFReg(priv, RF92CD_PATH_B, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7); + + // IMR + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x70000); + for (i=0;i<11;i++) { + PHY_SetRFReg(priv, RF92CD_PATH_A, (0x2f+i), bMask20Bits, IMR_SET_N[0][i]); + } + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x32fff); + + // Enable BB + PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_0800); + // IQK + PHY_SetBBReg(priv, 0xc80, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xc94, bMaskByte3, 0); + PHY_SetBBReg(priv, 0xc4c, bMaskByte3, 0); + PHY_SetBBReg(priv, 0xc88, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xc9c, bMaskByte3, 0); + PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xca0, bMaskByte3, 0); + PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xc78, bMaskByte1, 0); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000); + PHY_SetRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 0x84000); + + //Set related registers for BW config + + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0); + + /* + * Reload MAC default value + */ + RTL_W8(0x550, temp_0550); + RTL_W8(0x551, temp_0551); + RTL_W8(0x522, temp_0522); + + RESTORE_INT(flags); +} + +#endif + +#endif //CONFIG_RTL_92D_DMDP + +#endif // CONFIG_RTL_92D_SUPPORT + + + diff --git a/package/kernel/rtl8192cd/8192e_reg.h b/package/kernel/rtl8192cd/8192e_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8723b_reg.h b/package/kernel/rtl8192cd/8723b_reg.h index 9883dd20ce7..2be670fa930 100644 --- a/package/kernel/rtl8192cd/8723b_reg.h +++ b/package/kernel/rtl8192cd/8723b_reg.h @@ -1,1765 +1,1765 @@ - - - -#ifndef _8723B_REG_H_ -#define _8723B_REG_H_ - -#ifndef WLAN_HAL_INTERNAL_USED - - -//============================================================ -// 8188E Regsiter offset definition -//============================================================ - - -/* - * Project RTL8188E follows most of registers in Project RTL8192c - * This file includes additional registers for RTL8188E only - * Header file of RTL8192C registers should always be included - */ - -// -// 1. System Configure Register. (Offset 0x000 - 0x0FFh) -// -#define REG_8723B_BB_PAD_CTRL 0x64 -#define REG_8723B_HMEBOX_E0 0x88 -#define REG_8723B_HMEBOX_E1 0x8A -#define REG_8723B_HMEBOX_E2 0x8C -#define REG_8723B_HMEBOX_E3 0x8E -#define REG_8723B_WLLPS_CTRL 0x90 -#define REG_8723B_RPWM2 0x9E -#define REG_8723B_HIMR 0xB0 -#define REG_8723B_HISR 0xB4 -#define REG_8723B_HIMRE 0xB8 -#define REG_8723B_HISRE 0xBC -#define REG_8723B_EFUSE_DATA1 0xCC -#define REG_8723B_EFUSE_DATA0 0xCD -#define REG_8723B_EPPR 0xCF -#define REG_8723B_TXDMA_TH 0x218 -#define REG_8723B_LQ_TH 0x21C - -#define REG_8723B_WATCHDOG 0x368 - -#define REG_8723B_MACID_NOLINK 0x484 -#define REG_8723B_MACID_PAUSE 0x48C -#define REG_8723B_TXRPT_CTRL 0x4EC -#define REG_8723B_TXRPT_TIM 0x4F0 -#define REG_8723B_TXRPT_STSSET 0x4F2 -#define REG_8723B_TXRPT_STSVLD 0x4F4 -#define REG_8723B_TXRPT_STSINF 0x4F8 - - - -//============================================================ -// Registers for 8188E IQK -//============================================================ - - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - - -#define RF_RCK_OS 0x30 // RF TX PA control -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C // -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B - -#define RF_WE_LUT 0xEF - - -//#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch -//#define rFPGA0_XCD_SwitchControl 0x85c - -//#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control -//#define rFPGA0_XCD_RFInterfaceSW 0x874 - -//#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter -//#define rFPGA0_XCD_RFParameter 0x87c - -//#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -//#define rFPGA0_AnalogParameter2 0x884 -//#define rFPGA0_AnalogParameter3 0x888 -//#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy -//#define rFPGA0_AnalogParameter4 0x88c - -//#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback -//#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -//#define rFPGA0_PSDReport 0x8b4 // Useless now -//#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback -//#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback -//#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now - - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - - -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS_CTX 0x0514 -#define REG_SIFS_TRX 0x0516 -#define REG_TSFTR_SNC_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 - - -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 -#define REG_BCN_CTRL 0x0550 -#define REG_BCN_CTRL_1 0x0551 -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 -#define REG_TSFTR1 0x0568 // HW Port 1 TSF Register -#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) -#define REG_PSTIMER 0x0580 -#define REG_TIMER0 0x0584 -#define REG_TIMER1 0x0588 -#define REG_ACMHWCTRL 0x05C0 -#define REG_NOA_DESC_SEL 0x05CF -#define REG_NOA_DESC_DURATION 0x05E0 -#define REG_NOA_DESC_INTERVAL 0x05E4 -#define REG_NOA_DESC_START 0x05E8 -#define REG_NOA_DESC_COUNT 0x05EC - - -#define REG_SYS_ISO_CTRL 0x0000 -//#define REG_SYS_FUNC_EN 0x0002 -#define REG_APS_FSMCO 0x0004 -#define REG_SYS_CLKR 0x0008 -#define REG_9346CR 0x000A -#define REG_EE_VPD 0x000C -#define REG_AFE_MISC 0x0010 -#define REG_SPS0_CTRL 0x0011 -#define REG_SPS0_CTRL_6 0x0016 -#define REG_POWER_OFF_IN_PROCESS 0x0017 -#define REG_SPS_OCP_CFG 0x0018 -#define REG_RSV_CTRL 0x001C -//#define REG_RF_CTRL 0x001F -#define REG_LDOA15_CTRL 0x0020 -#define REG_LDOV12D_CTRL 0x0021 -//#define REG_LDOHCI12_CTRL 0x0022 -#define REG_LPLDO_CTRL 0x0023 -//#define REG_AFE_XTAL_CTRL 0x0024 -//#define REG_AFE_PLL_CTRL 0x0028 -#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl -#define REG_EFUSE_CTRL 0x0030 -#define REG_EFUSE_TEST 0x0034 -#define REG_PWR_DATA 0x0038 -#define REG_CAL_TIMER 0x003C -#define REG_ACLK_MON 0x003E -#define REG_GPIO_MUXCFG 0x0040 -#define REG_GPIO_IO_SEL 0x0042 -#define REG_MAC_PINMUX_CFG 0x0043 -#define REG_GPIO_PIN_CTRL 0x0044 -#define REG_GPIO_INTM 0x0048 -#define REG_LEDCFG0 0x004C -#define REG_LEDCFG1 0x004D -#define REG_LEDCFG2 0x004E -#define REG_LEDCFG3 0x004F -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 -#define REG_HSIMR 0x0058 -#define REG_HSISR 0x005c -#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. -#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. -#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. -#define REG_GPIO_OUTPUT 0x006c -#define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E -#define REG_XCK_OUT_CTRL 0x007c //RTL8188E -//#define REG_MCUFWDL 0x0080 -#define REG_WOL_EVENT 0x0081 //RTL8188E -#define REG_MCUTSTCFG 0x0084 -#define REG_HMEBOX_EXT_0 0x0088 -#define REG_HMEBOX_EXT_1 0x008A -#define REG_HMEBOX_EXT_2 0x008C -#define REG_HMEBOX_EXT_3 0x008E -#define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform -#define REG_HIMR_8723B 0x00B0 //RTL8188E -#define REG_HISR_8723B 0x00B4 //RTL8188E -#define REG_HIMRE_8723B 0x00B8 //RTL8188E -#define REG_HISRE_8723B 0x00BC //RTL8188E -#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 -#define REG_BIST_SCAN 0x00D0 -#define REG_BIST_RPT 0x00D4 -#define REG_BIST_ROM_RPT 0x00D8 -#define REG_USB_SIE_INTF 0x00E0 -#define REG_PCIE_MIO_INTF 0x00E4 -#define REG_PCIE_MIO_INTD 0x00E8 -#define REG_HPON_FSM 0x00EC -#define REG_SYS_CFG 0x00F0 -#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. -#define REG_TYPE_ID 0x00FC - -#define REG_32K_CTRL 0x0194 //RTL8188E - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c - - -//============================================================================ -// 8188E Regsiter Bit and Content definition -//============================================================================ - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_BB_PAD_CTRL bits (Offset 0x64-66, 24 bits) -//---------------------------------------------------------------------------- -#define BB_PAD_CTRL_8723B_PAPE_EN BIT(19) // PAD ¡§P_LNAON¡¨ output enable -#define BB_PAD_CTRL_8723B_PAPE_DRV BIT(18) // PAD ¡§P_LNAON¡¨ output value -#define BB_PAD_CTRL_8723B_LNAON_SR BIT(17) // Control SR of PAD ¡§P_LNAON¡¨ to control the slew rate -#define BB_PAD_CTRL_8723B_LNAON_E2 BIT(16) // Control E2 of PAD ¡§P_LNAON¡¨ for its output driving capability -#define BB_PAD_CTRL_8723B_TRSW_EN BIT(11) // PAD ¡§P_TRSWP¡¨ and ¡§P_TRSWN¡¨ output enable -#define BB_PAD_CTRL_8723B_TRSW_DRV BIT(10) // PADs ¡§P_TRSWP¡¨ and ¡§P_TRSWN¡¨ outputs values - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_WLLPS_CTRL bits (Offset 0x90-93, 32 bits) -//---------------------------------------------------------------------------- -#define WLLPS_CTRL_8723B_EABM BIT(31) -#define WLLPS_CTRL_8723B_ACKF BIT(30) -#define WLLPS_CTRL_8723B_ESWR BIT(28) -#define WLLPS_CTRL_8723B_PWMM BIT(27) -#define WLLPS_CTRL_8723B_EECK BIT(26) -#define WLLPS_CTRL_8723B_ELDO BIT(25) -#define WLLPS_CTRL_8723B_EXTAL BIT(24) -#define WLLPS_CTRL_8723B_LPS_EN BIT(0) - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_HIMR bits (Offset 0xB0-B3, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8188E REG_8723B_HISR bits (Offset 0xB4-B7, 32 bits) -//---------------------------------------------------------------------------- -#define HIMR_8723B_TXCCK BIT(30) // TXRPT interrupt when CCX bit of the packet is set -#define HIMR_8723B_PSTIMEOUT BIT(29) // Power Save Time Out Interrupt -#define HIMR_8723B_GTINT4 BIT(28) // When GTIMER4 expires, this bit is set to 1 -#define HIMR_8723B_GTINT3 BIT(27) // When GTIMER3 expires, this bit is set to 1 -#define HIMR_8723B_TBDER BIT(26) // Transmit Beacon0 Error -#define HIMR_8723B_TBDOK BIT(25) // Transmit Beacon0 OK, ad hoc only -#define HIMR_8723B_TSF_BIT32_TOGGLE BIT(24) // TSF Timer BIT32 toggle indication interrupt -#define HIMR_8723B_BcnInt BIT(20) // Beacon DMA Interrupt 0 -#define HIMR_8723B_BDOK BIT(16) // Beacon Queue DMA OK0 -#define HIMR_8723B_HSISR_IND_ON_INT BIT(15) // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define HIMR_8723B_BCNDMAINT_E BIT(14) // Beacon DMA Interrupt Extension for Win7 -#define HIMR_8723B_ATIMEND BIT(12) // CTWidnow End or ATIM Window End -#define HIMR_8723B_HISR1_IND_INT BIT(11) // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) -#define HIMR_8723B_C2HCMD BIT(10) // CPU to Host Command INT Status, Write 1 clear -#define HIMR_8723B_CPWM2 BIT(9) // CPU power Mode exchange INT Status, Write 1 clear -#define HIMR_8723B_CPWM BIT(8) // CPU power Mode exchange INT Status, Write 1 clear -#define HIMR_8723B_HIGHDOK BIT(7) // High Queue DMA OK -#define HIMR_8723B_MGNTDOK BIT(6) // Management Queue DMA OK -#define HIMR_8723B_BKDOK BIT(5) // AC_BK DMA OK -#define HIMR_8723B_BEDOK BIT(4) // AC_BE DMA OK -#define HIMR_8723B_VIDOK BIT(3) // AC_VI DMA OK -#define HIMR_8723B_VODOK BIT(2) // AC_VO DMA OK -#define HIMR_8723B_RDU BIT(1) // Rx Descriptor Unavailable -#define HIMR_8723B_ROK BIT(0) // Receive DMA OK - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_HIMRE bits (Offset 0xB8-BB, 32 bits) -//---------------------------------------------------------------------------- -//---------------------------------------------------------------------------- -// 8188E REG_8723B_HIMSE bits (Offset 0xBC-BF, 32 bits) -//---------------------------------------------------------------------------- -#define HIMRE_8723B_BCNDMAINT7 BIT(27) // Beacon DMA Interrupt 7 -#define HIMRE_8723B_BCNDMAINT6 BIT(26) // Beacon DMA Interrupt 6 -#define HIMRE_8723B_BCNDMAINT5 BIT(25) // Beacon DMA Interrupt 5 -#define HIMRE_8723B_BCNDMAINT4 BIT(24) // Beacon DMA Interrupt 4 -#define HIMRE_8723B_BCNDMAINT3 BIT(23) // Beacon DMA Interrupt 3 -#define HIMRE_8723B_BCNDMAINT2 BIT(22) // Beacon DMA Interrupt 2 -#define HIMRE_8723B_BCNDMAINT1 BIT(21) // Beacon DMA Interrupt 1 -#define HIMRE_8723B_BCNDOK7 BIT(20) // Beacon Queue DMA OK Interrup 7 -#define HIMRE_8723B_BCNDOK6 BIT(19) // Beacon Queue DMA OK Interrup 6 -#define HIMRE_8723B_BCNDOK5 BIT(18) // Beacon Queue DMA OK Interrup 5 -#define HIMRE_8723B_BCNDOK4 BIT(17) // Beacon Queue DMA OK Interrup 4 -#define HIMRE_8723B_BCNDOK3 BIT(16) // Beacon Queue DMA OK Interrup 3 -#define HIMRE_8723B_BCNDOK2 BIT(15) // Beacon Queue DMA OK Interrup 2 -#define HIMRE_8723B_BCNDOK1 BIT(14) // Beacon Queue DMA OK Interrup 1 -#define HIMRE_8723B_ATIMEND_E BIT(13) // ATIM Window End Extension for Win7 -#define HIMRE_8723B_TXERR BIT(11) // Tx Error Flag Interrupt Status, write 1 clear. -#define HIMRE_8723B_RXERR BIT(10) // Rx Error Flag INT Status, Write 1 clear -#define HIMRE_8723B_TXFOVW BIT(9) // Transmit FIFO Overflow -#define HIMRE_8723B_RXFOVW BIT(8) // Receive FIFO Overflow - - -//---------------------------------------------------------------------------- -// 8188E REG_EFUSE_ACCESS (Offset 0xCF, 8 bits) -//---------------------------------------------------------------------------- -#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. -#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_WATCHDOG bits (Offset 0x368-369, 16 bits) -//---------------------------------------------------------------------------- -#define WATCHDOG_8723B_ENABLE BIT(15) // Enable lbc timeout watchdog -#define WATCHDOG_8723B_R_IO_TIMEOUT_FLAG BIT(14) // Lbc timeout flag.Write ¡§1¡¨ to clear -#define WATCHDOG_8723B_RECORD_Mask 0x3FFF // Time out register address - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_TXRPT_CTRL bits (Offset 0x4EC-4EF, 32 bits) -//---------------------------------------------------------------------------- -#define TXRPT_CTRL_8723B_CNT_TH_SHIFT 16 -#define TXRPT_CTRL_8723B_CNT_TH_Mask 0xFFFF -#define TXRPT_CTRL_8723B_RPT_MACID_SHIFT 8 -#define TXRPT_CTRL_8723B_RPT_MACID_Mask 0x7F -#define TXRPT_CTRL_8723B_BCN_EN BIT(4) -#define TXRPT_CTRL_8723B_TXRPT_DIS BIT(3) -#define TXRPT_CTRL_8723B_CNT_OVER_EN BIT(2) -#define TXRPT_CTRL_8723B_TXRPT_TIM_EN BIT(1) -#define TXRPT_CTRL_8723B_TXRPT_EN BIT(0) - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_TXRPT_STSSET bits (Offset 0x4F2-4F3, 16 bits) -//---------------------------------------------------------------------------- -#define TXRPT_STSSET_8723B_TX_STS_SEL_SHIFT 11 -#define TXRPT_STSSET_8723B_TX_STS_SEL_Mask 0x1F -#define TXRPT_STSSET_8723B_TX_STS_CLR BIT(10) -#define TXRPT_STSSET_8723B_TX_STS_EN BIT(8) -#define TXRPT_STSSET_8723B_TX_STS_SET BIT(7) -#define TXRPT_STSSET_8723B_TX_STS_PORT BIT(6) -#define TXRPT_STSSET_8723B_TX_STS_SUBTPY_SHIFT 2 -#define TXRPT_STSSET_8723B_TX_STS_SUBTPY_Mask 0xF -#define TXRPT_STSSET_8723B_TX_STS_TPY_SHIFT 0 -#define TXRPT_STSSET_8723B_TX_STS_TPY_Mask 0x3 - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_TXRPT_STSVLD bits (Offset 0x4F4-4F6, 24 bits) -//---------------------------------------------------------------------------- -#define TXRPT_STSVLD_8723B_TX_TPY7_VLD BIT(23) -#define TXRPT_STSVLD_8723B_TX_TPY6_VLD BIT(22) -#define TXRPT_STSVLD_8723B_TX_TPY5_VLD BIT(21) -#define TXRPT_STSVLD_8723B_TX_TPY4_VLD BIT(20) -#define TXRPT_STSVLD_8723B_TX_TPY3_VLD BIT(19) -#define TXRPT_STSVLD_8723B_TX_TPY2_VLD BIT(18) -#define TXRPT_STSVLD_8723B_TX_TPY1_VLD BIT(17) -#define TXRPT_STSVLD_8723B_TX_TPY0_VLD BIT(16) -#define TXRPT_STSVLD_8723B_TX_BCN7_FAIL BIT(15) -#define TXRPT_STSVLD_8723B_TX_BCN6_FAIL BIT(14) -#define TXRPT_STSVLD_8723B_TX_BCN5_FAIL BIT(13) -#define TXRPT_STSVLD_8723B_TX_BCN4_FAIL BIT(12) -#define TXRPT_STSVLD_8723B_TX_BCN3_FAIL BIT(11) -#define TXRPT_STSVLD_8723B_TX_BCN2_FAIL BIT(10) -#define TXRPT_STSVLD_8723B_TX_BCN1_FAIL BIT(9) -#define TXRPT_STSVLD_8723B_TX_BCN0_FAIL BIT(8) -#define TXRPT_STSVLD_8723B_TX_BCN7_OK BIT(7) -#define TXRPT_STSVLD_8723B_TX_BCN6_OK BIT(6) -#define TXRPT_STSVLD_8723B_TX_BCN5_OK BIT(5) -#define TXRPT_STSVLD_8723B_TX_BCN4_OK BIT(4) -#define TXRPT_STSVLD_8723B_TX_BCN3_OK BIT(3) -#define TXRPT_STSVLD_8723B_TX_BCN2_OK BIT(2) -#define TXRPT_STSVLD_8723B_TX_BCN1_OK BIT(1) -#define TXRPT_STSVLD_8723B_TX_BCN0_OK BIT(0) - - -//---------------------------------------------------------------------------- -// 8188E REG_8723B_TX_STS_INF bits (Offset 0x4F8-4F9, 16 bits) -//---------------------------------------------------------------------------- -#define TX_STS_INF_8723B_TX_STS_INF_EN BIT(8) -#define TX_STS_INF_8723B_TX_STS_SET_INF BIT(7) -#define TX_STS_INF_8723B_TX_STS_PORT_INF BIT(6) -#define TX_STS_INF_8723B_TX_STS_SUBTPY_INF_SHIFT 2 -#define TX_STS_INF_8723B_TX_STS_SUBTPY_INF_Mask 0xF -#define TX_STS_INF_8723B_TX_STS_TPY_INF_SHIFT 0 -#define TX_STS_INF_8723B_TX_STS_TPY_INF_Mask 0x3 - - -//---------------------------------------------------------------------------- -// 8192C EEPROM/EFUSE share register definition. -//---------------------------------------------------------------------------- - -//==================================================== -// EEPROM/Efuse PG Offset for 88EE/88EU/88ES -//==================================================== -#define EEPROM_TX_PWR_INX_88E 0x10 - -#define EEPROM_ChannelPlan_88E 0xB8 -#define EEPROM_XTAL_88E 0xB9 -#define EEPROM_THERMAL_METER_88E 0xBA -#define EEPROM_IQK_LCK_88E 0xBB - -#define EEPROM_RF_BOARD_OPTION_88E 0xC1 -#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 -#define EEPROM_RF_BT_SETTING_88E 0xC3 -#define EEPROM_VERSION_88E 0xC4 -#define EEPROM_CUSTOMERID_88E 0xC5 -#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 - -// RTL8723B -#define EEPROM_MAC_ADDR_8723B 0xD0 -#define EEPROM_VID_88EE 0xD6 -#define EEPROM_DID_88EE 0xD8 -#define EEPROM_SVID_88EE 0xDA -#define EEPROM_SMID_88EE 0xDC - -#if 0 -//RTL88EU -#define EEPROM_MAC_ADDR_88EU 0xD7 -#define EEPROM_VID_88EU 0xD0 -#define EEPROM_PID_88EU 0xD2 - -// RTL88ES -#define EEPROM_MAC_ADDR_88ES 0x11A -#endif - -//----------------------------------------------------- -// -// RTL8188E SDIO Configuration -// -//----------------------------------------------------- - -// I/O bus domain address mapping -#define SDIO_LOCAL_BASE 0x10250000 -#define WLAN_IOREG_BASE 0x10260000 -#define FIRMWARE_FIFO_BASE 0x10270000 -#define TX_HIQ_BASE 0x10310000 -#define TX_MIQ_BASE 0x10320000 -#define TX_LOQ_BASE 0x10330000 -#define RX_RX0FF_BASE 0x10340000 - -// SDIO host local register space mapping. -#define SDIO_LOCAL_MSK 0x0FFF -#define WLAN_IOREG_MSK 0x7FFF -#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] -#define WLAN_RX0FF_MSK 0x0003 - -#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID -#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] -#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] -#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] -#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] -#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] -#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] - -// SDIO Tx Free Page Index -#define HI_QUEUE_IDX 0 -#define MID_QUEUE_IDX 1 -#define LOW_QUEUE_IDX 2 -#define PUBLIC_QUEUE_IDX 3 - -#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ -#define SDIO_MAX_RX_QUEUE 1 - -#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control -#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask -#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine -#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode -#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length -#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page -#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 -#define SDIO_REG_OQT_FREE_SPACE 0x0025 // OQT Free Space -#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 -#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion -#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 -#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 -#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock -#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control -#define SDIO_REG_HIMR_ON 0x0090 // SDIO Host Extension Interrupt Mask Always -#define SDIO_REG_HISR_ON 0x0091 // SDIO Host Extension Interrupt Status Always - -#define SDIO_HIMR_DISABLED 0 - -// RTL8188E SDIO Host Interrupt Mask Register -#define SDIO_HIMR_RX_REQUEST_MSK BIT0 -#define SDIO_HIMR_AVAL_MSK BIT1 -#define SDIO_HIMR_TXERR_MSK BIT2 -#define SDIO_HIMR_RXERR_MSK BIT3 -#define SDIO_HIMR_TXFOVW_MSK BIT4 -#define SDIO_HIMR_RXFOVW_MSK BIT5 -#define SDIO_HIMR_TXBCNOK_MSK BIT6 -#define SDIO_HIMR_TXBCNERR_MSK BIT7 -#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 -#define SDIO_HIMR_C2HCMD_MSK BIT17 -#define SDIO_HIMR_CPWM1_MSK BIT18 -#define SDIO_HIMR_CPWM2_MSK BIT19 -#define SDIO_HIMR_HSISR_IND_MSK BIT20 -#define SDIO_HIMR_GTINT3_IND_MSK BIT21 -#define SDIO_HIMR_GTINT4_IND_MSK BIT22 -#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 -#define SDIO_HIMR_OCPINT_MSK BIT24 -#define SDIO_HIMR_ATIMEND_MSK BIT25 -#define SDIO_HIMR_ATIMEND_E_MSK BIT26 -#define SDIO_HIMR_CTWEND_MSK BIT27 - -//RTL8188E SDIO Specific -#define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 - -// SDIO Host Interrupt Service Routine -#define SDIO_HISR_RX_REQUEST BIT0 -#define SDIO_HISR_AVAL BIT1 -#define SDIO_HISR_TXERR BIT2 -#define SDIO_HISR_RXERR BIT3 -#define SDIO_HISR_TXFOVW BIT4 -#define SDIO_HISR_RXFOVW BIT5 -#define SDIO_HISR_TXBCNOK BIT6 -#define SDIO_HISR_TXBCNERR BIT7 -#define SDIO_HISR_BCNERLY_INT BIT16 -#define SDIO_HISR_C2HCMD BIT17 -#define SDIO_HISR_CPWM1 BIT18 -#define SDIO_HISR_CPWM2 BIT19 -#define SDIO_HISR_HSISR_IND BIT20 -#define SDIO_HISR_GTINT3_IND BIT21 -#define SDIO_HISR_GTINT4_IND BIT22 -#define SDIO_HISR_PSTIMEOUT BIT23 -#define SDIO_HISR_OCPINT BIT24 -#define SDIO_HISR_ATIMEND BIT25 -#define SDIO_HISR_ATIMEND_E BIT26 -#define SDIO_HISR_CTWEND BIT27 - -//RTL8188E SDIO Specific -#define SDIO_HISR_MCU_ERR BIT28 -#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 - -#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ - SDIO_HISR_RXERR |\ - SDIO_HISR_TXFOVW |\ - SDIO_HISR_RXFOVW |\ - SDIO_HISR_TXBCNOK |\ - SDIO_HISR_TXBCNERR |\ - SDIO_HISR_C2HCMD |\ - SDIO_HISR_CPWM1 |\ - SDIO_HISR_CPWM2 |\ - SDIO_HISR_HSISR_IND |\ - SDIO_HISR_GTINT3_IND |\ - SDIO_HISR_GTINT4_IND |\ - SDIO_HISR_PSTIMEOUT |\ - SDIO_HISR_OCPINT) - -// SDIO HCI Suspend Control Register -#define HCI_RESUME_PWR_RDY BIT1 -#define HCI_SUS_CTRL BIT0 - -// SDIO Tx FIFO related -#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page -#define SDIO_TX_FIFO_PAGE_SZ 128 - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- - -//2 Special Option -// 0; Use interrupt endpoint to upload interrupt pkt -// 1; Use bulk endpoint to upload interrupt pkt, -#define INT_BULK_SEL BIT(4) - -//======================================================== -// General definitions -//======================================================== - -#define LAST_ENTRY_OF_TX_PKT_BUFFER_88E 176 // 22k 22528 bytes - -#ifdef USE_OUT_SRC - - -/*--------------------------Define Parameters-------------------------------*/ - - -// -// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 -// 3. RF register 0x00-2E -// 4. Bit Mask for BB/RF register -// 5. Other defintion for BB/RF R/W -// - - -// -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 1. Page1(0x100) -// -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -// -// 2. Page2(0x200) -// -// The following two definition are only used for USB interface. -#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. -#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. - -// -// 3. Page8(0x800) -// -#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? - -#define rFPGA0_TxInfo 0x804 // Status report?? -#define rFPGA0_PSDFunction 0x808 - -#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? - -#define rFPGA0_RFTiming1 0x810 // Useless now -#define rFPGA0_RFTiming2 0x814 - -#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_RFWakeUpParameter 0x850 // Useless now -#define rFPGA0_RFSleepUpParameter 0x854 - -#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 -#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_PSDReport 0x8b4 // Useless now -#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback -#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now - -// -// 4. Page9(0x900) -// -#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? - -#define rFPGA1_TxBlock 0x904 // Useless now -#define rFPGA1_DebugSelect 0x908 // Useless now -#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? - -// -// 5. PageA(0xA00) -// -// Set Control channel to upper or lower. These settings are required only for 40MHz -#define rCCK0_System 0xa00 - -#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI -#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain - -#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series -#define rCCK0_RxAGC2 0xa10 //AGC & DAGC - -#define rCCK0_RxHP 0xa14 - -#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold -#define rCCK0_DSPParameter2 0xa1c //SQ threshold - -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 -#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 //0xa57 -#define rCCK0_FACounterLower 0xa5c //0xa5b -#define rCCK0_FACounterUpper 0xa58 //0xa5c - -// -// PageB(0xB00) -// -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rPdp_AntA_8 0xb08 -#define rPdp_AntA_C 0xb0c -#define rPdp_AntA_10 0xb10 -#define rPdp_AntA_14 0xb14 -#define rPdp_AntA_18 0xb18 -#define rPdp_AntA_1C 0xb1c -#define rPdp_AntA_20 0xb20 -#define rPdp_AntA_24 0xb24 - -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_ram64x16 0xb2c - -#define rBndA 0xb30 -#define rHssiPar 0xb34 - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c - -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rPdp_AntB_8 0xb78 -#define rPdp_AntB_C 0xb7c -#define rPdp_AntB_10 0xb80 -#define rPdp_AntB_14 0xb84 -#define rPdp_AntB_18 0xb88 -#define rPdp_AntB_1C 0xb8c -#define rPdp_AntB_20 0xb90 -#define rPdp_AntB_24 0xb94 - -#define rConfig_Pmpd_AntB 0xb98 - -#define rBndB 0xba0 - -#define rAPK 0xbd8 -#define rPm_Rx0_AntA 0xbdc -#define rPm_Rx1_AntA 0xbe0 -#define rPm_Rx2_AntA 0xbe4 -#define rPm_Rx3_AntA 0xbe8 -#define rPm_Rx0_AntB 0xbec -#define rPm_Rx1_AntB 0xbf0 -#define rPm_Rx2_AntB 0xbf4 -#define rPm_Rx3_AntB 0xbf8 - - - -// -// 6. PageC(0xC00) -// -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain -#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. -#define rOFDM0_RxDetector3 0xc38 //Frame Sync. -#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI - -#define rOFDM0_RxDSP 0xc40 //Rx Sync Path -#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC -#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold -#define rOFDM0_ECCAThreshold 0xc4c // energy CCA - -#define rOFDM0_XAAGCCore1 0xc50 // DIG -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - - -// -// 7. PageD(0xD00) -// -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -#define rOFDM1_CFO 0xd08 // No setting now -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 - -#define rOFDM_PHYCounter1 0xda0 //cca, parity fail -#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail -#define rOFDM_PHYCounter3 0xda8 //MCS not support - -#define rOFDM_ShortCFOAB 0xdac // No setting now -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -// -// 8. PageE(0xE00) -// -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - -// -// 7. RF Register 0x00-0x2E (RF 8256) -// RF-0222D 0x00-3F -// -//Zebra1 -#define rZebra1_HSSIEnable 0x0 // Useless now -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 // RF channel switch - -//#endif -#define rZebra1_TxGain 0x8 // Useless now -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -//Zebra4 -#define rGlobalCtrl 0 // Useless now -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -//RTL8258 -#define rRTL8258_TxLPF 0x11 // Useless now -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -// -// RL6052 Register definition -// -#define RF_AC 0x00 // - -#define RF_IQADJ_G1 0x01 // -#define RF_IQADJ_G2 0x02 // -#define RF_BS_PA_APSET_G1_G4 0x03 -#define RF_BS_PA_APSET_G5_G8 0x04 -#define RF_POW_TRSW 0x05 // - -#define RF_GAIN_RX 0x06 // -#define RF_GAIN_TX 0x07 // - -#define RF_TXM_IDAC 0x08 // -#define RF_IPA_G 0x09 // -#define RF_TXBIAS_G 0x0A -#define RF_TXPA_AG 0x0B -#define RF_IPA_A 0x0C // -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_BS_IQGEN 0x0F // - -#define RF_MODE1 0x10 // -#define RF_MODE2 0x11 // - -#define RF_RX_AGC_HP 0x12 // -#define RF_TX_AGC 0x13 // -#define RF_BIAS 0x14 // -#define RF_IPA 0x15 // -#define RF_TXBIAS 0x16 -#define RF_POW_ABILITY 0x17 // -#define RF_CHNLBW 0x18 // RF channel and BW switch -#define RF_TOP 0x19 // - -#define RF_RX_G1 0x1A // -#define RF_RX_G2 0x1B // - -#define RF_RX_BB2 0x1C // -#define RF_RX_BB1 0x1D // - -#define RF_RCK1 0x1E // -#define RF_RCK2 0x1F // - -#define RF_TX_G1 0x20 // -#define RF_TX_G2 0x21 // -#define RF_TX_G3 0x22 // - -#define RF_TX_BB1 0x23 // - -//#if HARDWARE_TYPE_IS_RTL8192D == 1 -#define RF_T_METER_92D 0x42 // -#define RF_T_METER_88E 0x42 // -//#else -#define RF_T_METER 0x24 // -//#endif - -#define RF_SYN_G1 0x25 // RF TX Power control -#define RF_SYN_G2 0x26 // RF TX Power control -#define RF_SYN_G3 0x27 // RF TX Power control -#define RF_SYN_G4 0x28 // RF TX Power control -#define RF_SYN_G5 0x29 // RF TX Power control -#define RF_SYN_G6 0x2A // RF TX Power control -#define RF_SYN_G7 0x2B // RF TX Power control -#define RF_SYN_G8 0x2C // RF TX Power control - -#define RF_RCK_OS 0x30 // RF TX PA control - -#define RF_RCK_OS 0x30 // RF TX PA control -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C // -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B - -// -//Bit Mask -// -// 1. Page1(0x100) -#define bBBResetB 0x100 // Useless now? -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) - -// 2. Page8(0x800) -#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 // Useless now -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f - -#define bAntennaSelect 0x0300 - -#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -#define bPAStart 0xf0000000 // Useless now -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf //Reg0x814 -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 //T2R -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 //chane gain at continue Tx -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 // Useless now -//#define bHWSISelect 0x8 -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW - -#define bRFSI_TRSW 0x20 // Useless now -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -#define bLSSIReadAddress 0x7f800000 // T65 RF - -#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal - -#define bLSSIReadBackData 0xfffff // T65 RF - -#define bLSSIReadOKFlag 0x1000 // Useless now -#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ - -#define b80MClkDelay 0x18000000 // Useless -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bXtalCap 0x0f000000 - -#define bIntDifClkEnable 0x400 // Useless -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -// 3. Page9(0x900) -#define bOFDMTxSC 0x30000000 // Useless -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff //reset debug page and also HWord, LWord -#define bDebugItem 0xff //reset debug page and LWord -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -// 4. PageA(0xA00) -#define bCCKBBMode 0x3 // Useless -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch - -#define bCCKScramble 0x8 // Useless -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 //r_rx_clk -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f //AGCsamp_dly -#define bCCKFixedRxAGC 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -// 5. PageC(0xC00) -#define bNumOfSTF 0x3 // Useless -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 //the threshold for high power -#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -//#define bRxMF_Hold 0x3800 -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -#define bExtLNAGain 0x7c00 - -// 6. PageE(0xE00) -#define bSTBCEn 0x4 // Useless -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -//#define bRxPath1 0x01 -//#define bRxPath2 0x02 -//#define bRxPath3 0x04 -//#define bRxPath4 0x08 -//#define bTxPath1 0x10 -//#define bTxPath2 0x20 -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 //total -#define bShortCFOFLength 11 //fraction -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf // Useless -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 // Useless -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 // Useless -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -//Rx Pseduo noise -#define bRxPesudoNoiseOn 0x20000000 // Useless -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -//7. RF Register -//Zebra1 -#define bZebra1_HSSIEnable 0x8 // Useless -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -//Zebra4 -#define bRTL8256RegModeCtrl1 0x100 // Useless -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -//RTL8258 -#define bRTL8258_TxLPFBW 0xc // Useless -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -// -// Other Definition -// - -//byte endable for sb_write -#define bByte0 0x1 // Useless -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -//for PutRegsetting & GetRegSetting BitMask -#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskH3Bytes 0xffffff00 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - -//for PutRFRegsetting & GetRFRegSetting BitMask -//#define bMask12Bits 0xfffff // RF Reg mask bits -//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF -#define bRFRegOffsetMask 0xfffff - -//#define bEnable 0x1 // Useless -//#define bDisable 0x0 - -#define LeftAntenna 0x0 // Useless -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 //500ms // Useless -#define tUpdateRxCounter 100 //100ms - -#define rateCCK 0 // Useless -#define rateOFDM 1 -#define rateHT 2 - -//define Register-End -#define bPMAC_End 0x1ff // Useless -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -//define max debug item in each debug page -//#define bMaxItem_FPGA_PHY0 0x9 -//#define bMaxItem_FPGA_PHY1 0x3 -//#define bMaxItem_PHY_11B 0x16 -//#define bMaxItem_OFDM_PHY0 0x29 -//#define bMaxItem_OFDM_PHY1 0x0 - -#define bPMACControl 0x0 // Useless -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 // Useless -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - -/*--------------------------Define Parameters-------------------------------*/ -#endif - -#endif //#ifndef WLAN_HAL_INTERNAL_USED - -#endif - + + + +#ifndef _8723B_REG_H_ +#define _8723B_REG_H_ + +#ifndef WLAN_HAL_INTERNAL_USED + + +//============================================================ +// 8188E Regsiter offset definition +//============================================================ + + +/* + * Project RTL8188E follows most of registers in Project RTL8192c + * This file includes additional registers for RTL8188E only + * Header file of RTL8192C registers should always be included + */ + +// +// 1. System Configure Register. (Offset 0x000 - 0x0FFh) +// +#define REG_8723B_BB_PAD_CTRL 0x64 +#define REG_8723B_HMEBOX_E0 0x88 +#define REG_8723B_HMEBOX_E1 0x8A +#define REG_8723B_HMEBOX_E2 0x8C +#define REG_8723B_HMEBOX_E3 0x8E +#define REG_8723B_WLLPS_CTRL 0x90 +#define REG_8723B_RPWM2 0x9E +#define REG_8723B_HIMR 0xB0 +#define REG_8723B_HISR 0xB4 +#define REG_8723B_HIMRE 0xB8 +#define REG_8723B_HISRE 0xBC +#define REG_8723B_EFUSE_DATA1 0xCC +#define REG_8723B_EFUSE_DATA0 0xCD +#define REG_8723B_EPPR 0xCF +#define REG_8723B_TXDMA_TH 0x218 +#define REG_8723B_LQ_TH 0x21C + +#define REG_8723B_WATCHDOG 0x368 + +#define REG_8723B_MACID_NOLINK 0x484 +#define REG_8723B_MACID_PAUSE 0x48C +#define REG_8723B_TXRPT_CTRL 0x4EC +#define REG_8723B_TXRPT_TIM 0x4F0 +#define REG_8723B_TXRPT_STSSET 0x4F2 +#define REG_8723B_TXRPT_STSVLD 0x4F4 +#define REG_8723B_TXRPT_STSINF 0x4F8 + + + +//============================================================ +// Registers for 8188E IQK +//============================================================ + + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B + +#define RF_WE_LUT 0xEF + + +//#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +//#define rFPGA0_XCD_SwitchControl 0x85c + +//#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +//#define rFPGA0_XCD_RFInterfaceSW 0x874 + +//#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +//#define rFPGA0_XCD_RFParameter 0x87c + +//#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +//#define rFPGA0_AnalogParameter2 0x884 +//#define rFPGA0_AnalogParameter3 0x888 +//#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy +//#define rFPGA0_AnalogParameter4 0x88c + +//#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +//#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +//#define rFPGA0_PSDReport 0x8b4 // Useless now +//#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +//#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +//#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + + +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SNC_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 + + +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 // HW Port 1 TSF Register +#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 +#define REG_NOA_DESC_SEL 0x05CF +#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_INTERVAL 0x05E4 +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC + + +#define REG_SYS_ISO_CTRL 0x0000 +//#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_9346CR 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS0_CTRL_6 0x0016 +#define REG_POWER_OFF_IN_PROCESS 0x0017 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +//#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +//#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +//#define REG_AFE_XTAL_CTRL 0x0024 +//#define REG_AFE_PLL_CTRL 0x0028 +#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_PWR_DATA 0x0038 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. +#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. +#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. +#define REG_GPIO_OUTPUT 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E +#define REG_XCK_OUT_CTRL 0x007c //RTL8188E +//#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 //RTL8188E +#define REG_MCUTSTCFG 0x0084 +#define REG_HMEBOX_EXT_0 0x0088 +#define REG_HMEBOX_EXT_1 0x008A +#define REG_HMEBOX_EXT_2 0x008C +#define REG_HMEBOX_EXT_3 0x008E +#define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform +#define REG_HIMR_8723B 0x00B0 //RTL8188E +#define REG_HISR_8723B 0x00B4 //RTL8188E +#define REG_HIMRE_8723B 0x00B8 //RTL8188E +#define REG_HISRE_8723B 0x00BC //RTL8188E +#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. +#define REG_TYPE_ID 0x00FC + +#define REG_32K_CTRL 0x0194 //RTL8188E + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + + +//============================================================================ +// 8188E Regsiter Bit and Content definition +//============================================================================ + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_BB_PAD_CTRL bits (Offset 0x64-66, 24 bits) +//---------------------------------------------------------------------------- +#define BB_PAD_CTRL_8723B_PAPE_EN BIT(19) // PAD ¡§P_LNAON¡¨ output enable +#define BB_PAD_CTRL_8723B_PAPE_DRV BIT(18) // PAD ¡§P_LNAON¡¨ output value +#define BB_PAD_CTRL_8723B_LNAON_SR BIT(17) // Control SR of PAD ¡§P_LNAON¡¨ to control the slew rate +#define BB_PAD_CTRL_8723B_LNAON_E2 BIT(16) // Control E2 of PAD ¡§P_LNAON¡¨ for its output driving capability +#define BB_PAD_CTRL_8723B_TRSW_EN BIT(11) // PAD ¡§P_TRSWP¡¨ and ¡§P_TRSWN¡¨ output enable +#define BB_PAD_CTRL_8723B_TRSW_DRV BIT(10) // PADs ¡§P_TRSWP¡¨ and ¡§P_TRSWN¡¨ outputs values + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_WLLPS_CTRL bits (Offset 0x90-93, 32 bits) +//---------------------------------------------------------------------------- +#define WLLPS_CTRL_8723B_EABM BIT(31) +#define WLLPS_CTRL_8723B_ACKF BIT(30) +#define WLLPS_CTRL_8723B_ESWR BIT(28) +#define WLLPS_CTRL_8723B_PWMM BIT(27) +#define WLLPS_CTRL_8723B_EECK BIT(26) +#define WLLPS_CTRL_8723B_ELDO BIT(25) +#define WLLPS_CTRL_8723B_EXTAL BIT(24) +#define WLLPS_CTRL_8723B_LPS_EN BIT(0) + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_HIMR bits (Offset 0xB0-B3, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8188E REG_8723B_HISR bits (Offset 0xB4-B7, 32 bits) +//---------------------------------------------------------------------------- +#define HIMR_8723B_TXCCK BIT(30) // TXRPT interrupt when CCX bit of the packet is set +#define HIMR_8723B_PSTIMEOUT BIT(29) // Power Save Time Out Interrupt +#define HIMR_8723B_GTINT4 BIT(28) // When GTIMER4 expires, this bit is set to 1 +#define HIMR_8723B_GTINT3 BIT(27) // When GTIMER3 expires, this bit is set to 1 +#define HIMR_8723B_TBDER BIT(26) // Transmit Beacon0 Error +#define HIMR_8723B_TBDOK BIT(25) // Transmit Beacon0 OK, ad hoc only +#define HIMR_8723B_TSF_BIT32_TOGGLE BIT(24) // TSF Timer BIT32 toggle indication interrupt +#define HIMR_8723B_BcnInt BIT(20) // Beacon DMA Interrupt 0 +#define HIMR_8723B_BDOK BIT(16) // Beacon Queue DMA OK0 +#define HIMR_8723B_HSISR_IND_ON_INT BIT(15) // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define HIMR_8723B_BCNDMAINT_E BIT(14) // Beacon DMA Interrupt Extension for Win7 +#define HIMR_8723B_ATIMEND BIT(12) // CTWidnow End or ATIM Window End +#define HIMR_8723B_HISR1_IND_INT BIT(11) // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) +#define HIMR_8723B_C2HCMD BIT(10) // CPU to Host Command INT Status, Write 1 clear +#define HIMR_8723B_CPWM2 BIT(9) // CPU power Mode exchange INT Status, Write 1 clear +#define HIMR_8723B_CPWM BIT(8) // CPU power Mode exchange INT Status, Write 1 clear +#define HIMR_8723B_HIGHDOK BIT(7) // High Queue DMA OK +#define HIMR_8723B_MGNTDOK BIT(6) // Management Queue DMA OK +#define HIMR_8723B_BKDOK BIT(5) // AC_BK DMA OK +#define HIMR_8723B_BEDOK BIT(4) // AC_BE DMA OK +#define HIMR_8723B_VIDOK BIT(3) // AC_VI DMA OK +#define HIMR_8723B_VODOK BIT(2) // AC_VO DMA OK +#define HIMR_8723B_RDU BIT(1) // Rx Descriptor Unavailable +#define HIMR_8723B_ROK BIT(0) // Receive DMA OK + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_HIMRE bits (Offset 0xB8-BB, 32 bits) +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// 8188E REG_8723B_HIMSE bits (Offset 0xBC-BF, 32 bits) +//---------------------------------------------------------------------------- +#define HIMRE_8723B_BCNDMAINT7 BIT(27) // Beacon DMA Interrupt 7 +#define HIMRE_8723B_BCNDMAINT6 BIT(26) // Beacon DMA Interrupt 6 +#define HIMRE_8723B_BCNDMAINT5 BIT(25) // Beacon DMA Interrupt 5 +#define HIMRE_8723B_BCNDMAINT4 BIT(24) // Beacon DMA Interrupt 4 +#define HIMRE_8723B_BCNDMAINT3 BIT(23) // Beacon DMA Interrupt 3 +#define HIMRE_8723B_BCNDMAINT2 BIT(22) // Beacon DMA Interrupt 2 +#define HIMRE_8723B_BCNDMAINT1 BIT(21) // Beacon DMA Interrupt 1 +#define HIMRE_8723B_BCNDOK7 BIT(20) // Beacon Queue DMA OK Interrup 7 +#define HIMRE_8723B_BCNDOK6 BIT(19) // Beacon Queue DMA OK Interrup 6 +#define HIMRE_8723B_BCNDOK5 BIT(18) // Beacon Queue DMA OK Interrup 5 +#define HIMRE_8723B_BCNDOK4 BIT(17) // Beacon Queue DMA OK Interrup 4 +#define HIMRE_8723B_BCNDOK3 BIT(16) // Beacon Queue DMA OK Interrup 3 +#define HIMRE_8723B_BCNDOK2 BIT(15) // Beacon Queue DMA OK Interrup 2 +#define HIMRE_8723B_BCNDOK1 BIT(14) // Beacon Queue DMA OK Interrup 1 +#define HIMRE_8723B_ATIMEND_E BIT(13) // ATIM Window End Extension for Win7 +#define HIMRE_8723B_TXERR BIT(11) // Tx Error Flag Interrupt Status, write 1 clear. +#define HIMRE_8723B_RXERR BIT(10) // Rx Error Flag INT Status, Write 1 clear +#define HIMRE_8723B_TXFOVW BIT(9) // Transmit FIFO Overflow +#define HIMRE_8723B_RXFOVW BIT(8) // Receive FIFO Overflow + + +//---------------------------------------------------------------------------- +// 8188E REG_EFUSE_ACCESS (Offset 0xCF, 8 bits) +//---------------------------------------------------------------------------- +#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. +#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_WATCHDOG bits (Offset 0x368-369, 16 bits) +//---------------------------------------------------------------------------- +#define WATCHDOG_8723B_ENABLE BIT(15) // Enable lbc timeout watchdog +#define WATCHDOG_8723B_R_IO_TIMEOUT_FLAG BIT(14) // Lbc timeout flag.Write ¡§1¡¨ to clear +#define WATCHDOG_8723B_RECORD_Mask 0x3FFF // Time out register address + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_TXRPT_CTRL bits (Offset 0x4EC-4EF, 32 bits) +//---------------------------------------------------------------------------- +#define TXRPT_CTRL_8723B_CNT_TH_SHIFT 16 +#define TXRPT_CTRL_8723B_CNT_TH_Mask 0xFFFF +#define TXRPT_CTRL_8723B_RPT_MACID_SHIFT 8 +#define TXRPT_CTRL_8723B_RPT_MACID_Mask 0x7F +#define TXRPT_CTRL_8723B_BCN_EN BIT(4) +#define TXRPT_CTRL_8723B_TXRPT_DIS BIT(3) +#define TXRPT_CTRL_8723B_CNT_OVER_EN BIT(2) +#define TXRPT_CTRL_8723B_TXRPT_TIM_EN BIT(1) +#define TXRPT_CTRL_8723B_TXRPT_EN BIT(0) + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_TXRPT_STSSET bits (Offset 0x4F2-4F3, 16 bits) +//---------------------------------------------------------------------------- +#define TXRPT_STSSET_8723B_TX_STS_SEL_SHIFT 11 +#define TXRPT_STSSET_8723B_TX_STS_SEL_Mask 0x1F +#define TXRPT_STSSET_8723B_TX_STS_CLR BIT(10) +#define TXRPT_STSSET_8723B_TX_STS_EN BIT(8) +#define TXRPT_STSSET_8723B_TX_STS_SET BIT(7) +#define TXRPT_STSSET_8723B_TX_STS_PORT BIT(6) +#define TXRPT_STSSET_8723B_TX_STS_SUBTPY_SHIFT 2 +#define TXRPT_STSSET_8723B_TX_STS_SUBTPY_Mask 0xF +#define TXRPT_STSSET_8723B_TX_STS_TPY_SHIFT 0 +#define TXRPT_STSSET_8723B_TX_STS_TPY_Mask 0x3 + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_TXRPT_STSVLD bits (Offset 0x4F4-4F6, 24 bits) +//---------------------------------------------------------------------------- +#define TXRPT_STSVLD_8723B_TX_TPY7_VLD BIT(23) +#define TXRPT_STSVLD_8723B_TX_TPY6_VLD BIT(22) +#define TXRPT_STSVLD_8723B_TX_TPY5_VLD BIT(21) +#define TXRPT_STSVLD_8723B_TX_TPY4_VLD BIT(20) +#define TXRPT_STSVLD_8723B_TX_TPY3_VLD BIT(19) +#define TXRPT_STSVLD_8723B_TX_TPY2_VLD BIT(18) +#define TXRPT_STSVLD_8723B_TX_TPY1_VLD BIT(17) +#define TXRPT_STSVLD_8723B_TX_TPY0_VLD BIT(16) +#define TXRPT_STSVLD_8723B_TX_BCN7_FAIL BIT(15) +#define TXRPT_STSVLD_8723B_TX_BCN6_FAIL BIT(14) +#define TXRPT_STSVLD_8723B_TX_BCN5_FAIL BIT(13) +#define TXRPT_STSVLD_8723B_TX_BCN4_FAIL BIT(12) +#define TXRPT_STSVLD_8723B_TX_BCN3_FAIL BIT(11) +#define TXRPT_STSVLD_8723B_TX_BCN2_FAIL BIT(10) +#define TXRPT_STSVLD_8723B_TX_BCN1_FAIL BIT(9) +#define TXRPT_STSVLD_8723B_TX_BCN0_FAIL BIT(8) +#define TXRPT_STSVLD_8723B_TX_BCN7_OK BIT(7) +#define TXRPT_STSVLD_8723B_TX_BCN6_OK BIT(6) +#define TXRPT_STSVLD_8723B_TX_BCN5_OK BIT(5) +#define TXRPT_STSVLD_8723B_TX_BCN4_OK BIT(4) +#define TXRPT_STSVLD_8723B_TX_BCN3_OK BIT(3) +#define TXRPT_STSVLD_8723B_TX_BCN2_OK BIT(2) +#define TXRPT_STSVLD_8723B_TX_BCN1_OK BIT(1) +#define TXRPT_STSVLD_8723B_TX_BCN0_OK BIT(0) + + +//---------------------------------------------------------------------------- +// 8188E REG_8723B_TX_STS_INF bits (Offset 0x4F8-4F9, 16 bits) +//---------------------------------------------------------------------------- +#define TX_STS_INF_8723B_TX_STS_INF_EN BIT(8) +#define TX_STS_INF_8723B_TX_STS_SET_INF BIT(7) +#define TX_STS_INF_8723B_TX_STS_PORT_INF BIT(6) +#define TX_STS_INF_8723B_TX_STS_SUBTPY_INF_SHIFT 2 +#define TX_STS_INF_8723B_TX_STS_SUBTPY_INF_Mask 0xF +#define TX_STS_INF_8723B_TX_STS_TPY_INF_SHIFT 0 +#define TX_STS_INF_8723B_TX_STS_TPY_INF_Mask 0x3 + + +//---------------------------------------------------------------------------- +// 8192C EEPROM/EFUSE share register definition. +//---------------------------------------------------------------------------- + +//==================================================== +// EEPROM/Efuse PG Offset for 88EE/88EU/88ES +//==================================================== +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CUSTOMERID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 + +// RTL8723B +#define EEPROM_MAC_ADDR_8723B 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +#if 0 +//RTL88EU +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 + +// RTL88ES +#define EEPROM_MAC_ADDR_88ES 0x11A +#endif + +//----------------------------------------------------- +// +// RTL8188E SDIO Configuration +// +//----------------------------------------------------- + +// I/O bus domain address mapping +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define RX_RX0FF_BASE 0x10340000 + +// SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] +#define WLAN_RX0FF_MSK 0x0003 + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +// SDIO Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ +#define SDIO_MAX_RX_QUEUE 1 + +#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control +#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask +#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine +#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode +#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SDIO_REG_OQT_FREE_SPACE 0x0025 // OQT Free Space +#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control +#define SDIO_REG_HIMR_ON 0x0090 // SDIO Host Extension Interrupt Mask Always +#define SDIO_REG_HISR_ON 0x0091 // SDIO Host Extension Interrupt Status Always + +#define SDIO_HIMR_DISABLED 0 + +// RTL8188E SDIO Host Interrupt Mask Register +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +// SDIO Host Interrupt Service Routine +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIMEOUT BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + +#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ + SDIO_HISR_RXERR |\ + SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW |\ + SDIO_HISR_TXBCNOK |\ + SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD |\ + SDIO_HISR_CPWM1 |\ + SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND |\ + SDIO_HISR_GTINT3_IND |\ + SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT |\ + SDIO_HISR_OCPINT) + +// SDIO HCI Suspend Control Register +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + +// SDIO Tx FIFO related +#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page +#define SDIO_TX_FIFO_PAGE_SZ 128 + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- + +//2 Special Option +// 0; Use interrupt endpoint to upload interrupt pkt +// 1; Use bulk endpoint to upload interrupt pkt, +#define INT_BULK_SEL BIT(4) + +//======================================================== +// General definitions +//======================================================== + +#define LAST_ENTRY_OF_TX_PKT_BUFFER_88E 176 // 22k 22528 bytes + +#ifdef USE_OUT_SRC + + +/*--------------------------Define Parameters-------------------------------*/ + + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +// +// 2. Page2(0x200) +// +// The following two definition are only used for USB interface. +#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. +#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rPdp_AntA_8 0xb08 +#define rPdp_AntA_C 0xb0c +#define rPdp_AntA_10 0xb10 +#define rPdp_AntA_14 0xb14 +#define rPdp_AntA_18 0xb18 +#define rPdp_AntA_1C 0xb1c +#define rPdp_AntA_20 0xb20 +#define rPdp_AntA_24 0xb24 + +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_ram64x16 0xb2c + +#define rBndA 0xb30 +#define rHssiPar 0xb34 + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rPdp_AntB_8 0xb78 +#define rPdp_AntB_C 0xb7c +#define rPdp_AntB_10 0xb80 +#define rPdp_AntB_14 0xb84 +#define rPdp_AntB_18 0xb88 +#define rPdp_AntB_1C 0xb8c +#define rPdp_AntB_20 0xb90 +#define rPdp_AntB_24 0xb94 + +#define rConfig_Pmpd_AntB 0xb98 + +#define rBndB 0xba0 + +#define rAPK 0xbd8 +#define rPm_Rx0_AntA 0xbdc +#define rPm_Rx1_AntA 0xbe0 +#define rPm_Rx2_AntA 0xbe4 +#define rPm_Rx3_AntA 0xbe8 +#define rPm_Rx0_AntB 0xbec +#define rPm_Rx1_AntB 0xbf0 +#define rPm_Rx2_AntB 0xbf4 +#define rPm_Rx3_AntB 0xbf8 + + + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support + +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 // RF channel switch + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_IPA_G 0x09 // +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C // +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 // +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +//#if HARDWARE_TYPE_IS_RTL8192D == 1 +#define RF_T_METER_92D 0x42 // +#define RF_T_METER_88E 0x42 // +//#else +#define RF_T_METER 0x24 // +//#endif + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 // T65 RF + +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal + +#define bLSSIReadBackData 0xfffff // T65 RF + +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//7. RF Register +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// + +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskH3Bytes 0xffffff00 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + +//for PutRFRegsetting & GetRFRegSetting BitMask +//#define bMask12Bits 0xfffff // RF Reg mask bits +//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF +#define bRFRegOffsetMask 0xfffff + +//#define bEnable 0x1 // Useless +//#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +/*--------------------------Define Parameters-------------------------------*/ +#endif + +#endif //#ifndef WLAN_HAL_INTERNAL_USED + +#endif + diff --git a/package/kernel/rtl8192cd/8812_hw.c b/package/kernel/rtl8192cd/8812_hw.c old mode 100755 new mode 100644 index b8f5e785fee..e2e6aacd26d --- a/package/kernel/rtl8192cd/8812_hw.c +++ b/package/kernel/rtl8192cd/8812_hw.c @@ -1,3801 +1,3801 @@ - -#define _8812_HW_C_ - -#include "8192cd.h" -#include "8192cd_cfg.h" -#include "8192cd_util.h" - -#include "8192c_reg.h" -#include "8812_reg.h" -#include "8812_vht_gen.h" - -#ifdef __KERNEL__ -#include -#endif -//eric_8812 #include "8192cd_debug.h" -#include "8192cd_headers.h" - - - -#if defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_8723B_SUPPORT) -typedef struct _C2H_EVT_HDR{ - u1Byte CmdID: 4; - u1Byte CmdLen: 4; - u1Byte CmdSeq; -}C2H_EVT_HDR, *PC2H_EVT_HDR; - -typedef enum _RTL8812_C2H_EVT -{ - C2H_8812_DBG = 0, - C2H_8812_LB = 1, - C2H_8812_TXBF = 2, - CCXRPT = 3, - C2H_8812_TXPERORT = 4, - C2H_8812_RA_RPT = 12, -#ifdef TXRETRY_CNT - C2H_8812_TXRETRY = 13, //0x0D -#endif - C2H_8812_RA_PARA_RPT=14, - C2H_8812_EXTEND_IND = 0xFF, - MAX_8812_C2HEVENT -}RTL8812_C2H_EVT; - -typedef enum _RTL8812_EXTEND_C2H_EVT -{ - EXTEND_C2H_8812_DBG_PRINT = 0 - -}RTL8812_EXTEND_C2H_EVT; - -void UpdateBBRFVal8812(struct rtl8192cd_priv *priv, unsigned char channel) -{ - unsigned char current_is_5g = 0, switch_bw = 0; - unsigned char bTmp = 0; - unsigned int dwTmp = 0; - unsigned int tmp_cb0=0, tmp_eb0 = 0; //for_8812_mp_chip - unsigned int eRFPath, curMaxRFPath; - - curMaxRFPath = RF92CD_PATH_MAX; - - //check CCK_CHECK_en BIT7 - if ( RTL_R8(0x454) & BIT(7) ) - current_is_5g = 1; - else - current_is_5g = 0; - - if (((channel > 14) && (current_is_5g == 0)) || ((channel <= 14) && (current_is_5g == 1))) - switch_bw = 1; - - //printk("\n\n eric-current_is_5g = %d switch_bw = %d pre= %d\n\n", current_is_5g, switch_bw, priv->pshare->pre_channel); - - if (channel > 14 && (switch_bw || (priv->pshare->pre_channel == 0))) //2.4G to 5G - RTL_W8(0x454, (RTL_R8(0x454) | BIT(7))); - - //Set fc_area 0x860 - dwTmp = RTL_R32(0x860); - dwTmp &= ~(BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28)); - - if (channel <= 14) - dwTmp |= (0x96a << 17); - else if (channel <= 48) - dwTmp |= (0x494 << 17); - else if (channel <= 64) - dwTmp |= (0x453 << 17); - else if (channel <= 116) - dwTmp |= (0x452 << 17); - else if (channel <= 177) - dwTmp |= (0x412 << 17); - - RTL_W32(0x860, dwTmp); - - //Set RF MOD AG rf_0x18 - for (eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - dwTmp = PHY_QueryRFReg(priv, eRFPath, rRfChannel, bMask20Bits, 1); - dwTmp &= ~(BIT(8) | BIT(9) | BIT(16) | BIT(17) | BIT(18)); - - if (channel <= 14) - dwTmp |= 0x0; - else if (channel <= 64) - dwTmp |= (BIT(8) | BIT(16)); - else if (channel <= 140) - dwTmp |= (BIT(8) | BIT(16) | BIT(17)); - else - dwTmp |= (BIT(8) | BIT(16) | BIT(18)); - - PHY_SetRFReg(priv, eRFPath, rRfChannel, bMask20Bits, dwTmp); - } - - //Set BB registers //for_8812_mp_chip - if (switch_bw) { - if (!IS_TEST_CHIP(priv)) { - tmp_cb0 = RTL_R32(0xcb0); - tmp_cb0 &= ~(BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23)); - tmp_eb0 = RTL_R32(0xeb0); - tmp_eb0 &= ~(BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23)); - } - - if (!current_is_5g) { - bTmp = RTL_R8(0x82c); - bTmp &= ~(BIT(0) | BIT(1)); - bTmp |= BIT(0); - RTL_W8(0x82c, bTmp); - if (GET_CHIP_VER(priv) == VERSION_8881A) { - PHY_SetBBReg(priv, 0xcb0, 0xff, 0x55); - PHY_SetBBReg(priv, 0xcb0, 0xf000, 0x1); - } else { - if (IS_TEST_CHIP(priv)) { - RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(12)); - RTL_W32(0xeb8, RTL_R32(0xcb8) | BIT(12)); - RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(15))); - RTL_W32(0xeb8, RTL_R32(0xeb8) & (~BIT(15))); - } else { -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) - { - #if 0 - if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501) { - RTL_W32(0xcb0, tmp_cb0 | (0x53 << 16)); - RTL_W32(0xeb0, tmp_eb0 | (0x53 << 16)); - } else { - RTL_W32(0xcb0, tmp_cb0 | (0x54 << 16)); - RTL_W32(0xeb0, tmp_eb0 | (0x54 << 16)); - } - #else - //For 8812 PHY_PARAMETER after V40. - RTL_W32(0xcb0, 0x77337717); - RTL_W32(0xeb0, 0x77337717); - - if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501 || priv->pmib->dot11RFEntry.pa_type == PA_SKYWORKS_85712_HP) { - PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x00); - PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x00); - } else { - PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x10); - PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x10); - } - #endif - } else -#endif - { -#ifdef CONFIG_PA_RTC5634 - // internal PA+PAPE - if (priv->pmib->dot11RFEntry.pa_type == PA_RTC5634) { - //panic_printk("Set PAPE on\n"); - RTL_W32(0xcb0, 0x77537717); - RTL_W32(0xeb0, 0x77537717); - } -#endif - } - } - } -// RTL_W32(0x808, RTL_R32(0x808) & (~BIT(28))); - RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); - RTL_W8(0xa07, RTL_R8(0xa07) | 0xf); - RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); - PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x15); - } else { - bTmp = RTL_R8(0x82c); - bTmp &= ~(BIT(0) | BIT(1)); - RTL_W8(0x82c, bTmp); - - if (IS_TEST_CHIP(priv)) { - RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(12))); - RTL_W32(0xeb8, RTL_R32(0xcb8) & (~BIT(12))); - RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(15)); - RTL_W32(0xeb8, RTL_R32(0xeb8) | BIT(15)); - } else { - //RTL_W32(0xcb0, tmp_cb0 | (0x77 << 16)); - //RTL_W32(0xeb0, tmp_eb0 | (0x77 << 16)); - RTL_W32(0xcb0, 0x77777777); - RTL_W32(0xeb0, 0x77777777); - } - - RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); - RTL_W8(0xa07, (RTL_R8(0xa07) & 0xf0)|0x01); - RTL_W32(0x8c0, RTL_R32(0x8c0) | BIT(17)); - PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x17); - } - } else if (priv->pshare->pre_channel == 0) { //first launch - if (channel > 14) { - bTmp = RTL_R8(0x82c); - bTmp &= ~(BIT(0) | BIT(1)); - bTmp |= BIT(0); - RTL_W8(0x82c, bTmp); - - if (IS_TEST_CHIP(priv)) { - RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(12)); - RTL_W32(0xeb8, RTL_R32(0xcb8) | BIT(12)); - RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(15))); - RTL_W32(0xeb8, RTL_R32(0xeb8) & (~BIT(15))); - } else { -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) - { - #if 0 - if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501) { - RTL_W32(0xcb0, tmp_cb0 | (0x53 << 16)); - RTL_W32(0xeb0, tmp_eb0 | (0x53 << 16)); - } else { - RTL_W32(0xcb0, tmp_cb0 | (0x54 << 16)); - RTL_W32(0xeb0, tmp_eb0 | (0x54 << 16)); - } - #else - //For 8812 PHY_PARAMETER after V40. - RTL_W32(0xcb0, 0x77337717); - RTL_W32(0xeb0, 0x77337717); - - if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501 || priv->pmib->dot11RFEntry.pa_type == PA_SKYWORKS_85712_HP) { - PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x00); - PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x00); - } else { - PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x10); - PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x10); - } - #endif - } else -#endif - { -#ifdef CONFIG_PA_RTC5634 - // internal PA+PAPE - if (priv->pmib->dot11RFEntry.pa_type == PA_RTC5634) { - //panic_printk("Set PAPE on\n"); - RTL_W32(0xcb0, 0x77537717); - RTL_W32(0xeb0, 0x77537717); - } -#endif - } - } -// RTL_W32(0x808, RTL_R32(0x808) & (~BIT(28))); - RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); - RTL_W8(0xa07, RTL_R8(0xa07) | 0xf); - RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); - PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x15); - } else { - bTmp = RTL_R8(0x82c); - bTmp &= ~(BIT(0) | BIT(1)); - RTL_W8(0x82c, bTmp); - if (GET_CHIP_VER(priv) == VERSION_8881A) { - PHY_SetBBReg(priv, 0xcb0, 0xff, 0x00); - PHY_SetBBReg(priv, 0xcb0, 0xf000, 0x0); - } else { - - if (IS_TEST_CHIP(priv)) { - RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(12))); - RTL_W32(0xeb8, RTL_R32(0xcb8) & (~BIT(12))); - RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(15)); - RTL_W32(0xeb8, RTL_R32(0xeb8) | BIT(15)); - } else { - //RTL_W32(0xcb0, tmp_cb0 | (0x77 << 16)); - //RTL_W32(0xeb0, tmp_eb0 | (0x77 << 16)); - RTL_W32(0xcb0, 0x77777777); - RTL_W32(0xeb0, 0x77777777); - } - } - RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); - RTL_W32(0x8c0, RTL_R32(0x8c0) | BIT(17)); - PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x17); - } - } - - if (channel <= 14 && (switch_bw || (priv->pshare->pre_channel == 0))) - RTL_W8(0x454, (RTL_R8(0x454) & ~(BIT(7)))); - -#ifdef AC2G_256QAM - if(is_ac2g(priv)) - { - RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); //enable tx vht rates - } -#endif - SpurCheck8812(priv, 1, channel, 0); - - priv->pshare->pre_channel = channel; - -} - - -/* 8812 2.4G spur at 2480MHz */ -void SpurCheck8812(struct rtl8192cd_priv *priv, unsigned char ch_bw, unsigned char channel, unsigned int bandwidth) -{ - unsigned int dwTmp = 0; - unsigned char primary_channel = 0; -#ifdef RTK_AC_SUPPORT - if(ch_bw == 1 && (GET_CHIP_VER(priv) != VERSION_8723B)){ /* if switch channel */ - if((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40 && (channel == 11 || channel == 12)) || - (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20 && (channel == 13 || channel == 14))){ - RTL_W32(0x8ac,0x0ff0ff04); - RTL_W32(0X8c4,0x40000000); - if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40){ - dwTmp = RTL_R32(0x8ac); - dwTmp |= BIT(0); - RTL_W32(0x8ac, dwTmp); - } - }else if((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40 && (priv->pshare->pre_channel == 11 || priv->pshare->pre_channel == 12)) || - (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20 && (priv->pshare->pre_channel == 13 || priv->pshare->pre_channel == 14))){ - - /* Restore 0x8ac, 0x8c4*/ - PHY_SetBBReg(priv, 0x8ac, BIT(10), 0); - RTL_W32(0X8c4,0); - primary_channel = priv->pshare->txsc_20; - dwTmp = RTL_R32(0x8ac); - dwTmp &= ~(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(20) | BIT(21)); - - switch (priv->pshare->CurrentChannelBW) { - case HT_CHANNEL_WIDTH_AC_5: - dwTmp |= (BIT(6) | BIT(20)); - RTL_W32(0x8ac, dwTmp); - break; - case HT_CHANNEL_WIDTH_AC_10: - dwTmp |= (BIT(7) | BIT(8) | BIT(21)); - RTL_W32(0x8ac, dwTmp); - break; - case HT_CHANNEL_WIDTH_AC_20: - dwTmp |= (BIT(9) | BIT(20) | BIT(21)); - RTL_W32(0x8ac, dwTmp); - break; - case HT_CHANNEL_WIDTH_AC_40: - dwTmp |= (BIT(0) | BIT(9) | BIT(20) | BIT(21)); - RTL_W32(0x8ac, dwTmp); - break; - } - if (IS_C_CUT_8812(priv)) { - switch (priv->pshare->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_AC_5: - PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_10: - PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_20: - PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_40: - PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); - break; - } - } - - dwTmp = RTL_R32(0x8ac); - dwTmp &= ~(BIT(2)|BIT(3)|BIT(4)|BIT(5)); - - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - break; - case HT_CHANNEL_WIDTH_AC_40: - dwTmp |= (primary_channel << 2); - RTL_W32(0x8ac, dwTmp); - break; - } - } - }else if(ch_bw == 0){ /* if switch bandwidth */ - if((bandwidth == HT_CHANNEL_WIDTH_AC_20 && (priv->pmib->dot11RFEntry.dot11channel == 13 || priv->pmib->dot11RFEntry.dot11channel == 14)) || - (bandwidth == HT_CHANNEL_WIDTH_AC_40 && (priv->pmib->dot11RFEntry.dot11channel == 11 || priv->pmib->dot11RFEntry.dot11channel == 12)) - ){ - RTL_W32(0x8ac,0x0ff0ff04); - RTL_W32(0X8c4,0x40000000); - if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40){ - dwTmp = RTL_R32(0x8ac); - dwTmp |= BIT(0); - RTL_W32(0x8ac, dwTmp); - } - } - } -#endif -} - - -signed char convert_diff(signed char value) -{ - // range from -8 ~ 7 - if (value <= 7) - return value; - else - return (value - 16); -} - -void Write_OFDM_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, writeVal); - RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, writeVal); -} - -void Write_1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); - RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); - RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); - writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_HT1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); - RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); -} - -void Write_HT2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); - RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); -} - -void Write_VHT1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_VHT2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); - RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); - writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); -} -void Write_OFDM_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, writeVal); - RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, writeVal); -} - - -void Write_1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); - RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); - RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); - writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_HT1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); - RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); -} - -void Write_HT2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); - RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); -} - -void Write_VHT1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void Write_VHT2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) -{ - RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); - RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); - writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); -} - -void use_DefaultOFDMTxPower_8812(struct rtl8192cd_priv *priv) -{ - - unsigned int def_power = 0x20202020;//0x12121212; - //printk("NO Calibration data, use default OFDM power = 0x%x\n", def_power); - priv->pshare->rf_ft_var.bcn_pwr_idex= def_power & 0x3f; - - RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, def_power); - RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, def_power); - RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, def_power); - RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, def_power); - RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, def_power); - RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, def_power); - RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, def_power); - RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, def_power); - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, def_power); - RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, def_power); - RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, def_power); - - RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, def_power); - RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, def_power); - RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, def_power); - RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, def_power); - RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, def_power); - RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, def_power); - RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, def_power); - RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, def_power); - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, def_power); - RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, def_power); - RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, def_power); - -} - - -void Cal_OFDMTxPower_5G(struct rtl8192cd_priv *priv, unsigned char ch_idx) -{ - unsigned char tmp_TPI = 0; - unsigned char pwr_40_1s = 0, pwr_80_1s = 0; - signed char diff_ofdm_1t = 0; - signed char diff_bw40_2s = 0; - signed char diff_bw20_1s = 0; - signed char diff_bw20_2s = 0; - signed char diff_bw80_1s = 0; - signed char diff_bw80_2s = 0; - - unsigned int writeVal = 0; - unsigned char ch_idx_vht80 = get_center_channel(priv, priv->pmib->dot11RFEntry.dot11channel, priv->pmib->dot11nConfigEntry.dot11n2ndChOffset, 1) -1; - unsigned char ch_idx_ht40 = ((priv->pmib->dot11nConfigEntry.dot11n2ndChOffset==HT_2NDCH_OFFSET_BELOW) ? (priv->pmib->dot11RFEntry.dot11channel-2) : (priv->pmib->dot11RFEntry.dot11channel+2)) - 1; -#ifdef POWER_PERCENT_ADJUSTMENT - signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); -#endif - - // PATH A, OFDM - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx] & 0x0f); - diff_ofdm_1t = convert_diff(diff_ofdm_1t); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_A(priv, writeVal); - - //printk("Write_OFDM_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_ofdm_1t); - - - // PATH B, OFDM - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx] & 0x0f); - diff_ofdm_1t = convert_diff(diff_ofdm_1t); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_B(priv, writeVal); - - //printk("Write_OFDM_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_ofdm_1t); - - - if (priv->pshare->CurrentChannelBW == 0) { - //PATH A, BW20-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx] & 0xf0) >> 4); - diff_bw20_1s = convert_diff(diff_bw20_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_1S_A(priv, writeVal); - - //printk("Write_1S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw20_1s); - - - //PATH A, BW20-2S - diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx] & 0x0f); - diff_bw20_2s = convert_diff(diff_bw20_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_2S_A(priv, writeVal); - - //printk("Write_2S_A %d = %d + %d + %d\n", tmp_TPI, pwr_40_1s , diff_bw20_1s, diff_bw20_2s); - - // ==== // - - //PATH B, BW20-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx] & 0xf0) >> 4); - diff_bw20_1s = convert_diff(diff_bw20_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_1S_B(priv, writeVal); - - //printk("Write_1S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw20_1s); - - //PATH B, BW20-2S - diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx] & 0x0f); - diff_bw20_2s = convert_diff(diff_bw20_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_2S_B(priv, writeVal); - - //printk("Write_2S_B %d = %d + %d + %d\n", tmp_TPI, pwr_40_1s , diff_bw20_1s, diff_bw20_2s); - - } else if (priv->pshare->CurrentChannelBW == 1) { - //PATH A, BW40-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_1S_A(priv, writeVal); - - //printk("Write_1S_A %d = %d \n", tmp_TPI, pwr_40_1s); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx_ht40] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_2S_A(priv, writeVal); - - //printk("Write_2S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); - - // ==== // - - //PATH B, BW40-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_1S_B(priv, writeVal); - - //printk("Write_1S_B %d = %d \n", tmp_TPI, pwr_40_1s); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx_ht40] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_2S_B(priv, writeVal); - - //printk("Write_2S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); - - } else if (priv->pshare->CurrentChannelBW == 2) { - - //PATH A, BW40-1S - //printk("ch_idx_ht40 %d >>> [0x%x 0x%x]\n", ch_idx_ht40, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40], priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]); - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_A(priv, writeVal); - - //printk("Write_HT1S_A 0x%x = 0x%x\n", tmp_TPI, pwr_40_1s); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx_ht40] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_A(priv, writeVal); - - //printk("Write_HT2S_A 0x%x = 0x%x + 0x%x \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); - - // ==== // - - //PATH B, BW40-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_B(priv, writeVal); - - //printk("Write_1S_B %d = %d \n", tmp_TPI, pwr_40_1s); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx_ht40] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_B(priv, writeVal); - - - //PATH A, BW80-1S - pwr_80_1s = (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_vht80 - 4] + - priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_vht80 + 4]) / 2 ; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_80_1s = POWER_RANGE_CHECK(pwr_80_1s + pwrdiff_percent); -#endif - diff_bw80_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_A[ch_idx_vht80] & 0xf0) >> 4); - diff_bw80_1s = convert_diff(diff_bw80_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_80_1s + diff_bw80_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_VHT1S_A(priv, writeVal); - - //printk("Write_1S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s); - - - //PATH A, BW80-2S - diff_bw80_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_A[ch_idx_vht80] & 0xf0) >> 4); - diff_bw80_2s = convert_diff(diff_bw80_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_80_1s + diff_bw80_1s + diff_bw80_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_VHT2S_A(priv, writeVal); - - //printk("Write_2S_A %d = %d + %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s, diff_bw80_1s); - - - //PATH B, BW80-1S - pwr_40_1s = (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_vht80 - 4] + - priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_vht80 + 4]) / 2 ; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_bw80_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_B[ch_idx_vht80] & 0xf0) >> 4); - diff_bw80_1s = convert_diff(diff_bw80_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw80_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_VHT1S_B(priv, writeVal); - - //printk("Write_1S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s); - - - //PATH B, BW80-2S - diff_bw80_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_B[ch_idx_vht80] & 0xf0) >> 4); - diff_bw80_2s = convert_diff(diff_bw80_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw80_1s + diff_bw80_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_VHT2S_B(priv, writeVal); - - //printk("Write_2S_B %d = %d + %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s, diff_bw80_1s); - - } -} - -void Cal_OFDMTxPower_2G(struct rtl8192cd_priv *priv, unsigned char ch_idx) -{ - unsigned char tmp_TPI = 0; - unsigned char pwr_40_1s = 0; - signed char diff_ofdm_1t = 0; - signed char diff_bw40_2s = 0; - signed char diff_bw20_1s = 0; - signed char diff_bw20_2s = 0; - - unsigned int writeVal = 0; - //unsigned char ch_idx_ht20 = priv->pmib->dot11RFEntry.dot11channel -1; - -#ifdef POWER_PERCENT_ADJUSTMENT - signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); -#endif - - // PATH A, OFDM - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_A[ch_idx] & 0x0f); - diff_ofdm_1t = convert_diff(diff_ofdm_1t); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_A(priv, writeVal); - - - // PATH B, OFDM - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_B[ch_idx] & 0x0f); - diff_ofdm_1t = convert_diff(diff_ofdm_1t); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_B(priv, writeVal); - - if (priv->pshare->CurrentChannelBW == 0) { - //PATH A, BW20-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_A[ch_idx] & 0xf0) >> 4); - diff_bw20_1s = convert_diff(diff_bw20_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_A(priv, writeVal); - - - //PATH A, BW20-2S - diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx] & 0x0f); - diff_bw20_2s = convert_diff(diff_bw20_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_A(priv, writeVal); - - // ==== // - - //PATH B, BW20-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_B[ch_idx] & 0xf0) >> 4); - diff_bw20_1s = convert_diff(diff_bw20_1s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_B(priv, writeVal); - - //PATH B, BW20-2S - diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx] & 0x0f); - diff_bw20_2s = convert_diff(diff_bw20_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_B(priv, writeVal); - - } else if (priv->pshare->CurrentChannelBW == 1) { - //PATH A, BW40-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_A(priv, writeVal); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_A(priv, writeVal); - - // ==== // - - //PATH B, BW40-1S - pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); -#endif - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT1S_B(priv, writeVal); - - - //PATH A, BW40-2S - diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx] & 0xf0) >> 4); - diff_bw40_2s = convert_diff(diff_bw40_2s); - tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_HT2S_B(priv, writeVal); - - } -} -#ifdef TX_PG_8812 -void get_tx_pwr(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, - unsigned char *tmp_b3, unsigned char *tmp_b4) -{ - *tmp_b1 = (tmp_dw & (0xff)); - *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); - *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); - *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); -} - -void TxPG_CCK_8812(struct rtl8192cd_priv *priv) -{ - unsigned char b1, b2, b3, b4; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned int tmp_dw = 0; - unsigned int writeVal = 0; - - tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->CCKTxAgc_A[3])); - *tmp_b2 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->CCKTxAgc_A[2])); - *tmp_b3 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->CCKTxAgc_A[1])); - *tmp_b4 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->CCKTxAgc_A[0])); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, writeVal); - - tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->CCKTxAgc_B[3])); - *tmp_b2 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->CCKTxAgc_B[2])); - *tmp_b3 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->CCKTxAgc_B[1])); - *tmp_b4 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->CCKTxAgc_B[0])); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, writeVal); -} - - -void TxPG_OFDM_8812_A(struct rtl8192cd_priv *priv) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 =0; - unsigned int writeVal = 0; - - //printk("TxPG_OFDM_8812_A!!\n"); - tmp_dw = RTL_R32(rTxAGC_A_Ofdm18_Ofdm6_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_A[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_A[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_A[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_A[0]); - if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_max) - *tmp_b1 = priv->pshare->rf_ft_var.bcn_pwr_max; - priv->pshare->rf_ft_var.bcn_pwr_idex= *tmp_b1; - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_Ofdm54_Ofdm24_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_A[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_A[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_A[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_MCS3_MCS0_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_MCS7_MCS4_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_MCS11_MCS8_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[11]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[10]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[9]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_MCS15_MCS12_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[15]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[14]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[13]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); - - tmp_dw = RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar); - tmp_dw1= RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); - get_tx_pwr(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_A[11]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_A[10]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[9]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); - - tmp_dw = RTL_R32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[15]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[14]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[13]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); - - tmp_dw = RTL_R32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[19]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[18]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 - priv->pshare->phw->VHTTxAgcOffset_A[17]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 - priv->pshare->phw->VHTTxAgcOffset_A[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); -} - - -void TxPG_OFDM_8812_B(struct rtl8192cd_priv *priv) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 =0; - unsigned int writeVal = 0; - - //printk("TxPG_OFDM_8812_B!!\n"); - tmp_dw = RTL_R32(rTxAGC_B_Ofdm18_Ofdm6_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_B[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_B[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_B[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_B[0]); - if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_max) - *tmp_b1 = priv->pshare->rf_ft_var.bcn_pwr_max; - if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_idex) - priv->pshare->rf_ft_var.bcn_pwr_idex= *tmp_b1; - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Ofdm54_Ofdm24_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_B[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_B[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_B[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_MCS3_MCS0_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_MCS7_MCS4_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_MCS11_MCS8_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[11]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[10]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[9]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_MCS15_MCS12_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[15]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[14]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[13]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[3]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[2]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[1]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[7]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[6]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[5]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar); - tmp_dw1= RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); - get_tx_pwr(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_B[11]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_B[10]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[9]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[15]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[14]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[13]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); - tmp_dw = RTL_R32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar); - get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[19]); - *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[18]); - *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 - priv->pshare->phw->VHTTxAgcOffset_B[17]); - *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 - priv->pshare->phw->VHTTxAgcOffset_B[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); -} -#endif - - -#ifdef TXPWR_LMT_8812 - -unsigned char get_byte_from_dw(unsigned int tmp_dw, unsigned char byte_num) -{ - - if (byte_num == 0) - return (tmp_dw & (0xff)); - else if (byte_num == 1) - return ((tmp_dw & (0xff00)) >> 8); - else if (byte_num == 2) - return ((tmp_dw & (0xff0000)) >> 16); - else if (byte_num == 3) - return ((tmp_dw & (0xff000000)) >> 24); - else - return 0; -} - -unsigned int assign_lmt_reg_value(struct rtl8192cd_priv *priv, unsigned int reg_offset, unsigned char max_idx, unsigned char max_idx2) -{ - - unsigned int tmp_dw; - unsigned char reg_val[4]; - unsigned char i=0; - - tmp_dw = RTL_R32(reg_offset); - - //printk("[0x%03x] 0x%08x >> ", reg_offset, tmp_dw); - - get_tx_pwr(tmp_dw, (unsigned char *)®_val[0], (unsigned char *)®_val[1], - (unsigned char *)®_val[2], (unsigned char *)®_val[3]); - - if((reg_offset == rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) || - (reg_offset == rTxAGC_B_Nss2Index1_Nss1Index8_JAguar)) - { - reg_val[0] = POWER_MIN_CHECK(reg_val[0], max_idx); - reg_val[1] = POWER_MIN_CHECK(reg_val[1], max_idx); - reg_val[2] = POWER_MIN_CHECK(reg_val[2], max_idx2); - reg_val[3] = POWER_MIN_CHECK(reg_val[3], max_idx2); - } - else - { - for(i=0; i<4; i++) - { - reg_val[i] = POWER_MIN_CHECK(reg_val[i], max_idx); - } - } - - for(i=0; i<4; i++) - { - reg_val[i] = POWER_RANGE_CHECK(reg_val[i]); - } - - tmp_dw = (reg_val[3] << 24) | (reg_val[2] << 16) | (reg_val[1] << 8) | reg_val[0]; - - //printk("0x%08x\n", tmp_dw); - - RTL_W32(reg_offset, tmp_dw); - -} - -unsigned char check_lmt_valid(struct rtl8192cd_priv *priv, unsigned char phy_band) -{ - unsigned char lmt_valid = 1; - - if(phy_band == PHY_BAND_2G) - if(priv->pshare->txpwr_lmt_CCK == 0) - lmt_valid = 0; - - if(priv->pshare->txpwr_lmt_OFDM == 0) - lmt_valid = 0; - - if(priv->pshare->txpwr_lmt_HT1S == 0) - lmt_valid = 0; - - if(priv->pshare->txpwr_lmt_HT2S == 0) - lmt_valid = 0; - - if(phy_band == PHY_BAND_5G) - { - if(priv->pshare->txpwr_lmt_VHT1S == 0) - lmt_valid = 0; - - if(priv->pshare->txpwr_lmt_VHT2S == 0) - lmt_valid = 0; - } - - if(lmt_valid == 0) - DEBUG_WARN("NO Limit Value, NO limit TX POWER !!!\n limit for cck=%d, ofdm=%d, ht1s=%d, ht2s=%d, vht1s=%d, vht2s=%d\n", - priv->pshare->txpwr_lmt_CCK, - priv->pshare->txpwr_lmt_OFDM, - priv->pshare->txpwr_lmt_HT1S, - priv->pshare->txpwr_lmt_HT2S, - priv->pshare->txpwr_lmt_VHT1S, - priv->pshare->txpwr_lmt_VHT2S - ); - - return lmt_valid; - -} - - -void TxLMT_CCK_8812_A(struct rtl8192cd_priv *priv) -{ - - unsigned int tmp_dw = 0; - unsigned char idx_cck_11m = 0; - char lmt_pg_idx_cck = 0; - char max_lmt_idx_cck = 0; - - lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; - - //Cal Max tx pwr idx for CCK - tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); - idx_cck_11m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - - assign_lmt_reg_value(priv, rTxAGC_A_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); -} - -void TxLMT_CCK_8812_B(struct rtl8192cd_priv *priv) -{ - - unsigned int tmp_dw = 0; - unsigned char idx_cck_11m = 0; - char lmt_pg_idx_cck = 0; - char max_lmt_idx_cck = 0; - - lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; - - //Cal Max tx pwr idx for CCK - tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); - idx_cck_11m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - - assign_lmt_reg_value(priv, rTxAGC_B_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); -} - - -void TxLMT_OFDM_8812_A(struct rtl8192cd_priv *priv) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_cck_11m = 0; - unsigned char idx_odfm_54m = 0; - unsigned char idx_ht_mcs7 = 0; - unsigned char idx_ht_mcs15 = 0; - unsigned char idx_vht_1ss_mcs7 =0; - unsigned char idx_vht_2ss_mcs7 =0; - - char lmt_pg_idx_cck, lmt_pg_idx_ofdm = 0; - char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; - char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; - - char max_lmt_idx_cck, max_lmt_idx_ofdm = 0; - char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; - char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; - - lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; - lmt_pg_idx_ofdm = priv->pshare->txpwr_lmt_OFDM - priv->pshare->tgpwr_OFDM_new[0]; - lmt_pg_idx_ht1s = priv->pshare->txpwr_lmt_HT1S - priv->pshare->tgpwr_HT1S_new[0]; - lmt_pg_idx_ht2s = priv->pshare->txpwr_lmt_HT2S - priv->pshare->tgpwr_HT2S_new[0]; - lmt_pg_idx_vht1s = priv->pshare->txpwr_lmt_VHT1S - priv->pshare->tgpwr_VHT1S_new[0]; - lmt_pg_idx_vht2s = priv->pshare->txpwr_lmt_VHT2S - priv->pshare->tgpwr_VHT2S_new[0]; - - //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, - //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); - - - //Cal Max tx pwr idx for CCK - tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); - idx_cck_11m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - //Cal Max tx pwr idx for OFDM - tmp_dw = RTL_R32(rTxAGC_A_Ofdm54_Ofdm24_JAguar); - idx_odfm_54m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; - max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); - - //Cal Max tx pwr idx for HT1S - tmp_dw = RTL_R32(rTxAGC_A_MCS7_MCS4_JAguar); - idx_ht_mcs7 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - - //Cal Max tx pwr idx for HT2S - tmp_dw = RTL_R32(rTxAGC_A_MCS15_MCS12_JAguar); - idx_ht_mcs15 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); - - //Cal Max tx pwr idx for VHT1S - tmp_dw = RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); - idx_vht_1ss_mcs7 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; - max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); - - //Cal Max tx pwr idx for VHT2S - tmp_dw = RTL_R32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar); - idx_vht_2ss_mcs7 = get_byte_from_dw(tmp_dw, 1); - max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; - max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); - - assign_lmt_reg_value(priv, rTxAGC_A_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); - - assign_lmt_reg_value(priv, rTxAGC_A_Ofdm18_Ofdm6_JAguar, max_lmt_idx_ofdm, 0); - assign_lmt_reg_value(priv, rTxAGC_A_Ofdm54_Ofdm24_JAguar, max_lmt_idx_ofdm, 0); - - assign_lmt_reg_value(priv, rTxAGC_A_MCS3_MCS0_JAguar, max_lmt_idx_ht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_MCS7_MCS4_JAguar, max_lmt_idx_ht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_MCS11_MCS8_JAguar, max_lmt_idx_ht2s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_MCS15_MCS12_JAguar, max_lmt_idx_ht2s, 0); - - assign_lmt_reg_value(priv, rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, max_lmt_idx_vht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, max_lmt_idx_vht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, max_lmt_idx_vht1s, max_lmt_idx_vht2s); - assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, max_lmt_idx_vht2s, 0); - assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, max_lmt_idx_vht2s, 0); - -} - - -void TxLMT_OFDM_8812_B(struct rtl8192cd_priv *priv) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_cck_11m = 0; - unsigned char idx_odfm_54m = 0; - unsigned char idx_ht_mcs7 = 0; - unsigned char idx_ht_mcs15 = 0; - unsigned char idx_vht_1ss_mcs7 =0; - unsigned char idx_vht_2ss_mcs7 =0; - - char lmt_pg_idx_cck, lmt_pg_idx_ofdm = 0; - char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; - char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; - - char max_lmt_idx_cck, max_lmt_idx_ofdm = 0; - char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; - char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; - - lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[1]; - lmt_pg_idx_ofdm = priv->pshare->txpwr_lmt_OFDM - priv->pshare->tgpwr_OFDM_new[1]; - lmt_pg_idx_ht1s = priv->pshare->txpwr_lmt_HT1S - priv->pshare->tgpwr_HT1S_new[1]; - lmt_pg_idx_ht2s = priv->pshare->txpwr_lmt_HT2S - priv->pshare->tgpwr_HT2S_new[1]; - lmt_pg_idx_vht1s = priv->pshare->txpwr_lmt_VHT1S - priv->pshare->tgpwr_VHT1S_new[1]; - lmt_pg_idx_vht2s = priv->pshare->txpwr_lmt_VHT2S - priv->pshare->tgpwr_VHT2S_new[1]; - - //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, - //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); - - //Cal Max tx pwr idx for CCK - tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); - idx_cck_11m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - - //Cal Max tx pwr idx for OFDM - tmp_dw = RTL_R32(rTxAGC_B_Ofdm54_Ofdm24_JAguar); - idx_odfm_54m = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; - max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); - - //Cal Max tx pwr idx for HT1S - tmp_dw = RTL_R32(rTxAGC_B_MCS7_MCS4_JAguar); - idx_ht_mcs7 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - - //Cal Max tx pwr idx for HT2S - tmp_dw = RTL_R32(rTxAGC_B_MCS15_MCS12_JAguar); - idx_ht_mcs15 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); - - //Cal Max tx pwr idx for VHT1S - tmp_dw = RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); - idx_vht_1ss_mcs7 = get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; - max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); - - //Cal Max tx pwr idx for VHT2S - tmp_dw = RTL_R32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar); - idx_vht_2ss_mcs7 = get_byte_from_dw(tmp_dw, 1); - max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; - max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); - - assign_lmt_reg_value(priv, rTxAGC_B_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); - - assign_lmt_reg_value(priv, rTxAGC_B_Ofdm18_Ofdm6_JAguar, max_lmt_idx_ofdm, 0); - assign_lmt_reg_value(priv, rTxAGC_B_Ofdm54_Ofdm24_JAguar, max_lmt_idx_ofdm, 0); - - assign_lmt_reg_value(priv, rTxAGC_B_MCS3_MCS0_JAguar, max_lmt_idx_ht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_MCS7_MCS4_JAguar, max_lmt_idx_ht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_MCS11_MCS8_JAguar, max_lmt_idx_ht2s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_MCS15_MCS12_JAguar, max_lmt_idx_ht2s, 0); - - assign_lmt_reg_value(priv, rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, max_lmt_idx_vht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, max_lmt_idx_vht1s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, max_lmt_idx_vht1s, max_lmt_idx_vht2s); - assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, max_lmt_idx_vht2s, 0); - assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, max_lmt_idx_vht2s, 0); - -} - - -#endif - -void PHY_SetOFDMTxPower_8812(struct rtl8192cd_priv *priv, unsigned char channel) -{ - unsigned char ch_idx = 0; - // unsigned char tmp_TPI = 0; - unsigned char phy_band = 0; - u4Byte pwrdiff = 0x06060606; - - if (channel > 0) - ch_idx = (channel - 1); - else { - printk("Error Channel !!\n"); - return; - } - - if (channel > 14) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; - -#if 0 - printk("pwrlevel5GHT40_1S_A[%d]= %d \n", channel, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]); - printk("pwrdiff_5G_20BW1S_OFDM1T_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx]); - printk("pwrdiff_40BW2S_20BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx]); - printk("pwrdiff_5G_20BW1S_OFDM1T_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx]); - printk("pwrdiff_5G_40BW2S_20BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx]); - printk("pwrdiff_5G_80BW1S_160BW1S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_A[ch_idx]); - printk("pwrdiff_5G_80BW2S_160BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_A[ch_idx]); - - printk("pwrlevel5GHT40_1S_B[%d]= %d \n", channel, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]); - printk("pwrdiff_5G_20BW1S_OFDM1T_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx]); - printk("pwrdiff_40BW2S_20BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx]); - printk("pwrdiff_5G_20BW1S_OFDM1T_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx]); - printk("pwrdiff_5G_40BW2S_20BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx]); - printk("pwrdiff_5G_80BW1S_160BW1S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_B[ch_idx]); - printk("pwrdiff_5G_80BW2S_160BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_B[ch_idx]); -#endif - - if (phy_band == PHY_BAND_5G) { - if ((priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx] == 0) - || (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx] == 0)) { - use_DefaultOFDMTxPower_8812(priv); - return; - } - Cal_OFDMTxPower_5G(priv, ch_idx); - } else if (phy_band == PHY_BAND_2G) { - if ((priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx] == 0) - || (priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx] == 0)) { - use_DefaultOFDMTxPower_8812(priv); - return; - } - Cal_OFDMTxPower_2G(priv, ch_idx); - } - -#ifdef TX_PG_8812 - TxPG_OFDM_8812_A(priv); - TxPG_OFDM_8812_B(priv); -#endif - -#ifdef TXPWR_LMT_8812 - if (!priv->pshare->rf_ft_var.disable_txpwrlmt) - { - if (check_lmt_valid(priv, phy_band)) - { - TxLMT_OFDM_8812_A(priv); - TxLMT_OFDM_8812_B(priv); - } - } -#endif - { - int ofdm6a = RTL_R32(rTxAGC_A_Ofdm18_Ofdm6_JAguar) & 0x3f; - int ofdm6b = RTL_R32(rTxAGC_B_Ofdm18_Ofdm6_JAguar) & 0x3f; - if(ofdm6a>priv->pshare->rf_ft_var.bcn_pwr_max) { - ofdm6a = priv->pshare->rf_ft_var.bcn_pwr_max; - RTL_W8(rTxAGC_A_Ofdm18_Ofdm6_JAguar, ofdm6a); - } - if(ofdm6b>priv->pshare->rf_ft_var.bcn_pwr_max) { - ofdm6b = priv->pshare->rf_ft_var.bcn_pwr_max; - RTL_W8(rTxAGC_B_Ofdm18_Ofdm6_JAguar, ofdm6b); - } - priv->pshare->rf_ft_var.bcn_pwr_idex= max(ofdm6a,ofdm6b); - } - -} - -void PHY_SetCCKTxPower_8812(struct rtl8192cd_priv *priv, unsigned char channel) -{ - unsigned int def_power = 0x20202020;//0x12121212; - unsigned char ch_idx = 0; - unsigned char tmp_TPI = 0; - unsigned char phy_band = 0; - unsigned int writeVal = 0; - u4Byte pwrdiff = 0x06060606; -#ifdef POWER_PERCENT_ADJUSTMENT - signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); -#endif - - if (channel > 0) - ch_idx = (channel - 1); - else { - printk("Error Channel !!\n"); - return; - } - - if (channel > 14) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; - - if ((priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx] == 0) - && (priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx] == 0)) { - //printk("NO Calibration data, use default CCK power = 0x%x\n", def_power); - RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, def_power); - RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, def_power); - return; - } - - if (phy_band == PHY_BAND_2G) { - //printk("pwrlevelCCK_A[%d]= %d \n", ch_idx, priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx]); - //printk("pwrlevelCCK_B[%d]= %d \n", ch_idx, priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx]); - - //PATH A - tmp_TPI = priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - tmp_TPI = POWER_RANGE_CHECK(tmp_TPI + pwrdiff_percent); -#endif - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, writeVal); - - //PATH B - tmp_TPI = priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx]; -#ifdef POWER_PERCENT_ADJUSTMENT - tmp_TPI = POWER_RANGE_CHECK(tmp_TPI + pwrdiff_percent); -#endif - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, writeVal); - } -#ifdef TX_PG_8812 - TxPG_CCK_8812(priv); -#endif - -#ifdef TXPWR_LMT_8812 - if (!priv->pshare->rf_ft_var.disable_txpwrlmt) - { - if (check_lmt_valid(priv, phy_band)) - { - TxLMT_CCK_8812_A(priv); - TxLMT_CCK_8812_B(priv); - } - } -#endif - -} - - - - - - - - -// Firmware - -#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes -#define FW_START_ADDRESS 0x1000 -#define FWDL_ChkSum_rpt BIT(2) - -extern unsigned char *data_rtl8812fw_start, *data_rtl8812fw_end; -extern unsigned char *data_rtl8812fw_n_start, *data_rtl8812fw_n_end; //for_8812_mp_chip -#ifdef AC2G_256QAM -extern unsigned char *data_rtl8812fw_n_2g_start, *data_rtl8812fw_n_2g_end; -#endif - - -VOID -_8051Reset8812( - struct rtl8192cd_priv *priv -) -{ - u1Byte u1bTmp; - u1bTmp = RTL_R8(REG_SYS_FUNC_EN_8812 + 1); - RTL_W8(REG_SYS_FUNC_EN_8812 + 1, u1bTmp & (~BIT2)); - RTL_W8( REG_SYS_FUNC_EN_8812 + 1, u1bTmp | (BIT2)); -// RT_TRACE(COMP_INIT, DBG_LOUD, ("=====> _8051Reset8812(): 8051 reset success .\n")); -} - - -VOID -_FWDownloadEnable_8812( - struct rtl8192cd_priv *priv, - BOOLEAN enable -) -{ - u1Byte tmp; - - if (enable) { - // MCU firmware download enable. - RTL_W8( REG_MCUFWDL_8812, 0x05); - - // Clear Rom DL enable - tmp = RTL_R8( REG_MCUFWDL_8812 + 2); - RTL_W8( REG_MCUFWDL_8812 + 2, tmp & 0xf7); - } else { - // MCU firmware download enable. - tmp = RTL_R8( REG_MCUFWDL_8812); - RTL_W8( REG_MCUFWDL_8812, tmp & 0xfe); - } -} - -VOID -_FillDummy_8812( - pu1Byte pFwBuf, - pu4Byte pFwLen -) -{ - u4Byte FwLen = *pFwLen; - u1Byte remain = (u1Byte)(FwLen % 4); - remain = (remain == 0) ? 0 : (4 - remain); - - while (remain > 0) { - pFwBuf[FwLen] = 0; - FwLen++; - remain--; - } - - *pFwLen = FwLen; -} - - - -// BlockWrite: -// 92DU----------use 64-Byte/8-Byte/1-Byte (PlatformIOWriteNByte) -// 92CU/8723U----use 4-Byte/1-Byte (PlatformIOWriteNByte) -// PCI/SDIO------use 4-Byte/1-Byte (PlatformEFIOWrite4Byte) -// 92CU [MacOS]-- use 196-Byte/8-Byte/1-Byte (PlatformIOWriteNByte) - -VOID -_BlockWrite_8812( - struct rtl8192cd_priv *priv, - IN PVOID buffer, - IN u4Byte buffSize -) -{ - u4Byte blockSize_p1 = 4; // (Default) Phase #1 : PCI muse use 4-byte write to download FW - u4Byte blockSize_p2 = 8; // Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. - u4Byte blockSize_p3 = 1; // Phase #3 : Use 1-byte, the remnant of FW image. - u4Byte blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; - u4Byte remainSize_p1 = 0, remainSize_p2 = 0; - pu1Byte bufferPtr = (pu1Byte)buffer; - u4Byte i = 0, offset = 0; - - - //3 Phase #1 - blockCount_p1 = buffSize / blockSize_p1; - remainSize_p1 = buffSize % blockSize_p1; - - - for (i = 0 ; i < blockCount_p1 ; i++) { - RTL_W32( (FW_START_ADDRESS + i * blockSize_p1), cpu_to_le32(*((pu4Byte)(bufferPtr + i * blockSize_p1)))); - } - - //3 Phase #2 - if (remainSize_p1) { - offset = blockCount_p1 * blockSize_p1; - - blockCount_p2 = remainSize_p1 / blockSize_p2; - remainSize_p2 = remainSize_p1 % blockSize_p2; - - } - - //3 Phase #3 - if (remainSize_p2) { - offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); - blockCount_p3 = remainSize_p2 / blockSize_p3; - - // RT_TRACE(COMP_INIT,DBG_LOUD,("_BlockWrite_8812[P3] ::buffSize_p3( %d) blockSize_p3( %d) blockCount_p3( %d) \n",(buffSize-offset),blockSize_p3, blockCount_p3)); - - for (i = 0 ; i < blockCount_p3 ; i++) { - RTL_W8( (FW_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); - } - } -} - - -VOID -_PageWrite_8812( - struct rtl8192cd_priv *priv, - IN u4Byte page, - IN PVOID buffer, - IN u4Byte size -) -{ - u1Byte value8; - u1Byte u8Page = (u1Byte) (page & 0x07) ; - - value8 = (RTL_R8(REG_MCUFWDL_8812 + 2) & 0xF8 ) | u8Page ; - RTL_W8(REG_MCUFWDL_8812 + 2, value8); - - _BlockWrite_8812(priv, buffer, size); -} - - -VOID -_WriteFW_8812( - struct rtl8192cd_priv *priv, - IN PVOID buffer, - IN u4Byte size -) -{ - // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. - // We can remove _ReadChipVersion from ReadAdapterInfo8192C later. - u4Byte pageNums, remainSize ; - u4Byte page, offset; - pu1Byte bufferPtr = (pu1Byte)buffer; - -#if 1//DEV_BUS_TYPE==RT_PCI_INTERFACE - // 20100120 Joseph: Add for 88CE normal chip. - // Fill in zero to make firmware image to dword alignment. - // _FillDummy_8812(bufferPtr, &size); -#endif - - pageNums = size / MAX_PAGE_SIZE ; - - // RT_ASSERT((pageNums <= 8), ("Page numbers should not greater then 8 \n")); - - remainSize = size % MAX_PAGE_SIZE; - - for (page = 0; page < pageNums; page++) { - offset = page * MAX_PAGE_SIZE; - _PageWrite_8812(priv, page, (bufferPtr + offset), MAX_PAGE_SIZE); - } - if (remainSize) { - offset = pageNums * MAX_PAGE_SIZE; - page = pageNums; - _PageWrite_8812(priv, page, (bufferPtr + offset), remainSize); - } - // RT_TRACE(COMP_INIT, DBG_LOUD, ("_WriteFW_8812 Done- for Normal chip.\n")); -} - - -RT_STATUS -_FWFreeToGo8812( - struct rtl8192cd_priv *priv - -) -{ - u4Byte counter = 0; - u4Byte value32; - - // polling CheckSum report - do { - value32 = RTL_R32( REG_MCUFWDL_8812); - } while ((counter ++ < 6000) && (!(value32 & FWDL_ChkSum_rpt ))); - - if (counter >= 24000) { - // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("_FWFreeToGo8812:: chksum report faill ! REG_MCUFWDL:0x%08x .\n",value32)); - return RT_STATUS_FAILURE; - } - // RT_TRACE(COMP_INIT, DBG_LOUD, ("_FWFreeToGo8812:: Checksum report OK ! REG_MCUFWDL:0x%08x .\n",value32)); - - value32 = RTL_R32( REG_MCUFWDL_8812); - value32 |= MCUFWDL_RDY; - value32 &= ~WINTINI_RDY; - RTL_W32( REG_MCUFWDL_8812, value32); - - _8051Reset8812(priv); - - // polling for FW ready - counter = 0; - do { - if (RTL_R32( REG_MCUFWDL_8812) & WINTINI_RDY) { - // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Polling FW ready success!! REG_MCUFWDL:0x%08x in %d times.\n",PlatformEFIORead4Byte(Adapter, REG_MCUFWDL_8812),counter)); - return RT_STATUS_SUCCESS; - } - // PlatformStallExecution(5); - delay_us(5); - } while (counter++ < 24000); - - panic_printk("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", RTL_R32( REG_MCUFWDL_8812) ); - return RT_STATUS_FAILURE; -} - - -RT_STATUS -FirmwareDownload8812( - struct rtl8192cd_priv *priv -) -{ - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - - //u4Byte FwImageLen = 0; - u1Byte *pFirmwareBuf; - u4Byte FirmwareLen; - - RTL_W8( 0xf0, (RTL_R8(0xf0)& ~BIT(7))); -#ifdef CONFIG_RTL_8812_SUPPORT - if (IS_TEST_CHIP(priv)) { //for_8812_mp_chip - pFirmwareBuf = data_rtl8812fw_start + 32; - FirmwareLen = data_rtl8812fw_end - data_rtl8812fw_start - 32; -#ifdef AC2G_256QAM - } else if (is_ac2g(priv)) { - pFirmwareBuf = data_rtl8812fw_n_2g_start + 32; - FirmwareLen = data_rtl8812fw_n_2g_end - data_rtl8812fw_n_2g_start - 32; -#endif - } else { - pFirmwareBuf = data_rtl8812fw_n_start + 32; - FirmwareLen = data_rtl8812fw_n_end - data_rtl8812fw_n_start - 32; - } -#endif -#ifdef CONFIG_RTL_8723B_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8723B) { - pFirmwareBuf = data_rtl8723bfw_start + 32; - FirmwareLen = data_rtl8723bfw_end - data_rtl8723bfw_start - 32; - } -#endif - - - // panic_printk("%s, %d%x, %x\n", __FUNCTION__, __LINE__, pFirmwareBuf, FirmwareLen); - - - { - if (RTL_R8( REG_MCUFWDL_8812)&BIT7) { //8051 RAM code - RTL_W8(REG_MCUFWDL_8812, 0x00); - _8051Reset8812(priv); - } - } - - - - _FWDownloadEnable_8812(priv, TRUE); - - _WriteFW_8812(priv, pFirmwareBuf, FirmwareLen); - - _FWDownloadEnable_8812(priv, FALSE); - - - rtStatus = _FWFreeToGo8812(priv); - - if (RT_STATUS_SUCCESS != rtStatus) { - panic_printk("Firmware is not ready to run!\n") ; - goto Exit; - } - - -Exit: - - DEBUG_INFO(" <=== FirmwareDownload8812()\n"); - return rtStatus; - -} - - -// 8812 H2C - -BOOLEAN -CheckFwReadLastH2C_8812( - struct rtl8192cd_priv *priv, - IN u1Byte BoxNum -) -{ - u1Byte valHMETFR; - BOOLEAN Result = FALSE; - - valHMETFR = RTL_R8( REG_HMETFR_8812); - - // Do not seperate to 91C and 88C, we use the same setting. Suggested by SD4 Filen. 2009.12.03. - if (((valHMETFR >> BoxNum)&BIT0) == 0) - Result = TRUE; - - return Result; -} - - -u1Byte -FillH2CCmd8812( - struct rtl8192cd_priv *priv, - IN u1Byte ElementID, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer -) -{ - - u1Byte ioStatus = 0; - u1Byte BoxNum; - u2Byte BOXReg = 0, BOXExtReg = 0; - // u1Byte U1btmp; //Read 0x1bf - BOOLEAN bFwReadClear = FALSE; - u1Byte BufIndex = 0; - u1Byte WaitH2cLimmit = 0; - u1Byte BoxContent[4], BoxExtContent[4]; - u1Byte idx = 0; - - if (!GET_ROOT(priv)->bFWReady) - return 1; - - // 1. Find the last BOX number which has been writen. - BoxNum = priv->pshare->fw_q_fifo_count; //pHalData->LastHMEBoxNum; - switch (BoxNum) { - case 0: - BOXReg = REG_HMEBOX_0_8812; - BOXExtReg = REG_HMEBOX_EXT0_8812; - break; - case 1: - BOXReg = REG_HMEBOX_1_8812; - BOXExtReg = REG_HMEBOX_EXT1_8812; - break; - case 2: - BOXReg = REG_HMEBOX_2_8812; - BOXExtReg = REG_HMEBOX_EXT2_8812; - break; - case 3: - BOXReg = REG_HMEBOX_3_8812; - BOXExtReg = REG_HMEBOX_EXT3_8812; - break; - default: - break; - } - - // 2. Check if the box content is empty. - while (!bFwReadClear) { - bFwReadClear = CheckFwReadLastH2C_8812(priv, BoxNum); - if (WaitH2cLimmit++ >= 100) { - ioStatus = 1; - return ioStatus; - } else if (!bFwReadClear) { - delay_us(10); //us - } - } - - // 4. Fill the H2C cmd into box - memset(BoxContent, 0, sizeof(BoxContent)); - memset(BoxExtContent, 0, sizeof(BoxExtContent)); - - BoxContent[0] = ElementID; // Fill element ID - // RTPRINT(FFW, FW_MSG_H2C_CONTENT, ("[FW], Write ElementID BOXReg(%4x) = %2x \n", BOXReg, ElementID)); - - switch (CmdLen) { - case 1: - case 2: - case 3: { - //BoxContent[0] &= ~(BIT7); - memcpy((pu1Byte)(BoxContent) + 1, pCmdBuffer + BufIndex, CmdLen); - //For Endian Free. - for (idx = 0; idx < 4; idx++) { - RTL_W8(BOXReg + idx, BoxContent[idx]); - } - break; - } - case 4: - case 5: - case 6: - case 7: { - //BoxContent[0] |= (BIT7); - memcpy((pu1Byte)(BoxExtContent), pCmdBuffer + BufIndex + 3, (CmdLen - 3)); - memcpy((pu1Byte)(BoxContent) + 1, pCmdBuffer + BufIndex, 3); - //For Endian Free. - for (idx = 0 ; idx < 4 ; idx ++) { - RTL_W8( BOXExtReg + idx, BoxExtContent[idx]); - } - for (idx = 0 ; idx < 4 ; idx ++) { - RTL_W8( BOXReg + idx, BoxContent[idx]); - } - break; - } - - default: - // RTPRINT(FFW, FW_MSG_H2C_STATE, ("[FW], Invalid command len=%d!!!\n", CmdLen)); - ioStatus = 2; - return ioStatus; - break; - } - - if (++priv->pshare->fw_q_fifo_count > 3) - priv->pshare->fw_q_fifo_count = 0; - - // RTPRINT(FFW, FW_MSG_H2C_CONTENT, ("[FW], pHalData->LastHMEBoxNum = %d\n", pHalData->LastHMEBoxNum)); - return ioStatus; -} - - - - - - - -VOID -SetBcnCtrlReg_8812( - struct rtl8192cd_priv *priv, - IN u1Byte SetBits, - IN u1Byte ClearBits -) -{ - u1Byte tmp = RTL_R8(REG_BCN_CTRL_8812); - - tmp |= SetBits; - tmp &= ~ClearBits; - - RTL_W8(REG_BCN_CTRL_8812, tmp); -} - - -u1Byte -MRateIdxToARFRId8812( - struct rtl8192cd_priv *priv, - u1Byte RateIdx, - u1Byte RfType -) -{ - u1Byte Ret = 0; - - switch (RateIdx) { - - case RATR_INX_WIRELESS_NGB: - if (RfType == MIMO_1T1R) - Ret = 1; - else - Ret = 0; - break; - - case RATR_INX_WIRELESS_N: - case RATR_INX_WIRELESS_NG: - if (RfType == MIMO_1T1R) - Ret = 5; - else - Ret = 4; - break; - - case RATR_INX_WIRELESS_NB: - if (RfType == MIMO_1T1R) - Ret = 3; - else - Ret = 2; - break; - - case RATR_INX_WIRELESS_GB: - Ret = 6; - break; - - case RATR_INX_WIRELESS_G: - Ret = 7; - break; - - case RATR_INX_WIRELESS_B: - Ret = 8; - break; - - case RATR_INX_WIRELESS_MC: - if (!(priv->pmib->dot11BssType.net_work_type & WIRELESS_11A)) - Ret = 6; - else - Ret = 7; - break; - case RATR_INX_WIRELESS_AC_N: - if (RfType == MIMO_1T1R) - Ret = 10; - else - Ret = 9; - break; - - default: - Ret = 0; - break; - } - - return Ret; -} - -u1Byte -Get_RA_BW( - BOOLEAN bCurTxBW80MHz, - BOOLEAN bCurTxBW40MHz -) -{ - u1Byte BW = 0; - if (bCurTxBW80MHz) - BW = 2; - else if (bCurTxBW40MHz) - BW = 1; - else - BW = 0; - - return BW; -} - - - -#if 0 -typedef enum _WIRELESS_MODE { - WIRELESS_MODE_UNKNOWN = 0x00, - WIRELESS_MODE_A = 0x01, - WIRELESS_MODE_B = 0x02, - WIRELESS_MODE_G = 0x04, - WIRELESS_MODE_AUTO = 0x08, - WIRELESS_MODE_N_24G = 0x10, - WIRELESS_MODE_N_5G = 0x20, - WIRELESS_MODE_AC_5G = 0x40 -} WIRELESS_MODE; -#endif - -#define MIMO_PS_STATIC 0 -#define MIMO_PS_DYNAMIC 1 -#define MIMO_PS_NOLIMIT 3 - -#define FillOctetString(_os,_octet,_len) \ - (_os).Octet=(pu1Byte)(_octet); \ - (_os).Length=(_len); - - -u1Byte -Get_VHT_ENI( - u4Byte IOTAction, - u1Byte WirelessMode, - u4Byte ratr_bitmap -) -{ - u1Byte Ret = 0; - if (WirelessMode < WIRELESS_MODE_N_24G) - Ret = 0; - else if (WirelessMode == WIRELESS_MODE_N_24G || WirelessMode == WIRELESS_MODE_N_5G) { -#if 0 - //if(IOTAction == HT_IOT_VHT_HT_MIX_MODE) - { - if (ratr_bitmap & BIT20) // Mix , 2SS - Ret = 3; - else // Mix, 1SS - Ret = 2; - } -#else - Ret = 0; -#endif - - } else if (WirelessMode == WIRELESS_MODE_AC_5G) - Ret = 1; // VHT - - return (Ret << 4); -} - - - -BOOLEAN -Get_RA_ShortGI( - struct rtl8192cd_priv *priv, - struct stat_info * pEntry, - IN WIRELESS_MODE WirelessMode, - IN u1Byte ChnlBW -) -{ - BOOLEAN bShortGI; - - BOOLEAN bShortGI20MHz = FALSE, bShortGI40MHz = FALSE, bShortGI80MHz = FALSE; - - if ( WirelessMode == WIRELESS_MODE_N_24G || - WirelessMode == WIRELESS_MODE_N_5G || - WirelessMode == WIRELESS_MODE_AC_5G ) { - if (pEntry->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_) && - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M) { - bShortGI20MHz = TRUE; - } - if (pEntry->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_) - && priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M) { - bShortGI40MHz = TRUE; - } - #ifdef RTK_AC_SUPPORT - if (WirelessMode == WIRELESS_MODE_AC_5G && (GET_CHIP_VER(priv) != VERSION_8723B)) { - if ( (cpu_to_le32(pEntry->vht_cap_buf.vht_cap_info) & BIT(SHORT_GI80M_E)) - && priv->pmib->dot11nConfigEntry.dot11nShortGIfor80M) - bShortGI80MHz = TRUE; -#if 0 -// disable SGI when LDPC is enabled in AC mode - if((pEntry->is_realtek_sta) && (priv->pmib->dot11nConfigEntry.dot11nLDPC == 1) && - ((pEntry->ht_cap_len && cpu_to_le16(pEntry->ht_cap_buf.ht_cap_info) & _HTCAP_SUPPORT_RX_LDPC_) || - (pEntry->vht_cap_len && (cpu_to_le32(pEntry->vht_cap_buf.vht_cap_info) & BIT(RX_LDPC_E)))) ) { - bShortGI80MHz = bShortGI40MHz = bShortGI20MHz = 0; - } -#endif - } - #endif - } - - switch (ChnlBW) { - case HT_CHANNEL_WIDTH_20_40: - bShortGI = bShortGI40MHz; - break; - case HT_CHANNEL_WIDTH_80: - bShortGI = bShortGI80MHz; - break; - default: - case HT_CHANNEL_WIDTH_20: - bShortGI = bShortGI20MHz; - break; - } - return bShortGI; -} - - -u4Byte -RateToBitmap_2SSVHT( - pu1Byte pVHTRate -) -{ - - u1Byte i, j , tmpRate; - u4Byte RateBitmap = 0; - - for (i = j = 0; i < 4; i += 2, j += 10) { - tmpRate = (pVHTRate[0] >> i) & 3; - - switch (tmpRate) { - case 2: - RateBitmap = RateBitmap | (0x03ff << j); - break; - case 1: - RateBitmap = RateBitmap | (0x01ff << j); - break; - - case 0: - RateBitmap = RateBitmap | (0x00ff << j); - break; - - default: - break; - } - } - - return RateBitmap; -} - - -u4Byte -Get_VHT_HT_Mix_Ratrbitmap( - u4Byte IOTAction, - WIRELESS_MODE WirelessMode, - u4Byte HT_ratr_bitmap, - u4Byte VHT_ratr_bitmap -) -{ - u4Byte ratr_bitmap = 0; - if (WirelessMode == WIRELESS_MODE_N_24G || WirelessMode == WIRELESS_MODE_N_5G) { - /* - if(IOTAction == HT_IOT_VHT_HT_MIX_MODE) - ratr_bitmap = HT_ratr_bitmap | BIT28 | BIT29; - else - ratr_bitmap = HT_ratr_bitmap; - */ - } else - ratr_bitmap = VHT_ratr_bitmap; - - return ratr_bitmap; -} - - -#ifdef AC2G_256QAM -char is_ac2g(struct rtl8192cd_priv * priv) -{ - - unsigned char ac2g = 0; - - if((GET_CHIP_VER(priv)== VERSION_8812E) || (GET_CHIP_VER(priv)== VERSION_8881A)) - if(priv->pmib->dot11BssType.net_work_type & WIRELESS_11AC - && ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) == 0) - && (priv->pshare->rf_ft_var.ac2g_enable) - ) - ac2g = 1; - - return ac2g; - -} -#endif - -VOID -UpdateHalRAMask8812( - struct rtl8192cd_priv *priv, - struct stat_info *pEntry, - u1Byte rssi_level -) -{ - - u1Byte WirelessMode = WIRELESS_MODE_A; - u1Byte BW = HT_CHANNEL_WIDTH_20; - // u2Byte RateSet=0, i; - u1Byte MimoPs = MIMO_PS_NOLIMIT, MimoPs_enable = FALSE, ratr_index = 8, H2CCommand[7] = { 0}; - u4Byte ratr_bitmap = 0, IOTAction = 0; - u1Byte disable_cck_rate = FALSE; - u4Byte ratr_bitmap_msb = 0; - BOOLEAN bShortGI = FALSE, bCurTxBW80MHz = FALSE, bCurTxBW40MHz = FALSE; - struct stat_info *pstat = pEntry; - u1Byte rf_mimo_mode = get_rf_mimo_mode(priv); - #if CFG_HAL_RTK_AC_SUPPORT - unsigned int VHT_TxMap = priv->pmib->dot11acConfigEntry.dot11VHT_TxMap; - #endif - - if (pEntry == NULL) { - return; - } - { - if (pEntry->MIMO_ps & _HT_MIMO_PS_STATIC_) - MimoPs = MIMO_PS_STATIC; - else if (pEntry->MIMO_ps & _HT_MIMO_PS_DYNAMIC_) - MimoPs = MIMO_PS_DYNAMIC; - -#if 1 - BW = pstat->tx_bw; - if( BW > priv->pshare->CurrentChannelBW) - BW = priv->pshare->CurrentChannelBW; -#endif - add_RATid(priv, pEntry); - rssi_level = pstat->rssi_level; - ratr_bitmap = 0xfffffff; - // - // if(pstat->vht_cap_len && ( priv->pshare->rf_ft_var.support_11ac)) { - #ifdef RTK_AC_SUPPORT - if (pstat->vht_cap_len && (priv->pmib->dot11BssType.net_work_type & WIRELESS_11AC) && (!should_restrict_Nrate(priv, pstat)) && (GET_CHIP_VER(priv) != VERSION_8723B)) { //for 11ac logo - - if( (IS_B_CUT_8812(priv)) - && ((priv->pmib->dot11nConfigEntry.dot11nUse40M==0)||(BW == 0)) ) - { - //printk("\n !!! B CUT + AC STA + 20M, NO AC RATES !!!\n"); - //printk("AP=%dM, STA=%dM\n", (0x1<<(priv->pmib->dot11nConfigEntry.dot11nUse40M))*20 , (0x1<<(pstat->tx_bw))*20 ); - WirelessMode = WIRELESS_MODE_N_5G; - } - else{ - WirelessMode = WIRELESS_MODE_AC_5G; - } - - if (((le32_to_cpu(pstat->vht_cap_buf.vht_support_mcs[0]) >> 2) & 3) == 3) - rf_mimo_mode = MIMO_1T1R; - if (pstat->nss == 1) - rf_mimo_mode = MIMO_1T1R; - } else - #endif - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && (!should_restrict_Nrate(priv, pstat))) { - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && (priv->pmib->dot11RFEntry.dot11channel > 14)) - WirelessMode = WIRELESS_MODE_N_5G; - else - WirelessMode = WIRELESS_MODE_N_24G; - if ((pstat->tx_ra_bitmap & 0xff00000) == 0) - rf_mimo_mode = MIMO_1T1R; - } else if (((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) && - (priv->pmib->dot11RFEntry.dot11channel <= 14)) { - WirelessMode = WIRELESS_MODE_G; - } else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && - (priv->pmib->dot11RFEntry.dot11channel > 14) && - ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G))) { - WirelessMode = WIRELESS_MODE_A; - } else if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11B) { - WirelessMode = WIRELESS_MODE_B; - } - - pstat->WirelessMode = WirelessMode; - - if (WirelessMode == WIRELESS_MODE_AC_5G) { - ratr_bitmap &= 0xfff; - #ifdef RTK_AC_SUPPORT - if(GET_CHIP_VER(priv) != VERSION_8723B) { - int tmp32 = (pstat->vht_cap_buf.vht_support_mcs[0]); - // special 1SS & 2SS - if (pstat->nss == 1) - tmp32 |= cpu_to_le32(0xfffc); - else if ((pstat->nss == 2) && (le32_to_cpu(tmp32) & 0x0c) == 0x0c) - tmp32 &= cpu_to_le32(0xfffffff3); - // - ratr_bitmap |= RateToBitmap_2SSVHT((pu1Byte)&tmp32) << 12; - } - #endif - if (IS_TEST_CHIP(priv)) { // Test Chip... 2SS MCS7 - if (rf_mimo_mode == MIMO_1T1R) - ratr_bitmap &= 0x000fffff; - else - ratr_bitmap &= 0x3FCFFFFF; - } else { // MP Chip... MCS0~9 - if (rf_mimo_mode == MIMO_1T1R) - ratr_bitmap &= 0x003fffff; - } - - if (BW == HT_CHANNEL_WIDTH_80) - bCurTxBW80MHz = TRUE; - } -// if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40)) -// bCurTxBW40MHz = TRUE; - - if (priv->pshare->is_40m_bw && (BW == HT_CHANNEL_WIDTH_20_40) -#ifdef WIFI_11N_2040_COEXIST - && !((((GET_MIB(priv))->dot11OperationEntry.opmode) & WIFI_AP_STATE) - && COEXIST_ENABLE - && (priv->bg_ap_timeout || orForce20_Switch20Map(priv) - - )) -#endif - ) - - bCurTxBW40MHz = TRUE; - - } - - if(((GET_MIB(priv))->dot11OperationEntry.opmode) & WIFI_STATION_STATE) { - if(((GET_MIB(priv))->dot11Bss.t_stamp[1] & 0x6) == 0) { - bCurTxBW40MHz = bCurTxBW80MHz = FALSE; - } - } - BW = Get_RA_BW(bCurTxBW80MHz, bCurTxBW40MHz); - #if CFG_HAL_RTK_AC_SUPPORT - if(BW == 0) - { - //remove MCS9 for BW=20m - if (rf_mimo_mode == MIMO_1T1R) - VHT_TxMap &= ~(BIT(9)); - else if (rf_mimo_mode == MIMO_2T2R) - VHT_TxMap &= ~(BIT(9)|BIT(19)); - } - #endif - -#if 1 - - bShortGI = Get_RA_ShortGI(priv, pEntry, WirelessMode, BW); - pstat->tx_bw_fw = BW; - - if (MimoPs <= MIMO_PS_DYNAMIC) + +#define _8812_HW_C_ + +#include "8192cd.h" +#include "8192cd_cfg.h" +#include "8192cd_util.h" + +#include "8192c_reg.h" +#include "8812_reg.h" +#include "8812_vht_gen.h" + +#ifdef __KERNEL__ +#include +#endif +//eric_8812 #include "8192cd_debug.h" +#include "8192cd_headers.h" + + + +#if defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_8723B_SUPPORT) +typedef struct _C2H_EVT_HDR{ + u1Byte CmdID: 4; + u1Byte CmdLen: 4; + u1Byte CmdSeq; +}C2H_EVT_HDR, *PC2H_EVT_HDR; + +typedef enum _RTL8812_C2H_EVT +{ + C2H_8812_DBG = 0, + C2H_8812_LB = 1, + C2H_8812_TXBF = 2, + CCXRPT = 3, + C2H_8812_TXPERORT = 4, + C2H_8812_RA_RPT = 12, +#ifdef TXRETRY_CNT + C2H_8812_TXRETRY = 13, //0x0D +#endif + C2H_8812_RA_PARA_RPT=14, + C2H_8812_EXTEND_IND = 0xFF, + MAX_8812_C2HEVENT +}RTL8812_C2H_EVT; + +typedef enum _RTL8812_EXTEND_C2H_EVT +{ + EXTEND_C2H_8812_DBG_PRINT = 0 + +}RTL8812_EXTEND_C2H_EVT; + +void UpdateBBRFVal8812(struct rtl8192cd_priv *priv, unsigned char channel) +{ + unsigned char current_is_5g = 0, switch_bw = 0; + unsigned char bTmp = 0; + unsigned int dwTmp = 0; + unsigned int tmp_cb0=0, tmp_eb0 = 0; //for_8812_mp_chip + unsigned int eRFPath, curMaxRFPath; + + curMaxRFPath = RF92CD_PATH_MAX; + + //check CCK_CHECK_en BIT7 + if ( RTL_R8(0x454) & BIT(7) ) + current_is_5g = 1; + else + current_is_5g = 0; + + if (((channel > 14) && (current_is_5g == 0)) || ((channel <= 14) && (current_is_5g == 1))) + switch_bw = 1; + + //printk("\n\n eric-current_is_5g = %d switch_bw = %d pre= %d\n\n", current_is_5g, switch_bw, priv->pshare->pre_channel); + + if (channel > 14 && (switch_bw || (priv->pshare->pre_channel == 0))) //2.4G to 5G + RTL_W8(0x454, (RTL_R8(0x454) | BIT(7))); + + //Set fc_area 0x860 + dwTmp = RTL_R32(0x860); + dwTmp &= ~(BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28)); + + if (channel <= 14) + dwTmp |= (0x96a << 17); + else if (channel <= 48) + dwTmp |= (0x494 << 17); + else if (channel <= 64) + dwTmp |= (0x453 << 17); + else if (channel <= 116) + dwTmp |= (0x452 << 17); + else if (channel <= 177) + dwTmp |= (0x412 << 17); + + RTL_W32(0x860, dwTmp); + + //Set RF MOD AG rf_0x18 + for (eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + dwTmp = PHY_QueryRFReg(priv, eRFPath, rRfChannel, bMask20Bits, 1); + dwTmp &= ~(BIT(8) | BIT(9) | BIT(16) | BIT(17) | BIT(18)); + + if (channel <= 14) + dwTmp |= 0x0; + else if (channel <= 64) + dwTmp |= (BIT(8) | BIT(16)); + else if (channel <= 140) + dwTmp |= (BIT(8) | BIT(16) | BIT(17)); + else + dwTmp |= (BIT(8) | BIT(16) | BIT(18)); + + PHY_SetRFReg(priv, eRFPath, rRfChannel, bMask20Bits, dwTmp); + } + + //Set BB registers //for_8812_mp_chip + if (switch_bw) { + if (!IS_TEST_CHIP(priv)) { + tmp_cb0 = RTL_R32(0xcb0); + tmp_cb0 &= ~(BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23)); + tmp_eb0 = RTL_R32(0xeb0); + tmp_eb0 &= ~(BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23)); + } + + if (!current_is_5g) { + bTmp = RTL_R8(0x82c); + bTmp &= ~(BIT(0) | BIT(1)); + bTmp |= BIT(0); + RTL_W8(0x82c, bTmp); + if (GET_CHIP_VER(priv) == VERSION_8881A) { + PHY_SetBBReg(priv, 0xcb0, 0xff, 0x55); + PHY_SetBBReg(priv, 0xcb0, 0xf000, 0x1); + } else { + if (IS_TEST_CHIP(priv)) { + RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(12)); + RTL_W32(0xeb8, RTL_R32(0xcb8) | BIT(12)); + RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(15))); + RTL_W32(0xeb8, RTL_R32(0xeb8) & (~BIT(15))); + } else { +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) + { + #if 0 + if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501) { + RTL_W32(0xcb0, tmp_cb0 | (0x53 << 16)); + RTL_W32(0xeb0, tmp_eb0 | (0x53 << 16)); + } else { + RTL_W32(0xcb0, tmp_cb0 | (0x54 << 16)); + RTL_W32(0xeb0, tmp_eb0 | (0x54 << 16)); + } + #else + //For 8812 PHY_PARAMETER after V40. + RTL_W32(0xcb0, 0x77337717); + RTL_W32(0xeb0, 0x77337717); + + if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501 || priv->pmib->dot11RFEntry.pa_type == PA_SKYWORKS_85712_HP) { + PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x00); + PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x00); + } else { + PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x10); + PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x10); + } + #endif + } else +#endif + { +#ifdef CONFIG_PA_RTC5634 + // internal PA+PAPE + if (priv->pmib->dot11RFEntry.pa_type == PA_RTC5634) { + //panic_printk("Set PAPE on\n"); + RTL_W32(0xcb0, 0x77537717); + RTL_W32(0xeb0, 0x77537717); + } +#endif + } + } + } +// RTL_W32(0x808, RTL_R32(0x808) & (~BIT(28))); + RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); + RTL_W8(0xa07, RTL_R8(0xa07) | 0xf); + RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); + PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x15); + } else { + bTmp = RTL_R8(0x82c); + bTmp &= ~(BIT(0) | BIT(1)); + RTL_W8(0x82c, bTmp); + + if (IS_TEST_CHIP(priv)) { + RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(12))); + RTL_W32(0xeb8, RTL_R32(0xcb8) & (~BIT(12))); + RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(15)); + RTL_W32(0xeb8, RTL_R32(0xeb8) | BIT(15)); + } else { + //RTL_W32(0xcb0, tmp_cb0 | (0x77 << 16)); + //RTL_W32(0xeb0, tmp_eb0 | (0x77 << 16)); + RTL_W32(0xcb0, 0x77777777); + RTL_W32(0xeb0, 0x77777777); + } + + RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); + RTL_W8(0xa07, (RTL_R8(0xa07) & 0xf0)|0x01); + RTL_W32(0x8c0, RTL_R32(0x8c0) | BIT(17)); + PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x17); + } + } else if (priv->pshare->pre_channel == 0) { //first launch + if (channel > 14) { + bTmp = RTL_R8(0x82c); + bTmp &= ~(BIT(0) | BIT(1)); + bTmp |= BIT(0); + RTL_W8(0x82c, bTmp); + + if (IS_TEST_CHIP(priv)) { + RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(12)); + RTL_W32(0xeb8, RTL_R32(0xcb8) | BIT(12)); + RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(15))); + RTL_W32(0xeb8, RTL_R32(0xeb8) & (~BIT(15))); + } else { +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) + { + #if 0 + if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501) { + RTL_W32(0xcb0, tmp_cb0 | (0x53 << 16)); + RTL_W32(0xeb0, tmp_eb0 | (0x53 << 16)); + } else { + RTL_W32(0xcb0, tmp_cb0 | (0x54 << 16)); + RTL_W32(0xeb0, tmp_eb0 | (0x54 << 16)); + } + #else + //For 8812 PHY_PARAMETER after V40. + RTL_W32(0xcb0, 0x77337717); + RTL_W32(0xeb0, 0x77337717); + + if (priv->pmib->dot11RFEntry.pa_type == PA_RFMD_4501 || priv->pmib->dot11RFEntry.pa_type == PA_SKYWORKS_85712_HP) { + PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x00); + PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x00); + } else { + PHY_SetBBReg(priv, 0xcb4, 0x3ff00000, 0x10); + PHY_SetBBReg(priv, 0xeb4, 0x3ff00000, 0x10); + } + #endif + } else +#endif + { +#ifdef CONFIG_PA_RTC5634 + // internal PA+PAPE + if (priv->pmib->dot11RFEntry.pa_type == PA_RTC5634) { + //panic_printk("Set PAPE on\n"); + RTL_W32(0xcb0, 0x77537717); + RTL_W32(0xeb0, 0x77537717); + } +#endif + } + } +// RTL_W32(0x808, RTL_R32(0x808) & (~BIT(28))); + RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); + RTL_W8(0xa07, RTL_R8(0xa07) | 0xf); + RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); + PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x15); + } else { + bTmp = RTL_R8(0x82c); + bTmp &= ~(BIT(0) | BIT(1)); + RTL_W8(0x82c, bTmp); + if (GET_CHIP_VER(priv) == VERSION_8881A) { + PHY_SetBBReg(priv, 0xcb0, 0xff, 0x00); + PHY_SetBBReg(priv, 0xcb0, 0xf000, 0x0); + } else { + + if (IS_TEST_CHIP(priv)) { + RTL_W32(0xcb8, RTL_R32(0xcb8) & (~BIT(12))); + RTL_W32(0xeb8, RTL_R32(0xcb8) & (~BIT(12))); + RTL_W32(0xcb8, RTL_R32(0xcb8) | BIT(15)); + RTL_W32(0xeb8, RTL_R32(0xeb8) | BIT(15)); + } else { + //RTL_W32(0xcb0, tmp_cb0 | (0x77 << 16)); + //RTL_W32(0xeb0, tmp_eb0 | (0x77 << 16)); + RTL_W32(0xcb0, 0x77777777); + RTL_W32(0xeb0, 0x77777777); + } + } + RTL_W32(0x808, RTL_R32(0x808) | BIT(28)); + RTL_W32(0x8c0, RTL_R32(0x8c0) | BIT(17)); + PHY_SetBBReg(priv, 0x830, BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13), 0x17); + } + } + + if (channel <= 14 && (switch_bw || (priv->pshare->pre_channel == 0))) + RTL_W8(0x454, (RTL_R8(0x454) & ~(BIT(7)))); + +#ifdef AC2G_256QAM + if(is_ac2g(priv)) + { + RTL_W32(0x8c0, RTL_R32(0x8c0) & (~BIT(17))); //enable tx vht rates + } +#endif + SpurCheck8812(priv, 1, channel, 0); + + priv->pshare->pre_channel = channel; + +} + + +/* 8812 2.4G spur at 2480MHz */ +void SpurCheck8812(struct rtl8192cd_priv *priv, unsigned char ch_bw, unsigned char channel, unsigned int bandwidth) +{ + unsigned int dwTmp = 0; + unsigned char primary_channel = 0; +#ifdef RTK_AC_SUPPORT + if(ch_bw == 1 && (GET_CHIP_VER(priv) != VERSION_8723B)){ /* if switch channel */ + if((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40 && (channel == 11 || channel == 12)) || + (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20 && (channel == 13 || channel == 14))){ + RTL_W32(0x8ac,0x0ff0ff04); + RTL_W32(0X8c4,0x40000000); + if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40){ + dwTmp = RTL_R32(0x8ac); + dwTmp |= BIT(0); + RTL_W32(0x8ac, dwTmp); + } + }else if((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40 && (priv->pshare->pre_channel == 11 || priv->pshare->pre_channel == 12)) || + (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20 && (priv->pshare->pre_channel == 13 || priv->pshare->pre_channel == 14))){ + + /* Restore 0x8ac, 0x8c4*/ + PHY_SetBBReg(priv, 0x8ac, BIT(10), 0); + RTL_W32(0X8c4,0); + primary_channel = priv->pshare->txsc_20; + dwTmp = RTL_R32(0x8ac); + dwTmp &= ~(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(20) | BIT(21)); + + switch (priv->pshare->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_AC_5: + dwTmp |= (BIT(6) | BIT(20)); + RTL_W32(0x8ac, dwTmp); + break; + case HT_CHANNEL_WIDTH_AC_10: + dwTmp |= (BIT(7) | BIT(8) | BIT(21)); + RTL_W32(0x8ac, dwTmp); + break; + case HT_CHANNEL_WIDTH_AC_20: + dwTmp |= (BIT(9) | BIT(20) | BIT(21)); + RTL_W32(0x8ac, dwTmp); + break; + case HT_CHANNEL_WIDTH_AC_40: + dwTmp |= (BIT(0) | BIT(9) | BIT(20) | BIT(21)); + RTL_W32(0x8ac, dwTmp); + break; + } + if (IS_C_CUT_8812(priv)) { + switch (priv->pshare->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_AC_5: + PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_10: + PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_20: + PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_40: + PHY_SetBBReg(priv, 0x8c4, BIT(30), 0); + break; + } + } + + dwTmp = RTL_R32(0x8ac); + dwTmp &= ~(BIT(2)|BIT(3)|BIT(4)|BIT(5)); + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + break; + case HT_CHANNEL_WIDTH_AC_40: + dwTmp |= (primary_channel << 2); + RTL_W32(0x8ac, dwTmp); + break; + } + } + }else if(ch_bw == 0){ /* if switch bandwidth */ + if((bandwidth == HT_CHANNEL_WIDTH_AC_20 && (priv->pmib->dot11RFEntry.dot11channel == 13 || priv->pmib->dot11RFEntry.dot11channel == 14)) || + (bandwidth == HT_CHANNEL_WIDTH_AC_40 && (priv->pmib->dot11RFEntry.dot11channel == 11 || priv->pmib->dot11RFEntry.dot11channel == 12)) + ){ + RTL_W32(0x8ac,0x0ff0ff04); + RTL_W32(0X8c4,0x40000000); + if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_40){ + dwTmp = RTL_R32(0x8ac); + dwTmp |= BIT(0); + RTL_W32(0x8ac, dwTmp); + } + } + } +#endif +} + + +signed char convert_diff(signed char value) +{ + // range from -8 ~ 7 + if (value <= 7) + return value; + else + return (value - 16); +} + +void Write_OFDM_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, writeVal); + RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, writeVal); +} + +void Write_1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); + RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); + RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); + writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_HT1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); + RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); +} + +void Write_HT2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); + RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); +} + +void Write_VHT1S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_VHT2S_A(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); + RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); + writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); +} +void Write_OFDM_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, writeVal); + RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, writeVal); +} + + +void Write_1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); + RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); + RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); + writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_HT1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); + RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); +} + +void Write_HT2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); + RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); +} + +void Write_VHT1S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void Write_VHT2S_B(struct rtl8192cd_priv *priv, unsigned int writeVal) +{ + RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); + RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); + writeVal = (writeVal & 0xffff0000) | (RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) & 0xffff); + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); +} + +void use_DefaultOFDMTxPower_8812(struct rtl8192cd_priv *priv) +{ + + unsigned int def_power = 0x20202020;//0x12121212; + //printk("NO Calibration data, use default OFDM power = 0x%x\n", def_power); + priv->pshare->rf_ft_var.bcn_pwr_idex= def_power & 0x3f; + + RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, def_power); + RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, def_power); + RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, def_power); + RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, def_power); + RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, def_power); + RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, def_power); + RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, def_power); + RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, def_power); + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, def_power); + RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, def_power); + RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, def_power); + + RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, def_power); + RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, def_power); + RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, def_power); + RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, def_power); + RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, def_power); + RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, def_power); + RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, def_power); + RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, def_power); + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, def_power); + RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, def_power); + RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, def_power); + +} + + +void Cal_OFDMTxPower_5G(struct rtl8192cd_priv *priv, unsigned char ch_idx) +{ + unsigned char tmp_TPI = 0; + unsigned char pwr_40_1s = 0, pwr_80_1s = 0; + signed char diff_ofdm_1t = 0; + signed char diff_bw40_2s = 0; + signed char diff_bw20_1s = 0; + signed char diff_bw20_2s = 0; + signed char diff_bw80_1s = 0; + signed char diff_bw80_2s = 0; + + unsigned int writeVal = 0; + unsigned char ch_idx_vht80 = get_center_channel(priv, priv->pmib->dot11RFEntry.dot11channel, priv->pmib->dot11nConfigEntry.dot11n2ndChOffset, 1) -1; + unsigned char ch_idx_ht40 = ((priv->pmib->dot11nConfigEntry.dot11n2ndChOffset==HT_2NDCH_OFFSET_BELOW) ? (priv->pmib->dot11RFEntry.dot11channel-2) : (priv->pmib->dot11RFEntry.dot11channel+2)) - 1; +#ifdef POWER_PERCENT_ADJUSTMENT + signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); +#endif + + // PATH A, OFDM + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx] & 0x0f); + diff_ofdm_1t = convert_diff(diff_ofdm_1t); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_A(priv, writeVal); + + //printk("Write_OFDM_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_ofdm_1t); + + + // PATH B, OFDM + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx] & 0x0f); + diff_ofdm_1t = convert_diff(diff_ofdm_1t); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_B(priv, writeVal); + + //printk("Write_OFDM_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_ofdm_1t); + + + if (priv->pshare->CurrentChannelBW == 0) { + //PATH A, BW20-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx] & 0xf0) >> 4); + diff_bw20_1s = convert_diff(diff_bw20_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_1S_A(priv, writeVal); + + //printk("Write_1S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw20_1s); + + + //PATH A, BW20-2S + diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx] & 0x0f); + diff_bw20_2s = convert_diff(diff_bw20_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_2S_A(priv, writeVal); + + //printk("Write_2S_A %d = %d + %d + %d\n", tmp_TPI, pwr_40_1s , diff_bw20_1s, diff_bw20_2s); + + // ==== // + + //PATH B, BW20-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx] & 0xf0) >> 4); + diff_bw20_1s = convert_diff(diff_bw20_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_1S_B(priv, writeVal); + + //printk("Write_1S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw20_1s); + + //PATH B, BW20-2S + diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx] & 0x0f); + diff_bw20_2s = convert_diff(diff_bw20_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_2S_B(priv, writeVal); + + //printk("Write_2S_B %d = %d + %d + %d\n", tmp_TPI, pwr_40_1s , diff_bw20_1s, diff_bw20_2s); + + } else if (priv->pshare->CurrentChannelBW == 1) { + //PATH A, BW40-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_1S_A(priv, writeVal); + + //printk("Write_1S_A %d = %d \n", tmp_TPI, pwr_40_1s); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx_ht40] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_2S_A(priv, writeVal); + + //printk("Write_2S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); + + // ==== // + + //PATH B, BW40-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_1S_B(priv, writeVal); + + //printk("Write_1S_B %d = %d \n", tmp_TPI, pwr_40_1s); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx_ht40] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_2S_B(priv, writeVal); + + //printk("Write_2S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); + + } else if (priv->pshare->CurrentChannelBW == 2) { + + //PATH A, BW40-1S + //printk("ch_idx_ht40 %d >>> [0x%x 0x%x]\n", ch_idx_ht40, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40], priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]); + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_ht40]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_A(priv, writeVal); + + //printk("Write_HT1S_A 0x%x = 0x%x\n", tmp_TPI, pwr_40_1s); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx_ht40] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_A(priv, writeVal); + + //printk("Write_HT2S_A 0x%x = 0x%x + 0x%x \n", tmp_TPI, pwr_40_1s , diff_bw40_2s); + + // ==== // + + //PATH B, BW40-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_ht40]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_B(priv, writeVal); + + //printk("Write_1S_B %d = %d \n", tmp_TPI, pwr_40_1s); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx_ht40] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_B(priv, writeVal); + + + //PATH A, BW80-1S + pwr_80_1s = (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_vht80 - 4] + + priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx_vht80 + 4]) / 2 ; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_80_1s = POWER_RANGE_CHECK(pwr_80_1s + pwrdiff_percent); +#endif + diff_bw80_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_A[ch_idx_vht80] & 0xf0) >> 4); + diff_bw80_1s = convert_diff(diff_bw80_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_80_1s + diff_bw80_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_VHT1S_A(priv, writeVal); + + //printk("Write_1S_A %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s); + + + //PATH A, BW80-2S + diff_bw80_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_A[ch_idx_vht80] & 0xf0) >> 4); + diff_bw80_2s = convert_diff(diff_bw80_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_80_1s + diff_bw80_1s + diff_bw80_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_VHT2S_A(priv, writeVal); + + //printk("Write_2S_A %d = %d + %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s, diff_bw80_1s); + + + //PATH B, BW80-1S + pwr_40_1s = (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_vht80 - 4] + + priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx_vht80 + 4]) / 2 ; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_bw80_1s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_B[ch_idx_vht80] & 0xf0) >> 4); + diff_bw80_1s = convert_diff(diff_bw80_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw80_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_VHT1S_B(priv, writeVal); + + //printk("Write_1S_B %d = %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s); + + + //PATH B, BW80-2S + diff_bw80_2s = ((priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_B[ch_idx_vht80] & 0xf0) >> 4); + diff_bw80_2s = convert_diff(diff_bw80_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw80_1s + diff_bw80_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_VHT2S_B(priv, writeVal); + + //printk("Write_2S_B %d = %d + %d + %d \n", tmp_TPI, pwr_40_1s , diff_bw80_1s, diff_bw80_1s); + + } +} + +void Cal_OFDMTxPower_2G(struct rtl8192cd_priv *priv, unsigned char ch_idx) +{ + unsigned char tmp_TPI = 0; + unsigned char pwr_40_1s = 0; + signed char diff_ofdm_1t = 0; + signed char diff_bw40_2s = 0; + signed char diff_bw20_1s = 0; + signed char diff_bw20_2s = 0; + + unsigned int writeVal = 0; + //unsigned char ch_idx_ht20 = priv->pmib->dot11RFEntry.dot11channel -1; + +#ifdef POWER_PERCENT_ADJUSTMENT + signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); +#endif + + // PATH A, OFDM + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_A[ch_idx] & 0x0f); + diff_ofdm_1t = convert_diff(diff_ofdm_1t); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_A(priv, writeVal); + + + // PATH B, OFDM + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_ofdm_1t = (priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_B[ch_idx] & 0x0f); + diff_ofdm_1t = convert_diff(diff_ofdm_1t); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_ofdm_1t); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_B(priv, writeVal); + + if (priv->pshare->CurrentChannelBW == 0) { + //PATH A, BW20-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_A[ch_idx] & 0xf0) >> 4); + diff_bw20_1s = convert_diff(diff_bw20_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_A(priv, writeVal); + + + //PATH A, BW20-2S + diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx] & 0x0f); + diff_bw20_2s = convert_diff(diff_bw20_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_A(priv, writeVal); + + // ==== // + + //PATH B, BW20-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + diff_bw20_1s = ((priv->pmib->dot11RFEntry.pwrdiff_20BW1S_OFDM1T_B[ch_idx] & 0xf0) >> 4); + diff_bw20_1s = convert_diff(diff_bw20_1s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_B(priv, writeVal); + + //PATH B, BW20-2S + diff_bw20_2s = (priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx] & 0x0f); + diff_bw20_2s = convert_diff(diff_bw20_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw20_1s + diff_bw20_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_B(priv, writeVal); + + } else if (priv->pshare->CurrentChannelBW == 1) { + //PATH A, BW40-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_A(priv, writeVal); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_A(priv, writeVal); + + // ==== // + + //PATH B, BW40-1S + pwr_40_1s = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + pwr_40_1s = POWER_RANGE_CHECK(pwr_40_1s + pwrdiff_percent); +#endif + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT1S_B(priv, writeVal); + + + //PATH A, BW40-2S + diff_bw40_2s = ((priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx] & 0xf0) >> 4); + diff_bw40_2s = convert_diff(diff_bw40_2s); + tmp_TPI = POWER_RANGE_CHECK(pwr_40_1s + diff_bw40_2s); + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_HT2S_B(priv, writeVal); + + } +} +#ifdef TX_PG_8812 +void get_tx_pwr(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, + unsigned char *tmp_b3, unsigned char *tmp_b4) +{ + *tmp_b1 = (tmp_dw & (0xff)); + *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); + *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); + *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); +} + +void TxPG_CCK_8812(struct rtl8192cd_priv *priv) +{ + unsigned char b1, b2, b3, b4; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned int tmp_dw = 0; + unsigned int writeVal = 0; + + tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->CCKTxAgc_A[3])); + *tmp_b2 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->CCKTxAgc_A[2])); + *tmp_b3 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->CCKTxAgc_A[1])); + *tmp_b4 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->CCKTxAgc_A[0])); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, writeVal); + + tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->CCKTxAgc_B[3])); + *tmp_b2 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->CCKTxAgc_B[2])); + *tmp_b3 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->CCKTxAgc_B[1])); + *tmp_b4 = (unsigned char)(POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->CCKTxAgc_B[0])); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, writeVal); +} + + +void TxPG_OFDM_8812_A(struct rtl8192cd_priv *priv) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 =0; + unsigned int writeVal = 0; + + //printk("TxPG_OFDM_8812_A!!\n"); + tmp_dw = RTL_R32(rTxAGC_A_Ofdm18_Ofdm6_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_A[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_A[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_A[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_A[0]); + if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_max) + *tmp_b1 = priv->pshare->rf_ft_var.bcn_pwr_max; + priv->pshare->rf_ft_var.bcn_pwr_idex= *tmp_b1; + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Ofdm18_Ofdm6_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_Ofdm54_Ofdm24_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_A[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_A[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_A[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Ofdm54_Ofdm24_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_MCS3_MCS0_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_MCS3_MCS0_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_MCS7_MCS4_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_MCS7_MCS4_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_MCS11_MCS8_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[11]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[10]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[9]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_MCS11_MCS8_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_MCS15_MCS12_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_A[15]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_A[14]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_A[13]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_A[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_MCS15_MCS12_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, writeVal); + + tmp_dw = RTL_R32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar); + tmp_dw1= RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); + get_tx_pwr(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_A[11]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_A[10]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[9]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, writeVal); + + tmp_dw = RTL_R32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[15]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[14]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_A[13]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_A[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, writeVal); + + tmp_dw = RTL_R32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_A[19]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_A[18]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 - priv->pshare->phw->VHTTxAgcOffset_A[17]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 - priv->pshare->phw->VHTTxAgcOffset_A[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, writeVal); +} + + +void TxPG_OFDM_8812_B(struct rtl8192cd_priv *priv) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 =0; + unsigned int writeVal = 0; + + //printk("TxPG_OFDM_8812_B!!\n"); + tmp_dw = RTL_R32(rTxAGC_B_Ofdm18_Ofdm6_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_B[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_B[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_B[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_B[0]); + if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_max) + *tmp_b1 = priv->pshare->rf_ft_var.bcn_pwr_max; + if(*tmp_b1 > priv->pshare->rf_ft_var.bcn_pwr_idex) + priv->pshare->rf_ft_var.bcn_pwr_idex= *tmp_b1; + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Ofdm18_Ofdm6_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Ofdm54_Ofdm24_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->OFDMTxAgcOffset_B[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->OFDMTxAgcOffset_B[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->OFDMTxAgcOffset_B[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->OFDMTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Ofdm54_Ofdm24_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_MCS3_MCS0_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_MCS3_MCS0_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_MCS7_MCS4_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_MCS7_MCS4_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_MCS11_MCS8_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[11]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[10]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[9]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_MCS11_MCS8_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_MCS15_MCS12_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->MCSTxAgcOffset_B[15]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->MCSTxAgcOffset_B[14]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->MCSTxAgcOffset_B[13]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->MCSTxAgcOffset_B[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_MCS15_MCS12_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[3]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[2]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[1]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[7]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[6]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[5]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar); + tmp_dw1= RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); + get_tx_pwr(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_B[11]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b5 - priv->pshare->phw->VHTTxAgcOffset_B[10]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[9]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[15]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[14]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 + priv->pshare->phw->VHTTxAgcOffset_B[13]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 + priv->pshare->phw->VHTTxAgcOffset_B[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, writeVal); + tmp_dw = RTL_R32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar); + get_tx_pwr(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = POWER_RANGE_CHECK(*tmp_b1 + priv->pshare->phw->VHTTxAgcOffset_B[19]); + *tmp_b2 = POWER_RANGE_CHECK(*tmp_b2 + priv->pshare->phw->VHTTxAgcOffset_B[18]); + *tmp_b3 = POWER_RANGE_CHECK(*tmp_b3 - priv->pshare->phw->VHTTxAgcOffset_B[17]); + *tmp_b4 = POWER_RANGE_CHECK(*tmp_b4 - priv->pshare->phw->VHTTxAgcOffset_B[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + RTL_W32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, writeVal); +} +#endif + + +#ifdef TXPWR_LMT_8812 + +unsigned char get_byte_from_dw(unsigned int tmp_dw, unsigned char byte_num) +{ + + if (byte_num == 0) + return (tmp_dw & (0xff)); + else if (byte_num == 1) + return ((tmp_dw & (0xff00)) >> 8); + else if (byte_num == 2) + return ((tmp_dw & (0xff0000)) >> 16); + else if (byte_num == 3) + return ((tmp_dw & (0xff000000)) >> 24); + else + return 0; +} + +unsigned int assign_lmt_reg_value(struct rtl8192cd_priv *priv, unsigned int reg_offset, unsigned char max_idx, unsigned char max_idx2) +{ + + unsigned int tmp_dw; + unsigned char reg_val[4]; + unsigned char i=0; + + tmp_dw = RTL_R32(reg_offset); + + //printk("[0x%03x] 0x%08x >> ", reg_offset, tmp_dw); + + get_tx_pwr(tmp_dw, (unsigned char *)®_val[0], (unsigned char *)®_val[1], + (unsigned char *)®_val[2], (unsigned char *)®_val[3]); + + if((reg_offset == rTxAGC_A_Nss2Index1_Nss1Index8_JAguar) || + (reg_offset == rTxAGC_B_Nss2Index1_Nss1Index8_JAguar)) + { + reg_val[0] = POWER_MIN_CHECK(reg_val[0], max_idx); + reg_val[1] = POWER_MIN_CHECK(reg_val[1], max_idx); + reg_val[2] = POWER_MIN_CHECK(reg_val[2], max_idx2); + reg_val[3] = POWER_MIN_CHECK(reg_val[3], max_idx2); + } + else + { + for(i=0; i<4; i++) + { + reg_val[i] = POWER_MIN_CHECK(reg_val[i], max_idx); + } + } + + for(i=0; i<4; i++) + { + reg_val[i] = POWER_RANGE_CHECK(reg_val[i]); + } + + tmp_dw = (reg_val[3] << 24) | (reg_val[2] << 16) | (reg_val[1] << 8) | reg_val[0]; + + //printk("0x%08x\n", tmp_dw); + + RTL_W32(reg_offset, tmp_dw); + +} + +unsigned char check_lmt_valid(struct rtl8192cd_priv *priv, unsigned char phy_band) +{ + unsigned char lmt_valid = 1; + + if(phy_band == PHY_BAND_2G) + if(priv->pshare->txpwr_lmt_CCK == 0) + lmt_valid = 0; + + if(priv->pshare->txpwr_lmt_OFDM == 0) + lmt_valid = 0; + + if(priv->pshare->txpwr_lmt_HT1S == 0) + lmt_valid = 0; + + if(priv->pshare->txpwr_lmt_HT2S == 0) + lmt_valid = 0; + + if(phy_band == PHY_BAND_5G) + { + if(priv->pshare->txpwr_lmt_VHT1S == 0) + lmt_valid = 0; + + if(priv->pshare->txpwr_lmt_VHT2S == 0) + lmt_valid = 0; + } + + if(lmt_valid == 0) + DEBUG_WARN("NO Limit Value, NO limit TX POWER !!!\n limit for cck=%d, ofdm=%d, ht1s=%d, ht2s=%d, vht1s=%d, vht2s=%d\n", + priv->pshare->txpwr_lmt_CCK, + priv->pshare->txpwr_lmt_OFDM, + priv->pshare->txpwr_lmt_HT1S, + priv->pshare->txpwr_lmt_HT2S, + priv->pshare->txpwr_lmt_VHT1S, + priv->pshare->txpwr_lmt_VHT2S + ); + + return lmt_valid; + +} + + +void TxLMT_CCK_8812_A(struct rtl8192cd_priv *priv) +{ + + unsigned int tmp_dw = 0; + unsigned char idx_cck_11m = 0; + char lmt_pg_idx_cck = 0; + char max_lmt_idx_cck = 0; + + lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; + + //Cal Max tx pwr idx for CCK + tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); + idx_cck_11m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + + assign_lmt_reg_value(priv, rTxAGC_A_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); +} + +void TxLMT_CCK_8812_B(struct rtl8192cd_priv *priv) +{ + + unsigned int tmp_dw = 0; + unsigned char idx_cck_11m = 0; + char lmt_pg_idx_cck = 0; + char max_lmt_idx_cck = 0; + + lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; + + //Cal Max tx pwr idx for CCK + tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); + idx_cck_11m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + + assign_lmt_reg_value(priv, rTxAGC_B_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); +} + + +void TxLMT_OFDM_8812_A(struct rtl8192cd_priv *priv) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_cck_11m = 0; + unsigned char idx_odfm_54m = 0; + unsigned char idx_ht_mcs7 = 0; + unsigned char idx_ht_mcs15 = 0; + unsigned char idx_vht_1ss_mcs7 =0; + unsigned char idx_vht_2ss_mcs7 =0; + + char lmt_pg_idx_cck, lmt_pg_idx_ofdm = 0; + char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; + char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; + + char max_lmt_idx_cck, max_lmt_idx_ofdm = 0; + char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; + char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; + + lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[0]; + lmt_pg_idx_ofdm = priv->pshare->txpwr_lmt_OFDM - priv->pshare->tgpwr_OFDM_new[0]; + lmt_pg_idx_ht1s = priv->pshare->txpwr_lmt_HT1S - priv->pshare->tgpwr_HT1S_new[0]; + lmt_pg_idx_ht2s = priv->pshare->txpwr_lmt_HT2S - priv->pshare->tgpwr_HT2S_new[0]; + lmt_pg_idx_vht1s = priv->pshare->txpwr_lmt_VHT1S - priv->pshare->tgpwr_VHT1S_new[0]; + lmt_pg_idx_vht2s = priv->pshare->txpwr_lmt_VHT2S - priv->pshare->tgpwr_VHT2S_new[0]; + + //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, + //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); + + + //Cal Max tx pwr idx for CCK + tmp_dw = RTL_R32(rTxAGC_A_CCK11_CCK1_JAguar); + idx_cck_11m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + //Cal Max tx pwr idx for OFDM + tmp_dw = RTL_R32(rTxAGC_A_Ofdm54_Ofdm24_JAguar); + idx_odfm_54m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; + max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); + + //Cal Max tx pwr idx for HT1S + tmp_dw = RTL_R32(rTxAGC_A_MCS7_MCS4_JAguar); + idx_ht_mcs7 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + + //Cal Max tx pwr idx for HT2S + tmp_dw = RTL_R32(rTxAGC_A_MCS15_MCS12_JAguar); + idx_ht_mcs15 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); + + //Cal Max tx pwr idx for VHT1S + tmp_dw = RTL_R32(rTxAGC_A_Nss1Index7_Nss1Index4_JAguar); + idx_vht_1ss_mcs7 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; + max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); + + //Cal Max tx pwr idx for VHT2S + tmp_dw = RTL_R32(rTxAGC_A_Nss2Index9_Nss2Index6_JAguar); + idx_vht_2ss_mcs7 = get_byte_from_dw(tmp_dw, 1); + max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; + max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); + + assign_lmt_reg_value(priv, rTxAGC_A_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); + + assign_lmt_reg_value(priv, rTxAGC_A_Ofdm18_Ofdm6_JAguar, max_lmt_idx_ofdm, 0); + assign_lmt_reg_value(priv, rTxAGC_A_Ofdm54_Ofdm24_JAguar, max_lmt_idx_ofdm, 0); + + assign_lmt_reg_value(priv, rTxAGC_A_MCS3_MCS0_JAguar, max_lmt_idx_ht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_MCS7_MCS4_JAguar, max_lmt_idx_ht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_MCS11_MCS8_JAguar, max_lmt_idx_ht2s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_MCS15_MCS12_JAguar, max_lmt_idx_ht2s, 0); + + assign_lmt_reg_value(priv, rTxAGC_A_Nss1Index3_Nss1Index0_JAguar, max_lmt_idx_vht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_Nss1Index7_Nss1Index4_JAguar, max_lmt_idx_vht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index1_Nss1Index8_JAguar, max_lmt_idx_vht1s, max_lmt_idx_vht2s); + assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index5_Nss2Index2_JAguar, max_lmt_idx_vht2s, 0); + assign_lmt_reg_value(priv, rTxAGC_A_Nss2Index9_Nss2Index6_JAguar, max_lmt_idx_vht2s, 0); + +} + + +void TxLMT_OFDM_8812_B(struct rtl8192cd_priv *priv) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_cck_11m = 0; + unsigned char idx_odfm_54m = 0; + unsigned char idx_ht_mcs7 = 0; + unsigned char idx_ht_mcs15 = 0; + unsigned char idx_vht_1ss_mcs7 =0; + unsigned char idx_vht_2ss_mcs7 =0; + + char lmt_pg_idx_cck, lmt_pg_idx_ofdm = 0; + char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; + char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; + + char max_lmt_idx_cck, max_lmt_idx_ofdm = 0; + char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; + char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; + + lmt_pg_idx_cck = priv->pshare->txpwr_lmt_CCK - priv->pshare->tgpwr_CCK_new[1]; + lmt_pg_idx_ofdm = priv->pshare->txpwr_lmt_OFDM - priv->pshare->tgpwr_OFDM_new[1]; + lmt_pg_idx_ht1s = priv->pshare->txpwr_lmt_HT1S - priv->pshare->tgpwr_HT1S_new[1]; + lmt_pg_idx_ht2s = priv->pshare->txpwr_lmt_HT2S - priv->pshare->tgpwr_HT2S_new[1]; + lmt_pg_idx_vht1s = priv->pshare->txpwr_lmt_VHT1S - priv->pshare->tgpwr_VHT1S_new[1]; + lmt_pg_idx_vht2s = priv->pshare->txpwr_lmt_VHT2S - priv->pshare->tgpwr_VHT2S_new[1]; + + //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, + //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); + + //Cal Max tx pwr idx for CCK + tmp_dw = RTL_R32(rTxAGC_B_CCK11_CCK1_JAguar); + idx_cck_11m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + + //Cal Max tx pwr idx for OFDM + tmp_dw = RTL_R32(rTxAGC_B_Ofdm54_Ofdm24_JAguar); + idx_odfm_54m = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; + max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); + + //Cal Max tx pwr idx for HT1S + tmp_dw = RTL_R32(rTxAGC_B_MCS7_MCS4_JAguar); + idx_ht_mcs7 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + + //Cal Max tx pwr idx for HT2S + tmp_dw = RTL_R32(rTxAGC_B_MCS15_MCS12_JAguar); + idx_ht_mcs15 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); + + //Cal Max tx pwr idx for VHT1S + tmp_dw = RTL_R32(rTxAGC_B_Nss1Index7_Nss1Index4_JAguar); + idx_vht_1ss_mcs7 = get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; + max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); + + //Cal Max tx pwr idx for VHT2S + tmp_dw = RTL_R32(rTxAGC_B_Nss2Index9_Nss2Index6_JAguar); + idx_vht_2ss_mcs7 = get_byte_from_dw(tmp_dw, 1); + max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; + max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); + + assign_lmt_reg_value(priv, rTxAGC_B_CCK11_CCK1_JAguar, max_lmt_idx_cck, 0); + + assign_lmt_reg_value(priv, rTxAGC_B_Ofdm18_Ofdm6_JAguar, max_lmt_idx_ofdm, 0); + assign_lmt_reg_value(priv, rTxAGC_B_Ofdm54_Ofdm24_JAguar, max_lmt_idx_ofdm, 0); + + assign_lmt_reg_value(priv, rTxAGC_B_MCS3_MCS0_JAguar, max_lmt_idx_ht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_MCS7_MCS4_JAguar, max_lmt_idx_ht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_MCS11_MCS8_JAguar, max_lmt_idx_ht2s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_MCS15_MCS12_JAguar, max_lmt_idx_ht2s, 0); + + assign_lmt_reg_value(priv, rTxAGC_B_Nss1Index3_Nss1Index0_JAguar, max_lmt_idx_vht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_Nss1Index7_Nss1Index4_JAguar, max_lmt_idx_vht1s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index1_Nss1Index8_JAguar, max_lmt_idx_vht1s, max_lmt_idx_vht2s); + assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index5_Nss2Index2_JAguar, max_lmt_idx_vht2s, 0); + assign_lmt_reg_value(priv, rTxAGC_B_Nss2Index9_Nss2Index6_JAguar, max_lmt_idx_vht2s, 0); + +} + + +#endif + +void PHY_SetOFDMTxPower_8812(struct rtl8192cd_priv *priv, unsigned char channel) +{ + unsigned char ch_idx = 0; + // unsigned char tmp_TPI = 0; + unsigned char phy_band = 0; + u4Byte pwrdiff = 0x06060606; + + if (channel > 0) + ch_idx = (channel - 1); + else { + printk("Error Channel !!\n"); + return; + } + + if (channel > 14) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; + +#if 0 + printk("pwrlevel5GHT40_1S_A[%d]= %d \n", channel, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx]); + printk("pwrdiff_5G_20BW1S_OFDM1T_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx]); + printk("pwrdiff_40BW2S_20BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_A[ch_idx]); + printk("pwrdiff_5G_20BW1S_OFDM1T_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_A[ch_idx]); + printk("pwrdiff_5G_40BW2S_20BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_A[ch_idx]); + printk("pwrdiff_5G_80BW1S_160BW1S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_A[ch_idx]); + printk("pwrdiff_5G_80BW2S_160BW2S_A[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_A[ch_idx]); + + printk("pwrlevel5GHT40_1S_B[%d]= %d \n", channel, priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx]); + printk("pwrdiff_5G_20BW1S_OFDM1T_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx]); + printk("pwrdiff_40BW2S_20BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_40BW2S_20BW2S_B[ch_idx]); + printk("pwrdiff_5G_20BW1S_OFDM1T_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_20BW1S_OFDM1T_B[ch_idx]); + printk("pwrdiff_5G_40BW2S_20BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_40BW2S_20BW2S_B[ch_idx]); + printk("pwrdiff_5G_80BW1S_160BW1S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW1S_160BW1S_B[ch_idx]); + printk("pwrdiff_5G_80BW2S_160BW2S_B[%d]= 0x%x \n", channel, priv->pmib->dot11RFEntry.pwrdiff_5G_80BW2S_160BW2S_B[ch_idx]); +#endif + + if (phy_band == PHY_BAND_5G) { + if ((priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[ch_idx] == 0) + || (priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[ch_idx] == 0)) { + use_DefaultOFDMTxPower_8812(priv); + return; + } + Cal_OFDMTxPower_5G(priv, ch_idx); + } else if (phy_band == PHY_BAND_2G) { + if ((priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[ch_idx] == 0) + || (priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[ch_idx] == 0)) { + use_DefaultOFDMTxPower_8812(priv); + return; + } + Cal_OFDMTxPower_2G(priv, ch_idx); + } + +#ifdef TX_PG_8812 + TxPG_OFDM_8812_A(priv); + TxPG_OFDM_8812_B(priv); +#endif + +#ifdef TXPWR_LMT_8812 + if (!priv->pshare->rf_ft_var.disable_txpwrlmt) + { + if (check_lmt_valid(priv, phy_band)) + { + TxLMT_OFDM_8812_A(priv); + TxLMT_OFDM_8812_B(priv); + } + } +#endif + { + int ofdm6a = RTL_R32(rTxAGC_A_Ofdm18_Ofdm6_JAguar) & 0x3f; + int ofdm6b = RTL_R32(rTxAGC_B_Ofdm18_Ofdm6_JAguar) & 0x3f; + if(ofdm6a>priv->pshare->rf_ft_var.bcn_pwr_max) { + ofdm6a = priv->pshare->rf_ft_var.bcn_pwr_max; + RTL_W8(rTxAGC_A_Ofdm18_Ofdm6_JAguar, ofdm6a); + } + if(ofdm6b>priv->pshare->rf_ft_var.bcn_pwr_max) { + ofdm6b = priv->pshare->rf_ft_var.bcn_pwr_max; + RTL_W8(rTxAGC_B_Ofdm18_Ofdm6_JAguar, ofdm6b); + } + priv->pshare->rf_ft_var.bcn_pwr_idex= max(ofdm6a,ofdm6b); + } + +} + +void PHY_SetCCKTxPower_8812(struct rtl8192cd_priv *priv, unsigned char channel) +{ + unsigned int def_power = 0x20202020;//0x12121212; + unsigned char ch_idx = 0; + unsigned char tmp_TPI = 0; + unsigned char phy_band = 0; + unsigned int writeVal = 0; + u4Byte pwrdiff = 0x06060606; +#ifdef POWER_PERCENT_ADJUSTMENT + signed char pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); +#endif + + if (channel > 0) + ch_idx = (channel - 1); + else { + printk("Error Channel !!\n"); + return; + } + + if (channel > 14) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; + + if ((priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx] == 0) + && (priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx] == 0)) { + //printk("NO Calibration data, use default CCK power = 0x%x\n", def_power); + RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, def_power); + RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, def_power); + return; + } + + if (phy_band == PHY_BAND_2G) { + //printk("pwrlevelCCK_A[%d]= %d \n", ch_idx, priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx]); + //printk("pwrlevelCCK_B[%d]= %d \n", ch_idx, priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx]); + + //PATH A + tmp_TPI = priv->pmib->dot11RFEntry.pwrlevelCCK_A[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + tmp_TPI = POWER_RANGE_CHECK(tmp_TPI + pwrdiff_percent); +#endif + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + RTL_W32(rTxAGC_A_CCK11_CCK1_JAguar, writeVal); + + //PATH B + tmp_TPI = priv->pmib->dot11RFEntry.pwrlevelCCK_B[ch_idx]; +#ifdef POWER_PERCENT_ADJUSTMENT + tmp_TPI = POWER_RANGE_CHECK(tmp_TPI + pwrdiff_percent); +#endif + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + RTL_W32(rTxAGC_B_CCK11_CCK1_JAguar, writeVal); + } +#ifdef TX_PG_8812 + TxPG_CCK_8812(priv); +#endif + +#ifdef TXPWR_LMT_8812 + if (!priv->pshare->rf_ft_var.disable_txpwrlmt) + { + if (check_lmt_valid(priv, phy_band)) + { + TxLMT_CCK_8812_A(priv); + TxLMT_CCK_8812_B(priv); + } + } +#endif + +} + + + + + + + + +// Firmware + +#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes +#define FW_START_ADDRESS 0x1000 +#define FWDL_ChkSum_rpt BIT(2) + +extern unsigned char *data_rtl8812fw_start, *data_rtl8812fw_end; +extern unsigned char *data_rtl8812fw_n_start, *data_rtl8812fw_n_end; //for_8812_mp_chip +#ifdef AC2G_256QAM +extern unsigned char *data_rtl8812fw_n_2g_start, *data_rtl8812fw_n_2g_end; +#endif + + +VOID +_8051Reset8812( + struct rtl8192cd_priv *priv +) +{ + u1Byte u1bTmp; + u1bTmp = RTL_R8(REG_SYS_FUNC_EN_8812 + 1); + RTL_W8(REG_SYS_FUNC_EN_8812 + 1, u1bTmp & (~BIT2)); + RTL_W8( REG_SYS_FUNC_EN_8812 + 1, u1bTmp | (BIT2)); +// RT_TRACE(COMP_INIT, DBG_LOUD, ("=====> _8051Reset8812(): 8051 reset success .\n")); +} + + +VOID +_FWDownloadEnable_8812( + struct rtl8192cd_priv *priv, + BOOLEAN enable +) +{ + u1Byte tmp; + + if (enable) { + // MCU firmware download enable. + RTL_W8( REG_MCUFWDL_8812, 0x05); + + // Clear Rom DL enable + tmp = RTL_R8( REG_MCUFWDL_8812 + 2); + RTL_W8( REG_MCUFWDL_8812 + 2, tmp & 0xf7); + } else { + // MCU firmware download enable. + tmp = RTL_R8( REG_MCUFWDL_8812); + RTL_W8( REG_MCUFWDL_8812, tmp & 0xfe); + } +} + +VOID +_FillDummy_8812( + pu1Byte pFwBuf, + pu4Byte pFwLen +) +{ + u4Byte FwLen = *pFwLen; + u1Byte remain = (u1Byte)(FwLen % 4); + remain = (remain == 0) ? 0 : (4 - remain); + + while (remain > 0) { + pFwBuf[FwLen] = 0; + FwLen++; + remain--; + } + + *pFwLen = FwLen; +} + + + +// BlockWrite: +// 92DU----------use 64-Byte/8-Byte/1-Byte (PlatformIOWriteNByte) +// 92CU/8723U----use 4-Byte/1-Byte (PlatformIOWriteNByte) +// PCI/SDIO------use 4-Byte/1-Byte (PlatformEFIOWrite4Byte) +// 92CU [MacOS]-- use 196-Byte/8-Byte/1-Byte (PlatformIOWriteNByte) + +VOID +_BlockWrite_8812( + struct rtl8192cd_priv *priv, + IN PVOID buffer, + IN u4Byte buffSize +) +{ + u4Byte blockSize_p1 = 4; // (Default) Phase #1 : PCI muse use 4-byte write to download FW + u4Byte blockSize_p2 = 8; // Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. + u4Byte blockSize_p3 = 1; // Phase #3 : Use 1-byte, the remnant of FW image. + u4Byte blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; + u4Byte remainSize_p1 = 0, remainSize_p2 = 0; + pu1Byte bufferPtr = (pu1Byte)buffer; + u4Byte i = 0, offset = 0; + + + //3 Phase #1 + blockCount_p1 = buffSize / blockSize_p1; + remainSize_p1 = buffSize % blockSize_p1; + + + for (i = 0 ; i < blockCount_p1 ; i++) { + RTL_W32( (FW_START_ADDRESS + i * blockSize_p1), cpu_to_le32(*((pu4Byte)(bufferPtr + i * blockSize_p1)))); + } + + //3 Phase #2 + if (remainSize_p1) { + offset = blockCount_p1 * blockSize_p1; + + blockCount_p2 = remainSize_p1 / blockSize_p2; + remainSize_p2 = remainSize_p1 % blockSize_p2; + + } + + //3 Phase #3 + if (remainSize_p2) { + offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); + blockCount_p3 = remainSize_p2 / blockSize_p3; + + // RT_TRACE(COMP_INIT,DBG_LOUD,("_BlockWrite_8812[P3] ::buffSize_p3( %d) blockSize_p3( %d) blockCount_p3( %d) \n",(buffSize-offset),blockSize_p3, blockCount_p3)); + + for (i = 0 ; i < blockCount_p3 ; i++) { + RTL_W8( (FW_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); + } + } +} + + +VOID +_PageWrite_8812( + struct rtl8192cd_priv *priv, + IN u4Byte page, + IN PVOID buffer, + IN u4Byte size +) +{ + u1Byte value8; + u1Byte u8Page = (u1Byte) (page & 0x07) ; + + value8 = (RTL_R8(REG_MCUFWDL_8812 + 2) & 0xF8 ) | u8Page ; + RTL_W8(REG_MCUFWDL_8812 + 2, value8); + + _BlockWrite_8812(priv, buffer, size); +} + + +VOID +_WriteFW_8812( + struct rtl8192cd_priv *priv, + IN PVOID buffer, + IN u4Byte size +) +{ + // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. + // We can remove _ReadChipVersion from ReadAdapterInfo8192C later. + u4Byte pageNums, remainSize ; + u4Byte page, offset; + pu1Byte bufferPtr = (pu1Byte)buffer; + +#if 1//DEV_BUS_TYPE==RT_PCI_INTERFACE + // 20100120 Joseph: Add for 88CE normal chip. + // Fill in zero to make firmware image to dword alignment. + // _FillDummy_8812(bufferPtr, &size); +#endif + + pageNums = size / MAX_PAGE_SIZE ; + + // RT_ASSERT((pageNums <= 8), ("Page numbers should not greater then 8 \n")); + + remainSize = size % MAX_PAGE_SIZE; + + for (page = 0; page < pageNums; page++) { + offset = page * MAX_PAGE_SIZE; + _PageWrite_8812(priv, page, (bufferPtr + offset), MAX_PAGE_SIZE); + } + if (remainSize) { + offset = pageNums * MAX_PAGE_SIZE; + page = pageNums; + _PageWrite_8812(priv, page, (bufferPtr + offset), remainSize); + } + // RT_TRACE(COMP_INIT, DBG_LOUD, ("_WriteFW_8812 Done- for Normal chip.\n")); +} + + +RT_STATUS +_FWFreeToGo8812( + struct rtl8192cd_priv *priv + +) +{ + u4Byte counter = 0; + u4Byte value32; + + // polling CheckSum report + do { + value32 = RTL_R32( REG_MCUFWDL_8812); + } while ((counter ++ < 6000) && (!(value32 & FWDL_ChkSum_rpt ))); + + if (counter >= 24000) { + // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("_FWFreeToGo8812:: chksum report faill ! REG_MCUFWDL:0x%08x .\n",value32)); + return RT_STATUS_FAILURE; + } + // RT_TRACE(COMP_INIT, DBG_LOUD, ("_FWFreeToGo8812:: Checksum report OK ! REG_MCUFWDL:0x%08x .\n",value32)); + + value32 = RTL_R32( REG_MCUFWDL_8812); + value32 |= MCUFWDL_RDY; + value32 &= ~WINTINI_RDY; + RTL_W32( REG_MCUFWDL_8812, value32); + + _8051Reset8812(priv); + + // polling for FW ready + counter = 0; + do { + if (RTL_R32( REG_MCUFWDL_8812) & WINTINI_RDY) { + // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Polling FW ready success!! REG_MCUFWDL:0x%08x in %d times.\n",PlatformEFIORead4Byte(Adapter, REG_MCUFWDL_8812),counter)); + return RT_STATUS_SUCCESS; + } + // PlatformStallExecution(5); + delay_us(5); + } while (counter++ < 24000); + + panic_printk("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", RTL_R32( REG_MCUFWDL_8812) ); + return RT_STATUS_FAILURE; +} + + +RT_STATUS +FirmwareDownload8812( + struct rtl8192cd_priv *priv +) +{ + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + //u4Byte FwImageLen = 0; + u1Byte *pFirmwareBuf; + u4Byte FirmwareLen; + + RTL_W8( 0xf0, (RTL_R8(0xf0)& ~BIT(7))); +#ifdef CONFIG_RTL_8812_SUPPORT + if (IS_TEST_CHIP(priv)) { //for_8812_mp_chip + pFirmwareBuf = data_rtl8812fw_start + 32; + FirmwareLen = data_rtl8812fw_end - data_rtl8812fw_start - 32; +#ifdef AC2G_256QAM + } else if (is_ac2g(priv)) { + pFirmwareBuf = data_rtl8812fw_n_2g_start + 32; + FirmwareLen = data_rtl8812fw_n_2g_end - data_rtl8812fw_n_2g_start - 32; +#endif + } else { + pFirmwareBuf = data_rtl8812fw_n_start + 32; + FirmwareLen = data_rtl8812fw_n_end - data_rtl8812fw_n_start - 32; + } +#endif +#ifdef CONFIG_RTL_8723B_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8723B) { + pFirmwareBuf = data_rtl8723bfw_start + 32; + FirmwareLen = data_rtl8723bfw_end - data_rtl8723bfw_start - 32; + } +#endif + + + // panic_printk("%s, %d%x, %x\n", __FUNCTION__, __LINE__, pFirmwareBuf, FirmwareLen); + + + { + if (RTL_R8( REG_MCUFWDL_8812)&BIT7) { //8051 RAM code + RTL_W8(REG_MCUFWDL_8812, 0x00); + _8051Reset8812(priv); + } + } + + + + _FWDownloadEnable_8812(priv, TRUE); + + _WriteFW_8812(priv, pFirmwareBuf, FirmwareLen); + + _FWDownloadEnable_8812(priv, FALSE); + + + rtStatus = _FWFreeToGo8812(priv); + + if (RT_STATUS_SUCCESS != rtStatus) { + panic_printk("Firmware is not ready to run!\n") ; + goto Exit; + } + + +Exit: + + DEBUG_INFO(" <=== FirmwareDownload8812()\n"); + return rtStatus; + +} + + +// 8812 H2C + +BOOLEAN +CheckFwReadLastH2C_8812( + struct rtl8192cd_priv *priv, + IN u1Byte BoxNum +) +{ + u1Byte valHMETFR; + BOOLEAN Result = FALSE; + + valHMETFR = RTL_R8( REG_HMETFR_8812); + + // Do not seperate to 91C and 88C, we use the same setting. Suggested by SD4 Filen. 2009.12.03. + if (((valHMETFR >> BoxNum)&BIT0) == 0) + Result = TRUE; + + return Result; +} + + +u1Byte +FillH2CCmd8812( + struct rtl8192cd_priv *priv, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +) +{ + + u1Byte ioStatus = 0; + u1Byte BoxNum; + u2Byte BOXReg = 0, BOXExtReg = 0; + // u1Byte U1btmp; //Read 0x1bf + BOOLEAN bFwReadClear = FALSE; + u1Byte BufIndex = 0; + u1Byte WaitH2cLimmit = 0; + u1Byte BoxContent[4], BoxExtContent[4]; + u1Byte idx = 0; + + if (!GET_ROOT(priv)->bFWReady) + return 1; + + // 1. Find the last BOX number which has been writen. + BoxNum = priv->pshare->fw_q_fifo_count; //pHalData->LastHMEBoxNum; + switch (BoxNum) { + case 0: + BOXReg = REG_HMEBOX_0_8812; + BOXExtReg = REG_HMEBOX_EXT0_8812; + break; + case 1: + BOXReg = REG_HMEBOX_1_8812; + BOXExtReg = REG_HMEBOX_EXT1_8812; + break; + case 2: + BOXReg = REG_HMEBOX_2_8812; + BOXExtReg = REG_HMEBOX_EXT2_8812; + break; + case 3: + BOXReg = REG_HMEBOX_3_8812; + BOXExtReg = REG_HMEBOX_EXT3_8812; + break; + default: + break; + } + + // 2. Check if the box content is empty. + while (!bFwReadClear) { + bFwReadClear = CheckFwReadLastH2C_8812(priv, BoxNum); + if (WaitH2cLimmit++ >= 100) { + ioStatus = 1; + return ioStatus; + } else if (!bFwReadClear) { + delay_us(10); //us + } + } + + // 4. Fill the H2C cmd into box + memset(BoxContent, 0, sizeof(BoxContent)); + memset(BoxExtContent, 0, sizeof(BoxExtContent)); + + BoxContent[0] = ElementID; // Fill element ID + // RTPRINT(FFW, FW_MSG_H2C_CONTENT, ("[FW], Write ElementID BOXReg(%4x) = %2x \n", BOXReg, ElementID)); + + switch (CmdLen) { + case 1: + case 2: + case 3: { + //BoxContent[0] &= ~(BIT7); + memcpy((pu1Byte)(BoxContent) + 1, pCmdBuffer + BufIndex, CmdLen); + //For Endian Free. + for (idx = 0; idx < 4; idx++) { + RTL_W8(BOXReg + idx, BoxContent[idx]); + } + break; + } + case 4: + case 5: + case 6: + case 7: { + //BoxContent[0] |= (BIT7); + memcpy((pu1Byte)(BoxExtContent), pCmdBuffer + BufIndex + 3, (CmdLen - 3)); + memcpy((pu1Byte)(BoxContent) + 1, pCmdBuffer + BufIndex, 3); + //For Endian Free. + for (idx = 0 ; idx < 4 ; idx ++) { + RTL_W8( BOXExtReg + idx, BoxExtContent[idx]); + } + for (idx = 0 ; idx < 4 ; idx ++) { + RTL_W8( BOXReg + idx, BoxContent[idx]); + } + break; + } + + default: + // RTPRINT(FFW, FW_MSG_H2C_STATE, ("[FW], Invalid command len=%d!!!\n", CmdLen)); + ioStatus = 2; + return ioStatus; + break; + } + + if (++priv->pshare->fw_q_fifo_count > 3) + priv->pshare->fw_q_fifo_count = 0; + + // RTPRINT(FFW, FW_MSG_H2C_CONTENT, ("[FW], pHalData->LastHMEBoxNum = %d\n", pHalData->LastHMEBoxNum)); + return ioStatus; +} + + + + + + + +VOID +SetBcnCtrlReg_8812( + struct rtl8192cd_priv *priv, + IN u1Byte SetBits, + IN u1Byte ClearBits +) +{ + u1Byte tmp = RTL_R8(REG_BCN_CTRL_8812); + + tmp |= SetBits; + tmp &= ~ClearBits; + + RTL_W8(REG_BCN_CTRL_8812, tmp); +} + + +u1Byte +MRateIdxToARFRId8812( + struct rtl8192cd_priv *priv, + u1Byte RateIdx, + u1Byte RfType +) +{ + u1Byte Ret = 0; + + switch (RateIdx) { + + case RATR_INX_WIRELESS_NGB: + if (RfType == MIMO_1T1R) + Ret = 1; + else + Ret = 0; + break; + + case RATR_INX_WIRELESS_N: + case RATR_INX_WIRELESS_NG: + if (RfType == MIMO_1T1R) + Ret = 5; + else + Ret = 4; + break; + + case RATR_INX_WIRELESS_NB: + if (RfType == MIMO_1T1R) + Ret = 3; + else + Ret = 2; + break; + + case RATR_INX_WIRELESS_GB: + Ret = 6; + break; + + case RATR_INX_WIRELESS_G: + Ret = 7; + break; + + case RATR_INX_WIRELESS_B: + Ret = 8; + break; + + case RATR_INX_WIRELESS_MC: + if (!(priv->pmib->dot11BssType.net_work_type & WIRELESS_11A)) + Ret = 6; + else + Ret = 7; + break; + case RATR_INX_WIRELESS_AC_N: + if (RfType == MIMO_1T1R) + Ret = 10; + else + Ret = 9; + break; + + default: + Ret = 0; + break; + } + + return Ret; +} + +u1Byte +Get_RA_BW( + BOOLEAN bCurTxBW80MHz, + BOOLEAN bCurTxBW40MHz +) +{ + u1Byte BW = 0; + if (bCurTxBW80MHz) + BW = 2; + else if (bCurTxBW40MHz) + BW = 1; + else + BW = 0; + + return BW; +} + + + +#if 0 +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20, + WIRELESS_MODE_AC_5G = 0x40 +} WIRELESS_MODE; +#endif + +#define MIMO_PS_STATIC 0 +#define MIMO_PS_DYNAMIC 1 +#define MIMO_PS_NOLIMIT 3 + +#define FillOctetString(_os,_octet,_len) \ + (_os).Octet=(pu1Byte)(_octet); \ + (_os).Length=(_len); + + +u1Byte +Get_VHT_ENI( + u4Byte IOTAction, + u1Byte WirelessMode, + u4Byte ratr_bitmap +) +{ + u1Byte Ret = 0; + if (WirelessMode < WIRELESS_MODE_N_24G) + Ret = 0; + else if (WirelessMode == WIRELESS_MODE_N_24G || WirelessMode == WIRELESS_MODE_N_5G) { +#if 0 + //if(IOTAction == HT_IOT_VHT_HT_MIX_MODE) + { + if (ratr_bitmap & BIT20) // Mix , 2SS + Ret = 3; + else // Mix, 1SS + Ret = 2; + } +#else + Ret = 0; +#endif + + } else if (WirelessMode == WIRELESS_MODE_AC_5G) + Ret = 1; // VHT + + return (Ret << 4); +} + + + +BOOLEAN +Get_RA_ShortGI( + struct rtl8192cd_priv *priv, + struct stat_info * pEntry, + IN WIRELESS_MODE WirelessMode, + IN u1Byte ChnlBW +) +{ + BOOLEAN bShortGI; + + BOOLEAN bShortGI20MHz = FALSE, bShortGI40MHz = FALSE, bShortGI80MHz = FALSE; + + if ( WirelessMode == WIRELESS_MODE_N_24G || + WirelessMode == WIRELESS_MODE_N_5G || + WirelessMode == WIRELESS_MODE_AC_5G ) { + if (pEntry->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_) && + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M) { + bShortGI20MHz = TRUE; + } + if (pEntry->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_) + && priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M) { + bShortGI40MHz = TRUE; + } + #ifdef RTK_AC_SUPPORT + if (WirelessMode == WIRELESS_MODE_AC_5G && (GET_CHIP_VER(priv) != VERSION_8723B)) { + if ( (cpu_to_le32(pEntry->vht_cap_buf.vht_cap_info) & BIT(SHORT_GI80M_E)) + && priv->pmib->dot11nConfigEntry.dot11nShortGIfor80M) + bShortGI80MHz = TRUE; +#if 0 +// disable SGI when LDPC is enabled in AC mode + if((pEntry->is_realtek_sta) && (priv->pmib->dot11nConfigEntry.dot11nLDPC == 1) && + ((pEntry->ht_cap_len && cpu_to_le16(pEntry->ht_cap_buf.ht_cap_info) & _HTCAP_SUPPORT_RX_LDPC_) || + (pEntry->vht_cap_len && (cpu_to_le32(pEntry->vht_cap_buf.vht_cap_info) & BIT(RX_LDPC_E)))) ) { + bShortGI80MHz = bShortGI40MHz = bShortGI20MHz = 0; + } +#endif + } + #endif + } + + switch (ChnlBW) { + case HT_CHANNEL_WIDTH_20_40: + bShortGI = bShortGI40MHz; + break; + case HT_CHANNEL_WIDTH_80: + bShortGI = bShortGI80MHz; + break; + default: + case HT_CHANNEL_WIDTH_20: + bShortGI = bShortGI20MHz; + break; + } + return bShortGI; +} + + +u4Byte +RateToBitmap_2SSVHT( + pu1Byte pVHTRate +) +{ + + u1Byte i, j , tmpRate; + u4Byte RateBitmap = 0; + + for (i = j = 0; i < 4; i += 2, j += 10) { + tmpRate = (pVHTRate[0] >> i) & 3; + + switch (tmpRate) { + case 2: + RateBitmap = RateBitmap | (0x03ff << j); + break; + case 1: + RateBitmap = RateBitmap | (0x01ff << j); + break; + + case 0: + RateBitmap = RateBitmap | (0x00ff << j); + break; + + default: + break; + } + } + + return RateBitmap; +} + + +u4Byte +Get_VHT_HT_Mix_Ratrbitmap( + u4Byte IOTAction, + WIRELESS_MODE WirelessMode, + u4Byte HT_ratr_bitmap, + u4Byte VHT_ratr_bitmap +) +{ + u4Byte ratr_bitmap = 0; + if (WirelessMode == WIRELESS_MODE_N_24G || WirelessMode == WIRELESS_MODE_N_5G) { + /* + if(IOTAction == HT_IOT_VHT_HT_MIX_MODE) + ratr_bitmap = HT_ratr_bitmap | BIT28 | BIT29; + else + ratr_bitmap = HT_ratr_bitmap; + */ + } else + ratr_bitmap = VHT_ratr_bitmap; + + return ratr_bitmap; +} + + +#ifdef AC2G_256QAM +char is_ac2g(struct rtl8192cd_priv * priv) +{ + + unsigned char ac2g = 0; + + if((GET_CHIP_VER(priv)== VERSION_8812E) || (GET_CHIP_VER(priv)== VERSION_8881A)) + if(priv->pmib->dot11BssType.net_work_type & WIRELESS_11AC + && ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) == 0) + && (priv->pshare->rf_ft_var.ac2g_enable) + ) + ac2g = 1; + + return ac2g; + +} +#endif + +VOID +UpdateHalRAMask8812( + struct rtl8192cd_priv *priv, + struct stat_info *pEntry, + u1Byte rssi_level +) +{ + + u1Byte WirelessMode = WIRELESS_MODE_A; + u1Byte BW = HT_CHANNEL_WIDTH_20; + // u2Byte RateSet=0, i; + u1Byte MimoPs = MIMO_PS_NOLIMIT, MimoPs_enable = FALSE, ratr_index = 8, H2CCommand[7] = { 0}; + u4Byte ratr_bitmap = 0, IOTAction = 0; + u1Byte disable_cck_rate = FALSE; + u4Byte ratr_bitmap_msb = 0; + BOOLEAN bShortGI = FALSE, bCurTxBW80MHz = FALSE, bCurTxBW40MHz = FALSE; + struct stat_info *pstat = pEntry; + u1Byte rf_mimo_mode = get_rf_mimo_mode(priv); + #if CFG_HAL_RTK_AC_SUPPORT + unsigned int VHT_TxMap = priv->pmib->dot11acConfigEntry.dot11VHT_TxMap; + #endif + + if (pEntry == NULL) { + return; + } + { + if (pEntry->MIMO_ps & _HT_MIMO_PS_STATIC_) + MimoPs = MIMO_PS_STATIC; + else if (pEntry->MIMO_ps & _HT_MIMO_PS_DYNAMIC_) + MimoPs = MIMO_PS_DYNAMIC; + +#if 1 + BW = pstat->tx_bw; + if( BW > priv->pshare->CurrentChannelBW) + BW = priv->pshare->CurrentChannelBW; +#endif + add_RATid(priv, pEntry); + rssi_level = pstat->rssi_level; + ratr_bitmap = 0xfffffff; + // + // if(pstat->vht_cap_len && ( priv->pshare->rf_ft_var.support_11ac)) { + #ifdef RTK_AC_SUPPORT + if (pstat->vht_cap_len && (priv->pmib->dot11BssType.net_work_type & WIRELESS_11AC) && (!should_restrict_Nrate(priv, pstat)) && (GET_CHIP_VER(priv) != VERSION_8723B)) { //for 11ac logo + + if( (IS_B_CUT_8812(priv)) + && ((priv->pmib->dot11nConfigEntry.dot11nUse40M==0)||(BW == 0)) ) + { + //printk("\n !!! B CUT + AC STA + 20M, NO AC RATES !!!\n"); + //printk("AP=%dM, STA=%dM\n", (0x1<<(priv->pmib->dot11nConfigEntry.dot11nUse40M))*20 , (0x1<<(pstat->tx_bw))*20 ); + WirelessMode = WIRELESS_MODE_N_5G; + } + else{ + WirelessMode = WIRELESS_MODE_AC_5G; + } + + if (((le32_to_cpu(pstat->vht_cap_buf.vht_support_mcs[0]) >> 2) & 3) == 3) + rf_mimo_mode = MIMO_1T1R; + if (pstat->nss == 1) + rf_mimo_mode = MIMO_1T1R; + } else + #endif + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && (!should_restrict_Nrate(priv, pstat))) { + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && (priv->pmib->dot11RFEntry.dot11channel > 14)) + WirelessMode = WIRELESS_MODE_N_5G; + else + WirelessMode = WIRELESS_MODE_N_24G; + if ((pstat->tx_ra_bitmap & 0xff00000) == 0) + rf_mimo_mode = MIMO_1T1R; + } else if (((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) && + (priv->pmib->dot11RFEntry.dot11channel <= 14)) { + WirelessMode = WIRELESS_MODE_G; + } else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && + (priv->pmib->dot11RFEntry.dot11channel > 14) && + ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G))) { + WirelessMode = WIRELESS_MODE_A; + } else if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11B) { + WirelessMode = WIRELESS_MODE_B; + } + + pstat->WirelessMode = WirelessMode; + + if (WirelessMode == WIRELESS_MODE_AC_5G) { + ratr_bitmap &= 0xfff; + #ifdef RTK_AC_SUPPORT + if(GET_CHIP_VER(priv) != VERSION_8723B) { + int tmp32 = (pstat->vht_cap_buf.vht_support_mcs[0]); + // special 1SS & 2SS + if (pstat->nss == 1) + tmp32 |= cpu_to_le32(0xfffc); + else if ((pstat->nss == 2) && (le32_to_cpu(tmp32) & 0x0c) == 0x0c) + tmp32 &= cpu_to_le32(0xfffffff3); + // + ratr_bitmap |= RateToBitmap_2SSVHT((pu1Byte)&tmp32) << 12; + } + #endif + if (IS_TEST_CHIP(priv)) { // Test Chip... 2SS MCS7 + if (rf_mimo_mode == MIMO_1T1R) + ratr_bitmap &= 0x000fffff; + else + ratr_bitmap &= 0x3FCFFFFF; + } else { // MP Chip... MCS0~9 + if (rf_mimo_mode == MIMO_1T1R) + ratr_bitmap &= 0x003fffff; + } + + if (BW == HT_CHANNEL_WIDTH_80) + bCurTxBW80MHz = TRUE; + } +// if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40)) +// bCurTxBW40MHz = TRUE; + + if (priv->pshare->is_40m_bw && (BW == HT_CHANNEL_WIDTH_20_40) +#ifdef WIFI_11N_2040_COEXIST + && !((((GET_MIB(priv))->dot11OperationEntry.opmode) & WIFI_AP_STATE) + && COEXIST_ENABLE + && (priv->bg_ap_timeout || orForce20_Switch20Map(priv) + + )) +#endif + ) + + bCurTxBW40MHz = TRUE; + + } + + if(((GET_MIB(priv))->dot11OperationEntry.opmode) & WIFI_STATION_STATE) { + if(((GET_MIB(priv))->dot11Bss.t_stamp[1] & 0x6) == 0) { + bCurTxBW40MHz = bCurTxBW80MHz = FALSE; + } + } + BW = Get_RA_BW(bCurTxBW80MHz, bCurTxBW40MHz); + #if CFG_HAL_RTK_AC_SUPPORT + if(BW == 0) + { + //remove MCS9 for BW=20m + if (rf_mimo_mode == MIMO_1T1R) + VHT_TxMap &= ~(BIT(9)); + else if (rf_mimo_mode == MIMO_2T2R) + VHT_TxMap &= ~(BIT(9)|BIT(19)); + } + #endif + +#if 1 + + bShortGI = Get_RA_ShortGI(priv, pEntry, WirelessMode, BW); + pstat->tx_bw_fw = BW; + + if (MimoPs <= MIMO_PS_DYNAMIC) MimoPs_enable = TRUE; - phydm_UpdateHalRAMask(ODMPTR, WirelessMode, rf_mimo_mode, BW, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap, rssi_level); - pstat->ratr_idx = phydm_rate_id_mapping(ODMPTR, WirelessMode, rf_mimo_mode, BW); - -#else - // assign band mask and rate bitmap - switch (WirelessMode) { - case WIRELESS_MODE_B: { - ratr_index = RATR_INX_WIRELESS_B; - if (ratr_bitmap & 0x0000000c) //11M or 5.5M enable - ratr_bitmap &= 0x0000000d; - else - ratr_bitmap &= 0x0000000f; - } - break; - - case WIRELESS_MODE_G: { - ratr_index = RATR_INX_WIRELESS_GB; - - if (rssi_level == 1) - ratr_bitmap &= 0x00000f00; - else if (rssi_level == 2) - ratr_bitmap &= 0x00000ff0; - else - ratr_bitmap &= 0x00000ff5; - } - break; - - case WIRELESS_MODE_A: { - ratr_index = RATR_INX_WIRELESS_G; - ratr_bitmap &= 0x00000ff0; - } - break; - - case WIRELESS_MODE_N_24G: - case WIRELESS_MODE_N_5G: { - if (WirelessMode == WIRELESS_MODE_N_24G) - ratr_index = RATR_INX_WIRELESS_NGB; - else - ratr_index = RATR_INX_WIRELESS_NG; - - // if(MimoPs <= MIMO_PS_DYNAMIC) - if (MimoPs < MIMO_PS_DYNAMIC) { - if (rssi_level == 1) - ratr_bitmap &= 0x000f0000; - else if (rssi_level == 2) - ratr_bitmap &= 0x000ff000; - else - ratr_bitmap &= 0x000ff005; - } else { - if (rf_mimo_mode == MIMO_1T1R) { - if (bCurTxBW40MHz) { - if (rssi_level == 1) - ratr_bitmap &= 0x000f0000; - else if (rssi_level == 2) - ratr_bitmap &= 0x000ff000; - else - ratr_bitmap &= 0x000ff015; - } else { - if (rssi_level == 1) - ratr_bitmap &= 0x000f0000; - else if (rssi_level == 2) - ratr_bitmap &= 0x000ff000; - else - ratr_bitmap &= 0x000ff005; - } - } else { - if (bCurTxBW40MHz) { - if (rssi_level == 1) - ratr_bitmap &= 0x0fff0000; - else if (rssi_level == 2) - ratr_bitmap &= 0x0ffff000; - else - ratr_bitmap &= 0x0ffff015; - } else { - if (rssi_level == 1) - ratr_bitmap &= 0x0fff0000; - else if (rssi_level == 2) - ratr_bitmap &= 0x0ffff000; - else - ratr_bitmap &= 0x0ffff005; - } - } - } - } - break; -#ifdef RTK_AC_SUPPORT - case WIRELESS_MODE_AC_5G: { - ratr_index = RATR_INX_WIRELESS_AC_N; - - if(pstat->rssi && priv->pshare->rf_ft_var.rssi_ra) - { - if (pstat->rssi >= priv->pshare->rf_ft_var.rssi_thd1) - rssi_level = 1; - else if (pstat->rssi >= priv->pshare->rf_ft_var.rssi_thd2) - rssi_level = 2; - else - rssi_level = 3; - - if(pstat->rssi_level_ac && (pstat->rssi_level_ac==rssi_level)) - return; - - if (rf_mimo_mode == MIMO_1T1R) - { - if(rssi_level == 1) // add by Gary for ac-series - ratr_bitmap &= 0x003f8000; - else if (rssi_level == 2) - ratr_bitmap &= 0x003ff000; - else - ratr_bitmap &= 0x003ff010; - } - else - { - if(rssi_level == 1) // add by Gary for ac-series - ratr_bitmap &= 0xfe3f8000; // VHT 2SS MCS3~9 - else if (rssi_level == 2) - ratr_bitmap &= 0xfffff000; // VHT 2SS MCS0~9 - else - ratr_bitmap &= 0xfffff010; // All - } - - //panic_printk("[%s][%d] rssi_level=[%d->%d] ratr_bitmap=0x%x\n", __FUNCTION__, __LINE__, - //pstat->rssi_level_ac, rssi_level, ratr_bitmap); - - pstat->rssi_level_ac = rssi_level; - - } - else - { - if (rf_mimo_mode == MIMO_1T1R) - ratr_bitmap &= 0x003ff010; - else - ratr_bitmap &= 0xfffff010; - } - - ratr_bitmap &= (VHT_TxMap << 12)|0xff0; - - } - break; -#endif - default: - ratr_index = RATR_INX_WIRELESS_NGB; - - if (rf_mimo_mode == MIMO_1T1R) - ratr_bitmap &= 0x000ff0ff; - else - ratr_bitmap &= 0x0ffff0ff; - break; - } - - bShortGI = Get_RA_ShortGI(priv, pEntry, WirelessMode, BW); - - - - pstat->ratr_idx = MRateIdxToARFRId8812(priv, ratr_index, rf_mimo_mode) ; - pstat->tx_bw_fw = BW; - -#endif - - -#ifdef AC2G_256QAM - - if(is_ac2g(priv) && pstat->vht_cap_len ) - { - printk("AC2G STA Associated !!\n"); - if (rf_mimo_mode == MIMO_1T1R) - { - //bShortGI = 1; - ratr_bitmap = 0x003ff015; - - if(BW == 2) - pstat->ratr_idx = 10; - else - pstat->ratr_idx = 11; - - if(BW == 0) - VHT_TxMap = 0x1ff; - else - VHT_TxMap = 0x3ff; - - } - else if (rf_mimo_mode == MIMO_2T2R) - { - // bShortGI = 0; - ratr_bitmap = 0xffcff015; - - if(BW == 2) - pstat->ratr_idx = 9; - else - pstat->ratr_idx = 12; - - if(BW == 0) - VHT_TxMap = 0x7fdff; - else - VHT_TxMap = 0xfffff; - } - - ratr_bitmap &= ((VHT_TxMap << 12)|0xfff); - - pstat->WirelessMode = WIRELESS_MODE_AC_24G; - } - -#endif - - // for debug, set vht_txmap for RAMask - #if CFG_HAL_RTK_AC_SUPPORT - if (WirelessMode == WIRELESS_MODE_AC_5G) - ratr_bitmap &= (VHT_TxMap << 12)|0xff0; - #endif - - H2CCommand[0] = REMAP_AID(pstat); - H2CCommand[1] = (pstat->ratr_idx) | (bShortGI ? 0x80 : 0x00) ; - H2CCommand[2] = BW | Get_VHT_ENI(IOTAction, WirelessMode, ratr_bitmap); - - - H2CCommand[2] |= BIT6; // DisableTXPowerTraining - - H2CCommand[3] = (u1Byte)(ratr_bitmap & 0x000000ff); - H2CCommand[4] = (u1Byte)((ratr_bitmap & 0x0000ff00) >> 8); - H2CCommand[5] = (u1Byte)((ratr_bitmap & 0x00ff0000) >> 16); - H2CCommand[6] = (u1Byte)((ratr_bitmap & 0xff000000) >> 24); - - FillH2CCmd8812(priv, H2C_8812_RA_MASK, 7, H2CCommand); - - SetBcnCtrlReg_8812(priv, BIT3, 0); - /* - panic_printk("UpdateHalRAMask8812E(): bitmap = %x ratr_index = %1x, MacID:%x, ShortGI:%x, MimoPs=%d\n", - ratr_bitmap, pstat->ratr_idx, (pstat->aid), bShortGI, MimoPs); - - panic_printk("Cmd: %02x, %02x, %02x, %02x, %02x, %02x, %02x \n", - H2CCommand[0] ,H2CCommand[1], H2CCommand[2], - H2CCommand[3] ,H2CCommand[4], H2CCommand[5], H2CCommand[6] ); - */ -} -void -UpdateHalMSRRPT8812( - struct rtl8192cd_priv *priv, - struct stat_info *pstat, - unsigned char opmode -) -{ - u1Byte H2CCommand[3] = { 0}; - - update_remapAid(priv,pstat); - H2CCommand[0] = opmode & 0x01; - H2CCommand[1] = REMAP_AID(pstat) & 0xff; - H2CCommand[2] = 0; - FillH2CCmd8812(priv, H2C_8812_MSRRPT, 3, H2CCommand); - - // panic_printk("UpdateHalMSRRPT8812 Cmd: %02x, %02x, %02x \n", - // H2CCommand[0] ,H2CCommand[1], H2CCommand[2]); -} -#if 0 -void check_txrate_by_reg_8812(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - unsigned char initial_rate = 0x7f; - unsigned char legacyRA = 0 ; - unsigned int autoRate1 = 0; - -// if (!priv->pshare->rf_ft_var.update_rainfo) -// return; - - RTL_W8(0x8d, 0x01); - RTL_W8(0x8f, 0x40); - - if ( should_restrict_Nrate(priv, pstat) && is_fixedMCSTxRate(priv)) - legacyRA = 1; - - if (pstat->sta_in_firmware == 1) { - - -#ifdef WDS - if (pstat->state & WIFI_WDS) { - autoRate1 = (priv->pmib->dot11WdsInfo.entry[pstat->wds_idx].txRate == 0) ? 1 : 0; - } else -#endif - { - autoRate1 = priv->pmib->dot11StationConfigEntry.autoRate; - } - - if (autoRate1 || legacyRA) { - RTL_W8(0x8c, REMAP_AID(pstat) & 0x1f); - initial_rate = RTL_R8(0x2f0); - if ((initial_rate & 0x7f) == 0x7f) - return; - - - if ((initial_rate & 0x3f) < 12) { - pstat->current_tx_rate = dot11_rate_table[initial_rate & 0x3f]; - pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; - } else { - if ((initial_rate & 0x3f) >= 44) - pstat->current_tx_rate = VHT_RATE_ID + ((initial_rate & 0x3f) - 44); - else - pstat->current_tx_rate = HT_RATE_ID + ((initial_rate & 0x3f) - 12); - - if (initial_rate & BIT(7)) - pstat->ht_current_tx_info |= TX_USE_SHORT_GI; - else - pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; - } - - priv->pshare->current_tx_rate = pstat->current_tx_rate; - priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; - } - } -} -#endif - - -void odm_TXPowerTrackingCallback_ThermalMeter_8812E(struct rtl8192cd_priv * priv) -{ - unsigned char ThermalValue = 0, delta, channel, is_decrease, rf_mimo_mode; - unsigned char ThermalValue_AVG_count = 0; - unsigned int ThermalValue_AVG = 0; - int ele_D; - char OFDM_index[2]; - unsigned int i = 0, rf = 2; - - unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur - - rf_mimo_mode = get_rf_mimo_mode(priv); - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - if (priv->pshare->Power_tracking_on_8812 == 0) { - priv->pshare->Power_tracking_on_8812 = 1; - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x03); - return; - } else { - priv->pshare->Power_tracking_on_8812 = 0; - ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E - //printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); - } - - switch (rf_mimo_mode) { - case MIMO_1T1R: - rf = 1; - break; - case MIMO_2T2R: - rf = 2; - break; - default: - panic_printk("%s:%d get_rf_mimo_mode error!\n", __FUNCTION__, __LINE__); - break; - } - #ifdef CONFIG_RTL_8812_SUPPORT - if(GET_CHIP_VER(priv) != VERSION_8723B) { - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[0] = (unsigned char)i; - //printk("PathA 0xc1c[32:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]); - break; - } - } - - //Query OFDM path B default setting - if (rf_mimo_mode == MIMO_2T2R) { - ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[1] = (unsigned char)i; - //printk("PathB 0xe1c[31:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); - break; - } - } - } - } - #endif - /* Initialize */ - if (!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - - } - - /* calculate average thermal meter */ - { - priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; - priv->pshare->ThermalValue_AVG_index_8812++; - if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) - priv->pshare->ThermalValue_AVG_index_8812 = 0; - - for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { - if (priv->pshare->ThermalValue_AVG_8812[i]) { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); - } - } - - if (ThermalValue != priv->pshare->ThermalValue) { - //printk("\n******** START:%s() ********\n", __FUNCTION__); - //printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); - - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - if (1) { //AC2G_256QAM (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - if (is_decrease) { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[i]); - //printk(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); - } - } else { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); - //printk(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); - } - } - } -#endif - #ifdef CONFIG_RTL_8812_SUPPORT - if(GET_CHIP_VER(priv) != VERSION_8723B) { - PHY_SetBBReg(priv, 0xc1c, 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[0]]); - if (rf_mimo_mode == MIMO_2T2R) - PHY_SetBBReg(priv, 0xe1c, 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[1]]); - } - #endif - - } -/* - printk("PathA >>>>> 0xc1c[31:21] = 0x%x, OFDM_index:%d\n", PHY_QueryBBReg(priv, 0xc1c, 0xffe00000), OFDM_index[0]); - if (rf_mimo_mode == MIMO_2T2R) - printk("PathB >>>>> 0xe1c[31:21] = 0x%x, OFDM_index:%d\n", PHY_QueryBBReg(priv, 0xe1c, 0xffe00000), OFDM_index[1]); - printk("\n******** END:%s() ********\n", __FUNCTION__); -*/ - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - for (i = 0 ; i < rf ; i++) - priv->pshare->OFDM_index[i] = OFDM_index[i]; - } -} - - -void requestTxReport_8812(struct rtl8192cd_priv *priv) -{ - unsigned char h2cresult, counter = 20; - struct stat_info *sta; - unsigned char H2CCommand[2] = {0xff, 0xff}; - - if ( priv->pshare->sta_query_idx == -1) - return; - -#ifdef TXRETRY_CNT - priv->pshare->sta_query_retry_idx = priv->pshare->sta_query_idx; -#endif - - while (is_h2c_buf_occupy(priv)) { - delay_ms(2); - if (--counter == 0) - break; - } - - if (!counter) - return; - - sta = findNextSTA(priv, &priv->pshare->sta_query_idx); - if (sta) - H2CCommand[0] = REMAP_AID(sta); - else { - priv->pshare->sta_query_idx = -1; - return; - } - - sta = findNextSTA(priv, &priv->pshare->sta_query_idx); - if (sta) { - H2CCommand[1] = REMAP_AID(sta); - } else { - priv->pshare->sta_query_idx = -1; - } - - //WDEBUG("\n"); - h2cresult = FillH2CCmd8812(priv, H2C_8812_TX_REPORT, 2 , H2CCommand); - //WDEBUG("h2cresult=%d\n",h2cresult); - - -} - -#ifdef TXRETRY_CNT -void requestTxRetry_8812(struct rtl8192cd_priv *priv) -{ - unsigned char h2cresult, counter = 20; - struct stat_info *sta; - unsigned char H2CCommand[3] = {0xff, 0xff, 0x02}; - - if ( priv->pshare->sta_query_retry_idx == -1) - return; - - while (is_h2c_buf_occupy(priv)) { - delay_ms(2); - if (--counter == 0) - break; - } - - if (!counter) - return; - - sta = findNextSTA(priv, &priv->pshare->sta_query_retry_idx); - if (sta) - H2CCommand[0] = REMAP_AID(sta); - else { - priv->pshare->sta_query_retry_idx = -1; - return; - } - - sta = findNextSTA(priv, &priv->pshare->sta_query_retry_idx); - if (sta) { - H2CCommand[1] = REMAP_AID(sta); - } else { - priv->pshare->sta_query_retry_idx = -1; - } - - //WDEBUG("\n"); - priv->pshare->sta_query_retry_macid[0] = H2CCommand[0]; - priv->pshare->sta_query_retry_macid[1] = H2CCommand[1]; - h2cresult = FillH2CCmd8812(priv, H2C_8812_TX_REPORT, 3 , H2CCommand); - //WDEBUG("h2cresult=%d\n",h2cresult); - -} -#endif - -/*C2H_isr_8812() -AP Req Txrpt -"Start Address:USB:0xFD20PCIe/USB: 0x01A0" -|ID|SEQ |CONTENT |LEN|TRIGGER| ------------------------------------------ -|0 | 1 |2~13 |14 |15 | ------------------------------------------ - -|ID=0x04|SEQ|STA1 MACID(1B)|Tx_ok1(2B)|Tx_fail1(2B)|initial rate1(1B)|STA2 MACID(1B)|Tx_ok2(2B)|Tx_fail2(2B)|Initial rate2(1B)|Len=12(1B)|FF(1B)| -*/ -#if 0 -void C2H_isr_8812(struct rtl8192cd_priv *priv) -{ - struct tx_rpt rpt1; - int j, C2H_ID; - unsigned char MacID = 0xff; - int idx = 0x1a2; -#ifndef SMP_SYNC - unsigned long flags=0; -#endif - - //WDEBUG("\n"); - - SAVE_INT_AND_CLI(flags); - C2H_ID = RTL_R8(0x1a0); - - if ( (C2H_ID) == C2H_8812_TX_REPORT ) { - - for (j = 0; j < 2; j++) { - - MacID = RTL_R8(idx); - if (MacID == 0xff) - continue; - - rpt1.macid = MacID & TXdesc_92E_MacIdMask; - - if (rpt1.macid) { - - rpt1.txok = (RTL_R8(idx + 2)<<8) | RTL_R8(idx + 1); - rpt1.txfail = (RTL_R8(idx + 4)<<8) | RTL_R8(idx + 3); -/* -#ifdef _BIG_ENDIAN_ - rpt1.txok = le16_to_cpu(RTL_R16(idx + 1)); - rpt1.txfail = le16_to_cpu(RTL_R16(idx + 3)); -#else - rpt1.txok = be16_to_cpu(RTL_R16(idx + 1)); - rpt1.txfail = be16_to_cpu(RTL_R16(idx + 3)); -#endif -*/ - rpt1.initil_tx_rate = RTL_R8(idx + 5); - txrpt_handler(priv, &rpt1); // add inital tx rate handle for 8812E - } - idx += 6; - } - } - -// check sounding BW also... - - - - RTL_W8( 0x1af, 0); - if ( (C2H_ID) == C2H_8812_TX_REPORT ) - requestTxReport_8812(priv); - RESTORE_INT(flags); -} -#endif - -VOID -C2HRaReportHandler_8812( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -) -{ - u1Byte Rate = CmdBuf[0] & 0x3F; - u1Byte MacId = CmdBuf[1]; - BOOLEAN bLDPC = CmdBuf[2] & BIT0; - BOOLEAN bTxBF = (CmdBuf[2] & BIT1) >> 1; -#if (BEAMFORMING_SUPPORT == 1) - Beamforming_SetTxBFen(priv, MacId, bTxBF); -#endif -} - -VOID -C2HTxTxReportHandler_8812( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -) -{ - struct tx_rpt rpt1; - int k=0, j=0; - for(j=0; j<2; j++) { - rpt1.macid= CmdBuf[k]; - rpt1.txok = CmdBuf[k+1] | ((short)CmdBuf[k+2]<<8); - rpt1.txfail = CmdBuf[k+3] | ((short)CmdBuf[k+4]<<8); - rpt1.initil_tx_rate = CmdBuf[k+5]; - if(rpt1.macid != 0xff) - txrpt_handler(priv, &rpt1); - k+=6; - } -} - -#if (BEAMFORMING_SUPPORT == 1) -VOID C2HTxBeamformingHandler_8812( struct rtl8192cd_priv *priv, pu1Byte CmdBuf, u1Byte CmdLen); -#endif - -VOID -_C2HContentParsing8812( - struct rtl8192cd_priv *priv, - u1Byte c2hCmdId, - u1Byte c2hCmdLen, - pu1Byte tmpBuf -) -{ - - switch(c2hCmdId) - { - case C2H_8812_TXBF: -#if (BEAMFORMING_SUPPORT == 1) - C2HTxBeamformingHandler_8812(priv, tmpBuf, c2hCmdLen); -#endif - break; - case C2H_8812_TXPERORT: -#ifdef TXREPORT - C2HTxTxReportHandler_8812(priv, tmpBuf, c2hCmdLen); - - #ifdef TXRETRY_CNT - requestTxRetry_8812(priv); - #else - requestTxReport_8812(priv); - #endif - -#endif - break; - -#ifdef TXRETRY_CNT - case C2H_8812_TXRETRY: - C2HTxTxRetryHandler(priv, tmpBuf); - requestTxReport_8812(priv); - break; -#endif - - default: - if(!(phydm_c2H_content_parsing(ODMPTR, c2hCmdId, c2hCmdLen, tmpBuf))) { - printk("[C2H], Unkown packet!! CmdId(%#X)!\n", c2hCmdId); - } - break; - } -} - -VOID -C2HPacketHandler_8812( - struct rtl8192cd_priv *priv, - pu1Byte Buffer, - u1Byte Length - ) -{ - u1Byte c2hCmdId=0, c2hCmdSeq=0, c2hCmdLen=0; - pu1Byte tmpBuf=NULL; - c2hCmdId = Buffer[0]; - c2hCmdSeq = Buffer[1]; -/* -#ifdef CONFIG_WLAN_HAL - if(c2hCmdId==C2H_88XX_EXTEND_IND) - { - c2hCmdLen = Length; - tmpBuf = Buffer; - C2HExtEventHandler88XX(NULL, c2hCmdId, c2hCmdLen, tmpBuf); - } - else -#endif -*/ - { - c2hCmdLen = Length -2; - tmpBuf = Buffer+2; - - _C2HContentParsing8812(priv, c2hCmdId, c2hCmdLen, tmpBuf); - } -} - -#if (BEAMFORMING_SUPPORT == 1) -VOID -SetBeamformRfMode8812( - struct rtl8192cd_priv *priv, - PRT_BEAMFORMING_INFO pBeamformingInfo - ) -{ - u1Byte i; - u4Byte bSelfBeamformer = FALSE; - u4Byte bSelfBeamformee = FALSE; - RT_BEAMFORMING_ENTRY BeamformEntry; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - - BeamformCap = Beamforming_GetBeamCap(priv, pBeamformingInfo); - - if(BeamformCap == pBeamformingInfo->BeamformCap) - return; - else - pBeamformingInfo->BeamformCap = BeamformCap; - if(get_rf_mimo_mode(priv) == MIMO_1T1R) - return; - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000,0x1); // RF Mode table write enable - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000,0x1); // RF Mode table write enable - - bSelfBeamformer = BeamformCap & BEAMFORMER_CAP; - bSelfBeamformee = BeamformCap & BEAMFORMEE_CAP; - - if(bSelfBeamformer) - { - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000,0x3); // Select RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff,0xE26BF); // Enable TXIQGEN in RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff,0xE26BF); // Enable TXIQGEN in RX mode - } - else if (!priv->pmib->dot11RFEntry.tx2path) - { - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff,0xC26BF); // Disable TXIQGEN in RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff,0xC26BF); // Disable TXIQGEN in RX mode - } - PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000,0x0); // RF Mode table write disable - PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000,0x0); // RF Mode table write disable - - if(bSelfBeamformer) { - PHY_SetBBReg(priv, rTxPath_Jaguar, bMaskByte1, 0x33); -#ifdef RF_MIMO_SWITCH - priv->pshare->rf_phy_bb_backup[1] &= ~ bMaskByte1; - priv->pshare->rf_phy_bb_backup[1] |= 0x3300; -#endif - - } else { - PHY_SetBBReg(priv, rTxPath_Jaguar, bMaskByte1, 0x11); -#ifdef RF_MIMO_SWITCH - priv->pshare->rf_phy_bb_backup[1] &= ~ bMaskByte1; - priv->pshare->rf_phy_bb_backup[1] |= 0x1100; -#endif - } -} -VOID -SetBeamformEnter8812( - struct rtl8192cd_priv *priv, - u1Byte BFerBFeeIdx - ) -{ - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u4Byte CSI_Param; - PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); - RT_BEAMFORMING_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0; - - SetBeamformRfMode8812(priv, pBeamformingInfo); - - if(get_rf_mimo_mode(priv) == MIMO_2T2R) - RTL_W32(0x9B4, 0x01081008); - - if((pBeamformingInfo->BeamformCap & BEAMFORMEE_CAP) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) - { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; - - if (!IS_TEST_CHIP(priv)) { - if (IS_C_CUT_8812(priv)) - RTL_W16( REG_SND_PTCL_CTRL_8812, 0x2CB); // Disable SIG-B CRC8 check - else - RTL_W16( REG_SND_PTCL_CTRL_8812, 0x0B); - } - else - RTL_W16( REG_SND_PTCL_CTRL_8812, 0x1B); - - // MAC addresss/Partial AID of Beamformer - if(BFerIdx == 0) - { - for(i = 0; i < 6 ; i++) - RTL_W8( (REG_BFMER0_INFO_8812+i), BeamformerEntry.MacAddr[i]); - - //RTL_W16( REG_BFMER0_INFO_8812+6, BeamformerEntry.P_AID); - } - else - { - for(i = 0; i < 6 ; i++) - RTL_W8( (REG_BFMER1_INFO_8812+i), BeamformerEntry.MacAddr[i]); - - //RTL_W16( REG_BFMER1_INFO_8812+6, BeamformerEntry.P_AID); - } - - // CSI report parameters of Beamformer - if((BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) ||(BeamformerEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) ) - CSI_Param = 0x01090109; - else - CSI_Param = 0x03090309; - - RTL_W32( REG_CSI_RPT_PARAM_BW20_8812, CSI_Param); - RTL_W32( REG_CSI_RPT_PARAM_BW40_8812, CSI_Param); - RTL_W32( REG_CSI_RPT_PARAM_BW80_8812, CSI_Param); - - // Timeout value for MAC to leave NDP_RX_standby_state 60 us - // RTL_W8( REG_SND_PTCL_CTRL_8812+3, 0x3C); - RTL_W8( REG_SND_PTCL_CTRL_8812+3, 0x50); // // ndp_rx_standby_timer - } - - if((pBeamformingInfo->BeamformCap & BEAMFORMER_CAP) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) - { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - - if(OPMODE & WIFI_ADHOC_STATE) - STAid = BeamformeeEntry.AID; - else - STAid = BeamformeeEntry.P_AID; - - // P_AID of Beamformee & enable NDPA transmission - if(BFeeIdx == 0) - { - RTL_W16( REG_TXBF_CTRL_8812, STAid); - RTL_W8( REG_TXBF_CTRL_8812+3, RTL_R8( REG_TXBF_CTRL_8812+3)|BIT6|BIT7|BIT4); - } - else - { - RTL_W16( REG_TXBF_CTRL_8812+2, STAid |BIT14| BIT15|BIT12); - } - - // CSI report parameters of Beamformee - if(BFeeIdx == 0) - { - // Get BIT24 & BIT25 - u1Byte tmp = RTL_R8( REG_BFMEE_SEL_8812+3) & 0x3; - RTL_W8( REG_BFMEE_SEL_8812+3, tmp | 0x60); - RTL_W16( REG_BFMEE_SEL_8812, STAid | BIT9); - } - else - { - // Set BIT25 - RTL_W16( REG_BFMEE_SEL_8812+2, STAid | 0xE200); - } - - // if(pHalData->bIsMPChip == FALSE) - if (IS_TEST_CHIP(priv)) - { - // VHT category value - RTL_W8( REG_SND_PTCL_CTRL_8812+1, ACT_CAT_VHT); - // NDPA subtype - RTL_W8( REG_SND_PTCL_CTRL_8812+2, Type_NDPA >> 4); - } - - Beamforming_Notify(priv); - } -} - - -VOID -SetBeamformLeave8812( - struct rtl8192cd_priv *priv, - u1Byte Idx - ) -{ - PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); - RT_BEAMFORMING_ENTRY BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMER_ENTRY BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; - - /* Clear P_AID of Beamformee - * Clear MAC addresss of Beamformer - * Clear Associated Bfmee Sel - */ - if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) - { - if(Idx == 0) - { - ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformeeEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); - RTL_W16( REG_TXBF_CTRL_8812, 0); - RTL_W16( REG_BFMEE_SEL_8812, 0); - } - else - { - ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformeeEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); - RTL_R16( (REG_TXBF_CTRL_8812+2) & 0xF000); - RTL_W16( REG_BFMEE_SEL_8812+2, RTL_R16( REG_BFMEE_SEL_8812+2) & 0x60); - } - } - - if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) - { - if(Idx == 0) - { - ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformerEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); - RTL_W32( REG_BFMER0_INFO_8812, 0); - RTL_W16( REG_BFMER0_INFO_8812+4, 0); - } - else - { - ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformerEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); - RTL_W32( REG_BFMER1_INFO_8812, 0); - RTL_W16( REG_BFMER1_INFO_8812+4, 0); - } - } - - if(((pBeamformingInfo->BeamformerEntry[0]).BeamformEntryCap == BEAMFORMING_CAP_NONE) - && ((pBeamformingInfo->BeamformerEntry[1]).BeamformEntryCap == BEAMFORMING_CAP_NONE)){ - ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, All BeamformerEntryCap == NONE, STOP feedback CSI\n", __FUNCTION__, Idx)); - RTL_W8( REG_SND_PTCL_CTRL_8812, 0xC8); - } - -} -VOID -SetBeamformStatus8812( - struct rtl8192cd_priv *priv, - u1Byte Idx - ) -{ - u2Byte BeamCtrlVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); - RT_BEAMFORMING_ENTRY BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; - if(OPMODE & WIFI_ADHOC_STATE) - BeamCtrlVal = BeamformEntry.MacId; - else - BeamCtrlVal = BeamformEntry.P_AID; - if(Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8812; - else - { - BeamCtrlReg = REG_TXBF_CTRL_8812+2; - BeamCtrlVal |= BIT12 | BIT14|BIT15; - } - if((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED)&& (priv->pshare->rf_ft_var.applyVmatrix)) - { - if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20_40) - BeamCtrlVal |= (BIT9 | BIT10); - else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9 | BIT10 | BIT11); - } else { - BeamCtrlVal &= ~(BIT9|BIT10|BIT11); - } - RTL_W16(BeamCtrlReg, BeamCtrlVal); -} -//2REG_C2HEVT_CLEAR -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - - - -VOID Beamforming_NDPARate_8812( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate) -{ - - u2Byte NDPARate = Rate; - - if(NDPARate == 0) - { -// ??? -#if 0 - if(Mode == 1 || Mode == 4) - NDPARate = 0x0c; //MGN_MCS0; - else - NDPARate = 0x2c; //MGN_VHT1SS_MCS0; -#else - if(priv->pshare->rssi_min > 30) // link RSSI > 30% - NDPARate = 8; //MGN_24M - else - NDPARate = 4; //MGN_6M - -#endif - } - - if(NDPARate < 0x0c) - BW = HT_CHANNEL_WIDTH_20; - - RTL_W8(REG_NDPA_OPT_CTRL_8812, (NDPARate<<2) | (BW & 0x03)); - - -} - -VOID -C2HTxBeamformingHandler_8812( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -) -{ - u1Byte status = CmdBuf[0] & BIT0; - Beamforming_End(priv, status); -} - -VOID HW_VAR_HW_REG_TIMER_START_8812(struct rtl8192cd_priv *priv) -{ - RTL_W8(0x15F, 0x0); - RTL_W8(0x15F, 0x5); - -} - -VOID HW_VAR_HW_REG_TIMER_INIT_8812(struct rtl8192cd_priv *priv, int t) -{ - RTL_W8(0x164, 1); - RTL_W16(0x15C, t); - -} - -VOID HW_VAR_HW_REG_TIMER_STOP_8812(struct rtl8192cd_priv *priv) -{ - RTL_W8(0x15F, 0); -} - - -VOID _Beamforming_CLK(struct rtl8192cd_priv *priv) -{ - u2Byte u2btmp; - u1Byte QueueID, Count = 0, u1btmp; -#ifndef SMP_SYNC - unsigned long flags; -#endif - unsigned int loop = 5; - - if(priv->pshare->bScanInProcess==TRUE) - return; - - SAVE_INT_AND_CLI(flags); - - // Stop Usb TxDMA - RTL_W16(PCIE_CTRL_REG, 0xff00 ); - - // Wait TXFF empty - for(Count = 0; Count < loop; Count++) { - u2btmp = RTL_R16(REG_TXPKT_EMPTY_8812); - u2btmp = u2btmp & 0x7ff; - if(u2btmp != 0x7ff) { - delay_ms(10); - continue; - } else { - break; - } - } - - // TX pause - RTL_W8(REG_TXPAUSE_8812, 0xFF); - - // Wait TX State Machine OK - for(Count = 0; Count < 100; Count++) { - if(RTL_R32(REG_SCH_TXCMD_8812) != 0) - continue; - else - break; - } - - // Stop RX DMA path - u1btmp = RTL_R8(REG_RXDMA_CONTROL_8812); - RTL_W8(REG_RXDMA_CONTROL_8812, u1btmp| BIT2); - - for(Count = 0; Count < loop; Count++) { - u1btmp = RTL_R8( REG_RXDMA_CONTROL_8812); - if(u1btmp & BIT1) - break; - else - delay_ms(10); - } - - // Disable clock - RTL_W8(REG_SYS_CLKR_8812+1, 0xf0); - // Disable 320M - RTL_W8(REG_AFE_PLL_CTRL_8812+3, 0x8); - // Enable 320M - RTL_W8(REG_AFE_PLL_CTRL_8812+3, 0xa); - // Enable clock - RTL_W8( REG_SYS_CLKR_8812+1, 0xfc); - - // Release Tx pause - RTL_W8(REG_TXPAUSE_8812, 0); - - // Enable RX DMA path - u1btmp = RTL_R8(REG_RXDMA_CONTROL_8812); - RTL_W8(REG_RXDMA_CONTROL_8812, u1btmp & (~ BIT2)); - - // Start Usb TxDMA - RTL_W16(PCIE_CTRL_REG, 0x00 ); - RESTORE_INT(flags); -// panic_printk("FBEAM_ERROR <==%s\n", __FUNCTION__); -} - - -#endif - - -VOID RTL8812_MACID_PAUSE( - struct rtl8192cd_priv *priv, - BOOLEAN bSleep, - u4Byte aid -) -{ - if (priv->pshare->rf_ft_var.enable_macid_sleep) { - if (bSleep) { - if (aid > MACID_REGION3_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_3, RTL_R32(REG_MACID_PKT_SLEEP_3) | BIT(aid-MACID_REGION3_LIMIT-1)); - else if(aid > MACID_REGION2_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_2, RTL_R32(REG_MACID_PKT_SLEEP_2) | BIT(aid-MACID_REGION2_LIMIT-1)); - else if(aid > MACID_REGION1_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_1, RTL_R32(REG_MACID_PKT_SLEEP_1) | BIT(aid-MACID_REGION1_LIMIT-1)); - else - RTL_W32(REG_MACID_PKT_SLEEP_0, RTL_R32(REG_MACID_PKT_SLEEP_0) | BIT(aid)); - } else { - if (aid > MACID_REGION3_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_3, RTL_R32(REG_MACID_PKT_SLEEP_3) & ~BIT(aid-MACID_REGION3_LIMIT-1)); - else if(aid > MACID_REGION2_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_2, RTL_R32(REG_MACID_PKT_SLEEP_2) & ~BIT(aid-MACID_REGION2_LIMIT-1)); - else if(aid > MACID_REGION1_LIMIT) - RTL_W32(REG_MACID_PKT_SLEEP_1, RTL_R32(REG_MACID_PKT_SLEEP_1) & ~BIT(aid-MACID_REGION1_LIMIT-1)); - else - RTL_W32(REG_MACID_PKT_SLEEP_0, RTL_R32(REG_MACID_PKT_SLEEP_0) & ~BIT(aid)); - } - } -} - - -#endif //CONFIG_RTL_8812_SUPPORT - - -#if defined(DFS) || defined(RTK_AC_SUPPORT) //for 11ac logo -void SwitchChannel(struct rtl8192cd_priv *priv) -{ - - int ch = priv->pshare->dfsSwitchChannel; - int staidx = 0; -//#ifndef SMP_SYNC - unsigned long flags=0; -//#endif - struct stat_info *pstat = findNextSTA(priv, &staidx); - - priv->pmib->dot11RFEntry.dot11channel = ch; - priv->pshare->dfsSwitchChannel = 0; - RTL_W8(TXPAUSE, 0xff); - - PHY_SetBBReg(priv, 0x924, BIT(15), 0); // disable HW DFS report -#ifdef DFS - if (!priv->pmib->dot11DFSEntry.disable_DFS && - (OPMODE & WIFI_AP_STATE)) { - if (timer_pending(&priv->DFS_timer)) - del_timer_sync(&priv->DFS_timer); - - if (timer_pending(&priv->ch_avail_chk_timer)) - del_timer_sync(&priv->ch_avail_chk_timer); - - if (timer_pending(&priv->dfs_det_chk_timer)) - del_timer_sync(&priv->dfs_det_chk_timer); - } -#endif - - priv->pshare->CurrentChannelBW = priv->pshare->is_40m_bw = priv->pmib->dot11nConfigEntry.dot11nUse40M; - - if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80 && - priv->pmib->dot11RFEntry.band5GSelected == PHY_BAND_5G_3) - { - int channel = priv->pmib->dot11RFEntry.dot11channel; - - if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, channel)) { - priv->pshare->CurrentChannelBW = priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_AC_20; - } - } -#ifdef DFS - if(priv->pshare->rf_ft_var.dfs_next_ch != 0){ - priv->pmib->dot11RFEntry.dot11channel = priv->pshare->rf_ft_var.dfs_next_ch; - } -#endif - panic_printk("4. Swiching channel to %d! BW %dM mode\n", priv->pmib->dot11RFEntry.dot11channel, - (priv->pshare->CurrentChannelBW == 2)? 80 : ((priv->pshare->CurrentChannelBW == 1)? 40 : 20)); - - if ((ch>144) ? ((ch-1)%8) : (ch%8)) { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } else { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; - } - - SAVE_INT_AND_CLI(flags); - SMP_LOCK(flags); - SwBWMode(priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan); - SwChnl(priv, priv->pmib->dot11RFEntry.dot11channel, priv->pshare->offset_2nd_chan); - PHY_IQCalibrate(priv); //FOR_8812_IQK - SMP_UNLOCK(flags); - RESTORE_INT(flags); - - - priv->pmib->dot11DFSEntry.DFS_detected = 0; - priv->ht_cap_len = 0; - update_beacon(priv); - -#ifdef MBSSID - if (priv->pmib->miscEntry.vap_enable) { - int i; - for (i=0; ipvap_priv[i])) { - priv->pvap_priv[i]->pmib->dot11RFEntry.dot11channel = ch; - priv->pvap_priv[i]->ht_cap_len = 0; - update_beacon(priv->pvap_priv[i]); - } - } - } -#endif - - RTL_W8(TXPAUSE, 0x00); - - - while(pstat) - { -#ifdef TX_SHORTCUT - if (!priv->pmib->dot11OperationEntry.disable_txsc) { - int i; - for (i=0; itx_sc_ent[i].hwdesc1.Dword7 &= set_desc(~TX_TxBufSizeMask); - } -#endif - -#if defined(CONFIG_RTL_8812_SUPPORT) ||defined(CONFIG_RTL_8723B_SUPPORT) - if (GET_CHIP_VER(priv) == VERSION_8812E || GET_CHIP_VER(priv) == VERSION_8723B) { - UpdateHalRAMask8812(priv, pstat, 3); - } -#endif -#ifdef CONFIG_WLAN_HAL - if (IS_HAL_CHIP(priv)) { - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pstat, 3); - } -#endif - - pstat = findNextSTA(priv, &staidx); - - } - -#ifdef DFS - if (!priv->pmib->dot11DFSEntry.disable_DFS && - (OPMODE & WIFI_AP_STATE) && - (((priv->pmib->dot11RFEntry.dot11channel >= 52) && - (priv->pmib->dot11RFEntry.dot11channel <= 64)) || - ((priv->pmib->dot11RFEntry.dot11channel >= 100) && - (priv->pmib->dot11RFEntry.dot11channel <= 140)))) { - - init_timer(&priv->ch_avail_chk_timer); - priv->ch_avail_chk_timer.data = (unsigned long) priv; - priv->ch_avail_chk_timer.function = rtl8192cd_ch_avail_chk_timer; - - if ((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_ETSI) && - (IS_METEOROLOGY_CHANNEL(priv->pmib->dot11RFEntry.dot11channel))) - mod_timer(&priv->ch_avail_chk_timer, jiffies + CH_AVAIL_CHK_TO_CE); - else - mod_timer(&priv->ch_avail_chk_timer, jiffies + CH_AVAIL_CHK_TO); - - init_timer(&priv->DFS_timer); - priv->DFS_timer.data = (unsigned long) priv; - priv->DFS_timer.function = rtl8192cd_DFS_timer; - - init_timer(&priv->DFS_TXPAUSE_timer); - priv->DFS_TXPAUSE_timer.data = (unsigned long) priv; - priv->DFS_TXPAUSE_timer.function = rtl8192cd_DFS_TXPAUSE_timer; - - /* DFS activated after 5 sec; prevent switching channel due to DFS false alarm */ - mod_timer(&priv->DFS_timer, jiffies + RTL_SECONDS_TO_JIFFIES(5)); - - init_timer(&priv->dfs_det_chk_timer); - priv->dfs_det_chk_timer.data = (unsigned long) priv; - priv->dfs_det_chk_timer.function = rtl8192cd_dfs_det_chk_timer; - - mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10)); - - DFS_SetReg(priv); - - priv->pmib->dot11DFSEntry.disable_tx = 1; - } - else - priv->pmib->dot11DFSEntry.disable_tx = 0; -#endif -} -#endif - + phydm_UpdateHalRAMask(ODMPTR, WirelessMode, rf_mimo_mode, BW, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap, rssi_level); + pstat->ratr_idx = phydm_rate_id_mapping(ODMPTR, WirelessMode, rf_mimo_mode, BW); + +#else + // assign band mask and rate bitmap + switch (WirelessMode) { + case WIRELESS_MODE_B: { + ratr_index = RATR_INX_WIRELESS_B; + if (ratr_bitmap & 0x0000000c) //11M or 5.5M enable + ratr_bitmap &= 0x0000000d; + else + ratr_bitmap &= 0x0000000f; + } + break; + + case WIRELESS_MODE_G: { + ratr_index = RATR_INX_WIRELESS_GB; + + if (rssi_level == 1) + ratr_bitmap &= 0x00000f00; + else if (rssi_level == 2) + ratr_bitmap &= 0x00000ff0; + else + ratr_bitmap &= 0x00000ff5; + } + break; + + case WIRELESS_MODE_A: { + ratr_index = RATR_INX_WIRELESS_G; + ratr_bitmap &= 0x00000ff0; + } + break; + + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: { + if (WirelessMode == WIRELESS_MODE_N_24G) + ratr_index = RATR_INX_WIRELESS_NGB; + else + ratr_index = RATR_INX_WIRELESS_NG; + + // if(MimoPs <= MIMO_PS_DYNAMIC) + if (MimoPs < MIMO_PS_DYNAMIC) { + if (rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if (rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff005; + } else { + if (rf_mimo_mode == MIMO_1T1R) { + if (bCurTxBW40MHz) { + if (rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if (rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff015; + } else { + if (rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if (rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff005; + } + } else { + if (bCurTxBW40MHz) { + if (rssi_level == 1) + ratr_bitmap &= 0x0fff0000; + else if (rssi_level == 2) + ratr_bitmap &= 0x0ffff000; + else + ratr_bitmap &= 0x0ffff015; + } else { + if (rssi_level == 1) + ratr_bitmap &= 0x0fff0000; + else if (rssi_level == 2) + ratr_bitmap &= 0x0ffff000; + else + ratr_bitmap &= 0x0ffff005; + } + } + } + } + break; +#ifdef RTK_AC_SUPPORT + case WIRELESS_MODE_AC_5G: { + ratr_index = RATR_INX_WIRELESS_AC_N; + + if(pstat->rssi && priv->pshare->rf_ft_var.rssi_ra) + { + if (pstat->rssi >= priv->pshare->rf_ft_var.rssi_thd1) + rssi_level = 1; + else if (pstat->rssi >= priv->pshare->rf_ft_var.rssi_thd2) + rssi_level = 2; + else + rssi_level = 3; + + if(pstat->rssi_level_ac && (pstat->rssi_level_ac==rssi_level)) + return; + + if (rf_mimo_mode == MIMO_1T1R) + { + if(rssi_level == 1) // add by Gary for ac-series + ratr_bitmap &= 0x003f8000; + else if (rssi_level == 2) + ratr_bitmap &= 0x003ff000; + else + ratr_bitmap &= 0x003ff010; + } + else + { + if(rssi_level == 1) // add by Gary for ac-series + ratr_bitmap &= 0xfe3f8000; // VHT 2SS MCS3~9 + else if (rssi_level == 2) + ratr_bitmap &= 0xfffff000; // VHT 2SS MCS0~9 + else + ratr_bitmap &= 0xfffff010; // All + } + + //panic_printk("[%s][%d] rssi_level=[%d->%d] ratr_bitmap=0x%x\n", __FUNCTION__, __LINE__, + //pstat->rssi_level_ac, rssi_level, ratr_bitmap); + + pstat->rssi_level_ac = rssi_level; + + } + else + { + if (rf_mimo_mode == MIMO_1T1R) + ratr_bitmap &= 0x003ff010; + else + ratr_bitmap &= 0xfffff010; + } + + ratr_bitmap &= (VHT_TxMap << 12)|0xff0; + + } + break; +#endif + default: + ratr_index = RATR_INX_WIRELESS_NGB; + + if (rf_mimo_mode == MIMO_1T1R) + ratr_bitmap &= 0x000ff0ff; + else + ratr_bitmap &= 0x0ffff0ff; + break; + } + + bShortGI = Get_RA_ShortGI(priv, pEntry, WirelessMode, BW); + + + + pstat->ratr_idx = MRateIdxToARFRId8812(priv, ratr_index, rf_mimo_mode) ; + pstat->tx_bw_fw = BW; + +#endif + + +#ifdef AC2G_256QAM + + if(is_ac2g(priv) && pstat->vht_cap_len ) + { + printk("AC2G STA Associated !!\n"); + if (rf_mimo_mode == MIMO_1T1R) + { + //bShortGI = 1; + ratr_bitmap = 0x003ff015; + + if(BW == 2) + pstat->ratr_idx = 10; + else + pstat->ratr_idx = 11; + + if(BW == 0) + VHT_TxMap = 0x1ff; + else + VHT_TxMap = 0x3ff; + + } + else if (rf_mimo_mode == MIMO_2T2R) + { + // bShortGI = 0; + ratr_bitmap = 0xffcff015; + + if(BW == 2) + pstat->ratr_idx = 9; + else + pstat->ratr_idx = 12; + + if(BW == 0) + VHT_TxMap = 0x7fdff; + else + VHT_TxMap = 0xfffff; + } + + ratr_bitmap &= ((VHT_TxMap << 12)|0xfff); + + pstat->WirelessMode = WIRELESS_MODE_AC_24G; + } + +#endif + + // for debug, set vht_txmap for RAMask + #if CFG_HAL_RTK_AC_SUPPORT + if (WirelessMode == WIRELESS_MODE_AC_5G) + ratr_bitmap &= (VHT_TxMap << 12)|0xff0; + #endif + + H2CCommand[0] = REMAP_AID(pstat); + H2CCommand[1] = (pstat->ratr_idx) | (bShortGI ? 0x80 : 0x00) ; + H2CCommand[2] = BW | Get_VHT_ENI(IOTAction, WirelessMode, ratr_bitmap); + + + H2CCommand[2] |= BIT6; // DisableTXPowerTraining + + H2CCommand[3] = (u1Byte)(ratr_bitmap & 0x000000ff); + H2CCommand[4] = (u1Byte)((ratr_bitmap & 0x0000ff00) >> 8); + H2CCommand[5] = (u1Byte)((ratr_bitmap & 0x00ff0000) >> 16); + H2CCommand[6] = (u1Byte)((ratr_bitmap & 0xff000000) >> 24); + + FillH2CCmd8812(priv, H2C_8812_RA_MASK, 7, H2CCommand); + + SetBcnCtrlReg_8812(priv, BIT3, 0); + /* + panic_printk("UpdateHalRAMask8812E(): bitmap = %x ratr_index = %1x, MacID:%x, ShortGI:%x, MimoPs=%d\n", + ratr_bitmap, pstat->ratr_idx, (pstat->aid), bShortGI, MimoPs); + + panic_printk("Cmd: %02x, %02x, %02x, %02x, %02x, %02x, %02x \n", + H2CCommand[0] ,H2CCommand[1], H2CCommand[2], + H2CCommand[3] ,H2CCommand[4], H2CCommand[5], H2CCommand[6] ); + */ +} +void +UpdateHalMSRRPT8812( + struct rtl8192cd_priv *priv, + struct stat_info *pstat, + unsigned char opmode +) +{ + u1Byte H2CCommand[3] = { 0}; + + update_remapAid(priv,pstat); + H2CCommand[0] = opmode & 0x01; + H2CCommand[1] = REMAP_AID(pstat) & 0xff; + H2CCommand[2] = 0; + FillH2CCmd8812(priv, H2C_8812_MSRRPT, 3, H2CCommand); + + // panic_printk("UpdateHalMSRRPT8812 Cmd: %02x, %02x, %02x \n", + // H2CCommand[0] ,H2CCommand[1], H2CCommand[2]); +} +#if 0 +void check_txrate_by_reg_8812(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + unsigned char initial_rate = 0x7f; + unsigned char legacyRA = 0 ; + unsigned int autoRate1 = 0; + +// if (!priv->pshare->rf_ft_var.update_rainfo) +// return; + + RTL_W8(0x8d, 0x01); + RTL_W8(0x8f, 0x40); + + if ( should_restrict_Nrate(priv, pstat) && is_fixedMCSTxRate(priv)) + legacyRA = 1; + + if (pstat->sta_in_firmware == 1) { + + +#ifdef WDS + if (pstat->state & WIFI_WDS) { + autoRate1 = (priv->pmib->dot11WdsInfo.entry[pstat->wds_idx].txRate == 0) ? 1 : 0; + } else +#endif + { + autoRate1 = priv->pmib->dot11StationConfigEntry.autoRate; + } + + if (autoRate1 || legacyRA) { + RTL_W8(0x8c, REMAP_AID(pstat) & 0x1f); + initial_rate = RTL_R8(0x2f0); + if ((initial_rate & 0x7f) == 0x7f) + return; + + + if ((initial_rate & 0x3f) < 12) { + pstat->current_tx_rate = dot11_rate_table[initial_rate & 0x3f]; + pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; + } else { + if ((initial_rate & 0x3f) >= 44) + pstat->current_tx_rate = VHT_RATE_ID + ((initial_rate & 0x3f) - 44); + else + pstat->current_tx_rate = HT_RATE_ID + ((initial_rate & 0x3f) - 12); + + if (initial_rate & BIT(7)) + pstat->ht_current_tx_info |= TX_USE_SHORT_GI; + else + pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; + } + + priv->pshare->current_tx_rate = pstat->current_tx_rate; + priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; + } + } +} +#endif + + +void odm_TXPowerTrackingCallback_ThermalMeter_8812E(struct rtl8192cd_priv * priv) +{ + unsigned char ThermalValue = 0, delta, channel, is_decrease, rf_mimo_mode; + unsigned char ThermalValue_AVG_count = 0; + unsigned int ThermalValue_AVG = 0; + int ele_D; + char OFDM_index[2]; + unsigned int i = 0, rf = 2; + + unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur + + rf_mimo_mode = get_rf_mimo_mode(priv); + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + if (priv->pshare->Power_tracking_on_8812 == 0) { + priv->pshare->Power_tracking_on_8812 = 1; + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x03); + return; + } else { + priv->pshare->Power_tracking_on_8812 = 0; + ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E + //printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); + } + + switch (rf_mimo_mode) { + case MIMO_1T1R: + rf = 1; + break; + case MIMO_2T2R: + rf = 2; + break; + default: + panic_printk("%s:%d get_rf_mimo_mode error!\n", __FUNCTION__, __LINE__); + break; + } + #ifdef CONFIG_RTL_8812_SUPPORT + if(GET_CHIP_VER(priv) != VERSION_8723B) { + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[0] = (unsigned char)i; + //printk("PathA 0xc1c[32:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]); + break; + } + } + + //Query OFDM path B default setting + if (rf_mimo_mode == MIMO_2T2R) { + ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[1] = (unsigned char)i; + //printk("PathB 0xe1c[31:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); + break; + } + } + } + } + #endif + /* Initialize */ + if (!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + + } + + /* calculate average thermal meter */ + { + priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; + priv->pshare->ThermalValue_AVG_index_8812++; + if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) + priv->pshare->ThermalValue_AVG_index_8812 = 0; + + for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { + if (priv->pshare->ThermalValue_AVG_8812[i]) { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); + } + } + + if (ThermalValue != priv->pshare->ThermalValue) { + //printk("\n******** START:%s() ********\n", __FUNCTION__); + //printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); + + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + if (1) { //AC2G_256QAM (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[i]); + //printk(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + //printk(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); + } + } + } +#endif + #ifdef CONFIG_RTL_8812_SUPPORT + if(GET_CHIP_VER(priv) != VERSION_8723B) { + PHY_SetBBReg(priv, 0xc1c, 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[0]]); + if (rf_mimo_mode == MIMO_2T2R) + PHY_SetBBReg(priv, 0xe1c, 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[1]]); + } + #endif + + } +/* + printk("PathA >>>>> 0xc1c[31:21] = 0x%x, OFDM_index:%d\n", PHY_QueryBBReg(priv, 0xc1c, 0xffe00000), OFDM_index[0]); + if (rf_mimo_mode == MIMO_2T2R) + printk("PathB >>>>> 0xe1c[31:21] = 0x%x, OFDM_index:%d\n", PHY_QueryBBReg(priv, 0xe1c, 0xffe00000), OFDM_index[1]); + printk("\n******** END:%s() ********\n", __FUNCTION__); +*/ + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + for (i = 0 ; i < rf ; i++) + priv->pshare->OFDM_index[i] = OFDM_index[i]; + } +} + + +void requestTxReport_8812(struct rtl8192cd_priv *priv) +{ + unsigned char h2cresult, counter = 20; + struct stat_info *sta; + unsigned char H2CCommand[2] = {0xff, 0xff}; + + if ( priv->pshare->sta_query_idx == -1) + return; + +#ifdef TXRETRY_CNT + priv->pshare->sta_query_retry_idx = priv->pshare->sta_query_idx; +#endif + + while (is_h2c_buf_occupy(priv)) { + delay_ms(2); + if (--counter == 0) + break; + } + + if (!counter) + return; + + sta = findNextSTA(priv, &priv->pshare->sta_query_idx); + if (sta) + H2CCommand[0] = REMAP_AID(sta); + else { + priv->pshare->sta_query_idx = -1; + return; + } + + sta = findNextSTA(priv, &priv->pshare->sta_query_idx); + if (sta) { + H2CCommand[1] = REMAP_AID(sta); + } else { + priv->pshare->sta_query_idx = -1; + } + + //WDEBUG("\n"); + h2cresult = FillH2CCmd8812(priv, H2C_8812_TX_REPORT, 2 , H2CCommand); + //WDEBUG("h2cresult=%d\n",h2cresult); + + +} + +#ifdef TXRETRY_CNT +void requestTxRetry_8812(struct rtl8192cd_priv *priv) +{ + unsigned char h2cresult, counter = 20; + struct stat_info *sta; + unsigned char H2CCommand[3] = {0xff, 0xff, 0x02}; + + if ( priv->pshare->sta_query_retry_idx == -1) + return; + + while (is_h2c_buf_occupy(priv)) { + delay_ms(2); + if (--counter == 0) + break; + } + + if (!counter) + return; + + sta = findNextSTA(priv, &priv->pshare->sta_query_retry_idx); + if (sta) + H2CCommand[0] = REMAP_AID(sta); + else { + priv->pshare->sta_query_retry_idx = -1; + return; + } + + sta = findNextSTA(priv, &priv->pshare->sta_query_retry_idx); + if (sta) { + H2CCommand[1] = REMAP_AID(sta); + } else { + priv->pshare->sta_query_retry_idx = -1; + } + + //WDEBUG("\n"); + priv->pshare->sta_query_retry_macid[0] = H2CCommand[0]; + priv->pshare->sta_query_retry_macid[1] = H2CCommand[1]; + h2cresult = FillH2CCmd8812(priv, H2C_8812_TX_REPORT, 3 , H2CCommand); + //WDEBUG("h2cresult=%d\n",h2cresult); + +} +#endif + +/*C2H_isr_8812() +AP Req Txrpt +"Start Address:USB:0xFD20PCIe/USB: 0x01A0" +|ID|SEQ |CONTENT |LEN|TRIGGER| +----------------------------------------- +|0 | 1 |2~13 |14 |15 | +----------------------------------------- + +|ID=0x04|SEQ|STA1 MACID(1B)|Tx_ok1(2B)|Tx_fail1(2B)|initial rate1(1B)|STA2 MACID(1B)|Tx_ok2(2B)|Tx_fail2(2B)|Initial rate2(1B)|Len=12(1B)|FF(1B)| +*/ +#if 0 +void C2H_isr_8812(struct rtl8192cd_priv *priv) +{ + struct tx_rpt rpt1; + int j, C2H_ID; + unsigned char MacID = 0xff; + int idx = 0x1a2; +#ifndef SMP_SYNC + unsigned long flags=0; +#endif + + //WDEBUG("\n"); + + SAVE_INT_AND_CLI(flags); + C2H_ID = RTL_R8(0x1a0); + + if ( (C2H_ID) == C2H_8812_TX_REPORT ) { + + for (j = 0; j < 2; j++) { + + MacID = RTL_R8(idx); + if (MacID == 0xff) + continue; + + rpt1.macid = MacID & TXdesc_92E_MacIdMask; + + if (rpt1.macid) { + + rpt1.txok = (RTL_R8(idx + 2)<<8) | RTL_R8(idx + 1); + rpt1.txfail = (RTL_R8(idx + 4)<<8) | RTL_R8(idx + 3); +/* +#ifdef _BIG_ENDIAN_ + rpt1.txok = le16_to_cpu(RTL_R16(idx + 1)); + rpt1.txfail = le16_to_cpu(RTL_R16(idx + 3)); +#else + rpt1.txok = be16_to_cpu(RTL_R16(idx + 1)); + rpt1.txfail = be16_to_cpu(RTL_R16(idx + 3)); +#endif +*/ + rpt1.initil_tx_rate = RTL_R8(idx + 5); + txrpt_handler(priv, &rpt1); // add inital tx rate handle for 8812E + } + idx += 6; + } + } + +// check sounding BW also... + + + + RTL_W8( 0x1af, 0); + if ( (C2H_ID) == C2H_8812_TX_REPORT ) + requestTxReport_8812(priv); + RESTORE_INT(flags); +} +#endif + +VOID +C2HRaReportHandler_8812( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +) +{ + u1Byte Rate = CmdBuf[0] & 0x3F; + u1Byte MacId = CmdBuf[1]; + BOOLEAN bLDPC = CmdBuf[2] & BIT0; + BOOLEAN bTxBF = (CmdBuf[2] & BIT1) >> 1; +#if (BEAMFORMING_SUPPORT == 1) + Beamforming_SetTxBFen(priv, MacId, bTxBF); +#endif +} + +VOID +C2HTxTxReportHandler_8812( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +) +{ + struct tx_rpt rpt1; + int k=0, j=0; + for(j=0; j<2; j++) { + rpt1.macid= CmdBuf[k]; + rpt1.txok = CmdBuf[k+1] | ((short)CmdBuf[k+2]<<8); + rpt1.txfail = CmdBuf[k+3] | ((short)CmdBuf[k+4]<<8); + rpt1.initil_tx_rate = CmdBuf[k+5]; + if(rpt1.macid != 0xff) + txrpt_handler(priv, &rpt1); + k+=6; + } +} + +#if (BEAMFORMING_SUPPORT == 1) +VOID C2HTxBeamformingHandler_8812( struct rtl8192cd_priv *priv, pu1Byte CmdBuf, u1Byte CmdLen); +#endif + +VOID +_C2HContentParsing8812( + struct rtl8192cd_priv *priv, + u1Byte c2hCmdId, + u1Byte c2hCmdLen, + pu1Byte tmpBuf +) +{ + + switch(c2hCmdId) + { + case C2H_8812_TXBF: +#if (BEAMFORMING_SUPPORT == 1) + C2HTxBeamformingHandler_8812(priv, tmpBuf, c2hCmdLen); +#endif + break; + case C2H_8812_TXPERORT: +#ifdef TXREPORT + C2HTxTxReportHandler_8812(priv, tmpBuf, c2hCmdLen); + + #ifdef TXRETRY_CNT + requestTxRetry_8812(priv); + #else + requestTxReport_8812(priv); + #endif + +#endif + break; + +#ifdef TXRETRY_CNT + case C2H_8812_TXRETRY: + C2HTxTxRetryHandler(priv, tmpBuf); + requestTxReport_8812(priv); + break; +#endif + + default: + if(!(phydm_c2H_content_parsing(ODMPTR, c2hCmdId, c2hCmdLen, tmpBuf))) { + printk("[C2H], Unkown packet!! CmdId(%#X)!\n", c2hCmdId); + } + break; + } +} + +VOID +C2HPacketHandler_8812( + struct rtl8192cd_priv *priv, + pu1Byte Buffer, + u1Byte Length + ) +{ + u1Byte c2hCmdId=0, c2hCmdSeq=0, c2hCmdLen=0; + pu1Byte tmpBuf=NULL; + c2hCmdId = Buffer[0]; + c2hCmdSeq = Buffer[1]; +/* +#ifdef CONFIG_WLAN_HAL + if(c2hCmdId==C2H_88XX_EXTEND_IND) + { + c2hCmdLen = Length; + tmpBuf = Buffer; + C2HExtEventHandler88XX(NULL, c2hCmdId, c2hCmdLen, tmpBuf); + } + else +#endif +*/ + { + c2hCmdLen = Length -2; + tmpBuf = Buffer+2; + + _C2HContentParsing8812(priv, c2hCmdId, c2hCmdLen, tmpBuf); + } +} + +#if (BEAMFORMING_SUPPORT == 1) +VOID +SetBeamformRfMode8812( + struct rtl8192cd_priv *priv, + PRT_BEAMFORMING_INFO pBeamformingInfo + ) +{ + u1Byte i; + u4Byte bSelfBeamformer = FALSE; + u4Byte bSelfBeamformee = FALSE; + RT_BEAMFORMING_ENTRY BeamformEntry; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + + BeamformCap = Beamforming_GetBeamCap(priv, pBeamformingInfo); + + if(BeamformCap == pBeamformingInfo->BeamformCap) + return; + else + pBeamformingInfo->BeamformCap = BeamformCap; + if(get_rf_mimo_mode(priv) == MIMO_1T1R) + return; + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000,0x1); // RF Mode table write enable + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000,0x1); // RF Mode table write enable + + bSelfBeamformer = BeamformCap & BEAMFORMER_CAP; + bSelfBeamformee = BeamformCap & BEAMFORMEE_CAP; + + if(bSelfBeamformer) + { + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000,0x3); // Select RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff,0xE26BF); // Enable TXIQGEN in RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff,0xE26BF); // Enable TXIQGEN in RX mode + } + else if (!priv->pmib->dot11RFEntry.tx2path) + { + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff,0xC26BF); // Disable TXIQGEN in RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); // Select RX mode + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff,0x3F7FF); // Set Table data + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff,0xC26BF); // Disable TXIQGEN in RX mode + } + PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000,0x0); // RF Mode table write disable + PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000,0x0); // RF Mode table write disable + + if(bSelfBeamformer) { + PHY_SetBBReg(priv, rTxPath_Jaguar, bMaskByte1, 0x33); +#ifdef RF_MIMO_SWITCH + priv->pshare->rf_phy_bb_backup[1] &= ~ bMaskByte1; + priv->pshare->rf_phy_bb_backup[1] |= 0x3300; +#endif + + } else { + PHY_SetBBReg(priv, rTxPath_Jaguar, bMaskByte1, 0x11); +#ifdef RF_MIMO_SWITCH + priv->pshare->rf_phy_bb_backup[1] &= ~ bMaskByte1; + priv->pshare->rf_phy_bb_backup[1] |= 0x1100; +#endif + } +} +VOID +SetBeamformEnter8812( + struct rtl8192cd_priv *priv, + u1Byte BFerBFeeIdx + ) +{ + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); + RT_BEAMFORMING_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + SetBeamformRfMode8812(priv, pBeamformingInfo); + + if(get_rf_mimo_mode(priv) == MIMO_2T2R) + RTL_W32(0x9B4, 0x01081008); + + if((pBeamformingInfo->BeamformCap & BEAMFORMEE_CAP) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) + { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + if (!IS_TEST_CHIP(priv)) { + if (IS_C_CUT_8812(priv)) + RTL_W16( REG_SND_PTCL_CTRL_8812, 0x2CB); // Disable SIG-B CRC8 check + else + RTL_W16( REG_SND_PTCL_CTRL_8812, 0x0B); + } + else + RTL_W16( REG_SND_PTCL_CTRL_8812, 0x1B); + + // MAC addresss/Partial AID of Beamformer + if(BFerIdx == 0) + { + for(i = 0; i < 6 ; i++) + RTL_W8( (REG_BFMER0_INFO_8812+i), BeamformerEntry.MacAddr[i]); + + //RTL_W16( REG_BFMER0_INFO_8812+6, BeamformerEntry.P_AID); + } + else + { + for(i = 0; i < 6 ; i++) + RTL_W8( (REG_BFMER1_INFO_8812+i), BeamformerEntry.MacAddr[i]); + + //RTL_W16( REG_BFMER1_INFO_8812+6, BeamformerEntry.P_AID); + } + + // CSI report parameters of Beamformer + if((BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) ||(BeamformerEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) ) + CSI_Param = 0x01090109; + else + CSI_Param = 0x03090309; + + RTL_W32( REG_CSI_RPT_PARAM_BW20_8812, CSI_Param); + RTL_W32( REG_CSI_RPT_PARAM_BW40_8812, CSI_Param); + RTL_W32( REG_CSI_RPT_PARAM_BW80_8812, CSI_Param); + + // Timeout value for MAC to leave NDP_RX_standby_state 60 us + // RTL_W8( REG_SND_PTCL_CTRL_8812+3, 0x3C); + RTL_W8( REG_SND_PTCL_CTRL_8812+3, 0x50); // // ndp_rx_standby_timer + } + + if((pBeamformingInfo->BeamformCap & BEAMFORMER_CAP) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) + { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if(OPMODE & WIFI_ADHOC_STATE) + STAid = BeamformeeEntry.AID; + else + STAid = BeamformeeEntry.P_AID; + + // P_AID of Beamformee & enable NDPA transmission + if(BFeeIdx == 0) + { + RTL_W16( REG_TXBF_CTRL_8812, STAid); + RTL_W8( REG_TXBF_CTRL_8812+3, RTL_R8( REG_TXBF_CTRL_8812+3)|BIT6|BIT7|BIT4); + } + else + { + RTL_W16( REG_TXBF_CTRL_8812+2, STAid |BIT14| BIT15|BIT12); + } + + // CSI report parameters of Beamformee + if(BFeeIdx == 0) + { + // Get BIT24 & BIT25 + u1Byte tmp = RTL_R8( REG_BFMEE_SEL_8812+3) & 0x3; + RTL_W8( REG_BFMEE_SEL_8812+3, tmp | 0x60); + RTL_W16( REG_BFMEE_SEL_8812, STAid | BIT9); + } + else + { + // Set BIT25 + RTL_W16( REG_BFMEE_SEL_8812+2, STAid | 0xE200); + } + + // if(pHalData->bIsMPChip == FALSE) + if (IS_TEST_CHIP(priv)) + { + // VHT category value + RTL_W8( REG_SND_PTCL_CTRL_8812+1, ACT_CAT_VHT); + // NDPA subtype + RTL_W8( REG_SND_PTCL_CTRL_8812+2, Type_NDPA >> 4); + } + + Beamforming_Notify(priv); + } +} + + +VOID +SetBeamformLeave8812( + struct rtl8192cd_priv *priv, + u1Byte Idx + ) +{ + PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); + RT_BEAMFORMING_ENTRY BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMER_ENTRY BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + + /* Clear P_AID of Beamformee + * Clear MAC addresss of Beamformer + * Clear Associated Bfmee Sel + */ + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) + { + if(Idx == 0) + { + ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformeeEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); + RTL_W16( REG_TXBF_CTRL_8812, 0); + RTL_W16( REG_BFMEE_SEL_8812, 0); + } + else + { + ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformeeEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); + RTL_R16( (REG_TXBF_CTRL_8812+2) & 0xF000); + RTL_W16( REG_BFMEE_SEL_8812+2, RTL_R16( REG_BFMEE_SEL_8812+2) & 0x60); + } + } + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) + { + if(Idx == 0) + { + ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformerEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); + RTL_W32( REG_BFMER0_INFO_8812, 0); + RTL_W16( REG_BFMER0_INFO_8812+4, 0); + } + else + { + ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, BeamformerEntryCap == NONE, Idx=%d\n", __FUNCTION__, Idx)); + RTL_W32( REG_BFMER1_INFO_8812, 0); + RTL_W16( REG_BFMER1_INFO_8812+4, 0); + } + } + + if(((pBeamformingInfo->BeamformerEntry[0]).BeamformEntryCap == BEAMFORMING_CAP_NONE) + && ((pBeamformingInfo->BeamformerEntry[1]).BeamformEntryCap == BEAMFORMING_CAP_NONE)){ + ODM_RT_TRACE(ODMPTR, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[Beamforming]@%s, All BeamformerEntryCap == NONE, STOP feedback CSI\n", __FUNCTION__, Idx)); + RTL_W8( REG_SND_PTCL_CTRL_8812, 0xC8); + } + +} +VOID +SetBeamformStatus8812( + struct rtl8192cd_priv *priv, + u1Byte Idx + ) +{ + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo); + RT_BEAMFORMING_ENTRY BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + if(OPMODE & WIFI_ADHOC_STATE) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + if(Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8812; + else + { + BeamCtrlReg = REG_TXBF_CTRL_8812+2; + BeamCtrlVal |= BIT12 | BIT14|BIT15; + } + if((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED)&& (priv->pshare->rf_ft_var.applyVmatrix)) + { + if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20_40) + BeamCtrlVal |= (BIT9 | BIT10); + else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + } else { + BeamCtrlVal &= ~(BIT9|BIT10|BIT11); + } + RTL_W16(BeamCtrlReg, BeamCtrlVal); +} +//2REG_C2HEVT_CLEAR +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +VOID Beamforming_NDPARate_8812( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate) +{ + + u2Byte NDPARate = Rate; + + if(NDPARate == 0) + { +// ??? +#if 0 + if(Mode == 1 || Mode == 4) + NDPARate = 0x0c; //MGN_MCS0; + else + NDPARate = 0x2c; //MGN_VHT1SS_MCS0; +#else + if(priv->pshare->rssi_min > 30) // link RSSI > 30% + NDPARate = 8; //MGN_24M + else + NDPARate = 4; //MGN_6M + +#endif + } + + if(NDPARate < 0x0c) + BW = HT_CHANNEL_WIDTH_20; + + RTL_W8(REG_NDPA_OPT_CTRL_8812, (NDPARate<<2) | (BW & 0x03)); + + +} + +VOID +C2HTxBeamformingHandler_8812( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +) +{ + u1Byte status = CmdBuf[0] & BIT0; + Beamforming_End(priv, status); +} + +VOID HW_VAR_HW_REG_TIMER_START_8812(struct rtl8192cd_priv *priv) +{ + RTL_W8(0x15F, 0x0); + RTL_W8(0x15F, 0x5); + +} + +VOID HW_VAR_HW_REG_TIMER_INIT_8812(struct rtl8192cd_priv *priv, int t) +{ + RTL_W8(0x164, 1); + RTL_W16(0x15C, t); + +} + +VOID HW_VAR_HW_REG_TIMER_STOP_8812(struct rtl8192cd_priv *priv) +{ + RTL_W8(0x15F, 0); +} + + +VOID _Beamforming_CLK(struct rtl8192cd_priv *priv) +{ + u2Byte u2btmp; + u1Byte QueueID, Count = 0, u1btmp; +#ifndef SMP_SYNC + unsigned long flags; +#endif + unsigned int loop = 5; + + if(priv->pshare->bScanInProcess==TRUE) + return; + + SAVE_INT_AND_CLI(flags); + + // Stop Usb TxDMA + RTL_W16(PCIE_CTRL_REG, 0xff00 ); + + // Wait TXFF empty + for(Count = 0; Count < loop; Count++) { + u2btmp = RTL_R16(REG_TXPKT_EMPTY_8812); + u2btmp = u2btmp & 0x7ff; + if(u2btmp != 0x7ff) { + delay_ms(10); + continue; + } else { + break; + } + } + + // TX pause + RTL_W8(REG_TXPAUSE_8812, 0xFF); + + // Wait TX State Machine OK + for(Count = 0; Count < 100; Count++) { + if(RTL_R32(REG_SCH_TXCMD_8812) != 0) + continue; + else + break; + } + + // Stop RX DMA path + u1btmp = RTL_R8(REG_RXDMA_CONTROL_8812); + RTL_W8(REG_RXDMA_CONTROL_8812, u1btmp| BIT2); + + for(Count = 0; Count < loop; Count++) { + u1btmp = RTL_R8( REG_RXDMA_CONTROL_8812); + if(u1btmp & BIT1) + break; + else + delay_ms(10); + } + + // Disable clock + RTL_W8(REG_SYS_CLKR_8812+1, 0xf0); + // Disable 320M + RTL_W8(REG_AFE_PLL_CTRL_8812+3, 0x8); + // Enable 320M + RTL_W8(REG_AFE_PLL_CTRL_8812+3, 0xa); + // Enable clock + RTL_W8( REG_SYS_CLKR_8812+1, 0xfc); + + // Release Tx pause + RTL_W8(REG_TXPAUSE_8812, 0); + + // Enable RX DMA path + u1btmp = RTL_R8(REG_RXDMA_CONTROL_8812); + RTL_W8(REG_RXDMA_CONTROL_8812, u1btmp & (~ BIT2)); + + // Start Usb TxDMA + RTL_W16(PCIE_CTRL_REG, 0x00 ); + RESTORE_INT(flags); +// panic_printk("FBEAM_ERROR <==%s\n", __FUNCTION__); +} + + +#endif + + +VOID RTL8812_MACID_PAUSE( + struct rtl8192cd_priv *priv, + BOOLEAN bSleep, + u4Byte aid +) +{ + if (priv->pshare->rf_ft_var.enable_macid_sleep) { + if (bSleep) { + if (aid > MACID_REGION3_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_3, RTL_R32(REG_MACID_PKT_SLEEP_3) | BIT(aid-MACID_REGION3_LIMIT-1)); + else if(aid > MACID_REGION2_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_2, RTL_R32(REG_MACID_PKT_SLEEP_2) | BIT(aid-MACID_REGION2_LIMIT-1)); + else if(aid > MACID_REGION1_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_1, RTL_R32(REG_MACID_PKT_SLEEP_1) | BIT(aid-MACID_REGION1_LIMIT-1)); + else + RTL_W32(REG_MACID_PKT_SLEEP_0, RTL_R32(REG_MACID_PKT_SLEEP_0) | BIT(aid)); + } else { + if (aid > MACID_REGION3_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_3, RTL_R32(REG_MACID_PKT_SLEEP_3) & ~BIT(aid-MACID_REGION3_LIMIT-1)); + else if(aid > MACID_REGION2_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_2, RTL_R32(REG_MACID_PKT_SLEEP_2) & ~BIT(aid-MACID_REGION2_LIMIT-1)); + else if(aid > MACID_REGION1_LIMIT) + RTL_W32(REG_MACID_PKT_SLEEP_1, RTL_R32(REG_MACID_PKT_SLEEP_1) & ~BIT(aid-MACID_REGION1_LIMIT-1)); + else + RTL_W32(REG_MACID_PKT_SLEEP_0, RTL_R32(REG_MACID_PKT_SLEEP_0) & ~BIT(aid)); + } + } +} + + +#endif //CONFIG_RTL_8812_SUPPORT + + +#if defined(DFS) || defined(RTK_AC_SUPPORT) //for 11ac logo +void SwitchChannel(struct rtl8192cd_priv *priv) +{ + + int ch = priv->pshare->dfsSwitchChannel; + int staidx = 0; +//#ifndef SMP_SYNC + unsigned long flags=0; +//#endif + struct stat_info *pstat = findNextSTA(priv, &staidx); + + priv->pmib->dot11RFEntry.dot11channel = ch; + priv->pshare->dfsSwitchChannel = 0; + RTL_W8(TXPAUSE, 0xff); + + PHY_SetBBReg(priv, 0x924, BIT(15), 0); // disable HW DFS report +#ifdef DFS + if (!priv->pmib->dot11DFSEntry.disable_DFS && + (OPMODE & WIFI_AP_STATE)) { + if (timer_pending(&priv->DFS_timer)) + del_timer_sync(&priv->DFS_timer); + + if (timer_pending(&priv->ch_avail_chk_timer)) + del_timer_sync(&priv->ch_avail_chk_timer); + + if (timer_pending(&priv->dfs_det_chk_timer)) + del_timer_sync(&priv->dfs_det_chk_timer); + } +#endif + + priv->pshare->CurrentChannelBW = priv->pshare->is_40m_bw = priv->pmib->dot11nConfigEntry.dot11nUse40M; + + if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80 && + priv->pmib->dot11RFEntry.band5GSelected == PHY_BAND_5G_3) + { + int channel = priv->pmib->dot11RFEntry.dot11channel; + + if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, channel)) { + priv->pshare->CurrentChannelBW = priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_AC_20; + } + } +#ifdef DFS + if(priv->pshare->rf_ft_var.dfs_next_ch != 0){ + priv->pmib->dot11RFEntry.dot11channel = priv->pshare->rf_ft_var.dfs_next_ch; + } +#endif + panic_printk("4. Swiching channel to %d! BW %dM mode\n", priv->pmib->dot11RFEntry.dot11channel, + (priv->pshare->CurrentChannelBW == 2)? 80 : ((priv->pshare->CurrentChannelBW == 1)? 40 : 20)); + + if ((ch>144) ? ((ch-1)%8) : (ch%8)) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } else { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + + SAVE_INT_AND_CLI(flags); + SMP_LOCK(flags); + SwBWMode(priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan); + SwChnl(priv, priv->pmib->dot11RFEntry.dot11channel, priv->pshare->offset_2nd_chan); + PHY_IQCalibrate(priv); //FOR_8812_IQK + SMP_UNLOCK(flags); + RESTORE_INT(flags); + + + priv->pmib->dot11DFSEntry.DFS_detected = 0; + priv->ht_cap_len = 0; + update_beacon(priv); + +#ifdef MBSSID + if (priv->pmib->miscEntry.vap_enable) { + int i; + for (i=0; ipvap_priv[i])) { + priv->pvap_priv[i]->pmib->dot11RFEntry.dot11channel = ch; + priv->pvap_priv[i]->ht_cap_len = 0; + update_beacon(priv->pvap_priv[i]); + } + } + } +#endif + + RTL_W8(TXPAUSE, 0x00); + + + while(pstat) + { +#ifdef TX_SHORTCUT + if (!priv->pmib->dot11OperationEntry.disable_txsc) { + int i; + for (i=0; itx_sc_ent[i].hwdesc1.Dword7 &= set_desc(~TX_TxBufSizeMask); + } +#endif + +#if defined(CONFIG_RTL_8812_SUPPORT) ||defined(CONFIG_RTL_8723B_SUPPORT) + if (GET_CHIP_VER(priv) == VERSION_8812E || GET_CHIP_VER(priv) == VERSION_8723B) { + UpdateHalRAMask8812(priv, pstat, 3); + } +#endif +#ifdef CONFIG_WLAN_HAL + if (IS_HAL_CHIP(priv)) { + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pstat, 3); + } +#endif + + pstat = findNextSTA(priv, &staidx); + + } + +#ifdef DFS + if (!priv->pmib->dot11DFSEntry.disable_DFS && + (OPMODE & WIFI_AP_STATE) && + (((priv->pmib->dot11RFEntry.dot11channel >= 52) && + (priv->pmib->dot11RFEntry.dot11channel <= 64)) || + ((priv->pmib->dot11RFEntry.dot11channel >= 100) && + (priv->pmib->dot11RFEntry.dot11channel <= 140)))) { + + init_timer(&priv->ch_avail_chk_timer); + priv->ch_avail_chk_timer.data = (unsigned long) priv; + priv->ch_avail_chk_timer.function = rtl8192cd_ch_avail_chk_timer; + + if ((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_ETSI) && + (IS_METEOROLOGY_CHANNEL(priv->pmib->dot11RFEntry.dot11channel))) + mod_timer(&priv->ch_avail_chk_timer, jiffies + CH_AVAIL_CHK_TO_CE); + else + mod_timer(&priv->ch_avail_chk_timer, jiffies + CH_AVAIL_CHK_TO); + + init_timer(&priv->DFS_timer); + priv->DFS_timer.data = (unsigned long) priv; + priv->DFS_timer.function = rtl8192cd_DFS_timer; + + init_timer(&priv->DFS_TXPAUSE_timer); + priv->DFS_TXPAUSE_timer.data = (unsigned long) priv; + priv->DFS_TXPAUSE_timer.function = rtl8192cd_DFS_TXPAUSE_timer; + + /* DFS activated after 5 sec; prevent switching channel due to DFS false alarm */ + mod_timer(&priv->DFS_timer, jiffies + RTL_SECONDS_TO_JIFFIES(5)); + + init_timer(&priv->dfs_det_chk_timer); + priv->dfs_det_chk_timer.data = (unsigned long) priv; + priv->dfs_det_chk_timer.function = rtl8192cd_dfs_det_chk_timer; + + mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10)); + + DFS_SetReg(priv); + + priv->pmib->dot11DFSEntry.disable_tx = 1; + } + else + priv->pmib->dot11DFSEntry.disable_tx = 0; +#endif +} +#endif + diff --git a/package/kernel/rtl8192cd/8812_reg.h b/package/kernel/rtl8192cd/8812_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8812_vht_gen.c b/package/kernel/rtl8192cd/8812_vht_gen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/8812_vht_gen.h b/package/kernel/rtl8192cd/8812_vht_gen.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/Beamforming.c b/package/kernel/rtl8192cd/Beamforming.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/Beamforming.h b/package/kernel/rtl8192cd/Beamforming.h old mode 100755 new mode 100644 index 2d2972ca543..01ec56c25b3 --- a/package/kernel/rtl8192cd/Beamforming.h +++ b/package/kernel/rtl8192cd/Beamforming.h @@ -1,223 +1,223 @@ -#if (BEAMFORMING_SUPPORT == 1) - -#define TxBF_Nr(a,b) ((a>b) ? (b) : (a)) - -#define not_snding_rate_interval(pEntry, rate_upper, rate_lower) ((pEntry->pSTA->current_tx_rate >= rate_lower) && (pEntry->pSTA->current_tx_rate <= rate_upper)) - -VOID -Beamforming_SetBeamFormInit( - struct rtl8192cd_priv *priv - ); - -u1Byte -Beamforming_GetHTNDPTxRate( - struct rtl8192cd_priv *priv, - u1Byte CompSteeringNumofBFer -); - -u1Byte -Beamforming_GetVHTNDPTxRate( - struct rtl8192cd_priv *priv, - u1Byte CompSteeringNumofBFer -); - -void -Beamforming_CSIRate( - struct rtl8192cd_priv *priv -); - -VOID -Beamforming_GidPAid( - struct rtl8192cd_priv *priv, - struct stat_info *pstat -); - -enum _BEAMFORMING_CAP - -Beamforming_GetEntryBeamCapByMacId( - struct rtl8192cd_priv *priv, - IN u1Byte MacId -); - -BOOLEAN -Beamforming_InitEntry( - struct rtl8192cd_priv *priv, - struct stat_info *pSTA, - pu1Byte Idx -); - -BOOLEAN -Beamforming_DeInitEntry( - struct rtl8192cd_priv *priv, - pu1Byte RA -); - -VOID -Beamforming_Notify( - struct rtl8192cd_priv *priv -); - -VOID -Beamforming_Enter( - struct rtl8192cd_priv *priv, - struct stat_info *pstat -); - -VOID -Beamforming_TimerCallback( - struct rtl8192cd_priv *priv -); - -VOID -Beamforming_AutoTest( - struct rtl8192cd_priv *priv, - u1Byte Idx, - struct _RT_BEAMFORMING_ENTRY *pBeamformEntry -); - -VOID -Beamforming_End( - struct rtl8192cd_priv *priv, - BOOLEAN Status -); - -VOID -Beamforming_Leave( - struct rtl8192cd_priv *priv, - pu1Byte RA -); -VOID -Beamforming_Release( - struct rtl8192cd_priv *priv -); - -BEAMFORMING_CAP -Beamforming_GetBeamCap( - struct rtl8192cd_priv *priv, - IN PRT_BEAMFORMING_INFO pBeamInfo -); - -VOID -Beamforming_Init( - struct rtl8192cd_priv *priv -); - -VOID -Beamforming_SetTxBFen( - struct rtl8192cd_priv *priv, - u1Byte MacId, - BOOLEAN bTxBF -); - -PRT_BEAMFORMING_ENTRY -Beamforming_GetEntryByMacId( - struct rtl8192cd_priv *priv, - u1Byte MacId, - pu1Byte Idx - ); - -PRT_BEAMFORMING_ENTRY -Beamforming_GetFreeBFeeEntry( - struct rtl8192cd_priv *priv, - pu1Byte Idx, - pu1Byte RA - ); - -PRT_BEAMFORMER_ENTRY -Beamforming_GetFreeBFerEntry( - struct rtl8192cd_priv *priv, - OUT pu1Byte Idx, - pu1Byte RA - ); - -VOID -Beamforming_GetNDPAFrame( - struct rtl8192cd_priv *priv, - pu1Byte pNDPAFrame - ); - - - -#if 1 //eric-8822 -BOOLEAN -SendVHTNDPAPacket( - struct rtl8192cd_priv *priv, - IN pu1Byte RA, - IN u2Byte AID, - u1Byte BW, - u1Byte NDPTxRate - ); -BOOLEAN -SendVHTNDPAPacket_MU( - struct rtl8192cd_priv *priv, - IN pu1Byte RA, - IN u2Byte AID, - u1Byte BW, - u1Byte NDPTxRate, - u1Byte isUni - ); -BOOLEAN -SendReportPollPacket( - struct rtl8192cd_priv *priv, - IN pu1Byte RA, - u1Byte BW, - u1Byte TxRate, - BOOLEAN bFinalPoll - ); - -#endif - -#if (MU_BEAMFORMING_SUPPORT == 1) -u1Byte -beamform_GetFirstMUBFeeEntryIdx( - struct rtl8192cd_priv *priv - ); - -VOID -beamform_MUGrouping( - struct rtl8192cd_priv *priv, - u2Byte bitmap, - u1Byte *pairResult -); - -u1Byte -Beamforming_GetReportPollTxRate( - struct rtl8192cd_priv *priv -); - -#endif - -VOID -beamform_UpdateMinSoundingPeriod( - struct rtl8192cd_priv *priv, - IN u2Byte CurBFeePeriod, - IN BOOLEAN bBFeeLeave - ); - -VOID -beamform_SoundingTimerCallback( - struct rtl8192cd_priv *priv - ); - -VOID -beamform_SoundingTimeout( - struct rtl8192cd_priv *priv - ); - -void issue_action_GROUP_ID(struct rtl8192cd_priv *priv, unsigned char idx); - -VOID -Beamform_SoundingDown( - struct rtl8192cd_priv *priv, - IN BOOLEAN Status - ); - -//eric-6s -PRT_BEAMFORMING_ENTRY -Beamforming_GetBFeeEntryByAddr( - struct rtl8192cd_priv *priv, - IN pu1Byte RA, - OUT pu1Byte Idx - ); -#endif - +#if (BEAMFORMING_SUPPORT == 1) + +#define TxBF_Nr(a,b) ((a>b) ? (b) : (a)) + +#define not_snding_rate_interval(pEntry, rate_upper, rate_lower) ((pEntry->pSTA->current_tx_rate >= rate_lower) && (pEntry->pSTA->current_tx_rate <= rate_upper)) + +VOID +Beamforming_SetBeamFormInit( + struct rtl8192cd_priv *priv + ); + +u1Byte +Beamforming_GetHTNDPTxRate( + struct rtl8192cd_priv *priv, + u1Byte CompSteeringNumofBFer +); + +u1Byte +Beamforming_GetVHTNDPTxRate( + struct rtl8192cd_priv *priv, + u1Byte CompSteeringNumofBFer +); + +void +Beamforming_CSIRate( + struct rtl8192cd_priv *priv +); + +VOID +Beamforming_GidPAid( + struct rtl8192cd_priv *priv, + struct stat_info *pstat +); + +enum _BEAMFORMING_CAP + +Beamforming_GetEntryBeamCapByMacId( + struct rtl8192cd_priv *priv, + IN u1Byte MacId +); + +BOOLEAN +Beamforming_InitEntry( + struct rtl8192cd_priv *priv, + struct stat_info *pSTA, + pu1Byte Idx +); + +BOOLEAN +Beamforming_DeInitEntry( + struct rtl8192cd_priv *priv, + pu1Byte RA +); + +VOID +Beamforming_Notify( + struct rtl8192cd_priv *priv +); + +VOID +Beamforming_Enter( + struct rtl8192cd_priv *priv, + struct stat_info *pstat +); + +VOID +Beamforming_TimerCallback( + struct rtl8192cd_priv *priv +); + +VOID +Beamforming_AutoTest( + struct rtl8192cd_priv *priv, + u1Byte Idx, + struct _RT_BEAMFORMING_ENTRY *pBeamformEntry +); + +VOID +Beamforming_End( + struct rtl8192cd_priv *priv, + BOOLEAN Status +); + +VOID +Beamforming_Leave( + struct rtl8192cd_priv *priv, + pu1Byte RA +); +VOID +Beamforming_Release( + struct rtl8192cd_priv *priv +); + +BEAMFORMING_CAP +Beamforming_GetBeamCap( + struct rtl8192cd_priv *priv, + IN PRT_BEAMFORMING_INFO pBeamInfo +); + +VOID +Beamforming_Init( + struct rtl8192cd_priv *priv +); + +VOID +Beamforming_SetTxBFen( + struct rtl8192cd_priv *priv, + u1Byte MacId, + BOOLEAN bTxBF +); + +PRT_BEAMFORMING_ENTRY +Beamforming_GetEntryByMacId( + struct rtl8192cd_priv *priv, + u1Byte MacId, + pu1Byte Idx + ); + +PRT_BEAMFORMING_ENTRY +Beamforming_GetFreeBFeeEntry( + struct rtl8192cd_priv *priv, + pu1Byte Idx, + pu1Byte RA + ); + +PRT_BEAMFORMER_ENTRY +Beamforming_GetFreeBFerEntry( + struct rtl8192cd_priv *priv, + OUT pu1Byte Idx, + pu1Byte RA + ); + +VOID +Beamforming_GetNDPAFrame( + struct rtl8192cd_priv *priv, + pu1Byte pNDPAFrame + ); + + + +#if 1 //eric-8822 +BOOLEAN +SendVHTNDPAPacket( + struct rtl8192cd_priv *priv, + IN pu1Byte RA, + IN u2Byte AID, + u1Byte BW, + u1Byte NDPTxRate + ); +BOOLEAN +SendVHTNDPAPacket_MU( + struct rtl8192cd_priv *priv, + IN pu1Byte RA, + IN u2Byte AID, + u1Byte BW, + u1Byte NDPTxRate, + u1Byte isUni + ); +BOOLEAN +SendReportPollPacket( + struct rtl8192cd_priv *priv, + IN pu1Byte RA, + u1Byte BW, + u1Byte TxRate, + BOOLEAN bFinalPoll + ); + +#endif + +#if (MU_BEAMFORMING_SUPPORT == 1) +u1Byte +beamform_GetFirstMUBFeeEntryIdx( + struct rtl8192cd_priv *priv + ); + +VOID +beamform_MUGrouping( + struct rtl8192cd_priv *priv, + u2Byte bitmap, + u1Byte *pairResult +); + +u1Byte +Beamforming_GetReportPollTxRate( + struct rtl8192cd_priv *priv +); + +#endif + +VOID +beamform_UpdateMinSoundingPeriod( + struct rtl8192cd_priv *priv, + IN u2Byte CurBFeePeriod, + IN BOOLEAN bBFeeLeave + ); + +VOID +beamform_SoundingTimerCallback( + struct rtl8192cd_priv *priv + ); + +VOID +beamform_SoundingTimeout( + struct rtl8192cd_priv *priv + ); + +void issue_action_GROUP_ID(struct rtl8192cd_priv *priv, unsigned char idx); + +VOID +Beamform_SoundingDown( + struct rtl8192cd_priv *priv, + IN BOOLEAN Status + ); + +//eric-6s +PRT_BEAMFORMING_ENTRY +Beamforming_GetBFeeEntryByAddr( + struct rtl8192cd_priv *priv, + IN pu1Byte RA, + OUT pu1Byte Idx + ); +#endif + diff --git a/package/kernel/rtl8192cd/EdcaTurboCheck.c b/package/kernel/rtl8192cd/EdcaTurboCheck.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/EdcaTurboCheck.h b/package/kernel/rtl8192cd/EdcaTurboCheck.h index c09c4885302..6d472b882f8 100644 --- a/package/kernel/rtl8192cd/EdcaTurboCheck.h +++ b/package/kernel/rtl8192cd/EdcaTurboCheck.h @@ -1,35 +1,35 @@ - - -#ifndef __EDCATURBOCHECK_H__ -#define __EDCATURBOCHECK_H__ - -void EdcaParaInit( - struct rtl8192cd_priv *priv - ); - -#ifdef WIFI_WMM -VOID -IotEdcaSwitch( - struct rtl8192cd_priv *priv, - unsigned char enable - ); -#endif -#if 0 -BOOLEAN -ChooseIotMainSTA( - struct rtl8192cd_priv *priv, - PSTA_INFO_T pstat - ); -#endif -void -Choose_IOT_MainSTA( - struct rtl8192cd_priv *priv - ); - -VOID -IotEngine( - struct rtl8192cd_priv *priv - ); - -#endif - + + +#ifndef __EDCATURBOCHECK_H__ +#define __EDCATURBOCHECK_H__ + +void EdcaParaInit( + struct rtl8192cd_priv *priv + ); + +#ifdef WIFI_WMM +VOID +IotEdcaSwitch( + struct rtl8192cd_priv *priv, + unsigned char enable + ); +#endif +#if 0 +BOOLEAN +ChooseIotMainSTA( + struct rtl8192cd_priv *priv, + PSTA_INFO_T pstat + ); +#endif +void +Choose_IOT_MainSTA( + struct rtl8192cd_priv *priv + ); + +VOID +IotEngine( + struct rtl8192cd_priv *priv + ); + +#endif + diff --git a/package/kernel/rtl8192cd/Hal8188EPwrSeq.c b/package/kernel/rtl8192cd/Hal8188EPwrSeq.c index 9219cd56256..360972da0e5 100644 --- a/package/kernel/rtl8192cd/Hal8188EPwrSeq.c +++ b/package/kernel/rtl8192cd/Hal8188EPwrSeq.c @@ -1,103 +1,103 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8188EPwrSeq.c - -Abstract: - This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-07-07 Roger Create. - ---*/ -#ifdef __ECOS -#include -#endif -#include "8192cd.h" - -#ifdef CONFIG_RTL_88E_SUPPORT - -#include "HalPwrSeqCmd.h" -#include "Hal8188EPwrSeq.h" - - -/* - * drivers should parse below arrays and do the corresponding actions - */ - -/* Power on Array */ -WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_CARDEMU_TO_ACT - RTL8188E_TRANS_END -}; - -/* Radio off Array */ -WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_ACT_TO_CARDEMU - RTL8188E_TRANS_END -}; - -/* Card Disable Array */ -WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_ACT_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_CARDDIS - RTL8188E_TRANS_END -}; - -/* Card Enable Array */ -WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_CARDDIS_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_ACT - RTL8188E_TRANS_END -}; - -/* Suspend Array */ -WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_ACT_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_SUS - RTL8188E_TRANS_END -}; - -/* Resume Array */ -WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_SUS_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_ACT - RTL8188E_TRANS_END -}; - - - -/* HWPDN Array */ -WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - RTL8188E_TRANS_ACT_TO_CARDEMU - RTL8188E_TRANS_CARDEMU_TO_PDN - RTL8188E_TRANS_END -}; - -/* Enter LPS */ -WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - //FW behavior - RTL8188E_TRANS_ACT_TO_LPS - RTL8188E_TRANS_END -}; - -/* Leave LPS */ -WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= -{ - //FW behavior - RTL8188E_TRANS_LPS_TO_ACT - RTL8188E_TRANS_END -}; -#endif - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8188EPwrSeq.c + +Abstract: + This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-07-07 Roger Create. + +--*/ +#ifdef __ECOS +#include +#endif +#include "8192cd.h" + +#ifdef CONFIG_RTL_88E_SUPPORT + +#include "HalPwrSeqCmd.h" +#include "Hal8188EPwrSeq.h" + + +/* + * drivers should parse below arrays and do the corresponding actions + */ + +/* Power on Array */ +WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_CARDEMU_TO_ACT + RTL8188E_TRANS_END +}; + +/* Radio off Array */ +WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_ACT_TO_CARDEMU + RTL8188E_TRANS_END +}; + +/* Card Disable Array */ +WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_ACT_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_CARDDIS + RTL8188E_TRANS_END +}; + +/* Card Enable Array */ +WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_CARDDIS_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_ACT + RTL8188E_TRANS_END +}; + +/* Suspend Array */ +WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_ACT_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_SUS + RTL8188E_TRANS_END +}; + +/* Resume Array */ +WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_SUS_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_ACT + RTL8188E_TRANS_END +}; + + + +/* HWPDN Array */ +WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + RTL8188E_TRANS_ACT_TO_CARDEMU + RTL8188E_TRANS_CARDEMU_TO_PDN + RTL8188E_TRANS_END +}; + +/* Enter LPS */ +WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + //FW behavior + RTL8188E_TRANS_ACT_TO_LPS + RTL8188E_TRANS_END +}; + +/* Leave LPS */ +WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= +{ + //FW behavior + RTL8188E_TRANS_LPS_TO_ACT + RTL8188E_TRANS_END +}; +#endif + diff --git a/package/kernel/rtl8192cd/Hal8188EPwrSeq.h b/package/kernel/rtl8192cd/Hal8188EPwrSeq.h index 8ab70daebdc..c96e984eeac 100644 --- a/package/kernel/rtl8192cd/Hal8188EPwrSeq.h +++ b/package/kernel/rtl8192cd/Hal8188EPwrSeq.h @@ -1,164 +1,164 @@ -#ifdef CONFIG_RTL_88E_SUPPORT -#ifndef REALTEK_POWER_SEQUENCE_8188E -#define REALTEK_POWER_SEQUENCE_8188E - -#include "typedef.h" - -#ifdef BIT -#undef BIT -#endif -#define BIT(x) (1 << (x)) - - -/* - Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END - - PWR SEQ Version: rtl8188E_PwrSeq_V09.h -*/ -#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 -#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 -#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 -#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8188E_TRANS_END_STEPS 1 - - -#define RTL8188E_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \ -/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \ - {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \ - -#define RTL8188E_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - -#define RTL8188E_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ -/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ - {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8188E_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8188E_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step -#define RTL8188E_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8188E_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8188E_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; - -#endif -#endif - +#ifdef CONFIG_RTL_88E_SUPPORT +#ifndef REALTEK_POWER_SEQUENCE_8188E +#define REALTEK_POWER_SEQUENCE_8188E + +#include "typedef.h" + +#ifdef BIT +#undef BIT +#endif +#define BIT(x) (1 << (x)) + + +/* + Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END + + PWR SEQ Version: rtl8188E_PwrSeq_V09.h +*/ +#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 +#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 +#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8188E_TRANS_END_STEPS 1 + + +#define RTL8188E_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \ +/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \ + {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \ + +#define RTL8188E_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + +#define RTL8188E_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8188E_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ +/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8188E_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step +#define RTL8188E_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8188E_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8188E_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; + +#endif +#endif + diff --git a/package/kernel/rtl8192cd/Hal8192CDMOutSrc.c b/package/kernel/rtl8192cd/Hal8192CDMOutSrc.c index 90a948b59e1..ad53611e037 100644 --- a/package/kernel/rtl8192cd/Hal8192CDMOutSrc.c +++ b/package/kernel/rtl8192cd/Hal8192CDMOutSrc.c @@ -1,9631 +1,9631 @@ -//============================================================ -// -// File Name: Hal8192CDMOutSrc.c -// -// Description: -// -// This file is for 92CE/92CU outsource dynamic mechanism for partner. -// -// -//============================================================ - -#ifndef _HAL8192CDM_C_ -#define _HAL8192CDM_C_ - -#ifdef __KERNEL__ -#include -#include -#include -#include -#include -#include -#include -#include -#elif defined(__ECOS) -#include -#include -#include -#include -#endif - -#include "./8192cd_cfg.h" -#include "./8192cd.h" -#include "./8192cd_hw.h" -#include "./8192cd_headers.h" -#include "./8192cd_debug.h" - - - -#ifdef __KERNEL__ -#ifdef __LINUX_2_6__ -#include -#else -#include -#endif -#endif - -#if defined(CONFIG_RTL_819X) && defined(USE_RLX_BSP) -#if defined(CONFIG_OPENWRT_SDK) && !defined(CONFIG_ARCH_CPU_RLX) -#include -#else -#include -#endif //CONFIG_OPENWRT_SDK -#endif - - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 5 -#define APK_AFE_REG_NUM 16 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -//============================================================ -// Global var -//============================================================ - -#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST) -unsigned int OFDMSwingTable[] = { - 0x7f8001fe, // 0, +6.0dB - 0x788001e2, // 1, +5.5dB - 0x71c001c7, // 2, +5.0dB - 0x6b8001ae, // 3, +4.5dB - 0x65400195, // 4, +4.0dB - 0x5fc0017f, // 5, +3.5dB - 0x5a400169, // 6, +3.0dB - 0x55400155, // 7, +2.5dB - 0x50800142, // 8, +2.0dB - 0x4c000130, // 9, +1.5dB - 0x47c0011f, // 10, +1.0dB - 0x43c0010f, // 11, +0.5dB - 0x40000100, // 12, +0dB - 0x3c8000f2, // 13, -0.5dB - 0x390000e4, // 14, -1.0dB - 0x35c000d7, // 15, -1.5dB - 0x32c000cb, // 16, -2.0dB - 0x300000c0, // 17, -2.5dB - 0x2d4000b5, // 18, -3.0dB - 0x2ac000ab, // 19, -3.5dB - 0x288000a2, // 20, -4.0dB - 0x26000098, // 21, -4.5dB - 0x24000090, // 22, -5.0dB - 0x22000088, // 23, -5.5dB - 0x20000080, // 24, -6.0dB - 0x1e400079, // 25, -6.5dB - 0x1c800072, // 26, -7.0dB - 0x1b00006c, // 27. -7.5dB - 0x19800066, // 28, -8.0dB - 0x18000060, // 29, -8.5dB - 0x16c0005b, // 30, -9.0dB - 0x15800056, // 31, -9.5dB - 0x14400051, // 32, -10.0dB - 0x1300004c, // 33, -10.5dB - 0x12000048, // 34, -11.0dB - 0x11000044, // 35, -11.5dB - 0x10000040, // 36, -12.0dB -}; - - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; - -unsigned char TxPwrTrk_CCK_SwingTbl[TxPwrTrk_CCK_SwingTbl_Len][8] = { - /* 0.0dB */ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, - /* 0.5dB */ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, - /* 1.0dB */ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, - /* 1.5dB */ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, - /* 2.0dB */ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, - /* 2.5dB */ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, - /* 3.0dB */ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, - /* 3.5dB */ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, - /* 4.0dB */ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, - /* 4.5dB */ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, - /* 5.0dB */ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, - /* 5.5dB */ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, - /* 6.0dB */ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, - /* 6.5dB */ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, - /* 7.0dB */ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, - /* 7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, - /* 8.0dB */ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, - /* 8.5dB */ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, - /* 9.0dB */ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, - /* 9.5dB */ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, - /* 10.0dB */ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, - /* 10.5dB */ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, - /* 11.0dB */ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} -}; - -unsigned char TxPwrTrk_CCK_SwingTbl_CH14[TxPwrTrk_CCK_SwingTbl_Len][8] = { - /* 0.0dB */ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, - /* 0.5dB */ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, - /* 1.0dB */ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, - /* 1.5dB */ {0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00}, - /* 2.0dB */ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, - /* 2.5dB */ {0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00}, - /* 3.0dB */ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, - /* 3.5dB */ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, - /* 4.0dB */ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, - /* 4.5dB */ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, - /* 5.0dB */ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, - /* 5.5dB */ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, - /* 6.0dB */ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, - /* 6.5dB */ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, - /* 7.0dB */ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, - /* 7.5dB */ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, - /* 8.0dB */ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, - /* 8.5dB */ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, - /* 9.0dB */ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, - /* 9.5dB */ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, - /* 10.0dB */ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, - /* 10.5dB */ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, - /* 11.0dB */ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} -}; - -//#ifndef USE_OUT_SRC - -unsigned char CCKSwingTable_Ch1_Ch13[][8] = { -{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB -{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB -{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB -{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB -{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB -{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB -{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB -{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB -{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB -{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB -{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB -{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB -{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB -{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB -{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB -{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB -{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB -{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB -{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB -{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB -{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB -{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB -{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB -{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB -{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB -{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB -{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB -{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB -{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB -{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB -{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB -{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB -{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB -}; - -unsigned char CCKSwingTable_Ch14 [][8]= { -{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB -{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB -{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB -{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB -{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB -{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB -{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB -{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB -{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB -{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB -{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB -{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB -{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB -{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB -{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB -{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB -{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB -{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB -{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB -{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB -{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB -{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB -{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB -{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB -{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB -{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB -{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB -{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB -{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB -{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB -{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB -{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB -{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB -}; - -#endif - -//#if defined(_OUTSRC_COEXIST) -#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST) -const int OFDM_TABLE_SIZE= sizeof(OFDMSwingTable)/sizeof(int); -const int CCK_TABLE_SIZE= sizeof(CCKSwingTable_Ch1_Ch13) >>3; -#endif - - -#ifdef CONFIG_RTL_92D_SUPPORT - -static unsigned int OFDMSwingTable_92D[] = { - 0x7f8001fe, // 0, +6.0dB - 0x788001e2, // 1, +5.5dB - 0x71c001c7, // 2, +5.0dB - 0x6b8001ae, // 3, +4.5dB - 0x65400195, // 4, +4.0dB - 0x5fc0017f, // 5, +3.5dB - 0x5a400169, // 6, +3.0dB - 0x55400155, // 7, +2.5dB - 0x50800142, // 8, +2.0dB - 0x4c000130, // 9, +1.5dB - 0x47c0011f, // 10, +1.0dB - 0x43c0010f, // 11, +0.5dB - 0x40000100, // 12, +0dB - 0x3c8000f2, // 13, -0.5dB - 0x390000e4, // 14, -1.0dB - 0x35c000d7, // 15, -1.5dB - 0x32c000cb, // 16, -2.0dB - 0x300000c0, // 17, -2.5dB - 0x2d4000b5, // 18, -3.0dB - 0x2ac000ab, // 19, -3.5dB - 0x288000a2, // 20, -4.0dB - 0x26000098, // 21, -4.5dB - 0x24000090, // 22, -5.0dB - 0x22000088, // 23, -5.5dB - 0x20000080, // 24, -6.0dB - 0x1e400079, // 25, -6.5dB - 0x1c800072, // 26, -7.0dB - 0x1b00006c, // 27. -7.5dB - 0x19800066, // 28, -8.0dB - 0x18000060, // 29, -8.5dB - 0x16c0005b, // 30, -9.0dB - 0x15800056, // 31, -9.5dB - 0x14400051, // 32, -10.0dB - 0x1300004c, // 33, -10.5dB - 0x12000048, // 34, -11.0dB - 0x11000044, // 35, -11.5dB - 0x10000040, // 36, -12.0dB - 0x0f00003c,// 37, -12.5dB - 0x0e400039,// 38, -13.0dB - 0x0d800036,// 39, -13.5dB - 0x0cc00033,// 40, -14.0dB - 0x0c000030,// 41, -14.5dB - 0x0b40002d,// 42, -15.0dB -}; -#endif - - -#ifdef HW_ANT_SWITCH -#define RXDVY_A_EN ((HW_DIV_ENABLE && !priv->pshare->rf_ft_var.antSw_select) ? 0x80 : 0) -#define RXDVY_B_EN ((HW_DIV_ENABLE && priv->pshare->rf_ft_var.antSw_select) ? 0x80 : 0) -#endif - - -//3 ============================================================ -//3 DIG related functions -//3 ============================================================ -#if 0 -int getIGIFor1RCCA(int value_IGI) -{ - #define ONERCCA_LOW_TH 0x30 - #define ONERCCA_LOW_DIFF 8 - - if (value_IGI < ONERCCA_LOW_TH) { - if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) - return ONERCCA_LOW_TH; - else - return value_IGI + ONERCCA_LOW_DIFF; - } else { - return value_IGI; - } -} - - -void set_DIG_state(struct rtl8192cd_priv *priv, int state) -{ - int value_IGI; - - if (state) { - priv->pshare->DIG_on = 1; - priv->pshare->restore = 0; - } - else { - priv->pshare->DIG_on = 0; - if (priv->pshare->restore == 0) { - if (priv->pshare->rf_ft_var.use_ext_lna == 1) - value_IGI = 0x30; - else - value_IGI = 0x20; - -#if defined(HW_ANT_SWITCH) - // wirte new initial gain index into regC50/C58 - if (priv->pshare->rf_ft_var.one_path_cca == 0) { - RTL_W8(0xc50, value_IGI | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI | RXDVY_B_EN); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { - RTL_W8(0xc50, value_IGI | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, getIGIFor1RCCA(value_IGI) | RXDVY_B_EN); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { - RTL_W8(0xc50, getIGIFor1RCCA(value_IGI) | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI | RXDVY_B_EN); -#endif - } -#else - // Write IGI into HW - if (priv->pshare->rf_ft_var.one_path_cca == 0) { - RTL_W8(0xc50, value_IGI); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { - RTL_W8(0xc50, value_IGI); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, getIGIFor1RCCA(value_IGI)); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { - RTL_W8(0xc50, getIGIFor1RCCA(value_IGI)); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI); -#endif - } -#endif - priv->pshare->restore = 1; - } -#ifdef INTERFERENCE_CONTROL - priv->pshare->phw->signal_strength = 0; -#endif - } -} -#endif - -#ifdef CONFIG_RTL_92D_SUPPORT -void MP_DIG_process(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - u4Byte RXOK_cal, RxPWDBAve; - //unsigned int FA_cnt_ofdm = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + - // priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4; - //unsigned int FA_cnt_cck = priv->pshare->cck_FA_cnt; - - if (!(priv->drv_state & DRV_STATE_OPEN)) - return; - - if (!(priv->pshare->rf_ft_var.mp_specific && priv->pshare->mp_dig_on)) - return; - - //printk("===> %s, pBandType = %d\n", __FUNCTION__, priv->pmib->dot11RFEntry.phyBandSelect); - - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - - FA_statistic(priv); - - priv->pshare->LastNumQryPhyStatusAll = priv->pshare->NumQryPhyStatus; - priv->pshare->NumQryPhyStatus = priv->pshare->NumQryPhyStatusCCK + priv->pshare->NumQryPhyStatusOFDM; - RXOK_cal = priv->pshare->NumQryPhyStatus - priv->pshare->LastNumQryPhyStatusAll; - - if (RXOK_cal == 0) - RxPWDBAve = 0; - else - RxPWDBAve = priv->pshare->RxPWDBAve/RXOK_cal; - - priv->pshare->RxPWDBAve= 0; - - //printk("RX OK = %d\n", RXOK_cal); - //printk("RSSI = %d\n", RxPWDBAve); - //printk("DIG = (%x, %x), Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", RTL_R8(0xc50), RTL_R8(0xc58), priv->pshare->FA_total_cnt, FA_cnt_ofdm, FA_cnt_cck); - - if (RXOK_cal >= 70) { - if (RxPWDBAve <= 40) { - RTL_W8(0xc50, 0x1C); - RTL_W8(0xc58, 0x1C); - } else if (RxPWDBAve > 45) { - RTL_W8(0xc50, 0x20); - RTL_W8(0xc58, 0x20); - } - } - else { - RTL_W8(0xc50, 0x20); - RTL_W8(0xc58, 0x20); - } - } - mod_timer(&priv->pshare->MP_DIGTimer, RTL_MILISECONDS_TO_JIFFIES(700)); -} -#endif - -void DIG_process(struct rtl8192cd_priv *priv) -{ - #define DEAD_POINT_TH 10000 - #define DOWN_IG_HIT_TH 5 - #define DEAD_POINT_HIT_TH 3 - - unsigned char value_IGI; - signed char value8; - unsigned int IGI_target; - unsigned char Adap_IGI_Upper; -#ifdef INTERFERENCE_CONTROL - unsigned short thd0 = priv->pshare->threshold0; - unsigned short thd1 = priv->pshare->threshold1; - unsigned short thd2 = priv->pshare->threshold2; -#endif - - if (priv->pshare->DIG_on == 1) - { -#ifdef HIGH_POWER_EXT_LNA - if (priv->pshare->rf_ft_var.use_ext_lna == 1) { -// priv->pshare->FA_upper = 0x42; - priv->pshare->FA_upper = MIN_NUM(0x42, priv->pshare->rssi_min+36); - priv->pshare->FA_lower = 0x30; - } else -#endif - { - // Reset initial gain upper & lower bounds -#ifdef DFS - if (!priv->pmib->dot11DFSEntry.disable_DFS && - (OPMODE & WIFI_AP_STATE) && - (((priv->pmib->dot11RFEntry.dot11channel >= 52) && - (priv->pmib->dot11RFEntry.dot11channel <= 64)) || - ((priv->pmib->dot11RFEntry.dot11channel >= 100) && - (priv->pmib->dot11RFEntry.dot11channel <= 140)))){ - priv->pshare->FA_upper = 0x24; - priv->pshare->FA_lower = 0x20; - } - else -#endif - { -#ifdef INTERFERENCE_CONTROL - priv->pshare->FA_lower = 0x20; - - if (priv->pshare->rssi_min != 0xFF) - { -// priv->pshare->FA_upper = 0x3E; - - if (priv->pshare->rssi_min > 30) - priv->pshare->FA_lower = 0x24; - else if (priv->pshare->rssi_min > 25) - priv->pshare->FA_lower = 0x22; - - // limit upper bound to prevent the minimal signal sta from disconnect -// if ((priv->pshare->rssi_min + 10) < priv->pshare->FA_upper) -// priv->pshare->FA_upper = priv->pshare->rssi_min + 10; - priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+20); - } - else // before link - { - priv->pshare->FA_upper = 0x32; - - thd0 = 500; - thd1 = 8000; - thd2 = 10000; - } -#else - if (priv->pmib->dot11RFEntry.tx2path) { - if (priv->pmib->dot11BssType.net_work_type == WIRELESS_11B) - priv->pshare->FA_upper = MIN_NUM(0x2A, priv->pshare->rssi_min+10); - else - priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+10); - } - else - priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+10); - priv->pshare->FA_lower = 0x20; - - if (priv->pshare->rssi_min > 30) - priv->pshare->FA_lower = 0x24; - else if (priv->pshare->rssi_min > 25) - priv->pshare->FA_lower = 0x22; -#endif - } - } - - // determine a new initial gain index according to the sumation of all FA counters as well as upper & lower bounds - value8 = RTL_R8(0xc50); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) { - if(priv->pshare->rf_ft_var.one_path_cca==2) - value8 = RTL_R8(0xc58); - } -#endif - - value_IGI = (value8 & 0x7F); - -#if defined(CONFIG_RTL_NOISE_CONTROL_92C) - if(priv->pshare->rf_ft_var.dnc_enable) - if ((GET_CHIP_VER(priv) == VERSION_8192C)||(GET_CHIP_VER(priv) == VERSION_8188C)){ - unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; -#ifdef HIGH_POWER_EXT_LNA - if(priv->pshare->rf_ft_var.use_ext_lna) { - if( (priv->pshare->rssi_min > 50) ) { - if((!priv->pshare->DNC_on) && (value_IGI >= priv->pshare->FA_upper) && (priv->pshare->FA_total_cnt > priv->pshare->threshold2)) { - priv->pshare->DNC_on = 1; - priv->ext_stats.tp_average_pre = tp_now; - priv->pshare->FA_lower = 0x20; - PHY_SetBBReg(priv, 0x870, bMaskDWord, RTL_R32(0x870)|BIT(5)|BIT(6)|BIT(21)|BIT(22)); - -#ifdef HW_ANT_SWITCH - PHY_SetBBReg(priv, 0xc50, bMaskByte0, priv->pshare->FA_lower | RXDVY_A_EN); - PHY_SetBBReg(priv, 0xc58, bMaskByte0, priv->pshare->FA_lower | RXDVY_B_EN); -#else - PHY_SetBBReg(priv, 0xc50, bMaskByte0, priv->pshare->FA_lower); - PHY_SetBBReg(priv, 0xc58, bMaskByte0, priv->pshare->FA_lower); -#endif - - } else if(priv->pshare->DNC_on ==1) { - if(tp_now < priv->ext_stats.tp_average_pre + 2) { - priv->pshare->DNC_on = 0; - } - else { - priv->pshare->DNC_on =2; - priv->ext_stats.tp_average_pre = tp_now; - } - } else if(priv->pshare->DNC_on >= 2 ) { - if(( tp_now+10 < priv->ext_stats.tp_average_pre ) || (tp_now < 1) ) { - priv->pshare->DNC_on = 0; - } else if(priv->pshare->DNC_on<5) { - priv->ext_stats.tp_average_pre = tp_now; - ++priv->pshare->DNC_on; - } - } - }else { - priv->pshare->DNC_on = 0; - } - - if( priv->pshare->DNC_on ) - return; - else - PHY_SetBBReg(priv, 0x870, bMaskDWord, RTL_R32(0x870)& ~(BIT(5)|BIT(6)|BIT(21)|BIT(22))); - - } else -#endif - { - if( (priv->pshare->rssi_min > 40) && (value_IGI >= priv->pshare->FA_upper) ) { -// unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; - if((!priv->pshare->DNC_on) && (priv->pshare->FA_total_cnt > priv->pshare->threshold2)) { - priv->pshare->DNC_on = 1; - priv->ext_stats.tp_average_pre = tp_now; - } else if(priv->pshare->DNC_on ==1) { - if(tp_now < priv->ext_stats.tp_average_pre + 2) { - priv->pshare->DNC_on = 0; - } - else { - priv->pshare->DNC_on = 2; - priv->ext_stats.tp_average_pre = tp_now; - } - } else if(priv->pshare->DNC_on >= 2 ) { - if((tp_now +10 < priv->ext_stats.tp_average_pre ) - || ((priv->ext_stats.tp_average_pre < 10) && (priv->pshare->FA_total_cnt < priv->pshare->threshold1))) { - priv->pshare->DNC_on = 0; - } else if(priv->pshare->DNC_on<6) { - priv->ext_stats.tp_average_pre = tp_now; - ++priv->pshare->DNC_on; - } - } - if(priv->pshare->DNC_on) { - priv->pshare->FA_upper = 0x3e; - } - }else { - priv->pshare->DNC_on = 0; - } - } - } -#endif - - if ((priv->pshare->digDeadPoint == 0) && (priv->pshare->FA_total_cnt > DEAD_POINT_TH)) { - if ((priv->pshare->digDeadPointHitCount > 0) && (priv->pshare->digDeadPointCandidate == value_IGI)) { - priv->pshare->digDeadPointHitCount++; - if (priv->pshare->digDeadPointHitCount == DEAD_POINT_HIT_TH) { - priv->pshare->digDeadPoint = priv->pshare->digDeadPointCandidate; - } - } else { - priv->pshare->digDeadPointCandidate = value_IGI; - priv->pshare->digDeadPointHitCount = 1; - } - } - -#ifdef INTERFERENCE_CONTROL - if (priv->pshare->FA_total_cnt < thd0) { -#else - if (priv->pshare->FA_total_cnt < priv->pshare->threshold0) { -#endif - priv->pshare->digDownCount++; - if (priv->pshare->digDownCount > DOWN_IG_HIT_TH) { - // Reset deadpoint hit count - if ((priv->pshare->digDeadPoint == 0) && (priv->pshare->digDeadPointHitCount > 0) && (value_IGI == priv->pshare->digDeadPointCandidate)) - priv->pshare->digDeadPointHitCount = 0; - - value_IGI--; - - // Check if the new value is dead point - if ((priv->pshare->digDeadPoint > 0) && (value_IGI == priv->pshare->digDeadPoint)) - value_IGI++; - } -#ifdef INTERFERENCE_CONTROL - } else if (priv->pshare->FA_total_cnt < thd1) { -#else - } else if (priv->pshare->FA_total_cnt < priv->pshare->threshold1) { -#endif - value_IGI += 0; - priv->pshare->digDownCount = 0; -#ifdef INTERFERENCE_CONTROL - } else if (priv->pshare->FA_total_cnt < thd2) { -#else - } else if (priv->pshare->FA_total_cnt < priv->pshare->threshold2) { -#endif - value_IGI++; - priv->pshare->digDownCount = 0; -#ifdef INTERFERENCE_CONTROL - } else if (priv->pshare->FA_total_cnt >= thd2) { -#else - } else if (priv->pshare->FA_total_cnt >= priv->pshare->threshold2) { -#endif - value_IGI += 2; - priv->pshare->digDownCount = 0; - } else { - priv->pshare->digDownCount = 0; - } - - if (value_IGI > priv->pshare->FA_upper) - value_IGI = priv->pshare->FA_upper; - else if (value_IGI < priv->pshare->FA_lower) - value_IGI = priv->pshare->FA_lower; - if (priv->pshare->rf_ft_var.adaptivity_enable && priv->pshare->rf_ft_var.adaptivity_flag == TRUE) - { - Adap_IGI_Upper = priv->pshare->rf_ft_var.Adaptivity_IGI_upper; - if(value_IGI > Adap_IGI_Upper) - value_IGI = Adap_IGI_Upper; - } - -#if defined(HW_ANT_SWITCH) - // wirte new initial gain index into regC50/C58 - if (priv->pshare->rf_ft_var.one_path_cca == 0) { - RTL_W8(0xc50, value_IGI | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI | RXDVY_B_EN); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { - RTL_W8(0xc50, value_IGI | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, getIGIFor1RCCA(value_IGI) | RXDVY_B_EN); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { - RTL_W8(0xc50, getIGIFor1RCCA(value_IGI) | RXDVY_A_EN); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI| RXDVY_B_EN); -#endif - } -#else - // Write IGI into HW - if (priv->pshare->rf_ft_var.one_path_cca == 0) { - RTL_W8(0xc50, value_IGI); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { - RTL_W8(0xc50, value_IGI); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, getIGIFor1RCCA(value_IGI)); -#endif - } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { - RTL_W8(0xc50, getIGIFor1RCCA(value_IGI)); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, value_IGI); -#endif - } -#endif - - } -} - -#if 0 -void check_DIG_by_rssi(struct rtl8192cd_priv *priv, unsigned char rssi_strength) -{ - unsigned int dig_on = 0; - - if (OPMODE & WIFI_SITE_MONITOR) - return; - - if ((rssi_strength > priv->pshare->rf_ft_var.digGoUpperLevel) - && (rssi_strength < HP_LOWER+1) && (priv->pshare->phw->signal_strength != 2)) { -#ifndef CONFIG_RTL_92D_SUPPORT - if (priv->pshare->is_40m_bw) - // RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D - RTL_W8(0xc87, 0x30); - else - RTL_W8(0xc30, 0x44); -#endif - - if (priv->pshare->phw->signal_strength != 3) - dig_on++; - - priv->pshare->phw->signal_strength = 2; - } - else if ((rssi_strength > HP_LOWER+5) && (priv->pshare->phw->signal_strength != 3)) { -#ifndef CONFIG_RTL_92D_SUPPORT - if (priv->pshare->is_40m_bw) - // RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D - RTL_W8(0xc87, 0x30); - else - RTL_W8(0xc30, 0x44); -#endif - - if (priv->pshare->phw->signal_strength != 2) - dig_on++; - - priv->pshare->phw->signal_strength = 3; - } - else if (((rssi_strength < priv->pshare->rf_ft_var.digGoLowerLevel) - && (priv->pshare->phw->signal_strength != 1)) || !priv->pshare->phw->signal_strength) { - // DIG off -// set_DIG_state(priv, 0); - -#ifndef CONFIG_RTL_92D_SUPPORT - if (priv->pshare->is_40m_bw) - //RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D - RTL_W8(0xc87, 0x30); - else - RTL_W8(0xc30, 0x44); -#endif - - priv->pshare->phw->signal_strength = 1; - } - - if (dig_on) { - // DIG on - set_DIG_state(priv, 1); - } - - //check_DC_TH_by_rssi(priv, rssi_strength); -} - - -void DIG_for_site_survey(struct rtl8192cd_priv *priv, int do_ss) -{ - if (do_ss) { - // DIG off - set_DIG_state(priv, 0); - } - else { - // DIG on -#ifndef INTERFERENCE_CONTROL - if (priv->pshare->phw->signal_strength > 1) -#endif - { - set_DIG_state(priv, 1); - } - } -} -#endif - -#if 0 -//#ifdef INTERFERENCE_CONTROL -void check_NBI_by_rssi(struct rtl8192cd_priv *priv, unsigned char rssi_strength) -{ - if (OPMODE & WIFI_SITE_MONITOR) - return; - - if (priv->pshare->phw->nbi_filter_on) { - if (rssi_strength < 20) { - priv->pshare->phw->nbi_filter_on = 0; - RTL_W16(rOFDM0_RxDSP, RTL_R16(rOFDM0_RxDSP) & ~ BIT(9)); // NBI off - } - } else { // NBI OFF previous - if (rssi_strength > 25) { - priv->pshare->phw->nbi_filter_on = 1; - RTL_W16(rOFDM0_RxDSP, RTL_R16(rOFDM0_RxDSP) | BIT(9)); // NBI on - } - } -} -#endif - -/* - * dynamic CCK CCA enhance by rssi - */ -void CCK_CCA_dynamic_enhance(struct rtl8192cd_priv *priv, unsigned char rssi_strength) -{ -#if 1 - unsigned int cck_fa = priv->pshare->FA_total_cnt; - int rssi_thd = 30; - - if (rssi_strength == 0xff) { - if (cck_fa < 1000) { - if (priv->pshare->phw->CCK_CCA_enhanced != 2) { - RTL_W8(0xa0a, 0x40); - priv->pshare->phw->CCK_CCA_enhanced = 2; - } - } else { - if (priv->pshare->phw->CCK_CCA_enhanced != 1) { - RTL_W8(0xa0a, 0x83); - priv->pshare->phw->CCK_CCA_enhanced = 1; - } - } - return; - } - - if (rssi_strength > rssi_thd+5) { - if (priv->pshare->phw->CCK_CCA_enhanced != 0) { - RTL_W8(0xa0a, 0xcd); - priv->pshare->phw->CCK_CCA_enhanced = 0; - } - } else if (rssi_strength< rssi_thd) { - if ((rssi_strength > 9) || (priv->assoc_num >1)) { - if (priv->pshare->phw->CCK_CCA_enhanced != 1) { - RTL_W8(0xa0a, 0x83); - priv->pshare->phw->CCK_CCA_enhanced = 1; - } - } else { - if(cck_fa<1000) { - if (priv->pshare->phw->CCK_CCA_enhanced != 2) { - RTL_W8(0xa0a, 0x40); - priv->pshare->phw->CCK_CCA_enhanced = 2; - } - } else { - if (priv->pshare->phw->CCK_CCA_enhanced != 1) { - RTL_W8(0xa0a, 0x83); - priv->pshare->phw->CCK_CCA_enhanced = 1; - } - } - } - } - -#else - - if (rssi_strength == 0xff) - return; - - if (!priv->pshare->phw->CCK_CCA_enhanced && (rssi_strength < 30)) { - priv->pshare->phw->CCK_CCA_enhanced = TRUE; - RTL_W8(0xa0a, 0x83); - } - else if (priv->pshare->phw->CCK_CCA_enhanced && (rssi_strength > 35)) { - priv->pshare->phw->CCK_CCA_enhanced = FALSE; - RTL_W8(0xa0a, 0xcd); - } -#endif -} - - -//3 ============================================================ -//3 Dynamic Tx Power / Power Tracking -//3 ============================================================ - -#ifdef HIGH_POWER_EXT_PA -void tx_power_control(struct rtl8192cd_priv *priv) -{ -#ifndef SMP_SYNC - unsigned long x; -#endif - - int pwr_value = 0x10101010; - if( priv->pshare->phw->signal_strength == 3 && priv->pshare->phw->lower_tx_power== 0) { - SAVE_INT_AND_CLI(x); - priv->pshare->phw->power_backup[0x00] = RTL_R32(rTxAGC_A_Rate18_06); - priv->pshare->phw->power_backup[0x01] = RTL_R32(rTxAGC_A_Rate54_24); - priv->pshare->phw->power_backup[0x02] = RTL_R32(rTxAGC_B_Rate18_06); - priv->pshare->phw->power_backup[0x03] = RTL_R32(rTxAGC_B_Rate54_24); - priv->pshare->phw->power_backup[0x04] = RTL_R32(rTxAGC_A_Mcs03_Mcs00); - priv->pshare->phw->power_backup[0x05] = RTL_R32(rTxAGC_A_Mcs07_Mcs04); - priv->pshare->phw->power_backup[0x06] = RTL_R32(rTxAGC_A_Mcs11_Mcs08); - priv->pshare->phw->power_backup[0x07] = RTL_R32(rTxAGC_A_Mcs15_Mcs12); - priv->pshare->phw->power_backup[0x08] = RTL_R32(rTxAGC_B_Mcs03_Mcs00); - priv->pshare->phw->power_backup[0x09] = RTL_R32(rTxAGC_B_Mcs07_Mcs04); - priv->pshare->phw->power_backup[0x0a] = RTL_R32(rTxAGC_B_Mcs11_Mcs08); - priv->pshare->phw->power_backup[0x0b] = RTL_R32(rTxAGC_B_Mcs15_Mcs12); - priv->pshare->phw->power_backup[0x0c] = RTL_R32(rTxAGC_A_CCK11_2_B_CCK11); - priv->pshare->phw->power_backup[0x0d] = RTL_R32(rTxAGC_A_CCK1_Mcs32); - priv->pshare->phw->power_backup[0x0e] = RTL_R32(rTxAGC_B_CCK5_1_Mcs32); - RTL_W32(rTxAGC_A_Rate18_06, pwr_value); - RTL_W32(rTxAGC_A_Rate54_24, pwr_value); - RTL_W32(rTxAGC_B_Rate18_06, pwr_value); - RTL_W32(rTxAGC_B_Rate54_24, pwr_value); - RTL_W32(rTxAGC_A_Mcs03_Mcs00, pwr_value); - RTL_W32(rTxAGC_A_Mcs07_Mcs04, pwr_value); - RTL_W32(rTxAGC_A_Mcs11_Mcs08, pwr_value); - RTL_W32(rTxAGC_A_Mcs15_Mcs12, pwr_value); - RTL_W32(rTxAGC_B_Mcs03_Mcs00, pwr_value); - RTL_W32(rTxAGC_B_Mcs07_Mcs04, pwr_value); - RTL_W32(rTxAGC_B_Mcs11_Mcs08, pwr_value); - RTL_W32(rTxAGC_B_Mcs15_Mcs12, pwr_value); - RTL_W32(rTxAGC_A_CCK11_2_B_CCK11, pwr_value); - RTL_W32(rTxAGC_A_CCK1_Mcs32, (pwr_value & 0x0000ff00) | (priv->pshare->phw->power_backup[0x0d] &0xffff00ff)); - RTL_W32(rTxAGC_B_CCK5_1_Mcs32, (pwr_value & 0xffffff00) | (priv->pshare->phw->power_backup[0x0e] &0x000000ff)); - priv->pshare->phw->lower_tx_power = 1; - RESTORE_INT(x); - } - else if( priv->pshare->phw->signal_strength != 3 && priv->pshare->phw->lower_tx_power) { - SAVE_INT_AND_CLI(x); - RTL_W32(rTxAGC_A_Rate18_06, priv->pshare->phw->power_backup[0x00]); - RTL_W32(rTxAGC_A_Rate54_24, priv->pshare->phw->power_backup[0x01]); - RTL_W32(rTxAGC_B_Rate18_06, priv->pshare->phw->power_backup[0x02]); - RTL_W32(rTxAGC_B_Rate54_24, priv->pshare->phw->power_backup[0x03]); - RTL_W32(rTxAGC_A_Mcs03_Mcs00, priv->pshare->phw->power_backup[0x04]); - RTL_W32(rTxAGC_A_Mcs07_Mcs04, priv->pshare->phw->power_backup[0x05]); - RTL_W32(rTxAGC_A_Mcs11_Mcs08, priv->pshare->phw->power_backup[0x06]); - RTL_W32(rTxAGC_A_Mcs15_Mcs12, priv->pshare->phw->power_backup[0x07]); - RTL_W32(rTxAGC_B_Mcs03_Mcs00, priv->pshare->phw->power_backup[0x08]); - RTL_W32(rTxAGC_B_Mcs07_Mcs04, priv->pshare->phw->power_backup[0x09]); - RTL_W32(rTxAGC_B_Mcs11_Mcs08, priv->pshare->phw->power_backup[0x0a]); - RTL_W32(rTxAGC_B_Mcs15_Mcs12, priv->pshare->phw->power_backup[0x0b]); - RTL_W32(rTxAGC_A_CCK11_2_B_CCK11, priv->pshare->phw->power_backup[0x0c]); - RTL_W32(rTxAGC_A_CCK1_Mcs32, priv->pshare->phw->power_backup[0x0d]); - RTL_W32(rTxAGC_B_CCK5_1_Mcs32, priv->pshare->phw->power_backup[0x0e]); - priv->pshare->phw->lower_tx_power = 0; - RESTORE_INT(x); - } -} -#endif - -#if 0 -int get_CCK_swing_index(struct rtl8192cd_priv *priv) -{ - int TempCCk, index=12, i; - short channel; -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) - channel=priv->pshare->working_channel; - else -#endif - channel = (priv->pmib->dot11RFEntry.dot11channel); - - //Query CCK default setting From 0xa24 - TempCCk = PHY_QueryBBReg(priv, rCCK0_TxFilter2, bMaskDWord)&bMaskCCK; - TempCCk = cpu_to_le32(TempCCk); - for(i=0 ; ipshare->rf_ft_var.mp_specific) - channel=priv->pshare->working_channel; - else -#endif - channel = (priv->pmib->dot11RFEntry.dot11channel); - - -#ifdef CONFIG_RTL_88E_SUPPORT //for 88e tx power tracking - if(GET_CHIP_VER(priv) == VERSION_8188E){ - if(channel !=14) { - RTL_W8( 0xa22, 0x1c); - RTL_W8( 0xa23, 0x1a); - RTL_W8( 0xa24, 0x18); - RTL_W8( 0xa25, 0x12); - RTL_W8( 0xa26, 0xe); - RTL_W8( 0xa27, 0x8); - RTL_W8( 0xa28, 0x4); - RTL_W8( 0xa29, 0x2); - } - else{ - RTL_W8( 0xa22, 0x1c); - RTL_W8( 0xa23, 0x1a); - RTL_W8( 0xa24, 0x18); - RTL_W8( 0xa25, 0x12); - RTL_W8( 0xa26, 0x0); - RTL_W8( 0xa27, 0x0); - RTL_W8( 0xa28, 0x0); - RTL_W8( 0xa29, 0x0); - } - } - else -#endif - if(channel !=14) { - RTL_W8( 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]); - RTL_W8( 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]); - RTL_W8( 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]); - RTL_W8( 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]); - RTL_W8( 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]); - RTL_W8( 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]); - RTL_W8( 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]); - RTL_W8( 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]); - } - else{ - RTL_W8( 0xa22, CCKSwingTable_Ch14[CCK_index][0]); - RTL_W8( 0xa23, CCKSwingTable_Ch14[CCK_index][1]); - RTL_W8( 0xa24, CCKSwingTable_Ch14[CCK_index][2]); - RTL_W8( 0xa25, CCKSwingTable_Ch14[CCK_index][3]); - RTL_W8( 0xa26, CCKSwingTable_Ch14[CCK_index][4]); - RTL_W8( 0xa27, CCKSwingTable_Ch14[CCK_index][5]); - RTL_W8( 0xa28, CCKSwingTable_Ch14[CCK_index][6]); - RTL_W8( 0xa29, CCKSwingTable_Ch14[CCK_index][7]); - } -} -#endif - -unsigned char getThermalValue(struct rtl8192cd_priv *priv) -{ - unsigned char ThermalValue; - int sum=0, i=0; - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 0x60); - while ((PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 1) > 0x1f) && ((i++) < 1000)) {//<20ms, test is in 20 us - delay_us(20); - } - ThermalValue =(unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 1) & 0x01f; - priv->pshare->Thermal_idx = (priv->pshare->Thermal_idx+1)%8; - priv->pshare->Thermal_log[ priv->pshare->Thermal_idx ] = ThermalValue; - for(i=0; i<8; i++) { - if(!priv->pshare->Thermal_log[i]) - return ThermalValue; - sum += priv->pshare->Thermal_log[i]; - } - return (sum+4)>>3; -} - - -#ifdef CONFIG_RTL_92C_SUPPORT - -#ifdef HIGH_POWER_EXT_PA -void swingIndexRemap2(int *a, int b, int i) -{ - - u8 index_mapping_HighPower_92C[4][15] = { - {0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 18, 18, 18}, //2.4G, path A/MAC 0, decrease power - {0, 2, 4, 5, 7, 8, 10, 11, 13, 14, 16, 17, 19, 20, 22}, //2.4G, path A/MAC 0, increase power - {0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 18, 18, 18}, //2.4G, path A/MAC 0, decrease power - {0, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23}, //2.4G, path A/MAC 0, increase power - }; - - int d = RTL_ABS(*a, b); - int offset = 0; - - - if(i == 0) - offset = 1; - else - offset = 3; - - if(*a < b ) - { - //printk("\n\n Increase Power !! \n\n"); - *a = b - index_mapping_HighPower_92C[offset][d]; - } - else - { - //printk("\n\n Decrease Power !! \n\n"); - offset = offset - 1; - *a = b + index_mapping_HighPower_92C[offset][d]; - } - - //printk("\n\ a = %d, b = %d, offset = %d, d = %d, diff = %d \n\n", - //*a, b, offset, d, index_mapping_HighPower_92C[offset][d]); - -} -void swingIndexRemap(int *a, int b) -{ - int d = (RTL_ABS(*a, b) *3)>>1; - if(*a < b ) - *a = b - d; - else - *a = b + d; -} -#endif - -void tx_power_tracking(struct rtl8192cd_priv *priv) -{ - unsigned char ThermalValue = 0, delta, delta_LCK, delta_IQK; - int ele_A, ele_D, value32, X, Y, ele_C; - int OFDM_index[2]={0,0}, CCK_index; - int i = 0; - char is2T = ((GET_CHIP_VER(priv) == VERSION_8192C) ?1 :0); - unsigned char TxPwrLevel[2]; - unsigned char channel, OFDM_min_index = 6, rf=1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur -#ifdef POWER_PERCENT_ADJUSTMENT - signed char pwrdiff_percent; -#endif -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel=priv->pshare->working_channel; - if(priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ThermalValue = getThermalValue(priv); - - rf += is2T; - if(ThermalValue) { - - if(!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_LCK = ThermalValue; - priv->pshare->ThermalValue_IQK = ThermalValue; - - //Query OFDM path A default setting - ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for(i=0; ipshare->OFDM_index[0] = i; - priv->pshare->OFDM_index0[0] = i; - break; - } - } - - //Query OFDM path B default setting - if(is2T) { - ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for(i=0; ipshare->OFDM_index[1] = i; - priv->pshare->OFDM_index0[1] = i; - break; - } - } - } - priv->pshare->CCK_index = get_CCK_swing_index(priv); - priv->pshare->CCK_index0 = priv->pshare->CCK_index; - - } - - delta = RTL_ABS(ThermalValue, priv->pshare->ThermalValue); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); - -// printk("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", -// ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK); - - if(delta_LCK > 1) { - priv->pshare->ThermalValue_LCK = ThermalValue; -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) - printk("NOT do LCK during ctx !!!! \n"); - else - PHY_LCCalibrate(priv); - } - else -#endif - PHY_LCCalibrate(priv); - } - - if(delta > 0) { - if(ThermalValue > priv->pshare->ThermalValue) { - for(i = 0; i < rf; i++) - priv->pshare->OFDM_index[i] -= delta; - priv->pshare->CCK_index -= delta; - } else { - for(i = 0; i < rf; i++) - priv->pshare->OFDM_index[i] += delta; - priv->pshare->CCK_index += delta; - } - if(ThermalValue > priv->pmib->dot11RFEntry.ther) { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i]+1; - CCK_index = priv->pshare->CCK_index+1; - } else { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i]; - CCK_index = priv->pshare->CCK_index; - } -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - TxPwrLevel[0] = priv->pshare->mp_txpwr_patha; - TxPwrLevel[1] = priv->pshare->mp_txpwr_pathb; - } else -#endif - { - TxPwrLevel[0] = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[channel-1]; - TxPwrLevel[1] = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[channel-1]; - - if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { - unsigned char offset = (priv->pmib->dot11RFEntry.pwrdiffHT20[channel-1] & 0x0f); - TxPwrLevel[0] = COUNT_SIGN_OFFSET(TxPwrLevel[0], offset); - offset = ((priv->pmib->dot11RFEntry.pwrdiffOFDM[channel-1] & 0xf0) >> 4); - TxPwrLevel[1] = COUNT_SIGN_OFFSET(TxPwrLevel[1], offset); - } -#ifdef POWER_PERCENT_ADJUSTMENT - pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); - TxPwrLevel[0] = POWER_RANGE_CHECK(TxPwrLevel[0]+pwrdiff_percent); - TxPwrLevel[1] = POWER_RANGE_CHECK(TxPwrLevel[1]+pwrdiff_percent); -#endif - } - -// printk("TxPwrLevel[0]=%d, TxPwrLevel[1]=%d\n", TxPwrLevel[0], TxPwrLevel[1]); - for(i = 0; i < rf; i++) { - if(/*TxPwrLevel[i] >=0 &&*/ TxPwrLevel[i] <=26) { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) { - if (delta < 5) - OFDM_index[i] -= 1; - else - OFDM_index[i] -= 2; - } else if(delta > 5 && ThermalValue < priv->pmib->dot11RFEntry.ther) { - OFDM_index[i] += 1; - } - } else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > priv->pmib->dot11RFEntry.ther) { - if (delta < 5) - OFDM_index[i] -= 1; - else - OFDM_index[i] -= 2; - } else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > priv->pmib->dot11RFEntry.ther && delta > 5) { - OFDM_index[i] -= 1; - } - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) - { - int d = 0; - - OFDM_index[i] = priv->pshare->OFDM_index[i]; - d = RTL_ABS(OFDM_index[i], priv->pshare->OFDM_index0[i]); - - if(OFDM_index[i] < priv->pshare->OFDM_index0[i]) - { - OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, d, 0, 0); - } - else - { - OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, d, 1, 0); - } - - } - else -#endif - { -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) { - OFDM_index[i] = priv->pshare->OFDM_index[i]; - swingIndexRemap2(&OFDM_index[i], priv->pshare->OFDM_index0[i], i); //Modify HP tracking table, from Arthur 2012.02.13 - //swingIndexRemap(&OFDM_index[i], priv->pshare->OFDM_index0[i]); - } -#endif - } - if(OFDM_index[i] > OFDM_TABLE_SIZE-1) - OFDM_index[i] = OFDM_TABLE_SIZE-1; - else if (OFDM_index[i] < OFDM_min_index) - OFDM_index[i] = OFDM_min_index; - } - i=0; - { - if(/*TxPwrLevel[i] >=0 &&*/ TxPwrLevel[i] <=26) { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) { - if (delta < 5) - CCK_index -= 1; - else - CCK_index -= 2; - } else if(delta > 5 && ThermalValue < priv->pmib->dot11RFEntry.ther) { - CCK_index += 1; - } - } else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > priv->pmib->dot11RFEntry.ther) { - if (delta < 5) - CCK_index -= 1; - else - CCK_index -= 2; - } else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > priv->pmib->dot11RFEntry.ther && delta > 5) { - CCK_index -= 1; - } - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) - { - int d = 0; - - CCK_index = priv->pshare->CCK_index; - d = RTL_ABS(CCK_index, priv->pshare->CCK_index0); - - if(CCK_index < priv->pshare->CCK_index0) - { - CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, d, 0, 1); - } - else - { - CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, d, 1, 1); - } - - } - else -#endif - { -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) { - CCK_index = priv->pshare->CCK_index; - swingIndexRemap2( &CCK_index, priv->pshare->CCK_index0, i); //Modify HP tracking table, from Arthur 2012.02.13 - //swingIndexRemap( &CCK_index, priv->pshare->CCK_index0); - } -#endif - } - if(CCK_index > CCK_TABLE_SIZE-1) - CCK_index = CCK_TABLE_SIZE-1; - else if (CCK_index < 0) - CCK_index = 0; - } - - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable[(unsigned int)OFDM_index[0]] & 0xFFC00000)>>22; - X = priv->pshare->RegE94; - Y = priv->pshare->RegE9C; - - if(X != 0) { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); - - } else { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned int)OFDM_index[0]]); - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); - } - - - set_CCK_swing_index(priv, CCK_index); - - - if(is2T) { - ele_D = (OFDMSwingTable[(unsigned int)OFDM_index[1]] & 0xFFC00000)>>22; - X = priv->pshare->RegEB4; - Y = priv->pshare->RegEBC; - - if(X != 0) { - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); - - } else { - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned int)OFDM_index[1]]); - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); - } - } - } - - if(delta_IQK > 3) { - priv->pshare->ThermalValue_IQK = ThermalValue; -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) - printk("NOT do IQK during ctx !!!! \n"); - else - PHY_IQCalibrate(priv); - } - else -#endif - PHY_IQCalibrate(priv); - } - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - - } -} -#endif - - -#ifdef RX_GAIN_TRACK_92D -static void rx_gain_tracking_92D(struct rtl8192cd_priv *priv) -{ - u8 index_mapping[Rx_index_mapping_NUM] = { - 0x0f, 0x0f, 0x0f, 0x0f, 0x0b, - 0x0a, 0x09, 0x08, 0x07, 0x06, - 0x05, 0x04, 0x04, 0x03, 0x02 - }; - - u8 eRFPath, curMaxRFPath; - u32 u4tmp; - - u4tmp = (index_mapping[(priv->pmib->dot11RFEntry.ther - priv->pshare->ThermalValue_RxGain)]) << 12; - - DEBUG_INFO("===>%s interface %d Rx Gain %x\n", __FUNCTION__, priv->pshare->wlandev_idx, u4tmp); - - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else - curMaxRFPath = RF92CD_PATH_MAX; - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) - PHY_SetRFReg(priv, eRFPath, 0x3C, bMask20Bits, (priv->pshare->RegRF3C[eRFPath]&(~(0xF000)))|u4tmp); - -}; - -#endif - -#if 0 -//#ifdef CONFIG_RTL_88E_SUPPORT //for 88e tx power tracking - -void ODM_ResetIQKResult(struct rtl8192cd_priv *priv) -{ -/* -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte i; - - if (!IS_HARDWARE_TYPE_8192D(Adapter)) - return; -#endif -*/ - - unsigned char i; - - //printk("PHY_ResetIQKResult:: settings regs %d default regs %d\n", sizeof(priv->pshare->IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING), IQK_Matrix_Settings_NUM); - //0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc - - for(i = 0; i < IQK_Matrix_Settings_NUM; i++) - { - { - priv->pshare->IQKMatrixRegSetting[i].Value[0][0] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][2] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][4] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][6] = 0x100; - - priv->pshare->IQKMatrixRegSetting[i].Value[0][1] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][3] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][5] = - priv->pshare->IQKMatrixRegSetting[i].Value[0][7] = 0x0; - - priv->pshare->IQKMatrixRegSetting[i].bIQKDone = FALSE; - - } - } - -} - -#define RF_PATH_A 0 //Radio Path A -#define OFDM_TABLE_SIZE_92D 43 - -#define bRFRegOffsetMask 0xfffff - - -//091212 chiyokolin -void odm_TXPowerTrackingCallback_ThermalMeter_8188E(struct rtl8192cd_priv *priv) -{ - - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - unsigned char ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; - unsigned char ThermalValue_AVG_count = 0; - unsigned int ThermalValue_AVG = 0; - int ele_A=0, ele_D, TempCCk, X, value32; - int Y, ele_C=0; - char OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; - unsigned int i = 0, j = 0; - char is2T = FALSE; - //char bInteralPA = FALSE; - - unsigned char OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur - unsigned char Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/; - char OFDM_index_mapping[2][index_mapping_NUM_88E] = { - {0, 0, 2, 3, 4, 4, //2.4G, decrease power - 5, 6, 7, 7, 8, 9, - 10, 10, 11}, // For lower temperature, 20120220 updated on 20120220. - {0, 0, -1, -2, -3, -4, //2.4G, increase power - -4, -4, -4, -5, -7, -8, - -9, -9, -10}, - }; - unsigned char Thermal_mapping[2][index_mapping_NUM_88E] = { - {0, 2, 4, 6, 8, 10, //2.4G, decrease power - 12, 14, 16, 18, 20, 22, - 24, 26, 27}, - {0, 2, 4, 6, 8, 10, //2.4G,, increase power - 12, 14, 16, 18, 20, 22, - 25, 25, 25}, - }; - - priv->pshare->TXPowerTrackingCallbackCnt++; //cosa add for debug - priv->pshare->bTXPowerTrackingInit = TRUE; - -#if (MP_DRIVER == 1) - priv->pshare->TxPowerTrackControl = 1; //priv->pshare->TxPowerTrackControl; //_eric_?? // We should keep updating the control variable according to HalData. - // pshare->RegA24 will be initialized when ODM HW configuring, but MP configures with para files. - priv->pshare->RegA24 = 0x090e1317; -#endif - - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - if(priv->pshare->mp_txpwr_tracking == FALSE) - return; - } -#endif - - if(priv->pshare->Power_tracking_on_88E == 0) - { - priv->pshare->Power_tracking_on_88E = 1; - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x03); - return; - } - else - { - - priv->pshare->Power_tracking_on_88E = 0; - - //printk("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", priv->pshare->TxPowerTrackControl); - - ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, RF_T_METER_88E, 0xfc00, 1); //0x42: RF Reg[15:10] 88E - - printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); - - } - - if(is2T) - rf = 2; - else - rf = 1; - - if(ThermalValue) - { -// if(!pHalData->ThermalValue) - { - //Query OFDM path A default setting - ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; - - for(i=0; ipshare->RegA24; - - for(i=0 ; ipshare->bCCKinCH14) - { - if(memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==0) - { - CCK_index_old =(unsigned char) i; - //printk("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", - //rCCK0_TxFilter2, TempCCk, CCK_index_old, priv->pshare->bCCKinCH14); - break; - } - } - else - { - //printk("RegA24: 0x%X, CCKSwingTable_Ch1_Ch13[%d][2]: CCKSwingTable_Ch1_Ch13[i][2]: 0x%X\n", TempCCk, i, CCKSwingTable_Ch1_Ch13[i][2]); - if(memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==0) - { - CCK_index_old =(unsigned char) i; - //printk("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", - //rCCK0_TxFilter2, TempCCk, CCK_index_old, priv->pshare->bCCKinCH14); - break; - } - } - } - } - - if(!priv->pshare->ThermalValue) - { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_LCK = ThermalValue; - priv->pshare->ThermalValue_IQK = ThermalValue; - - for(i = 0; i < rf; i++) - priv->pshare->OFDM_index[i] = OFDM_index_old[i]; - priv->pshare->CCK_index = CCK_index_old; - } - - if(priv->pshare->bReloadtxpowerindex) - { - printk("reload ofdm index for band switch\n"); - } - - //calculate average thermal meter - { - priv->pshare->ThermalValue_AVG[priv->pshare->ThermalValue_AVG_index] = ThermalValue; - priv->pshare->ThermalValue_AVG_index++; - if(priv->pshare->ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) - priv->pshare->ThermalValue_AVG_index = 0; - - for(i = 0; i < AVG_THERMAL_NUM_88E; i++) - { - if(priv->pshare->ThermalValue_AVG[i]) - { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) - { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - printk("AVG Thermal Meter = 0x%x \n", ThermalValue); - } - } - } - - if(priv->pshare->bReloadtxpowerindex) - { - delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); - priv->pshare->bReloadtxpowerindex = FALSE; - priv->pshare->bDoneTxpower = FALSE; - } - else if(priv->pshare->bDoneTxpower) - { - delta = (ThermalValue > priv->pshare->ThermalValue)?(ThermalValue - priv->pshare->ThermalValue):(priv->pshare->ThermalValue - ThermalValue); - } - else - { - delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); - } - delta_LCK = (ThermalValue > priv->pshare->ThermalValue_LCK)?(ThermalValue - priv->pshare->ThermalValue_LCK):(priv->pshare->ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > priv->pshare->ThermalValue_IQK)?(ThermalValue - priv->pshare->ThermalValue_IQK):(priv->pshare->ThermalValue_IQK - ThermalValue); - - printk("Readback Thermal Meter = 0x%x \npre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x \ndelta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, priv->pshare->ThermalValue, priv->pshare->EEPROMThermalMeter, delta, delta_LCK, delta_IQK); - printk("pre thermal meter LCK 0x%x \npre thermal meter IQK 0x%x \ndelta_LCK_bound 0x%x delta_IQK_bound 0x%x\n", priv->pshare->ThermalValue_LCK, priv->pshare->ThermalValue_IQK, priv->pshare->Delta_LCK, priv->pshare->Delta_IQK); - - - //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) - if (delta_LCK >= 8) // Delta temperature is equal to or larger than 20 centigrade. - { - priv->pshare->ThermalValue_LCK = ThermalValue; - PHY_LCCalibrate(priv); - } - - - if(delta > 0 && priv->pshare->TxPowerTrackControl) - { - delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); - - //calculate new OFDM / CCK offset - { - { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) - j = 1; - else - j = 0; - - for(offset = 0; offset < index_mapping_NUM_88E; offset++) - { - if(delta < Thermal_mapping[j][offset]) - { - if(offset != 0) - offset--; - break; - } - } - if(offset >= index_mapping_NUM_88E) - offset = index_mapping_NUM_88E-1; - - index = OFDM_index_mapping[j][offset]; - - printk("\nj = %d delta = %d, index = %d\n\n", j, delta, index); - - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i] + OFDM_index_mapping[j][offset]; - CCK_index = priv->pshare->CCK_index + OFDM_index_mapping[j][offset]; - } - - if(is2T) - { - printk("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - priv->pshare->OFDM_index[0], priv->pshare->OFDM_index[1], priv->pshare->CCK_index); - } - else - { - printk("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", - priv->pshare->OFDM_index[0], priv->pshare->CCK_index); - } - - for(i = 0; i < rf; i++) - { - if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) - { - OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; - } - else if (OFDM_index[i] < OFDM_min_index) - { - OFDM_index[i] = OFDM_min_index; - } - } - - { - if(CCK_index > CCK_TABLE_SIZE-1) - CCK_index = CCK_TABLE_SIZE-1; - else if (CCK_index < 0) - CCK_index = 0; - } - - if(is2T) - { - printk("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], OFDM_index[1], CCK_index); - } - else - { - printk("new OFDM_A_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], CCK_index); - } - } - - //2 temporarily remove bNOPG - //Config by SwingTable - if(priv->pshare->TxPowerTrackControl /*&& !pHalData->bNOPG*/) - { - priv->pshare->bDoneTxpower = TRUE; - - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable[(unsigned char)OFDM_index[0]] & 0xFFC00000)>>22; - X = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][0]; - Y = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][1]; - - if(X != 0) - { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); - - } - else - { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned char)OFDM_index[0]]); - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); - } - - //printk("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n", - //(unsigned int)X, (unsigned int)Y, (unsigned int)ele_A, (unsigned int)ele_C, (unsigned int)ele_D, (unsigned int)X, (unsigned int)Y); - - { - //Adjust CCK according to IQK result - if(!priv->pshare->bCCKinCH14){ - RTL_W8(0xa22, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][0]); - RTL_W8(0xa23, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][1]); - RTL_W8(0xa24, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][2]); - RTL_W8(0xa25, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][3]); - RTL_W8(0xa26, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][4]); - RTL_W8(0xa27, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][5]); - RTL_W8(0xa28, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][6]); - RTL_W8(0xa29, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][7]); - } - else{ - RTL_W8(0xa22, CCKSwingTable_Ch14[(unsigned char)CCK_index][0]); - RTL_W8(0xa23, CCKSwingTable_Ch14[(unsigned char)CCK_index][1]); - RTL_W8(0xa24, CCKSwingTable_Ch14[(unsigned char)CCK_index][2]); - RTL_W8(0xa25, CCKSwingTable_Ch14[(unsigned char)CCK_index][3]); - RTL_W8(0xa26, CCKSwingTable_Ch14[(unsigned char)CCK_index][4]); - RTL_W8(0xa27, CCKSwingTable_Ch14[(unsigned char)CCK_index][5]); - RTL_W8(0xa28, CCKSwingTable_Ch14[(unsigned char)CCK_index][6]); - RTL_W8(0xa29, CCKSwingTable_Ch14[(unsigned char)CCK_index][7]); - } - } - - if(is2T) - { - ele_D = (OFDMSwingTable[(unsigned char)OFDM_index[1]] & 0xFFC00000)>>22; - - //new element A = element D x X - X = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][4]; - Y = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][5]; - - //if(X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G) - if((X != 0) && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) - - { - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); - - } - else - { - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned char)OFDM_index[1]]); - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); - } - - //printk("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - //(unsigned int)X, (unsigned int)Y, (unsigned int)ele_A, (unsigned int)ele_C, (unsigned int)ele_D, (unsigned int)X, (unsigned int)Y); - } - - printk("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n\n", PHY_QueryBBReg(priv, 0xc80, bMaskDWord), PHY_QueryBBReg(priv, 0xc94, bMaskDWord), PHY_QueryRFReg(priv, RF_PATH_A, 0x24, bRFRegOffsetMask, 1)); - } - } - - -#if 0 //DO NOT do IQK during 88E power tracking - // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) - if (delta_IQK >= 8) // Delta temperature is equal to or larger than 20 centigrade. - { - ODM_ResetIQKResult(priv); - -/* -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif -*/ - priv->pshare->ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8188E(priv, FALSE); - -/* -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -*/ - } -#endif - - //update thermal meter value - if(priv->pshare->TxPowerTrackControl) - { - //Adapter->HalFunc.SetHalDefVarHandler(Adapter, HAL_DEF_THERMAL_VALUE, &ThermalValue); - priv->pshare->ThermalValue = ThermalValue; - } - - } - - //printk("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"); - - priv->pshare->TXPowercount = 0; - -} - - - - -#endif - - - -#ifdef CONFIG_RTL_92D_SUPPORT - -void getDeltaValue(struct rtl8192cd_priv *priv) -{ - unsigned int tempval[2]; - - tempval[0] = priv->pmib->dot11RFEntry.deltaIQK; - tempval[1] = priv->pmib->dot11RFEntry.deltaLCK; - - switch(tempval[0]) - { - case 0: - tempval[0] = 5; - break; - - case 1: - tempval[0] = 4; - break; - - case 2: - tempval[0] = 3; - break; - - case 3: - default: - tempval[0] = 0; - break; - } - - switch(tempval[1]) - { - case 0: - tempval[1] = 4; - break; - - case 1: - tempval[1] = 3; - break; - - case 2: - tempval[1] = 2; - break; - - case 3: - default: - tempval[1] = 0; - break; - } - - priv->pshare->Delta_IQK = tempval[0]; - priv->pshare->Delta_LCK = tempval[1]; -} - -void tx_power_tracking_92D(struct rtl8192cd_priv *priv) -{ - u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, index[2], offset, ThermalValue_AVG_count = 0; - u32 ThermalValue_AVG = 0; - int ele_A, ele_D, X, value32, Y, ele_C; - char OFDM_index[2], CCK_index=0; - int i = 0; - char is2T = ((priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) ?1 :0); - u8 OFDM_min_index = 6, OFDM_min_index_internalPA = 5, rf=1, channel; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur u1Byte OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur - - u8 index_mapping[5][index_mapping_NUM] = { - {0, 1, 3, 6, 8, 9, //5G, path A/MAC 0, decrease power - 11, 13, 14, 16, 17, 18, 18}, - {0, 2, 4, 5, 7, 10, //5G, path A/MAC 0, increase power - 12, 14, 16, 18, 18, 18, 18}, - {0, 2, 3, 6, 8, 9, //5G, path B/MAC 1, decrease power - 11, 13, 14, 16, 17, 18, 18}, - {0, 2, 4, 5, 7, 10, //5G, path B/MAC 1, increase power - 13, 16, 16, 18, 18, 18, 18}, - {0, 1, 2, 3, 4, 5, //2.4G, for decreas power - 6, 7, 7, 8, 9, 10, 10}, - }; - -#if defined(RTL8192D_INT_PA) - - u8 index_mapping_internalPA[8][index_mapping_NUM] = { - {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch36-64, decrease power - 9, 11, 13, 15, 16, 16, 16}, - {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch36-64, increase power - 9, 11, 13, 15, 16, 18, 20}, - {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch100-165, decrease power - 9, 11, 13, 15, 16, 16, 16}, - {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch100-165, increase power - 9, 11, 13, 15, 16, 18, 20}, - {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch36-64, decrease power - 9, 11, 13, 15, 16, 16, 16}, - {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch36-64, increase power - 9, 11, 13, 15, 16, 18, 20}, - {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch100-165, decrease power - 9, 11, 13, 15, 16, 16, 16}, - {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch100-165, increase power - 9, 11, 13, 15, 16, 18, 20}, - }; - - u8 bInteralPA[2]; - -#endif - -#ifdef DPK_92D - short index_mapping_DPK[4][index_mapping_DPK_NUM]={ - {0, 0, 1, 2, 2, //path A current thermal > PG thermal - 3, 4, 5, 5, 6, - 7, 7, 8, 9, 9}, - {0, 0, -1, -2, -3, //path A current thermal < PG thermal - -3, -4, -5, -6, -6, - -7, -8, -9, -9, -10}, - {0, 0, 1, 2, 2, //path B current thermal > PG thermal - 3, 4, 5, 5, 6, - 7, 7, 8, 9, 9}, - {0, 0, -1, -2, -3, //path B current thermal < PG thermal - -3, -4, -5, -6, -6, - -7, -8, -9, -9, -10} - }; - - u8 delta_DPK; - short index_DPK[2] = { 0xb68, 0xb6c }, value_DPK, value_DPK_shift; - int j; - - if(priv->pshare->bDPKworking) { - DEBUG_INFO("DPK in progress abort tx power tracking \n"); - return; - } - -#endif - - -#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 - -u8 index_mapping_HighPower_PA[12][index_mapping_NUM] = { - {0, 2, 3, 4, 7, 8, 10, 12, 13, 15, 16, 17, 18}, //5G, path A/MAC 0, ch36-64, decrease power - {0, 2, 4, 7, 8, 10, 11, 15, 17, 19, 21, 23, 23}, //5G, path A/MAC 0, ch36-64, increase power - {0, 4, 5, 8, 9, 11, 14, 15, 16, 17, 18, 19, 20}, //5G, path A/MAC 0, ch100-140, decrease power - {0, 2, 4, 5, 7, 9, 13, 15, 19, 21, 22, 23, 23}, //5G, path A/MAC 0, ch100-140, increase power - {0, 4, 5, 8, 9, 11, 14, 15, 17, 18, 19, 20, 21}, //5G, path A/MAC 0, ch149-165, decrease power - {0, 2, 4, 6, 8, 10, 14, 16, 19, 21, 22, 24, 24}, //5G, path A/MAC 0, ch149-165, increase power - {0, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17}, //5G, path B/MAC 1, ch36-64, decrease power - {0, 2, 4, 7, 8, 10, 11, 15, 17, 19, 21, 23, 23}, //5G, path B/MAC 1, ch36-64, increase power - {0, 3, 4, 6, 7, 9, 12, 13, 14, 15, 17, 18, 19}, //5G, path B/MAC 1, ch100-140, decrease power - {0, 2, 4, 5, 7, 9, 13, 15, 19, 21, 22, 23, 23}, //5G, path B/MAC 1, ch100-140, increase power - {0, 3, 4, 6, 7, 9, 12, 13, 15, 16, 17, 18, 19}, //5G, path B/MAC 1, ch149-165, decrease power - {0, 3, 5, 7, 9, 11, 13, 17, 19, 21, 22, 23, 23}, //5G, path B/MAC 1, ch149-165, increase power - }; - -#endif - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel=priv->pshare->working_channel; - if(priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } -#if 0 - if (priv->pshare->pwr_trk_ongoing==0) { - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER_92D, bMask20Bits, 0x30000); - priv->pshare->pwr_trk_ongoing = 1; - return; - } - else -#endif - { - ThermalValue =(unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER_92D, 0xf800, 1); -// priv->pshare->pwr_trk_ongoing = 0; -#ifdef DPK_92D - priv->pshare->ThermalValue_DPKtrack = ThermalValue; -#endif - } - DEBUG_INFO("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx\n", ThermalValue, - priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); - - if(is2T) - rf = 2; - else - rf = 1; - - if (ThermalValue) { - - //Query OFDM path A default setting - ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for(i=0; ipshare->OFDM_index0[0] = i; - DEBUG_INFO("Initial pathA ele_D reg0x%x = 0x%lx, OFDM_index=0x%x\n", - rOFDM0_XATxIQImbalance, ele_D, priv->pshare->OFDM_index0[0]); - break; - } - } - - //Query OFDM path B default setting - if(is2T) { - ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; - for(i=0; ipshare->OFDM_index0[1] = i; - DEBUG_INFO("Initial pathB ele_D reg0x%x = 0x%lx, OFDM_index=0x%x\n", - rOFDM0_XBTxIQImbalance, ele_D, priv->pshare->OFDM_index0[1]); - break; - } - } - } - - if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - priv->pshare->CCK_index0 = get_CCK_swing_index(priv); - } else { - priv->pshare->CCK_index0 = 12; - } - - if(!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_LCK = ThermalValue; - priv->pshare->ThermalValue_IQK = ThermalValue; -#ifdef RX_GAIN_TRACK_92D - priv->pshare->ThermalValue_RxGain = priv->pmib->dot11RFEntry.ther; -#endif -#ifdef DPK_92D - priv->pshare->ThermalValue_DPK = ThermalValue; -#endif - for(i = 0; i < rf; i++) - priv->pshare->OFDM_index[i] = priv->pshare->OFDM_index0[i]; - priv->pshare->CCK_index = priv->pshare->CCK_index0; - } - - - //calculate average thermal meter - { - priv->pshare->Thermal_log[priv->pshare->Thermal_idx] = ThermalValue; - priv->pshare->Thermal_idx = (priv->pshare->Thermal_idx+1)%8; - - for(i=0; i<8; i++) { - if(priv->pshare->Thermal_log[i]) { - ThermalValue_AVG += priv->pshare->Thermal_log[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) - ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count); - } - - - delta = RTL_ABS(ThermalValue, priv->pshare->ThermalValue); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); - -// printk("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", -// ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK); - - getDeltaValue(priv); - -#ifdef DPK_92D - - if(priv->pshare->bDPKstore) { - - priv->pshare->ThermalValue_DPK = ThermalValue; - delta_DPK = 0; - - for(j = 0; j < rf; j++) { - - if(priv->pshare->ThermalValue_DPKstore > priv->pmib->dot11RFEntry.ther) - value_DPK_shift = index_mapping_DPK[j*2][priv->pshare->ThermalValue_DPKstore- priv->pmib->dot11RFEntry.ther]; - else - value_DPK_shift = index_mapping_DPK[j*2+1][priv->pmib->dot11RFEntry.ther- priv->pshare->ThermalValue_DPKstore]; - - for(i = 0; i < index_mapping_DPK_NUM; i++) { - priv->pshare->index_mapping_DPK_current[j*2][i] = - index_mapping_DPK[j*2][i]-value_DPK_shift; - priv->pshare->index_mapping_DPK_current[j*2+1][i] = - index_mapping_DPK[j*2+1][i]-value_DPK_shift; - } - } - } - else - { - delta_DPK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_DPK); - } - - for(j = 0; j < rf; j++) { - if(!priv->pshare->bDPKdone[j]) - priv->pshare->OFDM_min_index_internalPA_DPK[j] = 0; - } - -#endif - -#if 1 - if ((delta_LCK > priv->pshare->Delta_LCK) && (priv->pshare->Delta_LCK != 0)) { - priv->pshare->ThermalValue_LCK = ThermalValue; - PHY_LCCalibrate_92D(priv); - } -#endif - if(delta > 0 -#ifdef DPK_92D - ||(priv->pshare->bDPKstore) -#endif - ){ - if(delta == 0 && priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - goto TxPowerDPK; -#ifdef DPK_92D - if(priv->pshare->bDPKstore) - priv->pshare->bDPKstore = FALSE; -#endif - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - - //calculate new OFDM / CCK offset - { - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G){ - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) - { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i] - get_tx_tracking_index(priv, channel, i, delta, 0, 0); - - CCK_index = priv->pshare->CCK_index - get_tx_tracking_index(priv, channel, 0, delta, 0, 1); - } - else - { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i] + get_tx_tracking_index(priv, channel, i, delta, 1, 0); - - CCK_index = priv->pshare->CCK_index + get_tx_tracking_index(priv, channel, i, delta, 1, 1); - } - } - else -#endif - { - offset = 4; - - if(delta > index_mapping_NUM-1) - index[0] = index_mapping[offset][index_mapping_NUM-1]; - else - index[0] = index_mapping[offset][delta]; - - if(ThermalValue > priv->pmib->dot11RFEntry.ther) { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i] - delta; - CCK_index = priv->pshare->CCK_index - delta; - } - else { - for(i = 0; i < rf; i++) - OFDM_index[i] = priv->pshare->OFDM_index[i] + index[0]; - CCK_index = priv->pshare->CCK_index + index[0]; - } - } - } else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - for(i = 0; i < rf; i++){ - -#if defined(RTL8192D_INT_PA) - - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx==1) //MAC 1 5G - bInteralPA[i] = priv->pshare->phw->InternalPA5G[1]; - else - bInteralPA[i] = priv->pshare->phw->InternalPA5G[i]; - - if(bInteralPA[i]) { - if(priv->pshare->wlandev_idx == 1 || i == 1/*rf*/) - offset = 4; - else - offset = 0; - if(channel >= 100 && channel <= 165) - offset += 2; - } - else -#endif - { - if(priv->pshare->wlandev_idx == 1 || i == 1) - offset = 2; - else - offset = 0; - } - - -#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 - if(i == 0) - { - if(channel <= 99) - offset = 0; - else if(channel <= 140) - offset = 2; - else - offset = 4; - } - else - { - if(channel <= 99) - offset = 6; - else if(channel <= 140) - offset = 8; - else - offset = 10; - } -#endif - - - if(ThermalValue > priv->pmib->dot11RFEntry.ther) //set larger Tx power - offset++; -#if defined(RTL8192D_INT_PA) - if(bInteralPA[i]) { - if(delta > index_mapping_NUM-1) - index[i] = index_mapping_internalPA[offset][index_mapping_NUM-1]; - else - index[i] = index_mapping_internalPA[offset][delta]; - } else -#endif - { - if(delta > index_mapping_NUM-1) - index[i] = index_mapping[offset][index_mapping_NUM-1]; - else - index[i] = index_mapping[offset][delta]; - } - - - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) - { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) - index[i] = get_tx_tracking_index(priv, channel, i, delta, 0, 0); - else - index[i] = get_tx_tracking_index(priv, channel, i, delta, 1, 0); - } - else -#endif - { -#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 - { - if(delta > index_mapping_NUM-1) - index[i] = index_mapping_HighPower_PA[offset][index_mapping_NUM-1]; - else - index[i] = index_mapping_HighPower_PA[offset][delta]; - - //printk("\n\n offset = %d delta = %d \n", offset, delta); - //printk("index[%d]= %d\n\n", i, index[i]); - } -#endif - } - - - - if(ThermalValue > priv->pmib->dot11RFEntry.ther) //set larger Tx power - { -#if 0 - if(bInteralPA[i] && ThermalValue > 0x12) - index[i] = ((delta/2)*3+(delta%2)); -#endif - OFDM_index[i] = priv->pshare->OFDM_index[i] -index[i]; - } - else - { - OFDM_index[i] = priv->pshare->OFDM_index[i] + index[i]; - } - } - } - - if(is2T) - { - DEBUG_INFO("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - priv->pshare->OFDM_index[0], priv->pshare->OFDM_index[1], priv->pshare->CCK_index); - } - else - { - DEBUG_INFO("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", - priv->pshare->OFDM_index[0], priv->pshare->CCK_index); - } - - for(i = 0; i < rf; i++) - { - if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) { - OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; - } - else if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - if (OFDM_index[i] < (OFDM_min_index_internalPA)) - OFDM_index[i] = (OFDM_min_index_internalPA); - } else if(bInteralPA[i]) { -#ifdef DPK_92D - if (OFDM_index[i] < (OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i])) - { - priv->pshare->TxPowerLevelDPK[i] = OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i]-OFDM_index[i]; - OFDM_index[i] = (OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i]); - } - else - { - priv->pshare->TxPowerLevelDPK[i] = 0; - } -#else - if (OFDM_index[i] < (OFDM_min_index_internalPA)) - { - OFDM_index[i] = (OFDM_min_index_internalPA); - } -#endif - } else if(OFDM_index[i] < OFDM_min_index) { -#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 -#else - OFDM_index[i] = OFDM_min_index; -#endif - } - } - - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G){ - if(CCK_index > CCK_TABLE_SIZE_92D-1) - CCK_index = CCK_TABLE_SIZE_92D-1; - else if (CCK_index < 0) - CCK_index = 0; - } - - if(is2T) { - DEBUG_INFO("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], OFDM_index[1], CCK_index); - } - else - { - DEBUG_INFO("new OFDM_A_index=0x%x, CCK_index=0x%x\n", - OFDM_index[0], CCK_index); - } - } - - //Config by SwingTable - { - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable_92D[(unsigned int)OFDM_index[0]] & 0xFFC00000)>>22; - X = priv->pshare->RegE94; - Y = priv->pshare->RegE9C; - - if(X != 0 && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)){ - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); - - } - else - { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92D[(unsigned int)OFDM_index[0]]); - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); -#ifdef MP_TEST - if ((priv->pshare->rf_ft_var.mp_specific) && (!is2T)) { - unsigned char str[50]; - sprintf(str, "patha=%d,pathb=%d", priv->pshare->mp_txpwr_patha, priv->pshare->mp_txpwr_pathb); - mp_set_tx_power(priv, str); - } -#endif - } - DEBUG_INFO("TxPwrTracking for interface %d path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", - priv->pshare->wlandev_idx, X, Y, ele_A, ele_C, ele_D); - - - if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - { - //Adjust CCK according to IQK result - set_CCK_swing_index(priv, CCK_index); - } - - if(is2T) - { - ele_D = (OFDMSwingTable_92D[(unsigned int)OFDM_index[1]] & 0xFFC00000)>>22; - - //new element A = element D x X - X = priv->pshare->RegEB4; - Y = priv->pshare->RegEBC; - - if(X != 0 && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)){ - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D)>>8)&0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); - - } - else{ - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92D[(unsigned int)OFDM_index[1]]); - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); -#ifdef MP_TEST - if ((priv->pshare->rf_ft_var.mp_specific) ) { - unsigned char str[50]; - sprintf(str, "patha=%d,pathb=%d", priv->pshare->mp_txpwr_patha, priv->pshare->mp_txpwr_pathb); - mp_set_tx_power(priv, str); - - } -#endif - } - - DEBUG_INFO("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", - X, Y, ele_A, ele_C, ele_D); - } - - DEBUG_INFO("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", PHY_QueryBBReg(priv, 0xc80, bMaskDWord), - PHY_QueryBBReg(priv, 0xc94, bMaskDWord), PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x24, bMask20Bits,1)); - } - } - -TxPowerDPK: -#ifdef DPK_92D - { - char bNOPG = FALSE; - unsigned char pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[channel-1]; - if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) - pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[channel-1]; -#ifdef CONFIG_RTL_92D_DMDP - if ((priv->pmib->dot11RFEntry.macPhyMode==DUALMAC_DUALPHY) && - (priv->pshare->wlandev_idx == 1) && (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)) - pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[channel-1]; - if (pwrlevelHT40_1S_A == 0) - bNOPG = TRUE; -#endif - - //for DPK - if(delta_DPK > 0 && !bNOPG /*&& pHalData->bDPKdone*/) { - for(i = 0; i < rf; i++) { - if(bInteralPA[i] && priv->pshare->bDPKdone[i]) { - if(ThermalValue > priv->pmib->dot11RFEntry.ther) - value_DPK = priv->pshare->index_mapping_DPK_current[i*2][ThermalValue-priv->pmib->dot11RFEntry.ther]; - else - value_DPK = priv->pshare->index_mapping_DPK_current[i*2+1][priv->pmib->dot11RFEntry.ther-ThermalValue]; - - PHY_SetBBReg(priv, index_DPK[i], 0x7c00, value_DPK); - } - } - priv->pshare->ThermalValue_DPK = ThermalValue; - } - } -#endif - priv->pshare->pwr_trk_ongoing = 0; -#if 1 - if ((delta_IQK > priv->pshare->Delta_IQK) && (priv->pshare->Delta_IQK != 0)) { - priv->pshare->ThermalValue_IQK = ThermalValue; - PHY_IQCalibrate(priv); - } -#endif - -#ifdef RX_GAIN_TRACK_92D - if(priv->pmib->dot11RFEntry.ther && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) && - (ThermalValue < priv->pmib->dot11RFEntry.ther)) { - priv->pshare->ThermalValue_RxGain = ThermalValue; - rx_gain_tracking_92D(priv); - } -#endif - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - } -} - -#endif - -//3 ============================================================ -//3 EDCA Turbo -//3 ============================================================ - -void init_EDCA_para(struct rtl8192cd_priv *priv, int mode) -{ - static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time; - - struct ParaRecord EDCA[4]; -#ifdef RTL_MANUAL_EDCA - //unsigned char acm_bitmap; -#endif - - slot_time = 20; - sifs_time = 10; - - if (mode & WIRELESS_11N) - sifs_time = 16; - -#ifdef RTL_MANUAL_EDCA - if( priv->pmib->dot11QosEntry.ManualEDCA ) { - memset(EDCA, 0, 4*sizeof(struct ParaRecord)); - if( OPMODE & WIFI_AP_STATE ) - memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord)); - else - memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord)); - - - if ((mode & WIRELESS_11N) || - (mode & WIRELESS_11G)) { - slot_time = 9; - } - - - RTL_W32(EDCA_VO_PARA, (EDCA[VO].TXOPlimit << 16) | (EDCA[VO].ECWmax << 12) | (EDCA[VO].ECWmin << 8) | (sifs_time + EDCA[VO].AIFSN * slot_time)); -#ifdef WIFI_WMM - if (QOS_ENABLE) - RTL_W32(EDCA_VI_PARA, (EDCA[VI].TXOPlimit << 16) | (EDCA[VI].ECWmax << 12) | (EDCA[VI].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); - else -#endif - RTL_W32(EDCA_VI_PARA, (EDCA[BE].TXOPlimit << 16) | (EDCA[BE].ECWmax << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); - - RTL_W32(EDCA_BE_PARA, (EDCA[BE].TXOPlimit << 16) | (EDCA[BE].ECWmax << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[BE].AIFSN * slot_time)); - - RTL_W32(EDCA_BK_PARA, (EDCA[BK].TXOPlimit << 16) | (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[BK].AIFSN * slot_time)); - }else -#endif //RTL_MANUAL_EDCA - { - memset(EDCA, 0, 4*sizeof(struct ParaRecord)); - /* copy BE, BK from static data */ - if( OPMODE & WIFI_AP_STATE ) - memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord)); - else - memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord)); - - /* VI, VO apply settings in AG by default */ - if( OPMODE & WIFI_AP_STATE ) - memcpy(&EDCA[2], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); - else - memcpy(&EDCA[2], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); - - if ((mode & WIRELESS_11N) || - (mode & WIRELESS_11G)) { - slot_time = 9; - } else { - /* replace with settings in B */ - if( OPMODE & WIFI_AP_STATE ) - memcpy(&EDCA[2], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord)); - else - memcpy(&EDCA[2], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord)); - } - VO_TXOP = EDCA[VO].TXOPlimit; - VI_TXOP = EDCA[VI].TXOPlimit; - - RTL_W32(EDCA_VO_PARA, (VO_TXOP << 16) | (EDCA[VO].ECWmax << 12) | (EDCA[VO].ECWmin << 8) | (sifs_time + EDCA[VO].AIFSN * slot_time)); -#ifdef WIFI_WMM - if (QOS_ENABLE) - RTL_W32(EDCA_VI_PARA, (VI_TXOP << 16) | (EDCA[VI].ECWmax << 12) | (EDCA[VI].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); - else -#endif - RTL_W32(EDCA_VI_PARA, (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); - - RTL_W32(EDCA_BE_PARA, ((EDCA[BE].ECWmax) << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[BE].AIFSN * slot_time)); - RTL_W32(EDCA_BK_PARA, (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[BK].AIFSN * slot_time)); - - - RTL_W8(ACMHWCTRL, 0x00); - } - - priv->pshare->iot_mode_enable = 0; - if (priv->pshare->rf_ft_var.wifi_beq_iot) - priv->pshare->iot_mode_VI_exist = 0; - priv->pshare->iot_mode_VO_exist = 0; - -#ifdef WMM_VIBE_PRI - priv->pshare->iot_mode_BE_exist = 0; -#endif -#ifdef WMM_BEBK_PRI - priv->pshare->iot_mode_BK_exist = 0; -#endif -#ifdef LOW_TP_TXOP - priv->pshare->BE_cwmax_enhance = 0; -#endif -} -#if 0 -void choose_IOT_main_sta(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int i, assoc_num = GET_ROOT(priv)->assoc_num; -#ifdef MBSSID - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ - for (i=0; ipvap_priv[i]-> assoc_num; - } -#endif -#ifdef UNIVERSAL_REPEATER - if (IS_DRV_OPEN(GET_VXD_PRIV(GET_ROOT(priv)))) - assoc_num += GET_VXD_PRIV(GET_ROOT(priv))-> assoc_num; -#endif -#ifdef WDS - if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) - assoc_num ++; -#endif - - if (priv->pshare->rf_ft_var.low_tp_no_aggr) { - unsigned long sta_tp = (pstat->current_tx_bytes + pstat->current_rx_bytes) >> 17; - if (!pstat->low_tp_disable_ampdu && sta_tp <= 2) - pstat->low_tp_disable_ampdu = 1; - else if (pstat->low_tp_disable_ampdu && sta_tp >= 5) - pstat->low_tp_disable_ampdu = 0; - } - - if ((GET_ROOT(priv)->up_time % 2) == 0) { - unsigned int tx_2s_avg = 0; - unsigned int rx_2s_avg = 0; - int i=0, aggReady=0; - unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes); - - pstat->current_tx_bytes += pstat->tx_byte_cnt; - pstat->current_rx_bytes += pstat->rx_byte_cnt; - - if (total_sum != 0) { - if (total_sum <= 1000000) { - tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum); - rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum); - } else { - tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100)); - rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100)); - } - } - - for(i=0; i<8; i++) - aggReady += (pstat->ADDBA_ready[i]); - - if( (pstat->IOTPeer==HT_IOT_PEER_INTEL) - || (pstat->ht_cap_len && aggReady)) { - - if ((assoc_num==1) || (tx_2s_avg + rx_2s_avg >= 25)) { - priv->pshare->highTP_found_pstat = pstat; - } /*this STA's TXRX packet very close AP's total TXRX packet then let it as highTP_found_pstat*/ - else if(RTL_ABS((pstat->current_tx_bytes + pstat->current_rx_bytes) , total_sum)<50){ - priv->pshare->highTP_found_pstat = pstat; - } -#ifdef CLIENT_MODE - if (OPMODE & WIFI_STATION_STATE) { -// if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45)) - if(pstat->IOTPeer == HT_IOT_PEER_RALINK && ((tx_2s_avg + rx_2s_avg) >= 45)) - priv->pshare->highTP_found_pstat = pstat; - } -#endif - } - } - else { - pstat->current_tx_bytes = pstat->tx_byte_cnt; - pstat->current_rx_bytes = pstat->rx_byte_cnt; - } -} -#endif - -void rxBB_dm(struct rtl8192cd_priv *priv) -{ - if ((priv->up_time % 3) == 1) { - if (priv->pshare->rssi_min != 0xff) { - if (priv->pshare->rf_ft_var.dig_enable) { - // for DIG checking - check_DIG_by_rssi(priv, priv->pshare->rssi_min); - } -//#ifdef INTERFERENCE_CONTROL - if (priv->pshare->rf_ft_var.nbi_filter_enable) { - check_NBI_by_rssi(priv, priv->pshare->rssi_min); - } -//#endif - } - -#ifdef MP_TEST - if (!((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific)) -#endif - { -#ifdef HIGH_POWER_EXT_LNA - if (!priv->pshare->rf_ft_var.use_ext_lna) -#endif - CCK_CCA_dynamic_enhance(priv, priv->pshare->rssi_min); - } - } - if (priv->pshare->rf_ft_var.adaptivity_enable){ - unsigned char IGI; - IGI = RTL_R8(0xc50); - rtl8192cd_Adaptivity(priv,IGI); - } -} - -/* - * IOT related functions - */ -void IOT_engine(struct rtl8192cd_priv *priv) -{ -#ifdef WIFI_WMM - unsigned int switch_turbo = 0; -#endif -#ifdef MBSSID - int i; -#endif - int assoc_num = priv->assoc_num; - struct stat_info *pstat = priv->pshare->highTP_found_pstat; - - if(pstat) { - if((pstat->tx_avarage + pstat->rx_avarage) < (1<<17)) // 1M bps - pstat = NULL; - } -#if defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM) - if(priv->pmib->dot11QosEntry.ManualEDCA) - return ; -#endif - -#ifdef MBSSID - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ - for (i=0; ipvap_priv[i]-> assoc_num; - } -#endif -#ifdef UNIVERSAL_REPEATER - if (IS_DRV_OPEN(GET_VXD_PRIV(GET_ROOT(priv)))) - assoc_num += GET_VXD_PRIV(GET_ROOT(priv))-> assoc_num; -#endif -#ifdef WDS - if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) - assoc_num ++; -#endif - -#ifdef WIFI_WMM - if (QOS_ENABLE) { - if (!priv->pmib->dot11OperationEntry.wifi_specific || - ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))) { - if (priv->pshare->iot_mode_enable && - ((priv->pshare->phw->VO_pkt_count > 50) || - (priv->pshare->phw->VI_pkt_count > 50) || - (priv->pshare->phw->BK_pkt_count > 50))) { - priv->pshare->iot_mode_enable = 0; - switch_turbo++; - } else if ((!priv->pshare->iot_mode_enable) && - ((priv->pshare->phw->VO_pkt_count < 50) && - (priv->pshare->phw->VI_pkt_count < 50) && - (priv->pshare->phw->BK_pkt_count < 50))) { - priv->pshare->iot_mode_enable++; - switch_turbo++; - } - } - - if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { - if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) { - priv->pshare->iot_mode_VO_exist++; - switch_turbo++; - } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) { - priv->pshare->iot_mode_VO_exist = 0; - switch_turbo++; - } - -#ifdef WMM_VIBE_PRI - if (priv->pshare->iot_mode_VO_exist) { - //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count); - if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) { - priv->pshare->iot_mode_BE_exist++; - switch_turbo++; - } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) { - priv->pshare->iot_mode_BE_exist = 0; - switch_turbo++; - } - } -#endif - -#ifdef WMM_BEBK_PRI - if (priv->pshare->phw->BE_pkt_count) { - //printk("[%s %d] BK_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BK_pkt_count); - if (!priv->pshare->iot_mode_BK_exist && (priv->pshare->phw->BK_pkt_count > 250)) { - priv->pshare->iot_mode_BK_exist++; - switch_turbo++; - EDEBUG("switch_turbo++\n"); - } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BK_pkt_count < 250)) { - priv->pshare->iot_mode_BK_exist = 0; - switch_turbo++; - EDEBUG("switch_turbo++\n"); - } - } -#endif - - if (priv->pshare->rf_ft_var.wifi_beq_iot) { - if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) { - priv->pshare->iot_mode_VI_exist++; - switch_turbo++; - } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) { - priv->pshare->iot_mode_VI_exist = 0; - switch_turbo++; - } - } - -#ifdef CONFIG_RTL_92D_DMDP - if ((GET_CHIP_VER(priv) == VERSION_8192D) && (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) { - unsigned int tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); - if (priv->pshare->rf_ft_var.wifi_beq_iot) { - if (priv->pshare->wifi_beq_lower && priv->pshare->iot_mode_VI_exist && tp <= 20) { - priv->pshare->wifi_beq_lower= 0; - switch_turbo++; - } else if (!priv->pshare->wifi_beq_lower&& (!priv->pshare->iot_mode_VI_exist || tp > 20)) { - priv->pshare->wifi_beq_lower= 1; - switch_turbo++; - } - } - } -#endif - } - -#ifdef CLIENT_MODE - if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) - { - if (priv->pshare->iot_mode_enable && - (((priv->pshare->phw->VO_pkt_count > 50) || - (priv->pshare->phw->VI_pkt_count > 50) || - (priv->pshare->phw->BK_pkt_count > 50)) || - (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3])))) - { - priv->pshare->iot_mode_enable = 0; - switch_turbo++; - } - else if ((!priv->pshare->iot_mode_enable) && - (((priv->pshare->phw->VO_pkt_count < 50) && - (priv->pshare->phw->VI_pkt_count < 50) && - (priv->pshare->phw->BK_pkt_count < 50)) && - (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3])))) - { - priv->pshare->iot_mode_enable++; - switch_turbo++; - } - } -#endif - - priv->pshare->phw->VO_pkt_count = 0; - priv->pshare->phw->VI_pkt_count = 0; - if (priv->pshare->rf_ft_var.wifi_beq_iot) - priv->pshare->phw->VI_rx_pkt_count = 0; - priv->pshare->phw->BK_pkt_count = 0; -#ifdef WMM_VIBE_PRI - priv->pshare->phw->BE_pkt_count = 0; -#endif - } -#endif - - if ((priv->up_time % 2) == 0) { - /* - * decide EDCA content for different chip vendor - */ -#ifdef WIFI_WMM - if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || - ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) -#ifdef CLIENT_MODE - || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) -#endif - )) { - if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) { -#ifdef LOW_TP_TXOP - - - if (pstat->IOTPeer==HT_IOT_PEER_INTEL) - - { - - if (priv->pshare->txop_enlarge != 0xe) { - priv->pshare->txop_enlarge = 0xe; - if (priv->pshare->iot_mode_enable) - switch_turbo++; - } - } else if (priv->pshare->txop_enlarge != 2) { - priv->pshare->txop_enlarge = 2; - if (priv->pshare->iot_mode_enable) - switch_turbo++; - } -#else //LOW_TP_TXOP - - if (priv->pshare->txop_enlarge != 2) { - - - { - if (pstat->IOTPeer==HT_IOT_PEER_INTEL) - priv->pshare->txop_enlarge = 0xe; - else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) - priv->pshare->txop_enlarge = 0xd; - else - priv->pshare->txop_enlarge = 2; - - } - - if (priv->pshare->iot_mode_enable) - switch_turbo++; - } -#endif //LOW_TP_TXOP - } else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) { - if (priv->pshare->txop_enlarge) { - priv->pshare->txop_enlarge = 0; - if (priv->pshare->iot_mode_enable) - switch_turbo++; - } - } -#ifdef LOW_TP_TXOP - // for Intel IOT, need to enlarge CW MAX from 6 to 10 - - - if (pstat && pstat->IOTPeer==HT_IOT_PEER_INTEL && (((pstat->tx_avarage+pstat->rx_avarage)>>10) < - priv->pshare->rf_ft_var.cwmax_enhance_thd)) - - { - if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable) { - priv->pshare->BE_cwmax_enhance = 1; - switch_turbo++; - } - } else { - if (priv->pshare->BE_cwmax_enhance) { - priv->pshare->BE_cwmax_enhance = 0; - switch_turbo++; - } - } -#endif - } -#endif - - priv->pshare->current_tx_bytes = 0; - priv->pshare->current_rx_bytes = 0; - } - -#ifdef SW_TX_QUEUE - if ((assoc_num > 1) && (AMPDU_ENABLE)) - { - unsigned int total_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17)+(unsigned int)(priv->ext_stats.rx_avarage>>17); - if(total_tp > 0) { - if (((unsigned int)(priv->ext_stats.tx_avarage>>17) * 100/total_tp) > 30) - { - if (priv->pshare->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd) - { - if ((priv->pshare->swq_en == 0)) - { - switch_turbo++; - if (priv->pshare->txop_enlarge == 0) - priv->pshare->txop_enlarge = 2; - priv->pshare->swq_en = 1; - priv->pshare->swqen_keeptime = priv->up_time; - } - else - { - if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) - { - priv->pshare->txop_enlarge = 2; - switch_turbo--; - } - } - } - else if(priv->pshare->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd) - { - priv->pshare->swq_en = 0; - priv->pshare->swqen_keeptime = 0; - } - else if ((priv->pshare->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) - { - priv->pshare->txop_enlarge = 2; - switch_turbo--; - } - } - else if (((unsigned int)(priv->ext_stats.tx_avarage>>17) * 100/total_tp) < 20) - { - priv->pshare->swq_en = 0; - priv->pshare->swqen_keeptime = 0; - } - } - //debug msg - //printk("swq=%d,sw=%d,en=%d,mode=%d\n", priv->pshare->swq_en, switch_turbo, priv->pshare->txop_enlarge, priv->pshare->iot_mode_enable); - } -#if 1//defined(CONFIG_RTL_819XD) - else if( (assoc_num == 1) && (priv->up_time % 2)== 0 && (AMPDU_ENABLE) ) { - //if (pstat) { -// if ((pstat) && pstat->is_intel_sta) { - if ((pstat) && pstat->IOTPeer == HT_IOT_PEER_INTEL) { -// int en_thd = 14417920; - //if ((priv->pshare->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) ) { //50Mbps - if ((pstat->current_tx_bytes > 14417920) && (priv->pshare->swq_en == 0)) { // && (pstat->current_rx_bytes > 14417920) && (priv->pshare->swq_en == 0)) { //55Mbps - priv->pshare->swq_en = 1; - priv->pshare->swqen_keeptime = priv->up_time; - } - //else if ((priv->pshare->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps - else if ((pstat->tx_avarage < 9175040) && (priv->pshare->swq_en == 1)) { //35Mbps - priv->pshare->swq_en = 0; - priv->pshare->swqen_keeptime = 0; - } - } - else { - priv->pshare->swq_en = 0; - priv->pshare->swqen_keeptime = 0; - } - } -#endif -#endif - -#ifdef WIFI_WMM -#ifdef LOW_TP_TXOP - if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)) - && QOS_ENABLE) { - - if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) { - unsigned int thd_tp; - unsigned char under_thd; - unsigned int curr_tp; - - if (priv->pmib->dot11BssType.net_work_type & (WIRELESS_11N | WIRELESS_11G)) - { - // Determine the upper bound throughput threshold. - if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) { - if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num) - thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; - else - thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n; - } - else - thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; - - // Determine to close txop. -#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) - if(pstat && pstat->expire_to) - { - struct rtl8192cd_priv *tmppriv; - struct aid_obj *aidarray; - aidarray = container_of(pstat, struct aid_obj, station); - tmppriv = aidarray->priv; - - curr_tp = (unsigned int)(tmppriv->ext_stats.tx_avarage>>17) + (unsigned int)(tmppriv->ext_stats.rx_avarage>>17); - } - else -#endif - curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); - if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low) - under_thd = 1; - else - under_thd = 0; - } - else - { - under_thd = 0; - } - - if (switch_turbo) { - priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; - priv->pshare->rf_ft_var.low_tp_txop_count = 0; - } else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) { - priv->pshare->rf_ft_var.low_tp_txop_count++; - if (priv->pshare->rf_ft_var.low_tp_txop_close) { - priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay; - } - if (priv->pshare->rf_ft_var.low_tp_txop_count == priv->pshare->rf_ft_var.low_tp_txop_delay) { - priv->pshare->rf_ft_var.low_tp_txop_count = 0; - priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; - switch_turbo++; - } - } else { - priv->pshare->rf_ft_var.low_tp_txop_count = 0; - } - } - } -#endif - - if (switch_turbo) - IOT_EDCA_switch(priv, priv->pmib->dot11BssType.net_work_type, priv->pshare->iot_mode_enable); -#endif -} - - -#ifdef WIFI_WMM -void IOT_EDCA_switch(struct rtl8192cd_priv *priv, int mode, char enable) -{ - unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94; - unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs; - - if (!(!priv->pmib->dot11OperationEntry.wifi_specific || - ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) -#ifdef CLIENT_MODE - || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) -#endif - )) - return; - - if ((mode & WIRELESS_11N) && (priv->pshare->ht_sta_num -#ifdef WDS - || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) -#endif - )) - sifs_time = 16; - - if (mode & (WIRELESS_11G | WIRELESS_11N)) { - slot_time = 9; - } else { - BE_TXOP = 94; - VI_TXOP = 188; - } - -#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) - if (priv->pshare->is_40m_bw) - { - BE_TXOP = 23; - } -#endif - - if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { - if (priv->pshare->iot_mode_VO_exist) { -#ifdef WMM_VIBE_PRI - if (priv->pshare->iot_mode_BE_exist) { - vi_cw_max = 5; - vi_cw_min = 3; - vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); - } else -#endif - { - vi_cw_max = 6; - vi_cw_min = 4; - vi_aifs = 0x2b; - } - } else { - vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); - } - - RTL_W32(EDCA_VI_PARA, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16) - | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); - -#ifdef WMM_BEBK_PRI -#ifdef CONFIG_RTL_88E_SUPPORT - if ((GET_CHIP_VER(priv) == VERSION_8188E ) && priv->pshare->iot_mode_BK_exist) { - RTL_W32(EDCA_BK_PARA, (10 << 12) | (6 << 8) | 0x4f); - } -#endif -#endif - } - - if (!enable || (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist)) { - if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist) { -#ifdef CONFIG_RTL_92D_DMDP - if ((GET_CHIP_VER(priv) == VERSION_8192D) && (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) { - if (priv->pshare->wifi_beq_lower) - RTL_W32(EDCA_BE_PARA, (10 << 12) | (4 << 8) | (sifs_time + 10 * slot_time)); - else - RTL_W32(EDCA_BE_PARA, (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); - } else -#endif - RTL_W32(EDCA_BE_PARA, (10 << 12) | (4 << 8) | 0x4f); - } else { - RTL_W32(EDCA_BE_PARA, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8) - | (sifs_time + 3 * slot_time)); - } - RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); - } else { -#ifdef LOW_TP_TXOP - int txop; - unsigned int cw_max; - unsigned int txop_close; - - cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6); - txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0); - txop = (txop_close ? 0 : (BE_TXOP*2)); -#endif - if (priv->pshare->ht_sta_num -#ifdef WDS - || ((OPMODE & WIFI_AP_STATE) && (mode & WIRELESS_11N) && - priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) -#endif - ) { -/* - if (priv->pshare->txop_enlarge == 0xf) { - // is 8192S client - RTL_W32(EDCA_BE_PARA, ((BE_TXOP*2) << 16) | - (6 << 12) | (4 << 8) | (sifs_time + slot_time+ 0xf)); // 0xf is 92s circuit delay - priv->pshare->txop_enlarge = 2; - } - else -*/ - if (priv->pshare->txop_enlarge == 0xe) { -#ifndef LOW_TP_TXOP - // is intel client, use a different edca value -#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); -#else - //RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (4 << 8) | 0x1f); - if (get_rf_mimo_mode(priv) == MIMO_1T1R) - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); - else - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (8 << 12) | (5 << 8) | 0x1f); - - RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) & ~(DIS_TXOP_CFE)); -#endif - priv->pshare->txop_enlarge = 2; - } else if (priv->pshare->txop_enlarge == 0xd) { - // is intel ralink, use a different edca value - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (4 << 12) | (3 << 8) | 0x19); - priv->pshare->txop_enlarge = 2; - } else { - if (priv->pshare->txop_enlarge == 0) - RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); - - if (get_rf_mimo_mode(priv) == MIMO_2T2R) -#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) - RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | - (6 << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); -#else - RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | - (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); -#endif - else -#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) - RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | - (5 << 12) | (4 << 8) | (sifs_time + 2 * slot_time)); -#else - RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | - (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); -#endif - -#else - // is intel client, use a different edca value - if (get_rf_mimo_mode(priv) == MIMO_1T1R) - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); - else - RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | 0x1f); - } else { - txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge)); - - if (get_rf_mimo_mode(priv) == MIMO_2T2R) - RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); - else - RTL_W32(EDCA_BE_PARA, (txop << 16) | (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | - (3 << 8) | (sifs_time + 2 * slot_time)); -#endif - } - } else { -#ifdef LOW_TP_TXOP - RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); -#else -#if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8197DL) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); -#else - RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); -#endif - if (priv->pshare->txop_enlarge == 0xe) - RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) & ~(DIS_TXOP_CFE)); - else - RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); -#endif - } -/* - if (priv->pmib->dot11OperationEntry.wifi_specific == 2) { - RTL_W16(NAV_PROT_LEN, 0x01C0); - RTL_W8(CFEND_TH, 0xFF); - set_fw_reg(priv, 0xfd000ab0, 0, 0); - } -*/ - } -} - -//end of IOT_EDCA_switch -//======================================================================================================== - -#if 0 -void check_NAV_prot_len(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned int disassoc) -{ - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat - && pstat->ht_cap_len && pstat->is_intel_sta) { - if (!disassoc && (pstat->MIMO_ps & _HT_MIMO_PS_DYNAMIC_)) { - setSTABitMap(&priv->pshare->mimo_ps_dynamic_sta, pstat->aid); - } else { - clearSTABitMap(&priv->pshare->mimo_ps_dynamic_sta, pstat->aid); - } - -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv) != VERSION_8188E) -#endif - { - if (orSTABitMap(&priv->pshare->mimo_ps_dynamic_sta) { - RTL_W8(NAV_PROT_LEN, 0x40); - } else { - RTL_W8(NAV_PROT_LEN, 0x20); - } - } - } -} -#endif -#endif - - -//3 ============================================================ -//3 FA statistic functions -//3 ============================================================ -#if 0 - -#if !defined(CONFIG_RTL_NEW_AUTOCH) -static -#endif -void reset_FA_reg(struct rtl8192cd_priv *priv) -{ -#if !defined(CONFIG_RTL_NEW_AUTOCH) - unsigned char value8; - - value8 = RTL_R8(0xd03); - RTL_W8(0xd03, value8 | 0x08); // regD00[27]=1 to reset these OFDM FA counters - value8 = RTL_R8(0xd03); - RTL_W8(0xd03, value8 & 0xF7); // regD00[27]=0 to start counting - value8 = RTL_R8(0xa2d); - RTL_W8(0xa2d, value8 & 0x3F); // regA2D[7:6]=00 to disable counting - value8 = RTL_R8(0xa2d); - RTL_W8(0xa2d, value8 | 0x80); // regA2D[7:6]=10 to enable counting -#else - /* cck CCA */ - PHY_SetBBReg(priv, 0xa2c, BIT(13) | BIT(12), 0); - PHY_SetBBReg(priv, 0xa2c, BIT(13) | BIT(12), 2); - /* cck FA*/ - PHY_SetBBReg(priv, 0xa2c, BIT(15) | BIT(14), 0); - PHY_SetBBReg(priv, 0xa2c, BIT(15) | BIT(14), 2); - /* ofdm */ - PHY_SetBBReg(priv, 0xd00, BIT(27), 1); - PHY_SetBBReg(priv, 0xd00, BIT(27), 0); -#endif - -#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) - if (GET_CHIP_VER(priv) == VERSION_8192D){ - PHY_SetBBReg(priv, 0xf14, BIT(16),1); - PHY_SetBBReg(priv, 0xf14, BIT(16),0); - RTL_W32(RXERR_RPT, RTL_R32(RXERR_RPT)|BIT(27)); - RTL_W32(RXERR_RPT, RTL_R32(RXERR_RPT)&(~BIT(27))); - } -#endif - -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv)==VERSION_8188E) { - PHY_SetBBReg(priv, 0xc0c, BIT(31), 1); - PHY_SetBBReg(priv, 0xc0c, BIT(31), 0); - } -#endif -} - -#if defined(CONFIG_RTL_NEW_AUTOCH) -void hold_CCA_FA_counter(struct rtl8192cd_priv *priv) -{ - /* hold cck CCA & FA counter */ - PHY_SetBBReg(priv, 0xa2c, BIT(12), 1); - PHY_SetBBReg(priv, 0xa2c, BIT(14), 1); - - /* hold ofdm CCA & FA counter */ - PHY_SetBBReg(priv, 0xc00, BIT(31), 1); - PHY_SetBBReg(priv, 0xd00, BIT(31), 1); -} - -void release_CCA_FA_counter(struct rtl8192cd_priv *priv) -{ - /* release cck CCA & FA counter */ - PHY_SetBBReg(priv, 0xa2c, BIT(12), 0); - PHY_SetBBReg(priv, 0xa2c, BIT(14), 0); - - /* release ofdm CCA & FA counter */ - PHY_SetBBReg(priv, 0xc00, BIT(31), 0); - PHY_SetBBReg(priv, 0xd00, BIT(31), 0); - -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv)==VERSION_8188E) { - PHY_SetBBReg(priv, 0xc0c, BIT(31), 1); - PHY_SetBBReg(priv, 0xc0c, BIT(31), 0); - } -#endif -} - - -void _FA_statistic(struct rtl8192cd_priv *priv) -{ - // read OFDM FA counters - priv->pshare->ofdm_FA_cnt1 = RTL_R16(0xda2); - priv->pshare->ofdm_FA_cnt2 = RTL_R16(0xda4); - priv->pshare->ofdm_FA_cnt3 = RTL_R16(0xda6); - priv->pshare->ofdm_FA_cnt4 = RTL_R16(0xda8); - - priv->pshare->cck_FA_cnt = (RTL_R8(0xa5b) << 8) + RTL_R8(0xa5c); - -#ifdef INTERFERENCE_CONTROL - priv->pshare->ofdm_FA_total_cnt = (unsigned int) priv->pshare->ofdm_FA_cnt1 + - priv->pshare->ofdm_FA_cnt2 + priv->pshare->ofdm_FA_cnt3 + - priv->pshare->ofdm_FA_cnt4 + RTL_R16(0xcf0) + RTL_R16(0xcf2); - - priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_total_cnt + priv->pshare->cck_FA_cnt; -#else - priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + - priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4 + - priv->pshare->cck_FA_cnt + RTL_R16(0xcf0) + RTL_R16(0xcf2); -#endif -} -#endif - -void FA_statistic(struct rtl8192cd_priv *priv) -{ - -#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) - if (GET_CHIP_VER(priv) == VERSION_8192D){ -// priv->pshare->F90_cnt = PHY_QueryBBReg(priv, 0xf90, bMaskHWord); - priv->pshare->F94_cnt = PHY_QueryBBReg(priv, 0xf94, bMaskHWord); - priv->pshare->F94_cntOK = PHY_QueryBBReg(priv, 0xf94, bMaskLWord); - RTL_W32(RXERR_RPT,(RTL_R32(RXERR_RPT)&0x0fffffff)|0x70000000); - priv->pshare->Reg664_cnt = RTL_R32(RXERR_RPT) & 0xfffff; - RTL_W32(RXERR_RPT,(RTL_R32(RXERR_RPT)&0x0fffffff)|0x60000000); - priv->pshare->Reg664_cntOK = RTL_R32(RXERR_RPT) & 0xfffff; - } -#endif - -#if !defined(CONFIG_RTL_NEW_AUTOCH) - signed char value8; - - // read OFDM FA counters - priv->pshare->ofdm_FA_cnt1 = RTL_R16(0xda2); - priv->pshare->ofdm_FA_cnt2 = RTL_R16(0xda4); - priv->pshare->ofdm_FA_cnt3 = RTL_R16(0xda6); - priv->pshare->ofdm_FA_cnt4 = RTL_R16(0xda8); - - // read the CCK FA counters - value8 = RTL_R8(0xa2d); - RTL_W8(0xa2d, value8 | 0x40); // regA2D[6]=1 to hold and read the CCK FA counters - priv->pshare->cck_FA_cnt = RTL_R8(0xa5b); - priv->pshare->cck_FA_cnt = priv->pshare->cck_FA_cnt << 8; - priv->pshare->cck_FA_cnt += RTL_R8(0xa5c); -#ifdef INTERFERENCE_CONTROL - priv->pshare->ofdm_FA_total_cnt = (unsigned int) priv->pshare->ofdm_FA_cnt1 + - priv->pshare->ofdm_FA_cnt2 + priv->pshare->ofdm_FA_cnt3 + - priv->pshare->ofdm_FA_cnt4 + RTL_R16(0xcf0) + RTL_R16(0xcf2); - - priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_total_cnt + priv->pshare->cck_FA_cnt; -#else - - priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + - priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4 + - priv->pshare->cck_FA_cnt + RTL_R16(0xcf0) + RTL_R16(0xcf2); -#endif - if (priv->pshare->rf_ft_var.rssi_dump) - priv->pshare->CCA_total_cnt = ((RTL_R8(0xa60)<<8)|RTL_R8(0xa61)) + RTL_R16(0xda0); -#else - hold_CCA_FA_counter(priv); - _FA_statistic(priv); - - if (priv->pshare->rf_ft_var.rssi_dump) - priv->pshare->CCA_total_cnt = ((RTL_R8(0xa60)<<8)|RTL_R8(0xa61)) + RTL_R16(0xda0); - - release_CCA_FA_counter(priv); -#endif - - reset_FA_reg(priv); - -#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) - if (GET_CHIP_VER(priv) == VERSION_8192D){ - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G && !(OPMODE & WIFI_SITE_MONITOR)) { - if (priv->pshare->DNC_on == 0){ - //if ((priv->pshare->F94_cnt + priv->pshare->F90_cnt)> 3000){ - /* Reg 664: x > y && x > 1000 - Reg F94: x > 0.75*y && x > 1000 */ - if (((priv->pshare->Reg664_cnt>priv->pshare->Reg664_cntOK) && (priv->pshare->Reg664_cnt > 1000))|| - ((priv->pshare->F94_cnt > ((priv->pshare->Reg664_cntOK*3)>>2)) && (priv->pshare->F94_cnt > 1000))) { - priv->ext_stats.tp_average_pre = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; - priv->pshare->DNC_on = 1; - priv->pshare->DNC_chk_cnt = 1; - priv->pshare->DNC_chk = 2; // 0: don't check, 1; check, 2: just entering DNC - //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07600760); - PHY_SetBBReg(priv, 0xc50, bMaskByte0, 0x20); - PHY_SetBBReg(priv, 0xc58, bMaskByte0, 0x20); - //printk("Dynamic Noise Control ON\n"); - } - } else { - if ((priv->pshare->DNC_chk_cnt % 5)==0){ // check every 5*2=10 seconds - unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; - priv->pshare->DNC_chk_cnt = 0; - - if ((priv->pshare->DNC_chk == 2) && (tp_now < priv->ext_stats.tp_average_pre+5)){ - //no advantage, leave DNC state - priv->pshare->DNC_on = 0; - priv->pshare->DNC_chk = 0; - //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); - } - else - { - priv->pshare->DNC_chk = 0; - - /* If TP < 20M or TP varies more than 5M. Start Checking...*/ - if ((tp_now < 20) || ((tp_now < (priv->ext_stats.tp_average_pre-5))|| (tp_now > (priv->ext_stats.tp_average_pre+5)))){ - priv->pshare->DNC_chk = 1; - //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); - if (!timer_pending(&priv->dnc_timer)) { - //printk("... Start Check Noise ...\n"); - mod_timer(&priv->dnc_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); // 100 ms - } - } - } - - priv->ext_stats.tp_average_pre = tp_now; - - } else if ((priv->pshare->DNC_chk_cnt % 5)==1 && priv->pshare->DNC_chk == 1) { - priv->pshare->DNC_chk = 0; - //if ((priv->pshare->F94_cnt + priv->pshare->F90_cnt) < 120) { - if ((priv->pshare->F94_cnt + priv->pshare->Reg664_cnt) < 120) { - priv->pshare->DNC_on = 0; - //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); - //printk("Dynamic Noise Control OFF\n"); - } - } - priv->pshare->DNC_chk_cnt++; - } - } - } -#endif -} - - -//3 ============================================================ -//3 Rate Adaptive -//3 ============================================================ - -void check_RA_by_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int level = 0; - - switch (pstat->rssi_level) { - case 1: - if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) - level = 1; - else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || - ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && - (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && - (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) - level = 2; - else - level = 3; - break; - case 2: - if (pstat->rssi > priv->pshare->rf_ft_var.raGoUpUpper) - level = 1; - else if ((pstat->rssi < priv->pshare->rf_ft_var.raGoDown40MLower) || - ((!pstat->ht_cap_len || !priv->pshare->is_40m_bw || - !(pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_))) && - (pstat->rssi < priv->pshare->rf_ft_var.raGoDown20MLower))) - level = 3; - else - level = 2; - break; - case 3: - if (pstat->rssi > priv->pshare->rf_ft_var.raGoUpUpper) - level = 1; - else if ((pstat->rssi > priv->pshare->rf_ft_var.raGoUp20MLower) || - ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && - (pstat->rssi > priv->pshare->rf_ft_var.raGoUp40MLower) && - (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) - level = 2; - else - level = 3; - break; - default: - if (isErpSta(pstat)) - DEBUG_ERR("wrong rssi level setting\n"); - break; - } - - if (level != pstat->rssi_level) { - pstat->rssi_level = level; -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv)==VERSION_8188E) { -#ifdef TXREPORT - add_RATid(priv, pstat); -#endif - } else -#endif - { -#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) - add_update_RATid(priv, pstat); -#endif - } - } -} -#endif - -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - -void check_txrate_by_reg(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - unsigned char initial_rate = 0x7f; - unsigned char legacyRA =0 ; - - if( should_restrict_Nrate(priv, pstat) && is_fixedMCSTxRate(priv, pstat)) - legacyRA = 1; - - if (pstat->sta_in_firmware == 1) - { - if (is_auto_rate(priv , pstat) || legacyRA) - { - initial_rate = RTL_R8(INIDATA_RATE_SEL + REMAP_AID(pstat)) & 0x7f; - if (initial_rate == 0x7f) - return; - - if ((initial_rate&0x3f) < 12) { - pstat->current_tx_rate = dot11_rate_table[initial_rate&0x3f]; - pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; - } else { - pstat->current_tx_rate = HT_RATE_ID + ((initial_rate&0x3f) -12); - if (initial_rate & BIT(6)) - pstat->ht_current_tx_info |= TX_USE_SHORT_GI; - else - pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; - } - - priv->pshare->current_tx_rate = pstat->current_tx_rate; - priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; - } else if (pstat->ht_cap_len) { - unsigned int is_sgi = 0; - - if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40) -#ifdef WIFI_11N_2040_COEXIST - && !((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11nConfigEntry.dot11nCoexist && - (priv->bg_ap_timeout || orForce20_Switch20Map(priv) - )) -#endif - ) { - if (priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M - && (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_))) - is_sgi++; - } else if (priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M - && (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_))) { - is_sgi++; - } - - if (is_sgi) - pstat->ht_current_tx_info |= TX_USE_SHORT_GI; - else - pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; - } - - if (pstat->ht_cap_len) { - if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40)) - pstat->ht_current_tx_info |= TX_USE_40M_MODE; - else - pstat->ht_current_tx_info &= ~TX_USE_40M_MODE; - } - - priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; - } else { - DEBUG_INFO("sta has no aid found to check current tx rate\n"); - } -} -#endif -#if 0 -void add_RATid(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - unsigned char limit=16; - int i; - unsigned long flags; - unsigned int update_reg=0; - - SAVE_INT_AND_CLI(flags); - - pstat->tx_ra_bitmap = 0; - - for (i=0; i<32; i++) { - if (pstat->bssrateset[i]) - pstat->tx_ra_bitmap |= get_bit_value_from_ieee_value(pstat->bssrateset[i]&0x7f); - } - - if (pstat->ht_cap_len) { - if ((pstat->MIMO_ps & _HT_MIMO_PS_STATIC_) || - (get_rf_mimo_mode(priv)== MIMO_1T2R) || - (get_rf_mimo_mode(priv)== MIMO_1T1R)) - limit=8; - - for (i=0; iht_cap_buf.support_mcs[i/8] & BIT(i%8)) - pstat->tx_ra_bitmap |= BIT(i+12); - } - } - - if (pstat->ht_cap_len) { - unsigned int set_sgi = 0; - if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40) -#ifdef WIFI_11N_2040_COEXIST - && !((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11nConfigEntry.dot11nCoexist && - (priv->bg_ap_timeout || orForce20_Switch20Map(priv) - )) -#endif - ) { - if (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_) - && priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M) - set_sgi++; - } else if (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_) && - priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M) { - set_sgi++; - } - - if (set_sgi) { -#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) - if (GET_CHIP_VER(priv)==VERSION_8188E) - priv->pshare->RaInfo[pstat->aid].SGIEnable = 1; - else -#endif - pstat->tx_ra_bitmap |= BIT(28); - } -#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) - else { - if (GET_CHIP_VER(priv)==VERSION_8188E) - priv->pshare->RaInfo[pstat->aid].SGIEnable = 0; - } -#endif - } -#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) - else { - if (GET_CHIP_VER(priv)==VERSION_8188E) - priv->pshare->RaInfo[pstat->aid].SGIEnable = 0; - } -#endif - - if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) { - if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) - pstat->rssi_level = 1; - else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || - ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && - (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && - (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) - pstat->rssi_level = 2; - else - pstat->rssi_level = 3; - } - - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && - ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G))) - pstat->tx_ra_bitmap &= 0xfffffff0; //disable cck rate - -#ifdef P2P_SUPPORT - if(pstat->is_p2p_client){ - pstat->tx_ra_bitmap &= 0xfffffff0; //disable cck rate - } -#endif - - // rate adaptive by rssi - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && (!should_restrict_Nrate(priv, pstat))) { - if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x100f0000; - break; - case 2: - pstat->tx_ra_bitmap &= 0x100ff000; - break; - case 3: - if (priv->pshare->is_40m_bw) - pstat->tx_ra_bitmap &= 0x100ff005; - else - pstat->tx_ra_bitmap &= 0x100ff001; - break; - } - } else { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x1f8f0000; - break; - case 2: - pstat->tx_ra_bitmap &= 0x1f8ff000; - break; - case 3: - if (priv->pshare->is_40m_bw) - pstat->tx_ra_bitmap &= 0x010ff005; - else - pstat->tx_ra_bitmap &= 0x010ff001; - break; - } - - // Don't need to mask high rates due to new rate adaptive parameters - //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta - // pstat->tx_ra_bitmap &= 0x81ffffff; - - // NIC driver will report not supporting MCS15 and MCS14 in asoc req - //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) - // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14 - } - } - else if (((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) || - ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && - ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)))) - { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x00000f00; - break; - case 2: - pstat->tx_ra_bitmap &= 0x00000ff0; - break; - case 3: - pstat->tx_ra_bitmap &= 0x00000ff5; - break; - } - } else { - pstat->tx_ra_bitmap &= 0x0000000d; - } - -// Client mode IOT issue, Button 2009.07.17 -#ifdef CLIENT_MODE - if(OPMODE & WIFI_STATION_STATE) { - if(!pstat->is_rtl8192s_sta && pstat->is_realtek_sta && pstat->is_legacy_encrpt) - pstat->tx_ra_bitmap &= 0x0001ffff; // up to MCS4 - } -#endif -#if defined(CONFIG_RTL_92D_SUPPORT) && defined (USB_POWER_SUPPORT) - if ((GET_CHIP_VER(priv)==VERSION_8192D) && (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)) - pstat->tx_ra_bitmap &= USB_RA_MASK; -#endif - - update_remapAid(priv, pstat); - -#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) - if (GET_CHIP_VER(priv)==VERSION_8188E) { -#ifndef RATEADAPTIVE_BY_ODM - if (pstat->tx_ra_bitmap & 0xff000) { - if (priv->pshare->is_40m_bw) - priv->pshare->RaInfo[pstat->aid].RateID = ARFR_1T_40M; - else - priv->pshare->RaInfo[pstat->aid].RateID = ARFR_1T_20M; - } else if (pstat->tx_ra_bitmap & 0xff0) { - priv->pshare->RaInfo[pstat->aid].RateID = ARFR_BG_MIX; - } else { - priv->pshare->RaInfo[pstat->aid].RateID = ARFR_B_ONLY; - } - - priv->pshare->RaInfo[pstat->aid].RateMask = pstat->tx_ra_bitmap; - ARFBRefresh(priv, &priv->pshare->RaInfo[pstat->aid]); -#else - PODM_RA_INFO_T pRAInfo = &(ODMPTR->RAInfo[pstat->aid]); - if (pstat->tx_ra_bitmap & 0xff000) { - if (priv->pshare->is_40m_bw) - pRAInfo->RateID = ARFR_1T_40M; - else - pRAInfo->RateID = ARFR_1T_20M; - } else if (pstat->tx_ra_bitmap & 0xff0) { - pRAInfo->RateID = ARFR_BG_MIX; - } else { - pRAInfo->RateID = ARFR_B_ONLY; - } - ODM_RA_UpdateRateInfo_8188E(ODMPTR, pstat->aid, pRAInfo->RateID, pstat->tx_ra_bitmap, pRAInfo->RateSGI); -#endif - } else -#endif -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - { - - if (pstat->sta_in_firmware == 1) - { -#ifdef CONFIG_RTL_92D_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { - pstat->tx_ra_bitmap &= 0xfffffff0; - if (pstat->tx_ra_bitmap & 0xff00000) { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_40M, pstat->tx_ra_bitmap); - else - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_20M, pstat->tx_ra_bitmap); - update_reg++; - } else if (pstat->tx_ra_bitmap & 0xff000) { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_40M, pstat->tx_ra_bitmap); - else - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_20M, pstat->tx_ra_bitmap); - } else if (pstat->tx_ra_bitmap & 0xff0) { - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_Band_A_BMC, pstat->tx_ra_bitmap); - } else { - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_Band_A_BMC, pstat->tx_ra_bitmap); - } - } else -#endif - { - if (pstat->tx_ra_bitmap & 0xff00000) { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_40M, pstat->tx_ra_bitmap); - else - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_20M, pstat->tx_ra_bitmap); - update_reg++; - } else if (pstat->tx_ra_bitmap & 0xff000) { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_1T_40M, pstat->tx_ra_bitmap); - else - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_1T_20M, pstat->tx_ra_bitmap); - } else if (pstat->tx_ra_bitmap & 0xff0) { - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_BG_MIX, pstat->tx_ra_bitmap); - } else { - set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_B_ONLY, pstat->tx_ra_bitmap); - } - } - - /* - * Rate adaptive algorithm. - * If the STA is 2R, we set the inti rate to MCS 15 - */ - if (update_reg) { - if (!pstat->check_init_tx_rate && (pstat->rssi > 55)) { - pstat->check_init_tx_rate = 1; - } - } - DEBUG_INFO("Add id %d val %08x to ratr\n", pstat->aid, pstat->tx_ra_bitmap); - } else { -#ifdef CONFIG_RTL_92D_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_Band_A_40M, 0x1ffffff0); - else - set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_Band_A_20M, 0x1ffffff0); - } else -#endif - { - if (priv->pshare->is_40m_bw) - set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_40M, 0x1fffffff); - else - set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_20M, 0x1fffffff); - } - - } - } -#endif - - RESTORE_INT(flags); -} -#endif - -void set_rssi_cmd(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ -#ifndef SMP_SYNC - unsigned long flags; -#endif - unsigned int content = 0; - - int rssi = pstat->rssi; - -#ifdef HIGH_POWER_EXT_PA - if( priv->pshare->rf_ft_var.use_ext_pa ) - rssi += RSSI_DIFF_PA; - if( rssi > 100) - rssi = 100; -#endif - - - SAVE_INT_AND_CLI(flags); - - /* - * set rssi - */ - content = rssi<< 24; - -#ifdef CONFIG_RTL_92D_SUPPORT - /* - * set max macid - */ - if (GET_CHIP_VER(priv) == VERSION_8192D){ - content |= priv->pshare->max_fw_macid << 16; - } -#endif - - /* - * set macid - */ - content |= REMAP_AID(pstat) << 8; - - /* - * set cmd id - */ - content |= H2C_CMD_RSSI; - - signin_h2c_cmd(priv, content, 0); - - RESTORE_INT(flags); -} - -#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) -#ifdef CONFIG_PCI_HCI -void add_rssi_timer(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - struct stat_info *pstat = NULL; - unsigned int set_timer = 0; - unsigned long flags = 0; - - if (!(priv->drv_state & DRV_STATE_OPEN)) - return; - - if (timer_pending(&priv->add_rssi_timer)) - del_timer_sync(&priv->add_rssi_timer); - -#ifdef PCIE_POWER_SAVING - if ((priv->pwr_state == L2) || (priv->pwr_state == L1)) - return; -#endif - - if (!list_empty(&priv->addrssi_list)) { - pstat = list_entry(priv->addrssi_list.next, struct stat_info, addrssi_list); - if (!pstat) - return; - - if (!is_h2c_buf_occupy(priv)) { - set_rssi_cmd(priv, pstat); - if (!list_empty(&pstat->addrssi_list)) { - SAVE_INT_AND_CLI(flags); - SMP_LOCK(flags); - list_del_init(&pstat->addrssi_list); - RESTORE_INT(flags); - SMP_UNLOCK(flags); - } - - if (!list_empty(&priv->addrssi_list)) - set_timer++; - } else { - set_timer++; - } - } - - if (set_timer) - mod_timer(&priv->add_rssi_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(50)); // 50 ms -} - - -void add_update_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ -#ifndef SMP_SYNC - unsigned long flags; -#endif - - if (is_h2c_buf_occupy(priv)) { - if (list_empty(&pstat->addrssi_list)) { - SAVE_INT_AND_CLI(flags); - list_add_tail(&(pstat->addrssi_list), &(priv->addrssi_list)); - RESTORE_INT(flags); - - if (!timer_pending(&priv->add_rssi_timer)) - mod_timer(&priv->add_rssi_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(50)); // 50 ms - } - } else { - set_rssi_cmd(priv, pstat); - } -} -#endif // CONFIG_PCI_HCI - -#ifdef CONFIG_USB_HCI -void add_update_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - notify_update_sta_rssi(priv, pstat); -} -#endif // CONFIG_USB_HCI -#endif // CONFIG_RTL_92D_SUPPORT || CONFIG_RTL_92C_SUPPORT - - -void set_RATid_cmd(struct rtl8192cd_priv *priv, unsigned int macid, unsigned int rateid, unsigned int ratemask) -{ - unsigned int content = 0; - unsigned short ext_content = 0; - -//#ifdef CONFIG_RTL_8812_SUPPORT - if(! CHIP_VER_92X_SERIES(priv)) - return; -//#endif - - /* - * set ratemask - */ - ext_content = ratemask & 0xffff; - content = ((ratemask & 0xfff0000) >> 16) << 8; - - /* - * set short GI - */ - if (ratemask & BIT(28)) - content |= BIT(29); - - /* - * set macid (station aid) - */ - content |= (macid & 0x1f) << 24; - - /* - * set rateid (ARFR table) - */ - content |= (rateid & 0xf) << 20; - - /* - * set ext_content used - */ - content |= BIT(7); - - /* - * set cmd id - */ - content |= H2C_CMD_MACID; - - signin_h2c_cmd(priv, content, ext_content); -} - - - -//3 ============================================================ -//3 EDCCA -//3 ============================================================ -#if 0 -void check_EDCCA(struct rtl8192cd_priv *priv, short rssi) -{ - if ((priv->pshare->rf_ft_var.edcca_thd) && (priv->pmib->dot11RFEntry.dot11channel==14 - || priv->pshare->is_40m_bw -#if defined(CONFIG_RTL_92D_SUPPORT) - || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) -#endif - )) { - if((rssi > priv->pshare->rf_ft_var.edcca_thd) && (priv->pshare->phw->EDCCA_on == 0)) { - RTL_W32(rOFDM0_ECCAThreshold, 0xfc03fd); - priv->pshare->phw->EDCCA_on =1; - } else if( (rssi < priv->pshare->rf_ft_var.edcca_thd-5) && priv->pshare->phw->EDCCA_on) { - RTL_W32(rOFDM0_ECCAThreshold, 0x7f037f); - priv->pshare->phw->EDCCA_on =0; - } - } - if ((!priv->pshare->rf_ft_var.edcca_thd) && priv->pshare->phw->EDCCA_on) { - RTL_W32(0xc4c, 0x7f037f); - priv->pshare->phw->EDCCA_on = 0; - } -} -#endif - -//3 ============================================================ -//3 Antenna Diversity -//3 ============================================================ -#ifdef SW_ANT_SWITCH - -// -// 20100514 Luke/Joseph: -// Add new function to reset antenna diversity state after link. -// - -void resetSwAntDivVariable(struct rtl8192cd_priv *priv) -{ - priv->pshare->RSSI_sum_R = 0; - priv->pshare->RSSI_cnt_R = 0; - priv->pshare->RSSI_sum_L = 0; - priv->pshare->RSSI_cnt_L = 0; - priv->pshare->TXByteCnt_R = 0; - priv->pshare->TXByteCnt_L = 0; - priv->pshare->RXByteCnt_R = 0; - priv->pshare->RXByteCnt_L = 0; - -} -void SwAntDivRestAfterLink(struct rtl8192cd_priv *priv) -{ - priv->pshare->RSSI_test = FALSE; - priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_RESET; - memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); - priv->pshare->DM_SWAT_Table.mapIndex = 0; - priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; - priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; - resetSwAntDivVariable(priv); -} - - -void dm_SW_AntennaSwitchInit(struct rtl8192cd_priv *priv) -{ - if(!priv->pshare->rf_ft_var.antSw_enable) - return; - -// if (GET_CHIP_VER(priv) == VERSION_8188C) - if(get_rf_mimo_mode(priv)== MIMO_1T1R) - priv->pshare->rf_ft_var.antSw_select = 0; - - //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS:Init SW Antenna Switch\n")); - resetSwAntDivVariable(priv); - priv->pshare->DM_SWAT_Table.CurAntenna = Antenna_L; - priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_RESET; - memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); - priv->pshare->DM_SWAT_Table.mapIndex = 0; - -#ifdef GPIO_ANT_SWITCH -#ifdef CONFIG_RTL_92D_DMDP - if(priv->pshare->wlandev_idx==0) - priv->pshare->rf_ft_var.antHw_enable=0; - else - return; -#endif -// GPIO 45 : -// GPIO_MOD => data port -// GPIO_IO_SEL => output - RTL_W32(GPIO_PIN_CTRL, 0x00300000| RTL_R32(GPIO_PIN_CTRL)); - PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, priv->pshare->DM_SWAT_Table.CurAntenna); - RTL_W32(rFPGA0_XCD_RFParameter, RTL_R32(rFPGA0_XCD_RFParameter)| BIT(15)|BIT(16)); // enable ANTSEL - -#else - RTL_W32(LEDCFG, RTL_R32(LEDCFG) | BIT(23) ); //enable LED[1:0] pin as ANTSEL - - if ( !priv->pshare->rf_ft_var.antSw_select) { - RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) | BIT(13) ); //select ANTESEL from path A - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(8)| BIT(9) ); // enable ANTSEL A as SW control - RTL_W32(rFPGA0_XA_RFInterfaceOE, (RTL_R32(rFPGA0_XA_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna - } else { - RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) & ~ BIT(13) ); //select ANTESEL from path B - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(24)| BIT(25) ); // enable ANTSEL B as SW control - RTL_W32(rFPGA0_XB_RFInterfaceOE, (RTL_R32(rFPGA0_XB_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna - } - RTL_W16(rFPGA0_TxInfo, (RTL_R16(rFPGA0_TxInfo)&0xf0ff) | BIT(8) ); // b11-b8=0001 -#endif - - // Move the timer initialization to InitializeVariables function. - //PlatformInitializeTimer(Adapter, &pMgntInfo->SwAntennaSwitchTimer, (RT_TIMER_CALL_BACK)dm_SW_AntennaSwitchCallback, NULL, "SwAntennaSwitchTimer"); -} -// -// 20100514 Luke/Joseph: -// Add new function for antenna diversity after link. -// This is the main function of antenna diversity after link. -// This function is called in HalDmWatchDog() and dm_SW_AntennaSwitchCallback(). -// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. -// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. -// After 500ms, dm_SW_AntennaSwitchCallback() calls this function to compare the signal just -// listened on the air with the RSSI of original antenna. -// It chooses the antenna with better RSSI. -// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting -// penalty to get next try. -// -void dm_SW_AntennaSwitch(struct rtl8192cd_priv *priv, char Step) -{ - unsigned int curTxOkCnt, curRxOkCnt; - unsigned int CurByteCnt, PreByteCnt; - int Score_R=0, Score_L=0; - int RSSI_R, RSSI_L; - char nextAntenna=priv->pshare->DM_SWAT_Table.CurAntenna; - int i; - -//1 1. Determine which condition should turn off Antenna Diversity - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) - return; -#endif - -// if(!(GET_CHIP_VER(priv) == VERSION_8188C) || !priv->pshare->rf_ft_var.antSw_enable) -// return; - - if((!priv->assoc_num) -#ifdef PCIE_POWER_SAVING - || (priv->pwr_state == L2) || (priv->pwr_state == L1) -#endif - ){ - SwAntDivRestAfterLink(priv); - return; - } - - // Handling step mismatch condition. - // Peak step is not finished at last time. Recover the variable and check again. - if( Step != priv->pshare->DM_SWAT_Table.try_flag) - { - SwAntDivRestAfterLink(priv); - } - -//1 2. Initialization: Select a assocaiated AP or STA as RSSI target - if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_RESET) { -#ifdef CLIENT_MODE - if((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) { - // Target: Infrastructure mode AP. - priv->pshare->RSSI_target = NULL; - } -#endif - resetSwAntDivVariable(priv); - priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_PEAK; - return; - } - else { - -//1 3. Antenna Diversity - - //2 Calculate TX and RX OK bytes - - curTxOkCnt = priv->net_stats.tx_bytes - priv->pshare->lastTxOkCnt; - curRxOkCnt = priv->net_stats.rx_bytes - priv->pshare->lastRxOkCnt; - priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; - priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; - - //2 Try State - if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_DETERMINE) { - //3 1. Seperately caculate TX and RX OK byte counter for ant A and B - if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { - priv->pshare->TXByteCnt_R += curTxOkCnt; - priv->pshare->RXByteCnt_R += curRxOkCnt; - } else { - priv->pshare->TXByteCnt_L += curTxOkCnt; - priv->pshare->RXByteCnt_L += curRxOkCnt; - } - - //3 2. Change anntena for testing - if(priv->pshare->DM_SWAT_Table.RSSI_Trying != 0) { - nextAntenna = (priv->pshare->DM_SWAT_Table.CurAntenna ) ^ Antenna_MAX; - priv->pshare->DM_SWAT_Table.RSSI_Trying--; - } - - //2 Try State End: Determine the best antenna - - if(priv->pshare->DM_SWAT_Table.RSSI_Trying==0) { - nextAntenna = priv->pshare->DM_SWAT_Table.CurAntenna; - priv->pshare->DM_SWAT_Table.mapIndex = (priv->pshare->DM_SWAT_Table.mapIndex+1)%SELANT_MAP_SIZE; - - //3 TP Mode: Determine the best antenna by throuhgput - if(priv->pshare->DM_SWAT_Table.TestMode == TP_MODE) { - - - - //3 (1) Saperately caculate total byte count for two antennas - if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { - CurByteCnt = (priv->pshare->TXByteCnt_R + (priv->pshare->RXByteCnt_R<<1)); - PreByteCnt = (priv->pshare->TXByteCnt_L + (priv->pshare->RXByteCnt_L<<1)); - } else { - CurByteCnt = (priv->pshare->TXByteCnt_L + (priv->pshare->RXByteCnt_L<<1)); - PreByteCnt = (priv->pshare->TXByteCnt_R + (priv->pshare->RXByteCnt_R<<1)); - } - - //3 (2) Throughput Normalization - if(priv->pshare->TrafficLoad == TRAFFIC_HIGH) - CurByteCnt >>=3; - else if(priv->pshare->TrafficLoad == TRAFFIC_LOW) - CurByteCnt >>=1; - - if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { - priv->pshare->DM_SWAT_Table.SelectAntennaMap[0][priv->pshare->DM_SWAT_Table.mapIndex] = PreByteCnt; - priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][priv->pshare->DM_SWAT_Table.mapIndex] = CurByteCnt; - } else { - priv->pshare->DM_SWAT_Table.SelectAntennaMap[0][priv->pshare->DM_SWAT_Table.mapIndex] = CurByteCnt; - priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][priv->pshare->DM_SWAT_Table.mapIndex] = PreByteCnt; - } - - Score_R = Score_L=0; - for (i= 0; ipshare->DM_SWAT_Table.SelectAntennaMap[0][i]; - Score_R += priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][i]; - } - - nextAntenna = (Score_L > Score_R) ? Antenna_L : Antenna_R; - - if(priv->pshare->rf_ft_var.ant_dump&8) - panic_printk("Mode TP, select Ant%d, [Score1=%d,Score2=%d]\n", nextAntenna, Score_L, Score_R); - - } - - //3 RSSI Mode: Determine the best anntena by RSSI - else if(priv->pshare->DM_SWAT_Table.TestMode == RSSI_MODE) { - - //2 Saperately caculate average RSSI for two antennas - RSSI_L = RSSI_R = 0; - - if(priv->pshare->RSSI_cnt_R > 0) - RSSI_R = priv->pshare->RSSI_sum_R/priv->pshare->RSSI_cnt_R; - if(priv->pshare->RSSI_cnt_L > 0) - RSSI_L = priv->pshare->RSSI_sum_L/priv->pshare->RSSI_cnt_L; - - if(RSSI_L && RSSI_R ) - nextAntenna = (RSSI_L > RSSI_R) ? Antenna_L : Antenna_R; - - if(priv->pshare->rf_ft_var.ant_dump&8) - panic_printk("Mode RSSI, RSSI_R=%d(%d), RSSI_L=%d(%d), Ant=%d\n", - RSSI_R, priv->pshare->RSSI_cnt_R, RSSI_L, priv->pshare->RSSI_cnt_L, nextAntenna); - - } - - //3 Reset state - resetSwAntDivVariable(priv); - priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_PEAK; - priv->pshare->RSSI_test = FALSE; - } - } - - //1 Normal State - else if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_PEAK) { - - //3 Determine TP/RSSI mode by TRX OK count - if((curRxOkCnt+curTxOkCnt) > TP_MODE_THD) { - //2 Determine current traffic is high or low - if((curTxOkCnt+curRxOkCnt) > TRAFFIC_THRESHOLD) - priv->pshare->TrafficLoad = TRAFFIC_HIGH; - else - priv->pshare->TrafficLoad = TRAFFIC_LOW; - - priv->pshare->DM_SWAT_Table.RSSI_Trying = 10; - priv->pshare->DM_SWAT_Table.TestMode = TP_MODE; - } else { - - int idx = 0; - struct stat_info* pEntry = findNextSTA(priv, &idx); - priv->pshare->RSSI_target = NULL; - while(pEntry) { - if(pEntry && pEntry->expire_to) { - if(!priv->pshare->RSSI_target) - priv->pshare->RSSI_target = pEntry; - else if( pEntry->rssi < priv->pshare->RSSI_target->rssi ) - priv->pshare->RSSI_target = pEntry; - } - pEntry = findNextSTA(priv, &idx); - }; - - priv->pshare->DM_SWAT_Table.RSSI_Trying = 6; - priv->pshare->DM_SWAT_Table.TestMode = RSSI_MODE; - - if(priv->pshare->RSSI_target == NULL) { - SwAntDivRestAfterLink(priv); - return; - } - - //3 reset state - memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); - } - - //3 Begin to enter Try State - nextAntenna = (priv->pshare->DM_SWAT_Table.CurAntenna ) ^ Antenna_MAX; - priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_DETERMINE; - priv->pshare->RSSI_test = TRUE; - - //3 Reset variables - resetSwAntDivVariable(priv); - } - } - -//1 4.Change TRX antenna - if(nextAntenna != priv->pshare->DM_SWAT_Table.CurAntenna) { -#if defined(CONFIG_PCI_HCI) -#ifdef GPIO_ANT_SWITCH - PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, nextAntenna); -#else - if (!priv->pshare->rf_ft_var.antSw_select) - PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); - else - PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, nextAntenna); -#endif - -//1 5.Reset Statistics - priv->pshare->DM_SWAT_Table.CurAntenna = nextAntenna; -#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - notify_antenna_switch(priv, nextAntenna); -#endif - } - -//1 6.Set next timer - - if(priv->pshare->DM_SWAT_Table.RSSI_Trying == 0) { - return; - } - - if(priv->pshare->DM_SWAT_Table.TestMode == RSSI_MODE) { - mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(400)); // 400 ms - } else if(priv->pshare->DM_SWAT_Table.TestMode == TP_MODE) { - - if(priv->pshare->TrafficLoad == TRAFFIC_HIGH) { - if(priv->pshare->DM_SWAT_Table.RSSI_Trying%2 == 0) - mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(10)); // 10 ms - else - mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(80)); // 80 ms - - } else if(priv->pshare->TrafficLoad == TRAFFIC_LOW) { - if(priv->pshare->DM_SWAT_Table.RSSI_Trying%2 == 0) - mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(40)); // 40 ms - else - mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(80)); // 80 ms - } - } - -} - - -void dm_SW_AntennaSwitchCallback(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv*)task_priv; -#ifndef SMP_SYNC - unsigned long flags = 0; -#endif - if (!(priv->drv_state & DRV_STATE_OPEN)) - return; - - SAVE_INT_AND_CLI(flags); - dm_SW_AntennaSwitch(priv, SWAW_STEP_DETERMINE); - RESTORE_INT(flags); -} - -// -// 20100514 Luke/Joseph: -// This function is used to gather the RSSI information for antenna testing. -// It selects the RSSI of the peer STA that we want to know. -// -void dm_SWAW_RSSI_Check(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo) -{ - struct stat_info* pEntry = NULL; - pEntry = get_stainfo(priv, GetAddr2Ptr(get_pframe(pfrinfo))); - - if((priv->pshare->RSSI_target==NULL)||(priv->pshare->RSSI_target==pEntry)) { - //1 RSSI for SW Antenna Switch - if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) - { - priv->pshare->RSSI_sum_R += pfrinfo->rssi; - priv->pshare->RSSI_cnt_R++; - } else { - priv->pshare->RSSI_sum_L += pfrinfo->rssi; - priv->pshare->RSSI_cnt_L++; - } - } -} - -#ifndef HW_ANT_SWITCH - -int diversity_antenna_select(struct rtl8192cd_priv *priv, unsigned char *data) -{ - int ant = _atoi(data, 16); -// if(GET_CHIP_VER(priv) != VERSION_8188C) -// return 0; - -#ifdef PCIE_POWER_SAVING - PCIeWakeUp(priv, POWER_DOWN_T0); -#endif - if(ant==Antenna_L || ant==Antenna_R) { -#ifdef GPIO_ANT_SWITCH - PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, ant); -#else - if (!priv->pshare->rf_ft_var.antSw_select) - PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, ant); - else - PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, ant); -#endif - priv->pshare->DM_SWAT_Table.CurAntenna = ant; - priv->pshare->rf_ft_var.antSw_enable = 0; - SwAntDivRestAfterLink(priv); - memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); - return 1; - } else { - priv->pshare->rf_ft_var.antSw_enable = 1; - priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; - priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; - - return 0; - } -} -#endif -#endif -#if defined(HW_ANT_SWITCH) - -void dm_HW_AntennaSwitchInit(struct rtl8192cd_priv *priv) -{ - if(!priv->pshare->rf_ft_var.antHw_enable) - return; -#ifdef SW_ANT_SWITCH - priv->pshare->rf_ft_var.antSw_enable =0; -#endif - -// if (GET_CHIP_VER(priv) == VERSION_8188C) - if(get_rf_mimo_mode(priv)== MIMO_1T1R) - priv->pshare->rf_ft_var.antSw_select = 0; - - if ( !priv->pshare->rf_ft_var.antSw_select) { - RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) | BIT(13) ); //select ANTESEL from path A - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(8)| BIT(9)) ); // ANTSEL as HW control - RTL_W32(rFPGA0_XA_RFInterfaceOE, (RTL_R32(rFPGA0_XA_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna - RTL_W8(0xc50, RTL_R8(0xc50) | BIT(7)); // Enable Hardware antenna switch - RTL_W32(0xc54, RTL_R32(0xc54) | BIT(23) ); // Decide final antenna by comparing 2 antennas' pwdb - } else { - RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) & ~ BIT(13) ); //select ANTESEL from path B - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(24)| BIT(25)) ); // ANTSEL as HW control - RTL_W32(rFPGA0_XB_RFInterfaceOE, (RTL_R32(rFPGA0_XB_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, RTL_R8(0xc58) | BIT(7)); // Enable Hardware antenna switch -#endif - RTL_W32(0xc5C, RTL_R32(0xc5c) | BIT(23) ); // Decide final antenna by comparing 2 antennas' pwdb - } - - priv->pshare->rf_ft_var.CurAntenna = 0; - - RTL_W32(LEDCFG, RTL_R32(LEDCFG) | BIT(23) ); //enable LED[1:0] pin as ANTSEL - RTL_W16(0xca4, (RTL_R16(0xca4) & ~(0xfff))|0x0c0); // Pwdb threshold=12dB - RTL_W32(0x874, RTL_R32(0x874) & ~ BIT(23) ); // No update ANTSEL during GNT_BT=1 - RTL_W16(rFPGA0_TxInfo, (RTL_R16(rFPGA0_TxInfo)&0xf0ff) | BIT(8) ); // b11-b8=0001 - RTL_W32(0x80c, RTL_R32(0x80c) | BIT(21) ); // assign antenna by tx desc - - // CCK setting - RTL_W8(0xa01, RTL_R8(0xa01) | BIT(7)); // enable hw ant diversity - RTL_W8(0xa0c, (RTL_R8(0xa0c) & 0xe0) | 0x0f ); // b4=0, b3:0 = 1111 32 sample - RTL_W8(0xa11, RTL_R8(0xa11) | BIT(5)); // do not change default optional antenna - RTL_W8(0xa14, (RTL_R8(0xa14) & 0xe0) | 0x08 ); // default : optional = 1:1 -#ifdef GPIO_ANT_SWITCH - PHY_SetBBReg(priv, rFPGA0_XCD_RFParameter, 0x40000000, 0x01); // enable ANTSEL -#endif - -} - -void setRxIdleAnt(struct rtl8192cd_priv *priv, char Ant) -{ - if(priv->pshare->rf_ft_var.CurAntenna != Ant) { - if(Ant) { - RTL_W32(0x858, 0x65a965a9); -// RTL_W8(0x6d8, RTL_R8(0x6d8) | BIT(6) ); - } - else { - RTL_W32(0x858, 0x569a569a); -// RTL_W8(0x6d8, RTL_R8(0x6d8) & (~ BIT(6))); - } - priv->pshare->rf_ft_var.CurAntenna = Ant; - } -} - -void dm_STA_Ant_Select(struct rtl8192cd_priv *priv, struct stat_info *pstat) -{ - int ScoreA=0, ScoreB=0, i, nextAnt= pstat->CurAntenna, idleAnt=priv->pshare->rf_ft_var.CurAntenna; - - if((priv->pshare->rf_ft_var.CurAntenna & 0x80) - || ((pstat->hwRxAntSel[0] + pstat->hwRxAntSel[1])==0 && (pstat->cckPktCount[0] + pstat->cckPktCount[1])<10) ) - return; - - for(i=0; i<2; i++) { - if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0) - pstat->AntRSSI[i] = 0; - } - - if(pstat->hwRxAntSel[0] || pstat->hwRxAntSel[1]) { - ScoreA = pstat->hwRxAntSel[0]; - ScoreB = pstat->hwRxAntSel[1]; - - if(ScoreA != ScoreB) { - if(ScoreA > ScoreB) - nextAnt = 0; - else - nextAnt = 1; - } - } else { - ScoreA = pstat->cckPktCount[0]; - ScoreB = pstat->cckPktCount[1]; - - if(ScoreA > 5*ScoreB) - nextAnt = 0; - else if(ScoreB > 5*ScoreA) - nextAnt = 1; - else if(ScoreA > ScoreB) - nextAnt = 1; - else if(ScoreB > ScoreA) - nextAnt = 0; - } - - pstat->CurAntenna = nextAnt; - - if(priv->pshare->rf_ft_var.ant_dump&2) { - panic_printk("id=%d, OFDM/CCK: (%d, %d/%d, %d), RSSI:(%d, %d), ant=%d, RxIdle=%d\n", - pstat->aid, - pstat->hwRxAntSel[1], - pstat->hwRxAntSel[0], - pstat->cckPktCount[1], - pstat->cckPktCount[0], - pstat->AntRSSI[1], - pstat->AntRSSI[0], - (pstat->CurAntenna==0 ? 2: 1) - ,((priv->pshare->rf_ft_var.CurAntenna&1)==0 ? 2 : 1) - ); - } - - if(pstat->AntRSSI[idleAnt]==0) - pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1]; - -// reset variables - pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0; - pstat->cckPktCount[1]= pstat->cckPktCount[0] =0; - -} - -void dm_HW_IdleAntennaSelect(struct rtl8192cd_priv *priv) -{ - struct stat_info *pstat, *pstat_min=NULL; - struct list_head *phead, *plist; - int rssi_min= 0xff, i; -#ifdef SMP_SYNC - unsigned long flags = 0; -#endif - - if(priv->pshare->rf_ft_var.CurAntenna & 0x80) - return; - - phead = &priv->asoc_list; - - SMP_LOCK_ASOC_LIST(flags); - - plist = phead->next; - while(plist != phead) { - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - - if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) { - int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1]; - if((!pstat_min) || ( rssi < rssi_min) ) { - pstat_min = pstat; - rssi_min = rssi; - } - } - }; - - SMP_UNLOCK_ASOC_LIST(flags); - - if(pstat_min) - setRxIdleAnt(priv, pstat_min->CurAntenna); - - -#ifdef TX_SHORTCUT - if (!priv->pmib->dot11OperationEntry.disable_txsc) { - SMP_LOCK_ASOC_LIST(flags); - - plist = phead->next; - while(plist != phead) { - pstat = list_entry(plist, struct stat_info, asoc_list); - plist = plist->next; - - if(pstat->expire_to) { - for (i=0; itx_sc_ent[i].hwdesc1); - pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); - if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) - pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); - #ifdef CONFIG_PCI_HCI - pdesc= &(pstat->tx_sc_ent[i].hwdesc2); - pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); - if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) - pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); - #endif - } - } - }; - - SMP_UNLOCK_ASOC_LIST(flags); - } -#endif - -} - -int diversity_antenna_select(struct rtl8192cd_priv *priv, unsigned char *data) -{ - int ant = _atoi(data, 16); - -#ifdef PCIE_POWER_SAVING - PCIeWakeUp(priv, POWER_DOWN_T0); -#endif - - if (ant==Antenna_L || ant==Antenna_R) { - -#ifdef GPIO_ANT_SWITCH - if(priv->pshare->rf_ft_var.antSw_enable) { - PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, ant); - } else -#endif - { - if ( !priv->pshare->rf_ft_var.antSw_select) { - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(8)| BIT(9) ); // ANTSEL A as SW control - RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control - PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, ant); - } else { - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(24)| BIT(25) ); // ANTSEL B as HW control - PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, ant); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, RTL_R8(0xc58) & (~ BIT(7))); // rx OFDM SW control -#endif - } - RTL_W8(0xa01, RTL_R8(0xa01) & (~ BIT(7))); // rx CCK SW control - RTL_W32(0x80c, RTL_R32(0x80c) & (~ BIT(21))); // select ant by tx desc - RTL_W32(0x858, 0x569a569a); - } - if(HW_DIV_ENABLE) - priv->pshare->rf_ft_var.antHw_enable = BIT(5); - priv->pshare->rf_ft_var.CurAntenna = (ant%2); -#ifdef SW_ANT_SWITCH - if(priv->pshare->rf_ft_var.antSw_enable) - priv->pshare->rf_ft_var.antSw_enable = BIT(5); - priv->pshare->DM_SWAT_Table.CurAntenna = ant; - priv->pshare->RSSI_test =0; -#endif - } - else if(ant==0){ -#ifdef GPIO_ANT_SWITCH - if(priv->pshare->rf_ft_var.antHw_enable) -#endif - { - if (!priv->pshare->rf_ft_var.antSw_select) { - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(8)| BIT(9)) ); - RTL_W8(0xc50, RTL_R8(0xc50) | BIT(7)); // OFDM HW control - } else { - RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(24)| BIT(25)) ); -#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) - if ( -#ifdef CONFIG_RTL_92C_SUPPORT - (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) -#endif -#ifdef CONFIG_RTL_92D_SUPPORT -#ifdef CONFIG_RTL_92C_SUPPORT - || -#endif - (GET_CHIP_VER(priv)==VERSION_8192D) -#endif - ) - RTL_W8(0xc58, RTL_R8(0xc58) | BIT(7)); // OFDM HW control -#endif - } - RTL_W8(0xa01, RTL_R8(0xa01) | BIT(7)); // CCK HW control - RTL_W32(0x80c, RTL_R32(0x80c) | BIT(21) ); // by tx desc - priv->pshare->rf_ft_var.CurAntenna = 0; - RTL_W32(0x858, 0x569a569a); - priv->pshare->rf_ft_var.antHw_enable = 1; -#ifdef SW_ANT_SWITCH - priv->pshare->rf_ft_var.antSw_enable = 0; - priv->pshare->RSSI_test =0; -#endif - } -#ifdef SW_ANT_SWITCH - if(priv->pshare->rf_ft_var.antSw_enable) { - dm_SW_AntennaSwitchInit(priv); - RTL_W32(0x858, 0x569a569a); - priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; - priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; - priv->pshare->rf_ft_var.antHw_enable = 0; - priv->pshare->rf_ft_var.antSw_enable = 1; - } -#endif - - } -#if defined(SW_ANT_SWITCH) && !defined(GPIO_ANT_SWITCH) - else if(ant==3) { - if(!priv->pshare->rf_ft_var.antSw_enable) { - dm_SW_AntennaSwitchInit(priv); - RTL_W32(0x858, 0x569a569a); - priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; - priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; - } -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv)==VERSION_8188E) { - RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control - } else -#endif - { - if ( !priv->pshare->rf_ft_var.antSw_select) - RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control - else - RTL_W8(0xc58, RTL_R8(0xc58) & (~ BIT(7))); // rx OFDM SW control - } - - RTL_W8(0xa01, RTL_R8(0xa01) & (~ BIT(7))); // rx CCK SW control - RTL_W32(0x80c, RTL_R32(0x80c) & (~ BIT(21))); // select ant by tx desc - priv->pshare->rf_ft_var.antHw_enable = 0; - priv->pshare->rf_ft_var.antSw_enable = 1; - - } -#endif - - return 1; -} - -#endif - -//3 ============================================================ -//3 Dynamic Noise Control -//3 ============================================================ - -#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) -void dnc_timer(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - struct stat_info *pstat = NULL; - unsigned int set_timer = 0; - unsigned long flags; - - if (!(priv->drv_state & DRV_STATE_OPEN)) - return; - - if (timer_pending(&priv->dnc_timer)) - del_timer_sync(&priv->dnc_timer); - -#ifdef PCIE_POWER_SAVING - if ((priv->pwr_state == L2) || (priv->pwr_state == L1)) - return; -#endif - - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07600760); - PHY_SetBBReg(priv, 0xc50, bMaskByte0, 0x20); - PHY_SetBBReg(priv, 0xc58, bMaskByte0, 0x20); - } -} -#endif - - -//3 ============================================================ -//3 Leaving STA check -//3 ============================================================ -#if 0 -//#if defined(DETECT_STA_EXISTANCE) //&& (defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT)) -// Check for STA existance. If STA disappears, disconnect it. Added by Annie, 2010-08-10. -void DetectSTAExistance(struct rtl8192cd_priv *priv, struct tx_rpt *report, struct stat_info *pstat) -{ - unsigned char tmpbuf[16]; - - // Parameters - const unsigned int maxTxFailCnt = 300; // MAX Tx fail packet count - const unsigned int minTxFailCnt = 30; // MIN Tx fail packet count; this value should be less than maxTxFailCnt. - const unsigned int txFailSecThr= 3; // threshold of Tx Fail Time (in second) - - // Temporarily change Retry Limit when TxFail. (tfrl: TxFailRetryLimit) - const unsigned char TFRL = 7; // New Retry Limit value - const unsigned char TFRL_FailCnt = 2; // Tx Fail Count threshold to set Retry Limit - const unsigned char TFRL_SetTime = 2; // Time to set Retry Limit (in second) - const unsigned char TFRL_RcvTime = 10; // Time to recover Retry Limit (in second) - - if(OPMODE & WIFI_STATION_STATE) - return; - - if( report->txok != 0 ) - { // Reset Counter - pstat->tx_conti_fail_cnt = 0; - pstat->tx_last_good_time = priv->up_time; - pstat->leave = 0; - } - else if( report->txfail != 0 ) - { - pstat->tx_conti_fail_cnt += report->txfail; - DEBUG_WARN( "detect: txfail=%d, tx_conti_fail_cnt=%d\n", report->txfail, pstat->tx_conti_fail_cnt ); - - if( CHIP_VER_92X_SERIES(priv) && (priv->up_time >= (pstat->tx_last_good_time+TFRL_SetTime)) && - pstat->tx_conti_fail_cnt >= TFRL_FailCnt && - #if defined(CONFIG_RTL8672) || defined (NOT_RTK_BSP) - !pstat->ht_cap_len && // legacy rate only - #endif - !priv->pshare->bRLShortened ) - { // Shorten retry limit, because AP spending too much time to send out g mode STA pending packets in HW queue. - RTL_W16(RL, (TFRL&SRL_Mask)<pshare->bRLShortened = TRUE; - DEBUG_WARN( "== Shorten RetryLimit to 0x%04X ==\n", RTL_R16(RL) ); - } - - if( (pstat->tx_conti_fail_cnt >= maxTxFailCnt) || - (pstat->tx_conti_fail_cnt >= minTxFailCnt && priv->up_time >= (pstat->tx_last_good_time+txFailSecThr) ) - ) - { // This STA is considered as disappeared, so delete it. - DEBUG_WARN( "** tx_conti_fail_cnt=%d (min=%d,max=%d)\n", pstat->tx_conti_fail_cnt, minTxFailCnt, maxTxFailCnt); - DEBUG_WARN( "** tx_last_good_time=%d, up_time=%d (Thr:%d)\n", (int)pstat->tx_last_good_time, (int)priv->up_time, txFailSecThr ); - DEBUG_WARN( "AP is going to del_sta %02X:%02X:%02X:%02X:%02X:%02X\n", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5] ); - - sprintf((char *)tmpbuf, "%02x%02x%02x%02x%02x%02x", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); - -// del_sta(priv, tmpbuf); - ++(pstat->leave); - - if(CHIP_VER_92X_SERIES(priv) { - if (timer_pending(&priv->pshare->rl_recover_timer)) - del_timer_sync (&priv->pshare->rl_recover_timer); - mod_timer(&priv->pshare->rl_recover_timer, jiffies + EXPIRE_TO*TFRL_RcvTime); - } - - // Reset Counter - pstat->tx_conti_fail_cnt = 0; - pstat->tx_last_good_time = priv->up_time; - } - } -} - -// Timer callback function to recover hardware retry limit register. Added by Annie, 2010-08-10. -#if defined(__KERNEL__) || defined(__OSK__) -void RetryLimitRecovery(unsigned long task_priv) -#elif defined(__ECOS) -void RetryLimitRecovery(void *task_priv) -#endif -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - if( priv->pshare->bRLShortened ) - { - RTL_W16(RL, priv->pshare->RL_setting); - priv->pshare->bRLShortened = FALSE; - DEBUG_WARN( "== Recover RetryLimit to 0x%04X ==\n", RTL_R16(RL) ); - } -} - -// Chack STA leaving status; per interface. Added by Annie, 2010-08-10. -unsigned char NoLeavingSTA(struct rtl8192cd_priv *priv) -{ - unsigned char bStaAllOK = TRUE; - struct list_head *phead, *plist; - struct stat_info *pstat; - - phead = &priv->asoc_list; - if (!netif_running(priv->dev) || list_empty(phead)) - return bStaAllOK; - - plist = phead->next; - while (plist != phead) { - pstat = list_entry(plist, struct stat_info, asoc_list); - if( pstat->tx_conti_fail_cnt != 0 ) { - bStaAllOK = FALSE; - break; - } - plist = plist->next; - } - - return bStaAllOK; -} - -// Chack STA leaving status for all active interface and recover retry limit register value. Added by Annie, 2010-08-10. -void LeavingSTA_RLCheck(struct rtl8192cd_priv *priv) -{ - unsigned char bIfAllOK = TRUE; - static int AllOKTimes = 0; -#ifdef MBSSID - int i; -#endif - // Parameter - const unsigned char TFRL_RcvTime = 10; // Time to recover Retry Limit (in second) - - if( !NoLeavingSTA(priv) ) - bIfAllOK = FALSE; - -#ifdef UNIVERSAL_REPEATER - if (IS_ROOT_INTERFACE(priv) && GET_VXD_PRIV(priv) ) { - if( !NoLeavingSTA(GET_VXD_PRIV(priv)) ) - bIfAllOK = FALSE; - } -#endif - -#ifdef MBSSID - if (IS_ROOT_INTERFACE(priv)) { - if (GET_ROOT(priv)->pmib->miscEntry.vap_enable) { - for (i=0; ipvap_priv[i])) { - if( !NoLeavingSTA(priv->pvap_priv[i]) ) - bIfAllOK = FALSE; - } - } - } - } -#endif - - if( bIfAllOK ) { - AllOKTimes ++; - - if( AllOKTimes >= TFRL_RcvTime ) -#if defined(__KERNEL__) || defined(__OSK__) - RetryLimitRecovery((unsigned long)priv); -#elif defined(__ECOS) - RetryLimitRecovery((void *)priv); -#endif - } - else { - AllOKTimes = 0; - } -} -#endif - - - -#ifdef CONFIG_RTL_92C_SUPPORT - -/* - * PA Analog Pre-distortion Calibration R06 - */ -void APK_MAIN(struct rtl8192cd_priv *priv, unsigned int is2T) -{ - unsigned int regD[PATH_NUM]; - unsigned int tmpReg, index, offset, path, i=0, pathbound = PATH_NUM, apkbound=6; - unsigned int BB_backup[APK_BB_REG_NUM]; - unsigned int BB_REG[APK_BB_REG_NUM] = {0x904, 0xc04, 0x800, 0xc08, 0x874}; - unsigned int BB_AP_MODE[APK_BB_REG_NUM] = {0x00000020, 0x00a05430, 0x02040000, 0x000800e4, 0x00204000}; - unsigned int BB_normal_AP_MODE[APK_BB_REG_NUM] = {0x00000020, 0x00a05430, 0x02040000, 0x000800e4, 0x22204000}; - unsigned int AFE_backup[APK_AFE_REG_NUM]; - unsigned int AFE_REG[APK_AFE_REG_NUM] = { 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; - unsigned int MAC_backup[IQK_MAC_REG_NUM]; - unsigned int MAC_REG[IQK_MAC_REG_NUM] = {0x522, 0x550, 0x551, 0x040}; - unsigned int APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}}; - unsigned int APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = - { {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} }; - - unsigned int APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = - { {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}}; - - unsigned int APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = - { {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} }; - - unsigned int AFE_on_off[PATH_NUM] = {0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - unsigned int APK_offset[PATH_NUM] = {0xb68, 0xb6c}; - unsigned int APK_normal_offset[PATH_NUM] = {0xb28, 0xb98}; - unsigned int APK_value[PATH_NUM] = {0x92fc0000, 0x12fc0000}; - unsigned int APK_normal_value[PATH_NUM] = {0x92680000, 0x12680000}; - char APK_delta_mapping[APK_BB_REG_NUM][13] = {{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}}; - unsigned int APK_normal_setting_value_1[13] = - { 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 }; - unsigned int APK_normal_setting_value_2[16] = - { 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 }; - - - unsigned int APK_normal_RF_init_value_old[PATH_NUM][APK_BB_REG_NUM] = - {{0x0852c, 0x5a52c, 0x0a52c, 0x5a52c, 0x4a52c}, //path settings equal to path b settings - {0x0852c, 0x5a52c, 0x0a52c, 0x5a52c, 0x4a52c}}; - unsigned int APK_normal_RF_value_0_old[PATH_NUM][APK_BB_REG_NUM] = - {{0x52019, 0x52017, 0x52010, 0x5200d, 0x5200a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5200a}}; - unsigned int APK_normal_setting_value_1_old[13] = - {0x01017018, 0xf7ed8f84, 0x40372d20, 0x5b554e48, 0x6f6a6560, - 0x807c7873, 0x8f8b8884, 0x9d999693, 0xa9a6a3a0, 0xb5b2afac, - 0x12680000, 0x00880000, 0x00880000}; - unsigned int APK_normal_setting_value_2_old[16] = - {0x00810100, 0x00400056, 0x002b0032, 0x001f0024, 0x0019001c, - 0x00150017, 0x00120013, 0x00100011, 0x000e000f, 0x000c000d, - 0x000b000c, 0x000a000b, 0x0009000a, 0x00090009, 0x00080008, - 0x00080008}; - unsigned int AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - unsigned int APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a - unsigned int ThermalValue = 0; - int BB_offset, delta_V, delta_offset; - int newVerAPK = (IS_UMC_A_CUT_88C(priv)) ? 1 : 0; - unsigned int *pAPK_normal_setting_value_1 = APK_normal_setting_value_1, *pAPK_normal_setting_value_2 = APK_normal_setting_value_2 ; -#ifdef HIGH_POWER_EXT_PA - unsigned int tmp0x870=0, tmp0x860=0, tmp0x864=0; - - if(priv->pshare->rf_ft_var.use_ext_pa) - newVerAPK = 1; -#endif - - if(!newVerAPK) { - apkbound = 12; - pAPK_normal_setting_value_1 = APK_normal_setting_value_1_old; - pAPK_normal_setting_value_2 = APK_normal_setting_value_2_old; - } - - if(!is2T) - pathbound = 1; - - for(index = 0; index < PATH_NUM; index ++) { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) { - for(path = 0; path < pathbound; path++) { - if(newVerAPK) { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } else { - APK_RF_init_value[path][index] = APK_normal_RF_init_value_old[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0_old[path][index]; - } - - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - /* - * save BB default value - */ - for(index = 1; index < APK_BB_REG_NUM ; index++) - BB_backup[index] = PHY_QueryBBReg(priv, BB_REG[index], bMaskDWord); - -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) { - tmp0x870 = PHY_QueryBBReg(priv, 0x870, bMaskDWord); - tmp0x860 = PHY_QueryBBReg(priv, 0x860, bMaskDWord); - tmp0x864 = PHY_QueryBBReg(priv, 0x864, bMaskDWord); - } -#endif - - //save MAC default value - _PHY_SaveMACRegisters(priv, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(priv, AFE_REG, AFE_backup, APK_AFE_REG_NUM); - - for(path = 0; path < pathbound; path++) { - /* - * save old AP curve - */ - if(path == RF92CD_PATH_A) { - /* - * path A APK - * load APK setting - * path-A - */ - offset = 0xb00; - for(index = 0; index < 11; index ++) { - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); - offset += 0x04; - } - PHY_SetBBReg(priv, 0xb98, bMaskDWord, 0x12680000); - - offset = 0xb68; - for(; index < 13; index ++) { - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); - offset += 0x04; - } - - /* - * page-B1 - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); - - /* - *path A - */ - offset = 0xb00; - for(index = 0; index < 16; index++) { - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_2[index]); - offset += 0x04; - } - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - } else if(path == RF92CD_PATH_B) { - /* - * path B APK - * load APK setting - * path-B - */ - offset = 0xb70; - for(index = 0; index < 10; index ++) { - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); - offset += 0x04; - } - PHY_SetBBReg(priv, 0xb28, bMaskDWord, 0x12680000); - PHY_SetBBReg(priv, 0xb98, bMaskDWord, 0x12680000); - - offset = 0xb68; - index = 11; - for(; index < 13; index ++) { - //offset 0xb68, 0xb6c - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); - offset += 0x04; - } - - /* - * page-B1 - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); - - /* - * path B - */ - offset = 0xb60; - for(index = 0; index < 16; index++) { - PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_2[index]); - offset += 0x04; - } - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - } - - if(!newVerAPK) { - tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x3, bMaskDWord, 1); - - AP_curve[path][0] = tmpReg & 0x1F; //[4:0] - - tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, 1); - AP_curve[path][1] = (tmpReg & 0xF8000) >> 15; //[19:15] - AP_curve[path][2] = (tmpReg & 0x7C00) >> 10; //[14:10] - AP_curve[path][3] = (tmpReg & 0x3E0) >> 5; //[9:5] - } - - /* - * save RF default value - */ - regD[path] = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, 1); - - /* - * Path A AFE all on, path B AFE All off or vise versa - */ - for(index = 0; index < APK_AFE_REG_NUM ; index++) - PHY_SetBBReg(priv, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - - /* - * BB to AP mode - */ - if(path == RF92CD_PATH_A) { - for(index = 1; index < APK_BB_REG_NUM ; index++) - PHY_SetBBReg(priv, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - } - -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) { - PHY_SetBBReg(priv, 0x870, BIT(10), 1); - PHY_SetBBReg(priv, 0x870, BIT(26), 1); - PHY_SetBBReg(priv, 0x860, BIT(10), 0); - PHY_SetBBReg(priv, 0x864, BIT(10), 0); - } -#endif - - if(newVerAPK) { - if(path == RF92CD_PATH_A) { - PHY_SetBBReg(priv, 0xe30 , bMaskDWord, 0x01008c00); - PHY_SetBBReg(priv, 0xe34 , bMaskDWord, 0x01008c00); - } else if(path == RF92CD_PATH_B) { - PHY_SetBBReg(priv, 0xe50 , bMaskDWord, 0x01008c00); - PHY_SetBBReg(priv, 0xe54 , bMaskDWord, 0x01008c00); - } - } - - //MAC settings - _PHY_MACSettingCalibration(priv, MAC_REG, MAC_backup); - - - if(path == RF92CD_PATH_A) { - //Path B to standby mode - PHY_SetRFReg(priv, RF92CD_PATH_B, 0x0, bMaskDWord, 0x10000); - } else { - //Path A to standby mode - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMaskDWord, 0x10000); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x10, bMaskDWord, 0x1000f); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x11, bMaskDWord, 0x20103); - } - - /* - * Check Thermal value delta - */ - if (priv->pmib->dot11RFEntry.ther) { - ThermalValue = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x24, 0x1f, 1) & 0xff; - ThermalValue -= priv->pmib->dot11RFEntry.ther; - } - - delta_offset = ((ThermalValue+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 1; index < APK_BB_REG_NUM; index++) { - tmpReg = APK_RF_init_value[path][index]; - if (priv->pmib->dot11RFEntry.ther) { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT(15))) //sign bit 0 - BB_offset = -BB_offset; - delta_V = APK_delta_mapping[index][delta_offset]; - BB_offset += delta_V; - - if(BB_offset < 0) { - tmpReg = tmpReg & (~BIT(15)); - BB_offset = -BB_offset; - } else { - tmpReg = tmpReg | BIT(15); - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } - - if(newVerAPK) - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xc, bMaskDWord, 0x8992e); - else - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xc, bMaskDWord, 0x8992f); - - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x0, bMaskDWord, APK_RF_value_0[path][index]); - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, tmpReg); - - /* - * PA11+PAD01111, one shot - */ - i = 0; - do { - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x800000); - PHY_SetBBReg(priv, APK_offset[path], bMaskDWord, APK_value[0]); - delay_ms(3); - PHY_SetBBReg(priv, APK_offset[path], bMaskDWord, APK_value[1]); - delay_ms(20); - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - - if(!newVerAPK) { - tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xb, bMaskDWord, 1); - tmpReg = (tmpReg & 0x3E00) >> 9; - } else { - if(path == RF92CD_PATH_A) - tmpReg = PHY_QueryBBReg(priv, 0xbd8, 0x03E00000); - else - tmpReg = PHY_QueryBBReg(priv, 0xbd8, 0xF8000000); - } - i++; - } while((tmpReg > apkbound) && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - /* - * reload MAC default value - */ - _PHY_ReloadMACRegisters(priv, MAC_REG, MAC_backup); - - /* - * reload BB default value - */ - for(index = 1; index < APK_BB_REG_NUM ; index++) - PHY_SetBBReg(priv, BB_REG[index], bMaskDWord, BB_backup[index]); - -#ifdef HIGH_POWER_EXT_PA - if (priv->pshare->rf_ft_var.use_ext_pa) { - PHY_SetBBReg(priv, 0x870, bMaskDWord, tmp0x870); - PHY_SetBBReg(priv, 0x860, bMaskDWord, tmp0x860); - PHY_SetBBReg(priv, 0x864, bMaskDWord, tmp0x864); - } -#endif - - /* - * reload AFE default value - */ - _PHY_ReloadADDARegisters(priv, AFE_REG, AFE_backup, 16); - - - /* - * reload RF path default value - */ - for(path = 0; path < pathbound; path++) { - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if(path == RF92CD_PATH_B) { - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x10, bMaskDWord, 0x1000f); - PHY_SetRFReg(priv, RF92CD_PATH_A, 0x11, bMaskDWord, 0x20101); - } - - if(newVerAPK) { - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - } else { - if(APK_result[path][1] < 1) - APK_result[path][1] = 1; - else if (APK_result[path][1] > 5) - APK_result[path][1] = 5; - - if(APK_result[path][2] < 2) - APK_result[path][2] = 2; - else if (APK_result[path][2] > 6) - APK_result[path][2] = 6; - - if(APK_result[path][3] < 2) - APK_result[path][3] = 2; - else if (APK_result[path][3] > 6) - APK_result[path][3] = 6; - - if(APK_result[path][4] < 5) - APK_result[path][4] = 5; - else if (APK_result[path][4] > 9) - APK_result[path][4] = 9; - } - } - - for(path = 0; path < pathbound; path++) { - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(newVerAPK) { - if(path == RF92CD_PATH_A) - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xe, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); - } else { - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][2] << 5) | APK_result[path][3])); - PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xe, bMaskDWord, - ((APK_result[path][4] << 15) | (APK_result[path][4] << 10) | (APK_result[path][4] << 5) | APK_result[path][4])); - } - } -} - - - -/* -return FALSE => do IQK again -*/ -char _PHY_SimularityCompare(struct rtl8192cd_priv *priv, int result[][8], unsigned char c1, unsigned char c2) -{ - unsigned int i, j, diff, SimularityBitMap, bound = 0; - unsigned char final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - char bResult = TRUE, is2T = (GET_CHIP_VER(priv) == VERSION_8192C ? 1 : 0); - - bound = (is2T) ? 8 : 4; - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) { - if((i == 2 || i == 6) && !SimularityBitMap) { - if( result[c1][i]+ result[c1][i+1] == 0) - final_candidate[(i>>2)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i>>2)] = c1; - else - SimularityBitMap |= (1<>2); i++ ) { - if(final_candidate[i] != 0xFF) { - for( j = (i<<2); j < ((i+1)<<2)-2; j++) - result[3][j] = result[final_candidate[i]][j]; - bResult = FALSE; - } - } - return bResult; - } - else if (!(SimularityBitMap & 0x03)) { //path A TX OK - for(i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - return FALSE; - } - else if (!(SimularityBitMap & 0x0c)) { //path A RX OK - for(i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - return FALSE; - } - else if (!(SimularityBitMap & 0x30) && is2T) { //path B TX OK - for(i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - return FALSE; - } - else if (!(SimularityBitMap & 0xc0) && is2T) { //path B RX OK - for(i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - return FALSE; - } - else - return FALSE; - -} - - -//bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -unsigned char _PHY_PathA_IQK(struct rtl8192cd_priv *priv, char configPathB) -{ - unsigned int regEAC, regE94, regE9C, regEA4; - unsigned char result = 0x00; - - - // RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); -#if defined(HIGH_POWER_EXT_PA) && defined(CONFIG_RTL_92C_SUPPORT) - if (priv->pshare->rf_ft_var.use_ext_pa){ - - //path-A IQK setting - PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140102); - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x28160804); - - //path-B IQK setting - if(configPathB) { - PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c22); - PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c22); - PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140102); - PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x28160804); - } -}else -#endif -{ - //path-A IQK setting - PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x10008c1f); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x10008c1f); - PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140102); - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, ((configPathB |IS_UMC_B_CUT_88C(priv)) ? 0x28160202 : 0x28160502)); - - //path-B IQK setting - if(configPathB) { - PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x10008c22); - PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x10008c22); - PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140102); - PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x28160202); - } -} - - - - //LO calibration setting - PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x001028d1); - - //One shot, path A LOK & IQK - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); - - // delay x ms - delay_ms(IQK_DELAY_TIME); - - // Check failed - regEAC = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - regE94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); - regE9C= PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); - regEA4= PHY_QueryBBReg(priv, 0xea4, bMaskDWord); - - if(!(regEAC & BIT(28)) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - if(!(regEAC & BIT(27)) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else { -// RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); - } - - return result; -} - -//bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -unsigned char _PHY_PathB_IQK(struct rtl8192cd_priv *priv) -{ - unsigned int regEAC, regEB4, regEBC, regEC4, regECC; - unsigned char result = 0x00; -#if 0 - //path-B IQK setting - RTPRINT(FINIT, INIT_IQK, ("Path-B IQK setting!\n")); - PHY_SetBBReg(pAdapter, 0xe50, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, 0xe54, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, 0xe58, bMaskDWord, 0x82140102); - PHY_SetBBReg(pAdapter, 0xe5c, bMaskDWord, 0x28160202); - - //LO calibration setting - RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); - PHY_SetBBReg(pAdapter, 0xe4c, bMaskDWord, 0x001028d1); -#endif - //One shot, path B LOK & IQK -// RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000002); - PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000000); - - // delay x ms - delay_ms(IQK_DELAY_TIME); - - // Check failed - regEAC = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - regEB4 = PHY_QueryBBReg(priv, 0xeb4, bMaskDWord); - regEBC= PHY_QueryBBReg(priv, 0xebc, bMaskDWord); - regEC4= PHY_QueryBBReg(priv, 0xec4, bMaskDWord); - regECC= PHY_QueryBBReg(priv, 0xecc, bMaskDWord); - - if(!(regEAC & BIT(31)) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT(30)) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else { -// RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); - } - - return result; - -} - -void _PHY_PathAFillIQKMatrix(struct rtl8192cd_priv *priv, char bIQKOK, int result[][8], unsigned char final_candidate, char bTxOnly) -{ - int Oldval_0, X, TX0_A, reg; - int Y, TX0_C; - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) { - Oldval_0 = (PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - TX0_C = (Y * Oldval_0) >> 8; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - - if(bTxOnly) { -// RTPRINT(FINIT, INIT_IQK, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - PHY_SetBBReg(priv, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - PHY_SetBBReg(priv, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); - } -} - - -void _PHY_PathBFillIQKMatrix(struct rtl8192cd_priv *priv, char bIQKOK, int result[][8], unsigned char final_candidate, char bTxOnly) -{ - int Oldval_1, X, TX1_A, reg; - int Y, TX1_C; - - //RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - TX1_C = (Y * Oldval_1) >> 8; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - PHY_SetBBReg(priv, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - PHY_SetBBReg(priv, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -void _PHY_PathAStandBy_8192C(struct rtl8192cd_priv *priv) -{ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00010000); - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); -} - -void _PHY_IQCalibrate(struct rtl8192cd_priv *priv, int result[][8], unsigned char t, char is2T) -{ - unsigned int i; - unsigned char PathAOK, PathBOK; - unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = { 0x85c, 0xe6c, 0xe70, 0xe74, - 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, - 0xed8, 0xedc, 0xee0, 0xeec }; - unsigned int IQK_MAC_REG[IQK_MAC_REG_NUM] = {0x522, 0x550, 0x551, 0x040}; - - char isNormal = IS_TEST_CHIP(priv) ? 0 : 1; - unsigned int retryCount = 2; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif - - if(t==0) { - // Save ADDA parameters, turn Path A ADDA on - _PHY_SaveADDARegisters(priv, ADDA_REG, priv->pshare->ADDA_backup, APK_AFE_REG_NUM); - _PHY_SaveMACRegisters(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); - } - - _PHY_PathADDAOn(priv, ADDA_REG, TRUE, is2T); - - if(t==0) { - // Store 0xC04, 0xC08, 0x874 vale - priv->pshare->RegC04 = PHY_QueryBBReg(priv, 0xc04, bMaskDWord); - priv->pshare->RegC08 = PHY_QueryBBReg(priv, 0xc08, bMaskDWord); - priv->pshare->Reg874 = PHY_QueryBBReg(priv, 0x874, bMaskDWord); - } - - //MAC settings - _PHY_MACSettingCalibration(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); - - //PHY_SetBBReg(priv, 0x800, bMaskDWord, (PHY_QueryBBReg(priv, 0x800, bMaskDWord)& ~ BIT(24))); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(priv, 0xa04, bMaskDWord))) ); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); - PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22204000); - - PHY_SetBBReg(priv, 0x870, BIT(10), 1); - PHY_SetBBReg(priv, 0x870, BIT(26), 1); - PHY_SetBBReg(priv, 0x860, BIT(10), 0); - PHY_SetBBReg(priv, 0x864, BIT(10), 0); - -#if defined(HIGH_POWER_EXT_PA) && defined(CONFIG_RTL_92C_SUPPORT) - //Allen TRSW to TX for external PA - PHY_SetBBReg(priv, 0x870, 0x60, 3); - PHY_SetBBReg(priv, 0x870, 0x600000, 3); - PHY_SetBBReg(priv, 0x860, 0x60, 1); - PHY_SetBBReg(priv, 0x864, 0x60, 1); -#endif - - if(is2T) { - PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00010000); - PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00010000); - } - - //Page B init - if(isNormal) - PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x00080000); - else - PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); - - if(is2T) { - if(isNormal) - PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x00080000); - else - PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); - } - - // IQ calibration setting - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x01007c00); - PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); - - for(i = 0 ; i < retryCount ; i++){ - PathAOK = _PHY_PathA_IQK(priv, is2T); - if(PathAOK == 0x03){ - result[t][0] = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - result[t][0] = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathAOK){ -// RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); - } - - if(is2T){ - _PHY_PathAStandBy_8192C(priv); - - // Turn Path B ADDA on - _PHY_PathADDAOn(priv, ADDA_REG, FALSE, is2T); - - for(i = 0 ; i < retryCount ; i++){ - PathBOK = _PHY_PathB_IQK(priv); - if(PathBOK == 0x03){ -// RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (PHY_QueryBBReg(priv, 0xec4, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (PHY_QueryBBReg(priv, 0xecc, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { -// RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ -// RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value -// RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, priv->pshare->RegC04); - PHY_SetBBReg(priv, 0x874, bMaskDWord, priv->pshare->Reg874); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, priv->pshare->RegC08); - - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - - // Restore RX initial gain - PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032ed3); - - if(is2T) - PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00032ed3); - - if(t!=0) { - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(priv, ADDA_REG, priv->pshare->ADDA_backup, 16); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); - } -} - - -void PHY_IQCalibrate_92C(struct rtl8192cd_priv *priv) -{ - int result[4][8]; //last is final result - unsigned char i, final_candidate; - char bPathAOK, bPathBOK; - int RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - char is12simular, is13simular, is23simular; - unsigned int temp_870, temp_860, temp_864, temp_a04; - -#ifdef MP_TEST - if (!priv->pshare->rf_ft_var.mp_specific) -#endif - { - if (priv->pshare->iqk_2g_done) - return; - priv->pshare->iqk_2g_done = 1; - } - - priv->pshare->IQK_total_cnt++; - - temp_870 = PHY_QueryBBReg(priv, 0x870, bMaskDWord); - temp_860 = PHY_QueryBBReg(priv, 0x860, bMaskDWord); - temp_864 = PHY_QueryBBReg(priv, 0x864, bMaskDWord); - //temp_800 = PHY_QueryBBReg(priv, 0x800, bMaskDWord); - temp_a04 = PHY_QueryBBReg(priv, 0xa04, bMaskDWord); - - memset(result, 0, sizeof(result)); - - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - for (i=0; i<3; i++) { - _PHY_IQCalibrate(priv, result, i, (GET_CHIP_VER(priv) == VERSION_8192C ? 1 : 0)); - - if(i == 1) { - is12simular = _PHY_SimularityCompare(priv, result, 0, 1); - if(is12simular) { - final_candidate = 0; - break; - } - } - - if(i == 2) { - is13simular = _PHY_SimularityCompare(priv, result, 0, 2); - if(is13simular) { - final_candidate = 0; - break; - } - - is23simular = _PHY_SimularityCompare(priv, result, 1, 2); - if(is23simular) - final_candidate = 1; - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } - - - RTL_W32(0x870, temp_870); - RTL_W32(0x860, temp_860); - RTL_W32(0x864, temp_864); - //RTL_W32(0x800, temp_800); - RTL_W32(0xa04, temp_a04); - - //load 0xe30 IQC default value - if(GET_CHIP_VER(priv) == VERSION_8188C) { - RTL_W32(0xe30, 0x01008c00); - RTL_W32(0xe34, 0x01008c00); - } - - for (i=0; i<4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - DEBUG_INFO("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC); - } - - if(final_candidate != 0xff) { - priv->pshare->RegE94 = RegE94 = result[final_candidate][0]; - priv->pshare->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - priv->pshare->RegEB4 = RegEB4 = result[final_candidate][4]; - priv->pshare->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - DEBUG_INFO ("IQK: final_candidate is %x\n",final_candidate); - DEBUG_INFO ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC); - bPathAOK = bPathBOK = TRUE; - } - else { - priv->pshare->RegE94 = priv->pshare->RegEB4 = 0x100; //X default value - priv->pshare->RegE9C = priv->pshare->RegEBC = 0x0; //Y default value - priv->pshare->IQK_fail_cnt++; - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - _PHY_PathAFillIQKMatrix(priv, bPathAOK, result, final_candidate, (RegEA4 == 0)? 1 :0); - if(GET_CHIP_VER(priv) == VERSION_8192C){ - if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) - _PHY_PathBFillIQKMatrix(priv, bPathBOK, result, final_candidate, (RegEC4 == 0)? 1 :0); - } -} - -#endif - - -// 92d IQK -#ifdef CONFIG_RTL_92D_SUPPORT -void IQK_92D_5G_n(struct rtl8192cd_priv *priv) -{ - unsigned int temp_a04, temp_c04, temp_874, temp_c08, temp_870, - temp_860, temp_864, temp_88c, temp_c50, temp_c58, temp_b30, - switch2PI=0, X, reg; //Oldval_0, Oldval_1, TX0_A, TX1_A; - u8 temp_522, temp_550, temp_551; - unsigned int cal_num=0, cal_retry=0, ADDA_backup[IQK_ADDA_REG_NUM]; - int Y, result[8][3], result_final[8]={0,0,0,0,0,0,0,0}; //TX0_C, TX1_C; - - unsigned int i, RX0REG0xe40[3], RX0REG0xe40_final=0, REG0xe40, REG0xe94, REG0xe9c, delay_count; - unsigned int REG0xeac, RX1REG0xe40[3], RX1REG0xe40_final=0, REG0xeb4, REG0xea4,REG0xec4; - unsigned char TX0IQKOK = FALSE, TX1IQKOK = FALSE; - unsigned int TX_X0, TX_Y0, TX_X1, TX_Y1, RX_X0, RX_Y0, RX_X1, RX_Y1; - unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - return IQK_92D_5G_phy0_n(priv); -#endif - - //always do IQK for MP mode -#ifdef MP_TEST - if (!priv->pshare->rf_ft_var.mp_specific) -#endif - { - if (priv->pmib->dot11RFEntry.macPhyMode == SINGLEMAC_SINGLEPHY) { - if (priv->pshare->iqk_5g_done) - return; - priv->pshare->iqk_5g_done = 1; - } - } - - printk(">> %s \n",__FUNCTION__); - - watchdog_kick(); - - /* - * Save MAC default value - */ - temp_522 = RTL_R8(0x522); - temp_550 = RTL_R8(0x550); - temp_551 = RTL_R8(0x551); - - /* - * Save BB Parameter - */ - temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); - temp_c04 = RTL_R32(0xc04); - temp_874 = RTL_R32(0x874); - temp_c08 = RTL_R32(0xc08); - temp_870 = RTL_R32(0x870); - temp_860 = RTL_R32(0x860); - temp_864 = RTL_R32(0x864); - temp_88c = RTL_R32(0x88c); - temp_c50 = RTL_R32(0xc50); // 01/11/2011 update - temp_c58 = RTL_R32(0xc58); // 01/11/2011 update - temp_b30 = RTL_R32(0xb30); // 03/03/2011 update - - /* - * Save AFE Parameters - */ - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - ADDA_backup[i] = RTL_R32(ADDA_REG[i]); - - /* - * ============== - * Path-A TX/RX IQK - * ============== - */ - while (cal_num < 3) { - /* - * Path-A AFE all on - */ - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - RTL_W32(ADDA_REG[i], 0x04db25a4); - - /* - * MAC register setting - */ - RTL_W8(0x522, 0x3f); - RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); - RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); - - /* - * IQK must be done in PI mode - */ - if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); - switch2PI++; - } - - /* - * BB setting - */ - //PHY_SetBBReg(priv, 0x800, BIT(24), 0); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); - PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22208000); - PHY_SetBBReg(priv, 0x88c, BIT(23)|BIT(22)|BIT(21)|BIT(20), 0xf); - PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); // 03/03/2011 update - - /* - * AP or IQK - */ - //PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); - //PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); - - // IQK-R03 2011/02/16 update - - //path A AP setting for IQK - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0); - PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x20000000); - //path B AP setting for IQK - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0); - PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x20000000); - - /* - * IQK global setting - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x10007c00); - PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); - - /* - * path-A IQK setting - */ - PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140307); // 01/11/2011 update -#ifdef USB_POWER_SUPPORT - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160c66); -#else - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160960); // 01/11/2011 update -#endif - - /* - * path-B IQK setting - */ - PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c2f); - PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c2f); - PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82110000); - PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68110000); - - /* - * LO calibration setting - */ - PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); - -#ifdef USB_POWER_SUPPORT - // path-A TRSW setting - PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); - PHY_SetBBReg(priv, 0x860, BIT(6)|BIT(5), 3); -#else - /* - * path-A PA on - */ - /* - PHY_SetBBReg(priv, 0x870, BIT(11)|BIT(10), 3); - PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); - PHY_SetBBReg(priv, 0x860, BIT(11)|BIT(10), 3); - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000f60); // 01/11/2011 update - PHY_SetBBReg(priv, 0x860, bMaskDWord, 0x66e60e30); // 01/11/2011 update -#endif - /* - * One shot, path A LOK & IQK - */ - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); - - /* - * Delay 10 ms - */ - delay_ms(10); - - delay_count = 0; - while (1){ - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - if ((REG0xeac&BIT(26))||(delay_count>20)){ - break; - }else { - delay_ms(1); - delay_count++; - } - } - /* - * Check_TX_IQK_A_result - */ - REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); - REG0xe94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); - if(((REG0xeac&BIT(28)) == 0) && (((REG0xe94&0x3FF0000)>>16)!=0x142)) { - TX0IQKOK = TRUE; - REG0xe9c = PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); - TX_X0 = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; - TX_Y0 = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; - RX0REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X0<<16) | TX_Y0; - DEBUG_INFO("TX_X0 %08x TX_Y0 %08x RX0REG0xe40 %08x\n", TX_X0, TX_Y0, RX0REG0xe40[cal_num]); - result[0][cal_num] = TX_X0; - result[1][cal_num] = TX_Y0; - } else { - TX0IQKOK = FALSE; - if (++cal_retry >= 10) { - printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); - break; - } - } - - /* - * Check_RX_IQK_A_result - */ - if(TX0IQKOK == TRUE) { - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - REG0xea4 = PHY_QueryBBReg(priv, 0xea4, bMaskDWord); - if(((REG0xeac&BIT(27)) == 0) && (((REG0xea4&0x3FF0000)>>16)!=0x132)) { - RX_X0 = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; - RX_Y0 = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; - DEBUG_INFO("RX_X0 %08x RX_Y0 %08x\n", RX_X0, RX_Y0); - result[2][cal_num] = RX_X0; - result[3][cal_num] = RX_Y0; - cal_num++; - } else { - PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x19008c00); - if (++cal_retry >= 10) { - printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); - break; - } - } - } - } - - if (cal_num == 3) { - result_final[0] = get_mean_of_2_close_value(result[0]); - result_final[1] = get_mean_of_2_close_value(result[1]); - result_final[2] = get_mean_of_2_close_value(result[2]); - result_final[3] = get_mean_of_2_close_value(result[3]); - RX0REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX0REG0xe40); - - priv->pshare->RegE94=result_final[0]; - priv->pshare->RegE9C=result_final[1]; - } else { - priv->pshare->RegE94=0x100; - priv->pshare->RegE9C=0x00; - } - - /* - * Path-A PA off - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); - PHY_SetBBReg(priv, 0x860, bMaskDWord, temp_860); - - - /* - * ============== - * Path-B TX/RX IQK - * ============== - */ - cal_num = cal_retry = 0; - while (cal_num < 3) { - /* - * Path-B AFE all on - */ - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, 0x0b1b25a4); - - /* - * path-A IQK setting - */ - PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82110000); - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68110000); - - /* - * path-B IQK setting - */ - PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c22); - PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c22); - PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140307); // 01/11/2011 update - - // 01/11/2011 update -#ifdef USB_POWER_SUPPORT - PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68160c66); -#else - PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68160960); // 01/11/2011 update -#endif - - /* - * LO calibration setting - */ - PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); - -#ifdef USB_POWER_SUPPORT - PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 3); - PHY_SetBBReg(priv, 0x864, BIT(6)|BIT(5), 3); -#else - /* - * path-B PA on - */ - /* - PHY_SetBBReg(priv, 0x870, BIT(27)|BIT(26), 3); - PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 3); - PHY_SetBBReg(priv, 0x864, BIT(11)|BIT(10), 3); - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x0f600700); - PHY_SetBBReg(priv, 0x864, bMaskDWord, 0x061f0d30); -#endif - - /* - * One shot, path A LOK & IQK - */ - PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000002); - PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000000); - - /* - * Delay 10 ms - */ - delay_ms(10); - - delay_count = 0; - while (1){ - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - if ((REG0xeac&BIT(29))||(delay_count>20)){ - break; - }else { - delay_ms(1); - delay_count++; - } - } - /* - * Check_TX_IQK_B_result - */ - REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - REG0xeb4 = PHY_QueryBBReg(priv, 0xeb4, bMaskDWord); - if(((REG0xeac&BIT(31)) == 0) && ((REG0xeb4&0x3FF0000)!=0x142)) { - TX1IQKOK = TRUE; - TX_X1 = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; - TX_Y1 = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; - RX1REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X1<<16) | TX_Y1; - DEBUG_INFO("TX_X1 %08x TX_Y1 %08x RX1REG0xe40 %08x\n", TX_X1, TX_Y1, RX1REG0xe40[cal_num]); - result[4][cal_num] = TX_X1; - result[5][cal_num] = TX_Y1; - } else { - TX1IQKOK = FALSE; - if (++cal_retry >= 10) { - printk("%s Path-B Tx/Rx Check\n",__FUNCTION__); - break; - } - } - - /* - * Check_RX_IQK_B_result - */ - if(TX1IQKOK == TRUE) { - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - REG0xec4 = PHY_QueryBBReg(priv, 0xec4, bMaskDWord); - if(((REG0xeac&BIT(30)) == 0) && (((REG0xec4&0x3FF0000)>>16)!=0x132)) { - RX_X1 = (PHY_QueryBBReg(priv, 0xec4, bMaskDWord)&0x3FF0000)>>16; - RX_Y1 = (PHY_QueryBBReg(priv, 0xecc, bMaskDWord)&0x3FF0000)>>16; - DEBUG_INFO("RX_X1 %08x RX_Y1 %08x\n", RX_X1, RX_Y1); - result[6][cal_num] = RX_X1; - result[7][cal_num] = RX_Y1; - cal_num++; - } else { - PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x19008c00); - if (++cal_retry >= 10) { - printk("%s Path-B Tx/Rx Check\n",__FUNCTION__); - break; - } - } - } - } - - if (cal_num == 3) { - result_final[4] = get_mean_of_2_close_value(result[4]); - result_final[5] = get_mean_of_2_close_value(result[5]); - result_final[6] = get_mean_of_2_close_value(result[6]); - result_final[7] = get_mean_of_2_close_value(result[7]); - RX1REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX1REG0xe40); - - priv->pshare->RegEB4=result_final[4]; - priv->pshare->RegEBC=result_final[5]; - } else { - priv->pshare->RegEB4=0x100; - priv->pshare->RegEBC=0x00; - } - - /* - * Fill IQK result for Path A - */ - if (result_final[0]) { - /* - Oldval_0 = (PHY_QueryBBReg(priv, 0xc80, bMaskDWord) >> 22) & 0x3FF; - X = result_final[0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - PHY_SetBBReg(priv, 0xc80, 0x3FF, TX0_A); - PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X* Oldval_0>>7) & 0x1)); - - Y = result_final[1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - TX0_C = (Y * Oldval_0) >> 8; - PHY_SetBBReg(priv, 0xc94, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(priv, 0xc80, 0x003F0000, (TX0_C&0x3F)); - PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y* Oldval_0>>7) & 0x1)); - */ - - // IQK-R03 2011/02/16 update - X = result_final[0]; - Y = result_final[1]; - //printk("X=%x Y=%x\n",X,Y); - //Path-A OFDM_A - PHY_SetBBReg(priv, 0xe30, 0x03FF0000, X); - PHY_SetBBReg(priv, 0xc4c, BIT(24), 0); - //Path-A OFDM_C - PHY_SetBBReg(priv, 0xe30, 0x000003FF, Y); - PHY_SetBBReg(priv, 0xc4c, BIT(26), 0); - - if(result_final[2]) { - reg = result_final[2]; - PHY_SetBBReg(priv, 0xc14, 0x3FF, reg); - reg = result_final[3] & 0x3F; - PHY_SetBBReg(priv, 0xc14, 0xFC00, reg); - - reg = (result_final[3] >> 6) & 0xF; - PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); - - PHY_SetBBReg(priv, 0xe34, 0x03FF0000, result_final[2]); // X - PHY_SetBBReg(priv, 0xe34, 0x3FF, result_final[3]); //Y - } - } - - /* - * Fill IQK result for Path B - */ - if (result_final[4]) { - /* - Oldval_1 = (PHY_QueryBBReg(priv, 0xc88, bMaskDWord) >> 22) & 0x3FF; - - X = result_final[4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - PHY_SetBBReg(priv, 0xc88, 0x3FF, TX1_A); - PHY_SetBBReg(priv, 0xc4c, BIT(28), ((X* Oldval_1>>7) & 0x1)); - - Y = result_final[5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - TX1_C = (Y * Oldval_1) >> 8; - PHY_SetBBReg(priv, 0xc9c, 0xF0000000, ((TX1_C&0x3C0)>>6)); - PHY_SetBBReg(priv, 0xc88, 0x003F0000, (TX1_C&0x3F)); - PHY_SetBBReg(priv, 0xc4c, BIT(30), ((Y* Oldval_1>>7) & 0x1)); - */ - - // IQK-R03 2011/02/16 update - X = result_final[4]; - Y = result_final[5]; - //printk("X=%x Y=%x\n",X,Y); - //Path-A OFDM_A - PHY_SetBBReg(priv, 0xe50, 0x03FF0000, X); - PHY_SetBBReg(priv, 0xc4c, BIT(28), 0); - //Path-A OFDM_C - PHY_SetBBReg(priv, 0xe50, 0x000003FF, Y); - PHY_SetBBReg(priv, 0xc4c, BIT(30), 0); - - if(result_final[6]) { - reg = result_final[6]; - PHY_SetBBReg(priv, 0xc1c, 0x3FF, reg); - - reg = result_final[7] & 0x3F; - PHY_SetBBReg(priv, 0xc1c, 0xFC00, reg); - - reg = (result_final[7] >> 6) & 0xF; - PHY_SetBBReg(priv, 0xc78, 0x0000F000, reg); - - PHY_SetBBReg(priv, 0xe54, 0x03FF0000, result_final[6]); // X - PHY_SetBBReg(priv, 0xe54, 0x3FF, result_final[7]); //Y - } - } - - /* - * Path B PA off - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); - PHY_SetBBReg(priv, 0x864, bMaskDWord, temp_864); - - /* - * Exit IQK mode - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, temp_c04); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, temp_c08); - PHY_SetBBReg(priv, 0x874, bMaskDWord, temp_874); - //PHY_SetBBReg(priv, 0x800, bMaskDWord, temp_800); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, temp_a04); - PHY_SetBBReg(priv, 0x88c, bMaskDWord, temp_88c); - PHY_SetBBReg(priv, 0xb30, bMaskDWord, temp_b30); // 03/03/2011 update - //PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032fff); // 01/11/2011 update - //PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00032fff); // 01/11/2011 update - - // IQK-R03 2011/02/16 update - //path A IQ path to DP block - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); - //path B IQ path to DP block - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x010170b8); - - //path AB to initial gain - PHY_SetBBReg(priv, 0xc50, bMaskDWord, 0x50); // 01/11/2011 update - PHY_SetBBReg(priv, 0xc50, bMaskDWord, temp_c50); // 01/11/2011 update - PHY_SetBBReg(priv, 0xc58, bMaskDWord, 0x50); // 01/11/2011 update - PHY_SetBBReg(priv, 0xc58, bMaskDWord, temp_c58); // 01/11/2011 update - - - /* - * Reload MAC default value - */ - RTL_W8(0x550, temp_550); - RTL_W8(0x551, temp_551); - RTL_W8(0x522, temp_522); - - /* - * Switch back to SI if needed, after IQK - */ - if (switch2PI) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); - } - - /* - * Reload ADDA power saving parameters - */ - for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); - - -#if 0 //def CLIENT_MODE - clnt_save_IQK_res(priv); -#endif - - if (!TX0IQKOK && !TX1IQKOK) - priv->pshare->IQK_fail_cnt++; -} - - -void IQK_92D_2G(struct rtl8192cd_priv *priv) -{ - unsigned int cal_num=0, cal_retry=0, Oldval=0, temp_c04=0, temp_c08=0, temp_874=0, temp_eac; - unsigned int cal_e94, cal_e9c, cal_ea4, cal_eac, cal_eb4, cal_ebc, cal_ec4, cal_ecc; - unsigned int X, Y, val_e94[3], val_e9c[3], val_ea4[3], val_eac[3], val_eb4[3], val_ebc[3], val_ec4[3], val_ecc[3]; - unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; - unsigned int ADDA_backup[IQK_ADDA_REG_NUM], i; - u8 temp_522, temp_550, temp_551; - u32 temp_040, temp_a04, temp_870, temp_860, temp_864, temp_88c; - u8 switch2PI = 0; - unsigned char IQKOK = 0; - -#ifdef CONFIG_RTL_92D_DMDP - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - return IQK_92D_2G_phy1(priv); -#endif - - //always do IQK for MP mode -#ifdef MP_TEST - if (!priv->pshare->rf_ft_var.mp_specific) -#endif - { - if (priv->pmib->dot11RFEntry.macPhyMode == SINGLEMAC_SINGLEPHY) { - if (priv->pshare->iqk_2g_done) - return; - priv->pshare->iqk_2g_done = 1; - } - } - - printk(">> %s \n",__FUNCTION__); - - // Save ADDA power saving parameters - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - ADDA_backup[i] = RTL_R32(ADDA_REG[i]); - - /* - * Save MAC default value - */ - temp_522 = RTL_R8(0x522); - temp_550 = RTL_R8(0x550); - temp_551 = RTL_R8(0x551); - temp_040 = RTL_R32(0x40); - - // Save BB default - temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); - temp_870 = RTL_R32(0x870); - temp_860 = RTL_R32(0x860); - temp_864 = RTL_R32(0x864); - temp_88c = RTL_R32(0x88c); - - // Path-A ADDA all on - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - RTL_W32(ADDA_REG[i], 0x04db25a4); - - // IQ&LO calibration Setting - //IQK must be done in PI mode - if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); - switch2PI++; - } - - //MAC register setting - RTL_W8(0x522, 0x3f); - RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); - RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); - RTL_W32(0x40, 0); - - //BB setting - temp_c04 = RTL_R32(0xc04); - temp_c08 = RTL_R32(0xc08); - temp_874 = RTL_R32(0x874); - //PHY_SetBBReg(priv,0x800,BIT(24),0); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); - RTL_W32(0xc04, 0x03a05600); - RTL_W32(0xc08, 0x000800e4); - RTL_W32(0x874, 0x22204000); - - PHY_SetBBReg(priv, 0x870, BIT(10), 1); - PHY_SetBBReg(priv, 0x870, BIT(26), 1); - PHY_SetBBReg(priv, 0x860, BIT(10), 0); - PHY_SetBBReg(priv, 0x864, BIT(10), 0); - - PHY_SetBBReg(priv,0x88c,0x00f00000,0xf); - RTL_W32(0x840, 0x00010000); - RTL_W32(0x844, 0x00010000); - - //AP or IQK - RTL_W32(0xb68 , 0x0f600000); - RTL_W32(0xb6c , 0x0f600000); - - // IQK setting - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - RTL_W32(0xe40, 0x01007c00); - RTL_W32(0xe44, 0x01004800); - // path-A IQK setting - RTL_W32(0xe30, 0x10008c1f); - RTL_W32(0xe34, 0x10008c1f); - RTL_W32(0xe38, 0x82140102); - RTL_W32(0xe3c, 0x28160206); - // path-B IQK setting - RTL_W32(0xe50, 0x10008c22); - RTL_W32(0xe54, 0x10008c22); - RTL_W32(0xe58, 0x82140102); - RTL_W32(0xe5c, 0x28160206); - // LO calibration setting - RTL_W32(0xe4c, 0x00462911); - - // delay to ensure Path-A IQK success - delay_ms(10); - - // step 4: One shot, path A LOK & IQK - while (cal_num < 3) { - // One shot, path A LOK & IQK - RTL_W32(0xe48, 0xf9000000); - RTL_W32(0xe48, 0xf8000000); - // delay 1ms - delay_ms(1); - - // check fail bit and check abnormal condition, then fill BB IQ matrix - cal_e94 = (RTL_R32(0xe94) >> 16) & 0x3ff; - cal_e9c = (RTL_R32(0xe9c) >> 16) & 0x3ff; - cal_ea4 = (RTL_R32(0xea4) >> 16) & 0x3ff; - temp_eac = RTL_R32(0xeac); - cal_eac = (temp_eac >> 16) & 0x3ff; - if (!(temp_eac & BIT(28)) && !(temp_eac & BIT(27)) && - (cal_e94 != 0x142) && (cal_e9c != 0x42) && - (cal_ea4 != 0x132) && (cal_eac != 0x36)) { - val_e94[cal_num] = cal_e94; - val_e9c[cal_num] = cal_e9c; - val_ea4[cal_num] = cal_ea4; - val_eac[cal_num] = cal_eac; - cal_num++; - } else { - if (++cal_retry >= 10) { - printk("%s Path-A Check\n",__FUNCTION__); - break; - } - } - } - - if (cal_num == 3) { - cal_e94 = get_mean_of_2_close_value(val_e94); - cal_e9c = get_mean_of_2_close_value(val_e9c); - cal_ea4 = get_mean_of_2_close_value(val_ea4); - cal_eac = get_mean_of_2_close_value(val_eac); - - priv->pshare->RegE94=cal_e94; - priv->pshare->RegE9C=cal_e9c; - - Oldval = (RTL_R32(0xc80) >> 22) & 0x3ff; - - X = cal_e94; - PHY_SetBBReg(priv, 0xc80, 0x3ff, (X * Oldval)>>8); - PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X * Oldval) >> 7) & 0x1); - - Y = cal_e9c; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - PHY_SetBBReg(priv, 0xc94, 0xf0000000, (((Y * Oldval) >> 8) >> 6) & 0xf); - PHY_SetBBReg(priv, 0xc80, 0x003f0000, ((Y * Oldval) >> 8) & 0x3f); - PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y * Oldval) >> 7) & 0x1); - - PHY_SetBBReg(priv, 0xc14, 0x3ff, cal_ea4); - - PHY_SetBBReg(priv, 0xc14, 0xfc00, cal_eac & 0x3f); - - PHY_SetBBReg(priv, 0xca0, 0xf0000000, (cal_eac >> 6) & 0xf); - }else { - IQKOK++; - priv->pshare->RegE94=0x100; - priv->pshare->RegE9C=0x00; - } - - // step 5: Path-A standby mode - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - RTL_W32(0x840, 0x00010000); - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - - // step 6: Path-B ADDA all on - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - RTL_W32(ADDA_REG[i], 0x0b1b25a4); - - // step 7: One shot, path B LOK & IQK - cal_num = 0; - cal_retry = 0; - while (cal_num < 3) { - // One shot, path B LOK & IQK - RTL_W32(0xe60, 2); - RTL_W32(0xe60, 0); - // delay 1ms - delay_ms(1); - - // check fail bit and check abnormal condition, then fill BB IQ matrix - cal_eb4 = (RTL_R32(0xeb4) >> 16) & 0x3ff; - cal_ebc = (RTL_R32(0xebc) >> 16) & 0x3ff; - cal_ec4 = (RTL_R32(0xec4) >> 16) & 0x3ff; - cal_ecc = (RTL_R32(0xecc) >> 16) & 0x3ff; - temp_eac = RTL_R32(0xeac); - if (!(temp_eac & BIT(31)) && !(temp_eac & BIT(30)) && - (cal_eb4 != 0x142) && (cal_ebc != 0x42) && - (cal_ec4 != 0x132) && (cal_ecc != 0x36)) { - val_eb4[cal_num] = cal_eb4; - val_ebc[cal_num] = cal_ebc; - val_ec4[cal_num] = cal_ec4; - val_ecc[cal_num] = cal_ecc; - cal_num++; - } else { - if (++cal_retry >= 10) { - printk("%s Path-B Check\n",__FUNCTION__); - break; - } - } - } - - if (cal_num == 3) { - cal_eb4 = get_mean_of_2_close_value(val_eb4); - cal_ebc = get_mean_of_2_close_value(val_ebc); - cal_ec4 = get_mean_of_2_close_value(val_ec4); - cal_ecc = get_mean_of_2_close_value(val_ecc); - - priv->pshare->RegEB4=cal_eb4; - priv->pshare->RegEBC=cal_ebc; - - Oldval = (RTL_R32(0xc88) >> 22) & 0x3ff; - - X = cal_eb4; - PHY_SetBBReg(priv, 0xc88, 0x3ff, (X * Oldval) >> 8 ); - PHY_SetBBReg(priv, 0xc4c, BIT(28), ((X * Oldval) >> 7) & 0x1); - - Y = cal_ebc; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - PHY_SetBBReg(priv, 0xc9c, 0xf0000000, (((Y * Oldval) >> 8 ) >> 6) & 0xf); - PHY_SetBBReg(priv, 0xc88, 0x003f0000, ((Y * Oldval) >> 8 ) & 0x3f); - PHY_SetBBReg(priv, 0xc4c, BIT(30), ((Y * Oldval) >> 7) & 0x1); - - PHY_SetBBReg(priv, 0xc1c, 0x3ff, cal_ec4); - - PHY_SetBBReg(priv, 0xc1c, 0xfc00, cal_ecc & 0x3f); - - PHY_SetBBReg(priv, 0xc78, 0xf000, (cal_ecc >> 6) & 0xf); - }else { - IQKOK++; - priv->pshare->RegEB4=0x100; - priv->pshare->RegEBC=0x00; - } - - // step 8: back to BB mode, load original values - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - RTL_W32(0xc04, temp_c04); - RTL_W32(0xc08, temp_c08); - RTL_W32(0x874, temp_874); - //RTL_W32(0x800, temp_800); - RTL_W32(0xa04, temp_a04); - RTL_W32(0x88c, temp_88c); - RTL_W32(0x840, 0x32fff); - RTL_W32(0x844, 0x32fff); - RTL_W32(0x870, temp_870); - RTL_W32(0x860, temp_860); - RTL_W32(0x864, temp_864); - - /* - * Switch back to SI if needed, after IQK - */ - if (switch2PI) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); - } - - watchdog_kick(); - - /* - * Reload ADDA power saving parameters - */ - for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); - - /* - * Reload MAC default value - */ - RTL_W8(0x550, temp_550); - RTL_W8(0x551, temp_551); - RTL_W32(0x40, temp_040); - RTL_W8(0x522, temp_522); - - -#if 0 //def CLIENT_MODE - clnt_save_IQK_res(priv); -#endif - if (!IQKOK) - priv->pshare->IQK_fail_cnt++; -} -#ifdef CONFIG_RTL_92D_DMDP - -void IQK_92D_2G_phy1(struct rtl8192cd_priv *priv) -{ - unsigned int cal_num=0, cal_retry=0, Oldval=0, temp_c04=0, temp_c08=0, temp_874=0, temp_eac; - unsigned int cal_e94, cal_e9c, cal_ea4, cal_eac; - unsigned int X, Y, val_e94[3], val_e9c[3], val_ea4[3], val_eac[3]; - unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; - unsigned int ADDA_backup[IQK_ADDA_REG_NUM], i; - u8 temp_522, temp_550, temp_551; - u32 temp_040, temp_870, temp_860, temp_864, temp_a04, temp_88c; - u8 switch2PI = 0; - unsigned char IQKOK = 0; - -#ifdef MP_TEST - if (!priv->pshare->rf_ft_var.mp_specific) -#endif - { - if (priv->pshare->iqk_2g_done) - return; - priv->pshare->iqk_2g_done = 1; - } - - printk(">> %s \n",__FUNCTION__); - - // Save ADDA power saving parameters - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - ADDA_backup[i] = RTL_R32(ADDA_REG[i]); - - /* - * Save MAC default value - */ - temp_522 = RTL_R8(0x522); - temp_550 = RTL_R8(0x550); - temp_551 = RTL_R8(0x551); - temp_040 = RTL_R32(0x40); - - // Save BB default - temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); - temp_870 = RTL_R32(0x870); - temp_860 = RTL_R32(0x860); - temp_864 = RTL_R32(0x864); - temp_88c = RTL_R32(0x88c); - - // Path-A ADDA all on - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) { -#ifdef NON_INTR_ANTDIV - if (DMDP_PHY_QueryBBReg(0, 0xb30,BIT(27))) - RTL_W32(ADDA_REG[i], 0x04db25a4); - else -#endif - RTL_W32(ADDA_REG[i], 0x0b1b25a4); - } - - - // IQ&LO calibration Setting - - /* - * IQK must be done in PI mode - */ - if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); - switch2PI++; - } - - //MAC register setting - RTL_W8(0x522, 0x3f); - RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); - RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); - RTL_W32(0x40, 0); - - //BB setting - temp_c04 = RTL_R32(0xc04); - temp_c08 = RTL_R32(0xc08); - temp_874 = RTL_R32(0x874); - //PHY_SetBBReg(priv, 0x800, BIT(24), 0); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); - RTL_W32(0xc04, 0x03a05600); - RTL_W32(0xc08, 0x000800e4); - RTL_W32(0x874, 0x22204000); - - PHY_SetBBReg(priv, 0x870, BIT(10), 1); - PHY_SetBBReg(priv, 0x870, BIT(26), 1); - PHY_SetBBReg(priv, 0x860, BIT(10), 0); - PHY_SetBBReg(priv, 0x864, BIT(10), 0); - - PHY_SetBBReg(priv,0x88c,0x00f00000,0xf); - - RTL_W32(0x840, 0x00010000); - - //AP or IQK - RTL_W32(0xb68 , 0x0f600000); - RTL_W32(0xb6c , 0x0f600000); - - // IQK setting - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - RTL_W32(0xe40, 0x01007c00); - RTL_W32(0xe44, 0x01004800); - - // path-A IQK setting - RTL_W32(0xe30, 0x10008c22); - RTL_W32(0xe34, 0x10008c22); - RTL_W32(0xe38, 0x82140102); - RTL_W32(0xe3c, 0x28160206); - - // LO calibration setting - RTL_W32(0xe4c, 0x00462911); - - // delay to ensure Path-A IQK success - delay_ms(10); - - // step 4: One shot, path A LOK & IQK - while (cal_num < 3) { - // One shot, path A LOK & IQK - RTL_W32(0xe48, 0xf9000000); - RTL_W32(0xe48, 0xf8000000); - // delay 1ms - delay_ms(1); - - // check fail bit and check abnormal condition, then fill BB IQ matrix - cal_e94 = (RTL_R32(0xe94) >> 16) & 0x3ff; - cal_e9c = (RTL_R32(0xe9c) >> 16) & 0x3ff; - cal_ea4 = (RTL_R32(0xea4) >> 16) & 0x3ff; - temp_eac = RTL_R32(0xeac); - cal_eac = (temp_eac >> 16) & 0x3ff; - if (!(temp_eac & BIT(28)) && !(temp_eac & BIT(27)) && - (cal_e94 != 0x142) && (cal_e9c != 0x42) && - (cal_ea4 != 0x132) && (cal_eac != 0x36)) { - val_e94[cal_num] = cal_e94; - val_e9c[cal_num] = cal_e9c; - val_ea4[cal_num] = cal_ea4; - val_eac[cal_num] = cal_eac; - cal_num++; - } else { - if (++cal_retry >= 10) { - printk("%s Path-A Check\n",__FUNCTION__); - break; - } - } - } - - if (cal_num == 3) { - cal_e94 = get_mean_of_2_close_value(val_e94); - cal_e9c = get_mean_of_2_close_value(val_e9c); - cal_ea4 = get_mean_of_2_close_value(val_ea4); - cal_eac = get_mean_of_2_close_value(val_eac); - - priv->pshare->RegE94=cal_e94; - priv->pshare->RegE9C=cal_e9c; - - Oldval = (RTL_R32(0xc80) >> 22) & 0x3ff; - - X = cal_e94; - PHY_SetBBReg(priv, 0xc80, 0x3ff, (X * Oldval) >> 8); - PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X * Oldval) >> 7) & 0x1); - - Y = cal_e9c; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - PHY_SetBBReg(priv, 0xc94, 0xf0000000, (((Y * Oldval) >> 8) >> 6) & 0xf); - PHY_SetBBReg(priv, 0xc80, 0x003f0000, ((Y * Oldval) >> 8) & 0x3f); - PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y * Oldval) >> 7) & 0x1); - - PHY_SetBBReg(priv, 0xc14, 0x3ff, cal_ea4); - - PHY_SetBBReg(priv, 0xc14, 0xfc00, cal_eac & 0x3f); - - PHY_SetBBReg(priv, 0xca0, 0xf0000000, (cal_eac >> 6) & 0xf); - }else { - IQKOK++; - priv->pshare->RegE94=0x100; - priv->pshare->RegE9C=0x00; - } - - // back to BB mode, load original values - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - RTL_W32(0xc04, temp_c04); - RTL_W32(0xc08, temp_c08); - RTL_W32(0x874, temp_874); - //RTL_W32(0x800, temp_800); - RTL_W32(0xa04, temp_a04); - - RTL_W32(0x88c, temp_88c); - RTL_W32(0x840, 0x32fff); - RTL_W32(0x870, temp_870); - RTL_W32(0x860, temp_860); - RTL_W32(0x864, temp_864); - - // return to SI mode - if (switch2PI) { - RTL_W32(0x820, 0x01000000); - RTL_W32(0x828, 0x01000000); - } - - watchdog_kick(); - - /* - * Reload ADDA power saving parameters - */ - for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); - - /* - * Reload MAC default value - */ - RTL_W8(0x550, temp_550); - RTL_W8(0x551, temp_551); - RTL_W32(0x40, temp_040); - RTL_W8(0x522, temp_522); - - if (!IQKOK) - priv->pshare->IQK_fail_cnt++; -} - - -void IQK_92D_5G_phy0_n(struct rtl8192cd_priv *priv) -{ - unsigned int temp_a04, temp_c04, temp_874, temp_c08, temp_870, temp_860, temp_88c, temp_c50, temp_b30, - switch2PI=0, X, reg; //, Oldval_0, TX0_A; - u8 temp_522, temp_550, temp_551; - unsigned int cal_num=0, cal_retry=0, ADDA_backup[IQK_ADDA_REG_NUM]; - int Y, result[8][3], result_final[8]={0,0,0,0,0,0,0,0}; //, TX0_C; - - unsigned int i, RX0REG0xe40[3], RX0REG0xe40_final=0, REG0xe40, REG0xe94, REG0xe9c, delay_count; - unsigned int REG0xeac, REG0xea4; - unsigned char TX0IQKOK = FALSE; - unsigned int TX_X0, TX_Y0, RX_X0, RX_Y0; - unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, - 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; - -#ifdef MP_TEST - if (!priv->pshare->rf_ft_var.mp_specific) -#endif - { - if (priv->pshare->iqk_5g_done) - return; - priv->pshare->iqk_5g_done = 1; - } - - printk(">> %s \n",__FUNCTION__); - - watchdog_kick(); - - /* - * Save MAC default value - */ - temp_522 = RTL_R8(0x522); - temp_550 = RTL_R8(0x550); - temp_551 = RTL_R8(0x551); - - /* - * Save BB Parameter - */ - temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); - temp_c04 = RTL_R32(0xc04); - temp_874 = RTL_R32(0x874); - temp_c08 = RTL_R32(0xc08); - temp_870 = RTL_R32(0x870); - temp_860 = RTL_R32(0x860); - temp_88c = RTL_R32(0x88c); - temp_c50 = RTL_R32(0xc50); - temp_b30 = RTL_R32(0xb30); // 03/03/2011 update - - /* - * Save AFE Parameters - */ - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - ADDA_backup[i] = RTL_R32(ADDA_REG[i]); - - /* - * ============== - * Path-A TX/RX IQK - * ============== - */ - while (cal_num < 3) { - /* - * Path-A AFE all on - */ - for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) { -#ifdef NON_INTR_ANTDIV - if (DMDP_PHY_QueryBBReg(0, 0xb30,BIT(27))) - RTL_W32(ADDA_REG[i], 0x0b1b25a4); - else -#endif - RTL_W32(ADDA_REG[i], 0x04db25a4); - } - - /* - * MAC register setting - */ - RTL_W8(0x522, 0x3f); - RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); - RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); - - /* - * IQK must be done in PI mode - */ - if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); - switch2PI++; - } - - /* - * BB setting - */ - //PHY_SetBBReg(priv, 0x800, BIT(24), 0); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); - PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22208000); - PHY_SetBBReg(priv, 0x88c, BIT(23)|BIT(22)|BIT(21)|BIT(20), 0xf); - PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); // 03/03/2011 update - - /* - * AP or IQK - */ - //PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); - //PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); - - // IQK-R03 2011/02/16 update - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0); - PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x20000000); - - /* - * IQK global setting - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); - PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x10007c00); - PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); - - /* - * path-A IQK setting - */ - PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); - PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140307); // 01/11/2011 update - -#ifdef USB_POWER_SUPPORT - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160c66); -#else - PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160960); // 01/11/2011 update -#endif - /* - * LO calibration setting - */ - PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); - -#ifdef USB_POWER_SUPPORT - // PHY0 TRSW seting - PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); - PHY_SetBBReg(priv, 0x860, BIT(6)|BIT(5), 3); -#else - /* - * path-A PA on - */ - /* - PHY_SetBBReg(priv, 0x870, BIT(11)|BIT(10), 3); - PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); - PHY_SetBBReg(priv, 0x860, BIT(11)|BIT(10), 3); - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000f60); // 01/11/2011 update - PHY_SetBBReg(priv, 0x860, bMaskDWord, 0x66e60e30); // 01/11/2011 update -#endif - /* - * One shot, path A LOK & IQK - */ - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); - PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); - - /* - * Delay 10 ms - */ - delay_ms(10); - - delay_count = 0; - while (1){ - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - if ((REG0xeac&BIT(26))||(delay_count>20)){ - break; - }else { - delay_ms(1); - delay_count++; - } - } - - /* - * Check_TX_IQK_A_result - */ - REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - REG0xe94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); - if(((REG0xeac&BIT(28)) == 0) && (((REG0xe94&0x3FF0000)>>16)!=0x142)) { - TX0IQKOK = TRUE; - REG0xe9c = PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); - TX_X0 = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; - TX_Y0 = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; - RX0REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X0<<16) | TX_Y0; - DEBUG_INFO("TX_X0 %08x TX_Y0 %08x RX0REG0xe40 %08x\n", TX_X0, TX_Y0, RX0REG0xe40[cal_num]); - result[0][cal_num] = TX_X0; - result[1][cal_num] = TX_Y0; - } else { - TX0IQKOK = FALSE; - if (++cal_retry >= 10) { - printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); - break; - } - } - - /* - * Check_RX_IQK_A_result - */ - if(TX0IQKOK == TRUE) { - REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); - REG0xea4 = PHY_QueryBBReg(priv, 0xea4, bMaskDWord); - if(((REG0xeac&BIT(27)) == 0) && (((REG0xea4&0x3FF0000)>>16)!=0x132)) { - RX_X0 = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; - RX_Y0 = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; - DEBUG_INFO("RX_X0 %08x RX_Y0 %08x\n", RX_X0, RX_Y0); - result[2][cal_num] = RX_X0; - result[3][cal_num] = RX_Y0; - cal_num++; - } else { - PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); - PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x19008c00); - if (++cal_retry >= 10) { - printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); - break; - } - } - } - } - - if (cal_num == 3) { - result_final[0] = get_mean_of_2_close_value(result[0]); - result_final[1] = get_mean_of_2_close_value(result[1]); - result_final[2] = get_mean_of_2_close_value(result[2]); - result_final[3] = get_mean_of_2_close_value(result[3]); - RX0REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX0REG0xe40); - - priv->pshare->RegE94=result_final[0]; - priv->pshare->RegE9C=result_final[1]; - } else { - priv->pshare->RegE94=0x100; - priv->pshare->RegE9C=0x00; - } - - /* - * Fill IQK result for Path A - */ - if (result_final[0]) { - /* - Oldval_0 = (PHY_QueryBBReg(priv, 0xc80, bMaskDWord) >> 22) & 0x3FF; - X = result_final[0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - PHY_SetBBReg(priv, 0xc80, 0x3FF, TX0_A); - PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X* Oldval_0>>7) & 0x1)); - - Y = result_final[1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - TX0_C = (Y * Oldval_0) >> 8; - PHY_SetBBReg(priv, 0xc94, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(priv, 0xc80, 0x003F0000, (TX0_C&0x3F)); - PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y* Oldval_0>>7) & 0x1)); - */ - - // IQK-R03 2011/02/16 update - X = result_final[0]; - Y = result_final[1]; - //printk("X=%x Y=%x\n",X,Y); - //Path-A OFDM_A - PHY_SetBBReg(priv, 0xe30, 0x03FF0000, X); - PHY_SetBBReg(priv, 0xc4c, BIT(24), 0); - //Path-A OFDM_C - PHY_SetBBReg(priv, 0xe30, 0x000003FF, Y); - PHY_SetBBReg(priv, 0xc4c, BIT(26), 0); - - - if(result_final[2]) { - reg = result_final[2]; - PHY_SetBBReg(priv, 0xc14, 0x3FF, reg); - - reg = result_final[3] & 0x3F; - PHY_SetBBReg(priv, 0xc14, 0xFC00, reg); - - reg = (result_final[3] >> 6) & 0xF; - PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); - - PHY_SetBBReg(priv, 0xe34, 0x03FF0000, result_final[2]); // X - PHY_SetBBReg(priv, 0xe34, 0x3FF, result_final[3]); //Y - } - } - - /* - * Path-A PA off - */ - PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); - PHY_SetBBReg(priv, 0x860, bMaskDWord, temp_860); - - /* - * Exit IQK mode - */ - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - PHY_SetBBReg(priv, 0xc04, bMaskDWord, temp_c04); - PHY_SetBBReg(priv, 0xc08, bMaskDWord, temp_c08); - PHY_SetBBReg(priv, 0x874, bMaskDWord, temp_874); - //PHY_SetBBReg(priv, 0x800, bMaskDWord, temp_800); - PHY_SetBBReg(priv, 0xa04, bMaskDWord, temp_a04); - PHY_SetBBReg(priv, 0x88c, bMaskDWord, temp_88c); - PHY_SetBBReg(priv, 0xb30, bMaskDWord, temp_b30); // 03/03/2011 update - //PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032fff); // 01/11/2011 update - - //PHY0 IQ path to DP block - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); - - PHY_SetBBReg(priv, 0xc50, bMaskDWord, 0x50); - PHY_SetBBReg(priv, 0xc50, bMaskDWord, temp_c50); - - /* - * Reload MAC default value - */ - RTL_W8(0x550, temp_550); - RTL_W8(0x551, temp_551); - RTL_W8(0x522, temp_522); - - /* - * Switch back to SI if needed, after IQK - */ - if (switch2PI) { - PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); - PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); - } - - /* - * Reload ADDA power saving parameters - */ - for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) - PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); - - if (!TX0IQKOK) - priv->pshare->IQK_fail_cnt++; -} -#endif - -#ifdef SW_LCK_92D - -#define TARGET_CHNL_NUM_5G 221 -#define TARGET_CHNL_NUM_2G 14 -#define CV_CURVE_CNT 64 - -unsigned int CurveIndex_5G[TARGET_CHNL_NUM_5G]={0}; -unsigned int CurveIndex_2G[TARGET_CHNL_NUM_2G]={0}; - -static unsigned int TargetChnl_5G[TARGET_CHNL_NUM_5G] = { -25141, 25116, 25091, 25066, 25041, -25016, 24991, 24966, 24941, 24917, -24892, 24867, 24843, 24818, 24794, -24770, 24765, 24721, 24697, 24672, -24648, 24624, 24600, 24576, 24552, -24528, 24504, 24480, 24457, 24433, -24409, 24385, 24362, 24338, 24315, -24291, 24268, 24245, 24221, 24198, -24175, 24151, 24128, 24105, 24082, -24059, 24036, 24013, 23990, 23967, -23945, 23922, 23899, 23876, 23854, -23831, 23809, 23786, 23764, 23741, -23719, 23697, 23674, 23652, 23630, -23608, 23586, 23564, 23541, 23519, -23498, 23476, 23454, 23432, 23410, -23388, 23367, 23345, 23323, 23302, -23280, 23259, 23237, 23216, 23194, -23173, 23152, 23130, 23109, 23088, -23067, 23046, 23025, 23003, 22982, -22962, 22941, 22920, 22899, 22878, -22857, 22837, 22816, 22795, 22775, -22754, 22733, 22713, 22692, 22672, -22652, 22631, 22611, 22591, 22570, -22550, 22530, 22510, 22490, 22469, -22449, 22429, 22409, 22390, 22370, -22350, 22336, 22310, 22290, 22271, -22251, 22231, 22212, 22192, 22173, -22153, 22134, 22114, 22095, 22075, -22056, 22037, 22017, 21998, 21979, -21960, 21941, 21921, 21902, 21883, -21864, 21845, 21826, 21807, 21789, -21770, 21751, 21732, 21713, 21695, -21676, 21657, 21639, 21620, 21602, -21583, 21565, 21546, 21528, 21509, -21491, 21473, 21454, 21436, 21418, -21400, 21381, 21363, 21345, 21327, -21309, 21291, 21273, 21255, 21237, -21219, 21201, 21183, 21166, 21148, -21130, 21112, 21095, 21077, 21059, -21042, 21024, 21007, 20989, 20972, -25679, 25653, 25627, 25601, 25575, -25549, 25523, 25497, 25471, 25446, -25420, 25394, 25369, 25343, 25318, -25292, 25267, 25242, 25216, 25191, -25166 }; - -static unsigned int TargetChnl_2G[TARGET_CHNL_NUM_2G] = { // channel 1~14 -26084, 26030, 25976, 25923, 25869, 25816, 25764, -25711, 25658, 25606, 25554, 25502, 25451, 25328 -}; - -void _PHY_CalcCurvIndex(struct rtl8192cd_priv *priv, unsigned int *TargetChnl, - unsigned int *CurveCountVal, char is5G, unsigned int *CurveIndex) -{ - unsigned int smallestABSVal = 0xffffffff, u4tmp; - unsigned char i, j; - unsigned char chnl_num = is5G?(TARGET_CHNL_NUM_5G) : (TARGET_CHNL_NUM_2G); - - - for(i=0; ipmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G? RF92CD_PATH_A:(priv->pmib->dot11RFEntry.macPhyMode==SINGLEMAC_SINGLEPHY?RF92CD_PATH_B:RF92CD_PATH_A); - unsigned int u4tmp = 0; -// unsigned char bNeedPowerDownRadio = FALSE; - unsigned int channel = priv->pshare->RegRF18[eRFPath]&0xff; - //unsigned int channel = PHY_QueryRFReg(priv, eRFPath, rRfChannel, 0xff, 1); - - DEBUG_INFO("====>phy_ReloadLCKSetting interface %d path %d ch %d [0x%05x]\n", priv->pshare->wlandev_idx, eRFPath, channel, priv->pshare->RegRF28[eRFPath]); - - //only for 92D C-cut SMSP - if(GET_CHIP_VER(priv)!=VERSION_8192D -#ifdef CONFIG_RTL_92C_SUPPORT - || IS_TEST_CHIP(priv) -#endif - ) - return; - - if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { - //Path-A for 5G - u4tmp = CurveIndex_5G[channel-1]; - //printk("%s ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n",__FUNCTION__, u4tmp); -#ifdef CONFIG_RTL_92D_DMDP - if(priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx == 1) - { - priv->pshare->RegRF28[RF92CD_PATH_A] = RTL_SET_MASK(priv->pshare->RegRF28[RF92CD_PATH_A],0x3f800,u4tmp,11); //DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, 0x3f800, u4tmp); - DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); - }else -#endif - { - priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],0x3f800,u4tmp,11); //PHY_SetRFReg(priv, eRFPath, 0x28, 0x3f800, u4tmp); - PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); - } - DEBUG_INFO("%s ver 3 set RF-B, 2G, 0x28 = 0x%05x [0x%05x]!!\n", __FUNCTION__, PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1), priv->pshare->RegRF28[eRFPath]); - } - else if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - { - u4tmp = CurveIndex_2G[channel-1]; - //printk("%s ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", __FUNCTION__, u4tmp); -#ifdef CONFIG_RTL_92D_DMDP - if(priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx == 0) - { - priv->pshare->RegRF28[RF92CD_PATH_A] = RTL_SET_MASK(priv->pshare->RegRF28[RF92CD_PATH_A],0x3f800,u4tmp,11); //DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, 0x28, 0x3f800, u4tmp); - DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); - }else -#endif - { - priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],0x3f800,u4tmp,11); // PHY_SetRFReg(priv, eRFPath, 0x28, 0x3f800, u4tmp); - PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); - } - DEBUG_INFO("%s ver 3 set RF-B, 2G, 0x28 = 0x%05x [0x%05x]!!\n", __FUNCTION__, PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1), priv->pshare->RegRF28[eRFPath]); - } - -} - -/* Software LCK */ -void PHY_LCCalibrate_92D(struct rtl8192cd_priv *priv) -{ - unsigned char tmpReg; - unsigned int RF_mode[2]; - unsigned int eRFPath, curMaxRFPath; - unsigned int i; - unsigned int curveCountVal[CV_CURVE_CNT*2]={0}; - unsigned short timeout = 800, timecount = 0; - - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else - curMaxRFPath = RF92CD_PATH_MAX; - - //Check continuous TX and Packet TX - tmpReg = RTL_R8(0xd03); - - if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case - RTL_W8(0xd03, tmpReg&0x8F); // disable all continuous TX - else // Deal with Packet TX case - RTL_W8(TXPAUSE, 0xFF); // block all queues - - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0F); - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - // 1. Read original RF mode - RF_mode[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits, 1); - - // 2. Set RF mode = standby mode - PHY_SetRFReg(priv, eRFPath, 0x00, 0x70000, 0x01); - - // switch CV-curve control by LC-calibration - PHY_SetRFReg(priv, eRFPath, 0x2B, BIT(17), 0x0); - - // jenyu suggest - PHY_SetRFReg(priv, eRFPath, 0x28, BIT(8), 0x1); - - //4. Set LC calibration begin - PHY_SetRFReg(priv, eRFPath, 0x18, BIT(15), 0x01); - - while(!(PHY_QueryRFReg(priv, eRFPath, 0x2A, BIT(11), 1) && - timecount <= timeout)){ - //DEBUG_INFO("PHY_LCK delay for %d ms=2\n", timecount); - delay_ms(50); - timecount+=50; - } - - //u4tmp = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); - - memset((void *)curveCountVal, 0, CV_CURVE_CNT*2); - - //Set LC calibration off - PHY_SetRFReg(priv, eRFPath, 0x18, BIT(15), 0x00); - - // jenyu suggest - PHY_SetRFReg(priv, eRFPath, 0x28, BIT(8), 0x0); - - //save Curve-counting number - for(i=0; i> 5; - - readVal2 = PHY_QueryRFReg(priv, eRFPath, 0x50, 0xffc00, 1); - - curveCountVal[2*i] = (((readVal & 0x1F) << 10) | readVal2); - } - - if(eRFPath == RF92CD_PATH_A -#ifdef CONFIG_RTL_92D_DMDP - && priv->pshare->wlandev_idx == 0 -#endif - ) - _PHY_CalcCurvIndex(priv, TargetChnl_5G, curveCountVal, TRUE, CurveIndex_5G); - else - _PHY_CalcCurvIndex(priv, TargetChnl_2G, curveCountVal, FALSE, CurveIndex_2G); - - // switch CV-curve control mode - PHY_SetRFReg(priv, eRFPath, 0x2B, BIT(17), 0x1); - - // store 0x28 for Reload_LCK - priv->pshare->RegRF28[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); - } - - //Restore original situation - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) - { - PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, RF_mode[eRFPath]); - } - - if((tmpReg&0x70) != 0) - { - //Path-A - RTL_W8(0xd03, tmpReg); - } - else // Deal with Packet TX case - { - RTL_W8(TXPAUSE, 0x00); - } - - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x00); - - phy_ReloadLCKSetting(priv); - -} - -#else -/* Hardware LCK */ -static void PHY_LCCalibrate_92D(struct rtl8192cd_priv *priv) -{ - unsigned char tmpReg; - unsigned int RF_mode[2], tmpu4Byte[2]; - - unsigned int eRFPath, curMaxRFPath; - unsigned char timeout = 800, timecount = 0; - - if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) - curMaxRFPath = RF92CD_PATH_B; - else - curMaxRFPath = RF92CD_PATH_MAX; - - - // Check continuous TX and Packet TX - tmpReg = RTL_R8(0xd03); - - if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case - RTL_W8(0xd03, tmpReg&0x8F); // disable all continuous TX - else // Deal with Packet TX case - RTL_W8(TXPAUSE, 0xFF); // block all queues - - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0F); - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - // 1. Read original RF mode - RF_mode[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits, 1); - - // 2. Set RF mode = standby mode - PHY_SetRFReg(priv, eRFPath, 0x00, 0x70000, 0x01); - - tmpu4Byte[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); - PHY_SetRFReg(priv, eRFPath, 0x28, 0x700, 0x07); - - //4. Set LC calibration begin - PHY_SetRFReg(priv, eRFPath, 0x18, 0x08000, 0x01); - } - - watchdog_kick(); - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - while(!(PHY_QueryRFReg(priv, eRFPath, 0x2A, BIT(11), 1) && - timecount <= timeout)){ - DEBUG_INFO("PHY_LCK delay for %d ms=2\n", timecount); - delay_ms(50); - timecount+=50; - } - } - - for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, tmpu4Byte[eRFPath]); - priv->pshare->RegRF28[eRFPath] = tmpu4Byte[eRFPath]; - PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, RF_mode[eRFPath]); - } - - // Restore original situation - if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case - RTL_W8(0xd03, tmpReg); - else // Deal with Packet TX case - RTL_W8(TXPAUSE, 0x00); - - PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0); - -} - - -#endif //LCK_SW - -#ifdef DPK_92D - -#if 1 //copy from driver of station team -#define RF_AC 0x00 - -#define rPdp_AntA 0xb00 -#define rBndA 0xb30 -#define rPdp_AntB 0xb70 -#define rBndB 0xba0 - -#define RF_MODE1 0x10 -#define RF_MODE2 0x11 - -#define rTxAGC_A_CCK11_2_B_CCK11 0x86c - -#define RF_TX_G3 0x22 - -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C -#define RF_TRSW 0x3F - -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B - -#define RF_IQADJ_G1 0x01 -#define RF_IQADJ_G2 0x02 -#define RF_BS_PA_APSET_G1_G4 0x03 -#define RF_BS_PA_APSET_G5_G8 0x04 -#define RF_POW_TRSW 0x05 - -#define DP_OFFSET_NUM 9 -#define DP_AP_CUREVE_SELECT_NUM 3 -#define DP_gain_loss 1 -#define DP_PA_BIAS_NUM 4 - -#define rTxAGC_B_CCK5_1_Mcs32 0x838 - -#define RF_TXBIAS 0x16 -#endif - -#define DPK_DEBUG(fmt,args...) - -#define DP_BB_REG_NUM 7 -//#define DP_BB_REG_NUM_A 11 -//#define DP_BB_REG_NUM_B 10 -#define DP_BB_REG_NUM_A 10 -#define DP_BB_REG_NUM_B 9 - -#define DP_BB_REG_NUM_settings 6 -#define DP_BB_REG_NUM_loop 30 -#define DP_BB_REG_NUM_loop_tx 12 -#define DP_BB_REG_NUM_loop_rx 8 -#define DP_BB_REG_NUM_loop_pa 4 -#define DP_RF_REG_NUM 4 -#define DP_SRAM_NUM 16 -//#define DP_SRAM_NUM_db 22 -#define DP_SRAM_NUM_db 86 - -#define DP_PATH_NUM 2 -#define DP_PA_MODEL_NUM 32 -#define DP_PA_MODEL_RUN_NUM 8 -#define DP_PA_MODEL_PER_RUN_NUM 4 -#define DP_RETRY_LIMIT 10 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 -#if 1 -#define DP_GAIN_LOSS_BOUND_NUM 14 -#else -#define DP_GAIN_LOSS_BOUND_NUM 8 -#endif -#define DP_OFFSET_NUM 9 -//#define DP_AP_CUREVE_SELECT_NUM 2 // 3 -#define DP_gain_loss 1 - - -void rtl8192cd_DPK_timer(unsigned long task_priv) -{ - struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; - - if (!(priv->drv_state & DRV_STATE_OPEN)) - return; - - if (priv->pshare->pwr_trk_ongoing){ - DPK_DEBUG("==>_PHY_DigitalPredistortion() TxPowerTrackingInProgress() delay 100ms\n"); - mod_timer(&priv->pshare->DPKTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); - }else{ - PHY_DPCalibrate(priv); - } -} - -void _PHY_DPK_polling(struct rtl8192cd_priv *priv) -{ - unsigned int delaycount = 0, delaybound = 30, delay = 800; - unsigned int u4tmp; - - delaycount = 0; - - do{ - delay_us(delay); - - u4tmp = PHY_QueryBBReg(priv, 0xdf4, bMaskDWord); - //RTPRINT(FINIT, INIT_IQK, ("0xdf4 = 0x%x, delay %d us\n", u4tmp, delaycount*delay+800)); - delaycount++; - delay = 100; - u4tmp = (u4tmp & BIT(26)) >> 26; - }while(u4tmp == 0x01 && delaycount < delaybound); - -} - -// if AP curve check fail return FALSE -int _PHY_DPK_AP_curve_check(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned int RegiesterNum) -{ - unsigned int PA_power_temp[DP_PA_MODEL_NUM], i = 0, index = 5, - base = 532, ref1, ref2; - int power_I, power_Q; - - //store I, Q - - for(i = 0; i < DP_PA_MODEL_NUM; i++){ - power_I = (PA_power[i] >> 8); - if(power_I & BIT(7)) - power_I |= bMaskH3Bytes; - - power_Q = PA_power[i] & bMaskByte0; - if(power_Q & BIT(7)) - power_Q |= bMaskH3Bytes; - - PA_power_temp[i] = power_I*power_I+power_Q*power_Q; - } - - ref1 = PA_power_temp[0]; - for(i = 0; i < index; i++) - ref1 = (ref1 > PA_power_temp[i])?ref1:PA_power_temp[i]; - - ref2 = PA_power_temp[index]; - for(i = index; i < index*2; i++) - ref2 = (ref2 > PA_power_temp[i])?ref2:PA_power_temp[i]; - - DPK_DEBUG("==>_PHY_DPK_AP_cureve_check ref1 = 0x%x ref2 = 0x%x\n", ref1, ref2); - - if(ref1 == 0) - return FALSE; - - return ((ref2 << 9)/ref1) < base; -} - -// if DPK fail return FALSE -int _PHY_DPK_check(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned int RegiesterNum) -{ - unsigned int base = 407, PA_power_temp[2], i = 0; - int power_I, power_Q; - - while(i ==0 || i == (RegiesterNum-1)) - { - power_I = (PA_power[i] >> 8); - if(power_I & BIT(7)) - power_I |= bMaskH3Bytes; - - power_Q = PA_power[i] & bMaskByte0; - if(power_Q & BIT(7)) - power_Q |= bMaskH3Bytes; - - PA_power_temp[i==0?0:1] = power_I*power_I+ power_Q*power_Q; - - DPK_DEBUG("==>_PHY_DPK_check pa_power_temp[%d] 0x%x\n", i, PA_power_temp[i==0?0:1]); - - if(i == 0) - i = RegiesterNum -1; - else if (i == RegiesterNum -1) - break; - } - - //normalization - if(PA_power_temp[0] == 0) - return TRUE; - else - return (((PA_power_temp[1] << 9) /PA_power_temp[0]) <= base); - -} - -int _PHY_Find_Tx_Power_Index(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned char path, unsigned char bPlus3db, char bDecreaseTxIndex, unsigned char *tx_index_out) -{ - unsigned char i, tx_index = bDecreaseTxIndex?0x0f:0x15; - unsigned int tmpReg[11], tmpBase, RegNum = 11, base = /*323*/256; - unsigned int PA_power_normal[11]; -// unsigned int check_base =bPlus3db?(400-base):(323-base); - unsigned int check_base =bPlus3db?400:323; - - int power_I, power_Q; - int index = -1; - - DPK_DEBUG("==>tx_index minus %d bplus3db %d\n", base, bPlus3db); - - _PHY_DPK_polling(priv); - - if(path == RF92CD_PATH_A) - { - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017018); - tmpReg[0] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); - tmpReg[1] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017019); - tmpReg[2] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); - tmpReg[3] = PHY_QueryBBReg(priv, 0xbe0, bMaskDWord); - tmpReg[4] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701a); - tmpReg[5] = PHY_QueryBBReg(priv, 0xbe0, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701b); - tmpReg[6] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); - tmpReg[7] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701c); - tmpReg[8] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701e); - tmpReg[9] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); - - PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701f); - tmpReg[10] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); - - //RTPRINT(FINIT, INIT_IQK, ("==>_PHY_Find_Tx_Power_Index path A\n")); - - } - else if(path == RF92CD_PATH_B) - { - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017018); - tmpReg[0] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); - tmpReg[1] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017019); - tmpReg[2] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); - tmpReg[3] = PHY_QueryBBReg(priv, 0xbf0, bMaskDWord); - tmpReg[4] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701a); - tmpReg[5] = PHY_QueryBBReg(priv, 0xbf4, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701b); - tmpReg[6] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); - tmpReg[7] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701c); - tmpReg[8] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701e); - tmpReg[9] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); - - PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701f); - tmpReg[10] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); - - //RTPRINT(FINIT, INIT_IQK, ("==>_PHY_Find_Tx_Power_Index path B\n")); - - } - - for(i = 0; i < RegNum; i++) - { - power_I = (tmpReg[i] >> 8); - if(power_I & BIT(7)) - power_I |= bMaskH3Bytes; - - power_Q = tmpReg[i] & bMaskByte0; - if(power_Q & BIT(7)) - power_Q |= bMaskH3Bytes; - - PA_power[i] = power_I*power_I+ power_Q*power_Q; - } - - //normalization - tmpBase = PA_power[0]; - //RTPRINT(FINIT, INIT_IQK, ("==>PA_power START normalized\n")); - - if(tmpBase == 0) - DPK_DEBUG("==>PA_power[0] is ZERO !!!!!\n"); - - for(i = 0; i < RegNum; i++) - { - if(tmpBase != 0) - PA_power[i] = (PA_power[i] << 9) /tmpBase; - else - PA_power[i] = (PA_power[i] << 9) ; - PA_power_normal[i] = PA_power[i]; - PA_power[i] = (PA_power[i] > base)?(PA_power[i] - base):(base - PA_power[i]); - DPK_DEBUG("==>PA_power normalized index %d value 0x%x\n", i, PA_power[i]); - } - - //choose min for TX index to do DPK - base = bMaskDWord; - for(i = 0; i < RegNum; i++) - { - if(PA_power[i] < base) - { - base = PA_power[i]; - index = i; - } - } - - if(index == -1) - { - tx_index = 0x1c; - index = 0x1f - tx_index; - } - else - { - tx_index += index; - } - - DPK_DEBUG("==>tx_index result 0x%x PA_power[%d] = 0x%x\n", tx_index, index, PA_power[index]); - - *tx_index_out = tx_index; - - //Check pattern reliability - if(((PA_power_normal[index] > check_base) && (tx_index == 0x1f)) || - ((PA_power_normal[10] > base) && (!bPlus3db)) || - ((tx_index < 0x1a) && (!bPlus3db)) || - ((tx_index < 0x13) && (bDecreaseTxIndex)) - ) - return FALSE; - else - return TRUE; -// return tx_index; - -} - -unsigned char _PHY_Find_Rx_Power_Index(struct rtl8192cd_priv *priv, unsigned char tx_index, unsigned char rx_index, unsigned char path, char *bDecreaseTxIndex) -{ -// u1Byte rx_index = 0x04; - unsigned int tmpReg; - int power_I, power_Q, tmp; - unsigned char bPlus = FALSE, bMinus = FALSE; - unsigned short offset[2][2] = {{ //path, offset - 0xb28, 0xbe8},{ - 0xb98, 0xbf8}}; - int round = 0; - - while (TRUE) { - tmpReg = 0x52000 | tx_index | (rx_index << 5); - PHY_SetRFReg(priv, path, RF_AC, bMask20Bits, tmpReg); - //RTPRINT(FINIT, INIT_IQK, ("==>RF 0ffset 0 = 0x%x readback = 0x%x\n", tmpReg, - //PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); - - //----send one shot signal----// - PHY_SetBBReg(priv, offset[path][0], bMaskDWord, 0x80080000); //0xb28, 0xb98 - PHY_SetBBReg(priv, offset[path][0], bMaskDWord, 0x00080000); - - _PHY_DPK_polling(priv); - - tmpReg = PHY_QueryBBReg(priv, offset[path][1], bMaskDWord); - power_I = ((tmpReg & bMaskByte1) >> 8); - power_Q = tmpReg & bMaskByte0; - - if(power_I & BIT(7)) - { - power_I |= bMaskH3Bytes; - power_I = 0-power_I; //absolute value - } - - if(power_Q & BIT(7)) - { - power_Q |= bMaskH3Bytes; - power_Q = 0-power_Q; - } - //RTPRINT(FINIT, INIT_IQK, ("==>rx_index 0x%x I = 0x%x Q = 0x%x offset 0xbe8 = 0x%x\n", rx_index, power_I, power_Q, tmpReg)); - - tmp = (power_I > power_Q)? power_I:power_Q; - -#if 0 - if((rx_index == 0 && tmp > 0x6f)||(rx_index == 31 && tmp < 0x50)) - break; -#endif - - if((tmp<= 0x6f && tmp >= 0x50) ) - { - break; - } - else if(tmp < 0x50) - { - bPlus = TRUE; - if(bMinus) - { - rx_index++; - break; - } -// rx_index++; - rx_index += 2; - } - else if (tmp > 0x6f) - { - bMinus = TRUE; - if(bPlus) - { - rx_index--; - break; - } -// rx_index--; - rx_index -= 2; - } - - if(rx_index == 0 || rx_index == 31) - break; - - if (++round > 10000) { - panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); - break; - } - } - if(rx_index == 0 && tmp > 0x6f) - *bDecreaseTxIndex = TRUE; - - DPK_DEBUG("==>rx_index FINAL 0x%x I = 0x%x Q = 0x%x\n", rx_index, power_I, power_Q); - - return rx_index; - -} - -void PHY_DPCalibrate(struct rtl8192cd_priv *priv) -{ - char is2T = ((priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) ?1 :0); - - unsigned int tmpReg, value32/*, checkbit*/; - unsigned int AFE_backup[IQK_ADDA_REG_NUM]; - static unsigned int AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, 0xe6c, 0xe70, 0xe74, 0xe78, - 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, - 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, - 0xeec}; - - static unsigned int BB_backup[DP_BB_REG_NUM]; - static unsigned int BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_AnalogParameter4, rFPGA0_XAB_RFInterfaceSW, - rTxAGC_B_CCK11_A_CCK2_11 - }; - - static unsigned int BB_backup_A[DP_BB_REG_NUM_A]; - static unsigned int BB_REG_A[DP_BB_REG_NUM_A] = { - rFPGA0_XA_RFInterfaceOE, rTxAGC_A_Rate18_06, - rTxAGC_A_Rate54_24, rTxAGC_A_CCK1_Mcs32, - 0xe0c, rTxAGC_A_Mcs03_Mcs00, - rTxAGC_A_Mcs07_Mcs04, rTxAGC_A_Mcs11_Mcs08, - rTxAGC_A_Mcs15_Mcs12, rOFDM0_XAAGCCore1/*, - rBndA*/ - }; - - - static unsigned int BB_backup_B[DP_BB_REG_NUM_B]; - static unsigned int BB_REG_B[DP_BB_REG_NUM_B] = { - rFPGA0_XB_RFInterfaceOE, rTxAGC_B_Rate18_06, - rTxAGC_B_Rate54_24, rTxAGC_B_CCK1_55_Mcs32, - rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, - rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12, - rOFDM0_XBAGCCore1 /*, rBndB*/ - }; - - static unsigned int BB_settings[DP_BB_REG_NUM_settings] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0xccf000c0/*, 0x07600760*/}; - - static unsigned int BB_REG_loop[DP_PATH_NUM][DP_BB_REG_NUM_loop] = { - {0xb00, 0xb04, 0xb28, 0xb68, - 0xb08, 0xb0c, 0xb10, 0xb14, - 0xb18, 0xb1c, 0xb20, 0xb24, - 0xe28, 0xb00, 0xb04, 0xb08, - 0xb0c, 0xb10, 0xb14, 0xb18, - 0xb1c, 0xb20, 0xb24, 0xb28, - 0xb2c, rBndA, 0xb34, 0xb38, - 0xb3c, 0xe28}, - {0xb70, 0xb74, 0xb98, 0xb6C, - 0xb78, 0xb7c, 0xb80, 0xb84, - 0xb88, 0xb8c, 0xb90, 0xb94, - 0xe28, 0xb60, 0xb64, 0xb68, - 0xb6c, 0xb70, 0xb74, 0xb78, - 0xb7c, 0xb80, 0xb84, 0xb88, - 0xb8c, 0xb90, 0xb94, 0xb98, - 0xb9c, 0xe28} - }; - - static unsigned int BB_settings_loop[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x41382e21, 0x5b554f48, 0x6f6b6661, 0x817d7874, - 0x908c8884, 0x9d9a9793, 0xaaa7a4a1, 0xb6b3b0ad, - 0x40000000, 0x7d327c18, 0x7e057db3, 0x7e5f7e37, - 0x7e967e7c, 0x7ebe7eac, 0x7ed77ecc, 0x7eee7ee4, - 0x7f017ef9, 0x7f0e7f07, 0x7f1c7f15, 0x7f267f20, - 0x7f2f7f2a, 0x7f377f34, 0x7f3e7f3b, 0x7f457f42, - 0x7f4b7f48, 0x00000000 - }; - - static unsigned int BB_settings_loop_3db[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x5b4e402e, 0x7f776f65, 0x9c968f88, 0xb5afa8a3, - 0xcac4bfb9, 0xdcd8d4ce, 0xeeeae6e2, 0xfffbf7f2, - 0x40000000, 0x7dfe7d32, 0x7e967e59, 0x7ed77eba, - 0x7efd7eeb, 0x7f1a7f0e, 0x7f2d7f25, 0x7f3c7f36, - 0x7f4a7f44, 0x7f547f4e, 0x7f5d7f58, 0x7f657f60, - 0x7f6a7f68, 0x7f717f6e, 0x7f767f73, 0x7f7b7f78, - 0x7f7f7f7d, 0x00000000 - }; - - static unsigned int BB_settings_loop_tx[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x21212121, 0x21212121, 0x21212121, 0x21212121, - 0x21212121, 0x21212121, 0x21212121, 0x21212121, - 0x40000000, 0x7c187c18, 0x7c187c18, 0x7c187c18, - 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, - 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, - 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, - 0x7c187c18, 0x00000000 - }; - - static unsigned int BB_settings_loop_tx_3db[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, - 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, - 0x40000000, 0x7d327d32, 0x7d327d32, 0x7d327d32, - 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, - 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, - 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, - 0x7d327d32, 0x00000000 - }; - - - //for find 2dB loss point - static unsigned int BB_settings_loop_tx_2[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x41382e21, 0x5b554f48, 0x6f6b6661, 0x817d7874, - 0x908c8884, 0x9d9a9793, 0xaaa7a4a1, 0xb6b3b0ad, - 0x40000000, 0x7d327c18, 0x7e057db3, 0x7e5f7e37, - 0x7e967e7c, 0x7ebe7eac, 0x7ed77ecc, 0x7eee7ee4, - 0x7f017ef9, 0x7f0e7f07, 0x7f1c7f15, 0x7f267f20, - 0x7f2f7f2a, 0x7f377f34, 0x7f3e7f3b, 0x7f457f42, - 0x7f4b7f48, 0x00000000 - }; - - //for find 2dB loss point - static unsigned int BB_settings_loop_tx_2_3db[DP_BB_REG_NUM_loop] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x5b4e402e, 0x7f776f65, 0x9c968f88, 0xb5afa8a3, - 0xcac4bfb9, 0xdcd8d4ce, 0xeeeae6e2, 0xfffbf7f2, - 0x40000000, 0x7dfe7d32, 0x7e967e59, 0x7ed77eba, - 0x7efd7eeb, 0x7f1a7f0e, 0x7f2d7f25, 0x7f3c7f36, - 0x7f4a7f44, 0x7f547f4e, 0x7f5d7f58, 0x7f657f60, - 0x7f6a7f68, 0x7f717f6e, 0x7f767f73, 0x7f7b7f78, - 0x7f7f7f7d, 0x00000000 - }; - - - static unsigned int BB_settings_loop_rx[DP_BB_REG_NUM_loop_rx] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x21212121, 0x40000000, 0x7c187c18, 0x00000000 - }; - - static unsigned int BB_settings_loop_rx_3db[DP_BB_REG_NUM_loop_rx] = { - 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, - 0x2e2e2e2e, 0x40000000, 0x7d327d32, 0x00000000 - }; - - static unsigned int BB_settings_loop_pa[DP_BB_REG_NUM_loop_pa] = { - 0x02096eb8, 0xf76d9f84, 0x00044499, 0x02880140 - }; - - static unsigned int BB_settings_loop_dp[DP_BB_REG_NUM_loop_pa] = { - 0x01017098, 0x776d9f84, 0x00000000, 0x08080000 - }; - - unsigned int *BB_settings_temp; - - static unsigned char Sram_db_settings[DP_SRAM_NUM_db] = { - 0xfe, 0xf0, 0xe3, 0xd6, 0xca, - 0xbf, 0xb4, 0xaa, 0xa0, 0x97, - 0x8f, 0x87, 0x7f, 0x78, 0x71, - 0x6b, 0x65, 0x5f, 0x5a, 0x55, - 0x50, 0x4c, 0x47, 0x43, 0x40, - 0x3c, 0x39, 0x35, 0x32, 0x2f, - 0x2d, 0x2a, 0x28, 0x26, 0x23, - 0x21, 0x20, 0x1e, 0x1c, 0x1a, - 0x19, 0x18, 0x16, 0x16, 0x14, - 0x13, 0x12, 0x11, 0x10, 0x0f, - 0x0e, 0x0d, 0x0c, 0x0c, 0x0b, - 0x0a, 0x0a, 0x09, 0x09, 0x08, - 0x08, 0x07, 0x07, 0x06, 0x06, - 0x06, 0x05, 0x05, 0x05, 0x04, - 0x04, 0x04, 0x04, 0x03, 0x03, - 0x03, 0x03, 0x03, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, - 0x01 - }; - - //unsigned int pwsf[DP_SRAM_NUM]; - - static unsigned int offset[2][DP_OFFSET_NUM] = {{ //path, offset - 0xe34, 0xb28, 0xb00, 0xbdc, 0xbc0, - 0xbe8, rOFDM0_XATxIQImbalance, rBndA, - 0xb68},{ - 0xe54, 0xb98, 0xb70, 0xbec, 0xbc4, - 0xbf8, rOFDM0_XBTxIQImbalance, rBndB, - 0xb6c}}; - - //unsigned char OFDM_min_index = 6, OFDM_min_index_internalPA = 3; - unsigned char OFDM_index[2]; - //unsigned char retrycount = 0, retrybound = 1; - - unsigned int RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - static unsigned int RF_REG[DP_RF_REG_NUM] = { - RF_TX_G3, RF_TXPA_A4, RF_RXRF_A3, - RF_BS_PA_APSET_G1_G4/*, RF_BS_PA_APSET_G5_G8, - RF_BS_PA_APSET_G9_G11*/}; - - static unsigned int RF_AP_curve_select[DP_AP_CUREVE_SELECT_NUM] = { - 0x7bdef, 0x94a52, 0xa5294/*, 0xb5ad6*/ }; - - static unsigned int RF_PA_BIAS[3][DP_PA_BIAS_NUM] = {{ //40MHz / 20MHz, original - 0xe189f, 0xa189f, 0x6189f, 0x2189f },{ - 0xe087f, 0xa087f, 0x6087f, 0x2087f },{ - 0xe1874, 0xa1874, 0x61874, 0x21874}}; - - unsigned int PA_model_backup[DP_PATH_NUM][DP_PA_MODEL_NUM]; - - unsigned int PA_power[DP_PATH_NUM][DP_PA_MODEL_RUN_NUM*2]; - -#if DP_gain_loss == 1 - - int power_I, power_Q, coef; - - int gain_loss_backup[DP_PATH_NUM][DP_PA_MODEL_NUM]; //I,Q - - static unsigned int gain_loss_bound[DP_GAIN_LOSS_BOUND_NUM] = { - 63676, 60114 , 56751 , 53577 , 49145, - 47750, 45079 , 42557 , 40177 , 37929 , - 35807 , 33804 , 31913, 30128 - }; - - static int gain_loss_coef[DP_GAIN_LOSS_BOUND_NUM+1] = { - 512, 527, 543, 558, 573, - 589, 609, 625, 645, 666, - 681, 701, 722, 742, 768 - }; - -// BOOLEAN bNegative = FALSE; -// unsigned char index_for_zero_db = 24, AP_curve_index = 0; - unsigned char GainLossIndex = 0; //0db, 0x40 - char SramIndex = 24; - unsigned char /*index_for_zero_db = 6,*/ AP_curve_index = 0; - -#else - - unsigned char index_for_zero_db = 6, AP_curve_index = 0; - int power_I, power_Q; - static unsigned int gain_loss_bound[DP_GAIN_LOSS_BOUND_NUM] = { - 61870, 55142, 49145, 43801, 39037, - 34792, 31008, 27636 - }; -#endif - - unsigned int MAC_backup[IQK_MAC_REG_NUM]; - static unsigned int MAC_REG[IQK_MAC_REG_NUM] = { - 0x522, 0x550, 0x551, 0x040}; - - //unsigned int AFE_on_off[PATH_NUM] = { - // 0x04db25a4, 0x0b1b25a4}; //path A on path B path A off path B on - - unsigned char path_num, /*path_bound,*/ path = RF92CD_PATH_A, i, j, tx_index, rx_index; - int index, index_1, index_repeat; - - char bInternalPA = FALSE; -#if (DP_gain_loss != 1) - char SkipStep5 = FALSE; -#endif - char bPlus3db = FALSE, bDecreaseTxIndex = FALSE, bDecreaseTxIndexWithRx = FALSE; - -#ifdef DFS - if ((priv->pshare->rf_ft_var.dfsdelayiqk) && - (OPMODE & WIFI_AP_STATE) && - !priv->pmib->dot11DFSEntry.disable_DFS && - (timer_pending(&priv->ch_avail_chk_timer) || - priv->pmib->dot11DFSEntry.disable_tx)) - return; -#endif - - DPK_DEBUG("==>_PHY_DigitalPredistortion() interface index %d is2T = %d\n", priv->pshare->wlandev_idx, is2T); //anchin - - DPK_DEBUG("_PHY_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R")); - - DPK_DEBUG("==>_PHY_DigitalPredistortion() current thermal meter = 0x%x PG thermal meter = 0x%x bPlus3db %d\n", - priv->pshare->ThermalValue_DPKtrack, priv->pmib->dot11RFEntry.ther, bPlus3db); - - if ((priv->pmib->dot11RFEntry.phyBandSelect!= PHY_BAND_5G)||(GET_CHIP_VER(priv)!=VERSION_8192D)) - return; - - bInternalPA = priv->pshare->rf_ft_var.use_intpa92d; - - if(!is2T) - path_num = 1; - else - path_num = 2; - - if(!bInternalPA) { - DPK_DEBUG("==>_PHY_DigitalPredistortion() NOT internal5G\n"); - return; - } - - if(priv->pshare->pwr_trk_ongoing){ - DPK_DEBUG("==>_PHY_DigitalPredistortion() TxPowerTrackingInProgress() delay 100ms\n"); - mod_timer(&priv->pshare->DPKTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); - return; - } - - OFDM_index[RF92CD_PATH_A] = priv->pshare->OFDM_index[RF92CD_PATH_A]; - OFDM_index[RF92CD_PATH_B] = priv->pshare->OFDM_index[RF92CD_PATH_B]; - - DPK_DEBUG("original index 0x%x \n", priv->pshare->OFDM_index[0]); - - priv->pshare->bDPKworking = TRUE; - - //save global setting - //save BB default value - _PHY_SaveADDARegisters(priv, BB_REG, BB_backup, DP_BB_REG_NUM); - - //save MAC default value - _PHY_SaveMACRegisters(priv, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(priv, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - //save path A default value - //save path A BB default value - _PHY_SaveADDARegisters(priv, BB_REG_A, BB_backup_A, DP_BB_REG_NUM_A); - - //save path B BB default value - if(is2T) - _PHY_SaveADDARegisters(priv, BB_REG_B, BB_backup_B, DP_BB_REG_NUM_B); - - //save pathA/B RF default value - for(path=0; pathInternalPA5G[path]) - //continue; - - if(path == RF92CD_PATH_B) - { - //BB pah A register setting:fix TRSW to TX;external LNA off - if(!bInternalPA) - { - PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x0f600f60); - PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, ~(BIT8|BIT9), 0x66e60230); - } - else - { - PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07600760); - PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, ~(BIT8|BIT9), 0x66e60230); - } - PHY_SetBBReg(priv, rBndA, 0xF00000, 0x0a); - - //BB pah B register setting:fix TRSW to TX;external LNA off - if(is2T) - { - if(!bInternalPA) - { - PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x0f600f60); - PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, bMaskDWord, 0x061f0930); - } - else - { - PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07600760); - PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, bMaskDWord, 0x061f0130); - } - PHY_SetBBReg(priv, rBndB, 0xF00000, 0x0a); - } - } - - AP_curve_index = 1; - rx_index = 0x06; - bPlus3db = FALSE; - bDecreaseTxIndex = FALSE; - - if(path == RF92CD_PATH_A) - { - _PHY_PathADDAOn(priv, AFE_REG, TRUE, is2T); - } - else - { - _PHY_PathADDAOn(priv, AFE_REG, FALSE, is2T); - } - - if(path == RF92CD_PATH_B) - PHY_SetBBReg(priv, rFPGA1_DebugSelect, bMaskDWord, 0x00000303); - - //path A/B RF setting - //internal lopback off - if(path == RF92CD_PATH_A && !bInternalPA) - { - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x5007f); - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x6f1f9); - } - else if(path == RF92CD_PATH_B) - { - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x1000f); - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x60103); - } - - PHY_SetRFReg(priv, path, RF_RXRF_A3, bMask20Bits, 0xef456); - - //Path A/B to standby mode - PHY_SetRFReg(priv, path==RF92CD_PATH_A?RF92CD_PATH_B:RF92CD_PATH_A, - RF_AC, bMask20Bits, 0x10000); - - //set DPK PA bias table - index = priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40?0:1; - if(path == RF92CD_PATH_A) - { - for(i = 0; i < path_num; i++) - { - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, i, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[index][j]); - } - } - -Step1: - - DPK_DEBUG("==>AP curve select 0x%x bplus3db %d path%s!!\n", RF_AP_curve_select[AP_curve_index], bPlus3db, path==RF92CD_PATH_A?"A":"B"); - - //RF setting for AP curve selection - //default AP curve = 15 - PHY_SetRFReg(priv, path, RF_BS_PA_APSET_G1_G4, bMask20Bits, RF_AP_curve_select[AP_curve_index]); - - ////////////////////////////////////////////////// - // step 1: find RF TX/RX index - ///////////////////////////////////////////////// - //find RF TX index - //============================= - // PAGE_B for Path-A PM setting - //============================= - // open inner loopback @ b00[19]:od 0xb00 0x01097018 - if(bPlus3db) - BB_settings_temp = &(BB_settings_loop_tx_3db[0]); - else - BB_settings_temp = &(BB_settings_loop_tx[0]); - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); - - if(bDecreaseTxIndex) - tx_index = 0x19; - else - tx_index = 0x1f; - bDecreaseTxIndexWithRx = FALSE; - - //Set Tx GAC = 0x1f, than find Rx AGC - rx_index = _PHY_Find_Rx_Power_Index(priv, tx_index, rx_index, path, &bDecreaseTxIndexWithRx); - if(bDecreaseTxIndexWithRx) - { - if(bDecreaseTxIndex) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 - PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c - - for(i = 3; i < DP_RF_REG_NUM; i++) - PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); - - //set original DPK bias table - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); - continue; - } - else - { - bDecreaseTxIndex = TRUE; - goto Step1; - } - } - - //find 2dB loss point - //============================= - // PAGE_B for Path-A PM setting - //============================= - // open inner loopback @ b00[19]:od 0xb00 0x01097018 - if(bPlus3db) - BB_settings_temp = &(BB_settings_loop_tx_2_3db[0]); - else - BB_settings_temp = &(BB_settings_loop_tx_2[0]); - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); - - //RF setting - PHY_SetRFReg(priv, path, RF_AC, bMask20Bits, 0x52000 | tx_index | (rx_index << 5)); - - //----send one shot signal----// - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80080000); //0xb28, 0xb98 - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00080000); - - //get power - if(!_PHY_Find_Tx_Power_Index(priv, PA_power[path], path, bPlus3db, bDecreaseTxIndex, &tx_index)) - { - if(/*tx_index == 0x1f &&*/ !bPlus3db) - { - if(bDecreaseTxIndex) - { - if(tx_index < 0x11) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 - PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c - - for(i = 3; i < DP_RF_REG_NUM; i++) - PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); - - //set original DPK bias table - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); - - continue; - } - else - { - //RTPRINT(FINIT, INIT_IQK, ("==>Check pattern reliability path%s SUCCESS tx_index = 0x1b!!!!\n", path==RF90_PATH_A?"A":"B")); - } - } - else if(tx_index < 0x1a) - { - bDecreaseTxIndex = TRUE; - goto Step1; - } - else - { - bPlus3db = TRUE; - goto Step1; - } - } - else if(tx_index == 0x1f) - { - DPK_DEBUG("==>Check pattern reliability path%s FAIL!!!!\n", path==RF92CD_PATH_A?"A":"B"); - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 - PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c - - for(i = 3; i < DP_RF_REG_NUM; i++) - PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); - - //set original DPK bias table - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); - - continue; - } - - - } - else - { - DPK_DEBUG("==>Check pattern reliability path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); - } - - //find RF RX index - //============================= - // PAGE_B for Path-A PM setting - //============================= - // open inner loopback @ b00[19]:od 0xb00 0x01097018 - if(bPlus3db) - BB_settings_temp = &(BB_settings_loop_rx_3db[0]); - else - BB_settings_temp = &(BB_settings_loop_rx[0]); - - for(i = 0; i < 4; i++) - PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[i]); - for(; i < 12; i++) - PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[4]); - PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[5]); - for(; i < 29; i++) - PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[6]); - PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[7]); - - rx_index = _PHY_Find_Rx_Power_Index(priv, tx_index, rx_index, path, &bDecreaseTxIndex); - - ////////////////////////////////////// - //2.measure PA model - ////////////////////////////////////// - //========================================= - //PAGE_B for Path-A PAS setting //========================================= - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - if(bPlus3db) - BB_settings_temp = &(BB_settings_loop_3db[0]); - else - BB_settings_temp = &(BB_settings_loop[0]); - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); - - //LNA VDD to gnd - PHY_SetRFReg(priv,path, RF_AC, bMask20Bits, 0x52000 | tx_index | (rx_index << 5)); - - //----send one shot signal----// - // Path A - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80080000); //0xb28, 0xb98 - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00080000); - - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER, BIT17|BIT16, 0x03); - - _PHY_DPK_polling(priv); - - priv->pshare->ThermalValue_DPKstore = (unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, 0xf800, 1); //0x42: RF Reg[15:11] 92D - - // read PA model and save to PA_model_A[32] - for(i = 0; i < DP_PA_MODEL_RUN_NUM; i++) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017018+i); //0xb00, 0xb70 - for(index = 0; index < DP_PA_MODEL_PER_RUN_NUM; index++) - { - PA_model_backup[path][i*4+index] = PHY_QueryBBReg(priv, offset[path][3]+index*4, bMaskDWord); //0xbdc, 0xbec - DPK_DEBUG("==>PA_model_backup index %d value 0x%x()\n", i*4+index, PA_model_backup[path][i*4+index]); - } - } - -#if 0 - //find appropriate AP curve - if(AP_curve_index != (DP_AP_CUREVE_SELECT_NUM-1)) - { - if(!_PHY_DPK_AP_curve_check(priv, PA_model_backup[path], DP_PA_MODEL_NUM)) - { - DPK_DEBUG("==>find appropriate AP curve 0x%x path%s FAIL!!!!\n", RF_AP_curve_select[AP_curve_index], path==RF92CD_PATH_A?"A":"B"); - AP_curve_index++; - if(AP_curve_index < DP_AP_CUREVE_SELECT_NUM) - goto Step1; - } - else - { - DPK_DEBUG("==>find appropriate AP curve path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); - } - } -#endif - - //check PA model - if(!_PHY_DPK_check(priv, PA_model_backup[path], DP_PA_MODEL_NUM)) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); // add in 2011-06-02 - PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c - - for(i = 3; i < DP_RF_REG_NUM; i++) - PHY_SetRFReg(priv, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); - DPK_DEBUG("==>PA model path%s FAIL!!!!\n", path==RF92CD_PATH_A?"A":"B"); - priv->pshare->bDPKdone[path] = FALSE; - //set original DPK bias table - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); - - continue; - } - else - { - DPK_DEBUG("==>PA model path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); -// priv->pshare->bDPKdone[path] = TRUE; -// priv->pshare->bDPKstore = TRUE; - } - - ///////////////////////////////////////////////////////////////////////////////////////////////////// - // step 3: fill PA model to DP Calibration - ///////////////////////////////////////////////////////////////////////////////////////////////////// - //fill BB TX index for the DPK reference - DPK_DEBUG("==>fill PA model to DP Calibration\n"); - - if(path == RF92CD_PATH_A){ - for(index = 0; index < DP_PA_MODEL_RUN_NUM; index++){ - if(index != 3){ - PHY_SetBBReg(priv, 0xe00+index*4, bMaskDWord, 0x3c3c3c3c); - } else { - PHY_SetBBReg(priv, 0xe00+index*4, bMaskDWord, 0x03903c3c); - } - } - PHY_SetBBReg(priv, 0x86c, bMaskDWord, 0x3c3c3c3c); - }else if (path == RF92CD_PATH_B){ - for(index = 0; index < 4; index++) { - PHY_SetBBReg(priv, 0x830+index*4, bMaskDWord, 0x3c3c3c3c); - } - for(index = 0; index < 2; index++) { - PHY_SetBBReg(priv, 0x848+index*4, bMaskDWord, 0x3c3c3c3c); - } - for(index = 0; index < 2; index++) { - PHY_SetBBReg(priv, 0x868+index*4, bMaskDWord, 0x3c3c3c3c); - } - } - - // SRAM boundary setting - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); - - if(priv->pshare->phw->bNewTxGainTable) - PHY_SetBBReg(priv, offset[path][4], bMaskDWord, 0x0008421f); //0xbc0, 0xbc4 - else - PHY_SetBBReg(priv, offset[path][4], bMaskDWord, 0x0009ce7f); //0xbc0, 0xbc4 - - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_pa, DP_BB_REG_NUM_loop_pa); - - // fill PA model to page B1 registers - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); - for(index = 0; index < (DP_PA_MODEL_NUM/2); index++){ //path A = 0xb00, path B = 0xb60 - PHY_SetBBReg(priv, 0xb00+index*4+path*0x60, bMaskDWord, - (PA_model_backup[path][index*2+1] << 16) | PA_model_backup[path][index*2]); - } - PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); - - //one shot - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80044499); //0xb28, 0xb98 - PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00044499); - - _PHY_DPK_polling(priv); - -#if 1 - ////////////////////////////////////////////////////// - // step 4: calculate gain loss caused by DP - ////////////////////////////////////////////////////// - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x0029701f); //0xb00, 0xb70 - tmpReg = PHY_QueryBBReg(priv, offset[path][5], bMaskDWord); //0xbe8, 0xbf8 - - power_I = (tmpReg >> 16); - if(power_I & BIT(15)) - power_I |= bMaskLWord; ////////ZZZZZZZZZZZZZZZZZZ - - power_Q = tmpReg & bMaskLWord; - if(power_Q & BIT(15)) - power_Q |= bMaskHWord; - - DPK_DEBUG("0x%x = 0x%x power_I = 0x%x power_Q = 0x%x\n", offset[path][5], tmpReg, power_I, power_Q); - - tmpReg = power_I*power_I + power_Q*power_Q; - - DPK_DEBUG("gain loss = 0x%x \n", tmpReg); - - if(tmpReg < 26090) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 - PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c - - for(i = 3; i < DP_RF_REG_NUM; i++) - PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); - priv->pshare->bDPKdone[path] = FALSE; - //set original DPK bias table - for(j = 0; j < DP_PA_BIAS_NUM; j++) - PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); - - continue; - } - else - { - priv->pshare->bDPKdone[path] = TRUE; - priv->pshare->bDPKstore = TRUE; - } - - for(i = 0; i < DP_GAIN_LOSS_BOUND_NUM; i++) - { -#if DP_gain_loss == 1 - if(tmpReg > gain_loss_bound[i]/* || i == (DP_GAIN_LOSS_BOUND_NUM -1)*/) -#else - if(tmpReg > gain_loss_bound[i] || i == (DP_GAIN_LOSS_BOUND_NUM -1)) -#endif - { -#if DP_gain_loss == 0 - if(i == 0) - break; - - index = OFDM_index[path] > i?OFDM_index[path]-i:0; - if(index < OFDM_min_index_internalPA) - index = OFDM_min_index_internalPA; - PHY_SetBBReg(priv, offset[path][6], bMaskDWord, OFDMSwingTable[index]); //0xc80, 0xc88 - DPK_DEBUG("original index 0x%x gain_loss minus index 0x%x\n", priv->pshare->OFDM_index[0], i); -#endif - break; - } - } - -#if DP_gain_loss == 1 - - DPK_DEBUG("gain_loss Compensated coefficient %d\n", gain_loss_coef[i]); - coef = gain_loss_coef[i]; - GainLossIndex = i; - priv->pshare->OFDM_min_index_internalPA_DPK[path] = GainLossIndex == 0?0:(GainLossIndex/2+GainLossIndex%2); - - //read DP LUT value from register - for(i = 0; i < DP_PA_MODEL_RUN_NUM; i++) - { - PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x00297018+i); //0xb00, 0xb70 - for(index = 0; index < DP_PA_MODEL_PER_RUN_NUM; index++) - { - tmpReg = (i == 0 && index==0)?0x01000000:PHY_QueryBBReg(priv, offset[path][3]+index*4, bMaskDWord); //0xbdc, 0xbec - - gain_loss_backup[1][i*4+index] = (tmpReg >> 16); //I - if(gain_loss_backup[1][i*4+index] & BIT(15)) - gain_loss_backup[1][i*4+index] |= bMaskHWord; - - gain_loss_backup[0][i*4+index] = (tmpReg & bMaskLWord); //Q - if(gain_loss_backup[0][i*4+index] & BIT(15)) - gain_loss_backup[0][i*4+index] |= bMaskHWord; - DPK_DEBUG("==>DP LUT index %d value 0x%x() I = 0x%x, Q = 0x%x\n", i*4+index, tmpReg, gain_loss_backup[1][i*4+index], gain_loss_backup[0][i*4+index]); - - //gain * LUT - for(j = 0; j < 2; j++) - { - // RTPRINT(FINIT, INIT_IQK, ("==>0DP LUT sram %s index %d value %d()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); - - gain_loss_backup[j][i*4+index] = (gain_loss_backup[j][i*4+index] * coef) / (int)(512); - // RTPRINT(FINIT, INIT_IQK, ("==>1DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); - - gain_loss_backup[j][i*4+index] = gain_loss_backup[j][i*4+index] >= (int)(512)?(int)(511):gain_loss_backup[j][i*4+index] < (int)(-512)?(int)(-512):gain_loss_backup[j][i*4+index]; - // RTPRINT(FINIT, INIT_IQK, ("==>2DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); - - gain_loss_backup[j][i*4+index] = gain_loss_backup[j][i*4+index] >> 2; - // RTPRINT(FINIT, INIT_IQK, ("==>3DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); - - } - tmpReg = ((gain_loss_backup[1][i*4+index] & bMaskByte0) << 8 ) | ((gain_loss_backup[0][i*4+index] & bMaskByte0)); - gain_loss_backup[0][i*4+index] = tmpReg & bMaskLWord; - DPK_DEBUG("==>DP LUT sram index %d value 0x%x()\n", i*4+index, tmpReg); - } - } - - //write DP LUT into sram - for(i = 0; i < DP_PA_MODEL_NUM; i++) - { - value32 = (path==RF92CD_PATH_A?((i%2 == 0)?0x01000000:0x02000000): - ((i%2 == 0)?0x04000000:0x08000000)) | - gain_loss_backup[0][(DP_PA_MODEL_NUM-1)-i] |( (i/2) << 16); - DPK_DEBUG("0xb2c value = 0x%x\n", value32); - PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); - } -// PHY_SetBBReg(priv, 0xb2c , bMaskDWord, 0x00000000); - -#endif - -#endif - - /////////////////////////////////////////////////////////////// - // step 5: Enable Digital Predistortion - /////////////////////////////////////////////////////////////// - // LUT from sram -#if DP_gain_loss == 1 - { - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_dp, DP_BB_REG_NUM_loop_pa); - - // pwsf boundary - PHY_SetBBReg(priv, offset[path][7], bMaskDWord, 0x000fffff); //0xb30, 0xba0 - - // write pwsf to sram - //find tx_index index value - SramIndex = 24; //restore default value - SramIndex -= GainLossIndex; - if(bPlus3db) - SramIndex += 3*4; - - SramIndex = SramIndex >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:(SramIndex<0?0:SramIndex); - - DPK_DEBUG("tx_index = 0x%x, sram value 0x%x gainloss index %d bPlus3db %d\n", tx_index, Sram_db_settings[SramIndex], GainLossIndex, bPlus3db); - - index = 0x1f - tx_index; - if(SramIndex >= index*4) - { - index = SramIndex - index*4; - index_repeat = -2; - SramIndex = -2; - } - else - { - index_repeat = index - SramIndex/4; - SramIndex %= 4; - index = 0; - } - - index = index >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:index; - if(index_repeat == 1) - index_1 = SramIndex; - else - index_1 = index < (DP_SRAM_NUM_db-1)?(index_repeat==-2?index+1*4:index):index; - - DPK_DEBUG("0x1f value = 0x%x, index 0x%x repeat %d SramIndex %d\n", Sram_db_settings[index], index, index_repeat, SramIndex); - - for(i = 0; i < DP_SRAM_NUM; i++) - { - value32 = (path==RF92CD_PATH_A?0x10000000:0x20000000) | (i << 16) | - (Sram_db_settings[index_1] << 8 )| Sram_db_settings[index]; - DPK_DEBUG("0xb2c value = 0x%x\n", value32); - - PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); - if(index_repeat >= 0) - index_repeat -= 2; - else if(index_repeat == -1) - index_repeat = -2; - - if((index < (DP_SRAM_NUM_db-1)-1)) - { - if(index_repeat == -2) - { - index+=2*4; - index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; - } - if(index_repeat == 0) - { - index = SramIndex; - index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; - } - else if(index_repeat == 1) - { - index_1 = SramIndex; - } - else if(index_repeat == -1) - { - index = index_1+1*4; - index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; - } - } - else - { - index = index_1 = (DP_SRAM_NUM_db-1); - } - - index = index < DP_SRAM_NUM_db?index:DP_SRAM_NUM_db-1; - index_1 = index_1 < DP_SRAM_NUM_db?index_1:DP_SRAM_NUM_db-1; - } - } -#else - if(!SkipStep5) - { - _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_dp, DP_BB_REG_NUM_loop_pa); - - // pwsf boundary - PHY_SetBBReg(priv, offset[path][7], bMaskDWord, 0x000fffff); //0xb30, 0xba0 - - // write pwsf to sram - //find RF0x1f index value - if(bPlus3db) - tx_index += 3; - -// tx_index = 0x21; - - index = 0x1f - tx_index; - if(index_for_zero_db >= index) - { - index = index_for_zero_db - index; - index_repeat = -2; - } - else - { - index_repeat = index - index_for_zero_db; - index = 0; - } - - index = index >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:index; - index_1 = index < (DP_SRAM_NUM_db-1)?(index_repeat==-2?index+1:index):index; - - DPK_DEBUG("0x1f value = 0x%x, index 0x%x repeat %d\n", Sram_db_settings[index], index, index_repeat); - - for(i = 0; i < DP_SRAM_NUM; i++) - { - value32 = (path==RF92CD_PATH_A?0x10000000:0x20000000) | (i << 16) | - (Sram_db_settings[index_1] << 8 )| Sram_db_settings[index]; - DPK_DEBUG("0xb2c value = 0x%x\n", value32); - - PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); - if(index_repeat >= 0) - index_repeat -= 2; - else if(index_repeat == -1) - index_repeat = -2; - - if((index < (DP_SRAM_NUM_db-1)-1)) - { - if(index_repeat == -2) - { - index += 2; - index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; - } - if(index_repeat == 0) - { - index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; - } - else if(index_repeat == -1) - { - index++; - index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; - } - } - else - { - index = index_1 = (DP_SRAM_NUM_db-1); - } - } - } -#endif - } - - //reload RF default value - for(path = 0; pathpshare->phw->InternalPA5G[RF92CD_PATH_B]) - { - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x1000f); - PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x60101); - } - - //reload BB default value - for(index=0; indexpshare->bDPKworking = FALSE; - - DPK_DEBUG("<==_PHY_DigitalPredistortion()\n"); -} - -#endif -#endif - -#endif +//============================================================ +// +// File Name: Hal8192CDMOutSrc.c +// +// Description: +// +// This file is for 92CE/92CU outsource dynamic mechanism for partner. +// +// +//============================================================ + +#ifndef _HAL8192CDM_C_ +#define _HAL8192CDM_C_ + +#ifdef __KERNEL__ +#include +#include +#include +#include +#include +#include +#include +#include +#elif defined(__ECOS) +#include +#include +#include +#include +#endif + +#include "./8192cd_cfg.h" +#include "./8192cd.h" +#include "./8192cd_hw.h" +#include "./8192cd_headers.h" +#include "./8192cd_debug.h" + + + +#ifdef __KERNEL__ +#ifdef __LINUX_2_6__ +#include +#else +#include +#endif +#endif + +#if defined(CONFIG_RTL_819X) && defined(USE_RLX_BSP) +#if defined(CONFIG_OPENWRT_SDK) && !defined(CONFIG_ARCH_CPU_RLX) +#include +#else +#include +#endif //CONFIG_OPENWRT_SDK +#endif + + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 5 +#define APK_AFE_REG_NUM 16 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +//============================================================ +// Global var +//============================================================ + +#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST) +unsigned int OFDMSwingTable[] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB +}; + + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; + +unsigned char TxPwrTrk_CCK_SwingTbl[TxPwrTrk_CCK_SwingTbl_Len][8] = { + /* 0.0dB */ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, + /* 0.5dB */ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, + /* 1.0dB */ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, + /* 1.5dB */ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, + /* 2.0dB */ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, + /* 2.5dB */ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, + /* 3.0dB */ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, + /* 3.5dB */ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, + /* 4.0dB */ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, + /* 4.5dB */ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, + /* 5.0dB */ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, + /* 5.5dB */ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, + /* 6.0dB */ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, + /* 6.5dB */ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, + /* 7.0dB */ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, + /* 7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, + /* 8.0dB */ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, + /* 8.5dB */ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, + /* 9.0dB */ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, + /* 9.5dB */ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, + /* 10.0dB */ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, + /* 10.5dB */ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, + /* 11.0dB */ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} +}; + +unsigned char TxPwrTrk_CCK_SwingTbl_CH14[TxPwrTrk_CCK_SwingTbl_Len][8] = { + /* 0.0dB */ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, + /* 0.5dB */ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, + /* 1.0dB */ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, + /* 1.5dB */ {0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* 2.0dB */ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, + /* 2.5dB */ {0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* 3.0dB */ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, + /* 3.5dB */ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* 4.0dB */ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* 4.5dB */ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, + /* 5.0dB */ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, + /* 5.5dB */ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, + /* 6.0dB */ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, + /* 6.5dB */ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, + /* 7.0dB */ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, + /* 7.5dB */ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, + /* 8.0dB */ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, + /* 8.5dB */ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, + /* 9.0dB */ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, + /* 9.5dB */ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* 10.0dB */ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* 10.5dB */ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* 11.0dB */ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} +}; + +//#ifndef USE_OUT_SRC + +unsigned char CCKSwingTable_Ch1_Ch13[][8] = { +{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB +{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB +{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB +{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB +{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB +{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB +{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB +{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB +{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB +{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB +{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB +{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB +{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB +{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB +{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB +{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB +{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB +{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB +{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB +{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB +{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB +{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB +{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB +{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB +{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB +{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB +{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB +{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB +{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB +{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB +{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB +{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB +{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB +}; + +unsigned char CCKSwingTable_Ch14 [][8]= { +{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB +{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB +{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB +{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB +{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB +{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB +{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB +{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB +{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB +{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB +{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB +{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB +{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB +{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB +{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB +{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB +{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB +{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB +{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB +{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB +{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB +{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB +{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB +{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB +{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB +{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB +{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB +{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB +{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB +{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB +{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB +{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB +{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB +}; + +#endif + +//#if defined(_OUTSRC_COEXIST) +#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST) +const int OFDM_TABLE_SIZE= sizeof(OFDMSwingTable)/sizeof(int); +const int CCK_TABLE_SIZE= sizeof(CCKSwingTable_Ch1_Ch13) >>3; +#endif + + +#ifdef CONFIG_RTL_92D_SUPPORT + +static unsigned int OFDMSwingTable_92D[] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB + 0x0f00003c,// 37, -12.5dB + 0x0e400039,// 38, -13.0dB + 0x0d800036,// 39, -13.5dB + 0x0cc00033,// 40, -14.0dB + 0x0c000030,// 41, -14.5dB + 0x0b40002d,// 42, -15.0dB +}; +#endif + + +#ifdef HW_ANT_SWITCH +#define RXDVY_A_EN ((HW_DIV_ENABLE && !priv->pshare->rf_ft_var.antSw_select) ? 0x80 : 0) +#define RXDVY_B_EN ((HW_DIV_ENABLE && priv->pshare->rf_ft_var.antSw_select) ? 0x80 : 0) +#endif + + +//3 ============================================================ +//3 DIG related functions +//3 ============================================================ +#if 0 +int getIGIFor1RCCA(int value_IGI) +{ + #define ONERCCA_LOW_TH 0x30 + #define ONERCCA_LOW_DIFF 8 + + if (value_IGI < ONERCCA_LOW_TH) { + if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) + return ONERCCA_LOW_TH; + else + return value_IGI + ONERCCA_LOW_DIFF; + } else { + return value_IGI; + } +} + + +void set_DIG_state(struct rtl8192cd_priv *priv, int state) +{ + int value_IGI; + + if (state) { + priv->pshare->DIG_on = 1; + priv->pshare->restore = 0; + } + else { + priv->pshare->DIG_on = 0; + if (priv->pshare->restore == 0) { + if (priv->pshare->rf_ft_var.use_ext_lna == 1) + value_IGI = 0x30; + else + value_IGI = 0x20; + +#if defined(HW_ANT_SWITCH) + // wirte new initial gain index into regC50/C58 + if (priv->pshare->rf_ft_var.one_path_cca == 0) { + RTL_W8(0xc50, value_IGI | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI | RXDVY_B_EN); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { + RTL_W8(0xc50, value_IGI | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, getIGIFor1RCCA(value_IGI) | RXDVY_B_EN); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { + RTL_W8(0xc50, getIGIFor1RCCA(value_IGI) | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI | RXDVY_B_EN); +#endif + } +#else + // Write IGI into HW + if (priv->pshare->rf_ft_var.one_path_cca == 0) { + RTL_W8(0xc50, value_IGI); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { + RTL_W8(0xc50, value_IGI); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, getIGIFor1RCCA(value_IGI)); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { + RTL_W8(0xc50, getIGIFor1RCCA(value_IGI)); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI); +#endif + } +#endif + priv->pshare->restore = 1; + } +#ifdef INTERFERENCE_CONTROL + priv->pshare->phw->signal_strength = 0; +#endif + } +} +#endif + +#ifdef CONFIG_RTL_92D_SUPPORT +void MP_DIG_process(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + u4Byte RXOK_cal, RxPWDBAve; + //unsigned int FA_cnt_ofdm = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + + // priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4; + //unsigned int FA_cnt_cck = priv->pshare->cck_FA_cnt; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + if (!(priv->pshare->rf_ft_var.mp_specific && priv->pshare->mp_dig_on)) + return; + + //printk("===> %s, pBandType = %d\n", __FUNCTION__, priv->pmib->dot11RFEntry.phyBandSelect); + + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + + FA_statistic(priv); + + priv->pshare->LastNumQryPhyStatusAll = priv->pshare->NumQryPhyStatus; + priv->pshare->NumQryPhyStatus = priv->pshare->NumQryPhyStatusCCK + priv->pshare->NumQryPhyStatusOFDM; + RXOK_cal = priv->pshare->NumQryPhyStatus - priv->pshare->LastNumQryPhyStatusAll; + + if (RXOK_cal == 0) + RxPWDBAve = 0; + else + RxPWDBAve = priv->pshare->RxPWDBAve/RXOK_cal; + + priv->pshare->RxPWDBAve= 0; + + //printk("RX OK = %d\n", RXOK_cal); + //printk("RSSI = %d\n", RxPWDBAve); + //printk("DIG = (%x, %x), Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", RTL_R8(0xc50), RTL_R8(0xc58), priv->pshare->FA_total_cnt, FA_cnt_ofdm, FA_cnt_cck); + + if (RXOK_cal >= 70) { + if (RxPWDBAve <= 40) { + RTL_W8(0xc50, 0x1C); + RTL_W8(0xc58, 0x1C); + } else if (RxPWDBAve > 45) { + RTL_W8(0xc50, 0x20); + RTL_W8(0xc58, 0x20); + } + } + else { + RTL_W8(0xc50, 0x20); + RTL_W8(0xc58, 0x20); + } + } + mod_timer(&priv->pshare->MP_DIGTimer, RTL_MILISECONDS_TO_JIFFIES(700)); +} +#endif + +void DIG_process(struct rtl8192cd_priv *priv) +{ + #define DEAD_POINT_TH 10000 + #define DOWN_IG_HIT_TH 5 + #define DEAD_POINT_HIT_TH 3 + + unsigned char value_IGI; + signed char value8; + unsigned int IGI_target; + unsigned char Adap_IGI_Upper; +#ifdef INTERFERENCE_CONTROL + unsigned short thd0 = priv->pshare->threshold0; + unsigned short thd1 = priv->pshare->threshold1; + unsigned short thd2 = priv->pshare->threshold2; +#endif + + if (priv->pshare->DIG_on == 1) + { +#ifdef HIGH_POWER_EXT_LNA + if (priv->pshare->rf_ft_var.use_ext_lna == 1) { +// priv->pshare->FA_upper = 0x42; + priv->pshare->FA_upper = MIN_NUM(0x42, priv->pshare->rssi_min+36); + priv->pshare->FA_lower = 0x30; + } else +#endif + { + // Reset initial gain upper & lower bounds +#ifdef DFS + if (!priv->pmib->dot11DFSEntry.disable_DFS && + (OPMODE & WIFI_AP_STATE) && + (((priv->pmib->dot11RFEntry.dot11channel >= 52) && + (priv->pmib->dot11RFEntry.dot11channel <= 64)) || + ((priv->pmib->dot11RFEntry.dot11channel >= 100) && + (priv->pmib->dot11RFEntry.dot11channel <= 140)))){ + priv->pshare->FA_upper = 0x24; + priv->pshare->FA_lower = 0x20; + } + else +#endif + { +#ifdef INTERFERENCE_CONTROL + priv->pshare->FA_lower = 0x20; + + if (priv->pshare->rssi_min != 0xFF) + { +// priv->pshare->FA_upper = 0x3E; + + if (priv->pshare->rssi_min > 30) + priv->pshare->FA_lower = 0x24; + else if (priv->pshare->rssi_min > 25) + priv->pshare->FA_lower = 0x22; + + // limit upper bound to prevent the minimal signal sta from disconnect +// if ((priv->pshare->rssi_min + 10) < priv->pshare->FA_upper) +// priv->pshare->FA_upper = priv->pshare->rssi_min + 10; + priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+20); + } + else // before link + { + priv->pshare->FA_upper = 0x32; + + thd0 = 500; + thd1 = 8000; + thd2 = 10000; + } +#else + if (priv->pmib->dot11RFEntry.tx2path) { + if (priv->pmib->dot11BssType.net_work_type == WIRELESS_11B) + priv->pshare->FA_upper = MIN_NUM(0x2A, priv->pshare->rssi_min+10); + else + priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+10); + } + else + priv->pshare->FA_upper = MIN_NUM(0x3E, priv->pshare->rssi_min+10); + priv->pshare->FA_lower = 0x20; + + if (priv->pshare->rssi_min > 30) + priv->pshare->FA_lower = 0x24; + else if (priv->pshare->rssi_min > 25) + priv->pshare->FA_lower = 0x22; +#endif + } + } + + // determine a new initial gain index according to the sumation of all FA counters as well as upper & lower bounds + value8 = RTL_R8(0xc50); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) { + if(priv->pshare->rf_ft_var.one_path_cca==2) + value8 = RTL_R8(0xc58); + } +#endif + + value_IGI = (value8 & 0x7F); + +#if defined(CONFIG_RTL_NOISE_CONTROL_92C) + if(priv->pshare->rf_ft_var.dnc_enable) + if ((GET_CHIP_VER(priv) == VERSION_8192C)||(GET_CHIP_VER(priv) == VERSION_8188C)){ + unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; +#ifdef HIGH_POWER_EXT_LNA + if(priv->pshare->rf_ft_var.use_ext_lna) { + if( (priv->pshare->rssi_min > 50) ) { + if((!priv->pshare->DNC_on) && (value_IGI >= priv->pshare->FA_upper) && (priv->pshare->FA_total_cnt > priv->pshare->threshold2)) { + priv->pshare->DNC_on = 1; + priv->ext_stats.tp_average_pre = tp_now; + priv->pshare->FA_lower = 0x20; + PHY_SetBBReg(priv, 0x870, bMaskDWord, RTL_R32(0x870)|BIT(5)|BIT(6)|BIT(21)|BIT(22)); + +#ifdef HW_ANT_SWITCH + PHY_SetBBReg(priv, 0xc50, bMaskByte0, priv->pshare->FA_lower | RXDVY_A_EN); + PHY_SetBBReg(priv, 0xc58, bMaskByte0, priv->pshare->FA_lower | RXDVY_B_EN); +#else + PHY_SetBBReg(priv, 0xc50, bMaskByte0, priv->pshare->FA_lower); + PHY_SetBBReg(priv, 0xc58, bMaskByte0, priv->pshare->FA_lower); +#endif + + } else if(priv->pshare->DNC_on ==1) { + if(tp_now < priv->ext_stats.tp_average_pre + 2) { + priv->pshare->DNC_on = 0; + } + else { + priv->pshare->DNC_on =2; + priv->ext_stats.tp_average_pre = tp_now; + } + } else if(priv->pshare->DNC_on >= 2 ) { + if(( tp_now+10 < priv->ext_stats.tp_average_pre ) || (tp_now < 1) ) { + priv->pshare->DNC_on = 0; + } else if(priv->pshare->DNC_on<5) { + priv->ext_stats.tp_average_pre = tp_now; + ++priv->pshare->DNC_on; + } + } + }else { + priv->pshare->DNC_on = 0; + } + + if( priv->pshare->DNC_on ) + return; + else + PHY_SetBBReg(priv, 0x870, bMaskDWord, RTL_R32(0x870)& ~(BIT(5)|BIT(6)|BIT(21)|BIT(22))); + + } else +#endif + { + if( (priv->pshare->rssi_min > 40) && (value_IGI >= priv->pshare->FA_upper) ) { +// unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; + if((!priv->pshare->DNC_on) && (priv->pshare->FA_total_cnt > priv->pshare->threshold2)) { + priv->pshare->DNC_on = 1; + priv->ext_stats.tp_average_pre = tp_now; + } else if(priv->pshare->DNC_on ==1) { + if(tp_now < priv->ext_stats.tp_average_pre + 2) { + priv->pshare->DNC_on = 0; + } + else { + priv->pshare->DNC_on = 2; + priv->ext_stats.tp_average_pre = tp_now; + } + } else if(priv->pshare->DNC_on >= 2 ) { + if((tp_now +10 < priv->ext_stats.tp_average_pre ) + || ((priv->ext_stats.tp_average_pre < 10) && (priv->pshare->FA_total_cnt < priv->pshare->threshold1))) { + priv->pshare->DNC_on = 0; + } else if(priv->pshare->DNC_on<6) { + priv->ext_stats.tp_average_pre = tp_now; + ++priv->pshare->DNC_on; + } + } + if(priv->pshare->DNC_on) { + priv->pshare->FA_upper = 0x3e; + } + }else { + priv->pshare->DNC_on = 0; + } + } + } +#endif + + if ((priv->pshare->digDeadPoint == 0) && (priv->pshare->FA_total_cnt > DEAD_POINT_TH)) { + if ((priv->pshare->digDeadPointHitCount > 0) && (priv->pshare->digDeadPointCandidate == value_IGI)) { + priv->pshare->digDeadPointHitCount++; + if (priv->pshare->digDeadPointHitCount == DEAD_POINT_HIT_TH) { + priv->pshare->digDeadPoint = priv->pshare->digDeadPointCandidate; + } + } else { + priv->pshare->digDeadPointCandidate = value_IGI; + priv->pshare->digDeadPointHitCount = 1; + } + } + +#ifdef INTERFERENCE_CONTROL + if (priv->pshare->FA_total_cnt < thd0) { +#else + if (priv->pshare->FA_total_cnt < priv->pshare->threshold0) { +#endif + priv->pshare->digDownCount++; + if (priv->pshare->digDownCount > DOWN_IG_HIT_TH) { + // Reset deadpoint hit count + if ((priv->pshare->digDeadPoint == 0) && (priv->pshare->digDeadPointHitCount > 0) && (value_IGI == priv->pshare->digDeadPointCandidate)) + priv->pshare->digDeadPointHitCount = 0; + + value_IGI--; + + // Check if the new value is dead point + if ((priv->pshare->digDeadPoint > 0) && (value_IGI == priv->pshare->digDeadPoint)) + value_IGI++; + } +#ifdef INTERFERENCE_CONTROL + } else if (priv->pshare->FA_total_cnt < thd1) { +#else + } else if (priv->pshare->FA_total_cnt < priv->pshare->threshold1) { +#endif + value_IGI += 0; + priv->pshare->digDownCount = 0; +#ifdef INTERFERENCE_CONTROL + } else if (priv->pshare->FA_total_cnt < thd2) { +#else + } else if (priv->pshare->FA_total_cnt < priv->pshare->threshold2) { +#endif + value_IGI++; + priv->pshare->digDownCount = 0; +#ifdef INTERFERENCE_CONTROL + } else if (priv->pshare->FA_total_cnt >= thd2) { +#else + } else if (priv->pshare->FA_total_cnt >= priv->pshare->threshold2) { +#endif + value_IGI += 2; + priv->pshare->digDownCount = 0; + } else { + priv->pshare->digDownCount = 0; + } + + if (value_IGI > priv->pshare->FA_upper) + value_IGI = priv->pshare->FA_upper; + else if (value_IGI < priv->pshare->FA_lower) + value_IGI = priv->pshare->FA_lower; + if (priv->pshare->rf_ft_var.adaptivity_enable && priv->pshare->rf_ft_var.adaptivity_flag == TRUE) + { + Adap_IGI_Upper = priv->pshare->rf_ft_var.Adaptivity_IGI_upper; + if(value_IGI > Adap_IGI_Upper) + value_IGI = Adap_IGI_Upper; + } + +#if defined(HW_ANT_SWITCH) + // wirte new initial gain index into regC50/C58 + if (priv->pshare->rf_ft_var.one_path_cca == 0) { + RTL_W8(0xc50, value_IGI | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI | RXDVY_B_EN); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { + RTL_W8(0xc50, value_IGI | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, getIGIFor1RCCA(value_IGI) | RXDVY_B_EN); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { + RTL_W8(0xc50, getIGIFor1RCCA(value_IGI) | RXDVY_A_EN); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI| RXDVY_B_EN); +#endif + } +#else + // Write IGI into HW + if (priv->pshare->rf_ft_var.one_path_cca == 0) { + RTL_W8(0xc50, value_IGI); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 1) { + RTL_W8(0xc50, value_IGI); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, getIGIFor1RCCA(value_IGI)); +#endif + } else if (priv->pshare->rf_ft_var.one_path_cca == 2) { + RTL_W8(0xc50, getIGIFor1RCCA(value_IGI)); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, value_IGI); +#endif + } +#endif + + } +} + +#if 0 +void check_DIG_by_rssi(struct rtl8192cd_priv *priv, unsigned char rssi_strength) +{ + unsigned int dig_on = 0; + + if (OPMODE & WIFI_SITE_MONITOR) + return; + + if ((rssi_strength > priv->pshare->rf_ft_var.digGoUpperLevel) + && (rssi_strength < HP_LOWER+1) && (priv->pshare->phw->signal_strength != 2)) { +#ifndef CONFIG_RTL_92D_SUPPORT + if (priv->pshare->is_40m_bw) + // RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D + RTL_W8(0xc87, 0x30); + else + RTL_W8(0xc30, 0x44); +#endif + + if (priv->pshare->phw->signal_strength != 3) + dig_on++; + + priv->pshare->phw->signal_strength = 2; + } + else if ((rssi_strength > HP_LOWER+5) && (priv->pshare->phw->signal_strength != 3)) { +#ifndef CONFIG_RTL_92D_SUPPORT + if (priv->pshare->is_40m_bw) + // RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D + RTL_W8(0xc87, 0x30); + else + RTL_W8(0xc30, 0x44); +#endif + + if (priv->pshare->phw->signal_strength != 2) + dig_on++; + + priv->pshare->phw->signal_strength = 3; + } + else if (((rssi_strength < priv->pshare->rf_ft_var.digGoLowerLevel) + && (priv->pshare->phw->signal_strength != 1)) || !priv->pshare->phw->signal_strength) { + // DIG off +// set_DIG_state(priv, 0); + +#ifndef CONFIG_RTL_92D_SUPPORT + if (priv->pshare->is_40m_bw) + //RTL_W8(0xc87, (RTL_R8(0xc87) & 0xf) | 0x30); 92D + RTL_W8(0xc87, 0x30); + else + RTL_W8(0xc30, 0x44); +#endif + + priv->pshare->phw->signal_strength = 1; + } + + if (dig_on) { + // DIG on + set_DIG_state(priv, 1); + } + + //check_DC_TH_by_rssi(priv, rssi_strength); +} + + +void DIG_for_site_survey(struct rtl8192cd_priv *priv, int do_ss) +{ + if (do_ss) { + // DIG off + set_DIG_state(priv, 0); + } + else { + // DIG on +#ifndef INTERFERENCE_CONTROL + if (priv->pshare->phw->signal_strength > 1) +#endif + { + set_DIG_state(priv, 1); + } + } +} +#endif + +#if 0 +//#ifdef INTERFERENCE_CONTROL +void check_NBI_by_rssi(struct rtl8192cd_priv *priv, unsigned char rssi_strength) +{ + if (OPMODE & WIFI_SITE_MONITOR) + return; + + if (priv->pshare->phw->nbi_filter_on) { + if (rssi_strength < 20) { + priv->pshare->phw->nbi_filter_on = 0; + RTL_W16(rOFDM0_RxDSP, RTL_R16(rOFDM0_RxDSP) & ~ BIT(9)); // NBI off + } + } else { // NBI OFF previous + if (rssi_strength > 25) { + priv->pshare->phw->nbi_filter_on = 1; + RTL_W16(rOFDM0_RxDSP, RTL_R16(rOFDM0_RxDSP) | BIT(9)); // NBI on + } + } +} +#endif + +/* + * dynamic CCK CCA enhance by rssi + */ +void CCK_CCA_dynamic_enhance(struct rtl8192cd_priv *priv, unsigned char rssi_strength) +{ +#if 1 + unsigned int cck_fa = priv->pshare->FA_total_cnt; + int rssi_thd = 30; + + if (rssi_strength == 0xff) { + if (cck_fa < 1000) { + if (priv->pshare->phw->CCK_CCA_enhanced != 2) { + RTL_W8(0xa0a, 0x40); + priv->pshare->phw->CCK_CCA_enhanced = 2; + } + } else { + if (priv->pshare->phw->CCK_CCA_enhanced != 1) { + RTL_W8(0xa0a, 0x83); + priv->pshare->phw->CCK_CCA_enhanced = 1; + } + } + return; + } + + if (rssi_strength > rssi_thd+5) { + if (priv->pshare->phw->CCK_CCA_enhanced != 0) { + RTL_W8(0xa0a, 0xcd); + priv->pshare->phw->CCK_CCA_enhanced = 0; + } + } else if (rssi_strength< rssi_thd) { + if ((rssi_strength > 9) || (priv->assoc_num >1)) { + if (priv->pshare->phw->CCK_CCA_enhanced != 1) { + RTL_W8(0xa0a, 0x83); + priv->pshare->phw->CCK_CCA_enhanced = 1; + } + } else { + if(cck_fa<1000) { + if (priv->pshare->phw->CCK_CCA_enhanced != 2) { + RTL_W8(0xa0a, 0x40); + priv->pshare->phw->CCK_CCA_enhanced = 2; + } + } else { + if (priv->pshare->phw->CCK_CCA_enhanced != 1) { + RTL_W8(0xa0a, 0x83); + priv->pshare->phw->CCK_CCA_enhanced = 1; + } + } + } + } + +#else + + if (rssi_strength == 0xff) + return; + + if (!priv->pshare->phw->CCK_CCA_enhanced && (rssi_strength < 30)) { + priv->pshare->phw->CCK_CCA_enhanced = TRUE; + RTL_W8(0xa0a, 0x83); + } + else if (priv->pshare->phw->CCK_CCA_enhanced && (rssi_strength > 35)) { + priv->pshare->phw->CCK_CCA_enhanced = FALSE; + RTL_W8(0xa0a, 0xcd); + } +#endif +} + + +//3 ============================================================ +//3 Dynamic Tx Power / Power Tracking +//3 ============================================================ + +#ifdef HIGH_POWER_EXT_PA +void tx_power_control(struct rtl8192cd_priv *priv) +{ +#ifndef SMP_SYNC + unsigned long x; +#endif + + int pwr_value = 0x10101010; + if( priv->pshare->phw->signal_strength == 3 && priv->pshare->phw->lower_tx_power== 0) { + SAVE_INT_AND_CLI(x); + priv->pshare->phw->power_backup[0x00] = RTL_R32(rTxAGC_A_Rate18_06); + priv->pshare->phw->power_backup[0x01] = RTL_R32(rTxAGC_A_Rate54_24); + priv->pshare->phw->power_backup[0x02] = RTL_R32(rTxAGC_B_Rate18_06); + priv->pshare->phw->power_backup[0x03] = RTL_R32(rTxAGC_B_Rate54_24); + priv->pshare->phw->power_backup[0x04] = RTL_R32(rTxAGC_A_Mcs03_Mcs00); + priv->pshare->phw->power_backup[0x05] = RTL_R32(rTxAGC_A_Mcs07_Mcs04); + priv->pshare->phw->power_backup[0x06] = RTL_R32(rTxAGC_A_Mcs11_Mcs08); + priv->pshare->phw->power_backup[0x07] = RTL_R32(rTxAGC_A_Mcs15_Mcs12); + priv->pshare->phw->power_backup[0x08] = RTL_R32(rTxAGC_B_Mcs03_Mcs00); + priv->pshare->phw->power_backup[0x09] = RTL_R32(rTxAGC_B_Mcs07_Mcs04); + priv->pshare->phw->power_backup[0x0a] = RTL_R32(rTxAGC_B_Mcs11_Mcs08); + priv->pshare->phw->power_backup[0x0b] = RTL_R32(rTxAGC_B_Mcs15_Mcs12); + priv->pshare->phw->power_backup[0x0c] = RTL_R32(rTxAGC_A_CCK11_2_B_CCK11); + priv->pshare->phw->power_backup[0x0d] = RTL_R32(rTxAGC_A_CCK1_Mcs32); + priv->pshare->phw->power_backup[0x0e] = RTL_R32(rTxAGC_B_CCK5_1_Mcs32); + RTL_W32(rTxAGC_A_Rate18_06, pwr_value); + RTL_W32(rTxAGC_A_Rate54_24, pwr_value); + RTL_W32(rTxAGC_B_Rate18_06, pwr_value); + RTL_W32(rTxAGC_B_Rate54_24, pwr_value); + RTL_W32(rTxAGC_A_Mcs03_Mcs00, pwr_value); + RTL_W32(rTxAGC_A_Mcs07_Mcs04, pwr_value); + RTL_W32(rTxAGC_A_Mcs11_Mcs08, pwr_value); + RTL_W32(rTxAGC_A_Mcs15_Mcs12, pwr_value); + RTL_W32(rTxAGC_B_Mcs03_Mcs00, pwr_value); + RTL_W32(rTxAGC_B_Mcs07_Mcs04, pwr_value); + RTL_W32(rTxAGC_B_Mcs11_Mcs08, pwr_value); + RTL_W32(rTxAGC_B_Mcs15_Mcs12, pwr_value); + RTL_W32(rTxAGC_A_CCK11_2_B_CCK11, pwr_value); + RTL_W32(rTxAGC_A_CCK1_Mcs32, (pwr_value & 0x0000ff00) | (priv->pshare->phw->power_backup[0x0d] &0xffff00ff)); + RTL_W32(rTxAGC_B_CCK5_1_Mcs32, (pwr_value & 0xffffff00) | (priv->pshare->phw->power_backup[0x0e] &0x000000ff)); + priv->pshare->phw->lower_tx_power = 1; + RESTORE_INT(x); + } + else if( priv->pshare->phw->signal_strength != 3 && priv->pshare->phw->lower_tx_power) { + SAVE_INT_AND_CLI(x); + RTL_W32(rTxAGC_A_Rate18_06, priv->pshare->phw->power_backup[0x00]); + RTL_W32(rTxAGC_A_Rate54_24, priv->pshare->phw->power_backup[0x01]); + RTL_W32(rTxAGC_B_Rate18_06, priv->pshare->phw->power_backup[0x02]); + RTL_W32(rTxAGC_B_Rate54_24, priv->pshare->phw->power_backup[0x03]); + RTL_W32(rTxAGC_A_Mcs03_Mcs00, priv->pshare->phw->power_backup[0x04]); + RTL_W32(rTxAGC_A_Mcs07_Mcs04, priv->pshare->phw->power_backup[0x05]); + RTL_W32(rTxAGC_A_Mcs11_Mcs08, priv->pshare->phw->power_backup[0x06]); + RTL_W32(rTxAGC_A_Mcs15_Mcs12, priv->pshare->phw->power_backup[0x07]); + RTL_W32(rTxAGC_B_Mcs03_Mcs00, priv->pshare->phw->power_backup[0x08]); + RTL_W32(rTxAGC_B_Mcs07_Mcs04, priv->pshare->phw->power_backup[0x09]); + RTL_W32(rTxAGC_B_Mcs11_Mcs08, priv->pshare->phw->power_backup[0x0a]); + RTL_W32(rTxAGC_B_Mcs15_Mcs12, priv->pshare->phw->power_backup[0x0b]); + RTL_W32(rTxAGC_A_CCK11_2_B_CCK11, priv->pshare->phw->power_backup[0x0c]); + RTL_W32(rTxAGC_A_CCK1_Mcs32, priv->pshare->phw->power_backup[0x0d]); + RTL_W32(rTxAGC_B_CCK5_1_Mcs32, priv->pshare->phw->power_backup[0x0e]); + priv->pshare->phw->lower_tx_power = 0; + RESTORE_INT(x); + } +} +#endif + +#if 0 +int get_CCK_swing_index(struct rtl8192cd_priv *priv) +{ + int TempCCk, index=12, i; + short channel; +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) + channel=priv->pshare->working_channel; + else +#endif + channel = (priv->pmib->dot11RFEntry.dot11channel); + + //Query CCK default setting From 0xa24 + TempCCk = PHY_QueryBBReg(priv, rCCK0_TxFilter2, bMaskDWord)&bMaskCCK; + TempCCk = cpu_to_le32(TempCCk); + for(i=0 ; ipshare->rf_ft_var.mp_specific) + channel=priv->pshare->working_channel; + else +#endif + channel = (priv->pmib->dot11RFEntry.dot11channel); + + +#ifdef CONFIG_RTL_88E_SUPPORT //for 88e tx power tracking + if(GET_CHIP_VER(priv) == VERSION_8188E){ + if(channel !=14) { + RTL_W8( 0xa22, 0x1c); + RTL_W8( 0xa23, 0x1a); + RTL_W8( 0xa24, 0x18); + RTL_W8( 0xa25, 0x12); + RTL_W8( 0xa26, 0xe); + RTL_W8( 0xa27, 0x8); + RTL_W8( 0xa28, 0x4); + RTL_W8( 0xa29, 0x2); + } + else{ + RTL_W8( 0xa22, 0x1c); + RTL_W8( 0xa23, 0x1a); + RTL_W8( 0xa24, 0x18); + RTL_W8( 0xa25, 0x12); + RTL_W8( 0xa26, 0x0); + RTL_W8( 0xa27, 0x0); + RTL_W8( 0xa28, 0x0); + RTL_W8( 0xa29, 0x0); + } + } + else +#endif + if(channel !=14) { + RTL_W8( 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]); + RTL_W8( 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]); + RTL_W8( 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]); + RTL_W8( 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]); + RTL_W8( 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]); + RTL_W8( 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]); + RTL_W8( 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]); + RTL_W8( 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]); + } + else{ + RTL_W8( 0xa22, CCKSwingTable_Ch14[CCK_index][0]); + RTL_W8( 0xa23, CCKSwingTable_Ch14[CCK_index][1]); + RTL_W8( 0xa24, CCKSwingTable_Ch14[CCK_index][2]); + RTL_W8( 0xa25, CCKSwingTable_Ch14[CCK_index][3]); + RTL_W8( 0xa26, CCKSwingTable_Ch14[CCK_index][4]); + RTL_W8( 0xa27, CCKSwingTable_Ch14[CCK_index][5]); + RTL_W8( 0xa28, CCKSwingTable_Ch14[CCK_index][6]); + RTL_W8( 0xa29, CCKSwingTable_Ch14[CCK_index][7]); + } +} +#endif + +unsigned char getThermalValue(struct rtl8192cd_priv *priv) +{ + unsigned char ThermalValue; + int sum=0, i=0; + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 0x60); + while ((PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 1) > 0x1f) && ((i++) < 1000)) {//<20ms, test is in 20 us + delay_us(20); + } + ThermalValue =(unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, bMask20Bits, 1) & 0x01f; + priv->pshare->Thermal_idx = (priv->pshare->Thermal_idx+1)%8; + priv->pshare->Thermal_log[ priv->pshare->Thermal_idx ] = ThermalValue; + for(i=0; i<8; i++) { + if(!priv->pshare->Thermal_log[i]) + return ThermalValue; + sum += priv->pshare->Thermal_log[i]; + } + return (sum+4)>>3; +} + + +#ifdef CONFIG_RTL_92C_SUPPORT + +#ifdef HIGH_POWER_EXT_PA +void swingIndexRemap2(int *a, int b, int i) +{ + + u8 index_mapping_HighPower_92C[4][15] = { + {0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 18, 18, 18}, //2.4G, path A/MAC 0, decrease power + {0, 2, 4, 5, 7, 8, 10, 11, 13, 14, 16, 17, 19, 20, 22}, //2.4G, path A/MAC 0, increase power + {0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 18, 18, 18}, //2.4G, path A/MAC 0, decrease power + {0, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23}, //2.4G, path A/MAC 0, increase power + }; + + int d = RTL_ABS(*a, b); + int offset = 0; + + + if(i == 0) + offset = 1; + else + offset = 3; + + if(*a < b ) + { + //printk("\n\n Increase Power !! \n\n"); + *a = b - index_mapping_HighPower_92C[offset][d]; + } + else + { + //printk("\n\n Decrease Power !! \n\n"); + offset = offset - 1; + *a = b + index_mapping_HighPower_92C[offset][d]; + } + + //printk("\n\ a = %d, b = %d, offset = %d, d = %d, diff = %d \n\n", + //*a, b, offset, d, index_mapping_HighPower_92C[offset][d]); + +} +void swingIndexRemap(int *a, int b) +{ + int d = (RTL_ABS(*a, b) *3)>>1; + if(*a < b ) + *a = b - d; + else + *a = b + d; +} +#endif + +void tx_power_tracking(struct rtl8192cd_priv *priv) +{ + unsigned char ThermalValue = 0, delta, delta_LCK, delta_IQK; + int ele_A, ele_D, value32, X, Y, ele_C; + int OFDM_index[2]={0,0}, CCK_index; + int i = 0; + char is2T = ((GET_CHIP_VER(priv) == VERSION_8192C) ?1 :0); + unsigned char TxPwrLevel[2]; + unsigned char channel, OFDM_min_index = 6, rf=1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur +#ifdef POWER_PERCENT_ADJUSTMENT + signed char pwrdiff_percent; +#endif +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel=priv->pshare->working_channel; + if(priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ThermalValue = getThermalValue(priv); + + rf += is2T; + if(ThermalValue) { + + if(!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_LCK = ThermalValue; + priv->pshare->ThermalValue_IQK = ThermalValue; + + //Query OFDM path A default setting + ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; ipshare->OFDM_index[0] = i; + priv->pshare->OFDM_index0[0] = i; + break; + } + } + + //Query OFDM path B default setting + if(is2T) { + ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; ipshare->OFDM_index[1] = i; + priv->pshare->OFDM_index0[1] = i; + break; + } + } + } + priv->pshare->CCK_index = get_CCK_swing_index(priv); + priv->pshare->CCK_index0 = priv->pshare->CCK_index; + + } + + delta = RTL_ABS(ThermalValue, priv->pshare->ThermalValue); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); + +// printk("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", +// ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK); + + if(delta_LCK > 1) { + priv->pshare->ThermalValue_LCK = ThermalValue; +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) + printk("NOT do LCK during ctx !!!! \n"); + else + PHY_LCCalibrate(priv); + } + else +#endif + PHY_LCCalibrate(priv); + } + + if(delta > 0) { + if(ThermalValue > priv->pshare->ThermalValue) { + for(i = 0; i < rf; i++) + priv->pshare->OFDM_index[i] -= delta; + priv->pshare->CCK_index -= delta; + } else { + for(i = 0; i < rf; i++) + priv->pshare->OFDM_index[i] += delta; + priv->pshare->CCK_index += delta; + } + if(ThermalValue > priv->pmib->dot11RFEntry.ther) { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i]+1; + CCK_index = priv->pshare->CCK_index+1; + } else { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i]; + CCK_index = priv->pshare->CCK_index; + } +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + TxPwrLevel[0] = priv->pshare->mp_txpwr_patha; + TxPwrLevel[1] = priv->pshare->mp_txpwr_pathb; + } else +#endif + { + TxPwrLevel[0] = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[channel-1]; + TxPwrLevel[1] = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_B[channel-1]; + + if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { + unsigned char offset = (priv->pmib->dot11RFEntry.pwrdiffHT20[channel-1] & 0x0f); + TxPwrLevel[0] = COUNT_SIGN_OFFSET(TxPwrLevel[0], offset); + offset = ((priv->pmib->dot11RFEntry.pwrdiffOFDM[channel-1] & 0xf0) >> 4); + TxPwrLevel[1] = COUNT_SIGN_OFFSET(TxPwrLevel[1], offset); + } +#ifdef POWER_PERCENT_ADJUSTMENT + pwrdiff_percent = PwrPercent2PwrLevel(priv->pmib->dot11RFEntry.power_percent); + TxPwrLevel[0] = POWER_RANGE_CHECK(TxPwrLevel[0]+pwrdiff_percent); + TxPwrLevel[1] = POWER_RANGE_CHECK(TxPwrLevel[1]+pwrdiff_percent); +#endif + } + +// printk("TxPwrLevel[0]=%d, TxPwrLevel[1]=%d\n", TxPwrLevel[0], TxPwrLevel[1]); + for(i = 0; i < rf; i++) { + if(/*TxPwrLevel[i] >=0 &&*/ TxPwrLevel[i] <=26) { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) { + if (delta < 5) + OFDM_index[i] -= 1; + else + OFDM_index[i] -= 2; + } else if(delta > 5 && ThermalValue < priv->pmib->dot11RFEntry.ther) { + OFDM_index[i] += 1; + } + } else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > priv->pmib->dot11RFEntry.ther) { + if (delta < 5) + OFDM_index[i] -= 1; + else + OFDM_index[i] -= 2; + } else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > priv->pmib->dot11RFEntry.ther && delta > 5) { + OFDM_index[i] -= 1; + } + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) + { + int d = 0; + + OFDM_index[i] = priv->pshare->OFDM_index[i]; + d = RTL_ABS(OFDM_index[i], priv->pshare->OFDM_index0[i]); + + if(OFDM_index[i] < priv->pshare->OFDM_index0[i]) + { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, d, 0, 0); + } + else + { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, d, 1, 0); + } + + } + else +#endif + { +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) { + OFDM_index[i] = priv->pshare->OFDM_index[i]; + swingIndexRemap2(&OFDM_index[i], priv->pshare->OFDM_index0[i], i); //Modify HP tracking table, from Arthur 2012.02.13 + //swingIndexRemap(&OFDM_index[i], priv->pshare->OFDM_index0[i]); + } +#endif + } + if(OFDM_index[i] > OFDM_TABLE_SIZE-1) + OFDM_index[i] = OFDM_TABLE_SIZE-1; + else if (OFDM_index[i] < OFDM_min_index) + OFDM_index[i] = OFDM_min_index; + } + i=0; + { + if(/*TxPwrLevel[i] >=0 &&*/ TxPwrLevel[i] <=26) { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) { + if (delta < 5) + CCK_index -= 1; + else + CCK_index -= 2; + } else if(delta > 5 && ThermalValue < priv->pmib->dot11RFEntry.ther) { + CCK_index += 1; + } + } else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > priv->pmib->dot11RFEntry.ther) { + if (delta < 5) + CCK_index -= 1; + else + CCK_index -= 2; + } else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > priv->pmib->dot11RFEntry.ther && delta > 5) { + CCK_index -= 1; + } + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) + { + int d = 0; + + CCK_index = priv->pshare->CCK_index; + d = RTL_ABS(CCK_index, priv->pshare->CCK_index0); + + if(CCK_index < priv->pshare->CCK_index0) + { + CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, d, 0, 1); + } + else + { + CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, d, 1, 1); + } + + } + else +#endif + { +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) { + CCK_index = priv->pshare->CCK_index; + swingIndexRemap2( &CCK_index, priv->pshare->CCK_index0, i); //Modify HP tracking table, from Arthur 2012.02.13 + //swingIndexRemap( &CCK_index, priv->pshare->CCK_index0); + } +#endif + } + if(CCK_index > CCK_TABLE_SIZE-1) + CCK_index = CCK_TABLE_SIZE-1; + else if (CCK_index < 0) + CCK_index = 0; + } + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable[(unsigned int)OFDM_index[0]] & 0xFFC00000)>>22; + X = priv->pshare->RegE94; + Y = priv->pshare->RegE9C; + + if(X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); + + } else { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned int)OFDM_index[0]]); + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); + } + + + set_CCK_swing_index(priv, CCK_index); + + + if(is2T) { + ele_D = (OFDMSwingTable[(unsigned int)OFDM_index[1]] & 0xFFC00000)>>22; + X = priv->pshare->RegEB4; + Y = priv->pshare->RegEBC; + + if(X != 0) { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); + + } else { + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned int)OFDM_index[1]]); + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); + } + } + } + + if(delta_IQK > 3) { + priv->pshare->ThermalValue_IQK = ThermalValue; +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) + printk("NOT do IQK during ctx !!!! \n"); + else + PHY_IQCalibrate(priv); + } + else +#endif + PHY_IQCalibrate(priv); + } + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + + } +} +#endif + + +#ifdef RX_GAIN_TRACK_92D +static void rx_gain_tracking_92D(struct rtl8192cd_priv *priv) +{ + u8 index_mapping[Rx_index_mapping_NUM] = { + 0x0f, 0x0f, 0x0f, 0x0f, 0x0b, + 0x0a, 0x09, 0x08, 0x07, 0x06, + 0x05, 0x04, 0x04, 0x03, 0x02 + }; + + u8 eRFPath, curMaxRFPath; + u32 u4tmp; + + u4tmp = (index_mapping[(priv->pmib->dot11RFEntry.ther - priv->pshare->ThermalValue_RxGain)]) << 12; + + DEBUG_INFO("===>%s interface %d Rx Gain %x\n", __FUNCTION__, priv->pshare->wlandev_idx, u4tmp); + + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else + curMaxRFPath = RF92CD_PATH_MAX; + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) + PHY_SetRFReg(priv, eRFPath, 0x3C, bMask20Bits, (priv->pshare->RegRF3C[eRFPath]&(~(0xF000)))|u4tmp); + +}; + +#endif + +#if 0 +//#ifdef CONFIG_RTL_88E_SUPPORT //for 88e tx power tracking + +void ODM_ResetIQKResult(struct rtl8192cd_priv *priv) +{ +/* +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte i; + + if (!IS_HARDWARE_TYPE_8192D(Adapter)) + return; +#endif +*/ + + unsigned char i; + + //printk("PHY_ResetIQKResult:: settings regs %d default regs %d\n", sizeof(priv->pshare->IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING), IQK_Matrix_Settings_NUM); + //0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc + + for(i = 0; i < IQK_Matrix_Settings_NUM; i++) + { + { + priv->pshare->IQKMatrixRegSetting[i].Value[0][0] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][2] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][4] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][6] = 0x100; + + priv->pshare->IQKMatrixRegSetting[i].Value[0][1] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][3] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][5] = + priv->pshare->IQKMatrixRegSetting[i].Value[0][7] = 0x0; + + priv->pshare->IQKMatrixRegSetting[i].bIQKDone = FALSE; + + } + } + +} + +#define RF_PATH_A 0 //Radio Path A +#define OFDM_TABLE_SIZE_92D 43 + +#define bRFRegOffsetMask 0xfffff + + +//091212 chiyokolin +void odm_TXPowerTrackingCallback_ThermalMeter_8188E(struct rtl8192cd_priv *priv) +{ + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + unsigned char ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; + unsigned char ThermalValue_AVG_count = 0; + unsigned int ThermalValue_AVG = 0; + int ele_A=0, ele_D, TempCCk, X, value32; + int Y, ele_C=0; + char OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; + unsigned int i = 0, j = 0; + char is2T = FALSE; + //char bInteralPA = FALSE; + + unsigned char OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + unsigned char Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/; + char OFDM_index_mapping[2][index_mapping_NUM_88E] = { + {0, 0, 2, 3, 4, 4, //2.4G, decrease power + 5, 6, 7, 7, 8, 9, + 10, 10, 11}, // For lower temperature, 20120220 updated on 20120220. + {0, 0, -1, -2, -3, -4, //2.4G, increase power + -4, -4, -4, -5, -7, -8, + -9, -9, -10}, + }; + unsigned char Thermal_mapping[2][index_mapping_NUM_88E] = { + {0, 2, 4, 6, 8, 10, //2.4G, decrease power + 12, 14, 16, 18, 20, 22, + 24, 26, 27}, + {0, 2, 4, 6, 8, 10, //2.4G,, increase power + 12, 14, 16, 18, 20, 22, + 25, 25, 25}, + }; + + priv->pshare->TXPowerTrackingCallbackCnt++; //cosa add for debug + priv->pshare->bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) + priv->pshare->TxPowerTrackControl = 1; //priv->pshare->TxPowerTrackControl; //_eric_?? // We should keep updating the control variable according to HalData. + // pshare->RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + priv->pshare->RegA24 = 0x090e1317; +#endif + + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + if(priv->pshare->mp_txpwr_tracking == FALSE) + return; + } +#endif + + if(priv->pshare->Power_tracking_on_88E == 0) + { + priv->pshare->Power_tracking_on_88E = 1; + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x03); + return; + } + else + { + + priv->pshare->Power_tracking_on_88E = 0; + + //printk("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", priv->pshare->TxPowerTrackControl); + + ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, RF_T_METER_88E, 0xfc00, 1); //0x42: RF Reg[15:10] 88E + + printk("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); + + } + + if(is2T) + rf = 2; + else + rf = 1; + + if(ThermalValue) + { +// if(!pHalData->ThermalValue) + { + //Query OFDM path A default setting + ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; + + for(i=0; ipshare->RegA24; + + for(i=0 ; ipshare->bCCKinCH14) + { + if(memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==0) + { + CCK_index_old =(unsigned char) i; + //printk("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", + //rCCK0_TxFilter2, TempCCk, CCK_index_old, priv->pshare->bCCKinCH14); + break; + } + } + else + { + //printk("RegA24: 0x%X, CCKSwingTable_Ch1_Ch13[%d][2]: CCKSwingTable_Ch1_Ch13[i][2]: 0x%X\n", TempCCk, i, CCKSwingTable_Ch1_Ch13[i][2]); + if(memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==0) + { + CCK_index_old =(unsigned char) i; + //printk("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", + //rCCK0_TxFilter2, TempCCk, CCK_index_old, priv->pshare->bCCKinCH14); + break; + } + } + } + } + + if(!priv->pshare->ThermalValue) + { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_LCK = ThermalValue; + priv->pshare->ThermalValue_IQK = ThermalValue; + + for(i = 0; i < rf; i++) + priv->pshare->OFDM_index[i] = OFDM_index_old[i]; + priv->pshare->CCK_index = CCK_index_old; + } + + if(priv->pshare->bReloadtxpowerindex) + { + printk("reload ofdm index for band switch\n"); + } + + //calculate average thermal meter + { + priv->pshare->ThermalValue_AVG[priv->pshare->ThermalValue_AVG_index] = ThermalValue; + priv->pshare->ThermalValue_AVG_index++; + if(priv->pshare->ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) + priv->pshare->ThermalValue_AVG_index = 0; + + for(i = 0; i < AVG_THERMAL_NUM_88E; i++) + { + if(priv->pshare->ThermalValue_AVG[i]) + { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) + { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + printk("AVG Thermal Meter = 0x%x \n", ThermalValue); + } + } + } + + if(priv->pshare->bReloadtxpowerindex) + { + delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); + priv->pshare->bReloadtxpowerindex = FALSE; + priv->pshare->bDoneTxpower = FALSE; + } + else if(priv->pshare->bDoneTxpower) + { + delta = (ThermalValue > priv->pshare->ThermalValue)?(ThermalValue - priv->pshare->ThermalValue):(priv->pshare->ThermalValue - ThermalValue); + } + else + { + delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); + } + delta_LCK = (ThermalValue > priv->pshare->ThermalValue_LCK)?(ThermalValue - priv->pshare->ThermalValue_LCK):(priv->pshare->ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > priv->pshare->ThermalValue_IQK)?(ThermalValue - priv->pshare->ThermalValue_IQK):(priv->pshare->ThermalValue_IQK - ThermalValue); + + printk("Readback Thermal Meter = 0x%x \npre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x \ndelta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, priv->pshare->ThermalValue, priv->pshare->EEPROMThermalMeter, delta, delta_LCK, delta_IQK); + printk("pre thermal meter LCK 0x%x \npre thermal meter IQK 0x%x \ndelta_LCK_bound 0x%x delta_IQK_bound 0x%x\n", priv->pshare->ThermalValue_LCK, priv->pshare->ThermalValue_IQK, priv->pshare->Delta_LCK, priv->pshare->Delta_IQK); + + + //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) + if (delta_LCK >= 8) // Delta temperature is equal to or larger than 20 centigrade. + { + priv->pshare->ThermalValue_LCK = ThermalValue; + PHY_LCCalibrate(priv); + } + + + if(delta > 0 && priv->pshare->TxPowerTrackControl) + { + delta = ThermalValue > priv->pmib->dot11RFEntry.ther?(ThermalValue - priv->pmib->dot11RFEntry.ther):(priv->pmib->dot11RFEntry.ther - ThermalValue); + + //calculate new OFDM / CCK offset + { + { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) + j = 1; + else + j = 0; + + for(offset = 0; offset < index_mapping_NUM_88E; offset++) + { + if(delta < Thermal_mapping[j][offset]) + { + if(offset != 0) + offset--; + break; + } + } + if(offset >= index_mapping_NUM_88E) + offset = index_mapping_NUM_88E-1; + + index = OFDM_index_mapping[j][offset]; + + printk("\nj = %d delta = %d, index = %d\n\n", j, delta, index); + + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i] + OFDM_index_mapping[j][offset]; + CCK_index = priv->pshare->CCK_index + OFDM_index_mapping[j][offset]; + } + + if(is2T) + { + printk("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + priv->pshare->OFDM_index[0], priv->pshare->OFDM_index[1], priv->pshare->CCK_index); + } + else + { + printk("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", + priv->pshare->OFDM_index[0], priv->pshare->CCK_index); + } + + for(i = 0; i < rf; i++) + { + if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) + { + OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; + } + else if (OFDM_index[i] < OFDM_min_index) + { + OFDM_index[i] = OFDM_min_index; + } + } + + { + if(CCK_index > CCK_TABLE_SIZE-1) + CCK_index = CCK_TABLE_SIZE-1; + else if (CCK_index < 0) + CCK_index = 0; + } + + if(is2T) + { + printk("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], OFDM_index[1], CCK_index); + } + else + { + printk("new OFDM_A_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], CCK_index); + } + } + + //2 temporarily remove bNOPG + //Config by SwingTable + if(priv->pshare->TxPowerTrackControl /*&& !pHalData->bNOPG*/) + { + priv->pshare->bDoneTxpower = TRUE; + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable[(unsigned char)OFDM_index[0]] & 0xFFC00000)>>22; + X = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][0]; + Y = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][1]; + + if(X != 0) + { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); + + } + else + { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned char)OFDM_index[0]]); + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); + } + + //printk("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n", + //(unsigned int)X, (unsigned int)Y, (unsigned int)ele_A, (unsigned int)ele_C, (unsigned int)ele_D, (unsigned int)X, (unsigned int)Y); + + { + //Adjust CCK according to IQK result + if(!priv->pshare->bCCKinCH14){ + RTL_W8(0xa22, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][0]); + RTL_W8(0xa23, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][1]); + RTL_W8(0xa24, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][2]); + RTL_W8(0xa25, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][3]); + RTL_W8(0xa26, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][4]); + RTL_W8(0xa27, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][5]); + RTL_W8(0xa28, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][6]); + RTL_W8(0xa29, CCKSwingTable_Ch1_Ch13[(unsigned char)CCK_index][7]); + } + else{ + RTL_W8(0xa22, CCKSwingTable_Ch14[(unsigned char)CCK_index][0]); + RTL_W8(0xa23, CCKSwingTable_Ch14[(unsigned char)CCK_index][1]); + RTL_W8(0xa24, CCKSwingTable_Ch14[(unsigned char)CCK_index][2]); + RTL_W8(0xa25, CCKSwingTable_Ch14[(unsigned char)CCK_index][3]); + RTL_W8(0xa26, CCKSwingTable_Ch14[(unsigned char)CCK_index][4]); + RTL_W8(0xa27, CCKSwingTable_Ch14[(unsigned char)CCK_index][5]); + RTL_W8(0xa28, CCKSwingTable_Ch14[(unsigned char)CCK_index][6]); + RTL_W8(0xa29, CCKSwingTable_Ch14[(unsigned char)CCK_index][7]); + } + } + + if(is2T) + { + ele_D = (OFDMSwingTable[(unsigned char)OFDM_index[1]] & 0xFFC00000)>>22; + + //new element A = element D x X + X = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][4]; + Y = priv->pshare->IQKMatrixRegSetting[Indexforchannel].Value[0][5]; + + //if(X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G) + if((X != 0) && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) + + { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); + + } + else + { + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(unsigned char)OFDM_index[1]]); + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); + } + + //printk("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + //(unsigned int)X, (unsigned int)Y, (unsigned int)ele_A, (unsigned int)ele_C, (unsigned int)ele_D, (unsigned int)X, (unsigned int)Y); + } + + printk("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n\n", PHY_QueryBBReg(priv, 0xc80, bMaskDWord), PHY_QueryBBReg(priv, 0xc94, bMaskDWord), PHY_QueryRFReg(priv, RF_PATH_A, 0x24, bRFRegOffsetMask, 1)); + } + } + + +#if 0 //DO NOT do IQK during 88E power tracking + // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) + if (delta_IQK >= 8) // Delta temperature is equal to or larger than 20 centigrade. + { + ODM_ResetIQKResult(priv); + +/* +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif +*/ + priv->pshare->ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8188E(priv, FALSE); + +/* +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +*/ + } +#endif + + //update thermal meter value + if(priv->pshare->TxPowerTrackControl) + { + //Adapter->HalFunc.SetHalDefVarHandler(Adapter, HAL_DEF_THERMAL_VALUE, &ThermalValue); + priv->pshare->ThermalValue = ThermalValue; + } + + } + + //printk("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"); + + priv->pshare->TXPowercount = 0; + +} + + + + +#endif + + + +#ifdef CONFIG_RTL_92D_SUPPORT + +void getDeltaValue(struct rtl8192cd_priv *priv) +{ + unsigned int tempval[2]; + + tempval[0] = priv->pmib->dot11RFEntry.deltaIQK; + tempval[1] = priv->pmib->dot11RFEntry.deltaLCK; + + switch(tempval[0]) + { + case 0: + tempval[0] = 5; + break; + + case 1: + tempval[0] = 4; + break; + + case 2: + tempval[0] = 3; + break; + + case 3: + default: + tempval[0] = 0; + break; + } + + switch(tempval[1]) + { + case 0: + tempval[1] = 4; + break; + + case 1: + tempval[1] = 3; + break; + + case 2: + tempval[1] = 2; + break; + + case 3: + default: + tempval[1] = 0; + break; + } + + priv->pshare->Delta_IQK = tempval[0]; + priv->pshare->Delta_LCK = tempval[1]; +} + +void tx_power_tracking_92D(struct rtl8192cd_priv *priv) +{ + u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, index[2], offset, ThermalValue_AVG_count = 0; + u32 ThermalValue_AVG = 0; + int ele_A, ele_D, X, value32, Y, ele_C; + char OFDM_index[2], CCK_index=0; + int i = 0; + char is2T = ((priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) ?1 :0); + u8 OFDM_min_index = 6, OFDM_min_index_internalPA = 5, rf=1, channel; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur u1Byte OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + + u8 index_mapping[5][index_mapping_NUM] = { + {0, 1, 3, 6, 8, 9, //5G, path A/MAC 0, decrease power + 11, 13, 14, 16, 17, 18, 18}, + {0, 2, 4, 5, 7, 10, //5G, path A/MAC 0, increase power + 12, 14, 16, 18, 18, 18, 18}, + {0, 2, 3, 6, 8, 9, //5G, path B/MAC 1, decrease power + 11, 13, 14, 16, 17, 18, 18}, + {0, 2, 4, 5, 7, 10, //5G, path B/MAC 1, increase power + 13, 16, 16, 18, 18, 18, 18}, + {0, 1, 2, 3, 4, 5, //2.4G, for decreas power + 6, 7, 7, 8, 9, 10, 10}, + }; + +#if defined(RTL8192D_INT_PA) + + u8 index_mapping_internalPA[8][index_mapping_NUM] = { + {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch36-64, decrease power + 9, 11, 13, 15, 16, 16, 16}, + {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch36-64, increase power + 9, 11, 13, 15, 16, 18, 20}, + {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch100-165, decrease power + 9, 11, 13, 15, 16, 16, 16}, + {0, 1, 3, 4, 6, 7, //5G, path A/MAC 0, ch100-165, increase power + 9, 11, 13, 15, 16, 18, 20}, + {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch36-64, decrease power + 9, 11, 13, 15, 16, 16, 16}, + {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch36-64, increase power + 9, 11, 13, 15, 16, 18, 20}, + {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch100-165, decrease power + 9, 11, 13, 15, 16, 16, 16}, + {0, 1, 3, 4, 6, 7, //5G, path B/MAC 1, ch100-165, increase power + 9, 11, 13, 15, 16, 18, 20}, + }; + + u8 bInteralPA[2]; + +#endif + +#ifdef DPK_92D + short index_mapping_DPK[4][index_mapping_DPK_NUM]={ + {0, 0, 1, 2, 2, //path A current thermal > PG thermal + 3, 4, 5, 5, 6, + 7, 7, 8, 9, 9}, + {0, 0, -1, -2, -3, //path A current thermal < PG thermal + -3, -4, -5, -6, -6, + -7, -8, -9, -9, -10}, + {0, 0, 1, 2, 2, //path B current thermal > PG thermal + 3, 4, 5, 5, 6, + 7, 7, 8, 9, 9}, + {0, 0, -1, -2, -3, //path B current thermal < PG thermal + -3, -4, -5, -6, -6, + -7, -8, -9, -9, -10} + }; + + u8 delta_DPK; + short index_DPK[2] = { 0xb68, 0xb6c }, value_DPK, value_DPK_shift; + int j; + + if(priv->pshare->bDPKworking) { + DEBUG_INFO("DPK in progress abort tx power tracking \n"); + return; + } + +#endif + + +#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 + +u8 index_mapping_HighPower_PA[12][index_mapping_NUM] = { + {0, 2, 3, 4, 7, 8, 10, 12, 13, 15, 16, 17, 18}, //5G, path A/MAC 0, ch36-64, decrease power + {0, 2, 4, 7, 8, 10, 11, 15, 17, 19, 21, 23, 23}, //5G, path A/MAC 0, ch36-64, increase power + {0, 4, 5, 8, 9, 11, 14, 15, 16, 17, 18, 19, 20}, //5G, path A/MAC 0, ch100-140, decrease power + {0, 2, 4, 5, 7, 9, 13, 15, 19, 21, 22, 23, 23}, //5G, path A/MAC 0, ch100-140, increase power + {0, 4, 5, 8, 9, 11, 14, 15, 17, 18, 19, 20, 21}, //5G, path A/MAC 0, ch149-165, decrease power + {0, 2, 4, 6, 8, 10, 14, 16, 19, 21, 22, 24, 24}, //5G, path A/MAC 0, ch149-165, increase power + {0, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17}, //5G, path B/MAC 1, ch36-64, decrease power + {0, 2, 4, 7, 8, 10, 11, 15, 17, 19, 21, 23, 23}, //5G, path B/MAC 1, ch36-64, increase power + {0, 3, 4, 6, 7, 9, 12, 13, 14, 15, 17, 18, 19}, //5G, path B/MAC 1, ch100-140, decrease power + {0, 2, 4, 5, 7, 9, 13, 15, 19, 21, 22, 23, 23}, //5G, path B/MAC 1, ch100-140, increase power + {0, 3, 4, 6, 7, 9, 12, 13, 15, 16, 17, 18, 19}, //5G, path B/MAC 1, ch149-165, decrease power + {0, 3, 5, 7, 9, 11, 13, 17, 19, 21, 22, 23, 23}, //5G, path B/MAC 1, ch149-165, increase power + }; + +#endif + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel=priv->pshare->working_channel; + if(priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } +#if 0 + if (priv->pshare->pwr_trk_ongoing==0) { + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER_92D, bMask20Bits, 0x30000); + priv->pshare->pwr_trk_ongoing = 1; + return; + } + else +#endif + { + ThermalValue =(unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER_92D, 0xf800, 1); +// priv->pshare->pwr_trk_ongoing = 0; +#ifdef DPK_92D + priv->pshare->ThermalValue_DPKtrack = ThermalValue; +#endif + } + DEBUG_INFO("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx\n", ThermalValue, + priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther); + + if(is2T) + rf = 2; + else + rf = 1; + + if (ThermalValue) { + + //Query OFDM path A default setting + ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; ipshare->OFDM_index0[0] = i; + DEBUG_INFO("Initial pathA ele_D reg0x%x = 0x%lx, OFDM_index=0x%x\n", + rOFDM0_XATxIQImbalance, ele_D, priv->pshare->OFDM_index0[0]); + break; + } + } + + //Query OFDM path B default setting + if(is2T) { + ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D; + for(i=0; ipshare->OFDM_index0[1] = i; + DEBUG_INFO("Initial pathB ele_D reg0x%x = 0x%lx, OFDM_index=0x%x\n", + rOFDM0_XBTxIQImbalance, ele_D, priv->pshare->OFDM_index0[1]); + break; + } + } + } + + if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + priv->pshare->CCK_index0 = get_CCK_swing_index(priv); + } else { + priv->pshare->CCK_index0 = 12; + } + + if(!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_LCK = ThermalValue; + priv->pshare->ThermalValue_IQK = ThermalValue; +#ifdef RX_GAIN_TRACK_92D + priv->pshare->ThermalValue_RxGain = priv->pmib->dot11RFEntry.ther; +#endif +#ifdef DPK_92D + priv->pshare->ThermalValue_DPK = ThermalValue; +#endif + for(i = 0; i < rf; i++) + priv->pshare->OFDM_index[i] = priv->pshare->OFDM_index0[i]; + priv->pshare->CCK_index = priv->pshare->CCK_index0; + } + + + //calculate average thermal meter + { + priv->pshare->Thermal_log[priv->pshare->Thermal_idx] = ThermalValue; + priv->pshare->Thermal_idx = (priv->pshare->Thermal_idx+1)%8; + + for(i=0; i<8; i++) { + if(priv->pshare->Thermal_log[i]) { + ThermalValue_AVG += priv->pshare->Thermal_log[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) + ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count); + } + + + delta = RTL_ABS(ThermalValue, priv->pshare->ThermalValue); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); + +// printk("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", +// ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK); + + getDeltaValue(priv); + +#ifdef DPK_92D + + if(priv->pshare->bDPKstore) { + + priv->pshare->ThermalValue_DPK = ThermalValue; + delta_DPK = 0; + + for(j = 0; j < rf; j++) { + + if(priv->pshare->ThermalValue_DPKstore > priv->pmib->dot11RFEntry.ther) + value_DPK_shift = index_mapping_DPK[j*2][priv->pshare->ThermalValue_DPKstore- priv->pmib->dot11RFEntry.ther]; + else + value_DPK_shift = index_mapping_DPK[j*2+1][priv->pmib->dot11RFEntry.ther- priv->pshare->ThermalValue_DPKstore]; + + for(i = 0; i < index_mapping_DPK_NUM; i++) { + priv->pshare->index_mapping_DPK_current[j*2][i] = + index_mapping_DPK[j*2][i]-value_DPK_shift; + priv->pshare->index_mapping_DPK_current[j*2+1][i] = + index_mapping_DPK[j*2+1][i]-value_DPK_shift; + } + } + } + else + { + delta_DPK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_DPK); + } + + for(j = 0; j < rf; j++) { + if(!priv->pshare->bDPKdone[j]) + priv->pshare->OFDM_min_index_internalPA_DPK[j] = 0; + } + +#endif + +#if 1 + if ((delta_LCK > priv->pshare->Delta_LCK) && (priv->pshare->Delta_LCK != 0)) { + priv->pshare->ThermalValue_LCK = ThermalValue; + PHY_LCCalibrate_92D(priv); + } +#endif + if(delta > 0 +#ifdef DPK_92D + ||(priv->pshare->bDPKstore) +#endif + ){ + if(delta == 0 && priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + goto TxPowerDPK; +#ifdef DPK_92D + if(priv->pshare->bDPKstore) + priv->pshare->bDPKstore = FALSE; +#endif + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + + //calculate new OFDM / CCK offset + { + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G){ + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) + { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i] - get_tx_tracking_index(priv, channel, i, delta, 0, 0); + + CCK_index = priv->pshare->CCK_index - get_tx_tracking_index(priv, channel, 0, delta, 0, 1); + } + else + { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i] + get_tx_tracking_index(priv, channel, i, delta, 1, 0); + + CCK_index = priv->pshare->CCK_index + get_tx_tracking_index(priv, channel, i, delta, 1, 1); + } + } + else +#endif + { + offset = 4; + + if(delta > index_mapping_NUM-1) + index[0] = index_mapping[offset][index_mapping_NUM-1]; + else + index[0] = index_mapping[offset][delta]; + + if(ThermalValue > priv->pmib->dot11RFEntry.ther) { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i] - delta; + CCK_index = priv->pshare->CCK_index - delta; + } + else { + for(i = 0; i < rf; i++) + OFDM_index[i] = priv->pshare->OFDM_index[i] + index[0]; + CCK_index = priv->pshare->CCK_index + index[0]; + } + } + } else if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + for(i = 0; i < rf; i++){ + +#if defined(RTL8192D_INT_PA) + + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx==1) //MAC 1 5G + bInteralPA[i] = priv->pshare->phw->InternalPA5G[1]; + else + bInteralPA[i] = priv->pshare->phw->InternalPA5G[i]; + + if(bInteralPA[i]) { + if(priv->pshare->wlandev_idx == 1 || i == 1/*rf*/) + offset = 4; + else + offset = 0; + if(channel >= 100 && channel <= 165) + offset += 2; + } + else +#endif + { + if(priv->pshare->wlandev_idx == 1 || i == 1) + offset = 2; + else + offset = 0; + } + + +#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 + if(i == 0) + { + if(channel <= 99) + offset = 0; + else if(channel <= 140) + offset = 2; + else + offset = 4; + } + else + { + if(channel <= 99) + offset = 6; + else if(channel <= 140) + offset = 8; + else + offset = 10; + } +#endif + + + if(ThermalValue > priv->pmib->dot11RFEntry.ther) //set larger Tx power + offset++; +#if defined(RTL8192D_INT_PA) + if(bInteralPA[i]) { + if(delta > index_mapping_NUM-1) + index[i] = index_mapping_internalPA[offset][index_mapping_NUM-1]; + else + index[i] = index_mapping_internalPA[offset][delta]; + } else +#endif + { + if(delta > index_mapping_NUM-1) + index[i] = index_mapping[offset][index_mapping_NUM-1]; + else + index[i] = index_mapping[offset][delta]; + } + + + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) + { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) + index[i] = get_tx_tracking_index(priv, channel, i, delta, 0, 0); + else + index[i] = get_tx_tracking_index(priv, channel, i, delta, 1, 0); + } + else +#endif + { +#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 + { + if(delta > index_mapping_NUM-1) + index[i] = index_mapping_HighPower_PA[offset][index_mapping_NUM-1]; + else + index[i] = index_mapping_HighPower_PA[offset][delta]; + + //printk("\n\n offset = %d delta = %d \n", offset, delta); + //printk("index[%d]= %d\n\n", i, index[i]); + } +#endif + } + + + + if(ThermalValue > priv->pmib->dot11RFEntry.ther) //set larger Tx power + { +#if 0 + if(bInteralPA[i] && ThermalValue > 0x12) + index[i] = ((delta/2)*3+(delta%2)); +#endif + OFDM_index[i] = priv->pshare->OFDM_index[i] -index[i]; + } + else + { + OFDM_index[i] = priv->pshare->OFDM_index[i] + index[i]; + } + } + } + + if(is2T) + { + DEBUG_INFO("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + priv->pshare->OFDM_index[0], priv->pshare->OFDM_index[1], priv->pshare->CCK_index); + } + else + { + DEBUG_INFO("temp OFDM_A_index=0x%x, CCK_index=0x%x\n", + priv->pshare->OFDM_index[0], priv->pshare->CCK_index); + } + + for(i = 0; i < rf; i++) + { + if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1) { + OFDM_index[i] = OFDM_TABLE_SIZE_92D-1; + } + else if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + if (OFDM_index[i] < (OFDM_min_index_internalPA)) + OFDM_index[i] = (OFDM_min_index_internalPA); + } else if(bInteralPA[i]) { +#ifdef DPK_92D + if (OFDM_index[i] < (OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i])) + { + priv->pshare->TxPowerLevelDPK[i] = OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i]-OFDM_index[i]; + OFDM_index[i] = (OFDM_min_index_internalPA+ priv->pshare->OFDM_min_index_internalPA_DPK[i]); + } + else + { + priv->pshare->TxPowerLevelDPK[i] = 0; + } +#else + if (OFDM_index[i] < (OFDM_min_index_internalPA)) + { + OFDM_index[i] = (OFDM_min_index_internalPA); + } +#endif + } else if(OFDM_index[i] < OFDM_min_index) { +#ifdef HIGH_POWER_EXT_PA //Modify HP tracking table, from Arthur 2012.02.13 +#else + OFDM_index[i] = OFDM_min_index; +#endif + } + } + + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G){ + if(CCK_index > CCK_TABLE_SIZE_92D-1) + CCK_index = CCK_TABLE_SIZE_92D-1; + else if (CCK_index < 0) + CCK_index = 0; + } + + if(is2T) { + DEBUG_INFO("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], OFDM_index[1], CCK_index); + } + else + { + DEBUG_INFO("new OFDM_A_index=0x%x, CCK_index=0x%x\n", + OFDM_index[0], CCK_index); + } + } + + //Config by SwingTable + { + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable_92D[(unsigned int)OFDM_index[0]] & 0xFFC00000)>>22; + X = priv->pshare->RegE94; + Y = priv->pshare->RegE9C; + + if(X != 0 && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)){ + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); + + } + else + { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92D[(unsigned int)OFDM_index[0]]); + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); +#ifdef MP_TEST + if ((priv->pshare->rf_ft_var.mp_specific) && (!is2T)) { + unsigned char str[50]; + sprintf(str, "patha=%d,pathb=%d", priv->pshare->mp_txpwr_patha, priv->pshare->mp_txpwr_pathb); + mp_set_tx_power(priv, str); + } +#endif + } + DEBUG_INFO("TxPwrTracking for interface %d path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", + priv->pshare->wlandev_idx, X, Y, ele_A, ele_C, ele_D); + + + if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + { + //Adjust CCK according to IQK result + set_CCK_swing_index(priv, CCK_index); + } + + if(is2T) + { + ele_D = (OFDMSwingTable_92D[(unsigned int)OFDM_index[1]] & 0xFFC00000)>>22; + + //new element A = element D x X + X = priv->pshare->RegEB4; + Y = priv->pshare->RegEBC; + + if(X != 0 && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)){ + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D)>>8)&0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); + + } + else{ + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92D[(unsigned int)OFDM_index[1]]); + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); +#ifdef MP_TEST + if ((priv->pshare->rf_ft_var.mp_specific) ) { + unsigned char str[50]; + sprintf(str, "patha=%d,pathb=%d", priv->pshare->mp_txpwr_patha, priv->pshare->mp_txpwr_pathb); + mp_set_tx_power(priv, str); + + } +#endif + } + + DEBUG_INFO("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", + X, Y, ele_A, ele_C, ele_D); + } + + DEBUG_INFO("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", PHY_QueryBBReg(priv, 0xc80, bMaskDWord), + PHY_QueryBBReg(priv, 0xc94, bMaskDWord), PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x24, bMask20Bits,1)); + } + } + +TxPowerDPK: +#ifdef DPK_92D + { + char bNOPG = FALSE; + unsigned char pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevelHT40_1S_A[channel-1]; + if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) + pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_A[channel-1]; +#ifdef CONFIG_RTL_92D_DMDP + if ((priv->pmib->dot11RFEntry.macPhyMode==DUALMAC_DUALPHY) && + (priv->pshare->wlandev_idx == 1) && (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)) + pwrlevelHT40_1S_A = priv->pmib->dot11RFEntry.pwrlevel5GHT40_1S_B[channel-1]; + if (pwrlevelHT40_1S_A == 0) + bNOPG = TRUE; +#endif + + //for DPK + if(delta_DPK > 0 && !bNOPG /*&& pHalData->bDPKdone*/) { + for(i = 0; i < rf; i++) { + if(bInteralPA[i] && priv->pshare->bDPKdone[i]) { + if(ThermalValue > priv->pmib->dot11RFEntry.ther) + value_DPK = priv->pshare->index_mapping_DPK_current[i*2][ThermalValue-priv->pmib->dot11RFEntry.ther]; + else + value_DPK = priv->pshare->index_mapping_DPK_current[i*2+1][priv->pmib->dot11RFEntry.ther-ThermalValue]; + + PHY_SetBBReg(priv, index_DPK[i], 0x7c00, value_DPK); + } + } + priv->pshare->ThermalValue_DPK = ThermalValue; + } + } +#endif + priv->pshare->pwr_trk_ongoing = 0; +#if 1 + if ((delta_IQK > priv->pshare->Delta_IQK) && (priv->pshare->Delta_IQK != 0)) { + priv->pshare->ThermalValue_IQK = ThermalValue; + PHY_IQCalibrate(priv); + } +#endif + +#ifdef RX_GAIN_TRACK_92D + if(priv->pmib->dot11RFEntry.ther && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) && + (ThermalValue < priv->pmib->dot11RFEntry.ther)) { + priv->pshare->ThermalValue_RxGain = ThermalValue; + rx_gain_tracking_92D(priv); + } +#endif + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + } +} + +#endif + +//3 ============================================================ +//3 EDCA Turbo +//3 ============================================================ + +void init_EDCA_para(struct rtl8192cd_priv *priv, int mode) +{ + static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time; + + struct ParaRecord EDCA[4]; +#ifdef RTL_MANUAL_EDCA + //unsigned char acm_bitmap; +#endif + + slot_time = 20; + sifs_time = 10; + + if (mode & WIRELESS_11N) + sifs_time = 16; + +#ifdef RTL_MANUAL_EDCA + if( priv->pmib->dot11QosEntry.ManualEDCA ) { + memset(EDCA, 0, 4*sizeof(struct ParaRecord)); + if( OPMODE & WIFI_AP_STATE ) + memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord)); + else + memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord)); + + + if ((mode & WIRELESS_11N) || + (mode & WIRELESS_11G)) { + slot_time = 9; + } + + + RTL_W32(EDCA_VO_PARA, (EDCA[VO].TXOPlimit << 16) | (EDCA[VO].ECWmax << 12) | (EDCA[VO].ECWmin << 8) | (sifs_time + EDCA[VO].AIFSN * slot_time)); +#ifdef WIFI_WMM + if (QOS_ENABLE) + RTL_W32(EDCA_VI_PARA, (EDCA[VI].TXOPlimit << 16) | (EDCA[VI].ECWmax << 12) | (EDCA[VI].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); + else +#endif + RTL_W32(EDCA_VI_PARA, (EDCA[BE].TXOPlimit << 16) | (EDCA[BE].ECWmax << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); + + RTL_W32(EDCA_BE_PARA, (EDCA[BE].TXOPlimit << 16) | (EDCA[BE].ECWmax << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[BE].AIFSN * slot_time)); + + RTL_W32(EDCA_BK_PARA, (EDCA[BK].TXOPlimit << 16) | (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[BK].AIFSN * slot_time)); + }else +#endif //RTL_MANUAL_EDCA + { + memset(EDCA, 0, 4*sizeof(struct ParaRecord)); + /* copy BE, BK from static data */ + if( OPMODE & WIFI_AP_STATE ) + memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord)); + else + memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord)); + + /* VI, VO apply settings in AG by default */ + if( OPMODE & WIFI_AP_STATE ) + memcpy(&EDCA[2], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); + else + memcpy(&EDCA[2], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord)); + + if ((mode & WIRELESS_11N) || + (mode & WIRELESS_11G)) { + slot_time = 9; + } else { + /* replace with settings in B */ + if( OPMODE & WIFI_AP_STATE ) + memcpy(&EDCA[2], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord)); + else + memcpy(&EDCA[2], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord)); + } + VO_TXOP = EDCA[VO].TXOPlimit; + VI_TXOP = EDCA[VI].TXOPlimit; + + RTL_W32(EDCA_VO_PARA, (VO_TXOP << 16) | (EDCA[VO].ECWmax << 12) | (EDCA[VO].ECWmin << 8) | (sifs_time + EDCA[VO].AIFSN * slot_time)); +#ifdef WIFI_WMM + if (QOS_ENABLE) + RTL_W32(EDCA_VI_PARA, (VI_TXOP << 16) | (EDCA[VI].ECWmax << 12) | (EDCA[VI].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); + else +#endif + RTL_W32(EDCA_VI_PARA, (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[VI].AIFSN * slot_time)); + + RTL_W32(EDCA_BE_PARA, ((EDCA[BE].ECWmax) << 12) | (EDCA[BE].ECWmin << 8) | (sifs_time + EDCA[BE].AIFSN * slot_time)); + RTL_W32(EDCA_BK_PARA, (EDCA[BK].ECWmax << 12) | (EDCA[BK].ECWmin << 8) | (sifs_time + EDCA[BK].AIFSN * slot_time)); + + + RTL_W8(ACMHWCTRL, 0x00); + } + + priv->pshare->iot_mode_enable = 0; + if (priv->pshare->rf_ft_var.wifi_beq_iot) + priv->pshare->iot_mode_VI_exist = 0; + priv->pshare->iot_mode_VO_exist = 0; + +#ifdef WMM_VIBE_PRI + priv->pshare->iot_mode_BE_exist = 0; +#endif +#ifdef WMM_BEBK_PRI + priv->pshare->iot_mode_BK_exist = 0; +#endif +#ifdef LOW_TP_TXOP + priv->pshare->BE_cwmax_enhance = 0; +#endif +} +#if 0 +void choose_IOT_main_sta(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int i, assoc_num = GET_ROOT(priv)->assoc_num; +#ifdef MBSSID + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ + for (i=0; ipvap_priv[i]-> assoc_num; + } +#endif +#ifdef UNIVERSAL_REPEATER + if (IS_DRV_OPEN(GET_VXD_PRIV(GET_ROOT(priv)))) + assoc_num += GET_VXD_PRIV(GET_ROOT(priv))-> assoc_num; +#endif +#ifdef WDS + if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) + assoc_num ++; +#endif + + if (priv->pshare->rf_ft_var.low_tp_no_aggr) { + unsigned long sta_tp = (pstat->current_tx_bytes + pstat->current_rx_bytes) >> 17; + if (!pstat->low_tp_disable_ampdu && sta_tp <= 2) + pstat->low_tp_disable_ampdu = 1; + else if (pstat->low_tp_disable_ampdu && sta_tp >= 5) + pstat->low_tp_disable_ampdu = 0; + } + + if ((GET_ROOT(priv)->up_time % 2) == 0) { + unsigned int tx_2s_avg = 0; + unsigned int rx_2s_avg = 0; + int i=0, aggReady=0; + unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes); + + pstat->current_tx_bytes += pstat->tx_byte_cnt; + pstat->current_rx_bytes += pstat->rx_byte_cnt; + + if (total_sum != 0) { + if (total_sum <= 1000000) { + tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum); + rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum); + } else { + tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100)); + rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100)); + } + } + + for(i=0; i<8; i++) + aggReady += (pstat->ADDBA_ready[i]); + + if( (pstat->IOTPeer==HT_IOT_PEER_INTEL) + || (pstat->ht_cap_len && aggReady)) { + + if ((assoc_num==1) || (tx_2s_avg + rx_2s_avg >= 25)) { + priv->pshare->highTP_found_pstat = pstat; + } /*this STA's TXRX packet very close AP's total TXRX packet then let it as highTP_found_pstat*/ + else if(RTL_ABS((pstat->current_tx_bytes + pstat->current_rx_bytes) , total_sum)<50){ + priv->pshare->highTP_found_pstat = pstat; + } +#ifdef CLIENT_MODE + if (OPMODE & WIFI_STATION_STATE) { +// if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45)) + if(pstat->IOTPeer == HT_IOT_PEER_RALINK && ((tx_2s_avg + rx_2s_avg) >= 45)) + priv->pshare->highTP_found_pstat = pstat; + } +#endif + } + } + else { + pstat->current_tx_bytes = pstat->tx_byte_cnt; + pstat->current_rx_bytes = pstat->rx_byte_cnt; + } +} +#endif + +void rxBB_dm(struct rtl8192cd_priv *priv) +{ + if ((priv->up_time % 3) == 1) { + if (priv->pshare->rssi_min != 0xff) { + if (priv->pshare->rf_ft_var.dig_enable) { + // for DIG checking + check_DIG_by_rssi(priv, priv->pshare->rssi_min); + } +//#ifdef INTERFERENCE_CONTROL + if (priv->pshare->rf_ft_var.nbi_filter_enable) { + check_NBI_by_rssi(priv, priv->pshare->rssi_min); + } +//#endif + } + +#ifdef MP_TEST + if (!((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific)) +#endif + { +#ifdef HIGH_POWER_EXT_LNA + if (!priv->pshare->rf_ft_var.use_ext_lna) +#endif + CCK_CCA_dynamic_enhance(priv, priv->pshare->rssi_min); + } + } + if (priv->pshare->rf_ft_var.adaptivity_enable){ + unsigned char IGI; + IGI = RTL_R8(0xc50); + rtl8192cd_Adaptivity(priv,IGI); + } +} + +/* + * IOT related functions + */ +void IOT_engine(struct rtl8192cd_priv *priv) +{ +#ifdef WIFI_WMM + unsigned int switch_turbo = 0; +#endif +#ifdef MBSSID + int i; +#endif + int assoc_num = priv->assoc_num; + struct stat_info *pstat = priv->pshare->highTP_found_pstat; + + if(pstat) { + if((pstat->tx_avarage + pstat->rx_avarage) < (1<<17)) // 1M bps + pstat = NULL; + } +#if defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM) + if(priv->pmib->dot11QosEntry.ManualEDCA) + return ; +#endif + +#ifdef MBSSID + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){ + for (i=0; ipvap_priv[i]-> assoc_num; + } +#endif +#ifdef UNIVERSAL_REPEATER + if (IS_DRV_OPEN(GET_VXD_PRIV(GET_ROOT(priv)))) + assoc_num += GET_VXD_PRIV(GET_ROOT(priv))-> assoc_num; +#endif +#ifdef WDS + if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled) + assoc_num ++; +#endif + +#ifdef WIFI_WMM + if (QOS_ENABLE) { + if (!priv->pmib->dot11OperationEntry.wifi_specific || + ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))) { + if (priv->pshare->iot_mode_enable && + ((priv->pshare->phw->VO_pkt_count > 50) || + (priv->pshare->phw->VI_pkt_count > 50) || + (priv->pshare->phw->BK_pkt_count > 50))) { + priv->pshare->iot_mode_enable = 0; + switch_turbo++; + } else if ((!priv->pshare->iot_mode_enable) && + ((priv->pshare->phw->VO_pkt_count < 50) && + (priv->pshare->phw->VI_pkt_count < 50) && + (priv->pshare->phw->BK_pkt_count < 50))) { + priv->pshare->iot_mode_enable++; + switch_turbo++; + } + } + + if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { + if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) { + priv->pshare->iot_mode_VO_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) { + priv->pshare->iot_mode_VO_exist = 0; + switch_turbo++; + } + +#ifdef WMM_VIBE_PRI + if (priv->pshare->iot_mode_VO_exist) { + //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count); + if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) { + priv->pshare->iot_mode_BE_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) { + priv->pshare->iot_mode_BE_exist = 0; + switch_turbo++; + } + } +#endif + +#ifdef WMM_BEBK_PRI + if (priv->pshare->phw->BE_pkt_count) { + //printk("[%s %d] BK_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BK_pkt_count); + if (!priv->pshare->iot_mode_BK_exist && (priv->pshare->phw->BK_pkt_count > 250)) { + priv->pshare->iot_mode_BK_exist++; + switch_turbo++; + EDEBUG("switch_turbo++\n"); + } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BK_pkt_count < 250)) { + priv->pshare->iot_mode_BK_exist = 0; + switch_turbo++; + EDEBUG("switch_turbo++\n"); + } + } +#endif + + if (priv->pshare->rf_ft_var.wifi_beq_iot) { + if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) { + priv->pshare->iot_mode_VI_exist++; + switch_turbo++; + } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) { + priv->pshare->iot_mode_VI_exist = 0; + switch_turbo++; + } + } + +#ifdef CONFIG_RTL_92D_DMDP + if ((GET_CHIP_VER(priv) == VERSION_8192D) && (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) { + unsigned int tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); + if (priv->pshare->rf_ft_var.wifi_beq_iot) { + if (priv->pshare->wifi_beq_lower && priv->pshare->iot_mode_VI_exist && tp <= 20) { + priv->pshare->wifi_beq_lower= 0; + switch_turbo++; + } else if (!priv->pshare->wifi_beq_lower&& (!priv->pshare->iot_mode_VI_exist || tp > 20)) { + priv->pshare->wifi_beq_lower= 1; + switch_turbo++; + } + } + } +#endif + } + +#ifdef CLIENT_MODE + if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) + { + if (priv->pshare->iot_mode_enable && + (((priv->pshare->phw->VO_pkt_count > 50) || + (priv->pshare->phw->VI_pkt_count > 50) || + (priv->pshare->phw->BK_pkt_count > 50)) || + (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3])))) + { + priv->pshare->iot_mode_enable = 0; + switch_turbo++; + } + else if ((!priv->pshare->iot_mode_enable) && + (((priv->pshare->phw->VO_pkt_count < 50) && + (priv->pshare->phw->VI_pkt_count < 50) && + (priv->pshare->phw->BK_pkt_count < 50)) && + (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3])))) + { + priv->pshare->iot_mode_enable++; + switch_turbo++; + } + } +#endif + + priv->pshare->phw->VO_pkt_count = 0; + priv->pshare->phw->VI_pkt_count = 0; + if (priv->pshare->rf_ft_var.wifi_beq_iot) + priv->pshare->phw->VI_rx_pkt_count = 0; + priv->pshare->phw->BK_pkt_count = 0; +#ifdef WMM_VIBE_PRI + priv->pshare->phw->BE_pkt_count = 0; +#endif + } +#endif + + if ((priv->up_time % 2) == 0) { + /* + * decide EDCA content for different chip vendor + */ +#ifdef WIFI_WMM + if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || + ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) +#ifdef CLIENT_MODE + || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2)) +#endif + )) { + if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) { +#ifdef LOW_TP_TXOP + + + if (pstat->IOTPeer==HT_IOT_PEER_INTEL) + + { + + if (priv->pshare->txop_enlarge != 0xe) { + priv->pshare->txop_enlarge = 0xe; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } + } else if (priv->pshare->txop_enlarge != 2) { + priv->pshare->txop_enlarge = 2; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } +#else //LOW_TP_TXOP + + if (priv->pshare->txop_enlarge != 2) { + + + { + if (pstat->IOTPeer==HT_IOT_PEER_INTEL) + priv->pshare->txop_enlarge = 0xe; + else if (pstat->IOTPeer==HT_IOT_PEER_RALINK) + priv->pshare->txop_enlarge = 0xd; + else + priv->pshare->txop_enlarge = 2; + + } + + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } +#endif //LOW_TP_TXOP + } else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) { + if (priv->pshare->txop_enlarge) { + priv->pshare->txop_enlarge = 0; + if (priv->pshare->iot_mode_enable) + switch_turbo++; + } + } +#ifdef LOW_TP_TXOP + // for Intel IOT, need to enlarge CW MAX from 6 to 10 + + + if (pstat && pstat->IOTPeer==HT_IOT_PEER_INTEL && (((pstat->tx_avarage+pstat->rx_avarage)>>10) < + priv->pshare->rf_ft_var.cwmax_enhance_thd)) + + { + if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable) { + priv->pshare->BE_cwmax_enhance = 1; + switch_turbo++; + } + } else { + if (priv->pshare->BE_cwmax_enhance) { + priv->pshare->BE_cwmax_enhance = 0; + switch_turbo++; + } + } +#endif + } +#endif + + priv->pshare->current_tx_bytes = 0; + priv->pshare->current_rx_bytes = 0; + } + +#ifdef SW_TX_QUEUE + if ((assoc_num > 1) && (AMPDU_ENABLE)) + { + unsigned int total_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17)+(unsigned int)(priv->ext_stats.rx_avarage>>17); + if(total_tp > 0) { + if (((unsigned int)(priv->ext_stats.tx_avarage>>17) * 100/total_tp) > 30) + { + if (priv->pshare->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd) + { + if ((priv->pshare->swq_en == 0)) + { + switch_turbo++; + if (priv->pshare->txop_enlarge == 0) + priv->pshare->txop_enlarge = 2; + priv->pshare->swq_en = 1; + priv->pshare->swqen_keeptime = priv->up_time; + } + else + { + if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) + { + priv->pshare->txop_enlarge = 2; + switch_turbo--; + } + } + } + else if(priv->pshare->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd) + { + priv->pshare->swq_en = 0; + priv->pshare->swqen_keeptime = 0; + } + else if ((priv->pshare->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)) + { + priv->pshare->txop_enlarge = 2; + switch_turbo--; + } + } + else if (((unsigned int)(priv->ext_stats.tx_avarage>>17) * 100/total_tp) < 20) + { + priv->pshare->swq_en = 0; + priv->pshare->swqen_keeptime = 0; + } + } + //debug msg + //printk("swq=%d,sw=%d,en=%d,mode=%d\n", priv->pshare->swq_en, switch_turbo, priv->pshare->txop_enlarge, priv->pshare->iot_mode_enable); + } +#if 1//defined(CONFIG_RTL_819XD) + else if( (assoc_num == 1) && (priv->up_time % 2)== 0 && (AMPDU_ENABLE) ) { + //if (pstat) { +// if ((pstat) && pstat->is_intel_sta) { + if ((pstat) && pstat->IOTPeer == HT_IOT_PEER_INTEL) { +// int en_thd = 14417920; + //if ((priv->pshare->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) ) { //50Mbps + if ((pstat->current_tx_bytes > 14417920) && (priv->pshare->swq_en == 0)) { // && (pstat->current_rx_bytes > 14417920) && (priv->pshare->swq_en == 0)) { //55Mbps + priv->pshare->swq_en = 1; + priv->pshare->swqen_keeptime = priv->up_time; + } + //else if ((priv->pshare->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps + else if ((pstat->tx_avarage < 9175040) && (priv->pshare->swq_en == 1)) { //35Mbps + priv->pshare->swq_en = 0; + priv->pshare->swqen_keeptime = 0; + } + } + else { + priv->pshare->swq_en = 0; + priv->pshare->swqen_keeptime = 0; + } + } +#endif +#endif + +#ifdef WIFI_WMM +#ifdef LOW_TP_TXOP + if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)) + && QOS_ENABLE) { + + if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) { + unsigned int thd_tp; + unsigned char under_thd; + unsigned int curr_tp; + + if (priv->pmib->dot11BssType.net_work_type & (WIRELESS_11N | WIRELESS_11G)) + { + // Determine the upper bound throughput threshold. + if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) { + if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num) + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; + else + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n; + } + else + thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g; + + // Determine to close txop. +#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + if(pstat && pstat->expire_to) + { + struct rtl8192cd_priv *tmppriv; + struct aid_obj *aidarray; + aidarray = container_of(pstat, struct aid_obj, station); + tmppriv = aidarray->priv; + + curr_tp = (unsigned int)(tmppriv->ext_stats.tx_avarage>>17) + (unsigned int)(tmppriv->ext_stats.rx_avarage>>17); + } + else +#endif + curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17); + if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low) + under_thd = 1; + else + under_thd = 0; + } + else + { + under_thd = 0; + } + + if (switch_turbo) { + priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + } else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) { + priv->pshare->rf_ft_var.low_tp_txop_count++; + if (priv->pshare->rf_ft_var.low_tp_txop_close) { + priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay; + } + if (priv->pshare->rf_ft_var.low_tp_txop_count == priv->pshare->rf_ft_var.low_tp_txop_delay) { + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + priv->pshare->rf_ft_var.low_tp_txop_close = under_thd; + switch_turbo++; + } + } else { + priv->pshare->rf_ft_var.low_tp_txop_count = 0; + } + } + } +#endif + + if (switch_turbo) + IOT_EDCA_switch(priv, priv->pmib->dot11BssType.net_work_type, priv->pshare->iot_mode_enable); +#endif +} + + +#ifdef WIFI_WMM +void IOT_EDCA_switch(struct rtl8192cd_priv *priv, int mode, char enable) +{ + unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94; + unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs; + + if (!(!priv->pmib->dot11OperationEntry.wifi_specific || + ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) +#ifdef CLIENT_MODE + || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific)) +#endif + )) + return; + + if ((mode & WIRELESS_11N) && (priv->pshare->ht_sta_num +#ifdef WDS + || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) +#endif + )) + sifs_time = 16; + + if (mode & (WIRELESS_11G | WIRELESS_11N)) { + slot_time = 9; + } else { + BE_TXOP = 94; + VI_TXOP = 188; + } + +#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + if (priv->pshare->is_40m_bw) + { + BE_TXOP = 23; + } +#endif + + if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) { + if (priv->pshare->iot_mode_VO_exist) { +#ifdef WMM_VIBE_PRI + if (priv->pshare->iot_mode_BE_exist) { + vi_cw_max = 5; + vi_cw_min = 3; + vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); + } else +#endif + { + vi_cw_max = 6; + vi_cw_min = 4; + vi_aifs = 0x2b; + } + } else { + vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time); + } + + RTL_W32(EDCA_VI_PARA, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16) + | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs); + +#ifdef WMM_BEBK_PRI +#ifdef CONFIG_RTL_88E_SUPPORT + if ((GET_CHIP_VER(priv) == VERSION_8188E ) && priv->pshare->iot_mode_BK_exist) { + RTL_W32(EDCA_BK_PARA, (10 << 12) | (6 << 8) | 0x4f); + } +#endif +#endif + } + + if (!enable || (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist)) { + if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist) { +#ifdef CONFIG_RTL_92D_DMDP + if ((GET_CHIP_VER(priv) == VERSION_8192D) && (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)) { + if (priv->pshare->wifi_beq_lower) + RTL_W32(EDCA_BE_PARA, (10 << 12) | (4 << 8) | (sifs_time + 10 * slot_time)); + else + RTL_W32(EDCA_BE_PARA, (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); + } else +#endif + RTL_W32(EDCA_BE_PARA, (10 << 12) | (4 << 8) | 0x4f); + } else { + RTL_W32(EDCA_BE_PARA, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8) + | (sifs_time + 3 * slot_time)); + } + RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); + } else { +#ifdef LOW_TP_TXOP + int txop; + unsigned int cw_max; + unsigned int txop_close; + + cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6); + txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0); + txop = (txop_close ? 0 : (BE_TXOP*2)); +#endif + if (priv->pshare->ht_sta_num +#ifdef WDS + || ((OPMODE & WIFI_AP_STATE) && (mode & WIRELESS_11N) && + priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum) +#endif + ) { +/* + if (priv->pshare->txop_enlarge == 0xf) { + // is 8192S client + RTL_W32(EDCA_BE_PARA, ((BE_TXOP*2) << 16) | + (6 << 12) | (4 << 8) | (sifs_time + slot_time+ 0xf)); // 0xf is 92s circuit delay + priv->pshare->txop_enlarge = 2; + } + else +*/ + if (priv->pshare->txop_enlarge == 0xe) { +#ifndef LOW_TP_TXOP + // is intel client, use a different edca value +#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); +#else + //RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (4 << 8) | 0x1f); + if (get_rf_mimo_mode(priv) == MIMO_1T1R) + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); + else + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (8 << 12) | (5 << 8) | 0x1f); + + RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) & ~(DIS_TXOP_CFE)); +#endif + priv->pshare->txop_enlarge = 2; + } else if (priv->pshare->txop_enlarge == 0xd) { + // is intel ralink, use a different edca value + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (4 << 12) | (3 << 8) | 0x19); + priv->pshare->txop_enlarge = 2; + } else { + if (priv->pshare->txop_enlarge == 0) + RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); + + if (get_rf_mimo_mode(priv) == MIMO_2T2R) +#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | + (6 << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); +#else + RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | + (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); +#endif + else +#if 0 //defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | + (5 << 12) | (4 << 8) | (sifs_time + 2 * slot_time)); +#else + RTL_W32(EDCA_BE_PARA, ((BE_TXOP*priv->pshare->txop_enlarge) << 16) | + (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time)); +#endif + +#else + // is intel client, use a different edca value + if (get_rf_mimo_mode(priv) == MIMO_1T1R) + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | 0x1f); + else + RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | 0x1f); + } else { + txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge)); + + if (get_rf_mimo_mode(priv) == MIMO_2T2R) + RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); + else + RTL_W32(EDCA_BE_PARA, (txop << 16) | (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | + (3 << 8) | (sifs_time + 2 * slot_time)); +#endif + } + } else { +#ifdef LOW_TP_TXOP + RTL_W32(EDCA_BE_PARA, (txop << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); +#else +#if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8197DL) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA)) + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (5 << 8) | (sifs_time + 3 * slot_time)); +#else + RTL_W32(EDCA_BE_PARA, (BE_TXOP*2 << 16) | (6 << 12) | (4 << 8) | (sifs_time + 3 * slot_time)); +#endif + if (priv->pshare->txop_enlarge == 0xe) + RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) & ~(DIS_TXOP_CFE)); + else + RTL_W16(RD_CTRL, RTL_R16(RD_CTRL) | DIS_TXOP_CFE); +#endif + } +/* + if (priv->pmib->dot11OperationEntry.wifi_specific == 2) { + RTL_W16(NAV_PROT_LEN, 0x01C0); + RTL_W8(CFEND_TH, 0xFF); + set_fw_reg(priv, 0xfd000ab0, 0, 0); + } +*/ + } +} + +//end of IOT_EDCA_switch +//======================================================================================================== + +#if 0 +void check_NAV_prot_len(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned int disassoc) +{ + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat + && pstat->ht_cap_len && pstat->is_intel_sta) { + if (!disassoc && (pstat->MIMO_ps & _HT_MIMO_PS_DYNAMIC_)) { + setSTABitMap(&priv->pshare->mimo_ps_dynamic_sta, pstat->aid); + } else { + clearSTABitMap(&priv->pshare->mimo_ps_dynamic_sta, pstat->aid); + } + +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv) != VERSION_8188E) +#endif + { + if (orSTABitMap(&priv->pshare->mimo_ps_dynamic_sta) { + RTL_W8(NAV_PROT_LEN, 0x40); + } else { + RTL_W8(NAV_PROT_LEN, 0x20); + } + } + } +} +#endif +#endif + + +//3 ============================================================ +//3 FA statistic functions +//3 ============================================================ +#if 0 + +#if !defined(CONFIG_RTL_NEW_AUTOCH) +static +#endif +void reset_FA_reg(struct rtl8192cd_priv *priv) +{ +#if !defined(CONFIG_RTL_NEW_AUTOCH) + unsigned char value8; + + value8 = RTL_R8(0xd03); + RTL_W8(0xd03, value8 | 0x08); // regD00[27]=1 to reset these OFDM FA counters + value8 = RTL_R8(0xd03); + RTL_W8(0xd03, value8 & 0xF7); // regD00[27]=0 to start counting + value8 = RTL_R8(0xa2d); + RTL_W8(0xa2d, value8 & 0x3F); // regA2D[7:6]=00 to disable counting + value8 = RTL_R8(0xa2d); + RTL_W8(0xa2d, value8 | 0x80); // regA2D[7:6]=10 to enable counting +#else + /* cck CCA */ + PHY_SetBBReg(priv, 0xa2c, BIT(13) | BIT(12), 0); + PHY_SetBBReg(priv, 0xa2c, BIT(13) | BIT(12), 2); + /* cck FA*/ + PHY_SetBBReg(priv, 0xa2c, BIT(15) | BIT(14), 0); + PHY_SetBBReg(priv, 0xa2c, BIT(15) | BIT(14), 2); + /* ofdm */ + PHY_SetBBReg(priv, 0xd00, BIT(27), 1); + PHY_SetBBReg(priv, 0xd00, BIT(27), 0); +#endif + +#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) + if (GET_CHIP_VER(priv) == VERSION_8192D){ + PHY_SetBBReg(priv, 0xf14, BIT(16),1); + PHY_SetBBReg(priv, 0xf14, BIT(16),0); + RTL_W32(RXERR_RPT, RTL_R32(RXERR_RPT)|BIT(27)); + RTL_W32(RXERR_RPT, RTL_R32(RXERR_RPT)&(~BIT(27))); + } +#endif + +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8188E) { + PHY_SetBBReg(priv, 0xc0c, BIT(31), 1); + PHY_SetBBReg(priv, 0xc0c, BIT(31), 0); + } +#endif +} + +#if defined(CONFIG_RTL_NEW_AUTOCH) +void hold_CCA_FA_counter(struct rtl8192cd_priv *priv) +{ + /* hold cck CCA & FA counter */ + PHY_SetBBReg(priv, 0xa2c, BIT(12), 1); + PHY_SetBBReg(priv, 0xa2c, BIT(14), 1); + + /* hold ofdm CCA & FA counter */ + PHY_SetBBReg(priv, 0xc00, BIT(31), 1); + PHY_SetBBReg(priv, 0xd00, BIT(31), 1); +} + +void release_CCA_FA_counter(struct rtl8192cd_priv *priv) +{ + /* release cck CCA & FA counter */ + PHY_SetBBReg(priv, 0xa2c, BIT(12), 0); + PHY_SetBBReg(priv, 0xa2c, BIT(14), 0); + + /* release ofdm CCA & FA counter */ + PHY_SetBBReg(priv, 0xc00, BIT(31), 0); + PHY_SetBBReg(priv, 0xd00, BIT(31), 0); + +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8188E) { + PHY_SetBBReg(priv, 0xc0c, BIT(31), 1); + PHY_SetBBReg(priv, 0xc0c, BIT(31), 0); + } +#endif +} + + +void _FA_statistic(struct rtl8192cd_priv *priv) +{ + // read OFDM FA counters + priv->pshare->ofdm_FA_cnt1 = RTL_R16(0xda2); + priv->pshare->ofdm_FA_cnt2 = RTL_R16(0xda4); + priv->pshare->ofdm_FA_cnt3 = RTL_R16(0xda6); + priv->pshare->ofdm_FA_cnt4 = RTL_R16(0xda8); + + priv->pshare->cck_FA_cnt = (RTL_R8(0xa5b) << 8) + RTL_R8(0xa5c); + +#ifdef INTERFERENCE_CONTROL + priv->pshare->ofdm_FA_total_cnt = (unsigned int) priv->pshare->ofdm_FA_cnt1 + + priv->pshare->ofdm_FA_cnt2 + priv->pshare->ofdm_FA_cnt3 + + priv->pshare->ofdm_FA_cnt4 + RTL_R16(0xcf0) + RTL_R16(0xcf2); + + priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_total_cnt + priv->pshare->cck_FA_cnt; +#else + priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + + priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4 + + priv->pshare->cck_FA_cnt + RTL_R16(0xcf0) + RTL_R16(0xcf2); +#endif +} +#endif + +void FA_statistic(struct rtl8192cd_priv *priv) +{ + +#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) + if (GET_CHIP_VER(priv) == VERSION_8192D){ +// priv->pshare->F90_cnt = PHY_QueryBBReg(priv, 0xf90, bMaskHWord); + priv->pshare->F94_cnt = PHY_QueryBBReg(priv, 0xf94, bMaskHWord); + priv->pshare->F94_cntOK = PHY_QueryBBReg(priv, 0xf94, bMaskLWord); + RTL_W32(RXERR_RPT,(RTL_R32(RXERR_RPT)&0x0fffffff)|0x70000000); + priv->pshare->Reg664_cnt = RTL_R32(RXERR_RPT) & 0xfffff; + RTL_W32(RXERR_RPT,(RTL_R32(RXERR_RPT)&0x0fffffff)|0x60000000); + priv->pshare->Reg664_cntOK = RTL_R32(RXERR_RPT) & 0xfffff; + } +#endif + +#if !defined(CONFIG_RTL_NEW_AUTOCH) + signed char value8; + + // read OFDM FA counters + priv->pshare->ofdm_FA_cnt1 = RTL_R16(0xda2); + priv->pshare->ofdm_FA_cnt2 = RTL_R16(0xda4); + priv->pshare->ofdm_FA_cnt3 = RTL_R16(0xda6); + priv->pshare->ofdm_FA_cnt4 = RTL_R16(0xda8); + + // read the CCK FA counters + value8 = RTL_R8(0xa2d); + RTL_W8(0xa2d, value8 | 0x40); // regA2D[6]=1 to hold and read the CCK FA counters + priv->pshare->cck_FA_cnt = RTL_R8(0xa5b); + priv->pshare->cck_FA_cnt = priv->pshare->cck_FA_cnt << 8; + priv->pshare->cck_FA_cnt += RTL_R8(0xa5c); +#ifdef INTERFERENCE_CONTROL + priv->pshare->ofdm_FA_total_cnt = (unsigned int) priv->pshare->ofdm_FA_cnt1 + + priv->pshare->ofdm_FA_cnt2 + priv->pshare->ofdm_FA_cnt3 + + priv->pshare->ofdm_FA_cnt4 + RTL_R16(0xcf0) + RTL_R16(0xcf2); + + priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_total_cnt + priv->pshare->cck_FA_cnt; +#else + + priv->pshare->FA_total_cnt = priv->pshare->ofdm_FA_cnt1 + priv->pshare->ofdm_FA_cnt2 + + priv->pshare->ofdm_FA_cnt3 + priv->pshare->ofdm_FA_cnt4 + + priv->pshare->cck_FA_cnt + RTL_R16(0xcf0) + RTL_R16(0xcf2); +#endif + if (priv->pshare->rf_ft_var.rssi_dump) + priv->pshare->CCA_total_cnt = ((RTL_R8(0xa60)<<8)|RTL_R8(0xa61)) + RTL_R16(0xda0); +#else + hold_CCA_FA_counter(priv); + _FA_statistic(priv); + + if (priv->pshare->rf_ft_var.rssi_dump) + priv->pshare->CCA_total_cnt = ((RTL_R8(0xa60)<<8)|RTL_R8(0xa61)) + RTL_R16(0xda0); + + release_CCA_FA_counter(priv); +#endif + + reset_FA_reg(priv); + +#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) + if (GET_CHIP_VER(priv) == VERSION_8192D){ + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G && !(OPMODE & WIFI_SITE_MONITOR)) { + if (priv->pshare->DNC_on == 0){ + //if ((priv->pshare->F94_cnt + priv->pshare->F90_cnt)> 3000){ + /* Reg 664: x > y && x > 1000 + Reg F94: x > 0.75*y && x > 1000 */ + if (((priv->pshare->Reg664_cnt>priv->pshare->Reg664_cntOK) && (priv->pshare->Reg664_cnt > 1000))|| + ((priv->pshare->F94_cnt > ((priv->pshare->Reg664_cntOK*3)>>2)) && (priv->pshare->F94_cnt > 1000))) { + priv->ext_stats.tp_average_pre = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; + priv->pshare->DNC_on = 1; + priv->pshare->DNC_chk_cnt = 1; + priv->pshare->DNC_chk = 2; // 0: don't check, 1; check, 2: just entering DNC + //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07600760); + PHY_SetBBReg(priv, 0xc50, bMaskByte0, 0x20); + PHY_SetBBReg(priv, 0xc58, bMaskByte0, 0x20); + //printk("Dynamic Noise Control ON\n"); + } + } else { + if ((priv->pshare->DNC_chk_cnt % 5)==0){ // check every 5*2=10 seconds + unsigned long tp_now = (priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage)>>17; + priv->pshare->DNC_chk_cnt = 0; + + if ((priv->pshare->DNC_chk == 2) && (tp_now < priv->ext_stats.tp_average_pre+5)){ + //no advantage, leave DNC state + priv->pshare->DNC_on = 0; + priv->pshare->DNC_chk = 0; + //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); + } + else + { + priv->pshare->DNC_chk = 0; + + /* If TP < 20M or TP varies more than 5M. Start Checking...*/ + if ((tp_now < 20) || ((tp_now < (priv->ext_stats.tp_average_pre-5))|| (tp_now > (priv->ext_stats.tp_average_pre+5)))){ + priv->pshare->DNC_chk = 1; + //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); + if (!timer_pending(&priv->dnc_timer)) { + //printk("... Start Check Noise ...\n"); + mod_timer(&priv->dnc_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); // 100 ms + } + } + } + + priv->ext_stats.tp_average_pre = tp_now; + + } else if ((priv->pshare->DNC_chk_cnt % 5)==1 && priv->pshare->DNC_chk == 1) { + priv->pshare->DNC_chk = 0; + //if ((priv->pshare->F94_cnt + priv->pshare->F90_cnt) < 120) { + if ((priv->pshare->F94_cnt + priv->pshare->Reg664_cnt) < 120) { + priv->pshare->DNC_on = 0; + //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0); + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000700); + //printk("Dynamic Noise Control OFF\n"); + } + } + priv->pshare->DNC_chk_cnt++; + } + } + } +#endif +} + + +//3 ============================================================ +//3 Rate Adaptive +//3 ============================================================ + +void check_RA_by_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int level = 0; + + switch (pstat->rssi_level) { + case 1: + if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) + level = 1; + else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || + ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && + (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && + (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) + level = 2; + else + level = 3; + break; + case 2: + if (pstat->rssi > priv->pshare->rf_ft_var.raGoUpUpper) + level = 1; + else if ((pstat->rssi < priv->pshare->rf_ft_var.raGoDown40MLower) || + ((!pstat->ht_cap_len || !priv->pshare->is_40m_bw || + !(pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_))) && + (pstat->rssi < priv->pshare->rf_ft_var.raGoDown20MLower))) + level = 3; + else + level = 2; + break; + case 3: + if (pstat->rssi > priv->pshare->rf_ft_var.raGoUpUpper) + level = 1; + else if ((pstat->rssi > priv->pshare->rf_ft_var.raGoUp20MLower) || + ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && + (pstat->rssi > priv->pshare->rf_ft_var.raGoUp40MLower) && + (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) + level = 2; + else + level = 3; + break; + default: + if (isErpSta(pstat)) + DEBUG_ERR("wrong rssi level setting\n"); + break; + } + + if (level != pstat->rssi_level) { + pstat->rssi_level = level; +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8188E) { +#ifdef TXREPORT + add_RATid(priv, pstat); +#endif + } else +#endif + { +#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) + add_update_RATid(priv, pstat); +#endif + } + } +} +#endif + +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + +void check_txrate_by_reg(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + unsigned char initial_rate = 0x7f; + unsigned char legacyRA =0 ; + + if( should_restrict_Nrate(priv, pstat) && is_fixedMCSTxRate(priv, pstat)) + legacyRA = 1; + + if (pstat->sta_in_firmware == 1) + { + if (is_auto_rate(priv , pstat) || legacyRA) + { + initial_rate = RTL_R8(INIDATA_RATE_SEL + REMAP_AID(pstat)) & 0x7f; + if (initial_rate == 0x7f) + return; + + if ((initial_rate&0x3f) < 12) { + pstat->current_tx_rate = dot11_rate_table[initial_rate&0x3f]; + pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; + } else { + pstat->current_tx_rate = HT_RATE_ID + ((initial_rate&0x3f) -12); + if (initial_rate & BIT(6)) + pstat->ht_current_tx_info |= TX_USE_SHORT_GI; + else + pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; + } + + priv->pshare->current_tx_rate = pstat->current_tx_rate; + priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; + } else if (pstat->ht_cap_len) { + unsigned int is_sgi = 0; + + if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40) +#ifdef WIFI_11N_2040_COEXIST + && !((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11nConfigEntry.dot11nCoexist && + (priv->bg_ap_timeout || orForce20_Switch20Map(priv) + )) +#endif + ) { + if (priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M + && (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_))) + is_sgi++; + } else if (priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M + && (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_))) { + is_sgi++; + } + + if (is_sgi) + pstat->ht_current_tx_info |= TX_USE_SHORT_GI; + else + pstat->ht_current_tx_info &= ~TX_USE_SHORT_GI; + } + + if (pstat->ht_cap_len) { + if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40)) + pstat->ht_current_tx_info |= TX_USE_40M_MODE; + else + pstat->ht_current_tx_info &= ~TX_USE_40M_MODE; + } + + priv->pshare->ht_current_tx_info = pstat->ht_current_tx_info; + } else { + DEBUG_INFO("sta has no aid found to check current tx rate\n"); + } +} +#endif +#if 0 +void add_RATid(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + unsigned char limit=16; + int i; + unsigned long flags; + unsigned int update_reg=0; + + SAVE_INT_AND_CLI(flags); + + pstat->tx_ra_bitmap = 0; + + for (i=0; i<32; i++) { + if (pstat->bssrateset[i]) + pstat->tx_ra_bitmap |= get_bit_value_from_ieee_value(pstat->bssrateset[i]&0x7f); + } + + if (pstat->ht_cap_len) { + if ((pstat->MIMO_ps & _HT_MIMO_PS_STATIC_) || + (get_rf_mimo_mode(priv)== MIMO_1T2R) || + (get_rf_mimo_mode(priv)== MIMO_1T1R)) + limit=8; + + for (i=0; iht_cap_buf.support_mcs[i/8] & BIT(i%8)) + pstat->tx_ra_bitmap |= BIT(i+12); + } + } + + if (pstat->ht_cap_len) { + unsigned int set_sgi = 0; + if (priv->pshare->is_40m_bw && (pstat->tx_bw == HT_CHANNEL_WIDTH_20_40) +#ifdef WIFI_11N_2040_COEXIST + && !((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11nConfigEntry.dot11nCoexist && + (priv->bg_ap_timeout || orForce20_Switch20Map(priv) + )) +#endif + ) { + if (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_40M_) + && priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M) + set_sgi++; + } else if (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SHORTGI_20M_) && + priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M) { + set_sgi++; + } + + if (set_sgi) { +#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) + if (GET_CHIP_VER(priv)==VERSION_8188E) + priv->pshare->RaInfo[pstat->aid].SGIEnable = 1; + else +#endif + pstat->tx_ra_bitmap |= BIT(28); + } +#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) + else { + if (GET_CHIP_VER(priv)==VERSION_8188E) + priv->pshare->RaInfo[pstat->aid].SGIEnable = 0; + } +#endif + } +#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) + else { + if (GET_CHIP_VER(priv)==VERSION_8188E) + priv->pshare->RaInfo[pstat->aid].SGIEnable = 0; + } +#endif + + if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) { + if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) + pstat->rssi_level = 1; + else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || + ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && + (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && + (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) + pstat->rssi_level = 2; + else + pstat->rssi_level = 3; + } + + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && + ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G))) + pstat->tx_ra_bitmap &= 0xfffffff0; //disable cck rate + +#ifdef P2P_SUPPORT + if(pstat->is_p2p_client){ + pstat->tx_ra_bitmap &= 0xfffffff0; //disable cck rate + } +#endif + + // rate adaptive by rssi + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && (!should_restrict_Nrate(priv, pstat))) { + if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x100f0000; + break; + case 2: + pstat->tx_ra_bitmap &= 0x100ff000; + break; + case 3: + if (priv->pshare->is_40m_bw) + pstat->tx_ra_bitmap &= 0x100ff005; + else + pstat->tx_ra_bitmap &= 0x100ff001; + break; + } + } else { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x1f8f0000; + break; + case 2: + pstat->tx_ra_bitmap &= 0x1f8ff000; + break; + case 3: + if (priv->pshare->is_40m_bw) + pstat->tx_ra_bitmap &= 0x010ff005; + else + pstat->tx_ra_bitmap &= 0x010ff001; + break; + } + + // Don't need to mask high rates due to new rate adaptive parameters + //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta + // pstat->tx_ra_bitmap &= 0x81ffffff; + + // NIC driver will report not supporting MCS15 and MCS14 in asoc req + //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) + // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14 + } + } + else if (((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) || + ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) && + ((OPMODE & WIFI_AP_STATE) || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)))) + { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x00000f00; + break; + case 2: + pstat->tx_ra_bitmap &= 0x00000ff0; + break; + case 3: + pstat->tx_ra_bitmap &= 0x00000ff5; + break; + } + } else { + pstat->tx_ra_bitmap &= 0x0000000d; + } + +// Client mode IOT issue, Button 2009.07.17 +#ifdef CLIENT_MODE + if(OPMODE & WIFI_STATION_STATE) { + if(!pstat->is_rtl8192s_sta && pstat->is_realtek_sta && pstat->is_legacy_encrpt) + pstat->tx_ra_bitmap &= 0x0001ffff; // up to MCS4 + } +#endif +#if defined(CONFIG_RTL_92D_SUPPORT) && defined (USB_POWER_SUPPORT) + if ((GET_CHIP_VER(priv)==VERSION_8192D) && (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G)) + pstat->tx_ra_bitmap &= USB_RA_MASK; +#endif + + update_remapAid(priv, pstat); + +#if defined(CONFIG_RTL_88E_SUPPORT) && defined(TXREPORT) + if (GET_CHIP_VER(priv)==VERSION_8188E) { +#ifndef RATEADAPTIVE_BY_ODM + if (pstat->tx_ra_bitmap & 0xff000) { + if (priv->pshare->is_40m_bw) + priv->pshare->RaInfo[pstat->aid].RateID = ARFR_1T_40M; + else + priv->pshare->RaInfo[pstat->aid].RateID = ARFR_1T_20M; + } else if (pstat->tx_ra_bitmap & 0xff0) { + priv->pshare->RaInfo[pstat->aid].RateID = ARFR_BG_MIX; + } else { + priv->pshare->RaInfo[pstat->aid].RateID = ARFR_B_ONLY; + } + + priv->pshare->RaInfo[pstat->aid].RateMask = pstat->tx_ra_bitmap; + ARFBRefresh(priv, &priv->pshare->RaInfo[pstat->aid]); +#else + PODM_RA_INFO_T pRAInfo = &(ODMPTR->RAInfo[pstat->aid]); + if (pstat->tx_ra_bitmap & 0xff000) { + if (priv->pshare->is_40m_bw) + pRAInfo->RateID = ARFR_1T_40M; + else + pRAInfo->RateID = ARFR_1T_20M; + } else if (pstat->tx_ra_bitmap & 0xff0) { + pRAInfo->RateID = ARFR_BG_MIX; + } else { + pRAInfo->RateID = ARFR_B_ONLY; + } + ODM_RA_UpdateRateInfo_8188E(ODMPTR, pstat->aid, pRAInfo->RateID, pstat->tx_ra_bitmap, pRAInfo->RateSGI); +#endif + } else +#endif +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + { + + if (pstat->sta_in_firmware == 1) + { +#ifdef CONFIG_RTL_92D_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { + pstat->tx_ra_bitmap &= 0xfffffff0; + if (pstat->tx_ra_bitmap & 0xff00000) { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_40M, pstat->tx_ra_bitmap); + else + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_20M, pstat->tx_ra_bitmap); + update_reg++; + } else if (pstat->tx_ra_bitmap & 0xff000) { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_40M, pstat->tx_ra_bitmap); + else + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_Band_A_20M, pstat->tx_ra_bitmap); + } else if (pstat->tx_ra_bitmap & 0xff0) { + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_Band_A_BMC, pstat->tx_ra_bitmap); + } else { + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_Band_A_BMC, pstat->tx_ra_bitmap); + } + } else +#endif + { + if (pstat->tx_ra_bitmap & 0xff00000) { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_40M, pstat->tx_ra_bitmap); + else + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_2T_20M, pstat->tx_ra_bitmap); + update_reg++; + } else if (pstat->tx_ra_bitmap & 0xff000) { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_1T_40M, pstat->tx_ra_bitmap); + else + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_1T_20M, pstat->tx_ra_bitmap); + } else if (pstat->tx_ra_bitmap & 0xff0) { + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_BG_MIX, pstat->tx_ra_bitmap); + } else { + set_RATid_cmd(priv, REMAP_AID(pstat), ARFR_B_ONLY, pstat->tx_ra_bitmap); + } + } + + /* + * Rate adaptive algorithm. + * If the STA is 2R, we set the inti rate to MCS 15 + */ + if (update_reg) { + if (!pstat->check_init_tx_rate && (pstat->rssi > 55)) { + pstat->check_init_tx_rate = 1; + } + } + DEBUG_INFO("Add id %d val %08x to ratr\n", pstat->aid, pstat->tx_ra_bitmap); + } else { +#ifdef CONFIG_RTL_92D_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_Band_A_40M, 0x1ffffff0); + else + set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_Band_A_20M, 0x1ffffff0); + } else +#endif + { + if (priv->pshare->is_40m_bw) + set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_40M, 0x1fffffff); + else + set_RATid_cmd(priv, priv->pshare->fw_support_sta_num, ARFR_2T_20M, 0x1fffffff); + } + + } + } +#endif + + RESTORE_INT(flags); +} +#endif + +void set_rssi_cmd(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ +#ifndef SMP_SYNC + unsigned long flags; +#endif + unsigned int content = 0; + + int rssi = pstat->rssi; + +#ifdef HIGH_POWER_EXT_PA + if( priv->pshare->rf_ft_var.use_ext_pa ) + rssi += RSSI_DIFF_PA; + if( rssi > 100) + rssi = 100; +#endif + + + SAVE_INT_AND_CLI(flags); + + /* + * set rssi + */ + content = rssi<< 24; + +#ifdef CONFIG_RTL_92D_SUPPORT + /* + * set max macid + */ + if (GET_CHIP_VER(priv) == VERSION_8192D){ + content |= priv->pshare->max_fw_macid << 16; + } +#endif + + /* + * set macid + */ + content |= REMAP_AID(pstat) << 8; + + /* + * set cmd id + */ + content |= H2C_CMD_RSSI; + + signin_h2c_cmd(priv, content, 0); + + RESTORE_INT(flags); +} + +#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) +#ifdef CONFIG_PCI_HCI +void add_rssi_timer(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + struct stat_info *pstat = NULL; + unsigned int set_timer = 0; + unsigned long flags = 0; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + if (timer_pending(&priv->add_rssi_timer)) + del_timer_sync(&priv->add_rssi_timer); + +#ifdef PCIE_POWER_SAVING + if ((priv->pwr_state == L2) || (priv->pwr_state == L1)) + return; +#endif + + if (!list_empty(&priv->addrssi_list)) { + pstat = list_entry(priv->addrssi_list.next, struct stat_info, addrssi_list); + if (!pstat) + return; + + if (!is_h2c_buf_occupy(priv)) { + set_rssi_cmd(priv, pstat); + if (!list_empty(&pstat->addrssi_list)) { + SAVE_INT_AND_CLI(flags); + SMP_LOCK(flags); + list_del_init(&pstat->addrssi_list); + RESTORE_INT(flags); + SMP_UNLOCK(flags); + } + + if (!list_empty(&priv->addrssi_list)) + set_timer++; + } else { + set_timer++; + } + } + + if (set_timer) + mod_timer(&priv->add_rssi_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(50)); // 50 ms +} + + +void add_update_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ +#ifndef SMP_SYNC + unsigned long flags; +#endif + + if (is_h2c_buf_occupy(priv)) { + if (list_empty(&pstat->addrssi_list)) { + SAVE_INT_AND_CLI(flags); + list_add_tail(&(pstat->addrssi_list), &(priv->addrssi_list)); + RESTORE_INT(flags); + + if (!timer_pending(&priv->add_rssi_timer)) + mod_timer(&priv->add_rssi_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(50)); // 50 ms + } + } else { + set_rssi_cmd(priv, pstat); + } +} +#endif // CONFIG_PCI_HCI + +#ifdef CONFIG_USB_HCI +void add_update_rssi(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + notify_update_sta_rssi(priv, pstat); +} +#endif // CONFIG_USB_HCI +#endif // CONFIG_RTL_92D_SUPPORT || CONFIG_RTL_92C_SUPPORT + + +void set_RATid_cmd(struct rtl8192cd_priv *priv, unsigned int macid, unsigned int rateid, unsigned int ratemask) +{ + unsigned int content = 0; + unsigned short ext_content = 0; + +//#ifdef CONFIG_RTL_8812_SUPPORT + if(! CHIP_VER_92X_SERIES(priv)) + return; +//#endif + + /* + * set ratemask + */ + ext_content = ratemask & 0xffff; + content = ((ratemask & 0xfff0000) >> 16) << 8; + + /* + * set short GI + */ + if (ratemask & BIT(28)) + content |= BIT(29); + + /* + * set macid (station aid) + */ + content |= (macid & 0x1f) << 24; + + /* + * set rateid (ARFR table) + */ + content |= (rateid & 0xf) << 20; + + /* + * set ext_content used + */ + content |= BIT(7); + + /* + * set cmd id + */ + content |= H2C_CMD_MACID; + + signin_h2c_cmd(priv, content, ext_content); +} + + + +//3 ============================================================ +//3 EDCCA +//3 ============================================================ +#if 0 +void check_EDCCA(struct rtl8192cd_priv *priv, short rssi) +{ + if ((priv->pshare->rf_ft_var.edcca_thd) && (priv->pmib->dot11RFEntry.dot11channel==14 + || priv->pshare->is_40m_bw +#if defined(CONFIG_RTL_92D_SUPPORT) + || (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) +#endif + )) { + if((rssi > priv->pshare->rf_ft_var.edcca_thd) && (priv->pshare->phw->EDCCA_on == 0)) { + RTL_W32(rOFDM0_ECCAThreshold, 0xfc03fd); + priv->pshare->phw->EDCCA_on =1; + } else if( (rssi < priv->pshare->rf_ft_var.edcca_thd-5) && priv->pshare->phw->EDCCA_on) { + RTL_W32(rOFDM0_ECCAThreshold, 0x7f037f); + priv->pshare->phw->EDCCA_on =0; + } + } + if ((!priv->pshare->rf_ft_var.edcca_thd) && priv->pshare->phw->EDCCA_on) { + RTL_W32(0xc4c, 0x7f037f); + priv->pshare->phw->EDCCA_on = 0; + } +} +#endif + +//3 ============================================================ +//3 Antenna Diversity +//3 ============================================================ +#ifdef SW_ANT_SWITCH + +// +// 20100514 Luke/Joseph: +// Add new function to reset antenna diversity state after link. +// + +void resetSwAntDivVariable(struct rtl8192cd_priv *priv) +{ + priv->pshare->RSSI_sum_R = 0; + priv->pshare->RSSI_cnt_R = 0; + priv->pshare->RSSI_sum_L = 0; + priv->pshare->RSSI_cnt_L = 0; + priv->pshare->TXByteCnt_R = 0; + priv->pshare->TXByteCnt_L = 0; + priv->pshare->RXByteCnt_R = 0; + priv->pshare->RXByteCnt_L = 0; + +} +void SwAntDivRestAfterLink(struct rtl8192cd_priv *priv) +{ + priv->pshare->RSSI_test = FALSE; + priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_RESET; + memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); + priv->pshare->DM_SWAT_Table.mapIndex = 0; + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + resetSwAntDivVariable(priv); +} + + +void dm_SW_AntennaSwitchInit(struct rtl8192cd_priv *priv) +{ + if(!priv->pshare->rf_ft_var.antSw_enable) + return; + +// if (GET_CHIP_VER(priv) == VERSION_8188C) + if(get_rf_mimo_mode(priv)== MIMO_1T1R) + priv->pshare->rf_ft_var.antSw_select = 0; + + //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS:Init SW Antenna Switch\n")); + resetSwAntDivVariable(priv); + priv->pshare->DM_SWAT_Table.CurAntenna = Antenna_L; + priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_RESET; + memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); + priv->pshare->DM_SWAT_Table.mapIndex = 0; + +#ifdef GPIO_ANT_SWITCH +#ifdef CONFIG_RTL_92D_DMDP + if(priv->pshare->wlandev_idx==0) + priv->pshare->rf_ft_var.antHw_enable=0; + else + return; +#endif +// GPIO 45 : +// GPIO_MOD => data port +// GPIO_IO_SEL => output + RTL_W32(GPIO_PIN_CTRL, 0x00300000| RTL_R32(GPIO_PIN_CTRL)); + PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, priv->pshare->DM_SWAT_Table.CurAntenna); + RTL_W32(rFPGA0_XCD_RFParameter, RTL_R32(rFPGA0_XCD_RFParameter)| BIT(15)|BIT(16)); // enable ANTSEL + +#else + RTL_W32(LEDCFG, RTL_R32(LEDCFG) | BIT(23) ); //enable LED[1:0] pin as ANTSEL + + if ( !priv->pshare->rf_ft_var.antSw_select) { + RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) | BIT(13) ); //select ANTESEL from path A + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(8)| BIT(9) ); // enable ANTSEL A as SW control + RTL_W32(rFPGA0_XA_RFInterfaceOE, (RTL_R32(rFPGA0_XA_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna + } else { + RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) & ~ BIT(13) ); //select ANTESEL from path B + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(24)| BIT(25) ); // enable ANTSEL B as SW control + RTL_W32(rFPGA0_XB_RFInterfaceOE, (RTL_R32(rFPGA0_XB_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna + } + RTL_W16(rFPGA0_TxInfo, (RTL_R16(rFPGA0_TxInfo)&0xf0ff) | BIT(8) ); // b11-b8=0001 +#endif + + // Move the timer initialization to InitializeVariables function. + //PlatformInitializeTimer(Adapter, &pMgntInfo->SwAntennaSwitchTimer, (RT_TIMER_CALL_BACK)dm_SW_AntennaSwitchCallback, NULL, "SwAntennaSwitchTimer"); +} +// +// 20100514 Luke/Joseph: +// Add new function for antenna diversity after link. +// This is the main function of antenna diversity after link. +// This function is called in HalDmWatchDog() and dm_SW_AntennaSwitchCallback(). +// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. +// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. +// After 500ms, dm_SW_AntennaSwitchCallback() calls this function to compare the signal just +// listened on the air with the RSSI of original antenna. +// It chooses the antenna with better RSSI. +// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting +// penalty to get next try. +// +void dm_SW_AntennaSwitch(struct rtl8192cd_priv *priv, char Step) +{ + unsigned int curTxOkCnt, curRxOkCnt; + unsigned int CurByteCnt, PreByteCnt; + int Score_R=0, Score_L=0; + int RSSI_R, RSSI_L; + char nextAntenna=priv->pshare->DM_SWAT_Table.CurAntenna; + int i; + +//1 1. Determine which condition should turn off Antenna Diversity + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) + return; +#endif + +// if(!(GET_CHIP_VER(priv) == VERSION_8188C) || !priv->pshare->rf_ft_var.antSw_enable) +// return; + + if((!priv->assoc_num) +#ifdef PCIE_POWER_SAVING + || (priv->pwr_state == L2) || (priv->pwr_state == L1) +#endif + ){ + SwAntDivRestAfterLink(priv); + return; + } + + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != priv->pshare->DM_SWAT_Table.try_flag) + { + SwAntDivRestAfterLink(priv); + } + +//1 2. Initialization: Select a assocaiated AP or STA as RSSI target + if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_RESET) { +#ifdef CLIENT_MODE + if((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE)) == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) { + // Target: Infrastructure mode AP. + priv->pshare->RSSI_target = NULL; + } +#endif + resetSwAntDivVariable(priv); + priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_PEAK; + return; + } + else { + +//1 3. Antenna Diversity + + //2 Calculate TX and RX OK bytes + + curTxOkCnt = priv->net_stats.tx_bytes - priv->pshare->lastTxOkCnt; + curRxOkCnt = priv->net_stats.rx_bytes - priv->pshare->lastRxOkCnt; + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + + //2 Try State + if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_DETERMINE) { + //3 1. Seperately caculate TX and RX OK byte counter for ant A and B + if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { + priv->pshare->TXByteCnt_R += curTxOkCnt; + priv->pshare->RXByteCnt_R += curRxOkCnt; + } else { + priv->pshare->TXByteCnt_L += curTxOkCnt; + priv->pshare->RXByteCnt_L += curRxOkCnt; + } + + //3 2. Change anntena for testing + if(priv->pshare->DM_SWAT_Table.RSSI_Trying != 0) { + nextAntenna = (priv->pshare->DM_SWAT_Table.CurAntenna ) ^ Antenna_MAX; + priv->pshare->DM_SWAT_Table.RSSI_Trying--; + } + + //2 Try State End: Determine the best antenna + + if(priv->pshare->DM_SWAT_Table.RSSI_Trying==0) { + nextAntenna = priv->pshare->DM_SWAT_Table.CurAntenna; + priv->pshare->DM_SWAT_Table.mapIndex = (priv->pshare->DM_SWAT_Table.mapIndex+1)%SELANT_MAP_SIZE; + + //3 TP Mode: Determine the best antenna by throuhgput + if(priv->pshare->DM_SWAT_Table.TestMode == TP_MODE) { + + + + //3 (1) Saperately caculate total byte count for two antennas + if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { + CurByteCnt = (priv->pshare->TXByteCnt_R + (priv->pshare->RXByteCnt_R<<1)); + PreByteCnt = (priv->pshare->TXByteCnt_L + (priv->pshare->RXByteCnt_L<<1)); + } else { + CurByteCnt = (priv->pshare->TXByteCnt_L + (priv->pshare->RXByteCnt_L<<1)); + PreByteCnt = (priv->pshare->TXByteCnt_R + (priv->pshare->RXByteCnt_R<<1)); + } + + //3 (2) Throughput Normalization + if(priv->pshare->TrafficLoad == TRAFFIC_HIGH) + CurByteCnt >>=3; + else if(priv->pshare->TrafficLoad == TRAFFIC_LOW) + CurByteCnt >>=1; + + if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) { + priv->pshare->DM_SWAT_Table.SelectAntennaMap[0][priv->pshare->DM_SWAT_Table.mapIndex] = PreByteCnt; + priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][priv->pshare->DM_SWAT_Table.mapIndex] = CurByteCnt; + } else { + priv->pshare->DM_SWAT_Table.SelectAntennaMap[0][priv->pshare->DM_SWAT_Table.mapIndex] = CurByteCnt; + priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][priv->pshare->DM_SWAT_Table.mapIndex] = PreByteCnt; + } + + Score_R = Score_L=0; + for (i= 0; ipshare->DM_SWAT_Table.SelectAntennaMap[0][i]; + Score_R += priv->pshare->DM_SWAT_Table.SelectAntennaMap[1][i]; + } + + nextAntenna = (Score_L > Score_R) ? Antenna_L : Antenna_R; + + if(priv->pshare->rf_ft_var.ant_dump&8) + panic_printk("Mode TP, select Ant%d, [Score1=%d,Score2=%d]\n", nextAntenna, Score_L, Score_R); + + } + + //3 RSSI Mode: Determine the best anntena by RSSI + else if(priv->pshare->DM_SWAT_Table.TestMode == RSSI_MODE) { + + //2 Saperately caculate average RSSI for two antennas + RSSI_L = RSSI_R = 0; + + if(priv->pshare->RSSI_cnt_R > 0) + RSSI_R = priv->pshare->RSSI_sum_R/priv->pshare->RSSI_cnt_R; + if(priv->pshare->RSSI_cnt_L > 0) + RSSI_L = priv->pshare->RSSI_sum_L/priv->pshare->RSSI_cnt_L; + + if(RSSI_L && RSSI_R ) + nextAntenna = (RSSI_L > RSSI_R) ? Antenna_L : Antenna_R; + + if(priv->pshare->rf_ft_var.ant_dump&8) + panic_printk("Mode RSSI, RSSI_R=%d(%d), RSSI_L=%d(%d), Ant=%d\n", + RSSI_R, priv->pshare->RSSI_cnt_R, RSSI_L, priv->pshare->RSSI_cnt_L, nextAntenna); + + } + + //3 Reset state + resetSwAntDivVariable(priv); + priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_PEAK; + priv->pshare->RSSI_test = FALSE; + } + } + + //1 Normal State + else if(priv->pshare->DM_SWAT_Table.try_flag == SWAW_STEP_PEAK) { + + //3 Determine TP/RSSI mode by TRX OK count + if((curRxOkCnt+curTxOkCnt) > TP_MODE_THD) { + //2 Determine current traffic is high or low + if((curTxOkCnt+curRxOkCnt) > TRAFFIC_THRESHOLD) + priv->pshare->TrafficLoad = TRAFFIC_HIGH; + else + priv->pshare->TrafficLoad = TRAFFIC_LOW; + + priv->pshare->DM_SWAT_Table.RSSI_Trying = 10; + priv->pshare->DM_SWAT_Table.TestMode = TP_MODE; + } else { + + int idx = 0; + struct stat_info* pEntry = findNextSTA(priv, &idx); + priv->pshare->RSSI_target = NULL; + while(pEntry) { + if(pEntry && pEntry->expire_to) { + if(!priv->pshare->RSSI_target) + priv->pshare->RSSI_target = pEntry; + else if( pEntry->rssi < priv->pshare->RSSI_target->rssi ) + priv->pshare->RSSI_target = pEntry; + } + pEntry = findNextSTA(priv, &idx); + }; + + priv->pshare->DM_SWAT_Table.RSSI_Trying = 6; + priv->pshare->DM_SWAT_Table.TestMode = RSSI_MODE; + + if(priv->pshare->RSSI_target == NULL) { + SwAntDivRestAfterLink(priv); + return; + } + + //3 reset state + memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); + } + + //3 Begin to enter Try State + nextAntenna = (priv->pshare->DM_SWAT_Table.CurAntenna ) ^ Antenna_MAX; + priv->pshare->DM_SWAT_Table.try_flag = SWAW_STEP_DETERMINE; + priv->pshare->RSSI_test = TRUE; + + //3 Reset variables + resetSwAntDivVariable(priv); + } + } + +//1 4.Change TRX antenna + if(nextAntenna != priv->pshare->DM_SWAT_Table.CurAntenna) { +#if defined(CONFIG_PCI_HCI) +#ifdef GPIO_ANT_SWITCH + PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, nextAntenna); +#else + if (!priv->pshare->rf_ft_var.antSw_select) + PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); + else + PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, nextAntenna); +#endif + +//1 5.Reset Statistics + priv->pshare->DM_SWAT_Table.CurAntenna = nextAntenna; +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + notify_antenna_switch(priv, nextAntenna); +#endif + } + +//1 6.Set next timer + + if(priv->pshare->DM_SWAT_Table.RSSI_Trying == 0) { + return; + } + + if(priv->pshare->DM_SWAT_Table.TestMode == RSSI_MODE) { + mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(400)); // 400 ms + } else if(priv->pshare->DM_SWAT_Table.TestMode == TP_MODE) { + + if(priv->pshare->TrafficLoad == TRAFFIC_HIGH) { + if(priv->pshare->DM_SWAT_Table.RSSI_Trying%2 == 0) + mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(10)); // 10 ms + else + mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(80)); // 80 ms + + } else if(priv->pshare->TrafficLoad == TRAFFIC_LOW) { + if(priv->pshare->DM_SWAT_Table.RSSI_Trying%2 == 0) + mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(40)); // 40 ms + else + mod_timer(&priv->pshare->swAntennaSwitchTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(80)); // 80 ms + } + } + +} + + +void dm_SW_AntennaSwitchCallback(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv*)task_priv; +#ifndef SMP_SYNC + unsigned long flags = 0; +#endif + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + SAVE_INT_AND_CLI(flags); + dm_SW_AntennaSwitch(priv, SWAW_STEP_DETERMINE); + RESTORE_INT(flags); +} + +// +// 20100514 Luke/Joseph: +// This function is used to gather the RSSI information for antenna testing. +// It selects the RSSI of the peer STA that we want to know. +// +void dm_SWAW_RSSI_Check(struct rtl8192cd_priv *priv, struct rx_frinfo *pfrinfo) +{ + struct stat_info* pEntry = NULL; + pEntry = get_stainfo(priv, GetAddr2Ptr(get_pframe(pfrinfo))); + + if((priv->pshare->RSSI_target==NULL)||(priv->pshare->RSSI_target==pEntry)) { + //1 RSSI for SW Antenna Switch + if(priv->pshare->DM_SWAT_Table.CurAntenna == Antenna_R) + { + priv->pshare->RSSI_sum_R += pfrinfo->rssi; + priv->pshare->RSSI_cnt_R++; + } else { + priv->pshare->RSSI_sum_L += pfrinfo->rssi; + priv->pshare->RSSI_cnt_L++; + } + } +} + +#ifndef HW_ANT_SWITCH + +int diversity_antenna_select(struct rtl8192cd_priv *priv, unsigned char *data) +{ + int ant = _atoi(data, 16); +// if(GET_CHIP_VER(priv) != VERSION_8188C) +// return 0; + +#ifdef PCIE_POWER_SAVING + PCIeWakeUp(priv, POWER_DOWN_T0); +#endif + if(ant==Antenna_L || ant==Antenna_R) { +#ifdef GPIO_ANT_SWITCH + PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, ant); +#else + if (!priv->pshare->rf_ft_var.antSw_select) + PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, ant); + else + PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, ant); +#endif + priv->pshare->DM_SWAT_Table.CurAntenna = ant; + priv->pshare->rf_ft_var.antSw_enable = 0; + SwAntDivRestAfterLink(priv); + memset(priv->pshare->DM_SWAT_Table.SelectAntennaMap, 0, sizeof(priv->pshare->DM_SWAT_Table.SelectAntennaMap)); + return 1; + } else { + priv->pshare->rf_ft_var.antSw_enable = 1; + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + + return 0; + } +} +#endif +#endif +#if defined(HW_ANT_SWITCH) + +void dm_HW_AntennaSwitchInit(struct rtl8192cd_priv *priv) +{ + if(!priv->pshare->rf_ft_var.antHw_enable) + return; +#ifdef SW_ANT_SWITCH + priv->pshare->rf_ft_var.antSw_enable =0; +#endif + +// if (GET_CHIP_VER(priv) == VERSION_8188C) + if(get_rf_mimo_mode(priv)== MIMO_1T1R) + priv->pshare->rf_ft_var.antSw_select = 0; + + if ( !priv->pshare->rf_ft_var.antSw_select) { + RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) | BIT(13) ); //select ANTESEL from path A + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(8)| BIT(9)) ); // ANTSEL as HW control + RTL_W32(rFPGA0_XA_RFInterfaceOE, (RTL_R32(rFPGA0_XA_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna + RTL_W8(0xc50, RTL_R8(0xc50) | BIT(7)); // Enable Hardware antenna switch + RTL_W32(0xc54, RTL_R32(0xc54) | BIT(23) ); // Decide final antenna by comparing 2 antennas' pwdb + } else { + RTL_W32(rFPGA0_XAB_RFParameter, RTL_R32(rFPGA0_XAB_RFParameter) & ~ BIT(13) ); //select ANTESEL from path B + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(24)| BIT(25)) ); // ANTSEL as HW control + RTL_W32(rFPGA0_XB_RFInterfaceOE, (RTL_R32(rFPGA0_XB_RFInterfaceOE) & ~(BIT(8)|BIT(9)))| 0x01<<8 ); // 0x01: left antenna, 0x02: right antenna +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, RTL_R8(0xc58) | BIT(7)); // Enable Hardware antenna switch +#endif + RTL_W32(0xc5C, RTL_R32(0xc5c) | BIT(23) ); // Decide final antenna by comparing 2 antennas' pwdb + } + + priv->pshare->rf_ft_var.CurAntenna = 0; + + RTL_W32(LEDCFG, RTL_R32(LEDCFG) | BIT(23) ); //enable LED[1:0] pin as ANTSEL + RTL_W16(0xca4, (RTL_R16(0xca4) & ~(0xfff))|0x0c0); // Pwdb threshold=12dB + RTL_W32(0x874, RTL_R32(0x874) & ~ BIT(23) ); // No update ANTSEL during GNT_BT=1 + RTL_W16(rFPGA0_TxInfo, (RTL_R16(rFPGA0_TxInfo)&0xf0ff) | BIT(8) ); // b11-b8=0001 + RTL_W32(0x80c, RTL_R32(0x80c) | BIT(21) ); // assign antenna by tx desc + + // CCK setting + RTL_W8(0xa01, RTL_R8(0xa01) | BIT(7)); // enable hw ant diversity + RTL_W8(0xa0c, (RTL_R8(0xa0c) & 0xe0) | 0x0f ); // b4=0, b3:0 = 1111 32 sample + RTL_W8(0xa11, RTL_R8(0xa11) | BIT(5)); // do not change default optional antenna + RTL_W8(0xa14, (RTL_R8(0xa14) & 0xe0) | 0x08 ); // default : optional = 1:1 +#ifdef GPIO_ANT_SWITCH + PHY_SetBBReg(priv, rFPGA0_XCD_RFParameter, 0x40000000, 0x01); // enable ANTSEL +#endif + +} + +void setRxIdleAnt(struct rtl8192cd_priv *priv, char Ant) +{ + if(priv->pshare->rf_ft_var.CurAntenna != Ant) { + if(Ant) { + RTL_W32(0x858, 0x65a965a9); +// RTL_W8(0x6d8, RTL_R8(0x6d8) | BIT(6) ); + } + else { + RTL_W32(0x858, 0x569a569a); +// RTL_W8(0x6d8, RTL_R8(0x6d8) & (~ BIT(6))); + } + priv->pshare->rf_ft_var.CurAntenna = Ant; + } +} + +void dm_STA_Ant_Select(struct rtl8192cd_priv *priv, struct stat_info *pstat) +{ + int ScoreA=0, ScoreB=0, i, nextAnt= pstat->CurAntenna, idleAnt=priv->pshare->rf_ft_var.CurAntenna; + + if((priv->pshare->rf_ft_var.CurAntenna & 0x80) + || ((pstat->hwRxAntSel[0] + pstat->hwRxAntSel[1])==0 && (pstat->cckPktCount[0] + pstat->cckPktCount[1])<10) ) + return; + + for(i=0; i<2; i++) { + if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0) + pstat->AntRSSI[i] = 0; + } + + if(pstat->hwRxAntSel[0] || pstat->hwRxAntSel[1]) { + ScoreA = pstat->hwRxAntSel[0]; + ScoreB = pstat->hwRxAntSel[1]; + + if(ScoreA != ScoreB) { + if(ScoreA > ScoreB) + nextAnt = 0; + else + nextAnt = 1; + } + } else { + ScoreA = pstat->cckPktCount[0]; + ScoreB = pstat->cckPktCount[1]; + + if(ScoreA > 5*ScoreB) + nextAnt = 0; + else if(ScoreB > 5*ScoreA) + nextAnt = 1; + else if(ScoreA > ScoreB) + nextAnt = 1; + else if(ScoreB > ScoreA) + nextAnt = 0; + } + + pstat->CurAntenna = nextAnt; + + if(priv->pshare->rf_ft_var.ant_dump&2) { + panic_printk("id=%d, OFDM/CCK: (%d, %d/%d, %d), RSSI:(%d, %d), ant=%d, RxIdle=%d\n", + pstat->aid, + pstat->hwRxAntSel[1], + pstat->hwRxAntSel[0], + pstat->cckPktCount[1], + pstat->cckPktCount[0], + pstat->AntRSSI[1], + pstat->AntRSSI[0], + (pstat->CurAntenna==0 ? 2: 1) + ,((priv->pshare->rf_ft_var.CurAntenna&1)==0 ? 2 : 1) + ); + } + + if(pstat->AntRSSI[idleAnt]==0) + pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1]; + +// reset variables + pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0; + pstat->cckPktCount[1]= pstat->cckPktCount[0] =0; + +} + +void dm_HW_IdleAntennaSelect(struct rtl8192cd_priv *priv) +{ + struct stat_info *pstat, *pstat_min=NULL; + struct list_head *phead, *plist; + int rssi_min= 0xff, i; +#ifdef SMP_SYNC + unsigned long flags = 0; +#endif + + if(priv->pshare->rf_ft_var.CurAntenna & 0x80) + return; + + phead = &priv->asoc_list; + + SMP_LOCK_ASOC_LIST(flags); + + plist = phead->next; + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + + if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) { + int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1]; + if((!pstat_min) || ( rssi < rssi_min) ) { + pstat_min = pstat; + rssi_min = rssi; + } + } + }; + + SMP_UNLOCK_ASOC_LIST(flags); + + if(pstat_min) + setRxIdleAnt(priv, pstat_min->CurAntenna); + + +#ifdef TX_SHORTCUT + if (!priv->pmib->dot11OperationEntry.disable_txsc) { + SMP_LOCK_ASOC_LIST(flags); + + plist = phead->next; + while(plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + + if(pstat->expire_to) { + for (i=0; itx_sc_ent[i].hwdesc1); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + #ifdef CONFIG_PCI_HCI + pdesc= &(pstat->tx_sc_ent[i].hwdesc2); + pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25))); + if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1) + pdesc->Dword2 |= set_desc(BIT(24)|BIT(25)); + #endif + } + } + }; + + SMP_UNLOCK_ASOC_LIST(flags); + } +#endif + +} + +int diversity_antenna_select(struct rtl8192cd_priv *priv, unsigned char *data) +{ + int ant = _atoi(data, 16); + +#ifdef PCIE_POWER_SAVING + PCIeWakeUp(priv, POWER_DOWN_T0); +#endif + + if (ant==Antenna_L || ant==Antenna_R) { + +#ifdef GPIO_ANT_SWITCH + if(priv->pshare->rf_ft_var.antSw_enable) { + PHY_SetBBReg(priv, GPIO_PIN_CTRL, 0x3000, ant); + } else +#endif + { + if ( !priv->pshare->rf_ft_var.antSw_select) { + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(8)| BIT(9) ); // ANTSEL A as SW control + RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control + PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, 0x300, ant); + } else { + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) | BIT(24)| BIT(25) ); // ANTSEL B as HW control + PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, 0x300, ant); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, RTL_R8(0xc58) & (~ BIT(7))); // rx OFDM SW control +#endif + } + RTL_W8(0xa01, RTL_R8(0xa01) & (~ BIT(7))); // rx CCK SW control + RTL_W32(0x80c, RTL_R32(0x80c) & (~ BIT(21))); // select ant by tx desc + RTL_W32(0x858, 0x569a569a); + } + if(HW_DIV_ENABLE) + priv->pshare->rf_ft_var.antHw_enable = BIT(5); + priv->pshare->rf_ft_var.CurAntenna = (ant%2); +#ifdef SW_ANT_SWITCH + if(priv->pshare->rf_ft_var.antSw_enable) + priv->pshare->rf_ft_var.antSw_enable = BIT(5); + priv->pshare->DM_SWAT_Table.CurAntenna = ant; + priv->pshare->RSSI_test =0; +#endif + } + else if(ant==0){ +#ifdef GPIO_ANT_SWITCH + if(priv->pshare->rf_ft_var.antHw_enable) +#endif + { + if (!priv->pshare->rf_ft_var.antSw_select) { + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(8)| BIT(9)) ); + RTL_W8(0xc50, RTL_R8(0xc50) | BIT(7)); // OFDM HW control + } else { + RTL_W32(rFPGA0_XAB_RFInterfaceSW, RTL_R32(rFPGA0_XAB_RFInterfaceSW) & ~(BIT(24)| BIT(25)) ); +#if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) + if ( +#ifdef CONFIG_RTL_92C_SUPPORT + (GET_CHIP_VER(priv)==VERSION_8192C) || (GET_CHIP_VER(priv)==VERSION_8188C) +#endif +#ifdef CONFIG_RTL_92D_SUPPORT +#ifdef CONFIG_RTL_92C_SUPPORT + || +#endif + (GET_CHIP_VER(priv)==VERSION_8192D) +#endif + ) + RTL_W8(0xc58, RTL_R8(0xc58) | BIT(7)); // OFDM HW control +#endif + } + RTL_W8(0xa01, RTL_R8(0xa01) | BIT(7)); // CCK HW control + RTL_W32(0x80c, RTL_R32(0x80c) | BIT(21) ); // by tx desc + priv->pshare->rf_ft_var.CurAntenna = 0; + RTL_W32(0x858, 0x569a569a); + priv->pshare->rf_ft_var.antHw_enable = 1; +#ifdef SW_ANT_SWITCH + priv->pshare->rf_ft_var.antSw_enable = 0; + priv->pshare->RSSI_test =0; +#endif + } +#ifdef SW_ANT_SWITCH + if(priv->pshare->rf_ft_var.antSw_enable) { + dm_SW_AntennaSwitchInit(priv); + RTL_W32(0x858, 0x569a569a); + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + priv->pshare->rf_ft_var.antHw_enable = 0; + priv->pshare->rf_ft_var.antSw_enable = 1; + } +#endif + + } +#if defined(SW_ANT_SWITCH) && !defined(GPIO_ANT_SWITCH) + else if(ant==3) { + if(!priv->pshare->rf_ft_var.antSw_enable) { + dm_SW_AntennaSwitchInit(priv); + RTL_W32(0x858, 0x569a569a); + priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes; + priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes; + } +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv)==VERSION_8188E) { + RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control + } else +#endif + { + if ( !priv->pshare->rf_ft_var.antSw_select) + RTL_W8(0xc50, RTL_R8(0xc50) & (~ BIT(7))); // rx OFDM SW control + else + RTL_W8(0xc58, RTL_R8(0xc58) & (~ BIT(7))); // rx OFDM SW control + } + + RTL_W8(0xa01, RTL_R8(0xa01) & (~ BIT(7))); // rx CCK SW control + RTL_W32(0x80c, RTL_R32(0x80c) & (~ BIT(21))); // select ant by tx desc + priv->pshare->rf_ft_var.antHw_enable = 0; + priv->pshare->rf_ft_var.antSw_enable = 1; + + } +#endif + + return 1; +} + +#endif + +//3 ============================================================ +//3 Dynamic Noise Control +//3 ============================================================ + +#if defined(CONFIG_RTL_92D_SUPPORT) && defined(CONFIG_RTL_NOISE_CONTROL) +void dnc_timer(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + struct stat_info *pstat = NULL; + unsigned int set_timer = 0; + unsigned long flags; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + if (timer_pending(&priv->dnc_timer)) + del_timer_sync(&priv->dnc_timer); + +#ifdef PCIE_POWER_SAVING + if ((priv->pwr_state == L2) || (priv->pwr_state == L1)) + return; +#endif + + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + //PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07600760); + PHY_SetBBReg(priv, 0xc50, bMaskByte0, 0x20); + PHY_SetBBReg(priv, 0xc58, bMaskByte0, 0x20); + } +} +#endif + + +//3 ============================================================ +//3 Leaving STA check +//3 ============================================================ +#if 0 +//#if defined(DETECT_STA_EXISTANCE) //&& (defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT)) +// Check for STA existance. If STA disappears, disconnect it. Added by Annie, 2010-08-10. +void DetectSTAExistance(struct rtl8192cd_priv *priv, struct tx_rpt *report, struct stat_info *pstat) +{ + unsigned char tmpbuf[16]; + + // Parameters + const unsigned int maxTxFailCnt = 300; // MAX Tx fail packet count + const unsigned int minTxFailCnt = 30; // MIN Tx fail packet count; this value should be less than maxTxFailCnt. + const unsigned int txFailSecThr= 3; // threshold of Tx Fail Time (in second) + + // Temporarily change Retry Limit when TxFail. (tfrl: TxFailRetryLimit) + const unsigned char TFRL = 7; // New Retry Limit value + const unsigned char TFRL_FailCnt = 2; // Tx Fail Count threshold to set Retry Limit + const unsigned char TFRL_SetTime = 2; // Time to set Retry Limit (in second) + const unsigned char TFRL_RcvTime = 10; // Time to recover Retry Limit (in second) + + if(OPMODE & WIFI_STATION_STATE) + return; + + if( report->txok != 0 ) + { // Reset Counter + pstat->tx_conti_fail_cnt = 0; + pstat->tx_last_good_time = priv->up_time; + pstat->leave = 0; + } + else if( report->txfail != 0 ) + { + pstat->tx_conti_fail_cnt += report->txfail; + DEBUG_WARN( "detect: txfail=%d, tx_conti_fail_cnt=%d\n", report->txfail, pstat->tx_conti_fail_cnt ); + + if( CHIP_VER_92X_SERIES(priv) && (priv->up_time >= (pstat->tx_last_good_time+TFRL_SetTime)) && + pstat->tx_conti_fail_cnt >= TFRL_FailCnt && + #if defined(CONFIG_RTL8672) || defined (NOT_RTK_BSP) + !pstat->ht_cap_len && // legacy rate only + #endif + !priv->pshare->bRLShortened ) + { // Shorten retry limit, because AP spending too much time to send out g mode STA pending packets in HW queue. + RTL_W16(RL, (TFRL&SRL_Mask)<pshare->bRLShortened = TRUE; + DEBUG_WARN( "== Shorten RetryLimit to 0x%04X ==\n", RTL_R16(RL) ); + } + + if( (pstat->tx_conti_fail_cnt >= maxTxFailCnt) || + (pstat->tx_conti_fail_cnt >= minTxFailCnt && priv->up_time >= (pstat->tx_last_good_time+txFailSecThr) ) + ) + { // This STA is considered as disappeared, so delete it. + DEBUG_WARN( "** tx_conti_fail_cnt=%d (min=%d,max=%d)\n", pstat->tx_conti_fail_cnt, minTxFailCnt, maxTxFailCnt); + DEBUG_WARN( "** tx_last_good_time=%d, up_time=%d (Thr:%d)\n", (int)pstat->tx_last_good_time, (int)priv->up_time, txFailSecThr ); + DEBUG_WARN( "AP is going to del_sta %02X:%02X:%02X:%02X:%02X:%02X\n", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5] ); + + sprintf((char *)tmpbuf, "%02x%02x%02x%02x%02x%02x", pstat->hwaddr[0],pstat->hwaddr[1],pstat->hwaddr[2],pstat->hwaddr[3],pstat->hwaddr[4],pstat->hwaddr[5]); + +// del_sta(priv, tmpbuf); + ++(pstat->leave); + + if(CHIP_VER_92X_SERIES(priv) { + if (timer_pending(&priv->pshare->rl_recover_timer)) + del_timer_sync (&priv->pshare->rl_recover_timer); + mod_timer(&priv->pshare->rl_recover_timer, jiffies + EXPIRE_TO*TFRL_RcvTime); + } + + // Reset Counter + pstat->tx_conti_fail_cnt = 0; + pstat->tx_last_good_time = priv->up_time; + } + } +} + +// Timer callback function to recover hardware retry limit register. Added by Annie, 2010-08-10. +#if defined(__KERNEL__) || defined(__OSK__) +void RetryLimitRecovery(unsigned long task_priv) +#elif defined(__ECOS) +void RetryLimitRecovery(void *task_priv) +#endif +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + if( priv->pshare->bRLShortened ) + { + RTL_W16(RL, priv->pshare->RL_setting); + priv->pshare->bRLShortened = FALSE; + DEBUG_WARN( "== Recover RetryLimit to 0x%04X ==\n", RTL_R16(RL) ); + } +} + +// Chack STA leaving status; per interface. Added by Annie, 2010-08-10. +unsigned char NoLeavingSTA(struct rtl8192cd_priv *priv) +{ + unsigned char bStaAllOK = TRUE; + struct list_head *phead, *plist; + struct stat_info *pstat; + + phead = &priv->asoc_list; + if (!netif_running(priv->dev) || list_empty(phead)) + return bStaAllOK; + + plist = phead->next; + while (plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + if( pstat->tx_conti_fail_cnt != 0 ) { + bStaAllOK = FALSE; + break; + } + plist = plist->next; + } + + return bStaAllOK; +} + +// Chack STA leaving status for all active interface and recover retry limit register value. Added by Annie, 2010-08-10. +void LeavingSTA_RLCheck(struct rtl8192cd_priv *priv) +{ + unsigned char bIfAllOK = TRUE; + static int AllOKTimes = 0; +#ifdef MBSSID + int i; +#endif + // Parameter + const unsigned char TFRL_RcvTime = 10; // Time to recover Retry Limit (in second) + + if( !NoLeavingSTA(priv) ) + bIfAllOK = FALSE; + +#ifdef UNIVERSAL_REPEATER + if (IS_ROOT_INTERFACE(priv) && GET_VXD_PRIV(priv) ) { + if( !NoLeavingSTA(GET_VXD_PRIV(priv)) ) + bIfAllOK = FALSE; + } +#endif + +#ifdef MBSSID + if (IS_ROOT_INTERFACE(priv)) { + if (GET_ROOT(priv)->pmib->miscEntry.vap_enable) { + for (i=0; ipvap_priv[i])) { + if( !NoLeavingSTA(priv->pvap_priv[i]) ) + bIfAllOK = FALSE; + } + } + } + } +#endif + + if( bIfAllOK ) { + AllOKTimes ++; + + if( AllOKTimes >= TFRL_RcvTime ) +#if defined(__KERNEL__) || defined(__OSK__) + RetryLimitRecovery((unsigned long)priv); +#elif defined(__ECOS) + RetryLimitRecovery((void *)priv); +#endif + } + else { + AllOKTimes = 0; + } +} +#endif + + + +#ifdef CONFIG_RTL_92C_SUPPORT + +/* + * PA Analog Pre-distortion Calibration R06 + */ +void APK_MAIN(struct rtl8192cd_priv *priv, unsigned int is2T) +{ + unsigned int regD[PATH_NUM]; + unsigned int tmpReg, index, offset, path, i=0, pathbound = PATH_NUM, apkbound=6; + unsigned int BB_backup[APK_BB_REG_NUM]; + unsigned int BB_REG[APK_BB_REG_NUM] = {0x904, 0xc04, 0x800, 0xc08, 0x874}; + unsigned int BB_AP_MODE[APK_BB_REG_NUM] = {0x00000020, 0x00a05430, 0x02040000, 0x000800e4, 0x00204000}; + unsigned int BB_normal_AP_MODE[APK_BB_REG_NUM] = {0x00000020, 0x00a05430, 0x02040000, 0x000800e4, 0x22204000}; + unsigned int AFE_backup[APK_AFE_REG_NUM]; + unsigned int AFE_REG[APK_AFE_REG_NUM] = { 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; + unsigned int MAC_backup[IQK_MAC_REG_NUM]; + unsigned int MAC_REG[IQK_MAC_REG_NUM] = {0x522, 0x550, 0x551, 0x040}; + unsigned int APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}}; + unsigned int APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = + { {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} }; + + unsigned int APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = + { {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}}; + + unsigned int APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = + { {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} }; + + unsigned int AFE_on_off[PATH_NUM] = {0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + unsigned int APK_offset[PATH_NUM] = {0xb68, 0xb6c}; + unsigned int APK_normal_offset[PATH_NUM] = {0xb28, 0xb98}; + unsigned int APK_value[PATH_NUM] = {0x92fc0000, 0x12fc0000}; + unsigned int APK_normal_value[PATH_NUM] = {0x92680000, 0x12680000}; + char APK_delta_mapping[APK_BB_REG_NUM][13] = {{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}}; + unsigned int APK_normal_setting_value_1[13] = + { 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 }; + unsigned int APK_normal_setting_value_2[16] = + { 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 }; + + + unsigned int APK_normal_RF_init_value_old[PATH_NUM][APK_BB_REG_NUM] = + {{0x0852c, 0x5a52c, 0x0a52c, 0x5a52c, 0x4a52c}, //path settings equal to path b settings + {0x0852c, 0x5a52c, 0x0a52c, 0x5a52c, 0x4a52c}}; + unsigned int APK_normal_RF_value_0_old[PATH_NUM][APK_BB_REG_NUM] = + {{0x52019, 0x52017, 0x52010, 0x5200d, 0x5200a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5200a}}; + unsigned int APK_normal_setting_value_1_old[13] = + {0x01017018, 0xf7ed8f84, 0x40372d20, 0x5b554e48, 0x6f6a6560, + 0x807c7873, 0x8f8b8884, 0x9d999693, 0xa9a6a3a0, 0xb5b2afac, + 0x12680000, 0x00880000, 0x00880000}; + unsigned int APK_normal_setting_value_2_old[16] = + {0x00810100, 0x00400056, 0x002b0032, 0x001f0024, 0x0019001c, + 0x00150017, 0x00120013, 0x00100011, 0x000e000f, 0x000c000d, + 0x000b000c, 0x000a000b, 0x0009000a, 0x00090009, 0x00080008, + 0x00080008}; + unsigned int AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + unsigned int APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a + unsigned int ThermalValue = 0; + int BB_offset, delta_V, delta_offset; + int newVerAPK = (IS_UMC_A_CUT_88C(priv)) ? 1 : 0; + unsigned int *pAPK_normal_setting_value_1 = APK_normal_setting_value_1, *pAPK_normal_setting_value_2 = APK_normal_setting_value_2 ; +#ifdef HIGH_POWER_EXT_PA + unsigned int tmp0x870=0, tmp0x860=0, tmp0x864=0; + + if(priv->pshare->rf_ft_var.use_ext_pa) + newVerAPK = 1; +#endif + + if(!newVerAPK) { + apkbound = 12; + pAPK_normal_setting_value_1 = APK_normal_setting_value_1_old; + pAPK_normal_setting_value_2 = APK_normal_setting_value_2_old; + } + + if(!is2T) + pathbound = 1; + + for(index = 0; index < PATH_NUM; index ++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) { + for(path = 0; path < pathbound; path++) { + if(newVerAPK) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } else { + APK_RF_init_value[path][index] = APK_normal_RF_init_value_old[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0_old[path][index]; + } + + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + /* + * save BB default value + */ + for(index = 1; index < APK_BB_REG_NUM ; index++) + BB_backup[index] = PHY_QueryBBReg(priv, BB_REG[index], bMaskDWord); + +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) { + tmp0x870 = PHY_QueryBBReg(priv, 0x870, bMaskDWord); + tmp0x860 = PHY_QueryBBReg(priv, 0x860, bMaskDWord); + tmp0x864 = PHY_QueryBBReg(priv, 0x864, bMaskDWord); + } +#endif + + //save MAC default value + _PHY_SaveMACRegisters(priv, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(priv, AFE_REG, AFE_backup, APK_AFE_REG_NUM); + + for(path = 0; path < pathbound; path++) { + /* + * save old AP curve + */ + if(path == RF92CD_PATH_A) { + /* + * path A APK + * load APK setting + * path-A + */ + offset = 0xb00; + for(index = 0; index < 11; index ++) { + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); + offset += 0x04; + } + PHY_SetBBReg(priv, 0xb98, bMaskDWord, 0x12680000); + + offset = 0xb68; + for(; index < 13; index ++) { + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); + offset += 0x04; + } + + /* + * page-B1 + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); + + /* + *path A + */ + offset = 0xb00; + for(index = 0; index < 16; index++) { + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_2[index]); + offset += 0x04; + } + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + } else if(path == RF92CD_PATH_B) { + /* + * path B APK + * load APK setting + * path-B + */ + offset = 0xb70; + for(index = 0; index < 10; index ++) { + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); + offset += 0x04; + } + PHY_SetBBReg(priv, 0xb28, bMaskDWord, 0x12680000); + PHY_SetBBReg(priv, 0xb98, bMaskDWord, 0x12680000); + + offset = 0xb68; + index = 11; + for(; index < 13; index ++) { + //offset 0xb68, 0xb6c + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_1[index]); + offset += 0x04; + } + + /* + * page-B1 + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); + + /* + * path B + */ + offset = 0xb60; + for(index = 0; index < 16; index++) { + PHY_SetBBReg(priv, offset, bMaskDWord, pAPK_normal_setting_value_2[index]); + offset += 0x04; + } + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + } + + if(!newVerAPK) { + tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x3, bMaskDWord, 1); + + AP_curve[path][0] = tmpReg & 0x1F; //[4:0] + + tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, 1); + AP_curve[path][1] = (tmpReg & 0xF8000) >> 15; //[19:15] + AP_curve[path][2] = (tmpReg & 0x7C00) >> 10; //[14:10] + AP_curve[path][3] = (tmpReg & 0x3E0) >> 5; //[9:5] + } + + /* + * save RF default value + */ + regD[path] = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, 1); + + /* + * Path A AFE all on, path B AFE All off or vise versa + */ + for(index = 0; index < APK_AFE_REG_NUM ; index++) + PHY_SetBBReg(priv, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + + /* + * BB to AP mode + */ + if(path == RF92CD_PATH_A) { + for(index = 1; index < APK_BB_REG_NUM ; index++) + PHY_SetBBReg(priv, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + } + +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) { + PHY_SetBBReg(priv, 0x870, BIT(10), 1); + PHY_SetBBReg(priv, 0x870, BIT(26), 1); + PHY_SetBBReg(priv, 0x860, BIT(10), 0); + PHY_SetBBReg(priv, 0x864, BIT(10), 0); + } +#endif + + if(newVerAPK) { + if(path == RF92CD_PATH_A) { + PHY_SetBBReg(priv, 0xe30 , bMaskDWord, 0x01008c00); + PHY_SetBBReg(priv, 0xe34 , bMaskDWord, 0x01008c00); + } else if(path == RF92CD_PATH_B) { + PHY_SetBBReg(priv, 0xe50 , bMaskDWord, 0x01008c00); + PHY_SetBBReg(priv, 0xe54 , bMaskDWord, 0x01008c00); + } + } + + //MAC settings + _PHY_MACSettingCalibration(priv, MAC_REG, MAC_backup); + + + if(path == RF92CD_PATH_A) { + //Path B to standby mode + PHY_SetRFReg(priv, RF92CD_PATH_B, 0x0, bMaskDWord, 0x10000); + } else { + //Path A to standby mode + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMaskDWord, 0x10000); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x10, bMaskDWord, 0x1000f); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x11, bMaskDWord, 0x20103); + } + + /* + * Check Thermal value delta + */ + if (priv->pmib->dot11RFEntry.ther) { + ThermalValue = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x24, 0x1f, 1) & 0xff; + ThermalValue -= priv->pmib->dot11RFEntry.ther; + } + + delta_offset = ((ThermalValue+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 1; index < APK_BB_REG_NUM; index++) { + tmpReg = APK_RF_init_value[path][index]; + if (priv->pmib->dot11RFEntry.ther) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT(15))) //sign bit 0 + BB_offset = -BB_offset; + delta_V = APK_delta_mapping[index][delta_offset]; + BB_offset += delta_V; + + if(BB_offset < 0) { + tmpReg = tmpReg & (~BIT(15)); + BB_offset = -BB_offset; + } else { + tmpReg = tmpReg | BIT(15); + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } + + if(newVerAPK) + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xc, bMaskDWord, 0x8992e); + else + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xc, bMaskDWord, 0x8992f); + + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x0, bMaskDWord, APK_RF_value_0[path][index]); + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, tmpReg); + + /* + * PA11+PAD01111, one shot + */ + i = 0; + do { + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x800000); + PHY_SetBBReg(priv, APK_offset[path], bMaskDWord, APK_value[0]); + delay_ms(3); + PHY_SetBBReg(priv, APK_offset[path], bMaskDWord, APK_value[1]); + delay_ms(20); + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + + if(!newVerAPK) { + tmpReg = PHY_QueryRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xb, bMaskDWord, 1); + tmpReg = (tmpReg & 0x3E00) >> 9; + } else { + if(path == RF92CD_PATH_A) + tmpReg = PHY_QueryBBReg(priv, 0xbd8, 0x03E00000); + else + tmpReg = PHY_QueryBBReg(priv, 0xbd8, 0xF8000000); + } + i++; + } while((tmpReg > apkbound) && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + /* + * reload MAC default value + */ + _PHY_ReloadMACRegisters(priv, MAC_REG, MAC_backup); + + /* + * reload BB default value + */ + for(index = 1; index < APK_BB_REG_NUM ; index++) + PHY_SetBBReg(priv, BB_REG[index], bMaskDWord, BB_backup[index]); + +#ifdef HIGH_POWER_EXT_PA + if (priv->pshare->rf_ft_var.use_ext_pa) { + PHY_SetBBReg(priv, 0x870, bMaskDWord, tmp0x870); + PHY_SetBBReg(priv, 0x860, bMaskDWord, tmp0x860); + PHY_SetBBReg(priv, 0x864, bMaskDWord, tmp0x864); + } +#endif + + /* + * reload AFE default value + */ + _PHY_ReloadADDARegisters(priv, AFE_REG, AFE_backup, 16); + + + /* + * reload RF path default value + */ + for(path = 0; path < pathbound; path++) { + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if(path == RF92CD_PATH_B) { + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x10, bMaskDWord, 0x1000f); + PHY_SetRFReg(priv, RF92CD_PATH_A, 0x11, bMaskDWord, 0x20101); + } + + if(newVerAPK) { + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + } else { + if(APK_result[path][1] < 1) + APK_result[path][1] = 1; + else if (APK_result[path][1] > 5) + APK_result[path][1] = 5; + + if(APK_result[path][2] < 2) + APK_result[path][2] = 2; + else if (APK_result[path][2] > 6) + APK_result[path][2] = 6; + + if(APK_result[path][3] < 2) + APK_result[path][3] = 2; + else if (APK_result[path][3] > 6) + APK_result[path][3] = 6; + + if(APK_result[path][4] < 5) + APK_result[path][4] = 5; + else if (APK_result[path][4] > 9) + APK_result[path][4] = 9; + } + } + + for(path = 0; path < pathbound; path++) { + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(newVerAPK) { + if(path == RF92CD_PATH_A) + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xe, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); + } else { + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][2] << 5) | APK_result[path][3])); + PHY_SetRFReg(priv, (RF92CD_RADIO_PATH_E)path, 0xe, bMaskDWord, + ((APK_result[path][4] << 15) | (APK_result[path][4] << 10) | (APK_result[path][4] << 5) | APK_result[path][4])); + } + } +} + + + +/* +return FALSE => do IQK again +*/ +char _PHY_SimularityCompare(struct rtl8192cd_priv *priv, int result[][8], unsigned char c1, unsigned char c2) +{ + unsigned int i, j, diff, SimularityBitMap, bound = 0; + unsigned char final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + char bResult = TRUE, is2T = (GET_CHIP_VER(priv) == VERSION_8192C ? 1 : 0); + + bound = (is2T) ? 8 : 4; + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) { + if((i == 2 || i == 6) && !SimularityBitMap) { + if( result[c1][i]+ result[c1][i+1] == 0) + final_candidate[(i>>2)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i>>2)] = c1; + else + SimularityBitMap |= (1<>2); i++ ) { + if(final_candidate[i] != 0xFF) { + for( j = (i<<2); j < ((i+1)<<2)-2; j++) + result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + } + else if (!(SimularityBitMap & 0x03)) { //path A TX OK + for(i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + return FALSE; + } + else if (!(SimularityBitMap & 0x0c)) { //path A RX OK + for(i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + return FALSE; + } + else if (!(SimularityBitMap & 0x30) && is2T) { //path B TX OK + for(i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + return FALSE; + } + else if (!(SimularityBitMap & 0xc0) && is2T) { //path B RX OK + for(i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + return FALSE; + } + else + return FALSE; + +} + + +//bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +unsigned char _PHY_PathA_IQK(struct rtl8192cd_priv *priv, char configPathB) +{ + unsigned int regEAC, regE94, regE9C, regEA4; + unsigned char result = 0x00; + + + // RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); +#if defined(HIGH_POWER_EXT_PA) && defined(CONFIG_RTL_92C_SUPPORT) + if (priv->pshare->rf_ft_var.use_ext_pa){ + + //path-A IQK setting + PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140102); + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x28160804); + + //path-B IQK setting + if(configPathB) { + PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c22); + PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c22); + PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140102); + PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x28160804); + } +}else +#endif +{ + //path-A IQK setting + PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x10008c1f); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x10008c1f); + PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140102); + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, ((configPathB |IS_UMC_B_CUT_88C(priv)) ? 0x28160202 : 0x28160502)); + + //path-B IQK setting + if(configPathB) { + PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x10008c22); + PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x10008c22); + PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140102); + PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x28160202); + } +} + + + + //LO calibration setting + PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x001028d1); + + //One shot, path A LOK & IQK + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); + + // delay x ms + delay_ms(IQK_DELAY_TIME); + + // Check failed + regEAC = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + regE94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); + regE9C= PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); + regEA4= PHY_QueryBBReg(priv, 0xea4, bMaskDWord); + + if(!(regEAC & BIT(28)) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + if(!(regEAC & BIT(27)) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else { +// RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); + } + + return result; +} + +//bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +unsigned char _PHY_PathB_IQK(struct rtl8192cd_priv *priv) +{ + unsigned int regEAC, regEB4, regEBC, regEC4, regECC; + unsigned char result = 0x00; +#if 0 + //path-B IQK setting + RTPRINT(FINIT, INIT_IQK, ("Path-B IQK setting!\n")); + PHY_SetBBReg(pAdapter, 0xe50, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, 0xe54, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, 0xe58, bMaskDWord, 0x82140102); + PHY_SetBBReg(pAdapter, 0xe5c, bMaskDWord, 0x28160202); + + //LO calibration setting + RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); + PHY_SetBBReg(pAdapter, 0xe4c, bMaskDWord, 0x001028d1); +#endif + //One shot, path B LOK & IQK +// RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000002); + PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000000); + + // delay x ms + delay_ms(IQK_DELAY_TIME); + + // Check failed + regEAC = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + regEB4 = PHY_QueryBBReg(priv, 0xeb4, bMaskDWord); + regEBC= PHY_QueryBBReg(priv, 0xebc, bMaskDWord); + regEC4= PHY_QueryBBReg(priv, 0xec4, bMaskDWord); + regECC= PHY_QueryBBReg(priv, 0xecc, bMaskDWord); + + if(!(regEAC & BIT(31)) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT(30)) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else { +// RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); + } + + return result; + +} + +void _PHY_PathAFillIQKMatrix(struct rtl8192cd_priv *priv, char bIQKOK, int result[][8], unsigned char final_candidate, char bTxOnly) +{ + int Oldval_0, X, TX0_A, reg; + int Y, TX0_C; + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) { + Oldval_0 = (PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + TX0_C = (Y * Oldval_0) >> 8; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) { +// RTPRINT(FINIT, INIT_IQK, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + PHY_SetBBReg(priv, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + PHY_SetBBReg(priv, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); + } +} + + +void _PHY_PathBFillIQKMatrix(struct rtl8192cd_priv *priv, char bIQKOK, int result[][8], unsigned char final_candidate, char bTxOnly) +{ + int Oldval_1, X, TX1_A, reg; + int Y, TX1_C; + + //RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + TX1_C = (Y * Oldval_1) >> 8; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + PHY_SetBBReg(priv, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + PHY_SetBBReg(priv, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +void _PHY_PathAStandBy_8192C(struct rtl8192cd_priv *priv) +{ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00010000); + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); +} + +void _PHY_IQCalibrate(struct rtl8192cd_priv *priv, int result[][8], unsigned char t, char is2T) +{ + unsigned int i; + unsigned char PathAOK, PathBOK; + unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = { 0x85c, 0xe6c, 0xe70, 0xe74, + 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, + 0xed8, 0xedc, 0xee0, 0xeec }; + unsigned int IQK_MAC_REG[IQK_MAC_REG_NUM] = {0x522, 0x550, 0x551, 0x040}; + + char isNormal = IS_TEST_CHIP(priv) ? 0 : 1; + unsigned int retryCount = 2; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif + + if(t==0) { + // Save ADDA parameters, turn Path A ADDA on + _PHY_SaveADDARegisters(priv, ADDA_REG, priv->pshare->ADDA_backup, APK_AFE_REG_NUM); + _PHY_SaveMACRegisters(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); + } + + _PHY_PathADDAOn(priv, ADDA_REG, TRUE, is2T); + + if(t==0) { + // Store 0xC04, 0xC08, 0x874 vale + priv->pshare->RegC04 = PHY_QueryBBReg(priv, 0xc04, bMaskDWord); + priv->pshare->RegC08 = PHY_QueryBBReg(priv, 0xc08, bMaskDWord); + priv->pshare->Reg874 = PHY_QueryBBReg(priv, 0x874, bMaskDWord); + } + + //MAC settings + _PHY_MACSettingCalibration(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); + + //PHY_SetBBReg(priv, 0x800, bMaskDWord, (PHY_QueryBBReg(priv, 0x800, bMaskDWord)& ~ BIT(24))); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(priv, 0xa04, bMaskDWord))) ); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); + PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22204000); + + PHY_SetBBReg(priv, 0x870, BIT(10), 1); + PHY_SetBBReg(priv, 0x870, BIT(26), 1); + PHY_SetBBReg(priv, 0x860, BIT(10), 0); + PHY_SetBBReg(priv, 0x864, BIT(10), 0); + +#if defined(HIGH_POWER_EXT_PA) && defined(CONFIG_RTL_92C_SUPPORT) + //Allen TRSW to TX for external PA + PHY_SetBBReg(priv, 0x870, 0x60, 3); + PHY_SetBBReg(priv, 0x870, 0x600000, 3); + PHY_SetBBReg(priv, 0x860, 0x60, 1); + PHY_SetBBReg(priv, 0x864, 0x60, 1); +#endif + + if(is2T) { + PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00010000); + PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00010000); + } + + //Page B init + if(isNormal) + PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x00080000); + else + PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); + + if(is2T) { + if(isNormal) + PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x00080000); + else + PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x01007c00); + PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); + + for(i = 0 ; i < retryCount ; i++){ + PathAOK = _PHY_PathA_IQK(priv, is2T); + if(PathAOK == 0x03){ + result[t][0] = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + result[t][0] = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathAOK){ +// RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); + } + + if(is2T){ + _PHY_PathAStandBy_8192C(priv); + + // Turn Path B ADDA on + _PHY_PathADDAOn(priv, ADDA_REG, FALSE, is2T); + + for(i = 0 ; i < retryCount ; i++){ + PathBOK = _PHY_PathB_IQK(priv); + if(PathBOK == 0x03){ +// RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (PHY_QueryBBReg(priv, 0xec4, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (PHY_QueryBBReg(priv, 0xecc, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { +// RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ +// RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value +// RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, priv->pshare->RegC04); + PHY_SetBBReg(priv, 0x874, bMaskDWord, priv->pshare->Reg874); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, priv->pshare->RegC08); + + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + + // Restore RX initial gain + PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032ed3); + + if(is2T) + PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00032ed3); + + if(t!=0) { + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(priv, ADDA_REG, priv->pshare->ADDA_backup, 16); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(priv, IQK_MAC_REG, priv->pshare->IQK_MAC_backup); + } +} + + +void PHY_IQCalibrate_92C(struct rtl8192cd_priv *priv) +{ + int result[4][8]; //last is final result + unsigned char i, final_candidate; + char bPathAOK, bPathBOK; + int RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + char is12simular, is13simular, is23simular; + unsigned int temp_870, temp_860, temp_864, temp_a04; + +#ifdef MP_TEST + if (!priv->pshare->rf_ft_var.mp_specific) +#endif + { + if (priv->pshare->iqk_2g_done) + return; + priv->pshare->iqk_2g_done = 1; + } + + priv->pshare->IQK_total_cnt++; + + temp_870 = PHY_QueryBBReg(priv, 0x870, bMaskDWord); + temp_860 = PHY_QueryBBReg(priv, 0x860, bMaskDWord); + temp_864 = PHY_QueryBBReg(priv, 0x864, bMaskDWord); + //temp_800 = PHY_QueryBBReg(priv, 0x800, bMaskDWord); + temp_a04 = PHY_QueryBBReg(priv, 0xa04, bMaskDWord); + + memset(result, 0, sizeof(result)); + + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + for (i=0; i<3; i++) { + _PHY_IQCalibrate(priv, result, i, (GET_CHIP_VER(priv) == VERSION_8192C ? 1 : 0)); + + if(i == 1) { + is12simular = _PHY_SimularityCompare(priv, result, 0, 1); + if(is12simular) { + final_candidate = 0; + break; + } + } + + if(i == 2) { + is13simular = _PHY_SimularityCompare(priv, result, 0, 2); + if(is13simular) { + final_candidate = 0; + break; + } + + is23simular = _PHY_SimularityCompare(priv, result, 1, 2); + if(is23simular) + final_candidate = 1; + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } + + + RTL_W32(0x870, temp_870); + RTL_W32(0x860, temp_860); + RTL_W32(0x864, temp_864); + //RTL_W32(0x800, temp_800); + RTL_W32(0xa04, temp_a04); + + //load 0xe30 IQC default value + if(GET_CHIP_VER(priv) == VERSION_8188C) { + RTL_W32(0xe30, 0x01008c00); + RTL_W32(0xe34, 0x01008c00); + } + + for (i=0; i<4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + DEBUG_INFO("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC); + } + + if(final_candidate != 0xff) { + priv->pshare->RegE94 = RegE94 = result[final_candidate][0]; + priv->pshare->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + priv->pshare->RegEB4 = RegEB4 = result[final_candidate][4]; + priv->pshare->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + DEBUG_INFO ("IQK: final_candidate is %x\n",final_candidate); + DEBUG_INFO ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC); + bPathAOK = bPathBOK = TRUE; + } + else { + priv->pshare->RegE94 = priv->pshare->RegEB4 = 0x100; //X default value + priv->pshare->RegE9C = priv->pshare->RegEBC = 0x0; //Y default value + priv->pshare->IQK_fail_cnt++; + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + _PHY_PathAFillIQKMatrix(priv, bPathAOK, result, final_candidate, (RegEA4 == 0)? 1 :0); + if(GET_CHIP_VER(priv) == VERSION_8192C){ + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + _PHY_PathBFillIQKMatrix(priv, bPathBOK, result, final_candidate, (RegEC4 == 0)? 1 :0); + } +} + +#endif + + +// 92d IQK +#ifdef CONFIG_RTL_92D_SUPPORT +void IQK_92D_5G_n(struct rtl8192cd_priv *priv) +{ + unsigned int temp_a04, temp_c04, temp_874, temp_c08, temp_870, + temp_860, temp_864, temp_88c, temp_c50, temp_c58, temp_b30, + switch2PI=0, X, reg; //Oldval_0, Oldval_1, TX0_A, TX1_A; + u8 temp_522, temp_550, temp_551; + unsigned int cal_num=0, cal_retry=0, ADDA_backup[IQK_ADDA_REG_NUM]; + int Y, result[8][3], result_final[8]={0,0,0,0,0,0,0,0}; //TX0_C, TX1_C; + + unsigned int i, RX0REG0xe40[3], RX0REG0xe40_final=0, REG0xe40, REG0xe94, REG0xe9c, delay_count; + unsigned int REG0xeac, RX1REG0xe40[3], RX1REG0xe40_final=0, REG0xeb4, REG0xea4,REG0xec4; + unsigned char TX0IQKOK = FALSE, TX1IQKOK = FALSE; + unsigned int TX_X0, TX_Y0, TX_X1, TX_Y1, RX_X0, RX_Y0, RX_X1, RX_Y1; + unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + return IQK_92D_5G_phy0_n(priv); +#endif + + //always do IQK for MP mode +#ifdef MP_TEST + if (!priv->pshare->rf_ft_var.mp_specific) +#endif + { + if (priv->pmib->dot11RFEntry.macPhyMode == SINGLEMAC_SINGLEPHY) { + if (priv->pshare->iqk_5g_done) + return; + priv->pshare->iqk_5g_done = 1; + } + } + + printk(">> %s \n",__FUNCTION__); + + watchdog_kick(); + + /* + * Save MAC default value + */ + temp_522 = RTL_R8(0x522); + temp_550 = RTL_R8(0x550); + temp_551 = RTL_R8(0x551); + + /* + * Save BB Parameter + */ + temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); + temp_c04 = RTL_R32(0xc04); + temp_874 = RTL_R32(0x874); + temp_c08 = RTL_R32(0xc08); + temp_870 = RTL_R32(0x870); + temp_860 = RTL_R32(0x860); + temp_864 = RTL_R32(0x864); + temp_88c = RTL_R32(0x88c); + temp_c50 = RTL_R32(0xc50); // 01/11/2011 update + temp_c58 = RTL_R32(0xc58); // 01/11/2011 update + temp_b30 = RTL_R32(0xb30); // 03/03/2011 update + + /* + * Save AFE Parameters + */ + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + ADDA_backup[i] = RTL_R32(ADDA_REG[i]); + + /* + * ============== + * Path-A TX/RX IQK + * ============== + */ + while (cal_num < 3) { + /* + * Path-A AFE all on + */ + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + RTL_W32(ADDA_REG[i], 0x04db25a4); + + /* + * MAC register setting + */ + RTL_W8(0x522, 0x3f); + RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); + RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); + + /* + * IQK must be done in PI mode + */ + if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); + switch2PI++; + } + + /* + * BB setting + */ + //PHY_SetBBReg(priv, 0x800, BIT(24), 0); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); + PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22208000); + PHY_SetBBReg(priv, 0x88c, BIT(23)|BIT(22)|BIT(21)|BIT(20), 0xf); + PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); // 03/03/2011 update + + /* + * AP or IQK + */ + //PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); + //PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); + + // IQK-R03 2011/02/16 update + + //path A AP setting for IQK + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0); + PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x20000000); + //path B AP setting for IQK + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0); + PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x20000000); + + /* + * IQK global setting + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x10007c00); + PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); + + /* + * path-A IQK setting + */ + PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140307); // 01/11/2011 update +#ifdef USB_POWER_SUPPORT + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160c66); +#else + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160960); // 01/11/2011 update +#endif + + /* + * path-B IQK setting + */ + PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c2f); + PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c2f); + PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82110000); + PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68110000); + + /* + * LO calibration setting + */ + PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); + +#ifdef USB_POWER_SUPPORT + // path-A TRSW setting + PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); + PHY_SetBBReg(priv, 0x860, BIT(6)|BIT(5), 3); +#else + /* + * path-A PA on + */ + /* + PHY_SetBBReg(priv, 0x870, BIT(11)|BIT(10), 3); + PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); + PHY_SetBBReg(priv, 0x860, BIT(11)|BIT(10), 3); + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000f60); // 01/11/2011 update + PHY_SetBBReg(priv, 0x860, bMaskDWord, 0x66e60e30); // 01/11/2011 update +#endif + /* + * One shot, path A LOK & IQK + */ + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); + + /* + * Delay 10 ms + */ + delay_ms(10); + + delay_count = 0; + while (1){ + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + if ((REG0xeac&BIT(26))||(delay_count>20)){ + break; + }else { + delay_ms(1); + delay_count++; + } + } + /* + * Check_TX_IQK_A_result + */ + REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); + REG0xe94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); + if(((REG0xeac&BIT(28)) == 0) && (((REG0xe94&0x3FF0000)>>16)!=0x142)) { + TX0IQKOK = TRUE; + REG0xe9c = PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); + TX_X0 = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; + TX_Y0 = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; + RX0REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X0<<16) | TX_Y0; + DEBUG_INFO("TX_X0 %08x TX_Y0 %08x RX0REG0xe40 %08x\n", TX_X0, TX_Y0, RX0REG0xe40[cal_num]); + result[0][cal_num] = TX_X0; + result[1][cal_num] = TX_Y0; + } else { + TX0IQKOK = FALSE; + if (++cal_retry >= 10) { + printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); + break; + } + } + + /* + * Check_RX_IQK_A_result + */ + if(TX0IQKOK == TRUE) { + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + REG0xea4 = PHY_QueryBBReg(priv, 0xea4, bMaskDWord); + if(((REG0xeac&BIT(27)) == 0) && (((REG0xea4&0x3FF0000)>>16)!=0x132)) { + RX_X0 = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; + RX_Y0 = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; + DEBUG_INFO("RX_X0 %08x RX_Y0 %08x\n", RX_X0, RX_Y0); + result[2][cal_num] = RX_X0; + result[3][cal_num] = RX_Y0; + cal_num++; + } else { + PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x19008c00); + if (++cal_retry >= 10) { + printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); + break; + } + } + } + } + + if (cal_num == 3) { + result_final[0] = get_mean_of_2_close_value(result[0]); + result_final[1] = get_mean_of_2_close_value(result[1]); + result_final[2] = get_mean_of_2_close_value(result[2]); + result_final[3] = get_mean_of_2_close_value(result[3]); + RX0REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX0REG0xe40); + + priv->pshare->RegE94=result_final[0]; + priv->pshare->RegE9C=result_final[1]; + } else { + priv->pshare->RegE94=0x100; + priv->pshare->RegE9C=0x00; + } + + /* + * Path-A PA off + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); + PHY_SetBBReg(priv, 0x860, bMaskDWord, temp_860); + + + /* + * ============== + * Path-B TX/RX IQK + * ============== + */ + cal_num = cal_retry = 0; + while (cal_num < 3) { + /* + * Path-B AFE all on + */ + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, 0x0b1b25a4); + + /* + * path-A IQK setting + */ + PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82110000); + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68110000); + + /* + * path-B IQK setting + */ + PHY_SetBBReg(priv, 0xe50, bMaskDWord, 0x18008c22); + PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x18008c22); + PHY_SetBBReg(priv, 0xe58, bMaskDWord, 0x82140307); // 01/11/2011 update + + // 01/11/2011 update +#ifdef USB_POWER_SUPPORT + PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68160c66); +#else + PHY_SetBBReg(priv, 0xe5c, bMaskDWord, 0x68160960); // 01/11/2011 update +#endif + + /* + * LO calibration setting + */ + PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); + +#ifdef USB_POWER_SUPPORT + PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 3); + PHY_SetBBReg(priv, 0x864, BIT(6)|BIT(5), 3); +#else + /* + * path-B PA on + */ + /* + PHY_SetBBReg(priv, 0x870, BIT(27)|BIT(26), 3); + PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 3); + PHY_SetBBReg(priv, 0x864, BIT(11)|BIT(10), 3); + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x0f600700); + PHY_SetBBReg(priv, 0x864, bMaskDWord, 0x061f0d30); +#endif + + /* + * One shot, path A LOK & IQK + */ + PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000002); + PHY_SetBBReg(priv, 0xe60, bMaskDWord, 0x00000000); + + /* + * Delay 10 ms + */ + delay_ms(10); + + delay_count = 0; + while (1){ + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + if ((REG0xeac&BIT(29))||(delay_count>20)){ + break; + }else { + delay_ms(1); + delay_count++; + } + } + /* + * Check_TX_IQK_B_result + */ + REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + REG0xeb4 = PHY_QueryBBReg(priv, 0xeb4, bMaskDWord); + if(((REG0xeac&BIT(31)) == 0) && ((REG0xeb4&0x3FF0000)!=0x142)) { + TX1IQKOK = TRUE; + TX_X1 = (PHY_QueryBBReg(priv, 0xeb4, bMaskDWord)&0x3FF0000)>>16; + TX_Y1 = (PHY_QueryBBReg(priv, 0xebc, bMaskDWord)&0x3FF0000)>>16; + RX1REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X1<<16) | TX_Y1; + DEBUG_INFO("TX_X1 %08x TX_Y1 %08x RX1REG0xe40 %08x\n", TX_X1, TX_Y1, RX1REG0xe40[cal_num]); + result[4][cal_num] = TX_X1; + result[5][cal_num] = TX_Y1; + } else { + TX1IQKOK = FALSE; + if (++cal_retry >= 10) { + printk("%s Path-B Tx/Rx Check\n",__FUNCTION__); + break; + } + } + + /* + * Check_RX_IQK_B_result + */ + if(TX1IQKOK == TRUE) { + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + REG0xec4 = PHY_QueryBBReg(priv, 0xec4, bMaskDWord); + if(((REG0xeac&BIT(30)) == 0) && (((REG0xec4&0x3FF0000)>>16)!=0x132)) { + RX_X1 = (PHY_QueryBBReg(priv, 0xec4, bMaskDWord)&0x3FF0000)>>16; + RX_Y1 = (PHY_QueryBBReg(priv, 0xecc, bMaskDWord)&0x3FF0000)>>16; + DEBUG_INFO("RX_X1 %08x RX_Y1 %08x\n", RX_X1, RX_Y1); + result[6][cal_num] = RX_X1; + result[7][cal_num] = RX_Y1; + cal_num++; + } else { + PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xe54, bMaskDWord, 0x19008c00); + if (++cal_retry >= 10) { + printk("%s Path-B Tx/Rx Check\n",__FUNCTION__); + break; + } + } + } + } + + if (cal_num == 3) { + result_final[4] = get_mean_of_2_close_value(result[4]); + result_final[5] = get_mean_of_2_close_value(result[5]); + result_final[6] = get_mean_of_2_close_value(result[6]); + result_final[7] = get_mean_of_2_close_value(result[7]); + RX1REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX1REG0xe40); + + priv->pshare->RegEB4=result_final[4]; + priv->pshare->RegEBC=result_final[5]; + } else { + priv->pshare->RegEB4=0x100; + priv->pshare->RegEBC=0x00; + } + + /* + * Fill IQK result for Path A + */ + if (result_final[0]) { + /* + Oldval_0 = (PHY_QueryBBReg(priv, 0xc80, bMaskDWord) >> 22) & 0x3FF; + X = result_final[0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + PHY_SetBBReg(priv, 0xc80, 0x3FF, TX0_A); + PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X* Oldval_0>>7) & 0x1)); + + Y = result_final[1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + TX0_C = (Y * Oldval_0) >> 8; + PHY_SetBBReg(priv, 0xc94, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(priv, 0xc80, 0x003F0000, (TX0_C&0x3F)); + PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y* Oldval_0>>7) & 0x1)); + */ + + // IQK-R03 2011/02/16 update + X = result_final[0]; + Y = result_final[1]; + //printk("X=%x Y=%x\n",X,Y); + //Path-A OFDM_A + PHY_SetBBReg(priv, 0xe30, 0x03FF0000, X); + PHY_SetBBReg(priv, 0xc4c, BIT(24), 0); + //Path-A OFDM_C + PHY_SetBBReg(priv, 0xe30, 0x000003FF, Y); + PHY_SetBBReg(priv, 0xc4c, BIT(26), 0); + + if(result_final[2]) { + reg = result_final[2]; + PHY_SetBBReg(priv, 0xc14, 0x3FF, reg); + reg = result_final[3] & 0x3F; + PHY_SetBBReg(priv, 0xc14, 0xFC00, reg); + + reg = (result_final[3] >> 6) & 0xF; + PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); + + PHY_SetBBReg(priv, 0xe34, 0x03FF0000, result_final[2]); // X + PHY_SetBBReg(priv, 0xe34, 0x3FF, result_final[3]); //Y + } + } + + /* + * Fill IQK result for Path B + */ + if (result_final[4]) { + /* + Oldval_1 = (PHY_QueryBBReg(priv, 0xc88, bMaskDWord) >> 22) & 0x3FF; + + X = result_final[4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + PHY_SetBBReg(priv, 0xc88, 0x3FF, TX1_A); + PHY_SetBBReg(priv, 0xc4c, BIT(28), ((X* Oldval_1>>7) & 0x1)); + + Y = result_final[5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + TX1_C = (Y * Oldval_1) >> 8; + PHY_SetBBReg(priv, 0xc9c, 0xF0000000, ((TX1_C&0x3C0)>>6)); + PHY_SetBBReg(priv, 0xc88, 0x003F0000, (TX1_C&0x3F)); + PHY_SetBBReg(priv, 0xc4c, BIT(30), ((Y* Oldval_1>>7) & 0x1)); + */ + + // IQK-R03 2011/02/16 update + X = result_final[4]; + Y = result_final[5]; + //printk("X=%x Y=%x\n",X,Y); + //Path-A OFDM_A + PHY_SetBBReg(priv, 0xe50, 0x03FF0000, X); + PHY_SetBBReg(priv, 0xc4c, BIT(28), 0); + //Path-A OFDM_C + PHY_SetBBReg(priv, 0xe50, 0x000003FF, Y); + PHY_SetBBReg(priv, 0xc4c, BIT(30), 0); + + if(result_final[6]) { + reg = result_final[6]; + PHY_SetBBReg(priv, 0xc1c, 0x3FF, reg); + + reg = result_final[7] & 0x3F; + PHY_SetBBReg(priv, 0xc1c, 0xFC00, reg); + + reg = (result_final[7] >> 6) & 0xF; + PHY_SetBBReg(priv, 0xc78, 0x0000F000, reg); + + PHY_SetBBReg(priv, 0xe54, 0x03FF0000, result_final[6]); // X + PHY_SetBBReg(priv, 0xe54, 0x3FF, result_final[7]); //Y + } + } + + /* + * Path B PA off + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); + PHY_SetBBReg(priv, 0x864, bMaskDWord, temp_864); + + /* + * Exit IQK mode + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, temp_c04); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, temp_c08); + PHY_SetBBReg(priv, 0x874, bMaskDWord, temp_874); + //PHY_SetBBReg(priv, 0x800, bMaskDWord, temp_800); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, temp_a04); + PHY_SetBBReg(priv, 0x88c, bMaskDWord, temp_88c); + PHY_SetBBReg(priv, 0xb30, bMaskDWord, temp_b30); // 03/03/2011 update + //PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032fff); // 01/11/2011 update + //PHY_SetBBReg(priv, 0x844, bMaskDWord, 0x00032fff); // 01/11/2011 update + + // IQK-R03 2011/02/16 update + //path A IQ path to DP block + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); + //path B IQ path to DP block + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x010170b8); + + //path AB to initial gain + PHY_SetBBReg(priv, 0xc50, bMaskDWord, 0x50); // 01/11/2011 update + PHY_SetBBReg(priv, 0xc50, bMaskDWord, temp_c50); // 01/11/2011 update + PHY_SetBBReg(priv, 0xc58, bMaskDWord, 0x50); // 01/11/2011 update + PHY_SetBBReg(priv, 0xc58, bMaskDWord, temp_c58); // 01/11/2011 update + + + /* + * Reload MAC default value + */ + RTL_W8(0x550, temp_550); + RTL_W8(0x551, temp_551); + RTL_W8(0x522, temp_522); + + /* + * Switch back to SI if needed, after IQK + */ + if (switch2PI) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); + } + + /* + * Reload ADDA power saving parameters + */ + for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); + + +#if 0 //def CLIENT_MODE + clnt_save_IQK_res(priv); +#endif + + if (!TX0IQKOK && !TX1IQKOK) + priv->pshare->IQK_fail_cnt++; +} + + +void IQK_92D_2G(struct rtl8192cd_priv *priv) +{ + unsigned int cal_num=0, cal_retry=0, Oldval=0, temp_c04=0, temp_c08=0, temp_874=0, temp_eac; + unsigned int cal_e94, cal_e9c, cal_ea4, cal_eac, cal_eb4, cal_ebc, cal_ec4, cal_ecc; + unsigned int X, Y, val_e94[3], val_e9c[3], val_ea4[3], val_eac[3], val_eb4[3], val_ebc[3], val_ec4[3], val_ecc[3]; + unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; + unsigned int ADDA_backup[IQK_ADDA_REG_NUM], i; + u8 temp_522, temp_550, temp_551; + u32 temp_040, temp_a04, temp_870, temp_860, temp_864, temp_88c; + u8 switch2PI = 0; + unsigned char IQKOK = 0; + +#ifdef CONFIG_RTL_92D_DMDP + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + return IQK_92D_2G_phy1(priv); +#endif + + //always do IQK for MP mode +#ifdef MP_TEST + if (!priv->pshare->rf_ft_var.mp_specific) +#endif + { + if (priv->pmib->dot11RFEntry.macPhyMode == SINGLEMAC_SINGLEPHY) { + if (priv->pshare->iqk_2g_done) + return; + priv->pshare->iqk_2g_done = 1; + } + } + + printk(">> %s \n",__FUNCTION__); + + // Save ADDA power saving parameters + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + ADDA_backup[i] = RTL_R32(ADDA_REG[i]); + + /* + * Save MAC default value + */ + temp_522 = RTL_R8(0x522); + temp_550 = RTL_R8(0x550); + temp_551 = RTL_R8(0x551); + temp_040 = RTL_R32(0x40); + + // Save BB default + temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); + temp_870 = RTL_R32(0x870); + temp_860 = RTL_R32(0x860); + temp_864 = RTL_R32(0x864); + temp_88c = RTL_R32(0x88c); + + // Path-A ADDA all on + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + RTL_W32(ADDA_REG[i], 0x04db25a4); + + // IQ&LO calibration Setting + //IQK must be done in PI mode + if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); + switch2PI++; + } + + //MAC register setting + RTL_W8(0x522, 0x3f); + RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); + RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); + RTL_W32(0x40, 0); + + //BB setting + temp_c04 = RTL_R32(0xc04); + temp_c08 = RTL_R32(0xc08); + temp_874 = RTL_R32(0x874); + //PHY_SetBBReg(priv,0x800,BIT(24),0); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); + RTL_W32(0xc04, 0x03a05600); + RTL_W32(0xc08, 0x000800e4); + RTL_W32(0x874, 0x22204000); + + PHY_SetBBReg(priv, 0x870, BIT(10), 1); + PHY_SetBBReg(priv, 0x870, BIT(26), 1); + PHY_SetBBReg(priv, 0x860, BIT(10), 0); + PHY_SetBBReg(priv, 0x864, BIT(10), 0); + + PHY_SetBBReg(priv,0x88c,0x00f00000,0xf); + RTL_W32(0x840, 0x00010000); + RTL_W32(0x844, 0x00010000); + + //AP or IQK + RTL_W32(0xb68 , 0x0f600000); + RTL_W32(0xb6c , 0x0f600000); + + // IQK setting + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + RTL_W32(0xe40, 0x01007c00); + RTL_W32(0xe44, 0x01004800); + // path-A IQK setting + RTL_W32(0xe30, 0x10008c1f); + RTL_W32(0xe34, 0x10008c1f); + RTL_W32(0xe38, 0x82140102); + RTL_W32(0xe3c, 0x28160206); + // path-B IQK setting + RTL_W32(0xe50, 0x10008c22); + RTL_W32(0xe54, 0x10008c22); + RTL_W32(0xe58, 0x82140102); + RTL_W32(0xe5c, 0x28160206); + // LO calibration setting + RTL_W32(0xe4c, 0x00462911); + + // delay to ensure Path-A IQK success + delay_ms(10); + + // step 4: One shot, path A LOK & IQK + while (cal_num < 3) { + // One shot, path A LOK & IQK + RTL_W32(0xe48, 0xf9000000); + RTL_W32(0xe48, 0xf8000000); + // delay 1ms + delay_ms(1); + + // check fail bit and check abnormal condition, then fill BB IQ matrix + cal_e94 = (RTL_R32(0xe94) >> 16) & 0x3ff; + cal_e9c = (RTL_R32(0xe9c) >> 16) & 0x3ff; + cal_ea4 = (RTL_R32(0xea4) >> 16) & 0x3ff; + temp_eac = RTL_R32(0xeac); + cal_eac = (temp_eac >> 16) & 0x3ff; + if (!(temp_eac & BIT(28)) && !(temp_eac & BIT(27)) && + (cal_e94 != 0x142) && (cal_e9c != 0x42) && + (cal_ea4 != 0x132) && (cal_eac != 0x36)) { + val_e94[cal_num] = cal_e94; + val_e9c[cal_num] = cal_e9c; + val_ea4[cal_num] = cal_ea4; + val_eac[cal_num] = cal_eac; + cal_num++; + } else { + if (++cal_retry >= 10) { + printk("%s Path-A Check\n",__FUNCTION__); + break; + } + } + } + + if (cal_num == 3) { + cal_e94 = get_mean_of_2_close_value(val_e94); + cal_e9c = get_mean_of_2_close_value(val_e9c); + cal_ea4 = get_mean_of_2_close_value(val_ea4); + cal_eac = get_mean_of_2_close_value(val_eac); + + priv->pshare->RegE94=cal_e94; + priv->pshare->RegE9C=cal_e9c; + + Oldval = (RTL_R32(0xc80) >> 22) & 0x3ff; + + X = cal_e94; + PHY_SetBBReg(priv, 0xc80, 0x3ff, (X * Oldval)>>8); + PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X * Oldval) >> 7) & 0x1); + + Y = cal_e9c; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + PHY_SetBBReg(priv, 0xc94, 0xf0000000, (((Y * Oldval) >> 8) >> 6) & 0xf); + PHY_SetBBReg(priv, 0xc80, 0x003f0000, ((Y * Oldval) >> 8) & 0x3f); + PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y * Oldval) >> 7) & 0x1); + + PHY_SetBBReg(priv, 0xc14, 0x3ff, cal_ea4); + + PHY_SetBBReg(priv, 0xc14, 0xfc00, cal_eac & 0x3f); + + PHY_SetBBReg(priv, 0xca0, 0xf0000000, (cal_eac >> 6) & 0xf); + }else { + IQKOK++; + priv->pshare->RegE94=0x100; + priv->pshare->RegE9C=0x00; + } + + // step 5: Path-A standby mode + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + RTL_W32(0x840, 0x00010000); + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + + // step 6: Path-B ADDA all on + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + RTL_W32(ADDA_REG[i], 0x0b1b25a4); + + // step 7: One shot, path B LOK & IQK + cal_num = 0; + cal_retry = 0; + while (cal_num < 3) { + // One shot, path B LOK & IQK + RTL_W32(0xe60, 2); + RTL_W32(0xe60, 0); + // delay 1ms + delay_ms(1); + + // check fail bit and check abnormal condition, then fill BB IQ matrix + cal_eb4 = (RTL_R32(0xeb4) >> 16) & 0x3ff; + cal_ebc = (RTL_R32(0xebc) >> 16) & 0x3ff; + cal_ec4 = (RTL_R32(0xec4) >> 16) & 0x3ff; + cal_ecc = (RTL_R32(0xecc) >> 16) & 0x3ff; + temp_eac = RTL_R32(0xeac); + if (!(temp_eac & BIT(31)) && !(temp_eac & BIT(30)) && + (cal_eb4 != 0x142) && (cal_ebc != 0x42) && + (cal_ec4 != 0x132) && (cal_ecc != 0x36)) { + val_eb4[cal_num] = cal_eb4; + val_ebc[cal_num] = cal_ebc; + val_ec4[cal_num] = cal_ec4; + val_ecc[cal_num] = cal_ecc; + cal_num++; + } else { + if (++cal_retry >= 10) { + printk("%s Path-B Check\n",__FUNCTION__); + break; + } + } + } + + if (cal_num == 3) { + cal_eb4 = get_mean_of_2_close_value(val_eb4); + cal_ebc = get_mean_of_2_close_value(val_ebc); + cal_ec4 = get_mean_of_2_close_value(val_ec4); + cal_ecc = get_mean_of_2_close_value(val_ecc); + + priv->pshare->RegEB4=cal_eb4; + priv->pshare->RegEBC=cal_ebc; + + Oldval = (RTL_R32(0xc88) >> 22) & 0x3ff; + + X = cal_eb4; + PHY_SetBBReg(priv, 0xc88, 0x3ff, (X * Oldval) >> 8 ); + PHY_SetBBReg(priv, 0xc4c, BIT(28), ((X * Oldval) >> 7) & 0x1); + + Y = cal_ebc; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + PHY_SetBBReg(priv, 0xc9c, 0xf0000000, (((Y * Oldval) >> 8 ) >> 6) & 0xf); + PHY_SetBBReg(priv, 0xc88, 0x003f0000, ((Y * Oldval) >> 8 ) & 0x3f); + PHY_SetBBReg(priv, 0xc4c, BIT(30), ((Y * Oldval) >> 7) & 0x1); + + PHY_SetBBReg(priv, 0xc1c, 0x3ff, cal_ec4); + + PHY_SetBBReg(priv, 0xc1c, 0xfc00, cal_ecc & 0x3f); + + PHY_SetBBReg(priv, 0xc78, 0xf000, (cal_ecc >> 6) & 0xf); + }else { + IQKOK++; + priv->pshare->RegEB4=0x100; + priv->pshare->RegEBC=0x00; + } + + // step 8: back to BB mode, load original values + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + RTL_W32(0xc04, temp_c04); + RTL_W32(0xc08, temp_c08); + RTL_W32(0x874, temp_874); + //RTL_W32(0x800, temp_800); + RTL_W32(0xa04, temp_a04); + RTL_W32(0x88c, temp_88c); + RTL_W32(0x840, 0x32fff); + RTL_W32(0x844, 0x32fff); + RTL_W32(0x870, temp_870); + RTL_W32(0x860, temp_860); + RTL_W32(0x864, temp_864); + + /* + * Switch back to SI if needed, after IQK + */ + if (switch2PI) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); + } + + watchdog_kick(); + + /* + * Reload ADDA power saving parameters + */ + for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); + + /* + * Reload MAC default value + */ + RTL_W8(0x550, temp_550); + RTL_W8(0x551, temp_551); + RTL_W32(0x40, temp_040); + RTL_W8(0x522, temp_522); + + +#if 0 //def CLIENT_MODE + clnt_save_IQK_res(priv); +#endif + if (!IQKOK) + priv->pshare->IQK_fail_cnt++; +} +#ifdef CONFIG_RTL_92D_DMDP + +void IQK_92D_2G_phy1(struct rtl8192cd_priv *priv) +{ + unsigned int cal_num=0, cal_retry=0, Oldval=0, temp_c04=0, temp_c08=0, temp_874=0, temp_eac; + unsigned int cal_e94, cal_e9c, cal_ea4, cal_eac; + unsigned int X, Y, val_e94[3], val_e9c[3], val_ea4[3], val_eac[3]; + unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; + unsigned int ADDA_backup[IQK_ADDA_REG_NUM], i; + u8 temp_522, temp_550, temp_551; + u32 temp_040, temp_870, temp_860, temp_864, temp_a04, temp_88c; + u8 switch2PI = 0; + unsigned char IQKOK = 0; + +#ifdef MP_TEST + if (!priv->pshare->rf_ft_var.mp_specific) +#endif + { + if (priv->pshare->iqk_2g_done) + return; + priv->pshare->iqk_2g_done = 1; + } + + printk(">> %s \n",__FUNCTION__); + + // Save ADDA power saving parameters + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + ADDA_backup[i] = RTL_R32(ADDA_REG[i]); + + /* + * Save MAC default value + */ + temp_522 = RTL_R8(0x522); + temp_550 = RTL_R8(0x550); + temp_551 = RTL_R8(0x551); + temp_040 = RTL_R32(0x40); + + // Save BB default + temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); + temp_870 = RTL_R32(0x870); + temp_860 = RTL_R32(0x860); + temp_864 = RTL_R32(0x864); + temp_88c = RTL_R32(0x88c); + + // Path-A ADDA all on + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) { +#ifdef NON_INTR_ANTDIV + if (DMDP_PHY_QueryBBReg(0, 0xb30,BIT(27))) + RTL_W32(ADDA_REG[i], 0x04db25a4); + else +#endif + RTL_W32(ADDA_REG[i], 0x0b1b25a4); + } + + + // IQ&LO calibration Setting + + /* + * IQK must be done in PI mode + */ + if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); + switch2PI++; + } + + //MAC register setting + RTL_W8(0x522, 0x3f); + RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); + RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); + RTL_W32(0x40, 0); + + //BB setting + temp_c04 = RTL_R32(0xc04); + temp_c08 = RTL_R32(0xc08); + temp_874 = RTL_R32(0x874); + //PHY_SetBBReg(priv, 0x800, BIT(24), 0); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); + RTL_W32(0xc04, 0x03a05600); + RTL_W32(0xc08, 0x000800e4); + RTL_W32(0x874, 0x22204000); + + PHY_SetBBReg(priv, 0x870, BIT(10), 1); + PHY_SetBBReg(priv, 0x870, BIT(26), 1); + PHY_SetBBReg(priv, 0x860, BIT(10), 0); + PHY_SetBBReg(priv, 0x864, BIT(10), 0); + + PHY_SetBBReg(priv,0x88c,0x00f00000,0xf); + + RTL_W32(0x840, 0x00010000); + + //AP or IQK + RTL_W32(0xb68 , 0x0f600000); + RTL_W32(0xb6c , 0x0f600000); + + // IQK setting + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + RTL_W32(0xe40, 0x01007c00); + RTL_W32(0xe44, 0x01004800); + + // path-A IQK setting + RTL_W32(0xe30, 0x10008c22); + RTL_W32(0xe34, 0x10008c22); + RTL_W32(0xe38, 0x82140102); + RTL_W32(0xe3c, 0x28160206); + + // LO calibration setting + RTL_W32(0xe4c, 0x00462911); + + // delay to ensure Path-A IQK success + delay_ms(10); + + // step 4: One shot, path A LOK & IQK + while (cal_num < 3) { + // One shot, path A LOK & IQK + RTL_W32(0xe48, 0xf9000000); + RTL_W32(0xe48, 0xf8000000); + // delay 1ms + delay_ms(1); + + // check fail bit and check abnormal condition, then fill BB IQ matrix + cal_e94 = (RTL_R32(0xe94) >> 16) & 0x3ff; + cal_e9c = (RTL_R32(0xe9c) >> 16) & 0x3ff; + cal_ea4 = (RTL_R32(0xea4) >> 16) & 0x3ff; + temp_eac = RTL_R32(0xeac); + cal_eac = (temp_eac >> 16) & 0x3ff; + if (!(temp_eac & BIT(28)) && !(temp_eac & BIT(27)) && + (cal_e94 != 0x142) && (cal_e9c != 0x42) && + (cal_ea4 != 0x132) && (cal_eac != 0x36)) { + val_e94[cal_num] = cal_e94; + val_e9c[cal_num] = cal_e9c; + val_ea4[cal_num] = cal_ea4; + val_eac[cal_num] = cal_eac; + cal_num++; + } else { + if (++cal_retry >= 10) { + printk("%s Path-A Check\n",__FUNCTION__); + break; + } + } + } + + if (cal_num == 3) { + cal_e94 = get_mean_of_2_close_value(val_e94); + cal_e9c = get_mean_of_2_close_value(val_e9c); + cal_ea4 = get_mean_of_2_close_value(val_ea4); + cal_eac = get_mean_of_2_close_value(val_eac); + + priv->pshare->RegE94=cal_e94; + priv->pshare->RegE9C=cal_e9c; + + Oldval = (RTL_R32(0xc80) >> 22) & 0x3ff; + + X = cal_e94; + PHY_SetBBReg(priv, 0xc80, 0x3ff, (X * Oldval) >> 8); + PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X * Oldval) >> 7) & 0x1); + + Y = cal_e9c; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + PHY_SetBBReg(priv, 0xc94, 0xf0000000, (((Y * Oldval) >> 8) >> 6) & 0xf); + PHY_SetBBReg(priv, 0xc80, 0x003f0000, ((Y * Oldval) >> 8) & 0x3f); + PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y * Oldval) >> 7) & 0x1); + + PHY_SetBBReg(priv, 0xc14, 0x3ff, cal_ea4); + + PHY_SetBBReg(priv, 0xc14, 0xfc00, cal_eac & 0x3f); + + PHY_SetBBReg(priv, 0xca0, 0xf0000000, (cal_eac >> 6) & 0xf); + }else { + IQKOK++; + priv->pshare->RegE94=0x100; + priv->pshare->RegE9C=0x00; + } + + // back to BB mode, load original values + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + RTL_W32(0xc04, temp_c04); + RTL_W32(0xc08, temp_c08); + RTL_W32(0x874, temp_874); + //RTL_W32(0x800, temp_800); + RTL_W32(0xa04, temp_a04); + + RTL_W32(0x88c, temp_88c); + RTL_W32(0x840, 0x32fff); + RTL_W32(0x870, temp_870); + RTL_W32(0x860, temp_860); + RTL_W32(0x864, temp_864); + + // return to SI mode + if (switch2PI) { + RTL_W32(0x820, 0x01000000); + RTL_W32(0x828, 0x01000000); + } + + watchdog_kick(); + + /* + * Reload ADDA power saving parameters + */ + for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); + + /* + * Reload MAC default value + */ + RTL_W8(0x550, temp_550); + RTL_W8(0x551, temp_551); + RTL_W32(0x40, temp_040); + RTL_W8(0x522, temp_522); + + if (!IQKOK) + priv->pshare->IQK_fail_cnt++; +} + + +void IQK_92D_5G_phy0_n(struct rtl8192cd_priv *priv) +{ + unsigned int temp_a04, temp_c04, temp_874, temp_c08, temp_870, temp_860, temp_88c, temp_c50, temp_b30, + switch2PI=0, X, reg; //, Oldval_0, TX0_A; + u8 temp_522, temp_550, temp_551; + unsigned int cal_num=0, cal_retry=0, ADDA_backup[IQK_ADDA_REG_NUM]; + int Y, result[8][3], result_final[8]={0,0,0,0,0,0,0,0}; //, TX0_C; + + unsigned int i, RX0REG0xe40[3], RX0REG0xe40_final=0, REG0xe40, REG0xe94, REG0xe9c, delay_count; + unsigned int REG0xeac, REG0xea4; + unsigned char TX0IQKOK = FALSE; + unsigned int TX_X0, TX_Y0, RX_X0, RX_Y0; + unsigned int ADDA_REG[IQK_ADDA_REG_NUM] = {0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, + 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec}; + +#ifdef MP_TEST + if (!priv->pshare->rf_ft_var.mp_specific) +#endif + { + if (priv->pshare->iqk_5g_done) + return; + priv->pshare->iqk_5g_done = 1; + } + + printk(">> %s \n",__FUNCTION__); + + watchdog_kick(); + + /* + * Save MAC default value + */ + temp_522 = RTL_R8(0x522); + temp_550 = RTL_R8(0x550); + temp_551 = RTL_R8(0x551); + + /* + * Save BB Parameter + */ + temp_a04 = RTL_R32(0xa04);//RTL_R32(0x800); + temp_c04 = RTL_R32(0xc04); + temp_874 = RTL_R32(0x874); + temp_c08 = RTL_R32(0xc08); + temp_870 = RTL_R32(0x870); + temp_860 = RTL_R32(0x860); + temp_88c = RTL_R32(0x88c); + temp_c50 = RTL_R32(0xc50); + temp_b30 = RTL_R32(0xb30); // 03/03/2011 update + + /* + * Save AFE Parameters + */ + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + ADDA_backup[i] = RTL_R32(ADDA_REG[i]); + + /* + * ============== + * Path-A TX/RX IQK + * ============== + */ + while (cal_num < 3) { + /* + * Path-A AFE all on + */ + for( i = 0 ; i < IQK_ADDA_REG_NUM ; i++) { +#ifdef NON_INTR_ANTDIV + if (DMDP_PHY_QueryBBReg(0, 0xb30,BIT(27))) + RTL_W32(ADDA_REG[i], 0x0b1b25a4); + else +#endif + RTL_W32(ADDA_REG[i], 0x04db25a4); + } + + /* + * MAC register setting + */ + RTL_W8(0x522, 0x3f); + RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3))); + RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3))); + + /* + * IQK must be done in PI mode + */ + if (!PHY_QueryBBReg(priv, 0x820, BIT(8)) || !PHY_QueryBBReg(priv, 0x828, BIT(8))) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000100); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000100); + switch2PI++; + } + + /* + * BB setting + */ + //PHY_SetBBReg(priv, 0x800, BIT(24), 0); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, (0x0f000000 | temp_a04) ); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, 0x03a05600); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, 0x000800e4); + PHY_SetBBReg(priv, 0x874, bMaskDWord, 0x22208000); + PHY_SetBBReg(priv, 0x88c, BIT(23)|BIT(22)|BIT(21)|BIT(20), 0xf); + PHY_SetBBReg(priv, 0xb30, bMaskDWord, 0x00a00000); // 03/03/2011 update + + /* + * AP or IQK + */ + //PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x0f600000); + //PHY_SetBBReg(priv, 0xb6c, bMaskDWord, 0x0f600000); + + // IQK-R03 2011/02/16 update + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0); + PHY_SetBBReg(priv, 0xb68, bMaskDWord, 0x20000000); + + /* + * IQK global setting + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x808000); + PHY_SetBBReg(priv, 0xe40, bMaskDWord, 0x10007c00); + PHY_SetBBReg(priv, 0xe44, bMaskDWord, 0x01004800); + + /* + * path-A IQK setting + */ + PHY_SetBBReg(priv, 0xe30, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x18008c1f); + PHY_SetBBReg(priv, 0xe38, bMaskDWord, 0x82140307); // 01/11/2011 update + +#ifdef USB_POWER_SUPPORT + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160c66); +#else + PHY_SetBBReg(priv, 0xe3c, bMaskDWord, 0x68160960); // 01/11/2011 update +#endif + /* + * LO calibration setting + */ + PHY_SetBBReg(priv, 0xe4c, bMaskDWord, 0x00462911); + +#ifdef USB_POWER_SUPPORT + // PHY0 TRSW seting + PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); + PHY_SetBBReg(priv, 0x860, BIT(6)|BIT(5), 3); +#else + /* + * path-A PA on + */ + /* + PHY_SetBBReg(priv, 0x870, BIT(11)|BIT(10), 3); + PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 3); + PHY_SetBBReg(priv, 0x860, BIT(11)|BIT(10), 3); + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, 0x07000f60); // 01/11/2011 update + PHY_SetBBReg(priv, 0x860, bMaskDWord, 0x66e60e30); // 01/11/2011 update +#endif + /* + * One shot, path A LOK & IQK + */ + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf9000000); + PHY_SetBBReg(priv, 0xe48, bMaskDWord, 0xf8000000); + + /* + * Delay 10 ms + */ + delay_ms(10); + + delay_count = 0; + while (1){ + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + if ((REG0xeac&BIT(26))||(delay_count>20)){ + break; + }else { + delay_ms(1); + delay_count++; + } + } + + /* + * Check_TX_IQK_A_result + */ + REG0xe40 = PHY_QueryBBReg(priv, 0xe40, bMaskDWord); + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + REG0xe94 = PHY_QueryBBReg(priv, 0xe94, bMaskDWord); + if(((REG0xeac&BIT(28)) == 0) && (((REG0xe94&0x3FF0000)>>16)!=0x142)) { + TX0IQKOK = TRUE; + REG0xe9c = PHY_QueryBBReg(priv, 0xe9c, bMaskDWord); + TX_X0 = (PHY_QueryBBReg(priv, 0xe94, bMaskDWord)&0x3FF0000)>>16; + TX_Y0 = (PHY_QueryBBReg(priv, 0xe9c, bMaskDWord)&0x3FF0000)>>16; + RX0REG0xe40[cal_num] = (REG0xe40 & 0xfc00fc00) | (TX_X0<<16) | TX_Y0; + DEBUG_INFO("TX_X0 %08x TX_Y0 %08x RX0REG0xe40 %08x\n", TX_X0, TX_Y0, RX0REG0xe40[cal_num]); + result[0][cal_num] = TX_X0; + result[1][cal_num] = TX_Y0; + } else { + TX0IQKOK = FALSE; + if (++cal_retry >= 10) { + printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); + break; + } + } + + /* + * Check_RX_IQK_A_result + */ + if(TX0IQKOK == TRUE) { + REG0xeac = PHY_QueryBBReg(priv, 0xeac, bMaskDWord); + REG0xea4 = PHY_QueryBBReg(priv, 0xea4, bMaskDWord); + if(((REG0xeac&BIT(27)) == 0) && (((REG0xea4&0x3FF0000)>>16)!=0x132)) { + RX_X0 = (PHY_QueryBBReg(priv, 0xea4, bMaskDWord)&0x3FF0000)>>16; + RX_Y0 = (PHY_QueryBBReg(priv, 0xeac, bMaskDWord)&0x3FF0000)>>16; + DEBUG_INFO("RX_X0 %08x RX_Y0 %08x\n", RX_X0, RX_Y0); + result[2][cal_num] = RX_X0; + result[3][cal_num] = RX_Y0; + cal_num++; + } else { + PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100); + PHY_SetBBReg(priv, 0xe34, bMaskDWord, 0x19008c00); + if (++cal_retry >= 10) { + printk("%s Path-A Tx/Rx Check\n",__FUNCTION__); + break; + } + } + } + } + + if (cal_num == 3) { + result_final[0] = get_mean_of_2_close_value(result[0]); + result_final[1] = get_mean_of_2_close_value(result[1]); + result_final[2] = get_mean_of_2_close_value(result[2]); + result_final[3] = get_mean_of_2_close_value(result[3]); + RX0REG0xe40_final = 0x80000000 | get_mean_of_2_close_value(RX0REG0xe40); + + priv->pshare->RegE94=result_final[0]; + priv->pshare->RegE9C=result_final[1]; + } else { + priv->pshare->RegE94=0x100; + priv->pshare->RegE9C=0x00; + } + + /* + * Fill IQK result for Path A + */ + if (result_final[0]) { + /* + Oldval_0 = (PHY_QueryBBReg(priv, 0xc80, bMaskDWord) >> 22) & 0x3FF; + X = result_final[0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + PHY_SetBBReg(priv, 0xc80, 0x3FF, TX0_A); + PHY_SetBBReg(priv, 0xc4c, BIT(24), ((X* Oldval_0>>7) & 0x1)); + + Y = result_final[1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + TX0_C = (Y * Oldval_0) >> 8; + PHY_SetBBReg(priv, 0xc94, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(priv, 0xc80, 0x003F0000, (TX0_C&0x3F)); + PHY_SetBBReg(priv, 0xc4c, BIT(26), ((Y* Oldval_0>>7) & 0x1)); + */ + + // IQK-R03 2011/02/16 update + X = result_final[0]; + Y = result_final[1]; + //printk("X=%x Y=%x\n",X,Y); + //Path-A OFDM_A + PHY_SetBBReg(priv, 0xe30, 0x03FF0000, X); + PHY_SetBBReg(priv, 0xc4c, BIT(24), 0); + //Path-A OFDM_C + PHY_SetBBReg(priv, 0xe30, 0x000003FF, Y); + PHY_SetBBReg(priv, 0xc4c, BIT(26), 0); + + + if(result_final[2]) { + reg = result_final[2]; + PHY_SetBBReg(priv, 0xc14, 0x3FF, reg); + + reg = result_final[3] & 0x3F; + PHY_SetBBReg(priv, 0xc14, 0xFC00, reg); + + reg = (result_final[3] >> 6) & 0xF; + PHY_SetBBReg(priv, 0xca0, 0xF0000000, reg); + + PHY_SetBBReg(priv, 0xe34, 0x03FF0000, result_final[2]); // X + PHY_SetBBReg(priv, 0xe34, 0x3FF, result_final[3]); //Y + } + } + + /* + * Path-A PA off + */ + PHY_SetBBReg(priv, 0x870, bMaskDWord, temp_870); + PHY_SetBBReg(priv, 0x860, bMaskDWord, temp_860); + + /* + * Exit IQK mode + */ + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + PHY_SetBBReg(priv, 0xc04, bMaskDWord, temp_c04); + PHY_SetBBReg(priv, 0xc08, bMaskDWord, temp_c08); + PHY_SetBBReg(priv, 0x874, bMaskDWord, temp_874); + //PHY_SetBBReg(priv, 0x800, bMaskDWord, temp_800); + PHY_SetBBReg(priv, 0xa04, bMaskDWord, temp_a04); + PHY_SetBBReg(priv, 0x88c, bMaskDWord, temp_88c); + PHY_SetBBReg(priv, 0xb30, bMaskDWord, temp_b30); // 03/03/2011 update + //PHY_SetBBReg(priv, 0x840, bMaskDWord, 0x00032fff); // 01/11/2011 update + + //PHY0 IQ path to DP block + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8); + + PHY_SetBBReg(priv, 0xc50, bMaskDWord, 0x50); + PHY_SetBBReg(priv, 0xc50, bMaskDWord, temp_c50); + + /* + * Reload MAC default value + */ + RTL_W8(0x550, temp_550); + RTL_W8(0x551, temp_551); + RTL_W8(0x522, temp_522); + + /* + * Switch back to SI if needed, after IQK + */ + if (switch2PI) { + PHY_SetBBReg(priv, 0x820, bMaskDWord, 0x01000000); + PHY_SetBBReg(priv, 0x828, bMaskDWord, 0x01000000); + } + + /* + * Reload ADDA power saving parameters + */ + for(i = 0 ; i < IQK_ADDA_REG_NUM ; i++) + PHY_SetBBReg(priv, ADDA_REG[i], bMaskDWord, ADDA_backup[i]); + + if (!TX0IQKOK) + priv->pshare->IQK_fail_cnt++; +} +#endif + +#ifdef SW_LCK_92D + +#define TARGET_CHNL_NUM_5G 221 +#define TARGET_CHNL_NUM_2G 14 +#define CV_CURVE_CNT 64 + +unsigned int CurveIndex_5G[TARGET_CHNL_NUM_5G]={0}; +unsigned int CurveIndex_2G[TARGET_CHNL_NUM_2G]={0}; + +static unsigned int TargetChnl_5G[TARGET_CHNL_NUM_5G] = { +25141, 25116, 25091, 25066, 25041, +25016, 24991, 24966, 24941, 24917, +24892, 24867, 24843, 24818, 24794, +24770, 24765, 24721, 24697, 24672, +24648, 24624, 24600, 24576, 24552, +24528, 24504, 24480, 24457, 24433, +24409, 24385, 24362, 24338, 24315, +24291, 24268, 24245, 24221, 24198, +24175, 24151, 24128, 24105, 24082, +24059, 24036, 24013, 23990, 23967, +23945, 23922, 23899, 23876, 23854, +23831, 23809, 23786, 23764, 23741, +23719, 23697, 23674, 23652, 23630, +23608, 23586, 23564, 23541, 23519, +23498, 23476, 23454, 23432, 23410, +23388, 23367, 23345, 23323, 23302, +23280, 23259, 23237, 23216, 23194, +23173, 23152, 23130, 23109, 23088, +23067, 23046, 23025, 23003, 22982, +22962, 22941, 22920, 22899, 22878, +22857, 22837, 22816, 22795, 22775, +22754, 22733, 22713, 22692, 22672, +22652, 22631, 22611, 22591, 22570, +22550, 22530, 22510, 22490, 22469, +22449, 22429, 22409, 22390, 22370, +22350, 22336, 22310, 22290, 22271, +22251, 22231, 22212, 22192, 22173, +22153, 22134, 22114, 22095, 22075, +22056, 22037, 22017, 21998, 21979, +21960, 21941, 21921, 21902, 21883, +21864, 21845, 21826, 21807, 21789, +21770, 21751, 21732, 21713, 21695, +21676, 21657, 21639, 21620, 21602, +21583, 21565, 21546, 21528, 21509, +21491, 21473, 21454, 21436, 21418, +21400, 21381, 21363, 21345, 21327, +21309, 21291, 21273, 21255, 21237, +21219, 21201, 21183, 21166, 21148, +21130, 21112, 21095, 21077, 21059, +21042, 21024, 21007, 20989, 20972, +25679, 25653, 25627, 25601, 25575, +25549, 25523, 25497, 25471, 25446, +25420, 25394, 25369, 25343, 25318, +25292, 25267, 25242, 25216, 25191, +25166 }; + +static unsigned int TargetChnl_2G[TARGET_CHNL_NUM_2G] = { // channel 1~14 +26084, 26030, 25976, 25923, 25869, 25816, 25764, +25711, 25658, 25606, 25554, 25502, 25451, 25328 +}; + +void _PHY_CalcCurvIndex(struct rtl8192cd_priv *priv, unsigned int *TargetChnl, + unsigned int *CurveCountVal, char is5G, unsigned int *CurveIndex) +{ + unsigned int smallestABSVal = 0xffffffff, u4tmp; + unsigned char i, j; + unsigned char chnl_num = is5G?(TARGET_CHNL_NUM_5G) : (TARGET_CHNL_NUM_2G); + + + for(i=0; ipmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G? RF92CD_PATH_A:(priv->pmib->dot11RFEntry.macPhyMode==SINGLEMAC_SINGLEPHY?RF92CD_PATH_B:RF92CD_PATH_A); + unsigned int u4tmp = 0; +// unsigned char bNeedPowerDownRadio = FALSE; + unsigned int channel = priv->pshare->RegRF18[eRFPath]&0xff; + //unsigned int channel = PHY_QueryRFReg(priv, eRFPath, rRfChannel, 0xff, 1); + + DEBUG_INFO("====>phy_ReloadLCKSetting interface %d path %d ch %d [0x%05x]\n", priv->pshare->wlandev_idx, eRFPath, channel, priv->pshare->RegRF28[eRFPath]); + + //only for 92D C-cut SMSP + if(GET_CHIP_VER(priv)!=VERSION_8192D +#ifdef CONFIG_RTL_92C_SUPPORT + || IS_TEST_CHIP(priv) +#endif + ) + return; + + if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { + //Path-A for 5G + u4tmp = CurveIndex_5G[channel-1]; + //printk("%s ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n",__FUNCTION__, u4tmp); +#ifdef CONFIG_RTL_92D_DMDP + if(priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx == 1) + { + priv->pshare->RegRF28[RF92CD_PATH_A] = RTL_SET_MASK(priv->pshare->RegRF28[RF92CD_PATH_A],0x3f800,u4tmp,11); //DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, 0x3f800, u4tmp); + DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); + }else +#endif + { + priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],0x3f800,u4tmp,11); //PHY_SetRFReg(priv, eRFPath, 0x28, 0x3f800, u4tmp); + PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); + } + DEBUG_INFO("%s ver 3 set RF-B, 2G, 0x28 = 0x%05x [0x%05x]!!\n", __FUNCTION__, PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1), priv->pshare->RegRF28[eRFPath]); + } + else if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + { + u4tmp = CurveIndex_2G[channel-1]; + //printk("%s ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", __FUNCTION__, u4tmp); +#ifdef CONFIG_RTL_92D_DMDP + if(priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && priv->pshare->wlandev_idx == 0) + { + priv->pshare->RegRF28[RF92CD_PATH_A] = RTL_SET_MASK(priv->pshare->RegRF28[RF92CD_PATH_A],0x3f800,u4tmp,11); //DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, 0x28, 0x3f800, u4tmp); + DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]); + }else +#endif + { + priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],0x3f800,u4tmp,11); // PHY_SetRFReg(priv, eRFPath, 0x28, 0x3f800, u4tmp); + PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]); + } + DEBUG_INFO("%s ver 3 set RF-B, 2G, 0x28 = 0x%05x [0x%05x]!!\n", __FUNCTION__, PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1), priv->pshare->RegRF28[eRFPath]); + } + +} + +/* Software LCK */ +void PHY_LCCalibrate_92D(struct rtl8192cd_priv *priv) +{ + unsigned char tmpReg; + unsigned int RF_mode[2]; + unsigned int eRFPath, curMaxRFPath; + unsigned int i; + unsigned int curveCountVal[CV_CURVE_CNT*2]={0}; + unsigned short timeout = 800, timecount = 0; + + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else + curMaxRFPath = RF92CD_PATH_MAX; + + //Check continuous TX and Packet TX + tmpReg = RTL_R8(0xd03); + + if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case + RTL_W8(0xd03, tmpReg&0x8F); // disable all continuous TX + else // Deal with Packet TX case + RTL_W8(TXPAUSE, 0xFF); // block all queues + + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0F); + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + // 1. Read original RF mode + RF_mode[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits, 1); + + // 2. Set RF mode = standby mode + PHY_SetRFReg(priv, eRFPath, 0x00, 0x70000, 0x01); + + // switch CV-curve control by LC-calibration + PHY_SetRFReg(priv, eRFPath, 0x2B, BIT(17), 0x0); + + // jenyu suggest + PHY_SetRFReg(priv, eRFPath, 0x28, BIT(8), 0x1); + + //4. Set LC calibration begin + PHY_SetRFReg(priv, eRFPath, 0x18, BIT(15), 0x01); + + while(!(PHY_QueryRFReg(priv, eRFPath, 0x2A, BIT(11), 1) && + timecount <= timeout)){ + //DEBUG_INFO("PHY_LCK delay for %d ms=2\n", timecount); + delay_ms(50); + timecount+=50; + } + + //u4tmp = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); + + memset((void *)curveCountVal, 0, CV_CURVE_CNT*2); + + //Set LC calibration off + PHY_SetRFReg(priv, eRFPath, 0x18, BIT(15), 0x00); + + // jenyu suggest + PHY_SetRFReg(priv, eRFPath, 0x28, BIT(8), 0x0); + + //save Curve-counting number + for(i=0; i> 5; + + readVal2 = PHY_QueryRFReg(priv, eRFPath, 0x50, 0xffc00, 1); + + curveCountVal[2*i] = (((readVal & 0x1F) << 10) | readVal2); + } + + if(eRFPath == RF92CD_PATH_A +#ifdef CONFIG_RTL_92D_DMDP + && priv->pshare->wlandev_idx == 0 +#endif + ) + _PHY_CalcCurvIndex(priv, TargetChnl_5G, curveCountVal, TRUE, CurveIndex_5G); + else + _PHY_CalcCurvIndex(priv, TargetChnl_2G, curveCountVal, FALSE, CurveIndex_2G); + + // switch CV-curve control mode + PHY_SetRFReg(priv, eRFPath, 0x2B, BIT(17), 0x1); + + // store 0x28 for Reload_LCK + priv->pshare->RegRF28[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); + } + + //Restore original situation + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) + { + PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, RF_mode[eRFPath]); + } + + if((tmpReg&0x70) != 0) + { + //Path-A + RTL_W8(0xd03, tmpReg); + } + else // Deal with Packet TX case + { + RTL_W8(TXPAUSE, 0x00); + } + + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x00); + + phy_ReloadLCKSetting(priv); + +} + +#else +/* Hardware LCK */ +static void PHY_LCCalibrate_92D(struct rtl8192cd_priv *priv) +{ + unsigned char tmpReg; + unsigned int RF_mode[2], tmpu4Byte[2]; + + unsigned int eRFPath, curMaxRFPath; + unsigned char timeout = 800, timecount = 0; + + if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) + curMaxRFPath = RF92CD_PATH_B; + else + curMaxRFPath = RF92CD_PATH_MAX; + + + // Check continuous TX and Packet TX + tmpReg = RTL_R8(0xd03); + + if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case + RTL_W8(0xd03, tmpReg&0x8F); // disable all continuous TX + else // Deal with Packet TX case + RTL_W8(TXPAUSE, 0xFF); // block all queues + + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0F); + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + // 1. Read original RF mode + RF_mode[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits, 1); + + // 2. Set RF mode = standby mode + PHY_SetRFReg(priv, eRFPath, 0x00, 0x70000, 0x01); + + tmpu4Byte[eRFPath] = PHY_QueryRFReg(priv, eRFPath, 0x28, bMask20Bits, 1); + PHY_SetRFReg(priv, eRFPath, 0x28, 0x700, 0x07); + + //4. Set LC calibration begin + PHY_SetRFReg(priv, eRFPath, 0x18, 0x08000, 0x01); + } + + watchdog_kick(); + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + while(!(PHY_QueryRFReg(priv, eRFPath, 0x2A, BIT(11), 1) && + timecount <= timeout)){ + DEBUG_INFO("PHY_LCK delay for %d ms=2\n", timecount); + delay_ms(50); + timecount+=50; + } + } + + for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + PHY_SetRFReg(priv, eRFPath, 0x28, bMask20Bits, tmpu4Byte[eRFPath]); + priv->pshare->RegRF28[eRFPath] = tmpu4Byte[eRFPath]; + PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, RF_mode[eRFPath]); + } + + // Restore original situation + if ((tmpReg & 0x70) != 0) // Deal with contisuous TX case + RTL_W8(0xd03, tmpReg); + else // Deal with Packet TX case + RTL_W8(TXPAUSE, 0x00); + + PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0xF00000, 0x0); + +} + + +#endif //LCK_SW + +#ifdef DPK_92D + +#if 1 //copy from driver of station team +#define RF_AC 0x00 + +#define rPdp_AntA 0xb00 +#define rBndA 0xb30 +#define rPdp_AntB 0xb70 +#define rBndB 0xba0 + +#define RF_MODE1 0x10 +#define RF_MODE2 0x11 + +#define rTxAGC_A_CCK11_2_B_CCK11 0x86c + +#define RF_TX_G3 0x22 + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C +#define RF_TRSW 0x3F + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B + +#define RF_IQADJ_G1 0x01 +#define RF_IQADJ_G2 0x02 +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 + +#define DP_OFFSET_NUM 9 +#define DP_AP_CUREVE_SELECT_NUM 3 +#define DP_gain_loss 1 +#define DP_PA_BIAS_NUM 4 + +#define rTxAGC_B_CCK5_1_Mcs32 0x838 + +#define RF_TXBIAS 0x16 +#endif + +#define DPK_DEBUG(fmt,args...) + +#define DP_BB_REG_NUM 7 +//#define DP_BB_REG_NUM_A 11 +//#define DP_BB_REG_NUM_B 10 +#define DP_BB_REG_NUM_A 10 +#define DP_BB_REG_NUM_B 9 + +#define DP_BB_REG_NUM_settings 6 +#define DP_BB_REG_NUM_loop 30 +#define DP_BB_REG_NUM_loop_tx 12 +#define DP_BB_REG_NUM_loop_rx 8 +#define DP_BB_REG_NUM_loop_pa 4 +#define DP_RF_REG_NUM 4 +#define DP_SRAM_NUM 16 +//#define DP_SRAM_NUM_db 22 +#define DP_SRAM_NUM_db 86 + +#define DP_PATH_NUM 2 +#define DP_PA_MODEL_NUM 32 +#define DP_PA_MODEL_RUN_NUM 8 +#define DP_PA_MODEL_PER_RUN_NUM 4 +#define DP_RETRY_LIMIT 10 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 +#if 1 +#define DP_GAIN_LOSS_BOUND_NUM 14 +#else +#define DP_GAIN_LOSS_BOUND_NUM 8 +#endif +#define DP_OFFSET_NUM 9 +//#define DP_AP_CUREVE_SELECT_NUM 2 // 3 +#define DP_gain_loss 1 + + +void rtl8192cd_DPK_timer(unsigned long task_priv) +{ + struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + if (priv->pshare->pwr_trk_ongoing){ + DPK_DEBUG("==>_PHY_DigitalPredistortion() TxPowerTrackingInProgress() delay 100ms\n"); + mod_timer(&priv->pshare->DPKTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); + }else{ + PHY_DPCalibrate(priv); + } +} + +void _PHY_DPK_polling(struct rtl8192cd_priv *priv) +{ + unsigned int delaycount = 0, delaybound = 30, delay = 800; + unsigned int u4tmp; + + delaycount = 0; + + do{ + delay_us(delay); + + u4tmp = PHY_QueryBBReg(priv, 0xdf4, bMaskDWord); + //RTPRINT(FINIT, INIT_IQK, ("0xdf4 = 0x%x, delay %d us\n", u4tmp, delaycount*delay+800)); + delaycount++; + delay = 100; + u4tmp = (u4tmp & BIT(26)) >> 26; + }while(u4tmp == 0x01 && delaycount < delaybound); + +} + +// if AP curve check fail return FALSE +int _PHY_DPK_AP_curve_check(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned int RegiesterNum) +{ + unsigned int PA_power_temp[DP_PA_MODEL_NUM], i = 0, index = 5, + base = 532, ref1, ref2; + int power_I, power_Q; + + //store I, Q + + for(i = 0; i < DP_PA_MODEL_NUM; i++){ + power_I = (PA_power[i] >> 8); + if(power_I & BIT(7)) + power_I |= bMaskH3Bytes; + + power_Q = PA_power[i] & bMaskByte0; + if(power_Q & BIT(7)) + power_Q |= bMaskH3Bytes; + + PA_power_temp[i] = power_I*power_I+power_Q*power_Q; + } + + ref1 = PA_power_temp[0]; + for(i = 0; i < index; i++) + ref1 = (ref1 > PA_power_temp[i])?ref1:PA_power_temp[i]; + + ref2 = PA_power_temp[index]; + for(i = index; i < index*2; i++) + ref2 = (ref2 > PA_power_temp[i])?ref2:PA_power_temp[i]; + + DPK_DEBUG("==>_PHY_DPK_AP_cureve_check ref1 = 0x%x ref2 = 0x%x\n", ref1, ref2); + + if(ref1 == 0) + return FALSE; + + return ((ref2 << 9)/ref1) < base; +} + +// if DPK fail return FALSE +int _PHY_DPK_check(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned int RegiesterNum) +{ + unsigned int base = 407, PA_power_temp[2], i = 0; + int power_I, power_Q; + + while(i ==0 || i == (RegiesterNum-1)) + { + power_I = (PA_power[i] >> 8); + if(power_I & BIT(7)) + power_I |= bMaskH3Bytes; + + power_Q = PA_power[i] & bMaskByte0; + if(power_Q & BIT(7)) + power_Q |= bMaskH3Bytes; + + PA_power_temp[i==0?0:1] = power_I*power_I+ power_Q*power_Q; + + DPK_DEBUG("==>_PHY_DPK_check pa_power_temp[%d] 0x%x\n", i, PA_power_temp[i==0?0:1]); + + if(i == 0) + i = RegiesterNum -1; + else if (i == RegiesterNum -1) + break; + } + + //normalization + if(PA_power_temp[0] == 0) + return TRUE; + else + return (((PA_power_temp[1] << 9) /PA_power_temp[0]) <= base); + +} + +int _PHY_Find_Tx_Power_Index(struct rtl8192cd_priv *priv, unsigned int *PA_power, unsigned char path, unsigned char bPlus3db, char bDecreaseTxIndex, unsigned char *tx_index_out) +{ + unsigned char i, tx_index = bDecreaseTxIndex?0x0f:0x15; + unsigned int tmpReg[11], tmpBase, RegNum = 11, base = /*323*/256; + unsigned int PA_power_normal[11]; +// unsigned int check_base =bPlus3db?(400-base):(323-base); + unsigned int check_base =bPlus3db?400:323; + + int power_I, power_Q; + int index = -1; + + DPK_DEBUG("==>tx_index minus %d bplus3db %d\n", base, bPlus3db); + + _PHY_DPK_polling(priv); + + if(path == RF92CD_PATH_A) + { + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017018); + tmpReg[0] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); + tmpReg[1] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017019); + tmpReg[2] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); + tmpReg[3] = PHY_QueryBBReg(priv, 0xbe0, bMaskDWord); + tmpReg[4] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701a); + tmpReg[5] = PHY_QueryBBReg(priv, 0xbe0, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701b); + tmpReg[6] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); + tmpReg[7] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701c); + tmpReg[8] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701e); + tmpReg[9] = PHY_QueryBBReg(priv, 0xbdc, bMaskDWord); + + PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x0101701f); + tmpReg[10] = PHY_QueryBBReg(priv, 0xbe8, bMaskDWord); + + //RTPRINT(FINIT, INIT_IQK, ("==>_PHY_Find_Tx_Power_Index path A\n")); + + } + else if(path == RF92CD_PATH_B) + { + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017018); + tmpReg[0] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); + tmpReg[1] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017019); + tmpReg[2] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); + tmpReg[3] = PHY_QueryBBReg(priv, 0xbf0, bMaskDWord); + tmpReg[4] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701a); + tmpReg[5] = PHY_QueryBBReg(priv, 0xbf4, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701b); + tmpReg[6] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); + tmpReg[7] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701c); + tmpReg[8] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701e); + tmpReg[9] = PHY_QueryBBReg(priv, 0xbec, bMaskDWord); + + PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x0101701f); + tmpReg[10] = PHY_QueryBBReg(priv, 0xbf8, bMaskDWord); + + //RTPRINT(FINIT, INIT_IQK, ("==>_PHY_Find_Tx_Power_Index path B\n")); + + } + + for(i = 0; i < RegNum; i++) + { + power_I = (tmpReg[i] >> 8); + if(power_I & BIT(7)) + power_I |= bMaskH3Bytes; + + power_Q = tmpReg[i] & bMaskByte0; + if(power_Q & BIT(7)) + power_Q |= bMaskH3Bytes; + + PA_power[i] = power_I*power_I+ power_Q*power_Q; + } + + //normalization + tmpBase = PA_power[0]; + //RTPRINT(FINIT, INIT_IQK, ("==>PA_power START normalized\n")); + + if(tmpBase == 0) + DPK_DEBUG("==>PA_power[0] is ZERO !!!!!\n"); + + for(i = 0; i < RegNum; i++) + { + if(tmpBase != 0) + PA_power[i] = (PA_power[i] << 9) /tmpBase; + else + PA_power[i] = (PA_power[i] << 9) ; + PA_power_normal[i] = PA_power[i]; + PA_power[i] = (PA_power[i] > base)?(PA_power[i] - base):(base - PA_power[i]); + DPK_DEBUG("==>PA_power normalized index %d value 0x%x\n", i, PA_power[i]); + } + + //choose min for TX index to do DPK + base = bMaskDWord; + for(i = 0; i < RegNum; i++) + { + if(PA_power[i] < base) + { + base = PA_power[i]; + index = i; + } + } + + if(index == -1) + { + tx_index = 0x1c; + index = 0x1f - tx_index; + } + else + { + tx_index += index; + } + + DPK_DEBUG("==>tx_index result 0x%x PA_power[%d] = 0x%x\n", tx_index, index, PA_power[index]); + + *tx_index_out = tx_index; + + //Check pattern reliability + if(((PA_power_normal[index] > check_base) && (tx_index == 0x1f)) || + ((PA_power_normal[10] > base) && (!bPlus3db)) || + ((tx_index < 0x1a) && (!bPlus3db)) || + ((tx_index < 0x13) && (bDecreaseTxIndex)) + ) + return FALSE; + else + return TRUE; +// return tx_index; + +} + +unsigned char _PHY_Find_Rx_Power_Index(struct rtl8192cd_priv *priv, unsigned char tx_index, unsigned char rx_index, unsigned char path, char *bDecreaseTxIndex) +{ +// u1Byte rx_index = 0x04; + unsigned int tmpReg; + int power_I, power_Q, tmp; + unsigned char bPlus = FALSE, bMinus = FALSE; + unsigned short offset[2][2] = {{ //path, offset + 0xb28, 0xbe8},{ + 0xb98, 0xbf8}}; + int round = 0; + + while (TRUE) { + tmpReg = 0x52000 | tx_index | (rx_index << 5); + PHY_SetRFReg(priv, path, RF_AC, bMask20Bits, tmpReg); + //RTPRINT(FINIT, INIT_IQK, ("==>RF 0ffset 0 = 0x%x readback = 0x%x\n", tmpReg, + //PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); + + //----send one shot signal----// + PHY_SetBBReg(priv, offset[path][0], bMaskDWord, 0x80080000); //0xb28, 0xb98 + PHY_SetBBReg(priv, offset[path][0], bMaskDWord, 0x00080000); + + _PHY_DPK_polling(priv); + + tmpReg = PHY_QueryBBReg(priv, offset[path][1], bMaskDWord); + power_I = ((tmpReg & bMaskByte1) >> 8); + power_Q = tmpReg & bMaskByte0; + + if(power_I & BIT(7)) + { + power_I |= bMaskH3Bytes; + power_I = 0-power_I; //absolute value + } + + if(power_Q & BIT(7)) + { + power_Q |= bMaskH3Bytes; + power_Q = 0-power_Q; + } + //RTPRINT(FINIT, INIT_IQK, ("==>rx_index 0x%x I = 0x%x Q = 0x%x offset 0xbe8 = 0x%x\n", rx_index, power_I, power_Q, tmpReg)); + + tmp = (power_I > power_Q)? power_I:power_Q; + +#if 0 + if((rx_index == 0 && tmp > 0x6f)||(rx_index == 31 && tmp < 0x50)) + break; +#endif + + if((tmp<= 0x6f && tmp >= 0x50) ) + { + break; + } + else if(tmp < 0x50) + { + bPlus = TRUE; + if(bMinus) + { + rx_index++; + break; + } +// rx_index++; + rx_index += 2; + } + else if (tmp > 0x6f) + { + bMinus = TRUE; + if(bPlus) + { + rx_index--; + break; + } +// rx_index--; + rx_index -= 2; + } + + if(rx_index == 0 || rx_index == 31) + break; + + if (++round > 10000) { + panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); + break; + } + } + if(rx_index == 0 && tmp > 0x6f) + *bDecreaseTxIndex = TRUE; + + DPK_DEBUG("==>rx_index FINAL 0x%x I = 0x%x Q = 0x%x\n", rx_index, power_I, power_Q); + + return rx_index; + +} + +void PHY_DPCalibrate(struct rtl8192cd_priv *priv) +{ + char is2T = ((priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) ?1 :0); + + unsigned int tmpReg, value32/*, checkbit*/; + unsigned int AFE_backup[IQK_ADDA_REG_NUM]; + static unsigned int AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, 0xe6c, 0xe70, 0xe74, 0xe78, + 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, + 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, + 0xeec}; + + static unsigned int BB_backup[DP_BB_REG_NUM]; + static unsigned int BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_AnalogParameter4, rFPGA0_XAB_RFInterfaceSW, + rTxAGC_B_CCK11_A_CCK2_11 + }; + + static unsigned int BB_backup_A[DP_BB_REG_NUM_A]; + static unsigned int BB_REG_A[DP_BB_REG_NUM_A] = { + rFPGA0_XA_RFInterfaceOE, rTxAGC_A_Rate18_06, + rTxAGC_A_Rate54_24, rTxAGC_A_CCK1_Mcs32, + 0xe0c, rTxAGC_A_Mcs03_Mcs00, + rTxAGC_A_Mcs07_Mcs04, rTxAGC_A_Mcs11_Mcs08, + rTxAGC_A_Mcs15_Mcs12, rOFDM0_XAAGCCore1/*, + rBndA*/ + }; + + + static unsigned int BB_backup_B[DP_BB_REG_NUM_B]; + static unsigned int BB_REG_B[DP_BB_REG_NUM_B] = { + rFPGA0_XB_RFInterfaceOE, rTxAGC_B_Rate18_06, + rTxAGC_B_Rate54_24, rTxAGC_B_CCK1_55_Mcs32, + rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, + rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12, + rOFDM0_XBAGCCore1 /*, rBndB*/ + }; + + static unsigned int BB_settings[DP_BB_REG_NUM_settings] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0xccf000c0/*, 0x07600760*/}; + + static unsigned int BB_REG_loop[DP_PATH_NUM][DP_BB_REG_NUM_loop] = { + {0xb00, 0xb04, 0xb28, 0xb68, + 0xb08, 0xb0c, 0xb10, 0xb14, + 0xb18, 0xb1c, 0xb20, 0xb24, + 0xe28, 0xb00, 0xb04, 0xb08, + 0xb0c, 0xb10, 0xb14, 0xb18, + 0xb1c, 0xb20, 0xb24, 0xb28, + 0xb2c, rBndA, 0xb34, 0xb38, + 0xb3c, 0xe28}, + {0xb70, 0xb74, 0xb98, 0xb6C, + 0xb78, 0xb7c, 0xb80, 0xb84, + 0xb88, 0xb8c, 0xb90, 0xb94, + 0xe28, 0xb60, 0xb64, 0xb68, + 0xb6c, 0xb70, 0xb74, 0xb78, + 0xb7c, 0xb80, 0xb84, 0xb88, + 0xb8c, 0xb90, 0xb94, 0xb98, + 0xb9c, 0xe28} + }; + + static unsigned int BB_settings_loop[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x41382e21, 0x5b554f48, 0x6f6b6661, 0x817d7874, + 0x908c8884, 0x9d9a9793, 0xaaa7a4a1, 0xb6b3b0ad, + 0x40000000, 0x7d327c18, 0x7e057db3, 0x7e5f7e37, + 0x7e967e7c, 0x7ebe7eac, 0x7ed77ecc, 0x7eee7ee4, + 0x7f017ef9, 0x7f0e7f07, 0x7f1c7f15, 0x7f267f20, + 0x7f2f7f2a, 0x7f377f34, 0x7f3e7f3b, 0x7f457f42, + 0x7f4b7f48, 0x00000000 + }; + + static unsigned int BB_settings_loop_3db[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x5b4e402e, 0x7f776f65, 0x9c968f88, 0xb5afa8a3, + 0xcac4bfb9, 0xdcd8d4ce, 0xeeeae6e2, 0xfffbf7f2, + 0x40000000, 0x7dfe7d32, 0x7e967e59, 0x7ed77eba, + 0x7efd7eeb, 0x7f1a7f0e, 0x7f2d7f25, 0x7f3c7f36, + 0x7f4a7f44, 0x7f547f4e, 0x7f5d7f58, 0x7f657f60, + 0x7f6a7f68, 0x7f717f6e, 0x7f767f73, 0x7f7b7f78, + 0x7f7f7f7d, 0x00000000 + }; + + static unsigned int BB_settings_loop_tx[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x21212121, 0x21212121, 0x21212121, 0x21212121, + 0x21212121, 0x21212121, 0x21212121, 0x21212121, + 0x40000000, 0x7c187c18, 0x7c187c18, 0x7c187c18, + 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, + 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, + 0x7c187c18, 0x7c187c18, 0x7c187c18, 0x7c187c18, + 0x7c187c18, 0x00000000 + }; + + static unsigned int BB_settings_loop_tx_3db[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, + 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, 0x2e2e2e2e, + 0x40000000, 0x7d327d32, 0x7d327d32, 0x7d327d32, + 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, + 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, + 0x7d327d32, 0x7d327d32, 0x7d327d32, 0x7d327d32, + 0x7d327d32, 0x00000000 + }; + + + //for find 2dB loss point + static unsigned int BB_settings_loop_tx_2[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x41382e21, 0x5b554f48, 0x6f6b6661, 0x817d7874, + 0x908c8884, 0x9d9a9793, 0xaaa7a4a1, 0xb6b3b0ad, + 0x40000000, 0x7d327c18, 0x7e057db3, 0x7e5f7e37, + 0x7e967e7c, 0x7ebe7eac, 0x7ed77ecc, 0x7eee7ee4, + 0x7f017ef9, 0x7f0e7f07, 0x7f1c7f15, 0x7f267f20, + 0x7f2f7f2a, 0x7f377f34, 0x7f3e7f3b, 0x7f457f42, + 0x7f4b7f48, 0x00000000 + }; + + //for find 2dB loss point + static unsigned int BB_settings_loop_tx_2_3db[DP_BB_REG_NUM_loop] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x5b4e402e, 0x7f776f65, 0x9c968f88, 0xb5afa8a3, + 0xcac4bfb9, 0xdcd8d4ce, 0xeeeae6e2, 0xfffbf7f2, + 0x40000000, 0x7dfe7d32, 0x7e967e59, 0x7ed77eba, + 0x7efd7eeb, 0x7f1a7f0e, 0x7f2d7f25, 0x7f3c7f36, + 0x7f4a7f44, 0x7f547f4e, 0x7f5d7f58, 0x7f657f60, + 0x7f6a7f68, 0x7f717f6e, 0x7f767f73, 0x7f7b7f78, + 0x7f7f7f7d, 0x00000000 + }; + + + static unsigned int BB_settings_loop_rx[DP_BB_REG_NUM_loop_rx] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x21212121, 0x40000000, 0x7c187c18, 0x00000000 + }; + + static unsigned int BB_settings_loop_rx_3db[DP_BB_REG_NUM_loop_rx] = { + 0x01017e18, 0xf76d9f84, 0x00080000, 0x11880000, + 0x2e2e2e2e, 0x40000000, 0x7d327d32, 0x00000000 + }; + + static unsigned int BB_settings_loop_pa[DP_BB_REG_NUM_loop_pa] = { + 0x02096eb8, 0xf76d9f84, 0x00044499, 0x02880140 + }; + + static unsigned int BB_settings_loop_dp[DP_BB_REG_NUM_loop_pa] = { + 0x01017098, 0x776d9f84, 0x00000000, 0x08080000 + }; + + unsigned int *BB_settings_temp; + + static unsigned char Sram_db_settings[DP_SRAM_NUM_db] = { + 0xfe, 0xf0, 0xe3, 0xd6, 0xca, + 0xbf, 0xb4, 0xaa, 0xa0, 0x97, + 0x8f, 0x87, 0x7f, 0x78, 0x71, + 0x6b, 0x65, 0x5f, 0x5a, 0x55, + 0x50, 0x4c, 0x47, 0x43, 0x40, + 0x3c, 0x39, 0x35, 0x32, 0x2f, + 0x2d, 0x2a, 0x28, 0x26, 0x23, + 0x21, 0x20, 0x1e, 0x1c, 0x1a, + 0x19, 0x18, 0x16, 0x16, 0x14, + 0x13, 0x12, 0x11, 0x10, 0x0f, + 0x0e, 0x0d, 0x0c, 0x0c, 0x0b, + 0x0a, 0x0a, 0x09, 0x09, 0x08, + 0x08, 0x07, 0x07, 0x06, 0x06, + 0x06, 0x05, 0x05, 0x05, 0x04, + 0x04, 0x04, 0x04, 0x03, 0x03, + 0x03, 0x03, 0x03, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, + 0x01 + }; + + //unsigned int pwsf[DP_SRAM_NUM]; + + static unsigned int offset[2][DP_OFFSET_NUM] = {{ //path, offset + 0xe34, 0xb28, 0xb00, 0xbdc, 0xbc0, + 0xbe8, rOFDM0_XATxIQImbalance, rBndA, + 0xb68},{ + 0xe54, 0xb98, 0xb70, 0xbec, 0xbc4, + 0xbf8, rOFDM0_XBTxIQImbalance, rBndB, + 0xb6c}}; + + //unsigned char OFDM_min_index = 6, OFDM_min_index_internalPA = 3; + unsigned char OFDM_index[2]; + //unsigned char retrycount = 0, retrybound = 1; + + unsigned int RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + static unsigned int RF_REG[DP_RF_REG_NUM] = { + RF_TX_G3, RF_TXPA_A4, RF_RXRF_A3, + RF_BS_PA_APSET_G1_G4/*, RF_BS_PA_APSET_G5_G8, + RF_BS_PA_APSET_G9_G11*/}; + + static unsigned int RF_AP_curve_select[DP_AP_CUREVE_SELECT_NUM] = { + 0x7bdef, 0x94a52, 0xa5294/*, 0xb5ad6*/ }; + + static unsigned int RF_PA_BIAS[3][DP_PA_BIAS_NUM] = {{ //40MHz / 20MHz, original + 0xe189f, 0xa189f, 0x6189f, 0x2189f },{ + 0xe087f, 0xa087f, 0x6087f, 0x2087f },{ + 0xe1874, 0xa1874, 0x61874, 0x21874}}; + + unsigned int PA_model_backup[DP_PATH_NUM][DP_PA_MODEL_NUM]; + + unsigned int PA_power[DP_PATH_NUM][DP_PA_MODEL_RUN_NUM*2]; + +#if DP_gain_loss == 1 + + int power_I, power_Q, coef; + + int gain_loss_backup[DP_PATH_NUM][DP_PA_MODEL_NUM]; //I,Q + + static unsigned int gain_loss_bound[DP_GAIN_LOSS_BOUND_NUM] = { + 63676, 60114 , 56751 , 53577 , 49145, + 47750, 45079 , 42557 , 40177 , 37929 , + 35807 , 33804 , 31913, 30128 + }; + + static int gain_loss_coef[DP_GAIN_LOSS_BOUND_NUM+1] = { + 512, 527, 543, 558, 573, + 589, 609, 625, 645, 666, + 681, 701, 722, 742, 768 + }; + +// BOOLEAN bNegative = FALSE; +// unsigned char index_for_zero_db = 24, AP_curve_index = 0; + unsigned char GainLossIndex = 0; //0db, 0x40 + char SramIndex = 24; + unsigned char /*index_for_zero_db = 6,*/ AP_curve_index = 0; + +#else + + unsigned char index_for_zero_db = 6, AP_curve_index = 0; + int power_I, power_Q; + static unsigned int gain_loss_bound[DP_GAIN_LOSS_BOUND_NUM] = { + 61870, 55142, 49145, 43801, 39037, + 34792, 31008, 27636 + }; +#endif + + unsigned int MAC_backup[IQK_MAC_REG_NUM]; + static unsigned int MAC_REG[IQK_MAC_REG_NUM] = { + 0x522, 0x550, 0x551, 0x040}; + + //unsigned int AFE_on_off[PATH_NUM] = { + // 0x04db25a4, 0x0b1b25a4}; //path A on path B path A off path B on + + unsigned char path_num, /*path_bound,*/ path = RF92CD_PATH_A, i, j, tx_index, rx_index; + int index, index_1, index_repeat; + + char bInternalPA = FALSE; +#if (DP_gain_loss != 1) + char SkipStep5 = FALSE; +#endif + char bPlus3db = FALSE, bDecreaseTxIndex = FALSE, bDecreaseTxIndexWithRx = FALSE; + +#ifdef DFS + if ((priv->pshare->rf_ft_var.dfsdelayiqk) && + (OPMODE & WIFI_AP_STATE) && + !priv->pmib->dot11DFSEntry.disable_DFS && + (timer_pending(&priv->ch_avail_chk_timer) || + priv->pmib->dot11DFSEntry.disable_tx)) + return; +#endif + + DPK_DEBUG("==>_PHY_DigitalPredistortion() interface index %d is2T = %d\n", priv->pshare->wlandev_idx, is2T); //anchin + + DPK_DEBUG("_PHY_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R")); + + DPK_DEBUG("==>_PHY_DigitalPredistortion() current thermal meter = 0x%x PG thermal meter = 0x%x bPlus3db %d\n", + priv->pshare->ThermalValue_DPKtrack, priv->pmib->dot11RFEntry.ther, bPlus3db); + + if ((priv->pmib->dot11RFEntry.phyBandSelect!= PHY_BAND_5G)||(GET_CHIP_VER(priv)!=VERSION_8192D)) + return; + + bInternalPA = priv->pshare->rf_ft_var.use_intpa92d; + + if(!is2T) + path_num = 1; + else + path_num = 2; + + if(!bInternalPA) { + DPK_DEBUG("==>_PHY_DigitalPredistortion() NOT internal5G\n"); + return; + } + + if(priv->pshare->pwr_trk_ongoing){ + DPK_DEBUG("==>_PHY_DigitalPredistortion() TxPowerTrackingInProgress() delay 100ms\n"); + mod_timer(&priv->pshare->DPKTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(100)); + return; + } + + OFDM_index[RF92CD_PATH_A] = priv->pshare->OFDM_index[RF92CD_PATH_A]; + OFDM_index[RF92CD_PATH_B] = priv->pshare->OFDM_index[RF92CD_PATH_B]; + + DPK_DEBUG("original index 0x%x \n", priv->pshare->OFDM_index[0]); + + priv->pshare->bDPKworking = TRUE; + + //save global setting + //save BB default value + _PHY_SaveADDARegisters(priv, BB_REG, BB_backup, DP_BB_REG_NUM); + + //save MAC default value + _PHY_SaveMACRegisters(priv, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(priv, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //save path A default value + //save path A BB default value + _PHY_SaveADDARegisters(priv, BB_REG_A, BB_backup_A, DP_BB_REG_NUM_A); + + //save path B BB default value + if(is2T) + _PHY_SaveADDARegisters(priv, BB_REG_B, BB_backup_B, DP_BB_REG_NUM_B); + + //save pathA/B RF default value + for(path=0; pathInternalPA5G[path]) + //continue; + + if(path == RF92CD_PATH_B) + { + //BB pah A register setting:fix TRSW to TX;external LNA off + if(!bInternalPA) + { + PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x0f600f60); + PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, ~(BIT8|BIT9), 0x66e60230); + } + else + { + PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07600760); + PHY_SetBBReg(priv, rFPGA0_XA_RFInterfaceOE, ~(BIT8|BIT9), 0x66e60230); + } + PHY_SetBBReg(priv, rBndA, 0xF00000, 0x0a); + + //BB pah B register setting:fix TRSW to TX;external LNA off + if(is2T) + { + if(!bInternalPA) + { + PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x0f600f60); + PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, bMaskDWord, 0x061f0930); + } + else + { + PHY_SetBBReg(priv, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07600760); + PHY_SetBBReg(priv, rFPGA0_XB_RFInterfaceOE, bMaskDWord, 0x061f0130); + } + PHY_SetBBReg(priv, rBndB, 0xF00000, 0x0a); + } + } + + AP_curve_index = 1; + rx_index = 0x06; + bPlus3db = FALSE; + bDecreaseTxIndex = FALSE; + + if(path == RF92CD_PATH_A) + { + _PHY_PathADDAOn(priv, AFE_REG, TRUE, is2T); + } + else + { + _PHY_PathADDAOn(priv, AFE_REG, FALSE, is2T); + } + + if(path == RF92CD_PATH_B) + PHY_SetBBReg(priv, rFPGA1_DebugSelect, bMaskDWord, 0x00000303); + + //path A/B RF setting + //internal lopback off + if(path == RF92CD_PATH_A && !bInternalPA) + { + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x5007f); + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x6f1f9); + } + else if(path == RF92CD_PATH_B) + { + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x1000f); + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x60103); + } + + PHY_SetRFReg(priv, path, RF_RXRF_A3, bMask20Bits, 0xef456); + + //Path A/B to standby mode + PHY_SetRFReg(priv, path==RF92CD_PATH_A?RF92CD_PATH_B:RF92CD_PATH_A, + RF_AC, bMask20Bits, 0x10000); + + //set DPK PA bias table + index = priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40?0:1; + if(path == RF92CD_PATH_A) + { + for(i = 0; i < path_num; i++) + { + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, i, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[index][j]); + } + } + +Step1: + + DPK_DEBUG("==>AP curve select 0x%x bplus3db %d path%s!!\n", RF_AP_curve_select[AP_curve_index], bPlus3db, path==RF92CD_PATH_A?"A":"B"); + + //RF setting for AP curve selection + //default AP curve = 15 + PHY_SetRFReg(priv, path, RF_BS_PA_APSET_G1_G4, bMask20Bits, RF_AP_curve_select[AP_curve_index]); + + ////////////////////////////////////////////////// + // step 1: find RF TX/RX index + ///////////////////////////////////////////////// + //find RF TX index + //============================= + // PAGE_B for Path-A PM setting + //============================= + // open inner loopback @ b00[19]:od 0xb00 0x01097018 + if(bPlus3db) + BB_settings_temp = &(BB_settings_loop_tx_3db[0]); + else + BB_settings_temp = &(BB_settings_loop_tx[0]); + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); + + if(bDecreaseTxIndex) + tx_index = 0x19; + else + tx_index = 0x1f; + bDecreaseTxIndexWithRx = FALSE; + + //Set Tx GAC = 0x1f, than find Rx AGC + rx_index = _PHY_Find_Rx_Power_Index(priv, tx_index, rx_index, path, &bDecreaseTxIndexWithRx); + if(bDecreaseTxIndexWithRx) + { + if(bDecreaseTxIndex) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 + PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c + + for(i = 3; i < DP_RF_REG_NUM; i++) + PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); + + //set original DPK bias table + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); + continue; + } + else + { + bDecreaseTxIndex = TRUE; + goto Step1; + } + } + + //find 2dB loss point + //============================= + // PAGE_B for Path-A PM setting + //============================= + // open inner loopback @ b00[19]:od 0xb00 0x01097018 + if(bPlus3db) + BB_settings_temp = &(BB_settings_loop_tx_2_3db[0]); + else + BB_settings_temp = &(BB_settings_loop_tx_2[0]); + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); + + //RF setting + PHY_SetRFReg(priv, path, RF_AC, bMask20Bits, 0x52000 | tx_index | (rx_index << 5)); + + //----send one shot signal----// + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80080000); //0xb28, 0xb98 + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00080000); + + //get power + if(!_PHY_Find_Tx_Power_Index(priv, PA_power[path], path, bPlus3db, bDecreaseTxIndex, &tx_index)) + { + if(/*tx_index == 0x1f &&*/ !bPlus3db) + { + if(bDecreaseTxIndex) + { + if(tx_index < 0x11) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 + PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c + + for(i = 3; i < DP_RF_REG_NUM; i++) + PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); + + //set original DPK bias table + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); + + continue; + } + else + { + //RTPRINT(FINIT, INIT_IQK, ("==>Check pattern reliability path%s SUCCESS tx_index = 0x1b!!!!\n", path==RF90_PATH_A?"A":"B")); + } + } + else if(tx_index < 0x1a) + { + bDecreaseTxIndex = TRUE; + goto Step1; + } + else + { + bPlus3db = TRUE; + goto Step1; + } + } + else if(tx_index == 0x1f) + { + DPK_DEBUG("==>Check pattern reliability path%s FAIL!!!!\n", path==RF92CD_PATH_A?"A":"B"); + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 + PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c + + for(i = 3; i < DP_RF_REG_NUM; i++) + PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); + + //set original DPK bias table + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); + + continue; + } + + + } + else + { + DPK_DEBUG("==>Check pattern reliability path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); + } + + //find RF RX index + //============================= + // PAGE_B for Path-A PM setting + //============================= + // open inner loopback @ b00[19]:od 0xb00 0x01097018 + if(bPlus3db) + BB_settings_temp = &(BB_settings_loop_rx_3db[0]); + else + BB_settings_temp = &(BB_settings_loop_rx[0]); + + for(i = 0; i < 4; i++) + PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[i]); + for(; i < 12; i++) + PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[4]); + PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[5]); + for(; i < 29; i++) + PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[6]); + PHY_SetBBReg(priv, BB_REG_loop[path][i], bMaskDWord, BB_settings_temp[7]); + + rx_index = _PHY_Find_Rx_Power_Index(priv, tx_index, rx_index, path, &bDecreaseTxIndex); + + ////////////////////////////////////// + //2.measure PA model + ////////////////////////////////////// + //========================================= + //PAGE_B for Path-A PAS setting //========================================= + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + if(bPlus3db) + BB_settings_temp = &(BB_settings_loop_3db[0]); + else + BB_settings_temp = &(BB_settings_loop[0]); + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_temp, DP_BB_REG_NUM_loop); + + //LNA VDD to gnd + PHY_SetRFReg(priv,path, RF_AC, bMask20Bits, 0x52000 | tx_index | (rx_index << 5)); + + //----send one shot signal----// + // Path A + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80080000); //0xb28, 0xb98 + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00080000); + + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_T_METER, BIT17|BIT16, 0x03); + + _PHY_DPK_polling(priv); + + priv->pshare->ThermalValue_DPKstore = (unsigned char)PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_T_METER, 0xf800, 1); //0x42: RF Reg[15:11] 92D + + // read PA model and save to PA_model_A[32] + for(i = 0; i < DP_PA_MODEL_RUN_NUM; i++) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017018+i); //0xb00, 0xb70 + for(index = 0; index < DP_PA_MODEL_PER_RUN_NUM; index++) + { + PA_model_backup[path][i*4+index] = PHY_QueryBBReg(priv, offset[path][3]+index*4, bMaskDWord); //0xbdc, 0xbec + DPK_DEBUG("==>PA_model_backup index %d value 0x%x()\n", i*4+index, PA_model_backup[path][i*4+index]); + } + } + +#if 0 + //find appropriate AP curve + if(AP_curve_index != (DP_AP_CUREVE_SELECT_NUM-1)) + { + if(!_PHY_DPK_AP_curve_check(priv, PA_model_backup[path], DP_PA_MODEL_NUM)) + { + DPK_DEBUG("==>find appropriate AP curve 0x%x path%s FAIL!!!!\n", RF_AP_curve_select[AP_curve_index], path==RF92CD_PATH_A?"A":"B"); + AP_curve_index++; + if(AP_curve_index < DP_AP_CUREVE_SELECT_NUM) + goto Step1; + } + else + { + DPK_DEBUG("==>find appropriate AP curve path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); + } + } +#endif + + //check PA model + if(!_PHY_DPK_check(priv, PA_model_backup[path], DP_PA_MODEL_NUM)) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); // add in 2011-06-02 + PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c + + for(i = 3; i < DP_RF_REG_NUM; i++) + PHY_SetRFReg(priv, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + DPK_DEBUG("==>PA model path%s FAIL!!!!\n", path==RF92CD_PATH_A?"A":"B"); + priv->pshare->bDPKdone[path] = FALSE; + //set original DPK bias table + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); + + continue; + } + else + { + DPK_DEBUG("==>PA model path%s SUCCESS!!!!\n", path==RF92CD_PATH_A?"A":"B"); +// priv->pshare->bDPKdone[path] = TRUE; +// priv->pshare->bDPKstore = TRUE; + } + + ///////////////////////////////////////////////////////////////////////////////////////////////////// + // step 3: fill PA model to DP Calibration + ///////////////////////////////////////////////////////////////////////////////////////////////////// + //fill BB TX index for the DPK reference + DPK_DEBUG("==>fill PA model to DP Calibration\n"); + + if(path == RF92CD_PATH_A){ + for(index = 0; index < DP_PA_MODEL_RUN_NUM; index++){ + if(index != 3){ + PHY_SetBBReg(priv, 0xe00+index*4, bMaskDWord, 0x3c3c3c3c); + } else { + PHY_SetBBReg(priv, 0xe00+index*4, bMaskDWord, 0x03903c3c); + } + } + PHY_SetBBReg(priv, 0x86c, bMaskDWord, 0x3c3c3c3c); + }else if (path == RF92CD_PATH_B){ + for(index = 0; index < 4; index++) { + PHY_SetBBReg(priv, 0x830+index*4, bMaskDWord, 0x3c3c3c3c); + } + for(index = 0; index < 2; index++) { + PHY_SetBBReg(priv, 0x848+index*4, bMaskDWord, 0x3c3c3c3c); + } + for(index = 0; index < 2; index++) { + PHY_SetBBReg(priv, 0x868+index*4, bMaskDWord, 0x3c3c3c3c); + } + } + + // SRAM boundary setting + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); + + if(priv->pshare->phw->bNewTxGainTable) + PHY_SetBBReg(priv, offset[path][4], bMaskDWord, 0x0008421f); //0xbc0, 0xbc4 + else + PHY_SetBBReg(priv, offset[path][4], bMaskDWord, 0x0009ce7f); //0xbc0, 0xbc4 + + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_pa, DP_BB_REG_NUM_loop_pa); + + // fill PA model to page B1 registers + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0x400000); + for(index = 0; index < (DP_PA_MODEL_NUM/2); index++){ //path A = 0xb00, path B = 0xb60 + PHY_SetBBReg(priv, 0xb00+index*4+path*0x60, bMaskDWord, + (PA_model_backup[path][index*2+1] << 16) | PA_model_backup[path][index*2]); + } + PHY_SetBBReg(priv, 0xe28, 0xffffff00, 0); + + //one shot + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x80044499); //0xb28, 0xb98 + PHY_SetBBReg(priv, offset[path][1], bMaskDWord, 0x00044499); + + _PHY_DPK_polling(priv); + +#if 1 + ////////////////////////////////////////////////////// + // step 4: calculate gain loss caused by DP + ////////////////////////////////////////////////////// + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x0029701f); //0xb00, 0xb70 + tmpReg = PHY_QueryBBReg(priv, offset[path][5], bMaskDWord); //0xbe8, 0xbf8 + + power_I = (tmpReg >> 16); + if(power_I & BIT(15)) + power_I |= bMaskLWord; ////////ZZZZZZZZZZZZZZZZZZ + + power_Q = tmpReg & bMaskLWord; + if(power_Q & BIT(15)) + power_Q |= bMaskHWord; + + DPK_DEBUG("0x%x = 0x%x power_I = 0x%x power_Q = 0x%x\n", offset[path][5], tmpReg, power_I, power_Q); + + tmpReg = power_I*power_I + power_Q*power_Q; + + DPK_DEBUG("gain loss = 0x%x \n", tmpReg); + + if(tmpReg < 26090) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x01017098); //0xb00, 0xb70 + PHY_SetBBReg(priv, offset[path][8], bMaskDWord, 0x28080000); //0xb68, 0xb6c + + for(i = 3; i < DP_RF_REG_NUM; i++) + PHY_SetRFReg(priv, path, RF_REG[i], bMask20Bits, RF_backup[path][i]); + priv->pshare->bDPKdone[path] = FALSE; + //set original DPK bias table + for(j = 0; j < DP_PA_BIAS_NUM; j++) + PHY_SetRFReg(priv, path, RF_TXBIAS, bMask20Bits, RF_PA_BIAS[2][j]); + + continue; + } + else + { + priv->pshare->bDPKdone[path] = TRUE; + priv->pshare->bDPKstore = TRUE; + } + + for(i = 0; i < DP_GAIN_LOSS_BOUND_NUM; i++) + { +#if DP_gain_loss == 1 + if(tmpReg > gain_loss_bound[i]/* || i == (DP_GAIN_LOSS_BOUND_NUM -1)*/) +#else + if(tmpReg > gain_loss_bound[i] || i == (DP_GAIN_LOSS_BOUND_NUM -1)) +#endif + { +#if DP_gain_loss == 0 + if(i == 0) + break; + + index = OFDM_index[path] > i?OFDM_index[path]-i:0; + if(index < OFDM_min_index_internalPA) + index = OFDM_min_index_internalPA; + PHY_SetBBReg(priv, offset[path][6], bMaskDWord, OFDMSwingTable[index]); //0xc80, 0xc88 + DPK_DEBUG("original index 0x%x gain_loss minus index 0x%x\n", priv->pshare->OFDM_index[0], i); +#endif + break; + } + } + +#if DP_gain_loss == 1 + + DPK_DEBUG("gain_loss Compensated coefficient %d\n", gain_loss_coef[i]); + coef = gain_loss_coef[i]; + GainLossIndex = i; + priv->pshare->OFDM_min_index_internalPA_DPK[path] = GainLossIndex == 0?0:(GainLossIndex/2+GainLossIndex%2); + + //read DP LUT value from register + for(i = 0; i < DP_PA_MODEL_RUN_NUM; i++) + { + PHY_SetBBReg(priv, offset[path][2], bMaskDWord, 0x00297018+i); //0xb00, 0xb70 + for(index = 0; index < DP_PA_MODEL_PER_RUN_NUM; index++) + { + tmpReg = (i == 0 && index==0)?0x01000000:PHY_QueryBBReg(priv, offset[path][3]+index*4, bMaskDWord); //0xbdc, 0xbec + + gain_loss_backup[1][i*4+index] = (tmpReg >> 16); //I + if(gain_loss_backup[1][i*4+index] & BIT(15)) + gain_loss_backup[1][i*4+index] |= bMaskHWord; + + gain_loss_backup[0][i*4+index] = (tmpReg & bMaskLWord); //Q + if(gain_loss_backup[0][i*4+index] & BIT(15)) + gain_loss_backup[0][i*4+index] |= bMaskHWord; + DPK_DEBUG("==>DP LUT index %d value 0x%x() I = 0x%x, Q = 0x%x\n", i*4+index, tmpReg, gain_loss_backup[1][i*4+index], gain_loss_backup[0][i*4+index]); + + //gain * LUT + for(j = 0; j < 2; j++) + { + // RTPRINT(FINIT, INIT_IQK, ("==>0DP LUT sram %s index %d value %d()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); + + gain_loss_backup[j][i*4+index] = (gain_loss_backup[j][i*4+index] * coef) / (int)(512); + // RTPRINT(FINIT, INIT_IQK, ("==>1DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); + + gain_loss_backup[j][i*4+index] = gain_loss_backup[j][i*4+index] >= (int)(512)?(int)(511):gain_loss_backup[j][i*4+index] < (int)(-512)?(int)(-512):gain_loss_backup[j][i*4+index]; + // RTPRINT(FINIT, INIT_IQK, ("==>2DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); + + gain_loss_backup[j][i*4+index] = gain_loss_backup[j][i*4+index] >> 2; + // RTPRINT(FINIT, INIT_IQK, ("==>3DP LUT sram %s index %d value 0x%x()\n", j == 0?"Q":"I", i*4+index, gain_loss_backup[j][i*4+index])); + + } + tmpReg = ((gain_loss_backup[1][i*4+index] & bMaskByte0) << 8 ) | ((gain_loss_backup[0][i*4+index] & bMaskByte0)); + gain_loss_backup[0][i*4+index] = tmpReg & bMaskLWord; + DPK_DEBUG("==>DP LUT sram index %d value 0x%x()\n", i*4+index, tmpReg); + } + } + + //write DP LUT into sram + for(i = 0; i < DP_PA_MODEL_NUM; i++) + { + value32 = (path==RF92CD_PATH_A?((i%2 == 0)?0x01000000:0x02000000): + ((i%2 == 0)?0x04000000:0x08000000)) | + gain_loss_backup[0][(DP_PA_MODEL_NUM-1)-i] |( (i/2) << 16); + DPK_DEBUG("0xb2c value = 0x%x\n", value32); + PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); + } +// PHY_SetBBReg(priv, 0xb2c , bMaskDWord, 0x00000000); + +#endif + +#endif + + /////////////////////////////////////////////////////////////// + // step 5: Enable Digital Predistortion + /////////////////////////////////////////////////////////////// + // LUT from sram +#if DP_gain_loss == 1 + { + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_dp, DP_BB_REG_NUM_loop_pa); + + // pwsf boundary + PHY_SetBBReg(priv, offset[path][7], bMaskDWord, 0x000fffff); //0xb30, 0xba0 + + // write pwsf to sram + //find tx_index index value + SramIndex = 24; //restore default value + SramIndex -= GainLossIndex; + if(bPlus3db) + SramIndex += 3*4; + + SramIndex = SramIndex >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:(SramIndex<0?0:SramIndex); + + DPK_DEBUG("tx_index = 0x%x, sram value 0x%x gainloss index %d bPlus3db %d\n", tx_index, Sram_db_settings[SramIndex], GainLossIndex, bPlus3db); + + index = 0x1f - tx_index; + if(SramIndex >= index*4) + { + index = SramIndex - index*4; + index_repeat = -2; + SramIndex = -2; + } + else + { + index_repeat = index - SramIndex/4; + SramIndex %= 4; + index = 0; + } + + index = index >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:index; + if(index_repeat == 1) + index_1 = SramIndex; + else + index_1 = index < (DP_SRAM_NUM_db-1)?(index_repeat==-2?index+1*4:index):index; + + DPK_DEBUG("0x1f value = 0x%x, index 0x%x repeat %d SramIndex %d\n", Sram_db_settings[index], index, index_repeat, SramIndex); + + for(i = 0; i < DP_SRAM_NUM; i++) + { + value32 = (path==RF92CD_PATH_A?0x10000000:0x20000000) | (i << 16) | + (Sram_db_settings[index_1] << 8 )| Sram_db_settings[index]; + DPK_DEBUG("0xb2c value = 0x%x\n", value32); + + PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); + if(index_repeat >= 0) + index_repeat -= 2; + else if(index_repeat == -1) + index_repeat = -2; + + if((index < (DP_SRAM_NUM_db-1)-1)) + { + if(index_repeat == -2) + { + index+=2*4; + index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; + } + if(index_repeat == 0) + { + index = SramIndex; + index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; + } + else if(index_repeat == 1) + { + index_1 = SramIndex; + } + else if(index_repeat == -1) + { + index = index_1+1*4; + index_1 = index < (DP_SRAM_NUM_db-1)?index+1*4:index; + } + } + else + { + index = index_1 = (DP_SRAM_NUM_db-1); + } + + index = index < DP_SRAM_NUM_db?index:DP_SRAM_NUM_db-1; + index_1 = index_1 < DP_SRAM_NUM_db?index_1:DP_SRAM_NUM_db-1; + } + } +#else + if(!SkipStep5) + { + _PHY_SetADDARegisters(priv, BB_REG_loop[path], BB_settings_loop_dp, DP_BB_REG_NUM_loop_pa); + + // pwsf boundary + PHY_SetBBReg(priv, offset[path][7], bMaskDWord, 0x000fffff); //0xb30, 0xba0 + + // write pwsf to sram + //find RF0x1f index value + if(bPlus3db) + tx_index += 3; + +// tx_index = 0x21; + + index = 0x1f - tx_index; + if(index_for_zero_db >= index) + { + index = index_for_zero_db - index; + index_repeat = -2; + } + else + { + index_repeat = index - index_for_zero_db; + index = 0; + } + + index = index >= DP_SRAM_NUM_db?DP_SRAM_NUM_db-1:index; + index_1 = index < (DP_SRAM_NUM_db-1)?(index_repeat==-2?index+1:index):index; + + DPK_DEBUG("0x1f value = 0x%x, index 0x%x repeat %d\n", Sram_db_settings[index], index, index_repeat); + + for(i = 0; i < DP_SRAM_NUM; i++) + { + value32 = (path==RF92CD_PATH_A?0x10000000:0x20000000) | (i << 16) | + (Sram_db_settings[index_1] << 8 )| Sram_db_settings[index]; + DPK_DEBUG("0xb2c value = 0x%x\n", value32); + + PHY_SetBBReg(priv, 0xb2c , bMaskDWord, value32); + if(index_repeat >= 0) + index_repeat -= 2; + else if(index_repeat == -1) + index_repeat = -2; + + if((index < (DP_SRAM_NUM_db-1)-1)) + { + if(index_repeat == -2) + { + index += 2; + index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; + } + if(index_repeat == 0) + { + index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; + } + else if(index_repeat == -1) + { + index++; + index_1 = index < (DP_SRAM_NUM_db-1)?index+1:index; + } + } + else + { + index = index_1 = (DP_SRAM_NUM_db-1); + } + } + } +#endif + } + + //reload RF default value + for(path = 0; pathpshare->phw->InternalPA5G[RF92CD_PATH_B]) + { + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE1, bMask20Bits, 0x1000f); + PHY_SetRFReg(priv, RF92CD_PATH_A, RF_MODE2, bMask20Bits, 0x60101); + } + + //reload BB default value + for(index=0; indexpshare->bDPKworking = FALSE; + + DPK_DEBUG("<==_PHY_DigitalPredistortion()\n"); +} + +#endif +#endif + +#endif diff --git a/package/kernel/rtl8192cd/Hal8723BPwrSeq.c b/package/kernel/rtl8192cd/Hal8723BPwrSeq.c index 5136c515217..5097b8be7b8 100644 --- a/package/kernel/rtl8192cd/Hal8723BPwrSeq.c +++ b/package/kernel/rtl8192cd/Hal8723BPwrSeq.c @@ -1,96 +1,96 @@ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8821PwrSeq.c - -Abstract: - This file includes all kinds of Power Action event for RTL8723B and corresponding hardware configurtions which are released from HW SD. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-08 Roger Create. - ---*/ - -//#include "Mp_Precomp.h" //CONFIG_RTL_8723B_SUPPORT -#include "8192cd.h" -#include "HalPwrSeqCmd.h" -#include "Hal8723BPwrSeq.h" - -/* - drivers should parse below arrays and do the corresponding actions -*/ -//3 Power on Array -WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_CARDEMU_TO_ACT - RTL8723B_TRANS_END -}; - -//3Radio off GPIO Array -WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_ACT_TO_CARDEMU - RTL8723B_TRANS_END -}; - -//3Card Disable Array -WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_ACT_TO_CARDEMU - RTL8723B_TRANS_CARDEMU_TO_CARDDIS - RTL8723B_TRANS_END -}; - -//3 Card Enable Array -WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_CARDDIS_TO_CARDEMU - RTL8723B_TRANS_CARDEMU_TO_ACT - RTL8723B_TRANS_END -}; - -//3Suspend Array -WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_ACT_TO_CARDEMU - RTL8723B_TRANS_CARDEMU_TO_SUS - RTL8723B_TRANS_END -}; - -//3 Resume Array -WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_SUS_TO_CARDEMU - RTL8723B_TRANS_CARDEMU_TO_ACT - RTL8723B_TRANS_END -}; - - - -//3HWPDN Array -WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - RTL8723B_TRANS_ACT_TO_CARDEMU - RTL8723B_TRANS_CARDEMU_TO_PDN - RTL8723B_TRANS_END -}; - -//3 Enter LPS -WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - //FW behavior - RTL8723B_TRANS_ACT_TO_LPS - RTL8723B_TRANS_END -}; - -//3 Leave LPS -WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= -{ - //FW behavior - RTL8723B_TRANS_LPS_TO_ACT - RTL8723B_TRANS_END + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8821PwrSeq.c + +Abstract: + This file includes all kinds of Power Action event for RTL8723B and corresponding hardware configurtions which are released from HW SD. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-08 Roger Create. + +--*/ + +//#include "Mp_Precomp.h" //CONFIG_RTL_8723B_SUPPORT +#include "8192cd.h" +#include "HalPwrSeqCmd.h" +#include "Hal8723BPwrSeq.h" + +/* + drivers should parse below arrays and do the corresponding actions +*/ +//3 Power on Array +WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_CARDEMU_TO_ACT + RTL8723B_TRANS_END +}; + +//3Radio off GPIO Array +WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_ACT_TO_CARDEMU + RTL8723B_TRANS_END +}; + +//3Card Disable Array +WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_ACT_TO_CARDEMU + RTL8723B_TRANS_CARDEMU_TO_CARDDIS + RTL8723B_TRANS_END +}; + +//3 Card Enable Array +WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_CARDDIS_TO_CARDEMU + RTL8723B_TRANS_CARDEMU_TO_ACT + RTL8723B_TRANS_END +}; + +//3Suspend Array +WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_ACT_TO_CARDEMU + RTL8723B_TRANS_CARDEMU_TO_SUS + RTL8723B_TRANS_END +}; + +//3 Resume Array +WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_SUS_TO_CARDEMU + RTL8723B_TRANS_CARDEMU_TO_ACT + RTL8723B_TRANS_END +}; + + + +//3HWPDN Array +WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + RTL8723B_TRANS_ACT_TO_CARDEMU + RTL8723B_TRANS_CARDEMU_TO_PDN + RTL8723B_TRANS_END +}; + +//3 Enter LPS +WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + //FW behavior + RTL8723B_TRANS_ACT_TO_LPS + RTL8723B_TRANS_END +}; + +//3 Leave LPS +WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]= +{ + //FW behavior + RTL8723B_TRANS_LPS_TO_ACT + RTL8723B_TRANS_END }; \ No newline at end of file diff --git a/package/kernel/rtl8192cd/Hal8723BPwrSeq.h b/package/kernel/rtl8192cd/Hal8723BPwrSeq.h index 0eea2c6e959..f570e384ca2 100644 --- a/package/kernel/rtl8192cd/Hal8723BPwrSeq.h +++ b/package/kernel/rtl8192cd/Hal8723BPwrSeq.h @@ -1,183 +1,183 @@ -#ifndef REALTEK_POWER_SEQUENCE_8723B -#define REALTEK_POWER_SEQUENCE_8723B - - -/* - Check document WM-20150115-JackieLau-RTL8723B_Power_Architecture v10.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 25 -#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8723B_TRANS_END_STEPS 1 - - -#define RTL8723B_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ - {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \ - {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ - {0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* RF HW Power down disabled*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ - - -#define RTL8723B_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ - - -#define RTL8723B_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723B_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8723B_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8723B_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8723B_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8723B_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8723B_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; - -#endif +#ifndef REALTEK_POWER_SEQUENCE_8723B +#define REALTEK_POWER_SEQUENCE_8723B + + +/* + Check document WM-20150115-JackieLau-RTL8723B_Power_Architecture v10.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 25 +#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8723B_TRANS_END_STEPS 1 + + +#define RTL8723B_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ + {0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* RF HW Power down disabled*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ + + +#define RTL8723B_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ + + +#define RTL8723B_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8723B_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8723B_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8723B_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8723B_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8723B_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; + +#endif diff --git a/package/kernel/rtl8192cd/Hal8812PwrSeq.c b/package/kernel/rtl8192cd/Hal8812PwrSeq.c old mode 100755 new mode 100644 index 23ae37b4773..4a7818c0d12 --- a/package/kernel/rtl8192cd/Hal8812PwrSeq.c +++ b/package/kernel/rtl8192cd/Hal8812PwrSeq.c @@ -1,100 +1,100 @@ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8812PwrSeq.c - -Abstract: - This file includes all kinds of Power Action event for RTL8812 and corresponding hardware configurtions which are released from HW SD. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-10-26 William Create. - ---*/ - - -#ifdef CONFIG_RTL_8812_SUPPORT - -#include "HalPwrSeqCmd.h" -#include "Hal8812PwrSeq.h" - -/* - drivers should parse below arrays and do the corresponding actions -*/ -//3 Power on Array -WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_CARDEMU_TO_ACT - RTL8812_TRANS_END -}; - -//3Radio off GPIO Array -WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_ACT_TO_CARDEMU - RTL8812_TRANS_END -}; - -//3Card Disable Array -WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_ACT_TO_CARDEMU - RTL8812_TRANS_CARDEMU_TO_CARDDIS - RTL8812_TRANS_END -}; - -//3 Card Enable Array -WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_CARDDIS_TO_CARDEMU - RTL8812_TRANS_CARDEMU_TO_ACT - RTL8812_TRANS_END -}; - -//3Suspend Array -WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_ACT_TO_CARDEMU - RTL8812_TRANS_CARDEMU_TO_SUS - RTL8812_TRANS_END -}; - -//3 Resume Array -WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_SUS_TO_CARDEMU - RTL8812_TRANS_CARDEMU_TO_ACT - RTL8812_TRANS_END -}; - - - -//3HWPDN Array -WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= -{ - RTL8812_TRANS_ACT_TO_CARDEMU - RTL8812_TRANS_CARDEMU_TO_PDN - RTL8812_TRANS_END -}; - -//3 Enter LPS -WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]= -{ - //FW behavior - RTL8812_TRANS_ACT_TO_LPS - RTL8812_TRANS_END -}; - -//3 Leave LPS -WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]= -{ - //FW behavior - RTL8812_TRANS_LPS_TO_ACT - RTL8812_TRANS_END -}; - -#endif //CONFIG_RTL_8812_SUPPORT - + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8812PwrSeq.c + +Abstract: + This file includes all kinds of Power Action event for RTL8812 and corresponding hardware configurtions which are released from HW SD. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-10-26 William Create. + +--*/ + + +#ifdef CONFIG_RTL_8812_SUPPORT + +#include "HalPwrSeqCmd.h" +#include "Hal8812PwrSeq.h" + +/* + drivers should parse below arrays and do the corresponding actions +*/ +//3 Power on Array +WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_CARDEMU_TO_ACT + RTL8812_TRANS_END +}; + +//3Radio off GPIO Array +WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_ACT_TO_CARDEMU + RTL8812_TRANS_END +}; + +//3Card Disable Array +WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_ACT_TO_CARDEMU + RTL8812_TRANS_CARDEMU_TO_CARDDIS + RTL8812_TRANS_END +}; + +//3 Card Enable Array +WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_CARDDIS_TO_CARDEMU + RTL8812_TRANS_CARDEMU_TO_ACT + RTL8812_TRANS_END +}; + +//3Suspend Array +WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_ACT_TO_CARDEMU + RTL8812_TRANS_CARDEMU_TO_SUS + RTL8812_TRANS_END +}; + +//3 Resume Array +WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_SUS_TO_CARDEMU + RTL8812_TRANS_CARDEMU_TO_ACT + RTL8812_TRANS_END +}; + + + +//3HWPDN Array +WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]= +{ + RTL8812_TRANS_ACT_TO_CARDEMU + RTL8812_TRANS_CARDEMU_TO_PDN + RTL8812_TRANS_END +}; + +//3 Enter LPS +WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]= +{ + //FW behavior + RTL8812_TRANS_ACT_TO_LPS + RTL8812_TRANS_END +}; + +//3 Leave LPS +WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]= +{ + //FW behavior + RTL8812_TRANS_LPS_TO_ACT + RTL8812_TRANS_END +}; + +#endif //CONFIG_RTL_8812_SUPPORT + diff --git a/package/kernel/rtl8192cd/Hal8812PwrSeq.h b/package/kernel/rtl8192cd/Hal8812PwrSeq.h old mode 100755 new mode 100644 index 632ee439644..2ef4dc8793a --- a/package/kernel/rtl8192cd/Hal8812PwrSeq.h +++ b/package/kernel/rtl8192cd/Hal8812PwrSeq.h @@ -1,199 +1,199 @@ -//#ifndef REALTEK_POWER_SEQUENCE_8812 -//#define REALTEK_POWER_SEQUENCE_8812 - -#ifdef CONFIG_RTL_8812_SUPPORT - -#ifdef BIT -#undef BIT -#endif - -#define BIT(x) (1 << (x)) - -/* - Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15 -#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8812_TRANS_END_STEPS 1 - - -#define RTL8812_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0},/**/ \ - {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \ - {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /* 0x28[3] Choose the type of buffer after xosc: nand*/ - -#define RTL8812_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset*/ \ - /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \ - /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ - /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, // 0x02[1:0] = 0 reset BB */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8812_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT(7)},/*0x14[7] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT(0)},/* 0x15[0] =1 trun on ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT(4)},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/ - -#define RTL8812_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ - -#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0}, //0x194[0]=0 , disable 32K clock*/ \ - /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0}, /*0x03[2] = 0, reset 8051*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT(7)},/*0x14[7] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT(0)},/* 0x15[0] =1 trun on ZCD */ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT(4)},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \ - {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /*0x04[11] = 2b'01 enable WL suspend*/ - -#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \ - {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /* 0x28[3] Choose the type of buffer after xosc: schmitt trigger*/ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/*0x12[0] = 1 force PWM mode */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x03[2] = 1, enable 8051*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8812_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ - -#define RTL8812_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ - -#define RTL8812_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ - - -#define RTL8812_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8812_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]; - -#endif //CONFIG_RTL_8812_SUPPORT - +//#ifndef REALTEK_POWER_SEQUENCE_8812 +//#define REALTEK_POWER_SEQUENCE_8812 + +#ifdef CONFIG_RTL_8812_SUPPORT + +#ifdef BIT +#undef BIT +#endif + +#define BIT(x) (1 << (x)) + +/* + Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15 +#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8812_TRANS_END_STEPS 1 + + +#define RTL8812_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0},/**/ \ + {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \ + {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /* 0x28[3] Choose the type of buffer after xosc: nand*/ + +#define RTL8812_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ + {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset*/ \ + /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \ + /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ + /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, // 0x02[1:0] = 0 reset BB */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + +#define RTL8812_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\ + {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\ + {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ + {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ + {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ + {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT(7)},/*0x14[7] = 1 turn on ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT(0)},/* 0x15[0] =1 trun on ZCD */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT(4)},/*0x23[4] = 1 hpon LDO sleep mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/ + +#define RTL8812_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ + {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ + {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ + +#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0}, //0x194[0]=0 , disable 32K clock*/ \ + /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0}, /*0x03[2] = 0, reset 8051*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \ + {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\ + {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\ + {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ + {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ + {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ + {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT(7)},/*0x14[7] = 1 turn on ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT(0)},/* 0x15[0] =1 trun on ZCD */ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT(4)},/*0x23[4] = 1 hpon LDO sleep mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \ + {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /*0x04[11] = 2b'01 enable WL suspend*/ + +#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \ + {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), BIT(3)}, /* 0x28[3] Choose the type of buffer after xosc: schmitt trigger*/ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/*0x12[0] = 1 force PWM mode */ \ + {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ + {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3), 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x03[2] = 1, enable 8051*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8812_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ + +#define RTL8812_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ + +#define RTL8812_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ + {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ + + +#define RTL8812_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8812_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]; + +#endif //CONFIG_RTL_8812_SUPPORT + diff --git a/package/kernel/rtl8192cd/Hal8821APwrSeq.c b/package/kernel/rtl8192cd/Hal8821APwrSeq.c old mode 100755 new mode 100644 index ab9429b654b..9039889df85 --- a/package/kernel/rtl8192cd/Hal8821APwrSeq.c +++ b/package/kernel/rtl8192cd/Hal8821APwrSeq.c @@ -1,97 +1,97 @@ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8821PwrSeq.c - -Abstract: - This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-08 Roger Create. - ---*/ - -#ifdef CONFIG_RTL_92E_SUPPORT -//#include "Mp_Precomp.h" -#include "HalPwrSeqCmd.h" -#include "Hal8821APwrSeq.h" - -/* - drivers should parse below arrays and do the corresponding actions -*/ -//3 Power on Array -WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_CARDEMU_TO_ACT - RTL8821A_TRANS_END -}; - -//3Radio off GPIO Array -WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_ACT_TO_CARDEMU - RTL8821A_TRANS_END -}; - -//3Card Disable Array -WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_ACT_TO_CARDEMU - RTL8821A_TRANS_CARDEMU_TO_CARDDIS - RTL8821A_TRANS_END -}; - -//3 Card Enable Array -WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_CARDDIS_TO_CARDEMU - RTL8821A_TRANS_CARDEMU_TO_ACT - RTL8821A_TRANS_END -}; - -//3Suspend Array -WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_ACT_TO_CARDEMU - RTL8821A_TRANS_CARDEMU_TO_SUS - RTL8821A_TRANS_END -}; - -//3 Resume Array -WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_SUS_TO_CARDEMU - RTL8821A_TRANS_CARDEMU_TO_ACT - RTL8821A_TRANS_END -}; - - - -//3HWPDN Array -WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - RTL8821A_TRANS_ACT_TO_CARDEMU - RTL8821A_TRANS_CARDEMU_TO_PDN - RTL8821A_TRANS_END -}; - -//3 Enter LPS -WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - //FW behavior - RTL8821A_TRANS_ACT_TO_LPS - RTL8821A_TRANS_END -}; - -//3 Leave LPS -WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]= -{ - //FW behavior - RTL8821A_TRANS_LPS_TO_ACT - RTL8821A_TRANS_END -}; -#endif + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8821PwrSeq.c + +Abstract: + This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-08 Roger Create. + +--*/ + +#ifdef CONFIG_RTL_92E_SUPPORT +//#include "Mp_Precomp.h" +#include "HalPwrSeqCmd.h" +#include "Hal8821APwrSeq.h" + +/* + drivers should parse below arrays and do the corresponding actions +*/ +//3 Power on Array +WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_CARDEMU_TO_ACT + RTL8821A_TRANS_END +}; + +//3Radio off GPIO Array +WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_ACT_TO_CARDEMU + RTL8821A_TRANS_END +}; + +//3Card Disable Array +WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_ACT_TO_CARDEMU + RTL8821A_TRANS_CARDEMU_TO_CARDDIS + RTL8821A_TRANS_END +}; + +//3 Card Enable Array +WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_CARDDIS_TO_CARDEMU + RTL8821A_TRANS_CARDEMU_TO_ACT + RTL8821A_TRANS_END +}; + +//3Suspend Array +WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_ACT_TO_CARDEMU + RTL8821A_TRANS_CARDEMU_TO_SUS + RTL8821A_TRANS_END +}; + +//3 Resume Array +WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_SUS_TO_CARDEMU + RTL8821A_TRANS_CARDEMU_TO_ACT + RTL8821A_TRANS_END +}; + + + +//3HWPDN Array +WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + RTL8821A_TRANS_ACT_TO_CARDEMU + RTL8821A_TRANS_CARDEMU_TO_PDN + RTL8821A_TRANS_END +}; + +//3 Enter LPS +WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + //FW behavior + RTL8821A_TRANS_ACT_TO_LPS + RTL8821A_TRANS_END +}; + +//3 Leave LPS +WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]= +{ + //FW behavior + RTL8821A_TRANS_LPS_TO_ACT + RTL8821A_TRANS_END +}; +#endif diff --git a/package/kernel/rtl8192cd/Hal8821APwrSeq.h b/package/kernel/rtl8192cd/Hal8821APwrSeq.h old mode 100755 new mode 100644 index a4433cc0ed3..bae450a9707 --- a/package/kernel/rtl8192cd/Hal8821APwrSeq.h +++ b/package/kernel/rtl8192cd/Hal8821APwrSeq.h @@ -1,162 +1,162 @@ -//#ifndef REALTEK_POWER_SEQUENCE_8821 -//#define REALTEK_POWER_SEQUENCE_8821 - -#ifdef CONFIG_RTL_92E_SUPPORT - -#ifdef CONFIG_WLAN_HAL -#include "WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h" - -#endif - - -#ifdef BIT -#undef BIT -#endif -#define BIT(x) (1 << (x)) - -/* - Check document WM-20110607-Paul-RTL8821A_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 15 -#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8821A_TRANS_END_STEPS 1 - - -#define RTL8821A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0},/**/ \ - - -#define RTL8821A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - -#define RTL8821A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4)|BIT(3), (BIT(4)|BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8821A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8821A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ - -#define RTL8821A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ - -#define RTL8821A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ - - -#define RTL8821A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8821A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS+RTL8821A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]; - -#endif +//#ifndef REALTEK_POWER_SEQUENCE_8821 +//#define REALTEK_POWER_SEQUENCE_8821 + +#ifdef CONFIG_RTL_92E_SUPPORT + +#ifdef CONFIG_WLAN_HAL +#include "WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h" + +#endif + + +#ifdef BIT +#undef BIT +#endif +#define BIT(x) (1 << (x)) + +/* + Check document WM-20110607-Paul-RTL8821A_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 15 +#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8821A_TRANS_END_STEPS 1 + + +#define RTL8821A_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0},/**/ \ + + +#define RTL8821A_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + +#define RTL8821A_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4)|BIT(3), (BIT(4)|BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + +#define RTL8821A_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + +#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8821A_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ + +#define RTL8821A_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ + +#define RTL8821A_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ + + +#define RTL8821A_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8821A_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS+RTL8821A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS+RTL8821A_TRANS_END_STEPS]; + +#endif diff --git a/package/kernel/rtl8192cd/HalDMOutSrc.c b/package/kernel/rtl8192cd/HalDMOutSrc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/HalPwrSeqCmd.c b/package/kernel/rtl8192cd/HalPwrSeqCmd.c index 466c0702590..24abec55234 100644 --- a/package/kernel/rtl8192cd/HalPwrSeqCmd.c +++ b/package/kernel/rtl8192cd/HalPwrSeqCmd.c @@ -1,175 +1,175 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalPwrSeqCmd.c - -Abstract: - Implement HW Power sequence configuration CMD handling routine for Realtek devices. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-07-07 Roger Create. - ---*/ -#ifdef __ECOS -#include -#include -#include -#include -#endif - - -/* -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "mp_precomp.h" -#else -#include "../mp_precomp.h" -#endif -*/ -#ifdef __KERNEL__ -#include -#endif -#include "8192cd.h" -#include "8192cd_debug.h" -#include "8192cd_headers.h" -#include "8192cd_util.h" - -#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_8723B_SUPPORT) - -#define TRUE 1 -#define FALSE 0 - -// -// Description: -// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. -// -// Assumption: -// We should follow specific format which was released from HW SD. -// -// 2011.07.07, added by Roger. -// -unsigned int HalPwrSeqCmdParsing(struct rtl8192cd_priv *priv, unsigned char CutVersion, unsigned char FabVersion, - unsigned char InterfaceType, WLAN_PWR_CFG PwrSeqCmd[]) -{ - - WLAN_PWR_CFG PwrCfgCmd = {0}; - unsigned int bPollingBit = FALSE; - unsigned int AryIdx=0; - unsigned char value = 0; - unsigned int offset = 0; - unsigned int pollingCount = 0; // polling autoload done. - unsigned int maxPollingCnt = 5000; - unsigned int round = 0; - - do { - PwrCfgCmd=PwrSeqCmd[AryIdx]; - - DEBUG_INFO("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n", - __FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd), - GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd), - GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd)); - - //2 Only Handle the command whose FAB, CUT, and Interface are matched - if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&& - (GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&& - (GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) { - switch(GET_PWR_CFG_CMD(PwrCfgCmd)) - { - case PWR_CMD_READ: - DEBUG_INFO("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__); - break; - - case PWR_CMD_WRITE: - DEBUG_INFO("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__); - offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); - -#ifdef CONFIG_SDIO_HCI - // - // We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface - // 2011.07.07. - // - if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) - { - // Read Back SDIO Local value - value = SdioLocalCmd52Read1Byte(priv, offset); - - value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); - value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); - - // Write Back SDIO Local value - SdioLocalCmd52Write1Byte(priv, offset, value); - } - else -#endif - { - //Read the value from system register - value = RTL_R8(offset); - value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd))); - value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)); - - //Write the value back to sytem register - RTL_W8(offset, value); - } - break; - - case PWR_CMD_POLLING: - DEBUG_INFO("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__); - bPollingBit = FALSE; - offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); - - do { -#ifdef CONFIG_SDIO_HCI - if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) - value = SdioLocalCmd52Read1Byte(priv, offset); - else -#endif - value = RTL_R8(offset); - value=value&GET_PWR_CFG_MASK(PwrCfgCmd); - if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd))) - bPollingBit=TRUE; - else - delay_us(10); - - if(pollingCount++ > maxPollingCnt){ - DEBUG_WARN("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset); - return FALSE; - } - }while(!bPollingBit); - - break; - - case PWR_CMD_DELAY: - DEBUG_INFO("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__); - if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) - delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)); - else - delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000); - break; - - case PWR_CMD_END: - // When this command is parsed, end the process - DEBUG_INFO("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__); - return TRUE; - break; - - default: - DEBUG_ERR("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__); - break; - } - - } - - AryIdx++;//Add Array Index - - if (++round > 10000) { - panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); - break; - } - }while(1); - - return TRUE; -} -#endif - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalPwrSeqCmd.c + +Abstract: + Implement HW Power sequence configuration CMD handling routine for Realtek devices. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-07-07 Roger Create. + +--*/ +#ifdef __ECOS +#include +#include +#include +#include +#endif + + +/* +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "mp_precomp.h" +#else +#include "../mp_precomp.h" +#endif +*/ +#ifdef __KERNEL__ +#include +#endif +#include "8192cd.h" +#include "8192cd_debug.h" +#include "8192cd_headers.h" +#include "8192cd_util.h" + +#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_8723B_SUPPORT) + +#define TRUE 1 +#define FALSE 0 + +// +// Description: +// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. +// +// Assumption: +// We should follow specific format which was released from HW SD. +// +// 2011.07.07, added by Roger. +// +unsigned int HalPwrSeqCmdParsing(struct rtl8192cd_priv *priv, unsigned char CutVersion, unsigned char FabVersion, + unsigned char InterfaceType, WLAN_PWR_CFG PwrSeqCmd[]) +{ + + WLAN_PWR_CFG PwrCfgCmd = {0}; + unsigned int bPollingBit = FALSE; + unsigned int AryIdx=0; + unsigned char value = 0; + unsigned int offset = 0; + unsigned int pollingCount = 0; // polling autoload done. + unsigned int maxPollingCnt = 5000; + unsigned int round = 0; + + do { + PwrCfgCmd=PwrSeqCmd[AryIdx]; + + DEBUG_INFO("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n", + __FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd), + GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd), + GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd)); + + //2 Only Handle the command whose FAB, CUT, and Interface are matched + if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&& + (GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&& + (GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) { + switch(GET_PWR_CFG_CMD(PwrCfgCmd)) + { + case PWR_CMD_READ: + DEBUG_INFO("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__); + break; + + case PWR_CMD_WRITE: + DEBUG_INFO("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__); + offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); + +#ifdef CONFIG_SDIO_HCI + // + // We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface + // 2011.07.07. + // + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + { + // Read Back SDIO Local value + value = SdioLocalCmd52Read1Byte(priv, offset); + + value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); + value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); + + // Write Back SDIO Local value + SdioLocalCmd52Write1Byte(priv, offset, value); + } + else +#endif + { + //Read the value from system register + value = RTL_R8(offset); + value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd))); + value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)); + + //Write the value back to sytem register + RTL_W8(offset, value); + } + break; + + case PWR_CMD_POLLING: + DEBUG_INFO("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__); + bPollingBit = FALSE; + offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); + + do { +#ifdef CONFIG_SDIO_HCI + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + value = SdioLocalCmd52Read1Byte(priv, offset); + else +#endif + value = RTL_R8(offset); + value=value&GET_PWR_CFG_MASK(PwrCfgCmd); + if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd))) + bPollingBit=TRUE; + else + delay_us(10); + + if(pollingCount++ > maxPollingCnt){ + DEBUG_WARN("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset); + return FALSE; + } + }while(!bPollingBit); + + break; + + case PWR_CMD_DELAY: + DEBUG_INFO("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__); + if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) + delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)); + else + delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000); + break; + + case PWR_CMD_END: + // When this command is parsed, end the process + DEBUG_INFO("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__); + return TRUE; + break; + + default: + DEBUG_ERR("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__); + break; + } + + } + + AryIdx++;//Add Array Index + + if (++round > 10000) { + panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); + break; + } + }while(1); + + return TRUE; +} +#endif + diff --git a/package/kernel/rtl8192cd/HalPwrSeqCmd.h b/package/kernel/rtl8192cd/HalPwrSeqCmd.h index 9341915b125..0d03a7dfc5d 100644 --- a/package/kernel/rtl8192cd/HalPwrSeqCmd.h +++ b/package/kernel/rtl8192cd/HalPwrSeqCmd.h @@ -1,109 +1,109 @@ -#ifndef __HAL_PWRSEQCMD_H__ -#define __HAL_PWRSEQCMD_H__ - - -//#if defined(CONFIG_RTL_88E_SUPPORT)|| defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_92E_SUPPORT) - - /*---------------------------------------------*/ -//3 The value of cmd: 4 bits -/*---------------------------------------------*/ -#define PWR_CMD_READ 0x00 - // offset: the read register offset - // msk: the mask of the read value - // value: N/A, left by 0 - // note: dirver shall implement this function by read & msk -#define PWR_CMD_WRITE 0x01 - // offset: the read register offset - // msk: the mask of the write bits - // value: write value - // note: driver shall implement this cmd by read & msk after write -#define PWR_CMD_POLLING 0x02 - // offset: the read register offset - // msk: the mask of the polled value - // value: the value to be polled, masked by the msd field. - // note: driver shall implement this cmd by - // do{ - // if( (Read(offset) & msk) == (value & msk) ) - // break; - // } while(not timeout); -#define PWR_CMD_DELAY 0x03 - // offset: the value to delay - // msk: N/A - // value: the unit of delay, 0: us, 1: ms -#define PWR_CMD_END 0x04 - // offset: N/A - // msk: N/A - // value: N/A - -/*---------------------------------------------*/ -//3 The value of base: 4 bits -/*---------------------------------------------*/ - // define the base address of each block -#define PWR_BASEADDR_MAC 0x00 -#define PWR_BASEADDR_USB 0x01 -#define PWR_BASEADDR_PCIE 0x02 -#define PWR_BASEADDR_SDIO 0x03 - -/*---------------------------------------------*/ -//3 The value of interface_msk: 4 bits -/*---------------------------------------------*/ -#define PWR_INTF_SDIO_MSK BIT(0) -#define PWR_INTF_USB_MSK BIT(1) -#define PWR_INTF_PCI_MSK BIT(2) -#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -//3 The value of fab_msk: 4 bits -/*---------------------------------------------*/ -#define PWR_FAB_TSMC_MSK BIT(0) -#define PWR_FAB_UMC_MSK BIT(1) -#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -//3The value of cut_msk: 8 bits -/*---------------------------------------------*/ -#define PWR_CUT_TESTCHIP_MSK BIT(0) -#define PWR_CUT_A_MSK BIT(1) -#define PWR_CUT_B_MSK BIT(2) -#define PWR_CUT_C_MSK BIT(3) -#define PWR_CUT_D_MSK BIT(4) -#define PWR_CUT_E_MSK BIT(5) -#define PWR_CUT_F_MSK BIT(6) -#define PWR_CUT_G_MSK BIT(7) -#define PWR_CUT_ALL_MSK 0xFF - - -typedef enum _PWRSEQ_CMD_DELAY_UNIT_ -{ - PWRSEQ_DELAY_US, - PWRSEQ_DELAY_MS, -} PWRSEQ_DELAY_UNIT; - -typedef struct _WL_PWR_CFG_ -{ - unsigned short offset; - unsigned char cut_msk; - unsigned char fab_msk:4; - unsigned char interface_msk:4; - unsigned char base:4; - unsigned char cmd:4; - unsigned char msk; - unsigned char value; -} WLAN_PWR_CFG, *PWLAN_PWR_CFG; - - -#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset -#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk -#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk -#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk -#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base -#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd -#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk -#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value - -//#endif - - - -#endif //__HAL_PWRSEQCMD_H__ - +#ifndef __HAL_PWRSEQCMD_H__ +#define __HAL_PWRSEQCMD_H__ + + +//#if defined(CONFIG_RTL_88E_SUPPORT)|| defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_92E_SUPPORT) + + /*---------------------------------------------*/ +//3 The value of cmd: 4 bits +/*---------------------------------------------*/ +#define PWR_CMD_READ 0x00 + // offset: the read register offset + // msk: the mask of the read value + // value: N/A, left by 0 + // note: dirver shall implement this function by read & msk +#define PWR_CMD_WRITE 0x01 + // offset: the read register offset + // msk: the mask of the write bits + // value: write value + // note: driver shall implement this cmd by read & msk after write +#define PWR_CMD_POLLING 0x02 + // offset: the read register offset + // msk: the mask of the polled value + // value: the value to be polled, masked by the msd field. + // note: driver shall implement this cmd by + // do{ + // if( (Read(offset) & msk) == (value & msk) ) + // break; + // } while(not timeout); +#define PWR_CMD_DELAY 0x03 + // offset: the value to delay + // msk: N/A + // value: the unit of delay, 0: us, 1: ms +#define PWR_CMD_END 0x04 + // offset: N/A + // msk: N/A + // value: N/A + +/*---------------------------------------------*/ +//3 The value of base: 4 bits +/*---------------------------------------------*/ + // define the base address of each block +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +//3 The value of interface_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of fab_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3The value of cut_msk: 8 bits +/*---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ +{ + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ +{ + unsigned short offset; + unsigned char cut_msk; + unsigned char fab_msk:4; + unsigned char interface_msk:4; + unsigned char base:4; + unsigned char cmd:4; + unsigned char msk; + unsigned char value; +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + +//#endif + + + +#endif //__HAL_PWRSEQCMD_H__ + diff --git a/package/kernel/rtl8192cd/Makefile.ecos b/package/kernel/rtl8192cd/Makefile.ecos old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/RateAdaptive.c b/package/kernel/rtl8192cd/RateAdaptive.c index 0fd68dcce4a..fa0b5dce49d 100644 --- a/package/kernel/rtl8192cd/RateAdaptive.c +++ b/package/kernel/rtl8192cd/RateAdaptive.c @@ -1,581 +1,581 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - RateAdaptive.c - -Abstract: - Implement Rate Adaptive functions for common operations. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-12 Page Create. - ---*/ -#ifdef __ECOS -#include -#endif -#include "8192cd_cfg.h" -#ifdef CONFIG_RTL_88E_SUPPORT - - -#ifdef TXREPORT -#include "8192cd.h" -#include "8192cd_headers.h" -#include "8192cd_hw.h" -#include "8192cd_util.h" - -/* - * RateAdaptive.h - Start - */ -#define PERENTRY 23 -#define RETRYSIZE 5 -#define RATESIZE 28 -/* - * RateAdaptive.h - End - */ - - -static unsigned char RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 - {6,5,4,3,0,4},//86 , idx=1 - {6,5,4,2,0,4},//81 , idx=2 - {8,7,6,4,0,6},//75 , idx=3 - {10,9,8,6,0,8},//71 , idx=4 - {10,9,8,4,0,8},//66 , idx=5 - {10,9,8,2,0,8},//62 , idx=6 - {10,9,8,0,0,8},//59 , idx=7 - {18,17,16,8,0,16},//53 , idx=8 - {26,25,24,16,0,24},//50 , idx=9 - {34,33,32,24,0,32},//47 , idx=0x0a - //{34,33,32,16,0,32},//43 , idx=0x0b - //{34,33,32,8,0,32},//40 , idx=0x0c - //{34,33,28,8,0,32},//37 , idx=0x0d - //{34,33,20,8,0,32},//32 , idx=0x0e - //{34,32,24,8,0,32},//26 , idx=0x0f - //{49,48,32,16,0,48},//20 , idx=0x10 - //{49,48,24,0,0,48},//17 , idx=0x11 - //{49,47,16,16,0,48},//15 , idx=0x12 - //{49,44,16,16,0,48},//12 , idx=0x13 - //{49,40,16,0,0,48},//9 , idx=0x14 - {34,31,28,20,0,32},//43 , idx=0x0b - {34,31,27,18,0,32},//40 , idx=0x0c - {34,31,26,16,0,32},//37 , idx=0x0d - {34,30,22,16,0,32},//32 , idx=0x0e - {34,30,24,16,0,32},//26 , idx=0x0f - {49,46,40,16,0,48},//20 , idx=0x10 - {49,45,32,0,0,48},//17 , idx=0x11 - {49,45,22,18,0,48},//15 , idx=0x12 - {49,40,28,18,0,48},//12 , idx=0x13 - {49,34,20,16,0,48},//9 , idx=0x14 - {49,22,18,14,0,48},//6 , idx=0x15 - {49,16,16,0,0,48}};//3 //3, idx=0x16 - - -#if 0 -static unsigned char RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up - -static unsigned char PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; - -static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH - 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, - 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; - -/*static unsigned char RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, - 0,0,0,0,0,0x24,0x26,0x2a, - 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, - 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ -static unsigned char RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, - 0,0,0,0,0,0x24,0x26,0x2a, - 0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f, - 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; -static unsigned short N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, - 24,36,48,72,96,144,192,216, - 60,80,100,160,240,400,560,640, - 300,320,480,720,1000,1200,1600,2000}; -static unsigned short N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, - 12,18,24,36,48,72,96,108, - 30,40,50,80,120,200,280,320, - 150,160,240,360,500,600,800,1000}; -#if 0 -static unsigned char TRYING_NECESSARY[RATESIZE] = {2,2,2,2, - 2,2,3,3,4,4,5,7, - 4,4,7,10,10,12,12,18, - 5,7,7,8,11,18,36,60}; // 0329 // 1207 -static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, - 30,30,25,25,20,15,15,10, - 30,25,25,20,15,10,10,10, - 30,25,25,20,15,10,10,10}; -#endif - -static unsigned char DROPING_NECESSARY[RATESIZE] = {1,1,1,1, - 1,2,3,4,5,6,7,8, - 1,2,3,4,5,6,7,8, - 5,6,7,8,9,10,11,12}; - -#if 0 -static unsigned int INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode - 0x0f8ff010, // 1: 40M GN mode - 0x0f8ff005, // 2: BN mode/ 40M BGN mode - 0x0f8ff000, // 3: N mode - 0x00000ff5, // 4: BG mode - 0x00000ff0, // 5: G mode - 0x0000000d, // 6: B mode - 0, // 7: - 0, // 8: - 0, // 9: - 0, // 10: - 0, // 11: - 0, // 12: - 0, // 13: - 0, // 14: - 0, // 15: - - }; -#endif -static unsigned char PendingForRateUpFail[5]={2,10,24,40,60}; - -static unsigned short DefaultTxRPTTiming=0x186a; //200ms -unsigned short DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms -#if 0 -static unsigned short MinTxRPTTiming=0x186a; //200ms -#endif -unsigned char TxRPTTiming_idx=1; -unsigned char DynamicTxRPTTimingCounter=0; - - -// End Rate adaptive parameters -int RateAdaptiveInfoInit(PSTATION_RA_INFO pRaInfo) -{ - if(pRaInfo) - { -/* panic_printk("%s %d, aid %d\n", __FUNCTION__, __LINE__, pRaInfo->pstat->aid);*/ - pRaInfo->DecisionRate = 0x13; - pRaInfo->PreRate = 0x13; - pRaInfo->HighestRate=0x13; - pRaInfo->LowestRate=0; - pRaInfo->RateID=0; - pRaInfo->RateMask=0xffffffff; - pRaInfo->RssiStaRA=0; - pRaInfo->PreRssiStaRA=0; - pRaInfo->SGIEnable=0; - pRaInfo->RAUseRate=0xffffffff; - pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; - pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; - pRaInfo->RateSGI=0; - pRaInfo->Active=1; //Active is not used at present. by page, 110819 - pRaInfo->RptTime = 0x927c; - pRaInfo->DROP=0; - pRaInfo->RTY[0]=0; - pRaInfo->RTY[1]=0; - pRaInfo->RTY[2]=0; - pRaInfo->RTY[3]=0; - pRaInfo->RTY[4]=0; - pRaInfo->TOTAL=0; -#if 1 - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; -#endif -#if 0 - pRaInfo->TryingState=0; - pRaInfo->RateBeforeTrying=0x13; -#endif -#if 0 //def POWER_TRAINING_ACTIVE - pRaInfo->PTTryState=0; - pRaInfo->PTStage=0; - pRaInfo->PTStopCount=0; - pRaInfo->PTPreRate=0; - pRaInfo->PTPreRssi=0; - pRaInfo->PTModeSS=0; - pRaInfo->RAstage=0; -#endif - } - return 0; -} - -int ARFBRefresh(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) -{ // Wilson 2011/10/26 - unsigned int MaskFromReg; - int i; - - // Test for Wilson -#if defined(CONFIG_PCI_HCI) - RTL_W16(REG_88E_TXRPT_TIM, DefaultTxRPTTiming); //200ms -#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - notify_tx_report_interval_change(priv, DefaultTxRPTTiming); -#endif - RTL_W32(DARFRC, 0x04020100); - RTL_W32(DARFRC+4, 0x0a080706); - - switch(pRaInfo->RateID) { - case RATR_INX_WIRELESS_NGB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; - break; - case RATR_INX_WIRELESS_NG: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; - break; - case RATR_INX_WIRELESS_NB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; - break; - case RATR_INX_WIRELESS_N: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; - break; - case RATR_INX_WIRELESS_GB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; - break; - case RATR_INX_WIRELESS_G: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; - break; - case RATR_INX_WIRELESS_B: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; - break; - case 12: - MaskFromReg=RTL_R32(ARFR0); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 13: - MaskFromReg=RTL_R32(ARFR1); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 14: - MaskFromReg=RTL_R32(ARFR2); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 15: - MaskFromReg=RTL_R32(ARFR3); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - default: - pRaInfo->RAUseRate=(pRaInfo->RateMask); - break; - } - // Highest rate - if (pRaInfo->RAUseRate) { - for (i=RATESIZE;i>=0;i--) { - if((pRaInfo->RAUseRate)&BIT(i)) { - pRaInfo->HighestRate=i; - break; - } - } - } else { - pRaInfo->HighestRate=0; - } - - // Lowest rate - if (pRaInfo->RAUseRate) { - for (i=0;iRAUseRate)&BIT(i)) { - pRaInfo->LowestRate=i; - break; - } - } - } else { - pRaInfo->LowestRate=0; - } -#if 0 - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAExtendCounter=0; -#endif - -/* panic_printk("%s %d: RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", - __FUNCTION__, __LINE__, - pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate);*/ - return 0; -} - - -static int RateDown(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) -{ - unsigned char RateID, LowestRate, HighestRate; - unsigned char i; - - if(NULL == pRaInfo) { - printk("%s %d: pRaInfo is NULL\n", __FUNCTION__, __LINE__); - return -1; - } - RateID = pRaInfo->PreRate; - LowestRate = pRaInfo->LowestRate; - HighestRate = pRaInfo->HighestRate; - -/* panic_printk("%s %d: RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", - __FUNCTION__, __LINE__, - RateID, LowestRate, HighestRate, pRaInfo->RateSGI);*/ - - if (RateID > HighestRate) { - RateID=HighestRate; - } else if(pRaInfo->RateSGI) { - pRaInfo->RateSGI=0; - } else if (RateID > LowestRate) { - if (RateID > 0) { - for (i=RateID-1; i>LowestRate;i--) { - if (pRaInfo->RAUseRate & BIT(i)) { - RateID=i; - goto RateDownFinish; - } - } - } - } else if (RateID <= LowestRate) { - RateID = LowestRate; - } - -RateDownFinish: -#if 1 - if (pRaInfo->RAWaitingCounter==1) { - pRaInfo->RAWaitingCounter+=1; - pRaInfo->RAPendingCounter+=1; - } - else if(pRaInfo->RAWaitingCounter==0){ - } else { - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - } - - if(pRaInfo->RAPendingCounter>=4) - pRaInfo->RAPendingCounter=4; -#endif - - pRaInfo->DecisionRate=RateID; - RTL8188E_SetTxReportTimeByRA(priv, 2); - -/* panic_printk("=====> rate down %s %d: Rate down to RateID %d RateSGI %d\n", __FUNCTION__, __LINE__, RateID, pRaInfo->RateSGI);*/ - return 0; -} - - -static int RateUp(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) -{ - unsigned char RateID, HighestRate; - unsigned char i; - - if(NULL == pRaInfo) { - printk("%s %d: pRaInfo is NULL\n", __FUNCTION__, __LINE__); - return -1; - } - RateID = pRaInfo->PreRate; -#if 0 - pRaInfo->RateBeforeTrying=RateID; -#endif - HighestRate = pRaInfo->HighestRate; -/* panic_printk("%s %d: RateID=%d HighestRate=%d\n", __FUNCTION__, __LINE__, RateID, HighestRate);*/ -#if 1 - if (pRaInfo->RAWaitingCounter==1) { - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - } else if (pRaInfo->RAWaitingCounter>1) { - pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; - goto RateUpfinish; - } - RTL8188E_SetTxReportTimeByRA(priv, 0); -/* panic_printk("%s %d, Decrease RPT Timing\n", __FUNCTION__, __LINE__);*/ -#endif - - if (RateID < HighestRate) { - for (i=RateID+1; i<=HighestRate; i++) { - if (pRaInfo->RAUseRate & BIT(i)) { - RateID=i; - goto RateUpfinish; - } - } - } else if(RateID == HighestRate) { - if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) - pRaInfo->RateSGI = 1; - else if((pRaInfo->SGIEnable) !=1 ) - pRaInfo->RateSGI = 0; - } else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */ { - RateID = HighestRate; - } - -RateUpfinish: -#if 1 - //if(pRaInfo->RAWaitingCounter==10) - if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) - pRaInfo->RAWaitingCounter=0; - else - pRaInfo->RAWaitingCounter++; -#endif - pRaInfo->DecisionRate=RateID; -#if 0 - pRaInfo->TryingState=1; - StartRateTrying(Adapter,pRaInfo); -#endif -/* panic_printk("%s %d: Rate up to RateID %d\n", __FUNCTION__, __LINE__, RateID);*/ - return 0; -} - - -static void ResetRaCounter(PSTATION_RA_INFO pRaInfo){ - unsigned char RateID; - RateID=pRaInfo->DecisionRate; - pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; - pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; -} - -#if 0 -void StartRateTrying(IN PADAPTER Adapter, IN PSTATION_RA_INFO pRaInfo) -{ - - // Test for Wilson - PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME,0x0138); - RT_TRACE(COMP_RATE_ADAPTIVE, DBG_LOUD, - ("StartRateTrying(): ")); - // Need to Modify (Try bit?, Try timing) - - -} - -u1Byte EndRateTrying(IN PADAPTER Adapter, IN PSTATION_RA_INFO pRaInfo) -{ - - u1Byte TryResult=0; - u4Byte pool_retry; - pRaInfo->DecisionRate=(pRaInfo->DecisionRate)&0x7f; - PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME,0x44A5); - pool_retry=pRaInfo->RTY[1]+pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; - if (pool_retry>2) - TryResult=0; - else - TryResult=1; - - return TryResult; - - -} -#endif - - -/* moved to 8188e_hw.c - -void SetTxRPTTiming(IN PADAPTER Adapter, int extend) -{ - u2Byte WriteTxRPTTiming; - u1Byte idx; - - idx=TxRPTTiming_idx; - if (extend==0) // back to default timing - idx=1; //400ms - else if (extend==1) {// increase the timing - idx+=1; - if (idx>5) - idx=5; - } - else if (extend==2) {// decrease the timing - if(idx!=0) - idx-=1; - } - WriteTxRPTTiming=DynamicTxRPTTiming[idx]; - TxRPTTiming_idx=idx; - PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME, WriteTxRPTTiming); - -} -*/ - - -void RateDecision(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) -{ - unsigned char RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; - //unsigned int pool_retry; - //unsigned char Try_Result=0; - - if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */ { -#if 0 - if (pRaInfo->TryingState==1){ - - pRaInfo->TryingState=0; - Try_Result=EndRateTrying(Adapter,pRaInfo); - if (Try_Result==1) // Try good - pRaInfo->RateBeforeTrying=pRaInfo->DecisionRate; - else // Try bad - pRaInfo->DecisionRate=pRaInfo->RateBeforeTrying; - goto RateDecisionFinish; - } -#endif - if ((pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))) { - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - } - // Start RA decision - if (pRaInfo->PreRate > pRaInfo->HighestRate) - RateID = pRaInfo->HighestRate; - else - RateID = pRaInfo->PreRate; - if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) - RtyPtID=0; - else - RtyPtID=1; - PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page - -/* panic_printk("%s %d: NscDown init is %d\n", __FUNCTION__, __LINE__, pRaInfo->NscDown);*/ - //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; - pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; - pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; - pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; - pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; - pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; -/* panic_printk("%s %d: NscDown is %d, total*penalty[5] is %d\n", __FUNCTION__, __LINE__, - pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]));*/ - if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) - pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; - else - pRaInfo->NscDown=0; - - // rate up - PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; -/* panic_printk("%s %d: NscUp init is %d\n", __FUNCTION__, __LINE__, pRaInfo->NscUp);*/ - pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; - pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; - pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; - pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; - pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; -/* panic_printk("%s %d: NscUp is %d, total*up[5] is %d\n", __FUNCTION__, __LINE__, - pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]));*/ - if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) - pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; - else - pRaInfo->NscUp = 0; - /*printk("%s %d, RTY0 %d, RTY1 %d, RTY2 %d, RTY3 %d, RTY4 %d, userate 0x%08x\n", - __FUNCTION__, __LINE__, pRaInfo->RTY[0], pRaInfo->RTY[1], pRaInfo->RTY[2], pRaInfo->RTY[3], pRaInfo->RTY[4], pRaInfo->RAUseRate);*/ -/* panic_printk("%s %d: RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d\n", - __FUNCTION__, __LINE__, - pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp);*/ - if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) - RateDown(priv, pRaInfo); - //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) - RateUp(priv, pRaInfo); -#if 0 - RateDecisionFinish: -#endif - if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) - DynamicTxRPTTimingCounter+=1; - else - DynamicTxRPTTimingCounter=0; - - if (DynamicTxRPTTimingCounter>=4) { - RTL8188E_SetTxReportTimeByRA(priv, 1); -/* panic_printk("%s %d, <=====Rate don't change 4 times, Extend RPT Timing\n", __FUNCTION__, __LINE__);*/ - DynamicTxRPTTimingCounter=0; - } - - pRaInfo->RptTime = DynamicTxRPTTiming[TxRPTTiming_idx]; - pRaInfo->PreRate = pRaInfo->DecisionRate; - - ResetRaCounter( pRaInfo); - } -} -#endif -#endif - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.c + +Abstract: + Implement Rate Adaptive functions for common operations. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. + +--*/ +#ifdef __ECOS +#include +#endif +#include "8192cd_cfg.h" +#ifdef CONFIG_RTL_88E_SUPPORT + + +#ifdef TXREPORT +#include "8192cd.h" +#include "8192cd_headers.h" +#include "8192cd_hw.h" +#include "8192cd_util.h" + +/* + * RateAdaptive.h - Start + */ +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +/* + * RateAdaptive.h - End + */ + + +static unsigned char RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 + {6,5,4,3,0,4},//86 , idx=1 + {6,5,4,2,0,4},//81 , idx=2 + {8,7,6,4,0,6},//75 , idx=3 + {10,9,8,6,0,8},//71 , idx=4 + {10,9,8,4,0,8},//66 , idx=5 + {10,9,8,2,0,8},//62 , idx=6 + {10,9,8,0,0,8},//59 , idx=7 + {18,17,16,8,0,16},//53 , idx=8 + {26,25,24,16,0,24},//50 , idx=9 + {34,33,32,24,0,32},//47 , idx=0x0a + //{34,33,32,16,0,32},//43 , idx=0x0b + //{34,33,32,8,0,32},//40 , idx=0x0c + //{34,33,28,8,0,32},//37 , idx=0x0d + //{34,33,20,8,0,32},//32 , idx=0x0e + //{34,32,24,8,0,32},//26 , idx=0x0f + //{49,48,32,16,0,48},//20 , idx=0x10 + //{49,48,24,0,0,48},//17 , idx=0x11 + //{49,47,16,16,0,48},//15 , idx=0x12 + //{49,44,16,16,0,48},//12 , idx=0x13 + //{49,40,16,0,0,48},//9 , idx=0x14 + {34,31,28,20,0,32},//43 , idx=0x0b + {34,31,27,18,0,32},//40 , idx=0x0c + {34,31,26,16,0,32},//37 , idx=0x0d + {34,30,22,16,0,32},//32 , idx=0x0e + {34,30,24,16,0,32},//26 , idx=0x0f + {49,46,40,16,0,48},//20 , idx=0x10 + {49,45,32,0,0,48},//17 , idx=0x11 + {49,45,22,18,0,48},//15 , idx=0x12 + {49,40,28,18,0,48},//12 , idx=0x13 + {49,34,20,16,0,48},//9 , idx=0x14 + {49,22,18,14,0,48},//6 , idx=0x15 + {49,16,16,0,0,48}};//3 //3, idx=0x16 + + +#if 0 +static unsigned char RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up + +static unsigned char PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; + +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH + 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +/*static unsigned char RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ +static unsigned char RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; +static unsigned short N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,560,640, + 300,320,480,720,1000,1200,1600,2000}; +static unsigned short N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,280,320, + 150,160,240,360,500,600,800,1000}; +#if 0 +static unsigned char TRYING_NECESSARY[RATESIZE] = {2,2,2,2, + 2,2,3,3,4,4,5,7, + 4,4,7,10,10,12,12,18, + 5,7,7,8,11,18,36,60}; // 0329 // 1207 +static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, + 30,30,25,25,20,15,15,10, + 30,25,25,20,15,10,10,10, + 30,25,25,20,15,10,10,10}; +#endif + +static unsigned char DROPING_NECESSARY[RATESIZE] = {1,1,1,1, + 1,2,3,4,5,6,7,8, + 1,2,3,4,5,6,7,8, + 5,6,7,8,9,10,11,12}; + +#if 0 +static unsigned int INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode + 0x0f8ff010, // 1: 40M GN mode + 0x0f8ff005, // 2: BN mode/ 40M BGN mode + 0x0f8ff000, // 3: N mode + 0x00000ff5, // 4: BG mode + 0x00000ff0, // 5: G mode + 0x0000000d, // 6: B mode + 0, // 7: + 0, // 8: + 0, // 9: + 0, // 10: + 0, // 11: + 0, // 12: + 0, // 13: + 0, // 14: + 0, // 15: + + }; +#endif +static unsigned char PendingForRateUpFail[5]={2,10,24,40,60}; + +static unsigned short DefaultTxRPTTiming=0x186a; //200ms +unsigned short DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms +#if 0 +static unsigned short MinTxRPTTiming=0x186a; //200ms +#endif +unsigned char TxRPTTiming_idx=1; +unsigned char DynamicTxRPTTimingCounter=0; + + +// End Rate adaptive parameters +int RateAdaptiveInfoInit(PSTATION_RA_INFO pRaInfo) +{ + if(pRaInfo) + { +/* panic_printk("%s %d, aid %d\n", __FUNCTION__, __LINE__, pRaInfo->pstat->aid);*/ + pRaInfo->DecisionRate = 0x13; + pRaInfo->PreRate = 0x13; + pRaInfo->HighestRate=0x13; + pRaInfo->LowestRate=0; + pRaInfo->RateID=0; + pRaInfo->RateMask=0xffffffff; + pRaInfo->RssiStaRA=0; + pRaInfo->PreRssiStaRA=0; + pRaInfo->SGIEnable=0; + pRaInfo->RAUseRate=0xffffffff; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->RateSGI=0; + pRaInfo->Active=1; //Active is not used at present. by page, 110819 + pRaInfo->RptTime = 0x927c; + pRaInfo->DROP=0; + pRaInfo->RTY[0]=0; + pRaInfo->RTY[1]=0; + pRaInfo->RTY[2]=0; + pRaInfo->RTY[3]=0; + pRaInfo->RTY[4]=0; + pRaInfo->TOTAL=0; +#if 1 + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; +#endif +#if 0 + pRaInfo->TryingState=0; + pRaInfo->RateBeforeTrying=0x13; +#endif +#if 0 //def POWER_TRAINING_ACTIVE + pRaInfo->PTTryState=0; + pRaInfo->PTStage=0; + pRaInfo->PTStopCount=0; + pRaInfo->PTPreRate=0; + pRaInfo->PTPreRssi=0; + pRaInfo->PTModeSS=0; + pRaInfo->RAstage=0; +#endif + } + return 0; +} + +int ARFBRefresh(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) +{ // Wilson 2011/10/26 + unsigned int MaskFromReg; + int i; + + // Test for Wilson +#if defined(CONFIG_PCI_HCI) + RTL_W16(REG_88E_TXRPT_TIM, DefaultTxRPTTiming); //200ms +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + notify_tx_report_interval_change(priv, DefaultTxRPTTiming); +#endif + RTL_W32(DARFRC, 0x04020100); + RTL_W32(DARFRC+4, 0x0a080706); + + switch(pRaInfo->RateID) { + case RATR_INX_WIRELESS_NGB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; + break; + case RATR_INX_WIRELESS_NG: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; + break; + case RATR_INX_WIRELESS_N: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; + break; + case RATR_INX_WIRELESS_G: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; + break; + case 12: + MaskFromReg=RTL_R32(ARFR0); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 13: + MaskFromReg=RTL_R32(ARFR1); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 14: + MaskFromReg=RTL_R32(ARFR2); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 15: + MaskFromReg=RTL_R32(ARFR3); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + default: + pRaInfo->RAUseRate=(pRaInfo->RateMask); + break; + } + // Highest rate + if (pRaInfo->RAUseRate) { + for (i=RATESIZE;i>=0;i--) { + if((pRaInfo->RAUseRate)&BIT(i)) { + pRaInfo->HighestRate=i; + break; + } + } + } else { + pRaInfo->HighestRate=0; + } + + // Lowest rate + if (pRaInfo->RAUseRate) { + for (i=0;iRAUseRate)&BIT(i)) { + pRaInfo->LowestRate=i; + break; + } + } + } else { + pRaInfo->LowestRate=0; + } +#if 0 + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAExtendCounter=0; +#endif + +/* panic_printk("%s %d: RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", + __FUNCTION__, __LINE__, + pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate);*/ + return 0; +} + + +static int RateDown(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) +{ + unsigned char RateID, LowestRate, HighestRate; + unsigned char i; + + if(NULL == pRaInfo) { + printk("%s %d: pRaInfo is NULL\n", __FUNCTION__, __LINE__); + return -1; + } + RateID = pRaInfo->PreRate; + LowestRate = pRaInfo->LowestRate; + HighestRate = pRaInfo->HighestRate; + +/* panic_printk("%s %d: RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", + __FUNCTION__, __LINE__, + RateID, LowestRate, HighestRate, pRaInfo->RateSGI);*/ + + if (RateID > HighestRate) { + RateID=HighestRate; + } else if(pRaInfo->RateSGI) { + pRaInfo->RateSGI=0; + } else if (RateID > LowestRate) { + if (RateID > 0) { + for (i=RateID-1; i>LowestRate;i--) { + if (pRaInfo->RAUseRate & BIT(i)) { + RateID=i; + goto RateDownFinish; + } + } + } + } else if (RateID <= LowestRate) { + RateID = LowestRate; + } + +RateDownFinish: +#if 1 + if (pRaInfo->RAWaitingCounter==1) { + pRaInfo->RAWaitingCounter+=1; + pRaInfo->RAPendingCounter+=1; + } + else if(pRaInfo->RAWaitingCounter==0){ + } else { + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + + if(pRaInfo->RAPendingCounter>=4) + pRaInfo->RAPendingCounter=4; +#endif + + pRaInfo->DecisionRate=RateID; + RTL8188E_SetTxReportTimeByRA(priv, 2); + +/* panic_printk("=====> rate down %s %d: Rate down to RateID %d RateSGI %d\n", __FUNCTION__, __LINE__, RateID, pRaInfo->RateSGI);*/ + return 0; +} + + +static int RateUp(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) +{ + unsigned char RateID, HighestRate; + unsigned char i; + + if(NULL == pRaInfo) { + printk("%s %d: pRaInfo is NULL\n", __FUNCTION__, __LINE__); + return -1; + } + RateID = pRaInfo->PreRate; +#if 0 + pRaInfo->RateBeforeTrying=RateID; +#endif + HighestRate = pRaInfo->HighestRate; +/* panic_printk("%s %d: RateID=%d HighestRate=%d\n", __FUNCTION__, __LINE__, RateID, HighestRate);*/ +#if 1 + if (pRaInfo->RAWaitingCounter==1) { + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } else if (pRaInfo->RAWaitingCounter>1) { + pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; + goto RateUpfinish; + } + RTL8188E_SetTxReportTimeByRA(priv, 0); +/* panic_printk("%s %d, Decrease RPT Timing\n", __FUNCTION__, __LINE__);*/ +#endif + + if (RateID < HighestRate) { + for (i=RateID+1; i<=HighestRate; i++) { + if (pRaInfo->RAUseRate & BIT(i)) { + RateID=i; + goto RateUpfinish; + } + } + } else if(RateID == HighestRate) { + if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) + pRaInfo->RateSGI = 1; + else if((pRaInfo->SGIEnable) !=1 ) + pRaInfo->RateSGI = 0; + } else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */ { + RateID = HighestRate; + } + +RateUpfinish: +#if 1 + //if(pRaInfo->RAWaitingCounter==10) + if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) + pRaInfo->RAWaitingCounter=0; + else + pRaInfo->RAWaitingCounter++; +#endif + pRaInfo->DecisionRate=RateID; +#if 0 + pRaInfo->TryingState=1; + StartRateTrying(Adapter,pRaInfo); +#endif +/* panic_printk("%s %d: Rate up to RateID %d\n", __FUNCTION__, __LINE__, RateID);*/ + return 0; +} + + +static void ResetRaCounter(PSTATION_RA_INFO pRaInfo){ + unsigned char RateID; + RateID=pRaInfo->DecisionRate; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; +} + +#if 0 +void StartRateTrying(IN PADAPTER Adapter, IN PSTATION_RA_INFO pRaInfo) +{ + + // Test for Wilson + PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME,0x0138); + RT_TRACE(COMP_RATE_ADAPTIVE, DBG_LOUD, + ("StartRateTrying(): ")); + // Need to Modify (Try bit?, Try timing) + + +} + +u1Byte EndRateTrying(IN PADAPTER Adapter, IN PSTATION_RA_INFO pRaInfo) +{ + + u1Byte TryResult=0; + u4Byte pool_retry; + pRaInfo->DecisionRate=(pRaInfo->DecisionRate)&0x7f; + PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME,0x44A5); + pool_retry=pRaInfo->RTY[1]+pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + if (pool_retry>2) + TryResult=0; + else + TryResult=1; + + return TryResult; + + +} +#endif + + +/* moved to 8188e_hw.c + +void SetTxRPTTiming(IN PADAPTER Adapter, int extend) +{ + u2Byte WriteTxRPTTiming; + u1Byte idx; + + idx=TxRPTTiming_idx; + if (extend==0) // back to default timing + idx=1; //400ms + else if (extend==1) {// increase the timing + idx+=1; + if (idx>5) + idx=5; + } + else if (extend==2) {// decrease the timing + if(idx!=0) + idx-=1; + } + WriteTxRPTTiming=DynamicTxRPTTiming[idx]; + TxRPTTiming_idx=idx; + PlatformEFIOWrite2Byte(Adapter, REG_TX_RPT_TIME, WriteTxRPTTiming); + +} +*/ + + +void RateDecision(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) +{ + unsigned char RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + //unsigned int pool_retry; + //unsigned char Try_Result=0; + + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */ { +#if 0 + if (pRaInfo->TryingState==1){ + + pRaInfo->TryingState=0; + Try_Result=EndRateTrying(Adapter,pRaInfo); + if (Try_Result==1) // Try good + pRaInfo->RateBeforeTrying=pRaInfo->DecisionRate; + else // Try bad + pRaInfo->DecisionRate=pRaInfo->RateBeforeTrying; + goto RateDecisionFinish; + } +#endif + if ((pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))) { + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + // Start RA decision + if (pRaInfo->PreRate > pRaInfo->HighestRate) + RateID = pRaInfo->HighestRate; + else + RateID = pRaInfo->PreRate; + if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) + RtyPtID=0; + else + RtyPtID=1; + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page + +/* panic_printk("%s %d: NscDown init is %d\n", __FUNCTION__, __LINE__, pRaInfo->NscDown);*/ + //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; + pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; + pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; + pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; + pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; +/* panic_printk("%s %d: NscDown is %d, total*penalty[5] is %d\n", __FUNCTION__, __LINE__, + pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]));*/ + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) + pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; + else + pRaInfo->NscDown=0; + + // rate up + PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; +/* panic_printk("%s %d: NscUp init is %d\n", __FUNCTION__, __LINE__, pRaInfo->NscUp);*/ + pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; + pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; + pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; + pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; + pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; +/* panic_printk("%s %d: NscUp is %d, total*up[5] is %d\n", __FUNCTION__, __LINE__, + pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]));*/ + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) + pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; + else + pRaInfo->NscUp = 0; + /*printk("%s %d, RTY0 %d, RTY1 %d, RTY2 %d, RTY3 %d, RTY4 %d, userate 0x%08x\n", + __FUNCTION__, __LINE__, pRaInfo->RTY[0], pRaInfo->RTY[1], pRaInfo->RTY[2], pRaInfo->RTY[3], pRaInfo->RTY[4], pRaInfo->RAUseRate);*/ +/* panic_printk("%s %d: RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d\n", + __FUNCTION__, __LINE__, + pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp);*/ + if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) + RateDown(priv, pRaInfo); + //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) + RateUp(priv, pRaInfo); +#if 0 + RateDecisionFinish: +#endif + if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) + DynamicTxRPTTimingCounter+=1; + else + DynamicTxRPTTimingCounter=0; + + if (DynamicTxRPTTimingCounter>=4) { + RTL8188E_SetTxReportTimeByRA(priv, 1); +/* panic_printk("%s %d, <=====Rate don't change 4 times, Extend RPT Timing\n", __FUNCTION__, __LINE__);*/ + DynamicTxRPTTimingCounter=0; + } + + pRaInfo->RptTime = DynamicTxRPTTiming[TxRPTTiming_idx]; + pRaInfo->PreRate = pRaInfo->DecisionRate; + + ResetRaCounter( pRaInfo); + } +} +#endif +#endif + diff --git a/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8192EE b/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8192EE old mode 100755 new mode 100644 index fe22fae8f85..91491a23327 --- a/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8192EE +++ b/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8192EE @@ -1,114 +1,114 @@ -#ifndef __HALCFG_H__ -#define __HALCFG_H__ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalComDef.h - -Abstract: - Defined HAL Mapping Type - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - - -//1 Configuration below are decided by Driver - -//3 Driver provide some header files in order to eliminate warning message -#include "../rtl8881a/8881a.h" - -//3 Mapping Basic Type -#define VOID void -#define PVOID void * - -//typedef unsigned char BOOLEAN,*PBOOLEAN; -//typedef unsigned char UCHAR, *PUCHAR; -//typedef unsigned short USHORT, *PUSHORT; -typedef short SHORT; -//typedef unsigned int ULONG, *PULONG; -typedef long LONG; - -typedef long long LONGLONG; -//typedef unsigned int UINT; -typedef unsigned long long ULONGLONG; -typedef unsigned long long LARGE_INTEGER; - -typedef unsigned char u1Byte,*pu1Byte; -typedef unsigned short u2Byte,*pu2Byte; -typedef unsigned int u4Byte,*pu4Byte; -typedef unsigned long long u8Byte,*pu8Byte; - -typedef signed char s1Byte,*ps1Byte; -typedef signed short s2Byte,*ps2Byte; -typedef signed int s4Byte,*ps4Byte; -typedef signed long long s8Byte,*ps8Byte; -typedef unsigned long long ULONG64,*PULONG64; - -//typedef unsigned char UINT8; -//typedef unsigned short UINT16; -//typedef unsigned int UINT32; -//typedef signed int INT32; -//typedef signed char INT8; -//typedef signed int INT; - -typedef const unsigned char cu8; - -typedef __signed char s8; -//typedef unsigned char u8; - -typedef __signed short s16; -//typedef unsigned short u16; - -typedef __signed int s32; -//typedef unsigned int u32; - -typedef __signed__ long s64; -//typedef unsigned long u64; - - -//3 Mapping IO -#define HAL_PADAPTER PRTL8192CD_PRIV -#define HAL_RTL_R8(reg) \ - (RTL_R8_F(Adapter, reg)) - -#define HAL_RTL_R16(reg) \ - (RTL_R16_F(Adapter, reg)) - -#define HAL_RTL_R32(reg) \ - (RTL_R32_F(Adapter, reg)) - -#define HAL_RTL_W8(reg, val8) \ +#ifndef __HALCFG_H__ +#define __HALCFG_H__ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalComDef.h + +Abstract: + Defined HAL Mapping Type + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + + +//1 Configuration below are decided by Driver + +//3 Driver provide some header files in order to eliminate warning message +#include "../rtl8881a/8881a.h" + +//3 Mapping Basic Type +#define VOID void +#define PVOID void * + +//typedef unsigned char BOOLEAN,*PBOOLEAN; +//typedef unsigned char UCHAR, *PUCHAR; +//typedef unsigned short USHORT, *PUSHORT; +typedef short SHORT; +//typedef unsigned int ULONG, *PULONG; +typedef long LONG; + +typedef long long LONGLONG; +//typedef unsigned int UINT; +typedef unsigned long long ULONGLONG; +typedef unsigned long long LARGE_INTEGER; + +typedef unsigned char u1Byte,*pu1Byte; +typedef unsigned short u2Byte,*pu2Byte; +typedef unsigned int u4Byte,*pu4Byte; +typedef unsigned long long u8Byte,*pu8Byte; + +typedef signed char s1Byte,*ps1Byte; +typedef signed short s2Byte,*ps2Byte; +typedef signed int s4Byte,*ps4Byte; +typedef signed long long s8Byte,*ps8Byte; +typedef unsigned long long ULONG64,*PULONG64; + +//typedef unsigned char UINT8; +//typedef unsigned short UINT16; +//typedef unsigned int UINT32; +//typedef signed int INT32; +//typedef signed char INT8; +//typedef signed int INT; + +typedef const unsigned char cu8; + +typedef __signed char s8; +//typedef unsigned char u8; + +typedef __signed short s16; +//typedef unsigned short u16; + +typedef __signed int s32; +//typedef unsigned int u32; + +typedef __signed__ long s64; +//typedef unsigned long u64; + + +//3 Mapping IO +#define HAL_PADAPTER PRTL8192CD_PRIV +#define HAL_RTL_R8(reg) \ + (RTL_R8_F(Adapter, reg)) + +#define HAL_RTL_R16(reg) \ + (RTL_R16_F(Adapter, reg)) + +#define HAL_RTL_R32(reg) \ + (RTL_R32_F(Adapter, reg)) + +#define HAL_RTL_W8(reg, val8) \ do { \ - RTL_W8_F(Adapter, reg, val8); \ + RTL_W8_F(Adapter, reg, val8); \ } while (0) -#define HAL_RTL_W16(reg, val16) \ +#define HAL_RTL_W16(reg, val16) \ do { \ - RTL_W16_F(Adapter, reg, val16); \ + RTL_W16_F(Adapter, reg, val16); \ } while (0) -#define HAL_RTL_W32(reg, val32) \ +#define HAL_RTL_W32(reg, val32) \ do { \ - RTL_W32_F(Adapter, reg, val32) ; \ - } while (0) - - -//3 Mapping Linker Section -#define __HAL_MIPS16__ -#define __HAL_FAST__ -#define __HAL_MIDIUM__ -#define __HAL_LOW__ - - -//3 Mapping Critical Section Protection Method - - -//3 Mapping Debug -#define HALprintf printk - - + RTL_W32_F(Adapter, reg, val32) ; \ + } while (0) + + +//3 Mapping Linker Section +#define __HAL_MIPS16__ +#define __HAL_FAST__ +#define __HAL_MIDIUM__ +#define __HAL_LOW__ + + +//3 Mapping Critical Section Protection Method + + +//3 Mapping Debug +#define HALprintf printk + + #endif //#ifndef __HALCFG_H__ \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8881A b/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8881A old mode 100755 new mode 100644 index fe22fae8f85..91491a23327 --- a/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8881A +++ b/package/kernel/rtl8192cd/WlanHAL/Config/HalCfg.h_8881A @@ -1,114 +1,114 @@ -#ifndef __HALCFG_H__ -#define __HALCFG_H__ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalComDef.h - -Abstract: - Defined HAL Mapping Type - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - - -//1 Configuration below are decided by Driver - -//3 Driver provide some header files in order to eliminate warning message -#include "../rtl8881a/8881a.h" - -//3 Mapping Basic Type -#define VOID void -#define PVOID void * - -//typedef unsigned char BOOLEAN,*PBOOLEAN; -//typedef unsigned char UCHAR, *PUCHAR; -//typedef unsigned short USHORT, *PUSHORT; -typedef short SHORT; -//typedef unsigned int ULONG, *PULONG; -typedef long LONG; - -typedef long long LONGLONG; -//typedef unsigned int UINT; -typedef unsigned long long ULONGLONG; -typedef unsigned long long LARGE_INTEGER; - -typedef unsigned char u1Byte,*pu1Byte; -typedef unsigned short u2Byte,*pu2Byte; -typedef unsigned int u4Byte,*pu4Byte; -typedef unsigned long long u8Byte,*pu8Byte; - -typedef signed char s1Byte,*ps1Byte; -typedef signed short s2Byte,*ps2Byte; -typedef signed int s4Byte,*ps4Byte; -typedef signed long long s8Byte,*ps8Byte; -typedef unsigned long long ULONG64,*PULONG64; - -//typedef unsigned char UINT8; -//typedef unsigned short UINT16; -//typedef unsigned int UINT32; -//typedef signed int INT32; -//typedef signed char INT8; -//typedef signed int INT; - -typedef const unsigned char cu8; - -typedef __signed char s8; -//typedef unsigned char u8; - -typedef __signed short s16; -//typedef unsigned short u16; - -typedef __signed int s32; -//typedef unsigned int u32; - -typedef __signed__ long s64; -//typedef unsigned long u64; - - -//3 Mapping IO -#define HAL_PADAPTER PRTL8192CD_PRIV -#define HAL_RTL_R8(reg) \ - (RTL_R8_F(Adapter, reg)) - -#define HAL_RTL_R16(reg) \ - (RTL_R16_F(Adapter, reg)) - -#define HAL_RTL_R32(reg) \ - (RTL_R32_F(Adapter, reg)) - -#define HAL_RTL_W8(reg, val8) \ +#ifndef __HALCFG_H__ +#define __HALCFG_H__ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalComDef.h + +Abstract: + Defined HAL Mapping Type + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + + +//1 Configuration below are decided by Driver + +//3 Driver provide some header files in order to eliminate warning message +#include "../rtl8881a/8881a.h" + +//3 Mapping Basic Type +#define VOID void +#define PVOID void * + +//typedef unsigned char BOOLEAN,*PBOOLEAN; +//typedef unsigned char UCHAR, *PUCHAR; +//typedef unsigned short USHORT, *PUSHORT; +typedef short SHORT; +//typedef unsigned int ULONG, *PULONG; +typedef long LONG; + +typedef long long LONGLONG; +//typedef unsigned int UINT; +typedef unsigned long long ULONGLONG; +typedef unsigned long long LARGE_INTEGER; + +typedef unsigned char u1Byte,*pu1Byte; +typedef unsigned short u2Byte,*pu2Byte; +typedef unsigned int u4Byte,*pu4Byte; +typedef unsigned long long u8Byte,*pu8Byte; + +typedef signed char s1Byte,*ps1Byte; +typedef signed short s2Byte,*ps2Byte; +typedef signed int s4Byte,*ps4Byte; +typedef signed long long s8Byte,*ps8Byte; +typedef unsigned long long ULONG64,*PULONG64; + +//typedef unsigned char UINT8; +//typedef unsigned short UINT16; +//typedef unsigned int UINT32; +//typedef signed int INT32; +//typedef signed char INT8; +//typedef signed int INT; + +typedef const unsigned char cu8; + +typedef __signed char s8; +//typedef unsigned char u8; + +typedef __signed short s16; +//typedef unsigned short u16; + +typedef __signed int s32; +//typedef unsigned int u32; + +typedef __signed__ long s64; +//typedef unsigned long u64; + + +//3 Mapping IO +#define HAL_PADAPTER PRTL8192CD_PRIV +#define HAL_RTL_R8(reg) \ + (RTL_R8_F(Adapter, reg)) + +#define HAL_RTL_R16(reg) \ + (RTL_R16_F(Adapter, reg)) + +#define HAL_RTL_R32(reg) \ + (RTL_R32_F(Adapter, reg)) + +#define HAL_RTL_W8(reg, val8) \ do { \ - RTL_W8_F(Adapter, reg, val8); \ + RTL_W8_F(Adapter, reg, val8); \ } while (0) -#define HAL_RTL_W16(reg, val16) \ +#define HAL_RTL_W16(reg, val16) \ do { \ - RTL_W16_F(Adapter, reg, val16); \ + RTL_W16_F(Adapter, reg, val16); \ } while (0) -#define HAL_RTL_W32(reg, val32) \ +#define HAL_RTL_W32(reg, val32) \ do { \ - RTL_W32_F(Adapter, reg, val32) ; \ - } while (0) - - -//3 Mapping Linker Section -#define __HAL_MIPS16__ -#define __HAL_FAST__ -#define __HAL_MIDIUM__ -#define __HAL_LOW__ - - -//3 Mapping Critical Section Protection Method - - -//3 Mapping Debug -#define HALprintf printk - - + RTL_W32_F(Adapter, reg, val32) ; \ + } while (0) + + +//3 Mapping Linker Section +#define __HAL_MIPS16__ +#define __HAL_FAST__ +#define __HAL_MIDIUM__ +#define __HAL_LOW__ + + +//3 Mapping Critical Section Protection Method + + +//3 Mapping Debug +#define HALprintf printk + + #endif //#ifndef __HALCFG_H__ \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E.txt old mode 100755 new mode 100644 index c7948ac22c6..8454892fb98 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E.txt @@ -1,131 +1,131 @@ -//// AGC_TABLE 1 for CG -0xc78 0xfb000001 //-110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfb040001 -0xc78 0xfb050001 //-100 -0xc78 0xfb060001 -0xc78 0xfb070001 -0xc78 0xfb080001 -0xc78 0xfa090001 -0xc78 0xf90A0001 //-90 -0xc78 0xf80B0001 -0xc78 0xf70C0001 -0xc78 0xf60D0001 -0xc78 0xf50E0001 -0xc78 0xf40F0001 //-80 -0xc78 0xf3100001 -0xc78 0xf2110001 -0xc78 0xf1120001 -0xc78 0xf0130001 -0xc78 0xef140001 //-70 -0xc78 0xee150001 -0xc78 0xed160001 -0xc78 0xeb170001 -0xc78 0xea180001 -0xc78 0xe9190001 //-60 -0xc78 0xe81A0001 -0xc78 0xe71B0001 -0xc78 0xe61C0001 -0xc78 0xe51D0001 -0xc78 0xe41E0001 //-50 -0xc78 0xe31F0001 -0xc78 0xe2200001 -0xc78 0xc5210001 -0xc78 0xc4220001 -0xc78 0xc3230001 //-40 -0xc78 0x04240001 -0xc78 0x03250001 -0xc78 0x02260001 -0xc78 0xa6270001 -0xc78 0xa5280001 //-30 -0xc78 0xa4290001 -0xc78 0x852A0001 -0xc78 0x842B0001 -0xc78 0x832C0001 -0xc78 0x822D0001 //-20 -0xc78 0x242E0001 -0xc78 0x232F0001 -0xc78 0x22300001 -0xc78 0x66310001 -0xc78 0x65320001 //-10 -0xc78 0x64330001 -0xc78 0x63340001 -0xc78 0x62350001 -0xc78 0x61360001 -0xc78 0x46370001 //0 -0xc78 0x45380001 -0xc78 0x44390001 -0xc78 0x433A0001 -0xc78 0x423B0001 -0xc78 0x413C0001 //10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 //16 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfb410001 -0xc78 0xfb420001 -0xc78 0xfb430001 -0xc78 0xfb440001 -0xc78 0xfb450001 //-100 -0xc78 0xfa460001 -0xc78 0xf9470001 -0xc78 0xf8480001 -0xc78 0xf7490001 -0xc78 0xf64a0001 //-90 -0xc78 0xf54b0001 -0xc78 0xf44c0001 -0xc78 0xf34d0001 -0xc78 0xf24e0001 -0xc78 0xf14f0001 //-80 -0xc78 0xf0500001 -0xc78 0xef510001 -0xc78 0xee520001 -0xc78 0xed530001 -0xc78 0xec540001 //-70 -0xc78 0xeb550001 -0xc78 0xea560001 -0xc78 0xe9570001 -0xc78 0xe8580001 -0xc78 0xe7590001 //-60 -0xc78 0xe65a0001 -0xc78 0xe55b0001 -0xc78 0xe45c0001 -0xc78 0xe35d0001 -0xc78 0xe25e0001 //-50 -0xc78 0xe15f0001 -0xc78 0x8a600001 -0xc78 0x89610001 -0xc78 0x88620001 -0xc78 0x87630001 //-40 -0xc78 0x86640001 -0xc78 0x85650001 -0xc78 0x84660001 -0xc78 0x83670001 -0xc78 0x82680001 //-30 -0xc78 0x6b690001 -0xc78 0x6a6a0001 -0xc78 0x696b0001 -0xc78 0x686c0001 -0xc78 0x676d0001 //-20 -0xc78 0x666e0001 -0xc78 0x656f0001 -0xc78 0x64700001 -0xc78 0x63710001 -0xc78 0x62720001 //-10 -0xc78 0x61730001 -0xc78 0x46740001 -0xc78 0x45750001 -0xc78 0x44760001 -0xc78 0x43770001 //0 -0xc78 0x42780001 -0xc78 0x41790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 +//// AGC_TABLE 1 for CG +0xc78 0xfb000001 //-110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfb040001 +0xc78 0xfb050001 //-100 +0xc78 0xfb060001 +0xc78 0xfb070001 +0xc78 0xfb080001 +0xc78 0xfa090001 +0xc78 0xf90A0001 //-90 +0xc78 0xf80B0001 +0xc78 0xf70C0001 +0xc78 0xf60D0001 +0xc78 0xf50E0001 +0xc78 0xf40F0001 //-80 +0xc78 0xf3100001 +0xc78 0xf2110001 +0xc78 0xf1120001 +0xc78 0xf0130001 +0xc78 0xef140001 //-70 +0xc78 0xee150001 +0xc78 0xed160001 +0xc78 0xeb170001 +0xc78 0xea180001 +0xc78 0xe9190001 //-60 +0xc78 0xe81A0001 +0xc78 0xe71B0001 +0xc78 0xe61C0001 +0xc78 0xe51D0001 +0xc78 0xe41E0001 //-50 +0xc78 0xe31F0001 +0xc78 0xe2200001 +0xc78 0xc5210001 +0xc78 0xc4220001 +0xc78 0xc3230001 //-40 +0xc78 0x04240001 +0xc78 0x03250001 +0xc78 0x02260001 +0xc78 0xa6270001 +0xc78 0xa5280001 //-30 +0xc78 0xa4290001 +0xc78 0x852A0001 +0xc78 0x842B0001 +0xc78 0x832C0001 +0xc78 0x822D0001 //-20 +0xc78 0x242E0001 +0xc78 0x232F0001 +0xc78 0x22300001 +0xc78 0x66310001 +0xc78 0x65320001 //-10 +0xc78 0x64330001 +0xc78 0x63340001 +0xc78 0x62350001 +0xc78 0x61360001 +0xc78 0x46370001 //0 +0xc78 0x45380001 +0xc78 0x44390001 +0xc78 0x433A0001 +0xc78 0x423B0001 +0xc78 0x413C0001 //10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 //16 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfb410001 +0xc78 0xfb420001 +0xc78 0xfb430001 +0xc78 0xfb440001 +0xc78 0xfb450001 //-100 +0xc78 0xfa460001 +0xc78 0xf9470001 +0xc78 0xf8480001 +0xc78 0xf7490001 +0xc78 0xf64a0001 //-90 +0xc78 0xf54b0001 +0xc78 0xf44c0001 +0xc78 0xf34d0001 +0xc78 0xf24e0001 +0xc78 0xf14f0001 //-80 +0xc78 0xf0500001 +0xc78 0xef510001 +0xc78 0xee520001 +0xc78 0xed530001 +0xc78 0xec540001 //-70 +0xc78 0xeb550001 +0xc78 0xea560001 +0xc78 0xe9570001 +0xc78 0xe8580001 +0xc78 0xe7590001 //-60 +0xc78 0xe65a0001 +0xc78 0xe55b0001 +0xc78 0xe45c0001 +0xc78 0xe35d0001 +0xc78 0xe25e0001 //-50 +0xc78 0xe15f0001 +0xc78 0x8a600001 +0xc78 0x89610001 +0xc78 0x88620001 +0xc78 0x87630001 //-40 +0xc78 0x86640001 +0xc78 0x85650001 +0xc78 0x84660001 +0xc78 0x83670001 +0xc78 0x82680001 //-30 +0xc78 0x6b690001 +0xc78 0x6a6a0001 +0xc78 0x696b0001 +0xc78 0x686c0001 +0xc78 0x676d0001 //-20 +0xc78 0x666e0001 +0xc78 0x656f0001 +0xc78 0x64700001 +0xc78 0x63710001 +0xc78 0x62720001 //-10 +0xc78 0x61730001 +0xc78 0x46740001 +0xc78 0x45750001 +0xc78 0x44760001 +0xc78 0x43770001 //0 +0xc78 0x42780001 +0xc78 0x41790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES.txt index a65c42cbdb4..aefb26101d4 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 / LTE blocking -0xc78 0xfb000001 //-110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfb040001 -0xc78 0xfb050001 //-100 -0xc78 0xfb060001 -0xc78 0xfb070001 -0xc78 0xfa080001 -0xc78 0xf9090001 -0xc78 0xf80A0001 //-90 -0xc78 0xf70B0001 -0xc78 0xf60C0001 -0xc78 0xf50D0001 -0xc78 0xf40E0001 -0xc78 0xf30F0001 //-80 -0xc78 0xf2100001 -0xc78 0xf1110001 -0xc78 0xf0120001 -0xc78 0xef130001 -0xc78 0xee140001 //-70 -0xc78 0xed150001 -0xc78 0xec160001 -0xc78 0xeb170001 -0xc78 0xea180001 -0xc78 0xe9190001 //-60 -0xc78 0xc81A0001 -0xc78 0xc71B0001 -0xc78 0xc61C0001 -0xc78 0x071D0001 -0xc78 0x061E0001 //-50 -0xc78 0x051F0001 -0xc78 0x04200001 -0xc78 0x03210001 -0xc78 0xaa220001 -0xc78 0xa9230001 //-40 -0xc78 0xa8240001 -0xc78 0xa7250001 -0xc78 0xa6260001 -0xc78 0x85270001 -0xc78 0x84280001 //-30 -0xc78 0x83290001 -0xc78 0x252A0001 -0xc78 0x242B0001 -0xc78 0x232C0001 -0xc78 0x222D0001 //-20 -0xc78 0x672E0001 -0xc78 0x662F0001 -0xc78 0x65300001 -0xc78 0x64310001 -0xc78 0x63320001 //-10 -0xc78 0x62330001 -0xc78 0x61340001 -0xc78 0x45350001 -0xc78 0x44360001 -0xc78 0x43370001 //0 -0xc78 0x42380001 -0xc78 0x41390001 -0xc78 0x403A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 //10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 //16 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfb410001 -0xc78 0xfb420001 -0xc78 0xfb430001 -0xc78 0xfb440001 -0xc78 0xfb450001 //-100 -0xc78 0xfa460001 -0xc78 0xf9470001 -0xc78 0xf8480001 -0xc78 0xf7490001 -0xc78 0xf64a0001 //-90 -0xc78 0xf54b0001 -0xc78 0xf44c0001 -0xc78 0xf34d0001 -0xc78 0xf24e0001 -0xc78 0xf14f0001 //-80 -0xc78 0xf0500001 -0xc78 0xef510001 -0xc78 0xee520001 -0xc78 0xed530001 -0xc78 0xec540001 //-70 -0xc78 0xeb550001 -0xc78 0xea560001 -0xc78 0xe9570001 -0xc78 0xe8580001 -0xc78 0xe7590001 //-60 -0xc78 0xe65a0001 -0xc78 0xe55b0001 -0xc78 0xe45c0001 -0xc78 0xe35d0001 -0xc78 0xe25e0001 //-50 -0xc78 0xe15f0001 -0xc78 0x8a600001 -0xc78 0x89610001 -0xc78 0x88620001 -0xc78 0x87630001 //-40 -0xc78 0x86640001 -0xc78 0x85650001 -0xc78 0x84660001 -0xc78 0x83670001 -0xc78 0x82680001 //-30 -0xc78 0x6b690001 -0xc78 0x6a6a0001 -0xc78 0x696b0001 -0xc78 0x686c0001 -0xc78 0x676d0001 //-20 -0xc78 0x666e0001 -0xc78 0x656f0001 -0xc78 0x64700001 -0xc78 0x63710001 -0xc78 0x62720001 //-10 -0xc78 0x61730001 -0xc78 0x49740001 -0xc78 0x48750001 -0xc78 0x47760001 -0xc78 0x46770001 //0 -0xc78 0x45780001 -0xc78 0x44790001 -0xc78 0x437a0001 -0xc78 0x427b0001 -0xc78 0x417c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040022 -0xc50 0x00040020 +//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 / LTE blocking +0xc78 0xfb000001 //-110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfb040001 +0xc78 0xfb050001 //-100 +0xc78 0xfb060001 +0xc78 0xfb070001 +0xc78 0xfa080001 +0xc78 0xf9090001 +0xc78 0xf80A0001 //-90 +0xc78 0xf70B0001 +0xc78 0xf60C0001 +0xc78 0xf50D0001 +0xc78 0xf40E0001 +0xc78 0xf30F0001 //-80 +0xc78 0xf2100001 +0xc78 0xf1110001 +0xc78 0xf0120001 +0xc78 0xef130001 +0xc78 0xee140001 //-70 +0xc78 0xed150001 +0xc78 0xec160001 +0xc78 0xeb170001 +0xc78 0xea180001 +0xc78 0xe9190001 //-60 +0xc78 0xc81A0001 +0xc78 0xc71B0001 +0xc78 0xc61C0001 +0xc78 0x071D0001 +0xc78 0x061E0001 //-50 +0xc78 0x051F0001 +0xc78 0x04200001 +0xc78 0x03210001 +0xc78 0xaa220001 +0xc78 0xa9230001 //-40 +0xc78 0xa8240001 +0xc78 0xa7250001 +0xc78 0xa6260001 +0xc78 0x85270001 +0xc78 0x84280001 //-30 +0xc78 0x83290001 +0xc78 0x252A0001 +0xc78 0x242B0001 +0xc78 0x232C0001 +0xc78 0x222D0001 //-20 +0xc78 0x672E0001 +0xc78 0x662F0001 +0xc78 0x65300001 +0xc78 0x64310001 +0xc78 0x63320001 //-10 +0xc78 0x62330001 +0xc78 0x61340001 +0xc78 0x45350001 +0xc78 0x44360001 +0xc78 0x43370001 //0 +0xc78 0x42380001 +0xc78 0x41390001 +0xc78 0x403A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 //10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 //16 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfb410001 +0xc78 0xfb420001 +0xc78 0xfb430001 +0xc78 0xfb440001 +0xc78 0xfb450001 //-100 +0xc78 0xfa460001 +0xc78 0xf9470001 +0xc78 0xf8480001 +0xc78 0xf7490001 +0xc78 0xf64a0001 //-90 +0xc78 0xf54b0001 +0xc78 0xf44c0001 +0xc78 0xf34d0001 +0xc78 0xf24e0001 +0xc78 0xf14f0001 //-80 +0xc78 0xf0500001 +0xc78 0xef510001 +0xc78 0xee520001 +0xc78 0xed530001 +0xc78 0xec540001 //-70 +0xc78 0xeb550001 +0xc78 0xea560001 +0xc78 0xe9570001 +0xc78 0xe8580001 +0xc78 0xe7590001 //-60 +0xc78 0xe65a0001 +0xc78 0xe55b0001 +0xc78 0xe45c0001 +0xc78 0xe35d0001 +0xc78 0xe25e0001 //-50 +0xc78 0xe15f0001 +0xc78 0x8a600001 +0xc78 0x89610001 +0xc78 0x88620001 +0xc78 0x87630001 //-40 +0xc78 0x86640001 +0xc78 0x85650001 +0xc78 0x84660001 +0xc78 0x83670001 +0xc78 0x82680001 //-30 +0xc78 0x6b690001 +0xc78 0x6a6a0001 +0xc78 0x696b0001 +0xc78 0x686c0001 +0xc78 0x676d0001 //-20 +0xc78 0x666e0001 +0xc78 0x656f0001 +0xc78 0x64700001 +0xc78 0x63710001 +0xc78 0x62720001 //-10 +0xc78 0x61730001 +0xc78 0x49740001 +0xc78 0x48750001 +0xc78 0x47760001 +0xc78 0x46770001 //0 +0xc78 0x45780001 +0xc78 0x44790001 +0xc78 0x437a0001 +0xc78 0x427b0001 +0xc78 0x417c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040022 +0xc50 0x00040020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES_extlna.txt index f74f6fc177e..fb2fa60e59f 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192ES_extlna.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0xc78 0xff400001 // -110 -0xc78 0xff410001 -0xc78 0xff420001 -0xc78 0xfe430001 -0xc78 0xfd440001 -0xc78 0xfc450001 // -100 -0xc78 0xfb460001 -0xc78 0xfa470001 -0xc78 0xf9480001 -0xc78 0xf8490001 -0xc78 0xf74a0001 // -90 -0xc78 0xf64b0001 -0xc78 0xf54c0001 -0xc78 0xf44d0001 -0xc78 0xf34e0001 -0xc78 0xf24f0001 // -80 -0xc78 0xf1500001 -0xc78 0xf0510001 -0xc78 0xef520001 -0xc78 0xee530001 -0xc78 0xed540001 // -70 -0xc78 0xec550001 -0xc78 0xeb560001 -0xc78 0xea570001 -0xc78 0xe9580001 -0xc78 0xe8590001 // -60 -0xc78 0xe75a0001 -0xc78 0xe65b0001 -0xc78 0xe55c0001 -0xc78 0xe45d0001 -0xc78 0xe35e0001 // -50 -0xc78 0x885f0001 -0xc78 0x87600001 -0xc78 0x86610001 -0xc78 0xaa620001 -0xc78 0xa9630001 // -40 -0xc78 0xa8640001 -0xc78 0xa7650001 -0xc78 0xa6660001 -0xc78 0x67670001 -0xc78 0x66680001 //-30 -0xc78 0x65690001 -0xc78 0x646a0001 -0xc78 0x636b0001 -0xc78 0x4b6c0001 -0xc78 0x4a6d0001 // -20 -0xc78 0x496e0001 -0xc78 0x486f0001 -0xc78 0x47700001 -0xc78 0x46710001 -0xc78 0x45720001 // -10 -0xc78 0x44730001 -0xc78 0x43740001 -0xc78 0x42750001 -0xc78 0x41760001 -0xc78 0x40770001 // 0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 // 10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 -// AGC_TABLE 2 for CS -0xc78 0xff400001 //-110 -0xc78 0xff410001 -0xc78 0xff420001 -0xc78 0xfe430001 -0xc78 0xfd440001 -0xc78 0xfc450001 //-100 -0xc78 0xfb460001 -0xc78 0xfa470001 -0xc78 0xf9480001 -0xc78 0xf8490001 -0xc78 0xf74a0001 //-90 -0xc78 0xf64b0001 -0xc78 0xf54c0001 -0xc78 0xf44d0001 -0xc78 0xf34e0001 -0xc78 0xf24f0001 //-80 -0xc78 0xf1500001 -0xc78 0xf0510001 -0xc78 0xef520001 -0xc78 0xee530001 -0xc78 0xed540001 //-70 -0xc78 0xec550001 -0xc78 0xeb560001 -0xc78 0xea570001 -0xc78 0xe9580001 -0xc78 0xe8590001 //-60 -0xc78 0xe75a0001 -0xc78 0xe65b0001 -0xc78 0xe55c0001 -0xc78 0xe45d0001 -0xc78 0xe35e0001 //-50 -0xc78 0x885f0001 -0xc78 0x87600001 -0xc78 0x86610001 -0xc78 0xaa620001 -0xc78 0xa9630001 //-40 -0xc78 0xa8640001 -0xc78 0xa7650001 -0xc78 0xa6660001 -0xc78 0x67670001 -0xc78 0x66680001 //-30 -0xc78 0x65690001 -0xc78 0x646a0001 -0xc78 0x636b0001 -0xc78 0x4b6c0001 -0xc78 0x4a6d0001 //-20 -0xc78 0x496e0001 -0xc78 0x486f0001 -0xc78 0x47700001 -0xc78 0x46710001 -0xc78 0x45720001 //-10 -0xc78 0x44730001 -0xc78 0x43740001 -0xc78 0x42750001 -0xc78 0x41760001 -0xc78 0x40770001 //0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 -0xffff 0xffff +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0xc78 0xff400001 // -110 +0xc78 0xff410001 +0xc78 0xff420001 +0xc78 0xfe430001 +0xc78 0xfd440001 +0xc78 0xfc450001 // -100 +0xc78 0xfb460001 +0xc78 0xfa470001 +0xc78 0xf9480001 +0xc78 0xf8490001 +0xc78 0xf74a0001 // -90 +0xc78 0xf64b0001 +0xc78 0xf54c0001 +0xc78 0xf44d0001 +0xc78 0xf34e0001 +0xc78 0xf24f0001 // -80 +0xc78 0xf1500001 +0xc78 0xf0510001 +0xc78 0xef520001 +0xc78 0xee530001 +0xc78 0xed540001 // -70 +0xc78 0xec550001 +0xc78 0xeb560001 +0xc78 0xea570001 +0xc78 0xe9580001 +0xc78 0xe8590001 // -60 +0xc78 0xe75a0001 +0xc78 0xe65b0001 +0xc78 0xe55c0001 +0xc78 0xe45d0001 +0xc78 0xe35e0001 // -50 +0xc78 0x885f0001 +0xc78 0x87600001 +0xc78 0x86610001 +0xc78 0xaa620001 +0xc78 0xa9630001 // -40 +0xc78 0xa8640001 +0xc78 0xa7650001 +0xc78 0xa6660001 +0xc78 0x67670001 +0xc78 0x66680001 //-30 +0xc78 0x65690001 +0xc78 0x646a0001 +0xc78 0x636b0001 +0xc78 0x4b6c0001 +0xc78 0x4a6d0001 // -20 +0xc78 0x496e0001 +0xc78 0x486f0001 +0xc78 0x47700001 +0xc78 0x46710001 +0xc78 0x45720001 // -10 +0xc78 0x44730001 +0xc78 0x43740001 +0xc78 0x42750001 +0xc78 0x41760001 +0xc78 0x40770001 // 0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 // 10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 +// AGC_TABLE 2 for CS +0xc78 0xff400001 //-110 +0xc78 0xff410001 +0xc78 0xff420001 +0xc78 0xfe430001 +0xc78 0xfd440001 +0xc78 0xfc450001 //-100 +0xc78 0xfb460001 +0xc78 0xfa470001 +0xc78 0xf9480001 +0xc78 0xf8490001 +0xc78 0xf74a0001 //-90 +0xc78 0xf64b0001 +0xc78 0xf54c0001 +0xc78 0xf44d0001 +0xc78 0xf34e0001 +0xc78 0xf24f0001 //-80 +0xc78 0xf1500001 +0xc78 0xf0510001 +0xc78 0xef520001 +0xc78 0xee530001 +0xc78 0xed540001 //-70 +0xc78 0xec550001 +0xc78 0xeb560001 +0xc78 0xea570001 +0xc78 0xe9580001 +0xc78 0xe8590001 //-60 +0xc78 0xe75a0001 +0xc78 0xe65b0001 +0xc78 0xe55c0001 +0xc78 0xe45d0001 +0xc78 0xe35e0001 //-50 +0xc78 0x885f0001 +0xc78 0x87600001 +0xc78 0x86610001 +0xc78 0xaa620001 +0xc78 0xa9630001 //-40 +0xc78 0xa8640001 +0xc78 0xa7650001 +0xc78 0xa6660001 +0xc78 0x67670001 +0xc78 0x66680001 //-30 +0xc78 0x65690001 +0xc78 0x646a0001 +0xc78 0x636b0001 +0xc78 0x4b6c0001 +0xc78 0x4a6d0001 //-20 +0xc78 0x496e0001 +0xc78 0x486f0001 +0xc78 0x47700001 +0xc78 0x46710001 +0xc78 0x45720001 //-10 +0xc78 0x44730001 +0xc78 0x43740001 +0xc78 0x42750001 +0xc78 0x41760001 +0xc78 0x40770001 //0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna.txt old mode 100755 new mode 100644 index 883178f1026..208f04e4276 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0xc78 0xfb000001 // -110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfb040001 -0xc78 0xfb050001 // -100 -0xc78 0xfb060001 -0xc78 0xfb070001 -0xc78 0xfa080001 -0xc78 0xf9090001 -0xc78 0xf80A0001 // -90 -0xc78 0xf70B0001 -0xc78 0xf60C0001 -0xc78 0xf50D0001 -0xc78 0xf40E0001 -0xc78 0xf30F0001 // -80 -0xc78 0xf2100001 -0xc78 0xf1110001 -0xc78 0xf0120001 -0xc78 0xef130001 -0xc78 0xee140001 // -70 -0xc78 0xed150001 -0xc78 0xec160001 -0xc78 0xeb170001 -0xc78 0xea180001 -0xc78 0xe9190001 // -60 -0xc78 0xe81A0001 -0xc78 0xe71B0001 -0xc78 0xe61C0001 -0xc78 0xe51D0001 -0xc78 0xe41E0001 // -50 -0xc78 0xe31F0001 -0xc78 0xe2200001 -0xc78 0xe1210001 -0xc78 0x8a220001 -0xc78 0x89230001 // -40 -0xc78 0x88240001 -0xc78 0x87250001 -0xc78 0x86260001 -0xc78 0x85270001 -0xc78 0x84280001 //-30 -0xc78 0x83290001 -0xc78 0x822A0001 -0xc78 0x6a2B0001 -0xc78 0x692C0001 -0xc78 0x682D0001 // -20 -0xc78 0x672E0001 -0xc78 0x662F0001 -0xc78 0x65300001 -0xc78 0x64310001 -0xc78 0x63320001 // -10 -0xc78 0x62330001 -0xc78 0x61340001 -0xc78 0x60350001 -0xc78 0x47360001 -0xc78 0x46370001 // 0 -0xc78 0x45380001 -0xc78 0x44390001 -0xc78 0x433A0001 -0xc78 0x423B0001 -0xc78 0x413C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfb410001 -0xc78 0xfb420001 -0xc78 0xfb430001 -0xc78 0xfb440001 -0xc78 0xfb450001 //-100 -0xc78 0xfb460001 -0xc78 0xfb470001 -0xc78 0xfa480001 -0xc78 0xf9490001 -0xc78 0xf84a0001 //-90 -0xc78 0xf74b0001 -0xc78 0xf64c0001 -0xc78 0xf54d0001 -0xc78 0xf44e0001 -0xc78 0xf34f0001 //-80 -0xc78 0xf2500001 -0xc78 0xf1510001 -0xc78 0xf0520001 -0xc78 0xef530001 -0xc78 0xee540001 //-70 -0xc78 0xed550001 -0xc78 0xec560001 -0xc78 0xeb570001 -0xc78 0xea580001 -0xc78 0xe9590001 //-60 -0xc78 0xe85a0001 -0xc78 0xe75b0001 -0xc78 0xe65c0001 -0xc78 0xe55d0001 -0xc78 0xe45e0001 //-50 -0xc78 0xe35f0001 -0xc78 0xe2600001 -0xc78 0xe1610001 -0xc78 0x8a620001 -0xc78 0x89630001 //-40 -0xc78 0x88640001 -0xc78 0x87650001 -0xc78 0x86660001 -0xc78 0x85670001 -0xc78 0x84680001 //-30 -0xc78 0x83690001 -0xc78 0x826a0001 -0xc78 0x6a6b0001 -0xc78 0x696c0001 -0xc78 0x686d0001 //-20 -0xc78 0x676e0001 -0xc78 0x666f0001 -0xc78 0x65700001 -0xc78 0x64710001 -0xc78 0x63720001 //-10 -0xc78 0x62730001 -0xc78 0x61740001 -0xc78 0x60750001 -0xc78 0x47760001 -0xc78 0x46770001 //0 -0xc78 0x45780001 -0xc78 0x44790001 -0xc78 0x437a0001 -0xc78 0x427b0001 -0xc78 0x417c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0xc78 0xfb000001 // -110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfb040001 +0xc78 0xfb050001 // -100 +0xc78 0xfb060001 +0xc78 0xfb070001 +0xc78 0xfa080001 +0xc78 0xf9090001 +0xc78 0xf80A0001 // -90 +0xc78 0xf70B0001 +0xc78 0xf60C0001 +0xc78 0xf50D0001 +0xc78 0xf40E0001 +0xc78 0xf30F0001 // -80 +0xc78 0xf2100001 +0xc78 0xf1110001 +0xc78 0xf0120001 +0xc78 0xef130001 +0xc78 0xee140001 // -70 +0xc78 0xed150001 +0xc78 0xec160001 +0xc78 0xeb170001 +0xc78 0xea180001 +0xc78 0xe9190001 // -60 +0xc78 0xe81A0001 +0xc78 0xe71B0001 +0xc78 0xe61C0001 +0xc78 0xe51D0001 +0xc78 0xe41E0001 // -50 +0xc78 0xe31F0001 +0xc78 0xe2200001 +0xc78 0xe1210001 +0xc78 0x8a220001 +0xc78 0x89230001 // -40 +0xc78 0x88240001 +0xc78 0x87250001 +0xc78 0x86260001 +0xc78 0x85270001 +0xc78 0x84280001 //-30 +0xc78 0x83290001 +0xc78 0x822A0001 +0xc78 0x6a2B0001 +0xc78 0x692C0001 +0xc78 0x682D0001 // -20 +0xc78 0x672E0001 +0xc78 0x662F0001 +0xc78 0x65300001 +0xc78 0x64310001 +0xc78 0x63320001 // -10 +0xc78 0x62330001 +0xc78 0x61340001 +0xc78 0x60350001 +0xc78 0x47360001 +0xc78 0x46370001 // 0 +0xc78 0x45380001 +0xc78 0x44390001 +0xc78 0x433A0001 +0xc78 0x423B0001 +0xc78 0x413C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfb410001 +0xc78 0xfb420001 +0xc78 0xfb430001 +0xc78 0xfb440001 +0xc78 0xfb450001 //-100 +0xc78 0xfb460001 +0xc78 0xfb470001 +0xc78 0xfa480001 +0xc78 0xf9490001 +0xc78 0xf84a0001 //-90 +0xc78 0xf74b0001 +0xc78 0xf64c0001 +0xc78 0xf54d0001 +0xc78 0xf44e0001 +0xc78 0xf34f0001 //-80 +0xc78 0xf2500001 +0xc78 0xf1510001 +0xc78 0xf0520001 +0xc78 0xef530001 +0xc78 0xee540001 //-70 +0xc78 0xed550001 +0xc78 0xec560001 +0xc78 0xeb570001 +0xc78 0xea580001 +0xc78 0xe9590001 //-60 +0xc78 0xe85a0001 +0xc78 0xe75b0001 +0xc78 0xe65c0001 +0xc78 0xe55d0001 +0xc78 0xe45e0001 //-50 +0xc78 0xe35f0001 +0xc78 0xe2600001 +0xc78 0xe1610001 +0xc78 0x8a620001 +0xc78 0x89630001 //-40 +0xc78 0x88640001 +0xc78 0x87650001 +0xc78 0x86660001 +0xc78 0x85670001 +0xc78 0x84680001 //-30 +0xc78 0x83690001 +0xc78 0x826a0001 +0xc78 0x6a6b0001 +0xc78 0x696c0001 +0xc78 0x686d0001 //-20 +0xc78 0x676e0001 +0xc78 0x666f0001 +0xc78 0x65700001 +0xc78 0x64710001 +0xc78 0x63720001 //-10 +0xc78 0x62730001 +0xc78 0x61740001 +0xc78 0x60750001 +0xc78 0x47760001 +0xc78 0x46770001 //0 +0xc78 0x45780001 +0xc78 0x44790001 +0xc78 0x437a0001 +0xc78 0x427b0001 +0xc78 0x417c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type1.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type1.txt old mode 100755 new mode 100644 index 7b37c4e9553..c89316d99d7 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type1.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type1.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 -0xc78 0xfb000001 // -110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfa040001 -0xc78 0xf9050001 // -100 -0xc78 0xf8060001 -0xc78 0xf7070001 -0xc78 0xf6080001 -0xc78 0xf5090001 -0xc78 0xf40A0001 // -90 -0xc78 0xf30B0001 -0xc78 0xf20C0001 -0xc78 0xf10D0001 -0xc78 0xf00E0001 -0xc78 0xef0F0001 // -80 -0xc78 0xee100001 -0xc78 0xed110001 -0xc78 0xec120001 -0xc78 0xeb130001 -0xc78 0xea140001 // -70 -0xc78 0xe9150001 -0xc78 0xe8160001 -0xc78 0xe7170001 -0xc78 0xe6180001 -0xc78 0xe5190001 // -60 -0xc78 0xe41A0001 -0xc78 0xe31B0001 -0xc78 0xe21C0001 -0xc78 0xe11D0001 -0xc78 0x8a1E0001 // -50 -0xc78 0x891F0001 -0xc78 0x88200001 -0xc78 0x87210001 -0xc78 0x86220001 -0xc78 0x85230001 // -40 -0xc78 0x84240001 -0xc78 0x83250001 -0xc78 0x82260001 -0xc78 0x6a270001 -0xc78 0x69280001 //-30 -0xc78 0x68290001 -0xc78 0x672A0001 -0xc78 0x662B0001 -0xc78 0x652C0001 -0xc78 0x642D0001 // -20 -0xc78 0x632E0001 -0xc78 0x622F0001 -0xc78 0x61300001 -0xc78 0x60310001 -0xc78 0x47320001 // -10 -0xc78 0x46330001 -0xc78 0x45340001 -0xc78 0x44350001 -0xc78 0x43360001 -0xc78 0x42370001 // 0 -0xc78 0x41380001 -0xc78 0x40390001 -0xc78 0x403A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xfe400001 //-110 -0xc78 0xfe410001 -0xc78 0xfe420001 -0xc78 0xfd430001 -0xc78 0xfc440001 -0xc78 0xfb450001 //-100 -0xc78 0xfa460001 -0xc78 0xf9470001 -0xc78 0xf8480001 -0xc78 0xf7490001 -0xc78 0xf64a0001 //-90 -0xc78 0xf54b0001 -0xc78 0xf44c0001 -0xc78 0xf34d0001 -0xc78 0xf24e0001 -0xc78 0xf14f0001 //-80 -0xc78 0xf0500001 -0xc78 0xef510001 -0xc78 0xee520001 -0xc78 0xed530001 -0xc78 0xec540001 //-70 -0xc78 0xeb550001 -0xc78 0xea560001 -0xc78 0xe9570001 -0xc78 0xe8580001 -0xc78 0xe7590001 //-60 -0xc78 0xe65a0001 -0xc78 0xe55b0001 -0xc78 0xe45c0001 -0xc78 0xe35d0001 -0xc78 0x885e0001 //-50 -0xc78 0x875f0001 -0xc78 0xaa600001 -0xc78 0xa9610001 -0xc78 0xa8620001 -0xc78 0xa7630001 //-40 -0xc78 0xa6640001 -0xc78 0xa5650001 -0xc78 0x66660001 -0xc78 0x65670001 -0xc78 0x64680001 //-30 -0xc78 0x63690001 -0xc78 0x626a0001 -0xc78 0x496b0001 -0xc78 0x486c0001 -0xc78 0x476d0001 //-20 -0xc78 0x466e0001 -0xc78 0x456f0001 -0xc78 0x44700001 -0xc78 0x43710001 -0xc78 0x42720001 //-10 -0xc78 0x41730001 -0xc78 0x40740001 -0xc78 0x40750001 -0xc78 0x40760001 -0xc78 0x40770001 //0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040220 -0xc58 0x00000220 +//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 +0xc78 0xfb000001 // -110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfa040001 +0xc78 0xf9050001 // -100 +0xc78 0xf8060001 +0xc78 0xf7070001 +0xc78 0xf6080001 +0xc78 0xf5090001 +0xc78 0xf40A0001 // -90 +0xc78 0xf30B0001 +0xc78 0xf20C0001 +0xc78 0xf10D0001 +0xc78 0xf00E0001 +0xc78 0xef0F0001 // -80 +0xc78 0xee100001 +0xc78 0xed110001 +0xc78 0xec120001 +0xc78 0xeb130001 +0xc78 0xea140001 // -70 +0xc78 0xe9150001 +0xc78 0xe8160001 +0xc78 0xe7170001 +0xc78 0xe6180001 +0xc78 0xe5190001 // -60 +0xc78 0xe41A0001 +0xc78 0xe31B0001 +0xc78 0xe21C0001 +0xc78 0xe11D0001 +0xc78 0x8a1E0001 // -50 +0xc78 0x891F0001 +0xc78 0x88200001 +0xc78 0x87210001 +0xc78 0x86220001 +0xc78 0x85230001 // -40 +0xc78 0x84240001 +0xc78 0x83250001 +0xc78 0x82260001 +0xc78 0x6a270001 +0xc78 0x69280001 //-30 +0xc78 0x68290001 +0xc78 0x672A0001 +0xc78 0x662B0001 +0xc78 0x652C0001 +0xc78 0x642D0001 // -20 +0xc78 0x632E0001 +0xc78 0x622F0001 +0xc78 0x61300001 +0xc78 0x60310001 +0xc78 0x47320001 // -10 +0xc78 0x46330001 +0xc78 0x45340001 +0xc78 0x44350001 +0xc78 0x43360001 +0xc78 0x42370001 // 0 +0xc78 0x41380001 +0xc78 0x40390001 +0xc78 0x403A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xfe400001 //-110 +0xc78 0xfe410001 +0xc78 0xfe420001 +0xc78 0xfd430001 +0xc78 0xfc440001 +0xc78 0xfb450001 //-100 +0xc78 0xfa460001 +0xc78 0xf9470001 +0xc78 0xf8480001 +0xc78 0xf7490001 +0xc78 0xf64a0001 //-90 +0xc78 0xf54b0001 +0xc78 0xf44c0001 +0xc78 0xf34d0001 +0xc78 0xf24e0001 +0xc78 0xf14f0001 //-80 +0xc78 0xf0500001 +0xc78 0xef510001 +0xc78 0xee520001 +0xc78 0xed530001 +0xc78 0xec540001 //-70 +0xc78 0xeb550001 +0xc78 0xea560001 +0xc78 0xe9570001 +0xc78 0xe8580001 +0xc78 0xe7590001 //-60 +0xc78 0xe65a0001 +0xc78 0xe55b0001 +0xc78 0xe45c0001 +0xc78 0xe35d0001 +0xc78 0x885e0001 //-50 +0xc78 0x875f0001 +0xc78 0xaa600001 +0xc78 0xa9610001 +0xc78 0xa8620001 +0xc78 0xa7630001 //-40 +0xc78 0xa6640001 +0xc78 0xa5650001 +0xc78 0x66660001 +0xc78 0x65670001 +0xc78 0x64680001 //-30 +0xc78 0x63690001 +0xc78 0x626a0001 +0xc78 0x496b0001 +0xc78 0x486c0001 +0xc78 0x476d0001 //-20 +0xc78 0x466e0001 +0xc78 0x456f0001 +0xc78 0x44700001 +0xc78 0x43710001 +0xc78 0x42720001 //-10 +0xc78 0x41730001 +0xc78 0x40740001 +0xc78 0x40750001 +0xc78 0x40760001 +0xc78 0x40770001 //0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040220 +0xc58 0x00000220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type2.txt old mode 100755 new mode 100644 index 9216ab18b13..01bbb221b97 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type2.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v039_MP_20141027 -0xc78 0xfb000001 // -110 -0xc78 0xfb010001 -0xc78 0xfa020001 -0xc78 0xf9030001 -0xc78 0xf8040001 -0xc78 0xf7050001 // -100 -0xc78 0xf6060001 -0xc78 0xf5070001 -0xc78 0xf4080001 -0xc78 0xf3090001 -0xc78 0xf20A0001 // -90 -0xc78 0xf10B0001 -0xc78 0xf00C0001 -0xc78 0xef0D0001 -0xc78 0xee0E0001 -0xc78 0xed0F0001 // -80 -0xc78 0xec100001 -0xc78 0xeb110001 -0xc78 0xea120001 -0xc78 0xe9130001 -0xc78 0xe8140001 // -70 -0xc78 0xe7150001 -0xc78 0xe6160001 -0xc78 0xe5170001 -0xc78 0xe4180001 -0xc78 0xe3190001 // -60 -0xc78 0xe21A0001 -0xc78 0xe11B0001 -0xc78 0x8a1C0001 -0xc78 0x891D0001 -0xc78 0x881E0001 // -50 -0xc78 0x871F0001 -0xc78 0x86200001 -0xc78 0x85210001 -0xc78 0x84220001 -0xc78 0x83230001 // -40 -0xc78 0x82240001 -0xc78 0x6a250001 -0xc78 0x69260001 -0xc78 0x68270001 -0xc78 0x67280001 //-30 -0xc78 0x66290001 -0xc78 0x652A0001 -0xc78 0x642B0001 -0xc78 0x632C0001 -0xc78 0x622D0001 // -20 -0xc78 0x612E0001 -0xc78 0x602F0001 -0xc78 0x47300001 -0xc78 0x46310001 -0xc78 0x45320001 // -10 -0xc78 0x44330001 -0xc78 0x43340001 -0xc78 0x42350001 -0xc78 0x41360001 -0xc78 0x40370001 // 0 -0xc78 0x40380001 -0xc78 0x40390001 -0xc78 0x403A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xfa400001 //-110 -0xc78 0xf9410001 -0xc78 0xf8420001 -0xc78 0xf7430001 -0xc78 0xf6440001 -0xc78 0xf5450001 //-100 -0xc78 0xf4460001 -0xc78 0xf3470001 -0xc78 0xf2480001 -0xc78 0xf1490001 -0xc78 0xf04a0001 //-90 -0xc78 0xef4b0001 -0xc78 0xee4c0001 -0xc78 0xed4d0001 -0xc78 0xec4e0001 -0xc78 0xeb4f0001 //-80 -0xc78 0xea500001 -0xc78 0xce510001 -0xc78 0xcd520001 -0xc78 0xcc530001 -0xc78 0xcb540001 //-70 -0xc78 0xca550001 -0xc78 0xc9560001 -0xc78 0xc8570001 -0xc78 0xc7580001 -0xc78 0xc6590001 //-60 -0xc78 0xc55a0001 -0xc78 0xc45b0001 -0xc78 0xc35c0001 -0xc78 0x885d0001 -0xc78 0x875e0001 //-50 -0xc78 0x865f0001 -0xc78 0x85600001 -0xc78 0x84610001 -0xc78 0x6b620001 -0xc78 0x6a630001 //-40 -0xc78 0x69640001 -0xc78 0x68650001 -0xc78 0x67660001 -0xc78 0x66670001 -0xc78 0x65680001 //-30 -0xc78 0x64690001 -0xc78 0x636a0001 -0xc78 0x4a6b0001 -0xc78 0x496c0001 -0xc78 0x486d0001 //-20 -0xc78 0x476e0001 -0xc78 0x466f0001 -0xc78 0x45700001 -0xc78 0x44710001 -0xc78 0x43720001 //-10 -0xc78 0x42730001 -0xc78 0x41740001 -0xc78 0x40750001 -0xc78 0x40760001 -0xc78 0x40770001 //0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 +//RTL8192E_MAC_PHY_Parameter_v039_MP_20141027 +0xc78 0xfb000001 // -110 +0xc78 0xfb010001 +0xc78 0xfa020001 +0xc78 0xf9030001 +0xc78 0xf8040001 +0xc78 0xf7050001 // -100 +0xc78 0xf6060001 +0xc78 0xf5070001 +0xc78 0xf4080001 +0xc78 0xf3090001 +0xc78 0xf20A0001 // -90 +0xc78 0xf10B0001 +0xc78 0xf00C0001 +0xc78 0xef0D0001 +0xc78 0xee0E0001 +0xc78 0xed0F0001 // -80 +0xc78 0xec100001 +0xc78 0xeb110001 +0xc78 0xea120001 +0xc78 0xe9130001 +0xc78 0xe8140001 // -70 +0xc78 0xe7150001 +0xc78 0xe6160001 +0xc78 0xe5170001 +0xc78 0xe4180001 +0xc78 0xe3190001 // -60 +0xc78 0xe21A0001 +0xc78 0xe11B0001 +0xc78 0x8a1C0001 +0xc78 0x891D0001 +0xc78 0x881E0001 // -50 +0xc78 0x871F0001 +0xc78 0x86200001 +0xc78 0x85210001 +0xc78 0x84220001 +0xc78 0x83230001 // -40 +0xc78 0x82240001 +0xc78 0x6a250001 +0xc78 0x69260001 +0xc78 0x68270001 +0xc78 0x67280001 //-30 +0xc78 0x66290001 +0xc78 0x652A0001 +0xc78 0x642B0001 +0xc78 0x632C0001 +0xc78 0x622D0001 // -20 +0xc78 0x612E0001 +0xc78 0x602F0001 +0xc78 0x47300001 +0xc78 0x46310001 +0xc78 0x45320001 // -10 +0xc78 0x44330001 +0xc78 0x43340001 +0xc78 0x42350001 +0xc78 0x41360001 +0xc78 0x40370001 // 0 +0xc78 0x40380001 +0xc78 0x40390001 +0xc78 0x403A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xfa400001 //-110 +0xc78 0xf9410001 +0xc78 0xf8420001 +0xc78 0xf7430001 +0xc78 0xf6440001 +0xc78 0xf5450001 //-100 +0xc78 0xf4460001 +0xc78 0xf3470001 +0xc78 0xf2480001 +0xc78 0xf1490001 +0xc78 0xf04a0001 //-90 +0xc78 0xef4b0001 +0xc78 0xee4c0001 +0xc78 0xed4d0001 +0xc78 0xec4e0001 +0xc78 0xeb4f0001 //-80 +0xc78 0xea500001 +0xc78 0xce510001 +0xc78 0xcd520001 +0xc78 0xcc530001 +0xc78 0xcb540001 //-70 +0xc78 0xca550001 +0xc78 0xc9560001 +0xc78 0xc8570001 +0xc78 0xc7580001 +0xc78 0xc6590001 //-60 +0xc78 0xc55a0001 +0xc78 0xc45b0001 +0xc78 0xc35c0001 +0xc78 0x885d0001 +0xc78 0x875e0001 //-50 +0xc78 0x865f0001 +0xc78 0x85600001 +0xc78 0x84610001 +0xc78 0x6b620001 +0xc78 0x6a630001 //-40 +0xc78 0x69640001 +0xc78 0x68650001 +0xc78 0x67660001 +0xc78 0x66670001 +0xc78 0x65680001 //-30 +0xc78 0x64690001 +0xc78 0x636a0001 +0xc78 0x4a6b0001 +0xc78 0x496c0001 +0xc78 0x486d0001 //-20 +0xc78 0x476e0001 +0xc78 0x466f0001 +0xc78 0x45700001 +0xc78 0x44710001 +0xc78 0x43720001 //-10 +0xc78 0x42730001 +0xc78 0x41740001 +0xc78 0x40750001 +0xc78 0x40760001 +0xc78 0x40770001 //0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type3.txt old mode 100755 new mode 100644 index 8913c06e701..b4af4f314f9 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extlna_type3.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v039_MP_20141027 -0xc78 0xfb000001 // -110 -0xc78 0xfb010001 -0xc78 0xfa020001 -0xc78 0xf9030001 -0xc78 0xf8040001 -0xc78 0xf7050001 // -100 -0xc78 0xf6060001 -0xc78 0xf5070001 -0xc78 0xf4080001 -0xc78 0xf3090001 -0xc78 0xf20A0001 // -90 -0xc78 0xf10B0001 -0xc78 0xf00C0001 -0xc78 0xef0D0001 -0xc78 0xee0E0001 -0xc78 0xed0F0001 // -80 -0xc78 0xec100001 -0xc78 0xeb110001 -0xc78 0xea120001 -0xc78 0xe9130001 -0xc78 0xe8140001 // -70 -0xc78 0xe7150001 -0xc78 0xe6160001 -0xc78 0xe5170001 -0xc78 0xe4180001 -0xc78 0xe3190001 // -60 -0xc78 0xe21A0001 -0xc78 0xe11B0001 -0xc78 0x8a1C0001 -0xc78 0x891D0001 -0xc78 0x881E0001 // -50 -0xc78 0x871F0001 -0xc78 0x86200001 -0xc78 0x85210001 -0xc78 0x84220001 -0xc78 0x83230001 // -40 -0xc78 0x82240001 -0xc78 0x6a250001 -0xc78 0x69260001 -0xc78 0x68270001 -0xc78 0x67280001 //-30 -0xc78 0x66290001 -0xc78 0x652A0001 -0xc78 0x642B0001 -0xc78 0x632C0001 -0xc78 0x622D0001 // -20 -0xc78 0x612E0001 -0xc78 0x602F0001 -0xc78 0x47300001 -0xc78 0x46310001 -0xc78 0x45320001 // -10 -0xc78 0x44330001 -0xc78 0x43340001 -0xc78 0x42350001 -0xc78 0x41360001 -0xc78 0x40370001 // 0 -0xc78 0x40380001 -0xc78 0x40390001 -0xc78 0x403A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfa410001 -0xc78 0xf9420001 -0xc78 0xf8430001 -0xc78 0xf7440001 -0xc78 0xf6450001 //-100 -0xc78 0xf5460001 -0xc78 0xf4470001 -0xc78 0xf3480001 -0xc78 0xf2490001 -0xc78 0xf14a0001 //-90 -0xc78 0xf04b0001 -0xc78 0xef4c0001 -0xc78 0xee4d0001 -0xc78 0xed4e0001 -0xc78 0xec4f0001 //-80 -0xc78 0xeb500001 -0xc78 0xea510001 -0xc78 0xce520001 -0xc78 0xcd530001 -0xc78 0xcc540001 //-70 -0xc78 0xcb550001 -0xc78 0xca560001 -0xc78 0xc9570001 -0xc78 0xc8580001 -0xc78 0xc7590001 //-60 -0xc78 0xc65a0001 -0xc78 0xc55b0001 -0xc78 0xc45c0001 -0xc78 0xc35d0001 -0xc78 0x885e0001 //-50 -0xc78 0x875f0001 -0xc78 0x86600001 -0xc78 0x85610001 -0xc78 0x84620001 -0xc78 0x6b630001 //-40 -0xc78 0x6a640001 -0xc78 0x69650001 -0xc78 0x68660001 -0xc78 0x67670001 -0xc78 0x66680001 //-30 -0xc78 0x65690001 -0xc78 0x646a0001 -0xc78 0x636b0001 -0xc78 0x4a6c0001 -0xc78 0x496d0001 //-20 -0xc78 0x486e0001 -0xc78 0x476f0001 -0xc78 0x46700001 -0xc78 0x45710001 -0xc78 0x44720001 //-10 -0xc78 0x43730001 -0xc78 0x42740001 -0xc78 0x41750001 -0xc78 0x40760001 -0xc78 0x40770001 //0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 +//RTL8192E_MAC_PHY_Parameter_v039_MP_20141027 +0xc78 0xfb000001 // -110 +0xc78 0xfb010001 +0xc78 0xfa020001 +0xc78 0xf9030001 +0xc78 0xf8040001 +0xc78 0xf7050001 // -100 +0xc78 0xf6060001 +0xc78 0xf5070001 +0xc78 0xf4080001 +0xc78 0xf3090001 +0xc78 0xf20A0001 // -90 +0xc78 0xf10B0001 +0xc78 0xf00C0001 +0xc78 0xef0D0001 +0xc78 0xee0E0001 +0xc78 0xed0F0001 // -80 +0xc78 0xec100001 +0xc78 0xeb110001 +0xc78 0xea120001 +0xc78 0xe9130001 +0xc78 0xe8140001 // -70 +0xc78 0xe7150001 +0xc78 0xe6160001 +0xc78 0xe5170001 +0xc78 0xe4180001 +0xc78 0xe3190001 // -60 +0xc78 0xe21A0001 +0xc78 0xe11B0001 +0xc78 0x8a1C0001 +0xc78 0x891D0001 +0xc78 0x881E0001 // -50 +0xc78 0x871F0001 +0xc78 0x86200001 +0xc78 0x85210001 +0xc78 0x84220001 +0xc78 0x83230001 // -40 +0xc78 0x82240001 +0xc78 0x6a250001 +0xc78 0x69260001 +0xc78 0x68270001 +0xc78 0x67280001 //-30 +0xc78 0x66290001 +0xc78 0x652A0001 +0xc78 0x642B0001 +0xc78 0x632C0001 +0xc78 0x622D0001 // -20 +0xc78 0x612E0001 +0xc78 0x602F0001 +0xc78 0x47300001 +0xc78 0x46310001 +0xc78 0x45320001 // -10 +0xc78 0x44330001 +0xc78 0x43340001 +0xc78 0x42350001 +0xc78 0x41360001 +0xc78 0x40370001 // 0 +0xc78 0x40380001 +0xc78 0x40390001 +0xc78 0x403A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfa410001 +0xc78 0xf9420001 +0xc78 0xf8430001 +0xc78 0xf7440001 +0xc78 0xf6450001 //-100 +0xc78 0xf5460001 +0xc78 0xf4470001 +0xc78 0xf3480001 +0xc78 0xf2490001 +0xc78 0xf14a0001 //-90 +0xc78 0xf04b0001 +0xc78 0xef4c0001 +0xc78 0xee4d0001 +0xc78 0xed4e0001 +0xc78 0xec4f0001 //-80 +0xc78 0xeb500001 +0xc78 0xea510001 +0xc78 0xce520001 +0xc78 0xcd530001 +0xc78 0xcc540001 //-70 +0xc78 0xcb550001 +0xc78 0xca560001 +0xc78 0xc9570001 +0xc78 0xc8580001 +0xc78 0xc7590001 //-60 +0xc78 0xc65a0001 +0xc78 0xc55b0001 +0xc78 0xc45c0001 +0xc78 0xc35d0001 +0xc78 0x885e0001 //-50 +0xc78 0x875f0001 +0xc78 0x86600001 +0xc78 0x85610001 +0xc78 0x84620001 +0xc78 0x6b630001 //-40 +0xc78 0x6a640001 +0xc78 0x69650001 +0xc78 0x68660001 +0xc78 0x67670001 +0xc78 0x66680001 //-30 +0xc78 0x65690001 +0xc78 0x646a0001 +0xc78 0x636b0001 +0xc78 0x4a6c0001 +0xc78 0x496d0001 //-20 +0xc78 0x486e0001 +0xc78 0x476f0001 +0xc78 0x46700001 +0xc78 0x45710001 +0xc78 0x44720001 //-10 +0xc78 0x43730001 +0xc78 0x42740001 +0xc78 0x41750001 +0xc78 0x40760001 +0xc78 0x40770001 //0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extpa.txt old mode 100755 new mode 100644 index 883178f1026..208f04e4276 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_extpa.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0xc78 0xfb000001 // -110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfb040001 -0xc78 0xfb050001 // -100 -0xc78 0xfb060001 -0xc78 0xfb070001 -0xc78 0xfa080001 -0xc78 0xf9090001 -0xc78 0xf80A0001 // -90 -0xc78 0xf70B0001 -0xc78 0xf60C0001 -0xc78 0xf50D0001 -0xc78 0xf40E0001 -0xc78 0xf30F0001 // -80 -0xc78 0xf2100001 -0xc78 0xf1110001 -0xc78 0xf0120001 -0xc78 0xef130001 -0xc78 0xee140001 // -70 -0xc78 0xed150001 -0xc78 0xec160001 -0xc78 0xeb170001 -0xc78 0xea180001 -0xc78 0xe9190001 // -60 -0xc78 0xe81A0001 -0xc78 0xe71B0001 -0xc78 0xe61C0001 -0xc78 0xe51D0001 -0xc78 0xe41E0001 // -50 -0xc78 0xe31F0001 -0xc78 0xe2200001 -0xc78 0xe1210001 -0xc78 0x8a220001 -0xc78 0x89230001 // -40 -0xc78 0x88240001 -0xc78 0x87250001 -0xc78 0x86260001 -0xc78 0x85270001 -0xc78 0x84280001 //-30 -0xc78 0x83290001 -0xc78 0x822A0001 -0xc78 0x6a2B0001 -0xc78 0x692C0001 -0xc78 0x682D0001 // -20 -0xc78 0x672E0001 -0xc78 0x662F0001 -0xc78 0x65300001 -0xc78 0x64310001 -0xc78 0x63320001 // -10 -0xc78 0x62330001 -0xc78 0x61340001 -0xc78 0x60350001 -0xc78 0x47360001 -0xc78 0x46370001 // 0 -0xc78 0x45380001 -0xc78 0x44390001 -0xc78 0x433A0001 -0xc78 0x423B0001 -0xc78 0x413C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfb410001 -0xc78 0xfb420001 -0xc78 0xfb430001 -0xc78 0xfb440001 -0xc78 0xfb450001 //-100 -0xc78 0xfb460001 -0xc78 0xfb470001 -0xc78 0xfa480001 -0xc78 0xf9490001 -0xc78 0xf84a0001 //-90 -0xc78 0xf74b0001 -0xc78 0xf64c0001 -0xc78 0xf54d0001 -0xc78 0xf44e0001 -0xc78 0xf34f0001 //-80 -0xc78 0xf2500001 -0xc78 0xf1510001 -0xc78 0xf0520001 -0xc78 0xef530001 -0xc78 0xee540001 //-70 -0xc78 0xed550001 -0xc78 0xec560001 -0xc78 0xeb570001 -0xc78 0xea580001 -0xc78 0xe9590001 //-60 -0xc78 0xe85a0001 -0xc78 0xe75b0001 -0xc78 0xe65c0001 -0xc78 0xe55d0001 -0xc78 0xe45e0001 //-50 -0xc78 0xe35f0001 -0xc78 0xe2600001 -0xc78 0xe1610001 -0xc78 0x8a620001 -0xc78 0x89630001 //-40 -0xc78 0x88640001 -0xc78 0x87650001 -0xc78 0x86660001 -0xc78 0x85670001 -0xc78 0x84680001 //-30 -0xc78 0x83690001 -0xc78 0x826a0001 -0xc78 0x6a6b0001 -0xc78 0x696c0001 -0xc78 0x686d0001 //-20 -0xc78 0x676e0001 -0xc78 0x666f0001 -0xc78 0x65700001 -0xc78 0x64710001 -0xc78 0x63720001 //-10 -0xc78 0x62730001 -0xc78 0x61740001 -0xc78 0x60750001 -0xc78 0x47760001 -0xc78 0x46770001 //0 -0xc78 0x45780001 -0xc78 0x44790001 -0xc78 0x437a0001 -0xc78 0x427b0001 -0xc78 0x417c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0xc78 0xfb000001 // -110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfb040001 +0xc78 0xfb050001 // -100 +0xc78 0xfb060001 +0xc78 0xfb070001 +0xc78 0xfa080001 +0xc78 0xf9090001 +0xc78 0xf80A0001 // -90 +0xc78 0xf70B0001 +0xc78 0xf60C0001 +0xc78 0xf50D0001 +0xc78 0xf40E0001 +0xc78 0xf30F0001 // -80 +0xc78 0xf2100001 +0xc78 0xf1110001 +0xc78 0xf0120001 +0xc78 0xef130001 +0xc78 0xee140001 // -70 +0xc78 0xed150001 +0xc78 0xec160001 +0xc78 0xeb170001 +0xc78 0xea180001 +0xc78 0xe9190001 // -60 +0xc78 0xe81A0001 +0xc78 0xe71B0001 +0xc78 0xe61C0001 +0xc78 0xe51D0001 +0xc78 0xe41E0001 // -50 +0xc78 0xe31F0001 +0xc78 0xe2200001 +0xc78 0xe1210001 +0xc78 0x8a220001 +0xc78 0x89230001 // -40 +0xc78 0x88240001 +0xc78 0x87250001 +0xc78 0x86260001 +0xc78 0x85270001 +0xc78 0x84280001 //-30 +0xc78 0x83290001 +0xc78 0x822A0001 +0xc78 0x6a2B0001 +0xc78 0x692C0001 +0xc78 0x682D0001 // -20 +0xc78 0x672E0001 +0xc78 0x662F0001 +0xc78 0x65300001 +0xc78 0x64310001 +0xc78 0x63320001 // -10 +0xc78 0x62330001 +0xc78 0x61340001 +0xc78 0x60350001 +0xc78 0x47360001 +0xc78 0x46370001 // 0 +0xc78 0x45380001 +0xc78 0x44390001 +0xc78 0x433A0001 +0xc78 0x423B0001 +0xc78 0x413C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfb410001 +0xc78 0xfb420001 +0xc78 0xfb430001 +0xc78 0xfb440001 +0xc78 0xfb450001 //-100 +0xc78 0xfb460001 +0xc78 0xfb470001 +0xc78 0xfa480001 +0xc78 0xf9490001 +0xc78 0xf84a0001 //-90 +0xc78 0xf74b0001 +0xc78 0xf64c0001 +0xc78 0xf54d0001 +0xc78 0xf44e0001 +0xc78 0xf34f0001 //-80 +0xc78 0xf2500001 +0xc78 0xf1510001 +0xc78 0xf0520001 +0xc78 0xef530001 +0xc78 0xee540001 //-70 +0xc78 0xed550001 +0xc78 0xec560001 +0xc78 0xeb570001 +0xc78 0xea580001 +0xc78 0xe9590001 //-60 +0xc78 0xe85a0001 +0xc78 0xe75b0001 +0xc78 0xe65c0001 +0xc78 0xe55d0001 +0xc78 0xe45e0001 //-50 +0xc78 0xe35f0001 +0xc78 0xe2600001 +0xc78 0xe1610001 +0xc78 0x8a620001 +0xc78 0x89630001 //-40 +0xc78 0x88640001 +0xc78 0x87650001 +0xc78 0x86660001 +0xc78 0x85670001 +0xc78 0x84680001 //-30 +0xc78 0x83690001 +0xc78 0x826a0001 +0xc78 0x6a6b0001 +0xc78 0x696c0001 +0xc78 0x686d0001 //-20 +0xc78 0x676e0001 +0xc78 0x666f0001 +0xc78 0x65700001 +0xc78 0x64710001 +0xc78 0x63720001 //-10 +0xc78 0x62730001 +0xc78 0x61740001 +0xc78 0x60750001 +0xc78 0x47760001 +0xc78 0x46770001 //0 +0xc78 0x45780001 +0xc78 0x44790001 +0xc78 0x437a0001 +0xc78 0x427b0001 +0xc78 0x417c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_hp.txt old mode 100755 new mode 100644 index 476bdd1932c..9cace0d380a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192E_hp.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0xc78 0xff000001 // -110 -0xc78 0xff010001 -0xc78 0xff020001 -0xc78 0xff030001 -0xc78 0xff040001 -0xc78 0xfe050001 // -100 -0xc78 0xfd060001 -0xc78 0xfc070001 -0xc78 0xfb080001 -0xc78 0xfa090001 -0xc78 0xf90A0001 // -90 -0xc78 0xf80B0001 -0xc78 0xf70C0001 -0xc78 0xf60D0001 -0xc78 0xf50E0001 -0xc78 0xf40F0001 // -80 -0xc78 0xf3100001 -0xc78 0xf2110001 -0xc78 0xf1120001 -0xc78 0xf0130001 -0xc78 0xef140001 // -70 -0xc78 0xee150001 -0xc78 0xed160001 -0xc78 0xec170001 -0xc78 0xeb180001 -0xc78 0xea190001 // -60 -0xc78 0xe91A0001 -0xc78 0xe81B0001 -0xc78 0xe71C0001 -0xc78 0xe61D0001 -0xc78 0xe51E0001 // -50 -0xc78 0x891F0001 -0xc78 0x88200001 -0xc78 0x87210001 -0xc78 0x86220001 -0xc78 0xa9230001 // -40 -0xc78 0xa8240001 -0xc78 0x6a250001 -0xc78 0x69260001 -0xc78 0x68270001 -0xc78 0x67280001 //-30 -0xc78 0x66290001 -0xc78 0x652A0001 -0xc78 0x642B0001 -0xc78 0x4a2C0001 -0xc78 0x492D0001 // -20 -0xc78 0x482E0001 -0xc78 0x472F0001 -0xc78 0x46300001 -0xc78 0x45310001 -0xc78 0x44320001 // -10 -0xc78 0x43330001 -0xc78 0x42340001 -0xc78 0x41350001 -0xc78 0x40360001 -0xc78 0x40370001 // 0 -0xc78 0x40380001 -0xc78 0x40390001 -0xc78 0x403A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 // 10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 -// AGC_TABLE 2 for CS -0xc78 0xff400001 //-110 -0xc78 0xff410001 -0xc78 0xfe420001 -0xc78 0xfd430001 -0xc78 0xfc440001 -0xc78 0xfb450001 //-100 -0xc78 0xfa460001 -0xc78 0xf9470001 -0xc78 0xf8480001 -0xc78 0xf7490001 -0xc78 0xf64a0001 //-90 -0xc78 0xf54b0001 -0xc78 0xf44c0001 -0xc78 0xf34d0001 -0xc78 0xf24e0001 -0xc78 0xf14f0001 //-80 -0xc78 0xf0500001 -0xc78 0xef510001 -0xc78 0xee520001 -0xc78 0xed530001 -0xc78 0xec540001 //-70 -0xc78 0xeb550001 -0xc78 0xea560001 -0xc78 0xe9570001 -0xc78 0xe8580001 -0xc78 0xe7590001 //-60 -0xc78 0xe65a0001 -0xc78 0xe55b0001 -0xc78 0xe45c0001 -0xc78 0xe35d0001 -0xc78 0xe25e0001 //-50 -0xc78 0xe15f0001 -0xc78 0xe0600001 -0xc78 0x85610001 -0xc78 0x84620001 -0xc78 0x83630001 //-40 -0xc78 0x82640001 -0xc78 0xa5650001 -0xc78 0xa4660001 -0xc78 0xa3670001 -0xc78 0x65680001 //-30 -0xc78 0x64690001 -0xc78 0x636a0001 -0xc78 0x626b0001 -0xc78 0x616c0001 -0xc78 0x606d0001 //-20 -0xc78 0x466e0001 -0xc78 0x456f0001 -0xc78 0x44700001 -0xc78 0x43710001 -0xc78 0x42720001 //-10 -0xc78 0x41730001 -0xc78 0x40740001 -0xc78 0x40750001 -0xc78 0x40760001 -0xc78 0x40770001 //0 -0xc78 0x40780001 -0xc78 0x40790001 -0xc78 0x407a0001 -0xc78 0x407b0001 -0xc78 0x407c0001 //10 -0xc78 0x407d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040222 -0xc50 0x00040220 +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0xc78 0xff000001 // -110 +0xc78 0xff010001 +0xc78 0xff020001 +0xc78 0xff030001 +0xc78 0xff040001 +0xc78 0xfe050001 // -100 +0xc78 0xfd060001 +0xc78 0xfc070001 +0xc78 0xfb080001 +0xc78 0xfa090001 +0xc78 0xf90A0001 // -90 +0xc78 0xf80B0001 +0xc78 0xf70C0001 +0xc78 0xf60D0001 +0xc78 0xf50E0001 +0xc78 0xf40F0001 // -80 +0xc78 0xf3100001 +0xc78 0xf2110001 +0xc78 0xf1120001 +0xc78 0xf0130001 +0xc78 0xef140001 // -70 +0xc78 0xee150001 +0xc78 0xed160001 +0xc78 0xec170001 +0xc78 0xeb180001 +0xc78 0xea190001 // -60 +0xc78 0xe91A0001 +0xc78 0xe81B0001 +0xc78 0xe71C0001 +0xc78 0xe61D0001 +0xc78 0xe51E0001 // -50 +0xc78 0x891F0001 +0xc78 0x88200001 +0xc78 0x87210001 +0xc78 0x86220001 +0xc78 0xa9230001 // -40 +0xc78 0xa8240001 +0xc78 0x6a250001 +0xc78 0x69260001 +0xc78 0x68270001 +0xc78 0x67280001 //-30 +0xc78 0x66290001 +0xc78 0x652A0001 +0xc78 0x642B0001 +0xc78 0x4a2C0001 +0xc78 0x492D0001 // -20 +0xc78 0x482E0001 +0xc78 0x472F0001 +0xc78 0x46300001 +0xc78 0x45310001 +0xc78 0x44320001 // -10 +0xc78 0x43330001 +0xc78 0x42340001 +0xc78 0x41350001 +0xc78 0x40360001 +0xc78 0x40370001 // 0 +0xc78 0x40380001 +0xc78 0x40390001 +0xc78 0x403A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 // 10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 +// AGC_TABLE 2 for CS +0xc78 0xff400001 //-110 +0xc78 0xff410001 +0xc78 0xfe420001 +0xc78 0xfd430001 +0xc78 0xfc440001 +0xc78 0xfb450001 //-100 +0xc78 0xfa460001 +0xc78 0xf9470001 +0xc78 0xf8480001 +0xc78 0xf7490001 +0xc78 0xf64a0001 //-90 +0xc78 0xf54b0001 +0xc78 0xf44c0001 +0xc78 0xf34d0001 +0xc78 0xf24e0001 +0xc78 0xf14f0001 //-80 +0xc78 0xf0500001 +0xc78 0xef510001 +0xc78 0xee520001 +0xc78 0xed530001 +0xc78 0xec540001 //-70 +0xc78 0xeb550001 +0xc78 0xea560001 +0xc78 0xe9570001 +0xc78 0xe8580001 +0xc78 0xe7590001 //-60 +0xc78 0xe65a0001 +0xc78 0xe55b0001 +0xc78 0xe45c0001 +0xc78 0xe35d0001 +0xc78 0xe25e0001 //-50 +0xc78 0xe15f0001 +0xc78 0xe0600001 +0xc78 0x85610001 +0xc78 0x84620001 +0xc78 0x83630001 //-40 +0xc78 0x82640001 +0xc78 0xa5650001 +0xc78 0xa4660001 +0xc78 0xa3670001 +0xc78 0x65680001 //-30 +0xc78 0x64690001 +0xc78 0x636a0001 +0xc78 0x626b0001 +0xc78 0x616c0001 +0xc78 0x606d0001 //-20 +0xc78 0x466e0001 +0xc78 0x456f0001 +0xc78 0x44700001 +0xc78 0x43710001 +0xc78 0x42720001 //-10 +0xc78 0x41730001 +0xc78 0x40740001 +0xc78 0x40750001 +0xc78 0x40760001 +0xc78 0x40770001 //0 +0xc78 0x40780001 +0xc78 0x40790001 +0xc78 0x407a0001 +0xc78 0x407b0001 +0xc78 0x407c0001 //10 +0xc78 0x407d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040222 +0xc50 0x00040220 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192Emp.txt old mode 100755 new mode 100644 index d5311e68db9..b429816091b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/AGC_TAB_8192Emp.txt @@ -1,133 +1,133 @@ -//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 -0xc78 0xfb000001 //-110 -0xc78 0xfb010001 -0xc78 0xfb020001 -0xc78 0xfb030001 -0xc78 0xfb040001 -0xc78 0xfb050001 //-100 -0xc78 0xfb060001 -0xc78 0xfa070001 -0xc78 0xf9080001 -0xc78 0xf8090001 -0xc78 0xf70A0001 //-90 -0xc78 0xf60B0001 -0xc78 0xf50C0001 -0xc78 0xf40D0001 -0xc78 0xf30E0001 -0xc78 0xf20F0001 //-80 -0xc78 0xf1100001 -0xc78 0xf0110001 -0xc78 0xef120001 -0xc78 0xee130001 -0xc78 0xed140001 //-70 -0xc78 0xec150001 -0xc78 0xeb160001 -0xc78 0xea170001 -0xc78 0xcd180001 -0xc78 0xcc190001 //-60 -0xc78 0xcb1A0001 -0xc78 0xca1B0001 -0xc78 0xc91C0001 -0xc78 0xc81D0001 -0xc78 0x071E0001 //-50 -0xc78 0x061F0001 -0xc78 0x05200001 -0xc78 0x04210001 -0xc78 0x03220001 -0xc78 0xaa230001 //-40 -0xc78 0xa9240001 -0xc78 0xa8250001 -0xc78 0xa7260001 -0xc78 0xa6270001 -0xc78 0x85280001 //-30 -0xc78 0x84290001 -0xc78 0x832A0001 -0xc78 0x252B0001 -0xc78 0x242C0001 -0xc78 0x232D0001 //-20 -0xc78 0x222E0001 -0xc78 0x672F0001 -0xc78 0x66300001 -0xc78 0x65310001 -0xc78 0x64320001 //-10 -0xc78 0x63330001 -0xc78 0x62340001 -0xc78 0x61350001 -0xc78 0x45360001 -0xc78 0x44370001 //0 -0xc78 0x43380001 -0xc78 0x42390001 -0xc78 0x413A0001 -0xc78 0x403B0001 -0xc78 0x403C0001 //10 -0xc78 0x403D0001 -0xc78 0x403E0001 -0xc78 0x403F0001 //16 -// AGC_TABLE 2 for CS -0xc78 0xfb400001 //-110 -0xc78 0xfb410001 -0xc78 0xfb420001 -0xc78 0xfb430001 -0xc78 0xfb440001 -0xc78 0xfb450001 //-100 -0xc78 0xfb460001 -0xc78 0xfa470001 -0xc78 0xf9480001 -0xc78 0xf8490001 -0xc78 0xf74a0001 //-90 -0xc78 0xf64b0001 -0xc78 0xf54c0001 -0xc78 0xf44d0001 -0xc78 0xf34e0001 -0xc78 0xf24f0001 //-80 -0xc78 0xf1500001 -0xc78 0xf0510001 -0xc78 0xef520001 -0xc78 0xee530001 -0xc78 0xed540001 //-70 -0xc78 0xec550001 -0xc78 0xeb560001 -0xc78 0xea570001 -0xc78 0xe9580001 -0xc78 0xe8590001 //-60 -0xc78 0xe75a0001 -0xc78 0xe65b0001 -0xc78 0xe55c0001 -0xc78 0xe45d0001 -0xc78 0xe35e0001 //-50 -0xc78 0xe25f0001 -0xc78 0xe1600001 -0xc78 0x8a610001 -0xc78 0x89620001 -0xc78 0x88630001 //-40 -0xc78 0x87640001 -0xc78 0x86650001 -0xc78 0x85660001 -0xc78 0x84670001 -0xc78 0x83680001 //-30 -0xc78 0x82690001 -0xc78 0x6b6a0001 -0xc78 0x6a6b0001 -0xc78 0x696c0001 -0xc78 0x686d0001 //-20 -0xc78 0x676e0001 -0xc78 0x666f0001 -0xc78 0x65700001 -0xc78 0x64710001 -0xc78 0x63720001 //-10 -0xc78 0x62730001 -0xc78 0x61740001 -0xc78 0x49750001 -0xc78 0x48760001 -0xc78 0x47770001 //0 -0xc78 0x46780001 -0xc78 0x45790001 -0xc78 0x447a0001 -0xc78 0x437b0001 -0xc78 0x427c0001 //10 -0xc78 0x417d0001 -0xc78 0x407e0001 -0xc78 0x407f0001 //16 -0xc50 0x00040020 -0xc58 0x00000020 +//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 +0xc78 0xfb000001 //-110 +0xc78 0xfb010001 +0xc78 0xfb020001 +0xc78 0xfb030001 +0xc78 0xfb040001 +0xc78 0xfb050001 //-100 +0xc78 0xfb060001 +0xc78 0xfa070001 +0xc78 0xf9080001 +0xc78 0xf8090001 +0xc78 0xf70A0001 //-90 +0xc78 0xf60B0001 +0xc78 0xf50C0001 +0xc78 0xf40D0001 +0xc78 0xf30E0001 +0xc78 0xf20F0001 //-80 +0xc78 0xf1100001 +0xc78 0xf0110001 +0xc78 0xef120001 +0xc78 0xee130001 +0xc78 0xed140001 //-70 +0xc78 0xec150001 +0xc78 0xeb160001 +0xc78 0xea170001 +0xc78 0xcd180001 +0xc78 0xcc190001 //-60 +0xc78 0xcb1A0001 +0xc78 0xca1B0001 +0xc78 0xc91C0001 +0xc78 0xc81D0001 +0xc78 0x071E0001 //-50 +0xc78 0x061F0001 +0xc78 0x05200001 +0xc78 0x04210001 +0xc78 0x03220001 +0xc78 0xaa230001 //-40 +0xc78 0xa9240001 +0xc78 0xa8250001 +0xc78 0xa7260001 +0xc78 0xa6270001 +0xc78 0x85280001 //-30 +0xc78 0x84290001 +0xc78 0x832A0001 +0xc78 0x252B0001 +0xc78 0x242C0001 +0xc78 0x232D0001 //-20 +0xc78 0x222E0001 +0xc78 0x672F0001 +0xc78 0x66300001 +0xc78 0x65310001 +0xc78 0x64320001 //-10 +0xc78 0x63330001 +0xc78 0x62340001 +0xc78 0x61350001 +0xc78 0x45360001 +0xc78 0x44370001 //0 +0xc78 0x43380001 +0xc78 0x42390001 +0xc78 0x413A0001 +0xc78 0x403B0001 +0xc78 0x403C0001 //10 +0xc78 0x403D0001 +0xc78 0x403E0001 +0xc78 0x403F0001 //16 +// AGC_TABLE 2 for CS +0xc78 0xfb400001 //-110 +0xc78 0xfb410001 +0xc78 0xfb420001 +0xc78 0xfb430001 +0xc78 0xfb440001 +0xc78 0xfb450001 //-100 +0xc78 0xfb460001 +0xc78 0xfa470001 +0xc78 0xf9480001 +0xc78 0xf8490001 +0xc78 0xf74a0001 //-90 +0xc78 0xf64b0001 +0xc78 0xf54c0001 +0xc78 0xf44d0001 +0xc78 0xf34e0001 +0xc78 0xf24f0001 //-80 +0xc78 0xf1500001 +0xc78 0xf0510001 +0xc78 0xef520001 +0xc78 0xee530001 +0xc78 0xed540001 //-70 +0xc78 0xec550001 +0xc78 0xeb560001 +0xc78 0xea570001 +0xc78 0xe9580001 +0xc78 0xe8590001 //-60 +0xc78 0xe75a0001 +0xc78 0xe65b0001 +0xc78 0xe55c0001 +0xc78 0xe45d0001 +0xc78 0xe35e0001 //-50 +0xc78 0xe25f0001 +0xc78 0xe1600001 +0xc78 0x8a610001 +0xc78 0x89620001 +0xc78 0x88630001 //-40 +0xc78 0x87640001 +0xc78 0x86650001 +0xc78 0x85660001 +0xc78 0x84670001 +0xc78 0x83680001 //-30 +0xc78 0x82690001 +0xc78 0x6b6a0001 +0xc78 0x6a6b0001 +0xc78 0x696c0001 +0xc78 0x686d0001 //-20 +0xc78 0x676e0001 +0xc78 0x666f0001 +0xc78 0x65700001 +0xc78 0x64710001 +0xc78 0x63720001 //-10 +0xc78 0x62730001 +0xc78 0x61740001 +0xc78 0x49750001 +0xc78 0x48760001 +0xc78 0x47770001 //0 +0xc78 0x46780001 +0xc78 0x45790001 +0xc78 0x447a0001 +0xc78 0x437b0001 +0xc78 0x427c0001 //10 +0xc78 0x417d0001 +0xc78 0x407e0001 +0xc78 0x407f0001 //16 +0xc50 0x00040020 +0xc58 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_high_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_high_8192E.txt index a144771b745..a972d9cfda7 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_high_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_high_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x02 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x02 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_low_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_low_8192E.txt index 08cc78459fb..81274230019 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_low_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_low_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x0 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x0 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_normal_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_normal_8192E.txt index 39a1161be0c..1c1eed3295f 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_normal_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_def_normal_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x01 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x01 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_high_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_high_8192E.txt index f03aaf0e3d7..ddb6c574636 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_high_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_high_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x05 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x05 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_low_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_low_8192E.txt index 146d73eca7f..e7d511da3e5 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_low_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_low_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_normal_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_normal_8192E.txt index b98e8a63e1b..7aaf214840c 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_normal_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_gen_normal_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x04 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x04 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_state_criteria_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_state_criteria_8192E.txt index 8d0383c7635..7e1fed00500 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_state_criteria_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_state_criteria_8192E.txt @@ -1,35 +1,35 @@ -////Release version: 8881A.0820.2013 -// State: -// 1.) MACDM_TP_STATE_DEFAULT -// 2.) MACDM_TP_STATE_GENERAL -// 3.) MACDM_TP_STATE_TXOP -// So, we need four criteria -// 1.) MACDM_TP_THRS_DEF_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 2.) MACDM_TP_THRS_GEN_TO_DEF -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 3.) MACDM_TP_THRS_GEN_TO_TXOP -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 4.) MACDM_TP_THRS_TXOP_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -0x1a -0x1b -0x1c -0x2a -0x2b -0x2c -0x3a -0x3b -0x3c -0x4a -0x4b -0x4c +////Release version: 8881A.0820.2013 +// State: +// 1.) MACDM_TP_STATE_DEFAULT +// 2.) MACDM_TP_STATE_GENERAL +// 3.) MACDM_TP_STATE_TXOP +// So, we need four criteria +// 1.) MACDM_TP_THRS_DEF_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 2.) MACDM_TP_THRS_GEN_TO_DEF +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 3.) MACDM_TP_THRS_GEN_TO_TXOP +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 4.) MACDM_TP_THRS_TXOP_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +0x1a +0x1b +0x1c +0x2a +0x2b +0x2c +0x3a +0x3b +0x3c +0x4a +0x4b +0x4c 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_high_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_high_8192E.txt index a0b831b8da0..ef15d8353d6 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_high_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_high_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x08 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x08 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_low_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_low_8192E.txt index 96446d59ceb..4633edfd085 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_low_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_low_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x06 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x06 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_normal_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_normal_8192E.txt index 39d4beee894..f6a49b8ba6c 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_normal_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MACDM_txop_normal_8192E.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x07 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x07 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192E.txt old mode 100755 new mode 100644 index ea5afba54c6..03cb310ce90 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192E.txt @@ -1,103 +1,103 @@ -////Release version: RL0560A.0921.2012 -0x2C 0x96 -0x2D 0x05 -0x2E 0x82 -0x2F 0xF0 -0x65 0x01 // TRSWP TRSWN -0x78 0x2A -0x79 0x00 -//0x7C 0xC3 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x01 -0x432 0x02 -0x433 0x04 -0x434 0x05 -0x435 0x06 -0x436 0x07 -0x437 0x08 -0x438 0x00 -0x439 0x00 -0x43a 0x01 -0x43b 0x02 -0x43c 0x04 -0x43d 0x05 -0x43e 0x06 -0x43f 0x07 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x15 -0x445 0xf0 -0x446 0x0f -0x447 0x00 -0x458 0x41 -0x459 0xa8 -0x45a 0x72 -0x45b 0xb9 -0x460 0x66 -0x461 0x66 -0x480 0x08 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x4d3 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x540 0x12 // add for Cisco1252 IOT -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 // EDCA clock -0x652 0xc8 //enable NAV upper bound -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 - - - +////Release version: RL0560A.0921.2012 +0x2C 0x96 +0x2D 0x05 +0x2E 0x82 +0x2F 0xF0 +0x65 0x01 // TRSWP TRSWN +0x78 0x2A +0x79 0x00 +//0x7C 0xC3 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x01 +0x432 0x02 +0x433 0x04 +0x434 0x05 +0x435 0x06 +0x436 0x07 +0x437 0x08 +0x438 0x00 +0x439 0x00 +0x43a 0x01 +0x43b 0x02 +0x43c 0x04 +0x43d 0x05 +0x43e 0x06 +0x43f 0x07 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x15 +0x445 0xf0 +0x446 0x0f +0x447 0x00 +0x458 0x41 +0x459 0xa8 +0x45a 0x72 +0x45b 0xb9 +0x460 0x66 +0x461 0x66 +0x480 0x08 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x4d3 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x540 0x12 // add for Cisco1252 IOT +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 // EDCA clock +0x652 0xc8 //enable NAV upper bound +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 + + + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Eb.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Eb.txt old mode 100755 new mode 100644 index 1265f06f7bc..fad01f803a2 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Eb.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Eb.txt @@ -1,97 +1,97 @@ -////Release version: RL0560A.0921.2012 -0x65 0x01 // TRSWP TRSWN -0x78 0x2A -0x79 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x01 -0x432 0x02 -0x433 0x04 -0x434 0x05 -0x435 0x06 -0x436 0x07 -0x437 0x08 -0x438 0x00 -0x439 0x00 -0x43a 0x01 -0x43b 0x02 -0x43c 0x04 -0x43d 0x05 -0x43e 0x06 -0x43f 0x07 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x15 -0x445 0xf0 -0x446 0x0f -0x447 0x00 -0x458 0x41 -0x459 0xa8 -0x45a 0x72 -0x45b 0xb9 -0x460 0x66 -0x461 0x66 -0x480 0x08 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x4d3 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x540 0x12 // add for Cisco1252 IOT -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x652 0x20 -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 - - - +////Release version: RL0560A.0921.2012 +0x65 0x01 // TRSWP TRSWN +0x78 0x2A +0x79 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x01 +0x432 0x02 +0x433 0x04 +0x434 0x05 +0x435 0x06 +0x436 0x07 +0x437 0x08 +0x438 0x00 +0x439 0x00 +0x43a 0x01 +0x43b 0x02 +0x43c 0x04 +0x43d 0x05 +0x43e 0x06 +0x43f 0x07 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x15 +0x445 0xf0 +0x446 0x0f +0x447 0x00 +0x458 0x41 +0x459 0xa8 +0x45a 0x72 +0x45b 0xb9 +0x460 0x66 +0x461 0x66 +0x480 0x08 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x4d3 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x540 0x12 // add for Cisco1252 IOT +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x652 0x20 +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 + + + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Emp.txt old mode 100755 new mode 100644 index 9dbbcad4956..df70c09b556 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/MAC_REG_8192Emp.txt @@ -1,112 +1,112 @@ -//RTL8192E_MAC_PHY_Parameter_v016_MP_20130705 -//0x16 0x36 // SWR by Hillo -//0x28 0x83 -//0x2C 0x96 -//0x2D 0x05 -//0x2E 0x82 -//0x2F 0xF0 -//0x64 0x00 -//0x65 0x01 // TRSWP=1 ANTSEL2=0 for WLAN -//0x78 0x2A -//0x79 0x00 -//0x7C 0xC3 -0x303 0xA7 -0x421 0x0F -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5f -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0f -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x456 0x5e -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x540 0x12 -0x541 0x64 -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x08 -0x63d 0x08 -0x63e 0x0c -0x63f 0x0c -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 +//RTL8192E_MAC_PHY_Parameter_v016_MP_20130705 +//0x16 0x36 // SWR by Hillo +//0x28 0x83 +//0x2C 0x96 +//0x2D 0x05 +//0x2E 0x82 +//0x2F 0xF0 +//0x64 0x00 +//0x65 0x01 // TRSWP=1 ANTSEL2=0 for WLAN +//0x78 0x2A +//0x79 0x00 +//0x7C 0xC3 +0x303 0xA7 +0x421 0x0F +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5f +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0f +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x456 0x5e +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x540 0x12 +0x541 0x64 +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x08 +0x63d 0x08 +0x63e 0x0c +0x63f 0x0c +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E.txt old mode 100755 new mode 100644 index a886591c5a8..03e3c78ba4c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E.txt @@ -1,235 +1,235 @@ -////Release version: RTL8192E.001.0921.2012 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004000 // path B 1R RSSI off issue -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 - -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00040020 // -0xc54 0x0400101f // Antenna weighting TH -0xc58 0x00000020 // -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000000 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 -0xe10 0x30303030 -0xe14 0x30303030 -0xe18 0x30303030 -0xe1c 0x30303030 -0xe28 0x00000000 -0xe30 0x1000dc1f -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000008 -0xe68 0x0fc01616 -0xe6c 0x0fc01616 -0xe70 0x0fc01616 -0xe74 0x0fc01616 -0xe78 0x0fc01616 -0xe7c 0x0fc01616 -0xe80 0x0fc01616 -0xe84 0x0fc01616 -0xe88 0x0fc01616 -0xe8c 0x0fc01616 -0xed0 0x0fc01616 -0xed4 0x0fc01616 -0xed8 0x0fc01616 -0xedc 0x0fc01616 -0xee0 0x0fc01616 -0xeec 0x0fc01616 -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +////Release version: RTL8192E.001.0921.2012 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004000 // path B 1R RSSI off issue +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 + +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00040020 // +0xc54 0x0400101f // Antenna weighting TH +0xc58 0x00000020 // +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000000 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 +0xe10 0x30303030 +0xe14 0x30303030 +0xe18 0x30303030 +0xe1c 0x30303030 +0xe28 0x00000000 +0xe30 0x1000dc1f +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000008 +0xe68 0x0fc01616 +0xe6c 0x0fc01616 +0xe70 0x0fc01616 +0xe74 0x0fc01616 +0xe78 0x0fc01616 +0xe7c 0x0fc01616 +0xe80 0x0fc01616 +0xe84 0x0fc01616 +0xe88 0x0fc01616 +0xe8c 0x0fc01616 +0xed0 0x0fc01616 +0xed4 0x0fc01616 +0xed8 0x0fc01616 +0xedc 0x0fc01616 +0xee0 0x0fc01616 +0xeec 0x0fc01616 +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192ES_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192ES_extlna.txt index c0271f2fccf..bc3ac98c841 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192ES_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192ES_extlna.txt @@ -1,239 +1,239 @@ -//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390004 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390004 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00005000 -0x934 0x00004000 -0x938 0x00000540 -0x93c 0x00000000 -0x940 0x00000015 -0x944 0x0000083F -0x94c 0x00000008 -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d0c7c8 // bit7 ant div enable -0xa04 0x81ff800c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e2e120f -0xa10 0x95009b78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fff00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x21807531 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00340220 -0xc54 0x0080801f // Antenna weighting TH -0xc58 0x00000220 -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000600 // gain_var & table sel -0xc74 0x02013163 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd1c 0x0000007f -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 //0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -0xd80 0x01081008 // CSI default value -0xd84 0x00000800 // csi_feedback_en -0xd88 0xf0b50000 // scaling - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M -0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 -0xe60 0x00000008 -0xe68 0x0fc05656 -0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby -0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep -0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - -0xffff 0xffff +//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390004 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390004 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00005000 +0x934 0x00004000 +0x938 0x00000540 +0x93c 0x00000000 +0x940 0x00000015 +0x944 0x0000083F +0x94c 0x00000008 +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d0c7c8 // bit7 ant div enable +0xa04 0x81ff800c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e2e120f +0xa10 0x95009b78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fff00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x21807531 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00340220 +0xc54 0x0080801f // Antenna weighting TH +0xc58 0x00000220 +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000600 // gain_var & table sel +0xc74 0x02013163 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd1c 0x0000007f +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 //0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +0xd80 0x01081008 // CSI default value +0xd84 0x00000800 // csi_feedback_en +0xd88 0xf0b50000 // scaling + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M +0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 +0xe60 0x00000008 +0xe68 0x0fc05656 +0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby +0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep +0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extlna.txt old mode 100755 new mode 100644 index ade38bff799..ab7c862d60e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extlna.txt @@ -1,239 +1,239 @@ -//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390004 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390004 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 -0x94c 0x00000008 -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d0c7c8 // bit7 ant div enable -0xa04 0x81ff800c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e2f120f // 0xa0e=0x2f 2015 -0xa10 0x95009b78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fff00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00340220 -0xc54 0x0080801f // Antenna weighting TH -0xc58 0x00000220 -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000600 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd1c 0x0000007f -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 //0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -0xd80 0x01081008 // CSI default value -0xd84 0x00000800 // csi_feedback_en -0xd88 0xf0b50000 // scaling - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M -0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 -0xe60 0x00000008 -0xe68 0x0fc05656 -0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby -0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep -0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390004 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390004 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 +0x94c 0x00000008 +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d0c7c8 // bit7 ant div enable +0xa04 0x81ff800c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e2f120f // 0xa0e=0x2f 2015 +0xa10 0x95009b78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fff00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00340220 +0xc54 0x0080801f // Antenna weighting TH +0xc58 0x00000220 +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000600 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd1c 0x0000007f +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 //0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +0xd80 0x01081008 // CSI default value +0xd84 0x00000800 // csi_feedback_en +0xd88 0xf0b50000 // scaling + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M +0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 +0xe60 0x00000008 +0xe68 0x0fc05656 +0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby +0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep +0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extpa.txt old mode 100755 new mode 100644 index 9a024f601f4..b4aab84daf8 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_extpa.txt @@ -1,239 +1,239 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 -0x94c 0x00000008 -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d0c7c8 // bit7 ant div enable -0xa04 0x81ff000c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x95009b78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x10d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00340220 -0xc54 0x0080801f // Antenna weighting TH -0xc58 0x00000220 -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000600 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd1c 0x0000007f -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 //0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -0xd80 0x01081008 // CSI default value -0xd84 0x00000800 // csi_feedback_en -0xd88 0xf0b50000 // scaling - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M -0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 -0xe60 0x00000008 -0xe68 0x0fc05656 -0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby -0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep -0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 +0x94c 0x00000008 +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d0c7c8 // bit7 ant div enable +0xa04 0x81ff000c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x95009b78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x10d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00340220 +0xc54 0x0080801f // Antenna weighting TH +0xc58 0x00000220 +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000600 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd1c 0x0000007f +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 //0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +0xd80 0x01081008 // CSI default value +0xd84 0x00000800 // csi_feedback_en +0xd88 0xf0b50000 // scaling + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M +0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 +0xe60 0x00000008 +0xe68 0x0fc05656 +0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby +0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep +0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_hp.txt old mode 100755 new mode 100644 index 6c9628247f8..6dfb5fa3dc6 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192E_hp.txt @@ -1,239 +1,239 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390004 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390004 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 -0x94c 0x00000008 -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d0c7c8 // bit7 ant div enable -0xa04 0x81ff000c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e2e120f -0xa10 0x95009b78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x10d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00340220 -0xc54 0x0080801f // Antenna weighting TH -0xc58 0x00000220 -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000600 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x2d4000b5 // -3 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x2d4000b5 // -3 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd1c 0x0000007f -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 //0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -0xd80 0x01081008 // CSI default value -0xd84 0x00000800 // csi_feedback_en -0xd88 0xf0b50000 // scaling - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M -0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 -0xe60 0x00000008 -0xe68 0x0fc05656 -0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby -0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep -0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390004 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390004 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 +0x94c 0x00000008 +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d0c7c8 // bit7 ant div enable +0xa04 0x81ff000c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e2e120f +0xa10 0x95009b78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x10d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00340220 +0xc54 0x0080801f // Antenna weighting TH +0xc58 0x00000220 +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000600 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x2d4000b5 // -3 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x2d4000b5 // -3 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd1c 0x0000007f +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 //0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +0xd80 0x01081008 // CSI default value +0xd84 0x00000800 // csi_feedback_en +0xd88 0xf0b50000 // scaling + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M +0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 +0xe60 0x00000008 +0xe68 0x0fc05656 +0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby +0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep +0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Eb.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Eb.txt old mode 100755 new mode 100644 index 7c90bc0a415..505c29e9a2f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Eb.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Eb.txt @@ -1,235 +1,235 @@ -////Release version: RTL8192E.001.0921.2012 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00690204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00690204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004000 // path B 1R RSSI off issue -0x878 0x08080830 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 - -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00040020 // -0xc54 0x0400101f // Antenna weighting TH -0xc58 0x00000020 // -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000000 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR - -//======================= -// PAGE_E -//======================= -0xe00 0x24242424 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x24242424 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 -0xe10 0x30303030 -0xe14 0x30303030 -0xe18 0x30303030 -0xe1c 0x30303030 -0xe28 0x00000000 -0xe30 0x1000dc1f -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681304c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28130d05 -0xe60 0x00000008 -0xe68 0x0fc01616 -0xe6c 0x0fc01616 -0xe70 0x0fc01616 -0xe74 0x0fc01616 -0xe78 0x0fc01616 -0xe7c 0x0fc01616 -0xe80 0x0fc01616 -0xe84 0x0fc01616 -0xe88 0x0fc01616 -0xe8c 0x0fc01616 -0xed0 0x0fc01616 -0xed4 0x0fc01616 -0xed8 0x0fc01616 -0xedc 0x0fc01616 -0xee0 0x0fc01616 -0xeec 0x0fc01616 -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +////Release version: RTL8192E.001.0921.2012 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00690204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00690204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004000 // path B 1R RSSI off issue +0x878 0x08080830 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x826c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 + +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00040020 // +0xc54 0x0400101f // Antenna weighting TH +0xc58 0x00000020 // +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000000 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR + +//======================= +// PAGE_E +//======================= +0xe00 0x24242424 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x24242424 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 +0xe10 0x30303030 +0xe14 0x30303030 +0xe18 0x30303030 +0xe1c 0x30303030 +0xe28 0x00000000 +0xe30 0x1000dc1f +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681304c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28130d05 +0xe60 0x00000008 +0xe68 0x0fc01616 +0xe6c 0x0fc01616 +0xe70 0x0fc01616 +0xe74 0x0fc01616 +0xe78 0x0fc01616 +0xe7c 0x0fc01616 +0xe80 0x0fc01616 +0xe84 0x0fc01616 +0xe88 0x0fc01616 +0xe8c 0x0fc01616 +0xed0 0x0fc01616 +0xed4 0x0fc01616 +0xed8 0x0fc01616 +0xedc 0x0fc01616 +0xee0 0x0fc01616 +0xeec 0x0fc01616 +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Emp.txt old mode 100755 new mode 100644 index 4c2cecbb75a..d62c62a31d5 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_8192Emp.txt @@ -1,239 +1,239 @@ -//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 -0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) -0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 -0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M -0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M -0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M -0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0x840 0x00010000 // RF to standby mode -0x844 0x00010000 // RF to standby mode -0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0x850 0x00000000 // RF wakeup TBD -0x854 0x00000000 // RF sleep TBD -0x858 0x009a009a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60000 // 88CE default left anatenna -0x864 0x061f0000 -0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword -0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) -0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A -0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) -0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 - - -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing -0x914 0x00000001 -0x918 0x00000000 -0x91c 0x00010000 // LDPC setting -0x924 0x00000001 -0x928 0x00000000 -0x92c 0x00000000 -0x930 0x00000000 -0x934 0x00000000 -0x938 0x00000000 -0x93c 0x00000000 -0x940 0x00000000 -0x944 0x00000000 -0x94c 0x00000008 -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d0c7c8 // bit7 ant div enable -0xa04 0x81ff800c -0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x95009b78 // -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fff00 -0xa74 0x00000007 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b1 - -//======================= -// PAGE_B -//======================= -0xb38 0x00000000 - -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 -0xc34 0x469652af // FS option = L1 MF only -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x00340020 // -0xc54 0x0080801f // Antenna weighting TH -0xc58 0x00000020 // -0xc5c 0x00248492 // AGC RXHP corner -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b // Lower L1 MF TH for FS -0xc68 0x47c00bff // L1-SBD -0xc6c 0x00000036 // L1-SBD -0xc70 0x00000600 // gain_var & table sel -0xc74 0x02013169 // simple agc settling time -0xc78 0x0000001f -0xc7c 0x00b91612 // HT-AGC setting -0xc80 0x40000100 -0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 // ANTsw TH -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00040000 // LNAsw gain jump enable -0xce8 0x77644302 // c8c[30]=1b1 -0xcec 0x2f97d40c - -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd1c 0x0000007f -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00127353 //0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000282 // NBI CSI weighted -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -0xd80 0x01081008 // CSI default value -0xd84 0x00000800 // csi_feedback_en -0xd88 0xf0b50000 // scaling - -//======================= -// PAGE_E -//======================= -0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M -0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M -0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M -0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 -0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 -0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 -0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 -0xe60 0x00000008 -0xe68 0x0fc05656 -0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby -0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep -0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee4 0xb0000c1c // Port 1 -0xee8 0x00000001 // Port 1 - -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb - +//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02220385 // 92E testchip 0x818[17]=1b1 for IQ inverse +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x824 0x00390204 // 92E testchip 0x824[22:20]=3h6 for RF path-A mode table setting C-cut back to 3 +0x828 0x01000100 // 0x01000000 (SI) 0x01000100 (PI) +0x82c 0x00390204 // 92E testchip 0x82c[22:20]=3h6 for RF path-B mode table setting C-cut back to 3 +0x830 0x32323232 // Path-B TX AGC codewod 6M 9M 12M 18M +0x834 0x30303030 // Path-B TX AGC codewod 24M 36M 48M 54M +0x838 0x30303030 // Path-B TX AGC codewod MCS32 1M 2M 5.5M +0x83c 0x30303030 // Path-B TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0x840 0x00010000 // RF to standby mode +0x844 0x00010000 // RF to standby mode +0x848 0x28282828 // Path-B TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0x84c 0x28282828 // Path-B TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0x850 0x00000000 // RF wakeup TBD +0x854 0x00000000 // RF sleep TBD +0x858 0x009a009a +0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66f60000 // 88CE default left anatenna +0x864 0x061f0000 +0x868 0x30303030 // Path-B TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0x86c 0x30303030 // Path-A 11M/5.5M/2M TX AGC codeword Path-B 11M TX AGC codeword +0x870 0x00000000 // z2: 0x03000300 92C RF: 0x07000700 (2 internal PA) 92S RF: 0x03000700 (one internal PA) +0x874 0x55004200 // path B 1R RSSI off issue 92E MP: BIT[9:8] for IQ flag setting 1:refer to path-B 0: refer to path-A +0x878 0x08080808 // 92E TestChip 1SS Path-B Tx and Path-A enter RX mode 6 C-cut back to default +0x87c 0x00000000 // TST mode +0x880 0xb0000c1c // Port 0 AFE ctrl reg (ASIC) +0x884 0x00000001 // Port 0 AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode [27] [31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 + + +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +0x910 0x806c0001 // LDPC setting 910[5:0]=1 for AMPDU PHY status parsing +0x914 0x00000001 +0x918 0x00000000 +0x91c 0x00010000 // LDPC setting +0x924 0x00000001 +0x928 0x00000000 +0x92c 0x00000000 +0x930 0x00000000 +0x934 0x00000000 +0x938 0x00000000 +0x93c 0x00000000 +0x940 0x00000000 +0x944 0x00000000 +0x94c 0x00000008 +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d0c7c8 // bit7 ant div enable +0xa04 0x81ff800c +0xa08 0x8c838300 // MP: 0x88838300 driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x95009b78 // +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fff00 +0xa74 0x00000007 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b1 + +//======================= +// PAGE_B +//======================= +0xb38 0x00000000 + +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac47 // PWED_TH option2=0x69e9bb44 0x69e9ab44 0x69e9ac44 +0xc34 0x469652af // FS option = L1 MF only +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x00340020 // +0xc54 0x0080801f // Antenna weighting TH +0xc58 0x00000020 // +0xc5c 0x00248492 // AGC RXHP corner +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b // Lower L1 MF TH for FS +0xc68 0x47c00bff // L1-SBD +0xc6c 0x00000036 // L1-SBD +0xc70 0x00000600 // gain_var & table sel +0xc74 0x02013169 // simple agc settling time +0xc78 0x0000001f +0xc7c 0x00b91612 // HT-AGC setting +0xc80 0x40000100 +0xc84 0x21f60000 // New TX-DFIR enable c84[24]=1 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x000300A0 // ANTsw TH +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00040000 // LNAsw gain jump enable +0xce8 0x77644302 // c8c[30]=1b1 +0xcec 0x2f97d40c + +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd1c 0x0000007f +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00127353 //0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000282 // NBI CSI weighted +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +0xd80 0x01081008 // CSI default value +0xd84 0x00000800 // csi_feedback_en +0xd88 0xf0b50000 // scaling + +//======================= +// PAGE_E +//======================= +0xe00 0x30303030 // Path-A TX AGC codewod 6M 9M 12M 18M +0xe04 0x30303030 // Path-A TX AGC codewod 24M 36M 48M 54M +0xe08 0x03903030 // Path-A TX AGC codewod MCS32 1M +0xe10 0x30303030 // Path-A TX AGC codewod MCS0 MCS1 MCS2 MCS3 +0xe14 0x30303030 // Path-A TX AGC codewod MCS4 MCS5 MCS6 MCS7 +0xe18 0x30303030 // Path-A TX AGC codewod MCS8 MCS9 MCS10 MCS11 +0xe1c 0x30303030 // Path-A TX AGC codewod MCS12 MCS13 MCS14 MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 //default :0x681604c2 change RXIQK to mode 3 C-cut back to default +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 //default C-cut: 0x28160d05 change RXIQK to mode 3 +0xe60 0x00000008 +0xe68 0x0fc05656 +0xe6c 0x03c09696 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c005656 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c005656 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x03c09696 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c005656 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x03c09696 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x03c09696 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x03c09696 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x03c09696 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x0000d6d6 // AFE ctrl reg (ASIC) Standby +0xee0 0x0000d6d6 // AFE ctrl reg (ASIC) Sleep +0xeec 0x0fc01616 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee4 0xb0000c1c // Port 1 +0xee8 0x00000001 // Port 1 + +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB bcz HSSI use clk_bb + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192E.txt old mode 100755 new mode 100644 index 963c6515941..961b4ee2645 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192E.txt @@ -1,2 +1,2 @@ - + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192Emp.txt old mode 100755 new mode 100644 index 963c6515941..961b4ee2645 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_MP_8192Emp.txt @@ -1,2 +1,2 @@ - + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E.txt old mode 100755 new mode 100644 index 4557f798034..88fc8a9b72f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E.txt @@ -1,144 +1,144 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= -//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// For Ant A -0xe00 0xffffffff 0x0609090a // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00030406 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x01040508 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x01040508 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x0609090a // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00030406 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x01040508 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x01040508 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -0xffff 0xffff //end of file +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= +//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// For Ant A +0xe00 0xffffffff 0x0609090a // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00030406 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x01040508 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x01040508 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x0609090a // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00030406 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x01040508 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x01040508 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +0xffff 0xffff //end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E_new.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E_new.txt old mode 100755 new mode 100644 index e45e94c8ac3..8457fe1d2fc --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E_new.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192E_new.txt @@ -1,21 +1,21 @@ -//RL6286_MAC_PHY_Parameter_v024_20130125 -#Exact -0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v024_20130125 +#Exact +0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp.txt old mode 100755 new mode 100644 index e45e94c8ac3..8457fe1d2fc --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp.txt @@ -1,21 +1,21 @@ -//RL6286_MAC_PHY_Parameter_v024_20130125 -#Exact -0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v024_20130125 +#Exact +0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp_hp.txt old mode 100755 new mode 100644 index 244632c8f09..b2d26d79dd4 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/PHY_REG_PG_8192Emp_hp.txt @@ -1,21 +1,21 @@ -//RL6286_MAC_PHY_Parameter_v024_20130125 -#Exact -0xe00 26 27 27 27 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 28 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 27 27 28 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 26 27 27 27 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 27 28 28 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 27 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v024_20130125 +#Exact +0xe00 26 27 27 27 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 28 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 27 27 28 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 26 27 27 27 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 27 28 28 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 27 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 24 25 25 25 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E.txt old mode 100755 new mode 100644 index e568b35256d..37a3a3e53c0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E.txt @@ -1,180 +1,180 @@ -////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve -0x7F 0x00082 // for C cut -0x81 0x3FC00 // for C cut -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F0 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x6b25d //0x6b25d :spur -0x52 0x7E43E -0x53 0x00073 -0x56 0x51FF3 -0x35 0x00092 -0x35 0x00192 //CCK DY swing TX EVM -0x35 0x00292 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x8BD00 //TX IMR 4Be00 -0X19 0x739d0 -// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step -//0X34 0x0aff4 -//0X34 0x09ff7 -//0X34 0x08fea -//0X34 0x07fed -//0X34 0x06fe0 -//0X34 0x05fe1 -//0X34 0x045e0 -//0X34 0x031ef -//0X34 0x020eb -//0X34 0x010ee -//0X34 0x0006a - -//Tx gain PAD-2dB 3dB/step for 80M clk spur -//0x34 0x0adf4 -//0x34 0x09df7 -//0x34 0x08dea //0x08dea -//0x34 0x07ded -//0x34 0x06de0 -//0x34 0x05ced -//0x34 0x04ce0 -//0x34 0x034e0 -//0x34 0x0246d -//0x34 0x01460 -//0x34 0x0006f - -//For MP Chip power saving (92EE) -0x34 0xadd5 -0x34 0x9dd2 -0x34 0x8dcf -0x34 0x7dcc -0x34 0x6dc9 -0x34 0x54d0 //0x5cea -0x34 0x44cd //0x4ce7 -0x34 0x34ca //0x34e7 -0x34 0x244d //0x246a -0x34 0x144a //0x1467 -0x34 0x004f //0x0068 - -// FOR 1dB step -5dB -//0x34 0x0ade8 -//0x34 0x09de9 -//0x34 0x08dea -//0x34 0x07deb -//0x34 0x06dec -//0x34 0x05ded -//0x34 0x04dee -//0x34 0x03def -//0x34 0x02de0 -//0x34 0x01de1 -//0x34 0x00de2 - -//FOR 1dB step -10dB -//0x34 0x0aded -//0x34 0x09dee -//0x34 0x08def -//0x34 0x07de0 -//0x34 0x06de1 -//0x34 0x05de2 -//0x34 0x04de3 -//0x34 0x03de4 -//0x34 0x02de5 -//0x34 0x01de7 -//0x34 0x00de7 - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68002 // update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x782b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5efa0 //54fb0 -0x3b 0x40060 // CS gain table -0x3b 0x30890 -0x3b 0x20080 -0x3b 0x1f060 -0x3b 0x0ffb0 -0xef 0x000A0 //Rx gaintable WEb - -// write RF Rx mode table3 to 6 need BB 0x824[22:20] = 6 for path-A -//0xef 0x800A0 -//0x30 0x30000 -//0x31 0x0000f -//0x32 0x77f82 -//0xef 0x000A0 -//0x00 0x10159 - -// write RF Rx IQK mode at mode 3 ; need BB 0xe3c[:] = 3 for path A -//0xef 0x800A0 -//0x30 0x18000 -//0x31 0x0000f -//0x32 0xf117b -//0xef 0x000A0 -//0x00 0x10159 - -//LC calibration start -0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve +0x7F 0x00082 // for C cut +0x81 0x3FC00 // for C cut +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F0 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x6b25d //0x6b25d :spur +0x52 0x7E43E +0x53 0x00073 +0x56 0x51FF3 +0x35 0x00092 +0x35 0x00192 //CCK DY swing TX EVM +0x35 0x00292 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x8BD00 //TX IMR 4Be00 +0X19 0x739d0 +// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step +//0X34 0x0aff4 +//0X34 0x09ff7 +//0X34 0x08fea +//0X34 0x07fed +//0X34 0x06fe0 +//0X34 0x05fe1 +//0X34 0x045e0 +//0X34 0x031ef +//0X34 0x020eb +//0X34 0x010ee +//0X34 0x0006a + +//Tx gain PAD-2dB 3dB/step for 80M clk spur +//0x34 0x0adf4 +//0x34 0x09df7 +//0x34 0x08dea //0x08dea +//0x34 0x07ded +//0x34 0x06de0 +//0x34 0x05ced +//0x34 0x04ce0 +//0x34 0x034e0 +//0x34 0x0246d +//0x34 0x01460 +//0x34 0x0006f + +//For MP Chip power saving (92EE) +0x34 0xadd5 +0x34 0x9dd2 +0x34 0x8dcf +0x34 0x7dcc +0x34 0x6dc9 +0x34 0x54d0 //0x5cea +0x34 0x44cd //0x4ce7 +0x34 0x34ca //0x34e7 +0x34 0x244d //0x246a +0x34 0x144a //0x1467 +0x34 0x004f //0x0068 + +// FOR 1dB step -5dB +//0x34 0x0ade8 +//0x34 0x09de9 +//0x34 0x08dea +//0x34 0x07deb +//0x34 0x06dec +//0x34 0x05ded +//0x34 0x04dee +//0x34 0x03def +//0x34 0x02de0 +//0x34 0x01de1 +//0x34 0x00de2 + +//FOR 1dB step -10dB +//0x34 0x0aded +//0x34 0x09dee +//0x34 0x08def +//0x34 0x07de0 +//0x34 0x06de1 +//0x34 0x05de2 +//0x34 0x04de3 +//0x34 0x03de4 +//0x34 0x02de5 +//0x34 0x01de7 +//0x34 0x00de7 + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68002 // update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x782b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5efa0 //54fb0 +0x3b 0x40060 // CS gain table +0x3b 0x30890 +0x3b 0x20080 +0x3b 0x1f060 +0x3b 0x0ffb0 +0xef 0x000A0 //Rx gaintable WEb + +// write RF Rx mode table3 to 6 need BB 0x824[22:20] = 6 for path-A +//0xef 0x800A0 +//0x30 0x30000 +//0x31 0x0000f +//0x32 0x77f82 +//0xef 0x000A0 +//0x00 0x10159 + +// write RF Rx IQK mode at mode 3 ; need BB 0xe3c[:] = 3 for path A +//0xef 0x800A0 +//0x30 0x18000 +//0x31 0x0000f +//0x32 0xf117b +//0xef 0x000A0 +//0x00 0x10159 + +//LC calibration start +0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES.txt index ed03c92b532..0ec291fe9ce 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES.txt @@ -1,122 +1,122 @@ -//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 - LTE blocking -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x00064 //(121226): default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -0x1C 0x00000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0014e // LNA switch by BB control modified by Hillo -0x87 0x49f80 // modified by Hillo -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf52b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x70730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 - LTE blocking +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x00064 //(121226): default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +0x1C 0x00000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0014e // LNA switch by BB control modified by Hillo +0x87 0x49f80 // modified by Hillo +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf52b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x70730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES_extlna.txt index 2c0ab26ae15..9d452eb6cc3 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192ES_extlna.txt @@ -1,127 +1,127 @@ -//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x000F4 -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBC 0x00078 -0xBD 0xB3333 -0xBE 0x33340 -0xBF 0x00000 -0xC0 0x05999 -0xC1 0x09999 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -0x1C 0x00000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0014E // LNA switch by BB control modified by Hillo -0x87 0x49F80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xF0730 -0x3b 0xE0730 -0x3b 0xD0020 -0x3b 0xC0020 -0x3b 0xB0760 -0x3b 0xA0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x707b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - -0xffff 0xffff +//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x000F4 +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBC 0x00078 +0xBD 0xB3333 +0xBE 0x33340 +0xBF 0x00000 +0xC0 0x05999 +0xC1 0x09999 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +0x1C 0x00000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0014E // LNA switch by BB control modified by Hillo +0x87 0x49F80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xF0730 +0x3b 0xE0730 +0x3b 0xD0020 +0x3b 0xC0020 +0x3b 0xB0760 +0x3b 0xA0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x707b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extlna.txt old mode 100755 new mode 100644 index 97f87ac8eb0..98c4074a9da --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extlna.txt @@ -1,127 +1,127 @@ -//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x0146c -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBC 0x00078 -0xBD 0xB3333 -0xBE 0x33340 -0xBF 0x00000 -0xC0 0x05999 -0xC1 0x09999 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -0x1C 0x00000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x14e -0x87 0x49f80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xF0730 -0x3b 0xE0730 -0x3b 0xD0020 -0x3b 0xC0020 -0x3b 0xB0760 -0x3b 0xA0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x0146c +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBC 0x00078 +0xBD 0xB3333 +0xBE 0x33340 +0xBF 0x00000 +0xC0 0x05999 +0xC1 0x09999 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +0x1C 0x00000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x14e +0x87 0x49f80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xF0730 +0x3b 0xE0730 +0x3b 0xD0020 +0x3b 0xC0020 +0x3b 0xB0760 +0x3b 0xA0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extpa.txt old mode 100755 new mode 100644 index f99f821ca05..84b22505482 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_extpa.txt @@ -1,121 +1,121 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x0146C //(121226): default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0014e // LNA switch by BB control modified by Hillo -0x87 0x79f80 //0x48e00 // modified by Hillo -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf07b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 //MP chip cant remark -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x0146C //(121226): default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0014e // LNA switch by BB control modified by Hillo +0x87 0x79f80 //0x48e00 // modified by Hillo +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf07b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 //MP chip cant remark +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_hp.txt old mode 100755 new mode 100644 index 3f173436a71..eaf14aa7ab8 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192E_hp.txt @@ -1,121 +1,121 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x00064 //(121226): default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xa093 -0x34 0x908f -0x34 0x808c -0x34 0x704d -0x34 0x604a -0x34 0x5047 -0x34 0x400a -0x34 0x3007 -0x34 0x2004 -0x34 0x1001 -0x34 0x0000 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0010e // LNA switch by BB control modified by Hillo -0x87 0x4ff80 //0x48e00 // modified by Hillo -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf07b0 -0x3b 0xe0730 -0x3b 0xd0020 -0x3b 0xc0020 -0x3b 0xb0760 -0x3b 0xa0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 //MP chip cant remark -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x00064 //(121226): default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xa093 +0x34 0x908f +0x34 0x808c +0x34 0x704d +0x34 0x604a +0x34 0x5047 +0x34 0x400a +0x34 0x3007 +0x34 0x2004 +0x34 0x1001 +0x34 0x0000 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0010e // LNA switch by BB control modified by Hillo +0x87 0x4ff80 //0x48e00 // modified by Hillo +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf07b0 +0x3b 0xe0730 +0x3b 0xd0020 +0x3b 0xc0020 +0x3b 0xb0760 +0x3b 0xa0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 //MP chip cant remark +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Eb.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Eb.txt old mode 100755 new mode 100644 index 5a46b61620b..957f3068c57 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Eb.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Eb.txt @@ -1,178 +1,178 @@ -////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F0 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1(80081) for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x6b25d //0x6b25d :spur -0x52 0x7E43E -0x53 0x00073 -0x56 0x51FF3 -0x35 0x00092 -0x35 0x00192 //CCK DY swing TX EVM -0x35 0x00292 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x8BD00 //TX IMR 4Be00 -0X19 0x739d0 -// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step -//0X34 0x0aff4 -//0X34 0x09ff7 -//0X34 0x08fea -//0X34 0x07fed -//0X34 0x06fe0 -//0X34 0x05fe1 -//0X34 0x045e0 -//0X34 0x031ef -//0X34 0x020eb -//0X34 0x010ee -//0X34 0x0006a - -//Tx gain PAD-2dB 3dB/step for 80M clk spur -//0x34 0x0adf4 -//0x34 0x09df7 -//0x34 0x08dea //0x08dea -//0x34 0x07ded -//0x34 0x06de0 -//0x34 0x05ced -//0x34 0x04ce0 -//0x34 0x034e0 -//0x34 0x0246d -//0x34 0x01460 -//0x34 0x0006f - -//For MP Chip power saving (92EE) -0x34 0xadd5 -0x34 0x9dd2 -0x34 0x8dcf -0x34 0x7dcc -0x34 0x6dc9 -0x34 0x54d0 //0x5cea -0x34 0x44cd //0x4ce7 -0x34 0x34ca //0x34e7 -0x34 0x244d //0x246a -0x34 0x144a //0x1467 -0x34 0x004f //0x0068 - -// FOR 1dB step -5dB -//0x34 0x0ade8 -//0x34 0x09de9 -//0x34 0x08dea -//0x34 0x07deb -//0x34 0x06dec -//0x34 0x05ded -//0x34 0x04dee -//0x34 0x03def -//0x34 0x02de0 -//0x34 0x01de1 -//0x34 0x00de2 - -//FOR 1dB step -10dB -//0x34 0x0aded -//0x34 0x09dee -//0x34 0x08def -//0x34 0x07de0 -//0x34 0x06de1 -//0x34 0x05de2 -//0x34 0x04de3 -//0x34 0x03de4 -//0x34 0x02de5 -//0x34 0x01de7 -//0x34 0x00de7 - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68002 // update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5efa0 //54fb0 -0x3b 0x40060 // CS gain table -0x3b 0x30890 -0x3b 0x20080 -0x3b 0x1f060 -0x3b 0x0ffb0 -0xef 0x000A0 //Rx gaintable WEb - -// write RF Rx mode at mode 6 ; need BB 0x824[22:20] = 6 for path A -0xef 0x800A0 -0x30 0x30000 -0x31 0x0000f -0x32 0x77f82 -0xef 0x000A0 -0x00 0x10159 - -// write RF Rx IQK mode at mode 3 ; need BB 0xe3c[:] = 3 for path A -0xef 0x800A0 -0x30 0x18000 -0x31 0x0000f -0x32 0xf117b -0xef 0x000A0 -0x00 0x10159 - -//LC calibration start -0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 ====> MP chip can't remark -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x63e70 //RX mode //pc_wang only - +////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F0 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1(80081) for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x6b25d //0x6b25d :spur +0x52 0x7E43E +0x53 0x00073 +0x56 0x51FF3 +0x35 0x00092 +0x35 0x00192 //CCK DY swing TX EVM +0x35 0x00292 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x8BD00 //TX IMR 4Be00 +0X19 0x739d0 +// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step +//0X34 0x0aff4 +//0X34 0x09ff7 +//0X34 0x08fea +//0X34 0x07fed +//0X34 0x06fe0 +//0X34 0x05fe1 +//0X34 0x045e0 +//0X34 0x031ef +//0X34 0x020eb +//0X34 0x010ee +//0X34 0x0006a + +//Tx gain PAD-2dB 3dB/step for 80M clk spur +//0x34 0x0adf4 +//0x34 0x09df7 +//0x34 0x08dea //0x08dea +//0x34 0x07ded +//0x34 0x06de0 +//0x34 0x05ced +//0x34 0x04ce0 +//0x34 0x034e0 +//0x34 0x0246d +//0x34 0x01460 +//0x34 0x0006f + +//For MP Chip power saving (92EE) +0x34 0xadd5 +0x34 0x9dd2 +0x34 0x8dcf +0x34 0x7dcc +0x34 0x6dc9 +0x34 0x54d0 //0x5cea +0x34 0x44cd //0x4ce7 +0x34 0x34ca //0x34e7 +0x34 0x244d //0x246a +0x34 0x144a //0x1467 +0x34 0x004f //0x0068 + +// FOR 1dB step -5dB +//0x34 0x0ade8 +//0x34 0x09de9 +//0x34 0x08dea +//0x34 0x07deb +//0x34 0x06dec +//0x34 0x05ded +//0x34 0x04dee +//0x34 0x03def +//0x34 0x02de0 +//0x34 0x01de1 +//0x34 0x00de2 + +//FOR 1dB step -10dB +//0x34 0x0aded +//0x34 0x09dee +//0x34 0x08def +//0x34 0x07de0 +//0x34 0x06de1 +//0x34 0x05de2 +//0x34 0x04de3 +//0x34 0x03de4 +//0x34 0x02de5 +//0x34 0x01de7 +//0x34 0x00de7 + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68002 // update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5efa0 //54fb0 +0x3b 0x40060 // CS gain table +0x3b 0x30890 +0x3b 0x20080 +0x3b 0x1f060 +0x3b 0x0ffb0 +0xef 0x000A0 //Rx gaintable WEb + +// write RF Rx mode at mode 6 ; need BB 0x824[22:20] = 6 for path A +0xef 0x800A0 +0x30 0x30000 +0x31 0x0000f +0x32 0x77f82 +0xef 0x000A0 +0x00 0x10159 + +// write RF Rx IQK mode at mode 3 ; need BB 0xe3c[:] = 3 for path A +0xef 0x800A0 +0x30 0x18000 +0x31 0x0000f +0x32 0xf117b +0xef 0x000A0 +0x00 0x10159 + +//LC calibration start +0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 ====> MP chip can't remark +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x63e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Emp.txt old mode 100755 new mode 100644 index 10455069a6e..8c7cc7faacf --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192Emp.txt @@ -1,127 +1,127 @@ -//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] -0x1B 0x0394C //(121226): default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? -0xBB 0x00400 -0xBC 0x00078 -0xBD 0xB3333 -0xBE 0x33340 -0xBF 0x00000 -0xC0 0x05999 -0xC1 0x09999 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -0x1C 0x00000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e2 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0014e // LNA switch by BB control modified by Hillo -0x87 0x49f80 // modified by Hillo -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf02b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x78730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918): RC calibration : 1b[4] 1b[1] +0x1B 0x0394C //(121226): default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x90001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor check 40M spur for CH7? +0xBB 0x00400 +0xBC 0x00078 +0xBD 0xB3333 +0xBE 0x33340 +0xBF 0x00000 +0xC0 0x05999 +0xC1 0x09999 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +0x1C 0x00000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e2 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0014e // LNA switch by BB control modified by Hillo +0x87 0x49f80 // modified by Hillo +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf02b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x78730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192EmpA.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192EmpA.txt index 1878b2669da..12953d91e21 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192EmpA.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioA_8192EmpA.txt @@ -1,121 +1,121 @@ -//RTL8192E_MAC_PHY_Parameter_v010_MP_20130320 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB_filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1B 0x00064 //(121226): default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 -0xB0 0xFF9F1 // 0xFF9F0 -0xB1 0x55418 -0xB2 0x8CC00 //VCO current -0xB4 0x43083 //KVCO -0xB5 0x08166 //5G LO buffier increase current -0xB6 0x0803E // SDM neg edge -0xB7 0x1C69f //LPF -0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily -0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily -0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor -0xBB 0x00400 -0xBF 0xC0000 -0xC2 0x02400 -0xC3 0x00009 -0xC4 0x40C91 -0xC5 0x99999 -0xC6 0x000A3 -0xC7 0x88820 -0xC8 0x76C06 -0xC9 0x00000 -0xCA 0x80000 -//0xB6 0x0803E -//0xB2 0x8CC00 //VCO current - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E45E -0x53 0x00071 // [1:0] for Tx EVM shrink -0x56 0x51FF3 -0x35 0x000a8 // a8=ba -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving (92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x54d2 //0x5cea -0x34 0x44cf //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0051 //0x0068 - - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // update by Hillo for better IMR -0x86 0x0014e // LNA switch by BB control modified by Hillo -0x87 0x48e00 // modified by Hillo -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x7c730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 //54fb0 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x30090 -0x3b 0x20080 -0x3b 0x1f060 -0x3b 0x0ffb0 -0xef 0x000A0 //Rx gaintable WEb - - -0xfe -//LC calibration start -//0xb1 0x55400 -0x18 0x0fc07 //LC calibration -0xfe -0xfe -0xfe -0xfe - -//0xb1 0x55418 -//LC calibration end - -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v010_MP_20130320 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB_filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1B 0x00064 //(121226): default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 +0xB0 0xFF9F1 // 0xFF9F0 +0xB1 0x55418 +0xB2 0x8CC00 //VCO current +0xB4 0x43083 //KVCO +0xB5 0x08166 //5G LO buffier increase current +0xB6 0x0803E // SDM neg edge +0xB7 0x1C69f //LPF +0xB8 0x0407F //LPF Defalt:080FF reduce R3 (121005) RDC Lily +0xB9 0x80001 //Defalt:80001 CV curve offset +1 for 25C (121005) RDC Lily +0xBA 0x40001 //0x40000 : SDM 3 change 2 order for in-band noise floor +0xBB 0x00400 +0xBF 0xC0000 +0xC2 0x02400 +0xC3 0x00009 +0xC4 0x40C91 +0xC5 0x99999 +0xC6 0x000A3 +0xC7 0x88820 +0xC8 0x76C06 +0xC9 0x00000 +0xCA 0x80000 +//0xB6 0x0803E +//0xB2 0x8CC00 //VCO current + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E45E +0x53 0x00071 // [1:0] for Tx EVM shrink +0x56 0x51FF3 +0x35 0x000a8 // a8=ba +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving (92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x54d2 //0x5cea +0x34 0x44cf //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0051 //0x0068 + + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // update by Hillo for better IMR +0x86 0x0014e // LNA switch by BB control modified by Hillo +0x87 0x48e00 // modified by Hillo +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x7c730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 //54fb0 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x30090 +0x3b 0x20080 +0x3b 0x1f060 +0x3b 0x0ffb0 +0xef 0x000A0 //Rx gaintable WEb + + +0xfe +//LC calibration start +//0xb1 0x55400 +0x18 0x0fc07 //LC calibration +0xfe +0xfe +0xfe +0xfe + +//0xb1 0x55418 +//LC calibration end + +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E.txt old mode 100755 new mode 100644 index 7cc9d829088..d7011154f3f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E.txt @@ -1,169 +1,169 @@ -////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x6b25d //0x6b25d :spur -0x52 0x7E43e -0x53 0x00073 -0x56 0x51FF3 -0x35 0x00092 -0x35 0x00192 //CCK DY swing TX EVM -0x35 0x00292 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x8ec80 //TX IMR 4Be00 -0X19 0x739d0 - -// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step -//0X34 0x0aff4 -//0X34 0x09ff7 -//0X34 0x08fea -//0X34 0x07fed -//0X34 0x06fe0 -//0X34 0x05fe1 -//0X34 0x045e0 -//0X34 0x031ef -//0X34 0x020eb -//0X34 0x010ee -//0X34 0x0006a - -//Tx gain PAD-2dB 3dB/step for 80M clk spur -//0x34 0x0adf4 -//0x34 0x09df7 -//0x34 0x08dea //0x08dea -//0x34 0x07ded -//0x34 0x06de0 -//0x34 0x05ced -//0x34 0x04ce0 -//0x34 0x034e0 -//0x34 0x0246d -//0x34 0x01460 -//0x34 0x0006f - -//For MP Chip power saving(92EE) -0x34 0xadd5 -0x34 0x9dd2 -0x34 0x8dcf -0x34 0x7dcc -0x34 0x6dc9 -0x34 0x54d0 //0x5cea -0x34 0x44cd //0x4ce7 -0x34 0x34ca //0x34e7 -0x34 0x244d //0x246a -0x34 0x144a //0x1467 -0x34 0x004f //0x0068 - -//0x34 0xadf3 -//0x34 0x9df0 -//0x34 0x8ded -//0x34 0x7dea -//0x34 0x6de7 -//0x34 0x54ee //0x5cea -//0x34 0x44eb //0x4ce7 -//0x34 0x34e8 //0x34e7 -//0x34 0x246b //0x246a -//0x34 0x1468 //0x1467 -//0x34 0x006d //0x0068 - -// FOR 1dB step -5dB -//0x34 0x0ade8 -//0x34 0x09de9 -//0x34 0x08dea -//0x34 0x07deb -//0x34 0x06dec -//0x34 0x05ded -//0x34 0x04dee -//0x34 0x03def -//0x34 0x02de0 -//0x34 0x01de1 -//0x34 0x00de2 - -//FOR 1dB step -10dB -//0x34 0x0aded -//0x34 0x09dee -//0x34 0x08def -//0x34 0x07de0 -//0x34 0x06de1 -//0x34 0x05de2 -//0x34 0x04de3 -//0x34 0x03de4 -//0x34 0x02de5 -//0x34 0x01de7 -//0x34 0x00de7 - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68002 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x782b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5efa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40060 // CS gain table -0x3b 0x30890 -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -// change RF Rx mode table3 to 6 need BB 0x82C[22:20] = 6 -//0xef 0x800A0 -//0x30 0x30000 -//0x31 0x0000f -//0x32 0x77f82 -//0xef 0x000A0 - -// write RF Rx IQK mode at mode 3 ; need BB 0xe5c[:] = 3 for path B -//0xef 0x800A0 -//0x30 0x18000 -//0x31 0x0000f -//0x32 0xf117b -//0xef 0x000A0 -//0x00 0x10159 - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x6b25d //0x6b25d :spur +0x52 0x7E43e +0x53 0x00073 +0x56 0x51FF3 +0x35 0x00092 +0x35 0x00192 //CCK DY swing TX EVM +0x35 0x00292 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x8ec80 //TX IMR 4Be00 +0X19 0x739d0 + +// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step +//0X34 0x0aff4 +//0X34 0x09ff7 +//0X34 0x08fea +//0X34 0x07fed +//0X34 0x06fe0 +//0X34 0x05fe1 +//0X34 0x045e0 +//0X34 0x031ef +//0X34 0x020eb +//0X34 0x010ee +//0X34 0x0006a + +//Tx gain PAD-2dB 3dB/step for 80M clk spur +//0x34 0x0adf4 +//0x34 0x09df7 +//0x34 0x08dea //0x08dea +//0x34 0x07ded +//0x34 0x06de0 +//0x34 0x05ced +//0x34 0x04ce0 +//0x34 0x034e0 +//0x34 0x0246d +//0x34 0x01460 +//0x34 0x0006f + +//For MP Chip power saving(92EE) +0x34 0xadd5 +0x34 0x9dd2 +0x34 0x8dcf +0x34 0x7dcc +0x34 0x6dc9 +0x34 0x54d0 //0x5cea +0x34 0x44cd //0x4ce7 +0x34 0x34ca //0x34e7 +0x34 0x244d //0x246a +0x34 0x144a //0x1467 +0x34 0x004f //0x0068 + +//0x34 0xadf3 +//0x34 0x9df0 +//0x34 0x8ded +//0x34 0x7dea +//0x34 0x6de7 +//0x34 0x54ee //0x5cea +//0x34 0x44eb //0x4ce7 +//0x34 0x34e8 //0x34e7 +//0x34 0x246b //0x246a +//0x34 0x1468 //0x1467 +//0x34 0x006d //0x0068 + +// FOR 1dB step -5dB +//0x34 0x0ade8 +//0x34 0x09de9 +//0x34 0x08dea +//0x34 0x07deb +//0x34 0x06dec +//0x34 0x05ded +//0x34 0x04dee +//0x34 0x03def +//0x34 0x02de0 +//0x34 0x01de1 +//0x34 0x00de2 + +//FOR 1dB step -10dB +//0x34 0x0aded +//0x34 0x09dee +//0x34 0x08def +//0x34 0x07de0 +//0x34 0x06de1 +//0x34 0x05de2 +//0x34 0x04de3 +//0x34 0x03de4 +//0x34 0x02de5 +//0x34 0x01de7 +//0x34 0x00de7 + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68002 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x782b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5efa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40060 // CS gain table +0x3b 0x30890 +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +// change RF Rx mode table3 to 6 need BB 0x82C[22:20] = 6 +//0xef 0x800A0 +//0x30 0x30000 +//0x31 0x0000f +//0x32 0x77f82 +//0xef 0x000A0 + +// write RF Rx IQK mode at mode 3 ; need BB 0xe5c[:] = 3 for path B +//0xef 0x800A0 +//0x30 0x18000 +//0x31 0x0000f +//0x32 0xf117b +//0xef 0x000A0 +//0x00 0x10159 + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES.txt index aeb7ed40b1e..f1346ffa001 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x00064 //(121226) : default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 -0x1C 0x00000 -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x49f80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf52b0 // 0xf82b0 for CCK ACPR -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x70730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v029_MP_20140219 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x00064 //(121226) : default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 +0x1C 0x00000 +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x49f80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf52b0 // 0xf82b0 for CCK ACPR +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x70730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES_extlna.txt index 5c01b74ae2f..e8b1ba793de 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192ES_extlna.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x000F4 -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 -0x1C 0x00000 -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x0014E // LNA switch by BB control -0x87 0x49F80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xF0730 -0x3b 0xE0730 -0x3b 0xD0020 -0x3b 0xC0020 -0x3b 0xB0760 -0x3b 0xA0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x707b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - -0xffff 0xffff +//RTL8192E_MAC_PHY_Parameter_v036_MP_20140812 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x000F4 +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 +0x1C 0x00000 +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x0014E // LNA switch by BB control +0x87 0x49F80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xF0730 +0x3b 0xE0730 +0x3b 0xD0020 +0x3b 0xC0020 +0x3b 0xB0760 +0x3b 0xA0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x707b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extlna.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extlna.txt old mode 100755 new mode 100644 index 8fa2b19eac1..62c18d4a925 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extlna.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extlna.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x0146c -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 -0x1C 0x00000 -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x14e -0x87 0x49f80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xF0730 -0x3b 0xE0730 -0x3b 0xD0020 -0x3b 0xC0020 -0x3b 0xB0760 -0x3b 0xA0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v042_MP_20141222 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x0146c +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 +0x1C 0x00000 +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x14e +0x87 0x49f80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xF0730 +0x3b 0xE0730 +0x3b 0xD0020 +0x3b 0xC0020 +0x3b 0xB0760 +0x3b 0xA0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extpa.txt old mode 100755 new mode 100644 index 5bd193e812a..c91def30090 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_extpa.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x0146C //(121226) : default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x79f80 //0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf07b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x0146C //(121226) : default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x79f80 //0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf07b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_hp.txt old mode 100755 new mode 100644 index 98b691968bd..fc4a1c251b7 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192E_hp.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x00064 //(121226) : default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xa093 -0x34 0x908f -0x34 0x808c -0x34 0x704d -0x34 0x604a -0x34 0x5047 -0x34 0x400a -0x34 0x3007 -0x34 0x2004 -0x34 0x1001 -0x34 0x0000 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x0010e // LNA switch by BB control -0x87 0x4fd80 //0xf5f80 //0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf07b0 -0x3b 0xe0730 -0x3b 0xd0020 -0x3b 0xc0020 -0x3b 0xb0760 -0x3b 0xa0010 -0x3b 0x90000 -0x3b 0x80000 -0x3b 0x787b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v023_MP_20130910 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x00064 //(121226) : default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xa093 +0x34 0x908f +0x34 0x808c +0x34 0x704d +0x34 0x604a +0x34 0x5047 +0x34 0x400a +0x34 0x3007 +0x34 0x2004 +0x34 0x1001 +0x34 0x0000 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x0010e // LNA switch by BB control +0x87 0x4fd80 //0xf5f80 //0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf07b0 +0x3b 0xe0730 +0x3b 0xd0020 +0x3b 0xc0020 +0x3b 0xb0760 +0x3b 0xa0010 +0x3b 0x90000 +0x3b 0x80000 +0x3b 0x787b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Eb.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Eb.txt old mode 100755 new mode 100644 index 0b5c5ca2942..0315b1d70e6 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Eb.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Eb.txt @@ -1,166 +1,166 @@ -////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x83 0x00000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x6b25d //0x6b25d :spur -0x52 0x7E43e -0x53 0x00073 -0x56 0x51FF3 -0x35 0x00092 -0x35 0x00192 //CCK DY swing TX EVM -0x35 0x00292 //OFDM -0x36 0x01C24 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x8ec80 //TX IMR 4Be00 -0X19 0x739d0 - -// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step -//0X34 0x0aff4 -//0X34 0x09ff7 -//0X34 0x08fea -//0X34 0x07fed -//0X34 0x06fe0 -//0X34 0x05fe1 -//0X34 0x045e0 -//0X34 0x031ef -//0X34 0x020eb -//0X34 0x010ee -//0X34 0x0006a - -//Tx gain PAD-2dB 3dB/step for 80M clk spur -//0x34 0x0adf4 -//0x34 0x09df7 -//0x34 0x08dea //0x08dea -//0x34 0x07ded -//0x34 0x06de0 -//0x34 0x05ced -//0x34 0x04ce0 -//0x34 0x034e0 -//0x34 0x0246d -//0x34 0x01460 -//0x34 0x0006f - -//For MP Chip power saving(92EE) -0x34 0xadd5 -0x34 0x9dd2 -0x34 0x8dcf -0x34 0x7dcc -0x34 0x6dc9 -0x34 0x54d0 //0x5cea -0x34 0x44cd //0x4ce7 -0x34 0x34ca //0x34e7 -0x34 0x244d //0x246a -0x34 0x144a //0x1467 -0x34 0x004f //0x0068 - -//0x34 0xadf3 -//0x34 0x9df0 -//0x34 0x8ded -//0x34 0x7dea -//0x34 0x6de7 -//0x34 0x54ee //0x5cea -//0x34 0x44eb //0x4ce7 -//0x34 0x34e8 //0x34e7 -//0x34 0x246b //0x246a -//0x34 0x1468 //0x1467 -//0x34 0x006d //0x0068 - -// FOR 1dB step -5dB -//0x34 0x0ade8 -//0x34 0x09de9 -//0x34 0x08dea -//0x34 0x07deb -//0x34 0x06dec -//0x34 0x05ded -//0x34 0x04dee -//0x34 0x03def -//0x34 0x02de0 -//0x34 0x01de1 -//0x34 0x00de2 - -//FOR 1dB step -10dB -//0x34 0x0aded -//0x34 0x09dee -//0x34 0x08def -//0x34 0x07de0 -//0x34 0x06de1 -//0x34 0x05de2 -//0x34 0x04de3 -//0x34 0x03de4 -//0x34 0x02de5 -//0x34 0x01de7 -//0x34 0x00de7 - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68002 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5efa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40060 // CS gain table -0x3b 0x30890 -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - - -// change RF Rx mode table3 to 6 need BB 0x82C[22:20] = 6 -0xef 0x800A0 -0x30 0x30000 -0x31 0x0000f -0x32 0x77f82 -0xef 0x000A0 - -// write RF Rx IQK mode at mode 3 ; need BB 0xe5c[:] = 3 for path B -0xef 0x800A0 -0x30 0x18000 -0x31 0x0000f -0x32 0xf117b -0xef 0x000A0 -0x00 0x10159 - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x63e70 //RX mode //pc_wang only - +////RLE0560A 92EE test chip 20121005 modify RF VCO CV curve +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x83 0x00000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x6b25d //0x6b25d :spur +0x52 0x7E43e +0x53 0x00073 +0x56 0x51FF3 +0x35 0x00092 +0x35 0x00192 //CCK DY swing TX EVM +0x35 0x00292 //OFDM +0x36 0x01C24 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x8ec80 //TX IMR 4Be00 +0X19 0x739d0 + +// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step +//0X34 0x0aff4 +//0X34 0x09ff7 +//0X34 0x08fea +//0X34 0x07fed +//0X34 0x06fe0 +//0X34 0x05fe1 +//0X34 0x045e0 +//0X34 0x031ef +//0X34 0x020eb +//0X34 0x010ee +//0X34 0x0006a + +//Tx gain PAD-2dB 3dB/step for 80M clk spur +//0x34 0x0adf4 +//0x34 0x09df7 +//0x34 0x08dea //0x08dea +//0x34 0x07ded +//0x34 0x06de0 +//0x34 0x05ced +//0x34 0x04ce0 +//0x34 0x034e0 +//0x34 0x0246d +//0x34 0x01460 +//0x34 0x0006f + +//For MP Chip power saving(92EE) +0x34 0xadd5 +0x34 0x9dd2 +0x34 0x8dcf +0x34 0x7dcc +0x34 0x6dc9 +0x34 0x54d0 //0x5cea +0x34 0x44cd //0x4ce7 +0x34 0x34ca //0x34e7 +0x34 0x244d //0x246a +0x34 0x144a //0x1467 +0x34 0x004f //0x0068 + +//0x34 0xadf3 +//0x34 0x9df0 +//0x34 0x8ded +//0x34 0x7dea +//0x34 0x6de7 +//0x34 0x54ee //0x5cea +//0x34 0x44eb //0x4ce7 +//0x34 0x34e8 //0x34e7 +//0x34 0x246b //0x246a +//0x34 0x1468 //0x1467 +//0x34 0x006d //0x0068 + +// FOR 1dB step -5dB +//0x34 0x0ade8 +//0x34 0x09de9 +//0x34 0x08dea +//0x34 0x07deb +//0x34 0x06dec +//0x34 0x05ded +//0x34 0x04dee +//0x34 0x03def +//0x34 0x02de0 +//0x34 0x01de1 +//0x34 0x00de2 + +//FOR 1dB step -10dB +//0x34 0x0aded +//0x34 0x09dee +//0x34 0x08def +//0x34 0x07de0 +//0x34 0x06de1 +//0x34 0x05de2 +//0x34 0x04de3 +//0x34 0x03de4 +//0x34 0x02de5 +//0x34 0x01de7 +//0x34 0x00de7 + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68002 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5efa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40060 // CS gain table +0x3b 0x30890 +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + + +// change RF Rx mode table3 to 6 need BB 0x82C[22:20] = 6 +0xef 0x800A0 +0x30 0x30000 +0x31 0x0000f +0x32 0x77f82 +0xef 0x000A0 + +// write RF Rx IQK mode at mode 3 ; need BB 0xe5c[:] = 3 for path B +0xef 0x800A0 +0x30 0x18000 +0x31 0x0000f +0x32 0xf117b +0xef 0x000A0 +0x00 0x10159 + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x63e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Emp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Emp.txt old mode 100755 new mode 100644 index 1a521637b52..7ecc84d399c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Emp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192Emp.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] -0x1B 0x0394C //(121226) : default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 -0x1C 0x00000 -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000a8 -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002a8 //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x5dc8 //0x5cea -0x34 0x4dc5 //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0014 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x49f80 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf02b0 // 0xf82b0 for CCK ACPR -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x78730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x37090 // C-cut -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v043_MP_20141229 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] 1b[1] +0x1B 0x0394C //(121226) : default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 +0x1C 0x00000 +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000a8 +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002a8 //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x5dc8 //0x5cea +0x34 0x4dc5 //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0014 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x49f80 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf02b0 // 0xf82b0 for CCK ACPR +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x78730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x37090 // C-cut +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192EmpA.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192EmpA.txt index 70278463461..789f5117eac 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192EmpA.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/RadioB_8192EmpA.txt @@ -1,93 +1,93 @@ -//RTL8192E_MAC_PHY_Parameter_v010_MP_20130320 -0x7F 0x00082 // for C cut POW_SYN -0x81 0x3FC00 // for C cut POW_BB filter -0x00 0x30000 -0x08 0x08400 //DC leakage -0x18 0x00407 -0x19 0x00012 //(120918):RC calibration : 1b[4] -0x1B 0x00064 //(121226) : default 00 for CCK ACPR -0x1E 0x80009 -0x1F 0x00880 -0x2F 0x1A060 -0x3F 0x00000 -0x42 0x060C0 -0x57 0xd0000 //for 80M OFDM(right) spur -0x58 0xBE180 -0x67 0x01552 -0x7F 0x00082 // for C cut -0x81 0x3F000 // for C cut -0x83 0x00000 - -//phking -0xDF 0x00180 -0xEF 0x001a0 -0x51 0x69545 //0x6b25d :spur -0x52 0x7E42e -0x53 0x00071 -0x56 0x51FF3 -0x35 0x000aa -0x35 0x001e0 //CCK DY swing TX EVM -0x35 0x002aa //OFDM -0x36 0x01Ca8 -0x36 0x09C24 -0x36 0x11C24 -0x36 0x19C24 - -0x18 0x00C07 -0X5A 0x48000 //TX IMR 4Be00 // 8bd00 -0X19 0x739d0 - - -//For MP Chip power saving(92EE) -0x34 0xadd7 -0x34 0x9dd4 -0x34 0x8dd1 -0x34 0x7dce -0x34 0x6dcb -0x34 0x54d2 //0x5cea -0x34 0x44cf //0x4ce7 -0x34 0x34cc //0x34e7 -0x34 0x244f //0x246a -0x34 0x144c //0x1467 -0x34 0x0051 //0x0068 - - -//phking -0x00 0x30159 //RX mode -// RX setting 20111118 -0x84 0x68180 // Update by Hillo for better IMR -0x86 0x000ce // LNA switch by BB control -0x87 0x48a00 -0x8e 0x65540 -0x8f 0x88000 -// RX gain table 20111118 -0xef 0x020A0 //Rx gaintable WE -0x3b 0xf82b0 -0x3b 0xef7b0 -0x3b 0xd4fb0 -0x3b 0xcf060 -0x3b 0xb0090 -0x3b 0xa0080 -0x3b 0x90080 -0x3b 0x8f780 -0x3b 0x7c730 // update for CS 0x7c2b0 -0x3b 0x60fb0 // CS gain table -0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 -0x3b 0x40620 // update for CS 0x407a0 // CS gain table -0x3b 0x30090 -0x3b 0x20080 -0x3b 0x1f060 // HG for CCK -0x3b 0x0ffb0 // ULG for CCK -0xef 0x000A0 //Rx gaintable WEb - -0x00 0x10159 //standby mode -//0x18 0x0f407 //LC calibration only @ path A -0xfe -0xfe -0xfe -0xfe -0x1e 0x00001 -0x1f 0x80000 -0x00 0x33e70 //RX mode //pc_wang only - +//RTL8192E_MAC_PHY_Parameter_v010_MP_20130320 +0x7F 0x00082 // for C cut POW_SYN +0x81 0x3FC00 // for C cut POW_BB filter +0x00 0x30000 +0x08 0x08400 //DC leakage +0x18 0x00407 +0x19 0x00012 //(120918):RC calibration : 1b[4] +0x1B 0x00064 //(121226) : default 00 for CCK ACPR +0x1E 0x80009 +0x1F 0x00880 +0x2F 0x1A060 +0x3F 0x00000 +0x42 0x060C0 +0x57 0xd0000 //for 80M OFDM(right) spur +0x58 0xBE180 +0x67 0x01552 +0x7F 0x00082 // for C cut +0x81 0x3F000 // for C cut +0x83 0x00000 + +//phking +0xDF 0x00180 +0xEF 0x001a0 +0x51 0x69545 //0x6b25d :spur +0x52 0x7E42e +0x53 0x00071 +0x56 0x51FF3 +0x35 0x000aa +0x35 0x001e0 //CCK DY swing TX EVM +0x35 0x002aa //OFDM +0x36 0x01Ca8 +0x36 0x09C24 +0x36 0x11C24 +0x36 0x19C24 + +0x18 0x00C07 +0X5A 0x48000 //TX IMR 4Be00 // 8bd00 +0X19 0x739d0 + + +//For MP Chip power saving(92EE) +0x34 0xadd7 +0x34 0x9dd4 +0x34 0x8dd1 +0x34 0x7dce +0x34 0x6dcb +0x34 0x54d2 //0x5cea +0x34 0x44cf //0x4ce7 +0x34 0x34cc //0x34e7 +0x34 0x244f //0x246a +0x34 0x144c //0x1467 +0x34 0x0051 //0x0068 + + +//phking +0x00 0x30159 //RX mode +// RX setting 20111118 +0x84 0x68180 // Update by Hillo for better IMR +0x86 0x000ce // LNA switch by BB control +0x87 0x48a00 +0x8e 0x65540 +0x8f 0x88000 +// RX gain table 20111118 +0xef 0x020A0 //Rx gaintable WE +0x3b 0xf82b0 +0x3b 0xef7b0 +0x3b 0xd4fb0 +0x3b 0xcf060 +0x3b 0xb0090 +0x3b 0xa0080 +0x3b 0x90080 +0x3b 0x8f780 +0x3b 0x7c730 // update for CS 0x7c2b0 +0x3b 0x60fb0 // CS gain table +0x3b 0x5ffa0 // 0x54fb0 update by Gary 120921 +0x3b 0x40620 // update for CS 0x407a0 // CS gain table +0x3b 0x30090 +0x3b 0x20080 +0x3b 0x1f060 // HG for CCK +0x3b 0x0ffb0 // ULG for CCK +0xef 0x000A0 //Rx gaintable WEb + +0x00 0x10159 //standby mode +//0x18 0x0f407 //LC calibration only @ path A +0xfe +0xfe +0xfe +0xfe +0x1e 0x00001 +0x1f 0x80000 +0x00 0x33e70 //RX mode //pc_wang only + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_hp.txt old mode 100755 new mode 100644 index 9fd941e6760..a4042ffea90 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_hp.txt @@ -1,351 +1,351 @@ -//RL6310_MAC_PHY_RF_Parameter_v001_20130131 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// - - -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 25 25 25 -CH02 25 25 25 -CH03 28 28 28 -CH04 28 28 28 -CH05 28 28 28 -CH06 28 28 28 -CH07 28 28 28 -CH08 28 28 28 -CH09 28 28 28 -CH10 25 28 28 -CH11 25 28 28 -CH12 NA 25 28 -CH13 NA 25 25 -CH14 NA NA 25 -## END - -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 24 24 24 -CH02 24 24 24 -CH03 27 27 27 -CH04 27 27 27 -CH05 27 27 27 -CH06 27 27 27 -CH07 27 27 27 -CH08 27 27 27 -CH09 27 27 27 -CH10 24 27 27 -CH11 24 27 27 -CH12 NA 24 24 -CH13 NA 24 24 -CH14 NA NA NA -## END - -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 22 22 22 -CH02 22 22 22 -CH03 25 25 25 -CH04 25 25 25 -CH05 25 25 25 -CH06 25 25 25 -CH07 25 25 25 -CH08 25 25 25 -CH09 25 25 25 -CH10 22 25 25 -CH11 22 25 25 -CH12 NA 22 22 -CH13 NA 22 22 -CH14 NA NA NA -## END - -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 22 22 22 -CH02 22 22 22 -CH03 25 25 25 -CH04 25 25 25 -CH05 25 25 25 -CH06 25 25 25 -CH07 25 25 25 -CH08 25 25 25 -CH09 25 25 25 -CH10 22 25 25 -CH11 22 25 25 -CH12 NA 22 22 -CH13 NA 22 22 -CH14 NA NA NA -## END - -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 22 22 22 -CH04 22 22 22 -CH05 25 25 25 -CH06 25 25 25 -CH07 25 25 25 -CH08 22 25 25 -CH09 22 25 25 -CH10 22 22 22 -CH11 22 22 22 -CH12 NA 22 22 -CH13 NA 22 22 -CH14 NA NA NA -## END - -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 22 22 22 -CH04 22 22 22 -CH05 25 25 25 -CH06 25 25 25 -CH07 25 25 25 -CH08 22 25 25 -CH09 22 25 25 -CH10 22 22 22 -CH11 22 22 22 -CH12 NA 22 22 -CH13 NA 22 22 -CH14 NA NA NA -## END - -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END - -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END - -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END - -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 17 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 17 16 NA -CH159 17 16 NA -## END - -// -//Table 11: =========================================== -// -## 5G;, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END - -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 17 16 NA -## END - -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END - - - - - - - - - - - +//RL6310_MAC_PHY_RF_Parameter_v001_20130131 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// + + +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 25 25 25 +CH02 25 25 25 +CH03 28 28 28 +CH04 28 28 28 +CH05 28 28 28 +CH06 28 28 28 +CH07 28 28 28 +CH08 28 28 28 +CH09 28 28 28 +CH10 25 28 28 +CH11 25 28 28 +CH12 NA 25 28 +CH13 NA 25 25 +CH14 NA NA 25 +## END + +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 24 24 24 +CH02 24 24 24 +CH03 27 27 27 +CH04 27 27 27 +CH05 27 27 27 +CH06 27 27 27 +CH07 27 27 27 +CH08 27 27 27 +CH09 27 27 27 +CH10 24 27 27 +CH11 24 27 27 +CH12 NA 24 24 +CH13 NA 24 24 +CH14 NA NA NA +## END + +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 22 22 22 +CH02 22 22 22 +CH03 25 25 25 +CH04 25 25 25 +CH05 25 25 25 +CH06 25 25 25 +CH07 25 25 25 +CH08 25 25 25 +CH09 25 25 25 +CH10 22 25 25 +CH11 22 25 25 +CH12 NA 22 22 +CH13 NA 22 22 +CH14 NA NA NA +## END + +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 22 22 22 +CH02 22 22 22 +CH03 25 25 25 +CH04 25 25 25 +CH05 25 25 25 +CH06 25 25 25 +CH07 25 25 25 +CH08 25 25 25 +CH09 25 25 25 +CH10 22 25 25 +CH11 22 25 25 +CH12 NA 22 22 +CH13 NA 22 22 +CH14 NA NA NA +## END + +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 22 22 22 +CH04 22 22 22 +CH05 25 25 25 +CH06 25 25 25 +CH07 25 25 25 +CH08 22 25 25 +CH09 22 25 25 +CH10 22 22 22 +CH11 22 22 22 +CH12 NA 22 22 +CH13 NA 22 22 +CH14 NA NA NA +## END + +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 22 22 22 +CH04 22 22 22 +CH05 25 25 25 +CH06 25 25 25 +CH07 25 25 25 +CH08 22 25 25 +CH09 22 25 25 +CH10 22 22 22 +CH11 22 22 22 +CH12 NA 22 22 +CH13 NA 22 22 +CH14 NA NA NA +## END + +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END + +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END + +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END + +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 17 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 17 16 NA +CH159 17 16 NA +## END + +// +//Table 11: =========================================== +// +## 5G;, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END + +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 17 16 NA +## END + +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END + + + + + + + + + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_new.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_new.txt old mode 100755 new mode 100644 index 46355113fea..fba1da51ddd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_new.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TXPWR_LMT_92EE_new.txt @@ -1,351 +1,351 @@ -//RL6310_MAC_PHY_RF_Parameter_v001_20130131 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// - - -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 17 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END - -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 16 16 -CH02 16 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 16 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 16 15 15 -CH06 16 15 15 -CH07 16 15 15 -CH08 16 15 15 -CH09 16 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END - -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END - -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END - -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 17 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 17 16 NA -CH159 17 16 NA -## END - -// -//Table 11: =========================================== -// -## 5G;, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END - -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 17 16 NA -## END - -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END - - - - - - - - - - - +//RL6310_MAC_PHY_RF_Parameter_v001_20130131 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// + + +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 17 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END + +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 16 16 +CH02 16 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 16 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 16 15 15 +CH06 16 15 15 +CH07 16 15 15 +CH08 16 15 15 +CH09 16 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END + +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END + +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END + +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 17 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 17 16 NA +CH159 17 16 NA +## END + +// +//Table 11: =========================================== +// +## 5G;, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END + +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 17 16 NA +## END + +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END + + + + + + + + + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TxPowerTrack_AP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TxPowerTrack_AP.txt old mode 100755 new mode 100644 index e603ac6cd29..f619d06dc1a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TxPowerTrack_AP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/TxPowerTrack_AP.txt @@ -1,38 +1,38 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 -2GCCKA_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 -2GCCKB_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 -2GCCKB_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 - -//============== 2G PathA&B =============== - -2GA_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 -2GA_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 -2GB_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 -2GB_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 1 1 2 2 3 4 5 5 6 7 8 8 9 10 11 11 12 13 14 14 15 15 16 16 17 18 19 19 19 -5GLA_N 1 2 3 3 4 4 5 5 6 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 14 14 14 14 14 -5GLB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 16 17 17 18 19 20 20 20 -5GLB_N 1 1 2 2 3 4 5 5 6 6 7 7 8 8 9 9 10 11 12 12 13 13 14 14 14 14 14 14 14 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 -5GMA_N 1 2 3 3 4 5 6 6 6 7 7 8 8 9 10 11 11 12 13 13 14 15 16 16 16 16 16 16 16 -5GMB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 19 20 20 20 -5GMB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 14 14 14 14 14 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 -5GHA_N 1 2 3 3 4 5 6 6 7 8 9 9 10 10 11 11 12 13 14 14 15 15 16 16 16 16 16 16 16 -5GHB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 +2GCCKA_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 +2GCCKB_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 +2GCCKB_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 + +//============== 2G PathA&B =============== + +2GA_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 +2GA_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 +2GB_P 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 +2GB_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 23 23 23 23 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 1 1 2 2 3 4 5 5 6 7 8 8 9 10 11 11 12 13 14 14 15 15 16 16 17 18 19 19 19 +5GLA_N 1 2 3 3 4 4 5 5 6 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 14 14 14 14 14 +5GLB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 16 17 17 18 19 20 20 20 +5GLB_N 1 1 2 2 3 4 5 5 6 6 7 7 8 8 9 9 10 11 12 12 13 13 14 14 14 14 14 14 14 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 +5GMA_N 1 2 3 3 4 5 6 6 6 7 7 8 8 9 10 11 11 12 13 13 14 15 16 16 16 16 16 16 16 +5GMB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 19 20 20 20 +5GMB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 14 14 14 14 14 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 +5GHA_N 1 2 3 3 4 5 6 6 7 8 9 9 10 10 11 11 12 13 14 14 15 15 16 16 16 16 16 16 16 +5GHB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 21 5GHB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 14 14 14 14 14 \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/rtl8192Efw.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/rtl8192Efw.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8192E/rtl8192EfwMP.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8192E/rtl8192EfwMP.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F.txt old mode 100755 new mode 100644 index 74bb6dad47a..6d6ba95937f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F.txt @@ -1,135 +1,135 @@ -//rtl8197f version = 00 -0xc78 0x0ff0001f // Pin=-110dBm -0xc78 0x0fe0011f // Pin=-108dBm -0xc78 0x0fd0021f // Pin=-106dBm -0xc78 0x0fc0031f // Pin=-104dBm -0xc78 0x0fb0041f // Pin=-102dBm -0xc78 0x0fa0051f // Pin=-100dBm -0xc78 0x0f90061f // Pin=-98dBm -0xc78 0x0f80071f // Pin=-96dBm -0xc78 0x0f70081f // Pin=-94dBm -0xc78 0x0f60091f // Pin=-92dBm -0xc78 0x0f500A1f // Pin=-90dBm -0xc78 0x0f400B1f // Pin=-88dBm -0xc78 0x0f300C1f // Pin=-86dBm -0xc78 0x0f200D1f // Pin=-84dBm -0xc78 0x0f100E1f // Pin=-82dBm -0xc78 0x0f000F1f // Pin=-80dBm -0xc78 0x0ef0101f // Pin=-78dBm -0xc78 0x0ee0111f // Pin=-76dBm -0xc78 0x0ed0121f // Pin=-74dBm -0xc78 0x0ec0131f // Pin=-72dBm -0xc78 0x0eb0141f // Pin=-70dBm -0xc78 0x0ea0151f // Pin=-68dBm -0xc78 0x0e90161f // Pin=-66dBm -0xc78 0x0e80171f // Pin=-64dBm -0xc78 0x0e70181f // Pin=-62dBm -0xc78 0x0e60191f // Pin=-60dBm -0xc78 0x0e501A1f // Pin=-58dBm -0xc78 0x0e401B1f // Pin=-56dBm -0xc78 0x0e301C1f // Pin=-54dBm -0xc78 0x0e201D1f // Pin=-52dBm -0xc78 0x0e101E1f // Pin=-50dBm -0xc78 0x0c401F1f // Pin=-48dBm -0xc78 0x0c30201f // Pin=-46dBm -0xc78 0x0c20211f // Pin=-44dBm -0xc78 0x0c10221f // Pin=-42dBm -0xc78 0x0c00231f // Pin=-40dBm -0xc78 0x0a40241f // Pin=-38dBm -0xc78 0x0a30251f // Pin=-36dBm -0xc78 0x0a20261f // Pin=-34dBm -0xc78 0x0a10271f // Pin=-32dBm -0xc78 0x0a00281f // Pin=-30dBm -0xc78 0x0820291f // Pin=-28dBm -0xc78 0x08102A1f // Pin=-26dBm -0xc78 0x08002B1f // Pin=-24dBm -0xc78 0x06402C1f // Pin=-22dBm -0xc78 0x06302D1f // Pin=-20dBm -0xc78 0x06202E1f // Pin=-18dBm -0xc78 0x06102F1f // Pin=-16dBm -0xc78 0x0420301f // Pin=-14dBm -0xc78 0x0410311f // Pin=-12dBm -0xc78 0x0400321f // Pin=-10dBm -0xc78 0x0240331f // Pin=-08dBm -0xc78 0x0230341f // Pin=-06dBm -0xc78 0x0220351f // Pin=-04dBm -0xc78 0x0210361f // Pin=-02dBm -0xc78 0x0200371f // Pin=-00dBm -0xc78 0x0020381f // Pin=+02dBm -0xc78 0x0010391f // Pin=+04dBm -0xc78 0x00003A1f // Pin=+06dBm -0xc78 0x00003B1f // Pin=+08dBm -0xc78 0x00003C1f // Pin=+10dBm -0xc78 0x00003D1f // Pin=+12dBm -0xc78 0x00003E1f // Pin=+14dBm -0xc78 0x00003F1f // Pin=+16dBm -// AGC_TABLE 2 for CS -0xc78 0x0ff0401f // Pin=-110dBm -0xc78 0x0fe0411f // Pin=-108dBm -0xc78 0x0fd0421f // Pin=-106dBm -0xc78 0x0fc0431f // Pin=-104dBm -0xc78 0x0fb0441f // Pin=-102dBm -0xc78 0x0fa0451f // Pin=-100dBm -0xc78 0x0f90461f // Pin=-98dBm -0xc78 0x0f80471f // Pin=-96dBm -0xc78 0x0f70481f // Pin=-94dBm -0xc78 0x0f60491f // Pin=-92dBm -0xc78 0x0f504a1f // Pin=-90dBm -0xc78 0x0f404b1f // Pin=-88dBm -0xc78 0x0f304c1f // Pin=-86dBm -0xc78 0x0f204d1f // Pin=-84dBm -0xc78 0x0f104e1f // Pin=-82dBm -0xc78 0x0f004f1f // Pin=-80dBm -0xc78 0x0ef0501f // Pin=-78dBm -0xc78 0x0ee0511f // Pin=-76dBm -0xc78 0x0ed0521f // Pin=-74dBm -0xc78 0x0ec0531f // Pin=-72dBm -0xc78 0x0eb0541f // Pin=-70dBm -0xc78 0x0ea0551f // Pin=-68dBm -0xc78 0x0e90561f // Pin=-66dBm -0xc78 0x0e80571f // Pin=-64dBm -0xc78 0x0e70581f // Pin=-62dBm -0xc78 0x0e60591f // Pin=-60dBm -0xc78 0x0e505a1f // Pin=-58dBm -0xc78 0x0e405b1f // Pin=-56dBm -0xc78 0x0e305c1f // Pin=-54dBm -0xc78 0x0e205d1f // Pin=-52dBm -0xc78 0x0e105e1f // Pin=-50dBm -0xc78 0x0c405f1f // Pin=-48dBm -0xc78 0x0c30601f // Pin=-46dBm -0xc78 0x0c20611f // Pin=-44dBm -0xc78 0x0c10621f // Pin=-42dBm -0xc78 0x0c00631f // Pin=-40dBm -0xc78 0x0a40641f // Pin=-38dBm -0xc78 0x0a30651f // Pin=-36dBm -0xc78 0x0a20661f // Pin=-34dBm -0xc78 0x0a10671f // Pin=-32dBm -0xc78 0x0a00681f // Pin=-30dBm -0xc78 0x0820691f // Pin=-28dBm -0xc78 0x08106a1f // Pin=-26dBm -0xc78 0x08006b1f // Pin=-24dBm -0xc78 0x06406c1f // Pin=-22dBm -0xc78 0x06306d1f // Pin=-20dBm -0xc78 0x06206e1f // Pin=-18dBm -0xc78 0x06106f1f // Pin=-16dBm -0xc78 0x0420701f // Pin=-14dBm -0xc78 0x0410711f // Pin=-12dBm -0xc78 0x0400721f // Pin=-10dBm -0xc78 0x0240731f // Pin=-08dBm -0xc78 0x0230741f // Pin=-06dBm -0xc78 0x0220751f // Pin=-04dBm -0xc78 0x0210761f // Pin=-02dBm -0xc78 0x0200771f // Pin=-00dBm -0xc78 0x0020781f // Pin=+02dBm -0xc78 0x0010791f // Pin=+04dBm -0xc78 0x00007a1f // Pin=+06dBm -0xc78 0x00007b1f // Pin=+08dBm -0xc78 0x00007c1f // Pin=+10dBm -0xc78 0x00007d1f // Pin=+12dBm -0xc78 0x00007e1f // Pin=+14dBm -0xc78 0x00007f1f // Pin=+16dBm -0xc50 0x00340022 -0xc50 0x00340020 -0xc58 0x00000022 -0xc58 0x00000020 +//rtl8197f version = 00 +0xc78 0x0ff0001f // Pin=-110dBm +0xc78 0x0fe0011f // Pin=-108dBm +0xc78 0x0fd0021f // Pin=-106dBm +0xc78 0x0fc0031f // Pin=-104dBm +0xc78 0x0fb0041f // Pin=-102dBm +0xc78 0x0fa0051f // Pin=-100dBm +0xc78 0x0f90061f // Pin=-98dBm +0xc78 0x0f80071f // Pin=-96dBm +0xc78 0x0f70081f // Pin=-94dBm +0xc78 0x0f60091f // Pin=-92dBm +0xc78 0x0f500A1f // Pin=-90dBm +0xc78 0x0f400B1f // Pin=-88dBm +0xc78 0x0f300C1f // Pin=-86dBm +0xc78 0x0f200D1f // Pin=-84dBm +0xc78 0x0f100E1f // Pin=-82dBm +0xc78 0x0f000F1f // Pin=-80dBm +0xc78 0x0ef0101f // Pin=-78dBm +0xc78 0x0ee0111f // Pin=-76dBm +0xc78 0x0ed0121f // Pin=-74dBm +0xc78 0x0ec0131f // Pin=-72dBm +0xc78 0x0eb0141f // Pin=-70dBm +0xc78 0x0ea0151f // Pin=-68dBm +0xc78 0x0e90161f // Pin=-66dBm +0xc78 0x0e80171f // Pin=-64dBm +0xc78 0x0e70181f // Pin=-62dBm +0xc78 0x0e60191f // Pin=-60dBm +0xc78 0x0e501A1f // Pin=-58dBm +0xc78 0x0e401B1f // Pin=-56dBm +0xc78 0x0e301C1f // Pin=-54dBm +0xc78 0x0e201D1f // Pin=-52dBm +0xc78 0x0e101E1f // Pin=-50dBm +0xc78 0x0c401F1f // Pin=-48dBm +0xc78 0x0c30201f // Pin=-46dBm +0xc78 0x0c20211f // Pin=-44dBm +0xc78 0x0c10221f // Pin=-42dBm +0xc78 0x0c00231f // Pin=-40dBm +0xc78 0x0a40241f // Pin=-38dBm +0xc78 0x0a30251f // Pin=-36dBm +0xc78 0x0a20261f // Pin=-34dBm +0xc78 0x0a10271f // Pin=-32dBm +0xc78 0x0a00281f // Pin=-30dBm +0xc78 0x0820291f // Pin=-28dBm +0xc78 0x08102A1f // Pin=-26dBm +0xc78 0x08002B1f // Pin=-24dBm +0xc78 0x06402C1f // Pin=-22dBm +0xc78 0x06302D1f // Pin=-20dBm +0xc78 0x06202E1f // Pin=-18dBm +0xc78 0x06102F1f // Pin=-16dBm +0xc78 0x0420301f // Pin=-14dBm +0xc78 0x0410311f // Pin=-12dBm +0xc78 0x0400321f // Pin=-10dBm +0xc78 0x0240331f // Pin=-08dBm +0xc78 0x0230341f // Pin=-06dBm +0xc78 0x0220351f // Pin=-04dBm +0xc78 0x0210361f // Pin=-02dBm +0xc78 0x0200371f // Pin=-00dBm +0xc78 0x0020381f // Pin=+02dBm +0xc78 0x0010391f // Pin=+04dBm +0xc78 0x00003A1f // Pin=+06dBm +0xc78 0x00003B1f // Pin=+08dBm +0xc78 0x00003C1f // Pin=+10dBm +0xc78 0x00003D1f // Pin=+12dBm +0xc78 0x00003E1f // Pin=+14dBm +0xc78 0x00003F1f // Pin=+16dBm +// AGC_TABLE 2 for CS +0xc78 0x0ff0401f // Pin=-110dBm +0xc78 0x0fe0411f // Pin=-108dBm +0xc78 0x0fd0421f // Pin=-106dBm +0xc78 0x0fc0431f // Pin=-104dBm +0xc78 0x0fb0441f // Pin=-102dBm +0xc78 0x0fa0451f // Pin=-100dBm +0xc78 0x0f90461f // Pin=-98dBm +0xc78 0x0f80471f // Pin=-96dBm +0xc78 0x0f70481f // Pin=-94dBm +0xc78 0x0f60491f // Pin=-92dBm +0xc78 0x0f504a1f // Pin=-90dBm +0xc78 0x0f404b1f // Pin=-88dBm +0xc78 0x0f304c1f // Pin=-86dBm +0xc78 0x0f204d1f // Pin=-84dBm +0xc78 0x0f104e1f // Pin=-82dBm +0xc78 0x0f004f1f // Pin=-80dBm +0xc78 0x0ef0501f // Pin=-78dBm +0xc78 0x0ee0511f // Pin=-76dBm +0xc78 0x0ed0521f // Pin=-74dBm +0xc78 0x0ec0531f // Pin=-72dBm +0xc78 0x0eb0541f // Pin=-70dBm +0xc78 0x0ea0551f // Pin=-68dBm +0xc78 0x0e90561f // Pin=-66dBm +0xc78 0x0e80571f // Pin=-64dBm +0xc78 0x0e70581f // Pin=-62dBm +0xc78 0x0e60591f // Pin=-60dBm +0xc78 0x0e505a1f // Pin=-58dBm +0xc78 0x0e405b1f // Pin=-56dBm +0xc78 0x0e305c1f // Pin=-54dBm +0xc78 0x0e205d1f // Pin=-52dBm +0xc78 0x0e105e1f // Pin=-50dBm +0xc78 0x0c405f1f // Pin=-48dBm +0xc78 0x0c30601f // Pin=-46dBm +0xc78 0x0c20611f // Pin=-44dBm +0xc78 0x0c10621f // Pin=-42dBm +0xc78 0x0c00631f // Pin=-40dBm +0xc78 0x0a40641f // Pin=-38dBm +0xc78 0x0a30651f // Pin=-36dBm +0xc78 0x0a20661f // Pin=-34dBm +0xc78 0x0a10671f // Pin=-32dBm +0xc78 0x0a00681f // Pin=-30dBm +0xc78 0x0820691f // Pin=-28dBm +0xc78 0x08106a1f // Pin=-26dBm +0xc78 0x08006b1f // Pin=-24dBm +0xc78 0x06406c1f // Pin=-22dBm +0xc78 0x06306d1f // Pin=-20dBm +0xc78 0x06206e1f // Pin=-18dBm +0xc78 0x06106f1f // Pin=-16dBm +0xc78 0x0420701f // Pin=-14dBm +0xc78 0x0410711f // Pin=-12dBm +0xc78 0x0400721f // Pin=-10dBm +0xc78 0x0240731f // Pin=-08dBm +0xc78 0x0230741f // Pin=-06dBm +0xc78 0x0220751f // Pin=-04dBm +0xc78 0x0210761f // Pin=-02dBm +0xc78 0x0200771f // Pin=-00dBm +0xc78 0x0020781f // Pin=+02dBm +0xc78 0x0010791f // Pin=+04dBm +0xc78 0x00007a1f // Pin=+06dBm +0xc78 0x00007b1f // Pin=+08dBm +0xc78 0x00007c1f // Pin=+10dBm +0xc78 0x00007d1f // Pin=+12dBm +0xc78 0x00007e1f // Pin=+14dBm +0xc78 0x00007f1f // Pin=+16dBm +0xc50 0x00340022 +0xc50 0x00340020 +0xc58 0x00000022 +0xc58 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F_hp.txt old mode 100755 new mode 100644 index 64279ed3efd..90a6b469083 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197F_hp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xfe060001 // Pin=-104dBm -0x81c 0xfd080001 // Pin=-102dBm -0x81c 0xfc0a0001 // Pin=-100dBm -0x81c 0xfb0c0001 // Pin=-98dBm -0x81c 0xfa0e0001 // Pin=-96dBm -0x81c 0xf9100001 // Pin=-94dBm -0x81c 0xf8120001 // Pin=-92dBm -0x81c 0xf7140001 // Pin=-90dBm -0x81c 0xf6160001 // Pin=-88dBm -0x81c 0xf5180001 // Pin=-86dBm -0x81c 0xf41a0001 // Pin=-84dBm -0x81c 0xf31c0001 // Pin=-82dBm -0x81c 0xf21e0001 // Pin=-80dBm -0x81c 0xf1200001 // Pin=-78dBm -0x81c 0xef220001 // Pin=-76dBm -0x81c 0xee240001 // Pin=-74dBm -0x81c 0xed260001 // Pin=-72dBm -0x81c 0xec280001 // Pin=-70dBm -0x81c 0xeb2a0001 // Pin=-68dBm -0x81c 0xea2c0001 // Pin=-66dBm -0x81c 0xe92e0001 // Pin=-64dBm -0x81c 0xe8300001 // Pin=-62dBm -0x81c 0xe7320001 // Pin=-60dBm -0x81c 0xe6340001 // Pin=-58dBm -0x81c 0xc8360001 // Pin=-56dBm -0x81c 0xc7380001 // Pin=-54dBm -0x81c 0xc63a0001 // Pin=-52dBm -0x81c 0xc53c0001 // Pin=-50dBm -0x81c 0xc43e0001 // Pin=-48dBm -0x81c 0xc3400001 // Pin=-46dBm -0x81c 0xc2420001 // Pin=-44dBm -0x81c 0xc1440001 // Pin=-42dBm -0x81c 0xa8460001 // Pin=-40dBm -0x81c 0xa7480001 // Pin=-38dBm -0x81c 0xa64a0001 // Pin=-36dBm -0x81c 0x6a4c0001 // Pin=-34dBm -0x81c 0x694e0001 // Pin=-32dBm -0x81c 0x68500001 // Pin=-30dBm -0x81c 0x67520001 // Pin=-28dBm -0x81c 0x66540001 // Pin=-26dBm -0x81c 0x65560001 // Pin=-24dBm -0x81c 0x64580001 // Pin=-22dBm -0x81c 0x635a0001 // Pin=-20dBm -0x81c 0x475c0001 // Pin=-18dBm -0x81c 0x465e0001 // Pin=-16dBm -0x81c 0x45600001 // Pin=-14dBm -0x81c 0x44620001 // Pin=-12dBm -0x81c 0x43640001 // Pin=-10dBm -0x81c 0x42660001 // Pin=-08dBm -0x81c 0x41680001 // Pin=-06dBm -0x81c 0x416a0001 // Pin=-04dBm -0x81c 0x416c0001 // Pin=-02dBm -0x81c 0x416e0001 // Pin=-00dBm -0x81c 0x41700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfa000101 // Pin=-110dBm -0x81c 0xf9020101 // Pin=-108dBm -0x81c 0xf8040101 // Pin=-106dBm -0x81c 0xf7060101 // Pin=-104dBm -0x81c 0xf6080101 // Pin=-102dBm -0x81c 0xf50a0101 // Pin=-100dBm -0x81c 0xf40c0101 // Pin=-98dBm -0x81c 0xf30e0101 // Pin=-96dBm -0x81c 0xf2100101 // Pin=-94dBm -0x81c 0xf1120101 // Pin=-92dBm -0x81c 0xf0140101 // Pin=-90dBm -0x81c 0xef160101 // Pin=-88dBm -0x81c 0xee180101 // Pin=-86dBm -0x81c 0xed1a0101 // Pin=-84dBm -0x81c 0xec1c0101 // Pin=-82dBm -0x81c 0xeb1e0101 // Pin=-80dBm -0x81c 0xea200101 // Pin=-78dBm -0x81c 0xe9220101 // Pin=-76dBm -0x81c 0xe8240101 // Pin=-74dBm -0x81c 0xe7260101 // Pin=-72dBm -0x81c 0xe6280101 // Pin=-70dBm -0x81c 0xca2a0101 // Pin=-68dBm -0x81c 0xc92c0101 // Pin=-66dBm -0x81c 0xc82e0101 // Pin=-64dBm -0x81c 0xc7300101 // Pin=-62dBm -0x81c 0xc6320101 // Pin=-60dBm -0x81c 0xc5340101 // Pin=-58dBm -0x81c 0xc4360101 // Pin=-56dBm -0x81c 0xc3380101 // Pin=-54dBm -0x81c 0xc23a0101 // Pin=-52dBm -0x81c 0xa53c0101 // Pin=-50dBm -0x81c 0xa43e0101 // Pin=-48dBm -0x81c 0xa3400101 // Pin=-46dBm -0x81c 0xa2420101 // Pin=-44dBm -0x81c 0x84440101 // Pin=-42dBm -0x81c 0x83460101 // Pin=-40dBm -0x81c 0x82480101 // Pin=-38dBm -0x81c 0x474a0101 // Pin=-36dBm -0x81c 0x464c0101 // Pin=-34dBm -0x81c 0x454e0101 // Pin=-32dBm -0x81c 0x44500101 // Pin=-30dBm -0x81c 0x43520101 // Pin=-28dBm -0x81c 0x25540101 // Pin=-26dBm -0x81c 0x24560101 // Pin=-24dBm -0x81c 0x23580101 // Pin=-22dBm -0x81c 0x225a0101 // Pin=-20dBm -0x81c 0x045c0101 // Pin=-18dBm -0x81c 0x035e0101 // Pin=-16dBm -0x81c 0x02600101 // Pin=-14dBm -0x81c 0x01620101 // Pin=-12dBm -0x81c 0x01640101 // Pin=-10dBm -0x81c 0x01660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xfe060001 // Pin=-104dBm +0x81c 0xfd080001 // Pin=-102dBm +0x81c 0xfc0a0001 // Pin=-100dBm +0x81c 0xfb0c0001 // Pin=-98dBm +0x81c 0xfa0e0001 // Pin=-96dBm +0x81c 0xf9100001 // Pin=-94dBm +0x81c 0xf8120001 // Pin=-92dBm +0x81c 0xf7140001 // Pin=-90dBm +0x81c 0xf6160001 // Pin=-88dBm +0x81c 0xf5180001 // Pin=-86dBm +0x81c 0xf41a0001 // Pin=-84dBm +0x81c 0xf31c0001 // Pin=-82dBm +0x81c 0xf21e0001 // Pin=-80dBm +0x81c 0xf1200001 // Pin=-78dBm +0x81c 0xef220001 // Pin=-76dBm +0x81c 0xee240001 // Pin=-74dBm +0x81c 0xed260001 // Pin=-72dBm +0x81c 0xec280001 // Pin=-70dBm +0x81c 0xeb2a0001 // Pin=-68dBm +0x81c 0xea2c0001 // Pin=-66dBm +0x81c 0xe92e0001 // Pin=-64dBm +0x81c 0xe8300001 // Pin=-62dBm +0x81c 0xe7320001 // Pin=-60dBm +0x81c 0xe6340001 // Pin=-58dBm +0x81c 0xc8360001 // Pin=-56dBm +0x81c 0xc7380001 // Pin=-54dBm +0x81c 0xc63a0001 // Pin=-52dBm +0x81c 0xc53c0001 // Pin=-50dBm +0x81c 0xc43e0001 // Pin=-48dBm +0x81c 0xc3400001 // Pin=-46dBm +0x81c 0xc2420001 // Pin=-44dBm +0x81c 0xc1440001 // Pin=-42dBm +0x81c 0xa8460001 // Pin=-40dBm +0x81c 0xa7480001 // Pin=-38dBm +0x81c 0xa64a0001 // Pin=-36dBm +0x81c 0x6a4c0001 // Pin=-34dBm +0x81c 0x694e0001 // Pin=-32dBm +0x81c 0x68500001 // Pin=-30dBm +0x81c 0x67520001 // Pin=-28dBm +0x81c 0x66540001 // Pin=-26dBm +0x81c 0x65560001 // Pin=-24dBm +0x81c 0x64580001 // Pin=-22dBm +0x81c 0x635a0001 // Pin=-20dBm +0x81c 0x475c0001 // Pin=-18dBm +0x81c 0x465e0001 // Pin=-16dBm +0x81c 0x45600001 // Pin=-14dBm +0x81c 0x44620001 // Pin=-12dBm +0x81c 0x43640001 // Pin=-10dBm +0x81c 0x42660001 // Pin=-08dBm +0x81c 0x41680001 // Pin=-06dBm +0x81c 0x416a0001 // Pin=-04dBm +0x81c 0x416c0001 // Pin=-02dBm +0x81c 0x416e0001 // Pin=-00dBm +0x81c 0x41700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfa000101 // Pin=-110dBm +0x81c 0xf9020101 // Pin=-108dBm +0x81c 0xf8040101 // Pin=-106dBm +0x81c 0xf7060101 // Pin=-104dBm +0x81c 0xf6080101 // Pin=-102dBm +0x81c 0xf50a0101 // Pin=-100dBm +0x81c 0xf40c0101 // Pin=-98dBm +0x81c 0xf30e0101 // Pin=-96dBm +0x81c 0xf2100101 // Pin=-94dBm +0x81c 0xf1120101 // Pin=-92dBm +0x81c 0xf0140101 // Pin=-90dBm +0x81c 0xef160101 // Pin=-88dBm +0x81c 0xee180101 // Pin=-86dBm +0x81c 0xed1a0101 // Pin=-84dBm +0x81c 0xec1c0101 // Pin=-82dBm +0x81c 0xeb1e0101 // Pin=-80dBm +0x81c 0xea200101 // Pin=-78dBm +0x81c 0xe9220101 // Pin=-76dBm +0x81c 0xe8240101 // Pin=-74dBm +0x81c 0xe7260101 // Pin=-72dBm +0x81c 0xe6280101 // Pin=-70dBm +0x81c 0xca2a0101 // Pin=-68dBm +0x81c 0xc92c0101 // Pin=-66dBm +0x81c 0xc82e0101 // Pin=-64dBm +0x81c 0xc7300101 // Pin=-62dBm +0x81c 0xc6320101 // Pin=-60dBm +0x81c 0xc5340101 // Pin=-58dBm +0x81c 0xc4360101 // Pin=-56dBm +0x81c 0xc3380101 // Pin=-54dBm +0x81c 0xc23a0101 // Pin=-52dBm +0x81c 0xa53c0101 // Pin=-50dBm +0x81c 0xa43e0101 // Pin=-48dBm +0x81c 0xa3400101 // Pin=-46dBm +0x81c 0xa2420101 // Pin=-44dBm +0x81c 0x84440101 // Pin=-42dBm +0x81c 0x83460101 // Pin=-40dBm +0x81c 0x82480101 // Pin=-38dBm +0x81c 0x474a0101 // Pin=-36dBm +0x81c 0x464c0101 // Pin=-34dBm +0x81c 0x454e0101 // Pin=-32dBm +0x81c 0x44500101 // Pin=-30dBm +0x81c 0x43520101 // Pin=-28dBm +0x81c 0x25540101 // Pin=-26dBm +0x81c 0x24560101 // Pin=-24dBm +0x81c 0x23580101 // Pin=-22dBm +0x81c 0x225a0101 // Pin=-20dBm +0x81c 0x045c0101 // Pin=-18dBm +0x81c 0x035e0101 // Pin=-16dBm +0x81c 0x02600101 // Pin=-14dBm +0x81c 0x01620101 // Pin=-12dBm +0x81c 0x01640101 // Pin=-10dBm +0x81c 0x01660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp.txt old mode 100755 new mode 100644 index 1f5ce9de5aa..3a807186130 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xfe020001 // Pin=-108dBm -0x81c 0xfd040001 // Pin=-106dBm -0x81c 0xfc060001 // Pin=-104dBm -0x81c 0xfb080001 // Pin=-102dBm -0x81c 0xfa0a0001 // Pin=-100dBm -0x81c 0xf90c0001 // Pin=-98dBm -0x81c 0xf80e0001 // Pin=-96dBm -0x81c 0xf7100001 // Pin=-94dBm -0x81c 0xf6120001 // Pin=-92dBm -0x81c 0xf5140001 // Pin=-90dBm -0x81c 0xf4160001 // Pin=-88dBm -0x81c 0xf3180001 // Pin=-86dBm -0x81c 0xf21a0001 // Pin=-84dBm -0x81c 0xf11c0001 // Pin=-82dBm -0x81c 0xef1e0001 // Pin=-80dBm -0x81c 0xee200001 // Pin=-78dBm -0x81c 0xed220001 // Pin=-76dBm -0x81c 0xec240001 // Pin=-74dBm -0x81c 0xeb260001 // Pin=-72dBm -0x81c 0xea280001 // Pin=-70dBm -0x81c 0xe92a0001 // Pin=-68dBm -0x81c 0xe82c0001 // Pin=-66dBm -0x81c 0xe72e0001 // Pin=-64dBm -0x81c 0xe6300001 // Pin=-62dBm -0x81c 0xe5320001 // Pin=-60dBm -0x81c 0xe4340001 // Pin=-58dBm -0x81c 0xc7360001 // Pin=-56dBm -0x81c 0xc6380001 // Pin=-54dBm -0x81c 0xc53a0001 // Pin=-52dBm -0x81c 0xc43c0001 // Pin=-50dBm -0x81c 0xc33e0001 // Pin=-48dBm -0x81c 0xa5400001 // Pin=-46dBm -0x81c 0xa4420001 // Pin=-44dBm -0x81c 0xa3440001 // Pin=-42dBm -0x81c 0xa2460001 // Pin=-40dBm -0x81c 0x88480001 // Pin=-38dBm -0x81c 0x874a0001 // Pin=-36dBm -0x81c 0x694c0001 // Pin=-34dBm -0x81c 0x684e0001 // Pin=-32dBm -0x81c 0x67500001 // Pin=-30dBm -0x81c 0x66520001 // Pin=-28dBm -0x81c 0x65540001 // Pin=-26dBm -0x81c 0x64560001 // Pin=-24dBm -0x81c 0x63580001 // Pin=-22dBm -0x81c 0x625a0001 // Pin=-20dBm -0x81c 0x455c0001 // Pin=-18dBm -0x81c 0x445e0001 // Pin=-16dBm -0x81c 0x43600001 // Pin=-14dBm -0x81c 0x42620001 // Pin=-12dBm -0x81c 0x28640001 // Pin=-10dBm -0x81c 0x27660001 // Pin=-08dBm -0x81c 0x26680001 // Pin=-06dBm -0x81c 0x256a0001 // Pin=-04dBm -0x81c 0x246c0001 // Pin=-02dBm -0x81c 0x236e0001 // Pin=-00dBm -0x81c 0x22700001 // Pin=+02dBm -0x81c 0x21720001 // Pin=+04dBm -0x81c 0x21740001 // Pin=+06dBm -0x81c 0x21760001 // Pin=+08dBm -0x81c 0x21780001 // Pin=+10dBm -0x81c 0x217a0001 // Pin=+12dBm -0x81c 0x217c0001 // Pin=+14dBm -0x81c 0x217e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xff040101 // Pin=-106dBm -0x81c 0xff060101 // Pin=-104dBm -0x81c 0xff080101 // Pin=-102dBm -0x81c 0xfe0a0101 // Pin=-100dBm -0x81c 0xfd0c0101 // Pin=-98dBm -0x81c 0xfc0e0101 // Pin=-96dBm -0x81c 0xfb100101 // Pin=-94dBm -0x81c 0xfa120101 // Pin=-92dBm -0x81c 0xf9140101 // Pin=-90dBm -0x81c 0xf8160101 // Pin=-88dBm -0x81c 0xf7180101 // Pin=-86dBm -0x81c 0xf61a0101 // Pin=-84dBm -0x81c 0xf51c0101 // Pin=-82dBm -0x81c 0xf41e0101 // Pin=-80dBm -0x81c 0xf3200101 // Pin=-78dBm -0x81c 0xf2220101 // Pin=-76dBm -0x81c 0xf1240101 // Pin=-74dBm -0x81c 0xf0260101 // Pin=-72dBm -0x81c 0xef280101 // Pin=-70dBm -0x81c 0xee2a0101 // Pin=-68dBm -0x81c 0xed2c0101 // Pin=-66dBm -0x81c 0xec2e0101 // Pin=-64dBm -0x81c 0xeb300101 // Pin=-62dBm -0x81c 0xea320101 // Pin=-60dBm -0x81c 0xe9340101 // Pin=-58dBm -0x81c 0xe8360101 // Pin=-56dBm -0x81c 0xe7380101 // Pin=-54dBm -0x81c 0xe63a0101 // Pin=-52dBm -0x81c 0xe53c0101 // Pin=-50dBm -0x81c 0xe43e0101 // Pin=-48dBm -0x81c 0xe3400101 // Pin=-46dBm -0x81c 0xe2420101 // Pin=-44dBm -0x81c 0xc6440101 // Pin=-42dBm -0x81c 0xc5460101 // Pin=-40dBm -0x81c 0xc4480101 // Pin=-38dBm -0x81c 0xc34a0101 // Pin=-36dBm -0x81c 0xc24c0101 // Pin=-34dBm -0x81c 0xa54e0101 // Pin=-32dBm -0x81c 0xa4500101 // Pin=-30dBm -0x81c 0xa3520101 // Pin=-28dBm -0x81c 0xa2540101 // Pin=-26dBm -0x81c 0x84560101 // Pin=-24dBm -0x81c 0x83580101 // Pin=-22dBm -0x81c 0x825a0101 // Pin=-20dBm -0x81c 0x475c0101 // Pin=-18dBm -0x81c 0x465e0101 // Pin=-16dBm -0x81c 0x45600101 // Pin=-14dBm -0x81c 0x44620101 // Pin=-12dBm -0x81c 0x43640101 // Pin=-10dBm -0x81c 0x25660101 // Pin=-08dBm -0x81c 0x24680101 // Pin=-06dBm -0x81c 0x236a0101 // Pin=-04dBm -0x81c 0x226c0101 // Pin=-02dBm -0x81c 0x046e0101 // Pin=-00dBm -0x81c 0x03700101 // Pin=+02dBm -0x81c 0x02720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xfe020001 // Pin=-108dBm +0x81c 0xfd040001 // Pin=-106dBm +0x81c 0xfc060001 // Pin=-104dBm +0x81c 0xfb080001 // Pin=-102dBm +0x81c 0xfa0a0001 // Pin=-100dBm +0x81c 0xf90c0001 // Pin=-98dBm +0x81c 0xf80e0001 // Pin=-96dBm +0x81c 0xf7100001 // Pin=-94dBm +0x81c 0xf6120001 // Pin=-92dBm +0x81c 0xf5140001 // Pin=-90dBm +0x81c 0xf4160001 // Pin=-88dBm +0x81c 0xf3180001 // Pin=-86dBm +0x81c 0xf21a0001 // Pin=-84dBm +0x81c 0xf11c0001 // Pin=-82dBm +0x81c 0xef1e0001 // Pin=-80dBm +0x81c 0xee200001 // Pin=-78dBm +0x81c 0xed220001 // Pin=-76dBm +0x81c 0xec240001 // Pin=-74dBm +0x81c 0xeb260001 // Pin=-72dBm +0x81c 0xea280001 // Pin=-70dBm +0x81c 0xe92a0001 // Pin=-68dBm +0x81c 0xe82c0001 // Pin=-66dBm +0x81c 0xe72e0001 // Pin=-64dBm +0x81c 0xe6300001 // Pin=-62dBm +0x81c 0xe5320001 // Pin=-60dBm +0x81c 0xe4340001 // Pin=-58dBm +0x81c 0xc7360001 // Pin=-56dBm +0x81c 0xc6380001 // Pin=-54dBm +0x81c 0xc53a0001 // Pin=-52dBm +0x81c 0xc43c0001 // Pin=-50dBm +0x81c 0xc33e0001 // Pin=-48dBm +0x81c 0xa5400001 // Pin=-46dBm +0x81c 0xa4420001 // Pin=-44dBm +0x81c 0xa3440001 // Pin=-42dBm +0x81c 0xa2460001 // Pin=-40dBm +0x81c 0x88480001 // Pin=-38dBm +0x81c 0x874a0001 // Pin=-36dBm +0x81c 0x694c0001 // Pin=-34dBm +0x81c 0x684e0001 // Pin=-32dBm +0x81c 0x67500001 // Pin=-30dBm +0x81c 0x66520001 // Pin=-28dBm +0x81c 0x65540001 // Pin=-26dBm +0x81c 0x64560001 // Pin=-24dBm +0x81c 0x63580001 // Pin=-22dBm +0x81c 0x625a0001 // Pin=-20dBm +0x81c 0x455c0001 // Pin=-18dBm +0x81c 0x445e0001 // Pin=-16dBm +0x81c 0x43600001 // Pin=-14dBm +0x81c 0x42620001 // Pin=-12dBm +0x81c 0x28640001 // Pin=-10dBm +0x81c 0x27660001 // Pin=-08dBm +0x81c 0x26680001 // Pin=-06dBm +0x81c 0x256a0001 // Pin=-04dBm +0x81c 0x246c0001 // Pin=-02dBm +0x81c 0x236e0001 // Pin=-00dBm +0x81c 0x22700001 // Pin=+02dBm +0x81c 0x21720001 // Pin=+04dBm +0x81c 0x21740001 // Pin=+06dBm +0x81c 0x21760001 // Pin=+08dBm +0x81c 0x21780001 // Pin=+10dBm +0x81c 0x217a0001 // Pin=+12dBm +0x81c 0x217c0001 // Pin=+14dBm +0x81c 0x217e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xff040101 // Pin=-106dBm +0x81c 0xff060101 // Pin=-104dBm +0x81c 0xff080101 // Pin=-102dBm +0x81c 0xfe0a0101 // Pin=-100dBm +0x81c 0xfd0c0101 // Pin=-98dBm +0x81c 0xfc0e0101 // Pin=-96dBm +0x81c 0xfb100101 // Pin=-94dBm +0x81c 0xfa120101 // Pin=-92dBm +0x81c 0xf9140101 // Pin=-90dBm +0x81c 0xf8160101 // Pin=-88dBm +0x81c 0xf7180101 // Pin=-86dBm +0x81c 0xf61a0101 // Pin=-84dBm +0x81c 0xf51c0101 // Pin=-82dBm +0x81c 0xf41e0101 // Pin=-80dBm +0x81c 0xf3200101 // Pin=-78dBm +0x81c 0xf2220101 // Pin=-76dBm +0x81c 0xf1240101 // Pin=-74dBm +0x81c 0xf0260101 // Pin=-72dBm +0x81c 0xef280101 // Pin=-70dBm +0x81c 0xee2a0101 // Pin=-68dBm +0x81c 0xed2c0101 // Pin=-66dBm +0x81c 0xec2e0101 // Pin=-64dBm +0x81c 0xeb300101 // Pin=-62dBm +0x81c 0xea320101 // Pin=-60dBm +0x81c 0xe9340101 // Pin=-58dBm +0x81c 0xe8360101 // Pin=-56dBm +0x81c 0xe7380101 // Pin=-54dBm +0x81c 0xe63a0101 // Pin=-52dBm +0x81c 0xe53c0101 // Pin=-50dBm +0x81c 0xe43e0101 // Pin=-48dBm +0x81c 0xe3400101 // Pin=-46dBm +0x81c 0xe2420101 // Pin=-44dBm +0x81c 0xc6440101 // Pin=-42dBm +0x81c 0xc5460101 // Pin=-40dBm +0x81c 0xc4480101 // Pin=-38dBm +0x81c 0xc34a0101 // Pin=-36dBm +0x81c 0xc24c0101 // Pin=-34dBm +0x81c 0xa54e0101 // Pin=-32dBm +0x81c 0xa4500101 // Pin=-30dBm +0x81c 0xa3520101 // Pin=-28dBm +0x81c 0xa2540101 // Pin=-26dBm +0x81c 0x84560101 // Pin=-24dBm +0x81c 0x83580101 // Pin=-22dBm +0x81c 0x825a0101 // Pin=-20dBm +0x81c 0x475c0101 // Pin=-18dBm +0x81c 0x465e0101 // Pin=-16dBm +0x81c 0x45600101 // Pin=-14dBm +0x81c 0x44620101 // Pin=-12dBm +0x81c 0x43640101 // Pin=-10dBm +0x81c 0x25660101 // Pin=-08dBm +0x81c 0x24680101 // Pin=-06dBm +0x81c 0x236a0101 // Pin=-04dBm +0x81c 0x226c0101 // Pin=-02dBm +0x81c 0x046e0101 // Pin=-00dBm +0x81c 0x03700101 // Pin=+02dBm +0x81c 0x02720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp_hp.txt old mode 100755 new mode 100644 index 81e3a4a6d05..f472797f264 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/AGC_TAB_8197Fmp_hp.txt @@ -1,271 +1,271 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x81c 0xfe000003 // turn on the table for write data -0x81c 0xff000003 // Pin=-110dBm -0x81c 0xfe020003 // Pin=-108dBm -0x81c 0xfd040003 // Pin=-106dBm -0x81c 0xfc060003 // Pin=-104dBm -0x81c 0xfb080003 // Pin=-102dBm -0x81c 0xfa0a0003 // Pin=-100dBm -0x81c 0xf90c0003 // Pin=-98dBm -0x81c 0xf80e0003 // Pin=-96dBm -0x81c 0xf7100003 // Pin=-94dBm -0x81c 0xf6120003 // Pin=-92dBm -0x81c 0xf5140003 // Pin=-90dBm -0x81c 0xf4160003 // Pin=-88dBm -0x81c 0xf3180003 // Pin=-86dBm -0x81c 0xf21a0003 // Pin=-84dBm -0x81c 0xf11c0003 // Pin=-82dBm -0x81c 0xf01e0003 // Pin=-80dBm -0x81c 0xef200003 // Pin=-78dBm -0x81c 0xee220003 // Pin=-76dBm -0x81c 0xed240003 // Pin=-74dBm -0x81c 0xec260003 // Pin=-72dBm -0x81c 0xeb280003 // Pin=-70dBm -0x81c 0xea2a0003 // Pin=-68dBm -0x81c 0xe92c0003 // Pin=-66dBm -0x81c 0xe82e0003 // Pin=-64dBm -0x81c 0xe7300003 // Pin=-62dBm -0x81c 0xe6320003 // Pin=-60dBm -0x81c 0xe5340003 // Pin=-58dBm -0x81c 0xe4360003 // Pin=-56dBm -0x81c 0xe3380003 // Pin=-54dBm -0x81c 0xc53a0003 // Pin=-52dBm -0x81c 0xc43c0003 // Pin=-50dBm -0x81c 0xc33e0003 // Pin=-48dBm -0x81c 0xc2400003 // Pin=-46dBm -0x81c 0xc1420003 // Pin=-44dBm -0x81c 0xa8440003 // Pin=-42dBm -0x81c 0xa7460003 // Pin=-40dBm -0x81c 0xa6480003 // Pin=-38dBm -0x81c 0xa54a0003 // Pin=-36dBm -0x81c 0xa44c0003 // Pin=-34dBm -0x81c 0xa34e0003 // Pin=-32dBm -0x81c 0xa2500003 // Pin=-30dBm -0x81c 0x65520003 // Pin=-28dBm -0x81c 0x64540003 // Pin=-26dBm -0x81c 0x63560003 // Pin=-24dBm -0x81c 0x62580003 // Pin=-22dBm -0x81c 0x615a0003 // Pin=-20dBm -0x81c 0x465c0003 // Pin=-18dBm -0x81c 0x455e0003 // Pin=-16dBm -0x81c 0x44600003 // Pin=-14dBm -0x81c 0x43620003 // Pin=-12dBm -0x81c 0x42640003 // Pin=-10dBm -0x81c 0x41660003 // Pin=-08dBm -0x81c 0x41680003 // Pin=-06dBm -0x81c 0x416a0003 // Pin=-04dBm -0x81c 0x416c0003 // Pin=-02dBm -0x81c 0x416e0003 // Pin=-00dBm -0x81c 0x41700003 // Pin=+02dBm -0x81c 0x41720003 // Pin=+04dBm -0x81c 0x41740003 // Pin=+06dBm -0x81c 0x41760003 // Pin=+08dBm -0x81c 0x41780003 // Pin=+10dBm -0x81c 0x417a0003 // Pin=+12dBm -0x81c 0x417c0003 // Pin=+14dBm -0x81c 0x417e0003 // Pin=+16dBm -// AGC_TABLE 1 (5G LB) -0x81c 0xf6000103 // Pin=-110dBm -0x81c 0xf5020103 // Pin=-108dBm -0x81c 0xf4040103 // Pin=-106dBm -0x81c 0xf3060103 // Pin=-104dBm -0x81c 0xf2080103 // Pin=-102dBm -0x81c 0xf10a0103 // Pin=-100dBm -0x81c 0xf00c0103 // Pin=-98dBm -0x81c 0xef0e0103 // Pin=-96dBm -0x81c 0xee100103 // Pin=-94dBm -0x81c 0xed120103 // Pin=-92dBm -0x81c 0xec140103 // Pin=-90dBm -0x81c 0xeb160103 // Pin=-88dBm -0x81c 0xea180103 // Pin=-86dBm -0x81c 0xe91a0103 // Pin=-84dBm -0x81c 0xe81c0103 // Pin=-82dBm -0x81c 0xe71e0103 // Pin=-80dBm -0x81c 0xe6200103 // Pin=-78dBm -0x81c 0xe5220103 // Pin=-76dBm -0x81c 0xe4240103 // Pin=-74dBm -0x81c 0xe3260103 // Pin=-72dBm -0x81c 0xe2280103 // Pin=-70dBm -0x81c 0xc32a0103 // Pin=-68dBm -0x81c 0xc22c0103 // Pin=-66dBm -0x81c 0xc12e0103 // Pin=-64dBm -0x81c 0xa6300103 // Pin=-62dBm -0x81c 0xa5320103 // Pin=-60dBm -0x81c 0xa4340103 // Pin=-58dBm -0x81c 0xa3360103 // Pin=-56dBm -0x81c 0xa2380103 // Pin=-54dBm -0x81c 0xa13a0103 // Pin=-52dBm -0x81c 0x843c0103 // Pin=-50dBm -0x81c 0x833e0103 // Pin=-48dBm -0x81c 0x82400103 // Pin=-46dBm -0x81c 0x81420103 // Pin=-44dBm -0x81c 0x64440103 // Pin=-42dBm -0x81c 0x63460103 // Pin=-40dBm -0x81c 0x62480103 // Pin=-38dBm -0x81c 0x614a0103 // Pin=-36dBm -0x81c 0x444c0103 // Pin=-34dBm -0x81c 0x434e0103 // Pin=-32dBm -0x81c 0x42500103 // Pin=-30dBm -0x81c 0x41520103 // Pin=-28dBm -0x81c 0x25540103 // Pin=-26dBm -0x81c 0x24560103 // Pin=-24dBm -0x81c 0x23580103 // Pin=-22dBm -0x81c 0x225a0103 // Pin=-20dBm -0x81c 0x055c0103 // Pin=-18dBm -0x81c 0x045e0103 // Pin=-16dBm -0x81c 0x03600103 // Pin=-14dBm -0x81c 0x02620103 // Pin=-12dBm -0x81c 0x01640103 // Pin=-10dBm -0x81c 0x01660103 // Pin=-08dBm -0x81c 0x01680103 // Pin=-06dBm -0x81c 0x016a0103 // Pin=-04dBm -0x81c 0x016c0103 // Pin=-02dBm -0x81c 0x016e0103 // Pin=-00dBm -0x81c 0x01700103 // Pin=+02dBm -0x81c 0x01720103 // Pin=+04dBm -0x81c 0x01740103 // Pin=+06dBm -0x81c 0x01760103 // Pin=+08dBm -0x81c 0x01780103 // Pin=+10dBm -0x81c 0x017a0103 // Pin=+12dBm -0x81c 0x017c0103 // Pin=+14dBm -0x81c 0x017e0103 // Pin=+16dBm -// AGC_TABLE 2 (5G MB) -0x81c 0xf6000203 // Pin=-110dBm -0x81c 0xf5020203 // Pin=-108dBm -0x81c 0xf4040203 // Pin=-106dBm -0x81c 0xf3060203 // Pin=-104dBm -0x81c 0xf2080203 // Pin=-102dBm -0x81c 0xf10a0203 // Pin=-100dBm -0x81c 0xf00c0203 // Pin=-98dBm -0x81c 0xef0e0203 // Pin=-96dBm -0x81c 0xee100203 // Pin=-94dBm -0x81c 0xed120203 // Pin=-92dBm -0x81c 0xec140203 // Pin=-90dBm -0x81c 0xeb160203 // Pin=-88dBm -0x81c 0xea180203 // Pin=-86dBm -0x81c 0xe91a0203 // Pin=-84dBm -0x81c 0xe81c0203 // Pin=-82dBm -0x81c 0xe71e0203 // Pin=-80dBm -0x81c 0xe6200203 // Pin=-78dBm -0x81c 0xe5220203 // Pin=-76dBm -0x81c 0xe4240203 // Pin=-74dBm -0x81c 0xe3260203 // Pin=-72dBm -0x81c 0xe2280203 // Pin=-70dBm -0x81c 0xc32a0203 // Pin=-68dBm -0x81c 0xc22c0203 // Pin=-66dBm -0x81c 0xc12e0203 // Pin=-64dBm -0x81c 0xa6300203 // Pin=-62dBm -0x81c 0xa5320203 // Pin=-60dBm -0x81c 0xa4340203 // Pin=-58dBm -0x81c 0xa3360203 // Pin=-56dBm -0x81c 0xa2380203 // Pin=-54dBm -0x81c 0xa13a0203 // Pin=-52dBm -0x81c 0x843c0203 // Pin=-50dBm -0x81c 0x833e0203 // Pin=-48dBm -0x81c 0x82400203 // Pin=-46dBm -0x81c 0x81420203 // Pin=-44dBm -0x81c 0x64440203 // Pin=-42dBm -0x81c 0x63460203 // Pin=-40dBm -0x81c 0x62480203 // Pin=-38dBm -0x81c 0x454a0203 // Pin=-36dBm -0x81c 0x444c0203 // Pin=-34dBm -0x81c 0x434e0203 // Pin=-32dBm -0x81c 0x42500203 // Pin=-30dBm -0x81c 0x41520203 // Pin=-28dBm -0x81c 0x24540203 // Pin=-26dBm -0x81c 0x23560203 // Pin=-24dBm -0x81c 0x22580203 // Pin=-22dBm -0x81c 0x065a0203 // Pin=-20dBm -0x81c 0x055c0203 // Pin=-18dBm -0x81c 0x045e0203 // Pin=-16dBm -0x81c 0x03600203 // Pin=-14dBm -0x81c 0x02620203 // Pin=-12dBm -0x81c 0x01640203 // Pin=-10dBm -0x81c 0x01660203 // Pin=-08dBm -0x81c 0x01680203 // Pin=-06dBm -0x81c 0x016a0203 // Pin=-04dBm -0x81c 0x016c0203 // Pin=-02dBm -0x81c 0x016e0203 // Pin=-00dBm -0x81c 0x01700203 // Pin=+02dBm -0x81c 0x01720203 // Pin=+04dBm -0x81c 0x01740203 // Pin=+06dBm -0x81c 0x01760203 // Pin=+08dBm -0x81c 0x01780203 // Pin=+10dBm -0x81c 0x017a0203 // Pin=+12dBm -0x81c 0x017c0203 // Pin=+14dBm -0x81c 0x017e0203 // Pin=+16dBm -// AGC_TABLE 2 (5G HB) -0x81c 0xf5000303 // Pin=-110dBm -0x81c 0xf4020303 // Pin=-108dBm -0x81c 0xf3040303 // Pin=-106dBm -0x81c 0xf2060303 // Pin=-104dBm -0x81c 0xf1080303 // Pin=-102dBm -0x81c 0xf00a0303 // Pin=-100dBm -0x81c 0xef0c0303 // Pin=-98dBm -0x81c 0xee0e0303 // Pin=-96dBm -0x81c 0xed100303 // Pin=-94dBm -0x81c 0xec120303 // Pin=-92dBm -0x81c 0xeb140303 // Pin=-90dBm -0x81c 0xea160303 // Pin=-88dBm -0x81c 0xe9180303 // Pin=-86dBm -0x81c 0xe81a0303 // Pin=-84dBm -0x81c 0xe71c0303 // Pin=-82dBm -0x81c 0xe61e0303 // Pin=-80dBm -0x81c 0xe5200303 // Pin=-78dBm -0x81c 0xe4220303 // Pin=-76dBm -0x81c 0xe3240303 // Pin=-74dBm -0x81c 0xe2260303 // Pin=-72dBm -0x81c 0xe1280303 // Pin=-70dBm -0x81c 0xc32a0303 // Pin=-68dBm -0x81c 0xc22c0303 // Pin=-66dBm -0x81c 0xc12e0303 // Pin=-64dBm -0x81c 0xa5300303 // Pin=-62dBm -0x81c 0xa4320303 // Pin=-60dBm -0x81c 0xa3340303 // Pin=-58dBm -0x81c 0xa2360303 // Pin=-56dBm -0x81c 0xa1380303 // Pin=-54dBm -0x81c 0x843a0303 // Pin=-52dBm -0x81c 0x833c0303 // Pin=-50dBm -0x81c 0x823e0303 // Pin=-48dBm -0x81c 0x81400303 // Pin=-46dBm -0x81c 0x64420303 // Pin=-44dBm -0x81c 0x63440303 // Pin=-42dBm -0x81c 0x62460303 // Pin=-40dBm -0x81c 0x61480303 // Pin=-38dBm -0x81c 0x454a0303 // Pin=-36dBm -0x81c 0x444c0303 // Pin=-34dBm -0x81c 0x434e0303 // Pin=-32dBm -0x81c 0x42500303 // Pin=-30dBm -0x81c 0x41520303 // Pin=-28dBm -0x81c 0x24540303 // Pin=-26dBm -0x81c 0x23560303 // Pin=-24dBm -0x81c 0x22580303 // Pin=-22dBm -0x81c 0x215a0303 // Pin=-20dBm -0x81c 0x055c0303 // Pin=-18dBm -0x81c 0x045e0303 // Pin=-16dBm -0x81c 0x03600303 // Pin=-14dBm -0x81c 0x02620303 // Pin=-12dBm -0x81c 0x01640303 // Pin=-10dBm -0x81c 0x01660303 // Pin=-08dBm -0x81c 0x01680303 // Pin=-06dBm -0x81c 0x016a0303 // Pin=-04dBm -0x81c 0x016c0303 // Pin=-02dBm -0x81c 0x016e0303 // Pin=-00dBm -0x81c 0x01700303 // Pin=+02dBm -0x81c 0x01720303 // Pin=+04dBm -0x81c 0x01740303 // Pin=+06dBm -0x81c 0x01760303 // Pin=+08dBm -0x81c 0x01780303 // Pin=+10dBm -0x81c 0x017a0303 // Pin=+12dBm -0x81c 0x017c0303 // Pin=+14dBm -0x81c 0x017e0303 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x81c 0xfe000003 // turn on the table for write data +0x81c 0xff000003 // Pin=-110dBm +0x81c 0xfe020003 // Pin=-108dBm +0x81c 0xfd040003 // Pin=-106dBm +0x81c 0xfc060003 // Pin=-104dBm +0x81c 0xfb080003 // Pin=-102dBm +0x81c 0xfa0a0003 // Pin=-100dBm +0x81c 0xf90c0003 // Pin=-98dBm +0x81c 0xf80e0003 // Pin=-96dBm +0x81c 0xf7100003 // Pin=-94dBm +0x81c 0xf6120003 // Pin=-92dBm +0x81c 0xf5140003 // Pin=-90dBm +0x81c 0xf4160003 // Pin=-88dBm +0x81c 0xf3180003 // Pin=-86dBm +0x81c 0xf21a0003 // Pin=-84dBm +0x81c 0xf11c0003 // Pin=-82dBm +0x81c 0xf01e0003 // Pin=-80dBm +0x81c 0xef200003 // Pin=-78dBm +0x81c 0xee220003 // Pin=-76dBm +0x81c 0xed240003 // Pin=-74dBm +0x81c 0xec260003 // Pin=-72dBm +0x81c 0xeb280003 // Pin=-70dBm +0x81c 0xea2a0003 // Pin=-68dBm +0x81c 0xe92c0003 // Pin=-66dBm +0x81c 0xe82e0003 // Pin=-64dBm +0x81c 0xe7300003 // Pin=-62dBm +0x81c 0xe6320003 // Pin=-60dBm +0x81c 0xe5340003 // Pin=-58dBm +0x81c 0xe4360003 // Pin=-56dBm +0x81c 0xe3380003 // Pin=-54dBm +0x81c 0xc53a0003 // Pin=-52dBm +0x81c 0xc43c0003 // Pin=-50dBm +0x81c 0xc33e0003 // Pin=-48dBm +0x81c 0xc2400003 // Pin=-46dBm +0x81c 0xc1420003 // Pin=-44dBm +0x81c 0xa8440003 // Pin=-42dBm +0x81c 0xa7460003 // Pin=-40dBm +0x81c 0xa6480003 // Pin=-38dBm +0x81c 0xa54a0003 // Pin=-36dBm +0x81c 0xa44c0003 // Pin=-34dBm +0x81c 0xa34e0003 // Pin=-32dBm +0x81c 0xa2500003 // Pin=-30dBm +0x81c 0x65520003 // Pin=-28dBm +0x81c 0x64540003 // Pin=-26dBm +0x81c 0x63560003 // Pin=-24dBm +0x81c 0x62580003 // Pin=-22dBm +0x81c 0x615a0003 // Pin=-20dBm +0x81c 0x465c0003 // Pin=-18dBm +0x81c 0x455e0003 // Pin=-16dBm +0x81c 0x44600003 // Pin=-14dBm +0x81c 0x43620003 // Pin=-12dBm +0x81c 0x42640003 // Pin=-10dBm +0x81c 0x41660003 // Pin=-08dBm +0x81c 0x41680003 // Pin=-06dBm +0x81c 0x416a0003 // Pin=-04dBm +0x81c 0x416c0003 // Pin=-02dBm +0x81c 0x416e0003 // Pin=-00dBm +0x81c 0x41700003 // Pin=+02dBm +0x81c 0x41720003 // Pin=+04dBm +0x81c 0x41740003 // Pin=+06dBm +0x81c 0x41760003 // Pin=+08dBm +0x81c 0x41780003 // Pin=+10dBm +0x81c 0x417a0003 // Pin=+12dBm +0x81c 0x417c0003 // Pin=+14dBm +0x81c 0x417e0003 // Pin=+16dBm +// AGC_TABLE 1 (5G LB) +0x81c 0xf6000103 // Pin=-110dBm +0x81c 0xf5020103 // Pin=-108dBm +0x81c 0xf4040103 // Pin=-106dBm +0x81c 0xf3060103 // Pin=-104dBm +0x81c 0xf2080103 // Pin=-102dBm +0x81c 0xf10a0103 // Pin=-100dBm +0x81c 0xf00c0103 // Pin=-98dBm +0x81c 0xef0e0103 // Pin=-96dBm +0x81c 0xee100103 // Pin=-94dBm +0x81c 0xed120103 // Pin=-92dBm +0x81c 0xec140103 // Pin=-90dBm +0x81c 0xeb160103 // Pin=-88dBm +0x81c 0xea180103 // Pin=-86dBm +0x81c 0xe91a0103 // Pin=-84dBm +0x81c 0xe81c0103 // Pin=-82dBm +0x81c 0xe71e0103 // Pin=-80dBm +0x81c 0xe6200103 // Pin=-78dBm +0x81c 0xe5220103 // Pin=-76dBm +0x81c 0xe4240103 // Pin=-74dBm +0x81c 0xe3260103 // Pin=-72dBm +0x81c 0xe2280103 // Pin=-70dBm +0x81c 0xc32a0103 // Pin=-68dBm +0x81c 0xc22c0103 // Pin=-66dBm +0x81c 0xc12e0103 // Pin=-64dBm +0x81c 0xa6300103 // Pin=-62dBm +0x81c 0xa5320103 // Pin=-60dBm +0x81c 0xa4340103 // Pin=-58dBm +0x81c 0xa3360103 // Pin=-56dBm +0x81c 0xa2380103 // Pin=-54dBm +0x81c 0xa13a0103 // Pin=-52dBm +0x81c 0x843c0103 // Pin=-50dBm +0x81c 0x833e0103 // Pin=-48dBm +0x81c 0x82400103 // Pin=-46dBm +0x81c 0x81420103 // Pin=-44dBm +0x81c 0x64440103 // Pin=-42dBm +0x81c 0x63460103 // Pin=-40dBm +0x81c 0x62480103 // Pin=-38dBm +0x81c 0x614a0103 // Pin=-36dBm +0x81c 0x444c0103 // Pin=-34dBm +0x81c 0x434e0103 // Pin=-32dBm +0x81c 0x42500103 // Pin=-30dBm +0x81c 0x41520103 // Pin=-28dBm +0x81c 0x25540103 // Pin=-26dBm +0x81c 0x24560103 // Pin=-24dBm +0x81c 0x23580103 // Pin=-22dBm +0x81c 0x225a0103 // Pin=-20dBm +0x81c 0x055c0103 // Pin=-18dBm +0x81c 0x045e0103 // Pin=-16dBm +0x81c 0x03600103 // Pin=-14dBm +0x81c 0x02620103 // Pin=-12dBm +0x81c 0x01640103 // Pin=-10dBm +0x81c 0x01660103 // Pin=-08dBm +0x81c 0x01680103 // Pin=-06dBm +0x81c 0x016a0103 // Pin=-04dBm +0x81c 0x016c0103 // Pin=-02dBm +0x81c 0x016e0103 // Pin=-00dBm +0x81c 0x01700103 // Pin=+02dBm +0x81c 0x01720103 // Pin=+04dBm +0x81c 0x01740103 // Pin=+06dBm +0x81c 0x01760103 // Pin=+08dBm +0x81c 0x01780103 // Pin=+10dBm +0x81c 0x017a0103 // Pin=+12dBm +0x81c 0x017c0103 // Pin=+14dBm +0x81c 0x017e0103 // Pin=+16dBm +// AGC_TABLE 2 (5G MB) +0x81c 0xf6000203 // Pin=-110dBm +0x81c 0xf5020203 // Pin=-108dBm +0x81c 0xf4040203 // Pin=-106dBm +0x81c 0xf3060203 // Pin=-104dBm +0x81c 0xf2080203 // Pin=-102dBm +0x81c 0xf10a0203 // Pin=-100dBm +0x81c 0xf00c0203 // Pin=-98dBm +0x81c 0xef0e0203 // Pin=-96dBm +0x81c 0xee100203 // Pin=-94dBm +0x81c 0xed120203 // Pin=-92dBm +0x81c 0xec140203 // Pin=-90dBm +0x81c 0xeb160203 // Pin=-88dBm +0x81c 0xea180203 // Pin=-86dBm +0x81c 0xe91a0203 // Pin=-84dBm +0x81c 0xe81c0203 // Pin=-82dBm +0x81c 0xe71e0203 // Pin=-80dBm +0x81c 0xe6200203 // Pin=-78dBm +0x81c 0xe5220203 // Pin=-76dBm +0x81c 0xe4240203 // Pin=-74dBm +0x81c 0xe3260203 // Pin=-72dBm +0x81c 0xe2280203 // Pin=-70dBm +0x81c 0xc32a0203 // Pin=-68dBm +0x81c 0xc22c0203 // Pin=-66dBm +0x81c 0xc12e0203 // Pin=-64dBm +0x81c 0xa6300203 // Pin=-62dBm +0x81c 0xa5320203 // Pin=-60dBm +0x81c 0xa4340203 // Pin=-58dBm +0x81c 0xa3360203 // Pin=-56dBm +0x81c 0xa2380203 // Pin=-54dBm +0x81c 0xa13a0203 // Pin=-52dBm +0x81c 0x843c0203 // Pin=-50dBm +0x81c 0x833e0203 // Pin=-48dBm +0x81c 0x82400203 // Pin=-46dBm +0x81c 0x81420203 // Pin=-44dBm +0x81c 0x64440203 // Pin=-42dBm +0x81c 0x63460203 // Pin=-40dBm +0x81c 0x62480203 // Pin=-38dBm +0x81c 0x454a0203 // Pin=-36dBm +0x81c 0x444c0203 // Pin=-34dBm +0x81c 0x434e0203 // Pin=-32dBm +0x81c 0x42500203 // Pin=-30dBm +0x81c 0x41520203 // Pin=-28dBm +0x81c 0x24540203 // Pin=-26dBm +0x81c 0x23560203 // Pin=-24dBm +0x81c 0x22580203 // Pin=-22dBm +0x81c 0x065a0203 // Pin=-20dBm +0x81c 0x055c0203 // Pin=-18dBm +0x81c 0x045e0203 // Pin=-16dBm +0x81c 0x03600203 // Pin=-14dBm +0x81c 0x02620203 // Pin=-12dBm +0x81c 0x01640203 // Pin=-10dBm +0x81c 0x01660203 // Pin=-08dBm +0x81c 0x01680203 // Pin=-06dBm +0x81c 0x016a0203 // Pin=-04dBm +0x81c 0x016c0203 // Pin=-02dBm +0x81c 0x016e0203 // Pin=-00dBm +0x81c 0x01700203 // Pin=+02dBm +0x81c 0x01720203 // Pin=+04dBm +0x81c 0x01740203 // Pin=+06dBm +0x81c 0x01760203 // Pin=+08dBm +0x81c 0x01780203 // Pin=+10dBm +0x81c 0x017a0203 // Pin=+12dBm +0x81c 0x017c0203 // Pin=+14dBm +0x81c 0x017e0203 // Pin=+16dBm +// AGC_TABLE 2 (5G HB) +0x81c 0xf5000303 // Pin=-110dBm +0x81c 0xf4020303 // Pin=-108dBm +0x81c 0xf3040303 // Pin=-106dBm +0x81c 0xf2060303 // Pin=-104dBm +0x81c 0xf1080303 // Pin=-102dBm +0x81c 0xf00a0303 // Pin=-100dBm +0x81c 0xef0c0303 // Pin=-98dBm +0x81c 0xee0e0303 // Pin=-96dBm +0x81c 0xed100303 // Pin=-94dBm +0x81c 0xec120303 // Pin=-92dBm +0x81c 0xeb140303 // Pin=-90dBm +0x81c 0xea160303 // Pin=-88dBm +0x81c 0xe9180303 // Pin=-86dBm +0x81c 0xe81a0303 // Pin=-84dBm +0x81c 0xe71c0303 // Pin=-82dBm +0x81c 0xe61e0303 // Pin=-80dBm +0x81c 0xe5200303 // Pin=-78dBm +0x81c 0xe4220303 // Pin=-76dBm +0x81c 0xe3240303 // Pin=-74dBm +0x81c 0xe2260303 // Pin=-72dBm +0x81c 0xe1280303 // Pin=-70dBm +0x81c 0xc32a0303 // Pin=-68dBm +0x81c 0xc22c0303 // Pin=-66dBm +0x81c 0xc12e0303 // Pin=-64dBm +0x81c 0xa5300303 // Pin=-62dBm +0x81c 0xa4320303 // Pin=-60dBm +0x81c 0xa3340303 // Pin=-58dBm +0x81c 0xa2360303 // Pin=-56dBm +0x81c 0xa1380303 // Pin=-54dBm +0x81c 0x843a0303 // Pin=-52dBm +0x81c 0x833c0303 // Pin=-50dBm +0x81c 0x823e0303 // Pin=-48dBm +0x81c 0x81400303 // Pin=-46dBm +0x81c 0x64420303 // Pin=-44dBm +0x81c 0x63440303 // Pin=-42dBm +0x81c 0x62460303 // Pin=-40dBm +0x81c 0x61480303 // Pin=-38dBm +0x81c 0x454a0303 // Pin=-36dBm +0x81c 0x444c0303 // Pin=-34dBm +0x81c 0x434e0303 // Pin=-32dBm +0x81c 0x42500303 // Pin=-30dBm +0x81c 0x41520303 // Pin=-28dBm +0x81c 0x24540303 // Pin=-26dBm +0x81c 0x23560303 // Pin=-24dBm +0x81c 0x22580303 // Pin=-22dBm +0x81c 0x215a0303 // Pin=-20dBm +0x81c 0x055c0303 // Pin=-18dBm +0x81c 0x045e0303 // Pin=-16dBm +0x81c 0x03600303 // Pin=-14dBm +0x81c 0x02620303 // Pin=-12dBm +0x81c 0x01640303 // Pin=-10dBm +0x81c 0x01660303 // Pin=-08dBm +0x81c 0x01680303 // Pin=-06dBm +0x81c 0x016a0303 // Pin=-04dBm +0x81c 0x016c0303 // Pin=-02dBm +0x81c 0x016e0303 // Pin=-00dBm +0x81c 0x01700303 // Pin=+02dBm +0x81c 0x01720303 // Pin=+04dBm +0x81c 0x01740303 // Pin=+06dBm +0x81c 0x01760303 // Pin=+08dBm +0x81c 0x01780303 // Pin=+10dBm +0x81c 0x017a0303 // Pin=+12dBm +0x81c 0x017c0303 // Pin=+14dBm +0x81c 0x017e0303 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_high_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_high_8197F.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_high_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_high_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_low_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_low_8197F.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_low_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_low_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_normal_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_normal_8197F.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_normal_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_def_normal_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_high_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_high_8197F.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_high_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_high_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_low_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_low_8197F.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_low_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_low_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_normal_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_normal_8197F.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_normal_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_gen_normal_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_state_criteria_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_state_criteria_8197F.txt old mode 100755 new mode 100644 index 18d91fac5d0..d44bcb85c66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_state_criteria_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_state_criteria_8197F.txt @@ -1,35 +1,35 @@ -////Release version: 8881A.0820.2013 -// State: -// 1.) MACDM_TP_STATE_DEFAULT -// 2.) MACDM_TP_STATE_GENERAL -// 3.) MACDM_TP_STATE_TXOP -// So, we need four criteria -// 1.) MACDM_TP_THRS_DEF_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 2.) MACDM_TP_THRS_GEN_TO_DEF -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 3.) MACDM_TP_THRS_GEN_TO_TXOP -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 4.) MACDM_TP_THRS_TXOP_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -0x28 -0x28 -0x28 -0x1E -0x1E -0x1E -0x8C -0x8C -0x8C -0x82 -0x82 -0x82 +////Release version: 8881A.0820.2013 +// State: +// 1.) MACDM_TP_STATE_DEFAULT +// 2.) MACDM_TP_STATE_GENERAL +// 3.) MACDM_TP_STATE_TXOP +// So, we need four criteria +// 1.) MACDM_TP_THRS_DEF_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 2.) MACDM_TP_THRS_GEN_TO_DEF +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 3.) MACDM_TP_THRS_GEN_TO_TXOP +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 4.) MACDM_TP_THRS_TXOP_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +0x28 +0x28 +0x28 +0x1E +0x1E +0x1E +0x8C +0x8C +0x8C +0x82 +0x82 +0x82 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_high_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_high_8197F.txt old mode 100755 new mode 100644 index e01e46b9e5f..71936a7a338 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_high_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_high_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x0308AAAA +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x0308AAAA 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_low_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_low_8197F.txt old mode 100755 new mode 100644 index 760de6ccf1b..fd35b529ed0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_low_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_low_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03088888 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03088888 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_normal_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_normal_8197F.txt old mode 100755 new mode 100644 index 30889a39f89..0555ed20521 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_normal_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MACDM_txop_normal_8197F.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03089999 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03089999 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197F.txt old mode 100755 new mode 100644 index 5264a50ae19..442f36b41ea --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197F.txt @@ -1,155 +1,155 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x20 0xbd -0x21 0x1d -//0x24 0x59 -0x04 0x12 -//0x05 0x01 -//0x06 0x03 -0x07 0x14 -//0xa0 0x00 -//0xa1 0x00 -//0xa2 0x00 -//0xa3 0x04 -0x00 0x92 -0x01 0xb2 -//0x02 0xff -//0x03 0xff -//0x1c 0x00 -//0x1d 0x01 -//0x1e 0xf4 -//0x1f 0x07 -0x73 0x00 -0x78 0xfb -0x79 0x02 -0x7a 0x30 -0x7b 0x07 -0x420 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00//Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04//RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10//auto rate fall back 0 1ss 2ss 3ss -0x445 0xF0 -0x446 0x0E -0x447 0x1F -0x448 0x7C -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x0E -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x30 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x03 -0x49F 0xFE -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x01 -0x4A7 0x0E -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c7 0x80 //enable single packet ampdu -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x10 // Change max tx agg num to 16 -0x4cb 0x10 // Change max tx agg num to 16 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x64 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x22 -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x64 // -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x20 0xbd +0x21 0x1d +//0x24 0x59 +0x04 0x12 +//0x05 0x01 +//0x06 0x03 +0x07 0x14 +//0xa0 0x00 +//0xa1 0x00 +//0xa2 0x00 +//0xa3 0x04 +0x00 0x92 +0x01 0xb2 +//0x02 0xff +//0x03 0xff +//0x1c 0x00 +//0x1d 0x01 +//0x1e 0xf4 +//0x1f 0x07 +0x73 0x00 +0x78 0xfb +0x79 0x02 +0x7a 0x30 +0x7b 0x07 +0x420 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00//Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04//RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10//auto rate fall back 0 1ss 2ss 3ss +0x445 0xF0 +0x446 0x0E +0x447 0x1F +0x448 0x7C +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x0E +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x30 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x03 +0x49F 0xFE +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x01 +0x4A7 0x0E +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c7 0x80 //enable single packet ampdu +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x10 // Change max tx agg num to 16 +0x4cb 0x10 // Change max tx agg num to 16 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x64 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x22 +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x64 // +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197Fmp.txt old mode 100755 new mode 100644 index 724af22d54e..a7769b3af80 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/MAC_REG_8197Fmp.txt @@ -1,135 +1,135 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x010 0x7c // AFE power cut -0x014 0xdb // sawtooth capacitor & current -0x016 0x02 -0x073 0x10 // AFE iso -0x420 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00 //Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 //RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss -0x445 0xF0 -0x446 0x0E -0x447 0x1F -0x448 0x7C -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x0E -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x30 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x03 -0x49F 0xFE -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x01 -0x4A7 0x0E -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c7 0x80 //enable single packet ampdu -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x3C // Change max tx agg num to 60 //max tx agg num =62 -0x4cb 0x3C // Change max tx agg num to 60 //max tx agg num =62 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x64 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x2a -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x64 // -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x010 0x7c // AFE power cut +0x014 0xdb // sawtooth capacitor & current +0x016 0x02 +0x073 0x10 // AFE iso +0x420 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00 //Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 //RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss +0x445 0xF0 +0x446 0x0E +0x447 0x1F +0x448 0x7C +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x0E +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x30 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x03 +0x49F 0xFE +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x01 +0x4A7 0x0E +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c7 0x80 //enable single packet ampdu +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x3C // Change max tx agg num to 60 //max tx agg num =62 +0x4cb 0x3C // Change max tx agg num to 60 //max tx agg num =62 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x64 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x2a +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x64 // +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F.txt old mode 100755 new mode 100644 index f6bfb25721b..89e60288e80 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F.txt @@ -1,493 +1,493 @@ -//rtl8197f version = 1 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x00005308 // default OFDM and CCK is disable for initial flow // when 0x800[11]=0 20/40M RXADC clk is control by 0xbb0[18:16] and 0xbb0[22:20] -0x804 0x00004001 -0x808 0x0000fc00 -0x80c 0x00000000 -0x810 0x20200022 -0x814 0x020c3d10 -0x818 0x000003c5 -0x81c 0x07000000 -0x820 0x01000100 -0x824 0x003B4204 // RXHP MSB is 1 since RF CCK_IND is inverted -0x828 0x01000100 -0x82c 0x003B4204 // RXHP MSB is 1 since RF CCK_IND is inverted -0x830 0x00000084 -0x834 0x00690200 -0x838 0x00000004 -0x83c 0x00690200 -0x840 0x00010000 -0x844 0x00010000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00031FE0 // RF wakeup (RX idle in IGI) -0x854 0x00000000 -0x858 0x569a569a -0x85c 0x00400040 // ANAPAR control CCA_LP (trx on) -0x860 0x66f60000 -0x864 0x061f0000 -0x868 0x0f7f0130 -0x86c 0x0f7f0130 -0x870 0x00000300 -0x874 0x04003400 -0x878 0x08080808 -0x87c 0x004f0201 -0x880 0xd8001402 // anapar_bb_anta[31:0] -0x884 0xc0000120 // anapar_bb_anta[63:32] -0x888 0x00000000 -0x88c 0xcc0000c0 -0x890 0x00000000 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -0x8a0 0x00000000 -0x8a4 0x00000000 -0x8a8 0x00000109 -0x8ac 0x00000000 -0x8b0 0x00000000 -0x8b4 0x00000000 -0x8b8 0x00000000 -0x8bc 0x00000000 -0x8c0 0x03910c40 -0x8c4 0x00000000 -0x8c8 0x00000000 -0x8cc 0x00000000 -0x8d0 0x00000000 -0x8d4 0x00000000 -0x8d8 0x00000000 -0x8dc 0x00000000 -0x8e0 0x02000200 -0x8e4 0x00000000 -0x8e8 0xd8080000 -0x8ec 0x00000000 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000f00 -0x90c 0x81121313 -0x910 0x024c0000 -0x914 0x00000000 -0x918 0x00000000 -0x91c 0x00000000 -0x920 0x00000000 -0x924 0x00000000 -0x928 0x00000000 -0x92c 0x00010040 -0x930 0x88000000 -0x934 0x00000245 -0x938 0x00024588 -0x93c 0x00000000 -0x940 0x000007ff -0x944 0x7F7F0000 -0x948 0x000001A3 -0x94c 0x20200008 -0x950 0x00338697 -0x954 0x00000000 -0x958 0x4bc7b87a -0x95c 0x06eb9b79 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000100 -0x96c 0x00000003 -0x970 0x00000000 -0x974 0x00000000 -0x978 0x00000000 -0x97c 0x10030000 -0x980 0x00000000 -0x984 0x00050050 -0x988 0x000a560e -0x98c 0x1461c826 -0x990 0x0001469e -0x994 0x008858d1 -0x998 0x700086c9 -0x99c 0x77777777 -0x9a0 0x00000000 -0x9a4 0x00000000 -0x9a8 0x00000000 -0x9ac 0x00020000 -0x9b0 0x00000000 -0x9b4 0x00000000 -0x9b8 0x00000000 -0x9bc 0x00000000 -0x9c0 0x00000011 -0x9c4 0x00000000 -0x9c8 0x00000000 -0x9cc 0x00000000 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e0 0x00000000 -0x9e4 0x00000000 -0x9e8 0x00000000 -0x9ec 0x00000000 -0x9f0 0x80000000 -0x9f4 0x00000000 -0x9f8 0x00000000 -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff800c -0xa08 0x8c838300 -0xa0c 0x2e20200f -0xa10 0x9500bb78 -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0xe82c0001 -0xa24 0x64b80c1c -0xa28 0x00008810 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000107 -0xa78 0x00008900 -0xa7c 0x225b0606 -0xa80 0x2180Fa74 //88E: CCK LNA 2 to 3 bit mapping:0xa80[23]=1b1 0xa80[7]=1b1 CCK agc_rpt as new format -//0xa80 0x21003210 -0xa84 0x00200000 -0xa88 0x040c0000 -0xa8c 0x12345678 -0xa90 0xabcdef00 -0xa94 0x801b1b89 // a97[7]=1 for CCK tx wrong length -0xa98 0x00000000 -0xa9c 0x00020000 -0xaa0 0x00000000 -0xaa8 0xeaaf0000 // r_MF_FA_drop_en=1 r_CS_ratio_sel_new=0xf -0xaac 0x01235667 -0xab0 0x00000000 -// -//======================= -// PAGE_B -//======================= -0xb00 0x00000000 -0xb04 0x00000000 -0xb08 0x00000000 -0xb0c 0x00000000 -0xb10 0x00000000 -0xb14 0x00000000 -0xb18 0x00000000 -0xb1c 0x00000000 -0xb20 0x00000000 -0xb24 0x00000000 -0xb28 0x00000000 -0xb2c 0x00000000 -0xb30 0x00000000 -0xb34 0x00000000 -0xb38 0x00000000 -0xb3c 0x00000000 -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x00000000 -0xb4c 0x00000000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -0xb60 0x00000000 -0xb64 0x00000000 -0xb68 0x80000000 -0xb6c 0x80000000 -0xb70 0x00000000 -0xb74 0x00000000 -0xb78 0x00000000 -0xb7c 0x00000000 -0xb80 0x00000000 -0xb84 0x00000000 -0xb88 0x00000000 -0xb8c 0x00000000 -0xb90 0x00000000 -0xb94 0x00000000 -0xb98 0x00000000 -0xb9c 0x00000000 -0xba0 0x00000000 -0xba4 0x00000000 -0xba8 0x00000000 -0xbac 0x00000000 -0xbb0 0x00440000 -0xbb4 0x00000000 -0xbb8 0x00000000 -0xbbc 0x00000000 -0xbd0 0x00000000 -0xbd4 0x00000000 -0xbdc 0x02000000 -0xbe0 0x02000000 -0xbe4 0x02000000 -0xbe8 0x02000000 -0xbec 0x02000000 -0xbf0 0x02000000 -0xbf4 0x02000000 -0xbf8 0x02000000 -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x00000080 -0xc04 0x6f005433 -0xc08 0x000004e4 -0xc0c 0x6c6c6c6c -0xc10 0x20000000 // down sample factor for pathA is 4 -0xc14 0x40000100 -0xc18 0x20000000 // down sample factor for pathB is 4 -0xc1c 0x40000100 -0xc20 0x00000000 -0xc24 0x40000100 -0xc28 0x00000000 -0xc2c 0x40000100 -0xc30 0x0401a803 -0xc34 0x30000040 -0xc38 0x23408080 -0xc3c 0x00002b14 -0xc40 0x1cfc403f -0xc44 0x000100c7 -0xc48 0xec060106 -0xc4c 0x00f203fd -0xc50 0x00340020 -0xc54 0x04008017 -0xc58 0x00000020 -0xc5c 0x0070CDB6 // RXHP MSB is 1 since RF CCK_IND is inverted -0xc60 0x00280200 // default 20M tx filter apply old coeff. -0xc64 0x5012838b -0xc68 0x47c006c7 -0xc6c 0x00000035 -0xc70 0x00000007 -0xc74 0x020251A7 -0xc78 0x0fe07f1f -0xc7c 0x09BC1612 // RXHP MSB is 1 since RF CCK_IND is inverted -0xc80 0x40000100 -0xc84 0x12000000 -0xc88 0x40000100 -0xc8c 0xa0240000 -0xc90 0x40000100 -0xc94 0x00000000 -0xc98 0x40000100 -0xc9c 0x0000bdc8 -0xca0 0x00000000 -0xca4 0x098300a0 -0xca8 0x00000000 -0xcac 0x00057b1a -0xcb0 0x00000000 -0xcb4 0x00000000 -0xcb8 0x00000000 -0xcbc 0x28100200 -0xcc0 0x0010a3d0 -0xcc4 0x00000f7d -0xcc8 0x00000000 -0xccc 0x00000000 -0xcd0 0x00000000 -0xcd4 0x00000000 -0xcd8 0x64b22427 -0xcdc 0x00766932 -0xce0 0x40201006 -0xce4 0x00000000 -0xce8 0x40e04407 -0xcec 0x2e572000 -0xcf0 0x00000000 -0xcf4 0x00000000 -0xcf8 0x00000000 -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x000b0680 -0xd04 0xc0000403 -0xd08 0x00000087 -0xd0c 0x00000201 -0xd10 0x06288888 -0xd14 0x8888366b -0xd18 0x7d806db3 -0xd1c 0x00000000 -0xd20 0x167401b8 -0xd24 0x00000186 -0xd28 0xd513ff7d -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x40608000 -0xd38 0xa8000000 -0xd3c 0x00026ee2 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x20500000 -0xd58 0x16161616 -0xd5c 0x70320064 -0xd60 0x4653dee0 -0xd64 0x7e718a3c -0xd68 0x00000103 -0xd6c 0x00000000 -0xd70 0x00000000 -0xd74 0x00000000 -0xd78 0x00000000 -0xd7c 0x00000000 -0xd80 0x00000000 -0xd84 0x31310000 -0xd88 0x05b57e00 -0xd8c 0x00000000 -0xd90 0x00000000 -0xd94 0x44bbbb44 // ANAPAR pow (TX_CCK_RFON RX_WAIT_CCA Blue-Tooth RX AD3 CCA mode) -0xd98 0x44bb44ff // ANAPAR pow (TX_TO_TX TX_TO_RX TX_OFDM_RFBBON TestMode) -0xd9c 0x08023688 -0xda0 0x00000002 -0xda4 0x00000000 -0xda8 0x00000000 -0xdac 0x00000000 -0xdb0 0x00000000 -0xdb4 0x00000000 -0xdb8 0x00000000 -0xdbc 0x00000000 -0xdc0 0x00000000 -0xdc4 0x00210000 -0xdc8 0x00000200 -0xdcc 0x0000000f -0xdd0 0x00000020 -0xdd4 0x00007f7f -0xdd8 0xe5af1854 -0xddc 0x000040ab -0xde0 0x00000000 -0xde4 0x00000000 -0xde8 0x0002030b -0xdec 0x0000a987 -0xdf0 0x00005807 -0xdf4 0x00000000 -0xdf8 0x00000005 -//======================= -// PAGE_E -//======================= -0xe00 0x00000000 -0xe04 0x00000000 -0xe08 0x00000000 -0xe0c 0x000000ff // ANAPAR pow (CCA_LP) -0xe10 0x00000000 -0xe14 0x00000000 -0xe18 0x00000000 -0xe1c 0x00000000 -0xe20 0x00000000 -0xe24 0x00200000 -0xe28 0x00000000 -0xe2c 0x00000000 -0xe30 0x01007c00 -0xe34 0x01004800 -0xe38 0x10008c0f -0xe3c 0x3c008c0f -0xe40 0x02100000 -0xe44 0x00000000 -0xe48 0x00000000 -0xe4c 0x00000000 -0xe50 0x01007c00 -0xe54 0x01004800 -0xe58 0x10008c0f -0xe5c 0x3c008c0f -0xe60 0x02100000 -0xe64 0xbbbbbbbb // ANAPAR pow (RX_TO_RX RX_WAIT_RIFS RX_OFDM RX_CCK) -0xe68 0x40404040 // ANAPAR control RX AD3 CCA mode (rx off) -0xe6c 0x80408040 // ANAPAR control Blue-Tooth (tx off) -0xe70 0x80408040 // ANAPAR control RX_WAIT_CCA (tx off) -0xe74 0x40404040 // ANAPAR control TX_CCK_RFBBON (rx off) -0xe78 0x00400040 // ANAPAR control TestMode (trx on) -0xe7c 0x40404040 // ANAPAR control TX_OFDM_RFBBON (rx off) -0xe80 0x00ff0000 // ANAPAR pow (PMPD_ANAEN Sleep Standby) -0xe84 0x80408040 // ANAPAR control TX_TO_RX (tx off) -0xe88 0x40404040 // ANAPAR control TX_TO_TX (rx off) -0xe8c 0x80408040 // ANAPAR control RX_CCK (tx off) -0xe90 0x00000000 -0xe94 0x01000000 -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000000 -0xea4 0x01000000 -0xea8 0x00000000 -0xeac 0x00000000 -0xeb0 0x00000000 -0xeb4 0x01000000 -0xeb8 0x00000000 -0xebc 0x00000000 -0xec0 0x00000000 -0xec4 0x01000000 -0xec8 0x00000000 -0xecc 0x00000000 -0xed0 0x80408040 // ANAPAR control RX_OFDM (tx off) -0xed4 0x80408040 // ANAPAR control RX_WAIT_RIFS (tx off) -0xed8 0x80408040 // ANAPAR control RX_TO_RX (tx off) -0xedc 0xC040C040 // ANAPAR control Standby (trx off) -0xee0 0xC040C040 // ANAPAR control Sleep (trx off) -0xee4 0x00400040 // ANAPAR control PMPD_ANAEN (trx on) -0xee8 0xd8001402 // anapar_bb_antb[31:0] -0xeec 0xc0000120 // anapar_bb_anta[63:32] -0xef0 0x02000b09 -0xef4 0x00000001 -0xef8 0x00000000 -//======================= -// PAGE_F -//======================= -0xf00 0x00000300 -0xf04 0x00000000 -0xf08 0x0002030b -0xf0c 0x0000a987 -0xf10 0x00005807 -0xf14 0x00000003 -0xf18 0x00020002 -0xf1c 0x8000001f -0xf20 0x00000000 -0xf24 0x00000000 -0xf28 0x00000000 -0xf2c 0x00000000 -0xf30 0x00000000 -0xf34 0x00000000 -0xf38 0x00030155 -0xf3c 0x0000003a -0xf40 0x00000000 -0xf44 0x00000000 -0xf48 0x00000000 -0xf4c 0x13000000 -0xf50 0x00000010 -0xf54 0x00000000 -0xf58 0x00000000 -0xf5c 0x00000000 -0xf60 0x00000000 -0xf64 0x00000000 -0xf68 0x00000000 -0xf6c 0x00000000 -0xf70 0x00000000 -0xf74 0x00000000 -0xf78 0x00000000 -0xf7c 0x00000000 -0xf80 0x00000000 -0xf84 0x00000000 -0xf88 0x00000000 -0xf8c 0x00000000 -0xf90 0x00000002 -0xf94 0x00000000 -0xf98 0x00000000 -0xf9c 0x00000000 -0xfa0 0x00000000 -0xfa4 0x0002030b -0xfa8 0x0000a987 -0xfac 0x00005807 -0xfb0 0x00000000 -0xfb4 0x00000000 -0xfb8 0x00000000 -0xfbc 0x00000000 -0xfc0 0x00c02001 -0xfc4 0x90063000 -0xfc8 0x00000018 -0xfcc 0x10003005 -0xfd0 0x0000e5af -0xfd4 0x00000000 -0xfd8 0x00000000 -0xfdc 0x00000000 -0xfe0 0x00000000 -0xfe4 0x00000000 -0xfe8 0x00000000 -0xfec 0x00000000 -0xff0 0x00000000 -0xff4 0x00000000 -0xff8 0x00000000 +//rtl8197f version = 1 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x00005308 // default OFDM and CCK is disable for initial flow // when 0x800[11]=0 20/40M RXADC clk is control by 0xbb0[18:16] and 0xbb0[22:20] +0x804 0x00004001 +0x808 0x0000fc00 +0x80c 0x00000000 +0x810 0x20200022 +0x814 0x020c3d10 +0x818 0x000003c5 +0x81c 0x07000000 +0x820 0x01000100 +0x824 0x003B4204 // RXHP MSB is 1 since RF CCK_IND is inverted +0x828 0x01000100 +0x82c 0x003B4204 // RXHP MSB is 1 since RF CCK_IND is inverted +0x830 0x00000084 +0x834 0x00690200 +0x838 0x00000004 +0x83c 0x00690200 +0x840 0x00010000 +0x844 0x00010000 +0x848 0x00000000 +0x84c 0x00000000 +0x850 0x00031FE0 // RF wakeup (RX idle in IGI) +0x854 0x00000000 +0x858 0x569a569a +0x85c 0x00400040 // ANAPAR control CCA_LP (trx on) +0x860 0x66f60000 +0x864 0x061f0000 +0x868 0x0f7f0130 +0x86c 0x0f7f0130 +0x870 0x00000300 +0x874 0x04003400 +0x878 0x08080808 +0x87c 0x004f0201 +0x880 0xd8001402 // anapar_bb_anta[31:0] +0x884 0xc0000120 // anapar_bb_anta[63:32] +0x888 0x00000000 +0x88c 0xcc0000c0 +0x890 0x00000000 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +0x8a0 0x00000000 +0x8a4 0x00000000 +0x8a8 0x00000109 +0x8ac 0x00000000 +0x8b0 0x00000000 +0x8b4 0x00000000 +0x8b8 0x00000000 +0x8bc 0x00000000 +0x8c0 0x03910c40 +0x8c4 0x00000000 +0x8c8 0x00000000 +0x8cc 0x00000000 +0x8d0 0x00000000 +0x8d4 0x00000000 +0x8d8 0x00000000 +0x8dc 0x00000000 +0x8e0 0x02000200 +0x8e4 0x00000000 +0x8e8 0xd8080000 +0x8ec 0x00000000 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000f00 +0x90c 0x81121313 +0x910 0x024c0000 +0x914 0x00000000 +0x918 0x00000000 +0x91c 0x00000000 +0x920 0x00000000 +0x924 0x00000000 +0x928 0x00000000 +0x92c 0x00010040 +0x930 0x88000000 +0x934 0x00000245 +0x938 0x00024588 +0x93c 0x00000000 +0x940 0x000007ff +0x944 0x7F7F0000 +0x948 0x000001A3 +0x94c 0x20200008 +0x950 0x00338697 +0x954 0x00000000 +0x958 0x4bc7b87a +0x95c 0x06eb9b79 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000100 +0x96c 0x00000003 +0x970 0x00000000 +0x974 0x00000000 +0x978 0x00000000 +0x97c 0x10030000 +0x980 0x00000000 +0x984 0x00050050 +0x988 0x000a560e +0x98c 0x1461c826 +0x990 0x0001469e +0x994 0x008858d1 +0x998 0x700086c9 +0x99c 0x77777777 +0x9a0 0x00000000 +0x9a4 0x00000000 +0x9a8 0x00000000 +0x9ac 0x00020000 +0x9b0 0x00000000 +0x9b4 0x00000000 +0x9b8 0x00000000 +0x9bc 0x00000000 +0x9c0 0x00000011 +0x9c4 0x00000000 +0x9c8 0x00000000 +0x9cc 0x00000000 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e0 0x00000000 +0x9e4 0x00000000 +0x9e8 0x00000000 +0x9ec 0x00000000 +0x9f0 0x80000000 +0x9f4 0x00000000 +0x9f8 0x00000000 +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff800c +0xa08 0x8c838300 +0xa0c 0x2e20200f +0xa10 0x9500bb78 +0xa14 0x1114D028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0xe82c0001 +0xa24 0x64b80c1c +0xa28 0x00008810 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000107 +0xa78 0x00008900 +0xa7c 0x225b0606 +0xa80 0x2180Fa74 //88E: CCK LNA 2 to 3 bit mapping:0xa80[23]=1b1 0xa80[7]=1b1 CCK agc_rpt as new format +//0xa80 0x21003210 +0xa84 0x00200000 +0xa88 0x040c0000 +0xa8c 0x12345678 +0xa90 0xabcdef00 +0xa94 0x801b1b89 // a97[7]=1 for CCK tx wrong length +0xa98 0x00000000 +0xa9c 0x00020000 +0xaa0 0x00000000 +0xaa8 0xeaaf0000 // r_MF_FA_drop_en=1 r_CS_ratio_sel_new=0xf +0xaac 0x01235667 +0xab0 0x00000000 +// +//======================= +// PAGE_B +//======================= +0xb00 0x00000000 +0xb04 0x00000000 +0xb08 0x00000000 +0xb0c 0x00000000 +0xb10 0x00000000 +0xb14 0x00000000 +0xb18 0x00000000 +0xb1c 0x00000000 +0xb20 0x00000000 +0xb24 0x00000000 +0xb28 0x00000000 +0xb2c 0x00000000 +0xb30 0x00000000 +0xb34 0x00000000 +0xb38 0x00000000 +0xb3c 0x00000000 +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x00000000 +0xb4c 0x00000000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +0xb60 0x00000000 +0xb64 0x00000000 +0xb68 0x80000000 +0xb6c 0x80000000 +0xb70 0x00000000 +0xb74 0x00000000 +0xb78 0x00000000 +0xb7c 0x00000000 +0xb80 0x00000000 +0xb84 0x00000000 +0xb88 0x00000000 +0xb8c 0x00000000 +0xb90 0x00000000 +0xb94 0x00000000 +0xb98 0x00000000 +0xb9c 0x00000000 +0xba0 0x00000000 +0xba4 0x00000000 +0xba8 0x00000000 +0xbac 0x00000000 +0xbb0 0x00440000 +0xbb4 0x00000000 +0xbb8 0x00000000 +0xbbc 0x00000000 +0xbd0 0x00000000 +0xbd4 0x00000000 +0xbdc 0x02000000 +0xbe0 0x02000000 +0xbe4 0x02000000 +0xbe8 0x02000000 +0xbec 0x02000000 +0xbf0 0x02000000 +0xbf4 0x02000000 +0xbf8 0x02000000 +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x00000080 +0xc04 0x6f005433 +0xc08 0x000004e4 +0xc0c 0x6c6c6c6c +0xc10 0x20000000 // down sample factor for pathA is 4 +0xc14 0x40000100 +0xc18 0x20000000 // down sample factor for pathB is 4 +0xc1c 0x40000100 +0xc20 0x00000000 +0xc24 0x40000100 +0xc28 0x00000000 +0xc2c 0x40000100 +0xc30 0x0401a803 +0xc34 0x30000040 +0xc38 0x23408080 +0xc3c 0x00002b14 +0xc40 0x1cfc403f +0xc44 0x000100c7 +0xc48 0xec060106 +0xc4c 0x00f203fd +0xc50 0x00340020 +0xc54 0x04008017 +0xc58 0x00000020 +0xc5c 0x0070CDB6 // RXHP MSB is 1 since RF CCK_IND is inverted +0xc60 0x00280200 // default 20M tx filter apply old coeff. +0xc64 0x5012838b +0xc68 0x47c006c7 +0xc6c 0x00000035 +0xc70 0x00000007 +0xc74 0x020251A7 +0xc78 0x0fe07f1f +0xc7c 0x09BC1612 // RXHP MSB is 1 since RF CCK_IND is inverted +0xc80 0x40000100 +0xc84 0x12000000 +0xc88 0x40000100 +0xc8c 0xa0240000 +0xc90 0x40000100 +0xc94 0x00000000 +0xc98 0x40000100 +0xc9c 0x0000bdc8 +0xca0 0x00000000 +0xca4 0x098300a0 +0xca8 0x00000000 +0xcac 0x00057b1a +0xcb0 0x00000000 +0xcb4 0x00000000 +0xcb8 0x00000000 +0xcbc 0x28100200 +0xcc0 0x0010a3d0 +0xcc4 0x00000f7d +0xcc8 0x00000000 +0xccc 0x00000000 +0xcd0 0x00000000 +0xcd4 0x00000000 +0xcd8 0x64b22427 +0xcdc 0x00766932 +0xce0 0x40201006 +0xce4 0x00000000 +0xce8 0x40e04407 +0xcec 0x2e572000 +0xcf0 0x00000000 +0xcf4 0x00000000 +0xcf8 0x00000000 +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x000b0680 +0xd04 0xc0000403 +0xd08 0x00000087 +0xd0c 0x00000201 +0xd10 0x06288888 +0xd14 0x8888366b +0xd18 0x7d806db3 +0xd1c 0x00000000 +0xd20 0x167401b8 +0xd24 0x00000186 +0xd28 0xd513ff7d +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x40608000 +0xd38 0xa8000000 +0xd3c 0x00026ee2 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x20500000 +0xd58 0x16161616 +0xd5c 0x70320064 +0xd60 0x4653dee0 +0xd64 0x7e718a3c +0xd68 0x00000103 +0xd6c 0x00000000 +0xd70 0x00000000 +0xd74 0x00000000 +0xd78 0x00000000 +0xd7c 0x00000000 +0xd80 0x00000000 +0xd84 0x31310000 +0xd88 0x05b57e00 +0xd8c 0x00000000 +0xd90 0x00000000 +0xd94 0x44bbbb44 // ANAPAR pow (TX_CCK_RFON RX_WAIT_CCA Blue-Tooth RX AD3 CCA mode) +0xd98 0x44bb44ff // ANAPAR pow (TX_TO_TX TX_TO_RX TX_OFDM_RFBBON TestMode) +0xd9c 0x08023688 +0xda0 0x00000002 +0xda4 0x00000000 +0xda8 0x00000000 +0xdac 0x00000000 +0xdb0 0x00000000 +0xdb4 0x00000000 +0xdb8 0x00000000 +0xdbc 0x00000000 +0xdc0 0x00000000 +0xdc4 0x00210000 +0xdc8 0x00000200 +0xdcc 0x0000000f +0xdd0 0x00000020 +0xdd4 0x00007f7f +0xdd8 0xe5af1854 +0xddc 0x000040ab +0xde0 0x00000000 +0xde4 0x00000000 +0xde8 0x0002030b +0xdec 0x0000a987 +0xdf0 0x00005807 +0xdf4 0x00000000 +0xdf8 0x00000005 +//======================= +// PAGE_E +//======================= +0xe00 0x00000000 +0xe04 0x00000000 +0xe08 0x00000000 +0xe0c 0x000000ff // ANAPAR pow (CCA_LP) +0xe10 0x00000000 +0xe14 0x00000000 +0xe18 0x00000000 +0xe1c 0x00000000 +0xe20 0x00000000 +0xe24 0x00200000 +0xe28 0x00000000 +0xe2c 0x00000000 +0xe30 0x01007c00 +0xe34 0x01004800 +0xe38 0x10008c0f +0xe3c 0x3c008c0f +0xe40 0x02100000 +0xe44 0x00000000 +0xe48 0x00000000 +0xe4c 0x00000000 +0xe50 0x01007c00 +0xe54 0x01004800 +0xe58 0x10008c0f +0xe5c 0x3c008c0f +0xe60 0x02100000 +0xe64 0xbbbbbbbb // ANAPAR pow (RX_TO_RX RX_WAIT_RIFS RX_OFDM RX_CCK) +0xe68 0x40404040 // ANAPAR control RX AD3 CCA mode (rx off) +0xe6c 0x80408040 // ANAPAR control Blue-Tooth (tx off) +0xe70 0x80408040 // ANAPAR control RX_WAIT_CCA (tx off) +0xe74 0x40404040 // ANAPAR control TX_CCK_RFBBON (rx off) +0xe78 0x00400040 // ANAPAR control TestMode (trx on) +0xe7c 0x40404040 // ANAPAR control TX_OFDM_RFBBON (rx off) +0xe80 0x00ff0000 // ANAPAR pow (PMPD_ANAEN Sleep Standby) +0xe84 0x80408040 // ANAPAR control TX_TO_RX (tx off) +0xe88 0x40404040 // ANAPAR control TX_TO_TX (rx off) +0xe8c 0x80408040 // ANAPAR control RX_CCK (tx off) +0xe90 0x00000000 +0xe94 0x01000000 +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000000 +0xea4 0x01000000 +0xea8 0x00000000 +0xeac 0x00000000 +0xeb0 0x00000000 +0xeb4 0x01000000 +0xeb8 0x00000000 +0xebc 0x00000000 +0xec0 0x00000000 +0xec4 0x01000000 +0xec8 0x00000000 +0xecc 0x00000000 +0xed0 0x80408040 // ANAPAR control RX_OFDM (tx off) +0xed4 0x80408040 // ANAPAR control RX_WAIT_RIFS (tx off) +0xed8 0x80408040 // ANAPAR control RX_TO_RX (tx off) +0xedc 0xC040C040 // ANAPAR control Standby (trx off) +0xee0 0xC040C040 // ANAPAR control Sleep (trx off) +0xee4 0x00400040 // ANAPAR control PMPD_ANAEN (trx on) +0xee8 0xd8001402 // anapar_bb_antb[31:0] +0xeec 0xc0000120 // anapar_bb_anta[63:32] +0xef0 0x02000b09 +0xef4 0x00000001 +0xef8 0x00000000 +//======================= +// PAGE_F +//======================= +0xf00 0x00000300 +0xf04 0x00000000 +0xf08 0x0002030b +0xf0c 0x0000a987 +0xf10 0x00005807 +0xf14 0x00000003 +0xf18 0x00020002 +0xf1c 0x8000001f +0xf20 0x00000000 +0xf24 0x00000000 +0xf28 0x00000000 +0xf2c 0x00000000 +0xf30 0x00000000 +0xf34 0x00000000 +0xf38 0x00030155 +0xf3c 0x0000003a +0xf40 0x00000000 +0xf44 0x00000000 +0xf48 0x00000000 +0xf4c 0x13000000 +0xf50 0x00000010 +0xf54 0x00000000 +0xf58 0x00000000 +0xf5c 0x00000000 +0xf60 0x00000000 +0xf64 0x00000000 +0xf68 0x00000000 +0xf6c 0x00000000 +0xf70 0x00000000 +0xf74 0x00000000 +0xf78 0x00000000 +0xf7c 0x00000000 +0xf80 0x00000000 +0xf84 0x00000000 +0xf88 0x00000000 +0xf8c 0x00000000 +0xf90 0x00000002 +0xf94 0x00000000 +0xf98 0x00000000 +0xf9c 0x00000000 +0xfa0 0x00000000 +0xfa4 0x0002030b +0xfa8 0x0000a987 +0xfac 0x00005807 +0xfb0 0x00000000 +0xfb4 0x00000000 +0xfb8 0x00000000 +0xfbc 0x00000000 +0xfc0 0x00c02001 +0xfc4 0x90063000 +0xfc8 0x00000018 +0xfcc 0x10003005 +0xfd0 0x0000e5af +0xfd4 0x00000000 +0xfd8 0x00000000 +0xfdc 0x00000000 +0xfe0 0x00000000 +0xfe4 0x00000000 +0xfe8 0x00000000 +0xfec 0x00000000 +0xff0 0x00000000 +0xff4 0x00000000 +0xff8 0x00000000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F_hp.txt old mode 100755 new mode 100644 index 00cea3c0827..ea89240ba15 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197F_hp.txt @@ -1,960 +1,960 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57759178 -0x830 0xb79cea8B -0x834 0x0400c486 -0x838 0x87aa4330 -0x83c 0x4799477a -0x840 0x137780e0 -0x844 0x45bcfcde -0x848 0x5cd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x00015204 -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40c4e0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80024d69 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000100 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4a0000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x06510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00798079 -0xc6c 0x00794079 -0xc70 0x80794079 -0xc74 0x80794079 -0xc78 0x80798079 -0xc7c 0x00798079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x010000dd // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x00798079 -0xe6c 0x00794079 -0xe70 0x80794079 -0xe74 0x80794079 -0xe78 0x80798079 -0xe7c 0x00798079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x010000dd // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x00798079 -0x186c 0x00794079 -0x1870 0x80794079 -0x1874 0x80794079 -0x1878 0x80798079 -0x187c 0x00798079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x010000dd // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x00798079 -0x1a6c 0x00794079 -0x1a70 0x80794079 -0x1a74 0x80794079 -0x1a78 0x80798079 -0x1a7c 0x00798079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x010000dd //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x1914 0x00030000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe2461690 -0x1b10 0x00000d46 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x00080005 -0x1b80 0x00080007 -0x1b80 0x80000015 -0x1b80 0x80000017 -0x1b80 0x00040025 -0x1b80 0x00040027 -0x1b80 0x4a000035 -0x1b80 0x4a000037 -0x1b80 0x4b040045 -0x1b80 0x4b040047 -0x1b80 0x85030055 -0x1b80 0x85030057 -0x1b80 0x40010065 -0x1b80 0x40010067 -0x1b80 0xe01b0075 -0x1b80 0xe01b0077 -0x1b80 0x00040085 -0x1b80 0x00040087 -0x1b80 0x4b050095 -0x1b80 0x4b050097 -0x1b80 0x860300a5 -0x1b80 0x860300a7 -0x1b80 0x400300b5 -0x1b80 0x400300b7 -0x1b80 0xe01b00c5 -0x1b80 0xe01b00c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x4b0600e5 -0x1b80 0x4b0600e7 -0x1b80 0x870300f5 -0x1b80 0x870300f7 -0x1b80 0x40050105 -0x1b80 0x40050107 -0x1b80 0xe01b0115 -0x1b80 0xe01b0117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4b070135 -0x1b80 0x4b070137 -0x1b80 0x88030145 -0x1b80 0x88030147 -0x1b80 0x40070155 -0x1b80 0x40070157 -0x1b80 0xe01b0165 -0x1b80 0xe01b0167 -0x1b80 0x4b000175 -0x1b80 0x4b000177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x40000195 -0x1b80 0x40000197 -0x1b80 0x300001a5 -0x1b80 0x300001a7 -0x1b80 0xf00a01b5 -0x1b80 0xf00a01b7 -0x1b80 0xf10a01c5 -0x1b80 0xf10a01c7 -0x1b80 0xf20a01d5 -0x1b80 0xf20a01d7 -0x1b80 0xf30a01e5 -0x1b80 0xf30a01e7 -0x1b80 0xf40a01f5 -0x1b80 0xf40a01f7 -0x1b80 0xf50a0205 -0x1b80 0xf50a0207 -0x1b80 0xf60a0215 -0x1b80 0xf60a0217 -0x1b80 0xfe0a0225 -0x1b80 0xfe0a0227 -0x1b80 0xff0a0235 -0x1b80 0xff0a0237 -0x1b80 0x00010245 -0x1b80 0x00010247 -0x1b80 0x302e0255 -0x1b80 0x302e0257 -0x1b80 0x30340265 -0x1b80 0x30340267 -0x1b80 0x303a0275 -0x1b80 0x303a0277 -0x1b80 0x30500285 -0x1b80 0x30500287 -0x1b80 0x303a0295 -0x1b80 0x303a0297 -0x1b80 0x303402a5 -0x1b80 0x303402a7 -0x1b80 0x303a02b5 -0x1b80 0x303a02b7 -0x1b80 0x30d002c5 -0x1b80 0x30d002c7 -0x1b80 0x30b302d5 -0x1b80 0x30b302d7 -0x1b80 0xe06602e5 -0x1b80 0xe06602e7 -0x1b80 0x580002f5 -0x1b80 0x580002f7 -0x1b80 0x5c720305 -0x1b80 0x5c720307 -0x1b80 0x63400315 -0x1b80 0x63400317 -0x1b80 0xe0750325 -0x1b80 0xe0750327 -0x1b80 0x00010335 -0x1b80 0x00010337 -0x1b80 0xe0660345 -0x1b80 0xe0660347 -0x1b80 0x5c720355 -0x1b80 0x5c720357 -0x1b80 0x63400365 -0x1b80 0x63400367 -0x1b80 0x0ba60375 -0x1b80 0x0ba60377 -0x1b80 0xe0790385 -0x1b80 0xe0790387 -0x1b80 0x00010395 -0x1b80 0x00010397 -0x1b80 0xe06603a5 -0x1b80 0xe06603a7 -0x1b80 0x580303b5 -0x1b80 0x580303b7 -0x1b80 0x5cf103c5 -0x1b80 0x5cf103c7 -0x1b80 0x4d0403d5 -0x1b80 0x4d0403d7 -0x1b80 0x000703e5 -0x1b80 0x000703e7 -0x1b80 0x640203f5 -0x1b80 0x640203f7 -0x1b80 0x2ef80405 -0x1b80 0x2ef80407 -0x1b80 0x00020415 -0x1b80 0x00020417 -0x1b80 0x23030425 -0x1b80 0x23030427 -0x1b80 0x00000435 -0x1b80 0x00000437 -0x1b80 0x23130445 -0x1b80 0x23130447 -0x1b80 0xe77f0455 -0x1b80 0xe77f0457 -0x1b80 0x232f0465 -0x1b80 0x232f0467 -0x1b80 0xe79f0475 -0x1b80 0xe79f0477 -0x1b80 0x2ef00485 -0x1b80 0x2ef00487 -0x1b80 0x00020495 -0x1b80 0x00020497 -0x1b80 0x640004a5 -0x1b80 0x640004a7 -0x1b80 0x000404b5 -0x1b80 0x000404b7 -0x1b80 0x4d0004c5 -0x1b80 0x4d0004c7 -0x1b80 0x0ba604d5 -0x1b80 0x0ba604d7 -0x1b80 0xe08304e5 -0x1b80 0xe08304e7 -0x1b80 0x000104f5 -0x1b80 0x000104f7 -0x1b80 0xe0660505 -0x1b80 0xe0660507 -0x1b80 0x5c720515 -0x1b80 0x5c720517 -0x1b80 0x4d040525 -0x1b80 0x4d040527 -0x1b80 0x00070535 -0x1b80 0x00070537 -0x1b80 0x64020545 -0x1b80 0x64020547 -0x1b80 0x2ef80555 -0x1b80 0x2ef80557 -0x1b80 0x00020565 -0x1b80 0x00020567 -0x1b80 0x23030575 -0x1b80 0x23030577 -0x1b80 0x00000585 -0x1b80 0x00000587 -0x1b80 0x23130595 -0x1b80 0x23130597 -0x1b80 0xe77f05a5 -0x1b80 0xe77f05a7 -0x1b80 0x232f05b5 -0x1b80 0x232f05b7 -0x1b80 0xe93f05c5 -0x1b80 0xe93f05c7 -0x1b80 0x2ef005d5 -0x1b80 0x2ef005d7 -0x1b80 0x000205e5 -0x1b80 0x000205e7 -0x1b80 0x640005f5 -0x1b80 0x640005f7 -0x1b80 0x00040605 -0x1b80 0x00040607 -0x1b80 0x4d000615 -0x1b80 0x4d000617 -0x1b80 0x63600625 -0x1b80 0x63600627 -0x1b80 0x0ba60635 -0x1b80 0x0ba60637 -0x1b80 0xe0790645 -0x1b80 0xe0790647 -0x1b80 0x00010655 -0x1b80 0x00010657 -0x1b80 0x00070665 -0x1b80 0x00070667 -0x1b80 0x54010675 -0x1b80 0x54010677 -0x1b80 0x00040685 -0x1b80 0x00040687 -0x1b80 0x7b200695 -0x1b80 0x7b200697 -0x1b80 0x7a0006a5 -0x1b80 0x7a0006a7 -0x1b80 0x790006b5 -0x1b80 0x790006b7 -0x1b80 0x7f2006c5 -0x1b80 0x7f2006c7 -0x1b80 0x7e0006d5 -0x1b80 0x7e0006d7 -0x1b80 0x7d0006e5 -0x1b80 0x7d0006e7 -0x1b80 0x090106f5 -0x1b80 0x090106f7 -0x1b80 0x0c010705 -0x1b80 0x0c010707 -0x1b80 0x0d020715 -0x1b80 0x0d020717 -0x1b80 0x0e040725 -0x1b80 0x0e040727 -0x1b80 0x0f080735 -0x1b80 0x0f080737 -0x1b80 0x00010745 -0x1b80 0x00010747 -0x1b80 0x74010755 -0x1b80 0x74010757 -0x1b80 0x74000765 -0x1b80 0x74000767 -0x1b80 0x8e000775 -0x1b80 0x8e000777 -0x1b80 0x00010785 -0x1b80 0x00010787 -0x1b80 0xe08c0795 -0x1b80 0xe08c0797 -0x1b80 0x548007a5 -0x1b80 0x548007a7 -0x1b80 0x580107b5 -0x1b80 0x580107b7 -0x1b80 0xe08c07c5 -0x1b80 0xe08c07c7 -0x1b80 0x548107d5 -0x1b80 0x548107d7 -0x1b80 0xe08c07e5 -0x1b80 0xe08c07e7 -0x1b80 0x548207f5 -0x1b80 0x548207f7 -0x1b80 0xe09e0805 -0x1b80 0xe09e0807 -0x1b80 0x07140815 -0x1b80 0x07140817 -0x1b80 0x00010825 -0x1b80 0x00010827 -0x1b80 0xe0950835 -0x1b80 0xe0950837 -0x1b80 0x54800845 -0x1b80 0x54800847 -0x1b80 0xe0950855 -0x1b80 0xe0950857 -0x1b80 0x54810865 -0x1b80 0x54810867 -0x1b80 0xe0950875 -0x1b80 0xe0950877 -0x1b80 0x54820885 -0x1b80 0x54820887 -0x1b80 0xe09e0895 -0x1b80 0xe09e0897 -0x1b80 0x071408a5 -0x1b80 0x071408a7 -0x1b80 0x000108b5 -0x1b80 0x000108b7 -0x1b80 0x002a08c5 -0x1b80 0x002a08c7 -0x1b80 0x740108d5 -0x1b80 0x740108d7 -0x1b80 0x740008e5 -0x1b80 0x740008e7 -0x1b80 0x8e0008f5 -0x1b80 0x8e0008f7 -0x1b80 0x30930905 -0x1b80 0x30930907 -0x1b80 0x00020915 -0x1b80 0x00020917 -0x1b80 0x30180925 -0x1b80 0x30180927 -0x1b80 0x050a0935 -0x1b80 0x050a0937 -0x1b80 0x00010945 -0x1b80 0x00010947 -0x1b80 0x002a0955 -0x1b80 0x002a0957 -0x1b80 0x74010965 -0x1b80 0x74010967 -0x1b80 0x74000975 -0x1b80 0x74000977 -0x1b80 0x8e000985 -0x1b80 0x8e000987 -0x1b80 0x309c0995 -0x1b80 0x309c0997 -0x1b80 0x000209a5 -0x1b80 0x000209a7 -0x1b80 0x301809b5 -0x1b80 0x301809b7 -0x1b80 0x050a09c5 -0x1b80 0x050a09c7 -0x1b80 0x000109d5 -0x1b80 0x000109d7 -0x1b80 0x54c009e5 -0x1b80 0x54c009e7 -0x1b80 0x54a309f5 -0x1b80 0x54a309f7 -0x1b80 0x54c10a05 -0x1b80 0x54c10a07 -0x1b80 0x54a40a15 -0x1b80 0x54a40a17 -0x1b80 0x4c830a25 -0x1b80 0x4c830a27 -0x1b80 0x4c030a35 -0x1b80 0x4c030a37 -0x1b80 0xbf0c0a45 -0x1b80 0xbf0c0a47 -0x1b80 0x54c20a55 -0x1b80 0x54c20a57 -0x1b80 0x54a40a65 -0x1b80 0x54a40a67 -0x1b80 0x4c850a75 -0x1b80 0x4c850a77 -0x1b80 0x4c050a85 -0x1b80 0x4c050a87 -0x1b80 0xbf070a95 -0x1b80 0xbf070a97 -0x1b80 0x54c10aa5 -0x1b80 0x54c10aa7 -0x1b80 0x54a30ab5 -0x1b80 0x54a30ab7 -0x1b80 0x4c860ac5 -0x1b80 0x4c860ac7 -0x1b80 0x4c060ad5 -0x1b80 0x4c060ad7 -0x1b80 0xbf020ae5 -0x1b80 0xbf020ae7 -0x1b80 0x30180af5 -0x1b80 0x30180af7 -0x1b80 0x54e50b05 -0x1b80 0x54e50b07 -0x1b80 0x050a0b15 -0x1b80 0x050a0b17 -0x1b80 0x00010b25 -0x1b80 0x00010b27 -0x1b80 0x00070b35 -0x1b80 0x00070b37 -0x1b80 0x64020b45 -0x1b80 0x64020b47 -0x1b80 0x00040b55 -0x1b80 0x00040b57 -0x1b80 0x6bc00b65 -0x1b80 0x6bc00b67 -0x1b80 0x68a00b75 -0x1b80 0x68a00b77 -0x1b80 0x67600b85 -0x1b80 0x67600b87 -0x1b80 0x66800b95 -0x1b80 0x66800b97 -0x1b80 0x65700ba5 -0x1b80 0x65700ba7 -0x1b80 0x4d040bb5 -0x1b80 0x4d040bb7 -0x1b80 0x23410bc5 -0x1b80 0x23410bc7 -0x1b80 0x01e40bd5 -0x1b80 0x01e40bd7 -0x1b80 0x23410be5 -0x1b80 0x23410be7 -0x1b80 0x11e60bf5 -0x1b80 0x11e60bf7 -0x1b80 0x23410c05 -0x1b80 0x23410c07 -0x1b80 0x21e80c15 -0x1b80 0x21e80c17 -0x1b80 0x23410c25 -0x1b80 0x23410c27 -0x1b80 0x31ea0c35 -0x1b80 0x31ea0c37 -0x1b80 0x23410c45 -0x1b80 0x23410c47 -0x1b80 0x40210c55 -0x1b80 0x40210c57 -0x1b80 0x23410c65 -0x1b80 0x23410c67 -0x1b80 0x50610c75 -0x1b80 0x50610c77 -0x1b80 0x23410c85 -0x1b80 0x23410c87 -0x1b80 0x60e10c95 -0x1b80 0x60e10c97 -0x1b80 0x23410ca5 -0x1b80 0x23410ca7 -0x1b80 0x70210cb5 -0x1b80 0x70210cb7 -0x1b80 0x4d000cc5 -0x1b80 0x4d000cc7 -0x1b80 0x00070cd5 -0x1b80 0x00070cd7 -0x1b80 0x64000ce5 -0x1b80 0x64000ce7 -0x1b80 0x00010cf5 -0x1b80 0x00010cf7 -0x1b80 0x00070d05 -0x1b80 0x00070d07 -0x1b80 0x64020d15 -0x1b80 0x64020d17 -0x1b80 0x00040d25 -0x1b80 0x00040d27 -0x1b80 0x6b400d35 -0x1b80 0x6b400d37 -0x1b80 0x68a00d45 -0x1b80 0x68a00d47 -0x1b80 0x67600d55 -0x1b80 0x67600d57 -0x1b80 0x66c00d65 -0x1b80 0x66c00d67 -0x1b80 0x65700d75 -0x1b80 0x65700d77 -0x1b80 0x4d040d85 -0x1b80 0x4d040d87 -0x1b80 0x23410d95 -0x1b80 0x23410d97 -0x1b80 0x01e30da5 -0x1b80 0x01e30da7 -0x1b80 0x23410db5 -0x1b80 0x23410db7 -0x1b80 0x11e40dc5 -0x1b80 0x11e40dc7 -0x1b80 0x23410dd5 -0x1b80 0x23410dd7 -0x1b80 0x21e50de5 -0x1b80 0x21e50de7 -0x1b80 0x23410df5 -0x1b80 0x23410df7 -0x1b80 0x31e60e05 -0x1b80 0x31e60e07 -0x1b80 0x23410e15 -0x1b80 0x23410e17 -0x1b80 0x40010e25 -0x1b80 0x40010e27 -0x1b80 0x23410e35 -0x1b80 0x23410e37 -0x1b80 0x50210e45 -0x1b80 0x50210e47 -0x1b80 0x23410e55 -0x1b80 0x23410e57 -0x1b80 0x60410e65 -0x1b80 0x60410e67 -0x1b80 0x23410e75 -0x1b80 0x23410e77 -0x1b80 0x71010e85 -0x1b80 0x71010e87 -0x1b80 0x4d000e95 -0x1b80 0x4d000e97 -0x1b80 0x00070ea5 -0x1b80 0x00070ea7 -0x1b80 0x64000eb5 -0x1b80 0x64000eb7 -0x1b80 0x00010ec5 -0x1b80 0x00010ec7 -0x1b80 0x00000006 -0x1b80 0x00000002 - +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57759178 +0x830 0xb79cea8B +0x834 0x0400c486 +0x838 0x87aa4330 +0x83c 0x4799477a +0x840 0x137780e0 +0x844 0x45bcfcde +0x848 0x5cd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x00015204 +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40c4e0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80024d69 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000100 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4a0000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x06510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00798079 +0xc6c 0x00794079 +0xc70 0x80794079 +0xc74 0x80794079 +0xc78 0x80798079 +0xc7c 0x00798079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x010000dd // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x00798079 +0xe6c 0x00794079 +0xe70 0x80794079 +0xe74 0x80794079 +0xe78 0x80798079 +0xe7c 0x00798079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x010000dd // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x00798079 +0x186c 0x00794079 +0x1870 0x80794079 +0x1874 0x80794079 +0x1878 0x80798079 +0x187c 0x00798079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x010000dd // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x00798079 +0x1a6c 0x00794079 +0x1a70 0x80794079 +0x1a74 0x80794079 +0x1a78 0x80798079 +0x1a7c 0x00798079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x010000dd //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x1914 0x00030000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe2461690 +0x1b10 0x00000d46 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x00080005 +0x1b80 0x00080007 +0x1b80 0x80000015 +0x1b80 0x80000017 +0x1b80 0x00040025 +0x1b80 0x00040027 +0x1b80 0x4a000035 +0x1b80 0x4a000037 +0x1b80 0x4b040045 +0x1b80 0x4b040047 +0x1b80 0x85030055 +0x1b80 0x85030057 +0x1b80 0x40010065 +0x1b80 0x40010067 +0x1b80 0xe01b0075 +0x1b80 0xe01b0077 +0x1b80 0x00040085 +0x1b80 0x00040087 +0x1b80 0x4b050095 +0x1b80 0x4b050097 +0x1b80 0x860300a5 +0x1b80 0x860300a7 +0x1b80 0x400300b5 +0x1b80 0x400300b7 +0x1b80 0xe01b00c5 +0x1b80 0xe01b00c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x4b0600e5 +0x1b80 0x4b0600e7 +0x1b80 0x870300f5 +0x1b80 0x870300f7 +0x1b80 0x40050105 +0x1b80 0x40050107 +0x1b80 0xe01b0115 +0x1b80 0xe01b0117 +0x1b80 0x00040125 +0x1b80 0x00040127 +0x1b80 0x4b070135 +0x1b80 0x4b070137 +0x1b80 0x88030145 +0x1b80 0x88030147 +0x1b80 0x40070155 +0x1b80 0x40070157 +0x1b80 0xe01b0165 +0x1b80 0xe01b0167 +0x1b80 0x4b000175 +0x1b80 0x4b000177 +0x1b80 0x00040185 +0x1b80 0x00040187 +0x1b80 0x40000195 +0x1b80 0x40000197 +0x1b80 0x300001a5 +0x1b80 0x300001a7 +0x1b80 0xf00a01b5 +0x1b80 0xf00a01b7 +0x1b80 0xf10a01c5 +0x1b80 0xf10a01c7 +0x1b80 0xf20a01d5 +0x1b80 0xf20a01d7 +0x1b80 0xf30a01e5 +0x1b80 0xf30a01e7 +0x1b80 0xf40a01f5 +0x1b80 0xf40a01f7 +0x1b80 0xf50a0205 +0x1b80 0xf50a0207 +0x1b80 0xf60a0215 +0x1b80 0xf60a0217 +0x1b80 0xfe0a0225 +0x1b80 0xfe0a0227 +0x1b80 0xff0a0235 +0x1b80 0xff0a0237 +0x1b80 0x00010245 +0x1b80 0x00010247 +0x1b80 0x302e0255 +0x1b80 0x302e0257 +0x1b80 0x30340265 +0x1b80 0x30340267 +0x1b80 0x303a0275 +0x1b80 0x303a0277 +0x1b80 0x30500285 +0x1b80 0x30500287 +0x1b80 0x303a0295 +0x1b80 0x303a0297 +0x1b80 0x303402a5 +0x1b80 0x303402a7 +0x1b80 0x303a02b5 +0x1b80 0x303a02b7 +0x1b80 0x30d002c5 +0x1b80 0x30d002c7 +0x1b80 0x30b302d5 +0x1b80 0x30b302d7 +0x1b80 0xe06602e5 +0x1b80 0xe06602e7 +0x1b80 0x580002f5 +0x1b80 0x580002f7 +0x1b80 0x5c720305 +0x1b80 0x5c720307 +0x1b80 0x63400315 +0x1b80 0x63400317 +0x1b80 0xe0750325 +0x1b80 0xe0750327 +0x1b80 0x00010335 +0x1b80 0x00010337 +0x1b80 0xe0660345 +0x1b80 0xe0660347 +0x1b80 0x5c720355 +0x1b80 0x5c720357 +0x1b80 0x63400365 +0x1b80 0x63400367 +0x1b80 0x0ba60375 +0x1b80 0x0ba60377 +0x1b80 0xe0790385 +0x1b80 0xe0790387 +0x1b80 0x00010395 +0x1b80 0x00010397 +0x1b80 0xe06603a5 +0x1b80 0xe06603a7 +0x1b80 0x580303b5 +0x1b80 0x580303b7 +0x1b80 0x5cf103c5 +0x1b80 0x5cf103c7 +0x1b80 0x4d0403d5 +0x1b80 0x4d0403d7 +0x1b80 0x000703e5 +0x1b80 0x000703e7 +0x1b80 0x640203f5 +0x1b80 0x640203f7 +0x1b80 0x2ef80405 +0x1b80 0x2ef80407 +0x1b80 0x00020415 +0x1b80 0x00020417 +0x1b80 0x23030425 +0x1b80 0x23030427 +0x1b80 0x00000435 +0x1b80 0x00000437 +0x1b80 0x23130445 +0x1b80 0x23130447 +0x1b80 0xe77f0455 +0x1b80 0xe77f0457 +0x1b80 0x232f0465 +0x1b80 0x232f0467 +0x1b80 0xe79f0475 +0x1b80 0xe79f0477 +0x1b80 0x2ef00485 +0x1b80 0x2ef00487 +0x1b80 0x00020495 +0x1b80 0x00020497 +0x1b80 0x640004a5 +0x1b80 0x640004a7 +0x1b80 0x000404b5 +0x1b80 0x000404b7 +0x1b80 0x4d0004c5 +0x1b80 0x4d0004c7 +0x1b80 0x0ba604d5 +0x1b80 0x0ba604d7 +0x1b80 0xe08304e5 +0x1b80 0xe08304e7 +0x1b80 0x000104f5 +0x1b80 0x000104f7 +0x1b80 0xe0660505 +0x1b80 0xe0660507 +0x1b80 0x5c720515 +0x1b80 0x5c720517 +0x1b80 0x4d040525 +0x1b80 0x4d040527 +0x1b80 0x00070535 +0x1b80 0x00070537 +0x1b80 0x64020545 +0x1b80 0x64020547 +0x1b80 0x2ef80555 +0x1b80 0x2ef80557 +0x1b80 0x00020565 +0x1b80 0x00020567 +0x1b80 0x23030575 +0x1b80 0x23030577 +0x1b80 0x00000585 +0x1b80 0x00000587 +0x1b80 0x23130595 +0x1b80 0x23130597 +0x1b80 0xe77f05a5 +0x1b80 0xe77f05a7 +0x1b80 0x232f05b5 +0x1b80 0x232f05b7 +0x1b80 0xe93f05c5 +0x1b80 0xe93f05c7 +0x1b80 0x2ef005d5 +0x1b80 0x2ef005d7 +0x1b80 0x000205e5 +0x1b80 0x000205e7 +0x1b80 0x640005f5 +0x1b80 0x640005f7 +0x1b80 0x00040605 +0x1b80 0x00040607 +0x1b80 0x4d000615 +0x1b80 0x4d000617 +0x1b80 0x63600625 +0x1b80 0x63600627 +0x1b80 0x0ba60635 +0x1b80 0x0ba60637 +0x1b80 0xe0790645 +0x1b80 0xe0790647 +0x1b80 0x00010655 +0x1b80 0x00010657 +0x1b80 0x00070665 +0x1b80 0x00070667 +0x1b80 0x54010675 +0x1b80 0x54010677 +0x1b80 0x00040685 +0x1b80 0x00040687 +0x1b80 0x7b200695 +0x1b80 0x7b200697 +0x1b80 0x7a0006a5 +0x1b80 0x7a0006a7 +0x1b80 0x790006b5 +0x1b80 0x790006b7 +0x1b80 0x7f2006c5 +0x1b80 0x7f2006c7 +0x1b80 0x7e0006d5 +0x1b80 0x7e0006d7 +0x1b80 0x7d0006e5 +0x1b80 0x7d0006e7 +0x1b80 0x090106f5 +0x1b80 0x090106f7 +0x1b80 0x0c010705 +0x1b80 0x0c010707 +0x1b80 0x0d020715 +0x1b80 0x0d020717 +0x1b80 0x0e040725 +0x1b80 0x0e040727 +0x1b80 0x0f080735 +0x1b80 0x0f080737 +0x1b80 0x00010745 +0x1b80 0x00010747 +0x1b80 0x74010755 +0x1b80 0x74010757 +0x1b80 0x74000765 +0x1b80 0x74000767 +0x1b80 0x8e000775 +0x1b80 0x8e000777 +0x1b80 0x00010785 +0x1b80 0x00010787 +0x1b80 0xe08c0795 +0x1b80 0xe08c0797 +0x1b80 0x548007a5 +0x1b80 0x548007a7 +0x1b80 0x580107b5 +0x1b80 0x580107b7 +0x1b80 0xe08c07c5 +0x1b80 0xe08c07c7 +0x1b80 0x548107d5 +0x1b80 0x548107d7 +0x1b80 0xe08c07e5 +0x1b80 0xe08c07e7 +0x1b80 0x548207f5 +0x1b80 0x548207f7 +0x1b80 0xe09e0805 +0x1b80 0xe09e0807 +0x1b80 0x07140815 +0x1b80 0x07140817 +0x1b80 0x00010825 +0x1b80 0x00010827 +0x1b80 0xe0950835 +0x1b80 0xe0950837 +0x1b80 0x54800845 +0x1b80 0x54800847 +0x1b80 0xe0950855 +0x1b80 0xe0950857 +0x1b80 0x54810865 +0x1b80 0x54810867 +0x1b80 0xe0950875 +0x1b80 0xe0950877 +0x1b80 0x54820885 +0x1b80 0x54820887 +0x1b80 0xe09e0895 +0x1b80 0xe09e0897 +0x1b80 0x071408a5 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0xbf0c0a47 +0x1b80 0x54c20a55 +0x1b80 0x54c20a57 +0x1b80 0x54a40a65 +0x1b80 0x54a40a67 +0x1b80 0x4c850a75 +0x1b80 0x4c850a77 +0x1b80 0x4c050a85 +0x1b80 0x4c050a87 +0x1b80 0xbf070a95 +0x1b80 0xbf070a97 +0x1b80 0x54c10aa5 +0x1b80 0x54c10aa7 +0x1b80 0x54a30ab5 +0x1b80 0x54a30ab7 +0x1b80 0x4c860ac5 +0x1b80 0x4c860ac7 +0x1b80 0x4c060ad5 +0x1b80 0x4c060ad7 +0x1b80 0xbf020ae5 +0x1b80 0xbf020ae7 +0x1b80 0x30180af5 +0x1b80 0x30180af7 +0x1b80 0x54e50b05 +0x1b80 0x54e50b07 +0x1b80 0x050a0b15 +0x1b80 0x050a0b17 +0x1b80 0x00010b25 +0x1b80 0x00010b27 +0x1b80 0x00070b35 +0x1b80 0x00070b37 +0x1b80 0x64020b45 +0x1b80 0x64020b47 +0x1b80 0x00040b55 +0x1b80 0x00040b57 +0x1b80 0x6bc00b65 +0x1b80 0x6bc00b67 +0x1b80 0x68a00b75 +0x1b80 0x68a00b77 +0x1b80 0x67600b85 +0x1b80 0x67600b87 +0x1b80 0x66800b95 +0x1b80 0x66800b97 +0x1b80 0x65700ba5 +0x1b80 0x65700ba7 +0x1b80 0x4d040bb5 +0x1b80 0x4d040bb7 +0x1b80 0x23410bc5 +0x1b80 0x23410bc7 +0x1b80 0x01e40bd5 +0x1b80 0x01e40bd7 +0x1b80 0x23410be5 +0x1b80 0x23410be7 +0x1b80 0x11e60bf5 +0x1b80 0x11e60bf7 +0x1b80 0x23410c05 +0x1b80 0x23410c07 +0x1b80 0x21e80c15 +0x1b80 0x21e80c17 +0x1b80 0x23410c25 +0x1b80 0x23410c27 +0x1b80 0x31ea0c35 +0x1b80 0x31ea0c37 +0x1b80 0x23410c45 +0x1b80 0x23410c47 +0x1b80 0x40210c55 +0x1b80 0x40210c57 +0x1b80 0x23410c65 +0x1b80 0x23410c67 +0x1b80 0x50610c75 +0x1b80 0x50610c77 +0x1b80 0x23410c85 +0x1b80 0x23410c87 +0x1b80 0x60e10c95 +0x1b80 0x60e10c97 +0x1b80 0x23410ca5 +0x1b80 0x23410ca7 +0x1b80 0x70210cb5 +0x1b80 0x70210cb7 +0x1b80 0x4d000cc5 +0x1b80 0x4d000cc7 +0x1b80 0x00070cd5 +0x1b80 0x00070cd7 +0x1b80 0x64000ce5 +0x1b80 0x64000ce7 +0x1b80 0x00010cf5 +0x1b80 0x00010cf7 +0x1b80 0x00070d05 +0x1b80 0x00070d07 +0x1b80 0x64020d15 +0x1b80 0x64020d17 +0x1b80 0x00040d25 +0x1b80 0x00040d27 +0x1b80 0x6b400d35 +0x1b80 0x6b400d37 +0x1b80 0x68a00d45 +0x1b80 0x68a00d47 +0x1b80 0x67600d55 +0x1b80 0x67600d57 +0x1b80 0x66c00d65 +0x1b80 0x66c00d67 +0x1b80 0x65700d75 +0x1b80 0x65700d77 +0x1b80 0x4d040d85 +0x1b80 0x4d040d87 +0x1b80 0x23410d95 +0x1b80 0x23410d97 +0x1b80 0x01e30da5 +0x1b80 0x01e30da7 +0x1b80 0x23410db5 +0x1b80 0x23410db7 +0x1b80 0x11e40dc5 +0x1b80 0x11e40dc7 +0x1b80 0x23410dd5 +0x1b80 0x23410dd7 +0x1b80 0x21e50de5 +0x1b80 0x21e50de7 +0x1b80 0x23410df5 +0x1b80 0x23410df7 +0x1b80 0x31e60e05 +0x1b80 0x31e60e07 +0x1b80 0x23410e15 +0x1b80 0x23410e17 +0x1b80 0x40010e25 +0x1b80 0x40010e27 +0x1b80 0x23410e35 +0x1b80 0x23410e37 +0x1b80 0x50210e45 +0x1b80 0x50210e47 +0x1b80 0x23410e55 +0x1b80 0x23410e57 +0x1b80 0x60410e65 +0x1b80 0x60410e67 +0x1b80 0x23410e75 +0x1b80 0x23410e77 +0x1b80 0x71010e85 +0x1b80 0x71010e87 +0x1b80 0x4d000e95 +0x1b80 0x4d000e97 +0x1b80 0x00070ea5 +0x1b80 0x00070ea7 +0x1b80 0x64000eb5 +0x1b80 0x64000eb7 +0x1b80 0x00010ec5 +0x1b80 0x00010ec7 +0x1b80 0x00000006 +0x1b80 0x00000002 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp.txt old mode 100755 new mode 100644 index 88bfc15586e..9a3714d4b66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp.txt @@ -1,397 +1,397 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x080112e0 -0x808 0x0e028277 // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57757178 -0x830 0xa79cea8B -0x834 0x0400c485 -0x838 0x87aa4330 -0x83c 0x479747b9 -0x840 0x037750e0 -0x844 0x45bcfcde -0x848 0x5bd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x04444444 -0x874 0x31612c2e -0x878 0x00003153 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf00f000a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x27f00020 -0x8c4 0x48c00000 -0x8c8 0x80024569 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x49092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x480000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x07fd0080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -//0xb0c 0x01eaa006 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x00100000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3e020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00794079 -0xc6c 0x00798079 -0xc70 0x80798079 -0xc74 0x40798079 -0xc78 0x40794079 -0xc7c 0x00794079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x0100025c // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002915 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3e000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x80794079 -0xe6c 0x80798079 -0xe70 0x80798079 -0xe74 0x40798079 -0xe78 0x40794079 -0xe7c 0x00794079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x0100025c // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002915 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3e000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x80794079 -0x186c 0x80798079 -0x1870 0x80798079 -0x1874 0x40798079 -0x1878 0x40794079 -0x187c 0x00794079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x0100025c // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002915 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3e000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x80794079 -0x1a6c 0x80798079 -0x1a70 0x80798079 -0x1a74 0x40798079 -0x1a78 0x40794079 -0x1a7c 0x00794079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x0100025c //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002915 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x080112e0 +0x808 0x0e028277 // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57757178 +0x830 0xa79cea8B +0x834 0x0400c485 +0x838 0x87aa4330 +0x83c 0x479747b9 +0x840 0x037750e0 +0x844 0x45bcfcde +0x848 0x5bd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x0001520c +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x04444444 +0x874 0x31612c2e +0x878 0x00003153 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf00f000a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x27f00020 +0x8c4 0x48c00000 +0x8c8 0x80024569 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x49092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x480000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x07fd0080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +//0xb0c 0x01eaa006 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x00100000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3e020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00794079 +0xc6c 0x00798079 +0xc70 0x80798079 +0xc74 0x40798079 +0xc78 0x40794079 +0xc7c 0x00794079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x0100025c // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002915 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3e000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x80794079 +0xe6c 0x80798079 +0xe70 0x80798079 +0xe74 0x40798079 +0xe78 0x40794079 +0xe7c 0x00794079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x0100025c // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002915 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3e000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x80794079 +0x186c 0x80798079 +0x1870 0x80798079 +0x1874 0x40798079 +0x1878 0x40794079 +0x187c 0x00794079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x0100025c // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002915 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3e000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x80794079 +0x1a6c 0x80798079 +0x1a70 0x80798079 +0x1a74 0x40798079 +0x1a78 0x40794079 +0x1a7c 0x00794079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x0100025c //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002915 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp_hp.txt old mode 100755 new mode 100644 index a99bc5d7a3e..00993f82073 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_8197Fmp_hp.txt @@ -1,1887 +1,1887 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x1000001f -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x76433170 -0x830 0x79a0ea0b -0x834 0x042E6486 -0x838 0x87aa7640 -0x83c 0x9797b9b9 -0x840 0x17575fe0 -0x844 0x4BBDFCDE -0x848 0x5cd07f8b -0x84c 0x6CFbF7B5 -0x850 0x28836706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x43642855 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40f550a // all modes use 320M ADC clk -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80025169 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400082c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00400700 -0x90c 0x0B004000 -0x910 0x0000fc00 -0x914 0xD6400404 // ADC_backoff:12.5dB_DFIR_backoff:6.5dB -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4AB0E4E4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x944 0x08000000 -0x948 0x04000000 -0x950 0x02010080 -0x954 0x86510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x98c 0x03440000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00560000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000022d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000053 -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x19800000// RX_WAIT_CCA -0xc60 0x0B800001 -0xc60 0x05800002 -0xc60 0x07800003 -0xc60 0x19800004// TX_CCK_RFON -0xc60 0x0B800005 -0xc60 0x05800006 -0xc60 0x0E800007 -0xc60 0x19800008// TX_CCK_BBON -0xc60 0x0B800009 -0xc60 0x0580000A -0xc60 0x0E80000B -0xc60 0x1980000C// TX_OFDM_RFON -0xc60 0x0B80000D -0xc60 0x0580000E -0xc60 0x0E80000F -0xc60 0x19800010// TX_OFDM_BBON -0xc60 0x0B800011 -0xc60 0x05800012 -0xc60 0x0E800013 -0xc60 0x19800014// TX_TO_RX -0xc60 0x0B800015 -0xc60 0x05800016 -0xc60 0x07800017 -0xc60 0x19800018// TX_TO_TX -0xc60 0x0B800019 -0xc60 0x0580001A -0xc60 0x0E80001B -0xc60 0x1980001C// RX_CCK -0xc60 0x0B80001D -0xc60 0x0580001E -0xc60 0x0780001F -0xc60 0x19800020// RX_OFDM -0xc60 0x0B800021 -0xc60 0x05800022 -0xc60 0x07800023 -0xc60 0x19800024// RX_WAIT_RIFS -0xc60 0x0B800025 -0xc60 0x05800026 -0xc60 0x07800027 -0xc60 0x19800028// RX_TO_RX -0xc60 0x0B800029 -0xc60 0x0580002A -0xc60 0x0780002B -//0xc60 0x1980002C // RSVD -//0xc60 0x0B80002D -//0xc60 0x0580002E -//0xc60 0x0680002F -0xc60 0x19800030 // BT or LTE coexist -0xc60 0x0B800031 -0xc60 0x05800032 -0xc60 0x00800033 -0xc60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0xc60 0x0B800035 -0xc60 0x05800036 -0xc60 0x00800037 -0xc60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0xc60 0x0B800039 -0xc60 0x0580003A -0xc60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0xc60 0x1980003C // PMPD_ANAEN -//0xc60 0x0B80003D -//0xc60 0x0580003E -//0xc60 0x0080803F -0xc94 0x01000001 -0xc98 0x00188000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x77777000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x77700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000053 -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c020c14 -0xe5c 0x00000058 -0xe60 0x19800000// RX_WAIT_CCA -0xe60 0x0B800001 -0xe60 0x05800002 -0xe60 0x07800003 -0xe60 0x19800004// TX_CCK_RFON -0xe60 0x0B800005 -0xe60 0x05800006 -0xe60 0x0E800007 -0xe60 0x19800008// TX_CCK_BBON -0xe60 0x0B800009 -0xe60 0x0580000A -0xe60 0x0E80000B -0xe60 0x1980000C// TX_OFDM_RFON -0xe60 0x0B80000D -0xe60 0x0580000E -0xe60 0x0E80000F -0xe60 0x19800010// TX_OFDM_BBON -0xe60 0x0B800011 -0xe60 0x05800012 -0xe60 0x0E800013 -0xe60 0x19800014// TX_TO_RX -0xe60 0x0B800015 -0xe60 0x05800016 -0xe60 0x07800017 -0xe60 0x19800018// TX_TO_TX -0xe60 0x0B800019 -0xe60 0x0580001A -0xe60 0x0E80001B -0xe60 0x1980001C// RX_CCK -0xe60 0x0B80001D -0xe60 0x0580001E -0xe60 0x0780001F -0xe60 0x19800020// RX_OFDM -0xe60 0x0B800021 -0xe60 0x05800022 -0xe60 0x07800023 -0xe60 0x19800024// RX_WAIT_RIFS -0xe60 0x0B800025 -0xe60 0x05800026 -0xe60 0x07800027 -0xe60 0x19800028// RX_TO_RX -0xe60 0x0B800029 -0xe60 0x0580002A -0xe60 0x0780002B -//0xe60 0x1980002C // RSVD -//0xe60 0x0B80002D -//0xe60 0x0580002E -//0xe60 0x0680002F -0xe60 0x19800030 // BT or LTE coexist -0xe60 0x0B800031 -0xe60 0x05800032 -0xe60 0x00800033 -0xe60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0xe60 0x0B800035 -0xe60 0x05800036 -0xe60 0x00800037 -0xe60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0xe60 0x0B800039 -0xe60 0x0580003A -0xe60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0xe60 0x1980003C // PMPD_ANAEN -//0xe60 0x0B80003D -//0xe60 0x0580003E -//0xe60 0x0080803F -0xe94 0x01000001 -0xe98 0x00188000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x77777000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x77700000 -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000053 -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c020c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x19800000// RX_WAIT_CCA -0x1860 0x0B800001 -0x1860 0x05800002 -0x1860 0x07800003 -0x1860 0x19800004// TX_CCK_RFON -0x1860 0x0B800005 -0x1860 0x05800006 -0x1860 0x0E800007 -0x1860 0x19800008// TX_CCK_BBON -0x1860 0x0B800009 -0x1860 0x0580000A -0x1860 0x0E80000B -0x1860 0x1980000C// TX_OFDM_RFON -0x1860 0x0B80000D -0x1860 0x0580000E -0x1860 0x0E80000F -0x1860 0x19800010// TX_OFDM_BBON -0x1860 0x0B800011 -0x1860 0x05800012 -0x1860 0x0E800013 -0x1860 0x19800014// TX_TO_RX -0x1860 0x0B800015 -0x1860 0x05800016 -0x1860 0x07800017 -0x1860 0x19800018// TX_TO_TX -0x1860 0x0B800019 -0x1860 0x0580001A -0x1860 0x0E80001B -0x1860 0x1980001C// RX_CCK -0x1860 0x0B80001D -0x1860 0x0580001E -0x1860 0x0780001F -0x1860 0x19800020// RX_OFDM -0x1860 0x0B800021 -0x1860 0x05800022 -0x1860 0x07800023 -0x1860 0x19800024// RX_WAIT_RIFS -0x1860 0x0B800025 -0x1860 0x05800026 -0x1860 0x07800027 -0x1860 0x19800028// RX_TO_RX -0x1860 0x0B800029 -0x1860 0x0580002A -0x1860 0x0780002B -//0x1860 0x1980002C // RSVD -//0x1860 0x0B80002D -//0x1860 0x0580002E -//0x1860 0x0680002F -0x1860 0x19800030 // BT or LTE coexist -0x1860 0x0B800031 -0x1860 0x05800032 -0x1860 0x00800033 -0x1860 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0x1860 0x0B800035 -0x1860 0x05800036 -0x1860 0x00800037 -0x1860 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0x1860 0x0B800039 -0x1860 0x0580003A -0x1860 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0x1860 0x1980003C // PMPD_ANAEN -//0x1860 0x0B80003D -//0x1860 0x0580003E -//0x1860 0x0080803F -0x1894 0x01000001 -0x1898 0x00188000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x77777000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x77700000 -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000053 -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c020c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x19800000// RX_WAIT_CCA -0x1a60 0x0B800001 -0x1a60 0x05800002 -0x1a60 0x07800003 -0x1a60 0x19800004// TX_CCK_RFON -0x1a60 0x0B800005 -0x1a60 0x05800006 -0x1a60 0x0E800007 -0x1a60 0x19800008// TX_CCK_BBON -0x1a60 0x0B800009 -0x1a60 0x0580000A -0x1a60 0x0E80000B -0x1a60 0x1980000C// TX_OFDM_RFON -0x1a60 0x0B80000D -0x1a60 0x0580000E -0x1a60 0x0E80000F -0x1a60 0x19800010// TX_OFDM_BBON -0x1a60 0x0B800011 -0x1a60 0x05800012 -0x1a60 0x0E800013 -0x1a60 0x19800014// TX_TO_RX -0x1a60 0x0B800015 -0x1a60 0x05800016 -0x1a60 0x07800017 -0x1a60 0x19800018// TX_TO_TX -0x1a60 0x0B800019 -0x1a60 0x0580001A -0x1a60 0x0E80001B -0x1a60 0x1980001C// RX_CCK -0x1a60 0x0B80001D -0x1a60 0x0580001E -0x1a60 0x0780001F -0x1a60 0x19800020// RX_OFDM -0x1a60 0x0B800021 -0x1a60 0x05800022 -0x1a60 0x07800023 -0x1a60 0x19800024// RX_WAIT_RIFS -0x1a60 0x0B800025 -0x1a60 0x05800026 -0x1a60 0x07800027 -0x1a60 0x19800028// RX_TO_RX -0x1a60 0x0B800029 -0x1a60 0x0580002A -0x1a60 0x0780002B -//0x1a60 0x1980002C // RSVD -//0x1a60 0x0B80002D -//0x1a60 0x0580002E -//0x1a60 0x0680002F -0x1a60 0x19800030 // BT or LTE coexist -0x1a60 0x0B800031 -0x1a60 0x05800032 -0x1a60 0x00800033 -0x1a60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0x1a60 0x0B800035 -0x1a60 0x05800036 -0x1a60 0x00800037 -0x1a60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0x1a60 0x0B800039 -0x1a60 0x0580003A -0x1a60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0x1a60 0x1980003C // PMPD_ANAEN -//0x1a60 0x0B80003D -//0x1a60 0x0580003E -//0x1a60 0x0080803F -0x1a94 0x01000001 -0x1a98 0x00188000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x77777000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x77700000 -//======================= -// PAGE_19 : common setting -//======================= -0x1904 0x00030000 // enable IOQ_iqk_dpk -0x1914 0x00030000 -0x1984 0x03000000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x1998 0x12801000 //CCK CCK 1M -0x1998 0x12801000 //CCK CCK 1M -0x1998 0x12801001 //CCK CCK 2M -0x1998 0x12801002 //CCK CCK 5.5M -0x1998 0x12801003 //CCK CCK 11M -0x1998 0x12801004 //OFDM OFDM 6M -0x1998 0x12801005 //OFDM OFDM 9M -0x1998 0x12801006 //OFDM OFDM 12M -0x1998 0x12801007 //OFDM OFDM 18M -0x1998 0x12801008 //OFDM OFDM 24M -0x1998 0x12801009 //OFDM OFDM 36M -0x1998 0x1280100a //OFDM OFDM 48M -0x1998 0x1280100b //OFDM OFDM 54M -0x1998 0x1280100c //HT nss1 MCS0 -0x1998 0x1280100d //HT nss1 MCS1 -0x1998 0x1280100e //HT nss1 MCS2 -0x1998 0x1280100f //HT nss1 MCS3 -0x1998 0x12801010 //HT nss1 MCS4 -0x1998 0x12801011 //HT nss1 MCS5 -0x1998 0x12801012 //HT nss1 MCS6 -0x1998 0x12801013 //HT nss1 MCS7 -0x1998 0x12801014 //HT nss2 MCS8 -0x1998 0x12801015 //HT nss2 MCS9 -0x1998 0x12801016 //HT nss2 MCS10 -0x1998 0x12801017 //HT nss2 MCS11 -0x1998 0x12801018 //HT nss2 MCS12 -0x1998 0x12801019 //HT nss2 MCS13 -0x1998 0x1280101a //HT nss2 MCS14 -0x1998 0x1280101b //HT nss2 MCS15 -0x1998 0x1280101c //HT nss3 MCS16 -0x1998 0x1280101d //HT nss3 MCS17 -0x1998 0x1280101e //HT nss3 MCS18 -0x1998 0x1280101f //HT nss3 MCS19 -0x1998 0x12801020 //HT nss3 MCS20 -0x1998 0x12801021 //HT nss3 MCS21 -0x1998 0x12801022 //HT nss3 MCS22 -0x1998 0x12801023 //HT nss3 MCS23 -0x1998 0x1280102c //VHT nss1 MCS0 -0x1998 0x1280102d //VHT nss1 MCS1 -0x1998 0x1280102e //VHT nss1 MCS2 -0x1998 0x1280102f //VHT nss1 MCS3 -0x1998 0x12801030 //VHT nss1 MCS4 -0x1998 0x12801031 //VHT nss1 MCS5 -0x1998 0x12801032 //VHT nss1 MCS6 -0x1998 0x12801033 //VHT nss1 MCS7 -0x1998 0x12801034 //VHT nss1 MCS8 -0x1998 0x12801035 //VHT nss1 MCS9 -0x1998 0x12801036 //VHT nss2 MCS0 -0x1998 0x12801037 //VHT nss2 MCS1 -0x1998 0x12801038 //VHT nss2 MCS2 -0x1998 0x12801039 //VHT nss2 MCS3 -0x1998 0x1280103a //VHT nss2 MCS4 -0x1998 0x1280103b //VHT nss2 MCS5 -0x1998 0x1280103c //VHT nss2 MCS6 -0x1998 0x1280103d //VHT nss2 MCS7 -0x1998 0x1280103e //VHT nss2 MCS8 -0x1998 0x1280103f //VHT nss2 MCS9 -0x1998 0x12801040 //VHT nss3 MCS0 -0x1998 0x12801041 //VHT nss3 MCS1 -0x1998 0x12801042 //VHT nss3 MCS2 -0x1998 0x12801043 //VHT nss3 MCS3 -0x1998 0x12801044 //VHT nss3 MCS4 -0x1998 0x12801045 //VHT nss3 MCS5 -0x1998 0x12801046 //VHT nss3 MCS6 -0x1998 0x12801047 //VHT nss3 MCS7 -0x1998 0x12801048 //VHT nss3 MCS8 -0x1998 0x12801049 //VHT nss3 MCS9 -0x1998 0x12801100 //CCK CCK 1M -0x1998 0x12801101 //CCK CCK 2M -0x1998 0x12801102 //CCK CCK 5.5M -0x1998 0x12801103 //CCK CCK 11M -0x1998 0x12801104 //OFDM OFDM 6M -0x1998 0x12801105 //OFDM OFDM 9M -0x1998 0x12801106 //OFDM OFDM 12M -0x1998 0x12801107 //OFDM OFDM 18M -0x1998 0x12801108 //OFDM OFDM 24M -0x1998 0x12801109 //OFDM OFDM 36M -0x1998 0x1280110a //OFDM OFDM 48M -0x1998 0x1280110b //OFDM OFDM 54M -0x1998 0x1280110c //HT nss1 MCS0 -0x1998 0x1280110d //HT nss1 MCS1 -0x1998 0x1280110e //HT nss1 MCS2 -0x1998 0x1280110f //HT nss1 MCS3 -0x1998 0x12801110 //HT nss1 MCS4 -0x1998 0x12801111 //HT nss1 MCS5 -0x1998 0x12801112 //HT nss1 MCS6 -0x1998 0x12801113 //HT nss1 MCS7 -0x1998 0x12801114 //HT nss2 MCS8 -0x1998 0x12801115 //HT nss2 MCS9 -0x1998 0x12801116 //HT nss2 MCS10 -0x1998 0x12801117 //HT nss2 MCS11 -0x1998 0x12801118 //HT nss2 MCS12 -0x1998 0x12801119 //HT nss2 MCS13 -0x1998 0x1280111a //HT nss2 MCS14 -0x1998 0x1280111b //HT nss2 MCS15 -0x1998 0x1280111c //HT nss3 MCS16 -0x1998 0x1280111d //HT nss3 MCS17 -0x1998 0x1280111e //HT nss3 MCS18 -0x1998 0x1280111f //HT nss3 MCS19 -0x1998 0x12801120 //HT nss3 MCS20 -0x1998 0x12801121 //HT nss3 MCS21 -0x1998 0x12801122 //HT nss3 MCS22 -0x1998 0x12801123 //HT nss3 MCS23 -0x1998 0x1280112c //VHT nss1 MCS0 -0x1998 0x1280112d //VHT nss1 MCS1 -0x1998 0x1280112e //VHT nss1 MCS2 -0x1998 0x1280112f //VHT nss1 MCS3 -0x1998 0x12801130 //VHT nss1 MCS4 -0x1998 0x12801131 //VHT nss1 MCS5 -0x1998 0x12801132 //VHT nss1 MCS6 -0x1998 0x12801133 //VHT nss1 MCS7 -0x1998 0x12801134 //VHT nss1 MCS8 -0x1998 0x12801135 //VHT nss1 MCS9 -0x1998 0x12801136 //VHT nss2 MCS0 -0x1998 0x12801137 //VHT nss2 MCS1 -0x1998 0x12801138 //VHT nss2 MCS2 -0x1998 0x12801139 //VHT nss2 MCS3 -0x1998 0x1280113a //VHT nss2 MCS4 -0x1998 0x1280113b //VHT nss2 MCS5 -0x1998 0x1280113c //VHT nss2 MCS6 -0x1998 0x1280113d //VHT nss2 MCS7 -0x1998 0x1280113e //VHT nss2 MCS8 -0x1998 0x1280113f //VHT nss2 MCS9 -0x1998 0x12801140 //VHT nss3 MCS0 -0x1998 0x12801141 //VHT nss3 MCS1 -0x1998 0x12801142 //VHT nss3 MCS2 -0x1998 0x12801143 //VHT nss3 MCS3 -0x1998 0x12801144 //VHT nss3 MCS4 -0x1998 0x12801145 //VHT nss3 MCS5 -0x1998 0x12801146 //VHT nss3 MCS6 -0x1998 0x12801147 //VHT nss3 MCS7 -0x1998 0x12801148 //VHT nss3 MCS8 -0x1998 0x12801149 //VHT nss3 MCS9 -0x1998 0x12801200 //CCK CCK 1M -0x1998 0x12801201 //CCK CCK 2M -0x1998 0x12801202 //CCK CCK 5.5M -0x1998 0x12801203 //CCK CCK 11M -0x1998 0x12801204 //OFDM OFDM 6M -0x1998 0x12801205 //OFDM OFDM 9M -0x1998 0x12801206 //OFDM OFDM 12M -0x1998 0x12801207 //OFDM OFDM 18M -0x1998 0x12801208 //OFDM OFDM 24M -0x1998 0x12801209 //OFDM OFDM 36M -0x1998 0x1280120a //OFDM OFDM 48M -0x1998 0x1280120b //OFDM OFDM 54M -0x1998 0x1280120c //HT nss1 MCS0 -0x1998 0x1280120d //HT nss1 MCS1 -0x1998 0x1280120e //HT nss1 MCS2 -0x1998 0x1280120f //HT nss1 MCS3 -0x1998 0x12801210 //HT nss1 MCS4 -0x1998 0x12801211 //HT nss1 MCS5 -0x1998 0x12801212 //HT nss1 MCS6 -0x1998 0x12801213 //HT nss1 MCS7 -0x1998 0x12801214 //HT nss2 MCS8 -0x1998 0x12801215 //HT nss2 MCS9 -0x1998 0x12801216 //HT nss2 MCS10 -0x1998 0x12801217 //HT nss2 MCS11 -0x1998 0x12801218 //HT nss2 MCS12 -0x1998 0x12801219 //HT nss2 MCS13 -0x1998 0x1280121a //HT nss2 MCS14 -0x1998 0x1280121b //HT nss2 MCS15 -0x1998 0x1280121c //HT nss3 MCS16 -0x1998 0x1280121d //HT nss3 MCS17 -0x1998 0x1280121e //HT nss3 MCS18 -0x1998 0x1280121f //HT nss3 MCS19 -0x1998 0x12801220 //HT nss3 MCS20 -0x1998 0x12801221 //HT nss3 MCS21 -0x1998 0x12801222 //HT nss3 MCS22 -0x1998 0x12801223 //HT nss3 MCS23 -0x1998 0x1280122c //VHT nss1 MCS0 -0x1998 0x1280122d //VHT nss1 MCS1 -0x1998 0x1280122e //VHT nss1 MCS2 -0x1998 0x1280122f //VHT nss1 MCS3 -0x1998 0x12801230 //VHT nss1 MCS4 -0x1998 0x12801231 //VHT nss1 MCS5 -0x1998 0x12801232 //VHT nss1 MCS6 -0x1998 0x12801233 //VHT nss1 MCS7 -0x1998 0x12801234 //VHT nss1 MCS8 -0x1998 0x12801235 //VHT nss1 MCS9 -0x1998 0x12801236 //VHT nss2 MCS0 -0x1998 0x12801237 //VHT nss2 MCS1 -0x1998 0x12801238 //VHT nss2 MCS2 -0x1998 0x12801239 //VHT nss2 MCS3 -0x1998 0x1280123a //VHT nss2 MCS4 -0x1998 0x1280123b //VHT nss2 MCS5 -0x1998 0x1280123c //VHT nss2 MCS6 -0x1998 0x1280123d //VHT nss2 MCS7 -0x1998 0x1280123e //VHT nss2 MCS8 -0x1998 0x1280123f //VHT nss2 MCS9 -0x1998 0x12801240 //VHT nss3 MCS0 -0x1998 0x12801241 //VHT nss3 MCS1 -0x1998 0x12801242 //VHT nss3 MCS2 -0x1998 0x12801243 //VHT nss3 MCS3 -0x1998 0x12801244 //VHT nss3 MCS4 -0x1998 0x12801245 //VHT nss3 MCS5 -0x1998 0x12801246 //VHT nss3 MCS6 -0x1998 0x12801247 //VHT nss3 MCS7 -0x1998 0x12801248 //VHT nss3 MCS8 -0x1998 0x12801249 //VHT nss3 MCS9 -0x1998 0x12801300 //CCK CCK 1M -0x1998 0x12801301 //CCK CCK 2M -0x1998 0x12801302 //CCK CCK 5.5M -0x1998 0x12801303 //CCK CCK 11M -0x1998 0x12801304 //OFDM OFDM 6M -0x1998 0x12801305 //OFDM OFDM 9M -0x1998 0x12801306 //OFDM OFDM 12M -0x1998 0x12801307 //OFDM OFDM 18M -0x1998 0x12801308 //OFDM OFDM 24M -0x1998 0x12801309 //OFDM OFDM 36M -0x1998 0x1280130a //OFDM OFDM 48M -0x1998 0x1280130b //OFDM OFDM 54M -0x1998 0x1280130c //HT nss1 MCS0 -0x1998 0x1280130d //HT nss1 MCS1 -0x1998 0x1280130e //HT nss1 MCS2 -0x1998 0x1280130f //HT nss1 MCS3 -0x1998 0x12801310 //HT nss1 MCS4 -0x1998 0x12801311 //HT nss1 MCS5 -0x1998 0x12801312 //HT nss1 MCS6 -0x1998 0x12801313 //HT nss1 MCS7 -0x1998 0x12801314 //HT nss2 MCS8 -0x1998 0x12801315 //HT nss2 MCS9 -0x1998 0x12801316 //HT nss2 MCS10 -0x1998 0x12801317 //HT nss2 MCS11 -0x1998 0x12801318 //HT nss2 MCS12 -0x1998 0x12801319 //HT nss2 MCS13 -0x1998 0x1280131a //HT nss2 MCS14 -0x1998 0x1280131b //HT nss2 MCS15 -0x1998 0x1280131c //HT nss3 MCS16 -0x1998 0x1280131d //HT nss3 MCS17 -0x1998 0x1280131e //HT nss3 MCS18 -0x1998 0x1280131f //HT nss3 MCS19 -0x1998 0x12801320 //HT nss3 MCS20 -0x1998 0x12801321 //HT nss3 MCS21 -0x1998 0x12801322 //HT nss3 MCS22 -0x1998 0x12801323 //HT nss3 MCS23 -0x1998 0x1280132c //VHT nss1 MCS0 -0x1998 0x1280132d //VHT nss1 MCS1 -0x1998 0x1280132e //VHT nss1 MCS2 -0x1998 0x1280132f //VHT nss1 MCS3 -0x1998 0x12801330 //VHT nss1 MCS4 -0x1998 0x12801331 //VHT nss1 MCS5 -0x1998 0x12801332 //VHT nss1 MCS6 -0x1998 0x12801333 //VHT nss1 MCS7 -0x1998 0x12801334 //VHT nss1 MCS8 -0x1998 0x12801335 //VHT nss1 MCS9 -0x1998 0x12801336 //VHT nss2 MCS0 -0x1998 0x12801337 //VHT nss2 MCS1 -0x1998 0x12801338 //VHT nss2 MCS2 -0x1998 0x12801339 //VHT nss2 MCS3 -0x1998 0x1280133a //VHT nss2 MCS4 -0x1998 0x1280133b //VHT nss2 MCS5 -0x1998 0x1280133c //VHT nss2 MCS6 -0x1998 0x1280133d //VHT nss2 MCS7 -0x1998 0x1280133e //VHT nss2 MCS8 -0x1998 0x1280133f //VHT nss2 MCS9 -0x1998 0x12801340 //VHT nss3 MCS0 -0x1998 0x12801341 //VHT nss3 MCS1 -0x1998 0x12801342 //VHT nss3 MCS2 -0x1998 0x12801343 //VHT nss3 MCS3 -0x1998 0x12801344 //VHT nss3 MCS4 -0x1998 0x12801345 //VHT nss3 MCS5 -0x1998 0x12801346 //VHT nss3 MCS6 -0x1998 0x12801347 //VHT nss3 MCS7 -0x1998 0x12801348 //VHT nss3 MCS8 -0x1998 0x12801349 //VHT nss3 MCS9 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// ADC clk lock procedure -//======================= -0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) -// 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 -// 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line -// 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut - -// power_off/clk_off @ anapar_state=idle mode -0xc60 0x15808002 -0xc60 0x01808003 -0xe60 0x15808002 -0xe60 0x01808003 -0x1860 0x15808002 -0x1860 0x01808003 -0x1a60 0x15808002 -0x1a60 0x01808003 - -0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) -0xc5c 0x00080058 // [19] =1 to turn off ADC -0xe5c 0x00080058 // [19] =1 to turn off ADC -0x185c 0x00080058 // [19] =1 to turn off ADC -0x1a5c 0x00080058 // [19] =1 to turn off ADC - -// power_on/clk_off @ anapar_state=sleep mode -0xc60 0x15808036 -0xc60 0x0F808037 -0xe60 0x15808036 -0xe60 0x0F808037 -0x1860 0x15808036 -0x1860 0x0F808037 -0x1a60 0x15808036 -0x1a60 0x0F808037 - -0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) -0xc5c 0x0D000058 // [19] =0 to turn on ADC -0xe5c 0x0D000058 // [19] =0 to turn on ADC -0x185c 0x0D000058 // [19] =0 to turn on ADC -0x1a5c 0x0D000058 // [19] =0 to turn on ADC - -// power_on/clk_on @ anapar_state=idle mode -0xc60 0x05808002 -0xc60 0x0e808003 -0xe60 0x05808002 -0xe60 0x0e808003 -0x1860 0x05808002 -0x1860 0x0e808003 -0x1a60 0x05808002 -0x1a60 0x0e808003 -// recover original setting @ anapar_state=sleep mode -0xc60 0x05808036 -0xc60 0x0e808037 -0xe60 0x05808036 -0xe60 0x0e808037 -0x1860 0x05808036 -0x1860 0x0e808037 -0x1a60 0x05808036 -0x1a60 0x0e808037 - -0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) -0xb00 0xe3100000 //return true MAC - -//======================= -// PAGE_1c -//======================= -0x1c38 0x00000002 // enable IQK clk -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe24628d2 -0x1b10 0x88010d46 -0x1b14 0x00000000 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b00 0xf8015000 -0x1b00 0xf8057000 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b00 0xf8015002 -0x1b00 0xf8057002 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b00 0xf8015004 -0x1b00 0xf8057004 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b00 0xf8015006 -0x1b00 0xf8057006 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x09060005 -0x1b80 0x09060007 -0x1b80 0x0ffe0015 -0x1b80 0x0ffe0017 -0x1b80 0x00240025 -0x1b80 0x00240027 -0x1b80 0x00040035 -0x1b80 0x00040037 -0x1b80 0x05c00045 -0x1b80 0x05c00047 -0x1b80 0x00070055 -0x1b80 0x00070057 -0x1b80 0x64000065 -0x1b80 0x64000067 -0x1b80 0x00020075 -0x1b80 0x00020077 -0x1b80 0x00080085 -0x1b80 0x00080087 -0x1b80 0x80000095 -0x1b80 0x80000097 -0x1b80 0x090100a5 -0x1b80 0x090100a7 -0x1b80 0x0f0200b5 -0x1b80 0x0f0200b7 -0x1b80 0x002400c5 -0x1b80 0x002400c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x05c000e5 -0x1b80 0x05c000e7 -0x1b80 0x000700f5 -0x1b80 0x000700f7 -0x1b80 0x64020105 -0x1b80 0x64020107 -0x1b80 0x00020115 -0x1b80 0x00020117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4a000135 -0x1b80 0x4a000137 -0x1b80 0x4b040145 -0x1b80 0x4b040147 -0x1b80 0x85030155 -0x1b80 0x85030157 -0x1b80 0x40010165 -0x1b80 0x40010167 -0x1b80 0xe0290175 -0x1b80 0xe0290177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x4b050195 -0x1b80 0x4b050197 -0x1b80 0x860301a5 -0x1b80 0x860301a7 -0x1b80 0x400301b5 -0x1b80 0x400301b7 -0x1b80 0xe02901c5 -0x1b80 0xe02901c7 -0x1b80 0x000401d5 -0x1b80 0x000401d7 -0x1b80 0x4b0601e5 -0x1b80 0x4b0601e7 -0x1b80 0x870301f5 -0x1b80 0x870301f7 -0x1b80 0x40050205 -0x1b80 0x40050207 -0x1b80 0xe0290215 -0x1b80 0xe0290217 -0x1b80 0x00040225 -0x1b80 0x00040227 -0x1b80 0x4b070235 -0x1b80 0x4b070237 -0x1b80 0x88030245 -0x1b80 0x88030247 -0x1b80 0x40070255 -0x1b80 0x40070257 -0x1b80 0xe0290265 -0x1b80 0xe0290267 -0x1b80 0x4b000275 -0x1b80 0x4b000277 -0x1b80 0x30000285 -0x1b80 0x30000287 -0x1b80 0xa40a0295 -0x1b80 0xa40a0297 -0x1b80 0xe17602a5 -0x1b80 0xe17602a7 -0x1b80 0xf00e02b5 -0x1b80 0xf00e02b7 -0x1b80 0xf10e02c5 -0x1b80 0xf10e02c7 -0x1b80 0xf20e02d5 -0x1b80 0xf20e02d7 -0x1b80 0xf30e02e5 -0x1b80 0xf30e02e7 -0x1b80 0xf40d02f5 -0x1b80 0xf40d02f7 -0x1b80 0xf50c0305 -0x1b80 0xf50c0307 -0x1b80 0xf60c0315 -0x1b80 0xf60c0317 -0x1b80 0xf70b0325 -0x1b80 0xf70b0327 -0x1b80 0xf8060335 -0x1b80 0xf8060337 -0x1b80 0xf9060345 -0x1b80 0xf9060347 -0x1b80 0xfa090355 -0x1b80 0xfa090357 -0x1b80 0xfe090365 -0x1b80 0xfe090367 -0x1b80 0xff090375 -0x1b80 0xff090377 -0x1b80 0x00010385 -0x1b80 0x00010387 -0x1b80 0x30410395 -0x1b80 0x30410397 -0x1b80 0x305403a5 -0x1b80 0x305403a7 -0x1b80 0x306003b5 -0x1b80 0x306003b7 -0x1b80 0x305403c5 -0x1b80 0x305403c7 -0x1b80 0x306d03d5 -0x1b80 0x306d03d7 -0x1b80 0x306703e5 -0x1b80 0x306703e7 -0x1b80 0x31be03f5 -0x1b80 0x31be03f7 -0x1b80 0x31af0405 -0x1b80 0x31af0407 -0x1b80 0xe1110415 -0x1b80 0xe1110417 -0x1b80 0x4d040425 -0x1b80 0x4d040427 -0x1b80 0x20800435 -0x1b80 0x20800437 -0x1b80 0x00000445 -0x1b80 0x00000447 -0x1b80 0x4d000455 -0x1b80 0x4d000457 -0x1b80 0x55070465 -0x1b80 0x55070467 -0x1b80 0xe1110475 -0x1b80 0xe1110477 -0x1b80 0x4d040485 -0x1b80 0x4d040487 -0x1b80 0x20800495 -0x1b80 0x20800497 -0x1b80 0x840004a5 -0x1b80 0x840004a7 -0x1b80 0x4d0004b5 -0x1b80 0x4d0004b7 -0x1b80 0x550f04c5 -0x1b80 0x550f04c7 -0x1b80 0xe11104d5 -0x1b80 0xe11104d7 -0x1b80 0x4f0204e5 -0x1b80 0x4f0204e7 -0x1b80 0x4e0004f5 -0x1b80 0x4e0004f7 -0x1b80 0x53020505 -0x1b80 0x53020507 -0x1b80 0x52010515 -0x1b80 0x52010517 -0x1b80 0xe1150525 -0x1b80 0xe1150527 -0x1b80 0x00010535 -0x1b80 0x00010537 -0x1b80 0x5c720545 -0x1b80 0x5c720547 -0x1b80 0xe1200555 -0x1b80 0xe1200557 -0x1b80 0x54e50565 -0x1b80 0x54e50567 -0x1b80 0x54bf0575 -0x1b80 0x54bf0577 -0x1b80 0x54c50585 -0x1b80 0x54c50587 -0x1b80 0x54be0595 -0x1b80 0x54be0597 -0x1b80 0x54df05a5 -0x1b80 0x54df05a7 -0x1b80 0x0ba605b5 -0x1b80 0x0ba605b7 -0x1b80 0xf31a05c5 -0x1b80 0xf31a05c7 -0x1b80 0xf42f05d5 -0x1b80 0xf42f05d7 -0x1b80 0xf54c05e5 -0x1b80 0xf54c05e7 -0x1b80 0x000105f5 -0x1b80 0x000105f7 -0x1b80 0x62060605 -0x1b80 0x62060607 -0x1b80 0x60060615 -0x1b80 0x60060617 -0x1b80 0xe1950625 -0x1b80 0xe1950627 -0x1b80 0x0c000635 -0x1b80 0x0c000637 -0x1b80 0x5c720645 -0x1b80 0x5c720647 -0x1b80 0xe1200655 -0x1b80 0xe1200657 -0x1b80 0x5cf10665 -0x1b80 0x5cf10667 -0x1b80 0x0ac60675 -0x1b80 0x0ac60677 -0x1b80 0xe1a20685 -0x1b80 0xe1a20687 -0x1b80 0x0c010695 -0x1b80 0x0c010697 -0x1b80 0xe14706a5 -0x1b80 0xe14706a7 -0x1b80 0x54e506b5 -0x1b80 0x54e506b7 -0x1b80 0x000106c5 -0x1b80 0x000106c7 -0x1b80 0x732006d5 -0x1b80 0x732006d7 -0x1b80 0x720006e5 -0x1b80 0x720006e7 -0x1b80 0x710006f5 -0x1b80 0x710006f7 -0x1b80 0x5ce20705 -0x1b80 0x5ce20707 -0x1b80 0x54be0715 -0x1b80 0x54be0717 -0x1b80 0x62060725 -0x1b80 0x62060727 -0x1b80 0x60060735 -0x1b80 0x60060737 -0x1b80 0xe1950745 -0x1b80 0xe1950747 -0x1b80 0x30aa0755 -0x1b80 0x30aa0757 -0x1b80 0x56010765 -0x1b80 0x56010767 -0x1b80 0x5ce20775 -0x1b80 0x5ce20777 -0x1b80 0x0ae10785 -0x1b80 0x0ae10787 -0x1b80 0x630d0795 -0x1b80 0x630d0797 -0x1b80 0xe12d07a5 -0x1b80 0xe12d07a7 -0x1b80 0x002607b5 -0x1b80 0x002607b7 -0x1b80 0xe15c07c5 -0x1b80 0xe15c07c7 -0x1b80 0x000207d5 -0x1b80 0x000207d7 -0x1b80 0x630707e5 -0x1b80 0x630707e7 -0x1b80 0xe12d07f5 -0x1b80 0xe12d07f7 -0x1b80 0xe15c0805 -0x1b80 0xe15c0807 -0x1b80 0x56000815 -0x1b80 0x56000817 -0x1b80 0x5cf20825 -0x1b80 0x5cf20827 -0x1b80 0x0af10835 -0x1b80 0x0af10837 -0x1b80 0x07140845 -0x1b80 0x07140847 -0x1b80 0x07140855 -0x1b80 0x07140857 -0x1b80 0x630d0865 -0x1b80 0x630d0867 -0x1b80 0xe12d0875 -0x1b80 0xe12d0877 -0x1b80 0x00260885 -0x1b80 0x00260887 -0x1b80 0xe15c0895 -0x1b80 0xe15c0897 -0x1b80 0x000208a5 -0x1b80 0x000208a7 -0x1b80 0x30d308b5 -0x1b80 0x30d308b7 -0x1b80 0x560108c5 -0x1b80 0x560108c7 -0x1b80 0x5ce208d5 -0x1b80 0x5ce208d7 -0x1b80 0x0ae108e5 -0x1b80 0x0ae108e7 -0x1b80 0x631d08f5 -0x1b80 0x631d08f7 -0x1b80 0xe12d0905 -0x1b80 0xe12d0907 -0x1b80 0x00240915 -0x1b80 0x00240917 -0x1b80 0xe15c0925 -0x1b80 0xe15c0927 -0x1b80 0x00020935 -0x1b80 0x00020937 -0x1b80 0x63170945 -0x1b80 0x63170947 -0x1b80 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0xe77f19b7 -0x1b80 0x232f19c5 -0x1b80 0x232f19c7 -0x1b80 0xefbf19d5 -0x1b80 0xefbf19d7 -0x1b80 0x2ef019e5 -0x1b80 0x2ef019e7 -0x1b80 0x000219f5 -0x1b80 0x000219f7 -0x1b80 0x4d001a05 -0x1b80 0x4d001a07 -0x1b80 0x00011a15 -0x1b80 0x00011a17 -0x1b80 0x4d041a25 -0x1b80 0x4d041a27 -0x1b80 0x2ef81a35 -0x1b80 0x2ef81a37 -0x1b80 0x00021a45 -0x1b80 0x00021a47 -0x1b80 0x23031a55 -0x1b80 0x23031a57 -0x1b80 0x00001a65 -0x1b80 0x00001a67 -0x1b80 0x23131a75 -0x1b80 0x23131a77 -0x1b80 0xe77f1a85 -0x1b80 0xe77f1a87 -0x1b80 0x232f1a95 -0x1b80 0x232f1a97 -0x1b80 0xe79f1aa5 -0x1b80 0xe79f1aa7 -0x1b80 0x2ef01ab5 -0x1b80 0x2ef01ab7 -0x1b80 0x00021ac5 -0x1b80 0x00021ac7 -0x1b80 0x4d001ad5 -0x1b80 0x4d001ad7 -0x1b80 0x00011ae5 -0x1b80 0x00011ae7 -0x1b80 0x00041af5 -0x1b80 0x00041af7 -0x1b80 0x6bc01b05 -0x1b80 0x6bc01b07 -0x1b80 0x4d041b15 -0x1b80 0x4d041b17 -0x1b80 0x68241b25 -0x1b80 0x68241b27 -0x1b80 0x66061b35 -0x1b80 0x66061b37 -0x1b80 0x650c1b45 -0x1b80 0x650c1b47 -0x1b80 0x64471b55 -0x1b80 0x64471b57 -0x1b80 0x23411b65 -0x1b80 0x23411b67 -0x1b80 0x106c1b75 -0x1b80 0x106c1b77 -0x1b80 0x23411b85 -0x1b80 0x23411b87 -0x1b80 0x60e11b95 -0x1b80 0x60e11b97 -0x1b80 0x23411ba5 -0x1b80 0x23411ba7 -0x1b80 0x70e11bb5 -0x1b80 0x70e11bb7 -0x1b80 0x4d001bc5 -0x1b80 0x4d001bc7 -0x1b80 0x00011bd5 -0x1b80 0x00011bd7 -0x1b80 0x00041be5 -0x1b80 0x00041be7 -0x1b80 0x6b401bf5 -0x1b80 0x6b401bf7 -0x1b80 0x4d041c05 -0x1b80 0x4d041c07 -0x1b80 0x68481c15 -0x1b80 0x68481c17 -0x1b80 0x66061c25 -0x1b80 0x66061c27 -0x1b80 0x65181c35 -0x1b80 0x65181c37 -0x1b80 0x64471c45 -0x1b80 0x64471c47 -0x1b80 0x23411c55 -0x1b80 0x23411c57 -0x1b80 0x11e81c65 -0x1b80 0x11e81c67 -0x1b80 0x23411c75 -0x1b80 0x23411c77 -0x1b80 0x61e11c85 -0x1b80 0x61e11c87 -0x1b80 0x23411c95 -0x1b80 0x23411c97 -0x1b80 0x70611ca5 -0x1b80 0x70611ca7 -0x1b80 0x4d001cb5 -0x1b80 0x4d001cb7 -0x1b80 0x00011cc5 -0x1b80 0x00011cc7 -0x1b80 0x00000006 -0x1b80 0x00000002 +//RL6302_MAC_PHY_Parameter_v018_20140708 +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x1000001f +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x76433170 +0x830 0x79a0ea0b +0x834 0x042E6486 +0x838 0x87aa7640 +0x83c 0x9797b9b9 +0x840 0x17575fe0 +0x844 0x4BBDFCDE +0x848 0x5cd07f8b +0x84c 0x6CFbF7B5 +0x850 0x28836706 +0x854 0x0001520c +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x43642855 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40f550a // all modes use 320M ADC clk +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80025169 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400082c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00400700 +0x90c 0x0B004000 +0x910 0x0000fc00 +0x914 0xD6400404 // ADC_backoff:12.5dB_DFIR_backoff:6.5dB +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4AB0E4E4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x944 0x08000000 +0x948 0x04000000 +0x950 0x02010080 +0x954 0x86510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x98c 0x03440000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00560000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000022d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000053 +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x19800000// RX_WAIT_CCA +0xc60 0x0B800001 +0xc60 0x05800002 +0xc60 0x07800003 +0xc60 0x19800004// TX_CCK_RFON +0xc60 0x0B800005 +0xc60 0x05800006 +0xc60 0x0E800007 +0xc60 0x19800008// TX_CCK_BBON +0xc60 0x0B800009 +0xc60 0x0580000A +0xc60 0x0E80000B +0xc60 0x1980000C// TX_OFDM_RFON +0xc60 0x0B80000D +0xc60 0x0580000E +0xc60 0x0E80000F +0xc60 0x19800010// TX_OFDM_BBON +0xc60 0x0B800011 +0xc60 0x05800012 +0xc60 0x0E800013 +0xc60 0x19800014// TX_TO_RX +0xc60 0x0B800015 +0xc60 0x05800016 +0xc60 0x07800017 +0xc60 0x19800018// TX_TO_TX +0xc60 0x0B800019 +0xc60 0x0580001A +0xc60 0x0E80001B +0xc60 0x1980001C// RX_CCK +0xc60 0x0B80001D +0xc60 0x0580001E +0xc60 0x0780001F +0xc60 0x19800020// RX_OFDM +0xc60 0x0B800021 +0xc60 0x05800022 +0xc60 0x07800023 +0xc60 0x19800024// RX_WAIT_RIFS +0xc60 0x0B800025 +0xc60 0x05800026 +0xc60 0x07800027 +0xc60 0x19800028// RX_TO_RX +0xc60 0x0B800029 +0xc60 0x0580002A +0xc60 0x0780002B +//0xc60 0x1980002C // RSVD +//0xc60 0x0B80002D +//0xc60 0x0580002E +//0xc60 0x0680002F +0xc60 0x19800030 // BT or LTE coexist +0xc60 0x0B800031 +0xc60 0x05800032 +0xc60 0x00800033 +0xc60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0xc60 0x0B800035 +0xc60 0x05800036 +0xc60 0x00800037 +0xc60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0xc60 0x0B800039 +0xc60 0x0580003A +0xc60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0xc60 0x1980003C // PMPD_ANAEN +//0xc60 0x0B80003D +//0xc60 0x0580003E +//0xc60 0x0080803F +0xc94 0x01000001 +0xc98 0x00188000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x77777000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x77700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000053 +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c020c14 +0xe5c 0x00000058 +0xe60 0x19800000// RX_WAIT_CCA +0xe60 0x0B800001 +0xe60 0x05800002 +0xe60 0x07800003 +0xe60 0x19800004// TX_CCK_RFON +0xe60 0x0B800005 +0xe60 0x05800006 +0xe60 0x0E800007 +0xe60 0x19800008// TX_CCK_BBON +0xe60 0x0B800009 +0xe60 0x0580000A +0xe60 0x0E80000B +0xe60 0x1980000C// TX_OFDM_RFON +0xe60 0x0B80000D +0xe60 0x0580000E +0xe60 0x0E80000F +0xe60 0x19800010// TX_OFDM_BBON +0xe60 0x0B800011 +0xe60 0x05800012 +0xe60 0x0E800013 +0xe60 0x19800014// TX_TO_RX +0xe60 0x0B800015 +0xe60 0x05800016 +0xe60 0x07800017 +0xe60 0x19800018// TX_TO_TX +0xe60 0x0B800019 +0xe60 0x0580001A +0xe60 0x0E80001B +0xe60 0x1980001C// RX_CCK +0xe60 0x0B80001D +0xe60 0x0580001E +0xe60 0x0780001F +0xe60 0x19800020// RX_OFDM +0xe60 0x0B800021 +0xe60 0x05800022 +0xe60 0x07800023 +0xe60 0x19800024// RX_WAIT_RIFS +0xe60 0x0B800025 +0xe60 0x05800026 +0xe60 0x07800027 +0xe60 0x19800028// RX_TO_RX +0xe60 0x0B800029 +0xe60 0x0580002A +0xe60 0x0780002B +//0xe60 0x1980002C // RSVD +//0xe60 0x0B80002D +//0xe60 0x0580002E +//0xe60 0x0680002F +0xe60 0x19800030 // BT or LTE coexist +0xe60 0x0B800031 +0xe60 0x05800032 +0xe60 0x00800033 +0xe60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0xe60 0x0B800035 +0xe60 0x05800036 +0xe60 0x00800037 +0xe60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0xe60 0x0B800039 +0xe60 0x0580003A +0xe60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0xe60 0x1980003C // PMPD_ANAEN +//0xe60 0x0B80003D +//0xe60 0x0580003E +//0xe60 0x0080803F +0xe94 0x01000001 +0xe98 0x00188000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x77777000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x77700000 +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000053 +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c020c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x19800000// RX_WAIT_CCA +0x1860 0x0B800001 +0x1860 0x05800002 +0x1860 0x07800003 +0x1860 0x19800004// TX_CCK_RFON +0x1860 0x0B800005 +0x1860 0x05800006 +0x1860 0x0E800007 +0x1860 0x19800008// TX_CCK_BBON +0x1860 0x0B800009 +0x1860 0x0580000A +0x1860 0x0E80000B +0x1860 0x1980000C// TX_OFDM_RFON +0x1860 0x0B80000D +0x1860 0x0580000E +0x1860 0x0E80000F +0x1860 0x19800010// TX_OFDM_BBON +0x1860 0x0B800011 +0x1860 0x05800012 +0x1860 0x0E800013 +0x1860 0x19800014// TX_TO_RX +0x1860 0x0B800015 +0x1860 0x05800016 +0x1860 0x07800017 +0x1860 0x19800018// TX_TO_TX +0x1860 0x0B800019 +0x1860 0x0580001A +0x1860 0x0E80001B +0x1860 0x1980001C// RX_CCK +0x1860 0x0B80001D +0x1860 0x0580001E +0x1860 0x0780001F +0x1860 0x19800020// RX_OFDM +0x1860 0x0B800021 +0x1860 0x05800022 +0x1860 0x07800023 +0x1860 0x19800024// RX_WAIT_RIFS +0x1860 0x0B800025 +0x1860 0x05800026 +0x1860 0x07800027 +0x1860 0x19800028// RX_TO_RX +0x1860 0x0B800029 +0x1860 0x0580002A +0x1860 0x0780002B +//0x1860 0x1980002C // RSVD +//0x1860 0x0B80002D +//0x1860 0x0580002E +//0x1860 0x0680002F +0x1860 0x19800030 // BT or LTE coexist +0x1860 0x0B800031 +0x1860 0x05800032 +0x1860 0x00800033 +0x1860 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0x1860 0x0B800035 +0x1860 0x05800036 +0x1860 0x00800037 +0x1860 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0x1860 0x0B800039 +0x1860 0x0580003A +0x1860 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0x1860 0x1980003C // PMPD_ANAEN +//0x1860 0x0B80003D +//0x1860 0x0580003E +//0x1860 0x0080803F +0x1894 0x01000001 +0x1898 0x00188000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x77777000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x77700000 +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000053 +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c020c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x19800000// RX_WAIT_CCA +0x1a60 0x0B800001 +0x1a60 0x05800002 +0x1a60 0x07800003 +0x1a60 0x19800004// TX_CCK_RFON +0x1a60 0x0B800005 +0x1a60 0x05800006 +0x1a60 0x0E800007 +0x1a60 0x19800008// TX_CCK_BBON +0x1a60 0x0B800009 +0x1a60 0x0580000A +0x1a60 0x0E80000B +0x1a60 0x1980000C// TX_OFDM_RFON +0x1a60 0x0B80000D +0x1a60 0x0580000E +0x1a60 0x0E80000F +0x1a60 0x19800010// TX_OFDM_BBON +0x1a60 0x0B800011 +0x1a60 0x05800012 +0x1a60 0x0E800013 +0x1a60 0x19800014// TX_TO_RX +0x1a60 0x0B800015 +0x1a60 0x05800016 +0x1a60 0x07800017 +0x1a60 0x19800018// TX_TO_TX +0x1a60 0x0B800019 +0x1a60 0x0580001A +0x1a60 0x0E80001B +0x1a60 0x1980001C// RX_CCK +0x1a60 0x0B80001D +0x1a60 0x0580001E +0x1a60 0x0780001F +0x1a60 0x19800020// RX_OFDM +0x1a60 0x0B800021 +0x1a60 0x05800022 +0x1a60 0x07800023 +0x1a60 0x19800024// RX_WAIT_RIFS +0x1a60 0x0B800025 +0x1a60 0x05800026 +0x1a60 0x07800027 +0x1a60 0x19800028// RX_TO_RX +0x1a60 0x0B800029 +0x1a60 0x0580002A +0x1a60 0x0780002B +//0x1a60 0x1980002C // RSVD +//0x1a60 0x0B80002D +//0x1a60 0x0580002E +//0x1a60 0x0680002F +0x1a60 0x19800030 // BT or LTE coexist +0x1a60 0x0B800031 +0x1a60 0x05800032 +0x1a60 0x00800033 +0x1a60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0x1a60 0x0B800035 +0x1a60 0x05800036 +0x1a60 0x00800037 +0x1a60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0x1a60 0x0B800039 +0x1a60 0x0580003A +0x1a60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0x1a60 0x1980003C // PMPD_ANAEN +//0x1a60 0x0B80003D +//0x1a60 0x0580003E +//0x1a60 0x0080803F +0x1a94 0x01000001 +0x1a98 0x00188000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x77777000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x77700000 +//======================= +// PAGE_19 : common setting +//======================= +0x1904 0x00030000 // enable IOQ_iqk_dpk +0x1914 0x00030000 +0x1984 0x03000000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x1998 0x12801000 //CCK CCK 1M +0x1998 0x12801000 //CCK CCK 1M +0x1998 0x12801001 //CCK CCK 2M +0x1998 0x12801002 //CCK CCK 5.5M +0x1998 0x12801003 //CCK CCK 11M +0x1998 0x12801004 //OFDM OFDM 6M +0x1998 0x12801005 //OFDM OFDM 9M +0x1998 0x12801006 //OFDM OFDM 12M +0x1998 0x12801007 //OFDM OFDM 18M +0x1998 0x12801008 //OFDM OFDM 24M +0x1998 0x12801009 //OFDM OFDM 36M +0x1998 0x1280100a //OFDM OFDM 48M +0x1998 0x1280100b //OFDM OFDM 54M +0x1998 0x1280100c //HT nss1 MCS0 +0x1998 0x1280100d //HT nss1 MCS1 +0x1998 0x1280100e //HT nss1 MCS2 +0x1998 0x1280100f //HT nss1 MCS3 +0x1998 0x12801010 //HT nss1 MCS4 +0x1998 0x12801011 //HT nss1 MCS5 +0x1998 0x12801012 //HT nss1 MCS6 +0x1998 0x12801013 //HT nss1 MCS7 +0x1998 0x12801014 //HT nss2 MCS8 +0x1998 0x12801015 //HT nss2 MCS9 +0x1998 0x12801016 //HT nss2 MCS10 +0x1998 0x12801017 //HT nss2 MCS11 +0x1998 0x12801018 //HT nss2 MCS12 +0x1998 0x12801019 //HT nss2 MCS13 +0x1998 0x1280101a //HT nss2 MCS14 +0x1998 0x1280101b //HT nss2 MCS15 +0x1998 0x1280101c //HT nss3 MCS16 +0x1998 0x1280101d //HT nss3 MCS17 +0x1998 0x1280101e //HT nss3 MCS18 +0x1998 0x1280101f //HT nss3 MCS19 +0x1998 0x12801020 //HT nss3 MCS20 +0x1998 0x12801021 //HT nss3 MCS21 +0x1998 0x12801022 //HT nss3 MCS22 +0x1998 0x12801023 //HT nss3 MCS23 +0x1998 0x1280102c //VHT nss1 MCS0 +0x1998 0x1280102d //VHT nss1 MCS1 +0x1998 0x1280102e //VHT nss1 MCS2 +0x1998 0x1280102f //VHT nss1 MCS3 +0x1998 0x12801030 //VHT nss1 MCS4 +0x1998 0x12801031 //VHT nss1 MCS5 +0x1998 0x12801032 //VHT nss1 MCS6 +0x1998 0x12801033 //VHT nss1 MCS7 +0x1998 0x12801034 //VHT nss1 MCS8 +0x1998 0x12801035 //VHT nss1 MCS9 +0x1998 0x12801036 //VHT nss2 MCS0 +0x1998 0x12801037 //VHT nss2 MCS1 +0x1998 0x12801038 //VHT nss2 MCS2 +0x1998 0x12801039 //VHT nss2 MCS3 +0x1998 0x1280103a //VHT nss2 MCS4 +0x1998 0x1280103b //VHT nss2 MCS5 +0x1998 0x1280103c //VHT nss2 MCS6 +0x1998 0x1280103d //VHT nss2 MCS7 +0x1998 0x1280103e //VHT nss2 MCS8 +0x1998 0x1280103f //VHT nss2 MCS9 +0x1998 0x12801040 //VHT nss3 MCS0 +0x1998 0x12801041 //VHT nss3 MCS1 +0x1998 0x12801042 //VHT nss3 MCS2 +0x1998 0x12801043 //VHT nss3 MCS3 +0x1998 0x12801044 //VHT nss3 MCS4 +0x1998 0x12801045 //VHT nss3 MCS5 +0x1998 0x12801046 //VHT nss3 MCS6 +0x1998 0x12801047 //VHT nss3 MCS7 +0x1998 0x12801048 //VHT nss3 MCS8 +0x1998 0x12801049 //VHT nss3 MCS9 +0x1998 0x12801100 //CCK CCK 1M +0x1998 0x12801101 //CCK CCK 2M +0x1998 0x12801102 //CCK CCK 5.5M +0x1998 0x12801103 //CCK CCK 11M +0x1998 0x12801104 //OFDM OFDM 6M +0x1998 0x12801105 //OFDM OFDM 9M +0x1998 0x12801106 //OFDM OFDM 12M +0x1998 0x12801107 //OFDM OFDM 18M +0x1998 0x12801108 //OFDM OFDM 24M +0x1998 0x12801109 //OFDM OFDM 36M +0x1998 0x1280110a //OFDM OFDM 48M +0x1998 0x1280110b //OFDM OFDM 54M +0x1998 0x1280110c //HT nss1 MCS0 +0x1998 0x1280110d //HT nss1 MCS1 +0x1998 0x1280110e //HT nss1 MCS2 +0x1998 0x1280110f //HT nss1 MCS3 +0x1998 0x12801110 //HT nss1 MCS4 +0x1998 0x12801111 //HT nss1 MCS5 +0x1998 0x12801112 //HT nss1 MCS6 +0x1998 0x12801113 //HT nss1 MCS7 +0x1998 0x12801114 //HT nss2 MCS8 +0x1998 0x12801115 //HT nss2 MCS9 +0x1998 0x12801116 //HT nss2 MCS10 +0x1998 0x12801117 //HT nss2 MCS11 +0x1998 0x12801118 //HT nss2 MCS12 +0x1998 0x12801119 //HT nss2 MCS13 +0x1998 0x1280111a //HT nss2 MCS14 +0x1998 0x1280111b //HT nss2 MCS15 +0x1998 0x1280111c //HT nss3 MCS16 +0x1998 0x1280111d //HT nss3 MCS17 +0x1998 0x1280111e //HT nss3 MCS18 +0x1998 0x1280111f //HT nss3 MCS19 +0x1998 0x12801120 //HT nss3 MCS20 +0x1998 0x12801121 //HT nss3 MCS21 +0x1998 0x12801122 //HT nss3 MCS22 +0x1998 0x12801123 //HT nss3 MCS23 +0x1998 0x1280112c //VHT nss1 MCS0 +0x1998 0x1280112d //VHT nss1 MCS1 +0x1998 0x1280112e //VHT nss1 MCS2 +0x1998 0x1280112f //VHT nss1 MCS3 +0x1998 0x12801130 //VHT nss1 MCS4 +0x1998 0x12801131 //VHT nss1 MCS5 +0x1998 0x12801132 //VHT nss1 MCS6 +0x1998 0x12801133 //VHT nss1 MCS7 +0x1998 0x12801134 //VHT nss1 MCS8 +0x1998 0x12801135 //VHT nss1 MCS9 +0x1998 0x12801136 //VHT nss2 MCS0 +0x1998 0x12801137 //VHT nss2 MCS1 +0x1998 0x12801138 //VHT nss2 MCS2 +0x1998 0x12801139 //VHT nss2 MCS3 +0x1998 0x1280113a //VHT nss2 MCS4 +0x1998 0x1280113b //VHT nss2 MCS5 +0x1998 0x1280113c //VHT nss2 MCS6 +0x1998 0x1280113d //VHT nss2 MCS7 +0x1998 0x1280113e //VHT nss2 MCS8 +0x1998 0x1280113f //VHT nss2 MCS9 +0x1998 0x12801140 //VHT nss3 MCS0 +0x1998 0x12801141 //VHT nss3 MCS1 +0x1998 0x12801142 //VHT nss3 MCS2 +0x1998 0x12801143 //VHT nss3 MCS3 +0x1998 0x12801144 //VHT nss3 MCS4 +0x1998 0x12801145 //VHT nss3 MCS5 +0x1998 0x12801146 //VHT nss3 MCS6 +0x1998 0x12801147 //VHT nss3 MCS7 +0x1998 0x12801148 //VHT nss3 MCS8 +0x1998 0x12801149 //VHT nss3 MCS9 +0x1998 0x12801200 //CCK CCK 1M +0x1998 0x12801201 //CCK CCK 2M +0x1998 0x12801202 //CCK CCK 5.5M +0x1998 0x12801203 //CCK CCK 11M +0x1998 0x12801204 //OFDM OFDM 6M +0x1998 0x12801205 //OFDM OFDM 9M +0x1998 0x12801206 //OFDM OFDM 12M +0x1998 0x12801207 //OFDM OFDM 18M +0x1998 0x12801208 //OFDM OFDM 24M +0x1998 0x12801209 //OFDM OFDM 36M +0x1998 0x1280120a //OFDM OFDM 48M +0x1998 0x1280120b //OFDM OFDM 54M +0x1998 0x1280120c //HT nss1 MCS0 +0x1998 0x1280120d //HT nss1 MCS1 +0x1998 0x1280120e //HT nss1 MCS2 +0x1998 0x1280120f //HT nss1 MCS3 +0x1998 0x12801210 //HT nss1 MCS4 +0x1998 0x12801211 //HT nss1 MCS5 +0x1998 0x12801212 //HT nss1 MCS6 +0x1998 0x12801213 //HT nss1 MCS7 +0x1998 0x12801214 //HT nss2 MCS8 +0x1998 0x12801215 //HT nss2 MCS9 +0x1998 0x12801216 //HT nss2 MCS10 +0x1998 0x12801217 //HT nss2 MCS11 +0x1998 0x12801218 //HT nss2 MCS12 +0x1998 0x12801219 //HT nss2 MCS13 +0x1998 0x1280121a //HT nss2 MCS14 +0x1998 0x1280121b //HT nss2 MCS15 +0x1998 0x1280121c //HT nss3 MCS16 +0x1998 0x1280121d //HT nss3 MCS17 +0x1998 0x1280121e //HT nss3 MCS18 +0x1998 0x1280121f //HT nss3 MCS19 +0x1998 0x12801220 //HT nss3 MCS20 +0x1998 0x12801221 //HT nss3 MCS21 +0x1998 0x12801222 //HT nss3 MCS22 +0x1998 0x12801223 //HT nss3 MCS23 +0x1998 0x1280122c //VHT nss1 MCS0 +0x1998 0x1280122d //VHT nss1 MCS1 +0x1998 0x1280122e //VHT nss1 MCS2 +0x1998 0x1280122f //VHT nss1 MCS3 +0x1998 0x12801230 //VHT nss1 MCS4 +0x1998 0x12801231 //VHT nss1 MCS5 +0x1998 0x12801232 //VHT nss1 MCS6 +0x1998 0x12801233 //VHT nss1 MCS7 +0x1998 0x12801234 //VHT nss1 MCS8 +0x1998 0x12801235 //VHT nss1 MCS9 +0x1998 0x12801236 //VHT nss2 MCS0 +0x1998 0x12801237 //VHT nss2 MCS1 +0x1998 0x12801238 //VHT nss2 MCS2 +0x1998 0x12801239 //VHT nss2 MCS3 +0x1998 0x1280123a //VHT nss2 MCS4 +0x1998 0x1280123b //VHT nss2 MCS5 +0x1998 0x1280123c //VHT nss2 MCS6 +0x1998 0x1280123d //VHT nss2 MCS7 +0x1998 0x1280123e //VHT nss2 MCS8 +0x1998 0x1280123f //VHT nss2 MCS9 +0x1998 0x12801240 //VHT nss3 MCS0 +0x1998 0x12801241 //VHT nss3 MCS1 +0x1998 0x12801242 //VHT nss3 MCS2 +0x1998 0x12801243 //VHT nss3 MCS3 +0x1998 0x12801244 //VHT nss3 MCS4 +0x1998 0x12801245 //VHT nss3 MCS5 +0x1998 0x12801246 //VHT nss3 MCS6 +0x1998 0x12801247 //VHT nss3 MCS7 +0x1998 0x12801248 //VHT nss3 MCS8 +0x1998 0x12801249 //VHT nss3 MCS9 +0x1998 0x12801300 //CCK CCK 1M +0x1998 0x12801301 //CCK CCK 2M +0x1998 0x12801302 //CCK CCK 5.5M +0x1998 0x12801303 //CCK CCK 11M +0x1998 0x12801304 //OFDM OFDM 6M +0x1998 0x12801305 //OFDM OFDM 9M +0x1998 0x12801306 //OFDM OFDM 12M +0x1998 0x12801307 //OFDM OFDM 18M +0x1998 0x12801308 //OFDM OFDM 24M +0x1998 0x12801309 //OFDM OFDM 36M +0x1998 0x1280130a //OFDM OFDM 48M +0x1998 0x1280130b //OFDM OFDM 54M +0x1998 0x1280130c //HT nss1 MCS0 +0x1998 0x1280130d //HT nss1 MCS1 +0x1998 0x1280130e //HT nss1 MCS2 +0x1998 0x1280130f //HT nss1 MCS3 +0x1998 0x12801310 //HT nss1 MCS4 +0x1998 0x12801311 //HT nss1 MCS5 +0x1998 0x12801312 //HT nss1 MCS6 +0x1998 0x12801313 //HT nss1 MCS7 +0x1998 0x12801314 //HT nss2 MCS8 +0x1998 0x12801315 //HT nss2 MCS9 +0x1998 0x12801316 //HT nss2 MCS10 +0x1998 0x12801317 //HT nss2 MCS11 +0x1998 0x12801318 //HT nss2 MCS12 +0x1998 0x12801319 //HT nss2 MCS13 +0x1998 0x1280131a //HT nss2 MCS14 +0x1998 0x1280131b //HT nss2 MCS15 +0x1998 0x1280131c //HT nss3 MCS16 +0x1998 0x1280131d //HT nss3 MCS17 +0x1998 0x1280131e //HT nss3 MCS18 +0x1998 0x1280131f //HT nss3 MCS19 +0x1998 0x12801320 //HT nss3 MCS20 +0x1998 0x12801321 //HT nss3 MCS21 +0x1998 0x12801322 //HT nss3 MCS22 +0x1998 0x12801323 //HT nss3 MCS23 +0x1998 0x1280132c //VHT nss1 MCS0 +0x1998 0x1280132d //VHT nss1 MCS1 +0x1998 0x1280132e //VHT nss1 MCS2 +0x1998 0x1280132f //VHT nss1 MCS3 +0x1998 0x12801330 //VHT nss1 MCS4 +0x1998 0x12801331 //VHT nss1 MCS5 +0x1998 0x12801332 //VHT nss1 MCS6 +0x1998 0x12801333 //VHT nss1 MCS7 +0x1998 0x12801334 //VHT nss1 MCS8 +0x1998 0x12801335 //VHT nss1 MCS9 +0x1998 0x12801336 //VHT nss2 MCS0 +0x1998 0x12801337 //VHT nss2 MCS1 +0x1998 0x12801338 //VHT nss2 MCS2 +0x1998 0x12801339 //VHT nss2 MCS3 +0x1998 0x1280133a //VHT nss2 MCS4 +0x1998 0x1280133b //VHT nss2 MCS5 +0x1998 0x1280133c //VHT nss2 MCS6 +0x1998 0x1280133d //VHT nss2 MCS7 +0x1998 0x1280133e //VHT nss2 MCS8 +0x1998 0x1280133f //VHT nss2 MCS9 +0x1998 0x12801340 //VHT nss3 MCS0 +0x1998 0x12801341 //VHT nss3 MCS1 +0x1998 0x12801342 //VHT nss3 MCS2 +0x1998 0x12801343 //VHT nss3 MCS3 +0x1998 0x12801344 //VHT nss3 MCS4 +0x1998 0x12801345 //VHT nss3 MCS5 +0x1998 0x12801346 //VHT nss3 MCS6 +0x1998 0x12801347 //VHT nss3 MCS7 +0x1998 0x12801348 //VHT nss3 MCS8 +0x1998 0x12801349 //VHT nss3 MCS9 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// ADC clk lock procedure +//======================= +0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) +// 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 +// 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line +// 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut + +// power_off/clk_off @ anapar_state=idle mode +0xc60 0x15808002 +0xc60 0x01808003 +0xe60 0x15808002 +0xe60 0x01808003 +0x1860 0x15808002 +0x1860 0x01808003 +0x1a60 0x15808002 +0x1a60 0x01808003 + +0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) +0xc5c 0x00080058 // [19] =1 to turn off ADC +0xe5c 0x00080058 // [19] =1 to turn off ADC +0x185c 0x00080058 // [19] =1 to turn off ADC +0x1a5c 0x00080058 // [19] =1 to turn off ADC + +// power_on/clk_off @ anapar_state=sleep mode +0xc60 0x15808036 +0xc60 0x0F808037 +0xe60 0x15808036 +0xe60 0x0F808037 +0x1860 0x15808036 +0x1860 0x0F808037 +0x1a60 0x15808036 +0x1a60 0x0F808037 + +0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) +0xc5c 0x0D000058 // [19] =0 to turn on ADC +0xe5c 0x0D000058 // [19] =0 to turn on ADC +0x185c 0x0D000058 // [19] =0 to turn on ADC +0x1a5c 0x0D000058 // [19] =0 to turn on ADC + +// power_on/clk_on @ anapar_state=idle mode +0xc60 0x05808002 +0xc60 0x0e808003 +0xe60 0x05808002 +0xe60 0x0e808003 +0x1860 0x05808002 +0x1860 0x0e808003 +0x1a60 0x05808002 +0x1a60 0x0e808003 +// recover original setting @ anapar_state=sleep mode +0xc60 0x05808036 +0xc60 0x0e808037 +0xe60 0x05808036 +0xe60 0x0e808037 +0x1860 0x05808036 +0x1860 0x0e808037 +0x1a60 0x05808036 +0x1a60 0x0e808037 + +0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) +0xb00 0xe3100000 //return true MAC + +//======================= +// PAGE_1c +//======================= +0x1c38 0x00000002 // enable IQK clk +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe24628d2 +0x1b10 0x88010d46 +0x1b14 0x00000000 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b00 0xf8015000 +0x1b00 0xf8057000 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b00 0xf8015002 +0x1b00 0xf8057002 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b00 0xf8015004 +0x1b00 0xf8057004 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b00 0xf8015006 +0x1b00 0xf8057006 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x09060005 +0x1b80 0x09060007 +0x1b80 0x0ffe0015 +0x1b80 0x0ffe0017 +0x1b80 0x00240025 +0x1b80 0x00240027 +0x1b80 0x00040035 +0x1b80 0x00040037 +0x1b80 0x05c00045 +0x1b80 0x05c00047 +0x1b80 0x00070055 +0x1b80 0x00070057 +0x1b80 0x64000065 +0x1b80 0x64000067 +0x1b80 0x00020075 +0x1b80 0x00020077 +0x1b80 0x00080085 +0x1b80 0x00080087 +0x1b80 0x80000095 +0x1b80 0x80000097 +0x1b80 0x090100a5 +0x1b80 0x090100a7 +0x1b80 0x0f0200b5 +0x1b80 0x0f0200b7 +0x1b80 0x002400c5 +0x1b80 0x002400c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x05c000e5 +0x1b80 0x05c000e7 +0x1b80 0x000700f5 +0x1b80 0x000700f7 +0x1b80 0x64020105 +0x1b80 0x64020107 +0x1b80 0x00020115 +0x1b80 0x00020117 +0x1b80 0x00040125 +0x1b80 0x00040127 +0x1b80 0x4a000135 +0x1b80 0x4a000137 +0x1b80 0x4b040145 +0x1b80 0x4b040147 +0x1b80 0x85030155 +0x1b80 0x85030157 +0x1b80 0x40010165 +0x1b80 0x40010167 +0x1b80 0xe0290175 +0x1b80 0xe0290177 +0x1b80 0x00040185 +0x1b80 0x00040187 +0x1b80 0x4b050195 +0x1b80 0x4b050197 +0x1b80 0x860301a5 +0x1b80 0x860301a7 +0x1b80 0x400301b5 +0x1b80 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0x6b401bf7 +0x1b80 0x4d041c05 +0x1b80 0x4d041c07 +0x1b80 0x68481c15 +0x1b80 0x68481c17 +0x1b80 0x66061c25 +0x1b80 0x66061c27 +0x1b80 0x65181c35 +0x1b80 0x65181c37 +0x1b80 0x64471c45 +0x1b80 0x64471c47 +0x1b80 0x23411c55 +0x1b80 0x23411c57 +0x1b80 0x11e81c65 +0x1b80 0x11e81c67 +0x1b80 0x23411c75 +0x1b80 0x23411c77 +0x1b80 0x61e11c85 +0x1b80 0x61e11c87 +0x1b80 0x23411c95 +0x1b80 0x23411c97 +0x1b80 0x70611ca5 +0x1b80 0x70611ca7 +0x1b80 0x4d001cb5 +0x1b80 0x4d001cb7 +0x1b80 0x00011cc5 +0x1b80 0x00011cc7 +0x1b80 0x00000006 +0x1b80 0x00000002 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197F.txt old mode 100755 new mode 100644 index fb8c01185f0..499a79de33d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197F.txt @@ -1,2 +1,2 @@ -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197Fmp.txt old mode 100755 new mode 100644 index f5b24049b44..348729c2056 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_MP_8197Fmp.txt @@ -1,3 +1,3 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp.txt old mode 100755 new mode 100644 index d5db07f97fc..1f985ea3666 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type0.txt old mode 100755 new mode 100644 index d5db07f97fc..1f985ea3666 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type0.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type1.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type1.txt old mode 100755 new mode 100644 index 7179c904203..bcd4200e59f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type1.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type1.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 26 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 26 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 26 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 26 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 21 22 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type2.txt old mode 100755 new mode 100644 index d5db07f97fc..1f985ea3666 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type2.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type3.txt old mode 100755 new mode 100644 index d5db07f97fc..1f985ea3666 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type3.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type4.txt old mode 100755 new mode 100644 index d5db07f97fc..1f985ea3666 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type4.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type5.txt old mode 100755 new mode 100644 index 7c72b1cdcd2..107caa0f4e4 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type5.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 26 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 26 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 26 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 24 25 25 26 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 22 23 23 24 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 26 26 26 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 26 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 24 25 25 26 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 22 23 23 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type6.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type6.txt index d5db07f97fc..1f985ea3666 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type6.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/PHY_REG_PG_8197Fmp_Type6.txt @@ -1,22 +1,22 @@ -//MAC_PHY_Parameter -#Exact -0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff - +//MAC_PHY_Parameter +#Exact +0xe00 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 17 18 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 20 20 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 20 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 18 19 19 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 16 17 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioA_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioA_8197F.txt old mode 100755 new mode 100644 index 24aa24fa2cb..3b2f44dcc74 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioA_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioA_8197F.txt @@ -1,80 +1,80 @@ -//rtl8197f version = 0 - -0x00 0x30000 -0x18 0x00c07 -0xca 0x02000 - -// RXFE -0x81 0x0FC00 -0x82 0x003C0 -0x84 0xf4005 -0x86 0x933a5 -0x87 0x00000 -0x88 0x7B030 - -// RXBB -0x8E 0x64540 -0x8F 0xA8000 - -// TX -0xDF 0x00E00 -0x51 0x00c00 -0x52 0x98003 -0x53 0x18c4b -0x54 0x90030 -0x55 0x82000 -0x56 0x0880F -0x57 0x79000 -0x58 0x603F0 -0x5a 0x50000 -0x5b 0x00006 -0x5c 0x00015 -0x65 0x20000 -0x6e 0x38319 -0xDF 0x00600 - -// TX GAIN TABLE -0xEF 0x00100 -0x33 0x00583 -0x33 0x04983 -0x33 0x08D84 -0x33 0x0CDA5 -0x33 0x10DE5 -0x33 0x14DE8 -0x33 0x18DEB -0x33 0x1CDEE -0x33 0x20DF1 -0x33 0x24DF4 -0x33 0x28DF7 -0xEF 0x00000 - -// SYN -0xc9 0x00600 -0xb1 0x3331f -0xb2 0x33762 -0xb4 0x141f0 -0xb5 0x14000 -0xb6 0x12427 -0xb7 0x1060c -0xb8 0x70f3f -0xb9 0xc0008 -0xba 0x40005 -0xc2 0x02c01 -0xc3 0x0000b -0xc4 0x81e2f -0xc5 0x5c28f -0xc6 0x000a0 -0xc9 0x00600 -0xca 0x02000 - - -0xfe -// LC calibration -0x18 0x08c07 -0xfe -0xfe -0xfe - -0x00 0x35df5 - +//rtl8197f version = 0 + +0x00 0x30000 +0x18 0x00c07 +0xca 0x02000 + +// RXFE +0x81 0x0FC00 +0x82 0x003C0 +0x84 0xf4005 +0x86 0x933a5 +0x87 0x00000 +0x88 0x7B030 + +// RXBB +0x8E 0x64540 +0x8F 0xA8000 + +// TX +0xDF 0x00E00 +0x51 0x00c00 +0x52 0x98003 +0x53 0x18c4b +0x54 0x90030 +0x55 0x82000 +0x56 0x0880F +0x57 0x79000 +0x58 0x603F0 +0x5a 0x50000 +0x5b 0x00006 +0x5c 0x00015 +0x65 0x20000 +0x6e 0x38319 +0xDF 0x00600 + +// TX GAIN TABLE +0xEF 0x00100 +0x33 0x00583 +0x33 0x04983 +0x33 0x08D84 +0x33 0x0CDA5 +0x33 0x10DE5 +0x33 0x14DE8 +0x33 0x18DEB +0x33 0x1CDEE +0x33 0x20DF1 +0x33 0x24DF4 +0x33 0x28DF7 +0xEF 0x00000 + +// SYN +0xc9 0x00600 +0xb1 0x3331f +0xb2 0x33762 +0xb4 0x141f0 +0xb5 0x14000 +0xb6 0x12427 +0xb7 0x1060c +0xb8 0x70f3f +0xb9 0xc0008 +0xba 0x40005 +0xc2 0x02c01 +0xc3 0x0000b +0xc4 0x81e2f +0xc5 0x5c28f +0xc6 0x000a0 +0xc9 0x00600 +0xca 0x02000 + + +0xfe +// LC calibration +0x18 0x08c07 +0xfe +0xfe +0xfe + +0x00 0x35df5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioB_8197F.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioB_8197F.txt old mode 100755 new mode 100644 index 19e8824b2ad..4f70be81685 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioB_8197F.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/RadioB_8197F.txt @@ -1,52 +1,52 @@ -//rtl8197f version = 0 - -0x00 0x30000 - -// RXFE -0x81 0x0FC00 -0x82 0x003C0 -0x84 0x00005 -0x86 0x933a5 -0x87 0x00000 -0x88 0x7B030 - -// RXBB -0x8E 0x64540 -0x8F 0xA8000 - -// TX -0xDF 0x00E00 -0x51 0x00c00 -0x52 0x98003 -0x53 0x18c4b -0x54 0x90030 -0x55 0x82000 -0x56 0x0880F -0x57 0x79000 -0x58 0x603F0 -0x5a 0x50000 -0x5b 0x00006 -0x5c 0x00015 -0x65 0x20000 -0x6e 0x38319 -0xDF 0x00600 - -// TX GAIN TABLE -0xEF 0x00100 -0x33 0x00583 -0x33 0x04983 -0x33 0x08D84 -0x33 0x0CDA5 -0x33 0x10DE5 -0x33 0x14DE8 -0x33 0x18DEB -0x33 0x1CDEE -0x33 0x20DF1 -0x33 0x24DF4 -0x33 0x28DF7 -0xEF 0x00000 - -0x00 0x35df5 - - +//rtl8197f version = 0 + +0x00 0x30000 + +// RXFE +0x81 0x0FC00 +0x82 0x003C0 +0x84 0x00005 +0x86 0x933a5 +0x87 0x00000 +0x88 0x7B030 + +// RXBB +0x8E 0x64540 +0x8F 0xA8000 + +// TX +0xDF 0x00E00 +0x51 0x00c00 +0x52 0x98003 +0x53 0x18c4b +0x54 0x90030 +0x55 0x82000 +0x56 0x0880F +0x57 0x79000 +0x58 0x603F0 +0x5a 0x50000 +0x5b 0x00006 +0x5c 0x00015 +0x65 0x20000 +0x6e 0x38319 +0xDF 0x00600 + +// TX GAIN TABLE +0xEF 0x00100 +0x33 0x00583 +0x33 0x04983 +0x33 0x08D84 +0x33 0x0CDA5 +0x33 0x10DE5 +0x33 0x14DE8 +0x33 0x18DEB +0x33 0x1CDEE +0x33 0x20DF1 +0x33 0x24DF4 +0x33 0x28DF7 +0xEF 0x00000 + +0x00 0x35df5 + + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp.txt old mode 100755 new mode 100644 index 20cf5229756..8b9d2e0a56c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 17 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 17 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_TXBF.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_TXBF.txt old mode 100755 new mode 100644 index 22e9694a927..d846e5b743d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_TXBF.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_TXBF.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 18 18 -CH02 23 18 18 -CH03 23 18 18 -CH04 23 18 18 -CH05 23 18 18 -CH06 23 18 18 -CH07 23 18 18 -CH08 23 18 18 -CH09 23 18 18 -CH10 23 18 18 -CH11 23 18 18 -CH12 23 18 18 -CH13 23 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 22 18 18 -CH02 23 18 18 -CH03 24 18 18 -CH04 25 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 25 18 18 -CH08 24 18 18 -CH09 23 18 18 -CH10 22 18 18 -CH11 21 18 18 -CH12 18 18 18 -CH13 16 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 21 18 18 -CH02 22 18 18 -CH03 23 18 18 -CH04 24 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 24 18 18 -CH08 23 18 18 -CH09 22 18 18 -CH10 21 18 18 -CH11 20 18 18 -CH12 17 18 18 -CH13 15 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 20 18 18 -CH02 21 18 18 -CH03 22 18 18 -CH04 23 18 18 -CH05 24 18 18 -CH06 24 18 18 -CH07 23 18 18 -CH08 22 18 18 -CH09 21 18 18 -CH10 20 18 18 -CH11 19 18 18 -CH12 15 18 18 -CH13 13 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 20 18 18 -CH04 21 18 18 -CH05 22 18 18 -CH06 23 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 19 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 19 18 18 -CH04 20 18 18 -CH05 21 18 18 -CH06 22 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 17 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 18 18 +CH02 23 18 18 +CH03 23 18 18 +CH04 23 18 18 +CH05 23 18 18 +CH06 23 18 18 +CH07 23 18 18 +CH08 23 18 18 +CH09 23 18 18 +CH10 23 18 18 +CH11 23 18 18 +CH12 23 18 18 +CH13 23 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 22 18 18 +CH02 23 18 18 +CH03 24 18 18 +CH04 25 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 25 18 18 +CH08 24 18 18 +CH09 23 18 18 +CH10 22 18 18 +CH11 21 18 18 +CH12 18 18 18 +CH13 16 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 21 18 18 +CH02 22 18 18 +CH03 23 18 18 +CH04 24 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 24 18 18 +CH08 23 18 18 +CH09 22 18 18 +CH10 21 18 18 +CH11 20 18 18 +CH12 17 18 18 +CH13 15 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 20 18 18 +CH02 21 18 18 +CH03 22 18 18 +CH04 23 18 18 +CH05 24 18 18 +CH06 24 18 18 +CH07 23 18 18 +CH08 22 18 18 +CH09 21 18 18 +CH10 20 18 18 +CH11 19 18 18 +CH12 15 18 18 +CH13 13 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 20 18 18 +CH04 21 18 18 +CH05 22 18 18 +CH06 23 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 19 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 19 18 18 +CH04 20 18 18 +CH05 21 18 18 +CH06 22 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 17 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type0.txt old mode 100755 new mode 100644 index bddfd2288a7..1526a297668 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type0.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 19 16 16 -CH03 20 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 19 16 16 -CH11 18 16 16 -CH12 17 16 16 -CH13 15 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 19 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 18 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 18 15 15 -CH04 18 15 15 -CH05 18 15 15 -CH06 18 15 15 -CH07 18 15 15 -CH08 18 15 15 -CH09 17 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 14 15 15 -CH13 13 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 16 16 -CH04 16 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 16 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 16 15 15 -CH09 15 15 15 -CH10 14 15 15 -CH11 14 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 19 16 16 +CH03 20 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 19 16 16 +CH11 18 16 16 +CH12 17 16 16 +CH13 15 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 19 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 18 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 18 15 15 +CH04 18 15 15 +CH05 18 15 15 +CH06 18 15 15 +CH07 18 15 15 +CH08 18 15 15 +CH09 17 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 14 15 15 +CH13 13 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 16 16 +CH04 16 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 16 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 16 15 15 +CH09 15 15 15 +CH10 14 15 15 +CH11 14 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type1.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type1.txt old mode 100755 new mode 100644 index 22e9694a927..d846e5b743d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type1.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type1.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 18 18 -CH02 23 18 18 -CH03 23 18 18 -CH04 23 18 18 -CH05 23 18 18 -CH06 23 18 18 -CH07 23 18 18 -CH08 23 18 18 -CH09 23 18 18 -CH10 23 18 18 -CH11 23 18 18 -CH12 23 18 18 -CH13 23 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 22 18 18 -CH02 23 18 18 -CH03 24 18 18 -CH04 25 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 25 18 18 -CH08 24 18 18 -CH09 23 18 18 -CH10 22 18 18 -CH11 21 18 18 -CH12 18 18 18 -CH13 16 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 21 18 18 -CH02 22 18 18 -CH03 23 18 18 -CH04 24 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 24 18 18 -CH08 23 18 18 -CH09 22 18 18 -CH10 21 18 18 -CH11 20 18 18 -CH12 17 18 18 -CH13 15 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 20 18 18 -CH02 21 18 18 -CH03 22 18 18 -CH04 23 18 18 -CH05 24 18 18 -CH06 24 18 18 -CH07 23 18 18 -CH08 22 18 18 -CH09 21 18 18 -CH10 20 18 18 -CH11 19 18 18 -CH12 15 18 18 -CH13 13 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 20 18 18 -CH04 21 18 18 -CH05 22 18 18 -CH06 23 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 19 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 19 18 18 -CH04 20 18 18 -CH05 21 18 18 -CH06 22 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 17 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 18 18 +CH02 23 18 18 +CH03 23 18 18 +CH04 23 18 18 +CH05 23 18 18 +CH06 23 18 18 +CH07 23 18 18 +CH08 23 18 18 +CH09 23 18 18 +CH10 23 18 18 +CH11 23 18 18 +CH12 23 18 18 +CH13 23 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 22 18 18 +CH02 23 18 18 +CH03 24 18 18 +CH04 25 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 25 18 18 +CH08 24 18 18 +CH09 23 18 18 +CH10 22 18 18 +CH11 21 18 18 +CH12 18 18 18 +CH13 16 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 21 18 18 +CH02 22 18 18 +CH03 23 18 18 +CH04 24 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 24 18 18 +CH08 23 18 18 +CH09 22 18 18 +CH10 21 18 18 +CH11 20 18 18 +CH12 17 18 18 +CH13 15 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 20 18 18 +CH02 21 18 18 +CH03 22 18 18 +CH04 23 18 18 +CH05 24 18 18 +CH06 24 18 18 +CH07 23 18 18 +CH08 22 18 18 +CH09 21 18 18 +CH10 20 18 18 +CH11 19 18 18 +CH12 15 18 18 +CH13 13 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 20 18 18 +CH04 21 18 18 +CH05 22 18 18 +CH06 23 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 19 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 19 18 18 +CH04 20 18 18 +CH05 21 18 18 +CH06 22 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 17 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type2.txt old mode 100755 new mode 100644 index bddfd2288a7..1526a297668 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type2.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 19 16 16 -CH03 20 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 19 16 16 -CH11 18 16 16 -CH12 17 16 16 -CH13 15 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 19 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 18 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 18 15 15 -CH04 18 15 15 -CH05 18 15 15 -CH06 18 15 15 -CH07 18 15 15 -CH08 18 15 15 -CH09 17 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 14 15 15 -CH13 13 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 16 16 -CH04 16 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 16 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 16 15 15 -CH09 15 15 15 -CH10 14 15 15 -CH11 14 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 19 16 16 +CH03 20 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 19 16 16 +CH11 18 16 16 +CH12 17 16 16 +CH13 15 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 19 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 18 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 18 15 15 +CH04 18 15 15 +CH05 18 15 15 +CH06 18 15 15 +CH07 18 15 15 +CH08 18 15 15 +CH09 17 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 14 15 15 +CH13 13 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 16 16 +CH04 16 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 16 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 16 15 15 +CH09 15 15 15 +CH10 14 15 15 +CH11 14 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type3.txt old mode 100755 new mode 100644 index bddfd2288a7..1526a297668 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type3.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 19 16 16 -CH03 20 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 19 16 16 -CH11 18 16 16 -CH12 17 16 16 -CH13 15 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 19 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 18 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 18 15 15 -CH04 18 15 15 -CH05 18 15 15 -CH06 18 15 15 -CH07 18 15 15 -CH08 18 15 15 -CH09 17 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 14 15 15 -CH13 13 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 16 16 -CH04 16 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 16 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 16 15 15 -CH09 15 15 15 -CH10 14 15 15 -CH11 14 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 19 16 16 +CH03 20 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 19 16 16 +CH11 18 16 16 +CH12 17 16 16 +CH13 15 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 19 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 18 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 18 15 15 +CH04 18 15 15 +CH05 18 15 15 +CH06 18 15 15 +CH07 18 15 15 +CH08 18 15 15 +CH09 17 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 14 15 15 +CH13 13 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 16 16 +CH04 16 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 16 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 16 15 15 +CH09 15 15 15 +CH10 14 15 15 +CH11 14 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type4.txt old mode 100755 new mode 100644 index bddfd2288a7..1526a297668 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type4.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 19 16 16 -CH03 20 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 19 16 16 -CH11 18 16 16 -CH12 17 16 16 -CH13 15 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 19 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 18 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 18 15 15 -CH04 18 15 15 -CH05 18 15 15 -CH06 18 15 15 -CH07 18 15 15 -CH08 18 15 15 -CH09 17 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 14 15 15 -CH13 13 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 16 16 -CH04 16 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 16 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 16 15 15 -CH09 15 15 15 -CH10 14 15 15 -CH11 14 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 19 16 16 +CH03 20 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 19 16 16 +CH11 18 16 16 +CH12 17 16 16 +CH13 15 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 19 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 18 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 18 15 15 +CH04 18 15 15 +CH05 18 15 15 +CH06 18 15 15 +CH07 18 15 15 +CH08 18 15 15 +CH09 17 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 14 15 15 +CH13 13 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 16 16 +CH04 16 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 16 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 16 15 15 +CH09 15 15 15 +CH10 14 15 15 +CH11 14 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type5.txt old mode 100755 new mode 100644 index 22e9694a927..d846e5b743d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type5.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 18 18 -CH02 23 18 18 -CH03 23 18 18 -CH04 23 18 18 -CH05 23 18 18 -CH06 23 18 18 -CH07 23 18 18 -CH08 23 18 18 -CH09 23 18 18 -CH10 23 18 18 -CH11 23 18 18 -CH12 23 18 18 -CH13 23 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 22 18 18 -CH02 23 18 18 -CH03 24 18 18 -CH04 25 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 25 18 18 -CH08 24 18 18 -CH09 23 18 18 -CH10 22 18 18 -CH11 21 18 18 -CH12 18 18 18 -CH13 16 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 21 18 18 -CH02 22 18 18 -CH03 23 18 18 -CH04 24 18 18 -CH05 25 18 18 -CH06 25 18 18 -CH07 24 18 18 -CH08 23 18 18 -CH09 22 18 18 -CH10 21 18 18 -CH11 20 18 18 -CH12 17 18 18 -CH13 15 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 20 18 18 -CH02 21 18 18 -CH03 22 18 18 -CH04 23 18 18 -CH05 24 18 18 -CH06 24 18 18 -CH07 23 18 18 -CH08 22 18 18 -CH09 21 18 18 -CH10 20 18 18 -CH11 19 18 18 -CH12 15 18 18 -CH13 13 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 20 18 18 -CH04 21 18 18 -CH05 22 18 18 -CH06 23 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 19 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 19 18 18 -CH04 20 18 18 -CH05 21 18 18 -CH06 22 18 18 -CH07 22 18 18 -CH08 21 18 18 -CH09 20 18 18 -CH10 17 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 18 18 +CH02 23 18 18 +CH03 23 18 18 +CH04 23 18 18 +CH05 23 18 18 +CH06 23 18 18 +CH07 23 18 18 +CH08 23 18 18 +CH09 23 18 18 +CH10 23 18 18 +CH11 23 18 18 +CH12 23 18 18 +CH13 23 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 22 18 18 +CH02 23 18 18 +CH03 24 18 18 +CH04 25 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 25 18 18 +CH08 24 18 18 +CH09 23 18 18 +CH10 22 18 18 +CH11 21 18 18 +CH12 18 18 18 +CH13 16 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 21 18 18 +CH02 22 18 18 +CH03 23 18 18 +CH04 24 18 18 +CH05 25 18 18 +CH06 25 18 18 +CH07 24 18 18 +CH08 23 18 18 +CH09 22 18 18 +CH10 21 18 18 +CH11 20 18 18 +CH12 17 18 18 +CH13 15 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 20 18 18 +CH02 21 18 18 +CH03 22 18 18 +CH04 23 18 18 +CH05 24 18 18 +CH06 24 18 18 +CH07 23 18 18 +CH08 22 18 18 +CH09 21 18 18 +CH10 20 18 18 +CH11 19 18 18 +CH12 15 18 18 +CH13 13 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 20 18 18 +CH04 21 18 18 +CH05 22 18 18 +CH06 23 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 19 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 19 18 18 +CH04 20 18 18 +CH05 21 18 18 +CH06 22 18 18 +CH07 22 18 18 +CH08 21 18 18 +CH09 20 18 18 +CH10 17 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type6.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type6.txt index bddfd2288a7..1526a297668 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type6.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TXPWR_LMT_8197Fmp_Type6.txt @@ -1,229 +1,229 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 19 16 16 -CH03 20 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 19 16 16 -CH11 18 16 16 -CH12 17 16 16 -CH13 15 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 19 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 19 16 16 -CH04 19 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 19 16 16 -CH09 18 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 15 16 16 -CH13 13 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 18 15 15 -CH04 18 15 15 -CH05 18 15 15 -CH06 18 15 15 -CH07 18 15 15 -CH08 18 15 15 -CH09 17 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 14 15 15 -CH13 13 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 16 16 -CH04 16 16 16 -CH05 19 16 16 -CH06 19 16 16 -CH07 19 16 16 -CH08 16 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 16 15 15 -CH09 15 15 15 -CH10 14 15 15 -CH11 14 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 19 16 16 +CH03 20 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 19 16 16 +CH11 18 16 16 +CH12 17 16 16 +CH13 15 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 19 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 19 16 16 +CH04 19 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 19 16 16 +CH09 18 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 15 16 16 +CH13 13 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 18 15 15 +CH04 18 15 15 +CH05 18 15 15 +CH06 18 15 15 +CH07 18 15 15 +CH08 18 15 15 +CH09 17 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 14 15 15 +CH13 13 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 16 16 +CH04 16 16 16 +CH05 19 16 16 +CH06 19 16 16 +CH07 19 16 16 +CH08 16 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 16 15 15 +CH09 15 15 15 +CH10 14 15 15 +CH11 14 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA ## END \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TxPowerTrack_AP_8197Fmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TxPowerTrack_AP_8197Fmp.txt old mode 100755 new mode 100644 index eed1119c7a6..e1c5dad0968 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TxPowerTrack_AP_8197Fmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/TxPowerTrack_AP_8197Fmp.txt @@ -1,13 +1,13 @@ -//rtl8197f version = 20 -// -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKA_P -[2G][A][-][CCK] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GCCKA_N -[2G][B][+][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKB_P -[2G][B][-][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,17,17,17,17,17,17,17,17} //2GCCKB_N -[2G][A][+][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GA_P -[2G][A][-][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GA_N -[2G][B][+][ALL] = {0,1,1,2,3,4,4,5,6,7,7,8,9,10,11,12,12,13,14,15,16,17,17,18,19,20,21,22,22,22} //2GB_P +//rtl8197f version = 20 +// +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKA_P +[2G][A][-][CCK] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GCCKA_N +[2G][B][+][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKB_P +[2G][B][-][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,17,17,17,17,17,17,17,17} //2GCCKB_N +[2G][A][+][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GA_P +[2G][A][-][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GA_N +[2G][B][+][ALL] = {0,1,1,2,3,4,4,5,6,7,7,8,9,10,11,12,12,13,14,15,16,17,17,18,19,20,21,22,22,22} //2GB_P [2G][B][-][ALL] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,18,18,18,18,18,18,18,18} //2GB_N \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/Version.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/Version.txt old mode 100755 new mode 100644 index 237a40b78c7..79468d5fe33 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/Version.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/Version.txt @@ -1 +1 @@ -CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 +CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8197F/rtl8197Ffw.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8197F/rtl8197Ffw.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A.txt old mode 100755 new mode 100644 index 795f9cb7e18..6572fbd747d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xfe020001 // Pin=-108dBm -0x81c 0xfd040001 // Pin=-106dBm -0x81c 0xfc060001 // Pin=-104dBm -0x81c 0xfb080001 // Pin=-102dBm -0x81c 0xfa0a0001 // Pin=-100dBm -0x81c 0xf90c0001 // Pin=-98dBm -0x81c 0xf80e0001 // Pin=-96dBm -0x81c 0xf7100001 // Pin=-94dBm -0x81c 0xf6120001 // Pin=-92dBm -0x81c 0xf5140001 // Pin=-90dBm -0x81c 0xf4160001 // Pin=-88dBm -0x81c 0xf3180001 // Pin=-86dBm -0x81c 0xf21a0001 // Pin=-84dBm -0x81c 0xf11c0001 // Pin=-82dBm -0x81c 0xef1e0001 // Pin=-80dBm -0x81c 0xee200001 // Pin=-78dBm -0x81c 0xed220001 // Pin=-76dBm -0x81c 0xec240001 // Pin=-74dBm -0x81c 0xeb260001 // Pin=-72dBm -0x81c 0xea280001 // Pin=-70dBm -0x81c 0xe92a0001 // Pin=-68dBm -0x81c 0xe82c0001 // Pin=-66dBm -0x81c 0xe72e0001 // Pin=-64dBm -0x81c 0xe6300001 // Pin=-62dBm -0x81c 0xe5320001 // Pin=-60dBm -0x81c 0xe4340001 // Pin=-58dBm -0x81c 0xc7360001 // Pin=-56dBm -0x81c 0xc6380001 // Pin=-54dBm -0x81c 0xc53a0001 // Pin=-52dBm -0x81c 0xc43c0001 // Pin=-50dBm -0x81c 0xc33e0001 // Pin=-48dBm -0x81c 0xa5400001 // Pin=-46dBm -0x81c 0xa4420001 // Pin=-44dBm -0x81c 0xa3440001 // Pin=-42dBm -0x81c 0xa2460001 // Pin=-40dBm -0x81c 0x88480001 // Pin=-38dBm -0x81c 0x874a0001 // Pin=-36dBm -0x81c 0x694c0001 // Pin=-34dBm -0x81c 0x684e0001 // Pin=-32dBm -0x81c 0x67500001 // Pin=-30dBm -0x81c 0x66520001 // Pin=-28dBm -0x81c 0x65540001 // Pin=-26dBm -0x81c 0x64560001 // Pin=-24dBm -0x81c 0x63580001 // Pin=-22dBm -0x81c 0x625a0001 // Pin=-20dBm -0x81c 0x455c0001 // Pin=-18dBm -0x81c 0x445e0001 // Pin=-16dBm -0x81c 0x43600001 // Pin=-14dBm -0x81c 0x42620001 // Pin=-12dBm -0x81c 0x28640001 // Pin=-10dBm -0x81c 0x27660001 // Pin=-08dBm -0x81c 0x26680001 // Pin=-06dBm -0x81c 0x256a0001 // Pin=-04dBm -0x81c 0x246c0001 // Pin=-02dBm -0x81c 0x236e0001 // Pin=-00dBm -0x81c 0x22700001 // Pin=+02dBm -0x81c 0x21720001 // Pin=+04dBm -0x81c 0x21740001 // Pin=+06dBm -0x81c 0x21760001 // Pin=+08dBm -0x81c 0x21780001 // Pin=+10dBm -0x81c 0x217a0001 // Pin=+12dBm -0x81c 0x217c0001 // Pin=+14dBm -0x81c 0x217e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xff040101 // Pin=-106dBm -0x81c 0xfe060101 // Pin=-104dBm -0x81c 0xfd080101 // Pin=-102dBm -0x81c 0xfc0a0101 // Pin=-100dBm -0x81c 0xfb0c0101 // Pin=-98dBm -0x81c 0xfa0e0101 // Pin=-96dBm -0x81c 0xf9100101 // Pin=-94dBm -0x81c 0xf8120101 // Pin=-92dBm -0x81c 0xf7140101 // Pin=-90dBm -0x81c 0xf6160101 // Pin=-88dBm -0x81c 0xf5180101 // Pin=-86dBm -0x81c 0xf41a0101 // Pin=-84dBm -0x81c 0xf31c0101 // Pin=-82dBm -0x81c 0xf21e0101 // Pin=-80dBm -0x81c 0xf1200101 // Pin=-78dBm -0x81c 0xf0220101 // Pin=-76dBm -0x81c 0xef240101 // Pin=-74dBm -0x81c 0xee260101 // Pin=-72dBm -0x81c 0xed280101 // Pin=-70dBm -0x81c 0xec2a0101 // Pin=-68dBm -0x81c 0xeb2c0101 // Pin=-66dBm -0x81c 0xea2e0101 // Pin=-64dBm -0x81c 0xe9300101 // Pin=-62dBm -0x81c 0xe8320101 // Pin=-60dBm -0x81c 0xe7340101 // Pin=-58dBm -0x81c 0xe6360101 // Pin=-56dBm -0x81c 0xca380101 // Pin=-54dBm -0x81c 0xc93a0101 // Pin=-52dBm -0x81c 0xc83c0101 // Pin=-50dBm -0x81c 0xc73e0101 // Pin=-48dBm -0x81c 0xc6400101 // Pin=-46dBm -0x81c 0xc5420101 // Pin=-44dBm -0x81c 0xc4440101 // Pin=-42dBm -0x81c 0xc3460101 // Pin=-40dBm -0x81c 0xc2480101 // Pin=-38dBm -0x81c 0xa44a0101 // Pin=-36dBm -0x81c 0xa34c0101 // Pin=-34dBm -0x81c 0xa24e0101 // Pin=-32dBm -0x81c 0x84500101 // Pin=-30dBm -0x81c 0x83520101 // Pin=-28dBm -0x81c 0x82540101 // Pin=-26dBm -0x81c 0x65560101 // Pin=-24dBm -0x81c 0x64580101 // Pin=-22dBm -0x81c 0x635a0101 // Pin=-20dBm -0x81c 0x445c0101 // Pin=-18dBm -0x81c 0x435e0101 // Pin=-16dBm -0x81c 0x42600101 // Pin=-14dBm -0x81c 0x24620101 // Pin=-12dBm -0x81c 0x23640101 // Pin=-10dBm -0x81c 0x22660101 // Pin=-08dBm -0x81c 0x04680101 // Pin=-06dBm -0x81c 0x036a0101 // Pin=-04dBm -0x81c 0x026c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x02700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xfe020001 // Pin=-108dBm +0x81c 0xfd040001 // Pin=-106dBm +0x81c 0xfc060001 // Pin=-104dBm +0x81c 0xfb080001 // Pin=-102dBm +0x81c 0xfa0a0001 // Pin=-100dBm +0x81c 0xf90c0001 // Pin=-98dBm +0x81c 0xf80e0001 // Pin=-96dBm +0x81c 0xf7100001 // Pin=-94dBm +0x81c 0xf6120001 // Pin=-92dBm +0x81c 0xf5140001 // Pin=-90dBm +0x81c 0xf4160001 // Pin=-88dBm +0x81c 0xf3180001 // Pin=-86dBm +0x81c 0xf21a0001 // Pin=-84dBm +0x81c 0xf11c0001 // Pin=-82dBm +0x81c 0xef1e0001 // Pin=-80dBm +0x81c 0xee200001 // Pin=-78dBm +0x81c 0xed220001 // Pin=-76dBm +0x81c 0xec240001 // Pin=-74dBm +0x81c 0xeb260001 // Pin=-72dBm +0x81c 0xea280001 // Pin=-70dBm +0x81c 0xe92a0001 // Pin=-68dBm +0x81c 0xe82c0001 // Pin=-66dBm +0x81c 0xe72e0001 // Pin=-64dBm +0x81c 0xe6300001 // Pin=-62dBm +0x81c 0xe5320001 // Pin=-60dBm +0x81c 0xe4340001 // Pin=-58dBm +0x81c 0xc7360001 // Pin=-56dBm +0x81c 0xc6380001 // Pin=-54dBm +0x81c 0xc53a0001 // Pin=-52dBm +0x81c 0xc43c0001 // Pin=-50dBm +0x81c 0xc33e0001 // Pin=-48dBm +0x81c 0xa5400001 // Pin=-46dBm +0x81c 0xa4420001 // Pin=-44dBm +0x81c 0xa3440001 // Pin=-42dBm +0x81c 0xa2460001 // Pin=-40dBm +0x81c 0x88480001 // Pin=-38dBm +0x81c 0x874a0001 // Pin=-36dBm +0x81c 0x694c0001 // Pin=-34dBm +0x81c 0x684e0001 // Pin=-32dBm +0x81c 0x67500001 // Pin=-30dBm +0x81c 0x66520001 // Pin=-28dBm +0x81c 0x65540001 // Pin=-26dBm +0x81c 0x64560001 // Pin=-24dBm +0x81c 0x63580001 // Pin=-22dBm +0x81c 0x625a0001 // Pin=-20dBm +0x81c 0x455c0001 // Pin=-18dBm +0x81c 0x445e0001 // Pin=-16dBm +0x81c 0x43600001 // Pin=-14dBm +0x81c 0x42620001 // Pin=-12dBm +0x81c 0x28640001 // Pin=-10dBm +0x81c 0x27660001 // Pin=-08dBm +0x81c 0x26680001 // Pin=-06dBm +0x81c 0x256a0001 // Pin=-04dBm +0x81c 0x246c0001 // Pin=-02dBm +0x81c 0x236e0001 // Pin=-00dBm +0x81c 0x22700001 // Pin=+02dBm +0x81c 0x21720001 // Pin=+04dBm +0x81c 0x21740001 // Pin=+06dBm +0x81c 0x21760001 // Pin=+08dBm +0x81c 0x21780001 // Pin=+10dBm +0x81c 0x217a0001 // Pin=+12dBm +0x81c 0x217c0001 // Pin=+14dBm +0x81c 0x217e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xff040101 // Pin=-106dBm +0x81c 0xfe060101 // Pin=-104dBm +0x81c 0xfd080101 // Pin=-102dBm +0x81c 0xfc0a0101 // Pin=-100dBm +0x81c 0xfb0c0101 // Pin=-98dBm +0x81c 0xfa0e0101 // Pin=-96dBm +0x81c 0xf9100101 // Pin=-94dBm +0x81c 0xf8120101 // Pin=-92dBm +0x81c 0xf7140101 // Pin=-90dBm +0x81c 0xf6160101 // Pin=-88dBm +0x81c 0xf5180101 // Pin=-86dBm +0x81c 0xf41a0101 // Pin=-84dBm +0x81c 0xf31c0101 // Pin=-82dBm +0x81c 0xf21e0101 // Pin=-80dBm +0x81c 0xf1200101 // Pin=-78dBm +0x81c 0xf0220101 // Pin=-76dBm +0x81c 0xef240101 // Pin=-74dBm +0x81c 0xee260101 // Pin=-72dBm +0x81c 0xed280101 // Pin=-70dBm +0x81c 0xec2a0101 // Pin=-68dBm +0x81c 0xeb2c0101 // Pin=-66dBm +0x81c 0xea2e0101 // Pin=-64dBm +0x81c 0xe9300101 // Pin=-62dBm +0x81c 0xe8320101 // Pin=-60dBm +0x81c 0xe7340101 // Pin=-58dBm +0x81c 0xe6360101 // Pin=-56dBm +0x81c 0xca380101 // Pin=-54dBm +0x81c 0xc93a0101 // Pin=-52dBm +0x81c 0xc83c0101 // Pin=-50dBm +0x81c 0xc73e0101 // Pin=-48dBm +0x81c 0xc6400101 // Pin=-46dBm +0x81c 0xc5420101 // Pin=-44dBm +0x81c 0xc4440101 // Pin=-42dBm +0x81c 0xc3460101 // Pin=-40dBm +0x81c 0xc2480101 // Pin=-38dBm +0x81c 0xa44a0101 // Pin=-36dBm +0x81c 0xa34c0101 // Pin=-34dBm +0x81c 0xa24e0101 // Pin=-32dBm +0x81c 0x84500101 // Pin=-30dBm +0x81c 0x83520101 // Pin=-28dBm +0x81c 0x82540101 // Pin=-26dBm +0x81c 0x65560101 // Pin=-24dBm +0x81c 0x64580101 // Pin=-22dBm +0x81c 0x635a0101 // Pin=-20dBm +0x81c 0x445c0101 // Pin=-18dBm +0x81c 0x435e0101 // Pin=-16dBm +0x81c 0x42600101 // Pin=-14dBm +0x81c 0x24620101 // Pin=-12dBm +0x81c 0x23640101 // Pin=-10dBm +0x81c 0x22660101 // Pin=-08dBm +0x81c 0x04680101 // Pin=-06dBm +0x81c 0x036a0101 // Pin=-04dBm +0x81c 0x026c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x02700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A_hp.txt old mode 100755 new mode 100644 index 64279ed3efd..90a6b469083 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814A_hp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xfe060001 // Pin=-104dBm -0x81c 0xfd080001 // Pin=-102dBm -0x81c 0xfc0a0001 // Pin=-100dBm -0x81c 0xfb0c0001 // Pin=-98dBm -0x81c 0xfa0e0001 // Pin=-96dBm -0x81c 0xf9100001 // Pin=-94dBm -0x81c 0xf8120001 // Pin=-92dBm -0x81c 0xf7140001 // Pin=-90dBm -0x81c 0xf6160001 // Pin=-88dBm -0x81c 0xf5180001 // Pin=-86dBm -0x81c 0xf41a0001 // Pin=-84dBm -0x81c 0xf31c0001 // Pin=-82dBm -0x81c 0xf21e0001 // Pin=-80dBm -0x81c 0xf1200001 // Pin=-78dBm -0x81c 0xef220001 // Pin=-76dBm -0x81c 0xee240001 // Pin=-74dBm -0x81c 0xed260001 // Pin=-72dBm -0x81c 0xec280001 // Pin=-70dBm -0x81c 0xeb2a0001 // Pin=-68dBm -0x81c 0xea2c0001 // Pin=-66dBm -0x81c 0xe92e0001 // Pin=-64dBm -0x81c 0xe8300001 // Pin=-62dBm -0x81c 0xe7320001 // Pin=-60dBm -0x81c 0xe6340001 // Pin=-58dBm -0x81c 0xc8360001 // Pin=-56dBm -0x81c 0xc7380001 // Pin=-54dBm -0x81c 0xc63a0001 // Pin=-52dBm -0x81c 0xc53c0001 // Pin=-50dBm -0x81c 0xc43e0001 // Pin=-48dBm -0x81c 0xc3400001 // Pin=-46dBm -0x81c 0xc2420001 // Pin=-44dBm -0x81c 0xc1440001 // Pin=-42dBm -0x81c 0xa8460001 // Pin=-40dBm -0x81c 0xa7480001 // Pin=-38dBm -0x81c 0xa64a0001 // Pin=-36dBm -0x81c 0x6a4c0001 // Pin=-34dBm -0x81c 0x694e0001 // Pin=-32dBm -0x81c 0x68500001 // Pin=-30dBm -0x81c 0x67520001 // Pin=-28dBm -0x81c 0x66540001 // Pin=-26dBm -0x81c 0x65560001 // Pin=-24dBm -0x81c 0x64580001 // Pin=-22dBm -0x81c 0x635a0001 // Pin=-20dBm -0x81c 0x475c0001 // Pin=-18dBm -0x81c 0x465e0001 // Pin=-16dBm -0x81c 0x45600001 // Pin=-14dBm -0x81c 0x44620001 // Pin=-12dBm -0x81c 0x43640001 // Pin=-10dBm -0x81c 0x42660001 // Pin=-08dBm -0x81c 0x41680001 // Pin=-06dBm -0x81c 0x416a0001 // Pin=-04dBm -0x81c 0x416c0001 // Pin=-02dBm -0x81c 0x416e0001 // Pin=-00dBm -0x81c 0x41700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfa000101 // Pin=-110dBm -0x81c 0xf9020101 // Pin=-108dBm -0x81c 0xf8040101 // Pin=-106dBm -0x81c 0xf7060101 // Pin=-104dBm -0x81c 0xf6080101 // Pin=-102dBm -0x81c 0xf50a0101 // Pin=-100dBm -0x81c 0xf40c0101 // Pin=-98dBm -0x81c 0xf30e0101 // Pin=-96dBm -0x81c 0xf2100101 // Pin=-94dBm -0x81c 0xf1120101 // Pin=-92dBm -0x81c 0xf0140101 // Pin=-90dBm -0x81c 0xef160101 // Pin=-88dBm -0x81c 0xee180101 // Pin=-86dBm -0x81c 0xed1a0101 // Pin=-84dBm -0x81c 0xec1c0101 // Pin=-82dBm -0x81c 0xeb1e0101 // Pin=-80dBm -0x81c 0xea200101 // Pin=-78dBm -0x81c 0xe9220101 // Pin=-76dBm -0x81c 0xe8240101 // Pin=-74dBm -0x81c 0xe7260101 // Pin=-72dBm -0x81c 0xe6280101 // Pin=-70dBm -0x81c 0xca2a0101 // Pin=-68dBm -0x81c 0xc92c0101 // Pin=-66dBm -0x81c 0xc82e0101 // Pin=-64dBm -0x81c 0xc7300101 // Pin=-62dBm -0x81c 0xc6320101 // Pin=-60dBm -0x81c 0xc5340101 // Pin=-58dBm -0x81c 0xc4360101 // Pin=-56dBm -0x81c 0xc3380101 // Pin=-54dBm -0x81c 0xc23a0101 // Pin=-52dBm -0x81c 0xa53c0101 // Pin=-50dBm -0x81c 0xa43e0101 // Pin=-48dBm -0x81c 0xa3400101 // Pin=-46dBm -0x81c 0xa2420101 // Pin=-44dBm -0x81c 0x84440101 // Pin=-42dBm -0x81c 0x83460101 // Pin=-40dBm -0x81c 0x82480101 // Pin=-38dBm -0x81c 0x474a0101 // Pin=-36dBm -0x81c 0x464c0101 // Pin=-34dBm -0x81c 0x454e0101 // Pin=-32dBm -0x81c 0x44500101 // Pin=-30dBm -0x81c 0x43520101 // Pin=-28dBm -0x81c 0x25540101 // Pin=-26dBm -0x81c 0x24560101 // Pin=-24dBm -0x81c 0x23580101 // Pin=-22dBm -0x81c 0x225a0101 // Pin=-20dBm -0x81c 0x045c0101 // Pin=-18dBm -0x81c 0x035e0101 // Pin=-16dBm -0x81c 0x02600101 // Pin=-14dBm -0x81c 0x01620101 // Pin=-12dBm -0x81c 0x01640101 // Pin=-10dBm -0x81c 0x01660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xfe060001 // Pin=-104dBm +0x81c 0xfd080001 // Pin=-102dBm +0x81c 0xfc0a0001 // Pin=-100dBm +0x81c 0xfb0c0001 // Pin=-98dBm +0x81c 0xfa0e0001 // Pin=-96dBm +0x81c 0xf9100001 // Pin=-94dBm +0x81c 0xf8120001 // Pin=-92dBm +0x81c 0xf7140001 // Pin=-90dBm +0x81c 0xf6160001 // Pin=-88dBm +0x81c 0xf5180001 // Pin=-86dBm +0x81c 0xf41a0001 // Pin=-84dBm +0x81c 0xf31c0001 // Pin=-82dBm +0x81c 0xf21e0001 // Pin=-80dBm +0x81c 0xf1200001 // Pin=-78dBm +0x81c 0xef220001 // Pin=-76dBm +0x81c 0xee240001 // Pin=-74dBm +0x81c 0xed260001 // Pin=-72dBm +0x81c 0xec280001 // Pin=-70dBm +0x81c 0xeb2a0001 // Pin=-68dBm +0x81c 0xea2c0001 // Pin=-66dBm +0x81c 0xe92e0001 // Pin=-64dBm +0x81c 0xe8300001 // Pin=-62dBm +0x81c 0xe7320001 // Pin=-60dBm +0x81c 0xe6340001 // Pin=-58dBm +0x81c 0xc8360001 // Pin=-56dBm +0x81c 0xc7380001 // Pin=-54dBm +0x81c 0xc63a0001 // Pin=-52dBm +0x81c 0xc53c0001 // Pin=-50dBm +0x81c 0xc43e0001 // Pin=-48dBm +0x81c 0xc3400001 // Pin=-46dBm +0x81c 0xc2420001 // Pin=-44dBm +0x81c 0xc1440001 // Pin=-42dBm +0x81c 0xa8460001 // Pin=-40dBm +0x81c 0xa7480001 // Pin=-38dBm +0x81c 0xa64a0001 // Pin=-36dBm +0x81c 0x6a4c0001 // Pin=-34dBm +0x81c 0x694e0001 // Pin=-32dBm +0x81c 0x68500001 // Pin=-30dBm +0x81c 0x67520001 // Pin=-28dBm +0x81c 0x66540001 // Pin=-26dBm +0x81c 0x65560001 // Pin=-24dBm +0x81c 0x64580001 // Pin=-22dBm +0x81c 0x635a0001 // Pin=-20dBm +0x81c 0x475c0001 // Pin=-18dBm +0x81c 0x465e0001 // Pin=-16dBm +0x81c 0x45600001 // Pin=-14dBm +0x81c 0x44620001 // Pin=-12dBm +0x81c 0x43640001 // Pin=-10dBm +0x81c 0x42660001 // Pin=-08dBm +0x81c 0x41680001 // Pin=-06dBm +0x81c 0x416a0001 // Pin=-04dBm +0x81c 0x416c0001 // Pin=-02dBm +0x81c 0x416e0001 // Pin=-00dBm +0x81c 0x41700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfa000101 // Pin=-110dBm +0x81c 0xf9020101 // Pin=-108dBm +0x81c 0xf8040101 // Pin=-106dBm +0x81c 0xf7060101 // Pin=-104dBm +0x81c 0xf6080101 // Pin=-102dBm +0x81c 0xf50a0101 // Pin=-100dBm +0x81c 0xf40c0101 // Pin=-98dBm +0x81c 0xf30e0101 // Pin=-96dBm +0x81c 0xf2100101 // Pin=-94dBm +0x81c 0xf1120101 // Pin=-92dBm +0x81c 0xf0140101 // Pin=-90dBm +0x81c 0xef160101 // Pin=-88dBm +0x81c 0xee180101 // Pin=-86dBm +0x81c 0xed1a0101 // Pin=-84dBm +0x81c 0xec1c0101 // Pin=-82dBm +0x81c 0xeb1e0101 // Pin=-80dBm +0x81c 0xea200101 // Pin=-78dBm +0x81c 0xe9220101 // Pin=-76dBm +0x81c 0xe8240101 // Pin=-74dBm +0x81c 0xe7260101 // Pin=-72dBm +0x81c 0xe6280101 // Pin=-70dBm +0x81c 0xca2a0101 // Pin=-68dBm +0x81c 0xc92c0101 // Pin=-66dBm +0x81c 0xc82e0101 // Pin=-64dBm +0x81c 0xc7300101 // Pin=-62dBm +0x81c 0xc6320101 // Pin=-60dBm +0x81c 0xc5340101 // Pin=-58dBm +0x81c 0xc4360101 // Pin=-56dBm +0x81c 0xc3380101 // Pin=-54dBm +0x81c 0xc23a0101 // Pin=-52dBm +0x81c 0xa53c0101 // Pin=-50dBm +0x81c 0xa43e0101 // Pin=-48dBm +0x81c 0xa3400101 // Pin=-46dBm +0x81c 0xa2420101 // Pin=-44dBm +0x81c 0x84440101 // Pin=-42dBm +0x81c 0x83460101 // Pin=-40dBm +0x81c 0x82480101 // Pin=-38dBm +0x81c 0x474a0101 // Pin=-36dBm +0x81c 0x464c0101 // Pin=-34dBm +0x81c 0x454e0101 // Pin=-32dBm +0x81c 0x44500101 // Pin=-30dBm +0x81c 0x43520101 // Pin=-28dBm +0x81c 0x25540101 // Pin=-26dBm +0x81c 0x24560101 // Pin=-24dBm +0x81c 0x23580101 // Pin=-22dBm +0x81c 0x225a0101 // Pin=-20dBm +0x81c 0x045c0101 // Pin=-18dBm +0x81c 0x035e0101 // Pin=-16dBm +0x81c 0x02600101 // Pin=-14dBm +0x81c 0x01620101 // Pin=-12dBm +0x81c 0x01640101 // Pin=-10dBm +0x81c 0x01660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp.txt old mode 100755 new mode 100644 index 1f5ce9de5aa..3a807186130 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xfe020001 // Pin=-108dBm -0x81c 0xfd040001 // Pin=-106dBm -0x81c 0xfc060001 // Pin=-104dBm -0x81c 0xfb080001 // Pin=-102dBm -0x81c 0xfa0a0001 // Pin=-100dBm -0x81c 0xf90c0001 // Pin=-98dBm -0x81c 0xf80e0001 // Pin=-96dBm -0x81c 0xf7100001 // Pin=-94dBm -0x81c 0xf6120001 // Pin=-92dBm -0x81c 0xf5140001 // Pin=-90dBm -0x81c 0xf4160001 // Pin=-88dBm -0x81c 0xf3180001 // Pin=-86dBm -0x81c 0xf21a0001 // Pin=-84dBm -0x81c 0xf11c0001 // Pin=-82dBm -0x81c 0xef1e0001 // Pin=-80dBm -0x81c 0xee200001 // Pin=-78dBm -0x81c 0xed220001 // Pin=-76dBm -0x81c 0xec240001 // Pin=-74dBm -0x81c 0xeb260001 // Pin=-72dBm -0x81c 0xea280001 // Pin=-70dBm -0x81c 0xe92a0001 // Pin=-68dBm -0x81c 0xe82c0001 // Pin=-66dBm -0x81c 0xe72e0001 // Pin=-64dBm -0x81c 0xe6300001 // Pin=-62dBm -0x81c 0xe5320001 // Pin=-60dBm -0x81c 0xe4340001 // Pin=-58dBm -0x81c 0xc7360001 // Pin=-56dBm -0x81c 0xc6380001 // Pin=-54dBm -0x81c 0xc53a0001 // Pin=-52dBm -0x81c 0xc43c0001 // Pin=-50dBm -0x81c 0xc33e0001 // Pin=-48dBm -0x81c 0xa5400001 // Pin=-46dBm -0x81c 0xa4420001 // Pin=-44dBm -0x81c 0xa3440001 // Pin=-42dBm -0x81c 0xa2460001 // Pin=-40dBm -0x81c 0x88480001 // Pin=-38dBm -0x81c 0x874a0001 // Pin=-36dBm -0x81c 0x694c0001 // Pin=-34dBm -0x81c 0x684e0001 // Pin=-32dBm -0x81c 0x67500001 // Pin=-30dBm -0x81c 0x66520001 // Pin=-28dBm -0x81c 0x65540001 // Pin=-26dBm -0x81c 0x64560001 // Pin=-24dBm -0x81c 0x63580001 // Pin=-22dBm -0x81c 0x625a0001 // Pin=-20dBm -0x81c 0x455c0001 // Pin=-18dBm -0x81c 0x445e0001 // Pin=-16dBm -0x81c 0x43600001 // Pin=-14dBm -0x81c 0x42620001 // Pin=-12dBm -0x81c 0x28640001 // Pin=-10dBm -0x81c 0x27660001 // Pin=-08dBm -0x81c 0x26680001 // Pin=-06dBm -0x81c 0x256a0001 // Pin=-04dBm -0x81c 0x246c0001 // Pin=-02dBm -0x81c 0x236e0001 // Pin=-00dBm -0x81c 0x22700001 // Pin=+02dBm -0x81c 0x21720001 // Pin=+04dBm -0x81c 0x21740001 // Pin=+06dBm -0x81c 0x21760001 // Pin=+08dBm -0x81c 0x21780001 // Pin=+10dBm -0x81c 0x217a0001 // Pin=+12dBm -0x81c 0x217c0001 // Pin=+14dBm -0x81c 0x217e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xff040101 // Pin=-106dBm -0x81c 0xff060101 // Pin=-104dBm -0x81c 0xff080101 // Pin=-102dBm -0x81c 0xfe0a0101 // Pin=-100dBm -0x81c 0xfd0c0101 // Pin=-98dBm -0x81c 0xfc0e0101 // Pin=-96dBm -0x81c 0xfb100101 // Pin=-94dBm -0x81c 0xfa120101 // Pin=-92dBm -0x81c 0xf9140101 // Pin=-90dBm -0x81c 0xf8160101 // Pin=-88dBm -0x81c 0xf7180101 // Pin=-86dBm -0x81c 0xf61a0101 // Pin=-84dBm -0x81c 0xf51c0101 // Pin=-82dBm -0x81c 0xf41e0101 // Pin=-80dBm -0x81c 0xf3200101 // Pin=-78dBm -0x81c 0xf2220101 // Pin=-76dBm -0x81c 0xf1240101 // Pin=-74dBm -0x81c 0xf0260101 // Pin=-72dBm -0x81c 0xef280101 // Pin=-70dBm -0x81c 0xee2a0101 // Pin=-68dBm -0x81c 0xed2c0101 // Pin=-66dBm -0x81c 0xec2e0101 // Pin=-64dBm -0x81c 0xeb300101 // Pin=-62dBm -0x81c 0xea320101 // Pin=-60dBm -0x81c 0xe9340101 // Pin=-58dBm -0x81c 0xe8360101 // Pin=-56dBm -0x81c 0xe7380101 // Pin=-54dBm -0x81c 0xe63a0101 // Pin=-52dBm -0x81c 0xe53c0101 // Pin=-50dBm -0x81c 0xe43e0101 // Pin=-48dBm -0x81c 0xe3400101 // Pin=-46dBm -0x81c 0xe2420101 // Pin=-44dBm -0x81c 0xc6440101 // Pin=-42dBm -0x81c 0xc5460101 // Pin=-40dBm -0x81c 0xc4480101 // Pin=-38dBm -0x81c 0xc34a0101 // Pin=-36dBm -0x81c 0xc24c0101 // Pin=-34dBm -0x81c 0xa54e0101 // Pin=-32dBm -0x81c 0xa4500101 // Pin=-30dBm -0x81c 0xa3520101 // Pin=-28dBm -0x81c 0xa2540101 // Pin=-26dBm -0x81c 0x84560101 // Pin=-24dBm -0x81c 0x83580101 // Pin=-22dBm -0x81c 0x825a0101 // Pin=-20dBm -0x81c 0x475c0101 // Pin=-18dBm -0x81c 0x465e0101 // Pin=-16dBm -0x81c 0x45600101 // Pin=-14dBm -0x81c 0x44620101 // Pin=-12dBm -0x81c 0x43640101 // Pin=-10dBm -0x81c 0x25660101 // Pin=-08dBm -0x81c 0x24680101 // Pin=-06dBm -0x81c 0x236a0101 // Pin=-04dBm -0x81c 0x226c0101 // Pin=-02dBm -0x81c 0x046e0101 // Pin=-00dBm -0x81c 0x03700101 // Pin=+02dBm -0x81c 0x02720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xfe020001 // Pin=-108dBm +0x81c 0xfd040001 // Pin=-106dBm +0x81c 0xfc060001 // Pin=-104dBm +0x81c 0xfb080001 // Pin=-102dBm +0x81c 0xfa0a0001 // Pin=-100dBm +0x81c 0xf90c0001 // Pin=-98dBm +0x81c 0xf80e0001 // Pin=-96dBm +0x81c 0xf7100001 // Pin=-94dBm +0x81c 0xf6120001 // Pin=-92dBm +0x81c 0xf5140001 // Pin=-90dBm +0x81c 0xf4160001 // Pin=-88dBm +0x81c 0xf3180001 // Pin=-86dBm +0x81c 0xf21a0001 // Pin=-84dBm +0x81c 0xf11c0001 // Pin=-82dBm +0x81c 0xef1e0001 // Pin=-80dBm +0x81c 0xee200001 // Pin=-78dBm +0x81c 0xed220001 // Pin=-76dBm +0x81c 0xec240001 // Pin=-74dBm +0x81c 0xeb260001 // Pin=-72dBm +0x81c 0xea280001 // Pin=-70dBm +0x81c 0xe92a0001 // Pin=-68dBm +0x81c 0xe82c0001 // Pin=-66dBm +0x81c 0xe72e0001 // Pin=-64dBm +0x81c 0xe6300001 // Pin=-62dBm +0x81c 0xe5320001 // Pin=-60dBm +0x81c 0xe4340001 // Pin=-58dBm +0x81c 0xc7360001 // Pin=-56dBm +0x81c 0xc6380001 // Pin=-54dBm +0x81c 0xc53a0001 // Pin=-52dBm +0x81c 0xc43c0001 // Pin=-50dBm +0x81c 0xc33e0001 // Pin=-48dBm +0x81c 0xa5400001 // Pin=-46dBm +0x81c 0xa4420001 // Pin=-44dBm +0x81c 0xa3440001 // Pin=-42dBm +0x81c 0xa2460001 // Pin=-40dBm +0x81c 0x88480001 // Pin=-38dBm +0x81c 0x874a0001 // Pin=-36dBm +0x81c 0x694c0001 // Pin=-34dBm +0x81c 0x684e0001 // Pin=-32dBm +0x81c 0x67500001 // Pin=-30dBm +0x81c 0x66520001 // Pin=-28dBm +0x81c 0x65540001 // Pin=-26dBm +0x81c 0x64560001 // Pin=-24dBm +0x81c 0x63580001 // Pin=-22dBm +0x81c 0x625a0001 // Pin=-20dBm +0x81c 0x455c0001 // Pin=-18dBm +0x81c 0x445e0001 // Pin=-16dBm +0x81c 0x43600001 // Pin=-14dBm +0x81c 0x42620001 // Pin=-12dBm +0x81c 0x28640001 // Pin=-10dBm +0x81c 0x27660001 // Pin=-08dBm +0x81c 0x26680001 // Pin=-06dBm +0x81c 0x256a0001 // Pin=-04dBm +0x81c 0x246c0001 // Pin=-02dBm +0x81c 0x236e0001 // Pin=-00dBm +0x81c 0x22700001 // Pin=+02dBm +0x81c 0x21720001 // Pin=+04dBm +0x81c 0x21740001 // Pin=+06dBm +0x81c 0x21760001 // Pin=+08dBm +0x81c 0x21780001 // Pin=+10dBm +0x81c 0x217a0001 // Pin=+12dBm +0x81c 0x217c0001 // Pin=+14dBm +0x81c 0x217e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xff040101 // Pin=-106dBm +0x81c 0xff060101 // Pin=-104dBm +0x81c 0xff080101 // Pin=-102dBm +0x81c 0xfe0a0101 // Pin=-100dBm +0x81c 0xfd0c0101 // Pin=-98dBm +0x81c 0xfc0e0101 // Pin=-96dBm +0x81c 0xfb100101 // Pin=-94dBm +0x81c 0xfa120101 // Pin=-92dBm +0x81c 0xf9140101 // Pin=-90dBm +0x81c 0xf8160101 // Pin=-88dBm +0x81c 0xf7180101 // Pin=-86dBm +0x81c 0xf61a0101 // Pin=-84dBm +0x81c 0xf51c0101 // Pin=-82dBm +0x81c 0xf41e0101 // Pin=-80dBm +0x81c 0xf3200101 // Pin=-78dBm +0x81c 0xf2220101 // Pin=-76dBm +0x81c 0xf1240101 // Pin=-74dBm +0x81c 0xf0260101 // Pin=-72dBm +0x81c 0xef280101 // Pin=-70dBm +0x81c 0xee2a0101 // Pin=-68dBm +0x81c 0xed2c0101 // Pin=-66dBm +0x81c 0xec2e0101 // Pin=-64dBm +0x81c 0xeb300101 // Pin=-62dBm +0x81c 0xea320101 // Pin=-60dBm +0x81c 0xe9340101 // Pin=-58dBm +0x81c 0xe8360101 // Pin=-56dBm +0x81c 0xe7380101 // Pin=-54dBm +0x81c 0xe63a0101 // Pin=-52dBm +0x81c 0xe53c0101 // Pin=-50dBm +0x81c 0xe43e0101 // Pin=-48dBm +0x81c 0xe3400101 // Pin=-46dBm +0x81c 0xe2420101 // Pin=-44dBm +0x81c 0xc6440101 // Pin=-42dBm +0x81c 0xc5460101 // Pin=-40dBm +0x81c 0xc4480101 // Pin=-38dBm +0x81c 0xc34a0101 // Pin=-36dBm +0x81c 0xc24c0101 // Pin=-34dBm +0x81c 0xa54e0101 // Pin=-32dBm +0x81c 0xa4500101 // Pin=-30dBm +0x81c 0xa3520101 // Pin=-28dBm +0x81c 0xa2540101 // Pin=-26dBm +0x81c 0x84560101 // Pin=-24dBm +0x81c 0x83580101 // Pin=-22dBm +0x81c 0x825a0101 // Pin=-20dBm +0x81c 0x475c0101 // Pin=-18dBm +0x81c 0x465e0101 // Pin=-16dBm +0x81c 0x45600101 // Pin=-14dBm +0x81c 0x44620101 // Pin=-12dBm +0x81c 0x43640101 // Pin=-10dBm +0x81c 0x25660101 // Pin=-08dBm +0x81c 0x24680101 // Pin=-06dBm +0x81c 0x236a0101 // Pin=-04dBm +0x81c 0x226c0101 // Pin=-02dBm +0x81c 0x046e0101 // Pin=-00dBm +0x81c 0x03700101 // Pin=+02dBm +0x81c 0x02720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp_hp.txt old mode 100755 new mode 100644 index 81e3a4a6d05..f472797f264 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/AGC_TAB_8814Amp_hp.txt @@ -1,271 +1,271 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x81c 0xfe000003 // turn on the table for write data -0x81c 0xff000003 // Pin=-110dBm -0x81c 0xfe020003 // Pin=-108dBm -0x81c 0xfd040003 // Pin=-106dBm -0x81c 0xfc060003 // Pin=-104dBm -0x81c 0xfb080003 // Pin=-102dBm -0x81c 0xfa0a0003 // Pin=-100dBm -0x81c 0xf90c0003 // Pin=-98dBm -0x81c 0xf80e0003 // Pin=-96dBm -0x81c 0xf7100003 // Pin=-94dBm -0x81c 0xf6120003 // Pin=-92dBm -0x81c 0xf5140003 // Pin=-90dBm -0x81c 0xf4160003 // Pin=-88dBm -0x81c 0xf3180003 // Pin=-86dBm -0x81c 0xf21a0003 // Pin=-84dBm -0x81c 0xf11c0003 // Pin=-82dBm -0x81c 0xf01e0003 // Pin=-80dBm -0x81c 0xef200003 // Pin=-78dBm -0x81c 0xee220003 // Pin=-76dBm -0x81c 0xed240003 // Pin=-74dBm -0x81c 0xec260003 // Pin=-72dBm -0x81c 0xeb280003 // Pin=-70dBm -0x81c 0xea2a0003 // Pin=-68dBm -0x81c 0xe92c0003 // Pin=-66dBm -0x81c 0xe82e0003 // Pin=-64dBm -0x81c 0xe7300003 // Pin=-62dBm -0x81c 0xe6320003 // Pin=-60dBm -0x81c 0xe5340003 // Pin=-58dBm -0x81c 0xe4360003 // Pin=-56dBm -0x81c 0xe3380003 // Pin=-54dBm -0x81c 0xc53a0003 // Pin=-52dBm -0x81c 0xc43c0003 // Pin=-50dBm -0x81c 0xc33e0003 // Pin=-48dBm -0x81c 0xc2400003 // Pin=-46dBm -0x81c 0xc1420003 // Pin=-44dBm -0x81c 0xa8440003 // Pin=-42dBm -0x81c 0xa7460003 // Pin=-40dBm -0x81c 0xa6480003 // Pin=-38dBm -0x81c 0xa54a0003 // Pin=-36dBm -0x81c 0xa44c0003 // Pin=-34dBm -0x81c 0xa34e0003 // Pin=-32dBm -0x81c 0xa2500003 // Pin=-30dBm -0x81c 0x65520003 // Pin=-28dBm -0x81c 0x64540003 // Pin=-26dBm -0x81c 0x63560003 // Pin=-24dBm -0x81c 0x62580003 // Pin=-22dBm -0x81c 0x615a0003 // Pin=-20dBm -0x81c 0x465c0003 // Pin=-18dBm -0x81c 0x455e0003 // Pin=-16dBm -0x81c 0x44600003 // Pin=-14dBm -0x81c 0x43620003 // Pin=-12dBm -0x81c 0x42640003 // Pin=-10dBm -0x81c 0x41660003 // Pin=-08dBm -0x81c 0x41680003 // Pin=-06dBm -0x81c 0x416a0003 // Pin=-04dBm -0x81c 0x416c0003 // Pin=-02dBm -0x81c 0x416e0003 // Pin=-00dBm -0x81c 0x41700003 // Pin=+02dBm -0x81c 0x41720003 // Pin=+04dBm -0x81c 0x41740003 // Pin=+06dBm -0x81c 0x41760003 // Pin=+08dBm -0x81c 0x41780003 // Pin=+10dBm -0x81c 0x417a0003 // Pin=+12dBm -0x81c 0x417c0003 // Pin=+14dBm -0x81c 0x417e0003 // Pin=+16dBm -// AGC_TABLE 1 (5G LB) -0x81c 0xf6000103 // Pin=-110dBm -0x81c 0xf5020103 // Pin=-108dBm -0x81c 0xf4040103 // Pin=-106dBm -0x81c 0xf3060103 // Pin=-104dBm -0x81c 0xf2080103 // Pin=-102dBm -0x81c 0xf10a0103 // Pin=-100dBm -0x81c 0xf00c0103 // Pin=-98dBm -0x81c 0xef0e0103 // Pin=-96dBm -0x81c 0xee100103 // Pin=-94dBm -0x81c 0xed120103 // Pin=-92dBm -0x81c 0xec140103 // Pin=-90dBm -0x81c 0xeb160103 // Pin=-88dBm -0x81c 0xea180103 // Pin=-86dBm -0x81c 0xe91a0103 // Pin=-84dBm -0x81c 0xe81c0103 // Pin=-82dBm -0x81c 0xe71e0103 // Pin=-80dBm -0x81c 0xe6200103 // Pin=-78dBm -0x81c 0xe5220103 // Pin=-76dBm -0x81c 0xe4240103 // Pin=-74dBm -0x81c 0xe3260103 // Pin=-72dBm -0x81c 0xe2280103 // Pin=-70dBm -0x81c 0xc32a0103 // Pin=-68dBm -0x81c 0xc22c0103 // Pin=-66dBm -0x81c 0xc12e0103 // Pin=-64dBm -0x81c 0xa6300103 // Pin=-62dBm -0x81c 0xa5320103 // Pin=-60dBm -0x81c 0xa4340103 // Pin=-58dBm -0x81c 0xa3360103 // Pin=-56dBm -0x81c 0xa2380103 // Pin=-54dBm -0x81c 0xa13a0103 // Pin=-52dBm -0x81c 0x843c0103 // Pin=-50dBm -0x81c 0x833e0103 // Pin=-48dBm -0x81c 0x82400103 // Pin=-46dBm -0x81c 0x81420103 // Pin=-44dBm -0x81c 0x64440103 // Pin=-42dBm -0x81c 0x63460103 // Pin=-40dBm -0x81c 0x62480103 // Pin=-38dBm -0x81c 0x614a0103 // Pin=-36dBm -0x81c 0x444c0103 // Pin=-34dBm -0x81c 0x434e0103 // Pin=-32dBm -0x81c 0x42500103 // Pin=-30dBm -0x81c 0x41520103 // Pin=-28dBm -0x81c 0x25540103 // Pin=-26dBm -0x81c 0x24560103 // Pin=-24dBm -0x81c 0x23580103 // Pin=-22dBm -0x81c 0x225a0103 // Pin=-20dBm -0x81c 0x055c0103 // Pin=-18dBm -0x81c 0x045e0103 // Pin=-16dBm -0x81c 0x03600103 // Pin=-14dBm -0x81c 0x02620103 // Pin=-12dBm -0x81c 0x01640103 // Pin=-10dBm -0x81c 0x01660103 // Pin=-08dBm -0x81c 0x01680103 // Pin=-06dBm -0x81c 0x016a0103 // Pin=-04dBm -0x81c 0x016c0103 // Pin=-02dBm -0x81c 0x016e0103 // Pin=-00dBm -0x81c 0x01700103 // Pin=+02dBm -0x81c 0x01720103 // Pin=+04dBm -0x81c 0x01740103 // Pin=+06dBm -0x81c 0x01760103 // Pin=+08dBm -0x81c 0x01780103 // Pin=+10dBm -0x81c 0x017a0103 // Pin=+12dBm -0x81c 0x017c0103 // Pin=+14dBm -0x81c 0x017e0103 // Pin=+16dBm -// AGC_TABLE 2 (5G MB) -0x81c 0xf6000203 // Pin=-110dBm -0x81c 0xf5020203 // Pin=-108dBm -0x81c 0xf4040203 // Pin=-106dBm -0x81c 0xf3060203 // Pin=-104dBm -0x81c 0xf2080203 // Pin=-102dBm -0x81c 0xf10a0203 // Pin=-100dBm -0x81c 0xf00c0203 // Pin=-98dBm -0x81c 0xef0e0203 // Pin=-96dBm -0x81c 0xee100203 // Pin=-94dBm -0x81c 0xed120203 // Pin=-92dBm -0x81c 0xec140203 // Pin=-90dBm -0x81c 0xeb160203 // Pin=-88dBm -0x81c 0xea180203 // Pin=-86dBm -0x81c 0xe91a0203 // Pin=-84dBm -0x81c 0xe81c0203 // Pin=-82dBm -0x81c 0xe71e0203 // Pin=-80dBm -0x81c 0xe6200203 // Pin=-78dBm -0x81c 0xe5220203 // Pin=-76dBm -0x81c 0xe4240203 // Pin=-74dBm -0x81c 0xe3260203 // Pin=-72dBm -0x81c 0xe2280203 // Pin=-70dBm -0x81c 0xc32a0203 // Pin=-68dBm -0x81c 0xc22c0203 // Pin=-66dBm -0x81c 0xc12e0203 // Pin=-64dBm -0x81c 0xa6300203 // Pin=-62dBm -0x81c 0xa5320203 // Pin=-60dBm -0x81c 0xa4340203 // Pin=-58dBm -0x81c 0xa3360203 // Pin=-56dBm -0x81c 0xa2380203 // Pin=-54dBm -0x81c 0xa13a0203 // Pin=-52dBm -0x81c 0x843c0203 // Pin=-50dBm -0x81c 0x833e0203 // Pin=-48dBm -0x81c 0x82400203 // Pin=-46dBm -0x81c 0x81420203 // Pin=-44dBm -0x81c 0x64440203 // Pin=-42dBm -0x81c 0x63460203 // Pin=-40dBm -0x81c 0x62480203 // Pin=-38dBm -0x81c 0x454a0203 // Pin=-36dBm -0x81c 0x444c0203 // Pin=-34dBm -0x81c 0x434e0203 // Pin=-32dBm -0x81c 0x42500203 // Pin=-30dBm -0x81c 0x41520203 // Pin=-28dBm -0x81c 0x24540203 // Pin=-26dBm -0x81c 0x23560203 // Pin=-24dBm -0x81c 0x22580203 // Pin=-22dBm -0x81c 0x065a0203 // Pin=-20dBm -0x81c 0x055c0203 // Pin=-18dBm -0x81c 0x045e0203 // Pin=-16dBm -0x81c 0x03600203 // Pin=-14dBm -0x81c 0x02620203 // Pin=-12dBm -0x81c 0x01640203 // Pin=-10dBm -0x81c 0x01660203 // Pin=-08dBm -0x81c 0x01680203 // Pin=-06dBm -0x81c 0x016a0203 // Pin=-04dBm -0x81c 0x016c0203 // Pin=-02dBm -0x81c 0x016e0203 // Pin=-00dBm -0x81c 0x01700203 // Pin=+02dBm -0x81c 0x01720203 // Pin=+04dBm -0x81c 0x01740203 // Pin=+06dBm -0x81c 0x01760203 // Pin=+08dBm -0x81c 0x01780203 // Pin=+10dBm -0x81c 0x017a0203 // Pin=+12dBm -0x81c 0x017c0203 // Pin=+14dBm -0x81c 0x017e0203 // Pin=+16dBm -// AGC_TABLE 2 (5G HB) -0x81c 0xf5000303 // Pin=-110dBm -0x81c 0xf4020303 // Pin=-108dBm -0x81c 0xf3040303 // Pin=-106dBm -0x81c 0xf2060303 // Pin=-104dBm -0x81c 0xf1080303 // Pin=-102dBm -0x81c 0xf00a0303 // Pin=-100dBm -0x81c 0xef0c0303 // Pin=-98dBm -0x81c 0xee0e0303 // Pin=-96dBm -0x81c 0xed100303 // Pin=-94dBm -0x81c 0xec120303 // Pin=-92dBm -0x81c 0xeb140303 // Pin=-90dBm -0x81c 0xea160303 // Pin=-88dBm -0x81c 0xe9180303 // Pin=-86dBm -0x81c 0xe81a0303 // Pin=-84dBm -0x81c 0xe71c0303 // Pin=-82dBm -0x81c 0xe61e0303 // Pin=-80dBm -0x81c 0xe5200303 // Pin=-78dBm -0x81c 0xe4220303 // Pin=-76dBm -0x81c 0xe3240303 // Pin=-74dBm -0x81c 0xe2260303 // Pin=-72dBm -0x81c 0xe1280303 // Pin=-70dBm -0x81c 0xc32a0303 // Pin=-68dBm -0x81c 0xc22c0303 // Pin=-66dBm -0x81c 0xc12e0303 // Pin=-64dBm -0x81c 0xa5300303 // Pin=-62dBm -0x81c 0xa4320303 // Pin=-60dBm -0x81c 0xa3340303 // Pin=-58dBm -0x81c 0xa2360303 // Pin=-56dBm -0x81c 0xa1380303 // Pin=-54dBm -0x81c 0x843a0303 // Pin=-52dBm -0x81c 0x833c0303 // Pin=-50dBm -0x81c 0x823e0303 // Pin=-48dBm -0x81c 0x81400303 // Pin=-46dBm -0x81c 0x64420303 // Pin=-44dBm -0x81c 0x63440303 // Pin=-42dBm -0x81c 0x62460303 // Pin=-40dBm -0x81c 0x61480303 // Pin=-38dBm -0x81c 0x454a0303 // Pin=-36dBm -0x81c 0x444c0303 // Pin=-34dBm -0x81c 0x434e0303 // Pin=-32dBm -0x81c 0x42500303 // Pin=-30dBm -0x81c 0x41520303 // Pin=-28dBm -0x81c 0x24540303 // Pin=-26dBm -0x81c 0x23560303 // Pin=-24dBm -0x81c 0x22580303 // Pin=-22dBm -0x81c 0x215a0303 // Pin=-20dBm -0x81c 0x055c0303 // Pin=-18dBm -0x81c 0x045e0303 // Pin=-16dBm -0x81c 0x03600303 // Pin=-14dBm -0x81c 0x02620303 // Pin=-12dBm -0x81c 0x01640303 // Pin=-10dBm -0x81c 0x01660303 // Pin=-08dBm -0x81c 0x01680303 // Pin=-06dBm -0x81c 0x016a0303 // Pin=-04dBm -0x81c 0x016c0303 // Pin=-02dBm -0x81c 0x016e0303 // Pin=-00dBm -0x81c 0x01700303 // Pin=+02dBm -0x81c 0x01720303 // Pin=+04dBm -0x81c 0x01740303 // Pin=+06dBm -0x81c 0x01760303 // Pin=+08dBm -0x81c 0x01780303 // Pin=+10dBm -0x81c 0x017a0303 // Pin=+12dBm -0x81c 0x017c0303 // Pin=+14dBm -0x81c 0x017e0303 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x81c 0xfe000003 // turn on the table for write data +0x81c 0xff000003 // Pin=-110dBm +0x81c 0xfe020003 // Pin=-108dBm +0x81c 0xfd040003 // Pin=-106dBm +0x81c 0xfc060003 // Pin=-104dBm +0x81c 0xfb080003 // Pin=-102dBm +0x81c 0xfa0a0003 // Pin=-100dBm +0x81c 0xf90c0003 // Pin=-98dBm +0x81c 0xf80e0003 // Pin=-96dBm +0x81c 0xf7100003 // Pin=-94dBm +0x81c 0xf6120003 // Pin=-92dBm +0x81c 0xf5140003 // Pin=-90dBm +0x81c 0xf4160003 // Pin=-88dBm +0x81c 0xf3180003 // Pin=-86dBm +0x81c 0xf21a0003 // Pin=-84dBm +0x81c 0xf11c0003 // Pin=-82dBm +0x81c 0xf01e0003 // Pin=-80dBm +0x81c 0xef200003 // Pin=-78dBm +0x81c 0xee220003 // Pin=-76dBm +0x81c 0xed240003 // Pin=-74dBm +0x81c 0xec260003 // Pin=-72dBm +0x81c 0xeb280003 // Pin=-70dBm +0x81c 0xea2a0003 // Pin=-68dBm +0x81c 0xe92c0003 // Pin=-66dBm +0x81c 0xe82e0003 // Pin=-64dBm +0x81c 0xe7300003 // Pin=-62dBm +0x81c 0xe6320003 // Pin=-60dBm +0x81c 0xe5340003 // Pin=-58dBm +0x81c 0xe4360003 // Pin=-56dBm +0x81c 0xe3380003 // Pin=-54dBm +0x81c 0xc53a0003 // Pin=-52dBm +0x81c 0xc43c0003 // Pin=-50dBm +0x81c 0xc33e0003 // Pin=-48dBm +0x81c 0xc2400003 // Pin=-46dBm +0x81c 0xc1420003 // Pin=-44dBm +0x81c 0xa8440003 // Pin=-42dBm +0x81c 0xa7460003 // Pin=-40dBm +0x81c 0xa6480003 // Pin=-38dBm +0x81c 0xa54a0003 // Pin=-36dBm +0x81c 0xa44c0003 // Pin=-34dBm +0x81c 0xa34e0003 // Pin=-32dBm +0x81c 0xa2500003 // Pin=-30dBm +0x81c 0x65520003 // Pin=-28dBm +0x81c 0x64540003 // Pin=-26dBm +0x81c 0x63560003 // Pin=-24dBm +0x81c 0x62580003 // Pin=-22dBm +0x81c 0x615a0003 // Pin=-20dBm +0x81c 0x465c0003 // Pin=-18dBm +0x81c 0x455e0003 // Pin=-16dBm +0x81c 0x44600003 // Pin=-14dBm +0x81c 0x43620003 // Pin=-12dBm +0x81c 0x42640003 // Pin=-10dBm +0x81c 0x41660003 // Pin=-08dBm +0x81c 0x41680003 // Pin=-06dBm +0x81c 0x416a0003 // Pin=-04dBm +0x81c 0x416c0003 // Pin=-02dBm +0x81c 0x416e0003 // Pin=-00dBm +0x81c 0x41700003 // Pin=+02dBm +0x81c 0x41720003 // Pin=+04dBm +0x81c 0x41740003 // Pin=+06dBm +0x81c 0x41760003 // Pin=+08dBm +0x81c 0x41780003 // Pin=+10dBm +0x81c 0x417a0003 // Pin=+12dBm +0x81c 0x417c0003 // Pin=+14dBm +0x81c 0x417e0003 // Pin=+16dBm +// AGC_TABLE 1 (5G LB) +0x81c 0xf6000103 // Pin=-110dBm +0x81c 0xf5020103 // Pin=-108dBm +0x81c 0xf4040103 // Pin=-106dBm +0x81c 0xf3060103 // Pin=-104dBm +0x81c 0xf2080103 // Pin=-102dBm +0x81c 0xf10a0103 // Pin=-100dBm +0x81c 0xf00c0103 // Pin=-98dBm +0x81c 0xef0e0103 // Pin=-96dBm +0x81c 0xee100103 // Pin=-94dBm +0x81c 0xed120103 // Pin=-92dBm +0x81c 0xec140103 // Pin=-90dBm +0x81c 0xeb160103 // Pin=-88dBm +0x81c 0xea180103 // Pin=-86dBm +0x81c 0xe91a0103 // Pin=-84dBm +0x81c 0xe81c0103 // Pin=-82dBm +0x81c 0xe71e0103 // Pin=-80dBm +0x81c 0xe6200103 // Pin=-78dBm +0x81c 0xe5220103 // Pin=-76dBm +0x81c 0xe4240103 // Pin=-74dBm +0x81c 0xe3260103 // Pin=-72dBm +0x81c 0xe2280103 // Pin=-70dBm +0x81c 0xc32a0103 // Pin=-68dBm +0x81c 0xc22c0103 // Pin=-66dBm +0x81c 0xc12e0103 // Pin=-64dBm +0x81c 0xa6300103 // Pin=-62dBm +0x81c 0xa5320103 // Pin=-60dBm +0x81c 0xa4340103 // Pin=-58dBm +0x81c 0xa3360103 // Pin=-56dBm +0x81c 0xa2380103 // Pin=-54dBm +0x81c 0xa13a0103 // Pin=-52dBm +0x81c 0x843c0103 // Pin=-50dBm +0x81c 0x833e0103 // Pin=-48dBm +0x81c 0x82400103 // Pin=-46dBm +0x81c 0x81420103 // Pin=-44dBm +0x81c 0x64440103 // Pin=-42dBm +0x81c 0x63460103 // Pin=-40dBm +0x81c 0x62480103 // Pin=-38dBm +0x81c 0x614a0103 // Pin=-36dBm +0x81c 0x444c0103 // Pin=-34dBm +0x81c 0x434e0103 // Pin=-32dBm +0x81c 0x42500103 // Pin=-30dBm +0x81c 0x41520103 // Pin=-28dBm +0x81c 0x25540103 // Pin=-26dBm +0x81c 0x24560103 // Pin=-24dBm +0x81c 0x23580103 // Pin=-22dBm +0x81c 0x225a0103 // Pin=-20dBm +0x81c 0x055c0103 // Pin=-18dBm +0x81c 0x045e0103 // Pin=-16dBm +0x81c 0x03600103 // Pin=-14dBm +0x81c 0x02620103 // Pin=-12dBm +0x81c 0x01640103 // Pin=-10dBm +0x81c 0x01660103 // Pin=-08dBm +0x81c 0x01680103 // Pin=-06dBm +0x81c 0x016a0103 // Pin=-04dBm +0x81c 0x016c0103 // Pin=-02dBm +0x81c 0x016e0103 // Pin=-00dBm +0x81c 0x01700103 // Pin=+02dBm +0x81c 0x01720103 // Pin=+04dBm +0x81c 0x01740103 // Pin=+06dBm +0x81c 0x01760103 // Pin=+08dBm +0x81c 0x01780103 // Pin=+10dBm +0x81c 0x017a0103 // Pin=+12dBm +0x81c 0x017c0103 // Pin=+14dBm +0x81c 0x017e0103 // Pin=+16dBm +// AGC_TABLE 2 (5G MB) +0x81c 0xf6000203 // Pin=-110dBm +0x81c 0xf5020203 // Pin=-108dBm +0x81c 0xf4040203 // Pin=-106dBm +0x81c 0xf3060203 // Pin=-104dBm +0x81c 0xf2080203 // Pin=-102dBm +0x81c 0xf10a0203 // Pin=-100dBm +0x81c 0xf00c0203 // Pin=-98dBm +0x81c 0xef0e0203 // Pin=-96dBm +0x81c 0xee100203 // Pin=-94dBm +0x81c 0xed120203 // Pin=-92dBm +0x81c 0xec140203 // Pin=-90dBm +0x81c 0xeb160203 // Pin=-88dBm +0x81c 0xea180203 // Pin=-86dBm +0x81c 0xe91a0203 // Pin=-84dBm +0x81c 0xe81c0203 // Pin=-82dBm +0x81c 0xe71e0203 // Pin=-80dBm +0x81c 0xe6200203 // Pin=-78dBm +0x81c 0xe5220203 // Pin=-76dBm +0x81c 0xe4240203 // Pin=-74dBm +0x81c 0xe3260203 // Pin=-72dBm +0x81c 0xe2280203 // Pin=-70dBm +0x81c 0xc32a0203 // Pin=-68dBm +0x81c 0xc22c0203 // Pin=-66dBm +0x81c 0xc12e0203 // Pin=-64dBm +0x81c 0xa6300203 // Pin=-62dBm +0x81c 0xa5320203 // Pin=-60dBm +0x81c 0xa4340203 // Pin=-58dBm +0x81c 0xa3360203 // Pin=-56dBm +0x81c 0xa2380203 // Pin=-54dBm +0x81c 0xa13a0203 // Pin=-52dBm +0x81c 0x843c0203 // Pin=-50dBm +0x81c 0x833e0203 // Pin=-48dBm +0x81c 0x82400203 // Pin=-46dBm +0x81c 0x81420203 // Pin=-44dBm +0x81c 0x64440203 // Pin=-42dBm +0x81c 0x63460203 // Pin=-40dBm +0x81c 0x62480203 // Pin=-38dBm +0x81c 0x454a0203 // Pin=-36dBm +0x81c 0x444c0203 // Pin=-34dBm +0x81c 0x434e0203 // Pin=-32dBm +0x81c 0x42500203 // Pin=-30dBm +0x81c 0x41520203 // Pin=-28dBm +0x81c 0x24540203 // Pin=-26dBm +0x81c 0x23560203 // Pin=-24dBm +0x81c 0x22580203 // Pin=-22dBm +0x81c 0x065a0203 // Pin=-20dBm +0x81c 0x055c0203 // Pin=-18dBm +0x81c 0x045e0203 // Pin=-16dBm +0x81c 0x03600203 // Pin=-14dBm +0x81c 0x02620203 // Pin=-12dBm +0x81c 0x01640203 // Pin=-10dBm +0x81c 0x01660203 // Pin=-08dBm +0x81c 0x01680203 // Pin=-06dBm +0x81c 0x016a0203 // Pin=-04dBm +0x81c 0x016c0203 // Pin=-02dBm +0x81c 0x016e0203 // Pin=-00dBm +0x81c 0x01700203 // Pin=+02dBm +0x81c 0x01720203 // Pin=+04dBm +0x81c 0x01740203 // Pin=+06dBm +0x81c 0x01760203 // Pin=+08dBm +0x81c 0x01780203 // Pin=+10dBm +0x81c 0x017a0203 // Pin=+12dBm +0x81c 0x017c0203 // Pin=+14dBm +0x81c 0x017e0203 // Pin=+16dBm +// AGC_TABLE 2 (5G HB) +0x81c 0xf5000303 // Pin=-110dBm +0x81c 0xf4020303 // Pin=-108dBm +0x81c 0xf3040303 // Pin=-106dBm +0x81c 0xf2060303 // Pin=-104dBm +0x81c 0xf1080303 // Pin=-102dBm +0x81c 0xf00a0303 // Pin=-100dBm +0x81c 0xef0c0303 // Pin=-98dBm +0x81c 0xee0e0303 // Pin=-96dBm +0x81c 0xed100303 // Pin=-94dBm +0x81c 0xec120303 // Pin=-92dBm +0x81c 0xeb140303 // Pin=-90dBm +0x81c 0xea160303 // Pin=-88dBm +0x81c 0xe9180303 // Pin=-86dBm +0x81c 0xe81a0303 // Pin=-84dBm +0x81c 0xe71c0303 // Pin=-82dBm +0x81c 0xe61e0303 // Pin=-80dBm +0x81c 0xe5200303 // Pin=-78dBm +0x81c 0xe4220303 // Pin=-76dBm +0x81c 0xe3240303 // Pin=-74dBm +0x81c 0xe2260303 // Pin=-72dBm +0x81c 0xe1280303 // Pin=-70dBm +0x81c 0xc32a0303 // Pin=-68dBm +0x81c 0xc22c0303 // Pin=-66dBm +0x81c 0xc12e0303 // Pin=-64dBm +0x81c 0xa5300303 // Pin=-62dBm +0x81c 0xa4320303 // Pin=-60dBm +0x81c 0xa3340303 // Pin=-58dBm +0x81c 0xa2360303 // Pin=-56dBm +0x81c 0xa1380303 // Pin=-54dBm +0x81c 0x843a0303 // Pin=-52dBm +0x81c 0x833c0303 // Pin=-50dBm +0x81c 0x823e0303 // Pin=-48dBm +0x81c 0x81400303 // Pin=-46dBm +0x81c 0x64420303 // Pin=-44dBm +0x81c 0x63440303 // Pin=-42dBm +0x81c 0x62460303 // Pin=-40dBm +0x81c 0x61480303 // Pin=-38dBm +0x81c 0x454a0303 // Pin=-36dBm +0x81c 0x444c0303 // Pin=-34dBm +0x81c 0x434e0303 // Pin=-32dBm +0x81c 0x42500303 // Pin=-30dBm +0x81c 0x41520303 // Pin=-28dBm +0x81c 0x24540303 // Pin=-26dBm +0x81c 0x23560303 // Pin=-24dBm +0x81c 0x22580303 // Pin=-22dBm +0x81c 0x215a0303 // Pin=-20dBm +0x81c 0x055c0303 // Pin=-18dBm +0x81c 0x045e0303 // Pin=-16dBm +0x81c 0x03600303 // Pin=-14dBm +0x81c 0x02620303 // Pin=-12dBm +0x81c 0x01640303 // Pin=-10dBm +0x81c 0x01660303 // Pin=-08dBm +0x81c 0x01680303 // Pin=-06dBm +0x81c 0x016a0303 // Pin=-04dBm +0x81c 0x016c0303 // Pin=-02dBm +0x81c 0x016e0303 // Pin=-00dBm +0x81c 0x01700303 // Pin=+02dBm +0x81c 0x01720303 // Pin=+04dBm +0x81c 0x01740303 // Pin=+06dBm +0x81c 0x01760303 // Pin=+08dBm +0x81c 0x01780303 // Pin=+10dBm +0x81c 0x017a0303 // Pin=+12dBm +0x81c 0x017c0303 // Pin=+14dBm +0x81c 0x017e0303 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_high_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_high_8814A.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_high_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_high_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_low_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_low_8814A.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_low_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_low_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_normal_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_normal_8814A.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_normal_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_def_normal_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_high_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_high_8814A.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_high_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_high_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_low_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_low_8814A.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_low_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_low_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_normal_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_normal_8814A.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_normal_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_gen_normal_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_state_criteria_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_state_criteria_8814A.txt old mode 100755 new mode 100644 index 18d91fac5d0..d44bcb85c66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_state_criteria_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_state_criteria_8814A.txt @@ -1,35 +1,35 @@ -////Release version: 8881A.0820.2013 -// State: -// 1.) MACDM_TP_STATE_DEFAULT -// 2.) MACDM_TP_STATE_GENERAL -// 3.) MACDM_TP_STATE_TXOP -// So, we need four criteria -// 1.) MACDM_TP_THRS_DEF_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 2.) MACDM_TP_THRS_GEN_TO_DEF -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 3.) MACDM_TP_THRS_GEN_TO_TXOP -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 4.) MACDM_TP_THRS_TXOP_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -0x28 -0x28 -0x28 -0x1E -0x1E -0x1E -0x8C -0x8C -0x8C -0x82 -0x82 -0x82 +////Release version: 8881A.0820.2013 +// State: +// 1.) MACDM_TP_STATE_DEFAULT +// 2.) MACDM_TP_STATE_GENERAL +// 3.) MACDM_TP_STATE_TXOP +// So, we need four criteria +// 1.) MACDM_TP_THRS_DEF_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 2.) MACDM_TP_THRS_GEN_TO_DEF +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 3.) MACDM_TP_THRS_GEN_TO_TXOP +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 4.) MACDM_TP_THRS_TXOP_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +0x28 +0x28 +0x28 +0x1E +0x1E +0x1E +0x8C +0x8C +0x8C +0x82 +0x82 +0x82 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_high_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_high_8814A.txt old mode 100755 new mode 100644 index e01e46b9e5f..71936a7a338 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_high_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_high_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x0308AAAA +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x0308AAAA 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_low_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_low_8814A.txt old mode 100755 new mode 100644 index 760de6ccf1b..fd35b529ed0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_low_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_low_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03088888 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03088888 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_normal_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_normal_8814A.txt old mode 100755 new mode 100644 index 30889a39f89..0555ed20521 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_normal_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MACDM_txop_normal_8814A.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03089999 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03089999 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814A.txt old mode 100755 new mode 100644 index 0c28f4043ca..0d56ac61712 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814A.txt @@ -1,133 +1,133 @@ -0x010 0x7c // AFE power cut -0x025 0x00 // BIT_XTAL_GMN -0x073 0x10 // AFE iso -0x420 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00 //Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 //RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss -0x445 0xF0 -0x446 0x0E -0x447 0x1F -0x448 0x7C -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x0E -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x30 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x03 -0x49F 0xFE -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x01 -0x4A7 0x0E -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c7 0x80 //enable single packet ampdu -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x3F //max tx agg num =62 -0x4cb 0x3F //RTS max agg num =62 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x64 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x2a -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x64 // -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +0x010 0x7c // AFE power cut +0x025 0x00 // BIT_XTAL_GMN +0x073 0x10 // AFE iso +0x420 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00 //Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 //RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss +0x445 0xF0 +0x446 0x0E +0x447 0x1F +0x448 0x7C +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x0E +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x30 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x03 +0x49F 0xFE +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x01 +0x4A7 0x0E +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c7 0x80 //enable single packet ampdu +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x3F //max tx agg num =62 +0x4cb 0x3F //RTS max agg num =62 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x64 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x2a +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x64 // +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814Amp.txt old mode 100755 new mode 100644 index 724af22d54e..a7769b3af80 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/MAC_REG_8814Amp.txt @@ -1,135 +1,135 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x010 0x7c // AFE power cut -0x014 0xdb // sawtooth capacitor & current -0x016 0x02 -0x073 0x10 // AFE iso -0x420 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00 //Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 //RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss -0x445 0xF0 -0x446 0x0E -0x447 0x1F -0x448 0x7C -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x0E -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x30 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x03 -0x49F 0xFE -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x01 -0x4A7 0x0E -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c7 0x80 //enable single packet ampdu -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x3C // Change max tx agg num to 60 //max tx agg num =62 -0x4cb 0x3C // Change max tx agg num to 60 //max tx agg num =62 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x64 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x2a -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x64 // -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x010 0x7c // AFE power cut +0x014 0xdb // sawtooth capacitor & current +0x016 0x02 +0x073 0x10 // AFE iso +0x420 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00 //Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 //RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss +0x445 0xF0 +0x446 0x0E +0x447 0x1F +0x448 0x7C +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x0E +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x30 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x03 +0x49F 0xFE +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x01 +0x4A7 0x0E +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c7 0x80 //enable single packet ampdu +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x3C // Change max tx agg num to 60 //max tx agg num =62 +0x4cb 0x3C // Change max tx agg num to 60 //max tx agg num =62 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x64 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x2a +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x64 // +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A.txt old mode 100755 new mode 100644 index 00cea3c0827..ea89240ba15 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A.txt @@ -1,960 +1,960 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57759178 -0x830 0xb79cea8B -0x834 0x0400c486 -0x838 0x87aa4330 -0x83c 0x4799477a -0x840 0x137780e0 -0x844 0x45bcfcde -0x848 0x5cd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x00015204 -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40c4e0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80024d69 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000100 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4a0000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x06510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00798079 -0xc6c 0x00794079 -0xc70 0x80794079 -0xc74 0x80794079 -0xc78 0x80798079 -0xc7c 0x00798079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x010000dd // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x00798079 -0xe6c 0x00794079 -0xe70 0x80794079 -0xe74 0x80794079 -0xe78 0x80798079 -0xe7c 0x00798079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x010000dd // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x00798079 -0x186c 0x00794079 -0x1870 0x80794079 -0x1874 0x80794079 -0x1878 0x80798079 -0x187c 0x00798079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x010000dd // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x00798079 -0x1a6c 0x00794079 -0x1a70 0x80794079 -0x1a74 0x80794079 -0x1a78 0x80798079 -0x1a7c 0x00798079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x010000dd //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x1914 0x00030000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe2461690 -0x1b10 0x00000d46 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x00080005 -0x1b80 0x00080007 -0x1b80 0x80000015 -0x1b80 0x80000017 -0x1b80 0x00040025 -0x1b80 0x00040027 -0x1b80 0x4a000035 -0x1b80 0x4a000037 -0x1b80 0x4b040045 -0x1b80 0x4b040047 -0x1b80 0x85030055 -0x1b80 0x85030057 -0x1b80 0x40010065 -0x1b80 0x40010067 -0x1b80 0xe01b0075 -0x1b80 0xe01b0077 -0x1b80 0x00040085 -0x1b80 0x00040087 -0x1b80 0x4b050095 -0x1b80 0x4b050097 -0x1b80 0x860300a5 -0x1b80 0x860300a7 -0x1b80 0x400300b5 -0x1b80 0x400300b7 -0x1b80 0xe01b00c5 -0x1b80 0xe01b00c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x4b0600e5 -0x1b80 0x4b0600e7 -0x1b80 0x870300f5 -0x1b80 0x870300f7 -0x1b80 0x40050105 -0x1b80 0x40050107 -0x1b80 0xe01b0115 -0x1b80 0xe01b0117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4b070135 -0x1b80 0x4b070137 -0x1b80 0x88030145 -0x1b80 0x88030147 -0x1b80 0x40070155 -0x1b80 0x40070157 -0x1b80 0xe01b0165 -0x1b80 0xe01b0167 -0x1b80 0x4b000175 -0x1b80 0x4b000177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x40000195 -0x1b80 0x40000197 -0x1b80 0x300001a5 -0x1b80 0x300001a7 -0x1b80 0xf00a01b5 -0x1b80 0xf00a01b7 -0x1b80 0xf10a01c5 -0x1b80 0xf10a01c7 -0x1b80 0xf20a01d5 -0x1b80 0xf20a01d7 -0x1b80 0xf30a01e5 -0x1b80 0xf30a01e7 -0x1b80 0xf40a01f5 -0x1b80 0xf40a01f7 -0x1b80 0xf50a0205 -0x1b80 0xf50a0207 -0x1b80 0xf60a0215 -0x1b80 0xf60a0217 -0x1b80 0xfe0a0225 -0x1b80 0xfe0a0227 -0x1b80 0xff0a0235 -0x1b80 0xff0a0237 -0x1b80 0x00010245 -0x1b80 0x00010247 -0x1b80 0x302e0255 -0x1b80 0x302e0257 -0x1b80 0x30340265 -0x1b80 0x30340267 -0x1b80 0x303a0275 -0x1b80 0x303a0277 -0x1b80 0x30500285 -0x1b80 0x30500287 -0x1b80 0x303a0295 -0x1b80 0x303a0297 -0x1b80 0x303402a5 -0x1b80 0x303402a7 -0x1b80 0x303a02b5 -0x1b80 0x303a02b7 -0x1b80 0x30d002c5 -0x1b80 0x30d002c7 -0x1b80 0x30b302d5 -0x1b80 0x30b302d7 -0x1b80 0xe06602e5 -0x1b80 0xe06602e7 -0x1b80 0x580002f5 -0x1b80 0x580002f7 -0x1b80 0x5c720305 -0x1b80 0x5c720307 -0x1b80 0x63400315 -0x1b80 0x63400317 -0x1b80 0xe0750325 -0x1b80 0xe0750327 -0x1b80 0x00010335 -0x1b80 0x00010337 -0x1b80 0xe0660345 -0x1b80 0xe0660347 -0x1b80 0x5c720355 -0x1b80 0x5c720357 -0x1b80 0x63400365 -0x1b80 0x63400367 -0x1b80 0x0ba60375 -0x1b80 0x0ba60377 -0x1b80 0xe0790385 -0x1b80 0xe0790387 -0x1b80 0x00010395 -0x1b80 0x00010397 -0x1b80 0xe06603a5 -0x1b80 0xe06603a7 -0x1b80 0x580303b5 -0x1b80 0x580303b7 -0x1b80 0x5cf103c5 -0x1b80 0x5cf103c7 -0x1b80 0x4d0403d5 -0x1b80 0x4d0403d7 -0x1b80 0x000703e5 -0x1b80 0x000703e7 -0x1b80 0x640203f5 -0x1b80 0x640203f7 -0x1b80 0x2ef80405 -0x1b80 0x2ef80407 -0x1b80 0x00020415 -0x1b80 0x00020417 -0x1b80 0x23030425 -0x1b80 0x23030427 -0x1b80 0x00000435 -0x1b80 0x00000437 -0x1b80 0x23130445 -0x1b80 0x23130447 -0x1b80 0xe77f0455 -0x1b80 0xe77f0457 -0x1b80 0x232f0465 -0x1b80 0x232f0467 -0x1b80 0xe79f0475 -0x1b80 0xe79f0477 -0x1b80 0x2ef00485 -0x1b80 0x2ef00487 -0x1b80 0x00020495 -0x1b80 0x00020497 -0x1b80 0x640004a5 -0x1b80 0x640004a7 -0x1b80 0x000404b5 -0x1b80 0x000404b7 -0x1b80 0x4d0004c5 -0x1b80 0x4d0004c7 -0x1b80 0x0ba604d5 -0x1b80 0x0ba604d7 -0x1b80 0xe08304e5 -0x1b80 0xe08304e7 -0x1b80 0x000104f5 -0x1b80 0x000104f7 -0x1b80 0xe0660505 -0x1b80 0xe0660507 -0x1b80 0x5c720515 -0x1b80 0x5c720517 -0x1b80 0x4d040525 -0x1b80 0x4d040527 -0x1b80 0x00070535 -0x1b80 0x00070537 -0x1b80 0x64020545 -0x1b80 0x64020547 -0x1b80 0x2ef80555 -0x1b80 0x2ef80557 -0x1b80 0x00020565 -0x1b80 0x00020567 -0x1b80 0x23030575 -0x1b80 0x23030577 -0x1b80 0x00000585 -0x1b80 0x00000587 -0x1b80 0x23130595 -0x1b80 0x23130597 -0x1b80 0xe77f05a5 -0x1b80 0xe77f05a7 -0x1b80 0x232f05b5 -0x1b80 0x232f05b7 -0x1b80 0xe93f05c5 -0x1b80 0xe93f05c7 -0x1b80 0x2ef005d5 -0x1b80 0x2ef005d7 -0x1b80 0x000205e5 -0x1b80 0x000205e7 -0x1b80 0x640005f5 -0x1b80 0x640005f7 -0x1b80 0x00040605 -0x1b80 0x00040607 -0x1b80 0x4d000615 -0x1b80 0x4d000617 -0x1b80 0x63600625 -0x1b80 0x63600627 -0x1b80 0x0ba60635 -0x1b80 0x0ba60637 -0x1b80 0xe0790645 -0x1b80 0xe0790647 -0x1b80 0x00010655 -0x1b80 0x00010657 -0x1b80 0x00070665 -0x1b80 0x00070667 -0x1b80 0x54010675 -0x1b80 0x54010677 -0x1b80 0x00040685 -0x1b80 0x00040687 -0x1b80 0x7b200695 -0x1b80 0x7b200697 -0x1b80 0x7a0006a5 -0x1b80 0x7a0006a7 -0x1b80 0x790006b5 -0x1b80 0x790006b7 -0x1b80 0x7f2006c5 -0x1b80 0x7f2006c7 -0x1b80 0x7e0006d5 -0x1b80 0x7e0006d7 -0x1b80 0x7d0006e5 -0x1b80 0x7d0006e7 -0x1b80 0x090106f5 -0x1b80 0x090106f7 -0x1b80 0x0c010705 -0x1b80 0x0c010707 -0x1b80 0x0d020715 -0x1b80 0x0d020717 -0x1b80 0x0e040725 -0x1b80 0x0e040727 -0x1b80 0x0f080735 -0x1b80 0x0f080737 -0x1b80 0x00010745 -0x1b80 0x00010747 -0x1b80 0x74010755 -0x1b80 0x74010757 -0x1b80 0x74000765 -0x1b80 0x74000767 -0x1b80 0x8e000775 -0x1b80 0x8e000777 -0x1b80 0x00010785 -0x1b80 0x00010787 -0x1b80 0xe08c0795 -0x1b80 0xe08c0797 -0x1b80 0x548007a5 -0x1b80 0x548007a7 -0x1b80 0x580107b5 -0x1b80 0x580107b7 -0x1b80 0xe08c07c5 -0x1b80 0xe08c07c7 -0x1b80 0x548107d5 -0x1b80 0x548107d7 -0x1b80 0xe08c07e5 -0x1b80 0xe08c07e7 -0x1b80 0x548207f5 -0x1b80 0x548207f7 -0x1b80 0xe09e0805 -0x1b80 0xe09e0807 -0x1b80 0x07140815 -0x1b80 0x07140817 -0x1b80 0x00010825 -0x1b80 0x00010827 -0x1b80 0xe0950835 -0x1b80 0xe0950837 -0x1b80 0x54800845 -0x1b80 0x54800847 -0x1b80 0xe0950855 -0x1b80 0xe0950857 -0x1b80 0x54810865 -0x1b80 0x54810867 -0x1b80 0xe0950875 -0x1b80 0xe0950877 -0x1b80 0x54820885 -0x1b80 0x54820887 -0x1b80 0xe09e0895 -0x1b80 0xe09e0897 -0x1b80 0x071408a5 -0x1b80 0x071408a7 -0x1b80 0x000108b5 -0x1b80 0x000108b7 -0x1b80 0x002a08c5 -0x1b80 0x002a08c7 -0x1b80 0x740108d5 -0x1b80 0x740108d7 -0x1b80 0x740008e5 -0x1b80 0x740008e7 -0x1b80 0x8e0008f5 -0x1b80 0x8e0008f7 -0x1b80 0x30930905 -0x1b80 0x30930907 -0x1b80 0x00020915 -0x1b80 0x00020917 -0x1b80 0x30180925 -0x1b80 0x30180927 -0x1b80 0x050a0935 -0x1b80 0x050a0937 -0x1b80 0x00010945 -0x1b80 0x00010947 -0x1b80 0x002a0955 -0x1b80 0x002a0957 -0x1b80 0x74010965 -0x1b80 0x74010967 -0x1b80 0x74000975 -0x1b80 0x74000977 -0x1b80 0x8e000985 -0x1b80 0x8e000987 -0x1b80 0x309c0995 -0x1b80 0x309c0997 -0x1b80 0x000209a5 -0x1b80 0x000209a7 -0x1b80 0x301809b5 -0x1b80 0x301809b7 -0x1b80 0x050a09c5 -0x1b80 0x050a09c7 -0x1b80 0x000109d5 -0x1b80 0x000109d7 -0x1b80 0x54c009e5 -0x1b80 0x54c009e7 -0x1b80 0x54a309f5 -0x1b80 0x54a309f7 -0x1b80 0x54c10a05 -0x1b80 0x54c10a07 -0x1b80 0x54a40a15 -0x1b80 0x54a40a17 -0x1b80 0x4c830a25 -0x1b80 0x4c830a27 -0x1b80 0x4c030a35 -0x1b80 0x4c030a37 -0x1b80 0xbf0c0a45 -0x1b80 0xbf0c0a47 -0x1b80 0x54c20a55 -0x1b80 0x54c20a57 -0x1b80 0x54a40a65 -0x1b80 0x54a40a67 -0x1b80 0x4c850a75 -0x1b80 0x4c850a77 -0x1b80 0x4c050a85 -0x1b80 0x4c050a87 -0x1b80 0xbf070a95 -0x1b80 0xbf070a97 -0x1b80 0x54c10aa5 -0x1b80 0x54c10aa7 -0x1b80 0x54a30ab5 -0x1b80 0x54a30ab7 -0x1b80 0x4c860ac5 -0x1b80 0x4c860ac7 -0x1b80 0x4c060ad5 -0x1b80 0x4c060ad7 -0x1b80 0xbf020ae5 -0x1b80 0xbf020ae7 -0x1b80 0x30180af5 -0x1b80 0x30180af7 -0x1b80 0x54e50b05 -0x1b80 0x54e50b07 -0x1b80 0x050a0b15 -0x1b80 0x050a0b17 -0x1b80 0x00010b25 -0x1b80 0x00010b27 -0x1b80 0x00070b35 -0x1b80 0x00070b37 -0x1b80 0x64020b45 -0x1b80 0x64020b47 -0x1b80 0x00040b55 -0x1b80 0x00040b57 -0x1b80 0x6bc00b65 -0x1b80 0x6bc00b67 -0x1b80 0x68a00b75 -0x1b80 0x68a00b77 -0x1b80 0x67600b85 -0x1b80 0x67600b87 -0x1b80 0x66800b95 -0x1b80 0x66800b97 -0x1b80 0x65700ba5 -0x1b80 0x65700ba7 -0x1b80 0x4d040bb5 -0x1b80 0x4d040bb7 -0x1b80 0x23410bc5 -0x1b80 0x23410bc7 -0x1b80 0x01e40bd5 -0x1b80 0x01e40bd7 -0x1b80 0x23410be5 -0x1b80 0x23410be7 -0x1b80 0x11e60bf5 -0x1b80 0x11e60bf7 -0x1b80 0x23410c05 -0x1b80 0x23410c07 -0x1b80 0x21e80c15 -0x1b80 0x21e80c17 -0x1b80 0x23410c25 -0x1b80 0x23410c27 -0x1b80 0x31ea0c35 -0x1b80 0x31ea0c37 -0x1b80 0x23410c45 -0x1b80 0x23410c47 -0x1b80 0x40210c55 -0x1b80 0x40210c57 -0x1b80 0x23410c65 -0x1b80 0x23410c67 -0x1b80 0x50610c75 -0x1b80 0x50610c77 -0x1b80 0x23410c85 -0x1b80 0x23410c87 -0x1b80 0x60e10c95 -0x1b80 0x60e10c97 -0x1b80 0x23410ca5 -0x1b80 0x23410ca7 -0x1b80 0x70210cb5 -0x1b80 0x70210cb7 -0x1b80 0x4d000cc5 -0x1b80 0x4d000cc7 -0x1b80 0x00070cd5 -0x1b80 0x00070cd7 -0x1b80 0x64000ce5 -0x1b80 0x64000ce7 -0x1b80 0x00010cf5 -0x1b80 0x00010cf7 -0x1b80 0x00070d05 -0x1b80 0x00070d07 -0x1b80 0x64020d15 -0x1b80 0x64020d17 -0x1b80 0x00040d25 -0x1b80 0x00040d27 -0x1b80 0x6b400d35 -0x1b80 0x6b400d37 -0x1b80 0x68a00d45 -0x1b80 0x68a00d47 -0x1b80 0x67600d55 -0x1b80 0x67600d57 -0x1b80 0x66c00d65 -0x1b80 0x66c00d67 -0x1b80 0x65700d75 -0x1b80 0x65700d77 -0x1b80 0x4d040d85 -0x1b80 0x4d040d87 -0x1b80 0x23410d95 -0x1b80 0x23410d97 -0x1b80 0x01e30da5 -0x1b80 0x01e30da7 -0x1b80 0x23410db5 -0x1b80 0x23410db7 -0x1b80 0x11e40dc5 -0x1b80 0x11e40dc7 -0x1b80 0x23410dd5 -0x1b80 0x23410dd7 -0x1b80 0x21e50de5 -0x1b80 0x21e50de7 -0x1b80 0x23410df5 -0x1b80 0x23410df7 -0x1b80 0x31e60e05 -0x1b80 0x31e60e07 -0x1b80 0x23410e15 -0x1b80 0x23410e17 -0x1b80 0x40010e25 -0x1b80 0x40010e27 -0x1b80 0x23410e35 -0x1b80 0x23410e37 -0x1b80 0x50210e45 -0x1b80 0x50210e47 -0x1b80 0x23410e55 -0x1b80 0x23410e57 -0x1b80 0x60410e65 -0x1b80 0x60410e67 -0x1b80 0x23410e75 -0x1b80 0x23410e77 -0x1b80 0x71010e85 -0x1b80 0x71010e87 -0x1b80 0x4d000e95 -0x1b80 0x4d000e97 -0x1b80 0x00070ea5 -0x1b80 0x00070ea7 -0x1b80 0x64000eb5 -0x1b80 0x64000eb7 -0x1b80 0x00010ec5 -0x1b80 0x00010ec7 -0x1b80 0x00000006 -0x1b80 0x00000002 - +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57759178 +0x830 0xb79cea8B +0x834 0x0400c486 +0x838 0x87aa4330 +0x83c 0x4799477a +0x840 0x137780e0 +0x844 0x45bcfcde +0x848 0x5cd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x00015204 +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40c4e0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80024d69 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000100 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4a0000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x06510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00798079 +0xc6c 0x00794079 +0xc70 0x80794079 +0xc74 0x80794079 +0xc78 0x80798079 +0xc7c 0x00798079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x010000dd // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x00798079 +0xe6c 0x00794079 +0xe70 0x80794079 +0xe74 0x80794079 +0xe78 0x80798079 +0xe7c 0x00798079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x010000dd // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x00798079 +0x186c 0x00794079 +0x1870 0x80794079 +0x1874 0x80794079 +0x1878 0x80798079 +0x187c 0x00798079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x010000dd // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x00798079 +0x1a6c 0x00794079 +0x1a70 0x80794079 +0x1a74 0x80794079 +0x1a78 0x80798079 +0x1a7c 0x00798079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x010000dd //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x1914 0x00030000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe2461690 +0x1b10 0x00000d46 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x00080005 +0x1b80 0x00080007 +0x1b80 0x80000015 +0x1b80 0x80000017 +0x1b80 0x00040025 +0x1b80 0x00040027 +0x1b80 0x4a000035 +0x1b80 0x4a000037 +0x1b80 0x4b040045 +0x1b80 0x4b040047 +0x1b80 0x85030055 +0x1b80 0x85030057 +0x1b80 0x40010065 +0x1b80 0x40010067 +0x1b80 0xe01b0075 +0x1b80 0xe01b0077 +0x1b80 0x00040085 +0x1b80 0x00040087 +0x1b80 0x4b050095 +0x1b80 0x4b050097 +0x1b80 0x860300a5 +0x1b80 0x860300a7 +0x1b80 0x400300b5 +0x1b80 0x400300b7 +0x1b80 0xe01b00c5 +0x1b80 0xe01b00c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x4b0600e5 +0x1b80 0x4b0600e7 +0x1b80 0x870300f5 +0x1b80 0x870300f7 +0x1b80 0x40050105 +0x1b80 0x40050107 +0x1b80 0xe01b0115 +0x1b80 0xe01b0117 +0x1b80 0x00040125 +0x1b80 0x00040127 +0x1b80 0x4b070135 +0x1b80 0x4b070137 +0x1b80 0x88030145 +0x1b80 0x88030147 +0x1b80 0x40070155 +0x1b80 0x40070157 +0x1b80 0xe01b0165 +0x1b80 0xe01b0167 +0x1b80 0x4b000175 +0x1b80 0x4b000177 +0x1b80 0x00040185 +0x1b80 0x00040187 +0x1b80 0x40000195 +0x1b80 0x40000197 +0x1b80 0x300001a5 +0x1b80 0x300001a7 +0x1b80 0xf00a01b5 +0x1b80 0xf00a01b7 +0x1b80 0xf10a01c5 +0x1b80 0xf10a01c7 +0x1b80 0xf20a01d5 +0x1b80 0xf20a01d7 +0x1b80 0xf30a01e5 +0x1b80 0xf30a01e7 +0x1b80 0xf40a01f5 +0x1b80 0xf40a01f7 +0x1b80 0xf50a0205 +0x1b80 0xf50a0207 +0x1b80 0xf60a0215 +0x1b80 0xf60a0217 +0x1b80 0xfe0a0225 +0x1b80 0xfe0a0227 +0x1b80 0xff0a0235 +0x1b80 0xff0a0237 +0x1b80 0x00010245 +0x1b80 0x00010247 +0x1b80 0x302e0255 +0x1b80 0x302e0257 +0x1b80 0x30340265 +0x1b80 0x30340267 +0x1b80 0x303a0275 +0x1b80 0x303a0277 +0x1b80 0x30500285 +0x1b80 0x30500287 +0x1b80 0x303a0295 +0x1b80 0x303a0297 +0x1b80 0x303402a5 +0x1b80 0x303402a7 +0x1b80 0x303a02b5 +0x1b80 0x303a02b7 +0x1b80 0x30d002c5 +0x1b80 0x30d002c7 +0x1b80 0x30b302d5 +0x1b80 0x30b302d7 +0x1b80 0xe06602e5 +0x1b80 0xe06602e7 +0x1b80 0x580002f5 +0x1b80 0x580002f7 +0x1b80 0x5c720305 +0x1b80 0x5c720307 +0x1b80 0x63400315 +0x1b80 0x63400317 +0x1b80 0xe0750325 +0x1b80 0xe0750327 +0x1b80 0x00010335 +0x1b80 0x00010337 +0x1b80 0xe0660345 +0x1b80 0xe0660347 +0x1b80 0x5c720355 +0x1b80 0x5c720357 +0x1b80 0x63400365 +0x1b80 0x63400367 +0x1b80 0x0ba60375 +0x1b80 0x0ba60377 +0x1b80 0xe0790385 +0x1b80 0xe0790387 +0x1b80 0x00010395 +0x1b80 0x00010397 +0x1b80 0xe06603a5 +0x1b80 0xe06603a7 +0x1b80 0x580303b5 +0x1b80 0x580303b7 +0x1b80 0x5cf103c5 +0x1b80 0x5cf103c7 +0x1b80 0x4d0403d5 +0x1b80 0x4d0403d7 +0x1b80 0x000703e5 +0x1b80 0x000703e7 +0x1b80 0x640203f5 +0x1b80 0x640203f7 +0x1b80 0x2ef80405 +0x1b80 0x2ef80407 +0x1b80 0x00020415 +0x1b80 0x00020417 +0x1b80 0x23030425 +0x1b80 0x23030427 +0x1b80 0x00000435 +0x1b80 0x00000437 +0x1b80 0x23130445 +0x1b80 0x23130447 +0x1b80 0xe77f0455 +0x1b80 0xe77f0457 +0x1b80 0x232f0465 +0x1b80 0x232f0467 +0x1b80 0xe79f0475 +0x1b80 0xe79f0477 +0x1b80 0x2ef00485 +0x1b80 0x2ef00487 +0x1b80 0x00020495 +0x1b80 0x00020497 +0x1b80 0x640004a5 +0x1b80 0x640004a7 +0x1b80 0x000404b5 +0x1b80 0x000404b7 +0x1b80 0x4d0004c5 +0x1b80 0x4d0004c7 +0x1b80 0x0ba604d5 +0x1b80 0x0ba604d7 +0x1b80 0xe08304e5 +0x1b80 0xe08304e7 +0x1b80 0x000104f5 +0x1b80 0x000104f7 +0x1b80 0xe0660505 +0x1b80 0xe0660507 +0x1b80 0x5c720515 +0x1b80 0x5c720517 +0x1b80 0x4d040525 +0x1b80 0x4d040527 +0x1b80 0x00070535 +0x1b80 0x00070537 +0x1b80 0x64020545 +0x1b80 0x64020547 +0x1b80 0x2ef80555 +0x1b80 0x2ef80557 +0x1b80 0x00020565 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0x23410d97 +0x1b80 0x01e30da5 +0x1b80 0x01e30da7 +0x1b80 0x23410db5 +0x1b80 0x23410db7 +0x1b80 0x11e40dc5 +0x1b80 0x11e40dc7 +0x1b80 0x23410dd5 +0x1b80 0x23410dd7 +0x1b80 0x21e50de5 +0x1b80 0x21e50de7 +0x1b80 0x23410df5 +0x1b80 0x23410df7 +0x1b80 0x31e60e05 +0x1b80 0x31e60e07 +0x1b80 0x23410e15 +0x1b80 0x23410e17 +0x1b80 0x40010e25 +0x1b80 0x40010e27 +0x1b80 0x23410e35 +0x1b80 0x23410e37 +0x1b80 0x50210e45 +0x1b80 0x50210e47 +0x1b80 0x23410e55 +0x1b80 0x23410e57 +0x1b80 0x60410e65 +0x1b80 0x60410e67 +0x1b80 0x23410e75 +0x1b80 0x23410e77 +0x1b80 0x71010e85 +0x1b80 0x71010e87 +0x1b80 0x4d000e95 +0x1b80 0x4d000e97 +0x1b80 0x00070ea5 +0x1b80 0x00070ea7 +0x1b80 0x64000eb5 +0x1b80 0x64000eb7 +0x1b80 0x00010ec5 +0x1b80 0x00010ec7 +0x1b80 0x00000006 +0x1b80 0x00000002 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A_hp.txt old mode 100755 new mode 100644 index 00cea3c0827..ea89240ba15 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814A_hp.txt @@ -1,960 +1,960 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57759178 -0x830 0xb79cea8B -0x834 0x0400c486 -0x838 0x87aa4330 -0x83c 0x4799477a -0x840 0x137780e0 -0x844 0x45bcfcde -0x848 0x5cd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x00015204 -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40c4e0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80024d69 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000100 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4a0000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x06510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00798079 -0xc6c 0x00794079 -0xc70 0x80794079 -0xc74 0x80794079 -0xc78 0x80798079 -0xc7c 0x00798079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x010000dd // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x00798079 -0xe6c 0x00794079 -0xe70 0x80794079 -0xe74 0x80794079 -0xe78 0x80798079 -0xe7c 0x00798079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x010000dd // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x00798079 -0x186c 0x00794079 -0x1870 0x80794079 -0x1874 0x80794079 -0x1878 0x80798079 -0x187c 0x00798079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x010000dd // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x00798079 -0x1a6c 0x00794079 -0x1a70 0x80794079 -0x1a74 0x80794079 -0x1a78 0x80798079 -0x1a7c 0x00798079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x010000dd //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x1914 0x00030000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe2461690 -0x1b10 0x00000d46 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x00080005 -0x1b80 0x00080007 -0x1b80 0x80000015 -0x1b80 0x80000017 -0x1b80 0x00040025 -0x1b80 0x00040027 -0x1b80 0x4a000035 -0x1b80 0x4a000037 -0x1b80 0x4b040045 -0x1b80 0x4b040047 -0x1b80 0x85030055 -0x1b80 0x85030057 -0x1b80 0x40010065 -0x1b80 0x40010067 -0x1b80 0xe01b0075 -0x1b80 0xe01b0077 -0x1b80 0x00040085 -0x1b80 0x00040087 -0x1b80 0x4b050095 -0x1b80 0x4b050097 -0x1b80 0x860300a5 -0x1b80 0x860300a7 -0x1b80 0x400300b5 -0x1b80 0x400300b7 -0x1b80 0xe01b00c5 -0x1b80 0xe01b00c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x4b0600e5 -0x1b80 0x4b0600e7 -0x1b80 0x870300f5 -0x1b80 0x870300f7 -0x1b80 0x40050105 -0x1b80 0x40050107 -0x1b80 0xe01b0115 -0x1b80 0xe01b0117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4b070135 -0x1b80 0x4b070137 -0x1b80 0x88030145 -0x1b80 0x88030147 -0x1b80 0x40070155 -0x1b80 0x40070157 -0x1b80 0xe01b0165 -0x1b80 0xe01b0167 -0x1b80 0x4b000175 -0x1b80 0x4b000177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x40000195 -0x1b80 0x40000197 -0x1b80 0x300001a5 -0x1b80 0x300001a7 -0x1b80 0xf00a01b5 -0x1b80 0xf00a01b7 -0x1b80 0xf10a01c5 -0x1b80 0xf10a01c7 -0x1b80 0xf20a01d5 -0x1b80 0xf20a01d7 -0x1b80 0xf30a01e5 -0x1b80 0xf30a01e7 -0x1b80 0xf40a01f5 -0x1b80 0xf40a01f7 -0x1b80 0xf50a0205 -0x1b80 0xf50a0207 -0x1b80 0xf60a0215 -0x1b80 0xf60a0217 -0x1b80 0xfe0a0225 -0x1b80 0xfe0a0227 -0x1b80 0xff0a0235 -0x1b80 0xff0a0237 -0x1b80 0x00010245 -0x1b80 0x00010247 -0x1b80 0x302e0255 -0x1b80 0x302e0257 -0x1b80 0x30340265 -0x1b80 0x30340267 -0x1b80 0x303a0275 -0x1b80 0x303a0277 -0x1b80 0x30500285 -0x1b80 0x30500287 -0x1b80 0x303a0295 -0x1b80 0x303a0297 -0x1b80 0x303402a5 -0x1b80 0x303402a7 -0x1b80 0x303a02b5 -0x1b80 0x303a02b7 -0x1b80 0x30d002c5 -0x1b80 0x30d002c7 -0x1b80 0x30b302d5 -0x1b80 0x30b302d7 -0x1b80 0xe06602e5 -0x1b80 0xe06602e7 -0x1b80 0x580002f5 -0x1b80 0x580002f7 -0x1b80 0x5c720305 -0x1b80 0x5c720307 -0x1b80 0x63400315 -0x1b80 0x63400317 -0x1b80 0xe0750325 -0x1b80 0xe0750327 -0x1b80 0x00010335 -0x1b80 0x00010337 -0x1b80 0xe0660345 -0x1b80 0xe0660347 -0x1b80 0x5c720355 -0x1b80 0x5c720357 -0x1b80 0x63400365 -0x1b80 0x63400367 -0x1b80 0x0ba60375 -0x1b80 0x0ba60377 -0x1b80 0xe0790385 -0x1b80 0xe0790387 -0x1b80 0x00010395 -0x1b80 0x00010397 -0x1b80 0xe06603a5 -0x1b80 0xe06603a7 -0x1b80 0x580303b5 -0x1b80 0x580303b7 -0x1b80 0x5cf103c5 -0x1b80 0x5cf103c7 -0x1b80 0x4d0403d5 -0x1b80 0x4d0403d7 -0x1b80 0x000703e5 -0x1b80 0x000703e7 -0x1b80 0x640203f5 -0x1b80 0x640203f7 -0x1b80 0x2ef80405 -0x1b80 0x2ef80407 -0x1b80 0x00020415 -0x1b80 0x00020417 -0x1b80 0x23030425 -0x1b80 0x23030427 -0x1b80 0x00000435 -0x1b80 0x00000437 -0x1b80 0x23130445 -0x1b80 0x23130447 -0x1b80 0xe77f0455 -0x1b80 0xe77f0457 -0x1b80 0x232f0465 -0x1b80 0x232f0467 -0x1b80 0xe79f0475 -0x1b80 0xe79f0477 -0x1b80 0x2ef00485 -0x1b80 0x2ef00487 -0x1b80 0x00020495 -0x1b80 0x00020497 -0x1b80 0x640004a5 -0x1b80 0x640004a7 -0x1b80 0x000404b5 -0x1b80 0x000404b7 -0x1b80 0x4d0004c5 -0x1b80 0x4d0004c7 -0x1b80 0x0ba604d5 -0x1b80 0x0ba604d7 -0x1b80 0xe08304e5 -0x1b80 0xe08304e7 -0x1b80 0x000104f5 -0x1b80 0x000104f7 -0x1b80 0xe0660505 -0x1b80 0xe0660507 -0x1b80 0x5c720515 -0x1b80 0x5c720517 -0x1b80 0x4d040525 -0x1b80 0x4d040527 -0x1b80 0x00070535 -0x1b80 0x00070537 -0x1b80 0x64020545 -0x1b80 0x64020547 -0x1b80 0x2ef80555 -0x1b80 0x2ef80557 -0x1b80 0x00020565 -0x1b80 0x00020567 -0x1b80 0x23030575 -0x1b80 0x23030577 -0x1b80 0x00000585 -0x1b80 0x00000587 -0x1b80 0x23130595 -0x1b80 0x23130597 -0x1b80 0xe77f05a5 -0x1b80 0xe77f05a7 -0x1b80 0x232f05b5 -0x1b80 0x232f05b7 -0x1b80 0xe93f05c5 -0x1b80 0xe93f05c7 -0x1b80 0x2ef005d5 -0x1b80 0x2ef005d7 -0x1b80 0x000205e5 -0x1b80 0x000205e7 -0x1b80 0x640005f5 -0x1b80 0x640005f7 -0x1b80 0x00040605 -0x1b80 0x00040607 -0x1b80 0x4d000615 -0x1b80 0x4d000617 -0x1b80 0x63600625 -0x1b80 0x63600627 -0x1b80 0x0ba60635 -0x1b80 0x0ba60637 -0x1b80 0xe0790645 -0x1b80 0xe0790647 -0x1b80 0x00010655 -0x1b80 0x00010657 -0x1b80 0x00070665 -0x1b80 0x00070667 -0x1b80 0x54010675 -0x1b80 0x54010677 -0x1b80 0x00040685 -0x1b80 0x00040687 -0x1b80 0x7b200695 -0x1b80 0x7b200697 -0x1b80 0x7a0006a5 -0x1b80 0x7a0006a7 -0x1b80 0x790006b5 -0x1b80 0x790006b7 -0x1b80 0x7f2006c5 -0x1b80 0x7f2006c7 -0x1b80 0x7e0006d5 -0x1b80 0x7e0006d7 -0x1b80 0x7d0006e5 -0x1b80 0x7d0006e7 -0x1b80 0x090106f5 -0x1b80 0x090106f7 -0x1b80 0x0c010705 -0x1b80 0x0c010707 -0x1b80 0x0d020715 -0x1b80 0x0d020717 -0x1b80 0x0e040725 -0x1b80 0x0e040727 -0x1b80 0x0f080735 -0x1b80 0x0f080737 -0x1b80 0x00010745 -0x1b80 0x00010747 -0x1b80 0x74010755 -0x1b80 0x74010757 -0x1b80 0x74000765 -0x1b80 0x74000767 -0x1b80 0x8e000775 -0x1b80 0x8e000777 -0x1b80 0x00010785 -0x1b80 0x00010787 -0x1b80 0xe08c0795 -0x1b80 0xe08c0797 -0x1b80 0x548007a5 -0x1b80 0x548007a7 -0x1b80 0x580107b5 -0x1b80 0x580107b7 -0x1b80 0xe08c07c5 -0x1b80 0xe08c07c7 -0x1b80 0x548107d5 -0x1b80 0x548107d7 -0x1b80 0xe08c07e5 -0x1b80 0xe08c07e7 -0x1b80 0x548207f5 -0x1b80 0x548207f7 -0x1b80 0xe09e0805 -0x1b80 0xe09e0807 -0x1b80 0x07140815 -0x1b80 0x07140817 -0x1b80 0x00010825 -0x1b80 0x00010827 -0x1b80 0xe0950835 -0x1b80 0xe0950837 -0x1b80 0x54800845 -0x1b80 0x54800847 -0x1b80 0xe0950855 -0x1b80 0xe0950857 -0x1b80 0x54810865 -0x1b80 0x54810867 -0x1b80 0xe0950875 -0x1b80 0xe0950877 -0x1b80 0x54820885 -0x1b80 0x54820887 -0x1b80 0xe09e0895 -0x1b80 0xe09e0897 -0x1b80 0x071408a5 -0x1b80 0x071408a7 -0x1b80 0x000108b5 -0x1b80 0x000108b7 -0x1b80 0x002a08c5 -0x1b80 0x002a08c7 -0x1b80 0x740108d5 -0x1b80 0x740108d7 -0x1b80 0x740008e5 -0x1b80 0x740008e7 -0x1b80 0x8e0008f5 -0x1b80 0x8e0008f7 -0x1b80 0x30930905 -0x1b80 0x30930907 -0x1b80 0x00020915 -0x1b80 0x00020917 -0x1b80 0x30180925 -0x1b80 0x30180927 -0x1b80 0x050a0935 -0x1b80 0x050a0937 -0x1b80 0x00010945 -0x1b80 0x00010947 -0x1b80 0x002a0955 -0x1b80 0x002a0957 -0x1b80 0x74010965 -0x1b80 0x74010967 -0x1b80 0x74000975 -0x1b80 0x74000977 -0x1b80 0x8e000985 -0x1b80 0x8e000987 -0x1b80 0x309c0995 -0x1b80 0x309c0997 -0x1b80 0x000209a5 -0x1b80 0x000209a7 -0x1b80 0x301809b5 -0x1b80 0x301809b7 -0x1b80 0x050a09c5 -0x1b80 0x050a09c7 -0x1b80 0x000109d5 -0x1b80 0x000109d7 -0x1b80 0x54c009e5 -0x1b80 0x54c009e7 -0x1b80 0x54a309f5 -0x1b80 0x54a309f7 -0x1b80 0x54c10a05 -0x1b80 0x54c10a07 -0x1b80 0x54a40a15 -0x1b80 0x54a40a17 -0x1b80 0x4c830a25 -0x1b80 0x4c830a27 -0x1b80 0x4c030a35 -0x1b80 0x4c030a37 -0x1b80 0xbf0c0a45 -0x1b80 0xbf0c0a47 -0x1b80 0x54c20a55 -0x1b80 0x54c20a57 -0x1b80 0x54a40a65 -0x1b80 0x54a40a67 -0x1b80 0x4c850a75 -0x1b80 0x4c850a77 -0x1b80 0x4c050a85 -0x1b80 0x4c050a87 -0x1b80 0xbf070a95 -0x1b80 0xbf070a97 -0x1b80 0x54c10aa5 -0x1b80 0x54c10aa7 -0x1b80 0x54a30ab5 -0x1b80 0x54a30ab7 -0x1b80 0x4c860ac5 -0x1b80 0x4c860ac7 -0x1b80 0x4c060ad5 -0x1b80 0x4c060ad7 -0x1b80 0xbf020ae5 -0x1b80 0xbf020ae7 -0x1b80 0x30180af5 -0x1b80 0x30180af7 -0x1b80 0x54e50b05 -0x1b80 0x54e50b07 -0x1b80 0x050a0b15 -0x1b80 0x050a0b17 -0x1b80 0x00010b25 -0x1b80 0x00010b27 -0x1b80 0x00070b35 -0x1b80 0x00070b37 -0x1b80 0x64020b45 -0x1b80 0x64020b47 -0x1b80 0x00040b55 -0x1b80 0x00040b57 -0x1b80 0x6bc00b65 -0x1b80 0x6bc00b67 -0x1b80 0x68a00b75 -0x1b80 0x68a00b77 -0x1b80 0x67600b85 -0x1b80 0x67600b87 -0x1b80 0x66800b95 -0x1b80 0x66800b97 -0x1b80 0x65700ba5 -0x1b80 0x65700ba7 -0x1b80 0x4d040bb5 -0x1b80 0x4d040bb7 -0x1b80 0x23410bc5 -0x1b80 0x23410bc7 -0x1b80 0x01e40bd5 -0x1b80 0x01e40bd7 -0x1b80 0x23410be5 -0x1b80 0x23410be7 -0x1b80 0x11e60bf5 -0x1b80 0x11e60bf7 -0x1b80 0x23410c05 -0x1b80 0x23410c07 -0x1b80 0x21e80c15 -0x1b80 0x21e80c17 -0x1b80 0x23410c25 -0x1b80 0x23410c27 -0x1b80 0x31ea0c35 -0x1b80 0x31ea0c37 -0x1b80 0x23410c45 -0x1b80 0x23410c47 -0x1b80 0x40210c55 -0x1b80 0x40210c57 -0x1b80 0x23410c65 -0x1b80 0x23410c67 -0x1b80 0x50610c75 -0x1b80 0x50610c77 -0x1b80 0x23410c85 -0x1b80 0x23410c87 -0x1b80 0x60e10c95 -0x1b80 0x60e10c97 -0x1b80 0x23410ca5 -0x1b80 0x23410ca7 -0x1b80 0x70210cb5 -0x1b80 0x70210cb7 -0x1b80 0x4d000cc5 -0x1b80 0x4d000cc7 -0x1b80 0x00070cd5 -0x1b80 0x00070cd7 -0x1b80 0x64000ce5 -0x1b80 0x64000ce7 -0x1b80 0x00010cf5 -0x1b80 0x00010cf7 -0x1b80 0x00070d05 -0x1b80 0x00070d07 -0x1b80 0x64020d15 -0x1b80 0x64020d17 -0x1b80 0x00040d25 -0x1b80 0x00040d27 -0x1b80 0x6b400d35 -0x1b80 0x6b400d37 -0x1b80 0x68a00d45 -0x1b80 0x68a00d47 -0x1b80 0x67600d55 -0x1b80 0x67600d57 -0x1b80 0x66c00d65 -0x1b80 0x66c00d67 -0x1b80 0x65700d75 -0x1b80 0x65700d77 -0x1b80 0x4d040d85 -0x1b80 0x4d040d87 -0x1b80 0x23410d95 -0x1b80 0x23410d97 -0x1b80 0x01e30da5 -0x1b80 0x01e30da7 -0x1b80 0x23410db5 -0x1b80 0x23410db7 -0x1b80 0x11e40dc5 -0x1b80 0x11e40dc7 -0x1b80 0x23410dd5 -0x1b80 0x23410dd7 -0x1b80 0x21e50de5 -0x1b80 0x21e50de7 -0x1b80 0x23410df5 -0x1b80 0x23410df7 -0x1b80 0x31e60e05 -0x1b80 0x31e60e07 -0x1b80 0x23410e15 -0x1b80 0x23410e17 -0x1b80 0x40010e25 -0x1b80 0x40010e27 -0x1b80 0x23410e35 -0x1b80 0x23410e37 -0x1b80 0x50210e45 -0x1b80 0x50210e47 -0x1b80 0x23410e55 -0x1b80 0x23410e57 -0x1b80 0x60410e65 -0x1b80 0x60410e67 -0x1b80 0x23410e75 -0x1b80 0x23410e77 -0x1b80 0x71010e85 -0x1b80 0x71010e87 -0x1b80 0x4d000e95 -0x1b80 0x4d000e97 -0x1b80 0x00070ea5 -0x1b80 0x00070ea7 -0x1b80 0x64000eb5 -0x1b80 0x64000eb7 -0x1b80 0x00010ec5 -0x1b80 0x00010ec7 -0x1b80 0x00000006 -0x1b80 0x00000002 - +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57759178 +0x830 0xb79cea8B +0x834 0x0400c486 +0x838 0x87aa4330 +0x83c 0x4799477a +0x840 0x137780e0 +0x844 0x45bcfcde +0x848 0x5cd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x00015204 +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40c4e0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80024d69 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000100 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4a0000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x06510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00798079 +0xc6c 0x00794079 +0xc70 0x80794079 +0xc74 0x80794079 +0xc78 0x80798079 +0xc7c 0x00798079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x010000dd // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x00798079 +0xe6c 0x00794079 +0xe70 0x80794079 +0xe74 0x80794079 +0xe78 0x80798079 +0xe7c 0x00798079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x010000dd // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x00798079 +0x186c 0x00794079 +0x1870 0x80794079 +0x1874 0x80794079 +0x1878 0x80798079 +0x187c 0x00798079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x010000dd // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x00798079 +0x1a6c 0x00794079 +0x1a70 0x80794079 +0x1a74 0x80794079 +0x1a78 0x80798079 +0x1a7c 0x00798079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x010000dd //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x1914 0x00030000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe2461690 +0x1b10 0x00000d46 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x00080005 +0x1b80 0x00080007 +0x1b80 0x80000015 +0x1b80 0x80000017 +0x1b80 0x00040025 +0x1b80 0x00040027 +0x1b80 0x4a000035 +0x1b80 0x4a000037 +0x1b80 0x4b040045 +0x1b80 0x4b040047 +0x1b80 0x85030055 +0x1b80 0x85030057 +0x1b80 0x40010065 +0x1b80 0x40010067 +0x1b80 0xe01b0075 +0x1b80 0xe01b0077 +0x1b80 0x00040085 +0x1b80 0x00040087 +0x1b80 0x4b050095 +0x1b80 0x4b050097 +0x1b80 0x860300a5 +0x1b80 0x860300a7 +0x1b80 0x400300b5 +0x1b80 0x400300b7 +0x1b80 0xe01b00c5 +0x1b80 0xe01b00c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x4b0600e5 +0x1b80 0x4b0600e7 +0x1b80 0x870300f5 +0x1b80 0x870300f7 +0x1b80 0x40050105 +0x1b80 0x40050107 +0x1b80 0xe01b0115 +0x1b80 0xe01b0117 +0x1b80 0x00040125 +0x1b80 0x00040127 +0x1b80 0x4b070135 +0x1b80 0x4b070137 +0x1b80 0x88030145 +0x1b80 0x88030147 +0x1b80 0x40070155 +0x1b80 0x40070157 +0x1b80 0xe01b0165 +0x1b80 0xe01b0167 +0x1b80 0x4b000175 +0x1b80 0x4b000177 +0x1b80 0x00040185 +0x1b80 0x00040187 +0x1b80 0x40000195 +0x1b80 0x40000197 +0x1b80 0x300001a5 +0x1b80 0x300001a7 +0x1b80 0xf00a01b5 +0x1b80 0xf00a01b7 +0x1b80 0xf10a01c5 +0x1b80 0xf10a01c7 +0x1b80 0xf20a01d5 +0x1b80 0xf20a01d7 +0x1b80 0xf30a01e5 +0x1b80 0xf30a01e7 +0x1b80 0xf40a01f5 +0x1b80 0xf40a01f7 +0x1b80 0xf50a0205 +0x1b80 0xf50a0207 +0x1b80 0xf60a0215 +0x1b80 0xf60a0217 +0x1b80 0xfe0a0225 +0x1b80 0xfe0a0227 +0x1b80 0xff0a0235 +0x1b80 0xff0a0237 +0x1b80 0x00010245 +0x1b80 0x00010247 +0x1b80 0x302e0255 +0x1b80 0x302e0257 +0x1b80 0x30340265 +0x1b80 0x30340267 +0x1b80 0x303a0275 +0x1b80 0x303a0277 +0x1b80 0x30500285 +0x1b80 0x30500287 +0x1b80 0x303a0295 +0x1b80 0x303a0297 +0x1b80 0x303402a5 +0x1b80 0x303402a7 +0x1b80 0x303a02b5 +0x1b80 0x303a02b7 +0x1b80 0x30d002c5 +0x1b80 0x30d002c7 +0x1b80 0x30b302d5 +0x1b80 0x30b302d7 +0x1b80 0xe06602e5 +0x1b80 0xe06602e7 +0x1b80 0x580002f5 +0x1b80 0x580002f7 +0x1b80 0x5c720305 +0x1b80 0x5c720307 +0x1b80 0x63400315 +0x1b80 0x63400317 +0x1b80 0xe0750325 +0x1b80 0xe0750327 +0x1b80 0x00010335 +0x1b80 0x00010337 +0x1b80 0xe0660345 +0x1b80 0xe0660347 +0x1b80 0x5c720355 +0x1b80 0x5c720357 +0x1b80 0x63400365 +0x1b80 0x63400367 +0x1b80 0x0ba60375 +0x1b80 0x0ba60377 +0x1b80 0xe0790385 +0x1b80 0xe0790387 +0x1b80 0x00010395 +0x1b80 0x00010397 +0x1b80 0xe06603a5 +0x1b80 0xe06603a7 +0x1b80 0x580303b5 +0x1b80 0x580303b7 +0x1b80 0x5cf103c5 +0x1b80 0x5cf103c7 +0x1b80 0x4d0403d5 +0x1b80 0x4d0403d7 +0x1b80 0x000703e5 +0x1b80 0x000703e7 +0x1b80 0x640203f5 +0x1b80 0x640203f7 +0x1b80 0x2ef80405 +0x1b80 0x2ef80407 +0x1b80 0x00020415 +0x1b80 0x00020417 +0x1b80 0x23030425 +0x1b80 0x23030427 +0x1b80 0x00000435 +0x1b80 0x00000437 +0x1b80 0x23130445 +0x1b80 0x23130447 +0x1b80 0xe77f0455 +0x1b80 0xe77f0457 +0x1b80 0x232f0465 +0x1b80 0x232f0467 +0x1b80 0xe79f0475 +0x1b80 0xe79f0477 +0x1b80 0x2ef00485 +0x1b80 0x2ef00487 +0x1b80 0x00020495 +0x1b80 0x00020497 +0x1b80 0x640004a5 +0x1b80 0x640004a7 +0x1b80 0x000404b5 +0x1b80 0x000404b7 +0x1b80 0x4d0004c5 +0x1b80 0x4d0004c7 +0x1b80 0x0ba604d5 +0x1b80 0x0ba604d7 +0x1b80 0xe08304e5 +0x1b80 0xe08304e7 +0x1b80 0x000104f5 +0x1b80 0x000104f7 +0x1b80 0xe0660505 +0x1b80 0xe0660507 +0x1b80 0x5c720515 +0x1b80 0x5c720517 +0x1b80 0x4d040525 +0x1b80 0x4d040527 +0x1b80 0x00070535 +0x1b80 0x00070537 +0x1b80 0x64020545 +0x1b80 0x64020547 +0x1b80 0x2ef80555 +0x1b80 0x2ef80557 +0x1b80 0x00020565 +0x1b80 0x00020567 +0x1b80 0x23030575 +0x1b80 0x23030577 +0x1b80 0x00000585 +0x1b80 0x00000587 +0x1b80 0x23130595 +0x1b80 0x23130597 +0x1b80 0xe77f05a5 +0x1b80 0xe77f05a7 +0x1b80 0x232f05b5 +0x1b80 0x232f05b7 +0x1b80 0xe93f05c5 +0x1b80 0xe93f05c7 +0x1b80 0x2ef005d5 +0x1b80 0x2ef005d7 +0x1b80 0x000205e5 +0x1b80 0x000205e7 +0x1b80 0x640005f5 +0x1b80 0x640005f7 +0x1b80 0x00040605 +0x1b80 0x00040607 +0x1b80 0x4d000615 +0x1b80 0x4d000617 +0x1b80 0x63600625 +0x1b80 0x63600627 +0x1b80 0x0ba60635 +0x1b80 0x0ba60637 +0x1b80 0xe0790645 +0x1b80 0xe0790647 +0x1b80 0x00010655 +0x1b80 0x00010657 +0x1b80 0x00070665 +0x1b80 0x00070667 +0x1b80 0x54010675 +0x1b80 0x54010677 +0x1b80 0x00040685 +0x1b80 0x00040687 +0x1b80 0x7b200695 +0x1b80 0x7b200697 +0x1b80 0x7a0006a5 +0x1b80 0x7a0006a7 +0x1b80 0x790006b5 +0x1b80 0x790006b7 +0x1b80 0x7f2006c5 +0x1b80 0x7f2006c7 +0x1b80 0x7e0006d5 +0x1b80 0x7e0006d7 +0x1b80 0x7d0006e5 +0x1b80 0x7d0006e7 +0x1b80 0x090106f5 +0x1b80 0x090106f7 +0x1b80 0x0c010705 +0x1b80 0x0c010707 +0x1b80 0x0d020715 +0x1b80 0x0d020717 +0x1b80 0x0e040725 +0x1b80 0x0e040727 +0x1b80 0x0f080735 +0x1b80 0x0f080737 +0x1b80 0x00010745 +0x1b80 0x00010747 +0x1b80 0x74010755 +0x1b80 0x74010757 +0x1b80 0x74000765 +0x1b80 0x74000767 +0x1b80 0x8e000775 +0x1b80 0x8e000777 +0x1b80 0x00010785 +0x1b80 0x00010787 +0x1b80 0xe08c0795 +0x1b80 0xe08c0797 +0x1b80 0x548007a5 +0x1b80 0x548007a7 +0x1b80 0x580107b5 +0x1b80 0x580107b7 +0x1b80 0xe08c07c5 +0x1b80 0xe08c07c7 +0x1b80 0x548107d5 +0x1b80 0x548107d7 +0x1b80 0xe08c07e5 +0x1b80 0xe08c07e7 +0x1b80 0x548207f5 +0x1b80 0x548207f7 +0x1b80 0xe09e0805 +0x1b80 0xe09e0807 +0x1b80 0x07140815 +0x1b80 0x07140817 +0x1b80 0x00010825 +0x1b80 0x00010827 +0x1b80 0xe0950835 +0x1b80 0xe0950837 +0x1b80 0x54800845 +0x1b80 0x54800847 +0x1b80 0xe0950855 +0x1b80 0xe0950857 +0x1b80 0x54810865 +0x1b80 0x54810867 +0x1b80 0xe0950875 +0x1b80 0xe0950877 +0x1b80 0x54820885 +0x1b80 0x54820887 +0x1b80 0xe09e0895 +0x1b80 0xe09e0897 +0x1b80 0x071408a5 +0x1b80 0x071408a7 +0x1b80 0x000108b5 +0x1b80 0x000108b7 +0x1b80 0x002a08c5 +0x1b80 0x002a08c7 +0x1b80 0x740108d5 +0x1b80 0x740108d7 +0x1b80 0x740008e5 +0x1b80 0x740008e7 +0x1b80 0x8e0008f5 +0x1b80 0x8e0008f7 +0x1b80 0x30930905 +0x1b80 0x30930907 +0x1b80 0x00020915 +0x1b80 0x00020917 +0x1b80 0x30180925 +0x1b80 0x30180927 +0x1b80 0x050a0935 +0x1b80 0x050a0937 +0x1b80 0x00010945 +0x1b80 0x00010947 +0x1b80 0x002a0955 +0x1b80 0x002a0957 +0x1b80 0x74010965 +0x1b80 0x74010967 +0x1b80 0x74000975 +0x1b80 0x74000977 +0x1b80 0x8e000985 +0x1b80 0x8e000987 +0x1b80 0x309c0995 +0x1b80 0x309c0997 +0x1b80 0x000209a5 +0x1b80 0x000209a7 +0x1b80 0x301809b5 +0x1b80 0x301809b7 +0x1b80 0x050a09c5 +0x1b80 0x050a09c7 +0x1b80 0x000109d5 +0x1b80 0x000109d7 +0x1b80 0x54c009e5 +0x1b80 0x54c009e7 +0x1b80 0x54a309f5 +0x1b80 0x54a309f7 +0x1b80 0x54c10a05 +0x1b80 0x54c10a07 +0x1b80 0x54a40a15 +0x1b80 0x54a40a17 +0x1b80 0x4c830a25 +0x1b80 0x4c830a27 +0x1b80 0x4c030a35 +0x1b80 0x4c030a37 +0x1b80 0xbf0c0a45 +0x1b80 0xbf0c0a47 +0x1b80 0x54c20a55 +0x1b80 0x54c20a57 +0x1b80 0x54a40a65 +0x1b80 0x54a40a67 +0x1b80 0x4c850a75 +0x1b80 0x4c850a77 +0x1b80 0x4c050a85 +0x1b80 0x4c050a87 +0x1b80 0xbf070a95 +0x1b80 0xbf070a97 +0x1b80 0x54c10aa5 +0x1b80 0x54c10aa7 +0x1b80 0x54a30ab5 +0x1b80 0x54a30ab7 +0x1b80 0x4c860ac5 +0x1b80 0x4c860ac7 +0x1b80 0x4c060ad5 +0x1b80 0x4c060ad7 +0x1b80 0xbf020ae5 +0x1b80 0xbf020ae7 +0x1b80 0x30180af5 +0x1b80 0x30180af7 +0x1b80 0x54e50b05 +0x1b80 0x54e50b07 +0x1b80 0x050a0b15 +0x1b80 0x050a0b17 +0x1b80 0x00010b25 +0x1b80 0x00010b27 +0x1b80 0x00070b35 +0x1b80 0x00070b37 +0x1b80 0x64020b45 +0x1b80 0x64020b47 +0x1b80 0x00040b55 +0x1b80 0x00040b57 +0x1b80 0x6bc00b65 +0x1b80 0x6bc00b67 +0x1b80 0x68a00b75 +0x1b80 0x68a00b77 +0x1b80 0x67600b85 +0x1b80 0x67600b87 +0x1b80 0x66800b95 +0x1b80 0x66800b97 +0x1b80 0x65700ba5 +0x1b80 0x65700ba7 +0x1b80 0x4d040bb5 +0x1b80 0x4d040bb7 +0x1b80 0x23410bc5 +0x1b80 0x23410bc7 +0x1b80 0x01e40bd5 +0x1b80 0x01e40bd7 +0x1b80 0x23410be5 +0x1b80 0x23410be7 +0x1b80 0x11e60bf5 +0x1b80 0x11e60bf7 +0x1b80 0x23410c05 +0x1b80 0x23410c07 +0x1b80 0x21e80c15 +0x1b80 0x21e80c17 +0x1b80 0x23410c25 +0x1b80 0x23410c27 +0x1b80 0x31ea0c35 +0x1b80 0x31ea0c37 +0x1b80 0x23410c45 +0x1b80 0x23410c47 +0x1b80 0x40210c55 +0x1b80 0x40210c57 +0x1b80 0x23410c65 +0x1b80 0x23410c67 +0x1b80 0x50610c75 +0x1b80 0x50610c77 +0x1b80 0x23410c85 +0x1b80 0x23410c87 +0x1b80 0x60e10c95 +0x1b80 0x60e10c97 +0x1b80 0x23410ca5 +0x1b80 0x23410ca7 +0x1b80 0x70210cb5 +0x1b80 0x70210cb7 +0x1b80 0x4d000cc5 +0x1b80 0x4d000cc7 +0x1b80 0x00070cd5 +0x1b80 0x00070cd7 +0x1b80 0x64000ce5 +0x1b80 0x64000ce7 +0x1b80 0x00010cf5 +0x1b80 0x00010cf7 +0x1b80 0x00070d05 +0x1b80 0x00070d07 +0x1b80 0x64020d15 +0x1b80 0x64020d17 +0x1b80 0x00040d25 +0x1b80 0x00040d27 +0x1b80 0x6b400d35 +0x1b80 0x6b400d37 +0x1b80 0x68a00d45 +0x1b80 0x68a00d47 +0x1b80 0x67600d55 +0x1b80 0x67600d57 +0x1b80 0x66c00d65 +0x1b80 0x66c00d67 +0x1b80 0x65700d75 +0x1b80 0x65700d77 +0x1b80 0x4d040d85 +0x1b80 0x4d040d87 +0x1b80 0x23410d95 +0x1b80 0x23410d97 +0x1b80 0x01e30da5 +0x1b80 0x01e30da7 +0x1b80 0x23410db5 +0x1b80 0x23410db7 +0x1b80 0x11e40dc5 +0x1b80 0x11e40dc7 +0x1b80 0x23410dd5 +0x1b80 0x23410dd7 +0x1b80 0x21e50de5 +0x1b80 0x21e50de7 +0x1b80 0x23410df5 +0x1b80 0x23410df7 +0x1b80 0x31e60e05 +0x1b80 0x31e60e07 +0x1b80 0x23410e15 +0x1b80 0x23410e17 +0x1b80 0x40010e25 +0x1b80 0x40010e27 +0x1b80 0x23410e35 +0x1b80 0x23410e37 +0x1b80 0x50210e45 +0x1b80 0x50210e47 +0x1b80 0x23410e55 +0x1b80 0x23410e57 +0x1b80 0x60410e65 +0x1b80 0x60410e67 +0x1b80 0x23410e75 +0x1b80 0x23410e77 +0x1b80 0x71010e85 +0x1b80 0x71010e87 +0x1b80 0x4d000e95 +0x1b80 0x4d000e97 +0x1b80 0x00070ea5 +0x1b80 0x00070ea7 +0x1b80 0x64000eb5 +0x1b80 0x64000eb7 +0x1b80 0x00010ec5 +0x1b80 0x00010ec7 +0x1b80 0x00000006 +0x1b80 0x00000002 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp.txt old mode 100755 new mode 100644 index 88bfc15586e..9a3714d4b66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp.txt @@ -1,397 +1,397 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x080112e0 -0x808 0x0e028277 // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57757178 -0x830 0xa79cea8B -0x834 0x0400c485 -0x838 0x87aa4330 -0x83c 0x479747b9 -0x840 0x037750e0 -0x844 0x45bcfcde -0x848 0x5bd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x04444444 -0x874 0x31612c2e -0x878 0x00003153 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf00f000a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x27f00020 -0x8c4 0x48c00000 -0x8c8 0x80024569 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x49092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x480000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x07fd0080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -//0xb0c 0x01eaa006 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x00100000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3e020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00794079 -0xc6c 0x00798079 -0xc70 0x80798079 -0xc74 0x40798079 -0xc78 0x40794079 -0xc7c 0x00794079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x0100025c // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002915 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3e000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x80794079 -0xe6c 0x80798079 -0xe70 0x80798079 -0xe74 0x40798079 -0xe78 0x40794079 -0xe7c 0x00794079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x0100025c // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002915 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3e000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x80794079 -0x186c 0x80798079 -0x1870 0x80798079 -0x1874 0x40798079 -0x1878 0x40794079 -0x187c 0x00794079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x0100025c // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002915 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3e000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x80794079 -0x1a6c 0x80798079 -0x1a70 0x80798079 -0x1a74 0x40798079 -0x1a78 0x40794079 -0x1a7c 0x00794079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x0100025c //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002915 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x080112e0 +0x808 0x0e028277 // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57757178 +0x830 0xa79cea8B +0x834 0x0400c485 +0x838 0x87aa4330 +0x83c 0x479747b9 +0x840 0x037750e0 +0x844 0x45bcfcde +0x848 0x5bd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x0001520c +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x04444444 +0x874 0x31612c2e +0x878 0x00003153 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf00f000a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x27f00020 +0x8c4 0x48c00000 +0x8c8 0x80024569 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x49092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x480000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x07fd0080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +//0xb0c 0x01eaa006 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x00100000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3e020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00794079 +0xc6c 0x00798079 +0xc70 0x80798079 +0xc74 0x40798079 +0xc78 0x40794079 +0xc7c 0x00794079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x0100025c // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002915 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3e000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x80794079 +0xe6c 0x80798079 +0xe70 0x80798079 +0xe74 0x40798079 +0xe78 0x40794079 +0xe7c 0x00794079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x0100025c // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002915 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3e000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x80794079 +0x186c 0x80798079 +0x1870 0x80798079 +0x1874 0x40798079 +0x1878 0x40794079 +0x187c 0x00794079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x0100025c // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002915 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3e000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x80794079 +0x1a6c 0x80798079 +0x1a70 0x80798079 +0x1a74 0x40798079 +0x1a78 0x40794079 +0x1a7c 0x00794079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x0100025c //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002915 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp_hp.txt old mode 100755 new mode 100644 index a99bc5d7a3e..00993f82073 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_8814Amp_hp.txt @@ -1,1887 +1,1887 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x1000001f -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x76433170 -0x830 0x79a0ea0b -0x834 0x042E6486 -0x838 0x87aa7640 -0x83c 0x9797b9b9 -0x840 0x17575fe0 -0x844 0x4BBDFCDE -0x848 0x5cd07f8b -0x84c 0x6CFbF7B5 -0x850 0x28836706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x43642855 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40f550a // all modes use 320M ADC clk -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80025169 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400082c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00400700 -0x90c 0x0B004000 -0x910 0x0000fc00 -0x914 0xD6400404 // ADC_backoff:12.5dB_DFIR_backoff:6.5dB -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4AB0E4E4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x944 0x08000000 -0x948 0x04000000 -0x950 0x02010080 -0x954 0x86510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x98c 0x03440000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00560000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000022d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000053 -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x19800000// RX_WAIT_CCA -0xc60 0x0B800001 -0xc60 0x05800002 -0xc60 0x07800003 -0xc60 0x19800004// TX_CCK_RFON -0xc60 0x0B800005 -0xc60 0x05800006 -0xc60 0x0E800007 -0xc60 0x19800008// TX_CCK_BBON -0xc60 0x0B800009 -0xc60 0x0580000A -0xc60 0x0E80000B -0xc60 0x1980000C// TX_OFDM_RFON -0xc60 0x0B80000D -0xc60 0x0580000E -0xc60 0x0E80000F -0xc60 0x19800010// TX_OFDM_BBON -0xc60 0x0B800011 -0xc60 0x05800012 -0xc60 0x0E800013 -0xc60 0x19800014// TX_TO_RX -0xc60 0x0B800015 -0xc60 0x05800016 -0xc60 0x07800017 -0xc60 0x19800018// TX_TO_TX -0xc60 0x0B800019 -0xc60 0x0580001A -0xc60 0x0E80001B -0xc60 0x1980001C// RX_CCK -0xc60 0x0B80001D -0xc60 0x0580001E -0xc60 0x0780001F -0xc60 0x19800020// RX_OFDM -0xc60 0x0B800021 -0xc60 0x05800022 -0xc60 0x07800023 -0xc60 0x19800024// RX_WAIT_RIFS -0xc60 0x0B800025 -0xc60 0x05800026 -0xc60 0x07800027 -0xc60 0x19800028// RX_TO_RX -0xc60 0x0B800029 -0xc60 0x0580002A -0xc60 0x0780002B -//0xc60 0x1980002C // RSVD -//0xc60 0x0B80002D -//0xc60 0x0580002E -//0xc60 0x0680002F -0xc60 0x19800030 // BT or LTE coexist -0xc60 0x0B800031 -0xc60 0x05800032 -0xc60 0x00800033 -0xc60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0xc60 0x0B800035 -0xc60 0x05800036 -0xc60 0x00800037 -0xc60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0xc60 0x0B800039 -0xc60 0x0580003A -0xc60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0xc60 0x1980003C // PMPD_ANAEN -//0xc60 0x0B80003D -//0xc60 0x0580003E -//0xc60 0x0080803F -0xc94 0x01000001 -0xc98 0x00188000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x77777000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x77700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000053 -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c020c14 -0xe5c 0x00000058 -0xe60 0x19800000// RX_WAIT_CCA -0xe60 0x0B800001 -0xe60 0x05800002 -0xe60 0x07800003 -0xe60 0x19800004// TX_CCK_RFON -0xe60 0x0B800005 -0xe60 0x05800006 -0xe60 0x0E800007 -0xe60 0x19800008// TX_CCK_BBON -0xe60 0x0B800009 -0xe60 0x0580000A -0xe60 0x0E80000B -0xe60 0x1980000C// TX_OFDM_RFON -0xe60 0x0B80000D -0xe60 0x0580000E -0xe60 0x0E80000F -0xe60 0x19800010// TX_OFDM_BBON -0xe60 0x0B800011 -0xe60 0x05800012 -0xe60 0x0E800013 -0xe60 0x19800014// TX_TO_RX -0xe60 0x0B800015 -0xe60 0x05800016 -0xe60 0x07800017 -0xe60 0x19800018// TX_TO_TX -0xe60 0x0B800019 -0xe60 0x0580001A -0xe60 0x0E80001B -0xe60 0x1980001C// RX_CCK -0xe60 0x0B80001D -0xe60 0x0580001E -0xe60 0x0780001F -0xe60 0x19800020// RX_OFDM -0xe60 0x0B800021 -0xe60 0x05800022 -0xe60 0x07800023 -0xe60 0x19800024// RX_WAIT_RIFS -0xe60 0x0B800025 -0xe60 0x05800026 -0xe60 0x07800027 -0xe60 0x19800028// RX_TO_RX -0xe60 0x0B800029 -0xe60 0x0580002A -0xe60 0x0780002B -//0xe60 0x1980002C // RSVD -//0xe60 0x0B80002D -//0xe60 0x0580002E -//0xe60 0x0680002F -0xe60 0x19800030 // BT or LTE coexist -0xe60 0x0B800031 -0xe60 0x05800032 -0xe60 0x00800033 -0xe60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0xe60 0x0B800035 -0xe60 0x05800036 -0xe60 0x00800037 -0xe60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0xe60 0x0B800039 -0xe60 0x0580003A -0xe60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0xe60 0x1980003C // PMPD_ANAEN -//0xe60 0x0B80003D -//0xe60 0x0580003E -//0xe60 0x0080803F -0xe94 0x01000001 -0xe98 0x00188000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x77777000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x77700000 -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000053 -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c020c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x19800000// RX_WAIT_CCA -0x1860 0x0B800001 -0x1860 0x05800002 -0x1860 0x07800003 -0x1860 0x19800004// TX_CCK_RFON -0x1860 0x0B800005 -0x1860 0x05800006 -0x1860 0x0E800007 -0x1860 0x19800008// TX_CCK_BBON -0x1860 0x0B800009 -0x1860 0x0580000A -0x1860 0x0E80000B -0x1860 0x1980000C// TX_OFDM_RFON -0x1860 0x0B80000D -0x1860 0x0580000E -0x1860 0x0E80000F -0x1860 0x19800010// TX_OFDM_BBON -0x1860 0x0B800011 -0x1860 0x05800012 -0x1860 0x0E800013 -0x1860 0x19800014// TX_TO_RX -0x1860 0x0B800015 -0x1860 0x05800016 -0x1860 0x07800017 -0x1860 0x19800018// TX_TO_TX -0x1860 0x0B800019 -0x1860 0x0580001A -0x1860 0x0E80001B -0x1860 0x1980001C// RX_CCK -0x1860 0x0B80001D -0x1860 0x0580001E -0x1860 0x0780001F -0x1860 0x19800020// RX_OFDM -0x1860 0x0B800021 -0x1860 0x05800022 -0x1860 0x07800023 -0x1860 0x19800024// RX_WAIT_RIFS -0x1860 0x0B800025 -0x1860 0x05800026 -0x1860 0x07800027 -0x1860 0x19800028// RX_TO_RX -0x1860 0x0B800029 -0x1860 0x0580002A -0x1860 0x0780002B -//0x1860 0x1980002C // RSVD -//0x1860 0x0B80002D -//0x1860 0x0580002E -//0x1860 0x0680002F -0x1860 0x19800030 // BT or LTE coexist -0x1860 0x0B800031 -0x1860 0x05800032 -0x1860 0x00800033 -0x1860 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0x1860 0x0B800035 -0x1860 0x05800036 -0x1860 0x00800037 -0x1860 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0x1860 0x0B800039 -0x1860 0x0580003A -0x1860 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0x1860 0x1980003C // PMPD_ANAEN -//0x1860 0x0B80003D -//0x1860 0x0580003E -//0x1860 0x0080803F -0x1894 0x01000001 -0x1898 0x00188000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x77777000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x77700000 -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000053 -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c020c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x19800000// RX_WAIT_CCA -0x1a60 0x0B800001 -0x1a60 0x05800002 -0x1a60 0x07800003 -0x1a60 0x19800004// TX_CCK_RFON -0x1a60 0x0B800005 -0x1a60 0x05800006 -0x1a60 0x0E800007 -0x1a60 0x19800008// TX_CCK_BBON -0x1a60 0x0B800009 -0x1a60 0x0580000A -0x1a60 0x0E80000B -0x1a60 0x1980000C// TX_OFDM_RFON -0x1a60 0x0B80000D -0x1a60 0x0580000E -0x1a60 0x0E80000F -0x1a60 0x19800010// TX_OFDM_BBON -0x1a60 0x0B800011 -0x1a60 0x05800012 -0x1a60 0x0E800013 -0x1a60 0x19800014// TX_TO_RX -0x1a60 0x0B800015 -0x1a60 0x05800016 -0x1a60 0x07800017 -0x1a60 0x19800018// TX_TO_TX -0x1a60 0x0B800019 -0x1a60 0x0580001A -0x1a60 0x0E80001B -0x1a60 0x1980001C// RX_CCK -0x1a60 0x0B80001D -0x1a60 0x0580001E -0x1a60 0x0780001F -0x1a60 0x19800020// RX_OFDM -0x1a60 0x0B800021 -0x1a60 0x05800022 -0x1a60 0x07800023 -0x1a60 0x19800024// RX_WAIT_RIFS -0x1a60 0x0B800025 -0x1a60 0x05800026 -0x1a60 0x07800027 -0x1a60 0x19800028// RX_TO_RX -0x1a60 0x0B800029 -0x1a60 0x0580002A -0x1a60 0x0780002B -//0x1a60 0x1980002C // RSVD -//0x1a60 0x0B80002D -//0x1a60 0x0580002E -//0x1a60 0x0680002F -0x1a60 0x19800030 // BT or LTE coexist -0x1a60 0x0B800031 -0x1a60 0x05800032 -0x1a60 0x00800033 -0x1a60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep -0x1a60 0x0B800035 -0x1a60 0x05800036 -0x1a60 0x00800037 -0x1a60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby -0x1a60 0x0B800039 -0x1a60 0x0580003A -0x1a60 0x0E80803B // set [15]=1 to enable ANAPAR lookup -//0x1a60 0x1980003C // PMPD_ANAEN -//0x1a60 0x0B80003D -//0x1a60 0x0580003E -//0x1a60 0x0080803F -0x1a94 0x01000001 -0x1a98 0x00188000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x77777000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x77700000 -//======================= -// PAGE_19 : common setting -//======================= -0x1904 0x00030000 // enable IOQ_iqk_dpk -0x1914 0x00030000 -0x1984 0x03000000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x1998 0x12801000 //CCK CCK 1M -0x1998 0x12801000 //CCK CCK 1M -0x1998 0x12801001 //CCK CCK 2M -0x1998 0x12801002 //CCK CCK 5.5M -0x1998 0x12801003 //CCK CCK 11M -0x1998 0x12801004 //OFDM OFDM 6M -0x1998 0x12801005 //OFDM OFDM 9M -0x1998 0x12801006 //OFDM OFDM 12M -0x1998 0x12801007 //OFDM OFDM 18M -0x1998 0x12801008 //OFDM OFDM 24M -0x1998 0x12801009 //OFDM OFDM 36M -0x1998 0x1280100a //OFDM OFDM 48M -0x1998 0x1280100b //OFDM OFDM 54M -0x1998 0x1280100c //HT nss1 MCS0 -0x1998 0x1280100d //HT nss1 MCS1 -0x1998 0x1280100e //HT nss1 MCS2 -0x1998 0x1280100f //HT nss1 MCS3 -0x1998 0x12801010 //HT nss1 MCS4 -0x1998 0x12801011 //HT nss1 MCS5 -0x1998 0x12801012 //HT nss1 MCS6 -0x1998 0x12801013 //HT nss1 MCS7 -0x1998 0x12801014 //HT nss2 MCS8 -0x1998 0x12801015 //HT nss2 MCS9 -0x1998 0x12801016 //HT nss2 MCS10 -0x1998 0x12801017 //HT nss2 MCS11 -0x1998 0x12801018 //HT nss2 MCS12 -0x1998 0x12801019 //HT nss2 MCS13 -0x1998 0x1280101a //HT nss2 MCS14 -0x1998 0x1280101b //HT nss2 MCS15 -0x1998 0x1280101c //HT nss3 MCS16 -0x1998 0x1280101d //HT nss3 MCS17 -0x1998 0x1280101e //HT nss3 MCS18 -0x1998 0x1280101f //HT nss3 MCS19 -0x1998 0x12801020 //HT nss3 MCS20 -0x1998 0x12801021 //HT nss3 MCS21 -0x1998 0x12801022 //HT nss3 MCS22 -0x1998 0x12801023 //HT nss3 MCS23 -0x1998 0x1280102c //VHT nss1 MCS0 -0x1998 0x1280102d //VHT nss1 MCS1 -0x1998 0x1280102e //VHT nss1 MCS2 -0x1998 0x1280102f //VHT nss1 MCS3 -0x1998 0x12801030 //VHT nss1 MCS4 -0x1998 0x12801031 //VHT nss1 MCS5 -0x1998 0x12801032 //VHT nss1 MCS6 -0x1998 0x12801033 //VHT nss1 MCS7 -0x1998 0x12801034 //VHT nss1 MCS8 -0x1998 0x12801035 //VHT nss1 MCS9 -0x1998 0x12801036 //VHT nss2 MCS0 -0x1998 0x12801037 //VHT nss2 MCS1 -0x1998 0x12801038 //VHT nss2 MCS2 -0x1998 0x12801039 //VHT nss2 MCS3 -0x1998 0x1280103a //VHT nss2 MCS4 -0x1998 0x1280103b //VHT nss2 MCS5 -0x1998 0x1280103c //VHT nss2 MCS6 -0x1998 0x1280103d //VHT nss2 MCS7 -0x1998 0x1280103e //VHT nss2 MCS8 -0x1998 0x1280103f //VHT nss2 MCS9 -0x1998 0x12801040 //VHT nss3 MCS0 -0x1998 0x12801041 //VHT nss3 MCS1 -0x1998 0x12801042 //VHT nss3 MCS2 -0x1998 0x12801043 //VHT nss3 MCS3 -0x1998 0x12801044 //VHT nss3 MCS4 -0x1998 0x12801045 //VHT nss3 MCS5 -0x1998 0x12801046 //VHT nss3 MCS6 -0x1998 0x12801047 //VHT nss3 MCS7 -0x1998 0x12801048 //VHT nss3 MCS8 -0x1998 0x12801049 //VHT nss3 MCS9 -0x1998 0x12801100 //CCK CCK 1M -0x1998 0x12801101 //CCK CCK 2M -0x1998 0x12801102 //CCK CCK 5.5M -0x1998 0x12801103 //CCK CCK 11M -0x1998 0x12801104 //OFDM OFDM 6M -0x1998 0x12801105 //OFDM OFDM 9M -0x1998 0x12801106 //OFDM OFDM 12M -0x1998 0x12801107 //OFDM OFDM 18M -0x1998 0x12801108 //OFDM OFDM 24M -0x1998 0x12801109 //OFDM OFDM 36M -0x1998 0x1280110a //OFDM OFDM 48M -0x1998 0x1280110b //OFDM OFDM 54M -0x1998 0x1280110c //HT nss1 MCS0 -0x1998 0x1280110d //HT nss1 MCS1 -0x1998 0x1280110e //HT nss1 MCS2 -0x1998 0x1280110f //HT nss1 MCS3 -0x1998 0x12801110 //HT nss1 MCS4 -0x1998 0x12801111 //HT nss1 MCS5 -0x1998 0x12801112 //HT nss1 MCS6 -0x1998 0x12801113 //HT nss1 MCS7 -0x1998 0x12801114 //HT nss2 MCS8 -0x1998 0x12801115 //HT nss2 MCS9 -0x1998 0x12801116 //HT nss2 MCS10 -0x1998 0x12801117 //HT nss2 MCS11 -0x1998 0x12801118 //HT nss2 MCS12 -0x1998 0x12801119 //HT nss2 MCS13 -0x1998 0x1280111a //HT nss2 MCS14 -0x1998 0x1280111b //HT nss2 MCS15 -0x1998 0x1280111c //HT nss3 MCS16 -0x1998 0x1280111d //HT nss3 MCS17 -0x1998 0x1280111e //HT nss3 MCS18 -0x1998 0x1280111f //HT nss3 MCS19 -0x1998 0x12801120 //HT nss3 MCS20 -0x1998 0x12801121 //HT nss3 MCS21 -0x1998 0x12801122 //HT nss3 MCS22 -0x1998 0x12801123 //HT nss3 MCS23 -0x1998 0x1280112c //VHT nss1 MCS0 -0x1998 0x1280112d //VHT nss1 MCS1 -0x1998 0x1280112e //VHT nss1 MCS2 -0x1998 0x1280112f //VHT nss1 MCS3 -0x1998 0x12801130 //VHT nss1 MCS4 -0x1998 0x12801131 //VHT nss1 MCS5 -0x1998 0x12801132 //VHT nss1 MCS6 -0x1998 0x12801133 //VHT nss1 MCS7 -0x1998 0x12801134 //VHT nss1 MCS8 -0x1998 0x12801135 //VHT nss1 MCS9 -0x1998 0x12801136 //VHT nss2 MCS0 -0x1998 0x12801137 //VHT nss2 MCS1 -0x1998 0x12801138 //VHT nss2 MCS2 -0x1998 0x12801139 //VHT nss2 MCS3 -0x1998 0x1280113a //VHT nss2 MCS4 -0x1998 0x1280113b //VHT nss2 MCS5 -0x1998 0x1280113c //VHT nss2 MCS6 -0x1998 0x1280113d //VHT nss2 MCS7 -0x1998 0x1280113e //VHT nss2 MCS8 -0x1998 0x1280113f //VHT nss2 MCS9 -0x1998 0x12801140 //VHT nss3 MCS0 -0x1998 0x12801141 //VHT nss3 MCS1 -0x1998 0x12801142 //VHT nss3 MCS2 -0x1998 0x12801143 //VHT nss3 MCS3 -0x1998 0x12801144 //VHT nss3 MCS4 -0x1998 0x12801145 //VHT nss3 MCS5 -0x1998 0x12801146 //VHT nss3 MCS6 -0x1998 0x12801147 //VHT nss3 MCS7 -0x1998 0x12801148 //VHT nss3 MCS8 -0x1998 0x12801149 //VHT nss3 MCS9 -0x1998 0x12801200 //CCK CCK 1M -0x1998 0x12801201 //CCK CCK 2M -0x1998 0x12801202 //CCK CCK 5.5M -0x1998 0x12801203 //CCK CCK 11M -0x1998 0x12801204 //OFDM OFDM 6M -0x1998 0x12801205 //OFDM OFDM 9M -0x1998 0x12801206 //OFDM OFDM 12M -0x1998 0x12801207 //OFDM OFDM 18M -0x1998 0x12801208 //OFDM OFDM 24M -0x1998 0x12801209 //OFDM OFDM 36M -0x1998 0x1280120a //OFDM OFDM 48M -0x1998 0x1280120b //OFDM OFDM 54M -0x1998 0x1280120c //HT nss1 MCS0 -0x1998 0x1280120d //HT nss1 MCS1 -0x1998 0x1280120e //HT nss1 MCS2 -0x1998 0x1280120f //HT nss1 MCS3 -0x1998 0x12801210 //HT nss1 MCS4 -0x1998 0x12801211 //HT nss1 MCS5 -0x1998 0x12801212 //HT nss1 MCS6 -0x1998 0x12801213 //HT nss1 MCS7 -0x1998 0x12801214 //HT nss2 MCS8 -0x1998 0x12801215 //HT nss2 MCS9 -0x1998 0x12801216 //HT nss2 MCS10 -0x1998 0x12801217 //HT nss2 MCS11 -0x1998 0x12801218 //HT nss2 MCS12 -0x1998 0x12801219 //HT nss2 MCS13 -0x1998 0x1280121a //HT nss2 MCS14 -0x1998 0x1280121b //HT nss2 MCS15 -0x1998 0x1280121c //HT nss3 MCS16 -0x1998 0x1280121d //HT nss3 MCS17 -0x1998 0x1280121e //HT nss3 MCS18 -0x1998 0x1280121f //HT nss3 MCS19 -0x1998 0x12801220 //HT nss3 MCS20 -0x1998 0x12801221 //HT nss3 MCS21 -0x1998 0x12801222 //HT nss3 MCS22 -0x1998 0x12801223 //HT nss3 MCS23 -0x1998 0x1280122c //VHT nss1 MCS0 -0x1998 0x1280122d //VHT nss1 MCS1 -0x1998 0x1280122e //VHT nss1 MCS2 -0x1998 0x1280122f //VHT nss1 MCS3 -0x1998 0x12801230 //VHT nss1 MCS4 -0x1998 0x12801231 //VHT nss1 MCS5 -0x1998 0x12801232 //VHT nss1 MCS6 -0x1998 0x12801233 //VHT nss1 MCS7 -0x1998 0x12801234 //VHT nss1 MCS8 -0x1998 0x12801235 //VHT nss1 MCS9 -0x1998 0x12801236 //VHT nss2 MCS0 -0x1998 0x12801237 //VHT nss2 MCS1 -0x1998 0x12801238 //VHT nss2 MCS2 -0x1998 0x12801239 //VHT nss2 MCS3 -0x1998 0x1280123a //VHT nss2 MCS4 -0x1998 0x1280123b //VHT nss2 MCS5 -0x1998 0x1280123c //VHT nss2 MCS6 -0x1998 0x1280123d //VHT nss2 MCS7 -0x1998 0x1280123e //VHT nss2 MCS8 -0x1998 0x1280123f //VHT nss2 MCS9 -0x1998 0x12801240 //VHT nss3 MCS0 -0x1998 0x12801241 //VHT nss3 MCS1 -0x1998 0x12801242 //VHT nss3 MCS2 -0x1998 0x12801243 //VHT nss3 MCS3 -0x1998 0x12801244 //VHT nss3 MCS4 -0x1998 0x12801245 //VHT nss3 MCS5 -0x1998 0x12801246 //VHT nss3 MCS6 -0x1998 0x12801247 //VHT nss3 MCS7 -0x1998 0x12801248 //VHT nss3 MCS8 -0x1998 0x12801249 //VHT nss3 MCS9 -0x1998 0x12801300 //CCK CCK 1M -0x1998 0x12801301 //CCK CCK 2M -0x1998 0x12801302 //CCK CCK 5.5M -0x1998 0x12801303 //CCK CCK 11M -0x1998 0x12801304 //OFDM OFDM 6M -0x1998 0x12801305 //OFDM OFDM 9M -0x1998 0x12801306 //OFDM OFDM 12M -0x1998 0x12801307 //OFDM OFDM 18M -0x1998 0x12801308 //OFDM OFDM 24M -0x1998 0x12801309 //OFDM OFDM 36M -0x1998 0x1280130a //OFDM OFDM 48M -0x1998 0x1280130b //OFDM OFDM 54M -0x1998 0x1280130c //HT nss1 MCS0 -0x1998 0x1280130d //HT nss1 MCS1 -0x1998 0x1280130e //HT nss1 MCS2 -0x1998 0x1280130f //HT nss1 MCS3 -0x1998 0x12801310 //HT nss1 MCS4 -0x1998 0x12801311 //HT nss1 MCS5 -0x1998 0x12801312 //HT nss1 MCS6 -0x1998 0x12801313 //HT nss1 MCS7 -0x1998 0x12801314 //HT nss2 MCS8 -0x1998 0x12801315 //HT nss2 MCS9 -0x1998 0x12801316 //HT nss2 MCS10 -0x1998 0x12801317 //HT nss2 MCS11 -0x1998 0x12801318 //HT nss2 MCS12 -0x1998 0x12801319 //HT nss2 MCS13 -0x1998 0x1280131a //HT nss2 MCS14 -0x1998 0x1280131b //HT nss2 MCS15 -0x1998 0x1280131c //HT nss3 MCS16 -0x1998 0x1280131d //HT nss3 MCS17 -0x1998 0x1280131e //HT nss3 MCS18 -0x1998 0x1280131f //HT nss3 MCS19 -0x1998 0x12801320 //HT nss3 MCS20 -0x1998 0x12801321 //HT nss3 MCS21 -0x1998 0x12801322 //HT nss3 MCS22 -0x1998 0x12801323 //HT nss3 MCS23 -0x1998 0x1280132c //VHT nss1 MCS0 -0x1998 0x1280132d //VHT nss1 MCS1 -0x1998 0x1280132e //VHT nss1 MCS2 -0x1998 0x1280132f //VHT nss1 MCS3 -0x1998 0x12801330 //VHT nss1 MCS4 -0x1998 0x12801331 //VHT nss1 MCS5 -0x1998 0x12801332 //VHT nss1 MCS6 -0x1998 0x12801333 //VHT nss1 MCS7 -0x1998 0x12801334 //VHT nss1 MCS8 -0x1998 0x12801335 //VHT nss1 MCS9 -0x1998 0x12801336 //VHT nss2 MCS0 -0x1998 0x12801337 //VHT nss2 MCS1 -0x1998 0x12801338 //VHT nss2 MCS2 -0x1998 0x12801339 //VHT nss2 MCS3 -0x1998 0x1280133a //VHT nss2 MCS4 -0x1998 0x1280133b //VHT nss2 MCS5 -0x1998 0x1280133c //VHT nss2 MCS6 -0x1998 0x1280133d //VHT nss2 MCS7 -0x1998 0x1280133e //VHT nss2 MCS8 -0x1998 0x1280133f //VHT nss2 MCS9 -0x1998 0x12801340 //VHT nss3 MCS0 -0x1998 0x12801341 //VHT nss3 MCS1 -0x1998 0x12801342 //VHT nss3 MCS2 -0x1998 0x12801343 //VHT nss3 MCS3 -0x1998 0x12801344 //VHT nss3 MCS4 -0x1998 0x12801345 //VHT nss3 MCS5 -0x1998 0x12801346 //VHT nss3 MCS6 -0x1998 0x12801347 //VHT nss3 MCS7 -0x1998 0x12801348 //VHT nss3 MCS8 -0x1998 0x12801349 //VHT nss3 MCS9 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// ADC clk lock procedure -//======================= -0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) -// 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 -// 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line -// 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut - -// power_off/clk_off @ anapar_state=idle mode -0xc60 0x15808002 -0xc60 0x01808003 -0xe60 0x15808002 -0xe60 0x01808003 -0x1860 0x15808002 -0x1860 0x01808003 -0x1a60 0x15808002 -0x1a60 0x01808003 - -0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) -0xc5c 0x00080058 // [19] =1 to turn off ADC -0xe5c 0x00080058 // [19] =1 to turn off ADC -0x185c 0x00080058 // [19] =1 to turn off ADC -0x1a5c 0x00080058 // [19] =1 to turn off ADC - -// power_on/clk_off @ anapar_state=sleep mode -0xc60 0x15808036 -0xc60 0x0F808037 -0xe60 0x15808036 -0xe60 0x0F808037 -0x1860 0x15808036 -0x1860 0x0F808037 -0x1a60 0x15808036 -0x1a60 0x0F808037 - -0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) -0xc5c 0x0D000058 // [19] =0 to turn on ADC -0xe5c 0x0D000058 // [19] =0 to turn on ADC -0x185c 0x0D000058 // [19] =0 to turn on ADC -0x1a5c 0x0D000058 // [19] =0 to turn on ADC - -// power_on/clk_on @ anapar_state=idle mode -0xc60 0x05808002 -0xc60 0x0e808003 -0xe60 0x05808002 -0xe60 0x0e808003 -0x1860 0x05808002 -0x1860 0x0e808003 -0x1a60 0x05808002 -0x1a60 0x0e808003 -// recover original setting @ anapar_state=sleep mode -0xc60 0x05808036 -0xc60 0x0e808037 -0xe60 0x05808036 -0xe60 0x0e808037 -0x1860 0x05808036 -0x1860 0x0e808037 -0x1a60 0x05808036 -0x1a60 0x0e808037 - -0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) -0xb00 0xe3100000 //return true MAC - -//======================= -// PAGE_1c -//======================= -0x1c38 0x00000002 // enable IQK clk -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe24628d2 -0x1b10 0x88010d46 -0x1b14 0x00000000 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b00 0xf8015000 -0x1b00 0xf8057000 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b00 0xf8015002 -0x1b00 0xf8057002 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b00 0xf8015004 -0x1b00 0xf8057004 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b00 0xf8015006 -0x1b00 0xf8057006 -0x1b1c 0xa2147db2 -0x1b20 0x07040001 -0x1b24 0x07060807 -0x1b28 0xc0060324 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 -0x1bd4 0x00000001 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x09060005 -0x1b80 0x09060007 -0x1b80 0x0ffe0015 -0x1b80 0x0ffe0017 -0x1b80 0x00240025 -0x1b80 0x00240027 -0x1b80 0x00040035 -0x1b80 0x00040037 -0x1b80 0x05c00045 -0x1b80 0x05c00047 -0x1b80 0x00070055 -0x1b80 0x00070057 -0x1b80 0x64000065 -0x1b80 0x64000067 -0x1b80 0x00020075 -0x1b80 0x00020077 -0x1b80 0x00080085 -0x1b80 0x00080087 -0x1b80 0x80000095 -0x1b80 0x80000097 -0x1b80 0x090100a5 -0x1b80 0x090100a7 -0x1b80 0x0f0200b5 -0x1b80 0x0f0200b7 -0x1b80 0x002400c5 -0x1b80 0x002400c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x05c000e5 -0x1b80 0x05c000e7 -0x1b80 0x000700f5 -0x1b80 0x000700f7 -0x1b80 0x64020105 -0x1b80 0x64020107 -0x1b80 0x00020115 -0x1b80 0x00020117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4a000135 -0x1b80 0x4a000137 -0x1b80 0x4b040145 -0x1b80 0x4b040147 -0x1b80 0x85030155 -0x1b80 0x85030157 -0x1b80 0x40010165 -0x1b80 0x40010167 -0x1b80 0xe0290175 -0x1b80 0xe0290177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x4b050195 -0x1b80 0x4b050197 -0x1b80 0x860301a5 -0x1b80 0x860301a7 -0x1b80 0x400301b5 -0x1b80 0x400301b7 -0x1b80 0xe02901c5 -0x1b80 0xe02901c7 -0x1b80 0x000401d5 -0x1b80 0x000401d7 -0x1b80 0x4b0601e5 -0x1b80 0x4b0601e7 -0x1b80 0x870301f5 -0x1b80 0x870301f7 -0x1b80 0x40050205 -0x1b80 0x40050207 -0x1b80 0xe0290215 -0x1b80 0xe0290217 -0x1b80 0x00040225 -0x1b80 0x00040227 -0x1b80 0x4b070235 -0x1b80 0x4b070237 -0x1b80 0x88030245 -0x1b80 0x88030247 -0x1b80 0x40070255 -0x1b80 0x40070257 -0x1b80 0xe0290265 -0x1b80 0xe0290267 -0x1b80 0x4b000275 -0x1b80 0x4b000277 -0x1b80 0x30000285 -0x1b80 0x30000287 -0x1b80 0xa40a0295 -0x1b80 0xa40a0297 -0x1b80 0xe17602a5 -0x1b80 0xe17602a7 -0x1b80 0xf00e02b5 -0x1b80 0xf00e02b7 -0x1b80 0xf10e02c5 -0x1b80 0xf10e02c7 -0x1b80 0xf20e02d5 -0x1b80 0xf20e02d7 -0x1b80 0xf30e02e5 -0x1b80 0xf30e02e7 -0x1b80 0xf40d02f5 -0x1b80 0xf40d02f7 -0x1b80 0xf50c0305 -0x1b80 0xf50c0307 -0x1b80 0xf60c0315 -0x1b80 0xf60c0317 -0x1b80 0xf70b0325 -0x1b80 0xf70b0327 -0x1b80 0xf8060335 -0x1b80 0xf8060337 -0x1b80 0xf9060345 -0x1b80 0xf9060347 -0x1b80 0xfa090355 -0x1b80 0xfa090357 -0x1b80 0xfe090365 -0x1b80 0xfe090367 -0x1b80 0xff090375 -0x1b80 0xff090377 -0x1b80 0x00010385 -0x1b80 0x00010387 -0x1b80 0x30410395 -0x1b80 0x30410397 -0x1b80 0x305403a5 -0x1b80 0x305403a7 -0x1b80 0x306003b5 -0x1b80 0x306003b7 -0x1b80 0x305403c5 -0x1b80 0x305403c7 -0x1b80 0x306d03d5 -0x1b80 0x306d03d7 -0x1b80 0x306703e5 -0x1b80 0x306703e7 -0x1b80 0x31be03f5 -0x1b80 0x31be03f7 -0x1b80 0x31af0405 -0x1b80 0x31af0407 -0x1b80 0xe1110415 -0x1b80 0xe1110417 -0x1b80 0x4d040425 -0x1b80 0x4d040427 -0x1b80 0x20800435 -0x1b80 0x20800437 -0x1b80 0x00000445 -0x1b80 0x00000447 -0x1b80 0x4d000455 -0x1b80 0x4d000457 -0x1b80 0x55070465 -0x1b80 0x55070467 -0x1b80 0xe1110475 -0x1b80 0xe1110477 -0x1b80 0x4d040485 -0x1b80 0x4d040487 -0x1b80 0x20800495 -0x1b80 0x20800497 -0x1b80 0x840004a5 -0x1b80 0x840004a7 -0x1b80 0x4d0004b5 -0x1b80 0x4d0004b7 -0x1b80 0x550f04c5 -0x1b80 0x550f04c7 -0x1b80 0xe11104d5 -0x1b80 0xe11104d7 -0x1b80 0x4f0204e5 -0x1b80 0x4f0204e7 -0x1b80 0x4e0004f5 -0x1b80 0x4e0004f7 -0x1b80 0x53020505 -0x1b80 0x53020507 -0x1b80 0x52010515 -0x1b80 0x52010517 -0x1b80 0xe1150525 -0x1b80 0xe1150527 -0x1b80 0x00010535 -0x1b80 0x00010537 -0x1b80 0x5c720545 -0x1b80 0x5c720547 -0x1b80 0xe1200555 -0x1b80 0xe1200557 -0x1b80 0x54e50565 -0x1b80 0x54e50567 -0x1b80 0x54bf0575 -0x1b80 0x54bf0577 -0x1b80 0x54c50585 -0x1b80 0x54c50587 -0x1b80 0x54be0595 -0x1b80 0x54be0597 -0x1b80 0x54df05a5 -0x1b80 0x54df05a7 -0x1b80 0x0ba605b5 -0x1b80 0x0ba605b7 -0x1b80 0xf31a05c5 -0x1b80 0xf31a05c7 -0x1b80 0xf42f05d5 -0x1b80 0xf42f05d7 -0x1b80 0xf54c05e5 -0x1b80 0xf54c05e7 -0x1b80 0x000105f5 -0x1b80 0x000105f7 -0x1b80 0x62060605 -0x1b80 0x62060607 -0x1b80 0x60060615 -0x1b80 0x60060617 -0x1b80 0xe1950625 -0x1b80 0xe1950627 -0x1b80 0x0c000635 -0x1b80 0x0c000637 -0x1b80 0x5c720645 -0x1b80 0x5c720647 -0x1b80 0xe1200655 -0x1b80 0xe1200657 -0x1b80 0x5cf10665 -0x1b80 0x5cf10667 -0x1b80 0x0ac60675 -0x1b80 0x0ac60677 -0x1b80 0xe1a20685 -0x1b80 0xe1a20687 -0x1b80 0x0c010695 -0x1b80 0x0c010697 -0x1b80 0xe14706a5 -0x1b80 0xe14706a7 -0x1b80 0x54e506b5 -0x1b80 0x54e506b7 -0x1b80 0x000106c5 -0x1b80 0x000106c7 -0x1b80 0x732006d5 -0x1b80 0x732006d7 -0x1b80 0x720006e5 -0x1b80 0x720006e7 -0x1b80 0x710006f5 -0x1b80 0x710006f7 -0x1b80 0x5ce20705 -0x1b80 0x5ce20707 -0x1b80 0x54be0715 -0x1b80 0x54be0717 -0x1b80 0x62060725 -0x1b80 0x62060727 -0x1b80 0x60060735 -0x1b80 0x60060737 -0x1b80 0xe1950745 -0x1b80 0xe1950747 -0x1b80 0x30aa0755 -0x1b80 0x30aa0757 -0x1b80 0x56010765 -0x1b80 0x56010767 -0x1b80 0x5ce20775 -0x1b80 0x5ce20777 -0x1b80 0x0ae10785 -0x1b80 0x0ae10787 -0x1b80 0x630d0795 -0x1b80 0x630d0797 -0x1b80 0xe12d07a5 -0x1b80 0xe12d07a7 -0x1b80 0x002607b5 -0x1b80 0x002607b7 -0x1b80 0xe15c07c5 -0x1b80 0xe15c07c7 -0x1b80 0x000207d5 -0x1b80 0x000207d7 -0x1b80 0x630707e5 -0x1b80 0x630707e7 -0x1b80 0xe12d07f5 -0x1b80 0xe12d07f7 -0x1b80 0xe15c0805 -0x1b80 0xe15c0807 -0x1b80 0x56000815 -0x1b80 0x56000817 -0x1b80 0x5cf20825 -0x1b80 0x5cf20827 -0x1b80 0x0af10835 -0x1b80 0x0af10837 -0x1b80 0x07140845 -0x1b80 0x07140847 -0x1b80 0x07140855 -0x1b80 0x07140857 -0x1b80 0x630d0865 -0x1b80 0x630d0867 -0x1b80 0xe12d0875 -0x1b80 0xe12d0877 -0x1b80 0x00260885 -0x1b80 0x00260887 -0x1b80 0xe15c0895 -0x1b80 0xe15c0897 -0x1b80 0x000208a5 -0x1b80 0x000208a7 -0x1b80 0x30d308b5 -0x1b80 0x30d308b7 -0x1b80 0x560108c5 -0x1b80 0x560108c7 -0x1b80 0x5ce208d5 -0x1b80 0x5ce208d7 -0x1b80 0x0ae108e5 -0x1b80 0x0ae108e7 -0x1b80 0x631d08f5 -0x1b80 0x631d08f7 -0x1b80 0xe12d0905 -0x1b80 0xe12d0907 -0x1b80 0x00240915 -0x1b80 0x00240917 -0x1b80 0xe15c0925 -0x1b80 0xe15c0927 -0x1b80 0x00020935 -0x1b80 0x00020937 -0x1b80 0x63170945 -0x1b80 0x63170947 -0x1b80 0xe12d0955 -0x1b80 0xe12d0957 -0x1b80 0x630f0965 -0x1b80 0x630f0967 -0x1b80 0xe12d0975 -0x1b80 0xe12d0977 -0x1b80 0x63070985 -0x1b80 0x63070987 -0x1b80 0xe12d0995 -0x1b80 0xe12d0997 -0x1b80 0xe15c09a5 -0x1b80 0xe15c09a7 -0x1b80 0x560009b5 -0x1b80 0x560009b7 -0x1b80 0x5cf209c5 -0x1b80 0x5cf209c7 -0x1b80 0x0af109d5 -0x1b80 0x0af109d7 -0x1b80 0x071409e5 -0x1b80 0x071409e7 -0x1b80 0x071409f5 -0x1b80 0x071409f7 -0x1b80 0x630f0a05 -0x1b80 0x630f0a07 -0x1b80 0xe12d0a15 -0x1b80 0xe12d0a17 -0x1b80 0x63170a25 -0x1b80 0x63170a27 -0x1b80 0xe12d0a35 -0x1b80 0xe12d0a37 -0x1b80 0x631d0a45 -0x1b80 0x631d0a47 -0x1b80 0xe12d0a55 -0x1b80 0xe12d0a57 -0x1b80 0x00240a65 -0x1b80 0x00240a67 -0x1b80 0xe15c0a75 -0x1b80 0xe15c0a77 -0x1b80 0x00020a85 -0x1b80 0x00020a87 -0x1b80 0x30d30a95 -0x1b80 0x30d30a97 -0x1b80 0x56010aa5 -0x1b80 0x56010aa7 -0x1b80 0x5ce20ab5 -0x1b80 0x5ce20ab7 -0x1b80 0x0ae10ac5 -0x1b80 0x0ae10ac7 -0x1b80 0x633a0ad5 -0x1b80 0x633a0ad7 -0x1b80 0xe12d0ae5 -0x1b80 0xe12d0ae7 -0x1b80 0x63370af5 -0x1b80 0x63370af7 -0x1b80 0xe12d0b05 -0x1b80 0xe12d0b07 -0x1b80 0x632f0b15 -0x1b80 0x632f0b17 -0x1b80 0xe12d0b25 -0x1b80 0xe12d0b27 -0x1b80 0x63270b35 -0x1b80 0x63270b37 -0x1b80 0xe12d0b45 -0x1b80 0xe12d0b47 -0x1b80 0x631f0b55 -0x1b80 0x631f0b57 -0x1b80 0xe12d0b65 -0x1b80 0xe12d0b67 -0x1b80 0x63170b75 -0x1b80 0x63170b77 -0x1b80 0xe12d0b85 -0x1b80 0xe12d0b87 -0x1b80 0x630f0b95 -0x1b80 0x630f0b97 -0x1b80 0xe12d0ba5 -0x1b80 0xe12d0ba7 -0x1b80 0x63070bb5 -0x1b80 0x63070bb7 -0x1b80 0xe12d0bc5 -0x1b80 0xe12d0bc7 -0x1b80 0xe15c0bd5 -0x1b80 0xe15c0bd7 -0x1b80 0x56000be5 -0x1b80 0x56000be7 -0x1b80 0x5cf20bf5 -0x1b80 0x5cf20bf7 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-0x1b80 0x11e81c67 -0x1b80 0x23411c75 -0x1b80 0x23411c77 -0x1b80 0x61e11c85 -0x1b80 0x61e11c87 -0x1b80 0x23411c95 -0x1b80 0x23411c97 -0x1b80 0x70611ca5 -0x1b80 0x70611ca7 -0x1b80 0x4d001cb5 -0x1b80 0x4d001cb7 -0x1b80 0x00011cc5 -0x1b80 0x00011cc7 -0x1b80 0x00000006 -0x1b80 0x00000002 +//RL6302_MAC_PHY_Parameter_v018_20140708 +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x1000001f +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x76433170 +0x830 0x79a0ea0b +0x834 0x042E6486 +0x838 0x87aa7640 +0x83c 0x9797b9b9 +0x840 0x17575fe0 +0x844 0x4BBDFCDE +0x848 0x5cd07f8b +0x84c 0x6CFbF7B5 +0x850 0x28836706 +0x854 0x0001520c +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x43642855 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40f550a // all modes use 320M ADC clk +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80025169 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400082c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00400700 +0x90c 0x0B004000 +0x910 0x0000fc00 +0x914 0xD6400404 // ADC_backoff:12.5dB_DFIR_backoff:6.5dB +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4AB0E4E4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x944 0x08000000 +0x948 0x04000000 +0x950 0x02010080 +0x954 0x86510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x98c 0x03440000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00560000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000022d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000053 +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x19800000// RX_WAIT_CCA +0xc60 0x0B800001 +0xc60 0x05800002 +0xc60 0x07800003 +0xc60 0x19800004// TX_CCK_RFON +0xc60 0x0B800005 +0xc60 0x05800006 +0xc60 0x0E800007 +0xc60 0x19800008// TX_CCK_BBON +0xc60 0x0B800009 +0xc60 0x0580000A +0xc60 0x0E80000B +0xc60 0x1980000C// TX_OFDM_RFON +0xc60 0x0B80000D +0xc60 0x0580000E +0xc60 0x0E80000F +0xc60 0x19800010// TX_OFDM_BBON +0xc60 0x0B800011 +0xc60 0x05800012 +0xc60 0x0E800013 +0xc60 0x19800014// TX_TO_RX +0xc60 0x0B800015 +0xc60 0x05800016 +0xc60 0x07800017 +0xc60 0x19800018// TX_TO_TX +0xc60 0x0B800019 +0xc60 0x0580001A +0xc60 0x0E80001B +0xc60 0x1980001C// RX_CCK +0xc60 0x0B80001D +0xc60 0x0580001E +0xc60 0x0780001F +0xc60 0x19800020// RX_OFDM +0xc60 0x0B800021 +0xc60 0x05800022 +0xc60 0x07800023 +0xc60 0x19800024// RX_WAIT_RIFS +0xc60 0x0B800025 +0xc60 0x05800026 +0xc60 0x07800027 +0xc60 0x19800028// RX_TO_RX +0xc60 0x0B800029 +0xc60 0x0580002A +0xc60 0x0780002B +//0xc60 0x1980002C // RSVD +//0xc60 0x0B80002D +//0xc60 0x0580002E +//0xc60 0x0680002F +0xc60 0x19800030 // BT or LTE coexist +0xc60 0x0B800031 +0xc60 0x05800032 +0xc60 0x00800033 +0xc60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0xc60 0x0B800035 +0xc60 0x05800036 +0xc60 0x00800037 +0xc60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0xc60 0x0B800039 +0xc60 0x0580003A +0xc60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0xc60 0x1980003C // PMPD_ANAEN +//0xc60 0x0B80003D +//0xc60 0x0580003E +//0xc60 0x0080803F +0xc94 0x01000001 +0xc98 0x00188000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x77777000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x77700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000053 +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c020c14 +0xe5c 0x00000058 +0xe60 0x19800000// RX_WAIT_CCA +0xe60 0x0B800001 +0xe60 0x05800002 +0xe60 0x07800003 +0xe60 0x19800004// TX_CCK_RFON +0xe60 0x0B800005 +0xe60 0x05800006 +0xe60 0x0E800007 +0xe60 0x19800008// TX_CCK_BBON +0xe60 0x0B800009 +0xe60 0x0580000A +0xe60 0x0E80000B +0xe60 0x1980000C// TX_OFDM_RFON +0xe60 0x0B80000D +0xe60 0x0580000E +0xe60 0x0E80000F +0xe60 0x19800010// TX_OFDM_BBON +0xe60 0x0B800011 +0xe60 0x05800012 +0xe60 0x0E800013 +0xe60 0x19800014// TX_TO_RX +0xe60 0x0B800015 +0xe60 0x05800016 +0xe60 0x07800017 +0xe60 0x19800018// TX_TO_TX +0xe60 0x0B800019 +0xe60 0x0580001A +0xe60 0x0E80001B +0xe60 0x1980001C// RX_CCK +0xe60 0x0B80001D +0xe60 0x0580001E +0xe60 0x0780001F +0xe60 0x19800020// RX_OFDM +0xe60 0x0B800021 +0xe60 0x05800022 +0xe60 0x07800023 +0xe60 0x19800024// RX_WAIT_RIFS +0xe60 0x0B800025 +0xe60 0x05800026 +0xe60 0x07800027 +0xe60 0x19800028// RX_TO_RX +0xe60 0x0B800029 +0xe60 0x0580002A +0xe60 0x0780002B +//0xe60 0x1980002C // RSVD +//0xe60 0x0B80002D +//0xe60 0x0580002E +//0xe60 0x0680002F +0xe60 0x19800030 // BT or LTE coexist +0xe60 0x0B800031 +0xe60 0x05800032 +0xe60 0x00800033 +0xe60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0xe60 0x0B800035 +0xe60 0x05800036 +0xe60 0x00800037 +0xe60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0xe60 0x0B800039 +0xe60 0x0580003A +0xe60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0xe60 0x1980003C // PMPD_ANAEN +//0xe60 0x0B80003D +//0xe60 0x0580003E +//0xe60 0x0080803F +0xe94 0x01000001 +0xe98 0x00188000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x77777000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x77700000 +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000053 +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c020c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x19800000// RX_WAIT_CCA +0x1860 0x0B800001 +0x1860 0x05800002 +0x1860 0x07800003 +0x1860 0x19800004// TX_CCK_RFON +0x1860 0x0B800005 +0x1860 0x05800006 +0x1860 0x0E800007 +0x1860 0x19800008// TX_CCK_BBON +0x1860 0x0B800009 +0x1860 0x0580000A +0x1860 0x0E80000B +0x1860 0x1980000C// TX_OFDM_RFON +0x1860 0x0B80000D +0x1860 0x0580000E +0x1860 0x0E80000F +0x1860 0x19800010// TX_OFDM_BBON +0x1860 0x0B800011 +0x1860 0x05800012 +0x1860 0x0E800013 +0x1860 0x19800014// TX_TO_RX +0x1860 0x0B800015 +0x1860 0x05800016 +0x1860 0x07800017 +0x1860 0x19800018// TX_TO_TX +0x1860 0x0B800019 +0x1860 0x0580001A +0x1860 0x0E80001B +0x1860 0x1980001C// RX_CCK +0x1860 0x0B80001D +0x1860 0x0580001E +0x1860 0x0780001F +0x1860 0x19800020// RX_OFDM +0x1860 0x0B800021 +0x1860 0x05800022 +0x1860 0x07800023 +0x1860 0x19800024// RX_WAIT_RIFS +0x1860 0x0B800025 +0x1860 0x05800026 +0x1860 0x07800027 +0x1860 0x19800028// RX_TO_RX +0x1860 0x0B800029 +0x1860 0x0580002A +0x1860 0x0780002B +//0x1860 0x1980002C // RSVD +//0x1860 0x0B80002D +//0x1860 0x0580002E +//0x1860 0x0680002F +0x1860 0x19800030 // BT or LTE coexist +0x1860 0x0B800031 +0x1860 0x05800032 +0x1860 0x00800033 +0x1860 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0x1860 0x0B800035 +0x1860 0x05800036 +0x1860 0x00800037 +0x1860 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0x1860 0x0B800039 +0x1860 0x0580003A +0x1860 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0x1860 0x1980003C // PMPD_ANAEN +//0x1860 0x0B80003D +//0x1860 0x0580003E +//0x1860 0x0080803F +0x1894 0x01000001 +0x1898 0x00188000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x77777000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x77700000 +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000053 +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c020c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x19800000// RX_WAIT_CCA +0x1a60 0x0B800001 +0x1a60 0x05800002 +0x1a60 0x07800003 +0x1a60 0x19800004// TX_CCK_RFON +0x1a60 0x0B800005 +0x1a60 0x05800006 +0x1a60 0x0E800007 +0x1a60 0x19800008// TX_CCK_BBON +0x1a60 0x0B800009 +0x1a60 0x0580000A +0x1a60 0x0E80000B +0x1a60 0x1980000C// TX_OFDM_RFON +0x1a60 0x0B80000D +0x1a60 0x0580000E +0x1a60 0x0E80000F +0x1a60 0x19800010// TX_OFDM_BBON +0x1a60 0x0B800011 +0x1a60 0x05800012 +0x1a60 0x0E800013 +0x1a60 0x19800014// TX_TO_RX +0x1a60 0x0B800015 +0x1a60 0x05800016 +0x1a60 0x07800017 +0x1a60 0x19800018// TX_TO_TX +0x1a60 0x0B800019 +0x1a60 0x0580001A +0x1a60 0x0E80001B +0x1a60 0x1980001C// RX_CCK +0x1a60 0x0B80001D +0x1a60 0x0580001E +0x1a60 0x0780001F +0x1a60 0x19800020// RX_OFDM +0x1a60 0x0B800021 +0x1a60 0x05800022 +0x1a60 0x07800023 +0x1a60 0x19800024// RX_WAIT_RIFS +0x1a60 0x0B800025 +0x1a60 0x05800026 +0x1a60 0x07800027 +0x1a60 0x19800028// RX_TO_RX +0x1a60 0x0B800029 +0x1a60 0x0580002A +0x1a60 0x0780002B +//0x1a60 0x1980002C // RSVD +//0x1a60 0x0B80002D +//0x1a60 0x0580002E +//0x1a60 0x0680002F +0x1a60 0x19800030 // BT or LTE coexist +0x1a60 0x0B800031 +0x1a60 0x05800032 +0x1a60 0x00800033 +0x1a60 0x19800034 // invalid_pkt_pwrdn_SLEEP_MODE_bbrstb_sleep +0x1a60 0x0B800035 +0x1a60 0x05800036 +0x1a60 0x00800037 +0x1a60 0x19800038 // invalid_pkt_standby_STANDBY_MODE_bbrstb_standby +0x1a60 0x0B800039 +0x1a60 0x0580003A +0x1a60 0x0E80803B // set [15]=1 to enable ANAPAR lookup +//0x1a60 0x1980003C // PMPD_ANAEN +//0x1a60 0x0B80003D +//0x1a60 0x0580003E +//0x1a60 0x0080803F +0x1a94 0x01000001 +0x1a98 0x00188000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x77777000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x77700000 +//======================= +// PAGE_19 : common setting +//======================= +0x1904 0x00030000 // enable IOQ_iqk_dpk +0x1914 0x00030000 +0x1984 0x03000000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x1998 0x12801000 //CCK CCK 1M +0x1998 0x12801000 //CCK CCK 1M +0x1998 0x12801001 //CCK CCK 2M +0x1998 0x12801002 //CCK CCK 5.5M +0x1998 0x12801003 //CCK CCK 11M +0x1998 0x12801004 //OFDM OFDM 6M +0x1998 0x12801005 //OFDM OFDM 9M +0x1998 0x12801006 //OFDM OFDM 12M +0x1998 0x12801007 //OFDM OFDM 18M +0x1998 0x12801008 //OFDM OFDM 24M +0x1998 0x12801009 //OFDM OFDM 36M +0x1998 0x1280100a //OFDM OFDM 48M +0x1998 0x1280100b //OFDM OFDM 54M +0x1998 0x1280100c //HT nss1 MCS0 +0x1998 0x1280100d //HT nss1 MCS1 +0x1998 0x1280100e //HT nss1 MCS2 +0x1998 0x1280100f //HT nss1 MCS3 +0x1998 0x12801010 //HT nss1 MCS4 +0x1998 0x12801011 //HT nss1 MCS5 +0x1998 0x12801012 //HT nss1 MCS6 +0x1998 0x12801013 //HT nss1 MCS7 +0x1998 0x12801014 //HT nss2 MCS8 +0x1998 0x12801015 //HT nss2 MCS9 +0x1998 0x12801016 //HT nss2 MCS10 +0x1998 0x12801017 //HT nss2 MCS11 +0x1998 0x12801018 //HT nss2 MCS12 +0x1998 0x12801019 //HT nss2 MCS13 +0x1998 0x1280101a //HT nss2 MCS14 +0x1998 0x1280101b //HT nss2 MCS15 +0x1998 0x1280101c //HT nss3 MCS16 +0x1998 0x1280101d //HT nss3 MCS17 +0x1998 0x1280101e //HT nss3 MCS18 +0x1998 0x1280101f //HT nss3 MCS19 +0x1998 0x12801020 //HT nss3 MCS20 +0x1998 0x12801021 //HT nss3 MCS21 +0x1998 0x12801022 //HT nss3 MCS22 +0x1998 0x12801023 //HT nss3 MCS23 +0x1998 0x1280102c //VHT nss1 MCS0 +0x1998 0x1280102d //VHT nss1 MCS1 +0x1998 0x1280102e //VHT nss1 MCS2 +0x1998 0x1280102f //VHT nss1 MCS3 +0x1998 0x12801030 //VHT nss1 MCS4 +0x1998 0x12801031 //VHT nss1 MCS5 +0x1998 0x12801032 //VHT nss1 MCS6 +0x1998 0x12801033 //VHT nss1 MCS7 +0x1998 0x12801034 //VHT nss1 MCS8 +0x1998 0x12801035 //VHT nss1 MCS9 +0x1998 0x12801036 //VHT nss2 MCS0 +0x1998 0x12801037 //VHT nss2 MCS1 +0x1998 0x12801038 //VHT nss2 MCS2 +0x1998 0x12801039 //VHT nss2 MCS3 +0x1998 0x1280103a //VHT nss2 MCS4 +0x1998 0x1280103b //VHT nss2 MCS5 +0x1998 0x1280103c //VHT nss2 MCS6 +0x1998 0x1280103d //VHT nss2 MCS7 +0x1998 0x1280103e //VHT nss2 MCS8 +0x1998 0x1280103f //VHT nss2 MCS9 +0x1998 0x12801040 //VHT nss3 MCS0 +0x1998 0x12801041 //VHT nss3 MCS1 +0x1998 0x12801042 //VHT nss3 MCS2 +0x1998 0x12801043 //VHT nss3 MCS3 +0x1998 0x12801044 //VHT nss3 MCS4 +0x1998 0x12801045 //VHT nss3 MCS5 +0x1998 0x12801046 //VHT nss3 MCS6 +0x1998 0x12801047 //VHT nss3 MCS7 +0x1998 0x12801048 //VHT nss3 MCS8 +0x1998 0x12801049 //VHT nss3 MCS9 +0x1998 0x12801100 //CCK CCK 1M +0x1998 0x12801101 //CCK CCK 2M +0x1998 0x12801102 //CCK CCK 5.5M +0x1998 0x12801103 //CCK CCK 11M +0x1998 0x12801104 //OFDM OFDM 6M +0x1998 0x12801105 //OFDM OFDM 9M +0x1998 0x12801106 //OFDM OFDM 12M +0x1998 0x12801107 //OFDM OFDM 18M +0x1998 0x12801108 //OFDM OFDM 24M +0x1998 0x12801109 //OFDM OFDM 36M +0x1998 0x1280110a //OFDM OFDM 48M +0x1998 0x1280110b //OFDM OFDM 54M +0x1998 0x1280110c //HT nss1 MCS0 +0x1998 0x1280110d //HT nss1 MCS1 +0x1998 0x1280110e //HT nss1 MCS2 +0x1998 0x1280110f //HT nss1 MCS3 +0x1998 0x12801110 //HT nss1 MCS4 +0x1998 0x12801111 //HT nss1 MCS5 +0x1998 0x12801112 //HT nss1 MCS6 +0x1998 0x12801113 //HT nss1 MCS7 +0x1998 0x12801114 //HT nss2 MCS8 +0x1998 0x12801115 //HT nss2 MCS9 +0x1998 0x12801116 //HT nss2 MCS10 +0x1998 0x12801117 //HT nss2 MCS11 +0x1998 0x12801118 //HT nss2 MCS12 +0x1998 0x12801119 //HT nss2 MCS13 +0x1998 0x1280111a //HT nss2 MCS14 +0x1998 0x1280111b //HT nss2 MCS15 +0x1998 0x1280111c //HT nss3 MCS16 +0x1998 0x1280111d //HT nss3 MCS17 +0x1998 0x1280111e //HT nss3 MCS18 +0x1998 0x1280111f //HT nss3 MCS19 +0x1998 0x12801120 //HT nss3 MCS20 +0x1998 0x12801121 //HT nss3 MCS21 +0x1998 0x12801122 //HT nss3 MCS22 +0x1998 0x12801123 //HT nss3 MCS23 +0x1998 0x1280112c //VHT nss1 MCS0 +0x1998 0x1280112d //VHT nss1 MCS1 +0x1998 0x1280112e //VHT nss1 MCS2 +0x1998 0x1280112f //VHT nss1 MCS3 +0x1998 0x12801130 //VHT nss1 MCS4 +0x1998 0x12801131 //VHT nss1 MCS5 +0x1998 0x12801132 //VHT nss1 MCS6 +0x1998 0x12801133 //VHT nss1 MCS7 +0x1998 0x12801134 //VHT nss1 MCS8 +0x1998 0x12801135 //VHT nss1 MCS9 +0x1998 0x12801136 //VHT nss2 MCS0 +0x1998 0x12801137 //VHT nss2 MCS1 +0x1998 0x12801138 //VHT nss2 MCS2 +0x1998 0x12801139 //VHT nss2 MCS3 +0x1998 0x1280113a //VHT nss2 MCS4 +0x1998 0x1280113b //VHT nss2 MCS5 +0x1998 0x1280113c //VHT nss2 MCS6 +0x1998 0x1280113d //VHT nss2 MCS7 +0x1998 0x1280113e //VHT nss2 MCS8 +0x1998 0x1280113f //VHT nss2 MCS9 +0x1998 0x12801140 //VHT nss3 MCS0 +0x1998 0x12801141 //VHT nss3 MCS1 +0x1998 0x12801142 //VHT nss3 MCS2 +0x1998 0x12801143 //VHT nss3 MCS3 +0x1998 0x12801144 //VHT nss3 MCS4 +0x1998 0x12801145 //VHT nss3 MCS5 +0x1998 0x12801146 //VHT nss3 MCS6 +0x1998 0x12801147 //VHT nss3 MCS7 +0x1998 0x12801148 //VHT nss3 MCS8 +0x1998 0x12801149 //VHT nss3 MCS9 +0x1998 0x12801200 //CCK CCK 1M +0x1998 0x12801201 //CCK CCK 2M +0x1998 0x12801202 //CCK CCK 5.5M +0x1998 0x12801203 //CCK CCK 11M +0x1998 0x12801204 //OFDM OFDM 6M +0x1998 0x12801205 //OFDM OFDM 9M +0x1998 0x12801206 //OFDM OFDM 12M +0x1998 0x12801207 //OFDM OFDM 18M +0x1998 0x12801208 //OFDM OFDM 24M +0x1998 0x12801209 //OFDM OFDM 36M +0x1998 0x1280120a //OFDM OFDM 48M +0x1998 0x1280120b //OFDM OFDM 54M +0x1998 0x1280120c //HT nss1 MCS0 +0x1998 0x1280120d //HT nss1 MCS1 +0x1998 0x1280120e //HT nss1 MCS2 +0x1998 0x1280120f //HT nss1 MCS3 +0x1998 0x12801210 //HT nss1 MCS4 +0x1998 0x12801211 //HT nss1 MCS5 +0x1998 0x12801212 //HT nss1 MCS6 +0x1998 0x12801213 //HT nss1 MCS7 +0x1998 0x12801214 //HT nss2 MCS8 +0x1998 0x12801215 //HT nss2 MCS9 +0x1998 0x12801216 //HT nss2 MCS10 +0x1998 0x12801217 //HT nss2 MCS11 +0x1998 0x12801218 //HT nss2 MCS12 +0x1998 0x12801219 //HT nss2 MCS13 +0x1998 0x1280121a //HT nss2 MCS14 +0x1998 0x1280121b //HT nss2 MCS15 +0x1998 0x1280121c //HT nss3 MCS16 +0x1998 0x1280121d //HT nss3 MCS17 +0x1998 0x1280121e //HT nss3 MCS18 +0x1998 0x1280121f //HT nss3 MCS19 +0x1998 0x12801220 //HT nss3 MCS20 +0x1998 0x12801221 //HT nss3 MCS21 +0x1998 0x12801222 //HT nss3 MCS22 +0x1998 0x12801223 //HT nss3 MCS23 +0x1998 0x1280122c //VHT nss1 MCS0 +0x1998 0x1280122d //VHT nss1 MCS1 +0x1998 0x1280122e //VHT nss1 MCS2 +0x1998 0x1280122f //VHT nss1 MCS3 +0x1998 0x12801230 //VHT nss1 MCS4 +0x1998 0x12801231 //VHT nss1 MCS5 +0x1998 0x12801232 //VHT nss1 MCS6 +0x1998 0x12801233 //VHT nss1 MCS7 +0x1998 0x12801234 //VHT nss1 MCS8 +0x1998 0x12801235 //VHT nss1 MCS9 +0x1998 0x12801236 //VHT nss2 MCS0 +0x1998 0x12801237 //VHT nss2 MCS1 +0x1998 0x12801238 //VHT nss2 MCS2 +0x1998 0x12801239 //VHT nss2 MCS3 +0x1998 0x1280123a //VHT nss2 MCS4 +0x1998 0x1280123b //VHT nss2 MCS5 +0x1998 0x1280123c //VHT nss2 MCS6 +0x1998 0x1280123d //VHT nss2 MCS7 +0x1998 0x1280123e //VHT nss2 MCS8 +0x1998 0x1280123f //VHT nss2 MCS9 +0x1998 0x12801240 //VHT nss3 MCS0 +0x1998 0x12801241 //VHT nss3 MCS1 +0x1998 0x12801242 //VHT nss3 MCS2 +0x1998 0x12801243 //VHT nss3 MCS3 +0x1998 0x12801244 //VHT nss3 MCS4 +0x1998 0x12801245 //VHT nss3 MCS5 +0x1998 0x12801246 //VHT nss3 MCS6 +0x1998 0x12801247 //VHT nss3 MCS7 +0x1998 0x12801248 //VHT nss3 MCS8 +0x1998 0x12801249 //VHT nss3 MCS9 +0x1998 0x12801300 //CCK CCK 1M +0x1998 0x12801301 //CCK CCK 2M +0x1998 0x12801302 //CCK CCK 5.5M +0x1998 0x12801303 //CCK CCK 11M +0x1998 0x12801304 //OFDM OFDM 6M +0x1998 0x12801305 //OFDM OFDM 9M +0x1998 0x12801306 //OFDM OFDM 12M +0x1998 0x12801307 //OFDM OFDM 18M +0x1998 0x12801308 //OFDM OFDM 24M +0x1998 0x12801309 //OFDM OFDM 36M +0x1998 0x1280130a //OFDM OFDM 48M +0x1998 0x1280130b //OFDM OFDM 54M +0x1998 0x1280130c //HT nss1 MCS0 +0x1998 0x1280130d //HT nss1 MCS1 +0x1998 0x1280130e //HT nss1 MCS2 +0x1998 0x1280130f //HT nss1 MCS3 +0x1998 0x12801310 //HT nss1 MCS4 +0x1998 0x12801311 //HT nss1 MCS5 +0x1998 0x12801312 //HT nss1 MCS6 +0x1998 0x12801313 //HT nss1 MCS7 +0x1998 0x12801314 //HT nss2 MCS8 +0x1998 0x12801315 //HT nss2 MCS9 +0x1998 0x12801316 //HT nss2 MCS10 +0x1998 0x12801317 //HT nss2 MCS11 +0x1998 0x12801318 //HT nss2 MCS12 +0x1998 0x12801319 //HT nss2 MCS13 +0x1998 0x1280131a //HT nss2 MCS14 +0x1998 0x1280131b //HT nss2 MCS15 +0x1998 0x1280131c //HT nss3 MCS16 +0x1998 0x1280131d //HT nss3 MCS17 +0x1998 0x1280131e //HT nss3 MCS18 +0x1998 0x1280131f //HT nss3 MCS19 +0x1998 0x12801320 //HT nss3 MCS20 +0x1998 0x12801321 //HT nss3 MCS21 +0x1998 0x12801322 //HT nss3 MCS22 +0x1998 0x12801323 //HT nss3 MCS23 +0x1998 0x1280132c //VHT nss1 MCS0 +0x1998 0x1280132d //VHT nss1 MCS1 +0x1998 0x1280132e //VHT nss1 MCS2 +0x1998 0x1280132f //VHT nss1 MCS3 +0x1998 0x12801330 //VHT nss1 MCS4 +0x1998 0x12801331 //VHT nss1 MCS5 +0x1998 0x12801332 //VHT nss1 MCS6 +0x1998 0x12801333 //VHT nss1 MCS7 +0x1998 0x12801334 //VHT nss1 MCS8 +0x1998 0x12801335 //VHT nss1 MCS9 +0x1998 0x12801336 //VHT nss2 MCS0 +0x1998 0x12801337 //VHT nss2 MCS1 +0x1998 0x12801338 //VHT nss2 MCS2 +0x1998 0x12801339 //VHT nss2 MCS3 +0x1998 0x1280133a //VHT nss2 MCS4 +0x1998 0x1280133b //VHT nss2 MCS5 +0x1998 0x1280133c //VHT nss2 MCS6 +0x1998 0x1280133d //VHT nss2 MCS7 +0x1998 0x1280133e //VHT nss2 MCS8 +0x1998 0x1280133f //VHT nss2 MCS9 +0x1998 0x12801340 //VHT nss3 MCS0 +0x1998 0x12801341 //VHT nss3 MCS1 +0x1998 0x12801342 //VHT nss3 MCS2 +0x1998 0x12801343 //VHT nss3 MCS3 +0x1998 0x12801344 //VHT nss3 MCS4 +0x1998 0x12801345 //VHT nss3 MCS5 +0x1998 0x12801346 //VHT nss3 MCS6 +0x1998 0x12801347 //VHT nss3 MCS7 +0x1998 0x12801348 //VHT nss3 MCS8 +0x1998 0x12801349 //VHT nss3 MCS9 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// ADC clk lock procedure +//======================= +0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) +// 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 +// 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line +// 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut + +// power_off/clk_off @ anapar_state=idle mode +0xc60 0x15808002 +0xc60 0x01808003 +0xe60 0x15808002 +0xe60 0x01808003 +0x1860 0x15808002 +0x1860 0x01808003 +0x1a60 0x15808002 +0x1a60 0x01808003 + +0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) +0xc5c 0x00080058 // [19] =1 to turn off ADC +0xe5c 0x00080058 // [19] =1 to turn off ADC +0x185c 0x00080058 // [19] =1 to turn off ADC +0x1a5c 0x00080058 // [19] =1 to turn off ADC + +// power_on/clk_off @ anapar_state=sleep mode +0xc60 0x15808036 +0xc60 0x0F808037 +0xe60 0x15808036 +0xe60 0x0F808037 +0x1860 0x15808036 +0x1860 0x0F808037 +0x1a60 0x15808036 +0x1a60 0x0F808037 + +0xb00 0xe2100100 // [24]BBRSTB=0 to change anapar_state=sleep (make sure 0x804[18]=1b0) +0xc5c 0x0D000058 // [19] =0 to turn on ADC +0xe5c 0x0D000058 // [19] =0 to turn on ADC +0x185c 0x0D000058 // [19] =0 to turn on ADC +0x1a5c 0x0D000058 // [19] =0 to turn on ADC + +// power_on/clk_on @ anapar_state=idle mode +0xc60 0x05808002 +0xc60 0x0e808003 +0xe60 0x05808002 +0xe60 0x0e808003 +0x1860 0x05808002 +0x1860 0x0e808003 +0x1a60 0x05808002 +0x1a60 0x0e808003 +// recover original setting @ anapar_state=sleep mode +0xc60 0x05808036 +0xc60 0x0e808037 +0xe60 0x05808036 +0xe60 0x0e808037 +0x1860 0x05808036 +0x1860 0x0e808037 +0x1a60 0x05808036 +0x1a60 0x0e808037 + +0xb00 0xe3100100 // [24]BBRSTB=1 to change anapar_state=idle (make sure 0x804[18]=1b0) +0xb00 0xe3100000 //return true MAC + +//======================= +// PAGE_1c +//======================= +0x1c38 0x00000002 // enable IQK clk +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe24628d2 +0x1b10 0x88010d46 +0x1b14 0x00000000 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b00 0xf8015000 +0x1b00 0xf8057000 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b00 0xf8015002 +0x1b00 0xf8057002 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b00 0xf8015004 +0x1b00 0xf8057004 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b00 0xf8015006 +0x1b00 0xf8057006 +0x1b1c 0xa2147db2 +0x1b20 0x07040001 +0x1b24 0x07060807 +0x1b28 0xc0060324 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 +0x1bd4 0x00000001 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x09060005 +0x1b80 0x09060007 +0x1b80 0x0ffe0015 +0x1b80 0x0ffe0017 +0x1b80 0x00240025 +0x1b80 0x00240027 +0x1b80 0x00040035 +0x1b80 0x00040037 +0x1b80 0x05c00045 +0x1b80 0x05c00047 +0x1b80 0x00070055 +0x1b80 0x00070057 +0x1b80 0x64000065 +0x1b80 0x64000067 +0x1b80 0x00020075 +0x1b80 0x00020077 +0x1b80 0x00080085 +0x1b80 0x00080087 +0x1b80 0x80000095 +0x1b80 0x80000097 +0x1b80 0x090100a5 +0x1b80 0x090100a7 +0x1b80 0x0f0200b5 +0x1b80 0x0f0200b7 +0x1b80 0x002400c5 +0x1b80 0x002400c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x05c000e5 +0x1b80 0x05c000e7 +0x1b80 0x000700f5 +0x1b80 0x000700f7 +0x1b80 0x64020105 +0x1b80 0x64020107 +0x1b80 0x00020115 +0x1b80 0x00020117 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a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814A.txt old mode 100755 new mode 100644 index fb8c01185f0..499a79de33d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814A.txt @@ -1,2 +1,2 @@ -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814Amp.txt old mode 100755 new mode 100644 index f5b24049b44..348729c2056 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_MP_8814Amp.txt @@ -1,3 +1,3 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814A.txt old mode 100755 new mode 100644 index d1aefc673da..17aa2a002f5 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814A.txt @@ -1,110 +1,110 @@ -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp.txt old mode 100755 new mode 100644 index 5d3ce20a1d6..bafcc5b418b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type0.txt old mode 100755 new mode 100644 index ff99cd8b562..9e1a75c2de1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type0.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type2.txt old mode 100755 new mode 100644 index a134787e7c4..564ed10bfe6 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type2.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type3.txt old mode 100755 new mode 100644 index 2405f611091..bb258598e6a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type3.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v054_20141124 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type4.txt old mode 100755 new mode 100644 index a134787e7c4..564ed10bfe6 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type4.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type5.txt old mode 100755 new mode 100644 index 982bdcca8ed..f2c3107104c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type5.txt @@ -1,152 +1,152 @@ -//rtl8814a version = RL6302_MAC_PHY_Parameter_v075_20150526 -//RL6302_MAC_PHY_Parameter_v054_20141124 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//rtl8814a version = RL6302_MAC_PHY_Parameter_v075_20150526 +//RL6302_MAC_PHY_Parameter_v054_20141124 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type7.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type7.txt index 36ff049fb59..0e2c343b9f3 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type7.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type7.txt @@ -1,152 +1,152 @@ -//rtl8814a version = 96 -//rtl8814a version = 94 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//rtl8814a version = 96 +//rtl8814a version = 94 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 12 13 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 12 13 17 17// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type8.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type8.txt index a134787e7c4..564ed10bfe6 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type8.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/PHY_REG_PG_8814Amp_Type8.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A.txt old mode 100755 new mode 100644 index 8fcd59c83bf..eda1cb092b1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A.txt @@ -1,324 +1,324 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C09C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C09C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A_hp.txt old mode 100755 new mode 100644 index c2f5560fc20..33b524889f1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814A_hp.txt @@ -1,322 +1,322 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C09C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C09C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp.txt old mode 100755 new mode 100644 index 91fb466413d..a8ba10c05fe --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp.txt @@ -1,321 +1,321 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C05C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - - - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C05C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + + + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp_hp.txt old mode 100755 new mode 100644 index d2cc7acf26d..51969342411 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioA_8814Amp_hp.txt @@ -1,406 +1,406 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FF48 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0A78F -0xB5 0x00A3F -0xB6 0x0C09C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x50780 -0xBB 0x00000 -0xBC 0x40009 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x06800 -0x3E 0x00080 -0x3F 0x06000 -0x3E 0x00100 -0x3F 0x04800 -0x3E 0x00180 -0x3F 0x04000 -0x3E 0x00200 -0x3F 0x04000 -0x3E 0x00280 -0x3F 0x02800 -0x3E 0x00300 -0x3F 0x02800 -0x3E 0x00380 -0x3F 0x02000 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00000 //G mode need to check -0x3F 0x000BC -0x3E 0x00040 -0x3F 0x00053 -0x3E 0x00050 -0x3F 0x00050 -0x3E 0x00060 -0x3F 0x00050 -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0xEE080 //G mode need to check -0x3E 0x00008 -0x41 0xEE0C0 -0x3E 0x0000A -0x41 0xEE100 -0x3E 0x0000C -0x41 0xEE100 -0xEF 0x00000 -/////////////// -//0x18 0x1312A - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xec000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0F1 //63 -0x34 0x490EE //57 -0x34 0x480EB //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x45067 //33 -0x34 0x44046 //27 -0x34 0x4300C //21 -0x34 0x42009 //15 -0x34 0x41006 //9 -0x34 0x40003 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0F1 //63 -0x34 0x290EE //57 -0x34 0x280EB //51 -0x34 0x2706D //45 -0x34 0x2606A //39 -0x34 0x25067 //33 -0x34 0x24046 //27 -0x34 0x2300C //21 -0x34 0x22009 //15 -0x34 0x21006 //9 -0x34 0x20003 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0F0 //63 -0x34 0x090ED //57 -0x34 0x080EA //51 -0x34 0x0706D //45 -0x34 0x0606A //39 -0x34 0x0502D //33 -0x34 0x0402A //27 -0x34 0x03027 //21 -0x34 0x02024 //15 -0x34 0x01007 //9 -0x34 0x00004 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0x4A0F1 //63 -0x34 0x490EE //57 -0x34 0x480EB //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x45067 //33 -0x34 0x44046 //27 -0x34 0x4300C //21 -0x34 0x42009 //15 -0x34 0x41006 //9 -0x34 0x40003 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0x4A0F1 //63 -0x34 0x490EE //57 -0x34 0x480EB //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x45067 //33 -0x34 0x44046 //27 -0x34 0x4300C //21 -0x34 0x42009 //15 -0x34 0x41006 //9 -0x34 0x40003 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x8A0F0 //63 -0x34 0x890ED //57 -0x34 0x880EA //51 -0x34 0x8706D //45 -0x34 0x8606A //39 -0x34 0x8502D //33 -0x34 0x8402A //27 -0x34 0x83027 //21 -0x34 0x82024 //15 -0x34 0x81007 //9 -0x34 0x80004 //3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD_prePAD_PAD tank) -0xEF 0x00008 - - - -0x3C 0x0017d //HP_LB_PA_TANK[2:0] -0x3C 0x0057d //HP_MB_PA_TANK[2:0] -0x3C 0x0087d //HP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D0 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc // LOK -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0x18 0x1b126 //do LCK -0xfe -0xfe -0xfe -0x18 0x13126 //set channel again -0x18 0x13124 // switch channel +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FF48 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0A78F +0xB5 0x00A3F +0xB6 0x0C09C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x50780 +0xBB 0x00000 +0xBC 0x40009 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x06800 +0x3E 0x00080 +0x3F 0x06000 +0x3E 0x00100 +0x3F 0x04800 +0x3E 0x00180 +0x3F 0x04000 +0x3E 0x00200 +0x3F 0x04000 +0x3E 0x00280 +0x3F 0x02800 +0x3E 0x00300 +0x3F 0x02800 +0x3E 0x00380 +0x3F 0x02000 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00000 //G mode need to check +0x3F 0x000BC +0x3E 0x00040 +0x3F 0x00053 +0x3E 0x00050 +0x3F 0x00050 +0x3E 0x00060 +0x3F 0x00050 +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0xEE080 //G mode need to check +0x3E 0x00008 +0x41 0xEE0C0 +0x3E 0x0000A +0x41 0xEE100 +0x3E 0x0000C +0x41 0xEE100 +0xEF 0x00000 +/////////////// +//0x18 0x1312A + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xec000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0F1 //63 +0x34 0x490EE //57 +0x34 0x480EB //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x45067 //33 +0x34 0x44046 //27 +0x34 0x4300C //21 +0x34 0x42009 //15 +0x34 0x41006 //9 +0x34 0x40003 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0F1 //63 +0x34 0x290EE //57 +0x34 0x280EB //51 +0x34 0x2706D //45 +0x34 0x2606A //39 +0x34 0x25067 //33 +0x34 0x24046 //27 +0x34 0x2300C //21 +0x34 0x22009 //15 +0x34 0x21006 //9 +0x34 0x20003 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0F0 //63 +0x34 0x090ED //57 +0x34 0x080EA //51 +0x34 0x0706D //45 +0x34 0x0606A //39 +0x34 0x0502D //33 +0x34 0x0402A //27 +0x34 0x03027 //21 +0x34 0x02024 //15 +0x34 0x01007 //9 +0x34 0x00004 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0x4A0F1 //63 +0x34 0x490EE //57 +0x34 0x480EB //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x45067 //33 +0x34 0x44046 //27 +0x34 0x4300C //21 +0x34 0x42009 //15 +0x34 0x41006 //9 +0x34 0x40003 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0x4A0F1 //63 +0x34 0x490EE //57 +0x34 0x480EB //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x45067 //33 +0x34 0x44046 //27 +0x34 0x4300C //21 +0x34 0x42009 //15 +0x34 0x41006 //9 +0x34 0x40003 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x8A0F0 //63 +0x34 0x890ED //57 +0x34 0x880EA //51 +0x34 0x8706D //45 +0x34 0x8606A //39 +0x34 0x8502D //33 +0x34 0x8402A //27 +0x34 0x83027 //21 +0x34 0x82024 //15 +0x34 0x81007 //9 +0x34 0x80004 //3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD_prePAD_PAD tank) +0xEF 0x00008 + + + +0x3C 0x0017d //HP_LB_PA_TANK[2:0] +0x3C 0x0057d //HP_MB_PA_TANK[2:0] +0x3C 0x0087d //HP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D0 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc // LOK +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0x18 0x1b126 //do LCK +0xfe +0xfe +0xfe +0x18 0x13126 //set channel again +0x18 0x13124 // switch channel 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A.txt old mode 100755 new mode 100644 index 62deb9c0a30..90000512f36 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A_hp.txt old mode 100755 new mode 100644 index 349ec53556e..7c8a702a401 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814A_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp.txt old mode 100755 new mode 100644 index f76356b76db..74cafb4c294 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp_hp.txt old mode 100755 new mode 100644 index fefe6dc0d28..b9686e45a94 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioB_8814Amp_hp.txt @@ -1,323 +1,323 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xe4000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0F1 //63 -0x34 0x490EE //57 -0x34 0x480EB //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x45067 //33 -0x34 0x44046 //27 -0x34 0x4300C //21 -0x34 0x42009 //15 -0x34 0x41006 //9 -0x34 0x40003 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0F1 //63 -0x34 0x290EE //57 -0x34 0x280EB //51 -0x34 0x2706D //45 -0x34 0x2606A //39 -0x34 0x25067 //33 -0x34 0x24046 //27 -0x34 0x2300C //21 -0x34 0x22009 //15 -0x34 0x21006 //9 -0x34 0x20003 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0F0 //63 -0x34 0x090ED //57 -0x34 0x080EA //51 -0x34 0x0706D //45 -0x34 0x0606A //39 -0x34 0x0502D //33 -0x34 0x0402A //27 -0x34 0x03027 //21 -0x34 0x02024 //15 -0x34 0x01007 //9 -0x34 0x00004 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0x4A0F1 //63 -0x34 0x490EE //57 -0x34 0x480EB //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x45067 //33 -0x34 0x44046 //27 -0x34 0x4300C //21 -0x34 0x42009 //15 -0x34 0x41006 //9 -0x34 0x40003 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0x2A0F1 //63 -0x34 0x290EE //57 -0x34 0x280EB //51 -0x34 0x2706D //45 -0x34 0x2606A //39 -0x34 0x25067 //33 -0x34 0x24046 //27 -0x34 0x2300C //21 -0x34 0x22009 //15 -0x34 0x21006 //9 -0x34 0x20003 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x0A0F0 //63 -0x34 0x090ED //57 -0x34 0x080EA //51 -0x34 0x0706D //45 -0x34 0x0606A //39 -0x34 0x0502D //33 -0x34 0x0402A //27 -0x34 0x03027 //21 -0x34 0x02024 //15 -0x34 0x01007 //9 -0x34 0x00004 //3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD_PAD tank) -0xEF 0x00008 - - - -0x3C 0x0017e //HP_LB_PA_TANK[2:0] -0x3C 0x0057e //HP_MB_PA_TANK[2:0] -0x3C 0x0087e //HP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 //FDD43 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D0 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xe4000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0F1 //63 +0x34 0x490EE //57 +0x34 0x480EB //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x45067 //33 +0x34 0x44046 //27 +0x34 0x4300C //21 +0x34 0x42009 //15 +0x34 0x41006 //9 +0x34 0x40003 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0F1 //63 +0x34 0x290EE //57 +0x34 0x280EB //51 +0x34 0x2706D //45 +0x34 0x2606A //39 +0x34 0x25067 //33 +0x34 0x24046 //27 +0x34 0x2300C //21 +0x34 0x22009 //15 +0x34 0x21006 //9 +0x34 0x20003 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0F0 //63 +0x34 0x090ED //57 +0x34 0x080EA //51 +0x34 0x0706D //45 +0x34 0x0606A //39 +0x34 0x0502D //33 +0x34 0x0402A //27 +0x34 0x03027 //21 +0x34 0x02024 //15 +0x34 0x01007 //9 +0x34 0x00004 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0x4A0F1 //63 +0x34 0x490EE //57 +0x34 0x480EB //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x45067 //33 +0x34 0x44046 //27 +0x34 0x4300C //21 +0x34 0x42009 //15 +0x34 0x41006 //9 +0x34 0x40003 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0x2A0F1 //63 +0x34 0x290EE //57 +0x34 0x280EB //51 +0x34 0x2706D //45 +0x34 0x2606A //39 +0x34 0x25067 //33 +0x34 0x24046 //27 +0x34 0x2300C //21 +0x34 0x22009 //15 +0x34 0x21006 //9 +0x34 0x20003 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x0A0F0 //63 +0x34 0x090ED //57 +0x34 0x080EA //51 +0x34 0x0706D //45 +0x34 0x0606A //39 +0x34 0x0502D //33 +0x34 0x0402A //27 +0x34 0x03027 //21 +0x34 0x02024 //15 +0x34 0x01007 //9 +0x34 0x00004 //3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD_PAD tank) +0xEF 0x00008 + + + +0x3C 0x0017e //HP_LB_PA_TANK[2:0] +0x3C 0x0057e //HP_MB_PA_TANK[2:0] +0x3C 0x0087e //HP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 //FDD43 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D0 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A.txt old mode 100755 new mode 100644 index 3be2ef6ce50..d24513c9f4e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A_hp.txt old mode 100755 new mode 100644 index ffdca3eb0ee..19a05961f6c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814A_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp.txt old mode 100755 new mode 100644 index ed22e6d56d0..cfc3f9d7c8c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp_hp.txt old mode 100755 new mode 100644 index 9becccf85de..285d5379b89 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioC_8814Amp_hp.txt @@ -1,323 +1,323 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xe4000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0EF //63 -0x34 0x490EC //57 -0x34 0x480E9 //51 -0x34 0x4704D //45 -0x34 0x4604A //39 -0x34 0x45047 //33 -0x34 0x4400D //27 -0x34 0x4300A //21 -0x34 0x42007 //15 -0x34 0x41004 //9 -0x34 0x40001 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0EF //63 -0x34 0x290EC //57 -0x34 0x280E9 //51 -0x34 0x2704D //45 -0x34 0x2604A //39 -0x34 0x25047 //33 -0x34 0x2400D //27 -0x34 0x2300A //21 -0x34 0x22007 //15 -0x34 0x21004 //9 -0x34 0x20001 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0ED //63 -0x34 0x090EA //57 -0x34 0x0806D //51 -0x34 0x0706A //45 -0x34 0x06067 //39 -0x34 0x0502A //33 -0x34 0x04027 //27 -0x34 0x0300A //21 -0x34 0x02007 //15 -0x34 0x01004 //9 -0x34 0x00001 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0x4A0EF //63 -0x34 0x490EC //57 -0x34 0x480E9 //51 -0x34 0x4704D //45 -0x34 0x4604A //39 -0x34 0x45047 //33 -0x34 0x4400D //27 -0x34 0x4300A //21 -0x34 0x42007 //15 -0x34 0x41004 //9 -0x34 0x40001 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0x2A0EF //63 -0x34 0x290EC //57 -0x34 0x280E9 //51 -0x34 0x2704D //45 -0x34 0x2604A //39 -0x34 0x25047 //33 -0x34 0x2400D //27 -0x34 0x2300A //21 -0x34 0x22007 //15 -0x34 0x21004 //9 -0x34 0x20001 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x0A0ED //63 -0x34 0x090EA //57 -0x34 0x0806D //51 -0x34 0x0706A //45 -0x34 0x06067 //39 -0x34 0x0502A //33 -0x34 0x04027 //27 -0x34 0x0300A //21 -0x34 0x02007 //15 -0x34 0x01004 //9 -0x34 0x00001 //3 -0xEF 0x00000 -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD PAD tank) -0xEF 0x00008 - - - -0x3C 0x0017e //HP_LB_PA_TANK[2:0] -0x3C 0x0057e //HP_MB_PA_TANK[2:0] -0x3C 0x0087e //HP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 //FDD43 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D1 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xe4000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0EF //63 +0x34 0x490EC //57 +0x34 0x480E9 //51 +0x34 0x4704D //45 +0x34 0x4604A //39 +0x34 0x45047 //33 +0x34 0x4400D //27 +0x34 0x4300A //21 +0x34 0x42007 //15 +0x34 0x41004 //9 +0x34 0x40001 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0EF //63 +0x34 0x290EC //57 +0x34 0x280E9 //51 +0x34 0x2704D //45 +0x34 0x2604A //39 +0x34 0x25047 //33 +0x34 0x2400D //27 +0x34 0x2300A //21 +0x34 0x22007 //15 +0x34 0x21004 //9 +0x34 0x20001 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0ED //63 +0x34 0x090EA //57 +0x34 0x0806D //51 +0x34 0x0706A //45 +0x34 0x06067 //39 +0x34 0x0502A //33 +0x34 0x04027 //27 +0x34 0x0300A //21 +0x34 0x02007 //15 +0x34 0x01004 //9 +0x34 0x00001 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0x4A0EF //63 +0x34 0x490EC //57 +0x34 0x480E9 //51 +0x34 0x4704D //45 +0x34 0x4604A //39 +0x34 0x45047 //33 +0x34 0x4400D //27 +0x34 0x4300A //21 +0x34 0x42007 //15 +0x34 0x41004 //9 +0x34 0x40001 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0x2A0EF //63 +0x34 0x290EC //57 +0x34 0x280E9 //51 +0x34 0x2704D //45 +0x34 0x2604A //39 +0x34 0x25047 //33 +0x34 0x2400D //27 +0x34 0x2300A //21 +0x34 0x22007 //15 +0x34 0x21004 //9 +0x34 0x20001 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x0A0ED //63 +0x34 0x090EA //57 +0x34 0x0806D //51 +0x34 0x0706A //45 +0x34 0x06067 //39 +0x34 0x0502A //33 +0x34 0x04027 //27 +0x34 0x0300A //21 +0x34 0x02007 //15 +0x34 0x01004 //9 +0x34 0x00001 //3 +0xEF 0x00000 +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD PAD tank) +0xEF 0x00008 + + + +0x3C 0x0017e //HP_LB_PA_TANK[2:0] +0x3C 0x0057e //HP_MB_PA_TANK[2:0] +0x3C 0x0087e //HP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 //FDD43 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D1 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A.txt old mode 100755 new mode 100644 index 54d956fb0d1..364e0d97c3a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A_hp.txt old mode 100755 new mode 100644 index 935a575cd43..4732d1e45d2 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814A_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp.txt old mode 100755 new mode 100644 index 2a5357655a9..a39aa463791 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp_hp.txt old mode 100755 new mode 100644 index e355fd77d04..250a56c2a57 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/RadioD_8814Amp_hp.txt @@ -1,328 +1,328 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xec000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0F0 //63 -0x34 0x490ED //57 -0x34 0x480EA //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x4502D //33 -0x34 0x4402A //27 -0x34 0x4300D //21 -0x34 0x4200A //15 -0x34 0x41007 //9 -0x34 0x40004 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0F0 //63 -0x34 0x290ED //57 -0x34 0x280EA //51 -0x34 0x2706D //45 -0x34 0x2606A //39 -0x34 0x2502D //33 -0x34 0x2402A //27 -0x34 0x2300D //21 -0x34 0x2200A //15 -0x34 0x21007 //9 -0x34 0x20004 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0F0 //63 -0x34 0x090ED //57 -0x34 0x080EA //51 -0x34 0x0706D //45 -0x34 0x0606A //39 -0x34 0x0502D //33 -0x34 0x0402A //27 -0x34 0x0300D //21 -0x34 0x0200A //15 -0x34 0x01007 //9 -0x34 0x00004 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0xCA0F0 //63 -0x34 0xC90ED //57 -0x34 0xC80EA //51 -0x34 0xC706D //45 -0x34 0xC606A //39 -0x34 0xC502D //33 -0x34 0xC402A //27 -0x34 0xC3027 //21 -0x34 0xC2024 //15 -0x34 0xC1007 //9 -0x34 0xC0004 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0xAA0F0 //63 -0x34 0xA90ED //57 -0x34 0xA80EA //51 -0x34 0xA706D //45 -0x34 0xA606A //39 -0x34 0xA502D //33 -0x34 0xA402A //27 -0x34 0xA3027 //21 -0x34 0xA2024 //15 -0x34 0xA1007 //9 -0x34 0xA0004 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x8A0F0 //63 -0x34 0x890ED //57 -0x34 0x880EA //51 -0x34 0x8706D //45 -0x34 0x8606A //39 -0x34 0x8502D //33 -0x34 0x8402A //27 -0x34 0x83027 //21 -0x34 0x82024 //15 -0x34 0x81007 //9 -0x34 0x80004 //3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD PAD tank) -0xEF 0x00008 - - -//Table_5G_RTX_Tank_S0(PA output tank) - -0x3C 0x0017e //HP_LB_PA_TANK[2:0](3C[9:7]) -0x3C 0x00576 //HP_MB_PA_TANK[2:0] -0x3C 0x00872 //HP_HB_PA_TANK[2:0] -0x3C 0x0117d //LP_LB_PA_TANK[2:0] -0x3C 0x0157d //LP_MB_PA_TANK[2:0] -0x3C 0x0187d //LP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 //FDD43 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D1 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xec000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0F0 //63 +0x34 0x490ED //57 +0x34 0x480EA //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x4502D //33 +0x34 0x4402A //27 +0x34 0x4300D //21 +0x34 0x4200A //15 +0x34 0x41007 //9 +0x34 0x40004 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0F0 //63 +0x34 0x290ED //57 +0x34 0x280EA //51 +0x34 0x2706D //45 +0x34 0x2606A //39 +0x34 0x2502D //33 +0x34 0x2402A //27 +0x34 0x2300D //21 +0x34 0x2200A //15 +0x34 0x21007 //9 +0x34 0x20004 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0F0 //63 +0x34 0x090ED //57 +0x34 0x080EA //51 +0x34 0x0706D //45 +0x34 0x0606A //39 +0x34 0x0502D //33 +0x34 0x0402A //27 +0x34 0x0300D //21 +0x34 0x0200A //15 +0x34 0x01007 //9 +0x34 0x00004 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0xCA0F0 //63 +0x34 0xC90ED //57 +0x34 0xC80EA //51 +0x34 0xC706D //45 +0x34 0xC606A //39 +0x34 0xC502D //33 +0x34 0xC402A //27 +0x34 0xC3027 //21 +0x34 0xC2024 //15 +0x34 0xC1007 //9 +0x34 0xC0004 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0xAA0F0 //63 +0x34 0xA90ED //57 +0x34 0xA80EA //51 +0x34 0xA706D //45 +0x34 0xA606A //39 +0x34 0xA502D //33 +0x34 0xA402A //27 +0x34 0xA3027 //21 +0x34 0xA2024 //15 +0x34 0xA1007 //9 +0x34 0xA0004 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x8A0F0 //63 +0x34 0x890ED //57 +0x34 0x880EA //51 +0x34 0x8706D //45 +0x34 0x8606A //39 +0x34 0x8502D //33 +0x34 0x8402A //27 +0x34 0x83027 //21 +0x34 0x82024 //15 +0x34 0x81007 //9 +0x34 0x80004 //3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD PAD tank) +0xEF 0x00008 + + +//Table_5G_RTX_Tank_S0(PA output tank) + +0x3C 0x0017e //HP_LB_PA_TANK[2:0](3C[9:7]) +0x3C 0x00576 //HP_MB_PA_TANK[2:0] +0x3C 0x00872 //HP_HB_PA_TANK[2:0] +0x3C 0x0117d //LP_LB_PA_TANK[2:0] +0x3C 0x0157d //LP_MB_PA_TANK[2:0] +0x3C 0x0187d //LP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 //FDD43 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D1 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814A.txt old mode 100755 new mode 100644 index 21e8e43feb8..9b6c7fdaa60 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814A.txt @@ -1,325 +1,325 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 18 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 18 16 NA -CH159 18 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 18 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 18 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 18 16 NA +CH159 18 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 18 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp.txt old mode 100755 new mode 100644 index 58fff119fc3..4ec098adbd4 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA 23 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 23 23 23 -CH02 23 23 23 -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 23 23 -CH04 23 23 23 -CH05 23 23 23 -CH06 23 23 23 -CH07 23 23 23 -CH08 23 23 23 -CH09 23 23 23 -CH10 23 23 23 -CH11 23 23 23 -CH12 NA 23 23 -CH13 NA 23 23 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 23 23 -CH40 23 23 23 -CH44 23 23 23 -CH48 23 23 23 -//5G Band 2 -CH52 23 23 23 -CH56 23 23 23 -CH60 23 23 23 -CH64 23 23 23 -//5G Band 3 -CH100 23 23 23 -CH104 23 23 23 -CH108 23 23 23 -CH112 23 23 23 -CH116 23 23 23 -CH120 23 23 23 -CH124 23 23 23 -CH128 23 23 23 -CH132 23 23 23 -CH136 23 23 23 -CH140 23 23 23 -//5G Band 4 -CH149 23 23 NA -CH153 23 23 NA -CH157 23 23 NA -CH161 23 23 NA -CH165 23 23 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 23 23 -CH40 23 23 23 -CH44 23 23 23 -CH48 23 23 23 -//5G Band 2 -CH52 23 23 23 -CH56 23 23 23 -CH60 23 23 23 -CH64 23 23 23 -//5G Band 3 -CH100 23 23 23 -CH104 23 23 23 -CH108 23 23 23 -CH112 23 23 23 -CH116 23 23 23 -CH120 23 23 23 -CH124 23 23 23 -CH128 23 23 23 -CH132 23 23 23 -CH136 23 23 23 -CH140 23 23 23 -//5G Band 4 -CH149 23 23 NA -CH153 23 23 NA -CH157 23 23 NA -CH161 23 23 NA -CH165 23 23 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 23 23 -CH40 23 23 23 -CH44 23 23 23 -CH48 23 23 23 -//5G Band 2 -CH52 23 23 23 -CH56 23 23 23 -CH60 23 23 23 -CH64 23 23 23 -//5G Band 3 -CH100 23 23 23 -CH104 23 23 23 -CH108 23 23 23 -CH112 23 23 23 -CH116 23 23 23 -CH120 23 23 23 -CH124 23 23 23 -CH128 23 23 23 -CH132 23 23 23 -CH136 23 23 23 -CH140 23 23 23 -//5G Band 4 -CH149 23 23 NA -CH153 23 23 NA -CH157 23 23 NA -CH161 23 23 NA -CH165 23 23 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 23 23 -CH40 23 23 23 -CH44 23 23 23 -CH48 23 23 23 -//5G Band 2 -CH52 23 23 23 -CH56 23 23 23 -CH60 23 23 23 -CH64 23 23 23 -//5G Band 3 -CH100 23 23 23 -CH104 23 23 23 -CH108 23 23 23 -CH112 23 23 23 -CH116 23 23 23 -CH120 23 23 23 -CH124 23 23 23 -CH128 23 23 23 -CH132 23 23 23 -CH136 23 23 23 -CH140 23 23 23 -//5G Band 4 -CH149 23 23 NA -CH153 23 23 NA -CH157 23 23 NA -CH161 23 23 NA -CH165 23 23 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 23 23 -CH40 23 23 23 -CH44 23 23 23 -CH48 23 23 23 -//5G Band 2 -CH52 23 23 23 -CH56 23 23 23 -CH60 23 23 23 -CH64 23 23 23 -//5G Band 3 -CH100 23 23 23 -CH104 23 23 23 -CH108 23 23 23 -CH112 23 23 23 -CH116 23 23 23 -CH120 23 23 23 -CH124 23 23 23 -CH128 23 23 23 -CH132 23 23 23 -CH136 23 23 23 -CH140 23 23 23 -//5G Band 4 -CH149 23 23 NA -CH153 23 23 NA -CH157 23 23 NA -CH161 23 23 NA -CH165 23 23 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 23 23 -CH46 23 23 23 -//5G Band 2 -CH54 23 23 23 -CH62 23 23 23 -//5G Band 3 -CH102 23 23 23 -CH110 23 23 23 -CH118 23 23 23 -CH126 23 23 23 -CH134 23 23 23 -//5G Band 4 -CH151 23 23 NA -CH159 23 23 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 23 23 -CH46 23 23 23 -//5G Band 2 -CH54 23 23 23 -CH62 23 23 23 -//5G Band 3 -CH102 23 23 23 -CH110 23 23 23 -CH118 23 23 23 -CH126 23 23 23 -CH134 23 23 23 -//5G Band 4 -CH151 23 23 NA -CH159 23 23 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 23 23 -CH46 23 23 23 -//5G Band 2 -CH54 23 23 23 -CH62 23 23 23 -//5G Band 3 -CH102 23 23 23 -CH110 23 23 23 -CH118 23 23 23 -CH126 23 23 23 -CH134 23 23 23 -//5G Band 4 -CH151 23 23 NA -CH159 23 23 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 23 23 -CH46 23 23 23 -//5G Band 2 -CH54 23 23 23 -CH62 23 23 23 -//5G Band 3 -CH102 23 23 23 -CH110 23 23 23 -CH118 23 23 23 -CH126 23 23 23 -CH134 23 23 23 -//5G Band 4 -CH151 23 23 NA -CH159 23 23 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 23 23 -//5G Band 2 -CH58 23 23 23 -//5G Band 3 -CH106 23 23 23 -CH122 23 23 23 -//5G Band 4 -CH155 23 23 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 23 23 -//5G Band 2 -CH58 23 23 23 -//5G Band 3 -CH106 23 23 23 -CH122 23 23 23 -//5G Band 4 -CH155 23 23 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 23 23 -//5G Band 2 -CH58 23 23 23 -//5G Band 3 -CH106 23 23 23 -CH122 23 23 23 -//5G Band 4 -CH155 23 23 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 23 23 -//5G Band 2 -CH58 23 23 23 -//5G Band 3 -CH106 23 23 23 -CH122 23 23 23 -//5G Band 4 -CH155 23 23 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA 23 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 23 23 23 +CH02 23 23 23 +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 23 23 +CH04 23 23 23 +CH05 23 23 23 +CH06 23 23 23 +CH07 23 23 23 +CH08 23 23 23 +CH09 23 23 23 +CH10 23 23 23 +CH11 23 23 23 +CH12 NA 23 23 +CH13 NA 23 23 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 23 23 +CH40 23 23 23 +CH44 23 23 23 +CH48 23 23 23 +//5G Band 2 +CH52 23 23 23 +CH56 23 23 23 +CH60 23 23 23 +CH64 23 23 23 +//5G Band 3 +CH100 23 23 23 +CH104 23 23 23 +CH108 23 23 23 +CH112 23 23 23 +CH116 23 23 23 +CH120 23 23 23 +CH124 23 23 23 +CH128 23 23 23 +CH132 23 23 23 +CH136 23 23 23 +CH140 23 23 23 +//5G Band 4 +CH149 23 23 NA +CH153 23 23 NA +CH157 23 23 NA +CH161 23 23 NA +CH165 23 23 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 23 23 +CH40 23 23 23 +CH44 23 23 23 +CH48 23 23 23 +//5G Band 2 +CH52 23 23 23 +CH56 23 23 23 +CH60 23 23 23 +CH64 23 23 23 +//5G Band 3 +CH100 23 23 23 +CH104 23 23 23 +CH108 23 23 23 +CH112 23 23 23 +CH116 23 23 23 +CH120 23 23 23 +CH124 23 23 23 +CH128 23 23 23 +CH132 23 23 23 +CH136 23 23 23 +CH140 23 23 23 +//5G Band 4 +CH149 23 23 NA +CH153 23 23 NA +CH157 23 23 NA +CH161 23 23 NA +CH165 23 23 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 23 23 +CH40 23 23 23 +CH44 23 23 23 +CH48 23 23 23 +//5G Band 2 +CH52 23 23 23 +CH56 23 23 23 +CH60 23 23 23 +CH64 23 23 23 +//5G Band 3 +CH100 23 23 23 +CH104 23 23 23 +CH108 23 23 23 +CH112 23 23 23 +CH116 23 23 23 +CH120 23 23 23 +CH124 23 23 23 +CH128 23 23 23 +CH132 23 23 23 +CH136 23 23 23 +CH140 23 23 23 +//5G Band 4 +CH149 23 23 NA +CH153 23 23 NA +CH157 23 23 NA +CH161 23 23 NA +CH165 23 23 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 23 23 +CH40 23 23 23 +CH44 23 23 23 +CH48 23 23 23 +//5G Band 2 +CH52 23 23 23 +CH56 23 23 23 +CH60 23 23 23 +CH64 23 23 23 +//5G Band 3 +CH100 23 23 23 +CH104 23 23 23 +CH108 23 23 23 +CH112 23 23 23 +CH116 23 23 23 +CH120 23 23 23 +CH124 23 23 23 +CH128 23 23 23 +CH132 23 23 23 +CH136 23 23 23 +CH140 23 23 23 +//5G Band 4 +CH149 23 23 NA +CH153 23 23 NA +CH157 23 23 NA +CH161 23 23 NA +CH165 23 23 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 23 23 +CH40 23 23 23 +CH44 23 23 23 +CH48 23 23 23 +//5G Band 2 +CH52 23 23 23 +CH56 23 23 23 +CH60 23 23 23 +CH64 23 23 23 +//5G Band 3 +CH100 23 23 23 +CH104 23 23 23 +CH108 23 23 23 +CH112 23 23 23 +CH116 23 23 23 +CH120 23 23 23 +CH124 23 23 23 +CH128 23 23 23 +CH132 23 23 23 +CH136 23 23 23 +CH140 23 23 23 +//5G Band 4 +CH149 23 23 NA +CH153 23 23 NA +CH157 23 23 NA +CH161 23 23 NA +CH165 23 23 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 23 23 +CH46 23 23 23 +//5G Band 2 +CH54 23 23 23 +CH62 23 23 23 +//5G Band 3 +CH102 23 23 23 +CH110 23 23 23 +CH118 23 23 23 +CH126 23 23 23 +CH134 23 23 23 +//5G Band 4 +CH151 23 23 NA +CH159 23 23 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 23 23 +CH46 23 23 23 +//5G Band 2 +CH54 23 23 23 +CH62 23 23 23 +//5G Band 3 +CH102 23 23 23 +CH110 23 23 23 +CH118 23 23 23 +CH126 23 23 23 +CH134 23 23 23 +//5G Band 4 +CH151 23 23 NA +CH159 23 23 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 23 23 +CH46 23 23 23 +//5G Band 2 +CH54 23 23 23 +CH62 23 23 23 +//5G Band 3 +CH102 23 23 23 +CH110 23 23 23 +CH118 23 23 23 +CH126 23 23 23 +CH134 23 23 23 +//5G Band 4 +CH151 23 23 NA +CH159 23 23 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 23 23 +CH46 23 23 23 +//5G Band 2 +CH54 23 23 23 +CH62 23 23 23 +//5G Band 3 +CH102 23 23 23 +CH110 23 23 23 +CH118 23 23 23 +CH126 23 23 23 +CH134 23 23 23 +//5G Band 4 +CH151 23 23 NA +CH159 23 23 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 23 23 +//5G Band 2 +CH58 23 23 23 +//5G Band 3 +CH106 23 23 23 +CH122 23 23 23 +//5G Band 4 +CH155 23 23 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 23 23 +//5G Band 2 +CH58 23 23 23 +//5G Band 3 +CH106 23 23 23 +CH122 23 23 23 +//5G Band 4 +CH155 23 23 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 23 23 +//5G Band 2 +CH58 23 23 23 +//5G Band 3 +CH106 23 23 23 +CH122 23 23 23 +//5G Band 4 +CH155 23 23 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 23 23 +//5G Band 2 +CH58 23 23 23 +//5G Band 3 +CH106 23 23 23 +CH122 23 23 23 +//5G Band 4 +CH155 23 23 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_TXBF.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_TXBF.txt old mode 100755 new mode 100644 index 18329e65a8d..7e60f83513a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_TXBF.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_TXBF.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 21 9 20 -CH02 25 9 20 -CH03 25 9 20 -CH04 25 9 20 -CH05 25 9 20 -CH06 25 9 20 -CH07 25 9 20 -CH08 25 9 20 -CH09 25 9 20 -CH10 25 9 20 -CH11 19 9 20 -CH12 NA 9 20 -CH13 NA 9 20 -CH14 NA NA 20 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 11 20 -CH02 23 11 20 -CH03 23 11 20 -CH04 23 11 20 -CH05 23 11 20 -CH06 23 11 20 -CH07 23 11 20 -CH08 23 11 20 -CH09 23 11 20 -CH10 23 11 20 -CH11 16 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 16 11 20 -CH02 21 11 20 -CH03 21 11 20 -CH04 21 11 20 -CH05 21 11 20 -CH06 21 11 20 -CH07 21 11 20 -CH08 21 11 20 -CH09 21 11 20 -CH10 21 11 20 -CH11 17 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 11 20 -CH02 21 11 20 -CH03 21 11 20 -CH04 21 11 20 -CH05 21 11 20 -CH06 21 11 20 -CH07 21 11 20 -CH08 21 11 20 -CH09 21 11 20 -CH10 21 11 20 -CH11 17 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 16 11 20 -CH02 21 11 20 -CH03 21 11 20 -CH04 21 11 20 -CH05 21 11 20 -CH06 21 11 20 -CH07 21 11 20 -CH08 21 11 20 -CH09 21 11 20 -CH10 21 11 20 -CH11 17 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 20 20 20 -CH02 20 20 20 -CH03 20 20 20 -CH04 20 20 20 -CH05 20 20 20 -CH06 20 20 20 -CH07 20 20 20 -CH08 20 20 20 -CH09 20 20 20 -CH10 20 20 20 -CH11 20 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 11 20 -CH04 18 11 20 -CH05 18 11 20 -CH06 18 11 20 -CH07 18 11 20 -CH08 18 11 20 -CH09 18 11 20 -CH10 18 11 20 -CH11 16 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 11 20 -CH04 18 11 20 -CH05 18 11 20 -CH06 18 11 20 -CH07 18 11 20 -CH08 18 11 20 -CH09 18 11 20 -CH10 18 11 20 -CH11 16 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 11 20 -CH04 18 11 20 -CH05 18 11 20 -CH06 18 11 20 -CH07 18 11 20 -CH08 18 11 20 -CH09 18 11 20 -CH10 18 11 20 -CH11 16 11 20 -CH12 NA 11 20 -CH13 NA 11 20 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 20 20 20 -CH04 20 20 20 -CH05 20 20 20 -CH06 20 20 20 -CH07 20 20 20 -CH08 20 20 20 -CH09 20 20 20 -CH10 20 20 20 -CH11 20 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 21 13 20 -CH40 21 13 20 -CH44 21 13 20 -CH48 21 13 20 -//5G Band 2 -CH52 23 13 20 -CH56 23 13 20 -CH60 23 13 20 -CH64 23 13 20 -//5G Band 3 -CH100 23 21 20 -CH104 23 21 20 -CH108 23 21 20 -CH112 23 21 20 -CH116 23 21 20 -CH120 23 21 20 -CH124 23 21 20 -CH128 23 21 20 -CH132 23 21 20 -CH136 23 21 20 -CH140 23 21 20 -//5G Band 4 -CH149 24 23 NA -CH153 23 22 NA -CH157 23 22 NA -CH161 23 22 NA -CH165 23 22 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 13 20 -CH40 18 13 20 -CH44 18 13 20 -CH48 18 13 20 -//5G Band 2 -CH52 23 13 20 -CH56 23 13 20 -CH60 23 13 20 -CH64 23 13 20 -//5G Band 3 -CH100 23 21 20 -CH104 23 21 20 -CH108 23 21 20 -CH112 23 21 20 -CH116 23 21 20 -CH120 23 21 20 -CH124 23 21 20 -CH128 23 21 20 -CH132 23 21 20 -CH136 23 21 20 -CH140 23 20 20 -//5G Band 4 -CH149 21 22 NA -CH153 21 22 NA -CH157 21 24 NA -CH161 21 24 NA -CH165 21 24 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 13 20 -CH40 18 13 20 -CH44 18 13 20 -CH48 18 13 20 -//5G Band 2 -CH52 23 13 20 -CH56 23 13 20 -CH60 23 13 20 -CH64 23 13 20 -//5G Band 3 -CH100 23 21 20 -CH104 23 21 20 -CH108 23 21 20 -CH112 23 21 20 -CH116 23 21 20 -CH120 23 21 20 -CH124 23 21 20 -CH128 23 21 20 -CH132 23 21 20 -CH136 23 21 20 -CH140 23 20 20 -//5G Band 4 -CH149 21 22 NA -CH153 21 22 NA -CH157 21 24 NA -CH161 21 24 NA -CH165 21 24 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 13 20 -CH40 18 13 20 -CH44 18 13 20 -CH48 18 13 20 -//5G Band 2 -CH52 23 13 20 -CH56 23 13 20 -CH60 23 13 20 -CH64 23 13 20 -//5G Band 3 -CH100 23 21 20 -CH104 23 21 20 -CH108 23 21 20 -CH112 23 21 20 -CH116 23 21 20 -CH120 23 21 20 -CH124 23 21 20 -CH128 23 21 20 -CH132 23 21 20 -CH136 23 21 20 -CH140 23 20 20 -//5G Band 4 -CH149 21 22 NA -CH153 21 22 NA -CH157 21 24 NA -CH161 21 24 NA -CH165 21 24 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 11 20 -CH40 23 11 20 -CH44 23 11 20 -CH48 23 11 20 -//5G Band 2 -CH52 23 12 20 -CH56 23 12 20 -CH60 23 12 20 -CH64 23 12 20 -//5G Band 3 -CH100 23 19 20 -CH104 23 19 20 -CH108 23 19 20 -CH112 23 19 20 -CH116 23 19 20 -CH120 23 19 20 -CH124 23 19 20 -CH128 23 19 20 -CH132 23 19 20 -CH136 23 19 20 -CH140 23 19 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 13 20 -CH46 20 13 20 -//5G Band 2 -CH54 23 14 20 -CH62 23 14 20 -//5G Band 3 -CH102 23 21 20 -CH110 23 21 20 -CH118 23 21 20 -CH126 23 21 20 -CH134 23 21 20 -//5G Band 4 -CH151 21 20 NA -CH159 22 22 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 13 20 -CH46 20 13 20 -//5G Band 2 -CH54 23 14 20 -CH62 23 14 20 -//5G Band 3 -CH102 23 21 20 -CH110 23 21 20 -CH118 23 21 20 -CH126 23 21 20 -CH134 23 21 20 -//5G Band 4 -CH151 21 20 NA -CH159 22 22 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 13 20 -CH46 20 13 20 -//5G Band 2 -CH54 23 14 20 -CH62 23 14 20 -//5G Band 3 -CH102 23 21 20 -CH110 23 21 20 -CH118 23 21 20 -CH126 23 21 20 -CH134 23 21 20 -//5G Band 4 -CH151 21 20 NA -CH159 22 22 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 16 14 20 -//5G Band 2 -CH58 23 13 20 -//5G Band 3 -CH106 23 22 20 -CH122 23 22 20 -//5G Band 4 -CH155 21 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 16 14 20 -//5G Band 2 -CH58 23 13 20 -//5G Band 3 -CH106 23 22 20 -CH122 23 22 -//5G Band 4 -CH155 21 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 16 14 20 -//5G Band 2 -CH58 23 13 20 -//5G Band 3 -CH106 23 22 20 -CH122 23 22 20 -//5G Band 4 -CH155 21 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 12 20 -//5G Band 2 -CH58 23 11 20 -//5G Band 3 -CH106 23 19 20 -CH122 23 19 20 -//5G Band 4 -CH155 23 20 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 21 9 20 +CH02 25 9 20 +CH03 25 9 20 +CH04 25 9 20 +CH05 25 9 20 +CH06 25 9 20 +CH07 25 9 20 +CH08 25 9 20 +CH09 25 9 20 +CH10 25 9 20 +CH11 19 9 20 +CH12 NA 9 20 +CH13 NA 9 20 +CH14 NA NA 20 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 11 20 +CH02 23 11 20 +CH03 23 11 20 +CH04 23 11 20 +CH05 23 11 20 +CH06 23 11 20 +CH07 23 11 20 +CH08 23 11 20 +CH09 23 11 20 +CH10 23 11 20 +CH11 16 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 16 11 20 +CH02 21 11 20 +CH03 21 11 20 +CH04 21 11 20 +CH05 21 11 20 +CH06 21 11 20 +CH07 21 11 20 +CH08 21 11 20 +CH09 21 11 20 +CH10 21 11 20 +CH11 17 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 11 20 +CH02 21 11 20 +CH03 21 11 20 +CH04 21 11 20 +CH05 21 11 20 +CH06 21 11 20 +CH07 21 11 20 +CH08 21 11 20 +CH09 21 11 20 +CH10 21 11 20 +CH11 17 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 16 11 20 +CH02 21 11 20 +CH03 21 11 20 +CH04 21 11 20 +CH05 21 11 20 +CH06 21 11 20 +CH07 21 11 20 +CH08 21 11 20 +CH09 21 11 20 +CH10 21 11 20 +CH11 17 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 20 20 20 +CH02 20 20 20 +CH03 20 20 20 +CH04 20 20 20 +CH05 20 20 20 +CH06 20 20 20 +CH07 20 20 20 +CH08 20 20 20 +CH09 20 20 20 +CH10 20 20 20 +CH11 20 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 11 20 +CH04 18 11 20 +CH05 18 11 20 +CH06 18 11 20 +CH07 18 11 20 +CH08 18 11 20 +CH09 18 11 20 +CH10 18 11 20 +CH11 16 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 11 20 +CH04 18 11 20 +CH05 18 11 20 +CH06 18 11 20 +CH07 18 11 20 +CH08 18 11 20 +CH09 18 11 20 +CH10 18 11 20 +CH11 16 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 11 20 +CH04 18 11 20 +CH05 18 11 20 +CH06 18 11 20 +CH07 18 11 20 +CH08 18 11 20 +CH09 18 11 20 +CH10 18 11 20 +CH11 16 11 20 +CH12 NA 11 20 +CH13 NA 11 20 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 20 20 20 +CH04 20 20 20 +CH05 20 20 20 +CH06 20 20 20 +CH07 20 20 20 +CH08 20 20 20 +CH09 20 20 20 +CH10 20 20 20 +CH11 20 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 21 13 20 +CH40 21 13 20 +CH44 21 13 20 +CH48 21 13 20 +//5G Band 2 +CH52 23 13 20 +CH56 23 13 20 +CH60 23 13 20 +CH64 23 13 20 +//5G Band 3 +CH100 23 21 20 +CH104 23 21 20 +CH108 23 21 20 +CH112 23 21 20 +CH116 23 21 20 +CH120 23 21 20 +CH124 23 21 20 +CH128 23 21 20 +CH132 23 21 20 +CH136 23 21 20 +CH140 23 21 20 +//5G Band 4 +CH149 24 23 NA +CH153 23 22 NA +CH157 23 22 NA +CH161 23 22 NA +CH165 23 22 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 13 20 +CH40 18 13 20 +CH44 18 13 20 +CH48 18 13 20 +//5G Band 2 +CH52 23 13 20 +CH56 23 13 20 +CH60 23 13 20 +CH64 23 13 20 +//5G Band 3 +CH100 23 21 20 +CH104 23 21 20 +CH108 23 21 20 +CH112 23 21 20 +CH116 23 21 20 +CH120 23 21 20 +CH124 23 21 20 +CH128 23 21 20 +CH132 23 21 20 +CH136 23 21 20 +CH140 23 20 20 +//5G Band 4 +CH149 21 22 NA +CH153 21 22 NA +CH157 21 24 NA +CH161 21 24 NA +CH165 21 24 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 13 20 +CH40 18 13 20 +CH44 18 13 20 +CH48 18 13 20 +//5G Band 2 +CH52 23 13 20 +CH56 23 13 20 +CH60 23 13 20 +CH64 23 13 20 +//5G Band 3 +CH100 23 21 20 +CH104 23 21 20 +CH108 23 21 20 +CH112 23 21 20 +CH116 23 21 20 +CH120 23 21 20 +CH124 23 21 20 +CH128 23 21 20 +CH132 23 21 20 +CH136 23 21 20 +CH140 23 20 20 +//5G Band 4 +CH149 21 22 NA +CH153 21 22 NA +CH157 21 24 NA +CH161 21 24 NA +CH165 21 24 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 13 20 +CH40 18 13 20 +CH44 18 13 20 +CH48 18 13 20 +//5G Band 2 +CH52 23 13 20 +CH56 23 13 20 +CH60 23 13 20 +CH64 23 13 20 +//5G Band 3 +CH100 23 21 20 +CH104 23 21 20 +CH108 23 21 20 +CH112 23 21 20 +CH116 23 21 20 +CH120 23 21 20 +CH124 23 21 20 +CH128 23 21 20 +CH132 23 21 20 +CH136 23 21 20 +CH140 23 20 20 +//5G Band 4 +CH149 21 22 NA +CH153 21 22 NA +CH157 21 24 NA +CH161 21 24 NA +CH165 21 24 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 11 20 +CH40 23 11 20 +CH44 23 11 20 +CH48 23 11 20 +//5G Band 2 +CH52 23 12 20 +CH56 23 12 20 +CH60 23 12 20 +CH64 23 12 20 +//5G Band 3 +CH100 23 19 20 +CH104 23 19 20 +CH108 23 19 20 +CH112 23 19 20 +CH116 23 19 20 +CH120 23 19 20 +CH124 23 19 20 +CH128 23 19 20 +CH132 23 19 20 +CH136 23 19 20 +CH140 23 19 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 13 20 +CH46 20 13 20 +//5G Band 2 +CH54 23 14 20 +CH62 23 14 20 +//5G Band 3 +CH102 23 21 20 +CH110 23 21 20 +CH118 23 21 20 +CH126 23 21 20 +CH134 23 21 20 +//5G Band 4 +CH151 21 20 NA +CH159 22 22 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 13 20 +CH46 20 13 20 +//5G Band 2 +CH54 23 14 20 +CH62 23 14 20 +//5G Band 3 +CH102 23 21 20 +CH110 23 21 20 +CH118 23 21 20 +CH126 23 21 20 +CH134 23 21 20 +//5G Band 4 +CH151 21 20 NA +CH159 22 22 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 13 20 +CH46 20 13 20 +//5G Band 2 +CH54 23 14 20 +CH62 23 14 20 +//5G Band 3 +CH102 23 21 20 +CH110 23 21 20 +CH118 23 21 20 +CH126 23 21 20 +CH134 23 21 20 +//5G Band 4 +CH151 21 20 NA +CH159 22 22 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 16 14 20 +//5G Band 2 +CH58 23 13 20 +//5G Band 3 +CH106 23 22 20 +CH122 23 22 20 +//5G Band 4 +CH155 21 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 16 14 20 +//5G Band 2 +CH58 23 13 20 +//5G Band 3 +CH106 23 22 20 +CH122 23 22 +//5G Band 4 +CH155 21 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 16 14 20 +//5G Band 2 +CH58 23 13 20 +//5G Band 3 +CH106 23 22 20 +CH122 23 22 20 +//5G Band 4 +CH155 21 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 12 20 +//5G Band 2 +CH58 23 11 20 +//5G Band 3 +CH106 23 19 20 +CH122 23 19 20 +//5G Band 4 +CH155 23 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type0.txt old mode 100755 new mode 100644 index cd47a6ed8ad..d0797b3aa7e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type0.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type2.txt old mode 100755 new mode 100644 index d3511727d63..447172b023b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type2.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type3.txt old mode 100755 new mode 100644 index 5ad3ae38e30..059e12cbdd3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type3.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA 20 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA 20 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type4.txt old mode 100755 new mode 100644 index d3511727d63..447172b023b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type4.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type5.txt old mode 100755 new mode 100644 index 4fc4d2d9204..7c377fa8eeb --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type5.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA 20 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA 20 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type7.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type7.txt index 095d6c8c39e..125af35d9e6 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type7.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type7.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 22 16 16 -CH02 26 16 16 -CH03 26 16 16 -CH04 26 16 16 -CH05 26 16 16 -CH06 26 16 16 -CH07 26 16 16 -CH08 26 16 16 -CH09 26 16 16 -CH10 26 16 16 -CH11 22 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 19 16 16 -CH02 23 16 16 -CH03 23 16 16 -CH04 23 16 16 -CH05 23 16 16 -CH06 23 16 16 -CH07 23 16 16 -CH08 23 16 16 -CH09 23 16 16 -CH10 23 16 16 -CH11 19 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 23 16 16 -CH03 23 16 16 -CH04 23 16 16 -CH05 23 16 16 -CH06 23 16 16 -CH07 23 16 16 -CH08 23 16 16 -CH09 23 16 16 -CH10 23 16 16 -CH11 17 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 22 15 15 -CH03 22 15 15 -CH04 22 15 15 -CH05 22 15 15 -CH06 22 15 15 -CH07 22 15 15 -CH08 22 15 15 -CH09 22 15 15 -CH10 22 15 15 -CH11 16 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 21 14 14 -CH03 21 14 14 -CH04 21 14 14 -CH05 21 14 14 -CH06 21 14 14 -CH07 21 14 14 -CH08 21 14 14 -CH09 21 14 14 -CH10 21 14 14 -CH11 15 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 20 13 13 -CH03 20 13 13 -CH04 20 13 13 -CH05 20 13 13 -CH06 20 13 13 -CH07 20 13 13 -CH08 20 13 13 -CH09 20 13 13 -CH10 20 13 13 -CH11 14 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 16 16 -CH04 20 16 16 -CH05 20 16 16 -CH06 20 16 16 -CH07 20 16 16 -CH08 20 16 16 -CH09 20 16 16 -CH10 20 16 16 -CH11 17 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 15 15 -CH04 19 15 15 -CH05 19 15 15 -CH06 19 15 15 -CH07 19 15 15 -CH08 19 15 15 -CH09 19 15 15 -CH10 19 15 15 -CH11 16 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 14 14 -CH04 18 14 14 -CH05 18 14 14 -CH06 18 14 14 -CH07 18 14 14 -CH08 18 14 14 -CH09 18 14 14 -CH10 18 14 14 -CH11 15 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 13 13 -CH04 18 13 13 -CH05 18 13 13 -CH06 18 13 13 -CH07 18 13 13 -CH08 18 13 13 -CH09 18 13 13 -CH10 18 13 13 -CH11 15 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 19 16 16 -CH40 19 16 16 -CH44 19 16 16 -CH48 19 16 16 -//5G Band 2 -CH52 19 16 16 -CH56 19 16 16 -CH60 19 16 16 -CH64 19 16 16 -//5G Band 3 -CH100 18 16 16 -CH104 18 16 16 -CH108 18 16 16 -CH112 18 16 16 -CH116 18 16 16 -CH120 18 16 16 -CH124 18 16 16 -CH128 18 16 16 -CH132 18 16 16 -CH136 18 16 16 -CH140 18 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 16 16 -CH40 18 16 16 -CH44 18 16 16 -CH48 18 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 18 16 16 -CH60 18 16 16 -CH64 18 16 16 -//5G Band 3 -CH100 18 16 16 -CH104 18 16 16 -CH108 18 16 16 -CH112 18 16 16 -CH116 18 16 16 -CH120 18 16 16 -CH124 18 16 16 -CH128 18 16 16 -CH132 18 16 16 -CH136 18 16 16 -CH140 17 16 16 -//5G Band 4 -CH149 16 16 NA -CH153 19 16 NA -CH157 19 16 NA -CH161 19 16 NA -CH165 19 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 15 15 -CH40 17 15 15 -CH44 17 15 15 -CH48 17 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 17 15 15 -CH60 17 15 15 -CH64 17 15 15 -//5G Band 3 -CH100 17 15 15 -CH104 17 15 15 -CH108 17 15 15 -CH112 17 15 15 -CH116 17 15 15 -CH120 17 15 15 -CH124 17 15 15 -CH128 17 15 15 -CH132 17 15 15 -CH136 17 15 15 -CH140 16 15 15 -//5G Band 4 -CH149 15 15 NA -CH153 18 15 NA -CH157 18 15 NA -CH161 18 15 NA -CH165 18 15 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 16 14 14 -CH40 16 14 14 -CH44 16 14 14 -CH48 16 14 14 -//5G Band 2 -CH52 16 14 14 -CH56 16 14 14 -CH60 16 14 14 -CH64 16 14 14 -//5G Band 3 -CH100 16 14 14 -CH104 16 14 14 -CH108 16 14 14 -CH112 16 14 14 -CH116 16 14 14 -CH120 16 14 14 -CH124 16 14 14 -CH128 16 14 14 -CH132 16 14 14 -CH136 16 14 14 -CH140 15 14 14 -//5G Band 4 -CH149 14 14 NA -CH153 17 14 NA -CH157 17 14 NA -CH161 17 14 NA -CH165 17 14 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 13 13 -CH40 15 13 13 -CH44 15 13 13 -CH48 15 13 13 -//5G Band 2 -CH52 15 13 13 -CH56 15 13 13 -CH60 15 13 13 -CH64 15 13 13 -//5G Band 3 -CH100 15 13 13 -CH104 15 13 13 -CH108 15 13 13 -CH112 15 13 13 -CH116 15 13 13 -CH120 15 13 13 -CH124 15 13 13 -CH128 15 13 13 -CH132 15 13 13 -CH136 15 13 13 -CH140 14 13 13 -//5G Band 4 -CH149 13 13 NA -CH153 16 13 NA -CH157 16 13 NA -CH161 16 13 NA -CH165 16 13 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 16 16 -CH46 16 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 15 16 16 -CH110 19 16 16 -CH118 19 16 16 -CH126 19 16 16 -CH134 19 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 15 15 -CH46 15 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 14 15 15 -//5G Band 3 -CH102 14 15 15 -CH110 18 15 15 -CH118 18 15 15 -CH126 18 15 15 -CH134 18 15 15 -//5G Band 4 -CH151 15 15 NA -CH159 15 15 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 14 14 -CH46 14 14 14 -//5G Band 2 -CH54 14 14 14 -CH62 13 14 14 -//5G Band 3 -CH102 13 14 14 -CH110 17 14 14 -CH118 17 14 14 -CH126 17 14 14 -CH134 17 14 14 -//5G Band 4 -CH151 14 14 NA -CH159 14 14 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 13 13 13 -CH46 13 13 13 -//5G Band 2 -CH54 13 13 13 -CH62 12 13 13 -//5G Band 3 -CH102 12 13 13 -CH110 16 13 13 -CH118 16 13 13 -CH126 16 13 13 -CH134 16 13 13 -//5G Band 4 -CH151 13 13 NA -CH159 13 13 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 13 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 14 16 16 -CH122 14 16 16 -//5G Band 4 -CH155 14 16 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 12 15 15 -//5G Band 2 -CH58 12 15 15 -//5G Band 3 -CH106 13 15 15 -CH122 13 15 15 -//5G Band 4 -CH155 13 15 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 11 14 14 -//5G Band 2 -CH58 11 14 14 -//5G Band 3 -CH106 12 14 14 -CH122 12 14 14 -//5G Band 4 -CH155 12 14 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 10 13 13 -//5G Band 2 -CH58 10 13 13 -//5G Band 3 -CH106 11 13 13 -CH122 11 13 13 -//5G Band 4 -CH155 11 13 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 22 16 16 +CH02 26 16 16 +CH03 26 16 16 +CH04 26 16 16 +CH05 26 16 16 +CH06 26 16 16 +CH07 26 16 16 +CH08 26 16 16 +CH09 26 16 16 +CH10 26 16 16 +CH11 22 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 19 16 16 +CH02 23 16 16 +CH03 23 16 16 +CH04 23 16 16 +CH05 23 16 16 +CH06 23 16 16 +CH07 23 16 16 +CH08 23 16 16 +CH09 23 16 16 +CH10 23 16 16 +CH11 19 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 23 16 16 +CH03 23 16 16 +CH04 23 16 16 +CH05 23 16 16 +CH06 23 16 16 +CH07 23 16 16 +CH08 23 16 16 +CH09 23 16 16 +CH10 23 16 16 +CH11 17 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 22 15 15 +CH03 22 15 15 +CH04 22 15 15 +CH05 22 15 15 +CH06 22 15 15 +CH07 22 15 15 +CH08 22 15 15 +CH09 22 15 15 +CH10 22 15 15 +CH11 16 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 21 14 14 +CH03 21 14 14 +CH04 21 14 14 +CH05 21 14 14 +CH06 21 14 14 +CH07 21 14 14 +CH08 21 14 14 +CH09 21 14 14 +CH10 21 14 14 +CH11 15 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 20 13 13 +CH03 20 13 13 +CH04 20 13 13 +CH05 20 13 13 +CH06 20 13 13 +CH07 20 13 13 +CH08 20 13 13 +CH09 20 13 13 +CH10 20 13 13 +CH11 14 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 16 16 +CH04 20 16 16 +CH05 20 16 16 +CH06 20 16 16 +CH07 20 16 16 +CH08 20 16 16 +CH09 20 16 16 +CH10 20 16 16 +CH11 17 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 15 15 +CH04 19 15 15 +CH05 19 15 15 +CH06 19 15 15 +CH07 19 15 15 +CH08 19 15 15 +CH09 19 15 15 +CH10 19 15 15 +CH11 16 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 14 14 +CH04 18 14 14 +CH05 18 14 14 +CH06 18 14 14 +CH07 18 14 14 +CH08 18 14 14 +CH09 18 14 14 +CH10 18 14 14 +CH11 15 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 13 13 +CH04 18 13 13 +CH05 18 13 13 +CH06 18 13 13 +CH07 18 13 13 +CH08 18 13 13 +CH09 18 13 13 +CH10 18 13 13 +CH11 15 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 19 16 16 +CH40 19 16 16 +CH44 19 16 16 +CH48 19 16 16 +//5G Band 2 +CH52 19 16 16 +CH56 19 16 16 +CH60 19 16 16 +CH64 19 16 16 +//5G Band 3 +CH100 18 16 16 +CH104 18 16 16 +CH108 18 16 16 +CH112 18 16 16 +CH116 18 16 16 +CH120 18 16 16 +CH124 18 16 16 +CH128 18 16 16 +CH132 18 16 16 +CH136 18 16 16 +CH140 18 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 16 16 +CH40 18 16 16 +CH44 18 16 16 +CH48 18 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 18 16 16 +CH60 18 16 16 +CH64 18 16 16 +//5G Band 3 +CH100 18 16 16 +CH104 18 16 16 +CH108 18 16 16 +CH112 18 16 16 +CH116 18 16 16 +CH120 18 16 16 +CH124 18 16 16 +CH128 18 16 16 +CH132 18 16 16 +CH136 18 16 16 +CH140 17 16 16 +//5G Band 4 +CH149 16 16 NA +CH153 19 16 NA +CH157 19 16 NA +CH161 19 16 NA +CH165 19 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 15 15 +CH40 17 15 15 +CH44 17 15 15 +CH48 17 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 17 15 15 +CH60 17 15 15 +CH64 17 15 15 +//5G Band 3 +CH100 17 15 15 +CH104 17 15 15 +CH108 17 15 15 +CH112 17 15 15 +CH116 17 15 15 +CH120 17 15 15 +CH124 17 15 15 +CH128 17 15 15 +CH132 17 15 15 +CH136 17 15 15 +CH140 16 15 15 +//5G Band 4 +CH149 15 15 NA +CH153 18 15 NA +CH157 18 15 NA +CH161 18 15 NA +CH165 18 15 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 16 14 14 +CH40 16 14 14 +CH44 16 14 14 +CH48 16 14 14 +//5G Band 2 +CH52 16 14 14 +CH56 16 14 14 +CH60 16 14 14 +CH64 16 14 14 +//5G Band 3 +CH100 16 14 14 +CH104 16 14 14 +CH108 16 14 14 +CH112 16 14 14 +CH116 16 14 14 +CH120 16 14 14 +CH124 16 14 14 +CH128 16 14 14 +CH132 16 14 14 +CH136 16 14 14 +CH140 15 14 14 +//5G Band 4 +CH149 14 14 NA +CH153 17 14 NA +CH157 17 14 NA +CH161 17 14 NA +CH165 17 14 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 13 13 +CH40 15 13 13 +CH44 15 13 13 +CH48 15 13 13 +//5G Band 2 +CH52 15 13 13 +CH56 15 13 13 +CH60 15 13 13 +CH64 15 13 13 +//5G Band 3 +CH100 15 13 13 +CH104 15 13 13 +CH108 15 13 13 +CH112 15 13 13 +CH116 15 13 13 +CH120 15 13 13 +CH124 15 13 13 +CH128 15 13 13 +CH132 15 13 13 +CH136 15 13 13 +CH140 14 13 13 +//5G Band 4 +CH149 13 13 NA +CH153 16 13 NA +CH157 16 13 NA +CH161 16 13 NA +CH165 16 13 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 16 16 +CH46 16 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 15 16 16 +CH110 19 16 16 +CH118 19 16 16 +CH126 19 16 16 +CH134 19 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 15 15 +CH46 15 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 14 15 15 +//5G Band 3 +CH102 14 15 15 +CH110 18 15 15 +CH118 18 15 15 +CH126 18 15 15 +CH134 18 15 15 +//5G Band 4 +CH151 15 15 NA +CH159 15 15 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 14 14 +CH46 14 14 14 +//5G Band 2 +CH54 14 14 14 +CH62 13 14 14 +//5G Band 3 +CH102 13 14 14 +CH110 17 14 14 +CH118 17 14 14 +CH126 17 14 14 +CH134 17 14 14 +//5G Band 4 +CH151 14 14 NA +CH159 14 14 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 13 13 13 +CH46 13 13 13 +//5G Band 2 +CH54 13 13 13 +CH62 12 13 13 +//5G Band 3 +CH102 12 13 13 +CH110 16 13 13 +CH118 16 13 13 +CH126 16 13 13 +CH134 16 13 13 +//5G Band 4 +CH151 13 13 NA +CH159 13 13 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 13 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 14 16 16 +CH122 14 16 16 +//5G Band 4 +CH155 14 16 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 12 15 15 +//5G Band 2 +CH58 12 15 15 +//5G Band 3 +CH106 13 15 15 +CH122 13 15 15 +//5G Band 4 +CH155 13 15 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 11 14 14 +//5G Band 2 +CH58 11 14 14 +//5G Band 3 +CH106 12 14 14 +CH122 12 14 14 +//5G Band 4 +CH155 12 14 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 10 13 13 +//5G Band 2 +CH58 10 13 13 +//5G Band 3 +CH106 11 13 13 +CH122 11 13 13 +//5G Band 4 +CH155 11 13 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type8.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type8.txt index d3511727d63..447172b023b 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type8.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TXPWR_LMT_8814Amp_Type8.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH104 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 18 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 18 18 18 -CH46 18 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 18 18 18 -//5G Band 3 -CH102 18 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 18 18 18 -//5G Band 2 -CH58 18 18 18 -//5G Band 3 -CH106 18 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH104 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 18 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 18 18 18 +CH46 18 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 18 18 18 +//5G Band 3 +CH102 18 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 18 18 18 +//5G Band 2 +CH58 18 18 18 +//5G Band 3 +CH106 18 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814A.txt old mode 100755 new mode 100644 index ab0f2fa250a..d7b1a823846 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814A.txt @@ -1,43 +1,43 @@ -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKA_P -[2G][A][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKA_N -[2G][B][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GCCKB_P -[2G][B][-][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,8,8,9,9,10,10,11,11,12,12,13,13,14,15,15,16} //2GCCKB_N -[2G][C][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKC_P -[2G][C][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKC_N -[2G][D][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14,15} //2GCCKD_P -[2G][D][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13} //2GCCKD_N -[2G][A][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,13,13} //2GA_P -[2G][A][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,10,10,10} //2GA_N -[2G][B][+][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GB_P -[2G][B][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10} //2GB_N -[2G][C][+][ALL] = {0,0,1,1,2,2,3,3,3,4,4,5,5,5,6,6,7,7,8,8,8,9,9,10,10,10,11,11,12,12} //2GC_P -[2G][C][-][ALL] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GC_N -[2G][D][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,12,13} //2GD_P -[2G][D][-][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,13,14} //2GD_N -[5G][A][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GLA_P -[5G][A][-][ALL][0] = {0,1,2,3,4,5,5,6,7,8,9,10,11,12,13,14,14,15,16,17,18,19,20,21,22,23,23,24,25,25} //5GLA_N -[5G][B][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19,20,21,22,23,24,25,25,25,25,25,25} //5GLB_P -[5G][B][-][ALL][0] = {0,1,2,2,3,4,5,6,7,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,20,20,21,22,23,24} //5GLB_N -[5G][C][+][ALL][0] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,21,23,24,25,25,25,25,25,25,25,25,25} //5GLC_P -[5G][C][-][ALL][0] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GLC_N -[5G][D][+][ALL][0] = {0,1,2,4,5,6,7,9,10,11,12,14,15,16,17,18,20,21,22,23,25,25,25,25,25,25,25,25,25,25} //5GLD_P -[5G][D][-][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25} //5GLD_N -[5G][A][+][ALL][1] = {0,1,2,3,4,5,6,7,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,23,24,25,25,25} //5GMA_P -[5G][A][-][ALL][1] = {0,1,1,2,3,4,4,5,6,6,7,8,9,9,10,11,11,12,13,14,14,15,16,16,17,18,19,19,20,21} //5GMA_N -[5G][B][+][ALL][1] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,21,22,23,24,25,25,25,25,25,25} //5GMB_P -[5G][B][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,10,10,11,12,13,14,15,16,16,17,18,19,20,21,22,22,23,24,25} //5GMB_N -[5G][C][+][ALL][1] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25} //5GMC_P -[5G][C][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,14,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GMC_N -[5G][D][+][ALL][1] = {0,1,2,4,5,6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25,25} //5GMD_P -[5G][D][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,9,10,11,12,13,14,15,15,16,17,18,19,20,21,21,22,23,24,25} //5GMD_N -[5G][A][+][ALL][2] = {0,1,2,3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25} //5GHA_P -[5G][A][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,18,19,20,21,22,23,24,25,25} //5GHA_N -[5G][B][+][ALL][2] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GHB_P -[5G][B][-][ALL][2] = {0,1,2,2,3,4,5,6,6,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,19,20,21,22,23,23} //5GHB_N -[5G][C][+][ALL][2] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25,25} //5GHC_P -[5G][C][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25} //5GHC_N -[5G][D][+][ALL][2] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,22,23,24,25,25,25,25,25,25,25,25,25} //5GHD_P -[5G][D][-][ALL][2] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,18,19,20,21,22,23,23,24} //5GHD_N +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKA_P +[2G][A][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKA_N +[2G][B][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GCCKB_P +[2G][B][-][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,8,8,9,9,10,10,11,11,12,12,13,13,14,15,15,16} //2GCCKB_N +[2G][C][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKC_P +[2G][C][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKC_N +[2G][D][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14,15} //2GCCKD_P +[2G][D][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13} //2GCCKD_N +[2G][A][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,13,13} //2GA_P +[2G][A][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,10,10,10} //2GA_N +[2G][B][+][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GB_P +[2G][B][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10} //2GB_N +[2G][C][+][ALL] = {0,0,1,1,2,2,3,3,3,4,4,5,5,5,6,6,7,7,8,8,8,9,9,10,10,10,11,11,12,12} //2GC_P +[2G][C][-][ALL] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GC_N +[2G][D][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,12,13} //2GD_P +[2G][D][-][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,13,14} //2GD_N +[5G][A][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GLA_P +[5G][A][-][ALL][0] = {0,1,2,3,4,5,5,6,7,8,9,10,11,12,13,14,14,15,16,17,18,19,20,21,22,23,23,24,25,25} //5GLA_N +[5G][B][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19,20,21,22,23,24,25,25,25,25,25,25} //5GLB_P +[5G][B][-][ALL][0] = {0,1,2,2,3,4,5,6,7,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,20,20,21,22,23,24} //5GLB_N +[5G][C][+][ALL][0] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,21,23,24,25,25,25,25,25,25,25,25,25} //5GLC_P +[5G][C][-][ALL][0] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GLC_N +[5G][D][+][ALL][0] = {0,1,2,4,5,6,7,9,10,11,12,14,15,16,17,18,20,21,22,23,25,25,25,25,25,25,25,25,25,25} //5GLD_P +[5G][D][-][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25} //5GLD_N +[5G][A][+][ALL][1] = {0,1,2,3,4,5,6,7,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,23,24,25,25,25} //5GMA_P +[5G][A][-][ALL][1] = {0,1,1,2,3,4,4,5,6,6,7,8,9,9,10,11,11,12,13,14,14,15,16,16,17,18,19,19,20,21} //5GMA_N +[5G][B][+][ALL][1] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,21,22,23,24,25,25,25,25,25,25} //5GMB_P +[5G][B][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,10,10,11,12,13,14,15,16,16,17,18,19,20,21,22,22,23,24,25} //5GMB_N +[5G][C][+][ALL][1] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25} //5GMC_P +[5G][C][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,14,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GMC_N +[5G][D][+][ALL][1] = {0,1,2,4,5,6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25,25} //5GMD_P +[5G][D][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,9,10,11,12,13,14,15,15,16,17,18,19,20,21,21,22,23,24,25} //5GMD_N +[5G][A][+][ALL][2] = {0,1,2,3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25} //5GHA_P +[5G][A][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,18,19,20,21,22,23,24,25,25} //5GHA_N +[5G][B][+][ALL][2] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GHB_P +[5G][B][-][ALL][2] = {0,1,2,2,3,4,5,6,6,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,19,20,21,22,23,23} //5GHB_N +[5G][C][+][ALL][2] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25,25} //5GHC_P +[5G][C][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25} //5GHC_N +[5G][D][+][ALL][2] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,22,23,24,25,25,25,25,25,25,25,25,25} //5GHD_P +[5G][D][-][ALL][2] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,18,19,20,21,22,23,23,24} //5GHD_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814Amp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814Amp.txt old mode 100755 new mode 100644 index a985f8f1ca2..95c8129f6c5 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814Amp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/TxPowerTrack_AP_8814Amp.txt @@ -1,80 +1,80 @@ -//RL6302_MAC_PHY_Parameter_v030_201408022 -//=======================================================================================================================================// -// THER DIFF [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// - - -[2G][A][+][CCK] = { 0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9,10,10,11,11,12,13,13,14,14,14,14,14,14,14,14,14} //2GCCKA_P -[2G][A][-][CCK] = { 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9,10,10,10,10,11,11,11} //2GCCKA_N - -[2G][B][+][CCK] = { 0, 0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9,10,10,11,11,12,12,13,13,14,14,14,14,14,14,14,14} //2GCCKB_P -[2G][B][-][CCK] = { 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9,10,11,12,13,13,13,13,13,13,13,13,13,13,13} //2GCCKB_N - -[2G][C][+][CCK] = { 0, 0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9,10,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12} //2GCCKC_P -[2G][C][-][CCK] = { 0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 7, 7, 8, 9,10,10,10,11,11,12,12,13,13,13,13,13,13,13} //2GCCKC_N - -[2G][D][+][CCK] = { 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9,10,11,12,13,13,13,14,14,14,14,14,14,14,14} //2GCCKD_P -[2G][D][-][CCK] = { 0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9,10} //2GCCKD_N - -[2G][A][+][ALL] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9,10,10,11,12,12,13,13,14,14,14,14,14,14,14,14,14,14} //2GA_P -[2G][A][-][ALL] = { 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9,10,10,10,10,10,10,10} //2GA_N - -[2G][B][+][ALL] = { 0, 0, 1, 3, 3, 3, 4, 4, 5, 5, 6, 7, 8, 9,10,10,11,12,13,14,14,14,14,14,14,14,14,14,14,14} //2GB_P -[2G][B][-][ALL] = { 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 6, 7, 8, 9,10,10,11,11,11,12,13,14,14,14,14,14,14,14,14} //2GB_N - -[2G][C][+][ALL] = { 0, 1, 1, 2, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9,10,10,11,12,13,13,13,13,13,13,13,13,13,13,13} //2GC_P -[2G][C][-][ALL] = { 0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,10,11,11,11,11,12,12,12,13,13,13,14,14,14,14} //2GC_N - - -[2G][D][+][ALL] = { 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9,10,10,11,12,13,13,14,14,14,14,14,14,14,14,14,14} //2GD_P -[2G][D][-][ALL] = { 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9,10,10,10,10,10} //2GD_N - - -[5G][A][+][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GLA_P -[5G][A][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9,10,11,12,13,14,15,15,15,15,15,15,16,16,16,16,16,16} //5GLA_N - - -[5G][B][+][ALL][0] = { 0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GLB_P -[5G][B][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9,10,11,12,13,14,14,15,15,16,16,16,16,16,16,16,16,16} //5GLB_N - - -[5G][C][+][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GLC_P -[5G][C][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9,10,11,12,12,13,13,14,14,15,15,16,16,16,16,16,16,16,16} //5GLC_N - - -[5G][D][+][ALL][0] = { 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22} //5GLD_P -[5G][D][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9,11,11,12,13,13,14,14,15,15,15,15,16,16,16,16,16,16,16,16} //5GLD_N - - -[5G][A][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22,22} //5GMA_P -[5G][A][-][ALL][1] = { 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 6, 6, 6, 7, 8, 8, 9,10,11,12,13,14,15,16,16,16,16,16,16,16} //5GMA_N - - -[5G][B][+][ALL][1] = { 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GMB_P -[5G][B][-][ALL][1] = { 0, 1, 1, 2, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9,10,11,12,13,14,14,15,15,15,15,15,15,15,15,15} //5GMB_N - - -[5G][C][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GMC_P -[5G][C][-][ALL][1] = { 0, 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9,10,10,11,11,12,12,12,13,13,14,14,14,14,14,14,14,14} //5GMC_N - - -[5G][D][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,16,18,19,20,21,21,22,22,22,22,22,22,22,22,22} //5GMD_P -[5G][D][-][ALL][1] = { 0, 1, 1, 2, 3, 4, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9,10,10,11,12,13,14,15,16,16,16,16,16,16,16} //5GMD_N ----------------------- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 - -[5G][A][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,11,12,13,14,15,16,16,16,16,16,16,16,16,16,16,16,16,16} //5GHA_P -[5G][A][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22,22} //5GHA_N - - -[5G][B][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9,10,10,11,11,12,12,13,13,13,14,14,14,14,14,14,14,14} //5GHB_P -[5G][B][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,20,20,20,20,20,20,20,20,20} //5GHB_N - - -[5G][C][-][ALL][2] = { 0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9,10,11,12,12,13,14,15,15,16,17,17,17,17,17,17,17,17,17} //5GHC_P -[5G][C][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GHC_N - -[5G][D][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,20,20,20,20,20,20,20,20,20} //5GHD_P -[5G][D][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,16,18,19,20,21,22,22,22,22,22,22,22,22,22,22} //5GHD_N - - +//RL6302_MAC_PHY_Parameter_v030_201408022 +//=======================================================================================================================================// +// THER DIFF [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// + + +[2G][A][+][CCK] = { 0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9,10,10,11,11,12,13,13,14,14,14,14,14,14,14,14,14} //2GCCKA_P +[2G][A][-][CCK] = { 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9,10,10,10,10,11,11,11} //2GCCKA_N + +[2G][B][+][CCK] = { 0, 0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9,10,10,11,11,12,12,13,13,14,14,14,14,14,14,14,14} //2GCCKB_P +[2G][B][-][CCK] = { 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9,10,11,12,13,13,13,13,13,13,13,13,13,13,13} //2GCCKB_N + +[2G][C][+][CCK] = { 0, 0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9,10,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12} //2GCCKC_P +[2G][C][-][CCK] = { 0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 7, 7, 8, 9,10,10,10,11,11,12,12,13,13,13,13,13,13,13} //2GCCKC_N + +[2G][D][+][CCK] = { 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9,10,11,12,13,13,13,14,14,14,14,14,14,14,14} //2GCCKD_P +[2G][D][-][CCK] = { 0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9,10} //2GCCKD_N + +[2G][A][+][ALL] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9,10,10,11,12,12,13,13,14,14,14,14,14,14,14,14,14,14} //2GA_P +[2G][A][-][ALL] = { 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9,10,10,10,10,10,10,10} //2GA_N + +[2G][B][+][ALL] = { 0, 0, 1, 3, 3, 3, 4, 4, 5, 5, 6, 7, 8, 9,10,10,11,12,13,14,14,14,14,14,14,14,14,14,14,14} //2GB_P +[2G][B][-][ALL] = { 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 6, 7, 8, 9,10,10,11,11,11,12,13,14,14,14,14,14,14,14,14} //2GB_N + +[2G][C][+][ALL] = { 0, 1, 1, 2, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9,10,10,11,12,13,13,13,13,13,13,13,13,13,13,13} //2GC_P +[2G][C][-][ALL] = { 0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,10,11,11,11,11,12,12,12,13,13,13,14,14,14,14} //2GC_N + + +[2G][D][+][ALL] = { 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9,10,10,11,12,13,13,14,14,14,14,14,14,14,14,14,14} //2GD_P +[2G][D][-][ALL] = { 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9,10,10,10,10,10} //2GD_N + + +[5G][A][+][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GLA_P +[5G][A][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9,10,11,12,13,14,15,15,15,15,15,15,16,16,16,16,16,16} //5GLA_N + + +[5G][B][+][ALL][0] = { 0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GLB_P +[5G][B][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9,10,11,12,13,14,14,15,15,16,16,16,16,16,16,16,16,16} //5GLB_N + + +[5G][C][+][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GLC_P +[5G][C][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9,10,11,12,12,13,13,14,14,15,15,16,16,16,16,16,16,16,16} //5GLC_N + + +[5G][D][+][ALL][0] = { 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22} //5GLD_P +[5G][D][-][ALL][0] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9,11,11,12,13,13,14,14,15,15,15,15,16,16,16,16,16,16,16,16} //5GLD_N + + +[5G][A][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22,22} //5GMA_P +[5G][A][-][ALL][1] = { 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 6, 6, 6, 7, 8, 8, 9,10,11,12,13,14,15,16,16,16,16,16,16,16} //5GMA_N + + +[5G][B][+][ALL][1] = { 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21} //5GMB_P +[5G][B][-][ALL][1] = { 0, 1, 1, 2, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9,10,11,12,13,14,14,15,15,15,15,15,15,15,15,15} //5GMB_N + + +[5G][C][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GMC_P +[5G][C][-][ALL][1] = { 0, 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9,10,10,11,11,12,12,12,13,13,14,14,14,14,14,14,14,14} //5GMC_N + + +[5G][D][+][ALL][1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,16,18,19,20,21,21,22,22,22,22,22,22,22,22,22} //5GMD_P +[5G][D][-][ALL][1] = { 0, 1, 1, 2, 3, 4, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9,10,10,11,12,13,14,15,16,16,16,16,16,16,16} //5GMD_N +---------------------- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 + +[5G][A][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,11,12,13,14,15,16,16,16,16,16,16,16,16,16,16,16,16,16} //5GHA_P +[5G][A][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,22,22,22,22,22,22} //5GHA_N + + +[5G][B][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9,10,10,11,11,12,12,13,13,13,14,14,14,14,14,14,14,14} //5GHB_P +[5G][B][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,20,20,20,20,20,20,20,20,20} //5GHB_N + + +[5G][C][-][ALL][2] = { 0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9,10,11,12,12,13,14,15,15,16,17,17,17,17,17,17,17,17,17} //5GHC_P +[5G][C][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,21,21,21,21,21,21,21,21} //5GHC_N + +[5G][D][-][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,20,20,20,20,20,20,20,20,20} //5GHD_P +[5G][D][+][ALL][2] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,16,18,19,20,21,22,22,22,22,22,22,22,22,22,22} //5GHD_N + + \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/Version.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/Version.txt old mode 100755 new mode 100644 index 237a40b78c7..79468d5fe33 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/Version.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/Version.txt @@ -1 +1 @@ -CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 +CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/rtl8814Afw.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/rtl8814Afw.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8814A/rtl8814AfwMP.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8814A/rtl8814AfwMP.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B.txt old mode 100755 new mode 100644 index 795f9cb7e18..6572fbd747d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xfe020001 // Pin=-108dBm -0x81c 0xfd040001 // Pin=-106dBm -0x81c 0xfc060001 // Pin=-104dBm -0x81c 0xfb080001 // Pin=-102dBm -0x81c 0xfa0a0001 // Pin=-100dBm -0x81c 0xf90c0001 // Pin=-98dBm -0x81c 0xf80e0001 // Pin=-96dBm -0x81c 0xf7100001 // Pin=-94dBm -0x81c 0xf6120001 // Pin=-92dBm -0x81c 0xf5140001 // Pin=-90dBm -0x81c 0xf4160001 // Pin=-88dBm -0x81c 0xf3180001 // Pin=-86dBm -0x81c 0xf21a0001 // Pin=-84dBm -0x81c 0xf11c0001 // Pin=-82dBm -0x81c 0xef1e0001 // Pin=-80dBm -0x81c 0xee200001 // Pin=-78dBm -0x81c 0xed220001 // Pin=-76dBm -0x81c 0xec240001 // Pin=-74dBm -0x81c 0xeb260001 // Pin=-72dBm -0x81c 0xea280001 // Pin=-70dBm -0x81c 0xe92a0001 // Pin=-68dBm -0x81c 0xe82c0001 // Pin=-66dBm -0x81c 0xe72e0001 // Pin=-64dBm -0x81c 0xe6300001 // Pin=-62dBm -0x81c 0xe5320001 // Pin=-60dBm -0x81c 0xe4340001 // Pin=-58dBm -0x81c 0xc7360001 // Pin=-56dBm -0x81c 0xc6380001 // Pin=-54dBm -0x81c 0xc53a0001 // Pin=-52dBm -0x81c 0xc43c0001 // Pin=-50dBm -0x81c 0xc33e0001 // Pin=-48dBm -0x81c 0xa5400001 // Pin=-46dBm -0x81c 0xa4420001 // Pin=-44dBm -0x81c 0xa3440001 // Pin=-42dBm -0x81c 0xa2460001 // Pin=-40dBm -0x81c 0x88480001 // Pin=-38dBm -0x81c 0x874a0001 // Pin=-36dBm -0x81c 0x694c0001 // Pin=-34dBm -0x81c 0x684e0001 // Pin=-32dBm -0x81c 0x67500001 // Pin=-30dBm -0x81c 0x66520001 // Pin=-28dBm -0x81c 0x65540001 // Pin=-26dBm -0x81c 0x64560001 // Pin=-24dBm -0x81c 0x63580001 // Pin=-22dBm -0x81c 0x625a0001 // Pin=-20dBm -0x81c 0x455c0001 // Pin=-18dBm -0x81c 0x445e0001 // Pin=-16dBm -0x81c 0x43600001 // Pin=-14dBm -0x81c 0x42620001 // Pin=-12dBm -0x81c 0x28640001 // Pin=-10dBm -0x81c 0x27660001 // Pin=-08dBm -0x81c 0x26680001 // Pin=-06dBm -0x81c 0x256a0001 // Pin=-04dBm -0x81c 0x246c0001 // Pin=-02dBm -0x81c 0x236e0001 // Pin=-00dBm -0x81c 0x22700001 // Pin=+02dBm -0x81c 0x21720001 // Pin=+04dBm -0x81c 0x21740001 // Pin=+06dBm -0x81c 0x21760001 // Pin=+08dBm -0x81c 0x21780001 // Pin=+10dBm -0x81c 0x217a0001 // Pin=+12dBm -0x81c 0x217c0001 // Pin=+14dBm -0x81c 0x217e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xff040101 // Pin=-106dBm -0x81c 0xfe060101 // Pin=-104dBm -0x81c 0xfd080101 // Pin=-102dBm -0x81c 0xfc0a0101 // Pin=-100dBm -0x81c 0xfb0c0101 // Pin=-98dBm -0x81c 0xfa0e0101 // Pin=-96dBm -0x81c 0xf9100101 // Pin=-94dBm -0x81c 0xf8120101 // Pin=-92dBm -0x81c 0xf7140101 // Pin=-90dBm -0x81c 0xf6160101 // Pin=-88dBm -0x81c 0xf5180101 // Pin=-86dBm -0x81c 0xf41a0101 // Pin=-84dBm -0x81c 0xf31c0101 // Pin=-82dBm -0x81c 0xf21e0101 // Pin=-80dBm -0x81c 0xf1200101 // Pin=-78dBm -0x81c 0xf0220101 // Pin=-76dBm -0x81c 0xef240101 // Pin=-74dBm -0x81c 0xee260101 // Pin=-72dBm -0x81c 0xed280101 // Pin=-70dBm -0x81c 0xec2a0101 // Pin=-68dBm -0x81c 0xeb2c0101 // Pin=-66dBm -0x81c 0xea2e0101 // Pin=-64dBm -0x81c 0xe9300101 // Pin=-62dBm -0x81c 0xe8320101 // Pin=-60dBm -0x81c 0xe7340101 // Pin=-58dBm -0x81c 0xe6360101 // Pin=-56dBm -0x81c 0xca380101 // Pin=-54dBm -0x81c 0xc93a0101 // Pin=-52dBm -0x81c 0xc83c0101 // Pin=-50dBm -0x81c 0xc73e0101 // Pin=-48dBm -0x81c 0xc6400101 // Pin=-46dBm -0x81c 0xc5420101 // Pin=-44dBm -0x81c 0xc4440101 // Pin=-42dBm -0x81c 0xc3460101 // Pin=-40dBm -0x81c 0xc2480101 // Pin=-38dBm -0x81c 0xa44a0101 // Pin=-36dBm -0x81c 0xa34c0101 // Pin=-34dBm -0x81c 0xa24e0101 // Pin=-32dBm -0x81c 0x84500101 // Pin=-30dBm -0x81c 0x83520101 // Pin=-28dBm -0x81c 0x82540101 // Pin=-26dBm -0x81c 0x65560101 // Pin=-24dBm -0x81c 0x64580101 // Pin=-22dBm -0x81c 0x635a0101 // Pin=-20dBm -0x81c 0x445c0101 // Pin=-18dBm -0x81c 0x435e0101 // Pin=-16dBm -0x81c 0x42600101 // Pin=-14dBm -0x81c 0x24620101 // Pin=-12dBm -0x81c 0x23640101 // Pin=-10dBm -0x81c 0x22660101 // Pin=-08dBm -0x81c 0x04680101 // Pin=-06dBm -0x81c 0x036a0101 // Pin=-04dBm -0x81c 0x026c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x02700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xfe020001 // Pin=-108dBm +0x81c 0xfd040001 // Pin=-106dBm +0x81c 0xfc060001 // Pin=-104dBm +0x81c 0xfb080001 // Pin=-102dBm +0x81c 0xfa0a0001 // Pin=-100dBm +0x81c 0xf90c0001 // Pin=-98dBm +0x81c 0xf80e0001 // Pin=-96dBm +0x81c 0xf7100001 // Pin=-94dBm +0x81c 0xf6120001 // Pin=-92dBm +0x81c 0xf5140001 // Pin=-90dBm +0x81c 0xf4160001 // Pin=-88dBm +0x81c 0xf3180001 // Pin=-86dBm +0x81c 0xf21a0001 // Pin=-84dBm +0x81c 0xf11c0001 // Pin=-82dBm +0x81c 0xef1e0001 // Pin=-80dBm +0x81c 0xee200001 // Pin=-78dBm +0x81c 0xed220001 // Pin=-76dBm +0x81c 0xec240001 // Pin=-74dBm +0x81c 0xeb260001 // Pin=-72dBm +0x81c 0xea280001 // Pin=-70dBm +0x81c 0xe92a0001 // Pin=-68dBm +0x81c 0xe82c0001 // Pin=-66dBm +0x81c 0xe72e0001 // Pin=-64dBm +0x81c 0xe6300001 // Pin=-62dBm +0x81c 0xe5320001 // Pin=-60dBm +0x81c 0xe4340001 // Pin=-58dBm +0x81c 0xc7360001 // Pin=-56dBm +0x81c 0xc6380001 // Pin=-54dBm +0x81c 0xc53a0001 // Pin=-52dBm +0x81c 0xc43c0001 // Pin=-50dBm +0x81c 0xc33e0001 // Pin=-48dBm +0x81c 0xa5400001 // Pin=-46dBm +0x81c 0xa4420001 // Pin=-44dBm +0x81c 0xa3440001 // Pin=-42dBm +0x81c 0xa2460001 // Pin=-40dBm +0x81c 0x88480001 // Pin=-38dBm +0x81c 0x874a0001 // Pin=-36dBm +0x81c 0x694c0001 // Pin=-34dBm +0x81c 0x684e0001 // Pin=-32dBm +0x81c 0x67500001 // Pin=-30dBm +0x81c 0x66520001 // Pin=-28dBm +0x81c 0x65540001 // Pin=-26dBm +0x81c 0x64560001 // Pin=-24dBm +0x81c 0x63580001 // Pin=-22dBm +0x81c 0x625a0001 // Pin=-20dBm +0x81c 0x455c0001 // Pin=-18dBm +0x81c 0x445e0001 // Pin=-16dBm +0x81c 0x43600001 // Pin=-14dBm +0x81c 0x42620001 // Pin=-12dBm +0x81c 0x28640001 // Pin=-10dBm +0x81c 0x27660001 // Pin=-08dBm +0x81c 0x26680001 // Pin=-06dBm +0x81c 0x256a0001 // Pin=-04dBm +0x81c 0x246c0001 // Pin=-02dBm +0x81c 0x236e0001 // Pin=-00dBm +0x81c 0x22700001 // Pin=+02dBm +0x81c 0x21720001 // Pin=+04dBm +0x81c 0x21740001 // Pin=+06dBm +0x81c 0x21760001 // Pin=+08dBm +0x81c 0x21780001 // Pin=+10dBm +0x81c 0x217a0001 // Pin=+12dBm +0x81c 0x217c0001 // Pin=+14dBm +0x81c 0x217e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xff040101 // Pin=-106dBm +0x81c 0xfe060101 // Pin=-104dBm +0x81c 0xfd080101 // Pin=-102dBm +0x81c 0xfc0a0101 // Pin=-100dBm +0x81c 0xfb0c0101 // Pin=-98dBm +0x81c 0xfa0e0101 // Pin=-96dBm +0x81c 0xf9100101 // Pin=-94dBm +0x81c 0xf8120101 // Pin=-92dBm +0x81c 0xf7140101 // Pin=-90dBm +0x81c 0xf6160101 // Pin=-88dBm +0x81c 0xf5180101 // Pin=-86dBm +0x81c 0xf41a0101 // Pin=-84dBm +0x81c 0xf31c0101 // Pin=-82dBm +0x81c 0xf21e0101 // Pin=-80dBm +0x81c 0xf1200101 // Pin=-78dBm +0x81c 0xf0220101 // Pin=-76dBm +0x81c 0xef240101 // Pin=-74dBm +0x81c 0xee260101 // Pin=-72dBm +0x81c 0xed280101 // Pin=-70dBm +0x81c 0xec2a0101 // Pin=-68dBm +0x81c 0xeb2c0101 // Pin=-66dBm +0x81c 0xea2e0101 // Pin=-64dBm +0x81c 0xe9300101 // Pin=-62dBm +0x81c 0xe8320101 // Pin=-60dBm +0x81c 0xe7340101 // Pin=-58dBm +0x81c 0xe6360101 // Pin=-56dBm +0x81c 0xca380101 // Pin=-54dBm +0x81c 0xc93a0101 // Pin=-52dBm +0x81c 0xc83c0101 // Pin=-50dBm +0x81c 0xc73e0101 // Pin=-48dBm +0x81c 0xc6400101 // Pin=-46dBm +0x81c 0xc5420101 // Pin=-44dBm +0x81c 0xc4440101 // Pin=-42dBm +0x81c 0xc3460101 // Pin=-40dBm +0x81c 0xc2480101 // Pin=-38dBm +0x81c 0xa44a0101 // Pin=-36dBm +0x81c 0xa34c0101 // Pin=-34dBm +0x81c 0xa24e0101 // Pin=-32dBm +0x81c 0x84500101 // Pin=-30dBm +0x81c 0x83520101 // Pin=-28dBm +0x81c 0x82540101 // Pin=-26dBm +0x81c 0x65560101 // Pin=-24dBm +0x81c 0x64580101 // Pin=-22dBm +0x81c 0x635a0101 // Pin=-20dBm +0x81c 0x445c0101 // Pin=-18dBm +0x81c 0x435e0101 // Pin=-16dBm +0x81c 0x42600101 // Pin=-14dBm +0x81c 0x24620101 // Pin=-12dBm +0x81c 0x23640101 // Pin=-10dBm +0x81c 0x22660101 // Pin=-08dBm +0x81c 0x04680101 // Pin=-06dBm +0x81c 0x036a0101 // Pin=-04dBm +0x81c 0x026c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x02700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B_hp.txt old mode 100755 new mode 100644 index 64279ed3efd..90a6b469083 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822B_hp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xfe060001 // Pin=-104dBm -0x81c 0xfd080001 // Pin=-102dBm -0x81c 0xfc0a0001 // Pin=-100dBm -0x81c 0xfb0c0001 // Pin=-98dBm -0x81c 0xfa0e0001 // Pin=-96dBm -0x81c 0xf9100001 // Pin=-94dBm -0x81c 0xf8120001 // Pin=-92dBm -0x81c 0xf7140001 // Pin=-90dBm -0x81c 0xf6160001 // Pin=-88dBm -0x81c 0xf5180001 // Pin=-86dBm -0x81c 0xf41a0001 // Pin=-84dBm -0x81c 0xf31c0001 // Pin=-82dBm -0x81c 0xf21e0001 // Pin=-80dBm -0x81c 0xf1200001 // Pin=-78dBm -0x81c 0xef220001 // Pin=-76dBm -0x81c 0xee240001 // Pin=-74dBm -0x81c 0xed260001 // Pin=-72dBm -0x81c 0xec280001 // Pin=-70dBm -0x81c 0xeb2a0001 // Pin=-68dBm -0x81c 0xea2c0001 // Pin=-66dBm -0x81c 0xe92e0001 // Pin=-64dBm -0x81c 0xe8300001 // Pin=-62dBm -0x81c 0xe7320001 // Pin=-60dBm -0x81c 0xe6340001 // Pin=-58dBm -0x81c 0xc8360001 // Pin=-56dBm -0x81c 0xc7380001 // Pin=-54dBm -0x81c 0xc63a0001 // Pin=-52dBm -0x81c 0xc53c0001 // Pin=-50dBm -0x81c 0xc43e0001 // Pin=-48dBm -0x81c 0xc3400001 // Pin=-46dBm -0x81c 0xc2420001 // Pin=-44dBm -0x81c 0xc1440001 // Pin=-42dBm -0x81c 0xa8460001 // Pin=-40dBm -0x81c 0xa7480001 // Pin=-38dBm -0x81c 0xa64a0001 // Pin=-36dBm -0x81c 0x6a4c0001 // Pin=-34dBm -0x81c 0x694e0001 // Pin=-32dBm -0x81c 0x68500001 // Pin=-30dBm -0x81c 0x67520001 // Pin=-28dBm -0x81c 0x66540001 // Pin=-26dBm -0x81c 0x65560001 // Pin=-24dBm -0x81c 0x64580001 // Pin=-22dBm -0x81c 0x635a0001 // Pin=-20dBm -0x81c 0x475c0001 // Pin=-18dBm -0x81c 0x465e0001 // Pin=-16dBm -0x81c 0x45600001 // Pin=-14dBm -0x81c 0x44620001 // Pin=-12dBm -0x81c 0x43640001 // Pin=-10dBm -0x81c 0x42660001 // Pin=-08dBm -0x81c 0x41680001 // Pin=-06dBm -0x81c 0x416a0001 // Pin=-04dBm -0x81c 0x416c0001 // Pin=-02dBm -0x81c 0x416e0001 // Pin=-00dBm -0x81c 0x41700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfa000101 // Pin=-110dBm -0x81c 0xf9020101 // Pin=-108dBm -0x81c 0xf8040101 // Pin=-106dBm -0x81c 0xf7060101 // Pin=-104dBm -0x81c 0xf6080101 // Pin=-102dBm -0x81c 0xf50a0101 // Pin=-100dBm -0x81c 0xf40c0101 // Pin=-98dBm -0x81c 0xf30e0101 // Pin=-96dBm -0x81c 0xf2100101 // Pin=-94dBm -0x81c 0xf1120101 // Pin=-92dBm -0x81c 0xf0140101 // Pin=-90dBm -0x81c 0xef160101 // Pin=-88dBm -0x81c 0xee180101 // Pin=-86dBm -0x81c 0xed1a0101 // Pin=-84dBm -0x81c 0xec1c0101 // Pin=-82dBm -0x81c 0xeb1e0101 // Pin=-80dBm -0x81c 0xea200101 // Pin=-78dBm -0x81c 0xe9220101 // Pin=-76dBm -0x81c 0xe8240101 // Pin=-74dBm -0x81c 0xe7260101 // Pin=-72dBm -0x81c 0xe6280101 // Pin=-70dBm -0x81c 0xca2a0101 // Pin=-68dBm -0x81c 0xc92c0101 // Pin=-66dBm -0x81c 0xc82e0101 // Pin=-64dBm -0x81c 0xc7300101 // Pin=-62dBm -0x81c 0xc6320101 // Pin=-60dBm -0x81c 0xc5340101 // Pin=-58dBm -0x81c 0xc4360101 // Pin=-56dBm -0x81c 0xc3380101 // Pin=-54dBm -0x81c 0xc23a0101 // Pin=-52dBm -0x81c 0xa53c0101 // Pin=-50dBm -0x81c 0xa43e0101 // Pin=-48dBm -0x81c 0xa3400101 // Pin=-46dBm -0x81c 0xa2420101 // Pin=-44dBm -0x81c 0x84440101 // Pin=-42dBm -0x81c 0x83460101 // Pin=-40dBm -0x81c 0x82480101 // Pin=-38dBm -0x81c 0x474a0101 // Pin=-36dBm -0x81c 0x464c0101 // Pin=-34dBm -0x81c 0x454e0101 // Pin=-32dBm -0x81c 0x44500101 // Pin=-30dBm -0x81c 0x43520101 // Pin=-28dBm -0x81c 0x25540101 // Pin=-26dBm -0x81c 0x24560101 // Pin=-24dBm -0x81c 0x23580101 // Pin=-22dBm -0x81c 0x225a0101 // Pin=-20dBm -0x81c 0x045c0101 // Pin=-18dBm -0x81c 0x035e0101 // Pin=-16dBm -0x81c 0x02600101 // Pin=-14dBm -0x81c 0x01620101 // Pin=-12dBm -0x81c 0x01640101 // Pin=-10dBm -0x81c 0x01660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xfe060001 // Pin=-104dBm +0x81c 0xfd080001 // Pin=-102dBm +0x81c 0xfc0a0001 // Pin=-100dBm +0x81c 0xfb0c0001 // Pin=-98dBm +0x81c 0xfa0e0001 // Pin=-96dBm +0x81c 0xf9100001 // Pin=-94dBm +0x81c 0xf8120001 // Pin=-92dBm +0x81c 0xf7140001 // Pin=-90dBm +0x81c 0xf6160001 // Pin=-88dBm +0x81c 0xf5180001 // Pin=-86dBm +0x81c 0xf41a0001 // Pin=-84dBm +0x81c 0xf31c0001 // Pin=-82dBm +0x81c 0xf21e0001 // Pin=-80dBm +0x81c 0xf1200001 // Pin=-78dBm +0x81c 0xef220001 // Pin=-76dBm +0x81c 0xee240001 // Pin=-74dBm +0x81c 0xed260001 // Pin=-72dBm +0x81c 0xec280001 // Pin=-70dBm +0x81c 0xeb2a0001 // Pin=-68dBm +0x81c 0xea2c0001 // Pin=-66dBm +0x81c 0xe92e0001 // Pin=-64dBm +0x81c 0xe8300001 // Pin=-62dBm +0x81c 0xe7320001 // Pin=-60dBm +0x81c 0xe6340001 // Pin=-58dBm +0x81c 0xc8360001 // Pin=-56dBm +0x81c 0xc7380001 // Pin=-54dBm +0x81c 0xc63a0001 // Pin=-52dBm +0x81c 0xc53c0001 // Pin=-50dBm +0x81c 0xc43e0001 // Pin=-48dBm +0x81c 0xc3400001 // Pin=-46dBm +0x81c 0xc2420001 // Pin=-44dBm +0x81c 0xc1440001 // Pin=-42dBm +0x81c 0xa8460001 // Pin=-40dBm +0x81c 0xa7480001 // Pin=-38dBm +0x81c 0xa64a0001 // Pin=-36dBm +0x81c 0x6a4c0001 // Pin=-34dBm +0x81c 0x694e0001 // Pin=-32dBm +0x81c 0x68500001 // Pin=-30dBm +0x81c 0x67520001 // Pin=-28dBm +0x81c 0x66540001 // Pin=-26dBm +0x81c 0x65560001 // Pin=-24dBm +0x81c 0x64580001 // Pin=-22dBm +0x81c 0x635a0001 // Pin=-20dBm +0x81c 0x475c0001 // Pin=-18dBm +0x81c 0x465e0001 // Pin=-16dBm +0x81c 0x45600001 // Pin=-14dBm +0x81c 0x44620001 // Pin=-12dBm +0x81c 0x43640001 // Pin=-10dBm +0x81c 0x42660001 // Pin=-08dBm +0x81c 0x41680001 // Pin=-06dBm +0x81c 0x416a0001 // Pin=-04dBm +0x81c 0x416c0001 // Pin=-02dBm +0x81c 0x416e0001 // Pin=-00dBm +0x81c 0x41700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfa000101 // Pin=-110dBm +0x81c 0xf9020101 // Pin=-108dBm +0x81c 0xf8040101 // Pin=-106dBm +0x81c 0xf7060101 // Pin=-104dBm +0x81c 0xf6080101 // Pin=-102dBm +0x81c 0xf50a0101 // Pin=-100dBm +0x81c 0xf40c0101 // Pin=-98dBm +0x81c 0xf30e0101 // Pin=-96dBm +0x81c 0xf2100101 // Pin=-94dBm +0x81c 0xf1120101 // Pin=-92dBm +0x81c 0xf0140101 // Pin=-90dBm +0x81c 0xef160101 // Pin=-88dBm +0x81c 0xee180101 // Pin=-86dBm +0x81c 0xed1a0101 // Pin=-84dBm +0x81c 0xec1c0101 // Pin=-82dBm +0x81c 0xeb1e0101 // Pin=-80dBm +0x81c 0xea200101 // Pin=-78dBm +0x81c 0xe9220101 // Pin=-76dBm +0x81c 0xe8240101 // Pin=-74dBm +0x81c 0xe7260101 // Pin=-72dBm +0x81c 0xe6280101 // Pin=-70dBm +0x81c 0xca2a0101 // Pin=-68dBm +0x81c 0xc92c0101 // Pin=-66dBm +0x81c 0xc82e0101 // Pin=-64dBm +0x81c 0xc7300101 // Pin=-62dBm +0x81c 0xc6320101 // Pin=-60dBm +0x81c 0xc5340101 // Pin=-58dBm +0x81c 0xc4360101 // Pin=-56dBm +0x81c 0xc3380101 // Pin=-54dBm +0x81c 0xc23a0101 // Pin=-52dBm +0x81c 0xa53c0101 // Pin=-50dBm +0x81c 0xa43e0101 // Pin=-48dBm +0x81c 0xa3400101 // Pin=-46dBm +0x81c 0xa2420101 // Pin=-44dBm +0x81c 0x84440101 // Pin=-42dBm +0x81c 0x83460101 // Pin=-40dBm +0x81c 0x82480101 // Pin=-38dBm +0x81c 0x474a0101 // Pin=-36dBm +0x81c 0x464c0101 // Pin=-34dBm +0x81c 0x454e0101 // Pin=-32dBm +0x81c 0x44500101 // Pin=-30dBm +0x81c 0x43520101 // Pin=-28dBm +0x81c 0x25540101 // Pin=-26dBm +0x81c 0x24560101 // Pin=-24dBm +0x81c 0x23580101 // Pin=-22dBm +0x81c 0x225a0101 // Pin=-20dBm +0x81c 0x045c0101 // Pin=-18dBm +0x81c 0x035e0101 // Pin=-16dBm +0x81c 0x02600101 // Pin=-14dBm +0x81c 0x01620101 // Pin=-12dBm +0x81c 0x01640101 // Pin=-10dBm +0x81c 0x01660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp.txt old mode 100755 new mode 100644 index 1f5ce9de5aa..3a807186130 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp.txt @@ -1,139 +1,139 @@ -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xfe020001 // Pin=-108dBm -0x81c 0xfd040001 // Pin=-106dBm -0x81c 0xfc060001 // Pin=-104dBm -0x81c 0xfb080001 // Pin=-102dBm -0x81c 0xfa0a0001 // Pin=-100dBm -0x81c 0xf90c0001 // Pin=-98dBm -0x81c 0xf80e0001 // Pin=-96dBm -0x81c 0xf7100001 // Pin=-94dBm -0x81c 0xf6120001 // Pin=-92dBm -0x81c 0xf5140001 // Pin=-90dBm -0x81c 0xf4160001 // Pin=-88dBm -0x81c 0xf3180001 // Pin=-86dBm -0x81c 0xf21a0001 // Pin=-84dBm -0x81c 0xf11c0001 // Pin=-82dBm -0x81c 0xef1e0001 // Pin=-80dBm -0x81c 0xee200001 // Pin=-78dBm -0x81c 0xed220001 // Pin=-76dBm -0x81c 0xec240001 // Pin=-74dBm -0x81c 0xeb260001 // Pin=-72dBm -0x81c 0xea280001 // Pin=-70dBm -0x81c 0xe92a0001 // Pin=-68dBm -0x81c 0xe82c0001 // Pin=-66dBm -0x81c 0xe72e0001 // Pin=-64dBm -0x81c 0xe6300001 // Pin=-62dBm -0x81c 0xe5320001 // Pin=-60dBm -0x81c 0xe4340001 // Pin=-58dBm -0x81c 0xc7360001 // Pin=-56dBm -0x81c 0xc6380001 // Pin=-54dBm -0x81c 0xc53a0001 // Pin=-52dBm -0x81c 0xc43c0001 // Pin=-50dBm -0x81c 0xc33e0001 // Pin=-48dBm -0x81c 0xa5400001 // Pin=-46dBm -0x81c 0xa4420001 // Pin=-44dBm -0x81c 0xa3440001 // Pin=-42dBm -0x81c 0xa2460001 // Pin=-40dBm -0x81c 0x88480001 // Pin=-38dBm -0x81c 0x874a0001 // Pin=-36dBm -0x81c 0x694c0001 // Pin=-34dBm -0x81c 0x684e0001 // Pin=-32dBm -0x81c 0x67500001 // Pin=-30dBm -0x81c 0x66520001 // Pin=-28dBm -0x81c 0x65540001 // Pin=-26dBm -0x81c 0x64560001 // Pin=-24dBm -0x81c 0x63580001 // Pin=-22dBm -0x81c 0x625a0001 // Pin=-20dBm -0x81c 0x455c0001 // Pin=-18dBm -0x81c 0x445e0001 // Pin=-16dBm -0x81c 0x43600001 // Pin=-14dBm -0x81c 0x42620001 // Pin=-12dBm -0x81c 0x28640001 // Pin=-10dBm -0x81c 0x27660001 // Pin=-08dBm -0x81c 0x26680001 // Pin=-06dBm -0x81c 0x256a0001 // Pin=-04dBm -0x81c 0x246c0001 // Pin=-02dBm -0x81c 0x236e0001 // Pin=-00dBm -0x81c 0x22700001 // Pin=+02dBm -0x81c 0x21720001 // Pin=+04dBm -0x81c 0x21740001 // Pin=+06dBm -0x81c 0x21760001 // Pin=+08dBm -0x81c 0x21780001 // Pin=+10dBm -0x81c 0x217a0001 // Pin=+12dBm -0x81c 0x217c0001 // Pin=+14dBm -0x81c 0x217e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xff040101 // Pin=-106dBm -0x81c 0xff060101 // Pin=-104dBm -0x81c 0xff080101 // Pin=-102dBm -0x81c 0xfe0a0101 // Pin=-100dBm -0x81c 0xfd0c0101 // Pin=-98dBm -0x81c 0xfc0e0101 // Pin=-96dBm -0x81c 0xfb100101 // Pin=-94dBm -0x81c 0xfa120101 // Pin=-92dBm -0x81c 0xf9140101 // Pin=-90dBm -0x81c 0xf8160101 // Pin=-88dBm -0x81c 0xf7180101 // Pin=-86dBm -0x81c 0xf61a0101 // Pin=-84dBm -0x81c 0xf51c0101 // Pin=-82dBm -0x81c 0xf41e0101 // Pin=-80dBm -0x81c 0xf3200101 // Pin=-78dBm -0x81c 0xf2220101 // Pin=-76dBm -0x81c 0xf1240101 // Pin=-74dBm -0x81c 0xf0260101 // Pin=-72dBm -0x81c 0xef280101 // Pin=-70dBm -0x81c 0xee2a0101 // Pin=-68dBm -0x81c 0xed2c0101 // Pin=-66dBm -0x81c 0xec2e0101 // Pin=-64dBm -0x81c 0xeb300101 // Pin=-62dBm -0x81c 0xea320101 // Pin=-60dBm -0x81c 0xe9340101 // Pin=-58dBm -0x81c 0xe8360101 // Pin=-56dBm -0x81c 0xe7380101 // Pin=-54dBm -0x81c 0xe63a0101 // Pin=-52dBm -0x81c 0xe53c0101 // Pin=-50dBm -0x81c 0xe43e0101 // Pin=-48dBm -0x81c 0xe3400101 // Pin=-46dBm -0x81c 0xe2420101 // Pin=-44dBm -0x81c 0xc6440101 // Pin=-42dBm -0x81c 0xc5460101 // Pin=-40dBm -0x81c 0xc4480101 // Pin=-38dBm -0x81c 0xc34a0101 // Pin=-36dBm -0x81c 0xc24c0101 // Pin=-34dBm -0x81c 0xa54e0101 // Pin=-32dBm -0x81c 0xa4500101 // Pin=-30dBm -0x81c 0xa3520101 // Pin=-28dBm -0x81c 0xa2540101 // Pin=-26dBm -0x81c 0x84560101 // Pin=-24dBm -0x81c 0x83580101 // Pin=-22dBm -0x81c 0x825a0101 // Pin=-20dBm -0x81c 0x475c0101 // Pin=-18dBm -0x81c 0x465e0101 // Pin=-16dBm -0x81c 0x45600101 // Pin=-14dBm -0x81c 0x44620101 // Pin=-12dBm -0x81c 0x43640101 // Pin=-10dBm -0x81c 0x25660101 // Pin=-08dBm -0x81c 0x24680101 // Pin=-06dBm -0x81c 0x236a0101 // Pin=-04dBm -0x81c 0x226c0101 // Pin=-02dBm -0x81c 0x046e0101 // Pin=-00dBm -0x81c 0x03700101 // Pin=+02dBm -0x81c 0x02720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table -0x1850 0x22 -0x1850 0x20 // toogle initial gain twice for valid gain table -0x1a50 0x22 -0x1a50 0x20 // toogle initial gain twice for valid gain table +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xfe020001 // Pin=-108dBm +0x81c 0xfd040001 // Pin=-106dBm +0x81c 0xfc060001 // Pin=-104dBm +0x81c 0xfb080001 // Pin=-102dBm +0x81c 0xfa0a0001 // Pin=-100dBm +0x81c 0xf90c0001 // Pin=-98dBm +0x81c 0xf80e0001 // Pin=-96dBm +0x81c 0xf7100001 // Pin=-94dBm +0x81c 0xf6120001 // Pin=-92dBm +0x81c 0xf5140001 // Pin=-90dBm +0x81c 0xf4160001 // Pin=-88dBm +0x81c 0xf3180001 // Pin=-86dBm +0x81c 0xf21a0001 // Pin=-84dBm +0x81c 0xf11c0001 // Pin=-82dBm +0x81c 0xef1e0001 // Pin=-80dBm +0x81c 0xee200001 // Pin=-78dBm +0x81c 0xed220001 // Pin=-76dBm +0x81c 0xec240001 // Pin=-74dBm +0x81c 0xeb260001 // Pin=-72dBm +0x81c 0xea280001 // Pin=-70dBm +0x81c 0xe92a0001 // Pin=-68dBm +0x81c 0xe82c0001 // Pin=-66dBm +0x81c 0xe72e0001 // Pin=-64dBm +0x81c 0xe6300001 // Pin=-62dBm +0x81c 0xe5320001 // Pin=-60dBm +0x81c 0xe4340001 // Pin=-58dBm +0x81c 0xc7360001 // Pin=-56dBm +0x81c 0xc6380001 // Pin=-54dBm +0x81c 0xc53a0001 // Pin=-52dBm +0x81c 0xc43c0001 // Pin=-50dBm +0x81c 0xc33e0001 // Pin=-48dBm +0x81c 0xa5400001 // Pin=-46dBm +0x81c 0xa4420001 // Pin=-44dBm +0x81c 0xa3440001 // Pin=-42dBm +0x81c 0xa2460001 // Pin=-40dBm +0x81c 0x88480001 // Pin=-38dBm +0x81c 0x874a0001 // Pin=-36dBm +0x81c 0x694c0001 // Pin=-34dBm +0x81c 0x684e0001 // Pin=-32dBm +0x81c 0x67500001 // Pin=-30dBm +0x81c 0x66520001 // Pin=-28dBm +0x81c 0x65540001 // Pin=-26dBm +0x81c 0x64560001 // Pin=-24dBm +0x81c 0x63580001 // Pin=-22dBm +0x81c 0x625a0001 // Pin=-20dBm +0x81c 0x455c0001 // Pin=-18dBm +0x81c 0x445e0001 // Pin=-16dBm +0x81c 0x43600001 // Pin=-14dBm +0x81c 0x42620001 // Pin=-12dBm +0x81c 0x28640001 // Pin=-10dBm +0x81c 0x27660001 // Pin=-08dBm +0x81c 0x26680001 // Pin=-06dBm +0x81c 0x256a0001 // Pin=-04dBm +0x81c 0x246c0001 // Pin=-02dBm +0x81c 0x236e0001 // Pin=-00dBm +0x81c 0x22700001 // Pin=+02dBm +0x81c 0x21720001 // Pin=+04dBm +0x81c 0x21740001 // Pin=+06dBm +0x81c 0x21760001 // Pin=+08dBm +0x81c 0x21780001 // Pin=+10dBm +0x81c 0x217a0001 // Pin=+12dBm +0x81c 0x217c0001 // Pin=+14dBm +0x81c 0x217e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xff040101 // Pin=-106dBm +0x81c 0xff060101 // Pin=-104dBm +0x81c 0xff080101 // Pin=-102dBm +0x81c 0xfe0a0101 // Pin=-100dBm +0x81c 0xfd0c0101 // Pin=-98dBm +0x81c 0xfc0e0101 // Pin=-96dBm +0x81c 0xfb100101 // Pin=-94dBm +0x81c 0xfa120101 // Pin=-92dBm +0x81c 0xf9140101 // Pin=-90dBm +0x81c 0xf8160101 // Pin=-88dBm +0x81c 0xf7180101 // Pin=-86dBm +0x81c 0xf61a0101 // Pin=-84dBm +0x81c 0xf51c0101 // Pin=-82dBm +0x81c 0xf41e0101 // Pin=-80dBm +0x81c 0xf3200101 // Pin=-78dBm +0x81c 0xf2220101 // Pin=-76dBm +0x81c 0xf1240101 // Pin=-74dBm +0x81c 0xf0260101 // Pin=-72dBm +0x81c 0xef280101 // Pin=-70dBm +0x81c 0xee2a0101 // Pin=-68dBm +0x81c 0xed2c0101 // Pin=-66dBm +0x81c 0xec2e0101 // Pin=-64dBm +0x81c 0xeb300101 // Pin=-62dBm +0x81c 0xea320101 // Pin=-60dBm +0x81c 0xe9340101 // Pin=-58dBm +0x81c 0xe8360101 // Pin=-56dBm +0x81c 0xe7380101 // Pin=-54dBm +0x81c 0xe63a0101 // Pin=-52dBm +0x81c 0xe53c0101 // Pin=-50dBm +0x81c 0xe43e0101 // Pin=-48dBm +0x81c 0xe3400101 // Pin=-46dBm +0x81c 0xe2420101 // Pin=-44dBm +0x81c 0xc6440101 // Pin=-42dBm +0x81c 0xc5460101 // Pin=-40dBm +0x81c 0xc4480101 // Pin=-38dBm +0x81c 0xc34a0101 // Pin=-36dBm +0x81c 0xc24c0101 // Pin=-34dBm +0x81c 0xa54e0101 // Pin=-32dBm +0x81c 0xa4500101 // Pin=-30dBm +0x81c 0xa3520101 // Pin=-28dBm +0x81c 0xa2540101 // Pin=-26dBm +0x81c 0x84560101 // Pin=-24dBm +0x81c 0x83580101 // Pin=-22dBm +0x81c 0x825a0101 // Pin=-20dBm +0x81c 0x475c0101 // Pin=-18dBm +0x81c 0x465e0101 // Pin=-16dBm +0x81c 0x45600101 // Pin=-14dBm +0x81c 0x44620101 // Pin=-12dBm +0x81c 0x43640101 // Pin=-10dBm +0x81c 0x25660101 // Pin=-08dBm +0x81c 0x24680101 // Pin=-06dBm +0x81c 0x236a0101 // Pin=-04dBm +0x81c 0x226c0101 // Pin=-02dBm +0x81c 0x046e0101 // Pin=-00dBm +0x81c 0x03700101 // Pin=+02dBm +0x81c 0x02720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table +0x1850 0x22 +0x1850 0x20 // toogle initial gain twice for valid gain table +0x1a50 0x22 +0x1a50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp_hp.txt old mode 100755 new mode 100644 index b304aa944b7..fd6aa7324a8 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/AGC_TAB_8822Bmp_hp.txt @@ -1,332 +1,332 @@ -0x81c 0xff000003 // turn on the table for write data -0x81c 0xf5000003 // Pin=-110dBm -0x81c 0xf4020003 // Pin=-108dBm -0x81c 0xf3040003 // Pin=-106dBm -0x81c 0xf2060003 // Pin=-104dBm -0x81c 0xf1080003 // Pin=-102dBm -0x81c 0xf00a0003 // Pin=-100dBm -0x81c 0xef0c0003 // Pin=-98dBm -0x81c 0xee0e0003 // Pin=-96dBm -0x81c 0xed100003 // Pin=-94dBm -0x81c 0xec120003 // Pin=-92dBm -0x81c 0xeb140003 // Pin=-90dBm -0x81c 0xea160003 // Pin=-88dBm -0x81c 0xe9180003 // Pin=-86dBm -0x81c 0xe81a0003 // Pin=-84dBm -0x81c 0xe71c0003 // Pin=-82dBm -0x81c 0xe61e0003 // Pin=-80dBm -0x81c 0xe5200003 // Pin=-78dBm -0x81c 0xe4220003 // Pin=-76dBm -0x81c 0xe3240003 // Pin=-74dBm -0x81c 0xe2260003 // Pin=-72dBm -0x81c 0xe1280003 // Pin=-70dBm -0x81c 0xe02a0003 // Pin=-68dBm -0x81c 0xc32c0003 // Pin=-66dBm -0x81c 0xc22e0003 // Pin=-64dBm -0x81c 0xc1300003 // Pin=-62dBm -0x81c 0xc0320003 // Pin=-60dBm -0x81c 0xa4340003 // Pin=-58dBm -0x81c 0xa3360003 // Pin=-56dBm -0x81c 0xa2380003 // Pin=-54dBm -0x81c 0xa13a0003 // Pin=-52dBm -0x81c 0xa03c0003 // Pin=-50dBm -0x81c 0x823e0003 // Pin=-48dBm -0x81c 0x81400003 // Pin=-46dBm -0x81c 0x80420003 // Pin=-44dBm -0x81c 0x64440003 // Pin=-42dBm -0x81c 0x63460003 // Pin=-40dBm -0x81c 0x62480003 // Pin=-38dBm -0x81c 0x614a0003 // Pin=-36dBm -0x81c 0x604c0003 // Pin=-34dBm -0x81c 0x454e0003 // Pin=-32dBm -0x81c 0x44500003 // Pin=-30dBm -0x81c 0x43520003 // Pin=-28dBm -0x81c 0x42540003 // Pin=-26dBm -0x81c 0x41560003 // Pin=-24dBm -0x81c 0x40580003 // Pin=-22dBm -0x81c 0x055a0003 // Pin=-20dBm -0x81c 0x045c0003 // Pin=-18dBm -0x81c 0x035e0003 // Pin=-16dBm -0x81c 0x02600003 // Pin=-14dBm -0x81c 0x01620003 // Pin=-12dBm -0x81c 0x00640003 // Pin=-10dBm -0x81c 0x00660003 // Pin=-08dBm -0x81c 0x00680003 // Pin=-06dBm -0x81c 0x006a0003 // Pin=-04dBm -0x81c 0x006c0003 // Pin=-02dBm -0x81c 0x006e0003 // Pin=-00dBm -0x81c 0x00700003 // Pin=+02dBm -0x81c 0x00720003 // Pin=+04dBm -0x81c 0x00740003 // Pin=+06dBm -0x81c 0x00760003 // Pin=+08dBm -0x81c 0x00780003 // Pin=+10dBm -0x81c 0x007a0003 // Pin=+12dBm -0x81c 0x007c0003 // Pin=+14dBm -0x81c 0x007e0003 // Pin=+16dBm -// AGC_TABLE 1 (5G LB) -0x81c 0xf7000103 // Pin=-110dBm -0x81c 0xf6020103 // Pin=-108dBm -0x81c 0xf5040103 // Pin=-106dBm -0x81c 0xf4060103 // Pin=-104dBm -0x81c 0xf3080103 // Pin=-102dBm -0x81c 0xf20a0103 // Pin=-100dBm -0x81c 0xf10c0103 // Pin=-98dBm -0x81c 0xf00e0103 // Pin=-96dBm -0x81c 0xef100103 // Pin=-94dBm -0x81c 0xee120103 // Pin=-92dBm -0x81c 0xed140103 // Pin=-90dBm -0x81c 0xec160103 // Pin=-88dBm -0x81c 0xeb180103 // Pin=-86dBm -0x81c 0xea1a0103 // Pin=-84dBm -0x81c 0xe91c0103 // Pin=-82dBm -0x81c 0xe81e0103 // Pin=-80dBm -0x81c 0xe7200103 // Pin=-78dBm -0x81c 0xe6220103 // Pin=-76dBm -0x81c 0xe5240103 // Pin=-74dBm -0x81c 0xe4260103 // Pin=-72dBm -0x81c 0xe3280103 // Pin=-70dBm -0x81c 0xe22a0103 // Pin=-68dBm -0x81c 0xe12c0103 // Pin=-66dBm -0x81c 0xe02e0103 // Pin=-64dBm -0x81c 0xc3300103 // Pin=-62dBm -0x81c 0xc2320103 // Pin=-60dBm -0x81c 0xc1340103 // Pin=-58dBm -0x81c 0xc0360103 // Pin=-56dBm -0x81c 0xa3380103 // Pin=-54dBm -0x81c 0xa23a0103 // Pin=-52dBm -0x81c 0xa13c0103 // Pin=-50dBm -0x81c 0xa03e0103 // Pin=-48dBm -0x81c 0x82400103 // Pin=-46dBm -0x81c 0x81420103 // Pin=-44dBm -0x81c 0x80440103 // Pin=-42dBm -0x81c 0x62460103 // Pin=-40dBm -0x81c 0x61480103 // Pin=-38dBm -0x81c 0x434a0103 // Pin=-36dBm -0x81c 0x424c0103 // Pin=-34dBm -0x81c 0x414e0103 // Pin=-32dBm -0x81c 0x40500103 // Pin=-30dBm -0x81c 0x22520103 // Pin=-28dBm -0x81c 0x21540103 // Pin=-26dBm -0x81c 0x20560103 // Pin=-24dBm -0x81c 0x03580103 // Pin=-22dBm -0x81c 0x025a0103 // Pin=-20dBm -0x81c 0x015c0103 // Pin=-18dBm -0x81c 0x005e0103 // Pin=-16dBm -0x81c 0x00600103 // Pin=-14dBm -0x81c 0x00620103 // Pin=-12dBm -0x81c 0x00640103 // Pin=-10dBm -0x81c 0x00660103 // Pin=-08dBm -0x81c 0x00680103 // Pin=-06dBm -0x81c 0x006a0103 // Pin=-04dBm -0x81c 0x006c0103 // Pin=-02dBm -0x81c 0x006e0103 // Pin=-00dBm -0x81c 0x00700103 // Pin=+02dBm -0x81c 0x00720103 // Pin=+04dBm -0x81c 0x00740103 // Pin=+06dBm -0x81c 0x00760103 // Pin=+08dBm -0x81c 0x00780103 // Pin=+10dBm -0x81c 0x007a0103 // Pin=+12dBm -0x81c 0x007c0103 // Pin=+14dBm -0x81c 0x007e0103 // Pin=+16dBm -// AGC_TABLE 2 (5G MB) -0x81c 0xf6000203 // Pin=-110dBm -0x81c 0xf5020203 // Pin=-108dBm -0x81c 0xf4040203 // Pin=-106dBm -0x81c 0xf3060203 // Pin=-104dBm -0x81c 0xf2080203 // Pin=-102dBm -0x81c 0xf10a0203 // Pin=-100dBm -0x81c 0xf00c0203 // Pin=-98dBm -0x81c 0xef0e0203 // Pin=-96dBm -0x81c 0xee100203 // Pin=-94dBm -0x81c 0xed120203 // Pin=-92dBm -0x81c 0xec140203 // Pin=-90dBm -0x81c 0xeb160203 // Pin=-88dBm -0x81c 0xea180203 // Pin=-86dBm -0x81c 0xe91a0203 // Pin=-84dBm -0x81c 0xe81c0203 // Pin=-82dBm -0x81c 0xe71e0203 // Pin=-80dBm -0x81c 0xe6200203 // Pin=-78dBm -0x81c 0xe5220203 // Pin=-76dBm -0x81c 0xe4240203 // Pin=-74dBm -0x81c 0xe3260203 // Pin=-72dBm -0x81c 0xe2280203 // Pin=-70dBm -0x81c 0xe12a0203 // Pin=-68dBm -0x81c 0xe02c0203 // Pin=-66dBm -0x81c 0xc42e0203 // Pin=-64dBm -0x81c 0xc3300203 // Pin=-62dBm -0x81c 0xc2320203 // Pin=-60dBm -0x81c 0xc1340203 // Pin=-58dBm -0x81c 0xc0360203 // Pin=-56dBm -0x81c 0xa2380203 // Pin=-54dBm -0x81c 0xa13a0203 // Pin=-52dBm -0x81c 0xa03c0203 // Pin=-50dBm -0x81c 0x823e0203 // Pin=-48dBm -0x81c 0x81400203 // Pin=-46dBm -0x81c 0x80420203 // Pin=-44dBm -0x81c 0x63440203 // Pin=-42dBm -0x81c 0x62460203 // Pin=-40dBm -0x81c 0x61480203 // Pin=-38dBm -0x81c 0x604a0203 // Pin=-36dBm -0x81c 0x424c0203 // Pin=-34dBm -0x81c 0x414e0203 // Pin=-32dBm -0x81c 0x40500203 // Pin=-30dBm -0x81c 0x22520203 // Pin=-28dBm -0x81c 0x21540203 // Pin=-26dBm -0x81c 0x20560203 // Pin=-24dBm -0x81c 0x03580203 // Pin=-22dBm -0x81c 0x025a0203 // Pin=-20dBm -0x81c 0x015c0203 // Pin=-18dBm -0x81c 0x005e0203 // Pin=-16dBm -0x81c 0x00600203 // Pin=-14dBm -0x81c 0x00620203 // Pin=-12dBm -0x81c 0x00640203 // Pin=-10dBm -0x81c 0x00660203 // Pin=-08dBm -0x81c 0x00680203 // Pin=-06dBm -0x81c 0x006a0203 // Pin=-04dBm -0x81c 0x006c0203 // Pin=-02dBm -0x81c 0x006e0203 // Pin=-00dBm -0x81c 0x00700203 // Pin=+02dBm -0x81c 0x00720203 // Pin=+04dBm -0x81c 0x00740203 // Pin=+06dBm -0x81c 0x00760203 // Pin=+08dBm -0x81c 0x00780203 // Pin=+10dBm -0x81c 0x007a0203 // Pin=+12dBm -0x81c 0x007c0203 // Pin=+14dBm -0x81c 0x007e0203 // Pin=+16dBm -// AGC_TABLE 3 (5G HB) -0x81c 0xf6000303 // Pin=-110dBm -0x81c 0xf5020303 // Pin=-108dBm -0x81c 0xf4040303 // Pin=-106dBm -0x81c 0xf3060303 // Pin=-104dBm -0x81c 0xf2080303 // Pin=-102dBm -0x81c 0xf10a0303 // Pin=-100dBm -0x81c 0xf00c0303 // Pin=-98dBm -0x81c 0xef0e0303 // Pin=-96dBm -0x81c 0xee100303 // Pin=-94dBm -0x81c 0xed120303 // Pin=-92dBm -0x81c 0xec140303 // Pin=-90dBm -0x81c 0xeb160303 // Pin=-88dBm -0x81c 0xea180303 // Pin=-86dBm -0x81c 0xe91a0303 // Pin=-84dBm -0x81c 0xe81c0303 // Pin=-82dBm -0x81c 0xe71e0303 // Pin=-80dBm -0x81c 0xe6200303 // Pin=-78dBm -0x81c 0xe5220303 // Pin=-76dBm -0x81c 0xe4240303 // Pin=-74dBm -0x81c 0xe3260303 // Pin=-72dBm -0x81c 0xe2280303 // Pin=-70dBm -0x81c 0xe12a0303 // Pin=-68dBm -0x81c 0xe02c0303 // Pin=-66dBm -0x81c 0xc52e0303 // Pin=-64dBm -0x81c 0xc4300303 // Pin=-62dBm -0x81c 0xc3320303 // Pin=-60dBm -0x81c 0xc2340303 // Pin=-58dBm -0x81c 0xc1360303 // Pin=-56dBm -0x81c 0xc0380303 // Pin=-54dBm -0x81c 0xa23a0303 // Pin=-52dBm -0x81c 0xa13c0303 // Pin=-50dBm -0x81c 0xa03e0303 // Pin=-48dBm -0x81c 0x83400303 // Pin=-46dBm -0x81c 0x82420303 // Pin=-44dBm -0x81c 0x81440303 // Pin=-42dBm -0x81c 0x80460303 // Pin=-40dBm -0x81c 0x63480303 // Pin=-38dBm -0x81c 0x624a0303 // Pin=-36dBm -0x81c 0x614c0303 // Pin=-34dBm -0x81c 0x604e0303 // Pin=-32dBm -0x81c 0x41500303 // Pin=-30dBm -0x81c 0x40520303 // Pin=-28dBm -0x81c 0x22540303 // Pin=-26dBm -0x81c 0x21560303 // Pin=-24dBm -0x81c 0x20580303 // Pin=-22dBm -0x81c 0x035a0303 // Pin=-20dBm -0x81c 0x025c0303 // Pin=-18dBm -0x81c 0x015e0303 // Pin=-16dBm -0x81c 0x00600303 // Pin=-14dBm -0x81c 0x00620303 // Pin=-12dBm -0x81c 0x00640303 // Pin=-10dBm -0x81c 0x00660303 // Pin=-08dBm -0x81c 0x00680303 // Pin=-06dBm -0x81c 0x006a0303 // Pin=-04dBm -0x81c 0x006c0303 // Pin=-02dBm -0x81c 0x006e0303 // Pin=-00dBm -0x81c 0x00700303 // Pin=+02dBm -0x81c 0x00720303 // Pin=+04dBm -0x81c 0x00740303 // Pin=+06dBm -0x81c 0x00760303 // Pin=+08dBm -0x81c 0x00780303 // Pin=+10dBm -0x81c 0x007a0303 // Pin=+12dBm -0x81c 0x007c0303 // Pin=+14dBm -0x81c 0x007e0303 // Pin=+16dBm -// AGC_TABLE 4 (2G 11b) -0x81c 0xff000403 // turn on the table for write data -0x81c 0xf5000403 // Pin=-110dBm -0x81c 0xf4020403 // Pin=-108dBm -0x81c 0xf3040403 // Pin=-106dBm -0x81c 0xf2060403 // Pin=-104dBm -0x81c 0xf1080403 // Pin=-102dBm -0x81c 0xf00a0403 // Pin=-100dBm -0x81c 0xef0c0403 // Pin=-98dBm -0x81c 0xee0e0403 // Pin=-96dBm -0x81c 0xed100403 // Pin=-94dBm -0x81c 0xec120403 // Pin=-92dBm -0x81c 0xeb140403 // Pin=-90dBm -0x81c 0xea160403 // Pin=-88dBm -0x81c 0xe9180403 // Pin=-86dBm -0x81c 0xe81a0403 // Pin=-84dBm -0x81c 0xe71c0403 // Pin=-82dBm -0x81c 0xe61e0403 // Pin=-80dBm -0x81c 0xe5200403 // Pin=-78dBm -0x81c 0xe4220403 // Pin=-76dBm -0x81c 0xe3240403 // Pin=-74dBm -0x81c 0xe2260403 // Pin=-72dBm -0x81c 0xe1280403 // Pin=-70dBm -0x81c 0xe02a0403 // Pin=-68dBm -0x81c 0xc32c0403 // Pin=-66dBm -0x81c 0xc22e0403 // Pin=-64dBm -0x81c 0xc1300403 // Pin=-62dBm -0x81c 0xc0320403 // Pin=-60dBm -0x81c 0xa4340403 // Pin=-58dBm -0x81c 0xa3360403 // Pin=-56dBm -0x81c 0xa2380403 // Pin=-54dBm -0x81c 0xa13a0403 // Pin=-52dBm -0x81c 0xa03c0403 // Pin=-50dBm -0x81c 0x823e0403 // Pin=-48dBm -0x81c 0x81400403 // Pin=-46dBm -0x81c 0x80420403 // Pin=-44dBm -0x81c 0x64440403 // Pin=-42dBm -0x81c 0x63460403 // Pin=-40dBm -0x81c 0x62480403 // Pin=-38dBm -0x81c 0x614a0403 // Pin=-36dBm -0x81c 0x604c0403 // Pin=-34dBm -0x81c 0x454e0403 // Pin=-32dBm -0x81c 0x44500403 // Pin=-30dBm -0x81c 0x43520403 // Pin=-28dBm -0x81c 0x42540403 // Pin=-26dBm -0x81c 0x41560403 // Pin=-24dBm -0x81c 0x40580403 // Pin=-22dBm -0x81c 0x055a0403 // Pin=-20dBm -0x81c 0x045c0403 // Pin=-18dBm -0x81c 0x035e0403 // Pin=-16dBm -0x81c 0x02600403 // Pin=-14dBm -0x81c 0x01620403 // Pin=-12dBm -0x81c 0x00640403 // Pin=-10dBm -0x81c 0x00660403 // Pin=-08dBm -0x81c 0x00680403 // Pin=-06dBm -0x81c 0x006a0403 // Pin=-04dBm -0x81c 0x006c0403 // Pin=-02dBm -0x81c 0x006e0403 // Pin=-00dBm -0x81c 0x00700403 // Pin=+02dBm -0x81c 0x00720403 // Pin=+04dBm -0x81c 0x00740403 // Pin=+06dBm -0x81c 0x00760403 // Pin=+08dBm -0x81c 0x00780403 // Pin=+10dBm -0x81c 0x007a0403 // Pin=+12dBm -0x81c 0x007c0403 // Pin=+14dBm -0x81c 0x007e0403 // Pin=+16dBm -// toogle initial gain twice for valid gain table -0xc50 0x22 -0xc50 0x20 -0xe50 0x22 -0xe50 0x20 +0x81c 0xff000003 // turn on the table for write data +0x81c 0xf5000003 // Pin=-110dBm +0x81c 0xf4020003 // Pin=-108dBm +0x81c 0xf3040003 // Pin=-106dBm +0x81c 0xf2060003 // Pin=-104dBm +0x81c 0xf1080003 // Pin=-102dBm +0x81c 0xf00a0003 // Pin=-100dBm +0x81c 0xef0c0003 // Pin=-98dBm +0x81c 0xee0e0003 // Pin=-96dBm +0x81c 0xed100003 // Pin=-94dBm +0x81c 0xec120003 // Pin=-92dBm +0x81c 0xeb140003 // Pin=-90dBm +0x81c 0xea160003 // Pin=-88dBm +0x81c 0xe9180003 // Pin=-86dBm +0x81c 0xe81a0003 // Pin=-84dBm +0x81c 0xe71c0003 // Pin=-82dBm +0x81c 0xe61e0003 // Pin=-80dBm +0x81c 0xe5200003 // Pin=-78dBm +0x81c 0xe4220003 // Pin=-76dBm +0x81c 0xe3240003 // Pin=-74dBm +0x81c 0xe2260003 // Pin=-72dBm +0x81c 0xe1280003 // Pin=-70dBm +0x81c 0xe02a0003 // Pin=-68dBm +0x81c 0xc32c0003 // Pin=-66dBm +0x81c 0xc22e0003 // Pin=-64dBm +0x81c 0xc1300003 // Pin=-62dBm +0x81c 0xc0320003 // Pin=-60dBm +0x81c 0xa4340003 // Pin=-58dBm +0x81c 0xa3360003 // Pin=-56dBm +0x81c 0xa2380003 // Pin=-54dBm +0x81c 0xa13a0003 // Pin=-52dBm +0x81c 0xa03c0003 // Pin=-50dBm +0x81c 0x823e0003 // Pin=-48dBm +0x81c 0x81400003 // Pin=-46dBm +0x81c 0x80420003 // Pin=-44dBm +0x81c 0x64440003 // Pin=-42dBm +0x81c 0x63460003 // Pin=-40dBm +0x81c 0x62480003 // Pin=-38dBm +0x81c 0x614a0003 // Pin=-36dBm +0x81c 0x604c0003 // Pin=-34dBm +0x81c 0x454e0003 // Pin=-32dBm +0x81c 0x44500003 // Pin=-30dBm +0x81c 0x43520003 // Pin=-28dBm +0x81c 0x42540003 // Pin=-26dBm +0x81c 0x41560003 // Pin=-24dBm +0x81c 0x40580003 // Pin=-22dBm +0x81c 0x055a0003 // Pin=-20dBm +0x81c 0x045c0003 // Pin=-18dBm +0x81c 0x035e0003 // Pin=-16dBm +0x81c 0x02600003 // Pin=-14dBm +0x81c 0x01620003 // Pin=-12dBm +0x81c 0x00640003 // Pin=-10dBm +0x81c 0x00660003 // Pin=-08dBm +0x81c 0x00680003 // Pin=-06dBm +0x81c 0x006a0003 // Pin=-04dBm +0x81c 0x006c0003 // Pin=-02dBm +0x81c 0x006e0003 // Pin=-00dBm +0x81c 0x00700003 // Pin=+02dBm +0x81c 0x00720003 // Pin=+04dBm +0x81c 0x00740003 // Pin=+06dBm +0x81c 0x00760003 // Pin=+08dBm +0x81c 0x00780003 // Pin=+10dBm +0x81c 0x007a0003 // Pin=+12dBm +0x81c 0x007c0003 // Pin=+14dBm +0x81c 0x007e0003 // Pin=+16dBm +// AGC_TABLE 1 (5G LB) +0x81c 0xf7000103 // Pin=-110dBm +0x81c 0xf6020103 // Pin=-108dBm +0x81c 0xf5040103 // Pin=-106dBm +0x81c 0xf4060103 // Pin=-104dBm +0x81c 0xf3080103 // Pin=-102dBm +0x81c 0xf20a0103 // Pin=-100dBm +0x81c 0xf10c0103 // Pin=-98dBm +0x81c 0xf00e0103 // Pin=-96dBm +0x81c 0xef100103 // Pin=-94dBm +0x81c 0xee120103 // Pin=-92dBm +0x81c 0xed140103 // Pin=-90dBm +0x81c 0xec160103 // Pin=-88dBm +0x81c 0xeb180103 // Pin=-86dBm +0x81c 0xea1a0103 // Pin=-84dBm +0x81c 0xe91c0103 // Pin=-82dBm +0x81c 0xe81e0103 // Pin=-80dBm +0x81c 0xe7200103 // Pin=-78dBm +0x81c 0xe6220103 // Pin=-76dBm +0x81c 0xe5240103 // Pin=-74dBm +0x81c 0xe4260103 // Pin=-72dBm +0x81c 0xe3280103 // Pin=-70dBm +0x81c 0xe22a0103 // Pin=-68dBm +0x81c 0xe12c0103 // Pin=-66dBm +0x81c 0xe02e0103 // Pin=-64dBm +0x81c 0xc3300103 // Pin=-62dBm +0x81c 0xc2320103 // Pin=-60dBm +0x81c 0xc1340103 // Pin=-58dBm +0x81c 0xc0360103 // Pin=-56dBm +0x81c 0xa3380103 // Pin=-54dBm +0x81c 0xa23a0103 // Pin=-52dBm +0x81c 0xa13c0103 // Pin=-50dBm +0x81c 0xa03e0103 // Pin=-48dBm +0x81c 0x82400103 // Pin=-46dBm +0x81c 0x81420103 // Pin=-44dBm +0x81c 0x80440103 // Pin=-42dBm +0x81c 0x62460103 // Pin=-40dBm +0x81c 0x61480103 // Pin=-38dBm +0x81c 0x434a0103 // Pin=-36dBm +0x81c 0x424c0103 // Pin=-34dBm +0x81c 0x414e0103 // Pin=-32dBm +0x81c 0x40500103 // Pin=-30dBm +0x81c 0x22520103 // Pin=-28dBm +0x81c 0x21540103 // Pin=-26dBm +0x81c 0x20560103 // Pin=-24dBm +0x81c 0x03580103 // Pin=-22dBm +0x81c 0x025a0103 // Pin=-20dBm +0x81c 0x015c0103 // Pin=-18dBm +0x81c 0x005e0103 // Pin=-16dBm +0x81c 0x00600103 // Pin=-14dBm +0x81c 0x00620103 // Pin=-12dBm +0x81c 0x00640103 // Pin=-10dBm +0x81c 0x00660103 // Pin=-08dBm +0x81c 0x00680103 // Pin=-06dBm +0x81c 0x006a0103 // Pin=-04dBm +0x81c 0x006c0103 // Pin=-02dBm +0x81c 0x006e0103 // Pin=-00dBm +0x81c 0x00700103 // Pin=+02dBm +0x81c 0x00720103 // Pin=+04dBm +0x81c 0x00740103 // Pin=+06dBm +0x81c 0x00760103 // Pin=+08dBm +0x81c 0x00780103 // Pin=+10dBm +0x81c 0x007a0103 // Pin=+12dBm +0x81c 0x007c0103 // Pin=+14dBm +0x81c 0x007e0103 // Pin=+16dBm +// AGC_TABLE 2 (5G MB) +0x81c 0xf6000203 // Pin=-110dBm +0x81c 0xf5020203 // Pin=-108dBm +0x81c 0xf4040203 // Pin=-106dBm +0x81c 0xf3060203 // Pin=-104dBm +0x81c 0xf2080203 // Pin=-102dBm +0x81c 0xf10a0203 // Pin=-100dBm +0x81c 0xf00c0203 // Pin=-98dBm +0x81c 0xef0e0203 // Pin=-96dBm +0x81c 0xee100203 // Pin=-94dBm +0x81c 0xed120203 // Pin=-92dBm +0x81c 0xec140203 // Pin=-90dBm +0x81c 0xeb160203 // Pin=-88dBm +0x81c 0xea180203 // Pin=-86dBm +0x81c 0xe91a0203 // Pin=-84dBm +0x81c 0xe81c0203 // Pin=-82dBm +0x81c 0xe71e0203 // Pin=-80dBm +0x81c 0xe6200203 // Pin=-78dBm +0x81c 0xe5220203 // Pin=-76dBm +0x81c 0xe4240203 // Pin=-74dBm +0x81c 0xe3260203 // Pin=-72dBm +0x81c 0xe2280203 // Pin=-70dBm +0x81c 0xe12a0203 // Pin=-68dBm +0x81c 0xe02c0203 // Pin=-66dBm +0x81c 0xc42e0203 // Pin=-64dBm +0x81c 0xc3300203 // Pin=-62dBm +0x81c 0xc2320203 // Pin=-60dBm +0x81c 0xc1340203 // Pin=-58dBm +0x81c 0xc0360203 // Pin=-56dBm +0x81c 0xa2380203 // Pin=-54dBm +0x81c 0xa13a0203 // Pin=-52dBm +0x81c 0xa03c0203 // Pin=-50dBm +0x81c 0x823e0203 // Pin=-48dBm +0x81c 0x81400203 // Pin=-46dBm +0x81c 0x80420203 // Pin=-44dBm +0x81c 0x63440203 // Pin=-42dBm +0x81c 0x62460203 // Pin=-40dBm +0x81c 0x61480203 // Pin=-38dBm +0x81c 0x604a0203 // Pin=-36dBm +0x81c 0x424c0203 // Pin=-34dBm +0x81c 0x414e0203 // Pin=-32dBm +0x81c 0x40500203 // Pin=-30dBm +0x81c 0x22520203 // Pin=-28dBm +0x81c 0x21540203 // Pin=-26dBm +0x81c 0x20560203 // Pin=-24dBm +0x81c 0x03580203 // Pin=-22dBm +0x81c 0x025a0203 // Pin=-20dBm +0x81c 0x015c0203 // Pin=-18dBm +0x81c 0x005e0203 // Pin=-16dBm +0x81c 0x00600203 // Pin=-14dBm +0x81c 0x00620203 // Pin=-12dBm +0x81c 0x00640203 // Pin=-10dBm +0x81c 0x00660203 // Pin=-08dBm +0x81c 0x00680203 // Pin=-06dBm +0x81c 0x006a0203 // Pin=-04dBm +0x81c 0x006c0203 // Pin=-02dBm +0x81c 0x006e0203 // Pin=-00dBm +0x81c 0x00700203 // Pin=+02dBm +0x81c 0x00720203 // Pin=+04dBm +0x81c 0x00740203 // Pin=+06dBm +0x81c 0x00760203 // Pin=+08dBm +0x81c 0x00780203 // Pin=+10dBm +0x81c 0x007a0203 // Pin=+12dBm +0x81c 0x007c0203 // Pin=+14dBm +0x81c 0x007e0203 // Pin=+16dBm +// AGC_TABLE 3 (5G HB) +0x81c 0xf6000303 // Pin=-110dBm +0x81c 0xf5020303 // Pin=-108dBm +0x81c 0xf4040303 // Pin=-106dBm +0x81c 0xf3060303 // Pin=-104dBm +0x81c 0xf2080303 // Pin=-102dBm +0x81c 0xf10a0303 // Pin=-100dBm +0x81c 0xf00c0303 // Pin=-98dBm +0x81c 0xef0e0303 // Pin=-96dBm +0x81c 0xee100303 // Pin=-94dBm +0x81c 0xed120303 // Pin=-92dBm +0x81c 0xec140303 // Pin=-90dBm +0x81c 0xeb160303 // Pin=-88dBm +0x81c 0xea180303 // Pin=-86dBm +0x81c 0xe91a0303 // Pin=-84dBm +0x81c 0xe81c0303 // Pin=-82dBm +0x81c 0xe71e0303 // Pin=-80dBm +0x81c 0xe6200303 // Pin=-78dBm +0x81c 0xe5220303 // Pin=-76dBm +0x81c 0xe4240303 // Pin=-74dBm +0x81c 0xe3260303 // Pin=-72dBm +0x81c 0xe2280303 // Pin=-70dBm +0x81c 0xe12a0303 // Pin=-68dBm +0x81c 0xe02c0303 // Pin=-66dBm +0x81c 0xc52e0303 // Pin=-64dBm +0x81c 0xc4300303 // Pin=-62dBm +0x81c 0xc3320303 // Pin=-60dBm +0x81c 0xc2340303 // Pin=-58dBm +0x81c 0xc1360303 // Pin=-56dBm +0x81c 0xc0380303 // Pin=-54dBm +0x81c 0xa23a0303 // Pin=-52dBm +0x81c 0xa13c0303 // Pin=-50dBm +0x81c 0xa03e0303 // Pin=-48dBm +0x81c 0x83400303 // Pin=-46dBm +0x81c 0x82420303 // Pin=-44dBm +0x81c 0x81440303 // Pin=-42dBm +0x81c 0x80460303 // Pin=-40dBm +0x81c 0x63480303 // Pin=-38dBm +0x81c 0x624a0303 // Pin=-36dBm +0x81c 0x614c0303 // Pin=-34dBm +0x81c 0x604e0303 // Pin=-32dBm +0x81c 0x41500303 // Pin=-30dBm +0x81c 0x40520303 // Pin=-28dBm +0x81c 0x22540303 // Pin=-26dBm +0x81c 0x21560303 // Pin=-24dBm +0x81c 0x20580303 // Pin=-22dBm +0x81c 0x035a0303 // Pin=-20dBm +0x81c 0x025c0303 // Pin=-18dBm +0x81c 0x015e0303 // Pin=-16dBm +0x81c 0x00600303 // Pin=-14dBm +0x81c 0x00620303 // Pin=-12dBm +0x81c 0x00640303 // Pin=-10dBm +0x81c 0x00660303 // Pin=-08dBm +0x81c 0x00680303 // Pin=-06dBm +0x81c 0x006a0303 // Pin=-04dBm +0x81c 0x006c0303 // Pin=-02dBm +0x81c 0x006e0303 // Pin=-00dBm +0x81c 0x00700303 // Pin=+02dBm +0x81c 0x00720303 // Pin=+04dBm +0x81c 0x00740303 // Pin=+06dBm +0x81c 0x00760303 // Pin=+08dBm +0x81c 0x00780303 // Pin=+10dBm +0x81c 0x007a0303 // Pin=+12dBm +0x81c 0x007c0303 // Pin=+14dBm +0x81c 0x007e0303 // Pin=+16dBm +// AGC_TABLE 4 (2G 11b) +0x81c 0xff000403 // turn on the table for write data +0x81c 0xf5000403 // Pin=-110dBm +0x81c 0xf4020403 // Pin=-108dBm +0x81c 0xf3040403 // Pin=-106dBm +0x81c 0xf2060403 // Pin=-104dBm +0x81c 0xf1080403 // Pin=-102dBm +0x81c 0xf00a0403 // Pin=-100dBm +0x81c 0xef0c0403 // Pin=-98dBm +0x81c 0xee0e0403 // Pin=-96dBm +0x81c 0xed100403 // Pin=-94dBm +0x81c 0xec120403 // Pin=-92dBm +0x81c 0xeb140403 // Pin=-90dBm +0x81c 0xea160403 // Pin=-88dBm +0x81c 0xe9180403 // Pin=-86dBm +0x81c 0xe81a0403 // Pin=-84dBm +0x81c 0xe71c0403 // Pin=-82dBm +0x81c 0xe61e0403 // Pin=-80dBm +0x81c 0xe5200403 // Pin=-78dBm +0x81c 0xe4220403 // Pin=-76dBm +0x81c 0xe3240403 // Pin=-74dBm +0x81c 0xe2260403 // Pin=-72dBm +0x81c 0xe1280403 // Pin=-70dBm +0x81c 0xe02a0403 // Pin=-68dBm +0x81c 0xc32c0403 // Pin=-66dBm +0x81c 0xc22e0403 // Pin=-64dBm +0x81c 0xc1300403 // Pin=-62dBm +0x81c 0xc0320403 // Pin=-60dBm +0x81c 0xa4340403 // Pin=-58dBm +0x81c 0xa3360403 // Pin=-56dBm +0x81c 0xa2380403 // Pin=-54dBm +0x81c 0xa13a0403 // Pin=-52dBm +0x81c 0xa03c0403 // Pin=-50dBm +0x81c 0x823e0403 // Pin=-48dBm +0x81c 0x81400403 // Pin=-46dBm +0x81c 0x80420403 // Pin=-44dBm +0x81c 0x64440403 // Pin=-42dBm +0x81c 0x63460403 // Pin=-40dBm +0x81c 0x62480403 // Pin=-38dBm +0x81c 0x614a0403 // Pin=-36dBm +0x81c 0x604c0403 // Pin=-34dBm +0x81c 0x454e0403 // Pin=-32dBm +0x81c 0x44500403 // Pin=-30dBm +0x81c 0x43520403 // Pin=-28dBm +0x81c 0x42540403 // Pin=-26dBm +0x81c 0x41560403 // Pin=-24dBm +0x81c 0x40580403 // Pin=-22dBm +0x81c 0x055a0403 // Pin=-20dBm +0x81c 0x045c0403 // Pin=-18dBm +0x81c 0x035e0403 // Pin=-16dBm +0x81c 0x02600403 // Pin=-14dBm +0x81c 0x01620403 // Pin=-12dBm +0x81c 0x00640403 // Pin=-10dBm +0x81c 0x00660403 // Pin=-08dBm +0x81c 0x00680403 // Pin=-06dBm +0x81c 0x006a0403 // Pin=-04dBm +0x81c 0x006c0403 // Pin=-02dBm +0x81c 0x006e0403 // Pin=-00dBm +0x81c 0x00700403 // Pin=+02dBm +0x81c 0x00720403 // Pin=+04dBm +0x81c 0x00740403 // Pin=+06dBm +0x81c 0x00760403 // Pin=+08dBm +0x81c 0x00780403 // Pin=+10dBm +0x81c 0x007a0403 // Pin=+12dBm +0x81c 0x007c0403 // Pin=+14dBm +0x81c 0x007e0403 // Pin=+16dBm +// toogle initial gain twice for valid gain table +0xc50 0x22 +0xc50 0x20 +0xe50 0x22 +0xe50 0x20 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_high_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_high_8822B.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_high_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_high_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_low_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_low_8822B.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_low_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_low_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_normal_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_normal_8822B.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_normal_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_def_normal_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_high_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_high_8822B.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_high_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_high_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_low_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_low_8822B.txt old mode 100755 new mode 100644 index 81adbeca968..82637163259 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_low_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_low_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03080000 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03080000 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_normal_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_normal_8822B.txt old mode 100755 new mode 100644 index 0925edbc913..8024b7effe3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_normal_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_gen_normal_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03083333 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03083333 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_state_criteria_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_state_criteria_8822B.txt old mode 100755 new mode 100644 index 18d91fac5d0..d44bcb85c66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_state_criteria_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_state_criteria_8822B.txt @@ -1,35 +1,35 @@ -////Release version: 8881A.0820.2013 -// State: -// 1.) MACDM_TP_STATE_DEFAULT -// 2.) MACDM_TP_STATE_GENERAL -// 3.) MACDM_TP_STATE_TXOP -// So, we need four criteria -// 1.) MACDM_TP_THRS_DEF_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 2.) MACDM_TP_THRS_GEN_TO_DEF -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 3.) MACDM_TP_THRS_GEN_TO_TXOP -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -// 4.) MACDM_TP_THRS_TXOP_TO_GEN -// a.) RSSI low -// b.) RSSI normal -// c.) RSSI high -0x28 -0x28 -0x28 -0x1E -0x1E -0x1E -0x8C -0x8C -0x8C -0x82 -0x82 -0x82 +////Release version: 8881A.0820.2013 +// State: +// 1.) MACDM_TP_STATE_DEFAULT +// 2.) MACDM_TP_STATE_GENERAL +// 3.) MACDM_TP_STATE_TXOP +// So, we need four criteria +// 1.) MACDM_TP_THRS_DEF_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 2.) MACDM_TP_THRS_GEN_TO_DEF +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 3.) MACDM_TP_THRS_GEN_TO_TXOP +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +// 4.) MACDM_TP_THRS_TXOP_TO_GEN +// a.) RSSI low +// b.) RSSI normal +// c.) RSSI high +0x28 +0x28 +0x28 +0x1E +0x1E +0x1E +0x8C +0x8C +0x8C +0x82 +0x82 +0x82 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_high_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_high_8822B.txt old mode 100755 new mode 100644 index e01e46b9e5f..71936a7a338 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_high_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_high_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x0308AAAA +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x0308AAAA 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_low_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_low_8822B.txt old mode 100755 new mode 100644 index 760de6ccf1b..fd35b529ed0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_low_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_low_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03088888 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03088888 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_normal_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_normal_8822B.txt old mode 100755 new mode 100644 index 30889a39f89..0555ed20521 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_normal_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MACDM_txop_normal_8822B.txt @@ -1,4 +1,4 @@ -////Release version: 92E_TP_RSSI_Table_130923 -// Max line number: 30 -0x460 0x03089999 +////Release version: 92E_TP_RSSI_Table_130923 +// Max line number: 30 +0x460 0x03089999 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822B.txt old mode 100755 new mode 100644 index 0c28f4043ca..0d56ac61712 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822B.txt @@ -1,133 +1,133 @@ -0x010 0x7c // AFE power cut -0x025 0x00 // BIT_XTAL_GMN -0x073 0x10 // AFE iso -0x420 0x00 -0x428 0x0a -0x429 0x10 -0x430 0x00 //Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 //RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss -0x445 0xF0 -0x446 0x0E -0x447 0x1F -0x448 0x7C -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x0E -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x30 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x03 -0x49F 0xFE -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x01 -0x4A7 0x0E -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c7 0x80 //enable single packet ampdu -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x3F //max tx agg num =62 -0x4cb 0x3F //RTS max agg num =62 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x64 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x2a -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x64 // -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +0x010 0x7c // AFE power cut +0x025 0x00 // BIT_XTAL_GMN +0x073 0x10 // AFE iso +0x420 0x00 +0x428 0x0a +0x429 0x10 +0x430 0x00 //Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 //RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 //auto rate fall back 0 1ss 2ss 3ss +0x445 0xF0 +0x446 0x0E +0x447 0x1F +0x448 0x7C +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x0E +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x30 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x03 +0x49F 0xFE +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x01 +0x4A7 0x0E +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c7 0x80 //enable single packet ampdu +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x3F //max tx agg num =62 +0x4cb 0x3F //RTS max agg num =62 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x64 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x2a +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x64 // +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822Bmp.txt old mode 100755 new mode 100644 index fd1a06e64f8..c5781b39b34 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/MAC_REG_8822Bmp.txt @@ -1,136 +1,136 @@ -0x29 0xF9 -0x420 0x80 //en_rty_break -0x421 0x0f //en_rty_break -0x428 0x0a -0x429 0x10 -0x430 0x00 //Data auto rate fall back table -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 //RTS auto rate fall back -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 //auto rate fall back 0 1ss 2ss -0x445 0xF0 -0x446 0x01 -0x447 0xFE -0x448 0x00 -0x449 0x00 -0x44a 0x00 -0x44b 0x40 //VHT mode -0x44c 0x10 //auto rate fall back 1 only 1ss -0x44d 0xF0 -0x44e 0x3F -0x44f 0x00 -0x450 0x00 -0x451 0x00 -0x452 0x00 -0x453 0x40 -0x455 0x70 // 3.56ms -0x45E 0x04 //Tx Qos single-MPDU -0x49C 0x10 // ARFR4 for VHT 3SS -0x49D 0xF0 -0x49E 0x00 -0x49F 0x06 -0x4A0 0xE0 -0x4A1 0x03 -0x4A2 0x00 -0x4A3 0x40 -0x4A4 0x15 // ARFR5 for HT 3SS -0x4A5 0xF0 -0x4A6 0x00 -0x4A7 0x06 -0x4A8 0xE0 -0x4A9 0x00 -0x4AA 0x00 -0x4AB 0x00 -0x7DA 0x08 // For MAC Rx Hang -0x1448 0x06 -0x144a 0x06 -0x144c 0x06 -0x144e 0x06 -0x4c8 0xff -0x4c9 0x08 -0x4ca 0x2A -0x4cb 0x2A -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x4cf 0x08 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x521 0x2f //disable sifs break to impove TP -0x525 0x4f -0x551 0x10 -0x559 0x02 -0x55c 0x50 // For MAC clock 80MHz -0x55d 0xff -0x577 0x0b //diable 2nd CCA 20M/40M and freerun counter enable bit -0x5BE 0x64 //When 0x5BE = 0x4 TxOp length locked 4ms -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x01 //rx_length from Lsig -0x608 0x0e -0x609 0x22 -0x60C 0x18 // max rx limit 512byte unit -0x6a0 0xff -0x6a1 0xff -0x6a2 0xff -0x6a3 0xff -0x6a4 0xff -0x6a5 0xff -0x6de 0x84 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 // For MAC clock 80MHz -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 -0x7D4 0x10 //L-SIG length +0x29 0xF9 +0x420 0x80 //en_rty_break +0x421 0x0f //en_rty_break +0x428 0x0a +0x429 0x10 +0x430 0x00 //Data auto rate fall back table +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 //RTS auto rate fall back +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 //auto rate fall back 0 1ss 2ss +0x445 0xF0 +0x446 0x01 +0x447 0xFE +0x448 0x00 +0x449 0x00 +0x44a 0x00 +0x44b 0x40 //VHT mode +0x44c 0x10 //auto rate fall back 1 only 1ss +0x44d 0xF0 +0x44e 0x3F +0x44f 0x00 +0x450 0x00 +0x451 0x00 +0x452 0x00 +0x453 0x40 +0x455 0x70 // 3.56ms +0x45E 0x04 //Tx Qos single-MPDU +0x49C 0x10 // ARFR4 for VHT 3SS +0x49D 0xF0 +0x49E 0x00 +0x49F 0x06 +0x4A0 0xE0 +0x4A1 0x03 +0x4A2 0x00 +0x4A3 0x40 +0x4A4 0x15 // ARFR5 for HT 3SS +0x4A5 0xF0 +0x4A6 0x00 +0x4A7 0x06 +0x4A8 0xE0 +0x4A9 0x00 +0x4AA 0x00 +0x4AB 0x00 +0x7DA 0x08 // For MAC Rx Hang +0x1448 0x06 +0x144a 0x06 +0x144c 0x06 +0x144e 0x06 +0x4c8 0xff +0x4c9 0x08 +0x4ca 0x2A +0x4cb 0x2A +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x4cf 0x08 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x521 0x2f //disable sifs break to impove TP +0x525 0x4f +0x551 0x10 +0x559 0x02 +0x55c 0x50 // For MAC clock 80MHz +0x55d 0xff +0x577 0x0b //diable 2nd CCA 20M/40M and freerun counter enable bit +0x5BE 0x64 //When 0x5BE = 0x4 TxOp length locked 4ms +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x01 //rx_length from Lsig +0x608 0x0e +0x609 0x22 +0x60C 0x18 // max rx limit 512byte unit +0x6a0 0xff +0x6a1 0xff +0x6a2 0xff +0x6a3 0xff +0x6a4 0xff +0x6a5 0xff +0x6de 0x84 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 // For MAC clock 80MHz +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 +0x7D4 0x10 //L-SIG length 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B.txt old mode 100755 new mode 100644 index 00cea3c0827..ea89240ba15 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B.txt @@ -1,960 +1,960 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57759178 -0x830 0xb79cea8B -0x834 0x0400c486 -0x838 0x87aa4330 -0x83c 0x4799477a -0x840 0x137780e0 -0x844 0x45bcfcde -0x848 0x5cd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x00015204 -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40c4e0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80024d69 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000100 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4a0000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x06510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00798079 -0xc6c 0x00794079 -0xc70 0x80794079 -0xc74 0x80794079 -0xc78 0x80798079 -0xc7c 0x00798079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x010000dd // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x00798079 -0xe6c 0x00794079 -0xe70 0x80794079 -0xe74 0x80794079 -0xe78 0x80798079 -0xe7c 0x00798079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x010000dd // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x00798079 -0x186c 0x00794079 -0x1870 0x80794079 -0x1874 0x80794079 -0x1878 0x80798079 -0x187c 0x00798079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x010000dd // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x00798079 -0x1a6c 0x00794079 -0x1a70 0x80794079 -0x1a74 0x80794079 -0x1a78 0x80798079 -0x1a7c 0x00798079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x010000dd //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x1914 0x00030000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe2461690 -0x1b10 0x00000d46 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x00080005 -0x1b80 0x00080007 -0x1b80 0x80000015 -0x1b80 0x80000017 -0x1b80 0x00040025 -0x1b80 0x00040027 -0x1b80 0x4a000035 -0x1b80 0x4a000037 -0x1b80 0x4b040045 -0x1b80 0x4b040047 -0x1b80 0x85030055 -0x1b80 0x85030057 -0x1b80 0x40010065 -0x1b80 0x40010067 -0x1b80 0xe01b0075 -0x1b80 0xe01b0077 -0x1b80 0x00040085 -0x1b80 0x00040087 -0x1b80 0x4b050095 -0x1b80 0x4b050097 -0x1b80 0x860300a5 -0x1b80 0x860300a7 -0x1b80 0x400300b5 -0x1b80 0x400300b7 -0x1b80 0xe01b00c5 -0x1b80 0xe01b00c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x4b0600e5 -0x1b80 0x4b0600e7 -0x1b80 0x870300f5 -0x1b80 0x870300f7 -0x1b80 0x40050105 -0x1b80 0x40050107 -0x1b80 0xe01b0115 -0x1b80 0xe01b0117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4b070135 -0x1b80 0x4b070137 -0x1b80 0x88030145 -0x1b80 0x88030147 -0x1b80 0x40070155 -0x1b80 0x40070157 -0x1b80 0xe01b0165 -0x1b80 0xe01b0167 -0x1b80 0x4b000175 -0x1b80 0x4b000177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x40000195 -0x1b80 0x40000197 -0x1b80 0x300001a5 -0x1b80 0x300001a7 -0x1b80 0xf00a01b5 -0x1b80 0xf00a01b7 -0x1b80 0xf10a01c5 -0x1b80 0xf10a01c7 -0x1b80 0xf20a01d5 -0x1b80 0xf20a01d7 -0x1b80 0xf30a01e5 -0x1b80 0xf30a01e7 -0x1b80 0xf40a01f5 -0x1b80 0xf40a01f7 -0x1b80 0xf50a0205 -0x1b80 0xf50a0207 -0x1b80 0xf60a0215 -0x1b80 0xf60a0217 -0x1b80 0xfe0a0225 -0x1b80 0xfe0a0227 -0x1b80 0xff0a0235 -0x1b80 0xff0a0237 -0x1b80 0x00010245 -0x1b80 0x00010247 -0x1b80 0x302e0255 -0x1b80 0x302e0257 -0x1b80 0x30340265 -0x1b80 0x30340267 -0x1b80 0x303a0275 -0x1b80 0x303a0277 -0x1b80 0x30500285 -0x1b80 0x30500287 -0x1b80 0x303a0295 -0x1b80 0x303a0297 -0x1b80 0x303402a5 -0x1b80 0x303402a7 -0x1b80 0x303a02b5 -0x1b80 0x303a02b7 -0x1b80 0x30d002c5 -0x1b80 0x30d002c7 -0x1b80 0x30b302d5 -0x1b80 0x30b302d7 -0x1b80 0xe06602e5 -0x1b80 0xe06602e7 -0x1b80 0x580002f5 -0x1b80 0x580002f7 -0x1b80 0x5c720305 -0x1b80 0x5c720307 -0x1b80 0x63400315 -0x1b80 0x63400317 -0x1b80 0xe0750325 -0x1b80 0xe0750327 -0x1b80 0x00010335 -0x1b80 0x00010337 -0x1b80 0xe0660345 -0x1b80 0xe0660347 -0x1b80 0x5c720355 -0x1b80 0x5c720357 -0x1b80 0x63400365 -0x1b80 0x63400367 -0x1b80 0x0ba60375 -0x1b80 0x0ba60377 -0x1b80 0xe0790385 -0x1b80 0xe0790387 -0x1b80 0x00010395 -0x1b80 0x00010397 -0x1b80 0xe06603a5 -0x1b80 0xe06603a7 -0x1b80 0x580303b5 -0x1b80 0x580303b7 -0x1b80 0x5cf103c5 -0x1b80 0x5cf103c7 -0x1b80 0x4d0403d5 -0x1b80 0x4d0403d7 -0x1b80 0x000703e5 -0x1b80 0x000703e7 -0x1b80 0x640203f5 -0x1b80 0x640203f7 -0x1b80 0x2ef80405 -0x1b80 0x2ef80407 -0x1b80 0x00020415 -0x1b80 0x00020417 -0x1b80 0x23030425 -0x1b80 0x23030427 -0x1b80 0x00000435 -0x1b80 0x00000437 -0x1b80 0x23130445 -0x1b80 0x23130447 -0x1b80 0xe77f0455 -0x1b80 0xe77f0457 -0x1b80 0x232f0465 -0x1b80 0x232f0467 -0x1b80 0xe79f0475 -0x1b80 0xe79f0477 -0x1b80 0x2ef00485 -0x1b80 0x2ef00487 -0x1b80 0x00020495 -0x1b80 0x00020497 -0x1b80 0x640004a5 -0x1b80 0x640004a7 -0x1b80 0x000404b5 -0x1b80 0x000404b7 -0x1b80 0x4d0004c5 -0x1b80 0x4d0004c7 -0x1b80 0x0ba604d5 -0x1b80 0x0ba604d7 -0x1b80 0xe08304e5 -0x1b80 0xe08304e7 -0x1b80 0x000104f5 -0x1b80 0x000104f7 -0x1b80 0xe0660505 -0x1b80 0xe0660507 -0x1b80 0x5c720515 -0x1b80 0x5c720517 -0x1b80 0x4d040525 -0x1b80 0x4d040527 -0x1b80 0x00070535 -0x1b80 0x00070537 -0x1b80 0x64020545 -0x1b80 0x64020547 -0x1b80 0x2ef80555 -0x1b80 0x2ef80557 -0x1b80 0x00020565 -0x1b80 0x00020567 -0x1b80 0x23030575 -0x1b80 0x23030577 -0x1b80 0x00000585 -0x1b80 0x00000587 -0x1b80 0x23130595 -0x1b80 0x23130597 -0x1b80 0xe77f05a5 -0x1b80 0xe77f05a7 -0x1b80 0x232f05b5 -0x1b80 0x232f05b7 -0x1b80 0xe93f05c5 -0x1b80 0xe93f05c7 -0x1b80 0x2ef005d5 -0x1b80 0x2ef005d7 -0x1b80 0x000205e5 -0x1b80 0x000205e7 -0x1b80 0x640005f5 -0x1b80 0x640005f7 -0x1b80 0x00040605 -0x1b80 0x00040607 -0x1b80 0x4d000615 -0x1b80 0x4d000617 -0x1b80 0x63600625 -0x1b80 0x63600627 -0x1b80 0x0ba60635 -0x1b80 0x0ba60637 -0x1b80 0xe0790645 -0x1b80 0xe0790647 -0x1b80 0x00010655 -0x1b80 0x00010657 -0x1b80 0x00070665 -0x1b80 0x00070667 -0x1b80 0x54010675 -0x1b80 0x54010677 -0x1b80 0x00040685 -0x1b80 0x00040687 -0x1b80 0x7b200695 -0x1b80 0x7b200697 -0x1b80 0x7a0006a5 -0x1b80 0x7a0006a7 -0x1b80 0x790006b5 -0x1b80 0x790006b7 -0x1b80 0x7f2006c5 -0x1b80 0x7f2006c7 -0x1b80 0x7e0006d5 -0x1b80 0x7e0006d7 -0x1b80 0x7d0006e5 -0x1b80 0x7d0006e7 -0x1b80 0x090106f5 -0x1b80 0x090106f7 -0x1b80 0x0c010705 -0x1b80 0x0c010707 -0x1b80 0x0d020715 -0x1b80 0x0d020717 -0x1b80 0x0e040725 -0x1b80 0x0e040727 -0x1b80 0x0f080735 -0x1b80 0x0f080737 -0x1b80 0x00010745 -0x1b80 0x00010747 -0x1b80 0x74010755 -0x1b80 0x74010757 -0x1b80 0x74000765 -0x1b80 0x74000767 -0x1b80 0x8e000775 -0x1b80 0x8e000777 -0x1b80 0x00010785 -0x1b80 0x00010787 -0x1b80 0xe08c0795 -0x1b80 0xe08c0797 -0x1b80 0x548007a5 -0x1b80 0x548007a7 -0x1b80 0x580107b5 -0x1b80 0x580107b7 -0x1b80 0xe08c07c5 -0x1b80 0xe08c07c7 -0x1b80 0x548107d5 -0x1b80 0x548107d7 -0x1b80 0xe08c07e5 -0x1b80 0xe08c07e7 -0x1b80 0x548207f5 -0x1b80 0x548207f7 -0x1b80 0xe09e0805 -0x1b80 0xe09e0807 -0x1b80 0x07140815 -0x1b80 0x07140817 -0x1b80 0x00010825 -0x1b80 0x00010827 -0x1b80 0xe0950835 -0x1b80 0xe0950837 -0x1b80 0x54800845 -0x1b80 0x54800847 -0x1b80 0xe0950855 -0x1b80 0xe0950857 -0x1b80 0x54810865 -0x1b80 0x54810867 -0x1b80 0xe0950875 -0x1b80 0xe0950877 -0x1b80 0x54820885 -0x1b80 0x54820887 -0x1b80 0xe09e0895 -0x1b80 0xe09e0897 -0x1b80 0x071408a5 -0x1b80 0x071408a7 -0x1b80 0x000108b5 -0x1b80 0x000108b7 -0x1b80 0x002a08c5 -0x1b80 0x002a08c7 -0x1b80 0x740108d5 -0x1b80 0x740108d7 -0x1b80 0x740008e5 -0x1b80 0x740008e7 -0x1b80 0x8e0008f5 -0x1b80 0x8e0008f7 -0x1b80 0x30930905 -0x1b80 0x30930907 -0x1b80 0x00020915 -0x1b80 0x00020917 -0x1b80 0x30180925 -0x1b80 0x30180927 -0x1b80 0x050a0935 -0x1b80 0x050a0937 -0x1b80 0x00010945 -0x1b80 0x00010947 -0x1b80 0x002a0955 -0x1b80 0x002a0957 -0x1b80 0x74010965 -0x1b80 0x74010967 -0x1b80 0x74000975 -0x1b80 0x74000977 -0x1b80 0x8e000985 -0x1b80 0x8e000987 -0x1b80 0x309c0995 -0x1b80 0x309c0997 -0x1b80 0x000209a5 -0x1b80 0x000209a7 -0x1b80 0x301809b5 -0x1b80 0x301809b7 -0x1b80 0x050a09c5 -0x1b80 0x050a09c7 -0x1b80 0x000109d5 -0x1b80 0x000109d7 -0x1b80 0x54c009e5 -0x1b80 0x54c009e7 -0x1b80 0x54a309f5 -0x1b80 0x54a309f7 -0x1b80 0x54c10a05 -0x1b80 0x54c10a07 -0x1b80 0x54a40a15 -0x1b80 0x54a40a17 -0x1b80 0x4c830a25 -0x1b80 0x4c830a27 -0x1b80 0x4c030a35 -0x1b80 0x4c030a37 -0x1b80 0xbf0c0a45 -0x1b80 0xbf0c0a47 -0x1b80 0x54c20a55 -0x1b80 0x54c20a57 -0x1b80 0x54a40a65 -0x1b80 0x54a40a67 -0x1b80 0x4c850a75 -0x1b80 0x4c850a77 -0x1b80 0x4c050a85 -0x1b80 0x4c050a87 -0x1b80 0xbf070a95 -0x1b80 0xbf070a97 -0x1b80 0x54c10aa5 -0x1b80 0x54c10aa7 -0x1b80 0x54a30ab5 -0x1b80 0x54a30ab7 -0x1b80 0x4c860ac5 -0x1b80 0x4c860ac7 -0x1b80 0x4c060ad5 -0x1b80 0x4c060ad7 -0x1b80 0xbf020ae5 -0x1b80 0xbf020ae7 -0x1b80 0x30180af5 -0x1b80 0x30180af7 -0x1b80 0x54e50b05 -0x1b80 0x54e50b07 -0x1b80 0x050a0b15 -0x1b80 0x050a0b17 -0x1b80 0x00010b25 -0x1b80 0x00010b27 -0x1b80 0x00070b35 -0x1b80 0x00070b37 -0x1b80 0x64020b45 -0x1b80 0x64020b47 -0x1b80 0x00040b55 -0x1b80 0x00040b57 -0x1b80 0x6bc00b65 -0x1b80 0x6bc00b67 -0x1b80 0x68a00b75 -0x1b80 0x68a00b77 -0x1b80 0x67600b85 -0x1b80 0x67600b87 -0x1b80 0x66800b95 -0x1b80 0x66800b97 -0x1b80 0x65700ba5 -0x1b80 0x65700ba7 -0x1b80 0x4d040bb5 -0x1b80 0x4d040bb7 -0x1b80 0x23410bc5 -0x1b80 0x23410bc7 -0x1b80 0x01e40bd5 -0x1b80 0x01e40bd7 -0x1b80 0x23410be5 -0x1b80 0x23410be7 -0x1b80 0x11e60bf5 -0x1b80 0x11e60bf7 -0x1b80 0x23410c05 -0x1b80 0x23410c07 -0x1b80 0x21e80c15 -0x1b80 0x21e80c17 -0x1b80 0x23410c25 -0x1b80 0x23410c27 -0x1b80 0x31ea0c35 -0x1b80 0x31ea0c37 -0x1b80 0x23410c45 -0x1b80 0x23410c47 -0x1b80 0x40210c55 -0x1b80 0x40210c57 -0x1b80 0x23410c65 -0x1b80 0x23410c67 -0x1b80 0x50610c75 -0x1b80 0x50610c77 -0x1b80 0x23410c85 -0x1b80 0x23410c87 -0x1b80 0x60e10c95 -0x1b80 0x60e10c97 -0x1b80 0x23410ca5 -0x1b80 0x23410ca7 -0x1b80 0x70210cb5 -0x1b80 0x70210cb7 -0x1b80 0x4d000cc5 -0x1b80 0x4d000cc7 -0x1b80 0x00070cd5 -0x1b80 0x00070cd7 -0x1b80 0x64000ce5 -0x1b80 0x64000ce7 -0x1b80 0x00010cf5 -0x1b80 0x00010cf7 -0x1b80 0x00070d05 -0x1b80 0x00070d07 -0x1b80 0x64020d15 -0x1b80 0x64020d17 -0x1b80 0x00040d25 -0x1b80 0x00040d27 -0x1b80 0x6b400d35 -0x1b80 0x6b400d37 -0x1b80 0x68a00d45 -0x1b80 0x68a00d47 -0x1b80 0x67600d55 -0x1b80 0x67600d57 -0x1b80 0x66c00d65 -0x1b80 0x66c00d67 -0x1b80 0x65700d75 -0x1b80 0x65700d77 -0x1b80 0x4d040d85 -0x1b80 0x4d040d87 -0x1b80 0x23410d95 -0x1b80 0x23410d97 -0x1b80 0x01e30da5 -0x1b80 0x01e30da7 -0x1b80 0x23410db5 -0x1b80 0x23410db7 -0x1b80 0x11e40dc5 -0x1b80 0x11e40dc7 -0x1b80 0x23410dd5 -0x1b80 0x23410dd7 -0x1b80 0x21e50de5 -0x1b80 0x21e50de7 -0x1b80 0x23410df5 -0x1b80 0x23410df7 -0x1b80 0x31e60e05 -0x1b80 0x31e60e07 -0x1b80 0x23410e15 -0x1b80 0x23410e17 -0x1b80 0x40010e25 -0x1b80 0x40010e27 -0x1b80 0x23410e35 -0x1b80 0x23410e37 -0x1b80 0x50210e45 -0x1b80 0x50210e47 -0x1b80 0x23410e55 -0x1b80 0x23410e57 -0x1b80 0x60410e65 -0x1b80 0x60410e67 -0x1b80 0x23410e75 -0x1b80 0x23410e77 -0x1b80 0x71010e85 -0x1b80 0x71010e87 -0x1b80 0x4d000e95 -0x1b80 0x4d000e97 -0x1b80 0x00070ea5 -0x1b80 0x00070ea7 -0x1b80 0x64000eb5 -0x1b80 0x64000eb7 -0x1b80 0x00010ec5 -0x1b80 0x00010ec7 -0x1b80 0x00000006 -0x1b80 0x00000002 - +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57759178 +0x830 0xb79cea8B +0x834 0x0400c486 +0x838 0x87aa4330 +0x83c 0x4799477a +0x840 0x137780e0 +0x844 0x45bcfcde +0x848 0x5cd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x00015204 +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40c4e0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80024d69 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000100 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4a0000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x06510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00798079 +0xc6c 0x00794079 +0xc70 0x80794079 +0xc74 0x80794079 +0xc78 0x80798079 +0xc7c 0x00798079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x010000dd // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x00798079 +0xe6c 0x00794079 +0xe70 0x80794079 +0xe74 0x80794079 +0xe78 0x80798079 +0xe7c 0x00798079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x010000dd // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x00798079 +0x186c 0x00794079 +0x1870 0x80794079 +0x1874 0x80794079 +0x1878 0x80798079 +0x187c 0x00798079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x010000dd // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x00798079 +0x1a6c 0x00794079 +0x1a70 0x80794079 +0x1a74 0x80794079 +0x1a78 0x80798079 +0x1a7c 0x00798079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x010000dd //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x1914 0x00030000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe2461690 +0x1b10 0x00000d46 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x00080005 +0x1b80 0x00080007 +0x1b80 0x80000015 +0x1b80 0x80000017 +0x1b80 0x00040025 +0x1b80 0x00040027 +0x1b80 0x4a000035 +0x1b80 0x4a000037 +0x1b80 0x4b040045 +0x1b80 0x4b040047 +0x1b80 0x85030055 +0x1b80 0x85030057 +0x1b80 0x40010065 +0x1b80 0x40010067 +0x1b80 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mode 100644 index 00cea3c0827..ea89240ba15 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822B_hp.txt @@ -1,960 +1,960 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x08011280 -0x808 0x0e0282ff // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57759178 -0x830 0xb79cea8B -0x834 0x0400c486 -0x838 0x87aa4330 -0x83c 0x4799477a -0x840 0x137780e0 -0x844 0x45bcfcde -0x848 0x5cd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x00015204 -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x44444444 // s_factor_QAM_ML -0x874 0x31612c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf40c4e0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x3ff00020 -0x8c4 0x44c00000 -0x8c8 0x80024d69 -0x8cc 0x08250492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x4a092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000100 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x4a0000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x06510080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -0xb0c 0x31eaa006 // [29:28]=2b11 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x41cfffff -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3c020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00798079 -0xc6c 0x00794079 -0xc70 0x80794079 -0xc74 0x80794079 -0xc78 0x80798079 -0xc7c 0x00798079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x010000dd // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002929 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3c000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x00798079 -0xe6c 0x00794079 -0xe70 0x80794079 -0xe74 0x80794079 -0xe78 0x80798079 -0xe7c 0x00798079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x010000dd // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002929 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3c000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x00798079 -0x186c 0x00794079 -0x1870 0x80794079 -0x1874 0x80794079 -0x1878 0x80798079 -0x187c 0x00798079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x010000dd // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002929 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3c000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x00798079 -0x1a6c 0x00794079 -0x1a70 0x80794079 -0x1a74 0x80794079 -0x1a78 0x80798079 -0x1a7c 0x00798079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x010000dd //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002929 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x1914 0x00030000 -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML -//======================= -// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 - -//======================= -// IQK com init -//======================= -0x1b04 0xe2461690 -0x1b10 0x00000d46 -0x1b18 0x00292903 - -// Path A init -// IQK diff init -0x1b00 0xf8000000 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path B init -// IQK diff init -0x1b00 0xf8000002 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60802070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path C init -// IQK diff init -0x1b00 0xf8000004 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -// Path D init -// IQK diff init -0x1b00 0xf8000006 -0x1b1c 0xa2127c72 -0x1b20 0x40323070 -0x1b24 0x60804070 -0x1b28 0xc0060300 -0x1b2c 0x20000003 -0x1b30 0x20000000 -0x1b38 0x20000000 -0x1b3c 0x20000000 - -// Enable normal path IQC -0x1b94 0x80000000 -0x1b34 0x00000000 -0x1b34 0x00000002 -0x1b34 0x00000000 - -//================== -// NCTL Initial -//================== -0x1b00 0xf8000000 -0x1b80 0x00000007 -0x1b80 0x00080005 -0x1b80 0x00080007 -0x1b80 0x80000015 -0x1b80 0x80000017 -0x1b80 0x00040025 -0x1b80 0x00040027 -0x1b80 0x4a000035 -0x1b80 0x4a000037 -0x1b80 0x4b040045 -0x1b80 0x4b040047 -0x1b80 0x85030055 -0x1b80 0x85030057 -0x1b80 0x40010065 -0x1b80 0x40010067 -0x1b80 0xe01b0075 -0x1b80 0xe01b0077 -0x1b80 0x00040085 -0x1b80 0x00040087 -0x1b80 0x4b050095 -0x1b80 0x4b050097 -0x1b80 0x860300a5 -0x1b80 0x860300a7 -0x1b80 0x400300b5 -0x1b80 0x400300b7 -0x1b80 0xe01b00c5 -0x1b80 0xe01b00c7 -0x1b80 0x000400d5 -0x1b80 0x000400d7 -0x1b80 0x4b0600e5 -0x1b80 0x4b0600e7 -0x1b80 0x870300f5 -0x1b80 0x870300f7 -0x1b80 0x40050105 -0x1b80 0x40050107 -0x1b80 0xe01b0115 -0x1b80 0xe01b0117 -0x1b80 0x00040125 -0x1b80 0x00040127 -0x1b80 0x4b070135 -0x1b80 0x4b070137 -0x1b80 0x88030145 -0x1b80 0x88030147 -0x1b80 0x40070155 -0x1b80 0x40070157 -0x1b80 0xe01b0165 -0x1b80 0xe01b0167 -0x1b80 0x4b000175 -0x1b80 0x4b000177 -0x1b80 0x00040185 -0x1b80 0x00040187 -0x1b80 0x40000195 -0x1b80 0x40000197 -0x1b80 0x300001a5 -0x1b80 0x300001a7 -0x1b80 0xf00a01b5 -0x1b80 0xf00a01b7 -0x1b80 0xf10a01c5 -0x1b80 0xf10a01c7 -0x1b80 0xf20a01d5 -0x1b80 0xf20a01d7 -0x1b80 0xf30a01e5 -0x1b80 0xf30a01e7 -0x1b80 0xf40a01f5 -0x1b80 0xf40a01f7 -0x1b80 0xf50a0205 -0x1b80 0xf50a0207 -0x1b80 0xf60a0215 -0x1b80 0xf60a0217 -0x1b80 0xfe0a0225 -0x1b80 0xfe0a0227 -0x1b80 0xff0a0235 -0x1b80 0xff0a0237 -0x1b80 0x00010245 -0x1b80 0x00010247 -0x1b80 0x302e0255 -0x1b80 0x302e0257 -0x1b80 0x30340265 -0x1b80 0x30340267 -0x1b80 0x303a0275 -0x1b80 0x303a0277 -0x1b80 0x30500285 -0x1b80 0x30500287 -0x1b80 0x303a0295 -0x1b80 0x303a0297 -0x1b80 0x303402a5 -0x1b80 0x303402a7 -0x1b80 0x303a02b5 -0x1b80 0x303a02b7 -0x1b80 0x30d002c5 -0x1b80 0x30d002c7 -0x1b80 0x30b302d5 -0x1b80 0x30b302d7 -0x1b80 0xe06602e5 -0x1b80 0xe06602e7 -0x1b80 0x580002f5 -0x1b80 0x580002f7 -0x1b80 0x5c720305 -0x1b80 0x5c720307 -0x1b80 0x63400315 -0x1b80 0x63400317 -0x1b80 0xe0750325 -0x1b80 0xe0750327 -0x1b80 0x00010335 -0x1b80 0x00010337 -0x1b80 0xe0660345 -0x1b80 0xe0660347 -0x1b80 0x5c720355 -0x1b80 0x5c720357 -0x1b80 0x63400365 -0x1b80 0x63400367 -0x1b80 0x0ba60375 -0x1b80 0x0ba60377 -0x1b80 0xe0790385 -0x1b80 0xe0790387 -0x1b80 0x00010395 -0x1b80 0x00010397 -0x1b80 0xe06603a5 -0x1b80 0xe06603a7 -0x1b80 0x580303b5 -0x1b80 0x580303b7 -0x1b80 0x5cf103c5 -0x1b80 0x5cf103c7 -0x1b80 0x4d0403d5 -0x1b80 0x4d0403d7 -0x1b80 0x000703e5 -0x1b80 0x000703e7 -0x1b80 0x640203f5 -0x1b80 0x640203f7 -0x1b80 0x2ef80405 -0x1b80 0x2ef80407 -0x1b80 0x00020415 -0x1b80 0x00020417 -0x1b80 0x23030425 -0x1b80 0x23030427 -0x1b80 0x00000435 -0x1b80 0x00000437 -0x1b80 0x23130445 -0x1b80 0x23130447 -0x1b80 0xe77f0455 -0x1b80 0xe77f0457 -0x1b80 0x232f0465 -0x1b80 0x232f0467 -0x1b80 0xe79f0475 -0x1b80 0xe79f0477 -0x1b80 0x2ef00485 -0x1b80 0x2ef00487 -0x1b80 0x00020495 -0x1b80 0x00020497 -0x1b80 0x640004a5 -0x1b80 0x640004a7 -0x1b80 0x000404b5 -0x1b80 0x000404b7 -0x1b80 0x4d0004c5 -0x1b80 0x4d0004c7 -0x1b80 0x0ba604d5 -0x1b80 0x0ba604d7 -0x1b80 0xe08304e5 -0x1b80 0xe08304e7 -0x1b80 0x000104f5 -0x1b80 0x000104f7 -0x1b80 0xe0660505 -0x1b80 0xe0660507 -0x1b80 0x5c720515 -0x1b80 0x5c720517 -0x1b80 0x4d040525 -0x1b80 0x4d040527 -0x1b80 0x00070535 -0x1b80 0x00070537 -0x1b80 0x64020545 -0x1b80 0x64020547 -0x1b80 0x2ef80555 -0x1b80 0x2ef80557 -0x1b80 0x00020565 -0x1b80 0x00020567 -0x1b80 0x23030575 -0x1b80 0x23030577 -0x1b80 0x00000585 -0x1b80 0x00000587 -0x1b80 0x23130595 -0x1b80 0x23130597 -0x1b80 0xe77f05a5 -0x1b80 0xe77f05a7 -0x1b80 0x232f05b5 -0x1b80 0x232f05b7 -0x1b80 0xe93f05c5 -0x1b80 0xe93f05c7 -0x1b80 0x2ef005d5 -0x1b80 0x2ef005d7 -0x1b80 0x000205e5 -0x1b80 0x000205e7 -0x1b80 0x640005f5 -0x1b80 0x640005f7 -0x1b80 0x00040605 -0x1b80 0x00040607 -0x1b80 0x4d000615 -0x1b80 0x4d000617 -0x1b80 0x63600625 -0x1b80 0x63600627 -0x1b80 0x0ba60635 -0x1b80 0x0ba60637 -0x1b80 0xe0790645 -0x1b80 0xe0790647 -0x1b80 0x00010655 -0x1b80 0x00010657 -0x1b80 0x00070665 -0x1b80 0x00070667 -0x1b80 0x54010675 -0x1b80 0x54010677 -0x1b80 0x00040685 -0x1b80 0x00040687 -0x1b80 0x7b200695 -0x1b80 0x7b200697 -0x1b80 0x7a0006a5 -0x1b80 0x7a0006a7 -0x1b80 0x790006b5 -0x1b80 0x790006b7 -0x1b80 0x7f2006c5 -0x1b80 0x7f2006c7 -0x1b80 0x7e0006d5 -0x1b80 0x7e0006d7 -0x1b80 0x7d0006e5 -0x1b80 0x7d0006e7 -0x1b80 0x090106f5 -0x1b80 0x090106f7 -0x1b80 0x0c010705 -0x1b80 0x0c010707 -0x1b80 0x0d020715 -0x1b80 0x0d020717 -0x1b80 0x0e040725 -0x1b80 0x0e040727 -0x1b80 0x0f080735 -0x1b80 0x0f080737 -0x1b80 0x00010745 -0x1b80 0x00010747 -0x1b80 0x74010755 -0x1b80 0x74010757 -0x1b80 0x74000765 -0x1b80 0x74000767 -0x1b80 0x8e000775 -0x1b80 0x8e000777 -0x1b80 0x00010785 -0x1b80 0x00010787 -0x1b80 0xe08c0795 -0x1b80 0xe08c0797 -0x1b80 0x548007a5 -0x1b80 0x548007a7 -0x1b80 0x580107b5 -0x1b80 0x580107b7 -0x1b80 0xe08c07c5 -0x1b80 0xe08c07c7 -0x1b80 0x548107d5 -0x1b80 0x548107d7 -0x1b80 0xe08c07e5 -0x1b80 0xe08c07e7 -0x1b80 0x548207f5 -0x1b80 0x548207f7 -0x1b80 0xe09e0805 -0x1b80 0xe09e0807 -0x1b80 0x07140815 -0x1b80 0x07140817 -0x1b80 0x00010825 -0x1b80 0x00010827 -0x1b80 0xe0950835 -0x1b80 0xe0950837 -0x1b80 0x54800845 -0x1b80 0x54800847 -0x1b80 0xe0950855 -0x1b80 0xe0950857 -0x1b80 0x54810865 -0x1b80 0x54810867 -0x1b80 0xe0950875 -0x1b80 0xe0950877 -0x1b80 0x54820885 -0x1b80 0x54820887 -0x1b80 0xe09e0895 -0x1b80 0xe09e0897 -0x1b80 0x071408a5 -0x1b80 0x071408a7 -0x1b80 0x000108b5 -0x1b80 0x000108b7 -0x1b80 0x002a08c5 -0x1b80 0x002a08c7 -0x1b80 0x740108d5 -0x1b80 0x740108d7 -0x1b80 0x740008e5 -0x1b80 0x740008e7 -0x1b80 0x8e0008f5 -0x1b80 0x8e0008f7 -0x1b80 0x30930905 -0x1b80 0x30930907 -0x1b80 0x00020915 -0x1b80 0x00020917 -0x1b80 0x30180925 -0x1b80 0x30180927 -0x1b80 0x050a0935 -0x1b80 0x050a0937 -0x1b80 0x00010945 -0x1b80 0x00010947 -0x1b80 0x002a0955 -0x1b80 0x002a0957 -0x1b80 0x74010965 -0x1b80 0x74010967 -0x1b80 0x74000975 -0x1b80 0x74000977 -0x1b80 0x8e000985 -0x1b80 0x8e000987 -0x1b80 0x309c0995 -0x1b80 0x309c0997 -0x1b80 0x000209a5 -0x1b80 0x000209a7 -0x1b80 0x301809b5 -0x1b80 0x301809b7 -0x1b80 0x050a09c5 -0x1b80 0x050a09c7 -0x1b80 0x000109d5 -0x1b80 0x000109d7 -0x1b80 0x54c009e5 -0x1b80 0x54c009e7 -0x1b80 0x54a309f5 -0x1b80 0x54a309f7 -0x1b80 0x54c10a05 -0x1b80 0x54c10a07 -0x1b80 0x54a40a15 -0x1b80 0x54a40a17 -0x1b80 0x4c830a25 -0x1b80 0x4c830a27 -0x1b80 0x4c030a35 -0x1b80 0x4c030a37 -0x1b80 0xbf0c0a45 -0x1b80 0xbf0c0a47 -0x1b80 0x54c20a55 -0x1b80 0x54c20a57 -0x1b80 0x54a40a65 -0x1b80 0x54a40a67 -0x1b80 0x4c850a75 -0x1b80 0x4c850a77 -0x1b80 0x4c050a85 -0x1b80 0x4c050a87 -0x1b80 0xbf070a95 -0x1b80 0xbf070a97 -0x1b80 0x54c10aa5 -0x1b80 0x54c10aa7 -0x1b80 0x54a30ab5 -0x1b80 0x54a30ab7 -0x1b80 0x4c860ac5 -0x1b80 0x4c860ac7 -0x1b80 0x4c060ad5 -0x1b80 0x4c060ad7 -0x1b80 0xbf020ae5 -0x1b80 0xbf020ae7 -0x1b80 0x30180af5 -0x1b80 0x30180af7 -0x1b80 0x54e50b05 -0x1b80 0x54e50b07 -0x1b80 0x050a0b15 -0x1b80 0x050a0b17 -0x1b80 0x00010b25 -0x1b80 0x00010b27 -0x1b80 0x00070b35 -0x1b80 0x00070b37 -0x1b80 0x64020b45 -0x1b80 0x64020b47 -0x1b80 0x00040b55 -0x1b80 0x00040b57 -0x1b80 0x6bc00b65 -0x1b80 0x6bc00b67 -0x1b80 0x68a00b75 -0x1b80 0x68a00b77 -0x1b80 0x67600b85 -0x1b80 0x67600b87 -0x1b80 0x66800b95 -0x1b80 0x66800b97 -0x1b80 0x65700ba5 -0x1b80 0x65700ba7 -0x1b80 0x4d040bb5 -0x1b80 0x4d040bb7 -0x1b80 0x23410bc5 -0x1b80 0x23410bc7 -0x1b80 0x01e40bd5 -0x1b80 0x01e40bd7 -0x1b80 0x23410be5 -0x1b80 0x23410be7 -0x1b80 0x11e60bf5 -0x1b80 0x11e60bf7 -0x1b80 0x23410c05 -0x1b80 0x23410c07 -0x1b80 0x21e80c15 -0x1b80 0x21e80c17 -0x1b80 0x23410c25 -0x1b80 0x23410c27 -0x1b80 0x31ea0c35 -0x1b80 0x31ea0c37 -0x1b80 0x23410c45 -0x1b80 0x23410c47 -0x1b80 0x40210c55 -0x1b80 0x40210c57 -0x1b80 0x23410c65 -0x1b80 0x23410c67 -0x1b80 0x50610c75 -0x1b80 0x50610c77 -0x1b80 0x23410c85 -0x1b80 0x23410c87 -0x1b80 0x60e10c95 -0x1b80 0x60e10c97 -0x1b80 0x23410ca5 -0x1b80 0x23410ca7 -0x1b80 0x70210cb5 -0x1b80 0x70210cb7 -0x1b80 0x4d000cc5 -0x1b80 0x4d000cc7 -0x1b80 0x00070cd5 -0x1b80 0x00070cd7 -0x1b80 0x64000ce5 -0x1b80 0x64000ce7 -0x1b80 0x00010cf5 -0x1b80 0x00010cf7 -0x1b80 0x00070d05 -0x1b80 0x00070d07 -0x1b80 0x64020d15 -0x1b80 0x64020d17 -0x1b80 0x00040d25 -0x1b80 0x00040d27 -0x1b80 0x6b400d35 -0x1b80 0x6b400d37 -0x1b80 0x68a00d45 -0x1b80 0x68a00d47 -0x1b80 0x67600d55 -0x1b80 0x67600d57 -0x1b80 0x66c00d65 -0x1b80 0x66c00d67 -0x1b80 0x65700d75 -0x1b80 0x65700d77 -0x1b80 0x4d040d85 -0x1b80 0x4d040d87 -0x1b80 0x23410d95 -0x1b80 0x23410d97 -0x1b80 0x01e30da5 -0x1b80 0x01e30da7 -0x1b80 0x23410db5 -0x1b80 0x23410db7 -0x1b80 0x11e40dc5 -0x1b80 0x11e40dc7 -0x1b80 0x23410dd5 -0x1b80 0x23410dd7 -0x1b80 0x21e50de5 -0x1b80 0x21e50de7 -0x1b80 0x23410df5 -0x1b80 0x23410df7 -0x1b80 0x31e60e05 -0x1b80 0x31e60e07 -0x1b80 0x23410e15 -0x1b80 0x23410e17 -0x1b80 0x40010e25 -0x1b80 0x40010e27 -0x1b80 0x23410e35 -0x1b80 0x23410e37 -0x1b80 0x50210e45 -0x1b80 0x50210e47 -0x1b80 0x23410e55 -0x1b80 0x23410e57 -0x1b80 0x60410e65 -0x1b80 0x60410e67 -0x1b80 0x23410e75 -0x1b80 0x23410e77 -0x1b80 0x71010e85 -0x1b80 0x71010e87 -0x1b80 0x4d000e95 -0x1b80 0x4d000e97 -0x1b80 0x00070ea5 -0x1b80 0x00070ea7 -0x1b80 0x64000eb5 -0x1b80 0x64000eb7 -0x1b80 0x00010ec5 -0x1b80 0x00010ec7 -0x1b80 0x00000006 -0x1b80 0x00000002 - +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x08011280 +0x808 0x0e0282ff // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57759178 +0x830 0xb79cea8B +0x834 0x0400c486 +0x838 0x87aa4330 +0x83c 0x4799477a +0x840 0x137780e0 +0x844 0x45bcfcde +0x848 0x5cd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x00015204 +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x44444444 // s_factor_QAM_ML +0x874 0x31612c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf40c4e0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x3ff00020 +0x8c4 0x44c00000 +0x8c8 0x80024d69 +0x8cc 0x08250492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x4a092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000100 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x4a0000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x06510080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +0xb0c 0x31eaa006 // [29:28]=2b11 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x41cfffff +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3c020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00798079 +0xc6c 0x00794079 +0xc70 0x80794079 +0xc74 0x80794079 +0xc78 0x80798079 +0xc7c 0x00798079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x010000dd // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002929 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3c000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x00798079 +0xe6c 0x00794079 +0xe70 0x80794079 +0xe74 0x80794079 +0xe78 0x80798079 +0xe7c 0x00798079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x010000dd // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002929 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3c000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x00798079 +0x186c 0x00794079 +0x1870 0x80794079 +0x1874 0x80794079 +0x1878 0x80798079 +0x187c 0x00798079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x010000dd // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002929 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3c000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x00798079 +0x1a6c 0x00794079 +0x1a70 0x80794079 +0x1a74 0x80794079 +0x1a78 0x80798079 +0x1a7c 0x00798079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x010000dd //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002929 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x1914 0x00030000 +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_a // The setting of Page_A should be delayed since it needs 5us after ck320M is started +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff800c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 + +//======================= +// IQK com init +//======================= +0x1b04 0xe2461690 +0x1b10 0x00000d46 +0x1b18 0x00292903 + +// Path A init +// IQK diff init +0x1b00 0xf8000000 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path B init +// IQK diff init +0x1b00 0xf8000002 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60802070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path C init +// IQK diff init +0x1b00 0xf8000004 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +// Path D init +// IQK diff init +0x1b00 0xf8000006 +0x1b1c 0xa2127c72 +0x1b20 0x40323070 +0x1b24 0x60804070 +0x1b28 0xc0060300 +0x1b2c 0x20000003 +0x1b30 0x20000000 +0x1b38 0x20000000 +0x1b3c 0x20000000 + +// Enable normal path IQC +0x1b94 0x80000000 +0x1b34 0x00000000 +0x1b34 0x00000002 +0x1b34 0x00000000 + +//================== +// NCTL Initial +//================== +0x1b00 0xf8000000 +0x1b80 0x00000007 +0x1b80 0x00080005 +0x1b80 0x00080007 +0x1b80 0x80000015 +0x1b80 0x80000017 +0x1b80 0x00040025 +0x1b80 0x00040027 +0x1b80 0x4a000035 +0x1b80 0x4a000037 +0x1b80 0x4b040045 +0x1b80 0x4b040047 +0x1b80 0x85030055 +0x1b80 0x85030057 +0x1b80 0x40010065 +0x1b80 0x40010067 +0x1b80 0xe01b0075 +0x1b80 0xe01b0077 +0x1b80 0x00040085 +0x1b80 0x00040087 +0x1b80 0x4b050095 +0x1b80 0x4b050097 +0x1b80 0x860300a5 +0x1b80 0x860300a7 +0x1b80 0x400300b5 +0x1b80 0x400300b7 +0x1b80 0xe01b00c5 +0x1b80 0xe01b00c7 +0x1b80 0x000400d5 +0x1b80 0x000400d7 +0x1b80 0x4b0600e5 +0x1b80 0x4b0600e7 +0x1b80 0x870300f5 +0x1b80 0x870300f7 +0x1b80 0x40050105 +0x1b80 0x40050107 +0x1b80 0xe01b0115 +0x1b80 0xe01b0117 +0x1b80 0x00040125 +0x1b80 0x00040127 +0x1b80 0x4b070135 +0x1b80 0x4b070137 +0x1b80 0x88030145 +0x1b80 0x88030147 +0x1b80 0x40070155 +0x1b80 0x40070157 +0x1b80 0xe01b0165 +0x1b80 0xe01b0167 +0x1b80 0x4b000175 +0x1b80 0x4b000177 +0x1b80 0x00040185 +0x1b80 0x00040187 +0x1b80 0x40000195 +0x1b80 0x40000197 +0x1b80 0x300001a5 +0x1b80 0x300001a7 +0x1b80 0xf00a01b5 +0x1b80 0xf00a01b7 +0x1b80 0xf10a01c5 +0x1b80 0xf10a01c7 +0x1b80 0xf20a01d5 +0x1b80 0xf20a01d7 +0x1b80 0xf30a01e5 +0x1b80 0xf30a01e7 +0x1b80 0xf40a01f5 +0x1b80 0xf40a01f7 +0x1b80 0xf50a0205 +0x1b80 0xf50a0207 +0x1b80 0xf60a0215 +0x1b80 0xf60a0217 +0x1b80 0xfe0a0225 +0x1b80 0xfe0a0227 +0x1b80 0xff0a0235 +0x1b80 0xff0a0237 +0x1b80 0x00010245 +0x1b80 0x00010247 +0x1b80 0x302e0255 +0x1b80 0x302e0257 +0x1b80 0x30340265 +0x1b80 0x30340267 +0x1b80 0x303a0275 +0x1b80 0x303a0277 +0x1b80 0x30500285 +0x1b80 0x30500287 +0x1b80 0x303a0295 +0x1b80 0x303a0297 +0x1b80 0x303402a5 +0x1b80 0x303402a7 +0x1b80 0x303a02b5 +0x1b80 0x303a02b7 +0x1b80 0x30d002c5 +0x1b80 0x30d002c7 +0x1b80 0x30b302d5 +0x1b80 0x30b302d7 +0x1b80 0xe06602e5 +0x1b80 0xe06602e7 +0x1b80 0x580002f5 +0x1b80 0x580002f7 +0x1b80 0x5c720305 +0x1b80 0x5c720307 +0x1b80 0x63400315 +0x1b80 0x63400317 +0x1b80 0xe0750325 +0x1b80 0xe0750327 +0x1b80 0x00010335 +0x1b80 0x00010337 +0x1b80 0xe0660345 +0x1b80 0xe0660347 +0x1b80 0x5c720355 +0x1b80 0x5c720357 +0x1b80 0x63400365 +0x1b80 0x63400367 +0x1b80 0x0ba60375 +0x1b80 0x0ba60377 +0x1b80 0xe0790385 +0x1b80 0xe0790387 +0x1b80 0x00010395 +0x1b80 0x00010397 +0x1b80 0xe06603a5 +0x1b80 0xe06603a7 +0x1b80 0x580303b5 +0x1b80 0x580303b7 +0x1b80 0x5cf103c5 +0x1b80 0x5cf103c7 +0x1b80 0x4d0403d5 +0x1b80 0x4d0403d7 +0x1b80 0x000703e5 +0x1b80 0x000703e7 +0x1b80 0x640203f5 +0x1b80 0x640203f7 +0x1b80 0x2ef80405 +0x1b80 0x2ef80407 +0x1b80 0x00020415 +0x1b80 0x00020417 +0x1b80 0x23030425 +0x1b80 0x23030427 +0x1b80 0x00000435 +0x1b80 0x00000437 +0x1b80 0x23130445 +0x1b80 0x23130447 +0x1b80 0xe77f0455 +0x1b80 0xe77f0457 +0x1b80 0x232f0465 +0x1b80 0x232f0467 +0x1b80 0xe79f0475 +0x1b80 0xe79f0477 +0x1b80 0x2ef00485 +0x1b80 0x2ef00487 +0x1b80 0x00020495 +0x1b80 0x00020497 +0x1b80 0x640004a5 +0x1b80 0x640004a7 +0x1b80 0x000404b5 +0x1b80 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0x4d000e95 +0x1b80 0x4d000e97 +0x1b80 0x00070ea5 +0x1b80 0x00070ea7 +0x1b80 0x64000eb5 +0x1b80 0x64000eb7 +0x1b80 0x00010ec5 +0x1b80 0x00010ec7 +0x1b80 0x00000006 +0x1b80 0x00000002 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp.txt old mode 100755 new mode 100644 index 88bfc15586e..9a3714d4b66 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp.txt @@ -1,397 +1,397 @@ -//======================= -// PAGE_8 -//======================= -0x800 0x9020d010 -0x804 0x080112e0 -0x808 0x0e028277 // cck_en=0 ofdm_en=0 -0x80c 0x00000077 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x57757178 -0x830 0xa79cea8B -0x834 0x0400c485 -0x838 0x87aa4330 -0x83c 0x479747b9 -0x840 0x037750e0 -0x844 0x45bcfcde -0x848 0x5bd07f8b -0x84c 0x6cfdffb5 -0x850 0x28876706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74210368 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x438c2878 -0x870 0x04444444 -0x874 0x31612c2e -0x878 0x00003153 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202013e -0x8ac 0xf00f000a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057ff -0x8bc 0x8ca520c3 -0x8c0 0x27f00020 -0x8c4 0x48c00000 -0x8c8 0x80024569 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8dc 0x00000000 -0x8e0 0x32316400 -0x8e4 0x49092925 -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00f80fa1 //modified by Jason -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -//0x914 0x06000404 //ADC-backoff for MP chip -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x480000e4 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008400 -0x93c 0x001c0642 -0x940 0x02470430 -0x950 0x02010080 -0x954 0x07fd0080 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 //0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 //0x30000000 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x000002d5 //0x000002d4 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x801f8c00 -//======================= -// PAGE_b -//======================= -//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 -0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification -//0xb08 0xae0201eb -//0xb0c 0x01eaa006 -//0xb10 0x0000ee70 -//0xb14 0x0060000d -//0xb18 0x00000002 -//0xb1c 0x00000002 -//0xb20 0xa800001f -//0xb24 0x4e660300 -//0xb28 0x03020100 -//0xb2c 0x07060504 -//0xb30 0x0b0a0908 -//0xb34 0x0f0e0d0c -//0xb38 0x13121110 -//0xb3c 0x0000003a -//0xb40 0x00000000 -//0xb44 0x00000000 -//0xb48 0x13000032 -//0xb4c 0x48080000 -//0xb50 0x00000000 -//0xb54 0x00000000 -//0xb58 0x00000000 -0xb5c 0x00100000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000043 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0x3e020c14 //0x30020c1c -0xc5c 0x00000058 -0xc60 0x34347473 -0xc64 0x07003333 -0xc68 0x00794079 -0xc6c 0x00798079 -0xc70 0x80798079 -0xc74 0x40798079 -0xc78 0x40794079 -0xc7c 0x00794079 -0xc80 0x00790079 -0xc84 0x00790079 -0xc94 0x0100025c // for testchip TXDFIR -0xc98 0x00088000 -//0xc9c 0x00000000 -0xca0 0x00002915 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x54775477 -0xcb4 0x54775477 -0xcb8 0x00500000 -0xcbc 0x07700000 -0xcc0 0x00000010 -0xcc8 0x00000010 -0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000043 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0x3e000c14 //0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x80794079 -0xe6c 0x80798079 -0xe70 0x80798079 -0xe74 0x40798079 -0xe78 0x40794079 -0xe7c 0x00794079 -0xe80 0x00790079 -0xe84 0x00790079 -0xe94 0x0100025c // for testchip TXDFIR -0xe98 0x00088000 -//0xe9c 0x00000000 -0xea0 0x00002915 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x54775477 -0xeb4 0x54775477 -0xeb8 0x00500000 -0xebc 0x07700000 -0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_18 : Path_C setting -//======================= -//0x1800 0x00000003 // RF: RLE442C/D format with SI -0x1800 0x00000007 // RF: RLE442C/D format with PI -//0x1800 0x00040003 // RF: z2 format -0x1804 0x00042020 -0x1808 0x80410231 // RF: RLE442C format -//0x1808 0x80410121 // RF: z2 format -0x180c 0x00000000 -//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C -0x1810 0x00000100 // RF: RX IQ is correct -0x1814 0x01000000 // RF: RX IQ is correct -0x181c 0x40000043 -0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1850 0x00000020 -0x1854 0x00000000 -0x1858 0x3e000c14 //0x30020c1c -0x185c 0x00000058 -0x1860 0x34344443 -0x1864 0x07003333 -0x1868 0x80794079 -0x186c 0x80798079 -0x1870 0x80798079 -0x1874 0x40798079 -0x1878 0x40794079 -0x187c 0x00794079 -0x1880 0x00790079 -0x1884 0x00790079 -0x1894 0x0100025c // for testchip TXDFIR -0x1898 0x00088000 -//0x189c 0x00000000 -0x18a0 0x00002915 // TRSW mapping table -0x18a4 0x08040201 -0x18a8 0x80402010 -0x18ac 0x00000000 -0x18b0 0x54775477 -0x18b4 0x54775477 -0x18b8 0x00500000 -0x18bc 0x07700000 -0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_1a : Path_D setting -//======================= -//0x1a00 0x00000003 // RF: RLE442C/D format with SI -0x1a00 0x00000007 // RF: RLE442C/D format with PI -//0x1a00 0x00040003 // RF: z2 format -0x1a04 0x00042020 -0x1a08 0x80410231 // RF: RLE442C format -//0x1a08 0x80410121 // RF: z2 format -0x1a0c 0x00000000 -//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C -//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C -0x1a10 0x00000100 // RF: RX IQ is correct -0x1a14 0x01000000 // RF: RX IQ is correct -0x1a1c 0x40000043 -0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0x1a50 0x00000020 -0x1a54 0x00000000 -0x1a58 0x3e000c14 //0x30020c1c -0x1a5c 0x00000058 -0x1a60 0x34344443 -0x1a64 0x07003333 -0x1a68 0x80794079 -0x1a6c 0x80798079 -0x1a70 0x80798079 -0x1a74 0x40798079 -0x1a78 0x40794079 -0x1a7c 0x00794079 -0x1a80 0x00790079 -0x1a84 0x00790079 -0x1a94 0x0100025c //for testchip TXDFIR -0x1a98 0x00088000 -//0x1a9c 0x00000000 -0x1aa0 0x00002915 // TRSW mapping table -0x1aa4 0x08040201 -0x1aa8 0x80402010 -0x1aac 0x00000000 -0x1ab0 0x54775477 -0x1ab4 0x54775477 -0x1ab8 0x00500000 -0x1abc 0x07700000 -0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} -//======================= -// PAGE_19 : common setting -//======================= -0x198c 0x00000007 // dbg clk gat -0x1990 0xffaa5500 -0x1994 0x00000077 -0x19d4 0x88888888 // s_factor_QAM_ML -0x19d8 0x00000888 // s_factor_QAM_ML +//======================= +// PAGE_8 +//======================= +0x800 0x9020d010 +0x804 0x080112e0 +0x808 0x0e028277 // cck_en=0 ofdm_en=0 +0x80c 0x00000077 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x57757178 +0x830 0xa79cea8B +0x834 0x0400c485 +0x838 0x87aa4330 +0x83c 0x479747b9 +0x840 0x037750e0 +0x844 0x45bcfcde +0x848 0x5bd07f8b +0x84c 0x6cfdffb5 +0x850 0x28876706 +0x854 0x0001520c +0x858 0x4060c000 +0x85c 0x74210368 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x438c2878 +0x870 0x04444444 +0x874 0x31612c2e +0x878 0x00003153 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202013e +0x8ac 0xf00f000a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0xec0057ff +0x8bc 0x8ca520c3 +0x8c0 0x27f00020 +0x8c4 0x48c00000 +0x8c8 0x80024569 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8dc 0x00000000 +0x8e0 0x32316400 +0x8e4 0x49092925 +0x8e8 0xffffc42c +0x8ec 0x99999999 +0x8f0 0x00009999 +0x8f4 0x00f80fa1 //modified by Jason +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +//0x914 0x06000404 //ADC-backoff for MP chip +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x480000e4 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x938 0x00008400 +0x93c 0x001c0642 +0x940 0x02470430 +0x950 0x02010080 +0x954 0x07fd0080 +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 //0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 //0x30000000 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x000002d5 //0x000002d4 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x81ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x801f8c00 +//======================= +// PAGE_b +//======================= +//0xb00 0xe3100100 // PMC mode 0xb00[8]=1 +0xb00 0xe3100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +// the following marked reg are needed to be set to specificed value for PMAC allplication in ASIC verification +//0xb08 0xae0201eb +//0xb0c 0x01eaa006 +//0xb10 0x0000ee70 +//0xb14 0x0060000d +//0xb18 0x00000002 +//0xb1c 0x00000002 +//0xb20 0xa800001f +//0xb24 0x4e660300 +//0xb28 0x03020100 +//0xb2c 0x07060504 +//0xb30 0x0b0a0908 +//0xb34 0x0f0e0d0c +//0xb38 0x13121110 +//0xb3c 0x0000003a +//0xb40 0x00000000 +//0xb44 0x00000000 +//0xb48 0x13000032 +//0xb4c 0x48080000 +//0xb50 0x00000000 +//0xb54 0x00000000 +//0xb58 0x00000000 +0xb5c 0x00100000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000043 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x00000000 +0xc58 0x3e020c14 //0x30020c1c +0xc5c 0x00000058 +0xc60 0x34347473 +0xc64 0x07003333 +0xc68 0x00794079 +0xc6c 0x00798079 +0xc70 0x80798079 +0xc74 0x40798079 +0xc78 0x40794079 +0xc7c 0x00794079 +0xc80 0x00790079 +0xc84 0x00790079 +0xc94 0x0100025c // for testchip TXDFIR +0xc98 0x00088000 +//0xc9c 0x00000000 +0xca0 0x00002915 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcac 0x00000000 +0xcb0 0x54775477 +0xcb4 0x54775477 +0xcb8 0x00500000 +0xcbc 0x07700000 +0xcc0 0x00000010 +0xcc8 0x00000010 +0xcd8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xcdc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xce0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xce4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xce8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000043 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x00000000 +0xe58 0x3e000c14 //0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x80794079 +0xe6c 0x80798079 +0xe70 0x80798079 +0xe74 0x40798079 +0xe78 0x40794079 +0xe7c 0x00794079 +0xe80 0x00790079 +0xe84 0x00790079 +0xe94 0x0100025c // for testchip TXDFIR +0xe98 0x00088000 +//0xe9c 0x00000000 +0xea0 0x00002915 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeac 0x00000000 +0xeb0 0x54775477 +0xeb4 0x54775477 +0xeb8 0x00500000 +0xebc 0x07700000 +0xed8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0xedc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0xee0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0xee4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0xee8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_18 : Path_C setting +//======================= +//0x1800 0x00000003 // RF: RLE442C/D format with SI +0x1800 0x00000007 // RF: RLE442C/D format with PI +//0x1800 0x00040003 // RF: z2 format +0x1804 0x00042020 +0x1808 0x80410231 // RF: RLE442C format +//0x1808 0x80410121 // RF: z2 format +0x180c 0x00000000 +//0x1810 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1814 0x00000100 // RF: RX IQ is switched for RLE442C +0x1810 0x00000100 // RF: RX IQ is correct +0x1814 0x01000000 // RF: RX IQ is correct +0x181c 0x40000043 +0x1820 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1824 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1828 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x182c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1830 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1834 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1838 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x183c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1840 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1844 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1848 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x184c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1850 0x00000020 +0x1854 0x00000000 +0x1858 0x3e000c14 //0x30020c1c +0x185c 0x00000058 +0x1860 0x34344443 +0x1864 0x07003333 +0x1868 0x80794079 +0x186c 0x80798079 +0x1870 0x80798079 +0x1874 0x40798079 +0x1878 0x40794079 +0x187c 0x00794079 +0x1880 0x00790079 +0x1884 0x00790079 +0x1894 0x0100025c // for testchip TXDFIR +0x1898 0x00088000 +//0x189c 0x00000000 +0x18a0 0x00002915 // TRSW mapping table +0x18a4 0x08040201 +0x18a8 0x80402010 +0x18ac 0x00000000 +0x18b0 0x54775477 +0x18b4 0x54775477 +0x18b8 0x00500000 +0x18bc 0x07700000 +0x18d8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x18dc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x18e0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x18e4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x18e8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_1a : Path_D setting +//======================= +//0x1a00 0x00000003 // RF: RLE442C/D format with SI +0x1a00 0x00000007 // RF: RLE442C/D format with PI +//0x1a00 0x00040003 // RF: z2 format +0x1a04 0x00042020 +0x1a08 0x80410231 // RF: RLE442C format +//0x1a08 0x80410121 // RF: z2 format +0x1a0c 0x00000000 +//0x1a10 0x01000000 // RF: RX IQ is switched for RLE442C +//0x1a14 0x00000100 // RF: RX IQ is switched for RLE442C +0x1a10 0x00000100 // RF: RX IQ is correct +0x1a14 0x01000000 // RF: RX IQ is correct +0x1a1c 0x40000043 +0x1a20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0x1a24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0x1a28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x1a2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x1a30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x1a34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x1a38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0x1a3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0x1a40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0x1a44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0x1a48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0x1a4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0x1a50 0x00000020 +0x1a54 0x00000000 +0x1a58 0x3e000c14 //0x30020c1c +0x1a5c 0x00000058 +0x1a60 0x34344443 +0x1a64 0x07003333 +0x1a68 0x80794079 +0x1a6c 0x80798079 +0x1a70 0x80798079 +0x1a74 0x40798079 +0x1a78 0x40794079 +0x1a7c 0x00794079 +0x1a80 0x00790079 +0x1a84 0x00790079 +0x1a94 0x0100025c //for testchip TXDFIR +0x1a98 0x00088000 +//0x1a9c 0x00000000 +0x1aa0 0x00002915 // TRSW mapping table +0x1aa4 0x08040201 +0x1aa8 0x80402010 +0x1aac 0x00000000 +0x1ab0 0x54775477 +0x1ab4 0x54775477 +0x1ab8 0x00500000 +0x1abc 0x07700000 +0x1ad8 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +0x1adc 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +0x1ae0 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +0x1ae4 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +0x1ae8 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{NA NA MCS9 MCS8} +//======================= +// PAGE_19 : common setting +//======================= +0x198c 0x00000007 // dbg clk gat +0x1990 0xffaa5500 +0x1994 0x00000077 +0x19d4 0x88888888 // s_factor_QAM_ML +0x19d8 0x00000888 // s_factor_QAM_ML 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp_hp.txt old mode 100755 new mode 100644 index 4619a8fb4ce..fab099ee609 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_8822Bmp_hp.txt @@ -1,1302 +1,1302 @@ -//======================= -// Page_8 -//======================= -0x800 0x9020d010 -0x804 0x800181a0 -0x808 0x0e028233 -0x80c 0x10000013 -0x810 0x21101263 -0x814 0x020c3d10 -0x818 0x84a10385 -0x81c 0x1e1e081f -0x820 0x0001aaaa -0x824 0x00030fe0 -0x828 0x0000cccc -0x82c 0x75cb7010 -0x830 0x79a0ea2a -0x834 0x072E6986 -0x838 0x87766441 -0x83c 0x9194b2b6 -0x840 0x171740E0 -0x844 0x4d3d7cdb -0x848 0x4ad0408b -0x84c 0x6afbf7a5 -0x850 0x28A74706 -0x854 0x0001520c -0x858 0x4060c000 -0x85c 0x74010360 -0x860 0x68a7c321 -0x864 0x79f27432 -0x868 0x8ca7a314 -0x86c 0x778c2878 -0x870 0x77777777 -0x874 0x27612c2e -0x878 0xc0003152 -0x87c 0x5c8fc000 -0x880 0x00000000 -0x884 0x00000000 -0x888 0x00000000 -0x88c 0x00000000 -0x890 0x00000000 -0x894 0x00000000 -0x898 0x00000000 -0x89c 0x00000000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0x2202033e -0x8ac 0xf00f000a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0xec0057f7 -0x8bc 0xacb520a3 -0x8c0 0xffe04020 -0x8c4 0x47c00000 -0x8c8 0x000251a5 -0x8cc 0x08108000 -0x8d0 0x0000b800 -0x8d4 0x860308a0 -0x8d8 0x210b5612 -0x8dc 0x00000000 -0x8e0 0x32d16777 -0x8e4 0x4909292d -0x8e8 0xffffc42c -0x8ec 0x99999999 -0x8f0 0x00009999 -0x8f4 0x00d80fa1 -0x8f8 0x400000c0 -0x8fc 0x00000130 -//======================= -// Page_9 -//======================= -0x900 0x00800000 -0x904 0x00000000 -0x908 0x00000000 -0x90c 0xd3000000 -0x910 0x0000fc00 -0x914 0xc6380000 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055a2500 -0x928 0x4ab0e4e4 -0x92c 0xfffeb200 -0x930 0xfffffffe -0x934 0x001fffff -0x938 0x00008480 -0x93c 0xe41c0642 -0x940 0x0e470430 -0x944 0x00000000 -0x948 0xac000000 -0x94c 0x10000083 -0x950 0x32010080 -0x954 0x84510080 -0x958 0x00000001 -0x95c 0x04248000 -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x00001fff -0x974 0x44000fff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x98c 0x23440000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x80000088 -0x9a8 0x0c2f0000 -0x9ac 0x01560000 -0x9b0 0x70000000 -0x9b4 0x00000000 -0x9b8 0x00000000 -0x9bc 0x00000000 -0x9c0 0x00000000 -0x9c4 0x00000000 -0x9c8 0x00000000 -0x9cc 0x00000000 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e0 0x00000000 -0x9e4 0x02000402 -0x9e8 0x000022d4 -0x9ec 0x00000000 -0x9f0 0x00000000 -0x9f4 0x00000000 -0x9f8 0x00000000 -0x9fc 0xeffff7f7 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x81ff800c -0xa08 0x8c838300 -0xa0c 0x2e20100f -0xa10 0x9500bb78 -0xa14 0x1114d028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x84880000 -0xa24 0x384f6577 -0xa28 0x00001525 -0xa2c 0x00920000 -0xa70 0x101FFF00 -0xa74 0x00000148 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218275b2 -0xa84 0x80208c00 -0xa88 0x040c0000 -0xa8c 0x12345678 -0xa90 0xabcdef00 -0xa94 0x001b1b89 -0xa98 0x030a0000 -0xa9c 0x00060000 -0xaa0 0x00000000 -0xaa4 0x00040018 -//======================= -// PAGE_b -//======================= -0xb00 0xE1000440 -0xb04 0x00800000 -0xb08 0xff02030b -0xb0c 0x01eaa406 -0xb10 0x00030690 -0xb14 0x006000fa -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x4b00001f -0xb24 0x4e8e3e40 -0xb28 0x03020100 -0xb2c 0x07060504 -0xb30 0x0b0a0908 -0xb34 0x0f0e0d0c -0xb38 0x13121110 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x80000000 -0xb48 0x3f0000fa -0xb4c 0x88c80020 -0xb50 0x00000000 -0xb54 0x00004241 -0xb58 0xe0008208 -0xb5c 0x41effff9 -0xb60 0x00000000 -0xb64 0x00200063 -0xb68 0x0000003a -0xb6c 0x00000102 -0xb70 0x4e6d1870 -0xb74 0x03020100 -0xb78 0x07060504 -0xb7c 0x0b0a0908 -0xb80 0x0f0e0d0c -0xb84 0x13121110 -0xb88 0x00000000 -0xb8c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -0xc00 0x00000007 -0xc04 0x00000020 -0xc08 0x60403231 -0xc0c 0x00012345 -0xc10 0x00000100 -0xc14 0x01000000 -0xc18 0x00000000 -0xc1c 0x40040053 -0xc20 0x00020103 -0xc24 0x00000000 -0xc28 0x00000000 -0xc2c 0x00000000 -0xc30 0x00000000 -0xc34 0x00000000 -0xc38 0x00000000 -0xc3c 0x00000000 -0xc40 0x00000000 -0xc44 0x00000000 -0xc48 0x00000000 -0xc4c 0x00000000 -0xc50 0x00000020 -0xc54 0x00000000 -0xc58 0xd8020402 -0xc5c 0xde000120 -0xc68 0x59799979 -0xc6c 0x0000122a -0xc70 0x99795979 -0xc74 0x99795979 -0xc78 0x99799979 -0xc7c 0x99791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc88 0x00000000 -0xc8c 0x07000000 -0xc94 0x01000100 -0xc98 0x201c8000 -0xc9c 0x00000000 -0xca0 0x0000a555 -0xca4 0x08040201 -0xca8 0x80402010 -0xcac 0x00000000 -0xcb0 0x98543210 -0xcb4 0x000000ba -0xcb8 0x00000000 -0xcbc 0x00000000 -0xcc0 0x00000000 -0xcc4 0x00000000 -0xcc8 0x00000000 -0xccc 0x00000000 -0xcd0 0x00000000 -0xcd4 0x00000000 -0xcd8 0x00000000 -0xcdc 0x00000000 -0xce0 0x00000000 -0xce4 0x00000000 -0xce8 0x00000000 -0xcec 0x00000000 -//======================= -// PAGE_E : Path_B setting -//======================= -0xe00 0x00000007 -0xe04 0x00000020 -0xe08 0x60403231 -0xe0c 0x00012345 -0xe10 0x00000100 -0xe14 0x01000000 -0xe18 0x00000000 -0xe1c 0x40040053 -0xe20 0x00020103 -0xe24 0x00000000 -0xe28 0x00000000 -0xe2c 0x00000000 -0xe30 0x00000000 -0xe34 0x00000000 -0xe38 0x00000000 -0xe3c 0x00000000 -0xe40 0x00000000 -0xe44 0x00000000 -0xe48 0x00000000 -0xe4c 0x00000000 -0xe50 0x00000020 -0xe54 0x00000000 -0xe58 0xd8020402 -0xe5c 0xde000120 -0xe68 0x59799979 -0xe6c 0x0000122a -0xe70 0x99795979 -0xe74 0x99795979 -0xe78 0x99799979 -0xe7c 0x99791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe88 0x00000000 -0xe8c 0x07000000 -0xe94 0x01000100 -0xe98 0x201c8000 -0xe9c 0x00000000 -0xea0 0x0000a555 -0xea4 0x08040201 -0xea8 0x80402010 -0xeac 0x00000000 -0xeb0 0x98543210 -0xeb4 0x000000ba -0xeb8 0x00000000 -0xebc 0x00000000 -0xec0 0x00000000 -0xec4 0x00000000 -0xec8 0x00000000 -0xecc 0x00000000 -0xed0 0x00000000 -0xed4 0x00000000 -0xed8 0x00000000 -0xedc 0x00000000 -0xee0 0x00000000 -0xee4 0x00000000 -0xee8 0x00000000 -0xeec 0x00000000 -//======================= -// PAGE_19 : Path_19 setting -//======================= -0x1900 0x00000000 -0x1904 0x00238000 -0x1908 0x00000000 -0x190c 0x00000000 -0x1910 0x00000000 -0x1914 0x00000000 -0x1918 0x00000000 -0x191c 0x00000000 -0x1920 0x00000000 -0x1924 0x00000000 -0x1928 0x00000000 -0x192c 0x00000000 -0x1930 0x00000000 -0x1934 0x00000000 -0x1938 0x00000000 -0x193c 0x00000000 -0x1940 0x00000000 -0x1944 0x00000000 -0x1948 0x00000000 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a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822B.txt old mode 100755 new mode 100644 index fb8c01185f0..499a79de33d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822B.txt @@ -1,2 +1,2 @@ -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822Bmp.txt old mode 100755 new mode 100644 index f5b24049b44..348729c2056 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_MP_8822Bmp.txt @@ -1,3 +1,3 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -0x8fc 0x00000000 // dummy setting for driver from header -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +0x8fc 0x00000000 // dummy setting for driver from header +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822B.txt old mode 100755 new mode 100644 index d1aefc673da..17aa2a002f5 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822B.txt @@ -1,110 +1,110 @@ -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp.txt old mode 100755 new mode 100644 index 5d3ce20a1d6..bafcc5b418b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type0.txt old mode 100755 new mode 100644 index 45311266f20..efc799b25dd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type0.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type1.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type1.txt index 74e5f65cabe..5bd9af8dd6f 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type1.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type1.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type10.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type10.txt index 45311266f20..efc799b25dd 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type10.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type10.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type11.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type11.txt old mode 100755 new mode 100644 index e5b0b6266ac..72aed3c6e8b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type11.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type11.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type13.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type13.txt old mode 100755 new mode 100644 index 7132c928c45..96e00d697d8 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type13.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type13.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type14.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type14.txt old mode 100755 new mode 100644 index 45311266f20..efc799b25dd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type14.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type14.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type2.txt old mode 100755 new mode 100644 index 74e5f65cabe..5bd9af8dd6f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type2.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 24 24 25 25 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 22 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 24 24 20 21 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 23 23 23 24 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 20 21 21 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 23 24 24 24 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 20 20 20 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type3.txt old mode 100755 new mode 100644 index 2405f611091..bb258598e6a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type3.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v054_20141124 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type4.txt old mode 100755 new mode 100644 index e5b0b6266ac..72aed3c6e8b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type4.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type5.txt old mode 100755 new mode 100644 index 982bdcca8ed..f2c3107104c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type5.txt @@ -1,152 +1,152 @@ -//rtl8814a version = RL6302_MAC_PHY_Parameter_v075_20150526 -//RL6302_MAC_PHY_Parameter_v054_20141124 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//rtl8814a version = RL6302_MAC_PHY_Parameter_v075_20150526 +//RL6302_MAC_PHY_Parameter_v054_20141124 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 24 24 24 24 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 20 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 19 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 18 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 22 23 23 23 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 23 23 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 21 22 23 23 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 19 20 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 18 19 20 21 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type6.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type6.txt old mode 100755 new mode 100644 index e5b0b6266ac..72aed3c6e8b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type6.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type6.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type7.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type7.txt old mode 100755 new mode 100644 index e5b0b6266ac..72aed3c6e8b --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type7.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type7.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 19 20 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 19 19 15 15 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 17 18 18 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 16 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type8.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type8.txt old mode 100755 new mode 100644 index 7132c928c45..96e00d697d8 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type8.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type8.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 18 18 18 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 18 18 18 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 17 17 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 16 16 17 17 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 16 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 14 15 15 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 12 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type9.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type9.txt old mode 100755 new mode 100644 index 45311266f20..efc799b25dd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type9.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_Type9.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 14 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 12 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 10 11 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 15 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 13 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 16 16 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 12 13 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 15 15 15 15 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 9 10 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_hp.txt old mode 100755 new mode 100644 index cdde2565d4f..17982b08ce4 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_hp.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v054_20141124 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 19 22 22 22 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 17 18 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 21 21 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 18 21 21 21 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 19 20 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 22 22 17 18 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 20 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 22 22 22 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 19 20 20 22 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 17 18// TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_intpa.txt old mode 100755 new mode 100644 index dc6b2ac5a66..cf544875982 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/PHY_REG_PG_8822Bmp_intpa.txt @@ -1,151 +1,151 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 15 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][B]# -[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][C]# -[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[2.4G][D]# -[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][A]# -[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][B]# -[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][C]# -[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -#[5G][D]# -[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} -[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} -[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} -[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} -[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} -#[END]# -0xffff 0xffff +//RL6302_MAC_PHY_Parameter_v018_20140708 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xc20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 15 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][B]# +[1Tx] 0xe20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][C]# +[1Tx] 0x1820 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[2.4G][D]# +[1Tx] 0x1a20 0xffffffff 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][A]# +[1Tx] 0xc24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xc28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xc2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xc34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xc38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xcd8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xcdc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xc3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xc40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xc44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xc48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xc4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xce0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xce4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xce8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][B]# +[1Tx] 0xe24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0xe28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0xe34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0xe38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0xed8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0xedc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0xe3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0xe44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0xe48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0xe4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0xee0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0xee4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0xee8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][C]# +[1Tx] 0x1824 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1828 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x182c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1830 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1834 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1838 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x18d8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x18dc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x183c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1840 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1844 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1848 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x184c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x18e0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x18e4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x18e8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +#[5G][D]# +[1Tx] 0x1a24 0xffffffff 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +[1Tx] 0x1a28 0xffffffff 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0x1a2c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a30 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +[2Tx] 0x1a34 0xffffffff 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +[2Tx] 0x1a38 0xffffffff 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +[3Tx] 0x1ad8 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=HT_{MCS19 MCS18 MCS17 MCS16} +[3Tx] 0x1adc 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS23 MCS22 MCS21 MCS20} +[1Tx] 0x1a3c 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0x1a40 0xffffffff 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +[1Tx] 0x1a44 0xffffffff 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +[2Tx] 0x1a48 0xffffffff 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +[2Tx] 0x1a4c 0xffffffff 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +[3Tx] 0x1ae0 0xffffffff 18 19 20 20 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS3 MCS2 MCS1 MCS0} +[3Tx] 0x1ae4 0xffffffff 12 13 14 16 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS7 MCS6 MCS5 MCS4} +[3Tx] 0x1ae8 0x0000ffff 10 10 10 11 // TXAGC codeword (H-byte->L-byte)=VHT3SS_{MCS9 MCS8} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B.txt old mode 100755 new mode 100644 index 8fcd59c83bf..eda1cb092b1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B.txt @@ -1,324 +1,324 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C09C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C09C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B_hp.txt old mode 100755 new mode 100644 index c2f5560fc20..33b524889f1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822B_hp.txt @@ -1,322 +1,322 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C09C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C09C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp.txt old mode 100755 new mode 100644 index 91fb466413d..a8ba10c05fe --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp.txt @@ -1,321 +1,321 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -////SYN setting -0xB0 0xFFFFE -0xB1 0x3FE12 -0xB2 0x6AA3F -0xB3 0xFFC9A -0xB4 0x0279F -0xB5 0x00A3F -0xB6 0x0C05C -0xB7 0x3000C -0xB8 0x7400E -0xB9 0x08250 -0xBA 0x10000 -0xBB 0x00000 -0xBC 0x40001 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -// VCO bias -0xEF 0x20000 -0x3E 0x00000 -0x3F 0x90000 -0x3E 0x20000 -0x3F 0xA0000 -0x3E 0x40000 -0x3F 0xA0000 -0x3E 0x60000 -0x3F 0xA0000 -0xEF 0x00000 -// kvco table -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x001A0 -0x3E 0x00080 -0x3F 0x00180 -0x3E 0x00100 -0x3F 0x00120 -0x3E 0x00180 -0x3F 0x00100 -0x3E 0x00200 -0x3F 0x00100 -0x3E 0x00280 -0x3F 0x000A0 -0x3E 0x00300 -0x3F 0x00080 -0x3E 0x00380 -0x3F 0x00020 - -0xEF 0x00000 -// Ioffset -0xEF 0x40000 -0x3E 0x00030 //G mode need to check -0x3F 0x00018 -0x3E 0x00040 -0x3F 0x0000F -0x3E 0x00050 -0x3F 0x0000E -0x3E 0x00060 -0x3F 0x0000E -0xEF 0x00000 -// LPF -0xEF 0x00400 -0x3E 0x00006 -0x41 0x70100 //G mode need to check -0x3E 0x00008 -0x41 0x201C0 -0x3E 0x0000A -0x41 0x282C0 -0x3E 0x0000C -0x41 0x28340 -0xEF 0x00000 -/////////////// - - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - - - -//LCK -0x18 0x1b124 //do LCK -0xfe -0xfe -0xfe -0x18 0x13124 //set channel again +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +////SYN setting +0xB0 0xFFFFE +0xB1 0x3FE12 +0xB2 0x6AA3F +0xB3 0xFFC9A +0xB4 0x0279F +0xB5 0x00A3F +0xB6 0x0C05C +0xB7 0x3000C +0xB8 0x7400E +0xB9 0x08250 +0xBA 0x10000 +0xBB 0x00000 +0xBC 0x40001 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +// VCO bias +0xEF 0x20000 +0x3E 0x00000 +0x3F 0x90000 +0x3E 0x20000 +0x3F 0xA0000 +0x3E 0x40000 +0x3F 0xA0000 +0x3E 0x60000 +0x3F 0xA0000 +0xEF 0x00000 +// kvco table +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x001A0 +0x3E 0x00080 +0x3F 0x00180 +0x3E 0x00100 +0x3F 0x00120 +0x3E 0x00180 +0x3F 0x00100 +0x3E 0x00200 +0x3F 0x00100 +0x3E 0x00280 +0x3F 0x000A0 +0x3E 0x00300 +0x3F 0x00080 +0x3E 0x00380 +0x3F 0x00020 + +0xEF 0x00000 +// Ioffset +0xEF 0x40000 +0x3E 0x00030 //G mode need to check +0x3F 0x00018 +0x3E 0x00040 +0x3F 0x0000F +0x3E 0x00050 +0x3F 0x0000E +0x3E 0x00060 +0x3F 0x0000E +0xEF 0x00000 +// LPF +0xEF 0x00400 +0x3E 0x00006 +0x41 0x70100 //G mode need to check +0x3E 0x00008 +0x41 0x201C0 +0x3E 0x0000A +0x41 0x282C0 +0x3E 0x0000C +0x41 0x28340 +0xEF 0x00000 +/////////////// + + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + + + +//LCK +0x18 0x1b124 //do LCK +0xfe +0xfe +0xfe +0x18 0x13124 //set channel again 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp_hp.txt old mode 100755 new mode 100644 index cc152c7f2b4..ae5d5455ad9 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioA_8822Bmp_hp.txt @@ -1,440 +1,440 @@ -0x00 0x30000 // RF_mode setting -0x01 0x4002D // [4 1]=2b11 disable LTE_coextence -0x18 0x10d24 // [11:10]=2b11/10/01 for 20M/40M/80M - -//RF mode LUT -0xef 0x80000 -0x33 0x00002 //TX mode LUT -0x3e 0x0003f -0x3f 0xc0f4e -0x33 0x00001 //StandBy mode LUT -0x3e 0x00034 -0x3f 0x4080e - -//TX IQK mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0xdf 0x02449 //[11]: TX_GAIN [6]: TXA_TANK -0x33 0x00024 //[3:0]: RFMODE -0x3e 0x0003f -0x3f 0x60fde -0xef 0x00000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK - -//RxK1 mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0x33 0x00025 -0x3e 0x00037 -0x3f 0x6efce -0xef 0x00000 - -//RxK2 mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0x33 0x00026 -0x3e 0x00037 -0x3f 0x5efce -0xef 0x00000 - -//SYN Setting -0xB0 0xFF0F8 -0xB1 0x7DBE4 -0xB2 0x225D1 -0xB3 0xFC760 -0xB4 0x99DD4 // parts of channels 0xb4 0x99d44 -0xB5 0x400Fc -0xB6 0x187F0 -0xB7 0x30018 // B7[15:13] LCk time 000 min. -0xB8 0x80800 // for channel 2467M: 0xb8[19]=0 -0xB9 0x00000 -0xBA 0x08000 -0xBB 0x00000 -0xBC 0x40000 -0xBD 0x00000 -0xBE 0x00000 -0xBF 0x00000 -0xC0 0x00000 -0xC1 0x00000 -0xC2 0x00000 -0xC3 0x00000 -0xC4 0x02402 -0xC5 0x00009 -0xC6 0x40299 -0xC7 0x55555 -0xC8 0x0c16c -0xC9 0x1C140 -0xCA 0x00000 -0xCB 0x00000 -0xCC 0x00000 -0xCD 0x00000 -0xCE 0x90C00 -0xCF 0x6d200 -0xDF 0x00009 // debug mode 0x26C1B - -// End of SYN Setting - -//A mode TRx Setting - -//RX_A General Settings -0x18 0x10524 //5180MHz -0x89 0x00207 //LNA Bias[2:0]=111 -0x8A 0xFF186 //LNA tank[16:13] -0x8B 0x61E3C //LNA EN_Q[15:2] -0x8C 0x112C7 -0x8D 0xF4988 -0x8E 0x64D40 - -//RX_A AGC Table -0xEF 0x20000 //RX_A gain LUT Enable -//LB -0x33 0x00007 //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x00006 //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x00005 //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x00004 //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x00003 //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x00002 //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00001 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00000 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 - -//MB -0x33 0x0000f //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x0000e //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x0000d //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x0000c //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x0000b //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x0000a //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00009 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00008 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 - -//HB -0x33 0x00017 //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x00016 //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x00015 //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x00014 //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x00013 //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x00012 //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00011 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00010 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 -0xEF 0x00000 - -//RX_A Subband Table -0xEF 0x04000 -0x33 0x00000 //LB -0x3f 0x0000a -0x33 0x00001 //MB -0x3f 0x00005 -0x33 0x00002 //HB -0x3f 0x00000 -0xEF 0x00000 - -//RX_G General Settings -0x18 0x00401 //2412MHz -0x84 0x01209 -0x86 0x001a0 -0x87 0x68080 -0x88 0x70020 -0xde 0x00010 //RXG bias - -//RX_G AGC Table -0xEF 0x08000 //RX_G gain LUT Enable -0x33 0x0000f //CCK HG1 -0x3f 0x0003c -0x33 0x0000e //CCK HG2 -0x3f 0x00038 -0x33 0x0000d //CCK MG1 for ACPR -0x3f 0x00030 -0x33 0x0000c //CCK MG2-1 -0x3f 0x00028 -0x33 0x0000b //CCK MG3 -0x3f 0x00020 -0x33 0x0000a //CCK LG1-1 -0x3f 0x00018 -0x33 0x00009 //CCK LG2 -0x3f 0x00010 -0x33 0x00008 //CCK ULG-1 -0x3f 0x00008 -0x33 0x00007 //HG1 -0x3f 0x0003c -0x33 0x00006 //HG2 -0x3f 0x00038 -0x33 0x00005 //MG1 -0x3f 0x00030 -0x33 0x00004 //MG2-1 -0x3f 0x00028 -0x33 0x00003 //MG3 -0x3f 0x00020 -0x33 0x00002 //LG1-1 -0x3f 0x00018 -0x33 0x00001 //LG2 -0x3f 0x00010 -0x33 0x00000 //ULG-1 -0x3f 0x00008 -0xEF 0x00000 - -//VCO Current CAL (Should be done before LCK) -0xB8 0x80A00 //reference level -0xB0 0xFF0FA -0xCA 0x80000 -0xC9 0x1C141 -0xB0 0xFF0F8 - -//LCK -0x18 0x18d24 //set ch01 do LCK -0xffe -0xffe -0xffe -0xffe -0x18 0x10d24 //set 5180MHz - -//RCK -0x1B 0x75A40 //0x1B[6]=1 -0xDE 0x00012 -0x1D 0x00004 //RCK offset - - -0x61 0x0d4A4 -0x62 0x0d203 -0x63 0x00062 - -//bias1 of TXA -0xEF 0x00200 -0x30 0x004A0 -0x30 0x014A0 -0x30 0x024A0 -0x30 0x034A0 -0x30 0x044A0 -0x30 0x054A0 -0x30 0x064A0 -0x30 0x074A0 -0x30 0x084A0 -0x30 0x094A0 -0x30 0x0A4A0 -0x30 0x0B4A0 -0xEF 0x00000 -//bias1 end -//bias2 of TXA -0xEF 0x00080 -0x30 0x00203 -0x30 0x01203 -0x30 0x02203 -0x30 0x03203 -0x30 0x04203 -0x30 0x05203 -0x30 0x06203 -0x30 0x07203 -0x30 0x08203 -0x30 0x09203 -0x30 0x0A203 -0x30 0x0B203 -0xEF 0x00000 -//bias2 end -//tank -0xEF 0x00040 -0x30 0x00645 -0x30 0x01333 -0x30 0x02011 -0x30 0x04645 -0x30 0x05333 -0x30 0x06011 -0xEF 0x00000 -//tank end -// TXA Gain table -0xEF 0x00800 -//LB -0x33 0x00020 -0x3F 0x00006 -0x33 0x00021 -0x3F 0x00009 -0x33 0x00022 -0x3F 0x0000C -0x33 0x00023 -0x3F 0x00029 -0x33 0x00024 -0x3F 0x0002C -0x33 0x00025 -0x3F 0x0004B -0x33 0x00026 -0x3F 0x00448 -0x33 0x00027 -0x3F 0x0044B -0x33 0x00028 -0x3F 0x0084B -0x33 0x00029 -0x3F 0x0086B -0x33 0x0002A -0x3F 0x0086E -//MB -0x33 0x00060 -0x3F 0x00006 -0x33 0x00061 -0x3F 0x00009 -0x33 0x00062 -0x3F 0x0000C -0x33 0x00063 -0x3F 0x00029 -0x33 0x00064 -0x3F 0x0002C -0x33 0x00065 -0x3F 0x0004B -0x33 0x00066 -0x3F 0x00448 -0x33 0x00067 -0x3F 0x0044B -0x33 0x00068 -0x3F 0x0084B -0x33 0x00069 -0x3F 0x0086B -0x33 0x0006A -0x3F 0x0086E -//HB -0x33 0x000A0 -0x3F 0x00006 -0x33 0x000A1 -0x3F 0x00009 -0x33 0x000A2 -0x3F 0x0000C -0x33 0x000A3 -0x3F 0x00029 -0x33 0x000A4 -0x3F 0x0002C -0x33 0x000A5 -0x3F 0x0004B -0x33 0x000A6 -0x3F 0x00448 -0x33 0x000A7 -0x3F 0x0044B -0x33 0x000A8 -0x3F 0x0084B -0x33 0x000A9 -0x3F 0x0086B -0x33 0x000AA -0x3F 0x0086E -0xEF 0x00000 - -//TXG bias 1 -0xEF 0x00400 -0x33 0x00000 -0x3F 0x0047C -0x33 0x00001 -0x3F 0x0047C -0x33 0x00002 -0x3F 0x0047C -0x33 0x00003 -0x3F 0x0047C -0xEF 0x00000 -//TXG bias 2 -0xEF 0x00100 -0x33 0x00000 -0x3F 0x01726 -0x33 0x00001 -0x3F 0x01726 -0x33 0x00002 -0x3F 0x01726 -0x33 0x00003 -0x3F 0x01726 -0xEF 0x00000 - -//TXG EVM parameter -0x81 0xF400 -0x87 0x16040 -0x51 0x808 -0x52 0x98002 -0x53 0xFA47 -0x54 0x58032 -0x56 0x51000 -0x57 0xCE0A -0x58 0x82030 - -//TXG gain table -0xEF 0x00800 -0x33 0x00000 -0x3F 0x00003 -0x33 0x00001 -0x3F 0x00006 -0x33 0x00002 -0x3F 0x00009 -0x33 0x00003 -0x3F 0x00026 -0x33 0x00004 -0x3F 0x00029 -0x33 0x00005 -0x3F 0x0002c -0x33 0x00006 -0x3F 0x0002f -0x33 0x00007 -0x3F 0x00033 -0x33 0x00008 -0x3F 0x00036 -0x33 0x00009 -0x3F 0x00039 -0x33 0x0000a -0x3F 0x0003C -0xEF 0x00000 - -//TXLOK -0xEF 0x00010 -0x33 0x00000 -0x08 0x9C060 -0x33 0x00001 -0x08 0x9C060 -0xEF 0x00000 - -//TX mode table for TSSI: -0x33 0x000a2 -0xef 0x80000 -0x3e 0x0593f -0x3f 0xc0f4f -0xef 0x00000 -//RX mode table for TSSI: -0x33 0x000a3 -0xef 0x80000 -0x3e 0x05934 -0x3f 0x5afcf -0xef 0x00000 - +0x00 0x30000 // RF_mode setting +0x01 0x4002D // [4 1]=2b11 disable LTE_coextence +0x18 0x10d24 // [11:10]=2b11/10/01 for 20M/40M/80M + +//RF mode LUT +0xef 0x80000 +0x33 0x00002 //TX mode LUT +0x3e 0x0003f +0x3f 0xc0f4e +0x33 0x00001 //StandBy mode LUT +0x3e 0x00034 +0x3f 0x4080e + +//TX IQK mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0xdf 0x02449 //[11]: TX_GAIN [6]: TXA_TANK +0x33 0x00024 //[3:0]: RFMODE +0x3e 0x0003f +0x3f 0x60fde +0xef 0x00000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK + +//RxK1 mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0x33 0x00025 +0x3e 0x00037 +0x3f 0x6efce +0xef 0x00000 + +//RxK2 mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0x33 0x00026 +0x3e 0x00037 +0x3f 0x5efce +0xef 0x00000 + +//SYN Setting +0xB0 0xFF0F8 +0xB1 0x7DBE4 +0xB2 0x225D1 +0xB3 0xFC760 +0xB4 0x99DD4 // parts of channels 0xb4 0x99d44 +0xB5 0x400Fc +0xB6 0x187F0 +0xB7 0x30018 // B7[15:13] LCk time 000 min. +0xB8 0x80800 // for channel 2467M: 0xb8[19]=0 +0xB9 0x00000 +0xBA 0x08000 +0xBB 0x00000 +0xBC 0x40000 +0xBD 0x00000 +0xBE 0x00000 +0xBF 0x00000 +0xC0 0x00000 +0xC1 0x00000 +0xC2 0x00000 +0xC3 0x00000 +0xC4 0x02402 +0xC5 0x00009 +0xC6 0x40299 +0xC7 0x55555 +0xC8 0x0c16c +0xC9 0x1C140 +0xCA 0x00000 +0xCB 0x00000 +0xCC 0x00000 +0xCD 0x00000 +0xCE 0x90C00 +0xCF 0x6d200 +0xDF 0x00009 // debug mode 0x26C1B + +// End of SYN Setting + +//A mode TRx Setting + +//RX_A General Settings +0x18 0x10524 //5180MHz +0x89 0x00207 //LNA Bias[2:0]=111 +0x8A 0xFF186 //LNA tank[16:13] +0x8B 0x61E3C //LNA EN_Q[15:2] +0x8C 0x112C7 +0x8D 0xF4988 +0x8E 0x64D40 + +//RX_A AGC Table +0xEF 0x20000 //RX_A gain LUT Enable +//LB +0x33 0x00007 //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x00006 //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x00005 //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x00004 //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x00003 //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x00002 //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00001 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00000 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 + +//MB +0x33 0x0000f //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x0000e //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x0000d //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x0000c //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x0000b //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x0000a //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00009 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00008 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 + +//HB +0x33 0x00017 //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x00016 //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x00015 //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x00014 //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x00013 //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x00012 //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00011 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00010 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 +0xEF 0x00000 + +//RX_A Subband Table +0xEF 0x04000 +0x33 0x00000 //LB +0x3f 0x0000a +0x33 0x00001 //MB +0x3f 0x00005 +0x33 0x00002 //HB +0x3f 0x00000 +0xEF 0x00000 + +//RX_G General Settings +0x18 0x00401 //2412MHz +0x84 0x01209 +0x86 0x001a0 +0x87 0x68080 +0x88 0x70020 +0xde 0x00010 //RXG bias + +//RX_G AGC Table +0xEF 0x08000 //RX_G gain LUT Enable +0x33 0x0000f //CCK HG1 +0x3f 0x0003c +0x33 0x0000e //CCK HG2 +0x3f 0x00038 +0x33 0x0000d //CCK MG1 for ACPR +0x3f 0x00030 +0x33 0x0000c //CCK MG2-1 +0x3f 0x00028 +0x33 0x0000b //CCK MG3 +0x3f 0x00020 +0x33 0x0000a //CCK LG1-1 +0x3f 0x00018 +0x33 0x00009 //CCK LG2 +0x3f 0x00010 +0x33 0x00008 //CCK ULG-1 +0x3f 0x00008 +0x33 0x00007 //HG1 +0x3f 0x0003c +0x33 0x00006 //HG2 +0x3f 0x00038 +0x33 0x00005 //MG1 +0x3f 0x00030 +0x33 0x00004 //MG2-1 +0x3f 0x00028 +0x33 0x00003 //MG3 +0x3f 0x00020 +0x33 0x00002 //LG1-1 +0x3f 0x00018 +0x33 0x00001 //LG2 +0x3f 0x00010 +0x33 0x00000 //ULG-1 +0x3f 0x00008 +0xEF 0x00000 + +//VCO Current CAL (Should be done before LCK) +0xB8 0x80A00 //reference level +0xB0 0xFF0FA +0xCA 0x80000 +0xC9 0x1C141 +0xB0 0xFF0F8 + +//LCK +0x18 0x18d24 //set ch01 do LCK +0xffe +0xffe +0xffe +0xffe +0x18 0x10d24 //set 5180MHz + +//RCK +0x1B 0x75A40 //0x1B[6]=1 +0xDE 0x00012 +0x1D 0x00004 //RCK offset + + +0x61 0x0d4A4 +0x62 0x0d203 +0x63 0x00062 + +//bias1 of TXA +0xEF 0x00200 +0x30 0x004A0 +0x30 0x014A0 +0x30 0x024A0 +0x30 0x034A0 +0x30 0x044A0 +0x30 0x054A0 +0x30 0x064A0 +0x30 0x074A0 +0x30 0x084A0 +0x30 0x094A0 +0x30 0x0A4A0 +0x30 0x0B4A0 +0xEF 0x00000 +//bias1 end +//bias2 of TXA +0xEF 0x00080 +0x30 0x00203 +0x30 0x01203 +0x30 0x02203 +0x30 0x03203 +0x30 0x04203 +0x30 0x05203 +0x30 0x06203 +0x30 0x07203 +0x30 0x08203 +0x30 0x09203 +0x30 0x0A203 +0x30 0x0B203 +0xEF 0x00000 +//bias2 end +//tank +0xEF 0x00040 +0x30 0x00645 +0x30 0x01333 +0x30 0x02011 +0x30 0x04645 +0x30 0x05333 +0x30 0x06011 +0xEF 0x00000 +//tank end +// TXA Gain table +0xEF 0x00800 +//LB +0x33 0x00020 +0x3F 0x00006 +0x33 0x00021 +0x3F 0x00009 +0x33 0x00022 +0x3F 0x0000C +0x33 0x00023 +0x3F 0x00029 +0x33 0x00024 +0x3F 0x0002C +0x33 0x00025 +0x3F 0x0004B +0x33 0x00026 +0x3F 0x00448 +0x33 0x00027 +0x3F 0x0044B +0x33 0x00028 +0x3F 0x0084B +0x33 0x00029 +0x3F 0x0086B +0x33 0x0002A +0x3F 0x0086E +//MB +0x33 0x00060 +0x3F 0x00006 +0x33 0x00061 +0x3F 0x00009 +0x33 0x00062 +0x3F 0x0000C +0x33 0x00063 +0x3F 0x00029 +0x33 0x00064 +0x3F 0x0002C +0x33 0x00065 +0x3F 0x0004B +0x33 0x00066 +0x3F 0x00448 +0x33 0x00067 +0x3F 0x0044B +0x33 0x00068 +0x3F 0x0084B +0x33 0x00069 +0x3F 0x0086B +0x33 0x0006A +0x3F 0x0086E +//HB +0x33 0x000A0 +0x3F 0x00006 +0x33 0x000A1 +0x3F 0x00009 +0x33 0x000A2 +0x3F 0x0000C +0x33 0x000A3 +0x3F 0x00029 +0x33 0x000A4 +0x3F 0x0002C +0x33 0x000A5 +0x3F 0x0004B +0x33 0x000A6 +0x3F 0x00448 +0x33 0x000A7 +0x3F 0x0044B +0x33 0x000A8 +0x3F 0x0084B +0x33 0x000A9 +0x3F 0x0086B +0x33 0x000AA +0x3F 0x0086E +0xEF 0x00000 + +//TXG bias 1 +0xEF 0x00400 +0x33 0x00000 +0x3F 0x0047C +0x33 0x00001 +0x3F 0x0047C +0x33 0x00002 +0x3F 0x0047C +0x33 0x00003 +0x3F 0x0047C +0xEF 0x00000 +//TXG bias 2 +0xEF 0x00100 +0x33 0x00000 +0x3F 0x01726 +0x33 0x00001 +0x3F 0x01726 +0x33 0x00002 +0x3F 0x01726 +0x33 0x00003 +0x3F 0x01726 +0xEF 0x00000 + +//TXG EVM parameter +0x81 0xF400 +0x87 0x16040 +0x51 0x808 +0x52 0x98002 +0x53 0xFA47 +0x54 0x58032 +0x56 0x51000 +0x57 0xCE0A +0x58 0x82030 + +//TXG gain table +0xEF 0x00800 +0x33 0x00000 +0x3F 0x00003 +0x33 0x00001 +0x3F 0x00006 +0x33 0x00002 +0x3F 0x00009 +0x33 0x00003 +0x3F 0x00026 +0x33 0x00004 +0x3F 0x00029 +0x33 0x00005 +0x3F 0x0002c +0x33 0x00006 +0x3F 0x0002f +0x33 0x00007 +0x3F 0x00033 +0x33 0x00008 +0x3F 0x00036 +0x33 0x00009 +0x3F 0x00039 +0x33 0x0000a +0x3F 0x0003C +0xEF 0x00000 + +//TXLOK +0xEF 0x00010 +0x33 0x00000 +0x08 0x9C060 +0x33 0x00001 +0x08 0x9C060 +0xEF 0x00000 + +//TX mode table for TSSI: +0x33 0x000a2 +0xef 0x80000 +0x3e 0x0593f +0x3f 0xc0f4f +0xef 0x00000 +//RX mode table for TSSI: +0x33 0x000a3 +0xef 0x80000 +0x3e 0x05934 +0x3f 0x5afcf +0xef 0x00000 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B.txt old mode 100755 new mode 100644 index 62deb9c0a30..90000512f36 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B_hp.txt old mode 100755 new mode 100644 index 349ec53556e..7c8a702a401 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822B_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp.txt old mode 100755 new mode 100644 index f76356b76db..74cafb4c294 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fe11 -0x89 0x50110 -0x8a 0x42270 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x22233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x62233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa2233 -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9f233 -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fe11 +0x89 0x50110 +0x8a 0x42270 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x22233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x62233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa2233 +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9f233 +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp_hp.txt old mode 100755 new mode 100644 index 55286e98056..76e17ffbb54 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioB_8822Bmp_hp.txt @@ -1,397 +1,397 @@ -0x00 0x30000 // RF_mode setting -0x01 0x4002D // [4 1]=2b11 disable LTE_coextence -0x18 0x10d24 // [11:10]=2b11/10/01 for 20M/40M/80M - -//RF mode LUT -0xef 0x80000 -0x33 0x00002 //TX mode LUT -0x3e 0x0003f -0x3f 0xc0f4e -0x33 0x00001 //StandBy mode LUT -0x3e 0x00034 -0x3f 0x4080e - -//TX IQK mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0xdf 0x02449 //[11]: TX_GAIN [6]: TXA_TANK -0x33 0x00024 //[3:0]: RFMODE -0x3e 0x0003f -0x3f 0x60fde -0xef 0x00000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK - -//RxK1 mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0x33 0x00025 -0x3e 0x00037 -0x3f 0x6efce -0xef 0x00000 - -//RxK2 mode -0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK -0x33 0x00026 -0x3e 0x00037 -0x3f 0x5efce -0xef 0x00000 -0xdf 0x00009 - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x10524 //5180MHz -0x89 0x00207 //LNA Bias[2:0]=111 -0x8A 0xFF186 //LNA tank[16:13] -0x8B 0x61E3C //LNA EN_Q[15:2] -0x8C 0x112C7 -0x8D 0xF4988 -0x8E 0x64D40 - -//RX_A AGC Table -0xEF 0x20000 //RX_A gain LUT Enable -//LB -0x33 0x00007 //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x00006 //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x00005 //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x00004 //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x00003 //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x00002 //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00001 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00000 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 - -//MB -0x33 0x0000f //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x0000e //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x0000d //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x0000c //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x0000b //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x0000a //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00009 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00008 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 - -//HB -0x33 0x00017 //HG1 -0x3e 0x04000 -0x3f 0xC0006 -0x33 0x00016 //HG2 -0x3e 0x04080 -0x3f 0xC3186 -0x33 0x00015 //MG1 -0x3e 0x040C8 -0x3f 0xC3186 -0x33 0x00014 //MG2 -0x3e 0x04190 -0x3f 0xC3186 -0x33 0x00013 //MG3 -0x3e 0x04998 -0x3f 0xC3186 -0x33 0x00012 //LG1-1 -0x3e 0x05840 -0x3f 0xC3186 -0x33 0x00011 //LG2-1 -0x3e 0x058C2 -0x3f 0xC3186 -0x33 0x00010 //ULG1-1 -0x3e 0x05930 -0x3f 0xC3186 -0xEF 0x00000 - -//RX_A Subband Table -0xEF 0x04000 -0x33 0x00000 //LB -0x3f 0x0000a -0x33 0x00001 //MB -0x3f 0x00005 -0x33 0x00002 //HB -0x3f 0x00000 -0xEF 0x00000 - -//RX_G General Settings -0x18 0x00401 //2412MHz -0x84 0x01209 -0x86 0x001a0 -0x87 0x68080 -0x88 0x70020 -0xde 0x00010 //RXG bias - -//RX_G AGC Table -0xEF 0x08000 //RX_G gain LUT Enable -0x33 0x0000f //CCK HG1 -0x3f 0x0003c -0x33 0x0000e //CCK HG2 -0x3f 0x00038 -0x33 0x0000d //CCK MG1 for ACPR -0x3f 0x00030 -0x33 0x0000c //CCK MG2-1 -0x3f 0x00028 -0x33 0x0000b //CCK MG3 -0x3f 0x00020 -0x33 0x0000a //CCK LG1-1 -0x3f 0x00018 -0x33 0x00009 //CCK LG2 -0x3f 0x00010 -0x33 0x00008 //CCK ULG-1 -0x3f 0x00008 -0x33 0x00007 //HG1 -0x3f 0x0003c -0x33 0x00006 //HG2 -0x3f 0x00038 -0x33 0x00005 //MG1 -0x3f 0x00030 -0x33 0x00004 //MG2-1 -0x3f 0x00028 -0x33 0x00003 //MG3 -0x3f 0x00020 -0x33 0x00002 //LG1-1 -0x3f 0x00018 -0x33 0x00001 //LG2 -0x3f 0x00010 -0x33 0x00000 //ULG-1 -0x3f 0x00008 -0xEF 0x00000 - -//LCK -0x18 0x18d24 //set ch01 do LCK -0xffe -0xffe -0xffe -0xffe -0x18 0x10d24 //set 5180MHz - -//RCK -0x1B 0x75A40 //0x1B[6]=1 -0xDE 0x00012 -0x1D 0x00004 //RCK offset - - -0x61 0x0d4A4 -0x62 0x0d203 -0x63 0x00062 - -//bias1 of TXA -0xEF 0x00200 -0x30 0x004A0 -0x30 0x014A0 -0x30 0x024A0 -0x30 0x034A0 -0x30 0x044A0 -0x30 0x054A0 -0x30 0x064A0 -0x30 0x074A0 -0x30 0x084A0 -0x30 0x094A0 -0x30 0x0A4A0 -0x30 0x0B4A0 -0xEF 0x00000 -//bias1 end -//bias2 of TXA -0xEF 0x00080 -0x30 0x00203 -0x30 0x01203 -0x30 0x02203 -0x30 0x03203 -0x30 0x04203 -0x30 0x05203 -0x30 0x06203 -0x30 0x07203 -0x30 0x08203 -0x30 0x09203 -0x30 0x0A203 -0x30 0x0B203 -0xEF 0x00000 -//bias2 end -//tank -0xEF 0x00040 -0x30 0x00645 -0x30 0x01333 -0x30 0x02011 -0x30 0x04645 -0x30 0x05333 -0x30 0x06011 -0xEF 0x00000 -//tank end -// TXA Gain table -0xEF 0x00800 -//LB -0x33 0x00020 -0x3F 0x00006 -0x33 0x00021 -0x3F 0x00009 -0x33 0x00022 -0x3F 0x0000C -0x33 0x00023 -0x3F 0x00029 -0x33 0x00024 -0x3F 0x0002C -0x33 0x00025 -0x3F 0x0004B -0x33 0x00026 -0x3F 0x00448 -0x33 0x00027 -0x3F 0x0044B -0x33 0x00028 -0x3F 0x0084B -0x33 0x00029 -0x3F 0x0086B -0x33 0x0002A -0x3F 0x0086E -//MB -0x33 0x00060 -0x3F 0x00006 -0x33 0x00061 -0x3F 0x00009 -0x33 0x00062 -0x3F 0x0000C -0x33 0x00063 -0x3F 0x00029 -0x33 0x00064 -0x3F 0x0002C -0x33 0x00065 -0x3F 0x0004B -0x33 0x00066 -0x3F 0x00448 -0x33 0x00067 -0x3F 0x0044B -0x33 0x00068 -0x3F 0x0084B -0x33 0x00069 -0x3F 0x0086B -0x33 0x0006A -0x3F 0x0086E -//HB -0x33 0x000A0 -0x3F 0x00006 -0x33 0x000A1 -0x3F 0x00009 -0x33 0x000A2 -0x3F 0x0000C -0x33 0x000A3 -0x3F 0x00029 -0x33 0x000A4 -0x3F 0x0002C -0x33 0x000A5 -0x3F 0x0004B -0x33 0x000A6 -0x3F 0x00448 -0x33 0x000A7 -0x3F 0x0044B -0x33 0x000A8 -0x3F 0x0084B -0x33 0x000A9 -0x3F 0x0086B -0x33 0x000AA -0x3F 0x0086E -0xEF 0x00000 - -//TXG bias 1 -0xEF 0x00400 -0x33 0x00000 -0x3F 0x0265A -0x33 0x00001 -0x3F 0x0265A -0x33 0x00002 -0x3F 0x0265A -0x33 0x00003 -0x3F 0x0265A -0xEF 0x00000 -//TXG bias 2 -0xEF 0x00100 -0x33 0x00000 -0x3F 0x00745 -0x33 0x00001 -0x3F 0x00745 -0x33 0x00002 -0x3F 0x00745 -0x33 0x00003 -0x3F 0x00745 -0xEF 0x00000 - -//TXG EVM parameter -0x81 0xF400 -0x87 0x16040 -0x51 0x808 -0x52 0x98002 -0x53 0xFA47 -0x54 0x58032 -0x56 0x51000 -0x57 0xCE0A -0x58 0x82030 - -//TXG gain table -0xEF 0x00800 -0x33 0x00000 -0x3F 0x00003 -0x33 0x00001 -0x3F 0x00006 -0x33 0x00002 -0x3F 0x00009 -0x33 0x00003 -0x3F 0x00026 -0x33 0x00004 -0x3F 0x00029 -0x33 0x00005 -0x3F 0x0002c -0x33 0x00006 -0x3F 0x0002f -0x33 0x00007 -0x3F 0x00033 -0x33 0x00008 -0x3F 0x00036 -0x33 0x00009 -0x3F 0x00039 -0x33 0x0000a -0x3F 0x0003C -0xEF 0x00000 - -//TXLOK -0xEF 0x00010 -0x33 0x00000 -0x08 0x9C060 -0x33 0x00001 -0x08 0x9C060 -0xEF 0x00000 - -//TX mode table for TSSI: -0x33 0x000a2 -0xef 0x80000 -0x3e 0x0593f -0x3f 0xc0f4f -0xef 0x00000 -//RX mode table for TSSI: -0x33 0x000a3 -0xef 0x80000 -0x3e 0x05934 -0x3f 0x5afcf -0xef 0x00000 - +0x00 0x30000 // RF_mode setting +0x01 0x4002D // [4 1]=2b11 disable LTE_coextence +0x18 0x10d24 // [11:10]=2b11/10/01 for 20M/40M/80M + +//RF mode LUT +0xef 0x80000 +0x33 0x00002 //TX mode LUT +0x3e 0x0003f +0x3f 0xc0f4e +0x33 0x00001 //StandBy mode LUT +0x3e 0x00034 +0x3f 0x4080e + +//TX IQK mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0xdf 0x02449 //[11]: TX_GAIN [6]: TXA_TANK +0x33 0x00024 //[3:0]: RFMODE +0x3e 0x0003f +0x3f 0x60fde +0xef 0x00000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK + +//RxK1 mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0x33 0x00025 +0x3e 0x00037 +0x3f 0x6efce +0xef 0x00000 + +//RxK2 mode +0xef 0x80000 //[19]: RFMODE [11]: TX_GAIN [4]: TX_LOK +0x33 0x00026 +0x3e 0x00037 +0x3f 0x5efce +0xef 0x00000 +0xdf 0x00009 + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x10524 //5180MHz +0x89 0x00207 //LNA Bias[2:0]=111 +0x8A 0xFF186 //LNA tank[16:13] +0x8B 0x61E3C //LNA EN_Q[15:2] +0x8C 0x112C7 +0x8D 0xF4988 +0x8E 0x64D40 + +//RX_A AGC Table +0xEF 0x20000 //RX_A gain LUT Enable +//LB +0x33 0x00007 //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x00006 //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x00005 //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x00004 //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x00003 //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x00002 //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00001 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00000 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 + +//MB +0x33 0x0000f //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x0000e //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x0000d //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x0000c //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x0000b //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x0000a //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00009 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00008 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 + +//HB +0x33 0x00017 //HG1 +0x3e 0x04000 +0x3f 0xC0006 +0x33 0x00016 //HG2 +0x3e 0x04080 +0x3f 0xC3186 +0x33 0x00015 //MG1 +0x3e 0x040C8 +0x3f 0xC3186 +0x33 0x00014 //MG2 +0x3e 0x04190 +0x3f 0xC3186 +0x33 0x00013 //MG3 +0x3e 0x04998 +0x3f 0xC3186 +0x33 0x00012 //LG1-1 +0x3e 0x05840 +0x3f 0xC3186 +0x33 0x00011 //LG2-1 +0x3e 0x058C2 +0x3f 0xC3186 +0x33 0x00010 //ULG1-1 +0x3e 0x05930 +0x3f 0xC3186 +0xEF 0x00000 + +//RX_A Subband Table +0xEF 0x04000 +0x33 0x00000 //LB +0x3f 0x0000a +0x33 0x00001 //MB +0x3f 0x00005 +0x33 0x00002 //HB +0x3f 0x00000 +0xEF 0x00000 + +//RX_G General Settings +0x18 0x00401 //2412MHz +0x84 0x01209 +0x86 0x001a0 +0x87 0x68080 +0x88 0x70020 +0xde 0x00010 //RXG bias + +//RX_G AGC Table +0xEF 0x08000 //RX_G gain LUT Enable +0x33 0x0000f //CCK HG1 +0x3f 0x0003c +0x33 0x0000e //CCK HG2 +0x3f 0x00038 +0x33 0x0000d //CCK MG1 for ACPR +0x3f 0x00030 +0x33 0x0000c //CCK MG2-1 +0x3f 0x00028 +0x33 0x0000b //CCK MG3 +0x3f 0x00020 +0x33 0x0000a //CCK LG1-1 +0x3f 0x00018 +0x33 0x00009 //CCK LG2 +0x3f 0x00010 +0x33 0x00008 //CCK ULG-1 +0x3f 0x00008 +0x33 0x00007 //HG1 +0x3f 0x0003c +0x33 0x00006 //HG2 +0x3f 0x00038 +0x33 0x00005 //MG1 +0x3f 0x00030 +0x33 0x00004 //MG2-1 +0x3f 0x00028 +0x33 0x00003 //MG3 +0x3f 0x00020 +0x33 0x00002 //LG1-1 +0x3f 0x00018 +0x33 0x00001 //LG2 +0x3f 0x00010 +0x33 0x00000 //ULG-1 +0x3f 0x00008 +0xEF 0x00000 + +//LCK +0x18 0x18d24 //set ch01 do LCK +0xffe +0xffe +0xffe +0xffe +0x18 0x10d24 //set 5180MHz + +//RCK +0x1B 0x75A40 //0x1B[6]=1 +0xDE 0x00012 +0x1D 0x00004 //RCK offset + + +0x61 0x0d4A4 +0x62 0x0d203 +0x63 0x00062 + +//bias1 of TXA +0xEF 0x00200 +0x30 0x004A0 +0x30 0x014A0 +0x30 0x024A0 +0x30 0x034A0 +0x30 0x044A0 +0x30 0x054A0 +0x30 0x064A0 +0x30 0x074A0 +0x30 0x084A0 +0x30 0x094A0 +0x30 0x0A4A0 +0x30 0x0B4A0 +0xEF 0x00000 +//bias1 end +//bias2 of TXA +0xEF 0x00080 +0x30 0x00203 +0x30 0x01203 +0x30 0x02203 +0x30 0x03203 +0x30 0x04203 +0x30 0x05203 +0x30 0x06203 +0x30 0x07203 +0x30 0x08203 +0x30 0x09203 +0x30 0x0A203 +0x30 0x0B203 +0xEF 0x00000 +//bias2 end +//tank +0xEF 0x00040 +0x30 0x00645 +0x30 0x01333 +0x30 0x02011 +0x30 0x04645 +0x30 0x05333 +0x30 0x06011 +0xEF 0x00000 +//tank end +// TXA Gain table +0xEF 0x00800 +//LB +0x33 0x00020 +0x3F 0x00006 +0x33 0x00021 +0x3F 0x00009 +0x33 0x00022 +0x3F 0x0000C +0x33 0x00023 +0x3F 0x00029 +0x33 0x00024 +0x3F 0x0002C +0x33 0x00025 +0x3F 0x0004B +0x33 0x00026 +0x3F 0x00448 +0x33 0x00027 +0x3F 0x0044B +0x33 0x00028 +0x3F 0x0084B +0x33 0x00029 +0x3F 0x0086B +0x33 0x0002A +0x3F 0x0086E +//MB +0x33 0x00060 +0x3F 0x00006 +0x33 0x00061 +0x3F 0x00009 +0x33 0x00062 +0x3F 0x0000C +0x33 0x00063 +0x3F 0x00029 +0x33 0x00064 +0x3F 0x0002C +0x33 0x00065 +0x3F 0x0004B +0x33 0x00066 +0x3F 0x00448 +0x33 0x00067 +0x3F 0x0044B +0x33 0x00068 +0x3F 0x0084B +0x33 0x00069 +0x3F 0x0086B +0x33 0x0006A +0x3F 0x0086E +//HB +0x33 0x000A0 +0x3F 0x00006 +0x33 0x000A1 +0x3F 0x00009 +0x33 0x000A2 +0x3F 0x0000C +0x33 0x000A3 +0x3F 0x00029 +0x33 0x000A4 +0x3F 0x0002C +0x33 0x000A5 +0x3F 0x0004B +0x33 0x000A6 +0x3F 0x00448 +0x33 0x000A7 +0x3F 0x0044B +0x33 0x000A8 +0x3F 0x0084B +0x33 0x000A9 +0x3F 0x0086B +0x33 0x000AA +0x3F 0x0086E +0xEF 0x00000 + +//TXG bias 1 +0xEF 0x00400 +0x33 0x00000 +0x3F 0x0265A +0x33 0x00001 +0x3F 0x0265A +0x33 0x00002 +0x3F 0x0265A +0x33 0x00003 +0x3F 0x0265A +0xEF 0x00000 +//TXG bias 2 +0xEF 0x00100 +0x33 0x00000 +0x3F 0x00745 +0x33 0x00001 +0x3F 0x00745 +0x33 0x00002 +0x3F 0x00745 +0x33 0x00003 +0x3F 0x00745 +0xEF 0x00000 + +//TXG EVM parameter +0x81 0xF400 +0x87 0x16040 +0x51 0x808 +0x52 0x98002 +0x53 0xFA47 +0x54 0x58032 +0x56 0x51000 +0x57 0xCE0A +0x58 0x82030 + +//TXG gain table +0xEF 0x00800 +0x33 0x00000 +0x3F 0x00003 +0x33 0x00001 +0x3F 0x00006 +0x33 0x00002 +0x3F 0x00009 +0x33 0x00003 +0x3F 0x00026 +0x33 0x00004 +0x3F 0x00029 +0x33 0x00005 +0x3F 0x0002c +0x33 0x00006 +0x3F 0x0002f +0x33 0x00007 +0x3F 0x00033 +0x33 0x00008 +0x3F 0x00036 +0x33 0x00009 +0x3F 0x00039 +0x33 0x0000a +0x3F 0x0003C +0xEF 0x00000 + +//TXLOK +0xEF 0x00010 +0x33 0x00000 +0x08 0x9C060 +0x33 0x00001 +0x08 0x9C060 +0xEF 0x00000 + +//TX mode table for TSSI: +0x33 0x000a2 +0xef 0x80000 +0x3e 0x0593f +0x3f 0xc0f4f +0xef 0x00000 +//RX mode table for TSSI: +0x33 0x000a3 +0xef 0x80000 +0x3e 0x05934 +0x3f 0x5afcf +0xef 0x00000 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B.txt old mode 100755 new mode 100644 index 3be2ef6ce50..d24513c9f4e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B_hp.txt old mode 100755 new mode 100644 index ffdca3eb0ee..19a05961f6c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822B_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp.txt old mode 100755 new mode 100644 index ed22e6d56d0..cfc3f9d7c8c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp_hp.txt old mode 100755 new mode 100644 index 9becccf85de..285d5379b89 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioC_8822Bmp_hp.txt @@ -1,323 +1,323 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xe4000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0EF //63 -0x34 0x490EC //57 -0x34 0x480E9 //51 -0x34 0x4704D //45 -0x34 0x4604A //39 -0x34 0x45047 //33 -0x34 0x4400D //27 -0x34 0x4300A //21 -0x34 0x42007 //15 -0x34 0x41004 //9 -0x34 0x40001 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0EF //63 -0x34 0x290EC //57 -0x34 0x280E9 //51 -0x34 0x2704D //45 -0x34 0x2604A //39 -0x34 0x25047 //33 -0x34 0x2400D //27 -0x34 0x2300A //21 -0x34 0x22007 //15 -0x34 0x21004 //9 -0x34 0x20001 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0ED //63 -0x34 0x090EA //57 -0x34 0x0806D //51 -0x34 0x0706A //45 -0x34 0x06067 //39 -0x34 0x0502A //33 -0x34 0x04027 //27 -0x34 0x0300A //21 -0x34 0x02007 //15 -0x34 0x01004 //9 -0x34 0x00001 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0x4A0EF //63 -0x34 0x490EC //57 -0x34 0x480E9 //51 -0x34 0x4704D //45 -0x34 0x4604A //39 -0x34 0x45047 //33 -0x34 0x4400D //27 -0x34 0x4300A //21 -0x34 0x42007 //15 -0x34 0x41004 //9 -0x34 0x40001 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0x2A0EF //63 -0x34 0x290EC //57 -0x34 0x280E9 //51 -0x34 0x2704D //45 -0x34 0x2604A //39 -0x34 0x25047 //33 -0x34 0x2400D //27 -0x34 0x2300A //21 -0x34 0x22007 //15 -0x34 0x21004 //9 -0x34 0x20001 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x0A0ED //63 -0x34 0x090EA //57 -0x34 0x0806D //51 -0x34 0x0706A //45 -0x34 0x06067 //39 -0x34 0x0502A //33 -0x34 0x04027 //27 -0x34 0x0300A //21 -0x34 0x02007 //15 -0x34 0x01004 //9 -0x34 0x00001 //3 -0xEF 0x00000 -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD PAD tank) -0xEF 0x00008 - - - -0x3C 0x0017e //HP_LB_PA_TANK[2:0] -0x3C 0x0057e //HP_MB_PA_TANK[2:0] -0x3C 0x0087e //HP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 //FDD43 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D1 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xe4000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0EF //63 +0x34 0x490EC //57 +0x34 0x480E9 //51 +0x34 0x4704D //45 +0x34 0x4604A //39 +0x34 0x45047 //33 +0x34 0x4400D //27 +0x34 0x4300A //21 +0x34 0x42007 //15 +0x34 0x41004 //9 +0x34 0x40001 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0EF //63 +0x34 0x290EC //57 +0x34 0x280E9 //51 +0x34 0x2704D //45 +0x34 0x2604A //39 +0x34 0x25047 //33 +0x34 0x2400D //27 +0x34 0x2300A //21 +0x34 0x22007 //15 +0x34 0x21004 //9 +0x34 0x20001 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0ED //63 +0x34 0x090EA //57 +0x34 0x0806D //51 +0x34 0x0706A //45 +0x34 0x06067 //39 +0x34 0x0502A //33 +0x34 0x04027 //27 +0x34 0x0300A //21 +0x34 0x02007 //15 +0x34 0x01004 //9 +0x34 0x00001 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0x4A0EF //63 +0x34 0x490EC //57 +0x34 0x480E9 //51 +0x34 0x4704D //45 +0x34 0x4604A //39 +0x34 0x45047 //33 +0x34 0x4400D //27 +0x34 0x4300A //21 +0x34 0x42007 //15 +0x34 0x41004 //9 +0x34 0x40001 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0x2A0EF //63 +0x34 0x290EC //57 +0x34 0x280E9 //51 +0x34 0x2704D //45 +0x34 0x2604A //39 +0x34 0x25047 //33 +0x34 0x2400D //27 +0x34 0x2300A //21 +0x34 0x22007 //15 +0x34 0x21004 //9 +0x34 0x20001 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x0A0ED //63 +0x34 0x090EA //57 +0x34 0x0806D //51 +0x34 0x0706A //45 +0x34 0x06067 //39 +0x34 0x0502A //33 +0x34 0x04027 //27 +0x34 0x0300A //21 +0x34 0x02007 //15 +0x34 0x01004 //9 +0x34 0x00001 //3 +0xEF 0x00000 +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD PAD tank) +0xEF 0x00008 + + + +0x3C 0x0017e //HP_LB_PA_TANK[2:0] +0x3C 0x0057e //HP_MB_PA_TANK[2:0] +0x3C 0x0087e //HP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 //FDD43 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D1 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B.txt old mode 100755 new mode 100644 index 54d956fb0d1..364e0d97c3a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B.txt @@ -1,241 +1,241 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 // CG -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44CE6 -0x34 0x434E7 -0x34 0x4246A -0x34 0x41067 -0x34 0x40069 -//TX AGC 5GM -0x34 0x2ADF2 -0x34 0x29DEF -0x34 0x28DEC -0x34 0x27DE9 -0x34 0x26DE6 -0x34 0x25CE6 -0x34 0x244E7 -0x34 0x2346A -0x34 0x22467 -0x34 0x21069 -0x34 0x20066 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x04CE6 -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x00069 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C4 -0x35 0x081C4 -0x35 0x101C4 -0x35 0x20184 -0x35 0x28184 -0x35 0x30184 -0x35 0x40144 -0x35 0x48144 -0x35 0x50144 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD7 -0x36 0x0CBD7 -0x36 0x14BD7 -0x36 0x1CBD7 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x00249 -0x3C 0x00676 -0x3C 0x00A79 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F7C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35765 -0x64 0x194AC -0x65 0x831D7 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 // CG +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44CE6 +0x34 0x434E7 +0x34 0x4246A +0x34 0x41067 +0x34 0x40069 +//TX AGC 5GM +0x34 0x2ADF2 +0x34 0x29DEF +0x34 0x28DEC +0x34 0x27DE9 +0x34 0x26DE6 +0x34 0x25CE6 +0x34 0x244E7 +0x34 0x2346A +0x34 0x22467 +0x34 0x21069 +0x34 0x20066 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x04CE6 +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x00069 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C4 +0x35 0x081C4 +0x35 0x101C4 +0x35 0x20184 +0x35 0x28184 +0x35 0x30184 +0x35 0x40144 +0x35 0x48144 +0x35 0x50144 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD7 +0x36 0x0CBD7 +0x36 0x14BD7 +0x36 0x1CBD7 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x00249 +0x3C 0x00676 +0x3C 0x00A79 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F7C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35765 +0x64 0x194AC +0x65 0x831D7 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B_hp.txt old mode 100755 new mode 100644 index 935a575cd43..4732d1e45d2 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822B_hp.txt @@ -1,239 +1,239 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f198 // LNA=3b111 -0x3B 0x30a58 // LNA=3b110 -0x3B 0x2a790 // LNA=3b101 -0x3B 0x27bd0 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0A4EE -0x34 0x09076 -0x34 0x08073 -0x34 0x07070 -0x34 0x0606D -0x34 0x0506A -0x34 0x04049 -0x34 0x03046 -0x34 0x02028 -0x34 0x01025 -0x34 0x00022 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) -0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) -0xEF 0x00000 - -0x61 0xFDD43 -//LB -0x62 0x38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f198 // LNA=3b111 +0x3B 0x30a58 // LNA=3b110 +0x3B 0x2a790 // LNA=3b101 +0x3B 0x27bd0 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0A4EE +0x34 0x09076 +0x34 0x08073 +0x34 0x07070 +0x34 0x0606D +0x34 0x0506A +0x34 0x04049 +0x34 0x03046 +0x34 0x02028 +0x34 0x01025 +0x34 0x00022 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00522 // (prePAD_PAD_MOD=111_000_000) +0x3C 0x00902 // (prePAD_PAD_MOD=000_000_000) +0xEF 0x00000 + +0x61 0xFDD43 +//LB +0x62 0x38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp.txt old mode 100755 new mode 100644 index 2a5357655a9..a39aa463791 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp.txt @@ -1,240 +1,240 @@ -//A MODE S0:5180 -0x18 0x13124 -0x58 0x00F98 //0x80F98 -0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G - -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE4B58 -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3F258 // LNA=3b111 -0x3B 0x30A58 // LNA=3b110 -0x3B 0x2FA58 // LNA=3b101 -0x3B 0x22590 // LNA=3b100 -0x3B 0x1FA50 // LNA=3b011 -0x3B 0x10248 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF6 -0x34 0x09DF3 -0x34 0x08DF0 -0x34 0x07DED -0x34 0x06DEA -0x34 0x05CED -0x34 0x04CEA -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146A -0x34 0x0006B -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1312a -0x81 0x7fc00 -0x89 0x5011e -0x8a 0x43e50 -0x8b 0x1e180 -0x8c 0x93c3c -0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 -0xdf 0x00008 // for RXBB 0dB -0x85 0xf8000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc //HG0-1 -0x3B 0x38021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x31023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x2a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x2222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x1fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x11093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x0b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x00093 -0x3C 0x00000 - -//MB -0x3A 0x007bc //HG0-1 -0x3B 0x78021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0x71023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0x6a223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0x6222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x5fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x51093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x4b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x40093 -0x3C 0x00000 - -//HB -0x3A 0x007bc //HG0-1 -0x3B 0xb8021 -0x3C 0xfc000 -0x3A 0x0013c //HG2-1 -0x3B 0xb1023 -0x3C 0x00000 -0x3A 0x000bc //MG1-1 -0x3B 0xaa223 -0x3C 0x00000 -0x3A 0x000bc //MG2-1 -0x3B 0xa222b -0x3C 0x00000 -0x3A 0x000bc //MG3-1 -0x3B 0x9fc2b -0x3C 0x00000 -0x3A 0x001bc //LG1-1 -0x3B 0x91093 -0x3C 0x00000 -0x3A 0x001bc //LG2-1 -0x3B 0x8b093 -0x3C 0x00000 -0x3A 0x00144 //ULG1-1 -0x3B 0x80093 -0x3C 0x00000 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DE2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x248E3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0ADF5 -0x34 0x09DF2 -0x34 0x08DEF -0x34 0x07DEC -0x34 0x06DE9 -0x34 0x05DE6 -0x34 0x048E3 -0x34 0x038C8 -0x34 0x028C5 -0x34 0x018C2 -0x34 0x008C0 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C2 -0x35 0x081C2 -0x35 0x101C2 -0x35 0x201F2 -0x35 0x281F2 -0x35 0x301F2 -0x35 0x401F2 -0x35 0x481F2 -0x35 0x501F2 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BD9 -0x36 0x0CBD9 -0x36 0x14BD9 -0x36 0x1CBD9 -0x36 0x24FD7 -0x36 0x2CFD7 -0x36 0x34FD7 -0x36 0x3CFD7 -0x36 0x44FD7 -0x36 0x4CFD7 -0x36 0x54FD7 -0x36 0x5CFD7 -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0000E -0x3C 0x00870 -0x3C 0x00870 -0xEF 0x00000 - -0x61 0xBFD23 -//LB -0x62 0x06F6C //PA cascode=110 -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0xDF 0x00088 -0x63 0x35773 -0x64 0x194AC -0x65 0x831D5 - +//A MODE S0:5180 +0x18 0x13124 +0x58 0x00F98 //0x80F98 +0x40 0x00C00 // RX_A mixer LDO on & POW_TRIQGEN_G + +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE4B58 +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3F258 // LNA=3b111 +0x3B 0x30A58 // LNA=3b110 +0x3B 0x2FA58 // LNA=3b101 +0x3B 0x22590 // LNA=3b100 +0x3B 0x1FA50 // LNA=3b011 +0x3B 0x10248 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF6 +0x34 0x09DF3 +0x34 0x08DF0 +0x34 0x07DED +0x34 0x06DEA +0x34 0x05CED +0x34 0x04CEA +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146A +0x34 0x0006B +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1312a +0x81 0x7fc00 +0x89 0x5011e +0x8a 0x43e50 +0x8b 0x1e180 +0x8c 0x93c3c +0x8d 0xff200 // ehanceQ off:0xff200 on:0xffa00 +0xdf 0x00008 // for RXBB 0dB +0x85 0xf8000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc //HG0-1 +0x3B 0x38021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x31023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x2a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x2222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x1fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x11093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x0b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x00093 +0x3C 0x00000 + +//MB +0x3A 0x007bc //HG0-1 +0x3B 0x78021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0x71023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0x6a223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0x6222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x5fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x51093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x4b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x40093 +0x3C 0x00000 + +//HB +0x3A 0x007bc //HG0-1 +0x3B 0xb8021 +0x3C 0xfc000 +0x3A 0x0013c //HG2-1 +0x3B 0xb1023 +0x3C 0x00000 +0x3A 0x000bc //MG1-1 +0x3B 0xaa223 +0x3C 0x00000 +0x3A 0x000bc //MG2-1 +0x3B 0xa222b +0x3C 0x00000 +0x3A 0x000bc //MG3-1 +0x3B 0x9fc2b +0x3C 0x00000 +0x3A 0x001bc //LG1-1 +0x3B 0x91093 +0x3C 0x00000 +0x3A 0x001bc //LG2-1 +0x3B 0x8b093 +0x3C 0x00000 +0x3A 0x00144 //ULG1-1 +0x3B 0x80093 +0x3C 0x00000 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DE2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x248E3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0ADF5 +0x34 0x09DF2 +0x34 0x08DEF +0x34 0x07DEC +0x34 0x06DE9 +0x34 0x05DE6 +0x34 0x048E3 +0x34 0x038C8 +0x34 0x028C5 +0x34 0x018C2 +0x34 0x008C0 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C2 +0x35 0x081C2 +0x35 0x101C2 +0x35 0x201F2 +0x35 0x281F2 +0x35 0x301F2 +0x35 0x401F2 +0x35 0x481F2 +0x35 0x501F2 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BD9 +0x36 0x0CBD9 +0x36 0x14BD9 +0x36 0x1CBD9 +0x36 0x24FD7 +0x36 0x2CFD7 +0x36 0x34FD7 +0x36 0x3CFD7 +0x36 0x44FD7 +0x36 0x4CFD7 +0x36 0x54FD7 +0x36 0x5CFD7 +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0000E +0x3C 0x00870 +0x3C 0x00870 +0xEF 0x00000 + +0x61 0xBFD23 +//LB +0x62 0x06F6C //PA cascode=110 +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0xDF 0x00088 +0x63 0x35773 +0x64 0x194AC +0x65 0x831D5 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp_hp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp_hp.txt old mode 100755 new mode 100644 index e355fd77d04..250a56c2a57 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp_hp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/RadioD_8822Bmp_hp.txt @@ -1,328 +1,328 @@ -//RL6302_MAC_PHY_Parameter_v018_20140708 -//A MODE S0:5180 -0x18 0x13124 -0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G -0x58 0x00F98 //0x80F98 -0x7f 0x68004 //G mode TR_IQGEN_VBN -// G mode TRx Setting - -0x18 0x00006 -0x86 0xE335A // CS -0x87 0x49f80 // Mixer gain -0xDF 0x00008 -//RX_G AGC Table -0xEF 0x02000 -0x3B 0x3f19b // LNA=3b111 -0x3B 0x37a5b // LNA=3b110 -0x3B 0x2a433 // LNA=3b101 -0x3B 0x27bd3 // LNA=3b100 -0x3B 0x1f80b // LNA=3b011 -0x3B 0x17803 // LNA=3b010 - -//TX_G GainTable -0xEF 0x00100 -// highpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -// lowpower mode -0x34 0x0A0D0 -0x34 0x090CD -0x34 0x080CA -0x34 0x0704D -0x34 0x0604A -0x34 0x05047 -0x34 0x0400A -0x34 0x03007 -0x34 0x02004 -0x34 0x01001 -0x34 0x00001 -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A General Settings -0x18 0x1012a -0x81 0x7fc00 -0x89 0x50110 -0x8a 0x43e50 -0x8b 0x2e180 -0x8c 0x93c3c -0x85 0xf0000 // RX_A IQgen - -//RX_A AGC Table -0xEF 0x01000 -//LB -0x3A 0x007bc // UHG -0x3B 0x38021 -0x3C 0xec000 -0x3A 0x007bc // HG2 -0x3B 0x30221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x28c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x21c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x1cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x11091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x0a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x01389 -0x3C 0x00000 - -//MB -0x3A 0x007bc // UHG -0x3B 0x78021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0x70221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0x68c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0x61c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x5cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x51091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x4a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x41389 -0x3C 0x00000 - -//HB -0x3A 0x007bc // UHG -0x3B 0xb8021 -0x3C 0xe0000 -0x3A 0x007bc // HG2 -0x3B 0xb0221 -0x3C 0x28000 -0x3A 0x007bc // MG1 -0x3B 0xa8c21 -0x3C 0x00000 -0x3A 0x007bc // MG2 -0x3B 0xa1c31 -0x3C 0x00000 -0x3A 0x007bc // MG3 -0x3B 0x9cc31 -0x3C 0x00000 -0x3A 0x007bc // LG1 -0x3B 0x91091 -0x3C 0x00000 -0x3A 0x007bc // LG2 -0x3B 0x8a591 -0x3C 0x00000 -0x3A 0x007c8 // ULG -0x3B 0x81389 -0x3C 0x00000 - -0xEF 0x00000 - -// RX_A subband Table -0xEF 0x00800 -0x3B 0x00000 // LB -0x3A 0x00801 -0x3B 0x40000 // MB -0x3A 0x01802 -0x3B 0x80000 // HB -0x3A 0x01802 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0x18 0x13124 -0xEF 0x00100 -//TX AGC 5GHB_HP(12dBm) -0x34 0x4A0F0 //63 -0x34 0x490ED //57 -0x34 0x480EA //51 -0x34 0x4706D //45 -0x34 0x4606A //39 -0x34 0x4502D //33 -0x34 0x4402A //27 -0x34 0x4300D //21 -0x34 0x4200A //15 -0x34 0x41007 //9 -0x34 0x40004 //3 -//TX AGC 5GMB_HP(12dBm) -0x34 0x2A0F0 //63 -0x34 0x290ED //57 -0x34 0x280EA //51 -0x34 0x2706D //45 -0x34 0x2606A //39 -0x34 0x2502D //33 -0x34 0x2402A //27 -0x34 0x2300D //21 -0x34 0x2200A //15 -0x34 0x21007 //9 -0x34 0x20004 //3 -//TX AGC 5GLB_HP(12dBm) -0x34 0x0A0F0 //63 -0x34 0x090ED //57 -0x34 0x080EA //51 -0x34 0x0706D //45 -0x34 0x0606A //39 -0x34 0x0502D //33 -0x34 0x0402A //27 -0x34 0x0300D //21 -0x34 0x0200A //15 -0x34 0x01007 //9 -0x34 0x00004 //3 -//TX AGC 5GHB_LP(9dBm) -0x34 0xCA0F0 //63 -0x34 0xC90ED //57 -0x34 0xC80EA //51 -0x34 0xC706D //45 -0x34 0xC606A //39 -0x34 0xC502D //33 -0x34 0xC402A //27 -0x34 0xC3027 //21 -0x34 0xC2024 //15 -0x34 0xC1007 //9 -0x34 0xC0004 //3 -//TX AGC 5GMB_LP(9dBm) -0x34 0xAA0F0 //63 -0x34 0xA90ED //57 -0x34 0xA80EA //51 -0x34 0xA706D //45 -0x34 0xA606A //39 -0x34 0xA502D //33 -0x34 0xA402A //27 -0x34 0xA3027 //21 -0x34 0xA2024 //15 -0x34 0xA1007 //9 -0x34 0xA0004 //3 -//TX AGC 5GLB_LP(9dBm) -0x34 0x8A0F0 //63 -0x34 0x890ED //57 -0x34 0x880EA //51 -0x34 0x8706D //45 -0x34 0x8606A //39 -0x34 0x8502D //33 -0x34 0x8402A //27 -0x34 0x83027 //21 -0x34 0x82024 //15 -0x34 0x81007 //9 -0x34 0x80004 //3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00040 -0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0xDF 0x00001 -0x18 0x1712A -0xEF 0x00010 -0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 -0xEF 0x00000 - - -//Table_5G_TX_Tank_S0(MOD PAD tank) -0xEF 0x00008 - - -//Table_5G_RTX_Tank_S0(PA output tank) - -0x3C 0x0017e //HP_LB_PA_TANK[2:0](3C[9:7]) -0x3C 0x00576 //HP_MB_PA_TANK[2:0] -0x3C 0x00872 //HP_HB_PA_TANK[2:0] -0x3C 0x0117d //LP_LB_PA_TANK[2:0] -0x3C 0x0157d //LP_MB_PA_TANK[2:0] -0x3C 0x0187d //LP_HB_PA_TANK[2:0] -0xEF 0x00000 - -//0x59 0x68390 -0x61 0xC0D47 //FDD43 -//LB -0x62 0x0133c //38F4B -//MB and HB -//0x62 0x06DEF //PA cascode=011 -0x63 0x750E7 //32117 -0x64 0x14FEC //194AC -0x65 0x931D1 -0x66 0x00040 //00000(high ch) -//0x58 0x80FEc -//0xDF 0x04F8D -0x57 0x90000 -0x56 0x51Df0 - +//RL6302_MAC_PHY_Parameter_v018_20140708 +//A MODE S0:5180 +0x18 0x13124 +0x40 0x00c00 // RX_A mixer LDO on & POW_TRIQGEN_G +0x58 0x00F98 //0x80F98 +0x7f 0x68004 //G mode TR_IQGEN_VBN +// G mode TRx Setting + +0x18 0x00006 +0x86 0xE335A // CS +0x87 0x49f80 // Mixer gain +0xDF 0x00008 +//RX_G AGC Table +0xEF 0x02000 +0x3B 0x3f19b // LNA=3b111 +0x3B 0x37a5b // LNA=3b110 +0x3B 0x2a433 // LNA=3b101 +0x3B 0x27bd3 // LNA=3b100 +0x3B 0x1f80b // LNA=3b011 +0x3B 0x17803 // LNA=3b010 + +//TX_G GainTable +0xEF 0x00100 +// highpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +// lowpower mode +0x34 0x0A0D0 +0x34 0x090CD +0x34 0x080CA +0x34 0x0704D +0x34 0x0604A +0x34 0x05047 +0x34 0x0400A +0x34 0x03007 +0x34 0x02004 +0x34 0x01001 +0x34 0x00001 +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A General Settings +0x18 0x1012a +0x81 0x7fc00 +0x89 0x50110 +0x8a 0x43e50 +0x8b 0x2e180 +0x8c 0x93c3c +0x85 0xf0000 // RX_A IQgen + +//RX_A AGC Table +0xEF 0x01000 +//LB +0x3A 0x007bc // UHG +0x3B 0x38021 +0x3C 0xec000 +0x3A 0x007bc // HG2 +0x3B 0x30221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x28c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x21c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x1cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x11091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x0a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x01389 +0x3C 0x00000 + +//MB +0x3A 0x007bc // UHG +0x3B 0x78021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0x70221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0x68c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0x61c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x5cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x51091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x4a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x41389 +0x3C 0x00000 + +//HB +0x3A 0x007bc // UHG +0x3B 0xb8021 +0x3C 0xe0000 +0x3A 0x007bc // HG2 +0x3B 0xb0221 +0x3C 0x28000 +0x3A 0x007bc // MG1 +0x3B 0xa8c21 +0x3C 0x00000 +0x3A 0x007bc // MG2 +0x3B 0xa1c31 +0x3C 0x00000 +0x3A 0x007bc // MG3 +0x3B 0x9cc31 +0x3C 0x00000 +0x3A 0x007bc // LG1 +0x3B 0x91091 +0x3C 0x00000 +0x3A 0x007bc // LG2 +0x3B 0x8a591 +0x3C 0x00000 +0x3A 0x007c8 // ULG +0x3B 0x81389 +0x3C 0x00000 + +0xEF 0x00000 + +// RX_A subband Table +0xEF 0x00800 +0x3B 0x00000 // LB +0x3A 0x00801 +0x3B 0x40000 // MB +0x3A 0x01802 +0x3B 0x80000 // HB +0x3A 0x01802 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0x18 0x13124 +0xEF 0x00100 +//TX AGC 5GHB_HP(12dBm) +0x34 0x4A0F0 //63 +0x34 0x490ED //57 +0x34 0x480EA //51 +0x34 0x4706D //45 +0x34 0x4606A //39 +0x34 0x4502D //33 +0x34 0x4402A //27 +0x34 0x4300D //21 +0x34 0x4200A //15 +0x34 0x41007 //9 +0x34 0x40004 //3 +//TX AGC 5GMB_HP(12dBm) +0x34 0x2A0F0 //63 +0x34 0x290ED //57 +0x34 0x280EA //51 +0x34 0x2706D //45 +0x34 0x2606A //39 +0x34 0x2502D //33 +0x34 0x2402A //27 +0x34 0x2300D //21 +0x34 0x2200A //15 +0x34 0x21007 //9 +0x34 0x20004 //3 +//TX AGC 5GLB_HP(12dBm) +0x34 0x0A0F0 //63 +0x34 0x090ED //57 +0x34 0x080EA //51 +0x34 0x0706D //45 +0x34 0x0606A //39 +0x34 0x0502D //33 +0x34 0x0402A //27 +0x34 0x0300D //21 +0x34 0x0200A //15 +0x34 0x01007 //9 +0x34 0x00004 //3 +//TX AGC 5GHB_LP(9dBm) +0x34 0xCA0F0 //63 +0x34 0xC90ED //57 +0x34 0xC80EA //51 +0x34 0xC706D //45 +0x34 0xC606A //39 +0x34 0xC502D //33 +0x34 0xC402A //27 +0x34 0xC3027 //21 +0x34 0xC2024 //15 +0x34 0xC1007 //9 +0x34 0xC0004 //3 +//TX AGC 5GMB_LP(9dBm) +0x34 0xAA0F0 //63 +0x34 0xA90ED //57 +0x34 0xA80EA //51 +0x34 0xA706D //45 +0x34 0xA606A //39 +0x34 0xA502D //33 +0x34 0xA402A //27 +0x34 0xA3027 //21 +0x34 0xA2024 //15 +0x34 0xA1007 //9 +0x34 0xA0004 //3 +//TX AGC 5GLB_LP(9dBm) +0x34 0x8A0F0 //63 +0x34 0x890ED //57 +0x34 0x880EA //51 +0x34 0x8706D //45 +0x34 0x8606A //39 +0x34 0x8502D //33 +0x34 0x8402A //27 +0x34 0x83027 //21 +0x34 0x82024 //15 +0x34 0x81007 //9 +0x34 0x80004 //3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00040 +0x35 0x006cc //HP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x086cc //HP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x106cc //HP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x206cc //HP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x286cc //HP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x306cc //HP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x406cc //HP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x486cc //HP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x506cc //HP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x806cc //LP_LB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x886cc //LP_LB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0x906cc //LP_LB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa06cc //LP_MB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xa86cc //LP_MB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xb06cc //LP_MB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc06cc //LP_HB_40M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xc86cc //LP_HB_20M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0x35 0xd06cc //LP_HB_10M_BS_IPA_PACAS=110_PADYS_ATT=1100_BSCNT_IPA_PA=0101 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0xDF 0x00001 +0x18 0x1712A +0xEF 0x00010 +0x36 0x00473 //HP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x08473 //HP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x10473 //HP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x20473 //HP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x28473 //HP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x30473 //HP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x40473 //HP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x48473 //HP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x50473 //HP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x80473 //LP_LB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x88473 //LP_LB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0x90473 //LP_LB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa0473 //LP_MB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xa8473 //LP_MB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xb0473 //LP_MB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc0473 //LP_HB_40M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xc8473 //LP_HB_20M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0x36 0xd0473 //LP_HB_10M_BS_IPA_PADCAS=100_PADYS_ATT=0111_BSCNT_IPA_PA=0011 +0xEF 0x00000 + + +//Table_5G_TX_Tank_S0(MOD PAD tank) +0xEF 0x00008 + + +//Table_5G_RTX_Tank_S0(PA output tank) + +0x3C 0x0017e //HP_LB_PA_TANK[2:0](3C[9:7]) +0x3C 0x00576 //HP_MB_PA_TANK[2:0] +0x3C 0x00872 //HP_HB_PA_TANK[2:0] +0x3C 0x0117d //LP_LB_PA_TANK[2:0] +0x3C 0x0157d //LP_MB_PA_TANK[2:0] +0x3C 0x0187d //LP_HB_PA_TANK[2:0] +0xEF 0x00000 + +//0x59 0x68390 +0x61 0xC0D47 //FDD43 +//LB +0x62 0x0133c //38F4B +//MB and HB +//0x62 0x06DEF //PA cascode=011 +0x63 0x750E7 //32117 +0x64 0x14FEC //194AC +0x65 0x931D1 +0x66 0x00040 //00000(high ch) +//0x58 0x80FEc +//0xDF 0x04F8D +0x57 0x90000 +0x56 0x51Df0 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822B.txt old mode 100755 new mode 100644 index 21e8e43feb8..9b6c7fdaa60 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822B.txt @@ -1,325 +1,325 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 18 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 18 16 NA -CH159 18 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 18 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 18 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 18 16 NA +CH159 18 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 18 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp.txt old mode 100755 new mode 100644 index 6faf60b78a5..666782081d0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v046_20141008 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 15 15 -CH02 17 15 15 -CH03 17 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 15 14 14 -CH02 16 14 14 -CH03 16 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 14 13 13 -CH02 15 13 13 -CH03 15 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 15 15 -CH13 NA 15 15 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 14 14 14 -CH04 16 14 14 -CH05 16 14 14 -CH06 16 14 14 -CH07 16 14 14 -CH08 16 14 14 -CH09 16 14 14 -CH10 16 14 14 -CH11 14 14 14 -CH12 NA 14 14 -CH13 NA 14 14 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 13 13 -CH04 15 13 13 -CH05 15 13 13 -CH06 15 13 13 -CH07 15 13 13 -CH08 15 13 13 -CH09 15 13 13 -CH10 15 13 13 -CH11 13 13 13 -CH12 NA 13 13 -CH13 NA 13 13 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 22 16 16 -CH40 22 16 16 -CH44 22 16 16 -CH48 22 16 16 -//5G Band 2 -CH52 22 16 16 -CH56 22 16 16 -CH60 22 16 16 -CH64 22 16 16 -//5G Band 3 -CH100 22 16 16 -CH104 22 16 16 -CH108 22 16 16 -CH112 22 16 16 -CH116 22 16 16 -CH120 22 16 16 -CH124 22 16 16 -CH128 22 16 16 -CH132 22 16 16 -CH136 22 16 16 -CH140 22 16 16 -//5G Band 4 -CH149 22 16 NA -CH153 22 16 NA -CH157 22 16 NA -CH161 22 16 NA -CH165 22 16 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 22 16 16 -CH40 22 16 16 -CH44 22 16 16 -CH48 22 16 16 -//5G Band 2 -CH52 22 16 16 -CH56 22 16 16 -CH60 22 16 16 -CH64 22 16 16 -//5G Band 3 -CH100 22 16 16 -CH104 22 16 16 -CH108 22 16 16 -CH112 22 16 16 -CH116 22 16 16 -CH120 22 16 16 -CH124 22 16 16 -CH128 22 16 16 -CH132 22 16 16 -CH136 22 16 16 -CH140 22 16 16 -//5G Band 4 -CH149 22 16 NA -CH153 22 16 NA -CH157 22 16 NA -CH161 22 16 NA -CH165 22 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 22 15 15 -CH40 22 15 15 -CH44 22 15 15 -CH48 22 15 15 -//5G Band 2 -CH52 22 15 15 -CH56 22 15 15 -CH60 22 15 15 -CH64 22 15 15 -//5G Band 3 -CH100 22 15 15 -CH104 22 15 15 -CH108 22 15 15 -CH112 22 15 15 -CH116 22 15 15 -CH120 22 15 15 -CH124 22 15 15 -CH128 22 15 15 -CH132 22 15 15 -CH136 22 15 15 -CH140 22 15 15 -//5G Band 4 -CH149 22 15 NA -CH153 22 15 NA -CH157 22 15 NA -CH161 22 15 NA -CH165 22 15 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 22 14 14 -CH40 22 14 14 -CH44 22 14 14 -CH48 22 14 14 -//5G Band 2 -CH52 22 14 14 -CH56 22 14 14 -CH60 22 14 14 -CH64 22 14 14 -//5G Band 3 -CH100 22 14 14 -CH104 22 14 14 -CH108 22 14 14 -CH112 22 14 14 -CH116 22 14 14 -CH120 22 14 14 -CH124 22 14 14 -CH128 22 14 14 -CH132 22 14 14 -CH136 22 14 14 -CH140 22 14 14 -//5G Band 4 -CH149 22 14 NA -CH153 22 14 NA -CH157 22 14 NA -CH161 22 14 NA -CH165 22 14 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 22 13 13 -CH40 22 13 13 -CH44 22 13 13 -CH48 22 13 13 -//5G Band 2 -CH52 22 13 13 -CH56 22 13 13 -CH60 22 13 13 -CH64 22 13 13 -//5G Band 3 -CH100 22 13 13 -CH104 22 13 13 -CH108 22 13 13 -CH112 22 13 13 -CH116 22 13 13 -CH120 22 13 13 -CH124 22 13 13 -CH128 22 13 13 -CH132 22 13 13 -CH136 22 13 13 -CH140 22 13 13 -//5G Band 4 -CH149 22 13 NA -CH153 22 13 NA -CH157 22 13 NA -CH161 22 13 NA -CH165 22 13 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 22 16 16 -CH46 22 16 16 -//5G Band 2 -CH54 22 16 16 -CH62 22 16 16 -//5G Band 3 -CH102 22 16 16 -CH110 22 16 16 -CH118 22 16 16 -CH126 22 16 16 -CH134 22 16 16 -//5G Band 4 -CH151 22 16 NA -CH159 22 16 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 22 15 15 -CH46 22 15 15 -//5G Band 2 -CH54 22 15 15 -CH62 22 15 15 -//5G Band 3 -CH102 22 15 15 -CH110 22 15 15 -CH118 22 15 15 -CH126 22 15 15 -CH134 22 15 15 -//5G Band 4 -CH151 22 15 NA -CH159 22 15 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 22 14 14 -CH46 22 14 14 -//5G Band 2 -CH54 22 14 14 -CH62 22 14 14 -//5G Band 3 -CH102 22 14 14 -CH110 22 14 14 -CH118 22 14 14 -CH126 22 14 14 -CH134 22 14 14 -//5G Band 4 -CH151 22 14 NA -CH159 22 14 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 22 13 13 -CH46 22 13 13 -//5G Band 2 -CH54 22 13 13 -CH62 22 13 13 -//5G Band 3 -CH102 22 13 13 -CH110 22 13 13 -CH118 22 13 13 -CH126 22 13 13 -CH134 22 13 13 -//5G Band 4 -CH151 22 13 NA -CH159 22 13 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 22 16 16 -//5G Band 2 -CH58 22 16 16 -//5G Band 3 -CH106 22 16 16 -CH122 22 16 16 -//5G Band 4 -CH155 22 16 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 22 15 15 -//5G Band 2 -CH58 22 15 15 -//5G Band 3 -CH106 22 15 15 -CH122 22 15 15 -//5G Band 4 -CH155 22 15 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 22 14 14 -//5G Band 2 -CH58 22 14 14 -//5G Band 3 -CH106 22 14 14 -CH122 22 14 14 -//5G Band 4 -CH155 22 14 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 22 13 13 -//5G Band 2 -CH58 22 13 13 -//5G Band 3 -CH106 22 13 13 -CH122 22 13 13 -//5G Band 4 -CH155 22 13 NA -## END +//RL6302_MAC_PHY_Parameter_v046_20141008 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 15 15 +CH02 17 15 15 +CH03 17 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 15 14 14 +CH02 16 14 14 +CH03 16 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 14 13 13 +CH02 15 13 13 +CH03 15 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 15 15 +CH13 NA 15 15 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 14 14 14 +CH04 16 14 14 +CH05 16 14 14 +CH06 16 14 14 +CH07 16 14 14 +CH08 16 14 14 +CH09 16 14 14 +CH10 16 14 14 +CH11 14 14 14 +CH12 NA 14 14 +CH13 NA 14 14 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 13 13 +CH04 15 13 13 +CH05 15 13 13 +CH06 15 13 13 +CH07 15 13 13 +CH08 15 13 13 +CH09 15 13 13 +CH10 15 13 13 +CH11 13 13 13 +CH12 NA 13 13 +CH13 NA 13 13 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 22 16 16 +CH40 22 16 16 +CH44 22 16 16 +CH48 22 16 16 +//5G Band 2 +CH52 22 16 16 +CH56 22 16 16 +CH60 22 16 16 +CH64 22 16 16 +//5G Band 3 +CH100 22 16 16 +CH104 22 16 16 +CH108 22 16 16 +CH112 22 16 16 +CH116 22 16 16 +CH120 22 16 16 +CH124 22 16 16 +CH128 22 16 16 +CH132 22 16 16 +CH136 22 16 16 +CH140 22 16 16 +//5G Band 4 +CH149 22 16 NA +CH153 22 16 NA +CH157 22 16 NA +CH161 22 16 NA +CH165 22 16 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 22 16 16 +CH40 22 16 16 +CH44 22 16 16 +CH48 22 16 16 +//5G Band 2 +CH52 22 16 16 +CH56 22 16 16 +CH60 22 16 16 +CH64 22 16 16 +//5G Band 3 +CH100 22 16 16 +CH104 22 16 16 +CH108 22 16 16 +CH112 22 16 16 +CH116 22 16 16 +CH120 22 16 16 +CH124 22 16 16 +CH128 22 16 16 +CH132 22 16 16 +CH136 22 16 16 +CH140 22 16 16 +//5G Band 4 +CH149 22 16 NA +CH153 22 16 NA +CH157 22 16 NA +CH161 22 16 NA +CH165 22 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 22 15 15 +CH40 22 15 15 +CH44 22 15 15 +CH48 22 15 15 +//5G Band 2 +CH52 22 15 15 +CH56 22 15 15 +CH60 22 15 15 +CH64 22 15 15 +//5G Band 3 +CH100 22 15 15 +CH104 22 15 15 +CH108 22 15 15 +CH112 22 15 15 +CH116 22 15 15 +CH120 22 15 15 +CH124 22 15 15 +CH128 22 15 15 +CH132 22 15 15 +CH136 22 15 15 +CH140 22 15 15 +//5G Band 4 +CH149 22 15 NA +CH153 22 15 NA +CH157 22 15 NA +CH161 22 15 NA +CH165 22 15 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 22 14 14 +CH40 22 14 14 +CH44 22 14 14 +CH48 22 14 14 +//5G Band 2 +CH52 22 14 14 +CH56 22 14 14 +CH60 22 14 14 +CH64 22 14 14 +//5G Band 3 +CH100 22 14 14 +CH104 22 14 14 +CH108 22 14 14 +CH112 22 14 14 +CH116 22 14 14 +CH120 22 14 14 +CH124 22 14 14 +CH128 22 14 14 +CH132 22 14 14 +CH136 22 14 14 +CH140 22 14 14 +//5G Band 4 +CH149 22 14 NA +CH153 22 14 NA +CH157 22 14 NA +CH161 22 14 NA +CH165 22 14 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 22 13 13 +CH40 22 13 13 +CH44 22 13 13 +CH48 22 13 13 +//5G Band 2 +CH52 22 13 13 +CH56 22 13 13 +CH60 22 13 13 +CH64 22 13 13 +//5G Band 3 +CH100 22 13 13 +CH104 22 13 13 +CH108 22 13 13 +CH112 22 13 13 +CH116 22 13 13 +CH120 22 13 13 +CH124 22 13 13 +CH128 22 13 13 +CH132 22 13 13 +CH136 22 13 13 +CH140 22 13 13 +//5G Band 4 +CH149 22 13 NA +CH153 22 13 NA +CH157 22 13 NA +CH161 22 13 NA +CH165 22 13 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 22 16 16 +CH46 22 16 16 +//5G Band 2 +CH54 22 16 16 +CH62 22 16 16 +//5G Band 3 +CH102 22 16 16 +CH110 22 16 16 +CH118 22 16 16 +CH126 22 16 16 +CH134 22 16 16 +//5G Band 4 +CH151 22 16 NA +CH159 22 16 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 22 15 15 +CH46 22 15 15 +//5G Band 2 +CH54 22 15 15 +CH62 22 15 15 +//5G Band 3 +CH102 22 15 15 +CH110 22 15 15 +CH118 22 15 15 +CH126 22 15 15 +CH134 22 15 15 +//5G Band 4 +CH151 22 15 NA +CH159 22 15 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 22 14 14 +CH46 22 14 14 +//5G Band 2 +CH54 22 14 14 +CH62 22 14 14 +//5G Band 3 +CH102 22 14 14 +CH110 22 14 14 +CH118 22 14 14 +CH126 22 14 14 +CH134 22 14 14 +//5G Band 4 +CH151 22 14 NA +CH159 22 14 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 22 13 13 +CH46 22 13 13 +//5G Band 2 +CH54 22 13 13 +CH62 22 13 13 +//5G Band 3 +CH102 22 13 13 +CH110 22 13 13 +CH118 22 13 13 +CH126 22 13 13 +CH134 22 13 13 +//5G Band 4 +CH151 22 13 NA +CH159 22 13 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 22 16 16 +//5G Band 2 +CH58 22 16 16 +//5G Band 3 +CH106 22 16 16 +CH122 22 16 16 +//5G Band 4 +CH155 22 16 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 22 15 15 +//5G Band 2 +CH58 22 15 15 +//5G Band 3 +CH106 22 15 15 +CH122 22 15 15 +//5G Band 4 +CH155 22 15 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 22 14 14 +//5G Band 2 +CH58 22 14 14 +//5G Band 3 +CH106 22 14 14 +CH122 22 14 14 +//5G Band 4 +CH155 22 14 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 22 13 13 +//5G Band 2 +CH58 22 13 13 +//5G Band 3 +CH106 22 13 13 +CH122 22 13 13 +//5G Band 4 +CH155 22 13 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_TXBF.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_TXBF.txt old mode 100755 new mode 100644 index e6ffc8ca6b9..7d675bad407 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_TXBF.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_TXBF.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 20 30 30 -CH40 20 30 30 -CH44 20 30 30 -CH48 20 30 30 -//5G Band 2 -CH52 20 30 30 -CH56 20 30 30 -CH60 20 30 30 -CH64 20 30 30 -//5G Band 3 -CH100 20 30 30 -CH104 20 30 30 -CH108 20 30 30 -CH112 20 30 30 -CH116 20 30 30 -CH120 20 30 30 -CH124 20 30 30 -CH128 20 30 30 -CH132 20 30 30 -CH136 20 30 30 -CH140 20 30 30 -//5G Band 4 -CH149 20 30 NA -CH153 20 30 NA -CH157 20 30 NA -CH161 20 30 NA -CH165 20 30 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 20 30 30 -CH40 20 30 30 -CH44 20 30 30 -CH48 20 30 30 -//5G Band 2 -CH52 20 30 30 -CH56 20 30 30 -CH60 20 30 30 -CH64 20 30 30 -//5G Band 3 -CH100 20 30 30 -CH104 20 30 30 -CH108 20 30 30 -CH112 20 30 30 -CH116 20 30 30 -CH120 20 30 30 -CH124 20 30 30 -CH128 20 30 30 -CH132 20 30 30 -CH136 20 30 30 -CH140 20 30 30 -//5G Band 4 -CH149 20 30 NA -CH153 20 30 NA -CH157 20 30 NA -CH161 20 30 NA -CH165 20 30 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 20 30 30 -CH40 20 30 30 -CH44 20 30 30 -CH48 20 30 30 -//5G Band 2 -CH52 20 30 30 -CH56 20 30 30 -CH60 20 30 30 -CH64 20 30 30 -//5G Band 3 -CH100 20 30 30 -CH104 20 30 30 -CH108 20 30 30 -CH112 20 30 30 -CH116 20 30 30 -CH120 20 30 30 -CH124 20 30 30 -CH128 20 30 30 -CH132 20 30 30 -CH136 20 30 30 -CH140 20 30 30 -//5G Band 4 -CH149 20 30 NA -CH153 20 30 NA -CH157 20 30 NA -CH161 20 30 NA -CH165 20 30 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 20 30 30 -CH40 20 30 30 -CH44 20 30 30 -CH48 20 30 30 -//5G Band 2 -CH52 20 30 30 -CH56 20 30 30 -CH60 20 30 30 -CH64 20 30 30 -//5G Band 3 -CH100 20 30 30 -CH104 20 30 30 -CH108 20 30 30 -CH112 20 30 30 -CH116 20 30 30 -CH120 20 30 30 -CH124 20 30 30 -CH128 20 30 30 -CH132 20 30 30 -CH136 20 30 30 -CH140 20 30 30 -//5G Band 4 -CH149 20 30 NA -CH153 20 30 NA -CH157 20 30 NA -CH161 20 30 NA -CH165 20 30 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 20 30 30 -CH40 20 30 30 -CH44 20 30 30 -CH48 20 30 30 -//5G Band 2 -CH52 20 30 30 -CH56 20 30 30 -CH60 20 30 30 -CH64 20 30 30 -//5G Band 3 -CH100 20 30 30 -CH104 20 30 30 -CH108 20 30 30 -CH112 20 30 30 -CH116 20 30 30 -CH120 20 30 30 -CH124 20 30 30 -CH128 20 30 30 -CH132 20 30 30 -CH136 20 30 30 -CH140 20 30 30 -//5G Band 4 -CH149 20 30 NA -CH153 20 30 NA -CH157 20 30 NA -CH161 20 30 NA -CH165 20 30 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 30 30 -CH46 20 30 30 -//5G Band 2 -CH54 20 30 30 -CH62 20 30 30 -//5G Band 3 -CH102 20 30 30 -CH110 20 30 30 -CH118 20 30 30 -CH126 20 30 30 -CH134 20 30 30 -//5G Band 4 -CH151 20 30 NA -CH159 20 30 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 30 30 -CH46 20 30 30 -//5G Band 2 -CH54 20 30 30 -CH62 20 30 30 -//5G Band 3 -CH102 20 30 30 -CH110 20 30 30 -CH118 20 30 30 -CH126 20 30 30 -CH134 20 30 30 -//5G Band 4 -CH151 20 30 NA -CH159 20 30 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 30 30 -CH46 20 30 30 -//5G Band 2 -CH54 20 30 30 -CH62 20 30 30 -//5G Band 3 -CH102 20 30 30 -CH110 20 30 30 -CH118 20 30 30 -CH126 20 30 30 -CH134 20 30 30 -//5G Band 4 -CH151 20 30 NA -CH159 20 30 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 30 30 -CH46 20 30 30 -//5G Band 2 -CH54 20 30 30 -CH62 20 30 30 -//5G Band 3 -CH102 20 30 30 -CH110 20 30 30 -CH118 20 30 30 -CH126 20 30 30 -CH134 20 30 30 -//5G Band 4 -CH151 20 30 NA -CH159 20 30 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 30 30 -//5G Band 2 -CH58 20 30 30 -//5G Band 3 -CH106 20 30 30 -CH122 20 30 30 -//5G Band 4 -CH155 20 30 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 30 30 -//5G Band 2 -CH58 20 30 30 -//5G Band 3 -CH106 20 30 30 -CH122 20 30 30 -//5G Band 4 -CH155 20 30 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 30 30 -//5G Band 2 -CH58 20 30 30 -//5G Band 3 -CH106 20 30 30 -CH122 20 30 30 -//5G Band 4 -CH155 20 30 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 30 30 -//5G Band 2 -CH58 20 30 30 -//5G Band 3 -CH106 20 30 30 -CH122 20 30 30 -//5G Band 4 -CH155 20 30 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 20 30 30 +CH40 20 30 30 +CH44 20 30 30 +CH48 20 30 30 +//5G Band 2 +CH52 20 30 30 +CH56 20 30 30 +CH60 20 30 30 +CH64 20 30 30 +//5G Band 3 +CH100 20 30 30 +CH104 20 30 30 +CH108 20 30 30 +CH112 20 30 30 +CH116 20 30 30 +CH120 20 30 30 +CH124 20 30 30 +CH128 20 30 30 +CH132 20 30 30 +CH136 20 30 30 +CH140 20 30 30 +//5G Band 4 +CH149 20 30 NA +CH153 20 30 NA +CH157 20 30 NA +CH161 20 30 NA +CH165 20 30 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 20 30 30 +CH40 20 30 30 +CH44 20 30 30 +CH48 20 30 30 +//5G Band 2 +CH52 20 30 30 +CH56 20 30 30 +CH60 20 30 30 +CH64 20 30 30 +//5G Band 3 +CH100 20 30 30 +CH104 20 30 30 +CH108 20 30 30 +CH112 20 30 30 +CH116 20 30 30 +CH120 20 30 30 +CH124 20 30 30 +CH128 20 30 30 +CH132 20 30 30 +CH136 20 30 30 +CH140 20 30 30 +//5G Band 4 +CH149 20 30 NA +CH153 20 30 NA +CH157 20 30 NA +CH161 20 30 NA +CH165 20 30 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 20 30 30 +CH40 20 30 30 +CH44 20 30 30 +CH48 20 30 30 +//5G Band 2 +CH52 20 30 30 +CH56 20 30 30 +CH60 20 30 30 +CH64 20 30 30 +//5G Band 3 +CH100 20 30 30 +CH104 20 30 30 +CH108 20 30 30 +CH112 20 30 30 +CH116 20 30 30 +CH120 20 30 30 +CH124 20 30 30 +CH128 20 30 30 +CH132 20 30 30 +CH136 20 30 30 +CH140 20 30 30 +//5G Band 4 +CH149 20 30 NA +CH153 20 30 NA +CH157 20 30 NA +CH161 20 30 NA +CH165 20 30 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 20 30 30 +CH40 20 30 30 +CH44 20 30 30 +CH48 20 30 30 +//5G Band 2 +CH52 20 30 30 +CH56 20 30 30 +CH60 20 30 30 +CH64 20 30 30 +//5G Band 3 +CH100 20 30 30 +CH104 20 30 30 +CH108 20 30 30 +CH112 20 30 30 +CH116 20 30 30 +CH120 20 30 30 +CH124 20 30 30 +CH128 20 30 30 +CH132 20 30 30 +CH136 20 30 30 +CH140 20 30 30 +//5G Band 4 +CH149 20 30 NA +CH153 20 30 NA +CH157 20 30 NA +CH161 20 30 NA +CH165 20 30 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 20 30 30 +CH40 20 30 30 +CH44 20 30 30 +CH48 20 30 30 +//5G Band 2 +CH52 20 30 30 +CH56 20 30 30 +CH60 20 30 30 +CH64 20 30 30 +//5G Band 3 +CH100 20 30 30 +CH104 20 30 30 +CH108 20 30 30 +CH112 20 30 30 +CH116 20 30 30 +CH120 20 30 30 +CH124 20 30 30 +CH128 20 30 30 +CH132 20 30 30 +CH136 20 30 30 +CH140 20 30 30 +//5G Band 4 +CH149 20 30 NA +CH153 20 30 NA +CH157 20 30 NA +CH161 20 30 NA +CH165 20 30 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 30 30 +CH46 20 30 30 +//5G Band 2 +CH54 20 30 30 +CH62 20 30 30 +//5G Band 3 +CH102 20 30 30 +CH110 20 30 30 +CH118 20 30 30 +CH126 20 30 30 +CH134 20 30 30 +//5G Band 4 +CH151 20 30 NA +CH159 20 30 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 30 30 +CH46 20 30 30 +//5G Band 2 +CH54 20 30 30 +CH62 20 30 30 +//5G Band 3 +CH102 20 30 30 +CH110 20 30 30 +CH118 20 30 30 +CH126 20 30 30 +CH134 20 30 30 +//5G Band 4 +CH151 20 30 NA +CH159 20 30 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 30 30 +CH46 20 30 30 +//5G Band 2 +CH54 20 30 30 +CH62 20 30 30 +//5G Band 3 +CH102 20 30 30 +CH110 20 30 30 +CH118 20 30 30 +CH126 20 30 30 +CH134 20 30 30 +//5G Band 4 +CH151 20 30 NA +CH159 20 30 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 30 30 +CH46 20 30 30 +//5G Band 2 +CH54 20 30 30 +CH62 20 30 30 +//5G Band 3 +CH102 20 30 30 +CH110 20 30 30 +CH118 20 30 30 +CH126 20 30 30 +CH134 20 30 30 +//5G Band 4 +CH151 20 30 NA +CH159 20 30 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 30 30 +//5G Band 2 +CH58 20 30 30 +//5G Band 3 +CH106 20 30 30 +CH122 20 30 30 +//5G Band 4 +CH155 20 30 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 30 30 +//5G Band 2 +CH58 20 30 30 +//5G Band 3 +CH106 20 30 30 +CH122 20 30 30 +//5G Band 4 +CH155 20 30 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 30 30 +//5G Band 2 +CH58 20 30 30 +//5G Band 3 +CH106 20 30 30 +CH122 20 30 30 +//5G Band 4 +CH155 20 30 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 30 30 +//5G Band 2 +CH58 20 30 30 +//5G Band 3 +CH106 20 30 30 +CH122 20 30 30 +//5G Band 4 +CH155 20 30 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type0.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type0.txt old mode 100755 new mode 100644 index cd47a6ed8ad..d0797b3aa7e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type0.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type0.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type1.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type1.txt index 030680cbc67..d0286c98166 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type1.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type1.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type10.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type10.txt index cd47a6ed8ad..d0797b3aa7e 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type10.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type10.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type11.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type11.txt old mode 100755 new mode 100644 index 030680cbc67..d0286c98166 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type11.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type11.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type13.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type13.txt old mode 100755 new mode 100644 index cd47a6ed8ad..d0797b3aa7e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type13.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type13.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type14.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type14.txt old mode 100755 new mode 100644 index cd47a6ed8ad..d0797b3aa7e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type14.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type14.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type2.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type2.txt old mode 100755 new mode 100644 index 6f51ff5323f..4268d86320a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type2.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type2.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 30 30 30 -CH40 30 30 30 -CH44 30 30 30 -CH48 30 30 30 -//5G Band 2 -CH52 30 30 30 -CH56 30 30 30 -CH60 30 30 30 -CH64 30 30 30 -//5G Band 3 -CH100 30 30 30 -CH104 30 30 30 -CH108 30 30 30 -CH112 30 30 30 -CH116 30 30 30 -CH120 30 30 30 -CH124 30 30 30 -CH128 30 30 30 -CH132 30 30 30 -CH136 30 30 30 -CH140 30 30 30 -//5G Band 4 -CH149 30 30 NA -CH153 30 30 NA -CH157 30 30 NA -CH161 30 30 NA -CH165 30 30 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 30 30 30 -CH40 30 30 30 -CH44 30 30 30 -CH48 30 30 30 -//5G Band 2 -CH52 30 30 30 -CH56 30 30 30 -CH60 30 30 30 -CH64 30 30 30 -//5G Band 3 -CH100 30 30 30 -CH104 30 30 30 -CH108 30 30 30 -CH112 30 30 30 -CH116 30 30 30 -CH120 30 30 30 -CH124 30 30 30 -CH128 30 30 30 -CH132 30 30 30 -CH136 30 30 30 -CH140 30 30 30 -//5G Band 4 -CH149 30 30 NA -CH153 30 30 NA -CH157 30 30 NA -CH161 30 30 NA -CH165 30 30 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 30 30 30 -CH40 30 30 30 -CH44 30 30 30 -CH48 30 30 30 -//5G Band 2 -CH52 30 30 30 -CH56 30 30 30 -CH60 30 30 30 -CH64 30 30 30 -//5G Band 3 -CH100 30 30 30 -CH104 30 30 30 -CH108 30 30 30 -CH112 30 30 30 -CH116 30 30 30 -CH120 30 30 30 -CH124 30 30 30 -CH128 30 30 30 -CH132 30 30 30 -CH136 30 30 30 -CH140 30 30 30 -//5G Band 4 -CH149 30 30 NA -CH153 30 30 NA -CH157 30 30 NA -CH161 30 30 NA -CH165 30 30 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 30 30 30 -CH40 30 30 30 -CH44 30 30 30 -CH48 30 30 30 -//5G Band 2 -CH52 30 30 30 -CH56 30 30 30 -CH60 30 30 30 -CH64 30 30 30 -//5G Band 3 -CH100 30 30 30 -CH104 30 30 30 -CH108 30 30 30 -CH112 30 30 30 -CH116 30 30 30 -CH120 30 30 30 -CH124 30 30 30 -CH128 30 30 30 -CH132 30 30 30 -CH136 30 30 30 -CH140 30 30 30 -//5G Band 4 -CH149 30 30 NA -CH153 30 30 NA -CH157 30 30 NA -CH161 30 30 NA -CH165 30 30 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 30 30 30 -CH40 30 30 30 -CH44 30 30 30 -CH48 30 30 30 -//5G Band 2 -CH52 30 30 30 -CH56 30 30 30 -CH60 30 30 30 -CH64 30 30 30 -//5G Band 3 -CH100 30 30 30 -CH104 30 30 30 -CH108 30 30 30 -CH112 30 30 30 -CH116 30 30 30 -CH120 30 30 30 -CH124 30 30 30 -CH128 30 30 30 -CH132 30 30 30 -CH136 30 30 30 -CH140 30 30 30 -//5G Band 4 -CH149 30 30 NA -CH153 30 30 NA -CH157 30 30 NA -CH161 30 30 NA -CH165 30 30 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 30 30 30 -CH46 30 30 30 -//5G Band 2 -CH54 30 30 30 -CH62 30 30 30 -//5G Band 3 -CH102 30 30 30 -CH110 30 30 30 -CH118 30 30 30 -CH126 30 30 30 -CH134 30 30 30 -//5G Band 4 -CH151 30 30 NA -CH159 30 30 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 30 30 30 -CH46 30 30 30 -//5G Band 2 -CH54 30 30 30 -CH62 30 30 30 -//5G Band 3 -CH102 30 30 30 -CH110 30 30 30 -CH118 30 30 30 -CH126 30 30 30 -CH134 30 30 30 -//5G Band 4 -CH151 30 30 NA -CH159 30 30 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 30 30 30 -CH46 30 30 30 -//5G Band 2 -CH54 30 30 30 -CH62 30 30 30 -//5G Band 3 -CH102 30 30 30 -CH110 30 30 30 -CH118 30 30 30 -CH126 30 30 30 -CH134 30 30 30 -//5G Band 4 -CH151 30 30 NA -CH159 30 30 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 30 30 30 -CH46 30 30 30 -//5G Band 2 -CH54 30 30 30 -CH62 30 30 30 -//5G Band 3 -CH102 30 30 30 -CH110 30 30 30 -CH118 30 30 30 -CH126 30 30 30 -CH134 30 30 30 -//5G Band 4 -CH151 30 30 NA -CH159 30 30 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 30 30 30 -//5G Band 2 -CH58 30 30 30 -//5G Band 3 -CH106 30 30 30 -CH122 30 30 30 -//5G Band 4 -CH155 30 30 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 30 30 30 -//5G Band 2 -CH58 30 30 30 -//5G Band 3 -CH106 30 30 30 -CH122 30 30 30 -//5G Band 4 -CH155 30 30 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 30 30 30 -//5G Band 2 -CH58 30 30 30 -//5G Band 3 -CH106 30 30 30 -CH122 30 30 30 -//5G Band 4 -CH155 30 30 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 30 30 30 -//5G Band 2 -CH58 30 30 30 -//5G Band 3 -CH106 30 30 30 -CH122 30 30 30 -//5G Band 4 -CH155 30 30 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 30 30 30 +CH40 30 30 30 +CH44 30 30 30 +CH48 30 30 30 +//5G Band 2 +CH52 30 30 30 +CH56 30 30 30 +CH60 30 30 30 +CH64 30 30 30 +//5G Band 3 +CH100 30 30 30 +CH104 30 30 30 +CH108 30 30 30 +CH112 30 30 30 +CH116 30 30 30 +CH120 30 30 30 +CH124 30 30 30 +CH128 30 30 30 +CH132 30 30 30 +CH136 30 30 30 +CH140 30 30 30 +//5G Band 4 +CH149 30 30 NA +CH153 30 30 NA +CH157 30 30 NA +CH161 30 30 NA +CH165 30 30 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 30 30 30 +CH40 30 30 30 +CH44 30 30 30 +CH48 30 30 30 +//5G Band 2 +CH52 30 30 30 +CH56 30 30 30 +CH60 30 30 30 +CH64 30 30 30 +//5G Band 3 +CH100 30 30 30 +CH104 30 30 30 +CH108 30 30 30 +CH112 30 30 30 +CH116 30 30 30 +CH120 30 30 30 +CH124 30 30 30 +CH128 30 30 30 +CH132 30 30 30 +CH136 30 30 30 +CH140 30 30 30 +//5G Band 4 +CH149 30 30 NA +CH153 30 30 NA +CH157 30 30 NA +CH161 30 30 NA +CH165 30 30 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 30 30 30 +CH40 30 30 30 +CH44 30 30 30 +CH48 30 30 30 +//5G Band 2 +CH52 30 30 30 +CH56 30 30 30 +CH60 30 30 30 +CH64 30 30 30 +//5G Band 3 +CH100 30 30 30 +CH104 30 30 30 +CH108 30 30 30 +CH112 30 30 30 +CH116 30 30 30 +CH120 30 30 30 +CH124 30 30 30 +CH128 30 30 30 +CH132 30 30 30 +CH136 30 30 30 +CH140 30 30 30 +//5G Band 4 +CH149 30 30 NA +CH153 30 30 NA +CH157 30 30 NA +CH161 30 30 NA +CH165 30 30 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 30 30 30 +CH40 30 30 30 +CH44 30 30 30 +CH48 30 30 30 +//5G Band 2 +CH52 30 30 30 +CH56 30 30 30 +CH60 30 30 30 +CH64 30 30 30 +//5G Band 3 +CH100 30 30 30 +CH104 30 30 30 +CH108 30 30 30 +CH112 30 30 30 +CH116 30 30 30 +CH120 30 30 30 +CH124 30 30 30 +CH128 30 30 30 +CH132 30 30 30 +CH136 30 30 30 +CH140 30 30 30 +//5G Band 4 +CH149 30 30 NA +CH153 30 30 NA +CH157 30 30 NA +CH161 30 30 NA +CH165 30 30 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 30 30 30 +CH40 30 30 30 +CH44 30 30 30 +CH48 30 30 30 +//5G Band 2 +CH52 30 30 30 +CH56 30 30 30 +CH60 30 30 30 +CH64 30 30 30 +//5G Band 3 +CH100 30 30 30 +CH104 30 30 30 +CH108 30 30 30 +CH112 30 30 30 +CH116 30 30 30 +CH120 30 30 30 +CH124 30 30 30 +CH128 30 30 30 +CH132 30 30 30 +CH136 30 30 30 +CH140 30 30 30 +//5G Band 4 +CH149 30 30 NA +CH153 30 30 NA +CH157 30 30 NA +CH161 30 30 NA +CH165 30 30 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 30 30 30 +CH46 30 30 30 +//5G Band 2 +CH54 30 30 30 +CH62 30 30 30 +//5G Band 3 +CH102 30 30 30 +CH110 30 30 30 +CH118 30 30 30 +CH126 30 30 30 +CH134 30 30 30 +//5G Band 4 +CH151 30 30 NA +CH159 30 30 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 30 30 30 +CH46 30 30 30 +//5G Band 2 +CH54 30 30 30 +CH62 30 30 30 +//5G Band 3 +CH102 30 30 30 +CH110 30 30 30 +CH118 30 30 30 +CH126 30 30 30 +CH134 30 30 30 +//5G Band 4 +CH151 30 30 NA +CH159 30 30 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 30 30 30 +CH46 30 30 30 +//5G Band 2 +CH54 30 30 30 +CH62 30 30 30 +//5G Band 3 +CH102 30 30 30 +CH110 30 30 30 +CH118 30 30 30 +CH126 30 30 30 +CH134 30 30 30 +//5G Band 4 +CH151 30 30 NA +CH159 30 30 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 30 30 30 +CH46 30 30 30 +//5G Band 2 +CH54 30 30 30 +CH62 30 30 30 +//5G Band 3 +CH102 30 30 30 +CH110 30 30 30 +CH118 30 30 30 +CH126 30 30 30 +CH134 30 30 30 +//5G Band 4 +CH151 30 30 NA +CH159 30 30 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 30 30 30 +//5G Band 2 +CH58 30 30 30 +//5G Band 3 +CH106 30 30 30 +CH122 30 30 30 +//5G Band 4 +CH155 30 30 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 30 30 30 +//5G Band 2 +CH58 30 30 30 +//5G Band 3 +CH106 30 30 30 +CH122 30 30 30 +//5G Band 4 +CH155 30 30 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 30 30 30 +//5G Band 2 +CH58 30 30 30 +//5G Band 3 +CH106 30 30 30 +CH122 30 30 30 +//5G Band 4 +CH155 30 30 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 30 30 30 +//5G Band 2 +CH58 30 30 30 +//5G Band 3 +CH106 30 30 30 +CH122 30 30 30 +//5G Band 4 +CH155 30 30 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type3.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type3.txt old mode 100755 new mode 100644 index 5ad3ae38e30..059e12cbdd3 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type3.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type3.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA 20 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA 20 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type4.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type4.txt old mode 100755 new mode 100644 index 030680cbc67..d0286c98166 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type4.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type4.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type5.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type5.txt old mode 100755 new mode 100644 index 4fc4d2d9204..7c377fa8eeb --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type5.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type5.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA 20 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 23 20 20 -CH02 23 20 20 -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 23 20 20 -CH04 23 20 20 -CH05 23 20 20 -CH06 23 20 20 -CH07 23 20 20 -CH08 23 20 20 -CH09 23 20 20 -CH10 23 20 20 -CH11 23 20 20 -CH12 NA 20 20 -CH13 NA 20 20 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 23 20 20 -CH46 23 20 20 -//5G Band 2 -CH54 23 20 20 -CH62 23 20 20 -//5G Band 3 -CH102 23 20 20 -CH110 23 20 20 -CH118 23 20 20 -CH126 23 20 20 -CH134 23 20 20 -//5G Band 4 -CH151 23 20 NA -CH159 23 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 23 20 20 -//5G Band 2 -CH58 23 20 20 -//5G Band 3 -CH106 23 20 20 -CH122 23 20 20 -//5G Band 4 -CH155 23 20 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA 20 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 23 20 20 +CH02 23 20 20 +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 23 20 20 +CH04 23 20 20 +CH05 23 20 20 +CH06 23 20 20 +CH07 23 20 20 +CH08 23 20 20 +CH09 23 20 20 +CH10 23 20 20 +CH11 23 20 20 +CH12 NA 20 20 +CH13 NA 20 20 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 23 20 20 +CH46 23 20 20 +//5G Band 2 +CH54 23 20 20 +CH62 23 20 20 +//5G Band 3 +CH102 23 20 20 +CH110 23 20 20 +CH118 23 20 20 +CH126 23 20 20 +CH134 23 20 20 +//5G Band 4 +CH151 23 20 NA +CH159 23 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 23 20 20 +//5G Band 2 +CH58 23 20 20 +//5G Band 3 +CH106 23 20 20 +CH122 23 20 20 +//5G Band 4 +CH155 23 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type6.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type6.txt old mode 100755 new mode 100644 index 030680cbc67..d0286c98166 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type6.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type6.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type7.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type7.txt old mode 100755 new mode 100644 index 030680cbc67..d0286c98166 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type7.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type7.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type8.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type8.txt old mode 100755 new mode 100644 index 030680cbc67..d0286c98166 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type8.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type8.txt @@ -1,556 +1,556 @@ -//RL6302_MAC_PHY_Parameter_v054_20141124 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA 30 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 30 30 30 -CH02 30 30 30 -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 30 30 30 -CH04 30 30 30 -CH05 30 30 30 -CH06 30 30 30 -CH07 30 30 30 -CH08 30 30 30 -CH09 30 30 30 -CH10 30 30 30 -CH11 30 30 30 -CH12 NA 30 30 -CH13 NA 30 30 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 23 20 20 -CH40 23 20 20 -CH44 23 20 20 -CH48 23 20 20 -//5G Band 2 -CH52 23 20 20 -CH56 23 20 20 -CH60 23 20 20 -CH64 23 20 20 -//5G Band 3 -CH100 23 20 20 -CH104 23 20 20 -CH108 23 20 20 -CH112 23 20 20 -CH116 23 20 20 -CH120 23 20 20 -CH124 23 20 20 -CH128 23 20 20 -CH132 23 20 20 -CH136 23 20 20 -CH140 23 20 20 -//5G Band 4 -CH149 23 20 NA -CH153 23 20 NA -CH157 23 20 NA -CH161 23 20 NA -CH165 23 20 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 30: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 20 20 20 -CH46 20 20 20 -//5G Band 2 -CH54 20 20 20 -CH62 20 20 20 -//5G Band 3 -CH102 20 20 20 -CH110 20 20 20 -CH118 20 20 20 -CH126 20 20 20 -CH134 20 20 20 -//5G Band 4 -CH151 20 20 NA -CH159 20 20 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 20 20 20 -//5G Band 2 -CH58 20 20 20 -//5G Band 3 -CH106 20 20 20 -CH122 20 20 20 -//5G Band 4 -CH155 20 20 NA -## END +//RL6302_MAC_PHY_Parameter_v054_20141124 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA 30 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 30 30 30 +CH02 30 30 30 +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 30 30 30 +CH04 30 30 30 +CH05 30 30 30 +CH06 30 30 30 +CH07 30 30 30 +CH08 30 30 30 +CH09 30 30 30 +CH10 30 30 30 +CH11 30 30 30 +CH12 NA 30 30 +CH13 NA 30 30 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;30M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 23 20 20 +CH40 23 20 20 +CH44 23 20 20 +CH48 23 20 20 +//5G Band 2 +CH52 23 20 20 +CH56 23 20 20 +CH60 23 20 20 +CH64 23 20 20 +//5G Band 3 +CH100 23 20 20 +CH104 23 20 20 +CH108 23 20 20 +CH112 23 20 20 +CH116 23 20 20 +CH120 23 20 20 +CH124 23 20 20 +CH128 23 20 20 +CH132 23 20 20 +CH136 23 20 20 +CH140 23 20 20 +//5G Band 4 +CH149 23 20 NA +CH153 23 20 NA +CH157 23 20 NA +CH161 23 20 NA +CH165 23 20 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 30: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 20 20 20 +CH46 20 20 20 +//5G Band 2 +CH54 20 20 20 +CH62 20 20 20 +//5G Band 3 +CH102 20 20 20 +CH110 20 20 20 +CH118 20 20 20 +CH126 20 20 20 +CH134 20 20 20 +//5G Band 4 +CH151 20 20 NA +CH159 20 20 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 20 20 20 +//5G Band 2 +CH58 20 20 20 +//5G Band 3 +CH106 20 20 20 +CH122 20 20 20 +//5G Band 4 +CH155 20 20 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type9.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type9.txt old mode 100755 new mode 100644 index cd47a6ed8ad..d0797b3aa7e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type9.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TXPWR_LMT_8822Bmp_Type9.txt @@ -1,555 +1,555 @@ -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 17 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 8: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 9: =========================================== -// -## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 10: =========================================== -// -## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 11: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 12: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 13: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 14: =========================================== -// -## 5G, 20M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 15: =========================================== -// -## 5G, 20M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH104 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 16: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 17: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 18: =========================================== -// -## 5G, 40M, 3T, HT, //(MCS16~MCS23) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 19: =========================================== -// -## 5G, 40M, 4T, HT, //(MCS24~MCS31) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 17 17 -CH46 17 17 17 -//5G Band 2 -CH54 17 17 17 -CH62 17 17 17 -//5G Band 3 -CH102 17 17 17 -CH110 17 17 17 -CH118 17 17 17 -CH126 17 17 17 -CH134 17 17 17 -//5G Band 4 -CH151 17 17 NA -CH159 17 17 NA -## END -// -//Table 20: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 21: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 22: =========================================== -// -## 5G, 80M, 3T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END -// -//Table 23: =========================================== -// -## 5G, 80M, 4T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 17 17 17 -//5G Band 2 -CH58 17 17 17 -//5G Band 3 -CH106 17 17 17 -CH122 17 17 17 -//5G Band 4 -CH155 17 17 NA -## END +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 17 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 8: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 9: =========================================== +// +## 2.4G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 10: =========================================== +// +## 2.4G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 11: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 12: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 13: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 14: =========================================== +// +## 5G, 20M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 15: =========================================== +// +## 5G, 20M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH104 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 16: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 17: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 18: =========================================== +// +## 5G, 40M, 3T, HT, //(MCS16~MCS23) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 19: =========================================== +// +## 5G, 40M, 4T, HT, //(MCS24~MCS31) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 17 17 +CH46 17 17 17 +//5G Band 2 +CH54 17 17 17 +CH62 17 17 17 +//5G Band 3 +CH102 17 17 17 +CH110 17 17 17 +CH118 17 17 17 +CH126 17 17 17 +CH134 17 17 17 +//5G Band 4 +CH151 17 17 NA +CH159 17 17 NA +## END +// +//Table 20: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 21: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 22: =========================================== +// +## 5G, 80M, 3T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END +// +//Table 23: =========================================== +// +## 5G, 80M, 4T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 17 17 17 +//5G Band 2 +CH58 17 17 17 +//5G Band 3 +CH106 17 17 17 +CH122 17 17 17 +//5G Band 4 +CH155 17 17 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822B.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822B.txt old mode 100755 new mode 100644 index ab0f2fa250a..d7b1a823846 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822B.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822B.txt @@ -1,43 +1,43 @@ -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKA_P -[2G][A][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKA_N -[2G][B][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GCCKB_P -[2G][B][-][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,8,8,9,9,10,10,11,11,12,12,13,13,14,15,15,16} //2GCCKB_N -[2G][C][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKC_P -[2G][C][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKC_N -[2G][D][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14,15} //2GCCKD_P -[2G][D][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13} //2GCCKD_N -[2G][A][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,13,13} //2GA_P -[2G][A][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,10,10,10} //2GA_N -[2G][B][+][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GB_P -[2G][B][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10} //2GB_N -[2G][C][+][ALL] = {0,0,1,1,2,2,3,3,3,4,4,5,5,5,6,6,7,7,8,8,8,9,9,10,10,10,11,11,12,12} //2GC_P -[2G][C][-][ALL] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GC_N -[2G][D][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,12,13} //2GD_P -[2G][D][-][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,13,14} //2GD_N -[5G][A][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GLA_P -[5G][A][-][ALL][0] = {0,1,2,3,4,5,5,6,7,8,9,10,11,12,13,14,14,15,16,17,18,19,20,21,22,23,23,24,25,25} //5GLA_N -[5G][B][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19,20,21,22,23,24,25,25,25,25,25,25} //5GLB_P -[5G][B][-][ALL][0] = {0,1,2,2,3,4,5,6,7,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,20,20,21,22,23,24} //5GLB_N -[5G][C][+][ALL][0] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,21,23,24,25,25,25,25,25,25,25,25,25} //5GLC_P -[5G][C][-][ALL][0] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GLC_N -[5G][D][+][ALL][0] = {0,1,2,4,5,6,7,9,10,11,12,14,15,16,17,18,20,21,22,23,25,25,25,25,25,25,25,25,25,25} //5GLD_P -[5G][D][-][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25} //5GLD_N -[5G][A][+][ALL][1] = {0,1,2,3,4,5,6,7,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,23,24,25,25,25} //5GMA_P -[5G][A][-][ALL][1] = {0,1,1,2,3,4,4,5,6,6,7,8,9,9,10,11,11,12,13,14,14,15,16,16,17,18,19,19,20,21} //5GMA_N -[5G][B][+][ALL][1] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,21,22,23,24,25,25,25,25,25,25} //5GMB_P -[5G][B][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,10,10,11,12,13,14,15,16,16,17,18,19,20,21,22,22,23,24,25} //5GMB_N -[5G][C][+][ALL][1] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25} //5GMC_P -[5G][C][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,14,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GMC_N -[5G][D][+][ALL][1] = {0,1,2,4,5,6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25,25} //5GMD_P -[5G][D][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,9,10,11,12,13,14,15,15,16,17,18,19,20,21,21,22,23,24,25} //5GMD_N -[5G][A][+][ALL][2] = {0,1,2,3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25} //5GHA_P -[5G][A][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,18,19,20,21,22,23,24,25,25} //5GHA_N -[5G][B][+][ALL][2] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GHB_P -[5G][B][-][ALL][2] = {0,1,2,2,3,4,5,6,6,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,19,20,21,22,23,23} //5GHB_N -[5G][C][+][ALL][2] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25,25} //5GHC_P -[5G][C][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25} //5GHC_N -[5G][D][+][ALL][2] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,22,23,24,25,25,25,25,25,25,25,25,25} //5GHD_P -[5G][D][-][ALL][2] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,18,19,20,21,22,23,23,24} //5GHD_N +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKA_P +[2G][A][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKA_N +[2G][B][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GCCKB_P +[2G][B][-][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,8,8,9,9,10,10,11,11,12,12,13,13,14,15,15,16} //2GCCKB_N +[2G][C][+][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GCCKC_P +[2G][C][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13,14} //2GCCKC_N +[2G][D][+][CCK] = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14,15} //2GCCKD_P +[2G][D][-][CCK] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,6,7,7,8,8,9,9,10,10,11,11,12,12,12,13,13} //2GCCKD_N +[2G][A][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,13,13} //2GA_P +[2G][A][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,10,10,10} //2GA_N +[2G][B][+][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,14,14} //2GB_P +[2G][B][-][ALL] = {0,0,1,1,1,2,2,2,3,3,4,4,4,5,5,5,6,6,6,7,7,7,8,8,8,9,9,9,10,10} //2GB_N +[2G][C][+][ALL] = {0,0,1,1,2,2,3,3,3,4,4,5,5,5,6,6,7,7,8,8,8,9,9,10,10,10,11,11,12,12} //2GC_P +[2G][C][-][ALL] = {0,1,1,2,2,3,3,4,4,5,5,6,7,7,8,8,9,9,10,10,11,11,12,13,13,14,14,15,15,16} //2GC_N +[2G][D][+][ALL] = {0,0,1,1,2,2,3,3,4,4,4,5,5,6,6,7,7,8,8,8,9,9,10,10,11,11,12,12,12,13} //2GD_P +[2G][D][-][ALL] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13,13,14} //2GD_N +[5G][A][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GLA_P +[5G][A][-][ALL][0] = {0,1,2,3,4,5,5,6,7,8,9,10,11,12,13,14,14,15,16,17,18,19,20,21,22,23,23,24,25,25} //5GLA_N +[5G][B][+][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19,20,21,22,23,24,25,25,25,25,25,25} //5GLB_P +[5G][B][-][ALL][0] = {0,1,2,2,3,4,5,6,7,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,20,20,21,22,23,24} //5GLB_N +[5G][C][+][ALL][0] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,21,23,24,25,25,25,25,25,25,25,25,25} //5GLC_P +[5G][C][-][ALL][0] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GLC_N +[5G][D][+][ALL][0] = {0,1,2,4,5,6,7,9,10,11,12,14,15,16,17,18,20,21,22,23,25,25,25,25,25,25,25,25,25,25} //5GLD_P +[5G][D][-][ALL][0] = {0,1,2,3,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25} //5GLD_N +[5G][A][+][ALL][1] = {0,1,2,3,4,5,6,7,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,23,24,25,25,25} //5GMA_P +[5G][A][-][ALL][1] = {0,1,1,2,3,4,4,5,6,6,7,8,9,9,10,11,11,12,13,14,14,15,16,16,17,18,19,19,20,21} //5GMA_N +[5G][B][+][ALL][1] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,21,22,23,24,25,25,25,25,25,25} //5GMB_P +[5G][B][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,10,10,11,12,13,14,15,16,16,17,18,19,20,21,22,22,23,24,25} //5GMB_N +[5G][C][+][ALL][1] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25} //5GMC_P +[5G][C][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,14,14,15,16,17,18,19,19,20,21,22,23,24,24} //5GMC_N +[5G][D][+][ALL][1] = {0,1,2,4,5,6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,24,25,25,25,25,25,25,25,25,25} //5GMD_P +[5G][D][-][ALL][1] = {0,1,2,3,3,4,5,6,7,8,9,9,10,11,12,13,14,15,15,16,17,18,19,20,21,21,22,23,24,25} //5GMD_N +[5G][A][+][ALL][2] = {0,1,2,3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25} //5GHA_P +[5G][A][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,11,12,13,14,15,16,17,18,18,19,20,21,22,23,24,25,25} //5GHA_N +[5G][B][+][ALL][2] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,25,25,25,25} //5GHB_P +[5G][B][-][ALL][2] = {0,1,2,2,3,4,5,6,6,7,8,9,10,11,11,12,13,14,15,15,16,17,18,19,19,20,21,22,23,23} //5GHB_N +[5G][C][+][ALL][2] = {0,1,2,3,4,6,7,8,9,10,11,12,13,15,16,17,18,19,20,21,22,23,25,25,25,25,25,25,25,25} //5GHC_P +[5G][C][-][ALL][2] = {0,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,19,20,21,22,22,23,24,25,25} //5GHC_N +[5G][D][+][ALL][2] = {0,1,2,4,5,6,7,8,10,11,12,13,14,16,17,18,19,20,22,23,24,25,25,25,25,25,25,25,25,25} //5GHD_P +[5G][D][-][ALL][2] = {0,1,2,3,3,4,5,6,7,8,8,9,10,11,12,13,13,14,15,16,17,18,18,19,20,21,22,23,23,24} //5GHD_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822Bmp.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822Bmp.txt old mode 100755 new mode 100644 index 66519a850e6..816d0e1c41d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822Bmp.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/TxPowerTrack_AP_8822Bmp.txt @@ -1,26 +1,26 @@ -//rtl8822b version = 36 -//rtl8822b version = 29 -// -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKA_P -[2G][A][-][CCK] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GCCKA_N -[2G][B][+][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKB_P -[2G][B][-][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,17,17,17,17,17,17,17,17} //2GCCKB_N -[2G][A][+][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GA_P -[2G][A][-][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GA_N -[2G][B][+][ALL] = {0,1,1,2,3,4,4,5,6,7,7,8,9,10,11,12,12,13,14,15,16,17,17,18,19,20,21,22,22,22} //2GB_P -[2G][B][-][ALL] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,18,18,18,18,18,18,18,18} //2GB_N -[5G][A][+][ALL][0] = {0,1,2,2,3,4,5,5,6,7,8,9,9,10,11,12,13,14,14,15,16,17,18,19,19,20,20,20,20,20} //5GLA_P -[5G][A][-][ALL][0] = {0,1,2,2,3,3,4,5,6,7,8,8,9,9,10,11,11,12,12,12,13,13,14,14,14,15,15,15,15,15} //5GLA_N -[5G][B][+][ALL][0] = {0,1,2,2,3,4,5,6,7,8,8,9,10,11,11,12,13,14,15,15,16,17,18,18,19,19,19,19,19,19} //5GLB_P -[5G][B][-][ALL][0] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,10,11,11,12,12,12,13,13,14,14,14,15,15,15,15,15} //5GLB_N -[5G][A][+][ALL][1] = {0,1,2,2,3,4,4,5,6,6,7,7,8,9,9,10,11,11,12,13,14,15,16,16,17,17,18,18,18,18} //5GMA_P -[5G][A][-][ALL][1] = {0,1,2,2,3,4,5,5,6,6,7,7,8,8,9,10,10,11,11,12,12,13,13,14,14,14,14,14,14,14} //5GMA_N -[5G][B][+][ALL][1] = {0,1,2,2,3,4,5,6,6,7,8,8,9,9,10,11,12,12,13,14,15,16,17,17,18,18,18,18,18,18} //5GMB_P -[5G][B][-][ALL][1] = {0,1,1,2,2,3,3,4,5,5,6,7,7,8,8,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GMB_N -[5G][A][+][ALL][2] = {0,1,2,3,3,4,5,5,6,6,7,8,8,9,10,11,12,12,13,14,15,15,16,17,17,18,18,18,18,18} //5GHA_P -[5G][A][-][ALL][2] = {0,1,2,2,3,4,4,5,6,6,7,7,8,8,9,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GHA_N -[5G][B][+][ALL][2] = {0,1,2,2,3,4,5,5,6,6,7,8,8,9,10,10,11,12,13,14,15,15,16,16,17,17,17,17,17,17} //5GHB_P -[5G][B][-][ALL][2] = {0,1,2,2,3,3,4,4,5,6,6,7,7,8,9,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GHB_N +//rtl8822b version = 36 +//rtl8822b version = 29 +// +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKA_P +[2G][A][-][CCK] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GCCKA_N +[2G][B][+][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GCCKB_P +[2G][B][-][CCK] = {0,1,1,2,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,17,17,17,17,17,17,17,17} //2GCCKB_N +[2G][A][+][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,11,12,12,13,14,15,16,17,18,19,19,20,21,22,22,22} //2GA_P +[2G][A][-][ALL] = {0,1,2,3,3,4,5,6,6,7,8,9,10,11,12,13,13,14,15,16,17,18,18,18,18,18,18,18,18,18} //2GA_N +[2G][B][+][ALL] = {0,1,1,2,3,4,4,5,6,7,7,8,9,10,11,12,12,13,14,15,16,17,17,18,19,20,21,22,22,22} //2GB_P +[2G][B][-][ALL] = {0,1,2,3,3,4,4,5,6,7,8,9,10,11,12,13,13,14,15,16,16,17,18,18,18,18,18,18,18,18} //2GB_N +[5G][A][+][ALL][0] = {0,1,2,2,3,4,5,5,6,7,8,9,9,10,11,12,13,14,14,15,16,17,18,19,19,20,20,20,20,20} //5GLA_P +[5G][A][-][ALL][0] = {0,1,2,2,3,3,4,5,6,7,8,8,9,9,10,11,11,12,12,12,13,13,14,14,14,15,15,15,15,15} //5GLA_N +[5G][B][+][ALL][0] = {0,1,2,2,3,4,5,6,7,8,8,9,10,11,11,12,13,14,15,15,16,17,18,18,19,19,19,19,19,19} //5GLB_P +[5G][B][-][ALL][0] = {0,1,2,3,3,4,5,6,6,7,8,9,9,10,10,11,11,12,12,12,13,13,14,14,14,15,15,15,15,15} //5GLB_N +[5G][A][+][ALL][1] = {0,1,2,2,3,4,4,5,6,6,7,7,8,9,9,10,11,11,12,13,14,15,16,16,17,17,18,18,18,18} //5GMA_P +[5G][A][-][ALL][1] = {0,1,2,2,3,4,5,5,6,6,7,7,8,8,9,10,10,11,11,12,12,13,13,14,14,14,14,14,14,14} //5GMA_N +[5G][B][+][ALL][1] = {0,1,2,2,3,4,5,6,6,7,8,8,9,9,10,11,12,12,13,14,15,16,17,17,18,18,18,18,18,18} //5GMB_P +[5G][B][-][ALL][1] = {0,1,1,2,2,3,3,4,5,5,6,7,7,8,8,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GMB_N +[5G][A][+][ALL][2] = {0,1,2,3,3,4,5,5,6,6,7,8,8,9,10,11,12,12,13,14,15,15,16,17,17,18,18,18,18,18} //5GHA_P +[5G][A][-][ALL][2] = {0,1,2,2,3,4,4,5,6,6,7,7,8,8,9,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GHA_N +[5G][B][+][ALL][2] = {0,1,2,2,3,4,5,5,6,6,7,8,8,9,10,10,11,12,13,14,15,15,16,16,17,17,17,17,17,17} //5GHB_P +[5G][B][-][ALL][2] = {0,1,2,2,3,3,4,4,5,6,6,7,7,8,9,9,10,10,11,12,12,13,13,14,14,14,14,14,14,14} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/Version.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/Version.txt old mode 100755 new mode 100644 index 237a40b78c7..79468d5fe33 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/Version.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/Version.txt @@ -1 +1 @@ -CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 +CurrentVersion = RLE0572B_MAC_PHY_Parameter_v033_20140418 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/rtl8822Bfw.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/rtl8822Bfw.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8822B/rtl8822BfwMP.bin b/package/kernel/rtl8192cd/WlanHAL/Data/8822B/rtl8822BfwMP.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/AGC_TAB_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/AGC_TAB_8881A.txt old mode 100755 new mode 100644 index c9706cf01ec..6624e282503 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/AGC_TAB_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/AGC_TAB_8881A.txt @@ -1,131 +1,131 @@ -////Release version: RLE0547.0907.2012 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb41c0001 // Pin=-82dBm -0x81c 0xb31e0001 // Pin=-80dBm -0x81c 0xb2200001 // Pin=-78dBm -0x81c 0xb1220001 // Pin=-76dBm -0x81c 0xb0240001 // Pin=-74dBm -0x81c 0xaf260001 // Pin=-72dBm -0x81c 0xae280001 // Pin=-70dBm -0x81c 0xad2a0001 // Pin=-68dBm -0x81c 0xac2c0001 // Pin=-66dBm -0x81c 0xab2e0001 // Pin=-64dBm -0x81c 0xaa300001 // Pin=-62dBm -0x81c 0xa9320001 // Pin=-60dBm -0x81c 0xa8340001 // Pin=-58dBm -0x81c 0xa7360001 // Pin=-56dBm -0x81c 0xa6380001 // Pin=-54dBm -0x81c 0xa53a0001 // Pin=-52dBm -0x81c 0xa43c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G) -0x81c 0xfd800001 -0x81c 0xfc820001 -0x81c 0xfb840001 -0x81c 0xfa860001 -0x81c 0xf9880001 -0x81c 0xf88a0001 -0x81c 0xf78c0001 -0x81c 0xf68e0001 -0x81c 0xf5900001 // Pin=-94dBm -0x81c 0xf4920001 // Pin=-92dBm -0x81c 0xf3940001 // Pin=-90dBm -0x81c 0xf2960001 // Pin=-88dBm -0x81c 0xf1980001 // Pin=-86dBm -0x81c 0xf09a0001 // Pin=-84dBm -0x81c 0xef9c0001 // Pin=-82dBm -0x81c 0xee9e0001 // Pin=-80dBm -0x81c 0xeda00001 // Pin=-78dBm -0x81c 0xeca20001 // Pin=-76dBm -0x81c 0xeba40001 // Pin=-74dBm -0x81c 0xeaa60001 // Pin=-72dBm -0x81c 0xe9a80001 // Pin=-70dBm -0x81c 0xe8aa0001 // Pin=-68dBm -0x81c 0xe7ac0001 // Pin=-66dBm -0x81c 0xe6ae0001 // Pin=-64dBm -0x81c 0xc6b00001 // Pin=-62dBm -0x81c 0xc5b20001 // Pin=-60dBm -0x81c 0xa5b40001 // Pin=-58dBm -0x81c 0xa4b60001 // Pin=-56dBm -0x81c 0xa3b80001 // Pin=-54dBm -0x81c 0xa2ba0001 // Pin=-52dBm -0x81c 0xa1bc0001 // Pin=-50dBm -0x81c 0x65be0001 // Pin=-48dBm -0x81c 0x64c00001 // Pin=-46dBm -0x81c 0x63c20001 // Pin=-44dBm -0x81c 0x62c40001 // Pin=-42dBm -0x81c 0x61c60001 // Pin=-40dBm -0x81c 0x60c80001 // Pin=-38dBm -0x81c 0x60ca0001 // Pin=-36dBm -0x81c 0x60cc0001 // Pin=-34dBm -0x81c 0x60ce0001 // Pin=-32dBm -0x81c 0x60d00001 // Pin=-30dBm -0x81c 0x60d20001 // Pin=-28dBm -0x81c 0x60d40001 // Pin=-26dBm -0x81c 0x60d60001 // Pin=-24dBm -0x81c 0x60d80001 // Pin=-22dBm -0x81c 0x60da0001 // Pin=-20dBm -0x81c 0x60dc0001 // Pin=-18dBm -0x81c 0x60de0001 // Pin=-16dBm -0x81c 0x60e00001 // Pin=-14dBm -0x81c 0x60e20001 // Pin=-12dBm -0x81c 0x60e40001 // Pin=-10dBm -0x81c 0x60e60001 // Pin=-08dBm -0x81c 0x60e80001 // Pin=-06dBm -0x81c 0x60ea0001 // Pin=-04dBm -0x81c 0x60ec0001 // Pin=-02dBm -0x81c 0x60ee0001 // Pin=-00dBm -0x81c 0x60f00001 // Pin=+02dBm -0x81c 0x60f20001 // Pin=+04dBm -0x81c 0x60f40001 // Pin=+06dBm -0x81c 0x60f60001 // Pin=+08dBm -0x81c 0x60f80001 // Pin=+10dBm -0x81c 0x60fa0001 // Pin=+12dBm -0x81c 0x60fc0001 // Pin=+14dBm -0x81c 0x60fe0001 // Pin=+16dBm +////Release version: RLE0547.0907.2012 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb41c0001 // Pin=-82dBm +0x81c 0xb31e0001 // Pin=-80dBm +0x81c 0xb2200001 // Pin=-78dBm +0x81c 0xb1220001 // Pin=-76dBm +0x81c 0xb0240001 // Pin=-74dBm +0x81c 0xaf260001 // Pin=-72dBm +0x81c 0xae280001 // Pin=-70dBm +0x81c 0xad2a0001 // Pin=-68dBm +0x81c 0xac2c0001 // Pin=-66dBm +0x81c 0xab2e0001 // Pin=-64dBm +0x81c 0xaa300001 // Pin=-62dBm +0x81c 0xa9320001 // Pin=-60dBm +0x81c 0xa8340001 // Pin=-58dBm +0x81c 0xa7360001 // Pin=-56dBm +0x81c 0xa6380001 // Pin=-54dBm +0x81c 0xa53a0001 // Pin=-52dBm +0x81c 0xa43c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G) +0x81c 0xfd800001 +0x81c 0xfc820001 +0x81c 0xfb840001 +0x81c 0xfa860001 +0x81c 0xf9880001 +0x81c 0xf88a0001 +0x81c 0xf78c0001 +0x81c 0xf68e0001 +0x81c 0xf5900001 // Pin=-94dBm +0x81c 0xf4920001 // Pin=-92dBm +0x81c 0xf3940001 // Pin=-90dBm +0x81c 0xf2960001 // Pin=-88dBm +0x81c 0xf1980001 // Pin=-86dBm +0x81c 0xf09a0001 // Pin=-84dBm +0x81c 0xef9c0001 // Pin=-82dBm +0x81c 0xee9e0001 // Pin=-80dBm +0x81c 0xeda00001 // Pin=-78dBm +0x81c 0xeca20001 // Pin=-76dBm +0x81c 0xeba40001 // Pin=-74dBm +0x81c 0xeaa60001 // Pin=-72dBm +0x81c 0xe9a80001 // Pin=-70dBm +0x81c 0xe8aa0001 // Pin=-68dBm +0x81c 0xe7ac0001 // Pin=-66dBm +0x81c 0xe6ae0001 // Pin=-64dBm +0x81c 0xc6b00001 // Pin=-62dBm +0x81c 0xc5b20001 // Pin=-60dBm +0x81c 0xa5b40001 // Pin=-58dBm +0x81c 0xa4b60001 // Pin=-56dBm +0x81c 0xa3b80001 // Pin=-54dBm +0x81c 0xa2ba0001 // Pin=-52dBm +0x81c 0xa1bc0001 // Pin=-50dBm +0x81c 0x65be0001 // Pin=-48dBm +0x81c 0x64c00001 // Pin=-46dBm +0x81c 0x63c20001 // Pin=-44dBm +0x81c 0x62c40001 // Pin=-42dBm +0x81c 0x61c60001 // Pin=-40dBm +0x81c 0x60c80001 // Pin=-38dBm +0x81c 0x60ca0001 // Pin=-36dBm +0x81c 0x60cc0001 // Pin=-34dBm +0x81c 0x60ce0001 // Pin=-32dBm +0x81c 0x60d00001 // Pin=-30dBm +0x81c 0x60d20001 // Pin=-28dBm +0x81c 0x60d40001 // Pin=-26dBm +0x81c 0x60d60001 // Pin=-24dBm +0x81c 0x60d80001 // Pin=-22dBm +0x81c 0x60da0001 // Pin=-20dBm +0x81c 0x60dc0001 // Pin=-18dBm +0x81c 0x60de0001 // Pin=-16dBm +0x81c 0x60e00001 // Pin=-14dBm +0x81c 0x60e20001 // Pin=-12dBm +0x81c 0x60e40001 // Pin=-10dBm +0x81c 0x60e60001 // Pin=-08dBm +0x81c 0x60e80001 // Pin=-06dBm +0x81c 0x60ea0001 // Pin=-04dBm +0x81c 0x60ec0001 // Pin=-02dBm +0x81c 0x60ee0001 // Pin=-00dBm +0x81c 0x60f00001 // Pin=+02dBm +0x81c 0x60f20001 // Pin=+04dBm +0x81c 0x60f40001 // Pin=+06dBm +0x81c 0x60f60001 // Pin=+08dBm +0x81c 0x60f80001 // Pin=+10dBm +0x81c 0x60fa0001 // Pin=+12dBm +0x81c 0x60fc0001 // Pin=+14dBm +0x81c 0x60fe0001 // Pin=+16dBm 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/MAC_REG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/MAC_REG_8881A.txt old mode 100755 new mode 100644 index 6ab9f9ab987..dbe089204fa --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/MAC_REG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/MAC_REG_8881A.txt @@ -1,99 +1,99 @@ -////Release version: RTLE0538.0806.2012 -//0x010 0x0c // AFE power cut -//0x072 0x00 // AFE iso -//0x067 0x20 -//0x04F 0x01 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 +////Release version: RTLE0538.0806.2012 +//0x010 0x0c // AFE power cut +//0x072 0x00 // AFE iso +//0x067 0x20 +//0x04F 0x01 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_1T_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_1T_8881A.txt old mode 100755 new mode 100644 index 310bf04fceb..8ea9696824f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_1T_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_1T_8881A.txt @@ -1,230 +1,230 @@ -//Release version: RTL8188E.009.0105.2012 -//20111125 -0x24 0x37410421 //0x24[27]=1'b0 -//20111004 Alex -//0x24 038180f1 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x28 0xf2ffff82 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x40 0x00000004 //BT LO Leakage -//0x66 0x00040000 //110315 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x0220038e // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 //88E: 0x824[9]=1'b0 -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a11a9 //88E:R130 0x858[15:0]=16h11a9 //0x569a569a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60110 //88E:R133 0x860[14:12]=3'd0 //8723E default WiFi for 1 anatenna solution -0x864 0x061f0641 //88E:R130 0x864[15:0]=16'h0641 //0x061f0130 -0x868 0x00000000 -0x86c 0x27272700 //0x32323200 //Path-A 11M/5.5M/2M TX AGC codeword -0x870 0x07000760 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x25004000 // 0x874[27:24]=4'b0101 ADC Gain x 1 //0x22004000 -0x878 0x00000808 //88E:R130+R132 0x878[15:0]=16'h0808,0x878[31:16]=16'h0000 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // AFE ctrl reg (ASIC), 0x880[17]=1'b0 -0x884 0x00000001 // AFE ctrl reg (ASIC), 0x884[2:1]=0 -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -0x910 0x00000002 // 88E:RX_Status, Reg910[15:0]=16'd2 -0x914 0x00000100 // 88E:Antenna Diversity, 0x914[7:0]=0, 0x914[15:8]=1 -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e7f120f -0xa10 0x9500bb78 -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 //88E:R124+R127 RegA76=0x00,RegA77=0x00 -0xa78 0x00000900 //88E:R124+R127 RegA78=0x00,RegA79=0x09 -0xa7c 0x22c00606 //88E:R134 RegA7C=0x06,RegA7D=0x06,RegA7E=0xc0,RegA7F=0x22 -0xa80 0x21807531 //88E: CCK LNA 2 to 3 bit mapping, 0xa80[23]=1'b1. 0xa80[7]=1'b0, CCK agc_rpt as old format -//0xa80 0x21003210 //88E:R134 RegA80=0x10,RegA81=0x32,RegA82=0x00,RegA83=0x21 -// -//======================= -// PAGE_B -//======================= -0xb2c 0x80000000 //default LNA -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652af -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f //88E:R122 //0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69553420 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc0094 -0xc58 0x00003169 // simple agc settling time //0x00000967 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x00250492 // switch RXHP corner //0x00681492 //88E:R122+mantis2467 0xc5c[20:18]=3'd1, 0xc5c[23:21]=3'd1, 0xc5c[26:24]=3'd0 //0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b //by Gary -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //88E:R129 0xc6c[8:7]=0 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x020610db // 1st and 2nd BB PW time = 400ns //0x038610db -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 //0x1b00006c //BB Swing reduce to -7.5dB -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0x20200000 -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 //88E: 0xca4[10:0]=0xa0, 0xca4[22:12]=0x30 //0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00000740 //88E: supportL-byte)={11M 5.5M 2M 1M} -0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x001c1208 -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59799979? // for ADC/DAC clk gating -0xc6c 0x59795979 -0xc70 0x99795979 -0xc74 0x99795979 -0xc78 0x99799979 -0xc7c ?0x19799979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x00000000 -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77775754 // Ctrl 0-7 Selection -0xcb4 0x10000077 // Ctrl 8-9 Selection -0xcb8 0x00508240 - -//0x66 0xC8043007 -//0x4c 0x01628202 -//0x7c 0x000000c3 - +////Release version: RLE0547.0907.2012 +//======================= +// PAGE_8 +//======================= +0x800 0x0020d410 +0x804 0x080112e0 +0x808 0x0e028211 // cck_en=0 ofdm_en=0 +0x80c 0x12131111 +0x810 0x10101261 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa8e26 +0x834 0x0437a705 +0x838 0x06389b45 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x62103f8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31a12c2e +0x878 0x00000152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa0000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c005fff +0x8bc 0x8ca520a0 +0x8c0 0x01f00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x974 0x000003ff // RFE Output Pin +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x01081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00910000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +//0xa80 0x218075b2 +0xa80 0x21805490 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode +0xb00 0x03100000 // TMAC mode +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x001c1208 +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59799979? // for ADC/DAC clk gating +0xc6c 0x59795979 +0xc70 0x99795979 +0xc74 0x99795979 +0xc78 0x99799979 +0xc7c ?0x19799979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x00000000 +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77775754 // Ctrl 0-7 Selection +0xcb4 0x10000077 // Ctrl 8-9 Selection +0xcb8 0x00508240 + +//0x66 0xC8043007 +//0x4c 0x01628202 +//0x7c 0x000000c3 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_MP_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_MP_8881A.txt old mode 100755 new mode 100644 index 2a7c856b21e..0e380ded09c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_MP_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_MP_8881A.txt @@ -1,3 +1,3 @@ -//20100311 - +//20100311 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_PG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_PG_8881A.txt old mode 100755 new mode 100644 index 45d3c4093f9..cdbef2a7b37 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_PG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/PHY_REG_PG_8881A.txt @@ -1,144 +1,144 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= -//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -0xff //end of file +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= +//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +0xff //end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RTL8881FW_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RTL8881FW_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RTL8881TXBUF_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RTL8881TXBUF_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RadioA_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RadioA_8881A.txt old mode 100755 new mode 100644 index 3aa6750ede0..5683b3f6c79 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RadioA_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V700/RadioA_8881A.txt @@ -1,307 +1,307 @@ -////Release version: RLE0547.0907.2012 -//A MODE S0:5210 -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0xf8000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -//RX Gain Table // Should set 0x3A then 0x3B -0xEF 0x01000 -//LB -0x3A 0x000c4 //HG1 -0x3B 0x3a000 -0x3A 0x001fc //HG2 -0x3B 0x32000 -0x3A 0x001b4 //MG1 -0x3B 0x2a000 -0x3A 0x001c4 //MG2 -0x3B 0x221c8 -0x3A 0x00188 //LG0 -0x3B 0x1a001 -//MB -0x3A 0x000c4 //HG1 -0x3B 0x7a000 -0x3A 0x001fc //HG2 -0x3B 0x72000 -0x3A 0x001b4 //MG1 -0x3B 0x6a000 -0x3A 0x001c4 //MG2 -0x3B 0x621c8 -0x3A 0x00188 //LG0 -0x3B 0x5a001 -//HB -0x3A 0x000c4 //HG1 -0x3B 0xba000 -0x3A 0x001fc //HG2 -0x3B 0xb2000 -0x3A 0x001b4 //MG1 -0x3B 0xaa000 -0x3A 0x001c4 //MG2 -0x3B 0xa21c8 -0x3A 0x00188 //LG0 -0x3B 0x9a001 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF7 -0x34 0x49DF3 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46CCE -0x34 0x45CCB -0x34 0x4488D -0x34 0x4348D -0x34 0x4248A -0x34 0x4108D -0x34 0x4008A -//TX AGC 5GM -0x34 0x2ADF7 -0x34 0x29DF2 -0x34 0x28DEE -0x34 0x27DEB -0x34 0x26CCD -0x34 0x25CCA -0x34 0x2488C -0x34 0x2384C -0x34 0x22849 -0x34 0x21449 -0x34 0x2004D -//TX AGC 5GL -0x34 0x0ADF7 -0x34 0x09DF4 -0x34 0x08DD3 -0x34 0x07DD0 -0x34 0x06DCD -0x34 0x05CCD -0x34 0x04CCA -0x34 0x0388C -0x34 0x0288B -0x34 0x0148B -0x34 0x00489 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x20196 //MB 80M -0x35 0x28196 //MB 40M -0x35 0x30196 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x052B3 //LB 80M -0x36 0x0D2B3 //LB 40M -0x36 0x152B3 //non -0x36 0x1D2B3 //LB 20M -0x36 0x26634 //MB 80M -0x36 0x2E634 //MB 40M -0x36 0x36634 //non -0x36 0x3E634 //MB 20M -0x36 0x467B4 //HB 80M -0x36 0x4E7B4 //HB 40M -0x36 0x567B4 //non -0x36 0x5E7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00900 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0x01184 //LO leakage -0x59 0x6016C //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x710E7 -0x64 0x1A88C -0x65 0x91016 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB7 0x30008 -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x39258 //Gain 7 -0x3B 0x31258 //Gain 6 -0x3B 0x29258 //Gain 5 -0x3B 0x27a58 //Gain 4 xx have problem -0x3B 0x1fa58 //Gain 3 -0x3B 0x12590 //Gain 2 -0x3B 0x08248 //Gain 1 -0x3B 0x00a40 //Gain 0 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF0 -0x34 0x09DED -0x34 0x08DEA -0x34 0x07DE7 -0x34 0x06CEA -0x34 0x05CE7 -0x34 0x044EA -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x0006A -0xEF 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00160 -//0x45 0x08160 -//0x45 0x10160 - -//0x46 0x00124 -//0x46 0x08124 -//0x46 0x10124 -//0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F +////Release version: RLE0547.0907.2012 +//A MODE S0:5210 +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0xf8000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +//RX Gain Table // Should set 0x3A then 0x3B +0xEF 0x01000 +//LB +0x3A 0x000c4 //HG1 +0x3B 0x3a000 +0x3A 0x001fc //HG2 +0x3B 0x32000 +0x3A 0x001b4 //MG1 +0x3B 0x2a000 +0x3A 0x001c4 //MG2 +0x3B 0x221c8 +0x3A 0x00188 //LG0 +0x3B 0x1a001 +//MB +0x3A 0x000c4 //HG1 +0x3B 0x7a000 +0x3A 0x001fc //HG2 +0x3B 0x72000 +0x3A 0x001b4 //MG1 +0x3B 0x6a000 +0x3A 0x001c4 //MG2 +0x3B 0x621c8 +0x3A 0x00188 //LG0 +0x3B 0x5a001 +//HB +0x3A 0x000c4 //HG1 +0x3B 0xba000 +0x3A 0x001fc //HG2 +0x3B 0xb2000 +0x3A 0x001b4 //MG1 +0x3B 0xaa000 +0x3A 0x001c4 //MG2 +0x3B 0xa21c8 +0x3A 0x00188 //LG0 +0x3B 0x9a001 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF7 +0x34 0x49DF3 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46CCE +0x34 0x45CCB +0x34 0x4488D +0x34 0x4348D +0x34 0x4248A +0x34 0x4108D +0x34 0x4008A +//TX AGC 5GM +0x34 0x2ADF7 +0x34 0x29DF2 +0x34 0x28DEE +0x34 0x27DEB +0x34 0x26CCD +0x34 0x25CCA +0x34 0x2488C +0x34 0x2384C +0x34 0x22849 +0x34 0x21449 +0x34 0x2004D +//TX AGC 5GL +0x34 0x0ADF7 +0x34 0x09DF4 +0x34 0x08DD3 +0x34 0x07DD0 +0x34 0x06DCD +0x34 0x05CCD +0x34 0x04CCA +0x34 0x0388C +0x34 0x0288B +0x34 0x0148B +0x34 0x00489 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x20196 //MB 80M +0x35 0x28196 //MB 40M +0x35 0x30196 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x052B3 //LB 80M +0x36 0x0D2B3 //LB 40M +0x36 0x152B3 //non +0x36 0x1D2B3 //LB 20M +0x36 0x26634 //MB 80M +0x36 0x2E634 //MB 40M +0x36 0x36634 //non +0x36 0x3E634 //MB 20M +0x36 0x467B4 //HB 80M +0x36 0x4E7B4 //HB 40M +0x36 0x567B4 //non +0x36 0x5E7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00900 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0x01184 //LO leakage +0x59 0x6016C //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x710E7 +0x64 0x1A88C +0x65 0x91016 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB7 0x30008 +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x39258 //Gain 7 +0x3B 0x31258 //Gain 6 +0x3B 0x29258 //Gain 5 +0x3B 0x27a58 //Gain 4 xx have problem +0x3B 0x1fa58 //Gain 3 +0x3B 0x12590 //Gain 2 +0x3B 0x08248 //Gain 1 +0x3B 0x00a40 //Gain 0 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF0 +0x34 0x09DED +0x34 0x08DEA +0x34 0x07DE7 +0x34 0x06CEA +0x34 0x05CE7 +0x34 0x044EA +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x0006A +0xEF 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00160 +//0x45 0x08160 +//0x45 0x10160 + +//0x46 0x00124 +//0x46 0x08124 +//0x46 0x10124 +//0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/AGC_TAB_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/AGC_TAB_8881A.txt old mode 100755 new mode 100644 index c9706cf01ec..6624e282503 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/AGC_TAB_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/AGC_TAB_8881A.txt @@ -1,131 +1,131 @@ -////Release version: RLE0547.0907.2012 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb41c0001 // Pin=-82dBm -0x81c 0xb31e0001 // Pin=-80dBm -0x81c 0xb2200001 // Pin=-78dBm -0x81c 0xb1220001 // Pin=-76dBm -0x81c 0xb0240001 // Pin=-74dBm -0x81c 0xaf260001 // Pin=-72dBm -0x81c 0xae280001 // Pin=-70dBm -0x81c 0xad2a0001 // Pin=-68dBm -0x81c 0xac2c0001 // Pin=-66dBm -0x81c 0xab2e0001 // Pin=-64dBm -0x81c 0xaa300001 // Pin=-62dBm -0x81c 0xa9320001 // Pin=-60dBm -0x81c 0xa8340001 // Pin=-58dBm -0x81c 0xa7360001 // Pin=-56dBm -0x81c 0xa6380001 // Pin=-54dBm -0x81c 0xa53a0001 // Pin=-52dBm -0x81c 0xa43c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G) -0x81c 0xfd800001 -0x81c 0xfc820001 -0x81c 0xfb840001 -0x81c 0xfa860001 -0x81c 0xf9880001 -0x81c 0xf88a0001 -0x81c 0xf78c0001 -0x81c 0xf68e0001 -0x81c 0xf5900001 // Pin=-94dBm -0x81c 0xf4920001 // Pin=-92dBm -0x81c 0xf3940001 // Pin=-90dBm -0x81c 0xf2960001 // Pin=-88dBm -0x81c 0xf1980001 // Pin=-86dBm -0x81c 0xf09a0001 // Pin=-84dBm -0x81c 0xef9c0001 // Pin=-82dBm -0x81c 0xee9e0001 // Pin=-80dBm -0x81c 0xeda00001 // Pin=-78dBm -0x81c 0xeca20001 // Pin=-76dBm -0x81c 0xeba40001 // Pin=-74dBm -0x81c 0xeaa60001 // Pin=-72dBm -0x81c 0xe9a80001 // Pin=-70dBm -0x81c 0xe8aa0001 // Pin=-68dBm -0x81c 0xe7ac0001 // Pin=-66dBm -0x81c 0xe6ae0001 // Pin=-64dBm -0x81c 0xc6b00001 // Pin=-62dBm -0x81c 0xc5b20001 // Pin=-60dBm -0x81c 0xa5b40001 // Pin=-58dBm -0x81c 0xa4b60001 // Pin=-56dBm -0x81c 0xa3b80001 // Pin=-54dBm -0x81c 0xa2ba0001 // Pin=-52dBm -0x81c 0xa1bc0001 // Pin=-50dBm -0x81c 0x65be0001 // Pin=-48dBm -0x81c 0x64c00001 // Pin=-46dBm -0x81c 0x63c20001 // Pin=-44dBm -0x81c 0x62c40001 // Pin=-42dBm -0x81c 0x61c60001 // Pin=-40dBm -0x81c 0x60c80001 // Pin=-38dBm -0x81c 0x60ca0001 // Pin=-36dBm -0x81c 0x60cc0001 // Pin=-34dBm -0x81c 0x60ce0001 // Pin=-32dBm -0x81c 0x60d00001 // Pin=-30dBm -0x81c 0x60d20001 // Pin=-28dBm -0x81c 0x60d40001 // Pin=-26dBm -0x81c 0x60d60001 // Pin=-24dBm -0x81c 0x60d80001 // Pin=-22dBm -0x81c 0x60da0001 // Pin=-20dBm -0x81c 0x60dc0001 // Pin=-18dBm -0x81c 0x60de0001 // Pin=-16dBm -0x81c 0x60e00001 // Pin=-14dBm -0x81c 0x60e20001 // Pin=-12dBm -0x81c 0x60e40001 // Pin=-10dBm -0x81c 0x60e60001 // Pin=-08dBm -0x81c 0x60e80001 // Pin=-06dBm -0x81c 0x60ea0001 // Pin=-04dBm -0x81c 0x60ec0001 // Pin=-02dBm -0x81c 0x60ee0001 // Pin=-00dBm -0x81c 0x60f00001 // Pin=+02dBm -0x81c 0x60f20001 // Pin=+04dBm -0x81c 0x60f40001 // Pin=+06dBm -0x81c 0x60f60001 // Pin=+08dBm -0x81c 0x60f80001 // Pin=+10dBm -0x81c 0x60fa0001 // Pin=+12dBm -0x81c 0x60fc0001 // Pin=+14dBm -0x81c 0x60fe0001 // Pin=+16dBm +////Release version: RLE0547.0907.2012 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb41c0001 // Pin=-82dBm +0x81c 0xb31e0001 // Pin=-80dBm +0x81c 0xb2200001 // Pin=-78dBm +0x81c 0xb1220001 // Pin=-76dBm +0x81c 0xb0240001 // Pin=-74dBm +0x81c 0xaf260001 // Pin=-72dBm +0x81c 0xae280001 // Pin=-70dBm +0x81c 0xad2a0001 // Pin=-68dBm +0x81c 0xac2c0001 // Pin=-66dBm +0x81c 0xab2e0001 // Pin=-64dBm +0x81c 0xaa300001 // Pin=-62dBm +0x81c 0xa9320001 // Pin=-60dBm +0x81c 0xa8340001 // Pin=-58dBm +0x81c 0xa7360001 // Pin=-56dBm +0x81c 0xa6380001 // Pin=-54dBm +0x81c 0xa53a0001 // Pin=-52dBm +0x81c 0xa43c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G) +0x81c 0xfd800001 +0x81c 0xfc820001 +0x81c 0xfb840001 +0x81c 0xfa860001 +0x81c 0xf9880001 +0x81c 0xf88a0001 +0x81c 0xf78c0001 +0x81c 0xf68e0001 +0x81c 0xf5900001 // Pin=-94dBm +0x81c 0xf4920001 // Pin=-92dBm +0x81c 0xf3940001 // Pin=-90dBm +0x81c 0xf2960001 // Pin=-88dBm +0x81c 0xf1980001 // Pin=-86dBm +0x81c 0xf09a0001 // Pin=-84dBm +0x81c 0xef9c0001 // Pin=-82dBm +0x81c 0xee9e0001 // Pin=-80dBm +0x81c 0xeda00001 // Pin=-78dBm +0x81c 0xeca20001 // Pin=-76dBm +0x81c 0xeba40001 // Pin=-74dBm +0x81c 0xeaa60001 // Pin=-72dBm +0x81c 0xe9a80001 // Pin=-70dBm +0x81c 0xe8aa0001 // Pin=-68dBm +0x81c 0xe7ac0001 // Pin=-66dBm +0x81c 0xe6ae0001 // Pin=-64dBm +0x81c 0xc6b00001 // Pin=-62dBm +0x81c 0xc5b20001 // Pin=-60dBm +0x81c 0xa5b40001 // Pin=-58dBm +0x81c 0xa4b60001 // Pin=-56dBm +0x81c 0xa3b80001 // Pin=-54dBm +0x81c 0xa2ba0001 // Pin=-52dBm +0x81c 0xa1bc0001 // Pin=-50dBm +0x81c 0x65be0001 // Pin=-48dBm +0x81c 0x64c00001 // Pin=-46dBm +0x81c 0x63c20001 // Pin=-44dBm +0x81c 0x62c40001 // Pin=-42dBm +0x81c 0x61c60001 // Pin=-40dBm +0x81c 0x60c80001 // Pin=-38dBm +0x81c 0x60ca0001 // Pin=-36dBm +0x81c 0x60cc0001 // Pin=-34dBm +0x81c 0x60ce0001 // Pin=-32dBm +0x81c 0x60d00001 // Pin=-30dBm +0x81c 0x60d20001 // Pin=-28dBm +0x81c 0x60d40001 // Pin=-26dBm +0x81c 0x60d60001 // Pin=-24dBm +0x81c 0x60d80001 // Pin=-22dBm +0x81c 0x60da0001 // Pin=-20dBm +0x81c 0x60dc0001 // Pin=-18dBm +0x81c 0x60de0001 // Pin=-16dBm +0x81c 0x60e00001 // Pin=-14dBm +0x81c 0x60e20001 // Pin=-12dBm +0x81c 0x60e40001 // Pin=-10dBm +0x81c 0x60e60001 // Pin=-08dBm +0x81c 0x60e80001 // Pin=-06dBm +0x81c 0x60ea0001 // Pin=-04dBm +0x81c 0x60ec0001 // Pin=-02dBm +0x81c 0x60ee0001 // Pin=-00dBm +0x81c 0x60f00001 // Pin=+02dBm +0x81c 0x60f20001 // Pin=+04dBm +0x81c 0x60f40001 // Pin=+06dBm +0x81c 0x60f60001 // Pin=+08dBm +0x81c 0x60f80001 // Pin=+10dBm +0x81c 0x60fa0001 // Pin=+12dBm +0x81c 0x60fc0001 // Pin=+14dBm +0x81c 0x60fe0001 // Pin=+16dBm 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/MAC_REG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/MAC_REG_8881A.txt old mode 100755 new mode 100644 index 6ab9f9ab987..dbe089204fa --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/MAC_REG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/MAC_REG_8881A.txt @@ -1,99 +1,99 @@ -////Release version: RTLE0538.0806.2012 -//0x010 0x0c // AFE power cut -//0x072 0x00 // AFE iso -//0x067 0x20 -//0x04F 0x01 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 +////Release version: RTLE0538.0806.2012 +//0x010 0x0c // AFE power cut +//0x072 0x00 // AFE iso +//0x067 0x20 +//0x04F 0x01 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_1T_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_1T_8881A.txt old mode 100755 new mode 100644 index 310bf04fceb..8ea9696824f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_1T_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_1T_8881A.txt @@ -1,230 +1,230 @@ -//Release version: RTL8188E.009.0105.2012 -//20111125 -0x24 0x37410421 //0x24[27]=1'b0 -//20111004 Alex -//0x24 038180f1 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x28 0xf2ffff82 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x40 0x00000004 //BT LO Leakage -//0x66 0x00040000 //110315 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x0220038e // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 //88E: 0x824[9]=1'b0 -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a11a9 //88E:R130 0x858[15:0]=16h11a9 //0x569a569a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60110 //88E:R133 0x860[14:12]=3'd0 //8723E default WiFi for 1 anatenna solution -0x864 0x061f0641 //88E:R130 0x864[15:0]=16'h0641 //0x061f0130 -0x868 0x00000000 -0x86c 0x27272700 //0x32323200 //Path-A 11M/5.5M/2M TX AGC codeword -0x870 0x07000760 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x25004000 // 0x874[27:24]=4'b0101 ADC Gain x 1 //0x22004000 -0x878 0x00000808 //88E:R130+R132 0x878[15:0]=16'h0808,0x878[31:16]=16'h0000 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // AFE ctrl reg (ASIC), 0x880[17]=1'b0 -0x884 0x00000001 // AFE ctrl reg (ASIC), 0x884[2:1]=0 -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -0x910 0x00000002 // 88E:RX_Status, Reg910[15:0]=16'd2 -0x914 0x00000100 // 88E:Antenna Diversity, 0x914[7:0]=0, 0x914[15:8]=1 -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e7f120f -0xa10 0x9500bb78 -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 //88E:R124+R127 RegA76=0x00,RegA77=0x00 -0xa78 0x00000900 //88E:R124+R127 RegA78=0x00,RegA79=0x09 -0xa7c 0x22c00606 //88E:R134 RegA7C=0x06,RegA7D=0x06,RegA7E=0xc0,RegA7F=0x22 -0xa80 0x21807531 //88E: CCK LNA 2 to 3 bit mapping, 0xa80[23]=1'b1. 0xa80[7]=1'b0, CCK agc_rpt as old format -//0xa80 0x21003210 //88E:R134 RegA80=0x10,RegA81=0x32,RegA82=0x00,RegA83=0x21 -// -//======================= -// PAGE_B -//======================= -0xb2c 0x80000000 //default LNA -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652af -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f //88E:R122 //0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69553420 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc0094 -0xc58 0x00003169 // simple agc settling time //0x00000967 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x00250492 // switch RXHP corner //0x00681492 //88E:R122+mantis2467 0xc5c[20:18]=3'd1, 0xc5c[23:21]=3'd1, 0xc5c[26:24]=3'd0 //0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b //by Gary -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //88E:R129 0xc6c[8:7]=0 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x020610db // 1st and 2nd BB PW time = 400ns //0x038610db -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 //0x1b00006c //BB Swing reduce to -7.5dB -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0x20200000 -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 //88E: 0xca4[10:0]=0xa0, 0xca4[22:12]=0x30 //0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00000740 //88E: supportL-byte)={11M 5.5M 2M 1M} -0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x001c1208 -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59799979? // for ADC/DAC clk gating -0xc6c 0x59795979 -0xc70 0x99795979 -0xc74 0x99795979 -0xc78 0x99799979 -0xc7c 0x19799979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x00000000 -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77775754 // Ctrl 0-7 Selection -0xcb4 0x10000077 // Ctrl 8-9 Selection -0xcb8 0x00508240 - -//0x66 0xC8043007 -//0x4c 0x01628202 -//0x7c 0x000000c3 - +////Release version: RLE0547.1031.2012 +//======================= +// PAGE_8 +//======================= +0x800 0x0020d410 +0x804 0x080112e0 +0x808 0x0e028211 // cck_en=0 ofdm_en=0 +0x80c 0x12131111 +0x810 0x20101261 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa8e26 +0x834 0x0437a705 +0x838 0x06389b45 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x62103f8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31612c2e +0x878 0x00000152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa0000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c005fff +0x8bc 0x8ca520a0 +0x8c0 0x01f00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x974 0x000003ff // RFE Output Pin +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x01081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00910000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +//0xa80 0x218075b2 +0xa80 0x21805490 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode +0xb00 0x03100000 // TMAC mode +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x001c1208 +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59799979? // for ADC/DAC clk gating +0xc6c 0x59795979 +0xc70 0x99795979 +0xc74 0x99795979 +0xc78 0x99799979 +0xc7c 0x19799979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x00000000 +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77775754 // Ctrl 0-7 Selection +0xcb4 0x10000077 // Ctrl 8-9 Selection +0xcb8 0x00508240 + +//0x66 0xC8043007 +//0x4c 0x01628202 +//0x7c 0x000000c3 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_MP_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_MP_8881A.txt old mode 100755 new mode 100644 index 2a7c856b21e..0e380ded09c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_MP_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_MP_8881A.txt @@ -1,3 +1,3 @@ -//20100311 - +//20100311 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_PG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_PG_8881A.txt old mode 100755 new mode 100644 index 45d3c4093f9..cdbef2a7b37 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_PG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/PHY_REG_PG_8881A.txt @@ -1,144 +1,144 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= -//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -0xff //end of file +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= +//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +0xff //end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RTL8881FW_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RTL8881FW_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RTL8881TXBUF_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RTL8881TXBUF_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RadioA_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RadioA_8881A.txt old mode 100755 new mode 100644 index 3aa6750ede0..5683b3f6c79 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RadioA_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B/RadioA_8881A.txt @@ -1,307 +1,307 @@ -////Release version: RLE0547.0907.2012 -//A MODE S0:5210 -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0xf8000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -//RX Gain Table // Should set 0x3A then 0x3B -0xEF 0x01000 -//LB -0x3A 0x000c4 //HG1 -0x3B 0x3a000 -0x3A 0x001fc //HG2 -0x3B 0x32000 -0x3A 0x001b4 //MG1 -0x3B 0x2a000 -0x3A 0x001c4 //MG2 -0x3B 0x221c8 -0x3A 0x00188 //LG0 -0x3B 0x1a001 -//MB -0x3A 0x000c4 //HG1 -0x3B 0x7a000 -0x3A 0x001fc //HG2 -0x3B 0x72000 -0x3A 0x001b4 //MG1 -0x3B 0x6a000 -0x3A 0x001c4 //MG2 -0x3B 0x621c8 -0x3A 0x00188 //LG0 -0x3B 0x5a001 -//HB -0x3A 0x000c4 //HG1 -0x3B 0xba000 -0x3A 0x001fc //HG2 -0x3B 0xb2000 -0x3A 0x001b4 //MG1 -0x3B 0xaa000 -0x3A 0x001c4 //MG2 -0x3B 0xa21c8 -0x3A 0x00188 //LG0 -0x3B 0x9a001 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF7 -0x34 0x49DF3 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46CCE -0x34 0x45CCB -0x34 0x4488D -0x34 0x4348D -0x34 0x4248A -0x34 0x4108D -0x34 0x4008A -//TX AGC 5GM -0x34 0x2ADF7 -0x34 0x29DF2 -0x34 0x28DEE -0x34 0x27DEB -0x34 0x26CCD -0x34 0x25CCA -0x34 0x2488C -0x34 0x2384C -0x34 0x22849 -0x34 0x21449 -0x34 0x2004D -//TX AGC 5GL -0x34 0x0ADF7 -0x34 0x09DF4 -0x34 0x08DD3 -0x34 0x07DD0 -0x34 0x06DCD -0x34 0x05CCD -0x34 0x04CCA -0x34 0x0388C -0x34 0x0288B -0x34 0x0148B -0x34 0x00489 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x20196 //MB 80M -0x35 0x28196 //MB 40M -0x35 0x30196 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x052B3 //LB 80M -0x36 0x0D2B3 //LB 40M -0x36 0x152B3 //non -0x36 0x1D2B3 //LB 20M -0x36 0x26634 //MB 80M -0x36 0x2E634 //MB 40M -0x36 0x36634 //non -0x36 0x3E634 //MB 20M -0x36 0x467B4 //HB 80M -0x36 0x4E7B4 //HB 40M -0x36 0x567B4 //non -0x36 0x5E7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00900 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0x01184 //LO leakage -0x59 0x6016C //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x710E7 -0x64 0x1A88C -0x65 0x91016 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB7 0x30008 -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x39258 //Gain 7 -0x3B 0x31258 //Gain 6 -0x3B 0x29258 //Gain 5 -0x3B 0x27a58 //Gain 4 xx have problem -0x3B 0x1fa58 //Gain 3 -0x3B 0x12590 //Gain 2 -0x3B 0x08248 //Gain 1 -0x3B 0x00a40 //Gain 0 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF0 -0x34 0x09DED -0x34 0x08DEA -0x34 0x07DE7 -0x34 0x06CEA -0x34 0x05CE7 -0x34 0x044EA -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x0006A -0xEF 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00160 -//0x45 0x08160 -//0x45 0x10160 - -//0x46 0x00124 -//0x46 0x08124 -//0x46 0x10124 -//0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F +////Release version: RLE0547.0907.2012 +//A MODE S0:5210 +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0xf8000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +//RX Gain Table // Should set 0x3A then 0x3B +0xEF 0x01000 +//LB +0x3A 0x000c4 //HG1 +0x3B 0x3a000 +0x3A 0x001fc //HG2 +0x3B 0x32000 +0x3A 0x001b4 //MG1 +0x3B 0x2a000 +0x3A 0x001c4 //MG2 +0x3B 0x221c8 +0x3A 0x00188 //LG0 +0x3B 0x1a001 +//MB +0x3A 0x000c4 //HG1 +0x3B 0x7a000 +0x3A 0x001fc //HG2 +0x3B 0x72000 +0x3A 0x001b4 //MG1 +0x3B 0x6a000 +0x3A 0x001c4 //MG2 +0x3B 0x621c8 +0x3A 0x00188 //LG0 +0x3B 0x5a001 +//HB +0x3A 0x000c4 //HG1 +0x3B 0xba000 +0x3A 0x001fc //HG2 +0x3B 0xb2000 +0x3A 0x001b4 //MG1 +0x3B 0xaa000 +0x3A 0x001c4 //MG2 +0x3B 0xa21c8 +0x3A 0x00188 //LG0 +0x3B 0x9a001 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF7 +0x34 0x49DF3 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46CCE +0x34 0x45CCB +0x34 0x4488D +0x34 0x4348D +0x34 0x4248A +0x34 0x4108D +0x34 0x4008A +//TX AGC 5GM +0x34 0x2ADF7 +0x34 0x29DF2 +0x34 0x28DEE +0x34 0x27DEB +0x34 0x26CCD +0x34 0x25CCA +0x34 0x2488C +0x34 0x2384C +0x34 0x22849 +0x34 0x21449 +0x34 0x2004D +//TX AGC 5GL +0x34 0x0ADF7 +0x34 0x09DF4 +0x34 0x08DD3 +0x34 0x07DD0 +0x34 0x06DCD +0x34 0x05CCD +0x34 0x04CCA +0x34 0x0388C +0x34 0x0288B +0x34 0x0148B +0x34 0x00489 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x20196 //MB 80M +0x35 0x28196 //MB 40M +0x35 0x30196 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x052B3 //LB 80M +0x36 0x0D2B3 //LB 40M +0x36 0x152B3 //non +0x36 0x1D2B3 //LB 20M +0x36 0x26634 //MB 80M +0x36 0x2E634 //MB 40M +0x36 0x36634 //non +0x36 0x3E634 //MB 20M +0x36 0x467B4 //HB 80M +0x36 0x4E7B4 //HB 40M +0x36 0x567B4 //non +0x36 0x5E7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00900 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0x01184 //LO leakage +0x59 0x6016C //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x710E7 +0x64 0x1A88C +0x65 0x91016 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB7 0x30008 +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x39258 //Gain 7 +0x3B 0x31258 //Gain 6 +0x3B 0x29258 //Gain 5 +0x3B 0x27a58 //Gain 4 xx have problem +0x3B 0x1fa58 //Gain 3 +0x3B 0x12590 //Gain 2 +0x3B 0x08248 //Gain 1 +0x3B 0x00a40 //Gain 0 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF0 +0x34 0x09DED +0x34 0x08DEA +0x34 0x07DE7 +0x34 0x06CEA +0x34 0x05CE7 +0x34 0x044EA +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x0006A +0xEF 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00160 +//0x45 0x08160 +//0x45 0x10160 + +//0x46 0x00124 +//0x46 0x08124 +//0x46 0x10124 +//0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP.txt index 8a89dcdfea1..501c62c69fb 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfb000101 // Pin=-110dBm -0x81c 0xfa020101 // Pin=-108dBm -0x81c 0xf9040101 // Pin=-106dBm -0x81c 0xf8060101 // Pin=-104dBm -0x81c 0xf7080101 // Pin=-102dBm -0x81c 0xf60a0101 // Pin=-100dBm -0x81c 0xf50c0101 // Pin=-98dBm -0x81c 0xf40e0101 // Pin=-96dBm -0x81c 0xf3100101 // Pin=-94dBm -0x81c 0xf2120101 // Pin=-92dBm -0x81c 0xf1140101 // Pin=-90dBm -0x81c 0xf0160101 // Pin=-88dBm -0x81c 0xef180101 // Pin=-86dBm -0x81c 0xee1a0101 // Pin=-84dBm -0x81c 0xed1c0101 // Pin=-82dBm -0x81c 0xec1e0101 // Pin=-80dBm -0x81c 0xeb200101 // Pin=-78dBm -0x81c 0xea220101 // Pin=-76dBm -0x81c 0xe9240101 // Pin=-74dBm -0x81c 0xe8260101 // Pin=-72dBm -0x81c 0xe7280101 // Pin=-70dBm -0x81c 0xe62a0101 // Pin=-68dBm -0x81c 0xe52c0101 // Pin=-66dBm -0x81c 0xe42e0101 // Pin=-64dBm -0x81c 0xe3300101 // Pin=-62dBm -0x81c 0xe2320101 // Pin=-60dBm -0x81c 0xa3340101 // Pin=-58dBm -0x81c 0xa2360101 // Pin=-56dBm -0x81c 0xa1380101 // Pin=-54dBm -0x81c 0x863a0101 // Pin=-52dBm -0x81c 0x853c0101 // Pin=-50dBm -0x81c 0x843e0101 // Pin=-48dBm -0x81c 0x83400101 // Pin=-46dBm -0x81c 0x66420101 // Pin=-44dBm -0x81c 0x65440101 // Pin=-42dBm -0x81c 0x64460101 // Pin=-40dBm -0x81c 0x63480101 // Pin=-38dBm -0x81c 0x624a0101 // Pin=-36dBm -0x81c 0x2a4c0101 // Pin=-34dBm -0x81c 0x294e0101 // Pin=-32dBm -0x81c 0x28500101 // Pin=-30dBm -0x81c 0x27520101 // Pin=-28dBm -0x81c 0x26540101 // Pin=-26dBm -0x81c 0x25560101 // Pin=-24dBm -0x81c 0x24580101 // Pin=-22dBm -0x81c 0x235a0101 // Pin=-20dBm -0x81c 0x225c0101 // Pin=-18dBm -0x81c 0x215e0101 // Pin=-16dBm -0x81c 0x05600101 // Pin=-14dBm -0x81c 0x04620101 // Pin=-12dBm -0x81c 0x03640101 // Pin=-10dBm -0x81c 0x02660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xfa000201 // Pin=-110dBm -0x81c 0xf9020201 // Pin=-108dBm -0x81c 0xf8040201 // Pin=-106dBm -0x81c 0xf7060201 // Pin=-104dBm -0x81c 0xf6080201 // Pin=-102dBm -0x81c 0xf50a0201 // Pin=-100dBm -0x81c 0xf40c0201 // Pin=-98dBm -0x81c 0xf30e0201 // Pin=-96dBm -0x81c 0xf2100201 // Pin=-94dBm -0x81c 0xf1120201 // Pin=-92dBm -0x81c 0xf0140201 // Pin=-90dBm -0x81c 0xef160201 // Pin=-88dBm -0x81c 0xee180201 // Pin=-86dBm -0x81c 0xed1a0201 // Pin=-84dBm -0x81c 0xec1c0201 // Pin=-82dBm -0x81c 0xeb1e0201 // Pin=-80dBm -0x81c 0xea200201 // Pin=-78dBm -0x81c 0xe9220201 // Pin=-76dBm -0x81c 0xe8240201 // Pin=-74dBm -0x81c 0xe7260201 // Pin=-72dBm -0x81c 0xe6280201 // Pin=-70dBm -0x81c 0xe52a0201 // Pin=-68dBm -0x81c 0xe42c0201 // Pin=-66dBm -0x81c 0xe32e0201 // Pin=-64dBm -0x81c 0xe2300201 // Pin=-62dBm -0x81c 0xa3320201 // Pin=-60dBm -0x81c 0xa2340201 // Pin=-58dBm -0x81c 0xa1360201 // Pin=-56dBm -0x81c 0x86380201 // Pin=-54dBm -0x81c 0x853a0201 // Pin=-52dBm -0x81c 0x843c0201 // Pin=-50dBm -0x81c 0x833e0201 // Pin=-48dBm -0x81c 0x68400201 // Pin=-46dBm -0x81c 0x67420201 // Pin=-44dBm -0x81c 0x66440201 // Pin=-42dBm -0x81c 0x65460201 // Pin=-40dBm -0x81c 0x64480201 // Pin=-38dBm -0x81c 0x634a0201 // Pin=-36dBm -0x81c 0x624c0201 // Pin=-34dBm -0x81c 0x284e0201 // Pin=-32dBm -0x81c 0x27500201 // Pin=-30dBm -0x81c 0x26520201 // Pin=-28dBm -0x81c 0x25540201 // Pin=-26dBm -0x81c 0x24560201 // Pin=-24dBm -0x81c 0x23580201 // Pin=-22dBm -0x81c 0x225a0201 // Pin=-20dBm -0x81c 0x215c0201 // Pin=-18dBm -0x81c 0x055e0201 // Pin=-16dBm -0x81c 0x04600201 // Pin=-14dBm -0x81c 0x03620201 // Pin=-12dBm -0x81c 0x02640201 // Pin=-10dBm -0x81c 0x01660201 // Pin=-08dBm -0x81c 0x01680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xf9000301 // Pin=-110dBm -0x81c 0xf8020301 // Pin=-108dBm -0x81c 0xf7040301 // Pin=-106dBm -0x81c 0xf6060301 // Pin=-104dBm -0x81c 0xf5080301 // Pin=-102dBm -0x81c 0xf40a0301 // Pin=-100dBm -0x81c 0xf30c0301 // Pin=-98dBm -0x81c 0xf20e0301 // Pin=-96dBm -0x81c 0xf1100301 // Pin=-94dBm -0x81c 0xf0120301 // Pin=-92dBm -0x81c 0xef140301 // Pin=-90dBm -0x81c 0xee160301 // Pin=-88dBm -0x81c 0xed180301 // Pin=-86dBm -0x81c 0xec1a0301 // Pin=-84dBm -0x81c 0xeb1c0301 // Pin=-82dBm -0x81c 0xea1e0301 // Pin=-80dBm -0x81c 0xe9200301 // Pin=-78dBm -0x81c 0xe8220301 // Pin=-76dBm -0x81c 0xe7240301 // Pin=-74dBm -0x81c 0xe6260301 // Pin=-72dBm -0x81c 0xe5280301 // Pin=-70dBm -0x81c 0xe42a0301 // Pin=-68dBm -0x81c 0xe32c0301 // Pin=-66dBm -0x81c 0xa42e0301 // Pin=-64dBm -0x81c 0xa3300301 // Pin=-62dBm -0x81c 0xa2320301 // Pin=-60dBm -0x81c 0x89340301 // Pin=-58dBm -0x81c 0x88360301 // Pin=-56dBm -0x81c 0x87380301 // Pin=-54dBm -0x81c 0x863a0301 // Pin=-52dBm -0x81c 0x6a3c0301 // Pin=-50dBm -0x81c 0x693e0301 // Pin=-48dBm -0x81c 0x68400301 // Pin=-46dBm -0x81c 0x67420301 // Pin=-44dBm -0x81c 0x66440301 // Pin=-42dBm -0x81c 0x65460301 // Pin=-40dBm -0x81c 0x64480301 // Pin=-38dBm -0x81c 0x284a0301 // Pin=-36dBm -0x81c 0x274c0301 // Pin=-34dBm -0x81c 0x264e0301 // Pin=-32dBm -0x81c 0x25500301 // Pin=-30dBm -0x81c 0x24520301 // Pin=-28dBm -0x81c 0x23540301 // Pin=-26dBm -0x81c 0x22560301 // Pin=-24dBm -0x81c 0x21580301 // Pin=-22dBm -0x81c 0x055a0301 // Pin=-20dBm -0x81c 0x045c0301 // Pin=-18dBm -0x81c 0x035e0301 // Pin=-16dBm -0x81c 0x02600301 // Pin=-14dBm -0x81c 0x01620301 // Pin=-12dBm -0x81c 0x01640301 // Pin=-10dBm -0x81c 0x01660301 // Pin=-08dBm -0x81c 0x01680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfb000101 // Pin=-110dBm +0x81c 0xfa020101 // Pin=-108dBm +0x81c 0xf9040101 // Pin=-106dBm +0x81c 0xf8060101 // Pin=-104dBm +0x81c 0xf7080101 // Pin=-102dBm +0x81c 0xf60a0101 // Pin=-100dBm +0x81c 0xf50c0101 // Pin=-98dBm +0x81c 0xf40e0101 // Pin=-96dBm +0x81c 0xf3100101 // Pin=-94dBm +0x81c 0xf2120101 // Pin=-92dBm +0x81c 0xf1140101 // Pin=-90dBm +0x81c 0xf0160101 // Pin=-88dBm +0x81c 0xef180101 // Pin=-86dBm +0x81c 0xee1a0101 // Pin=-84dBm +0x81c 0xed1c0101 // Pin=-82dBm +0x81c 0xec1e0101 // Pin=-80dBm +0x81c 0xeb200101 // Pin=-78dBm +0x81c 0xea220101 // Pin=-76dBm +0x81c 0xe9240101 // Pin=-74dBm +0x81c 0xe8260101 // Pin=-72dBm +0x81c 0xe7280101 // Pin=-70dBm +0x81c 0xe62a0101 // Pin=-68dBm +0x81c 0xe52c0101 // Pin=-66dBm +0x81c 0xe42e0101 // Pin=-64dBm +0x81c 0xe3300101 // Pin=-62dBm +0x81c 0xe2320101 // Pin=-60dBm +0x81c 0xa3340101 // Pin=-58dBm +0x81c 0xa2360101 // Pin=-56dBm +0x81c 0xa1380101 // Pin=-54dBm +0x81c 0x863a0101 // Pin=-52dBm +0x81c 0x853c0101 // Pin=-50dBm +0x81c 0x843e0101 // Pin=-48dBm +0x81c 0x83400101 // Pin=-46dBm +0x81c 0x66420101 // Pin=-44dBm +0x81c 0x65440101 // Pin=-42dBm +0x81c 0x64460101 // Pin=-40dBm +0x81c 0x63480101 // Pin=-38dBm +0x81c 0x624a0101 // Pin=-36dBm +0x81c 0x2a4c0101 // Pin=-34dBm +0x81c 0x294e0101 // Pin=-32dBm +0x81c 0x28500101 // Pin=-30dBm +0x81c 0x27520101 // Pin=-28dBm +0x81c 0x26540101 // Pin=-26dBm +0x81c 0x25560101 // Pin=-24dBm +0x81c 0x24580101 // Pin=-22dBm +0x81c 0x235a0101 // Pin=-20dBm +0x81c 0x225c0101 // Pin=-18dBm +0x81c 0x215e0101 // Pin=-16dBm +0x81c 0x05600101 // Pin=-14dBm +0x81c 0x04620101 // Pin=-12dBm +0x81c 0x03640101 // Pin=-10dBm +0x81c 0x02660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xfa000201 // Pin=-110dBm +0x81c 0xf9020201 // Pin=-108dBm +0x81c 0xf8040201 // Pin=-106dBm +0x81c 0xf7060201 // Pin=-104dBm +0x81c 0xf6080201 // Pin=-102dBm +0x81c 0xf50a0201 // Pin=-100dBm +0x81c 0xf40c0201 // Pin=-98dBm +0x81c 0xf30e0201 // Pin=-96dBm +0x81c 0xf2100201 // Pin=-94dBm +0x81c 0xf1120201 // Pin=-92dBm +0x81c 0xf0140201 // Pin=-90dBm +0x81c 0xef160201 // Pin=-88dBm +0x81c 0xee180201 // Pin=-86dBm +0x81c 0xed1a0201 // Pin=-84dBm +0x81c 0xec1c0201 // Pin=-82dBm +0x81c 0xeb1e0201 // Pin=-80dBm +0x81c 0xea200201 // Pin=-78dBm +0x81c 0xe9220201 // Pin=-76dBm +0x81c 0xe8240201 // Pin=-74dBm +0x81c 0xe7260201 // Pin=-72dBm +0x81c 0xe6280201 // Pin=-70dBm +0x81c 0xe52a0201 // Pin=-68dBm +0x81c 0xe42c0201 // Pin=-66dBm +0x81c 0xe32e0201 // Pin=-64dBm +0x81c 0xe2300201 // Pin=-62dBm +0x81c 0xa3320201 // Pin=-60dBm +0x81c 0xa2340201 // Pin=-58dBm +0x81c 0xa1360201 // Pin=-56dBm +0x81c 0x86380201 // Pin=-54dBm +0x81c 0x853a0201 // Pin=-52dBm +0x81c 0x843c0201 // Pin=-50dBm +0x81c 0x833e0201 // Pin=-48dBm +0x81c 0x68400201 // Pin=-46dBm +0x81c 0x67420201 // Pin=-44dBm +0x81c 0x66440201 // Pin=-42dBm +0x81c 0x65460201 // Pin=-40dBm +0x81c 0x64480201 // Pin=-38dBm +0x81c 0x634a0201 // Pin=-36dBm +0x81c 0x624c0201 // Pin=-34dBm +0x81c 0x284e0201 // Pin=-32dBm +0x81c 0x27500201 // Pin=-30dBm +0x81c 0x26520201 // Pin=-28dBm +0x81c 0x25540201 // Pin=-26dBm +0x81c 0x24560201 // Pin=-24dBm +0x81c 0x23580201 // Pin=-22dBm +0x81c 0x225a0201 // Pin=-20dBm +0x81c 0x215c0201 // Pin=-18dBm +0x81c 0x055e0201 // Pin=-16dBm +0x81c 0x04600201 // Pin=-14dBm +0x81c 0x03620201 // Pin=-12dBm +0x81c 0x02640201 // Pin=-10dBm +0x81c 0x01660201 // Pin=-08dBm +0x81c 0x01680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xf9000301 // Pin=-110dBm +0x81c 0xf8020301 // Pin=-108dBm +0x81c 0xf7040301 // Pin=-106dBm +0x81c 0xf6060301 // Pin=-104dBm +0x81c 0xf5080301 // Pin=-102dBm +0x81c 0xf40a0301 // Pin=-100dBm +0x81c 0xf30c0301 // Pin=-98dBm +0x81c 0xf20e0301 // Pin=-96dBm +0x81c 0xf1100301 // Pin=-94dBm +0x81c 0xf0120301 // Pin=-92dBm +0x81c 0xef140301 // Pin=-90dBm +0x81c 0xee160301 // Pin=-88dBm +0x81c 0xed180301 // Pin=-86dBm +0x81c 0xec1a0301 // Pin=-84dBm +0x81c 0xeb1c0301 // Pin=-82dBm +0x81c 0xea1e0301 // Pin=-80dBm +0x81c 0xe9200301 // Pin=-78dBm +0x81c 0xe8220301 // Pin=-76dBm +0x81c 0xe7240301 // Pin=-74dBm +0x81c 0xe6260301 // Pin=-72dBm +0x81c 0xe5280301 // Pin=-70dBm +0x81c 0xe42a0301 // Pin=-68dBm +0x81c 0xe32c0301 // Pin=-66dBm +0x81c 0xa42e0301 // Pin=-64dBm +0x81c 0xa3300301 // Pin=-62dBm +0x81c 0xa2320301 // Pin=-60dBm +0x81c 0x89340301 // Pin=-58dBm +0x81c 0x88360301 // Pin=-56dBm +0x81c 0x87380301 // Pin=-54dBm +0x81c 0x863a0301 // Pin=-52dBm +0x81c 0x6a3c0301 // Pin=-50dBm +0x81c 0x693e0301 // Pin=-48dBm +0x81c 0x68400301 // Pin=-46dBm +0x81c 0x67420301 // Pin=-44dBm +0x81c 0x66440301 // Pin=-42dBm +0x81c 0x65460301 // Pin=-40dBm +0x81c 0x64480301 // Pin=-38dBm +0x81c 0x284a0301 // Pin=-36dBm +0x81c 0x274c0301 // Pin=-34dBm +0x81c 0x264e0301 // Pin=-32dBm +0x81c 0x25500301 // Pin=-30dBm +0x81c 0x24520301 // Pin=-28dBm +0x81c 0x23540301 // Pin=-26dBm +0x81c 0x22560301 // Pin=-24dBm +0x81c 0x21580301 // Pin=-22dBm +0x81c 0x055a0301 // Pin=-20dBm +0x81c 0x045c0301 // Pin=-18dBm +0x81c 0x035e0301 // Pin=-16dBm +0x81c 0x02600301 // Pin=-14dBm +0x81c 0x01620301 // Pin=-12dBm +0x81c 0x01640301 // Pin=-10dBm +0x81c 0x01660301 // Pin=-08dBm +0x81c 0x01680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP_intpa.txt old mode 100755 new mode 100644 index 8a89dcdfea1..501c62c69fb --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881ABP_intpa.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfb000101 // Pin=-110dBm -0x81c 0xfa020101 // Pin=-108dBm -0x81c 0xf9040101 // Pin=-106dBm -0x81c 0xf8060101 // Pin=-104dBm -0x81c 0xf7080101 // Pin=-102dBm -0x81c 0xf60a0101 // Pin=-100dBm -0x81c 0xf50c0101 // Pin=-98dBm -0x81c 0xf40e0101 // Pin=-96dBm -0x81c 0xf3100101 // Pin=-94dBm -0x81c 0xf2120101 // Pin=-92dBm -0x81c 0xf1140101 // Pin=-90dBm -0x81c 0xf0160101 // Pin=-88dBm -0x81c 0xef180101 // Pin=-86dBm -0x81c 0xee1a0101 // Pin=-84dBm -0x81c 0xed1c0101 // Pin=-82dBm -0x81c 0xec1e0101 // Pin=-80dBm -0x81c 0xeb200101 // Pin=-78dBm -0x81c 0xea220101 // Pin=-76dBm -0x81c 0xe9240101 // Pin=-74dBm -0x81c 0xe8260101 // Pin=-72dBm -0x81c 0xe7280101 // Pin=-70dBm -0x81c 0xe62a0101 // Pin=-68dBm -0x81c 0xe52c0101 // Pin=-66dBm -0x81c 0xe42e0101 // Pin=-64dBm -0x81c 0xe3300101 // Pin=-62dBm -0x81c 0xe2320101 // Pin=-60dBm -0x81c 0xa3340101 // Pin=-58dBm -0x81c 0xa2360101 // Pin=-56dBm -0x81c 0xa1380101 // Pin=-54dBm -0x81c 0x863a0101 // Pin=-52dBm -0x81c 0x853c0101 // Pin=-50dBm -0x81c 0x843e0101 // Pin=-48dBm -0x81c 0x83400101 // Pin=-46dBm -0x81c 0x66420101 // Pin=-44dBm -0x81c 0x65440101 // Pin=-42dBm -0x81c 0x64460101 // Pin=-40dBm -0x81c 0x63480101 // Pin=-38dBm -0x81c 0x624a0101 // Pin=-36dBm -0x81c 0x2a4c0101 // Pin=-34dBm -0x81c 0x294e0101 // Pin=-32dBm -0x81c 0x28500101 // Pin=-30dBm -0x81c 0x27520101 // Pin=-28dBm -0x81c 0x26540101 // Pin=-26dBm -0x81c 0x25560101 // Pin=-24dBm -0x81c 0x24580101 // Pin=-22dBm -0x81c 0x235a0101 // Pin=-20dBm -0x81c 0x225c0101 // Pin=-18dBm -0x81c 0x215e0101 // Pin=-16dBm -0x81c 0x05600101 // Pin=-14dBm -0x81c 0x04620101 // Pin=-12dBm -0x81c 0x03640101 // Pin=-10dBm -0x81c 0x02660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xfa000201 // Pin=-110dBm -0x81c 0xf9020201 // Pin=-108dBm -0x81c 0xf8040201 // Pin=-106dBm -0x81c 0xf7060201 // Pin=-104dBm -0x81c 0xf6080201 // Pin=-102dBm -0x81c 0xf50a0201 // Pin=-100dBm -0x81c 0xf40c0201 // Pin=-98dBm -0x81c 0xf30e0201 // Pin=-96dBm -0x81c 0xf2100201 // Pin=-94dBm -0x81c 0xf1120201 // Pin=-92dBm -0x81c 0xf0140201 // Pin=-90dBm -0x81c 0xef160201 // Pin=-88dBm -0x81c 0xee180201 // Pin=-86dBm -0x81c 0xed1a0201 // Pin=-84dBm -0x81c 0xec1c0201 // Pin=-82dBm -0x81c 0xeb1e0201 // Pin=-80dBm -0x81c 0xea200201 // Pin=-78dBm -0x81c 0xe9220201 // Pin=-76dBm -0x81c 0xe8240201 // Pin=-74dBm -0x81c 0xe7260201 // Pin=-72dBm -0x81c 0xe6280201 // Pin=-70dBm -0x81c 0xe52a0201 // Pin=-68dBm -0x81c 0xe42c0201 // Pin=-66dBm -0x81c 0xe32e0201 // Pin=-64dBm -0x81c 0xe2300201 // Pin=-62dBm -0x81c 0xa3320201 // Pin=-60dBm -0x81c 0xa2340201 // Pin=-58dBm -0x81c 0xa1360201 // Pin=-56dBm -0x81c 0x86380201 // Pin=-54dBm -0x81c 0x853a0201 // Pin=-52dBm -0x81c 0x843c0201 // Pin=-50dBm -0x81c 0x833e0201 // Pin=-48dBm -0x81c 0x68400201 // Pin=-46dBm -0x81c 0x67420201 // Pin=-44dBm -0x81c 0x66440201 // Pin=-42dBm -0x81c 0x65460201 // Pin=-40dBm -0x81c 0x64480201 // Pin=-38dBm -0x81c 0x634a0201 // Pin=-36dBm -0x81c 0x624c0201 // Pin=-34dBm -0x81c 0x284e0201 // Pin=-32dBm -0x81c 0x27500201 // Pin=-30dBm -0x81c 0x26520201 // Pin=-28dBm -0x81c 0x25540201 // Pin=-26dBm -0x81c 0x24560201 // Pin=-24dBm -0x81c 0x23580201 // Pin=-22dBm -0x81c 0x225a0201 // Pin=-20dBm -0x81c 0x215c0201 // Pin=-18dBm -0x81c 0x055e0201 // Pin=-16dBm -0x81c 0x04600201 // Pin=-14dBm -0x81c 0x03620201 // Pin=-12dBm -0x81c 0x02640201 // Pin=-10dBm -0x81c 0x01660201 // Pin=-08dBm -0x81c 0x01680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xf9000301 // Pin=-110dBm -0x81c 0xf8020301 // Pin=-108dBm -0x81c 0xf7040301 // Pin=-106dBm -0x81c 0xf6060301 // Pin=-104dBm -0x81c 0xf5080301 // Pin=-102dBm -0x81c 0xf40a0301 // Pin=-100dBm -0x81c 0xf30c0301 // Pin=-98dBm -0x81c 0xf20e0301 // Pin=-96dBm -0x81c 0xf1100301 // Pin=-94dBm -0x81c 0xf0120301 // Pin=-92dBm -0x81c 0xef140301 // Pin=-90dBm -0x81c 0xee160301 // Pin=-88dBm -0x81c 0xed180301 // Pin=-86dBm -0x81c 0xec1a0301 // Pin=-84dBm -0x81c 0xeb1c0301 // Pin=-82dBm -0x81c 0xea1e0301 // Pin=-80dBm -0x81c 0xe9200301 // Pin=-78dBm -0x81c 0xe8220301 // Pin=-76dBm -0x81c 0xe7240301 // Pin=-74dBm -0x81c 0xe6260301 // Pin=-72dBm -0x81c 0xe5280301 // Pin=-70dBm -0x81c 0xe42a0301 // Pin=-68dBm -0x81c 0xe32c0301 // Pin=-66dBm -0x81c 0xa42e0301 // Pin=-64dBm -0x81c 0xa3300301 // Pin=-62dBm -0x81c 0xa2320301 // Pin=-60dBm -0x81c 0x89340301 // Pin=-58dBm -0x81c 0x88360301 // Pin=-56dBm -0x81c 0x87380301 // Pin=-54dBm -0x81c 0x863a0301 // Pin=-52dBm -0x81c 0x6a3c0301 // Pin=-50dBm -0x81c 0x693e0301 // Pin=-48dBm -0x81c 0x68400301 // Pin=-46dBm -0x81c 0x67420301 // Pin=-44dBm -0x81c 0x66440301 // Pin=-42dBm -0x81c 0x65460301 // Pin=-40dBm -0x81c 0x64480301 // Pin=-38dBm -0x81c 0x284a0301 // Pin=-36dBm -0x81c 0x274c0301 // Pin=-34dBm -0x81c 0x264e0301 // Pin=-32dBm -0x81c 0x25500301 // Pin=-30dBm -0x81c 0x24520301 // Pin=-28dBm -0x81c 0x23540301 // Pin=-26dBm -0x81c 0x22560301 // Pin=-24dBm -0x81c 0x21580301 // Pin=-22dBm -0x81c 0x055a0301 // Pin=-20dBm -0x81c 0x045c0301 // Pin=-18dBm -0x81c 0x035e0301 // Pin=-16dBm -0x81c 0x02600301 // Pin=-14dBm -0x81c 0x01620301 // Pin=-12dBm -0x81c 0x01640301 // Pin=-10dBm -0x81c 0x01660301 // Pin=-08dBm -0x81c 0x01680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfb000101 // Pin=-110dBm +0x81c 0xfa020101 // Pin=-108dBm +0x81c 0xf9040101 // Pin=-106dBm +0x81c 0xf8060101 // Pin=-104dBm +0x81c 0xf7080101 // Pin=-102dBm +0x81c 0xf60a0101 // Pin=-100dBm +0x81c 0xf50c0101 // Pin=-98dBm +0x81c 0xf40e0101 // Pin=-96dBm +0x81c 0xf3100101 // Pin=-94dBm +0x81c 0xf2120101 // Pin=-92dBm +0x81c 0xf1140101 // Pin=-90dBm +0x81c 0xf0160101 // Pin=-88dBm +0x81c 0xef180101 // Pin=-86dBm +0x81c 0xee1a0101 // Pin=-84dBm +0x81c 0xed1c0101 // Pin=-82dBm +0x81c 0xec1e0101 // Pin=-80dBm +0x81c 0xeb200101 // Pin=-78dBm +0x81c 0xea220101 // Pin=-76dBm +0x81c 0xe9240101 // Pin=-74dBm +0x81c 0xe8260101 // Pin=-72dBm +0x81c 0xe7280101 // Pin=-70dBm +0x81c 0xe62a0101 // Pin=-68dBm +0x81c 0xe52c0101 // Pin=-66dBm +0x81c 0xe42e0101 // Pin=-64dBm +0x81c 0xe3300101 // Pin=-62dBm +0x81c 0xe2320101 // Pin=-60dBm +0x81c 0xa3340101 // Pin=-58dBm +0x81c 0xa2360101 // Pin=-56dBm +0x81c 0xa1380101 // Pin=-54dBm +0x81c 0x863a0101 // Pin=-52dBm +0x81c 0x853c0101 // Pin=-50dBm +0x81c 0x843e0101 // Pin=-48dBm +0x81c 0x83400101 // Pin=-46dBm +0x81c 0x66420101 // Pin=-44dBm +0x81c 0x65440101 // Pin=-42dBm +0x81c 0x64460101 // Pin=-40dBm +0x81c 0x63480101 // Pin=-38dBm +0x81c 0x624a0101 // Pin=-36dBm +0x81c 0x2a4c0101 // Pin=-34dBm +0x81c 0x294e0101 // Pin=-32dBm +0x81c 0x28500101 // Pin=-30dBm +0x81c 0x27520101 // Pin=-28dBm +0x81c 0x26540101 // Pin=-26dBm +0x81c 0x25560101 // Pin=-24dBm +0x81c 0x24580101 // Pin=-22dBm +0x81c 0x235a0101 // Pin=-20dBm +0x81c 0x225c0101 // Pin=-18dBm +0x81c 0x215e0101 // Pin=-16dBm +0x81c 0x05600101 // Pin=-14dBm +0x81c 0x04620101 // Pin=-12dBm +0x81c 0x03640101 // Pin=-10dBm +0x81c 0x02660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xfa000201 // Pin=-110dBm +0x81c 0xf9020201 // Pin=-108dBm +0x81c 0xf8040201 // Pin=-106dBm +0x81c 0xf7060201 // Pin=-104dBm +0x81c 0xf6080201 // Pin=-102dBm +0x81c 0xf50a0201 // Pin=-100dBm +0x81c 0xf40c0201 // Pin=-98dBm +0x81c 0xf30e0201 // Pin=-96dBm +0x81c 0xf2100201 // Pin=-94dBm +0x81c 0xf1120201 // Pin=-92dBm +0x81c 0xf0140201 // Pin=-90dBm +0x81c 0xef160201 // Pin=-88dBm +0x81c 0xee180201 // Pin=-86dBm +0x81c 0xed1a0201 // Pin=-84dBm +0x81c 0xec1c0201 // Pin=-82dBm +0x81c 0xeb1e0201 // Pin=-80dBm +0x81c 0xea200201 // Pin=-78dBm +0x81c 0xe9220201 // Pin=-76dBm +0x81c 0xe8240201 // Pin=-74dBm +0x81c 0xe7260201 // Pin=-72dBm +0x81c 0xe6280201 // Pin=-70dBm +0x81c 0xe52a0201 // Pin=-68dBm +0x81c 0xe42c0201 // Pin=-66dBm +0x81c 0xe32e0201 // Pin=-64dBm +0x81c 0xe2300201 // Pin=-62dBm +0x81c 0xa3320201 // Pin=-60dBm +0x81c 0xa2340201 // Pin=-58dBm +0x81c 0xa1360201 // Pin=-56dBm +0x81c 0x86380201 // Pin=-54dBm +0x81c 0x853a0201 // Pin=-52dBm +0x81c 0x843c0201 // Pin=-50dBm +0x81c 0x833e0201 // Pin=-48dBm +0x81c 0x68400201 // Pin=-46dBm +0x81c 0x67420201 // Pin=-44dBm +0x81c 0x66440201 // Pin=-42dBm +0x81c 0x65460201 // Pin=-40dBm +0x81c 0x64480201 // Pin=-38dBm +0x81c 0x634a0201 // Pin=-36dBm +0x81c 0x624c0201 // Pin=-34dBm +0x81c 0x284e0201 // Pin=-32dBm +0x81c 0x27500201 // Pin=-30dBm +0x81c 0x26520201 // Pin=-28dBm +0x81c 0x25540201 // Pin=-26dBm +0x81c 0x24560201 // Pin=-24dBm +0x81c 0x23580201 // Pin=-22dBm +0x81c 0x225a0201 // Pin=-20dBm +0x81c 0x215c0201 // Pin=-18dBm +0x81c 0x055e0201 // Pin=-16dBm +0x81c 0x04600201 // Pin=-14dBm +0x81c 0x03620201 // Pin=-12dBm +0x81c 0x02640201 // Pin=-10dBm +0x81c 0x01660201 // Pin=-08dBm +0x81c 0x01680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xf9000301 // Pin=-110dBm +0x81c 0xf8020301 // Pin=-108dBm +0x81c 0xf7040301 // Pin=-106dBm +0x81c 0xf6060301 // Pin=-104dBm +0x81c 0xf5080301 // Pin=-102dBm +0x81c 0xf40a0301 // Pin=-100dBm +0x81c 0xf30c0301 // Pin=-98dBm +0x81c 0xf20e0301 // Pin=-96dBm +0x81c 0xf1100301 // Pin=-94dBm +0x81c 0xf0120301 // Pin=-92dBm +0x81c 0xef140301 // Pin=-90dBm +0x81c 0xee160301 // Pin=-88dBm +0x81c 0xed180301 // Pin=-86dBm +0x81c 0xec1a0301 // Pin=-84dBm +0x81c 0xeb1c0301 // Pin=-82dBm +0x81c 0xea1e0301 // Pin=-80dBm +0x81c 0xe9200301 // Pin=-78dBm +0x81c 0xe8220301 // Pin=-76dBm +0x81c 0xe7240301 // Pin=-74dBm +0x81c 0xe6260301 // Pin=-72dBm +0x81c 0xe5280301 // Pin=-70dBm +0x81c 0xe42a0301 // Pin=-68dBm +0x81c 0xe32c0301 // Pin=-66dBm +0x81c 0xa42e0301 // Pin=-64dBm +0x81c 0xa3300301 // Pin=-62dBm +0x81c 0xa2320301 // Pin=-60dBm +0x81c 0x89340301 // Pin=-58dBm +0x81c 0x88360301 // Pin=-56dBm +0x81c 0x87380301 // Pin=-54dBm +0x81c 0x863a0301 // Pin=-52dBm +0x81c 0x6a3c0301 // Pin=-50dBm +0x81c 0x693e0301 // Pin=-48dBm +0x81c 0x68400301 // Pin=-46dBm +0x81c 0x67420301 // Pin=-44dBm +0x81c 0x66440301 // Pin=-42dBm +0x81c 0x65460301 // Pin=-40dBm +0x81c 0x64480301 // Pin=-38dBm +0x81c 0x284a0301 // Pin=-36dBm +0x81c 0x274c0301 // Pin=-34dBm +0x81c 0x264e0301 // Pin=-32dBm +0x81c 0x25500301 // Pin=-30dBm +0x81c 0x24520301 // Pin=-28dBm +0x81c 0x23540301 // Pin=-26dBm +0x81c 0x22560301 // Pin=-24dBm +0x81c 0x21580301 // Pin=-22dBm +0x81c 0x055a0301 // Pin=-20dBm +0x81c 0x045c0301 // Pin=-18dBm +0x81c 0x035e0301 // Pin=-16dBm +0x81c 0x02600301 // Pin=-14dBm +0x81c 0x01620301 // Pin=-12dBm +0x81c 0x01640301 // Pin=-10dBm +0x81c 0x01660301 // Pin=-08dBm +0x81c 0x01680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP.txt index 6d66638be5e..2ccd2de24a1 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfe000101 // Pin=-110dBm -0x81c 0xfd020101 // Pin=-108dBm -0x81c 0xfc040101 // Pin=-106dBm -0x81c 0xfb060101 // Pin=-104dBm -0x81c 0xfa080101 // Pin=-102dBm -0x81c 0xf90a0101 // Pin=-100dBm -0x81c 0xf80c0101 // Pin=-98dBm -0x81c 0xf70e0101 // Pin=-96dBm -0x81c 0xf6100101 // Pin=-94dBm -0x81c 0xf5120101 // Pin=-92dBm -0x81c 0xf4140101 // Pin=-90dBm -0x81c 0xf3160101 // Pin=-88dBm -0x81c 0xf2180101 // Pin=-86dBm -0x81c 0xf11a0101 // Pin=-84dBm -0x81c 0xf01c0101 // Pin=-82dBm -0x81c 0xef1e0101 // Pin=-80dBm -0x81c 0xee200101 // Pin=-78dBm -0x81c 0xed220101 // Pin=-76dBm -0x81c 0xec240101 // Pin=-74dBm -0x81c 0xeb260101 // Pin=-72dBm -0x81c 0xea280101 // Pin=-70dBm -0x81c 0xe92a0101 // Pin=-68dBm -0x81c 0xe82c0101 // Pin=-66dBm -0x81c 0xe72e0101 // Pin=-64dBm -0x81c 0xe6300101 // Pin=-62dBm -0x81c 0xe5320101 // Pin=-60dBm -0x81c 0xe4340101 // Pin=-58dBm -0x81c 0xe3360101 // Pin=-56dBm -0x81c 0xa6380101 // Pin=-54dBm -0x81c 0xa53a0101 // Pin=-52dBm -0x81c 0xa43c0101 // Pin=-50dBm -0x81c 0xa33e0101 // Pin=-48dBm -0x81c 0x83400101 // Pin=-46dBm -0x81c 0x82420101 // Pin=-44dBm -0x81c 0x65440101 // Pin=-42dBm -0x81c 0x64460101 // Pin=-40dBm -0x81c 0x63480101 // Pin=-38dBm -0x81c 0x624a0101 // Pin=-36dBm -0x81c 0x614c0101 // Pin=-34dBm -0x81c 0x2a4e0101 // Pin=-32dBm -0x81c 0x29500101 // Pin=-30dBm -0x81c 0x28520101 // Pin=-28dBm -0x81c 0x27540101 // Pin=-26dBm -0x81c 0x26560101 // Pin=-24dBm -0x81c 0x25580101 // Pin=-22dBm -0x81c 0x245a0101 // Pin=-20dBm -0x81c 0x235c0101 // Pin=-18dBm -0x81c 0x225e0101 // Pin=-16dBm -0x81c 0x06600101 // Pin=-14dBm -0x81c 0x05620101 // Pin=-12dBm -0x81c 0x04640101 // Pin=-10dBm -0x81c 0x03660101 // Pin=-08dBm -0x81c 0x02680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xff000201 // Pin=-110dBm -0x81c 0xfe020201 // Pin=-108dBm -0x81c 0xfd040201 // Pin=-106dBm -0x81c 0xfc060201 // Pin=-104dBm -0x81c 0xfb080201 // Pin=-102dBm -0x81c 0xfa0a0201 // Pin=-100dBm -0x81c 0xf90c0201 // Pin=-98dBm -0x81c 0xf80e0201 // Pin=-96dBm -0x81c 0xf7100201 // Pin=-94dBm -0x81c 0xf6120201 // Pin=-92dBm -0x81c 0xf5140201 // Pin=-90dBm -0x81c 0xf4160201 // Pin=-88dBm -0x81c 0xf3180201 // Pin=-86dBm -0x81c 0xf21a0201 // Pin=-84dBm -0x81c 0xf11c0201 // Pin=-82dBm -0x81c 0xf01e0201 // Pin=-80dBm -0x81c 0xef200201 // Pin=-78dBm -0x81c 0xee220201 // Pin=-76dBm -0x81c 0xed240201 // Pin=-74dBm -0x81c 0xec260201 // Pin=-72dBm -0x81c 0xeb280201 // Pin=-70dBm -0x81c 0xea2a0201 // Pin=-68dBm -0x81c 0xe92c0201 // Pin=-66dBm -0x81c 0xe82e0201 // Pin=-64dBm -0x81c 0xe7300201 // Pin=-62dBm -0x81c 0xe6320201 // Pin=-60dBm -0x81c 0xe5340201 // Pin=-58dBm -0x81c 0xe4360201 // Pin=-56dBm -0x81c 0xe3380201 // Pin=-54dBm -0x81c 0xe23a0201 // Pin=-52dBm -0x81c 0xa53c0201 // Pin=-50dBm -0x81c 0xa43e0201 // Pin=-48dBm -0x81c 0xa3400201 // Pin=-46dBm //8->a -0x81c 0x85420201 // Pin=-44dBm //add 1 index RxBB -0x81c 0x84440201 // Pin=-42dBm //add 1 index RxBB -0x81c 0x83460201 // Pin=-40dBm //add 1 index RxBB -0x81c 0x67480201 // Pin=-38dBm //add 1 index RxBB -0x81c 0x664a0201 // Pin=-36dBm //add 1 index RxBB -0x81c 0x654c0201 // Pin=-34dBm //add 1 index RxBB -0x81c 0x644e0201 // Pin=-32dBm //add 1 index RxBB -0x81c 0x63500201 // Pin=-30dBm //2->6 -0x81c 0x28520201 // Pin=-28dBm -0x81c 0x27540201 // Pin=-26dBm -0x81c 0x26560201 // Pin=-24dBm -0x81c 0x25580201 // Pin=-22dBm -0x81c 0x245a0201 // Pin=-20dBm -0x81c 0x235c0201 // Pin=-18dBm -0x81c 0x225e0201 // Pin=-16dBm -0x81c 0x06600201 // Pin=-14dBm -0x81c 0x05620201 // Pin=-12dBm -0x81c 0x04640201 // Pin=-10dBm -0x81c 0x03660201 // Pin=-08dBm -0x81c 0x02680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xff000301 // Pin=-110dBm -0x81c 0xfe020301 // Pin=-108dBm -0x81c 0xfd040301 // Pin=-106dBm -0x81c 0xfc060301 // Pin=-104dBm -0x81c 0xfb080301 // Pin=-102dBm -0x81c 0xfa0a0301 // Pin=-100dBm -0x81c 0xf90c0301 // Pin=-98dBm -0x81c 0xf80e0301 // Pin=-96dBm -0x81c 0xf7100301 // Pin=-94dBm -0x81c 0xf6120301 // Pin=-92dBm -0x81c 0xf5140301 // Pin=-90dBm -0x81c 0xf4160301 // Pin=-88dBm -0x81c 0xf3180301 // Pin=-86dBm -0x81c 0xf21a0301 // Pin=-84dBm -0x81c 0xf11c0301 // Pin=-82dBm -0x81c 0xf01e0301 // Pin=-80dBm -0x81c 0xef200301 // Pin=-78dBm -0x81c 0xee220301 // Pin=-76dBm -0x81c 0xed240301 // Pin=-74dBm -0x81c 0xec260301 // Pin=-72dBm -0x81c 0xeb280301 // Pin=-70dBm -0x81c 0xea2a0301 // Pin=-68dBm -0x81c 0xe92c0301 // Pin=-66dBm -0x81c 0xe82e0301 // Pin=-64dBm -0x81c 0xe7300301 // Pin=-62dBm -0x81c 0xe6320301 // Pin=-60dBm -0x81c 0xe5340301 // Pin=-58dBm -0x81c 0xe4360301 // Pin=-56dBm -0x81c 0xe3380301 // Pin=-54dBm -0x81c 0xa63a0301 // Pin=-52dBm -0x81c 0xa53c0301 // Pin=-50dBm -0x81c 0xa43e0301 // Pin=-48dBm -0x81c 0xa3400301 // Pin=-46dBm -0x81c 0xa2420301 // Pin=-44dBm //8->a -0x81c 0x84440301 // Pin=-42dBm -0x81c 0x83460301 // Pin=-40dBm -0x81c 0x67480301 // Pin=-38dBm -0x81c 0x664a0301 // Pin=-36dBm -0x81c 0x654c0301 // Pin=-34dBm -0x81c 0x644e0301 // Pin=-32dBm -0x81c 0x28500301 // Pin=-30dBm //6->2 -0x81c 0x27520301 // Pin=-28dBm -0x81c 0x26540301 // Pin=-26dBm -0x81c 0x25560301 // Pin=-24dBm -0x81c 0x24580301 // Pin=-22dBm -0x81c 0x235a0301 // Pin=-20dBm -0x81c 0x225c0301 // Pin=-18dBm -0x81c 0x215e0301 // Pin=-16dBm -0x81c 0x06600301 // Pin=-14dBm -0x81c 0x05620301 // Pin=-12dBm -0x81c 0x04640301 // Pin=-10dBm -0x81c 0x03660301 // Pin=-08dBm -0x81c 0x02680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfe000101 // Pin=-110dBm +0x81c 0xfd020101 // Pin=-108dBm +0x81c 0xfc040101 // Pin=-106dBm +0x81c 0xfb060101 // Pin=-104dBm +0x81c 0xfa080101 // Pin=-102dBm +0x81c 0xf90a0101 // Pin=-100dBm +0x81c 0xf80c0101 // Pin=-98dBm +0x81c 0xf70e0101 // Pin=-96dBm +0x81c 0xf6100101 // Pin=-94dBm +0x81c 0xf5120101 // Pin=-92dBm +0x81c 0xf4140101 // Pin=-90dBm +0x81c 0xf3160101 // Pin=-88dBm +0x81c 0xf2180101 // Pin=-86dBm +0x81c 0xf11a0101 // Pin=-84dBm +0x81c 0xf01c0101 // Pin=-82dBm +0x81c 0xef1e0101 // Pin=-80dBm +0x81c 0xee200101 // Pin=-78dBm +0x81c 0xed220101 // Pin=-76dBm +0x81c 0xec240101 // Pin=-74dBm +0x81c 0xeb260101 // Pin=-72dBm +0x81c 0xea280101 // Pin=-70dBm +0x81c 0xe92a0101 // Pin=-68dBm +0x81c 0xe82c0101 // Pin=-66dBm +0x81c 0xe72e0101 // Pin=-64dBm +0x81c 0xe6300101 // Pin=-62dBm +0x81c 0xe5320101 // Pin=-60dBm +0x81c 0xe4340101 // Pin=-58dBm +0x81c 0xe3360101 // Pin=-56dBm +0x81c 0xa6380101 // Pin=-54dBm +0x81c 0xa53a0101 // Pin=-52dBm +0x81c 0xa43c0101 // Pin=-50dBm +0x81c 0xa33e0101 // Pin=-48dBm +0x81c 0x83400101 // Pin=-46dBm +0x81c 0x82420101 // Pin=-44dBm +0x81c 0x65440101 // Pin=-42dBm +0x81c 0x64460101 // Pin=-40dBm +0x81c 0x63480101 // Pin=-38dBm +0x81c 0x624a0101 // Pin=-36dBm +0x81c 0x614c0101 // Pin=-34dBm +0x81c 0x2a4e0101 // Pin=-32dBm +0x81c 0x29500101 // Pin=-30dBm +0x81c 0x28520101 // Pin=-28dBm +0x81c 0x27540101 // Pin=-26dBm +0x81c 0x26560101 // Pin=-24dBm +0x81c 0x25580101 // Pin=-22dBm +0x81c 0x245a0101 // Pin=-20dBm +0x81c 0x235c0101 // Pin=-18dBm +0x81c 0x225e0101 // Pin=-16dBm +0x81c 0x06600101 // Pin=-14dBm +0x81c 0x05620101 // Pin=-12dBm +0x81c 0x04640101 // Pin=-10dBm +0x81c 0x03660101 // Pin=-08dBm +0x81c 0x02680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xff000201 // Pin=-110dBm +0x81c 0xfe020201 // Pin=-108dBm +0x81c 0xfd040201 // Pin=-106dBm +0x81c 0xfc060201 // Pin=-104dBm +0x81c 0xfb080201 // Pin=-102dBm +0x81c 0xfa0a0201 // Pin=-100dBm +0x81c 0xf90c0201 // Pin=-98dBm +0x81c 0xf80e0201 // Pin=-96dBm +0x81c 0xf7100201 // Pin=-94dBm +0x81c 0xf6120201 // Pin=-92dBm +0x81c 0xf5140201 // Pin=-90dBm +0x81c 0xf4160201 // Pin=-88dBm +0x81c 0xf3180201 // Pin=-86dBm +0x81c 0xf21a0201 // Pin=-84dBm +0x81c 0xf11c0201 // Pin=-82dBm +0x81c 0xf01e0201 // Pin=-80dBm +0x81c 0xef200201 // Pin=-78dBm +0x81c 0xee220201 // Pin=-76dBm +0x81c 0xed240201 // Pin=-74dBm +0x81c 0xec260201 // Pin=-72dBm +0x81c 0xeb280201 // Pin=-70dBm +0x81c 0xea2a0201 // Pin=-68dBm +0x81c 0xe92c0201 // Pin=-66dBm +0x81c 0xe82e0201 // Pin=-64dBm +0x81c 0xe7300201 // Pin=-62dBm +0x81c 0xe6320201 // Pin=-60dBm +0x81c 0xe5340201 // Pin=-58dBm +0x81c 0xe4360201 // Pin=-56dBm +0x81c 0xe3380201 // Pin=-54dBm +0x81c 0xe23a0201 // Pin=-52dBm +0x81c 0xa53c0201 // Pin=-50dBm +0x81c 0xa43e0201 // Pin=-48dBm +0x81c 0xa3400201 // Pin=-46dBm //8->a +0x81c 0x85420201 // Pin=-44dBm //add 1 index RxBB +0x81c 0x84440201 // Pin=-42dBm //add 1 index RxBB +0x81c 0x83460201 // Pin=-40dBm //add 1 index RxBB +0x81c 0x67480201 // Pin=-38dBm //add 1 index RxBB +0x81c 0x664a0201 // Pin=-36dBm //add 1 index RxBB +0x81c 0x654c0201 // Pin=-34dBm //add 1 index RxBB +0x81c 0x644e0201 // Pin=-32dBm //add 1 index RxBB +0x81c 0x63500201 // Pin=-30dBm //2->6 +0x81c 0x28520201 // Pin=-28dBm +0x81c 0x27540201 // Pin=-26dBm +0x81c 0x26560201 // Pin=-24dBm +0x81c 0x25580201 // Pin=-22dBm +0x81c 0x245a0201 // Pin=-20dBm +0x81c 0x235c0201 // Pin=-18dBm +0x81c 0x225e0201 // Pin=-16dBm +0x81c 0x06600201 // Pin=-14dBm +0x81c 0x05620201 // Pin=-12dBm +0x81c 0x04640201 // Pin=-10dBm +0x81c 0x03660201 // Pin=-08dBm +0x81c 0x02680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xff000301 // Pin=-110dBm +0x81c 0xfe020301 // Pin=-108dBm +0x81c 0xfd040301 // Pin=-106dBm +0x81c 0xfc060301 // Pin=-104dBm +0x81c 0xfb080301 // Pin=-102dBm +0x81c 0xfa0a0301 // Pin=-100dBm +0x81c 0xf90c0301 // Pin=-98dBm +0x81c 0xf80e0301 // Pin=-96dBm +0x81c 0xf7100301 // Pin=-94dBm +0x81c 0xf6120301 // Pin=-92dBm +0x81c 0xf5140301 // Pin=-90dBm +0x81c 0xf4160301 // Pin=-88dBm +0x81c 0xf3180301 // Pin=-86dBm +0x81c 0xf21a0301 // Pin=-84dBm +0x81c 0xf11c0301 // Pin=-82dBm +0x81c 0xf01e0301 // Pin=-80dBm +0x81c 0xef200301 // Pin=-78dBm +0x81c 0xee220301 // Pin=-76dBm +0x81c 0xed240301 // Pin=-74dBm +0x81c 0xec260301 // Pin=-72dBm +0x81c 0xeb280301 // Pin=-70dBm +0x81c 0xea2a0301 // Pin=-68dBm +0x81c 0xe92c0301 // Pin=-66dBm +0x81c 0xe82e0301 // Pin=-64dBm +0x81c 0xe7300301 // Pin=-62dBm +0x81c 0xe6320301 // Pin=-60dBm +0x81c 0xe5340301 // Pin=-58dBm +0x81c 0xe4360301 // Pin=-56dBm +0x81c 0xe3380301 // Pin=-54dBm +0x81c 0xa63a0301 // Pin=-52dBm +0x81c 0xa53c0301 // Pin=-50dBm +0x81c 0xa43e0301 // Pin=-48dBm +0x81c 0xa3400301 // Pin=-46dBm +0x81c 0xa2420301 // Pin=-44dBm //8->a +0x81c 0x84440301 // Pin=-42dBm +0x81c 0x83460301 // Pin=-40dBm +0x81c 0x67480301 // Pin=-38dBm +0x81c 0x664a0301 // Pin=-36dBm +0x81c 0x654c0301 // Pin=-34dBm +0x81c 0x644e0301 // Pin=-32dBm +0x81c 0x28500301 // Pin=-30dBm //6->2 +0x81c 0x27520301 // Pin=-28dBm +0x81c 0x26540301 // Pin=-26dBm +0x81c 0x25560301 // Pin=-24dBm +0x81c 0x24580301 // Pin=-22dBm +0x81c 0x235a0301 // Pin=-20dBm +0x81c 0x225c0301 // Pin=-18dBm +0x81c 0x215e0301 // Pin=-16dBm +0x81c 0x06600301 // Pin=-14dBm +0x81c 0x05620301 // Pin=-12dBm +0x81c 0x04640301 // Pin=-10dBm +0x81c 0x03660301 // Pin=-08dBm +0x81c 0x02680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_2layer.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_2layer.txt old mode 100755 new mode 100644 index 66e8f0d424f..e163632f6e0 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_2layer.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_2layer.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xfe040101 // Pin=-106dBm -0x81c 0xfd060101 // Pin=-104dBm -0x81c 0xfc080101 // Pin=-102dBm -0x81c 0xfb0a0101 // Pin=-100dBm -0x81c 0xfa0c0101 // Pin=-98dBm -0x81c 0xf90e0101 // Pin=-96dBm -0x81c 0xf8100101 // Pin=-94dBm -0x81c 0xf7120101 // Pin=-92dBm -0x81c 0xf6140101 // Pin=-90dBm -0x81c 0xf5160101 // Pin=-88dBm -0x81c 0xf4180101 // Pin=-86dBm -0x81c 0xf31a0101 // Pin=-84dBm -0x81c 0xf21c0101 // Pin=-82dBm -0x81c 0xf11e0101 // Pin=-80dBm -0x81c 0xf0200101 // Pin=-78dBm -0x81c 0xef220101 // Pin=-76dBm -0x81c 0xee240101 // Pin=-74dBm -0x81c 0xed260101 // Pin=-72dBm -0x81c 0xec280101 // Pin=-70dBm -0x81c 0xeb2a0101 // Pin=-68dBm -0x81c 0xea2c0101 // Pin=-66dBm -0x81c 0xe92e0101 // Pin=-64dBm -0x81c 0xe8300101 // Pin=-62dBm -0x81c 0xe7320101 // Pin=-60dBm -0x81c 0xe6340101 // Pin=-58dBm -0x81c 0xe5360101 // Pin=-56dBm -0x81c 0xe4380101 // Pin=-54dBm -0x81c 0xe33a0101 // Pin=-52dBm -0x81c 0xa73c0101 // Pin=-50dBm -0x81c 0xa63e0101 // Pin=-48dBm -0x81c 0xa5400101 // Pin=-46dBm -0x81c 0x86420101 // Pin=-44dBm -0x81c 0x85440101 // Pin=-42dBm -0x81c 0x84460101 // Pin=-40dBm -0x81c 0x83480101 // Pin=-38dBm -0x81c 0x674a0101 // Pin=-36dBm -0x81c 0x664c0101 // Pin=-34dBm -0x81c 0x654e0101 // Pin=-32dBm -0x81c 0x48500101 // Pin=-30dBm -0x81c 0x47520101 // Pin=-28dBm -0x81c 0x29540101 // Pin=-26dBm -0x81c 0x28560101 // Pin=-24dBm -0x81c 0x27580101 // Pin=-22dBm -0x81c 0x265a0101 // Pin=-20dBm -0x81c 0x255c0101 // Pin=-18dBm -0x81c 0x245e0101 // Pin=-16dBm -0x81c 0x23600101 // Pin=-14dBm -0x81c 0x22620101 // Pin=-12dBm -0x81c 0x07640101 // Pin=-10dBm -0x81c 0x06660101 // Pin=-08dBm -0x81c 0x05680101 // Pin=-06dBm -0x81c 0x046a0101 // Pin=-04dBm -0x81c 0x036c0101 // Pin=-02dBm -0x81c 0x026e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xff000201 // Pin=-110dBm -0x81c 0xff020201 // Pin=-108dBm -0x81c 0xfe040201 // Pin=-106dBm -0x81c 0xfd060201 // Pin=-104dBm -0x81c 0xfc080201 // Pin=-102dBm -0x81c 0xfb0a0201 // Pin=-100dBm -0x81c 0xfa0c0201 // Pin=-98dBm -0x81c 0xf90e0201 // Pin=-96dBm -0x81c 0xf8100201 // Pin=-94dBm -0x81c 0xf7120201 // Pin=-92dBm -0x81c 0xf6140201 // Pin=-90dBm -0x81c 0xf5160201 // Pin=-88dBm -0x81c 0xf4180201 // Pin=-86dBm -0x81c 0xf31a0201 // Pin=-84dBm -0x81c 0xf21c0201 // Pin=-82dBm -0x81c 0xf11e0201 // Pin=-80dBm -0x81c 0xf0200201 // Pin=-78dBm -0x81c 0xef220201 // Pin=-76dBm -0x81c 0xee240201 // Pin=-74dBm -0x81c 0xed260201 // Pin=-72dBm -0x81c 0xec280201 // Pin=-70dBm -0x81c 0xeb2a0201 // Pin=-68dBm -0x81c 0xea2c0201 // Pin=-66dBm -0x81c 0xe92e0201 // Pin=-64dBm -0x81c 0xe8300201 // Pin=-62dBm -0x81c 0xe7320201 // Pin=-60dBm -0x81c 0xc9340201 // Pin=-58dBm -0x81c 0xe5360201 // Pin=-56dBm -0x81c 0xe4380201 // Pin=-54dBm -0x81c 0xe33a0201 // Pin=-52dBm -0x81c 0xa73c0201 // Pin=-50dBm -0x81c 0xa63e0201 // Pin=-48dBm -0x81c 0xa5400201 // Pin=-46dBm -0x81c 0xa4420201 // Pin=-44dBm -0x81c 0xa3440201 // Pin=-42dBm -0x81c 0x84460201 // Pin=-40dBm -0x81c 0x68480201 // Pin=-38dBm -0x81c 0x674a0201 // Pin=-36dBm -0x81c 0x664c0201 // Pin=-34dBm -0x81c 0x654e0201 // Pin=-32dBm -0x81c 0x64500201 // Pin=-30dBm -0x81c 0x47520201 // Pin=-28dBm -0x81c 0x29540201 // Pin=-26dBm -0x81c 0x28560201 // Pin=-24dBm -0x81c 0x27580201 // Pin=-22dBm -0x81c 0x265a0201 // Pin=-20dBm -0x81c 0x255c0201 // Pin=-18dBm -0x81c 0x245e0201 // Pin=-16dBm -0x81c 0x23600201 // Pin=-14dBm -0x81c 0x08620201 // Pin=-12dBm -0x81c 0x07640201 // Pin=-10dBm -0x81c 0x06660201 // Pin=-08dBm -0x81c 0x05680201 // Pin=-06dBm -0x81c 0x046a0201 // Pin=-04dBm -0x81c 0x036c0201 // Pin=-02dBm -0x81c 0x026e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xff000301 // Pin=-110dBm -0x81c 0xff020301 // Pin=-108dBm -0x81c 0xfe040301 // Pin=-106dBm -0x81c 0xfd060301 // Pin=-104dBm -0x81c 0xfc080301 // Pin=-102dBm -0x81c 0xfb0a0301 // Pin=-100dBm -0x81c 0xfa0c0301 // Pin=-98dBm -0x81c 0xf90e0301 // Pin=-96dBm -0x81c 0xf8100301 // Pin=-94dBm -0x81c 0xf7120301 // Pin=-92dBm -0x81c 0xf6140301 // Pin=-90dBm -0x81c 0xf5160301 // Pin=-88dBm -0x81c 0xf4180301 // Pin=-86dBm -0x81c 0xf31a0301 // Pin=-84dBm -0x81c 0xf21c0301 // Pin=-82dBm -0x81c 0xf11e0301 // Pin=-80dBm -0x81c 0xf0200301 // Pin=-78dBm -0x81c 0xef220301 // Pin=-76dBm -0x81c 0xee240301 // Pin=-74dBm -0x81c 0xed260301 // Pin=-72dBm -0x81c 0xec280301 // Pin=-70dBm -0x81c 0xeb2a0301 // Pin=-68dBm -0x81c 0xea2c0301 // Pin=-66dBm -0x81c 0xe92e0301 // Pin=-64dBm -0x81c 0xe8300301 // Pin=-62dBm -0x81c 0xe7320301 // Pin=-60dBm -0x81c 0xe6340301 // Pin=-58dBm -0x81c 0xe5360301 // Pin=-56dBm -0x81c 0xe4380301 // Pin=-54dBm -0x81c 0xa73a0301 // Pin=-52dBm -0x81c 0xa63c0301 // Pin=-50dBm -0x81c 0xa53e0301 // Pin=-48dBm -0x81c 0xa4400301 // Pin=-46dBm -0x81c 0xa3420301 // Pin=-44dBm -0x81c 0x6a440301 // Pin=-42dBm -0x81c 0x69460301 // Pin=-40dBm -0x81c 0x68480301 // Pin=-38dBm -0x81c 0x674a0301 // Pin=-36dBm -0x81c 0x4a4c0301 // Pin=-34dBm -0x81c 0x654e0301 // Pin=-32dBm -0x81c 0x48500301 // Pin=-30dBm -0x81c 0x29520301 // Pin=-28dBm -0x81c 0x28540301 // Pin=-26dBm -0x81c 0x27560301 // Pin=-24dBm -0x81c 0x26580301 // Pin=-22dBm -0x81c 0x255a0301 // Pin=-20dBm -0x81c 0x245c0301 // Pin=-18dBm -0x81c 0x235e0301 // Pin=-16dBm -0x81c 0x07600301 // Pin=-14dBm -0x81c 0x06620301 // Pin=-12dBm -0x81c 0x05640301 // Pin=-10dBm -0x81c 0x04660301 // Pin=-08dBm -0x81c 0x03680301 // Pin=-06dBm -0x81c 0x026a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xfe040101 // Pin=-106dBm +0x81c 0xfd060101 // Pin=-104dBm +0x81c 0xfc080101 // Pin=-102dBm +0x81c 0xfb0a0101 // Pin=-100dBm +0x81c 0xfa0c0101 // Pin=-98dBm +0x81c 0xf90e0101 // Pin=-96dBm +0x81c 0xf8100101 // Pin=-94dBm +0x81c 0xf7120101 // Pin=-92dBm +0x81c 0xf6140101 // Pin=-90dBm +0x81c 0xf5160101 // Pin=-88dBm +0x81c 0xf4180101 // Pin=-86dBm +0x81c 0xf31a0101 // Pin=-84dBm +0x81c 0xf21c0101 // Pin=-82dBm +0x81c 0xf11e0101 // Pin=-80dBm +0x81c 0xf0200101 // Pin=-78dBm +0x81c 0xef220101 // Pin=-76dBm +0x81c 0xee240101 // Pin=-74dBm +0x81c 0xed260101 // Pin=-72dBm +0x81c 0xec280101 // Pin=-70dBm +0x81c 0xeb2a0101 // Pin=-68dBm +0x81c 0xea2c0101 // Pin=-66dBm +0x81c 0xe92e0101 // Pin=-64dBm +0x81c 0xe8300101 // Pin=-62dBm +0x81c 0xe7320101 // Pin=-60dBm +0x81c 0xe6340101 // Pin=-58dBm +0x81c 0xe5360101 // Pin=-56dBm +0x81c 0xe4380101 // Pin=-54dBm +0x81c 0xe33a0101 // Pin=-52dBm +0x81c 0xa73c0101 // Pin=-50dBm +0x81c 0xa63e0101 // Pin=-48dBm +0x81c 0xa5400101 // Pin=-46dBm +0x81c 0x86420101 // Pin=-44dBm +0x81c 0x85440101 // Pin=-42dBm +0x81c 0x84460101 // Pin=-40dBm +0x81c 0x83480101 // Pin=-38dBm +0x81c 0x674a0101 // Pin=-36dBm +0x81c 0x664c0101 // Pin=-34dBm +0x81c 0x654e0101 // Pin=-32dBm +0x81c 0x48500101 // Pin=-30dBm +0x81c 0x47520101 // Pin=-28dBm +0x81c 0x29540101 // Pin=-26dBm +0x81c 0x28560101 // Pin=-24dBm +0x81c 0x27580101 // Pin=-22dBm +0x81c 0x265a0101 // Pin=-20dBm +0x81c 0x255c0101 // Pin=-18dBm +0x81c 0x245e0101 // Pin=-16dBm +0x81c 0x23600101 // Pin=-14dBm +0x81c 0x22620101 // Pin=-12dBm +0x81c 0x07640101 // Pin=-10dBm +0x81c 0x06660101 // Pin=-08dBm +0x81c 0x05680101 // Pin=-06dBm +0x81c 0x046a0101 // Pin=-04dBm +0x81c 0x036c0101 // Pin=-02dBm +0x81c 0x026e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xff000201 // Pin=-110dBm +0x81c 0xff020201 // Pin=-108dBm +0x81c 0xfe040201 // Pin=-106dBm +0x81c 0xfd060201 // Pin=-104dBm +0x81c 0xfc080201 // Pin=-102dBm +0x81c 0xfb0a0201 // Pin=-100dBm +0x81c 0xfa0c0201 // Pin=-98dBm +0x81c 0xf90e0201 // Pin=-96dBm +0x81c 0xf8100201 // Pin=-94dBm +0x81c 0xf7120201 // Pin=-92dBm +0x81c 0xf6140201 // Pin=-90dBm +0x81c 0xf5160201 // Pin=-88dBm +0x81c 0xf4180201 // Pin=-86dBm +0x81c 0xf31a0201 // Pin=-84dBm +0x81c 0xf21c0201 // Pin=-82dBm +0x81c 0xf11e0201 // Pin=-80dBm +0x81c 0xf0200201 // Pin=-78dBm +0x81c 0xef220201 // Pin=-76dBm +0x81c 0xee240201 // Pin=-74dBm +0x81c 0xed260201 // Pin=-72dBm +0x81c 0xec280201 // Pin=-70dBm +0x81c 0xeb2a0201 // Pin=-68dBm +0x81c 0xea2c0201 // Pin=-66dBm +0x81c 0xe92e0201 // Pin=-64dBm +0x81c 0xe8300201 // Pin=-62dBm +0x81c 0xe7320201 // Pin=-60dBm +0x81c 0xc9340201 // Pin=-58dBm +0x81c 0xe5360201 // Pin=-56dBm +0x81c 0xe4380201 // Pin=-54dBm +0x81c 0xe33a0201 // Pin=-52dBm +0x81c 0xa73c0201 // Pin=-50dBm +0x81c 0xa63e0201 // Pin=-48dBm +0x81c 0xa5400201 // Pin=-46dBm +0x81c 0xa4420201 // Pin=-44dBm +0x81c 0xa3440201 // Pin=-42dBm +0x81c 0x84460201 // Pin=-40dBm +0x81c 0x68480201 // Pin=-38dBm +0x81c 0x674a0201 // Pin=-36dBm +0x81c 0x664c0201 // Pin=-34dBm +0x81c 0x654e0201 // Pin=-32dBm +0x81c 0x64500201 // Pin=-30dBm +0x81c 0x47520201 // Pin=-28dBm +0x81c 0x29540201 // Pin=-26dBm +0x81c 0x28560201 // Pin=-24dBm +0x81c 0x27580201 // Pin=-22dBm +0x81c 0x265a0201 // Pin=-20dBm +0x81c 0x255c0201 // Pin=-18dBm +0x81c 0x245e0201 // Pin=-16dBm +0x81c 0x23600201 // Pin=-14dBm +0x81c 0x08620201 // Pin=-12dBm +0x81c 0x07640201 // Pin=-10dBm +0x81c 0x06660201 // Pin=-08dBm +0x81c 0x05680201 // Pin=-06dBm +0x81c 0x046a0201 // Pin=-04dBm +0x81c 0x036c0201 // Pin=-02dBm +0x81c 0x026e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xff000301 // Pin=-110dBm +0x81c 0xff020301 // Pin=-108dBm +0x81c 0xfe040301 // Pin=-106dBm +0x81c 0xfd060301 // Pin=-104dBm +0x81c 0xfc080301 // Pin=-102dBm +0x81c 0xfb0a0301 // Pin=-100dBm +0x81c 0xfa0c0301 // Pin=-98dBm +0x81c 0xf90e0301 // Pin=-96dBm +0x81c 0xf8100301 // Pin=-94dBm +0x81c 0xf7120301 // Pin=-92dBm +0x81c 0xf6140301 // Pin=-90dBm +0x81c 0xf5160301 // Pin=-88dBm +0x81c 0xf4180301 // Pin=-86dBm +0x81c 0xf31a0301 // Pin=-84dBm +0x81c 0xf21c0301 // Pin=-82dBm +0x81c 0xf11e0301 // Pin=-80dBm +0x81c 0xf0200301 // Pin=-78dBm +0x81c 0xef220301 // Pin=-76dBm +0x81c 0xee240301 // Pin=-74dBm +0x81c 0xed260301 // Pin=-72dBm +0x81c 0xec280301 // Pin=-70dBm +0x81c 0xeb2a0301 // Pin=-68dBm +0x81c 0xea2c0301 // Pin=-66dBm +0x81c 0xe92e0301 // Pin=-64dBm +0x81c 0xe8300301 // Pin=-62dBm +0x81c 0xe7320301 // Pin=-60dBm +0x81c 0xe6340301 // Pin=-58dBm +0x81c 0xe5360301 // Pin=-56dBm +0x81c 0xe4380301 // Pin=-54dBm +0x81c 0xa73a0301 // Pin=-52dBm +0x81c 0xa63c0301 // Pin=-50dBm +0x81c 0xa53e0301 // Pin=-48dBm +0x81c 0xa4400301 // Pin=-46dBm +0x81c 0xa3420301 // Pin=-44dBm +0x81c 0x6a440301 // Pin=-42dBm +0x81c 0x69460301 // Pin=-40dBm +0x81c 0x68480301 // Pin=-38dBm +0x81c 0x674a0301 // Pin=-36dBm +0x81c 0x4a4c0301 // Pin=-34dBm +0x81c 0x654e0301 // Pin=-32dBm +0x81c 0x48500301 // Pin=-30dBm +0x81c 0x29520301 // Pin=-28dBm +0x81c 0x28540301 // Pin=-26dBm +0x81c 0x27560301 // Pin=-24dBm +0x81c 0x26580301 // Pin=-22dBm +0x81c 0x255a0301 // Pin=-20dBm +0x81c 0x245c0301 // Pin=-18dBm +0x81c 0x235e0301 // Pin=-16dBm +0x81c 0x07600301 // Pin=-14dBm +0x81c 0x06620301 // Pin=-12dBm +0x81c 0x05640301 // Pin=-10dBm +0x81c 0x04660301 // Pin=-08dBm +0x81c 0x03680301 // Pin=-06dBm +0x81c 0x026a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_intpa.txt old mode 100755 new mode 100644 index 6d66638be5e..2ccd2de24a1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AMP_intpa.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfe000101 // Pin=-110dBm -0x81c 0xfd020101 // Pin=-108dBm -0x81c 0xfc040101 // Pin=-106dBm -0x81c 0xfb060101 // Pin=-104dBm -0x81c 0xfa080101 // Pin=-102dBm -0x81c 0xf90a0101 // Pin=-100dBm -0x81c 0xf80c0101 // Pin=-98dBm -0x81c 0xf70e0101 // Pin=-96dBm -0x81c 0xf6100101 // Pin=-94dBm -0x81c 0xf5120101 // Pin=-92dBm -0x81c 0xf4140101 // Pin=-90dBm -0x81c 0xf3160101 // Pin=-88dBm -0x81c 0xf2180101 // Pin=-86dBm -0x81c 0xf11a0101 // Pin=-84dBm -0x81c 0xf01c0101 // Pin=-82dBm -0x81c 0xef1e0101 // Pin=-80dBm -0x81c 0xee200101 // Pin=-78dBm -0x81c 0xed220101 // Pin=-76dBm -0x81c 0xec240101 // Pin=-74dBm -0x81c 0xeb260101 // Pin=-72dBm -0x81c 0xea280101 // Pin=-70dBm -0x81c 0xe92a0101 // Pin=-68dBm -0x81c 0xe82c0101 // Pin=-66dBm -0x81c 0xe72e0101 // Pin=-64dBm -0x81c 0xe6300101 // Pin=-62dBm -0x81c 0xe5320101 // Pin=-60dBm -0x81c 0xe4340101 // Pin=-58dBm -0x81c 0xe3360101 // Pin=-56dBm -0x81c 0xa6380101 // Pin=-54dBm -0x81c 0xa53a0101 // Pin=-52dBm -0x81c 0xa43c0101 // Pin=-50dBm -0x81c 0xa33e0101 // Pin=-48dBm -0x81c 0x83400101 // Pin=-46dBm -0x81c 0x82420101 // Pin=-44dBm -0x81c 0x65440101 // Pin=-42dBm -0x81c 0x64460101 // Pin=-40dBm -0x81c 0x63480101 // Pin=-38dBm -0x81c 0x624a0101 // Pin=-36dBm -0x81c 0x614c0101 // Pin=-34dBm -0x81c 0x2a4e0101 // Pin=-32dBm -0x81c 0x29500101 // Pin=-30dBm -0x81c 0x28520101 // Pin=-28dBm -0x81c 0x27540101 // Pin=-26dBm -0x81c 0x26560101 // Pin=-24dBm -0x81c 0x25580101 // Pin=-22dBm -0x81c 0x245a0101 // Pin=-20dBm -0x81c 0x235c0101 // Pin=-18dBm -0x81c 0x225e0101 // Pin=-16dBm -0x81c 0x06600101 // Pin=-14dBm -0x81c 0x05620101 // Pin=-12dBm -0x81c 0x04640101 // Pin=-10dBm -0x81c 0x03660101 // Pin=-08dBm -0x81c 0x02680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xff000201 // Pin=-110dBm -0x81c 0xfe020201 // Pin=-108dBm -0x81c 0xfd040201 // Pin=-106dBm -0x81c 0xfc060201 // Pin=-104dBm -0x81c 0xfb080201 // Pin=-102dBm -0x81c 0xfa0a0201 // Pin=-100dBm -0x81c 0xf90c0201 // Pin=-98dBm -0x81c 0xf80e0201 // Pin=-96dBm -0x81c 0xf7100201 // Pin=-94dBm -0x81c 0xf6120201 // Pin=-92dBm -0x81c 0xf5140201 // Pin=-90dBm -0x81c 0xf4160201 // Pin=-88dBm -0x81c 0xf3180201 // Pin=-86dBm -0x81c 0xf21a0201 // Pin=-84dBm -0x81c 0xf11c0201 // Pin=-82dBm -0x81c 0xf01e0201 // Pin=-80dBm -0x81c 0xef200201 // Pin=-78dBm -0x81c 0xee220201 // Pin=-76dBm -0x81c 0xed240201 // Pin=-74dBm -0x81c 0xec260201 // Pin=-72dBm -0x81c 0xeb280201 // Pin=-70dBm -0x81c 0xea2a0201 // Pin=-68dBm -0x81c 0xe92c0201 // Pin=-66dBm -0x81c 0xe82e0201 // Pin=-64dBm -0x81c 0xe7300201 // Pin=-62dBm -0x81c 0xe6320201 // Pin=-60dBm -0x81c 0xe5340201 // Pin=-58dBm -0x81c 0xe4360201 // Pin=-56dBm -0x81c 0xe3380201 // Pin=-54dBm -0x81c 0xe23a0201 // Pin=-52dBm -0x81c 0xa53c0201 // Pin=-50dBm -0x81c 0xa43e0201 // Pin=-48dBm -0x81c 0xa3400201 // Pin=-46dBm //8->a -0x81c 0x85420201 // Pin=-44dBm //add 1 index RxBB -0x81c 0x84440201 // Pin=-42dBm //add 1 index RxBB -0x81c 0x83460201 // Pin=-40dBm //add 1 index RxBB -0x81c 0x67480201 // Pin=-38dBm //add 1 index RxBB -0x81c 0x664a0201 // Pin=-36dBm //add 1 index RxBB -0x81c 0x654c0201 // Pin=-34dBm //add 1 index RxBB -0x81c 0x644e0201 // Pin=-32dBm //add 1 index RxBB -0x81c 0x63500201 // Pin=-30dBm //2->6 -0x81c 0x28520201 // Pin=-28dBm -0x81c 0x27540201 // Pin=-26dBm -0x81c 0x26560201 // Pin=-24dBm -0x81c 0x25580201 // Pin=-22dBm -0x81c 0x245a0201 // Pin=-20dBm -0x81c 0x235c0201 // Pin=-18dBm -0x81c 0x225e0201 // Pin=-16dBm -0x81c 0x06600201 // Pin=-14dBm -0x81c 0x05620201 // Pin=-12dBm -0x81c 0x04640201 // Pin=-10dBm -0x81c 0x03660201 // Pin=-08dBm -0x81c 0x02680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xff000301 // Pin=-110dBm -0x81c 0xfe020301 // Pin=-108dBm -0x81c 0xfd040301 // Pin=-106dBm -0x81c 0xfc060301 // Pin=-104dBm -0x81c 0xfb080301 // Pin=-102dBm -0x81c 0xfa0a0301 // Pin=-100dBm -0x81c 0xf90c0301 // Pin=-98dBm -0x81c 0xf80e0301 // Pin=-96dBm -0x81c 0xf7100301 // Pin=-94dBm -0x81c 0xf6120301 // Pin=-92dBm -0x81c 0xf5140301 // Pin=-90dBm -0x81c 0xf4160301 // Pin=-88dBm -0x81c 0xf3180301 // Pin=-86dBm -0x81c 0xf21a0301 // Pin=-84dBm -0x81c 0xf11c0301 // Pin=-82dBm -0x81c 0xf01e0301 // Pin=-80dBm -0x81c 0xef200301 // Pin=-78dBm -0x81c 0xee220301 // Pin=-76dBm -0x81c 0xed240301 // Pin=-74dBm -0x81c 0xec260301 // Pin=-72dBm -0x81c 0xeb280301 // Pin=-70dBm -0x81c 0xea2a0301 // Pin=-68dBm -0x81c 0xe92c0301 // Pin=-66dBm -0x81c 0xe82e0301 // Pin=-64dBm -0x81c 0xe7300301 // Pin=-62dBm -0x81c 0xe6320301 // Pin=-60dBm -0x81c 0xe5340301 // Pin=-58dBm -0x81c 0xe4360301 // Pin=-56dBm -0x81c 0xe3380301 // Pin=-54dBm -0x81c 0xa63a0301 // Pin=-52dBm -0x81c 0xa53c0301 // Pin=-50dBm -0x81c 0xa43e0301 // Pin=-48dBm -0x81c 0xa3400301 // Pin=-46dBm -0x81c 0xa2420301 // Pin=-44dBm //8->a -0x81c 0x84440301 // Pin=-42dBm -0x81c 0x83460301 // Pin=-40dBm -0x81c 0x67480301 // Pin=-38dBm -0x81c 0x664a0301 // Pin=-36dBm -0x81c 0x654c0301 // Pin=-34dBm -0x81c 0x644e0301 // Pin=-32dBm -0x81c 0x28500301 // Pin=-30dBm //6->2 -0x81c 0x27520301 // Pin=-28dBm -0x81c 0x26540301 // Pin=-26dBm -0x81c 0x25560301 // Pin=-24dBm -0x81c 0x24580301 // Pin=-22dBm -0x81c 0x235a0301 // Pin=-20dBm -0x81c 0x225c0301 // Pin=-18dBm -0x81c 0x215e0301 // Pin=-16dBm -0x81c 0x06600301 // Pin=-14dBm -0x81c 0x05620301 // Pin=-12dBm -0x81c 0x04640301 // Pin=-10dBm -0x81c 0x03660301 // Pin=-08dBm -0x81c 0x02680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfe000101 // Pin=-110dBm +0x81c 0xfd020101 // Pin=-108dBm +0x81c 0xfc040101 // Pin=-106dBm +0x81c 0xfb060101 // Pin=-104dBm +0x81c 0xfa080101 // Pin=-102dBm +0x81c 0xf90a0101 // Pin=-100dBm +0x81c 0xf80c0101 // Pin=-98dBm +0x81c 0xf70e0101 // Pin=-96dBm +0x81c 0xf6100101 // Pin=-94dBm +0x81c 0xf5120101 // Pin=-92dBm +0x81c 0xf4140101 // Pin=-90dBm +0x81c 0xf3160101 // Pin=-88dBm +0x81c 0xf2180101 // Pin=-86dBm +0x81c 0xf11a0101 // Pin=-84dBm +0x81c 0xf01c0101 // Pin=-82dBm +0x81c 0xef1e0101 // Pin=-80dBm +0x81c 0xee200101 // Pin=-78dBm +0x81c 0xed220101 // Pin=-76dBm +0x81c 0xec240101 // Pin=-74dBm +0x81c 0xeb260101 // Pin=-72dBm +0x81c 0xea280101 // Pin=-70dBm +0x81c 0xe92a0101 // Pin=-68dBm +0x81c 0xe82c0101 // Pin=-66dBm +0x81c 0xe72e0101 // Pin=-64dBm +0x81c 0xe6300101 // Pin=-62dBm +0x81c 0xe5320101 // Pin=-60dBm +0x81c 0xe4340101 // Pin=-58dBm +0x81c 0xe3360101 // Pin=-56dBm +0x81c 0xa6380101 // Pin=-54dBm +0x81c 0xa53a0101 // Pin=-52dBm +0x81c 0xa43c0101 // Pin=-50dBm +0x81c 0xa33e0101 // Pin=-48dBm +0x81c 0x83400101 // Pin=-46dBm +0x81c 0x82420101 // Pin=-44dBm +0x81c 0x65440101 // Pin=-42dBm +0x81c 0x64460101 // Pin=-40dBm +0x81c 0x63480101 // Pin=-38dBm +0x81c 0x624a0101 // Pin=-36dBm +0x81c 0x614c0101 // Pin=-34dBm +0x81c 0x2a4e0101 // Pin=-32dBm +0x81c 0x29500101 // Pin=-30dBm +0x81c 0x28520101 // Pin=-28dBm +0x81c 0x27540101 // Pin=-26dBm +0x81c 0x26560101 // Pin=-24dBm +0x81c 0x25580101 // Pin=-22dBm +0x81c 0x245a0101 // Pin=-20dBm +0x81c 0x235c0101 // Pin=-18dBm +0x81c 0x225e0101 // Pin=-16dBm +0x81c 0x06600101 // Pin=-14dBm +0x81c 0x05620101 // Pin=-12dBm +0x81c 0x04640101 // Pin=-10dBm +0x81c 0x03660101 // Pin=-08dBm +0x81c 0x02680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xff000201 // Pin=-110dBm +0x81c 0xfe020201 // Pin=-108dBm +0x81c 0xfd040201 // Pin=-106dBm +0x81c 0xfc060201 // Pin=-104dBm +0x81c 0xfb080201 // Pin=-102dBm +0x81c 0xfa0a0201 // Pin=-100dBm +0x81c 0xf90c0201 // Pin=-98dBm +0x81c 0xf80e0201 // Pin=-96dBm +0x81c 0xf7100201 // Pin=-94dBm +0x81c 0xf6120201 // Pin=-92dBm +0x81c 0xf5140201 // Pin=-90dBm +0x81c 0xf4160201 // Pin=-88dBm +0x81c 0xf3180201 // Pin=-86dBm +0x81c 0xf21a0201 // Pin=-84dBm +0x81c 0xf11c0201 // Pin=-82dBm +0x81c 0xf01e0201 // Pin=-80dBm +0x81c 0xef200201 // Pin=-78dBm +0x81c 0xee220201 // Pin=-76dBm +0x81c 0xed240201 // Pin=-74dBm +0x81c 0xec260201 // Pin=-72dBm +0x81c 0xeb280201 // Pin=-70dBm +0x81c 0xea2a0201 // Pin=-68dBm +0x81c 0xe92c0201 // Pin=-66dBm +0x81c 0xe82e0201 // Pin=-64dBm +0x81c 0xe7300201 // Pin=-62dBm +0x81c 0xe6320201 // Pin=-60dBm +0x81c 0xe5340201 // Pin=-58dBm +0x81c 0xe4360201 // Pin=-56dBm +0x81c 0xe3380201 // Pin=-54dBm +0x81c 0xe23a0201 // Pin=-52dBm +0x81c 0xa53c0201 // Pin=-50dBm +0x81c 0xa43e0201 // Pin=-48dBm +0x81c 0xa3400201 // Pin=-46dBm //8->a +0x81c 0x85420201 // Pin=-44dBm //add 1 index RxBB +0x81c 0x84440201 // Pin=-42dBm //add 1 index RxBB +0x81c 0x83460201 // Pin=-40dBm //add 1 index RxBB +0x81c 0x67480201 // Pin=-38dBm //add 1 index RxBB +0x81c 0x664a0201 // Pin=-36dBm //add 1 index RxBB +0x81c 0x654c0201 // Pin=-34dBm //add 1 index RxBB +0x81c 0x644e0201 // Pin=-32dBm //add 1 index RxBB +0x81c 0x63500201 // Pin=-30dBm //2->6 +0x81c 0x28520201 // Pin=-28dBm +0x81c 0x27540201 // Pin=-26dBm +0x81c 0x26560201 // Pin=-24dBm +0x81c 0x25580201 // Pin=-22dBm +0x81c 0x245a0201 // Pin=-20dBm +0x81c 0x235c0201 // Pin=-18dBm +0x81c 0x225e0201 // Pin=-16dBm +0x81c 0x06600201 // Pin=-14dBm +0x81c 0x05620201 // Pin=-12dBm +0x81c 0x04640201 // Pin=-10dBm +0x81c 0x03660201 // Pin=-08dBm +0x81c 0x02680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xff000301 // Pin=-110dBm +0x81c 0xfe020301 // Pin=-108dBm +0x81c 0xfd040301 // Pin=-106dBm +0x81c 0xfc060301 // Pin=-104dBm +0x81c 0xfb080301 // Pin=-102dBm +0x81c 0xfa0a0301 // Pin=-100dBm +0x81c 0xf90c0301 // Pin=-98dBm +0x81c 0xf80e0301 // Pin=-96dBm +0x81c 0xf7100301 // Pin=-94dBm +0x81c 0xf6120301 // Pin=-92dBm +0x81c 0xf5140301 // Pin=-90dBm +0x81c 0xf4160301 // Pin=-88dBm +0x81c 0xf3180301 // Pin=-86dBm +0x81c 0xf21a0301 // Pin=-84dBm +0x81c 0xf11c0301 // Pin=-82dBm +0x81c 0xf01e0301 // Pin=-80dBm +0x81c 0xef200301 // Pin=-78dBm +0x81c 0xee220301 // Pin=-76dBm +0x81c 0xed240301 // Pin=-74dBm +0x81c 0xec260301 // Pin=-72dBm +0x81c 0xeb280301 // Pin=-70dBm +0x81c 0xea2a0301 // Pin=-68dBm +0x81c 0xe92c0301 // Pin=-66dBm +0x81c 0xe82e0301 // Pin=-64dBm +0x81c 0xe7300301 // Pin=-62dBm +0x81c 0xe6320301 // Pin=-60dBm +0x81c 0xe5340301 // Pin=-58dBm +0x81c 0xe4360301 // Pin=-56dBm +0x81c 0xe3380301 // Pin=-54dBm +0x81c 0xa63a0301 // Pin=-52dBm +0x81c 0xa53c0301 // Pin=-50dBm +0x81c 0xa43e0301 // Pin=-48dBm +0x81c 0xa3400301 // Pin=-46dBm +0x81c 0xa2420301 // Pin=-44dBm //8->a +0x81c 0x84440301 // Pin=-42dBm +0x81c 0x83460301 // Pin=-40dBm +0x81c 0x67480301 // Pin=-38dBm +0x81c 0x664a0301 // Pin=-36dBm +0x81c 0x654c0301 // Pin=-34dBm +0x81c 0x644e0301 // Pin=-32dBm +0x81c 0x28500301 // Pin=-30dBm //6->2 +0x81c 0x27520301 // Pin=-28dBm +0x81c 0x26540301 // Pin=-26dBm +0x81c 0x25560301 // Pin=-24dBm +0x81c 0x24580301 // Pin=-22dBm +0x81c 0x235a0301 // Pin=-20dBm +0x81c 0x225c0301 // Pin=-18dBm +0x81c 0x215e0301 // Pin=-16dBm +0x81c 0x06600301 // Pin=-14dBm +0x81c 0x05620301 // Pin=-12dBm +0x81c 0x04640301 // Pin=-10dBm +0x81c 0x03660301 // Pin=-08dBm +0x81c 0x02680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN.txt old mode 100755 new mode 100644 index eb47b995399..5a5c7463243 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfc000101 // Pin=-110dBm -0x81c 0xfb020101 // Pin=-108dBm -0x81c 0xfa040101 // Pin=-106dBm -0x81c 0xf9060101 // Pin=-104dBm -0x81c 0xf8080101 // Pin=-102dBm -0x81c 0xf70a0101 // Pin=-100dBm -0x81c 0xf60c0101 // Pin=-98dBm -0x81c 0xf50e0101 // Pin=-96dBm -0x81c 0xf4100101 // Pin=-94dBm -0x81c 0xf3120101 // Pin=-92dBm -0x81c 0xf2140101 // Pin=-90dBm -0x81c 0xf1160101 // Pin=-88dBm -0x81c 0xf0180101 // Pin=-86dBm -0x81c 0xef1a0101 // Pin=-84dBm -0x81c 0xee1c0101 // Pin=-82dBm -0x81c 0xed1e0101 // Pin=-80dBm -0x81c 0xec200101 // Pin=-78dBm -0x81c 0xeb220101 // Pin=-76dBm -0x81c 0xea240101 // Pin=-74dBm -0x81c 0xe9260101 // Pin=-72dBm -0x81c 0xe8280101 // Pin=-70dBm -0x81c 0xe72a0101 // Pin=-68dBm -0x81c 0xe62c0101 // Pin=-66dBm -0x81c 0xe52e0101 // Pin=-64dBm -0x81c 0xe4300101 // Pin=-62dBm -0x81c 0xe3320101 // Pin=-60dBm -0x81c 0xa7340101 // Pin=-58dBm -0x81c 0xa6360101 // Pin=-56dBm -0x81c 0xa5380101 // Pin=-54dBm -0x81c 0xa43a0101 // Pin=-52dBm -0x81c 0xa33c0101 // Pin=-50dBm -0x81c 0x693e0101 // Pin=-48dBm -0x81c 0x68400101 // Pin=-46dBm -0x81c 0x67420101 // Pin=-44dBm -0x81c 0x66440101 // Pin=-42dBm -0x81c 0x65460101 // Pin=-40dBm -0x81c 0x48480101 // Pin=-38dBm -0x81c 0x474a0101 // Pin=-36dBm -0x81c 0x464c0101 // Pin=-34dBm -0x81c 0x454e0101 // Pin=-32dBm -0x81c 0x27500101 // Pin=-30dBm -0x81c 0x26520101 // Pin=-28dBm -0x81c 0x25540101 // Pin=-26dBm -0x81c 0x24560101 // Pin=-24dBm -0x81c 0x08580101 // Pin=-22dBm -0x81c 0x075a0101 // Pin=-20dBm -0x81c 0x065c0101 // Pin=-18dBm -0x81c 0x055e0101 // Pin=-16dBm -0x81c 0x04600101 // Pin=-14dBm -0x81c 0x03620101 // Pin=-12dBm -0x81c 0x02640101 // Pin=-10dBm -0x81c 0x01660101 // Pin=-08dBm -0x81c 0x01680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xfb000201 // Pin=-110dBm -0x81c 0xfa020201 // Pin=-108dBm -0x81c 0xf9040201 // Pin=-106dBm -0x81c 0xf8060201 // Pin=-104dBm -0x81c 0xf7080201 // Pin=-102dBm -0x81c 0xf60a0201 // Pin=-100dBm -0x81c 0xf50c0201 // Pin=-98dBm -0x81c 0xf40e0201 // Pin=-96dBm -0x81c 0xf3100201 // Pin=-94dBm -0x81c 0xf2120201 // Pin=-92dBm -0x81c 0xf1140201 // Pin=-90dBm -0x81c 0xf0160201 // Pin=-88dBm -0x81c 0xef180201 // Pin=-86dBm -0x81c 0xee1a0201 // Pin=-84dBm -0x81c 0xed1c0201 // Pin=-82dBm -0x81c 0xec1e0201 // Pin=-80dBm -0x81c 0xeb200201 // Pin=-78dBm -0x81c 0xea220201 // Pin=-76dBm -0x81c 0xe9240201 // Pin=-74dBm -0x81c 0xe8260201 // Pin=-72dBm -0x81c 0xe7280201 // Pin=-70dBm -0x81c 0xe62a0201 // Pin=-68dBm -0x81c 0xe52c0201 // Pin=-66dBm -0x81c 0xe42e0201 // Pin=-64dBm -0x81c 0xe3300201 // Pin=-62dBm -0x81c 0xa7320201 // Pin=-60dBm -0x81c 0xa6340201 // Pin=-58dBm -0x81c 0xa5360201 // Pin=-56dBm -0x81c 0xa4380201 // Pin=-54dBm -0x81c 0xa33a0201 // Pin=-52dBm -0x81c 0x693c0201 // Pin=-50dBm -0x81c 0x683e0201 // Pin=-48dBm -0x81c 0x67400201 // Pin=-46dBm -0x81c 0x66420201 // Pin=-44dBm -0x81c 0x65440201 // Pin=-42dBm -0x81c 0x48460201 // Pin=-40dBm -0x81c 0x47480201 // Pin=-38dBm -0x81c 0x464a0201 // Pin=-36dBm -0x81c 0x454c0201 // Pin=-34dBm -0x81c 0x274e0201 // Pin=-32dBm -0x81c 0x26500201 // Pin=-30dBm -0x81c 0x25520201 // Pin=-28dBm -0x81c 0x24540201 // Pin=-26dBm -0x81c 0x09560201 // Pin=-24dBm -0x81c 0x08580201 // Pin=-22dBm -0x81c 0x075a0201 // Pin=-20dBm -0x81c 0x065c0201 // Pin=-18dBm -0x81c 0x055e0201 // Pin=-16dBm -0x81c 0x04600201 // Pin=-14dBm -0x81c 0x03620201 // Pin=-12dBm -0x81c 0x02640201 // Pin=-10dBm -0x81c 0x01660201 // Pin=-08dBm -0x81c 0x01680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xfd000301 // Pin=-110dBm -0x81c 0xfc020301 // Pin=-108dBm -0x81c 0xfb040301 // Pin=-106dBm -0x81c 0xfa060301 // Pin=-104dBm -0x81c 0xf9080301 // Pin=-102dBm -0x81c 0xf80a0301 // Pin=-100dBm -0x81c 0xf70c0301 // Pin=-98dBm -0x81c 0xf60e0301 // Pin=-96dBm -0x81c 0xf5100301 // Pin=-94dBm -0x81c 0xf4120301 // Pin=-92dBm -0x81c 0xf3140301 // Pin=-90dBm -0x81c 0xf2160301 // Pin=-88dBm -0x81c 0xf1180301 // Pin=-86dBm -0x81c 0xf01a0301 // Pin=-84dBm -0x81c 0xef1c0301 // Pin=-82dBm -0x81c 0xee1e0301 // Pin=-80dBm -0x81c 0xed200301 // Pin=-78dBm -0x81c 0xec220301 // Pin=-76dBm -0x81c 0xeb240301 // Pin=-74dBm -0x81c 0xea260301 // Pin=-72dBm -0x81c 0xe9280301 // Pin=-70dBm -0x81c 0xe82a0301 // Pin=-68dBm -0x81c 0xe72c0301 // Pin=-66dBm -0x81c 0xe62e0301 // Pin=-64dBm -0x81c 0xe5300301 // Pin=-62dBm -0x81c 0xe4320301 // Pin=-60dBm -0x81c 0xe3340301 // Pin=-58dBm -0x81c 0xa5360301 // Pin=-56dBm -0x81c 0xa4380301 // Pin=-54dBm -0x81c 0xa33a0301 // Pin=-52dBm -0x81c 0xa23c0301 // Pin=-50dBm -0x81c 0x693e0301 // Pin=-48dBm -0x81c 0x68400301 // Pin=-46dBm -0x81c 0x67420301 // Pin=-44dBm -0x81c 0x4a440301 // Pin=-42dBm -0x81c 0x49460301 // Pin=-40dBm -0x81c 0x48480301 // Pin=-38dBm -0x81c 0x474a0301 // Pin=-36dBm -0x81c 0x294c0301 // Pin=-34dBm -0x81c 0x284e0301 // Pin=-32dBm -0x81c 0x27500301 // Pin=-30dBm -0x81c 0x26520301 // Pin=-28dBm -0x81c 0x25540301 // Pin=-26dBm -0x81c 0x24560301 // Pin=-24dBm -0x81c 0x08580301 // Pin=-22dBm -0x81c 0x075a0301 // Pin=-20dBm -0x81c 0x065c0301 // Pin=-18dBm -0x81c 0x055e0301 // Pin=-16dBm -0x81c 0x04600301 // Pin=-14dBm -0x81c 0x03620301 // Pin=-12dBm -0x81c 0x02640301 // Pin=-10dBm -0x81c 0x01660301 // Pin=-08dBm -0x81c 0x01680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfc000101 // Pin=-110dBm +0x81c 0xfb020101 // Pin=-108dBm +0x81c 0xfa040101 // Pin=-106dBm +0x81c 0xf9060101 // Pin=-104dBm +0x81c 0xf8080101 // Pin=-102dBm +0x81c 0xf70a0101 // Pin=-100dBm +0x81c 0xf60c0101 // Pin=-98dBm +0x81c 0xf50e0101 // Pin=-96dBm +0x81c 0xf4100101 // Pin=-94dBm +0x81c 0xf3120101 // Pin=-92dBm +0x81c 0xf2140101 // Pin=-90dBm +0x81c 0xf1160101 // Pin=-88dBm +0x81c 0xf0180101 // Pin=-86dBm +0x81c 0xef1a0101 // Pin=-84dBm +0x81c 0xee1c0101 // Pin=-82dBm +0x81c 0xed1e0101 // Pin=-80dBm +0x81c 0xec200101 // Pin=-78dBm +0x81c 0xeb220101 // Pin=-76dBm +0x81c 0xea240101 // Pin=-74dBm +0x81c 0xe9260101 // Pin=-72dBm +0x81c 0xe8280101 // Pin=-70dBm +0x81c 0xe72a0101 // Pin=-68dBm +0x81c 0xe62c0101 // Pin=-66dBm +0x81c 0xe52e0101 // Pin=-64dBm +0x81c 0xe4300101 // Pin=-62dBm +0x81c 0xe3320101 // Pin=-60dBm +0x81c 0xa7340101 // Pin=-58dBm +0x81c 0xa6360101 // Pin=-56dBm +0x81c 0xa5380101 // Pin=-54dBm +0x81c 0xa43a0101 // Pin=-52dBm +0x81c 0xa33c0101 // Pin=-50dBm +0x81c 0x693e0101 // Pin=-48dBm +0x81c 0x68400101 // Pin=-46dBm +0x81c 0x67420101 // Pin=-44dBm +0x81c 0x66440101 // Pin=-42dBm +0x81c 0x65460101 // Pin=-40dBm +0x81c 0x48480101 // Pin=-38dBm +0x81c 0x474a0101 // Pin=-36dBm +0x81c 0x464c0101 // Pin=-34dBm +0x81c 0x454e0101 // Pin=-32dBm +0x81c 0x27500101 // Pin=-30dBm +0x81c 0x26520101 // Pin=-28dBm +0x81c 0x25540101 // Pin=-26dBm +0x81c 0x24560101 // Pin=-24dBm +0x81c 0x08580101 // Pin=-22dBm +0x81c 0x075a0101 // Pin=-20dBm +0x81c 0x065c0101 // Pin=-18dBm +0x81c 0x055e0101 // Pin=-16dBm +0x81c 0x04600101 // Pin=-14dBm +0x81c 0x03620101 // Pin=-12dBm +0x81c 0x02640101 // Pin=-10dBm +0x81c 0x01660101 // Pin=-08dBm +0x81c 0x01680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xfb000201 // Pin=-110dBm +0x81c 0xfa020201 // Pin=-108dBm +0x81c 0xf9040201 // Pin=-106dBm +0x81c 0xf8060201 // Pin=-104dBm +0x81c 0xf7080201 // Pin=-102dBm +0x81c 0xf60a0201 // Pin=-100dBm +0x81c 0xf50c0201 // Pin=-98dBm +0x81c 0xf40e0201 // Pin=-96dBm +0x81c 0xf3100201 // Pin=-94dBm +0x81c 0xf2120201 // Pin=-92dBm +0x81c 0xf1140201 // Pin=-90dBm +0x81c 0xf0160201 // Pin=-88dBm +0x81c 0xef180201 // Pin=-86dBm +0x81c 0xee1a0201 // Pin=-84dBm +0x81c 0xed1c0201 // Pin=-82dBm +0x81c 0xec1e0201 // Pin=-80dBm +0x81c 0xeb200201 // Pin=-78dBm +0x81c 0xea220201 // Pin=-76dBm +0x81c 0xe9240201 // Pin=-74dBm +0x81c 0xe8260201 // Pin=-72dBm +0x81c 0xe7280201 // Pin=-70dBm +0x81c 0xe62a0201 // Pin=-68dBm +0x81c 0xe52c0201 // Pin=-66dBm +0x81c 0xe42e0201 // Pin=-64dBm +0x81c 0xe3300201 // Pin=-62dBm +0x81c 0xa7320201 // Pin=-60dBm +0x81c 0xa6340201 // Pin=-58dBm +0x81c 0xa5360201 // Pin=-56dBm +0x81c 0xa4380201 // Pin=-54dBm +0x81c 0xa33a0201 // Pin=-52dBm +0x81c 0x693c0201 // Pin=-50dBm +0x81c 0x683e0201 // Pin=-48dBm +0x81c 0x67400201 // Pin=-46dBm +0x81c 0x66420201 // Pin=-44dBm +0x81c 0x65440201 // Pin=-42dBm +0x81c 0x48460201 // Pin=-40dBm +0x81c 0x47480201 // Pin=-38dBm +0x81c 0x464a0201 // Pin=-36dBm +0x81c 0x454c0201 // Pin=-34dBm +0x81c 0x274e0201 // Pin=-32dBm +0x81c 0x26500201 // Pin=-30dBm +0x81c 0x25520201 // Pin=-28dBm +0x81c 0x24540201 // Pin=-26dBm +0x81c 0x09560201 // Pin=-24dBm +0x81c 0x08580201 // Pin=-22dBm +0x81c 0x075a0201 // Pin=-20dBm +0x81c 0x065c0201 // Pin=-18dBm +0x81c 0x055e0201 // Pin=-16dBm +0x81c 0x04600201 // Pin=-14dBm +0x81c 0x03620201 // Pin=-12dBm +0x81c 0x02640201 // Pin=-10dBm +0x81c 0x01660201 // Pin=-08dBm +0x81c 0x01680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xfd000301 // Pin=-110dBm +0x81c 0xfc020301 // Pin=-108dBm +0x81c 0xfb040301 // Pin=-106dBm +0x81c 0xfa060301 // Pin=-104dBm +0x81c 0xf9080301 // Pin=-102dBm +0x81c 0xf80a0301 // Pin=-100dBm +0x81c 0xf70c0301 // Pin=-98dBm +0x81c 0xf60e0301 // Pin=-96dBm +0x81c 0xf5100301 // Pin=-94dBm +0x81c 0xf4120301 // Pin=-92dBm +0x81c 0xf3140301 // Pin=-90dBm +0x81c 0xf2160301 // Pin=-88dBm +0x81c 0xf1180301 // Pin=-86dBm +0x81c 0xf01a0301 // Pin=-84dBm +0x81c 0xef1c0301 // Pin=-82dBm +0x81c 0xee1e0301 // Pin=-80dBm +0x81c 0xed200301 // Pin=-78dBm +0x81c 0xec220301 // Pin=-76dBm +0x81c 0xeb240301 // Pin=-74dBm +0x81c 0xea260301 // Pin=-72dBm +0x81c 0xe9280301 // Pin=-70dBm +0x81c 0xe82a0301 // Pin=-68dBm +0x81c 0xe72c0301 // Pin=-66dBm +0x81c 0xe62e0301 // Pin=-64dBm +0x81c 0xe5300301 // Pin=-62dBm +0x81c 0xe4320301 // Pin=-60dBm +0x81c 0xe3340301 // Pin=-58dBm +0x81c 0xa5360301 // Pin=-56dBm +0x81c 0xa4380301 // Pin=-54dBm +0x81c 0xa33a0301 // Pin=-52dBm +0x81c 0xa23c0301 // Pin=-50dBm +0x81c 0x693e0301 // Pin=-48dBm +0x81c 0x68400301 // Pin=-46dBm +0x81c 0x67420301 // Pin=-44dBm +0x81c 0x4a440301 // Pin=-42dBm +0x81c 0x49460301 // Pin=-40dBm +0x81c 0x48480301 // Pin=-38dBm +0x81c 0x474a0301 // Pin=-36dBm +0x81c 0x294c0301 // Pin=-34dBm +0x81c 0x284e0301 // Pin=-32dBm +0x81c 0x27500301 // Pin=-30dBm +0x81c 0x26520301 // Pin=-28dBm +0x81c 0x25540301 // Pin=-26dBm +0x81c 0x24560301 // Pin=-24dBm +0x81c 0x08580301 // Pin=-22dBm +0x81c 0x075a0301 // Pin=-20dBm +0x81c 0x065c0301 // Pin=-18dBm +0x81c 0x055e0301 // Pin=-16dBm +0x81c 0x04600301 // Pin=-14dBm +0x81c 0x03620301 // Pin=-12dBm +0x81c 0x02640301 // Pin=-10dBm +0x81c 0x01660301 // Pin=-08dBm +0x81c 0x01680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN_extpa.txt index 66e8f0d424f..e163632f6e0 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881AN_extpa.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xff000101 // Pin=-110dBm -0x81c 0xff020101 // Pin=-108dBm -0x81c 0xfe040101 // Pin=-106dBm -0x81c 0xfd060101 // Pin=-104dBm -0x81c 0xfc080101 // Pin=-102dBm -0x81c 0xfb0a0101 // Pin=-100dBm -0x81c 0xfa0c0101 // Pin=-98dBm -0x81c 0xf90e0101 // Pin=-96dBm -0x81c 0xf8100101 // Pin=-94dBm -0x81c 0xf7120101 // Pin=-92dBm -0x81c 0xf6140101 // Pin=-90dBm -0x81c 0xf5160101 // Pin=-88dBm -0x81c 0xf4180101 // Pin=-86dBm -0x81c 0xf31a0101 // Pin=-84dBm -0x81c 0xf21c0101 // Pin=-82dBm -0x81c 0xf11e0101 // Pin=-80dBm -0x81c 0xf0200101 // Pin=-78dBm -0x81c 0xef220101 // Pin=-76dBm -0x81c 0xee240101 // Pin=-74dBm -0x81c 0xed260101 // Pin=-72dBm -0x81c 0xec280101 // Pin=-70dBm -0x81c 0xeb2a0101 // Pin=-68dBm -0x81c 0xea2c0101 // Pin=-66dBm -0x81c 0xe92e0101 // Pin=-64dBm -0x81c 0xe8300101 // Pin=-62dBm -0x81c 0xe7320101 // Pin=-60dBm -0x81c 0xe6340101 // Pin=-58dBm -0x81c 0xe5360101 // Pin=-56dBm -0x81c 0xe4380101 // Pin=-54dBm -0x81c 0xe33a0101 // Pin=-52dBm -0x81c 0xa73c0101 // Pin=-50dBm -0x81c 0xa63e0101 // Pin=-48dBm -0x81c 0xa5400101 // Pin=-46dBm -0x81c 0x86420101 // Pin=-44dBm -0x81c 0x85440101 // Pin=-42dBm -0x81c 0x84460101 // Pin=-40dBm -0x81c 0x83480101 // Pin=-38dBm -0x81c 0x674a0101 // Pin=-36dBm -0x81c 0x664c0101 // Pin=-34dBm -0x81c 0x654e0101 // Pin=-32dBm -0x81c 0x48500101 // Pin=-30dBm -0x81c 0x47520101 // Pin=-28dBm -0x81c 0x29540101 // Pin=-26dBm -0x81c 0x28560101 // Pin=-24dBm -0x81c 0x27580101 // Pin=-22dBm -0x81c 0x265a0101 // Pin=-20dBm -0x81c 0x255c0101 // Pin=-18dBm -0x81c 0x245e0101 // Pin=-16dBm -0x81c 0x23600101 // Pin=-14dBm -0x81c 0x22620101 // Pin=-12dBm -0x81c 0x07640101 // Pin=-10dBm -0x81c 0x06660101 // Pin=-08dBm -0x81c 0x05680101 // Pin=-06dBm -0x81c 0x046a0101 // Pin=-04dBm -0x81c 0x036c0101 // Pin=-02dBm -0x81c 0x026e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xff000201 // Pin=-110dBm -0x81c 0xff020201 // Pin=-108dBm -0x81c 0xfe040201 // Pin=-106dBm -0x81c 0xfd060201 // Pin=-104dBm -0x81c 0xfc080201 // Pin=-102dBm -0x81c 0xfb0a0201 // Pin=-100dBm -0x81c 0xfa0c0201 // Pin=-98dBm -0x81c 0xf90e0201 // Pin=-96dBm -0x81c 0xf8100201 // Pin=-94dBm -0x81c 0xf7120201 // Pin=-92dBm -0x81c 0xf6140201 // Pin=-90dBm -0x81c 0xf5160201 // Pin=-88dBm -0x81c 0xf4180201 // Pin=-86dBm -0x81c 0xf31a0201 // Pin=-84dBm -0x81c 0xf21c0201 // Pin=-82dBm -0x81c 0xf11e0201 // Pin=-80dBm -0x81c 0xf0200201 // Pin=-78dBm -0x81c 0xef220201 // Pin=-76dBm -0x81c 0xee240201 // Pin=-74dBm -0x81c 0xed260201 // Pin=-72dBm -0x81c 0xec280201 // Pin=-70dBm -0x81c 0xeb2a0201 // Pin=-68dBm -0x81c 0xea2c0201 // Pin=-66dBm -0x81c 0xe92e0201 // Pin=-64dBm -0x81c 0xe8300201 // Pin=-62dBm -0x81c 0xe7320201 // Pin=-60dBm -0x81c 0xc9340201 // Pin=-58dBm -0x81c 0xe5360201 // Pin=-56dBm -0x81c 0xe4380201 // Pin=-54dBm -0x81c 0xe33a0201 // Pin=-52dBm -0x81c 0xa73c0201 // Pin=-50dBm -0x81c 0xa63e0201 // Pin=-48dBm -0x81c 0xa5400201 // Pin=-46dBm -0x81c 0xa4420201 // Pin=-44dBm -0x81c 0xa3440201 // Pin=-42dBm -0x81c 0x84460201 // Pin=-40dBm -0x81c 0x68480201 // Pin=-38dBm -0x81c 0x674a0201 // Pin=-36dBm -0x81c 0x664c0201 // Pin=-34dBm -0x81c 0x654e0201 // Pin=-32dBm -0x81c 0x64500201 // Pin=-30dBm -0x81c 0x47520201 // Pin=-28dBm -0x81c 0x29540201 // Pin=-26dBm -0x81c 0x28560201 // Pin=-24dBm -0x81c 0x27580201 // Pin=-22dBm -0x81c 0x265a0201 // Pin=-20dBm -0x81c 0x255c0201 // Pin=-18dBm -0x81c 0x245e0201 // Pin=-16dBm -0x81c 0x23600201 // Pin=-14dBm -0x81c 0x08620201 // Pin=-12dBm -0x81c 0x07640201 // Pin=-10dBm -0x81c 0x06660201 // Pin=-08dBm -0x81c 0x05680201 // Pin=-06dBm -0x81c 0x046a0201 // Pin=-04dBm -0x81c 0x036c0201 // Pin=-02dBm -0x81c 0x026e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xff000301 // Pin=-110dBm -0x81c 0xff020301 // Pin=-108dBm -0x81c 0xfe040301 // Pin=-106dBm -0x81c 0xfd060301 // Pin=-104dBm -0x81c 0xfc080301 // Pin=-102dBm -0x81c 0xfb0a0301 // Pin=-100dBm -0x81c 0xfa0c0301 // Pin=-98dBm -0x81c 0xf90e0301 // Pin=-96dBm -0x81c 0xf8100301 // Pin=-94dBm -0x81c 0xf7120301 // Pin=-92dBm -0x81c 0xf6140301 // Pin=-90dBm -0x81c 0xf5160301 // Pin=-88dBm -0x81c 0xf4180301 // Pin=-86dBm -0x81c 0xf31a0301 // Pin=-84dBm -0x81c 0xf21c0301 // Pin=-82dBm -0x81c 0xf11e0301 // Pin=-80dBm -0x81c 0xf0200301 // Pin=-78dBm -0x81c 0xef220301 // Pin=-76dBm -0x81c 0xee240301 // Pin=-74dBm -0x81c 0xed260301 // Pin=-72dBm -0x81c 0xec280301 // Pin=-70dBm -0x81c 0xeb2a0301 // Pin=-68dBm -0x81c 0xea2c0301 // Pin=-66dBm -0x81c 0xe92e0301 // Pin=-64dBm -0x81c 0xe8300301 // Pin=-62dBm -0x81c 0xe7320301 // Pin=-60dBm -0x81c 0xe6340301 // Pin=-58dBm -0x81c 0xe5360301 // Pin=-56dBm -0x81c 0xe4380301 // Pin=-54dBm -0x81c 0xa73a0301 // Pin=-52dBm -0x81c 0xa63c0301 // Pin=-50dBm -0x81c 0xa53e0301 // Pin=-48dBm -0x81c 0xa4400301 // Pin=-46dBm -0x81c 0xa3420301 // Pin=-44dBm -0x81c 0x6a440301 // Pin=-42dBm -0x81c 0x69460301 // Pin=-40dBm -0x81c 0x68480301 // Pin=-38dBm -0x81c 0x674a0301 // Pin=-36dBm -0x81c 0x4a4c0301 // Pin=-34dBm -0x81c 0x654e0301 // Pin=-32dBm -0x81c 0x48500301 // Pin=-30dBm -0x81c 0x29520301 // Pin=-28dBm -0x81c 0x28540301 // Pin=-26dBm -0x81c 0x27560301 // Pin=-24dBm -0x81c 0x26580301 // Pin=-22dBm -0x81c 0x255a0301 // Pin=-20dBm -0x81c 0x245c0301 // Pin=-18dBm -0x81c 0x235e0301 // Pin=-16dBm -0x81c 0x07600301 // Pin=-14dBm -0x81c 0x06620301 // Pin=-12dBm -0x81c 0x05640301 // Pin=-10dBm -0x81c 0x04660301 // Pin=-08dBm -0x81c 0x03680301 // Pin=-06dBm -0x81c 0x026a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xff000101 // Pin=-110dBm +0x81c 0xff020101 // Pin=-108dBm +0x81c 0xfe040101 // Pin=-106dBm +0x81c 0xfd060101 // Pin=-104dBm +0x81c 0xfc080101 // Pin=-102dBm +0x81c 0xfb0a0101 // Pin=-100dBm +0x81c 0xfa0c0101 // Pin=-98dBm +0x81c 0xf90e0101 // Pin=-96dBm +0x81c 0xf8100101 // Pin=-94dBm +0x81c 0xf7120101 // Pin=-92dBm +0x81c 0xf6140101 // Pin=-90dBm +0x81c 0xf5160101 // Pin=-88dBm +0x81c 0xf4180101 // Pin=-86dBm +0x81c 0xf31a0101 // Pin=-84dBm +0x81c 0xf21c0101 // Pin=-82dBm +0x81c 0xf11e0101 // Pin=-80dBm +0x81c 0xf0200101 // Pin=-78dBm +0x81c 0xef220101 // Pin=-76dBm +0x81c 0xee240101 // Pin=-74dBm +0x81c 0xed260101 // Pin=-72dBm +0x81c 0xec280101 // Pin=-70dBm +0x81c 0xeb2a0101 // Pin=-68dBm +0x81c 0xea2c0101 // Pin=-66dBm +0x81c 0xe92e0101 // Pin=-64dBm +0x81c 0xe8300101 // Pin=-62dBm +0x81c 0xe7320101 // Pin=-60dBm +0x81c 0xe6340101 // Pin=-58dBm +0x81c 0xe5360101 // Pin=-56dBm +0x81c 0xe4380101 // Pin=-54dBm +0x81c 0xe33a0101 // Pin=-52dBm +0x81c 0xa73c0101 // Pin=-50dBm +0x81c 0xa63e0101 // Pin=-48dBm +0x81c 0xa5400101 // Pin=-46dBm +0x81c 0x86420101 // Pin=-44dBm +0x81c 0x85440101 // Pin=-42dBm +0x81c 0x84460101 // Pin=-40dBm +0x81c 0x83480101 // Pin=-38dBm +0x81c 0x674a0101 // Pin=-36dBm +0x81c 0x664c0101 // Pin=-34dBm +0x81c 0x654e0101 // Pin=-32dBm +0x81c 0x48500101 // Pin=-30dBm +0x81c 0x47520101 // Pin=-28dBm +0x81c 0x29540101 // Pin=-26dBm +0x81c 0x28560101 // Pin=-24dBm +0x81c 0x27580101 // Pin=-22dBm +0x81c 0x265a0101 // Pin=-20dBm +0x81c 0x255c0101 // Pin=-18dBm +0x81c 0x245e0101 // Pin=-16dBm +0x81c 0x23600101 // Pin=-14dBm +0x81c 0x22620101 // Pin=-12dBm +0x81c 0x07640101 // Pin=-10dBm +0x81c 0x06660101 // Pin=-08dBm +0x81c 0x05680101 // Pin=-06dBm +0x81c 0x046a0101 // Pin=-04dBm +0x81c 0x036c0101 // Pin=-02dBm +0x81c 0x026e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xff000201 // Pin=-110dBm +0x81c 0xff020201 // Pin=-108dBm +0x81c 0xfe040201 // Pin=-106dBm +0x81c 0xfd060201 // Pin=-104dBm +0x81c 0xfc080201 // Pin=-102dBm +0x81c 0xfb0a0201 // Pin=-100dBm +0x81c 0xfa0c0201 // Pin=-98dBm +0x81c 0xf90e0201 // Pin=-96dBm +0x81c 0xf8100201 // Pin=-94dBm +0x81c 0xf7120201 // Pin=-92dBm +0x81c 0xf6140201 // Pin=-90dBm +0x81c 0xf5160201 // Pin=-88dBm +0x81c 0xf4180201 // Pin=-86dBm +0x81c 0xf31a0201 // Pin=-84dBm +0x81c 0xf21c0201 // Pin=-82dBm +0x81c 0xf11e0201 // Pin=-80dBm +0x81c 0xf0200201 // Pin=-78dBm +0x81c 0xef220201 // Pin=-76dBm +0x81c 0xee240201 // Pin=-74dBm +0x81c 0xed260201 // Pin=-72dBm +0x81c 0xec280201 // Pin=-70dBm +0x81c 0xeb2a0201 // Pin=-68dBm +0x81c 0xea2c0201 // Pin=-66dBm +0x81c 0xe92e0201 // Pin=-64dBm +0x81c 0xe8300201 // Pin=-62dBm +0x81c 0xe7320201 // Pin=-60dBm +0x81c 0xc9340201 // Pin=-58dBm +0x81c 0xe5360201 // Pin=-56dBm +0x81c 0xe4380201 // Pin=-54dBm +0x81c 0xe33a0201 // Pin=-52dBm +0x81c 0xa73c0201 // Pin=-50dBm +0x81c 0xa63e0201 // Pin=-48dBm +0x81c 0xa5400201 // Pin=-46dBm +0x81c 0xa4420201 // Pin=-44dBm +0x81c 0xa3440201 // Pin=-42dBm +0x81c 0x84460201 // Pin=-40dBm +0x81c 0x68480201 // Pin=-38dBm +0x81c 0x674a0201 // Pin=-36dBm +0x81c 0x664c0201 // Pin=-34dBm +0x81c 0x654e0201 // Pin=-32dBm +0x81c 0x64500201 // Pin=-30dBm +0x81c 0x47520201 // Pin=-28dBm +0x81c 0x29540201 // Pin=-26dBm +0x81c 0x28560201 // Pin=-24dBm +0x81c 0x27580201 // Pin=-22dBm +0x81c 0x265a0201 // Pin=-20dBm +0x81c 0x255c0201 // Pin=-18dBm +0x81c 0x245e0201 // Pin=-16dBm +0x81c 0x23600201 // Pin=-14dBm +0x81c 0x08620201 // Pin=-12dBm +0x81c 0x07640201 // Pin=-10dBm +0x81c 0x06660201 // Pin=-08dBm +0x81c 0x05680201 // Pin=-06dBm +0x81c 0x046a0201 // Pin=-04dBm +0x81c 0x036c0201 // Pin=-02dBm +0x81c 0x026e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xff000301 // Pin=-110dBm +0x81c 0xff020301 // Pin=-108dBm +0x81c 0xfe040301 // Pin=-106dBm +0x81c 0xfd060301 // Pin=-104dBm +0x81c 0xfc080301 // Pin=-102dBm +0x81c 0xfb0a0301 // Pin=-100dBm +0x81c 0xfa0c0301 // Pin=-98dBm +0x81c 0xf90e0301 // Pin=-96dBm +0x81c 0xf8100301 // Pin=-94dBm +0x81c 0xf7120301 // Pin=-92dBm +0x81c 0xf6140301 // Pin=-90dBm +0x81c 0xf5160301 // Pin=-88dBm +0x81c 0xf4180301 // Pin=-86dBm +0x81c 0xf31a0301 // Pin=-84dBm +0x81c 0xf21c0301 // Pin=-82dBm +0x81c 0xf11e0301 // Pin=-80dBm +0x81c 0xf0200301 // Pin=-78dBm +0x81c 0xef220301 // Pin=-76dBm +0x81c 0xee240301 // Pin=-74dBm +0x81c 0xed260301 // Pin=-72dBm +0x81c 0xec280301 // Pin=-70dBm +0x81c 0xeb2a0301 // Pin=-68dBm +0x81c 0xea2c0301 // Pin=-66dBm +0x81c 0xe92e0301 // Pin=-64dBm +0x81c 0xe8300301 // Pin=-62dBm +0x81c 0xe7320301 // Pin=-60dBm +0x81c 0xe6340301 // Pin=-58dBm +0x81c 0xe5360301 // Pin=-56dBm +0x81c 0xe4380301 // Pin=-54dBm +0x81c 0xa73a0301 // Pin=-52dBm +0x81c 0xa63c0301 // Pin=-50dBm +0x81c 0xa53e0301 // Pin=-48dBm +0x81c 0xa4400301 // Pin=-46dBm +0x81c 0xa3420301 // Pin=-44dBm +0x81c 0x6a440301 // Pin=-42dBm +0x81c 0x69460301 // Pin=-40dBm +0x81c 0x68480301 // Pin=-38dBm +0x81c 0x674a0301 // Pin=-36dBm +0x81c 0x4a4c0301 // Pin=-34dBm +0x81c 0x654e0301 // Pin=-32dBm +0x81c 0x48500301 // Pin=-30dBm +0x81c 0x29520301 // Pin=-28dBm +0x81c 0x28540301 // Pin=-26dBm +0x81c 0x27560301 // Pin=-24dBm +0x81c 0x26580301 // Pin=-22dBm +0x81c 0x255a0301 // Pin=-20dBm +0x81c 0x245c0301 // Pin=-18dBm +0x81c 0x235e0301 // Pin=-16dBm +0x81c 0x07600301 // Pin=-14dBm +0x81c 0x06620301 // Pin=-12dBm +0x81c 0x05640301 // Pin=-10dBm +0x81c 0x04660301 // Pin=-08dBm +0x81c 0x03680301 // Pin=-06dBm +0x81c 0x026a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881Am.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881Am.txt old mode 100755 new mode 100644 index d40b08699b6..b9c2dbe6c79 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881Am.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/AGC_TAB_8881Am.txt @@ -1,263 +1,263 @@ -//RL6310_MAC_PHY_RF_Parameter_v015_20130702 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb31c0001 // Pin=-82dBm -0x81c 0xb21e0001 // Pin=-80dBm -0x81c 0xb1200001 // Pin=-78dBm -0x81c 0xb0220001 // Pin=-76dBm -0x81c 0xaf240001 // Pin=-74dBm -0x81c 0xae260001 // Pin=-72dBm -0x81c 0xad280001 // Pin=-70dBm -0x81c 0xac2a0001 // Pin=-68dBm -0x81c 0xab2c0001 // Pin=-66dBm -0x81c 0xaa2e0001 // Pin=-64dBm -0x81c 0xa9300001 // Pin=-62dBm -0x81c 0xa8320001 // Pin=-60dBm -0x81c 0xa7340001 // Pin=-58dBm -0x81c 0xa6360001 // Pin=-56dBm -0x81c 0xa5380001 // Pin=-54dBm -0x81c 0xa43a0001 // Pin=-52dBm -0x81c 0xa33c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G Low Band) -0x81c 0xfe000101 // Pin=-110dBm -0x81c 0xfd020101 // Pin=-108dBm -0x81c 0xfc040101 // Pin=-106dBm -0x81c 0xfb060101 // Pin=-104dBm -0x81c 0xfa080101 // Pin=-102dBm -0x81c 0xf90a0101 // Pin=-100dBm -0x81c 0xf80c0101 // Pin=-98dBm -0x81c 0xf70e0101 // Pin=-96dBm -0x81c 0xf6100101 // Pin=-94dBm -0x81c 0xf5120101 // Pin=-92dBm -0x81c 0xf4140101 // Pin=-90dBm -0x81c 0xf3160101 // Pin=-88dBm -0x81c 0xf2180101 // Pin=-86dBm -0x81c 0xf11a0101 // Pin=-84dBm -0x81c 0xf01c0101 // Pin=-82dBm -0x81c 0xef1e0101 // Pin=-80dBm -0x81c 0xee200101 // Pin=-78dBm -0x81c 0xed220101 // Pin=-76dBm -0x81c 0xec240101 // Pin=-74dBm -0x81c 0xeb260101 // Pin=-72dBm -0x81c 0xea280101 // Pin=-70dBm -0x81c 0xe92a0101 // Pin=-68dBm -0x81c 0xe82c0101 // Pin=-66dBm -0x81c 0xe72e0101 // Pin=-64dBm -0x81c 0xe6300101 // Pin=-62dBm -0x81c 0xe5320101 // Pin=-60dBm -0x81c 0xe4340101 // Pin=-58dBm -0x81c 0xe3360101 // Pin=-56dBm -0x81c 0xa6380101 // Pin=-54dBm -0x81c 0xa53a0101 // Pin=-52dBm -0x81c 0xa43c0101 // Pin=-50dBm -0x81c 0xa33e0101 // Pin=-48dBm -0x81c 0x83400101 // Pin=-46dBm -0x81c 0x82420101 // Pin=-44dBm -0x81c 0x65440101 // Pin=-42dBm -0x81c 0x64460101 // Pin=-40dBm -0x81c 0x63480101 // Pin=-38dBm -0x81c 0x624a0101 // Pin=-36dBm -0x81c 0x614c0101 // Pin=-34dBm -0x81c 0x2a4e0101 // Pin=-32dBm -0x81c 0x29500101 // Pin=-30dBm -0x81c 0x28520101 // Pin=-28dBm -0x81c 0x27540101 // Pin=-26dBm -0x81c 0x26560101 // Pin=-24dBm -0x81c 0x25580101 // Pin=-22dBm -0x81c 0x245a0101 // Pin=-20dBm -0x81c 0x235c0101 // Pin=-18dBm -0x81c 0x225e0101 // Pin=-16dBm -0x81c 0x06600101 // Pin=-14dBm -0x81c 0x05620101 // Pin=-12dBm -0x81c 0x04640101 // Pin=-10dBm -0x81c 0x03660101 // Pin=-08dBm -0x81c 0x02680101 // Pin=-06dBm -0x81c 0x016a0101 // Pin=-04dBm -0x81c 0x016c0101 // Pin=-02dBm -0x81c 0x016e0101 // Pin=-00dBm -0x81c 0x01700101 // Pin=+02dBm -0x81c 0x01720101 // Pin=+04dBm -0x81c 0x01740101 // Pin=+06dBm -0x81c 0x01760101 // Pin=+08dBm -0x81c 0x01780101 // Pin=+10dBm -0x81c 0x017a0101 // Pin=+12dBm -0x81c 0x017c0101 // Pin=+14dBm -0x81c 0x017e0101 // Pin=+16dBm -// AGC_TABLE 2 (5G Mid band) -0x81c 0xff000201 // Pin=-110dBm -0x81c 0xfe020201 // Pin=-108dBm -0x81c 0xfd040201 // Pin=-106dBm -0x81c 0xfc060201 // Pin=-104dBm -0x81c 0xfb080201 // Pin=-102dBm -0x81c 0xfa0a0201 // Pin=-100dBm -0x81c 0xf90c0201 // Pin=-98dBm -0x81c 0xf80e0201 // Pin=-96dBm -0x81c 0xf7100201 // Pin=-94dBm -0x81c 0xf6120201 // Pin=-92dBm -0x81c 0xf5140201 // Pin=-90dBm -0x81c 0xf4160201 // Pin=-88dBm -0x81c 0xf3180201 // Pin=-86dBm -0x81c 0xf21a0201 // Pin=-84dBm -0x81c 0xf11c0201 // Pin=-82dBm -0x81c 0xf01e0201 // Pin=-80dBm -0x81c 0xef200201 // Pin=-78dBm -0x81c 0xee220201 // Pin=-76dBm -0x81c 0xed240201 // Pin=-74dBm -0x81c 0xec260201 // Pin=-72dBm -0x81c 0xeb280201 // Pin=-70dBm -0x81c 0xea2a0201 // Pin=-68dBm -0x81c 0xe92c0201 // Pin=-66dBm -0x81c 0xe82e0201 // Pin=-64dBm -0x81c 0xe7300201 // Pin=-62dBm -0x81c 0xe6320201 // Pin=-60dBm -0x81c 0xe5340201 // Pin=-58dBm -0x81c 0xe4360201 // Pin=-56dBm -0x81c 0xe3380201 // Pin=-54dBm -0x81c 0xe23a0201 // Pin=-52dBm -0x81c 0xa53c0201 // Pin=-50dBm -0x81c 0xa43e0201 // Pin=-48dBm -0x81c 0x85400201 // Pin=-46dBm -0x81c 0x84420201 // Pin=-44dBm -0x81c 0x83440201 // Pin=-42dBm -0x81c 0x82460201 // Pin=-40dBm -0x81c 0x65480201 // Pin=-38dBm -0x81c 0x644a0201 // Pin=-36dBm -0x81c 0x634c0201 // Pin=-34dBm -0x81c 0x624e0201 // Pin=-32dBm -0x81c 0x2a500201 // Pin=-30dBm -0x81c 0x29520201 // Pin=-28dBm -0x81c 0x28540201 // Pin=-26dBm -0x81c 0x27560201 // Pin=-24dBm -0x81c 0x26580201 // Pin=-22dBm -0x81c 0x255a0201 // Pin=-20dBm -0x81c 0x245c0201 // Pin=-18dBm -0x81c 0x235e0201 // Pin=-16dBm -0x81c 0x06600201 // Pin=-14dBm -0x81c 0x05620201 // Pin=-12dBm -0x81c 0x04640201 // Pin=-10dBm -0x81c 0x03660201 // Pin=-08dBm -0x81c 0x02680201 // Pin=-06dBm -0x81c 0x016a0201 // Pin=-04dBm -0x81c 0x016c0201 // Pin=-02dBm -0x81c 0x016e0201 // Pin=-00dBm -0x81c 0x01700201 // Pin=+02dBm -0x81c 0x01720201 // Pin=+04dBm -0x81c 0x01740201 // Pin=+06dBm -0x81c 0x01760201 // Pin=+08dBm -0x81c 0x01780201 // Pin=+10dBm -0x81c 0x017a0201 // Pin=+12dBm -0x81c 0x017c0201 // Pin=+14dBm -0x81c 0x017e0201 // Pin=+16dBm -// AGC_TABLE 3 (5G High band) -0x81c 0xff000301 // Pin=-110dBm -0x81c 0xfe020301 // Pin=-108dBm -0x81c 0xfd040301 // Pin=-106dBm -0x81c 0xfc060301 // Pin=-104dBm -0x81c 0xfb080301 // Pin=-102dBm -0x81c 0xfa0a0301 // Pin=-100dBm -0x81c 0xf90c0301 // Pin=-98dBm -0x81c 0xf80e0301 // Pin=-96dBm -0x81c 0xf7100301 // Pin=-94dBm -0x81c 0xf6120301 // Pin=-92dBm -0x81c 0xf5140301 // Pin=-90dBm -0x81c 0xf4160301 // Pin=-88dBm -0x81c 0xf3180301 // Pin=-86dBm -0x81c 0xf21a0301 // Pin=-84dBm -0x81c 0xf11c0301 // Pin=-82dBm -0x81c 0xf01e0301 // Pin=-80dBm -0x81c 0xef200301 // Pin=-78dBm -0x81c 0xee220301 // Pin=-76dBm -0x81c 0xed240301 // Pin=-74dBm -0x81c 0xec260301 // Pin=-72dBm -0x81c 0xeb280301 // Pin=-70dBm -0x81c 0xea2a0301 // Pin=-68dBm -0x81c 0xe92c0301 // Pin=-66dBm -0x81c 0xe82e0301 // Pin=-64dBm -0x81c 0xe7300301 // Pin=-62dBm -0x81c 0xe6320301 // Pin=-60dBm -0x81c 0xe5340301 // Pin=-58dBm -0x81c 0xe4360301 // Pin=-56dBm -0x81c 0xe3380301 // Pin=-54dBm -0x81c 0xa63a0301 // Pin=-52dBm -0x81c 0xa53c0301 // Pin=-50dBm -0x81c 0xa43e0301 // Pin=-48dBm -0x81c 0xa3400301 // Pin=-46dBm -0x81c 0x84420301 // Pin=-44dBm -0x81c 0x83440301 // Pin=-42dBm -0x81c 0x82460301 // Pin=-40dBm -0x81c 0x65480301 // Pin=-38dBm -0x81c 0x644a0301 // Pin=-36dBm -0x81c 0x634c0301 // Pin=-34dBm -0x81c 0x624e0301 // Pin=-32dBm -0x81c 0x61500301 // Pin=-30dBm -0x81c 0x27520301 // Pin=-28dBm -0x81c 0x26540301 // Pin=-26dBm -0x81c 0x25560301 // Pin=-24dBm -0x81c 0x24580301 // Pin=-22dBm -0x81c 0x235a0301 // Pin=-20dBm -0x81c 0x225c0301 // Pin=-18dBm -0x81c 0x215e0301 // Pin=-16dBm -0x81c 0x06600301 // Pin=-14dBm -0x81c 0x05620301 // Pin=-12dBm -0x81c 0x04640301 // Pin=-10dBm -0x81c 0x03660301 // Pin=-08dBm -0x81c 0x02680301 // Pin=-06dBm -0x81c 0x016a0301 // Pin=-04dBm -0x81c 0x016c0301 // Pin=-02dBm -0x81c 0x016e0301 // Pin=-00dBm -0x81c 0x01700301 // Pin=+02dBm -0x81c 0x01720301 // Pin=+04dBm -0x81c 0x01740301 // Pin=+06dBm -0x81c 0x01760301 // Pin=+08dBm -0x81c 0x01780301 // Pin=+10dBm -0x81c 0x017a0301 // Pin=+12dBm -0x81c 0x017c0301 // Pin=+14dBm -0x81c 0x017e0301 // Pin=+16dBm -0xc50 0x00000022 -0xc50 0x00000020 +//RL6310_MAC_PHY_RF_Parameter_v015_20130702 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb31c0001 // Pin=-82dBm +0x81c 0xb21e0001 // Pin=-80dBm +0x81c 0xb1200001 // Pin=-78dBm +0x81c 0xb0220001 // Pin=-76dBm +0x81c 0xaf240001 // Pin=-74dBm +0x81c 0xae260001 // Pin=-72dBm +0x81c 0xad280001 // Pin=-70dBm +0x81c 0xac2a0001 // Pin=-68dBm +0x81c 0xab2c0001 // Pin=-66dBm +0x81c 0xaa2e0001 // Pin=-64dBm +0x81c 0xa9300001 // Pin=-62dBm +0x81c 0xa8320001 // Pin=-60dBm +0x81c 0xa7340001 // Pin=-58dBm +0x81c 0xa6360001 // Pin=-56dBm +0x81c 0xa5380001 // Pin=-54dBm +0x81c 0xa43a0001 // Pin=-52dBm +0x81c 0xa33c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G Low Band) +0x81c 0xfe000101 // Pin=-110dBm +0x81c 0xfd020101 // Pin=-108dBm +0x81c 0xfc040101 // Pin=-106dBm +0x81c 0xfb060101 // Pin=-104dBm +0x81c 0xfa080101 // Pin=-102dBm +0x81c 0xf90a0101 // Pin=-100dBm +0x81c 0xf80c0101 // Pin=-98dBm +0x81c 0xf70e0101 // Pin=-96dBm +0x81c 0xf6100101 // Pin=-94dBm +0x81c 0xf5120101 // Pin=-92dBm +0x81c 0xf4140101 // Pin=-90dBm +0x81c 0xf3160101 // Pin=-88dBm +0x81c 0xf2180101 // Pin=-86dBm +0x81c 0xf11a0101 // Pin=-84dBm +0x81c 0xf01c0101 // Pin=-82dBm +0x81c 0xef1e0101 // Pin=-80dBm +0x81c 0xee200101 // Pin=-78dBm +0x81c 0xed220101 // Pin=-76dBm +0x81c 0xec240101 // Pin=-74dBm +0x81c 0xeb260101 // Pin=-72dBm +0x81c 0xea280101 // Pin=-70dBm +0x81c 0xe92a0101 // Pin=-68dBm +0x81c 0xe82c0101 // Pin=-66dBm +0x81c 0xe72e0101 // Pin=-64dBm +0x81c 0xe6300101 // Pin=-62dBm +0x81c 0xe5320101 // Pin=-60dBm +0x81c 0xe4340101 // Pin=-58dBm +0x81c 0xe3360101 // Pin=-56dBm +0x81c 0xa6380101 // Pin=-54dBm +0x81c 0xa53a0101 // Pin=-52dBm +0x81c 0xa43c0101 // Pin=-50dBm +0x81c 0xa33e0101 // Pin=-48dBm +0x81c 0x83400101 // Pin=-46dBm +0x81c 0x82420101 // Pin=-44dBm +0x81c 0x65440101 // Pin=-42dBm +0x81c 0x64460101 // Pin=-40dBm +0x81c 0x63480101 // Pin=-38dBm +0x81c 0x624a0101 // Pin=-36dBm +0x81c 0x614c0101 // Pin=-34dBm +0x81c 0x2a4e0101 // Pin=-32dBm +0x81c 0x29500101 // Pin=-30dBm +0x81c 0x28520101 // Pin=-28dBm +0x81c 0x27540101 // Pin=-26dBm +0x81c 0x26560101 // Pin=-24dBm +0x81c 0x25580101 // Pin=-22dBm +0x81c 0x245a0101 // Pin=-20dBm +0x81c 0x235c0101 // Pin=-18dBm +0x81c 0x225e0101 // Pin=-16dBm +0x81c 0x06600101 // Pin=-14dBm +0x81c 0x05620101 // Pin=-12dBm +0x81c 0x04640101 // Pin=-10dBm +0x81c 0x03660101 // Pin=-08dBm +0x81c 0x02680101 // Pin=-06dBm +0x81c 0x016a0101 // Pin=-04dBm +0x81c 0x016c0101 // Pin=-02dBm +0x81c 0x016e0101 // Pin=-00dBm +0x81c 0x01700101 // Pin=+02dBm +0x81c 0x01720101 // Pin=+04dBm +0x81c 0x01740101 // Pin=+06dBm +0x81c 0x01760101 // Pin=+08dBm +0x81c 0x01780101 // Pin=+10dBm +0x81c 0x017a0101 // Pin=+12dBm +0x81c 0x017c0101 // Pin=+14dBm +0x81c 0x017e0101 // Pin=+16dBm +// AGC_TABLE 2 (5G Mid band) +0x81c 0xff000201 // Pin=-110dBm +0x81c 0xfe020201 // Pin=-108dBm +0x81c 0xfd040201 // Pin=-106dBm +0x81c 0xfc060201 // Pin=-104dBm +0x81c 0xfb080201 // Pin=-102dBm +0x81c 0xfa0a0201 // Pin=-100dBm +0x81c 0xf90c0201 // Pin=-98dBm +0x81c 0xf80e0201 // Pin=-96dBm +0x81c 0xf7100201 // Pin=-94dBm +0x81c 0xf6120201 // Pin=-92dBm +0x81c 0xf5140201 // Pin=-90dBm +0x81c 0xf4160201 // Pin=-88dBm +0x81c 0xf3180201 // Pin=-86dBm +0x81c 0xf21a0201 // Pin=-84dBm +0x81c 0xf11c0201 // Pin=-82dBm +0x81c 0xf01e0201 // Pin=-80dBm +0x81c 0xef200201 // Pin=-78dBm +0x81c 0xee220201 // Pin=-76dBm +0x81c 0xed240201 // Pin=-74dBm +0x81c 0xec260201 // Pin=-72dBm +0x81c 0xeb280201 // Pin=-70dBm +0x81c 0xea2a0201 // Pin=-68dBm +0x81c 0xe92c0201 // Pin=-66dBm +0x81c 0xe82e0201 // Pin=-64dBm +0x81c 0xe7300201 // Pin=-62dBm +0x81c 0xe6320201 // Pin=-60dBm +0x81c 0xe5340201 // Pin=-58dBm +0x81c 0xe4360201 // Pin=-56dBm +0x81c 0xe3380201 // Pin=-54dBm +0x81c 0xe23a0201 // Pin=-52dBm +0x81c 0xa53c0201 // Pin=-50dBm +0x81c 0xa43e0201 // Pin=-48dBm +0x81c 0x85400201 // Pin=-46dBm +0x81c 0x84420201 // Pin=-44dBm +0x81c 0x83440201 // Pin=-42dBm +0x81c 0x82460201 // Pin=-40dBm +0x81c 0x65480201 // Pin=-38dBm +0x81c 0x644a0201 // Pin=-36dBm +0x81c 0x634c0201 // Pin=-34dBm +0x81c 0x624e0201 // Pin=-32dBm +0x81c 0x2a500201 // Pin=-30dBm +0x81c 0x29520201 // Pin=-28dBm +0x81c 0x28540201 // Pin=-26dBm +0x81c 0x27560201 // Pin=-24dBm +0x81c 0x26580201 // Pin=-22dBm +0x81c 0x255a0201 // Pin=-20dBm +0x81c 0x245c0201 // Pin=-18dBm +0x81c 0x235e0201 // Pin=-16dBm +0x81c 0x06600201 // Pin=-14dBm +0x81c 0x05620201 // Pin=-12dBm +0x81c 0x04640201 // Pin=-10dBm +0x81c 0x03660201 // Pin=-08dBm +0x81c 0x02680201 // Pin=-06dBm +0x81c 0x016a0201 // Pin=-04dBm +0x81c 0x016c0201 // Pin=-02dBm +0x81c 0x016e0201 // Pin=-00dBm +0x81c 0x01700201 // Pin=+02dBm +0x81c 0x01720201 // Pin=+04dBm +0x81c 0x01740201 // Pin=+06dBm +0x81c 0x01760201 // Pin=+08dBm +0x81c 0x01780201 // Pin=+10dBm +0x81c 0x017a0201 // Pin=+12dBm +0x81c 0x017c0201 // Pin=+14dBm +0x81c 0x017e0201 // Pin=+16dBm +// AGC_TABLE 3 (5G High band) +0x81c 0xff000301 // Pin=-110dBm +0x81c 0xfe020301 // Pin=-108dBm +0x81c 0xfd040301 // Pin=-106dBm +0x81c 0xfc060301 // Pin=-104dBm +0x81c 0xfb080301 // Pin=-102dBm +0x81c 0xfa0a0301 // Pin=-100dBm +0x81c 0xf90c0301 // Pin=-98dBm +0x81c 0xf80e0301 // Pin=-96dBm +0x81c 0xf7100301 // Pin=-94dBm +0x81c 0xf6120301 // Pin=-92dBm +0x81c 0xf5140301 // Pin=-90dBm +0x81c 0xf4160301 // Pin=-88dBm +0x81c 0xf3180301 // Pin=-86dBm +0x81c 0xf21a0301 // Pin=-84dBm +0x81c 0xf11c0301 // Pin=-82dBm +0x81c 0xf01e0301 // Pin=-80dBm +0x81c 0xef200301 // Pin=-78dBm +0x81c 0xee220301 // Pin=-76dBm +0x81c 0xed240301 // Pin=-74dBm +0x81c 0xec260301 // Pin=-72dBm +0x81c 0xeb280301 // Pin=-70dBm +0x81c 0xea2a0301 // Pin=-68dBm +0x81c 0xe92c0301 // Pin=-66dBm +0x81c 0xe82e0301 // Pin=-64dBm +0x81c 0xe7300301 // Pin=-62dBm +0x81c 0xe6320301 // Pin=-60dBm +0x81c 0xe5340301 // Pin=-58dBm +0x81c 0xe4360301 // Pin=-56dBm +0x81c 0xe3380301 // Pin=-54dBm +0x81c 0xa63a0301 // Pin=-52dBm +0x81c 0xa53c0301 // Pin=-50dBm +0x81c 0xa43e0301 // Pin=-48dBm +0x81c 0xa3400301 // Pin=-46dBm +0x81c 0x84420301 // Pin=-44dBm +0x81c 0x83440301 // Pin=-42dBm +0x81c 0x82460301 // Pin=-40dBm +0x81c 0x65480301 // Pin=-38dBm +0x81c 0x644a0301 // Pin=-36dBm +0x81c 0x634c0301 // Pin=-34dBm +0x81c 0x624e0301 // Pin=-32dBm +0x81c 0x61500301 // Pin=-30dBm +0x81c 0x27520301 // Pin=-28dBm +0x81c 0x26540301 // Pin=-26dBm +0x81c 0x25560301 // Pin=-24dBm +0x81c 0x24580301 // Pin=-22dBm +0x81c 0x235a0301 // Pin=-20dBm +0x81c 0x225c0301 // Pin=-18dBm +0x81c 0x215e0301 // Pin=-16dBm +0x81c 0x06600301 // Pin=-14dBm +0x81c 0x05620301 // Pin=-12dBm +0x81c 0x04640301 // Pin=-10dBm +0x81c 0x03660301 // Pin=-08dBm +0x81c 0x02680301 // Pin=-06dBm +0x81c 0x016a0301 // Pin=-04dBm +0x81c 0x016c0301 // Pin=-02dBm +0x81c 0x016e0301 // Pin=-00dBm +0x81c 0x01700301 // Pin=+02dBm +0x81c 0x01720301 // Pin=+04dBm +0x81c 0x01740301 // Pin=+06dBm +0x81c 0x01760301 // Pin=+08dBm +0x81c 0x01780301 // Pin=+10dBm +0x81c 0x017a0301 // Pin=+12dBm +0x81c 0x017c0301 // Pin=+14dBm +0x81c 0x017e0301 // Pin=+16dBm +0xc50 0x00000022 +0xc50 0x00000020 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_high_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_high_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_high_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_high_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_low_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_low_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_low_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_low_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_normal_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_normal_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_normal_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_def_normal_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_high_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_high_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_high_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_high_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_low_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_low_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_low_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_low_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_normal_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_normal_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_normal_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_gen_normal_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_state_criteria_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_state_criteria_8881A.txt index e79b27a31e5..4e01fc766eb 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_state_criteria_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_state_criteria_8881A.txt @@ -1,15 +1,15 @@ -////Release version: 8881A.0820.2013 -// State: -// 1.) MACDM_TP_STATE_DEFAULT -// 2.) MACDM_TP_STATE_GENERAL -// 3.) MACDM_TP_STATE_TXOP -// So, we need four criteria -// 1.) MACDM_TP_THRS_DEF_TO_GEN -// 2.) MACDM_TP_THRS_GEN_TO_DEF -// 3.) MACDM_TP_THRS_GEN_TO_TXOP -// 4.) MACDM_TP_THRS_TXOP_TO_GEN -0x1 -0x2 -0x3 -0x4 +////Release version: 8881A.0820.2013 +// State: +// 1.) MACDM_TP_STATE_DEFAULT +// 2.) MACDM_TP_STATE_GENERAL +// 3.) MACDM_TP_STATE_TXOP +// So, we need four criteria +// 1.) MACDM_TP_THRS_DEF_TO_GEN +// 2.) MACDM_TP_THRS_GEN_TO_DEF +// 3.) MACDM_TP_THRS_GEN_TO_TXOP +// 4.) MACDM_TP_THRS_TXOP_TO_GEN +0x1 +0x2 +0x3 +0x4 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_high_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_high_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_high_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_high_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_low_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_low_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_low_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_low_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_normal_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_normal_8881A.txt index 98ef59d3828..07110197947 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_normal_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MACDM_txop_normal_8881A.txt @@ -1,4 +1,4 @@ -////Release version: 8881A.0820.2013 -// Max line number: 30 -0x460 0x03086666 +////Release version: 8881A.0820.2013 +// Max line number: 30 +0x460 0x03086666 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MAC_REG_8881Am.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MAC_REG_8881Am.txt old mode 100755 new mode 100644 index 69520dc5f3e..d42e2cad836 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MAC_REG_8881Am.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/MAC_REG_8881Am.txt @@ -1,102 +1,102 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V004_20140708_Beta -//0x010 0x0c // AFE power cut -//0x072 0x00 // AFE iso -//0x067 0x20 -//0x04F 0x01 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x607 0x07 //for formal chip -0x608 0x0e -0x609 0x2a -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x08 -0x63d 0x08 -0x63e 0x0c -0x63f 0x0c -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //for formal chip +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V004_20140708_Beta +//0x010 0x0c // AFE power cut +//0x072 0x00 // AFE iso +//0x067 0x20 +//0x04F 0x01 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x607 0x07 //for formal chip +0x608 0x0e +0x609 0x2a +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x08 +0x63d 0x08 +0x63e 0x0c +0x63f 0x0c +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //for formal chip 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881AMP.txt old mode 100755 new mode 100644 index 68879e57149..0b68a4b9221 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881AMP.txt @@ -1,197 +1,197 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V004_20140708_Beta -//======================= -// PAGE_8 -//======================= -0x800 0x0020d090 -0x804 0x080112e0 -0x808 0x0e028211 // cck_en=0 ofdm_en=0 -0x80c 0x92131111 -0x810 0x20101261 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002081dd -0x830 0x2aaaeec8 -0x834 0x0437a706 -0x838 0x06489b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x62103f8b -0x84c 0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x888c2878 -0x870 0x08888888 -0x874 0x31612c2e -0x878 0x00000152 -0x87c 0x000fd000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa2000338 -0x8ac 0x0ff0fa0a -0x8b4 0x000fc080 -0x8b8 0x7c0057ff -0x8bc 0x0CA52090 -0x8c0 0x1bf00020 -0x8c4 0x00000000 -0x8c8 0x00013169 -0x8cc 0x08248492 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x974 0x000003ff // RFE Output Pin -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x9a4 0x00400080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x01081008 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e0 0x00005d00 -0x9e4 0x00000002 -0x9e8 0x00000000 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c8a8300 -0xa0c 0x2e68000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -//0xa80 0x218075b2 -0xa80 0x21805490 -0xa84 0x001f0000 -//======================= -// PAGE_b -//======================= -//0xb00 0xc3100100 // PMC mode -0xb00 0xc3100040 // TMAC mode -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x24000003 -0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x001c1208 -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x19791979 -0xc6c 0x19791979 -0xc70 0x19791979 -0xc74 0x19791979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77771755 // Ctrl 0-7 Selection -0xcb4 0x10000077 // Ctrl 8-9 Selection -0xcb8 0x00508240 - -//0x66 0xC8043007 -//0x4c 0x01628202 -//0x7c 0x000000c3 - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V004_20140708_Beta +//======================= +// PAGE_8 +//======================= +0x800 0x0020d090 +0x804 0x080112e0 +0x808 0x0e028211 // cck_en=0 ofdm_en=0 +0x80c 0x92131111 +0x810 0x20101261 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002081dd +0x830 0x2aaaeec8 +0x834 0x0437a706 +0x838 0x06489b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x62103f8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x888c2878 +0x870 0x08888888 +0x874 0x31612c2e +0x878 0x00000152 +0x87c 0x000fd000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa2000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c0057ff +0x8bc 0x0CA52090 +0x8c0 0x1bf00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x974 0x000003ff // RFE Output Pin +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00400080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e0 0x00005d00 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +//0xa80 0x218075b2 +0xa80 0x21805490 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0xc3100100 // PMC mode +0xb00 0xc3100040 // TMAC mode +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x24000003 +0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x001c1208 +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x19791979 +0xc6c 0x19791979 +0xc70 0x19791979 +0xc74 0x19791979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77771755 // Ctrl 0-7 Selection +0xcb4 0x10000077 // Ctrl 8-9 Selection +0xcb8 0x00508240 + +//0x66 0xC8043007 +//0x4c 0x01628202 +//0x7c 0x000000c3 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881Am.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881Am.txt old mode 100755 new mode 100644 index 87222f98990..b9d0691c69a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881Am.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_8881Am.txt @@ -1,197 +1,197 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//======================= -// PAGE_8 -//======================= -0x800 0x0020d090 -0x804 0x080112e0 -0x808 0x0e028211 // cck_en=0 ofdm_en=0 -0x80c 0x92131111 -0x810 0x20101261 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002081dd -0x830 0x2aaaeec8 -0x834 0x0437a706 -0x838 0x06489b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x62103f8b -0x84c 0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x888c2878 -0x870 0x08888888 -0x874 0x31612c2e -0x878 0x00000152 -0x87c 0x000fd000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa2000338 -0x8ac 0x0ff0fa0a -0x8b4 0x000fc080 -0x8b8 0x7c0057ff -0x8bc 0x0CA52090 -0x8c0 0x1bf00020 -0x8c4 0x00000000 -0x8c8 0x00013169 -0x8cc 0x08248492 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x974 0x000003ff // RFE Output Pin -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x9a4 0x00400080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x01081008 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e0 0x00005d00 -0x9e4 0x00000002 -0x9e8 0x00000000 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c8a8300 -0xa0c 0x2e68000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -//0xa80 0x218075b2 -0xa80 0x21805490 -0xa84 0x001f0000 -//======================= -// PAGE_b -//======================= -//0xb00 0xc3100100 // PMC mode -0xb00 0xc3100040 // TMAC mode -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x24000003 -0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x001c1208 -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x19791979 -0xc6c 0x19791979 -0xc70 0x19791979 -0xc74 0x19791979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77771755 // Ctrl 0-7 Selection -0xcb4 0x10000077 // Ctrl 8-9 Selection -0xcb8 0x00508240 - -//0x66 0xC8043007 -//0x4c 0x01628202 -//0x7c 0x000000c3 - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//======================= +// PAGE_8 +//======================= +0x800 0x0020d090 +0x804 0x080112e0 +0x808 0x0e028211 // cck_en=0 ofdm_en=0 +0x80c 0x92131111 +0x810 0x20101261 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002081dd +0x830 0x2aaaeec8 +0x834 0x0437a706 +0x838 0x06489b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x62103f8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x888c2878 +0x870 0x08888888 +0x874 0x31612c2e +0x878 0x00000152 +0x87c 0x000fd000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa2000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c0057ff +0x8bc 0x0CA52090 +0x8c0 0x1bf00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x974 0x000003ff // RFE Output Pin +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00400080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e0 0x00005d00 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +//0xa80 0x218075b2 +0xa80 0x21805490 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0xc3100100 // PMC mode +0xb00 0xc3100040 // TMAC mode +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x24000003 +0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x001c1208 +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x19791979 +0xc6c 0x19791979 +0xc70 0x19791979 +0xc74 0x19791979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77771755 // Ctrl 0-7 Selection +0xcb4 0x10000077 // Ctrl 8-9 Selection +0xcb8 0x00508240 + +//0x66 0xC8043007 +//0x4c 0x01628202 +//0x7c 0x000000c3 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_MP_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_MP_8881A.txt old mode 100755 new mode 100644 index 2a7c856b21e..0e380ded09c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_MP_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_MP_8881A.txt @@ -1,3 +1,3 @@ -//20100311 - +//20100311 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP.txt old mode 100755 new mode 100644 index 2377f842c2d..d86cb127748 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP.txt @@ -1,52 +1,52 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP_intpa.txt old mode 100755 new mode 100644 index 6255818b527..54280032c72 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881ABP_intpa.txt @@ -1,53 +1,53 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP.txt old mode 100755 new mode 100644 index 2377f842c2d..d86cb127748 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP.txt @@ -1,52 +1,52 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP_intpa.txt old mode 100755 new mode 100644 index 6255818b527..54280032c72 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AMP_intpa.txt @@ -1,53 +1,53 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN.txt old mode 100755 new mode 100644 index 6255818b527..54280032c72 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN.txt @@ -1,53 +1,53 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 -//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v006_20140115 +//RL6310_MAC_PHY_RF_Parameter_8881AN_v01_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 17 17 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 17 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 17 17 17 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 16 16 17 17 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 14 15 16 16 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 16 16 16 16 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 13 14 14 15 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 16 16 11 12 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 14 15 16 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN_extpa.txt index 2377f842c2d..d86cb127748 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881AN_extpa.txt @@ -1,52 +1,52 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 -//RTK Version -#[v1][Exact]# -#[2.4G][A]# -0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//RL6310_MAC_PHY_RF_Parameter_8881AB_v003_20130904 +//RTK Version +#[v1][Exact]# +#[2.4G][A]# +0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 18 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 16 17 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 18 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 14 15 16 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881A_new.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881A_new.txt old mode 100755 new mode 100644 index e09192e303f..4cab70a578d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881A_new.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881A_new.txt @@ -1,50 +1,50 @@ -//RTL8881_MAC_PHY_Parameter_8881AQ_v017_20130904 -#[v1][Exact]# -#[2.4G][A]# -0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RTL8881_MAC_PHY_Parameter_8881AQ_v017_20130904 +#[v1][Exact]# +#[2.4G][A]# +0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881Am.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881Am.txt old mode 100755 new mode 100644 index e09192e303f..4cab70a578d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881Am.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/PHY_REG_PG_8881Am.txt @@ -1,50 +1,50 @@ -//RTL8881_MAC_PHY_Parameter_8881AQ_v017_20130904 -#[v1][Exact]# -#[2.4G][A]# -0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[2.4G][B]# -0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -#[END]# - -#[5G][A]# -0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# - -#[5G][B]# -0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -#[END]# -0xffff 0xffff +//RTL8881_MAC_PHY_Parameter_8881AQ_v017_20130904 +#[v1][Exact]# +#[2.4G][A]# +0xc20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[2.4G][B]# +0xe20 16 17 18 19 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +#[END]# + +#[5G][A]# +0xc24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# + +#[5G][B]# +0xe24 19 19 19 19 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 16 17 17 18 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 19 19 19 19 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 15 16 17 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 19 19 13 14 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 17 18 19 19 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 13 14 15 16 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RTL8881FW_A_CUT_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RTL8881FW_A_CUT_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RTL8881TXBUF_A_CUT_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RTL8881TXBUF_A_CUT_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP.txt index 0d1824f5aa5..363db875c7f 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP.txt @@ -1,398 +1,398 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x00244 //111 7-1 -0x3B 0x38027 -0x3C 0x82000 -0x3A 0x00244 //110 6-1 -0x3B 0x30113 -0x3C 0x82000 -0x3A 0x0014c //101 5-1 -0x3B 0x28027 -0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x00244 //111 7-1 -0x3B 0x78027 -0x3C 0x82000 -0x3A 0x00244 //110 6-1 -0x3B 0x70113 -0x3C 0x82000 -0x3A 0x0014c //101 5-1 -0x3B 0x68027 -0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x00244 //111 7-1 -0x3B 0xb8027 -0x3C 0x82000 -0x3A 0x00244 //110 6-1 -0x3B 0xb0113 -0x3C 0x82000 -0x3A 0x0014c //101 5-1 -0x3B 0xa8027 -0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACE7 -0x34 0x49CE5 -0x34 0x48CE3 -0x34 0x478C7 -0x34 0x464A7 -0x34 0x45487 -0x34 0x44484 -0x34 0x43067 -0x34 0x42047 -0x34 0x41044 -0x34 0x40041 -//TX AGC 5GM -0x34 0x2ACE8 -0x34 0x298E8 -0x34 0x288C9 -0x34 0x274A9 -0x34 0x26489 -0x34 0x25486 -0x34 0x24069 -0x34 0x23066 -0x34 0x22046 -0x34 0x21043 -0x34 0x20040 -//TX AGC 5GL -0x34 0x0ACED -0x34 0x098ED -0x34 0x088CD -0x34 0x074AD -0x34 0x0648D -0x34 0x0548A -0x34 0x0406D -0x34 0x0306A -0x34 0x0204A -0x34 0x01047 -0x34 0x00044 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x201F6 //MB 80M -0x35 0x281F6 //MB 40M -0x35 0x301F6 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x114E7 -0x64 0x1A88C -0x65 0x93014 -0x55 0x38031 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF3 -0x34 0x09DF0 -0x34 0x08DED -0x34 0x07DEA -0x34 0x06CED -0x34 0x05CEA -0x34 0x044EB -0x34 0x034E8 -0x34 0x0246B -0x34 0x01468 -0x34 0x0006B -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x00244 //111 7-1 +0x3B 0x38027 +0x3C 0x82000 +0x3A 0x00244 //110 6-1 +0x3B 0x30113 +0x3C 0x82000 +0x3A 0x0014c //101 5-1 +0x3B 0x28027 +0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x00244 //111 7-1 +0x3B 0x78027 +0x3C 0x82000 +0x3A 0x00244 //110 6-1 +0x3B 0x70113 +0x3C 0x82000 +0x3A 0x0014c //101 5-1 +0x3B 0x68027 +0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x00244 //111 7-1 +0x3B 0xb8027 +0x3C 0x82000 +0x3A 0x00244 //110 6-1 +0x3B 0xb0113 +0x3C 0x82000 +0x3A 0x0014c //101 5-1 +0x3B 0xa8027 +0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACE7 +0x34 0x49CE5 +0x34 0x48CE3 +0x34 0x478C7 +0x34 0x464A7 +0x34 0x45487 +0x34 0x44484 +0x34 0x43067 +0x34 0x42047 +0x34 0x41044 +0x34 0x40041 +//TX AGC 5GM +0x34 0x2ACE8 +0x34 0x298E8 +0x34 0x288C9 +0x34 0x274A9 +0x34 0x26489 +0x34 0x25486 +0x34 0x24069 +0x34 0x23066 +0x34 0x22046 +0x34 0x21043 +0x34 0x20040 +//TX AGC 5GL +0x34 0x0ACED +0x34 0x098ED +0x34 0x088CD +0x34 0x074AD +0x34 0x0648D +0x34 0x0548A +0x34 0x0406D +0x34 0x0306A +0x34 0x0204A +0x34 0x01047 +0x34 0x00044 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x201F6 //MB 80M +0x35 0x281F6 //MB 40M +0x35 0x301F6 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x114E7 +0x64 0x1A88C +0x65 0x93014 +0x55 0x38031 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF3 +0x34 0x09DF0 +0x34 0x08DED +0x34 0x07DEA +0x34 0x06CED +0x34 0x05CEA +0x34 0x044EB +0x34 0x034E8 +0x34 0x0246B +0x34 0x01468 +0x34 0x0006B +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP_intpa.txt old mode 100755 new mode 100644 index c50714c3cb7..f5febc01e9e --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881ABP_intpa.txt @@ -1,370 +1,370 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 //21 -0x34 0x49DF2 //18.5 -0x34 0x48DEF //15.5 -0x34 0x47DEC //12.5 -0x34 0x46CED //9.2 -0x34 0x45CAD //6.4 -0x34 0x4488D //2.9 -0x34 0x4384E //0 -0x34 0x4244F //-2.4 -0x34 0x4144C //-5.4 -0x34 0x40449 //-8 -//TX AGC 5GM -0x34 0x2ADF7 //21.2 -0x34 0x29DF4 //18.2 -0x34 0x28DF1 //15.3 -0x34 0x27DEE //12.2 -0x34 0x26CEF //9.2 -0x34 0x25CAF //6.2 -0x34 0x2488F //3.2 -0x34 0x23850 //0.3 -0x34 0x22450 //-3.3 -0x34 0x2144D //-6.2 -0x34 0x2044A //-8.8 -//TX AGC 5GL -0x34 0x0ADF7 //20.5 -0x34 0x09DF4 //18.7 -0x34 0x08DF1 //15.6 -0x34 0x07DEE //12.3 -0x34 0x06DCC //9.2 -0x34 0x05CEC //6.6 -0x34 0x048CC //3.2 -0x34 0x0388C //0.7 -0x34 0x0284B //-2 -0x34 0x0144B //-5.2 -0x34 0x0044A //-8.2 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C9 //LB 80M -0x35 0x081C9 //LB 40M -0x35 0x10148 //LB 20M -0x35 0x201E9 //MB 80M -0x35 0x281E9 //MB 40M -0x35 0x30188 //MB 20M -0x35 0x401C9 //HB 80M -0x35 0x481C9 //HB 40M -0x35 0x50148 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x86358 //LB 80M -0x36 0x8E358 //LB 40M -0x36 0x964D8 //non -0x36 0x9E358 //LB 20M -0x36 0xA76D9 //MB 80M -0x36 0xAF6D9 //MB 40M -0x36 0xB76D9 //non -0x36 0xBF6D9 //MB 20M -0x36 0xC66D8 //HB 80M -0x36 0xCE6D8 //HB 40M -0x36 0xD6658 //non -0x36 0xDE658 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CA //LB -0x3C 0x00524 //MB -0x3C 0x00A36 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x0887C //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xF6D83 -0x62 0x9374C -0x63 0x118F1 -0x64 0x1C26C -0x65 0x91017 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF7 -0x34 0x09DF4 -0x34 0x08DF1 -0x34 0x07DEE -0x34 0x06CF1 -0x34 0x05CEE -0x34 0x044EE -0x34 0x034EC -0x34 0x0246F -0x34 0x0146C -0x34 0x0006D -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 //21 +0x34 0x49DF2 //18.5 +0x34 0x48DEF //15.5 +0x34 0x47DEC //12.5 +0x34 0x46CED //9.2 +0x34 0x45CAD //6.4 +0x34 0x4488D //2.9 +0x34 0x4384E //0 +0x34 0x4244F //-2.4 +0x34 0x4144C //-5.4 +0x34 0x40449 //-8 +//TX AGC 5GM +0x34 0x2ADF7 //21.2 +0x34 0x29DF4 //18.2 +0x34 0x28DF1 //15.3 +0x34 0x27DEE //12.2 +0x34 0x26CEF //9.2 +0x34 0x25CAF //6.2 +0x34 0x2488F //3.2 +0x34 0x23850 //0.3 +0x34 0x22450 //-3.3 +0x34 0x2144D //-6.2 +0x34 0x2044A //-8.8 +//TX AGC 5GL +0x34 0x0ADF7 //20.5 +0x34 0x09DF4 //18.7 +0x34 0x08DF1 //15.6 +0x34 0x07DEE //12.3 +0x34 0x06DCC //9.2 +0x34 0x05CEC //6.6 +0x34 0x048CC //3.2 +0x34 0x0388C //0.7 +0x34 0x0284B //-2 +0x34 0x0144B //-5.2 +0x34 0x0044A //-8.2 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C9 //LB 80M +0x35 0x081C9 //LB 40M +0x35 0x10148 //LB 20M +0x35 0x201E9 //MB 80M +0x35 0x281E9 //MB 40M +0x35 0x30188 //MB 20M +0x35 0x401C9 //HB 80M +0x35 0x481C9 //HB 40M +0x35 0x50148 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x86358 //LB 80M +0x36 0x8E358 //LB 40M +0x36 0x964D8 //non +0x36 0x9E358 //LB 20M +0x36 0xA76D9 //MB 80M +0x36 0xAF6D9 //MB 40M +0x36 0xB76D9 //non +0x36 0xBF6D9 //MB 20M +0x36 0xC66D8 //HB 80M +0x36 0xCE6D8 //HB 40M +0x36 0xD6658 //non +0x36 0xDE658 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CA //LB +0x3C 0x00524 //MB +0x3C 0x00A36 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x0887C //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xF6D83 +0x62 0x9374C +0x63 0x118F1 +0x64 0x1C26C +0x65 0x91017 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF7 +0x34 0x09DF4 +0x34 0x08DF1 +0x34 0x07DEE +0x34 0x06CF1 +0x34 0x05CEE +0x34 0x044EE +0x34 0x034EC +0x34 0x0246F +0x34 0x0146C +0x34 0x0006D +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP.txt index bd37b6229b0..8025380a701 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP.txt @@ -1,371 +1,371 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACE8 -0x34 0x49CE6 -0x34 0x48CE4 -0x34 0x478C7 -0x34 0x464A6 -0x34 0x45486 -0x34 0x44483 -0x34 0x43066 -0x34 0x42046 -0x34 0x41043 -0x34 0x40040 -//TX AGC 5GM -0x34 0x2ACED -0x34 0x298ED -0x34 0x288CE -0x34 0x274AD -0x34 0x2648D -0x34 0x2548A -0x34 0x2406D -0x34 0x2306A -0x34 0x2204A -0x34 0x21047 -0x34 0x20044 -//TX AGC 5GL -0x34 0x0ACE9 -0x34 0x098E9 -0x34 0x088C9 -0x34 0x074A9 -0x34 0x06489 -0x34 0x05486 -0x34 0x04069 -0x34 0x03066 -0x34 0x02046 -0x34 0x01043 -0x34 0x00040 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x201F6 //MB 80M -0x35 0x281F6 //MB 40M -0x35 0x301F6 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x114E7 -0x64 0x1A88C -0x65 0x93014 -0x55 0x38031 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF3 -0x34 0x09DF0 -0x34 0x08DED -0x34 0x07DEA -0x34 0x06CED -0x34 0x05CEA -0x34 0x044EB -0x34 0x034E8 -0x34 0x0246B -0x34 0x01468 -0x34 0x0006B -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACE8 +0x34 0x49CE6 +0x34 0x48CE4 +0x34 0x478C7 +0x34 0x464A6 +0x34 0x45486 +0x34 0x44483 +0x34 0x43066 +0x34 0x42046 +0x34 0x41043 +0x34 0x40040 +//TX AGC 5GM +0x34 0x2ACED +0x34 0x298ED +0x34 0x288CE +0x34 0x274AD +0x34 0x2648D +0x34 0x2548A +0x34 0x2406D +0x34 0x2306A +0x34 0x2204A +0x34 0x21047 +0x34 0x20044 +//TX AGC 5GL +0x34 0x0ACE9 +0x34 0x098E9 +0x34 0x088C9 +0x34 0x074A9 +0x34 0x06489 +0x34 0x05486 +0x34 0x04069 +0x34 0x03066 +0x34 0x02046 +0x34 0x01043 +0x34 0x00040 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x201F6 //MB 80M +0x35 0x281F6 //MB 40M +0x35 0x301F6 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x114E7 +0x64 0x1A88C +0x65 0x93014 +0x55 0x38031 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF3 +0x34 0x09DF0 +0x34 0x08DED +0x34 0x07DEA +0x34 0x06CED +0x34 0x05CEA +0x34 0x044EB +0x34 0x034E8 +0x34 0x0246B +0x34 0x01468 +0x34 0x0006B +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_2layer.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_2layer.txt old mode 100755 new mode 100644 index f320f727d76..18e6197c31d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_2layer.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_2layer.txt @@ -1,371 +1,371 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACED -0x34 0x49CEA -0x34 0x48CE7 -0x34 0x478CC -0x34 0x464A9 -0x34 0x4548C -0x34 0x44489 -0x34 0x4306A -0x34 0x4204D -0x34 0x4104A -0x34 0x40047 -//TX AGC 5GM -0x34 0x2ACF0 -0x34 0x29CED -0x34 0x28CEA -0x34 0x278CE -0x34 0x264AB -0x34 0x2548D -0x34 0x2448A -0x34 0x2306B -0x34 0x2204D -0x34 0x2104A -0x34 0x20047 -//TX AGC 5GL -0x34 0x0ACEF -0x34 0x098ED -0x34 0x088CF -0x34 0x074AC -0x34 0x0648E -0x34 0x0548B -0x34 0x0406C -0x34 0x03069 -0x34 0x0204C -0x34 0x01046 -0x34 0x00046 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x201F6 //MB 80M -0x35 0x281F6 //MB 40M -0x35 0x301F6 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x114E7 -0x64 0x1A88C -0x65 0x93011 -0x55 0x38031 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF3 -0x34 0x09DF0 -0x34 0x08DED -0x34 0x07DEA -0x34 0x06CED -0x34 0x05CEA -0x34 0x044EB -0x34 0x034E8 -0x34 0x0246B -0x34 0x01468 -0x34 0x0006B -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACED +0x34 0x49CEA +0x34 0x48CE7 +0x34 0x478CC +0x34 0x464A9 +0x34 0x4548C +0x34 0x44489 +0x34 0x4306A +0x34 0x4204D +0x34 0x4104A +0x34 0x40047 +//TX AGC 5GM +0x34 0x2ACF0 +0x34 0x29CED +0x34 0x28CEA +0x34 0x278CE +0x34 0x264AB +0x34 0x2548D +0x34 0x2448A +0x34 0x2306B +0x34 0x2204D +0x34 0x2104A +0x34 0x20047 +//TX AGC 5GL +0x34 0x0ACEF +0x34 0x098ED +0x34 0x088CF +0x34 0x074AC +0x34 0x0648E +0x34 0x0548B +0x34 0x0406C +0x34 0x03069 +0x34 0x0204C +0x34 0x01046 +0x34 0x00046 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x201F6 //MB 80M +0x35 0x281F6 //MB 40M +0x35 0x301F6 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x114E7 +0x64 0x1A88C +0x65 0x93011 +0x55 0x38031 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF3 +0x34 0x09DF0 +0x34 0x08DED +0x34 0x07DEA +0x34 0x06CED +0x34 0x05CEA +0x34 0x044EB +0x34 0x034E8 +0x34 0x0246B +0x34 0x01468 +0x34 0x0006B +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_intpa.txt old mode 100755 new mode 100644 index 9d6e2e8fe4a..b51fe421dbd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AMP_intpa.txt @@ -1,370 +1,370 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 //21 -0x34 0x49DF1 //18.5 -0x34 0x48DEE //15.5 -0x34 0x47DEB //12.5 -0x34 0x46CEC //9.2 -0x34 0x45CAC //6.4 -0x34 0x4488C //2.9 -0x34 0x4384D //0 -0x34 0x4244E //-2.4 -0x34 0x4144B //-5.4 -0x34 0x40448 //-8 -//TX AGC 5GM -0x34 0x2ADF7 //21.2 -0x34 0x29DF4 //18.2 -0x34 0x28DF1 //15.3 -0x34 0x27DEE //12.2 -0x34 0x26CEF //9.2 -0x34 0x25CAF //6.2 -0x34 0x2488F //3.2 -0x34 0x23850 //0.3 -0x34 0x22450 //-3.3 -0x34 0x2144D //-6.2 -0x34 0x2044A //-8.8 -//TX AGC 5GL -0x34 0x0ADF7 //20.5 -0x34 0x09DF4 //18.7 -0x34 0x08DF1 //15.6 -0x34 0x07DEE //12.3 -0x34 0x06DCC //9.2 -0x34 0x05CEC //6.6 -0x34 0x048CC //3.2 -0x34 0x0388C //0.7 -0x34 0x0284D //-2 -0x34 0x0144D //-5.2 -0x34 0x0044A //-8.2 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C9 //LB 80M -0x35 0x081C9 //LB 40M -0x35 0x10148 //LB 20M -0x35 0x201C8 //MB 80M -0x35 0x281C8 //MB 40M -0x35 0x30188 //MB 20M -0x35 0x401C8 //HB 80M -0x35 0x481C8 //HB 40M -0x35 0x50148 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x86358 //LB 80M -0x36 0x8E358 //LB 40M -0x36 0x964D8 //non -0x36 0x9E358 //LB 20M -0x36 0xA6458 //MB 80M -0x36 0xAE6D8 //MB 40M -0x36 0xB66D8 //non -0x36 0xBE6D8 //MB 20M -0x36 0xC6658 //HB 80M -0x36 0xCE658 //HB 40M -0x36 0xD6658 //non -0x36 0xDE658 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002B8 //LB -0x3C 0x00400 //MB -0x3C 0x00AB8 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xF6D83 -0x62 0x93BCC -0x63 0x118F1 -0x64 0x1C26C -0x65 0x91017 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF7 -0x34 0x09DF4 -0x34 0x08DF1 -0x34 0x07DEE -0x34 0x06CF1 -0x34 0x05CEE -0x34 0x044EE -0x34 0x034EC -0x34 0x0246F -0x34 0x0146C -0x34 0x0006D -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 //21 +0x34 0x49DF1 //18.5 +0x34 0x48DEE //15.5 +0x34 0x47DEB //12.5 +0x34 0x46CEC //9.2 +0x34 0x45CAC //6.4 +0x34 0x4488C //2.9 +0x34 0x4384D //0 +0x34 0x4244E //-2.4 +0x34 0x4144B //-5.4 +0x34 0x40448 //-8 +//TX AGC 5GM +0x34 0x2ADF7 //21.2 +0x34 0x29DF4 //18.2 +0x34 0x28DF1 //15.3 +0x34 0x27DEE //12.2 +0x34 0x26CEF //9.2 +0x34 0x25CAF //6.2 +0x34 0x2488F //3.2 +0x34 0x23850 //0.3 +0x34 0x22450 //-3.3 +0x34 0x2144D //-6.2 +0x34 0x2044A //-8.8 +//TX AGC 5GL +0x34 0x0ADF7 //20.5 +0x34 0x09DF4 //18.7 +0x34 0x08DF1 //15.6 +0x34 0x07DEE //12.3 +0x34 0x06DCC //9.2 +0x34 0x05CEC //6.6 +0x34 0x048CC //3.2 +0x34 0x0388C //0.7 +0x34 0x0284D //-2 +0x34 0x0144D //-5.2 +0x34 0x0044A //-8.2 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C9 //LB 80M +0x35 0x081C9 //LB 40M +0x35 0x10148 //LB 20M +0x35 0x201C8 //MB 80M +0x35 0x281C8 //MB 40M +0x35 0x30188 //MB 20M +0x35 0x401C8 //HB 80M +0x35 0x481C8 //HB 40M +0x35 0x50148 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x86358 //LB 80M +0x36 0x8E358 //LB 40M +0x36 0x964D8 //non +0x36 0x9E358 //LB 20M +0x36 0xA6458 //MB 80M +0x36 0xAE6D8 //MB 40M +0x36 0xB66D8 //non +0x36 0xBE6D8 //MB 20M +0x36 0xC6658 //HB 80M +0x36 0xCE658 //HB 40M +0x36 0xD6658 //non +0x36 0xDE658 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002B8 //LB +0x3C 0x00400 //MB +0x3C 0x00AB8 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xF6D83 +0x62 0x93BCC +0x63 0x118F1 +0x64 0x1C26C +0x65 0x91017 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF7 +0x34 0x09DF4 +0x34 0x08DF1 +0x34 0x07DEE +0x34 0x06CF1 +0x34 0x05CEE +0x34 0x044EE +0x34 0x034EC +0x34 0x0246F +0x34 0x0146C +0x34 0x0006D +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN.txt old mode 100755 new mode 100644 index 9d6e2e8fe4a..b51fe421dbd --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN.txt @@ -1,370 +1,370 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 //21 -0x34 0x49DF1 //18.5 -0x34 0x48DEE //15.5 -0x34 0x47DEB //12.5 -0x34 0x46CEC //9.2 -0x34 0x45CAC //6.4 -0x34 0x4488C //2.9 -0x34 0x4384D //0 -0x34 0x4244E //-2.4 -0x34 0x4144B //-5.4 -0x34 0x40448 //-8 -//TX AGC 5GM -0x34 0x2ADF7 //21.2 -0x34 0x29DF4 //18.2 -0x34 0x28DF1 //15.3 -0x34 0x27DEE //12.2 -0x34 0x26CEF //9.2 -0x34 0x25CAF //6.2 -0x34 0x2488F //3.2 -0x34 0x23850 //0.3 -0x34 0x22450 //-3.3 -0x34 0x2144D //-6.2 -0x34 0x2044A //-8.8 -//TX AGC 5GL -0x34 0x0ADF7 //20.5 -0x34 0x09DF4 //18.7 -0x34 0x08DF1 //15.6 -0x34 0x07DEE //12.3 -0x34 0x06DCC //9.2 -0x34 0x05CEC //6.6 -0x34 0x048CC //3.2 -0x34 0x0388C //0.7 -0x34 0x0284D //-2 -0x34 0x0144D //-5.2 -0x34 0x0044A //-8.2 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C9 //LB 80M -0x35 0x081C9 //LB 40M -0x35 0x10148 //LB 20M -0x35 0x201C8 //MB 80M -0x35 0x281C8 //MB 40M -0x35 0x30188 //MB 20M -0x35 0x401C8 //HB 80M -0x35 0x481C8 //HB 40M -0x35 0x50148 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x86358 //LB 80M -0x36 0x8E358 //LB 40M -0x36 0x964D8 //non -0x36 0x9E358 //LB 20M -0x36 0xA6458 //MB 80M -0x36 0xAE6D8 //MB 40M -0x36 0xB66D8 //non -0x36 0xBE6D8 //MB 20M -0x36 0xC6658 //HB 80M -0x36 0xCE658 //HB 40M -0x36 0xD6658 //non -0x36 0xDE658 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002B8 //LB -0x3C 0x00400 //MB -0x3C 0x00AB8 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xF6D83 -0x62 0x93BCC -0x63 0x118F1 -0x64 0x1C26C -0x65 0x91017 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF7 -0x34 0x09DF4 -0x34 0x08DF1 -0x34 0x07DEE -0x34 0x06CF1 -0x34 0x05CEE -0x34 0x044EE -0x34 0x034EC -0x34 0x0246F -0x34 0x0146C -0x34 0x0006D -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 //21 +0x34 0x49DF1 //18.5 +0x34 0x48DEE //15.5 +0x34 0x47DEB //12.5 +0x34 0x46CEC //9.2 +0x34 0x45CAC //6.4 +0x34 0x4488C //2.9 +0x34 0x4384D //0 +0x34 0x4244E //-2.4 +0x34 0x4144B //-5.4 +0x34 0x40448 //-8 +//TX AGC 5GM +0x34 0x2ADF7 //21.2 +0x34 0x29DF4 //18.2 +0x34 0x28DF1 //15.3 +0x34 0x27DEE //12.2 +0x34 0x26CEF //9.2 +0x34 0x25CAF //6.2 +0x34 0x2488F //3.2 +0x34 0x23850 //0.3 +0x34 0x22450 //-3.3 +0x34 0x2144D //-6.2 +0x34 0x2044A //-8.8 +//TX AGC 5GL +0x34 0x0ADF7 //20.5 +0x34 0x09DF4 //18.7 +0x34 0x08DF1 //15.6 +0x34 0x07DEE //12.3 +0x34 0x06DCC //9.2 +0x34 0x05CEC //6.6 +0x34 0x048CC //3.2 +0x34 0x0388C //0.7 +0x34 0x0284D //-2 +0x34 0x0144D //-5.2 +0x34 0x0044A //-8.2 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C9 //LB 80M +0x35 0x081C9 //LB 40M +0x35 0x10148 //LB 20M +0x35 0x201C8 //MB 80M +0x35 0x281C8 //MB 40M +0x35 0x30188 //MB 20M +0x35 0x401C8 //HB 80M +0x35 0x481C8 //HB 40M +0x35 0x50148 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x86358 //LB 80M +0x36 0x8E358 //LB 40M +0x36 0x964D8 //non +0x36 0x9E358 //LB 20M +0x36 0xA6458 //MB 80M +0x36 0xAE6D8 //MB 40M +0x36 0xB66D8 //non +0x36 0xBE6D8 //MB 20M +0x36 0xC6658 //HB 80M +0x36 0xCE658 //HB 40M +0x36 0xD6658 //non +0x36 0xDE658 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002B8 //LB +0x3C 0x00400 //MB +0x3C 0x00AB8 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xF6D83 +0x62 0x93BCC +0x63 0x118F1 +0x64 0x1C26C +0x65 0x91017 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF7 +0x34 0x09DF4 +0x34 0x08DF1 +0x34 0x07DEE +0x34 0x06CF1 +0x34 0x05CEE +0x34 0x044EE +0x34 0x034EC +0x34 0x0246F +0x34 0x0146C +0x34 0x0006D +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN_extpa.txt index f320f727d76..18e6197c31d 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881AN_extpa.txt @@ -1,371 +1,371 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACED -0x34 0x49CEA -0x34 0x48CE7 -0x34 0x478CC -0x34 0x464A9 -0x34 0x4548C -0x34 0x44489 -0x34 0x4306A -0x34 0x4204D -0x34 0x4104A -0x34 0x40047 -//TX AGC 5GM -0x34 0x2ACF0 -0x34 0x29CED -0x34 0x28CEA -0x34 0x278CE -0x34 0x264AB -0x34 0x2548D -0x34 0x2448A -0x34 0x2306B -0x34 0x2204D -0x34 0x2104A -0x34 0x20047 -//TX AGC 5GL -0x34 0x0ACEF -0x34 0x098ED -0x34 0x088CF -0x34 0x074AC -0x34 0x0648E -0x34 0x0548B -0x34 0x0406C -0x34 0x03069 -0x34 0x0204C -0x34 0x01046 -0x34 0x00046 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x201F6 //MB 80M -0x35 0x281F6 //MB 40M -0x35 0x301F6 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x114E7 -0x64 0x1A88C -0x65 0x93011 -0x55 0x38031 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF3 -0x34 0x09DF0 -0x34 0x08DED -0x34 0x07DEA -0x34 0x06CED -0x34 0x05CEA -0x34 0x044EB -0x34 0x034E8 -0x34 0x0246B -0x34 0x01468 -0x34 0x0006B -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V006_20140930 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACED +0x34 0x49CEA +0x34 0x48CE7 +0x34 0x478CC +0x34 0x464A9 +0x34 0x4548C +0x34 0x44489 +0x34 0x4306A +0x34 0x4204D +0x34 0x4104A +0x34 0x40047 +//TX AGC 5GM +0x34 0x2ACF0 +0x34 0x29CED +0x34 0x28CEA +0x34 0x278CE +0x34 0x264AB +0x34 0x2548D +0x34 0x2448A +0x34 0x2306B +0x34 0x2204D +0x34 0x2104A +0x34 0x20047 +//TX AGC 5GL +0x34 0x0ACEF +0x34 0x098ED +0x34 0x088CF +0x34 0x074AC +0x34 0x0648E +0x34 0x0548B +0x34 0x0406C +0x34 0x03069 +0x34 0x0204C +0x34 0x01046 +0x34 0x00046 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x201F6 //MB 80M +0x35 0x281F6 //MB 40M +0x35 0x301F6 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x114E7 +0x64 0x1A88C +0x65 0x93011 +0x55 0x38031 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF3 +0x34 0x09DF0 +0x34 0x08DED +0x34 0x07DEA +0x34 0x06CED +0x34 0x05CEA +0x34 0x044EB +0x34 0x034E8 +0x34 0x0246B +0x34 0x01468 +0x34 0x0006B +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881Am.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881Am.txt old mode 100755 new mode 100644 index cc39f74adbb..709026ff505 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881Am.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/RadioA_8881Am.txt @@ -1,409 +1,409 @@ -//RL6310_MAC_PHY_RF_Parameter_v015_20130702 -//A MODE S0:5210 -//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating - -0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 - -//0x1C 0x739D0 //disable RCK -//0x1C 0x539D2 //enable RCK -0x1E 0x80000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -0x89 0x00080 -0x8b 0x80180 - -0xEF 0x01000 -//LB -//0x3A 0x00244 //111 7-1 -//0x3B 0x38027 -//0x3C 0x82000 -//0x3A 0x00244 //110 6-1 -//0x3B 0x30113 -//0x3C 0x82000 -//0x3A 0x0014c //101 5-1 -//0x3B 0x28027 -//0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0x27027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x1f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x17f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -//0x3B 0x048027 -0x3B 0x08027 -0x3C 0xca000 -//MB -//0x3A 0x00244 //111 7-1 -//0x3B 0x78027 -//0x3C 0x82000 -//0x3A 0x00244 //110 6-1 -//0x3B 0x70113 -//0x3C 0x82000 -//0x3A 0x0014c //101 5-1 -//0x3B 0x68027 -//0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0x67027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x5f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x57f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x48027 -0x3C 0xca000 -//HB -//0x3A 0x00244 //111 7-1 -//0x3B 0xb8027 -//0x3C 0x82000 -//0x3A 0x00244 //110 6-1 -//0x3B 0xb0113 -//0x3C 0x82000 -//0x3A 0x0014c //101 5-1 -//0x3B 0xa8027 -//0x3C 0x82000 -0x3A 0x000cc //100 4-1 -0x3B 0xa7027 -0x3C 0x42000 -0x3A 0x0014c //011 3-1 -0x3B 0x9f913 -0x3C 0x42000 -0x3A 0x0010c //010 3new -0x3B 0x97f10 -0x3C 0x12000 -0x3A 0x000d0 //001 2 -0x3B 0x88027 -0x3C 0xca000 -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACEC -0x34 0x49CEA -0x34 0x48CE8 -0x34 0x478CC -0x34 0x464AC -0x34 0x4548C -0x34 0x44489 -0x34 0x4306C -0x34 0x4204C -0x34 0x41049 -0x34 0x40046 -//TX AGC 5GM -0x34 0x2ACEC -0x34 0x298EC -0x34 0x288CD -0x34 0x274AD -0x34 0x2648D -0x34 0x2548A -0x34 0x2406D -0x34 0x2306A -0x34 0x2204A -0x34 0x21047 -0x34 0x20044 -//TX AGC 5GL -0x34 0x0ACED -0x34 0x098ED -0x34 0x088CD -0x34 0x074AD -0x34 0x0648D -0x34 0x0548A -0x34 0x0406D -0x34 0x0306A -0x34 0x0204A -0x34 0x01047 -0x34 0x00044 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x201F6 //MB 80M -0x35 0x281F6 //MB 40M -0x35 0x301F6 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0xF6394 //LO leakage -0x59 0x680DC //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x114E7 -0x64 0x1A88C -0x65 0x93014 -0x55 0x58031 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0xB7 0x30008 -//0x18 0x1F12A //set ch42; do LCK -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xfe //Note: It should be 0xffe in RadioA.csv -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x3824B //Gain 7 -0x3B 0x3024B //Gain 6 -0x3B 0x2824B //Gain 5 -0x3B 0x20F4B //Gain 4 -0x3B 0x18F4B //Gain 3 -0x3B 0x104B2 //Gain 2 -0x3B 0x08049 //Gain 1 -0x3B 0x00148 //Gain 0 -0x3B 0x7824B //CCK Gain 7 -0x3B 0x7024B //CCK Gain 6 -0x3B 0x6824B //CCK Gain 5 -0x3B 0x60F4B //CCK Gain 4 -0x3B 0x58F4B //CCK Gain 3 -0x3B 0x504B2 //CCK Gain 2 -0x3B 0x48049 //CCK Gain 1 -0x3B 0x40148 //CCK Gain 0 -//0x3B 0x39258 //Gain 7 0010 0100 1011 24b -//0x3B 0x31258 //Gain 6 -//0x3B 0x29258 //Gain 5 -//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b -//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b -//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 -//0x3B 0x08248 //Gain 1 0000 0100 1001 049 -//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF7 -0x35 0x04800 -0x34 0x09DF4 -0x35 0x03C00 -0x34 0x08DF1 -0x35 0x03000 -0x34 0x07DEE -0x35 0x02400 -0x34 0x06CF1 -0x35 0x03000 -0x34 0x05CEE -0x35 0x02400 -0x34 0x044EE -0x35 0x03000 -0x34 0x034EC -0x35 0x02400 -0x34 0x0246F -0x35 0x03000 -0x34 0x0146C -0x35 0x02400 -0x34 0x0006D -0x35 0x03000 -0xEF 0x00000 - -0xED 0x00010 -0x44 0x0ADF6 -0x44 0x09DEF -0x44 0x08DF0 -0x44 0x07DED -0x44 0x06CF0 -0x44 0x05CED -0x44 0x044F0 -0x44 0x034ED -0x44 0x02470 -0x44 0x0146D -0x44 0x00070 -0xED 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -//0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00140 -0x45 0x08140 -0x45 0x10140 - -0x46 0x00124 -0x46 0x08124 -0x46 0x10124 -0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - -//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 -0xB4 0x1219C //Ires bias by chris 1128 -//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 -0xB7 0x3000C -0x1C 0x539D2 //enable RCK -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -//0xffe -//0xffe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -//0x18 0x1F12A //set ch42; do LCK -0x18 0x1712A //set ch42 -//0x1C 0x539D2 //enable RCK - +//RL6310_MAC_PHY_RF_Parameter_v015_20130702 +//A MODE S0:5210 +//PAK 20121016+EEMing20121026_0x64+EEMing20121029_AmpmApkTable + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating + +0x00 0x10000 //turn on RF into stand-by mode add @ 20121206 + +//0x1C 0x739D0 //disable RCK +//0x1C 0x539D2 //enable RCK +0x1E 0x80000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +0x89 0x00080 +0x8b 0x80180 + +0xEF 0x01000 +//LB +//0x3A 0x00244 //111 7-1 +//0x3B 0x38027 +//0x3C 0x82000 +//0x3A 0x00244 //110 6-1 +//0x3B 0x30113 +//0x3C 0x82000 +//0x3A 0x0014c //101 5-1 +//0x3B 0x28027 +//0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0x27027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x1f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x17f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +//0x3B 0x048027 +0x3B 0x08027 +0x3C 0xca000 +//MB +//0x3A 0x00244 //111 7-1 +//0x3B 0x78027 +//0x3C 0x82000 +//0x3A 0x00244 //110 6-1 +//0x3B 0x70113 +//0x3C 0x82000 +//0x3A 0x0014c //101 5-1 +//0x3B 0x68027 +//0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0x67027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x5f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x57f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x48027 +0x3C 0xca000 +//HB +//0x3A 0x00244 //111 7-1 +//0x3B 0xb8027 +//0x3C 0x82000 +//0x3A 0x00244 //110 6-1 +//0x3B 0xb0113 +//0x3C 0x82000 +//0x3A 0x0014c //101 5-1 +//0x3B 0xa8027 +//0x3C 0x82000 +0x3A 0x000cc //100 4-1 +0x3B 0xa7027 +0x3C 0x42000 +0x3A 0x0014c //011 3-1 +0x3B 0x9f913 +0x3C 0x42000 +0x3A 0x0010c //010 3new +0x3B 0x97f10 +0x3C 0x12000 +0x3A 0x000d0 //001 2 +0x3B 0x88027 +0x3C 0xca000 +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACEC +0x34 0x49CEA +0x34 0x48CE8 +0x34 0x478CC +0x34 0x464AC +0x34 0x4548C +0x34 0x44489 +0x34 0x4306C +0x34 0x4204C +0x34 0x41049 +0x34 0x40046 +//TX AGC 5GM +0x34 0x2ACEC +0x34 0x298EC +0x34 0x288CD +0x34 0x274AD +0x34 0x2648D +0x34 0x2548A +0x34 0x2406D +0x34 0x2306A +0x34 0x2204A +0x34 0x21047 +0x34 0x20044 +//TX AGC 5GL +0x34 0x0ACED +0x34 0x098ED +0x34 0x088CD +0x34 0x074AD +0x34 0x0648D +0x34 0x0548A +0x34 0x0406D +0x34 0x0306A +0x34 0x0204A +0x34 0x01047 +0x34 0x00044 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x201F6 //MB 80M +0x35 0x281F6 //MB 40M +0x35 0x301F6 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0xF6394 //LO leakage +0x59 0x680DC //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x114E7 +0x64 0x1A88C +0x65 0x93014 +0x55 0x58031 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +//0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0xB7 0x30008 +//0x18 0x1F12A //set ch42; do LCK +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xfe //Note: It should be 0xffe in RadioA.csv +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x3824B //Gain 7 +0x3B 0x3024B //Gain 6 +0x3B 0x2824B //Gain 5 +0x3B 0x20F4B //Gain 4 +0x3B 0x18F4B //Gain 3 +0x3B 0x104B2 //Gain 2 +0x3B 0x08049 //Gain 1 +0x3B 0x00148 //Gain 0 +0x3B 0x7824B //CCK Gain 7 +0x3B 0x7024B //CCK Gain 6 +0x3B 0x6824B //CCK Gain 5 +0x3B 0x60F4B //CCK Gain 4 +0x3B 0x58F4B //CCK Gain 3 +0x3B 0x504B2 //CCK Gain 2 +0x3B 0x48049 //CCK Gain 1 +0x3B 0x40148 //CCK Gain 0 +//0x3B 0x39258 //Gain 7 0010 0100 1011 24b +//0x3B 0x31258 //Gain 6 +//0x3B 0x29258 //Gain 5 +//0x3B 0x27a58 //Gain 4 1111 0100 1011 f4b +//0x3B 0x1fa58 //Gain 3 1111 0100 1011 f4b +//0x3B 0x12590 //Gain 2 0100 1011 0010 4b2 +//0x3B 0x08248 //Gain 1 0000 0100 1001 049 +//0x3B 0x00a40 //Gain 0 0001 0100 1000 148 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF7 +0x35 0x04800 +0x34 0x09DF4 +0x35 0x03C00 +0x34 0x08DF1 +0x35 0x03000 +0x34 0x07DEE +0x35 0x02400 +0x34 0x06CF1 +0x35 0x03000 +0x34 0x05CEE +0x35 0x02400 +0x34 0x044EE +0x35 0x03000 +0x34 0x034EC +0x35 0x02400 +0x34 0x0246F +0x35 0x03000 +0x34 0x0146C +0x35 0x02400 +0x34 0x0006D +0x35 0x03000 +0xEF 0x00000 + +0xED 0x00010 +0x44 0x0ADF6 +0x44 0x09DEF +0x44 0x08DF0 +0x44 0x07DED +0x44 0x06CF0 +0x44 0x05CED +0x44 0x044F0 +0x44 0x034ED +0x44 0x02470 +0x44 0x0146D +0x44 0x00070 +0xED 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +//0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00140 +0x45 0x08140 +0x45 0x10140 + +0x46 0x00124 +0x46 0x08124 +0x46 0x10124 +0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + +//0xB3 0xF0618 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +//0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB3 0xF0E18 //Ires; F0608:Ibg. by chris 1128 +0xB4 0x1219C //Ires bias by chris 1128 +//0xB7 0x00008 //Full scan for G mode LCK by chris 1128 +0xB7 0x3000C +0x1C 0x539D2 //enable RCK +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +//0xffe +//0xffe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +//0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +//0x18 0x1F12A //set ch42; do LCK +0x18 0x1712A //set ch42 +//0x1C 0x539D2 //enable RCK + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP.txt old mode 100755 new mode 100644 index 14046678bd3..2e9a7da839a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 16 17 17 -CH02 22 22 22 -CH03 22 22 22 -CH04 22 22 22 -CH05 22 22 22 -CH06 22 22 22 -CH07 22 22 22 -CH08 22 22 22 -CH09 22 22 22 -CH10 22 22 22 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 13 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 16 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 12 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 12 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 10 16 16 -CH04 15 16 16 -CH05 15 16 16 -CH06 15 16 16 -CH07 15 16 16 -CH08 15 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 11 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 10 16 16 -CH04 15 16 16 -CH05 15 16 16 -CH06 15 16 16 -CH07 15 16 16 -CH08 15 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 11 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 15 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 14 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 14 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 16 16 -CH46 16 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 16 16 -CH46 16 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 16 16 16 -//5G Band 2 -CH58 16 16 16 -//5G Band 3 -CH106 14 14 14 -CH122 19 19 19 -//5G Band 4 -CH155 16 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 16 17 17 +CH02 22 22 22 +CH03 22 22 22 +CH04 22 22 22 +CH05 22 22 22 +CH06 22 22 22 +CH07 22 22 22 +CH08 22 22 22 +CH09 22 22 22 +CH10 22 22 22 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 13 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 16 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 12 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 12 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 10 16 16 +CH04 15 16 16 +CH05 15 16 16 +CH06 15 16 16 +CH07 15 16 16 +CH08 15 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 11 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 10 16 16 +CH04 15 16 16 +CH05 15 16 16 +CH06 15 16 16 +CH07 15 16 16 +CH08 15 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 11 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 15 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 14 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 14 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 16 16 +CH46 16 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 16 16 +CH46 16 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 16 16 16 +//5G Band 2 +CH58 16 16 16 +//5G Band 3 +CH106 14 14 14 +CH122 19 19 19 +//5G Band 4 +CH155 16 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP_intpa.txt old mode 100755 new mode 100644 index 5a73d0a0ff5..46702854961 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881ABP_intpa.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 16 17 17 -CH12 NA 17 17 -CH13 NA 16 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 16 17 17 +CH12 NA 17 17 +CH13 NA 16 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP.txt old mode 100755 new mode 100644 index f101cfad7dc..8e2b77e62e6 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 17 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 16 16 -CH02 16 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 16 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 16 15 15 -CH06 16 15 15 -CH07 16 15 15 -CH08 16 15 15 -CH09 16 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 17 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 17 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 17 16 NA -CH153 17 16 NA -CH157 17 16 NA -CH161 17 16 NA -CH165 17 16 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 17 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 17 16 NA -CH159 17 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 17 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 17 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 16 16 +CH02 16 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 16 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 16 15 15 +CH06 16 15 15 +CH07 16 15 15 +CH08 16 15 15 +CH09 16 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 17 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 17 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 17 16 NA +CH153 17 16 NA +CH157 17 16 NA +CH161 17 16 NA +CH165 17 16 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 17 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 17 16 NA +CH159 17 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 17 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP_intpa.txt old mode 100755 new mode 100644 index 5a73d0a0ff5..46702854961 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AMP_intpa.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 16 17 17 -CH12 NA 17 17 -CH13 NA 16 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 16 17 17 +CH12 NA 17 17 +CH13 NA 16 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN.txt old mode 100755 new mode 100644 index 5a73d0a0ff5..46702854961 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 16 17 17 -CH12 NA 17 17 -CH13 NA 16 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 17 17 17 -CH56 17 17 17 -CH60 17 17 17 -CH64 17 17 17 -//5G Band 3 -CH100 17 17 17 -CH114 17 17 17 -CH108 17 17 17 -CH112 17 17 17 -CH116 17 17 17 -CH120 17 17 17 -CH124 17 17 17 -CH128 17 17 17 -CH132 17 17 17 -CH136 17 17 17 -CH140 17 17 17 -//5G Band 4 -CH149 17 17 NA -CH153 17 17 NA -CH157 17 17 NA -CH161 17 17 NA -CH165 17 17 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 15 16 16 -CH62 15 16 16 -//5G Band 3 -CH102 16 16 16 -CH110 16 16 16 -CH118 16 16 16 -CH126 16 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 16 16 NA -CH159 16 16 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 16 16 -//5G Band 2 -CH58 13 16 16 -//5G Band 3 -CH106 13 16 16 -CH122 16 16 16 -//5G Band 4 -CH155 16 16 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 16 17 17 +CH12 NA 17 17 +CH13 NA 16 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 17 17 17 +CH56 17 17 17 +CH60 17 17 17 +CH64 17 17 17 +//5G Band 3 +CH100 17 17 17 +CH114 17 17 17 +CH108 17 17 17 +CH112 17 17 17 +CH116 17 17 17 +CH120 17 17 17 +CH124 17 17 17 +CH128 17 17 17 +CH132 17 17 17 +CH136 17 17 17 +CH140 17 17 17 +//5G Band 4 +CH149 17 17 NA +CH153 17 17 NA +CH157 17 17 NA +CH161 17 17 NA +CH165 17 17 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 15 16 16 +CH62 15 16 16 +//5G Band 3 +CH102 16 16 16 +CH110 16 16 16 +CH118 16 16 16 +CH126 16 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 16 16 NA +CH159 16 16 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 16 16 +//5G Band 2 +CH58 13 16 16 +//5G Band 3 +CH106 13 16 16 +CH122 16 16 16 +//5G Band 4 +CH155 16 16 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN_extpa.txt index 14046678bd3..2e9a7da839a 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881AN_extpa.txt @@ -1,326 +1,326 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 16 17 17 -CH02 22 22 22 -CH03 22 22 22 -CH04 22 22 22 -CH05 22 22 22 -CH06 22 22 22 -CH07 22 22 22 -CH08 22 22 22 -CH09 22 22 22 -CH10 22 22 22 -CH11 17 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA 17 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 13 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 16 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 12 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 12 17 17 -CH02 17 17 17 -CH03 17 17 17 -CH04 17 17 17 -CH05 17 17 17 -CH06 17 17 17 -CH07 17 17 17 -CH08 17 17 17 -CH09 17 17 17 -CH10 17 17 17 -CH11 15 17 17 -CH12 NA 17 17 -CH13 NA 17 17 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 10 16 16 -CH04 15 16 16 -CH05 15 16 16 -CH06 15 16 16 -CH07 15 16 16 -CH08 15 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 11 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 10 16 16 -CH04 15 16 16 -CH05 15 16 16 -CH06 15 16 16 -CH07 15 16 16 -CH08 15 16 16 -CH09 15 16 16 -CH10 15 16 16 -CH11 11 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 17 17 -CH40 17 17 17 -CH44 17 17 17 -CH48 17 17 17 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 15 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 14 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 18 18 18 -CH40 18 18 18 -CH44 18 18 18 -CH48 18 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 14 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 16 16 -CH46 16 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 11: =========================================== -// -## 5G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 16 16 16 -CH46 16 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 16 16 16 -//5G Band 2 -CH58 16 16 16 -//5G Band 3 -CH106 14 14 14 -CH122 19 19 19 -//5G Band 4 -CH155 16 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 16 17 17 +CH02 22 22 22 +CH03 22 22 22 +CH04 22 22 22 +CH05 22 22 22 +CH06 22 22 22 +CH07 22 22 22 +CH08 22 22 22 +CH09 22 22 22 +CH10 22 22 22 +CH11 17 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA 17 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 13 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 16 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 12 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 12 17 17 +CH02 17 17 17 +CH03 17 17 17 +CH04 17 17 17 +CH05 17 17 17 +CH06 17 17 17 +CH07 17 17 17 +CH08 17 17 17 +CH09 17 17 17 +CH10 17 17 17 +CH11 15 17 17 +CH12 NA 17 17 +CH13 NA 17 17 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 10 16 16 +CH04 15 16 16 +CH05 15 16 16 +CH06 15 16 16 +CH07 15 16 16 +CH08 15 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 11 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 10 16 16 +CH04 15 16 16 +CH05 15 16 16 +CH06 15 16 16 +CH07 15 16 16 +CH08 15 16 16 +CH09 15 16 16 +CH10 15 16 16 +CH11 11 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 17 17 +CH40 17 17 17 +CH44 17 17 17 +CH48 17 17 17 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 15 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 14 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 18 18 18 +CH40 18 18 18 +CH44 18 18 18 +CH48 18 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 14 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 16 16 +CH46 16 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 11: =========================================== +// +## 5G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 16 16 16 +CH46 16 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 16 16 16 +//5G Band 2 +CH58 16 16 16 +//5G Band 3 +CH106 14 14 14 +CH122 19 19 19 +//5G Band 4 +CH155 16 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881A_new.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881A_new.txt old mode 100755 new mode 100644 index 10306679a2c..5d6b6b49fa2 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881A_new.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TXPWR_LMT_8881A_new.txt @@ -1,351 +1,351 @@ -//RL6310_MAC_PHY_RF_Parameter_8881AQ_v017_20130904 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// - - -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 18 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA 18 -## END - -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 15 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END - -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 15 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END - -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 18 18 -CH02 18 18 18 -CH03 18 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END - -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END - -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 18 18 -CH04 18 18 18 -CH05 18 18 18 -CH06 18 18 18 -CH07 18 18 18 -CH08 18 18 18 -CH09 18 18 18 -CH10 18 18 18 -CH11 15 18 18 -CH12 NA 18 18 -CH13 NA 18 18 -CH14 NA NA NA -## END - -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 18 18 -CH40 17 18 18 -CH44 17 18 18 -CH48 17 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 17 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END - -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 18 18 -CH40 17 18 18 -CH44 17 18 18 -CH48 17 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 17 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END - -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 17 18 18 -CH40 17 18 18 -CH44 17 18 18 -CH48 17 18 18 -//5G Band 2 -CH52 18 18 18 -CH56 18 18 18 -CH60 18 18 18 -CH64 18 18 18 -//5G Band 3 -CH100 18 18 18 -CH114 18 18 18 -CH108 18 18 18 -CH112 18 18 18 -CH116 18 18 18 -CH120 18 18 18 -CH124 18 18 18 -CH128 18 18 18 -CH132 18 18 18 -CH136 18 18 18 -CH140 17 18 18 -//5G Band 4 -CH149 18 18 NA -CH153 18 18 NA -CH157 18 18 NA -CH161 18 18 NA -CH165 18 18 NA -## END - -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 18 18 -CH46 17 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 17 18 18 -//5G Band 3 -CH102 16 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END - -// -//Table 11: =========================================== -// -## 5G;, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 17 18 18 -CH46 17 18 18 -//5G Band 2 -CH54 18 18 18 -CH62 17 18 18 -//5G Band 3 -CH102 16 18 18 -CH110 18 18 18 -CH118 18 18 18 -CH126 18 18 18 -CH134 18 18 18 -//5G Band 4 -CH151 18 18 NA -CH159 18 18 NA -## END - -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 18 18 -//5G Band 2 -CH58 15 18 18 -//5G Band 3 -CH106 15 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END - -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 18 18 -//5G Band 2 -CH58 15 18 18 -//5G Band 3 -CH106 15 18 18 -CH122 18 18 18 -//5G Band 4 -CH155 18 18 NA -## END - - - - - - - - - - - +//RL6310_MAC_PHY_RF_Parameter_8881AQ_v017_20130904 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// + + +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 18 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA 18 +## END + +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 15 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END + +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 15 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END + +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 18 18 +CH02 18 18 18 +CH03 18 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END + +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END + +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 18 18 +CH04 18 18 18 +CH05 18 18 18 +CH06 18 18 18 +CH07 18 18 18 +CH08 18 18 18 +CH09 18 18 18 +CH10 18 18 18 +CH11 15 18 18 +CH12 NA 18 18 +CH13 NA 18 18 +CH14 NA NA NA +## END + +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 18 18 +CH40 17 18 18 +CH44 17 18 18 +CH48 17 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 17 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END + +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 18 18 +CH40 17 18 18 +CH44 17 18 18 +CH48 17 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 17 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END + +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 17 18 18 +CH40 17 18 18 +CH44 17 18 18 +CH48 17 18 18 +//5G Band 2 +CH52 18 18 18 +CH56 18 18 18 +CH60 18 18 18 +CH64 18 18 18 +//5G Band 3 +CH100 18 18 18 +CH114 18 18 18 +CH108 18 18 18 +CH112 18 18 18 +CH116 18 18 18 +CH120 18 18 18 +CH124 18 18 18 +CH128 18 18 18 +CH132 18 18 18 +CH136 18 18 18 +CH140 17 18 18 +//5G Band 4 +CH149 18 18 NA +CH153 18 18 NA +CH157 18 18 NA +CH161 18 18 NA +CH165 18 18 NA +## END + +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 18 18 +CH46 17 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 17 18 18 +//5G Band 3 +CH102 16 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END + +// +//Table 11: =========================================== +// +## 5G;, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 17 18 18 +CH46 17 18 18 +//5G Band 2 +CH54 18 18 18 +CH62 17 18 18 +//5G Band 3 +CH102 16 18 18 +CH110 18 18 18 +CH118 18 18 18 +CH126 18 18 18 +CH134 18 18 18 +//5G Band 4 +CH151 18 18 NA +CH159 18 18 NA +## END + +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 18 18 +//5G Band 2 +CH58 15 18 18 +//5G Band 3 +CH106 15 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END + +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 18 18 +//5G Band 2 +CH58 15 18 18 +//5G Band 3 +CH106 15 18 18 +CH122 18 18 18 +//5G Band 4 +CH155 18 18 NA +## END + + + + + + + + + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881A.txt old mode 100755 new mode 100644 index 6832b6a29c6..39f30707e12 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881A.txt @@ -1,24 +1,24 @@ -//RL6310_MAC_PHY_RF_Parameter_v012_20130323 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P -[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P -[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P -[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P -[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_v012_20130323 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P +[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P +[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P +[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P +[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP.txt old mode 100755 new mode 100644 index c67653642a3..bd4e24ffd3d --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP.txt @@ -1,24 +1,24 @@ -//RL6299_MAC_PHY_RF_Parameter_v012_20130508 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P -[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P -[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P -[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P -[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 17, 17, 17, 17, 17} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 17, 17, 17, 17, 17} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 11, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 11, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 10, 12, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 10, 12, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GHB_N +//RL6299_MAC_PHY_RF_Parameter_v012_20130508 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P +[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P +[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P +[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P +[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 17, 17, 17, 17, 17} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 17, 17, 17, 17, 17} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 11, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 11, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 10, 12, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 10, 12, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP_intpa.txt old mode 100755 new mode 100644 index 61bd3f76b32..146357d1be1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881ABP_intpa.txt @@ -1,24 +1,24 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P -[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P -[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P -[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P -[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P +[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P +[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P +[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P +[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP.txt old mode 100755 new mode 100644 index 1d2ce30995c..92d1de76953 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP.txt @@ -1,25 +1,25 @@ -//RL6310_MAC_PHY_RF_Parameter_v014_20130603 -//RL6310_MAC_PHY_RF_Parameter_v012_20130323 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GCCKA_P -[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GCCKB_P -[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GA_P -[2G][A][-][ALL] = {0, 1, 1, 1, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GB_P -[2G][B][-][ALL] = {0, 1, 1, 1, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_v014_20130603 +//RL6310_MAC_PHY_RF_Parameter_v012_20130323 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GCCKA_P +[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GCCKB_P +[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GA_P +[2G][A][-][ALL] = {0, 1, 1, 1, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7} //2GB_P +[2G][B][-][ALL] = {0, 1, 1, 1, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP_intpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP_intpa.txt old mode 100755 new mode 100644 index 61bd3f76b32..146357d1be1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP_intpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AMP_intpa.txt @@ -1,24 +1,24 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P -[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P -[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P -[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P -[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P +[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P +[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P +[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P +[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN.txt old mode 100755 new mode 100644 index 61bd3f76b32..146357d1be1 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN.txt @@ -1,24 +1,24 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P -[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P -[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P -[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P -[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKA_P +[2G][A][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GCCKB_P +[2G][B][-][CCK] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GA_P +[2G][A][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8} //2GB_P +[2G][B][-][ALL] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN_extpa.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN_extpa.txt index fae67b40c9e..ce8f5d60708 100644 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN_extpa.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_MP/TxPowerTrack_AP_8881AN_extpa.txt @@ -1,24 +1,24 @@ -//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P -[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P -[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P -[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P -[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N -[5G][A][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHB_N +//RL6310_MAC_PHY_RF_Parameter_8881A_Merge_V005_20140717 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKA_P +[2G][A][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GCCKB_P +[2G][B][-][CCK] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GA_P +[2G][A][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9} //2GB_P +[2G][B][-][ALL] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11} //2GB_N +[5G][A][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18} //5GHB_N diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/AGC_TAB_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/AGC_TAB_8881A.txt old mode 100755 new mode 100644 index c9706cf01ec..6624e282503 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/AGC_TAB_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/AGC_TAB_8881A.txt @@ -1,131 +1,131 @@ -////Release version: RLE0547.0907.2012 -0x81c 0xbf000001 -0x81c 0xbf020001 -0x81c 0xbf040001 -0x81c 0xbf060001 -0x81c 0xbe080001 -0x81c 0xbd0a0001 -0x81c 0xbc0c0001 -0x81c 0xba0e0001 -0x81c 0xb9100001 // Pin=-94dBm -0x81c 0xb8120001 // Pin=-92dBm -0x81c 0xb7140001 // Pin=-90dBm -0x81c 0xb6160001 // Pin=-88dBm -0x81c 0xb5180001 // Pin=-86dBm -0x81c 0xb41a0001 // Pin=-84dBm -0x81c 0xb41c0001 // Pin=-82dBm -0x81c 0xb31e0001 // Pin=-80dBm -0x81c 0xb2200001 // Pin=-78dBm -0x81c 0xb1220001 // Pin=-76dBm -0x81c 0xb0240001 // Pin=-74dBm -0x81c 0xaf260001 // Pin=-72dBm -0x81c 0xae280001 // Pin=-70dBm -0x81c 0xad2a0001 // Pin=-68dBm -0x81c 0xac2c0001 // Pin=-66dBm -0x81c 0xab2e0001 // Pin=-64dBm -0x81c 0xaa300001 // Pin=-62dBm -0x81c 0xa9320001 // Pin=-60dBm -0x81c 0xa8340001 // Pin=-58dBm -0x81c 0xa7360001 // Pin=-56dBm -0x81c 0xa6380001 // Pin=-54dBm -0x81c 0xa53a0001 // Pin=-52dBm -0x81c 0xa43c0001 // Pin=-50dBm //7-->5 -0x81c 0x673e0001 // Pin=-48dBm -0x81c 0x66400001 // Pin=-46dBm -0x81c 0x65420001 // Pin=-44dBm -0x81c 0x64440001 // Pin=-42dBm -0x81c 0x63460001 // Pin=-40dBm -0x81c 0x62480001 // Pin=-38dBm -0x81c 0x614a0001 // Pin=-36dBm //6-->3 -0x81c 0x474c0001 // Pin=-34dBm -0x81c 0x464e0001 // Pin=-32dBm -0x81c 0x45500001 // Pin=-30dBm -0x81c 0x44520001 // Pin=-28dBm -0x81c 0x43540001 // Pin=-26dBm -0x81c 0x42560001 // Pin=-24dBm -0x81c 0x41580001 // Pin=-22dBm //5-->2 -0x81c 0x285a0001 // Pin=-20dBm -0x81c 0x275c0001 // Pin=-18dBm -0x81c 0x265e0001 // Pin=-16dBm -0x81c 0x25600001 // Pin=-14dBm -0x81c 0x24620001 // Pin=-12dBm //3-->1 -0x81c 0x0a640001 // Pin=-10dBm -0x81c 0x09660001 // Pin=-08dBm -0x81c 0x08680001 // Pin=-06dBm -0x81c 0x076a0001 // Pin=-04dBm -0x81c 0x066c0001 // Pin=-02dBm -0x81c 0x056e0001 // Pin=-00dBm -0x81c 0x04700001 // Pin=+02dBm -0x81c 0x03720001 // Pin=+04dBm -0x81c 0x02740001 // Pin=+06dBm -0x81c 0x01760001 // Pin=+08dBm -0x81c 0x01780001 // Pin=+10dBm -0x81c 0x017a0001 // Pin=+12dBm -0x81c 0x017c0001 // Pin=+14dBm -0x81c 0x017e0001 // Pin=+16dBm //2-->0 -// AGC_TABLE 1 (5G) -0x81c 0xfd800001 -0x81c 0xfc820001 -0x81c 0xfb840001 -0x81c 0xfa860001 -0x81c 0xf9880001 -0x81c 0xf88a0001 -0x81c 0xf78c0001 -0x81c 0xf68e0001 -0x81c 0xf5900001 // Pin=-94dBm -0x81c 0xf4920001 // Pin=-92dBm -0x81c 0xf3940001 // Pin=-90dBm -0x81c 0xf2960001 // Pin=-88dBm -0x81c 0xf1980001 // Pin=-86dBm -0x81c 0xf09a0001 // Pin=-84dBm -0x81c 0xef9c0001 // Pin=-82dBm -0x81c 0xee9e0001 // Pin=-80dBm -0x81c 0xeda00001 // Pin=-78dBm -0x81c 0xeca20001 // Pin=-76dBm -0x81c 0xeba40001 // Pin=-74dBm -0x81c 0xeaa60001 // Pin=-72dBm -0x81c 0xe9a80001 // Pin=-70dBm -0x81c 0xe8aa0001 // Pin=-68dBm -0x81c 0xe7ac0001 // Pin=-66dBm -0x81c 0xe6ae0001 // Pin=-64dBm -0x81c 0xc6b00001 // Pin=-62dBm -0x81c 0xc5b20001 // Pin=-60dBm -0x81c 0xa5b40001 // Pin=-58dBm -0x81c 0xa4b60001 // Pin=-56dBm -0x81c 0xa3b80001 // Pin=-54dBm -0x81c 0xa2ba0001 // Pin=-52dBm -0x81c 0xa1bc0001 // Pin=-50dBm -0x81c 0x65be0001 // Pin=-48dBm -0x81c 0x64c00001 // Pin=-46dBm -0x81c 0x63c20001 // Pin=-44dBm -0x81c 0x62c40001 // Pin=-42dBm -0x81c 0x61c60001 // Pin=-40dBm -0x81c 0x60c80001 // Pin=-38dBm -0x81c 0x60ca0001 // Pin=-36dBm -0x81c 0x60cc0001 // Pin=-34dBm -0x81c 0x60ce0001 // Pin=-32dBm -0x81c 0x60d00001 // Pin=-30dBm -0x81c 0x60d20001 // Pin=-28dBm -0x81c 0x60d40001 // Pin=-26dBm -0x81c 0x60d60001 // Pin=-24dBm -0x81c 0x60d80001 // Pin=-22dBm -0x81c 0x60da0001 // Pin=-20dBm -0x81c 0x60dc0001 // Pin=-18dBm -0x81c 0x60de0001 // Pin=-16dBm -0x81c 0x60e00001 // Pin=-14dBm -0x81c 0x60e20001 // Pin=-12dBm -0x81c 0x60e40001 // Pin=-10dBm -0x81c 0x60e60001 // Pin=-08dBm -0x81c 0x60e80001 // Pin=-06dBm -0x81c 0x60ea0001 // Pin=-04dBm -0x81c 0x60ec0001 // Pin=-02dBm -0x81c 0x60ee0001 // Pin=-00dBm -0x81c 0x60f00001 // Pin=+02dBm -0x81c 0x60f20001 // Pin=+04dBm -0x81c 0x60f40001 // Pin=+06dBm -0x81c 0x60f60001 // Pin=+08dBm -0x81c 0x60f80001 // Pin=+10dBm -0x81c 0x60fa0001 // Pin=+12dBm -0x81c 0x60fc0001 // Pin=+14dBm -0x81c 0x60fe0001 // Pin=+16dBm +////Release version: RLE0547.0907.2012 +0x81c 0xbf000001 +0x81c 0xbf020001 +0x81c 0xbf040001 +0x81c 0xbf060001 +0x81c 0xbe080001 +0x81c 0xbd0a0001 +0x81c 0xbc0c0001 +0x81c 0xba0e0001 +0x81c 0xb9100001 // Pin=-94dBm +0x81c 0xb8120001 // Pin=-92dBm +0x81c 0xb7140001 // Pin=-90dBm +0x81c 0xb6160001 // Pin=-88dBm +0x81c 0xb5180001 // Pin=-86dBm +0x81c 0xb41a0001 // Pin=-84dBm +0x81c 0xb41c0001 // Pin=-82dBm +0x81c 0xb31e0001 // Pin=-80dBm +0x81c 0xb2200001 // Pin=-78dBm +0x81c 0xb1220001 // Pin=-76dBm +0x81c 0xb0240001 // Pin=-74dBm +0x81c 0xaf260001 // Pin=-72dBm +0x81c 0xae280001 // Pin=-70dBm +0x81c 0xad2a0001 // Pin=-68dBm +0x81c 0xac2c0001 // Pin=-66dBm +0x81c 0xab2e0001 // Pin=-64dBm +0x81c 0xaa300001 // Pin=-62dBm +0x81c 0xa9320001 // Pin=-60dBm +0x81c 0xa8340001 // Pin=-58dBm +0x81c 0xa7360001 // Pin=-56dBm +0x81c 0xa6380001 // Pin=-54dBm +0x81c 0xa53a0001 // Pin=-52dBm +0x81c 0xa43c0001 // Pin=-50dBm //7-->5 +0x81c 0x673e0001 // Pin=-48dBm +0x81c 0x66400001 // Pin=-46dBm +0x81c 0x65420001 // Pin=-44dBm +0x81c 0x64440001 // Pin=-42dBm +0x81c 0x63460001 // Pin=-40dBm +0x81c 0x62480001 // Pin=-38dBm +0x81c 0x614a0001 // Pin=-36dBm //6-->3 +0x81c 0x474c0001 // Pin=-34dBm +0x81c 0x464e0001 // Pin=-32dBm +0x81c 0x45500001 // Pin=-30dBm +0x81c 0x44520001 // Pin=-28dBm +0x81c 0x43540001 // Pin=-26dBm +0x81c 0x42560001 // Pin=-24dBm +0x81c 0x41580001 // Pin=-22dBm //5-->2 +0x81c 0x285a0001 // Pin=-20dBm +0x81c 0x275c0001 // Pin=-18dBm +0x81c 0x265e0001 // Pin=-16dBm +0x81c 0x25600001 // Pin=-14dBm +0x81c 0x24620001 // Pin=-12dBm //3-->1 +0x81c 0x0a640001 // Pin=-10dBm +0x81c 0x09660001 // Pin=-08dBm +0x81c 0x08680001 // Pin=-06dBm +0x81c 0x076a0001 // Pin=-04dBm +0x81c 0x066c0001 // Pin=-02dBm +0x81c 0x056e0001 // Pin=-00dBm +0x81c 0x04700001 // Pin=+02dBm +0x81c 0x03720001 // Pin=+04dBm +0x81c 0x02740001 // Pin=+06dBm +0x81c 0x01760001 // Pin=+08dBm +0x81c 0x01780001 // Pin=+10dBm +0x81c 0x017a0001 // Pin=+12dBm +0x81c 0x017c0001 // Pin=+14dBm +0x81c 0x017e0001 // Pin=+16dBm //2-->0 +// AGC_TABLE 1 (5G) +0x81c 0xfd800001 +0x81c 0xfc820001 +0x81c 0xfb840001 +0x81c 0xfa860001 +0x81c 0xf9880001 +0x81c 0xf88a0001 +0x81c 0xf78c0001 +0x81c 0xf68e0001 +0x81c 0xf5900001 // Pin=-94dBm +0x81c 0xf4920001 // Pin=-92dBm +0x81c 0xf3940001 // Pin=-90dBm +0x81c 0xf2960001 // Pin=-88dBm +0x81c 0xf1980001 // Pin=-86dBm +0x81c 0xf09a0001 // Pin=-84dBm +0x81c 0xef9c0001 // Pin=-82dBm +0x81c 0xee9e0001 // Pin=-80dBm +0x81c 0xeda00001 // Pin=-78dBm +0x81c 0xeca20001 // Pin=-76dBm +0x81c 0xeba40001 // Pin=-74dBm +0x81c 0xeaa60001 // Pin=-72dBm +0x81c 0xe9a80001 // Pin=-70dBm +0x81c 0xe8aa0001 // Pin=-68dBm +0x81c 0xe7ac0001 // Pin=-66dBm +0x81c 0xe6ae0001 // Pin=-64dBm +0x81c 0xc6b00001 // Pin=-62dBm +0x81c 0xc5b20001 // Pin=-60dBm +0x81c 0xa5b40001 // Pin=-58dBm +0x81c 0xa4b60001 // Pin=-56dBm +0x81c 0xa3b80001 // Pin=-54dBm +0x81c 0xa2ba0001 // Pin=-52dBm +0x81c 0xa1bc0001 // Pin=-50dBm +0x81c 0x65be0001 // Pin=-48dBm +0x81c 0x64c00001 // Pin=-46dBm +0x81c 0x63c20001 // Pin=-44dBm +0x81c 0x62c40001 // Pin=-42dBm +0x81c 0x61c60001 // Pin=-40dBm +0x81c 0x60c80001 // Pin=-38dBm +0x81c 0x60ca0001 // Pin=-36dBm +0x81c 0x60cc0001 // Pin=-34dBm +0x81c 0x60ce0001 // Pin=-32dBm +0x81c 0x60d00001 // Pin=-30dBm +0x81c 0x60d20001 // Pin=-28dBm +0x81c 0x60d40001 // Pin=-26dBm +0x81c 0x60d60001 // Pin=-24dBm +0x81c 0x60d80001 // Pin=-22dBm +0x81c 0x60da0001 // Pin=-20dBm +0x81c 0x60dc0001 // Pin=-18dBm +0x81c 0x60de0001 // Pin=-16dBm +0x81c 0x60e00001 // Pin=-14dBm +0x81c 0x60e20001 // Pin=-12dBm +0x81c 0x60e40001 // Pin=-10dBm +0x81c 0x60e60001 // Pin=-08dBm +0x81c 0x60e80001 // Pin=-06dBm +0x81c 0x60ea0001 // Pin=-04dBm +0x81c 0x60ec0001 // Pin=-02dBm +0x81c 0x60ee0001 // Pin=-00dBm +0x81c 0x60f00001 // Pin=+02dBm +0x81c 0x60f20001 // Pin=+04dBm +0x81c 0x60f40001 // Pin=+06dBm +0x81c 0x60f60001 // Pin=+08dBm +0x81c 0x60f80001 // Pin=+10dBm +0x81c 0x60fa0001 // Pin=+12dBm +0x81c 0x60fc0001 // Pin=+14dBm +0x81c 0x60fe0001 // Pin=+16dBm 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/MAC_REG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/MAC_REG_8881A.txt old mode 100755 new mode 100644 index 6ab9f9ab987..dbe089204fa --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/MAC_REG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/MAC_REG_8881A.txt @@ -1,99 +1,99 @@ -////Release version: RTLE0538.0806.2012 -//0x010 0x0c // AFE power cut -//0x072 0x00 // AFE iso -//0x067 0x20 -//0x04F 0x01 -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x0a -0x63d 0x0a -0x63e 0x0e -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 +////Release version: RTLE0538.0806.2012 +//0x010 0x0c // AFE power cut +//0x072 0x00 // AFE iso +//0x067 0x20 +//0x04F 0x01 +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x0a +0x63d 0x0a +0x63e 0x0e +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_1T_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_1T_8881A.txt old mode 100755 new mode 100644 index 310bf04fceb..8ea9696824f --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_1T_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_1T_8881A.txt @@ -1,230 +1,230 @@ -//Release version: RTL8188E.009.0105.2012 -//20111125 -0x24 0x37410421 //0x24[27]=1'b0 -//20111004 Alex -//0x24 038180f1 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x28 0xf2ffff82 //reducing 80M spur -//0x28 0xf2ffff83 //reducing 80M spur -//0x40 0x00000004 //BT LO Leakage -//0x66 0x00040000 //110315 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x0220038e // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 //88E: 0x824[9]=1'b0 -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a11a9 //88E:R130 0x858[15:0]=16h11a9 //0x569a569a -0x85c 0x01000014 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66f60110 //88E:R133 0x860[14:12]=3'd0 //8723E default WiFi for 1 anatenna solution -0x864 0x061f0641 //88E:R130 0x864[15:0]=16'h0641 //0x061f0130 -0x868 0x00000000 -0x86c 0x27272700 //0x32323200 //Path-A 11M/5.5M/2M TX AGC codeword -0x870 0x07000760 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x25004000 // 0x874[27:24]=4'b0101 ADC Gain x 1 //0x22004000 -0x878 0x00000808 //88E:R130+R132 0x878[15:0]=16'h0808,0x878[31:16]=16'h0000 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xb0000c1c // AFE ctrl reg (ASIC), 0x880[17]=1'b0 -0x884 0x00000001 // AFE ctrl reg (ASIC), 0x884[2:1]=0 -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -0x910 0x00000002 // 88E:RX_Status, Reg910[15:0]=16'd2 -0x914 0x00000100 // 88E:Antenna Diversity, 0x914[7:0]=0, 0x914[15:8]=1 -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e7f120f -0xa10 0x9500bb78 -0xa14 0x1114D028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 //88E:R124+R127 RegA76=0x00,RegA77=0x00 -0xa78 0x00000900 //88E:R124+R127 RegA78=0x00,RegA79=0x09 -0xa7c 0x22c00606 //88E:R134 RegA7C=0x06,RegA7D=0x06,RegA7E=0xc0,RegA7F=0x22 -0xa80 0x21807531 //88E: CCK LNA 2 to 3 bit mapping, 0xa80[23]=1'b1. 0xa80[7]=1'b0, CCK agc_rpt as old format -//0xa80 0x21003210 //88E:R134 RegA80=0x10,RegA81=0x32,RegA82=0x00,RegA83=0x21 -// -//======================= -// PAGE_B -//======================= -0xb2c 0x80000000 //default LNA -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652af -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f //88E:R122 //0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69553420 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc0094 -0xc58 0x00003169 // simple agc settling time //0x00000967 //88E:R122 //0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x00250492 // switch RXHP corner //0x00681492 //88E:R122+mantis2467 0xc5c[20:18]=3'd1, 0xc5c[23:21]=3'd1, 0xc5c[26:24]=3'd0 //0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b //by Gary -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //88E:R129 0xc6c[8:7]=0 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x020610db // 1st and 2nd BB PW time = 400ns //0x038610db -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 //0x1b00006c //BB Swing reduce to -7.5dB -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0x20200000 -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x000300A0 //88E: 0xca4[10:0]=0xa0, 0xca4[22:12]=0x30 //0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00000740 //88E: supportL-byte)={11M 5.5M 2M 1M} -0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x001c1208 -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59799979? // for ADC/DAC clk gating -0xc6c 0x59795979 -0xc70 0x99795979 -0xc74 0x99795979 -0xc78 0x99799979 -0xc7c 0x19799979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x00000000 -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77775754 // Ctrl 0-7 Selection -0xcb4 0x10000077 // Ctrl 8-9 Selection -0xcb8 0x00508240 - -//0x66 0xC8043007 -//0x4c 0x01628202 -//0x7c 0x000000c3 - +////Release version: RLE0547.1031.2012 +//======================= +// PAGE_8 +//======================= +0x800 0x0020d410 +0x804 0x080112e0 +0x808 0x0e028211 // cck_en=0 ofdm_en=0 +0x80c 0x12131111 +0x810 0x20101261 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa8e26 +0x834 0x0437a705 +0x838 0x06389b45 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x62103f8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31612c2e +0x878 0x00000152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa0000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c005fff +0x8bc 0x8ca520a0 +0x8c0 0x01f00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x974 0x000003ff // RFE Output Pin +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x01081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00910000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +//0xa80 0x218075b2 +0xa80 0x21805490 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode +0xb00 0x03100000 // TMAC mode +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x24000003 +0xc20 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x30303030 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x30303030 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x2c2c2c2c // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x2a2a2a2a // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x001c1208 +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59799979? // for ADC/DAC clk gating +0xc6c 0x59795979 +0xc70 0x99795979 +0xc74 0x99795979 +0xc78 0x99799979 +0xc7c 0x19799979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x00000000 +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77775754 // Ctrl 0-7 Selection +0xcb4 0x10000077 // Ctrl 8-9 Selection +0xcb8 0x00508240 + +//0x66 0xC8043007 +//0x4c 0x01628202 +//0x7c 0x000000c3 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_MP_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_MP_8881A.txt old mode 100755 new mode 100644 index 2a7c856b21e..0e380ded09c --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_MP_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_MP_8881A.txt @@ -1,3 +1,3 @@ -//20100311 - +//20100311 + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_PG_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_PG_8881A.txt old mode 100755 new mode 100644 index 45d3c4093f9..cdbef2a7b37 --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_PG_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/PHY_REG_PG_8881A.txt @@ -1,144 +1,144 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= -//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 -//========================= -// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -0xff //end of file +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= +//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x0a0c0c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x02040608 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x02040608 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0a0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x02040608 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 +//========================= +// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +0xff //end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RTL8881FW_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RTL8881FW_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RTL8881TXBUF_Test_T.BIN b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RTL8881TXBUF_Test_T.BIN old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RadioA_8881A.txt b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RadioA_8881A.txt old mode 100755 new mode 100644 index 96df1689713..7d4a87ea50a --- a/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RadioA_8881A.txt +++ b/package/kernel/rtl8192cd/WlanHAL/Data/8881A/V702B_Skyworth/RadioA_8881A.txt @@ -1,307 +1,307 @@ -////Release version: RLE0547.0907.2012 -//A MODE S0:5210 -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0xf8000 // RX 80M RCK offset - -0x82 0x00830 -0x83 0x21800 -0x84 0x28000 -0x85 0x48000 -0x86 0x94838 -0x87 0x44980 -0x88 0x48000 -0x89 0x0d480 -0x8A 0x42240 -0x8B 0xf0380 -0x8C 0x90000 -0x8D 0x22852 -0x8E 0x65540 -0x8F 0x88001 - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting - -//Ioffset setting - -// A mode TRx Setting should start before SYN setting 0725 Yn -0x18 0x1712a -//RX Gain Table // Should set 0x3A then 0x3B -0xEF 0x01000 -//LB -0x3A 0x000c4 //HG1 -0x3B 0x3a000 -0x3A 0x001fc //HG2 -0x3B 0x32000 -0x3A 0x001b4 //MG1 -0x3B 0x2a000 -0x3A 0x001c4 //MG2 -0x3B 0x221c8 -0x3A 0x00188 //LG0 -0x3B 0x1a001 -//MB -0x3A 0x000c4 //HG1 -0x3B 0x7a000 -0x3A 0x001fc //HG2 -0x3B 0x72000 -0x3A 0x001b4 //MG1 -0x3B 0x6a000 -0x3A 0x001c4 //MG2 -0x3B 0x621c8 -0x3A 0x00188 //LG0 -0x3B 0x5a001 -//HB -0x3A 0x000c4 //HG1 -0x3B 0xba000 -0x3A 0x001fc //HG2 -0x3B 0xb2000 -0x3A 0x001b4 //MG1 -0x3B 0xaa000 -0x3A 0x001c4 //MG2 -0x3B 0xa21c8 -0x3A 0x00188 //LG0 -0x3B 0x9a001 - -0xEF 0x00000 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ACEE -0x34 0x49CEC -0x34 0x48CEA -0x34 0x478CD -0x34 0x464AC -0x34 0x4548C -0x34 0x44489 -0x34 0x4306C -0x34 0x4204C -0x34 0x41049 -0x34 0x40046 -//TX AGC 5GM -0x34 0x2ACED -0x34 0x298ED -0x34 0x288CE -0x34 0x274AD -0x34 0x2648D -0x34 0x2548A -0x34 0x2406D -0x34 0x2306A -0x34 0x2204A -0x34 0x21047 -0x34 0x20044 -//TX AGC 5GL -0x34 0x0ACED -0x34 0x098ED -0x34 0x088CD -0x34 0x074AD -0x34 0x0648D -0x34 0x0548A -0x34 0x0406D -0x34 0x0306A -0x34 0x0204A -0x34 0x01047 -0x34 0x00044 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00145 //LB 80M -0x35 0x08145 //LB 40M -0x35 0x10145 //LB 20M -0x35 0x20196 //MB 80M -0x35 0x28196 //MB 40M -0x35 0x30196 //MB 20M -0x35 0x401C7 //HB 80M -0x35 0x481C7 //HB 40M -0x35 0x501C7 //HB 20M -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x85633 //LB 80M -0x36 0x8D633 //LB 40M -0x36 0x95633 //non -0x36 0x9D633 //LB 20M -0x36 0xA6634 //MB 80M -0x36 0xAE634 //MB 40M -0x36 0xB6634 //non -0x36 0xBE634 //MB 20M -0x36 0xC67B4 //HB 80M -0x36 0xCE7B4 //HB 40M -0x36 0xD67B4 //non -0x36 0xDE7B4 //HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x0022A //LB -0x3C 0x00594 //MB -0x3C 0x00822 //HB -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0x02000 -0xEF 0x00000 - -0xDF 0x000C0 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -0x58 0x01184 //LO leakage -0x59 0x6006C //IQGEN - -0x61 0xEAD53 -0x62 0x93BC4 -0x63 0x714E7 -0x64 0x1A88C -0x65 0x91014 - -//APK -//0x63 0x70EE9 //LB -//0x63 0x70EE9 //MB -//0x63 0x71267 //HB - -//SYN setting -0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy -0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0xB7 0x30008 -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -//0xB3 0xF0E18 //sel_ioffset UP *by Andy -0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy -0x18 0x1712A //set ch42 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x39258 //Gain 7 -0x3B 0x31258 //Gain 6 -0x3B 0x29258 //Gain 5 -0x3B 0x27a58 //Gain 4 xx have problem -0x3B 0x1fa58 //Gain 3 -0x3B 0x12590 //Gain 2 -0x3B 0x08248 //Gain 1 -0x3B 0x00a40 //Gain 0 -0xEF 0x00000 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF0 -0x34 0x09DED -0x34 0x08DEA -0x34 0x07DE7 -0x34 0x06CEA -0x34 0x05CE7 -0x34 0x044EA -0x34 0x034E7 -0x34 0x0246A -0x34 0x01467 -0x34 0x0006A -0xEF 0x00000 - -//RX_BTG GainTable -0xED 0x00001 -0x40 0x38da7 //Gain 7 -0x40 0x300c2 //Gain 6 -//0x40 0x28ce6 //Gain 5 -0x40 0x288e2 //Gain 5 cck -0x40 0x200b8 //Gain 4 cck -0x40 0x188a5 //Gain 3 -0x40 0x10fbc //Gain 2 -0x40 0x08f71 //Gain 1 -0x40 0x00240 //Gain 0 -0xED 0x00000 - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//by PAK -//0xDF 0x00880 // APK setting and Gain table in debug mode -0x56 0x51DF3 -0x51 0x00C01 -0x52 0x006D6 -0x53 0xFC649 -0xDD 0x00040 -0x70 0x49661 -0x71 0x7843E -0x72 0x00382 -0x74 0x51400 - -0x35 0x00160 -0x35 0x08160 -0x35 0x10160 - -0x36 0x00124 -0x36 0x08124 -0x36 0x10124 -0x36 0x18124 - -0xED 0x0000c -0x45 0x00160 -//0x45 0x08160 -//0x45 0x10160 - -//0x46 0x00124 -//0x46 0x08124 -//0x46 0x10124 -//0x46 0x18124 - -0xDF 0x00088 // Enable RXBB=0 - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F - - -//by PAK -//0xDF 0x20F88 -//0x56 0x51DEE -//0x58 0x01198 -//0x61 0xFCD63 -//0x62 0x93FC2 -//0x63 0x114E9 -//0x64 0x19DEC -//0x65 0x911D5 -//0xB2 0x8583F +////Release version: RLE0547.0907.2012 +//A MODE S0:5210 +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0xf8000 // RX 80M RCK offset + +0x82 0x00830 +0x83 0x21800 +0x84 0x28000 +0x85 0x48000 +0x86 0x94838 +0x87 0x44980 +0x88 0x48000 +0x89 0x0d480 +0x8A 0x42240 +0x8B 0xf0380 +0x8C 0x90000 +0x8D 0x22852 +0x8E 0x65540 +0x8F 0x88001 + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting + +//Ioffset setting + +// A mode TRx Setting should start before SYN setting 0725 Yn +0x18 0x1712a +//RX Gain Table // Should set 0x3A then 0x3B +0xEF 0x01000 +//LB +0x3A 0x000c4 //HG1 +0x3B 0x3a000 +0x3A 0x001fc //HG2 +0x3B 0x32000 +0x3A 0x001b4 //MG1 +0x3B 0x2a000 +0x3A 0x001c4 //MG2 +0x3B 0x221c8 +0x3A 0x00188 //LG0 +0x3B 0x1a001 +//MB +0x3A 0x000c4 //HG1 +0x3B 0x7a000 +0x3A 0x001fc //HG2 +0x3B 0x72000 +0x3A 0x001b4 //MG1 +0x3B 0x6a000 +0x3A 0x001c4 //MG2 +0x3B 0x621c8 +0x3A 0x00188 //LG0 +0x3B 0x5a001 +//HB +0x3A 0x000c4 //HG1 +0x3B 0xba000 +0x3A 0x001fc //HG2 +0x3B 0xb2000 +0x3A 0x001b4 //MG1 +0x3B 0xaa000 +0x3A 0x001c4 //MG2 +0x3B 0xa21c8 +0x3A 0x00188 //LG0 +0x3B 0x9a001 + +0xEF 0x00000 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ACEE +0x34 0x49CEC +0x34 0x48CEA +0x34 0x478CD +0x34 0x464AC +0x34 0x4548C +0x34 0x44489 +0x34 0x4306C +0x34 0x4204C +0x34 0x41049 +0x34 0x40046 +//TX AGC 5GM +0x34 0x2ACED +0x34 0x298ED +0x34 0x288CE +0x34 0x274AD +0x34 0x2648D +0x34 0x2548A +0x34 0x2406D +0x34 0x2306A +0x34 0x2204A +0x34 0x21047 +0x34 0x20044 +//TX AGC 5GL +0x34 0x0ACED +0x34 0x098ED +0x34 0x088CD +0x34 0x074AD +0x34 0x0648D +0x34 0x0548A +0x34 0x0406D +0x34 0x0306A +0x34 0x0204A +0x34 0x01047 +0x34 0x00044 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00145 //LB 80M +0x35 0x08145 //LB 40M +0x35 0x10145 //LB 20M +0x35 0x20196 //MB 80M +0x35 0x28196 //MB 40M +0x35 0x30196 //MB 20M +0x35 0x401C7 //HB 80M +0x35 0x481C7 //HB 40M +0x35 0x501C7 //HB 20M +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x85633 //LB 80M +0x36 0x8D633 //LB 40M +0x36 0x95633 //non +0x36 0x9D633 //LB 20M +0x36 0xA6634 //MB 80M +0x36 0xAE634 //MB 40M +0x36 0xB6634 //non +0x36 0xBE634 //MB 20M +0x36 0xC67B4 //HB 80M +0x36 0xCE7B4 //HB 40M +0x36 0xD67B4 //non +0x36 0xDE7B4 //HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x0022A //LB +0x3C 0x00594 //MB +0x3C 0x00822 //HB +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0x02000 +0xEF 0x00000 + +0xDF 0x000C0 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +0x58 0x01184 //LO leakage +0x59 0x6006C //IQGEN + +0x61 0xEAD53 +0x62 0x93BC4 +0x63 0x714E7 +0x64 0x1A88C +0x65 0x91014 + +//APK +//0x63 0x70EE9 //LB +//0x63 0x70EE9 //MB +//0x63 0x71267 //HB + +//SYN setting +0xB3 0xF0E18 //Ires; F0340:Ibg. sel_ioffset DN for LCK *by Andy +0xB4 0x13E4C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0xB7 0x30008 +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +//0xB3 0xF0E18 //sel_ioffset UP *by Andy +0xB4 0x1364C //LC CAL. NORMAL OPERATION:1A68D(Ires); 1A689:Ibg *by Andy +0x18 0x1712A //set ch42 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x39258 //Gain 7 +0x3B 0x31258 //Gain 6 +0x3B 0x29258 //Gain 5 +0x3B 0x27a58 //Gain 4 xx have problem +0x3B 0x1fa58 //Gain 3 +0x3B 0x12590 //Gain 2 +0x3B 0x08248 //Gain 1 +0x3B 0x00a40 //Gain 0 +0xEF 0x00000 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF0 +0x34 0x09DED +0x34 0x08DEA +0x34 0x07DE7 +0x34 0x06CEA +0x34 0x05CE7 +0x34 0x044EA +0x34 0x034E7 +0x34 0x0246A +0x34 0x01467 +0x34 0x0006A +0xEF 0x00000 + +//RX_BTG GainTable +0xED 0x00001 +0x40 0x38da7 //Gain 7 +0x40 0x300c2 //Gain 6 +//0x40 0x28ce6 //Gain 5 +0x40 0x288e2 //Gain 5 cck +0x40 0x200b8 //Gain 4 cck +0x40 0x188a5 //Gain 3 +0x40 0x10fbc //Gain 2 +0x40 0x08f71 //Gain 1 +0x40 0x00240 //Gain 0 +0xED 0x00000 + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//by PAK +//0xDF 0x00880 // APK setting and Gain table in debug mode +0x56 0x51DF3 +0x51 0x00C01 +0x52 0x006D6 +0x53 0xFC649 +0xDD 0x00040 +0x70 0x49661 +0x71 0x7843E +0x72 0x00382 +0x74 0x51400 + +0x35 0x00160 +0x35 0x08160 +0x35 0x10160 + +0x36 0x00124 +0x36 0x08124 +0x36 0x10124 +0x36 0x18124 + +0xED 0x0000c +0x45 0x00160 +//0x45 0x08160 +//0x45 0x10160 + +//0x46 0x00124 +//0x46 0x08124 +//0x46 0x10124 +//0x46 0x18124 + +0xDF 0x00088 // Enable RXBB=0 + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F + + +//by PAK +//0xDF 0x20F88 +//0x56 0x51DEE +//0x58 0x01198 +//0x61 0xFCD63 +//0x62 0x93FC2 +//0x63 0x114E9 +//0x64 0x19DEC +//0x65 0x911D5 +//0xB2 0x8583F 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/HalCfg.c b/package/kernel/rtl8192cd/WlanHAL/HalCfg.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalCfg.h b/package/kernel/rtl8192cd/WlanHAL/HalCfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalCommon.c b/package/kernel/rtl8192cd/WlanHAL/HalCommon.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalCommon.h b/package/kernel/rtl8192cd/WlanHAL/HalCommon.h old mode 100755 new mode 100644 index f530822b59f..4ee0a2b51cb --- a/package/kernel/rtl8192cd/WlanHAL/HalCommon.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalCommon.h @@ -1,163 +1,163 @@ -#ifndef __HALCOMMON_H__ -#define __HALCOMMON_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalCommon.h - -Abstract: - Defined HAL Common - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-05-18 Lun-Wu Create. ---*/ - -// Total 32bytes, we need control in 8bytes - -// TODO: temp setting, we need to move to matching file -// Some setting can be replaced after normal MAC reg.h are released - -// Loopback mode. -#define LBMODE_NORMAL 0x00 -#define LBMODE_MAC 0x0B -#define LBMODE_MAC_DLY 0x03 - -/* -Network Type -00: No link -01: Link in ad hoc network -10: Link in infrastructure network -11: AP mode -Default: 00b. -*/ -#define MSR_NOLINK 0x00 -#define MSR_ADHOC 0x01 -#define MSR_INFRA 0x02 -#define MSR_AP 0x03 - -//---------------------------------------------------------------------------- -// (PBP) Packet Buffer Page Register (Offset 0x104[7:4], 4 bits) -//---------------------------------------------------------------------------- -#define PBP_UNIT 128 - -//TXBD_IDX Common -#define BIT_SHIFT_QUEUE_HOST_IDX 0 -#define BIT_SHIFT_QUEUE_HW_IDX 16 -#define BIT_MASK_QUEUE_IDX 0x0FFF - - -VOID -HalGeneralDummy( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -HAL_ReadTypeID( - INPUT HAL_PADAPTER Adapter -); - -VOID -ResetHALIndex( - VOID -); - -VOID -DecreaseHALIndex( - VOID -); - -RT_STATUS -HalAssociateNic( - HAL_PADAPTER Adapter, - BOOLEAN IsDefaultAdapter -); - -RT_STATUS -HalDisAssociateNic( - HAL_PADAPTER Adapter, - BOOLEAN IsDefaultAdapter -); - -VOID -SoftwareCRC32 ( - IN pu1Byte pBuf, - IN u2Byte byteNum, - OUT pu4Byte pCRC32 -); - - -u1Byte -GetXorResultWithCRC ( - IN u1Byte a, - IN u1Byte b -); - -u1Byte -CRC5 ( - IN pu1Byte dwInput, - IN u1Byte len -); - -VOID -SoftwareCRC32_RXBuffGather ( - IN pu1Byte pPktBufAddr, - IN pu2Byte pPktBufLen, - IN u2Byte pktNum, - OUT pu4Byte pCRC32 -); - -RT_STATUS -GetTxRPTBuf88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte macID, - IN u1Byte variable, - IN u1Byte byteoffset, - OUT pu1Byte val -); - -RT_STATUS -SetTxRPTBuf88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte macID, - IN u1Byte variable, - IN pu1Byte val -); - -VOID -SetCRC5ToRPTBuffer88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte val, - IN u4Byte macID, - IN u1Byte bValid - -); - -RT_STATUS -ReleaseOnePacket88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte macID -); - -BOOLEAN -LoadFileToIORegTable( - IN pu1Byte pRegFileStart, - IN u4Byte RegFileLen, - OUT pu1Byte pTableStart, - IN u4Byte TableEleNum -); - -BOOLEAN -LoadFileToOneParaTable( - IN pu1Byte pFileStart, - IN u4Byte FileLen, - OUT pu1Byte pTableStart, - IN u4Byte TableEleNum -); - -#endif // __HALCOMMON_H__ - +#ifndef __HALCOMMON_H__ +#define __HALCOMMON_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalCommon.h + +Abstract: + Defined HAL Common + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-05-18 Lun-Wu Create. +--*/ + +// Total 32bytes, we need control in 8bytes + +// TODO: temp setting, we need to move to matching file +// Some setting can be replaced after normal MAC reg.h are released + +// Loopback mode. +#define LBMODE_NORMAL 0x00 +#define LBMODE_MAC 0x0B +#define LBMODE_MAC_DLY 0x03 + +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +//---------------------------------------------------------------------------- +// (PBP) Packet Buffer Page Register (Offset 0x104[7:4], 4 bits) +//---------------------------------------------------------------------------- +#define PBP_UNIT 128 + +//TXBD_IDX Common +#define BIT_SHIFT_QUEUE_HOST_IDX 0 +#define BIT_SHIFT_QUEUE_HW_IDX 16 +#define BIT_MASK_QUEUE_IDX 0x0FFF + + +VOID +HalGeneralDummy( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +HAL_ReadTypeID( + INPUT HAL_PADAPTER Adapter +); + +VOID +ResetHALIndex( + VOID +); + +VOID +DecreaseHALIndex( + VOID +); + +RT_STATUS +HalAssociateNic( + HAL_PADAPTER Adapter, + BOOLEAN IsDefaultAdapter +); + +RT_STATUS +HalDisAssociateNic( + HAL_PADAPTER Adapter, + BOOLEAN IsDefaultAdapter +); + +VOID +SoftwareCRC32 ( + IN pu1Byte pBuf, + IN u2Byte byteNum, + OUT pu4Byte pCRC32 +); + + +u1Byte +GetXorResultWithCRC ( + IN u1Byte a, + IN u1Byte b +); + +u1Byte +CRC5 ( + IN pu1Byte dwInput, + IN u1Byte len +); + +VOID +SoftwareCRC32_RXBuffGather ( + IN pu1Byte pPktBufAddr, + IN pu2Byte pPktBufLen, + IN u2Byte pktNum, + OUT pu4Byte pCRC32 +); + +RT_STATUS +GetTxRPTBuf88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte macID, + IN u1Byte variable, + IN u1Byte byteoffset, + OUT pu1Byte val +); + +RT_STATUS +SetTxRPTBuf88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte macID, + IN u1Byte variable, + IN pu1Byte val +); + +VOID +SetCRC5ToRPTBuffer88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte val, + IN u4Byte macID, + IN u1Byte bValid + +); + +RT_STATUS +ReleaseOnePacket88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte macID +); + +BOOLEAN +LoadFileToIORegTable( + IN pu1Byte pRegFileStart, + IN u4Byte RegFileLen, + OUT pu1Byte pTableStart, + IN u4Byte TableEleNum +); + +BOOLEAN +LoadFileToOneParaTable( + IN pu1Byte pFileStart, + IN u4Byte FileLen, + OUT pu1Byte pTableStart, + IN u4Byte TableEleNum +); + +#endif // __HALCOMMON_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.c b/package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.h b/package/kernel/rtl8192cd/WlanHAL/HalDbgCmd.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalDef.h b/package/kernel/rtl8192cd/WlanHAL/HalDef.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComBit.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComBit.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyBit.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyBit.h old mode 100755 new mode 100644 index 7751f109d52..8721374dd14 --- a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyBit.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyBit.h @@ -1,696 +1,696 @@ -#ifndef __INC_HALCOMPHYBIT_H -#define __INC_HALCOMPHYBIT_H - -/*-------------------------Modification Log----------------------------------- - --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ - -//3 ============Programming guide Start===================== -/* - BB BIT define rules - 1. For all bit define, it should be prefixed by "BIT_BB" - 2. For all bit mask, it should be prefixed by "BIT_MASK_BB" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_BB" - 4. For other case, prefix is not needed - - RF BIT define rules - 1. For all bit define, it should be prefixed by "BIT_RF" - 2. For all bit mask, it should be prefixed by "BIT_MASK_RF" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_RF" - 4. For other case, prefix is not needed - - SET BIT define rules - 1. Setting byte mask for BB or RF, it should be prefixed by "BIT_SET" - - Suffixed BIT define rules - 1. For AC chip, it should be suffixed by "_AC" - 2. For N chip, it should be suffixed by "_N" - 3. For Common bit define, it should be suffixed by "_COMMON" - -*/ -#if IS_RTL88XX_AC -/**** page 8 ****/ - -//REG_BB_RCCKENABLE_AC offset:0x808 -#define BIT_MASK_BB_BOFDMEN_AC 0x20000000 -#define BIT_MASK_BB_BCCKEN_AC 0x10000000 -#define BIT_MASK_BB_BRXPATH_AC 0xff - -//REG_BB_RTXPATH_AC offset:0x80c -#define BIT_MASK_BB_BTXPATH_AC 0x0fffffff - -//REG_BB_RAGC_TABLE_AC offset:0x82c // AGC tabel select -#define BIT_MASK_BB_BAGC_TABLE_AC 0x3 - -//REG_BB_CCAONSEC_AC offset:0x838 -#define BIT_MASK_BB_CCA_AC 0xf - -//REG_BB_REDCCA_AC offset:0x8a4 // EDCCA -#define BIT_MASK_BB_BEDCCA_AC 0xffff - -//REG_BB_RHSSIREAD_AC offset:0x8b0 // RF read addr -#define BIT_MASK_BB_BHSSIREAD_ADDR_AC 0xff - -/**** page 9 ****/ -//REG_BB_AGC_TABLE_AC_V2 0x958 -#define BIT_MASK_BB_BAGC_TABLE_AC_V2 0x0000001f - - -/**** page a ****/ -//REG_BB_RCCK_SYSTEM_AC offset: 0xa00 // for cck sideband -#define BIT_MASK_BB_BCCK_SYSTEM_AC 0x10 -//REG_BB_RCCK_RX_AC offset: 0xa04 // for cck rx path selection -#define BIT_MASK_BB_BCCK_RX_AC 0x0c000000 -//REG_BB_RCCK_CCA_AC offset: 0xa08 // cca threshold -#define BIT_MASK_BB_BCCK_CCA_AC 0x00ff0000 - -// REG_BB_RCCK_TXFILTER1_AC offset: 0xa20 -#define BIT_MASK_BB_BCCK_TXFILTER1_C0_AC 0x00ff0000 -#define BIT_MASK_BB_BCCK_TXFILTER1_C1_AC 0xff000000 -//REG_BB_RCCK_TXFILTER2_AC offset: 0xa24 -#define BIT_MASK_BB_BCCK_TXFILTER2_C2_AC 0x000000ff -#define BIT_MASK_BB_BCCK_TXFILTER2_C3_AC 0x0000ff00 -#define BIT_MASK_BB_BCCK_TXFILTER2_C4_AC 0x00ff0000 -#define BIT_MASK_BB_BCCK_TXFILTER2_C5_AC 0xff000000 -//REG_BB_RCCK_TXFILTER3_AC offset: 0xa28 -#define BIT_MASK_BB_BCCK_TXFILTER3_C6_AC 0x000000ff -#define BIT_MASK_BB_BCCK_TXFILTER3_C7_AC 0x0000ff00 -//REG_BB_RCCK_FALSEALARM_AC offset: 0xa5c // counter for cck false alarm -#define BIT_MASK_BB_B_FALSEALARM_AC 0xffff -/**** page b ****/ -/**** page c ****/ -//REG_BB_AGC_TABLE_AC_V1 0xc1c -#define BIT_MASK_BB_BAGC_TABLE_AC_V1 0x00000f00 -//REG_BB_A_LSSIWRITE_AC offset :0xc90 -#define BIT_MASK_BB_LSSIWRITE_AC 0xf0000000 -/**** page d ****/ -/**** page e ****/ - - -#endif //#if IS_RTL88XX_AC - - -#if IS_RTL88XX_N - -// -// 2. Page8(0x800) -// -#define BIT_MASK_BB_RFMOD_N_N 0x1 // Reg 0x800 rFPGA0_RFMOD -#define BIT_MASK_BB_JAPANMODE_N 0x2 -#define BIT_MASK_BB_CCKTXSC_N 0x30 -#define BIT_MASK_BB_CCKEN_N 0x1000000 -#define BIT_MASK_BB_OFDMEN_N 0x2000000 -#define BIT_MASK_BB_OFDMRXADCPHASE_N 0x10000 // Useless now -#define BIT_MASK_BB_OFDMTXDACPHASE_N 0x40000 - -#define BIT_MASK_BB_XATXAGC_N 0x3f -#define BIT_MASK_BB_XBTXAGC_N 0xf00 // Reg 80c rFPGA0_TxGainStage -/* -#define BIT_MASK_BB_XCTXAGC_N 0xf000 -#define BIT_MASK_BB_XDTXAGC_N 0xf0000 -*/ - -#define BIT_MASK_BB_PASTART_N 0xf0000000 // Useless now -#define BIT_MASK_BB_TRSTART_N 0x00f00000 -#define BIT_MASK_BB_RFSTART_N 0x0000f000 -#define BIT_MASK_BB_BBSTART_N 0x000000f0 -#define BIT_MASK_BB_BBCCKSTART_N 0x0000000f -#define BIT_MASK_BB_PAEND_N 0xf //Reg0x814 -#define BIT_MASK_BB_TREND_N 0x0f000000 -#define BIT_MASK_BB_RFEND_N 0x000f0000 -#define BIT_MASK_BB_CCAMASK_N 0x000000f0 //T2R -#define BIT_MASK_BB_R2RCCAMASK_N 0x00000f00 -#define BIT_MASK_BB_HSSI_R2TDELAY_N 0xf8000000 -#define BIT_MASK_BB_HSSI_T2RDELAY_N 0xf80000 -#define BIT_MASK_BB_CONTTXHSSI_N 0x400 //chane gain at continue Tx -#define BIT_MASK_BB_IGFROMCCK_N 0x200 -#define BIT_MASK_BB_AGCADDRESS_N 0x3f -#define BIT_MASK_BB_RXHPTX_N 0x7000 -#define BIT_MASK_BB_RXHPT2R_N 0x38000 -#define BIT_MASK_BB_RXHPCCKINI_N 0xc0000 -#define BIT_MASK_BB_AGCTXCODE_N 0xc00000 -#define BIT_MASK_BB_AGCRXCODE_N 0x300000 - -#define BIT_MASK_BB_3WIREDATALENGTH_N 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 -#define BIT_MASK_BB_3WIREADDRESSLENGTH_N 0x400 - -#define BIT_MASK_BB_3WIRERFPOWERDOWN_N 0x1 // Useless now -#define BIT_MASK_BB_5GPAPEPOLARITY_N 0x40000000 -#define BIT_MASK_BB_2GPAPEPOLARITY_N 0x80000000 -#define BIT_MASK_BB_RFSW_TXDEFAULTANT_N 0x3 -#define BIT_MASK_BB_RFSW_TXOPTIONANT_N 0x30 -#define BIT_MASK_BB_RFSW_RXDEFAULTANT_N 0x300 -#define BIT_MASK_BB_RFSW_RXOPTIONANT_N 0x3000 -#define BIT_MASK_BB_RFSI_3WIREDATA_N 0x1 -#define BIT_MASK_BB_RFSI_3WIRECLOCK_N 0x2 -#define BIT_MASK_BB_RFSI_3WIRELOAD_N 0x4 -#define BIT_MASK_BB_RFSI_3WIRERW_N 0x8 -#define BIT_MASK_BB_RFSI_3WIRE_N 0xf - -#define BIT_MASK_BB_RFSI_RFENV_N 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW -#define BIT_MASK_BB_RFSI_TRSW_N 0x20 // Useless now -#define BIT_MASK_BB_RFSI_TRSWB_N 0x40 -#define BIT_MASK_BB_RFSI_ANTSW_N 0x100 -#define BIT_MASK_BB_RFSI_ANTSWB_N 0x200 -#define BIT_MASK_BB_RFSI_PAPE_N 0x400 -#define BIT_MASK_BB_RFSI_PAPE5G_N 0x800 -#define BIT_MASK_BB_BANDSELECT_N 0x1 -#define BIT_MASK_BB_HTSIG2_GI_N 0x80 -#define BIT_MASK_BB_HTSIG2_SMOOTHING_N 0x01 -#define BIT_MASK_BB_HTSIG2_SOUNDING_N 0x02 -#define BIT_MASK_BB_HTSIG2_AGGREATON_N 0x08 -#define BIT_MASK_BB_HTSIG2_STBC_N 0x30 -#define BIT_MASK_BB_HTSIG2_ADVCODING_N 0x40 -#define BIT_MASK_BB_HTSIG2_NUMOFHTLTF_N 0x300 -#define BIT_MASK_BB_HTSIG2_CRC8_N 0x3fc -#define BIT_MASK_BB_HTSIG1_MCS_N 0x7f -#define BIT_MASK_BB_HTSIG1_BANDWIDTH_N 0x80 -#define BIT_MASK_BB_HTSIG1_HTLENGTH_N 0xffff -#define BIT_MASK_BB_LSIG_RATE_N 0xf -#define BIT_MASK_BB_LSIG_RESERVED_N 0x10 -#define BIT_MASK_BB_LSIG_LENGTH_N 0x1fffe -#define BIT_MASK_BB_LSIG_PARITY_N 0x20 -#define BIT_MASK_BB_CCKRXPHASE_N 0x4 - -//#define BIT_MASK_BB_LSSIREADADDRESS 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 -#define BIT_MASK_BB_LSSIREADADDRESS_N 0x7f800000 // T65 RF -#define BIT_MASK_BB_LSSIREADEDGE_N 0x80000000 //LSSI "Read" edge signal - -//#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack -#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfffff // T65 RF - -#define BIT_MASK_BB_LSSIREADOKFLAG_N 0x1000 // Useless now -#define BIT_MASK_BB_CCKSAMPLERATE_N 0x8 //0: 44MHz, 1:88MHz -#define BIT_MASK_BB_REGULATOR0STANDBY_N 0x1 -#define BIT_MASK_BB_REGULATORPLLSTANDBY_N 0x2 -#define BIT_MASK_BB_REGULATOR1STANDBY_N 0x4 -#define BIT_MASK_BB_PLLPOWERUP_N 0x8 -#define BIT_MASK_BB_DPLLPOWERUP_N 0x10 -#define BIT_MASK_BB_DA10POWERUP_N 0x20 -#define BIT_MASK_BB_AD7POWERUP_N 0x200 -#define BIT_MASK_BB_DA6POWERUP_N 0x2000 -#define BIT_MASK_BB_XTALPOWERUP_N 0x4000 -#define BIT_MASK_BB_40MDCLKPOWERUP_N 0x8000 -#define BIT_MASK_BB_DA6DEBUGMODE_N 0x20000 -#define BIT_MASK_BB_DA6SWING_N 0x380000 - -#define BIT_MASK_BB_ADCLKPHASE_N 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ - -#define BIT_MASK_BB_80MCLKDELAY_N 0x18000000 // Useless -#define BIT_MASK_BB_AFEWATCHDOGENABLE_N 0x20000000 - -#define BIT_MASK_BB_XTALCAP01_N 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap -#define BIT_MASK_BB_XTALCAP23_N 0x3 -#define BIT_MASK_BB_XTALCAP92X_N 0x0f000000 - -#define BIT_MASK_BB_INTDIFCLKENABLE_N 0x400 // Useless -#define BIT_MASK_BB_EXTSIGCLKENABLE_N 0x800 -#define BIT_MASK_BB_BANDGAPMBIASPOWERUP_N 0x10000 -#define BIT_MASK_BB_AD11SHGAIN_N 0xc0000 -#define BIT_MASK_BB_AD11INPUTRANGE_N 0x700000 -#define BIT_MASK_BB_AD11OPCURRENT_N 0x3800000 -#define BIT_MASK_BB_IPATHLOOPBACK_N 0x4000000 -#define BIT_MASK_BB_QPATHLOOPBACK_N 0x8000000 -#define BIT_MASK_BB_AFELOOPBACK_N 0x10000000 -#define BIT_MASK_BB_DA10SWING_N 0x7e0 -#define BIT_MASK_BB_DA10REVERSE_N 0x800 -#define BIT_MASK_BB_DACLKSOURCE_N 0x1000 -#define BIT_MASK_BB_AD7INPUTRANGE_N 0x6000 -#define BIT_MASK_BB_AD7GAIN_N 0x38000 -#define BIT_MASK_BB_AD7OUTPUTCMMODE_N 0x40000 -#define BIT_MASK_BB_AD7INPUTCMMODE_N 0x380000 -#define BIT_MASK_BB_AD7CURRENT_N 0xc00000 -#define BIT_MASK_BB_REGULATORADJUST_N 0x7000000 -#define BIT_MASK_BB_AD11POWERUPATTX_N 0x1 -#define BIT_MASK_BB_DA10PSATTX_N 0x10 -#define BIT_MASK_BB_AD11POWERUPATRX_N 0x100 -#define BIT_MASK_BB_DA10PSATRX_N 0x1000 -#define BIT_MASK_BB_CCKRXAGCFORMAT_N 0x200 -#define BIT_MASK_BB_PSDFFTSAMPLEPPOINT_N 0xc000 -#define BIT_MASK_BB_PSDAVERAGENUM_N 0x3000 -#define BIT_MASK_BB_IQPATHCONTROL_N 0xc00 -#define BIT_MASK_BB_PSDFREQ_N 0x3ff -#define BIT_MASK_BB_PSDANTENNAPATH_N 0x30 -#define BIT_MASK_BB_PSDIQSWITCH_N 0x40 -#define BIT_MASK_BB_PSDRXTRIGGER_N 0x400000 -#define BIT_MASK_BB_PSDTXTRIGGER_N 0x80000000 -#define BIT_MASK_BB_PSDSINETONESCALE_N 0x7f000000 -#define BIT_MASK_BB_PSDREPORT_N 0xffff - - -// -// 3. Page9(0x900) -// -#define BIT_MASK_BB_OFDMTXSC_N 0x30000000 // Useless -#define BIT_MASK_BB_CCKTXON_N 0x1 -#define BIT_MASK_BB_OFDMTXON_N 0x2 -#define BIT_MASK_BB_DEBUGPAGE_N 0xfff //reset debug page and also HWord, LWord -#define BIT_MASK_BB_DEBUGITEM_N 0xff //reset debug page and LWord -#define BIT_MASK_BB_ANTL_N 0x10 -#define BIT_MASK_BB_ANTNONHT_N 0x100 -#define BIT_MASK_BB_ANTHT1_N 0x1000 -#define BIT_MASK_BB_ANTHT2_N 0x10000 -#define BIT_MASK_BB_ANTHT1S1_N 0x100000 -#define BIT_MASK_BB_ANTNONHTS1_N 0x1000000 - - -// -// 4. PageA(0xA00) -// -#define BIT_MASK_BB_CCKBBMODE_N 0x3 // Useless -#define BIT_MASK_BB_CCKTXPOWERSAVING_N 0x80 -#define BIT_MASK_BB_CCKRXPOWERSAVING_N 0x40 -#define BIT_MASK_BB_CCKSIDEBAND_N 0x10 // Reg 0xa00 rCCK0_System 20/40 switch -#define BIT_MASK_BB_CCKSCRAMBLE_N 0x8 // Useless -#define BIT_MASK_BB_CCKANTDIVERSITY_N 0x8000 -#define BIT_MASK_BB_CCKCARRIERRECOVERY_N 0x4000 -#define BIT_MASK_BB_CCKTXRATE_N 0x3000 -#define BIT_MASK_BB_CCKDCCANCEL_N 0x0800 -#define BIT_MASK_BB_CCKISICANCEL_N 0x0400 -#define BIT_MASK_BB_CCKMATCHFILTER_N 0x0200 -#define BIT_MASK_BB_CCKEQUALIZER_N 0x0100 -#define BIT_MASK_BB_CCKPREAMBLEDETECT_N 0x800000 -#define BIT_MASK_BB_CCKFASTFALSECCA_N 0x400000 -#define BIT_MASK_BB_CCKCHESTSTART_N 0x300000 -#define BIT_MASK_BB_CCKCCACOUNT_N 0x080000 -#define BIT_MASK_BB_CCKCS_LIM_N 0x070000 -#define BIT_MASK_BB_CCKBISTMODE_N 0x80000000 -#define BIT_MASK_BB_CCKCCAMASK_N 0x40000000 -#define BIT_MASK_BB_CCKTXDACPHASE_N 0x4 -#define BIT_MASK_BB_CCKRXADCPHASE_N 0x20000000 //r_rx_clk -#define BIT_MASK_BB_CCKR_CP_MODE0_N 0x0100 -#define BIT_MASK_BB_CCKTXDCOFFSET_N 0xf0 -#define BIT_MASK_BB_CCKRXDCOFFSET_N 0xf -#define BIT_MASK_BB_CCKCCAMODE_N 0xc000 -#define BIT_MASK_BB_CCKFALSECS_LIM_N 0x3f00 -#define BIT_MASK_BB_CCKCS_RATIO_N 0xc00000 -#define BIT_MASK_BB_CCKCORGBIT_SEL_N 0x300000 -#define BIT_MASK_BB_CCKPD_LIM_N 0x0f0000 -#define BIT_MASK_BB_CCKNEWCCA_N 0x80000000 -#define BIT_MASK_BB_CCKRXHPOFIG_N 0x8000 -#define BIT_MASK_BB_CCKRXIG_N 0x7f00 -#define BIT_MASK_BB_CCKLNAPOLARITY_N 0x800000 -#define BIT_MASK_BB_CCKRX1STGAIN_N 0x7f0000 -#define BIT_MASK_BB_CCKRFEXTEND_N 0x20000000 //CCK Rx Iinital gain polarity -#define BIT_MASK_BB_CCKRXAGCSATLEVEL_N 0x1f000000 -#define BIT_MASK_BB_CCKRXAGCSATCOUNT_N 0xe0 -#define BIT_MASK_BB_CCKRXRFSETTLE_N 0x1f //AGCsamp_dly -#define BIT_MASK_BB_CCKFIXEDRXAGC_N 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define BIT_MASK_BB_CCKANTENNAPOLARITY_N 0x2000 -#define BIT_MASK_BB_CCKTXFILTERTYPE_N 0x0c00 -#define BIT_MASK_BB_CCKRXAGCREPORTTYPE_N 0x0300 -#define BIT_MASK_BB_CCKRXDAGCEN_N 0x80000000 -#define BIT_MASK_BB_CCKRXDAGCPERIOD_N 0x20000000 -#define BIT_MASK_BB_CCKRXDAGCSATLEVEL_N 0x1f000000 -#define BIT_MASK_BB_CCKTIMINGRECOVERY_N 0x800000 -#define BIT_MASK_BB_CCKTXC0_N 0x3f0000 -#define BIT_MASK_BB_CCKTXC1_N 0x3f000000 -#define BIT_MASK_BB_CCKTXC2_N 0x3f -#define BIT_MASK_BB_CCKTXC3_N 0x3f00 -#define BIT_MASK_BB_CCKTXC4_N 0x3f0000 -#define BIT_MASK_BB_CCKTXC5_N 0x3f000000 -#define BIT_MASK_BB_CCKTXC6_N 0x3f -#define BIT_MASK_BB_CCKTXC7_N 0x3f00 -#define BIT_MASK_BB_CCKDEBUGPORT_N 0xff0000 -#define BIT_MASK_BB_CCKDACDEBUG_N 0x0f000000 -#define BIT_MASK_BB_CCKFALSEALARMENABLE_N 0x8000 -#define BIT_MASK_BB_CCKFALSEALARMREAD_N 0x4000 -#define BIT_MASK_BB_CCKTRSSI_N 0x7f -#define BIT_MASK_BB_CCKRXAGCREPORT_N 0xfe -#define BIT_MASK_BB_CCKRXREPORT_ANTSEL_N 0x80000000 -#define BIT_MASK_BB_CCKRXREPORT_MFOFF_N 0x40000000 -#define BIT_MASK_BB_CCKRXRXREPORT_SQLOSS_N 0x20000000 -#define BIT_MASK_BB_CCKRXREPORT_PKTLOSS_N 0x10000000 -#define BIT_MASK_BB_CCKRXREPORT_LOCKEDBIT_N 0x08000000 -#define BIT_MASK_BB_CCKRXREPORT_RATEERROR_N 0x04000000 -#define BIT_MASK_BB_CCKRXREPORT_RXRATE_N 0x03000000 -#define BIT_MASK_BB_CCKRXFACOUNTERLOWER_N 0xff -#define BIT_MASK_BB_CCKRXFACOUNTERUPPER_N 0xff000000 -#define BIT_MASK_BB_CCKRXHPAGCSTART_N 0xe000 -#define BIT_MASK_BB_CCKRXHPAGCFINAL_N 0x1c00 -#define BIT_MASK_BB_CCKRXFALSEALARMENABLE_N 0x8000 -#define BIT_MASK_BB_CCKFACOUNTERFREEZE_N 0x4000 -#define BIT_MASK_BB_CCKTXPATHSEL_N 0x10000000 -#define BIT_MASK_BB_CCKDEFAULTRXPATH_N 0xc000000 -#define BIT_MASK_BB_CCKOPTIONRXPATH_N 0x3000000 - - -// -// 5. PageC(0xC00) -// -#define BIT_MASK_BB_NUMOFSTF_N 0x3 // Useless -#define BIT_MASK_BB_SHIFT_L_N 0xc0 -#define BIT_MASK_BB_GI_TH_N 0xc -#define BIT_MASK_BB_RXPATHA_N 0x1 -#define BIT_MASK_BB_RXPATHB_N 0x2 -#define BIT_MASK_BB_RXPATHC_N 0x4 -#define BIT_MASK_BB_RXPATHD_N 0x8 -#define BIT_MASK_BB_TXPATHA_N 0x1 -#define BIT_MASK_BB_TXPATHB_N 0x2 -#define BIT_MASK_BB_TXPATHC_N 0x4 -#define BIT_MASK_BB_TXPATHD_N 0x8 -#define BIT_MASK_BB_TRSSIFREQ_N 0x200 -#define BIT_MASK_BB_ADCBACKOFF_N 0x3000 -#define BIT_MASK_BB_DFIRBACKOFF_N 0xc000 -#define BIT_MASK_BB_TRSSILATCHPHASE_N 0x10000 -#define BIT_MASK_BB_RXIDCOFFSET_N 0xff -#define BIT_MASK_BB_RXQDCOFFSET_N 0xff00 -#define BIT_MASK_BB_RXDFIRMODE_N 0x1800000 -#define BIT_MASK_BB_RXDCNFTYPE_N 0xe000000 -#define BIT_MASK_BB_RXIQIMB_A_N 0x3ff -#define BIT_MASK_BB_RXIQIMB_B_N 0xfc00 -#define BIT_MASK_BB_RXIQIMB_C_N 0x3f0000 -#define BIT_MASK_BB_RXIQIMB_D_N 0xffc00000 -#define BIT_MASK_BB_DC_DC_NOTCH_N 0x60000 -#define BIT_MASK_BB_RXNBINOTCH_N 0x1f000000 -#define BIT_MASK_BB_PD_TH_N 0xf -#define BIT_MASK_BB_PD_TH_OPT2_N 0xc000 -#define BIT_MASK_BB_PWED_TH_N 0x700 -#define BIT_MASK_BB_IFMF_WIN_L_N 0x800 -#define BIT_MASK_BB_PD_OPTION_N 0x1000 -#define BIT_MASK_BB_MF_WIN_L_N 0xe000 -#define BIT_MASK_BB_BW_SEARCH_L_N 0x30000 -#define BIT_MASK_BB_WIN_ENH_L_N 0xc0000 -#define BIT_MASK_BB_BW_TH_N 0x700000 -#define BIT_MASK_BB_ED_TH2_N 0x3800000 -#define BIT_MASK_BB_BW_OPTION_N 0x4000000 -#define BIT_MASK_BB_RATIO_TH_N 0x18000000 -#define BIT_MASK_BB_WINDOW_L_N 0xe0000000 -#define BIT_MASK_BB_SBD_OPTION_N 0x1 -#define BIT_MASK_BB_FRAME_TH_N 0x1c -#define BIT_MASK_BB_FS_OPTION_N 0x60 -#define BIT_MASK_BB_DC_SLOPE_CHECK_N 0x80 -#define BIT_MASK_BB_FGUARD_COUNTER_DC_L_N 0xe00 -#define BIT_MASK_BB_FRAME_WEIGHT_SHORT_N 0x7000 -#define BIT_MASK_BB_SUB_TUNE_N 0xe00000 -#define BIT_MASK_BB_FRAME_DC_LENGTH_N 0xe000000 -#define BIT_MASK_BB_SBD_START_OFFSET_N 0x30000000 -#define BIT_MASK_BB_FRAME_TH_2_N 0x7 -#define BIT_MASK_BB_FRAME_GI2_TH_N 0x38 -#define BIT_MASK_BB_GI2_SYNC_EN_N 0x40 -#define BIT_MASK_BB_SARCH_SHORT_EARLY_N 0x300 -#define BIT_MASK_BB_SARCH_SHORT_LATE_N 0xc00 -#define BIT_MASK_BB_SARCH_GI2_LATE_N 0x70000 -#define BIT_MASK_BB_CFOANTSUM_N 0x1 -#define BIT_MASK_BB_CFOACC_N 0x2 -#define BIT_MASK_BB_CFOSTARTOFFSET_N 0xc -#define BIT_MASK_BB_CFOLOOKBACK_N 0x70 -#define BIT_MASK_BB_CFOSUMWEIGHT_N 0x80 -#define BIT_MASK_BB_DAGCENABLE_N 0x10000 -#define BIT_MASK_BB_TXIQIMB_A_N 0x3ff -#define BIT_MASK_BB_TXIQIMB_B_N 0xfc00 -#define BIT_MASK_BB_TXIQIMB_C_N 0x3f0000 -#define BIT_MASK_BB_TXIQIMB_D_N 0xffc00000 -#define BIT_MASK_BB_TXIDCOFFSET_N 0xff -#define BIT_MASK_BB_TXQDCOFFSET_N 0xff00 -#define BIT_MASK_BB_TXDFIRMODE_N 0x10000 -#define BIT_MASK_BB_TXPESUDONOISEON_N 0x4000000 -#define BIT_MASK_BB_TXPESUDONOISE_A_N 0xff -#define BIT_MASK_BB_TXPESUDONOISE_B_N 0xff00 -#define BIT_MASK_BB_TXPESUDONOISE_C_N 0xff0000 -#define BIT_MASK_BB_TXPESUDONOISE_D_N 0xff000000 -#define BIT_MASK_BB_CCADROPOPTION_N 0x20000 -#define BIT_MASK_BB_CCADROPTHRES_N 0xfff00000 -#define BIT_MASK_BB_EDCCA_H_N 0xf -#define BIT_MASK_BB_EDCCA_L_N 0xf0 -#define BIT_MASK_BB_LAMBDA_ED_N 0x300 -#define BIT_MASK_BB_RXINITIALGAIN_N 0x7f -#define BIT_MASK_BB_RXANTDIVEN_N 0x80 -#define BIT_MASK_BB_RXAGCADDRESSFORLNA_N 0x7f00 -#define BIT_MASK_BB_RXHIGHPOWERFLOW_N 0x8000 -#define BIT_MASK_BB_RXAGCFREEZETHRES_N 0xc0000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC1_N 0x300000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC2_N 0xc00000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC3_N 0x3000000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC0_N 0xc000000 -#define BIT_MASK_BB_RXRSSI_CMP_EN_N 0x10000000 -#define BIT_MASK_BB_RXQUICKAGCEN_N 0x20000000 -#define BIT_MASK_BB_RXAGCFREEZETHRESMODE_N 0x40000000 -#define BIT_MASK_BB_RXOVERFLOWCHECKTYPE_N 0x80000000 -#define BIT_MASK_BB_RXAGCSHIFT_N 0x7f -#define BIT_MASK_BB_TRSW_TRI_ONLY_N 0x80 -#define BIT_MASK_BB_POWERTHRES_N 0x300 -#define BIT_MASK_BB_RXAGCEN_N 0x1 -#define BIT_MASK_BB_RXAGCTOGETHEREN_N 0x2 -#define BIT_MASK_BB_RXAGCMIN_N 0x4 -#define BIT_MASK_BB_RXHP_INI_N 0x7 -#define BIT_MASK_BB_RXHP_TRLNA_N 0x70 -#define BIT_MASK_BB_RXHP_RSSI_N 0x700 -#define BIT_MASK_BB_RXHP_BBP1_N 0x7000 -#define BIT_MASK_BB_RXHP_BBP2_N 0x70000 -#define BIT_MASK_BB_RXHP_BBP3_N 0x700000 -#define BIT_MASK_BB_RSSI_H_N 0x7f0000 //the threshold for high power -#define BIT_MASK_BB_RSSI_GEN_N 0x7f000000 //the threshold for ant diversity -#define BIT_MASK_BB_RXSETTLE_TRSW_N 0x7 -#define BIT_MASK_BB_RXSETTLE_LNA_N 0x38 -#define BIT_MASK_BB_RXSETTLE_RSSI_N 0x1c0 -#define BIT_MASK_BB_RXSETTLE_BBP_N 0xe00 -#define BIT_MASK_BB_RXSETTLE_RXHP_N 0x7000 -#define BIT_MASK_BB_RXSETTLE_ANTSW_RSSI_N 0x38000 -#define BIT_MASK_BB_RXSETTLE_ANTSW_N 0xc0000 -#define BIT_MASK_BB_RXPROCESSTIME_DAGC_N 0x300000 -#define BIT_MASK_BB_RXSETTLE_HSSI_N 0x400000 -#define BIT_MASK_BB_RXPROCESSTIME_BBPPW_N 0x800000 -#define BIT_MASK_BB_RXANTENNAPOWERSHIFT_N 0x3000000 -#define BIT_MASK_BB_RSSITABLESELECT_N 0xc000000 -#define BIT_MASK_BB_RXHP_FINAL_N 0x7000000 -#define BIT_MASK_BB_RXHTSETTLE_BBP_N 0x7 -#define BIT_MASK_BB_RXHTSETTLE_HSSI_N 0x8 -#define BIT_MASK_BB_RXHTSETTLE_RXHP_N 0x70 -#define BIT_MASK_BB_RXHTSETTLE_BBPPW_N 0x80 -#define BIT_MASK_BB_RXHTSETTLE_IDLE_N 0x300 -#define BIT_MASK_BB_RXHTSETTLE_RESERVED_N 0x1c00 -#define BIT_MASK_BB_RXHTRXHPEN_N 0x8000 -#define BIT_MASK_BB_RXHTAGCFREEZETHRES_N 0x30000 -#define BIT_MASK_BB_RXHTAGCTOGETHEREN_N 0x40000 -#define BIT_MASK_BB_RXHTAGCMIN_N 0x80000 -#define BIT_MASK_BB_RXHTAGCEN_N 0x100000 -#define BIT_MASK_BB_RXHTDAGCEN_N 0x200000 -#define BIT_MASK_BB_RXHTRXHP_BBP_N 0x1c00000 -#define BIT_MASK_BB_RXHTRXHP_FINAL_N 0xe0000000 -#define BIT_MASK_BB_RXPWRATIOTH_N 0x3 -#define BIT_MASK_BB_RXPWRATIOEN_N 0x4 -#define BIT_MASK_BB_RXMFHOLD_N 0x3800 -#define BIT_MASK_BB_RXPD_DELAY_TH1_N 0x38 -#define BIT_MASK_BB_RXPD_DELAY_TH2_N 0x1c0 -#define BIT_MASK_BB_RXPD_DC_COUNT_MAX_N 0x600 -//#define bRxMF_Hold 0x3800 -#define BIT_MASK_BB_RxPD_Delay_TH_N 0x8000 -#define BIT_MASK_BB_RxProcess_Delay_N 0xf0000 -#define BIT_MASK_BB_RxSearchrange_GI2_Early_N 0x700000 -#define BIT_MASK_BB_RxFrame_Guard_Counter_L_N 0x3800000 -#define BIT_MASK_BB_RxSGI_Guard_L_N 0xc000000 -#define BIT_MASK_BB_RxSGI_Search_L_N 0x30000000 -#define BIT_MASK_BB_RxSGI_TH_N 0xc0000000 -#define BIT_MASK_BB_DFSCnt0_N 0xff -#define BIT_MASK_BB_DFSCnt1_N 0xff00 -#define BIT_MASK_BB_DFSFlag_N 0xf0000 -#define BIT_MASK_BB_MFWeightSum_N 0x300000 -#define BIT_MASK_BB_MinIdxTH_N 0x7f000000 -#define BIT_MASK_BB_DAFormat_N 0x40000 -#define BIT_MASK_BB_TxChEmuEnable_N 0x01000000 -#define BIT_MASK_BB_TRSWIsolation_A_N 0x7f -#define BIT_MASK_BB_TRSWIsolation_B_N 0x7f00 -/* -#define BIT_MASK_BB_TRSWIsolation_C_N 0x7f0000 -#define BIT_MASK_BB_TRSWIsolation_D_N 0x7f000000 -*/ -#define BIT_MASK_BB_ExtLNAGain_N 0x7c00 - - -// -// 6. PageE(0xE00) -// -#define BIT_MASK_BB_STBCEN_N 0x4 // Useless -#define BIT_MASK_BB_ANTENNAMAPPING_N 0x10 -#define BIT_MASK_BB_NSS_N 0x20 -#define BIT_MASK_BB_CFOANTSUMD_N 0x200 -#define BIT_MASK_BB_OFDMDISPWSAVTX_N 0x400000 -#define BIT_MASK_BB_PHYCOUNTERRESET_N 0x8000000 -#define BIT_MASK_BB_CFOREPORTGET_N 0x4000000 -#define BIT_MASK_BB_OFDMCONTINUETX_N 0x10000000 -#define BIT_MASK_BB_OFDMSINGLECARRIER_N 0x20000000 -#define BIT_MASK_BB_OFDMSINGLETONE_N 0x40000000 -/* -#define bRxPath1 0x01 -#define bRxPath2 0x02 -#define bRxPath3 0x04 -#define bRxPath4 0x08 -#define bTxPath1 0x10 -#define bTxPath2 0x20 -*/ -#define BIT_MASK_BB_HTDETECT_N 0x100 -#define BIT_MASK_BB_CFOEN_N 0x10000 -#define BIT_MASK_BB_CFOVALUE_N 0xfff00000 -#define BIT_MASK_BB_SIGTONE_RE_N 0x3f -#define BIT_MASK_BB_SIGTONE_IM_N 0x7f00 -#define BIT_MASK_BB_COUNTER_CCA_N 0xffff -#define BIT_MASK_BB_COUNTER_PARITYFAIL_N 0xffff0000 -#define BIT_MASK_BB_COUNTER_RATEILLEGAL_N 0xffff -#define BIT_MASK_BB_COUNTER_CRC8FAIL_N 0xffff0000 -#define BIT_MASK_BB_COUNTER_MCSNOSUPPORT_N 0xffff -#define BIT_MASK_BB_COUNTER_FASTSYNC_N 0xffff -#define BIT_MASK_BB_SHORTCFO_N 0xfff -#define BIT_MASK_BB_SHORTCFOTLENGTH_N 12 //total -#define BIT_MASK_BB_SHORTCFOFLENGTH_N 11 //fraction -#define BIT_MASK_BB_LONGCFO_N 0x7ff -#define BIT_MASK_BB_LONGCFOTLENGTH_N 11 -#define BIT_MASK_BB_LONGCFOFLENGTH_N 11 -#define BIT_MASK_BB_TAILCFO_N 0x1fff -#define BIT_MASK_BB_TAILCFOTLENGTH_N 13 -#define BIT_MASK_BB_TAILCFOFLENGTH_N 12 -#define BIT_MASK_BB_MAX_EN_PWDB_N 0xffff -#define BIT_MASK_BB_CC_POWER_DB_N 0xffff0000 -#define BIT_MASK_BB_NOISE_PWDB_N 0xffff -#define BIT_MASK_BB_POWERMEASTLENGTH_N 10 -#define BIT_MASK_BB_POWERMEASFLENGTH_N 3 -#define BIT_MASK_BB_RX_HT_BW_N 0x1 -#define BIT_MASK_BB_RXSC_N 0x6 -#define BIT_MASK_BB_RX_HT_N 0x8 -#define BIT_MASK_BB_NB_INTF_DET_ON_N 0x1 -#define BIT_MASK_BB_INTF_WIN_LEN_CFG_N 0x30 -#define BIT_MASK_BB_NB_INTF_TH_CFG_N 0x1c0 -#define BIT_MASK_BB_RFGAIN_N 0x3f -#define BIT_MASK_BB_TABLESEL_N 0x40 -#define BIT_MASK_BB_TRSW_N 0x80 -#define BIT_MASK_BB_RXSNR_A_N 0xff -#define BIT_MASK_BB_RXSNR_B_N 0xff00 -/* -#define BIT_MASK_BB_RXSNR_C_N 0xff0000 -#define BIT_MASK_BB_RXSNR_D_N 0xff000000 -*/ -#define BIT_MASK_BB_SNREVMTLENGTH_N 8 -#define BIT_MASK_BB_SNREVMFLENGTH_N 1 -#define BIT_MASK_BB_CSI1ST_N 0xff -#define BIT_MASK_BB_CSI2ND_N 0xff00 -#define BIT_MASK_BB_RXEVM1ST_N 0xff0000 -#define BIT_MASK_BB_RXEVM2ND_N 0xff000000 -#define BIT_MASK_BB_SIGEVM_N 0xff -#define BIT_MASK_BB_PWDB_N 0xff00 -#define BIT_MASK_BB_SGIEN_N 0x10000 - -#define BIT_MASK_BB_SFACTORQAM1_N 0xf // Useless -#define BIT_MASK_BB_SFACTORQAM2_N 0xf0 -#define BIT_MASK_BB_SFACTORQAM3_N 0xf00 -#define BIT_MASK_BB_SFACTORQAM4_N 0xf000 -#define BIT_MASK_BB_SFACTORQAM5_N 0xf0000 -#define BIT_MASK_BB_SFACTORQAM6_N 0xf0000 -#define BIT_MASK_BB_SFACTORQAM7_N 0xf00000 -#define BIT_MASK_BB_SFACTORQAM8_N 0xf000000 -#define BIT_MASK_BB_SFACTORQAM9_N 0xf0000000 -#define BIT_MASK_BB_CSISCHEME_N 0x100000 - -#define BIT_MASK_BB_NOISELVLTOPSET_N 0x3 // Useless -#define BIT_MASK_BB_CHSMOOTH_N 0x4 -#define BIT_MASK_BB_CHSMOOTHCFG1_N 0x38 -#define BIT_MASK_BB_CHSMOOTHCFG2_N 0x1c0 -#define BIT_MASK_BB_CHSMOOTHCFG3_N 0xe00 -#define BIT_MASK_BB_CHSMOOTHCFG4_N 0x7000 -#define BIT_MASK_BB_MRCMODE_N 0x800000 -#define BIT_MASK_BB_THEVMCFG_N 0x7000000 - -#define BIT_MASK_BB_LOOPFITTYPE_N 0x1 // Useless -#define BIT_MASK_BB_UPDCFO_N 0x40 -#define BIT_MASK_BB_UPDCFOOFFDATA_N 0x80 -#define BIT_MASK_BB_ADVUPDCFO_N 0x100 -#define BIT_MASK_BB_ADVTIMECTRL_N 0x800 -#define BIT_MASK_BB_UPDCLKO_N 0x1000 -#define BIT_MASK_BB_FC_N 0x6000 -#define BIT_MASK_BB_TRACKINGMODE_N 0x8000 -#define BIT_MASK_BB_PHCMPENABLE_N 0x10000 -#define BIT_MASK_BB_UPDCLKOLTF_N 0x20000 -#define BIT_MASK_BB_COMCHCFO_N 0x40000 -#define BIT_MASK_BB_CSIESTIMODE_N 0x80000 -#define BIT_MASK_BB_ADVUPDEQZ_N 0x100000 -#define BIT_MASK_BB_UCHCFG_N 0x7000000 -#define BIT_MASK_BB_UPDEQZ_N 0x8000000 - -#define BIT_MASK_BB_TXAGCRATE18_06_N 0x7f7f7f7f // Useless -#define BIT_MASK_BB_TXAGCRATE54_24_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS32_N 0x7f -#define BIT_MASK_BB_TXAGCRATECCK_N 0x7f00 -#define BIT_MASK_BB_TXAGCRATEMCS3_MCS0_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS7_MCS4_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS11_MCS8_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS15_MCS12_N 0x7f7f7f7f - -//Rx Pseduo noise -#define BIT_MASK_BB_RXPESUDONOISEON_N 0x20000000 // Useless -#define BIT_MASK_BB_RXPESUDONOISE_A_N 0xff -#define BIT_MASK_BB_RXPESUDONOISE_B_N 0xff00 -/* -#define BIT_MASK_BB_RXPESUDONOISE_C_N 0xff0000 -#define BIT_MASK_BB_RXPESUDONOISE_D_N 0xff000000 -*/ -#define BIT_MASK_BB_PESUDONOISESTATE_A_N 0xffff -#define BIT_MASK_BB_PESUDONOISESTATE_B_N 0xffff0000 -/* -#define BIT_MASK_BB_PESUDONOISESTATE_C_N 0xffff -#define BIT_MASK_BB_PESUDONOISESTATE_D_N 0xffff0000 -*/ - - -// -//7. RF Register -// -//Zebra1 -#define BIT_MASK_RF_ZEBRA1_HSSIENABLE_N 0x8 // Useless -#define BIT_MASK_RF_ZEBRA1_TRXCONTROL_N 0xc00 -#define BIT_MASK_RF_ZEBRA1_TRXGAINSETTING_N 0x07f -#define BIT_MASK_RF_ZEBRA1_RXCORNER_N 0xc00 -#define BIT_MASK_RF_ZEBRA1_TXCHARGEPUMP_N 0x38 -#define BIT_MASK_RF_ZEBRA1_RXCHARGEPUMP_N 0x7 -#define BIT_MASK_RF_ZEBRA1_CHANNELNUM_N 0xf80 -#define BIT_MASK_RF_ZEBRA1_TXLPFBW_N 0x400 -#define BIT_MASK_RF_ZEBRA1_RXLPFBW_N 0x600 - -//Zebra4 -#define BIT_MASK_RF_RTL8256REGMODECTRL1_N 0x100 // Useless -#define BIT_MASK_RF_RTL8256REGMODECTRL0_N 0x40 -#define BIT_MASK_RF_RTL8256_TXLPFBW_N 0x18 -#define BIT_MASK_RF_RTL8256_RXLPFBW_N 0x600 - -//RTL8258 -#define BIT_MASK_RF_RTL8258_TXLPFBW_N 0xc // Useless -#define BIT_MASK_RF_RTL8258_RXLPFBW_N 0xc00 -#define BIT_MASK_RF_RTL8258_RSSILPFBW_N 0xc0 - - - -#endif //#if IS_RTL88XX_N - -// Other Common setting bit define - -//byte endable for sb_write -#define BIT_MASK_SET_BYTE0_COMMON 0x1 // Useless -#define BIT_MASK_SET_BYTE1_COMMON 0x2 -#define BIT_MASK_SET_BYTE2_COMMON 0x4 -#define BIT_MASK_SET_BYTE3_COMMON 0x8 -#define BIT_MASK_SET_WORD0_COMMON 0x3 -#define BIT_MASK_SET_WORD1_COMMON 0xc -#define BIT_MASK_SET_DWORD_COMMON 0xf - -//for PutRegsetting & GetRegSetting BitMask -#define BIT_MASK_SET_MASKBYTE0_COMMON 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f -#define BIT_MASK_SET_MASKBYTE1_COMMON 0xff00 -#define BIT_MASK_SET_MASKBYTE2_COMMON 0xff0000 -#define BIT_MASK_SET_MASKBYTE3_COMMON 0xff000000 -#define BIT_MASK_SET_MASKHWORD_COMMON 0xffff0000 -#define BIT_MASK_SET_MASKLWORD_COMMON 0x0000ffff -#define BIT_MASK_SET_MASKDWORD_COMMON 0xffffffff -#define BIT_MASK_SET_MASKH4BITS_COMMON 0xf0000000 -#define BIT_MASK_SET_MASKH3BYTES_COMMON 0xffffff00 -#define BIT_MASK_SET_MASKOFDM_D_COMMON 0xffc00000 -#define BIT_MASK_SET_MASKCCK_COMMON 0x3f3f3f3f - -//for PutRFRegsetting & GetRFRegSetting BitMask -#define BIT_MASK_SET_MASK12BITS_COMMON 0xfff // RF Reg mask bits -#define BIT_MASK_SET_MASK20BITS_COMMON 0xfffff // RF Reg mask bits T65 RF - - -#endif//__INC_HALCOMPHYBIT_H - - +#ifndef __INC_HALCOMPHYBIT_H +#define __INC_HALCOMPHYBIT_H + +/*-------------------------Modification Log----------------------------------- + +-------------------------Modification Log-----------------------------------*/ + +/*--------------------------Include File--------------------------------------*/ + +//3 ============Programming guide Start===================== +/* + BB BIT define rules + 1. For all bit define, it should be prefixed by "BIT_BB" + 2. For all bit mask, it should be prefixed by "BIT_MASK_BB" + 3. For all bit shift, it should be prefixed by "BIT_SHIFT_BB" + 4. For other case, prefix is not needed + + RF BIT define rules + 1. For all bit define, it should be prefixed by "BIT_RF" + 2. For all bit mask, it should be prefixed by "BIT_MASK_RF" + 3. For all bit shift, it should be prefixed by "BIT_SHIFT_RF" + 4. For other case, prefix is not needed + + SET BIT define rules + 1. Setting byte mask for BB or RF, it should be prefixed by "BIT_SET" + + Suffixed BIT define rules + 1. For AC chip, it should be suffixed by "_AC" + 2. For N chip, it should be suffixed by "_N" + 3. For Common bit define, it should be suffixed by "_COMMON" + +*/ +#if IS_RTL88XX_AC +/**** page 8 ****/ + +//REG_BB_RCCKENABLE_AC offset:0x808 +#define BIT_MASK_BB_BOFDMEN_AC 0x20000000 +#define BIT_MASK_BB_BCCKEN_AC 0x10000000 +#define BIT_MASK_BB_BRXPATH_AC 0xff + +//REG_BB_RTXPATH_AC offset:0x80c +#define BIT_MASK_BB_BTXPATH_AC 0x0fffffff + +//REG_BB_RAGC_TABLE_AC offset:0x82c // AGC tabel select +#define BIT_MASK_BB_BAGC_TABLE_AC 0x3 + +//REG_BB_CCAONSEC_AC offset:0x838 +#define BIT_MASK_BB_CCA_AC 0xf + +//REG_BB_REDCCA_AC offset:0x8a4 // EDCCA +#define BIT_MASK_BB_BEDCCA_AC 0xffff + +//REG_BB_RHSSIREAD_AC offset:0x8b0 // RF read addr +#define BIT_MASK_BB_BHSSIREAD_ADDR_AC 0xff + +/**** page 9 ****/ +//REG_BB_AGC_TABLE_AC_V2 0x958 +#define BIT_MASK_BB_BAGC_TABLE_AC_V2 0x0000001f + + +/**** page a ****/ +//REG_BB_RCCK_SYSTEM_AC offset: 0xa00 // for cck sideband +#define BIT_MASK_BB_BCCK_SYSTEM_AC 0x10 +//REG_BB_RCCK_RX_AC offset: 0xa04 // for cck rx path selection +#define BIT_MASK_BB_BCCK_RX_AC 0x0c000000 +//REG_BB_RCCK_CCA_AC offset: 0xa08 // cca threshold +#define BIT_MASK_BB_BCCK_CCA_AC 0x00ff0000 + +// REG_BB_RCCK_TXFILTER1_AC offset: 0xa20 +#define BIT_MASK_BB_BCCK_TXFILTER1_C0_AC 0x00ff0000 +#define BIT_MASK_BB_BCCK_TXFILTER1_C1_AC 0xff000000 +//REG_BB_RCCK_TXFILTER2_AC offset: 0xa24 +#define BIT_MASK_BB_BCCK_TXFILTER2_C2_AC 0x000000ff +#define BIT_MASK_BB_BCCK_TXFILTER2_C3_AC 0x0000ff00 +#define BIT_MASK_BB_BCCK_TXFILTER2_C4_AC 0x00ff0000 +#define BIT_MASK_BB_BCCK_TXFILTER2_C5_AC 0xff000000 +//REG_BB_RCCK_TXFILTER3_AC offset: 0xa28 +#define BIT_MASK_BB_BCCK_TXFILTER3_C6_AC 0x000000ff +#define BIT_MASK_BB_BCCK_TXFILTER3_C7_AC 0x0000ff00 +//REG_BB_RCCK_FALSEALARM_AC offset: 0xa5c // counter for cck false alarm +#define BIT_MASK_BB_B_FALSEALARM_AC 0xffff +/**** page b ****/ +/**** page c ****/ +//REG_BB_AGC_TABLE_AC_V1 0xc1c +#define BIT_MASK_BB_BAGC_TABLE_AC_V1 0x00000f00 +//REG_BB_A_LSSIWRITE_AC offset :0xc90 +#define BIT_MASK_BB_LSSIWRITE_AC 0xf0000000 +/**** page d ****/ +/**** page e ****/ + + +#endif //#if IS_RTL88XX_AC + + +#if IS_RTL88XX_N + +// +// 2. Page8(0x800) +// +#define BIT_MASK_BB_RFMOD_N_N 0x1 // Reg 0x800 rFPGA0_RFMOD +#define BIT_MASK_BB_JAPANMODE_N 0x2 +#define BIT_MASK_BB_CCKTXSC_N 0x30 +#define BIT_MASK_BB_CCKEN_N 0x1000000 +#define BIT_MASK_BB_OFDMEN_N 0x2000000 +#define BIT_MASK_BB_OFDMRXADCPHASE_N 0x10000 // Useless now +#define BIT_MASK_BB_OFDMTXDACPHASE_N 0x40000 + +#define BIT_MASK_BB_XATXAGC_N 0x3f +#define BIT_MASK_BB_XBTXAGC_N 0xf00 // Reg 80c rFPGA0_TxGainStage +/* +#define BIT_MASK_BB_XCTXAGC_N 0xf000 +#define BIT_MASK_BB_XDTXAGC_N 0xf0000 +*/ + +#define BIT_MASK_BB_PASTART_N 0xf0000000 // Useless now +#define BIT_MASK_BB_TRSTART_N 0x00f00000 +#define BIT_MASK_BB_RFSTART_N 0x0000f000 +#define BIT_MASK_BB_BBSTART_N 0x000000f0 +#define BIT_MASK_BB_BBCCKSTART_N 0x0000000f +#define BIT_MASK_BB_PAEND_N 0xf //Reg0x814 +#define BIT_MASK_BB_TREND_N 0x0f000000 +#define BIT_MASK_BB_RFEND_N 0x000f0000 +#define BIT_MASK_BB_CCAMASK_N 0x000000f0 //T2R +#define BIT_MASK_BB_R2RCCAMASK_N 0x00000f00 +#define BIT_MASK_BB_HSSI_R2TDELAY_N 0xf8000000 +#define BIT_MASK_BB_HSSI_T2RDELAY_N 0xf80000 +#define BIT_MASK_BB_CONTTXHSSI_N 0x400 //chane gain at continue Tx +#define BIT_MASK_BB_IGFROMCCK_N 0x200 +#define BIT_MASK_BB_AGCADDRESS_N 0x3f +#define BIT_MASK_BB_RXHPTX_N 0x7000 +#define BIT_MASK_BB_RXHPT2R_N 0x38000 +#define BIT_MASK_BB_RXHPCCKINI_N 0xc0000 +#define BIT_MASK_BB_AGCTXCODE_N 0xc00000 +#define BIT_MASK_BB_AGCRXCODE_N 0x300000 + +#define BIT_MASK_BB_3WIREDATALENGTH_N 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define BIT_MASK_BB_3WIREADDRESSLENGTH_N 0x400 + +#define BIT_MASK_BB_3WIRERFPOWERDOWN_N 0x1 // Useless now +#define BIT_MASK_BB_5GPAPEPOLARITY_N 0x40000000 +#define BIT_MASK_BB_2GPAPEPOLARITY_N 0x80000000 +#define BIT_MASK_BB_RFSW_TXDEFAULTANT_N 0x3 +#define BIT_MASK_BB_RFSW_TXOPTIONANT_N 0x30 +#define BIT_MASK_BB_RFSW_RXDEFAULTANT_N 0x300 +#define BIT_MASK_BB_RFSW_RXOPTIONANT_N 0x3000 +#define BIT_MASK_BB_RFSI_3WIREDATA_N 0x1 +#define BIT_MASK_BB_RFSI_3WIRECLOCK_N 0x2 +#define BIT_MASK_BB_RFSI_3WIRELOAD_N 0x4 +#define BIT_MASK_BB_RFSI_3WIRERW_N 0x8 +#define BIT_MASK_BB_RFSI_3WIRE_N 0xf + +#define BIT_MASK_BB_RFSI_RFENV_N 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW +#define BIT_MASK_BB_RFSI_TRSW_N 0x20 // Useless now +#define BIT_MASK_BB_RFSI_TRSWB_N 0x40 +#define BIT_MASK_BB_RFSI_ANTSW_N 0x100 +#define BIT_MASK_BB_RFSI_ANTSWB_N 0x200 +#define BIT_MASK_BB_RFSI_PAPE_N 0x400 +#define BIT_MASK_BB_RFSI_PAPE5G_N 0x800 +#define BIT_MASK_BB_BANDSELECT_N 0x1 +#define BIT_MASK_BB_HTSIG2_GI_N 0x80 +#define BIT_MASK_BB_HTSIG2_SMOOTHING_N 0x01 +#define BIT_MASK_BB_HTSIG2_SOUNDING_N 0x02 +#define BIT_MASK_BB_HTSIG2_AGGREATON_N 0x08 +#define BIT_MASK_BB_HTSIG2_STBC_N 0x30 +#define BIT_MASK_BB_HTSIG2_ADVCODING_N 0x40 +#define BIT_MASK_BB_HTSIG2_NUMOFHTLTF_N 0x300 +#define BIT_MASK_BB_HTSIG2_CRC8_N 0x3fc +#define BIT_MASK_BB_HTSIG1_MCS_N 0x7f +#define BIT_MASK_BB_HTSIG1_BANDWIDTH_N 0x80 +#define BIT_MASK_BB_HTSIG1_HTLENGTH_N 0xffff +#define BIT_MASK_BB_LSIG_RATE_N 0xf +#define BIT_MASK_BB_LSIG_RESERVED_N 0x10 +#define BIT_MASK_BB_LSIG_LENGTH_N 0x1fffe +#define BIT_MASK_BB_LSIG_PARITY_N 0x20 +#define BIT_MASK_BB_CCKRXPHASE_N 0x4 + +//#define BIT_MASK_BB_LSSIREADADDRESS 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 +#define BIT_MASK_BB_LSSIREADADDRESS_N 0x7f800000 // T65 RF +#define BIT_MASK_BB_LSSIREADEDGE_N 0x80000000 //LSSI "Read" edge signal + +//#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack +#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfffff // T65 RF + +#define BIT_MASK_BB_LSSIREADOKFLAG_N 0x1000 // Useless now +#define BIT_MASK_BB_CCKSAMPLERATE_N 0x8 //0: 44MHz, 1:88MHz +#define BIT_MASK_BB_REGULATOR0STANDBY_N 0x1 +#define BIT_MASK_BB_REGULATORPLLSTANDBY_N 0x2 +#define BIT_MASK_BB_REGULATOR1STANDBY_N 0x4 +#define BIT_MASK_BB_PLLPOWERUP_N 0x8 +#define BIT_MASK_BB_DPLLPOWERUP_N 0x10 +#define BIT_MASK_BB_DA10POWERUP_N 0x20 +#define BIT_MASK_BB_AD7POWERUP_N 0x200 +#define BIT_MASK_BB_DA6POWERUP_N 0x2000 +#define BIT_MASK_BB_XTALPOWERUP_N 0x4000 +#define BIT_MASK_BB_40MDCLKPOWERUP_N 0x8000 +#define BIT_MASK_BB_DA6DEBUGMODE_N 0x20000 +#define BIT_MASK_BB_DA6SWING_N 0x380000 + +#define BIT_MASK_BB_ADCLKPHASE_N 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define BIT_MASK_BB_80MCLKDELAY_N 0x18000000 // Useless +#define BIT_MASK_BB_AFEWATCHDOGENABLE_N 0x20000000 + +#define BIT_MASK_BB_XTALCAP01_N 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define BIT_MASK_BB_XTALCAP23_N 0x3 +#define BIT_MASK_BB_XTALCAP92X_N 0x0f000000 + +#define BIT_MASK_BB_INTDIFCLKENABLE_N 0x400 // Useless +#define BIT_MASK_BB_EXTSIGCLKENABLE_N 0x800 +#define BIT_MASK_BB_BANDGAPMBIASPOWERUP_N 0x10000 +#define BIT_MASK_BB_AD11SHGAIN_N 0xc0000 +#define BIT_MASK_BB_AD11INPUTRANGE_N 0x700000 +#define BIT_MASK_BB_AD11OPCURRENT_N 0x3800000 +#define BIT_MASK_BB_IPATHLOOPBACK_N 0x4000000 +#define BIT_MASK_BB_QPATHLOOPBACK_N 0x8000000 +#define BIT_MASK_BB_AFELOOPBACK_N 0x10000000 +#define BIT_MASK_BB_DA10SWING_N 0x7e0 +#define BIT_MASK_BB_DA10REVERSE_N 0x800 +#define BIT_MASK_BB_DACLKSOURCE_N 0x1000 +#define BIT_MASK_BB_AD7INPUTRANGE_N 0x6000 +#define BIT_MASK_BB_AD7GAIN_N 0x38000 +#define BIT_MASK_BB_AD7OUTPUTCMMODE_N 0x40000 +#define BIT_MASK_BB_AD7INPUTCMMODE_N 0x380000 +#define BIT_MASK_BB_AD7CURRENT_N 0xc00000 +#define BIT_MASK_BB_REGULATORADJUST_N 0x7000000 +#define BIT_MASK_BB_AD11POWERUPATTX_N 0x1 +#define BIT_MASK_BB_DA10PSATTX_N 0x10 +#define BIT_MASK_BB_AD11POWERUPATRX_N 0x100 +#define BIT_MASK_BB_DA10PSATRX_N 0x1000 +#define BIT_MASK_BB_CCKRXAGCFORMAT_N 0x200 +#define BIT_MASK_BB_PSDFFTSAMPLEPPOINT_N 0xc000 +#define BIT_MASK_BB_PSDAVERAGENUM_N 0x3000 +#define BIT_MASK_BB_IQPATHCONTROL_N 0xc00 +#define BIT_MASK_BB_PSDFREQ_N 0x3ff +#define BIT_MASK_BB_PSDANTENNAPATH_N 0x30 +#define BIT_MASK_BB_PSDIQSWITCH_N 0x40 +#define BIT_MASK_BB_PSDRXTRIGGER_N 0x400000 +#define BIT_MASK_BB_PSDTXTRIGGER_N 0x80000000 +#define BIT_MASK_BB_PSDSINETONESCALE_N 0x7f000000 +#define BIT_MASK_BB_PSDREPORT_N 0xffff + + +// +// 3. Page9(0x900) +// +#define BIT_MASK_BB_OFDMTXSC_N 0x30000000 // Useless +#define BIT_MASK_BB_CCKTXON_N 0x1 +#define BIT_MASK_BB_OFDMTXON_N 0x2 +#define BIT_MASK_BB_DEBUGPAGE_N 0xfff //reset debug page and also HWord, LWord +#define BIT_MASK_BB_DEBUGITEM_N 0xff //reset debug page and LWord +#define BIT_MASK_BB_ANTL_N 0x10 +#define BIT_MASK_BB_ANTNONHT_N 0x100 +#define BIT_MASK_BB_ANTHT1_N 0x1000 +#define BIT_MASK_BB_ANTHT2_N 0x10000 +#define BIT_MASK_BB_ANTHT1S1_N 0x100000 +#define BIT_MASK_BB_ANTNONHTS1_N 0x1000000 + + +// +// 4. PageA(0xA00) +// +#define BIT_MASK_BB_CCKBBMODE_N 0x3 // Useless +#define BIT_MASK_BB_CCKTXPOWERSAVING_N 0x80 +#define BIT_MASK_BB_CCKRXPOWERSAVING_N 0x40 +#define BIT_MASK_BB_CCKSIDEBAND_N 0x10 // Reg 0xa00 rCCK0_System 20/40 switch +#define BIT_MASK_BB_CCKSCRAMBLE_N 0x8 // Useless +#define BIT_MASK_BB_CCKANTDIVERSITY_N 0x8000 +#define BIT_MASK_BB_CCKCARRIERRECOVERY_N 0x4000 +#define BIT_MASK_BB_CCKTXRATE_N 0x3000 +#define BIT_MASK_BB_CCKDCCANCEL_N 0x0800 +#define BIT_MASK_BB_CCKISICANCEL_N 0x0400 +#define BIT_MASK_BB_CCKMATCHFILTER_N 0x0200 +#define BIT_MASK_BB_CCKEQUALIZER_N 0x0100 +#define BIT_MASK_BB_CCKPREAMBLEDETECT_N 0x800000 +#define BIT_MASK_BB_CCKFASTFALSECCA_N 0x400000 +#define BIT_MASK_BB_CCKCHESTSTART_N 0x300000 +#define BIT_MASK_BB_CCKCCACOUNT_N 0x080000 +#define BIT_MASK_BB_CCKCS_LIM_N 0x070000 +#define BIT_MASK_BB_CCKBISTMODE_N 0x80000000 +#define BIT_MASK_BB_CCKCCAMASK_N 0x40000000 +#define BIT_MASK_BB_CCKTXDACPHASE_N 0x4 +#define BIT_MASK_BB_CCKRXADCPHASE_N 0x20000000 //r_rx_clk +#define BIT_MASK_BB_CCKR_CP_MODE0_N 0x0100 +#define BIT_MASK_BB_CCKTXDCOFFSET_N 0xf0 +#define BIT_MASK_BB_CCKRXDCOFFSET_N 0xf +#define BIT_MASK_BB_CCKCCAMODE_N 0xc000 +#define BIT_MASK_BB_CCKFALSECS_LIM_N 0x3f00 +#define BIT_MASK_BB_CCKCS_RATIO_N 0xc00000 +#define BIT_MASK_BB_CCKCORGBIT_SEL_N 0x300000 +#define BIT_MASK_BB_CCKPD_LIM_N 0x0f0000 +#define BIT_MASK_BB_CCKNEWCCA_N 0x80000000 +#define BIT_MASK_BB_CCKRXHPOFIG_N 0x8000 +#define BIT_MASK_BB_CCKRXIG_N 0x7f00 +#define BIT_MASK_BB_CCKLNAPOLARITY_N 0x800000 +#define BIT_MASK_BB_CCKRX1STGAIN_N 0x7f0000 +#define BIT_MASK_BB_CCKRFEXTEND_N 0x20000000 //CCK Rx Iinital gain polarity +#define BIT_MASK_BB_CCKRXAGCSATLEVEL_N 0x1f000000 +#define BIT_MASK_BB_CCKRXAGCSATCOUNT_N 0xe0 +#define BIT_MASK_BB_CCKRXRFSETTLE_N 0x1f //AGCsamp_dly +#define BIT_MASK_BB_CCKFIXEDRXAGC_N 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define BIT_MASK_BB_CCKANTENNAPOLARITY_N 0x2000 +#define BIT_MASK_BB_CCKTXFILTERTYPE_N 0x0c00 +#define BIT_MASK_BB_CCKRXAGCREPORTTYPE_N 0x0300 +#define BIT_MASK_BB_CCKRXDAGCEN_N 0x80000000 +#define BIT_MASK_BB_CCKRXDAGCPERIOD_N 0x20000000 +#define BIT_MASK_BB_CCKRXDAGCSATLEVEL_N 0x1f000000 +#define BIT_MASK_BB_CCKTIMINGRECOVERY_N 0x800000 +#define BIT_MASK_BB_CCKTXC0_N 0x3f0000 +#define BIT_MASK_BB_CCKTXC1_N 0x3f000000 +#define BIT_MASK_BB_CCKTXC2_N 0x3f +#define BIT_MASK_BB_CCKTXC3_N 0x3f00 +#define BIT_MASK_BB_CCKTXC4_N 0x3f0000 +#define BIT_MASK_BB_CCKTXC5_N 0x3f000000 +#define BIT_MASK_BB_CCKTXC6_N 0x3f +#define BIT_MASK_BB_CCKTXC7_N 0x3f00 +#define BIT_MASK_BB_CCKDEBUGPORT_N 0xff0000 +#define BIT_MASK_BB_CCKDACDEBUG_N 0x0f000000 +#define BIT_MASK_BB_CCKFALSEALARMENABLE_N 0x8000 +#define BIT_MASK_BB_CCKFALSEALARMREAD_N 0x4000 +#define BIT_MASK_BB_CCKTRSSI_N 0x7f +#define BIT_MASK_BB_CCKRXAGCREPORT_N 0xfe +#define BIT_MASK_BB_CCKRXREPORT_ANTSEL_N 0x80000000 +#define BIT_MASK_BB_CCKRXREPORT_MFOFF_N 0x40000000 +#define BIT_MASK_BB_CCKRXRXREPORT_SQLOSS_N 0x20000000 +#define BIT_MASK_BB_CCKRXREPORT_PKTLOSS_N 0x10000000 +#define BIT_MASK_BB_CCKRXREPORT_LOCKEDBIT_N 0x08000000 +#define BIT_MASK_BB_CCKRXREPORT_RATEERROR_N 0x04000000 +#define BIT_MASK_BB_CCKRXREPORT_RXRATE_N 0x03000000 +#define BIT_MASK_BB_CCKRXFACOUNTERLOWER_N 0xff +#define BIT_MASK_BB_CCKRXFACOUNTERUPPER_N 0xff000000 +#define BIT_MASK_BB_CCKRXHPAGCSTART_N 0xe000 +#define BIT_MASK_BB_CCKRXHPAGCFINAL_N 0x1c00 +#define BIT_MASK_BB_CCKRXFALSEALARMENABLE_N 0x8000 +#define BIT_MASK_BB_CCKFACOUNTERFREEZE_N 0x4000 +#define BIT_MASK_BB_CCKTXPATHSEL_N 0x10000000 +#define BIT_MASK_BB_CCKDEFAULTRXPATH_N 0xc000000 +#define BIT_MASK_BB_CCKOPTIONRXPATH_N 0x3000000 + + +// +// 5. PageC(0xC00) +// +#define BIT_MASK_BB_NUMOFSTF_N 0x3 // Useless +#define BIT_MASK_BB_SHIFT_L_N 0xc0 +#define BIT_MASK_BB_GI_TH_N 0xc +#define BIT_MASK_BB_RXPATHA_N 0x1 +#define BIT_MASK_BB_RXPATHB_N 0x2 +#define BIT_MASK_BB_RXPATHC_N 0x4 +#define BIT_MASK_BB_RXPATHD_N 0x8 +#define BIT_MASK_BB_TXPATHA_N 0x1 +#define BIT_MASK_BB_TXPATHB_N 0x2 +#define BIT_MASK_BB_TXPATHC_N 0x4 +#define BIT_MASK_BB_TXPATHD_N 0x8 +#define BIT_MASK_BB_TRSSIFREQ_N 0x200 +#define BIT_MASK_BB_ADCBACKOFF_N 0x3000 +#define BIT_MASK_BB_DFIRBACKOFF_N 0xc000 +#define BIT_MASK_BB_TRSSILATCHPHASE_N 0x10000 +#define BIT_MASK_BB_RXIDCOFFSET_N 0xff +#define BIT_MASK_BB_RXQDCOFFSET_N 0xff00 +#define BIT_MASK_BB_RXDFIRMODE_N 0x1800000 +#define BIT_MASK_BB_RXDCNFTYPE_N 0xe000000 +#define BIT_MASK_BB_RXIQIMB_A_N 0x3ff +#define BIT_MASK_BB_RXIQIMB_B_N 0xfc00 +#define BIT_MASK_BB_RXIQIMB_C_N 0x3f0000 +#define BIT_MASK_BB_RXIQIMB_D_N 0xffc00000 +#define BIT_MASK_BB_DC_DC_NOTCH_N 0x60000 +#define BIT_MASK_BB_RXNBINOTCH_N 0x1f000000 +#define BIT_MASK_BB_PD_TH_N 0xf +#define BIT_MASK_BB_PD_TH_OPT2_N 0xc000 +#define BIT_MASK_BB_PWED_TH_N 0x700 +#define BIT_MASK_BB_IFMF_WIN_L_N 0x800 +#define BIT_MASK_BB_PD_OPTION_N 0x1000 +#define BIT_MASK_BB_MF_WIN_L_N 0xe000 +#define BIT_MASK_BB_BW_SEARCH_L_N 0x30000 +#define BIT_MASK_BB_WIN_ENH_L_N 0xc0000 +#define BIT_MASK_BB_BW_TH_N 0x700000 +#define BIT_MASK_BB_ED_TH2_N 0x3800000 +#define BIT_MASK_BB_BW_OPTION_N 0x4000000 +#define BIT_MASK_BB_RATIO_TH_N 0x18000000 +#define BIT_MASK_BB_WINDOW_L_N 0xe0000000 +#define BIT_MASK_BB_SBD_OPTION_N 0x1 +#define BIT_MASK_BB_FRAME_TH_N 0x1c +#define BIT_MASK_BB_FS_OPTION_N 0x60 +#define BIT_MASK_BB_DC_SLOPE_CHECK_N 0x80 +#define BIT_MASK_BB_FGUARD_COUNTER_DC_L_N 0xe00 +#define BIT_MASK_BB_FRAME_WEIGHT_SHORT_N 0x7000 +#define BIT_MASK_BB_SUB_TUNE_N 0xe00000 +#define BIT_MASK_BB_FRAME_DC_LENGTH_N 0xe000000 +#define BIT_MASK_BB_SBD_START_OFFSET_N 0x30000000 +#define BIT_MASK_BB_FRAME_TH_2_N 0x7 +#define BIT_MASK_BB_FRAME_GI2_TH_N 0x38 +#define BIT_MASK_BB_GI2_SYNC_EN_N 0x40 +#define BIT_MASK_BB_SARCH_SHORT_EARLY_N 0x300 +#define BIT_MASK_BB_SARCH_SHORT_LATE_N 0xc00 +#define BIT_MASK_BB_SARCH_GI2_LATE_N 0x70000 +#define BIT_MASK_BB_CFOANTSUM_N 0x1 +#define BIT_MASK_BB_CFOACC_N 0x2 +#define BIT_MASK_BB_CFOSTARTOFFSET_N 0xc +#define BIT_MASK_BB_CFOLOOKBACK_N 0x70 +#define BIT_MASK_BB_CFOSUMWEIGHT_N 0x80 +#define BIT_MASK_BB_DAGCENABLE_N 0x10000 +#define BIT_MASK_BB_TXIQIMB_A_N 0x3ff +#define BIT_MASK_BB_TXIQIMB_B_N 0xfc00 +#define BIT_MASK_BB_TXIQIMB_C_N 0x3f0000 +#define BIT_MASK_BB_TXIQIMB_D_N 0xffc00000 +#define BIT_MASK_BB_TXIDCOFFSET_N 0xff +#define BIT_MASK_BB_TXQDCOFFSET_N 0xff00 +#define BIT_MASK_BB_TXDFIRMODE_N 0x10000 +#define BIT_MASK_BB_TXPESUDONOISEON_N 0x4000000 +#define BIT_MASK_BB_TXPESUDONOISE_A_N 0xff +#define BIT_MASK_BB_TXPESUDONOISE_B_N 0xff00 +#define BIT_MASK_BB_TXPESUDONOISE_C_N 0xff0000 +#define BIT_MASK_BB_TXPESUDONOISE_D_N 0xff000000 +#define BIT_MASK_BB_CCADROPOPTION_N 0x20000 +#define BIT_MASK_BB_CCADROPTHRES_N 0xfff00000 +#define BIT_MASK_BB_EDCCA_H_N 0xf +#define BIT_MASK_BB_EDCCA_L_N 0xf0 +#define BIT_MASK_BB_LAMBDA_ED_N 0x300 +#define BIT_MASK_BB_RXINITIALGAIN_N 0x7f +#define BIT_MASK_BB_RXANTDIVEN_N 0x80 +#define BIT_MASK_BB_RXAGCADDRESSFORLNA_N 0x7f00 +#define BIT_MASK_BB_RXHIGHPOWERFLOW_N 0x8000 +#define BIT_MASK_BB_RXAGCFREEZETHRES_N 0xc0000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC1_N 0x300000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC2_N 0xc00000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC3_N 0x3000000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC0_N 0xc000000 +#define BIT_MASK_BB_RXRSSI_CMP_EN_N 0x10000000 +#define BIT_MASK_BB_RXQUICKAGCEN_N 0x20000000 +#define BIT_MASK_BB_RXAGCFREEZETHRESMODE_N 0x40000000 +#define BIT_MASK_BB_RXOVERFLOWCHECKTYPE_N 0x80000000 +#define BIT_MASK_BB_RXAGCSHIFT_N 0x7f +#define BIT_MASK_BB_TRSW_TRI_ONLY_N 0x80 +#define BIT_MASK_BB_POWERTHRES_N 0x300 +#define BIT_MASK_BB_RXAGCEN_N 0x1 +#define BIT_MASK_BB_RXAGCTOGETHEREN_N 0x2 +#define BIT_MASK_BB_RXAGCMIN_N 0x4 +#define BIT_MASK_BB_RXHP_INI_N 0x7 +#define BIT_MASK_BB_RXHP_TRLNA_N 0x70 +#define BIT_MASK_BB_RXHP_RSSI_N 0x700 +#define BIT_MASK_BB_RXHP_BBP1_N 0x7000 +#define BIT_MASK_BB_RXHP_BBP2_N 0x70000 +#define BIT_MASK_BB_RXHP_BBP3_N 0x700000 +#define BIT_MASK_BB_RSSI_H_N 0x7f0000 //the threshold for high power +#define BIT_MASK_BB_RSSI_GEN_N 0x7f000000 //the threshold for ant diversity +#define BIT_MASK_BB_RXSETTLE_TRSW_N 0x7 +#define BIT_MASK_BB_RXSETTLE_LNA_N 0x38 +#define BIT_MASK_BB_RXSETTLE_RSSI_N 0x1c0 +#define BIT_MASK_BB_RXSETTLE_BBP_N 0xe00 +#define BIT_MASK_BB_RXSETTLE_RXHP_N 0x7000 +#define BIT_MASK_BB_RXSETTLE_ANTSW_RSSI_N 0x38000 +#define BIT_MASK_BB_RXSETTLE_ANTSW_N 0xc0000 +#define BIT_MASK_BB_RXPROCESSTIME_DAGC_N 0x300000 +#define BIT_MASK_BB_RXSETTLE_HSSI_N 0x400000 +#define BIT_MASK_BB_RXPROCESSTIME_BBPPW_N 0x800000 +#define BIT_MASK_BB_RXANTENNAPOWERSHIFT_N 0x3000000 +#define BIT_MASK_BB_RSSITABLESELECT_N 0xc000000 +#define BIT_MASK_BB_RXHP_FINAL_N 0x7000000 +#define BIT_MASK_BB_RXHTSETTLE_BBP_N 0x7 +#define BIT_MASK_BB_RXHTSETTLE_HSSI_N 0x8 +#define BIT_MASK_BB_RXHTSETTLE_RXHP_N 0x70 +#define BIT_MASK_BB_RXHTSETTLE_BBPPW_N 0x80 +#define BIT_MASK_BB_RXHTSETTLE_IDLE_N 0x300 +#define BIT_MASK_BB_RXHTSETTLE_RESERVED_N 0x1c00 +#define BIT_MASK_BB_RXHTRXHPEN_N 0x8000 +#define BIT_MASK_BB_RXHTAGCFREEZETHRES_N 0x30000 +#define BIT_MASK_BB_RXHTAGCTOGETHEREN_N 0x40000 +#define BIT_MASK_BB_RXHTAGCMIN_N 0x80000 +#define BIT_MASK_BB_RXHTAGCEN_N 0x100000 +#define BIT_MASK_BB_RXHTDAGCEN_N 0x200000 +#define BIT_MASK_BB_RXHTRXHP_BBP_N 0x1c00000 +#define BIT_MASK_BB_RXHTRXHP_FINAL_N 0xe0000000 +#define BIT_MASK_BB_RXPWRATIOTH_N 0x3 +#define BIT_MASK_BB_RXPWRATIOEN_N 0x4 +#define BIT_MASK_BB_RXMFHOLD_N 0x3800 +#define BIT_MASK_BB_RXPD_DELAY_TH1_N 0x38 +#define BIT_MASK_BB_RXPD_DELAY_TH2_N 0x1c0 +#define BIT_MASK_BB_RXPD_DC_COUNT_MAX_N 0x600 +//#define bRxMF_Hold 0x3800 +#define BIT_MASK_BB_RxPD_Delay_TH_N 0x8000 +#define BIT_MASK_BB_RxProcess_Delay_N 0xf0000 +#define BIT_MASK_BB_RxSearchrange_GI2_Early_N 0x700000 +#define BIT_MASK_BB_RxFrame_Guard_Counter_L_N 0x3800000 +#define BIT_MASK_BB_RxSGI_Guard_L_N 0xc000000 +#define BIT_MASK_BB_RxSGI_Search_L_N 0x30000000 +#define BIT_MASK_BB_RxSGI_TH_N 0xc0000000 +#define BIT_MASK_BB_DFSCnt0_N 0xff +#define BIT_MASK_BB_DFSCnt1_N 0xff00 +#define BIT_MASK_BB_DFSFlag_N 0xf0000 +#define BIT_MASK_BB_MFWeightSum_N 0x300000 +#define BIT_MASK_BB_MinIdxTH_N 0x7f000000 +#define BIT_MASK_BB_DAFormat_N 0x40000 +#define BIT_MASK_BB_TxChEmuEnable_N 0x01000000 +#define BIT_MASK_BB_TRSWIsolation_A_N 0x7f +#define BIT_MASK_BB_TRSWIsolation_B_N 0x7f00 +/* +#define BIT_MASK_BB_TRSWIsolation_C_N 0x7f0000 +#define BIT_MASK_BB_TRSWIsolation_D_N 0x7f000000 +*/ +#define BIT_MASK_BB_ExtLNAGain_N 0x7c00 + + +// +// 6. PageE(0xE00) +// +#define BIT_MASK_BB_STBCEN_N 0x4 // Useless +#define BIT_MASK_BB_ANTENNAMAPPING_N 0x10 +#define BIT_MASK_BB_NSS_N 0x20 +#define BIT_MASK_BB_CFOANTSUMD_N 0x200 +#define BIT_MASK_BB_OFDMDISPWSAVTX_N 0x400000 +#define BIT_MASK_BB_PHYCOUNTERRESET_N 0x8000000 +#define BIT_MASK_BB_CFOREPORTGET_N 0x4000000 +#define BIT_MASK_BB_OFDMCONTINUETX_N 0x10000000 +#define BIT_MASK_BB_OFDMSINGLECARRIER_N 0x20000000 +#define BIT_MASK_BB_OFDMSINGLETONE_N 0x40000000 +/* +#define bRxPath1 0x01 +#define bRxPath2 0x02 +#define bRxPath3 0x04 +#define bRxPath4 0x08 +#define bTxPath1 0x10 +#define bTxPath2 0x20 +*/ +#define BIT_MASK_BB_HTDETECT_N 0x100 +#define BIT_MASK_BB_CFOEN_N 0x10000 +#define BIT_MASK_BB_CFOVALUE_N 0xfff00000 +#define BIT_MASK_BB_SIGTONE_RE_N 0x3f +#define BIT_MASK_BB_SIGTONE_IM_N 0x7f00 +#define BIT_MASK_BB_COUNTER_CCA_N 0xffff +#define BIT_MASK_BB_COUNTER_PARITYFAIL_N 0xffff0000 +#define BIT_MASK_BB_COUNTER_RATEILLEGAL_N 0xffff +#define BIT_MASK_BB_COUNTER_CRC8FAIL_N 0xffff0000 +#define BIT_MASK_BB_COUNTER_MCSNOSUPPORT_N 0xffff +#define BIT_MASK_BB_COUNTER_FASTSYNC_N 0xffff +#define BIT_MASK_BB_SHORTCFO_N 0xfff +#define BIT_MASK_BB_SHORTCFOTLENGTH_N 12 //total +#define BIT_MASK_BB_SHORTCFOFLENGTH_N 11 //fraction +#define BIT_MASK_BB_LONGCFO_N 0x7ff +#define BIT_MASK_BB_LONGCFOTLENGTH_N 11 +#define BIT_MASK_BB_LONGCFOFLENGTH_N 11 +#define BIT_MASK_BB_TAILCFO_N 0x1fff +#define BIT_MASK_BB_TAILCFOTLENGTH_N 13 +#define BIT_MASK_BB_TAILCFOFLENGTH_N 12 +#define BIT_MASK_BB_MAX_EN_PWDB_N 0xffff +#define BIT_MASK_BB_CC_POWER_DB_N 0xffff0000 +#define BIT_MASK_BB_NOISE_PWDB_N 0xffff +#define BIT_MASK_BB_POWERMEASTLENGTH_N 10 +#define BIT_MASK_BB_POWERMEASFLENGTH_N 3 +#define BIT_MASK_BB_RX_HT_BW_N 0x1 +#define BIT_MASK_BB_RXSC_N 0x6 +#define BIT_MASK_BB_RX_HT_N 0x8 +#define BIT_MASK_BB_NB_INTF_DET_ON_N 0x1 +#define BIT_MASK_BB_INTF_WIN_LEN_CFG_N 0x30 +#define BIT_MASK_BB_NB_INTF_TH_CFG_N 0x1c0 +#define BIT_MASK_BB_RFGAIN_N 0x3f +#define BIT_MASK_BB_TABLESEL_N 0x40 +#define BIT_MASK_BB_TRSW_N 0x80 +#define BIT_MASK_BB_RXSNR_A_N 0xff +#define BIT_MASK_BB_RXSNR_B_N 0xff00 +/* +#define BIT_MASK_BB_RXSNR_C_N 0xff0000 +#define BIT_MASK_BB_RXSNR_D_N 0xff000000 +*/ +#define BIT_MASK_BB_SNREVMTLENGTH_N 8 +#define BIT_MASK_BB_SNREVMFLENGTH_N 1 +#define BIT_MASK_BB_CSI1ST_N 0xff +#define BIT_MASK_BB_CSI2ND_N 0xff00 +#define BIT_MASK_BB_RXEVM1ST_N 0xff0000 +#define BIT_MASK_BB_RXEVM2ND_N 0xff000000 +#define BIT_MASK_BB_SIGEVM_N 0xff +#define BIT_MASK_BB_PWDB_N 0xff00 +#define BIT_MASK_BB_SGIEN_N 0x10000 + +#define BIT_MASK_BB_SFACTORQAM1_N 0xf // Useless +#define BIT_MASK_BB_SFACTORQAM2_N 0xf0 +#define BIT_MASK_BB_SFACTORQAM3_N 0xf00 +#define BIT_MASK_BB_SFACTORQAM4_N 0xf000 +#define BIT_MASK_BB_SFACTORQAM5_N 0xf0000 +#define BIT_MASK_BB_SFACTORQAM6_N 0xf0000 +#define BIT_MASK_BB_SFACTORQAM7_N 0xf00000 +#define BIT_MASK_BB_SFACTORQAM8_N 0xf000000 +#define BIT_MASK_BB_SFACTORQAM9_N 0xf0000000 +#define BIT_MASK_BB_CSISCHEME_N 0x100000 + +#define BIT_MASK_BB_NOISELVLTOPSET_N 0x3 // Useless +#define BIT_MASK_BB_CHSMOOTH_N 0x4 +#define BIT_MASK_BB_CHSMOOTHCFG1_N 0x38 +#define BIT_MASK_BB_CHSMOOTHCFG2_N 0x1c0 +#define BIT_MASK_BB_CHSMOOTHCFG3_N 0xe00 +#define BIT_MASK_BB_CHSMOOTHCFG4_N 0x7000 +#define BIT_MASK_BB_MRCMODE_N 0x800000 +#define BIT_MASK_BB_THEVMCFG_N 0x7000000 + +#define BIT_MASK_BB_LOOPFITTYPE_N 0x1 // Useless +#define BIT_MASK_BB_UPDCFO_N 0x40 +#define BIT_MASK_BB_UPDCFOOFFDATA_N 0x80 +#define BIT_MASK_BB_ADVUPDCFO_N 0x100 +#define BIT_MASK_BB_ADVTIMECTRL_N 0x800 +#define BIT_MASK_BB_UPDCLKO_N 0x1000 +#define BIT_MASK_BB_FC_N 0x6000 +#define BIT_MASK_BB_TRACKINGMODE_N 0x8000 +#define BIT_MASK_BB_PHCMPENABLE_N 0x10000 +#define BIT_MASK_BB_UPDCLKOLTF_N 0x20000 +#define BIT_MASK_BB_COMCHCFO_N 0x40000 +#define BIT_MASK_BB_CSIESTIMODE_N 0x80000 +#define BIT_MASK_BB_ADVUPDEQZ_N 0x100000 +#define BIT_MASK_BB_UCHCFG_N 0x7000000 +#define BIT_MASK_BB_UPDEQZ_N 0x8000000 + +#define BIT_MASK_BB_TXAGCRATE18_06_N 0x7f7f7f7f // Useless +#define BIT_MASK_BB_TXAGCRATE54_24_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS32_N 0x7f +#define BIT_MASK_BB_TXAGCRATECCK_N 0x7f00 +#define BIT_MASK_BB_TXAGCRATEMCS3_MCS0_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS7_MCS4_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS11_MCS8_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS15_MCS12_N 0x7f7f7f7f + +//Rx Pseduo noise +#define BIT_MASK_BB_RXPESUDONOISEON_N 0x20000000 // Useless +#define BIT_MASK_BB_RXPESUDONOISE_A_N 0xff +#define BIT_MASK_BB_RXPESUDONOISE_B_N 0xff00 +/* +#define BIT_MASK_BB_RXPESUDONOISE_C_N 0xff0000 +#define BIT_MASK_BB_RXPESUDONOISE_D_N 0xff000000 +*/ +#define BIT_MASK_BB_PESUDONOISESTATE_A_N 0xffff +#define BIT_MASK_BB_PESUDONOISESTATE_B_N 0xffff0000 +/* +#define BIT_MASK_BB_PESUDONOISESTATE_C_N 0xffff +#define BIT_MASK_BB_PESUDONOISESTATE_D_N 0xffff0000 +*/ + + +// +//7. RF Register +// +//Zebra1 +#define BIT_MASK_RF_ZEBRA1_HSSIENABLE_N 0x8 // Useless +#define BIT_MASK_RF_ZEBRA1_TRXCONTROL_N 0xc00 +#define BIT_MASK_RF_ZEBRA1_TRXGAINSETTING_N 0x07f +#define BIT_MASK_RF_ZEBRA1_RXCORNER_N 0xc00 +#define BIT_MASK_RF_ZEBRA1_TXCHARGEPUMP_N 0x38 +#define BIT_MASK_RF_ZEBRA1_RXCHARGEPUMP_N 0x7 +#define BIT_MASK_RF_ZEBRA1_CHANNELNUM_N 0xf80 +#define BIT_MASK_RF_ZEBRA1_TXLPFBW_N 0x400 +#define BIT_MASK_RF_ZEBRA1_RXLPFBW_N 0x600 + +//Zebra4 +#define BIT_MASK_RF_RTL8256REGMODECTRL1_N 0x100 // Useless +#define BIT_MASK_RF_RTL8256REGMODECTRL0_N 0x40 +#define BIT_MASK_RF_RTL8256_TXLPFBW_N 0x18 +#define BIT_MASK_RF_RTL8256_RXLPFBW_N 0x600 + +//RTL8258 +#define BIT_MASK_RF_RTL8258_TXLPFBW_N 0xc // Useless +#define BIT_MASK_RF_RTL8258_RXLPFBW_N 0xc00 +#define BIT_MASK_RF_RTL8258_RSSILPFBW_N 0xc0 + + + +#endif //#if IS_RTL88XX_N + +// Other Common setting bit define + +//byte endable for sb_write +#define BIT_MASK_SET_BYTE0_COMMON 0x1 // Useless +#define BIT_MASK_SET_BYTE1_COMMON 0x2 +#define BIT_MASK_SET_BYTE2_COMMON 0x4 +#define BIT_MASK_SET_BYTE3_COMMON 0x8 +#define BIT_MASK_SET_WORD0_COMMON 0x3 +#define BIT_MASK_SET_WORD1_COMMON 0xc +#define BIT_MASK_SET_DWORD_COMMON 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define BIT_MASK_SET_MASKBYTE0_COMMON 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define BIT_MASK_SET_MASKBYTE1_COMMON 0xff00 +#define BIT_MASK_SET_MASKBYTE2_COMMON 0xff0000 +#define BIT_MASK_SET_MASKBYTE3_COMMON 0xff000000 +#define BIT_MASK_SET_MASKHWORD_COMMON 0xffff0000 +#define BIT_MASK_SET_MASKLWORD_COMMON 0x0000ffff +#define BIT_MASK_SET_MASKDWORD_COMMON 0xffffffff +#define BIT_MASK_SET_MASKH4BITS_COMMON 0xf0000000 +#define BIT_MASK_SET_MASKH3BYTES_COMMON 0xffffff00 +#define BIT_MASK_SET_MASKOFDM_D_COMMON 0xffc00000 +#define BIT_MASK_SET_MASKCCK_COMMON 0x3f3f3f3f + +//for PutRFRegsetting & GetRFRegSetting BitMask +#define BIT_MASK_SET_MASK12BITS_COMMON 0xfff // RF Reg mask bits +#define BIT_MASK_SET_MASK20BITS_COMMON 0xfffff // RF Reg mask bits T65 RF + + +#endif//__INC_HALCOMPHYBIT_H + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyReg.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyReg.h old mode 100755 new mode 100644 index 3c3d78f87d6..e54dd5b0251 --- a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyReg.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComPhyReg.h @@ -1,692 +1,692 @@ - -#ifndef __INC_HALCOMPHYREG_BB_H -#define __INC_HALCOMPHYREG_BB_H - -#if IS_RTL88XX_AC - - - -// -// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 -// 3. RF register 0x00-2E -// 4. Bit Mask for BB/RF register -// 5. Other defintion for BB/RF R/W -// - -//============Programming guide Start===================== -/* - BB REG define rules - 1. For all reg define, it should be prefixed by " REG_BB" - - - RF REG define rules - 1. For all reg define, it should be prefixed by " REG_RF" - -*/ -/**** page 8 ****/ -#define REG_BB_CCKENABLE_AC 0x808 // OFDM/CCK block enable -#define REG_BB_RXPATH_AC 0x808 // Rx antenna -#define REG_BB_TXPATH_AC 0x80c // Tx antenna -#define REG_BB_AGC_TABLE_AC 0x82c // AGC tabel select -#define REG_BB_PWED_TH_AC 0x830 -#define REG_BB_BWINDICATION_AC 0x834 -#define REG_BB_CCAONSEC_AC 0x838 -#define REG_BB_L1_Weight_Jaguar 0x840 -#define REG_BB_L1PEAKTH_AC 0x848 -#define REG_BB_FC_AREA_AC 0x860 // fc_area -#define REG_BB_FPGA0_XB_RFINTERFACEOE_AC 0x864 -#define REG_BB_FPGA0_XAB_RFINTERFACESW_AC 0x870 // RF Interface Software Control -#define REG_BB_FPGA0_XCD_RFINTERFACESW_AC 0x874 -#define REG_BB_FPGA0_XAB_RFPARAMETER_AC 0x878 // RF Parameter -#define REG_BB_FPGA0_XCD_RFPARAMETER_AC 0x87c -#define REG_BB_FPGA0_ANALOGPARAMETER1_AC 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define REG_BB_FPGA0_ANALOGPARAMETER2_AC 0x884 -#define REG_BB_FPGA0_ANALOGPARAMETER3_AC 0x888 -#define REG_BB_FPGA0_ADDACLOCKEN_AC 0x888 // enable ad/da clock1 for dual-phy -#define REG_BB_FPGA0_ANALOGPARAMETER4_AC 0x88c -#define REG_BB_EDCCA_AC 0x8a4 // EDCCA -#define REG_BB_RFMOD_AC 0x8ac //RF mode -#define REG_BB_HSSIREAD_AC 0x8b0 // RF read addr -#define REG_BB_FC_ENABL_VHT_AC 0x8c0 -#define REG_BB_VHTLEN_USE_LSIG_AC 0x8c3 // Use LSIG for VHT length -#define REG_BB_ADC_BUF_CLK_AC 0x8c4 -#define REG_BB_ADC_BUF_CLK_2_AC 0x8c8 - -/**** For 8814 Rx spur issue ****/ -#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) -#define rNBI_Setting_Jaguar 0x87c -#define rCSI_Mask_Setting1_Jaguar 0x874 -#define rCSI_Fix_Mask7_Jaguar 0x89c -#define rCSI_Fix_Mask6_Jaguar 0x898 -#define rCSI_Fix_Mask0_Jaguar 0x880 -#define rCSI_Fix_Mask1_Jaguar 0x884 - -// Block & Path enable -#define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable -#define bOFDMEN_Jaguar 0x20000000 -#define bCCKEN_Jaguar 0x10000000 -#define rADC_Buf_160_Clk_Jaguar 0x8c4 -#endif - -/**** page 9 ****/ -#define REG_BB_SINGLETONE_CONTTX_AC 0x914 -#define REG_BB_AGC_TABLE_AC_V2 0x958 -#define REG_BB_TX_PATH_SEL_1 0x93c -#define REG_BB_TX_PATH_SEL_2 0x940 - - -/**** page a ****/ -#define REG_BB_CCK_SYSTEM_AC 0xa00 // for cck sideband -#define REG_BB_CCK_RX_AC 0xa04 // for cck rx path selection -#define REG_BB_CCK_CCA_AC 0xa08 // cca threshold -// CCK TX scaling -#define REG_BB_CCK_TXFILTER1_AC 0xa20 -#define REG_BB_CCK_TXFILTER2_AC 0xa24 -#define REG_BB_CCK_TXFILTER3_MSK_AC 0xa28 -#define REG_BB_CCK_FALSEALARM_AC 0xa5c // counter for cck false alarm - -/**** page b ****/ -// RSSI Dump -#define REG_BB_A_RSSIDUMP_AC 0xBF0 -#define REG_BB_B_RSSIDUMP_AC 0xBF1 -#define REG_BB_S1_RXEVMDUMP_AC 0xBF4 -#define REG_BB_S2_RXEVMDUMP_AC 0xBF5 -#define REG_BB_A_RXSNRDUMP_AC 0xBF6 -#define REG_BB_B_RXSNRDUMP_AC 0xBF7 -#define REG_BB_A_CFOSHORTDUMP_AC 0xBF8 -#define REG_BB_B_CFOSHORTDUMP_AC 0xBFA -#define REG_BB_A_CFOLONGDUMP_AC 0xBEC -#define REG_BB_B_CFOLONGDUMP_AC 0xBEE -// YN: mask the following register definition temporarily -//#define REG_BB_PDP_ANTA_AC 0xb00 -//#define REG_BB_PDP_ANTA_4_AC 0xb04 -//#define REG_BB_CONFIG_PMPD_ANTA_AC 0xb28 -//#define REG_BB_CONFIG_ANTA_AC 0xb68 -//#define REG_BB_CONFIG_ANTB_AC 0xb6c -//#define REG_BB_PDP_ANTB_AC 0xb70 -//#define REG_BB_PDP_ANTB_4_AC 0xb74 -//#define REG_BB_CONFIG_PMPD_ANTB_AC 0xb98 -//#define REG_BB_APK_AC 0xbd8 - -/**** page c ****/ -#define REG_BB_A_RXIQC_AB_AC 0xc10 //RxIQ imblance matrix coeff. A & B -#define REG_BB_A_RXIQC_CD_AC 0xc14 //RxIQ imblance matrix coeff. C & D -#define REG_BB_AGC_TABLE_AC_V1 0xc1c - -// TX AGC -#define REG_BB_TXAGC_A_CCK11_CCK1_AC 0xc20 -#define REG_BB_TXAGC_A_OFDM18_OFDM6_AC 0xc24 -#define REG_BB_TXAGC_A_OFDM54_OFDM24_AC 0xc28 -#define REG_BB_TXAGC_A_MCS3_MCS0_AC 0xc2c -#define REG_BB_TXAGC_A_MCS7_MCS4_AC 0xc30 -#define REG_BB_TXAGC_A_MCS11_MCS8_AC 0xc34 -#define REG_BB_TXAGC_A_MCS15_MCS12_AC 0xc38 -#define REG_BB_TXAGC_A_MCS19_MCS16_AC 0xcd8 -#define REG_BB_TXAGC_A_MCS23_MCS20_AC 0xcdc -#define REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC 0xc3c -#define REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC 0xc40 -#define REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC 0xc44 -#define REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC 0xc48 -#define REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC 0xc4c -#define REG_BB_TXAGC_A_NSS3INDEX3_NSS3INDEX0_AC 0xce0 -#define REG_BB_TXAGC_A_NSS3INDEX7_NSS3INDEX4_AC 0xce4 -#define REG_BB_TXAGC_A_NSS3INDEX9_NSS3INDEX8_AC 0xce8 - -// DIG-related -#define REG_BB_A_IGI_AC 0xc50 // Initial Gain for path-A -// AFE-related -#define REG_BB_A_AFEPWR1_AC 0xc60 // dynamic AFE power control -#define REG_BB_A_AFEPWR2_AC 0xc64 // dynamic AFE power control -#define REG_BB_A_RX_WAITCCA_TX_CCKRFON_AC 0xc68 -#define REG_BB_A_TX_CCKBBON_OFDMRFON_AC 0xc6c -#define REG_BB_A_TX_OFDMBBON_TX2RX_AC 0xc70 -#define REG_BB_A_TX2TX_RXCCK_AC 0xc74 -#define REG_BB_A_RX_OFDM_WAITRIFS_AC 0xc78 -#define REG_BB_A_RX2RX_BT_AC 0xc7c -#define REG_BB_A_SLEEP_NAV_AC 0xc80 -#define REG_BB_A_PMPD_AC 0xc84 -#define REG_BB_A_LSSIWRITE_AC 0xc90 // RF write addr -#define REG_BB_A_RFE_PINMUX_AC 0xcb0 // Path_A RFE cotrol pinmux -#define REG_BB_A_RFE_AC 0xcb8 // Path_A RFE cotrol - -/**** page d ****/ -#define REG_BB_A_PIREAD_AC 0xd04 // RF readback with PI -#define REG_BB_B_PIREAD_AC 0xd44 // RF readback with PI -#define REG_BB_C_PIREAD_AC 0xd84 // RF readback with PI -#define REG_BB_D_PIREAD_AC 0xdc4 // RF readback with PI -#define REG_BB_A_SIREAD_AC 0xd08 // RF readback with SI -#define REG_BB_B_SIREAD_AC 0xd48 // RF readback with SI -#define REG_BB_C_SIREAD_AC 0xd88 // RF readback with SI -#define REG_BB_D_SIREAD_AC 0xdc8 // RF readback with SI - - -/**** page e ****/ -// RXIQC -#define REG_BB_B_TXSCALE_AC 0xe1c // Path_B TX scaling factor -#define REG_BB_B_RXIQC_AB_AC 0xe10 //RxIQ imblance matrix coeff. A & B -#define REG_BB_B_RXIQC_CD_AC 0xe14 //RxIQ imblance matrix coeff. C & D - -// TX AGC -#define REG_BB_TXAGC_B_CCK11_CCK1_AC 0xe20 -#define REG_BB_TXAGC_B_OFDM18_OFDM6_AC 0xe24 -#define REG_BB_TXAGC_B_OFDM54_OFDM24_AC 0xe28 -#define REG_BB_TXAGC_B_MCS3_MCS0_AC 0xe2c -#define REG_BB_TXAGC_B_MCS7_MCS4_AC 0xe30 -#define REG_BB_TXAGC_B_MCS11_MCS8_AC 0xe34 -#define REG_BB_TXAGC_B_MCS15_MCS12_AC 0xe38 -#define REG_BB_TXAGC_B_MCS19_MCS16_AC 0xed8 -#define REG_BB_TXAGC_B_MCS23_MCS20_AC 0xedc -#define REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC 0xe3c -#define REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC 0xe40 -#define REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC 0xe44 -#define REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC 0xe48 -#define REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC 0xe4c -#define REG_BB_TXAGC_B_NSS3INDEX3_NSS3INDEX0_AC 0xee0 -#define REG_BB_TXAGC_B_NSS3INDEX7_NSS3INDEX4_AC 0xee4 -#define REG_BB_TXAGC_B_NSS3INDEX9_NSS3INDEX8_AC 0xee8 - -// DIG-related -#define REG_BB_B_IGI_AC 0xe50 // Initial Gain for path-B -#define REG_BB_B_LSSIWRITE_AC 0xe90 // RF write addr - -// Misc functions -#define REG_BB_B_RFE_PINMUX_AC 0xeb0 // Path_B RFE control pinmux -#define REG_BB_B_RFE_AC 0xeb8 // Path_B RFE control - -/**** page f ****/ -// DIG-related -#define REG_BB_OFDM_FALSEALARM1_AC 0xf48 // counter for break -#define REG_BB_OFDM_FALSEALARM2_AC 0xf4c // counter for spoofing -// Report-related -#define REG_BB_OFDM_SHORTCFOAB_AC 0xf60 -#define REG_BB_OFDM_LONGCFOAB_AC 0xf64 -#define REG_BB_OFDM_ENDCFOAB_AC 0xf70 -#define REG_BB_OFDM_AGCREPORT_AC 0xf84 -#define REG_BB_OFDM_RXSNR_AC 0xf88 -#define REG_BB_OFDM_RXEVMCSI_AC 0xf8c -#define REG_BB_OFDM_SIGREPORT_AC 0xf90 - -/**** page 18 ****/ -// TX AGC -#define REG_BB_TXAGC_C_CCK11_CCK1_AC 0x1820 -#define REG_BB_TXAGC_C_OFDM18_OFDM6_AC 0x1824 -#define REG_BB_TXAGC_C_OFDM54_OFDM24_AC 0x1828 -#define REG_BB_TXAGC_C_MCS3_MCS0_AC 0x182c -#define REG_BB_TXAGC_C_MCS7_MCS4_AC 0x1830 -#define REG_BB_TXAGC_C_MCS11_MCS8_AC 0x1834 -#define REG_BB_TXAGC_C_MCS15_MCS12_AC 0x1838 -#define REG_BB_TXAGC_C_MCS19_MCS16_AC 0x18d8 -#define REG_BB_TXAGC_C_MCS23_MCS20_AC 0x18dc -#define REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC 0x183c -#define REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC 0x1840 -#define REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC 0x1844 -#define REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC 0x1848 -#define REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC 0x184c -#define REG_BB_TXAGC_C_NSS3INDEX3_NSS3INDEX0_AC 0x18e0 -#define REG_BB_TXAGC_C_NSS3INDEX7_NSS3INDEX4_AC 0x18e4 -#define REG_BB_TXAGC_C_NSS3INDEX9_NSS3INDEX8_AC 0x18e8 - -#define REG_BB_C_LSSIWRITE_AC 0x1890 // RF write addr -#define REG_BB_C_RFE_PINMUX_AC 0x18b4 // Path_C RFE control pinmux - -/**** page 19 ****/ -//TX BeamForming -#define REG_BB_TXBF_ANT_SET_BF1 0x19ac -#define REG_BB_TXBF_ANT_SET_BF0 0x19b4 - - -/**** page 1a ****/ -// TX AGC -#define REG_BB_TXAGC_D_CCK11_CCK1_AC 0x1a20 -#define REG_BB_TXAGC_D_OFDM18_OFDM6_AC 0x1a24 -#define REG_BB_TXAGC_D_OFDM54_OFDM24_AC 0x1a28 -#define REG_BB_TXAGC_D_MCS3_MCS0_AC 0x1a2c -#define REG_BB_TXAGC_D_MCS7_MCS4_AC 0x1a30 -#define REG_BB_TXAGC_D_MCS11_MCS8_AC 0x1a34 -#define REG_BB_TXAGC_D_MCS15_MCS12_AC 0x1a38 -#define REG_BB_TXAGC_D_MCS19_MCS16_AC 0x1ad8 -#define REG_BB_TXAGC_D_MCS23_MCS20_AC 0x1adc -#define REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC 0x1a3c -#define REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC 0x1a40 -#define REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC 0x1a44 -#define REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC 0x1a48 -#define REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC 0x1a4c -#define REG_BB_TXAGC_D_NSS3INDEX3_NSS3INDEX0_AC 0x1ae0 -#define REG_BB_TXAGC_D_NSS3INDEX7_NSS3INDEX4_AC 0x1ae4 -#define REG_BB_TXAGC_D_NSS3INDEX9_NSS3INDEX8_AC 0x1ae8 - -#define REG_BB_D_LSSIWRITE_AC 0x1a90 // RF write addr -#define REG_BB_D_RFE_PINMUX_AC 0x1ab4 // Path_D RFE control pinmux - - -////////////////////////////////////// - - - - -// RF Register -// -#define REG_RF_AC_AC 0x00 -#define REG_RF_RF_TOP_AC 0x07 -#define REG_RF_TXLOK_AC 0x08 -#define REG_RF_TXAPK_AC 0x0B -#define REG_RF_CHNLBW_AC 0x18 // RF channel and BW switch -#define REG_RF_TXLCTANK_AC 0x54 -#define REG_RF_APK_AC 0x63 -#define REG_BRF_CHNLBW_MOD_AG_AC 0x70300 -#define REG_BRF_CHNLBW_BW_AC 0xc00 -#define REG_RF_RCK1_AC 0x1c -#define REG_RF_RCK2_AC 0x1d -#define REG_RF_RCK3_AC 0x1e -#define REG_RF_LCK_AC 0xB4 -#define REG_BB_BRFREGOFFSETMASK_AC 0xfffff - -// TX AGC V2 - 8814A MP -#define REG_BB_TXAGC_V2_BASE_ADDR 0x1998 - -/* -Example: -0x1998 = 0x12801151 -0x1998[7:0]=0x51: TX_RATE VHT 4ss mcs7 -0x1998[9:8]=path_idx=1: path B (path A/B/C/D -> 0/1/2/3) -0x1998[12]¢FDy3¢FG?n1, |b8813!LS|3!¡Ó@¢FDI. -0x1998[23]=1: write -0x1998[31:24]=0x12: txagc codeword -*/ - -#define BIT_SHIFT_BB_TXAGC_V2_TX_RATE 0 -#define BIT_MASK_BB_TXAGC_V2_TX_RATE 0xff -#define BIT_BB_TXAGC_V2_TX_RATE(x) (((x) & BIT_MASK_BB_TXAGC_V2_TX_RATE) << BIT_SHIFT_BB_TXAGC_V2_TX_RATE) - -#define BIT_SHIFT_BB_TXAGC_V2_PATH_IDX 8 -#define BIT_MASK_BB_TXAGC_V2_PATH_IDX 0x3 -#define BIT_BB_TXAGC_V2_PATH_IDX(x) (((x) & BIT_MASK_BB_TXAGC_V2_PATH_IDX) << BIT_SHIFT_BB_TXAGC_V2_PATH_IDX) - -#define BIT_SHIFT_BB_TXAGC_V2_NONE 12 -#define BIT_MASK_BB_TXAGC_V2_NONE 0x1 -#define BIT_BB_TXAGC_V2_NONE(x) (((x) & BIT_MASK_BB_TXAGC_V2_NONE) << BIT_SHIFT_BB_TXAGC_V2_NONE) - -#define BIT_SHIFT_BB_TXAGC_V2_WRITE 23 -#define BIT_MASK_BB_TXAGC_V2_WRITE 0x1 -#define BIT_BB_TXAGC_V2_WRITE(x) (((x) & BIT_MASK_BB_TXAGC_V2_WRITE) << BIT_SHIFT_BB_TXAGC_V2_WRITE) - -#define BIT_SHIFT_BB_TXAGC_V2_CODEWORD 24 -#define BIT_MASK_BB_TXAGC_V2_CODEWORD 0xff -#define BIT_BB_TXAGC_V2_CODEWORD(x) (((x) & BIT_MASK_BB_TXAGC_V2_CODEWORD) << BIT_SHIFT_BB_TXAGC_V2_CODEWORD) - -#define FILL_REG_BB_TXAGC_V2(RATE, PATH_IDX, NONE_VALUE, WRITE_VALUE, DEF_POWER) (BIT_BB_TXAGC_V2_TX_RATE(RATE) | BIT_BB_TXAGC_V2_PATH_IDX(PATH_IDX) | BIT_BB_TXAGC_V2_NONE(NONE_VALUE) | BIT_BB_TXAGC_V2_WRITE(WRITE_VALUE) | BIT_BB_TXAGC_V2_CODEWORD(DEF_POWER)) - -#define TX_AGC_CCK_1M 0x00 -#define TX_AGC_CCK_2M 0x01 -#define TX_AGC_CCK_5_5M 0x02 -#define TX_AGC_CCK_11M 0x03 -#define TX_AGC_OFDM_6M 0x04 -#define TX_AGC_OFDM_9M 0x05 -#define TX_AGC_OFDM_12M 0x06 -#define TX_AGC_OFDM_18M 0x07 -#define TX_AGC_OFDM_24M 0x08 -#define TX_AGC_OFDM_36M 0x09 -#define TX_AGC_OFDM_48M 0x0A -#define TX_AGC_OFDM_54M 0x0B - -#define TX_AGC_HT_NSS1_MCS0 0x0C -#define TX_AGC_HT_NSS1_MCS1 0x0D -#define TX_AGC_HT_NSS1_MCS2 0x0E -#define TX_AGC_HT_NSS1_MCS3 0x0F -#define TX_AGC_HT_NSS1_MCS4 0x10 -#define TX_AGC_HT_NSS1_MCS5 0x11 -#define TX_AGC_HT_NSS1_MCS6 0x12 -#define TX_AGC_HT_NSS1_MCS7 0x13 -#define TX_AGC_HT_NSS2_MCS8 0x14 -#define TX_AGC_HT_NSS2_MCS9 0x15 -#define TX_AGC_HT_NSS2_MCS10 0x16 -#define TX_AGC_HT_NSS2_MCS11 0x17 -#define TX_AGC_HT_NSS2_MCS12 0x18 -#define TX_AGC_HT_NSS2_MCS13 0x19 -#define TX_AGC_HT_NSS2_MCS14 0x1A -#define TX_AGC_HT_NSS2_MCS15 0x1B -#define TX_AGC_HT_NSS3_MCS16 0x1C -#define TX_AGC_HT_NSS3_MCS17 0x1D -#define TX_AGC_HT_NSS3_MCS18 0x1E -#define TX_AGC_HT_NSS3_MCS19 0x1F -#define TX_AGC_HT_NSS3_MCS20 0x20 -#define TX_AGC_HT_NSS3_MCS21 0x21 -#define TX_AGC_HT_NSS3_MCS22 0x22 -#define TX_AGC_HT_NSS3_MCS23 0x23 -#define TX_AGC_HT_NSS4_MCS24 0x24 -#define TX_AGC_HT_NSS4_MCS25 0x25 -#define TX_AGC_HT_NSS4_MCS26 0x26 -#define TX_AGC_HT_NSS4_MCS27 0x27 -#define TX_AGC_HT_NSS4_MCS28 0x28 -#define TX_AGC_HT_NSS4_MCS29 0x29 -#define TX_AGC_HT_NSS4_MCS30 0x2A -#define TX_AGC_HT_NSS4_MCS31 0x2B - -#define TX_AGC_VHT_NSS1_MCS0 0x2C -#define TX_AGC_VHT_NSS1_MCS1 0x2D -#define TX_AGC_VHT_NSS1_MCS2 0x2E -#define TX_AGC_VHT_NSS1_MCS3 0x2F -#define TX_AGC_VHT_NSS1_MCS4 0x30 -#define TX_AGC_VHT_NSS1_MCS5 0x31 -#define TX_AGC_VHT_NSS1_MCS6 0x32 -#define TX_AGC_VHT_NSS1_MCS7 0x33 -#define TX_AGC_VHT_NSS1_MCS8 0x34 -#define TX_AGC_VHT_NSS1_MCS9 0x35 -#define TX_AGC_VHT_NSS2_MCS0 0x36 -#define TX_AGC_VHT_NSS2_MCS1 0x37 -#define TX_AGC_VHT_NSS2_MCS2 0x38 -#define TX_AGC_VHT_NSS2_MCS3 0x39 -#define TX_AGC_VHT_NSS2_MCS4 0x3A -#define TX_AGC_VHT_NSS2_MCS5 0x3B -#define TX_AGC_VHT_NSS2_MCS6 0x3C -#define TX_AGC_VHT_NSS2_MCS7 0x3D -#define TX_AGC_VHT_NSS2_MCS8 0x3E -#define TX_AGC_VHT_NSS2_MCS9 0x3F -#define TX_AGC_VHT_NSS3_MCS0 0x40 -#define TX_AGC_VHT_NSS3_MCS1 0x41 -#define TX_AGC_VHT_NSS3_MCS2 0x42 -#define TX_AGC_VHT_NSS3_MCS3 0x43 -#define TX_AGC_VHT_NSS3_MCS4 0x44 -#define TX_AGC_VHT_NSS3_MCS5 0x45 -#define TX_AGC_VHT_NSS3_MCS6 0x46 -#define TX_AGC_VHT_NSS3_MCS7 0x47 -#define TX_AGC_VHT_NSS3_MCS8 0x48 -#define TX_AGC_VHT_NSS3_MCS9 0x49 -#define TX_AGC_VHT_NSS4_MCS0 0x4A -#define TX_AGC_VHT_NSS4_MCS1 0x4B -#define TX_AGC_VHT_NSS4_MCS2 0x4C -#define TX_AGC_VHT_NSS4_MCS3 0x4D -#define TX_AGC_VHT_NSS4_MCS4 0x4E -#define TX_AGC_VHT_NSS4_MCS5 0x4F -#define TX_AGC_VHT_NSS4_MCS6 0x50 -#define TX_AGC_VHT_NSS4_MCs7 0x51 -#define TX_AGC_VHT_NSS4_MCS8 0x52 -#define TX_AGC_VHT_NSS4_MCS9 0x53 - -//eric-8814 -#define RF_SYN_G1 0x25 // RF TX Power control -#define RF_SYN_G2 0x26 // RF TX Power control -#define RF_SYN_G3 0x27 // RF TX Power control -#define RF_SYN_G4 0x28 // RF TX Power control -#define RF_SYN_G5 0x29 // RF TX Power control -#define RF_SYN_G6 0x2A // RF TX Power control -#define RF_SYN_G7 0x2B // RF TX Power control -#define RF_SYN_G8 0x2C // RF TX Power control - -#define RF_RCK_OS 0x30 // RF TX PA control -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C // -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF - - -#endif //#if IS_RTL88XX_AC - - -#if IS_RTL88XX_N - -// -// 2. BB Register Page8(0x800) -// -#define REG_BB_FPGA0_RFMOD_N 0x800 //RF mode & CCK TxSC // RF BW Setting?? -#define REG_BB_FPGA0_TXINFO_N 0x804 // Status report?? -#define REG_BB_FPGA0_PSDFUNCTION_N 0x808 -#define REG_BB_FPGA0_TXGAINSTAGE_N 0x80c // Set TX PWR init gain? -#define REG_BB_FPGA0_RFTIMING1_N 0x810 // Useless now -#define REG_BB_FPGA0_RFTIMING2_N 0x814 -#define REG_BB_PRIMESC_N 0x818 - -#define REG_BB_FPGA0_XA_HSSIPARAMETER1_N 0x820 // RF 3 wire register -#define REG_BB_FPGA0_XA_HSSIPARAMETER2_N 0x824 -#define REG_BB_FPGA0_XB_HSSIPARAMETER1_N 0x828 -#define REG_BB_FPGA0_XB_HSSIPARAMETER2_N 0x82c -#define REG_BB_TXAGC_B_RATE18_06_N 0x830 -#define REG_BB_TXAGC_B_RATE54_24_N 0x834 -#define REG_BB_TXAGC_B_CCK5_1_MCS32_N 0x838 -#define REG_BB_TXAGC_B_MCS03_MCS00_N 0x83c -#define REG_BB_FPGA0_XA_LSSIPARAMETER_N 0x840 -#define REG_BB_FPGA0_XB_LSSIPARAMETER_N 0x844 -#define REG_BB_TXAGC_B_MCS07_MCS04_N 0x848 -#define REG_BB_TXAGC_B_MCS11_MCS08_N 0x84c -#define REG_BB_FPGA0_RFWAKEUPPARAMETER_N 0x850 // Useless now -#define REG_BB_FPGA0_RFSLEEPUPPARAMETER_N 0x854 -#define REG_BB_FPGA0_XAB_SWITCHCONTROL_N 0x858 // RF Channel switch -#define REG_BB_FPGA0_XCD_SWITCHCONTROL_N 0x85c -#define REG_BB_FPGA0_XA_RFINTERFACEOE_N 0x860 // RF Channel switch -#define REG_BB_FPGA0_XB_RFINTERFACEOE_N 0x864 -#define REG_BB_TXAGC_B_MCS15_MCS12_N 0x868 -#define REG_BB_TXAGC_A_CCK11_2_B_CCK11_N 0x86c -#define REG_BB_FPGA0_XAB_RFINTERFACESW_N 0x870 // RF Interface Software Control -#define REG_BB_FPGA0_XCD_RFINTERFACESW_N 0x874 -#define REG_BB_FPGA0_XAB_RFPARAMETER_N 0x878 // RF Parameter -#define REG_BB_FPGA0_XCD_RFPARAMETER_N 0x87c -#define REG_BB_FPGA0_ANALOGPARAMETER1_N 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define REG_BB_FPGA0_ANALOGPARAMETER2_N 0x884 -#define REG_BB_FPGA0_ANALOGPARAMETER3_N 0x888 // Useless now -#define REG_BB_FPGA0_ANALOGPARAMETER4_N 0x88c -#define REG_BB_FPGA0_XA_LSSIREADBACK_N 0x8a0 // Tranceiver LSSI Readback -#define REG_BB_FPGA0_XB_LSSIREADBACK_N 0x8a4 - -#define REG_BB_FPGA0_PSDREPORT_N 0x8b4 // Useless now -#define REG_BB_TRANSCEIVERA_HSPI_READBACK_N 0x8b8 -#define REG_BB_TRANSCEIVERB_HSPI_READBACK_N 0x8bc -#define REG_BB_FPGA0_XAB_RFINTERFACERB_N 0x8e0 // Useless now // RF Interface Readback Value - - - -// -// 3. BB Register Page9(0x900) -// -#define REG_BB_FPGA1_RFMOD_N 0x900 //RF mode & OFDM TxSC // RF BW Setting?? -#define REG_BB_FPGA1_TXBLOCK_N 0x904 // Useless now -#define REG_BB_FPGA1_DEBUGSELECT_N 0x908 // Useless now -#define REG_BB_FPGA1_TXINFO_N 0x90c // Useless now // Status report?? - - -// -// 4. BB Register PageA(0xA00) -// -// Set Control channel to upper or lower. These settings are required only for 40MHz -#define REG_BB_CCK0_SYSTEM_N 0xa00 -#define REG_BB_CCK0_AFESETTING_N 0xa04 // Disable init gain now // Select RX path by RSSI -#define REG_BB_CCK0_CCA_N 0xa08 // Disable init gain now // Init gain -#define REG_BB_CCK0_RXAGC1_N 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series -#define REG_BB_CCK0_RXAGC2_N 0xa10 //AGC & DAGC -#define REG_BB_CCK0_RXHP_N 0xa14 -#define REG_BB_CCK0_DSPPARAMETER1_N 0xa18 //Timing recovery & Channel estimation threshold -#define REG_BB_CCK0_DSPPARAMETER2_N 0xa1c //SQ threshold -#define REG_BB_CCK0_TXFILTER1_N 0xa20 -#define REG_BB_CCK0_TXFILTER2_N 0xa24 -#define REG_BB_CCK0_DEBUGPORT_N 0xa28 //debug port and Tx filter3 -#define REG_BB_CCK0_FALSEALARMREPORT_N 0xa2c //0xa2d useless now 0xa30-a4f channel report -#define REG_BB_CCK0_TRSSIREPORT_N 0xa50 -#define REG_BB_CCK0_RXREPORT_N 0xa54 //0xa57 -#define REG_BB_CCK0_FACOUNTERLOWER_N 0xa5c //0xa5b -#define REG_BB_CCK0_FACOUNTERUPPER_N 0xa58 //0xa5c - - -// -// 5. BB Register PageC(0xC00) -// -#define REG_BB_OFDM0_LSTF_N 0xc00 -#define REG_BB_OFDM0_TRXPATHENABLE_N 0xc04 -#define REG_BB_OFDM0_TRMUXPAR_N 0xc08 -#define REG_BB_OFDM0_TRSWISOLATION_N 0xc0c -#define REG_BB_OFDM0_XARXAFE_N 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define REG_BB_OFDM0_XARXIQIMBALANCE_N 0xc14 //RxIQ imblance matrix -#define REG_BB_OFDM0_XBRXAFE_N 0xc18 -#define REG_BB_OFDM0_XBRXIQIMBALANCE_N 0xc1c -/* -#define REG_BB_OFDM0_XCRXAFE_N 0xc20 -#define REG_BB_OFDM0_XCRXIQIMBALANCE_N 0xc24 -#define REG_BB_OFDM0_XDRXAFE_N 0xc28 -#define REG_BB_OFDM0_XDRXIQIMBALANCE_N 0xc2c -*/ -#define REG_BB_OFDM0_RXDETECTOR1_N 0xc30 //PD,BW & SBD // DM tune init gain -#define REG_BB_OFDM0_RXDETECTOR2_N 0xc34 //SBD & Fame Sync. -#define REG_BB_OFDM0_RXDETECTOR3_N 0xc38 //Frame Sync. -#define REG_BB_OFDM0_RXDETECTOR4_N 0xc3c //PD, SBD, Frame Sync & Short-GI -#define REG_BB_OFDM0_RXDSP_N 0xc40 //Rx Sync Path -#define REG_BB_OFDM0_CFOANDDAGC_N 0xc44 //CFO & DAGC -#define REG_BB_OFDM0_CCADROPTHRESHOLD_N 0xc48 //CCA Drop threshold -#define REG_BB_OFDM0_ECCATHRESHOLD_N 0xc4c // energy CCA -#define REG_BB_OFDM0_XAAGCCORE1_N 0xc50 // DIG -#define REG_BB_OFDM0_XAAGCCORE2_N 0xc54 -#define REG_BB_OFDM0_XBAGCCORE1_N 0xc58 -#define REG_BB_OFDM0_XBAGCCORE2_N 0xc5c -/* -#define REG_BB_OFDM0_XCAGCCORE1_N 0xc60 -#define REG_BB_OFDM0_XCAGCCORE2_N 0xc64 -#define REG_BB_OFDM0_XDAGCCORE1_N 0xc68 -#define REG_BB_OFDM0_XDAGCCORE2_N 0xc6c -*/ -#define REG_BB_OFDM0_AGCPARAMETER1_N 0xc70 -#define REG_BB_OFDM0_AGCPARAMETER2_N 0xc74 -#define REG_BB_OFDM0_AGCRSSITABLE_N 0xc78 -#define REG_BB_OFDM0_HTSTFAGC_N 0xc7c -#define REG_BB_OFDM0_XATXIQIMBALANC_N 0xc80 // TX PWR TRACK and DIG -#define REG_BB_OFDM0_XATXAFE_N 0xc84 -#define REG_BB_OFDM0_XBTXIQIMBALANCE_N 0xc88 -#define REG_BB_OFDM0_XBTXAFE_N 0xc8c - - -#define REG_BB_OFDM0_XCTXIQIMBALANCE_N 0xc90 -#define REG_BB_OFDM0_XCTXAFE_N 0xc94 -#define REG_BB_OFDM0_XDTXIQIMBALANCE_N 0xc98 -#define REG_BB_OFDM0_XDTXAFE_N 0xc9c -#define REG_BB_OFDM0_RXIQEXTANTA_N 0xca0 - - -#define REG_BB_OFDM0_RXHPPARAMETER_N 0xce0 -#define REG_BB_OFDM0_TXPSEUDONOISEWGT_N 0xce4 -#define REG_BB_OFDM0_FRAMESYNC_N 0xcf0 -#define REG_BB_OFDM0_DFSREPORT_N 0xcf4 -#define REG_BB_OFDM0_TXCOEFF1_N 0xca4 -#define REG_BB_OFDM0_TXCOEFF2_N 0xca8 -#define REG_BB_OFDM0_TXCOEFF3_N 0xcac -#define REG_BB_OFDM0_TXCOEFF4_N 0xcb0 -#define REG_BB_OFDM0_TXCOEFF5_N 0xcb4 -#define REG_BB_OFDM0_TXCOEFF6_N 0xcb8 - - -// -// 6. BB Register PageD(0xD00) -// -#define REG_BB_OFDM1_LSTF_N 0xd00 -#define REG_BB_OFDM1_TRXPATHENABLE_N 0xd04 -#define REG_BB_OFDM1_CFO_N 0xd08 // No setting now -#define REG_BB_OFDM1_CSI1_N 0xd10 -#define REG_BB_OFDM1_SBD_N 0xd14 -#define REG_BB_OFDM1_CSI2_N 0xd18 -#define REG_BB_OFDM1_CFOTRACKING_N 0xd2c -#define REG_BB_OFDM1_TRXMESAURE1_N 0xd34 -#define REG_BB_OFDM1_INTFDET_N 0xd3c -#define REG_BB_OFDM1_PSEUDONOISESTATEAB_N 0xd50 -#define REG_BB_OFDM1_PSEUDONOISESTATECD_N 0xd54 -#define REG_BB_OFDM1_RXPSEUDONOISEWGT_N 0xd58 -#define REG_BB_OFDM_PHYCOUNTER1_N 0xda0 //cca, parity fail -#define REG_BB_OFDM_PHYCOUNTER2_N 0xda4 //rate illegal, crc8 fail -#define REG_BB_OFDM_PHYCOUNTER3_N 0xda8 //MCS not support -#define REG_BB_OFDM_SHORTCFOAB_N 0xdac // No setting now -#define REG_BB_OFDM_SHORTCFOCD_N 0xdb0 -#define REG_BB_OFDM_LONGCFOAB_N 0xdb4 -#define REG_BB_OFDM_LONGCFOCD_N 0xdb8 -#define REG_BB_OFDM_TAILCFOAB_N 0xdbc -#define REG_BB_OFDM_TAILCFOCD_N 0xdc0 -#define REG_BB_OFDM_PWMEASURE1_N 0xdc4 -#define REG_BB_OFDM_PWMEASURE2_N 0xdc8 -#define REG_BB_OFDM_BWREPORT_N 0xdcc -#define REG_BB_OFDM_AGCREPORT_N 0xdd0 -#define REG_BB_OFDM_RXSNR_N 0xdd4 -#define REG_BB_OFDM_RXEVMCSI_N 0xdd8 -#define REG_BB_OFDM_SIGREPORT_N 0xddc - - -// -// 6. BB Register PageE(0xE00) -// -#define REG_BB_TXAGC_A_RATE18_06_N 0xe00 -#define REG_BB_TXAGC_A_RATE54_24_N 0xe04 -#define REG_BB_TXAGC_A_CCK1_MCS32_N 0xe08 -#define REG_BB_TXAGC_A_MCS03_MCS00_N 0xe10 -#define REG_BB_TXAGC_A_MCS07_MCS04_N 0xe14 -#define REG_BB_TXAGC_A_MCS11_MCS08_N 0xe18 -#define REG_BB_TXAGC_A_MCS15_MCS12_N 0xe1c - - -// -// 7. RF Register 0x00-0x2E -// -//Zebra1 -#define REG_RF_ZEBRA1_HSSIENABLE_N 0x0 // Useless now -#define REG_RF_ZEBRA1_TRXENABLE1_N 0x1 -#define REG_RF_ZEBRA1_TRXENABLE2_N 0x2 -#define REG_RF_ZEBRA1_AGC_N 0x4 -#define REG_RF_ZEBRA1_CHARGEPUMP_N 0x5 -#define REG_RF_ZEBRA1_CHANNEL_N 0x7 // RF channel switch -#define REG_RF_ZEBRA1_TXGAIN_N 0x8 // Useless now -#define REG_RF_ZEBRA1_TXLPF_N 0x9 -#define REG_RF_ZEBRA1_RXLPF_N 0xb -#define REG_RF_ZEBRA1_RXHPFCORNER_N 0xc -#define REG_RF_RFCHANNEL_N 0x18 // RF channel switch For T65 RF 0222d -#define REG_RF_CSI_MASK_N 0x42 - -//Zebra4 -#define REG_RF_GLOBALCTRL_N 0 // Useless now -#define REG_RF_RTL8256_TXLPF_N 19 -#define REG_RF_RTL8256_RXLPF_N 11 - -//RTL8258 -#define REG_RF_RTL8258_RSSILPF_N 0xa -#define REG_RF_RTL8258_TXLPF_N 0x11 // Useless now -#define REG_RF_RTL8258_RXLPF_N 0x13 - -// 92E temp -#define RF_SYN_G1 0x25 // RF TX Power control -#define RF_SYN_G2 0x26 // RF TX Power control -#define RF_SYN_G3 0x27 // RF TX Power control -#define RF_SYN_G4 0x28 // RF TX Power control -#define RF_SYN_G5 0x29 // RF TX Power control -#define RF_SYN_G6 0x2A // RF TX Power control -#define RF_SYN_G7 0x2B // RF TX Power control -#define RF_SYN_G8 0x2C // RF TX Power control - -#define RF_RCK_OS 0x30 // RF TX PA control -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C // -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF - -#define REG_BFMEE_SEL_8192E 0x0714 -#define REG_SND_PTCL_CTRL_8192E 0x0718 -#define REG_BFMER0_INFO_8192E 0x06E4 -#define REG_BFMER1_INFO_8192E 0x06EC -#define REG_CSI_RPT_PARAM_BW20_92E 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_92E 0x06F8 - -#endif //#if IS_RTL88XX_N -#endif //#ifndef __INC_HALCOMPHYREG_BB_H - - + +#ifndef __INC_HALCOMPHYREG_BB_H +#define __INC_HALCOMPHYREG_BB_H + +#if IS_RTL88XX_AC + + + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + +//============Programming guide Start===================== +/* + BB REG define rules + 1. For all reg define, it should be prefixed by " REG_BB" + + + RF REG define rules + 1. For all reg define, it should be prefixed by " REG_RF" + +*/ +/**** page 8 ****/ +#define REG_BB_CCKENABLE_AC 0x808 // OFDM/CCK block enable +#define REG_BB_RXPATH_AC 0x808 // Rx antenna +#define REG_BB_TXPATH_AC 0x80c // Tx antenna +#define REG_BB_AGC_TABLE_AC 0x82c // AGC tabel select +#define REG_BB_PWED_TH_AC 0x830 +#define REG_BB_BWINDICATION_AC 0x834 +#define REG_BB_CCAONSEC_AC 0x838 +#define REG_BB_L1_Weight_Jaguar 0x840 +#define REG_BB_L1PEAKTH_AC 0x848 +#define REG_BB_FC_AREA_AC 0x860 // fc_area +#define REG_BB_FPGA0_XB_RFINTERFACEOE_AC 0x864 +#define REG_BB_FPGA0_XAB_RFINTERFACESW_AC 0x870 // RF Interface Software Control +#define REG_BB_FPGA0_XCD_RFINTERFACESW_AC 0x874 +#define REG_BB_FPGA0_XAB_RFPARAMETER_AC 0x878 // RF Parameter +#define REG_BB_FPGA0_XCD_RFPARAMETER_AC 0x87c +#define REG_BB_FPGA0_ANALOGPARAMETER1_AC 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define REG_BB_FPGA0_ANALOGPARAMETER2_AC 0x884 +#define REG_BB_FPGA0_ANALOGPARAMETER3_AC 0x888 +#define REG_BB_FPGA0_ADDACLOCKEN_AC 0x888 // enable ad/da clock1 for dual-phy +#define REG_BB_FPGA0_ANALOGPARAMETER4_AC 0x88c +#define REG_BB_EDCCA_AC 0x8a4 // EDCCA +#define REG_BB_RFMOD_AC 0x8ac //RF mode +#define REG_BB_HSSIREAD_AC 0x8b0 // RF read addr +#define REG_BB_FC_ENABL_VHT_AC 0x8c0 +#define REG_BB_VHTLEN_USE_LSIG_AC 0x8c3 // Use LSIG for VHT length +#define REG_BB_ADC_BUF_CLK_AC 0x8c4 +#define REG_BB_ADC_BUF_CLK_2_AC 0x8c8 + +/**** For 8814 Rx spur issue ****/ +#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) +#define rNBI_Setting_Jaguar 0x87c +#define rCSI_Mask_Setting1_Jaguar 0x874 +#define rCSI_Fix_Mask7_Jaguar 0x89c +#define rCSI_Fix_Mask6_Jaguar 0x898 +#define rCSI_Fix_Mask0_Jaguar 0x880 +#define rCSI_Fix_Mask1_Jaguar 0x884 + +// Block & Path enable +#define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable +#define bOFDMEN_Jaguar 0x20000000 +#define bCCKEN_Jaguar 0x10000000 +#define rADC_Buf_160_Clk_Jaguar 0x8c4 +#endif + +/**** page 9 ****/ +#define REG_BB_SINGLETONE_CONTTX_AC 0x914 +#define REG_BB_AGC_TABLE_AC_V2 0x958 +#define REG_BB_TX_PATH_SEL_1 0x93c +#define REG_BB_TX_PATH_SEL_2 0x940 + + +/**** page a ****/ +#define REG_BB_CCK_SYSTEM_AC 0xa00 // for cck sideband +#define REG_BB_CCK_RX_AC 0xa04 // for cck rx path selection +#define REG_BB_CCK_CCA_AC 0xa08 // cca threshold +// CCK TX scaling +#define REG_BB_CCK_TXFILTER1_AC 0xa20 +#define REG_BB_CCK_TXFILTER2_AC 0xa24 +#define REG_BB_CCK_TXFILTER3_MSK_AC 0xa28 +#define REG_BB_CCK_FALSEALARM_AC 0xa5c // counter for cck false alarm + +/**** page b ****/ +// RSSI Dump +#define REG_BB_A_RSSIDUMP_AC 0xBF0 +#define REG_BB_B_RSSIDUMP_AC 0xBF1 +#define REG_BB_S1_RXEVMDUMP_AC 0xBF4 +#define REG_BB_S2_RXEVMDUMP_AC 0xBF5 +#define REG_BB_A_RXSNRDUMP_AC 0xBF6 +#define REG_BB_B_RXSNRDUMP_AC 0xBF7 +#define REG_BB_A_CFOSHORTDUMP_AC 0xBF8 +#define REG_BB_B_CFOSHORTDUMP_AC 0xBFA +#define REG_BB_A_CFOLONGDUMP_AC 0xBEC +#define REG_BB_B_CFOLONGDUMP_AC 0xBEE +// YN: mask the following register definition temporarily +//#define REG_BB_PDP_ANTA_AC 0xb00 +//#define REG_BB_PDP_ANTA_4_AC 0xb04 +//#define REG_BB_CONFIG_PMPD_ANTA_AC 0xb28 +//#define REG_BB_CONFIG_ANTA_AC 0xb68 +//#define REG_BB_CONFIG_ANTB_AC 0xb6c +//#define REG_BB_PDP_ANTB_AC 0xb70 +//#define REG_BB_PDP_ANTB_4_AC 0xb74 +//#define REG_BB_CONFIG_PMPD_ANTB_AC 0xb98 +//#define REG_BB_APK_AC 0xbd8 + +/**** page c ****/ +#define REG_BB_A_RXIQC_AB_AC 0xc10 //RxIQ imblance matrix coeff. A & B +#define REG_BB_A_RXIQC_CD_AC 0xc14 //RxIQ imblance matrix coeff. C & D +#define REG_BB_AGC_TABLE_AC_V1 0xc1c + +// TX AGC +#define REG_BB_TXAGC_A_CCK11_CCK1_AC 0xc20 +#define REG_BB_TXAGC_A_OFDM18_OFDM6_AC 0xc24 +#define REG_BB_TXAGC_A_OFDM54_OFDM24_AC 0xc28 +#define REG_BB_TXAGC_A_MCS3_MCS0_AC 0xc2c +#define REG_BB_TXAGC_A_MCS7_MCS4_AC 0xc30 +#define REG_BB_TXAGC_A_MCS11_MCS8_AC 0xc34 +#define REG_BB_TXAGC_A_MCS15_MCS12_AC 0xc38 +#define REG_BB_TXAGC_A_MCS19_MCS16_AC 0xcd8 +#define REG_BB_TXAGC_A_MCS23_MCS20_AC 0xcdc +#define REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC 0xc3c +#define REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC 0xc40 +#define REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC 0xc44 +#define REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC 0xc48 +#define REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC 0xc4c +#define REG_BB_TXAGC_A_NSS3INDEX3_NSS3INDEX0_AC 0xce0 +#define REG_BB_TXAGC_A_NSS3INDEX7_NSS3INDEX4_AC 0xce4 +#define REG_BB_TXAGC_A_NSS3INDEX9_NSS3INDEX8_AC 0xce8 + +// DIG-related +#define REG_BB_A_IGI_AC 0xc50 // Initial Gain for path-A +// AFE-related +#define REG_BB_A_AFEPWR1_AC 0xc60 // dynamic AFE power control +#define REG_BB_A_AFEPWR2_AC 0xc64 // dynamic AFE power control +#define REG_BB_A_RX_WAITCCA_TX_CCKRFON_AC 0xc68 +#define REG_BB_A_TX_CCKBBON_OFDMRFON_AC 0xc6c +#define REG_BB_A_TX_OFDMBBON_TX2RX_AC 0xc70 +#define REG_BB_A_TX2TX_RXCCK_AC 0xc74 +#define REG_BB_A_RX_OFDM_WAITRIFS_AC 0xc78 +#define REG_BB_A_RX2RX_BT_AC 0xc7c +#define REG_BB_A_SLEEP_NAV_AC 0xc80 +#define REG_BB_A_PMPD_AC 0xc84 +#define REG_BB_A_LSSIWRITE_AC 0xc90 // RF write addr +#define REG_BB_A_RFE_PINMUX_AC 0xcb0 // Path_A RFE cotrol pinmux +#define REG_BB_A_RFE_AC 0xcb8 // Path_A RFE cotrol + +/**** page d ****/ +#define REG_BB_A_PIREAD_AC 0xd04 // RF readback with PI +#define REG_BB_B_PIREAD_AC 0xd44 // RF readback with PI +#define REG_BB_C_PIREAD_AC 0xd84 // RF readback with PI +#define REG_BB_D_PIREAD_AC 0xdc4 // RF readback with PI +#define REG_BB_A_SIREAD_AC 0xd08 // RF readback with SI +#define REG_BB_B_SIREAD_AC 0xd48 // RF readback with SI +#define REG_BB_C_SIREAD_AC 0xd88 // RF readback with SI +#define REG_BB_D_SIREAD_AC 0xdc8 // RF readback with SI + + +/**** page e ****/ +// RXIQC +#define REG_BB_B_TXSCALE_AC 0xe1c // Path_B TX scaling factor +#define REG_BB_B_RXIQC_AB_AC 0xe10 //RxIQ imblance matrix coeff. A & B +#define REG_BB_B_RXIQC_CD_AC 0xe14 //RxIQ imblance matrix coeff. C & D + +// TX AGC +#define REG_BB_TXAGC_B_CCK11_CCK1_AC 0xe20 +#define REG_BB_TXAGC_B_OFDM18_OFDM6_AC 0xe24 +#define REG_BB_TXAGC_B_OFDM54_OFDM24_AC 0xe28 +#define REG_BB_TXAGC_B_MCS3_MCS0_AC 0xe2c +#define REG_BB_TXAGC_B_MCS7_MCS4_AC 0xe30 +#define REG_BB_TXAGC_B_MCS11_MCS8_AC 0xe34 +#define REG_BB_TXAGC_B_MCS15_MCS12_AC 0xe38 +#define REG_BB_TXAGC_B_MCS19_MCS16_AC 0xed8 +#define REG_BB_TXAGC_B_MCS23_MCS20_AC 0xedc +#define REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC 0xe3c +#define REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC 0xe40 +#define REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC 0xe44 +#define REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC 0xe48 +#define REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC 0xe4c +#define REG_BB_TXAGC_B_NSS3INDEX3_NSS3INDEX0_AC 0xee0 +#define REG_BB_TXAGC_B_NSS3INDEX7_NSS3INDEX4_AC 0xee4 +#define REG_BB_TXAGC_B_NSS3INDEX9_NSS3INDEX8_AC 0xee8 + +// DIG-related +#define REG_BB_B_IGI_AC 0xe50 // Initial Gain for path-B +#define REG_BB_B_LSSIWRITE_AC 0xe90 // RF write addr + +// Misc functions +#define REG_BB_B_RFE_PINMUX_AC 0xeb0 // Path_B RFE control pinmux +#define REG_BB_B_RFE_AC 0xeb8 // Path_B RFE control + +/**** page f ****/ +// DIG-related +#define REG_BB_OFDM_FALSEALARM1_AC 0xf48 // counter for break +#define REG_BB_OFDM_FALSEALARM2_AC 0xf4c // counter for spoofing +// Report-related +#define REG_BB_OFDM_SHORTCFOAB_AC 0xf60 +#define REG_BB_OFDM_LONGCFOAB_AC 0xf64 +#define REG_BB_OFDM_ENDCFOAB_AC 0xf70 +#define REG_BB_OFDM_AGCREPORT_AC 0xf84 +#define REG_BB_OFDM_RXSNR_AC 0xf88 +#define REG_BB_OFDM_RXEVMCSI_AC 0xf8c +#define REG_BB_OFDM_SIGREPORT_AC 0xf90 + +/**** page 18 ****/ +// TX AGC +#define REG_BB_TXAGC_C_CCK11_CCK1_AC 0x1820 +#define REG_BB_TXAGC_C_OFDM18_OFDM6_AC 0x1824 +#define REG_BB_TXAGC_C_OFDM54_OFDM24_AC 0x1828 +#define REG_BB_TXAGC_C_MCS3_MCS0_AC 0x182c +#define REG_BB_TXAGC_C_MCS7_MCS4_AC 0x1830 +#define REG_BB_TXAGC_C_MCS11_MCS8_AC 0x1834 +#define REG_BB_TXAGC_C_MCS15_MCS12_AC 0x1838 +#define REG_BB_TXAGC_C_MCS19_MCS16_AC 0x18d8 +#define REG_BB_TXAGC_C_MCS23_MCS20_AC 0x18dc +#define REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC 0x183c +#define REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC 0x1840 +#define REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC 0x1844 +#define REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC 0x1848 +#define REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC 0x184c +#define REG_BB_TXAGC_C_NSS3INDEX3_NSS3INDEX0_AC 0x18e0 +#define REG_BB_TXAGC_C_NSS3INDEX7_NSS3INDEX4_AC 0x18e4 +#define REG_BB_TXAGC_C_NSS3INDEX9_NSS3INDEX8_AC 0x18e8 + +#define REG_BB_C_LSSIWRITE_AC 0x1890 // RF write addr +#define REG_BB_C_RFE_PINMUX_AC 0x18b4 // Path_C RFE control pinmux + +/**** page 19 ****/ +//TX BeamForming +#define REG_BB_TXBF_ANT_SET_BF1 0x19ac +#define REG_BB_TXBF_ANT_SET_BF0 0x19b4 + + +/**** page 1a ****/ +// TX AGC +#define REG_BB_TXAGC_D_CCK11_CCK1_AC 0x1a20 +#define REG_BB_TXAGC_D_OFDM18_OFDM6_AC 0x1a24 +#define REG_BB_TXAGC_D_OFDM54_OFDM24_AC 0x1a28 +#define REG_BB_TXAGC_D_MCS3_MCS0_AC 0x1a2c +#define REG_BB_TXAGC_D_MCS7_MCS4_AC 0x1a30 +#define REG_BB_TXAGC_D_MCS11_MCS8_AC 0x1a34 +#define REG_BB_TXAGC_D_MCS15_MCS12_AC 0x1a38 +#define REG_BB_TXAGC_D_MCS19_MCS16_AC 0x1ad8 +#define REG_BB_TXAGC_D_MCS23_MCS20_AC 0x1adc +#define REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC 0x1a3c +#define REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC 0x1a40 +#define REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC 0x1a44 +#define REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC 0x1a48 +#define REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC 0x1a4c +#define REG_BB_TXAGC_D_NSS3INDEX3_NSS3INDEX0_AC 0x1ae0 +#define REG_BB_TXAGC_D_NSS3INDEX7_NSS3INDEX4_AC 0x1ae4 +#define REG_BB_TXAGC_D_NSS3INDEX9_NSS3INDEX8_AC 0x1ae8 + +#define REG_BB_D_LSSIWRITE_AC 0x1a90 // RF write addr +#define REG_BB_D_RFE_PINMUX_AC 0x1ab4 // Path_D RFE control pinmux + + +////////////////////////////////////// + + + + +// RF Register +// +#define REG_RF_AC_AC 0x00 +#define REG_RF_RF_TOP_AC 0x07 +#define REG_RF_TXLOK_AC 0x08 +#define REG_RF_TXAPK_AC 0x0B +#define REG_RF_CHNLBW_AC 0x18 // RF channel and BW switch +#define REG_RF_TXLCTANK_AC 0x54 +#define REG_RF_APK_AC 0x63 +#define REG_BRF_CHNLBW_MOD_AG_AC 0x70300 +#define REG_BRF_CHNLBW_BW_AC 0xc00 +#define REG_RF_RCK1_AC 0x1c +#define REG_RF_RCK2_AC 0x1d +#define REG_RF_RCK3_AC 0x1e +#define REG_RF_LCK_AC 0xB4 +#define REG_BB_BRFREGOFFSETMASK_AC 0xfffff + +// TX AGC V2 - 8814A MP +#define REG_BB_TXAGC_V2_BASE_ADDR 0x1998 + +/* +Example: +0x1998 = 0x12801151 +0x1998[7:0]=0x51: TX_RATE VHT 4ss mcs7 +0x1998[9:8]=path_idx=1: path B (path A/B/C/D -> 0/1/2/3) +0x1998[12]¢FDy3¢FG?n1, |b8813!LS|3!¡Ó@¢FDI. +0x1998[23]=1: write +0x1998[31:24]=0x12: txagc codeword +*/ + +#define BIT_SHIFT_BB_TXAGC_V2_TX_RATE 0 +#define BIT_MASK_BB_TXAGC_V2_TX_RATE 0xff +#define BIT_BB_TXAGC_V2_TX_RATE(x) (((x) & BIT_MASK_BB_TXAGC_V2_TX_RATE) << BIT_SHIFT_BB_TXAGC_V2_TX_RATE) + +#define BIT_SHIFT_BB_TXAGC_V2_PATH_IDX 8 +#define BIT_MASK_BB_TXAGC_V2_PATH_IDX 0x3 +#define BIT_BB_TXAGC_V2_PATH_IDX(x) (((x) & BIT_MASK_BB_TXAGC_V2_PATH_IDX) << BIT_SHIFT_BB_TXAGC_V2_PATH_IDX) + +#define BIT_SHIFT_BB_TXAGC_V2_NONE 12 +#define BIT_MASK_BB_TXAGC_V2_NONE 0x1 +#define BIT_BB_TXAGC_V2_NONE(x) (((x) & BIT_MASK_BB_TXAGC_V2_NONE) << BIT_SHIFT_BB_TXAGC_V2_NONE) + +#define BIT_SHIFT_BB_TXAGC_V2_WRITE 23 +#define BIT_MASK_BB_TXAGC_V2_WRITE 0x1 +#define BIT_BB_TXAGC_V2_WRITE(x) (((x) & BIT_MASK_BB_TXAGC_V2_WRITE) << BIT_SHIFT_BB_TXAGC_V2_WRITE) + +#define BIT_SHIFT_BB_TXAGC_V2_CODEWORD 24 +#define BIT_MASK_BB_TXAGC_V2_CODEWORD 0xff +#define BIT_BB_TXAGC_V2_CODEWORD(x) (((x) & BIT_MASK_BB_TXAGC_V2_CODEWORD) << BIT_SHIFT_BB_TXAGC_V2_CODEWORD) + +#define FILL_REG_BB_TXAGC_V2(RATE, PATH_IDX, NONE_VALUE, WRITE_VALUE, DEF_POWER) (BIT_BB_TXAGC_V2_TX_RATE(RATE) | BIT_BB_TXAGC_V2_PATH_IDX(PATH_IDX) | BIT_BB_TXAGC_V2_NONE(NONE_VALUE) | BIT_BB_TXAGC_V2_WRITE(WRITE_VALUE) | BIT_BB_TXAGC_V2_CODEWORD(DEF_POWER)) + +#define TX_AGC_CCK_1M 0x00 +#define TX_AGC_CCK_2M 0x01 +#define TX_AGC_CCK_5_5M 0x02 +#define TX_AGC_CCK_11M 0x03 +#define TX_AGC_OFDM_6M 0x04 +#define TX_AGC_OFDM_9M 0x05 +#define TX_AGC_OFDM_12M 0x06 +#define TX_AGC_OFDM_18M 0x07 +#define TX_AGC_OFDM_24M 0x08 +#define TX_AGC_OFDM_36M 0x09 +#define TX_AGC_OFDM_48M 0x0A +#define TX_AGC_OFDM_54M 0x0B + +#define TX_AGC_HT_NSS1_MCS0 0x0C +#define TX_AGC_HT_NSS1_MCS1 0x0D +#define TX_AGC_HT_NSS1_MCS2 0x0E +#define TX_AGC_HT_NSS1_MCS3 0x0F +#define TX_AGC_HT_NSS1_MCS4 0x10 +#define TX_AGC_HT_NSS1_MCS5 0x11 +#define TX_AGC_HT_NSS1_MCS6 0x12 +#define TX_AGC_HT_NSS1_MCS7 0x13 +#define TX_AGC_HT_NSS2_MCS8 0x14 +#define TX_AGC_HT_NSS2_MCS9 0x15 +#define TX_AGC_HT_NSS2_MCS10 0x16 +#define TX_AGC_HT_NSS2_MCS11 0x17 +#define TX_AGC_HT_NSS2_MCS12 0x18 +#define TX_AGC_HT_NSS2_MCS13 0x19 +#define TX_AGC_HT_NSS2_MCS14 0x1A +#define TX_AGC_HT_NSS2_MCS15 0x1B +#define TX_AGC_HT_NSS3_MCS16 0x1C +#define TX_AGC_HT_NSS3_MCS17 0x1D +#define TX_AGC_HT_NSS3_MCS18 0x1E +#define TX_AGC_HT_NSS3_MCS19 0x1F +#define TX_AGC_HT_NSS3_MCS20 0x20 +#define TX_AGC_HT_NSS3_MCS21 0x21 +#define TX_AGC_HT_NSS3_MCS22 0x22 +#define TX_AGC_HT_NSS3_MCS23 0x23 +#define TX_AGC_HT_NSS4_MCS24 0x24 +#define TX_AGC_HT_NSS4_MCS25 0x25 +#define TX_AGC_HT_NSS4_MCS26 0x26 +#define TX_AGC_HT_NSS4_MCS27 0x27 +#define TX_AGC_HT_NSS4_MCS28 0x28 +#define TX_AGC_HT_NSS4_MCS29 0x29 +#define TX_AGC_HT_NSS4_MCS30 0x2A +#define TX_AGC_HT_NSS4_MCS31 0x2B + +#define TX_AGC_VHT_NSS1_MCS0 0x2C +#define TX_AGC_VHT_NSS1_MCS1 0x2D +#define TX_AGC_VHT_NSS1_MCS2 0x2E +#define TX_AGC_VHT_NSS1_MCS3 0x2F +#define TX_AGC_VHT_NSS1_MCS4 0x30 +#define TX_AGC_VHT_NSS1_MCS5 0x31 +#define TX_AGC_VHT_NSS1_MCS6 0x32 +#define TX_AGC_VHT_NSS1_MCS7 0x33 +#define TX_AGC_VHT_NSS1_MCS8 0x34 +#define TX_AGC_VHT_NSS1_MCS9 0x35 +#define TX_AGC_VHT_NSS2_MCS0 0x36 +#define TX_AGC_VHT_NSS2_MCS1 0x37 +#define TX_AGC_VHT_NSS2_MCS2 0x38 +#define TX_AGC_VHT_NSS2_MCS3 0x39 +#define TX_AGC_VHT_NSS2_MCS4 0x3A +#define TX_AGC_VHT_NSS2_MCS5 0x3B +#define TX_AGC_VHT_NSS2_MCS6 0x3C +#define TX_AGC_VHT_NSS2_MCS7 0x3D +#define TX_AGC_VHT_NSS2_MCS8 0x3E +#define TX_AGC_VHT_NSS2_MCS9 0x3F +#define TX_AGC_VHT_NSS3_MCS0 0x40 +#define TX_AGC_VHT_NSS3_MCS1 0x41 +#define TX_AGC_VHT_NSS3_MCS2 0x42 +#define TX_AGC_VHT_NSS3_MCS3 0x43 +#define TX_AGC_VHT_NSS3_MCS4 0x44 +#define TX_AGC_VHT_NSS3_MCS5 0x45 +#define TX_AGC_VHT_NSS3_MCS6 0x46 +#define TX_AGC_VHT_NSS3_MCS7 0x47 +#define TX_AGC_VHT_NSS3_MCS8 0x48 +#define TX_AGC_VHT_NSS3_MCS9 0x49 +#define TX_AGC_VHT_NSS4_MCS0 0x4A +#define TX_AGC_VHT_NSS4_MCS1 0x4B +#define TX_AGC_VHT_NSS4_MCS2 0x4C +#define TX_AGC_VHT_NSS4_MCS3 0x4D +#define TX_AGC_VHT_NSS4_MCS4 0x4E +#define TX_AGC_VHT_NSS4_MCS5 0x4F +#define TX_AGC_VHT_NSS4_MCS6 0x50 +#define TX_AGC_VHT_NSS4_MCs7 0x51 +#define TX_AGC_VHT_NSS4_MCS8 0x52 +#define TX_AGC_VHT_NSS4_MCS9 0x53 + +//eric-8814 +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF + + +#endif //#if IS_RTL88XX_AC + + +#if IS_RTL88XX_N + +// +// 2. BB Register Page8(0x800) +// +#define REG_BB_FPGA0_RFMOD_N 0x800 //RF mode & CCK TxSC // RF BW Setting?? +#define REG_BB_FPGA0_TXINFO_N 0x804 // Status report?? +#define REG_BB_FPGA0_PSDFUNCTION_N 0x808 +#define REG_BB_FPGA0_TXGAINSTAGE_N 0x80c // Set TX PWR init gain? +#define REG_BB_FPGA0_RFTIMING1_N 0x810 // Useless now +#define REG_BB_FPGA0_RFTIMING2_N 0x814 +#define REG_BB_PRIMESC_N 0x818 + +#define REG_BB_FPGA0_XA_HSSIPARAMETER1_N 0x820 // RF 3 wire register +#define REG_BB_FPGA0_XA_HSSIPARAMETER2_N 0x824 +#define REG_BB_FPGA0_XB_HSSIPARAMETER1_N 0x828 +#define REG_BB_FPGA0_XB_HSSIPARAMETER2_N 0x82c +#define REG_BB_TXAGC_B_RATE18_06_N 0x830 +#define REG_BB_TXAGC_B_RATE54_24_N 0x834 +#define REG_BB_TXAGC_B_CCK5_1_MCS32_N 0x838 +#define REG_BB_TXAGC_B_MCS03_MCS00_N 0x83c +#define REG_BB_FPGA0_XA_LSSIPARAMETER_N 0x840 +#define REG_BB_FPGA0_XB_LSSIPARAMETER_N 0x844 +#define REG_BB_TXAGC_B_MCS07_MCS04_N 0x848 +#define REG_BB_TXAGC_B_MCS11_MCS08_N 0x84c +#define REG_BB_FPGA0_RFWAKEUPPARAMETER_N 0x850 // Useless now +#define REG_BB_FPGA0_RFSLEEPUPPARAMETER_N 0x854 +#define REG_BB_FPGA0_XAB_SWITCHCONTROL_N 0x858 // RF Channel switch +#define REG_BB_FPGA0_XCD_SWITCHCONTROL_N 0x85c +#define REG_BB_FPGA0_XA_RFINTERFACEOE_N 0x860 // RF Channel switch +#define REG_BB_FPGA0_XB_RFINTERFACEOE_N 0x864 +#define REG_BB_TXAGC_B_MCS15_MCS12_N 0x868 +#define REG_BB_TXAGC_A_CCK11_2_B_CCK11_N 0x86c +#define REG_BB_FPGA0_XAB_RFINTERFACESW_N 0x870 // RF Interface Software Control +#define REG_BB_FPGA0_XCD_RFINTERFACESW_N 0x874 +#define REG_BB_FPGA0_XAB_RFPARAMETER_N 0x878 // RF Parameter +#define REG_BB_FPGA0_XCD_RFPARAMETER_N 0x87c +#define REG_BB_FPGA0_ANALOGPARAMETER1_N 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define REG_BB_FPGA0_ANALOGPARAMETER2_N 0x884 +#define REG_BB_FPGA0_ANALOGPARAMETER3_N 0x888 // Useless now +#define REG_BB_FPGA0_ANALOGPARAMETER4_N 0x88c +#define REG_BB_FPGA0_XA_LSSIREADBACK_N 0x8a0 // Tranceiver LSSI Readback +#define REG_BB_FPGA0_XB_LSSIREADBACK_N 0x8a4 + +#define REG_BB_FPGA0_PSDREPORT_N 0x8b4 // Useless now +#define REG_BB_TRANSCEIVERA_HSPI_READBACK_N 0x8b8 +#define REG_BB_TRANSCEIVERB_HSPI_READBACK_N 0x8bc +#define REG_BB_FPGA0_XAB_RFINTERFACERB_N 0x8e0 // Useless now // RF Interface Readback Value + + + +// +// 3. BB Register Page9(0x900) +// +#define REG_BB_FPGA1_RFMOD_N 0x900 //RF mode & OFDM TxSC // RF BW Setting?? +#define REG_BB_FPGA1_TXBLOCK_N 0x904 // Useless now +#define REG_BB_FPGA1_DEBUGSELECT_N 0x908 // Useless now +#define REG_BB_FPGA1_TXINFO_N 0x90c // Useless now // Status report?? + + +// +// 4. BB Register PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define REG_BB_CCK0_SYSTEM_N 0xa00 +#define REG_BB_CCK0_AFESETTING_N 0xa04 // Disable init gain now // Select RX path by RSSI +#define REG_BB_CCK0_CCA_N 0xa08 // Disable init gain now // Init gain +#define REG_BB_CCK0_RXAGC1_N 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define REG_BB_CCK0_RXAGC2_N 0xa10 //AGC & DAGC +#define REG_BB_CCK0_RXHP_N 0xa14 +#define REG_BB_CCK0_DSPPARAMETER1_N 0xa18 //Timing recovery & Channel estimation threshold +#define REG_BB_CCK0_DSPPARAMETER2_N 0xa1c //SQ threshold +#define REG_BB_CCK0_TXFILTER1_N 0xa20 +#define REG_BB_CCK0_TXFILTER2_N 0xa24 +#define REG_BB_CCK0_DEBUGPORT_N 0xa28 //debug port and Tx filter3 +#define REG_BB_CCK0_FALSEALARMREPORT_N 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define REG_BB_CCK0_TRSSIREPORT_N 0xa50 +#define REG_BB_CCK0_RXREPORT_N 0xa54 //0xa57 +#define REG_BB_CCK0_FACOUNTERLOWER_N 0xa5c //0xa5b +#define REG_BB_CCK0_FACOUNTERUPPER_N 0xa58 //0xa5c + + +// +// 5. BB Register PageC(0xC00) +// +#define REG_BB_OFDM0_LSTF_N 0xc00 +#define REG_BB_OFDM0_TRXPATHENABLE_N 0xc04 +#define REG_BB_OFDM0_TRMUXPAR_N 0xc08 +#define REG_BB_OFDM0_TRSWISOLATION_N 0xc0c +#define REG_BB_OFDM0_XARXAFE_N 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define REG_BB_OFDM0_XARXIQIMBALANCE_N 0xc14 //RxIQ imblance matrix +#define REG_BB_OFDM0_XBRXAFE_N 0xc18 +#define REG_BB_OFDM0_XBRXIQIMBALANCE_N 0xc1c +/* +#define REG_BB_OFDM0_XCRXAFE_N 0xc20 +#define REG_BB_OFDM0_XCRXIQIMBALANCE_N 0xc24 +#define REG_BB_OFDM0_XDRXAFE_N 0xc28 +#define REG_BB_OFDM0_XDRXIQIMBALANCE_N 0xc2c +*/ +#define REG_BB_OFDM0_RXDETECTOR1_N 0xc30 //PD,BW & SBD // DM tune init gain +#define REG_BB_OFDM0_RXDETECTOR2_N 0xc34 //SBD & Fame Sync. +#define REG_BB_OFDM0_RXDETECTOR3_N 0xc38 //Frame Sync. +#define REG_BB_OFDM0_RXDETECTOR4_N 0xc3c //PD, SBD, Frame Sync & Short-GI +#define REG_BB_OFDM0_RXDSP_N 0xc40 //Rx Sync Path +#define REG_BB_OFDM0_CFOANDDAGC_N 0xc44 //CFO & DAGC +#define REG_BB_OFDM0_CCADROPTHRESHOLD_N 0xc48 //CCA Drop threshold +#define REG_BB_OFDM0_ECCATHRESHOLD_N 0xc4c // energy CCA +#define REG_BB_OFDM0_XAAGCCORE1_N 0xc50 // DIG +#define REG_BB_OFDM0_XAAGCCORE2_N 0xc54 +#define REG_BB_OFDM0_XBAGCCORE1_N 0xc58 +#define REG_BB_OFDM0_XBAGCCORE2_N 0xc5c +/* +#define REG_BB_OFDM0_XCAGCCORE1_N 0xc60 +#define REG_BB_OFDM0_XCAGCCORE2_N 0xc64 +#define REG_BB_OFDM0_XDAGCCORE1_N 0xc68 +#define REG_BB_OFDM0_XDAGCCORE2_N 0xc6c +*/ +#define REG_BB_OFDM0_AGCPARAMETER1_N 0xc70 +#define REG_BB_OFDM0_AGCPARAMETER2_N 0xc74 +#define REG_BB_OFDM0_AGCRSSITABLE_N 0xc78 +#define REG_BB_OFDM0_HTSTFAGC_N 0xc7c +#define REG_BB_OFDM0_XATXIQIMBALANC_N 0xc80 // TX PWR TRACK and DIG +#define REG_BB_OFDM0_XATXAFE_N 0xc84 +#define REG_BB_OFDM0_XBTXIQIMBALANCE_N 0xc88 +#define REG_BB_OFDM0_XBTXAFE_N 0xc8c + + +#define REG_BB_OFDM0_XCTXIQIMBALANCE_N 0xc90 +#define REG_BB_OFDM0_XCTXAFE_N 0xc94 +#define REG_BB_OFDM0_XDTXIQIMBALANCE_N 0xc98 +#define REG_BB_OFDM0_XDTXAFE_N 0xc9c +#define REG_BB_OFDM0_RXIQEXTANTA_N 0xca0 + + +#define REG_BB_OFDM0_RXHPPARAMETER_N 0xce0 +#define REG_BB_OFDM0_TXPSEUDONOISEWGT_N 0xce4 +#define REG_BB_OFDM0_FRAMESYNC_N 0xcf0 +#define REG_BB_OFDM0_DFSREPORT_N 0xcf4 +#define REG_BB_OFDM0_TXCOEFF1_N 0xca4 +#define REG_BB_OFDM0_TXCOEFF2_N 0xca8 +#define REG_BB_OFDM0_TXCOEFF3_N 0xcac +#define REG_BB_OFDM0_TXCOEFF4_N 0xcb0 +#define REG_BB_OFDM0_TXCOEFF5_N 0xcb4 +#define REG_BB_OFDM0_TXCOEFF6_N 0xcb8 + + +// +// 6. BB Register PageD(0xD00) +// +#define REG_BB_OFDM1_LSTF_N 0xd00 +#define REG_BB_OFDM1_TRXPATHENABLE_N 0xd04 +#define REG_BB_OFDM1_CFO_N 0xd08 // No setting now +#define REG_BB_OFDM1_CSI1_N 0xd10 +#define REG_BB_OFDM1_SBD_N 0xd14 +#define REG_BB_OFDM1_CSI2_N 0xd18 +#define REG_BB_OFDM1_CFOTRACKING_N 0xd2c +#define REG_BB_OFDM1_TRXMESAURE1_N 0xd34 +#define REG_BB_OFDM1_INTFDET_N 0xd3c +#define REG_BB_OFDM1_PSEUDONOISESTATEAB_N 0xd50 +#define REG_BB_OFDM1_PSEUDONOISESTATECD_N 0xd54 +#define REG_BB_OFDM1_RXPSEUDONOISEWGT_N 0xd58 +#define REG_BB_OFDM_PHYCOUNTER1_N 0xda0 //cca, parity fail +#define REG_BB_OFDM_PHYCOUNTER2_N 0xda4 //rate illegal, crc8 fail +#define REG_BB_OFDM_PHYCOUNTER3_N 0xda8 //MCS not support +#define REG_BB_OFDM_SHORTCFOAB_N 0xdac // No setting now +#define REG_BB_OFDM_SHORTCFOCD_N 0xdb0 +#define REG_BB_OFDM_LONGCFOAB_N 0xdb4 +#define REG_BB_OFDM_LONGCFOCD_N 0xdb8 +#define REG_BB_OFDM_TAILCFOAB_N 0xdbc +#define REG_BB_OFDM_TAILCFOCD_N 0xdc0 +#define REG_BB_OFDM_PWMEASURE1_N 0xdc4 +#define REG_BB_OFDM_PWMEASURE2_N 0xdc8 +#define REG_BB_OFDM_BWREPORT_N 0xdcc +#define REG_BB_OFDM_AGCREPORT_N 0xdd0 +#define REG_BB_OFDM_RXSNR_N 0xdd4 +#define REG_BB_OFDM_RXEVMCSI_N 0xdd8 +#define REG_BB_OFDM_SIGREPORT_N 0xddc + + +// +// 6. BB Register PageE(0xE00) +// +#define REG_BB_TXAGC_A_RATE18_06_N 0xe00 +#define REG_BB_TXAGC_A_RATE54_24_N 0xe04 +#define REG_BB_TXAGC_A_CCK1_MCS32_N 0xe08 +#define REG_BB_TXAGC_A_MCS03_MCS00_N 0xe10 +#define REG_BB_TXAGC_A_MCS07_MCS04_N 0xe14 +#define REG_BB_TXAGC_A_MCS11_MCS08_N 0xe18 +#define REG_BB_TXAGC_A_MCS15_MCS12_N 0xe1c + + +// +// 7. RF Register 0x00-0x2E +// +//Zebra1 +#define REG_RF_ZEBRA1_HSSIENABLE_N 0x0 // Useless now +#define REG_RF_ZEBRA1_TRXENABLE1_N 0x1 +#define REG_RF_ZEBRA1_TRXENABLE2_N 0x2 +#define REG_RF_ZEBRA1_AGC_N 0x4 +#define REG_RF_ZEBRA1_CHARGEPUMP_N 0x5 +#define REG_RF_ZEBRA1_CHANNEL_N 0x7 // RF channel switch +#define REG_RF_ZEBRA1_TXGAIN_N 0x8 // Useless now +#define REG_RF_ZEBRA1_TXLPF_N 0x9 +#define REG_RF_ZEBRA1_RXLPF_N 0xb +#define REG_RF_ZEBRA1_RXHPFCORNER_N 0xc +#define REG_RF_RFCHANNEL_N 0x18 // RF channel switch For T65 RF 0222d +#define REG_RF_CSI_MASK_N 0x42 + +//Zebra4 +#define REG_RF_GLOBALCTRL_N 0 // Useless now +#define REG_RF_RTL8256_TXLPF_N 19 +#define REG_RF_RTL8256_RXLPF_N 11 + +//RTL8258 +#define REG_RF_RTL8258_RSSILPF_N 0xa +#define REG_RF_RTL8258_TXLPF_N 0x11 // Useless now +#define REG_RF_RTL8258_RXLPF_N 0x13 + +// 92E temp +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF + +#define REG_BFMEE_SEL_8192E 0x0714 +#define REG_SND_PTCL_CTRL_8192E 0x0718 +#define REG_BFMER0_INFO_8192E 0x06E4 +#define REG_BFMER1_INFO_8192E 0x06EC +#define REG_CSI_RPT_PARAM_BW20_92E 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_92E 0x06F8 + +#endif //#if IS_RTL88XX_N +#endif //#ifndef __INC_HALCOMPHYREG_BB_H + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComRXDesc.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComRXDesc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComReg.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComReg.h old mode 100755 new mode 100644 index d5e0e225583..5f9f3492eba --- a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComReg.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComReg.h @@ -1,1927 +1,1927 @@ -#ifndef __HAL_COM_REG_H__ -#define __HAL_COM_REG_H__ -/*-------------------------Modification Log----------------------------------- - For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524 - The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A - 8812A and 8188E is not included in page0 register - - For other pages, it is based on MAC_Register.doc SVN502 - Most IC is the same with 8812A --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ -#include "HalHWCfg.h" -/*--------------------------Include File--------------------------------------*/ - - - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - - #define REG_SYS_ISO_CTRL 0x0000 - #define REG_SYS_FUNC_EN 0x0002 - #define REG_SYS_PW_CTRL 0x0004 - #define REG_SYS_CLK_CTRL 0x0008 - #define REG_SYS_EEPROM_CTRL 0x000A - #define REG_EE_VPD 0x000C - #define REG_SYS_SWR_CTRL1 0x0010 - #define REG_SYS_SWR_CTRL2 0x0014 - #define REG_SYS_SWR_CTRL3 0x0018 - #define REG_RSV_CTRL 0x001C - #define REG_RF_CTRL 0x001F - #define REG_AFE_LDO_CTRL 0x0020 - #define REG_AFE_CTRL1 0x0024 - #define REG_AFE_CTRL2 0x0028 - #define REG_AFE_CTRL3 0x002C - #define REG_EFUSE_CTRL 0x0030 - #define REG_LDO_EFUSE_CTRL 0x0034 - #define REG_PWR_OPTION_CTRL 0x0038 - #define REG_CAL_TIMER 0x003C - #define REG_ACLK_MON 0x003E - #define REG_GPIO_MUXCFG 0x0040 - #define REG_GPIO_PIN_CTRL 0x0044 - #define REG_GPIO_INTM 0x0048 - #define REG_LED_CFG 0x004C - #define REG_FSIMR 0x0050 - #define REG_FSISR 0x0054 - #define REG_HSIMR 0x0058 - #define REG_HSISR 0x005C - #define REG_GPIO_EXT_CTRL 0x0060 - #define REG_PAD_CTRL1 0x0064 - #define REG_WL_BT_PWR_CTRL 0x0068 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - - #define REG_SDM_DEBUG 0x006C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_GSSR 0x006C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - - #define REG_SDIO_CTRL 0x0070 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_SYS_CLKR 0x0070 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - - #define REG_HCI_OPT_CTRL 0x0074 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - - #define REG_AFE_CTRL4 0x0078 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_AFE_XTAL_CTRL_EXT 0x0078 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - - #define REG_LDO_SWR_CTRL 0x007C - #define REG_8051FW_CTRL 0x0080 - #define REG_MCU_TST_CFG 0x0084 - #define REG_HMEBOX_E0_E1 0x0088 - #define REG_HMEBOX_E2_E3 0x008C - #define REG_WLLPS_CTRL 0x0090 - #define REG_GPIO_DEBOUNCE_CTRL 0x0098 - #define REG_RPWM2 0x009C - #define REG_SYSON_FSM_MON 0x00A0 - #define REG_PMC_DBG_CTRL1 0x00A8 - #define REG_HIMR0 0x00B0 - #define REG_HISR0 0x00B4 - #define REG_HIMR1 0x00B8 - #define REG_HISR1 0x00BC - #define REG_DBG_PORT_SEL 0x00C0 - #define REG_PAD_CTRL2 0x00C4 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_MEM_RMC 0x00C8 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - - #define REG_PMC_DBG_CTRL2 0x00CC - #define REG_BIST_CTRL 0x00D0 - #define REG_BIST_RPT 0x00D4 - #define REG_MEM_CTRL 0x00D8 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WLAN_DBG 0x00DC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - - #define REG_USB_SIE_INTF 0x00E0 - #define REG_PCIE_MIO_INTF 0x00E4 - #define REG_PCIE_MIO_INTD 0x00E8 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_HPON_FSM 0x00EC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SYS_CFG1 0x00F0 -#define REG_SYS_STATUS1 0x00F4 -#define REG_SYS_STATUS2 0x00F8 -#define REG_SYS_CFG2 0x00FC -#define REG_CR 0x0100 -#define REG_PBP 0x0104 -#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 -#define REG_TSF_CLK_STATE 0x0108 -#define REG_TXDMA_PQ_MAP 0x010C -#define REG_TRXFF_BNDY 0x0114 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PTA_I2C_MBOX 0x0118 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FF_STATUS 0x0118 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RXFF_PTR 0x011C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_FEIMR 0x0120 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FE1IMR 0x0120 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_FEISR 0x0124 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FE1ISR 0x0124 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_CPWM 0x012C -#define REG_FWIMR 0x0130 -#define REG_FWISR 0x0134 -#define REG_FTIMR 0x0138 -#define REG_FTISR 0x013C -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 -#define REG_CPWM2 0x014C -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015C -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_TC5_CTRL 0x0168 -#define REG_TC6_CTRL 0x016C -#define REG_MBIST_FAIL 0x0170 -#define REG_MBIST_START_PAUSE 0x0174 -#define REG_MBIST_DONE 0x0178 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_MBIST_ROM_CRC_DATA 0x017C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_MBIST_FAIL_NRML 0x017C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_AES_DECRPT_DATA 0x0180 -#define REG_AES_DECRPT_CFG 0x0184 -#define REG_TMETER 0x0190 -#define REG_OSC_32K_CTRL 0x0194 -#define REG_32K_CAL_REG1 0x0198 -#define REG_C2HEVT 0x01A0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_TC7_CTRL 0x01B0 -#define REG_TC8_CTRL 0x01B4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SW_DEFINED_PAGE1 0x01B8 -#define REG_MCUTST_I 0x01C0 -#define REG_MCUTST_II 0x01C4 -#define REG_FMETHR 0x01C8 -#define REG_HMETFR 0x01CC -#define REG_HMEBOX0 0x01D0 -#define REG_HMEBOX1 0x01D4 -#define REG_HMEBOX2 0x01D8 -#define REG_HMEBOX3 0x01DC -#define REG_LLT_INIT 0x01E0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_GENTST 0x01E4 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_LLT_INIT_ADDR 0x01E4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BB_ACCESS_CTRL 0x01E8 -#define REG_BB_ACCESS_DATA 0x01EC -#define REG_HMEBOX_E0 0x01F0 -#define REG_HMEBOX_E1 0x01F4 -#define REG_HMEBOX_E2 0x01F8 -#define REG_HMEBOX_E3 0x01FC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RQPN_CTRL_HLPQ 0x0200 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FIFOPAGE_CTRL_1 0x0200 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_FIFOPAGE_INFO 0x0204 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FIFOPAGE_CTRL_2 0x0204 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_DWBCN0_CTRL 0x0208 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_AUTO_LLT_V1 0x0208 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TXDMA_OFFSET_CHK 0x020C -#define REG_TXDMA_STATUS 0x0210 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RQPN_NPQ 0x0214 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_TX_DMA_DBG 0x0214 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TQPNT1 0x0218 -#define REG_TQPNT2 0x021C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TDE_DEBUG 0x0220 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_TQPNT3 0x0220 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_AUTO_LLT 0x0224 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_TQPNT4 0x0224 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_DWBCN1_CTRL 0x0228 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_RQPN_CTRL_1 0x0228 -#define REG_RQPN_CTRL_2 0x022C -#define REG_FIFOPAGE_INFO_1 0x0230 -#define REG_FIFOPAGE_INFO_2 0x0234 -#define REG_FIFOPAGE_INFO_3 0x0238 -#define REG_FIFOPAGE_INFO_4 0x023C -#define REG_FIFOPAGE_INFO_5 0x0240 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RXDMA_AGG_PG_TH 0x0280 -#define REG_RXPKT_NUM 0x0284 -#define REG_RXDMA_CONTROL 0x0286 -#define REG_RXDMA_STATUS 0x0288 -#define REG_RXDMA_DPR 0x028C -#define REG_RXDMA_MODE 0x0290 -#define REG_C2H_PKT 0x0294 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_PCIE_CTRL 0x0300 - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_LX_CTRL1 0x0300 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_INT_MIG 0x0304 -#define REG_BCNQ_TXBD_DESA 0x0308 -#define REG_MGQ_TXBD_DESA 0x0310 -#define REG_VOQ_TXBD_DESA 0x0318 -#define REG_VIQ_TXBD_DESA 0x0320 -#define REG_BEQ_TXBD_DESA 0x0328 -#define REG_BKQ_TXBD_DESA 0x0330 -#define REG_RXQ_RXBD_DESA 0x0338 -#define REG_HI0Q_TXBD_DESA 0x0340 -#define REG_HI1Q_TXBD_DESA 0x0348 -#define REG_HI2Q_TXBD_DESA 0x0350 -#define REG_HI3Q_TXBD_DESA 0x0358 -#define REG_HI4Q_TXBD_DESA 0x0360 -#define REG_HI5Q_TXBD_DESA 0x0368 -#define REG_HI6Q_TXBD_DESA 0x0370 -#define REG_HI7Q_TXBD_DESA 0x0378 -#define REG_MGQ_TXBD_NUM 0x0380 -#define REG_RX_RXBD_NUM 0x0382 -#define REG_VOQ_TXBD_NUM 0x0384 -#define REG_VIQ_TXBD_NUM 0x0386 -#define REG_BEQ_TXBD_NUM 0x0388 -#define REG_BKQ_TXBD_NUM 0x038A -#define REG_HI0Q_TXBD_NUM 0x038C -#define REG_HI1Q_TXBD_NUM 0x038E -#define REG_HI2Q_TXBD_NUM 0x0390 -#define REG_HI3Q_TXBD_NUM 0x0392 -#define REG_HI4Q_TXBD_NUM 0x0394 -#define REG_HI5Q_TXBD_NUM 0x0396 -#define REG_HI6Q_TXBD_NUM 0x0398 -#define REG_HI7Q_TXBD_NUM 0x039A -#define REG_TSFTIMER_HCI 0x039C -#define REG_BD_RWPTR_CLR 0x039C -#define REG_VOQ_TXBD_IDX 0x03A0 -#define REG_VIQ_TXBD_IDX 0x03A4 -#define REG_BEQ_TXBD_IDX 0x03A8 -#define REG_BKQ_TXBD_IDX 0x03AC -#define REG_MGQ_TXBD_IDX 0x03B0 -#define REG_RXQ_RXBD_IDX 0x03B4 -#define REG_HI0Q_TXBD_IDX 0x03B8 -#define REG_HI1Q_TXBD_IDX 0x03BC -#define REG_HI2Q_TXBD_IDX 0x03C0 -#define REG_HI3Q_TXBD_IDX 0x03C4 -#define REG_HI4Q_TXBD_IDX 0x03C8 -#define REG_HI5Q_TXBD_IDX 0x03CC -#define REG_HI6Q_TXBD_IDX 0x03D0 -#define REG_HI7Q_TXBD_IDX 0x03D4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_DBG_SEL_V1 0x03D8 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PCIE_HRPWM1_V1 0x03D9 -#define REG_PCIE_HCPWM1_V1 0x03DA - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_PCIE_CTRL2 0x03DB - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_LX_CTRL2 0x03DB - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PCIE_HRPWM2_V1 0x03DC -#define REG_PCIE_HCPWM2_V1 0x03DE -#define REG_PCIE_H2C_MSG_V1 0x03E0 -#define REG_PCIE_C2H_MSG_V1 0x03E4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_DBI_WDATA_V1 0x03E8 - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_LX_DMA_ISR 0x03E8 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_DBI_RDATA_V1 0x03EC - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_LX_DMA_IMR 0x03EC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_DBI_FLAG_V1 0x03F0 - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_LX_DMA_DBG 0x03F0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) - -#define REG_MDIO_V1 0x03F4 - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_BUS_MIX_CFG 0x03F8 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_HCI_MIX_CFG 0x03FC - -#endif - - -#if (RTL8881A_SUPPORT) - -#define REG_BUS_MIX_CFG1 0x03FC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_Q0_INFO 0x0400 -#define REG_Q1_INFO 0x0404 -#define REG_Q2_INFO 0x0408 -#define REG_Q3_INFO 0x040C -#define REG_MGQ_INFO 0x0410 -#define REG_HIQ_INFO 0x0414 -#define REG_BCNQ_INFO 0x0418 -#define REG_TXPKT_EMPTY 0x041A -#define REG_CPU_MGQ_INFO 0x041C -#define REG_FWHW_TXQ_CTRL 0x0420 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_HWSEQ_CTRL 0x0423 -#define REG_BCNQ_BDNY 0x0424 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BCNQ_BDNY_V1 0x0424 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_MGQ_BDNY 0x0425 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_LIFETIME_EN 0x0426 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_FW_FREE_TAIL 0x0427 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SPEC_SIFS 0x0428 -#define REG_RETRY_LIMIT 0x042A -#define REG_TXBF_CTRL 0x042C -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RRSR 0x0440 -#define REG_ARFR0 0x0444 -#define REG_ARFR1_V1 0x044C -#define REG_CCK_CHECK 0x0454 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_AMPDU_BURST_CTRL 0x0455 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_AMPDU_MAX_TIME_V1 0x0455 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_AMPDU_MAX_TIME 0x0456 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BCNQ1_BDNY_V1 0x0456 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BCNQ1_BDNY 0x0457 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_AMPDU_MAX_LENGTH 0x0458 -#define REG_ACQ_STOP 0x045C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WMAC_LBK_BUF_HD 0x045D - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_NDPA_RATE 0x045D - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TX_HANG_CTRL 0x045E -#define REG_NDPA_OPT_CTRL 0x045F - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_FAST_EDCA_CTRL 0x0460 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_CMDQ_INFO 0x0464 -#define REG_Q4_INFO 0x0468 -#define REG_Q5_INFO 0x046C -#define REG_Q6_INFO 0x0470 -#define REG_Q7_INFO 0x0474 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WMAC_LBK_BUF_HD_V1 0x0478 -#define REG_MGQ_BDNY_V1 0x047A - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TXRPT_CTRL 0x047C -#define REG_INIRTS_RATE_SEL 0x0480 -#define REG_BASIC_CFEND_RATE 0x0481 -#define REG_STBC_CFEND_RATE 0x0482 -#define REG_DATA_SC 0x0483 -#define REG_MACID_SLEEP3 0x0484 -#define REG_MACID_SLEEP1 0x0488 -#define REG_ARFR2_V1 0x048C -#define REG_ARFR3_V1 0x0494 -#define REG_ARFR4 0x049C -#define REG_ARFR5 0x04A4 -#define REG_TXRPT_START_OFFSET 0x04AC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TRYING_CNT_TH 0x04B0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_POWER_STAGE1 0x04B4 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_POWER_STAGE2 0x04B8 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC -#define REG_PKT_LIFE_TIME 0x04C0 -#define REG_STBC_SETTING 0x04C4 -#define REG_STBC_SETTING2 0x04C5 -#define REG_QUEUE_CTRL 0x04C6 -#define REG_SINGLE_AMPDU_CTRL 0x04C7 -#define REG_PROT_MODE_CTRL 0x04C8 -#define REG_BAR_MODE_CTRL 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT 0x04CF -#define REG_MACID_SLEEP2 0x04D0 -#define REG_MACID_SLEEP 0x04D4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_HW_SEQ0 0x04D8 -#define REG_HW_SEQ1 0x04DA -#define REG_HW_SEQ2 0x04DC -#define REG_HW_SEQ3 0x04DE - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_CSI_SEQ 0x04DE - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_NULL_PKT_STATUS 0x04E0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_NULL_PKT_STATUS_V1 0x04E0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PTCL_ERR_STATUS 0x04E2 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PTCL_PKT_NUM 0x04E3 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PTCL_TX_RPT 0x04F0 -#define REG_DUMMY_PAGE4 0x04FC - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_DUMMY_PAGE4_V1 0x04FC -#define REG_MOREDATA 0x04FE - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS 0x0514 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -#define REG_MBSSID_CTRL 0x0526 -#define REG_P2PPS_CTRL 0x0527 -#define REG_PKT_LIFETIME_CTRL 0x0528 -#define REG_P2PPS_SPEC_STATE 0x052B -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_P2PPS_STATE 0x0543 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 -#define REG_BCN_CTRL 0x0550 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BCN_CTRL1 0x0551 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BCN_CTRL_CLINT0 0x0551 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_MBSSID_BCN_SPACE 0x0554 -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_USTIME_TSF 0x055C -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TSFTR1 0x0568 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_FREERUN_CNT 0x0568 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_ATIMWND1 0x0570 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_ATIMWND1_V1 0x0570 -#define REG_TBTT_PROHIBIT_INFRA 0x0571 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_CTWND 0x0572 -#define REG_BCNIVLCUNT 0x0573 -#define REG_BCNDROPCTRL 0x0574 -#define REG_HGQ_TIMEOUT_PERIOD 0x0575 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 -#define REG_MISC_CTRL 0x0577 -#define REG_BCN_CTRL_CLINT1 0x0578 -#define REG_BCN_CTRL_CLINT2 0x0579 -#define REG_BCN_CTRL_CLINT3 0x057A -#define REG_P2PPS1_SPEC_STATE 0x057C -#define REG_P2PPS1_STATE 0x057D -#define REG_P2PPS2_SPEC_STATE 0x057E -#define REG_P2PPS2_STATE 0x057F - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_PS_TIMER 0x0580 -#define REG_TIMER0 0x0584 -#define REG_TIMER1 0x0588 -#define REG_TBTT_CTN_AREA 0x058C -#define REG_FORCE_BCN_IFS 0x058E -#define REG_TXOP_MIN 0x0590 -#define REG_PRE_BKF_TIME 0x0592 -#define REG_CROSS_TXOP_CTRL 0x0593 -#define REG_ATIMWND2 0x05A0 -#define REG_ATIMWND3 0x05A1 -#define REG_ATIMWND4 0x05A2 -#define REG_ATIMWND5 0x05A3 -#define REG_ATIMWND6 0x05A4 -#define REG_ATIMWND7 0x05A5 -#define REG_ATIMUGT 0x05A6 -#define REG_HIQ_NO_LMT_EN 0x05A7 -#define REG_DTIM_COUNTER_ROOT 0x05A8 -#define REG_DTIM_COUNTER_VAP1 0x05A9 -#define REG_DTIM_COUNTER_VAP2 0x05AA -#define REG_DTIM_COUNTER_VAP3 0x05AB -#define REG_DTIM_COUNTER_VAP4 0x05AC -#define REG_DTIM_COUNTER_VAP5 0x05AD -#define REG_DTIM_COUNTER_VAP6 0x05AE -#define REG_DTIM_COUNTER_VAP7 0x05AF -#define REG_DIS_ATIM 0x05B0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_EARLY_128US 0x05B1 -#define REG_P2PPS1_CTRL 0x05B2 -#define REG_P2PPS2_CTRL 0x05B3 -#define REG_TIMER0_SRC_SEL 0x05B4 -#define REG_NOA_UNIT_SEL 0x05B5 -#define REG_P2POFF_DIS_TXTIME 0x05B7 -#define REG_MBSSID_BCN_SPACE2 0x05B8 -#define REG_MBSSID_BCN_SPACE3 0x05BC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_ACMHWCTRL 0x05C0 -#define REG_ACMRSTCTRL 0x05C1 -#define REG_ACMAVG 0x05C2 -#define REG_VO_ADMTIME 0x05C4 -#define REG_VI_ADMTIME 0x05C6 -#define REG_BE_ADMTIME 0x05C8 -#define REG_EDCA_RANDOM_GEN 0x05CC -#define REG_TXCMD_NOA_SEL 0x05CF -#define REG_NOA_PARAM 0x05E0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_NOA_SUBIE 0x05ED - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_P2P_RST 0x05F0 -#define REG_SCHEDULER_RST 0x05F1 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SCH_TXCMD 0x05F8 -#define REG_PAGE5_DUMMY 0x05FC -#define REG_WMAC_CR 0x0600 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BWOPMODE 0x0603 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TCR 0x0604 -#define REG_RCR 0x0608 -#define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D -#define REG_RX_DRVINFO_SZ 0x060F -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG_1 0x0628 -#define REG_MBIDCAMCFG_2 0x062C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_MCU_TEST_1 0x0630 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WMAC_TCR_TSFT_OFS 0x0630 -#define REG_UDF_THSD 0x0632 -#define REG_ZLD_NUM 0x0633 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_MCU_TEST_2 0x0634 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_STMP_THSD 0x0634 -#define REG_WMAC_TXTIMEOUT 0x0635 -#define REG_MCU_TEST_2_V1 0x0636 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_USTIME_EDCA 0x0638 -#define REG_MAC_SPEC_SIFS 0x063A -#define REG_RESP_SIFS_CCK 0x063C -#define REG_RESP_SIFS_OFDM 0x063E -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 -#define REG_NAV_CTRL 0x0650 -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WMAC_BACAM_RPMEN 0x0661 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RXERR_RPT 0x0664 -#define REG_WMAC_TRXPTCL_CTL 0x0668 -#define REG_CAMCMD 0x0670 -#define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 -#define REG_CAMDBG 0x067C -#define REG_SECCFG 0x0680 -#define REG_WOW_CTRL 0x0690 -#define REG_PS_RX_INFO 0x0692 -#define REG_WMMPS_UAPSD_TID 0x0693 -#define REG_LPNAV_CTRL 0x0694 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WKFMCAM_NUM 0x0698 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_RWD 0x069C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RXFLTMAP0 0x06A0 -#define REG_RXFLTMAP1 0x06A2 -#define REG_RXFLTMAP 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - - #define REG_FLC_RPC 0x06AC - #define REG_FLC_RPCT 0x06AD - #define REG_FLC_PTS 0x06AE - #define REG_FLC_TRPC 0x06AF - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_RXPKTMON_CTRL 0x06B0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_STATE_MON 0x06B4 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_ERROR_MON 0x06B8 -#define REG_SEARCH_MACID 0x06BC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_COEX_TABLE 0x06C0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_RXCMD_0 0x06D0 -#define REG_RXCMD_1 0x06D4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WMAC_RESP_TXINFO 0x06D8 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BBPSF_CTRL 0x06DC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_P2P_RX_BCN_NOA 0x06E0 -#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO 0x06EC -#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 -#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC -#define REG_MACID1 0x0700 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BSSID1 0x0708 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BCN_PSR_RPT1 0x0710 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_ASSOCIATED_BFMEE_SEL 0x0714 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BEAMFORMEE_SEL 0x0714 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SND_PTCL_CTRL 0x0718 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_SOUNDING_PTCL_CTRL 0x0718 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_RX_CSI_RPT_INFO 0x071C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_RX_CSI_RPT 0x071C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_NS_ARP_CTRL 0x0720 -#define REG_NS_ARP_INFO 0x0724 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_NS_ARP_IPADDR 0x0728 -#define REG_WRITE_RX_CSI_RPT_INFO 0x072C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BEAMFORMING_INFO_NSARP 0x072C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_NS_ARP_IPV6_MYADDR 0x0730 -#define REG_WMAC 0x0750 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_SW 0x0760 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_COEX_V2 0x0762 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_COEX 0x0764 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WLAN_ACT_MSK_CTRL 0x0768 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WLAN_ACT_MASK_CTRL 0x0768 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_STATISTICS_CTRL 0x076E -#define REG_BT_COEX_ENH_INTF_CTRL 0x076E - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_ACT_STATISTICS 0x0770 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_STATISTICS_OTH_CTRL 0x0778 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_Statistics_Control_Register 0x0778 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_CMD_ID 0x077C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_Status_Report_Register 0x077C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT__STATUS_RPT 0x077D -#define REG_BT_DATA 0x0780 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_Interrupt_Control_Register 0x0780 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WLAN_RPT_ 0x0781 -#define REG_BT_ISR_CTRL 0x0783 -#define REG_WLAN_RPT_TO_CTR 0x0784 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_WLAN_Report_Time_Out_Control_Register 0x0784 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_ISOLATION_TABLE 0x0785 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_Isolation_Table_Register_Register 0x0785 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_ISR_STA 0x078F - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_Interrupt_Status_Register 0x078F - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_TDMA_Time_Register 0x0790 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_CH_INFO 0x0794 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_BT_ACT_Register 0x0794 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_BT_STATIC_INFO_EXT 0x0795 -#define REG_LTR_IDLE_LATENCY 0x0798 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_OBFF_CTRL_basic 0x0798 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_LTR_ACTIVE_LATENCY 0x079C - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_OBFF_CTRL2_timer 0x079C - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_OBFF_CTRL 0x07A0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_LTR_CTRL_basic 0x07A0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_LTR_CTRL 0x07A4 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_LTR_CTRL2_timer_threshold 0x07A4 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_LTR_CTRL2 0x07A8 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_LTR_IDLE_latency 0x07A8 -#define REG_LTR_ACTIVE_latency 0x07AC - -#endif - - -#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) - -#define REG_ANTTRN_CTRL 0x07B0 - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_Antenna_Training_Control_Register 0x07B0 - -#endif - - -#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) - -#define REG_WMAC_PKTCNT_RWD 0x07B8 -#define REG_WMAC_PKTCNT_CTRL 0x07BC - -#endif - - -#if (RTL8814A_SUPPORT) - -#define REG_IQ_DUMP 0x07C0 -#define REG_OFDM_CCK_LEN_MASK 0x07D0 -#define REG_NDP_SIG 0x07E0 -#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 -#define REG_CPU_DMEM_CON 0x1080 -#define REG_HIMR2 0x10B0 -#define REG_HISR2 0x10B4 -#define REG_HIMR3 0x10B8 -#define REG_HISR3 0x10BC -#define REG_SW_MDIO 0x10C0 -#define REG_SW_FLUSH 0x10C4 -#define REG_FW_DBG0 0x10E0 -#define REG_FW_DBG1 0x10E4 -#define REG_FW_DBG2 0x10E8 -#define REG_FW_DBG3 0x10EC -#define REG_FW_DBG4 0x10F0 -#define REG_FW_DBG5 0x10F4 -#define REG_FW_DBG6 0x10F8 -#define REG_FW_DBG7 0x10FC -#define REG_CR_EXT 0x1100 -#define REG_FWFF 0x1114 -#define REG_FT2IMR 0x1120 -#define REG_FT2ISR 0x1124 -#define REG_FT3IMR 0x1128 -#define REG_FT3ISR 0x112C -#define REG_FW2IMR 0x1130 -#define REG_FW2ISR 0x1134 -#define REG_FT1IMR 0x1138 -#define REG_FT1ISR 0x113C -#define REG_SPWR0 0x1140 -#define REG_SPWR1 0x1144 -#define REG_SPWR2 0x1148 -#define REG_SPWR3 0x114C -#define REG_POWSEQ 0x1150 -#define REG_MSG2 0x11F0 -#define REG_MSG3 0x11F4 -#define REG_MSG4 0x11F8 -#define REG_MSG5 0x11FC -#define REG_Q0_Q1_INFO 0x1400 -#define REG_Q2_Q3_INFO 0x1404 -#define REG_Q4_Q5_INFO 0x1408 -#define REG_Q6_Q7_INFO 0x140C -#define REG_MGQ_HIQ_INFO 0x1410 -#define REG_CMDQ_BCNQ_INFO 0x1414 -#define REG_USEREG_SETTING 0x1420 -#define REG_AESIV_SETTING 0x1424 -#define REG_BF0_TIME_SETTING 0x1428 -#define REG_BF1_TIME_SETTING 0x142C -#define REG_BF_TIMOUT_EN 0x1430 -#define REG_MACID_RELEASE0 0x1434 -#define REG_MACID_RELEASE1 0x1438 -#define REG_MACID_RELEASE2 0x143C -#define REG_MACID_RELEASE3 0x1440 -#define REG_MACID_RELEASE_SETTING 0x1444 -#define REG_FAST_EDCA_VOVI_SETTING 0x1448 -#define REG_FAST_EDCA_BEBK_SETTING 0x144C -#define REG_MACID_DROP0 0x1450 -#define REG_MACID_DROP1 0x1454 -#define REG_MACID_DROP2 0x1458 -#define REG_MACID_DROP3 0x145C - -#endif - - -//----------------------------------------------------- -// -// 0x1200h ~ 0x12FFh DDMA CTRL -// -// // temp add by Eric, wait for docutment define -//----------------------------------------------------- - -#define REG_DDMA_CH0SA 0x1200 -#define REG_DDMA_CH0DA 0x1204 -#define REG_DDMA_CH0CTRL 0x1208 -#define REG_DDMA_CH1SA 0x1210 -#define REG_DDMA_CH1DA 0x1214 -#define REG_DDMA_CH1CTRL 0x1218 -#define REG_DDMA_CH2SA 0x1220 -#define REG_DDMA_CH2DA 0x1224 -#define REG_DDMA_CH2CTRL 0x1228 -#define REG_DDMA_CH3SA 0x1230 -#define REG_DDMA_CH3DA 0x1234 -#define REG_DDMA_CH3CTRL 0x1238 -#define REG_DDMA_CH4SA 0x1240 -#define REG_DDMA_CH4DA 0x1244 -#define REG_DDMA_CH4CTRL 0x1248 -#define REG_DDMA_CH5SA 0x1250 -#define REG_DDMA_CH5DA 0x1254 -#define REG_DDMA_CH5CTRL 0x1258 - -#define REG_DDMA_INT_MSK 0x12E0 -#define REG_DDMA_CHSTATUS 0x12E8 -#define REG_DDMA_CHKSUM 0x12F0 -#define REG_DDMA_MONITER 0x12FC - -//----------------------------------------------------- -// -// 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress -// -//----------------------------------------------------- -#define REG_RXPKTBUF_STARTADDR 0xFB00 -#define REG_TXPKTBUF_STARTADDR 0xFC00 - -//----------------------------------------------------- -// -// 0xFD00h ~ 0xFDFFh 8051 CPU Local REG -// -//----------------------------------------------------- -#define REG_SYS_CTRL 0xFD00 -#define REG_PONSTS_RPT1 0xFD01 -#define REG_PONSTS_RPT2 0xFD02 -#define REG_PONSTS_RPT3 0xFD03 -#define REG_PONSTS_RPT4 0xFD04 //0x84 -#define REG_PONSTS_RPT5 0xFD05 //0x85 -#define REG_8051ERRFLAG 0xFD08 -#define REG_8051ERRFLAG_MASK 0xFD09 -#define REG_TXADDRH 0xFD10 //Tx Packet High Address -#define REG_RXADDRH 0xFD11 //Rx Packet High Address -#define REG_TXADDRH_EXT 0xFD12 //0xFD12[0] : for 8051 access txpktbuf high64k as external register - -#define REG_U3_STATE 0xFD48 //(Read only) [7:4] : usb3 changed last state. [3:0] usb3 state - -//for MAILBOX -#define REG_OUTDATA0 0xFD50 -#define REG_OUTDATA1 0xFD54 -#define REG_OUTRDY 0xFD58 //bit[0] : OutReady, bit[1] : OutEmptyIntEn - -#define REG_INDATA0 0xFD60 -#define REG_INDATA1 0xFD64 -#define REG_INRDY 0xFD68 //bit[0] : InReady, bit[1] : InRdyIntEn - -//MCU ERROR debug REG -#define REG_MCUERR_PCLSB 0xFD90 //PC[7:0] -#define REG_MCUERR_PCMSB 0xFD91 //PC[15:8] -#define REG_MCUERR_ACC 0xFD92 -#define REG_MCUERR_B 0xFD93 -#define REG_MCUERR_DPTRLSB 0xFD94 //DPTR[7:0] -#define REG_MCUERR_DPTRMSB 0xFD95 //DPTR[15:8] -#define REG_MCUERR_SP 0xFD96 //SP[7:0] -#define REG_MCUERR_IE 0xFD97 //IE[7:0] -#define REG_MCUERR_EIE 0xFD98 //EIE[7:0] -#define REG_VERA_SIM 0xFD9F -//0xFD99~0xFD9F are reserved.. - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFEFFh USB Configuration -// -//----------------------------------------------------- - -/* RTS5101 USB Register Definition */ -#define REG_USB_SETUP_DEC_INT 0xFE00 -#define REG_USB_DMACTL 0xFE01 -#define REG_USB_IRQSTAT0 0xFE02 -#define REG_USB_IRQSTAT1 0xFE03 -#define REG_USB_IRQEN0 0xFE04 -#define REG_USB_IRQEN1 0xFE05 -#define REG_USB_AUTOPTRL 0xFE06 -#define REG_USB_AUTOPTRH 0xFE07 -#define REG_USB_AUTODAT 0xFE08 - -#define REG_USB_SCRATCH0 0xFE09 -#define REG_USB_SCRATCH1 0xFE0A -#define REG_USB_SEEPROM 0xFE0B -#define REG_USB_GPIO0 0xFE0C -#define REG_USB_GPIO0DIR 0xFE0D -#define REG_USB_CLKSEL 0xFE0E -#define REG_USB_BOOTCTL 0xFE0F - -#define REG_USB_USBCTL 0xFE10 -#define REG_USB_USBSTAT 0xFE11 -#define REG_USB_DEVADDR 0xFE12 -#define REG_USB_USBTEST 0xFE13 -#define REG_USB_FNUM0 0xFE14 -#define REG_USB_FNUM1 0xFE15 - -#define REG_USB_EP_IDX 0xFE20 -#define REG_USB_EP_CFG 0xFE21 -#define REG_USB_EP_CTL 0xFE22 -#define REG_USB_EP_STAT 0xFE23 -#define REG_USB_EP_IRQ 0xFE24 -#define REG_USB_EP_IRQEN 0xFE25 -#define REG_USB_EP_MAXPKT0 0xFE26 -#define REG_USB_EP_MAXPKT1 0xFE27 -#define REG_USB_EP_DAT 0xFE28 -#define REG_USB_EP_BC0 0xFE29 -#define REG_USB_EP_BC1 0xFE2A -#define REG_USB_EP_TC0 0xFE2B -#define REG_USB_EP_TC1 0xFE2C -#define REG_USB_EP_TC2 0xFE2D -#define REG_USB_EP_CTL2 0xFE2E - -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_VID 0xFE60 -#define REG_USB_PID 0xFE62 -#define REG_USB_OPT 0xFE64 -#define REG_USB_CONFIG 0xFE65 //RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ - //TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 -#define REG_USB_PHY_PARA1 0xFE68 //Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) -#define REG_USB_PHY_PARA2 0xFE69 //Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) -#define REG_USB_PHY_PARA3 0xFE6A //Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) -#define REG_USB_PHY_PARA4 0xFE6B //(USB PHY 0xE7[7:0]) -#define REG_USB_OPT2 0xFE6C -#define REG_USB_MAC_ADDR 0xFE70 //0xFE70~0xFE75 -#define REG_USB_MANUFACTURE_SETTING 0xFE80 //0xFE80~0xFE90 Max : 32 bytes -#define REG_USB_PRODUCT_STRING 0xFEA0 //0xFEA0~0xFECF Max : 48 bytes -#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 //0xFED0~0xFEDF Max : 12 bytes - -#define REG_USB_ALTERNATE_SETTING 0xFE4F -#define REG_USB_INT_BINTERVAL 0xFE6E -#define REG_USB_GPS_EP_CONFIG 0xFE6D - - -//eric-8814 -#define RF_SYN_G1 0x25 // RF TX Power control -#define RF_SYN_G2 0x26 // RF TX Power control -#define RF_SYN_G3 0x27 // RF TX Power control -#define RF_SYN_G4 0x28 // RF TX Power control -#define RF_SYN_G5 0x29 // RF TX Power control -#define RF_SYN_G6 0x2A // RF TX Power control -#define RF_SYN_G7 0x2B // RF TX Power control -#define RF_SYN_G8 0x2C // RF TX Power control - -#define RF_RCK_OS 0x30 // RF TX PA control -#define RF_TXPA_G1 0x31 // RF TX PA control -#define RF_TXPA_G2 0x32 // RF TX PA control -#define RF_TXPA_G3 0x33 // RF TX PA control -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C // -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF - - -#endif //__HAL_COM_REG_H__ - +#ifndef __HAL_COM_REG_H__ +#define __HAL_COM_REG_H__ +/*-------------------------Modification Log----------------------------------- + For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524 + The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A + 8812A and 8188E is not included in page0 register + + For other pages, it is based on MAC_Register.doc SVN502 + Most IC is the same with 8812A +-------------------------Modification Log-----------------------------------*/ + +/*--------------------------Include File--------------------------------------*/ +#include "HalHWCfg.h" +/*--------------------------Include File--------------------------------------*/ + + + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + + #define REG_SYS_ISO_CTRL 0x0000 + #define REG_SYS_FUNC_EN 0x0002 + #define REG_SYS_PW_CTRL 0x0004 + #define REG_SYS_CLK_CTRL 0x0008 + #define REG_SYS_EEPROM_CTRL 0x000A + #define REG_EE_VPD 0x000C + #define REG_SYS_SWR_CTRL1 0x0010 + #define REG_SYS_SWR_CTRL2 0x0014 + #define REG_SYS_SWR_CTRL3 0x0018 + #define REG_RSV_CTRL 0x001C + #define REG_RF_CTRL 0x001F + #define REG_AFE_LDO_CTRL 0x0020 + #define REG_AFE_CTRL1 0x0024 + #define REG_AFE_CTRL2 0x0028 + #define REG_AFE_CTRL3 0x002C + #define REG_EFUSE_CTRL 0x0030 + #define REG_LDO_EFUSE_CTRL 0x0034 + #define REG_PWR_OPTION_CTRL 0x0038 + #define REG_CAL_TIMER 0x003C + #define REG_ACLK_MON 0x003E + #define REG_GPIO_MUXCFG 0x0040 + #define REG_GPIO_PIN_CTRL 0x0044 + #define REG_GPIO_INTM 0x0048 + #define REG_LED_CFG 0x004C + #define REG_FSIMR 0x0050 + #define REG_FSISR 0x0054 + #define REG_HSIMR 0x0058 + #define REG_HSISR 0x005C + #define REG_GPIO_EXT_CTRL 0x0060 + #define REG_PAD_CTRL1 0x0064 + #define REG_WL_BT_PWR_CTRL 0x0068 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + + #define REG_SDM_DEBUG 0x006C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_GSSR 0x006C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + + #define REG_SDIO_CTRL 0x0070 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_SYS_CLKR 0x0070 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + + #define REG_HCI_OPT_CTRL 0x0074 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + + #define REG_AFE_CTRL4 0x0078 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_AFE_XTAL_CTRL_EXT 0x0078 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + + #define REG_LDO_SWR_CTRL 0x007C + #define REG_8051FW_CTRL 0x0080 + #define REG_MCU_TST_CFG 0x0084 + #define REG_HMEBOX_E0_E1 0x0088 + #define REG_HMEBOX_E2_E3 0x008C + #define REG_WLLPS_CTRL 0x0090 + #define REG_GPIO_DEBOUNCE_CTRL 0x0098 + #define REG_RPWM2 0x009C + #define REG_SYSON_FSM_MON 0x00A0 + #define REG_PMC_DBG_CTRL1 0x00A8 + #define REG_HIMR0 0x00B0 + #define REG_HISR0 0x00B4 + #define REG_HIMR1 0x00B8 + #define REG_HISR1 0x00BC + #define REG_DBG_PORT_SEL 0x00C0 + #define REG_PAD_CTRL2 0x00C4 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_MEM_RMC 0x00C8 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + + #define REG_PMC_DBG_CTRL2 0x00CC + #define REG_BIST_CTRL 0x00D0 + #define REG_BIST_RPT 0x00D4 + #define REG_MEM_CTRL 0x00D8 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WLAN_DBG 0x00DC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + + #define REG_USB_SIE_INTF 0x00E0 + #define REG_PCIE_MIO_INTF 0x00E4 + #define REG_PCIE_MIO_INTD 0x00E8 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_HPON_FSM 0x00EC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SYS_CFG1 0x00F0 +#define REG_SYS_STATUS1 0x00F4 +#define REG_SYS_STATUS2 0x00F8 +#define REG_SYS_CFG2 0x00FC +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TSF_CLK_STATE 0x0108 +#define REG_TXDMA_PQ_MAP 0x010C +#define REG_TRXFF_BNDY 0x0114 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PTA_I2C_MBOX 0x0118 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FF_STATUS 0x0118 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RXFF_PTR 0x011C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_FEIMR 0x0120 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FE1IMR 0x0120 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_FEISR 0x0124 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FE1ISR 0x0124 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_CPWM 0x012C +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 +#define REG_CPWM2 0x014C +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_TC5_CTRL 0x0168 +#define REG_TC6_CTRL 0x016C +#define REG_MBIST_FAIL 0x0170 +#define REG_MBIST_START_PAUSE 0x0174 +#define REG_MBIST_DONE 0x0178 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_MBIST_ROM_CRC_DATA 0x017C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_MBIST_FAIL_NRML 0x017C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_AES_DECRPT_DATA 0x0180 +#define REG_AES_DECRPT_CFG 0x0184 +#define REG_TMETER 0x0190 +#define REG_OSC_32K_CTRL 0x0194 +#define REG_32K_CAL_REG1 0x0198 +#define REG_C2HEVT 0x01A0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_TC7_CTRL 0x01B0 +#define REG_TC8_CTRL 0x01B4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SW_DEFINED_PAGE1 0x01B8 +#define REG_MCUTST_I 0x01C0 +#define REG_MCUTST_II 0x01C4 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX0 0x01D0 +#define REG_HMEBOX1 0x01D4 +#define REG_HMEBOX2 0x01D8 +#define REG_HMEBOX3 0x01DC +#define REG_LLT_INIT 0x01E0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_GENTST 0x01E4 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_LLT_INIT_ADDR 0x01E4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BB_ACCESS_CTRL 0x01E8 +#define REG_BB_ACCESS_DATA 0x01EC +#define REG_HMEBOX_E0 0x01F0 +#define REG_HMEBOX_E1 0x01F4 +#define REG_HMEBOX_E2 0x01F8 +#define REG_HMEBOX_E3 0x01FC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RQPN_CTRL_HLPQ 0x0200 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FIFOPAGE_CTRL_1 0x0200 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_FIFOPAGE_INFO 0x0204 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FIFOPAGE_CTRL_2 0x0204 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_DWBCN0_CTRL 0x0208 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_AUTO_LLT_V1 0x0208 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RQPN_NPQ 0x0214 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_TX_DMA_DBG 0x0214 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TQPNT1 0x0218 +#define REG_TQPNT2 0x021C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TDE_DEBUG 0x0220 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_TQPNT3 0x0220 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_AUTO_LLT 0x0224 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_TQPNT4 0x0224 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_DWBCN1_CTRL 0x0228 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_RQPN_CTRL_1 0x0228 +#define REG_RQPN_CTRL_2 0x022C +#define REG_FIFOPAGE_INFO_1 0x0230 +#define REG_FIFOPAGE_INFO_2 0x0234 +#define REG_FIFOPAGE_INFO_3 0x0238 +#define REG_FIFOPAGE_INFO_4 0x023C +#define REG_FIFOPAGE_INFO_5 0x0240 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_CONTROL 0x0286 +#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_DPR 0x028C +#define REG_RXDMA_MODE 0x0290 +#define REG_C2H_PKT 0x0294 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_PCIE_CTRL 0x0300 + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_LX_CTRL1 0x0300 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_INT_MIG 0x0304 +#define REG_BCNQ_TXBD_DESA 0x0308 +#define REG_MGQ_TXBD_DESA 0x0310 +#define REG_VOQ_TXBD_DESA 0x0318 +#define REG_VIQ_TXBD_DESA 0x0320 +#define REG_BEQ_TXBD_DESA 0x0328 +#define REG_BKQ_TXBD_DESA 0x0330 +#define REG_RXQ_RXBD_DESA 0x0338 +#define REG_HI0Q_TXBD_DESA 0x0340 +#define REG_HI1Q_TXBD_DESA 0x0348 +#define REG_HI2Q_TXBD_DESA 0x0350 +#define REG_HI3Q_TXBD_DESA 0x0358 +#define REG_HI4Q_TXBD_DESA 0x0360 +#define REG_HI5Q_TXBD_DESA 0x0368 +#define REG_HI6Q_TXBD_DESA 0x0370 +#define REG_HI7Q_TXBD_DESA 0x0378 +#define REG_MGQ_TXBD_NUM 0x0380 +#define REG_RX_RXBD_NUM 0x0382 +#define REG_VOQ_TXBD_NUM 0x0384 +#define REG_VIQ_TXBD_NUM 0x0386 +#define REG_BEQ_TXBD_NUM 0x0388 +#define REG_BKQ_TXBD_NUM 0x038A +#define REG_HI0Q_TXBD_NUM 0x038C +#define REG_HI1Q_TXBD_NUM 0x038E +#define REG_HI2Q_TXBD_NUM 0x0390 +#define REG_HI3Q_TXBD_NUM 0x0392 +#define REG_HI4Q_TXBD_NUM 0x0394 +#define REG_HI5Q_TXBD_NUM 0x0396 +#define REG_HI6Q_TXBD_NUM 0x0398 +#define REG_HI7Q_TXBD_NUM 0x039A +#define REG_TSFTIMER_HCI 0x039C +#define REG_BD_RWPTR_CLR 0x039C +#define REG_VOQ_TXBD_IDX 0x03A0 +#define REG_VIQ_TXBD_IDX 0x03A4 +#define REG_BEQ_TXBD_IDX 0x03A8 +#define REG_BKQ_TXBD_IDX 0x03AC +#define REG_MGQ_TXBD_IDX 0x03B0 +#define REG_RXQ_RXBD_IDX 0x03B4 +#define REG_HI0Q_TXBD_IDX 0x03B8 +#define REG_HI1Q_TXBD_IDX 0x03BC +#define REG_HI2Q_TXBD_IDX 0x03C0 +#define REG_HI3Q_TXBD_IDX 0x03C4 +#define REG_HI4Q_TXBD_IDX 0x03C8 +#define REG_HI5Q_TXBD_IDX 0x03CC +#define REG_HI6Q_TXBD_IDX 0x03D0 +#define REG_HI7Q_TXBD_IDX 0x03D4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_DBG_SEL_V1 0x03D8 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PCIE_HRPWM1_V1 0x03D9 +#define REG_PCIE_HCPWM1_V1 0x03DA + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_PCIE_CTRL2 0x03DB + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_LX_CTRL2 0x03DB + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PCIE_HRPWM2_V1 0x03DC +#define REG_PCIE_HCPWM2_V1 0x03DE +#define REG_PCIE_H2C_MSG_V1 0x03E0 +#define REG_PCIE_C2H_MSG_V1 0x03E4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_DBI_WDATA_V1 0x03E8 + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_LX_DMA_ISR 0x03E8 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_DBI_RDATA_V1 0x03EC + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_LX_DMA_IMR 0x03EC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_DBI_FLAG_V1 0x03F0 + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_LX_DMA_DBG 0x03F0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT) + +#define REG_MDIO_V1 0x03F4 + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_BUS_MIX_CFG 0x03F8 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_HCI_MIX_CFG 0x03FC + +#endif + + +#if (RTL8881A_SUPPORT) + +#define REG_BUS_MIX_CFG1 0x03FC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_Q0_INFO 0x0400 +#define REG_Q1_INFO 0x0404 +#define REG_Q2_INFO 0x0408 +#define REG_Q3_INFO 0x040C +#define REG_MGQ_INFO 0x0410 +#define REG_HIQ_INFO 0x0414 +#define REG_BCNQ_INFO 0x0418 +#define REG_TXPKT_EMPTY 0x041A +#define REG_CPU_MGQ_INFO 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_HWSEQ_CTRL 0x0423 +#define REG_BCNQ_BDNY 0x0424 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BCNQ_BDNY_V1 0x0424 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_MGQ_BDNY 0x0425 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_LIFETIME_EN 0x0426 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_FW_FREE_TAIL 0x0427 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SPEC_SIFS 0x0428 +#define REG_RETRY_LIMIT 0x042A +#define REG_TXBF_CTRL 0x042C +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1_V1 0x044C +#define REG_CCK_CHECK 0x0454 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_AMPDU_BURST_CTRL 0x0455 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_AMPDU_MAX_TIME_V1 0x0455 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_AMPDU_MAX_TIME 0x0456 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BCNQ1_BDNY_V1 0x0456 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BCNQ1_BDNY 0x0457 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH 0x0458 +#define REG_ACQ_STOP 0x045C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD 0x045D + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_NDPA_RATE 0x045D + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TX_HANG_CTRL 0x045E +#define REG_NDPA_OPT_CTRL 0x045F + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_FAST_EDCA_CTRL 0x0460 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_CMDQ_INFO 0x0464 +#define REG_Q4_INFO 0x0468 +#define REG_Q5_INFO 0x046C +#define REG_Q6_INFO 0x0470 +#define REG_Q7_INFO 0x0474 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD_V1 0x0478 +#define REG_MGQ_BDNY_V1 0x047A + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TXRPT_CTRL 0x047C +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_BASIC_CFEND_RATE 0x0481 +#define REG_STBC_CFEND_RATE 0x0482 +#define REG_DATA_SC 0x0483 +#define REG_MACID_SLEEP3 0x0484 +#define REG_MACID_SLEEP1 0x0488 +#define REG_ARFR2_V1 0x048C +#define REG_ARFR3_V1 0x0494 +#define REG_ARFR4 0x049C +#define REG_ARFR5 0x04A4 +#define REG_TXRPT_START_OFFSET 0x04AC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TRYING_CNT_TH 0x04B0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_POWER_STAGE1 0x04B4 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_POWER_STAGE2 0x04B8 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC +#define REG_PKT_LIFE_TIME 0x04C0 +#define REG_STBC_SETTING 0x04C4 +#define REG_STBC_SETTING2 0x04C5 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04C7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +#define REG_MACID_SLEEP2 0x04D0 +#define REG_MACID_SLEEP 0x04D4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_CSI_SEQ 0x04DE + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_NULL_PKT_STATUS 0x04E0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_NULL_PKT_STATUS_V1 0x04E0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PTCL_ERR_STATUS 0x04E2 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PTCL_PKT_NUM 0x04E3 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PTCL_TX_RPT 0x04F0 +#define REG_DUMMY_PAGE4 0x04FC + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_DUMMY_PAGE4_V1 0x04FC +#define REG_MOREDATA 0x04FE + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS 0x0514 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +#define REG_MBSSID_CTRL 0x0526 +#define REG_P2PPS_CTRL 0x0527 +#define REG_PKT_LIFETIME_CTRL 0x0528 +#define REG_P2PPS_SPEC_STATE 0x052B +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_P2PPS_STATE 0x0543 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BCN_CTRL1 0x0551 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BCN_CTRL_CLINT0 0x0551 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_MBSSID_BCN_SPACE 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TSFTR1 0x0568 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_FREERUN_CNT 0x0568 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_ATIMWND1 0x0570 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_ATIMWND1_V1 0x0570 +#define REG_TBTT_PROHIBIT_INFRA 0x0571 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_CTWND 0x0572 +#define REG_BCNIVLCUNT 0x0573 +#define REG_BCNDROPCTRL 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD 0x0575 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 +#define REG_MISC_CTRL 0x0577 +#define REG_BCN_CTRL_CLINT1 0x0578 +#define REG_BCN_CTRL_CLINT2 0x0579 +#define REG_BCN_CTRL_CLINT3 0x057A +#define REG_P2PPS1_SPEC_STATE 0x057C +#define REG_P2PPS1_STATE 0x057D +#define REG_P2PPS2_SPEC_STATE 0x057E +#define REG_P2PPS2_STATE 0x057F + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_PS_TIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_TBTT_CTN_AREA 0x058C +#define REG_FORCE_BCN_IFS 0x058E +#define REG_TXOP_MIN 0x0590 +#define REG_PRE_BKF_TIME 0x0592 +#define REG_CROSS_TXOP_CTRL 0x0593 +#define REG_ATIMWND2 0x05A0 +#define REG_ATIMWND3 0x05A1 +#define REG_ATIMWND4 0x05A2 +#define REG_ATIMWND5 0x05A3 +#define REG_ATIMWND6 0x05A4 +#define REG_ATIMWND7 0x05A5 +#define REG_ATIMUGT 0x05A6 +#define REG_HIQ_NO_LMT_EN 0x05A7 +#define REG_DTIM_COUNTER_ROOT 0x05A8 +#define REG_DTIM_COUNTER_VAP1 0x05A9 +#define REG_DTIM_COUNTER_VAP2 0x05AA +#define REG_DTIM_COUNTER_VAP3 0x05AB +#define REG_DTIM_COUNTER_VAP4 0x05AC +#define REG_DTIM_COUNTER_VAP5 0x05AD +#define REG_DTIM_COUNTER_VAP6 0x05AE +#define REG_DTIM_COUNTER_VAP7 0x05AF +#define REG_DIS_ATIM 0x05B0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_EARLY_128US 0x05B1 +#define REG_P2PPS1_CTRL 0x05B2 +#define REG_P2PPS2_CTRL 0x05B3 +#define REG_TIMER0_SRC_SEL 0x05B4 +#define REG_NOA_UNIT_SEL 0x05B5 +#define REG_P2POFF_DIS_TXTIME 0x05B7 +#define REG_MBSSID_BCN_SPACE2 0x05B8 +#define REG_MBSSID_BCN_SPACE3 0x05BC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_ACMHWCTRL 0x05C0 +#define REG_ACMRSTCTRL 0x05C1 +#define REG_ACMAVG 0x05C2 +#define REG_VO_ADMTIME 0x05C4 +#define REG_VI_ADMTIME 0x05C6 +#define REG_BE_ADMTIME 0x05C8 +#define REG_EDCA_RANDOM_GEN 0x05CC +#define REG_TXCMD_NOA_SEL 0x05CF +#define REG_NOA_PARAM 0x05E0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_NOA_SUBIE 0x05ED + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_P2P_RST 0x05F0 +#define REG_SCHEDULER_RST 0x05F1 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SCH_TXCMD 0x05F8 +#define REG_PAGE5_DUMMY 0x05FC +#define REG_WMAC_CR 0x0600 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BWOPMODE 0x0603 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG_1 0x0628 +#define REG_MBIDCAMCFG_2 0x062C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_MCU_TEST_1 0x0630 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WMAC_TCR_TSFT_OFS 0x0630 +#define REG_UDF_THSD 0x0632 +#define REG_ZLD_NUM 0x0633 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_MCU_TEST_2 0x0634 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_STMP_THSD 0x0634 +#define REG_WMAC_TXTIMEOUT 0x0635 +#define REG_MCU_TEST_2_V1 0x0636 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A +#define REG_RESP_SIFS_CCK 0x063C +#define REG_RESP_SIFS_OFDM 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WMAC_BACAM_RPMEN 0x0661 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_WMMPS_UAPSD_TID 0x0693 +#define REG_LPNAV_CTRL 0x0694 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WKFMCAM_NUM 0x0698 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_RWD 0x069C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + + #define REG_FLC_RPC 0x06AC + #define REG_FLC_RPCT 0x06AD + #define REG_FLC_PTS 0x06AE + #define REG_FLC_TRPC 0x06AF + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_RXPKTMON_CTRL 0x06B0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_STATE_MON 0x06B4 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_ERROR_MON 0x06B8 +#define REG_SEARCH_MACID 0x06BC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_COEX_TABLE 0x06C0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_RXCMD_0 0x06D0 +#define REG_RXCMD_1 0x06D4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WMAC_RESP_TXINFO 0x06D8 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BBPSF_CTRL 0x06DC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_P2P_RX_BCN_NOA 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO 0x06EC +#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 +#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC +#define REG_MACID1 0x0700 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BSSID1 0x0708 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BCN_PSR_RPT1 0x0710 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_ASSOCIATED_BFMEE_SEL 0x0714 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BEAMFORMEE_SEL 0x0714 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SND_PTCL_CTRL 0x0718 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_SOUNDING_PTCL_CTRL 0x0718 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_RX_CSI_RPT_INFO 0x071C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_RX_CSI_RPT 0x071C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_NS_ARP_CTRL 0x0720 +#define REG_NS_ARP_INFO 0x0724 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_NS_ARP_IPADDR 0x0728 +#define REG_WRITE_RX_CSI_RPT_INFO 0x072C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BEAMFORMING_INFO_NSARP 0x072C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_NS_ARP_IPV6_MYADDR 0x0730 +#define REG_WMAC 0x0750 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_SW 0x0760 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_COEX_V2 0x0762 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_COEX 0x0764 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WLAN_ACT_MSK_CTRL 0x0768 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL 0x0768 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_STATISTICS_CTRL 0x076E +#define REG_BT_COEX_ENH_INTF_CTRL 0x076E + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_ACT_STATISTICS 0x0770 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_STATISTICS_OTH_CTRL 0x0778 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_Statistics_Control_Register 0x0778 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_CMD_ID 0x077C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_Status_Report_Register 0x077C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT__STATUS_RPT 0x077D +#define REG_BT_DATA 0x0780 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_Interrupt_Control_Register 0x0780 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WLAN_RPT_ 0x0781 +#define REG_BT_ISR_CTRL 0x0783 +#define REG_WLAN_RPT_TO_CTR 0x0784 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_WLAN_Report_Time_Out_Control_Register 0x0784 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_ISOLATION_TABLE 0x0785 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_Isolation_Table_Register_Register 0x0785 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_ISR_STA 0x078F + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_Interrupt_Status_Register 0x078F + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_TDMA_Time_Register 0x0790 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_CH_INFO 0x0794 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_BT_ACT_Register 0x0794 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_BT_STATIC_INFO_EXT 0x0795 +#define REG_LTR_IDLE_LATENCY 0x0798 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_OBFF_CTRL_basic 0x0798 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_LTR_ACTIVE_LATENCY 0x079C + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_OBFF_CTRL2_timer 0x079C + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_OBFF_CTRL 0x07A0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_LTR_CTRL_basic 0x07A0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_LTR_CTRL 0x07A4 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_LTR_CTRL2_timer_threshold 0x07A4 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_LTR_CTRL2 0x07A8 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_LTR_IDLE_latency 0x07A8 +#define REG_LTR_ACTIVE_latency 0x07AC + +#endif + + +#if (RTL8192E_SUPPORT || RTL8881A_SUPPORT) + +#define REG_ANTTRN_CTRL 0x07B0 + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_Antenna_Training_Control_Register 0x07B0 + +#endif + + +#if (RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8881A_SUPPORT) + +#define REG_WMAC_PKTCNT_RWD 0x07B8 +#define REG_WMAC_PKTCNT_CTRL 0x07BC + +#endif + + +#if (RTL8814A_SUPPORT) + +#define REG_IQ_DUMP 0x07C0 +#define REG_OFDM_CCK_LEN_MASK 0x07D0 +#define REG_NDP_SIG 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 +#define REG_CPU_DMEM_CON 0x1080 +#define REG_HIMR2 0x10B0 +#define REG_HISR2 0x10B4 +#define REG_HIMR3 0x10B8 +#define REG_HISR3 0x10BC +#define REG_SW_MDIO 0x10C0 +#define REG_SW_FLUSH 0x10C4 +#define REG_FW_DBG0 0x10E0 +#define REG_FW_DBG1 0x10E4 +#define REG_FW_DBG2 0x10E8 +#define REG_FW_DBG3 0x10EC +#define REG_FW_DBG4 0x10F0 +#define REG_FW_DBG5 0x10F4 +#define REG_FW_DBG6 0x10F8 +#define REG_FW_DBG7 0x10FC +#define REG_CR_EXT 0x1100 +#define REG_FWFF 0x1114 +#define REG_FT2IMR 0x1120 +#define REG_FT2ISR 0x1124 +#define REG_FT3IMR 0x1128 +#define REG_FT3ISR 0x112C +#define REG_FW2IMR 0x1130 +#define REG_FW2ISR 0x1134 +#define REG_FT1IMR 0x1138 +#define REG_FT1ISR 0x113C +#define REG_SPWR0 0x1140 +#define REG_SPWR1 0x1144 +#define REG_SPWR2 0x1148 +#define REG_SPWR3 0x114C +#define REG_POWSEQ 0x1150 +#define REG_MSG2 0x11F0 +#define REG_MSG3 0x11F4 +#define REG_MSG4 0x11F8 +#define REG_MSG5 0x11FC +#define REG_Q0_Q1_INFO 0x1400 +#define REG_Q2_Q3_INFO 0x1404 +#define REG_Q4_Q5_INFO 0x1408 +#define REG_Q6_Q7_INFO 0x140C +#define REG_MGQ_HIQ_INFO 0x1410 +#define REG_CMDQ_BCNQ_INFO 0x1414 +#define REG_USEREG_SETTING 0x1420 +#define REG_AESIV_SETTING 0x1424 +#define REG_BF0_TIME_SETTING 0x1428 +#define REG_BF1_TIME_SETTING 0x142C +#define REG_BF_TIMOUT_EN 0x1430 +#define REG_MACID_RELEASE0 0x1434 +#define REG_MACID_RELEASE1 0x1438 +#define REG_MACID_RELEASE2 0x143C +#define REG_MACID_RELEASE3 0x1440 +#define REG_MACID_RELEASE_SETTING 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING 0x144C +#define REG_MACID_DROP0 0x1450 +#define REG_MACID_DROP1 0x1454 +#define REG_MACID_DROP2 0x1458 +#define REG_MACID_DROP3 0x145C + +#endif + + +//----------------------------------------------------- +// +// 0x1200h ~ 0x12FFh DDMA CTRL +// +// // temp add by Eric, wait for docutment define +//----------------------------------------------------- + +#define REG_DDMA_CH0SA 0x1200 +#define REG_DDMA_CH0DA 0x1204 +#define REG_DDMA_CH0CTRL 0x1208 +#define REG_DDMA_CH1SA 0x1210 +#define REG_DDMA_CH1DA 0x1214 +#define REG_DDMA_CH1CTRL 0x1218 +#define REG_DDMA_CH2SA 0x1220 +#define REG_DDMA_CH2DA 0x1224 +#define REG_DDMA_CH2CTRL 0x1228 +#define REG_DDMA_CH3SA 0x1230 +#define REG_DDMA_CH3DA 0x1234 +#define REG_DDMA_CH3CTRL 0x1238 +#define REG_DDMA_CH4SA 0x1240 +#define REG_DDMA_CH4DA 0x1244 +#define REG_DDMA_CH4CTRL 0x1248 +#define REG_DDMA_CH5SA 0x1250 +#define REG_DDMA_CH5DA 0x1254 +#define REG_DDMA_CH5CTRL 0x1258 + +#define REG_DDMA_INT_MSK 0x12E0 +#define REG_DDMA_CHSTATUS 0x12E8 +#define REG_DDMA_CHKSUM 0x12F0 +#define REG_DDMA_MONITER 0x12FC + +//----------------------------------------------------- +// +// 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress +// +//----------------------------------------------------- +#define REG_RXPKTBUF_STARTADDR 0xFB00 +#define REG_TXPKTBUF_STARTADDR 0xFC00 + +//----------------------------------------------------- +// +// 0xFD00h ~ 0xFDFFh 8051 CPU Local REG +// +//----------------------------------------------------- +#define REG_SYS_CTRL 0xFD00 +#define REG_PONSTS_RPT1 0xFD01 +#define REG_PONSTS_RPT2 0xFD02 +#define REG_PONSTS_RPT3 0xFD03 +#define REG_PONSTS_RPT4 0xFD04 //0x84 +#define REG_PONSTS_RPT5 0xFD05 //0x85 +#define REG_8051ERRFLAG 0xFD08 +#define REG_8051ERRFLAG_MASK 0xFD09 +#define REG_TXADDRH 0xFD10 //Tx Packet High Address +#define REG_RXADDRH 0xFD11 //Rx Packet High Address +#define REG_TXADDRH_EXT 0xFD12 //0xFD12[0] : for 8051 access txpktbuf high64k as external register + +#define REG_U3_STATE 0xFD48 //(Read only) [7:4] : usb3 changed last state. [3:0] usb3 state + +//for MAILBOX +#define REG_OUTDATA0 0xFD50 +#define REG_OUTDATA1 0xFD54 +#define REG_OUTRDY 0xFD58 //bit[0] : OutReady, bit[1] : OutEmptyIntEn + +#define REG_INDATA0 0xFD60 +#define REG_INDATA1 0xFD64 +#define REG_INRDY 0xFD68 //bit[0] : InReady, bit[1] : InRdyIntEn + +//MCU ERROR debug REG +#define REG_MCUERR_PCLSB 0xFD90 //PC[7:0] +#define REG_MCUERR_PCMSB 0xFD91 //PC[15:8] +#define REG_MCUERR_ACC 0xFD92 +#define REG_MCUERR_B 0xFD93 +#define REG_MCUERR_DPTRLSB 0xFD94 //DPTR[7:0] +#define REG_MCUERR_DPTRMSB 0xFD95 //DPTR[15:8] +#define REG_MCUERR_SP 0xFD96 //SP[7:0] +#define REG_MCUERR_IE 0xFD97 //IE[7:0] +#define REG_MCUERR_EIE 0xFD98 //EIE[7:0] +#define REG_VERA_SIM 0xFD9F +//0xFD99~0xFD9F are reserved.. + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFEFFh USB Configuration +// +//----------------------------------------------------- + +/* RTS5101 USB Register Definition */ +#define REG_USB_SETUP_DEC_INT 0xFE00 +#define REG_USB_DMACTL 0xFE01 +#define REG_USB_IRQSTAT0 0xFE02 +#define REG_USB_IRQSTAT1 0xFE03 +#define REG_USB_IRQEN0 0xFE04 +#define REG_USB_IRQEN1 0xFE05 +#define REG_USB_AUTOPTRL 0xFE06 +#define REG_USB_AUTOPTRH 0xFE07 +#define REG_USB_AUTODAT 0xFE08 + +#define REG_USB_SCRATCH0 0xFE09 +#define REG_USB_SCRATCH1 0xFE0A +#define REG_USB_SEEPROM 0xFE0B +#define REG_USB_GPIO0 0xFE0C +#define REG_USB_GPIO0DIR 0xFE0D +#define REG_USB_CLKSEL 0xFE0E +#define REG_USB_BOOTCTL 0xFE0F + +#define REG_USB_USBCTL 0xFE10 +#define REG_USB_USBSTAT 0xFE11 +#define REG_USB_DEVADDR 0xFE12 +#define REG_USB_USBTEST 0xFE13 +#define REG_USB_FNUM0 0xFE14 +#define REG_USB_FNUM1 0xFE15 + +#define REG_USB_EP_IDX 0xFE20 +#define REG_USB_EP_CFG 0xFE21 +#define REG_USB_EP_CTL 0xFE22 +#define REG_USB_EP_STAT 0xFE23 +#define REG_USB_EP_IRQ 0xFE24 +#define REG_USB_EP_IRQEN 0xFE25 +#define REG_USB_EP_MAXPKT0 0xFE26 +#define REG_USB_EP_MAXPKT1 0xFE27 +#define REG_USB_EP_DAT 0xFE28 +#define REG_USB_EP_BC0 0xFE29 +#define REG_USB_EP_BC1 0xFE2A +#define REG_USB_EP_TC0 0xFE2B +#define REG_USB_EP_TC1 0xFE2C +#define REG_USB_EP_TC2 0xFE2D +#define REG_USB_EP_CTL2 0xFE2E + +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_VID 0xFE60 +#define REG_USB_PID 0xFE62 +#define REG_USB_OPT 0xFE64 +#define REG_USB_CONFIG 0xFE65 //RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ + //TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 +#define REG_USB_PHY_PARA1 0xFE68 //Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) +#define REG_USB_PHY_PARA2 0xFE69 //Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) +#define REG_USB_PHY_PARA3 0xFE6A //Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) +#define REG_USB_PHY_PARA4 0xFE6B //(USB PHY 0xE7[7:0]) +#define REG_USB_OPT2 0xFE6C +#define REG_USB_MAC_ADDR 0xFE70 //0xFE70~0xFE75 +#define REG_USB_MANUFACTURE_SETTING 0xFE80 //0xFE80~0xFE90 Max : 32 bytes +#define REG_USB_PRODUCT_STRING 0xFEA0 //0xFEA0~0xFECF Max : 48 bytes +#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 //0xFED0~0xFEDF Max : 12 bytes + +#define REG_USB_ALTERNATE_SETTING 0xFE4F +#define REG_USB_INT_BINTERVAL 0xFE6E +#define REG_USB_GPS_EP_CONFIG 0xFE6D + + +//eric-8814 +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF + + +#endif //__HAL_COM_REG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComTXDesc.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalComTXDesc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalHWCfg.h b/package/kernel/rtl8192cd/WlanHAL/HalHeader/HalHWCfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform.h old mode 100755 new mode 100644 index 9cba73460de..5ef202080f0 --- a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform.h @@ -1,120 +1,120 @@ -#ifndef _HALMAC_2_PLATFORM_H_ -#define _HALMAC_2_PLATFORM_H_ - -/*========================================================== - Search The Keyword [Driver] - Search The Keyword [Driver] - Search The Keyword [Driver] -===========================================================*/ - - -#define BUILD_TEST 0/*[Driver] always set BUILD_TEST =0*/ - -#if BUILD_TEST -//#include "../Platform/App/HalTestBuild/halmac_2_platformapi.h" -#include "../Platform/App/Test/halmac_2_platformapi.h" -#else -/*[Driver] use thier own header files*/ -//#include "../Platform/App/VS2010MFC/AutoTest/stdafx.h" -//#include "../Header/GeneralDef.h" -#include "../../8192cd_cfg.h" //eric-8812b -#include "halmac_hw_cfg.h" -#ifndef __ECOS -#include -#include -#else -#include -#endif -#include "Hal88XXDesc.h" - -#endif - -/****************************************************/ -/*Define the Platform related Macro*/ -/***************************************************/ - -/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/ - -#ifndef _TRUE - #define _TRUE 1 -#endif - -#ifndef _FALSE - #define _FALSE (!_TRUE) -#endif - -#ifndef NULL - #define NULL ((void *)0) -#endif - -#if 0 -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; -typedef char s8; -typedef short s16; -typedef long s32; -#endif - -typedef u8 *pu8; -typedef u16 *pu16; -typedef u32 *pu32; -typedef s8 *ps8; -typedef s16 *ps16; -typedef s32 *ps32; - -#define HALMAC_INLINE __inline - -//eric-8822 ?? -#define HALMAC_PLATFORM_LITTLE_ENDIAN 1 -#define HALMAC_PLATFORM_BIG_ENDIAN 0 - -/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN is not mandatory. - But Little endian must be '1'. Big endian must be '0'. */ -/*[Driver] config the system endian*/ - -#ifdef _LITTLE_ENDIAN_ -#undef HALMAC_SYSTEM_ENDIAN -#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN -#endif - -#ifdef _BIG_ENDIAN_ -#undef HALMAC_SYSTEM_ENDIAN -#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN -#endif - - -/*[Driver] config if the operating platform*/ -#define HALMAC_PLATFORM_WINDOWS 0 -#define HALMAC_PLATFORM_LINUX 0 -#define HALMAC_PLATFORM_AP 1 -#define HALMAC_PLATFORM_TESTPROGRAM 0 /*[Driver] must set HALMAC_PLATFORM_TESTPROGRAM =0*/ - -/*[Driver] config if enable the dbg msg or notl*/ -#define HALMAC_DBG_MSG_ENABLE 0//1 - -/*[Driver] config if it support signal*/ -#define PLATFORM_SUPPORT_SIGNAL 0 - -/*[Driver] provide the type of signal and mutex*/ -#if PLATFORM_SUPPORT_SIGNAL -/* Signal type */ -typedef CEvent HALMAC_SIGNAL; -#endif -/* Mutex type */ -//typedef CRITICAL_SECTION HALMAC_MUTEX; -#ifndef __ECOS -typedef spinlock_t HALMAC_MUTEX; -#else -typedef int HALMAC_MUTEX; -#endif - -#define HALMAC_DBG_MSG_LEVEL HALMAC_DBG_ERR - -/*[Driver] define the Platform SDIO Bus CLK */ -#define PLATFORM_SD_CLK 50000000 /*50MHz*/ - -#endif//_HALMAC_2_PLATFORM_H_ - - - +#ifndef _HALMAC_2_PLATFORM_H_ +#define _HALMAC_2_PLATFORM_H_ + +/*========================================================== + Search The Keyword [Driver] + Search The Keyword [Driver] + Search The Keyword [Driver] +===========================================================*/ + + +#define BUILD_TEST 0/*[Driver] always set BUILD_TEST =0*/ + +#if BUILD_TEST +//#include "../Platform/App/HalTestBuild/halmac_2_platformapi.h" +#include "../Platform/App/Test/halmac_2_platformapi.h" +#else +/*[Driver] use thier own header files*/ +//#include "../Platform/App/VS2010MFC/AutoTest/stdafx.h" +//#include "../Header/GeneralDef.h" +#include "../../8192cd_cfg.h" //eric-8812b +#include "halmac_hw_cfg.h" +#ifndef __ECOS +#include +#include +#else +#include +#endif +#include "Hal88XXDesc.h" + +#endif + +/****************************************************/ +/*Define the Platform related Macro*/ +/***************************************************/ + +/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/ + +#ifndef _TRUE + #define _TRUE 1 +#endif + +#ifndef _FALSE + #define _FALSE (!_TRUE) +#endif + +#ifndef NULL + #define NULL ((void *)0) +#endif + +#if 0 +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned long u32; +typedef char s8; +typedef short s16; +typedef long s32; +#endif + +typedef u8 *pu8; +typedef u16 *pu16; +typedef u32 *pu32; +typedef s8 *ps8; +typedef s16 *ps16; +typedef s32 *ps32; + +#define HALMAC_INLINE __inline + +//eric-8822 ?? +#define HALMAC_PLATFORM_LITTLE_ENDIAN 1 +#define HALMAC_PLATFORM_BIG_ENDIAN 0 + +/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN is not mandatory. + But Little endian must be '1'. Big endian must be '0'. */ +/*[Driver] config the system endian*/ + +#ifdef _LITTLE_ENDIAN_ +#undef HALMAC_SYSTEM_ENDIAN +#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN +#endif + +#ifdef _BIG_ENDIAN_ +#undef HALMAC_SYSTEM_ENDIAN +#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN +#endif + + +/*[Driver] config if the operating platform*/ +#define HALMAC_PLATFORM_WINDOWS 0 +#define HALMAC_PLATFORM_LINUX 0 +#define HALMAC_PLATFORM_AP 1 +#define HALMAC_PLATFORM_TESTPROGRAM 0 /*[Driver] must set HALMAC_PLATFORM_TESTPROGRAM =0*/ + +/*[Driver] config if enable the dbg msg or notl*/ +#define HALMAC_DBG_MSG_ENABLE 0//1 + +/*[Driver] config if it support signal*/ +#define PLATFORM_SUPPORT_SIGNAL 0 + +/*[Driver] provide the type of signal and mutex*/ +#if PLATFORM_SUPPORT_SIGNAL +/* Signal type */ +typedef CEvent HALMAC_SIGNAL; +#endif +/* Mutex type */ +//typedef CRITICAL_SECTION HALMAC_MUTEX; +#ifndef __ECOS +typedef spinlock_t HALMAC_MUTEX; +#else +typedef int HALMAC_MUTEX; +#endif + +#define HALMAC_DBG_MSG_LEVEL HALMAC_DBG_ERR + +/*[Driver] define the Platform SDIO Bus CLK */ +#define PLATFORM_SD_CLK 50000000 /*50MHz*/ + +#endif//_HALMAC_2_PLATFORM_H_ + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform_temp.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_2_platform_temp.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_func_8197f.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_func_8197f.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_func_8197f.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8197f/halmac_func_8197f.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/RTL8821Cfw_NIC.bin b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/RTL8821Cfw_NIC.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_func_8821c.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_func_8821c.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_func_8821c.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8821c/halmac_func_8821c.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/RTL8822Bfw_NIC.bin b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/RTL8822Bfw_NIC.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_func_8822b.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_func_8822b.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_func_8822b.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_8822b/halmac_func_8822b.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_88xx_cfg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_88xx_cfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_pcie.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_pcie.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_pcie.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_pcie.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_sdio.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_sdio.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_sdio.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_sdio.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_usb.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_usb.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_usb.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_api_88xx_usb.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_func_88xx.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_func_88xx.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_func_88xx.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_88xx/halmac_func_88xx.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_api.c b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_api.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_api.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_api.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit2.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit2.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit_8821c.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit_8821c.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit_8822b.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_bit_8822b.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_info.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_info.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_c2h_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_c2h_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_c2h_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_c2h_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_h2c_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_h2c_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_h2c_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_fw_offload_h2c_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_h2c_extra_info_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_h2c_extra_info_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_h2c_extra_info_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_h2c_extra_info_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg.h old mode 100755 new mode 100644 index 8f67cf45f73..b26d26cebbc --- a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg.h @@ -1,75 +1,75 @@ -#ifndef __HALMAC__HW_CFG_H__ -#define __HALMAC__HW_CFG_H__ - -/*-------------------------Modification Log----------------------------------- - 20120416 KaiYuan Add BIT Define --------------------------Modification Log-----------------------------------*/ - - -/*--------------------------Define -------------------------------------------*/ - -#if 1 -#ifndef BIT - #define BIT(x) (1 << (x)) -#endif -#endif - - -/* Interface define*/ - -#ifdef CONFIG_WLAN_HAL_8881A -#define HALMAC_8881A_SUPPORT 1 -#else -#define HALMAC_8881A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8192EE -#define HALMAC_8192E_SUPPORT 1 -#else -#define HALMAC_8192E_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8814AE -#define HALMAC_8814AMP_SUPPORT 1 -#define HALMAC_8814A_SUPPORT 1 -#else -#define HALMAC_8814AMP_SUPPORT 0 -#define HALMAC_8814A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8197F -#define HALMAC_8197F_SUPPORT 1 -#else -#define HALMAC_8197F_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8822BE -#define HALMAC_8822B_SUPPORT 1 -#else -#define HALMAC_8822B_SUPPORT 0 -#endif - - -#define HALMAC_8723A_SUPPORT 0 -#define HALMAC_8188E_SUPPORT 0 -#define HALMAC_8821A_SUPPORT 0 -#define HALMAC_8723B_SUPPORT 0 -#define HALMAC_8812A_SUPPORT 0 -#define HALMAC_8821B_SUPPORT 0 -#define HALMAC_8814B_SUPPORT 0 -#define HALMAC_8703B_SUPPORT 0 -#define HALMAC_8723D_SUPPORT 0 -#define HALMAC_8188F_SUPPORT 0 -#define HALMAC_8821BMP_SUPPORT 0 -#define HALMAC_8195A_SUPPORT 0 -#define HALMAC_8821B_SUPPORT 0 -#define HALMAC_8196F_SUPPORT 0 -#define HALMAC_8821C_SUPPORT 0 - - - - -#endif//__HALMAC__HW_CFG_H__ - - - +#ifndef __HALMAC__HW_CFG_H__ +#define __HALMAC__HW_CFG_H__ + +/*-------------------------Modification Log----------------------------------- + 20120416 KaiYuan Add BIT Define +-------------------------Modification Log-----------------------------------*/ + + +/*--------------------------Define -------------------------------------------*/ + +#if 1 +#ifndef BIT + #define BIT(x) (1 << (x)) +#endif +#endif + + +/* Interface define*/ + +#ifdef CONFIG_WLAN_HAL_8881A +#define HALMAC_8881A_SUPPORT 1 +#else +#define HALMAC_8881A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8192EE +#define HALMAC_8192E_SUPPORT 1 +#else +#define HALMAC_8192E_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8814AE +#define HALMAC_8814AMP_SUPPORT 1 +#define HALMAC_8814A_SUPPORT 1 +#else +#define HALMAC_8814AMP_SUPPORT 0 +#define HALMAC_8814A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8197F +#define HALMAC_8197F_SUPPORT 1 +#else +#define HALMAC_8197F_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8822BE +#define HALMAC_8822B_SUPPORT 1 +#else +#define HALMAC_8822B_SUPPORT 0 +#endif + + +#define HALMAC_8723A_SUPPORT 0 +#define HALMAC_8188E_SUPPORT 0 +#define HALMAC_8821A_SUPPORT 0 +#define HALMAC_8723B_SUPPORT 0 +#define HALMAC_8812A_SUPPORT 0 +#define HALMAC_8821B_SUPPORT 0 +#define HALMAC_8814B_SUPPORT 0 +#define HALMAC_8703B_SUPPORT 0 +#define HALMAC_8723D_SUPPORT 0 +#define HALMAC_8188F_SUPPORT 0 +#define HALMAC_8821BMP_SUPPORT 0 +#define HALMAC_8195A_SUPPORT 0 +#define HALMAC_8821B_SUPPORT 0 +#define HALMAC_8196F_SUPPORT 0 +#define HALMAC_8821C_SUPPORT 0 + + + + +#endif//__HALMAC__HW_CFG_H__ + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg_temp.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_hw_cfg_temp.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_c2h_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_c2h_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_c2h_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_c2h_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_h2c_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_h2c_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_h2c_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_original_h2c_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_pcie_reg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_pcie_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_pwr_seq_cmd.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_pwr_seq_cmd.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg2.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg2.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg_8821c.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg_8821c.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg_8822b.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_reg_8822b.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_chip.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_chip.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_bd_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_chip.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_chip.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_rx_desc_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_sdio_reg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_sdio_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_chip.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_chip.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_bd_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_ap.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_ap.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_chip.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_chip.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_nic.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_tx_desc_nic.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_type.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_type.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_usb_reg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmac_usb_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_bit.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_bit.h old mode 100755 new mode 100644 index 5b2efc28113..fcfaf45b718 --- a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_bit.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_bit.h @@ -1,697 +1,697 @@ -#ifndef __HALMAC_BB_RF_BIT_H__ -#define __HALMAC_BB_RF_BIT_H__ - - -/*-------------------------Modification Log----------------------------------- - --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ - -//3 ============Programming guide Start===================== -/* - BB BIT define rules - 1. For all bit define, it should be prefixed by "BIT_BB" - 2. For all bit mask, it should be prefixed by "BIT_MASK_BB" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_BB" - 4. For other case, prefix is not needed - - RF BIT define rules - 1. For all bit define, it should be prefixed by "BIT_RF" - 2. For all bit mask, it should be prefixed by "BIT_MASK_RF" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_RF" - 4. For other case, prefix is not needed - - SET BIT define rules - 1. Setting byte mask for BB or RF, it should be prefixed by "BIT_SET" - - Suffixed BIT define rules - 1. For AC chip, it should be suffixed by "_AC" - 2. For N chip, it should be suffixed by "_N" - 3. For Common bit define, it should be suffixed by "_COMMON" - -*/ -#if 1//IS_RTL88XX_AC -/**** page 8 ****/ - -//REG_BB_RCCKENABLE_AC offset:0x808 -#define BIT_MASK_BB_BOFDMEN_AC 0x20000000 -#define BIT_MASK_BB_BCCKEN_AC 0x10000000 -#define BIT_MASK_BB_BRXPATH_AC 0xff - -//REG_BB_RTXPATH_AC offset:0x80c -#define BIT_MASK_BB_BTXPATH_AC 0x0fffffff - -//REG_BB_RAGC_TABLE_AC offset:0x82c // AGC tabel select -#define BIT_MASK_BB_BAGC_TABLE_AC 0x3 - -//REG_BB_CCAONSEC_AC offset:0x838 -#define BIT_MASK_BB_CCA_AC 0xf - -//REG_BB_REDCCA_AC offset:0x8a4 // EDCCA -#define BIT_MASK_BB_BEDCCA_AC 0xffff - -//REG_BB_RHSSIREAD_AC offset:0x8b0 // RF read addr -#define BIT_MASK_BB_BHSSIREAD_ADDR_AC 0xff - -/**** page 9 ****/ -//REG_BB_AGC_TABLE_AC_V2 0x958 -#define BIT_MASK_BB_BAGC_TABLE_AC_V2 0x0000001f - - -/**** page a ****/ -//REG_BB_RCCK_SYSTEM_AC offset: 0xa00 // for cck sideband -#define BIT_MASK_BB_BCCK_SYSTEM_AC 0x10 -//REG_BB_RCCK_RX_AC offset: 0xa04 // for cck rx path selection -#define BIT_MASK_BB_BCCK_RX_AC 0x0c000000 -//REG_BB_RCCK_CCA_AC offset: 0xa08 // cca threshold -#define BIT_MASK_BB_BCCK_CCA_AC 0x00ff0000 - -// REG_BB_RCCK_TXFILTER1_AC offset: 0xa20 -#define BIT_MASK_BB_BCCK_TXFILTER1_C0_AC 0x00ff0000 -#define BIT_MASK_BB_BCCK_TXFILTER1_C1_AC 0xff000000 -//REG_BB_RCCK_TXFILTER2_AC offset: 0xa24 -#define BIT_MASK_BB_BCCK_TXFILTER2_C2_AC 0x000000ff -#define BIT_MASK_BB_BCCK_TXFILTER2_C3_AC 0x0000ff00 -#define BIT_MASK_BB_BCCK_TXFILTER2_C4_AC 0x00ff0000 -#define BIT_MASK_BB_BCCK_TXFILTER2_C5_AC 0xff000000 -//REG_BB_RCCK_TXFILTER3_AC offset: 0xa28 -#define BIT_MASK_BB_BCCK_TXFILTER3_C6_AC 0x000000ff -#define BIT_MASK_BB_BCCK_TXFILTER3_C7_AC 0x0000ff00 -//REG_BB_RCCK_FALSEALARM_AC offset: 0xa5c // counter for cck false alarm -#define BIT_MASK_BB_B_FALSEALARM_AC 0xffff -/**** page b ****/ -/**** page c ****/ -//REG_BB_AGC_TABLE_AC_V1 0xc1c -#define BIT_MASK_BB_BAGC_TABLE_AC_V1 0x00000f00 -//REG_BB_A_LSSIWRITE_AC offset :0xc90 -#define BIT_MASK_BB_LSSIWRITE_AC 0xf0000000 -/**** page d ****/ -/**** page e ****/ - - -#endif //#if IS_RTL88XX_AC - - -#if 1//IS_RTL88XX_N - -// -// 2. Page8(0x800) -// -#define BIT_MASK_BB_RFMOD_N_N 0x1 // Reg 0x800 rFPGA0_RFMOD -#define BIT_MASK_BB_JAPANMODE_N 0x2 -#define BIT_MASK_BB_CCKTXSC_N 0x30 -#define BIT_MASK_BB_CCKEN_N 0x1000000 -#define BIT_MASK_BB_OFDMEN_N 0x2000000 -#define BIT_MASK_BB_OFDMRXADCPHASE_N 0x10000 // Useless now -#define BIT_MASK_BB_OFDMTXDACPHASE_N 0x40000 - -#define BIT_MASK_BB_XATXAGC_N 0x3f -#define BIT_MASK_BB_XBTXAGC_N 0xf00 // Reg 80c rFPGA0_TxGainStage -/* -#define BIT_MASK_BB_XCTXAGC_N 0xf000 -#define BIT_MASK_BB_XDTXAGC_N 0xf0000 -*/ - -#define BIT_MASK_BB_PASTART_N 0xf0000000 // Useless now -#define BIT_MASK_BB_TRSTART_N 0x00f00000 -#define BIT_MASK_BB_RFSTART_N 0x0000f000 -#define BIT_MASK_BB_BBSTART_N 0x000000f0 -#define BIT_MASK_BB_BBCCKSTART_N 0x0000000f -#define BIT_MASK_BB_PAEND_N 0xf //Reg0x814 -#define BIT_MASK_BB_TREND_N 0x0f000000 -#define BIT_MASK_BB_RFEND_N 0x000f0000 -#define BIT_MASK_BB_CCAMASK_N 0x000000f0 //T2R -#define BIT_MASK_BB_R2RCCAMASK_N 0x00000f00 -#define BIT_MASK_BB_HSSI_R2TDELAY_N 0xf8000000 -#define BIT_MASK_BB_HSSI_T2RDELAY_N 0xf80000 -#define BIT_MASK_BB_CONTTXHSSI_N 0x400 //chane gain at continue Tx -#define BIT_MASK_BB_IGFROMCCK_N 0x200 -#define BIT_MASK_BB_AGCADDRESS_N 0x3f -#define BIT_MASK_BB_RXHPTX_N 0x7000 -#define BIT_MASK_BB_RXHPT2R_N 0x38000 -#define BIT_MASK_BB_RXHPCCKINI_N 0xc0000 -#define BIT_MASK_BB_AGCTXCODE_N 0xc00000 -#define BIT_MASK_BB_AGCRXCODE_N 0x300000 - -#define BIT_MASK_BB_3WIREDATALENGTH_N 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 -#define BIT_MASK_BB_3WIREADDRESSLENGTH_N 0x400 - -#define BIT_MASK_BB_3WIRERFPOWERDOWN_N 0x1 // Useless now -#define BIT_MASK_BB_5GPAPEPOLARITY_N 0x40000000 -#define BIT_MASK_BB_2GPAPEPOLARITY_N 0x80000000 -#define BIT_MASK_BB_RFSW_TXDEFAULTANT_N 0x3 -#define BIT_MASK_BB_RFSW_TXOPTIONANT_N 0x30 -#define BIT_MASK_BB_RFSW_RXDEFAULTANT_N 0x300 -#define BIT_MASK_BB_RFSW_RXOPTIONANT_N 0x3000 -#define BIT_MASK_BB_RFSI_3WIREDATA_N 0x1 -#define BIT_MASK_BB_RFSI_3WIRECLOCK_N 0x2 -#define BIT_MASK_BB_RFSI_3WIRELOAD_N 0x4 -#define BIT_MASK_BB_RFSI_3WIRERW_N 0x8 -#define BIT_MASK_BB_RFSI_3WIRE_N 0xf - -#define BIT_MASK_BB_RFSI_RFENV_N 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW -#define BIT_MASK_BB_RFSI_TRSW_N 0x20 // Useless now -#define BIT_MASK_BB_RFSI_TRSWB_N 0x40 -#define BIT_MASK_BB_RFSI_ANTSW_N 0x100 -#define BIT_MASK_BB_RFSI_ANTSWB_N 0x200 -#define BIT_MASK_BB_RFSI_PAPE_N 0x400 -#define BIT_MASK_BB_RFSI_PAPE5G_N 0x800 -#define BIT_MASK_BB_BANDSELECT_N 0x1 -#define BIT_MASK_BB_HTSIG2_GI_N 0x80 -#define BIT_MASK_BB_HTSIG2_SMOOTHING_N 0x01 -#define BIT_MASK_BB_HTSIG2_SOUNDING_N 0x02 -#define BIT_MASK_BB_HTSIG2_AGGREATON_N 0x08 -#define BIT_MASK_BB_HTSIG2_STBC_N 0x30 -#define BIT_MASK_BB_HTSIG2_ADVCODING_N 0x40 -#define BIT_MASK_BB_HTSIG2_NUMOFHTLTF_N 0x300 -#define BIT_MASK_BB_HTSIG2_CRC8_N 0x3fc -#define BIT_MASK_BB_HTSIG1_MCS_N 0x7f -#define BIT_MASK_BB_HTSIG1_BANDWIDTH_N 0x80 -#define BIT_MASK_BB_HTSIG1_HTLENGTH_N 0xffff -#define BIT_MASK_BB_LSIG_RATE_N 0xf -#define BIT_MASK_BB_LSIG_RESERVED_N 0x10 -#define BIT_MASK_BB_LSIG_LENGTH_N 0x1fffe -#define BIT_MASK_BB_LSIG_PARITY_N 0x20 -#define BIT_MASK_BB_CCKRXPHASE_N 0x4 - -//#define BIT_MASK_BB_LSSIREADADDRESS 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 -#define BIT_MASK_BB_LSSIREADADDRESS_N 0x7f800000 // T65 RF -#define BIT_MASK_BB_LSSIREADEDGE_N 0x80000000 //LSSI "Read" edge signal - -//#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack -#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfffff // T65 RF - -#define BIT_MASK_BB_LSSIREADOKFLAG_N 0x1000 // Useless now -#define BIT_MASK_BB_CCKSAMPLERATE_N 0x8 //0: 44MHz, 1:88MHz -#define BIT_MASK_BB_REGULATOR0STANDBY_N 0x1 -#define BIT_MASK_BB_REGULATORPLLSTANDBY_N 0x2 -#define BIT_MASK_BB_REGULATOR1STANDBY_N 0x4 -#define BIT_MASK_BB_PLLPOWERUP_N 0x8 -#define BIT_MASK_BB_DPLLPOWERUP_N 0x10 -#define BIT_MASK_BB_DA10POWERUP_N 0x20 -#define BIT_MASK_BB_AD7POWERUP_N 0x200 -#define BIT_MASK_BB_DA6POWERUP_N 0x2000 -#define BIT_MASK_BB_XTALPOWERUP_N 0x4000 -#define BIT_MASK_BB_40MDCLKPOWERUP_N 0x8000 -#define BIT_MASK_BB_DA6DEBUGMODE_N 0x20000 -#define BIT_MASK_BB_DA6SWING_N 0x380000 - -#define BIT_MASK_BB_ADCLKPHASE_N 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ - -#define BIT_MASK_BB_80MCLKDELAY_N 0x18000000 // Useless -#define BIT_MASK_BB_AFEWATCHDOGENABLE_N 0x20000000 - -#define BIT_MASK_BB_XTALCAP01_N 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap -#define BIT_MASK_BB_XTALCAP23_N 0x3 -#define BIT_MASK_BB_XTALCAP92X_N 0x0f000000 - -#define BIT_MASK_BB_INTDIFCLKENABLE_N 0x400 // Useless -#define BIT_MASK_BB_EXTSIGCLKENABLE_N 0x800 -#define BIT_MASK_BB_BANDGAPMBIASPOWERUP_N 0x10000 -#define BIT_MASK_BB_AD11SHGAIN_N 0xc0000 -#define BIT_MASK_BB_AD11INPUTRANGE_N 0x700000 -#define BIT_MASK_BB_AD11OPCURRENT_N 0x3800000 -#define BIT_MASK_BB_IPATHLOOPBACK_N 0x4000000 -#define BIT_MASK_BB_QPATHLOOPBACK_N 0x8000000 -#define BIT_MASK_BB_AFELOOPBACK_N 0x10000000 -#define BIT_MASK_BB_DA10SWING_N 0x7e0 -#define BIT_MASK_BB_DA10REVERSE_N 0x800 -#define BIT_MASK_BB_DACLKSOURCE_N 0x1000 -#define BIT_MASK_BB_AD7INPUTRANGE_N 0x6000 -#define BIT_MASK_BB_AD7GAIN_N 0x38000 -#define BIT_MASK_BB_AD7OUTPUTCMMODE_N 0x40000 -#define BIT_MASK_BB_AD7INPUTCMMODE_N 0x380000 -#define BIT_MASK_BB_AD7CURRENT_N 0xc00000 -#define BIT_MASK_BB_REGULATORADJUST_N 0x7000000 -#define BIT_MASK_BB_AD11POWERUPATTX_N 0x1 -#define BIT_MASK_BB_DA10PSATTX_N 0x10 -#define BIT_MASK_BB_AD11POWERUPATRX_N 0x100 -#define BIT_MASK_BB_DA10PSATRX_N 0x1000 -#define BIT_MASK_BB_CCKRXAGCFORMAT_N 0x200 -#define BIT_MASK_BB_PSDFFTSAMPLEPPOINT_N 0xc000 -#define BIT_MASK_BB_PSDAVERAGENUM_N 0x3000 -#define BIT_MASK_BB_IQPATHCONTROL_N 0xc00 -#define BIT_MASK_BB_PSDFREQ_N 0x3ff -#define BIT_MASK_BB_PSDANTENNAPATH_N 0x30 -#define BIT_MASK_BB_PSDIQSWITCH_N 0x40 -#define BIT_MASK_BB_PSDRXTRIGGER_N 0x400000 -#define BIT_MASK_BB_PSDTXTRIGGER_N 0x80000000 -#define BIT_MASK_BB_PSDSINETONESCALE_N 0x7f000000 -#define BIT_MASK_BB_PSDREPORT_N 0xffff - - -// -// 3. Page9(0x900) -// -#define BIT_MASK_BB_OFDMTXSC_N 0x30000000 // Useless -#define BIT_MASK_BB_CCKTXON_N 0x1 -#define BIT_MASK_BB_OFDMTXON_N 0x2 -#define BIT_MASK_BB_DEBUGPAGE_N 0xfff //reset debug page and also HWord, LWord -#define BIT_MASK_BB_DEBUGITEM_N 0xff //reset debug page and LWord -#define BIT_MASK_BB_ANTL_N 0x10 -#define BIT_MASK_BB_ANTNONHT_N 0x100 -#define BIT_MASK_BB_ANTHT1_N 0x1000 -#define BIT_MASK_BB_ANTHT2_N 0x10000 -#define BIT_MASK_BB_ANTHT1S1_N 0x100000 -#define BIT_MASK_BB_ANTNONHTS1_N 0x1000000 - - -// -// 4. PageA(0xA00) -// -#define BIT_MASK_BB_CCKBBMODE_N 0x3 // Useless -#define BIT_MASK_BB_CCKTXPOWERSAVING_N 0x80 -#define BIT_MASK_BB_CCKRXPOWERSAVING_N 0x40 -#define BIT_MASK_BB_CCKSIDEBAND_N 0x10 // Reg 0xa00 rCCK0_System 20/40 switch -#define BIT_MASK_BB_CCKSCRAMBLE_N 0x8 // Useless -#define BIT_MASK_BB_CCKANTDIVERSITY_N 0x8000 -#define BIT_MASK_BB_CCKCARRIERRECOVERY_N 0x4000 -#define BIT_MASK_BB_CCKTXRATE_N 0x3000 -#define BIT_MASK_BB_CCKDCCANCEL_N 0x0800 -#define BIT_MASK_BB_CCKISICANCEL_N 0x0400 -#define BIT_MASK_BB_CCKMATCHFILTER_N 0x0200 -#define BIT_MASK_BB_CCKEQUALIZER_N 0x0100 -#define BIT_MASK_BB_CCKPREAMBLEDETECT_N 0x800000 -#define BIT_MASK_BB_CCKFASTFALSECCA_N 0x400000 -#define BIT_MASK_BB_CCKCHESTSTART_N 0x300000 -#define BIT_MASK_BB_CCKCCACOUNT_N 0x080000 -#define BIT_MASK_BB_CCKCS_LIM_N 0x070000 -#define BIT_MASK_BB_CCKBISTMODE_N 0x80000000 -#define BIT_MASK_BB_CCKCCAMASK_N 0x40000000 -#define BIT_MASK_BB_CCKTXDACPHASE_N 0x4 -#define BIT_MASK_BB_CCKRXADCPHASE_N 0x20000000 //r_rx_clk -#define BIT_MASK_BB_CCKR_CP_MODE0_N 0x0100 -#define BIT_MASK_BB_CCKTXDCOFFSET_N 0xf0 -#define BIT_MASK_BB_CCKRXDCOFFSET_N 0xf -#define BIT_MASK_BB_CCKCCAMODE_N 0xc000 -#define BIT_MASK_BB_CCKFALSECS_LIM_N 0x3f00 -#define BIT_MASK_BB_CCKCS_RATIO_N 0xc00000 -#define BIT_MASK_BB_CCKCORGBIT_SEL_N 0x300000 -#define BIT_MASK_BB_CCKPD_LIM_N 0x0f0000 -#define BIT_MASK_BB_CCKNEWCCA_N 0x80000000 -#define BIT_MASK_BB_CCKRXHPOFIG_N 0x8000 -#define BIT_MASK_BB_CCKRXIG_N 0x7f00 -#define BIT_MASK_BB_CCKLNAPOLARITY_N 0x800000 -#define BIT_MASK_BB_CCKRX1STGAIN_N 0x7f0000 -#define BIT_MASK_BB_CCKRFEXTEND_N 0x20000000 //CCK Rx Iinital gain polarity -#define BIT_MASK_BB_CCKRXAGCSATLEVEL_N 0x1f000000 -#define BIT_MASK_BB_CCKRXAGCSATCOUNT_N 0xe0 -#define BIT_MASK_BB_CCKRXRFSETTLE_N 0x1f //AGCsamp_dly -#define BIT_MASK_BB_CCKFIXEDRXAGC_N 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define BIT_MASK_BB_CCKANTENNAPOLARITY_N 0x2000 -#define BIT_MASK_BB_CCKTXFILTERTYPE_N 0x0c00 -#define BIT_MASK_BB_CCKRXAGCREPORTTYPE_N 0x0300 -#define BIT_MASK_BB_CCKRXDAGCEN_N 0x80000000 -#define BIT_MASK_BB_CCKRXDAGCPERIOD_N 0x20000000 -#define BIT_MASK_BB_CCKRXDAGCSATLEVEL_N 0x1f000000 -#define BIT_MASK_BB_CCKTIMINGRECOVERY_N 0x800000 -#define BIT_MASK_BB_CCKTXC0_N 0x3f0000 -#define BIT_MASK_BB_CCKTXC1_N 0x3f000000 -#define BIT_MASK_BB_CCKTXC2_N 0x3f -#define BIT_MASK_BB_CCKTXC3_N 0x3f00 -#define BIT_MASK_BB_CCKTXC4_N 0x3f0000 -#define BIT_MASK_BB_CCKTXC5_N 0x3f000000 -#define BIT_MASK_BB_CCKTXC6_N 0x3f -#define BIT_MASK_BB_CCKTXC7_N 0x3f00 -#define BIT_MASK_BB_CCKDEBUGPORT_N 0xff0000 -#define BIT_MASK_BB_CCKDACDEBUG_N 0x0f000000 -#define BIT_MASK_BB_CCKFALSEALARMENABLE_N 0x8000 -#define BIT_MASK_BB_CCKFALSEALARMREAD_N 0x4000 -#define BIT_MASK_BB_CCKTRSSI_N 0x7f -#define BIT_MASK_BB_CCKRXAGCREPORT_N 0xfe -#define BIT_MASK_BB_CCKRXREPORT_ANTSEL_N 0x80000000 -#define BIT_MASK_BB_CCKRXREPORT_MFOFF_N 0x40000000 -#define BIT_MASK_BB_CCKRXRXREPORT_SQLOSS_N 0x20000000 -#define BIT_MASK_BB_CCKRXREPORT_PKTLOSS_N 0x10000000 -#define BIT_MASK_BB_CCKRXREPORT_LOCKEDBIT_N 0x08000000 -#define BIT_MASK_BB_CCKRXREPORT_RATEERROR_N 0x04000000 -#define BIT_MASK_BB_CCKRXREPORT_RXRATE_N 0x03000000 -#define BIT_MASK_BB_CCKRXFACOUNTERLOWER_N 0xff -#define BIT_MASK_BB_CCKRXFACOUNTERUPPER_N 0xff000000 -#define BIT_MASK_BB_CCKRXHPAGCSTART_N 0xe000 -#define BIT_MASK_BB_CCKRXHPAGCFINAL_N 0x1c00 -#define BIT_MASK_BB_CCKRXFALSEALARMENABLE_N 0x8000 -#define BIT_MASK_BB_CCKFACOUNTERFREEZE_N 0x4000 -#define BIT_MASK_BB_CCKTXPATHSEL_N 0x10000000 -#define BIT_MASK_BB_CCKDEFAULTRXPATH_N 0xc000000 -#define BIT_MASK_BB_CCKOPTIONRXPATH_N 0x3000000 - - -// -// 5. PageC(0xC00) -// -#define BIT_MASK_BB_NUMOFSTF_N 0x3 // Useless -#define BIT_MASK_BB_SHIFT_L_N 0xc0 -#define BIT_MASK_BB_GI_TH_N 0xc -#define BIT_MASK_BB_RXPATHA_N 0x1 -#define BIT_MASK_BB_RXPATHB_N 0x2 -#define BIT_MASK_BB_RXPATHC_N 0x4 -#define BIT_MASK_BB_RXPATHD_N 0x8 -#define BIT_MASK_BB_TXPATHA_N 0x1 -#define BIT_MASK_BB_TXPATHB_N 0x2 -#define BIT_MASK_BB_TXPATHC_N 0x4 -#define BIT_MASK_BB_TXPATHD_N 0x8 -#define BIT_MASK_BB_TRSSIFREQ_N 0x200 -#define BIT_MASK_BB_ADCBACKOFF_N 0x3000 -#define BIT_MASK_BB_DFIRBACKOFF_N 0xc000 -#define BIT_MASK_BB_TRSSILATCHPHASE_N 0x10000 -#define BIT_MASK_BB_RXIDCOFFSET_N 0xff -#define BIT_MASK_BB_RXQDCOFFSET_N 0xff00 -#define BIT_MASK_BB_RXDFIRMODE_N 0x1800000 -#define BIT_MASK_BB_RXDCNFTYPE_N 0xe000000 -#define BIT_MASK_BB_RXIQIMB_A_N 0x3ff -#define BIT_MASK_BB_RXIQIMB_B_N 0xfc00 -#define BIT_MASK_BB_RXIQIMB_C_N 0x3f0000 -#define BIT_MASK_BB_RXIQIMB_D_N 0xffc00000 -#define BIT_MASK_BB_DC_DC_NOTCH_N 0x60000 -#define BIT_MASK_BB_RXNBINOTCH_N 0x1f000000 -#define BIT_MASK_BB_PD_TH_N 0xf -#define BIT_MASK_BB_PD_TH_OPT2_N 0xc000 -#define BIT_MASK_BB_PWED_TH_N 0x700 -#define BIT_MASK_BB_IFMF_WIN_L_N 0x800 -#define BIT_MASK_BB_PD_OPTION_N 0x1000 -#define BIT_MASK_BB_MF_WIN_L_N 0xe000 -#define BIT_MASK_BB_BW_SEARCH_L_N 0x30000 -#define BIT_MASK_BB_WIN_ENH_L_N 0xc0000 -#define BIT_MASK_BB_BW_TH_N 0x700000 -#define BIT_MASK_BB_ED_TH2_N 0x3800000 -#define BIT_MASK_BB_BW_OPTION_N 0x4000000 -#define BIT_MASK_BB_RATIO_TH_N 0x18000000 -#define BIT_MASK_BB_WINDOW_L_N 0xe0000000 -#define BIT_MASK_BB_SBD_OPTION_N 0x1 -#define BIT_MASK_BB_FRAME_TH_N 0x1c -#define BIT_MASK_BB_FS_OPTION_N 0x60 -#define BIT_MASK_BB_DC_SLOPE_CHECK_N 0x80 -#define BIT_MASK_BB_FGUARD_COUNTER_DC_L_N 0xe00 -#define BIT_MASK_BB_FRAME_WEIGHT_SHORT_N 0x7000 -#define BIT_MASK_BB_SUB_TUNE_N 0xe00000 -#define BIT_MASK_BB_FRAME_DC_LENGTH_N 0xe000000 -#define BIT_MASK_BB_SBD_START_OFFSET_N 0x30000000 -#define BIT_MASK_BB_FRAME_TH_2_N 0x7 -#define BIT_MASK_BB_FRAME_GI2_TH_N 0x38 -#define BIT_MASK_BB_GI2_SYNC_EN_N 0x40 -#define BIT_MASK_BB_SARCH_SHORT_EARLY_N 0x300 -#define BIT_MASK_BB_SARCH_SHORT_LATE_N 0xc00 -#define BIT_MASK_BB_SARCH_GI2_LATE_N 0x70000 -#define BIT_MASK_BB_CFOANTSUM_N 0x1 -#define BIT_MASK_BB_CFOACC_N 0x2 -#define BIT_MASK_BB_CFOSTARTOFFSET_N 0xc -#define BIT_MASK_BB_CFOLOOKBACK_N 0x70 -#define BIT_MASK_BB_CFOSUMWEIGHT_N 0x80 -#define BIT_MASK_BB_DAGCENABLE_N 0x10000 -#define BIT_MASK_BB_TXIQIMB_A_N 0x3ff -#define BIT_MASK_BB_TXIQIMB_B_N 0xfc00 -#define BIT_MASK_BB_TXIQIMB_C_N 0x3f0000 -#define BIT_MASK_BB_TXIQIMB_D_N 0xffc00000 -#define BIT_MASK_BB_TXIDCOFFSET_N 0xff -#define BIT_MASK_BB_TXQDCOFFSET_N 0xff00 -#define BIT_MASK_BB_TXDFIRMODE_N 0x10000 -#define BIT_MASK_BB_TXPESUDONOISEON_N 0x4000000 -#define BIT_MASK_BB_TXPESUDONOISE_A_N 0xff -#define BIT_MASK_BB_TXPESUDONOISE_B_N 0xff00 -#define BIT_MASK_BB_TXPESUDONOISE_C_N 0xff0000 -#define BIT_MASK_BB_TXPESUDONOISE_D_N 0xff000000 -#define BIT_MASK_BB_CCADROPOPTION_N 0x20000 -#define BIT_MASK_BB_CCADROPTHRES_N 0xfff00000 -#define BIT_MASK_BB_EDCCA_H_N 0xf -#define BIT_MASK_BB_EDCCA_L_N 0xf0 -#define BIT_MASK_BB_LAMBDA_ED_N 0x300 -#define BIT_MASK_BB_RXINITIALGAIN_N 0x7f -#define BIT_MASK_BB_RXANTDIVEN_N 0x80 -#define BIT_MASK_BB_RXAGCADDRESSFORLNA_N 0x7f00 -#define BIT_MASK_BB_RXHIGHPOWERFLOW_N 0x8000 -#define BIT_MASK_BB_RXAGCFREEZETHRES_N 0xc0000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC1_N 0x300000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC2_N 0xc00000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC3_N 0x3000000 -#define BIT_MASK_BB_RXFREEZESTEP_AGC0_N 0xc000000 -#define BIT_MASK_BB_RXRSSI_CMP_EN_N 0x10000000 -#define BIT_MASK_BB_RXQUICKAGCEN_N 0x20000000 -#define BIT_MASK_BB_RXAGCFREEZETHRESMODE_N 0x40000000 -#define BIT_MASK_BB_RXOVERFLOWCHECKTYPE_N 0x80000000 -#define BIT_MASK_BB_RXAGCSHIFT_N 0x7f -#define BIT_MASK_BB_TRSW_TRI_ONLY_N 0x80 -#define BIT_MASK_BB_POWERTHRES_N 0x300 -#define BIT_MASK_BB_RXAGCEN_N 0x1 -#define BIT_MASK_BB_RXAGCTOGETHEREN_N 0x2 -#define BIT_MASK_BB_RXAGCMIN_N 0x4 -#define BIT_MASK_BB_RXHP_INI_N 0x7 -#define BIT_MASK_BB_RXHP_TRLNA_N 0x70 -#define BIT_MASK_BB_RXHP_RSSI_N 0x700 -#define BIT_MASK_BB_RXHP_BBP1_N 0x7000 -#define BIT_MASK_BB_RXHP_BBP2_N 0x70000 -#define BIT_MASK_BB_RXHP_BBP3_N 0x700000 -#define BIT_MASK_BB_RSSI_H_N 0x7f0000 //the threshold for high power -#define BIT_MASK_BB_RSSI_GEN_N 0x7f000000 //the threshold for ant diversity -#define BIT_MASK_BB_RXSETTLE_TRSW_N 0x7 -#define BIT_MASK_BB_RXSETTLE_LNA_N 0x38 -#define BIT_MASK_BB_RXSETTLE_RSSI_N 0x1c0 -#define BIT_MASK_BB_RXSETTLE_BBP_N 0xe00 -#define BIT_MASK_BB_RXSETTLE_RXHP_N 0x7000 -#define BIT_MASK_BB_RXSETTLE_ANTSW_RSSI_N 0x38000 -#define BIT_MASK_BB_RXSETTLE_ANTSW_N 0xc0000 -#define BIT_MASK_BB_RXPROCESSTIME_DAGC_N 0x300000 -#define BIT_MASK_BB_RXSETTLE_HSSI_N 0x400000 -#define BIT_MASK_BB_RXPROCESSTIME_BBPPW_N 0x800000 -#define BIT_MASK_BB_RXANTENNAPOWERSHIFT_N 0x3000000 -#define BIT_MASK_BB_RSSITABLESELECT_N 0xc000000 -#define BIT_MASK_BB_RXHP_FINAL_N 0x7000000 -#define BIT_MASK_BB_RXHTSETTLE_BBP_N 0x7 -#define BIT_MASK_BB_RXHTSETTLE_HSSI_N 0x8 -#define BIT_MASK_BB_RXHTSETTLE_RXHP_N 0x70 -#define BIT_MASK_BB_RXHTSETTLE_BBPPW_N 0x80 -#define BIT_MASK_BB_RXHTSETTLE_IDLE_N 0x300 -#define BIT_MASK_BB_RXHTSETTLE_RESERVED_N 0x1c00 -#define BIT_MASK_BB_RXHTRXHPEN_N 0x8000 -#define BIT_MASK_BB_RXHTAGCFREEZETHRES_N 0x30000 -#define BIT_MASK_BB_RXHTAGCTOGETHEREN_N 0x40000 -#define BIT_MASK_BB_RXHTAGCMIN_N 0x80000 -#define BIT_MASK_BB_RXHTAGCEN_N 0x100000 -#define BIT_MASK_BB_RXHTDAGCEN_N 0x200000 -#define BIT_MASK_BB_RXHTRXHP_BBP_N 0x1c00000 -#define BIT_MASK_BB_RXHTRXHP_FINAL_N 0xe0000000 -#define BIT_MASK_BB_RXPWRATIOTH_N 0x3 -#define BIT_MASK_BB_RXPWRATIOEN_N 0x4 -#define BIT_MASK_BB_RXMFHOLD_N 0x3800 -#define BIT_MASK_BB_RXPD_DELAY_TH1_N 0x38 -#define BIT_MASK_BB_RXPD_DELAY_TH2_N 0x1c0 -#define BIT_MASK_BB_RXPD_DC_COUNT_MAX_N 0x600 -//#define bRxMF_Hold 0x3800 -#define BIT_MASK_BB_RxPD_Delay_TH_N 0x8000 -#define BIT_MASK_BB_RxProcess_Delay_N 0xf0000 -#define BIT_MASK_BB_RxSearchrange_GI2_Early_N 0x700000 -#define BIT_MASK_BB_RxFrame_Guard_Counter_L_N 0x3800000 -#define BIT_MASK_BB_RxSGI_Guard_L_N 0xc000000 -#define BIT_MASK_BB_RxSGI_Search_L_N 0x30000000 -#define BIT_MASK_BB_RxSGI_TH_N 0xc0000000 -#define BIT_MASK_BB_DFSCnt0_N 0xff -#define BIT_MASK_BB_DFSCnt1_N 0xff00 -#define BIT_MASK_BB_DFSFlag_N 0xf0000 -#define BIT_MASK_BB_MFWeightSum_N 0x300000 -#define BIT_MASK_BB_MinIdxTH_N 0x7f000000 -#define BIT_MASK_BB_DAFormat_N 0x40000 -#define BIT_MASK_BB_TxChEmuEnable_N 0x01000000 -#define BIT_MASK_BB_TRSWIsolation_A_N 0x7f -#define BIT_MASK_BB_TRSWIsolation_B_N 0x7f00 -/* -#define BIT_MASK_BB_TRSWIsolation_C_N 0x7f0000 -#define BIT_MASK_BB_TRSWIsolation_D_N 0x7f000000 -*/ -#define BIT_MASK_BB_ExtLNAGain_N 0x7c00 - - -// -// 6. PageE(0xE00) -// -#define BIT_MASK_BB_STBCEN_N 0x4 // Useless -#define BIT_MASK_BB_ANTENNAMAPPING_N 0x10 -#define BIT_MASK_BB_NSS_N 0x20 -#define BIT_MASK_BB_CFOANTSUMD_N 0x200 -#define BIT_MASK_BB_OFDMDISPWSAVTX_N 0x400000 -#define BIT_MASK_BB_PHYCOUNTERRESET_N 0x8000000 -#define BIT_MASK_BB_CFOREPORTGET_N 0x4000000 -#define BIT_MASK_BB_OFDMCONTINUETX_N 0x10000000 -#define BIT_MASK_BB_OFDMSINGLECARRIER_N 0x20000000 -#define BIT_MASK_BB_OFDMSINGLETONE_N 0x40000000 -/* -#define bRxPath1 0x01 -#define bRxPath2 0x02 -#define bRxPath3 0x04 -#define bRxPath4 0x08 -#define bTxPath1 0x10 -#define bTxPath2 0x20 -*/ -#define BIT_MASK_BB_HTDETECT_N 0x100 -#define BIT_MASK_BB_CFOEN_N 0x10000 -#define BIT_MASK_BB_CFOVALUE_N 0xfff00000 -#define BIT_MASK_BB_SIGTONE_RE_N 0x3f -#define BIT_MASK_BB_SIGTONE_IM_N 0x7f00 -#define BIT_MASK_BB_COUNTER_CCA_N 0xffff -#define BIT_MASK_BB_COUNTER_PARITYFAIL_N 0xffff0000 -#define BIT_MASK_BB_COUNTER_RATEILLEGAL_N 0xffff -#define BIT_MASK_BB_COUNTER_CRC8FAIL_N 0xffff0000 -#define BIT_MASK_BB_COUNTER_MCSNOSUPPORT_N 0xffff -#define BIT_MASK_BB_COUNTER_FASTSYNC_N 0xffff -#define BIT_MASK_BB_SHORTCFO_N 0xfff -#define BIT_MASK_BB_SHORTCFOTLENGTH_N 12 //total -#define BIT_MASK_BB_SHORTCFOFLENGTH_N 11 //fraction -#define BIT_MASK_BB_LONGCFO_N 0x7ff -#define BIT_MASK_BB_LONGCFOTLENGTH_N 11 -#define BIT_MASK_BB_LONGCFOFLENGTH_N 11 -#define BIT_MASK_BB_TAILCFO_N 0x1fff -#define BIT_MASK_BB_TAILCFOTLENGTH_N 13 -#define BIT_MASK_BB_TAILCFOFLENGTH_N 12 -#define BIT_MASK_BB_MAX_EN_PWDB_N 0xffff -#define BIT_MASK_BB_CC_POWER_DB_N 0xffff0000 -#define BIT_MASK_BB_NOISE_PWDB_N 0xffff -#define BIT_MASK_BB_POWERMEASTLENGTH_N 10 -#define BIT_MASK_BB_POWERMEASFLENGTH_N 3 -#define BIT_MASK_BB_RX_HT_BW_N 0x1 -#define BIT_MASK_BB_RXSC_N 0x6 -#define BIT_MASK_BB_RX_HT_N 0x8 -#define BIT_MASK_BB_NB_INTF_DET_ON_N 0x1 -#define BIT_MASK_BB_INTF_WIN_LEN_CFG_N 0x30 -#define BIT_MASK_BB_NB_INTF_TH_CFG_N 0x1c0 -#define BIT_MASK_BB_RFGAIN_N 0x3f -#define BIT_MASK_BB_TABLESEL_N 0x40 -#define BIT_MASK_BB_TRSW_N 0x80 -#define BIT_MASK_BB_RXSNR_A_N 0xff -#define BIT_MASK_BB_RXSNR_B_N 0xff00 -/* -#define BIT_MASK_BB_RXSNR_C_N 0xff0000 -#define BIT_MASK_BB_RXSNR_D_N 0xff000000 -*/ -#define BIT_MASK_BB_SNREVMTLENGTH_N 8 -#define BIT_MASK_BB_SNREVMFLENGTH_N 1 -#define BIT_MASK_BB_CSI1ST_N 0xff -#define BIT_MASK_BB_CSI2ND_N 0xff00 -#define BIT_MASK_BB_RXEVM1ST_N 0xff0000 -#define BIT_MASK_BB_RXEVM2ND_N 0xff000000 -#define BIT_MASK_BB_SIGEVM_N 0xff -#define BIT_MASK_BB_PWDB_N 0xff00 -#define BIT_MASK_BB_SGIEN_N 0x10000 - -#define BIT_MASK_BB_SFACTORQAM1_N 0xf // Useless -#define BIT_MASK_BB_SFACTORQAM2_N 0xf0 -#define BIT_MASK_BB_SFACTORQAM3_N 0xf00 -#define BIT_MASK_BB_SFACTORQAM4_N 0xf000 -#define BIT_MASK_BB_SFACTORQAM5_N 0xf0000 -#define BIT_MASK_BB_SFACTORQAM6_N 0xf0000 -#define BIT_MASK_BB_SFACTORQAM7_N 0xf00000 -#define BIT_MASK_BB_SFACTORQAM8_N 0xf000000 -#define BIT_MASK_BB_SFACTORQAM9_N 0xf0000000 -#define BIT_MASK_BB_CSISCHEME_N 0x100000 - -#define BIT_MASK_BB_NOISELVLTOPSET_N 0x3 // Useless -#define BIT_MASK_BB_CHSMOOTH_N 0x4 -#define BIT_MASK_BB_CHSMOOTHCFG1_N 0x38 -#define BIT_MASK_BB_CHSMOOTHCFG2_N 0x1c0 -#define BIT_MASK_BB_CHSMOOTHCFG3_N 0xe00 -#define BIT_MASK_BB_CHSMOOTHCFG4_N 0x7000 -#define BIT_MASK_BB_MRCMODE_N 0x800000 -#define BIT_MASK_BB_THEVMCFG_N 0x7000000 - -#define BIT_MASK_BB_LOOPFITTYPE_N 0x1 // Useless -#define BIT_MASK_BB_UPDCFO_N 0x40 -#define BIT_MASK_BB_UPDCFOOFFDATA_N 0x80 -#define BIT_MASK_BB_ADVUPDCFO_N 0x100 -#define BIT_MASK_BB_ADVTIMECTRL_N 0x800 -#define BIT_MASK_BB_UPDCLKO_N 0x1000 -#define BIT_MASK_BB_FC_N 0x6000 -#define BIT_MASK_BB_TRACKINGMODE_N 0x8000 -#define BIT_MASK_BB_PHCMPENABLE_N 0x10000 -#define BIT_MASK_BB_UPDCLKOLTF_N 0x20000 -#define BIT_MASK_BB_COMCHCFO_N 0x40000 -#define BIT_MASK_BB_CSIESTIMODE_N 0x80000 -#define BIT_MASK_BB_ADVUPDEQZ_N 0x100000 -#define BIT_MASK_BB_UCHCFG_N 0x7000000 -#define BIT_MASK_BB_UPDEQZ_N 0x8000000 - -#define BIT_MASK_BB_TXAGCRATE18_06_N 0x7f7f7f7f // Useless -#define BIT_MASK_BB_TXAGCRATE54_24_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS32_N 0x7f -#define BIT_MASK_BB_TXAGCRATECCK_N 0x7f00 -#define BIT_MASK_BB_TXAGCRATEMCS3_MCS0_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS7_MCS4_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS11_MCS8_N 0x7f7f7f7f -#define BIT_MASK_BB_TXAGCRATEMCS15_MCS12_N 0x7f7f7f7f - -//Rx Pseduo noise -#define BIT_MASK_BB_RXPESUDONOISEON_N 0x20000000 // Useless -#define BIT_MASK_BB_RXPESUDONOISE_A_N 0xff -#define BIT_MASK_BB_RXPESUDONOISE_B_N 0xff00 -/* -#define BIT_MASK_BB_RXPESUDONOISE_C_N 0xff0000 -#define BIT_MASK_BB_RXPESUDONOISE_D_N 0xff000000 -*/ -#define BIT_MASK_BB_PESUDONOISESTATE_A_N 0xffff -#define BIT_MASK_BB_PESUDONOISESTATE_B_N 0xffff0000 -/* -#define BIT_MASK_BB_PESUDONOISESTATE_C_N 0xffff -#define BIT_MASK_BB_PESUDONOISESTATE_D_N 0xffff0000 -*/ - - -// -//7. RF Register -// -//Zebra1 -#define BIT_MASK_RF_ZEBRA1_HSSIENABLE_N 0x8 // Useless -#define BIT_MASK_RF_ZEBRA1_TRXCONTROL_N 0xc00 -#define BIT_MASK_RF_ZEBRA1_TRXGAINSETTING_N 0x07f -#define BIT_MASK_RF_ZEBRA1_RXCORNER_N 0xc00 -#define BIT_MASK_RF_ZEBRA1_TXCHARGEPUMP_N 0x38 -#define BIT_MASK_RF_ZEBRA1_RXCHARGEPUMP_N 0x7 -#define BIT_MASK_RF_ZEBRA1_CHANNELNUM_N 0xf80 -#define BIT_MASK_RF_ZEBRA1_TXLPFBW_N 0x400 -#define BIT_MASK_RF_ZEBRA1_RXLPFBW_N 0x600 - -//Zebra4 -#define BIT_MASK_RF_RTL8256REGMODECTRL1_N 0x100 // Useless -#define BIT_MASK_RF_RTL8256REGMODECTRL0_N 0x40 -#define BIT_MASK_RF_RTL8256_TXLPFBW_N 0x18 -#define BIT_MASK_RF_RTL8256_RXLPFBW_N 0x600 - -//RTL8258 -#define BIT_MASK_RF_RTL8258_TXLPFBW_N 0xc // Useless -#define BIT_MASK_RF_RTL8258_RXLPFBW_N 0xc00 -#define BIT_MASK_RF_RTL8258_RSSILPFBW_N 0xc0 - - - -#endif //#if IS_RTL88XX_N - -// Other Common setting bit define - -//byte endable for sb_write -#define BIT_MASK_SET_BYTE0_COMMON 0x1 // Useless -#define BIT_MASK_SET_BYTE1_COMMON 0x2 -#define BIT_MASK_SET_BYTE2_COMMON 0x4 -#define BIT_MASK_SET_BYTE3_COMMON 0x8 -#define BIT_MASK_SET_WORD0_COMMON 0x3 -#define BIT_MASK_SET_WORD1_COMMON 0xc -#define BIT_MASK_SET_DWORD_COMMON 0xf - -//for PutRegsetting & GetRegSetting BitMask -#define BIT_MASK_SET_MASKBYTE0_COMMON 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f -#define BIT_MASK_SET_MASKBYTE1_COMMON 0xff00 -#define BIT_MASK_SET_MASKBYTE2_COMMON 0xff0000 -#define BIT_MASK_SET_MASKBYTE3_COMMON 0xff000000 -#define BIT_MASK_SET_MASKHWORD_COMMON 0xffff0000 -#define BIT_MASK_SET_MASKLWORD_COMMON 0x0000ffff -#define BIT_MASK_SET_MASKDWORD_COMMON 0xffffffff -#define BIT_MASK_SET_MASKH4BITS_COMMON 0xf0000000 -#define BIT_MASK_SET_MASKH3BYTES_COMMON 0xffffff00 -#define BIT_MASK_SET_MASKOFDM_D_COMMON 0xffc00000 -#define BIT_MASK_SET_MASKCCK_COMMON 0x3f3f3f3f - -//for PutRFRegsetting & GetRFRegSetting BitMask -#define BIT_MASK_SET_MASK12BITS_COMMON 0xfff // RF Reg mask bits -#define BIT_MASK_SET_MASK20BITS_COMMON 0xfffff // RF Reg mask bits T65 RF - - -#endif//__INC_HALCOMPHYBIT_H - - +#ifndef __HALMAC_BB_RF_BIT_H__ +#define __HALMAC_BB_RF_BIT_H__ + + +/*-------------------------Modification Log----------------------------------- + +-------------------------Modification Log-----------------------------------*/ + +/*--------------------------Include File--------------------------------------*/ + +//3 ============Programming guide Start===================== +/* + BB BIT define rules + 1. For all bit define, it should be prefixed by "BIT_BB" + 2. For all bit mask, it should be prefixed by "BIT_MASK_BB" + 3. For all bit shift, it should be prefixed by "BIT_SHIFT_BB" + 4. For other case, prefix is not needed + + RF BIT define rules + 1. For all bit define, it should be prefixed by "BIT_RF" + 2. For all bit mask, it should be prefixed by "BIT_MASK_RF" + 3. For all bit shift, it should be prefixed by "BIT_SHIFT_RF" + 4. For other case, prefix is not needed + + SET BIT define rules + 1. Setting byte mask for BB or RF, it should be prefixed by "BIT_SET" + + Suffixed BIT define rules + 1. For AC chip, it should be suffixed by "_AC" + 2. For N chip, it should be suffixed by "_N" + 3. For Common bit define, it should be suffixed by "_COMMON" + +*/ +#if 1//IS_RTL88XX_AC +/**** page 8 ****/ + +//REG_BB_RCCKENABLE_AC offset:0x808 +#define BIT_MASK_BB_BOFDMEN_AC 0x20000000 +#define BIT_MASK_BB_BCCKEN_AC 0x10000000 +#define BIT_MASK_BB_BRXPATH_AC 0xff + +//REG_BB_RTXPATH_AC offset:0x80c +#define BIT_MASK_BB_BTXPATH_AC 0x0fffffff + +//REG_BB_RAGC_TABLE_AC offset:0x82c // AGC tabel select +#define BIT_MASK_BB_BAGC_TABLE_AC 0x3 + +//REG_BB_CCAONSEC_AC offset:0x838 +#define BIT_MASK_BB_CCA_AC 0xf + +//REG_BB_REDCCA_AC offset:0x8a4 // EDCCA +#define BIT_MASK_BB_BEDCCA_AC 0xffff + +//REG_BB_RHSSIREAD_AC offset:0x8b0 // RF read addr +#define BIT_MASK_BB_BHSSIREAD_ADDR_AC 0xff + +/**** page 9 ****/ +//REG_BB_AGC_TABLE_AC_V2 0x958 +#define BIT_MASK_BB_BAGC_TABLE_AC_V2 0x0000001f + + +/**** page a ****/ +//REG_BB_RCCK_SYSTEM_AC offset: 0xa00 // for cck sideband +#define BIT_MASK_BB_BCCK_SYSTEM_AC 0x10 +//REG_BB_RCCK_RX_AC offset: 0xa04 // for cck rx path selection +#define BIT_MASK_BB_BCCK_RX_AC 0x0c000000 +//REG_BB_RCCK_CCA_AC offset: 0xa08 // cca threshold +#define BIT_MASK_BB_BCCK_CCA_AC 0x00ff0000 + +// REG_BB_RCCK_TXFILTER1_AC offset: 0xa20 +#define BIT_MASK_BB_BCCK_TXFILTER1_C0_AC 0x00ff0000 +#define BIT_MASK_BB_BCCK_TXFILTER1_C1_AC 0xff000000 +//REG_BB_RCCK_TXFILTER2_AC offset: 0xa24 +#define BIT_MASK_BB_BCCK_TXFILTER2_C2_AC 0x000000ff +#define BIT_MASK_BB_BCCK_TXFILTER2_C3_AC 0x0000ff00 +#define BIT_MASK_BB_BCCK_TXFILTER2_C4_AC 0x00ff0000 +#define BIT_MASK_BB_BCCK_TXFILTER2_C5_AC 0xff000000 +//REG_BB_RCCK_TXFILTER3_AC offset: 0xa28 +#define BIT_MASK_BB_BCCK_TXFILTER3_C6_AC 0x000000ff +#define BIT_MASK_BB_BCCK_TXFILTER3_C7_AC 0x0000ff00 +//REG_BB_RCCK_FALSEALARM_AC offset: 0xa5c // counter for cck false alarm +#define BIT_MASK_BB_B_FALSEALARM_AC 0xffff +/**** page b ****/ +/**** page c ****/ +//REG_BB_AGC_TABLE_AC_V1 0xc1c +#define BIT_MASK_BB_BAGC_TABLE_AC_V1 0x00000f00 +//REG_BB_A_LSSIWRITE_AC offset :0xc90 +#define BIT_MASK_BB_LSSIWRITE_AC 0xf0000000 +/**** page d ****/ +/**** page e ****/ + + +#endif //#if IS_RTL88XX_AC + + +#if 1//IS_RTL88XX_N + +// +// 2. Page8(0x800) +// +#define BIT_MASK_BB_RFMOD_N_N 0x1 // Reg 0x800 rFPGA0_RFMOD +#define BIT_MASK_BB_JAPANMODE_N 0x2 +#define BIT_MASK_BB_CCKTXSC_N 0x30 +#define BIT_MASK_BB_CCKEN_N 0x1000000 +#define BIT_MASK_BB_OFDMEN_N 0x2000000 +#define BIT_MASK_BB_OFDMRXADCPHASE_N 0x10000 // Useless now +#define BIT_MASK_BB_OFDMTXDACPHASE_N 0x40000 + +#define BIT_MASK_BB_XATXAGC_N 0x3f +#define BIT_MASK_BB_XBTXAGC_N 0xf00 // Reg 80c rFPGA0_TxGainStage +/* +#define BIT_MASK_BB_XCTXAGC_N 0xf000 +#define BIT_MASK_BB_XDTXAGC_N 0xf0000 +*/ + +#define BIT_MASK_BB_PASTART_N 0xf0000000 // Useless now +#define BIT_MASK_BB_TRSTART_N 0x00f00000 +#define BIT_MASK_BB_RFSTART_N 0x0000f000 +#define BIT_MASK_BB_BBSTART_N 0x000000f0 +#define BIT_MASK_BB_BBCCKSTART_N 0x0000000f +#define BIT_MASK_BB_PAEND_N 0xf //Reg0x814 +#define BIT_MASK_BB_TREND_N 0x0f000000 +#define BIT_MASK_BB_RFEND_N 0x000f0000 +#define BIT_MASK_BB_CCAMASK_N 0x000000f0 //T2R +#define BIT_MASK_BB_R2RCCAMASK_N 0x00000f00 +#define BIT_MASK_BB_HSSI_R2TDELAY_N 0xf8000000 +#define BIT_MASK_BB_HSSI_T2RDELAY_N 0xf80000 +#define BIT_MASK_BB_CONTTXHSSI_N 0x400 //chane gain at continue Tx +#define BIT_MASK_BB_IGFROMCCK_N 0x200 +#define BIT_MASK_BB_AGCADDRESS_N 0x3f +#define BIT_MASK_BB_RXHPTX_N 0x7000 +#define BIT_MASK_BB_RXHPT2R_N 0x38000 +#define BIT_MASK_BB_RXHPCCKINI_N 0xc0000 +#define BIT_MASK_BB_AGCTXCODE_N 0xc00000 +#define BIT_MASK_BB_AGCRXCODE_N 0x300000 + +#define BIT_MASK_BB_3WIREDATALENGTH_N 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define BIT_MASK_BB_3WIREADDRESSLENGTH_N 0x400 + +#define BIT_MASK_BB_3WIRERFPOWERDOWN_N 0x1 // Useless now +#define BIT_MASK_BB_5GPAPEPOLARITY_N 0x40000000 +#define BIT_MASK_BB_2GPAPEPOLARITY_N 0x80000000 +#define BIT_MASK_BB_RFSW_TXDEFAULTANT_N 0x3 +#define BIT_MASK_BB_RFSW_TXOPTIONANT_N 0x30 +#define BIT_MASK_BB_RFSW_RXDEFAULTANT_N 0x300 +#define BIT_MASK_BB_RFSW_RXOPTIONANT_N 0x3000 +#define BIT_MASK_BB_RFSI_3WIREDATA_N 0x1 +#define BIT_MASK_BB_RFSI_3WIRECLOCK_N 0x2 +#define BIT_MASK_BB_RFSI_3WIRELOAD_N 0x4 +#define BIT_MASK_BB_RFSI_3WIRERW_N 0x8 +#define BIT_MASK_BB_RFSI_3WIRE_N 0xf + +#define BIT_MASK_BB_RFSI_RFENV_N 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW +#define BIT_MASK_BB_RFSI_TRSW_N 0x20 // Useless now +#define BIT_MASK_BB_RFSI_TRSWB_N 0x40 +#define BIT_MASK_BB_RFSI_ANTSW_N 0x100 +#define BIT_MASK_BB_RFSI_ANTSWB_N 0x200 +#define BIT_MASK_BB_RFSI_PAPE_N 0x400 +#define BIT_MASK_BB_RFSI_PAPE5G_N 0x800 +#define BIT_MASK_BB_BANDSELECT_N 0x1 +#define BIT_MASK_BB_HTSIG2_GI_N 0x80 +#define BIT_MASK_BB_HTSIG2_SMOOTHING_N 0x01 +#define BIT_MASK_BB_HTSIG2_SOUNDING_N 0x02 +#define BIT_MASK_BB_HTSIG2_AGGREATON_N 0x08 +#define BIT_MASK_BB_HTSIG2_STBC_N 0x30 +#define BIT_MASK_BB_HTSIG2_ADVCODING_N 0x40 +#define BIT_MASK_BB_HTSIG2_NUMOFHTLTF_N 0x300 +#define BIT_MASK_BB_HTSIG2_CRC8_N 0x3fc +#define BIT_MASK_BB_HTSIG1_MCS_N 0x7f +#define BIT_MASK_BB_HTSIG1_BANDWIDTH_N 0x80 +#define BIT_MASK_BB_HTSIG1_HTLENGTH_N 0xffff +#define BIT_MASK_BB_LSIG_RATE_N 0xf +#define BIT_MASK_BB_LSIG_RESERVED_N 0x10 +#define BIT_MASK_BB_LSIG_LENGTH_N 0x1fffe +#define BIT_MASK_BB_LSIG_PARITY_N 0x20 +#define BIT_MASK_BB_CCKRXPHASE_N 0x4 + +//#define BIT_MASK_BB_LSSIREADADDRESS 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 +#define BIT_MASK_BB_LSSIREADADDRESS_N 0x7f800000 // T65 RF +#define BIT_MASK_BB_LSSIREADEDGE_N 0x80000000 //LSSI "Read" edge signal + +//#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack +#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfffff // T65 RF + +#define BIT_MASK_BB_LSSIREADOKFLAG_N 0x1000 // Useless now +#define BIT_MASK_BB_CCKSAMPLERATE_N 0x8 //0: 44MHz, 1:88MHz +#define BIT_MASK_BB_REGULATOR0STANDBY_N 0x1 +#define BIT_MASK_BB_REGULATORPLLSTANDBY_N 0x2 +#define BIT_MASK_BB_REGULATOR1STANDBY_N 0x4 +#define BIT_MASK_BB_PLLPOWERUP_N 0x8 +#define BIT_MASK_BB_DPLLPOWERUP_N 0x10 +#define BIT_MASK_BB_DA10POWERUP_N 0x20 +#define BIT_MASK_BB_AD7POWERUP_N 0x200 +#define BIT_MASK_BB_DA6POWERUP_N 0x2000 +#define BIT_MASK_BB_XTALPOWERUP_N 0x4000 +#define BIT_MASK_BB_40MDCLKPOWERUP_N 0x8000 +#define BIT_MASK_BB_DA6DEBUGMODE_N 0x20000 +#define BIT_MASK_BB_DA6SWING_N 0x380000 + +#define BIT_MASK_BB_ADCLKPHASE_N 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define BIT_MASK_BB_80MCLKDELAY_N 0x18000000 // Useless +#define BIT_MASK_BB_AFEWATCHDOGENABLE_N 0x20000000 + +#define BIT_MASK_BB_XTALCAP01_N 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define BIT_MASK_BB_XTALCAP23_N 0x3 +#define BIT_MASK_BB_XTALCAP92X_N 0x0f000000 + +#define BIT_MASK_BB_INTDIFCLKENABLE_N 0x400 // Useless +#define BIT_MASK_BB_EXTSIGCLKENABLE_N 0x800 +#define BIT_MASK_BB_BANDGAPMBIASPOWERUP_N 0x10000 +#define BIT_MASK_BB_AD11SHGAIN_N 0xc0000 +#define BIT_MASK_BB_AD11INPUTRANGE_N 0x700000 +#define BIT_MASK_BB_AD11OPCURRENT_N 0x3800000 +#define BIT_MASK_BB_IPATHLOOPBACK_N 0x4000000 +#define BIT_MASK_BB_QPATHLOOPBACK_N 0x8000000 +#define BIT_MASK_BB_AFELOOPBACK_N 0x10000000 +#define BIT_MASK_BB_DA10SWING_N 0x7e0 +#define BIT_MASK_BB_DA10REVERSE_N 0x800 +#define BIT_MASK_BB_DACLKSOURCE_N 0x1000 +#define BIT_MASK_BB_AD7INPUTRANGE_N 0x6000 +#define BIT_MASK_BB_AD7GAIN_N 0x38000 +#define BIT_MASK_BB_AD7OUTPUTCMMODE_N 0x40000 +#define BIT_MASK_BB_AD7INPUTCMMODE_N 0x380000 +#define BIT_MASK_BB_AD7CURRENT_N 0xc00000 +#define BIT_MASK_BB_REGULATORADJUST_N 0x7000000 +#define BIT_MASK_BB_AD11POWERUPATTX_N 0x1 +#define BIT_MASK_BB_DA10PSATTX_N 0x10 +#define BIT_MASK_BB_AD11POWERUPATRX_N 0x100 +#define BIT_MASK_BB_DA10PSATRX_N 0x1000 +#define BIT_MASK_BB_CCKRXAGCFORMAT_N 0x200 +#define BIT_MASK_BB_PSDFFTSAMPLEPPOINT_N 0xc000 +#define BIT_MASK_BB_PSDAVERAGENUM_N 0x3000 +#define BIT_MASK_BB_IQPATHCONTROL_N 0xc00 +#define BIT_MASK_BB_PSDFREQ_N 0x3ff +#define BIT_MASK_BB_PSDANTENNAPATH_N 0x30 +#define BIT_MASK_BB_PSDIQSWITCH_N 0x40 +#define BIT_MASK_BB_PSDRXTRIGGER_N 0x400000 +#define BIT_MASK_BB_PSDTXTRIGGER_N 0x80000000 +#define BIT_MASK_BB_PSDSINETONESCALE_N 0x7f000000 +#define BIT_MASK_BB_PSDREPORT_N 0xffff + + +// +// 3. Page9(0x900) +// +#define BIT_MASK_BB_OFDMTXSC_N 0x30000000 // Useless +#define BIT_MASK_BB_CCKTXON_N 0x1 +#define BIT_MASK_BB_OFDMTXON_N 0x2 +#define BIT_MASK_BB_DEBUGPAGE_N 0xfff //reset debug page and also HWord, LWord +#define BIT_MASK_BB_DEBUGITEM_N 0xff //reset debug page and LWord +#define BIT_MASK_BB_ANTL_N 0x10 +#define BIT_MASK_BB_ANTNONHT_N 0x100 +#define BIT_MASK_BB_ANTHT1_N 0x1000 +#define BIT_MASK_BB_ANTHT2_N 0x10000 +#define BIT_MASK_BB_ANTHT1S1_N 0x100000 +#define BIT_MASK_BB_ANTNONHTS1_N 0x1000000 + + +// +// 4. PageA(0xA00) +// +#define BIT_MASK_BB_CCKBBMODE_N 0x3 // Useless +#define BIT_MASK_BB_CCKTXPOWERSAVING_N 0x80 +#define BIT_MASK_BB_CCKRXPOWERSAVING_N 0x40 +#define BIT_MASK_BB_CCKSIDEBAND_N 0x10 // Reg 0xa00 rCCK0_System 20/40 switch +#define BIT_MASK_BB_CCKSCRAMBLE_N 0x8 // Useless +#define BIT_MASK_BB_CCKANTDIVERSITY_N 0x8000 +#define BIT_MASK_BB_CCKCARRIERRECOVERY_N 0x4000 +#define BIT_MASK_BB_CCKTXRATE_N 0x3000 +#define BIT_MASK_BB_CCKDCCANCEL_N 0x0800 +#define BIT_MASK_BB_CCKISICANCEL_N 0x0400 +#define BIT_MASK_BB_CCKMATCHFILTER_N 0x0200 +#define BIT_MASK_BB_CCKEQUALIZER_N 0x0100 +#define BIT_MASK_BB_CCKPREAMBLEDETECT_N 0x800000 +#define BIT_MASK_BB_CCKFASTFALSECCA_N 0x400000 +#define BIT_MASK_BB_CCKCHESTSTART_N 0x300000 +#define BIT_MASK_BB_CCKCCACOUNT_N 0x080000 +#define BIT_MASK_BB_CCKCS_LIM_N 0x070000 +#define BIT_MASK_BB_CCKBISTMODE_N 0x80000000 +#define BIT_MASK_BB_CCKCCAMASK_N 0x40000000 +#define BIT_MASK_BB_CCKTXDACPHASE_N 0x4 +#define BIT_MASK_BB_CCKRXADCPHASE_N 0x20000000 //r_rx_clk +#define BIT_MASK_BB_CCKR_CP_MODE0_N 0x0100 +#define BIT_MASK_BB_CCKTXDCOFFSET_N 0xf0 +#define BIT_MASK_BB_CCKRXDCOFFSET_N 0xf +#define BIT_MASK_BB_CCKCCAMODE_N 0xc000 +#define BIT_MASK_BB_CCKFALSECS_LIM_N 0x3f00 +#define BIT_MASK_BB_CCKCS_RATIO_N 0xc00000 +#define BIT_MASK_BB_CCKCORGBIT_SEL_N 0x300000 +#define BIT_MASK_BB_CCKPD_LIM_N 0x0f0000 +#define BIT_MASK_BB_CCKNEWCCA_N 0x80000000 +#define BIT_MASK_BB_CCKRXHPOFIG_N 0x8000 +#define BIT_MASK_BB_CCKRXIG_N 0x7f00 +#define BIT_MASK_BB_CCKLNAPOLARITY_N 0x800000 +#define BIT_MASK_BB_CCKRX1STGAIN_N 0x7f0000 +#define BIT_MASK_BB_CCKRFEXTEND_N 0x20000000 //CCK Rx Iinital gain polarity +#define BIT_MASK_BB_CCKRXAGCSATLEVEL_N 0x1f000000 +#define BIT_MASK_BB_CCKRXAGCSATCOUNT_N 0xe0 +#define BIT_MASK_BB_CCKRXRFSETTLE_N 0x1f //AGCsamp_dly +#define BIT_MASK_BB_CCKFIXEDRXAGC_N 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define BIT_MASK_BB_CCKANTENNAPOLARITY_N 0x2000 +#define BIT_MASK_BB_CCKTXFILTERTYPE_N 0x0c00 +#define BIT_MASK_BB_CCKRXAGCREPORTTYPE_N 0x0300 +#define BIT_MASK_BB_CCKRXDAGCEN_N 0x80000000 +#define BIT_MASK_BB_CCKRXDAGCPERIOD_N 0x20000000 +#define BIT_MASK_BB_CCKRXDAGCSATLEVEL_N 0x1f000000 +#define BIT_MASK_BB_CCKTIMINGRECOVERY_N 0x800000 +#define BIT_MASK_BB_CCKTXC0_N 0x3f0000 +#define BIT_MASK_BB_CCKTXC1_N 0x3f000000 +#define BIT_MASK_BB_CCKTXC2_N 0x3f +#define BIT_MASK_BB_CCKTXC3_N 0x3f00 +#define BIT_MASK_BB_CCKTXC4_N 0x3f0000 +#define BIT_MASK_BB_CCKTXC5_N 0x3f000000 +#define BIT_MASK_BB_CCKTXC6_N 0x3f +#define BIT_MASK_BB_CCKTXC7_N 0x3f00 +#define BIT_MASK_BB_CCKDEBUGPORT_N 0xff0000 +#define BIT_MASK_BB_CCKDACDEBUG_N 0x0f000000 +#define BIT_MASK_BB_CCKFALSEALARMENABLE_N 0x8000 +#define BIT_MASK_BB_CCKFALSEALARMREAD_N 0x4000 +#define BIT_MASK_BB_CCKTRSSI_N 0x7f +#define BIT_MASK_BB_CCKRXAGCREPORT_N 0xfe +#define BIT_MASK_BB_CCKRXREPORT_ANTSEL_N 0x80000000 +#define BIT_MASK_BB_CCKRXREPORT_MFOFF_N 0x40000000 +#define BIT_MASK_BB_CCKRXRXREPORT_SQLOSS_N 0x20000000 +#define BIT_MASK_BB_CCKRXREPORT_PKTLOSS_N 0x10000000 +#define BIT_MASK_BB_CCKRXREPORT_LOCKEDBIT_N 0x08000000 +#define BIT_MASK_BB_CCKRXREPORT_RATEERROR_N 0x04000000 +#define BIT_MASK_BB_CCKRXREPORT_RXRATE_N 0x03000000 +#define BIT_MASK_BB_CCKRXFACOUNTERLOWER_N 0xff +#define BIT_MASK_BB_CCKRXFACOUNTERUPPER_N 0xff000000 +#define BIT_MASK_BB_CCKRXHPAGCSTART_N 0xe000 +#define BIT_MASK_BB_CCKRXHPAGCFINAL_N 0x1c00 +#define BIT_MASK_BB_CCKRXFALSEALARMENABLE_N 0x8000 +#define BIT_MASK_BB_CCKFACOUNTERFREEZE_N 0x4000 +#define BIT_MASK_BB_CCKTXPATHSEL_N 0x10000000 +#define BIT_MASK_BB_CCKDEFAULTRXPATH_N 0xc000000 +#define BIT_MASK_BB_CCKOPTIONRXPATH_N 0x3000000 + + +// +// 5. PageC(0xC00) +// +#define BIT_MASK_BB_NUMOFSTF_N 0x3 // Useless +#define BIT_MASK_BB_SHIFT_L_N 0xc0 +#define BIT_MASK_BB_GI_TH_N 0xc +#define BIT_MASK_BB_RXPATHA_N 0x1 +#define BIT_MASK_BB_RXPATHB_N 0x2 +#define BIT_MASK_BB_RXPATHC_N 0x4 +#define BIT_MASK_BB_RXPATHD_N 0x8 +#define BIT_MASK_BB_TXPATHA_N 0x1 +#define BIT_MASK_BB_TXPATHB_N 0x2 +#define BIT_MASK_BB_TXPATHC_N 0x4 +#define BIT_MASK_BB_TXPATHD_N 0x8 +#define BIT_MASK_BB_TRSSIFREQ_N 0x200 +#define BIT_MASK_BB_ADCBACKOFF_N 0x3000 +#define BIT_MASK_BB_DFIRBACKOFF_N 0xc000 +#define BIT_MASK_BB_TRSSILATCHPHASE_N 0x10000 +#define BIT_MASK_BB_RXIDCOFFSET_N 0xff +#define BIT_MASK_BB_RXQDCOFFSET_N 0xff00 +#define BIT_MASK_BB_RXDFIRMODE_N 0x1800000 +#define BIT_MASK_BB_RXDCNFTYPE_N 0xe000000 +#define BIT_MASK_BB_RXIQIMB_A_N 0x3ff +#define BIT_MASK_BB_RXIQIMB_B_N 0xfc00 +#define BIT_MASK_BB_RXIQIMB_C_N 0x3f0000 +#define BIT_MASK_BB_RXIQIMB_D_N 0xffc00000 +#define BIT_MASK_BB_DC_DC_NOTCH_N 0x60000 +#define BIT_MASK_BB_RXNBINOTCH_N 0x1f000000 +#define BIT_MASK_BB_PD_TH_N 0xf +#define BIT_MASK_BB_PD_TH_OPT2_N 0xc000 +#define BIT_MASK_BB_PWED_TH_N 0x700 +#define BIT_MASK_BB_IFMF_WIN_L_N 0x800 +#define BIT_MASK_BB_PD_OPTION_N 0x1000 +#define BIT_MASK_BB_MF_WIN_L_N 0xe000 +#define BIT_MASK_BB_BW_SEARCH_L_N 0x30000 +#define BIT_MASK_BB_WIN_ENH_L_N 0xc0000 +#define BIT_MASK_BB_BW_TH_N 0x700000 +#define BIT_MASK_BB_ED_TH2_N 0x3800000 +#define BIT_MASK_BB_BW_OPTION_N 0x4000000 +#define BIT_MASK_BB_RATIO_TH_N 0x18000000 +#define BIT_MASK_BB_WINDOW_L_N 0xe0000000 +#define BIT_MASK_BB_SBD_OPTION_N 0x1 +#define BIT_MASK_BB_FRAME_TH_N 0x1c +#define BIT_MASK_BB_FS_OPTION_N 0x60 +#define BIT_MASK_BB_DC_SLOPE_CHECK_N 0x80 +#define BIT_MASK_BB_FGUARD_COUNTER_DC_L_N 0xe00 +#define BIT_MASK_BB_FRAME_WEIGHT_SHORT_N 0x7000 +#define BIT_MASK_BB_SUB_TUNE_N 0xe00000 +#define BIT_MASK_BB_FRAME_DC_LENGTH_N 0xe000000 +#define BIT_MASK_BB_SBD_START_OFFSET_N 0x30000000 +#define BIT_MASK_BB_FRAME_TH_2_N 0x7 +#define BIT_MASK_BB_FRAME_GI2_TH_N 0x38 +#define BIT_MASK_BB_GI2_SYNC_EN_N 0x40 +#define BIT_MASK_BB_SARCH_SHORT_EARLY_N 0x300 +#define BIT_MASK_BB_SARCH_SHORT_LATE_N 0xc00 +#define BIT_MASK_BB_SARCH_GI2_LATE_N 0x70000 +#define BIT_MASK_BB_CFOANTSUM_N 0x1 +#define BIT_MASK_BB_CFOACC_N 0x2 +#define BIT_MASK_BB_CFOSTARTOFFSET_N 0xc +#define BIT_MASK_BB_CFOLOOKBACK_N 0x70 +#define BIT_MASK_BB_CFOSUMWEIGHT_N 0x80 +#define BIT_MASK_BB_DAGCENABLE_N 0x10000 +#define BIT_MASK_BB_TXIQIMB_A_N 0x3ff +#define BIT_MASK_BB_TXIQIMB_B_N 0xfc00 +#define BIT_MASK_BB_TXIQIMB_C_N 0x3f0000 +#define BIT_MASK_BB_TXIQIMB_D_N 0xffc00000 +#define BIT_MASK_BB_TXIDCOFFSET_N 0xff +#define BIT_MASK_BB_TXQDCOFFSET_N 0xff00 +#define BIT_MASK_BB_TXDFIRMODE_N 0x10000 +#define BIT_MASK_BB_TXPESUDONOISEON_N 0x4000000 +#define BIT_MASK_BB_TXPESUDONOISE_A_N 0xff +#define BIT_MASK_BB_TXPESUDONOISE_B_N 0xff00 +#define BIT_MASK_BB_TXPESUDONOISE_C_N 0xff0000 +#define BIT_MASK_BB_TXPESUDONOISE_D_N 0xff000000 +#define BIT_MASK_BB_CCADROPOPTION_N 0x20000 +#define BIT_MASK_BB_CCADROPTHRES_N 0xfff00000 +#define BIT_MASK_BB_EDCCA_H_N 0xf +#define BIT_MASK_BB_EDCCA_L_N 0xf0 +#define BIT_MASK_BB_LAMBDA_ED_N 0x300 +#define BIT_MASK_BB_RXINITIALGAIN_N 0x7f +#define BIT_MASK_BB_RXANTDIVEN_N 0x80 +#define BIT_MASK_BB_RXAGCADDRESSFORLNA_N 0x7f00 +#define BIT_MASK_BB_RXHIGHPOWERFLOW_N 0x8000 +#define BIT_MASK_BB_RXAGCFREEZETHRES_N 0xc0000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC1_N 0x300000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC2_N 0xc00000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC3_N 0x3000000 +#define BIT_MASK_BB_RXFREEZESTEP_AGC0_N 0xc000000 +#define BIT_MASK_BB_RXRSSI_CMP_EN_N 0x10000000 +#define BIT_MASK_BB_RXQUICKAGCEN_N 0x20000000 +#define BIT_MASK_BB_RXAGCFREEZETHRESMODE_N 0x40000000 +#define BIT_MASK_BB_RXOVERFLOWCHECKTYPE_N 0x80000000 +#define BIT_MASK_BB_RXAGCSHIFT_N 0x7f +#define BIT_MASK_BB_TRSW_TRI_ONLY_N 0x80 +#define BIT_MASK_BB_POWERTHRES_N 0x300 +#define BIT_MASK_BB_RXAGCEN_N 0x1 +#define BIT_MASK_BB_RXAGCTOGETHEREN_N 0x2 +#define BIT_MASK_BB_RXAGCMIN_N 0x4 +#define BIT_MASK_BB_RXHP_INI_N 0x7 +#define BIT_MASK_BB_RXHP_TRLNA_N 0x70 +#define BIT_MASK_BB_RXHP_RSSI_N 0x700 +#define BIT_MASK_BB_RXHP_BBP1_N 0x7000 +#define BIT_MASK_BB_RXHP_BBP2_N 0x70000 +#define BIT_MASK_BB_RXHP_BBP3_N 0x700000 +#define BIT_MASK_BB_RSSI_H_N 0x7f0000 //the threshold for high power +#define BIT_MASK_BB_RSSI_GEN_N 0x7f000000 //the threshold for ant diversity +#define BIT_MASK_BB_RXSETTLE_TRSW_N 0x7 +#define BIT_MASK_BB_RXSETTLE_LNA_N 0x38 +#define BIT_MASK_BB_RXSETTLE_RSSI_N 0x1c0 +#define BIT_MASK_BB_RXSETTLE_BBP_N 0xe00 +#define BIT_MASK_BB_RXSETTLE_RXHP_N 0x7000 +#define BIT_MASK_BB_RXSETTLE_ANTSW_RSSI_N 0x38000 +#define BIT_MASK_BB_RXSETTLE_ANTSW_N 0xc0000 +#define BIT_MASK_BB_RXPROCESSTIME_DAGC_N 0x300000 +#define BIT_MASK_BB_RXSETTLE_HSSI_N 0x400000 +#define BIT_MASK_BB_RXPROCESSTIME_BBPPW_N 0x800000 +#define BIT_MASK_BB_RXANTENNAPOWERSHIFT_N 0x3000000 +#define BIT_MASK_BB_RSSITABLESELECT_N 0xc000000 +#define BIT_MASK_BB_RXHP_FINAL_N 0x7000000 +#define BIT_MASK_BB_RXHTSETTLE_BBP_N 0x7 +#define BIT_MASK_BB_RXHTSETTLE_HSSI_N 0x8 +#define BIT_MASK_BB_RXHTSETTLE_RXHP_N 0x70 +#define BIT_MASK_BB_RXHTSETTLE_BBPPW_N 0x80 +#define BIT_MASK_BB_RXHTSETTLE_IDLE_N 0x300 +#define BIT_MASK_BB_RXHTSETTLE_RESERVED_N 0x1c00 +#define BIT_MASK_BB_RXHTRXHPEN_N 0x8000 +#define BIT_MASK_BB_RXHTAGCFREEZETHRES_N 0x30000 +#define BIT_MASK_BB_RXHTAGCTOGETHEREN_N 0x40000 +#define BIT_MASK_BB_RXHTAGCMIN_N 0x80000 +#define BIT_MASK_BB_RXHTAGCEN_N 0x100000 +#define BIT_MASK_BB_RXHTDAGCEN_N 0x200000 +#define BIT_MASK_BB_RXHTRXHP_BBP_N 0x1c00000 +#define BIT_MASK_BB_RXHTRXHP_FINAL_N 0xe0000000 +#define BIT_MASK_BB_RXPWRATIOTH_N 0x3 +#define BIT_MASK_BB_RXPWRATIOEN_N 0x4 +#define BIT_MASK_BB_RXMFHOLD_N 0x3800 +#define BIT_MASK_BB_RXPD_DELAY_TH1_N 0x38 +#define BIT_MASK_BB_RXPD_DELAY_TH2_N 0x1c0 +#define BIT_MASK_BB_RXPD_DC_COUNT_MAX_N 0x600 +//#define bRxMF_Hold 0x3800 +#define BIT_MASK_BB_RxPD_Delay_TH_N 0x8000 +#define BIT_MASK_BB_RxProcess_Delay_N 0xf0000 +#define BIT_MASK_BB_RxSearchrange_GI2_Early_N 0x700000 +#define BIT_MASK_BB_RxFrame_Guard_Counter_L_N 0x3800000 +#define BIT_MASK_BB_RxSGI_Guard_L_N 0xc000000 +#define BIT_MASK_BB_RxSGI_Search_L_N 0x30000000 +#define BIT_MASK_BB_RxSGI_TH_N 0xc0000000 +#define BIT_MASK_BB_DFSCnt0_N 0xff +#define BIT_MASK_BB_DFSCnt1_N 0xff00 +#define BIT_MASK_BB_DFSFlag_N 0xf0000 +#define BIT_MASK_BB_MFWeightSum_N 0x300000 +#define BIT_MASK_BB_MinIdxTH_N 0x7f000000 +#define BIT_MASK_BB_DAFormat_N 0x40000 +#define BIT_MASK_BB_TxChEmuEnable_N 0x01000000 +#define BIT_MASK_BB_TRSWIsolation_A_N 0x7f +#define BIT_MASK_BB_TRSWIsolation_B_N 0x7f00 +/* +#define BIT_MASK_BB_TRSWIsolation_C_N 0x7f0000 +#define BIT_MASK_BB_TRSWIsolation_D_N 0x7f000000 +*/ +#define BIT_MASK_BB_ExtLNAGain_N 0x7c00 + + +// +// 6. PageE(0xE00) +// +#define BIT_MASK_BB_STBCEN_N 0x4 // Useless +#define BIT_MASK_BB_ANTENNAMAPPING_N 0x10 +#define BIT_MASK_BB_NSS_N 0x20 +#define BIT_MASK_BB_CFOANTSUMD_N 0x200 +#define BIT_MASK_BB_OFDMDISPWSAVTX_N 0x400000 +#define BIT_MASK_BB_PHYCOUNTERRESET_N 0x8000000 +#define BIT_MASK_BB_CFOREPORTGET_N 0x4000000 +#define BIT_MASK_BB_OFDMCONTINUETX_N 0x10000000 +#define BIT_MASK_BB_OFDMSINGLECARRIER_N 0x20000000 +#define BIT_MASK_BB_OFDMSINGLETONE_N 0x40000000 +/* +#define bRxPath1 0x01 +#define bRxPath2 0x02 +#define bRxPath3 0x04 +#define bRxPath4 0x08 +#define bTxPath1 0x10 +#define bTxPath2 0x20 +*/ +#define BIT_MASK_BB_HTDETECT_N 0x100 +#define BIT_MASK_BB_CFOEN_N 0x10000 +#define BIT_MASK_BB_CFOVALUE_N 0xfff00000 +#define BIT_MASK_BB_SIGTONE_RE_N 0x3f +#define BIT_MASK_BB_SIGTONE_IM_N 0x7f00 +#define BIT_MASK_BB_COUNTER_CCA_N 0xffff +#define BIT_MASK_BB_COUNTER_PARITYFAIL_N 0xffff0000 +#define BIT_MASK_BB_COUNTER_RATEILLEGAL_N 0xffff +#define BIT_MASK_BB_COUNTER_CRC8FAIL_N 0xffff0000 +#define BIT_MASK_BB_COUNTER_MCSNOSUPPORT_N 0xffff +#define BIT_MASK_BB_COUNTER_FASTSYNC_N 0xffff +#define BIT_MASK_BB_SHORTCFO_N 0xfff +#define BIT_MASK_BB_SHORTCFOTLENGTH_N 12 //total +#define BIT_MASK_BB_SHORTCFOFLENGTH_N 11 //fraction +#define BIT_MASK_BB_LONGCFO_N 0x7ff +#define BIT_MASK_BB_LONGCFOTLENGTH_N 11 +#define BIT_MASK_BB_LONGCFOFLENGTH_N 11 +#define BIT_MASK_BB_TAILCFO_N 0x1fff +#define BIT_MASK_BB_TAILCFOTLENGTH_N 13 +#define BIT_MASK_BB_TAILCFOFLENGTH_N 12 +#define BIT_MASK_BB_MAX_EN_PWDB_N 0xffff +#define BIT_MASK_BB_CC_POWER_DB_N 0xffff0000 +#define BIT_MASK_BB_NOISE_PWDB_N 0xffff +#define BIT_MASK_BB_POWERMEASTLENGTH_N 10 +#define BIT_MASK_BB_POWERMEASFLENGTH_N 3 +#define BIT_MASK_BB_RX_HT_BW_N 0x1 +#define BIT_MASK_BB_RXSC_N 0x6 +#define BIT_MASK_BB_RX_HT_N 0x8 +#define BIT_MASK_BB_NB_INTF_DET_ON_N 0x1 +#define BIT_MASK_BB_INTF_WIN_LEN_CFG_N 0x30 +#define BIT_MASK_BB_NB_INTF_TH_CFG_N 0x1c0 +#define BIT_MASK_BB_RFGAIN_N 0x3f +#define BIT_MASK_BB_TABLESEL_N 0x40 +#define BIT_MASK_BB_TRSW_N 0x80 +#define BIT_MASK_BB_RXSNR_A_N 0xff +#define BIT_MASK_BB_RXSNR_B_N 0xff00 +/* +#define BIT_MASK_BB_RXSNR_C_N 0xff0000 +#define BIT_MASK_BB_RXSNR_D_N 0xff000000 +*/ +#define BIT_MASK_BB_SNREVMTLENGTH_N 8 +#define BIT_MASK_BB_SNREVMFLENGTH_N 1 +#define BIT_MASK_BB_CSI1ST_N 0xff +#define BIT_MASK_BB_CSI2ND_N 0xff00 +#define BIT_MASK_BB_RXEVM1ST_N 0xff0000 +#define BIT_MASK_BB_RXEVM2ND_N 0xff000000 +#define BIT_MASK_BB_SIGEVM_N 0xff +#define BIT_MASK_BB_PWDB_N 0xff00 +#define BIT_MASK_BB_SGIEN_N 0x10000 + +#define BIT_MASK_BB_SFACTORQAM1_N 0xf // Useless +#define BIT_MASK_BB_SFACTORQAM2_N 0xf0 +#define BIT_MASK_BB_SFACTORQAM3_N 0xf00 +#define BIT_MASK_BB_SFACTORQAM4_N 0xf000 +#define BIT_MASK_BB_SFACTORQAM5_N 0xf0000 +#define BIT_MASK_BB_SFACTORQAM6_N 0xf0000 +#define BIT_MASK_BB_SFACTORQAM7_N 0xf00000 +#define BIT_MASK_BB_SFACTORQAM8_N 0xf000000 +#define BIT_MASK_BB_SFACTORQAM9_N 0xf0000000 +#define BIT_MASK_BB_CSISCHEME_N 0x100000 + +#define BIT_MASK_BB_NOISELVLTOPSET_N 0x3 // Useless +#define BIT_MASK_BB_CHSMOOTH_N 0x4 +#define BIT_MASK_BB_CHSMOOTHCFG1_N 0x38 +#define BIT_MASK_BB_CHSMOOTHCFG2_N 0x1c0 +#define BIT_MASK_BB_CHSMOOTHCFG3_N 0xe00 +#define BIT_MASK_BB_CHSMOOTHCFG4_N 0x7000 +#define BIT_MASK_BB_MRCMODE_N 0x800000 +#define BIT_MASK_BB_THEVMCFG_N 0x7000000 + +#define BIT_MASK_BB_LOOPFITTYPE_N 0x1 // Useless +#define BIT_MASK_BB_UPDCFO_N 0x40 +#define BIT_MASK_BB_UPDCFOOFFDATA_N 0x80 +#define BIT_MASK_BB_ADVUPDCFO_N 0x100 +#define BIT_MASK_BB_ADVTIMECTRL_N 0x800 +#define BIT_MASK_BB_UPDCLKO_N 0x1000 +#define BIT_MASK_BB_FC_N 0x6000 +#define BIT_MASK_BB_TRACKINGMODE_N 0x8000 +#define BIT_MASK_BB_PHCMPENABLE_N 0x10000 +#define BIT_MASK_BB_UPDCLKOLTF_N 0x20000 +#define BIT_MASK_BB_COMCHCFO_N 0x40000 +#define BIT_MASK_BB_CSIESTIMODE_N 0x80000 +#define BIT_MASK_BB_ADVUPDEQZ_N 0x100000 +#define BIT_MASK_BB_UCHCFG_N 0x7000000 +#define BIT_MASK_BB_UPDEQZ_N 0x8000000 + +#define BIT_MASK_BB_TXAGCRATE18_06_N 0x7f7f7f7f // Useless +#define BIT_MASK_BB_TXAGCRATE54_24_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS32_N 0x7f +#define BIT_MASK_BB_TXAGCRATECCK_N 0x7f00 +#define BIT_MASK_BB_TXAGCRATEMCS3_MCS0_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS7_MCS4_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS11_MCS8_N 0x7f7f7f7f +#define BIT_MASK_BB_TXAGCRATEMCS15_MCS12_N 0x7f7f7f7f + +//Rx Pseduo noise +#define BIT_MASK_BB_RXPESUDONOISEON_N 0x20000000 // Useless +#define BIT_MASK_BB_RXPESUDONOISE_A_N 0xff +#define BIT_MASK_BB_RXPESUDONOISE_B_N 0xff00 +/* +#define BIT_MASK_BB_RXPESUDONOISE_C_N 0xff0000 +#define BIT_MASK_BB_RXPESUDONOISE_D_N 0xff000000 +*/ +#define BIT_MASK_BB_PESUDONOISESTATE_A_N 0xffff +#define BIT_MASK_BB_PESUDONOISESTATE_B_N 0xffff0000 +/* +#define BIT_MASK_BB_PESUDONOISESTATE_C_N 0xffff +#define BIT_MASK_BB_PESUDONOISESTATE_D_N 0xffff0000 +*/ + + +// +//7. RF Register +// +//Zebra1 +#define BIT_MASK_RF_ZEBRA1_HSSIENABLE_N 0x8 // Useless +#define BIT_MASK_RF_ZEBRA1_TRXCONTROL_N 0xc00 +#define BIT_MASK_RF_ZEBRA1_TRXGAINSETTING_N 0x07f +#define BIT_MASK_RF_ZEBRA1_RXCORNER_N 0xc00 +#define BIT_MASK_RF_ZEBRA1_TXCHARGEPUMP_N 0x38 +#define BIT_MASK_RF_ZEBRA1_RXCHARGEPUMP_N 0x7 +#define BIT_MASK_RF_ZEBRA1_CHANNELNUM_N 0xf80 +#define BIT_MASK_RF_ZEBRA1_TXLPFBW_N 0x400 +#define BIT_MASK_RF_ZEBRA1_RXLPFBW_N 0x600 + +//Zebra4 +#define BIT_MASK_RF_RTL8256REGMODECTRL1_N 0x100 // Useless +#define BIT_MASK_RF_RTL8256REGMODECTRL0_N 0x40 +#define BIT_MASK_RF_RTL8256_TXLPFBW_N 0x18 +#define BIT_MASK_RF_RTL8256_RXLPFBW_N 0x600 + +//RTL8258 +#define BIT_MASK_RF_RTL8258_TXLPFBW_N 0xc // Useless +#define BIT_MASK_RF_RTL8258_RXLPFBW_N 0xc00 +#define BIT_MASK_RF_RTL8258_RSSILPFBW_N 0xc0 + + + +#endif //#if IS_RTL88XX_N + +// Other Common setting bit define + +//byte endable for sb_write +#define BIT_MASK_SET_BYTE0_COMMON 0x1 // Useless +#define BIT_MASK_SET_BYTE1_COMMON 0x2 +#define BIT_MASK_SET_BYTE2_COMMON 0x4 +#define BIT_MASK_SET_BYTE3_COMMON 0x8 +#define BIT_MASK_SET_WORD0_COMMON 0x3 +#define BIT_MASK_SET_WORD1_COMMON 0xc +#define BIT_MASK_SET_DWORD_COMMON 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define BIT_MASK_SET_MASKBYTE0_COMMON 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define BIT_MASK_SET_MASKBYTE1_COMMON 0xff00 +#define BIT_MASK_SET_MASKBYTE2_COMMON 0xff0000 +#define BIT_MASK_SET_MASKBYTE3_COMMON 0xff000000 +#define BIT_MASK_SET_MASKHWORD_COMMON 0xffff0000 +#define BIT_MASK_SET_MASKLWORD_COMMON 0x0000ffff +#define BIT_MASK_SET_MASKDWORD_COMMON 0xffffffff +#define BIT_MASK_SET_MASKH4BITS_COMMON 0xf0000000 +#define BIT_MASK_SET_MASKH3BYTES_COMMON 0xffffff00 +#define BIT_MASK_SET_MASKOFDM_D_COMMON 0xffc00000 +#define BIT_MASK_SET_MASKCCK_COMMON 0x3f3f3f3f + +//for PutRFRegsetting & GetRFRegSetting BitMask +#define BIT_MASK_SET_MASK12BITS_COMMON 0xfff // RF Reg mask bits +#define BIT_MASK_SET_MASK20BITS_COMMON 0xfffff // RF Reg mask bits T65 RF + + +#endif//__INC_HALCOMPHYBIT_H + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_reg.h b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_reg.h old mode 100755 new mode 100644 index 67ab5f36f60..32ea2ed11ee --- a/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_reg.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMac88XX/halmisc_bb_rf_reg.h @@ -1,466 +1,466 @@ - -#ifndef __HALMAC_BB_RF_REG_H__ -#define __HALMAC_BB_RF_REG_H__ - -#if 1//IS_RTL88XX_AC - - - -// -// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF -// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 -// 3. RF register 0x00-2E -// 4. Bit Mask for BB/RF register -// 5. Other defintion for BB/RF R/W -// - -//============Programming guide Start===================== -/* - BB REG define rules - 1. For all reg define, it should be prefixed by " REG_BB" - - - RF REG define rules - 1. For all reg define, it should be prefixed by " REG_RF" - -*/ -/**** page 8 ****/ -#define REG_BB_CCKENABLE_AC 0x808 // OFDM/CCK block enable -#define REG_BB_RXPATH_AC 0x808 // Rx antenna -#define REG_BB_TXPATH_AC 0x80c // Tx antenna -#define REG_BB_AGC_TABLE_AC 0x82c // AGC tabel select -#define REG_BB_PWED_TH_AC 0x830 -#define REG_BB_BWINDICATION_AC 0x834 -#define REG_BB_CCAONSEC_AC 0x838 -#define REG_BB_L1PEAKTH_AC 0x848 -#define REG_BB_FC_AREA_AC 0x860 // fc_area -#define REG_BB_FPGA0_XB_RFINTERFACEOE_AC 0x864 -#define REG_BB_FPGA0_XAB_RFINTERFACESW_AC 0x870 // RF Interface Software Control -#define REG_BB_FPGA0_XCD_RFINTERFACESW_AC 0x874 -#define REG_BB_FPGA0_XAB_RFPARAMETER_AC 0x878 // RF Parameter -#define REG_BB_FPGA0_XCD_RFPARAMETER_AC 0x87c -#define REG_BB_FPGA0_ANALOGPARAMETER1_AC 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define REG_BB_FPGA0_ANALOGPARAMETER2_AC 0x884 -#define REG_BB_FPGA0_ANALOGPARAMETER3_AC 0x888 -#define REG_BB_FPGA0_ADDACLOCKEN_AC 0x888 // enable ad/da clock1 for dual-phy -#define REG_BB_FPGA0_ANALOGPARAMETER4_AC 0x88c -#define REG_BB_EDCCA_AC 0x8a4 // EDCCA -#define REG_BB_RFMOD_AC 0x8ac //RF mode -#define REG_BB_HSSIREAD_AC 0x8b0 // RF read addr -#define REG_BB_FC_ENABL_VHT_AC 0x8c0 -#define REG_BB_VHTLEN_USE_LSIG_AC 0x8c3 // Use LSIG for VHT length -#define REG_BB_ADC_BUF_CLK_AC 0x8c4 - -/**** page 9 ****/ -#define REG_BB_SINGLETONE_CONTTX_AC 0x914 -#define REG_BB_AGC_TABLE_AC_V2 0x958 - - -/**** page a ****/ -#define REG_BB_CCK_SYSTEM_AC 0xa00 // for cck sideband -#define REG_BB_CCK_RX_AC 0xa04 // for cck rx path selection -#define REG_BB_CCK_CCA_AC 0xa08 // cca threshold -// CCK TX scaling -#define REG_BB_CCK_TXFILTER1_AC 0xa20 -#define REG_BB_CCK_TXFILTER2_AC 0xa24 -#define REG_BB_CCK_TXFILTER3_MSK_AC 0xa28 -#define REG_BB_CCK_FALSEALARM_AC 0xa5c // counter for cck false alarm - -/**** page b ****/ -// RSSI Dump -#define REG_BB_A_RSSIDUMP_AC 0xBF0 -#define REG_BB_B_RSSIDUMP_AC 0xBF1 -#define REG_BB_S1_RXEVMDUMP_AC 0xBF4 -#define REG_BB_S2_RXEVMDUMP_AC 0xBF5 -#define REG_BB_A_RXSNRDUMP_AC 0xBF6 -#define REG_BB_B_RXSNRDUMP_AC 0xBF7 -#define REG_BB_A_CFOSHORTDUMP_AC 0xBF8 -#define REG_BB_B_CFOSHORTDUMP_AC 0xBFA -#define REG_BB_A_CFOLONGDUMP_AC 0xBEC -#define REG_BB_B_CFOLONGDUMP_AC 0xBEE -// YN: mask the following register definition temporarily -//#define REG_BB_PDP_ANTA_AC 0xb00 -//#define REG_BB_PDP_ANTA_4_AC 0xb04 -//#define REG_BB_CONFIG_PMPD_ANTA_AC 0xb28 -//#define REG_BB_CONFIG_ANTA_AC 0xb68 -//#define REG_BB_CONFIG_ANTB_AC 0xb6c -//#define REG_BB_PDP_ANTB_AC 0xb70 -//#define REG_BB_PDP_ANTB_4_AC 0xb74 -//#define REG_BB_CONFIG_PMPD_ANTB_AC 0xb98 -//#define REG_BB_APK_AC 0xbd8 - -/**** page c ****/ -#define REG_BB_A_RXIQC_AB_AC 0xc10 //RxIQ imblance matrix coeff. A & B -#define REG_BB_A_RXIQC_CD_AC 0xc14 //RxIQ imblance matrix coeff. C & D -#define REG_BB_AGC_TABLE_AC_V1 0xc1c - -// TX AGC -#define REG_BB_TXAGC_A_CCK11_CCK1_AC 0xc20 -#define REG_BB_TXAGC_A_OFDM18_OFDM6_AC 0xc24 -#define REG_BB_TXAGC_A_OFDM54_OFDM24_AC 0xc28 -#define REG_BB_TXAGC_A_MCS3_MCS0_AC 0xc2c -#define REG_BB_TXAGC_A_MCS7_MCS4_AC 0xc30 -#define REG_BB_TXAGC_A_MCS11_MCS8_AC 0xc34 -#define REG_BB_TXAGC_A_MCS15_MCS12_AC 0xc38 -#define REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC 0xc3c -#define REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC 0xc40 -#define REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC 0xc44 -#define REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC 0xc48 -#define REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC 0xc4c -// DIG-related -#define REG_BB_A_IGI_AC 0xc50 // Initial Gain for path-A -// AFE-related -#define REG_BB_A_AFEPWR1_AC 0xc60 // dynamic AFE power control -#define REG_BB_A_AFEPWR2_AC 0xc64 // dynamic AFE power control -#define REG_BB_A_RX_WAITCCA_TX_CCKRFON_AC 0xc68 -#define REG_BB_A_TX_CCKBBON_OFDMRFON_AC 0xc6c -#define REG_BB_A_TX_OFDMBBON_TX2RX_AC 0xc70 -#define REG_BB_A_TX2TX_RXCCK_AC 0xc74 -#define REG_BB_A_RX_OFDM_WAITRIFS_AC 0xc78 -#define REG_BB_A_RX2RX_BT_AC 0xc7c -#define REG_BB_A_SLEEP_NAV_AC 0xc80 -#define REG_BB_A_PMPD_AC 0xc84 -#define REG_BB_A_LSSIWRITE_AC 0xc90 // RF write addr -#define REG_BB_A_RFE_PINMUX_AC 0xcb0 // Path_A RFE cotrol pinmux -#define REG_BB_A_RFE_AC 0xcb8 // Path_A RFE cotrol - -/**** page d ****/ -#define REG_BB_A_PIREAD_AC 0xd04 // RF readback with PI -#define REG_BB_B_PIREAD_AC 0xd44 // RF readback with PI -#define REG_BB_C_PIREAD_AC 0xd84 // RF readback with PI -#define REG_BB_D_PIREAD_AC 0xdc4 // RF readback with PI -#define REG_BB_A_SIREAD_AC 0xd08 // RF readback with SI -#define REG_BB_B_SIREAD_AC 0xd48 // RF readback with SI -#define REG_BB_C_SIREAD_AC 0xd88 // RF readback with SI -#define REG_BB_D_SIREAD_AC 0xdc8 // RF readback with SI - - -/**** page e ****/ -// RXIQC -#define REG_BB_B_TXSCALE_AC 0xe1c // Path_B TX scaling factor -#define REG_BB_B_RXIQC_AB_AC 0xe10 //RxIQ imblance matrix coeff. A & B -#define REG_BB_B_RXIQC_CD_AC 0xe14 //RxIQ imblance matrix coeff. C & D - -// TX AGC -#define REG_BB_TXAGC_B_CCK11_CCK1_AC 0xe20 -#define REG_BB_TXAGC_B_OFDM18_OFDM6_AC 0xe24 -#define REG_BB_TXAGC_B_OFDM54_OFDM24_AC 0xe28 -#define REG_BB_TXAGC_B_MCS3_MCS0_AC 0xe2c -#define REG_BB_TXAGC_B_MCS7_MCS4_AC 0xe30 -#define REG_BB_TXAGC_B_MCS11_MCS8_AC 0xe34 -#define REG_BB_TXAGC_B_MCS15_MCS12_AC 0xe38 -#define REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC 0xe3c -#define REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC 0xe40 -#define REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC 0xe44 -#define REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC 0xe48 -#define REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC 0xe4c - -// DIG-related -#define REG_BB_B_IGI_AC 0xe50 // Initial Gain for path-B -#define REG_BB_B_LSSIWRITE_AC 0xe90 // RF write addr - -// Misc functions -#define REG_BB_B_RFE_PINMUX_AC 0xeb0 // Path_B RFE control pinmux -#define REG_BB_B_RFE_AC 0xeb8 // Path_B RFE control - -/**** page f ****/ -// DIG-related -#define REG_BB_OFDM_FALSEALARM1_AC 0xf48 // counter for break -#define REG_BB_OFDM_FALSEALARM2_AC 0xf4c // counter for spoofing -// Report-related -#define REG_BB_OFDM_SHORTCFOAB_AC 0xf60 -#define REG_BB_OFDM_LONGCFOAB_AC 0xf64 -#define REG_BB_OFDM_ENDCFOAB_AC 0xf70 -#define REG_BB_OFDM_AGCREPORT_AC 0xf84 -#define REG_BB_OFDM_RXSNR_AC 0xf88 -#define REG_BB_OFDM_RXEVMCSI_AC 0xf8c -#define REG_BB_OFDM_SIGREPORT_AC 0xf90 - -/**** page 18 ****/ -// TX AGC -#define REG_BB_TXAGC_C_CCK11_CCK1_AC 0x1820 -#define REG_BB_TXAGC_C_OFDM18_OFDM6_AC 0x1824 -#define REG_BB_TXAGC_C_OFDM54_OFDM24_AC 0x1828 -#define REG_BB_TXAGC_C_MCS3_MCS0_AC 0x182c -#define REG_BB_TXAGC_C_MCS7_MCS4_AC 0x1830 -#define REG_BB_TXAGC_C_MCS11_MCS8_AC 0x1834 -#define REG_BB_TXAGC_C_MCS15_MCS12_AC 0x1838 -#define REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC 0x183c -#define REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC 0x1840 -#define REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC 0x1844 -#define REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC 0x1848 -#define REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC 0x184c - -#define REG_BB_C_LSSIWRITE_AC 0x1890 // RF write addr -#define REG_BB_C_RFE_PINMUX_AC 0x18b4 // Path_C RFE control pinmux - - -/**** page 1a ****/ -// TX AGC -#define REG_BB_TXAGC_D_CCK11_CCK1_AC 0x1a20 -#define REG_BB_TXAGC_D_OFDM18_OFDM6_AC 0x1a24 -#define REG_BB_TXAGC_D_OFDM54_OFDM24_AC 0x1a28 -#define REG_BB_TXAGC_D_MCS3_MCS0_AC 0x1a2c -#define REG_BB_TXAGC_D_MCS7_MCS4_AC 0x1a30 -#define REG_BB_TXAGC_D_MCS11_MCS8_AC 0x1a34 -#define REG_BB_TXAGC_D_MCS15_MCS12_AC 0x1a38 -#define REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC 0x1a3c -#define REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC 0x1a40 -#define REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC 0x1a44 -#define REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC 0x1a48 -#define REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC 0x1a4c - -#define REG_BB_D_LSSIWRITE_AC 0x1a90 // RF write addr -#define REG_BB_D_RFE_PINMUX_AC 0x1ab4 // Path_D RFE control pinmux - - -////////////////////////////////////// - - - - -// RF Register -// -#define REG_RF_AC_AC 0x00 -#define REG_RF_RF_TOP_AC 0x07 -#define REG_RF_TXLOK_AC 0x08 -#define REG_RF_TXAPK_AC 0x0B -#define REG_RF_CHNLBW_AC 0x18 // RF channel and BW switch -#define REG_RF_TXLCTANK_AC 0x54 -#define REG_RF_APK_AC 0x63 -#define REG_BRF_CHNLBW_MOD_AG_AC 0x70300 -#define REG_BRF_CHNLBW_BW_AC 0xc00 -#define REG_RF_RCK1_AC 0x1c -#define REG_RF_RCK2_AC 0x1d -#define REG_RF_RCK3_AC 0x1e -#define REG_RF_LCK_AC 0xB4 -#define REG_BB_BRFREGOFFSETMASK_AC 0xfffff - - -#endif //#if IS_RTL88XX_AC - - -#if 1//IS_RTL88XX_N - -// -// 2. BB Register Page8(0x800) -// -#define REG_BB_FPGA0_RFMOD_N 0x800 //RF mode & CCK TxSC // RF BW Setting?? -#define REG_BB_FPGA0_TXINFO_N 0x804 // Status report?? -#define REG_BB_FPGA0_PSDFUNCTION_N 0x808 -#define REG_BB_FPGA0_TXGAINSTAGE_N 0x80c // Set TX PWR init gain? -#define REG_BB_FPGA0_RFTIMING1_N 0x810 // Useless now -#define REG_BB_FPGA0_RFTIMING2_N 0x814 -#define REG_BB_PRIMESC_N 0x818 - -#define REG_BB_FPGA0_XA_HSSIPARAMETER1_N 0x820 // RF 3 wire register -#define REG_BB_FPGA0_XA_HSSIPARAMETER2_N 0x824 -#define REG_BB_FPGA0_XB_HSSIPARAMETER1_N 0x828 -#define REG_BB_FPGA0_XB_HSSIPARAMETER2_N 0x82c -#define REG_BB_TXAGC_B_RATE18_06_N 0x830 -#define REG_BB_TXAGC_B_RATE54_24_N 0x834 -#define REG_BB_TXAGC_B_CCK5_1_MCS32_N 0x838 -#define REG_BB_TXAGC_B_MCS03_MCS00_N 0x83c -#define REG_BB_FPGA0_XA_LSSIPARAMETER_N 0x840 -#define REG_BB_FPGA0_XB_LSSIPARAMETER_N 0x844 -#define REG_BB_TXAGC_B_MCS07_MCS04_N 0x848 -#define REG_BB_TXAGC_B_MCS11_MCS08_N 0x84c -#define REG_BB_FPGA0_RFWAKEUPPARAMETER_N 0x850 // Useless now -#define REG_BB_FPGA0_RFSLEEPUPPARAMETER_N 0x854 -#define REG_BB_FPGA0_XAB_SWITCHCONTROL_N 0x858 // RF Channel switch -#define REG_BB_FPGA0_XCD_SWITCHCONTROL_N 0x85c -#define REG_BB_FPGA0_XA_RFINTERFACEOE_N 0x860 // RF Channel switch -#define REG_BB_FPGA0_XB_RFINTERFACEOE_N 0x864 -#define REG_BB_TXAGC_B_MCS15_MCS12_N 0x868 -#define REG_BB_TXAGC_A_CCK11_2_B_CCK11_N 0x86c -#define REG_BB_FPGA0_XAB_RFINTERFACESW_N 0x870 // RF Interface Software Control -#define REG_BB_FPGA0_XCD_RFINTERFACESW_N 0x874 -#define REG_BB_FPGA0_XAB_RFPARAMETER_N 0x878 // RF Parameter -#define REG_BB_FPGA0_XCD_RFPARAMETER_N 0x87c -#define REG_BB_FPGA0_ANALOGPARAMETER1_N 0x880 // Crystal cap setting RF-R/W protection for parameter4?? -#define REG_BB_FPGA0_ANALOGPARAMETER2_N 0x884 -#define REG_BB_FPGA0_ANALOGPARAMETER3_N 0x888 // Useless now -#define REG_BB_FPGA0_ANALOGPARAMETER4_N 0x88c -#define REG_BB_FPGA0_XA_LSSIREADBACK_N 0x8a0 // Tranceiver LSSI Readback -#define REG_BB_FPGA0_XB_LSSIREADBACK_N 0x8a4 - -#define REG_BB_FPGA0_PSDREPORT_N 0x8b4 // Useless now -#define REG_BB_TRANSCEIVERA_HSPI_READBACK_N 0x8b8 -#define REG_BB_TRANSCEIVERB_HSPI_READBACK_N 0x8bc -#define REG_BB_FPGA0_XAB_RFINTERFACERB_N 0x8e0 // Useless now // RF Interface Readback Value - - - -// -// 3. BB Register Page9(0x900) -// -#define REG_BB_FPGA1_RFMOD_N 0x900 //RF mode & OFDM TxSC // RF BW Setting?? -#define REG_BB_FPGA1_TXBLOCK_N 0x904 // Useless now -#define REG_BB_FPGA1_DEBUGSELECT_N 0x908 // Useless now -#define REG_BB_FPGA1_TXINFO_N 0x90c // Useless now // Status report?? - - -// -// 4. BB Register PageA(0xA00) -// -// Set Control channel to upper or lower. These settings are required only for 40MHz -#define REG_BB_CCK0_SYSTEM_N 0xa00 -#define REG_BB_CCK0_AFESETTING_N 0xa04 // Disable init gain now // Select RX path by RSSI -#define REG_BB_CCK0_CCA_N 0xa08 // Disable init gain now // Init gain -#define REG_BB_CCK0_RXAGC1_N 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series -#define REG_BB_CCK0_RXAGC2_N 0xa10 //AGC & DAGC -#define REG_BB_CCK0_RXHP_N 0xa14 -#define REG_BB_CCK0_DSPPARAMETER1_N 0xa18 //Timing recovery & Channel estimation threshold -#define REG_BB_CCK0_DSPPARAMETER2_N 0xa1c //SQ threshold -#define REG_BB_CCK0_TXFILTER1_N 0xa20 -#define REG_BB_CCK0_TXFILTER2_N 0xa24 -#define REG_BB_CCK0_DEBUGPORT_N 0xa28 //debug port and Tx filter3 -#define REG_BB_CCK0_FALSEALARMREPORT_N 0xa2c //0xa2d useless now 0xa30-a4f channel report -#define REG_BB_CCK0_TRSSIREPORT_N 0xa50 -#define REG_BB_CCK0_RXREPORT_N 0xa54 //0xa57 -#define REG_BB_CCK0_FACOUNTERLOWER_N 0xa5c //0xa5b -#define REG_BB_CCK0_FACOUNTERUPPER_N 0xa58 //0xa5c - - -// -// 5. BB Register PageC(0xC00) -// -#define REG_BB_OFDM0_LSTF_N 0xc00 -#define REG_BB_OFDM0_TRXPATHENABLE_N 0xc04 -#define REG_BB_OFDM0_TRMUXPAR_N 0xc08 -#define REG_BB_OFDM0_TRSWISOLATION_N 0xc0c -#define REG_BB_OFDM0_XARXAFE_N 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define REG_BB_OFDM0_XARXIQIMBALANCE_N 0xc14 //RxIQ imblance matrix -#define REG_BB_OFDM0_XBRXAFE_N 0xc18 -#define REG_BB_OFDM0_XBRXIQIMBALANCE_N 0xc1c -/* -#define REG_BB_OFDM0_XCRXAFE_N 0xc20 -#define REG_BB_OFDM0_XCRXIQIMBALANCE_N 0xc24 -#define REG_BB_OFDM0_XDRXAFE_N 0xc28 -#define REG_BB_OFDM0_XDRXIQIMBALANCE_N 0xc2c -*/ -#define REG_BB_OFDM0_RXDETECTOR1_N 0xc30 //PD,BW & SBD // DM tune init gain -#define REG_BB_OFDM0_RXDETECTOR2_N 0xc34 //SBD & Fame Sync. -#define REG_BB_OFDM0_RXDETECTOR3_N 0xc38 //Frame Sync. -#define REG_BB_OFDM0_RXDETECTOR4_N 0xc3c //PD, SBD, Frame Sync & Short-GI -#define REG_BB_OFDM0_RXDSP_N 0xc40 //Rx Sync Path -#define REG_BB_OFDM0_CFOANDDAGC_N 0xc44 //CFO & DAGC -#define REG_BB_OFDM0_CCADROPTHRESHOLD_N 0xc48 //CCA Drop threshold -#define REG_BB_OFDM0_ECCATHRESHOLD_N 0xc4c // energy CCA -#define REG_BB_OFDM0_XAAGCCORE1_N 0xc50 // DIG -#define REG_BB_OFDM0_XAAGCCORE2_N 0xc54 -#define REG_BB_OFDM0_XBAGCCORE1_N 0xc58 -#define REG_BB_OFDM0_XBAGCCORE2_N 0xc5c -/* -#define REG_BB_OFDM0_XCAGCCORE1_N 0xc60 -#define REG_BB_OFDM0_XCAGCCORE2_N 0xc64 -#define REG_BB_OFDM0_XDAGCCORE1_N 0xc68 -#define REG_BB_OFDM0_XDAGCCORE2_N 0xc6c -*/ -#define REG_BB_OFDM0_AGCPARAMETER1_N 0xc70 -#define REG_BB_OFDM0_AGCPARAMETER2_N 0xc74 -#define REG_BB_OFDM0_AGCRSSITABLE_N 0xc78 -#define REG_BB_OFDM0_HTSTFAGC_N 0xc7c -#define REG_BB_OFDM0_XATXIQIMBALANC_N 0xc80 // TX PWR TRACK and DIG -#define REG_BB_OFDM0_XATXAFE_N 0xc84 -#define REG_BB_OFDM0_XBTXIQIMBALANCE_N 0xc88 -#define REG_BB_OFDM0_XBTXAFE_N 0xc8c - - -#define REG_BB_OFDM0_XCTXIQIMBALANCE_N 0xc90 -#define REG_BB_OFDM0_XCTXAFE_N 0xc94 -#define REG_BB_OFDM0_XDTXIQIMBALANCE_N 0xc98 -#define REG_BB_OFDM0_XDTXAFE_N 0xc9c -#define REG_BB_OFDM0_RXIQEXTANTA_N 0xca0 - - -#define REG_BB_OFDM0_RXHPPARAMETER_N 0xce0 -#define REG_BB_OFDM0_TXPSEUDONOISEWGT_N 0xce4 -#define REG_BB_OFDM0_FRAMESYNC_N 0xcf0 -#define REG_BB_OFDM0_DFSREPORT_N 0xcf4 -#define REG_BB_OFDM0_TXCOEFF1_N 0xca4 -#define REG_BB_OFDM0_TXCOEFF2_N 0xca8 -#define REG_BB_OFDM0_TXCOEFF3_N 0xcac -#define REG_BB_OFDM0_TXCOEFF4_N 0xcb0 -#define REG_BB_OFDM0_TXCOEFF5_N 0xcb4 -#define REG_BB_OFDM0_TXCOEFF6_N 0xcb8 - - -// -// 6. BB Register PageD(0xD00) -// -#define REG_BB_OFDM1_LSTF_N 0xd00 -#define REG_BB_OFDM1_TRXPATHENABLE_N 0xd04 -#define REG_BB_OFDM1_CFO_N 0xd08 // No setting now -#define REG_BB_OFDM1_CSI1_N 0xd10 -#define REG_BB_OFDM1_SBD_N 0xd14 -#define REG_BB_OFDM1_CSI2_N 0xd18 -#define REG_BB_OFDM1_CFOTRACKING_N 0xd2c -#define REG_BB_OFDM1_TRXMESAURE1_N 0xd34 -#define REG_BB_OFDM1_INTFDET_N 0xd3c -#define REG_BB_OFDM1_PSEUDONOISESTATEAB_N 0xd50 -#define REG_BB_OFDM1_PSEUDONOISESTATECD_N 0xd54 -#define REG_BB_OFDM1_RXPSEUDONOISEWGT_N 0xd58 -#define REG_BB_OFDM_PHYCOUNTER1_N 0xda0 //cca, parity fail -#define REG_BB_OFDM_PHYCOUNTER2_N 0xda4 //rate illegal, crc8 fail -#define REG_BB_OFDM_PHYCOUNTER3_N 0xda8 //MCS not support -#define REG_BB_OFDM_SHORTCFOAB_N 0xdac // No setting now -#define REG_BB_OFDM_SHORTCFOCD_N 0xdb0 -#define REG_BB_OFDM_LONGCFOAB_N 0xdb4 -#define REG_BB_OFDM_LONGCFOCD_N 0xdb8 -#define REG_BB_OFDM_TAILCFOAB_N 0xdbc -#define REG_BB_OFDM_TAILCFOCD_N 0xdc0 -#define REG_BB_OFDM_PWMEASURE1_N 0xdc4 -#define REG_BB_OFDM_PWMEASURE2_N 0xdc8 -#define REG_BB_OFDM_BWREPORT_N 0xdcc -#define REG_BB_OFDM_AGCREPORT_N 0xdd0 -#define REG_BB_OFDM_RXSNR_N 0xdd4 -#define REG_BB_OFDM_RXEVMCSI_N 0xdd8 -#define REG_BB_OFDM_SIGREPORT_N 0xddc - - -// -// 6. BB Register PageE(0xE00) -// -#define REG_BB_TXAGC_A_RATE18_06_N 0xe00 -#define REG_BB_TXAGC_A_RATE54_24_N 0xe04 -#define REG_BB_TXAGC_A_CCK1_MCS32_N 0xe08 -#define REG_BB_TXAGC_A_MCS03_MCS00_N 0xe10 -#define REG_BB_TXAGC_A_MCS07_MCS04_N 0xe14 -#define REG_BB_TXAGC_A_MCS11_MCS08_N 0xe18 -#define REG_BB_TXAGC_A_MCS15_MCS12_N 0xe1c - - -// -// 7. RF Register 0x00-0x2E -// -//Zebra1 -#define REG_RF_ZEBRA1_HSSIENABLE_N 0x0 // Useless now -#define REG_RF_ZEBRA1_TRXENABLE1_N 0x1 -#define REG_RF_ZEBRA1_TRXENABLE2_N 0x2 -#define REG_RF_ZEBRA1_AGC_N 0x4 -#define REG_RF_ZEBRA1_CHARGEPUMP_N 0x5 -#define REG_RF_ZEBRA1_CHANNEL_N 0x7 // RF channel switch -#define REG_RF_ZEBRA1_TXGAIN_N 0x8 // Useless now -#define REG_RF_ZEBRA1_TXLPF_N 0x9 -#define REG_RF_ZEBRA1_RXLPF_N 0xb -#define REG_RF_ZEBRA1_RXHPFCORNER_N 0xc -#define REG_RF_RFCHANNEL_N 0x18 // RF channel switch For T65 RF 0222d -#define REG_RF_CSI_MASK_N 0x42 - -//Zebra4 -#define REG_RF_GLOBALCTRL_N 0 // Useless now -#define REG_RF_RTL8256_TXLPF_N 19 -#define REG_RF_RTL8256_RXLPF_N 11 - -//RTL8258 -#define REG_RF_RTL8258_RSSILPF_N 0xa -#define REG_RF_RTL8258_TXLPF_N 0x11 // Useless now -#define REG_RF_RTL8258_RXLPF_N 0x13 - - -#endif //#if IS_RTL88XX_N -#endif //#ifndef __HALMAC_RF_REG_H__ - - + +#ifndef __HALMAC_BB_RF_REG_H__ +#define __HALMAC_BB_RF_REG_H__ + +#if 1//IS_RTL88XX_AC + + + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + +//============Programming guide Start===================== +/* + BB REG define rules + 1. For all reg define, it should be prefixed by " REG_BB" + + + RF REG define rules + 1. For all reg define, it should be prefixed by " REG_RF" + +*/ +/**** page 8 ****/ +#define REG_BB_CCKENABLE_AC 0x808 // OFDM/CCK block enable +#define REG_BB_RXPATH_AC 0x808 // Rx antenna +#define REG_BB_TXPATH_AC 0x80c // Tx antenna +#define REG_BB_AGC_TABLE_AC 0x82c // AGC tabel select +#define REG_BB_PWED_TH_AC 0x830 +#define REG_BB_BWINDICATION_AC 0x834 +#define REG_BB_CCAONSEC_AC 0x838 +#define REG_BB_L1PEAKTH_AC 0x848 +#define REG_BB_FC_AREA_AC 0x860 // fc_area +#define REG_BB_FPGA0_XB_RFINTERFACEOE_AC 0x864 +#define REG_BB_FPGA0_XAB_RFINTERFACESW_AC 0x870 // RF Interface Software Control +#define REG_BB_FPGA0_XCD_RFINTERFACESW_AC 0x874 +#define REG_BB_FPGA0_XAB_RFPARAMETER_AC 0x878 // RF Parameter +#define REG_BB_FPGA0_XCD_RFPARAMETER_AC 0x87c +#define REG_BB_FPGA0_ANALOGPARAMETER1_AC 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define REG_BB_FPGA0_ANALOGPARAMETER2_AC 0x884 +#define REG_BB_FPGA0_ANALOGPARAMETER3_AC 0x888 +#define REG_BB_FPGA0_ADDACLOCKEN_AC 0x888 // enable ad/da clock1 for dual-phy +#define REG_BB_FPGA0_ANALOGPARAMETER4_AC 0x88c +#define REG_BB_EDCCA_AC 0x8a4 // EDCCA +#define REG_BB_RFMOD_AC 0x8ac //RF mode +#define REG_BB_HSSIREAD_AC 0x8b0 // RF read addr +#define REG_BB_FC_ENABL_VHT_AC 0x8c0 +#define REG_BB_VHTLEN_USE_LSIG_AC 0x8c3 // Use LSIG for VHT length +#define REG_BB_ADC_BUF_CLK_AC 0x8c4 + +/**** page 9 ****/ +#define REG_BB_SINGLETONE_CONTTX_AC 0x914 +#define REG_BB_AGC_TABLE_AC_V2 0x958 + + +/**** page a ****/ +#define REG_BB_CCK_SYSTEM_AC 0xa00 // for cck sideband +#define REG_BB_CCK_RX_AC 0xa04 // for cck rx path selection +#define REG_BB_CCK_CCA_AC 0xa08 // cca threshold +// CCK TX scaling +#define REG_BB_CCK_TXFILTER1_AC 0xa20 +#define REG_BB_CCK_TXFILTER2_AC 0xa24 +#define REG_BB_CCK_TXFILTER3_MSK_AC 0xa28 +#define REG_BB_CCK_FALSEALARM_AC 0xa5c // counter for cck false alarm + +/**** page b ****/ +// RSSI Dump +#define REG_BB_A_RSSIDUMP_AC 0xBF0 +#define REG_BB_B_RSSIDUMP_AC 0xBF1 +#define REG_BB_S1_RXEVMDUMP_AC 0xBF4 +#define REG_BB_S2_RXEVMDUMP_AC 0xBF5 +#define REG_BB_A_RXSNRDUMP_AC 0xBF6 +#define REG_BB_B_RXSNRDUMP_AC 0xBF7 +#define REG_BB_A_CFOSHORTDUMP_AC 0xBF8 +#define REG_BB_B_CFOSHORTDUMP_AC 0xBFA +#define REG_BB_A_CFOLONGDUMP_AC 0xBEC +#define REG_BB_B_CFOLONGDUMP_AC 0xBEE +// YN: mask the following register definition temporarily +//#define REG_BB_PDP_ANTA_AC 0xb00 +//#define REG_BB_PDP_ANTA_4_AC 0xb04 +//#define REG_BB_CONFIG_PMPD_ANTA_AC 0xb28 +//#define REG_BB_CONFIG_ANTA_AC 0xb68 +//#define REG_BB_CONFIG_ANTB_AC 0xb6c +//#define REG_BB_PDP_ANTB_AC 0xb70 +//#define REG_BB_PDP_ANTB_4_AC 0xb74 +//#define REG_BB_CONFIG_PMPD_ANTB_AC 0xb98 +//#define REG_BB_APK_AC 0xbd8 + +/**** page c ****/ +#define REG_BB_A_RXIQC_AB_AC 0xc10 //RxIQ imblance matrix coeff. A & B +#define REG_BB_A_RXIQC_CD_AC 0xc14 //RxIQ imblance matrix coeff. C & D +#define REG_BB_AGC_TABLE_AC_V1 0xc1c + +// TX AGC +#define REG_BB_TXAGC_A_CCK11_CCK1_AC 0xc20 +#define REG_BB_TXAGC_A_OFDM18_OFDM6_AC 0xc24 +#define REG_BB_TXAGC_A_OFDM54_OFDM24_AC 0xc28 +#define REG_BB_TXAGC_A_MCS3_MCS0_AC 0xc2c +#define REG_BB_TXAGC_A_MCS7_MCS4_AC 0xc30 +#define REG_BB_TXAGC_A_MCS11_MCS8_AC 0xc34 +#define REG_BB_TXAGC_A_MCS15_MCS12_AC 0xc38 +#define REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC 0xc3c +#define REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC 0xc40 +#define REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC 0xc44 +#define REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC 0xc48 +#define REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC 0xc4c +// DIG-related +#define REG_BB_A_IGI_AC 0xc50 // Initial Gain for path-A +// AFE-related +#define REG_BB_A_AFEPWR1_AC 0xc60 // dynamic AFE power control +#define REG_BB_A_AFEPWR2_AC 0xc64 // dynamic AFE power control +#define REG_BB_A_RX_WAITCCA_TX_CCKRFON_AC 0xc68 +#define REG_BB_A_TX_CCKBBON_OFDMRFON_AC 0xc6c +#define REG_BB_A_TX_OFDMBBON_TX2RX_AC 0xc70 +#define REG_BB_A_TX2TX_RXCCK_AC 0xc74 +#define REG_BB_A_RX_OFDM_WAITRIFS_AC 0xc78 +#define REG_BB_A_RX2RX_BT_AC 0xc7c +#define REG_BB_A_SLEEP_NAV_AC 0xc80 +#define REG_BB_A_PMPD_AC 0xc84 +#define REG_BB_A_LSSIWRITE_AC 0xc90 // RF write addr +#define REG_BB_A_RFE_PINMUX_AC 0xcb0 // Path_A RFE cotrol pinmux +#define REG_BB_A_RFE_AC 0xcb8 // Path_A RFE cotrol + +/**** page d ****/ +#define REG_BB_A_PIREAD_AC 0xd04 // RF readback with PI +#define REG_BB_B_PIREAD_AC 0xd44 // RF readback with PI +#define REG_BB_C_PIREAD_AC 0xd84 // RF readback with PI +#define REG_BB_D_PIREAD_AC 0xdc4 // RF readback with PI +#define REG_BB_A_SIREAD_AC 0xd08 // RF readback with SI +#define REG_BB_B_SIREAD_AC 0xd48 // RF readback with SI +#define REG_BB_C_SIREAD_AC 0xd88 // RF readback with SI +#define REG_BB_D_SIREAD_AC 0xdc8 // RF readback with SI + + +/**** page e ****/ +// RXIQC +#define REG_BB_B_TXSCALE_AC 0xe1c // Path_B TX scaling factor +#define REG_BB_B_RXIQC_AB_AC 0xe10 //RxIQ imblance matrix coeff. A & B +#define REG_BB_B_RXIQC_CD_AC 0xe14 //RxIQ imblance matrix coeff. C & D + +// TX AGC +#define REG_BB_TXAGC_B_CCK11_CCK1_AC 0xe20 +#define REG_BB_TXAGC_B_OFDM18_OFDM6_AC 0xe24 +#define REG_BB_TXAGC_B_OFDM54_OFDM24_AC 0xe28 +#define REG_BB_TXAGC_B_MCS3_MCS0_AC 0xe2c +#define REG_BB_TXAGC_B_MCS7_MCS4_AC 0xe30 +#define REG_BB_TXAGC_B_MCS11_MCS8_AC 0xe34 +#define REG_BB_TXAGC_B_MCS15_MCS12_AC 0xe38 +#define REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC 0xe3c +#define REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC 0xe40 +#define REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC 0xe44 +#define REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC 0xe48 +#define REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC 0xe4c + +// DIG-related +#define REG_BB_B_IGI_AC 0xe50 // Initial Gain for path-B +#define REG_BB_B_LSSIWRITE_AC 0xe90 // RF write addr + +// Misc functions +#define REG_BB_B_RFE_PINMUX_AC 0xeb0 // Path_B RFE control pinmux +#define REG_BB_B_RFE_AC 0xeb8 // Path_B RFE control + +/**** page f ****/ +// DIG-related +#define REG_BB_OFDM_FALSEALARM1_AC 0xf48 // counter for break +#define REG_BB_OFDM_FALSEALARM2_AC 0xf4c // counter for spoofing +// Report-related +#define REG_BB_OFDM_SHORTCFOAB_AC 0xf60 +#define REG_BB_OFDM_LONGCFOAB_AC 0xf64 +#define REG_BB_OFDM_ENDCFOAB_AC 0xf70 +#define REG_BB_OFDM_AGCREPORT_AC 0xf84 +#define REG_BB_OFDM_RXSNR_AC 0xf88 +#define REG_BB_OFDM_RXEVMCSI_AC 0xf8c +#define REG_BB_OFDM_SIGREPORT_AC 0xf90 + +/**** page 18 ****/ +// TX AGC +#define REG_BB_TXAGC_C_CCK11_CCK1_AC 0x1820 +#define REG_BB_TXAGC_C_OFDM18_OFDM6_AC 0x1824 +#define REG_BB_TXAGC_C_OFDM54_OFDM24_AC 0x1828 +#define REG_BB_TXAGC_C_MCS3_MCS0_AC 0x182c +#define REG_BB_TXAGC_C_MCS7_MCS4_AC 0x1830 +#define REG_BB_TXAGC_C_MCS11_MCS8_AC 0x1834 +#define REG_BB_TXAGC_C_MCS15_MCS12_AC 0x1838 +#define REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC 0x183c +#define REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC 0x1840 +#define REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC 0x1844 +#define REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC 0x1848 +#define REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC 0x184c + +#define REG_BB_C_LSSIWRITE_AC 0x1890 // RF write addr +#define REG_BB_C_RFE_PINMUX_AC 0x18b4 // Path_C RFE control pinmux + + +/**** page 1a ****/ +// TX AGC +#define REG_BB_TXAGC_D_CCK11_CCK1_AC 0x1a20 +#define REG_BB_TXAGC_D_OFDM18_OFDM6_AC 0x1a24 +#define REG_BB_TXAGC_D_OFDM54_OFDM24_AC 0x1a28 +#define REG_BB_TXAGC_D_MCS3_MCS0_AC 0x1a2c +#define REG_BB_TXAGC_D_MCS7_MCS4_AC 0x1a30 +#define REG_BB_TXAGC_D_MCS11_MCS8_AC 0x1a34 +#define REG_BB_TXAGC_D_MCS15_MCS12_AC 0x1a38 +#define REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC 0x1a3c +#define REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC 0x1a40 +#define REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC 0x1a44 +#define REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC 0x1a48 +#define REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC 0x1a4c + +#define REG_BB_D_LSSIWRITE_AC 0x1a90 // RF write addr +#define REG_BB_D_RFE_PINMUX_AC 0x1ab4 // Path_D RFE control pinmux + + +////////////////////////////////////// + + + + +// RF Register +// +#define REG_RF_AC_AC 0x00 +#define REG_RF_RF_TOP_AC 0x07 +#define REG_RF_TXLOK_AC 0x08 +#define REG_RF_TXAPK_AC 0x0B +#define REG_RF_CHNLBW_AC 0x18 // RF channel and BW switch +#define REG_RF_TXLCTANK_AC 0x54 +#define REG_RF_APK_AC 0x63 +#define REG_BRF_CHNLBW_MOD_AG_AC 0x70300 +#define REG_BRF_CHNLBW_BW_AC 0xc00 +#define REG_RF_RCK1_AC 0x1c +#define REG_RF_RCK2_AC 0x1d +#define REG_RF_RCK3_AC 0x1e +#define REG_RF_LCK_AC 0xB4 +#define REG_BB_BRFREGOFFSETMASK_AC 0xfffff + + +#endif //#if IS_RTL88XX_AC + + +#if 1//IS_RTL88XX_N + +// +// 2. BB Register Page8(0x800) +// +#define REG_BB_FPGA0_RFMOD_N 0x800 //RF mode & CCK TxSC // RF BW Setting?? +#define REG_BB_FPGA0_TXINFO_N 0x804 // Status report?? +#define REG_BB_FPGA0_PSDFUNCTION_N 0x808 +#define REG_BB_FPGA0_TXGAINSTAGE_N 0x80c // Set TX PWR init gain? +#define REG_BB_FPGA0_RFTIMING1_N 0x810 // Useless now +#define REG_BB_FPGA0_RFTIMING2_N 0x814 +#define REG_BB_PRIMESC_N 0x818 + +#define REG_BB_FPGA0_XA_HSSIPARAMETER1_N 0x820 // RF 3 wire register +#define REG_BB_FPGA0_XA_HSSIPARAMETER2_N 0x824 +#define REG_BB_FPGA0_XB_HSSIPARAMETER1_N 0x828 +#define REG_BB_FPGA0_XB_HSSIPARAMETER2_N 0x82c +#define REG_BB_TXAGC_B_RATE18_06_N 0x830 +#define REG_BB_TXAGC_B_RATE54_24_N 0x834 +#define REG_BB_TXAGC_B_CCK5_1_MCS32_N 0x838 +#define REG_BB_TXAGC_B_MCS03_MCS00_N 0x83c +#define REG_BB_FPGA0_XA_LSSIPARAMETER_N 0x840 +#define REG_BB_FPGA0_XB_LSSIPARAMETER_N 0x844 +#define REG_BB_TXAGC_B_MCS07_MCS04_N 0x848 +#define REG_BB_TXAGC_B_MCS11_MCS08_N 0x84c +#define REG_BB_FPGA0_RFWAKEUPPARAMETER_N 0x850 // Useless now +#define REG_BB_FPGA0_RFSLEEPUPPARAMETER_N 0x854 +#define REG_BB_FPGA0_XAB_SWITCHCONTROL_N 0x858 // RF Channel switch +#define REG_BB_FPGA0_XCD_SWITCHCONTROL_N 0x85c +#define REG_BB_FPGA0_XA_RFINTERFACEOE_N 0x860 // RF Channel switch +#define REG_BB_FPGA0_XB_RFINTERFACEOE_N 0x864 +#define REG_BB_TXAGC_B_MCS15_MCS12_N 0x868 +#define REG_BB_TXAGC_A_CCK11_2_B_CCK11_N 0x86c +#define REG_BB_FPGA0_XAB_RFINTERFACESW_N 0x870 // RF Interface Software Control +#define REG_BB_FPGA0_XCD_RFINTERFACESW_N 0x874 +#define REG_BB_FPGA0_XAB_RFPARAMETER_N 0x878 // RF Parameter +#define REG_BB_FPGA0_XCD_RFPARAMETER_N 0x87c +#define REG_BB_FPGA0_ANALOGPARAMETER1_N 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define REG_BB_FPGA0_ANALOGPARAMETER2_N 0x884 +#define REG_BB_FPGA0_ANALOGPARAMETER3_N 0x888 // Useless now +#define REG_BB_FPGA0_ANALOGPARAMETER4_N 0x88c +#define REG_BB_FPGA0_XA_LSSIREADBACK_N 0x8a0 // Tranceiver LSSI Readback +#define REG_BB_FPGA0_XB_LSSIREADBACK_N 0x8a4 + +#define REG_BB_FPGA0_PSDREPORT_N 0x8b4 // Useless now +#define REG_BB_TRANSCEIVERA_HSPI_READBACK_N 0x8b8 +#define REG_BB_TRANSCEIVERB_HSPI_READBACK_N 0x8bc +#define REG_BB_FPGA0_XAB_RFINTERFACERB_N 0x8e0 // Useless now // RF Interface Readback Value + + + +// +// 3. BB Register Page9(0x900) +// +#define REG_BB_FPGA1_RFMOD_N 0x900 //RF mode & OFDM TxSC // RF BW Setting?? +#define REG_BB_FPGA1_TXBLOCK_N 0x904 // Useless now +#define REG_BB_FPGA1_DEBUGSELECT_N 0x908 // Useless now +#define REG_BB_FPGA1_TXINFO_N 0x90c // Useless now // Status report?? + + +// +// 4. BB Register PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define REG_BB_CCK0_SYSTEM_N 0xa00 +#define REG_BB_CCK0_AFESETTING_N 0xa04 // Disable init gain now // Select RX path by RSSI +#define REG_BB_CCK0_CCA_N 0xa08 // Disable init gain now // Init gain +#define REG_BB_CCK0_RXAGC1_N 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define REG_BB_CCK0_RXAGC2_N 0xa10 //AGC & DAGC +#define REG_BB_CCK0_RXHP_N 0xa14 +#define REG_BB_CCK0_DSPPARAMETER1_N 0xa18 //Timing recovery & Channel estimation threshold +#define REG_BB_CCK0_DSPPARAMETER2_N 0xa1c //SQ threshold +#define REG_BB_CCK0_TXFILTER1_N 0xa20 +#define REG_BB_CCK0_TXFILTER2_N 0xa24 +#define REG_BB_CCK0_DEBUGPORT_N 0xa28 //debug port and Tx filter3 +#define REG_BB_CCK0_FALSEALARMREPORT_N 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define REG_BB_CCK0_TRSSIREPORT_N 0xa50 +#define REG_BB_CCK0_RXREPORT_N 0xa54 //0xa57 +#define REG_BB_CCK0_FACOUNTERLOWER_N 0xa5c //0xa5b +#define REG_BB_CCK0_FACOUNTERUPPER_N 0xa58 //0xa5c + + +// +// 5. BB Register PageC(0xC00) +// +#define REG_BB_OFDM0_LSTF_N 0xc00 +#define REG_BB_OFDM0_TRXPATHENABLE_N 0xc04 +#define REG_BB_OFDM0_TRMUXPAR_N 0xc08 +#define REG_BB_OFDM0_TRSWISOLATION_N 0xc0c +#define REG_BB_OFDM0_XARXAFE_N 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define REG_BB_OFDM0_XARXIQIMBALANCE_N 0xc14 //RxIQ imblance matrix +#define REG_BB_OFDM0_XBRXAFE_N 0xc18 +#define REG_BB_OFDM0_XBRXIQIMBALANCE_N 0xc1c +/* +#define REG_BB_OFDM0_XCRXAFE_N 0xc20 +#define REG_BB_OFDM0_XCRXIQIMBALANCE_N 0xc24 +#define REG_BB_OFDM0_XDRXAFE_N 0xc28 +#define REG_BB_OFDM0_XDRXIQIMBALANCE_N 0xc2c +*/ +#define REG_BB_OFDM0_RXDETECTOR1_N 0xc30 //PD,BW & SBD // DM tune init gain +#define REG_BB_OFDM0_RXDETECTOR2_N 0xc34 //SBD & Fame Sync. +#define REG_BB_OFDM0_RXDETECTOR3_N 0xc38 //Frame Sync. +#define REG_BB_OFDM0_RXDETECTOR4_N 0xc3c //PD, SBD, Frame Sync & Short-GI +#define REG_BB_OFDM0_RXDSP_N 0xc40 //Rx Sync Path +#define REG_BB_OFDM0_CFOANDDAGC_N 0xc44 //CFO & DAGC +#define REG_BB_OFDM0_CCADROPTHRESHOLD_N 0xc48 //CCA Drop threshold +#define REG_BB_OFDM0_ECCATHRESHOLD_N 0xc4c // energy CCA +#define REG_BB_OFDM0_XAAGCCORE1_N 0xc50 // DIG +#define REG_BB_OFDM0_XAAGCCORE2_N 0xc54 +#define REG_BB_OFDM0_XBAGCCORE1_N 0xc58 +#define REG_BB_OFDM0_XBAGCCORE2_N 0xc5c +/* +#define REG_BB_OFDM0_XCAGCCORE1_N 0xc60 +#define REG_BB_OFDM0_XCAGCCORE2_N 0xc64 +#define REG_BB_OFDM0_XDAGCCORE1_N 0xc68 +#define REG_BB_OFDM0_XDAGCCORE2_N 0xc6c +*/ +#define REG_BB_OFDM0_AGCPARAMETER1_N 0xc70 +#define REG_BB_OFDM0_AGCPARAMETER2_N 0xc74 +#define REG_BB_OFDM0_AGCRSSITABLE_N 0xc78 +#define REG_BB_OFDM0_HTSTFAGC_N 0xc7c +#define REG_BB_OFDM0_XATXIQIMBALANC_N 0xc80 // TX PWR TRACK and DIG +#define REG_BB_OFDM0_XATXAFE_N 0xc84 +#define REG_BB_OFDM0_XBTXIQIMBALANCE_N 0xc88 +#define REG_BB_OFDM0_XBTXAFE_N 0xc8c + + +#define REG_BB_OFDM0_XCTXIQIMBALANCE_N 0xc90 +#define REG_BB_OFDM0_XCTXAFE_N 0xc94 +#define REG_BB_OFDM0_XDTXIQIMBALANCE_N 0xc98 +#define REG_BB_OFDM0_XDTXAFE_N 0xc9c +#define REG_BB_OFDM0_RXIQEXTANTA_N 0xca0 + + +#define REG_BB_OFDM0_RXHPPARAMETER_N 0xce0 +#define REG_BB_OFDM0_TXPSEUDONOISEWGT_N 0xce4 +#define REG_BB_OFDM0_FRAMESYNC_N 0xcf0 +#define REG_BB_OFDM0_DFSREPORT_N 0xcf4 +#define REG_BB_OFDM0_TXCOEFF1_N 0xca4 +#define REG_BB_OFDM0_TXCOEFF2_N 0xca8 +#define REG_BB_OFDM0_TXCOEFF3_N 0xcac +#define REG_BB_OFDM0_TXCOEFF4_N 0xcb0 +#define REG_BB_OFDM0_TXCOEFF5_N 0xcb4 +#define REG_BB_OFDM0_TXCOEFF6_N 0xcb8 + + +// +// 6. BB Register PageD(0xD00) +// +#define REG_BB_OFDM1_LSTF_N 0xd00 +#define REG_BB_OFDM1_TRXPATHENABLE_N 0xd04 +#define REG_BB_OFDM1_CFO_N 0xd08 // No setting now +#define REG_BB_OFDM1_CSI1_N 0xd10 +#define REG_BB_OFDM1_SBD_N 0xd14 +#define REG_BB_OFDM1_CSI2_N 0xd18 +#define REG_BB_OFDM1_CFOTRACKING_N 0xd2c +#define REG_BB_OFDM1_TRXMESAURE1_N 0xd34 +#define REG_BB_OFDM1_INTFDET_N 0xd3c +#define REG_BB_OFDM1_PSEUDONOISESTATEAB_N 0xd50 +#define REG_BB_OFDM1_PSEUDONOISESTATECD_N 0xd54 +#define REG_BB_OFDM1_RXPSEUDONOISEWGT_N 0xd58 +#define REG_BB_OFDM_PHYCOUNTER1_N 0xda0 //cca, parity fail +#define REG_BB_OFDM_PHYCOUNTER2_N 0xda4 //rate illegal, crc8 fail +#define REG_BB_OFDM_PHYCOUNTER3_N 0xda8 //MCS not support +#define REG_BB_OFDM_SHORTCFOAB_N 0xdac // No setting now +#define REG_BB_OFDM_SHORTCFOCD_N 0xdb0 +#define REG_BB_OFDM_LONGCFOAB_N 0xdb4 +#define REG_BB_OFDM_LONGCFOCD_N 0xdb8 +#define REG_BB_OFDM_TAILCFOAB_N 0xdbc +#define REG_BB_OFDM_TAILCFOCD_N 0xdc0 +#define REG_BB_OFDM_PWMEASURE1_N 0xdc4 +#define REG_BB_OFDM_PWMEASURE2_N 0xdc8 +#define REG_BB_OFDM_BWREPORT_N 0xdcc +#define REG_BB_OFDM_AGCREPORT_N 0xdd0 +#define REG_BB_OFDM_RXSNR_N 0xdd4 +#define REG_BB_OFDM_RXEVMCSI_N 0xdd8 +#define REG_BB_OFDM_SIGREPORT_N 0xddc + + +// +// 6. BB Register PageE(0xE00) +// +#define REG_BB_TXAGC_A_RATE18_06_N 0xe00 +#define REG_BB_TXAGC_A_RATE54_24_N 0xe04 +#define REG_BB_TXAGC_A_CCK1_MCS32_N 0xe08 +#define REG_BB_TXAGC_A_MCS03_MCS00_N 0xe10 +#define REG_BB_TXAGC_A_MCS07_MCS04_N 0xe14 +#define REG_BB_TXAGC_A_MCS11_MCS08_N 0xe18 +#define REG_BB_TXAGC_A_MCS15_MCS12_N 0xe1c + + +// +// 7. RF Register 0x00-0x2E +// +//Zebra1 +#define REG_RF_ZEBRA1_HSSIENABLE_N 0x0 // Useless now +#define REG_RF_ZEBRA1_TRXENABLE1_N 0x1 +#define REG_RF_ZEBRA1_TRXENABLE2_N 0x2 +#define REG_RF_ZEBRA1_AGC_N 0x4 +#define REG_RF_ZEBRA1_CHARGEPUMP_N 0x5 +#define REG_RF_ZEBRA1_CHANNEL_N 0x7 // RF channel switch +#define REG_RF_ZEBRA1_TXGAIN_N 0x8 // Useless now +#define REG_RF_ZEBRA1_TXLPF_N 0x9 +#define REG_RF_ZEBRA1_RXLPF_N 0xb +#define REG_RF_ZEBRA1_RXHPFCORNER_N 0xc +#define REG_RF_RFCHANNEL_N 0x18 // RF channel switch For T65 RF 0222d +#define REG_RF_CSI_MASK_N 0x42 + +//Zebra4 +#define REG_RF_GLOBALCTRL_N 0 // Useless now +#define REG_RF_RTL8256_TXLPF_N 19 +#define REG_RF_RTL8256_RXLPF_N 11 + +//RTL8258 +#define REG_RF_RTL8258_RSSILPF_N 0xa +#define REG_RF_RTL8258_TXLPF_N 0x11 // Useless now +#define REG_RF_RTL8258_RXLPF_N 0x13 + + +#endif //#if IS_RTL88XX_N +#endif //#ifndef __HALMAC_RF_REG_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.c b/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.c old mode 100755 new mode 100644 index 00a56ef87cb..9194e0148d6 --- a/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.c +++ b/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.c @@ -1,340 +1,340 @@ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalMacAPI.c - -Abstract: - Define MAC function support - for Driver - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-07-07 Eric Create. ---*/ - -#include "HalPrecomp.h" - -#ifdef CONFIG_WLAN_MACHAL_API -void associate_halMac_API(struct rtl8192cd_priv *priv) -{ - - priv->pshare->use_macHalAPI = 1; - priv->pHalmac_platform_api = (PHALMAC_PLATFORM_API)kmalloc(sizeof(HALMAC_PLATFORM_API), GFP_ATOMIC); - //priv->pHalmac_adapter = (PHALMAC_ADAPTER)kmalloc(sizeof(HALMAC_ADAPTER), GFP_ATOMIC); - //priv->pHalmac_api = (PHALMAC_API)kmalloc(sizeof(HALMAC_API), GFP_ATOMIC); - - PHALMAC_PLATFORM_API pMacHalFunc = priv->pHalmac_platform_api; - - - // - //Initialization Related - // - pMacHalFunc->SDIO_CMD52_READ = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_READ_8 = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_READ_16 = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_READ_32 = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD52_WRITE = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_WRITE_8 = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_WRITE_16 = MacHalGeneralDummy; - pMacHalFunc->SDIO_CMD53_WRITE_32 = MacHalGeneralDummy; - pMacHalFunc->REG_READ_8 = HALAPI_R8; - pMacHalFunc->REG_READ_16 = HALAPI_R16; - pMacHalFunc->REG_READ_32 = HALAPI_R32; - pMacHalFunc->REG_WRITE_8 = HALAPI_W8; - pMacHalFunc->REG_WRITE_16 = HALAPI_W16; - pMacHalFunc->REG_WRITE_32 = HALAPI_W32; - pMacHalFunc->SEND_RSVD_PAGE = HAL_SEND_RSVD_PAGE; -#ifdef WLAN_SUPPORT_H2C_PACKET - pMacHalFunc->SEND_H2C_PKT = HAL_SEND_H2C_PKT; -#endif - pMacHalFunc->RTL_MALLOC = HALAPI_MALLOC; - pMacHalFunc->RTL_FREE = HALAPI_FREE; - pMacHalFunc->RTL_MEMCPY = HALAPI_MEMCPY; - pMacHalFunc->RTL_MEMSET = HALAPI_MEMSET; - pMacHalFunc->RTL_DELAY_US = HALAPI_DELAY_US; -// pMacHalFunc->SIGNAL_INIT = MacHalGeneralDummy; -// pMacHalFunc->SIGNAL_DEINIT = MacHalGeneralDummy; -// pMacHalFunc->SIGNAL_WAIT = MacHalGeneralDummy; -// pMacHalFunc->SIGNAL_SET = MacHalGeneralDummy; - pMacHalFunc->MSG_PRINT = HALAPI_PRINT; - pMacHalFunc->MUTEX_INIT = HALAPI_MUTEX_INIT; - pMacHalFunc->MUTEX_DEINIT = HALAPI_MUTEX_DEINIT; - pMacHalFunc->MUTEX_LOCK = HALAPI_MUTEX_LOCK; - pMacHalFunc->MUTEX_UNLOCK = HALAPI_MUTEX_UNLOCK; - pMacHalFunc->EVENT_INDICATION = HALAPI_EVENT_INDICATION; -} - -#ifdef WLAN_SUPPORT_H2C_PACKET -u8 HAL_SEND_H2C_PKT( - IN VOID *pDriver_adapter, - IN u8 *pBuf, - IN u32 size -) -{ -#if 1 - //TX_DESC_DATA_88XX desc_data; - PHCI_TX_DMA_QUEUE_STRUCT_88XX cur_q; - PHCI_TX_DMA_MANAGER_88XX ptx_dma; - PTX_BUFFER_DESCRIPTOR cur_txbd; - HAL_PADAPTER pAdapter = (HAL_PADAPTER)pDriver_adapter; - pu1Byte cur_h2c_buffer; - u2Byte host_wrtie,hw_read; - PH2C_PAYLOAD_88XX h2c_buf_start = (PH2C_PAYLOAD_88XX)_GET_HAL_DATA(pAdapter)->h2c_buf; - ptx_dma = (PHCI_TX_DMA_MANAGER_88XX)(_GET_HAL_DATA(pAdapter)->PTxDMA88XX); - cur_q = &(ptx_dma->tx_queue[HCI_TX_DMA_QUEUE_CMD]); - cur_txbd = cur_q->pTXBD_head + cur_q->host_idx; - - cur_h2c_buffer = &(h2c_buf_start[cur_q->host_idx]); - - //memset(&desc_data, 0, sizeof(TX_DESC_DATA_88XX)); - hw_read = GetTxQueueHWIdx88XX(pDriver_adapter,HCI_TX_DMA_QUEUE_CMD); - host_wrtie = cur_q->host_idx; - - //printk("h2c send packet \n"); - if(CIRC_SPACE_RTK(host_wrtie,hw_read,H2C_ENTERY_MAX_NUM) < 1) - { - printk("h2c page full \n"); - return FALSE; - } - - memcpy(cur_h2c_buffer,pBuf,size); - // 1. Fill desc_data - //desc_data.hdrLen = size; - //desc_data.pHdr = pBuf; - // 2. FillTXDESC - //FillH2CTxDesc88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD); - - // 3. SetTXBufferDesc - //SetTxBufferDesc88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD, (PTX_DESC_DATA_88XX)&desc_data); - - if (size) { - _dma_cache_wback(((GET_DESC_FIELD(cur_txbd->TXBD_ELE[1].Dword1, TXBD_DW1_PHYADDR_LOW_MSK, TXBD_DW1_PHYADDR_LOW_SH)|0x80000000) - CONFIG_LUNA_SLAVE_PHYMEM_OFFSET_HAL), - (u4Byte)size); - } - - - //printk("cur_h2c_buffer adr = %x \n",cur_h2c_buffer); - //RT_PRINT_DATA(COMP_SEND, DBG_TRACE, "H2C Payload:\n", cur_h2c_buffer, 32); - - - UpdateSWTXBDHostIdx88XX(pDriver_adapter, cur_q); - SyncSWTXBDHostIdxToHW88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD); - return TRUE; - -#endif -} -#endif - -u8 HAL_SEND_RSVD_PAGE( - IN VOID *pDriver_adapter, - IN u8 *pBuf, - IN u32 size -) -{ - SigninBeaconTXBD88XX(pDriver_adapter,(pu4Byte)pBuf, size); // fill TXDESC & TXBD - - //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, "DLtoTXBUFandDDMA88XX\n", pbuf, len); - - if(_FALSE == DownloadRsvdPage88XX(pDriver_adapter,NULL,0,0)) { - RT_TRACE_F(COMP_INIT, DBG_WARNING,("Download to TXpktbuf fail ! \n")); - return FALSE; - }else{ - return TRUE; - } -} - -u8 -HALAPI_R8( - IN VOID *pDriver_adapter, - IN u32 offset -) -{ - return RTL_R8_F(pDriver_adapter,offset); -} - -u16 -HALAPI_R16( - IN VOID *pDriver_adapter, - IN u32 offset -) -{ - return RTL_R16_F(pDriver_adapter,offset); -} - -u32 -HALAPI_R32( - IN VOID *pDriver_adapter, - IN u32 offset -) -{ - return RTL_R32_F(pDriver_adapter,offset); -} - - -VOID -HALAPI_W8( - IN VOID *pDriver_adapter, - IN u32 offset, - IN u8 value -) -{ - RTL_W8_F(pDriver_adapter,offset,value); -} - -VOID -HALAPI_W16( - IN VOID *pDriver_adapter, - IN u32 offset, - IN u16 value -) -{ - RTL_W16_F(pDriver_adapter,offset,value); -} - -VOID -HALAPI_W32( - IN VOID *pDriver_adapter, - IN u32 offset, - IN u32 value -) -{ - RTL_W32_F(pDriver_adapter,offset,value); -} - -VOID -MacHalGeneralDummy(struct rtl8192cd_priv *priv) -{ -} - -u8 -HALAPI_PRINT( - IN VOID *pDriver_adapter, - IN u32 msg_type, - IN u8 msg_level, - IN s8* lpszFormat,... -) -{ -//#if HALMAC_DEBUG_MESSAGE - printk(lpszFormat); -//#endif - return _TRUE; -} - -VOID -HALAPI_MALLOC( - IN VOID *pDriver_adapter, - IN u32 size -) -{ - kmalloc(size, GFP_ATOMIC); -} - - -VOID -HALAPI_FREE( - IN VOID *pDriver_adapter, - IN VOID *pBuf, - IN u32 size -) -{ - kfree(pBuf); -} - - -VOID -HALAPI_MEMCPY( - IN VOID *pDriver_adapter, - IN VOID *dest, - IN VOID *src, - IN u32 size -) -{ - memcpy(dest,src,size); -} - -VOID -HALAPI_MEMSET( - IN VOID *pDriver_adapter, - IN VOID *pAddress, - IN u8 value, - IN u32 size -) -{ - memset(pAddress,value,size); -} -VOID -HALAPI_DELAY_US( - IN VOID *pDriver_adapter, - IN u32 us -) -{ - delay_us(us); -} -#if 0 -VOID -HALAPI_MSLEEP( - IN VOID *pDriver_adapter, - IN u32 ms -) -{ - delay_ms(ms); -} -#endif -VOID -HALAPI_MUTEX_INIT( - IN VOID *pDriver_adapter, - IN HALMAC_MUTEX *pMutex -) -{ - return; -} - -VOID -HALAPI_MUTEX_DEINIT( - IN VOID *pDriver_adapter, - IN HALMAC_MUTEX *pMutex -) -{ - return; -} - -VOID -HALAPI_MUTEX_LOCK( - IN VOID *pDriver_adapter, - IN HALMAC_MUTEX *pMutex -) -{ - u32 flag; - spin_lock_irqsave(pMutex, flag); -} - - - -VOID -HALAPI_MUTEX_UNLOCK( - IN VOID *pDriver_adapter, - IN HALMAC_MUTEX *pMutex -) -{ - u32 flag; - spin_unlock_irqrestore(pMutex, flag); -} - -VOID -HALAPI_EVENT_INDICATION( - IN VOID *pDriver_adapter, - IN HALMAC_FEATURE_ID feature_id, - IN HALMAC_CMD_PROCESS_STATUS process_status, - IN u8* buf, u32 size -) -{ - return; -} - -#endif - - - + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalMacAPI.c + +Abstract: + Define MAC function support + for Driver + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-07-07 Eric Create. +--*/ + +#include "HalPrecomp.h" + +#ifdef CONFIG_WLAN_MACHAL_API +void associate_halMac_API(struct rtl8192cd_priv *priv) +{ + + priv->pshare->use_macHalAPI = 1; + priv->pHalmac_platform_api = (PHALMAC_PLATFORM_API)kmalloc(sizeof(HALMAC_PLATFORM_API), GFP_ATOMIC); + //priv->pHalmac_adapter = (PHALMAC_ADAPTER)kmalloc(sizeof(HALMAC_ADAPTER), GFP_ATOMIC); + //priv->pHalmac_api = (PHALMAC_API)kmalloc(sizeof(HALMAC_API), GFP_ATOMIC); + + PHALMAC_PLATFORM_API pMacHalFunc = priv->pHalmac_platform_api; + + + // + //Initialization Related + // + pMacHalFunc->SDIO_CMD52_READ = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_READ_8 = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_READ_16 = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_READ_32 = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD52_WRITE = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_WRITE_8 = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_WRITE_16 = MacHalGeneralDummy; + pMacHalFunc->SDIO_CMD53_WRITE_32 = MacHalGeneralDummy; + pMacHalFunc->REG_READ_8 = HALAPI_R8; + pMacHalFunc->REG_READ_16 = HALAPI_R16; + pMacHalFunc->REG_READ_32 = HALAPI_R32; + pMacHalFunc->REG_WRITE_8 = HALAPI_W8; + pMacHalFunc->REG_WRITE_16 = HALAPI_W16; + pMacHalFunc->REG_WRITE_32 = HALAPI_W32; + pMacHalFunc->SEND_RSVD_PAGE = HAL_SEND_RSVD_PAGE; +#ifdef WLAN_SUPPORT_H2C_PACKET + pMacHalFunc->SEND_H2C_PKT = HAL_SEND_H2C_PKT; +#endif + pMacHalFunc->RTL_MALLOC = HALAPI_MALLOC; + pMacHalFunc->RTL_FREE = HALAPI_FREE; + pMacHalFunc->RTL_MEMCPY = HALAPI_MEMCPY; + pMacHalFunc->RTL_MEMSET = HALAPI_MEMSET; + pMacHalFunc->RTL_DELAY_US = HALAPI_DELAY_US; +// pMacHalFunc->SIGNAL_INIT = MacHalGeneralDummy; +// pMacHalFunc->SIGNAL_DEINIT = MacHalGeneralDummy; +// pMacHalFunc->SIGNAL_WAIT = MacHalGeneralDummy; +// pMacHalFunc->SIGNAL_SET = MacHalGeneralDummy; + pMacHalFunc->MSG_PRINT = HALAPI_PRINT; + pMacHalFunc->MUTEX_INIT = HALAPI_MUTEX_INIT; + pMacHalFunc->MUTEX_DEINIT = HALAPI_MUTEX_DEINIT; + pMacHalFunc->MUTEX_LOCK = HALAPI_MUTEX_LOCK; + pMacHalFunc->MUTEX_UNLOCK = HALAPI_MUTEX_UNLOCK; + pMacHalFunc->EVENT_INDICATION = HALAPI_EVENT_INDICATION; +} + +#ifdef WLAN_SUPPORT_H2C_PACKET +u8 HAL_SEND_H2C_PKT( + IN VOID *pDriver_adapter, + IN u8 *pBuf, + IN u32 size +) +{ +#if 1 + //TX_DESC_DATA_88XX desc_data; + PHCI_TX_DMA_QUEUE_STRUCT_88XX cur_q; + PHCI_TX_DMA_MANAGER_88XX ptx_dma; + PTX_BUFFER_DESCRIPTOR cur_txbd; + HAL_PADAPTER pAdapter = (HAL_PADAPTER)pDriver_adapter; + pu1Byte cur_h2c_buffer; + u2Byte host_wrtie,hw_read; + PH2C_PAYLOAD_88XX h2c_buf_start = (PH2C_PAYLOAD_88XX)_GET_HAL_DATA(pAdapter)->h2c_buf; + ptx_dma = (PHCI_TX_DMA_MANAGER_88XX)(_GET_HAL_DATA(pAdapter)->PTxDMA88XX); + cur_q = &(ptx_dma->tx_queue[HCI_TX_DMA_QUEUE_CMD]); + cur_txbd = cur_q->pTXBD_head + cur_q->host_idx; + + cur_h2c_buffer = &(h2c_buf_start[cur_q->host_idx]); + + //memset(&desc_data, 0, sizeof(TX_DESC_DATA_88XX)); + hw_read = GetTxQueueHWIdx88XX(pDriver_adapter,HCI_TX_DMA_QUEUE_CMD); + host_wrtie = cur_q->host_idx; + + //printk("h2c send packet \n"); + if(CIRC_SPACE_RTK(host_wrtie,hw_read,H2C_ENTERY_MAX_NUM) < 1) + { + printk("h2c page full \n"); + return FALSE; + } + + memcpy(cur_h2c_buffer,pBuf,size); + // 1. Fill desc_data + //desc_data.hdrLen = size; + //desc_data.pHdr = pBuf; + // 2. FillTXDESC + //FillH2CTxDesc88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD); + + // 3. SetTXBufferDesc + //SetTxBufferDesc88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD, (PTX_DESC_DATA_88XX)&desc_data); + + if (size) { + _dma_cache_wback(((GET_DESC_FIELD(cur_txbd->TXBD_ELE[1].Dword1, TXBD_DW1_PHYADDR_LOW_MSK, TXBD_DW1_PHYADDR_LOW_SH)|0x80000000) - CONFIG_LUNA_SLAVE_PHYMEM_OFFSET_HAL), + (u4Byte)size); + } + + + //printk("cur_h2c_buffer adr = %x \n",cur_h2c_buffer); + //RT_PRINT_DATA(COMP_SEND, DBG_TRACE, "H2C Payload:\n", cur_h2c_buffer, 32); + + + UpdateSWTXBDHostIdx88XX(pDriver_adapter, cur_q); + SyncSWTXBDHostIdxToHW88XX(pDriver_adapter, HCI_TX_DMA_QUEUE_CMD); + return TRUE; + +#endif +} +#endif + +u8 HAL_SEND_RSVD_PAGE( + IN VOID *pDriver_adapter, + IN u8 *pBuf, + IN u32 size +) +{ + SigninBeaconTXBD88XX(pDriver_adapter,(pu4Byte)pBuf, size); // fill TXDESC & TXBD + + //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, "DLtoTXBUFandDDMA88XX\n", pbuf, len); + + if(_FALSE == DownloadRsvdPage88XX(pDriver_adapter,NULL,0,0)) { + RT_TRACE_F(COMP_INIT, DBG_WARNING,("Download to TXpktbuf fail ! \n")); + return FALSE; + }else{ + return TRUE; + } +} + +u8 +HALAPI_R8( + IN VOID *pDriver_adapter, + IN u32 offset +) +{ + return RTL_R8_F(pDriver_adapter,offset); +} + +u16 +HALAPI_R16( + IN VOID *pDriver_adapter, + IN u32 offset +) +{ + return RTL_R16_F(pDriver_adapter,offset); +} + +u32 +HALAPI_R32( + IN VOID *pDriver_adapter, + IN u32 offset +) +{ + return RTL_R32_F(pDriver_adapter,offset); +} + + +VOID +HALAPI_W8( + IN VOID *pDriver_adapter, + IN u32 offset, + IN u8 value +) +{ + RTL_W8_F(pDriver_adapter,offset,value); +} + +VOID +HALAPI_W16( + IN VOID *pDriver_adapter, + IN u32 offset, + IN u16 value +) +{ + RTL_W16_F(pDriver_adapter,offset,value); +} + +VOID +HALAPI_W32( + IN VOID *pDriver_adapter, + IN u32 offset, + IN u32 value +) +{ + RTL_W32_F(pDriver_adapter,offset,value); +} + +VOID +MacHalGeneralDummy(struct rtl8192cd_priv *priv) +{ +} + +u8 +HALAPI_PRINT( + IN VOID *pDriver_adapter, + IN u32 msg_type, + IN u8 msg_level, + IN s8* lpszFormat,... +) +{ +//#if HALMAC_DEBUG_MESSAGE + printk(lpszFormat); +//#endif + return _TRUE; +} + +VOID +HALAPI_MALLOC( + IN VOID *pDriver_adapter, + IN u32 size +) +{ + kmalloc(size, GFP_ATOMIC); +} + + +VOID +HALAPI_FREE( + IN VOID *pDriver_adapter, + IN VOID *pBuf, + IN u32 size +) +{ + kfree(pBuf); +} + + +VOID +HALAPI_MEMCPY( + IN VOID *pDriver_adapter, + IN VOID *dest, + IN VOID *src, + IN u32 size +) +{ + memcpy(dest,src,size); +} + +VOID +HALAPI_MEMSET( + IN VOID *pDriver_adapter, + IN VOID *pAddress, + IN u8 value, + IN u32 size +) +{ + memset(pAddress,value,size); +} +VOID +HALAPI_DELAY_US( + IN VOID *pDriver_adapter, + IN u32 us +) +{ + delay_us(us); +} +#if 0 +VOID +HALAPI_MSLEEP( + IN VOID *pDriver_adapter, + IN u32 ms +) +{ + delay_ms(ms); +} +#endif +VOID +HALAPI_MUTEX_INIT( + IN VOID *pDriver_adapter, + IN HALMAC_MUTEX *pMutex +) +{ + return; +} + +VOID +HALAPI_MUTEX_DEINIT( + IN VOID *pDriver_adapter, + IN HALMAC_MUTEX *pMutex +) +{ + return; +} + +VOID +HALAPI_MUTEX_LOCK( + IN VOID *pDriver_adapter, + IN HALMAC_MUTEX *pMutex +) +{ + u32 flag; + spin_lock_irqsave(pMutex, flag); +} + + + +VOID +HALAPI_MUTEX_UNLOCK( + IN VOID *pDriver_adapter, + IN HALMAC_MUTEX *pMutex +) +{ + u32 flag; + spin_unlock_irqrestore(pMutex, flag); +} + +VOID +HALAPI_EVENT_INDICATION( + IN VOID *pDriver_adapter, + IN HALMAC_FEATURE_ID feature_id, + IN HALMAC_CMD_PROCESS_STATUS process_status, + IN u8* buf, u32 size +) +{ + return; +} + +#endif + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.h b/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.h old mode 100755 new mode 100644 index 0188a85d340..5a4ca552af5 --- a/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMacAPI.h @@ -1,54 +1,54 @@ - -#ifndef __HALMACAPI_H__ -#define __HALMACAPI_H__ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalMacFunc.h - -Abstract: - Define MAC function support - for Driver - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-07-07 Eric Create. ---*/ - - - -#include "./HalMac88XX/halmac_2_platform.h" - - - -void associate_halMac_API(struct rtl8192cd_priv *priv); -VOID MacHalGeneralDummy(struct rtl8192cd_priv *priv); -u8 HALAPI_R8(VOID *pDriver_adapter,u32 offset); -u8 HAL_SEND_RSVD_PAGE(VOID *pDriver_adapter,u8 *pBuf,u32 size); -u8 HAL_SEND_H2C_PKT(VOID *pDriver_adapter,u8 *pBuf,u32 size); -u16 HALAPI_R16(VOID *pDriver_adapter,u32 offset); -u32 HALAPI_R32(VOID *pDriver_adapter,u32 offset); -VOID HALAPI_W8(VOID *pDriver_adapter,u32 offset,u8 value); -VOID HALAPI_W16(VOID *pDriver_adapter,u32 offset,u16 value); -VOID HALAPI_W32(VOID *pDriver_adapter,u32 offset,u32 value); -u8 HALAPI_PRINT(VOID *pDriver_adapter,u32 msg_type,u8 msg_level,s8* lpszFormat,...); -VOID HALAPI_MALLOC(VOID *pDriver_adapter,u32 ms); -VOID HALAPI_FREE(VOID *pDriver_adapter,VOID *pBuf,u32 size); -VOID HALAPI_MEMCPY(VOID *pDriver_adapter,VOID *dest,VOID *src,u32 size); -VOID HALAPI_MEMSET(VOID *pDriver_adapter,VOID *pAddress,u8 value,u32 size); -VOID HALAPI_DELAY_US(VOID *pDriver_adapter,u32 us); -VOID HALAPI_MSLEEP(VOID *pDriver_adapter,u32 ms); -VOID HALAPI_MUTEX_INIT(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); -VOID HALAPI_MUTEX_DEINIT(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); -VOID HALAPI_MUTEX_LOCK(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); -VOID HALAPI_MUTEX_UNLOCK(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); -VOID HALAPI_EVENT_INDICATION(VOID *pDriver_adapter,HALMAC_FEATURE_ID feature_id,HALMAC_CMD_PROCESS_STATUS process_status,u8* buf, u32 size); - - - - -#endif //__HALMACAPI_H__ - - + +#ifndef __HALMACAPI_H__ +#define __HALMACAPI_H__ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalMacFunc.h + +Abstract: + Define MAC function support + for Driver + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-07-07 Eric Create. +--*/ + + + +#include "./HalMac88XX/halmac_2_platform.h" + + + +void associate_halMac_API(struct rtl8192cd_priv *priv); +VOID MacHalGeneralDummy(struct rtl8192cd_priv *priv); +u8 HALAPI_R8(VOID *pDriver_adapter,u32 offset); +u8 HAL_SEND_RSVD_PAGE(VOID *pDriver_adapter,u8 *pBuf,u32 size); +u8 HAL_SEND_H2C_PKT(VOID *pDriver_adapter,u8 *pBuf,u32 size); +u16 HALAPI_R16(VOID *pDriver_adapter,u32 offset); +u32 HALAPI_R32(VOID *pDriver_adapter,u32 offset); +VOID HALAPI_W8(VOID *pDriver_adapter,u32 offset,u8 value); +VOID HALAPI_W16(VOID *pDriver_adapter,u32 offset,u16 value); +VOID HALAPI_W32(VOID *pDriver_adapter,u32 offset,u32 value); +u8 HALAPI_PRINT(VOID *pDriver_adapter,u32 msg_type,u8 msg_level,s8* lpszFormat,...); +VOID HALAPI_MALLOC(VOID *pDriver_adapter,u32 ms); +VOID HALAPI_FREE(VOID *pDriver_adapter,VOID *pBuf,u32 size); +VOID HALAPI_MEMCPY(VOID *pDriver_adapter,VOID *dest,VOID *src,u32 size); +VOID HALAPI_MEMSET(VOID *pDriver_adapter,VOID *pAddress,u8 value,u32 size); +VOID HALAPI_DELAY_US(VOID *pDriver_adapter,u32 us); +VOID HALAPI_MSLEEP(VOID *pDriver_adapter,u32 ms); +VOID HALAPI_MUTEX_INIT(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); +VOID HALAPI_MUTEX_DEINIT(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); +VOID HALAPI_MUTEX_LOCK(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); +VOID HALAPI_MUTEX_UNLOCK(VOID *pDriver_adapter,HALMAC_MUTEX *pMutex); +VOID HALAPI_EVENT_INDICATION(VOID *pDriver_adapter,HALMAC_FEATURE_ID feature_id,HALMAC_CMD_PROCESS_STATUS process_status,u8* buf, u32 size); + + + + +#endif //__HALMACAPI_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.c b/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.c old mode 100755 new mode 100644 index 74823220d83..986c6f50867 --- a/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.c +++ b/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.c @@ -1,113 +1,113 @@ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalMacFunc.c - -Abstract: - Define MAC function support - for Driver - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-04-29 Eric Create. ---*/ - -#include "HalPrecomp.h" - -#if defined(CONFIG_WLAN_HAL) -void MACFM_software_init(struct rtl8192cd_priv *priv) -{ - unsigned long ability = 0; - //priv->pshare->_dmODM.priv = priv; - -#ifdef CONFIG_WLAN_HAL_8881A - if (GET_CHIP_VER(priv) == VERSION_8881A) { - ability = - 0; - } -#endif //CONFIG_WLAN_HAL_8881A - -#ifdef CONFIG_WLAN_HAL_8192EE - if (GET_CHIP_VER(priv) == VERSION_8192E) { - ability = - 0; - } -#endif //CONFIG_WLAN_HAL_8192EE - -#ifdef CONFIG_WLAN_HAL_8814AE - if (GET_CHIP_VER(priv) == VERSION_8814A) { - ability = -#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC - MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | -#endif - MAC_FUN_HW_TX_SHORTCUT_HDR_CONV | - MAC_FUN_HW_SUPPORT_EACH_VAP_INT | - MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET | - MAC_FUN_HW_HW_FILL_MACID | - MAC_FUN_HW_HW_DETEC_POWER_STATE | - MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE | -#if CFG_HAL_TX_AMSDU - MAC_FUN_HW_SUPPORT_TX_AMSDU | -#endif - 0; - } -#endif //CONFIG_WLAN_HAL_8814AE - -#ifdef CONFIG_WLAN_HAL_8197F - if (GET_CHIP_VER(priv) == VERSION_8197F) { - ability = -#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC - MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | -#endif - MAC_FUN_HW_SUPPORT_EACH_VAP_INT | - MAC_FUN_HW_SUPPORT_H2C_PACKET | - MAC_FUN_HW_SUPPORT_AXI_EXCEPTION | - MAC_FUN_HW_SUPPORT_AP_OFFLOAD | //for BIT_CPWM2 INT - 0; - } - -#endif //CONFIG_WLAN_HAL_8197F - -#ifdef CONFIG_WLAN_HAL_8822BE -if (GET_CHIP_VER(priv) == VERSION_8822B) { - ability = -#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC - MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | -#endif - MAC_FUN_HW_SUPPORT_EACH_VAP_INT | - MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET | - MAC_FUN_HW_HW_FILL_MACID | - MAC_FUN_HW_HW_DETEC_POWER_STATE | - MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE | -#if CFG_HAL_TX_AMSDU - MAC_FUN_HW_SUPPORT_TX_AMSDU | -#endif - //MAC_FUN_HW_SUPPORT_H2C_PACKET | - //MAC_FUN_HW_SUPPORT_AP_OFFLOAD | - 0; -} - -#endif //CONFIG_WLAN_HAL_8822BE - - priv->pshare->hal_SupportMACfunction = ability; -} - - -void MACHAL_version_init( -IN HAL_PADAPTER Adapter -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - - pHalData->MacVersion.is_MAC_v1 = IS_HARDWARE_TYPE_MAC_V1(Adapter); - pHalData->MacVersion.is_MAC_v2 = IS_HARDWARE_TYPE_MAC_V2(Adapter); - pHalData->MacVersion.MACHALSupport = IS_HARDWARE_MACHAL_SUPPORT(Adapter); -} - -#endif // CONFIG_WLAN_HAL - - - + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalMacFunc.c + +Abstract: + Define MAC function support + for Driver + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-04-29 Eric Create. +--*/ + +#include "HalPrecomp.h" + +#if defined(CONFIG_WLAN_HAL) +void MACFM_software_init(struct rtl8192cd_priv *priv) +{ + unsigned long ability = 0; + //priv->pshare->_dmODM.priv = priv; + +#ifdef CONFIG_WLAN_HAL_8881A + if (GET_CHIP_VER(priv) == VERSION_8881A) { + ability = + 0; + } +#endif //CONFIG_WLAN_HAL_8881A + +#ifdef CONFIG_WLAN_HAL_8192EE + if (GET_CHIP_VER(priv) == VERSION_8192E) { + ability = + 0; + } +#endif //CONFIG_WLAN_HAL_8192EE + +#ifdef CONFIG_WLAN_HAL_8814AE + if (GET_CHIP_VER(priv) == VERSION_8814A) { + ability = +#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC + MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | +#endif + MAC_FUN_HW_TX_SHORTCUT_HDR_CONV | + MAC_FUN_HW_SUPPORT_EACH_VAP_INT | + MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET | + MAC_FUN_HW_HW_FILL_MACID | + MAC_FUN_HW_HW_DETEC_POWER_STATE | + MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE | +#if CFG_HAL_TX_AMSDU + MAC_FUN_HW_SUPPORT_TX_AMSDU | +#endif + 0; + } +#endif //CONFIG_WLAN_HAL_8814AE + +#ifdef CONFIG_WLAN_HAL_8197F + if (GET_CHIP_VER(priv) == VERSION_8197F) { + ability = +#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC + MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | +#endif + MAC_FUN_HW_SUPPORT_EACH_VAP_INT | + MAC_FUN_HW_SUPPORT_H2C_PACKET | + MAC_FUN_HW_SUPPORT_AXI_EXCEPTION | + MAC_FUN_HW_SUPPORT_AP_OFFLOAD | //for BIT_CPWM2 INT + 0; + } + +#endif //CONFIG_WLAN_HAL_8197F + +#ifdef CONFIG_WLAN_HAL_8822BE +if (GET_CHIP_VER(priv) == VERSION_8822B) { + ability = +#if CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC + MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC | +#endif + MAC_FUN_HW_SUPPORT_EACH_VAP_INT | + MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET | + MAC_FUN_HW_HW_FILL_MACID | + MAC_FUN_HW_HW_DETEC_POWER_STATE | + MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE | +#if CFG_HAL_TX_AMSDU + MAC_FUN_HW_SUPPORT_TX_AMSDU | +#endif + //MAC_FUN_HW_SUPPORT_H2C_PACKET | + //MAC_FUN_HW_SUPPORT_AP_OFFLOAD | + 0; +} + +#endif //CONFIG_WLAN_HAL_8822BE + + priv->pshare->hal_SupportMACfunction = ability; +} + + +void MACHAL_version_init( +IN HAL_PADAPTER Adapter +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + + pHalData->MacVersion.is_MAC_v1 = IS_HARDWARE_TYPE_MAC_V1(Adapter); + pHalData->MacVersion.is_MAC_v2 = IS_HARDWARE_TYPE_MAC_V2(Adapter); + pHalData->MacVersion.MACHALSupport = IS_HARDWARE_MACHAL_SUPPORT(Adapter); +} + +#endif // CONFIG_WLAN_HAL + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.h b/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.h old mode 100755 new mode 100644 index 7083c8af3a7..d4a33d34fc3 --- a/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.h +++ b/package/kernel/rtl8192cd/WlanHAL/HalMacFunc.h @@ -1,90 +1,90 @@ - -#ifndef __HALMACFUNC_H__ -#define __HALMACFUNC_H__ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - HalMacFunc.h - -Abstract: - Define MAC function support - for Driver - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-04-29 Eric Create. ---*/ - - -void -MACFM_software_init( - struct rtl8192cd_priv *priv -); - -void -MACHAL_version_init( -IN HAL_PADAPTER Adapter -); - -typedef struct _MAC_VERSION_ -{ - unsigned char is_MAC_v1; - unsigned char is_MAC_v2; - unsigned char MACHALSupport; -}MAC_VERSION,*PMAC_VERSION; - -typedef enum _MACFun_Support_Ability_Definition -{ - // - // MAC Func section BIT 0-19 - // - MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC = BIT0, - MAC_FUN_HW_TX_SHORTCUT_HDR_CONV = BIT1, - MAC_FUN_HW_SUPPORT_EACH_VAP_INT = BIT2, - MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET = BIT3, - MAC_FUN_HW_HW_FILL_MACID = BIT4, - MAC_FUN_HW_HW_DETEC_POWER_STATE = BIT5, - MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE = BIT6, - MAC_FUN_HW_SUPPORT_TX_AMSDU = BIT7, - MAC_FUN_HW_SUPPORT_H2C_PACKET = BIT8, - MAC_FUN_HW_SUPPORT_AXI_EXCEPTION = BIT9, - MAC_FUN_HW_SUPPORT_AP_OFFLOAD = BIT10, - -}MACFUN_SUPPORT_ABILITY,*PMACFUN_SUPPORT_ABILITY; - -#define IS_SUPPORT_WLAN_HAL_HW_TX_SHORTCUT_REUSE_TXDESC(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC) - -#define IS_SUPPORT_WLAN_HAL_HW_TX_SHORTCUT_HDR_CONV(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_TX_SHORTCUT_HDR_CONV) - -#define IS_SUPPORT_EACH_VAP_INT(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_EACH_VAP_INT) - -#define IS_SUPPORT_RELEASE_ONE_PACKET(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET) - -#define IS_SUPPORT_HW_FILL_MACID(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_HW_FILL_MACID) - -#define IS_SUPPORT_HW_DETEC_POWER_STATE(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_HW_DETEC_POWER_STATE) - -#define IS_SUPPORT_MULTICAST_BMC_ENHANCE(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE) - -#define IS_SUPPORT_TX_AMSDU(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_TX_AMSDU) - -#define IS_SUPPORT_H2C_PACKET(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_H2C_PACKET) - -#define IS_SUPPORT_AXI_EXCEPTION(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_AXI_EXCEPTION) -#define IS_SUPPORT_AP_OFFLOAD(priv) \ - (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_AP_OFFLOAD) -#endif //__HALMACFUNC_H__ - - + +#ifndef __HALMACFUNC_H__ +#define __HALMACFUNC_H__ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalMacFunc.h + +Abstract: + Define MAC function support + for Driver + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-04-29 Eric Create. +--*/ + + +void +MACFM_software_init( + struct rtl8192cd_priv *priv +); + +void +MACHAL_version_init( +IN HAL_PADAPTER Adapter +); + +typedef struct _MAC_VERSION_ +{ + unsigned char is_MAC_v1; + unsigned char is_MAC_v2; + unsigned char MACHALSupport; +}MAC_VERSION,*PMAC_VERSION; + +typedef enum _MACFun_Support_Ability_Definition +{ + // + // MAC Func section BIT 0-19 + // + MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC = BIT0, + MAC_FUN_HW_TX_SHORTCUT_HDR_CONV = BIT1, + MAC_FUN_HW_SUPPORT_EACH_VAP_INT = BIT2, + MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET = BIT3, + MAC_FUN_HW_HW_FILL_MACID = BIT4, + MAC_FUN_HW_HW_DETEC_POWER_STATE = BIT5, + MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE = BIT6, + MAC_FUN_HW_SUPPORT_TX_AMSDU = BIT7, + MAC_FUN_HW_SUPPORT_H2C_PACKET = BIT8, + MAC_FUN_HW_SUPPORT_AXI_EXCEPTION = BIT9, + MAC_FUN_HW_SUPPORT_AP_OFFLOAD = BIT10, + +}MACFUN_SUPPORT_ABILITY,*PMACFUN_SUPPORT_ABILITY; + +#define IS_SUPPORT_WLAN_HAL_HW_TX_SHORTCUT_REUSE_TXDESC(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_TX_SHORTCUT_REUSE_TXDESC) + +#define IS_SUPPORT_WLAN_HAL_HW_TX_SHORTCUT_HDR_CONV(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_TX_SHORTCUT_HDR_CONV) + +#define IS_SUPPORT_EACH_VAP_INT(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_EACH_VAP_INT) + +#define IS_SUPPORT_RELEASE_ONE_PACKET(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_RELEASE_ONE_PACKET) + +#define IS_SUPPORT_HW_FILL_MACID(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_HW_FILL_MACID) + +#define IS_SUPPORT_HW_DETEC_POWER_STATE(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_HW_DETEC_POWER_STATE) + +#define IS_SUPPORT_MULTICAST_BMC_ENHANCE(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_MULTICAST_BMC_ENHANCE) + +#define IS_SUPPORT_TX_AMSDU(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_TX_AMSDU) + +#define IS_SUPPORT_H2C_PACKET(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_H2C_PACKET) + +#define IS_SUPPORT_AXI_EXCEPTION(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_AXI_EXCEPTION) +#define IS_SUPPORT_AP_OFFLOAD(priv) \ + (priv->pshare->hal_SupportMACfunction & MAC_FUN_HW_SUPPORT_AP_OFFLOAD) +#endif //__HALMACFUNC_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/HalPrecomp.h b/package/kernel/rtl8192cd/WlanHAL/HalPrecomp.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/HalPrecompInc.h b/package/kernel/rtl8192cd/WlanHAL/HalPrecompInc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Include/GeneralDef.h b/package/kernel/rtl8192cd/WlanHAL/Include/GeneralDef.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Include/PlatformDef.h b/package/kernel/rtl8192cd/WlanHAL/Include/PlatformDef.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Include/StatusCode.h b/package/kernel/rtl8192cd/WlanHAL/Include/StatusCode.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/Output/HalLib.h b/package/kernel/rtl8192cd/WlanHAL/Output/HalLib.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXCfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.c index 591a934a2b2..91e10bf9709 100644 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.c @@ -1,711 +1,711 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXDM.c - -Abstract: - Defined RTL88XX HAL common Function - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-08-19 Filen Create. ---*/ - -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../HalPrecomp.h" -#endif - -#if CFG_HAL_MACDM - -typedef enum _MACDM_STATE_CHANGE_{ - MACDM_STATE_CHANGE_NO = 0, - MACDM_STATE_CHANGE_UP, - MACDM_STATE_CHANGE_DOWN -} MACDM_STATE_CHANGE, *PMACDM_STATE_CHANGE; - - -#define MAX_MSDU_LEN_802_11 1536 -#define MAX_AMSDU_LEN_802_11 8192 -u4Byte -CalMaxAggreNum( - IN u4Byte page_size, - IN u4Byte min_pageNum, //the minimum pageNum of "dedicated queue + pub queue" - IN BOOLEAN AMSDU_En, - IN u4Byte txdesc_len -) -{ - u4Byte MaxPktSize; - BOOLEAN bWithRemainder; - u4Byte PageNumOnePkt; - u4Byte UpperboundPktNum = 0; - - if (AMSDU_En) { - MaxPktSize = MAX_AMSDU_LEN_802_11; - } - else { - MaxPktSize = MAX_MSDU_LEN_802_11; - } - - bWithRemainder = ((MaxPktSize+txdesc_len) % page_size) ? _TRUE: _FALSE; - PageNumOnePkt = (MaxPktSize+txdesc_len) / page_size; - if (bWithRemainder) { - PageNumOnePkt++; - } - - UpperboundPktNum = min_pageNum / PageNumOnePkt; - - return UpperboundPktNum>>1; -} - -#define MAX_VALUE_REG_AGGRE_NUM 63 -VOID -DecisionAggrePara( - IN HAL_PADAPTER Adapter, - IN u4Byte aggre_state, - IN u4Byte TxopMaxAggreNum -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - BOOLEAN bEnableTXOP = _TRUE; - u4Byte AggreNum = MAX_VALUE_REG_AGGRE_NUM; - - pHalData->MACDM_Aggre_state = aggre_state; - - switch(aggre_state) { - case MACDM_AGGRE_STATE_NONE: - bEnableTXOP = _FALSE; - break; - - case MACDM_AGGRE_STATE_TXOP: - bEnableTXOP = _TRUE; - - //exception catch - if (TxopMaxAggreNum > MAX_VALUE_REG_AGGRE_NUM) { - TxopMaxAggreNum = MAX_VALUE_REG_AGGRE_NUM; - } - - AggreNum = TxopMaxAggreNum; - break; - - case MACDM_AGGRE_STATE_TXOP_EARLY: - // TODO: check with Pisa, three mode - bEnableTXOP = _TRUE; - - //exception catch - if (TxopMaxAggreNum > MAX_VALUE_REG_AGGRE_NUM) { - TxopMaxAggreNum = MAX_VALUE_REG_AGGRE_NUM; - } - - AggreNum = TxopMaxAggreNum; - break; - - default: - RT_TRACE(COMP_INIT, DBG_WARNING, ("AGGRE_STATE Error\n")); - break; - } - - //Fill HW register - HAL_RTL_W16(REG_PROT_MODE_CTRL+2, AggreNum | (AggreNum<<8)); - - if (_TRUE==bEnableTXOP) { - HAL_RTL_W8(REG_EDCA_BE_PARAM+2, 0x5E); - } - else { - HAL_RTL_W8(REG_EDCA_BE_PARAM+2, 0x0); - } -} - - -static -RSSI_LVL_DM_88XX -TranslateRSSI88XX( - u4Byte rssi_lvl_odm -) -{ - u4Byte rssi = RSSI_LVL_NORMAL; - - switch(rssi_lvl_odm) { - case 1: - //high quality - rssi = RSSI_LVL_HIGH; - break; - case 2: - //normal quality - rssi = RSSI_LVL_NORMAL; - break; - case 3: - //low quality - rssi = RSSI_LVL_LOW; - break; - default: - break; - } - - return rssi; -} - - -static -BOOLEAN -LoadMACDMTable( - IN HAL_PADAPTER Adapter, - IN u4Byte MACDM_State, - IN u4Byte rssi_lvl -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - u4Byte offset, value, tbl_idx = 0, round = 0; - - while(1) { - - offset = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].offset; - value = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].value; - - if (offset == 0xFFFF) { - break; - } - - HAL_RTL_W32(offset, value); - tbl_idx++; - - if (++round > 10000) { - panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); - break; - } - } - - return _TRUE; -} - - -VOID -InitMACDM88XX( - IN HAL_PADAPTER Adapter -) -{ - //PHAL_INTERFACE pHalFunc = GET_HAL_INTERFACE(Adapter); - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - pu1Byte pRegFileStart; - u4Byte RegFileLen; - u4Byte stateThrs[MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1]; //1: EOF - u4Byte thrs_idx,rssi_idx; - - - pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT; - - // TODO: should load from mib - pHalData->MACDM_Mode_Sel = MACDM_MODE_MAX_TP; - - pHalData->MACDM_preRssiLvl = RSSI_LVL_LOW; - - //Load Raise/Fall state criteria from the para.c (translation from txt file) - HAL_memset(stateThrs, 0, sizeof(stateThrs)); - HAL_memset(pHalData->MACDM_stateThrs, 0, sizeof(pHalData->MACDM_stateThrs)); - - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_SIZE, (pu1Byte)&RegFileLen); - LoadFileToOneParaTable(pRegFileStart, - RegFileLen, - (pu1Byte)stateThrs, - (MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1)); - - //one-way arrary translate to two-way arrary - for(thrs_idx=0; thrs_idxMACDM_stateThrs[thrs_idx][rssi_idx] = stateThrs[thrs_idx*RSSI_LVL_MAX_NUM + rssi_idx]; - } - } - -#if 0 //Filen: for verification - RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) ); - RT_TRACE(COMP_INIT, DBG_LOUD, ("0: value(0x%x)\n", pHalData->MACDM_stateThrs[0])); - RT_TRACE(COMP_INIT, DBG_LOUD, ("1: value(0x%x)\n", pHalData->MACDM_stateThrs[1])); - RT_TRACE(COMP_INIT, DBG_LOUD, ("2: value(0x%x)\n", pHalData->MACDM_stateThrs[2])); - RT_TRACE(COMP_INIT, DBG_LOUD, ("3: value(0x%x)\n", pHalData->MACDM_stateThrs[3])); - RT_TRACE(COMP_INIT, DBG_LOUD, ("4: value(0x%x)\n", pHalData->MACDM_stateThrs[4])); -#endif - - //Load Table parameter from the para.c (translation from txt file) - HAL_memset(pHalData->MACDM_Table, 0, sizeof(pHalData->MACDM_Table)); - - //(default, low) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW], - MAX_MACDM_REG_NUM); - - //(default, normal) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_NORMAL], - MAX_MACDM_REG_NUM); - - //(default, high) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_HIGH], - MAX_MACDM_REG_NUM); - - //(general, low) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_LOW], - MAX_MACDM_REG_NUM); - - //(general, normal) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_NORMAL], - MAX_MACDM_REG_NUM); - - //(general, high) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_HIGH], - MAX_MACDM_REG_NUM); - - //(txop, low) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_LOW], - MAX_MACDM_REG_NUM); - - //(txop, normal) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_NORMAL], - MAX_MACDM_REG_NUM); - - //(txop, high) - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_START, (pu1Byte)&pRegFileStart); - GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_SIZE, (pu1Byte)&RegFileLen); - LoadFileToIORegTable(pRegFileStart, - RegFileLen, - (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_HIGH], - MAX_MACDM_REG_NUM); - - - #if 0 //Filen: for verification - RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) ); - RT_TRACE(COMP_INIT, DBG_LOUD, ("0: offset(0x%x), value(0x%x)\n", - pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].offset, - pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].value) - ); - - RT_TRACE(COMP_INIT, DBG_LOUD, ("1: offset(0x%x), value(0x%x)\n", - pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].offset, - pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].value) - ); - #endif - - //Load MACDM table by initial value - LoadMACDMTable(Adapter, pHalData->MACDM_State, pHalData->MACDM_preRssiLvl); -} - - -static -MACDM_STATE_CHANGE -CheckMACDMThrs( - IN HAL_PADAPTER Adapter, - IN u4Byte MACDM_State, - IN u4Byte TP, - IN u4Byte rssi_lvl -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - - switch(MACDM_State) { - case MACDM_TP_STATE_DEFAULT: - if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_DEF_TO_GEN][rssi_lvl]) { - return MACDM_STATE_CHANGE_UP; - } - break; - case MACDM_TP_STATE_GENERAL: - if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_DEF][rssi_lvl]) { - return MACDM_STATE_CHANGE_DOWN; - } - else if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_TXOP][rssi_lvl]) { - return MACDM_STATE_CHANGE_UP; - } - break; - case MACDM_TP_STATE_TXOP: - if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_TXOP_TO_GEN][rssi_lvl]) { - return MACDM_STATE_CHANGE_DOWN; - } - break; - default: - break; - } - - return MACDM_STATE_CHANGE_NO; -} - - -static -BOOLEAN -MACDM_Core88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte TP, // Mbps - IN u4Byte rssi_lvl_odm, - IN u4Byte CurTxRate, //Data Rate Index - IN WIRELESS_MODE WirelessMode -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - u4Byte rssi_lvl = TranslateRSSI88XX(rssi_lvl_odm); - BOOLEAN StateChange = _FALSE; - MACDM_STATE_CHANGE stateChange; - u4Byte RequestAggreState; - - stateChange = CheckMACDMThrs(Adapter, pHalData->MACDM_State, TP, rssi_lvl); - - //3 Stage 1: check TP & RSSI - switch(pHalData->MACDM_State) { - case MACDM_TP_STATE_DEFAULT: - if (MACDM_STATE_CHANGE_UP == stateChange) { - pHalData->MACDM_State = MACDM_TP_STATE_GENERAL; - LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); - RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", - MACDM_TP_STATE_DEFAULT, - pHalData->MACDM_State)); - StateChange = _TRUE; - } - else if (MACDM_STATE_CHANGE_NO == stateChange) { - if (pHalData->MACDM_preRssiLvl != rssi_lvl) { - LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl); - } - } - else { - //Error, impossible - } - break; - - case MACDM_TP_STATE_GENERAL: - - if (MACDM_STATE_CHANGE_UP == stateChange) { - pHalData->MACDM_State = MACDM_TP_STATE_TXOP; - LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl); - RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", - MACDM_TP_STATE_GENERAL, - pHalData->MACDM_State)); - - // TODO: TXOP_SPEED mode by loading file - // TODO: now 92E support only -#if IS_EXIST_RTL8192EE - if ( IS_HARDWARE_TYPE_8192EE(Adapter) ) { - if ((TP >= 155) && - (CurTxRate == _MCS15_RATE_) && - (rssi_lvl == RSSI_LVL_HIGH) - ) { - HAL_RTL_W32(REG_FAST_EDCA_CTRL, 0x0308DDDD); - } - } -#endif // IS_EXIST_RTL8192EE - StateChange = _TRUE; - } - else if (MACDM_STATE_CHANGE_DOWN == stateChange) { - pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT; - LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl); - RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", - MACDM_TP_STATE_GENERAL, - pHalData->MACDM_State)); - StateChange = _TRUE; - } - else { - //MACDM_STATE_CHANGE_NO - if (pHalData->MACDM_preRssiLvl != rssi_lvl) { - LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); - } - } - break; - - case MACDM_TP_STATE_TXOP: - if (MACDM_STATE_CHANGE_DOWN == stateChange) { - pHalData->MACDM_State = MACDM_TP_STATE_GENERAL; - LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); - RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", - MACDM_TP_STATE_TXOP, - pHalData->MACDM_State)); - StateChange = _TRUE; - } - else if (MACDM_STATE_CHANGE_NO == stateChange) { - if (pHalData->MACDM_preRssiLvl != rssi_lvl) { - LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl); - } - - // TODO: TXOP_SPEED mode by loading file - // TODO: now 92E support only -#if IS_EXIST_RTL8192EE - if ( IS_HARDWARE_TYPE_8192EE(Adapter) ) { - if ((TP >= 155) && - (CurTxRate == _MCS15_RATE_) && - (rssi_lvl == RSSI_LVL_HIGH) - ) { - HAL_RTL_W32(REG_FAST_EDCA_CTRL, 0x0308DDDD); - } - } -#endif // IS_EXIST_RTL8192EE - - } - else { - //Error, impossible - } - - break; - - default: - //impossible - break; - }; - - //3 Stage 2: check air collision - // TODO: 3SS - switch(WirelessMode) { - case WIRELESS_MODE_A: - case WIRELESS_MODE_G: - if (CurTxRate <= _12M_RATE_) { - - // low rate - if (RSSI_LVL_HIGH!=rssi_lvl) { - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - else { - // Disable TXOP - RequestAggreState = MACDM_AGGRE_STATE_NONE; - } - } - else { - // high rate - //OFDM 18 / 24 / 36 / 48 /54 - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - - break; - - case WIRELESS_MODE_N_24G: - case WIRELESS_MODE_N_5G: - if ((CurTxRate <= _MCS11_RATE_ && - CurTxRate >= _MCS8_RATE_ - ) || - (CurTxRate <= _MCS3_RATE_ && - CurTxRate >= _MCS0_RATE_ - ) || - (CurTxRate <= _54M_RATE_) - ) { - // low rate - if (RSSI_LVL_HIGH!=rssi_lvl) { - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - else { - // Disable TXOP - RequestAggreState = MACDM_AGGRE_STATE_NONE; - } - } - else { - //high rate - //MCS 4~7, 12~15 - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - break; - - case WIRELESS_MODE_AC_5G: - // TODO: - if ((CurTxRate <= _NSS3_MCS9_RATE_ && - CurTxRate >= _NSS3_MCS6_RATE_ - ) || - (CurTxRate <= _NSS2_MCS9_RATE_ && - CurTxRate >= _NSS2_MCS6_RATE_ - ) || - (CurTxRate <= _NSS1_MCS9_RATE_ && - CurTxRate >= _NSS1_MCS6_RATE_ - ) - ) { - // high rate - // Enable TXOP - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - else { - // low rate - if (RSSI_LVL_HIGH!=rssi_lvl) { - RequestAggreState = MACDM_AGGRE_STATE_TXOP; - } - else { - // Disable TXOP - RequestAggreState = MACDM_AGGRE_STATE_NONE; - } - } - break; - - case WIRELESS_MODE_B: - default: - RequestAggreState = MACDM_AGGRE_STATE_NONE; - break; - } - - if (RequestAggreState!=pHalData->MACDM_Aggre_state) { - DecisionAggrePara(Adapter, RequestAggreState, 0); - } - else { - // DoNothing - } - - //Record last one RSSI Level - pHalData->MACDM_preRssiLvl = rssi_lvl; - - return StateChange; -} - - -VOID -Timer1SecDM88XX( - IN HAL_PADAPTER Adapter -) -{ - HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); - u4Byte idx = 0; - HAL_PSTAINFO pEntry = findNextSTA(Adapter, &idx); - - //RT_TRACE_F(COMP_DBG, DBG_LOUD, ("mode(%d)\n", pHalData->MACDM_Mode_Sel)); - - switch(pHalData->MACDM_Mode_Sel) { - case MACDM_MODE_MAX_TP: - { - u4Byte tmpTotal_tp = 0; - u4Byte highest_tp = 0; - HAL_PSTAINFO pstat_highest = NULL; - - while(pEntry) { - if(pEntry && pEntry->expire_to) { - tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb - - if (tmpTotal_tp > highest_tp) { - highest_tp = tmpTotal_tp; - pstat_highest = pEntry; - } - } - - pEntry = findNextSTA(Adapter, &idx); - }; - - // TODO: current_tx_rate is not correct, we should get this value from FW - // TODO: transform current_tx_rate format - if (pstat_highest) { - MACDM_Core88XX(Adapter, - highest_tp, - pstat_highest->rssi_level, - pstat_highest->current_tx_rate, - pstat_highest->WirelessMode - ); - } - } - break; - - case MACDM_MODE_AVERAGE: - { - u4Byte tmpTotal_tp = 0, Total_tp = 0, average_tp = 0; - u4Byte LinkedStaNum = 0; - u4Byte Total_rssi = 0, average_rssi = 0; - u4Byte Min_CurTxRate = 0xFFFFFFFF; - HAL_PSTAINFO pstat_Average = NULL; - - while(pEntry) { - - if(pEntry && pEntry->expire_to) { - - LinkedStaNum++; - - //accumulate throughput - tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17;//unit: bytes -> Mb - Total_tp += tmpTotal_tp; - - //accumulate RSSI - Total_rssi += pEntry->rssi_level; - - //find lowest rate of all linked sta - if (pEntry->current_tx_rate < Min_CurTxRate) { - Min_CurTxRate = pEntry->current_tx_rate; - pstat_Average = pEntry; - } - } - - pEntry = findNextSTA(Adapter, &idx); - }; - - if (LinkedStaNum != 0) { - average_tp = Total_tp / LinkedStaNum; - average_rssi = Total_rssi / LinkedStaNum; - - // TODO: current_tx_rate is not correct, we should get this value from FW - // TODO: transform current_tx_rate format - MACDM_Core88XX(Adapter, - average_tp, - average_rssi, - Min_CurTxRate, - pstat_Average->WirelessMode - ); - } - } - break; - - case MACDM_MODE_MIN_TP: - { - u4Byte tmpTotal_tp = 0; - u4Byte lowest_tp = 0xffffffff; - HAL_PSTAINFO pstat_lowest = NULL; - - while(pEntry) { - if(pEntry && pEntry->expire_to) { - tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb - - //find lowest sta - if (tmpTotal_tp < lowest_tp) { - lowest_tp = tmpTotal_tp; - pstat_lowest = pEntry; - } - } - - pEntry = findNextSTA(Adapter, &idx); - }; - - // TODO: current_tx_rate is not correct, we should get this value from FW - // TODO: transform current_tx_rate format - if (pstat_lowest) { - MACDM_Core88XX(Adapter, - lowest_tp, - pstat_lowest->rssi_level, - pstat_lowest->current_tx_rate, - pstat_lowest->WirelessMode - ); - } - } - break; - - case MACDM_MODE_STOP: - default: - break; - } - -} - -#endif //#if CFG_HAL_MACDM - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXDM.c + +Abstract: + Defined RTL88XX HAL common Function + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-08-19 Filen Create. +--*/ + +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../HalPrecomp.h" +#endif + +#if CFG_HAL_MACDM + +typedef enum _MACDM_STATE_CHANGE_{ + MACDM_STATE_CHANGE_NO = 0, + MACDM_STATE_CHANGE_UP, + MACDM_STATE_CHANGE_DOWN +} MACDM_STATE_CHANGE, *PMACDM_STATE_CHANGE; + + +#define MAX_MSDU_LEN_802_11 1536 +#define MAX_AMSDU_LEN_802_11 8192 +u4Byte +CalMaxAggreNum( + IN u4Byte page_size, + IN u4Byte min_pageNum, //the minimum pageNum of "dedicated queue + pub queue" + IN BOOLEAN AMSDU_En, + IN u4Byte txdesc_len +) +{ + u4Byte MaxPktSize; + BOOLEAN bWithRemainder; + u4Byte PageNumOnePkt; + u4Byte UpperboundPktNum = 0; + + if (AMSDU_En) { + MaxPktSize = MAX_AMSDU_LEN_802_11; + } + else { + MaxPktSize = MAX_MSDU_LEN_802_11; + } + + bWithRemainder = ((MaxPktSize+txdesc_len) % page_size) ? _TRUE: _FALSE; + PageNumOnePkt = (MaxPktSize+txdesc_len) / page_size; + if (bWithRemainder) { + PageNumOnePkt++; + } + + UpperboundPktNum = min_pageNum / PageNumOnePkt; + + return UpperboundPktNum>>1; +} + +#define MAX_VALUE_REG_AGGRE_NUM 63 +VOID +DecisionAggrePara( + IN HAL_PADAPTER Adapter, + IN u4Byte aggre_state, + IN u4Byte TxopMaxAggreNum +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + BOOLEAN bEnableTXOP = _TRUE; + u4Byte AggreNum = MAX_VALUE_REG_AGGRE_NUM; + + pHalData->MACDM_Aggre_state = aggre_state; + + switch(aggre_state) { + case MACDM_AGGRE_STATE_NONE: + bEnableTXOP = _FALSE; + break; + + case MACDM_AGGRE_STATE_TXOP: + bEnableTXOP = _TRUE; + + //exception catch + if (TxopMaxAggreNum > MAX_VALUE_REG_AGGRE_NUM) { + TxopMaxAggreNum = MAX_VALUE_REG_AGGRE_NUM; + } + + AggreNum = TxopMaxAggreNum; + break; + + case MACDM_AGGRE_STATE_TXOP_EARLY: + // TODO: check with Pisa, three mode + bEnableTXOP = _TRUE; + + //exception catch + if (TxopMaxAggreNum > MAX_VALUE_REG_AGGRE_NUM) { + TxopMaxAggreNum = MAX_VALUE_REG_AGGRE_NUM; + } + + AggreNum = TxopMaxAggreNum; + break; + + default: + RT_TRACE(COMP_INIT, DBG_WARNING, ("AGGRE_STATE Error\n")); + break; + } + + //Fill HW register + HAL_RTL_W16(REG_PROT_MODE_CTRL+2, AggreNum | (AggreNum<<8)); + + if (_TRUE==bEnableTXOP) { + HAL_RTL_W8(REG_EDCA_BE_PARAM+2, 0x5E); + } + else { + HAL_RTL_W8(REG_EDCA_BE_PARAM+2, 0x0); + } +} + + +static +RSSI_LVL_DM_88XX +TranslateRSSI88XX( + u4Byte rssi_lvl_odm +) +{ + u4Byte rssi = RSSI_LVL_NORMAL; + + switch(rssi_lvl_odm) { + case 1: + //high quality + rssi = RSSI_LVL_HIGH; + break; + case 2: + //normal quality + rssi = RSSI_LVL_NORMAL; + break; + case 3: + //low quality + rssi = RSSI_LVL_LOW; + break; + default: + break; + } + + return rssi; +} + + +static +BOOLEAN +LoadMACDMTable( + IN HAL_PADAPTER Adapter, + IN u4Byte MACDM_State, + IN u4Byte rssi_lvl +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + u4Byte offset, value, tbl_idx = 0, round = 0; + + while(1) { + + offset = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].offset; + value = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].value; + + if (offset == 0xFFFF) { + break; + } + + HAL_RTL_W32(offset, value); + tbl_idx++; + + if (++round > 10000) { + panic_printk("%s[%d] while (1) goes too many\n", __FUNCTION__, __LINE__); + break; + } + } + + return _TRUE; +} + + +VOID +InitMACDM88XX( + IN HAL_PADAPTER Adapter +) +{ + //PHAL_INTERFACE pHalFunc = GET_HAL_INTERFACE(Adapter); + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + pu1Byte pRegFileStart; + u4Byte RegFileLen; + u4Byte stateThrs[MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1]; //1: EOF + u4Byte thrs_idx,rssi_idx; + + + pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT; + + // TODO: should load from mib + pHalData->MACDM_Mode_Sel = MACDM_MODE_MAX_TP; + + pHalData->MACDM_preRssiLvl = RSSI_LVL_LOW; + + //Load Raise/Fall state criteria from the para.c (translation from txt file) + HAL_memset(stateThrs, 0, sizeof(stateThrs)); + HAL_memset(pHalData->MACDM_stateThrs, 0, sizeof(pHalData->MACDM_stateThrs)); + + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_SIZE, (pu1Byte)&RegFileLen); + LoadFileToOneParaTable(pRegFileStart, + RegFileLen, + (pu1Byte)stateThrs, + (MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1)); + + //one-way arrary translate to two-way arrary + for(thrs_idx=0; thrs_idxMACDM_stateThrs[thrs_idx][rssi_idx] = stateThrs[thrs_idx*RSSI_LVL_MAX_NUM + rssi_idx]; + } + } + +#if 0 //Filen: for verification + RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) ); + RT_TRACE(COMP_INIT, DBG_LOUD, ("0: value(0x%x)\n", pHalData->MACDM_stateThrs[0])); + RT_TRACE(COMP_INIT, DBG_LOUD, ("1: value(0x%x)\n", pHalData->MACDM_stateThrs[1])); + RT_TRACE(COMP_INIT, DBG_LOUD, ("2: value(0x%x)\n", pHalData->MACDM_stateThrs[2])); + RT_TRACE(COMP_INIT, DBG_LOUD, ("3: value(0x%x)\n", pHalData->MACDM_stateThrs[3])); + RT_TRACE(COMP_INIT, DBG_LOUD, ("4: value(0x%x)\n", pHalData->MACDM_stateThrs[4])); +#endif + + //Load Table parameter from the para.c (translation from txt file) + HAL_memset(pHalData->MACDM_Table, 0, sizeof(pHalData->MACDM_Table)); + + //(default, low) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW], + MAX_MACDM_REG_NUM); + + //(default, normal) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_NORMAL], + MAX_MACDM_REG_NUM); + + //(default, high) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_HIGH], + MAX_MACDM_REG_NUM); + + //(general, low) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_LOW], + MAX_MACDM_REG_NUM); + + //(general, normal) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_NORMAL], + MAX_MACDM_REG_NUM); + + //(general, high) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_HIGH], + MAX_MACDM_REG_NUM); + + //(txop, low) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_LOW], + MAX_MACDM_REG_NUM); + + //(txop, normal) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_NORMAL], + MAX_MACDM_REG_NUM); + + //(txop, high) + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_START, (pu1Byte)&pRegFileStart); + GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_SIZE, (pu1Byte)&RegFileLen); + LoadFileToIORegTable(pRegFileStart, + RegFileLen, + (pu1Byte)pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_HIGH], + MAX_MACDM_REG_NUM); + + + #if 0 //Filen: for verification + RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) ); + RT_TRACE(COMP_INIT, DBG_LOUD, ("0: offset(0x%x), value(0x%x)\n", + pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].offset, + pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].value) + ); + + RT_TRACE(COMP_INIT, DBG_LOUD, ("1: offset(0x%x), value(0x%x)\n", + pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].offset, + pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].value) + ); + #endif + + //Load MACDM table by initial value + LoadMACDMTable(Adapter, pHalData->MACDM_State, pHalData->MACDM_preRssiLvl); +} + + +static +MACDM_STATE_CHANGE +CheckMACDMThrs( + IN HAL_PADAPTER Adapter, + IN u4Byte MACDM_State, + IN u4Byte TP, + IN u4Byte rssi_lvl +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + + switch(MACDM_State) { + case MACDM_TP_STATE_DEFAULT: + if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_DEF_TO_GEN][rssi_lvl]) { + return MACDM_STATE_CHANGE_UP; + } + break; + case MACDM_TP_STATE_GENERAL: + if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_DEF][rssi_lvl]) { + return MACDM_STATE_CHANGE_DOWN; + } + else if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_TXOP][rssi_lvl]) { + return MACDM_STATE_CHANGE_UP; + } + break; + case MACDM_TP_STATE_TXOP: + if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_TXOP_TO_GEN][rssi_lvl]) { + return MACDM_STATE_CHANGE_DOWN; + } + break; + default: + break; + } + + return MACDM_STATE_CHANGE_NO; +} + + +static +BOOLEAN +MACDM_Core88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte TP, // Mbps + IN u4Byte rssi_lvl_odm, + IN u4Byte CurTxRate, //Data Rate Index + IN WIRELESS_MODE WirelessMode +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + u4Byte rssi_lvl = TranslateRSSI88XX(rssi_lvl_odm); + BOOLEAN StateChange = _FALSE; + MACDM_STATE_CHANGE stateChange; + u4Byte RequestAggreState; + + stateChange = CheckMACDMThrs(Adapter, pHalData->MACDM_State, TP, rssi_lvl); + + //3 Stage 1: check TP & RSSI + switch(pHalData->MACDM_State) { + case MACDM_TP_STATE_DEFAULT: + if (MACDM_STATE_CHANGE_UP == stateChange) { + pHalData->MACDM_State = MACDM_TP_STATE_GENERAL; + LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); + RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", + MACDM_TP_STATE_DEFAULT, + pHalData->MACDM_State)); + StateChange = _TRUE; + } + else if (MACDM_STATE_CHANGE_NO == stateChange) { + if (pHalData->MACDM_preRssiLvl != rssi_lvl) { + LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl); + } + } + else { + //Error, impossible + } + break; + + case MACDM_TP_STATE_GENERAL: + + if (MACDM_STATE_CHANGE_UP == stateChange) { + pHalData->MACDM_State = MACDM_TP_STATE_TXOP; + LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl); + RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", + MACDM_TP_STATE_GENERAL, + pHalData->MACDM_State)); + + // TODO: TXOP_SPEED mode by loading file + // TODO: now 92E support only +#if IS_EXIST_RTL8192EE + if ( IS_HARDWARE_TYPE_8192EE(Adapter) ) { + if ((TP >= 155) && + (CurTxRate == _MCS15_RATE_) && + (rssi_lvl == RSSI_LVL_HIGH) + ) { + HAL_RTL_W32(REG_FAST_EDCA_CTRL, 0x0308DDDD); + } + } +#endif // IS_EXIST_RTL8192EE + StateChange = _TRUE; + } + else if (MACDM_STATE_CHANGE_DOWN == stateChange) { + pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT; + LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl); + RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", + MACDM_TP_STATE_GENERAL, + pHalData->MACDM_State)); + StateChange = _TRUE; + } + else { + //MACDM_STATE_CHANGE_NO + if (pHalData->MACDM_preRssiLvl != rssi_lvl) { + LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); + } + } + break; + + case MACDM_TP_STATE_TXOP: + if (MACDM_STATE_CHANGE_DOWN == stateChange) { + pHalData->MACDM_State = MACDM_TP_STATE_GENERAL; + LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl); + RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n", + MACDM_TP_STATE_TXOP, + pHalData->MACDM_State)); + StateChange = _TRUE; + } + else if (MACDM_STATE_CHANGE_NO == stateChange) { + if (pHalData->MACDM_preRssiLvl != rssi_lvl) { + LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl); + } + + // TODO: TXOP_SPEED mode by loading file + // TODO: now 92E support only +#if IS_EXIST_RTL8192EE + if ( IS_HARDWARE_TYPE_8192EE(Adapter) ) { + if ((TP >= 155) && + (CurTxRate == _MCS15_RATE_) && + (rssi_lvl == RSSI_LVL_HIGH) + ) { + HAL_RTL_W32(REG_FAST_EDCA_CTRL, 0x0308DDDD); + } + } +#endif // IS_EXIST_RTL8192EE + + } + else { + //Error, impossible + } + + break; + + default: + //impossible + break; + }; + + //3 Stage 2: check air collision + // TODO: 3SS + switch(WirelessMode) { + case WIRELESS_MODE_A: + case WIRELESS_MODE_G: + if (CurTxRate <= _12M_RATE_) { + + // low rate + if (RSSI_LVL_HIGH!=rssi_lvl) { + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + else { + // Disable TXOP + RequestAggreState = MACDM_AGGRE_STATE_NONE; + } + } + else { + // high rate + //OFDM 18 / 24 / 36 / 48 /54 + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + + break; + + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: + if ((CurTxRate <= _MCS11_RATE_ && + CurTxRate >= _MCS8_RATE_ + ) || + (CurTxRate <= _MCS3_RATE_ && + CurTxRate >= _MCS0_RATE_ + ) || + (CurTxRate <= _54M_RATE_) + ) { + // low rate + if (RSSI_LVL_HIGH!=rssi_lvl) { + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + else { + // Disable TXOP + RequestAggreState = MACDM_AGGRE_STATE_NONE; + } + } + else { + //high rate + //MCS 4~7, 12~15 + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + break; + + case WIRELESS_MODE_AC_5G: + // TODO: + if ((CurTxRate <= _NSS3_MCS9_RATE_ && + CurTxRate >= _NSS3_MCS6_RATE_ + ) || + (CurTxRate <= _NSS2_MCS9_RATE_ && + CurTxRate >= _NSS2_MCS6_RATE_ + ) || + (CurTxRate <= _NSS1_MCS9_RATE_ && + CurTxRate >= _NSS1_MCS6_RATE_ + ) + ) { + // high rate + // Enable TXOP + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + else { + // low rate + if (RSSI_LVL_HIGH!=rssi_lvl) { + RequestAggreState = MACDM_AGGRE_STATE_TXOP; + } + else { + // Disable TXOP + RequestAggreState = MACDM_AGGRE_STATE_NONE; + } + } + break; + + case WIRELESS_MODE_B: + default: + RequestAggreState = MACDM_AGGRE_STATE_NONE; + break; + } + + if (RequestAggreState!=pHalData->MACDM_Aggre_state) { + DecisionAggrePara(Adapter, RequestAggreState, 0); + } + else { + // DoNothing + } + + //Record last one RSSI Level + pHalData->MACDM_preRssiLvl = rssi_lvl; + + return StateChange; +} + + +VOID +Timer1SecDM88XX( + IN HAL_PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); + u4Byte idx = 0; + HAL_PSTAINFO pEntry = findNextSTA(Adapter, &idx); + + //RT_TRACE_F(COMP_DBG, DBG_LOUD, ("mode(%d)\n", pHalData->MACDM_Mode_Sel)); + + switch(pHalData->MACDM_Mode_Sel) { + case MACDM_MODE_MAX_TP: + { + u4Byte tmpTotal_tp = 0; + u4Byte highest_tp = 0; + HAL_PSTAINFO pstat_highest = NULL; + + while(pEntry) { + if(pEntry && pEntry->expire_to) { + tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb + + if (tmpTotal_tp > highest_tp) { + highest_tp = tmpTotal_tp; + pstat_highest = pEntry; + } + } + + pEntry = findNextSTA(Adapter, &idx); + }; + + // TODO: current_tx_rate is not correct, we should get this value from FW + // TODO: transform current_tx_rate format + if (pstat_highest) { + MACDM_Core88XX(Adapter, + highest_tp, + pstat_highest->rssi_level, + pstat_highest->current_tx_rate, + pstat_highest->WirelessMode + ); + } + } + break; + + case MACDM_MODE_AVERAGE: + { + u4Byte tmpTotal_tp = 0, Total_tp = 0, average_tp = 0; + u4Byte LinkedStaNum = 0; + u4Byte Total_rssi = 0, average_rssi = 0; + u4Byte Min_CurTxRate = 0xFFFFFFFF; + HAL_PSTAINFO pstat_Average = NULL; + + while(pEntry) { + + if(pEntry && pEntry->expire_to) { + + LinkedStaNum++; + + //accumulate throughput + tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17;//unit: bytes -> Mb + Total_tp += tmpTotal_tp; + + //accumulate RSSI + Total_rssi += pEntry->rssi_level; + + //find lowest rate of all linked sta + if (pEntry->current_tx_rate < Min_CurTxRate) { + Min_CurTxRate = pEntry->current_tx_rate; + pstat_Average = pEntry; + } + } + + pEntry = findNextSTA(Adapter, &idx); + }; + + if (LinkedStaNum != 0) { + average_tp = Total_tp / LinkedStaNum; + average_rssi = Total_rssi / LinkedStaNum; + + // TODO: current_tx_rate is not correct, we should get this value from FW + // TODO: transform current_tx_rate format + MACDM_Core88XX(Adapter, + average_tp, + average_rssi, + Min_CurTxRate, + pstat_Average->WirelessMode + ); + } + } + break; + + case MACDM_MODE_MIN_TP: + { + u4Byte tmpTotal_tp = 0; + u4Byte lowest_tp = 0xffffffff; + HAL_PSTAINFO pstat_lowest = NULL; + + while(pEntry) { + if(pEntry && pEntry->expire_to) { + tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb + + //find lowest sta + if (tmpTotal_tp < lowest_tp) { + lowest_tp = tmpTotal_tp; + pstat_lowest = pEntry; + } + } + + pEntry = findNextSTA(Adapter, &idx); + }; + + // TODO: current_tx_rate is not correct, we should get this value from FW + // TODO: transform current_tx_rate format + if (pstat_lowest) { + MACDM_Core88XX(Adapter, + lowest_tp, + pstat_lowest->rssi_level, + pstat_lowest->current_tx_rate, + pstat_lowest->WirelessMode + ); + } + } + break; + + case MACDM_MODE_STOP: + default: + break; + } + +} + +#endif //#if CFG_HAL_MACDM + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.h index 2e75bdf35f4..6d9b76b6dc6 100644 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDM.h @@ -1,92 +1,92 @@ -#ifndef __HAL88XX_DM_H__ -#define __HAL88XX_DM_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXDM.h - -Abstract: - Defined HAL 88XX Dynamic Mechanism Related Define & Marco - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-08-19 Filen Create. ---*/ - -typedef enum _RSSI_LVL_DM_88XX_ { - RSSI_LVL_LOW = 0, - RSSI_LVL_NORMAL = 1, - RSSI_LVL_HIGH = 2, - RSSI_LVL_MAX_NUM -}RSSI_LVL_DM_88XX, *PRSSI_LVL_DM_88XX; - - -typedef enum _MACDM_MODE_88XX_ { - MACDM_MODE_STOP = 0, - MACDM_MODE_MAX_TP = 1, - MACDM_MODE_AVERAGE = 2, - MACDM_MODE_MIN_TP = 3, - MACDM_MODE_MAX_NUM -}MACDM_MODE_88XX, *PMACDM_MODE_88XX; - - -typedef enum _MACDM_TP_STATE_88XX_ { - MACDM_TP_STATE_DEFAULT = 0, - MACDM_TP_STATE_GENERAL = 1, - MACDM_TP_STATE_TXOP = 2, - MACDM_TP_STATE_MAX_NUM -}MACDM_TP_STATE_88XX, *PMACDM_TP_STATE_88XX; - - -typedef enum _MACDM_TP_THRS_88XX_ { - MACDM_TP_THRS_DEF_TO_GEN = 0, - MACDM_TP_THRS_GEN_TO_DEF = 1, - MACDM_TP_THRS_GEN_TO_TXOP = 2, - MACDM_TP_THRS_TXOP_TO_GEN = 3, - MACDM_TP_THRS_MAX_NUM -}MACDM_TP_THRS_88XX, *PMACDM_TP_THRS_88XX; - - -typedef enum _MACDM_AGGRE_STATE_{ - MACDM_AGGRE_STATE_NONE = 0, - MACDM_AGGRE_STATE_TXOP, - MACDM_AGGRE_STATE_TXOP_EARLY -} MACDM_AGGRE_STATE, *PMACDM_AGGRE_STATE; - - -VOID -InitMACDM88XX( - IN HAL_PADAPTER Adapter -); - - -VOID -Timer1SecDM88XX( - IN HAL_PADAPTER Adapter -); - - -u4Byte -CalMaxAggreNum( - IN u4Byte page_size, - IN u4Byte min_pageNum, //the minimum pageNum of "dedicated queue + pub queue" - IN BOOLEAN AMSDU_En, - IN u4Byte txdesc_len -); - - -VOID -DecisionAggrePara( - IN HAL_PADAPTER Adapter, - IN u4Byte aggre_state, - IN u4Byte TxopMaxAggreNum -); - - - - -#endif //__HAL88XX_DM_H__ - +#ifndef __HAL88XX_DM_H__ +#define __HAL88XX_DM_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXDM.h + +Abstract: + Defined HAL 88XX Dynamic Mechanism Related Define & Marco + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-08-19 Filen Create. +--*/ + +typedef enum _RSSI_LVL_DM_88XX_ { + RSSI_LVL_LOW = 0, + RSSI_LVL_NORMAL = 1, + RSSI_LVL_HIGH = 2, + RSSI_LVL_MAX_NUM +}RSSI_LVL_DM_88XX, *PRSSI_LVL_DM_88XX; + + +typedef enum _MACDM_MODE_88XX_ { + MACDM_MODE_STOP = 0, + MACDM_MODE_MAX_TP = 1, + MACDM_MODE_AVERAGE = 2, + MACDM_MODE_MIN_TP = 3, + MACDM_MODE_MAX_NUM +}MACDM_MODE_88XX, *PMACDM_MODE_88XX; + + +typedef enum _MACDM_TP_STATE_88XX_ { + MACDM_TP_STATE_DEFAULT = 0, + MACDM_TP_STATE_GENERAL = 1, + MACDM_TP_STATE_TXOP = 2, + MACDM_TP_STATE_MAX_NUM +}MACDM_TP_STATE_88XX, *PMACDM_TP_STATE_88XX; + + +typedef enum _MACDM_TP_THRS_88XX_ { + MACDM_TP_THRS_DEF_TO_GEN = 0, + MACDM_TP_THRS_GEN_TO_DEF = 1, + MACDM_TP_THRS_GEN_TO_TXOP = 2, + MACDM_TP_THRS_TXOP_TO_GEN = 3, + MACDM_TP_THRS_MAX_NUM +}MACDM_TP_THRS_88XX, *PMACDM_TP_THRS_88XX; + + +typedef enum _MACDM_AGGRE_STATE_{ + MACDM_AGGRE_STATE_NONE = 0, + MACDM_AGGRE_STATE_TXOP, + MACDM_AGGRE_STATE_TXOP_EARLY +} MACDM_AGGRE_STATE, *PMACDM_AGGRE_STATE; + + +VOID +InitMACDM88XX( + IN HAL_PADAPTER Adapter +); + + +VOID +Timer1SecDM88XX( + IN HAL_PADAPTER Adapter +); + + +u4Byte +CalMaxAggreNum( + IN u4Byte page_size, + IN u4Byte min_pageNum, //the minimum pageNum of "dedicated queue + pub queue" + IN BOOLEAN AMSDU_En, + IN u4Byte txdesc_len +); + + +VOID +DecisionAggrePara( + IN HAL_PADAPTER Adapter, + IN u4Byte aggre_state, + IN u4Byte TxopMaxAggreNum +); + + + + +#endif //__HAL88XX_DM_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDebug.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDebug.h old mode 100755 new mode 100644 index ac31268df1c..0ed13cc0d96 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDebug.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDebug.h @@ -1,65 +1,65 @@ -#ifndef __HAL88XXDEBUG_H__ -#define __HAL88XXDEBUG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXDebug.h - -Abstract: - Defined HAL 88XX debug reigster - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-09-07 Eric Create. ---*/ - - -// -//**Note**: -// If one of these register is used, we should register MACRO at RTL88XXX_debug.h. -// -// Range List: -// 1.) 0x5FE ~ 0x5FF : there are no control circuit. But these register can be R/W. - -//1 Debug Register Location (from different IC) -// 4 Bytes -#define REG_DRV_DBG REG_PAGE5_DUMMY - -#define REG_DBG_DWORD_0 REG_DRV_DBG - - - -//3 Register Debug register for our purpose -// 1.) Driver Component Error -#define REGDUMP_DRV_ERR0 REG_DBG_DWORD_0 - - -//REGDUMP_DRV_ERR0 -typedef enum _DRV_ERR0_STATUS_ -{ - DRV_ER_INIT_PON = BIT0, - DRV_ER_INIT_MAC = BIT1, - DRV_ER_INIT_HCIDMA = BIT2, - DRV_ER_INIT_MACPHYREGFILE = BIT3, - DRV_ER_INIT_BBEGFILE = BIT4, - DRV_ER_INIT_PHYRF = BIT5, - DRV_ER_INIT_DLFW = BIT6, - DRV_ER_INIT_RSVD_0 = BIT7, - DRV_ER_INIT_RSVD_1 = BIT8, - DRV_ER_INIT_RSVD_2 = BIT9, - DRV_ER_CLOSE_STOP_HW = BIT10, - DRV_ER_RSVD_0 = BIT11, - DRV_ER_RSVD_1 = BIT12, - DRV_ER_RSVD_2 = BIT13, - DRV_ER_RSVD_3 = BIT14, - DRV_ER_RSVD_4 = BIT15, - DRV_ER_RSVD_5 = BIT16, - -}DRV_ERR0_STATUS, *PDRV_ERR0_STATUS; - - -#endif // __HAL88XXDEBUG_H__ - +#ifndef __HAL88XXDEBUG_H__ +#define __HAL88XXDEBUG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXDebug.h + +Abstract: + Defined HAL 88XX debug reigster + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-09-07 Eric Create. +--*/ + + +// +//**Note**: +// If one of these register is used, we should register MACRO at RTL88XXX_debug.h. +// +// Range List: +// 1.) 0x5FE ~ 0x5FF : there are no control circuit. But these register can be R/W. + +//1 Debug Register Location (from different IC) +// 4 Bytes +#define REG_DRV_DBG REG_PAGE5_DUMMY + +#define REG_DBG_DWORD_0 REG_DRV_DBG + + + +//3 Register Debug register for our purpose +// 1.) Driver Component Error +#define REGDUMP_DRV_ERR0 REG_DBG_DWORD_0 + + +//REGDUMP_DRV_ERR0 +typedef enum _DRV_ERR0_STATUS_ +{ + DRV_ER_INIT_PON = BIT0, + DRV_ER_INIT_MAC = BIT1, + DRV_ER_INIT_HCIDMA = BIT2, + DRV_ER_INIT_MACPHYREGFILE = BIT3, + DRV_ER_INIT_BBEGFILE = BIT4, + DRV_ER_INIT_PHYRF = BIT5, + DRV_ER_INIT_DLFW = BIT6, + DRV_ER_INIT_RSVD_0 = BIT7, + DRV_ER_INIT_RSVD_1 = BIT8, + DRV_ER_INIT_RSVD_2 = BIT9, + DRV_ER_CLOSE_STOP_HW = BIT10, + DRV_ER_RSVD_0 = BIT11, + DRV_ER_RSVD_1 = BIT12, + DRV_ER_RSVD_2 = BIT13, + DRV_ER_RSVD_3 = BIT14, + DRV_ER_RSVD_4 = BIT15, + DRV_ER_RSVD_5 = BIT16, + +}DRV_ERR0_STATUS, *PDRV_ERR0_STATUS; + + +#endif // __HAL88XXDEBUG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDef.h old mode 100755 new mode 100644 index 3c46d83ae15..5d2aaf6b853 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDef.h @@ -1,286 +1,286 @@ -#ifndef __HAL88XX_DEF_H__ -#define __HAL88XX_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXDef.h - -Abstract: - Defined HAL 88XX common data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - -#ifdef WLAN_HAL_INTERNAL_USED - -MIMO_TR_STATUS -GetChipIDMIMO88XX( - IN HAL_PADAPTER Adapter -); - - -VOID -CAMEmptyEntry88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte index -); - - -u4Byte -CAMFindUsable88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte for_begin -); - - -VOID -CAMReadMACConfig88XX -( - IN HAL_PADAPTER Adapter, - IN u1Byte index, - OUT pu1Byte pMacad, - OUT PCAM_ENTRY_CFG pCfg -); - - -VOID -CAMProgramEntry88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte index, - IN pu1Byte macad, - IN pu1Byte key128, - IN u2Byte config -); - - -VOID -SetHwReg88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte variable, - IN pu1Byte val -); - - -VOID -GetHwReg88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte variable, - OUT pu1Byte val -); - -RT_STATUS -GetMACIDQueueInTXPKTBUF88XX( - IN HAL_PADAPTER Adapter, - OUT pu1Byte MACIDList -); - - -RT_STATUS -SetMACIDSleep88XX( - IN HAL_PADAPTER Adapter, - IN BOOLEAN bSleep, - IN u4Byte aid -); - -#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES) -RT_STATUS -InitLLT_Table88XX( - IN HAL_PADAPTER Adapter -); -#endif //#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES) - -#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) -RT_STATUS -InitLLT_Table88XX_V1( - IN HAL_PADAPTER Adapter -); -#endif //#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) - -RT_STATUS -InitPON88XX( - IN HAL_PADAPTER Adapter -); - -RT_STATUS -InitMAC88XX( - IN HAL_PADAPTER Adapter -); - -VOID -InitIMR88XX( - IN HAL_PADAPTER Adapter, - IN RT_OP_MODE OPMode -); - -VOID -InitVAPIMR88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte VapSeq -); - - -RT_STATUS -InitHCIDMAMem88XX( - IN HAL_PADAPTER Adapter -); - -RT_STATUS -InitHCIDMAReg88XX( - IN HAL_PADAPTER Adapter -); - -VOID -StopHCIDMASW88XX( - IN HAL_PADAPTER Adapter -); - -VOID -StopHCIDMAHW88XX( - IN HAL_PADAPTER Adapter -); - -#if CFG_HAL_SUPPORT_MBSSID -VOID -InitMBSSID88XX( - IN HAL_PADAPTER Adapter -); - -VOID -InitMBIDCAM88XX( - IN HAL_PADAPTER Adapter -); - -VOID -StopMBSSID88XX( - IN HAL_PADAPTER Adapter -); -#endif //CFG_HAL_SUPPORT_MBSSID - -RT_STATUS -SetMBIDCAM88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte MBID_Addr, - IN u1Byte IsRoot -); - -RT_STATUS -StopMBIDCAM88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte MBID_Addr -); - -RT_STATUS -ResetHWForSurprise88XX( - IN HAL_PADAPTER Adapter -); - -#if CFG_HAL_MULTI_MAC_CLONE -VOID -McloneSetMBSSID88XX( - IN HAL_PADAPTER Adapter, - IN pu1Byte macAddr, - IN int entIdx -); - -VOID -McloneStopMBSSID88XX( - IN HAL_PADAPTER Adapter, - IN int entIdx -); -#endif // #if CFG_HAL_MULTI_MAC_CLONE - -RT_STATUS -StopHW88XX( - IN HAL_PADAPTER Adapter -); - -RT_STATUS -StopSW88XX( - IN HAL_PADAPTER Adapter -); - -VOID -DisableVXDAP88XX( - IN HAL_PADAPTER Adapter -); - -VOID -Timer1Sec88XX( - IN HAL_PADAPTER Adapter -); - -RT_STATUS -GetTxRPTBuf88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte macID, - IN u1Byte variable, - IN u1Byte byteoffset, - OUT pu1Byte val -); - -RT_STATUS -SetTxRPTBuf88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte macID, - IN u1Byte variable, - IN pu1Byte val -); - -u4Byte -CheckHang88XX( - IN HAL_PADAPTER Adapter -); - -VOID -SetCRC5ToRPTBuffer88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte val, - IN u4Byte macID, - IN u1Byte bValid -); - -VOID -SetCRC5ValidBit88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte group, - IN u1Byte bValid - -); - -VOID -SetCRC5EndBit88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte group, - IN u1Byte bEnd -); - -VOID -InitMACIDSearch88XX( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -CheckHWMACIDResult88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte MacID, - OUT pu1Byte result -); - - -RT_STATUS -InitDDMA88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte source, - IN u4Byte dest, - IN u4Byte length -); - -#endif //WLAN_HAL_INTERNAL_USED - -#endif //__HAL88XX_DEF_H__ +#ifndef __HAL88XX_DEF_H__ +#define __HAL88XX_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXDef.h + +Abstract: + Defined HAL 88XX common data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + +#ifdef WLAN_HAL_INTERNAL_USED + +MIMO_TR_STATUS +GetChipIDMIMO88XX( + IN HAL_PADAPTER Adapter +); + + +VOID +CAMEmptyEntry88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte index +); + + +u4Byte +CAMFindUsable88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte for_begin +); + + +VOID +CAMReadMACConfig88XX +( + IN HAL_PADAPTER Adapter, + IN u1Byte index, + OUT pu1Byte pMacad, + OUT PCAM_ENTRY_CFG pCfg +); + + +VOID +CAMProgramEntry88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte index, + IN pu1Byte macad, + IN pu1Byte key128, + IN u2Byte config +); + + +VOID +SetHwReg88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte variable, + IN pu1Byte val +); + + +VOID +GetHwReg88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte variable, + OUT pu1Byte val +); + +RT_STATUS +GetMACIDQueueInTXPKTBUF88XX( + IN HAL_PADAPTER Adapter, + OUT pu1Byte MACIDList +); + + +RT_STATUS +SetMACIDSleep88XX( + IN HAL_PADAPTER Adapter, + IN BOOLEAN bSleep, + IN u4Byte aid +); + +#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES) +RT_STATUS +InitLLT_Table88XX( + IN HAL_PADAPTER Adapter +); +#endif //#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES) + +#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) +RT_STATUS +InitLLT_Table88XX_V1( + IN HAL_PADAPTER Adapter +); +#endif //#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) + +RT_STATUS +InitPON88XX( + IN HAL_PADAPTER Adapter +); + +RT_STATUS +InitMAC88XX( + IN HAL_PADAPTER Adapter +); + +VOID +InitIMR88XX( + IN HAL_PADAPTER Adapter, + IN RT_OP_MODE OPMode +); + +VOID +InitVAPIMR88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte VapSeq +); + + +RT_STATUS +InitHCIDMAMem88XX( + IN HAL_PADAPTER Adapter +); + +RT_STATUS +InitHCIDMAReg88XX( + IN HAL_PADAPTER Adapter +); + +VOID +StopHCIDMASW88XX( + IN HAL_PADAPTER Adapter +); + +VOID +StopHCIDMAHW88XX( + IN HAL_PADAPTER Adapter +); + +#if CFG_HAL_SUPPORT_MBSSID +VOID +InitMBSSID88XX( + IN HAL_PADAPTER Adapter +); + +VOID +InitMBIDCAM88XX( + IN HAL_PADAPTER Adapter +); + +VOID +StopMBSSID88XX( + IN HAL_PADAPTER Adapter +); +#endif //CFG_HAL_SUPPORT_MBSSID + +RT_STATUS +SetMBIDCAM88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte MBID_Addr, + IN u1Byte IsRoot +); + +RT_STATUS +StopMBIDCAM88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte MBID_Addr +); + +RT_STATUS +ResetHWForSurprise88XX( + IN HAL_PADAPTER Adapter +); + +#if CFG_HAL_MULTI_MAC_CLONE +VOID +McloneSetMBSSID88XX( + IN HAL_PADAPTER Adapter, + IN pu1Byte macAddr, + IN int entIdx +); + +VOID +McloneStopMBSSID88XX( + IN HAL_PADAPTER Adapter, + IN int entIdx +); +#endif // #if CFG_HAL_MULTI_MAC_CLONE + +RT_STATUS +StopHW88XX( + IN HAL_PADAPTER Adapter +); + +RT_STATUS +StopSW88XX( + IN HAL_PADAPTER Adapter +); + +VOID +DisableVXDAP88XX( + IN HAL_PADAPTER Adapter +); + +VOID +Timer1Sec88XX( + IN HAL_PADAPTER Adapter +); + +RT_STATUS +GetTxRPTBuf88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte macID, + IN u1Byte variable, + IN u1Byte byteoffset, + OUT pu1Byte val +); + +RT_STATUS +SetTxRPTBuf88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte macID, + IN u1Byte variable, + IN pu1Byte val +); + +u4Byte +CheckHang88XX( + IN HAL_PADAPTER Adapter +); + +VOID +SetCRC5ToRPTBuffer88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte val, + IN u4Byte macID, + IN u1Byte bValid +); + +VOID +SetCRC5ValidBit88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte group, + IN u1Byte bValid + +); + +VOID +SetCRC5EndBit88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte group, + IN u1Byte bEnd +); + +VOID +InitMACIDSearch88XX( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +CheckHWMACIDResult88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte MacID, + OUT pu1Byte result +); + + +RT_STATUS +InitDDMA88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte source, + IN u4Byte dest, + IN u4Byte length +); + +#endif //WLAN_HAL_INTERNAL_USED + +#endif //__HAL88XX_DEF_H__ diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDesc.h old mode 100755 new mode 100644 index 2a0c7edb4c3..34c4588f159 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDesc.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXDesc.h @@ -1,54 +1,54 @@ -#ifndef __HAL88XXDESC_H__ -#define __HAL88XXDESC_H__ - - -#define SET_MEM_OP(Dw, Value32, Mask, Shift) \ - (((Dw) & ~((Mask)<<(Shift)))|(((Value32)&(Mask))<<(Shift))) - - -#if CFG_HAL_CHECK_SWAP - -//No Clear First -#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ - Dw |= (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ - (HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift))): \ - (((Value32)&(Mask))<<(Shift)); - -//3 Note: Performance bad, don't use as possible -//Clear first then set -#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ -{ \ - u4Byte lDw = Dw; \ - Dw = (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ - (HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(lDw), Value32, Mask, Shift))) : \ - (SET_MEM_OP(lDw, Value32, Mask, Shift)); \ -} - -#define GET_DESC_FIELD(Dw, Mask, Shift) \ - ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ - ((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask)) : \ - (((Dw)>>(Shift)) & (Mask))) - -#define GET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_le32_to_cpu(val) : val) -#define SET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_cpu_to_le32(val) : val) - - -#else - -#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ - Dw |= (HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift))); - - -#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ - Dw = (HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(Dw), Value32, Mask, Shift))); - - -#define GET_DESC_FIELD(Dw, Mask, Shift) \ - ((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask)) - -#define GET_DESC(val) (val) -#define SET_DESC(val) (val) - -#endif - -#endif // __HAL88XXDESC_H__ +#ifndef __HAL88XXDESC_H__ +#define __HAL88XXDESC_H__ + + +#define SET_MEM_OP(Dw, Value32, Mask, Shift) \ + (((Dw) & ~((Mask)<<(Shift)))|(((Value32)&(Mask))<<(Shift))) + + +#if CFG_HAL_CHECK_SWAP + +//No Clear First +#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ + Dw |= (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ + (HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift))): \ + (((Value32)&(Mask))<<(Shift)); + +//3 Note: Performance bad, don't use as possible +//Clear first then set +#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ +{ \ + u4Byte lDw = Dw; \ + Dw = (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ + (HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(lDw), Value32, Mask, Shift))) : \ + (SET_MEM_OP(lDw, Value32, Mask, Shift)); \ +} + +#define GET_DESC_FIELD(Dw, Mask, Shift) \ + ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \ + ((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask)) : \ + (((Dw)>>(Shift)) & (Mask))) + +#define GET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_le32_to_cpu(val) : val) +#define SET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_cpu_to_le32(val) : val) + + +#else + +#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ + Dw |= (HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift))); + + +#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ + Dw = (HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(Dw), Value32, Mask, Shift))); + + +#define GET_DESC_FIELD(Dw, Mask, Shift) \ + ((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask)) + +#define GET_DESC(val) (val) +#define SET_DESC(val) (val) + +#endif + +#endif // __HAL88XXDESC_H__ diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.h old mode 100755 new mode 100644 index f1dda5ce3d0..7a6ff907598 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXFirmware.h @@ -1,484 +1,484 @@ -#ifndef __HAL88XX_FIRMWARE_H__ -#define __HAL88XX_FIRMWARE_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXFirmware.h - -Abstract: - Defined HAL 88XX Firmware data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-04-11 Filen Create. ---*/ - -#define H2C_PACKET_PAYLOAD_MAX_SIZE 32 -#define H2C_ENTERY_MAX_NUM 32 - -/**********************/ -// Mapping C2H callback function - -#define ctrlInfoSZ 32 - -typedef struct _Ctrl_Info_ { - u1Byte SGI: 1; - u1Byte Data_Rate: 7; - u1Byte PKT_DROP: 1; - u1Byte TRY_RATE: 1; - u1Byte Rsvd: 1; - u1Byte DATA_BW: 2; - u1Byte PWRSTS: 3; - u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; - u1Byte Rsvd2: 1; - u1Byte GROUP_TABLE_ID: 3; - u1Byte RTY_LOW_RATE_EN: 1; - u1Byte DATA_RTY_LOW_RATE: 7; - u1Byte RTY_LMT_EN: 1; - u1Byte RTS_RT_LOW_RATE: 7; - u1Byte Rsvd3: 1; - u1Byte PKT_TX_ONE_SEL: 1; - u1Byte DATA_RT_LMT: 6; - u1Byte Rsvd4: 8; - u1Byte Rsvd5: 8; -} Ctrl_Info , *PCtrl_Info; - - -typedef enum _RTL88XX_C2H_EVT -{ - C2H_88XX_DBG = 0, - C2H_88XX_LB = 1, - C2H_88XX_TXBF = 2, - C2H_88XX_TX_REPORT = 3, - C2H_88XX_TX_RATE =4, - C2H_88XX_BT_INFO = 9, - C2H_88XX_BT_MP = 11, -#ifdef TXRETRY_CNT - C2H_88XX_TX_RETRY = 13, //0x0D -#endif - C2H_88XX_RA_PARA_RPT=14, - C2H_88XX_RA_DYNAMIC_TX_PATH_RPT = 15, - C2H_88XX_STATISTIC_RPT = 41, - C2H_88XX_EXTEND_IND = 0xFF, - MAX_88XX_C2HEVENT -}RTL88XX_C2H_EVT; - -typedef enum _RTL88XX_EXTEND_C2H_EVT -{ - EXTEND_C2H_88XX_DBG_PRINT = 0, - EXTEND_C2H_88XX_CCX_RPT = 0xf, - EXTEND_C2H_88XX_ATM_RPT = 0x11, -}RTL88XX_EXTEND_C2H_EVT; - -typedef struct _TXRPT_ -{ - u1Byte RPT_MACID; - u2Byte RPT_TXOK; - u2Byte RPT_TXFAIL; - u1Byte RPT_InitialRate; -}__attribute__ ((packed)) TXRPT,*PTXRPT ; - - -typedef struct _APREQTXRPT_ -{ - TXRPT txrpt[2]; -}__attribute__ ((packed)) APREQTXRPT,*PAPREQTXRPT ; - - -#define GEN_FW_CMD_HANDLER(size, cmd) {size, cmd##Handler}, - - -//void h2csetdsr(void); - -struct cmdobj { - u4Byte parmsize; - VOID (*c2hfuns)(IN HAL_PADAPTER Adapter,u1Byte *pbuf); -}; - - - -//----------------------------------------------------- -// -// 0x1200h ~ 0x12FFh DDMA CTRL -// -//----------------------------------------------------- -#define DDMA_LEN_MASK 0x0001FFFF -#define DDMA_CH_CHKSUM_CNT BIT(24) -#define DDMA_RST_CHKSUM_STS BIT(25) -#define DDMA_MODE_BLOCK_CPU BIT(26) -#define DDMA_CHKSUM_FAIL BIT(27) -#define DDMA_DA_W_DISABLE BIT(28) -#define DDMA_CHKSUM_EN BIT(29) -#define DDMA_CH_OWN BIT(31) - - - - -typedef struct _RTL88XX_FW_HDR_ -{ - u2Byte signature; - u1Byte category; - u1Byte function; - - u2Byte version; - u1Byte subversion; - u1Byte rsvd1; - - u1Byte month; //human easy reading format - u1Byte day; //human easy reading format - u1Byte hour; //human easy reading format - u1Byte minute; //human easy reading format - - u2Byte ram_code_size; - u1Byte Foundry; //0: TSMC, 1:UMC, 2:SMIC - u1Byte rsvd3; - u4Byte svnidx; - u4Byte rsvd5; - u4Byte rsvd6; - u4Byte rsvd7; - -}RTL88XX_FW_HDR, *PRTL88XX_FW_HDR; - -typedef struct _RTL88XX_MIPS_FW_HDR_ -{ - //offset0 - u2Byte signature; - u1Byte category; - u1Byte function; - u2Byte version; - u1Byte Subversion; - u1Byte sub_index; - //offset8 - u4Byte SVN_index; - u4Byte rsvd1; - //offset16 - u1Byte Month; - u1Byte Date; - u1Byte Hour; - u1Byte Min; - u2Byte Year; - u1Byte Foundry; - u1Byte rsvd2; - //offset24 - u1Byte MEM_USAGE__DL_from:1; - u1Byte MEM_USAGE__BOOT_from:1; - u1Byte MEM_USAGE__BOOT_LOADER:1; - u1Byte MEM_USAGE__IRAM:1; - u1Byte MEM_USAGE__ERAM:1; - u1Byte MEM_USAGE__rsvd4:3; - u1Byte rsvd3; - u2Byte BOOT_LOADER_SZ; - u4Byte rsvd5; - //offset32 - u4Byte TOTAL_DMEM_SZ; - u2Byte FW_CFG_SZ; - u2Byte FW_ATTR_SZ; - //offset40 - u4Byte IROM_SZ; - u4Byte EROM_SZ; - //offset 48 - u4Byte IRAM_SZ; - u4Byte ERAM_SZ; - //offset 56 - u4Byte rsvd6; - u4Byte rsvd7; -}RTL88XX_MIPS_FW_HDR, *PRTL88XX_MIPS_FW_HDR; - -// TODO: Filen, check below -typedef enum _RTL88XX_H2C_CMD -{ -// H2C_88XX_RSVDPAGE = 0, - H2C_88XX_MSRRPT = 0x1, -// H2C_88XX_KEEP_ALIVE_CTRL = 0x3, -// H2C_88XX_WO_WLAN = 0x5, // Wake on Wlan. -// H2C_88XX_REMOTE_WAKEUP = 0x7, - H2C_88XX_AP_OFFLOAD = 0x8, - H2C_88XX_BCN_RSVDPAGE = 0x9, - H2C_88XX_PROBE_RSVDPAGE = 0xa, - H2C_88XX_APPS_OFFLOAD_SETTING = 0xc, - H2C_88XX_APPS_OFFLOAD_CTRL = 0xd, - H2C_88XX_WAKEUP_PIN = 0x13, -// H2C_88XX_SETPWRMODE = 0x20, -// H2C_88XX_P2P_PS_MODE = 0x24, - H2C_88XX_SAP_PS = 0x26, - H2C_88XX_RA_MASK = 0x40, - H2C_88XX_RSSI_REPORT = 0x42, - H2C_88XX_AP_REQ_TXREP = 0x43, - H2C_88XX_RA_MASK_3SS = 0x46, - H2C_88XX_RA_PARA_ADJUST = 0x47, - H2C_88XX_DYNAMIC_TX_PATH = 0x48, - H2C_88XX_FW_TRACE_EN = 0x49, - -#ifdef ENABLE_BT_COEXIST - H2C_88XX_BT_TDMA = 0x60, /* BT TDMA */ - H2C_88XX_BT_INFO = 0x61, /* BT info */ - H2C_88XX_BT_63 = 0x63, -#endif - H2C_88XX_APREQ_ATM_RPT = 0xB3, // for ATM info - H2C_88XX_APREQ_STATISTIC_RPT = 0xB9, //for FW report statistic counter - H2C_88XX_NHM = 0xC1, - H2C_88XX_BCN_IGNORE_EDCCA = 0xC2, - H2C_88XX_REPEAT_WAKE_PULSE = 0xC4, - MAX_88XX_H2CCMD -}RTL88XX_H2C_CMD; - - -typedef enum _RTL88XX_C2H_CMD -{ -// C2H_88XX_DBG = 0, -// C2H_88XX_C2H_LB = 0x1, -// C2H_88XX_SND_TXBF = 0x2, -// C2H_88XX_CCXRPT = 0x3, - C2H_88XX_APREQTXRPT = 0x4, -// C2H_88XX_INITIALRATE = 0x5, -// C2H_88XX_PSD_RPT = 0x6, -// C2H_88XX_SCAN_COMPLETE = 0x7, -// C2H_88XX_PSD_CONTROL = 0x8, -// C2H_88XX_BT_INFO = 0x9, -// C2H_88XX_BT_LOOPBACK = 0xa, - - MAX_88XX_C2HCMD -}RTL88XX_C2H_CMD; - - -VOID -ReadMIPSFwHdr88XX( - IN HAL_PADAPTER Adapter -); - -RT_STATUS -InitMIPSFirmware88XX( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -InitFirmware88XX( - IN HAL_PADAPTER Adapter -); - -#if 0 -typedef struct _H2C_CONTENT_ -{ - u4Byte content; - u2Byte ext_content; -}H2C_CONTENT, *PH2C_CONTENT; - - - -BOOLEAN -IsH2CBufOccupy88XX( - IN HAL_PADAPTER Adapter -); - - -BOOLEAN -SigninH2C88XX( - IN HAL_PADAPTER Adapter, - IN PH2C_CONTENT pH2CContent -); -#else -BOOLEAN -CheckFwReadLastH2C88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte BoxNum -); - -RT_STATUS -FillH2CCmd88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte ElementID, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer -); -#endif -#ifdef CFG_HAL_WLAN_SUPPORT_H2C_PACKET -VOID -SetH2CPacketHeader88XX( - IN VOID *pDriver_adapter, - OUT u8 *pHal_h2c_hdr, - IN u8 ack, - IN u16 totallength, - IN u8 category, - IN u8 CMDID, - IN u16 sub_CMDID -); -u8 -SendH2CPacket88XX( - IN VOID *pDriver_adapter, - IN u8 *pBuf, - IN u32 size -); -#endif -u8 -ParseC2HPacket88XX( - IN VOID *pDriver_adapter, - IN u8 *pbuf, - IN u32 c2hsize -); - - -VOID -UpdateHalRAMask88XX( - IN HAL_PADAPTER Adapter, - HAL_PSTAINFO pEntry, - u1Byte rssi_level -); - -VOID -UpdateHalRAMask8814A( - IN HAL_PADAPTER Adapter, - HAL_PSTAINFO pEntry, - u1Byte rssi_level -); - -void -UpdateHalMSRRPT88XX( - IN HAL_PADAPTER Adapter, - HAL_PSTAINFO pEntry, - u1Byte opmode -); - -extern void -SetStatistic_Report88XX( - IN HAL_PADAPTER Adapter, - u1Byte report_en, - u1Byte report_type, - u1Byte report_interval -); -#ifdef RTK_ATM -extern void -SetATM_Report88XX( - IN HAL_PADAPTER Adapter, - u1Byte ATM_en, - u1Byte range1_en, - u1Byte range2_en, - u1Byte range3_en, - u1Byte range4_en, - u1Byte request_period -); -#endif -void -SetAPOffload88XX( - IN HAL_PADAPTER Adapter, - u1Byte bEn, - u1Byte numOfAP, - u1Byte bHidden, - u1Byte bDenyAny, - pu1Byte loc_bcn, - pu1Byte loc_probe -); - -#ifdef AP_PS_Offlaod -void -SetAPPSOffload88XX( - IN HAL_PADAPTER Adapter, - u1Byte _PS_offload_En, - u1Byte _phase, - u1Byte _pause_Qnum_limit, - u1Byte _timeout_time -); - -void -APPSOffloadMacidPauseCtrl88XX( - IN HAL_PADAPTER Adapter, - u1Byte macid, - u1Byte setPause -); -#endif - -VOID SetSAPPS88XX -( - IN HAL_PADAPTER Adapter, - u1Byte en, - u1Byte duration -); - -VOID -SetRsvdPage88XX -( - IN IN HAL_PADAPTER Adapter, - IN pu1Byte prsp, - IN pu4Byte beaconbuf, - IN u4Byte pktLen, - IN u4Byte bigPktLen, - IN u4Byte bcnLen -); - -u4Byte -GetRsvdPageLoc88XX -( - IN IN HAL_PADAPTER Adapter, - IN u4Byte frlen, - OUT pu1Byte loc_page -); - -BOOLEAN -DownloadRsvdPage88XX -( - IN HAL_PADAPTER Adapter, - IN pu4Byte beaconbuf, - IN u4Byte beaconPktLen, - IN u1Byte bReDownload -); - -void C2HHandler88XX( - IN HAL_PADAPTER Adapter -); - -void C2HPacket88XX( - IN HAL_PADAPTER Adapter, - IN pu1Byte pBuf, - IN u2Byte length -); - -VOID -C2HEventHandler88XX -( - IN HAL_PADAPTER Adapter, - IN u1Byte c2hCmdId, - IN u2Byte c2hCmdLen, - IN pu1Byte tmpBuf -); - -VOID -C2HExtEventHandler88XX -( - IN HAL_PADAPTER Adapter, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf -); - -#ifdef RTK_ATM -VOID -C2HATMReportHandler88XX -( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u2Byte CmdLen -); -#endif - -#if (BEAMFORMING_SUPPORT == 1) -VOID -C2HTxBeamformingHandler88XX( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); -#endif -#if (MU_BEAMFORMING_SUPPORT == 1) -VOID -C2HCCXRptHandler88XX( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); -#endif - -#endif //__HAL88XX_FIRMWARE_H__ - +#ifndef __HAL88XX_FIRMWARE_H__ +#define __HAL88XX_FIRMWARE_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXFirmware.h + +Abstract: + Defined HAL 88XX Firmware data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-04-11 Filen Create. +--*/ + +#define H2C_PACKET_PAYLOAD_MAX_SIZE 32 +#define H2C_ENTERY_MAX_NUM 32 + +/**********************/ +// Mapping C2H callback function + +#define ctrlInfoSZ 32 + +typedef struct _Ctrl_Info_ { + u1Byte SGI: 1; + u1Byte Data_Rate: 7; + u1Byte PKT_DROP: 1; + u1Byte TRY_RATE: 1; + u1Byte Rsvd: 1; + u1Byte DATA_BW: 2; + u1Byte PWRSTS: 3; + u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; + u1Byte Rsvd2: 1; + u1Byte GROUP_TABLE_ID: 3; + u1Byte RTY_LOW_RATE_EN: 1; + u1Byte DATA_RTY_LOW_RATE: 7; + u1Byte RTY_LMT_EN: 1; + u1Byte RTS_RT_LOW_RATE: 7; + u1Byte Rsvd3: 1; + u1Byte PKT_TX_ONE_SEL: 1; + u1Byte DATA_RT_LMT: 6; + u1Byte Rsvd4: 8; + u1Byte Rsvd5: 8; +} Ctrl_Info , *PCtrl_Info; + + +typedef enum _RTL88XX_C2H_EVT +{ + C2H_88XX_DBG = 0, + C2H_88XX_LB = 1, + C2H_88XX_TXBF = 2, + C2H_88XX_TX_REPORT = 3, + C2H_88XX_TX_RATE =4, + C2H_88XX_BT_INFO = 9, + C2H_88XX_BT_MP = 11, +#ifdef TXRETRY_CNT + C2H_88XX_TX_RETRY = 13, //0x0D +#endif + C2H_88XX_RA_PARA_RPT=14, + C2H_88XX_RA_DYNAMIC_TX_PATH_RPT = 15, + C2H_88XX_STATISTIC_RPT = 41, + C2H_88XX_EXTEND_IND = 0xFF, + MAX_88XX_C2HEVENT +}RTL88XX_C2H_EVT; + +typedef enum _RTL88XX_EXTEND_C2H_EVT +{ + EXTEND_C2H_88XX_DBG_PRINT = 0, + EXTEND_C2H_88XX_CCX_RPT = 0xf, + EXTEND_C2H_88XX_ATM_RPT = 0x11, +}RTL88XX_EXTEND_C2H_EVT; + +typedef struct _TXRPT_ +{ + u1Byte RPT_MACID; + u2Byte RPT_TXOK; + u2Byte RPT_TXFAIL; + u1Byte RPT_InitialRate; +}__attribute__ ((packed)) TXRPT,*PTXRPT ; + + +typedef struct _APREQTXRPT_ +{ + TXRPT txrpt[2]; +}__attribute__ ((packed)) APREQTXRPT,*PAPREQTXRPT ; + + +#define GEN_FW_CMD_HANDLER(size, cmd) {size, cmd##Handler}, + + +//void h2csetdsr(void); + +struct cmdobj { + u4Byte parmsize; + VOID (*c2hfuns)(IN HAL_PADAPTER Adapter,u1Byte *pbuf); +}; + + + +//----------------------------------------------------- +// +// 0x1200h ~ 0x12FFh DDMA CTRL +// +//----------------------------------------------------- +#define DDMA_LEN_MASK 0x0001FFFF +#define DDMA_CH_CHKSUM_CNT BIT(24) +#define DDMA_RST_CHKSUM_STS BIT(25) +#define DDMA_MODE_BLOCK_CPU BIT(26) +#define DDMA_CHKSUM_FAIL BIT(27) +#define DDMA_DA_W_DISABLE BIT(28) +#define DDMA_CHKSUM_EN BIT(29) +#define DDMA_CH_OWN BIT(31) + + + + +typedef struct _RTL88XX_FW_HDR_ +{ + u2Byte signature; + u1Byte category; + u1Byte function; + + u2Byte version; + u1Byte subversion; + u1Byte rsvd1; + + u1Byte month; //human easy reading format + u1Byte day; //human easy reading format + u1Byte hour; //human easy reading format + u1Byte minute; //human easy reading format + + u2Byte ram_code_size; + u1Byte Foundry; //0: TSMC, 1:UMC, 2:SMIC + u1Byte rsvd3; + u4Byte svnidx; + u4Byte rsvd5; + u4Byte rsvd6; + u4Byte rsvd7; + +}RTL88XX_FW_HDR, *PRTL88XX_FW_HDR; + +typedef struct _RTL88XX_MIPS_FW_HDR_ +{ + //offset0 + u2Byte signature; + u1Byte category; + u1Byte function; + u2Byte version; + u1Byte Subversion; + u1Byte sub_index; + //offset8 + u4Byte SVN_index; + u4Byte rsvd1; + //offset16 + u1Byte Month; + u1Byte Date; + u1Byte Hour; + u1Byte Min; + u2Byte Year; + u1Byte Foundry; + u1Byte rsvd2; + //offset24 + u1Byte MEM_USAGE__DL_from:1; + u1Byte MEM_USAGE__BOOT_from:1; + u1Byte MEM_USAGE__BOOT_LOADER:1; + u1Byte MEM_USAGE__IRAM:1; + u1Byte MEM_USAGE__ERAM:1; + u1Byte MEM_USAGE__rsvd4:3; + u1Byte rsvd3; + u2Byte BOOT_LOADER_SZ; + u4Byte rsvd5; + //offset32 + u4Byte TOTAL_DMEM_SZ; + u2Byte FW_CFG_SZ; + u2Byte FW_ATTR_SZ; + //offset40 + u4Byte IROM_SZ; + u4Byte EROM_SZ; + //offset 48 + u4Byte IRAM_SZ; + u4Byte ERAM_SZ; + //offset 56 + u4Byte rsvd6; + u4Byte rsvd7; +}RTL88XX_MIPS_FW_HDR, *PRTL88XX_MIPS_FW_HDR; + +// TODO: Filen, check below +typedef enum _RTL88XX_H2C_CMD +{ +// H2C_88XX_RSVDPAGE = 0, + H2C_88XX_MSRRPT = 0x1, +// H2C_88XX_KEEP_ALIVE_CTRL = 0x3, +// H2C_88XX_WO_WLAN = 0x5, // Wake on Wlan. +// H2C_88XX_REMOTE_WAKEUP = 0x7, + H2C_88XX_AP_OFFLOAD = 0x8, + H2C_88XX_BCN_RSVDPAGE = 0x9, + H2C_88XX_PROBE_RSVDPAGE = 0xa, + H2C_88XX_APPS_OFFLOAD_SETTING = 0xc, + H2C_88XX_APPS_OFFLOAD_CTRL = 0xd, + H2C_88XX_WAKEUP_PIN = 0x13, +// H2C_88XX_SETPWRMODE = 0x20, +// H2C_88XX_P2P_PS_MODE = 0x24, + H2C_88XX_SAP_PS = 0x26, + H2C_88XX_RA_MASK = 0x40, + H2C_88XX_RSSI_REPORT = 0x42, + H2C_88XX_AP_REQ_TXREP = 0x43, + H2C_88XX_RA_MASK_3SS = 0x46, + H2C_88XX_RA_PARA_ADJUST = 0x47, + H2C_88XX_DYNAMIC_TX_PATH = 0x48, + H2C_88XX_FW_TRACE_EN = 0x49, + +#ifdef ENABLE_BT_COEXIST + H2C_88XX_BT_TDMA = 0x60, /* BT TDMA */ + H2C_88XX_BT_INFO = 0x61, /* BT info */ + H2C_88XX_BT_63 = 0x63, +#endif + H2C_88XX_APREQ_ATM_RPT = 0xB3, // for ATM info + H2C_88XX_APREQ_STATISTIC_RPT = 0xB9, //for FW report statistic counter + H2C_88XX_NHM = 0xC1, + H2C_88XX_BCN_IGNORE_EDCCA = 0xC2, + H2C_88XX_REPEAT_WAKE_PULSE = 0xC4, + MAX_88XX_H2CCMD +}RTL88XX_H2C_CMD; + + +typedef enum _RTL88XX_C2H_CMD +{ +// C2H_88XX_DBG = 0, +// C2H_88XX_C2H_LB = 0x1, +// C2H_88XX_SND_TXBF = 0x2, +// C2H_88XX_CCXRPT = 0x3, + C2H_88XX_APREQTXRPT = 0x4, +// C2H_88XX_INITIALRATE = 0x5, +// C2H_88XX_PSD_RPT = 0x6, +// C2H_88XX_SCAN_COMPLETE = 0x7, +// C2H_88XX_PSD_CONTROL = 0x8, +// C2H_88XX_BT_INFO = 0x9, +// C2H_88XX_BT_LOOPBACK = 0xa, + + MAX_88XX_C2HCMD +}RTL88XX_C2H_CMD; + + +VOID +ReadMIPSFwHdr88XX( + IN HAL_PADAPTER Adapter +); + +RT_STATUS +InitMIPSFirmware88XX( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +InitFirmware88XX( + IN HAL_PADAPTER Adapter +); + +#if 0 +typedef struct _H2C_CONTENT_ +{ + u4Byte content; + u2Byte ext_content; +}H2C_CONTENT, *PH2C_CONTENT; + + + +BOOLEAN +IsH2CBufOccupy88XX( + IN HAL_PADAPTER Adapter +); + + +BOOLEAN +SigninH2C88XX( + IN HAL_PADAPTER Adapter, + IN PH2C_CONTENT pH2CContent +); +#else +BOOLEAN +CheckFwReadLastH2C88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte BoxNum +); + +RT_STATUS +FillH2CCmd88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); +#endif +#ifdef CFG_HAL_WLAN_SUPPORT_H2C_PACKET +VOID +SetH2CPacketHeader88XX( + IN VOID *pDriver_adapter, + OUT u8 *pHal_h2c_hdr, + IN u8 ack, + IN u16 totallength, + IN u8 category, + IN u8 CMDID, + IN u16 sub_CMDID +); +u8 +SendH2CPacket88XX( + IN VOID *pDriver_adapter, + IN u8 *pBuf, + IN u32 size +); +#endif +u8 +ParseC2HPacket88XX( + IN VOID *pDriver_adapter, + IN u8 *pbuf, + IN u32 c2hsize +); + + +VOID +UpdateHalRAMask88XX( + IN HAL_PADAPTER Adapter, + HAL_PSTAINFO pEntry, + u1Byte rssi_level +); + +VOID +UpdateHalRAMask8814A( + IN HAL_PADAPTER Adapter, + HAL_PSTAINFO pEntry, + u1Byte rssi_level +); + +void +UpdateHalMSRRPT88XX( + IN HAL_PADAPTER Adapter, + HAL_PSTAINFO pEntry, + u1Byte opmode +); + +extern void +SetStatistic_Report88XX( + IN HAL_PADAPTER Adapter, + u1Byte report_en, + u1Byte report_type, + u1Byte report_interval +); +#ifdef RTK_ATM +extern void +SetATM_Report88XX( + IN HAL_PADAPTER Adapter, + u1Byte ATM_en, + u1Byte range1_en, + u1Byte range2_en, + u1Byte range3_en, + u1Byte range4_en, + u1Byte request_period +); +#endif +void +SetAPOffload88XX( + IN HAL_PADAPTER Adapter, + u1Byte bEn, + u1Byte numOfAP, + u1Byte bHidden, + u1Byte bDenyAny, + pu1Byte loc_bcn, + pu1Byte loc_probe +); + +#ifdef AP_PS_Offlaod +void +SetAPPSOffload88XX( + IN HAL_PADAPTER Adapter, + u1Byte _PS_offload_En, + u1Byte _phase, + u1Byte _pause_Qnum_limit, + u1Byte _timeout_time +); + +void +APPSOffloadMacidPauseCtrl88XX( + IN HAL_PADAPTER Adapter, + u1Byte macid, + u1Byte setPause +); +#endif + +VOID SetSAPPS88XX +( + IN HAL_PADAPTER Adapter, + u1Byte en, + u1Byte duration +); + +VOID +SetRsvdPage88XX +( + IN IN HAL_PADAPTER Adapter, + IN pu1Byte prsp, + IN pu4Byte beaconbuf, + IN u4Byte pktLen, + IN u4Byte bigPktLen, + IN u4Byte bcnLen +); + +u4Byte +GetRsvdPageLoc88XX +( + IN IN HAL_PADAPTER Adapter, + IN u4Byte frlen, + OUT pu1Byte loc_page +); + +BOOLEAN +DownloadRsvdPage88XX +( + IN HAL_PADAPTER Adapter, + IN pu4Byte beaconbuf, + IN u4Byte beaconPktLen, + IN u1Byte bReDownload +); + +void C2HHandler88XX( + IN HAL_PADAPTER Adapter +); + +void C2HPacket88XX( + IN HAL_PADAPTER Adapter, + IN pu1Byte pBuf, + IN u2Byte length +); + +VOID +C2HEventHandler88XX +( + IN HAL_PADAPTER Adapter, + IN u1Byte c2hCmdId, + IN u2Byte c2hCmdLen, + IN pu1Byte tmpBuf +); + +VOID +C2HExtEventHandler88XX +( + IN HAL_PADAPTER Adapter, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +); + +#ifdef RTK_ATM +VOID +C2HATMReportHandler88XX +( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u2Byte CmdLen +); +#endif + +#if (BEAMFORMING_SUPPORT == 1) +VOID +C2HTxBeamformingHandler88XX( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); +#endif +#if (MU_BEAMFORMING_SUPPORT == 1) +VOID +C2HCCXRptHandler88XX( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); +#endif + +#endif //__HAL88XX_FIRMWARE_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXHWImg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.c old mode 100755 new mode 100644 index 64b9b1c48a7..7b360b4df9c --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.c @@ -1,837 +1,837 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXIsr.c - -Abstract: - Defined RTL88XX HAL common Function - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-04-30 Filen Create. ---*/ - -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../HalPrecomp.h" -#endif - -VOID -EnableIMR88XX( - IN HAL_PADAPTER Adapter -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - - RT_TRACE_F(COMP_INIT, DBG_LOUD, ("\n")); - - HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); - HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); - -#if IS_RTL88XX_MAC_V2 - if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) { - HAL_RTL_W32(REG_HIMR2, pHalData->IntMask[2]); - HAL_RTL_W32(REG_HIMR3, pHalData->IntMask[3]); - } -#endif //IS_RTL88XX_MAC_V2 - -#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { - // write AXI exception interrupt IMR - HAL_RTL_W32(REG_HSIMR, pHalData->IntMask[4]); - } -#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - -#if 0//CFG_HAL_TX_AMSDU - if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { //Do not enable FW IMR if FW does not use, REG_FTIMR do not trigger interrupt to host - HAL_RTL_W32(REG_FTIMR, HAL_RTL_R32(REG_FTIMR) | pHalData->FtIntMask); - } -#endif - - -} - - -// -// Description: -// Recognize the interrupt content by reading the interrupt register or content and masking interrupt mask (IMR) -// if it is our NIC's interrupt. After recognizing, we may clear the all interrupts (ISR). -// Arguments: -// [in] Adapter - -// The adapter context. -// [in] pContent - -// Under PCI interface, this field is ignord. -// Under USB interface, the content is the interrupt content pointer. -// Under SDIO interface, this is the interrupt type which is Local interrupt or system interrupt. -// [in] ContentLen - -// The length in byte of pContent. -// Return: -// If any interrupt matches the mask (IMR), return TRUE, and return FALSE otherwise. -// - -HAL_IMEM -BOOLEAN -InterruptRecognized88XX( - IN HAL_PADAPTER Adapter, - IN PVOID pContent, - IN u4Byte ContentLen -) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - u1Byte result; - - pHalData->IntArray_bak[0] = pHalData->IntArray[0]; - pHalData->IntArray_bak[1] = pHalData->IntArray[1]; - - pHalData->IntArray[0] = HAL_RTL_R32(REG_HISR0); - pHalData->IntArray[0] &= pHalData->IntMask[0]; - HAL_RTL_W32(REG_HISR0, pHalData->IntArray[0]); - - pHalData->IntArray[1] = HAL_RTL_R32(REG_HISR1); - pHalData->IntArray[1] &= pHalData->IntMask[1]; - HAL_RTL_W32(REG_HISR1, pHalData->IntArray[1]); - - result = (pHalData->IntArray[0]!=0 || pHalData->IntArray[1]!=0); - -#if IS_RTL88XX_MAC_V2 - if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) { - - pHalData->IntArray[2] = HAL_RTL_R32(REG_HISR2); - pHalData->IntArray[2] &= pHalData->IntMask[2]; - HAL_RTL_W32(REG_HISR2, pHalData->IntArray[2]); - - pHalData->IntArray[3] = HAL_RTL_R32(REG_HISR3); - pHalData->IntArray[3] &= pHalData->IntMask[3]; - HAL_RTL_W32(REG_HISR3, pHalData->IntArray[3]); - - result = (result || (pHalData->IntArray[2]!=0 || pHalData->IntArray[3]!=0 )); - - } -#endif // #if IS_RTL88XX_MAC_V2 - -#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { - pHalData->IntArray[4] = HAL_RTL_R32(REG_HSISR); - pHalData->IntArray[4] &= pHalData->IntMask[4]; - HAL_RTL_W32(REG_HSISR, pHalData->IntArray[4]); - } - - result = (result || (pHalData->IntArray[4]!=0)); - -#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - -#if 0 //CFG_HAL_TX_AMSDU - if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { - pHalData->FtIntArray = HAL_RTL_R32(REG_FTISR); - pHalData->FtIntArray &= pHalData->FtIntMask; - HAL_RTL_W32(REG_FTISR, pHalData->FtIntArray); - - result = (result || (pHalData->FtIntArray!=0)); - } -#endif - - return result; -} - -// -// Description: -// Check the interrupt content (read from previous process) in HAL. -// Arguments: -// [in] pAdapter - -// The adapter context pointer. -// [in] intType - -// The HAL interrupt type for querying. -// Return: -// If the corresponding interrupt content (bit) is toggled, return TRUE. -// If the input interrupt type isn't recognized or this corresponding -// hal interupt isn't toggled, return FALSE. -// Note: -// We don't perform I/O here to read interrupt such as ISR here, so the -// interrupt content shall be read before this handler. -// -HAL_IMEM -BOOLEAN -GetInterrupt88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType - ) -{ - HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); - BOOLEAN bResult = FALSE; - - switch(intType) - { - default: - // Unknown interrupt type, no need to alarm because this IC may not - // support this interrupt. - RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); - break; - - case HAL_INT_TYPE_ANY: - bResult = (pHalData->IntArray[0] || pHalData->IntArray[1]) ? TRUE : FALSE; - break; - - //4 // ========== DWORD 0 ========== - case HAL_INT_TYPE_BCNDERR0: - bResult = (pHalData->IntArray[0] & BIT_BCNDERR0) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TBDOK: - bResult = (pHalData->IntArray[0] & BIT_TXBCN0OK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TBDER: - bResult = (pHalData->IntArray[0] & BIT_TXBCN0ERR) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt: - bResult = (pHalData->IntArray[0] & BIT_BCNDMAINT0) ? TRUE : FALSE; - break; - - //TCP_ACK_ACC - case HAL_INT_TYPE_GTIMER3: - bResult = (pHalData->IntArray[0] & BIT_GTINT3) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_GTIMER4: - bResult = (pHalData->IntArray[0] & BIT_GTINT4) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_PSTIMEOUT: - bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_PSTIMEOUT1: - bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT1) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_PSTIMEOUT2: - bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT2) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_C2HCMD: - bResult = (pHalData->IntArray[0] & BIT_C2HCMD) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_VIDOK: - bResult = (pHalData->IntArray[0] & BIT_VIDOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_VODOK: - bResult = (pHalData->IntArray[0] & BIT_VODOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BEDOK: - bResult = (pHalData->IntArray[0] & BIT_BEDOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BKDOK: - bResult = (pHalData->IntArray[0] & BIT_BKDOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_MGNTDOK: - bResult = (pHalData->IntArray[0] & BIT_MGTDOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_HIGHDOK: - bResult = (pHalData->IntArray[0] & BIT_HIGHDOK) ? TRUE : FALSE; - break; - - #if 0 //Filen: removed - case HAL_INT_TYPE_BDOK: - bResult = (pHalData->IntArray[0] & IMR_BCNDOK0_88E) ? TRUE : FALSE; - break; - #endif - - case HAL_INT_TYPE_CPWM: - bResult = (pHalData->IntArray[0] & BIT_CPWM) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TSF_BIT32_TOGGLE: - bResult = (pHalData->IntArray[0] & BIT_TSF_BIT32_TOGGLE) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_RX_OK: - bResult = (pHalData->IntArray[0] & BIT_RXOK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_RDU: - bResult = (pHalData->IntArray[0] & BIT_RDU) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_CPWM2: - bResult = (pHalData->IntArray[0] & BIT_CPWM2) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_CTWEND: -#if IS_RTL88XX_MAC_V1 - if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v1) { - bResult = (pHalData->IntArray[0] & BIT_CTWEND) ? TRUE : FALSE; - } -#endif //(IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) - -#if IS_RTL88XX_MAC_V2 - if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) - { - //this interrupt is removed at 8814A - bResult = FALSE; - } -#endif // IS_RTL8192E_SERIES - break; - - //4 // ========== DWORD 1 ========== - case HAL_INT_TYPE_RXFOVW: - bResult = (pHalData->IntArray[1] & BIT_FOVW) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TXFOVW: - bResult = (pHalData->IntArray[1] & BIT_TXFOVW) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_RXERR: - bResult = (pHalData->IntArray[1] & BIT_RXERR_INT) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TXERR: - bResult = (pHalData->IntArray[1] & BIT_TXERR_INT) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt_MBSSID: - bResult = ((pHalData->IntArray[1] & (BIT_BCNDMAINT1|BIT_BCNDMAINT2|BIT_BCNDMAINT3|BIT_BCNDMAINT4| - BIT_BCNDMAINT5|BIT_BCNDMAINT6|BIT_BCNDMAINT7)) || - (pHalData->IntArray[0] & BIT_BCNDMAINT0) - ) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt1: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT1) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt2: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT2) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt3: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT3) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt4: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT4) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt5: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT5) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt6: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT6) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_BcnInt7: - bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT7) ? TRUE : FALSE; - break; - -#if CFG_HAL_SUPPORT_EACH_VAP_INT - if ( IS_SUPPORT_EACH_VAP_INT(Adapter) ) { - - case HAL_INT_TYPE_TXBCNOK_MBSSID: - bResult = ((pHalData->IntArray[2] & (BIT_TXBCN1OK|BIT_TXBCN2OK|BIT_TXBCN3OK|BIT_TXBCN4OK| - BIT_TXBCN5OK|BIT_TXBCN6OK|BIT_TXBCN7OK)) || - (pHalData->IntArray[0] & BIT_TXBCN0OK) - ) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN1OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN1OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN2OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN2OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN3OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN3OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN4OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN4OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN5OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN5OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN6OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN6OK) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN7OK: - bResult = (pHalData->IntArray[2] & BIT_TXBCN7OK) ? TRUE : FALSE; - break; - - case HAL_INT_TYPE_TXBCNERR_MBSSID: - bResult = ((pHalData->IntArray[2] & (BIT_TXBCN1ERR|BIT_TXBCN2ERR|BIT_TXBCN3ERR|BIT_TXBCN4ERR| - BIT_TXBCN5ERR|BIT_TXBCN6ERR|BIT_TXBCN7ERR)) || - (pHalData->IntArray[0] & BIT_TXBCN0ERR) - ) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN1ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN1ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN2ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN2ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN3ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN3ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN4ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN4ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN5ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN5ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN6ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN6ERR) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_TXBCN7ERR: - bResult = (pHalData->IntArray[2] & BIT_TXBCN7ERR) ? TRUE : FALSE; - break; - } -#endif // #if CFG_HAL_SUPPORT_EACH_VAP_INT - -#if CFG_HAL_HW_DETEC_POWER_STATE - if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { - - case HAL_INT_TYPE_PwrInt0: - bResult = (pHalData->IntArray[3] & BIT_PWR_INT_31to0) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_PwrInt1: - bResult = (pHalData->IntArray[3] & BIT_PWR_INT_63to32) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_PwrInt2: - bResult = (pHalData->IntArray[3] & BIT_PWR_INT_95to64) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_PwrInt3: - bResult = (pHalData->IntArray[3] & BIT_PWR_INT_126to96) ? TRUE : FALSE; - break; - case HAL_INT_TYPE_PwrInt4: - bResult = (pHalData->IntArray[3] & BIT_PWR_INT_127) ? TRUE : FALSE; - break; - } -#endif //#if CFG_HAL_HW_DETEC_POWER_STATE - - -#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { - case HAL_INT_TYPE_AXI_EXCEPTION: - bResult = (pHalData->IntArray[4] & BIT_AXI_EXCEPT_HINT) ? TRUE : FALSE; - break; - } -#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - -#if 0//CFG_HAL_TX_AMSDU - if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { - - case HAL_INT_TYPE_FS_TIMEOUT0: - bResult = (pHalData->FtIntArray & BIT_FS_PS_TIMEOUT0_EN) ? TRUE : FALSE; - break; - } -#endif - - } - - return bResult; -} - - -// TODO: Pedro, we can set several IMR combination for different scenario. Ex: 1) AP, 2) Client, 3) .... -// TODO: this can avoid to check non-necessary interrupt in __wlan_interrupt(..)... -VOID -AddInterruptMask88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType - ) -{ - HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); - - switch(intType) - { - default: - // Unknown interrupt type, no need to alarm because this IC may not - // support this interrupt. - RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); - break; - - case HAL_INT_TYPE_ANY: - pHalData->IntMask[0] = 0xFFFFFFFF; - pHalData->IntMask[1] = 0xFFFFFFFF; - break; - - //4 // ========== DWORD 0 ========== - case HAL_INT_TYPE_BCNDERR0: - pHalData->IntMask[0] |= BIT_BCNDERR0; - break; - - case HAL_INT_TYPE_TBDOK: - pHalData->IntMask[0] |= BIT_TXBCN0OK; - break; - - case HAL_INT_TYPE_TBDER: - pHalData->IntMask[0] |= BIT_TXBCN0ERR; - break; - - //TCP_ACK_ACC - case HAL_INT_TYPE_GTIMER3: - pHalData->IntMask[0] |= BIT_GTINT3; - break; - - case HAL_INT_TYPE_GTIMER4: - pHalData->IntMask[0] |= BIT_GTINT4; - break; - case HAL_INT_TYPE_BcnInt: - pHalData->IntMask[0] |= BIT_BCNDMAINT0; - break; - - case HAL_INT_TYPE_PSTIMEOUT: - pHalData->IntMask[0] |= BIT_PSTIMEOUT; - break; - - case HAL_INT_TYPE_PSTIMEOUT1: - pHalData->IntMask[0] |= BIT_PSTIMEOUT1; - break; - - case HAL_INT_TYPE_PSTIMEOUT2: - pHalData->IntMask[0] |= BIT_PSTIMEOUT2; - break; - - case HAL_INT_TYPE_C2HCMD: - pHalData->IntMask[0] |= BIT_C2HCMD; - break; - - case HAL_INT_TYPE_VIDOK: - pHalData->IntMask[0] |= BIT_VIDOK; - break; - - case HAL_INT_TYPE_VODOK: - pHalData->IntMask[0] |= BIT_VODOK; - break; - - case HAL_INT_TYPE_BEDOK: - pHalData->IntMask[0] |= BIT_BEDOK; - break; - - case HAL_INT_TYPE_BKDOK: - pHalData->IntMask[0] |= BIT_BKDOK; - break; - - case HAL_INT_TYPE_MGNTDOK: - pHalData->IntMask[0] |= BIT_MGTDOK; - break; - - case HAL_INT_TYPE_HIGHDOK: - pHalData->IntMask[0] |= BIT_HIGHDOK; - break; - - #if 0 //Filen: removed - case HAL_INT_TYPE_BDOK: - pHalData->IntMask[0] |= IMR_BCNDOK0_88E; - break; - #endif - - case HAL_INT_TYPE_CPWM: - pHalData->IntMask[0] |= BIT_CPWM; - break; - - case HAL_INT_TYPE_TSF_BIT32_TOGGLE: - pHalData->IntMask[0] |= BIT_TSF_BIT32_TOGGLE; - break; - - case HAL_INT_TYPE_RX_OK: - pHalData->IntMask[0] |= BIT_RXOK; - break; - - case HAL_INT_TYPE_RDU: - pHalData->IntMask[0] |= BIT_RDU; - break; - case HAL_INT_TYPE_CPWM2: - pHalData->IntMask[0] |= BIT_CPWM2; - break; - - //4 // ========== DWORD 1 ========== - case HAL_INT_TYPE_RXFOVW: - pHalData->IntMask[1] |= BIT_FOVW; - break; - - case HAL_INT_TYPE_TXFOVW: - pHalData->IntMask[1] |= BIT_TXFOVW; - break; - - case HAL_INT_TYPE_RXERR: - pHalData->IntMask[1] |= BIT_RXERR_INT; - break; - - case HAL_INT_TYPE_TXERR: - pHalData->IntMask[1] |= BIT_TXERR_INT; - break; - -#if CFG_HAL_HW_DETEC_POWER_STATE - if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { - - case HAL_INT_TYPE_PwrInt0: - pHalData->IntMask[3] |= BIT_PWR_INT_31to0; - break; - case HAL_INT_TYPE_PwrInt1: - pHalData->IntMask[3] |= BIT_PWR_INT_63to32; - break; - case HAL_INT_TYPE_PwrInt2: - pHalData->IntMask[3] |= BIT_PWR_INT_95to64; - break; - case HAL_INT_TYPE_PwrInt3: - pHalData->IntMask[3] |= BIT_PWR_INT_126to96; - break; - case HAL_INT_TYPE_PwrInt4: - pHalData->IntMask[3] |= BIT_PWR_INT_127; - break; - } -#endif // #if CFG_HAL_HW_DETEC_POWER_STATE - -#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { - case HAL_INT_TYPE_AXI_EXCEPTION: - pHalData->IntMask[4] |= BIT_AXI_EXCEPT_HINT; - break; - } -#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - -#if 0//CFG_HAL_TX_AMSDU - if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { - - case HAL_INT_TYPE_FS_TIMEOUT0: - pHalData->FtIntArray |= BIT_FS_PS_TIMEOUT0_EN; - break; - } -#endif - } -} - - -VOID -RemoveInterruptMask88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType - ) -{ - HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); - - switch(intType) - { - default: - // Unknown interrupt type, no need to alarm because this IC may not - // support this interrupt. - RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); - break; - - case HAL_INT_TYPE_ANY: - pHalData->IntMask[0] &= ~0xFFFFFFFF; - pHalData->IntMask[1] &= ~0xFFFFFFFF; - break; - - //4 // ========== DWORD 0 ========== - case HAL_INT_TYPE_BCNDERR0: - pHalData->IntMask[0] &= ~BIT_BCNDERR0; - break; - - case HAL_INT_TYPE_TBDOK: - pHalData->IntMask[0] &= ~BIT_TXBCN0OK; - break; - - case HAL_INT_TYPE_TBDER: - pHalData->IntMask[0] &= ~BIT_TXBCN0ERR; - break; - - //TCP_ACK_ACC - case HAL_INT_TYPE_GTIMER3: - pHalData->IntMask[0] &= ~BIT_GTINT3; - break; - - case HAL_INT_TYPE_GTIMER4: - pHalData->IntMask[0] &= ~BIT_GTINT4; - break; - case HAL_INT_TYPE_BcnInt: - pHalData->IntMask[0] &= ~BIT_BCNDMAINT0; - break; - - case HAL_INT_TYPE_PSTIMEOUT: - pHalData->IntMask[0] &= ~BIT_PSTIMEOUT; - break; - - case HAL_INT_TYPE_PSTIMEOUT1: - pHalData->IntMask[0] &= ~BIT_PSTIMEOUT1; - break; - - case HAL_INT_TYPE_PSTIMEOUT2: - pHalData->IntMask[0] &= ~BIT_PSTIMEOUT2; - break; - - case HAL_INT_TYPE_C2HCMD: - pHalData->IntMask[0] &= ~BIT_C2HCMD; - break; - - case HAL_INT_TYPE_VIDOK: - pHalData->IntMask[0] &= ~BIT_VIDOK; - break; - - case HAL_INT_TYPE_VODOK: - pHalData->IntMask[0] &= ~BIT_VODOK; - break; - - case HAL_INT_TYPE_BEDOK: - pHalData->IntMask[0] &= ~BIT_BEDOK; - break; - - case HAL_INT_TYPE_BKDOK: - pHalData->IntMask[0] &= ~BIT_BKDOK; - break; - - case HAL_INT_TYPE_MGNTDOK: - pHalData->IntMask[0] &= ~BIT_MGTDOK; - break; - - case HAL_INT_TYPE_HIGHDOK: - pHalData->IntMask[0] &= ~BIT_HIGHDOK; - break; - - #if 0 //Filen: removed - case HAL_INT_TYPE_BDOK: - pHalData->IntMask[0] &= ~IMR_BCNDOK0_88E; - break; - #endif - - case HAL_INT_TYPE_CPWM: - pHalData->IntMask[0] &= ~BIT_CPWM; - break; - - case HAL_INT_TYPE_TSF_BIT32_TOGGLE: - pHalData->IntMask[0] &= ~BIT_TSF_BIT32_TOGGLE; - break; - - case HAL_INT_TYPE_RX_OK: - pHalData->IntMask[0] &= ~BIT_RXOK; - break; - - case HAL_INT_TYPE_RDU: - pHalData->IntMask[0] &= ~BIT_RDU; - break; - case HAL_INT_TYPE_CPWM2: - pHalData->IntMask[0] &= ~BIT_CPWM2; - break; - - //4 // ========== DWORD 1 ========== - case HAL_INT_TYPE_RXFOVW: - pHalData->IntMask[1] &= ~BIT_FOVW; - break; - - case HAL_INT_TYPE_TXFOVW: - pHalData->IntMask[1] &= ~BIT_TXFOVW; - break; - - case HAL_INT_TYPE_RXERR: - pHalData->IntMask[1] &= ~BIT_RXERR_INT; - break; - - case HAL_INT_TYPE_TXERR: - pHalData->IntMask[1] &= ~BIT_TXERR_INT; - break; - -#if CFG_HAL_HW_DETEC_POWER_STATE - if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { - - case HAL_INT_TYPE_PwrInt0: - pHalData->IntMask[3] &= ~BIT_PWR_INT_31to0; - break; - case HAL_INT_TYPE_PwrInt1: - pHalData->IntMask[3] &= ~BIT_PWR_INT_63to32; - break; - case HAL_INT_TYPE_PwrInt2: - pHalData->IntMask[3] &= ~BIT_PWR_INT_95to64; - break; - case HAL_INT_TYPE_PwrInt3: - pHalData->IntMask[3] &= ~BIT_PWR_INT_126to96; - break; - case HAL_INT_TYPE_PwrInt4: - pHalData->IntMask[3] &= ~BIT_PWR_INT_127; - break; - } -#endif // #if CFG_HAL_HW_DETEC_POWER_STATE - -#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { - case HAL_INT_TYPE_AXI_EXCEPTION: - pHalData->IntMask[4] &= ~BIT_AXI_EXCEPT_HINT; - break; - } -#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION - -#if 0//CFG_HAL_TX_AMSDU - if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { - - - case HAL_INT_TYPE_FS_TIMEOUT0: - pHalData->FtIntArray &= ~BIT_FS_PS_TIMEOUT0_EN; - break; - } -#endif - - } -} - - -HAL_IMEM -VOID -DisableRxRelatedInterrupt88XX( - IN HAL_PADAPTER Adapter - ) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - HAL_PADAPTER priv = Adapter; - ULONG flags; - -#if 0 - HAL_SAVE_INT_AND_CLI(flags); - - pHalData->IntMask_RxINTBackup[0] = pHalData->IntMask[0]; - pHalData->IntMask_RxINTBackup[1] = pHalData->IntMask[1]; - - pHalData->IntMask[0] &= ~BIT_RXOK; - pHalData->IntMask[1] &= ~BIT_FOVW; - - HAL_RESTORE_INT(flags); - - HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); - HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); -#else - HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0] & ~ (BIT_RXOK | BIT_RDU)); - HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1] & ~BIT_FOVW); -#endif - -} - -HAL_IMEM -VOID -EnableRxRelatedInterrupt88XX( - IN HAL_PADAPTER Adapter - ) -{ - PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); - HAL_PADAPTER priv = Adapter; - ULONG flags; - -#if 0 - HAL_SAVE_INT_AND_CLI(flags); - - pHalData->IntMask[0] = pHalData->IntMask_RxINTBackup[0]; - pHalData->IntMask[1] = pHalData->IntMask_RxINTBackup[1]; - - HAL_RESTORE_INT(flags); -#endif - HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); - HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); - -} - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXIsr.c + +Abstract: + Defined RTL88XX HAL common Function + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-04-30 Filen Create. +--*/ + +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../HalPrecomp.h" +#endif + +VOID +EnableIMR88XX( + IN HAL_PADAPTER Adapter +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + + RT_TRACE_F(COMP_INIT, DBG_LOUD, ("\n")); + + HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); + HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); + +#if IS_RTL88XX_MAC_V2 + if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) { + HAL_RTL_W32(REG_HIMR2, pHalData->IntMask[2]); + HAL_RTL_W32(REG_HIMR3, pHalData->IntMask[3]); + } +#endif //IS_RTL88XX_MAC_V2 + +#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { + // write AXI exception interrupt IMR + HAL_RTL_W32(REG_HSIMR, pHalData->IntMask[4]); + } +#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + +#if 0//CFG_HAL_TX_AMSDU + if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { //Do not enable FW IMR if FW does not use, REG_FTIMR do not trigger interrupt to host + HAL_RTL_W32(REG_FTIMR, HAL_RTL_R32(REG_FTIMR) | pHalData->FtIntMask); + } +#endif + + +} + + +// +// Description: +// Recognize the interrupt content by reading the interrupt register or content and masking interrupt mask (IMR) +// if it is our NIC's interrupt. After recognizing, we may clear the all interrupts (ISR). +// Arguments: +// [in] Adapter - +// The adapter context. +// [in] pContent - +// Under PCI interface, this field is ignord. +// Under USB interface, the content is the interrupt content pointer. +// Under SDIO interface, this is the interrupt type which is Local interrupt or system interrupt. +// [in] ContentLen - +// The length in byte of pContent. +// Return: +// If any interrupt matches the mask (IMR), return TRUE, and return FALSE otherwise. +// + +HAL_IMEM +BOOLEAN +InterruptRecognized88XX( + IN HAL_PADAPTER Adapter, + IN PVOID pContent, + IN u4Byte ContentLen +) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + u1Byte result; + + pHalData->IntArray_bak[0] = pHalData->IntArray[0]; + pHalData->IntArray_bak[1] = pHalData->IntArray[1]; + + pHalData->IntArray[0] = HAL_RTL_R32(REG_HISR0); + pHalData->IntArray[0] &= pHalData->IntMask[0]; + HAL_RTL_W32(REG_HISR0, pHalData->IntArray[0]); + + pHalData->IntArray[1] = HAL_RTL_R32(REG_HISR1); + pHalData->IntArray[1] &= pHalData->IntMask[1]; + HAL_RTL_W32(REG_HISR1, pHalData->IntArray[1]); + + result = (pHalData->IntArray[0]!=0 || pHalData->IntArray[1]!=0); + +#if IS_RTL88XX_MAC_V2 + if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) { + + pHalData->IntArray[2] = HAL_RTL_R32(REG_HISR2); + pHalData->IntArray[2] &= pHalData->IntMask[2]; + HAL_RTL_W32(REG_HISR2, pHalData->IntArray[2]); + + pHalData->IntArray[3] = HAL_RTL_R32(REG_HISR3); + pHalData->IntArray[3] &= pHalData->IntMask[3]; + HAL_RTL_W32(REG_HISR3, pHalData->IntArray[3]); + + result = (result || (pHalData->IntArray[2]!=0 || pHalData->IntArray[3]!=0 )); + + } +#endif // #if IS_RTL88XX_MAC_V2 + +#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { + pHalData->IntArray[4] = HAL_RTL_R32(REG_HSISR); + pHalData->IntArray[4] &= pHalData->IntMask[4]; + HAL_RTL_W32(REG_HSISR, pHalData->IntArray[4]); + } + + result = (result || (pHalData->IntArray[4]!=0)); + +#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + +#if 0 //CFG_HAL_TX_AMSDU + if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { + pHalData->FtIntArray = HAL_RTL_R32(REG_FTISR); + pHalData->FtIntArray &= pHalData->FtIntMask; + HAL_RTL_W32(REG_FTISR, pHalData->FtIntArray); + + result = (result || (pHalData->FtIntArray!=0)); + } +#endif + + return result; +} + +// +// Description: +// Check the interrupt content (read from previous process) in HAL. +// Arguments: +// [in] pAdapter - +// The adapter context pointer. +// [in] intType - +// The HAL interrupt type for querying. +// Return: +// If the corresponding interrupt content (bit) is toggled, return TRUE. +// If the input interrupt type isn't recognized or this corresponding +// hal interupt isn't toggled, return FALSE. +// Note: +// We don't perform I/O here to read interrupt such as ISR here, so the +// interrupt content shall be read before this handler. +// +HAL_IMEM +BOOLEAN +GetInterrupt88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType + ) +{ + HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); + BOOLEAN bResult = FALSE; + + switch(intType) + { + default: + // Unknown interrupt type, no need to alarm because this IC may not + // support this interrupt. + RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); + break; + + case HAL_INT_TYPE_ANY: + bResult = (pHalData->IntArray[0] || pHalData->IntArray[1]) ? TRUE : FALSE; + break; + + //4 // ========== DWORD 0 ========== + case HAL_INT_TYPE_BCNDERR0: + bResult = (pHalData->IntArray[0] & BIT_BCNDERR0) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TBDOK: + bResult = (pHalData->IntArray[0] & BIT_TXBCN0OK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TBDER: + bResult = (pHalData->IntArray[0] & BIT_TXBCN0ERR) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt: + bResult = (pHalData->IntArray[0] & BIT_BCNDMAINT0) ? TRUE : FALSE; + break; + + //TCP_ACK_ACC + case HAL_INT_TYPE_GTIMER3: + bResult = (pHalData->IntArray[0] & BIT_GTINT3) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_GTIMER4: + bResult = (pHalData->IntArray[0] & BIT_GTINT4) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_PSTIMEOUT: + bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_PSTIMEOUT1: + bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT1) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_PSTIMEOUT2: + bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT2) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_C2HCMD: + bResult = (pHalData->IntArray[0] & BIT_C2HCMD) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_VIDOK: + bResult = (pHalData->IntArray[0] & BIT_VIDOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_VODOK: + bResult = (pHalData->IntArray[0] & BIT_VODOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BEDOK: + bResult = (pHalData->IntArray[0] & BIT_BEDOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BKDOK: + bResult = (pHalData->IntArray[0] & BIT_BKDOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_MGNTDOK: + bResult = (pHalData->IntArray[0] & BIT_MGTDOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_HIGHDOK: + bResult = (pHalData->IntArray[0] & BIT_HIGHDOK) ? TRUE : FALSE; + break; + + #if 0 //Filen: removed + case HAL_INT_TYPE_BDOK: + bResult = (pHalData->IntArray[0] & IMR_BCNDOK0_88E) ? TRUE : FALSE; + break; + #endif + + case HAL_INT_TYPE_CPWM: + bResult = (pHalData->IntArray[0] & BIT_CPWM) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TSF_BIT32_TOGGLE: + bResult = (pHalData->IntArray[0] & BIT_TSF_BIT32_TOGGLE) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_RX_OK: + bResult = (pHalData->IntArray[0] & BIT_RXOK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_RDU: + bResult = (pHalData->IntArray[0] & BIT_RDU) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_CPWM2: + bResult = (pHalData->IntArray[0] & BIT_CPWM2) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_CTWEND: +#if IS_RTL88XX_MAC_V1 + if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v1) { + bResult = (pHalData->IntArray[0] & BIT_CTWEND) ? TRUE : FALSE; + } +#endif //(IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) + +#if IS_RTL88XX_MAC_V2 + if ( _GET_HAL_DATA(Adapter)->MacVersion.is_MAC_v2) + { + //this interrupt is removed at 8814A + bResult = FALSE; + } +#endif // IS_RTL8192E_SERIES + break; + + //4 // ========== DWORD 1 ========== + case HAL_INT_TYPE_RXFOVW: + bResult = (pHalData->IntArray[1] & BIT_FOVW) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TXFOVW: + bResult = (pHalData->IntArray[1] & BIT_TXFOVW) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_RXERR: + bResult = (pHalData->IntArray[1] & BIT_RXERR_INT) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TXERR: + bResult = (pHalData->IntArray[1] & BIT_TXERR_INT) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt_MBSSID: + bResult = ((pHalData->IntArray[1] & (BIT_BCNDMAINT1|BIT_BCNDMAINT2|BIT_BCNDMAINT3|BIT_BCNDMAINT4| + BIT_BCNDMAINT5|BIT_BCNDMAINT6|BIT_BCNDMAINT7)) || + (pHalData->IntArray[0] & BIT_BCNDMAINT0) + ) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt1: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT1) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt2: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT2) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt3: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT3) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt4: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT4) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt5: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT5) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt6: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT6) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_BcnInt7: + bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT7) ? TRUE : FALSE; + break; + +#if CFG_HAL_SUPPORT_EACH_VAP_INT + if ( IS_SUPPORT_EACH_VAP_INT(Adapter) ) { + + case HAL_INT_TYPE_TXBCNOK_MBSSID: + bResult = ((pHalData->IntArray[2] & (BIT_TXBCN1OK|BIT_TXBCN2OK|BIT_TXBCN3OK|BIT_TXBCN4OK| + BIT_TXBCN5OK|BIT_TXBCN6OK|BIT_TXBCN7OK)) || + (pHalData->IntArray[0] & BIT_TXBCN0OK) + ) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN1OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN1OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN2OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN2OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN3OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN3OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN4OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN4OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN5OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN5OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN6OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN6OK) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN7OK: + bResult = (pHalData->IntArray[2] & BIT_TXBCN7OK) ? TRUE : FALSE; + break; + + case HAL_INT_TYPE_TXBCNERR_MBSSID: + bResult = ((pHalData->IntArray[2] & (BIT_TXBCN1ERR|BIT_TXBCN2ERR|BIT_TXBCN3ERR|BIT_TXBCN4ERR| + BIT_TXBCN5ERR|BIT_TXBCN6ERR|BIT_TXBCN7ERR)) || + (pHalData->IntArray[0] & BIT_TXBCN0ERR) + ) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN1ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN1ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN2ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN2ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN3ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN3ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN4ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN4ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN5ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN5ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN6ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN6ERR) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_TXBCN7ERR: + bResult = (pHalData->IntArray[2] & BIT_TXBCN7ERR) ? TRUE : FALSE; + break; + } +#endif // #if CFG_HAL_SUPPORT_EACH_VAP_INT + +#if CFG_HAL_HW_DETEC_POWER_STATE + if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { + + case HAL_INT_TYPE_PwrInt0: + bResult = (pHalData->IntArray[3] & BIT_PWR_INT_31to0) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_PwrInt1: + bResult = (pHalData->IntArray[3] & BIT_PWR_INT_63to32) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_PwrInt2: + bResult = (pHalData->IntArray[3] & BIT_PWR_INT_95to64) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_PwrInt3: + bResult = (pHalData->IntArray[3] & BIT_PWR_INT_126to96) ? TRUE : FALSE; + break; + case HAL_INT_TYPE_PwrInt4: + bResult = (pHalData->IntArray[3] & BIT_PWR_INT_127) ? TRUE : FALSE; + break; + } +#endif //#if CFG_HAL_HW_DETEC_POWER_STATE + + +#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { + case HAL_INT_TYPE_AXI_EXCEPTION: + bResult = (pHalData->IntArray[4] & BIT_AXI_EXCEPT_HINT) ? TRUE : FALSE; + break; + } +#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + +#if 0//CFG_HAL_TX_AMSDU + if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { + + case HAL_INT_TYPE_FS_TIMEOUT0: + bResult = (pHalData->FtIntArray & BIT_FS_PS_TIMEOUT0_EN) ? TRUE : FALSE; + break; + } +#endif + + } + + return bResult; +} + + +// TODO: Pedro, we can set several IMR combination for different scenario. Ex: 1) AP, 2) Client, 3) .... +// TODO: this can avoid to check non-necessary interrupt in __wlan_interrupt(..)... +VOID +AddInterruptMask88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType + ) +{ + HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); + + switch(intType) + { + default: + // Unknown interrupt type, no need to alarm because this IC may not + // support this interrupt. + RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); + break; + + case HAL_INT_TYPE_ANY: + pHalData->IntMask[0] = 0xFFFFFFFF; + pHalData->IntMask[1] = 0xFFFFFFFF; + break; + + //4 // ========== DWORD 0 ========== + case HAL_INT_TYPE_BCNDERR0: + pHalData->IntMask[0] |= BIT_BCNDERR0; + break; + + case HAL_INT_TYPE_TBDOK: + pHalData->IntMask[0] |= BIT_TXBCN0OK; + break; + + case HAL_INT_TYPE_TBDER: + pHalData->IntMask[0] |= BIT_TXBCN0ERR; + break; + + //TCP_ACK_ACC + case HAL_INT_TYPE_GTIMER3: + pHalData->IntMask[0] |= BIT_GTINT3; + break; + + case HAL_INT_TYPE_GTIMER4: + pHalData->IntMask[0] |= BIT_GTINT4; + break; + case HAL_INT_TYPE_BcnInt: + pHalData->IntMask[0] |= BIT_BCNDMAINT0; + break; + + case HAL_INT_TYPE_PSTIMEOUT: + pHalData->IntMask[0] |= BIT_PSTIMEOUT; + break; + + case HAL_INT_TYPE_PSTIMEOUT1: + pHalData->IntMask[0] |= BIT_PSTIMEOUT1; + break; + + case HAL_INT_TYPE_PSTIMEOUT2: + pHalData->IntMask[0] |= BIT_PSTIMEOUT2; + break; + + case HAL_INT_TYPE_C2HCMD: + pHalData->IntMask[0] |= BIT_C2HCMD; + break; + + case HAL_INT_TYPE_VIDOK: + pHalData->IntMask[0] |= BIT_VIDOK; + break; + + case HAL_INT_TYPE_VODOK: + pHalData->IntMask[0] |= BIT_VODOK; + break; + + case HAL_INT_TYPE_BEDOK: + pHalData->IntMask[0] |= BIT_BEDOK; + break; + + case HAL_INT_TYPE_BKDOK: + pHalData->IntMask[0] |= BIT_BKDOK; + break; + + case HAL_INT_TYPE_MGNTDOK: + pHalData->IntMask[0] |= BIT_MGTDOK; + break; + + case HAL_INT_TYPE_HIGHDOK: + pHalData->IntMask[0] |= BIT_HIGHDOK; + break; + + #if 0 //Filen: removed + case HAL_INT_TYPE_BDOK: + pHalData->IntMask[0] |= IMR_BCNDOK0_88E; + break; + #endif + + case HAL_INT_TYPE_CPWM: + pHalData->IntMask[0] |= BIT_CPWM; + break; + + case HAL_INT_TYPE_TSF_BIT32_TOGGLE: + pHalData->IntMask[0] |= BIT_TSF_BIT32_TOGGLE; + break; + + case HAL_INT_TYPE_RX_OK: + pHalData->IntMask[0] |= BIT_RXOK; + break; + + case HAL_INT_TYPE_RDU: + pHalData->IntMask[0] |= BIT_RDU; + break; + case HAL_INT_TYPE_CPWM2: + pHalData->IntMask[0] |= BIT_CPWM2; + break; + + //4 // ========== DWORD 1 ========== + case HAL_INT_TYPE_RXFOVW: + pHalData->IntMask[1] |= BIT_FOVW; + break; + + case HAL_INT_TYPE_TXFOVW: + pHalData->IntMask[1] |= BIT_TXFOVW; + break; + + case HAL_INT_TYPE_RXERR: + pHalData->IntMask[1] |= BIT_RXERR_INT; + break; + + case HAL_INT_TYPE_TXERR: + pHalData->IntMask[1] |= BIT_TXERR_INT; + break; + +#if CFG_HAL_HW_DETEC_POWER_STATE + if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { + + case HAL_INT_TYPE_PwrInt0: + pHalData->IntMask[3] |= BIT_PWR_INT_31to0; + break; + case HAL_INT_TYPE_PwrInt1: + pHalData->IntMask[3] |= BIT_PWR_INT_63to32; + break; + case HAL_INT_TYPE_PwrInt2: + pHalData->IntMask[3] |= BIT_PWR_INT_95to64; + break; + case HAL_INT_TYPE_PwrInt3: + pHalData->IntMask[3] |= BIT_PWR_INT_126to96; + break; + case HAL_INT_TYPE_PwrInt4: + pHalData->IntMask[3] |= BIT_PWR_INT_127; + break; + } +#endif // #if CFG_HAL_HW_DETEC_POWER_STATE + +#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { + case HAL_INT_TYPE_AXI_EXCEPTION: + pHalData->IntMask[4] |= BIT_AXI_EXCEPT_HINT; + break; + } +#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + +#if 0//CFG_HAL_TX_AMSDU + if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { + + case HAL_INT_TYPE_FS_TIMEOUT0: + pHalData->FtIntArray |= BIT_FS_PS_TIMEOUT0_EN; + break; + } +#endif + } +} + + +VOID +RemoveInterruptMask88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType + ) +{ + HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter); + + switch(intType) + { + default: + // Unknown interrupt type, no need to alarm because this IC may not + // support this interrupt. + RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType)); + break; + + case HAL_INT_TYPE_ANY: + pHalData->IntMask[0] &= ~0xFFFFFFFF; + pHalData->IntMask[1] &= ~0xFFFFFFFF; + break; + + //4 // ========== DWORD 0 ========== + case HAL_INT_TYPE_BCNDERR0: + pHalData->IntMask[0] &= ~BIT_BCNDERR0; + break; + + case HAL_INT_TYPE_TBDOK: + pHalData->IntMask[0] &= ~BIT_TXBCN0OK; + break; + + case HAL_INT_TYPE_TBDER: + pHalData->IntMask[0] &= ~BIT_TXBCN0ERR; + break; + + //TCP_ACK_ACC + case HAL_INT_TYPE_GTIMER3: + pHalData->IntMask[0] &= ~BIT_GTINT3; + break; + + case HAL_INT_TYPE_GTIMER4: + pHalData->IntMask[0] &= ~BIT_GTINT4; + break; + case HAL_INT_TYPE_BcnInt: + pHalData->IntMask[0] &= ~BIT_BCNDMAINT0; + break; + + case HAL_INT_TYPE_PSTIMEOUT: + pHalData->IntMask[0] &= ~BIT_PSTIMEOUT; + break; + + case HAL_INT_TYPE_PSTIMEOUT1: + pHalData->IntMask[0] &= ~BIT_PSTIMEOUT1; + break; + + case HAL_INT_TYPE_PSTIMEOUT2: + pHalData->IntMask[0] &= ~BIT_PSTIMEOUT2; + break; + + case HAL_INT_TYPE_C2HCMD: + pHalData->IntMask[0] &= ~BIT_C2HCMD; + break; + + case HAL_INT_TYPE_VIDOK: + pHalData->IntMask[0] &= ~BIT_VIDOK; + break; + + case HAL_INT_TYPE_VODOK: + pHalData->IntMask[0] &= ~BIT_VODOK; + break; + + case HAL_INT_TYPE_BEDOK: + pHalData->IntMask[0] &= ~BIT_BEDOK; + break; + + case HAL_INT_TYPE_BKDOK: + pHalData->IntMask[0] &= ~BIT_BKDOK; + break; + + case HAL_INT_TYPE_MGNTDOK: + pHalData->IntMask[0] &= ~BIT_MGTDOK; + break; + + case HAL_INT_TYPE_HIGHDOK: + pHalData->IntMask[0] &= ~BIT_HIGHDOK; + break; + + #if 0 //Filen: removed + case HAL_INT_TYPE_BDOK: + pHalData->IntMask[0] &= ~IMR_BCNDOK0_88E; + break; + #endif + + case HAL_INT_TYPE_CPWM: + pHalData->IntMask[0] &= ~BIT_CPWM; + break; + + case HAL_INT_TYPE_TSF_BIT32_TOGGLE: + pHalData->IntMask[0] &= ~BIT_TSF_BIT32_TOGGLE; + break; + + case HAL_INT_TYPE_RX_OK: + pHalData->IntMask[0] &= ~BIT_RXOK; + break; + + case HAL_INT_TYPE_RDU: + pHalData->IntMask[0] &= ~BIT_RDU; + break; + case HAL_INT_TYPE_CPWM2: + pHalData->IntMask[0] &= ~BIT_CPWM2; + break; + + //4 // ========== DWORD 1 ========== + case HAL_INT_TYPE_RXFOVW: + pHalData->IntMask[1] &= ~BIT_FOVW; + break; + + case HAL_INT_TYPE_TXFOVW: + pHalData->IntMask[1] &= ~BIT_TXFOVW; + break; + + case HAL_INT_TYPE_RXERR: + pHalData->IntMask[1] &= ~BIT_RXERR_INT; + break; + + case HAL_INT_TYPE_TXERR: + pHalData->IntMask[1] &= ~BIT_TXERR_INT; + break; + +#if CFG_HAL_HW_DETEC_POWER_STATE + if ( IS_SUPPORT_HW_DETEC_POWER_STATE(Adapter)) { + + case HAL_INT_TYPE_PwrInt0: + pHalData->IntMask[3] &= ~BIT_PWR_INT_31to0; + break; + case HAL_INT_TYPE_PwrInt1: + pHalData->IntMask[3] &= ~BIT_PWR_INT_63to32; + break; + case HAL_INT_TYPE_PwrInt2: + pHalData->IntMask[3] &= ~BIT_PWR_INT_95to64; + break; + case HAL_INT_TYPE_PwrInt3: + pHalData->IntMask[3] &= ~BIT_PWR_INT_126to96; + break; + case HAL_INT_TYPE_PwrInt4: + pHalData->IntMask[3] &= ~BIT_PWR_INT_127; + break; + } +#endif // #if CFG_HAL_HW_DETEC_POWER_STATE + +#if CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + if(IS_SUPPORT_AXI_EXCEPTION(Adapter)) { + case HAL_INT_TYPE_AXI_EXCEPTION: + pHalData->IntMask[4] &= ~BIT_AXI_EXCEPT_HINT; + break; + } +#endif // CFG_HAL_SUPPORT_AXI_BUS_EXCEPTION + +#if 0//CFG_HAL_TX_AMSDU + if ( IS_SUPPORT_TX_AMSDU(Adapter) ) { + + + case HAL_INT_TYPE_FS_TIMEOUT0: + pHalData->FtIntArray &= ~BIT_FS_PS_TIMEOUT0_EN; + break; + } +#endif + + } +} + + +HAL_IMEM +VOID +DisableRxRelatedInterrupt88XX( + IN HAL_PADAPTER Adapter + ) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + HAL_PADAPTER priv = Adapter; + ULONG flags; + +#if 0 + HAL_SAVE_INT_AND_CLI(flags); + + pHalData->IntMask_RxINTBackup[0] = pHalData->IntMask[0]; + pHalData->IntMask_RxINTBackup[1] = pHalData->IntMask[1]; + + pHalData->IntMask[0] &= ~BIT_RXOK; + pHalData->IntMask[1] &= ~BIT_FOVW; + + HAL_RESTORE_INT(flags); + + HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); + HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); +#else + HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0] & ~ (BIT_RXOK | BIT_RDU)); + HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1] & ~BIT_FOVW); +#endif + +} + +HAL_IMEM +VOID +EnableRxRelatedInterrupt88XX( + IN HAL_PADAPTER Adapter + ) +{ + PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter); + HAL_PADAPTER priv = Adapter; + ULONG flags; + +#if 0 + HAL_SAVE_INT_AND_CLI(flags); + + pHalData->IntMask[0] = pHalData->IntMask_RxINTBackup[0]; + pHalData->IntMask[1] = pHalData->IntMask_RxINTBackup[1]; + + HAL_RESTORE_INT(flags); +#endif + HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]); + HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]); + +} + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.h old mode 100755 new mode 100644 index 7e6854785f2..fd167fecb81 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXIsr.h @@ -1,88 +1,88 @@ -#ifndef __HAL88XX_ISR_H__ -#define __HAL88XX_ISR_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXIsr.h - -Abstract: - Defined HAL 88XX Interrupt Service Routine Related Define & Marco - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-04-30 Filen Create. ---*/ - - - - - - - - - - - - -VOID -EnableIMR88XX( - IN HAL_PADAPTER Adapter -); - -HAL_IMEM -BOOLEAN -InterruptRecognized88XX( - IN HAL_PADAPTER Adapter, - IN PVOID pContent, - IN u4Byte ContentLen -); - -HAL_IMEM -BOOLEAN -GetInterrupt88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType -); - - -VOID -AddInterruptMask88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType -); - - -VOID -RemoveInterruptMask88XX( - IN HAL_PADAPTER Adapter, - IN HAL_INT_TYPE intType -); - -HAL_IMEM -VOID -DisableRxRelatedInterrupt88XX( - IN HAL_PADAPTER Adapter - ); - -HAL_IMEM -VOID -EnableRxRelatedInterrupt88XX( - IN HAL_PADAPTER Adapter - ); - - - - - - - - - - - - - -#endif //__HAL88XX_ISR_H__ +#ifndef __HAL88XX_ISR_H__ +#define __HAL88XX_ISR_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXIsr.h + +Abstract: + Defined HAL 88XX Interrupt Service Routine Related Define & Marco + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-04-30 Filen Create. +--*/ + + + + + + + + + + + + +VOID +EnableIMR88XX( + IN HAL_PADAPTER Adapter +); + +HAL_IMEM +BOOLEAN +InterruptRecognized88XX( + IN HAL_PADAPTER Adapter, + IN PVOID pContent, + IN u4Byte ContentLen +); + +HAL_IMEM +BOOLEAN +GetInterrupt88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType +); + + +VOID +AddInterruptMask88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType +); + + +VOID +RemoveInterruptMask88XX( + IN HAL_PADAPTER Adapter, + IN HAL_INT_TYPE intType +); + +HAL_IMEM +VOID +DisableRxRelatedInterrupt88XX( + IN HAL_PADAPTER Adapter + ); + +HAL_IMEM +VOID +EnableRxRelatedInterrupt88XX( + IN HAL_PADAPTER Adapter + ); + + + + + + + + + + + + + +#endif //__HAL88XX_ISR_H__ diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.c old mode 100755 new mode 100644 index 193fdbf80e2..30854459be3 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.c @@ -1,5383 +1,5383 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXPhyCfg.c - -Abstract: - Defined HAL 88XX PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ - -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../HalPrecomp.h" -#endif - - -#ifdef TXPWR_LMT - -void HAL_get_tx_pwr(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, - unsigned char *tmp_b3, unsigned char *tmp_b4) -{ - *tmp_b1 = (tmp_dw & (0xff)); - *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); - *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); - *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); -} - - -unsigned char HAL_get_byte_from_dw(unsigned int tmp_dw, unsigned char byte_num) -{ - - if (byte_num == 0) - return (tmp_dw & (0xff)); - else if (byte_num == 1) - return ((tmp_dw & (0xff00)) >> 8); - else if (byte_num == 2) - return ((tmp_dw & (0xff0000)) >> 16); - else if (byte_num == 3) - return ((tmp_dw & (0xff000000)) >> 24); - else - return 0; -} - -unsigned int HAL_assign_lmt_reg_value(IN HAL_PADAPTER Adapter, unsigned int reg_offset, unsigned char max_idx, unsigned char max_idx2) -{ - - unsigned int tmp_dw; - unsigned char reg_val[4]; - unsigned char i = 0; - - tmp_dw = HAL_RTL_R32(reg_offset); - - //printk("[0x%03x] 0x%08x >> ", reg_offset, tmp_dw); - - HAL_get_tx_pwr(tmp_dw, (unsigned char *)®_val[0], (unsigned char *)®_val[1], - (unsigned char *)®_val[2], (unsigned char *)®_val[3]); - -#if IS_RTL88XX_N - if (reg_offset == REG_BB_TXAGC_A_CCK1_MCS32_N) { - reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); - } else if (reg_offset == REG_BB_TXAGC_B_CCK5_1_MCS32_N) { - reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); - reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx)); - reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx)); - } else if (reg_offset == REG_BB_TXAGC_A_CCK11_2_B_CCK11_N) { - //if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - reg_val[0] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[0], max_idx2)); - reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); - reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx)); - reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx)); - } else -#endif -#if IS_RTL88XX_AC - if ((reg_offset == REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC) || - (reg_offset == REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC)) { - reg_val[0] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[0], max_idx)); - reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); - reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx2)); - reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx2)); - } else -#endif - { - for (i = 0; i < 4; i++) { - reg_val[i] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[i], max_idx)); - } - } - - tmp_dw = (reg_val[3] << 24) | (reg_val[2] << 16) | (reg_val[1] << 8) | reg_val[0]; - - //printk("0x%08x\n", tmp_dw); - - HAL_RTL_W32(reg_offset, tmp_dw); - -} - -unsigned char HAL_check_lmt_valid(IN HAL_PADAPTER Adapter, unsigned char phy_band) -{ - unsigned char lmt_valid = 1; - - if (phy_band == PHY_BAND_2G) - if (Adapter->pshare->txpwr_lmt_CCK == 0) - lmt_valid = 0; - - if (Adapter->pshare->txpwr_lmt_OFDM == 0) - lmt_valid = 0; - - if (Adapter->pshare->txpwr_lmt_HT1S == 0) - lmt_valid = 0; - - if (Adapter->pshare->txpwr_lmt_HT2S == 0) - lmt_valid = 0; - -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - if(Adapter->pshare->txpwr_lmt_HT3S == 0) - lmt_valid = 0; - } -#endif - - - if (phy_band == PHY_BAND_5G) { - if (Adapter->pshare->txpwr_lmt_VHT1S == 0) - lmt_valid = 0; - - if (Adapter->pshare->txpwr_lmt_VHT2S == 0) - lmt_valid = 0; -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - if(Adapter->pshare->txpwr_lmt_VHT3S == 0) - lmt_valid = 0; - } -#endif - } -#if 1 - - if ((Adapter->pmib->dot11StationConfigEntry.dot11RegDomain != DOMAIN_TEST) - && lmt_valid == 0) { - panic_printk("NO Limit Value, NO limit TX POWER !!!\n limit for cck=%d, ofdm=%d, ht1s=%d, ht2s=%d, vht1s=%d, vht2s=%d\n", - Adapter->pshare->txpwr_lmt_CCK, - Adapter->pshare->txpwr_lmt_OFDM, - Adapter->pshare->txpwr_lmt_HT1S, - Adapter->pshare->txpwr_lmt_HT2S, - Adapter->pshare->txpwr_lmt_VHT1S, - Adapter->pshare->txpwr_lmt_VHT2S - ); - } - -#endif - return lmt_valid; - -} - - -#if IS_RTL88XX_AC -void TxLMT_OFDM_Jaguar_PathX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte bPathXEnIdx - ) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_odfm_54m = 0; - unsigned char idx_ht_mcs7 = 0; - unsigned char idx_ht_mcs15 = 0; - unsigned char idx_vht_1ss_mcs7 =0; - unsigned char idx_vht_2ss_mcs7 =0; - - char lmt_pg_idx_ofdm = 0; - char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; - char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; - - char max_lmt_idx_ofdm = 0; - char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; - char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; - - // for MIMO 3T3R, 4T4R - unsigned char idx_vht_3ss_mcs7 =0; - unsigned char idx_vht_4ss_mcs7 =0; - char lmt_pg_idx_ht3s, lmt_pg_idx_ht4s = 0; - char lmt_pg_idx_vht3s, lmt_pg_idx_vht4s = 0; - char max_lmt_idx_ht3s, max_lmt_idx_ht4s = 0; - char max_lmt_idx_vht3s, max_lmt_idx_vht4s = 0; - - u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; - u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; - - u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; - u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; - u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; - u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_D_MCS15_MCS12_AC}; - - u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; - u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; - - lmt_pg_idx_ofdm = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[0]; - lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[0]; - lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[0]; - lmt_pg_idx_vht1s = Adapter->pshare->txpwr_lmt_VHT1S - Adapter->pshare->tgpwr_VHT1S_new[0]; - lmt_pg_idx_vht2s = Adapter->pshare->txpwr_lmt_VHT2S - Adapter->pshare->tgpwr_VHT2S_new[0]; - - //Cal Max tx pwr idx for OFDM - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx]); - idx_odfm_54m = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; - max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); - - //Cal Max tx pwr idx for HT1S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx]); - idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - - //Cal Max tx pwr idx for HT2S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx]); - idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); - - //Cal Max tx pwr idx for VHT1S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx]); - idx_vht_1ss_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; - max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); - - //Cal Max tx pwr idx for VHT2S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx]); - idx_vht_2ss_mcs7 = HAL_get_byte_from_dw(tmp_dw, 1); - max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; - max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_OFDM18_OFDM6_AC[bPathXEnIdx], max_lmt_idx_ofdm, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx], max_lmt_idx_ofdm, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS3_MCS0_AC[bPathXEnIdx], max_lmt_idx_ht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx], max_lmt_idx_ht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS11_MCS8_AC[bPathXEnIdx], max_lmt_idx_ht2s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx], max_lmt_idx_ht2s, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[bPathXEnIdx], max_lmt_idx_vht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx], max_lmt_idx_vht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], max_lmt_idx_vht1s, max_lmt_idx_vht2s); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[bPathXEnIdx], max_lmt_idx_vht2s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx], max_lmt_idx_vht2s, 0); - -} - - -#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES -void TxLMT_OFDM_Jaguar_AC_8814( - IN HAL_PADAPTER Adapter - ) -{ - - unsigned int tmp_dw = 0; - unsigned char bPathXEnIdx, rate, start, end; - - unsigned char idx_odfm_54m = 0; - unsigned char idx_ht_mcs7 = 0; - unsigned char idx_ht_mcs15 = 0; - unsigned char idx_vht_1ss_mcs7 =0; - unsigned char idx_vht_2ss_mcs7 =0; - unsigned char idx_vht_3ss_mcs7 =0; - unsigned char idx_vht_4ss_mcs7 =0; - - char lmt_pg_idx_ofdm = 0; - char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; - char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; - char lmt_pg_idx_ht3s, lmt_pg_idx_ht4s = 0; - char lmt_pg_idx_vht3s, lmt_pg_idx_vht4s = 0; - - char max_lmt_idx_ofdm = 0; - char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; - char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; - char max_lmt_idx_ht3s, max_lmt_idx_ht4s = 0; - char max_lmt_idx_vht3s, max_lmt_idx_vht4s = 0; - -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - start=1; - end=2; - } else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - start=1; - end=2; - } else -#endif - { - start=0; - end=3; - } - if(GET_CHIP_VER(Adapter) == VERSION_8822B){ - start=0; - end=1; - } - - - /* Cal Max tx pwr idx for each path */ - for(bPathXEnIdx = start; bPathXEnIdx <= end ; bPathXEnIdx++ ){ - lmt_pg_idx_ofdm = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[bPathXEnIdx]; - lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[bPathXEnIdx]; - lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[bPathXEnIdx]; -#ifdef CONFIG_WLAN_HAL_8814AE - lmt_pg_idx_ht3s = Adapter->pshare->txpwr_lmt_HT3S - Adapter->pshare->tgpwr_HT3S_new[bPathXEnIdx]; - lmt_pg_idx_ht4s = Adapter->pshare->txpwr_lmt_HT4S - Adapter->pshare->tgpwr_HT4S_new[bPathXEnIdx]; -#endif - lmt_pg_idx_vht1s = Adapter->pshare->txpwr_lmt_VHT1S - Adapter->pshare->tgpwr_VHT1S_new[bPathXEnIdx]; - lmt_pg_idx_vht2s = Adapter->pshare->txpwr_lmt_VHT2S - Adapter->pshare->tgpwr_VHT2S_new[bPathXEnIdx]; -#ifdef CONFIG_WLAN_HAL_8814AE - lmt_pg_idx_vht3s = Adapter->pshare->txpwr_lmt_VHT3S - Adapter->pshare->tgpwr_VHT3S_new[bPathXEnIdx]; - lmt_pg_idx_vht4s = Adapter->pshare->txpwr_lmt_VHT4S - Adapter->pshare->tgpwr_VHT4S_new[bPathXEnIdx]; -#endif -#if 0 // Debug message - printk("lmt_pg_idx_ofdm=%d =(txpwr_lmt_OFDM=%d - tgpwr_OFDM_new[%u]=%d)\n",lmt_pg_idx_ofdm, Adapter->pshare->txpwr_lmt_OFDM, bPathXEnIdx, Adapter->pshare->tgpwr_OFDM_new[bPathXEnIdx]); - printk("lmt_pg_idx_ht1s=%d =(txpwr_lmt_HT1S=%d - tgpwr_HT1S_new[%u]=%d)\n",lmt_pg_idx_ht1s, Adapter->pshare->txpwr_lmt_HT1S, bPathXEnIdx, Adapter->pshare->tgpwr_HT1S_new[bPathXEnIdx]); - printk("lmt_pg_idx_ht2s=%d =(txpwr_lmt_HT2S=%d - tgpwr_HT2S_new[%u]=%d)\n",lmt_pg_idx_ht2s, Adapter->pshare->txpwr_lmt_HT2S, bPathXEnIdx, Adapter->pshare->tgpwr_HT2S_new[bPathXEnIdx]); - printk("lmt_pg_idx_ht3s=%d =(txpwr_lmt_HT3S=%d - tgpwr_HT3S_new[%u]=%d)\n",lmt_pg_idx_ht3s, Adapter->pshare->txpwr_lmt_HT3S, bPathXEnIdx, Adapter->pshare->tgpwr_HT3S_new[bPathXEnIdx]); - printk("lmt_pg_idx_ht4s=%d =(txpwr_lmt_HT4S=%d - tgpwr_HT4S_new[%u]=%d)\n",lmt_pg_idx_ht4s, Adapter->pshare->txpwr_lmt_HT4S, bPathXEnIdx, Adapter->pshare->tgpwr_HT4S_new[bPathXEnIdx]); - printk("lmt_pg_idx_vht1s=%d =(txpwr_lmt_VHT1S=%d - tgpwr_VHT1S_new[%u]=%d)\n",lmt_pg_idx_vht1s, Adapter->pshare->txpwr_lmt_VHT1S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT1S_new[bPathXEnIdx]); - printk("lmt_pg_idx_vht2s=%d =(txpwr_lmt_VHT2S=%d - tgpwr_VHT2S_new[%u]=%d)\n",lmt_pg_idx_vht2s, Adapter->pshare->txpwr_lmt_VHT2S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT2S_new[bPathXEnIdx]); - printk("lmt_pg_idx_vht3s=%d =(txpwr_lmt_VHT3S=%d - tgpwr_VHT3S_new[%u]=%d)\n",lmt_pg_idx_vht3s, Adapter->pshare->txpwr_lmt_VHT3S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT3S_new[bPathXEnIdx]); - printk("lmt_pg_idx_vht4s=%d =(txpwr_lmt_VHT4S=%d - tgpwr_VHT4S_new[%u]=%d)\n",lmt_pg_idx_vht4s, Adapter->pshare->txpwr_lmt_VHT4S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT4S_new[bPathXEnIdx]); -#endif - max_lmt_idx_ofdm = lmt_pg_idx_ofdm + HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M); - max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); - max_lmt_idx_ht1s = lmt_pg_idx_ht1s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0); - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - max_lmt_idx_ht2s = lmt_pg_idx_ht2s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0); - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); -#ifdef CONFIG_WLAN_HAL_8814AE - max_lmt_idx_ht3s = lmt_pg_idx_ht3s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0); - max_lmt_idx_ht3s = POWER_MIN_INDEX(max_lmt_idx_ht3s); -#endif - max_lmt_idx_vht1s = lmt_pg_idx_vht1s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0); - max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); - max_lmt_idx_vht2s = lmt_pg_idx_vht2s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0); - max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); -#ifdef CONFIG_WLAN_HAL_8814AE - max_lmt_idx_vht3s = lmt_pg_idx_vht3s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0); - max_lmt_idx_vht3s = POWER_MIN_INDEX(max_lmt_idx_vht3s); -#endif -#if 0 // Debug message - printk("max_lmt_idx_ofdm=%d =(lmt_pg_idx_ofdm=%d + HAL_VAR_CurrentTxAgcOFDM(%d, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M)=%d)\n",max_lmt_idx_ofdm, lmt_pg_idx_ofdm, bPathXEnIdx, HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M)); - printk("max_lmt_idx_ht1s=%d =(lmt_pg_idx_ht1s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht1s, lmt_pg_idx_ht1s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0)); - printk("max_lmt_idx_ht2s=%d =(lmt_pg_idx_ht2s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht2s, lmt_pg_idx_ht2s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0)); - printk("max_lmt_idx_ht3s=%d =(lmt_pg_idx_ht3s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht3s, lmt_pg_idx_ht3s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0)); - printk("max_lmt_idx_vht1s=%d =(lmt_pg_idx_vht1s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht1s, lmt_pg_idx_vht1s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0)); - printk("max_lmt_idx_vht2s=%d =(lmt_pg_idx_vht2s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht2s, lmt_pg_idx_vht2s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0)); - printk("max_lmt_idx_vht3s=%d =(lmt_pg_idx_vht3s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht3s, lmt_pg_idx_vht3s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0)); -#endif - /* set OFDM power index */ - for(rate = 0; rate <= TX_AGC_OFDM_54M - TX_AGC_OFDM_6M; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_OFDM_6M, rate+TX_AGC_OFDM_6M, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, rate), max_lmt_idx_ofdm))); - /* set MCS 1/2/3 SS power index */ - for(rate = 0; rate <= TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht1s))); - for(rate = TX_AGC_HT_NSS2_MCS8-TX_AGC_HT_NSS1_MCS0; rate <= TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht2s))); -#ifdef CONFIG_WLAN_HAL_8814AE - for(rate = TX_AGC_HT_NSS3_MCS16-TX_AGC_HT_NSS1_MCS0; rate <= TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht3s))); -#endif - /* set VHT MCS 1/2/3 SS power index */ - for(rate = 0; rate <= TX_AGC_VHT_NSS1_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht1s))); - for(rate = TX_AGC_VHT_NSS2_MCS0-TX_AGC_VHT_NSS1_MCS0; rate <= TX_AGC_VHT_NSS2_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht2s))); -#ifdef CONFIG_WLAN_HAL_8814AE - for(rate = TX_AGC_VHT_NSS3_MCS0-TX_AGC_VHT_NSS1_MCS0; rate <= TX_AGC_VHT_NSS3_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) - PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht3s))); -#endif - } -} - - -void TxLMT_CCK_Jaguar_AC_8814(IN HAL_PADAPTER Adapter) -{ - - unsigned int tmp_dw = 0; - unsigned char idx_cck_11m = 0; - unsigned char bPathXEnIdx, rate; - char max_lmt_idx_cck, lmt_pg_idx_cck; - int i, start, end; - -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - start=1; - end=2; - } else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - start=1; - end=2; - } else -#endif - { - start=0; - end=3; - } - - - //Cal Max tx pwr idx for CCK - for(bPathXEnIdx = start; bPathXEnIdx <= end ; bPathXEnIdx++ ){ - lmt_pg_idx_cck = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[bPathXEnIdx]; - //printk("lmt_pg_idx_cck=%d =(txpwr_lmt_CCK=%d - tgpwr_CCK_new[%u]=%d)\n",lmt_pg_idx_cck, Adapter->pshare->txpwr_lmt_CCK, bPathXEnIdx, Adapter->pshare->tgpwr_CCK_new[bPathXEnIdx]); - - max_lmt_idx_cck = lmt_pg_idx_cck + HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, TX_AGC_CCK_11M); - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - //printk("max_lmt_idx_cck=%d =(lmt_pg_idx_cck=%d + HAL_VAR_CurrentTxAgcCCK(%d, TX_AGC_CCK_11M)=%d)\n",max_lmt_idx_cck, lmt_pg_idx_cck, bPathXEnIdx, HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, TX_AGC_CCK_11M)); - /* set CCK power index */ - for(rate = 0; rate <= TX_AGC_CCK_11M; rate++) - PHYSetTxPower88XX(Adapter, rate, rate, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, rate), max_lmt_idx_cck))); - } -} -#endif - - -void TxLMT_OFDM_Jaguar_AC(IN HAL_PADAPTER Adapter) -{ - if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 2); - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 2); - TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 3); - } -} - -void TxLMT_CCK_Jaguar_AC(IN HAL_PADAPTER Adapter, IN pu1Byte bPathXEn) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_cck_11m = 0; - - char lmt_pg_idx_cck; - - char max_lmt_idx_cck; - int i; - - unsigned int REG_BB_TXAGC_X_CCK11_CCK1_AC[4] = {REG_BB_TXAGC_A_CCK11_CCK1_AC, REG_BB_TXAGC_B_CCK11_CCK1_AC, REG_BB_TXAGC_C_CCK11_CCK1_AC, REG_BB_TXAGC_D_CCK11_CCK1_AC}; - - lmt_pg_idx_cck = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[0]; - - //Cal Max tx pwr idx for CCK - for(i = 0; i < 4; i++) { - if (bPathXEn[i]) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_CCK11_CCK1_AC[i]); - idx_cck_11m = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; - max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_CCK11_CCK1_AC[i], max_lmt_idx_cck, 0); - } - } - - -} - - -#endif -#if IS_RTL88XX_N -void TxLMT_OFDM_Jaguar_N(IN HAL_PADAPTER Adapter) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_ht_mcs7 = 0; - unsigned char idx_ht_mcs15 = 0; - unsigned char idx_rate54 = 0; - - char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; - char lmt_pg_idx_rate; - - char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; - char max_lmt_rate54 = 0; - - lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[0]; - lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[0]; - lmt_pg_idx_rate = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[0]; - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_RATE54_24_N); - idx_rate54 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_rate54 = idx_rate54 + lmt_pg_idx_rate; - max_lmt_rate54 = POWER_MIN_INDEX(max_lmt_rate54); - - //Cal Max tx pwr idx for HT1S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS07_MCS04_N); - idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - - //Cal Max tx pwr idx for HT2S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_N); - idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); - - RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_OFDM_Jaguar_N, idx_rate54=%x, idx_ht_mcs7=%x, idx_ht_mcs15=%x\n", idx_rate54, idx_ht_mcs7, idx_ht_mcs15)); - RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_OFDM_Jaguar_N, OFDM Limit=%x, HT1S Limit=%x, HT2S Limit=%x\n", max_lmt_rate54, max_lmt_idx_ht1s, max_lmt_idx_ht2s)); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_RATE18_06_N, max_lmt_rate54, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_RATE54_24_N, max_lmt_rate54, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS03_MCS00_N, max_lmt_idx_ht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS07_MCS04_N, max_lmt_idx_ht1s, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS11_MCS08_N, max_lmt_idx_ht2s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS15_MCS12_N, max_lmt_idx_ht2s, 0); - - - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - - lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[1]; - lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[1]; - lmt_pg_idx_rate = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[1]; - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_RATE54_24_N); - idx_rate54 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_rate54 = idx_rate54 + lmt_pg_idx_rate; - max_lmt_rate54 = POWER_MIN_INDEX(max_lmt_rate54); - //Cal Max tx pwr idx for HT1S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS07_MCS04_N); - idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; - max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); - - //Cal Max tx pwr idx for HT2S - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS15_MCS12_N); - idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; - max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_RATE18_06_N, max_lmt_rate54, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_RATE54_24_N, max_lmt_rate54, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS03_MCS00_N, max_lmt_idx_ht1s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS07_MCS04_N, max_lmt_idx_ht1s, 0); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS11_MCS08_N, max_lmt_idx_ht2s, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS15_MCS12_N, max_lmt_idx_ht2s, 0); - } -} - -void TxLMT_CCK_Jaguar_N(IN HAL_PADAPTER Adapter) -{ - - unsigned int tmp_dw = 0; - - unsigned char idx_cck_11m_A = 0, idx_cck_11m_B = 0; - - char lmt_pg_idx_cck_A,lmt_pg_idx_cck_B; - - char max_lmt_idx_cck_A; - char max_lmt_idx_cck_B = 0; - - lmt_pg_idx_cck_A = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[0]; - - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - lmt_pg_idx_cck_B = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[1]; - - //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, - //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); - - - //Cal Max tx pwr idx for CCK - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_2_B_CCK11_N); - idx_cck_11m_A = HAL_get_byte_from_dw(tmp_dw, 3); - max_lmt_idx_cck_A = idx_cck_11m_A + lmt_pg_idx_cck_A; - max_lmt_idx_cck_A = POWER_MIN_INDEX(max_lmt_idx_cck_A); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_2_B_CCK11_N); - idx_cck_11m_B = HAL_get_byte_from_dw(tmp_dw, 0); - max_lmt_idx_cck_B = idx_cck_11m_B + lmt_pg_idx_cck_B; - max_lmt_idx_cck_B = POWER_MIN_INDEX(max_lmt_idx_cck_B); - - RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_CCK_Jaguar_N, idx_cck_11m_A=%x, idx_cck_11m_B=%x\n", idx_cck_11m_A, idx_cck_11m_B)); - RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_CCK_Jaguar_N, CCK Limit A=%x, CCK Limit B=%x\n", max_lmt_idx_cck_A, max_lmt_idx_cck_B)); - - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, max_lmt_idx_cck_A, 0); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, max_lmt_idx_cck_A, max_lmt_idx_cck_B); - HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, max_lmt_idx_cck_B, 0); -} -#endif - -#endif //TXPWR_LMT - - -#if IS_RTL88XX_AC - -void -phy_RFSerialWrite_88XX_AC -( - IN HAL_PADAPTER Adapter, - IN RFRF88XX_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte Data -) -{ - u4Byte dwTmp = 0; - u4Byte value = ((RegAddr << 20) | Data); // addr BIT[27:20], data BIT[19:0] - u4Byte temp_CCA = 0; - - - temp_CCA = HAL_RTL_R32(REG_BB_CCAONSEC_AC); - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, 0xc); // CCA off - - if (eRFPath == RF88XX_PATH_A) { - dwTmp = HAL_RTL_R32(REG_BB_A_LSSIWRITE_AC); - dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; - dwTmp |= value; - - HAL_RTL_W32(REG_BB_A_LSSIWRITE_AC, dwTmp); - } else if (eRFPath == RF88XX_PATH_B) { - dwTmp = HAL_RTL_R32(REG_BB_B_LSSIWRITE_AC); - dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; - dwTmp |= value; - - HAL_RTL_W32(REG_BB_B_LSSIWRITE_AC, dwTmp); - } -#if IS_RTL8814A_SERIES - else if(eRFPath == RF88XX_PATH_C) - { - dwTmp = HAL_RTL_R32(REG_BB_C_LSSIWRITE_AC); - dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; - dwTmp |= value; - - HAL_RTL_W32(REG_BB_C_LSSIWRITE_AC, dwTmp); - } - else if(eRFPath == RF88XX_PATH_D) - { - dwTmp = HAL_RTL_R32(REG_BB_D_LSSIWRITE_AC); - dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; - dwTmp |= value; - - HAL_RTL_W32(REG_BB_D_LSSIWRITE_AC, dwTmp); - } -#endif - - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, temp_CCA); // CCA off -} - -u4Byte -PHY_QueryRFReg_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - // The phy Query function have bug in 8812 & 8881, must follow the rules as below - // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] - // 2. Before Query RF reg, we must turn off CCA - // 3. delay 10us after set addr - // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - - HAL_PADAPTER priv = Adapter; - unsigned long flags; - u4Byte Original_Value, Readback_Value, BitShift; - u4Byte temp_CCA; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - - HAL_SAVE_INT_AND_CLI(flags); - - temp_CCA = HAL_RTL_R32(REG_BB_CCAONSEC_AC); - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, 0xc); // CCA off - - HAL_RTL_W8(REG_BB_HSSIREAD_AC, RegAddr); - - delay_us(30); - - // normally, we use PI mode in normal chip - if (eRFPath == RF88XX_PATH_A) { - Original_Value = HAL_RTL_R32(REG_BB_A_PIREAD_AC); - } else if (eRFPath == RF88XX_PATH_B) { - Original_Value = HAL_RTL_R32(REG_BB_B_PIREAD_AC); - } -#if IS_RTL8814A_SERIES - else if(eRFPath == RF88XX_PATH_C) { - Original_Value = HAL_RTL_R32(REG_BB_C_PIREAD_AC); - } - else if(eRFPath == RF88XX_PATH_D) { - Original_Value = HAL_RTL_R32(REG_BB_D_PIREAD_AC); - } -#endif - else { - RT_TRACE_F(COMP_RF, DBG_SERIOUS, ("RF PATH no existence\n")); - HAL_RESTORE_INT(flags); - return 0xFFFFFFFF; - } - - Original_Value &= 0xfffff; - - BitShift = phy_CalculateBitShift_88XX(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, temp_CCA); // CCA on - - HAL_RESTORE_INT(flags); - - return (Readback_Value); -} - -void -PHY_SetRFReg_88XX_AC -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -) -{ - u4Byte Original_Value, BitShift, New_Value; - HAL_PADAPTER priv = Adapter; - unsigned long flags; - -#if CFG_HAL_DISABLE_BB_RF - return; -#endif //CFG_HAL_DISABLE_BB_RF - -#if (RTL8822B_SUPPORT == 1) - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - HAL_SAVE_INT_AND_CLI(flags); - config_phydm_write_rf_reg_8822b((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask, Data); - HAL_RESTORE_INT(flags); - delay_us(4); - return; - } -#endif - - - HAL_SAVE_INT_AND_CLI(flags); - if (BitMask != BIT_MASK_SET_MASK20BITS_COMMON) { - Original_Value = GET_HAL_INTERFACE(priv)->PHYQueryRFRegHandler(Adapter, eRFPath, RegAddr, BIT_MASK_SET_MASK20BITS_COMMON); - //Original_Value = PHY_QueryRFReg_88XX_AC(Adapter, eRFPath, RegAddr, BIT_MASK_SET_MASK20BITS_COMMON); - BitShift = phy_CalculateBitShift_88XX(BitMask); - New_Value = ((Original_Value & (~BitMask)) | (Data << BitShift)); - phy_RFSerialWrite_88XX_AC(Adapter, eRFPath, RegAddr, New_Value); - } else { - phy_RFSerialWrite_88XX_AC(Adapter, eRFPath, RegAddr, Data); - } - - HAL_RESTORE_INT(flags); - delay_us(4); // At least 500ns delay to avoid RF write fail. -} - - -#if 1//def TX_PG_Jaguar - -void get_tx_pwr_88XX(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, - unsigned char *tmp_b3, unsigned char *tmp_b4) -{ - *tmp_b1 = (tmp_dw & (0xff)); - *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); - *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); - *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); -} - -void TxPG_CCK_Jaguar -( - IN HAL_PADAPTER Adapter, - IN pu1Byte bPathXEn -) -{ - unsigned char b1, b2, b3, b4; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned int tmp_dw = 0; - unsigned int writeVal = 0; - - if (bPathXEn[0]) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_CCK1_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_A[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_A[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_A[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_CCK11_CCK1_AC, writeVal); - } - // TODO: 8814AE CCKTxAgc_B[4,5,6,7] ??? - if (bPathXEn[1]) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_CCK11_CCK1_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_B[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_B[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_B[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_CCK11_CCK1_AC, writeVal); - } -#if IS_RTL8814A_SERIES - if (bPathXEn[2]) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_CCK11_CCK1_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_C[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_C[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_C[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_C[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_CCK11_CCK1_AC, writeVal); - } - if (bPathXEn[3]) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_CCK11_CCK1_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_D[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_D[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_D[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_D[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_CCK11_CCK1_AC, writeVal); - } -#endif -} - - -#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) -void TxPG_CCK_8814 -( - IN HAL_PADAPTER Adapter -) -{ - int path, rate, start, end; - char *pTxAgcOffset; - -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - start=1; - end=2; - } else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - start=1; - end=2; - } else -#endif - { - start=0; - end=3; - } - - - for(path=start;path<=end;path++){ - switch(path){ - case 0: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_A; break; - case 1: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_B; break; - case 2: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_C; break; - case 3: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_D; break; - } - for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ - //printk("CurrentTxAgcCCK[%d][%d]=%x + %x = ",path,rate,Adapter->pshare->phw->CurrentTxAgcCCK[path][rate],(unsigned char)*(pTxAgcOffset+rate)); - Adapter->pshare->phw->CurrentTxAgcCCK[path][rate] += (unsigned char)*(pTxAgcOffset+rate); - Adapter->pshare->phw->CurrentTxAgcCCK[path][rate] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - //printk("CurrentTxAgcCCK[%d][%d]=%x\n",path,rate,Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - } - } -} - - -void TxPG_OFDM_8814 -( - IN HAL_PADAPTER Adapter -) -{ - int path, rate, start, end; - char *pTxAgcOffset; - -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { - start=1; - end=2; - } else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { - start=1; - end=2; - } else -#endif - { - start=0; - end=3; - } - - /* OFDM */ - for(path=start;path<=end;path++){ - switch(path){ - case 0: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_A; break; - case 1: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_B; break; - case 2: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_C; break; - case 3: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_D; break; - } - for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ - //printk("CurrentTxAgcOFDM[%d][%d]=%x + %x = ",path,rate-TX_AGC_OFDM_6M,Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_OFDM_6M)); - Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_OFDM_6M); - Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); - PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); - //printk("CurrentTxAgcOFDM[%d][%d]=%x\n",path,rate-TX_AGC_OFDM_6M,Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); - } - } - /* HT MCS */ - for(path=start;path<=end;path++){ - switch(path){ - case 0: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_A; break; - case 1: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_B; break; - case 2: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_C; break; - case 3: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_D; break; - } - for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ - //printk("CurrentTxAgcMCS[%d][%d]=%x + %x = ",path,rate-TX_AGC_HT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_HT_NSS1_MCS0)); - Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_HT_NSS1_MCS0); - Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - //printk("CurrentTxAgcMCS[%d][%d]=%x\n",path,rate-TX_AGC_HT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - } - /* VHT MCS */ - for(path=start;path<=end;path++){ - switch(path){ - case 0: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_A; break; - case 1: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_B; break; - case 2: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_C; break; - case 3: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_D; break; - } - for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ - //printk("CurrentTxAgcVHT[%d][%d]=%x + %x = ",path,rate-TX_AGC_VHT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0)); - if( rate == TX_AGC_VHT_NSS1_MCS8 || rate == TX_AGC_VHT_NSS1_MCS9 \ - || rate == TX_AGC_VHT_NSS2_MCS8|| rate == TX_AGC_VHT_NSS2_MCS9 \ - || rate == TX_AGC_VHT_NSS3_MCS8 || rate == TX_AGC_VHT_NSS3_MCS9 ) - Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] -= (unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0); - else - Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0); - Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - //printk("CurrentTxAgcVHT[%d][%d]=%x\n",path,rate-TX_AGC_VHT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - } -} -#endif -#endif - -void TxPG_OFDM_Jaguar_A -( - IN HAL_PADAPTER Adapter -) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 = 0; - unsigned int writeVal = 0; - //printk("TxPG_OFDM_8812_A!!\n"); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_A[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_A[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_A[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_A[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_A[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_A[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS3_MCS0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS3_MCS0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS7_MCS4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS7_MCS4_AC, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS11_MCS8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_AC, writeVal); - } - if (HAL_VAR_PHYBANDSELECT == PHY_BAND_5G) { - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC); - tmp_dw1 = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_A[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_A[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[19]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[18]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_A[17]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_A[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, writeVal); - } -} - - -void TxPG_OFDM_Jaguar_B -( - IN HAL_PADAPTER Adapter -) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 = 0; - unsigned int writeVal = 0; - - //printk("TxPG_OFDM_8812_B!!\n"); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_OFDM18_OFDM6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_B[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_B[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_B[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_OFDM18_OFDM6_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_OFDM54_OFDM24_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_B[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_B[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_B[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_OFDM54_OFDM24_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS3_MCS0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS3_MCS0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS7_MCS4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS7_MCS4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS11_MCS8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS15_MCS12_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC); - tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_B[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_B[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[19]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[18]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_B[17]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_B[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, writeVal); -} - -#if IS_RTL8814A_SERIES -void TxPG_OFDM_Jaguar_C -( - IN HAL_PADAPTER Adapter -) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 =0; - unsigned int writeVal = 0; - - //printk("TxPG_OFDM_8812_B!!\n"); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_OFDM18_OFDM6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_C[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_C[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_C[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_C[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_OFDM18_OFDM6_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_OFDM54_OFDM24_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_C[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_C[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_C[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_C[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_OFDM54_OFDM24_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS3_MCS0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_MCS3_MCS0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS7_MCS4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_MCS7_MCS4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS11_MCS8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_MCS11_MCS8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS15_MCS12_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_MCS15_MCS12_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC); - tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_C[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_C[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[19]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[18]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_C[17]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_C[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, writeVal); -} - -void TxPG_OFDM_Jaguar_D -( - IN HAL_PADAPTER Adapter -) -{ - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 =0; - unsigned int writeVal = 0; - - //printk("TxPG_OFDM_8812_B!!\n"); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_OFDM18_OFDM6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_D[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_D[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_D[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_D[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_OFDM18_OFDM6_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_OFDM54_OFDM24_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_D[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_D[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_D[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_D[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_OFDM54_OFDM24_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS3_MCS0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_MCS3_MCS0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS7_MCS4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_MCS7_MCS4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS11_MCS8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_MCS11_MCS8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS15_MCS12_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_MCS15_MCS12_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[3]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[2]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[1]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[0]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[7]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[6]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[5]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[4]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC); - tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_D[11]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_D[10]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[9]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[8]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[15]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[14]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[13]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[12]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[19]); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[18]); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_D[17]); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_D[16]); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC, writeVal); -} -#endif - - -void -checkSwitchChannelPara88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte channel -) -{ - RT_TRACE_F(COMP_RF, DBG_TRACE, ("Switch to channel [%x] \n", channel)); - - // BW - RT_TRACE_F(COMP_RF, DBG_TRACE, ("BW parameter \n")); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("CCK en 0x808[28][29]=%x \n", HAL_RTL_R32(0x808))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("rf_mode BB 0x8ac[21,20,9:6,1,0]=%x \n", HAL_RTL_R32(0x8ac))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("rf_mode MAC 0x8[7:6]=%x \n", HAL_RTL_R8(0x8))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("RF TRX_BW RF 0x18=%x \n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xffffffff, 1))); - - - // 2.4G <=> 5G - RT_TRACE_F(COMP_RF, DBG_TRACE, ("2.4G 5G switch \n")); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("CCK_CHECK_en 0x454[7]=%x \n", HAL_RTL_R8(0x454))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("AGC table select 0x82c[1:0]=%x \n", HAL_RTL_R32(0x82c))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xcb0))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xeb0))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xcb0))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xeb0))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("fc_area 0x860[28:17]= %x \n", HAL_RTL_R32(0x860))); - RT_TRACE_F(COMP_RF, DBG_TRACE, ("RF MOD AG reg18[18,17,16,9,8]=%x\n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xc00, 1))); -} - -#if 0 -void checkSwitchChannelPara88XX(IN HAL_PADAPTER Adapter, unsigned char channel) -{ - printk("Switch to channel [%x] \n", channel); - - // BW - printk("BW parameter \n"); - printk("CCK en 0x808[28][29]=%x \n", HAL_RTL_R32(0x808)); - printk("rf_mode BB 0x8ac[21,20,9:6,1,0]=%x \n", HAL_RTL_R32(0x8ac)); - printk("rf_mode MAC 0x8[7:6]=%x \n", HAL_RTL_R8(0x8)); - printk("RF TRX_BW RF 0x18=%x \n", PHY_QueryRFReg_88XX_AC(Adapter, 0, 0x18, 0xffffffff)); - - - // 2.4G <=> 5G - printk("2.4G 5G switch \n"); - printk("CCK_CHECK_en 0x454[7]=%x \n", HAL_RTL_R8(0x454)); - printk("AGC table select 0x82c[1:0]=%x \n", HAL_RTL_R32(0x82c)); - printk("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xcb0)); - printk("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xeb0)); - printk("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xcb0)); - printk("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xeb0)); - printk("fc_area 0x860[28:17]= %x \n", HAL_RTL_R32(0x860)); - printk("RF MOD AG reg18[18,17,16,9,8]=%x\n", PHY_QueryRFReg_88XX_AC(Adapter, 0, 0x18, 0xc00)); - - printk("0x8ac = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x8ac, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x8ac = %x\n", HAL_RTL_R32(0x8ac)); - printk("0x668 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x668, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x668 = %x\n", HAL_RTL_R32(0x668)); - printk("0x8c4 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x8c4, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x8c4 = %x\n", HAL_RTL_R32(0x8c4)); - printk("0x24 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x24, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x24 = %x\n", HAL_RTL_R32(0x24)); - printk("0xa00 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0xa00, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0xa00 = %x\n", HAL_RTL_R32(0xa00)); - printk("0x483 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x483, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x483 = %x\n", HAL_RTL_R32(0x483)); - printk("0x838 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x838, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x838 = %x\n", HAL_RTL_R32(0x838)); - printk("0x440 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x440, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x440 = %x\n", HAL_RTL_R32(0x440)); - printk("0x848 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x848, BIT_MASK_SET_MASKDWORD_COMMON)); - printk("0x848 = %x\n", HAL_RTL_R32(0x848)); -} -#endif - - -#if 1 //eric-8822 -int conver_bw_hal_2_odm(int bandwidth) -{ - int bandwidth_odm = ODM_BW20M; - - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - bandwidth_odm = ODM_BW5M; - break; - case HT_CHANNEL_WIDTH_AC_10: - bandwidth_odm = ODM_BW10M; - break; - case HT_CHANNEL_WIDTH_AC_20: - bandwidth_odm = ODM_BW20M; - break; - case HT_CHANNEL_WIDTH_AC_40: - bandwidth_odm = ODM_BW40M; - break; - case HT_CHANNEL_WIDTH_AC_80: - bandwidth_odm = ODM_BW80M; - break; - case HT_CHANNEL_WIDTH_AC_160: - bandwidth_odm = ODM_BW160M; - break; - } - - return bandwidth_odm; -} -#endif - -void -SwBWMode88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -) -{ - - u4Byte rfBand = 0, clkSel = 0 , rrSR = 0, tmp_rf = 0; - u1Byte dataSC = 0; - u1Byte SCSettingOf40 = 0; - u1Byte SCSettingOf20 = 0; - u1Byte Current_band; - - if (HAL_VAR_DOT11CHANNEL <= CHANNEL_MAX_NUMBER_2G) - Current_band = RF88XX_BAND_ON_2_4G; - else - Current_band = RF88XX_BAND_ON_5G; - SCSettingOf20 = HAL_VAR_TXSC_20; - SCSettingOf40 = HAL_VAR_TXSC_40; - -#if (RTL8822B_SUPPORT == 1) - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - - int bandwidth_odm = conver_bw_hal_2_odm(bandwidth); - - rfBand = HAL_RTL_R32(REG_WMAC_TRXPTCL_CTL); - rfBand &= ~(BIT(7) | BIT(8)); - - dataSC = ( SCSettingOf20 | (SCSettingOf40 << 4)); - - switch (bandwidth) { - - case HT_CHANNEL_WIDTH_AC_40: - - rfBand |= BIT(7); - break; - - case HT_CHANNEL_WIDTH_AC_80: - - rfBand |= BIT(8); - break; - } - - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - HAL_RTL_W8(REG_DATA_SC, dataSC); - -#ifdef MP_TEST - if(Adapter->pshare->rf_ft_var.mp_specific) - config_phydm_trx_mode_8822b((&(Adapter->pshare->_dmODM)), Adapter->pshare->mp_antenna_tx, Adapter->pshare->mp_antenna_rx, 0); -#endif - //else - //config_phydm_trx_mode_8822b((&(Adapter->pshare->_dmODM)), (ODM_RF_A|ODM_RF_B), (ODM_RF_A|ODM_RF_B), Adapter->pmib->dot11RFEntry.tx2path); - - config_phydm_switch_bandwidth_8822b((&(Adapter->pshare->_dmODM)), SCSettingOf20, bandwidth_odm); - - return; - } -#endif - - //3 ========== <1> Set rf_mode 0x8ac / 0x24 (REG_AFE_CTRL1, BIT_MAC_CLK_SEL)/ 0x668 - - rfBand = HAL_RTL_R32(REG_WMAC_TRXPTCL_CTL); - rfBand &= ~(BIT(7) | BIT(8)); - -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - clkSel = HAL_RTL_R32(REG_SYS_CLK_CTRL); - clkSel &= ~(BIT(6)|BIT(7)); - } else -#endif - { - clkSel = HAL_RTL_R32(REG_AFE_CTRL1); - clkSel &= ~(BIT(20)|BIT(21)); - } - - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x200040); // 5M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0100000100 - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x200140); // 5M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0100010100 - } - clkSel |= BIT(7); - HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); - - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x100040); // 5M : 0x8ac[21,20,9:6,1,0]=8'b01000100 - clkSel |= BIT(21); - HAL_RTL_W32(REG_AFE_CTRL1, clkSel); - } - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - break; - case HT_CHANNEL_WIDTH_AC_10: -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x300180); // 10M :0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0110011000 - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x300280); // 10M :0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0110101000 - } - clkSel |= BIT(6); - HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x200180); // 10M : 0x8ac[21,20,9:6,1,0]=8'b10011000 - clkSel |= BIT(20); - HAL_RTL_W32(REG_AFE_CTRL1, clkSel); - } - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - break; - case HT_CHANNEL_WIDTH_AC_20: -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter)) { - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10000200); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1000100000 - } else { // 2.4G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010000); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001000000 - } - } else { - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - if (IS_HAL_A_CUT(Adapter)) { - // MP chip - A-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10000300); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1000110000 - } else { - // MP chip - B-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010100); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001010000 - } - } else { // 2.4G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010100); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001010000 - } - } - HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300200); // 20M : 0x8ac[21,20,9:6,1,0]=8'b11100000 - HAL_RTL_W32(REG_AFE_CTRL1, clkSel); - } - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - break; - case HT_CHANNEL_WIDTH_AC_40: -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter)) { - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0xC01); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b0110001 - } else { // 2.4G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20001); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1000001 - } - } else { - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - if (IS_HAL_A_CUT(Adapter)) { - // MP chip - A-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20001); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1000001 - } else { - // MP chip - B-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20C20CC3, 0x20020401); // 40M : 0x8ac[29,23,22,17,11,10,7,6,1,0]=10'b1001010001 - } - } else { // 2.4G - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20401); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1010001 - } - } - HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300201); // 40M : 0x8ac[21,20,9:6,1,0]=8'b11100001 - HAL_RTL_W32(REG_AFE_CTRL1, clkSel); - } - rfBand |= BIT(7); - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - break; - case HT_CHANNEL_WIDTH_AC_80: -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0xC3, 0x2); // 80M : 0x8ac[7,6,1,0]=4'b0010 - } else { - if (IS_HAL_A_CUT(Adapter)) { - // MP chip - A-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0xC3, 0x2); // 80M : 0x8ac[7,6,1,0]=4'b0010 - } else { - // MP chip - B-cut - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x430430C3, 0x40041002); // 80M : 0x8ac[30,25,24,18,13,12,7,6,1,0]=10'b1001010010 - } - } - HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300202); // 80M : 0x8ac[21,20,9:6,1,0]=8'b11100010 - HAL_RTL_W32(REG_AFE_CTRL1, clkSel); - } - rfBand |= BIT(8); - HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); - break; - } - - //3 ========== <2> Set adc buff clk 0x8c4 - -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - if(IS_HAL_TEST_CHIP(Adapter) || IS_HAL_A_CUT(Adapter)) { - switch (bandwidth) - { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 1); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); - } - break; - case HT_CHANNEL_WIDTH_AC_40: - if (Current_band == RF88XX_BAND_ON_5G) { // 5G - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 0); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); - } - break; - case HT_CHANNEL_WIDTH_AC_80: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); - break; - } - } else { - switch (bandwidth) - { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 1); - break; - case HT_CHANNEL_WIDTH_AC_20: - case HT_CHANNEL_WIDTH_AC_40: - case HT_CHANNEL_WIDTH_AC_80: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); - break; - } - } - - } else -#endif - { - switch (bandwidth) - { - case HT_CHANNEL_WIDTH_AC_5: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_10: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_20: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_40: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); - break; - case HT_CHANNEL_WIDTH_AC_80: - PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); - break; - } - } - - //3 ========== <3> Set primary channel 0x8ac & 0xa00, txsc 0x483 - - dataSC = HAL_RTL_R8(REG_DATA_SC); - - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - break; - - case HT_CHANNEL_WIDTH_AC_40: - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x3C, SCSettingOf20); //0x8ac[5:2]=1/2 -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - // Do nothing for 8814A - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, 0xF0000000, SCSettingOf20); //0x838[31:28]=1/2 - } - - if (SCSettingOf20 == 1) { - // BIT(4) = 1, upper sideBand - PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_SYSTEM_AC, 0x10, 0x1); //0xa00 BIT(4)=1 - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_SYSTEM_AC, 0x10, 0x0); //0xa00 BIT(4)=0 - } - - dataSC &= 0xf0; - dataSC |= SCSettingOf20; - HAL_RTL_W8(REG_DATA_SC, dataSC); //0x483[3:0]=1/2 - break; - - case HT_CHANNEL_WIDTH_AC_80: - PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x3C, SCSettingOf20); //0x8ac[5:2]=1/2/3/4 offset 9&10 seems few to use -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - // Do nothing for 8814A - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, 0xF0000000, SCSettingOf20); //0x838[31:28]=1/2/3/4 - } - - dataSC = ( SCSettingOf20 | (SCSettingOf40 << 4)); //0x483[3:0]=1/2/3/4 - HAL_RTL_W8(REG_DATA_SC, dataSC); - - break; - } - - //3 ========== <4> Set Equzlier step size , reg0x864[20:18] - -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - // Do nothing for 8814A - } else -#endif - { - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); - break; - case HT_CHANNEL_WIDTH_AC_10: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); - break; - case HT_CHANNEL_WIDTH_AC_20: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); - break; - case HT_CHANNEL_WIDTH_AC_40: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 2); - break; - case HT_CHANNEL_WIDTH_AC_80: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 2); - break; - } - } - - - //3 ========== <> PWED_TH_FB, 0x82C[15:12] - //3 ========== <> r_CCA_primary, 0x838[0] -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - switch (bandwidth) - { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x9); - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x1); - } else { - if (Current_band == RF88XX_BAND_ON_5G) - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); - else - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); - } - break; - case HT_CHANNEL_WIDTH_AC_40: - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x5); - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x0); - } else { - if (Current_band == RF88XX_BAND_ON_5G) - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x8); - else - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); - } - break; - case HT_CHANNEL_WIDTH_AC_80: - if(IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); - PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x0); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x3); - } - break; - } - } -#endif - - - //3 ========== <5> 0821, L1_peak_th 0x848 - -#if IS_RTL8814A_SERIES - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - // Do nothing here.. - } else -#endif - { - switch (bandwidth) - { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - #if 0 - if(GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 7); // 2R 0x848[25:22] = 0x7 - else - PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); // 1R 0x848[25:22] = 0x8 - #endif - if (IS_HARDWARE_TYPE_8881A(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); - } - break; - case HT_CHANNEL_WIDTH_AC_40: - if (IS_HARDWARE_TYPE_8881A(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); - } - break; - case HT_CHANNEL_WIDTH_AC_80: - if (IS_HARDWARE_TYPE_8881A(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 7); - } - break; - } - } - - //3 ========== <6> Set RRSR_RSC 0x440[22:21] - - rrSR = HAL_RTL_R32(REG_RRSR); - rrSR &= ~(BIT(21) | BIT(22)); - - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - break; - case HT_CHANNEL_WIDTH_AC_40: - HAL_RTL_W32(REG_RRSR, rrSR); - break; - case HT_CHANNEL_WIDTH_AC_80: - HAL_RTL_W32(REG_RRSR, rrSR); - break; - } - - //3 ========== <7> Set RF TRX_BW rf_0x18[11:10] - switch (bandwidth) { - case HT_CHANNEL_WIDTH_AC_5: - case HT_CHANNEL_WIDTH_AC_10: - case HT_CHANNEL_WIDTH_AC_20: - tmp_rf = 0x03; - break; - case HT_CHANNEL_WIDTH_AC_40: - tmp_rf = 0x01; - break; - case HT_CHANNEL_WIDTH_AC_80: - tmp_rf = 0x00; - break; - } - - if(GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) - { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); -#if IS_RTL8814A_SERIES - /* 2nd CCA enable/disable settings*/ - if(IS_HARDWARE_TYPE_8814A(Adapter)) { - if (!Adapter->pshare->rf_ft_var.disable_2ndcca) - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_A); - } -#endif - } - else if(GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); -#if IS_RTL8814A_SERIES - /* 2nd CCA enable/disable settings*/ - if(IS_HARDWARE_TYPE_8814A(Adapter)) { - if (!Adapter->pshare->rf_ft_var.disable_2ndcca) - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); - } -#endif - } -#if IS_RTL8814A_SERIES - else if(GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) - { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - if(IS_HARDWARE_TYPE_8814A(Adapter)) - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); -#if IS_RTL8814A_SERIES - /* 2nd CCA enable/disable settings*/ - if(IS_HARDWARE_TYPE_8814A(Adapter)) { - if (!Adapter->pshare->rf_ft_var.disable_2ndcca) { -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if (Current_band == RF88XX_BAND_ON_5G) { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); - } - else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if (Current_band == RF88XX_BAND_ON_2_4G) { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); - } - else -#endif - { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_ABCD); - } - } - } -#endif - } - else if(GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) - { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); -#if IS_RTL8814A_SERIES - /* 2nd CCA enable/disable settings*/ - if(IS_HARDWARE_TYPE_8814A(Adapter)) { - if (!Adapter->pshare->rf_ft_var.disable_2ndcca) { -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if (Current_band == RF88XX_BAND_ON_5G) { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); - } - else -#endif -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if (Current_band == RF88XX_BAND_ON_2_4G) { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); - } - else -#endif - { - GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_ABCD); - } - } - } -#endif - } -#endif -#if IS_RTL8814A_SERIES - // for MP chip A-cut - if(IS_HARDWARE_TYPE_8814A(Adapter)) { - if (IS_HAL_A_CUT(Adapter)) { - phy_ADC_CLK_8814A(Adapter); - } - } -#endif -#if IS_RTL8814A_SERIES - /* RCK for pathB/C/D. Fix 8814 MP-chip RF reg setting bug */ - if (IS_HARDWARE_TYPE_8814A(Adapter) && !IS_HAL_TEST_CHIP(Adapter)){ - unsigned int rfPathA = PHY_QueryRFReg(Adapter, RF88XX_PATH_A, 0x1c, 0xffffffff, 1); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, 0x1c, 0xffffffff, rfPathA); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, 0x1c, 0xffffffff, rfPathA); - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, 0x1c, 0xffffffff, rfPathA); - } -#endif - -} - -void -SetChannelPara88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte channel, - IN s4Byte offset -) -{ - u4Byte val = channel; - u4Byte eRFPath, curMaxRFPath; - - //AGC_Table - // TODO: 8813AE BB/RF - if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { - - if (channel <= CHANNEL_MAX_NUMBER_2G) { - // 2G - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, BIT_MASK_BB_BAGC_TABLE_AC, 0); - } else { - //5G - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, BIT_MASK_BB_BAGC_TABLE_AC, 1); - } - } -#if IS_RTL8814A_SERIES - else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - if (channel <= CHANNEL_MAX_NUMBER_2G) { - // 2G - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 0); - } - else { - //5G - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - if (36 <= channel && channel <= 64) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 1); - } else if (100 <= channel && channel <= 144) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 2); - } else if (149 <= channel) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 3); - } else { - printk("%s(%d): REG_BB_AGC_TABLE setting error !!! \n", __FUNCTION__, __LINE__); - } - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 1); - } - } - } -#endif - else { - if (channel <= CHANNEL_MAX_NUMBER_2G) { - // 2G - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 0); - } else { - //5G - if ((GET_CHIP_VER(Adapter) == VERSION_8881A)) { - if (channel <= 64) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 1); - } else if (channel >= 100 && channel <= 140) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 2); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 3); - } - } else { - if (channel <= 64) { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 1); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 2); - } - } - } - } - - // fc_area - if (36 <= channel && channel <= 48) { - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x494); //0x860[28:17]=0x494 - } else if (50 <= channel && channel <= 64) { - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x453); //0x860[28:17]=0x453 - } else if (100 <= channel && channel <= 116) { - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x452); //0x860[28:17]=0x452 - } else if (118 <= channel && channel <= 165) { - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x412); //0x860[28:17]=0x412 - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x96a); //0x860[28:17]=0x96a - } - - // RF_MOD_AG - if (channel <= 14) { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x0); //RF_A reg18[18,17,16,9,8]=4'b00101 - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x0); //RF_B reg18[18,17,16,9,8]=4'b00101 -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x0); //RF_C reg18[18,17,16,9,8]=5'b00000 - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x0); //RF_D reg18[18,17,16,9,8]=5'b00000 - } -#endif - } else if (36 <= channel && channel <= 64) { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x101); //RF_A reg18[18,17,16,9,8]=4'b00101 - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x101); //RF_B reg18[18,17,16,9,8]=4'b00101 -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x101); //RF_A reg18[18,17,16,9,8]=5'b00101 - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x101); //RF_B reg18[18,17,16,9,8]=5'b00101 - } -#endif - } else if (100 <= channel && channel <= 140) { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x301); //RF_A reg18[18,17,16,9,8]=4'b01101 - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x301); //RF_B reg18[18,17,16,9,8]=4'b01101 -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x301); //RF_A reg18[18,17,16,9,8]=5'b01101 - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x301); //RF_B reg18[18,17,16,9,8]=5'b01101 - } -#endif - } else if (140 < channel) { - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x501); //RF_A reg18[18,17,16,9,8]=4'b10101 - PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x501); //RF_B reg18[18,17,16,9,8]=4'b10101 -#if IS_RTL8814A_SERIES - if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x501); //RF_A reg18[18,17,16,9,8]=5'b10101 - PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x501); //RF_B reg18[18,17,16,9,8]=5'b10101 - } -#endif - } - - // set channel number - curMaxRFPath = RF88XX_PATH_MAX; - - if (channel > 14) - HAL_VAR_CURR_BAND = RF88XX_BAND_ON_5G; - else - HAL_VAR_CURR_BAND = RF88XX_BAND_ON_2_4G; - - if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_80) { - if (channel <= 48) - val = 42; - else if (channel <= 64) - val = 58; - else if (channel <= 112) - val = 106; - else if (channel <= 128) - val = 122; - else if (channel <= 144) - val = 138; - else if (channel <= 161) - val = 155; - else if (channel <= 177) - val = 171; - } else if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_20_40) { - if (offset == 1) - val -= 2; - else - val += 2; - } - - if (HAL_VAR_USE_FRQ_2_3G) { - val += 14; - } - - for (eRFPath = RF88XX_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { - PHY_SetRFReg_88XX_AC(Adapter, eRFPath, REG_RF_CHNLBW_AC, 0xff, val); - } -} - - -void -CheckBand88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte RequestChannel -) -{ - - u1Byte Current_band; - //check CCK_CHECK_en BIT7 - if ( HAL_RTL_R8(REG_CCK_CHECK) & BIT(7) ) - Current_band = RF88XX_BAND_ON_5G; - else - Current_band = RF88XX_BAND_ON_2_4G; - - if (HAL_VAR_pre_channel == 0) { // fisrt lauch, no need to check band - if (RequestChannel <= CHANNEL_MAX_NUMBER_2G) { - SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_2_4G); - } else { - SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_5G); - } - } else { - if (RequestChannel <= CHANNEL_MAX_NUMBER_2G) { - // Request for 2.4G Band - if (Current_band == RF88XX_BAND_ON_2_4G) { - // In 2.4G ,Donothing - } else if (Current_band == RF88XX_BAND_ON_5G) { - // In 5G ,switch band to 2.4G - SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_2_4G); - } - } else if (RequestChannel > CHANNEL_MAX_NUMBER_2G) { - // Request for 5G Band - if (Current_band == RF88XX_BAND_ON_2_4G) { - // In 2.4G ,switch band to 5G - SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_5G); - } else if (Current_band == RF88XX_BAND_ON_5G) { - // In 5G ,Donothing - } - } - } -} - -#if IS_RTL8814A_SERIES -void -phy_ADC_CLK_8814A( - IN HAL_PADAPTER Adapter - ) -{ - printk("[%s]\n",__FUNCTION__); - - u4Byte MAC_REG_520, BB_REG_8FC, BB_REG_808, RXIQC[4], Search_index = 0, MAC_Active = 1; - u4Byte RXIQC_REG[2][4] = {{0xc10, 0xe10, 0x1810, 0x1a10}, {0xc14, 0xe14, 0x1814, 0x1a14}} ; - - //1 Step1. MAC TX pause - - MAC_REG_520 = PHY_QueryBBReg( Adapter, 0x520, BIT_MASK_SET_MASKDWORD_COMMON); - BB_REG_8FC = PHY_QueryBBReg( Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON); - BB_REG_808 = PHY_QueryBBReg( Adapter, 0x808, BIT_MASK_SET_MASKDWORD_COMMON); - PHY_SetBBReg(Adapter, 0x520, BIT_MASK_SET_MASKBYTE2_COMMON, 0x3f); - - //1 Step 2. Backup RXIQC & RXIQC = 0 - - for(Search_index = 0; Search_index<4; Search_index++){ - RXIQC[Search_index] = PHY_QueryBBReg( Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON); - PHY_SetBBReg(Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x0); - PHY_SetBBReg(Adapter, RXIQC_REG[1][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x0); - } - PHY_SetBBReg(Adapter, 0xa14, 0x00000300, 0x3); - Search_index = 0; - - - //1 Step 3. Monitor MAC IDLE - PHY_SetBBReg(Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON, 0x0); - while(MAC_Active){ - MAC_Active = PHY_QueryBBReg( Adapter, 0xfa0, BIT_MASK_SET_MASKDWORD_COMMON) & (0x803e0008); - Search_index++; - if(Search_index>1000){ - break; - } - } - //1 Step 4. ADC clk flow - - PHY_SetBBReg(Adapter, 0x808, BIT_MASK_SET_MASKBYTE0_COMMON, 0x11); - PHY_SetBBReg(Adapter, 0x90c, BIT(13), 0x1); - PHY_SetBBReg(Adapter, 0x764, BIT(10)|BIT(9), 0x3); - - PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x1); - // 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 - // 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line - // 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut - // power_off/clk_off @ anapar_state=idle mode - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0xc60 0x15808002 - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0xc60 0x01808003 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0xe60 0x15808002 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0xe60 0x01808003 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0x1860 0x15808002 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0x1860 0x01808003 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0x1a60 0x15808002 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0x1a60 0x01808003 - PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x0); - PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x0); - PHY_SetBBReg(Adapter, 0xc5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0xc5c 0x00080058 // [19] =1 to turn off ADC - PHY_SetBBReg(Adapter, 0xe5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0xe5c 0x00080058 // [19] =1 to turn off ADC - PHY_SetBBReg(Adapter, 0x185c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0x185c 0x00080058 // [19] =1 to turn off ADC - PHY_SetBBReg(Adapter, 0x1a5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0x1a5c 0x00080058 // [19] =1 to turn off ADC - // power_on/clk_off - - //PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x1); - - PHY_SetBBReg(Adapter, 0xc5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0xc5c 0x0D000058 // [19] =0 to turn on ADC - PHY_SetBBReg(Adapter, 0xe5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0xe5c 0x0D000058 // [19] =0 to turn on ADC - PHY_SetBBReg(Adapter, 0x185c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0x185c 0x0D000058 // [19] =0 to turn on ADC - PHY_SetBBReg(Adapter, 0x1a5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0x1a5c 0x0D000058 // [19] =0 to turn on ADC - - // power_on/clk_on @ anapar_state=BT mode - - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xc60 0x05808002 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xe60 0x05808002 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1860 0x05808002 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1a60 0x05808002 - PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x1); - PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x1); - // recover original setting @ anapar_state=BT mode - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xc60 0x05808036 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xe60 0x05808036 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1860 0x05808036 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1a60 0x05808036 - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0xc60 0x05800002 - PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0xc60 0x07808003 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0xe60 0x05800002 - PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0xe60 0x07808003 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0x1860 0x05800002 - PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0x1860 0x07808003 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0x1a60 0x05800002 - PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0x1a60 0x07808003 - PHY_SetBBReg(Adapter, 0x764, BIT(10)|BIT(9), 0x0); - PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x0); - PHY_SetBBReg(Adapter, 0x90c, BIT(13), 0x0); - - //1 Step 5. Recover MAC TX & IQC - - PHY_SetBBReg(Adapter, 0x520, BIT_MASK_SET_MASKDWORD_COMMON, MAC_REG_520); - PHY_SetBBReg(Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON, BB_REG_8FC); - PHY_SetBBReg(Adapter, 0x808, BIT_MASK_SET_MASKDWORD_COMMON, BB_REG_808); - for(Search_index = 0; Search_index<4; Search_index++){ - PHY_SetBBReg(Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, RXIQC[Search_index]); - PHY_SetBBReg(Adapter, RXIQC_REG[1][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x01000000); - } - PHY_SetBBReg(Adapter, 0xa14, 0x00000300, 0x0); -} -#endif - -void -SwitchWirelessBand88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte RequestChannel, - IN u1Byte Band -) -{ - if (Band == RF88XX_BAND_ON_2_4G) { // 2.4G band - RT_TRACE(COMP_RF, DBG_LOUD, ("==>SwitchWirelessBand88XX_AC() BAND_ON_2_4G settings\n")); - - // STOP Tx/Rx - PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC , 0x00); - - // PWED_TH -#if IS_RTL8881A_SERIES - if (IS_HARDWARE_TYPE_8881A(Adapter)) { - if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_PWED_TH_AC, BIT3 | BIT2 | BIT1, 0x3); - } - } -#endif - - //PinMux - if (GET_CHIP_VER(Adapter) == VERSION_8881A) { - if (IS_HAL_TEST_CHIP(Adapter)) { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x00); - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x0); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf0, 0x7); - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x7); - } - } else if (GET_CHIP_VER(Adapter) == VERSION_8812E) { - if (IS_HAL_TEST_CHIP(Adapter)) { - // r_select_5G for path_A/B - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT12, 0x0); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT12, 0x0); - - // LANON (5G uses external LNA) - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT15, 0x1); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT15, 0x1); - - } else { - // TODO: Eric check PA type fill reg[REG_BB_RA_RFE_PINMUX] - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x77); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x77); - } - } else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - panic_printk("2G RFE TYPE\n"); -#ifdef HIGH_POWER_EXT_PA -#ifdef HIGH_POWER_EXT_LNA - //3 RFE Type 2 - if (Adapter->pshare->rf_ft_var.use_ext_pa && Adapter->pshare->rf_ft_var.use_ext_lna) { - switch(Adapter->pmib->dot11RFEntry.rfe_type){ - case 3: - case 5: - panic_printk("TRSWITCH: RFE TYPE 3 or 5\n"); - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77707770); - PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x45); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] - break; - case 2: - case 4: - panic_printk("TRSWITCH: RFE TYPE 2 or 4\n"); - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77707770); - PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x72); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] - break; - default: - GDEBUG("TRSWITCH: Unknown RFE type (%d)!\n", Adapter->pmib->dot11RFEntry.rfe_type); - break; - // TODO: high power setting - - } - } else -#endif -#endif - //3 RFE Type 7 or 9 - { - panic_printk("TRSWITCH: RFE TYPE 7 or 9\n"); - - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0xC00000, 0x2); // (S3 RFE output enable) , 0x40[23:22] - - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); - PHY_SetBBReg_88XX(Adapter, 0x1abc, 0xFF00000, 0x77); // 0x1ABC[27:20] - } - } - // cck_enable - PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC, 0x3); - - if (GET_CHIP_VER(Adapter) != VERSION_8814A) // 8814 RX CCK is from PHY parameters and no 2G/5G selectable - PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_RX_AC, 0x0f000000, 0x1); - - // CCK_CHECK_en - HAL_RTL_W8(REG_CCK_CHECK, (HAL_RTL_R8(REG_CCK_CHECK) & ~(BIT(7)))); // 5G to 2.4G last lauch - - } else if (Band == RF88XX_BAND_ON_5G) { //5G band - RT_TRACE(COMP_RF, DBG_LOUD, ("==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings\n")); - - // CCK_CHECK_en - HAL_RTL_W8(REG_CCK_CHECK, (HAL_RTL_R8(REG_CCK_CHECK) | BIT(7))); // 2.4G to 5G first lauch - - // STOP CCK,OFDM - PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC , 0x00); - - // PWED_TH -#if IS_RTL8881A_SERIES - if (IS_HARDWARE_TYPE_8881A(Adapter)) { - if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_PWED_TH_AC, BIT3 | BIT2 | BIT1, 0x2); - } - } -#endif - - //PinMux - if (GET_CHIP_VER(Adapter) == VERSION_8881A) { -#if 1 -#ifdef CONFIG_WLAN_HAL_8881A - if ( (HAL_VAR_INTERLPA_8881A == 1 && (get_bonding_type_8881A() != BOND_8881AB)) -#ifdef CONFIG_8881A_HP - || HAL_VAR_HP_8881A == 1 -#endif - ) { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x54); - panic_printk("8881A internal PA PIN control or 8881A high power\n"); - } else -#endif - { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x55); - panic_printk("8881A external PA PIN control :87503 or RTC 5634\n"); - } - - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x1); -#else - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf0, 0x4); - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x5); -#endif - } else if (GET_CHIP_VER(Adapter) == VERSION_8812E) { - if (IS_HAL_TEST_CHIP(Adapter)) { - // r_select_5G for path_A/B - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT12, 0x1); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT12, 0x1); - - // LANON (5G uses external LNA) - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT15, 0x0); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT15, 0x0); - } else { - // TODO: Eric check PA type fill reg[REG_BB_RA_RFE_PINMUX] - if (HAL_VAR_PA_TYPE == PA_RFMD_4501 || HAL_VAR_PA_TYPE == PA_SKYWORKS_85712_HP) { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x53); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x53); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x54); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x54); - } - } - } else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { - panic_printk("5G RFE TYPE\n"); -#ifdef HIGH_POWER_EXT_PA -#ifdef HIGH_POWER_EXT_LNA - //3 RFE Type - if (Adapter->pshare->rf_ft_var.use_ext_pa && Adapter->pshare->rf_ft_var.use_ext_lna) { - switch(Adapter->pmib->dot11RFEntry.rfe_type){ - case 3: - case 5: - panic_printk("TRSWITCH: RFE TYPE 3 or 5\n"); - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77177717); - PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x54); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] - break; - case 2: - case 4: - case 8: - panic_printk("TRSWITCH: RFE TYPE 2 or 4 or 8\n"); - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77177717); - PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x37); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] - break; - default: - GDEBUG("TRSWITCH: Unknown RFE type (%d)!\n", Adapter->pmib->dot11RFEntry.rfe_type); - break; - } - // TODO: high power setting - } else -#endif -#endif - //3 RFE Type 7 or 9 - { - panic_printk("TRSWITCH: RFE TYPE 7 or 9\n"); - PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) - PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] - // RFE type 0 - PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); - PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); - PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); - PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); - PHY_SetBBReg_88XX(Adapter, 0x1abc, 0xFF00000, 0x54); // 0x1ABC[27:20] - } - //else { - // RT_TRACE(COMP_RF, DBG_WARNING,("Error: No set BB register\n")); - //} - - PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC|BIT_MASK_BB_BOFDMEN_AC , 0x2); - PHY_SetBBReg_88XX(Adapter, REG_BB_FC_ENABL_VHT_AC, BIT17 ,0x0); - } - } -} - - - -void UpdateBBRFVal88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel, - IN s4Byte offset -) -{ - -#if (RTL8822B_SUPPORT == 1) - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - - int val = channel; - - if (channel > 14) - HAL_VAR_CURR_BAND = RF88XX_BAND_ON_5G; - else - HAL_VAR_CURR_BAND = RF88XX_BAND_ON_2_4G; - if (!Adapter->pshare->rf_ft_var.mp_specific) - { - if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_80) { - if (channel <= 48) - val = 42; - else if (channel <= 64) - val = 58; - else if (channel <= 112) - val = 106; - else if (channel <= 128) - val = 122; - else if (channel <= 144) - val = 138; - else if (channel <= 161) - val = 155; - else if (channel <= 177) - val = 171; - } else if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_20_40) { - if (offset == 1) - val -= 2; - else - val += 2; - } - - if (HAL_VAR_USE_FRQ_2_3G) { - val += 14; - } - } - //eric-8822 ?? what shall MAC do during swchnl?? - config_phydm_switch_band_8822b((&(Adapter->pshare->_dmODM)), val); - config_phydm_switch_channel_8822b((&(Adapter->pshare->_dmODM)), val); - return; - } -#endif - - CheckBand88XX_AC(Adapter, channel); - - SetChannelPara88XX_AC(Adapter, channel, offset); - - HAL_VAR_pre_channel = channel; - -} - -#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) -void -SetCurrentTxAGC( - IN HAL_PADAPTER Adapter, - IN u1Byte txPathIdx, - IN u1Byte txRate, - IN u1Byte power -) -{ - if(txRate <= TX_AGC_CCK_11M){ - Adapter->pshare->phw->CurrentTxAgcCCK[txPathIdx][txRate] = power; - }else if(txRate <= TX_AGC_OFDM_54M){ - Adapter->pshare->phw->CurrentTxAgcOFDM[txPathIdx][txRate - TX_AGC_OFDM_6M] = power; - }else if(txRate <= TX_AGC_HT_NSS4_MCS31 ){ - Adapter->pshare->phw->CurrentTxAgcMCS[txPathIdx][txRate - TX_AGC_HT_NSS1_MCS0] = power; - }else if(txRate <= TX_AGC_VHT_NSS4_MCS9){ - Adapter->pshare->phw->CurrentTxAgcVHT[txPathIdx][txRate - TX_AGC_VHT_NSS1_MCS0] = power; - } -} - - -void -PHYSetTxPower88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte txRateStart, - IN u1Byte txRateEnd, - IN u1Byte txPathIdx, - IN u1Byte defPower -) -{ - u1Byte i = 0; - u1Byte tx_path_idx = txPathIdx; // select path a/b/c/d - u1Byte tx_none = 0x1; - u1Byte tx_write = 0x1; - u1Byte def_power = defPower; - u4Byte value32 = 0; - -#if 0 - printk("[%s] Path %u, rate from 0x%x to 0x%x: 0x%x\n", __FUNCTION__, tx_path_idx+1, txRateStart, txRateEnd, def_power); -#endif - - -#if (RTL8822B_SUPPORT == 1) - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - for (i = txRateStart; i <= txRateEnd; i++) { - phydm_write_txagc_1byte_8822b((&(Adapter->pshare->_dmODM)), defPower, txPathIdx, i); - SetCurrentTxAGC(Adapter,tx_path_idx,i,def_power); - } - return; - } -#endif - - // before write data, we must add extra one write commnad to "turn on" the AGC table - // TODO: this can be moved to other place ?? ex: after init done ? - HAL_RTL_W32(REG_BB_TXAGC_V2_BASE_ADDR, FILL_REG_BB_TXAGC_V2(txRateStart, tx_path_idx, tx_none, tx_write, def_power)); - - for (i = txRateStart; i <= txRateEnd; i++) { - HAL_RTL_W32(REG_BB_TXAGC_V2_BASE_ADDR, FILL_REG_BB_TXAGC_V2(i, tx_path_idx, tx_none, tx_write, def_power)); - SetCurrentTxAGC(Adapter,tx_path_idx,i,def_power); /* Path, Rate, Power */ - } -} -#endif - - -RT_STATUS -PHYSetCCKTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -) -{ - u4Byte def_power = 0x12121212;//0x20202020; - u4Byte writeVal = 0; - u1Byte ch_idx = 0; - u1Byte tmp_TPI = 0; - u1Byte phy_band = 0; - u1Byte bPathXEn[4] = {0}; - u1Byte i; - - u1Byte def_power_value = 0x12; - - u4Byte REG_BB_TXAGC_X_CCK11_CCK1_AC[4] = {REG_BB_TXAGC_A_CCK11_CCK1_AC, REG_BB_TXAGC_B_CCK11_CCK1_AC, - REG_BB_TXAGC_C_CCK11_CCK1_AC, REG_BB_TXAGC_D_CCK11_CCK1_AC - }; - u1Byte HAL_VAR_pwrlevelCCK_X[4] = {HAL_VAR_pwrlevelCCK_A(channel - 1), HAL_VAR_pwrlevelCCK_B(channel - 1), - HAL_VAR_pwrlevelCCK_C(channel - 1), HAL_VAR_pwrlevelCCK_D(channel - 1) - }; - - if (channel > 0) - ch_idx = (channel - 1); - else { - RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel [%x]!\n", channel)); - return RT_STATUS_FAILURE; - } - - if (channel > CHANNEL_MAX_NUMBER_2G) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; - -#if 0 - printk("\n----------------------- CCK Efuse Power ------------------------\n"); - printk("[%s]HAL_VAR_pwrlevelCCK_A(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_A(ch_idx)); - printk("[%s]HAL_VAR_pwrlevelCCK_B(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_B(ch_idx)); - printk("[%s]HAL_VAR_pwrlevelCCK_C(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_C(ch_idx)); - printk("[%s]HAL_VAR_pwrlevelCCK_D(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_D(ch_idx)); -#endif - if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - bPathXEn[0] = 1; - bPathXEn[1] = 0; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if(HAL_VAR_pwrlevelCCK_A(ch_idx) == 0) { - RT_TRACE_F(COMP_RF, DBG_WARNING,("1T1R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); - -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); - } - return RT_STATUS_SUCCESS; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0) || (HAL_VAR_pwrlevelCCK_B(ch_idx) == 0)) { - RT_TRACE_F(COMP_RF, DBG_WARNING,("2T2R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); - -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); - } - return RT_STATUS_SUCCESS; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - if(IS_HARDWARE_TYPE_8814A(Adapter)){ -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - bPathXEn[0] = 0; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelCCK_B(ch_idx)== 0) || (HAL_VAR_pwrlevelCCK_C(ch_idx) == 0)){ - RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); - } - return RT_STATUS_SUCCESS; - } -#else - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevelCCK_B(ch_idx)== 0) || (HAL_VAR_pwrlevelCCK_C(ch_idx) == 0) - ||(HAL_VAR_pwrlevelCCK_D(ch_idx)== 0) - ){ - RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 3, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[3], def_power); - } - return RT_STATUS_SUCCESS; - } -#endif - }else{ - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelCCK_C(ch_idx) == 0) - ) { - RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); - } - return RT_STATUS_SUCCESS; - } - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelCCK_C(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_D(ch_idx) == 0) - ) { - RT_TRACE_F(COMP_RF, DBG_WARNING,("4T4R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); - -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 3, def_power_value); - } else -#endif - { - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[3], def_power); - } - return RT_STATUS_SUCCESS; - } - } - - - if (phy_band == PHY_BAND_2G) { - - for(i = 0; i < 4; i++) { - //PATH X - if(bPathXEn[i]) { -#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES - if ( (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, i, HAL_VAR_pwrlevelCCK_X[i]?HAL_VAR_pwrlevelCCK_X[i]:0x12); - } else -#endif - { - tmp_TPI = HAL_VAR_pwrlevelCCK_X[i]; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[i], writeVal); - } - } - } - } - -#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES - if(IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)){ - TxPG_CCK_8814(Adapter); - }else -#endif - TxPG_CCK_Jaguar(Adapter, bPathXEn); -#if 0//def CONFIG_WLAN_HAL_8814AE - printk("CCK After TxPG_CCK_8814\n"); - for(path=0;path<4;path++){ - printk("\n Path%d\n CCK: ",path); - for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - } - } -#endif //#ifdef CONFIG_WLAN_HAL_8814AE - -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { -#if IS_RTL8814A_SERIES - if(IS_HARDWARE_TYPE_8814A(Adapter)) - TxLMT_CCK_Jaguar_AC_8814(Adapter); - else -#endif - TxLMT_CCK_Jaguar_AC(Adapter, bPathXEn); - } - } -#endif - - - return RT_STATUS_SUCCESS; -} - -RT_STATUS -PHYSetOFDMTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -) -{ - u1Byte ch_idx = 0, no_cali_data = 0; - u1Byte phy_band = 0; - - if (channel > 0) - ch_idx = (channel - 1); - else { - RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel !!\n")); - return RT_STATUS_FAILURE; - } - - if (channel > CHANNEL_MAX_NUMBER_2G) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; -#if 0 - printk("\n----------------------- 5G Efuse Power ------------------------\n"); - - printk("HAL_VAR_pwrlevel5GHT40_1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)); - printk("HAL_VAR_pwrlevel5GHT40_1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)); - printk("HAL_VAR_pwrlevel5GHT40_1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)); - printk("HAL_VAR_pwrlevel5GHT40_1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)); - - printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(ch_idx)); - - printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(ch_idx)); - - printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(ch_idx)); - - printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(ch_idx)); - printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(ch_idx)); - - - printk("\n----------------------- 2G Efuse Power ------------------------\n"); - - printk("HAL_VAR_pwrlevelHT40_1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_A(ch_idx)); - printk("HAL_VAR_pwrlevelHT40_1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_B(ch_idx)); - printk("HAL_VAR_pwrlevelHT40_1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_C(ch_idx)); - printk("HAL_VAR_pwrlevelHT40_1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_D(ch_idx)); - - printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_A(ch_idx)); - printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_B(ch_idx)); - printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_C(ch_idx)); - printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_D(ch_idx)); - printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_D(%d)=%x\n\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_D(ch_idx)); -#endif - - if (phy_band == PHY_BAND_5G) { - if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) == 0) - ) { - no_cali_data = 1; - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - if(IS_HARDWARE_TYPE_8814A(Adapter)){ -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0)) { - no_cali_data = 1; - } -#else - if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) == 0) - ) { - no_cali_data = 1; - } -#endif - }else{ - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) - ) { - no_cali_data = 1; - } - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0)) { - no_cali_data = 1; - - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx) == 0)) { - no_cali_data = 1; - } - } - } else { - if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) - ) { - no_cali_data = 1; - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - if(IS_HARDWARE_TYPE_8814A(Adapter)){ -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)) { - no_cali_data = 1; - } -#else - if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0) - ||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) - ) { - no_cali_data = 1; - } -#endif - }else{ - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0) - ) { - no_cali_data = 1; - } - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0)) { - no_cali_data = 1; - } - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx) == 0)) { - no_cali_data = 1; - } - } - } - - if (phy_band == PHY_BAND_5G) { - CalOFDMTxPower5G_88XX_AC(Adapter, ch_idx); - } else if (phy_band == PHY_BAND_2G) { - CalOFDMTxPower2G_88XX_AC(Adapter, ch_idx); - } - -#if 0 //IS_RTL8822B_SERIES //eric-8822 show tx agc - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - int i = 0, ii=0; - - panic_printk("\n PATH A Power:\n"); - for (i = TX_AGC_OFDM_6M; i <= TX_AGC_VHT_NSS2_MCS9; i++) { - panic_printk("%d ", config_phydm_read_txagc_8822b((&(Adapter->pshare->_dmODM)), 0, i)); - ii++; - if(ii==4){ - ii=0; - panic_printk("\n"); - } - } - - ii = 0; - - panic_printk("\n PATH B Power:\n"); - for (i = TX_AGC_OFDM_6M; i <= TX_AGC_VHT_NSS2_MCS9; i++) { - panic_printk("%d ", config_phydm_read_txagc_8822b((&(Adapter->pshare->_dmODM)), 1, i)); - ii++; - if(ii==4){ - ii=0; - panic_printk("\n"); - } - } - panic_printk("\n"); - } -#endif - - -#if 0//def CONFIG_WLAN_HAL_8814AE - int path, rate; - printk("After CalOFDMTxPower5G_88XX_AC()\n"); - for(path=0;path<4;path++){ - printk("\n Path%d\nCCK: ",path); - for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - } - printk("\n OFDM: "); - for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); - } - printk("\n HT MCS 1SS: "); - for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS1_MCS7;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n HT MCS 2SS: "); - for(rate=TX_AGC_HT_NSS2_MCS8;rate<=TX_AGC_HT_NSS2_MCS15;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n HT MCS 3SS: "); - for(rate=TX_AGC_HT_NSS3_MCS16;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n VHT MCS 1SS: "); - for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS1_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n VHT MCS 2SS: "); - for(rate=TX_AGC_VHT_NSS2_MCS0;rate<=TX_AGC_VHT_NSS2_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n VHT MCS 3SS: "); - for(rate=TX_AGC_VHT_NSS3_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n"); - } -#endif //#ifdef CONFIG_WLAN_HAL_8814AE - - - - - if (!no_cali_data) { - -#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES - if((IS_HARDWARE_TYPE_8814A(Adapter))||(IS_HARDWARE_TYPE_8822BE(Adapter))){ - TxPG_OFDM_8814(Adapter); - -#if 0//def CONFIG_WLAN_HAL_8814AE - int path, rate; - - printk("After TxPG_OFDM_8814()\n"); - for(path=0;path<4;path++){ - printk("\n Path%d\n CCK: ",path); - for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); - } - printk("\n OFDM: "); - for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); - } - printk("\n HT MCS 1SS: "); - for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS1_MCS7;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n HT MCS 2SS: "); - for(rate=TX_AGC_HT_NSS2_MCS8;rate<=TX_AGC_HT_NSS2_MCS15;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n HT MCS 3SS: "); - for(rate=TX_AGC_HT_NSS3_MCS16;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); - } - printk("\n VHT MCS 1SS: "); - for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS1_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n VHT MCS 2SS: "); - for(rate=TX_AGC_VHT_NSS2_MCS0;rate<=TX_AGC_VHT_NSS2_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n VHT MCS 3SS: "); - for(rate=TX_AGC_VHT_NSS3_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ - printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); - } - printk("\n"); - } -#endif //#ifdef CONFIG_WLAN_HAL_8814AE - }else -#endif - { - // TODO: try to rewrite and combine the functions: TxPG_OFDM_Jaguar_A, B, C, D - if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - TxPG_OFDM_Jaguar_A(Adapter); - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - TxPG_OFDM_Jaguar_A(Adapter); - TxPG_OFDM_Jaguar_B(Adapter); - } -#if IS_RTL8814A_SERIES - else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - TxPG_OFDM_Jaguar_A(Adapter); - TxPG_OFDM_Jaguar_B(Adapter); - TxPG_OFDM_Jaguar_C(Adapter); - } else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - TxPG_OFDM_Jaguar_A(Adapter); - TxPG_OFDM_Jaguar_B(Adapter); - TxPG_OFDM_Jaguar_C(Adapter); - TxPG_OFDM_Jaguar_D(Adapter); - } -#endif - } - -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { -#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES - if((IS_HARDWARE_TYPE_8814A(Adapter))||(IS_HARDWARE_TYPE_8822B(Adapter))) - TxLMT_OFDM_Jaguar_AC_8814(Adapter); - else -#endif - TxLMT_OFDM_Jaguar_AC(Adapter); - - } - } -#endif - } - return RT_STATUS_SUCCESS; -} - -#if RTL8881A_SUPPORT -RT_STATUS -AddTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN s1Byte index -) -{ - - char add_index; - unsigned char b1, b2, b3, b4, b5; - unsigned char* tmp_b1 = &b1; - unsigned char* tmp_b2 = &b2; - unsigned char* tmp_b3 = &b3; - unsigned char* tmp_b4 = &b4; - unsigned char* tmp_b5 = &b5; - unsigned int tmp_dw = 0; - unsigned int tmp_dw1 = 0; - unsigned int writeVal = 0; - - add_index = index - Adapter->pshare->rf_ft_var.pwrtrk_TxAGC; - Adapter->pshare->rf_ft_var.pwrtrk_TxAGC = index; - - - //printk("TxPG_OFDM_8812_A!!\n"); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS3_MCS0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS3_MCS0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS7_MCS4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS7_MCS4_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS11_MCS8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS8_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, writeVal); - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, writeVal); - - tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC); - get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); - *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); - *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); - *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); - *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); - writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; - HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, writeVal); - - - - return RT_STATUS_SUCCESS; - -} -#endif - -void -CalOFDMTxPower5G_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte ch_idx -) -{ - u1Byte tmp_TPI = 0; - u1Byte pwr_40_1s = 0, pwr_80_1s = 0, ch_idx_ht40 = 0, ch_idx_vht80 = 0; - s1Byte diff_ofdm_1t = 0; - s1Byte diff_bw40_2s = 0; - s1Byte diff_bw40_3s = 0; - s1Byte diff_bw20_1s = 0; - s1Byte diff_bw20_2s = 0; - s1Byte diff_bw20_3s = 0; - s1Byte diff_bw80_1s = 0; - s1Byte diff_bw80_2s = 0; - s1Byte diff_bw80_3s = 0; - u4Byte writeVal = 0; - u1Byte bPathXEn[4] = {0}; - ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (HAL_VAR_DOT11CHANNEL-2) : (HAL_VAR_DOT11CHANNEL+2)) -1; - ch_idx_vht80 = get_center_channel(Adapter, HAL_VAR_DOT11CHANNEL, HAL_VAR_OFFSET_2ND_CHANNEL, 1) -1; - - u1Byte i; - u1Byte HAL_VAR_pwrlevel5GHT40_1S_X[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx), - HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) - }; - /* for 40M*/ - u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_40M[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_ht40), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_ht40), - HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_ht40), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_ht40) - }; - /* for 80M*/ - u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_A[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_vht80-4), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_vht80-4), - HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_vht80-4), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_vht80-4) - }; - u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_B[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_vht80+4), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_vht80+4), - HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_vht80+4), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_vht80+4) - }; - s1Byte HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[4] = {HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(ch_idx), HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(ch_idx), - HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(ch_idx), HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[4] = {HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(ch_idx), HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(ch_idx), - HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(ch_idx), HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_X[4] = {HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(ch_idx), - HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_X[4] = {HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(ch_idx), - HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[4] = {HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(ch_idx)}; - s1Byte HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_X[4] = {HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(ch_idx)}; - - - if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)== 0) - ) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - if(IS_HARDWARE_TYPE_8814A(Adapter)){ -#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) - bPathXEn[0] = 0; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0)){ - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } -#else - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)== 0) - ){ - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } -#endif - }else - - { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) - ) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0)) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - bPathXEn[0] = 1; - bPathXEn[1] = 0; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - - for (i = 0; i < 4; i++) { - // PATH i, OFDM - if(bPathXEn[i]) { - pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - diff_ofdm_1t = (HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[i] & 0x0f); - diff_ofdm_1t = convert_diff_88XX_AC(diff_ofdm_1t); - tmp_TPI = pwr_40_1s + diff_ofdm_1t; - //tmp_TPI = HAL_POWER_RANGE_CHECK(tmp_TPI ); -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_OFDM_54M, i, tmp_TPI); - } else -#endif - { - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_X_88XX_AC(Adapter, writeVal, i); - } - } - } - - //3 20M - if (HAL_VAR_CurrentChannelBW == 0) { - - for (i = 0; i < 4; i++) { - if(bPathXEn[i]) { - //PATH i, BW20-1S - - pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - //printk("[%s]pwr_40_1s=%x\n",__FUNCTION__,pwr_40_1s); - diff_bw20_1s = ((HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[i] & 0xf0) >> 4); - //printk("[%s]diff_bw20_1s=%x\n",__FUNCTION__,diff_bw20_1s); - diff_bw20_1s = convert_diff_88XX_AC(diff_bw20_1s); - tmp_TPI = pwr_40_1s + diff_bw20_1s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - //printk("[%s]writeVal=%x\n",__FUNCTION__,writeVal); -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); - } else -#endif - { - Write_1S_X_88XX_AC(Adapter, writeVal, i); - } - - //PATH i, BW20-2S - diff_bw20_2s = (HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[i] & 0x0f); - //printk("[%s]diff_bw20_2s=%x\n",__FUNCTION__,diff_bw20_2s); - - diff_bw20_2s = convert_diff_88XX_AC(diff_bw20_2s); - tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); - } else -#endif - { - Write_2S_X_88XX_AC(Adapter, writeVal, i); - } - -#if IS_RTL8814A_SERIES - //PATH i, BW20-3S - diff_bw20_3s = (HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[i] & 0x0f); - diff_bw20_3s = convert_diff_88XX_AC(diff_bw20_3s); - tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s + diff_bw20_3s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); - } else - { - Write_3S_X_88XX_AC(Adapter, writeVal, i); - } -#endif - } - } - //3 40M - } else if (HAL_VAR_CurrentChannelBW == 1) { - for (i = 0; i < 4; i++) { - if(bPathXEn[i]) { - //PATH i, BW40-1S - pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X_40M[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); - } else -#endif - { - Write_1S_X_88XX_AC(Adapter, writeVal, i); - } - - //PATH i, BW40-2S - diff_bw40_2s = ((HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[i] & 0xf0) >> 4); - diff_bw40_2s = convert_diff_88XX_AC(diff_bw40_2s); - tmp_TPI = pwr_40_1s + diff_bw40_2s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); - } else -#endif - { - Write_2S_X_88XX_AC(Adapter, writeVal, i); - } - -#if defined(CONFIG_WLAN_HAL_8814AE) - //PATH i, BW40-3S - diff_bw40_3s = ((HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[i] & 0xf0) >> 4); - diff_bw40_3s = convert_diff_88XX_AC(diff_bw40_3s); - tmp_TPI = pwr_40_1s + diff_bw40_2s + diff_bw40_3s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); - } else -#endif - { - Write_3S_X_88XX_AC(Adapter, writeVal, i); - } -#endif - } - } - } - //3 80M - else if (HAL_VAR_CurrentChannelBW == 2) { - - - for (i = 0; i < 4; i++) { - if(bPathXEn[i]) { - //PATH X, BW80-1S - pwr_40_1s = (HAL_VAR_pwrlevel5GHT40_1S_X_A[i] + - HAL_VAR_pwrlevel5GHT40_1S_X_B[i]) / 2 ; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - diff_bw80_1s = ((HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_X[i] & 0xf0) >> 4); - diff_bw80_1s = convert_diff_88XX_AC(diff_bw80_1s); - tmp_TPI = pwr_40_1s + diff_bw80_1s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); - } else -#endif - { - Write_1S_X_88XX_AC(Adapter, writeVal, i); - } - - //PATH X, BW80-2S - diff_bw80_2s = ((HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_X[i] & 0xf0) >> 4); - diff_bw80_2s = convert_diff_88XX_AC(diff_bw80_2s); - tmp_TPI = pwr_40_1s + diff_bw80_1s + diff_bw80_2s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); - } else -#endif - { - Write_2S_X_88XX_AC(Adapter, writeVal, i); - } - -#if defined(CONFIG_WLAN_HAL_8814AE) - //PATH X, BW80-2S - diff_bw80_3s = ((HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_X[i] & 0xf0) >> 4); - diff_bw80_3s = convert_diff_88XX_AC(diff_bw80_3s); - //panic_printk("diff_bw80_3s=%c, %d\n",diff_bw80_3s,diff_bw80_3s); - tmp_TPI = pwr_40_1s + diff_bw80_1s + diff_bw80_2s +diff_bw80_3s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); - } else -#endif - { - Write_3S_X_88XX_AC(Adapter, writeVal, i); - } - -#endif - } - } - } -} - -void -CalOFDMTxPower2G_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte ch_idx -) -{ - u1Byte tmp_TPI = 0; - u1Byte pwr_40_1s = 0, ch_idx_ht40 = 0; - s1Byte diff_ofdm_1t = 0; - s1Byte diff_bw40_2s = 0; - s1Byte diff_bw40_3s = 0; - s1Byte diff_bw20_1s = 0; - s1Byte diff_bw20_2s = 0; - s1Byte diff_bw20_3s = 0; - u4Byte writeVal = 0; - u1Byte bPathXEn[4] = {0}; - u1Byte i; - - ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (HAL_VAR_DOT11CHANNEL-2) : (HAL_VAR_DOT11CHANNEL+2)) -1; - - u1Byte HAL_VAR_pwrlevelHT40_1S_X[4] = {HAL_VAR_pwrlevelHT40_1S_A(ch_idx), HAL_VAR_pwrlevelHT40_1S_B(ch_idx), - HAL_VAR_pwrlevelHT40_1S_C(ch_idx), HAL_VAR_pwrlevelHT40_1S_D(ch_idx) - }; - /* for 40M*/ - u1Byte HAL_VAR_pwrlevelHT40_1S_X_40M[4] = {HAL_VAR_pwrlevelHT40_1S_A(ch_idx_ht40), HAL_VAR_pwrlevelHT40_1S_B(ch_idx_ht40), - HAL_VAR_pwrlevelHT40_1S_C(ch_idx_ht40), HAL_VAR_pwrlevelHT40_1S_D(ch_idx_ht40) - }; - s1Byte HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[4] = {HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(ch_idx), HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(ch_idx), - HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(ch_idx), HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_40BW2S_20BW2S_X[4] = {HAL_VAR_pwrdiff_40BW2S_20BW2S_A(ch_idx), HAL_VAR_pwrdiff_40BW2S_20BW2S_B(ch_idx), - HAL_VAR_pwrdiff_40BW2S_20BW2S_C(ch_idx), HAL_VAR_pwrdiff_40BW2S_20BW2S_D(ch_idx) - }; - s1Byte HAL_VAR_pwrdiff_40BW3S_20BW3S_X[4] = {HAL_VAR_pwrdiff_40BW3S_20BW3S_A(ch_idx), HAL_VAR_pwrdiff_40BW3S_20BW3S_B(ch_idx), - HAL_VAR_pwrdiff_40BW3S_20BW3S_C(ch_idx), HAL_VAR_pwrdiff_40BW3S_20BW3S_D(ch_idx) - }; - - if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) - ) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { - if(IS_HARDWARE_TYPE_8814A(Adapter)){ -#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) - bPathXEn[0] = 0; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)){ - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } -#else - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 1; - if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0) - ||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx)== 0) - ){ - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } -#endif - }else{ - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 1; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) - ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0) - ) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - bPathXEn[0] = 1; - bPathXEn[1] = 1; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0)) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { - bPathXEn[0] = 1; - bPathXEn[1] = 0; - bPathXEn[2] = 0; - bPathXEn[3] = 0; - if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)) { - use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); - return; - } - } - - - for(i = 0; i < 4; i++) { - // PATH X, OFDM - if(bPathXEn[i]) { - pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - diff_ofdm_1t = (HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[i] & 0x0f); - diff_ofdm_1t = convert_diff_88XX_AC(diff_ofdm_1t); - tmp_TPI = pwr_40_1s + diff_ofdm_1t; - //tmp_TPI = HAL_POWER_RANGE_CHECK(tmp_TPI ); -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_OFDM_54M, i, tmp_TPI); - } else -#endif - { - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; - Write_OFDM_X_88XX_AC(Adapter, writeVal, i); - } - } - } - //3 20M - if (HAL_VAR_dot11nUse40M == 0) { - - for (i = 0; i < 4; i++) { - if(bPathXEn[i]) { - //PATH A, BW20-1S - pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - diff_bw20_1s = ((HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[i] & 0xf0) >> 4); - diff_bw20_1s = convert_diff_88XX_AC(diff_bw20_1s); - tmp_TPI = pwr_40_1s + diff_bw20_1s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); - } else -#endif - { - Write_1S_X_88XX_AC(Adapter, writeVal, i); - } - - //PATH A, BW20-2S - diff_bw20_2s = (HAL_VAR_pwrdiff_40BW2S_20BW2S_X[i] & 0x0f); - diff_bw20_2s = convert_diff_88XX_AC(diff_bw20_2s); - tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); - } else -#endif - { - Write_2S_X_88XX_AC(Adapter, writeVal, i); - } - -#if defined(CONFIG_WLAN_HAL_8814AE) - //PATH i, BW20-3S - diff_bw20_3s = (HAL_VAR_pwrdiff_40BW3S_20BW3S_X[i] & 0x0f); - diff_bw20_3s = convert_diff_88XX_AC(diff_bw20_3s); - tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s + diff_bw20_3s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); - } else -#endif - { - Write_3S_X_88XX_AC(Adapter, writeVal, i); - } -#endif - } - } - //3 40M - } else if (HAL_VAR_dot11nUse40M == 1) { - for (i = 0; i < 4; i++) { - if(bPathXEn[i]) { - //PATH A, BW40-1S - pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X_40M[i]; - if(pwr_40_1s == 0) - pwr_40_1s = 0x12; - tmp_TPI = pwr_40_1s ; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); - } else -#endif - { - Write_1S_X_88XX_AC(Adapter, writeVal, i); - } - - //PATH A, BW40-2S - diff_bw40_2s = ((HAL_VAR_pwrdiff_40BW2S_20BW2S_X[i] & 0xf0) >> 4); - diff_bw40_2s = convert_diff_88XX_AC(diff_bw40_2s); - tmp_TPI = pwr_40_1s + diff_bw40_2s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) - if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| - ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); - } else -#endif - { - Write_2S_X_88XX_AC(Adapter, writeVal, i); - } - -#if defined(CONFIG_WLAN_HAL_8814AE) - //PATH i, BW40-3S - diff_bw40_3s = ((HAL_VAR_pwrdiff_40BW3S_20BW3S_X[i] & 0xf0) >> 4); - diff_bw40_3s = convert_diff_88XX_AC(diff_bw40_3s); - tmp_TPI = pwr_40_1s + diff_bw40_2s + diff_bw40_3s; - writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); - PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); - } else -#endif - { - Write_3S_X_88XX_AC(Adapter, writeVal, i); - } -#endif - } - } - - } -} - - - -s1Byte -convert_diff_88XX_AC( - IN s1Byte value -) -{ - // range from -8 ~ 7 - if (value <= 7) - return value; - else - return (value - 16); -} - -void -Write_OFDM_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -) -{ - u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; - u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; - - HAL_RTL_W32(REG_BB_TXAGC_X_OFDM18_OFDM6_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx], writeVal); -} - -void -Write_1S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -) -{ - u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; - u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; - u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; - u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; - HAL_RTL_W32(REG_BB_TXAGC_X_MCS3_MCS0_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx], writeVal); - // TODO: compare with Write_2S_X_88XX_AC, why don't we write only NSS1 (reference to Write_2S_X_88XX_AC) - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], writeVal); -} - - -void -Write_2S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -) -{ - u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; - u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_D_MCS15_MCS12_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; - - HAL_RTL_W32(REG_BB_TXAGC_X_MCS11_MCS8_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx], writeVal); - writeVal = (writeVal & 0xffff0000) | (HAL_RTL_R32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx]) & 0xffff); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], writeVal); -} - -void -Write_3S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -) -{ - u4Byte REG_BB_TXAGC_X_MCS19_MCS16_AC[4] = {REG_BB_TXAGC_A_MCS19_MCS16_AC, REG_BB_TXAGC_B_MCS19_MCS16_AC, REG_BB_TXAGC_C_MCS19_MCS16_AC, REG_BB_TXAGC_D_MCS19_MCS16_AC}; - u4Byte REG_BB_TXAGC_X_MCS23_MCS20_AC[4] = {REG_BB_TXAGC_A_MCS23_MCS20_AC, REG_BB_TXAGC_B_MCS23_MCS20_AC, REG_BB_TXAGC_C_MCS23_MCS20_AC, REG_BB_TXAGC_D_MCS23_MCS20_AC}; - u4Byte REG_BB_TXAGC_X_NSS3INDEX3_NSS3INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_B_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_C_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_D_NSS3INDEX3_NSS3INDEX0_AC}; - u4Byte REG_BB_TXAGC_X_NSS3INDEX7_NSS3INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_B_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_C_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_D_NSS3INDEX7_NSS3INDEX4_AC}; - u4Byte REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_B_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_C_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_D_NSS3INDEX9_NSS3INDEX8_AC}; - - HAL_RTL_W32(REG_BB_TXAGC_X_MCS19_MCS16_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS23_MCS20_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX3_NSS3INDEX0_AC[bPathXEnIdx], writeVal); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX7_NSS3INDEX4_AC[bPathXEnIdx], writeVal); - writeVal = (writeVal & 0xffff) | (HAL_RTL_R32(REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[bPathXEnIdx]) & 0xffff0000); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[bPathXEnIdx], writeVal); -} - -void -use_DefaultOFDMTxPowerPathX88XX_AC( - IN HAL_PADAPTER Adapter, - IN pu1Byte bPathXEn -) -{ - u4Byte def_power = 0x20202020; //eric-8822 ?? //0x12121212; //0x20202020; - u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; - u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; - u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; - u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; - u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; - u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC}; - u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; - u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; - u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; - u1Byte i; - - u1Byte def_power_value = 0x16; - - for (i = 0; i < 4; i++) { - if (bPathXEn[i]) { -#if IS_RTL8814A_SERIES - if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { - PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_VHT_NSS4_MCS9, i, def_power_value); - } else -#endif -#if IS_RTL8822B_SERIES //eric-8822 - if ( IS_HARDWARE_TYPE_8822BE(Adapter)) { -#if 1 - if(i == 0 && Adapter->pshare->rf_ft_var.txa) - def_power_value = Adapter->pshare->rf_ft_var.txa; - - if(i == 1 && Adapter->pshare->rf_ft_var.txb) - def_power_value = Adapter->pshare->rf_ft_var.txb; - -#endif - PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_VHT_NSS2_MCS9, i, def_power_value); - } else -#endif - - { - HAL_RTL_W32(REG_BB_TXAGC_X_OFDM18_OFDM6_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS3_MCS0_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS7_MCS4_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS11_MCS8_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_MCS15_MCS12_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[i], def_power); - HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[i], def_power); - } - } - } -} - -#endif //#if IS_RTL88XX_AC - - -#if IS_RTL88XX_N - -void -phy_RFSerialWrite_88XX_N -( - IN HAL_PADAPTER Adapter, - IN RFRF88XX_RADIO_PATH_E eRFPath, - IN u4Byte Offset, - IN u4Byte Data -) -{ - u4Byte DataAndAddr = 0; - u4Byte NewOffset; - - Offset &= 0xff; - - // - // Switch page for 8256 RF IC - // - NewOffset = Offset; - - // - // Put write addr in [5:0] and write data in [31:16] - // - //DataAndAddr = (Data<<16) | (NewOffset&0x3f); - DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; // T65 RF - - // - // Write Operation - // - if (eRFPath == RF88XX_PATH_A) { - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_LSSIPARAMETER_N, BIT_MASK_SET_MASKDWORD_COMMON, DataAndAddr); - } else { - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_LSSIPARAMETER_N, BIT_MASK_SET_MASKDWORD_COMMON, DataAndAddr); - } -} - -u4Byte -phy_RFSerialRead_88XX_N -( - IN HAL_PADAPTER Adapter, - IN RFRF88XX_RADIO_PATH_E eRFPath, - IN u4Byte Offset -) -{ - u4Byte tmplong, tmplong2; - u4Byte retValue = 0; - u4Byte NewOffset; - - // - // Make sure RF register offset is correct - // - - Offset &= 0xff; - - - // - // Switch page for 8256 RF IC - // - NewOffset = Offset; - - // For 92S LSSI Read RFLSSIRead - // For RF A/B write 0x824/82c(does not work in the future) - // We must use 0x824 for RF A and B to execute read trigger - // 1. PathA : addr write 0x824, Path B : addr write 0x82c - - if (eRFPath == RF88XX_PATH_A) { - tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON);; - tmplong2 = (tmplong2 & (~BIT_MASK_BB_LSSIREADADDRESS_N)) | (NewOffset << 23) | BIT_MASK_BB_LSSIREADEDGE_N; //T65 RF - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); - } else { - tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XB_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON); - tmplong2 = (tmplong2 & (~BIT_MASK_BB_LSSIREADADDRESS_N)) | (NewOffset << 23) | BIT_MASK_BB_LSSIREADEDGE_N; //T65 RF - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); - } - - tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON); - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 | BIT_MASK_BB_LSSIREADEDGE_N); - - delay_us(20); - - // 1. Path A, PI mode read data from 0x8b8 - // 2. Path A, SI mode read data from 0x8a0 - // 3. Path B, PI mode read data from 0x8bc - // 4. Path B, SI mode read data from 0x8a4 - - if (eRFPath == RF88XX_PATH_A) { - if ((HAL_RTL_R32(REG_BB_FPGA0_XA_HSSIPARAMETER1_N)&BIT(8))) { - retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_TRANSCEIVERA_HSPI_READBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); - } else { - retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_LSSIREADBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); - } - } else if (eRFPath == RF88XX_PATH_B) { - if ((HAL_RTL_R32(REG_BB_FPGA0_XB_HSSIPARAMETER1_N)&BIT(8))) { - retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_TRANSCEIVERB_HSPI_READBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); - } else { - retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XB_LSSIREADBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); - } - } - - - return retValue; -} - -void PHY_SetRFReg_88XX_N -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -) -{ - u4Byte Original_Value, BitShift, New_Value; - HAL_PADAPTER priv = Adapter; - u4Byte flags; - -#if CFG_HAL_DISABLE_BB_RF - return; -#endif //CFG_HAL_DISABLE_BB_RF - - HAL_SAVE_INT_AND_CLI(flags); - - if (BitMask != BIT_MASK_SET_MASK20BITS_COMMON) { - Original_Value = phy_RFSerialRead_88XX_N(Adapter, eRFPath, RegAddr); - BitShift = phy_CalculateBitShift_88XX(BitMask); - New_Value = ((Original_Value & (~BitMask)) | (Data << BitShift)); - - phy_RFSerialWrite_88XX_N(Adapter, eRFPath, RegAddr, New_Value); - } else { - phy_RFSerialWrite_88XX_N(Adapter, eRFPath, RegAddr, Data); - } - - HAL_RESTORE_INT(flags); - delay_us(4); // At least 500ns delay to avoid RF write fail. -} - -u4Byte -PHY_QueryRFReg_88XX_N -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - HAL_PADAPTER priv = Adapter; - u4Byte flags; - u4Byte Original_Value, Readback_Value, BitShift; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - - HAL_SAVE_INT_AND_CLI(flags); - Original_Value = phy_RFSerialRead_88XX_N(Adapter, eRFPath, RegAddr); - BitShift = phy_CalculateBitShift_88XX(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - HAL_RESTORE_INT(flags); - - return (Readback_Value); -} - -RT_STATUS -PHYSetOFDMTxPower88XX_N( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -) -{ - u4Byte writeVal, defValue = 0x28, pwrdiff = 0x06060606; - u1Byte offset, ch_idx=0, ch_idx_ht40=0; - u1Byte pwrlevelHT40_1S_A = 0; - u1Byte pwrlevelHT40_1S_B = 0; - u1Byte pwrdiffHT40_2S = 0; - u1Byte pwrdiffHT20 = HAL_VAR_pwrdiffHT20(channel - 1); - u1Byte pwrdiffOFDM = HAL_VAR_pwrdiffOFDM(channel - 1); - u1Byte base, byte0, byte1, byte2, byte3; - u1Byte phy_band = 0, is_coexist = 0; - PRTL8192CD_PRIV priv = Adapter; -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - s1Byte pwrdiff_percent = HAL_PwrPercent2PwrLevel(HAL_VAR_power_percent); -#endif - - if (channel > 0) { - ch_idx = (channel - 1); - ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (channel-2) : (channel+2)) -1; - } else { - RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel !!\n")); - return RT_STATUS_FAILURE; - } - - if (channel > CHANNEL_MAX_NUMBER_2G) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; - - -#ifdef WIFI_11N_2040_COEXIST - if(COEXIST_ENABLE && (((HAL_OPMODE & WIFI_AP_STATE) && - (Adapter->bg_ap_timeout || orForce20_Switch20Map(Adapter) - )) - )) - is_coexist = 1; -#endif - - if ((HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) || is_coexist) { - pwrlevelHT40_1S_A = HAL_VAR_pwrlevelHT40_1S_A(ch_idx); - pwrlevelHT40_1S_B = HAL_VAR_pwrlevelHT40_1S_B(ch_idx); - pwrdiffHT40_2S = HAL_VAR_pwrdiffHT40_2S(ch_idx); - } else if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { - pwrlevelHT40_1S_A = HAL_VAR_pwrlevelHT40_1S_A(ch_idx_ht40); - pwrlevelHT40_1S_B = HAL_VAR_pwrlevelHT40_1S_B(ch_idx_ht40); - pwrdiffHT40_2S = HAL_VAR_pwrdiffHT40_2S(ch_idx_ht40); - } - - if ((pwrlevelHT40_1S_A == 0) ) - - { - // use default value - -#if CFG_HAL_HIGH_POWER_EXT_PA - if (HAL_VAR_use_ext_pa) - defValue = HP_OFDM_POWER_DEFAULT ; -#endif -#if (!CFG_HAL_ADD_TX_POWER_BY_CMD) - writeVal = (defValue << 24) | (defValue << 16) | (defValue << 8) | (defValue); - HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); -#else - - base = defValue; - byte0 = byte1 = byte2 = byte3 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_ofdm_18); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_ofdm_12); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_ofdm_9); - HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_ofdm_6); - - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); - - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); - - byte0 = byte1 = byte2 = byte3 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_ofdm_54); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_ofdm_48); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_ofdm_36); - HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_ofdm_24); - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); - - byte0 = byte1 = byte2 = byte3 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_mcs_3); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_mcs_2); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_mcs_1); - HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_mcs_0); - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); - - byte0 = byte1 = byte2 = byte3 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_mcs_7); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_mcs_6); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_mcs_5); - HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_mcs_4); - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); - - byte0 = byte1 = byte2 = byte3 = 0; - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); - - byte0 = byte1 = byte2 = byte3 = 0; - byte0 = HAL_POWER_RANGE_CHECK(base + byte0); - byte1 = HAL_POWER_RANGE_CHECK(base + byte1); - byte2 = HAL_POWER_RANGE_CHECK(base + byte2); - byte3 = HAL_POWER_RANGE_CHECK(base + byte3); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) - HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); - -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { - TxLMT_OFDM_Jaguar_N(Adapter); - } - } -#endif // TXPWR_LMT - -#endif // ADD_TX_POWER_BY_CMD - return RT_STATUS_SUCCESS; // use default - } - - /****************************** PATH A ******************************/ - base = pwrlevelHT40_1S_A; - offset = (pwrdiffOFDM & 0x0f); - base = HAL_COUNT_SIGN_OFFSET(base, offset); -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); -#endif - - // fill 6Mbps ~ 18Mbps - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(0)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(1)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(2)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(3)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); - - // fill 24Mbps ~ 54Mbps - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(4)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(5)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(6)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(7)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); - - // cal HT rate diff - base = pwrlevelHT40_1S_A; - if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) { - offset = (pwrdiffHT20 & 0x0f); - base = HAL_COUNT_SIGN_OFFSET(base, offset); - } -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); -#endif - - // fill MCS0~MCS3 - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(0)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(1)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(2)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(3)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); - - // fill MCS4~MCS7 - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(4)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(5)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(6)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(7)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); - - offset = (pwrdiffHT40_2S & 0x0f); - base = HAL_COUNT_SIGN_OFFSET(base, offset); - - - //_TXPWR_REDEFINE ?? MCS 8 - 11, shall NOT add power by rate even NOT USB power ?? - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(8)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(9)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(10)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(11)); - - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - - //DEBUG_INFO("debug e18:%x,%x,[%x,%x,%x,%x],%x\n", offset, base, byte0, byte1, byte2, byte3, writeVal); - HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(12)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(13)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(14)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(15)); - - writeVal = (byte0<<24) | (byte1<<16) |(byte2<<8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); - - /****************************** PATH B ******************************/ - - if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { - - base = pwrlevelHT40_1S_B; - offset = ((pwrdiffOFDM & 0xf0) >> 4); - base = HAL_COUNT_SIGN_OFFSET(base, offset); -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); -#endif - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(0)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(1)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(2)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(3)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(4)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(5)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(6)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(7)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); - - base = pwrlevelHT40_1S_B; - if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) { - offset = ((pwrdiffHT20 & 0xf0) >> 4); - base = HAL_COUNT_SIGN_OFFSET(base, offset); - } -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); -#endif - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(0)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(1)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(2)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(3)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(4)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(5)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(6)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(7)); - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); - - offset = ((pwrdiffHT40_2S & 0xf0) >> 4); - base = HAL_COUNT_SIGN_OFFSET(base, offset); - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(8)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(9)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(10)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(11)); - - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); - - byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(12)); - byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(13)); - byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(14)); - byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(15)); - - writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; - HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); - } -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { - TxLMT_OFDM_Jaguar_N(Adapter); - } - } -#endif // TXPWR_LMT - - return RT_STATUS_SUCCESS; -} - -RT_STATUS -PHYSetCCKTxPower88XX_N( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -) -{ - unsigned int writeVal = 0, pwrdiff = 0x06060606; - u1Byte byte, byte1, byte2; - u1Byte pwrlevelCCK_A = HAL_VAR_pwrlevelCCK_A(channel-1); - u1Byte pwrlevelCCK_B = HAL_VAR_pwrlevelCCK_B(channel-1); -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - s1Byte pwrdiff_percent = HAL_PwrPercent2PwrLevel(HAL_VAR_power_percent); -#endif - u1Byte phy_band = 0; - - if (channel > CHANNEL_MAX_NUMBER_2G) - phy_band = PHY_BAND_5G; - else - phy_band = PHY_BAND_2G; - - if (HAL_cck_pwr_max) { - byte = HAL_POWER_RANGE_CHECK((char)HAL_cck_pwr_max); - writeVal = byte; - Adapter->pshare->rf_ft_var.bcn_pwr_idex=writeVal; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); - writeVal = (byte << 16) | (byte << 8) | byte; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); - writeVal = (byte << 24) | (byte << 16) | (byte << 8) | byte; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); - return RT_STATUS_SUCCESS; - } - - if ((pwrlevelCCK_A == 0 && pwrlevelCCK_B == 0)) { -#if CFG_HAL_HIGH_POWER_EXT_PA - if (HAL_VAR_use_ext_pa) - byte = HP_CCK_POWER_DEFAULT; - else -#endif - byte = 0x24; - - -#if (!CFG_HAL_ADD_TX_POWER_BY_CMD) - // use default value - writeVal = byte; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); - writeVal = (byte << 16) | (byte << 8) | byte; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); - writeVal = (byte << 24) | (byte << 16) | (byte << 8) | byte; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); -#else - // use cmd value - pwrlevelCCK_A = pwrlevelCCK_B = byte; - byte = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_1); - - writeVal = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); - - byte = byte1 = byte2 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_1); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_txPowerPlus_cck_2); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_txPowerPlus_cck_5); - byte = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte); - byte1 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte1); - byte2 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte2); - - writeVal = ((byte2 << 16) | (byte1 << 8) | byte); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); - - byte = byte1 = byte2 = 0; - HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_2); - HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_txPowerPlus_cck_5); - HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_txPowerPlus_cck_11); - byte = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte); - byte1 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte1); - byte2 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte2); - writeVal = ((byte2 << 24) | (byte1 << 16) | (byte << 8) | byte2); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); - -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { - TxLMT_CCK_Jaguar_N(Adapter); - } - } -#endif // TXPWR_LMT - -#endif - { - int cck1a = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00); - int cck1b = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00); - if(cck1a>Adapter->pshare->rf_ft_var.bcn_pwr_max) { - cck1a = Adapter->pshare->rf_ft_var.bcn_pwr_max; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, cck1a); - } - if(cck1b>Adapter->pshare->rf_ft_var.bcn_pwr_max) { - cck1b = Adapter->pshare->rf_ft_var.bcn_pwr_max; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00, cck1b); - } - Adapter->pshare->rf_ft_var.bcn_pwr_idex= max(cck1a,cck1b); - } - return RT_STATUS_SUCCESS; // use default - } -#if CFG_HAL_POWER_PERCENT_ADJUSTMENT - pwrlevelCCK_A = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + pwrdiff_percent); - pwrlevelCCK_B = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + pwrdiff_percent); -#endif - - // use flash value to fill - - writeVal = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(3) + Adapter->pmib->dot11RFEntry.add_cck1M_pwr); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); - writeVal = (HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(1)) << 16) | - (HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(2)) << 8) | - HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(3) + Adapter->pmib->dot11RFEntry.add_cck1M_pwr); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); - writeVal = (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(0)) << 24) | - (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(1)) << 16) | - (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(2)) << 8) | - HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(0)); - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); - -#ifdef TXPWR_LMT - if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { - if (HAL_check_lmt_valid(Adapter, phy_band)) { - TxLMT_CCK_Jaguar_N(Adapter); - } - } -#endif // TXPWR_LMT - - { - int cck1a = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00); - int cck1b = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00); - if(cck1a>Adapter->pshare->rf_ft_var.bcn_pwr_max) { - cck1a = Adapter->pshare->rf_ft_var.bcn_pwr_max; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, cck1a); - } - if(cck1b>Adapter->pshare->rf_ft_var.bcn_pwr_max) { - cck1b = Adapter->pshare->rf_ft_var.bcn_pwr_max; - PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00, cck1b); - } - Adapter->pshare->rf_ft_var.bcn_pwr_idex= max(cck1a,cck1b); - } - - return RT_STATUS_SUCCESS; -} - -#if 0 -void -printk92E(IN HAL_PADAPTER Adapter) -{ - printk("0x440 = %x\n", HAL_RTL_R32(0x440)); - - printk("0x800 = %x\n", HAL_RTL_R32(0x800)); - printk("0xa00 = %x\n", HAL_RTL_R32(0xa00)); - printk("0xd00 = %x\n", HAL_RTL_R32(0xd00)); - printk("0x818 = %x\n", HAL_RTL_R32(0x818)); - printk("0x800 = %x\n", HAL_RTL_R32(0x800)); - - printk("RF TRX_BW RF PathA 0x18=%x \n", PHY_QueryRFReg_88XX_N(Adapter, 0, 0x18, 0xffffffff)); - - printk("RF TRX_BW RF PathB 0x18=%x \n", PHY_QueryRFReg_88XX_N(Adapter, 1, 0x18, 0xffffffff)); - - printk("RF TRX_BW RF PathA 0x18=%x \n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xffffffff, 1)); - - printk("RF TRX_BW RF PathB 0x18=%x \n", PHY_QueryRFReg(Adapter, 1, 0x18, 0xffffffff, 1)); - -} -#endif - -void -SwBWMode88XX_N( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -) -{ - u4Byte eRFPath, curMaxRFPath, val, rrSR = 0; - u1Byte nCur40MhzPrimeSC, regDataSC; - unsigned int dwTmp1 = 0, dwTmp2 = 0, dwTmp3 = 0; - - RT_TRACE(COMP_RF, DBG_TRACE, ("SwBWMode(): Switch to %s bandwidth\n", bandwidth ? "40MHz" : "20MHz")); - - curMaxRFPath = RF88XX_PATH_MAX; - - if (offset == 1) - nCur40MhzPrimeSC = 2; - else - nCur40MhzPrimeSC = 1; - - //3 <1> Set MAC register - rrSR = HAL_RTL_R32(REG_RRSR); - rrSR &= ~(BIT(21) | BIT(22)); - - regDataSC = HAL_RTL_R8(0x483); - - if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { - dwTmp1 = HAL_RTL_R32(0x800); - dwTmp2 = HAL_RTL_R32(0xce4); - dwTmp3 = HAL_RTL_R32(0xc30); - dwTmp1 &= ~(BIT(10) | BIT(9) | BIT(8) | BIT(13) | BIT(12) | BIT(14)); - dwTmp2 &= ~(BIT(31) | BIT(30)); - dwTmp3 &= ~(BIT(10) | BIT(9) | BIT(8)); - } - switch (bandwidth) { - case HT_CHANNEL_WIDTH_20: - if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { - dwTmp3 |= (BIT(10)); - HAL_RTL_W32(0xc30, dwTmp3); - } - break; - case HT_CHANNEL_WIDTH_20_40: - HAL_RTL_W32(REG_RRSR, rrSR); - - regDataSC &= 0xf0; - regDataSC |= Adapter->pshare->txsc_20_92e; - HAL_RTL_W8(0x483, regDataSC); - - // Let 812cd_rx, re-assign value - if (HAL_VAR_IS_40M_BW) { - HAL_VAR_REG_RRSR_2 = 0; - HAL_VAR_REG_81B = 0; - } - if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { - dwTmp3 |= (BIT(10)); - HAL_RTL_W32(0xc30, dwTmp3); - } - break; - if (IS_C_CUT_8192E(Adapter)) { - case HT_CHANNEL_WIDTH_10: - dwTmp1 |= (BIT(10) | BIT(8) | BIT(12) | BIT(14)); - dwTmp2 |= (BIT(31)); - dwTmp3 |= (BIT(10) | BIT(9)); - HAL_RTL_W32(0x800, dwTmp1); - HAL_RTL_W32(0xce4, dwTmp2); - HAL_RTL_W32(0xc30, dwTmp3); - break; - case HT_CHANNEL_WIDTH_5: - dwTmp1 |= (BIT(10) | BIT(8) | BIT(14)); - dwTmp2 |= (BIT(30)); - dwTmp3 |= (BIT(10) | BIT(9) | BIT(8)); - HAL_RTL_W32(0x800, dwTmp1); - HAL_RTL_W32(0xce4, dwTmp2); - HAL_RTL_W32(0xc30, dwTmp3); - break; - } - default: - RT_TRACE(COMP_RF, DBG_LOUD, ("SwBWMode(): bandwidth mode error!\n")); - return; - break; - } - - //3 <2> Set PHY related register - switch (bandwidth) { - case HT_CHANNEL_WIDTH_20: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x0); - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA1_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x0); - val = 3; - break; - case HT_CHANNEL_WIDTH_20_40: - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x1); - PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA1_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x1); - // Set Control channel to upper or lower. These settings are required only for 40MHz - PHY_SetBBReg_88XX(Adapter, REG_BB_CCK0_SYSTEM_N, BIT_MASK_BB_CCKSIDEBAND_N, (nCur40MhzPrimeSC >> 1)); - PHY_SetBBReg_88XX(Adapter, REG_BB_OFDM1_LSTF_N, 0xC00, nCur40MhzPrimeSC); - val = 1; - - PHY_SetBBReg_88XX(Adapter, REG_BB_PRIMESC_N, (BIT(26) | BIT(27)), (nCur40MhzPrimeSC == 2) ? 1 : 2); - break; - default: - RT_TRACE(COMP_RF, DBG_LOUD, ("SwBWMode(): bandwidth mode error! %d\n", __LINE__)); - return; - break; - } - - for (eRFPath = RF88XX_PATH_A; eRFPath < curMaxRFPath; eRFPath++) - PHY_SetRFReg_88XX_N(Adapter, eRFPath, REG_RF_RFCHANNEL_N, (BIT(11) | BIT(10)), val); -} - - - - -/* ---------------------------------- - Power Tracking Realted functions ---------------------------------------*/ -#if 0 -void -TXPowerTracking_ThermalMeter_88XX -( - IN HAL_PADAPTER Adapter -) -{ - u1Byte ThermalValue = 0, delta, channel, is_decrease, rf_mimo_mode; - u1Byte ThermalValue_AVG_count = 0; - u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur - s1Byte OFDM_index[2], index ; - u4Byte ThermalValue_AVG = 0; - u4Byte i = 0, j = 0, rf; - s4Byte value32, CCK_index, ele_A, ele_D, ele_C, X, Y; - PRTL8192CD_PRIV priv = Adapter; - - rf_mimo_mode = GetChipIDMIMO88XX(Adapter); - -#ifdef CFG_HAL_MP_TEST - if ((HAL_OPMODE & WIFI_MP_STATE) || HAL_VAR_MP_SPECIFIC) { - channel = HAL_VAR_WORKING_CHANNEL; - //printk("MP start , channel = %x \n",channel); - if (HAL_VAR_MP_TXPWR_TRACKING == FALSE) - return; - } else -#endif - { - channel = HAL_VAR_DOT11CHANNEL; - } - - if (HAL_VAR_POWER_TRACKING_ON_88XX == 0) { - HAL_VAR_POWER_TRACKING_ON_88XX = 1; - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("TXPowerTracking_ThermalMeter_88XX: First Timer set 0x42\n")); - //printk("First Timer set 0x42\n"); - PHY_SetRFReg_88XX_N(Adapter, RF88XX_PATH_A, REG_RF_CSI_MASK_N, (BIT(17) | BIT(16)), 0x03); - return; - } - //else - { - // HAL_VAR_POWER_TRACKING_ON_88XX = 0; - ThermalValue = (unsigned char)PHY_QueryRFReg_88XX_N(Adapter, RF88XX_PATH_A, REG_RF_CSI_MASK_N, 0xfc00); //0x42: RF Reg[15:10] 88E - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, HAL_VAR_THERMALVALUE, HAL_VAR_THER)); - //printk("\nReadback Thermal Meter = %x \n",ThermalValue); - } - - switch (rf_mimo_mode) { - case MIMO_1T1R: - rf = 1; - //printk("%s:%d get_rf_mimo_mode =1 !\n", __FUNCTION__, __LINE__); - break; - case MIMO_2T2R: - rf = 2; - //printk("%s:%d get_rf_mimo_mode =2 !\n", __FUNCTION__, __LINE__); - break; - default: - //printk("%s:%d get_rf_mimo_mode error!\n", __FUNCTION__, __LINE__); - break; - } - - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKOFDM_D_COMMON); - //printk("0xc80 ele_D = %x \n",ele_D); - // TODO : need to check mask - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[0] = (unsigned char)i; - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); - break; - } - } - - //Query OFDM path B default setting - if (rf_mimo_mode == MIMO_2T2R) { - ele_D = PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKOFDM_D_COMMON); - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[1] = (unsigned char)i; - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); - //printk("PathB 0xe1c[31:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); - break; - } - } - } - - /* Initialize */ - // if first time use flash default PG value - if (!HAL_VAR_THERMALVALUE) { - HAL_VAR_THERMALVALUE = HAL_VAR_THER; - //printk("HAL_VAR_THERMALVALUE = %x \n",HAL_VAR_THERMALVALUE); - } - - /* calculate average thermal meter */ - { - HAL_VAR_THERMALVALUE_AVG_88XX(HAL_VAR_THERMALVALUE_AVG_INDEX_88XX) = ThermalValue; - HAL_VAR_THERMALVALUE_AVG_INDEX_88XX++; - if (HAL_VAR_THERMALVALUE_AVG_INDEX_88XX == AVG_THERMAL_NUM_88XX) - HAL_VAR_THERMALVALUE_AVG_INDEX_88XX = 0; - - for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { - if (HAL_VAR_THERMALVALUE_AVG_88XX(i)) { - ThermalValue_AVG += HAL_VAR_THERMALVALUE_AVG_88XX(i); - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); - } - } - - if (ThermalValue != HAL_VAR_THERMALVALUE) { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\n******** START:%s() ********\n", __FUNCTION__)); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, HAL_VAR_THERMALVALUE, HAL_VAR_THER)); - - delta = HAL_RTL_ABS(ThermalValue, HAL_VAR_THER); - is_decrease = ((ThermalValue < HAL_VAR_THER) ? 1 : 0); - - //printk("delta = %x \n",delta); - //printk("is_decrease = %x \n",is_decrease); - - if (HAL_VAR_PHYBANDSELECT == PHY_BAND_2G) { -#ifdef CFG_TRACKING_TABLE_FILE - if (HAL_VAR_PWR_TRACK_FILE) { - - if (is_decrease) { - for (i = 0; i < rf; i++) { - OFDM_index[i] = HAL_VAR_OFDM_BASE_INDEX(i) + get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E - 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0))); - //printk(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0)); - CCK_index = HAL_VAR_CCK_BASE_INDEX + get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, HAL_VAR_CCK_BASE_INDEX, get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1))); - CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); - } - } else { - for (i = 0; i < rf; i++) { - OFDM_index[i] = HAL_VAR_OFDM_BASE_INDEX(i) - get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0); - //printk("HAL_VAR_OFDM_BASE_INDEX(i) = %x OFDM_index[i] =%x \n",HAL_VAR_OFDM_BASE_INDEX(i),OFDM_index[i]); - OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0))); - //printk(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0)); - CCK_index = HAL_VAR_CCK_BASE_INDEX - get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, HAL_VAR_CCK_BASE_INDEX, get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1))); - //printk("HAL_VAR_CCK_BASE_INDEX = %x CCK_index =%x \n",HAL_VAR_CCK_BASE_INDEX,CCK_index); - CCK_index = ((CCK_index < 0 ) ? 0 : CCK_index); - //printk("HAL_VAR_CCK_BASE_INDEX = %x CCK_index =%x \n",HAL_VAR_CCK_BASE_INDEX,CCK_index); - } - } - } -#endif //CFG_TRACKING_TABLE_FILE - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n", OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n", OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); - - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; - X = Adapter->pshare->RegE94; - Y = Adapter->pshare->RegE9C; - - if (X != 0) { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XCTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, value32); - - value32 = ((X * ele_D) >> 7) & 0x01; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(24), value32); - - } else { - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XCTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, 0x00); - PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(24), 0x00); - } - - set_CCK_swing_index_88XX(Adapter, CCK_index); - - if (rf == 2) { - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; - X = Adapter->pshare->RegEB4; - Y = Adapter->pshare->RegEBC; - - if (X != 0) { - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XDTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, value32); - - value32 = ((X * ele_D) >> 7) & 0x01; - PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(28), value32); - - } else { - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); - PHY_SetBBReg(Adapter, REG_BB_OFDM0_XDTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, 0x00); - PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(28), 0x00); - } - - } - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON))); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON))); - set_CCK_swing_index_88XX(Adapter, CCK_index); - - if (delta > 3) { -#ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) - printk("NOT do IQK during ctx !!!! \n"); - else - PHY_IQCalibrate_8192E(&(priv->pshare->_dmODM), false); - } else -#endif - PHY_IQCalibrate_8192E(&(priv->pshare->_dmODM), false); - } - } else { - // TODO 5G setting - } - - //update thermal meter value - HAL_VAR_THERMALVALUE = ThermalValue; - for (i = 0 ; i < rf ; i++) - HAL_VAR_OFDM_INDEX(i) = OFDM_index[i]; - HAL_VAR_CCK_INDEX = CCK_index; - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); - } -} - - -void -set_CCK_swing_index_88XX( - IN HAL_PADAPTER Adapter, - IN s2Byte CCK_index -) -{ - u2Byte channel; - -#if CFG_HAL_DISABLE_BB_RF - return; -#endif //CFG_HAL_DISABLE_BB_RF - -#ifdef CFG_HAL_MP_TEST - if ((HAL_OPMODE & WIFI_MP_STATE) || HAL_VAR_MP_SPECIFIC) - channel = HAL_VAR_WORKING_CHANNEL; - else -#endif - channel = HAL_VAR_DOT11CHANNEL; - - if (channel != 14) { - HAL_RTL_W8( 0xa22, CCKSwingTable_Ch1_Ch13_92E[CCK_index][0]); - HAL_RTL_W8( 0xa23, CCKSwingTable_Ch1_Ch13_92E[CCK_index][1]); - HAL_RTL_W8( 0xa24, CCKSwingTable_Ch1_Ch13_92E[CCK_index][2]); - HAL_RTL_W8( 0xa25, CCKSwingTable_Ch1_Ch13_92E[CCK_index][3]); - HAL_RTL_W8( 0xa26, CCKSwingTable_Ch1_Ch13_92E[CCK_index][4]); - HAL_RTL_W8( 0xa27, CCKSwingTable_Ch1_Ch13_92E[CCK_index][5]); - HAL_RTL_W8( 0xa28, CCKSwingTable_Ch1_Ch13_92E[CCK_index][6]); - HAL_RTL_W8( 0xa29, CCKSwingTable_Ch1_Ch13_92E[CCK_index][7]); - } else { - HAL_RTL_W8( 0xa22, CCKSwingTable_Ch14_92E[CCK_index][0]); - HAL_RTL_W8( 0xa23, CCKSwingTable_Ch14_92E[CCK_index][1]); - HAL_RTL_W8( 0xa24, CCKSwingTable_Ch14_92E[CCK_index][2]); - HAL_RTL_W8( 0xa25, CCKSwingTable_Ch14_92E[CCK_index][3]); - HAL_RTL_W8( 0xa26, CCKSwingTable_Ch14_92E[CCK_index][4]); - HAL_RTL_W8( 0xa27, CCKSwingTable_Ch14_92E[CCK_index][5]); - HAL_RTL_W8( 0xa28, CCKSwingTable_Ch14_92E[CCK_index][6]); - HAL_RTL_W8( 0xa29, CCKSwingTable_Ch14_92E[CCK_index][7]); - } - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("0xa22 ~ 0xa29 = {0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x,}\n", - HAL_RTL_R8(0xa22), - HAL_RTL_R8(0xa23), - HAL_RTL_R8(0xa24), - HAL_RTL_R8(0xa25), - HAL_RTL_R8(0xa26), - HAL_RTL_R8(0xa27), - HAL_RTL_R8(0xa28), - HAL_RTL_R8(0xa29) - )); -} - - -s4Byte -get_tx_tracking_index_88XX( - IN HAL_PADAPTER Adapter, - IN s4Byte channel, - IN s4Byte i, - IN s4Byte delta, - IN s4Byte is_decrease, - IN s4Byte is_CCK -) -{ - s4Byte index = 0; - - if (delta == 0) - return 0; - - if (delta > index_mapping_NUM_MAX) - delta = index_mapping_NUM_MAX; - - //printk("\n_eric_tracking +++ channel = %d, i = %d, delta = %d, is_decrease = %d, is_CCK = %d\n", channel, i, delta, is_decrease, is_CCK); - - // note, we transfer the table - // - delta = delta - 1; - - if (channel > 14) { - if (channel <= 99) { - index = HAL_VAR_TXPWR_TRACKING_5GL(((i * 2) + is_decrease), delta); - } else if (channel <= 140) { - index = HAL_VAR_TXPWR_TRACKING_5GM(((i * 2) + is_decrease), delta); - } else { - index = HAL_VAR_TXPWR_TRACKING_5GH(((i * 2) + is_decrease), delta); - } - } else { - if (is_CCK) { - index = HAL_VAR_TXPWR_TRACKING_2G_CCK(((i * 2) + is_decrease), delta); - } else { - index = HAL_VAR_TXPWR_TRACKING_2G_OFDM(((i * 2) + is_decrease), delta); - } - } - - //printk("check Table index = %d\n", index); - - return index; - -} -#endif -#endif //#if IS_RTL88XX_N - - -u4Byte -phy_CalculateBitShift_88XX( - IN u4Byte BitMask) -{ - u4Byte i; - - for (i = 0; i <= 31; i++) { - if (((BitMask >> i) & 0x1) == 1) - break; - } - - return (i); -} - - - -u4Byte -PHY_QueryBBReg_88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - u4Byte ReturnValue = 0; - u4Byte OriginalValue; - u4Byte BitShift; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - - OriginalValue = HAL_RTL_R32(RegAddr); - BitShift = phy_CalculateBitShift_88XX(BitMask); - ReturnValue = (OriginalValue & BitMask) >> BitShift; - - return (ReturnValue); -} - - -void -PHY_SetBBReg_88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -) -{ - u4Byte OriginalValue, BitShift, NewValue; - -#if CFG_HAL_DISABLE_BB_RF - return; -#endif //CFG_HAL_DISABLE_BB_RF - - if (BitMask != BIT_MASK_SET_MASKDWORD_COMMON) { - //if not "double word" write - - OriginalValue = HAL_RTL_R32(RegAddr); - BitShift = phy_CalculateBitShift_88XX(BitMask); - NewValue = ((OriginalValue & (~BitMask)) | (Data << BitShift)); - HAL_RTL_W32(RegAddr, NewValue); - } else - HAL_RTL_W32(RegAddr, Data); - -} - - -#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) -BOOLEAN -IsBBRegRange88XX -( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr -) -{ - if ((RegAddr >= 0x800) && (RegAddr <= 0xFFF)) { - return _TRUE; - } else { - return _FALSE; - } -} -#endif //(IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) - -#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) -BOOLEAN -IsBBRegRange88XX_V1 -( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr -) -{ - if (((RegAddr >= 0x800) && (RegAddr <= 0xFFF)) || - ((RegAddr >= 0x1800) && (RegAddr <= 0x1FFF)) ) { - return _TRUE; - } else { - return _FALSE; - } -} -#endif //(IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) - - - - - - - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXPhyCfg.c + +Abstract: + Defined HAL 88XX PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ + +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../HalPrecomp.h" +#endif + + +#ifdef TXPWR_LMT + +void HAL_get_tx_pwr(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, + unsigned char *tmp_b3, unsigned char *tmp_b4) +{ + *tmp_b1 = (tmp_dw & (0xff)); + *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); + *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); + *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); +} + + +unsigned char HAL_get_byte_from_dw(unsigned int tmp_dw, unsigned char byte_num) +{ + + if (byte_num == 0) + return (tmp_dw & (0xff)); + else if (byte_num == 1) + return ((tmp_dw & (0xff00)) >> 8); + else if (byte_num == 2) + return ((tmp_dw & (0xff0000)) >> 16); + else if (byte_num == 3) + return ((tmp_dw & (0xff000000)) >> 24); + else + return 0; +} + +unsigned int HAL_assign_lmt_reg_value(IN HAL_PADAPTER Adapter, unsigned int reg_offset, unsigned char max_idx, unsigned char max_idx2) +{ + + unsigned int tmp_dw; + unsigned char reg_val[4]; + unsigned char i = 0; + + tmp_dw = HAL_RTL_R32(reg_offset); + + //printk("[0x%03x] 0x%08x >> ", reg_offset, tmp_dw); + + HAL_get_tx_pwr(tmp_dw, (unsigned char *)®_val[0], (unsigned char *)®_val[1], + (unsigned char *)®_val[2], (unsigned char *)®_val[3]); + +#if IS_RTL88XX_N + if (reg_offset == REG_BB_TXAGC_A_CCK1_MCS32_N) { + reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); + } else if (reg_offset == REG_BB_TXAGC_B_CCK5_1_MCS32_N) { + reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); + reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx)); + reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx)); + } else if (reg_offset == REG_BB_TXAGC_A_CCK11_2_B_CCK11_N) { + //if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + reg_val[0] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[0], max_idx2)); + reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); + reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx)); + reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx)); + } else +#endif +#if IS_RTL88XX_AC + if ((reg_offset == REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC) || + (reg_offset == REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC)) { + reg_val[0] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[0], max_idx)); + reg_val[1] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[1], max_idx)); + reg_val[2] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[2], max_idx2)); + reg_val[3] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[3], max_idx2)); + } else +#endif + { + for (i = 0; i < 4; i++) { + reg_val[i] = POWER_RANGE_CHECK(POWER_MIN_CHECK(reg_val[i], max_idx)); + } + } + + tmp_dw = (reg_val[3] << 24) | (reg_val[2] << 16) | (reg_val[1] << 8) | reg_val[0]; + + //printk("0x%08x\n", tmp_dw); + + HAL_RTL_W32(reg_offset, tmp_dw); + +} + +unsigned char HAL_check_lmt_valid(IN HAL_PADAPTER Adapter, unsigned char phy_band) +{ + unsigned char lmt_valid = 1; + + if (phy_band == PHY_BAND_2G) + if (Adapter->pshare->txpwr_lmt_CCK == 0) + lmt_valid = 0; + + if (Adapter->pshare->txpwr_lmt_OFDM == 0) + lmt_valid = 0; + + if (Adapter->pshare->txpwr_lmt_HT1S == 0) + lmt_valid = 0; + + if (Adapter->pshare->txpwr_lmt_HT2S == 0) + lmt_valid = 0; + +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + if(Adapter->pshare->txpwr_lmt_HT3S == 0) + lmt_valid = 0; + } +#endif + + + if (phy_band == PHY_BAND_5G) { + if (Adapter->pshare->txpwr_lmt_VHT1S == 0) + lmt_valid = 0; + + if (Adapter->pshare->txpwr_lmt_VHT2S == 0) + lmt_valid = 0; +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + if(Adapter->pshare->txpwr_lmt_VHT3S == 0) + lmt_valid = 0; + } +#endif + } +#if 1 + + if ((Adapter->pmib->dot11StationConfigEntry.dot11RegDomain != DOMAIN_TEST) + && lmt_valid == 0) { + panic_printk("NO Limit Value, NO limit TX POWER !!!\n limit for cck=%d, ofdm=%d, ht1s=%d, ht2s=%d, vht1s=%d, vht2s=%d\n", + Adapter->pshare->txpwr_lmt_CCK, + Adapter->pshare->txpwr_lmt_OFDM, + Adapter->pshare->txpwr_lmt_HT1S, + Adapter->pshare->txpwr_lmt_HT2S, + Adapter->pshare->txpwr_lmt_VHT1S, + Adapter->pshare->txpwr_lmt_VHT2S + ); + } + +#endif + return lmt_valid; + +} + + +#if IS_RTL88XX_AC +void TxLMT_OFDM_Jaguar_PathX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte bPathXEnIdx + ) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_odfm_54m = 0; + unsigned char idx_ht_mcs7 = 0; + unsigned char idx_ht_mcs15 = 0; + unsigned char idx_vht_1ss_mcs7 =0; + unsigned char idx_vht_2ss_mcs7 =0; + + char lmt_pg_idx_ofdm = 0; + char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; + char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; + + char max_lmt_idx_ofdm = 0; + char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; + char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; + + // for MIMO 3T3R, 4T4R + unsigned char idx_vht_3ss_mcs7 =0; + unsigned char idx_vht_4ss_mcs7 =0; + char lmt_pg_idx_ht3s, lmt_pg_idx_ht4s = 0; + char lmt_pg_idx_vht3s, lmt_pg_idx_vht4s = 0; + char max_lmt_idx_ht3s, max_lmt_idx_ht4s = 0; + char max_lmt_idx_vht3s, max_lmt_idx_vht4s = 0; + + u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; + u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; + + u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; + u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; + u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; + u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_D_MCS15_MCS12_AC}; + + u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; + u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; + + lmt_pg_idx_ofdm = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[0]; + lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[0]; + lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[0]; + lmt_pg_idx_vht1s = Adapter->pshare->txpwr_lmt_VHT1S - Adapter->pshare->tgpwr_VHT1S_new[0]; + lmt_pg_idx_vht2s = Adapter->pshare->txpwr_lmt_VHT2S - Adapter->pshare->tgpwr_VHT2S_new[0]; + + //Cal Max tx pwr idx for OFDM + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx]); + idx_odfm_54m = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ofdm = idx_odfm_54m + lmt_pg_idx_ofdm; + max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); + + //Cal Max tx pwr idx for HT1S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx]); + idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + + //Cal Max tx pwr idx for HT2S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx]); + idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); + + //Cal Max tx pwr idx for VHT1S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx]); + idx_vht_1ss_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_vht1s = idx_vht_1ss_mcs7 + lmt_pg_idx_vht1s; + max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); + + //Cal Max tx pwr idx for VHT2S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx]); + idx_vht_2ss_mcs7 = HAL_get_byte_from_dw(tmp_dw, 1); + max_lmt_idx_vht2s = idx_vht_2ss_mcs7 + lmt_pg_idx_vht2s; + max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_OFDM18_OFDM6_AC[bPathXEnIdx], max_lmt_idx_ofdm, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx], max_lmt_idx_ofdm, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS3_MCS0_AC[bPathXEnIdx], max_lmt_idx_ht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx], max_lmt_idx_ht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS11_MCS8_AC[bPathXEnIdx], max_lmt_idx_ht2s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx], max_lmt_idx_ht2s, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[bPathXEnIdx], max_lmt_idx_vht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx], max_lmt_idx_vht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], max_lmt_idx_vht1s, max_lmt_idx_vht2s); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[bPathXEnIdx], max_lmt_idx_vht2s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx], max_lmt_idx_vht2s, 0); + +} + + +#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES +void TxLMT_OFDM_Jaguar_AC_8814( + IN HAL_PADAPTER Adapter + ) +{ + + unsigned int tmp_dw = 0; + unsigned char bPathXEnIdx, rate, start, end; + + unsigned char idx_odfm_54m = 0; + unsigned char idx_ht_mcs7 = 0; + unsigned char idx_ht_mcs15 = 0; + unsigned char idx_vht_1ss_mcs7 =0; + unsigned char idx_vht_2ss_mcs7 =0; + unsigned char idx_vht_3ss_mcs7 =0; + unsigned char idx_vht_4ss_mcs7 =0; + + char lmt_pg_idx_ofdm = 0; + char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; + char lmt_pg_idx_vht1s, lmt_pg_idx_vht2s = 0; + char lmt_pg_idx_ht3s, lmt_pg_idx_ht4s = 0; + char lmt_pg_idx_vht3s, lmt_pg_idx_vht4s = 0; + + char max_lmt_idx_ofdm = 0; + char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; + char max_lmt_idx_vht1s, max_lmt_idx_vht2s = 0; + char max_lmt_idx_ht3s, max_lmt_idx_ht4s = 0; + char max_lmt_idx_vht3s, max_lmt_idx_vht4s = 0; + +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + start=1; + end=2; + } else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + start=1; + end=2; + } else +#endif + { + start=0; + end=3; + } + if(GET_CHIP_VER(Adapter) == VERSION_8822B){ + start=0; + end=1; + } + + + /* Cal Max tx pwr idx for each path */ + for(bPathXEnIdx = start; bPathXEnIdx <= end ; bPathXEnIdx++ ){ + lmt_pg_idx_ofdm = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[bPathXEnIdx]; + lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[bPathXEnIdx]; + lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[bPathXEnIdx]; +#ifdef CONFIG_WLAN_HAL_8814AE + lmt_pg_idx_ht3s = Adapter->pshare->txpwr_lmt_HT3S - Adapter->pshare->tgpwr_HT3S_new[bPathXEnIdx]; + lmt_pg_idx_ht4s = Adapter->pshare->txpwr_lmt_HT4S - Adapter->pshare->tgpwr_HT4S_new[bPathXEnIdx]; +#endif + lmt_pg_idx_vht1s = Adapter->pshare->txpwr_lmt_VHT1S - Adapter->pshare->tgpwr_VHT1S_new[bPathXEnIdx]; + lmt_pg_idx_vht2s = Adapter->pshare->txpwr_lmt_VHT2S - Adapter->pshare->tgpwr_VHT2S_new[bPathXEnIdx]; +#ifdef CONFIG_WLAN_HAL_8814AE + lmt_pg_idx_vht3s = Adapter->pshare->txpwr_lmt_VHT3S - Adapter->pshare->tgpwr_VHT3S_new[bPathXEnIdx]; + lmt_pg_idx_vht4s = Adapter->pshare->txpwr_lmt_VHT4S - Adapter->pshare->tgpwr_VHT4S_new[bPathXEnIdx]; +#endif +#if 0 // Debug message + printk("lmt_pg_idx_ofdm=%d =(txpwr_lmt_OFDM=%d - tgpwr_OFDM_new[%u]=%d)\n",lmt_pg_idx_ofdm, Adapter->pshare->txpwr_lmt_OFDM, bPathXEnIdx, Adapter->pshare->tgpwr_OFDM_new[bPathXEnIdx]); + printk("lmt_pg_idx_ht1s=%d =(txpwr_lmt_HT1S=%d - tgpwr_HT1S_new[%u]=%d)\n",lmt_pg_idx_ht1s, Adapter->pshare->txpwr_lmt_HT1S, bPathXEnIdx, Adapter->pshare->tgpwr_HT1S_new[bPathXEnIdx]); + printk("lmt_pg_idx_ht2s=%d =(txpwr_lmt_HT2S=%d - tgpwr_HT2S_new[%u]=%d)\n",lmt_pg_idx_ht2s, Adapter->pshare->txpwr_lmt_HT2S, bPathXEnIdx, Adapter->pshare->tgpwr_HT2S_new[bPathXEnIdx]); + printk("lmt_pg_idx_ht3s=%d =(txpwr_lmt_HT3S=%d - tgpwr_HT3S_new[%u]=%d)\n",lmt_pg_idx_ht3s, Adapter->pshare->txpwr_lmt_HT3S, bPathXEnIdx, Adapter->pshare->tgpwr_HT3S_new[bPathXEnIdx]); + printk("lmt_pg_idx_ht4s=%d =(txpwr_lmt_HT4S=%d - tgpwr_HT4S_new[%u]=%d)\n",lmt_pg_idx_ht4s, Adapter->pshare->txpwr_lmt_HT4S, bPathXEnIdx, Adapter->pshare->tgpwr_HT4S_new[bPathXEnIdx]); + printk("lmt_pg_idx_vht1s=%d =(txpwr_lmt_VHT1S=%d - tgpwr_VHT1S_new[%u]=%d)\n",lmt_pg_idx_vht1s, Adapter->pshare->txpwr_lmt_VHT1S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT1S_new[bPathXEnIdx]); + printk("lmt_pg_idx_vht2s=%d =(txpwr_lmt_VHT2S=%d - tgpwr_VHT2S_new[%u]=%d)\n",lmt_pg_idx_vht2s, Adapter->pshare->txpwr_lmt_VHT2S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT2S_new[bPathXEnIdx]); + printk("lmt_pg_idx_vht3s=%d =(txpwr_lmt_VHT3S=%d - tgpwr_VHT3S_new[%u]=%d)\n",lmt_pg_idx_vht3s, Adapter->pshare->txpwr_lmt_VHT3S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT3S_new[bPathXEnIdx]); + printk("lmt_pg_idx_vht4s=%d =(txpwr_lmt_VHT4S=%d - tgpwr_VHT4S_new[%u]=%d)\n",lmt_pg_idx_vht4s, Adapter->pshare->txpwr_lmt_VHT4S, bPathXEnIdx, Adapter->pshare->tgpwr_VHT4S_new[bPathXEnIdx]); +#endif + max_lmt_idx_ofdm = lmt_pg_idx_ofdm + HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M); + max_lmt_idx_ofdm = POWER_MIN_INDEX(max_lmt_idx_ofdm); + max_lmt_idx_ht1s = lmt_pg_idx_ht1s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0); + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + max_lmt_idx_ht2s = lmt_pg_idx_ht2s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0); + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); +#ifdef CONFIG_WLAN_HAL_8814AE + max_lmt_idx_ht3s = lmt_pg_idx_ht3s + HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0); + max_lmt_idx_ht3s = POWER_MIN_INDEX(max_lmt_idx_ht3s); +#endif + max_lmt_idx_vht1s = lmt_pg_idx_vht1s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0); + max_lmt_idx_vht1s = POWER_MIN_INDEX(max_lmt_idx_vht1s); + max_lmt_idx_vht2s = lmt_pg_idx_vht2s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0); + max_lmt_idx_vht2s = POWER_MIN_INDEX(max_lmt_idx_vht2s); +#ifdef CONFIG_WLAN_HAL_8814AE + max_lmt_idx_vht3s = lmt_pg_idx_vht3s + HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0); + max_lmt_idx_vht3s = POWER_MIN_INDEX(max_lmt_idx_vht3s); +#endif +#if 0 // Debug message + printk("max_lmt_idx_ofdm=%d =(lmt_pg_idx_ofdm=%d + HAL_VAR_CurrentTxAgcOFDM(%d, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M)=%d)\n",max_lmt_idx_ofdm, lmt_pg_idx_ofdm, bPathXEnIdx, HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, TX_AGC_OFDM_54M-TX_AGC_OFDM_6M)); + printk("max_lmt_idx_ht1s=%d =(lmt_pg_idx_ht1s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht1s, lmt_pg_idx_ht1s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0)); + printk("max_lmt_idx_ht2s=%d =(lmt_pg_idx_ht2s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht2s, lmt_pg_idx_ht2s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0)); + printk("max_lmt_idx_ht3s=%d =(lmt_pg_idx_ht3s=%d + HAL_VAR_CurrentTxAgcMCS(%d, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0)=%d)\n",max_lmt_idx_ht3s, lmt_pg_idx_ht3s, bPathXEnIdx, HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0)); + printk("max_lmt_idx_vht1s=%d =(lmt_pg_idx_vht1s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht1s, lmt_pg_idx_vht1s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS1_MCS7-TX_AGC_VHT_NSS1_MCS0)); + printk("max_lmt_idx_vht2s=%d =(lmt_pg_idx_vht2s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht2s, lmt_pg_idx_vht2s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS2_MCS7-TX_AGC_VHT_NSS1_MCS0)); + printk("max_lmt_idx_vht3s=%d =(lmt_pg_idx_vht3s=%d + HAL_VAR_CurrentTxAgcVHT(%d, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0)=%d)\n",max_lmt_idx_vht3s, lmt_pg_idx_vht3s, bPathXEnIdx, HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, TX_AGC_VHT_NSS3_MCS7-TX_AGC_VHT_NSS1_MCS0)); +#endif + /* set OFDM power index */ + for(rate = 0; rate <= TX_AGC_OFDM_54M - TX_AGC_OFDM_6M; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_OFDM_6M, rate+TX_AGC_OFDM_6M, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcOFDM(bPathXEnIdx, rate), max_lmt_idx_ofdm))); + /* set MCS 1/2/3 SS power index */ + for(rate = 0; rate <= TX_AGC_HT_NSS1_MCS7-TX_AGC_HT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht1s))); + for(rate = TX_AGC_HT_NSS2_MCS8-TX_AGC_HT_NSS1_MCS0; rate <= TX_AGC_HT_NSS2_MCS15-TX_AGC_HT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht2s))); +#ifdef CONFIG_WLAN_HAL_8814AE + for(rate = TX_AGC_HT_NSS3_MCS16-TX_AGC_HT_NSS1_MCS0; rate <= TX_AGC_HT_NSS3_MCS23-TX_AGC_HT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_HT_NSS1_MCS0, rate+TX_AGC_HT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcMCS(bPathXEnIdx, rate), max_lmt_idx_ht3s))); +#endif + /* set VHT MCS 1/2/3 SS power index */ + for(rate = 0; rate <= TX_AGC_VHT_NSS1_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht1s))); + for(rate = TX_AGC_VHT_NSS2_MCS0-TX_AGC_VHT_NSS1_MCS0; rate <= TX_AGC_VHT_NSS2_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht2s))); +#ifdef CONFIG_WLAN_HAL_8814AE + for(rate = TX_AGC_VHT_NSS3_MCS0-TX_AGC_VHT_NSS1_MCS0; rate <= TX_AGC_VHT_NSS3_MCS9-TX_AGC_VHT_NSS1_MCS0; rate++) + PHYSetTxPower88XX(Adapter, rate+TX_AGC_VHT_NSS1_MCS0, rate+TX_AGC_VHT_NSS1_MCS0, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcVHT(bPathXEnIdx, rate), max_lmt_idx_vht3s))); +#endif + } +} + + +void TxLMT_CCK_Jaguar_AC_8814(IN HAL_PADAPTER Adapter) +{ + + unsigned int tmp_dw = 0; + unsigned char idx_cck_11m = 0; + unsigned char bPathXEnIdx, rate; + char max_lmt_idx_cck, lmt_pg_idx_cck; + int i, start, end; + +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + start=1; + end=2; + } else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + start=1; + end=2; + } else +#endif + { + start=0; + end=3; + } + + + //Cal Max tx pwr idx for CCK + for(bPathXEnIdx = start; bPathXEnIdx <= end ; bPathXEnIdx++ ){ + lmt_pg_idx_cck = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[bPathXEnIdx]; + //printk("lmt_pg_idx_cck=%d =(txpwr_lmt_CCK=%d - tgpwr_CCK_new[%u]=%d)\n",lmt_pg_idx_cck, Adapter->pshare->txpwr_lmt_CCK, bPathXEnIdx, Adapter->pshare->tgpwr_CCK_new[bPathXEnIdx]); + + max_lmt_idx_cck = lmt_pg_idx_cck + HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, TX_AGC_CCK_11M); + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + //printk("max_lmt_idx_cck=%d =(lmt_pg_idx_cck=%d + HAL_VAR_CurrentTxAgcCCK(%d, TX_AGC_CCK_11M)=%d)\n",max_lmt_idx_cck, lmt_pg_idx_cck, bPathXEnIdx, HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, TX_AGC_CCK_11M)); + /* set CCK power index */ + for(rate = 0; rate <= TX_AGC_CCK_11M; rate++) + PHYSetTxPower88XX(Adapter, rate, rate, bPathXEnIdx, POWER_RANGE_CHECK(POWER_MIN_CHECK(HAL_VAR_CurrentTxAgcCCK(bPathXEnIdx, rate), max_lmt_idx_cck))); + } +} +#endif + + +void TxLMT_OFDM_Jaguar_AC(IN HAL_PADAPTER Adapter) +{ + if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 2); + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 0); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 1); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 2); + TxLMT_OFDM_Jaguar_PathX_AC(Adapter, 3); + } +} + +void TxLMT_CCK_Jaguar_AC(IN HAL_PADAPTER Adapter, IN pu1Byte bPathXEn) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_cck_11m = 0; + + char lmt_pg_idx_cck; + + char max_lmt_idx_cck; + int i; + + unsigned int REG_BB_TXAGC_X_CCK11_CCK1_AC[4] = {REG_BB_TXAGC_A_CCK11_CCK1_AC, REG_BB_TXAGC_B_CCK11_CCK1_AC, REG_BB_TXAGC_C_CCK11_CCK1_AC, REG_BB_TXAGC_D_CCK11_CCK1_AC}; + + lmt_pg_idx_cck = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[0]; + + //Cal Max tx pwr idx for CCK + for(i = 0; i < 4; i++) { + if (bPathXEn[i]) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_X_CCK11_CCK1_AC[i]); + idx_cck_11m = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck = idx_cck_11m + lmt_pg_idx_cck; + max_lmt_idx_cck = POWER_MIN_INDEX(max_lmt_idx_cck); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_X_CCK11_CCK1_AC[i], max_lmt_idx_cck, 0); + } + } + + +} + + +#endif +#if IS_RTL88XX_N +void TxLMT_OFDM_Jaguar_N(IN HAL_PADAPTER Adapter) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_ht_mcs7 = 0; + unsigned char idx_ht_mcs15 = 0; + unsigned char idx_rate54 = 0; + + char lmt_pg_idx_ht1s, lmt_pg_idx_ht2s = 0; + char lmt_pg_idx_rate; + + char max_lmt_idx_ht1s, max_lmt_idx_ht2s = 0; + char max_lmt_rate54 = 0; + + lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[0]; + lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[0]; + lmt_pg_idx_rate = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[0]; + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_RATE54_24_N); + idx_rate54 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_rate54 = idx_rate54 + lmt_pg_idx_rate; + max_lmt_rate54 = POWER_MIN_INDEX(max_lmt_rate54); + + //Cal Max tx pwr idx for HT1S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS07_MCS04_N); + idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + + //Cal Max tx pwr idx for HT2S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_N); + idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); + + RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_OFDM_Jaguar_N, idx_rate54=%x, idx_ht_mcs7=%x, idx_ht_mcs15=%x\n", idx_rate54, idx_ht_mcs7, idx_ht_mcs15)); + RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_OFDM_Jaguar_N, OFDM Limit=%x, HT1S Limit=%x, HT2S Limit=%x\n", max_lmt_rate54, max_lmt_idx_ht1s, max_lmt_idx_ht2s)); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_RATE18_06_N, max_lmt_rate54, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_RATE54_24_N, max_lmt_rate54, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS03_MCS00_N, max_lmt_idx_ht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS07_MCS04_N, max_lmt_idx_ht1s, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS11_MCS08_N, max_lmt_idx_ht2s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_MCS15_MCS12_N, max_lmt_idx_ht2s, 0); + + + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + + lmt_pg_idx_ht1s = Adapter->pshare->txpwr_lmt_HT1S - Adapter->pshare->tgpwr_HT1S_new[1]; + lmt_pg_idx_ht2s = Adapter->pshare->txpwr_lmt_HT2S - Adapter->pshare->tgpwr_HT2S_new[1]; + lmt_pg_idx_rate = Adapter->pshare->txpwr_lmt_OFDM - Adapter->pshare->tgpwr_OFDM_new[1]; + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_RATE54_24_N); + idx_rate54 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_rate54 = idx_rate54 + lmt_pg_idx_rate; + max_lmt_rate54 = POWER_MIN_INDEX(max_lmt_rate54); + //Cal Max tx pwr idx for HT1S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS07_MCS04_N); + idx_ht_mcs7 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht1s = idx_ht_mcs7 + lmt_pg_idx_ht1s; + max_lmt_idx_ht1s = POWER_MIN_INDEX(max_lmt_idx_ht1s); + + //Cal Max tx pwr idx for HT2S + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS15_MCS12_N); + idx_ht_mcs15 = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_ht2s = idx_ht_mcs15 + lmt_pg_idx_ht2s; + max_lmt_idx_ht2s = POWER_MIN_INDEX(max_lmt_idx_ht2s); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_RATE18_06_N, max_lmt_rate54, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_RATE54_24_N, max_lmt_rate54, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS03_MCS00_N, max_lmt_idx_ht1s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS07_MCS04_N, max_lmt_idx_ht1s, 0); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS11_MCS08_N, max_lmt_idx_ht2s, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_MCS15_MCS12_N, max_lmt_idx_ht2s, 0); + } +} + +void TxLMT_CCK_Jaguar_N(IN HAL_PADAPTER Adapter) +{ + + unsigned int tmp_dw = 0; + + unsigned char idx_cck_11m_A = 0, idx_cck_11m_B = 0; + + char lmt_pg_idx_cck_A,lmt_pg_idx_cck_B; + + char max_lmt_idx_cck_A; + char max_lmt_idx_cck_B = 0; + + lmt_pg_idx_cck_A = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[0]; + + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + lmt_pg_idx_cck_B = Adapter->pshare->txpwr_lmt_CCK - Adapter->pshare->tgpwr_CCK_new[1]; + + //printk("%d %d %d %d %d %d\n", lmt_pg_idx_cck, lmt_pg_idx_ofdm, + //lmt_pg_idx_ht1s, lmt_pg_idx_ht2s, lmt_pg_idx_vht1s, lmt_pg_idx_vht2s); + + + //Cal Max tx pwr idx for CCK + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_2_B_CCK11_N); + idx_cck_11m_A = HAL_get_byte_from_dw(tmp_dw, 3); + max_lmt_idx_cck_A = idx_cck_11m_A + lmt_pg_idx_cck_A; + max_lmt_idx_cck_A = POWER_MIN_INDEX(max_lmt_idx_cck_A); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_2_B_CCK11_N); + idx_cck_11m_B = HAL_get_byte_from_dw(tmp_dw, 0); + max_lmt_idx_cck_B = idx_cck_11m_B + lmt_pg_idx_cck_B; + max_lmt_idx_cck_B = POWER_MIN_INDEX(max_lmt_idx_cck_B); + + RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_CCK_Jaguar_N, idx_cck_11m_A=%x, idx_cck_11m_B=%x\n", idx_cck_11m_A, idx_cck_11m_B)); + RT_TRACE(COMP_RF, DBG_TRACE, ("TxLMT_CCK_Jaguar_N, CCK Limit A=%x, CCK Limit B=%x\n", max_lmt_idx_cck_A, max_lmt_idx_cck_B)); + + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, max_lmt_idx_cck_A, 0); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, max_lmt_idx_cck_A, max_lmt_idx_cck_B); + HAL_assign_lmt_reg_value(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, max_lmt_idx_cck_B, 0); +} +#endif + +#endif //TXPWR_LMT + + +#if IS_RTL88XX_AC + +void +phy_RFSerialWrite_88XX_AC +( + IN HAL_PADAPTER Adapter, + IN RFRF88XX_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte Data +) +{ + u4Byte dwTmp = 0; + u4Byte value = ((RegAddr << 20) | Data); // addr BIT[27:20], data BIT[19:0] + u4Byte temp_CCA = 0; + + + temp_CCA = HAL_RTL_R32(REG_BB_CCAONSEC_AC); + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, 0xc); // CCA off + + if (eRFPath == RF88XX_PATH_A) { + dwTmp = HAL_RTL_R32(REG_BB_A_LSSIWRITE_AC); + dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; + dwTmp |= value; + + HAL_RTL_W32(REG_BB_A_LSSIWRITE_AC, dwTmp); + } else if (eRFPath == RF88XX_PATH_B) { + dwTmp = HAL_RTL_R32(REG_BB_B_LSSIWRITE_AC); + dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; + dwTmp |= value; + + HAL_RTL_W32(REG_BB_B_LSSIWRITE_AC, dwTmp); + } +#if IS_RTL8814A_SERIES + else if(eRFPath == RF88XX_PATH_C) + { + dwTmp = HAL_RTL_R32(REG_BB_C_LSSIWRITE_AC); + dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; + dwTmp |= value; + + HAL_RTL_W32(REG_BB_C_LSSIWRITE_AC, dwTmp); + } + else if(eRFPath == RF88XX_PATH_D) + { + dwTmp = HAL_RTL_R32(REG_BB_D_LSSIWRITE_AC); + dwTmp &= BIT_MASK_BB_LSSIWRITE_AC; + dwTmp |= value; + + HAL_RTL_W32(REG_BB_D_LSSIWRITE_AC, dwTmp); + } +#endif + + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, temp_CCA); // CCA off +} + +u4Byte +PHY_QueryRFReg_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + // The phy Query function have bug in 8812 & 8881, must follow the rules as below + // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] + // 2. Before Query RF reg, we must turn off CCA + // 3. delay 10us after set addr + // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + + HAL_PADAPTER priv = Adapter; + unsigned long flags; + u4Byte Original_Value, Readback_Value, BitShift; + u4Byte temp_CCA; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + + HAL_SAVE_INT_AND_CLI(flags); + + temp_CCA = HAL_RTL_R32(REG_BB_CCAONSEC_AC); + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, 0xc); // CCA off + + HAL_RTL_W8(REG_BB_HSSIREAD_AC, RegAddr); + + delay_us(30); + + // normally, we use PI mode in normal chip + if (eRFPath == RF88XX_PATH_A) { + Original_Value = HAL_RTL_R32(REG_BB_A_PIREAD_AC); + } else if (eRFPath == RF88XX_PATH_B) { + Original_Value = HAL_RTL_R32(REG_BB_B_PIREAD_AC); + } +#if IS_RTL8814A_SERIES + else if(eRFPath == RF88XX_PATH_C) { + Original_Value = HAL_RTL_R32(REG_BB_C_PIREAD_AC); + } + else if(eRFPath == RF88XX_PATH_D) { + Original_Value = HAL_RTL_R32(REG_BB_D_PIREAD_AC); + } +#endif + else { + RT_TRACE_F(COMP_RF, DBG_SERIOUS, ("RF PATH no existence\n")); + HAL_RESTORE_INT(flags); + return 0xFFFFFFFF; + } + + Original_Value &= 0xfffff; + + BitShift = phy_CalculateBitShift_88XX(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT_MASK_BB_CCA_AC, temp_CCA); // CCA on + + HAL_RESTORE_INT(flags); + + return (Readback_Value); +} + +void +PHY_SetRFReg_88XX_AC +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +) +{ + u4Byte Original_Value, BitShift, New_Value; + HAL_PADAPTER priv = Adapter; + unsigned long flags; + +#if CFG_HAL_DISABLE_BB_RF + return; +#endif //CFG_HAL_DISABLE_BB_RF + +#if (RTL8822B_SUPPORT == 1) + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + HAL_SAVE_INT_AND_CLI(flags); + config_phydm_write_rf_reg_8822b((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask, Data); + HAL_RESTORE_INT(flags); + delay_us(4); + return; + } +#endif + + + HAL_SAVE_INT_AND_CLI(flags); + if (BitMask != BIT_MASK_SET_MASK20BITS_COMMON) { + Original_Value = GET_HAL_INTERFACE(priv)->PHYQueryRFRegHandler(Adapter, eRFPath, RegAddr, BIT_MASK_SET_MASK20BITS_COMMON); + //Original_Value = PHY_QueryRFReg_88XX_AC(Adapter, eRFPath, RegAddr, BIT_MASK_SET_MASK20BITS_COMMON); + BitShift = phy_CalculateBitShift_88XX(BitMask); + New_Value = ((Original_Value & (~BitMask)) | (Data << BitShift)); + phy_RFSerialWrite_88XX_AC(Adapter, eRFPath, RegAddr, New_Value); + } else { + phy_RFSerialWrite_88XX_AC(Adapter, eRFPath, RegAddr, Data); + } + + HAL_RESTORE_INT(flags); + delay_us(4); // At least 500ns delay to avoid RF write fail. +} + + +#if 1//def TX_PG_Jaguar + +void get_tx_pwr_88XX(unsigned int tmp_dw, unsigned char *tmp_b1, unsigned char *tmp_b2, + unsigned char *tmp_b3, unsigned char *tmp_b4) +{ + *tmp_b1 = (tmp_dw & (0xff)); + *tmp_b2 = ((tmp_dw & (0xff00)) >> 8); + *tmp_b3 = ((tmp_dw & (0xff0000)) >> 16); + *tmp_b4 = ((tmp_dw & (0xff000000)) >> 24); +} + +void TxPG_CCK_Jaguar +( + IN HAL_PADAPTER Adapter, + IN pu1Byte bPathXEn +) +{ + unsigned char b1, b2, b3, b4; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned int tmp_dw = 0; + unsigned int writeVal = 0; + + if (bPathXEn[0]) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_CCK11_CCK1_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_A[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_A[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_A[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_CCK11_CCK1_AC, writeVal); + } + // TODO: 8814AE CCKTxAgc_B[4,5,6,7] ??? + if (bPathXEn[1]) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_CCK11_CCK1_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_B[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_B[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_B[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_CCK11_CCK1_AC, writeVal); + } +#if IS_RTL8814A_SERIES + if (bPathXEn[2]) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_CCK11_CCK1_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_C[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_C[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_C[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_C[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_CCK11_CCK1_AC, writeVal); + } + if (bPathXEn[3]) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_CCK11_CCK1_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->CCKTxAgc_D[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->CCKTxAgc_D[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->CCKTxAgc_D[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->CCKTxAgc_D[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_CCK11_CCK1_AC, writeVal); + } +#endif +} + + +#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) +void TxPG_CCK_8814 +( + IN HAL_PADAPTER Adapter +) +{ + int path, rate, start, end; + char *pTxAgcOffset; + +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + start=1; + end=2; + } else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + start=1; + end=2; + } else +#endif + { + start=0; + end=3; + } + + + for(path=start;path<=end;path++){ + switch(path){ + case 0: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_A; break; + case 1: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_B; break; + case 2: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_C; break; + case 3: pTxAgcOffset = Adapter->pshare->phw->CCKTxAgc_D; break; + } + for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ + //printk("CurrentTxAgcCCK[%d][%d]=%x + %x = ",path,rate,Adapter->pshare->phw->CurrentTxAgcCCK[path][rate],(unsigned char)*(pTxAgcOffset+rate)); + Adapter->pshare->phw->CurrentTxAgcCCK[path][rate] += (unsigned char)*(pTxAgcOffset+rate); + Adapter->pshare->phw->CurrentTxAgcCCK[path][rate] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + //printk("CurrentTxAgcCCK[%d][%d]=%x\n",path,rate,Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + } + } +} + + +void TxPG_OFDM_8814 +( + IN HAL_PADAPTER Adapter +) +{ + int path, rate, start, end; + char *pTxAgcOffset; + +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) { + start=1; + end=2; + } else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if(Adapter->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) { + start=1; + end=2; + } else +#endif + { + start=0; + end=3; + } + + /* OFDM */ + for(path=start;path<=end;path++){ + switch(path){ + case 0: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_A; break; + case 1: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_B; break; + case 2: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_C; break; + case 3: pTxAgcOffset = Adapter->pshare->phw->OFDMTxAgcOffset_D; break; + } + for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ + //printk("CurrentTxAgcOFDM[%d][%d]=%x + %x = ",path,rate-TX_AGC_OFDM_6M,Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_OFDM_6M)); + Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_OFDM_6M); + Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); + PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); + //printk("CurrentTxAgcOFDM[%d][%d]=%x\n",path,rate-TX_AGC_OFDM_6M,Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); + } + } + /* HT MCS */ + for(path=start;path<=end;path++){ + switch(path){ + case 0: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_A; break; + case 1: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_B; break; + case 2: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_C; break; + case 3: pTxAgcOffset = Adapter->pshare->phw->MCSTxAgcOffset_D; break; + } + for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ + //printk("CurrentTxAgcMCS[%d][%d]=%x + %x = ",path,rate-TX_AGC_HT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_HT_NSS1_MCS0)); + Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_HT_NSS1_MCS0); + Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + //printk("CurrentTxAgcMCS[%d][%d]=%x\n",path,rate-TX_AGC_HT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + } + /* VHT MCS */ + for(path=start;path<=end;path++){ + switch(path){ + case 0: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_A; break; + case 1: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_B; break; + case 2: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_C; break; + case 3: pTxAgcOffset = Adapter->pshare->phw->VHTTxAgcOffset_D; break; + } + for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ + //printk("CurrentTxAgcVHT[%d][%d]=%x + %x = ",path,rate-TX_AGC_VHT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0],(unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0)); + if( rate == TX_AGC_VHT_NSS1_MCS8 || rate == TX_AGC_VHT_NSS1_MCS9 \ + || rate == TX_AGC_VHT_NSS2_MCS8|| rate == TX_AGC_VHT_NSS2_MCS9 \ + || rate == TX_AGC_VHT_NSS3_MCS8 || rate == TX_AGC_VHT_NSS3_MCS9 ) + Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] -= (unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0); + else + Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] += (unsigned char)*(pTxAgcOffset+rate-TX_AGC_VHT_NSS1_MCS0); + Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0] = HAL_POWER_RANGE_CHECK(Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + PHYSetTxPower88XX(Adapter, rate, rate, path, Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + //printk("CurrentTxAgcVHT[%d][%d]=%x\n",path,rate-TX_AGC_VHT_NSS1_MCS0,Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + } +} +#endif +#endif + +void TxPG_OFDM_Jaguar_A +( + IN HAL_PADAPTER Adapter +) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 = 0; + unsigned int writeVal = 0; + //printk("TxPG_OFDM_8812_A!!\n"); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_A[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_A[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_A[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_A[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_A[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_A[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS3_MCS0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS3_MCS0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS7_MCS4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS7_MCS4_AC, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS11_MCS8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_A[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_A[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_A[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_A[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_AC, writeVal); + } + if (HAL_VAR_PHYBANDSELECT == PHY_BAND_5G) { + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC); + tmp_dw1 = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_A[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_A[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_A[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_A[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_A[19]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_A[18]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_A[17]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_A[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, writeVal); + } +} + + +void TxPG_OFDM_Jaguar_B +( + IN HAL_PADAPTER Adapter +) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 = 0; + unsigned int writeVal = 0; + + //printk("TxPG_OFDM_8812_B!!\n"); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_OFDM18_OFDM6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_B[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_B[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_B[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_OFDM18_OFDM6_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_OFDM54_OFDM24_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_B[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_B[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_B[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_OFDM54_OFDM24_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS3_MCS0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS3_MCS0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS7_MCS4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS7_MCS4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS11_MCS8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_MCS15_MCS12_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_B[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_B[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_B[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_B[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC); + tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_B[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_B[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_B[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_B[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_B[19]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_B[18]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_B[17]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_B[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, writeVal); +} + +#if IS_RTL8814A_SERIES +void TxPG_OFDM_Jaguar_C +( + IN HAL_PADAPTER Adapter +) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 =0; + unsigned int writeVal = 0; + + //printk("TxPG_OFDM_8812_B!!\n"); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_OFDM18_OFDM6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_C[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_C[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_C[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_C[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_OFDM18_OFDM6_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_OFDM54_OFDM24_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_C[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_C[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_C[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_C[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_OFDM54_OFDM24_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS3_MCS0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_MCS3_MCS0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS7_MCS4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_MCS7_MCS4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS11_MCS8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_MCS11_MCS8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_MCS15_MCS12_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_C[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_C[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_C[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_C[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_MCS15_MCS12_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC); + tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_C[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_C[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_C[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_C[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_C[19]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_C[18]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_C[17]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_C[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, writeVal); +} + +void TxPG_OFDM_Jaguar_D +( + IN HAL_PADAPTER Adapter +) +{ + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 =0; + unsigned int writeVal = 0; + + //printk("TxPG_OFDM_8812_B!!\n"); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_OFDM18_OFDM6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_D[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_D[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_D[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_D[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_OFDM18_OFDM6_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_OFDM54_OFDM24_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->OFDMTxAgcOffset_D[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->OFDMTxAgcOffset_D[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->OFDMTxAgcOffset_D[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->OFDMTxAgcOffset_D[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_OFDM54_OFDM24_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS3_MCS0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_MCS3_MCS0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS7_MCS4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_MCS7_MCS4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS11_MCS8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_MCS11_MCS8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_MCS15_MCS12_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->MCSTxAgcOffset_D[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->MCSTxAgcOffset_D[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->MCSTxAgcOffset_D[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->MCSTxAgcOffset_D[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_MCS15_MCS12_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[3]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[2]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[1]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[0]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[7]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[6]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[5]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[4]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC); + tmp_dw1= HAL_RTL_R32(REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw1, tmp_b1, tmp_b2, tmp_b3, tmp_b5); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_D[11]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b5 - Adapter->pshare->phw->VHTTxAgcOffset_D[10]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[9]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[8]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[15]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[14]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + Adapter->pshare->phw->VHTTxAgcOffset_D[13]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + Adapter->pshare->phw->VHTTxAgcOffset_D[12]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + Adapter->pshare->phw->VHTTxAgcOffset_D[19]); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + Adapter->pshare->phw->VHTTxAgcOffset_D[18]); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 - Adapter->pshare->phw->VHTTxAgcOffset_D[17]); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 - Adapter->pshare->phw->VHTTxAgcOffset_D[16]); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC, writeVal); +} +#endif + + +void +checkSwitchChannelPara88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte channel +) +{ + RT_TRACE_F(COMP_RF, DBG_TRACE, ("Switch to channel [%x] \n", channel)); + + // BW + RT_TRACE_F(COMP_RF, DBG_TRACE, ("BW parameter \n")); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("CCK en 0x808[28][29]=%x \n", HAL_RTL_R32(0x808))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("rf_mode BB 0x8ac[21,20,9:6,1,0]=%x \n", HAL_RTL_R32(0x8ac))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("rf_mode MAC 0x8[7:6]=%x \n", HAL_RTL_R8(0x8))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("RF TRX_BW RF 0x18=%x \n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xffffffff, 1))); + + + // 2.4G <=> 5G + RT_TRACE_F(COMP_RF, DBG_TRACE, ("2.4G 5G switch \n")); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("CCK_CHECK_en 0x454[7]=%x \n", HAL_RTL_R8(0x454))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("AGC table select 0x82c[1:0]=%x \n", HAL_RTL_R32(0x82c))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xcb0))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xeb0))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xcb0))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xeb0))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("fc_area 0x860[28:17]= %x \n", HAL_RTL_R32(0x860))); + RT_TRACE_F(COMP_RF, DBG_TRACE, ("RF MOD AG reg18[18,17,16,9,8]=%x\n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xc00, 1))); +} + +#if 0 +void checkSwitchChannelPara88XX(IN HAL_PADAPTER Adapter, unsigned char channel) +{ + printk("Switch to channel [%x] \n", channel); + + // BW + printk("BW parameter \n"); + printk("CCK en 0x808[28][29]=%x \n", HAL_RTL_R32(0x808)); + printk("rf_mode BB 0x8ac[21,20,9:6,1,0]=%x \n", HAL_RTL_R32(0x8ac)); + printk("rf_mode MAC 0x8[7:6]=%x \n", HAL_RTL_R8(0x8)); + printk("RF TRX_BW RF 0x18=%x \n", PHY_QueryRFReg_88XX_AC(Adapter, 0, 0x18, 0xffffffff)); + + + // 2.4G <=> 5G + printk("2.4G 5G switch \n"); + printk("CCK_CHECK_en 0x454[7]=%x \n", HAL_RTL_R8(0x454)); + printk("AGC table select 0x82c[1:0]=%x \n", HAL_RTL_R32(0x82c)); + printk("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xcb0)); + printk("RFE module 0xcb0[7:4]= %x \n", HAL_RTL_R32(0xeb0)); + printk("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xcb0)); + printk("TRSW module 0xcb0[23:16]= %x \n", HAL_RTL_R32(0xeb0)); + printk("fc_area 0x860[28:17]= %x \n", HAL_RTL_R32(0x860)); + printk("RF MOD AG reg18[18,17,16,9,8]=%x\n", PHY_QueryRFReg_88XX_AC(Adapter, 0, 0x18, 0xc00)); + + printk("0x8ac = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x8ac, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x8ac = %x\n", HAL_RTL_R32(0x8ac)); + printk("0x668 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x668, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x668 = %x\n", HAL_RTL_R32(0x668)); + printk("0x8c4 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x8c4, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x8c4 = %x\n", HAL_RTL_R32(0x8c4)); + printk("0x24 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x24, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x24 = %x\n", HAL_RTL_R32(0x24)); + printk("0xa00 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0xa00, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0xa00 = %x\n", HAL_RTL_R32(0xa00)); + printk("0x483 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x483, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x483 = %x\n", HAL_RTL_R32(0x483)); + printk("0x838 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x838, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x838 = %x\n", HAL_RTL_R32(0x838)); + printk("0x440 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x440, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x440 = %x\n", HAL_RTL_R32(0x440)); + printk("0x848 = %x\n", PHY_QueryBBReg_88XX(Adapter, 0x848, BIT_MASK_SET_MASKDWORD_COMMON)); + printk("0x848 = %x\n", HAL_RTL_R32(0x848)); +} +#endif + + +#if 1 //eric-8822 +int conver_bw_hal_2_odm(int bandwidth) +{ + int bandwidth_odm = ODM_BW20M; + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + bandwidth_odm = ODM_BW5M; + break; + case HT_CHANNEL_WIDTH_AC_10: + bandwidth_odm = ODM_BW10M; + break; + case HT_CHANNEL_WIDTH_AC_20: + bandwidth_odm = ODM_BW20M; + break; + case HT_CHANNEL_WIDTH_AC_40: + bandwidth_odm = ODM_BW40M; + break; + case HT_CHANNEL_WIDTH_AC_80: + bandwidth_odm = ODM_BW80M; + break; + case HT_CHANNEL_WIDTH_AC_160: + bandwidth_odm = ODM_BW160M; + break; + } + + return bandwidth_odm; +} +#endif + +void +SwBWMode88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +) +{ + + u4Byte rfBand = 0, clkSel = 0 , rrSR = 0, tmp_rf = 0; + u1Byte dataSC = 0; + u1Byte SCSettingOf40 = 0; + u1Byte SCSettingOf20 = 0; + u1Byte Current_band; + + if (HAL_VAR_DOT11CHANNEL <= CHANNEL_MAX_NUMBER_2G) + Current_band = RF88XX_BAND_ON_2_4G; + else + Current_band = RF88XX_BAND_ON_5G; + SCSettingOf20 = HAL_VAR_TXSC_20; + SCSettingOf40 = HAL_VAR_TXSC_40; + +#if (RTL8822B_SUPPORT == 1) + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + + int bandwidth_odm = conver_bw_hal_2_odm(bandwidth); + + rfBand = HAL_RTL_R32(REG_WMAC_TRXPTCL_CTL); + rfBand &= ~(BIT(7) | BIT(8)); + + dataSC = ( SCSettingOf20 | (SCSettingOf40 << 4)); + + switch (bandwidth) { + + case HT_CHANNEL_WIDTH_AC_40: + + rfBand |= BIT(7); + break; + + case HT_CHANNEL_WIDTH_AC_80: + + rfBand |= BIT(8); + break; + } + + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + HAL_RTL_W8(REG_DATA_SC, dataSC); + +#ifdef MP_TEST + if(Adapter->pshare->rf_ft_var.mp_specific) + config_phydm_trx_mode_8822b((&(Adapter->pshare->_dmODM)), Adapter->pshare->mp_antenna_tx, Adapter->pshare->mp_antenna_rx, 0); +#endif + //else + //config_phydm_trx_mode_8822b((&(Adapter->pshare->_dmODM)), (ODM_RF_A|ODM_RF_B), (ODM_RF_A|ODM_RF_B), Adapter->pmib->dot11RFEntry.tx2path); + + config_phydm_switch_bandwidth_8822b((&(Adapter->pshare->_dmODM)), SCSettingOf20, bandwidth_odm); + + return; + } +#endif + + //3 ========== <1> Set rf_mode 0x8ac / 0x24 (REG_AFE_CTRL1, BIT_MAC_CLK_SEL)/ 0x668 + + rfBand = HAL_RTL_R32(REG_WMAC_TRXPTCL_CTL); + rfBand &= ~(BIT(7) | BIT(8)); + +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + clkSel = HAL_RTL_R32(REG_SYS_CLK_CTRL); + clkSel &= ~(BIT(6)|BIT(7)); + } else +#endif + { + clkSel = HAL_RTL_R32(REG_AFE_CTRL1); + clkSel &= ~(BIT(20)|BIT(21)); + } + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x200040); // 5M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0100000100 + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x200140); // 5M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0100010100 + } + clkSel |= BIT(7); + HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); + + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x100040); // 5M : 0x8ac[21,20,9:6,1,0]=8'b01000100 + clkSel |= BIT(21); + HAL_RTL_W32(REG_AFE_CTRL1, clkSel); + } + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + break; + case HT_CHANNEL_WIDTH_AC_10: +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x300180); // 10M :0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0110011000 + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x300280); // 10M :0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b0110101000 + } + clkSel |= BIT(6); + HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x200180); // 10M : 0x8ac[21,20,9:6,1,0]=8'b10011000 + clkSel |= BIT(20); + HAL_RTL_W32(REG_AFE_CTRL1, clkSel); + } + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + break; + case HT_CHANNEL_WIDTH_AC_20: +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter)) { + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10000200); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1000100000 + } else { // 2.4G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010000); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001000000 + } + } else { + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + if (IS_HAL_A_CUT(Adapter)) { + // MP chip - A-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10000300); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1000110000 + } else { + // MP chip - B-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010100); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001010000 + } + } else { // 2.4G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x103103C3, 0x10010100); // 20M : 0x8ac[28,21,20,16,9,8,7,6,1,0]=10'b1001010000 + } + } + HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300200); // 20M : 0x8ac[21,20,9:6,1,0]=8'b11100000 + HAL_RTL_W32(REG_AFE_CTRL1, clkSel); + } + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + break; + case HT_CHANNEL_WIDTH_AC_40: +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter)) { + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0xC01); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b0110001 + } else { // 2.4G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20001); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1000001 + } + } else { + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + if (IS_HAL_A_CUT(Adapter)) { + // MP chip - A-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20001); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1000001 + } else { + // MP chip - B-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20C20CC3, 0x20020401); // 40M : 0x8ac[29,23,22,17,11,10,7,6,1,0]=10'b1001010001 + } + } else { // 2.4G + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x20CC3, 0x20401); // 40M : 0x8ac[17,11,10,7,6,1,0]=7'b1010001 + } + } + HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300201); // 40M : 0x8ac[21,20,9:6,1,0]=8'b11100001 + HAL_RTL_W32(REG_AFE_CTRL1, clkSel); + } + rfBand |= BIT(7); + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + break; + case HT_CHANNEL_WIDTH_AC_80: +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0xC3, 0x2); // 80M : 0x8ac[7,6,1,0]=4'b0010 + } else { + if (IS_HAL_A_CUT(Adapter)) { + // MP chip - A-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0xC3, 0x2); // 80M : 0x8ac[7,6,1,0]=4'b0010 + } else { + // MP chip - B-cut + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x430430C3, 0x40041002); // 80M : 0x8ac[30,25,24,18,13,12,7,6,1,0]=10'b1001010010 + } + } + HAL_RTL_W32(REG_SYS_CLK_CTRL, clkSel); + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x003003C3, 0x300202); // 80M : 0x8ac[21,20,9:6,1,0]=8'b11100010 + HAL_RTL_W32(REG_AFE_CTRL1, clkSel); + } + rfBand |= BIT(8); + HAL_RTL_W32(REG_WMAC_TRXPTCL_CTL, rfBand); + break; + } + + //3 ========== <2> Set adc buff clk 0x8c4 + +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + if(IS_HAL_TEST_CHIP(Adapter) || IS_HAL_A_CUT(Adapter)) { + switch (bandwidth) + { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 1); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); + } + break; + case HT_CHANNEL_WIDTH_AC_40: + if (Current_band == RF88XX_BAND_ON_5G) { // 5G + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 0); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); + } + break; + case HT_CHANNEL_WIDTH_AC_80: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); + break; + } + } else { + switch (bandwidth) + { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_2_AC, BIT(31), 1); + break; + case HT_CHANNEL_WIDTH_AC_20: + case HT_CHANNEL_WIDTH_AC_40: + case HT_CHANNEL_WIDTH_AC_80: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); + break; + } + } + + } else +#endif + { + switch (bandwidth) + { + case HT_CHANNEL_WIDTH_AC_5: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_10: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_20: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_40: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 0); + break; + case HT_CHANNEL_WIDTH_AC_80: + PHY_SetBBReg_88XX(Adapter, REG_BB_ADC_BUF_CLK_AC, BIT(30), 1); + break; + } + } + + //3 ========== <3> Set primary channel 0x8ac & 0xa00, txsc 0x483 + + dataSC = HAL_RTL_R8(REG_DATA_SC); + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + break; + + case HT_CHANNEL_WIDTH_AC_40: + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x3C, SCSettingOf20); //0x8ac[5:2]=1/2 +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + // Do nothing for 8814A + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, 0xF0000000, SCSettingOf20); //0x838[31:28]=1/2 + } + + if (SCSettingOf20 == 1) { + // BIT(4) = 1, upper sideBand + PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_SYSTEM_AC, 0x10, 0x1); //0xa00 BIT(4)=1 + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_SYSTEM_AC, 0x10, 0x0); //0xa00 BIT(4)=0 + } + + dataSC &= 0xf0; + dataSC |= SCSettingOf20; + HAL_RTL_W8(REG_DATA_SC, dataSC); //0x483[3:0]=1/2 + break; + + case HT_CHANNEL_WIDTH_AC_80: + PHY_SetBBReg_88XX(Adapter, REG_BB_RFMOD_AC, 0x3C, SCSettingOf20); //0x8ac[5:2]=1/2/3/4 offset 9&10 seems few to use +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + // Do nothing for 8814A + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, 0xF0000000, SCSettingOf20); //0x838[31:28]=1/2/3/4 + } + + dataSC = ( SCSettingOf20 | (SCSettingOf40 << 4)); //0x483[3:0]=1/2/3/4 + HAL_RTL_W8(REG_DATA_SC, dataSC); + + break; + } + + //3 ========== <4> Set Equzlier step size , reg0x864[20:18] + +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + // Do nothing for 8814A + } else +#endif + { + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); + break; + case HT_CHANNEL_WIDTH_AC_10: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); + break; + case HT_CHANNEL_WIDTH_AC_20: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 4); + break; + case HT_CHANNEL_WIDTH_AC_40: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 2); + break; + case HT_CHANNEL_WIDTH_AC_80: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_RFINTERFACEOE_AC, (BIT20 | BIT19 | BIT18), 2); + break; + } + } + + + //3 ========== <> PWED_TH_FB, 0x82C[15:12] + //3 ========== <> r_CCA_primary, 0x838[0] +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + switch (bandwidth) + { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x9); + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x1); + } else { + if (Current_band == RF88XX_BAND_ON_5G) + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); + else + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); + } + break; + case HT_CHANNEL_WIDTH_AC_40: + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x5); + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x0); + } else { + if (Current_band == RF88XX_BAND_ON_5G) + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x8); + else + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); + } + break; + case HT_CHANNEL_WIDTH_AC_80: + if(IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x7); + PHY_SetBBReg_88XX(Adapter, REG_BB_CCAONSEC_AC, BIT0, 0x0); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, (BIT15|BIT14|BIT13|BIT12), 0x3); + } + break; + } + } +#endif + + + //3 ========== <5> 0821, L1_peak_th 0x848 + +#if IS_RTL8814A_SERIES + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + // Do nothing here.. + } else +#endif + { + switch (bandwidth) + { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + #if 0 + if(GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 7); // 2R 0x848[25:22] = 0x7 + else + PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); // 1R 0x848[25:22] = 0x8 + #endif + if (IS_HARDWARE_TYPE_8881A(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); + } + break; + case HT_CHANNEL_WIDTH_AC_40: + if (IS_HARDWARE_TYPE_8881A(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 8); + } + break; + case HT_CHANNEL_WIDTH_AC_80: + if (IS_HARDWARE_TYPE_8881A(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_L1PEAKTH_AC, 0x03C00000, 7); + } + break; + } + } + + //3 ========== <6> Set RRSR_RSC 0x440[22:21] + + rrSR = HAL_RTL_R32(REG_RRSR); + rrSR &= ~(BIT(21) | BIT(22)); + + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + break; + case HT_CHANNEL_WIDTH_AC_40: + HAL_RTL_W32(REG_RRSR, rrSR); + break; + case HT_CHANNEL_WIDTH_AC_80: + HAL_RTL_W32(REG_RRSR, rrSR); + break; + } + + //3 ========== <7> Set RF TRX_BW rf_0x18[11:10] + switch (bandwidth) { + case HT_CHANNEL_WIDTH_AC_5: + case HT_CHANNEL_WIDTH_AC_10: + case HT_CHANNEL_WIDTH_AC_20: + tmp_rf = 0x03; + break; + case HT_CHANNEL_WIDTH_AC_40: + tmp_rf = 0x01; + break; + case HT_CHANNEL_WIDTH_AC_80: + tmp_rf = 0x00; + break; + } + + if(GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) + { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); +#if IS_RTL8814A_SERIES + /* 2nd CCA enable/disable settings*/ + if(IS_HARDWARE_TYPE_8814A(Adapter)) { + if (!Adapter->pshare->rf_ft_var.disable_2ndcca) + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_A); + } +#endif + } + else if(GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); +#if IS_RTL8814A_SERIES + /* 2nd CCA enable/disable settings*/ + if(IS_HARDWARE_TYPE_8814A(Adapter)) { + if (!Adapter->pshare->rf_ft_var.disable_2ndcca) + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); + } +#endif + } +#if IS_RTL8814A_SERIES + else if(GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) + { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + if(IS_HARDWARE_TYPE_8814A(Adapter)) + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); +#if IS_RTL8814A_SERIES + /* 2nd CCA enable/disable settings*/ + if(IS_HARDWARE_TYPE_8814A(Adapter)) { + if (!Adapter->pshare->rf_ft_var.disable_2ndcca) { +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if (Current_band == RF88XX_BAND_ON_5G) { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); + } + else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if (Current_band == RF88XX_BAND_ON_2_4G) { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); + } + else +#endif + { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_ABCD); + } + } + } +#endif + } + else if(GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) + { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, REG_RF_CHNLBW_AC, (BIT11|BIT10),tmp_rf); +#if IS_RTL8814A_SERIES + /* 2nd CCA enable/disable settings*/ + if(IS_HARDWARE_TYPE_8814A(Adapter)) { + if (!Adapter->pshare->rf_ft_var.disable_2ndcca) { +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if (Current_band == RF88XX_BAND_ON_5G) { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); + } + else +#endif +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if (Current_band == RF88XX_BAND_ON_2_4G) { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_AB); + } + else +#endif + { + GET_HAL_INTERFACE(Adapter)->PHYSetSecCCATHbyRXANT(Adapter, ANTENNA_ABCD); + } + } + } +#endif + } +#endif +#if IS_RTL8814A_SERIES + // for MP chip A-cut + if(IS_HARDWARE_TYPE_8814A(Adapter)) { + if (IS_HAL_A_CUT(Adapter)) { + phy_ADC_CLK_8814A(Adapter); + } + } +#endif +#if IS_RTL8814A_SERIES + /* RCK for pathB/C/D. Fix 8814 MP-chip RF reg setting bug */ + if (IS_HARDWARE_TYPE_8814A(Adapter) && !IS_HAL_TEST_CHIP(Adapter)){ + unsigned int rfPathA = PHY_QueryRFReg(Adapter, RF88XX_PATH_A, 0x1c, 0xffffffff, 1); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, 0x1c, 0xffffffff, rfPathA); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_C, 0x1c, 0xffffffff, rfPathA); + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_D, 0x1c, 0xffffffff, rfPathA); + } +#endif + +} + +void +SetChannelPara88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte channel, + IN s4Byte offset +) +{ + u4Byte val = channel; + u4Byte eRFPath, curMaxRFPath; + + //AGC_Table + // TODO: 8813AE BB/RF + if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { + + if (channel <= CHANNEL_MAX_NUMBER_2G) { + // 2G + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, BIT_MASK_BB_BAGC_TABLE_AC, 0); + } else { + //5G + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC, BIT_MASK_BB_BAGC_TABLE_AC, 1); + } + } +#if IS_RTL8814A_SERIES + else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + if (channel <= CHANNEL_MAX_NUMBER_2G) { + // 2G + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 0); + } + else { + //5G + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + if (36 <= channel && channel <= 64) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 1); + } else if (100 <= channel && channel <= 144) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 2); + } else if (149 <= channel) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 3); + } else { + printk("%s(%d): REG_BB_AGC_TABLE setting error !!! \n", __FUNCTION__, __LINE__); + } + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V2, BIT_MASK_BB_BAGC_TABLE_AC_V2, 1); + } + } + } +#endif + else { + if (channel <= CHANNEL_MAX_NUMBER_2G) { + // 2G + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 0); + } else { + //5G + if ((GET_CHIP_VER(Adapter) == VERSION_8881A)) { + if (channel <= 64) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 1); + } else if (channel >= 100 && channel <= 140) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 2); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 3); + } + } else { + if (channel <= 64) { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 1); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_AGC_TABLE_AC_V1, BIT_MASK_BB_BAGC_TABLE_AC_V1, 2); + } + } + } + } + + // fc_area + if (36 <= channel && channel <= 48) { + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x494); //0x860[28:17]=0x494 + } else if (50 <= channel && channel <= 64) { + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x453); //0x860[28:17]=0x453 + } else if (100 <= channel && channel <= 116) { + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x452); //0x860[28:17]=0x452 + } else if (118 <= channel && channel <= 165) { + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x412); //0x860[28:17]=0x412 + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_AREA_AC, 0x1ffe0000, 0x96a); //0x860[28:17]=0x96a + } + + // RF_MOD_AG + if (channel <= 14) { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x0); //RF_A reg18[18,17,16,9,8]=4'b00101 + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x0); //RF_B reg18[18,17,16,9,8]=4'b00101 +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x0); //RF_C reg18[18,17,16,9,8]=5'b00000 + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x0); //RF_D reg18[18,17,16,9,8]=5'b00000 + } +#endif + } else if (36 <= channel && channel <= 64) { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x101); //RF_A reg18[18,17,16,9,8]=4'b00101 + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x101); //RF_B reg18[18,17,16,9,8]=4'b00101 +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x101); //RF_A reg18[18,17,16,9,8]=5'b00101 + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x101); //RF_B reg18[18,17,16,9,8]=5'b00101 + } +#endif + } else if (100 <= channel && channel <= 140) { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x301); //RF_A reg18[18,17,16,9,8]=4'b01101 + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x301); //RF_B reg18[18,17,16,9,8]=4'b01101 +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x301); //RF_A reg18[18,17,16,9,8]=5'b01101 + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x301); //RF_B reg18[18,17,16,9,8]=5'b01101 + } +#endif + } else if (140 < channel) { + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_A, REG_RF_CHNLBW_AC, 0x70300, 0x501); //RF_A reg18[18,17,16,9,8]=4'b10101 + PHY_SetRFReg_88XX_AC(Adapter, RF88XX_PATH_B, REG_RF_CHNLBW_AC, 0x70300, 0x501); //RF_B reg18[18,17,16,9,8]=4'b10101 +#if IS_RTL8814A_SERIES + if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_C,REG_RF_CHNLBW_AC,0x70300,0x501); //RF_A reg18[18,17,16,9,8]=5'b10101 + PHY_SetRFReg_88XX_AC(Adapter,RF88XX_PATH_D,REG_RF_CHNLBW_AC,0x70300,0x501); //RF_B reg18[18,17,16,9,8]=5'b10101 + } +#endif + } + + // set channel number + curMaxRFPath = RF88XX_PATH_MAX; + + if (channel > 14) + HAL_VAR_CURR_BAND = RF88XX_BAND_ON_5G; + else + HAL_VAR_CURR_BAND = RF88XX_BAND_ON_2_4G; + + if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_80) { + if (channel <= 48) + val = 42; + else if (channel <= 64) + val = 58; + else if (channel <= 112) + val = 106; + else if (channel <= 128) + val = 122; + else if (channel <= 144) + val = 138; + else if (channel <= 161) + val = 155; + else if (channel <= 177) + val = 171; + } else if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_20_40) { + if (offset == 1) + val -= 2; + else + val += 2; + } + + if (HAL_VAR_USE_FRQ_2_3G) { + val += 14; + } + + for (eRFPath = RF88XX_PATH_A; eRFPath < curMaxRFPath; eRFPath++) { + PHY_SetRFReg_88XX_AC(Adapter, eRFPath, REG_RF_CHNLBW_AC, 0xff, val); + } +} + + +void +CheckBand88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte RequestChannel +) +{ + + u1Byte Current_band; + //check CCK_CHECK_en BIT7 + if ( HAL_RTL_R8(REG_CCK_CHECK) & BIT(7) ) + Current_band = RF88XX_BAND_ON_5G; + else + Current_band = RF88XX_BAND_ON_2_4G; + + if (HAL_VAR_pre_channel == 0) { // fisrt lauch, no need to check band + if (RequestChannel <= CHANNEL_MAX_NUMBER_2G) { + SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_2_4G); + } else { + SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_5G); + } + } else { + if (RequestChannel <= CHANNEL_MAX_NUMBER_2G) { + // Request for 2.4G Band + if (Current_band == RF88XX_BAND_ON_2_4G) { + // In 2.4G ,Donothing + } else if (Current_band == RF88XX_BAND_ON_5G) { + // In 5G ,switch band to 2.4G + SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_2_4G); + } + } else if (RequestChannel > CHANNEL_MAX_NUMBER_2G) { + // Request for 5G Band + if (Current_band == RF88XX_BAND_ON_2_4G) { + // In 2.4G ,switch band to 5G + SwitchWirelessBand88XX_AC(Adapter, RequestChannel, RF88XX_BAND_ON_5G); + } else if (Current_band == RF88XX_BAND_ON_5G) { + // In 5G ,Donothing + } + } + } +} + +#if IS_RTL8814A_SERIES +void +phy_ADC_CLK_8814A( + IN HAL_PADAPTER Adapter + ) +{ + printk("[%s]\n",__FUNCTION__); + + u4Byte MAC_REG_520, BB_REG_8FC, BB_REG_808, RXIQC[4], Search_index = 0, MAC_Active = 1; + u4Byte RXIQC_REG[2][4] = {{0xc10, 0xe10, 0x1810, 0x1a10}, {0xc14, 0xe14, 0x1814, 0x1a14}} ; + + //1 Step1. MAC TX pause + + MAC_REG_520 = PHY_QueryBBReg( Adapter, 0x520, BIT_MASK_SET_MASKDWORD_COMMON); + BB_REG_8FC = PHY_QueryBBReg( Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON); + BB_REG_808 = PHY_QueryBBReg( Adapter, 0x808, BIT_MASK_SET_MASKDWORD_COMMON); + PHY_SetBBReg(Adapter, 0x520, BIT_MASK_SET_MASKBYTE2_COMMON, 0x3f); + + //1 Step 2. Backup RXIQC & RXIQC = 0 + + for(Search_index = 0; Search_index<4; Search_index++){ + RXIQC[Search_index] = PHY_QueryBBReg( Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON); + PHY_SetBBReg(Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x0); + PHY_SetBBReg(Adapter, RXIQC_REG[1][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x0); + } + PHY_SetBBReg(Adapter, 0xa14, 0x00000300, 0x3); + Search_index = 0; + + + //1 Step 3. Monitor MAC IDLE + PHY_SetBBReg(Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON, 0x0); + while(MAC_Active){ + MAC_Active = PHY_QueryBBReg( Adapter, 0xfa0, BIT_MASK_SET_MASKDWORD_COMMON) & (0x803e0008); + Search_index++; + if(Search_index>1000){ + break; + } + } + //1 Step 4. ADC clk flow + + PHY_SetBBReg(Adapter, 0x808, BIT_MASK_SET_MASKBYTE0_COMMON, 0x11); + PHY_SetBBReg(Adapter, 0x90c, BIT(13), 0x1); + PHY_SetBBReg(Adapter, 0x764, BIT(10)|BIT(9), 0x3); + + PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x1); + // 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be written when bbrstb=0 + // 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line + // 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut + // power_off/clk_off @ anapar_state=idle mode + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0xc60 0x15808002 + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0xc60 0x01808003 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0xe60 0x15808002 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0xe60 0x01808003 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0x1860 0x15808002 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0x1860 0x01808003 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x15800002); //0x1a60 0x15808002 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x01808003); //0x1a60 0x01808003 + PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x0); + PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x0); + PHY_SetBBReg(Adapter, 0xc5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0xc5c 0x00080058 // [19] =1 to turn off ADC + PHY_SetBBReg(Adapter, 0xe5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0xe5c 0x00080058 // [19] =1 to turn off ADC + PHY_SetBBReg(Adapter, 0x185c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0x185c 0x00080058 // [19] =1 to turn off ADC + PHY_SetBBReg(Adapter, 0x1a5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D080058); //0x1a5c 0x00080058 // [19] =1 to turn off ADC + // power_on/clk_off + + //PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x1); + + PHY_SetBBReg(Adapter, 0xc5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0xc5c 0x0D000058 // [19] =0 to turn on ADC + PHY_SetBBReg(Adapter, 0xe5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0xe5c 0x0D000058 // [19] =0 to turn on ADC + PHY_SetBBReg(Adapter, 0x185c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0x185c 0x0D000058 // [19] =0 to turn on ADC + PHY_SetBBReg(Adapter, 0x1a5c, BIT_MASK_SET_MASKDWORD_COMMON, 0x0D000058); //0x1a5c 0x0D000058 // [19] =0 to turn on ADC + + // power_on/clk_on @ anapar_state=BT mode + + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xc60 0x05808002 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xe60 0x05808002 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1860 0x05808002 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1a60 0x05808002 + PHY_SetBBReg(Adapter, 0x764, BIT(10), 0x1); + PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x1); + // recover original setting @ anapar_state=BT mode + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xc60 0x05808036 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0xe60 0x05808036 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1860 0x05808036 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05808032); //0x1a60 0x05808036 + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0xc60 0x05800002 + PHY_SetBBReg(Adapter, 0xc60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0xc60 0x07808003 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0xe60 0x05800002 + PHY_SetBBReg(Adapter, 0xe60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0xe60 0x07808003 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0x1860 0x05800002 + PHY_SetBBReg(Adapter, 0x1860, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0x1860 0x07808003 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x05800002); //0x1a60 0x05800002 + PHY_SetBBReg(Adapter, 0x1a60, BIT_MASK_SET_MASKDWORD_COMMON, 0x07808003); //0x1a60 0x07808003 + PHY_SetBBReg(Adapter, 0x764, BIT(10)|BIT(9), 0x0); + PHY_SetBBReg(Adapter, 0x804, BIT(2), 0x0); + PHY_SetBBReg(Adapter, 0x90c, BIT(13), 0x0); + + //1 Step 5. Recover MAC TX & IQC + + PHY_SetBBReg(Adapter, 0x520, BIT_MASK_SET_MASKDWORD_COMMON, MAC_REG_520); + PHY_SetBBReg(Adapter, 0x8fc, BIT_MASK_SET_MASKDWORD_COMMON, BB_REG_8FC); + PHY_SetBBReg(Adapter, 0x808, BIT_MASK_SET_MASKDWORD_COMMON, BB_REG_808); + for(Search_index = 0; Search_index<4; Search_index++){ + PHY_SetBBReg(Adapter, RXIQC_REG[0][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, RXIQC[Search_index]); + PHY_SetBBReg(Adapter, RXIQC_REG[1][Search_index], BIT_MASK_SET_MASKDWORD_COMMON, 0x01000000); + } + PHY_SetBBReg(Adapter, 0xa14, 0x00000300, 0x0); +} +#endif + +void +SwitchWirelessBand88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte RequestChannel, + IN u1Byte Band +) +{ + if (Band == RF88XX_BAND_ON_2_4G) { // 2.4G band + RT_TRACE(COMP_RF, DBG_LOUD, ("==>SwitchWirelessBand88XX_AC() BAND_ON_2_4G settings\n")); + + // STOP Tx/Rx + PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC , 0x00); + + // PWED_TH +#if IS_RTL8881A_SERIES + if (IS_HARDWARE_TYPE_8881A(Adapter)) { + if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_PWED_TH_AC, BIT3 | BIT2 | BIT1, 0x3); + } + } +#endif + + //PinMux + if (GET_CHIP_VER(Adapter) == VERSION_8881A) { + if (IS_HAL_TEST_CHIP(Adapter)) { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x00); + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x0); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf0, 0x7); + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x7); + } + } else if (GET_CHIP_VER(Adapter) == VERSION_8812E) { + if (IS_HAL_TEST_CHIP(Adapter)) { + // r_select_5G for path_A/B + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT12, 0x0); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT12, 0x0); + + // LANON (5G uses external LNA) + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT15, 0x1); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT15, 0x1); + + } else { + // TODO: Eric check PA type fill reg[REG_BB_RA_RFE_PINMUX] + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x77); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x77); + } + } else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + panic_printk("2G RFE TYPE\n"); +#ifdef HIGH_POWER_EXT_PA +#ifdef HIGH_POWER_EXT_LNA + //3 RFE Type 2 + if (Adapter->pshare->rf_ft_var.use_ext_pa && Adapter->pshare->rf_ft_var.use_ext_lna) { + switch(Adapter->pmib->dot11RFEntry.rfe_type){ + case 3: + case 5: + panic_printk("TRSWITCH: RFE TYPE 3 or 5\n"); + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x45704570); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77707770); + PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x45); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] + break; + case 2: + case 4: + panic_printk("TRSWITCH: RFE TYPE 2 or 4\n"); + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x72707270); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77707770); + PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x72); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] + break; + default: + GDEBUG("TRSWITCH: Unknown RFE type (%d)!\n", Adapter->pmib->dot11RFEntry.rfe_type); + break; + // TODO: high power setting + + } + } else +#endif +#endif + //3 RFE Type 7 or 9 + { + panic_printk("TRSWITCH: RFE TYPE 7 or 9\n"); + + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0xC00000, 0x2); // (S3 RFE output enable) , 0x40[23:22] + + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77777777); + PHY_SetBBReg_88XX(Adapter, 0x1abc, 0xFF00000, 0x77); // 0x1ABC[27:20] + } + } + // cck_enable + PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC, 0x3); + + if (GET_CHIP_VER(Adapter) != VERSION_8814A) // 8814 RX CCK is from PHY parameters and no 2G/5G selectable + PHY_SetBBReg_88XX(Adapter, REG_BB_CCK_RX_AC, 0x0f000000, 0x1); + + // CCK_CHECK_en + HAL_RTL_W8(REG_CCK_CHECK, (HAL_RTL_R8(REG_CCK_CHECK) & ~(BIT(7)))); // 5G to 2.4G last lauch + + } else if (Band == RF88XX_BAND_ON_5G) { //5G band + RT_TRACE(COMP_RF, DBG_LOUD, ("==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings\n")); + + // CCK_CHECK_en + HAL_RTL_W8(REG_CCK_CHECK, (HAL_RTL_R8(REG_CCK_CHECK) | BIT(7))); // 2.4G to 5G first lauch + + // STOP CCK,OFDM + PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC | BIT_MASK_BB_BOFDMEN_AC , 0x00); + + // PWED_TH +#if IS_RTL8881A_SERIES + if (IS_HARDWARE_TYPE_8881A(Adapter)) { + if ((GET_CHIP_VER(Adapter) == VERSION_8881A) && IS_HAL_TEST_CHIP(Adapter)) { + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_PWED_TH_AC, BIT3 | BIT2 | BIT1, 0x2); + } + } +#endif + + //PinMux + if (GET_CHIP_VER(Adapter) == VERSION_8881A) { +#if 1 +#ifdef CONFIG_WLAN_HAL_8881A + if ( (HAL_VAR_INTERLPA_8881A == 1 && (get_bonding_type_8881A() != BOND_8881AB)) +#ifdef CONFIG_8881A_HP + || HAL_VAR_HP_8881A == 1 +#endif + ) { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x54); + panic_printk("8881A internal PA PIN control or 8881A high power\n"); + } else +#endif + { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xff, 0x55); + panic_printk("8881A external PA PIN control :87503 or RTC 5634\n"); + } + + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x1); +#else + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf0, 0x4); + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, 0xf000, 0x5); +#endif + } else if (GET_CHIP_VER(Adapter) == VERSION_8812E) { + if (IS_HAL_TEST_CHIP(Adapter)) { + // r_select_5G for path_A/B + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT12, 0x1); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT12, 0x1); + + // LANON (5G uses external LNA) + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_AC, BIT15, 0x0); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_AC, BIT15, 0x0); + } else { + // TODO: Eric check PA type fill reg[REG_BB_RA_RFE_PINMUX] + if (HAL_VAR_PA_TYPE == PA_RFMD_4501 || HAL_VAR_PA_TYPE == PA_SKYWORKS_85712_HP) { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x53); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x53); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x54); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKBYTE2_COMMON, 0x54); + } + } + } else if (GET_CHIP_VER(Adapter) == VERSION_8814A) { + panic_printk("5G RFE TYPE\n"); +#ifdef HIGH_POWER_EXT_PA +#ifdef HIGH_POWER_EXT_LNA + //3 RFE Type + if (Adapter->pshare->rf_ft_var.use_ext_pa && Adapter->pshare->rf_ft_var.use_ext_lna) { + switch(Adapter->pmib->dot11RFEntry.rfe_type){ + case 3: + case 5: + panic_printk("TRSWITCH: RFE TYPE 3 or 5\n"); + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54175417); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77177717); + PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x54); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] + break; + case 2: + case 4: + case 8: + panic_printk("TRSWITCH: RFE TYPE 2 or 4 or 8\n"); + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x37173717); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x77177717); + PHY_SetBBReg_88XX(Adapter, 0x1ABC, 0x0FF00000, 0x37); // (D¸ô, use ANTSW/ANTSWB pins as LNAON), 0x1ABC[27:20] + break; + default: + GDEBUG("TRSWITCH: Unknown RFE type (%d)!\n", Adapter->pmib->dot11RFEntry.rfe_type); + break; + } + // TODO: high power setting + } else +#endif +#endif + //3 RFE Type 7 or 9 + { + panic_printk("TRSWITCH: RFE TYPE 7 or 9\n"); + PHY_SetBBReg_88XX(Adapter, 0x1994, 0xf, 0xf); // (ANTSW/ANTSWB controlled by S3) + PHY_SetBBReg_88XX(Adapter, REG_GPIO_MUXCFG, 0x00f00000, 0xf); // (S3 RFE output enable) , 0x40[23:20] + // RFE type 0 + PHY_SetBBReg_88XX(Adapter, REG_BB_A_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); + PHY_SetBBReg_88XX(Adapter, REG_BB_B_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); + PHY_SetBBReg_88XX(Adapter, REG_BB_C_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); + PHY_SetBBReg_88XX(Adapter, REG_BB_D_RFE_PINMUX_AC, BIT_MASK_SET_MASKDWORD_COMMON, 0x54775477); + PHY_SetBBReg_88XX(Adapter, 0x1abc, 0xFF00000, 0x54); // 0x1ABC[27:20] + } + //else { + // RT_TRACE(COMP_RF, DBG_WARNING,("Error: No set BB register\n")); + //} + + PHY_SetBBReg_88XX(Adapter, REG_BB_CCKENABLE_AC, BIT_MASK_BB_BCCKEN_AC|BIT_MASK_BB_BOFDMEN_AC , 0x2); + PHY_SetBBReg_88XX(Adapter, REG_BB_FC_ENABL_VHT_AC, BIT17 ,0x0); + } + } +} + + + +void UpdateBBRFVal88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel, + IN s4Byte offset +) +{ + +#if (RTL8822B_SUPPORT == 1) + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + + int val = channel; + + if (channel > 14) + HAL_VAR_CURR_BAND = RF88XX_BAND_ON_5G; + else + HAL_VAR_CURR_BAND = RF88XX_BAND_ON_2_4G; + if (!Adapter->pshare->rf_ft_var.mp_specific) + { + if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_80) { + if (channel <= 48) + val = 42; + else if (channel <= 64) + val = 58; + else if (channel <= 112) + val = 106; + else if (channel <= 128) + val = 122; + else if (channel <= 144) + val = 138; + else if (channel <= 161) + val = 155; + else if (channel <= 177) + val = 171; + } else if (HAL_VAR_CURRENTCHANNELBW == RF88XX_HT_CHANNEL_WIDTH_20_40) { + if (offset == 1) + val -= 2; + else + val += 2; + } + + if (HAL_VAR_USE_FRQ_2_3G) { + val += 14; + } + } + //eric-8822 ?? what shall MAC do during swchnl?? + config_phydm_switch_band_8822b((&(Adapter->pshare->_dmODM)), val); + config_phydm_switch_channel_8822b((&(Adapter->pshare->_dmODM)), val); + return; + } +#endif + + CheckBand88XX_AC(Adapter, channel); + + SetChannelPara88XX_AC(Adapter, channel, offset); + + HAL_VAR_pre_channel = channel; + +} + +#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) +void +SetCurrentTxAGC( + IN HAL_PADAPTER Adapter, + IN u1Byte txPathIdx, + IN u1Byte txRate, + IN u1Byte power +) +{ + if(txRate <= TX_AGC_CCK_11M){ + Adapter->pshare->phw->CurrentTxAgcCCK[txPathIdx][txRate] = power; + }else if(txRate <= TX_AGC_OFDM_54M){ + Adapter->pshare->phw->CurrentTxAgcOFDM[txPathIdx][txRate - TX_AGC_OFDM_6M] = power; + }else if(txRate <= TX_AGC_HT_NSS4_MCS31 ){ + Adapter->pshare->phw->CurrentTxAgcMCS[txPathIdx][txRate - TX_AGC_HT_NSS1_MCS0] = power; + }else if(txRate <= TX_AGC_VHT_NSS4_MCS9){ + Adapter->pshare->phw->CurrentTxAgcVHT[txPathIdx][txRate - TX_AGC_VHT_NSS1_MCS0] = power; + } +} + + +void +PHYSetTxPower88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte txRateStart, + IN u1Byte txRateEnd, + IN u1Byte txPathIdx, + IN u1Byte defPower +) +{ + u1Byte i = 0; + u1Byte tx_path_idx = txPathIdx; // select path a/b/c/d + u1Byte tx_none = 0x1; + u1Byte tx_write = 0x1; + u1Byte def_power = defPower; + u4Byte value32 = 0; + +#if 0 + printk("[%s] Path %u, rate from 0x%x to 0x%x: 0x%x\n", __FUNCTION__, tx_path_idx+1, txRateStart, txRateEnd, def_power); +#endif + + +#if (RTL8822B_SUPPORT == 1) + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + for (i = txRateStart; i <= txRateEnd; i++) { + phydm_write_txagc_1byte_8822b((&(Adapter->pshare->_dmODM)), defPower, txPathIdx, i); + SetCurrentTxAGC(Adapter,tx_path_idx,i,def_power); + } + return; + } +#endif + + // before write data, we must add extra one write commnad to "turn on" the AGC table + // TODO: this can be moved to other place ?? ex: after init done ? + HAL_RTL_W32(REG_BB_TXAGC_V2_BASE_ADDR, FILL_REG_BB_TXAGC_V2(txRateStart, tx_path_idx, tx_none, tx_write, def_power)); + + for (i = txRateStart; i <= txRateEnd; i++) { + HAL_RTL_W32(REG_BB_TXAGC_V2_BASE_ADDR, FILL_REG_BB_TXAGC_V2(i, tx_path_idx, tx_none, tx_write, def_power)); + SetCurrentTxAGC(Adapter,tx_path_idx,i,def_power); /* Path, Rate, Power */ + } +} +#endif + + +RT_STATUS +PHYSetCCKTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +) +{ + u4Byte def_power = 0x12121212;//0x20202020; + u4Byte writeVal = 0; + u1Byte ch_idx = 0; + u1Byte tmp_TPI = 0; + u1Byte phy_band = 0; + u1Byte bPathXEn[4] = {0}; + u1Byte i; + + u1Byte def_power_value = 0x12; + + u4Byte REG_BB_TXAGC_X_CCK11_CCK1_AC[4] = {REG_BB_TXAGC_A_CCK11_CCK1_AC, REG_BB_TXAGC_B_CCK11_CCK1_AC, + REG_BB_TXAGC_C_CCK11_CCK1_AC, REG_BB_TXAGC_D_CCK11_CCK1_AC + }; + u1Byte HAL_VAR_pwrlevelCCK_X[4] = {HAL_VAR_pwrlevelCCK_A(channel - 1), HAL_VAR_pwrlevelCCK_B(channel - 1), + HAL_VAR_pwrlevelCCK_C(channel - 1), HAL_VAR_pwrlevelCCK_D(channel - 1) + }; + + if (channel > 0) + ch_idx = (channel - 1); + else { + RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel [%x]!\n", channel)); + return RT_STATUS_FAILURE; + } + + if (channel > CHANNEL_MAX_NUMBER_2G) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; + +#if 0 + printk("\n----------------------- CCK Efuse Power ------------------------\n"); + printk("[%s]HAL_VAR_pwrlevelCCK_A(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_A(ch_idx)); + printk("[%s]HAL_VAR_pwrlevelCCK_B(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_B(ch_idx)); + printk("[%s]HAL_VAR_pwrlevelCCK_C(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_C(ch_idx)); + printk("[%s]HAL_VAR_pwrlevelCCK_D(%d)=%x\n",__FUNCTION__,ch_idx,HAL_VAR_pwrlevelCCK_D(ch_idx)); +#endif + if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + bPathXEn[0] = 1; + bPathXEn[1] = 0; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if(HAL_VAR_pwrlevelCCK_A(ch_idx) == 0) { + RT_TRACE_F(COMP_RF, DBG_WARNING,("1T1R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); + +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); + } + return RT_STATUS_SUCCESS; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0) || (HAL_VAR_pwrlevelCCK_B(ch_idx) == 0)) { + RT_TRACE_F(COMP_RF, DBG_WARNING,("2T2R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); + +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); + } + return RT_STATUS_SUCCESS; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + if(IS_HARDWARE_TYPE_8814A(Adapter)){ +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + bPathXEn[0] = 0; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelCCK_B(ch_idx)== 0) || (HAL_VAR_pwrlevelCCK_C(ch_idx) == 0)){ + RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); + } + return RT_STATUS_SUCCESS; + } +#else + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevelCCK_B(ch_idx)== 0) || (HAL_VAR_pwrlevelCCK_C(ch_idx) == 0) + ||(HAL_VAR_pwrlevelCCK_D(ch_idx)== 0) + ){ + RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 3, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[3], def_power); + } + return RT_STATUS_SUCCESS; + } +#endif + }else{ + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelCCK_C(ch_idx) == 0) + ) { + RT_TRACE_F(COMP_RF, DBG_WARNING,("3T3R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); + } + return RT_STATUS_SUCCESS; + } + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevelCCK_A(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelCCK_C(ch_idx) == 0)||(HAL_VAR_pwrlevelCCK_D(ch_idx) == 0) + ) { + RT_TRACE_F(COMP_RF, DBG_WARNING,("4T4R NO Calibration data, use default CCK power = 0x%x\n", (unsigned int)def_power)); + +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 0, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 1, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 2, def_power_value); + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, 3, def_power_value); + } else +#endif + { + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[0], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[1], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[2], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[3], def_power); + } + return RT_STATUS_SUCCESS; + } + } + + + if (phy_band == PHY_BAND_2G) { + + for(i = 0; i < 4; i++) { + //PATH X + if(bPathXEn[i]) { +#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES + if ( (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_CCK_1M, TX_AGC_CCK_11M, i, HAL_VAR_pwrlevelCCK_X[i]?HAL_VAR_pwrlevelCCK_X[i]:0x12); + } else +#endif + { + tmp_TPI = HAL_VAR_pwrlevelCCK_X[i]; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + HAL_RTL_W32(REG_BB_TXAGC_X_CCK11_CCK1_AC[i], writeVal); + } + } + } + } + +#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES + if(IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)){ + TxPG_CCK_8814(Adapter); + }else +#endif + TxPG_CCK_Jaguar(Adapter, bPathXEn); +#if 0//def CONFIG_WLAN_HAL_8814AE + printk("CCK After TxPG_CCK_8814\n"); + for(path=0;path<4;path++){ + printk("\n Path%d\n CCK: ",path); + for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + } + } +#endif //#ifdef CONFIG_WLAN_HAL_8814AE + +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { +#if IS_RTL8814A_SERIES + if(IS_HARDWARE_TYPE_8814A(Adapter)) + TxLMT_CCK_Jaguar_AC_8814(Adapter); + else +#endif + TxLMT_CCK_Jaguar_AC(Adapter, bPathXEn); + } + } +#endif + + + return RT_STATUS_SUCCESS; +} + +RT_STATUS +PHYSetOFDMTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +) +{ + u1Byte ch_idx = 0, no_cali_data = 0; + u1Byte phy_band = 0; + + if (channel > 0) + ch_idx = (channel - 1); + else { + RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel !!\n")); + return RT_STATUS_FAILURE; + } + + if (channel > CHANNEL_MAX_NUMBER_2G) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; +#if 0 + printk("\n----------------------- 5G Efuse Power ------------------------\n"); + + printk("HAL_VAR_pwrlevel5GHT40_1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)); + printk("HAL_VAR_pwrlevel5GHT40_1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)); + printk("HAL_VAR_pwrlevel5GHT40_1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)); + printk("HAL_VAR_pwrlevel5GHT40_1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)); + + printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(ch_idx)); + + printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(ch_idx)); + + printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(ch_idx)); + + printk("HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(ch_idx)); + printk("HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(ch_idx)); + + + printk("\n----------------------- 2G Efuse Power ------------------------\n"); + + printk("HAL_VAR_pwrlevelHT40_1S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_A(ch_idx)); + printk("HAL_VAR_pwrlevelHT40_1S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_B(ch_idx)); + printk("HAL_VAR_pwrlevelHT40_1S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_C(ch_idx)); + printk("HAL_VAR_pwrlevelHT40_1S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrlevelHT40_1S_D(ch_idx)); + + printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_A(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_A(ch_idx)); + printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_B(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_B(ch_idx)); + printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_C(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_C(ch_idx)); + printk("HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW2S_20BW2S_D(%d)=%x\n",ch_idx,HAL_VAR_pwrdiff_40BW2S_20BW2S_D(ch_idx)); + printk("HAL_VAR_pwrdiff_40BW3S_20BW3S_D(%d)=%x\n\n",ch_idx,HAL_VAR_pwrdiff_40BW3S_20BW3S_D(ch_idx)); +#endif + + if (phy_band == PHY_BAND_5G) { + if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) == 0) + ) { + no_cali_data = 1; + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + if(IS_HARDWARE_TYPE_8814A(Adapter)){ +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0)) { + no_cali_data = 1; + } +#else + if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) == 0) + ) { + no_cali_data = 1; + } +#endif + }else{ + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) + ) { + no_cali_data = 1; + } + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx) == 0) || (HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0)) { + no_cali_data = 1; + + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx) == 0)) { + no_cali_data = 1; + } + } + } else { + if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) + ) { + no_cali_data = 1; + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + if(IS_HARDWARE_TYPE_8814A(Adapter)){ +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)) { + no_cali_data = 1; + } +#else + if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0) + ||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) + ) { + no_cali_data = 1; + } +#endif + }else{ + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx)== 0) + ) { + no_cali_data = 1; + } + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx) == 0) || (HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0)) { + no_cali_data = 1; + } + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx) == 0)) { + no_cali_data = 1; + } + } + } + + if (phy_band == PHY_BAND_5G) { + CalOFDMTxPower5G_88XX_AC(Adapter, ch_idx); + } else if (phy_band == PHY_BAND_2G) { + CalOFDMTxPower2G_88XX_AC(Adapter, ch_idx); + } + +#if 0 //IS_RTL8822B_SERIES //eric-8822 show tx agc + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + int i = 0, ii=0; + + panic_printk("\n PATH A Power:\n"); + for (i = TX_AGC_OFDM_6M; i <= TX_AGC_VHT_NSS2_MCS9; i++) { + panic_printk("%d ", config_phydm_read_txagc_8822b((&(Adapter->pshare->_dmODM)), 0, i)); + ii++; + if(ii==4){ + ii=0; + panic_printk("\n"); + } + } + + ii = 0; + + panic_printk("\n PATH B Power:\n"); + for (i = TX_AGC_OFDM_6M; i <= TX_AGC_VHT_NSS2_MCS9; i++) { + panic_printk("%d ", config_phydm_read_txagc_8822b((&(Adapter->pshare->_dmODM)), 1, i)); + ii++; + if(ii==4){ + ii=0; + panic_printk("\n"); + } + } + panic_printk("\n"); + } +#endif + + +#if 0//def CONFIG_WLAN_HAL_8814AE + int path, rate; + printk("After CalOFDMTxPower5G_88XX_AC()\n"); + for(path=0;path<4;path++){ + printk("\n Path%d\nCCK: ",path); + for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + } + printk("\n OFDM: "); + for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); + } + printk("\n HT MCS 1SS: "); + for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS1_MCS7;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n HT MCS 2SS: "); + for(rate=TX_AGC_HT_NSS2_MCS8;rate<=TX_AGC_HT_NSS2_MCS15;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n HT MCS 3SS: "); + for(rate=TX_AGC_HT_NSS3_MCS16;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n VHT MCS 1SS: "); + for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS1_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n VHT MCS 2SS: "); + for(rate=TX_AGC_VHT_NSS2_MCS0;rate<=TX_AGC_VHT_NSS2_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n VHT MCS 3SS: "); + for(rate=TX_AGC_VHT_NSS3_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n"); + } +#endif //#ifdef CONFIG_WLAN_HAL_8814AE + + + + + if (!no_cali_data) { + +#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES + if((IS_HARDWARE_TYPE_8814A(Adapter))||(IS_HARDWARE_TYPE_8822BE(Adapter))){ + TxPG_OFDM_8814(Adapter); + +#if 0//def CONFIG_WLAN_HAL_8814AE + int path, rate; + + printk("After TxPG_OFDM_8814()\n"); + for(path=0;path<4;path++){ + printk("\n Path%d\n CCK: ",path); + for(rate=TX_AGC_CCK_1M;rate<=TX_AGC_CCK_11M;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcCCK[path][rate]); + } + printk("\n OFDM: "); + for(rate=TX_AGC_OFDM_6M;rate<=TX_AGC_OFDM_54M;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcOFDM[path][rate-TX_AGC_OFDM_6M]); + } + printk("\n HT MCS 1SS: "); + for(rate=TX_AGC_HT_NSS1_MCS0;rate<=TX_AGC_HT_NSS1_MCS7;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n HT MCS 2SS: "); + for(rate=TX_AGC_HT_NSS2_MCS8;rate<=TX_AGC_HT_NSS2_MCS15;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n HT MCS 3SS: "); + for(rate=TX_AGC_HT_NSS3_MCS16;rate<=TX_AGC_HT_NSS3_MCS23;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcMCS[path][rate-TX_AGC_HT_NSS1_MCS0]); + } + printk("\n VHT MCS 1SS: "); + for(rate=TX_AGC_VHT_NSS1_MCS0;rate<=TX_AGC_VHT_NSS1_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n VHT MCS 2SS: "); + for(rate=TX_AGC_VHT_NSS2_MCS0;rate<=TX_AGC_VHT_NSS2_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n VHT MCS 3SS: "); + for(rate=TX_AGC_VHT_NSS3_MCS0;rate<=TX_AGC_VHT_NSS3_MCS9;rate++){ + printk("%x,",Adapter->pshare->phw->CurrentTxAgcVHT[path][rate-TX_AGC_VHT_NSS1_MCS0]); + } + printk("\n"); + } +#endif //#ifdef CONFIG_WLAN_HAL_8814AE + }else +#endif + { + // TODO: try to rewrite and combine the functions: TxPG_OFDM_Jaguar_A, B, C, D + if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + TxPG_OFDM_Jaguar_A(Adapter); + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + TxPG_OFDM_Jaguar_A(Adapter); + TxPG_OFDM_Jaguar_B(Adapter); + } +#if IS_RTL8814A_SERIES + else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + TxPG_OFDM_Jaguar_A(Adapter); + TxPG_OFDM_Jaguar_B(Adapter); + TxPG_OFDM_Jaguar_C(Adapter); + } else if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + TxPG_OFDM_Jaguar_A(Adapter); + TxPG_OFDM_Jaguar_B(Adapter); + TxPG_OFDM_Jaguar_C(Adapter); + TxPG_OFDM_Jaguar_D(Adapter); + } +#endif + } + +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { +#if IS_RTL8814A_SERIES || IS_RTL8822B_SERIES + if((IS_HARDWARE_TYPE_8814A(Adapter))||(IS_HARDWARE_TYPE_8822B(Adapter))) + TxLMT_OFDM_Jaguar_AC_8814(Adapter); + else +#endif + TxLMT_OFDM_Jaguar_AC(Adapter); + + } + } +#endif + } + return RT_STATUS_SUCCESS; +} + +#if RTL8881A_SUPPORT +RT_STATUS +AddTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN s1Byte index +) +{ + + char add_index; + unsigned char b1, b2, b3, b4, b5; + unsigned char* tmp_b1 = &b1; + unsigned char* tmp_b2 = &b2; + unsigned char* tmp_b3 = &b3; + unsigned char* tmp_b4 = &b4; + unsigned char* tmp_b5 = &b5; + unsigned int tmp_dw = 0; + unsigned int tmp_dw1 = 0; + unsigned int writeVal = 0; + + add_index = index - Adapter->pshare->rf_ft_var.pwrtrk_TxAGC; + Adapter->pshare->rf_ft_var.pwrtrk_TxAGC = index; + + + //printk("TxPG_OFDM_8812_A!!\n"); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_OFDM18_OFDM6_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_OFDM54_OFDM24_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS3_MCS0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS3_MCS0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS7_MCS4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS7_MCS4_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS11_MCS8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS8_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_MCS15_MCS12_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, writeVal); + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, writeVal); + + tmp_dw = HAL_RTL_R32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC); + get_tx_pwr_88XX(tmp_dw, tmp_b1, tmp_b2, tmp_b3, tmp_b4); + *tmp_b1 = HAL_POWER_RANGE_CHECK(*tmp_b1 + add_index); + *tmp_b2 = HAL_POWER_RANGE_CHECK(*tmp_b2 + add_index); + *tmp_b3 = HAL_POWER_RANGE_CHECK(*tmp_b3 + add_index); + *tmp_b4 = HAL_POWER_RANGE_CHECK(*tmp_b4 + add_index); + writeVal = (*tmp_b4 << 24) | (*tmp_b3 << 16) | (*tmp_b2 << 8) | *tmp_b1; + HAL_RTL_W32(REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, writeVal); + + + + return RT_STATUS_SUCCESS; + +} +#endif + +void +CalOFDMTxPower5G_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte ch_idx +) +{ + u1Byte tmp_TPI = 0; + u1Byte pwr_40_1s = 0, pwr_80_1s = 0, ch_idx_ht40 = 0, ch_idx_vht80 = 0; + s1Byte diff_ofdm_1t = 0; + s1Byte diff_bw40_2s = 0; + s1Byte diff_bw40_3s = 0; + s1Byte diff_bw20_1s = 0; + s1Byte diff_bw20_2s = 0; + s1Byte diff_bw20_3s = 0; + s1Byte diff_bw80_1s = 0; + s1Byte diff_bw80_2s = 0; + s1Byte diff_bw80_3s = 0; + u4Byte writeVal = 0; + u1Byte bPathXEn[4] = {0}; + ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (HAL_VAR_DOT11CHANNEL-2) : (HAL_VAR_DOT11CHANNEL+2)) -1; + ch_idx_vht80 = get_center_channel(Adapter, HAL_VAR_DOT11CHANNEL, HAL_VAR_OFFSET_2ND_CHANNEL, 1) -1; + + u1Byte i; + u1Byte HAL_VAR_pwrlevel5GHT40_1S_X[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx), + HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx) + }; + /* for 40M*/ + u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_40M[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_ht40), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_ht40), + HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_ht40), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_ht40) + }; + /* for 80M*/ + u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_A[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_vht80-4), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_vht80-4), + HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_vht80-4), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_vht80-4) + }; + u1Byte HAL_VAR_pwrlevel5GHT40_1S_X_B[4] = {HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx_vht80+4), HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx_vht80+4), + HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx_vht80+4), HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx_vht80+4) + }; + s1Byte HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[4] = {HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_A(ch_idx), HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_B(ch_idx), + HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_C(ch_idx), HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[4] = {HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_A(ch_idx), HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_B(ch_idx), + HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_C(ch_idx), HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_X[4] = {HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_B(ch_idx), + HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_X[4] = {HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_B(ch_idx), + HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[4] = {HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_A(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_B(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_C(ch_idx), HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_D(ch_idx)}; + s1Byte HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_X[4] = {HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_A(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_B(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_C(ch_idx), HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_D(ch_idx)}; + + + if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)== 0) + ) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + if(IS_HARDWARE_TYPE_8814A(Adapter)){ +#if defined(CONFIG_SLOT_0_8814_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8814_2T2R_SUPPORT) + bPathXEn[0] = 0; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0)){ + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } +#else + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx) == 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_D(ch_idx)== 0) + ){ + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } +#endif + }else + + { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevel5GHT40_1S_C(ch_idx)== 0) + ) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevel5GHT40_1S_B(ch_idx) == 0)) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + bPathXEn[0] = 1; + bPathXEn[1] = 0; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevel5GHT40_1S_A(ch_idx)== 0)) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + + for (i = 0; i < 4; i++) { + // PATH i, OFDM + if(bPathXEn[i]) { + pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + diff_ofdm_1t = (HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[i] & 0x0f); + diff_ofdm_1t = convert_diff_88XX_AC(diff_ofdm_1t); + tmp_TPI = pwr_40_1s + diff_ofdm_1t; + //tmp_TPI = HAL_POWER_RANGE_CHECK(tmp_TPI ); +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_OFDM_54M, i, tmp_TPI); + } else +#endif + { + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_X_88XX_AC(Adapter, writeVal, i); + } + } + } + + //3 20M + if (HAL_VAR_CurrentChannelBW == 0) { + + for (i = 0; i < 4; i++) { + if(bPathXEn[i]) { + //PATH i, BW20-1S + + pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + //printk("[%s]pwr_40_1s=%x\n",__FUNCTION__,pwr_40_1s); + diff_bw20_1s = ((HAL_VAR_pwrdiff_5G_20BW1S_OFDM1T_X[i] & 0xf0) >> 4); + //printk("[%s]diff_bw20_1s=%x\n",__FUNCTION__,diff_bw20_1s); + diff_bw20_1s = convert_diff_88XX_AC(diff_bw20_1s); + tmp_TPI = pwr_40_1s + diff_bw20_1s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + //printk("[%s]writeVal=%x\n",__FUNCTION__,writeVal); +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); + } else +#endif + { + Write_1S_X_88XX_AC(Adapter, writeVal, i); + } + + //PATH i, BW20-2S + diff_bw20_2s = (HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[i] & 0x0f); + //printk("[%s]diff_bw20_2s=%x\n",__FUNCTION__,diff_bw20_2s); + + diff_bw20_2s = convert_diff_88XX_AC(diff_bw20_2s); + tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); + } else +#endif + { + Write_2S_X_88XX_AC(Adapter, writeVal, i); + } + +#if IS_RTL8814A_SERIES + //PATH i, BW20-3S + diff_bw20_3s = (HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[i] & 0x0f); + diff_bw20_3s = convert_diff_88XX_AC(diff_bw20_3s); + tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s + diff_bw20_3s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); + } else + { + Write_3S_X_88XX_AC(Adapter, writeVal, i); + } +#endif + } + } + //3 40M + } else if (HAL_VAR_CurrentChannelBW == 1) { + for (i = 0; i < 4; i++) { + if(bPathXEn[i]) { + //PATH i, BW40-1S + pwr_40_1s = HAL_VAR_pwrlevel5GHT40_1S_X_40M[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); + } else +#endif + { + Write_1S_X_88XX_AC(Adapter, writeVal, i); + } + + //PATH i, BW40-2S + diff_bw40_2s = ((HAL_VAR_pwrdiff_5G_40BW2S_20BW2S_X[i] & 0xf0) >> 4); + diff_bw40_2s = convert_diff_88XX_AC(diff_bw40_2s); + tmp_TPI = pwr_40_1s + diff_bw40_2s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); + } else +#endif + { + Write_2S_X_88XX_AC(Adapter, writeVal, i); + } + +#if defined(CONFIG_WLAN_HAL_8814AE) + //PATH i, BW40-3S + diff_bw40_3s = ((HAL_VAR_pwrdiff_5G_40BW3S_20BW3S_X[i] & 0xf0) >> 4); + diff_bw40_3s = convert_diff_88XX_AC(diff_bw40_3s); + tmp_TPI = pwr_40_1s + diff_bw40_2s + diff_bw40_3s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); + } else +#endif + { + Write_3S_X_88XX_AC(Adapter, writeVal, i); + } +#endif + } + } + } + //3 80M + else if (HAL_VAR_CurrentChannelBW == 2) { + + + for (i = 0; i < 4; i++) { + if(bPathXEn[i]) { + //PATH X, BW80-1S + pwr_40_1s = (HAL_VAR_pwrlevel5GHT40_1S_X_A[i] + + HAL_VAR_pwrlevel5GHT40_1S_X_B[i]) / 2 ; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + diff_bw80_1s = ((HAL_VAR_pwrdiff_5G_80BW1S_160BW1S_X[i] & 0xf0) >> 4); + diff_bw80_1s = convert_diff_88XX_AC(diff_bw80_1s); + tmp_TPI = pwr_40_1s + diff_bw80_1s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); + } else +#endif + { + Write_1S_X_88XX_AC(Adapter, writeVal, i); + } + + //PATH X, BW80-2S + diff_bw80_2s = ((HAL_VAR_pwrdiff_5G_80BW2S_160BW2S_X[i] & 0xf0) >> 4); + diff_bw80_2s = convert_diff_88XX_AC(diff_bw80_2s); + tmp_TPI = pwr_40_1s + diff_bw80_1s + diff_bw80_2s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); + } else +#endif + { + Write_2S_X_88XX_AC(Adapter, writeVal, i); + } + +#if defined(CONFIG_WLAN_HAL_8814AE) + //PATH X, BW80-2S + diff_bw80_3s = ((HAL_VAR_pwrdiff_5G_80BW3S_160BW3S_X[i] & 0xf0) >> 4); + diff_bw80_3s = convert_diff_88XX_AC(diff_bw80_3s); + //panic_printk("diff_bw80_3s=%c, %d\n",diff_bw80_3s,diff_bw80_3s); + tmp_TPI = pwr_40_1s + diff_bw80_1s + diff_bw80_2s +diff_bw80_3s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); + } else +#endif + { + Write_3S_X_88XX_AC(Adapter, writeVal, i); + } + +#endif + } + } + } +} + +void +CalOFDMTxPower2G_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte ch_idx +) +{ + u1Byte tmp_TPI = 0; + u1Byte pwr_40_1s = 0, ch_idx_ht40 = 0; + s1Byte diff_ofdm_1t = 0; + s1Byte diff_bw40_2s = 0; + s1Byte diff_bw40_3s = 0; + s1Byte diff_bw20_1s = 0; + s1Byte diff_bw20_2s = 0; + s1Byte diff_bw20_3s = 0; + u4Byte writeVal = 0; + u1Byte bPathXEn[4] = {0}; + u1Byte i; + + ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (HAL_VAR_DOT11CHANNEL-2) : (HAL_VAR_DOT11CHANNEL+2)) -1; + + u1Byte HAL_VAR_pwrlevelHT40_1S_X[4] = {HAL_VAR_pwrlevelHT40_1S_A(ch_idx), HAL_VAR_pwrlevelHT40_1S_B(ch_idx), + HAL_VAR_pwrlevelHT40_1S_C(ch_idx), HAL_VAR_pwrlevelHT40_1S_D(ch_idx) + }; + /* for 40M*/ + u1Byte HAL_VAR_pwrlevelHT40_1S_X_40M[4] = {HAL_VAR_pwrlevelHT40_1S_A(ch_idx_ht40), HAL_VAR_pwrlevelHT40_1S_B(ch_idx_ht40), + HAL_VAR_pwrlevelHT40_1S_C(ch_idx_ht40), HAL_VAR_pwrlevelHT40_1S_D(ch_idx_ht40) + }; + s1Byte HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[4] = {HAL_VAR_pwrdiff_20BW1S_OFDM1T_A(ch_idx), HAL_VAR_pwrdiff_20BW1S_OFDM1T_B(ch_idx), + HAL_VAR_pwrdiff_20BW1S_OFDM1T_C(ch_idx), HAL_VAR_pwrdiff_20BW1S_OFDM1T_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_40BW2S_20BW2S_X[4] = {HAL_VAR_pwrdiff_40BW2S_20BW2S_A(ch_idx), HAL_VAR_pwrdiff_40BW2S_20BW2S_B(ch_idx), + HAL_VAR_pwrdiff_40BW2S_20BW2S_C(ch_idx), HAL_VAR_pwrdiff_40BW2S_20BW2S_D(ch_idx) + }; + s1Byte HAL_VAR_pwrdiff_40BW3S_20BW3S_X[4] = {HAL_VAR_pwrdiff_40BW3S_20BW3S_A(ch_idx), HAL_VAR_pwrdiff_40BW3S_20BW3S_B(ch_idx), + HAL_VAR_pwrdiff_40BW3S_20BW3S_C(ch_idx), HAL_VAR_pwrdiff_40BW3S_20BW3S_D(ch_idx) + }; + + if (GetChipIDMIMO88XX(Adapter) == MIMO_4T4R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx) == 0) + ) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_3T3R) { + if(IS_HARDWARE_TYPE_8814A(Adapter)){ +#if defined(CONFIG_SLOT_0_8194_2T2R_SUPPORT) || defined(CONFIG_SLOT_1_8194_2T2R_SUPPORT) + bPathXEn[0] = 0; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0)){ + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } +#else + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 1; + if ((HAL_VAR_pwrlevelHT40_1S_B(ch_idx)== 0) || (HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0) + ||(HAL_VAR_pwrlevelHT40_1S_D(ch_idx)== 0) + ){ + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } +#endif + }else{ + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 1; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0) + ||(HAL_VAR_pwrlevelHT40_1S_C(ch_idx) == 0) + ) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + bPathXEn[0] = 1; + bPathXEn[1] = 1; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)||(HAL_VAR_pwrlevelHT40_1S_B(ch_idx) == 0)) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + else if (GetChipIDMIMO88XX(Adapter) == MIMO_1T1R) { + bPathXEn[0] = 1; + bPathXEn[1] = 0; + bPathXEn[2] = 0; + bPathXEn[3] = 0; + if ((HAL_VAR_pwrlevelHT40_1S_A(ch_idx)== 0)) { + use_DefaultOFDMTxPowerPathX88XX_AC(Adapter, bPathXEn); + return; + } + } + + + for(i = 0; i < 4; i++) { + // PATH X, OFDM + if(bPathXEn[i]) { + pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + diff_ofdm_1t = (HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[i] & 0x0f); + diff_ofdm_1t = convert_diff_88XX_AC(diff_ofdm_1t); + tmp_TPI = pwr_40_1s + diff_ofdm_1t; + //tmp_TPI = HAL_POWER_RANGE_CHECK(tmp_TPI ); +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_OFDM_54M, i, tmp_TPI); + } else +#endif + { + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; + Write_OFDM_X_88XX_AC(Adapter, writeVal, i); + } + } + } + //3 20M + if (HAL_VAR_dot11nUse40M == 0) { + + for (i = 0; i < 4; i++) { + if(bPathXEn[i]) { + //PATH A, BW20-1S + pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + diff_bw20_1s = ((HAL_VAR_pwrdiff_20BW1S_OFDM1T_X[i] & 0xf0) >> 4); + diff_bw20_1s = convert_diff_88XX_AC(diff_bw20_1s); + tmp_TPI = pwr_40_1s + diff_bw20_1s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); + } else +#endif + { + Write_1S_X_88XX_AC(Adapter, writeVal, i); + } + + //PATH A, BW20-2S + diff_bw20_2s = (HAL_VAR_pwrdiff_40BW2S_20BW2S_X[i] & 0x0f); + diff_bw20_2s = convert_diff_88XX_AC(diff_bw20_2s); + tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); + } else +#endif + { + Write_2S_X_88XX_AC(Adapter, writeVal, i); + } + +#if defined(CONFIG_WLAN_HAL_8814AE) + //PATH i, BW20-3S + diff_bw20_3s = (HAL_VAR_pwrdiff_40BW3S_20BW3S_X[i] & 0x0f); + diff_bw20_3s = convert_diff_88XX_AC(diff_bw20_3s); + tmp_TPI = pwr_40_1s + diff_bw20_1s + diff_bw20_2s + diff_bw20_3s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); + } else +#endif + { + Write_3S_X_88XX_AC(Adapter, writeVal, i); + } +#endif + } + } + //3 40M + } else if (HAL_VAR_dot11nUse40M == 1) { + for (i = 0; i < 4; i++) { + if(bPathXEn[i]) { + //PATH A, BW40-1S + pwr_40_1s = HAL_VAR_pwrlevelHT40_1S_X_40M[i]; + if(pwr_40_1s == 0) + pwr_40_1s = 0x12; + tmp_TPI = pwr_40_1s ; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS1_MCS0, TX_AGC_HT_NSS1_MCS7, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS1_MCS0, TX_AGC_VHT_NSS1_MCS9, i, tmp_TPI); + } else +#endif + { + Write_1S_X_88XX_AC(Adapter, writeVal, i); + } + + //PATH A, BW40-2S + diff_bw40_2s = ((HAL_VAR_pwrdiff_40BW2S_20BW2S_X[i] & 0xf0) >> 4); + diff_bw40_2s = convert_diff_88XX_AC(diff_bw40_2s); + tmp_TPI = pwr_40_1s + diff_bw40_2s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if (IS_RTL8814A_SERIES||IS_RTL8822B_SERIES) + if (( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))|| + ( IS_HARDWARE_TYPE_8822B(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE))){ + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS2_MCS8, TX_AGC_HT_NSS2_MCS15, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS2_MCS0, TX_AGC_VHT_NSS2_MCS9, i, tmp_TPI); + } else +#endif + { + Write_2S_X_88XX_AC(Adapter, writeVal, i); + } + +#if defined(CONFIG_WLAN_HAL_8814AE) + //PATH i, BW40-3S + diff_bw40_3s = ((HAL_VAR_pwrdiff_40BW3S_20BW3S_X[i] & 0xf0) >> 4); + diff_bw40_3s = convert_diff_88XX_AC(diff_bw40_3s); + tmp_TPI = pwr_40_1s + diff_bw40_2s + diff_bw40_3s; + writeVal = (tmp_TPI << 24) | (tmp_TPI << 16) | (tmp_TPI << 8) | tmp_TPI; +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_HT_NSS3_MCS16, TX_AGC_HT_NSS3_MCS23, i, tmp_TPI); + PHYSetTxPower88XX(Adapter, TX_AGC_VHT_NSS3_MCS0, TX_AGC_VHT_NSS3_MCS9, i, tmp_TPI); + } else +#endif + { + Write_3S_X_88XX_AC(Adapter, writeVal, i); + } +#endif + } + } + + } +} + + + +s1Byte +convert_diff_88XX_AC( + IN s1Byte value +) +{ + // range from -8 ~ 7 + if (value <= 7) + return value; + else + return (value - 16); +} + +void +Write_OFDM_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +) +{ + u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; + u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; + + HAL_RTL_W32(REG_BB_TXAGC_X_OFDM18_OFDM6_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[bPathXEnIdx], writeVal); +} + +void +Write_1S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +) +{ + u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; + u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; + u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; + u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; + HAL_RTL_W32(REG_BB_TXAGC_X_MCS3_MCS0_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS7_MCS4_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[bPathXEnIdx], writeVal); + // TODO: compare with Write_2S_X_88XX_AC, why don't we write only NSS1 (reference to Write_2S_X_88XX_AC) + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], writeVal); +} + + +void +Write_2S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +) +{ + u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; + u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_D_MCS15_MCS12_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; + + HAL_RTL_W32(REG_BB_TXAGC_X_MCS11_MCS8_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS15_MCS12_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[bPathXEnIdx], writeVal); + writeVal = (writeVal & 0xffff0000) | (HAL_RTL_R32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx]) & 0xffff); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[bPathXEnIdx], writeVal); +} + +void +Write_3S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +) +{ + u4Byte REG_BB_TXAGC_X_MCS19_MCS16_AC[4] = {REG_BB_TXAGC_A_MCS19_MCS16_AC, REG_BB_TXAGC_B_MCS19_MCS16_AC, REG_BB_TXAGC_C_MCS19_MCS16_AC, REG_BB_TXAGC_D_MCS19_MCS16_AC}; + u4Byte REG_BB_TXAGC_X_MCS23_MCS20_AC[4] = {REG_BB_TXAGC_A_MCS23_MCS20_AC, REG_BB_TXAGC_B_MCS23_MCS20_AC, REG_BB_TXAGC_C_MCS23_MCS20_AC, REG_BB_TXAGC_D_MCS23_MCS20_AC}; + u4Byte REG_BB_TXAGC_X_NSS3INDEX3_NSS3INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_B_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_C_NSS3INDEX3_NSS3INDEX0_AC, REG_BB_TXAGC_D_NSS3INDEX3_NSS3INDEX0_AC}; + u4Byte REG_BB_TXAGC_X_NSS3INDEX7_NSS3INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_B_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_C_NSS3INDEX7_NSS3INDEX4_AC, REG_BB_TXAGC_D_NSS3INDEX7_NSS3INDEX4_AC}; + u4Byte REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_B_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_C_NSS3INDEX9_NSS3INDEX8_AC, REG_BB_TXAGC_D_NSS3INDEX9_NSS3INDEX8_AC}; + + HAL_RTL_W32(REG_BB_TXAGC_X_MCS19_MCS16_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS23_MCS20_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX3_NSS3INDEX0_AC[bPathXEnIdx], writeVal); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX7_NSS3INDEX4_AC[bPathXEnIdx], writeVal); + writeVal = (writeVal & 0xffff) | (HAL_RTL_R32(REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[bPathXEnIdx]) & 0xffff0000); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS3INDEX9_NSS3INDEX8_AC[bPathXEnIdx], writeVal); +} + +void +use_DefaultOFDMTxPowerPathX88XX_AC( + IN HAL_PADAPTER Adapter, + IN pu1Byte bPathXEn +) +{ + u4Byte def_power = 0x20202020; //eric-8822 ?? //0x12121212; //0x20202020; + u4Byte REG_BB_TXAGC_X_OFDM18_OFDM6_AC[4] = {REG_BB_TXAGC_A_OFDM18_OFDM6_AC, REG_BB_TXAGC_B_OFDM18_OFDM6_AC, REG_BB_TXAGC_C_OFDM18_OFDM6_AC, REG_BB_TXAGC_D_OFDM18_OFDM6_AC}; + u4Byte REG_BB_TXAGC_X_OFDM54_OFDM24_AC[4] = {REG_BB_TXAGC_A_OFDM54_OFDM24_AC, REG_BB_TXAGC_B_OFDM54_OFDM24_AC, REG_BB_TXAGC_C_OFDM54_OFDM24_AC, REG_BB_TXAGC_D_OFDM54_OFDM24_AC}; + u4Byte REG_BB_TXAGC_X_MCS3_MCS0_AC[4] = {REG_BB_TXAGC_A_MCS3_MCS0_AC, REG_BB_TXAGC_B_MCS3_MCS0_AC, REG_BB_TXAGC_C_MCS3_MCS0_AC, REG_BB_TXAGC_D_MCS3_MCS0_AC}; + u4Byte REG_BB_TXAGC_X_MCS7_MCS4_AC[4] = {REG_BB_TXAGC_A_MCS7_MCS4_AC, REG_BB_TXAGC_B_MCS7_MCS4_AC, REG_BB_TXAGC_C_MCS7_MCS4_AC, REG_BB_TXAGC_D_MCS7_MCS4_AC}; + u4Byte REG_BB_TXAGC_X_MCS11_MCS8_AC[4] = {REG_BB_TXAGC_A_MCS11_MCS8_AC, REG_BB_TXAGC_B_MCS11_MCS8_AC, REG_BB_TXAGC_C_MCS11_MCS8_AC, REG_BB_TXAGC_D_MCS11_MCS8_AC}; + u4Byte REG_BB_TXAGC_X_MCS15_MCS12_AC[4] = {REG_BB_TXAGC_A_MCS15_MCS12_AC, REG_BB_TXAGC_B_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC, REG_BB_TXAGC_C_MCS15_MCS12_AC}; + u4Byte REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_C_NSS1INDEX3_NSS1INDEX0_AC, REG_BB_TXAGC_D_NSS1INDEX3_NSS1INDEX0_AC}; + u4Byte REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[4] = {REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_C_NSS1INDEX7_NSS1INDEX4_AC, REG_BB_TXAGC_D_NSS1INDEX7_NSS1INDEX4_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_C_NSS2INDEX1_NSS1INDEX8_AC, REG_BB_TXAGC_D_NSS2INDEX1_NSS1INDEX8_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_C_NSS2INDEX5_NSS2INDEX2_AC, REG_BB_TXAGC_D_NSS2INDEX5_NSS2INDEX2_AC}; + u4Byte REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[4] = {REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_C_NSS2INDEX9_NSS2INDEX6_AC, REG_BB_TXAGC_D_NSS2INDEX9_NSS2INDEX6_AC}; + u1Byte i; + + u1Byte def_power_value = 0x16; + + for (i = 0; i < 4; i++) { + if (bPathXEn[i]) { +#if IS_RTL8814A_SERIES + if ( IS_HARDWARE_TYPE_8814A(Adapter) && (IS_HAL_TEST_CHIP(Adapter)==FALSE)) { + PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_VHT_NSS4_MCS9, i, def_power_value); + } else +#endif +#if IS_RTL8822B_SERIES //eric-8822 + if ( IS_HARDWARE_TYPE_8822BE(Adapter)) { +#if 1 + if(i == 0 && Adapter->pshare->rf_ft_var.txa) + def_power_value = Adapter->pshare->rf_ft_var.txa; + + if(i == 1 && Adapter->pshare->rf_ft_var.txb) + def_power_value = Adapter->pshare->rf_ft_var.txb; + +#endif + PHYSetTxPower88XX(Adapter, TX_AGC_OFDM_6M, TX_AGC_VHT_NSS2_MCS9, i, def_power_value); + } else +#endif + + { + HAL_RTL_W32(REG_BB_TXAGC_X_OFDM18_OFDM6_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_OFDM54_OFDM24_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS3_MCS0_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS7_MCS4_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS11_MCS8_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_MCS15_MCS12_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX3_NSS1INDEX0_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS1INDEX7_NSS1INDEX4_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX1_NSS1INDEX8_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX5_NSS2INDEX2_AC[i], def_power); + HAL_RTL_W32(REG_BB_TXAGC_X_NSS2INDEX9_NSS2INDEX6_AC[i], def_power); + } + } + } +} + +#endif //#if IS_RTL88XX_AC + + +#if IS_RTL88XX_N + +void +phy_RFSerialWrite_88XX_N +( + IN HAL_PADAPTER Adapter, + IN RFRF88XX_RADIO_PATH_E eRFPath, + IN u4Byte Offset, + IN u4Byte Data +) +{ + u4Byte DataAndAddr = 0; + u4Byte NewOffset; + + Offset &= 0xff; + + // + // Switch page for 8256 RF IC + // + NewOffset = Offset; + + // + // Put write addr in [5:0] and write data in [31:16] + // + //DataAndAddr = (Data<<16) | (NewOffset&0x3f); + DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; // T65 RF + + // + // Write Operation + // + if (eRFPath == RF88XX_PATH_A) { + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_LSSIPARAMETER_N, BIT_MASK_SET_MASKDWORD_COMMON, DataAndAddr); + } else { + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_LSSIPARAMETER_N, BIT_MASK_SET_MASKDWORD_COMMON, DataAndAddr); + } +} + +u4Byte +phy_RFSerialRead_88XX_N +( + IN HAL_PADAPTER Adapter, + IN RFRF88XX_RADIO_PATH_E eRFPath, + IN u4Byte Offset +) +{ + u4Byte tmplong, tmplong2; + u4Byte retValue = 0; + u4Byte NewOffset; + + // + // Make sure RF register offset is correct + // + + Offset &= 0xff; + + + // + // Switch page for 8256 RF IC + // + NewOffset = Offset; + + // For 92S LSSI Read RFLSSIRead + // For RF A/B write 0x824/82c(does not work in the future) + // We must use 0x824 for RF A and B to execute read trigger + // 1. PathA : addr write 0x824, Path B : addr write 0x82c + + if (eRFPath == RF88XX_PATH_A) { + tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON);; + tmplong2 = (tmplong2 & (~BIT_MASK_BB_LSSIREADADDRESS_N)) | (NewOffset << 23) | BIT_MASK_BB_LSSIREADEDGE_N; //T65 RF + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); + } else { + tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XB_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON); + tmplong2 = (tmplong2 & (~BIT_MASK_BB_LSSIREADADDRESS_N)) | (NewOffset << 23) | BIT_MASK_BB_LSSIREADEDGE_N; //T65 RF + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XB_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); + } + + tmplong2 = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON); + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 & (~BIT_MASK_BB_LSSIREADEDGE_N)); + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_XA_HSSIPARAMETER2_N, BIT_MASK_SET_MASKDWORD_COMMON, tmplong2 | BIT_MASK_BB_LSSIREADEDGE_N); + + delay_us(20); + + // 1. Path A, PI mode read data from 0x8b8 + // 2. Path A, SI mode read data from 0x8a0 + // 3. Path B, PI mode read data from 0x8bc + // 4. Path B, SI mode read data from 0x8a4 + + if (eRFPath == RF88XX_PATH_A) { + if ((HAL_RTL_R32(REG_BB_FPGA0_XA_HSSIPARAMETER1_N)&BIT(8))) { + retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_TRANSCEIVERA_HSPI_READBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); + } else { + retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XA_LSSIREADBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); + } + } else if (eRFPath == RF88XX_PATH_B) { + if ((HAL_RTL_R32(REG_BB_FPGA0_XB_HSSIPARAMETER1_N)&BIT(8))) { + retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_TRANSCEIVERB_HSPI_READBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); + } else { + retValue = PHY_QueryBBReg_88XX(Adapter, REG_BB_FPGA0_XB_LSSIREADBACK_N, BIT_MASK_BB_LSSIREADBACKDATA_N); + } + } + + + return retValue; +} + +void PHY_SetRFReg_88XX_N +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +) +{ + u4Byte Original_Value, BitShift, New_Value; + HAL_PADAPTER priv = Adapter; + u4Byte flags; + +#if CFG_HAL_DISABLE_BB_RF + return; +#endif //CFG_HAL_DISABLE_BB_RF + + HAL_SAVE_INT_AND_CLI(flags); + + if (BitMask != BIT_MASK_SET_MASK20BITS_COMMON) { + Original_Value = phy_RFSerialRead_88XX_N(Adapter, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift_88XX(BitMask); + New_Value = ((Original_Value & (~BitMask)) | (Data << BitShift)); + + phy_RFSerialWrite_88XX_N(Adapter, eRFPath, RegAddr, New_Value); + } else { + phy_RFSerialWrite_88XX_N(Adapter, eRFPath, RegAddr, Data); + } + + HAL_RESTORE_INT(flags); + delay_us(4); // At least 500ns delay to avoid RF write fail. +} + +u4Byte +PHY_QueryRFReg_88XX_N +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + HAL_PADAPTER priv = Adapter; + u4Byte flags; + u4Byte Original_Value, Readback_Value, BitShift; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + + HAL_SAVE_INT_AND_CLI(flags); + Original_Value = phy_RFSerialRead_88XX_N(Adapter, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift_88XX(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + HAL_RESTORE_INT(flags); + + return (Readback_Value); +} + +RT_STATUS +PHYSetOFDMTxPower88XX_N( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +) +{ + u4Byte writeVal, defValue = 0x28, pwrdiff = 0x06060606; + u1Byte offset, ch_idx=0, ch_idx_ht40=0; + u1Byte pwrlevelHT40_1S_A = 0; + u1Byte pwrlevelHT40_1S_B = 0; + u1Byte pwrdiffHT40_2S = 0; + u1Byte pwrdiffHT20 = HAL_VAR_pwrdiffHT20(channel - 1); + u1Byte pwrdiffOFDM = HAL_VAR_pwrdiffOFDM(channel - 1); + u1Byte base, byte0, byte1, byte2, byte3; + u1Byte phy_band = 0, is_coexist = 0; + PRTL8192CD_PRIV priv = Adapter; +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + s1Byte pwrdiff_percent = HAL_PwrPercent2PwrLevel(HAL_VAR_power_percent); +#endif + + if (channel > 0) { + ch_idx = (channel - 1); + ch_idx_ht40 = ((HAL_VAR_OFFSET_2ND_CHANNEL==1) ? (channel-2) : (channel+2)) -1; + } else { + RT_TRACE_F(COMP_RF, DBG_WARNING, ("Error Channel !!\n")); + return RT_STATUS_FAILURE; + } + + if (channel > CHANNEL_MAX_NUMBER_2G) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; + + +#ifdef WIFI_11N_2040_COEXIST + if(COEXIST_ENABLE && (((HAL_OPMODE & WIFI_AP_STATE) && + (Adapter->bg_ap_timeout || orForce20_Switch20Map(Adapter) + )) + )) + is_coexist = 1; +#endif + + if ((HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) || is_coexist) { + pwrlevelHT40_1S_A = HAL_VAR_pwrlevelHT40_1S_A(ch_idx); + pwrlevelHT40_1S_B = HAL_VAR_pwrlevelHT40_1S_B(ch_idx); + pwrdiffHT40_2S = HAL_VAR_pwrdiffHT40_2S(ch_idx); + } else if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { + pwrlevelHT40_1S_A = HAL_VAR_pwrlevelHT40_1S_A(ch_idx_ht40); + pwrlevelHT40_1S_B = HAL_VAR_pwrlevelHT40_1S_B(ch_idx_ht40); + pwrdiffHT40_2S = HAL_VAR_pwrdiffHT40_2S(ch_idx_ht40); + } + + if ((pwrlevelHT40_1S_A == 0) ) + + { + // use default value + +#if CFG_HAL_HIGH_POWER_EXT_PA + if (HAL_VAR_use_ext_pa) + defValue = HP_OFDM_POWER_DEFAULT ; +#endif +#if (!CFG_HAL_ADD_TX_POWER_BY_CMD) + writeVal = (defValue << 24) | (defValue << 16) | (defValue << 8) | (defValue); + HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); +#else + + base = defValue; + byte0 = byte1 = byte2 = byte3 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_ofdm_18); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_ofdm_12); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_ofdm_9); + HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_ofdm_6); + + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); + + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); + + byte0 = byte1 = byte2 = byte3 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_ofdm_54); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_ofdm_48); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_ofdm_36); + HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_ofdm_24); + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); + + byte0 = byte1 = byte2 = byte3 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_mcs_3); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_mcs_2); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_mcs_1); + HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_mcs_0); + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); + + byte0 = byte1 = byte2 = byte3 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte0, HAL_VAR_txPowerPlus_mcs_7); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_VAR_txPowerPlus_mcs_6); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_VAR_txPowerPlus_mcs_5); + HAL_ASSIGN_TX_POWER_OFFSET(byte3, HAL_VAR_txPowerPlus_mcs_4); + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); + + byte0 = byte1 = byte2 = byte3 = 0; + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); + + byte0 = byte1 = byte2 = byte3 = 0; + byte0 = HAL_POWER_RANGE_CHECK(base + byte0); + byte1 = HAL_POWER_RANGE_CHECK(base + byte1); + byte2 = HAL_POWER_RANGE_CHECK(base + byte2); + byte3 = HAL_POWER_RANGE_CHECK(base + byte3); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) + HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); + +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { + TxLMT_OFDM_Jaguar_N(Adapter); + } + } +#endif // TXPWR_LMT + +#endif // ADD_TX_POWER_BY_CMD + return RT_STATUS_SUCCESS; // use default + } + + /****************************** PATH A ******************************/ + base = pwrlevelHT40_1S_A; + offset = (pwrdiffOFDM & 0x0f); + base = HAL_COUNT_SIGN_OFFSET(base, offset); +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); +#endif + + // fill 6Mbps ~ 18Mbps + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(0)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(1)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(2)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(3)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_RATE18_06_N, writeVal); + + // fill 24Mbps ~ 54Mbps + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(4)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(5)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(6)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_A(7)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_RATE54_24_N, writeVal); + + // cal HT rate diff + base = pwrlevelHT40_1S_A; + if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) { + offset = (pwrdiffHT20 & 0x0f); + base = HAL_COUNT_SIGN_OFFSET(base, offset); + } +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); +#endif + + // fill MCS0~MCS3 + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(0)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(1)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(2)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(3)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS03_MCS00_N, writeVal); + + // fill MCS4~MCS7 + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(4)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(5)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(6)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(7)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS07_MCS04_N, writeVal); + + offset = (pwrdiffHT40_2S & 0x0f); + base = HAL_COUNT_SIGN_OFFSET(base, offset); + + + //_TXPWR_REDEFINE ?? MCS 8 - 11, shall NOT add power by rate even NOT USB power ?? + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(8)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(9)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(10)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(11)); + + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + + //DEBUG_INFO("debug e18:%x,%x,[%x,%x,%x,%x],%x\n", offset, base, byte0, byte1, byte2, byte3, writeVal); + HAL_RTL_W32(REG_BB_TXAGC_A_MCS11_MCS08_N, writeVal); + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(12)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(13)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(14)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_A(15)); + + writeVal = (byte0<<24) | (byte1<<16) |(byte2<<8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_A_MCS15_MCS12_N, writeVal); + + /****************************** PATH B ******************************/ + + if (GetChipIDMIMO88XX(Adapter) == MIMO_2T2R) { + + base = pwrlevelHT40_1S_B; + offset = ((pwrdiffOFDM & 0xf0) >> 4); + base = HAL_COUNT_SIGN_OFFSET(base, offset); +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); +#endif + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(0)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(1)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(2)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(3)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_RATE18_06_N, writeVal); + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(4)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(5)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(6)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_OFDMTxAgcOffset_B(7)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_RATE54_24_N, writeVal); + + base = pwrlevelHT40_1S_B; + if (HAL_VAR_CurrentChannelBW == HT_CHANNEL_WIDTH_20) { + offset = ((pwrdiffHT20 & 0xf0) >> 4); + base = HAL_COUNT_SIGN_OFFSET(base, offset); + } +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + base = HAL_POWER_RANGE_CHECK(base + pwrdiff_percent); +#endif + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(0)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(1)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(2)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(3)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS03_MCS00_N, writeVal); + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(4)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(5)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(6)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(7)); + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS07_MCS04_N, writeVal); + + offset = ((pwrdiffHT40_2S & 0xf0) >> 4); + base = HAL_COUNT_SIGN_OFFSET(base, offset); + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(8)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(9)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(10)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(11)); + + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS11_MCS08_N, writeVal); + + byte0 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(12)); + byte1 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(13)); + byte2 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(14)); + byte3 = HAL_POWER_RANGE_CHECK(base + HAL_VAR_MCSTxAgcOffset_B(15)); + + writeVal = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3; + HAL_RTL_W32(REG_BB_TXAGC_B_MCS15_MCS12_N, writeVal); + } +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { + TxLMT_OFDM_Jaguar_N(Adapter); + } + } +#endif // TXPWR_LMT + + return RT_STATUS_SUCCESS; +} + +RT_STATUS +PHYSetCCKTxPower88XX_N( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +) +{ + unsigned int writeVal = 0, pwrdiff = 0x06060606; + u1Byte byte, byte1, byte2; + u1Byte pwrlevelCCK_A = HAL_VAR_pwrlevelCCK_A(channel-1); + u1Byte pwrlevelCCK_B = HAL_VAR_pwrlevelCCK_B(channel-1); +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + s1Byte pwrdiff_percent = HAL_PwrPercent2PwrLevel(HAL_VAR_power_percent); +#endif + u1Byte phy_band = 0; + + if (channel > CHANNEL_MAX_NUMBER_2G) + phy_band = PHY_BAND_5G; + else + phy_band = PHY_BAND_2G; + + if (HAL_cck_pwr_max) { + byte = HAL_POWER_RANGE_CHECK((char)HAL_cck_pwr_max); + writeVal = byte; + Adapter->pshare->rf_ft_var.bcn_pwr_idex=writeVal; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); + writeVal = (byte << 16) | (byte << 8) | byte; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); + writeVal = (byte << 24) | (byte << 16) | (byte << 8) | byte; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); + return RT_STATUS_SUCCESS; + } + + if ((pwrlevelCCK_A == 0 && pwrlevelCCK_B == 0)) { +#if CFG_HAL_HIGH_POWER_EXT_PA + if (HAL_VAR_use_ext_pa) + byte = HP_CCK_POWER_DEFAULT; + else +#endif + byte = 0x24; + + +#if (!CFG_HAL_ADD_TX_POWER_BY_CMD) + // use default value + writeVal = byte; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); + writeVal = (byte << 16) | (byte << 8) | byte; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); + writeVal = (byte << 24) | (byte << 16) | (byte << 8) | byte; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); +#else + // use cmd value + pwrlevelCCK_A = pwrlevelCCK_B = byte; + byte = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_1); + + writeVal = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); + + byte = byte1 = byte2 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_1); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_txPowerPlus_cck_2); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_txPowerPlus_cck_5); + byte = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte); + byte1 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte1); + byte2 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + byte2); + + writeVal = ((byte2 << 16) | (byte1 << 8) | byte); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); + + byte = byte1 = byte2 = 0; + HAL_ASSIGN_TX_POWER_OFFSET(byte, HAL_txPowerPlus_cck_2); + HAL_ASSIGN_TX_POWER_OFFSET(byte1, HAL_txPowerPlus_cck_5); + HAL_ASSIGN_TX_POWER_OFFSET(byte2, HAL_txPowerPlus_cck_11); + byte = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte); + byte1 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte1); + byte2 = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + byte2); + writeVal = ((byte2 << 24) | (byte1 << 16) | (byte << 8) | byte2); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); + +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { + TxLMT_CCK_Jaguar_N(Adapter); + } + } +#endif // TXPWR_LMT + +#endif + { + int cck1a = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00); + int cck1b = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00); + if(cck1a>Adapter->pshare->rf_ft_var.bcn_pwr_max) { + cck1a = Adapter->pshare->rf_ft_var.bcn_pwr_max; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, cck1a); + } + if(cck1b>Adapter->pshare->rf_ft_var.bcn_pwr_max) { + cck1b = Adapter->pshare->rf_ft_var.bcn_pwr_max; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00, cck1b); + } + Adapter->pshare->rf_ft_var.bcn_pwr_idex= max(cck1a,cck1b); + } + return RT_STATUS_SUCCESS; // use default + } +#if CFG_HAL_POWER_PERCENT_ADJUSTMENT + pwrlevelCCK_A = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + pwrdiff_percent); + pwrlevelCCK_B = HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + pwrdiff_percent); +#endif + + // use flash value to fill + + writeVal = HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(3) + Adapter->pmib->dot11RFEntry.add_cck1M_pwr); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, writeVal); + writeVal = (HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(1)) << 16) | + (HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(2)) << 8) | + HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(3) + Adapter->pmib->dot11RFEntry.add_cck1M_pwr); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0xffffff00, writeVal); + writeVal = (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(0)) << 24) | + (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(1)) << 16) | + (HAL_POWER_RANGE_CHECK(pwrlevelCCK_A + HAL_CCKTxAgc_A(2)) << 8) | + HAL_POWER_RANGE_CHECK(pwrlevelCCK_B + HAL_CCKTxAgc_B(0)); + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK11_2_B_CCK11_N, 0xffffffff, writeVal); + +#ifdef TXPWR_LMT + if (!Adapter->pshare->rf_ft_var.disable_txpwrlmt) { + if (HAL_check_lmt_valid(Adapter, phy_band)) { + TxLMT_CCK_Jaguar_N(Adapter); + } + } +#endif // TXPWR_LMT + + { + int cck1a = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00); + int cck1b = PHY_QueryBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00); + if(cck1a>Adapter->pshare->rf_ft_var.bcn_pwr_max) { + cck1a = Adapter->pshare->rf_ft_var.bcn_pwr_max; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_A_CCK1_MCS32_N, 0x0000ff00, cck1a); + } + if(cck1b>Adapter->pshare->rf_ft_var.bcn_pwr_max) { + cck1b = Adapter->pshare->rf_ft_var.bcn_pwr_max; + PHY_SetBBReg_88XX(Adapter, REG_BB_TXAGC_B_CCK5_1_MCS32_N, 0x0000ff00, cck1b); + } + Adapter->pshare->rf_ft_var.bcn_pwr_idex= max(cck1a,cck1b); + } + + return RT_STATUS_SUCCESS; +} + +#if 0 +void +printk92E(IN HAL_PADAPTER Adapter) +{ + printk("0x440 = %x\n", HAL_RTL_R32(0x440)); + + printk("0x800 = %x\n", HAL_RTL_R32(0x800)); + printk("0xa00 = %x\n", HAL_RTL_R32(0xa00)); + printk("0xd00 = %x\n", HAL_RTL_R32(0xd00)); + printk("0x818 = %x\n", HAL_RTL_R32(0x818)); + printk("0x800 = %x\n", HAL_RTL_R32(0x800)); + + printk("RF TRX_BW RF PathA 0x18=%x \n", PHY_QueryRFReg_88XX_N(Adapter, 0, 0x18, 0xffffffff)); + + printk("RF TRX_BW RF PathB 0x18=%x \n", PHY_QueryRFReg_88XX_N(Adapter, 1, 0x18, 0xffffffff)); + + printk("RF TRX_BW RF PathA 0x18=%x \n", PHY_QueryRFReg(Adapter, 0, 0x18, 0xffffffff, 1)); + + printk("RF TRX_BW RF PathB 0x18=%x \n", PHY_QueryRFReg(Adapter, 1, 0x18, 0xffffffff, 1)); + +} +#endif + +void +SwBWMode88XX_N( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +) +{ + u4Byte eRFPath, curMaxRFPath, val, rrSR = 0; + u1Byte nCur40MhzPrimeSC, regDataSC; + unsigned int dwTmp1 = 0, dwTmp2 = 0, dwTmp3 = 0; + + RT_TRACE(COMP_RF, DBG_TRACE, ("SwBWMode(): Switch to %s bandwidth\n", bandwidth ? "40MHz" : "20MHz")); + + curMaxRFPath = RF88XX_PATH_MAX; + + if (offset == 1) + nCur40MhzPrimeSC = 2; + else + nCur40MhzPrimeSC = 1; + + //3 <1> Set MAC register + rrSR = HAL_RTL_R32(REG_RRSR); + rrSR &= ~(BIT(21) | BIT(22)); + + regDataSC = HAL_RTL_R8(0x483); + + if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { + dwTmp1 = HAL_RTL_R32(0x800); + dwTmp2 = HAL_RTL_R32(0xce4); + dwTmp3 = HAL_RTL_R32(0xc30); + dwTmp1 &= ~(BIT(10) | BIT(9) | BIT(8) | BIT(13) | BIT(12) | BIT(14)); + dwTmp2 &= ~(BIT(31) | BIT(30)); + dwTmp3 &= ~(BIT(10) | BIT(9) | BIT(8)); + } + switch (bandwidth) { + case HT_CHANNEL_WIDTH_20: + if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { + dwTmp3 |= (BIT(10)); + HAL_RTL_W32(0xc30, dwTmp3); + } + break; + case HT_CHANNEL_WIDTH_20_40: + HAL_RTL_W32(REG_RRSR, rrSR); + + regDataSC &= 0xf0; + regDataSC |= Adapter->pshare->txsc_20_92e; + HAL_RTL_W8(0x483, regDataSC); + + // Let 812cd_rx, re-assign value + if (HAL_VAR_IS_40M_BW) { + HAL_VAR_REG_RRSR_2 = 0; + HAL_VAR_REG_81B = 0; + } + if (IS_C_CUT_8192E(Adapter) || IS_D_CUT_8192E(Adapter)) { + dwTmp3 |= (BIT(10)); + HAL_RTL_W32(0xc30, dwTmp3); + } + break; + if (IS_C_CUT_8192E(Adapter)) { + case HT_CHANNEL_WIDTH_10: + dwTmp1 |= (BIT(10) | BIT(8) | BIT(12) | BIT(14)); + dwTmp2 |= (BIT(31)); + dwTmp3 |= (BIT(10) | BIT(9)); + HAL_RTL_W32(0x800, dwTmp1); + HAL_RTL_W32(0xce4, dwTmp2); + HAL_RTL_W32(0xc30, dwTmp3); + break; + case HT_CHANNEL_WIDTH_5: + dwTmp1 |= (BIT(10) | BIT(8) | BIT(14)); + dwTmp2 |= (BIT(30)); + dwTmp3 |= (BIT(10) | BIT(9) | BIT(8)); + HAL_RTL_W32(0x800, dwTmp1); + HAL_RTL_W32(0xce4, dwTmp2); + HAL_RTL_W32(0xc30, dwTmp3); + break; + } + default: + RT_TRACE(COMP_RF, DBG_LOUD, ("SwBWMode(): bandwidth mode error!\n")); + return; + break; + } + + //3 <2> Set PHY related register + switch (bandwidth) { + case HT_CHANNEL_WIDTH_20: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x0); + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA1_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x0); + val = 3; + break; + case HT_CHANNEL_WIDTH_20_40: + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA0_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x1); + PHY_SetBBReg_88XX(Adapter, REG_BB_FPGA1_RFMOD_N, BIT_MASK_BB_RFMOD_N_N, 0x1); + // Set Control channel to upper or lower. These settings are required only for 40MHz + PHY_SetBBReg_88XX(Adapter, REG_BB_CCK0_SYSTEM_N, BIT_MASK_BB_CCKSIDEBAND_N, (nCur40MhzPrimeSC >> 1)); + PHY_SetBBReg_88XX(Adapter, REG_BB_OFDM1_LSTF_N, 0xC00, nCur40MhzPrimeSC); + val = 1; + + PHY_SetBBReg_88XX(Adapter, REG_BB_PRIMESC_N, (BIT(26) | BIT(27)), (nCur40MhzPrimeSC == 2) ? 1 : 2); + break; + default: + RT_TRACE(COMP_RF, DBG_LOUD, ("SwBWMode(): bandwidth mode error! %d\n", __LINE__)); + return; + break; + } + + for (eRFPath = RF88XX_PATH_A; eRFPath < curMaxRFPath; eRFPath++) + PHY_SetRFReg_88XX_N(Adapter, eRFPath, REG_RF_RFCHANNEL_N, (BIT(11) | BIT(10)), val); +} + + + + +/* ---------------------------------- + Power Tracking Realted functions +--------------------------------------*/ +#if 0 +void +TXPowerTracking_ThermalMeter_88XX +( + IN HAL_PADAPTER Adapter +) +{ + u1Byte ThermalValue = 0, delta, channel, is_decrease, rf_mimo_mode; + u1Byte ThermalValue_AVG_count = 0; + u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur + s1Byte OFDM_index[2], index ; + u4Byte ThermalValue_AVG = 0; + u4Byte i = 0, j = 0, rf; + s4Byte value32, CCK_index, ele_A, ele_D, ele_C, X, Y; + PRTL8192CD_PRIV priv = Adapter; + + rf_mimo_mode = GetChipIDMIMO88XX(Adapter); + +#ifdef CFG_HAL_MP_TEST + if ((HAL_OPMODE & WIFI_MP_STATE) || HAL_VAR_MP_SPECIFIC) { + channel = HAL_VAR_WORKING_CHANNEL; + //printk("MP start , channel = %x \n",channel); + if (HAL_VAR_MP_TXPWR_TRACKING == FALSE) + return; + } else +#endif + { + channel = HAL_VAR_DOT11CHANNEL; + } + + if (HAL_VAR_POWER_TRACKING_ON_88XX == 0) { + HAL_VAR_POWER_TRACKING_ON_88XX = 1; + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("TXPowerTracking_ThermalMeter_88XX: First Timer set 0x42\n")); + //printk("First Timer set 0x42\n"); + PHY_SetRFReg_88XX_N(Adapter, RF88XX_PATH_A, REG_RF_CSI_MASK_N, (BIT(17) | BIT(16)), 0x03); + return; + } + //else + { + // HAL_VAR_POWER_TRACKING_ON_88XX = 0; + ThermalValue = (unsigned char)PHY_QueryRFReg_88XX_N(Adapter, RF88XX_PATH_A, REG_RF_CSI_MASK_N, 0xfc00); //0x42: RF Reg[15:10] 88E + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, HAL_VAR_THERMALVALUE, HAL_VAR_THER)); + //printk("\nReadback Thermal Meter = %x \n",ThermalValue); + } + + switch (rf_mimo_mode) { + case MIMO_1T1R: + rf = 1; + //printk("%s:%d get_rf_mimo_mode =1 !\n", __FUNCTION__, __LINE__); + break; + case MIMO_2T2R: + rf = 2; + //printk("%s:%d get_rf_mimo_mode =2 !\n", __FUNCTION__, __LINE__); + break; + default: + //printk("%s:%d get_rf_mimo_mode error!\n", __FUNCTION__, __LINE__); + break; + } + + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKOFDM_D_COMMON); + //printk("0xc80 ele_D = %x \n",ele_D); + // TODO : need to check mask + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[0] = (unsigned char)i; + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); + break; + } + } + + //Query OFDM path B default setting + if (rf_mimo_mode == MIMO_2T2R) { + ele_D = PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKOFDM_D_COMMON); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[1] = (unsigned char)i; + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); + //printk("PathB 0xe1c[31:21] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); + break; + } + } + } + + /* Initialize */ + // if first time use flash default PG value + if (!HAL_VAR_THERMALVALUE) { + HAL_VAR_THERMALVALUE = HAL_VAR_THER; + //printk("HAL_VAR_THERMALVALUE = %x \n",HAL_VAR_THERMALVALUE); + } + + /* calculate average thermal meter */ + { + HAL_VAR_THERMALVALUE_AVG_88XX(HAL_VAR_THERMALVALUE_AVG_INDEX_88XX) = ThermalValue; + HAL_VAR_THERMALVALUE_AVG_INDEX_88XX++; + if (HAL_VAR_THERMALVALUE_AVG_INDEX_88XX == AVG_THERMAL_NUM_88XX) + HAL_VAR_THERMALVALUE_AVG_INDEX_88XX = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { + if (HAL_VAR_THERMALVALUE_AVG_88XX(i)) { + ThermalValue_AVG += HAL_VAR_THERMALVALUE_AVG_88XX(i); + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); + } + } + + if (ThermalValue != HAL_VAR_THERMALVALUE) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\n******** START:%s() ********\n", __FUNCTION__)); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, HAL_VAR_THERMALVALUE, HAL_VAR_THER)); + + delta = HAL_RTL_ABS(ThermalValue, HAL_VAR_THER); + is_decrease = ((ThermalValue < HAL_VAR_THER) ? 1 : 0); + + //printk("delta = %x \n",delta); + //printk("is_decrease = %x \n",is_decrease); + + if (HAL_VAR_PHYBANDSELECT == PHY_BAND_2G) { +#ifdef CFG_TRACKING_TABLE_FILE + if (HAL_VAR_PWR_TRACK_FILE) { + + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = HAL_VAR_OFDM_BASE_INDEX(i) + get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E - 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0))); + //printk(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0)); + CCK_index = HAL_VAR_CCK_BASE_INDEX + get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, HAL_VAR_CCK_BASE_INDEX, get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1))); + CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = HAL_VAR_OFDM_BASE_INDEX(i) - get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0); + //printk("HAL_VAR_OFDM_BASE_INDEX(i) = %x OFDM_index[i] =%x \n",HAL_VAR_OFDM_BASE_INDEX(i),OFDM_index[i]); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0))); + //printk(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], HAL_VAR_OFDM_BASE_INDEX(i), get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 0)); + CCK_index = HAL_VAR_CCK_BASE_INDEX - get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, (">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, HAL_VAR_CCK_BASE_INDEX, get_tx_tracking_index_88XX(Adapter, channel, i, delta, is_decrease, 1))); + //printk("HAL_VAR_CCK_BASE_INDEX = %x CCK_index =%x \n",HAL_VAR_CCK_BASE_INDEX,CCK_index); + CCK_index = ((CCK_index < 0 ) ? 0 : CCK_index); + //printk("HAL_VAR_CCK_BASE_INDEX = %x CCK_index =%x \n",HAL_VAR_CCK_BASE_INDEX,CCK_index); + } + } + } +#endif //CFG_TRACKING_TABLE_FILE + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n", OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n", OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; + X = Adapter->pshare->RegE94; + Y = Adapter->pshare->RegE9C; + + if (X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XCTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(24), value32); + + } else { + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XCTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, 0x00); + PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(24), 0x00); + } + + set_CCK_swing_index_88XX(Adapter, CCK_index); + + if (rf == 2) { + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; + X = Adapter->pshare->RegEB4; + Y = Adapter->pshare->RegEBC; + + if (X != 0) { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XDTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(28), value32); + + } else { + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); + PHY_SetBBReg(Adapter, REG_BB_OFDM0_XDTXAFE_N, BIT_MASK_SET_MASKH4BITS_COMMON, 0x00); + PHY_SetBBReg(Adapter, REG_BB_OFDM0_ECCATHRESHOLD_N, BIT(28), 0x00); + } + + } + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XATXIQIMBALANC_N, BIT_MASK_SET_MASKDWORD_COMMON))); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg_88XX(Adapter, REG_BB_OFDM0_XBTXIQIMBALANCE_N, BIT_MASK_SET_MASKDWORD_COMMON))); + set_CCK_swing_index_88XX(Adapter, CCK_index); + + if (delta > 3) { +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_BACKGROUND) && !(OPMODE & WIFI_MP_CTX_PACKET)) + printk("NOT do IQK during ctx !!!! \n"); + else + PHY_IQCalibrate_8192E(&(priv->pshare->_dmODM), false); + } else +#endif + PHY_IQCalibrate_8192E(&(priv->pshare->_dmODM), false); + } + } else { + // TODO 5G setting + } + + //update thermal meter value + HAL_VAR_THERMALVALUE = ThermalValue; + for (i = 0 ; i < rf ; i++) + HAL_VAR_OFDM_INDEX(i) = OFDM_index[i]; + HAL_VAR_CCK_INDEX = CCK_index; + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + } +} + + +void +set_CCK_swing_index_88XX( + IN HAL_PADAPTER Adapter, + IN s2Byte CCK_index +) +{ + u2Byte channel; + +#if CFG_HAL_DISABLE_BB_RF + return; +#endif //CFG_HAL_DISABLE_BB_RF + +#ifdef CFG_HAL_MP_TEST + if ((HAL_OPMODE & WIFI_MP_STATE) || HAL_VAR_MP_SPECIFIC) + channel = HAL_VAR_WORKING_CHANNEL; + else +#endif + channel = HAL_VAR_DOT11CHANNEL; + + if (channel != 14) { + HAL_RTL_W8( 0xa22, CCKSwingTable_Ch1_Ch13_92E[CCK_index][0]); + HAL_RTL_W8( 0xa23, CCKSwingTable_Ch1_Ch13_92E[CCK_index][1]); + HAL_RTL_W8( 0xa24, CCKSwingTable_Ch1_Ch13_92E[CCK_index][2]); + HAL_RTL_W8( 0xa25, CCKSwingTable_Ch1_Ch13_92E[CCK_index][3]); + HAL_RTL_W8( 0xa26, CCKSwingTable_Ch1_Ch13_92E[CCK_index][4]); + HAL_RTL_W8( 0xa27, CCKSwingTable_Ch1_Ch13_92E[CCK_index][5]); + HAL_RTL_W8( 0xa28, CCKSwingTable_Ch1_Ch13_92E[CCK_index][6]); + HAL_RTL_W8( 0xa29, CCKSwingTable_Ch1_Ch13_92E[CCK_index][7]); + } else { + HAL_RTL_W8( 0xa22, CCKSwingTable_Ch14_92E[CCK_index][0]); + HAL_RTL_W8( 0xa23, CCKSwingTable_Ch14_92E[CCK_index][1]); + HAL_RTL_W8( 0xa24, CCKSwingTable_Ch14_92E[CCK_index][2]); + HAL_RTL_W8( 0xa25, CCKSwingTable_Ch14_92E[CCK_index][3]); + HAL_RTL_W8( 0xa26, CCKSwingTable_Ch14_92E[CCK_index][4]); + HAL_RTL_W8( 0xa27, CCKSwingTable_Ch14_92E[CCK_index][5]); + HAL_RTL_W8( 0xa28, CCKSwingTable_Ch14_92E[CCK_index][6]); + HAL_RTL_W8( 0xa29, CCKSwingTable_Ch14_92E[CCK_index][7]); + } + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("0xa22 ~ 0xa29 = {0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x,}\n", + HAL_RTL_R8(0xa22), + HAL_RTL_R8(0xa23), + HAL_RTL_R8(0xa24), + HAL_RTL_R8(0xa25), + HAL_RTL_R8(0xa26), + HAL_RTL_R8(0xa27), + HAL_RTL_R8(0xa28), + HAL_RTL_R8(0xa29) + )); +} + + +s4Byte +get_tx_tracking_index_88XX( + IN HAL_PADAPTER Adapter, + IN s4Byte channel, + IN s4Byte i, + IN s4Byte delta, + IN s4Byte is_decrease, + IN s4Byte is_CCK +) +{ + s4Byte index = 0; + + if (delta == 0) + return 0; + + if (delta > index_mapping_NUM_MAX) + delta = index_mapping_NUM_MAX; + + //printk("\n_eric_tracking +++ channel = %d, i = %d, delta = %d, is_decrease = %d, is_CCK = %d\n", channel, i, delta, is_decrease, is_CCK); + + // note, we transfer the table + // + delta = delta - 1; + + if (channel > 14) { + if (channel <= 99) { + index = HAL_VAR_TXPWR_TRACKING_5GL(((i * 2) + is_decrease), delta); + } else if (channel <= 140) { + index = HAL_VAR_TXPWR_TRACKING_5GM(((i * 2) + is_decrease), delta); + } else { + index = HAL_VAR_TXPWR_TRACKING_5GH(((i * 2) + is_decrease), delta); + } + } else { + if (is_CCK) { + index = HAL_VAR_TXPWR_TRACKING_2G_CCK(((i * 2) + is_decrease), delta); + } else { + index = HAL_VAR_TXPWR_TRACKING_2G_OFDM(((i * 2) + is_decrease), delta); + } + } + + //printk("check Table index = %d\n", index); + + return index; + +} +#endif +#endif //#if IS_RTL88XX_N + + +u4Byte +phy_CalculateBitShift_88XX( + IN u4Byte BitMask) +{ + u4Byte i; + + for (i = 0; i <= 31; i++) { + if (((BitMask >> i) & 0x1) == 1) + break; + } + + return (i); +} + + + +u4Byte +PHY_QueryBBReg_88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + u4Byte ReturnValue = 0; + u4Byte OriginalValue; + u4Byte BitShift; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + + OriginalValue = HAL_RTL_R32(RegAddr); + BitShift = phy_CalculateBitShift_88XX(BitMask); + ReturnValue = (OriginalValue & BitMask) >> BitShift; + + return (ReturnValue); +} + + +void +PHY_SetBBReg_88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +) +{ + u4Byte OriginalValue, BitShift, NewValue; + +#if CFG_HAL_DISABLE_BB_RF + return; +#endif //CFG_HAL_DISABLE_BB_RF + + if (BitMask != BIT_MASK_SET_MASKDWORD_COMMON) { + //if not "double word" write + + OriginalValue = HAL_RTL_R32(RegAddr); + BitShift = phy_CalculateBitShift_88XX(BitMask); + NewValue = ((OriginalValue & (~BitMask)) | (Data << BitShift)); + HAL_RTL_W32(RegAddr, NewValue); + } else + HAL_RTL_W32(RegAddr, Data); + +} + + +#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) +BOOLEAN +IsBBRegRange88XX +( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr +) +{ + if ((RegAddr >= 0x800) && (RegAddr <= 0xFFF)) { + return _TRUE; + } else { + return _FALSE; + } +} +#endif //(IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) + +#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) +BOOLEAN +IsBBRegRange88XX_V1 +( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr +) +{ + if (((RegAddr >= 0x800) && (RegAddr <= 0xFFF)) || + ((RegAddr >= 0x1800) && (RegAddr <= 0x1FFF)) ) { + return _TRUE; + } else { + return _FALSE; + } +} +#endif //(IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) + + + + + + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.h old mode 100755 new mode 100644 index da727b76534..0bd9feec288 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPhyCfg.h @@ -1,367 +1,367 @@ -#ifndef __HAL88XXPHYCFG_H__ -#define __HAL88XXPHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXPhyCfg.h - -Abstract: - Defined HAL 88XX PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ - - - -typedef enum _RF88XX_RADIO_PATH_ { - RF88XX_PATH_A = 0, //Radio Path A - RF88XX_PATH_B = 1, //Radio Path B -#if defined(CONFIG_WLAN_HAL_8814AE) - RF88XX_PATH_C = 2, //Radio Path C - RF88XX_PATH_D = 3, //Radio Path D -#endif - RF88XX_PATH_MAX //Max RF number -} RFRF88XX_RADIO_PATH_E, *PRFRF88XX_RADIO_PATH_E; - -typedef enum _BAND_TYPE{ - RF88XX_BAND_ON_2_4G = 0, - RF88XX_BAND_ON_5G, - RF88XX_BAND_ON_BOTH, - RF88XX_BANDMAX -}RF88XX_BAND_TYPE,*PRF88XX_BAND_TYPE; - -typedef enum _RF88XX_HT_CHANNEL_WIDTH { - RF88XX_HT_CHANNEL_WIDTH_20 = 0, - RF88XX_HT_CHANNEL_WIDTH_20_40 = 1, - RF88XX_HT_CHANNEL_WIDTH_80 = 2, - RF88XX_HT_CHANNEL_WIDTH_160 = 3, - RF88XX_HT_CHANNEL_WIDTH_10 = 4 -}RF88XX_HT_CHANNEL_WIDTH,*PRF88XXHT_CHANNEL_WIDTH; - -typedef enum _RF88XX_HT_CHANNEL_WIDTH_AC { - RF88XX_HT_CHANNEL_WIDTH_AC_20 = 0, - RF88XX_HT_CHANNEL_WIDTH_AC_40 = 1, - RF88XX_HT_CHANNEL_WIDTH_AC_80 = 2, - RF88XX_HT_CHANNEL_WIDTH_AC_160 = 3, - RF88XX_HT_CHANNEL_WIDTH_AC_10 = 4, - RF88XX_HT_CHANNEL_WIDTH_AC_5 = 5 -}RF88XX_HT_CHANNEL_WIDTH_AC,*PRF88XX_HT_CHANNEL_WIDTH_AC; - - -u4Byte -phy_CalculateBitShift_88XX( - IN u4Byte BitMask -); - -#if IS_RTL88XX_N -void -phy_RFSerialWrite_88XX_N( - IN HAL_PADAPTER Adapter, - IN RFRF88XX_RADIO_PATH_E eRFPath, - IN u4Byte Offset, - IN u4Byte Data -); -#endif - - -u4Byte -PHY_QueryBBReg_88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -void -PHY_SetBBReg_88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -); - -void -PHY_SetRFReg_88XX_AC -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -); - -u4Byte -PHY_QueryRFReg_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -void -SwBWMode88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -); - - -void -SetChannelPara88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte channel, - IN s4Byte offset -); - -void -CheckBand88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte RequestChannel -); - -void -phy_ADC_CLK_8814A( - IN HAL_PADAPTER Adapter -); - -void SwitchWirelessBand88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte RequestChannel, - IN u1Byte Band -); - - -void UpdateBBRFVal88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel, - IN s4Byte offset -); - - -RT_STATUS -PHYSetCCKTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -); - -RT_STATUS -PHYSetOFDMTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -); - - -void -CalOFDMTxPower5G_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte ch_idx -); - -void -CalOFDMTxPower2G_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u1Byte ch_idx -); - -s1Byte -convert_diff_88XX_AC( - IN s1Byte value -); - -void -Write_1S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -); - - -void -Write_2S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -); - -void -Write_3S_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -); - -#if 0 -void -Write_1S_A_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); - -void -Write_2S_A_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); - -void -Write_1S_B_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); - -void -Write_2S_B_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); - -#endif - -void -Write_OFDM_X_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal, - IN u1Byte bPathXEnIdx -); - -#if 0 -void -Write_OFDM_A_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); - -void -Write_OFDM_B_88XX_AC( - IN HAL_PADAPTER Adapter, - IN u4Byte writeVal -); -#endif - -void -use_DefaultOFDMTxPowerPathX88XX_AC( - IN HAL_PADAPTER Adapter, - IN pu1Byte bPathXEn -); - -#if 0 -void -use_DefaultOFDMTxPowerPathA88XX_AC( - IN HAL_PADAPTER Adapter -); - -void -use_DefaultOFDMTxPowerPathB88XX_AC( - IN HAL_PADAPTER Adapter -); -#endif - -RT_STATUS PHYSetOFDMTxPower88XX_N( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -); - -RT_STATUS PHYSetCCKTxPower88XX_N( - IN HAL_PADAPTER Adapter, - IN u1Byte channel -); - -void -SwBWMode88XX_N( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -); - -void -PHY_SetRFReg_88XX_N -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -); - -u4Byte -PHY_QueryRFReg_88XX_N -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -#if 0 -s4Byte -get_tx_tracking_index_88XX( - IN HAL_PADAPTER Adapter, - IN s4Byte channel, - IN s4Byte i, - IN s4Byte delta, - IN s4Byte is_decrease, - IN s4Byte is_CCK -); - - -void -set_CCK_swing_index_88XX( - IN HAL_PADAPTER Adapter, - IN s2Byte CCK_index -); - -void TXPowerTracking_ThermalMeter_88XX -( - IN HAL_PADAPTER Adapter -); -#endif - -void -PHYSetTxPower88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte txRateStart, - IN u1Byte txRateEnd, - IN u1Byte txPathIdx, - IN u1Byte defPower -); - -RT_STATUS -AddTxPower88XX_AC( - IN HAL_PADAPTER Adapter, - IN s1Byte index -); -#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) -BOOLEAN -IsBBRegRange88XX -( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr -); -#endif //#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) - - -#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) -BOOLEAN -IsBBRegRange88XX_V1 -( - IN HAL_PADAPTER Adapter, - IN u4Byte RegAddr -); -#endif //#if (IS_RTL8814A_SERIES) - -#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) -void -SetCurrentTxAGC( - IN HAL_PADAPTER Adapter, - IN u1Byte txPathIdx, - IN u1Byte txRate, - IN u1Byte power -); -#endif - -#endif // #ifndef __HAL88XXPHYCFG_H__ - +#ifndef __HAL88XXPHYCFG_H__ +#define __HAL88XXPHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXPhyCfg.h + +Abstract: + Defined HAL 88XX PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ + + + +typedef enum _RF88XX_RADIO_PATH_ { + RF88XX_PATH_A = 0, //Radio Path A + RF88XX_PATH_B = 1, //Radio Path B +#if defined(CONFIG_WLAN_HAL_8814AE) + RF88XX_PATH_C = 2, //Radio Path C + RF88XX_PATH_D = 3, //Radio Path D +#endif + RF88XX_PATH_MAX //Max RF number +} RFRF88XX_RADIO_PATH_E, *PRFRF88XX_RADIO_PATH_E; + +typedef enum _BAND_TYPE{ + RF88XX_BAND_ON_2_4G = 0, + RF88XX_BAND_ON_5G, + RF88XX_BAND_ON_BOTH, + RF88XX_BANDMAX +}RF88XX_BAND_TYPE,*PRF88XX_BAND_TYPE; + +typedef enum _RF88XX_HT_CHANNEL_WIDTH { + RF88XX_HT_CHANNEL_WIDTH_20 = 0, + RF88XX_HT_CHANNEL_WIDTH_20_40 = 1, + RF88XX_HT_CHANNEL_WIDTH_80 = 2, + RF88XX_HT_CHANNEL_WIDTH_160 = 3, + RF88XX_HT_CHANNEL_WIDTH_10 = 4 +}RF88XX_HT_CHANNEL_WIDTH,*PRF88XXHT_CHANNEL_WIDTH; + +typedef enum _RF88XX_HT_CHANNEL_WIDTH_AC { + RF88XX_HT_CHANNEL_WIDTH_AC_20 = 0, + RF88XX_HT_CHANNEL_WIDTH_AC_40 = 1, + RF88XX_HT_CHANNEL_WIDTH_AC_80 = 2, + RF88XX_HT_CHANNEL_WIDTH_AC_160 = 3, + RF88XX_HT_CHANNEL_WIDTH_AC_10 = 4, + RF88XX_HT_CHANNEL_WIDTH_AC_5 = 5 +}RF88XX_HT_CHANNEL_WIDTH_AC,*PRF88XX_HT_CHANNEL_WIDTH_AC; + + +u4Byte +phy_CalculateBitShift_88XX( + IN u4Byte BitMask +); + +#if IS_RTL88XX_N +void +phy_RFSerialWrite_88XX_N( + IN HAL_PADAPTER Adapter, + IN RFRF88XX_RADIO_PATH_E eRFPath, + IN u4Byte Offset, + IN u4Byte Data +); +#endif + + +u4Byte +PHY_QueryBBReg_88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +void +PHY_SetBBReg_88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +); + +void +PHY_SetRFReg_88XX_AC +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +); + +u4Byte +PHY_QueryRFReg_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +void +SwBWMode88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +); + + +void +SetChannelPara88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte channel, + IN s4Byte offset +); + +void +CheckBand88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte RequestChannel +); + +void +phy_ADC_CLK_8814A( + IN HAL_PADAPTER Adapter +); + +void SwitchWirelessBand88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte RequestChannel, + IN u1Byte Band +); + + +void UpdateBBRFVal88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel, + IN s4Byte offset +); + + +RT_STATUS +PHYSetCCKTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +); + +RT_STATUS +PHYSetOFDMTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +); + + +void +CalOFDMTxPower5G_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte ch_idx +); + +void +CalOFDMTxPower2G_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u1Byte ch_idx +); + +s1Byte +convert_diff_88XX_AC( + IN s1Byte value +); + +void +Write_1S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +); + + +void +Write_2S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +); + +void +Write_3S_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +); + +#if 0 +void +Write_1S_A_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); + +void +Write_2S_A_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); + +void +Write_1S_B_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); + +void +Write_2S_B_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); + +#endif + +void +Write_OFDM_X_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal, + IN u1Byte bPathXEnIdx +); + +#if 0 +void +Write_OFDM_A_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); + +void +Write_OFDM_B_88XX_AC( + IN HAL_PADAPTER Adapter, + IN u4Byte writeVal +); +#endif + +void +use_DefaultOFDMTxPowerPathX88XX_AC( + IN HAL_PADAPTER Adapter, + IN pu1Byte bPathXEn +); + +#if 0 +void +use_DefaultOFDMTxPowerPathA88XX_AC( + IN HAL_PADAPTER Adapter +); + +void +use_DefaultOFDMTxPowerPathB88XX_AC( + IN HAL_PADAPTER Adapter +); +#endif + +RT_STATUS PHYSetOFDMTxPower88XX_N( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +); + +RT_STATUS PHYSetCCKTxPower88XX_N( + IN HAL_PADAPTER Adapter, + IN u1Byte channel +); + +void +SwBWMode88XX_N( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +); + +void +PHY_SetRFReg_88XX_N +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +); + +u4Byte +PHY_QueryRFReg_88XX_N +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +#if 0 +s4Byte +get_tx_tracking_index_88XX( + IN HAL_PADAPTER Adapter, + IN s4Byte channel, + IN s4Byte i, + IN s4Byte delta, + IN s4Byte is_decrease, + IN s4Byte is_CCK +); + + +void +set_CCK_swing_index_88XX( + IN HAL_PADAPTER Adapter, + IN s2Byte CCK_index +); + +void TXPowerTracking_ThermalMeter_88XX +( + IN HAL_PADAPTER Adapter +); +#endif + +void +PHYSetTxPower88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte txRateStart, + IN u1Byte txRateEnd, + IN u1Byte txPathIdx, + IN u1Byte defPower +); + +RT_STATUS +AddTxPower88XX_AC( + IN HAL_PADAPTER Adapter, + IN s1Byte index +); +#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) +BOOLEAN +IsBBRegRange88XX +( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr +); +#endif //#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES) + + +#if (IS_RTL8814A_SERIES || IS_RTL8197F_SERIES || IS_RTL8822B_SERIES) +BOOLEAN +IsBBRegRange88XX_V1 +( + IN HAL_PADAPTER Adapter, + IN u4Byte RegAddr +); +#endif //#if (IS_RTL8814A_SERIES) + +#if (IS_RTL8814A_SERIES || IS_RTL8822B_SERIES) +void +SetCurrentTxAGC( + IN HAL_PADAPTER Adapter, + IN u1Byte txPathIdx, + IN u1Byte txRate, + IN u1Byte power +); +#endif + +#endif // #ifndef __HAL88XXPHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h old mode 100755 new mode 100644 index 5d5470968ea..59626521fd7 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h @@ -1,132 +1,132 @@ -#ifndef __HAL88XX_PWRSEQCMD_H__ -#define __HAL88XX_PWRSEQCMD_H__ - - /*++ - Copyright (c) Realtek Semiconductor Corp. All rights reserved. - - Module Name: - Hal88XXPwrSeqCmd.h - - Abstract: - Defined HAL 88XX Power Sequence Command - - Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-04-03 Filen Create. - --*/ - -#if 0 - /*---------------------------------------------*/ -//3 The value of cmd: 4 bits -/*---------------------------------------------*/ -#define PWR_CMD_READ 0x00 - // offset: the read register offset - // msk: the mask of the read value - // value: N/A, left by 0 - // note: dirver shall implement this function by read & msk -#define PWR_CMD_WRITE 0x01 - // offset: the read register offset - // msk: the mask of the write bits - // value: write value - // note: driver shall implement this cmd by read & msk after write -#define PWR_CMD_POLLING 0x02 - // offset: the read register offset - // msk: the mask of the polled value - // value: the value to be polled, masked by the msd field. - // note: driver shall implement this cmd by - // do{ - // if( (Read(offset) & msk) == (value & msk) ) - // break; - // } while(not timeout); -#define PWR_CMD_DELAY 0x03 - // offset: the value to delay - // msk: N/A - // value: the unit of delay, 0: us, 1: ms -#define PWR_CMD_END 0x04 - // offset: N/A - // msk: N/A - // value: N/A - -/*---------------------------------------------*/ -//3 The value of base: 4 bits -/*---------------------------------------------*/ - // define the base address of each block -#define PWR_BASEADDR_MAC 0x00 -#define PWR_BASEADDR_USB 0x01 -#define PWR_BASEADDR_PCIE 0x02 -#define PWR_BASEADDR_SDIO 0x03 - -/*---------------------------------------------*/ -//3 The value of interface_msk: 4 bits -/*---------------------------------------------*/ -#define PWR_INTF_SDIO_MSK BIT(0) -#define PWR_INTF_USB_MSK BIT(1) -#define PWR_INTF_PCI_MSK BIT(2) -#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -//3 The value of fab_msk: 4 bits -/*---------------------------------------------*/ -#define PWR_FAB_TSMC_MSK BIT(0) -#define PWR_FAB_UMC_MSK BIT(1) -#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/*---------------------------------------------*/ -//3The value of cut_msk: 8 bits -/*---------------------------------------------*/ -#define PWR_CUT_TESTCHIP_MSK BIT(0) -#define PWR_CUT_A_MSK BIT(1) -#define PWR_CUT_B_MSK BIT(2) -#define PWR_CUT_C_MSK BIT(3) -#define PWR_CUT_D_MSK BIT(4) -#define PWR_CUT_E_MSK BIT(5) -#define PWR_CUT_F_MSK BIT(6) -#define PWR_CUT_G_MSK BIT(7) -#define PWR_CUT_ALL_MSK 0xFF - - -typedef enum _PWRSEQ_CMD_DELAY_UNIT_ -{ - PWRSEQ_DELAY_US, - PWRSEQ_DELAY_MS, -} PWRSEQ_DELAY_UNIT; - -typedef struct _WL_PWR_CFG_ -{ - unsigned short offset; - unsigned char cut_msk; - unsigned char fab_msk:4; - unsigned char interface_msk:4; - unsigned char base:4; - unsigned char cmd:4; - unsigned char msk; - unsigned char value; -} WLAN_PWR_CFG, *PWLAN_PWR_CFG; - - -#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset -#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk -#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk -#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk -#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base -#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd -#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk -#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value - -#else -#include "../../HalPwrSeqCmd.h" -#endif - -BOOLEAN -HalPwrSeqCmdParsing88XX( - IN HAL_PADAPTER Adapter, - IN u1Byte CutVersion, - IN u1Byte FabVersion, - IN u1Byte InterfaceType, - IN WLAN_PWR_CFG PwrSeqCmd[] -); - - -#endif //#define __HAL88XX_PWRSEQCMD_H__ - +#ifndef __HAL88XX_PWRSEQCMD_H__ +#define __HAL88XX_PWRSEQCMD_H__ + + /*++ + Copyright (c) Realtek Semiconductor Corp. All rights reserved. + + Module Name: + Hal88XXPwrSeqCmd.h + + Abstract: + Defined HAL 88XX Power Sequence Command + + Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-04-03 Filen Create. + --*/ + +#if 0 + /*---------------------------------------------*/ +//3 The value of cmd: 4 bits +/*---------------------------------------------*/ +#define PWR_CMD_READ 0x00 + // offset: the read register offset + // msk: the mask of the read value + // value: N/A, left by 0 + // note: dirver shall implement this function by read & msk +#define PWR_CMD_WRITE 0x01 + // offset: the read register offset + // msk: the mask of the write bits + // value: write value + // note: driver shall implement this cmd by read & msk after write +#define PWR_CMD_POLLING 0x02 + // offset: the read register offset + // msk: the mask of the polled value + // value: the value to be polled, masked by the msd field. + // note: driver shall implement this cmd by + // do{ + // if( (Read(offset) & msk) == (value & msk) ) + // break; + // } while(not timeout); +#define PWR_CMD_DELAY 0x03 + // offset: the value to delay + // msk: N/A + // value: the unit of delay, 0: us, 1: ms +#define PWR_CMD_END 0x04 + // offset: N/A + // msk: N/A + // value: N/A + +/*---------------------------------------------*/ +//3 The value of base: 4 bits +/*---------------------------------------------*/ + // define the base address of each block +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +//3 The value of interface_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of fab_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3The value of cut_msk: 8 bits +/*---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ +{ + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ +{ + unsigned short offset; + unsigned char cut_msk; + unsigned char fab_msk:4; + unsigned char interface_msk:4; + unsigned char base:4; + unsigned char cmd:4; + unsigned char msk; + unsigned char value; +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + +#else +#include "../../HalPwrSeqCmd.h" +#endif + +BOOLEAN +HalPwrSeqCmdParsing88XX( + IN HAL_PADAPTER Adapter, + IN u1Byte CutVersion, + IN u1Byte FabVersion, + IN u1Byte InterfaceType, + IN WLAN_PWR_CFG PwrSeqCmd[] +); + + +#endif //#define __HAL88XX_PWRSEQCMD_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXReg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXReg.h old mode 100755 new mode 100644 index 2920962532f..2eaebd4a1f7 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXReg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXReg.h @@ -1,25 +1,25 @@ -#ifndef __RTL88XX_REG_H__ -#define __RTL88XX_REG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88XXReg.h - -Abstract: - Defined RTL88XX Register Offset & Marco & Bit define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. - 2012-03-29 Lun-Wu Yeh Add Tx/Rx Desc Reg ---*/ - -/*--------------------------Define -------------------------------------------*/ - - - -#endif //__RTL88XX_REG_H__ - +#ifndef __RTL88XX_REG_H__ +#define __RTL88XX_REG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88XXReg.h + +Abstract: + Defined RTL88XX Register Offset & Marco & Bit define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. + 2012-03-29 Lun-Wu Yeh Add Tx/Rx Desc Reg +--*/ + +/*--------------------------Define -------------------------------------------*/ + + + +#endif //__RTL88XX_REG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.h old mode 100755 new mode 100644 index 76cf83858f3..ce3d748de14 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXRxDesc.h @@ -1,177 +1,177 @@ -#ifndef __HAL88XXRXDESC_H__ -#define __HAL88XXRXDESC_H__ - -#if defined(_PC_) || defined(_PUMA6_) -#ifdef FS -#undef FS -#endif -#endif - -typedef struct _RX_DESC_88XX_ -{ - volatile u4Byte Dword0; - volatile u4Byte Dword1; - volatile u4Byte Dword2; - volatile u4Byte Dword3; - volatile u4Byte Dword4; - volatile u4Byte Dword5; -} RX_DESC_88XX, *PRX_DESC_88XX; - -#define SIZE_RXDESC_88XX 24 - -typedef enum _HCI_RX_DMA_QUEUE_88XX_ -{ - HCI_RX_DMA_QUEUE_Q0 = 0, - HCI_RX_DMA_QUEUE_MAX_NUM -} HCI_RX_DMA_QUEUE_88XX, *PHCI_RX_DMA_QUEUE_88XX; - -typedef struct _RX_BUFFER_DESCRIPTOR_ -{ - u4Byte Dword0; - u4Byte Dword1; -#if TXBD_SEG_32_64_SEL - u4Byte Dword2; - u4Byte Dword3; -#endif -} RX_BUFFER_DESCRIPTOR, *PRX_BUFFER_DESCRIPTOR; - -typedef struct _HCI_RX_DMA_QUEUE_STRUCT_88XX_ -{ - PRX_BUFFER_DESCRIPTOR pRXBD_head; -#ifdef CONFIG_NET_PCI - unsigned long rxbd_dma_addr; -#endif - - u2Byte hw_idx; //Mapping to HW register - u2Byte host_idx; //Mapping to HW register - //Special case: - // If we can't allocate a new SKB(RXDESC+Payload) to mapping RXBD, - // we still need to maintain a pointer in order to recieve RxPkt continuously - u2Byte cur_host_idx; // the index to indicate the next location that we have received RxPkt - -#if CFG_HAL_DELAY_REFILL_RX_BUF - u2Byte rxbd_ok_cnt; -#endif - - u2Byte total_rxbd_num; - u2Byte avail_rxbd_num; - u4Byte reg_rwptr_idx; -#if RXBD_READY_CHECK_METHOD - // reset signal from 0x100[1], CR[HCI_RXDMA_EN] - u2Byte rxtag_seq_num; -#endif -} HCI_RX_DMA_QUEUE_STRUCT_88XX, *PHCI_RX_DMA_QUEUE_STRUCT_88XX; - -typedef struct _HCI_RX_DMA_MANAGER_88XX_ -{ - HCI_RX_DMA_QUEUE_STRUCT_88XX rx_queue[HCI_RX_DMA_QUEUE_MAX_NUM]; -} HCI_RX_DMA_MANAGER_88XX, *PHCI_RX_DMA_MANAGER_88XX; - -typedef struct _RX_DESC_STATUS_88XX_ -{ - // RXBD - BOOLEAN FS; - BOOLEAN LS; - u2Byte RXBuffSize; - -#if CFG_HAL_DBG - u2Byte remaining_pkt_len; - u4Byte pktBufAddr[32]; - u2Byte pktBufLen[32]; - u2Byte pktNum; -#endif - - //4 Note: value below Only valid in FS=1 - // Dword0 - u2Byte PKT_LEN; - BOOLEAN CRC32; - BOOLEAN ICVERR; - u1Byte DRV_INFO_SIZE; - u1Byte SECURITY; - u1Byte SHIFT; - BOOLEAN PHYST; - BOOLEAN SWDEC; - BOOLEAN EOR; - - // Dword 1 - BOOLEAN PAGGR; - - // Dword 2 - BOOLEAN C2HPkt; - BOOLEAN FCS_OK; - - // Dowrd 3 - u1Byte RX_RATE; - - // Dword 4 - BOOLEAN OFDM_SGI; - BOOLEAN CCK_SPLCP; - BOOLEAN LDPC; - BOOLEAN STBC; - BOOLEAN NOT_SOUNDING; - u1Byte BW; -#if CFG_HAL_HW_FILL_MACID - u1Byte rxMACID; -#endif -} RX_DESC_STATUS_88XX, *PRX_DESC_STATUS_88XX; - -HAL_IMEM -RT_STATUS -QueryRxDesc88XX ( - IN HAL_PADAPTER Adapter, - IN u4Byte queueIndex, - IN pu1Byte pBufAddr, - OUT PVOID pRxDescStatus -); - -RT_STATUS -QueryRxDesc88XX_V1 ( - IN HAL_PADAPTER Adapter, - IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX - IN pu1Byte pBufAddr, - OUT PVOID pRxDescStatus -); -HAL_IMEM -RT_STATUS -UpdateRXBDInfo88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX - IN u2Byte rxbd_idx, - IN pu1Byte pBuf, - IN PVOID Callback, // callback function - IN BOOLEAN bInit -); - -HAL_IMEM -u2Byte -UpdateRXBDHWIdx88XX( - IN HAL_PADAPTER Adapter, - IN u4Byte queueIndex -); - -HAL_IMEM -VOID -UpdateRXBDHostIdx88XX ( - IN HAL_PADAPTER Adapter, - IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX - IN u4Byte Count -); - -RT_STATUS -PrepareRXBD88XX( - IN HAL_PADAPTER Adapter, - IN u2Byte bufferLen, - IN PVOID Callback // callback function -); - -void DumpRxBDesc88XX( - IN HAL_PADAPTER Adapter, -#ifdef CONFIG_RTL_PROC_NEW - IN struct seq_file *s, -#endif - IN u4Byte q_num -); - -#endif //#ifndef __HAL88XXRXDESC_H__ - - +#ifndef __HAL88XXRXDESC_H__ +#define __HAL88XXRXDESC_H__ + +#if defined(_PC_) || defined(_PUMA6_) +#ifdef FS +#undef FS +#endif +#endif + +typedef struct _RX_DESC_88XX_ +{ + volatile u4Byte Dword0; + volatile u4Byte Dword1; + volatile u4Byte Dword2; + volatile u4Byte Dword3; + volatile u4Byte Dword4; + volatile u4Byte Dword5; +} RX_DESC_88XX, *PRX_DESC_88XX; + +#define SIZE_RXDESC_88XX 24 + +typedef enum _HCI_RX_DMA_QUEUE_88XX_ +{ + HCI_RX_DMA_QUEUE_Q0 = 0, + HCI_RX_DMA_QUEUE_MAX_NUM +} HCI_RX_DMA_QUEUE_88XX, *PHCI_RX_DMA_QUEUE_88XX; + +typedef struct _RX_BUFFER_DESCRIPTOR_ +{ + u4Byte Dword0; + u4Byte Dword1; +#if TXBD_SEG_32_64_SEL + u4Byte Dword2; + u4Byte Dword3; +#endif +} RX_BUFFER_DESCRIPTOR, *PRX_BUFFER_DESCRIPTOR; + +typedef struct _HCI_RX_DMA_QUEUE_STRUCT_88XX_ +{ + PRX_BUFFER_DESCRIPTOR pRXBD_head; +#ifdef CONFIG_NET_PCI + unsigned long rxbd_dma_addr; +#endif + + u2Byte hw_idx; //Mapping to HW register + u2Byte host_idx; //Mapping to HW register + //Special case: + // If we can't allocate a new SKB(RXDESC+Payload) to mapping RXBD, + // we still need to maintain a pointer in order to recieve RxPkt continuously + u2Byte cur_host_idx; // the index to indicate the next location that we have received RxPkt + +#if CFG_HAL_DELAY_REFILL_RX_BUF + u2Byte rxbd_ok_cnt; +#endif + + u2Byte total_rxbd_num; + u2Byte avail_rxbd_num; + u4Byte reg_rwptr_idx; +#if RXBD_READY_CHECK_METHOD + // reset signal from 0x100[1], CR[HCI_RXDMA_EN] + u2Byte rxtag_seq_num; +#endif +} HCI_RX_DMA_QUEUE_STRUCT_88XX, *PHCI_RX_DMA_QUEUE_STRUCT_88XX; + +typedef struct _HCI_RX_DMA_MANAGER_88XX_ +{ + HCI_RX_DMA_QUEUE_STRUCT_88XX rx_queue[HCI_RX_DMA_QUEUE_MAX_NUM]; +} HCI_RX_DMA_MANAGER_88XX, *PHCI_RX_DMA_MANAGER_88XX; + +typedef struct _RX_DESC_STATUS_88XX_ +{ + // RXBD + BOOLEAN FS; + BOOLEAN LS; + u2Byte RXBuffSize; + +#if CFG_HAL_DBG + u2Byte remaining_pkt_len; + u4Byte pktBufAddr[32]; + u2Byte pktBufLen[32]; + u2Byte pktNum; +#endif + + //4 Note: value below Only valid in FS=1 + // Dword0 + u2Byte PKT_LEN; + BOOLEAN CRC32; + BOOLEAN ICVERR; + u1Byte DRV_INFO_SIZE; + u1Byte SECURITY; + u1Byte SHIFT; + BOOLEAN PHYST; + BOOLEAN SWDEC; + BOOLEAN EOR; + + // Dword 1 + BOOLEAN PAGGR; + + // Dword 2 + BOOLEAN C2HPkt; + BOOLEAN FCS_OK; + + // Dowrd 3 + u1Byte RX_RATE; + + // Dword 4 + BOOLEAN OFDM_SGI; + BOOLEAN CCK_SPLCP; + BOOLEAN LDPC; + BOOLEAN STBC; + BOOLEAN NOT_SOUNDING; + u1Byte BW; +#if CFG_HAL_HW_FILL_MACID + u1Byte rxMACID; +#endif +} RX_DESC_STATUS_88XX, *PRX_DESC_STATUS_88XX; + +HAL_IMEM +RT_STATUS +QueryRxDesc88XX ( + IN HAL_PADAPTER Adapter, + IN u4Byte queueIndex, + IN pu1Byte pBufAddr, + OUT PVOID pRxDescStatus +); + +RT_STATUS +QueryRxDesc88XX_V1 ( + IN HAL_PADAPTER Adapter, + IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX + IN pu1Byte pBufAddr, + OUT PVOID pRxDescStatus +); +HAL_IMEM +RT_STATUS +UpdateRXBDInfo88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX + IN u2Byte rxbd_idx, + IN pu1Byte pBuf, + IN PVOID Callback, // callback function + IN BOOLEAN bInit +); + +HAL_IMEM +u2Byte +UpdateRXBDHWIdx88XX( + IN HAL_PADAPTER Adapter, + IN u4Byte queueIndex +); + +HAL_IMEM +VOID +UpdateRXBDHostIdx88XX ( + IN HAL_PADAPTER Adapter, + IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX + IN u4Byte Count +); + +RT_STATUS +PrepareRXBD88XX( + IN HAL_PADAPTER Adapter, + IN u2Byte bufferLen, + IN PVOID Callback // callback function +); + +void DumpRxBDesc88XX( + IN HAL_PADAPTER Adapter, +#ifdef CONFIG_RTL_PROC_NEW + IN struct seq_file *s, +#endif + IN u4Byte q_num +); + +#endif //#ifndef __HAL88XXRXDESC_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXTxDesc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/Hal88XXVerify.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h old mode 100755 new mode 100644 index 97e0f84c485..dbae6f997d2 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h @@ -1,139 +1,139 @@ -#ifndef __HAL8192E_DEF_H__ -#define __HAL8192E_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8192EDef.h - -Abstract: - Defined HAL 8192E data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-04-16 Filen Create. ---*/ - -extern u1Byte *data_AGC_TAB_8192E_start, *data_AGC_TAB_8192E_end; -extern u1Byte *data_MAC_REG_8192E_start, *data_MAC_REG_8192E_end; -extern u1Byte *data_PHY_REG_8192E_start, *data_PHY_REG_8192E_end; -//extern u1Byte *data_PHY_REG_1T_8192E_start, *data_PHY_REG_1T_8192E_end; -extern u1Byte *data_PHY_REG_MP_8192E_start, *data_PHY_REG_MP_8192E_end; -#ifdef TXPWR_LMT_92EE -extern u1Byte *data_PHY_REG_PG_8192E_new_start, *data_PHY_REG_PG_8192E_new_end; -#endif -extern u1Byte *data_PHY_REG_PG_8192E_start, *data_PHY_REG_PG_8192E_end; - - -extern u1Byte *data_RadioA_8192E_start, *data_RadioA_8192E_end; -extern u1Byte *data_RadioB_8192E_start, *data_RadioB_8192E_end; - -//High Power - -#if CFG_HAL_HIGH_POWER_EXT_PA -#ifdef PWR_BY_RATE_92E_HP -extern u1Byte *data_PHY_REG_PG_8192Emp_hp_start, *data_PHY_REG_PG_8192Emp_hp_end; -#endif -#if CFG_HAL_HIGH_POWER_EXT_LNA -extern u1Byte *data_AGC_TAB_8192E_hp_start, *data_AGC_TAB_8192E_hp_end; -extern u1Byte *data_PHY_REG_8192E_hp_start, *data_PHY_REG_8192E_hp_end; -extern u1Byte *data_RadioA_8192E_hp_start, *data_RadioA_8192E_hp_end; -extern u1Byte *data_RadioB_8192E_hp_start, *data_RadioB_8192E_hp_end; -#endif -extern u1Byte *data_AGC_TAB_8192E_extpa_start, *data_AGC_TAB_8192E_extpa_end; -extern u1Byte *data_PHY_REG_8192E_extpa_start, *data_PHY_REG_8192E_extpa_end; -extern u1Byte *data_RadioA_8192E_extpa_start, *data_RadioA_8192E_extpa_end; -extern u1Byte *data_RadioB_8192E_extpa_start, *data_RadioB_8192E_extpa_end; -#endif - -#if CFG_HAL_HIGH_POWER_EXT_LNA -#if IS_EXIST_PCI -extern u1Byte *data_AGC_TAB_8192E_extlna_start, *data_AGC_TAB_8192E_extlna_end; -extern u1Byte *data_AGC_TAB_8192E_extlna_type1_start, *data_AGC_TAB_8192E_extlna_type1_end; -extern u1Byte *data_AGC_TAB_8192E_extlna_type2_start, *data_AGC_TAB_8192E_extlna_type2_end; -extern u1Byte *data_AGC_TAB_8192E_extlna_type3_start, *data_AGC_TAB_8192E_extlna_type3_end; -extern u1Byte *data_PHY_REG_8192E_extlna_start, *data_PHY_REG_8192E_extlna_end; -extern u1Byte *data_RadioA_8192E_extlna_start, *data_RadioA_8192E_extlna_end; -extern u1Byte *data_RadioB_8192E_extlna_start, *data_RadioB_8192E_extlna_end; -#endif -#if IS_EXIST_SDIO -extern u1Byte *data_AGC_TAB_8192ES_extlna_start, *data_AGC_TAB_8192ES_extlna_end; -extern u1Byte *data_PHY_REG_8192ES_extlna_start, *data_PHY_REG_8192ES_extlna_end; -extern u1Byte *data_RadioA_8192ES_extlna_start, *data_RadioA_8192ES_extlna_end; -extern u1Byte *data_RadioB_8192ES_extlna_start, *data_RadioB_8192ES_extlna_end; -#endif -#endif - -// B-cut support -extern u1Byte *data_MAC_REG_8192Eb_start, *data_MAC_REG_8192Eb_end; -extern u1Byte *data_PHY_REG_8192Eb_start, *data_PHY_REG_8192Eb_end; -#if IS_EXIST_PCI -extern u1Byte *data_RadioA_8192Eb_start, *data_RadioA_8192Eb_end; -extern u1Byte *data_RadioB_8192Eb_start, *data_RadioB_8192Eb_end; -#endif - -// MP chip -#if IS_EXIST_PCI -extern u1Byte *data_AGC_TAB_8192Emp_start, *data_AGC_TAB_8192Emp_end; -extern u1Byte *data_RadioA_8192Emp_start, *data_RadioA_8192Emp_end; -extern u1Byte *data_RadioB_8192Emp_start, *data_RadioB_8192Emp_end; -extern u1Byte *data_RadioA_8192EmpA_start, *data_RadioA_8192EmpA_end; -extern u1Byte *data_RadioB_8192EmpA_start, *data_RadioB_8192EmpA_end; -#endif -#if IS_EXIST_SDIO -extern u1Byte *data_AGC_TAB_8192ES_start, *data_AGC_TAB_8192ES_end; -extern u1Byte *data_RadioA_8192ES_start, *data_RadioA_8192ES_end; -extern u1Byte *data_RadioB_8192ES_start, *data_RadioB_8192ES_end; -#endif -extern u1Byte *data_PHY_REG_MP_8192Emp_start, *data_PHY_REG_MP_8192Emp_end; -extern u1Byte *data_PHY_REG_PG_8192Emp_start, *data_PHY_REG_PG_8192Emp_end; -extern u1Byte *data_MAC_REG_8192Emp_start, *data_MAC_REG_8192Emp_end; -extern u1Byte *data_PHY_REG_8192Emp_start, *data_PHY_REG_8192Emp_end; - -// FW -#if IS_EXIST_PCI -extern u1Byte *data_rtl8192Efw_start, *data_rtl8192Efw_end; -extern u1Byte *data_rtl8192EfwMP_start, *data_rtl8192EfwMP_end; -#endif -#if IS_EXIST_SDIO -extern u1Byte *data_rtl8192ESfwMP_start, *data_rtl8192ESfwMP_end; -#endif - -// Power Tracking -extern u1Byte *data_TxPowerTrack_AP_start, *data_TxPowerTrack_AP_end; - -#ifdef TXPWR_LMT_92EE -extern unsigned char *data_TXPWR_LMT_92EE_new_start, *data_TXPWR_LMT_92EE_new_end; -#ifdef PWR_BY_RATE_92E_HP -#if CFG_HAL_HIGH_POWER_EXT_PA -extern unsigned char *data_TXPWR_LMT_92EE_hp_start, *data_TXPWR_LMT_92EE_hp_end; -#endif -#endif -#endif - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8192E_start, *data_MACDM_def_high_8192E_end; -extern u1Byte *data_MACDM_def_low_8192E_start, *data_MACDM_def_low_8192E_end; -extern u1Byte *data_MACDM_def_normal_8192E_start, *data_MACDM_def_normal_8192E_end; - -//general -extern u1Byte *data_MACDM_gen_high_8192E_start, *data_MACDM_gen_high_8192E_end; -extern u1Byte *data_MACDM_gen_low_8192E_start, *data_MACDM_gen_low_8192E_end; -extern u1Byte *data_MACDM_gen_normal_8192E_start, *data_MACDM_gen_normal_8192E_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8192E_start, *data_MACDM_txop_high_8192E_end; -extern u1Byte *data_MACDM_txop_low_8192E_start, *data_MACDM_txop_low_8192E_end; -extern u1Byte *data_MACDM_txop_normal_8192E_start, *data_MACDM_txop_normal_8192E_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8192E_start, *data_MACDM_state_criteria_8192E_end; - - - -#endif //__HAL8192E_DEF_H__ - - +#ifndef __HAL8192E_DEF_H__ +#define __HAL8192E_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192EDef.h + +Abstract: + Defined HAL 8192E data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-04-16 Filen Create. +--*/ + +extern u1Byte *data_AGC_TAB_8192E_start, *data_AGC_TAB_8192E_end; +extern u1Byte *data_MAC_REG_8192E_start, *data_MAC_REG_8192E_end; +extern u1Byte *data_PHY_REG_8192E_start, *data_PHY_REG_8192E_end; +//extern u1Byte *data_PHY_REG_1T_8192E_start, *data_PHY_REG_1T_8192E_end; +extern u1Byte *data_PHY_REG_MP_8192E_start, *data_PHY_REG_MP_8192E_end; +#ifdef TXPWR_LMT_92EE +extern u1Byte *data_PHY_REG_PG_8192E_new_start, *data_PHY_REG_PG_8192E_new_end; +#endif +extern u1Byte *data_PHY_REG_PG_8192E_start, *data_PHY_REG_PG_8192E_end; + + +extern u1Byte *data_RadioA_8192E_start, *data_RadioA_8192E_end; +extern u1Byte *data_RadioB_8192E_start, *data_RadioB_8192E_end; + +//High Power + +#if CFG_HAL_HIGH_POWER_EXT_PA +#ifdef PWR_BY_RATE_92E_HP +extern u1Byte *data_PHY_REG_PG_8192Emp_hp_start, *data_PHY_REG_PG_8192Emp_hp_end; +#endif +#if CFG_HAL_HIGH_POWER_EXT_LNA +extern u1Byte *data_AGC_TAB_8192E_hp_start, *data_AGC_TAB_8192E_hp_end; +extern u1Byte *data_PHY_REG_8192E_hp_start, *data_PHY_REG_8192E_hp_end; +extern u1Byte *data_RadioA_8192E_hp_start, *data_RadioA_8192E_hp_end; +extern u1Byte *data_RadioB_8192E_hp_start, *data_RadioB_8192E_hp_end; +#endif +extern u1Byte *data_AGC_TAB_8192E_extpa_start, *data_AGC_TAB_8192E_extpa_end; +extern u1Byte *data_PHY_REG_8192E_extpa_start, *data_PHY_REG_8192E_extpa_end; +extern u1Byte *data_RadioA_8192E_extpa_start, *data_RadioA_8192E_extpa_end; +extern u1Byte *data_RadioB_8192E_extpa_start, *data_RadioB_8192E_extpa_end; +#endif + +#if CFG_HAL_HIGH_POWER_EXT_LNA +#if IS_EXIST_PCI +extern u1Byte *data_AGC_TAB_8192E_extlna_start, *data_AGC_TAB_8192E_extlna_end; +extern u1Byte *data_AGC_TAB_8192E_extlna_type1_start, *data_AGC_TAB_8192E_extlna_type1_end; +extern u1Byte *data_AGC_TAB_8192E_extlna_type2_start, *data_AGC_TAB_8192E_extlna_type2_end; +extern u1Byte *data_AGC_TAB_8192E_extlna_type3_start, *data_AGC_TAB_8192E_extlna_type3_end; +extern u1Byte *data_PHY_REG_8192E_extlna_start, *data_PHY_REG_8192E_extlna_end; +extern u1Byte *data_RadioA_8192E_extlna_start, *data_RadioA_8192E_extlna_end; +extern u1Byte *data_RadioB_8192E_extlna_start, *data_RadioB_8192E_extlna_end; +#endif +#if IS_EXIST_SDIO +extern u1Byte *data_AGC_TAB_8192ES_extlna_start, *data_AGC_TAB_8192ES_extlna_end; +extern u1Byte *data_PHY_REG_8192ES_extlna_start, *data_PHY_REG_8192ES_extlna_end; +extern u1Byte *data_RadioA_8192ES_extlna_start, *data_RadioA_8192ES_extlna_end; +extern u1Byte *data_RadioB_8192ES_extlna_start, *data_RadioB_8192ES_extlna_end; +#endif +#endif + +// B-cut support +extern u1Byte *data_MAC_REG_8192Eb_start, *data_MAC_REG_8192Eb_end; +extern u1Byte *data_PHY_REG_8192Eb_start, *data_PHY_REG_8192Eb_end; +#if IS_EXIST_PCI +extern u1Byte *data_RadioA_8192Eb_start, *data_RadioA_8192Eb_end; +extern u1Byte *data_RadioB_8192Eb_start, *data_RadioB_8192Eb_end; +#endif + +// MP chip +#if IS_EXIST_PCI +extern u1Byte *data_AGC_TAB_8192Emp_start, *data_AGC_TAB_8192Emp_end; +extern u1Byte *data_RadioA_8192Emp_start, *data_RadioA_8192Emp_end; +extern u1Byte *data_RadioB_8192Emp_start, *data_RadioB_8192Emp_end; +extern u1Byte *data_RadioA_8192EmpA_start, *data_RadioA_8192EmpA_end; +extern u1Byte *data_RadioB_8192EmpA_start, *data_RadioB_8192EmpA_end; +#endif +#if IS_EXIST_SDIO +extern u1Byte *data_AGC_TAB_8192ES_start, *data_AGC_TAB_8192ES_end; +extern u1Byte *data_RadioA_8192ES_start, *data_RadioA_8192ES_end; +extern u1Byte *data_RadioB_8192ES_start, *data_RadioB_8192ES_end; +#endif +extern u1Byte *data_PHY_REG_MP_8192Emp_start, *data_PHY_REG_MP_8192Emp_end; +extern u1Byte *data_PHY_REG_PG_8192Emp_start, *data_PHY_REG_PG_8192Emp_end; +extern u1Byte *data_MAC_REG_8192Emp_start, *data_MAC_REG_8192Emp_end; +extern u1Byte *data_PHY_REG_8192Emp_start, *data_PHY_REG_8192Emp_end; + +// FW +#if IS_EXIST_PCI +extern u1Byte *data_rtl8192Efw_start, *data_rtl8192Efw_end; +extern u1Byte *data_rtl8192EfwMP_start, *data_rtl8192EfwMP_end; +#endif +#if IS_EXIST_SDIO +extern u1Byte *data_rtl8192ESfwMP_start, *data_rtl8192ESfwMP_end; +#endif + +// Power Tracking +extern u1Byte *data_TxPowerTrack_AP_start, *data_TxPowerTrack_AP_end; + +#ifdef TXPWR_LMT_92EE +extern unsigned char *data_TXPWR_LMT_92EE_new_start, *data_TXPWR_LMT_92EE_new_end; +#ifdef PWR_BY_RATE_92E_HP +#if CFG_HAL_HIGH_POWER_EXT_PA +extern unsigned char *data_TXPWR_LMT_92EE_hp_start, *data_TXPWR_LMT_92EE_hp_end; +#endif +#endif +#endif + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8192E_start, *data_MACDM_def_high_8192E_end; +extern u1Byte *data_MACDM_def_low_8192E_start, *data_MACDM_def_low_8192E_end; +extern u1Byte *data_MACDM_def_normal_8192E_start, *data_MACDM_def_normal_8192E_end; + +//general +extern u1Byte *data_MACDM_gen_high_8192E_start, *data_MACDM_gen_high_8192E_end; +extern u1Byte *data_MACDM_gen_low_8192E_start, *data_MACDM_gen_low_8192E_end; +extern u1Byte *data_MACDM_gen_normal_8192E_start, *data_MACDM_gen_normal_8192E_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8192E_start, *data_MACDM_txop_high_8192E_end; +extern u1Byte *data_MACDM_txop_low_8192E_start, *data_MACDM_txop_low_8192E_end; +extern u1Byte *data_MACDM_txop_normal_8192E_start, *data_MACDM_txop_normal_8192E_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8192E_start, *data_MACDM_state_criteria_8192E_end; + + + +#endif //__HAL8192E_DEF_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c old mode 100755 new mode 100644 index 8e6c4627805..09d9ac1e4c0 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c @@ -1,19 +1,19 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8192EPhyCfg.c - -Abstract: - Defined HAL 92E PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-22 Eric Create. ---*/ - - - - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192EPhyCfg.c + +Abstract: + Defined HAL 92E PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-22 Eric Create. +--*/ + + + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h old mode 100755 new mode 100644 index 6c6d06dc97a..72b273d06cb --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h @@ -1,23 +1,23 @@ -#ifndef __HAL8192EPHYCFG_H__ -#define __HAL8192EPHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8192EPhyCfg.h - -Abstract: - Defined HAL 92E PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-22 Eric Create. ---*/ - - - - -#endif //__HAL8192EPHYCFG_H__ - +#ifndef __HAL8192EPHYCFG_H__ +#define __HAL8192EPHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192EPhyCfg.h + +Abstract: + Defined HAL 92E PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-22 Eric Create. +--*/ + + + + +#endif //__HAL8192EPHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h old mode 100755 new mode 100644 index 88d14aee7a9..7f9dc581470 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h @@ -1,201 +1,201 @@ -#ifndef REALTEK_POWER_SEQUENCE_8192E -#define REALTEK_POWER_SEQUENCE_8192E - - -/* - Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 20 -#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8192E_TRANS_END_STEPS 1 - - -#define RTL8192E_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\ - {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - /*{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3A},*/ /*0x7A = 0x3A start BT*/\ - -#define RTL8192E_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ - - -#define RTL8192E_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8192E_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ -#ifndef NOT_RTK_BSP -#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/ \ - /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ -#else -#ifdef DONT_DISABLE_XTAL_ON_CLOSE -#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/ -#else -#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE -#endif -#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ -/* {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},*/ /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ -/* {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},*/ /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ -#endif - -#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8192E_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8192E_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8192E_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8192E_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8192E_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS+RTL8192E_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]; - -#endif - +#ifndef REALTEK_POWER_SEQUENCE_8192E +#define REALTEK_POWER_SEQUENCE_8192E + + +/* + Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 20 +#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8192E_TRANS_END_STEPS 1 + + +#define RTL8192E_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\ + {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + /*{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3A},*/ /*0x7A = 0x3A start BT*/\ + +#define RTL8192E_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ + + +#define RTL8192E_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8192E_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ +#ifndef NOT_RTK_BSP +#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/ \ + /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x04[10] = 1, enable SW LPS*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ +#else +#ifdef DONT_DISABLE_XTAL_ON_CLOSE +#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/ +#else +#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE +#endif +#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ +/* {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},*/ /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ +/* {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},*/ /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ +#endif + +#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8192E_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8192E_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8192E_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8192E_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8192E_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS+RTL8192E_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]; + +#endif + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEDef.h old mode 100755 new mode 100644 index 71faa3a2fe9..cc7a618fd27 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEDef.h @@ -1,119 +1,119 @@ -#ifndef __HAL8192EE_DEF_H__ -#define __HAL8192EE_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8192EEDef.h - -Abstract: - Defined HAL 8192EE data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - -/* -RT_STATUS -InitPON8192EE( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - -RT_STATUS -StopHW8192EE( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -hal_Associate_8192EE( - HAL_PADAPTER Adapter, - BOOLEAN IsDefaultAdapter -); - -*/ - -struct _RT_BEAMFORMING_INFO; - -VOID -SetBeamformRfMode92E( - struct rtl8192cd_priv *priv, - struct _RT_BEAMFORMING_INFO *pBeamformingInfo -); - - - -VOID -SetBeamformEnter92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformLeave92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformStatus92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - - -VOID -Beamforming_NDPARate_92E( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate -); - -VOID -C2HTxBeamformingHandler_92E( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); - -VOID -_C2HContentParsing92E( - struct rtl8192cd_priv *priv, - u1Byte c2hCmdId, - u1Byte c2hCmdLen, - pu1Byte tmpBuf -); - -VOID -C2HPacketHandler_92E( - struct rtl8192cd_priv *priv, - pu1Byte Buffer, - u1Byte Length -); - -VOID HW_VAR_HW_REG_TIMER_START_92E( - struct rtl8192cd_priv *priv -); - -VOID HW_VAR_HW_REG_TIMER_INIT_92E( - struct rtl8192cd_priv *priv, - u2Byte t -); - -VOID HW_VAR_HW_REG_TIMER_STOP_92E( - struct rtl8192cd_priv *priv -); - -RT_STATUS -hal_Associate_8192EE( +#ifndef __HAL8192EE_DEF_H__ +#define __HAL8192EE_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192EEDef.h + +Abstract: + Defined HAL 8192EE data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + +/* +RT_STATUS +InitPON8192EE( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + +RT_STATUS +StopHW8192EE( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +hal_Associate_8192EE( + HAL_PADAPTER Adapter, + BOOLEAN IsDefaultAdapter +); + +*/ + +struct _RT_BEAMFORMING_INFO; + +VOID +SetBeamformRfMode92E( + struct rtl8192cd_priv *priv, + struct _RT_BEAMFORMING_INFO *pBeamformingInfo +); + + + +VOID +SetBeamformEnter92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformLeave92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformStatus92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + + +VOID +Beamforming_NDPARate_92E( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate +); + +VOID +C2HTxBeamformingHandler_92E( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); + +VOID +_C2HContentParsing92E( + struct rtl8192cd_priv *priv, + u1Byte c2hCmdId, + u1Byte c2hCmdLen, + pu1Byte tmpBuf +); + +VOID +C2HPacketHandler_92E( + struct rtl8192cd_priv *priv, + pu1Byte Buffer, + u1Byte Length +); + +VOID HW_VAR_HW_REG_TIMER_START_92E( + struct rtl8192cd_priv *priv +); + +VOID HW_VAR_HW_REG_TIMER_INIT_92E( + struct rtl8192cd_priv *priv, + u2Byte t +); + +VOID HW_VAR_HW_REG_TIMER_STOP_92E( + struct rtl8192cd_priv *priv +); + +RT_STATUS +hal_Associate_8192EE( struct rtl8192cd_priv *priv, BOOLEAN IsDefaultAdapter -); - -#endif //__HAL8192EE_DEF_H__ - +); + +#endif //__HAL8192EE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h index 84f3ee2db68..e8335e31500 100644 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h @@ -1,119 +1,119 @@ -#ifndef __HAL8192EE_DEF_H__ -#define __HAL8192EE_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8192EEDef.h - -Abstract: - Defined HAL 8192EE data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - -/* -RT_STATUS -InitPON8192EE( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - -RT_STATUS -StopHW8192EE( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -hal_Associate_8192EE( - HAL_PADAPTER Adapter, - BOOLEAN IsDefaultAdapter -); - -*/ - -struct _RT_BEAMFORMING_INFO; - -VOID -SetBeamformRfMode92E( - struct rtl8192cd_priv *priv, - struct _RT_BEAMFORMING_INFO *pBeamformingInfo -); - - - -VOID -SetBeamformEnter92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformLeave92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformStatus92E( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - - -VOID -Beamforming_NDPARate_92E( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate -); - -VOID -C2HTxBeamformingHandler_92E( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); - -VOID -_C2HContentParsing92E( - struct rtl8192cd_priv *priv, - u1Byte c2hCmdId, - u1Byte c2hCmdLen, - pu1Byte tmpBuf -); - -VOID -C2HPacketHandler_92E( - struct rtl8192cd_priv *priv, - pu1Byte Buffer, - u1Byte Length -); - -VOID HW_VAR_HW_REG_TIMER_START_92E( - struct rtl8192cd_priv *priv -); - -VOID HW_VAR_HW_REG_TIMER_INIT_92E( - struct rtl8192cd_priv *priv, - u2Byte t -); - -VOID HW_VAR_HW_REG_TIMER_STOP_92E( - struct rtl8192cd_priv *priv -); - -RT_STATUS -hal_Associate_8192ES( - struct rtl8192cd_priv *priv, - BOOLEAN IsDefaultAdapter -); - -#endif //__HAL8192EE_DEF_H__ - +#ifndef __HAL8192EE_DEF_H__ +#define __HAL8192EE_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8192EEDef.h + +Abstract: + Defined HAL 8192EE data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + +/* +RT_STATUS +InitPON8192EE( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + +RT_STATUS +StopHW8192EE( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +hal_Associate_8192EE( + HAL_PADAPTER Adapter, + BOOLEAN IsDefaultAdapter +); + +*/ + +struct _RT_BEAMFORMING_INFO; + +VOID +SetBeamformRfMode92E( + struct rtl8192cd_priv *priv, + struct _RT_BEAMFORMING_INFO *pBeamformingInfo +); + + + +VOID +SetBeamformEnter92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformLeave92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformStatus92E( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + + +VOID +Beamforming_NDPARate_92E( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate +); + +VOID +C2HTxBeamformingHandler_92E( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); + +VOID +_C2HContentParsing92E( + struct rtl8192cd_priv *priv, + u1Byte c2hCmdId, + u1Byte c2hCmdLen, + pu1Byte tmpBuf +); + +VOID +C2HPacketHandler_92E( + struct rtl8192cd_priv *priv, + pu1Byte Buffer, + u1Byte Length +); + +VOID HW_VAR_HW_REG_TIMER_START_92E( + struct rtl8192cd_priv *priv +); + +VOID HW_VAR_HW_REG_TIMER_INIT_92E( + struct rtl8192cd_priv *priv, + u2Byte t +); + +VOID HW_VAR_HW_REG_TIMER_STOP_92E( + struct rtl8192cd_priv *priv +); + +RT_STATUS +hal_Associate_8192ES( + struct rtl8192cd_priv *priv, + BOOLEAN IsDefaultAdapter +); + +#endif //__HAL8192EE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FCfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FDef.h old mode 100755 new mode 100644 index 249c01e4369..9dc1e38fd64 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FDef.h @@ -1,150 +1,150 @@ -#ifndef __HAL8197F_DEF_H__ -#define __HAL8197F_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8197FDef.h - -Abstract: - Defined HAL 8197F data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - - -extern u1Byte *data_AGC_TAB_8197F_start, *data_AGC_TAB_8197F_end; -extern u1Byte *data_MAC_REG_8197F_start, *data_MAC_REG_8197F_end; -extern u1Byte *data_PHY_REG_8197F_start, *data_PHY_REG_8197F_end; -extern u1Byte *data_RadioA_8197F_start, *data_RadioA_8197F_end; -extern u1Byte *data_RadioB_8197F_start, *data_RadioB_8197F_end; - -/////////////////////////////////////////////////////////// - -extern u1Byte *data_MAC_REG_8197Fm_start, *data_MAC_REG_8197Fm_end; -extern u1Byte *data_PHY_REG_8197Fm_start, *data_PHY_REG_8197Fm_end; -extern u1Byte *data_PHY_REG_8197FMP_start, *data_PHY_REG_8197FMP_end; - -extern u1Byte *data_AGC_TAB_8197Fm_start, *data_AGC_TAB_8197Fm_end; -extern u1Byte *data_AGC_TAB_8197FBP_start, *data_AGC_TAB_8197FBP_end; -#ifdef CONFIG_8197F_2LAYER -extern u1Byte *data_AGC_TAB_8197FMP_2layer_start, *data_AGC_TAB_8197FMP_2layer_end; -#endif -extern u1Byte *data_AGC_TAB_8197FMP_start, *data_AGC_TAB_8197FMP_end; -extern u1Byte *data_AGC_TAB_8197FN_start, *data_AGC_TAB_8197FN_end; -extern u1Byte *data_AGC_TAB_8197FBP_intpa_start, *data_AGC_TAB_8197FBP_intpa_end; -extern u1Byte *data_AGC_TAB_8197FMP_intpa_start, *data_AGC_TAB_8197FMP_intpa_end; -extern u1Byte *data_AGC_TAB_8197FN_extpa_start, *data_AGC_TAB_8197FN_extpa_end; - -extern u1Byte *data_RadioA_8197Fm_start, *data_RadioA_8197Fm_end; -extern u1Byte *data_RadioA_8197FBP_start, *data_RadioA_8197FBP_end; -extern u1Byte *data_RadioA_8197FMP_start, *data_RadioA_8197FMP_end; -#ifdef CONFIG_8197F_2LAYER -extern u1Byte *data_RadioA_8197FMP_2layer_start, *data_RadioA_8197FMP_2layer_end; -#endif -extern u1Byte *data_RadioA_8197FN_start, *data_RadioA_8197FN_end; -extern u1Byte *data_RadioA_8197FBP_intpa_start, *data_RadioA_8197FBP_intpa_end; -extern u1Byte *data_RadioA_8197FMP_intpa_start, *data_RadioA_8197FMP_intpa_end; -extern u1Byte *data_RadioA_8197FN_extpa_start, *data_RadioA_8197FN_extpa_end; - -extern u1Byte *data_TxPowerTrack_AP_8197F_start, *data_TxPowerTrack_AP_8197F_end; -extern u1Byte *data_TxPowerTrack_AP_8197FMP_start, *data_TxPowerTrack_AP_8197FMP_end; -extern u1Byte *data_TxPowerTrack_AP_8197FBP_start, *data_TxPowerTrack_AP_8197FBP_end; -extern u1Byte *data_TxPowerTrack_AP_8197FN_start, *data_TxPowerTrack_AP_8197FN_end; -extern u1Byte *data_TxPowerTrack_AP_8197FMP_intpa_start, *data_TxPowerTrack_AP_8197FMP_intpa_end; -extern u1Byte *data_TxPowerTrack_AP_8197FBP_intpa_start, *data_TxPowerTrack_AP_8197FBP_intpa_end; -extern u1Byte *data_TxPowerTrack_AP_8197FN_extpa_start, *data_TxPowerTrack_AP_8197FN_extpa_end; - -extern u1Byte *data_PHY_REG_PG_8197Fmp_start, *data_PHY_REG_PG_8197Fmp_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type0_start, *data_PHY_REG_PG_8197Fmp_Type0_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type2_start, *data_PHY_REG_PG_8197Fmp_Type2_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type3_start, *data_PHY_REG_PG_8197Fmp_Type3_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type4_start, *data_PHY_REG_PG_8197Fmp_Type4_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type6_start, *data_PHY_REG_PG_8197Fmp_Type6_end; -#if CFG_HAL_HIGH_POWER_EXT_PA -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type1_start, *data_PHY_REG_PG_8197Fmp_Type1_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type4_start, *data_PHY_REG_PG_8197Fmp_Type4_end; -extern u1Byte *data_PHY_REG_PG_8197Fmp_Type5_start, *data_PHY_REG_PG_8197Fmp_Type5_end; -#endif - -#ifdef TXPWR_LMT_8197F -extern unsigned char *data_TXPWR_LMT_8197Fmp_start, *data_TXPWR_LMT_8197Fmp_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type0_start, *data_TXPWR_LMT_8197Fmp_Type0_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type2_start, *data_TXPWR_LMT_8197Fmp_Type2_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type3_start, *data_TXPWR_LMT_8197Fmp_Type3_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type4_start, *data_TXPWR_LMT_8197Fmp_Type4_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type6_start, *data_TXPWR_LMT_8197Fmp_Type6_end; -#if CFG_HAL_HIGH_POWER_EXT_PA -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type1_start, *data_TXPWR_LMT_8197Fmp_Type1_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type4_start, *data_TXPWR_LMT_8197Fmp_Type4_end; -extern unsigned char *data_TXPWR_LMT_8197Fmp_Type5_start, *data_TXPWR_LMT_8197Fmp_Type5_end; -#endif -#ifdef BEAMFORMING_AUTO -extern unsigned char *data_TXPWR_LMT_8197Fmp_TXBF_start, *data_TXPWR_LMT_8197Fmp_TXBF_end; -#endif -#endif - -#if 1 //Filen, file below should be updated -extern u1Byte *data_PHY_REG_MP_8197F_start, *data_PHY_REG_MP_8197F_end; -extern u1Byte *data_rtl8197Ffw_start, *data_rtl8197Ffw_end; -extern u1Byte *data_RTL8197FFW_Test_T_start, *data_RTL8197FFW_Test_T_end; -extern u1Byte *data_RTL8197FTXBUF_Test_T_start, *data_RTL8197FTXBUF_Test_T_end; -extern u1Byte *data_RTL8197FFW_A_CUT_T_start, *data_RTL8197FFW_A_CUT_T_end; -extern u1Byte *data_RTL8197FTXBUF_A_CUT_T_start, *data_RTL8197FTXBUF_A_CUT_T_end; -#endif - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8197F_start, *data_MACDM_def_high_8197F_end; -extern u1Byte *data_MACDM_def_low_8197F_start, *data_MACDM_def_low_8197F_end; -extern u1Byte *data_MACDM_def_normal_8197F_start, *data_MACDM_def_normal_8197F_end; - -//general -extern u1Byte *data_MACDM_gen_high_8197F_start, *data_MACDM_gen_high_8197F_end; -extern u1Byte *data_MACDM_gen_low_8197F_start, *data_MACDM_gen_low_8197F_end; -extern u1Byte *data_MACDM_gen_normal_8197F_start, *data_MACDM_gen_normal_8197F_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8197F_start, *data_MACDM_txop_high_8197F_end; -extern u1Byte *data_MACDM_txop_low_8197F_start, *data_MACDM_txop_low_8197F_end; -extern u1Byte *data_MACDM_txop_normal_8197F_start, *data_MACDM_txop_normal_8197F_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8197F_start, *data_MACDM_state_criteria_8197F_end; - - -RT_STATUS -StopHW8197F( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -hal_Associate_8197F( - HAL_PADAPTER Adapter, - BOOLEAN IsDefaultAdapter -); - - -RT_STATUS -InitPON8197F( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - - - - - - - - - - - - -#endif //__HAL8197F_DEF_H__ +#ifndef __HAL8197F_DEF_H__ +#define __HAL8197F_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8197FDef.h + +Abstract: + Defined HAL 8197F data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + + +extern u1Byte *data_AGC_TAB_8197F_start, *data_AGC_TAB_8197F_end; +extern u1Byte *data_MAC_REG_8197F_start, *data_MAC_REG_8197F_end; +extern u1Byte *data_PHY_REG_8197F_start, *data_PHY_REG_8197F_end; +extern u1Byte *data_RadioA_8197F_start, *data_RadioA_8197F_end; +extern u1Byte *data_RadioB_8197F_start, *data_RadioB_8197F_end; + +/////////////////////////////////////////////////////////// + +extern u1Byte *data_MAC_REG_8197Fm_start, *data_MAC_REG_8197Fm_end; +extern u1Byte *data_PHY_REG_8197Fm_start, *data_PHY_REG_8197Fm_end; +extern u1Byte *data_PHY_REG_8197FMP_start, *data_PHY_REG_8197FMP_end; + +extern u1Byte *data_AGC_TAB_8197Fm_start, *data_AGC_TAB_8197Fm_end; +extern u1Byte *data_AGC_TAB_8197FBP_start, *data_AGC_TAB_8197FBP_end; +#ifdef CONFIG_8197F_2LAYER +extern u1Byte *data_AGC_TAB_8197FMP_2layer_start, *data_AGC_TAB_8197FMP_2layer_end; +#endif +extern u1Byte *data_AGC_TAB_8197FMP_start, *data_AGC_TAB_8197FMP_end; +extern u1Byte *data_AGC_TAB_8197FN_start, *data_AGC_TAB_8197FN_end; +extern u1Byte *data_AGC_TAB_8197FBP_intpa_start, *data_AGC_TAB_8197FBP_intpa_end; +extern u1Byte *data_AGC_TAB_8197FMP_intpa_start, *data_AGC_TAB_8197FMP_intpa_end; +extern u1Byte *data_AGC_TAB_8197FN_extpa_start, *data_AGC_TAB_8197FN_extpa_end; + +extern u1Byte *data_RadioA_8197Fm_start, *data_RadioA_8197Fm_end; +extern u1Byte *data_RadioA_8197FBP_start, *data_RadioA_8197FBP_end; +extern u1Byte *data_RadioA_8197FMP_start, *data_RadioA_8197FMP_end; +#ifdef CONFIG_8197F_2LAYER +extern u1Byte *data_RadioA_8197FMP_2layer_start, *data_RadioA_8197FMP_2layer_end; +#endif +extern u1Byte *data_RadioA_8197FN_start, *data_RadioA_8197FN_end; +extern u1Byte *data_RadioA_8197FBP_intpa_start, *data_RadioA_8197FBP_intpa_end; +extern u1Byte *data_RadioA_8197FMP_intpa_start, *data_RadioA_8197FMP_intpa_end; +extern u1Byte *data_RadioA_8197FN_extpa_start, *data_RadioA_8197FN_extpa_end; + +extern u1Byte *data_TxPowerTrack_AP_8197F_start, *data_TxPowerTrack_AP_8197F_end; +extern u1Byte *data_TxPowerTrack_AP_8197FMP_start, *data_TxPowerTrack_AP_8197FMP_end; +extern u1Byte *data_TxPowerTrack_AP_8197FBP_start, *data_TxPowerTrack_AP_8197FBP_end; +extern u1Byte *data_TxPowerTrack_AP_8197FN_start, *data_TxPowerTrack_AP_8197FN_end; +extern u1Byte *data_TxPowerTrack_AP_8197FMP_intpa_start, *data_TxPowerTrack_AP_8197FMP_intpa_end; +extern u1Byte *data_TxPowerTrack_AP_8197FBP_intpa_start, *data_TxPowerTrack_AP_8197FBP_intpa_end; +extern u1Byte *data_TxPowerTrack_AP_8197FN_extpa_start, *data_TxPowerTrack_AP_8197FN_extpa_end; + +extern u1Byte *data_PHY_REG_PG_8197Fmp_start, *data_PHY_REG_PG_8197Fmp_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type0_start, *data_PHY_REG_PG_8197Fmp_Type0_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type2_start, *data_PHY_REG_PG_8197Fmp_Type2_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type3_start, *data_PHY_REG_PG_8197Fmp_Type3_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type4_start, *data_PHY_REG_PG_8197Fmp_Type4_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type6_start, *data_PHY_REG_PG_8197Fmp_Type6_end; +#if CFG_HAL_HIGH_POWER_EXT_PA +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type1_start, *data_PHY_REG_PG_8197Fmp_Type1_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type4_start, *data_PHY_REG_PG_8197Fmp_Type4_end; +extern u1Byte *data_PHY_REG_PG_8197Fmp_Type5_start, *data_PHY_REG_PG_8197Fmp_Type5_end; +#endif + +#ifdef TXPWR_LMT_8197F +extern unsigned char *data_TXPWR_LMT_8197Fmp_start, *data_TXPWR_LMT_8197Fmp_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type0_start, *data_TXPWR_LMT_8197Fmp_Type0_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type2_start, *data_TXPWR_LMT_8197Fmp_Type2_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type3_start, *data_TXPWR_LMT_8197Fmp_Type3_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type4_start, *data_TXPWR_LMT_8197Fmp_Type4_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type6_start, *data_TXPWR_LMT_8197Fmp_Type6_end; +#if CFG_HAL_HIGH_POWER_EXT_PA +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type1_start, *data_TXPWR_LMT_8197Fmp_Type1_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type4_start, *data_TXPWR_LMT_8197Fmp_Type4_end; +extern unsigned char *data_TXPWR_LMT_8197Fmp_Type5_start, *data_TXPWR_LMT_8197Fmp_Type5_end; +#endif +#ifdef BEAMFORMING_AUTO +extern unsigned char *data_TXPWR_LMT_8197Fmp_TXBF_start, *data_TXPWR_LMT_8197Fmp_TXBF_end; +#endif +#endif + +#if 1 //Filen, file below should be updated +extern u1Byte *data_PHY_REG_MP_8197F_start, *data_PHY_REG_MP_8197F_end; +extern u1Byte *data_rtl8197Ffw_start, *data_rtl8197Ffw_end; +extern u1Byte *data_RTL8197FFW_Test_T_start, *data_RTL8197FFW_Test_T_end; +extern u1Byte *data_RTL8197FTXBUF_Test_T_start, *data_RTL8197FTXBUF_Test_T_end; +extern u1Byte *data_RTL8197FFW_A_CUT_T_start, *data_RTL8197FFW_A_CUT_T_end; +extern u1Byte *data_RTL8197FTXBUF_A_CUT_T_start, *data_RTL8197FTXBUF_A_CUT_T_end; +#endif + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8197F_start, *data_MACDM_def_high_8197F_end; +extern u1Byte *data_MACDM_def_low_8197F_start, *data_MACDM_def_low_8197F_end; +extern u1Byte *data_MACDM_def_normal_8197F_start, *data_MACDM_def_normal_8197F_end; + +//general +extern u1Byte *data_MACDM_gen_high_8197F_start, *data_MACDM_gen_high_8197F_end; +extern u1Byte *data_MACDM_gen_low_8197F_start, *data_MACDM_gen_low_8197F_end; +extern u1Byte *data_MACDM_gen_normal_8197F_start, *data_MACDM_gen_normal_8197F_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8197F_start, *data_MACDM_txop_high_8197F_end; +extern u1Byte *data_MACDM_txop_low_8197F_start, *data_MACDM_txop_low_8197F_end; +extern u1Byte *data_MACDM_txop_normal_8197F_start, *data_MACDM_txop_normal_8197F_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8197F_start, *data_MACDM_state_criteria_8197F_end; + + +RT_STATUS +StopHW8197F( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +hal_Associate_8197F( + HAL_PADAPTER Adapter, + BOOLEAN IsDefaultAdapter +); + + +RT_STATUS +InitPON8197F( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + + + + + + + + + + + + +#endif //__HAL8197F_DEF_H__ diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FFirmware.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FFirmware.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FFirmware.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FFirmware.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FHWImg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FIsr.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FIsr.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.c old mode 100755 new mode 100644 index 969e90d4bb5..fc8269039b1 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.c @@ -1,102 +1,102 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8197FPhyCfg.c - -Abstract: - Defined HAL 8197F PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../../HalPrecomp.h" -#endif - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8197F( - IN HAL_PADAPTER Adapter -) -{ - // Do Nothing now -} - -u4Byte -PHY_QueryRFReg_8197F( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - u4Byte Readback_Value; - unsigned long flags; - HAL_PADAPTER priv = Adapter; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - - - HAL_SAVE_INT_AND_CLI(flags); - Readback_Value = config_phydm_read_rf_reg_8197f((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask); - HAL_RESTORE_INT(flags); - return Readback_Value; - - -} - -void PHY_SetRFReg_8197F -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -) -{ - u4Byte flags; - HAL_PADAPTER priv = Adapter; -#if CFG_HAL_DISABLE_BB_RF - return; -#endif //CFG_HAL_DISABLE_BB_RF - - HAL_SAVE_INT_AND_CLI(flags); - config_phydm_write_rf_reg_8197f((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask, Data); - HAL_RESTORE_INT(flags); - delay_us(20); - return; -} - -void -SwBWMode88XX_97F( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -) -{ - u1Byte regDataSC; - switch (bandwidth) { - case HT_CHANNEL_WIDTH_20: - bandwidth = ODM_BW20M; - break; - - case HT_CHANNEL_WIDTH_20_40: - bandwidth = ODM_BW40M; - regDataSC = HAL_RTL_R8(REG_DATA_SC); - regDataSC &= 0xf0; - regDataSC |= Adapter->pshare->txsc_20_92e; - HAL_RTL_W8(REG_DATA_SC, regDataSC); - break; - } - config_phydm_switch_bandwidth_8197f((&(Adapter->pshare->_dmODM)), offset, bandwidth); - return; - -} - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8197FPhyCfg.c + +Abstract: + Defined HAL 8197F PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../../HalPrecomp.h" +#endif + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8197F( + IN HAL_PADAPTER Adapter +) +{ + // Do Nothing now +} + +u4Byte +PHY_QueryRFReg_8197F( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + u4Byte Readback_Value; + unsigned long flags; + HAL_PADAPTER priv = Adapter; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + + + HAL_SAVE_INT_AND_CLI(flags); + Readback_Value = config_phydm_read_rf_reg_8197f((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask); + HAL_RESTORE_INT(flags); + return Readback_Value; + + +} + +void PHY_SetRFReg_8197F +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +) +{ + u4Byte flags; + HAL_PADAPTER priv = Adapter; +#if CFG_HAL_DISABLE_BB_RF + return; +#endif //CFG_HAL_DISABLE_BB_RF + + HAL_SAVE_INT_AND_CLI(flags); + config_phydm_write_rf_reg_8197f((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask, Data); + HAL_RESTORE_INT(flags); + delay_us(20); + return; +} + +void +SwBWMode88XX_97F( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +) +{ + u1Byte regDataSC; + switch (bandwidth) { + case HT_CHANNEL_WIDTH_20: + bandwidth = ODM_BW20M; + break; + + case HT_CHANNEL_WIDTH_20_40: + bandwidth = ODM_BW40M; + regDataSC = HAL_RTL_R8(REG_DATA_SC); + regDataSC &= 0xf0; + regDataSC |= Adapter->pshare->txsc_20_92e; + HAL_RTL_W8(REG_DATA_SC, regDataSC); + break; + } + config_phydm_switch_bandwidth_8197f((&(Adapter->pshare->_dmODM)), offset, bandwidth); + return; + +} + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.h old mode 100755 new mode 100644 index b9f06058029..97b2134f7a8 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPhyCfg.h @@ -1,56 +1,56 @@ -#ifndef __HAL8197FPHYCFG_H__ -#define __HAL8197FPHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8197FPhyCfg.h - -Abstract: - Defined HAL 88XX PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ - - - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8197F( - IN HAL_PADAPTER Adapter -); - -u4Byte -PHY_QueryRFReg_8197F( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -void -PHY_SetRFReg_8197F -( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data -); - -void -SwBWMode88XX_97F( - IN HAL_PADAPTER Adapter, - IN u4Byte bandwidth, - IN s4Byte offset -); - - - - -#endif // #ifndef __HAL8197FPHYCFG_H__ - +#ifndef __HAL8197FPHYCFG_H__ +#define __HAL8197FPHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8197FPhyCfg.h + +Abstract: + Defined HAL 88XX PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ + + + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8197F( + IN HAL_PADAPTER Adapter +); + +u4Byte +PHY_QueryRFReg_8197F( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +void +PHY_SetRFReg_8197F +( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data +); + +void +SwBWMode88XX_97F( + IN HAL_PADAPTER Adapter, + IN u4Byte bandwidth, + IN s4Byte offset +); + + + + +#endif // #ifndef __HAL8197FPHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.h old mode 100755 new mode 100644 index 868353ab436..56667aeeafb --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FPwrSeqCmd.h @@ -1,196 +1,196 @@ -#ifndef REALTEK_POWER_SEQUENCE_8197F -#define REALTEK_POWER_SEQUENCE_8197F - - -/* - Check document WM-20140117-JackieLau-RTL8197F_Power_Architecture.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS 25 -#define RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8197F_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8197F_TRANS_CARDDIS_TO_CARDEMU_STEPS 15 -#define RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8197F_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8197F_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8197F_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8197F_TRANS_END_STEPS 1 - -#if 0 - -{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ -{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ -{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ -{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ -{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - -#endif - -#define RTL8197F_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x0073, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/**/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - - -#define RTL8197F_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - -#define RTL8197F_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8197F_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8197F_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8197F_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - -#define RTL8197F_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8197F_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8197F_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8197F_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8197F_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - -#define RTL8197F_TRANS_96FSOC_POWER_ON \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x00A3, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 | BIT1 | BIT2 , 0}, /*0xa0[26:24] = 0 to prepare for checking HPON PMC*/ \ - {0x00A0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT4|BIT5|BIT6|BIT7, BIT5}, /* 0xa0[9:4] == 6'b10_0010 HPON PMC is ready.*/ \ - {0x00A1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1, BIT1}, /* 0xa0[9:4] == 6'b10_0010 HPON PMC is ready.*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0}, /*set (0x4[8] =1) to enable MAC PMC*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /* Polling (0x4[8] == 0){MAC PMC is ready}*/ \ - {0x00A3, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 | BIT1 | BIT2 , 0x4}, /*0xa0[26:24] = 4 to prepare for checking HPON PMC*/ \ - {0x00A0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7, 0}, /* If 0xa0[7:0] == 8'b0 HPON PMC is ready.*/ \ - {0x00A1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1, BIT0}, /* 0xa0[9:8] == 6'b01 HPON PMC is ready.*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0xFF}, /*0x2[7:0] = 0xff to enable all function */ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0xFF}, /*0x2[15:8] = 0xff to enable all function */ \ - - -extern WLAN_PWR_CFG rtl8197F_power_on_flow[RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_radio_off_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_card_disable_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_card_enable_flow[RTL8197F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_suspend_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_resume_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_hwpdn_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_enter_lps_flow[RTL8197F_TRANS_ACT_TO_LPS_STEPS+RTL8197F_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8197F_leave_lps_flow[RTL8197F_TRANS_LPS_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; - - -#endif +#ifndef REALTEK_POWER_SEQUENCE_8197F +#define REALTEK_POWER_SEQUENCE_8197F + + +/* + Check document WM-20140117-JackieLau-RTL8197F_Power_Architecture.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS 25 +#define RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS 15 +#define RTL8197F_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8197F_TRANS_CARDDIS_TO_CARDEMU_STEPS 15 +#define RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8197F_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8197F_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8197F_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8197F_TRANS_END_STEPS 1 + +#if 0 + +{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ +{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ +{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ +{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ +{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + +#endif + +#define RTL8197F_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0073, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/**/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + + +#define RTL8197F_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + +#define RTL8197F_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8197F_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8197F_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8197F_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + +#define RTL8197F_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8197F_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8197F_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8197F_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8197F_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + +#define RTL8197F_TRANS_96FSOC_POWER_ON \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x00A3, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 | BIT1 | BIT2 , 0}, /*0xa0[26:24] = 0 to prepare for checking HPON PMC*/ \ + {0x00A0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT4|BIT5|BIT6|BIT7, BIT5}, /* 0xa0[9:4] == 6'b10_0010 HPON PMC is ready.*/ \ + {0x00A1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1, BIT1}, /* 0xa0[9:4] == 6'b10_0010 HPON PMC is ready.*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0}, /*set (0x4[8] =1) to enable MAC PMC*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /* Polling (0x4[8] == 0){MAC PMC is ready}*/ \ + {0x00A3, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 | BIT1 | BIT2 , 0x4}, /*0xa0[26:24] = 4 to prepare for checking HPON PMC*/ \ + {0x00A0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7, 0}, /* If 0xa0[7:0] == 8'b0 HPON PMC is ready.*/ \ + {0x00A1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0|BIT1, BIT0}, /* 0xa0[9:8] == 6'b01 HPON PMC is ready.*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0xFF}, /*0x2[7:0] = 0xff to enable all function */ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0xFF}, /*0x2[15:8] = 0xff to enable all function */ \ + + +extern WLAN_PWR_CFG rtl8197F_power_on_flow[RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_radio_off_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_card_disable_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_card_enable_flow[RTL8197F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_suspend_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_resume_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_hwpdn_flow[RTL8197F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8197F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_enter_lps_flow[RTL8197F_TRANS_ACT_TO_LPS_STEPS+RTL8197F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8197F_leave_lps_flow[RTL8197F_TRANS_LPS_TO_ACT_STEPS+RTL8197F_TRANS_END_STEPS]; + + +#endif diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FReg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FReg.h old mode 100755 new mode 100644 index d3f5a12faa9..8b137891791 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FReg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FReg.h @@ -1 +1 @@ - + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FRxDesc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.h old mode 100755 new mode 100644 index f4ae27af3c0..3192efc65cc --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FTxDesc.h @@ -1,35 +1,35 @@ -#ifndef __HAL8197FA_TXDESC_H__ -#define __HAL8197FA_TXDESC_H__ - - -typedef enum _HCI_DMA_QUEUE_ { -/* - //QoS - HCI_DMA_QUEUE_VO = 0, - HCI_DMA_QUEUE_VI, - HCI_DMA_QUEUE_BE, - HCI_DMA_QUEUE_BK, - - //Beacon / MGT - HCI_DMA_QUEUE_MGT, - HCI_DMA_QUEUE_BCN, - - //HI - HCI_DMA_QUEUE_H0, - HCI_DMA_QUEUE_H1, - HCI_DMA_QUEUE_H2, - HCI_DMA_QUEUE_H3, - HCI_DMA_QUEUE_H4, - HCI_DMA_QUEUE_H5, - HCI_DMA_QUEUE_H6, - HCI_DMA_QUEUE_H7, - - HCI_DMA_QUEUE_MAX_NUM -*/ -}HCI_DMA_QUEUE, *PHCI_DMA_QUEUE; - - - - - +#ifndef __HAL8197FA_TXDESC_H__ +#define __HAL8197FA_TXDESC_H__ + + +typedef enum _HCI_DMA_QUEUE_ { +/* + //QoS + HCI_DMA_QUEUE_VO = 0, + HCI_DMA_QUEUE_VI, + HCI_DMA_QUEUE_BE, + HCI_DMA_QUEUE_BK, + + //Beacon / MGT + HCI_DMA_QUEUE_MGT, + HCI_DMA_QUEUE_BCN, + + //HI + HCI_DMA_QUEUE_H0, + HCI_DMA_QUEUE_H1, + HCI_DMA_QUEUE_H2, + HCI_DMA_QUEUE_H3, + HCI_DMA_QUEUE_H4, + HCI_DMA_QUEUE_H5, + HCI_DMA_QUEUE_H6, + HCI_DMA_QUEUE_H7, + + HCI_DMA_QUEUE_MAX_NUM +*/ +}HCI_DMA_QUEUE, *PHCI_DMA_QUEUE; + + + + + #endif //#ifndef __HAL8197FA_TXDESC_H__ \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/Hal8197FVerify.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEDef.h old mode 100755 new mode 100644 index f792b8dd597..70fc6634231 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEDef.h @@ -1,41 +1,41 @@ -#ifndef __HAL8197FE_DEF_H__ -#define __HAL8197FE_DEF_H__ - -#if (BEAMFORMING_SUPPORT == 1) - -VOID -Beamforming_NDPARate_8197F( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate -); - -VOID -SetBeamformStatus8197F( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformLeave8197F( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformEnter8197F( - struct rtl8192cd_priv *priv, - u1Byte BFerBFeeIdx -); - -VOID -C2HTxBeamformingHandler_8197F( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); -#endif - -#endif //__HAL8197FE_DEF_H__ - +#ifndef __HAL8197FE_DEF_H__ +#define __HAL8197FE_DEF_H__ + +#if (BEAMFORMING_SUPPORT == 1) + +VOID +Beamforming_NDPARate_8197F( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate +); + +VOID +SetBeamformStatus8197F( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformLeave8197F( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformEnter8197F( + struct rtl8192cd_priv *priv, + u1Byte BFerBFeeIdx +); + +VOID +C2HTxBeamformingHandler_8197F( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); +#endif + +#endif //__HAL8197FE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8197F/RTL8197FE/Hal8197FEGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814ADef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814ADef.h old mode 100755 new mode 100644 index 060eecfb700..8b2d124ad24 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814ADef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814ADef.h @@ -1,147 +1,147 @@ -#ifndef __HAL8814A_DEF_H__ -#define __HAL8814A_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8814ADef.h - -Abstract: - Defined HAL 8814A data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-05-28 Filen Create. ---*/ - -// Test Chip -extern u1Byte *data_AGC_TAB_8814A_start, *data_AGC_TAB_8814A_end; -extern u1Byte *data_MAC_REG_8814A_start, *data_MAC_REG_8814A_end; -extern u1Byte *data_PHY_REG_8814A_start, *data_PHY_REG_8814A_end; -//extern u1Byte *data_PHY_REG_1T_8814A_start, *data_PHY_REG_1T_8814A_end; -extern u1Byte *data_PHY_REG_MP_8814A_start, *data_PHY_REG_MP_8814A_end; -extern u1Byte *data_PHY_REG_PG_8814A_start, *data_PHY_REG_PG_8814A_end; -extern u1Byte *data_RadioA_8814A_start, *data_RadioA_8814A_end; -extern u1Byte *data_RadioB_8814A_start, *data_RadioB_8814A_end; -extern u1Byte *data_RadioC_8814A_start, *data_RadioC_8814A_end; -extern u1Byte *data_RadioD_8814A_start, *data_RadioD_8814A_end; - - -//High Power -#if CFG_HAL_HIGH_POWER_EXT_PA -extern u1Byte *data_AGC_TAB_8814A_hp_start, *data_AGC_TAB_8814A_hp_end; -extern u1Byte *data_PHY_REG_8814A_hp_start, *data_PHY_REG_8814A_hp_end; -extern u1Byte *data_RadioA_8814A_hp_start, *data_RadioA_8814A_hp_end; -extern u1Byte *data_RadioB_8814A_hp_start, *data_RadioB_8814A_hp_end; -extern u1Byte *data_RadioC_8814A_hp_start, *data_RadioC_8814A_hp_end; -extern u1Byte *data_RadioD_8814A_hp_start, *data_RadioD_8814A_hp_end; -#endif - -// FW -extern u1Byte *data_rtl8814Afw_start, *data_rtl8814Afw_end; -extern u1Byte *data_rtl8814AfwMP_start, *data_rtl8814AfwMP_end; - -// Power Tracking -extern u1Byte *data_TxPowerTrack_AP_8814A_start, *data_TxPowerTrack_AP_8814A_end; - - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8814A_start, *data_MACDM_def_high_8814A_end; -extern u1Byte *data_MACDM_def_low_8814A_start, *data_MACDM_def_low_8814A_end; -extern u1Byte *data_MACDM_def_normal_8814A_start, *data_MACDM_def_normal_8814A_end; - -//general -extern u1Byte *data_MACDM_gen_high_8814A_start, *data_MACDM_gen_high_8814A_end; -extern u1Byte *data_MACDM_gen_low_8814A_start, *data_MACDM_gen_low_8814A_end; -extern u1Byte *data_MACDM_gen_normal_8814A_start, *data_MACDM_gen_normal_8814A_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8814A_start, *data_MACDM_txop_high_8814A_end; -extern u1Byte *data_MACDM_txop_low_8814A_start, *data_MACDM_txop_low_8814A_end; -extern u1Byte *data_MACDM_txop_normal_8814A_start, *data_MACDM_txop_normal_8814A_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8814A_start, *data_MACDM_state_criteria_8814A_end; - - -// MP chip -extern u1Byte *data_AGC_TAB_8814Amp_start, *data_AGC_TAB_8814Amp_end; -extern u1Byte *data_MAC_REG_8814Amp_start, *data_MAC_REG_8814Amp_end; -extern u1Byte *data_PHY_REG_8814Amp_start, *data_PHY_REG_8814Amp_end; -//extern u1Byte *data_PHY_REG_1T_8814A_start, *data_PHY_REG_1T_8814A_end; -extern u1Byte *data_PHY_REG_MP_8814Amp_start, *data_PHY_REG_MP_8814Amp_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_start, *data_PHY_REG_PG_8814Amp_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type0_start, *data_PHY_REG_PG_8814Amp_Type0_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type7_start, *data_PHY_REG_PG_8814Amp_Type7_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type9_start, *data_PHY_REG_PG_8814Amp_Type9_end; -extern u1Byte *data_RadioA_8814Amp_start, *data_RadioA_8814Amp_end; -extern u1Byte *data_RadioB_8814Amp_start, *data_RadioB_8814Amp_end; -extern u1Byte *data_RadioC_8814Amp_start, *data_RadioC_8814Amp_end; -extern u1Byte *data_RadioD_8814Amp_start, *data_RadioD_8814Amp_end; - - -//High Power -#if CFG_HAL_HIGH_POWER_EXT_PA -extern u1Byte *data_AGC_TAB_8814Amp_hp_start, *data_AGC_TAB_8814Amp_hp_end; -extern u1Byte *data_PHY_REG_8814Amp_hp_start, *data_PHY_REG_8814Amp_hp_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type2_start, *data_PHY_REG_PG_8814Amp_Type2_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type3_start, *data_PHY_REG_PG_8814Amp_Type3_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type4_start, *data_PHY_REG_PG_8814Amp_Type4_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type5_start, *data_PHY_REG_PG_8814Amp_Type5_end; -extern u1Byte *data_PHY_REG_PG_8814Amp_Type8_start, *data_PHY_REG_PG_8814Amp_Type8_end; -extern u1Byte *data_RadioA_8814Amp_hp_start, *data_RadioA_8814Amp_hp_end; -extern u1Byte *data_RadioB_8814Amp_hp_start, *data_RadioB_8814Amp_hp_end; -extern u1Byte *data_RadioC_8814Amp_hp_start, *data_RadioC_8814Amp_hp_end; -extern u1Byte *data_RadioD_8814Amp_hp_start, *data_RadioD_8814Amp_hp_end; -#endif - -// FW -extern u1Byte *data_rtl8814Afw_start, *data_rtl8814Afw_end; -extern u1Byte *data_rtl8814AfwMP_start, *data_rtl8814AfwMP_end; - -// Power Tracking -extern u1Byte *data_TxPowerTrack_AP_8814Amp_start, *data_TxPowerTrack_AP_8814Amp_end; - -#ifdef TXPWR_LMT_8814A -extern unsigned char *data_TXPWR_LMT_8814Amp_start, *data_TXPWR_LMT_8814Amp_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type0_start, *data_TXPWR_LMT_8814Amp_Type0_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type7_start, *data_TXPWR_LMT_8814Amp_Type7_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type9_start, *data_TXPWR_LMT_8814Amp_Type9_end; -#if CFG_HAL_HIGH_POWER_EXT_PA -extern unsigned char *data_TXPWR_LMT_8814Amp_Type2_start, *data_TXPWR_LMT_8814Amp_Type2_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type3_start, *data_TXPWR_LMT_8814Amp_Type3_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type4_start, *data_TXPWR_LMT_8814Amp_Type4_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type5_start, *data_TXPWR_LMT_8814Amp_Type5_end; -extern unsigned char *data_TXPWR_LMT_8814Amp_Type8_start, *data_TXPWR_LMT_8814Amp_Type8_end; -#endif -#ifdef BEAMFORMING_AUTO -extern unsigned char *data_TXPWR_LMT_8814Amp_TXBF_start, *data_TXPWR_LMT_8814Amp_TXBF_end; -#endif -#endif - - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8814Amp_start, *data_MACDM_def_high_8814Amp_end; -extern u1Byte *data_MACDM_def_low_8814Amp_start, *data_MACDM_def_low_8814Amp_end; -extern u1Byte *data_MACDM_def_normal_8814Amp_start, *data_MACDM_def_normal_8814Amp_end; - -//general -extern u1Byte *data_MACDM_gen_high_8814Amp_start, *data_MACDM_gen_high_8814Amp_end; -extern u1Byte *data_MACDM_gen_low_8814Amp_start, *data_MACDM_gen_low_8814Amp_end; -extern u1Byte *data_MACDM_gen_normal_8814Amp_start, *data_MACDM_gen_normal_8814Amp_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8814Amp_start, *data_MACDM_txop_high_8814Amp_end; -extern u1Byte *data_MACDM_txop_low_8814Amp_start, *data_MACDM_txop_low_8814Amp_end; -extern u1Byte *data_MACDM_txop_normal_8814Amp_start, *data_MACDM_txop_normal_8814Amp_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8814Amp_start, *data_MACDM_state_criteria_8814Amp_end; - -#endif //__HAL8814A_DEF_H__ - - +#ifndef __HAL8814A_DEF_H__ +#define __HAL8814A_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8814ADef.h + +Abstract: + Defined HAL 8814A data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-05-28 Filen Create. +--*/ + +// Test Chip +extern u1Byte *data_AGC_TAB_8814A_start, *data_AGC_TAB_8814A_end; +extern u1Byte *data_MAC_REG_8814A_start, *data_MAC_REG_8814A_end; +extern u1Byte *data_PHY_REG_8814A_start, *data_PHY_REG_8814A_end; +//extern u1Byte *data_PHY_REG_1T_8814A_start, *data_PHY_REG_1T_8814A_end; +extern u1Byte *data_PHY_REG_MP_8814A_start, *data_PHY_REG_MP_8814A_end; +extern u1Byte *data_PHY_REG_PG_8814A_start, *data_PHY_REG_PG_8814A_end; +extern u1Byte *data_RadioA_8814A_start, *data_RadioA_8814A_end; +extern u1Byte *data_RadioB_8814A_start, *data_RadioB_8814A_end; +extern u1Byte *data_RadioC_8814A_start, *data_RadioC_8814A_end; +extern u1Byte *data_RadioD_8814A_start, *data_RadioD_8814A_end; + + +//High Power +#if CFG_HAL_HIGH_POWER_EXT_PA +extern u1Byte *data_AGC_TAB_8814A_hp_start, *data_AGC_TAB_8814A_hp_end; +extern u1Byte *data_PHY_REG_8814A_hp_start, *data_PHY_REG_8814A_hp_end; +extern u1Byte *data_RadioA_8814A_hp_start, *data_RadioA_8814A_hp_end; +extern u1Byte *data_RadioB_8814A_hp_start, *data_RadioB_8814A_hp_end; +extern u1Byte *data_RadioC_8814A_hp_start, *data_RadioC_8814A_hp_end; +extern u1Byte *data_RadioD_8814A_hp_start, *data_RadioD_8814A_hp_end; +#endif + +// FW +extern u1Byte *data_rtl8814Afw_start, *data_rtl8814Afw_end; +extern u1Byte *data_rtl8814AfwMP_start, *data_rtl8814AfwMP_end; + +// Power Tracking +extern u1Byte *data_TxPowerTrack_AP_8814A_start, *data_TxPowerTrack_AP_8814A_end; + + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8814A_start, *data_MACDM_def_high_8814A_end; +extern u1Byte *data_MACDM_def_low_8814A_start, *data_MACDM_def_low_8814A_end; +extern u1Byte *data_MACDM_def_normal_8814A_start, *data_MACDM_def_normal_8814A_end; + +//general +extern u1Byte *data_MACDM_gen_high_8814A_start, *data_MACDM_gen_high_8814A_end; +extern u1Byte *data_MACDM_gen_low_8814A_start, *data_MACDM_gen_low_8814A_end; +extern u1Byte *data_MACDM_gen_normal_8814A_start, *data_MACDM_gen_normal_8814A_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8814A_start, *data_MACDM_txop_high_8814A_end; +extern u1Byte *data_MACDM_txop_low_8814A_start, *data_MACDM_txop_low_8814A_end; +extern u1Byte *data_MACDM_txop_normal_8814A_start, *data_MACDM_txop_normal_8814A_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8814A_start, *data_MACDM_state_criteria_8814A_end; + + +// MP chip +extern u1Byte *data_AGC_TAB_8814Amp_start, *data_AGC_TAB_8814Amp_end; +extern u1Byte *data_MAC_REG_8814Amp_start, *data_MAC_REG_8814Amp_end; +extern u1Byte *data_PHY_REG_8814Amp_start, *data_PHY_REG_8814Amp_end; +//extern u1Byte *data_PHY_REG_1T_8814A_start, *data_PHY_REG_1T_8814A_end; +extern u1Byte *data_PHY_REG_MP_8814Amp_start, *data_PHY_REG_MP_8814Amp_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_start, *data_PHY_REG_PG_8814Amp_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type0_start, *data_PHY_REG_PG_8814Amp_Type0_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type7_start, *data_PHY_REG_PG_8814Amp_Type7_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type9_start, *data_PHY_REG_PG_8814Amp_Type9_end; +extern u1Byte *data_RadioA_8814Amp_start, *data_RadioA_8814Amp_end; +extern u1Byte *data_RadioB_8814Amp_start, *data_RadioB_8814Amp_end; +extern u1Byte *data_RadioC_8814Amp_start, *data_RadioC_8814Amp_end; +extern u1Byte *data_RadioD_8814Amp_start, *data_RadioD_8814Amp_end; + + +//High Power +#if CFG_HAL_HIGH_POWER_EXT_PA +extern u1Byte *data_AGC_TAB_8814Amp_hp_start, *data_AGC_TAB_8814Amp_hp_end; +extern u1Byte *data_PHY_REG_8814Amp_hp_start, *data_PHY_REG_8814Amp_hp_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type2_start, *data_PHY_REG_PG_8814Amp_Type2_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type3_start, *data_PHY_REG_PG_8814Amp_Type3_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type4_start, *data_PHY_REG_PG_8814Amp_Type4_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type5_start, *data_PHY_REG_PG_8814Amp_Type5_end; +extern u1Byte *data_PHY_REG_PG_8814Amp_Type8_start, *data_PHY_REG_PG_8814Amp_Type8_end; +extern u1Byte *data_RadioA_8814Amp_hp_start, *data_RadioA_8814Amp_hp_end; +extern u1Byte *data_RadioB_8814Amp_hp_start, *data_RadioB_8814Amp_hp_end; +extern u1Byte *data_RadioC_8814Amp_hp_start, *data_RadioC_8814Amp_hp_end; +extern u1Byte *data_RadioD_8814Amp_hp_start, *data_RadioD_8814Amp_hp_end; +#endif + +// FW +extern u1Byte *data_rtl8814Afw_start, *data_rtl8814Afw_end; +extern u1Byte *data_rtl8814AfwMP_start, *data_rtl8814AfwMP_end; + +// Power Tracking +extern u1Byte *data_TxPowerTrack_AP_8814Amp_start, *data_TxPowerTrack_AP_8814Amp_end; + +#ifdef TXPWR_LMT_8814A +extern unsigned char *data_TXPWR_LMT_8814Amp_start, *data_TXPWR_LMT_8814Amp_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type0_start, *data_TXPWR_LMT_8814Amp_Type0_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type7_start, *data_TXPWR_LMT_8814Amp_Type7_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type9_start, *data_TXPWR_LMT_8814Amp_Type9_end; +#if CFG_HAL_HIGH_POWER_EXT_PA +extern unsigned char *data_TXPWR_LMT_8814Amp_Type2_start, *data_TXPWR_LMT_8814Amp_Type2_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type3_start, *data_TXPWR_LMT_8814Amp_Type3_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type4_start, *data_TXPWR_LMT_8814Amp_Type4_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type5_start, *data_TXPWR_LMT_8814Amp_Type5_end; +extern unsigned char *data_TXPWR_LMT_8814Amp_Type8_start, *data_TXPWR_LMT_8814Amp_Type8_end; +#endif +#ifdef BEAMFORMING_AUTO +extern unsigned char *data_TXPWR_LMT_8814Amp_TXBF_start, *data_TXPWR_LMT_8814Amp_TXBF_end; +#endif +#endif + + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8814Amp_start, *data_MACDM_def_high_8814Amp_end; +extern u1Byte *data_MACDM_def_low_8814Amp_start, *data_MACDM_def_low_8814Amp_end; +extern u1Byte *data_MACDM_def_normal_8814Amp_start, *data_MACDM_def_normal_8814Amp_end; + +//general +extern u1Byte *data_MACDM_gen_high_8814Amp_start, *data_MACDM_gen_high_8814Amp_end; +extern u1Byte *data_MACDM_gen_low_8814Amp_start, *data_MACDM_gen_low_8814Amp_end; +extern u1Byte *data_MACDM_gen_normal_8814Amp_start, *data_MACDM_gen_normal_8814Amp_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8814Amp_start, *data_MACDM_txop_high_8814Amp_end; +extern u1Byte *data_MACDM_txop_low_8814Amp_start, *data_MACDM_txop_low_8814Amp_end; +extern u1Byte *data_MACDM_txop_normal_8814Amp_start, *data_MACDM_txop_normal_8814Amp_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8814Amp_start, *data_MACDM_state_criteria_8814Amp_end; + +#endif //__HAL8814A_DEF_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.h old mode 100755 new mode 100644 index 81cb8b8240d..7044bef1d4c --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AFirmware.h @@ -1,44 +1,44 @@ -#ifndef __HAL8814A_FIRMWARE_H__ -#define __HAL8814A_FIRMWARE_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88814AFirmware.h - -Abstract: - Defined HAL 8814A Firmware data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-08-27 Eric Create. ---*/ - -#define ctrlInfoSZ_8814 32 - - -typedef struct _Ctrl_Info_8814_ { - u1Byte SGI: 1; - u1Byte Data_Rate: 7; - u1Byte PKT_DROP: 1; - u1Byte TRY_RATE: 1; - u1Byte Rsvd: 1; - u1Byte DATA_BW: 2; - u1Byte PWRSTS: 3; - u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; - u1Byte Rsvd2: 1; - u1Byte GROUP_TABLE_ID: 3; - u1Byte RTY_LOW_RATE_EN: 1; - u1Byte DATA_RTY_LOW_RATE: 7; - u1Byte RTY_LMT_EN: 1; - u1Byte RTS_RT_LOW_RATE: 7; - u1Byte Rsvd3: 1; - u1Byte PKT_TX_ONE_SEL: 1; - u1Byte DATA_RT_LMT: 6; - u1Byte Rsvd4: 8; - u1Byte Rsvd5: 8; -} Ctrl_Info_8814, *PCtrl_Info_8814; - -#endif +#ifndef __HAL8814A_FIRMWARE_H__ +#define __HAL8814A_FIRMWARE_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88814AFirmware.h + +Abstract: + Defined HAL 8814A Firmware data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-08-27 Eric Create. +--*/ + +#define ctrlInfoSZ_8814 32 + + +typedef struct _Ctrl_Info_8814_ { + u1Byte SGI: 1; + u1Byte Data_Rate: 7; + u1Byte PKT_DROP: 1; + u1Byte TRY_RATE: 1; + u1Byte Rsvd: 1; + u1Byte DATA_BW: 2; + u1Byte PWRSTS: 3; + u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; + u1Byte Rsvd2: 1; + u1Byte GROUP_TABLE_ID: 3; + u1Byte RTY_LOW_RATE_EN: 1; + u1Byte DATA_RTY_LOW_RATE: 7; + u1Byte RTY_LMT_EN: 1; + u1Byte RTS_RT_LOW_RATE: 7; + u1Byte Rsvd3: 1; + u1Byte PKT_TX_ONE_SEL: 1; + u1Byte DATA_RT_LMT: 6; + u1Byte Rsvd4: 8; + u1Byte Rsvd5: 8; +} Ctrl_Info_8814, *PCtrl_Info_8814; + +#endif diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.c old mode 100755 new mode 100644 index dd8a05b03c5..c1851717ddd --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.c @@ -1,381 +1,381 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8814APhyCfg.c - -Abstract: - Defined HAL 8814A PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-05-28 Filen Create. ---*/ -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../../HalPrecomp.h" -#endif - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8814A( - IN HAL_PADAPTER Adapter -) -{ - // Do Nothing now -} - -u4Byte -PHY_QueryRFReg_8814( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - // The phy Query function have bug in 8812 & 8881, must follow the rules as below - // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] - // 2. Before Query RF reg, we must turn off CCA - // 3. delay 10us after set addr - // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - - HAL_PADAPTER priv = Adapter; - unsigned long flags; - u4Byte Original_Value, Readback_Value, BitShift; - u4Byte temp_CCA; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - - HAL_SAVE_INT_AND_CLI(flags); - - u4Byte DataAndAddr = 0; - u4Byte Direct_Addr; - - RegAddr &= 0xff; - switch(eRFPath){ - case RF88XX_PATH_A: - Direct_Addr = 0x2800+RegAddr*4; - break; - case RF88XX_PATH_B: - Direct_Addr = 0x2c00+RegAddr*4; - break; - case RF88XX_PATH_C: - Direct_Addr = 0x3800+RegAddr*4; - break; - case RF88XX_PATH_D: - Direct_Addr = 0x3c00+RegAddr*4; - break; - } - - - BitMask &= bRFRegOffsetMask; - - Readback_Value = PHY_QueryBBReg(Adapter, Direct_Addr, BitMask); - - HAL_RESTORE_INT(flags); - - return (Readback_Value); -} - - -/* Setting CCA TH 2nd CCA parameter by Rx Antenna */ -void -PHY_Set_SecCCATH_by_RXANT_8814A( - IN HAL_PADAPTER Adapter, - IN u4Byte ulAntennaRx -) -{ - HAL_PADAPTER priv = Adapter; - - u1Byte Current_band; - - if (HAL_VAR_DOT11CHANNEL <= CHANNEL_MAX_NUMBER_2G) - Current_band = RF88XX_BAND_ON_2_4G; - else - Current_band = RF88XX_BAND_ON_5G; - - - if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_80){ - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x7C0000, 0x8); // 830[22:18] reset default - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x76); // 838[15:8] reset default - if(priv->pshare->rf_ft_var.mp_specific == 1) - PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x1); - switch(ulAntennaRx){ - case ANTENNA_A: // xT1R - case ANTENNA_B: - case ANTENNA_C: - case ANTENNA_D: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7599); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 9, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x887); // 838[27:24]=8, RF80_secondary40, 838[23:20]=8, RF80_secondary20, 838[19:16]=7, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); //0x844[27:24]=0xb - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); - break; - case ANTENNA_AB: // xT2R - case ANTENNA_AC: - case ANTENNA_BC: - case ANTENNA_BD: - case ANTENNA_CD: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 0x82C[23:20] = 7, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x444); // 838[27:24]=4, RF80_secondary40, 838[23:20]=4, RF80_secondary20, 838[19:16]=4, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); - break; - case ANTENNA_ABC: // xT3R - case ANTENNA_BCD: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7398); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); - break; - case ANTENNA_ABCD: // xT4R - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7366); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 840[15:12]=7, L1_square_Pk_weight_80M - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); - break; - default: - printk("Unknown Rx antenna.\n"); - break; - } - }else if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40){ - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:16] reset default - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 840[15:12] reset default - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x1, 0x1); // 838[0] =0x1 - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0xFF00, 0x43); // 838[15:8] =0x52 - if(priv->pshare->rf_ft_var.mp_specific == 1) - PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x1); - switch(ulAntennaRx){ - case ANTENNA_A: // xT1R - case ANTENNA_B: - case ANTENNA_C: - case ANTENNA_D: - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 82C[23:16] reset default - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); //0x844[27:24]=0xb - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79B8EA0A); - break; - case ANTENNA_AB: // xT2R - case ANTENNA_AC: - case ANTENNA_BC: - case ANTENNA_BD: - case ANTENNA_CD: - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 82C[23:16] reset default - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); - break; - - default: - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x7C0000, 0xa); // 830[22:18] = 5b'01010 - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x22); // 0x839 - if(Current_band == RF88XX_BAND_ON_2_4G) { - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7596); - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A8EA0B); - }else{ - if (ulAntennaRx==ANTENNA_ABCD) - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7555); - else - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); - - //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7398); // 82C[23:16] reset default - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A8EA08); // 0x830 - } - break; - } - }else{ - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x76); // 838[15:8] reset default - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000000F, 0x1); // Enable 2ndCCA for 20M suggested by Casper and BB - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7543); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x7); - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x7aa); // 0x838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 0x840[15:12]=7, L1_square_Pk_weight_80M - PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); // 0x844[27:24]=0xb - if(priv->pshare->rf_ft_var.mp_specific == 1) - PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x2); - switch(ulAntennaRx){ - case ANTENNA_A: // xT1R - case ANTENNA_B: - case ANTENNA_C: - case ANTENNA_D: - case ANTENNA_AB: // xT2R - case ANTENNA_AC: - case ANTENNA_BC: - case ANTENNA_BD: - case ANTENNA_CD: - if(Current_band == RF88XX_BAND_ON_2_4G){ - //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7343); // 0x82f, 0x82e - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); // 0x830 - }else{ - //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7543); // 0x82f, 0x82e - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); // 0x830 - } - break; - default: - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x000000FF, 0x08); // 0x830 - if (ulAntennaRx==ANTENNA_ABCD){ - if(Current_band == RF88XX_BAND_ON_2_4G) { - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x2); // 0x82c - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); // 0x830 - }else{ - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79a14a0a); - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); // 82C[23:16] reset default - } - }else - PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); - //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7343); // 0x82f, 0x82e - break; - } - } - -} - - -// <20141230, James> A workaround to eliminate the 5280MHz & 5600MHz & 5760MHz spur of 8814A. (Asked by BBSD Neil.) -void -phy_SpurCalibration_8814A( - IN HAL_PADAPTER Adapter -) -{ - BOOLEAN Reset_NBI_CSI = TRUE; - BOOLEAN Temp_Flag = TRUE; - - if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20 && HAL_VAR_WORKING_CHANNEL == 153){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(16), 1); - - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); - Temp_Flag=FALSE; - } - - Reset_NBI_CSI = FALSE; - }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20_40 && HAL_VAR_WORKING_CHANNEL == 151){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT(16), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - if ((HAL_RFE_TYPE == 0)||(HAL_RFE_TYPE == 7)||(HAL_RFE_TYPE == 9)){ //for ifem - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x6); - Temp_Flag=FALSE; - } - } - Reset_NBI_CSI = FALSE; - }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_80 && HAL_VAR_WORKING_CHANNEL == 155){ // center ch 155 - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x2d); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT(16), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - - Reset_NBI_CSI = FALSE; - } - - if((HAL_RFE_TYPE == 0)||(HAL_RFE_TYPE == 7)||(HAL_RFE_TYPE == 9)){ //for ifem - switch(HAL_VAR_CURRENTCHANNELBW){ - case HT_CHANNEL_WIDTH_20_40: - if(HAL_VAR_WORKING_CHANNEL == 54 || HAL_VAR_WORKING_CHANNEL == 118){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1f); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT(0), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(Adapter->pmib->dot11RFEntry.MIMO_TR_mode==MIMO_1T1R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x6); - Temp_Flag=FALSE; - } - - Reset_NBI_CSI = FALSE; - } - break; - case HT_CHANNEL_WIDTH_80: // center ch 58, 122 - if(HAL_VAR_WORKING_CHANNEL == 58 || HAL_VAR_WORKING_CHANNEL == 122){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1d); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(0), 1); - Reset_NBI_CSI = FALSE; - } - break; - default: - break; - } - } - if (Reset_NBI_CSI){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x7e); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - - } - if(Temp_Flag){ - if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_20){ - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); - }else{ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x7); - } - }else if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_20_40) - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x5); - }else{ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x8); - } - else if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_80) - if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x99); - } else if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_AC)||(Adapter->pshare->mp_antenna_rx==ANTENNA_AB)||(Adapter->pshare->mp_antenna_rx==ANTENNA_BC)||(Adapter->pshare->mp_antenna_rx==ANTENNA_BD)||(Adapter->pshare->mp_antenna_rx==ANTENNA_CD))) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_2T2R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); - } else if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) - || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x66); - } else { - PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); - } - } -} - -void -phy_ConfigBB_8814A( - IN HAL_PADAPTER Adapter -) -{ - printk("[%s] start\n",__FUNCTION__); - PHY_SetBBReg(Adapter, rOFDMCCKEN_Jaguar, bOFDMEN_Jaguar|bCCKEN_Jaguar, 0x3); - PHY_SetBBReg(Adapter, 0x820, BIT_MASK_SET_MASKDWORD_COMMON, 0x0003BD20); - PHY_SetBBReg(Adapter, 0x828, BIT_MASK_SET_MASKDWORD_COMMON, 0x0003BD20); - PHY_SetBBReg(Adapter, rADC_Buf_160_Clk_Jaguar, BIT31, 0x1); -} - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8814APhyCfg.c + +Abstract: + Defined HAL 8814A PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-05-28 Filen Create. +--*/ +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../../HalPrecomp.h" +#endif + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8814A( + IN HAL_PADAPTER Adapter +) +{ + // Do Nothing now +} + +u4Byte +PHY_QueryRFReg_8814( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + // The phy Query function have bug in 8812 & 8881, must follow the rules as below + // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] + // 2. Before Query RF reg, we must turn off CCA + // 3. delay 10us after set addr + // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + + HAL_PADAPTER priv = Adapter; + unsigned long flags; + u4Byte Original_Value, Readback_Value, BitShift; + u4Byte temp_CCA; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + + HAL_SAVE_INT_AND_CLI(flags); + + u4Byte DataAndAddr = 0; + u4Byte Direct_Addr; + + RegAddr &= 0xff; + switch(eRFPath){ + case RF88XX_PATH_A: + Direct_Addr = 0x2800+RegAddr*4; + break; + case RF88XX_PATH_B: + Direct_Addr = 0x2c00+RegAddr*4; + break; + case RF88XX_PATH_C: + Direct_Addr = 0x3800+RegAddr*4; + break; + case RF88XX_PATH_D: + Direct_Addr = 0x3c00+RegAddr*4; + break; + } + + + BitMask &= bRFRegOffsetMask; + + Readback_Value = PHY_QueryBBReg(Adapter, Direct_Addr, BitMask); + + HAL_RESTORE_INT(flags); + + return (Readback_Value); +} + + +/* Setting CCA TH 2nd CCA parameter by Rx Antenna */ +void +PHY_Set_SecCCATH_by_RXANT_8814A( + IN HAL_PADAPTER Adapter, + IN u4Byte ulAntennaRx +) +{ + HAL_PADAPTER priv = Adapter; + + u1Byte Current_band; + + if (HAL_VAR_DOT11CHANNEL <= CHANNEL_MAX_NUMBER_2G) + Current_band = RF88XX_BAND_ON_2_4G; + else + Current_band = RF88XX_BAND_ON_5G; + + + if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_80){ + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x7C0000, 0x8); // 830[22:18] reset default + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x76); // 838[15:8] reset default + if(priv->pshare->rf_ft_var.mp_specific == 1) + PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x1); + switch(ulAntennaRx){ + case ANTENNA_A: // xT1R + case ANTENNA_B: + case ANTENNA_C: + case ANTENNA_D: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7599); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 9, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x887); // 838[27:24]=8, RF80_secondary40, 838[23:20]=8, RF80_secondary20, 838[19:16]=7, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); //0x844[27:24]=0xb + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); + break; + case ANTENNA_AB: // xT2R + case ANTENNA_AC: + case ANTENNA_BC: + case ANTENNA_BD: + case ANTENNA_CD: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 0x82C[23:20] = 7, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x444); // 838[27:24]=4, RF80_secondary40, 838[23:20]=4, RF80_secondary20, 838[19:16]=4, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); + break; + case ANTENNA_ABC: // xT3R + case ANTENNA_BCD: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7398); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); + break; + case ANTENNA_ABCD: // xT4R + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7366); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 840[15:12]=7, L1_square_Pk_weight_80M + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); + break; + default: + printk("Unknown Rx antenna.\n"); + break; + } + }else if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40){ + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:16] reset default + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 840[15:12] reset default + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x1, 0x1); // 838[0] =0x1 + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0xFF00, 0x43); // 838[15:8] =0x52 + if(priv->pshare->rf_ft_var.mp_specific == 1) + PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x1); + switch(ulAntennaRx){ + case ANTENNA_A: // xT1R + case ANTENNA_B: + case ANTENNA_C: + case ANTENNA_D: + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 82C[23:16] reset default + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); //0x844[27:24]=0xb + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79B8EA0A); + break; + case ANTENNA_AB: // xT2R + case ANTENNA_AC: + case ANTENNA_BC: + case ANTENNA_BD: + case ANTENNA_CD: + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); // 82C[23:16] reset default + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); + break; + + default: + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x7C0000, 0xa); // 830[22:18] = 5b'01010 + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xd); //0x844[27:24]=0xd + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x22); // 0x839 + if(Current_band == RF88XX_BAND_ON_2_4G) { + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7596); + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A8EA0B); + }else{ + if (ulAntennaRx==ANTENNA_ABCD) + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7555); + else + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7598); + + //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7398); // 82C[23:16] reset default + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A8EA08); // 0x830 + } + break; + } + }else{ + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000FF00, 0x76); // 838[15:8] reset default + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0000000F, 0x1); // Enable 2ndCCA for 20M suggested by Casper and BB + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7543); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x7); + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x7aa); // 0x838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); // 0x840[15:12]=7, L1_square_Pk_weight_80M + PHY_SetBBReg(priv, 0x844, 0x0F000000, 0xb); // 0x844[27:24]=0xb + if(priv->pshare->rf_ft_var.mp_specific == 1) + PHY_SetBBReg(priv, 0x8ac, 0x3c, 0x2); + switch(ulAntennaRx){ + case ANTENNA_A: // xT1R + case ANTENNA_B: + case ANTENNA_C: + case ANTENNA_D: + case ANTENNA_AB: // xT2R + case ANTENNA_AC: + case ANTENNA_BC: + case ANTENNA_BD: + case ANTENNA_CD: + if(Current_band == RF88XX_BAND_ON_2_4G){ + //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7343); // 0x82f, 0x82e + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); // 0x830 + }else{ + //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7543); // 0x82f, 0x82e + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA0A); // 0x830 + } + break; + default: + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0x000000FF, 0x08); // 0x830 + if (ulAntennaRx==ANTENNA_ABCD){ + if(Current_band == RF88XX_BAND_ON_2_4G) { + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x2); // 0x82c + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); // 0x830 + }else{ + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79a14a0a); + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); // 82C[23:16] reset default + } + }else + PHY_SetBBReg(priv, REG_BB_PWED_TH_AC, 0xFFFFFFFF, 0x79A0EA08); + //PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0xFFFF0000, 0x7343); // 0x82f, 0x82e + break; + } + } + +} + + +// <20141230, James> A workaround to eliminate the 5280MHz & 5600MHz & 5760MHz spur of 8814A. (Asked by BBSD Neil.) +void +phy_SpurCalibration_8814A( + IN HAL_PADAPTER Adapter +) +{ + BOOLEAN Reset_NBI_CSI = TRUE; + BOOLEAN Temp_Flag = TRUE; + + if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20 && HAL_VAR_WORKING_CHANNEL == 153){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(16), 1); + + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); + Temp_Flag=FALSE; + } + + Reset_NBI_CSI = FALSE; + }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20_40 && HAL_VAR_WORKING_CHANNEL == 151){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT(16), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + if ((HAL_RFE_TYPE == 0)||(HAL_RFE_TYPE == 7)||(HAL_RFE_TYPE == 9)){ //for ifem + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x6); + Temp_Flag=FALSE; + } + } + Reset_NBI_CSI = FALSE; + }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_80 && HAL_VAR_WORKING_CHANNEL == 155){ // center ch 155 + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x2d); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT(16), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + + Reset_NBI_CSI = FALSE; + } + + if((HAL_RFE_TYPE == 0)||(HAL_RFE_TYPE == 7)||(HAL_RFE_TYPE == 9)){ //for ifem + switch(HAL_VAR_CURRENTCHANNELBW){ + case HT_CHANNEL_WIDTH_20_40: + if(HAL_VAR_WORKING_CHANNEL == 54 || HAL_VAR_WORKING_CHANNEL == 118){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1f); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT(0), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(Adapter->pmib->dot11RFEntry.MIMO_TR_mode==MIMO_1T1R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x6); + Temp_Flag=FALSE; + } + + Reset_NBI_CSI = FALSE; + } + break; + case HT_CHANNEL_WIDTH_80: // center ch 58, 122 + if(HAL_VAR_WORKING_CHANNEL == 58 || HAL_VAR_WORKING_CHANNEL == 122){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1d); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(0), 1); + Reset_NBI_CSI = FALSE; + } + break; + default: + break; + } + } + if (Reset_NBI_CSI){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x7e); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + + } + if(Temp_Flag){ + if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_20){ + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x3); + }else{ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x0000F000, 0x7); + } + }else if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_20_40) + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x5); + }else{ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x000F0000, 0x8); + } + else if(HAL_VAR_CURRENTCHANNELBW==HT_CHANNEL_WIDTH_80) + if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_A)||(Adapter->pshare->mp_antenna_rx==ANTENNA_B)||(Adapter->pshare->mp_antenna_rx==ANTENNA_C)||(Adapter->pshare->mp_antenna_rx==ANTENNA_D))) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_1T1R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x99); + } else if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&((Adapter->pshare->mp_antenna_rx==ANTENNA_AC)||(Adapter->pshare->mp_antenna_rx==ANTENNA_AB)||(Adapter->pshare->mp_antenna_rx==ANTENNA_BC)||(Adapter->pshare->mp_antenna_rx==ANTENNA_BD)||(Adapter->pshare->mp_antenna_rx==ANTENNA_CD))) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_2T2R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); + } else if (((Adapter->pshare->rf_ft_var.mp_specific==1)&&(Adapter->pshare->mp_antenna_rx==ANTENNA_ABCD)) + || ((Adapter->pshare->rf_ft_var.mp_specific==0)&&(get_rf_mimo_mode(Adapter)==MIMO_3T3R))){ + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x66); + } else { + PHY_SetBBReg(Adapter, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); + } + } +} + +void +phy_ConfigBB_8814A( + IN HAL_PADAPTER Adapter +) +{ + printk("[%s] start\n",__FUNCTION__); + PHY_SetBBReg(Adapter, rOFDMCCKEN_Jaguar, bOFDMEN_Jaguar|bCCKEN_Jaguar, 0x3); + PHY_SetBBReg(Adapter, 0x820, BIT_MASK_SET_MASKDWORD_COMMON, 0x0003BD20); + PHY_SetBBReg(Adapter, 0x828, BIT_MASK_SET_MASKDWORD_COMMON, 0x0003BD20); + PHY_SetBBReg(Adapter, rADC_Buf_160_Clk_Jaguar, BIT31, 0x1); +} + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.h old mode 100755 new mode 100644 index 9c3b8b8532a..f61978c9456 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.h @@ -1,48 +1,48 @@ -#ifndef __HAL8814APHYCFG_H__ -#define __HAL8814APHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8814APhyCfg.h - -Abstract: - Defined HAL 8814A PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-05-28 Filen Create. ---*/ - -void -TXPowerTracking_ThermalMeter_Tmp8814A( - IN HAL_PADAPTER Adapter -); - -u4Byte -PHY_QueryRFReg_8814( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -void -PHY_Set_SecCCATH_by_RXANT_8814A( - IN HAL_PADAPTER Adapter, - IN u4Byte ulAntennaRx -); - -void -phy_SpurCalibration_8814A( - IN HAL_PADAPTER Adapter -); - -void -phy_ConfigBB_8814A( - IN HAL_PADAPTER Adapter -); -#endif //__HAL8814APHYCFG_H__ - +#ifndef __HAL8814APHYCFG_H__ +#define __HAL8814APHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8814APhyCfg.h + +Abstract: + Defined HAL 8814A PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-05-28 Filen Create. +--*/ + +void +TXPowerTracking_ThermalMeter_Tmp8814A( + IN HAL_PADAPTER Adapter +); + +u4Byte +PHY_QueryRFReg_8814( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +void +PHY_Set_SecCCATH_by_RXANT_8814A( + IN HAL_PADAPTER Adapter, + IN u4Byte ulAntennaRx +); + +void +phy_SpurCalibration_8814A( + IN HAL_PADAPTER Adapter +); + +void +phy_ConfigBB_8814A( + IN HAL_PADAPTER Adapter +); +#endif //__HAL8814APHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.h old mode 100755 new mode 100644 index e17e765c9e6..21ee6a6c1b2 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.h @@ -1,176 +1,176 @@ -#ifndef REALTEK_POWER_SEQUENCE_8814A -#define REALTEK_POWER_SEQUENCE_8814A - - -/* - Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16 -#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20 -#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17 -#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17 -#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20 -#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8814A_TRANS_END_STEPS 1 - - -#define RTL8814A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \ - {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3|BIT2|BIT1), (BIT3|BIT2|BIT1)},/* 0x14[11:9]=3'b111,OCP current threshold=1.5A */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \ - {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \ - /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ - {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* */ \ - {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x30, 0x20},/* */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ - -#define RTL8814A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \ - /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*Don't turn off XTAL if wlan down or reboot*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8814A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ - {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ - {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */ - -#define RTL8814A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ -#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ - /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ - - -#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \ - /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \ - /*{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},*/ /*PCIe DMA start*/ \ - {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/ - - -#define RTL8814A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8814A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8814A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/ - - -#define RTL8814A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \ - /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8814A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]; - -#endif - +#ifndef REALTEK_POWER_SEQUENCE_8814A +#define REALTEK_POWER_SEQUENCE_8814A + + +/* + Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16 +#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20 +#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17 +#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17 +#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20 +#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8814A_TRANS_END_STEPS 1 + + +#define RTL8814A_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \ + {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3|BIT2|BIT1), (BIT3|BIT2|BIT1)},/* 0x14[11:9]=3'b111,OCP current threshold=1.5A */ \ + {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \ + {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \ + {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \ + /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ + {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* */ \ + {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x30, 0x20},/* */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ + +#define RTL8814A_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ + {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \ + /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ + /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*Don't turn off XTAL if wlan down or reboot*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + +#define RTL8814A_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ + {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ + {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */ + +#define RTL8814A_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ +#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ + /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ + + +#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \ + /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \ + /*{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},*/ /*PCIe DMA start*/ \ + {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/ + + +#define RTL8814A_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8814A_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8814A_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ + {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ + {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/ + + +#define RTL8814A_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \ + /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8814A_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]; + +#endif + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEDef.h old mode 100755 new mode 100644 index 1e821753a8d..d179c1f29e6 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEDef.h @@ -1,125 +1,125 @@ -#ifndef __HAL8814AE_DEF_H__ -#define __HAL8814AE_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8814AEDef.h - -Abstract: - Defined HAL 8814AE data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2013-05-28 Filen Create. ---*/ - - -/*RT_STATUS -InitPON8814AE( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - -RT_STATUS -StopHW8814AE( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -ResetHWForSurprise8814AE( - IN HAL_PADAPTER Adapter -); -*/ - -RT_STATUS -hal_Associate_8814AE( - struct rtl8192cd_priv *priv, - BOOLEAN IsDefaultAdapter -); - -VOID -C2HPacketHandler_8814A( - struct rtl8192cd_priv *priv, - pu1Byte Buffer, - u1Byte Length -); - - -#if (BEAMFORMING_SUPPORT == 1) - -struct _RT_BEAMFORMING_INFO; - -BOOLEAN -beamforming_setiqgen_8814a ( - struct rtl8192cd_priv *priv - ); - +#ifndef __HAL8814AE_DEF_H__ +#define __HAL8814AE_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8814AEDef.h + +Abstract: + Defined HAL 8814AE data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2013-05-28 Filen Create. +--*/ + + +/*RT_STATUS +InitPON8814AE( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + +RT_STATUS +StopHW8814AE( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +ResetHWForSurprise8814AE( + IN HAL_PADAPTER Adapter +); +*/ + +RT_STATUS +hal_Associate_8814AE( + struct rtl8192cd_priv *priv, + BOOLEAN IsDefaultAdapter +); + +VOID +C2HPacketHandler_8814A( + struct rtl8192cd_priv *priv, + pu1Byte Buffer, + u1Byte Length +); + + +#if (BEAMFORMING_SUPPORT == 1) + +struct _RT_BEAMFORMING_INFO; + +BOOLEAN +beamforming_setiqgen_8814a ( + struct rtl8192cd_priv *priv + ); + u1Byte halTxbf8814A_GetNtx( struct rtl8192cd_priv *priv -); - -VOID -SetBeamformRfMode8814A( - struct rtl8192cd_priv *priv, - PRT_BEAMFORMING_INFO pBeamformingInfo, - u1Byte idx -); - -VOID -SetBeamformEnter8814A( - struct rtl8192cd_priv *priv, - u1Byte BFerBFeeIdx -); - -VOID -SetBeamformLeave8814A( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - -VOID -SetBeamformStatus8814A( - struct rtl8192cd_priv *priv, - u1Byte Idx -); - +); + +VOID +SetBeamformRfMode8814A( + struct rtl8192cd_priv *priv, + PRT_BEAMFORMING_INFO pBeamformingInfo, + u1Byte idx +); + +VOID +SetBeamformEnter8814A( + struct rtl8192cd_priv *priv, + u1Byte BFerBFeeIdx +); + +VOID +SetBeamformLeave8814A( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + +VOID +SetBeamformStatus8814A( + struct rtl8192cd_priv *priv, + u1Byte Idx +); + VOID C2HTxBeamformingHandler_8814A( struct rtl8192cd_priv *priv, pu1Byte CmdBuf, u1Byte CmdLen -); - -VOID -Beamforming_NDPARate_8814A( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate -); - -VOID -_C2HContentParsing8814A( - struct rtl8192cd_priv *priv, - u1Byte c2hCmdId, - u1Byte c2hCmdLen, - pu1Byte tmpBuf -); - - -VOID HW_VAR_HW_REG_TIMER_START_8814A(struct rtl8192cd_priv *priv); - -VOID HW_VAR_HW_REG_TIMER_INIT_8814A(struct rtl8192cd_priv *priv, int t); - -VOID HW_VAR_HW_REG_TIMER_STOP_8814A(struct rtl8192cd_priv *priv); - -#endif - - -#endif //__HAL8814AE_DEF_H__ - +); + +VOID +Beamforming_NDPARate_8814A( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate +); + +VOID +_C2HContentParsing8814A( + struct rtl8192cd_priv *priv, + u1Byte c2hCmdId, + u1Byte c2hCmdLen, + pu1Byte tmpBuf +); + + +VOID HW_VAR_HW_REG_TIMER_START_8814A(struct rtl8192cd_priv *priv); + +VOID HW_VAR_HW_REG_TIMER_INIT_8814A(struct rtl8192cd_priv *priv, int t); + +VOID HW_VAR_HW_REG_TIMER_STOP_8814A(struct rtl8192cd_priv *priv); + +#endif + + +#endif //__HAL8814AE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BDef.h old mode 100755 new mode 100644 index 169b301c58f..98c1d5ce673 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BDef.h @@ -1,147 +1,147 @@ -#ifndef __HAL8822B_DEF_H__ -#define __HAL8822B_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8822BDef.h - -Abstract: - Defined HAL 8822B data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015/06/25 Eric Create. ---*/ - -// Test Chip -extern u1Byte *data_AGC_TAB_8822B_start, *data_AGC_TAB_8822B_end; -extern u1Byte *data_MAC_REG_8822B_start, *data_MAC_REG_8822B_end; -extern u1Byte *data_PHY_REG_8822B_start, *data_PHY_REG_8822B_end; -//extern u1Byte *data_PHY_REG_1T_8822B_start, *data_PHY_REG_1T_8822B_end; -extern u1Byte *data_PHY_REG_MP_8822B_start, *data_PHY_REG_MP_8822B_end; -extern u1Byte *data_PHY_REG_PG_8822B_start, *data_PHY_REG_PG_8822B_end; -extern u1Byte *data_RadioA_8822B_start, *data_RadioA_8822B_end; -extern u1Byte *data_RadioB_8822B_start, *data_RadioB_8822B_end; - - -//High Power -#if CFG_HAL_HIGH_POWER_EXT_PA -extern u1Byte *data_AGC_TAB_8822B_hp_start, *data_AGC_TAB_8822B_hp_end; -extern u1Byte *data_PHY_REG_8822B_hp_start, *data_PHY_REG_8822B_hp_end; -extern u1Byte *data_RadioA_8822B_hp_start, *data_RadioA_8822B_hp_end; -extern u1Byte *data_RadioB_8822B_hp_start, *data_RadioB_8822B_hp_end; -#endif - -// FW -extern u1Byte *data_rtl8822Bfw_start, *data_rtl8822Bfw_end; -extern u1Byte *data_rtl8822BfwMP_start, *data_rtl8822BfwMP_end; - -// Power Tracking -extern u1Byte *data_TxPowerTrack_AP_8822B_start, *data_TxPowerTrack_AP_8822B_end; - - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8822B_start, *data_MACDM_def_high_8822B_end; -extern u1Byte *data_MACDM_def_low_8822B_start, *data_MACDM_def_low_8822B_end; -extern u1Byte *data_MACDM_def_normal_8822B_start, *data_MACDM_def_normal_8822B_end; - -//general -extern u1Byte *data_MACDM_gen_high_8822B_start, *data_MACDM_gen_high_8822B_end; -extern u1Byte *data_MACDM_gen_low_8822B_start, *data_MACDM_gen_low_8822B_end; -extern u1Byte *data_MACDM_gen_normal_8822B_start, *data_MACDM_gen_normal_8822B_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8822B_start, *data_MACDM_txop_high_8822B_end; -extern u1Byte *data_MACDM_txop_low_8822B_start, *data_MACDM_txop_low_8822B_end; -extern u1Byte *data_MACDM_txop_normal_8822B_start, *data_MACDM_txop_normal_8822B_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8822B_start, *data_MACDM_state_criteria_8822B_end; - - -// MP chip -extern u1Byte *data_AGC_TAB_8822Bmp_start, *data_AGC_TAB_8822Bmp_end; -extern u1Byte *data_MAC_REG_8822Bmp_start, *data_MAC_REG_8822Bmp_end; -extern u1Byte *data_PHY_REG_8822Bmp_start, *data_PHY_REG_8822Bmp_end; -//extern u1Byte *data_PHY_REG_1T_8822B_start, *data_PHY_REG_1T_8822B_end; -extern u1Byte *data_PHY_REG_MP_8822Bmp_start, *data_PHY_REG_MP_8822Bmp_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_start, *data_PHY_REG_PG_8822Bmp_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type0_start, *data_PHY_REG_PG_8822Bmp_Type0_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type8_start, *data_PHY_REG_PG_8822Bmp_Type8_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type9_start, *data_PHY_REG_PG_8822Bmp_Type9_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type10_start, *data_PHY_REG_PG_8822Bmp_Type10_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type13_start, *data_PHY_REG_PG_8822Bmp_Type13_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type14_start, *data_PHY_REG_PG_8822Bmp_Type14_end; -extern u1Byte *data_RadioA_8822Bmp_start, *data_RadioA_8822Bmp_end; -extern u1Byte *data_RadioB_8822Bmp_start, *data_RadioB_8822Bmp_end; - -//High Power -#if CFG_HAL_HIGH_POWER_EXT_PA -extern u1Byte *data_AGC_TAB_8822Bmp_hp_start, *data_AGC_TAB_8822Bmp_hp_end; -extern u1Byte *data_PHY_REG_8822Bmp_hp_start, *data_PHY_REG_8822Bmp_hp_end; -//extern u1Byte *data_PHY_REG_PG_8822Bmp_hp_start, *data_PHY_REG_PG_8822Bmp_hp_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type1_start, *data_PHY_REG_PG_8822Bmp_Type1_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type4_start, *data_PHY_REG_PG_8822Bmp_Type4_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type6_start, *data_PHY_REG_PG_8822Bmp_Type6_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type7_start, *data_PHY_REG_PG_8822Bmp_Type7_end; -extern u1Byte *data_PHY_REG_PG_8822Bmp_Type11_start, *data_PHY_REG_PG_8822Bmp_Type11_end; -extern u1Byte *data_RadioA_8822Bmp_hp_start, *data_RadioA_8822Bmp_hp_end; -extern u1Byte *data_RadioB_8822Bmp_hp_start, *data_RadioB_8822Bmp_hp_end; -#endif - -// FW -extern u1Byte *data_rtl8822Bfw_start, *data_rtl8822Bfw_end; -extern u1Byte *data_rtl8822BfwMP_start, *data_rtl8822BfwMP_end; - -// Power Tracking -extern u1Byte *data_TxPowerTrack_AP_8822Bmp_start, *data_TxPowerTrack_AP_8822Bmp_end; - -#ifdef TXPWR_LMT_8822B -extern unsigned char *data_TXPWR_LMT_8822Bmp_start, *data_TXPWR_LMT_8822Bmp_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type0_start, *data_TXPWR_LMT_8822Bmp_Type0_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type8_start, *data_TXPWR_LMT_8822Bmp_Type8_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type9_start, *data_TXPWR_LMT_8822Bmp_Type9_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type10_start, *data_TXPWR_LMT_8822Bmp_Type10_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type13_start, *data_TXPWR_LMT_8822Bmp_Type13_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type14_start, *data_TXPWR_LMT_8822Bmp_Type14_end; - -#if CFG_HAL_HIGH_POWER_EXT_PA -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type1_start, *data_TXPWR_LMT_8822Bmp_Type1_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type4_start, *data_TXPWR_LMT_8822Bmp_Type4_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type6_start, *data_TXPWR_LMT_8822Bmp_Type6_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type7_start, *data_TXPWR_LMT_8822Bmp_Type7_end; -extern unsigned char *data_TXPWR_LMT_8822Bmp_Type11_start, *data_TXPWR_LMT_8822Bmp_Type11_end; -#endif -#ifdef BEAMFORMING_AUTO -extern unsigned char *data_TXPWR_LMT_8822Bmp_TXBF_start, *data_TXPWR_LMT_8822Bmp_TXBF_end; -#endif -#endif - - - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8822Bmp_start, *data_MACDM_def_high_8822Bmp_end; -extern u1Byte *data_MACDM_def_low_8822Bmp_start, *data_MACDM_def_low_8822Bmp_end; -extern u1Byte *data_MACDM_def_normal_8822Bmp_start, *data_MACDM_def_normal_8822Bmp_end; - -//general -extern u1Byte *data_MACDM_gen_high_8822Bmp_start, *data_MACDM_gen_high_8822Bmp_end; -extern u1Byte *data_MACDM_gen_low_8822Bmp_start, *data_MACDM_gen_low_8822Bmp_end; -extern u1Byte *data_MACDM_gen_normal_8822Bmp_start, *data_MACDM_gen_normal_8822Bmp_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8822Bmp_start, *data_MACDM_txop_high_8822Bmp_end; -extern u1Byte *data_MACDM_txop_low_8822Bmp_start, *data_MACDM_txop_low_8822Bmp_end; -extern u1Byte *data_MACDM_txop_normal_8822Bmp_start, *data_MACDM_txop_normal_8822Bmp_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8822Bmp_start, *data_MACDM_state_criteria_8822Bmp_end; - -#endif //__HAL8822B_DEF_H__ - - +#ifndef __HAL8822B_DEF_H__ +#define __HAL8822B_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8822BDef.h + +Abstract: + Defined HAL 8822B data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015/06/25 Eric Create. +--*/ + +// Test Chip +extern u1Byte *data_AGC_TAB_8822B_start, *data_AGC_TAB_8822B_end; +extern u1Byte *data_MAC_REG_8822B_start, *data_MAC_REG_8822B_end; +extern u1Byte *data_PHY_REG_8822B_start, *data_PHY_REG_8822B_end; +//extern u1Byte *data_PHY_REG_1T_8822B_start, *data_PHY_REG_1T_8822B_end; +extern u1Byte *data_PHY_REG_MP_8822B_start, *data_PHY_REG_MP_8822B_end; +extern u1Byte *data_PHY_REG_PG_8822B_start, *data_PHY_REG_PG_8822B_end; +extern u1Byte *data_RadioA_8822B_start, *data_RadioA_8822B_end; +extern u1Byte *data_RadioB_8822B_start, *data_RadioB_8822B_end; + + +//High Power +#if CFG_HAL_HIGH_POWER_EXT_PA +extern u1Byte *data_AGC_TAB_8822B_hp_start, *data_AGC_TAB_8822B_hp_end; +extern u1Byte *data_PHY_REG_8822B_hp_start, *data_PHY_REG_8822B_hp_end; +extern u1Byte *data_RadioA_8822B_hp_start, *data_RadioA_8822B_hp_end; +extern u1Byte *data_RadioB_8822B_hp_start, *data_RadioB_8822B_hp_end; +#endif + +// FW +extern u1Byte *data_rtl8822Bfw_start, *data_rtl8822Bfw_end; +extern u1Byte *data_rtl8822BfwMP_start, *data_rtl8822BfwMP_end; + +// Power Tracking +extern u1Byte *data_TxPowerTrack_AP_8822B_start, *data_TxPowerTrack_AP_8822B_end; + + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8822B_start, *data_MACDM_def_high_8822B_end; +extern u1Byte *data_MACDM_def_low_8822B_start, *data_MACDM_def_low_8822B_end; +extern u1Byte *data_MACDM_def_normal_8822B_start, *data_MACDM_def_normal_8822B_end; + +//general +extern u1Byte *data_MACDM_gen_high_8822B_start, *data_MACDM_gen_high_8822B_end; +extern u1Byte *data_MACDM_gen_low_8822B_start, *data_MACDM_gen_low_8822B_end; +extern u1Byte *data_MACDM_gen_normal_8822B_start, *data_MACDM_gen_normal_8822B_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8822B_start, *data_MACDM_txop_high_8822B_end; +extern u1Byte *data_MACDM_txop_low_8822B_start, *data_MACDM_txop_low_8822B_end; +extern u1Byte *data_MACDM_txop_normal_8822B_start, *data_MACDM_txop_normal_8822B_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8822B_start, *data_MACDM_state_criteria_8822B_end; + + +// MP chip +extern u1Byte *data_AGC_TAB_8822Bmp_start, *data_AGC_TAB_8822Bmp_end; +extern u1Byte *data_MAC_REG_8822Bmp_start, *data_MAC_REG_8822Bmp_end; +extern u1Byte *data_PHY_REG_8822Bmp_start, *data_PHY_REG_8822Bmp_end; +//extern u1Byte *data_PHY_REG_1T_8822B_start, *data_PHY_REG_1T_8822B_end; +extern u1Byte *data_PHY_REG_MP_8822Bmp_start, *data_PHY_REG_MP_8822Bmp_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_start, *data_PHY_REG_PG_8822Bmp_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type0_start, *data_PHY_REG_PG_8822Bmp_Type0_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type8_start, *data_PHY_REG_PG_8822Bmp_Type8_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type9_start, *data_PHY_REG_PG_8822Bmp_Type9_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type10_start, *data_PHY_REG_PG_8822Bmp_Type10_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type13_start, *data_PHY_REG_PG_8822Bmp_Type13_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type14_start, *data_PHY_REG_PG_8822Bmp_Type14_end; +extern u1Byte *data_RadioA_8822Bmp_start, *data_RadioA_8822Bmp_end; +extern u1Byte *data_RadioB_8822Bmp_start, *data_RadioB_8822Bmp_end; + +//High Power +#if CFG_HAL_HIGH_POWER_EXT_PA +extern u1Byte *data_AGC_TAB_8822Bmp_hp_start, *data_AGC_TAB_8822Bmp_hp_end; +extern u1Byte *data_PHY_REG_8822Bmp_hp_start, *data_PHY_REG_8822Bmp_hp_end; +//extern u1Byte *data_PHY_REG_PG_8822Bmp_hp_start, *data_PHY_REG_PG_8822Bmp_hp_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type1_start, *data_PHY_REG_PG_8822Bmp_Type1_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type4_start, *data_PHY_REG_PG_8822Bmp_Type4_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type6_start, *data_PHY_REG_PG_8822Bmp_Type6_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type7_start, *data_PHY_REG_PG_8822Bmp_Type7_end; +extern u1Byte *data_PHY_REG_PG_8822Bmp_Type11_start, *data_PHY_REG_PG_8822Bmp_Type11_end; +extern u1Byte *data_RadioA_8822Bmp_hp_start, *data_RadioA_8822Bmp_hp_end; +extern u1Byte *data_RadioB_8822Bmp_hp_start, *data_RadioB_8822Bmp_hp_end; +#endif + +// FW +extern u1Byte *data_rtl8822Bfw_start, *data_rtl8822Bfw_end; +extern u1Byte *data_rtl8822BfwMP_start, *data_rtl8822BfwMP_end; + +// Power Tracking +extern u1Byte *data_TxPowerTrack_AP_8822Bmp_start, *data_TxPowerTrack_AP_8822Bmp_end; + +#ifdef TXPWR_LMT_8822B +extern unsigned char *data_TXPWR_LMT_8822Bmp_start, *data_TXPWR_LMT_8822Bmp_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type0_start, *data_TXPWR_LMT_8822Bmp_Type0_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type8_start, *data_TXPWR_LMT_8822Bmp_Type8_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type9_start, *data_TXPWR_LMT_8822Bmp_Type9_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type10_start, *data_TXPWR_LMT_8822Bmp_Type10_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type13_start, *data_TXPWR_LMT_8822Bmp_Type13_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type14_start, *data_TXPWR_LMT_8822Bmp_Type14_end; + +#if CFG_HAL_HIGH_POWER_EXT_PA +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type1_start, *data_TXPWR_LMT_8822Bmp_Type1_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type4_start, *data_TXPWR_LMT_8822Bmp_Type4_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type6_start, *data_TXPWR_LMT_8822Bmp_Type6_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type7_start, *data_TXPWR_LMT_8822Bmp_Type7_end; +extern unsigned char *data_TXPWR_LMT_8822Bmp_Type11_start, *data_TXPWR_LMT_8822Bmp_Type11_end; +#endif +#ifdef BEAMFORMING_AUTO +extern unsigned char *data_TXPWR_LMT_8822Bmp_TXBF_start, *data_TXPWR_LMT_8822Bmp_TXBF_end; +#endif +#endif + + + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8822Bmp_start, *data_MACDM_def_high_8822Bmp_end; +extern u1Byte *data_MACDM_def_low_8822Bmp_start, *data_MACDM_def_low_8822Bmp_end; +extern u1Byte *data_MACDM_def_normal_8822Bmp_start, *data_MACDM_def_normal_8822Bmp_end; + +//general +extern u1Byte *data_MACDM_gen_high_8822Bmp_start, *data_MACDM_gen_high_8822Bmp_end; +extern u1Byte *data_MACDM_gen_low_8822Bmp_start, *data_MACDM_gen_low_8822Bmp_end; +extern u1Byte *data_MACDM_gen_normal_8822Bmp_start, *data_MACDM_gen_normal_8822Bmp_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8822Bmp_start, *data_MACDM_txop_high_8822Bmp_end; +extern u1Byte *data_MACDM_txop_low_8822Bmp_start, *data_MACDM_txop_low_8822Bmp_end; +extern u1Byte *data_MACDM_txop_normal_8822Bmp_start, *data_MACDM_txop_normal_8822Bmp_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8822Bmp_start, *data_MACDM_state_criteria_8822Bmp_end; + +#endif //__HAL8822B_DEF_H__ + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.h old mode 100755 new mode 100644 index 2880845dc1a..fc3e7e524fb --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BFirmware.h @@ -1,44 +1,44 @@ -#ifndef __HAL8822B_FIRMWARE_H__ -#define __HAL8822B_FIRMWARE_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal88822BFirmware.h - -Abstract: - Defined HAL 8822B Firmware data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-06-25 Eric Create. ---*/ - -#define ctrlInfoSZ_8822 32 - - -typedef struct _Ctrl_Info_8822_ { - u1Byte SGI: 1; - u1Byte Data_Rate: 7; - u1Byte PKT_DROP: 1; - u1Byte TRY_RATE: 1; - u1Byte Rsvd: 1; - u1Byte DATA_BW: 2; - u1Byte PWRSTS: 3; - u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; - u1Byte Rsvd2: 1; - u1Byte GROUP_TABLE_ID: 3; - u1Byte RTY_LOW_RATE_EN: 1; - u1Byte DATA_RTY_LOW_RATE: 7; - u1Byte RTY_LMT_EN: 1; - u1Byte RTS_RT_LOW_RATE: 7; - u1Byte Rsvd3: 1; - u1Byte PKT_TX_ONE_SEL: 1; - u1Byte DATA_RT_LMT: 6; - u1Byte Rsvd4: 8; - u1Byte Rsvd5: 8; -} Ctrl_Info_8822, *PCtrl_Info_8822; - -#endif +#ifndef __HAL8822B_FIRMWARE_H__ +#define __HAL8822B_FIRMWARE_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal88822BFirmware.h + +Abstract: + Defined HAL 8822B Firmware data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-06-25 Eric Create. +--*/ + +#define ctrlInfoSZ_8822 32 + + +typedef struct _Ctrl_Info_8822_ { + u1Byte SGI: 1; + u1Byte Data_Rate: 7; + u1Byte PKT_DROP: 1; + u1Byte TRY_RATE: 1; + u1Byte Rsvd: 1; + u1Byte DATA_BW: 2; + u1Byte PWRSTS: 3; + u1Byte RTY_PKT_1SS_ANT_INFO_EN: 4; + u1Byte Rsvd2: 1; + u1Byte GROUP_TABLE_ID: 3; + u1Byte RTY_LOW_RATE_EN: 1; + u1Byte DATA_RTY_LOW_RATE: 7; + u1Byte RTY_LMT_EN: 1; + u1Byte RTS_RT_LOW_RATE: 7; + u1Byte Rsvd3: 1; + u1Byte PKT_TX_ONE_SEL: 1; + u1Byte DATA_RT_LMT: 6; + u1Byte Rsvd4: 8; + u1Byte Rsvd5: 8; +} Ctrl_Info_8822, *PCtrl_Info_8822; + +#endif diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.c old mode 100755 new mode 100644 index 85b10747438..92a90deefb3 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.c @@ -1,217 +1,217 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8822BPhyCfg.c - -Abstract: - Defined HAL 8822B PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-06-25 Eric Create. ---*/ -#include "HalPrecomp.h" - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8822B( - IN HAL_PADAPTER Adapter -) -{ - // Do Nothing now -} - -u4Byte -PHY_QueryRFReg_8822( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -) -{ - // The phy Query function have bug in 8812 & 8881, must follow the rules as below - // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] - // 2. Before Query RF reg, we must turn off CCA - // 3. delay 10us after set addr - // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB - - HAL_PADAPTER priv = Adapter; - unsigned long flags; - u4Byte Original_Value, Readback_Value, BitShift; - u4Byte temp_CCA; - -#if CFG_HAL_DISABLE_BB_RF - return 0; -#endif //CFG_HAL_DISABLE_BB_RF - -#if 1 //eric-8822 - if(IS_HARDWARE_TYPE_8822BE(Adapter)) { - HAL_SAVE_INT_AND_CLI(flags); - Readback_Value = config_phydm_read_rf_reg_8822b((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask); - HAL_RESTORE_INT(flags); - return Readback_Value; - } -#endif - - HAL_SAVE_INT_AND_CLI(flags); - - u4Byte DataAndAddr = 0; - u4Byte Direct_Addr; - - RegAddr &= 0xff; - switch(eRFPath){ - case RF88XX_PATH_A: - Direct_Addr = 0x2800+RegAddr*4; - break; - case RF88XX_PATH_B: - Direct_Addr = 0x2c00+RegAddr*4; - break; - } - - - BitMask &= bRFRegOffsetMask; - - Readback_Value = PHY_QueryBBReg(Adapter, Direct_Addr, BitMask); - - HAL_RESTORE_INT(flags); - - return (Readback_Value); -} - - -void -PHY_Set_SecCCATH_by_RXANT_8822B( - IN HAL_PADAPTER Adapter, - IN u4Byte ulAntennaRx -) -{ - HAL_PADAPTER priv = Adapter; - //1 Setting CCA TH 2nd CCA parameter by Rx Antenna - if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_80){ - switch(ulAntennaRx){ - case ANTENNA_A: // xT1R - case ANTENNA_B: - case ANTENNA_C: - case ANTENNA_D: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x89); // 0x82C[23:20] = 8, PWDB_TH_QB, 0x82C[19:16] = 9, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x887); // 838[27:24]=8, RF80_secondary40, 838[23:20]=8, RF80_secondary20, 838[19:16]=7, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M - break; - case ANTENNA_AB: // xT2R - case ANTENNA_AC: - //case ANTENNA_AD: - case ANTENNA_BC: - case ANTENNA_BD: - case ANTENNA_CD: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x78); // 0x82C[23:20] = 7, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x444); // 838[27:24]=4, RF80_secondary40, 838[23:20]=4, RF80_secondary20, 838[19:16]=4, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M - break; - case ANTENNA_ABC: // xT3R - //case ANTENNA_ABD: - //case ANTENNA_ACD: - case ANTENNA_BCD: - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M - break; - case ANTENNA_ABCD: // xT4R - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M - break; - default: - panic_printk("Unknown Rx antenna.\n"); - break; - } - }else{ - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x0); // Enable 2ndCCA - PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x43); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB - PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x7aa); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary - PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M - } -} - - -// <20141230, James> A workaround to eliminate the 5280MHz & 5600MHz & 5760MHz spur of 8822B. (Asked by BBSD Neil.) -void -phy_SpurCalibration_8822B( - IN HAL_PADAPTER Adapter -) -{ - BOOLEAN Reset_NBI_CSI = TRUE; - - if(HAL_RFE_TYPE == 0 || HAL_RFE_TYPE == 1 || HAL_RFE_TYPE == 2 || HAL_RFE_TYPE == 3 || HAL_RFE_TYPE == 4){ - if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20 && HAL_VAR_WORKING_CHANNEL == 153){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(16), 1); - Reset_NBI_CSI = FALSE; - }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20_40 && HAL_VAR_WORKING_CHANNEL == 151){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT(16), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - Reset_NBI_CSI = FALSE; - }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_80 && HAL_VAR_WORKING_CHANNEL == 155){ // center ch 155 - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x2d); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT(16), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - Reset_NBI_CSI = FALSE; - } - } - if(HAL_RFE_TYPE == 0){ - switch(HAL_VAR_CURRENTCHANNELBW){ - case HT_CHANNEL_WIDTH_20_40: - if(HAL_VAR_WORKING_CHANNEL == 54 || HAL_VAR_WORKING_CHANNEL == 118){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1f); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT(0), 1); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - Reset_NBI_CSI = FALSE; - } - break; - case HT_CHANNEL_WIDTH_80: // center ch 58, 122 - if(HAL_VAR_WORKING_CHANNEL == 58 || HAL_VAR_WORKING_CHANNEL == 122){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1d); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(0), 1); - Reset_NBI_CSI = FALSE; - } - break; - default: - break; - } - } - if (Reset_NBI_CSI){ - PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x7e); - PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); - } -} - - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8822BPhyCfg.c + +Abstract: + Defined HAL 8822B PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-06-25 Eric Create. +--*/ +#include "HalPrecomp.h" + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8822B( + IN HAL_PADAPTER Adapter +) +{ + // Do Nothing now +} + +u4Byte +PHY_QueryRFReg_8822( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +) +{ + // The phy Query function have bug in 8812 & 8881, must follow the rules as below + // 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0] + // 2. Before Query RF reg, we must turn off CCA + // 3. delay 10us after set addr + // 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + // 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB + + HAL_PADAPTER priv = Adapter; + unsigned long flags; + u4Byte Original_Value, Readback_Value, BitShift; + u4Byte temp_CCA; + +#if CFG_HAL_DISABLE_BB_RF + return 0; +#endif //CFG_HAL_DISABLE_BB_RF + +#if 1 //eric-8822 + if(IS_HARDWARE_TYPE_8822BE(Adapter)) { + HAL_SAVE_INT_AND_CLI(flags); + Readback_Value = config_phydm_read_rf_reg_8822b((&(Adapter->pshare->_dmODM)), eRFPath, RegAddr, BitMask); + HAL_RESTORE_INT(flags); + return Readback_Value; + } +#endif + + HAL_SAVE_INT_AND_CLI(flags); + + u4Byte DataAndAddr = 0; + u4Byte Direct_Addr; + + RegAddr &= 0xff; + switch(eRFPath){ + case RF88XX_PATH_A: + Direct_Addr = 0x2800+RegAddr*4; + break; + case RF88XX_PATH_B: + Direct_Addr = 0x2c00+RegAddr*4; + break; + } + + + BitMask &= bRFRegOffsetMask; + + Readback_Value = PHY_QueryBBReg(Adapter, Direct_Addr, BitMask); + + HAL_RESTORE_INT(flags); + + return (Readback_Value); +} + + +void +PHY_Set_SecCCATH_by_RXANT_8822B( + IN HAL_PADAPTER Adapter, + IN u4Byte ulAntennaRx +) +{ + HAL_PADAPTER priv = Adapter; + //1 Setting CCA TH 2nd CCA parameter by Rx Antenna + if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_80){ + switch(ulAntennaRx){ + case ANTENNA_A: // xT1R + case ANTENNA_B: + case ANTENNA_C: + case ANTENNA_D: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x89); // 0x82C[23:20] = 8, PWDB_TH_QB, 0x82C[19:16] = 9, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x887); // 838[27:24]=8, RF80_secondary40, 838[23:20]=8, RF80_secondary20, 838[19:16]=7, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M + break; + case ANTENNA_AB: // xT2R + case ANTENNA_AC: + //case ANTENNA_AD: + case ANTENNA_BC: + case ANTENNA_BD: + case ANTENNA_CD: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x78); // 0x82C[23:20] = 7, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x444); // 838[27:24]=4, RF80_secondary40, 838[23:20]=4, RF80_secondary20, 838[19:16]=4, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M + break; + case ANTENNA_ABC: // xT3R + //case ANTENNA_ABD: + //case ANTENNA_ACD: + case ANTENNA_BCD: + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x6); //840[15:12]=6, L1_square_Pk_weight_80M + break; + case ANTENNA_ABCD: // xT4R + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x1); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x98); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x666); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M + break; + default: + panic_printk("Unknown Rx antenna.\n"); + break; + } + }else{ + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x00000001, 0x0); // Enable 2ndCCA + PHY_SetBBReg(priv, REG_BB_AGC_TABLE_AC, 0x00FF0000, 0x43); // 0x82C[23:20] = 9, PWDB_TH_QB, 0x82C[19:16] = 8, PWDB_TH_HB + PHY_SetBBReg(priv, REG_BB_CCAONSEC_AC, 0x0FFF0000, 0x7aa); // 838[27:24]=6, RF80_secondary40, 838[23:20]=6, RF80_secondary20, 838[19:16]=6, RF80_primary + PHY_SetBBReg(priv, REG_BB_L1_Weight_Jaguar, 0x0000F000, 0x7); //840[15:12]=7, L1_square_Pk_weight_80M + } +} + + +// <20141230, James> A workaround to eliminate the 5280MHz & 5600MHz & 5760MHz spur of 8822B. (Asked by BBSD Neil.) +void +phy_SpurCalibration_8822B( + IN HAL_PADAPTER Adapter +) +{ + BOOLEAN Reset_NBI_CSI = TRUE; + + if(HAL_RFE_TYPE == 0 || HAL_RFE_TYPE == 1 || HAL_RFE_TYPE == 2 || HAL_RFE_TYPE == 3 || HAL_RFE_TYPE == 4){ + if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20 && HAL_VAR_WORKING_CHANNEL == 153){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(16), 1); + Reset_NBI_CSI = FALSE; + }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_20_40 && HAL_VAR_WORKING_CHANNEL == 151){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0xf); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT(16), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + Reset_NBI_CSI = FALSE; + }else if(HAL_VAR_CURRENTCHANNELBW == HT_CHANNEL_WIDTH_80 && HAL_VAR_WORKING_CHANNEL == 155){ // center ch 155 + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x2d); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT(16), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + Reset_NBI_CSI = FALSE; + } + } + if(HAL_RFE_TYPE == 0){ + switch(HAL_VAR_CURRENTCHANNELBW){ + case HT_CHANNEL_WIDTH_20_40: + if(HAL_VAR_WORKING_CHANNEL == 54 || HAL_VAR_WORKING_CHANNEL == 118){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1f); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT(0), 1); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + Reset_NBI_CSI = FALSE; + } + break; + case HT_CHANNEL_WIDTH_80: // center ch 58, 122 + if(HAL_VAR_WORKING_CHANNEL == 58 || HAL_VAR_WORKING_CHANNEL == 122){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x1d); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 1); // CSI Mask by reg + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT(0), 1); + Reset_NBI_CSI = FALSE; + } + break; + default: + break; + } + } + if (Reset_NBI_CSI){ + PHY_SetBBReg(Adapter, rNBI_Setting_Jaguar, 0x000fe000, 0x7e); + PHY_SetBBReg(Adapter, rCSI_Mask_Setting1_Jaguar, BIT(0), 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask0_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask1_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask6_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + PHY_SetBBReg(Adapter, rCSI_Fix_Mask7_Jaguar, BIT_MASK_SET_MASKDWORD_COMMON, 0); + } +} + + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.h old mode 100755 new mode 100644 index 37a71f744c7..092b24be28f --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPhyCfg.h @@ -1,46 +1,46 @@ -#ifndef __HAL8822BPHYCFG_H__ -#define __HAL8822BPHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8822BPhyCfg.h - -Abstract: - Defined HAL 8822B PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-06-25 Eric Create. ---*/ - -void -TXPowerTracking_ThermalMeter_Tmp8822B( - IN HAL_PADAPTER Adapter -); - -u4Byte -PHY_QueryRFReg_8822( - IN HAL_PADAPTER Adapter, - IN u4Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask -); - -void -PHY_Set_SecCCATH_by_RXANT_8822B( - IN HAL_PADAPTER Adapter, - IN u4Byte ulAntennaRx -); - -void -phy_SpurCalibration_8822B( - IN HAL_PADAPTER Adapter -); - - - -#endif //__HAL8822BPHYCFG_H__ - +#ifndef __HAL8822BPHYCFG_H__ +#define __HAL8822BPHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8822BPhyCfg.h + +Abstract: + Defined HAL 8822B PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-06-25 Eric Create. +--*/ + +void +TXPowerTracking_ThermalMeter_Tmp8822B( + IN HAL_PADAPTER Adapter +); + +u4Byte +PHY_QueryRFReg_8822( + IN HAL_PADAPTER Adapter, + IN u4Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask +); + +void +PHY_Set_SecCCATH_by_RXANT_8822B( + IN HAL_PADAPTER Adapter, + IN u4Byte ulAntennaRx +); + +void +phy_SpurCalibration_8822B( + IN HAL_PADAPTER Adapter +); + + + +#endif //__HAL8822BPHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.h old mode 100755 new mode 100644 index b895a81be51..8de8bd36b99 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/Hal8822BPwrSeqCmd.h @@ -1,212 +1,212 @@ -#ifndef REALTEK_POWER_SEQUENCE_8822B -#define REALTEK_POWER_SEQUENCE_8822B - - -/* - Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8822B_TRANS_CARDEMU_TO_ACT_STEPS 16 -#define RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS 20 -#define RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS 17 -#define RTL8822B_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS 17 -#define RTL8822B_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8822B_TRANS_ACT_TO_LPS_STEPS 20 -#define RTL8822B_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8822B_TRANS_END_STEPS 1 - - -#define RTL8822B_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \ - {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3|BIT2|BIT1), (BIT3|BIT2|BIT1)},/* 0x14[11:9]=3'b111,OCP current threshold=1.5A */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \ - {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \ - /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ - {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* */ \ - {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x30, 0x20},/* */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ - -#define RTL8822B_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \ - /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk =500k */ \ - /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \ - {0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \ - {0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8822B_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0c},\ - {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0E},\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ - {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ - {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */ - -#define RTL8822B_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ - -#define RTL8822B_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ - /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \ - /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},*/ \ - /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},*/ \ - /*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \ - /*{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, gpio 0~7 output same value as input ?? */ \ - /*{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff}, gpio0~7 output mode */ \ - /*{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, 0x47[7:0] = 00 gpio mode */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8822B */ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8822B */ \ - {0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8822B */ \ - {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8822B +2 */ \ - {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ - {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/ - -#define RTL8822B_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \ - /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \ - /*{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},*/ /*PCIe DMA start*/ \ - {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/ - - -#define RTL8822B_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8822B_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8822B_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/ - - -#define RTL8822B_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \ - /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8822B_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8822B_power_on_flow[RTL8822B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_radio_off_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_card_disable_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_card_enable_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_suspend_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_resume_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_hwpdn_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_enter_lps_flow[RTL8822B_TRANS_ACT_TO_LPS_STEPS+RTL8822B_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8822B_leave_lps_flow[RTL8822B_TRANS_LPS_TO_ACT_STEPS+RTL8822B_TRANS_END_STEPS]; - -#endif - +#ifndef REALTEK_POWER_SEQUENCE_8822B +#define REALTEK_POWER_SEQUENCE_8822B + + +/* + Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8822B_TRANS_CARDEMU_TO_ACT_STEPS 16 +#define RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS 20 +#define RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS 17 +#define RTL8822B_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS 17 +#define RTL8822B_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8822B_TRANS_ACT_TO_LPS_STEPS 20 +#define RTL8822B_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8822B_TRANS_END_STEPS 1 + + +#define RTL8822B_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \ + {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3|BIT2|BIT1), (BIT3|BIT2|BIT1)},/* 0x14[11:9]=3'b111,OCP current threshold=1.5A */ \ + {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \ + {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \ + {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \ + /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ + {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* */ \ + {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x30, 0x20},/* */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ + +#define RTL8822B_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ + {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \ + /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk =500k */ \ + /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \ + {0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \ + {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \ + {0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \ + {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + +#define RTL8822B_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0c},\ + {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0E},\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ + {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ + {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ + {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ + {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */ + +#define RTL8822B_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ + +#define RTL8822B_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ + /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \ + /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},*/ \ + /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},*/ \ + /*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \ + /*{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, gpio 0~7 output same value as input ?? */ \ + /*{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff}, gpio0~7 output mode */ \ + /*{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, 0x47[7:0] = 00 gpio mode */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8822B */ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8822B */ \ + {0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8822B */ \ + {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8822B +2 */ \ + {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \ + {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/ + +#define RTL8822B_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \ + {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ + {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \ + /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \ + /*{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},*/ /*PCIe DMA start*/ \ + {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/ + + +#define RTL8822B_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8822B_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8822B_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ + {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \ + {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/ + + +#define RTL8822B_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \ + /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ + {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ + {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8822B_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8822B_power_on_flow[RTL8822B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_radio_off_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_card_disable_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_card_enable_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_suspend_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_resume_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_hwpdn_flow[RTL8822B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8822B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_enter_lps_flow[RTL8822B_TRANS_ACT_TO_LPS_STEPS+RTL8822B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8822B_leave_lps_flow[RTL8822B_TRANS_LPS_TO_ACT_STEPS+RTL8822B_TRANS_END_STEPS]; + +#endif + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEDef.h old mode 100755 new mode 100644 index d33a9a91411..a0c3fc6bde8 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEDef.h @@ -1,112 +1,112 @@ -#ifndef __HAL8822BE_DEF_H__ -#define __HAL8822BE_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8822BEDef.h - -Abstract: - Defined HAL 8822BE data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2015-06-25 Eric Create. ---*/ - - -/*RT_STATUS -InitPON8822BE( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - -RT_STATUS -StopHW8822BE( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS -ResetHWForSurprise8822BE( - IN HAL_PADAPTER Adapter -); -*/ - -RT_STATUS -hal_Associate_8822BE( - struct rtl8192cd_priv *priv, - BOOLEAN IsDefaultAdapter -); - -#if (BEAMFORMING_SUPPORT == 1) -VOID -SetBeamformInit8822B( - struct rtl8192cd_priv *priv - ); - -VOID -SetBeamformEnter8822B( - struct rtl8192cd_priv *priv, - IN u1Byte BFerBFeeIdx - ); - -VOID -SetBeamformLeave8822B( - struct rtl8192cd_priv *priv, - IN u1Byte Idx - ); - -VOID -SetBeamformStatus8822B( - struct rtl8192cd_priv *priv, - IN u1Byte Idx - ); - -void -Beamforming_dym_disable_bf_coeff_8822B( - struct rtl8192cd_priv *priv, - u1Byte enable -); - - -#ifdef CONFIG_VERIWAVE_MU_CHECK -void Beamforming_set_csi_data( - struct rtl8192cd_priv *priv, - int idx, - int reg_idx); -#endif - -void Beamforming_CSIRate_8822B( - struct rtl8192cd_priv *priv -); - - -VOID Beamforming_NDPARate_8822B( - struct rtl8192cd_priv *priv, - BOOLEAN Mode, - u1Byte BW, - u1Byte Rate - ); - - -#if (MU_BEAMFORMING_SUPPORT == 1) -VOID -HalTxbf8822B_ConfigGtab( - struct rtl8192cd_priv *priv - ); -#endif - -VOID -C2HTxBeamformingHandler_8822B( - struct rtl8192cd_priv *priv, - pu1Byte CmdBuf, - u1Byte CmdLen -); -#endif - - -#endif //__HAL8822BE_DEF_H__ - +#ifndef __HAL8822BE_DEF_H__ +#define __HAL8822BE_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8822BEDef.h + +Abstract: + Defined HAL 8822BE data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2015-06-25 Eric Create. +--*/ + + +/*RT_STATUS +InitPON8822BE( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + +RT_STATUS +StopHW8822BE( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS +ResetHWForSurprise8822BE( + IN HAL_PADAPTER Adapter +); +*/ + +RT_STATUS +hal_Associate_8822BE( + struct rtl8192cd_priv *priv, + BOOLEAN IsDefaultAdapter +); + +#if (BEAMFORMING_SUPPORT == 1) +VOID +SetBeamformInit8822B( + struct rtl8192cd_priv *priv + ); + +VOID +SetBeamformEnter8822B( + struct rtl8192cd_priv *priv, + IN u1Byte BFerBFeeIdx + ); + +VOID +SetBeamformLeave8822B( + struct rtl8192cd_priv *priv, + IN u1Byte Idx + ); + +VOID +SetBeamformStatus8822B( + struct rtl8192cd_priv *priv, + IN u1Byte Idx + ); + +void +Beamforming_dym_disable_bf_coeff_8822B( + struct rtl8192cd_priv *priv, + u1Byte enable +); + + +#ifdef CONFIG_VERIWAVE_MU_CHECK +void Beamforming_set_csi_data( + struct rtl8192cd_priv *priv, + int idx, + int reg_idx); +#endif + +void Beamforming_CSIRate_8822B( + struct rtl8192cd_priv *priv +); + + +VOID Beamforming_NDPARate_8822B( + struct rtl8192cd_priv *priv, + BOOLEAN Mode, + u1Byte BW, + u1Byte Rate + ); + + +#if (MU_BEAMFORMING_SUPPORT == 1) +VOID +HalTxbf8822B_ConfigGtab( + struct rtl8192cd_priv *priv + ); +#endif + +VOID +C2HTxBeamformingHandler_8822B( + struct rtl8192cd_priv *priv, + pu1Byte CmdBuf, + u1Byte CmdLen +); +#endif + + +#endif //__HAL8822BE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8822B/RTL8822BE/Hal8822BEGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ACfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ACfg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ADef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ADef.h old mode 100755 new mode 100644 index 60d56326f9e..21ca67ec950 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ADef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ADef.h @@ -1,138 +1,138 @@ -#ifndef __HAL8881A_DEF_H__ -#define __HAL8881A_DEF_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8881ADef.h - -Abstract: - Defined HAL 8881A data structure & Define - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-03-23 Filen Create. ---*/ - - -extern u1Byte *data_AGC_TAB_8881A_start, *data_AGC_TAB_8881A_end; -extern u1Byte *data_MAC_REG_8881A_start, *data_MAC_REG_8881A_end; -extern u1Byte *data_PHY_REG_8881A_start, *data_PHY_REG_8881A_end; -extern u1Byte *data_RadioA_8881A_start, *data_RadioA_8881A_end; -extern u1Byte *data_PHY_REG_PG_8881A_start, *data_PHY_REG_PG_8881A_end; - -/////////////////////////////////////////////////////////// - -extern u1Byte *data_MAC_REG_8881Am_start, *data_MAC_REG_8881Am_end; -extern u1Byte *data_PHY_REG_8881Am_start, *data_PHY_REG_8881Am_end; -extern u1Byte *data_PHY_REG_8881AMP_start, *data_PHY_REG_8881AMP_end; - -extern u1Byte *data_AGC_TAB_8881Am_start, *data_AGC_TAB_8881Am_end; -extern u1Byte *data_AGC_TAB_8881ABP_start, *data_AGC_TAB_8881ABP_end; -#ifdef CONFIG_8881A_2LAYER -extern u1Byte *data_AGC_TAB_8881AMP_2layer_start, *data_AGC_TAB_8881AMP_2layer_end; -#endif -extern u1Byte *data_AGC_TAB_8881AMP_start, *data_AGC_TAB_8881AMP_end; -extern u1Byte *data_AGC_TAB_8881AN_start, *data_AGC_TAB_8881AN_end; -extern u1Byte *data_AGC_TAB_8881ABP_intpa_start, *data_AGC_TAB_8881ABP_intpa_end; -extern u1Byte *data_AGC_TAB_8881AMP_intpa_start, *data_AGC_TAB_8881AMP_intpa_end; -extern u1Byte *data_AGC_TAB_8881AN_extpa_start, *data_AGC_TAB_8881AN_extpa_end; - -extern u1Byte *data_RadioA_8881Am_start, *data_RadioA_8881Am_end; -extern u1Byte *data_RadioA_8881ABP_start, *data_RadioA_8881ABP_end; -extern u1Byte *data_RadioA_8881AMP_start, *data_RadioA_8881AMP_end; -#ifdef CONFIG_8881A_2LAYER -extern u1Byte *data_RadioA_8881AMP_2layer_start, *data_RadioA_8881AMP_2layer_end; -#endif -extern u1Byte *data_RadioA_8881AN_start, *data_RadioA_8881AN_end; -extern u1Byte *data_RadioA_8881ABP_intpa_start, *data_RadioA_8881ABP_intpa_end; -extern u1Byte *data_RadioA_8881AMP_intpa_start, *data_RadioA_8881AMP_intpa_end; -extern u1Byte *data_RadioA_8881AN_extpa_start, *data_RadioA_8881AN_extpa_end; - -extern u1Byte *data_TxPowerTrack_AP_8881A_start, *data_TxPowerTrack_AP_8881A_end; -extern u1Byte *data_TxPowerTrack_AP_8881AMP_start, *data_TxPowerTrack_AP_8881AMP_end; -extern u1Byte *data_TxPowerTrack_AP_8881ABP_start, *data_TxPowerTrack_AP_8881ABP_end; -extern u1Byte *data_TxPowerTrack_AP_8881AN_start, *data_TxPowerTrack_AP_8881AN_end; -extern u1Byte *data_TxPowerTrack_AP_8881AMP_intpa_start, *data_TxPowerTrack_AP_8881AMP_intpa_end; -extern u1Byte *data_TxPowerTrack_AP_8881ABP_intpa_start, *data_TxPowerTrack_AP_8881ABP_intpa_end; -extern u1Byte *data_TxPowerTrack_AP_8881AN_extpa_start, *data_TxPowerTrack_AP_8881AN_extpa_end; - -extern u1Byte *data_PHY_REG_PG_8881Am_start, *data_PHY_REG_PG_8881Am_end; -extern u1Byte *data_PHY_REG_PG_8881A_new_start, *data_PHY_REG_PG_8881A_new_end; -extern u1Byte *data_PHY_REG_PG_8881AMP_start, *data_PHY_REG_PG_8881AMP_end; -extern u1Byte *data_PHY_REG_PG_8881ABP_start, *data_PHY_REG_PG_8881ABP_end; -extern u1Byte *data_PHY_REG_PG_8881AN_start, *data_PHY_REG_PG_8881AN_end; -extern u1Byte *data_PHY_REG_PG_8881AMP_intpa_start, *data_PHY_REG_PG_8881AMP_intpa_end; -extern u1Byte *data_PHY_REG_PG_8881ABP_intpa_start, *data_PHY_REG_PG_8881ABP_intpa_end; -extern u1Byte *data_PHY_REG_PG_8881AN_extpa_start, *data_PHY_REG_PG_8881AN_extpa_end; -#ifdef TXPWR_LMT_8881A -extern unsigned char *data_TXPWR_LMT_8881A_new_start, *data_TXPWR_LMT_8881A_new_end; -extern unsigned char *data_TXPWR_LMT_8881AMP_start, *data_TXPWR_LMT_8881AMP_end; -extern unsigned char *data_TXPWR_LMT_8881ABP_start, *data_TXPWR_LMT_8881ABP_end; -extern unsigned char *data_TXPWR_LMT_8881AN_start, *data_TXPWR_LMT_8881AN_end; -extern unsigned char *data_TXPWR_LMT_8881AMP_intpa_start, *data_TXPWR_LMT_8881AMP_intpa_end; -extern unsigned char *data_TXPWR_LMT_8881ABP_intpa_start, *data_TXPWR_LMT_8881ABP_intpa_end; -extern unsigned char *data_TXPWR_LMT_8881AN_extpa_start, *data_TXPWR_LMT_8881AN_extpa_end; -#endif - -#if 1 //Filen, file below should be updated -extern u1Byte *data_PHY_REG_MP_8881A_start, *data_PHY_REG_MP_8881A_end; -extern u1Byte *data_RTL8881FW_Test_T_start, *data_RTL8881FW_Test_T_end; -extern u1Byte *data_RTL8881TXBUF_Test_T_start, *data_RTL8881TXBUF_Test_T_end; -extern u1Byte *data_RTL8881FW_A_CUT_T_start, *data_RTL8881FW_A_CUT_T_end; -extern u1Byte *data_RTL8881TXBUF_A_CUT_T_start, *data_RTL8881TXBUF_A_CUT_T_end; -#endif - -//3 MACDM -//default -extern u1Byte *data_MACDM_def_high_8881A_start, *data_MACDM_def_high_8881A_end; -extern u1Byte *data_MACDM_def_low_8881A_start, *data_MACDM_def_low_8881A_end; -extern u1Byte *data_MACDM_def_normal_8881A_start, *data_MACDM_def_normal_8881A_end; - -//general -extern u1Byte *data_MACDM_gen_high_8881A_start, *data_MACDM_gen_high_8881A_end; -extern u1Byte *data_MACDM_gen_low_8881A_start, *data_MACDM_gen_low_8881A_end; -extern u1Byte *data_MACDM_gen_normal_8881A_start, *data_MACDM_gen_normal_8881A_end; - -//txop -extern u1Byte *data_MACDM_txop_high_8881A_start, *data_MACDM_txop_high_8881A_end; -extern u1Byte *data_MACDM_txop_low_8881A_start, *data_MACDM_txop_low_8881A_end; -extern u1Byte *data_MACDM_txop_normal_8881A_start, *data_MACDM_txop_normal_8881A_end; - -//criteria -extern u1Byte *data_MACDM_state_criteria_8881A_start, *data_MACDM_state_criteria_8881A_end; - - -RT_STATUS -StopHW8881A( - IN HAL_PADAPTER Adapter -); - - -RT_STATUS +#ifndef __HAL8881A_DEF_H__ +#define __HAL8881A_DEF_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8881ADef.h + +Abstract: + Defined HAL 8881A data structure & Define + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-03-23 Filen Create. +--*/ + + +extern u1Byte *data_AGC_TAB_8881A_start, *data_AGC_TAB_8881A_end; +extern u1Byte *data_MAC_REG_8881A_start, *data_MAC_REG_8881A_end; +extern u1Byte *data_PHY_REG_8881A_start, *data_PHY_REG_8881A_end; +extern u1Byte *data_RadioA_8881A_start, *data_RadioA_8881A_end; +extern u1Byte *data_PHY_REG_PG_8881A_start, *data_PHY_REG_PG_8881A_end; + +/////////////////////////////////////////////////////////// + +extern u1Byte *data_MAC_REG_8881Am_start, *data_MAC_REG_8881Am_end; +extern u1Byte *data_PHY_REG_8881Am_start, *data_PHY_REG_8881Am_end; +extern u1Byte *data_PHY_REG_8881AMP_start, *data_PHY_REG_8881AMP_end; + +extern u1Byte *data_AGC_TAB_8881Am_start, *data_AGC_TAB_8881Am_end; +extern u1Byte *data_AGC_TAB_8881ABP_start, *data_AGC_TAB_8881ABP_end; +#ifdef CONFIG_8881A_2LAYER +extern u1Byte *data_AGC_TAB_8881AMP_2layer_start, *data_AGC_TAB_8881AMP_2layer_end; +#endif +extern u1Byte *data_AGC_TAB_8881AMP_start, *data_AGC_TAB_8881AMP_end; +extern u1Byte *data_AGC_TAB_8881AN_start, *data_AGC_TAB_8881AN_end; +extern u1Byte *data_AGC_TAB_8881ABP_intpa_start, *data_AGC_TAB_8881ABP_intpa_end; +extern u1Byte *data_AGC_TAB_8881AMP_intpa_start, *data_AGC_TAB_8881AMP_intpa_end; +extern u1Byte *data_AGC_TAB_8881AN_extpa_start, *data_AGC_TAB_8881AN_extpa_end; + +extern u1Byte *data_RadioA_8881Am_start, *data_RadioA_8881Am_end; +extern u1Byte *data_RadioA_8881ABP_start, *data_RadioA_8881ABP_end; +extern u1Byte *data_RadioA_8881AMP_start, *data_RadioA_8881AMP_end; +#ifdef CONFIG_8881A_2LAYER +extern u1Byte *data_RadioA_8881AMP_2layer_start, *data_RadioA_8881AMP_2layer_end; +#endif +extern u1Byte *data_RadioA_8881AN_start, *data_RadioA_8881AN_end; +extern u1Byte *data_RadioA_8881ABP_intpa_start, *data_RadioA_8881ABP_intpa_end; +extern u1Byte *data_RadioA_8881AMP_intpa_start, *data_RadioA_8881AMP_intpa_end; +extern u1Byte *data_RadioA_8881AN_extpa_start, *data_RadioA_8881AN_extpa_end; + +extern u1Byte *data_TxPowerTrack_AP_8881A_start, *data_TxPowerTrack_AP_8881A_end; +extern u1Byte *data_TxPowerTrack_AP_8881AMP_start, *data_TxPowerTrack_AP_8881AMP_end; +extern u1Byte *data_TxPowerTrack_AP_8881ABP_start, *data_TxPowerTrack_AP_8881ABP_end; +extern u1Byte *data_TxPowerTrack_AP_8881AN_start, *data_TxPowerTrack_AP_8881AN_end; +extern u1Byte *data_TxPowerTrack_AP_8881AMP_intpa_start, *data_TxPowerTrack_AP_8881AMP_intpa_end; +extern u1Byte *data_TxPowerTrack_AP_8881ABP_intpa_start, *data_TxPowerTrack_AP_8881ABP_intpa_end; +extern u1Byte *data_TxPowerTrack_AP_8881AN_extpa_start, *data_TxPowerTrack_AP_8881AN_extpa_end; + +extern u1Byte *data_PHY_REG_PG_8881Am_start, *data_PHY_REG_PG_8881Am_end; +extern u1Byte *data_PHY_REG_PG_8881A_new_start, *data_PHY_REG_PG_8881A_new_end; +extern u1Byte *data_PHY_REG_PG_8881AMP_start, *data_PHY_REG_PG_8881AMP_end; +extern u1Byte *data_PHY_REG_PG_8881ABP_start, *data_PHY_REG_PG_8881ABP_end; +extern u1Byte *data_PHY_REG_PG_8881AN_start, *data_PHY_REG_PG_8881AN_end; +extern u1Byte *data_PHY_REG_PG_8881AMP_intpa_start, *data_PHY_REG_PG_8881AMP_intpa_end; +extern u1Byte *data_PHY_REG_PG_8881ABP_intpa_start, *data_PHY_REG_PG_8881ABP_intpa_end; +extern u1Byte *data_PHY_REG_PG_8881AN_extpa_start, *data_PHY_REG_PG_8881AN_extpa_end; +#ifdef TXPWR_LMT_8881A +extern unsigned char *data_TXPWR_LMT_8881A_new_start, *data_TXPWR_LMT_8881A_new_end; +extern unsigned char *data_TXPWR_LMT_8881AMP_start, *data_TXPWR_LMT_8881AMP_end; +extern unsigned char *data_TXPWR_LMT_8881ABP_start, *data_TXPWR_LMT_8881ABP_end; +extern unsigned char *data_TXPWR_LMT_8881AN_start, *data_TXPWR_LMT_8881AN_end; +extern unsigned char *data_TXPWR_LMT_8881AMP_intpa_start, *data_TXPWR_LMT_8881AMP_intpa_end; +extern unsigned char *data_TXPWR_LMT_8881ABP_intpa_start, *data_TXPWR_LMT_8881ABP_intpa_end; +extern unsigned char *data_TXPWR_LMT_8881AN_extpa_start, *data_TXPWR_LMT_8881AN_extpa_end; +#endif + +#if 1 //Filen, file below should be updated +extern u1Byte *data_PHY_REG_MP_8881A_start, *data_PHY_REG_MP_8881A_end; +extern u1Byte *data_RTL8881FW_Test_T_start, *data_RTL8881FW_Test_T_end; +extern u1Byte *data_RTL8881TXBUF_Test_T_start, *data_RTL8881TXBUF_Test_T_end; +extern u1Byte *data_RTL8881FW_A_CUT_T_start, *data_RTL8881FW_A_CUT_T_end; +extern u1Byte *data_RTL8881TXBUF_A_CUT_T_start, *data_RTL8881TXBUF_A_CUT_T_end; +#endif + +//3 MACDM +//default +extern u1Byte *data_MACDM_def_high_8881A_start, *data_MACDM_def_high_8881A_end; +extern u1Byte *data_MACDM_def_low_8881A_start, *data_MACDM_def_low_8881A_end; +extern u1Byte *data_MACDM_def_normal_8881A_start, *data_MACDM_def_normal_8881A_end; + +//general +extern u1Byte *data_MACDM_gen_high_8881A_start, *data_MACDM_gen_high_8881A_end; +extern u1Byte *data_MACDM_gen_low_8881A_start, *data_MACDM_gen_low_8881A_end; +extern u1Byte *data_MACDM_gen_normal_8881A_start, *data_MACDM_gen_normal_8881A_end; + +//txop +extern u1Byte *data_MACDM_txop_high_8881A_start, *data_MACDM_txop_high_8881A_end; +extern u1Byte *data_MACDM_txop_low_8881A_start, *data_MACDM_txop_low_8881A_end; +extern u1Byte *data_MACDM_txop_normal_8881A_start, *data_MACDM_txop_normal_8881A_end; + +//criteria +extern u1Byte *data_MACDM_state_criteria_8881A_start, *data_MACDM_state_criteria_8881A_end; + + +RT_STATUS +StopHW8881A( + IN HAL_PADAPTER Adapter +); + + +RT_STATUS hal_Associate_8881A( HAL_PADAPTER Adapter, BOOLEAN IsDefaultAdapter -); - - -RT_STATUS -InitPON8881A( - IN HAL_PADAPTER Adapter, - IN u4Byte ClkSel -); - - - - - - - - - - - - -#endif //__HAL8881A_DEF_H__ +); + + +RT_STATUS +InitPON8881A( + IN HAL_PADAPTER Adapter, + IN u4Byte ClkSel +); + + + + + + + + + + + + +#endif //__HAL8881A_DEF_H__ diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.c old mode 100755 new mode 100644 index bd052261556..84a540e9bf9 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.c +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.c @@ -1,30 +1,30 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8881APhyCfg.c - -Abstract: - Defined HAL 8881A PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ -#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) -#include "HalPrecomp.h" -#else -#include "../../HalPrecomp.h" -#endif - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8881A( - IN HAL_PADAPTER Adapter -) -{ - // Do Nothing now -} - - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8881APhyCfg.c + +Abstract: + Defined HAL 8881A PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ +#if !defined(__ECOS) && !defined(CPTCFG_CFG80211_MODULE) +#include "HalPrecomp.h" +#else +#include "../../HalPrecomp.h" +#endif + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8881A( + IN HAL_PADAPTER Adapter +) +{ + // Do Nothing now +} + + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.h old mode 100755 new mode 100644 index 07c87a5ef57..c002c290766 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.h @@ -1,31 +1,31 @@ -#ifndef __HAL8881APHYCFG_H__ -#define __HAL8881APHYCFG_H__ - -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8881APhyCfg.h - -Abstract: - Defined HAL 88XX PHY BB setting functions - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2012-11-14 Eric Create. ---*/ - - - -// TODO: this function should be modified -void -TXPowerTracking_ThermalMeter_Tmp8881A( - IN HAL_PADAPTER Adapter -); - - - - -#endif // #ifndef __HAL8881APHYCFG_H__ - +#ifndef __HAL8881APHYCFG_H__ +#define __HAL8881APHYCFG_H__ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8881APhyCfg.h + +Abstract: + Defined HAL 88XX PHY BB setting functions + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2012-11-14 Eric Create. +--*/ + + + +// TODO: this function should be modified +void +TXPowerTracking_ThermalMeter_Tmp8881A( + IN HAL_PADAPTER Adapter +); + + + + +#endif // #ifndef __HAL8881APHYCFG_H__ + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.h old mode 100755 new mode 100644 index 94cd15cddf9..38384048e08 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.h @@ -1,134 +1,134 @@ -#ifndef REALTEK_POWER_SEQUENCE_8881A -#define REALTEK_POWER_SEQUENCE_8881A - -/* - Check document WM-20110607-Paul-RTL8881A_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8881A_TRANS_CARDEMU_TO_ACT_STEPS 10 -#define RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS 10 -#define RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS 10 -#define RTL8881A_TRANS_SUS_TO_CARDEMU_STEPS 10 -#define RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS 10 -#define RTL8881A_TRANS_PDN_TO_CARDEMU_STEPS 10 -#define RTL8881A_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8881A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8881A_TRANS_END_STEPS 1 - -#define RTL8881A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x06[0] = 1 */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x04[8] = 1 polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0}, /*wait till 0x04[8] = 0*/ - -#define RTL8881A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, /* 0x02[1:0] = 0 reset BB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - -#define RTL8881A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - -#define RTL8881A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8881A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - -#define RTL8881A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - - -#define RTL8881A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ - -#define RTL8881A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ - -//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step -#define RTL8881A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ - - -#define RTL8881A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8881A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // - - -extern WLAN_PWR_CFG rtl8881A_power_on_flow[RTL8881A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_radio_off_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_card_disable_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_card_enable_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_suspend_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_resume_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_hwpdn_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_enter_lps_flow[RTL8881A_TRANS_ACT_TO_LPS_STEPS+RTL8881A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8881A_leave_lps_flow[RTL8881A_TRANS_LPS_TO_ACT_STEPS+RTL8881A_TRANS_END_STEPS]; - -#endif - +#ifndef REALTEK_POWER_SEQUENCE_8881A +#define REALTEK_POWER_SEQUENCE_8881A + +/* + Check document WM-20110607-Paul-RTL8881A_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8881A_TRANS_CARDEMU_TO_ACT_STEPS 10 +#define RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS 10 +#define RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS 10 +#define RTL8881A_TRANS_SUS_TO_CARDEMU_STEPS 10 +#define RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS 10 +#define RTL8881A_TRANS_PDN_TO_CARDEMU_STEPS 10 +#define RTL8881A_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8881A_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8881A_TRANS_END_STEPS 1 + +#define RTL8881A_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x06[0] = 1 */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x04[8] = 1 polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(0), 0}, /*wait till 0x04[8] = 0*/ + +#define RTL8881A_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, /* 0x02[1:0] = 0 reset BB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + +#define RTL8881A_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ + +#define RTL8881A_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8881A_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ + +#define RTL8881A_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + + +#define RTL8881A_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ + +#define RTL8881A_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ + +//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step +#define RTL8881A_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ + + +#define RTL8881A_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8881A_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8881A_power_on_flow[RTL8881A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_radio_off_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_card_disable_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_card_enable_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_suspend_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_resume_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_hwpdn_flow[RTL8881A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8881A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_enter_lps_flow[RTL8881A_TRANS_ACT_TO_LPS_STEPS+RTL8881A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8881A_leave_lps_flow[RTL8881A_TRANS_LPS_TO_ACT_STEPS+RTL8881A_TRANS_END_STEPS]; + +#endif + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AReg.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AReg.h old mode 100755 new mode 100644 index d3f5a12faa9..8b137891791 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AReg.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AReg.h @@ -1 +1 @@ - + diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.h old mode 100755 new mode 100644 index 4b80e3e813c..8b7e810fe33 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.h @@ -1,35 +1,35 @@ -#ifndef __HAL8881A_TXDESC_H__ -#define __HAL8881A_TXDESC_H__ - - -typedef enum _HCI_DMA_QUEUE_ { -/* - //QoS - HCI_DMA_QUEUE_VO = 0, - HCI_DMA_QUEUE_VI, - HCI_DMA_QUEUE_BE, - HCI_DMA_QUEUE_BK, - - //Beacon / MGT - HCI_DMA_QUEUE_MGT, - HCI_DMA_QUEUE_BCN, - - //HI - HCI_DMA_QUEUE_H0, - HCI_DMA_QUEUE_H1, - HCI_DMA_QUEUE_H2, - HCI_DMA_QUEUE_H3, - HCI_DMA_QUEUE_H4, - HCI_DMA_QUEUE_H5, - HCI_DMA_QUEUE_H6, - HCI_DMA_QUEUE_H7, - - HCI_DMA_QUEUE_MAX_NUM -*/ -}HCI_DMA_QUEUE, *PHCI_DMA_QUEUE; - - - - - +#ifndef __HAL8881A_TXDESC_H__ +#define __HAL8881A_TXDESC_H__ + + +typedef enum _HCI_DMA_QUEUE_ { +/* + //QoS + HCI_DMA_QUEUE_VO = 0, + HCI_DMA_QUEUE_VI, + HCI_DMA_QUEUE_BE, + HCI_DMA_QUEUE_BK, + + //Beacon / MGT + HCI_DMA_QUEUE_MGT, + HCI_DMA_QUEUE_BCN, + + //HI + HCI_DMA_QUEUE_H0, + HCI_DMA_QUEUE_H1, + HCI_DMA_QUEUE_H2, + HCI_DMA_QUEUE_H3, + HCI_DMA_QUEUE_H4, + HCI_DMA_QUEUE_H5, + HCI_DMA_QUEUE_H6, + HCI_DMA_QUEUE_H7, + + HCI_DMA_QUEUE_MAX_NUM +*/ +}HCI_DMA_QUEUE, *PHCI_DMA_QUEUE; + + + + + #endif //#ifndef __HAL8881A_TXDESC_H__ \ No newline at end of file diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.c b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/RTL8881AE/Hal8881AEDef.h b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/RTL8881AE/Hal8881AEDef.h index 5a2b1b2b646..509ff5f9972 100644 --- a/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/RTL8881AE/Hal8881AEDef.h +++ b/package/kernel/rtl8192cd/WlanHAL/RTL88XX/RTL8881A/RTL8881AE/Hal8881AEDef.h @@ -1,27 +1,27 @@ -#ifndef __HAL8881AE_DEF_H__ -#define __HAL8881AE_DEF_H__ - -VOID -C2HPacketHandler_8881A( - struct rtl8192cd_priv *priv, - pu1Byte Buffer, - u1Byte Length -); - +#ifndef __HAL8881AE_DEF_H__ +#define __HAL8881AE_DEF_H__ -#if (BEAMFORMING_SUPPORT == 1) +VOID +C2HPacketHandler_8881A( + struct rtl8192cd_priv *priv, + pu1Byte Buffer, + u1Byte Length +); + + +#if (BEAMFORMING_SUPPORT == 1) VOID SetBeamformEnter8881A( struct rtl8192cd_priv *priv, u1Byte BFerBFeeIdx -); - +); + VOID -SetBeamformLeave8881A( +SetBeamformLeave8881A( struct rtl8192cd_priv *priv, u1Byte Idx -); -#endif - -#endif //__HAL8881AE_DEF_H__ - +); +#endif + +#endif //__HAL8881AE_DEF_H__ + diff --git a/package/kernel/rtl8192cd/Wlan_QoSType.h b/package/kernel/rtl8192cd/Wlan_QoSType.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/Wlan_TypeDef.h b/package/kernel/rtl8192cd/Wlan_TypeDef.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/bin2c.pl b/package/kernel/rtl8192cd/bin2c.pl old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/btcoexist/hal/hal_btc/hal_btc_chip/hal_btc_8197f.c b/package/kernel/rtl8192cd/btcoexist/hal/hal_btc/hal_btc_chip/hal_btc_8197f.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/data/AGC_TAB.txt b/package/kernel/rtl8192cd/data/AGC_TAB.txt index d7ad6528f38..68141056b67 100644 --- a/package/kernel/rtl8192cd/data/AGC_TAB.txt +++ b/package/kernel/rtl8192cd/data/AGC_TAB.txt @@ -1,164 +1,164 @@ -// AGC_TABLE 091118 -0xc78 0x7B000001 //-110 -0xc78 0x7B010001 -0xc78 0x7B020001 -0xc78 0x7B030001 -0xc78 0x7B040001 -0xc78 0x7B050001 //-100 -0xc78 0x7A060001 -0xc78 0x79070001 -0xc78 0x78080001 -0xc78 0x77090001 -0xc78 0x760A0001 //-90 -0xc78 0x750B0001 -0xc78 0x740C0001 -0xc78 0x730D0001 -0xc78 0x720E0001 -0xc78 0x710F0001 //-80 -0xc78 0x70100001 -0xc78 0x6F110001 -0xc78 0x6E120001 -0xc78 0x6D130001 -0xc78 0x6C140001 //-70 -0xc78 0x6B150001 -0xc78 0x6A160001 -0xc78 0x69170001 -0xc78 0x68180001 -0xc78 0x67190001 //-60 -0xc78 0x661A0001 -0xc78 0x651B0001 -0xc78 0x641C0001 -0xc78 0x631D0001 -0xc78 0x621E0001 //-50 -0xc78 0x611F0001 -0xc78 0x60200001 -0xc78 0x49210001 -0xc78 0x48220001 -0xc78 0x47230001 //-40 -0xc78 0x46240001 -0xc78 0x45250001 -0xc78 0x44260001 -0xc78 0x43270001 -0xc78 0x42280001 //-30 -0xc78 0x41290001 -0xc78 0x402A0001 -0xc78 0x262B0001 -0xc78 0x252C0001 -0xc78 0x242D0001 //-20 -0xc78 0x232E0001 -0xc78 0x222F0001 -0xc78 0x21300001 -0xc78 0x20310001 -0xc78 0x06320001 //-10 -0xc78 0x05330001 -0xc78 0x04340001 -0xc78 0x03350001 -0xc78 0x02360001 -0xc78 0x01370001 //0 -0xc78 0x00380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -// AGC_TABLE 2 -0xc78 0x7B400001 //-110 -0xc78 0x7B410001 -0xc78 0x7B420001 -0xc78 0x7B430001 -0xc78 0x7B440001 -0xc78 0x7B450001 //-100 -0xc78 0x7A460001 -0xc78 0x79470001 -0xc78 0x78480001 -0xc78 0x77490001 -0xc78 0x764a0001 //-90 -0xc78 0x754b0001 -0xc78 0x744c0001 -0xc78 0x734d0001 -0xc78 0x724e0001 -0xc78 0x714f0001 //-80 -0xc78 0x70500001 -0xc78 0x6F510001 -0xc78 0x6E520001 -0xc78 0x6D530001 -0xc78 0x6C540001 //-70 -0xc78 0x6B550001 -0xc78 0x6A560001 -0xc78 0x69570001 -0xc78 0x68580001 -0xc78 0x67590001 //-60 -0xc78 0x665a0001 -0xc78 0x655b0001 -0xc78 0x645c0001 -0xc78 0x635d0001 -0xc78 0x625e0001 //-50 -0xc78 0x615f0001 -0xc78 0x60600001 -0xc78 0x49610001 -0xc78 0x48620001 -0xc78 0x47630001 //-40 -0xc78 0x46640001 -0xc78 0x45650001 -0xc78 0x44660001 -0xc78 0x43670001 -0xc78 0x42680001 //-30 -0xc78 0x41690001 -0xc78 0x406a0001 -0xc78 0x266b0001 -0xc78 0x256c0001 -0xc78 0x246d0001 //-20 -0xc78 0x236e0001 -0xc78 0x226f0001 -0xc78 0x21700001 -0xc78 0x20710001 -0xc78 0x06720001 //-10 -0xc78 0x05730001 -0xc78 0x04740001 -0xc78 0x03750001 -0xc78 0x02760001 -0xc78 0x01770001 //0 -0xc78 0x00780001 -0xc78 0x00790001 -0xc78 0x007a0001 -0xc78 0x007b0001 -0xc78 0x007c0001 //10 -0xc78 0x007d0001 -0xc78 0x007e0001 -0xc78 0x007f0001 //16 -// RSSI TABLE -0xc78 0x3800001e -0xc78 0x3801001e -0xc78 0x3802001e -0xc78 0x3803001e -0xc78 0x3804001e -0xc78 0x3805001e -0xc78 0x3806001e -0xc78 0x3807001e -0xc78 0x3808001e //-54 -0xc78 0x3C09001e //-50 -0xc78 0x3E0A001e -0xc78 0x400B001e //-46 -0xc78 0x440C001e //-42 -0xc78 0x480D001e //-38 -0xc78 0x4C0E001e -0xc78 0x500F001e //-30 -0xc78 0x5210001e -0xc78 0x5611001e //-24 -0xc78 0x5A12001e //-20 -0xc78 0x5E13001e -0xc78 0x6014001e //-14 -0xc78 0x6015001e -0xc78 0x6016001e -0xc78 0x6217001e -0xc78 0x6218001e -0xc78 0x6219001e -0xc78 0x621A001e -0xc78 0x621B001e -0xc78 0x621C001e -0xc78 0x621D001e -0xc78 0x621E001e -0xc78 0x621F001e +// AGC_TABLE 091118 +0xc78 0x7B000001 //-110 +0xc78 0x7B010001 +0xc78 0x7B020001 +0xc78 0x7B030001 +0xc78 0x7B040001 +0xc78 0x7B050001 //-100 +0xc78 0x7A060001 +0xc78 0x79070001 +0xc78 0x78080001 +0xc78 0x77090001 +0xc78 0x760A0001 //-90 +0xc78 0x750B0001 +0xc78 0x740C0001 +0xc78 0x730D0001 +0xc78 0x720E0001 +0xc78 0x710F0001 //-80 +0xc78 0x70100001 +0xc78 0x6F110001 +0xc78 0x6E120001 +0xc78 0x6D130001 +0xc78 0x6C140001 //-70 +0xc78 0x6B150001 +0xc78 0x6A160001 +0xc78 0x69170001 +0xc78 0x68180001 +0xc78 0x67190001 //-60 +0xc78 0x661A0001 +0xc78 0x651B0001 +0xc78 0x641C0001 +0xc78 0x631D0001 +0xc78 0x621E0001 //-50 +0xc78 0x611F0001 +0xc78 0x60200001 +0xc78 0x49210001 +0xc78 0x48220001 +0xc78 0x47230001 //-40 +0xc78 0x46240001 +0xc78 0x45250001 +0xc78 0x44260001 +0xc78 0x43270001 +0xc78 0x42280001 //-30 +0xc78 0x41290001 +0xc78 0x402A0001 +0xc78 0x262B0001 +0xc78 0x252C0001 +0xc78 0x242D0001 //-20 +0xc78 0x232E0001 +0xc78 0x222F0001 +0xc78 0x21300001 +0xc78 0x20310001 +0xc78 0x06320001 //-10 +0xc78 0x05330001 +0xc78 0x04340001 +0xc78 0x03350001 +0xc78 0x02360001 +0xc78 0x01370001 //0 +0xc78 0x00380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +// AGC_TABLE 2 +0xc78 0x7B400001 //-110 +0xc78 0x7B410001 +0xc78 0x7B420001 +0xc78 0x7B430001 +0xc78 0x7B440001 +0xc78 0x7B450001 //-100 +0xc78 0x7A460001 +0xc78 0x79470001 +0xc78 0x78480001 +0xc78 0x77490001 +0xc78 0x764a0001 //-90 +0xc78 0x754b0001 +0xc78 0x744c0001 +0xc78 0x734d0001 +0xc78 0x724e0001 +0xc78 0x714f0001 //-80 +0xc78 0x70500001 +0xc78 0x6F510001 +0xc78 0x6E520001 +0xc78 0x6D530001 +0xc78 0x6C540001 //-70 +0xc78 0x6B550001 +0xc78 0x6A560001 +0xc78 0x69570001 +0xc78 0x68580001 +0xc78 0x67590001 //-60 +0xc78 0x665a0001 +0xc78 0x655b0001 +0xc78 0x645c0001 +0xc78 0x635d0001 +0xc78 0x625e0001 //-50 +0xc78 0x615f0001 +0xc78 0x60600001 +0xc78 0x49610001 +0xc78 0x48620001 +0xc78 0x47630001 //-40 +0xc78 0x46640001 +0xc78 0x45650001 +0xc78 0x44660001 +0xc78 0x43670001 +0xc78 0x42680001 //-30 +0xc78 0x41690001 +0xc78 0x406a0001 +0xc78 0x266b0001 +0xc78 0x256c0001 +0xc78 0x246d0001 //-20 +0xc78 0x236e0001 +0xc78 0x226f0001 +0xc78 0x21700001 +0xc78 0x20710001 +0xc78 0x06720001 //-10 +0xc78 0x05730001 +0xc78 0x04740001 +0xc78 0x03750001 +0xc78 0x02760001 +0xc78 0x01770001 //0 +0xc78 0x00780001 +0xc78 0x00790001 +0xc78 0x007a0001 +0xc78 0x007b0001 +0xc78 0x007c0001 //10 +0xc78 0x007d0001 +0xc78 0x007e0001 +0xc78 0x007f0001 //16 +// RSSI TABLE +0xc78 0x3800001e +0xc78 0x3801001e +0xc78 0x3802001e +0xc78 0x3803001e +0xc78 0x3804001e +0xc78 0x3805001e +0xc78 0x3806001e +0xc78 0x3807001e +0xc78 0x3808001e //-54 +0xc78 0x3C09001e //-50 +0xc78 0x3E0A001e +0xc78 0x400B001e //-46 +0xc78 0x440C001e //-42 +0xc78 0x480D001e //-38 +0xc78 0x4C0E001e +0xc78 0x500F001e //-30 +0xc78 0x5210001e +0xc78 0x5611001e //-24 +0xc78 0x5A12001e //-20 +0xc78 0x5E13001e +0xc78 0x6014001e //-14 +0xc78 0x6015001e +0xc78 0x6016001e +0xc78 0x6217001e +0xc78 0x6218001e +0xc78 0x6219001e +0xc78 0x621A001e +0xc78 0x621B001e +0xc78 0x621C001e +0xc78 0x621D001e +0xc78 0x621E001e +0xc78 0x621F001e 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data/AGC_TAB_n_92C.txt b/package/kernel/rtl8192cd/data/AGC_TAB_n_92C.txt old mode 100755 new mode 100644 index d7ad6528f38..68141056b67 --- a/package/kernel/rtl8192cd/data/AGC_TAB_n_92C.txt +++ b/package/kernel/rtl8192cd/data/AGC_TAB_n_92C.txt @@ -1,164 +1,164 @@ -// AGC_TABLE 091118 -0xc78 0x7B000001 //-110 -0xc78 0x7B010001 -0xc78 0x7B020001 -0xc78 0x7B030001 -0xc78 0x7B040001 -0xc78 0x7B050001 //-100 -0xc78 0x7A060001 -0xc78 0x79070001 -0xc78 0x78080001 -0xc78 0x77090001 -0xc78 0x760A0001 //-90 -0xc78 0x750B0001 -0xc78 0x740C0001 -0xc78 0x730D0001 -0xc78 0x720E0001 -0xc78 0x710F0001 //-80 -0xc78 0x70100001 -0xc78 0x6F110001 -0xc78 0x6E120001 -0xc78 0x6D130001 -0xc78 0x6C140001 //-70 -0xc78 0x6B150001 -0xc78 0x6A160001 -0xc78 0x69170001 -0xc78 0x68180001 -0xc78 0x67190001 //-60 -0xc78 0x661A0001 -0xc78 0x651B0001 -0xc78 0x641C0001 -0xc78 0x631D0001 -0xc78 0x621E0001 //-50 -0xc78 0x611F0001 -0xc78 0x60200001 -0xc78 0x49210001 -0xc78 0x48220001 -0xc78 0x47230001 //-40 -0xc78 0x46240001 -0xc78 0x45250001 -0xc78 0x44260001 -0xc78 0x43270001 -0xc78 0x42280001 //-30 -0xc78 0x41290001 -0xc78 0x402A0001 -0xc78 0x262B0001 -0xc78 0x252C0001 -0xc78 0x242D0001 //-20 -0xc78 0x232E0001 -0xc78 0x222F0001 -0xc78 0x21300001 -0xc78 0x20310001 -0xc78 0x06320001 //-10 -0xc78 0x05330001 -0xc78 0x04340001 -0xc78 0x03350001 -0xc78 0x02360001 -0xc78 0x01370001 //0 -0xc78 0x00380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -// AGC_TABLE 2 -0xc78 0x7B400001 //-110 -0xc78 0x7B410001 -0xc78 0x7B420001 -0xc78 0x7B430001 -0xc78 0x7B440001 -0xc78 0x7B450001 //-100 -0xc78 0x7A460001 -0xc78 0x79470001 -0xc78 0x78480001 -0xc78 0x77490001 -0xc78 0x764a0001 //-90 -0xc78 0x754b0001 -0xc78 0x744c0001 -0xc78 0x734d0001 -0xc78 0x724e0001 -0xc78 0x714f0001 //-80 -0xc78 0x70500001 -0xc78 0x6F510001 -0xc78 0x6E520001 -0xc78 0x6D530001 -0xc78 0x6C540001 //-70 -0xc78 0x6B550001 -0xc78 0x6A560001 -0xc78 0x69570001 -0xc78 0x68580001 -0xc78 0x67590001 //-60 -0xc78 0x665a0001 -0xc78 0x655b0001 -0xc78 0x645c0001 -0xc78 0x635d0001 -0xc78 0x625e0001 //-50 -0xc78 0x615f0001 -0xc78 0x60600001 -0xc78 0x49610001 -0xc78 0x48620001 -0xc78 0x47630001 //-40 -0xc78 0x46640001 -0xc78 0x45650001 -0xc78 0x44660001 -0xc78 0x43670001 -0xc78 0x42680001 //-30 -0xc78 0x41690001 -0xc78 0x406a0001 -0xc78 0x266b0001 -0xc78 0x256c0001 -0xc78 0x246d0001 //-20 -0xc78 0x236e0001 -0xc78 0x226f0001 -0xc78 0x21700001 -0xc78 0x20710001 -0xc78 0x06720001 //-10 -0xc78 0x05730001 -0xc78 0x04740001 -0xc78 0x03750001 -0xc78 0x02760001 -0xc78 0x01770001 //0 -0xc78 0x00780001 -0xc78 0x00790001 -0xc78 0x007a0001 -0xc78 0x007b0001 -0xc78 0x007c0001 //10 -0xc78 0x007d0001 -0xc78 0x007e0001 -0xc78 0x007f0001 //16 -// RSSI TABLE -0xc78 0x3800001e -0xc78 0x3801001e -0xc78 0x3802001e -0xc78 0x3803001e -0xc78 0x3804001e -0xc78 0x3805001e -0xc78 0x3806001e -0xc78 0x3807001e -0xc78 0x3808001e //-54 -0xc78 0x3C09001e //-50 -0xc78 0x3E0A001e -0xc78 0x400B001e //-46 -0xc78 0x440C001e //-42 -0xc78 0x480D001e //-38 -0xc78 0x4C0E001e -0xc78 0x500F001e //-30 -0xc78 0x5210001e -0xc78 0x5611001e //-24 -0xc78 0x5A12001e //-20 -0xc78 0x5E13001e -0xc78 0x6014001e //-14 -0xc78 0x6015001e -0xc78 0x6016001e -0xc78 0x6217001e -0xc78 0x6218001e -0xc78 0x6219001e -0xc78 0x621A001e -0xc78 0x621B001e -0xc78 0x621C001e -0xc78 0x621D001e -0xc78 0x621E001e -0xc78 0x621F001e +// AGC_TABLE 091118 +0xc78 0x7B000001 //-110 +0xc78 0x7B010001 +0xc78 0x7B020001 +0xc78 0x7B030001 +0xc78 0x7B040001 +0xc78 0x7B050001 //-100 +0xc78 0x7A060001 +0xc78 0x79070001 +0xc78 0x78080001 +0xc78 0x77090001 +0xc78 0x760A0001 //-90 +0xc78 0x750B0001 +0xc78 0x740C0001 +0xc78 0x730D0001 +0xc78 0x720E0001 +0xc78 0x710F0001 //-80 +0xc78 0x70100001 +0xc78 0x6F110001 +0xc78 0x6E120001 +0xc78 0x6D130001 +0xc78 0x6C140001 //-70 +0xc78 0x6B150001 +0xc78 0x6A160001 +0xc78 0x69170001 +0xc78 0x68180001 +0xc78 0x67190001 //-60 +0xc78 0x661A0001 +0xc78 0x651B0001 +0xc78 0x641C0001 +0xc78 0x631D0001 +0xc78 0x621E0001 //-50 +0xc78 0x611F0001 +0xc78 0x60200001 +0xc78 0x49210001 +0xc78 0x48220001 +0xc78 0x47230001 //-40 +0xc78 0x46240001 +0xc78 0x45250001 +0xc78 0x44260001 +0xc78 0x43270001 +0xc78 0x42280001 //-30 +0xc78 0x41290001 +0xc78 0x402A0001 +0xc78 0x262B0001 +0xc78 0x252C0001 +0xc78 0x242D0001 //-20 +0xc78 0x232E0001 +0xc78 0x222F0001 +0xc78 0x21300001 +0xc78 0x20310001 +0xc78 0x06320001 //-10 +0xc78 0x05330001 +0xc78 0x04340001 +0xc78 0x03350001 +0xc78 0x02360001 +0xc78 0x01370001 //0 +0xc78 0x00380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +// AGC_TABLE 2 +0xc78 0x7B400001 //-110 +0xc78 0x7B410001 +0xc78 0x7B420001 +0xc78 0x7B430001 +0xc78 0x7B440001 +0xc78 0x7B450001 //-100 +0xc78 0x7A460001 +0xc78 0x79470001 +0xc78 0x78480001 +0xc78 0x77490001 +0xc78 0x764a0001 //-90 +0xc78 0x754b0001 +0xc78 0x744c0001 +0xc78 0x734d0001 +0xc78 0x724e0001 +0xc78 0x714f0001 //-80 +0xc78 0x70500001 +0xc78 0x6F510001 +0xc78 0x6E520001 +0xc78 0x6D530001 +0xc78 0x6C540001 //-70 +0xc78 0x6B550001 +0xc78 0x6A560001 +0xc78 0x69570001 +0xc78 0x68580001 +0xc78 0x67590001 //-60 +0xc78 0x665a0001 +0xc78 0x655b0001 +0xc78 0x645c0001 +0xc78 0x635d0001 +0xc78 0x625e0001 //-50 +0xc78 0x615f0001 +0xc78 0x60600001 +0xc78 0x49610001 +0xc78 0x48620001 +0xc78 0x47630001 //-40 +0xc78 0x46640001 +0xc78 0x45650001 +0xc78 0x44660001 +0xc78 0x43670001 +0xc78 0x42680001 //-30 +0xc78 0x41690001 +0xc78 0x406a0001 +0xc78 0x266b0001 +0xc78 0x256c0001 +0xc78 0x246d0001 //-20 +0xc78 0x236e0001 +0xc78 0x226f0001 +0xc78 0x21700001 +0xc78 0x20710001 +0xc78 0x06720001 //-10 +0xc78 0x05730001 +0xc78 0x04740001 +0xc78 0x03750001 +0xc78 0x02760001 +0xc78 0x01770001 //0 +0xc78 0x00780001 +0xc78 0x00790001 +0xc78 0x007a0001 +0xc78 0x007b0001 +0xc78 0x007c0001 //10 +0xc78 0x007d0001 +0xc78 0x007e0001 +0xc78 0x007f0001 //16 +// RSSI TABLE +0xc78 0x3800001e +0xc78 0x3801001e +0xc78 0x3802001e +0xc78 0x3803001e +0xc78 0x3804001e +0xc78 0x3805001e +0xc78 0x3806001e +0xc78 0x3807001e +0xc78 0x3808001e //-54 +0xc78 0x3C09001e //-50 +0xc78 0x3E0A001e +0xc78 0x400B001e //-46 +0xc78 0x440C001e //-42 +0xc78 0x480D001e //-38 +0xc78 0x4C0E001e +0xc78 0x500F001e //-30 +0xc78 0x5210001e +0xc78 0x5611001e //-24 +0xc78 0x5A12001e //-20 +0xc78 0x5E13001e +0xc78 0x6014001e //-14 +0xc78 0x6015001e +0xc78 0x6016001e +0xc78 0x6217001e +0xc78 0x6218001e +0xc78 0x6219001e +0xc78 0x621A001e +0xc78 0x621B001e +0xc78 0x621C001e +0xc78 0x621D001e +0xc78 0x621E001e +0xc78 0x621F001e 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data/AGC_TAB_n_hp.txt b/package/kernel/rtl8192cd/data/AGC_TAB_n_hp.txt old mode 100755 new mode 100644 index d9e134f789e..d7ab8b78952 --- a/package/kernel/rtl8192cd/data/AGC_TAB_n_hp.txt +++ b/package/kernel/rtl8192cd/data/AGC_TAB_n_hp.txt @@ -1,164 +1,164 @@ -// AGC_TABLE 091118 -0xc78 0x7B000001 //-110 -0xc78 0x7B010001 -0xc78 0x7B020001 -0xc78 0x7B030001 -0xc78 0x7B040001 -0xc78 0x7B050001 //-100 -0xc78 0x7b060001 -0xc78 0x7b070001 -0xc78 0x7b080001 -0xc78 0x7a090001 -0xc78 0x790A0001 //-90 -0xc78 0x780B0001 -0xc78 0x770C0001 -0xc78 0x760D0001 -0xc78 0x750E0001 -0xc78 0x740F0001 //-80 -0xc78 0x73100001 -0xc78 0x72110001 -0xc78 0x71120001 -0xc78 0x70130001 -0xc78 0x6f140001 //-70 -0xc78 0x6e150001 -0xc78 0x6d160001 -0xc78 0x6c170001 -0xc78 0x6b180001 -0xc78 0x6a190001 //-60 -0xc78 0x691A0001 -0xc78 0x681B0001 -0xc78 0x671C0001 -0xc78 0x661D0001 -0xc78 0x651E0001 //-50 -0xc78 0x641F0001 -0xc78 0x63200001 -0xc78 0x62210001 -0xc78 0x61220001 -0xc78 0x60230001 //-40 -0xc78 0x46240001 -0xc78 0x45250001 -0xc78 0x44260001 -0xc78 0x43270001 -0xc78 0x42280001 //-30 -0xc78 0x41290001 -0xc78 0x402A0001 -0xc78 0x262B0001 -0xc78 0x252C0001 -0xc78 0x242D0001 //-20 -0xc78 0x232E0001 -0xc78 0x222F0001 -0xc78 0x21300001 -0xc78 0x20310001 -0xc78 0x06320001 //-10 -0xc78 0x05330001 -0xc78 0x04340001 -0xc78 0x03350001 -0xc78 0x02360001 -0xc78 0x01370001 //0 -0xc78 0x00380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -// AGC_TABLE 2 -0xc78 0x7B400001 //-110 -0xc78 0x7B410001 -0xc78 0x7B420001 -0xc78 0x7B430001 -0xc78 0x7B440001 -0xc78 0x7B450001 //-100 -0xc78 0x7b460001 -0xc78 0x7b470001 -0xc78 0x7b480001 -0xc78 0x7a490001 -0xc78 0x794a0001 //-90 -0xc78 0x784b0001 -0xc78 0x774c0001 -0xc78 0x764d0001 -0xc78 0x754e0001 -0xc78 0x744f0001 //-80 -0xc78 0x73500001 -0xc78 0x72510001 -0xc78 0x71520001 -0xc78 0x70530001 -0xc78 0x6f540001 //-70 -0xc78 0x6e550001 -0xc78 0x6d560001 -0xc78 0x6c570001 -0xc78 0x6b580001 -0xc78 0x6a590001 //-60 -0xc78 0x695a0001 -0xc78 0x685b0001 -0xc78 0x675c0001 -0xc78 0x665d0001 -0xc78 0x655e0001 //-50 -0xc78 0x645f0001 -0xc78 0x63600001 -0xc78 0x62610001 -0xc78 0x61620001 -0xc78 0x60630001 //-40 -0xc78 0x46640001 -0xc78 0x45650001 -0xc78 0x44660001 -0xc78 0x43670001 -0xc78 0x42680001 //-30 -0xc78 0x41690001 -0xc78 0x406a0001 -0xc78 0x266b0001 -0xc78 0x256c0001 -0xc78 0x246d0001 //-20 -0xc78 0x236e0001 -0xc78 0x226f0001 -0xc78 0x21700001 -0xc78 0x20710001 -0xc78 0x06720001 //-10 -0xc78 0x05730001 -0xc78 0x04740001 -0xc78 0x03750001 -0xc78 0x02760001 -0xc78 0x01770001 //0 -0xc78 0x00780001 -0xc78 0x00790001 -0xc78 0x007a0001 -0xc78 0x007b0001 -0xc78 0x007c0001 //10 -0xc78 0x007d0001 -0xc78 0x007e0001 -0xc78 0x007f0001 //16 -// RSSI TABLE -0xc78 0x3800001e -0xc78 0x3801001e -0xc78 0x3802001e -0xc78 0x3803001e -0xc78 0x3804001e -0xc78 0x3805001e -0xc78 0x3806001e -0xc78 0x3807001e -0xc78 0x3808001e //-54 -0xc78 0x3C09001e //-50 -0xc78 0x3E0A001e -0xc78 0x400B001e //-46 -0xc78 0x440C001e //-42 -0xc78 0x480D001e //-38 -0xc78 0x4C0E001e -0xc78 0x500F001e //-30 -0xc78 0x5210001e -0xc78 0x5611001e //-24 -0xc78 0x5A12001e //-20 -0xc78 0x5E13001e -0xc78 0x6014001e //-14 -0xc78 0x6015001e -0xc78 0x6016001e -0xc78 0x6217001e -0xc78 0x6218001e -0xc78 0x6219001e -0xc78 0x621A001e -0xc78 0x621B001e -0xc78 0x621C001e -0xc78 0x621D001e -0xc78 0x621E001e -0xc78 0x621F001e +// AGC_TABLE 091118 +0xc78 0x7B000001 //-110 +0xc78 0x7B010001 +0xc78 0x7B020001 +0xc78 0x7B030001 +0xc78 0x7B040001 +0xc78 0x7B050001 //-100 +0xc78 0x7b060001 +0xc78 0x7b070001 +0xc78 0x7b080001 +0xc78 0x7a090001 +0xc78 0x790A0001 //-90 +0xc78 0x780B0001 +0xc78 0x770C0001 +0xc78 0x760D0001 +0xc78 0x750E0001 +0xc78 0x740F0001 //-80 +0xc78 0x73100001 +0xc78 0x72110001 +0xc78 0x71120001 +0xc78 0x70130001 +0xc78 0x6f140001 //-70 +0xc78 0x6e150001 +0xc78 0x6d160001 +0xc78 0x6c170001 +0xc78 0x6b180001 +0xc78 0x6a190001 //-60 +0xc78 0x691A0001 +0xc78 0x681B0001 +0xc78 0x671C0001 +0xc78 0x661D0001 +0xc78 0x651E0001 //-50 +0xc78 0x641F0001 +0xc78 0x63200001 +0xc78 0x62210001 +0xc78 0x61220001 +0xc78 0x60230001 //-40 +0xc78 0x46240001 +0xc78 0x45250001 +0xc78 0x44260001 +0xc78 0x43270001 +0xc78 0x42280001 //-30 +0xc78 0x41290001 +0xc78 0x402A0001 +0xc78 0x262B0001 +0xc78 0x252C0001 +0xc78 0x242D0001 //-20 +0xc78 0x232E0001 +0xc78 0x222F0001 +0xc78 0x21300001 +0xc78 0x20310001 +0xc78 0x06320001 //-10 +0xc78 0x05330001 +0xc78 0x04340001 +0xc78 0x03350001 +0xc78 0x02360001 +0xc78 0x01370001 //0 +0xc78 0x00380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +// AGC_TABLE 2 +0xc78 0x7B400001 //-110 +0xc78 0x7B410001 +0xc78 0x7B420001 +0xc78 0x7B430001 +0xc78 0x7B440001 +0xc78 0x7B450001 //-100 +0xc78 0x7b460001 +0xc78 0x7b470001 +0xc78 0x7b480001 +0xc78 0x7a490001 +0xc78 0x794a0001 //-90 +0xc78 0x784b0001 +0xc78 0x774c0001 +0xc78 0x764d0001 +0xc78 0x754e0001 +0xc78 0x744f0001 //-80 +0xc78 0x73500001 +0xc78 0x72510001 +0xc78 0x71520001 +0xc78 0x70530001 +0xc78 0x6f540001 //-70 +0xc78 0x6e550001 +0xc78 0x6d560001 +0xc78 0x6c570001 +0xc78 0x6b580001 +0xc78 0x6a590001 //-60 +0xc78 0x695a0001 +0xc78 0x685b0001 +0xc78 0x675c0001 +0xc78 0x665d0001 +0xc78 0x655e0001 //-50 +0xc78 0x645f0001 +0xc78 0x63600001 +0xc78 0x62610001 +0xc78 0x61620001 +0xc78 0x60630001 //-40 +0xc78 0x46640001 +0xc78 0x45650001 +0xc78 0x44660001 +0xc78 0x43670001 +0xc78 0x42680001 //-30 +0xc78 0x41690001 +0xc78 0x406a0001 +0xc78 0x266b0001 +0xc78 0x256c0001 +0xc78 0x246d0001 //-20 +0xc78 0x236e0001 +0xc78 0x226f0001 +0xc78 0x21700001 +0xc78 0x20710001 +0xc78 0x06720001 //-10 +0xc78 0x05730001 +0xc78 0x04740001 +0xc78 0x03750001 +0xc78 0x02760001 +0xc78 0x01770001 //0 +0xc78 0x00780001 +0xc78 0x00790001 +0xc78 0x007a0001 +0xc78 0x007b0001 +0xc78 0x007c0001 //10 +0xc78 0x007d0001 +0xc78 0x007e0001 +0xc78 0x007f0001 //16 +// RSSI TABLE +0xc78 0x3800001e +0xc78 0x3801001e +0xc78 0x3802001e +0xc78 0x3803001e +0xc78 0x3804001e +0xc78 0x3805001e +0xc78 0x3806001e +0xc78 0x3807001e +0xc78 0x3808001e //-54 +0xc78 0x3C09001e //-50 +0xc78 0x3E0A001e +0xc78 0x400B001e //-46 +0xc78 0x440C001e //-42 +0xc78 0x480D001e //-38 +0xc78 0x4C0E001e +0xc78 0x500F001e //-30 +0xc78 0x5210001e +0xc78 0x5611001e //-24 +0xc78 0x5A12001e //-20 +0xc78 0x5E13001e +0xc78 0x6014001e //-14 +0xc78 0x6015001e +0xc78 0x6016001e +0xc78 0x6217001e +0xc78 0x6218001e +0xc78 0x6219001e +0xc78 0x621A001e +0xc78 0x621B001e +0xc78 0x621C001e +0xc78 0x621D001e +0xc78 0x621E001e +0xc78 0x621F001e 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data/MACPHY_REG_92C.txt b/package/kernel/rtl8192cd/data/MACPHY_REG_92C.txt old mode 100755 new mode 100644 index 88425bc5c1c..6381fea76a2 --- a/package/kernel/rtl8192cd/data/MACPHY_REG_92C.txt +++ b/package/kernel/rtl8192cd/data/MACPHY_REG_92C.txt @@ -1,111 +1,111 @@ -//version 09 modify: -//1. set port 2 MACID and BSSID initial value -//2. set NAV upper limit -//3. disable TX ACQ over beacon time - -//TX and RX packet buffer init, this is done before MAC TRX register init, the following -// register setting is done in Power on flow - -//0x200 0x29 //RQPN -//0x201 0x29 -//0x202 0xA3 -//0x203 0x80 -//0x10C 0x71 // for normal chip setting -//0x10D 0xF7 //HPQ_SEL mapping for Normal chip -//0x114 0xF6 //TXRKTBUG_PG_BNDY -//0x209 0xF6 //Beacon Head Page -//0x115 0x00 -//0x116 0xFF -//0x117 0x27 -//0x424 0xF6 //BCNQ_PGBNDY -//0x45D 0xF6 //WMAC_LBK_BF_HD -//0x60F 0x04 //enable PHY status RCR[28] = 1, 0x60F = 0x04 - -//EDCA and WMAC related -0x420 0x80 //0x420[7] = 1 BK_AMPDU_RTY_NEW -0x423 0x00 -0x430 0x00 //DARFRC, AS 92S -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 //DARFRC, AS 92S -0x435 0x05 -0x436 0x06 -0x437 0x07 -0x438 0x00 //RARFRC, AS 92S -0x439 0x00 -0x43A 0x00 -0x43B 0x01 -0x43C 0x04 //RARFRC, AS 92S -0x43D 0x05 -0x43E 0x06 -0x43F 0x07 -0x440 0x5F //RRSR -0x441 0x01 -0x442 0x00 -0x444 0x15 // -0x445 0xF0 -0x446 0x0F -0x447 0x00 -0x458 0x41 //AGG_LMT -0x459 0xa8 //a8 -0x45A 0x72 //82 -0x45B 0xb9 //b9 -0x460 0x66 -0x461 0x66 -0x462 0x08 -0x463 0x03 -0x4C8 0xff //PROT_MODE_CTRL need tuning -0x4C9 0x08 -0x4CC 0xff //Disable BAR retry need tuning -0x4CD 0xff -0x4CE 0x01 -0x500 0x26 //VO EDCA -0x501 0xA2 -0x502 0x2f -0x503 0x00 -0x504 0x28 //VI EDCA -0x505 0xA3 -0x506 0x5E -0x507 0x00 -0x508 0x2B //BE -0x509 0xA4 -0x50A 0x5E -0x50B 0x00 -0x50c 0x4f //BK EDCA -0x50D 0xA4 -0x50E 0x00 -0x50F 0x00 -0x512 0x1C //PIFS -0x514 0x0a -0x515 0x10 -0x516 0x0a -0x517 0x10 -0x51A 0x16 //AGGR_BK_TIME -0x524 0x0F -0x525 0x4F //disable CFE -0x546 0x20 // NAC_PROT_LEN -0x547 0x00 -0x550 0x10 // disable auto sync, and initially disable all beacon function, disable beacon update -0x551 0x10 -0x559 0x02 //BCNDMATIM -0x55A 0x02 //ATIMWND -0x55D 0xFF //disable BCN MAX threshold -0x605 0x30 // enable TX deadlock -0x608 0x0E //RCR -0x609 0x2A //RCR+1 -0x652 0xC8 // enable NAV update upper bound -0x63C 0x08 -0x63D 0x08 -0x63E 0x0C -0x63F 0x0C -0x66E 0x05 // RX BAR IOT issue for Atheros NIC, where atheros BAR has bug -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 - +//version 09 modify: +//1. set port 2 MACID and BSSID initial value +//2. set NAV upper limit +//3. disable TX ACQ over beacon time + +//TX and RX packet buffer init, this is done before MAC TRX register init, the following +// register setting is done in Power on flow + +//0x200 0x29 //RQPN +//0x201 0x29 +//0x202 0xA3 +//0x203 0x80 +//0x10C 0x71 // for normal chip setting +//0x10D 0xF7 //HPQ_SEL mapping for Normal chip +//0x114 0xF6 //TXRKTBUG_PG_BNDY +//0x209 0xF6 //Beacon Head Page +//0x115 0x00 +//0x116 0xFF +//0x117 0x27 +//0x424 0xF6 //BCNQ_PGBNDY +//0x45D 0xF6 //WMAC_LBK_BF_HD +//0x60F 0x04 //enable PHY status RCR[28] = 1, 0x60F = 0x04 + +//EDCA and WMAC related +0x420 0x80 //0x420[7] = 1 BK_AMPDU_RTY_NEW +0x423 0x00 +0x430 0x00 //DARFRC, AS 92S +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 //DARFRC, AS 92S +0x435 0x05 +0x436 0x06 +0x437 0x07 +0x438 0x00 //RARFRC, AS 92S +0x439 0x00 +0x43A 0x00 +0x43B 0x01 +0x43C 0x04 //RARFRC, AS 92S +0x43D 0x05 +0x43E 0x06 +0x43F 0x07 +0x440 0x5F //RRSR +0x441 0x01 +0x442 0x00 +0x444 0x15 // +0x445 0xF0 +0x446 0x0F +0x447 0x00 +0x458 0x41 //AGG_LMT +0x459 0xa8 //a8 +0x45A 0x72 //82 +0x45B 0xb9 //b9 +0x460 0x66 +0x461 0x66 +0x462 0x08 +0x463 0x03 +0x4C8 0xff //PROT_MODE_CTRL need tuning +0x4C9 0x08 +0x4CC 0xff //Disable BAR retry need tuning +0x4CD 0xff +0x4CE 0x01 +0x500 0x26 //VO EDCA +0x501 0xA2 +0x502 0x2f +0x503 0x00 +0x504 0x28 //VI EDCA +0x505 0xA3 +0x506 0x5E +0x507 0x00 +0x508 0x2B //BE +0x509 0xA4 +0x50A 0x5E +0x50B 0x00 +0x50c 0x4f //BK EDCA +0x50D 0xA4 +0x50E 0x00 +0x50F 0x00 +0x512 0x1C //PIFS +0x514 0x0a +0x515 0x10 +0x516 0x0a +0x517 0x10 +0x51A 0x16 //AGGR_BK_TIME +0x524 0x0F +0x525 0x4F //disable CFE +0x546 0x20 // NAC_PROT_LEN +0x547 0x00 +0x550 0x10 // disable auto sync, and initially disable all beacon function, disable beacon update +0x551 0x10 +0x559 0x02 //BCNDMATIM +0x55A 0x02 //ATIMWND +0x55D 0xFF //disable BCN MAX threshold +0x605 0x30 // enable TX deadlock +0x608 0x0E //RCR +0x609 0x2A //RCR+1 +0x652 0xC8 // enable NAV update upper bound +0x63C 0x08 +0x63D 0x08 +0x63E 0x0C +0x63F 0x0C +0x66E 0x05 // RX BAR IOT issue for Atheros NIC, where atheros BAR has bug +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 + diff --git a/package/kernel/rtl8192cd/data/PHY_REG_1T.txt b/package/kernel/rtl8192cd/data/PHY_REG_1T.txt old mode 100755 new mode 100644 index e5e986bbc74..c0122843feb --- a/package/kernel/rtl8192cd/data/PHY_REG_1T.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_1T.txt @@ -1,244 +1,244 @@ -//091204 -//0x024 0x11800f //syn CLK enable // tmp 40MHz solution -//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000001 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10000330 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x65a965a9 -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x0f7f0230 //88CE default left anatenna -0x864 0x0f7f0130 -0x868 0x00000000 -0x86c 0x00323232 //Path-A 2M/5.5M/11M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x00004000 // -0x878 0x00000808 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc00004 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000000 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0xc1ff000c -0xa08 0x8c038300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e62120f -0xa10 0x95009b78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf80 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -0xb00 0x01017018 -0xb04 0xf7ed8f84 -0xb08 0x40372d20 -0xb0c 0x5b554e48 -0xb10 0x6f6a6560 -0xb14 0x807c7873 -0xb18 0x8f8b8884 -0xb1c 0x9d999693 -0xb20 0xa9a6a3a0 -0xb24 0xb5b2afac -0xb28 0x00810100 -0xb2c 0x00400056 -0xb30 0x002b0032 -0xb34 0x001f0024 -0xb38 0x0019001c -0xb3c 0x00150017 -0xb40 0x00120013 -0xb44 0x00100011 -0xb48 0x000e000f -0xb4c 0x000c000d -0xb50 0x000b000c -0xb54 0x000a000b -0xb58 0x0009000a -0xb5c 0x00090009 -0xb60 0x00080008 -0xb64 0x00080008 -0xb68 0x0fe00000 -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac4a // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a979718 -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x433c0094 -0xc58 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00000000 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00000000 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000000 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020401 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03002a2a // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -//0xe60 0x021400a0 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//091204 +//0x024 0x11800f //syn CLK enable // tmp 40MHz solution +//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 +0x804 0x00000001 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10000330 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x00000000 +0x82c 0x00000000 +0x830 0x00000000 +0x834 0x00000000 +0x838 0x00000000 +0x83c 0x00000000 +0x840 0x00010000 //RF to standby mode +0x844 0x00000000 +0x848 0x00000000 +0x84c 0x00000000 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x65a965a9 +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x0f7f0230 //88CE default left anatenna +0x864 0x0f7f0130 +0x868 0x00000000 +0x86c 0x00323232 //Path-A 2M/5.5M/11M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x00004000 // +0x878 0x00000808 // RF mode for standby & rx_low_power codeword +0x87c 0x00000000 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xccc00004 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000000 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121111 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0xc1ff000c +0xa08 0x8c038300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e62120f +0xa10 0x95009b78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf80 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +0xb00 0x01017018 +0xb04 0xf7ed8f84 +0xb08 0x40372d20 +0xb0c 0x5b554e48 +0xb10 0x6f6a6560 +0xb14 0x807c7873 +0xb18 0x8f8b8884 +0xb1c 0x9d999693 +0xb20 0xa9a6a3a0 +0xb24 0xb5b2afac +0xb28 0x00810100 +0xb2c 0x00400056 +0xb30 0x002b0032 +0xb34 0x001f0024 +0xb38 0x0019001c +0xb3c 0x00150017 +0xb40 0x00120013 +0xb44 0x00100011 +0xb48 0x000e000f +0xb4c 0x000c000d +0xb50 0x000b000c +0xb54 0x000a000b +0xb58 0x0009000a +0xb5c 0x00090009 +0xb60 0x00080008 +0xb64 0x00080008 +0xb68 0x0fe00000 +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05611 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac4a // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a979718 +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x433c0094 +0xc58 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00000000 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00000000 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000000 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020401 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03002a2a // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +//0xe60 0x021400a0 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_1T_n.txt b/package/kernel/rtl8192cd/data/PHY_REG_1T_n.txt old mode 100755 new mode 100644 index f66c0cb17d5..fa83cac9be3 --- a/package/kernel/rtl8192cd/data/PHY_REG_1T_n.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_1T_n.txt @@ -1,221 +1,221 @@ -//100311 -//0x024 0x11800f //syn CLK enable // tmp 40MHz solution -//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution - - -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000001 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10000330 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x001b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60230 //88CE default left anatenna -0x864 0x061f0130 -0x868 0x00000000 -0x86c 0x32323200 //Path-A 11M/5.5M/2M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22004000 // -0x878 0x00000808 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc0094 -0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020401 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 -0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//100311 +//0x024 0x11800f //syn CLK enable // tmp 40MHz solution +//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution + + +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 +0x804 0x00000001 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10000330 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x00000000 +0x82c 0x00000000 +0x830 0x00000000 +0x834 0x00000000 +0x838 0x00000000 +0x83c 0x00000000 +0x840 0x00010000 //RF to standby mode +0x844 0x00000000 +0x848 0x00000000 +0x84c 0x00000000 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x001b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60230 //88CE default left anatenna +0x864 0x061f0130 +0x868 0x00000000 +0x86c 0x32323200 //Path-A 11M/5.5M/2M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22004000 // +0x878 0x00000808 // RF mode for standby & rx_low_power codeword +0x87c 0x00000000 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121111 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05611 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x43bc0094 +0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020401 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 +0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_1T_n_hp.txt b/package/kernel/rtl8192cd/data/PHY_REG_1T_n_hp.txt old mode 100755 new mode 100644 index c3344332708..320ed6a01e3 --- a/package/kernel/rtl8192cd/data/PHY_REG_1T_n_hp.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_1T_n_hp.txt @@ -1,222 +1,222 @@ -//100311 -//0x024 0x11800f //syn CLK enable // tmp 40MHz solution -//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -0x040 0x000C0004 //Arthur-enable path 0 TR switch -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040000 -0x804 0x00000001 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390204 // jerry- for CCK Rx path A dynamic range -0x828 0x00000000 -0x82c 0x00000000 -0x830 0x00000000 -0x834 0x00000000 -0x838 0x00000000 -0x83c 0x00000000 -0x840 0x00010000 //RF to standby mode -0x844 0x00000000 -0x848 0x00000000 -0x84c 0x00000000 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x001b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60230 //88CE default left anatenna -0x864 0x061f0130 -0x868 0x00000000 -0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword -0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22004000 // -0x878 0x00000808 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121111 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x15160000 //Arthur-power tracking for high-power -0xa24 0x070b0f12 //Arthur-power tracking for high-power -0xa28 0x00000104 //Arthur-power tracking for high-power -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05611 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA -0xc54 0x43bc0094 -0xc58 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c56000d // disable AGC flow-1, 0x2c56000d for external LAN during high input power -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x24000090 //Arthur-power tracking for high-power -0xc84 0x20f60000 -0xc88 0x24000090 //Arthur-power tracking for high-power -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020401 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 -0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee8 0x31555448 // Authur-enable PAPE -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff - +//100311 +//0x024 0x11800f //syn CLK enable // tmp 40MHz solution +//0x028 0xffdb83 //320MHz CLK enable, medium BB clock driving // tmp 40MHz solution +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +0x040 0x000C0004 //Arthur-enable path 0 TR switch +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040000 +0x804 0x00000001 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10005388 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390204 // jerry- for CCK Rx path A dynamic range +0x828 0x00000000 +0x82c 0x00000000 +0x830 0x00000000 +0x834 0x00000000 +0x838 0x00000000 +0x83c 0x00000000 +0x840 0x00010000 //RF to standby mode +0x844 0x00000000 +0x848 0x00000000 +0x84c 0x00000000 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x001b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60230 //88CE default left anatenna +0x864 0x061f0130 +0x868 0x00000000 +0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword +0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22004000 // +0x878 0x00000808 // RF mode for standby & rx_low_power codeword +0x87c 0x00000000 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121111 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x15160000 //Arthur-power tracking for high-power +0xa24 0x070b0f12 //Arthur-power tracking for high-power +0xa28 0x00000104 //Arthur-power tracking for high-power +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05611 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA +0xc54 0x43bc0094 +0xc58 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c56000d // disable AGC flow-1, 0x2c56000d for external LAN during high input power +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x24000090 //Arthur-power tracking for high-power +0xc84 0x20f60000 +0xc88 0x24000090 //Arthur-power tracking for high-power +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020401 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 +0xe6c 0x631b25a0 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x081b25a0 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x081b25a0 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x631b25a0 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x081b25a0 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x631b25a0 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x631b25a0 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x631b25a0 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x631b25a0 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a0 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a0 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6b1b25a0 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee8 0x31555448 // Authur-enable PAPE +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff + diff --git a/package/kernel/rtl8192cd/data/PHY_REG_2T.txt b/package/kernel/rtl8192cd/data/PHY_REG_2T.txt old mode 100755 new mode 100644 index c730f36e211..c02d20f6ba2 --- a/package/kernel/rtl8192cd/data/PHY_REG_2T.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_2T.txt @@ -1,271 +1,271 @@ -//091204 -//0x024 0x0011800f //syn CLK enable -//0x028 0x00ffdb83 //320MHz CLK enable -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10000330 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390004 -0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x65a965a9 -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x0f7f0130 -0x864 0x0f7f0130 -0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x00004000 // -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc000004 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000000 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0xc1ff000c -0xa08 0x8c038300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e62120f -0xa10 0x95009b78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf80 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -0xb00 0x01017018 -0xb04 0xf7ed8f84 -0xb08 0x40372d20 -0xb0c 0x5b554e48 -0xb10 0x6f6a6560 -0xb14 0x807c7873 -0xb18 0x8f8b8884 -0xb1c 0x9d999693 -0xb20 0xa9a6a3a0 -0xb24 0xb5b2afac -0xb28 0x00810100 -0xb2c 0x00400056 -0xb30 0x002b0032 -0xb34 0x001f0024 -0xb38 0x0019001c -0xb3c 0x00150017 -0xb40 0x00120013 -0xb44 0x00100011 -0xb48 0x000e000f -0xb4c 0x000c000d -0xb50 0x000b000c -0xb54 0x000a000b -0xb58 0x0009000a -0xb5c 0x00090009 -0xb60 0x00080008 -0xb64 0x00080008 -0xb68 0x0fe00000 -0xb70 0x01017018 -0xb74 0xf7ed8f84 -0xb78 0x40372d20 -0xb7c 0x5b554e48 -0xb80 0x6f6a6560 -0xb84 0x807c7873 -0xb88 0x8f8b8884 -0xb8c 0x9d999693 -0xb90 0xa9a6a3a0 -0xb94 0xb5b2afac -0xb98 0x00810100 -0xb9c 0x00400056 -0xba0 0x002b0032 -0xba4 0x001f0024 -0xba8 0x0019001c -0xbac 0x00150017 -0xbb0 0x00120013 -0xbb4 0x00100011 -0xbb8 0x000e000f -0xbbc 0x000c000d -0xbc0 0x000b000c -0xbc4 0x000a000b -0xbc8 0x0009000a -0xbcc 0x00090009 -0xbd0 0x00080008 -0xbd4 0x00080008 -0xb6c 0x0fe00000 -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 // initial gain @ CCA negedge -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac4a // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a979718 -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x433c0094 -0xc58 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 //for MRC weighting function -0xc90 0x00000000 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00000000 // TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000000 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2b2b2b2b // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2b2b2b2b // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x2b2b2b2b // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2b2b2b2b // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2b2b2b2b // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2b2b2b2b // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2b2b2b2b // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -//0xe60 0x021400a0 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//091204 +//0x024 0x0011800f //syn CLK enable +//0x028 0x00ffdb83 //320MHz CLK enable +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10000330 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390004 +0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x65a965a9 +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x0f7f0130 +0x864 0x0f7f0130 +0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x00004000 // +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x00000000 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc000004 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000000 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0xc1ff000c +0xa08 0x8c038300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e62120f +0xa10 0x95009b78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf80 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +0xb00 0x01017018 +0xb04 0xf7ed8f84 +0xb08 0x40372d20 +0xb0c 0x5b554e48 +0xb10 0x6f6a6560 +0xb14 0x807c7873 +0xb18 0x8f8b8884 +0xb1c 0x9d999693 +0xb20 0xa9a6a3a0 +0xb24 0xb5b2afac +0xb28 0x00810100 +0xb2c 0x00400056 +0xb30 0x002b0032 +0xb34 0x001f0024 +0xb38 0x0019001c +0xb3c 0x00150017 +0xb40 0x00120013 +0xb44 0x00100011 +0xb48 0x000e000f +0xb4c 0x000c000d +0xb50 0x000b000c +0xb54 0x000a000b +0xb58 0x0009000a +0xb5c 0x00090009 +0xb60 0x00080008 +0xb64 0x00080008 +0xb68 0x0fe00000 +0xb70 0x01017018 +0xb74 0xf7ed8f84 +0xb78 0x40372d20 +0xb7c 0x5b554e48 +0xb80 0x6f6a6560 +0xb84 0x807c7873 +0xb88 0x8f8b8884 +0xb8c 0x9d999693 +0xb90 0xa9a6a3a0 +0xb94 0xb5b2afac +0xb98 0x00810100 +0xb9c 0x00400056 +0xba0 0x002b0032 +0xba4 0x001f0024 +0xba8 0x0019001c +0xbac 0x00150017 +0xbb0 0x00120013 +0xbb4 0x00100011 +0xbb8 0x000e000f +0xbbc 0x000c000d +0xbc0 0x000b000c +0xbc4 0x000a000b +0xbc8 0x0009000a +0xbcc 0x00090009 +0xbd0 0x00080008 +0xbd4 0x00080008 +0xb6c 0x0fe00000 +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 // initial gain @ CCA negedge +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac4a // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a979718 +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x433c0094 +0xc58 0x6954341e // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 //for MRC weighting function +0xc90 0x00000000 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00000000 // TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000000 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2b2b2b2b // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2b2b2b2b // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x2b2b2b2b // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2b2b2b2b // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2b2b2b2b // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2b2b2b2b // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2b2b2b2b // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +//0xe60 0x021400a0 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_2T_n.txt b/package/kernel/rtl8192cd/data/PHY_REG_2T_n.txt old mode 100755 new mode 100644 index 591d7c8c979..fe7c6c6fac4 --- a/package/kernel/rtl8192cd/data/PHY_REG_2T_n.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_2T_n.txt @@ -1,219 +1,219 @@ -//100311 -//0x024 0x0011800f //syn CLK enable -//0x028 0x00ffdb83 //320MHz CLK enable -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10000330 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390004 -0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60230 //88CE default left anatenna -0x864 0x061f0130 -0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x2b2b2b27 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22184000 //path B 1R RSSI off issue -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x00000000 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc0094 -0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 //for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//100311 +//0x024 0x0011800f //syn CLK enable +//0x028 0x00ffdb83 //320MHz CLK enable +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10000330 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390004 +0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60230 //88CE default left anatenna +0x864 0x061f0130 +0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x2b2b2b27 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22184000 //path B 1R RSSI off issue +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x00000000 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x43bc0094 +0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 //for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_2T_n_hp.txt b/package/kernel/rtl8192cd/data/PHY_REG_2T_n_hp.txt index adc0f5897c1..351931593ea 100644 --- a/package/kernel/rtl8192cd/data/PHY_REG_2T_n_hp.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_2T_n_hp.txt @@ -1,220 +1,220 @@ -//100311 -//0x024 0x0011800f //syn CLK enable -//0x028 0x00ffdb83 //320MHz CLK enable -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390204 // jerry- for CCK Rx path A dynamic range -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390204 // jerry- for CCK Rx path B dynamic range -0x830 0x24242424 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x24242424 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x20202024 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x24242424 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x24242424 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x24242424 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60230 //88CE default left anatenna -0x864 0x061f0130 -0x868 0x24242424 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword -0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22184000 //path B 1R RSSI off issue -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x00ffc3f1 // TST mode 0x00000000 -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e6b120f // Arthur+BS 11.12.20 fix, original is 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x15160000 //Arthur-power tracking for high-power -0xa24 0x070b0f12 //Arthur-power tracking for high-power -0xa28 0x00000104 //Arthur-power tracking for high-power -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA -0xc54 0x43bc0094 -0xc58 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c56000d // disable AGC flow-1, 0x2c56000d for external LAN during high input power -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x24000090 //Arthur-power tracking for high-power -0xc84 0x20f60000 -0xc88 0x24000090 //Arthur-power tracking for high-power -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee8 0x31555448 // Authur-enable PAPE -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//100311 +//0x024 0x0011800f //syn CLK enable +//0x028 0x00ffdb83 //320MHz CLK enable +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10005388 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390204 // jerry- for CCK Rx path A dynamic range +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390204 // jerry- for CCK Rx path B dynamic range +0x830 0x24242424 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x24242424 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x20202024 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x24242424 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x24242424 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x24242424 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60230 //88CE default left anatenna +0x864 0x061f0130 +0x868 0x24242424 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword +0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22184000 //path B 1R RSSI off issue +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x00ffc3f1 // TST mode 0x00000000 +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e6b120f // Arthur+BS 11.12.20 fix, original is 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x15160000 //Arthur-power tracking for high-power +0xa24 0x070b0f12 //Arthur-power tracking for high-power +0xa28 0x00000104 //Arthur-power tracking for high-power +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA +0xc54 0x43bc0094 +0xc58 0x6954342e // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342e for external LNA +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c56000d // disable AGC flow-1, 0x2c56000d for external LAN during high input power +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x24000090 //Arthur-power tracking for high-power +0xc84 0x20f60000 +0xc88 0x24000090 //Arthur-power tracking for high-power +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee8 0x31555448 // Authur-enable PAPE +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_2T_n_lna.txt b/package/kernel/rtl8192cd/data/PHY_REG_2T_n_lna.txt old mode 100755 new mode 100644 index 77259b01f7a..710878c9c5c --- a/package/kernel/rtl8192cd/data/PHY_REG_2T_n_lna.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_2T_n_lna.txt @@ -1,220 +1,220 @@ -//100311 -//0x024 0x0011800f //syn CLK enable -//0x028 0x00ffdb83 //320MHz CLK enable -0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10005388 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390204 // jerry- for CCK Rx path A dynamic range -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390204 // jerry- for CCK Rx path B dynamic range -0x830 0x24242424 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x24242424 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x20202024 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x24242424 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x24242424 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x24242424 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60230 //88CE default left anatenna -0x864 0x061f0130 -0x868 0x24242424 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword -0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22184000 //path B 1R RSSI off issue -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x00ffc3f1 // TST mode 0x00000000 -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x000004d5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c -0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 -0xa0c 0x2e6b120f // Arthur+BS 11.12.20 fix, original is 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x48071d40 -0xc04 0x03a05633 -0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a97971c -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x6954342a // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342a for external LNA -0xc54 0x43bc0094 -0xc58 0x6954342a // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342a for external LNA -0xc5c 0x433c0094 -0xc60 0x00000000 // DTR TH -0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x00b91612 -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 // for MRC weighting function -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000000 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b22427 // reserved -0xcdc 0x00766932 // reserved -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608000 -0xd38 0x00000000 -0xd3c 0x00027293 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -0xee8 0x31555448 // Authur-enable PAPE -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf4c 0x00000000 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//100311 +//0x024 0x0011800f //syn CLK enable +//0x028 0x00ffdb83 //320MHz CLK enable +0x028 0xffff83 //320MHz CLK enable, strong BB clock driving // tmp 40MHz solution +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10005388 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390204 // jerry- for CCK Rx path A dynamic range +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390204 // jerry- for CCK Rx path B dynamic range +0x830 0x24242424 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x24242424 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x20202024 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x24242424 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x24242424 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x24242424 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60230 //88CE default left anatenna +0x864 0x061f0130 +0x868 0x24242424 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x20202020 // Path-A 11M/5.5M/2M TX AGC codeword, Path-B 11M TX AGC codeword +0x870 0x03000300 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22184000 //path B 1R RSSI off issue +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x00ffc3f1 // TST mode 0x00000000 +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x000004d5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c +0xa08 0x8c838300 // MP: 0x88838300, driver: 0x8ccd8300 +0xa0c 0x2e6b120f // Arthur+BS 11.12.20 fix, original is 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x48071d40 +0xc04 0x03a05633 +0xc08 0x000000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a97971c +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x6954342a // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342a for external LNA +0xc54 0x43bc0094 +0xc58 0x6954342a // AAGC=1,0x68043420, AAGC=2,0x69543420, 0x6954342a for external LNA +0xc5c 0x433c0094 +0xc60 0x00000000 // DTR TH +0xc64 0x5116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x018610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x00b91612 +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 // for MRC weighting function +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000000 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b22427 // reserved +0xcdc 0x00766932 // reserved +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608000 +0xd38 0x00000000 +0xd3c 0x00027293 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x24242424 // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x24242424 // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902024 // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x24242424 // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x24242424 // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x24242424 // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x24242424 // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c1b25a4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +0xee8 0x31555448 // Authur-enable PAPE +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf4c 0x00000000 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_MP_n_92C.txt b/package/kernel/rtl8192cd/data/PHY_REG_MP_n_92C.txt index 7d3186fa286..ce7c5e73de1 100644 --- a/package/kernel/rtl8192cd/data/PHY_REG_MP_n_92C.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_MP_n_92C.txt @@ -1,4 +1,4 @@ -//20100315 -0xc30 0x69e9ac4a //RX false alarm issue -0xc3c 0x0a979718 +//20100315 +0xc30 0x69e9ac4a //RX false alarm issue +0xc3c 0x0a979718 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data/PHY_REG_PG_92C.txt b/package/kernel/rtl8192cd/data/PHY_REG_PG_92C.txt index 635ed84840d..3fb9baa728c 100644 --- a/package/kernel/rtl8192cd/data/PHY_REG_PG_92C.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_PG_92C.txt @@ -1,26 +1,26 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= - - -//Offset talbe_0 for BG_EN=0 -// For Ant A -0xe00 0xffffffff 0x0609090a // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00030406 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x01040508 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x01040508 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x0609090a // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00030406 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x01040508 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x01040508 // base on 0x32 //for MCS=15,14,13,12 -0xff +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= + + +//Offset talbe_0 for BG_EN=0 +// For Ant A +0xe00 0xffffffff 0x0609090a // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00030406 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x01040508 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x090a0a0b // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x01040508 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x0609090a // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00030406 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x01040508 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x090a0a0b // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x01040508 // base on 0x32 //for MCS=15,14,13,12 +0xff diff --git a/package/kernel/rtl8192cd/data/PHY_REG_PG_hp.txt b/package/kernel/rtl8192cd/data/PHY_REG_PG_hp.txt index 582c5287e98..5d62c4a58d2 100644 --- a/package/kernel/rtl8192cd/data/PHY_REG_PG_hp.txt +++ b/package/kernel/rtl8192cd/data/PHY_REG_PG_hp.txt @@ -1,27 +1,27 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -// High-power application, jerry 20100928 -//========================= - - -//Offset talbe_0 for BG_EN=0 -// For Ant A -0xe00 0xffffffff 0x06080808 // base on 0x30 //for 18M,12M,09M,06M //27,28,28,28dBm -0xe04 0xffffffff 0x00040406 // base on 0x30 //for 54M,48M,36M,24M //24,26,26,27dBm -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 28 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 28 dB -0xe10 0xffffffff 0x04060608 // base on 0x30 //for MCS=03,02,01,00 //26,27,27,28dBm -0xe14 0xffffffff 0x00020204 // base on 0x30 //for MCS=07,06,05,04 //24,25,25,26dBm -0xe18 0xffffffff 0x04060608 // base on 0x30 //for MCS=11,10,09,08 //26,27,27,28dBm -0xe1c 0xffffffff 0x00020204 // base on 0x30 //for MCS=15,14,13,12 //24,25,25,26dBm -// For Ant B -0x830 0xffffffff 0x06080808 // base on 0x32 //for 18M,12M,09M,06M //same as Ant A -0x834 0xffffffff 0x00040406 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 28dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 28dB -0x83c 0xffffffff 0x04060608 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020204 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x04060608 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00020204 // base on 0x32 //for MCS=15,14,13,12 -0xff +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +// High-power application, jerry 20100928 +//========================= + + +//Offset talbe_0 for BG_EN=0 +// For Ant A +0xe00 0xffffffff 0x06080808 // base on 0x30 //for 18M,12M,09M,06M //27,28,28,28dBm +0xe04 0xffffffff 0x00040406 // base on 0x30 //for 54M,48M,36M,24M //24,26,26,27dBm +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 28 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 28 dB +0xe10 0xffffffff 0x04060608 // base on 0x30 //for MCS=03,02,01,00 //26,27,27,28dBm +0xe14 0xffffffff 0x00020204 // base on 0x30 //for MCS=07,06,05,04 //24,25,25,26dBm +0xe18 0xffffffff 0x04060608 // base on 0x30 //for MCS=11,10,09,08 //26,27,27,28dBm +0xe1c 0xffffffff 0x00020204 // base on 0x30 //for MCS=15,14,13,12 //24,25,25,26dBm +// For Ant B +0x830 0xffffffff 0x06080808 // base on 0x32 //for 18M,12M,09M,06M //same as Ant A +0x834 0xffffffff 0x00040406 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 28dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 28dB +0x83c 0xffffffff 0x04060608 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020204 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x04060608 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00020204 // base on 0x32 //for MCS=15,14,13,12 +0xff diff --git a/package/kernel/rtl8192cd/data/REG_TXPWR_TRK.txt b/package/kernel/rtl8192cd/data/REG_TXPWR_TRK.txt index 9243f8c965f..4f5ad98a102 100644 --- a/package/kernel/rtl8192cd/data/REG_TXPWR_TRK.txt +++ b/package/kernel/rtl8192cd/data/REG_TXPWR_TRK.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 2G PathA&B =============== - -2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 0 1 2 4 5 7 8 10 12 -5GLA_N 1 2 3 5 7 9 10 12 14 16 -5GLB_P 0 1 2 4 5 7 8 10 12 -5GLB_N 1 2 3 5 7 9 10 12 14 16 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 0 1 2 4 5 7 8 10 12 -5GMA_N 1 2 3 5 7 9 10 12 14 16 -5GMB_P 0 1 2 4 5 7 8 10 12 -5GMB_N 1 2 3 5 7 9 10 12 14 16 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 0 1 2 4 5 7 8 10 12 -5GHA_N 1 2 3 5 7 9 10 12 14 16 -5GHB_P 0 1 2 4 5 7 8 10 12 -5GHB_N 1 2 3 5 7 9 10 12 14 16 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 2G PathA&B =============== + +2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 0 1 2 4 5 7 8 10 12 +5GLA_N 1 2 3 5 7 9 10 12 14 16 +5GLB_P 0 1 2 4 5 7 8 10 12 +5GLB_N 1 2 3 5 7 9 10 12 14 16 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 0 1 2 4 5 7 8 10 12 +5GMA_N 1 2 3 5 7 9 10 12 14 16 +5GMB_P 0 1 2 4 5 7 8 10 12 +5GMB_N 1 2 3 5 7 9 10 12 14 16 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 0 1 2 4 5 7 8 10 12 +5GHA_N 1 2 3 5 7 9 10 12 14 16 +5GHB_P 0 1 2 4 5 7 8 10 12 +5GHB_N 1 2 3 5 7 9 10 12 14 16 + + diff --git a/package/kernel/rtl8192cd/data/REG_TXPWR_TRK_hp.txt b/package/kernel/rtl8192cd/data/REG_TXPWR_TRK_hp.txt index 9243f8c965f..4f5ad98a102 100644 --- a/package/kernel/rtl8192cd/data/REG_TXPWR_TRK_hp.txt +++ b/package/kernel/rtl8192cd/data/REG_TXPWR_TRK_hp.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 2G PathA&B =============== - -2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 0 1 2 4 5 7 8 10 12 -5GLA_N 1 2 3 5 7 9 10 12 14 16 -5GLB_P 0 1 2 4 5 7 8 10 12 -5GLB_N 1 2 3 5 7 9 10 12 14 16 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 0 1 2 4 5 7 8 10 12 -5GMA_N 1 2 3 5 7 9 10 12 14 16 -5GMB_P 0 1 2 4 5 7 8 10 12 -5GMB_N 1 2 3 5 7 9 10 12 14 16 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 0 1 2 4 5 7 8 10 12 -5GHA_N 1 2 3 5 7 9 10 12 14 16 -5GHB_P 0 1 2 4 5 7 8 10 12 -5GHB_N 1 2 3 5 7 9 10 12 14 16 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 2G PathA&B =============== + +2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 0 1 2 4 5 7 8 10 12 +5GLA_N 1 2 3 5 7 9 10 12 14 16 +5GLB_P 0 1 2 4 5 7 8 10 12 +5GLB_N 1 2 3 5 7 9 10 12 14 16 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 0 1 2 4 5 7 8 10 12 +5GMA_N 1 2 3 5 7 9 10 12 14 16 +5GMB_P 0 1 2 4 5 7 8 10 12 +5GMB_N 1 2 3 5 7 9 10 12 14 16 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 0 1 2 4 5 7 8 10 12 +5GHA_N 1 2 3 5 7 9 10 12 14 16 +5GHB_P 0 1 2 4 5 7 8 10 12 +5GHB_N 1 2 3 5 7 9 10 12 14 16 + + diff --git a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c.txt b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c.txt index 5851a7ce42f..ef000ed8966 100644 --- a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c.txt +++ b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c.txt @@ -1,75 +1,75 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: FCC, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1 17 17// band edge -11 17 17// band edge - - -//=========================================== -// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 15.5 15// band edge -11 13.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: FCC, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 15.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: FCC, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 15 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: FCC, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: FCC, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: FCC, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1 17 17// band edge +11 17 17// band edge + + +//=========================================== +// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 15.5 15// band edge +11 13.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: FCC, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 15.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: FCC, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 15 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: FCC, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: FCC, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_1.txt b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_1.txt index 5851a7ce42f..ef000ed8966 100644 --- a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_1.txt +++ b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_1.txt @@ -1,75 +1,75 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: FCC, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1 17 17// band edge -11 17 17// band edge - - -//=========================================== -// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 15.5 15// band edge -11 13.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: FCC, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 15.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: FCC, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 15 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: FCC, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: FCC, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: FCC, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1 17 17// band edge +11 17 17// band edge + + +//=========================================== +// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 15.5 15// band edge +11 13.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: FCC, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 15.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: FCC, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 15 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: FCC, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: FCC, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_2.txt b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_2.txt index 47f0a89ffb9..16e996b9460 100644 --- a/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_2.txt +++ b/package/kernel/rtl8192cd/data/TXPWR_LMT_92c_2.txt @@ -1,74 +1,74 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: CE, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1:13 16 17// band edge - - -//=========================================== -// Table 2: CE, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 16.5 15// band edge -13 16.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: CE, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 16 13// band edge -13 16 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: CE, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 13 13// band edge -13 13 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: CE, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: CE, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13 13// band edge -11 13 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: CE, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1:13 16 17// band edge + + +//=========================================== +// Table 2: CE, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 16.5 15// band edge +13 16.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: CE, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 16 13// band edge +13 16 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: CE, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 13 13// band edge +13 13 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: CE, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: CE, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13 13// band edge +11 13 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data/radio_a_1T.txt b/package/kernel/rtl8192cd/data/radio_a_1T.txt old mode 100755 new mode 100644 index e27126480b7..d9e7b67c138 --- a/package/kernel/rtl8192cd/data/radio_a_1T.txt +++ b/package/kernel/rtl8192cd/data/radio_a_1T.txt @@ -1,155 +1,155 @@ -//091201 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0X09 0X2044f -0x0a 0x1adb0 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0c52c -0x0e 0x11087 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x10255 //12255 //0x10255 for CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc300 -0x1d 0xa1250 -0x1e 0x44009 //RC calibration power on -0x1f 0x80441 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x00000 -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x0f400 -0x27 0xc8799 //0x27 0xcc799 -0x28 0x55540 //0x28 0x59540 -0x29 0x04582 -0x2a 0x00001 -0x2b 0x21334 - -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00709 -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x00709 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0050b -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66623 -0x2c 0x0001a - -0x2a 0x60000 //0x60000 for 1M spurs - -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0x231fc //turn on PAD2 //?? -0x10 0x6000f //RX IQ K -0x11 0x3f9f8 //turn on RXBB BFAC //?? -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x1000f //standbt mode -0x11 0x20103 //RF lpbk switches on if at APK mode - -//RXAGC_RXHP table -0x12 0x32000 -0x12 0x71000 -0x12 0xb0000 -0x12 0xfc000 - -//TX gain table -0x13 0x287b3 -0x13 0x247a7 -0x13 0x2079b -0x13 0x1c49f -0x13 0x1839e -0x13 0x142a1 -0x13 0x102a8 -0x13 0x0c29c -0x13 0x081a0 -0x13 0x040ac -0x13 0x00024 - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0xcf415 //OFDM -0x15 0x8f415 //CCK -0x15 0x4f415 //MCS - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - - - -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80443 //RC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x00 0x30159 //RX mode - -0xff 0xffff - - - - +//091201 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0X09 0X2044f +0x0a 0x1adb0 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0c52c +0x0e 0x11087 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x10255 //12255 //0x10255 for CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc300 +0x1d 0xa1250 +0x1e 0x44009 //RC calibration power on +0x1f 0x80441 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x00000 +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x0f400 +0x27 0xc8799 //0x27 0xcc799 +0x28 0x55540 //0x28 0x59540 +0x29 0x04582 +0x2a 0x00001 +0x2b 0x21334 + +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00709 +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x00709 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0050b +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66623 +0x2c 0x0001a + +0x2a 0x60000 //0x60000 for 1M spurs + +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0x231fc //turn on PAD2 //?? +0x10 0x6000f //RX IQ K +0x11 0x3f9f8 //turn on RXBB BFAC //?? +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x1000f //standbt mode +0x11 0x20103 //RF lpbk switches on if at APK mode + +//RXAGC_RXHP table +0x12 0x32000 +0x12 0x71000 +0x12 0xb0000 +0x12 0xfc000 + +//TX gain table +0x13 0x287b3 +0x13 0x247a7 +0x13 0x2079b +0x13 0x1c49f +0x13 0x1839e +0x13 0x142a1 +0x13 0x102a8 +0x13 0x0c29c +0x13 0x081a0 +0x13 0x040ac +0x13 0x00024 + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0xcf415 //OFDM +0x15 0x8f415 //CCK +0x15 0x4f415 //MCS + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + + + +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80443 //RC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x00 0x30159 //RX mode + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_a_1T_n.txt b/package/kernel/rtl8192cd/data/radio_a_1T_n.txt old mode 100755 new mode 100644 index 26edebc1eb6..f954b7391e6 --- a/package/kernel/rtl8192cd/data/radio_a_1T_n.txt +++ b/package/kernel/rtl8192cd/data/radio_a_1T_n.txt @@ -1,169 +1,169 @@ -//100311 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb0 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e52c -0x0e 0x39ce7 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x10255 //12255 //0x10255 for CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc378 //Alex 0xfc300 -0x1d 0xa1250 -0x1e 0x4445f //RC calibration power on -0x1f 0x80001 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x00000 -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x4f000 -0x27 0xec7d9 //0x27 0xcc799 -0x28 0x977c0 //0x28 0x59540 -0x29 0x04783 -0x2a 0x00001 -0x2b 0x21334 - -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00808 -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x0060a -0x2b 0x4b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0060a -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66666 //Alex 0x66623 -0x2c 0x0001a - -0x2a 0xe0000 //0x60000 for 1M spurs - -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0xe31fc //Alex_0x231fc //turn on PAD2 -0x10 0x6000f //RX IQ K -0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x3000f //Alex RX mode -0x11 0xff500 //Alex RX mode -//0x10 0x1000f //standbt mode -//0x11 0x20103 //RF lpbk switches on if at APK mode -0x10 0x00000 //Alex shut down mode -0x11 0x00000 //Alex shut down mode -0x10 0x8000f //Alex low power RX mode -0x11 0x3f100 // Alex low power RX mode -0x10 0x9000f //Alex low power idle mode -0x11 0x23100 //Alex power idle mode - -//RXAGC_RXHP table -0x12 0x32000 -0x12 0x71000 -0x12 0xb0000 -0x12 0xfc000 - -//TX gain table -0x13 0x287b3 -0x13 0x244b7 -0x13 0x204ab -0x13 0x1c49f -0x13 0x18493 -0x13 0x1438f -0x13 0x10299 -0x13 0x0c29c -0x13 0x081a0 -0x13 0x040ac -0x13 0x00020 - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 - - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - - - -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80003 //RC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1e 0x44457 -0x1f 0x80000 -0x00 0x30159 //RX mode - -0xff 0xffff - - - - +//100311 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb0 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e52c +0x0e 0x39ce7 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x10255 //12255 //0x10255 for CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc378 //Alex 0xfc300 +0x1d 0xa1250 +0x1e 0x4445f //RC calibration power on +0x1f 0x80001 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x00000 +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x4f000 +0x27 0xec7d9 //0x27 0xcc799 +0x28 0x977c0 //0x28 0x59540 +0x29 0x04783 +0x2a 0x00001 +0x2b 0x21334 + +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00808 +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x0060a +0x2b 0x4b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0060a +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66666 //Alex 0x66623 +0x2c 0x0001a + +0x2a 0xe0000 //0x60000 for 1M spurs + +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0xe31fc //Alex_0x231fc //turn on PAD2 +0x10 0x6000f //RX IQ K +0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x3000f //Alex RX mode +0x11 0xff500 //Alex RX mode +//0x10 0x1000f //standbt mode +//0x11 0x20103 //RF lpbk switches on if at APK mode +0x10 0x00000 //Alex shut down mode +0x11 0x00000 //Alex shut down mode +0x10 0x8000f //Alex low power RX mode +0x11 0x3f100 // Alex low power RX mode +0x10 0x9000f //Alex low power idle mode +0x11 0x23100 //Alex power idle mode + +//RXAGC_RXHP table +0x12 0x32000 +0x12 0x71000 +0x12 0xb0000 +0x12 0xfc000 + +//TX gain table +0x13 0x287b3 +0x13 0x244b7 +0x13 0x204ab +0x13 0x1c49f +0x13 0x18493 +0x13 0x1438f +0x13 0x10299 +0x13 0x0c29c +0x13 0x081a0 +0x13 0x040ac +0x13 0x00020 + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 + + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + + + +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80003 //RC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1e 0x44457 +0x1f 0x80000 +0x00 0x30159 //RX mode + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_a_2T.txt b/package/kernel/rtl8192cd/data/radio_a_2T.txt old mode 100755 new mode 100644 index 1fa18d35deb..468148b2df0 --- a/package/kernel/rtl8192cd/data/radio_a_2T.txt +++ b/package/kernel/rtl8192cd/data/radio_a_2T.txt @@ -1,153 +1,153 @@ -//091201 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0X09 0X2044f -0x0a 0x1adb0 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0c52c -0x0e 0x21087 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x10255 //12255 //0x10255 for CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc300 -0x1d 0xa1250 -0x1e 0x44009 //RC calibration power on -0x1f 0x80441 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x00000 -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x0f400 -0x27 0xc8799 //0x27 0xcc799 -0x28 0x55540 //0x28 0x59540 -0x29 0x04582 -0x2a 0x00001 -0x2b 0x21334 - -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00709 -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x00709 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0050b -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66623 -0x2c 0x0001a - -0x2a 0x60000 //0x60000 for 1M spurs - -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0x231fc //turn on PAD2 //?? -0x10 0x6000f //RX IQ K -0x11 0x3f9f8 //turn on RXBB BFAC //?? -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x1000f //standbt mode -0x11 0x20103 //RF lpbk switches on if at APK mode - -//RXAGC_RXHP table -0x12 0x32000 -0x12 0x71000 -0x12 0xb0000 -0x12 0xfc000 - -//TX gain table -0x13 0x287b3 -0x13 0x247a7 -0x13 0x2079b -0x13 0x1c49f -0x13 0x1839e -0x13 0x142a1 -0x13 0x102a8 -0x13 0x0c29c -0x13 0x081a0 -0x13 0x040ac -0x13 0x00024 - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f433 -0x15 0x4f433 -0x15 0x8f433 - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - - -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80443 //RC calibration -0xfe // delay 50ms -0x00 0x30159 //RX mode - -0xff 0xffff - - - - +//091201 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0X09 0X2044f +0x0a 0x1adb0 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0c52c +0x0e 0x21087 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x10255 //12255 //0x10255 for CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc300 +0x1d 0xa1250 +0x1e 0x44009 //RC calibration power on +0x1f 0x80441 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x00000 +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x0f400 +0x27 0xc8799 //0x27 0xcc799 +0x28 0x55540 //0x28 0x59540 +0x29 0x04582 +0x2a 0x00001 +0x2b 0x21334 + +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00709 +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x00709 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0050b +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66623 +0x2c 0x0001a + +0x2a 0x60000 //0x60000 for 1M spurs + +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0x231fc //turn on PAD2 //?? +0x10 0x6000f //RX IQ K +0x11 0x3f9f8 //turn on RXBB BFAC //?? +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x1000f //standbt mode +0x11 0x20103 //RF lpbk switches on if at APK mode + +//RXAGC_RXHP table +0x12 0x32000 +0x12 0x71000 +0x12 0xb0000 +0x12 0xfc000 + +//TX gain table +0x13 0x287b3 +0x13 0x247a7 +0x13 0x2079b +0x13 0x1c49f +0x13 0x1839e +0x13 0x142a1 +0x13 0x102a8 +0x13 0x0c29c +0x13 0x081a0 +0x13 0x040ac +0x13 0x00024 + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f433 +0x15 0x4f433 +0x15 0x8f433 + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + + +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80443 //RC calibration +0xfe // delay 50ms +0x00 0x30159 //RX mode + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_a_2T_n.txt b/package/kernel/rtl8192cd/data/radio_a_2T_n.txt old mode 100755 new mode 100644 index 574b326e5af..4151b18743f --- a/package/kernel/rtl8192cd/data/radio_a_2T_n.txt +++ b/package/kernel/rtl8192cd/data/radio_a_2T_n.txt @@ -1,169 +1,169 @@ -//100311 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb0 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e52c -0x0e 0x39ce7 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x10255 //12255 //0x10255 for CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc378 //Alex 0xfc300 -0x1d 0xa1250 -0x1e 0x4445f //RC calibration power on -0x1f 0x80001 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x00000 -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x4f000 -0x27 0xec7d9 //0x27 0xcc799 -0x28 0x977c0 //0x28 0x59540 -0x29 0x04783 -0x2a 0x00001 -0x2b 0x21334 - -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00808 -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x0060a -0x2b 0x4b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0060a -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66666 //Alex 0x66623 -0x2c 0x0001a - -0x2a 0xe0000 //0x60000 for 1M spurs - -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0xe31fc //Alex_0x231fc //turn on PAD2 -0x10 0x6000f //RX IQ K -0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x3000f //Alex RX mode -0x11 0xff500 //Alex RX mode -//0x10 0x1000f //standbt mode -//0x11 0x20103 //RF lpbk switches on if at APK mode -0x10 0x00000 //Alex shut down mode -0x11 0x00000 //Alex shut down mode -0x10 0x8000f //Alex low power RX mode -0x11 0x3f100 // Alex low power RX mode -0x10 0x9000f //Alex low power idle mode -0x11 0x23100 //Alex power idle mode - -//RXAGC_RXHP table -0x12 0x32000 -0x12 0x71000 -0x12 0xb0000 -0x12 0xfc000 - -//TX gain table -0x13 0x287af -0x13 0x244b7 -0x13 0x204ab -0x13 0x1c49f -0x13 0x18493 -0x13 0x14297 -0x13 0x10295 -0x13 0x0c298 -0x13 0x0819c -0x13 0x040a8 -0x13 0x0001c - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 - - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - - - -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80003 //RC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1e 0x44457 -0x1f 0x80000 -0x00 0x30159 //RX mode - -0xff 0xffff - - - - +//100311 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb0 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e52c +0x0e 0x39ce7 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x10255 //12255 //0x10255 for CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc378 //Alex 0xfc300 +0x1d 0xa1250 +0x1e 0x4445f //RC calibration power on +0x1f 0x80001 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x00000 +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x4f000 +0x27 0xec7d9 //0x27 0xcc799 +0x28 0x977c0 //0x28 0x59540 +0x29 0x04783 +0x2a 0x00001 +0x2b 0x21334 + +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00808 +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x0060a +0x2b 0x4b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0060a +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66666 //Alex 0x66623 +0x2c 0x0001a + +0x2a 0xe0000 //0x60000 for 1M spurs + +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0xe31fc //Alex_0x231fc //turn on PAD2 +0x10 0x6000f //RX IQ K +0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x3000f //Alex RX mode +0x11 0xff500 //Alex RX mode +//0x10 0x1000f //standbt mode +//0x11 0x20103 //RF lpbk switches on if at APK mode +0x10 0x00000 //Alex shut down mode +0x11 0x00000 //Alex shut down mode +0x10 0x8000f //Alex low power RX mode +0x11 0x3f100 // Alex low power RX mode +0x10 0x9000f //Alex low power idle mode +0x11 0x23100 //Alex power idle mode + +//RXAGC_RXHP table +0x12 0x32000 +0x12 0x71000 +0x12 0xb0000 +0x12 0xfc000 + +//TX gain table +0x13 0x287af +0x13 0x244b7 +0x13 0x204ab +0x13 0x1c49f +0x13 0x18493 +0x13 0x14297 +0x13 0x10295 +0x13 0x0c298 +0x13 0x0819c +0x13 0x040a8 +0x13 0x0001c + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 + + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + + + +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80003 //RC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1e 0x44457 +0x1f 0x80000 +0x00 0x30159 //RX mode + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_a_2T_n_hp.txt b/package/kernel/rtl8192cd/data/radio_a_2T_n_hp.txt index 5de8fcfc09f..6128eb93f72 100644 --- a/package/kernel/rtl8192cd/data/radio_a_2T_n_hp.txt +++ b/package/kernel/rtl8192cd/data/radio_a_2T_n_hp.txt @@ -1,157 +1,157 @@ -//100701 -//////////////////////// -//0x26 OFDM CCK -// 0x4f000 0xf400 -//////////////////////// -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb1 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e529 //jerry-low gain for ext.PA -0x0e 0x39ce7 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x00255 //12255 //jerry-0x00255 for high power CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc378 //Alex 0xfc300 -0x1d 0xa1250 -0x1e 0x4445f //RC calibration power on -0x1f 0x80001 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x0083c //Arthur-adjust PAPE voltage -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x4f000 -0x27 0xec7d9 //0x27 0xcc799 -0x28 0x577c0 //0x28 0x59540 -0x29 0x04783 -0x2a 0x00001 -0x2b 0x21334 -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00808 -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x0060a -0x2b 0x4b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0060a -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66666 //Alex 0x66623 -0x2c 0x0001a -0x2a 0xe0000 //0x60000 for 1M spurs -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0xe31fc //Alex_0x231fc //turn on PAD2 -0x10 0x6000f //RX IQ K -0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x3000f //Alex RX mode -0x11 0xff500 //Alex RX mode -//0x10 0x1000f //standbt mode -//0x11 0x20103 //RF lpbk switches on if at APK mode -0x10 0x00000 //Alex shut down mode -0x11 0x00000 //Alex shut down mode -0x10 0x8000f //Alex low power RX mode -0x11 0x3f100 // Alex low power RX mode -0x10 0x9000f //Alex low power idle mode -0x11 0x23100 //Alex power idle mode -//RXAGC_RXHP table - jerry for ACPR -0x12 0xd8000 //0x32000; d4000 -0x12 0x90000 //0x71000; 90000 -0x12 0x51000 //0xb0000; 51000 -0x12 0x12000 //0xfc000; 12000 -//TX gain table - Arthur -0x13 0x28fa8 //Arthur+BS 2011-12-27 old:0x24fa8 //jerry-old 0x28fb4 -0x13 0x24fa8 -0x13 0x207a4 -0x13 0x1c3b0 //0x1c3b0 for 39-40 nonlinear issue -0x13 0x183a4 -0x13 0x14398 -0x13 0x101a4 -0x13 0x0c198 -0x13 0x080a4 -0x13 0x04098 -0x13 0x00014 -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80003 //RC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1e 0x44457 -0x1f 0x80000 -0x00 0x30159 //RX mode -0xff 0xffff - +//100701 +//////////////////////// +//0x26 OFDM CCK +// 0x4f000 0xf400 +//////////////////////// +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb1 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e529 //jerry-low gain for ext.PA +0x0e 0x39ce7 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x00255 //12255 //jerry-0x00255 for high power CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc378 //Alex 0xfc300 +0x1d 0xa1250 +0x1e 0x4445f //RC calibration power on +0x1f 0x80001 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x0083c //Arthur-adjust PAPE voltage +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x4f000 +0x27 0xec7d9 //0x27 0xcc799 +0x28 0x577c0 //0x28 0x59540 +0x29 0x04783 +0x2a 0x00001 +0x2b 0x21334 +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00808 +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x0060a +0x2b 0x4b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0060a +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66666 //Alex 0x66623 +0x2c 0x0001a +0x2a 0xe0000 //0x60000 for 1M spurs +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0xe31fc //Alex_0x231fc //turn on PAD2 +0x10 0x6000f //RX IQ K +0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x3000f //Alex RX mode +0x11 0xff500 //Alex RX mode +//0x10 0x1000f //standbt mode +//0x11 0x20103 //RF lpbk switches on if at APK mode +0x10 0x00000 //Alex shut down mode +0x11 0x00000 //Alex shut down mode +0x10 0x8000f //Alex low power RX mode +0x11 0x3f100 // Alex low power RX mode +0x10 0x9000f //Alex low power idle mode +0x11 0x23100 //Alex power idle mode +//RXAGC_RXHP table - jerry for ACPR +0x12 0xd8000 //0x32000; d4000 +0x12 0x90000 //0x71000; 90000 +0x12 0x51000 //0xb0000; 51000 +0x12 0x12000 //0xfc000; 12000 +//TX gain table - Arthur +0x13 0x28fa8 //Arthur+BS 2011-12-27 old:0x24fa8 //jerry-old 0x28fb4 +0x13 0x24fa8 +0x13 0x207a4 +0x13 0x1c3b0 //0x1c3b0 for 39-40 nonlinear issue +0x13 0x183a4 +0x13 0x14398 +0x13 0x101a4 +0x13 0x0c198 +0x13 0x080a4 +0x13 0x04098 +0x13 0x00014 +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80003 //RC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1e 0x44457 +0x1f 0x80000 +0x00 0x30159 //RX mode +0xff 0xffff + diff --git a/package/kernel/rtl8192cd/data/radio_a_2T_n_lna.txt b/package/kernel/rtl8192cd/data/radio_a_2T_n_lna.txt old mode 100755 new mode 100644 index 49ecf00e19e..687f3b1daa0 --- a/package/kernel/rtl8192cd/data/radio_a_2T_n_lna.txt +++ b/package/kernel/rtl8192cd/data/radio_a_2T_n_lna.txt @@ -1,173 +1,173 @@ -//100701 -//////////////////////// -//0x26 OFDM CCK -// 0x4f000 0xf400 -//////////////////////// -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb1 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e52c -0x0e 0x39ce7 -0x0f 0x00451 -0x19 0x00000 -0x1a 0x00255 //12255 //jerry-0x00255 for high power CCK ACPR -0x1b 0x60a00 //RSSI -0x1c 0xfc378 //Alex 0xfc300 -0x1d 0xa1250 -0x1e 0x4445f //RC calibration power on -0x1f 0x80001 //RC calibration power on -0x20 0x0b614 -0x21 0x6c000 //idac poweron -0x22 0x0083c //Arthur-adjust PAPE voltage -0x23 0x01558 -0x24 0x00060 // enabile temp meter -0x25 0x00483 //0x00583 //0x00483 for unlock issue -0x26 0x4f000 -0x27 0xec7d9 //0x27 0xcc799 -0x28 0x577c0 //0x28 0x59540 -0x29 0x04783 -0x2a 0x00001 -0x2b 0x21334 - -//Fractional-N table -0x2a 0x00000 -0x2b 0x00054 -0x2a 0x00001 -0x2b 0x00808 -0x2b 0x53333 -0x2c 0x0000c -0x2a 0x00002 -0x2b 0x00808 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00003 -0x2b 0x00808 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00004 -0x2b 0x00808 -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x00005 -0x2b 0x00808 -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x00006 -0x2b 0x00709 -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x00007 -0x2b 0x00709 -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x00008 -0x2b 0x0060a -0x2b 0x4b333 -0x2c 0x0000d -0x2a 0x00009 -0x2b 0x0060a -0x2b 0x53333 -0x2c 0x0000d -0x2a 0x0000a -0x2b 0x0060a -0x2b 0x5b333 -0x2c 0x0000d -0x2a 0x0000b -0x2b 0x0060a -0x2b 0x63333 -0x2c 0x0000d -0x2a 0x0000c -0x2b 0x0060a -0x2b 0x6b333 -0x2c 0x0000d -0x2a 0x0000d -0x2b 0x0060a -0x2b 0x73333 -0x2c 0x0000d -0x2a 0x0000e -0x2b 0x0050b -0x2b 0x66666 //Alex 0x66623 -0x2c 0x0001a - -0x2a 0xe0000 //0x60000 for 1M spurs - -//RF mode table -0x10 0x4000f //TX IQ K -0x11 0xe31fc //Alex_0x231fc //turn on PAD2 -0x10 0x6000f //RX IQ K -0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC -0x10 0x2000f //TX Mode -0x11 0x203f9 // turn on rf tssi -0x10 0x3000f //Alex RX mode -0x11 0xff500 //Alex RX mode -//0x10 0x1000f //standbt mode -//0x11 0x20103 //RF lpbk switches on if at APK mode -0x10 0x00000 //Alex shut down mode -0x11 0x00000 //Alex shut down mode -0x10 0x8000f //Alex low power RX mode -0x11 0x3f100 // Alex low power RX mode -0x10 0x9000f //Alex low power idle mode -0x11 0x23100 //Alex power idle mode - -//RXAGC_RXHP table - jerry for ACPR -0x12 0xd8000 //0x32000; d4000 -0x12 0x90000 //0x71000; 90000 -0x12 0x51000 //0xb0000; 51000 -0x12 0x12000 //0xfc000; 12000 - -//TX gain table -0x13 0x287af -0x13 0x244b7 -0x13 0x204ab -0x13 0x1c49f -0x13 0x18493 -0x13 0x14297 -0x13 0x10295 -0x13 0x0c298 -0x13 0x0819c -0x13 0x040a8 -0x13 0x0001c - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 - - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - - - -0x00 0x10159 //standby mode -0x18 0x0f401 //LC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1f 0x80003 //RC calibration -0xfe // delay 50ms -0xfe // delay 50ms -0x1e 0x44457 -0x1f 0x80000 -0x00 0x30159 //RX mode - -0xff 0xffff - - - - +//100701 +//////////////////////// +//0x26 OFDM CCK +// 0x4f000 0xf400 +//////////////////////// +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb1 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e52c +0x0e 0x39ce7 +0x0f 0x00451 +0x19 0x00000 +0x1a 0x00255 //12255 //jerry-0x00255 for high power CCK ACPR +0x1b 0x60a00 //RSSI +0x1c 0xfc378 //Alex 0xfc300 +0x1d 0xa1250 +0x1e 0x4445f //RC calibration power on +0x1f 0x80001 //RC calibration power on +0x20 0x0b614 +0x21 0x6c000 //idac poweron +0x22 0x0083c //Arthur-adjust PAPE voltage +0x23 0x01558 +0x24 0x00060 // enabile temp meter +0x25 0x00483 //0x00583 //0x00483 for unlock issue +0x26 0x4f000 +0x27 0xec7d9 //0x27 0xcc799 +0x28 0x577c0 //0x28 0x59540 +0x29 0x04783 +0x2a 0x00001 +0x2b 0x21334 + +//Fractional-N table +0x2a 0x00000 +0x2b 0x00054 +0x2a 0x00001 +0x2b 0x00808 +0x2b 0x53333 +0x2c 0x0000c +0x2a 0x00002 +0x2b 0x00808 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00003 +0x2b 0x00808 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00004 +0x2b 0x00808 +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x00005 +0x2b 0x00808 +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x00006 +0x2b 0x00709 +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x00007 +0x2b 0x00709 +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x00008 +0x2b 0x0060a +0x2b 0x4b333 +0x2c 0x0000d +0x2a 0x00009 +0x2b 0x0060a +0x2b 0x53333 +0x2c 0x0000d +0x2a 0x0000a +0x2b 0x0060a +0x2b 0x5b333 +0x2c 0x0000d +0x2a 0x0000b +0x2b 0x0060a +0x2b 0x63333 +0x2c 0x0000d +0x2a 0x0000c +0x2b 0x0060a +0x2b 0x6b333 +0x2c 0x0000d +0x2a 0x0000d +0x2b 0x0060a +0x2b 0x73333 +0x2c 0x0000d +0x2a 0x0000e +0x2b 0x0050b +0x2b 0x66666 //Alex 0x66623 +0x2c 0x0001a + +0x2a 0xe0000 //0x60000 for 1M spurs + +//RF mode table +0x10 0x4000f //TX IQ K +0x11 0xe31fc //Alex_0x231fc //turn on PAD2 +0x10 0x6000f //RX IQ K +0x11 0xff9f8 //Alex 0x3f9f8 //turn on RXBB BFAC +0x10 0x2000f //TX Mode +0x11 0x203f9 // turn on rf tssi +0x10 0x3000f //Alex RX mode +0x11 0xff500 //Alex RX mode +//0x10 0x1000f //standbt mode +//0x11 0x20103 //RF lpbk switches on if at APK mode +0x10 0x00000 //Alex shut down mode +0x11 0x00000 //Alex shut down mode +0x10 0x8000f //Alex low power RX mode +0x11 0x3f100 // Alex low power RX mode +0x10 0x9000f //Alex low power idle mode +0x11 0x23100 //Alex power idle mode + +//RXAGC_RXHP table - jerry for ACPR +0x12 0xd8000 //0x32000; d4000 +0x12 0x90000 //0x71000; 90000 +0x12 0x51000 //0xb0000; 51000 +0x12 0x12000 //0xfc000; 12000 + +//TX gain table +0x13 0x287af +0x13 0x244b7 +0x13 0x204ab +0x13 0x1c49f +0x13 0x18493 +0x13 0x14297 +0x13 0x10295 +0x13 0x0c298 +0x13 0x0819c +0x13 0x040a8 +0x13 0x0001c + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 + + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + + + +0x00 0x10159 //standby mode +0x18 0x0f401 //LC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1f 0x80003 //RC calibration +0xfe // delay 50ms +0xfe // delay 50ms +0x1e 0x44457 +0x1f 0x80000 +0x00 0x30159 //RX mode + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_b_2T.txt b/package/kernel/rtl8192cd/data/radio_b_2T.txt old mode 100755 new mode 100644 index 19428e28975..4892e8bb58f --- a/package/kernel/rtl8192cd/data/radio_b_2T.txt +++ b/package/kernel/rtl8192cd/data/radio_b_2T.txt @@ -1,34 +1,34 @@ -//091201 -0x00 0x30159 //RX mode -0x01 0x30001 //TRX IQGEN Current -0x02 0x19000 //TX IQGEN Current -0X09 0X2044f -0x0a 0x00fb0 -0x0b 0xd4c0b -0x0c 0x8992e -0x0d 0x0c52e -0x0e 0x42108 -0x0f 0x00451 - -//TX gain table -0x13 0x28fb3 -0x13 0x247a7 -0x13 0x205a3 -0x13 0x1c3a6 -0x13 0x182a9 -0x13 0x142ac -0x13 0x101b0 -0x13 0x0c1a4 -0x13 0x080b0 -0x13 0x040a4 -0x13 0x0001c - - -//IPA bias table -0x15 0x0f433 - -//TX table II -0x16 0xe0336 -0x16 0xe033a for MCS15 CH3 - +//091201 +0x00 0x30159 //RX mode +0x01 0x30001 //TRX IQGEN Current +0x02 0x19000 //TX IQGEN Current +0X09 0X2044f +0x0a 0x00fb0 +0x0b 0xd4c0b +0x0c 0x8992e +0x0d 0x0c52e +0x0e 0x42108 +0x0f 0x00451 + +//TX gain table +0x13 0x28fb3 +0x13 0x247a7 +0x13 0x205a3 +0x13 0x1c3a6 +0x13 0x182a9 +0x13 0x142ac +0x13 0x101b0 +0x13 0x0c1a4 +0x13 0x080b0 +0x13 0x040a4 +0x13 0x0001c + + +//IPA bias table +0x15 0x0f433 + +//TX table II +0x16 0xe0336 +0x16 0xe033a for MCS15 CH3 + 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data/radio_b_2T_n.txt b/package/kernel/rtl8192cd/data/radio_b_2T_n.txt old mode 100755 new mode 100644 index f2382bad3eb..288cc34378d --- a/package/kernel/rtl8192cd/data/radio_b_2T_n.txt +++ b/package/kernel/rtl8192cd/data/radio_b_2T_n.txt @@ -1,57 +1,57 @@ -//100204 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb0 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e52c -0x0e 0x39ce7 -0x0f 0x00451 - -//RXAGC_RXHP table -0x12 0x32000 -0x12 0x71000 -0x12 0xb0000 -0x12 0xfc000 - -//TX gain table -0x13 0x287af -0x13 0x244b7 -0x13 0x204ab -0x13 0x1c49f -0x13 0x18493 -0x13 0x14297 -0x13 0x10295 -0x13 0x0c298 -0x13 0x0819c -0x13 0x040a8 -0x13 0x0001c - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 - - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - -0xff 0xffff - - - - +//100204 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb0 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e52c +0x0e 0x39ce7 +0x0f 0x00451 + +//RXAGC_RXHP table +0x12 0x32000 +0x12 0x71000 +0x12 0xb0000 +0x12 0xfc000 + +//TX gain table +0x13 0x287af +0x13 0x244b7 +0x13 0x204ab +0x13 0x1c49f +0x13 0x18493 +0x13 0x14297 +0x13 0x10295 +0x13 0x0c298 +0x13 0x0819c +0x13 0x040a8 +0x13 0x0001c + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 + + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/radio_b_2T_n_hp.txt b/package/kernel/rtl8192cd/data/radio_b_2T_n_hp.txt index 2539298b588..3d4084e89ad 100644 --- a/package/kernel/rtl8192cd/data/radio_b_2T_n_hp.txt +++ b/package/kernel/rtl8192cd/data/radio_b_2T_n_hp.txt @@ -1,47 +1,47 @@ -//100701 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb1 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e529 //jerry-low gain for ext.PA -0x0e 0x39ce7 -0x0f 0x00451 -//RXAGC_RXHP table - jerry for ACPR -0x12 0xd8000 //0x32000; d4000 -0x12 0x90000 //0x71000; 90000 -0x12 0x51000 //0xb0000; 51000 -0x12 0x12000 //0xfc000; 12000 -//TX gain table - Arthur -0x13 0x28fa8 //Arthur+BS 2011-12-27 old:0x24fa8 //jerry-old 0x28fb4 -0x13 0x24fa8 -0x13 0x207a4 -0x13 0x1c3b0 //jerry-0x1c3b0 for 39-40 nonlinear issue -0x13 0x183a4 -0x13 0x14398 -0x13 0x101a4 -0x13 0x0c198 -0x13 0x080a4 -0x13 0x04098 -0x13 0x00014 -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain -0xff 0xffff - +//100701 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb1 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e529 //jerry-low gain for ext.PA +0x0e 0x39ce7 +0x0f 0x00451 +//RXAGC_RXHP table - jerry for ACPR +0x12 0xd8000 //0x32000; d4000 +0x12 0x90000 //0x71000; 90000 +0x12 0x51000 //0xb0000; 51000 +0x12 0x12000 //0xfc000; 12000 +//TX gain table - Arthur +0x13 0x28fa8 //Arthur+BS 2011-12-27 old:0x24fa8 //jerry-old 0x28fb4 +0x13 0x24fa8 +0x13 0x207a4 +0x13 0x1c3b0 //jerry-0x1c3b0 for 39-40 nonlinear issue +0x13 0x183a4 +0x13 0x14398 +0x13 0x101a4 +0x13 0x0c198 +0x13 0x080a4 +0x13 0x04098 +0x13 0x00014 +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain +0xff 0xffff + diff --git a/package/kernel/rtl8192cd/data/radio_b_2T_n_lna.txt b/package/kernel/rtl8192cd/data/radio_b_2T_n_lna.txt old mode 100755 new mode 100644 index 761a74343fe..9be12cf56c4 --- a/package/kernel/rtl8192cd/data/radio_b_2T_n_lna.txt +++ b/package/kernel/rtl8192cd/data/radio_b_2T_n_lna.txt @@ -1,57 +1,57 @@ -//100701 -0x00 0x30159 //RX mode -0x01 0x31284 //TRX IQGEN Current -0x02 0x98000 //TX IQGEN Current -0x03 0x18c63 -0x04 0x210e7 -0X09 0X2044f -0x0a 0x1adb1 -0x0b 0x54867 -0x0c 0x8992e -0x0d 0x0e52c -0x0e 0x39ce7 -0x0f 0x00451 - -//RXAGC_RXHP table - jerry for ACPR -0x12 0xd8000 //0x32000; d4000 -0x12 0x90000 //0x71000; 90000 -0x12 0x51000 //0xb0000; 51000 -0x12 0x12000 //0xfc000; 12000 - -//TX gain table -0x13 0x287af -0x13 0x244b7 -0x13 0x204ab -0x13 0x1c49f -0x13 0x18493 -0x13 0x14297 -0x13 0x10295 -0x13 0x0c298 -0x13 0x0819c -0x13 0x040a8 -0x13 0x0001c - -//BIAS table -0x14 0x1944c -0x14 0x59444 -0x14 0x9944c -0x14 0xd9444 - -//IPA bias table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -0x15 0xcf424 - - -//TX table II -0x16 0xe0330 //High gain -0x16 0xa0330 //middle gain -0x16 0x60330 //low gain -0x16 0x20330 //ultra low gain - -0xff 0xffff - - - - +//100701 +0x00 0x30159 //RX mode +0x01 0x31284 //TRX IQGEN Current +0x02 0x98000 //TX IQGEN Current +0x03 0x18c63 +0x04 0x210e7 +0X09 0X2044f +0x0a 0x1adb1 +0x0b 0x54867 +0x0c 0x8992e +0x0d 0x0e52c +0x0e 0x39ce7 +0x0f 0x00451 + +//RXAGC_RXHP table - jerry for ACPR +0x12 0xd8000 //0x32000; d4000 +0x12 0x90000 //0x71000; 90000 +0x12 0x51000 //0xb0000; 51000 +0x12 0x12000 //0xfc000; 12000 + +//TX gain table +0x13 0x287af +0x13 0x244b7 +0x13 0x204ab +0x13 0x1c49f +0x13 0x18493 +0x13 0x14297 +0x13 0x10295 +0x13 0x0c298 +0x13 0x0819c +0x13 0x040a8 +0x13 0x0001c + +//BIAS table +0x14 0x1944c +0x14 0x59444 +0x14 0x9944c +0x14 0xd9444 + +//IPA bias table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +0x15 0xcf424 + + +//TX table II +0x16 0xe0330 //High gain +0x16 0xa0330 //middle gain +0x16 0x60330 //low gain +0x16 0x20330 //ultra low gain + +0xff 0xffff + + + + diff --git a/package/kernel/rtl8192cd/data/rtl8192cfwn.bin b/package/kernel/rtl8192cd/data/rtl8192cfwn.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/data/rtl8192cfwua.bin b/package/kernel/rtl8192cd/data/rtl8192cfwua.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/data_8723/PHY_REG_PG_8723.txt b/package/kernel/rtl8192cd/data_8723/PHY_REG_PG_8723.txt index 267f669849a..8c13218e349 100644 --- a/package/kernel/rtl8192cd/data_8723/PHY_REG_PG_8723.txt +++ b/package/kernel/rtl8192cd/data_8723/PHY_REG_PG_8723.txt @@ -1,11 +1,11 @@ -//RTL8723B_MP_Parameter_D-cut_v17_20150211 -#[v1][Exact]# -#[2.4G][A]# -[1Tx] 0xe08 0x0000ff00 0 0 19 0 // TXAGC codeword (H-byte->L-byte)={1M} -[1Tx] 0x86c 0xffffff00 16 17 18 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M} -[1Tx] 0xe00 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -[1Tx] 0xe04 0xffffffff 14 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -[1Tx] 0xe10 0xffffffff 19 20 21 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -[1Tx] 0xe14 0xffffffff 13 15 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -#[END]# -0xffff 0xffff +//RTL8723B_MP_Parameter_D-cut_v17_20150211 +#[v1][Exact]# +#[2.4G][A]# +[1Tx] 0xe08 0x0000ff00 0 0 19 0 // TXAGC codeword (H-byte->L-byte)={1M} +[1Tx] 0x86c 0xffffff00 16 17 18 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M} +[1Tx] 0xe00 0xffffffff 20 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +[1Tx] 0xe04 0xffffffff 14 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +[1Tx] 0xe10 0xffffffff 19 20 21 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +[1Tx] 0xe14 0xffffffff 13 15 17 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +#[END]# +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8723/TXPWR_LMT_8723.txt b/package/kernel/rtl8192cd/data_8723/TXPWR_LMT_8723.txt index 50225aba94b..d61124f2a32 100644 --- a/package/kernel/rtl8192cd/data_8723/TXPWR_LMT_8723.txt +++ b/package/kernel/rtl8192cd/data_8723/TXPWR_LMT_8723.txt @@ -1,162 +1,162 @@ -//RTL8723B_MP_Parameter_D-cut_v17_20150211 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G -// Bandwidth: 20/40 MHZ -// RF Path: 1Transmit RF -// Rate Section: CCK/OFDM/HT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test please write the smaller tx power limit of RF A or B. -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// - -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 16 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 16 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END - -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 14 16 16 -CH02 14 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 14 16 16 -CH11 14 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 13 16 16 -CH02 13 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 13 16 16 -CH11 13 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 16 16 -CH02 16 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 16 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 13 16 16 -CH04 13 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 13 16 16 -CH09 13 16 16 -CH10 13 16 16 -CH11 13 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 16 15 15 -CH05 16 15 15 -CH06 16 15 15 -CH07 16 15 15 -CH08 16 15 15 -CH09 16 15 15 -CH10 16 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END - - - - - - - - - - - +//RTL8723B_MP_Parameter_D-cut_v17_20150211 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G +// Bandwidth: 20/40 MHZ +// RF Path: 1Transmit RF +// Rate Section: CCK/OFDM/HT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test please write the smaller tx power limit of RF A or B. +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// + +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 16 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 16 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END + +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 14 16 16 +CH02 14 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 14 16 16 +CH11 14 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 13 16 16 +CH02 13 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 13 16 16 +CH11 13 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 16 16 +CH02 16 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 16 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 13 16 16 +CH04 13 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 13 16 16 +CH09 13 16 16 +CH10 13 16 16 +CH11 13 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 16 15 15 +CH05 16 15 15 +CH06 16 15 15 +CH07 16 15 15 +CH08 16 15 15 +CH09 16 15 15 +CH10 16 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END + + + + + + + + + + + diff --git a/package/kernel/rtl8192cd/data_8723/TxPowerTrack_AP_8723.txt b/package/kernel/rtl8192cd/data_8723/TxPowerTrack_AP_8723.txt index 7fa29617037..7fe4e429927 100644 --- a/package/kernel/rtl8192cd/data_8723/TxPowerTrack_AP_8723.txt +++ b/package/kernel/rtl8192cd/data_8723/TxPowerTrack_AP_8723.txt @@ -1,25 +1,25 @@ -//RTL8723B_MP_Parameter_D-cut_v17_20150211 -//RTL8723BE_20130304 -//=======================================================================================================================================// -// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // -//=======================================================================================================================================// -[2G][A][+][CCK] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKA_P -[2G][A][-][CCK] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKA_N -[2G][B][+][CCK] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKB_P -[2G][B][-][CCK] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKB_N -[2G][A][+][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GA_P -[2G][A][-][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15} //2GA_N -[2G][B][+][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GB_P -[2G][B][-][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15} //2GB_N -[5G][A][+][ALL][0] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} //5GLA_P -[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GLA_N -[5G][B][+][ALL][0] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20} //5GLB_P -[5G][B][-][ALL][0] = {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GLB_N -[5G][A][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GMA_P -[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16} //5GMA_N -[5G][B][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20} //5GMB_P -[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GMB_N -[5G][A][+][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GHA_P -[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16} //5GHA_N -[5G][B][+][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GHB_P -[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GHB_N +//RTL8723B_MP_Parameter_D-cut_v17_20150211 +//RTL8723BE_20130304 +//=======================================================================================================================================// +// [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] // +//=======================================================================================================================================// +[2G][A][+][CCK] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKA_P +[2G][A][-][CCK] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKA_N +[2G][B][+][CCK] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKB_P +[2G][B][-][CCK] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GCCKB_N +[2G][A][+][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GA_P +[2G][A][-][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15} //2GA_N +[2G][B][+][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15} //2GB_P +[2G][B][-][ALL] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15} //2GB_N +[5G][A][+][ALL][0] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} //5GLA_P +[5G][A][-][ALL][0] = {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GLA_N +[5G][B][+][ALL][0] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20} //5GLB_P +[5G][B][-][ALL][0] = {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GLB_N +[5G][A][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GMA_P +[5G][A][-][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16} //5GMA_N +[5G][B][+][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20} //5GMB_P +[5G][B][-][ALL][1] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GMB_N +[5G][A][+][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GHA_P +[5G][A][-][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16} //5GHA_N +[5G][B][+][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21} //5GHB_P +[5G][B][-][ALL][2] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14} //5GHB_N diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812.txt old mode 100755 new mode 100644 index 808fb617346..97aca01307f --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812.txt @@ -1,134 +1,134 @@ -0x81c 0xff000001 -0x81c 0xff020001 -0x81c 0xff040001 -0x81c 0xff060001 -0x81c 0xff080001 -0x81c 0xfe0a0001 -0x81c 0xfd0c0001 -0x81c 0xfc0e0001 -0x81c 0xfa100001 // Pin=-94dBm -0x81c 0xf9120001 // Pin=-92dBm -0x81c 0xf8140001 // Pin=-90dBm -0x81c 0xf7160001 // Pin=-88dBm -0x81c 0xf6180001 // Pin=-86dBm -0x81c 0xf51a0001 // Pin=-84dBm -0x81c 0xf41c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff800001 -0x81c 0xff820001 -0x81c 0xff840001 -0x81c 0xff860001 -0x81c 0xff880001 -0x81c 0xff8a0001 -0x81c 0xfe8c0001 -0x81c 0xfd8e0001 -0x81c 0xfc900001 // Pin=-94dBm -0x81c 0xfb920001 // Pin=-92dBm -0x81c 0xfa940001 // Pin=-90dBm -0x81c 0xf9960001 // Pin=-88dBm -0x81c 0xf8980001 // Pin=-86dBm -0x81c 0xf79a0001 // Pin=-84dBm -0x81c 0xf69c0001 // Pin=-82dBm -0x81c 0xf59e0001 // Pin=-80dBm -0x81c 0xf4a00001 // Pin=-78dBm -0x81c 0xf3a20001 // Pin=-76dBm -0x81c 0xf2a40001 // Pin=-74dBm -0x81c 0xf1a60001 // Pin=-72dBm -0x81c 0xf0a80001 // Pin=-70dBm -0x81c 0xefaa0001 // Pin=-68dBm -0x81c 0xeeac0001 // Pin=-66dBm -0x81c 0xedae0001 // Pin=-64dBm -0x81c 0xecb00001 // Pin=-62dBm -0x81c 0xebb20001 // Pin=-60dBm -0x81c 0xeab40001 // Pin=-58dBm -0x81c 0xe9b60001 // Pin=-56dBm -0x81c 0xe8b80001 // Pin=-54dBm -0x81c 0xe7ba0001 // Pin=-52dBm -0x81c 0xe6bc0001 // Pin=-50dBm -0x81c 0xcabe0001 // Pin=-48dBm -0x81c 0xc9c00001 // Pin=-46dBm -//0x81c 0xe5c20001 // Pin=-44dBm -//0x81c 0xe4c40001 // Pin=-42dBm -0x81c 0xc8c20001 // Pin=-44dBm -0x81c 0xc7c40001 // Pin=-42dBm -0x81c 0xc6c60001 // Pin=-40dBm -//0x81c 0xaac80001 // Pin=-38dBm -0x81c 0xc5c80001 // Pin=-38dBm -0x81c 0xc4ca0001 // Pin=-36dBm -0x81c 0xc3cc0001 // Pin=-34dBm -0x81c 0xc2ce0001 // Pin=-32dBm -0x81c 0xc1d00001 // Pin=-30dBm -0x81c 0xa5d20001 // Pin=-28dBm -0x81c 0xa5d40001 // Pin=-26dBm -0x81c 0xa4d60001 // Pin=-24dBm -0x81c 0xa3d80001 // Pin=-22dBm -0x81c 0x4eda0001 // Pin=-20dBm -0x81c 0x4ddc0001 // Pin=-18dBm -0x81c 0x4cde0001 // Pin=-16dBm -0x81c 0x4be00001 // Pin=-14dBm -0x81c 0x4ae20001 // Pin=-12dBm -0x81c 0x49e40001 // Pin=-10dBm -0x81c 0x48e60001 // Pin=-08dBm -0x81c 0x47e80001 // Pin=-06dBm -0x81c 0x08ea0001 // Pin=-04dBm -0x81c 0x07ec0001 // Pin=-02dBm -0x81c 0x06ee0001 // Pin=-00dBm -0x81c 0x05f00001 // Pin=+02dBm -0x81c 0x04f20001 // Pin=+04dBm -0x81c 0x03f40001 // Pin=+06dBm -0x81c 0x02f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - +0x81c 0xff000001 +0x81c 0xff020001 +0x81c 0xff040001 +0x81c 0xff060001 +0x81c 0xff080001 +0x81c 0xfe0a0001 +0x81c 0xfd0c0001 +0x81c 0xfc0e0001 +0x81c 0xfa100001 // Pin=-94dBm +0x81c 0xf9120001 // Pin=-92dBm +0x81c 0xf8140001 // Pin=-90dBm +0x81c 0xf7160001 // Pin=-88dBm +0x81c 0xf6180001 // Pin=-86dBm +0x81c 0xf51a0001 // Pin=-84dBm +0x81c 0xf41c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff800001 +0x81c 0xff820001 +0x81c 0xff840001 +0x81c 0xff860001 +0x81c 0xff880001 +0x81c 0xff8a0001 +0x81c 0xfe8c0001 +0x81c 0xfd8e0001 +0x81c 0xfc900001 // Pin=-94dBm +0x81c 0xfb920001 // Pin=-92dBm +0x81c 0xfa940001 // Pin=-90dBm +0x81c 0xf9960001 // Pin=-88dBm +0x81c 0xf8980001 // Pin=-86dBm +0x81c 0xf79a0001 // Pin=-84dBm +0x81c 0xf69c0001 // Pin=-82dBm +0x81c 0xf59e0001 // Pin=-80dBm +0x81c 0xf4a00001 // Pin=-78dBm +0x81c 0xf3a20001 // Pin=-76dBm +0x81c 0xf2a40001 // Pin=-74dBm +0x81c 0xf1a60001 // Pin=-72dBm +0x81c 0xf0a80001 // Pin=-70dBm +0x81c 0xefaa0001 // Pin=-68dBm +0x81c 0xeeac0001 // Pin=-66dBm +0x81c 0xedae0001 // Pin=-64dBm +0x81c 0xecb00001 // Pin=-62dBm +0x81c 0xebb20001 // Pin=-60dBm +0x81c 0xeab40001 // Pin=-58dBm +0x81c 0xe9b60001 // Pin=-56dBm +0x81c 0xe8b80001 // Pin=-54dBm +0x81c 0xe7ba0001 // Pin=-52dBm +0x81c 0xe6bc0001 // Pin=-50dBm +0x81c 0xcabe0001 // Pin=-48dBm +0x81c 0xc9c00001 // Pin=-46dBm +//0x81c 0xe5c20001 // Pin=-44dBm +//0x81c 0xe4c40001 // Pin=-42dBm +0x81c 0xc8c20001 // Pin=-44dBm +0x81c 0xc7c40001 // Pin=-42dBm +0x81c 0xc6c60001 // Pin=-40dBm +//0x81c 0xaac80001 // Pin=-38dBm +0x81c 0xc5c80001 // Pin=-38dBm +0x81c 0xc4ca0001 // Pin=-36dBm +0x81c 0xc3cc0001 // Pin=-34dBm +0x81c 0xc2ce0001 // Pin=-32dBm +0x81c 0xc1d00001 // Pin=-30dBm +0x81c 0xa5d20001 // Pin=-28dBm +0x81c 0xa5d40001 // Pin=-26dBm +0x81c 0xa4d60001 // Pin=-24dBm +0x81c 0xa3d80001 // Pin=-22dBm +0x81c 0x4eda0001 // Pin=-20dBm +0x81c 0x4ddc0001 // Pin=-18dBm +0x81c 0x4cde0001 // Pin=-16dBm +0x81c 0x4be00001 // Pin=-14dBm +0x81c 0x4ae20001 // Pin=-12dBm +0x81c 0x49e40001 // Pin=-10dBm +0x81c 0x48e60001 // Pin=-08dBm +0x81c 0x47e80001 // Pin=-06dBm +0x81c 0x08ea0001 // Pin=-04dBm +0x81c 0x07ec0001 // Pin=-02dBm +0x81c 0x06ee0001 // Pin=-00dBm +0x81c 0x05f00001 // Pin=+02dBm +0x81c 0x04f20001 // Pin=+04dBm +0x81c 0x03f40001 // Pin=+06dBm +0x81c 0x02f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_hp.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_hp.txt index 978971f4c72..0ce3f6c1b09 100644 --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_hp.txt @@ -1,134 +1,134 @@ -0x81c 0xff000001 -0x81c 0xff020001 -0x81c 0xff040001 -0x81c 0xff060001 -0x81c 0xff080001 -0x81c 0xfe0a0001 -0x81c 0xfd0c0001 -0x81c 0xfc0e0001 -0x81c 0xfa100001 // Pin=-94dBm -0x81c 0xf9120001 // Pin=-92dBm -0x81c 0xf8140001 // Pin=-90dBm -0x81c 0xf7160001 // Pin=-88dBm -0x81c 0xf6180001 // Pin=-86dBm -0x81c 0xf51a0001 // Pin=-84dBm -0x81c 0xf41c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfd800001 -0x81c 0xfc820001 -0x81c 0xfb840001 -0x81c 0xfa860001 -0x81c 0xf9880001 -0x81c 0xf88a0001 -0x81c 0xf78c0001 -0x81c 0xf68e0001 -0x81c 0xf5900001 // Pin=-94dBm -0x81c 0xf4920001 // Pin=-92dBm -0x81c 0xf3940001 // Pin=-90dBm -0x81c 0xf2960001 // Pin=-88dBm -0x81c 0xf1980001 // Pin=-86dBm -0x81c 0xf09a0001 // Pin=-84dBm -0x81c 0xef9c0001 // Pin=-82dBm -0x81c 0xee9e0001 // Pin=-80dBm -0x81c 0xeda00001 // Pin=-78dBm -0x81c 0xeca20001 // Pin=-76dBm -0x81c 0xeba40001 // Pin=-74dBm -0x81c 0xeaa60001 // Pin=-72dBm -0x81c 0xe9a80001 // Pin=-70dBm -0x81c 0xe8aa0001 // Pin=-68dBm -0x81c 0xe7ac0001 // Pin=-66dBm -0x81c 0xe6ae0001 // Pin=-64dBm -0x81c 0xe5b00001 // Pin=-62dBm,..cb or e5 -0x81c 0xcab20001 // Pin=-60dBm -0x81c 0xc9b40001 // Pin=-58dBm -0x81c 0xc8b60001 // Pin=-56dBm -0x81c 0xc7b80001 // Pin=-54dBm -0x81c 0xc6ba0001 // Pin=-52dBm -0x81c 0xc5bc0001 // Pin=-50dBm -0x81c 0xc4be0001 // Pin=-48dBm -0x81c 0xc3c00001 // Pin=-46dBm -//0x81c 0xe5c20001 // Pin=-44dBm -//0x81c 0xe4c40001 // Pin=-42dBm -0x81c 0xc2c20001 // Pin=-44dBm -0x81c 0xc1c40001 // Pin=-42dBm,....c1 or a5 -0x81c 0xa5c60001 // Pin=-40dBm -//0x81c 0xaac80001 // Pin=-38dBm -0x81c 0xa4c80001 // Pin=-38dBm -0x81c 0xa3ca0001 // Pin=-36dBm -0x81c 0x4ecc0001 // Pin=-34dBm -0x81c 0x4dce0001 // Pin=-32dBm -0x81c 0x4cd00001 // Pin=-30dBm -0x81c 0x4bd20001 // Pin=-28dBm -0x81c 0x4ad40001 // Pin=-26dBm -0x81c 0x49d60001 // Pin=-24dBm -0x81c 0x48d80001 // Pin=-22dBm -0x81c 0x09da0001 // Pin=-20dBm,....47 or 09 -0x81c 0x08dc0001 // Pin=-18dBm -0x81c 0x07de0001 // Pin=-16dBm -0x81c 0x06e00001 // Pin=-14dBm -0x81c 0x05e20001 // Pin=-12dBm -0x81c 0x04e40001 // Pin=-10dBm -0x81c 0x03e60001 // Pin=-08dBm -0x81c 0x02e80001 // Pin=-06dBm -0x81c 0x01ea0001 // Pin=-04dBm -0x81c 0x01ec0001 // Pin=-02dBm -0x81c 0x01ee0001 // Pin=-00dBm -0x81c 0x01f00001 // Pin=+02dBm -0x81c 0x01f20001 // Pin=+04dBm -0x81c 0x01f40001 // Pin=+06dBm -0x81c 0x01f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - +0x81c 0xff000001 +0x81c 0xff020001 +0x81c 0xff040001 +0x81c 0xff060001 +0x81c 0xff080001 +0x81c 0xfe0a0001 +0x81c 0xfd0c0001 +0x81c 0xfc0e0001 +0x81c 0xfa100001 // Pin=-94dBm +0x81c 0xf9120001 // Pin=-92dBm +0x81c 0xf8140001 // Pin=-90dBm +0x81c 0xf7160001 // Pin=-88dBm +0x81c 0xf6180001 // Pin=-86dBm +0x81c 0xf51a0001 // Pin=-84dBm +0x81c 0xf41c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfd800001 +0x81c 0xfc820001 +0x81c 0xfb840001 +0x81c 0xfa860001 +0x81c 0xf9880001 +0x81c 0xf88a0001 +0x81c 0xf78c0001 +0x81c 0xf68e0001 +0x81c 0xf5900001 // Pin=-94dBm +0x81c 0xf4920001 // Pin=-92dBm +0x81c 0xf3940001 // Pin=-90dBm +0x81c 0xf2960001 // Pin=-88dBm +0x81c 0xf1980001 // Pin=-86dBm +0x81c 0xf09a0001 // Pin=-84dBm +0x81c 0xef9c0001 // Pin=-82dBm +0x81c 0xee9e0001 // Pin=-80dBm +0x81c 0xeda00001 // Pin=-78dBm +0x81c 0xeca20001 // Pin=-76dBm +0x81c 0xeba40001 // Pin=-74dBm +0x81c 0xeaa60001 // Pin=-72dBm +0x81c 0xe9a80001 // Pin=-70dBm +0x81c 0xe8aa0001 // Pin=-68dBm +0x81c 0xe7ac0001 // Pin=-66dBm +0x81c 0xe6ae0001 // Pin=-64dBm +0x81c 0xe5b00001 // Pin=-62dBm,..cb or e5 +0x81c 0xcab20001 // Pin=-60dBm +0x81c 0xc9b40001 // Pin=-58dBm +0x81c 0xc8b60001 // Pin=-56dBm +0x81c 0xc7b80001 // Pin=-54dBm +0x81c 0xc6ba0001 // Pin=-52dBm +0x81c 0xc5bc0001 // Pin=-50dBm +0x81c 0xc4be0001 // Pin=-48dBm +0x81c 0xc3c00001 // Pin=-46dBm +//0x81c 0xe5c20001 // Pin=-44dBm +//0x81c 0xe4c40001 // Pin=-42dBm +0x81c 0xc2c20001 // Pin=-44dBm +0x81c 0xc1c40001 // Pin=-42dBm,....c1 or a5 +0x81c 0xa5c60001 // Pin=-40dBm +//0x81c 0xaac80001 // Pin=-38dBm +0x81c 0xa4c80001 // Pin=-38dBm +0x81c 0xa3ca0001 // Pin=-36dBm +0x81c 0x4ecc0001 // Pin=-34dBm +0x81c 0x4dce0001 // Pin=-32dBm +0x81c 0x4cd00001 // Pin=-30dBm +0x81c 0x4bd20001 // Pin=-28dBm +0x81c 0x4ad40001 // Pin=-26dBm +0x81c 0x49d60001 // Pin=-24dBm +0x81c 0x48d80001 // Pin=-22dBm +0x81c 0x09da0001 // Pin=-20dBm,....47 or 09 +0x81c 0x08dc0001 // Pin=-18dBm +0x81c 0x07de0001 // Pin=-16dBm +0x81c 0x06e00001 // Pin=-14dBm +0x81c 0x05e20001 // Pin=-12dBm +0x81c 0x04e40001 // Pin=-10dBm +0x81c 0x03e60001 // Pin=-08dBm +0x81c 0x02e80001 // Pin=-06dBm +0x81c 0x01ea0001 // Pin=-04dBm +0x81c 0x01ec0001 // Pin=-02dBm +0x81c 0x01ee0001 // Pin=-00dBm +0x81c 0x01f00001 // Pin=+02dBm +0x81c 0x01f20001 // Pin=+04dBm +0x81c 0x01f40001 // Pin=+06dBm +0x81c 0x01f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_default.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_default.txt index f618c064ec5..bbdf8ba9d44 100644 --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_default.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_default.txt @@ -1,136 +1,136 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xff060001 // Pin=-104dBm -0x81c 0xff080001 // Pin=-102dBm -0x81c 0xfe0a0001 // Pin=-100dBm -0x81c 0xfd0c0001 // Pin=-98dBm -0x81c 0xfc0e0001 // Pin=-96dBm -0x81c 0xfb100001 // Pin=-94dBm -0x81c 0xfa120001 // Pin=-92dBm -0x81c 0xf9140001 // Pin=-90dBm -0x81c 0xf8160001 // Pin=-88dBm -0x81c 0xf7180001 // Pin=-86dBm -0x81c 0xf61a0001 // Pin=-84dBm -0x81c 0xf51c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff800001 // Pin=-110dBm -0x81c 0xff820001 // Pin=-108dBm -0x81c 0xff840001 // Pin=-106dBm -0x81c 0xfe860001 // Pin=-104dBm -0x81c 0xfd880001 // Pin=-102dBm -0x81c 0xfc8a0001 // Pin=-100dBm -0x81c 0xfb8c0001 // Pin=-98dBm -0x81c 0xfa8e0001 // Pin=-96dBm -0x81c 0xf9900001 // Pin=-94dBm -0x81c 0xf8920001 // Pin=-92dBm -0x81c 0xf7940001 // Pin=-90dBm -0x81c 0xf6960001 // Pin=-88dBm -0x81c 0xf5980001 // Pin=-86dBm -0x81c 0xf49a0001 // Pin=-84dBm -0x81c 0xf39c0001 // Pin=-82dBm -0x81c 0xf29e0001 // Pin=-80dBm -0x81c 0xf1a00001 // Pin=-78dBm -0x81c 0xf0a20001 // Pin=-76dBm -0x81c 0xefa40001 // Pin=-74dBm -0x81c 0xeea60001 // Pin=-72dBm -0x81c 0xeda80001 // Pin=-70dBm -0x81c 0xecaa0001 // Pin=-68dBm -0x81c 0xebac0001 // Pin=-66dBm -0x81c 0xeaae0001 // Pin=-64dBm -0x81c 0xe9b00001 // Pin=-62dBm -0x81c 0xe8b20001 // Pin=-60dBm -0x81c 0xe7b40001 // Pin=-58dBm -0x81c 0xe6b60001 // Pin=-56dBm -0x81c 0xe5b80001 // Pin=-54dBm -0x81c 0xe4ba0001 // Pin=-52dBm -0x81c 0xe3bc0001 // Pin=-50dBm -0x81c 0xa8be0001 // Pin=-48dBm -0x81c 0xa7c00001 // Pin=-46dBm -0x81c 0xa6c20001 // Pin=-44dBm -0x81c 0xa5c40001 // Pin=-42dBm -0x81c 0xa4c60001 // Pin=-40dBm -0x81c 0xa3c80001 // Pin=-38dBm -0x81c 0xa2ca0001 // Pin=-36dBm -0x81c 0xa1cc0001 // Pin=-34dBm -0x81c 0x68ce0001 // Pin=-32dBm -0x81c 0x67d00001 // Pin=-30dBm -0x81c 0x66d20001 // Pin=-28dBm -0x81c 0x65d40001 // Pin=-26dBm -0x81c 0x64d60001 // Pin=-24dBm -0x81c 0x47d80001 // Pin=-22dBm -0x81c 0x46da0001 // Pin=-20dBm -0x81c 0x45dc0001 // Pin=-18dBm -0x81c 0x44de0001 // Pin=-16dBm -0x81c 0x43e00001 // Pin=-14dBm -0x81c 0x42e20001 // Pin=-12dBm -0x81c 0x08e40001 // Pin=-10dBm -0x81c 0x07e60001 // Pin=-08dBm -0x81c 0x06e80001 // Pin=-06dBm -0x81c 0x05ea0001 // Pin=-04dBm -0x81c 0x04ec0001 // Pin=-02dBm -0x81c 0x03ee0001 // Pin=-00dBm -0x81c 0x02f00001 // Pin=+02dBm -0x81c 0x01f20001 // Pin=+04dBm -0x81c 0x01f40001 // Pin=+06dBm -0x81c 0x01f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table +//RL6286_MAC_PHY_Parameter_v041_20131127 +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xff060001 // Pin=-104dBm +0x81c 0xff080001 // Pin=-102dBm +0x81c 0xfe0a0001 // Pin=-100dBm +0x81c 0xfd0c0001 // Pin=-98dBm +0x81c 0xfc0e0001 // Pin=-96dBm +0x81c 0xfb100001 // Pin=-94dBm +0x81c 0xfa120001 // Pin=-92dBm +0x81c 0xf9140001 // Pin=-90dBm +0x81c 0xf8160001 // Pin=-88dBm +0x81c 0xf7180001 // Pin=-86dBm +0x81c 0xf61a0001 // Pin=-84dBm +0x81c 0xf51c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff800001 // Pin=-110dBm +0x81c 0xff820001 // Pin=-108dBm +0x81c 0xff840001 // Pin=-106dBm +0x81c 0xfe860001 // Pin=-104dBm +0x81c 0xfd880001 // Pin=-102dBm +0x81c 0xfc8a0001 // Pin=-100dBm +0x81c 0xfb8c0001 // Pin=-98dBm +0x81c 0xfa8e0001 // Pin=-96dBm +0x81c 0xf9900001 // Pin=-94dBm +0x81c 0xf8920001 // Pin=-92dBm +0x81c 0xf7940001 // Pin=-90dBm +0x81c 0xf6960001 // Pin=-88dBm +0x81c 0xf5980001 // Pin=-86dBm +0x81c 0xf49a0001 // Pin=-84dBm +0x81c 0xf39c0001 // Pin=-82dBm +0x81c 0xf29e0001 // Pin=-80dBm +0x81c 0xf1a00001 // Pin=-78dBm +0x81c 0xf0a20001 // Pin=-76dBm +0x81c 0xefa40001 // Pin=-74dBm +0x81c 0xeea60001 // Pin=-72dBm +0x81c 0xeda80001 // Pin=-70dBm +0x81c 0xecaa0001 // Pin=-68dBm +0x81c 0xebac0001 // Pin=-66dBm +0x81c 0xeaae0001 // Pin=-64dBm +0x81c 0xe9b00001 // Pin=-62dBm +0x81c 0xe8b20001 // Pin=-60dBm +0x81c 0xe7b40001 // Pin=-58dBm +0x81c 0xe6b60001 // Pin=-56dBm +0x81c 0xe5b80001 // Pin=-54dBm +0x81c 0xe4ba0001 // Pin=-52dBm +0x81c 0xe3bc0001 // Pin=-50dBm +0x81c 0xa8be0001 // Pin=-48dBm +0x81c 0xa7c00001 // Pin=-46dBm +0x81c 0xa6c20001 // Pin=-44dBm +0x81c 0xa5c40001 // Pin=-42dBm +0x81c 0xa4c60001 // Pin=-40dBm +0x81c 0xa3c80001 // Pin=-38dBm +0x81c 0xa2ca0001 // Pin=-36dBm +0x81c 0xa1cc0001 // Pin=-34dBm +0x81c 0x68ce0001 // Pin=-32dBm +0x81c 0x67d00001 // Pin=-30dBm +0x81c 0x66d20001 // Pin=-28dBm +0x81c 0x65d40001 // Pin=-26dBm +0x81c 0x64d60001 // Pin=-24dBm +0x81c 0x47d80001 // Pin=-22dBm +0x81c 0x46da0001 // Pin=-20dBm +0x81c 0x45dc0001 // Pin=-18dBm +0x81c 0x44de0001 // Pin=-16dBm +0x81c 0x43e00001 // Pin=-14dBm +0x81c 0x42e20001 // Pin=-12dBm +0x81c 0x08e40001 // Pin=-10dBm +0x81c 0x07e60001 // Pin=-08dBm +0x81c 0x06e80001 // Pin=-06dBm +0x81c 0x05ea0001 // Pin=-04dBm +0x81c 0x04ec0001 // Pin=-02dBm +0x81c 0x03ee0001 // Pin=-00dBm +0x81c 0x02f00001 // Pin=+02dBm +0x81c 0x01f20001 // Pin=+04dBm +0x81c 0x01f40001 // Pin=+06dBm +0x81c 0x01f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extlna.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extlna.txt index 7d511c1b139..97431979f59 100644 --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extlna.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extlna.txt @@ -1,136 +1,136 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xff060001 // Pin=-104dBm -0x81c 0xff080001 // Pin=-102dBm -0x81c 0xfe0a0001 // Pin=-100dBm -0x81c 0xfd0c0001 // Pin=-98dBm -0x81c 0xfc0e0001 // Pin=-96dBm -0x81c 0xfb100001 // Pin=-94dBm -0x81c 0xfa120001 // Pin=-92dBm -0x81c 0xf9140001 // Pin=-90dBm -0x81c 0xf8160001 // Pin=-88dBm -0x81c 0xf7180001 // Pin=-86dBm -0x81c 0xf61a0001 // Pin=-84dBm -0x81c 0xf51c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfc800001 // Pin=-110dBm -0x81c 0xfb820001 // Pin=-108dBm -0x81c 0xfa840001 // Pin=-106dBm -0x81c 0xf9860001 // Pin=-104dBm -0x81c 0xf8880001 // Pin=-102dBm -0x81c 0xf78a0001 // Pin=-100dBm -0x81c 0xf68c0001 // Pin=-98dBm -0x81c 0xf58e0001 // Pin=-96dBm -0x81c 0xf4900001 // Pin=-94dBm -0x81c 0xf3920001 // Pin=-92dBm -0x81c 0xf2940001 // Pin=-90dBm -0x81c 0xf1960001 // Pin=-88dBm -0x81c 0xf0980001 // Pin=-86dBm -0x81c 0xef9a0001 // Pin=-84dBm -0x81c 0xee9c0001 // Pin=-82dBm -0x81c 0xed9e0001 // Pin=-80dBm -0x81c 0xeca00001 // Pin=-78dBm -0x81c 0xeba20001 // Pin=-76dBm -0x81c 0xeaa40001 // Pin=-74dBm -0x81c 0xe9a60001 // Pin=-72dBm -0x81c 0xe8a80001 // Pin=-70dBm -0x81c 0xe7aa0001 // Pin=-68dBm -0x81c 0xe6ac0001 // Pin=-66dBm -0x81c 0xe5ae0001 // Pin=-64dBm -0x81c 0xe4b00001 // Pin=-62dBm -0x81c 0xe3b20001 // Pin=-60dBm -0x81c 0xa8b40001 // Pin=-58dBm -0x81c 0xa7b60001 // Pin=-56dBm -0x81c 0xa6b80001 // Pin=-54dBm -0x81c 0xa5ba0001 // Pin=-52dBm -0x81c 0xa4bc0001 // Pin=-50dBm -0x81c 0xa3be0001 // Pin=-48dBm -0x81c 0xa2c00001 // Pin=-46dBm -0x81c 0xa1c20001 // Pin=-44dBm -0x81c 0x68c40001 // Pin=-42dBm -0x81c 0x67c60001 // Pin=-40dBm -0x81c 0x66c80001 // Pin=-38dBm -0x81c 0x65ca0001 // Pin=-36dBm -0x81c 0x64cc0001 // Pin=-34dBm -0x81c 0x47ce0001 // Pin=-32dBm -0x81c 0x46d00001 // Pin=-30dBm -0x81c 0x45d20001 // Pin=-28dBm -0x81c 0x44d40001 // Pin=-26dBm -0x81c 0x43d60001 // Pin=-24dBm -0x81c 0x42d80001 // Pin=-22dBm -0x81c 0x08da0001 // Pin=-20dBm -0x81c 0x07dc0001 // Pin=-18dBm -0x81c 0x06de0001 // Pin=-16dBm -0x81c 0x05e00001 // Pin=-14dBm -0x81c 0x04e20001 // Pin=-12dBm -0x81c 0x03e40001 // Pin=-10dBm -0x81c 0x02e60001 // Pin=-08dBm -0x81c 0x01e80001 // Pin=-06dBm -0x81c 0x01ea0001 // Pin=-04dBm -0x81c 0x01ec0001 // Pin=-02dBm -0x81c 0x01ee0001 // Pin=-00dBm -0x81c 0x01f00001 // Pin=+02dBm -0x81c 0x01f20001 // Pin=+04dBm -0x81c 0x01f40001 // Pin=+06dBm -0x81c 0x01f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table +//RL6286_MAC_PHY_Parameter_v041_20131127 +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xff060001 // Pin=-104dBm +0x81c 0xff080001 // Pin=-102dBm +0x81c 0xfe0a0001 // Pin=-100dBm +0x81c 0xfd0c0001 // Pin=-98dBm +0x81c 0xfc0e0001 // Pin=-96dBm +0x81c 0xfb100001 // Pin=-94dBm +0x81c 0xfa120001 // Pin=-92dBm +0x81c 0xf9140001 // Pin=-90dBm +0x81c 0xf8160001 // Pin=-88dBm +0x81c 0xf7180001 // Pin=-86dBm +0x81c 0xf61a0001 // Pin=-84dBm +0x81c 0xf51c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfc800001 // Pin=-110dBm +0x81c 0xfb820001 // Pin=-108dBm +0x81c 0xfa840001 // Pin=-106dBm +0x81c 0xf9860001 // Pin=-104dBm +0x81c 0xf8880001 // Pin=-102dBm +0x81c 0xf78a0001 // Pin=-100dBm +0x81c 0xf68c0001 // Pin=-98dBm +0x81c 0xf58e0001 // Pin=-96dBm +0x81c 0xf4900001 // Pin=-94dBm +0x81c 0xf3920001 // Pin=-92dBm +0x81c 0xf2940001 // Pin=-90dBm +0x81c 0xf1960001 // Pin=-88dBm +0x81c 0xf0980001 // Pin=-86dBm +0x81c 0xef9a0001 // Pin=-84dBm +0x81c 0xee9c0001 // Pin=-82dBm +0x81c 0xed9e0001 // Pin=-80dBm +0x81c 0xeca00001 // Pin=-78dBm +0x81c 0xeba20001 // Pin=-76dBm +0x81c 0xeaa40001 // Pin=-74dBm +0x81c 0xe9a60001 // Pin=-72dBm +0x81c 0xe8a80001 // Pin=-70dBm +0x81c 0xe7aa0001 // Pin=-68dBm +0x81c 0xe6ac0001 // Pin=-66dBm +0x81c 0xe5ae0001 // Pin=-64dBm +0x81c 0xe4b00001 // Pin=-62dBm +0x81c 0xe3b20001 // Pin=-60dBm +0x81c 0xa8b40001 // Pin=-58dBm +0x81c 0xa7b60001 // Pin=-56dBm +0x81c 0xa6b80001 // Pin=-54dBm +0x81c 0xa5ba0001 // Pin=-52dBm +0x81c 0xa4bc0001 // Pin=-50dBm +0x81c 0xa3be0001 // Pin=-48dBm +0x81c 0xa2c00001 // Pin=-46dBm +0x81c 0xa1c20001 // Pin=-44dBm +0x81c 0x68c40001 // Pin=-42dBm +0x81c 0x67c60001 // Pin=-40dBm +0x81c 0x66c80001 // Pin=-38dBm +0x81c 0x65ca0001 // Pin=-36dBm +0x81c 0x64cc0001 // Pin=-34dBm +0x81c 0x47ce0001 // Pin=-32dBm +0x81c 0x46d00001 // Pin=-30dBm +0x81c 0x45d20001 // Pin=-28dBm +0x81c 0x44d40001 // Pin=-26dBm +0x81c 0x43d60001 // Pin=-24dBm +0x81c 0x42d80001 // Pin=-22dBm +0x81c 0x08da0001 // Pin=-20dBm +0x81c 0x07dc0001 // Pin=-18dBm +0x81c 0x06de0001 // Pin=-16dBm +0x81c 0x05e00001 // Pin=-14dBm +0x81c 0x04e20001 // Pin=-12dBm +0x81c 0x03e40001 // Pin=-10dBm +0x81c 0x02e60001 // Pin=-08dBm +0x81c 0x01e80001 // Pin=-06dBm +0x81c 0x01ea0001 // Pin=-04dBm +0x81c 0x01ec0001 // Pin=-02dBm +0x81c 0x01ee0001 // Pin=-00dBm +0x81c 0x01f00001 // Pin=+02dBm +0x81c 0x01f20001 // Pin=+04dBm +0x81c 0x01f40001 // Pin=+06dBm +0x81c 0x01f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extpa.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extpa.txt index f618c064ec5..bbdf8ba9d44 100644 --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extpa.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_extpa.txt @@ -1,136 +1,136 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xff060001 // Pin=-104dBm -0x81c 0xff080001 // Pin=-102dBm -0x81c 0xfe0a0001 // Pin=-100dBm -0x81c 0xfd0c0001 // Pin=-98dBm -0x81c 0xfc0e0001 // Pin=-96dBm -0x81c 0xfb100001 // Pin=-94dBm -0x81c 0xfa120001 // Pin=-92dBm -0x81c 0xf9140001 // Pin=-90dBm -0x81c 0xf8160001 // Pin=-88dBm -0x81c 0xf7180001 // Pin=-86dBm -0x81c 0xf61a0001 // Pin=-84dBm -0x81c 0xf51c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xff800001 // Pin=-110dBm -0x81c 0xff820001 // Pin=-108dBm -0x81c 0xff840001 // Pin=-106dBm -0x81c 0xfe860001 // Pin=-104dBm -0x81c 0xfd880001 // Pin=-102dBm -0x81c 0xfc8a0001 // Pin=-100dBm -0x81c 0xfb8c0001 // Pin=-98dBm -0x81c 0xfa8e0001 // Pin=-96dBm -0x81c 0xf9900001 // Pin=-94dBm -0x81c 0xf8920001 // Pin=-92dBm -0x81c 0xf7940001 // Pin=-90dBm -0x81c 0xf6960001 // Pin=-88dBm -0x81c 0xf5980001 // Pin=-86dBm -0x81c 0xf49a0001 // Pin=-84dBm -0x81c 0xf39c0001 // Pin=-82dBm -0x81c 0xf29e0001 // Pin=-80dBm -0x81c 0xf1a00001 // Pin=-78dBm -0x81c 0xf0a20001 // Pin=-76dBm -0x81c 0xefa40001 // Pin=-74dBm -0x81c 0xeea60001 // Pin=-72dBm -0x81c 0xeda80001 // Pin=-70dBm -0x81c 0xecaa0001 // Pin=-68dBm -0x81c 0xebac0001 // Pin=-66dBm -0x81c 0xeaae0001 // Pin=-64dBm -0x81c 0xe9b00001 // Pin=-62dBm -0x81c 0xe8b20001 // Pin=-60dBm -0x81c 0xe7b40001 // Pin=-58dBm -0x81c 0xe6b60001 // Pin=-56dBm -0x81c 0xe5b80001 // Pin=-54dBm -0x81c 0xe4ba0001 // Pin=-52dBm -0x81c 0xe3bc0001 // Pin=-50dBm -0x81c 0xa8be0001 // Pin=-48dBm -0x81c 0xa7c00001 // Pin=-46dBm -0x81c 0xa6c20001 // Pin=-44dBm -0x81c 0xa5c40001 // Pin=-42dBm -0x81c 0xa4c60001 // Pin=-40dBm -0x81c 0xa3c80001 // Pin=-38dBm -0x81c 0xa2ca0001 // Pin=-36dBm -0x81c 0xa1cc0001 // Pin=-34dBm -0x81c 0x68ce0001 // Pin=-32dBm -0x81c 0x67d00001 // Pin=-30dBm -0x81c 0x66d20001 // Pin=-28dBm -0x81c 0x65d40001 // Pin=-26dBm -0x81c 0x64d60001 // Pin=-24dBm -0x81c 0x47d80001 // Pin=-22dBm -0x81c 0x46da0001 // Pin=-20dBm -0x81c 0x45dc0001 // Pin=-18dBm -0x81c 0x44de0001 // Pin=-16dBm -0x81c 0x43e00001 // Pin=-14dBm -0x81c 0x42e20001 // Pin=-12dBm -0x81c 0x08e40001 // Pin=-10dBm -0x81c 0x07e60001 // Pin=-08dBm -0x81c 0x06e80001 // Pin=-06dBm -0x81c 0x05ea0001 // Pin=-04dBm -0x81c 0x04ec0001 // Pin=-02dBm -0x81c 0x03ee0001 // Pin=-00dBm -0x81c 0x02f00001 // Pin=+02dBm -0x81c 0x01f20001 // Pin=+04dBm -0x81c 0x01f40001 // Pin=+06dBm -0x81c 0x01f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table +//RL6286_MAC_PHY_Parameter_v041_20131127 +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xff060001 // Pin=-104dBm +0x81c 0xff080001 // Pin=-102dBm +0x81c 0xfe0a0001 // Pin=-100dBm +0x81c 0xfd0c0001 // Pin=-98dBm +0x81c 0xfc0e0001 // Pin=-96dBm +0x81c 0xfb100001 // Pin=-94dBm +0x81c 0xfa120001 // Pin=-92dBm +0x81c 0xf9140001 // Pin=-90dBm +0x81c 0xf8160001 // Pin=-88dBm +0x81c 0xf7180001 // Pin=-86dBm +0x81c 0xf61a0001 // Pin=-84dBm +0x81c 0xf51c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xff800001 // Pin=-110dBm +0x81c 0xff820001 // Pin=-108dBm +0x81c 0xff840001 // Pin=-106dBm +0x81c 0xfe860001 // Pin=-104dBm +0x81c 0xfd880001 // Pin=-102dBm +0x81c 0xfc8a0001 // Pin=-100dBm +0x81c 0xfb8c0001 // Pin=-98dBm +0x81c 0xfa8e0001 // Pin=-96dBm +0x81c 0xf9900001 // Pin=-94dBm +0x81c 0xf8920001 // Pin=-92dBm +0x81c 0xf7940001 // Pin=-90dBm +0x81c 0xf6960001 // Pin=-88dBm +0x81c 0xf5980001 // Pin=-86dBm +0x81c 0xf49a0001 // Pin=-84dBm +0x81c 0xf39c0001 // Pin=-82dBm +0x81c 0xf29e0001 // Pin=-80dBm +0x81c 0xf1a00001 // Pin=-78dBm +0x81c 0xf0a20001 // Pin=-76dBm +0x81c 0xefa40001 // Pin=-74dBm +0x81c 0xeea60001 // Pin=-72dBm +0x81c 0xeda80001 // Pin=-70dBm +0x81c 0xecaa0001 // Pin=-68dBm +0x81c 0xebac0001 // Pin=-66dBm +0x81c 0xeaae0001 // Pin=-64dBm +0x81c 0xe9b00001 // Pin=-62dBm +0x81c 0xe8b20001 // Pin=-60dBm +0x81c 0xe7b40001 // Pin=-58dBm +0x81c 0xe6b60001 // Pin=-56dBm +0x81c 0xe5b80001 // Pin=-54dBm +0x81c 0xe4ba0001 // Pin=-52dBm +0x81c 0xe3bc0001 // Pin=-50dBm +0x81c 0xa8be0001 // Pin=-48dBm +0x81c 0xa7c00001 // Pin=-46dBm +0x81c 0xa6c20001 // Pin=-44dBm +0x81c 0xa5c40001 // Pin=-42dBm +0x81c 0xa4c60001 // Pin=-40dBm +0x81c 0xa3c80001 // Pin=-38dBm +0x81c 0xa2ca0001 // Pin=-36dBm +0x81c 0xa1cc0001 // Pin=-34dBm +0x81c 0x68ce0001 // Pin=-32dBm +0x81c 0x67d00001 // Pin=-30dBm +0x81c 0x66d20001 // Pin=-28dBm +0x81c 0x65d40001 // Pin=-26dBm +0x81c 0x64d60001 // Pin=-24dBm +0x81c 0x47d80001 // Pin=-22dBm +0x81c 0x46da0001 // Pin=-20dBm +0x81c 0x45dc0001 // Pin=-18dBm +0x81c 0x44de0001 // Pin=-16dBm +0x81c 0x43e00001 // Pin=-14dBm +0x81c 0x42e20001 // Pin=-12dBm +0x81c 0x08e40001 // Pin=-10dBm +0x81c 0x07e60001 // Pin=-08dBm +0x81c 0x06e80001 // Pin=-06dBm +0x81c 0x05ea0001 // Pin=-04dBm +0x81c 0x04ec0001 // Pin=-02dBm +0x81c 0x03ee0001 // Pin=-00dBm +0x81c 0x02f00001 // Pin=+02dBm +0x81c 0x01f20001 // Pin=+04dBm +0x81c 0x01f40001 // Pin=+06dBm +0x81c 0x01f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_hp.txt b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_hp.txt index 7d511c1b139..97431979f59 100644 --- a/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/AGC_TAB_8812_n_hp.txt @@ -1,136 +1,136 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -0x81c 0xff000001 // Pin=-110dBm -0x81c 0xff020001 // Pin=-108dBm -0x81c 0xff040001 // Pin=-106dBm -0x81c 0xff060001 // Pin=-104dBm -0x81c 0xff080001 // Pin=-102dBm -0x81c 0xfe0a0001 // Pin=-100dBm -0x81c 0xfd0c0001 // Pin=-98dBm -0x81c 0xfc0e0001 // Pin=-96dBm -0x81c 0xfb100001 // Pin=-94dBm -0x81c 0xfa120001 // Pin=-92dBm -0x81c 0xf9140001 // Pin=-90dBm -0x81c 0xf8160001 // Pin=-88dBm -0x81c 0xf7180001 // Pin=-86dBm -0x81c 0xf61a0001 // Pin=-84dBm -0x81c 0xf51c0001 // Pin=-82dBm -0x81c 0xf41e0001 // Pin=-80dBm -0x81c 0xf3200001 // Pin=-78dBm -0x81c 0xf2220001 // Pin=-76dBm -0x81c 0xf1240001 // Pin=-74dBm -0x81c 0xf0260001 // Pin=-72dBm -0x81c 0xef280001 // Pin=-70dBm -0x81c 0xee2a0001 // Pin=-68dBm -0x81c 0xed2c0001 // Pin=-66dBm -0x81c 0xec2e0001 // Pin=-64dBm -0x81c 0xeb300001 // Pin=-62dBm -0x81c 0xea320001 // Pin=-60dBm -0x81c 0xe9340001 // Pin=-58dBm -0x81c 0xe8360001 // Pin=-56dBm -0x81c 0xe7380001 // Pin=-54dBm -0x81c 0xe63a0001 // Pin=-52dBm -0x81c 0xe53c0001 // Pin=-50dBm -0x81c 0xc73e0001 // Pin=-48dBm -0x81c 0xc6400001 // Pin=-46dBm -0x81c 0xc5420001 // Pin=-44dBm -0x81c 0xc4440001 // Pin=-42dBm -0x81c 0xc3460001 // Pin=-40dBm -0x81c 0xc2480001 // Pin=-38dBm -0x81c 0xc14a0001 // Pin=-36dBm -0x81c 0xa74c0001 // Pin=-34dBm -0x81c 0xa64e0001 // Pin=-32dBm -0x81c 0xa5500001 // Pin=-30dBm -0x81c 0xa4520001 // Pin=-28dBm -0x81c 0xa3540001 // Pin=-26dBm -0x81c 0xa2560001 // Pin=-24dBm -0x81c 0xa1580001 // Pin=-22dBm -0x81c 0x675a0001 // Pin=-20dBm -0x81c 0x665c0001 // Pin=-18dBm -0x81c 0x655e0001 // Pin=-16dBm -0x81c 0x64600001 // Pin=-14dBm -0x81c 0x63620001 // Pin=-12dBm -0x81c 0x48640001 // Pin=-10dBm -0x81c 0x47660001 // Pin=-08dBm -0x81c 0x46680001 // Pin=-06dBm -0x81c 0x456a0001 // Pin=-04dBm -0x81c 0x446c0001 // Pin=-02dBm -0x81c 0x436e0001 // Pin=-00dBm -0x81c 0x42700001 // Pin=+02dBm -0x81c 0x41720001 // Pin=+04dBm -0x81c 0x41740001 // Pin=+06dBm -0x81c 0x41760001 // Pin=+08dBm -0x81c 0x41780001 // Pin=+10dBm -0x81c 0x417a0001 // Pin=+12dBm -0x81c 0x417c0001 // Pin=+14dBm -0x81c 0x417e0001 // Pin=+16dBm -// AGC_TABLE 1 (5G) -0x81c 0xfc800001 // Pin=-110dBm -0x81c 0xfb820001 // Pin=-108dBm -0x81c 0xfa840001 // Pin=-106dBm -0x81c 0xf9860001 // Pin=-104dBm -0x81c 0xf8880001 // Pin=-102dBm -0x81c 0xf78a0001 // Pin=-100dBm -0x81c 0xf68c0001 // Pin=-98dBm -0x81c 0xf58e0001 // Pin=-96dBm -0x81c 0xf4900001 // Pin=-94dBm -0x81c 0xf3920001 // Pin=-92dBm -0x81c 0xf2940001 // Pin=-90dBm -0x81c 0xf1960001 // Pin=-88dBm -0x81c 0xf0980001 // Pin=-86dBm -0x81c 0xef9a0001 // Pin=-84dBm -0x81c 0xee9c0001 // Pin=-82dBm -0x81c 0xed9e0001 // Pin=-80dBm -0x81c 0xeca00001 // Pin=-78dBm -0x81c 0xeba20001 // Pin=-76dBm -0x81c 0xeaa40001 // Pin=-74dBm -0x81c 0xe9a60001 // Pin=-72dBm -0x81c 0xe8a80001 // Pin=-70dBm -0x81c 0xe7aa0001 // Pin=-68dBm -0x81c 0xe6ac0001 // Pin=-66dBm -0x81c 0xe5ae0001 // Pin=-64dBm -0x81c 0xe4b00001 // Pin=-62dBm -0x81c 0xe3b20001 // Pin=-60dBm -0x81c 0xa8b40001 // Pin=-58dBm -0x81c 0xa7b60001 // Pin=-56dBm -0x81c 0xa6b80001 // Pin=-54dBm -0x81c 0xa5ba0001 // Pin=-52dBm -0x81c 0xa4bc0001 // Pin=-50dBm -0x81c 0xa3be0001 // Pin=-48dBm -0x81c 0xa2c00001 // Pin=-46dBm -0x81c 0xa1c20001 // Pin=-44dBm -0x81c 0x68c40001 // Pin=-42dBm -0x81c 0x67c60001 // Pin=-40dBm -0x81c 0x66c80001 // Pin=-38dBm -0x81c 0x65ca0001 // Pin=-36dBm -0x81c 0x64cc0001 // Pin=-34dBm -0x81c 0x47ce0001 // Pin=-32dBm -0x81c 0x46d00001 // Pin=-30dBm -0x81c 0x45d20001 // Pin=-28dBm -0x81c 0x44d40001 // Pin=-26dBm -0x81c 0x43d60001 // Pin=-24dBm -0x81c 0x42d80001 // Pin=-22dBm -0x81c 0x08da0001 // Pin=-20dBm -0x81c 0x07dc0001 // Pin=-18dBm -0x81c 0x06de0001 // Pin=-16dBm -0x81c 0x05e00001 // Pin=-14dBm -0x81c 0x04e20001 // Pin=-12dBm -0x81c 0x03e40001 // Pin=-10dBm -0x81c 0x02e60001 // Pin=-08dBm -0x81c 0x01e80001 // Pin=-06dBm -0x81c 0x01ea0001 // Pin=-04dBm -0x81c 0x01ec0001 // Pin=-02dBm -0x81c 0x01ee0001 // Pin=-00dBm -0x81c 0x01f00001 // Pin=+02dBm -0x81c 0x01f20001 // Pin=+04dBm -0x81c 0x01f40001 // Pin=+06dBm -0x81c 0x01f60001 // Pin=+08dBm -0x81c 0x01f80001 // Pin=+10dBm -0x81c 0x01fa0001 // Pin=+12dBm -0x81c 0x01fc0001 // Pin=+14dBm -0x81c 0x01fe0001 // Pin=+16dBm - -0xc50 0x22 -0xc50 0x20 // toogle initial gain twice for valid gain table -0xe50 0x22 -0xe50 0x20 // toogle initial gain twice for valid gain table +//RL6286_MAC_PHY_Parameter_v041_20131127 +0x81c 0xff000001 // Pin=-110dBm +0x81c 0xff020001 // Pin=-108dBm +0x81c 0xff040001 // Pin=-106dBm +0x81c 0xff060001 // Pin=-104dBm +0x81c 0xff080001 // Pin=-102dBm +0x81c 0xfe0a0001 // Pin=-100dBm +0x81c 0xfd0c0001 // Pin=-98dBm +0x81c 0xfc0e0001 // Pin=-96dBm +0x81c 0xfb100001 // Pin=-94dBm +0x81c 0xfa120001 // Pin=-92dBm +0x81c 0xf9140001 // Pin=-90dBm +0x81c 0xf8160001 // Pin=-88dBm +0x81c 0xf7180001 // Pin=-86dBm +0x81c 0xf61a0001 // Pin=-84dBm +0x81c 0xf51c0001 // Pin=-82dBm +0x81c 0xf41e0001 // Pin=-80dBm +0x81c 0xf3200001 // Pin=-78dBm +0x81c 0xf2220001 // Pin=-76dBm +0x81c 0xf1240001 // Pin=-74dBm +0x81c 0xf0260001 // Pin=-72dBm +0x81c 0xef280001 // Pin=-70dBm +0x81c 0xee2a0001 // Pin=-68dBm +0x81c 0xed2c0001 // Pin=-66dBm +0x81c 0xec2e0001 // Pin=-64dBm +0x81c 0xeb300001 // Pin=-62dBm +0x81c 0xea320001 // Pin=-60dBm +0x81c 0xe9340001 // Pin=-58dBm +0x81c 0xe8360001 // Pin=-56dBm +0x81c 0xe7380001 // Pin=-54dBm +0x81c 0xe63a0001 // Pin=-52dBm +0x81c 0xe53c0001 // Pin=-50dBm +0x81c 0xc73e0001 // Pin=-48dBm +0x81c 0xc6400001 // Pin=-46dBm +0x81c 0xc5420001 // Pin=-44dBm +0x81c 0xc4440001 // Pin=-42dBm +0x81c 0xc3460001 // Pin=-40dBm +0x81c 0xc2480001 // Pin=-38dBm +0x81c 0xc14a0001 // Pin=-36dBm +0x81c 0xa74c0001 // Pin=-34dBm +0x81c 0xa64e0001 // Pin=-32dBm +0x81c 0xa5500001 // Pin=-30dBm +0x81c 0xa4520001 // Pin=-28dBm +0x81c 0xa3540001 // Pin=-26dBm +0x81c 0xa2560001 // Pin=-24dBm +0x81c 0xa1580001 // Pin=-22dBm +0x81c 0x675a0001 // Pin=-20dBm +0x81c 0x665c0001 // Pin=-18dBm +0x81c 0x655e0001 // Pin=-16dBm +0x81c 0x64600001 // Pin=-14dBm +0x81c 0x63620001 // Pin=-12dBm +0x81c 0x48640001 // Pin=-10dBm +0x81c 0x47660001 // Pin=-08dBm +0x81c 0x46680001 // Pin=-06dBm +0x81c 0x456a0001 // Pin=-04dBm +0x81c 0x446c0001 // Pin=-02dBm +0x81c 0x436e0001 // Pin=-00dBm +0x81c 0x42700001 // Pin=+02dBm +0x81c 0x41720001 // Pin=+04dBm +0x81c 0x41740001 // Pin=+06dBm +0x81c 0x41760001 // Pin=+08dBm +0x81c 0x41780001 // Pin=+10dBm +0x81c 0x417a0001 // Pin=+12dBm +0x81c 0x417c0001 // Pin=+14dBm +0x81c 0x417e0001 // Pin=+16dBm +// AGC_TABLE 1 (5G) +0x81c 0xfc800001 // Pin=-110dBm +0x81c 0xfb820001 // Pin=-108dBm +0x81c 0xfa840001 // Pin=-106dBm +0x81c 0xf9860001 // Pin=-104dBm +0x81c 0xf8880001 // Pin=-102dBm +0x81c 0xf78a0001 // Pin=-100dBm +0x81c 0xf68c0001 // Pin=-98dBm +0x81c 0xf58e0001 // Pin=-96dBm +0x81c 0xf4900001 // Pin=-94dBm +0x81c 0xf3920001 // Pin=-92dBm +0x81c 0xf2940001 // Pin=-90dBm +0x81c 0xf1960001 // Pin=-88dBm +0x81c 0xf0980001 // Pin=-86dBm +0x81c 0xef9a0001 // Pin=-84dBm +0x81c 0xee9c0001 // Pin=-82dBm +0x81c 0xed9e0001 // Pin=-80dBm +0x81c 0xeca00001 // Pin=-78dBm +0x81c 0xeba20001 // Pin=-76dBm +0x81c 0xeaa40001 // Pin=-74dBm +0x81c 0xe9a60001 // Pin=-72dBm +0x81c 0xe8a80001 // Pin=-70dBm +0x81c 0xe7aa0001 // Pin=-68dBm +0x81c 0xe6ac0001 // Pin=-66dBm +0x81c 0xe5ae0001 // Pin=-64dBm +0x81c 0xe4b00001 // Pin=-62dBm +0x81c 0xe3b20001 // Pin=-60dBm +0x81c 0xa8b40001 // Pin=-58dBm +0x81c 0xa7b60001 // Pin=-56dBm +0x81c 0xa6b80001 // Pin=-54dBm +0x81c 0xa5ba0001 // Pin=-52dBm +0x81c 0xa4bc0001 // Pin=-50dBm +0x81c 0xa3be0001 // Pin=-48dBm +0x81c 0xa2c00001 // Pin=-46dBm +0x81c 0xa1c20001 // Pin=-44dBm +0x81c 0x68c40001 // Pin=-42dBm +0x81c 0x67c60001 // Pin=-40dBm +0x81c 0x66c80001 // Pin=-38dBm +0x81c 0x65ca0001 // Pin=-36dBm +0x81c 0x64cc0001 // Pin=-34dBm +0x81c 0x47ce0001 // Pin=-32dBm +0x81c 0x46d00001 // Pin=-30dBm +0x81c 0x45d20001 // Pin=-28dBm +0x81c 0x44d40001 // Pin=-26dBm +0x81c 0x43d60001 // Pin=-24dBm +0x81c 0x42d80001 // Pin=-22dBm +0x81c 0x08da0001 // Pin=-20dBm +0x81c 0x07dc0001 // Pin=-18dBm +0x81c 0x06de0001 // Pin=-16dBm +0x81c 0x05e00001 // Pin=-14dBm +0x81c 0x04e20001 // Pin=-12dBm +0x81c 0x03e40001 // Pin=-10dBm +0x81c 0x02e60001 // Pin=-08dBm +0x81c 0x01e80001 // Pin=-06dBm +0x81c 0x01ea0001 // Pin=-04dBm +0x81c 0x01ec0001 // Pin=-02dBm +0x81c 0x01ee0001 // Pin=-00dBm +0x81c 0x01f00001 // Pin=+02dBm +0x81c 0x01f20001 // Pin=+04dBm +0x81c 0x01f40001 // Pin=+06dBm +0x81c 0x01f60001 // Pin=+08dBm +0x81c 0x01f80001 // Pin=+10dBm +0x81c 0x01fa0001 // Pin=+12dBm +0x81c 0x01fc0001 // Pin=+14dBm +0x81c 0x01fe0001 // Pin=+16dBm + +0xc50 0x22 +0xc50 0x20 // toogle initial gain twice for valid gain table +0xe50 0x22 +0xe50 0x20 // toogle initial gain twice for valid gain table 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/MAC_REG_8812.txt b/package/kernel/rtl8192cd/data_8812/MAC_REG_8812.txt old mode 100755 new mode 100644 index f0b7f7441e4..76944481be9 --- a/package/kernel/rtl8192cd/data_8812/MAC_REG_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/MAC_REG_8812.txt @@ -1,98 +1,98 @@ -//Release version: RTLE442D.0515.2012 -0x010 0x0c // AFE power cut -0x011 0x6a // SWR=1.3V -0x072 0x00 // AFE iso -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -//0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x460 0x88 -0x461 0x88 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x605 0x30 -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x0a -0x63d 0x0e -0x63e 0x0a -0x63f 0x0e -0x640 0x40 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0xffff 0xffff +//Release version: RTLE442D.0515.2012 +0x010 0x0c // AFE power cut +0x011 0x6a // SWR=1.3V +0x072 0x00 // AFE iso +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +//0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x460 0x88 +0x461 0x88 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x605 0x30 +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x0a +0x63d 0x0e +0x63e 0x0a +0x63f 0x0e +0x640 0x40 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/MAC_REG_8812_n.txt b/package/kernel/rtl8192cd/data_8812/MAC_REG_8812_n.txt index 9c31a2efaad..4eec0032d1d 100644 --- a/package/kernel/rtl8192cd/data_8812/MAC_REG_8812_n.txt +++ b/package/kernel/rtl8192cd/data_8812/MAC_REG_8812_n.txt @@ -1,103 +1,103 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -0x010 0x0c // AFE power cut -0x025 0x0F // USB clock buffer driving=2b00 -0x072 0x00 // AFE iso -0x428 0x0a -0x429 0x10 -0x430 0x00 -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 -0x435 0x05 -0x436 0x07 -0x437 0x08 -0x43c 0x04 -0x43d 0x05 -0x43e 0x07 -0x43f 0x08 -0x440 0x5d -0x441 0x01 -0x442 0x00 -0x444 0x10 -0x445 0x00 -0x446 0x00 -0x447 0x00 -0x448 0x00 -0x449 0xf0 -0x44a 0x0F -0x44b 0x3e -0x44c 0x10 -0x44d 0x00 -0x44e 0x00 -0x44f 0x00 -0x450 0x00 -0x451 0xf0 -0x452 0x0f -0x453 0x00 -0x45b 0x80 //Tx Qos single-MPDU -0x460 0x66 -0x461 0x66 -0x4c8 0xff -0x4c9 0x08 -0x4cc 0xff -0x4cd 0xff -0x4ce 0x01 -0x500 0x26 -0x501 0xa2 -0x502 0x2f -0x503 0x00 -0x504 0x28 -0x505 0xa3 -0x506 0x5e -0x507 0x00 -0x508 0x2b -0x509 0xa4 -0x50a 0x5e -0x50b 0x00 -0x50c 0x4f -0x50d 0xa4 -0x50e 0x00 -0x50f 0x00 -0x512 0x1c -0x514 0x0a -0x516 0x0a -0x525 0x4f -0x550 0x10 -0x551 0x10 -0x559 0x02 -0x55c 0x50 -0x55d 0xff -0x604 0x01 //compute tx Lsig length from BB symbol -0x605 0x30 -0x607 0x03 //rx_length from Lsig -0x608 0x0e -0x609 0x28 -0x620 0xff -0x621 0xff -0x622 0xff -0x623 0xff -0x624 0xff -0x625 0xff -0x626 0xff -0x627 0xff -0x638 0x50 -0x63c 0x08 -0x63d 0x08 -0x63e 0x0c -0x63f 0x0c -0x640 0x80 //ACK timeout -0x642 0x40 //EIFS -0x643 0x00 -0x652 0xC8 -0x66e 0x05 -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 -0x718 0x40 //bypass sig-b crc8 +//RL6286_MAC_PHY_Parameter_v041_20131127 +0x010 0x0c // AFE power cut +0x025 0x0F // USB clock buffer driving=2b00 +0x072 0x00 // AFE iso +0x428 0x0a +0x429 0x10 +0x430 0x00 +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 +0x435 0x05 +0x436 0x07 +0x437 0x08 +0x43c 0x04 +0x43d 0x05 +0x43e 0x07 +0x43f 0x08 +0x440 0x5d +0x441 0x01 +0x442 0x00 +0x444 0x10 +0x445 0x00 +0x446 0x00 +0x447 0x00 +0x448 0x00 +0x449 0xf0 +0x44a 0x0F +0x44b 0x3e +0x44c 0x10 +0x44d 0x00 +0x44e 0x00 +0x44f 0x00 +0x450 0x00 +0x451 0xf0 +0x452 0x0f +0x453 0x00 +0x45b 0x80 //Tx Qos single-MPDU +0x460 0x66 +0x461 0x66 +0x4c8 0xff +0x4c9 0x08 +0x4cc 0xff +0x4cd 0xff +0x4ce 0x01 +0x500 0x26 +0x501 0xa2 +0x502 0x2f +0x503 0x00 +0x504 0x28 +0x505 0xa3 +0x506 0x5e +0x507 0x00 +0x508 0x2b +0x509 0xa4 +0x50a 0x5e +0x50b 0x00 +0x50c 0x4f +0x50d 0xa4 +0x50e 0x00 +0x50f 0x00 +0x512 0x1c +0x514 0x0a +0x516 0x0a +0x525 0x4f +0x550 0x10 +0x551 0x10 +0x559 0x02 +0x55c 0x50 +0x55d 0xff +0x604 0x01 //compute tx Lsig length from BB symbol +0x605 0x30 +0x607 0x03 //rx_length from Lsig +0x608 0x0e +0x609 0x28 +0x620 0xff +0x621 0xff +0x622 0xff +0x623 0xff +0x624 0xff +0x625 0xff +0x626 0xff +0x627 0xff +0x638 0x50 +0x63c 0x08 +0x63d 0x08 +0x63e 0x0c +0x63f 0x0c +0x640 0x80 //ACK timeout +0x642 0x40 //EIFS +0x643 0x00 +0x652 0xC8 +0x66e 0x05 +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 +0x718 0x40 //bypass sig-b crc8 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812.txt old mode 100755 new mode 100644 index 43e97b1dc62..fd5d922411d --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812.txt @@ -1,241 +1,241 @@ -//Release version: RLE442D.0702.2012 - -//======================= -// PAGE_8 -//======================= -0x800 0x0020d010 -0x804 0x080112c0 -0x808 0x0e028233 // cck_en=0, ofdm_en=0 -0x80c 0x12131113 -0x810 0x10101241 -0x814 0x020c3d10 -0x818 0x04000385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002083d5 -0x830 0x2aaaae38 -0x834 0x0037a705 -0x838 0x26389c45 -0x83c 0x00000712 -0x840 0xc0000001 -0x844 0x48003cde -0x848 0x6210ff8b -0x84c 0x6cfdffb8 -0x850 0x28876706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x69298321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x338c2878 -0x870 0x03333333 -0x874 0x31e12c2e -0x878 0x00000152 -0x87c 0x000fc000 -0x8a0 0x00000003 -0x8a4 0x7f7f7f7f -0x8a8 0x00000338 -0x8ac 0x0ff0fa0a -0x8b4 0x000fc080 -0x8b8 0x7c005fff -0x8bc 0x8ca420a0 -0x8c0 0x01f00020 -0x8c4 0x00000000 -0x8c8 0x00013169 -0x8cc 0x08248492 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000700 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x9a4 0x00000080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x01081008 -0x9b4 0x01081008 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000002 -0x9e8 0x00000000 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c8a8300 -0xa0c 0x2e68000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00910000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x001f0000 -//======================= -// PAGE_b -//======================= -//0xb00 0x03100100 // PMC mode, 0xb00[8]=1 -0xb00 0x03100000 // TMAC mode, 0xb00[8]=0 -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000003 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M,5.5M,2M,1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M,12M,9M,6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M,48M,36M,24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3,MCS2,MCS1,MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7,MCS6,MCS5,MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11,MCS10,MCS9,MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15,MCS14,MCS13,MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3,MCS2,MCS1,MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7,MCS6,MCS5,MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1,MCS0},VHT1SS_{MC9,MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5,MCS4,MCS3,MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9,MCS8,MCS7,MCS6} -0xc50 0x0000001c -0xc54 0x001c1208 -0xc58 0x30020c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x19791979 -0xc6c 0x19791979 -0xc70 0x19791979 -0xc74 0x19791979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x00000000 -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x98543210 -0xcb4 0x00000098 -0xcb8 0x00508240 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000003 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M,5.5M,2M,1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M,12M,9M,6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M,48M,36M,24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3,MCS2,MCS1,MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7,MCS6,MCS5,MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11,MCS10,MCS9,MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15,MCS14,MCS13,MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3,MCS2,MCS1,MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7,MCS6,MCS5,MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1,MCS0},VHT1SS_{MC9,MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5,MCS4,MCS3,MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9,MCS8,MCS7,MCS6} -0xe50 0x0000001c -0xe54 0x001c1208 -0xe58 0x30020c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x19791979 -0xe6c 0x19791979 -0xe70 0x19791979 -0xe74 0x19791979 -0xe78 0x19791979 -0xe7c 0x19791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe94 0x00000000 -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000029 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeb0 0x98543210 -0xeb4 0x00000098 -0xeb8 0x00508240 - -0xffff 0xffff +//Release version: RLE442D.0702.2012 + +//======================= +// PAGE_8 +//======================= +0x800 0x0020d010 +0x804 0x080112c0 +0x808 0x0e028233 // cck_en=0, ofdm_en=0 +0x80c 0x12131113 +0x810 0x10101241 +0x814 0x020c3d10 +0x818 0x04000385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083d5 +0x830 0x2aaaae38 +0x834 0x0037a705 +0x838 0x26389c45 +0x83c 0x00000712 +0x840 0xc0000001 +0x844 0x48003cde +0x848 0x6210ff8b +0x84c 0x6cfdffb8 +0x850 0x28876706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x69298321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31e12c2e +0x878 0x00000152 +0x87c 0x000fc000 +0x8a0 0x00000003 +0x8a4 0x7f7f7f7f +0x8a8 0x00000338 +0x8ac 0x0ff0fa0a +0x8b4 0x000fc080 +0x8b8 0x7c005fff +0x8bc 0x8ca420a0 +0x8c0 0x01f00020 +0x8c4 0x00000000 +0x8c8 0x00013169 +0x8cc 0x08248492 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000700 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x9a4 0x00000080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x01081008 +0x9b4 0x01081008 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000002 +0x9e8 0x00000000 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c8a8300 +0xa0c 0x2e68000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00910000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x001f0000 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode, 0xb00[8]=1 +0xb00 0x03100000 // TMAC mode, 0xb00[8]=0 +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M,5.5M,2M,1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M,12M,9M,6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M,48M,36M,24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3,MCS2,MCS1,MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7,MCS6,MCS5,MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11,MCS10,MCS9,MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15,MCS14,MCS13,MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3,MCS2,MCS1,MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7,MCS6,MCS5,MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1,MCS0},VHT1SS_{MC9,MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5,MCS4,MCS3,MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9,MCS8,MCS7,MCS6} +0xc50 0x0000001c +0xc54 0x001c1208 +0xc58 0x30020c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x19791979 +0xc6c 0x19791979 +0xc70 0x19791979 +0xc74 0x19791979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x00000000 +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x98543210 +0xcb4 0x00000098 +0xcb8 0x00508240 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000003 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M,5.5M,2M,1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M,12M,9M,6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M,48M,36M,24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3,MCS2,MCS1,MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7,MCS6,MCS5,MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11,MCS10,MCS9,MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15,MCS14,MCS13,MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3,MCS2,MCS1,MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7,MCS6,MCS5,MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1,MCS0},VHT1SS_{MC9,MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5,MCS4,MCS3,MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9,MCS8,MCS7,MCS6} +0xe50 0x0000001c +0xe54 0x001c1208 +0xe58 0x30020c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x19791979 +0xe6c 0x19791979 +0xe70 0x19791979 +0xe74 0x19791979 +0xe78 0x19791979 +0xe7c 0x19791979 +0xe80 0x19791979 +0xe84 0x19791979 +0xe94 0x00000000 +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000029 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeb0 0x98543210 +0xeb4 0x00000098 +0xeb8 0x00508240 + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_default.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_default.txt index 59d5e62eaec..b01bd80e968 100644 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_default.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_default.txt @@ -1,247 +1,247 @@ -//RL6286_MAC_PHY_Parameter_v042_20131128 -//======================= -// PAGE_8 -//======================= -0x800 0x8020d010 -0x804 0x080112e0 -0x808 0x0e028233 // cck_en=0 ofdm_en=0 -0x80c 0x12131113 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002083dd -0x830 0x2aaa6c86 -0x834 0x0037a706 -0x838 0x06c89b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x6210ff8b -0x84c 0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x338c2878 -0x870 0x03333333 -0x874 0x31602c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202033e -0x8ac 0x0ff0fa0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0x6c0057ff -0x8bc 0x4ca520a3 -0x8c0 0x27f00020 -0x8c4 0x00000000 -0x8c8 0x00012D69 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8dc 0x00000000 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000701 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000003 -0x9e8 0x000002d5 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x001f8c80 -//======================= -// PAGE_b -//======================= -//0xb00 0x03100100 // PMC mode 0xb00[8]=1 -0xb00 0x03100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000003 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x0008121c -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59799979 -0xc6c 0x59795979 -0xc70 0x19795979 -0xc74 0x19795979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77547777 -0xcb4 0x00000077 -0xcb8 0x00508242 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000003 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x0008121c -0xe58 0x30000c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x59791979 -0xe6c 0x59795979 -0xe70 0x19795979 -0xe74 0x19795979 -0xe78 0x19791979 -0xe7c 0x19791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe94 0x0100005c -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000029 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeb0 0x77547777 -0xeb4 0x00000077 -0xeb8 0x00508242 +//RL6286_MAC_PHY_Parameter_v042_20131128 +//======================= +// PAGE_8 +//======================= +0x800 0x8020d010 +0x804 0x080112e0 +0x808 0x0e028233 // cck_en=0 ofdm_en=0 +0x80c 0x12131113 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa6c86 +0x834 0x0037a706 +0x838 0x06c89b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x6210ff8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31602c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202033e +0x8ac 0x0ff0fa0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0x6c0057ff +0x8bc 0x4ca520a3 +0x8c0 0x27f00020 +0x8c4 0x00000000 +0x8c8 0x00012D69 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8dc 0x00000000 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000701 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000003 +0x9e8 0x000002d5 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x001f8c80 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode 0xb00[8]=1 +0xb00 0x03100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x0008121c +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59799979 +0xc6c 0x59795979 +0xc70 0x19795979 +0xc74 0x19795979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77547777 +0xcb4 0x00000077 +0xcb8 0x00508242 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000003 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x0008121c +0xe58 0x30000c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x59791979 +0xe6c 0x59795979 +0xe70 0x19795979 +0xe74 0x19795979 +0xe78 0x19791979 +0xe7c 0x19791979 +0xe80 0x19791979 +0xe84 0x19791979 +0xe94 0x0100005c +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000029 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeb0 0x77547777 +0xeb4 0x00000077 +0xeb8 0x00508242 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extlna.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extlna.txt index 898051ad9fe..38499a1dda7 100644 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extlna.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extlna.txt @@ -1,247 +1,247 @@ -//RL6286_MAC_PHY_Parameter_v042_20131128 -//======================= -// PAGE_8 -//======================= -0x800 0x8020d010 -0x804 0x080112e0 -0x808 0x0e028233 // cck_en=0 ofdm_en=0 -0x80c 0x12131113 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002083dd -0x830 0x2eee7226 //0x2eaaeeb8 -0x834 0x0037a706 -0x838 0x06c89b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x6210ff8b -0x84c 0x6cfeffb8 //0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79766c32 //0x79727432 -0x868 0x8ca7a314 -0x86c 0x338c2878 -0x870 0x03333333 -0x874 0x31602c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202033e -0x8ac 0x0ff0fa0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0x6c0057ff -0x8bc 0x4ca520a3 -0x8c0 0x27f00020 -0x8c4 0x00000000 -0x8c8 0x00012D69 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8dc 0x00000000 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000701 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000003 -0x9e8 0x000002d5 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x001f8c80 -//======================= -// PAGE_b -//======================= -//0xb00 0x03100100 // PMC mode 0xb00[8]=1 -0xb00 0x03100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000003 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x0008121c -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59791979 -0xc6c 0x59795979 -0xc70 0x19795979 -0xc74 0x19795979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77547777 -0xcb4 0x00000077 -0xcb8 0x00508242 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000003 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x0008121c -0xe58 0x30000c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x59791979 -0xe6c 0x59795979 -0xe70 0x19795979 -0xe74 0x19795979 -0xe78 0x19791979 -0xe7c 0x19791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe94 0x0100005c -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000029 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeb0 0x77547777 -0xeb4 0x00000077 -0xeb8 0x00508242 +//RL6286_MAC_PHY_Parameter_v042_20131128 +//======================= +// PAGE_8 +//======================= +0x800 0x8020d010 +0x804 0x080112e0 +0x808 0x0e028233 // cck_en=0 ofdm_en=0 +0x80c 0x12131113 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2eee7226 //0x2eaaeeb8 +0x834 0x0037a706 +0x838 0x06c89b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x6210ff8b +0x84c 0x6cfeffb8 //0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79766c32 //0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31602c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202033e +0x8ac 0x0ff0fa0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0x6c0057ff +0x8bc 0x4ca520a3 +0x8c0 0x27f00020 +0x8c4 0x00000000 +0x8c8 0x00012D69 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8dc 0x00000000 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000701 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000003 +0x9e8 0x000002d5 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x001f8c80 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode 0xb00[8]=1 +0xb00 0x03100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x0008121c +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59791979 +0xc6c 0x59795979 +0xc70 0x19795979 +0xc74 0x19795979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77547777 +0xcb4 0x00000077 +0xcb8 0x00508242 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000003 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x0008121c +0xe58 0x30000c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x59791979 +0xe6c 0x59795979 +0xe70 0x19795979 +0xe74 0x19795979 +0xe78 0x19791979 +0xe7c 0x19791979 +0xe80 0x19791979 +0xe84 0x19791979 +0xe94 0x0100005c +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000029 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeb0 0x77547777 +0xeb4 0x00000077 +0xeb8 0x00508242 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extpa.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extpa.txt index 664f912632a..a8380929c48 100644 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extpa.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_extpa.txt @@ -1,247 +1,247 @@ -//RL6286_MAC_PHY_Parameter_v042_20131128 -//======================= -// PAGE_8 -//======================= -0x800 0x8020d010 -0x804 0x080112e0 -0x808 0x0e028233 // cck_en=0 ofdm_en=0 -0x80c 0x12131113 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002083dd -0x830 0x2aaa6c86 -0x834 0x0037a706 -0x838 0x06c89b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x6210ff8b -0x84c 0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x338c2878 -0x870 0x03333333 -0x874 0x31602c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202033e -0x8ac 0x0ff0fa0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0x6c0057ff -0x8bc 0x4ca520a3 -0x8c0 0x27f00020 -0x8c4 0x00000000 -0x8c8 0x00012D69 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8dc 0x00000000 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000701 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000003 -0x9e8 0x000002d5 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x001f8c80 -//======================= -// PAGE_b -//======================= -//0xb00 0x03100100 // PMC mode 0xb00[8]=1 -0xb00 0x03100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000003 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x0008121c -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59791979 -0xc6c 0x59795979 -0xc70 0x19795979 -0xc74 0x19795979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77547777 -0xcb4 0x00000077 -0xcb8 0x00508242 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000003 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x0008121c -0xe58 0x30000c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x59791979 -0xe6c 0x59795979 -0xe70 0x19795979 -0xe74 0x19795979 -0xe78 0x19791979 -0xe7c 0x19791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe94 0x0100005c -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000029 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeb0 0x77547777 -0xeb4 0x00000077 -0xeb8 0x00508242 +//RL6286_MAC_PHY_Parameter_v042_20131128 +//======================= +// PAGE_8 +//======================= +0x800 0x8020d010 +0x804 0x080112e0 +0x808 0x0e028233 // cck_en=0 ofdm_en=0 +0x80c 0x12131113 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa6c86 +0x834 0x0037a706 +0x838 0x06c89b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x6210ff8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31602c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202033e +0x8ac 0x0ff0fa0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0x6c0057ff +0x8bc 0x4ca520a3 +0x8c0 0x27f00020 +0x8c4 0x00000000 +0x8c8 0x00012D69 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8dc 0x00000000 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000701 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000003 +0x9e8 0x000002d5 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x001f8c80 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode 0xb00[8]=1 +0xb00 0x03100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x0008121c +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59791979 +0xc6c 0x59795979 +0xc70 0x19795979 +0xc74 0x19795979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77547777 +0xcb4 0x00000077 +0xcb8 0x00508242 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000003 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x0008121c +0xe58 0x30000c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x59791979 +0xe6c 0x59795979 +0xe70 0x19795979 +0xe74 0x19795979 +0xe78 0x19791979 +0xe7c 0x19791979 +0xe80 0x19791979 +0xe84 0x19791979 +0xe94 0x0100005c +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000029 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeb0 0x77547777 +0xeb4 0x00000077 +0xeb8 0x00508242 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_hp.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_hp.txt index 664f912632a..a8380929c48 100644 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_8812_n_hp.txt @@ -1,247 +1,247 @@ -//RL6286_MAC_PHY_Parameter_v042_20131128 -//======================= -// PAGE_8 -//======================= -0x800 0x8020d010 -0x804 0x080112e0 -0x808 0x0e028233 // cck_en=0 ofdm_en=0 -0x80c 0x12131113 -0x810 0x20101263 -0x814 0x020c3d10 -0x818 0x03a00385 -0x820 0x00000000 -0x824 0x00030fe0 -0x828 0x00000000 -0x82c 0x002083dd -0x830 0x2aaa6c86 -0x834 0x0037a706 -0x838 0x06c89b44 -0x83c 0x0000095b -0x840 0xc0000001 -0x844 0x40003cde -0x848 0x6210ff8b -0x84c 0x6cfdffb8 -0x850 0x28874706 -0x854 0x0001520c -0x858 0x8060e000 -0x85c 0x74210168 -0x860 0x6929c321 -0x864 0x79727432 -0x868 0x8ca7a314 -0x86c 0x338c2878 -0x870 0x03333333 -0x874 0x31602c2e -0x878 0x00003152 -0x87c 0x000fc000 -0x8a0 0x00000013 -0x8a4 0x7f7f7f7f -0x8a8 0xa202033e -0x8ac 0x0ff0fa0a -0x8b0 0x00000600 -0x8b4 0x000fc080 -0x8b8 0x6c0057ff -0x8bc 0x4ca520a3 -0x8c0 0x27f00020 -0x8c4 0x00000000 -0x8c8 0x00012D69 -0x8cc 0x08248492 -0x8d0 0x0000b800 -0x8dc 0x00000000 -0x8d4 0x940008a0 -0x8d8 0x290b5612 -0x8f8 0x400002c0 // RF: RLE442C format (30-bit) -//0x8f8 0x400000c0 // RF: z2 format (16-bit) -0x8fc 0x00000000 -//======================= -// PAGE_9 -//======================= -0x900 0x00000701 -0x90c 0x00000000 -0x910 0x0000fc00 -0x914 0x00000404 -0x918 0x1c1028c0 -0x91c 0x64b11a1c -0x920 0xe0767233 -0x924 0x055aa500 -0x928 0x00000004 -0x92c 0xfffe0000 -0x930 0xfffffffe -0x934 0x001fffff -0x960 0x00000000 -0x964 0x00000000 -0x968 0x00000000 -0x96c 0x00000000 -0x970 0x801fffff -0x978 0x00000000 -0x97c 0x00000000 -0x980 0x00000000 -0x984 0x00000000 -0x988 0x00000000 -0x990 0x27100000 -0x994 0xffff0100 -0x998 0xffffff5c -0x99c 0xffffffff -0x9a0 0x000000ff -0x9a4 0x00080080 -0x9a8 0x00000000 -0x9ac 0x00000000 -0x9b0 0x81081008 -0x9b4 0x00000000 -0x9b8 0x01081008 -0x9bc 0x01081008 -0x9d0 0x00000000 -0x9d4 0x00000000 -0x9d8 0x00000000 -0x9dc 0x00000000 -0x9e4 0x00000003 -0x9e8 0x000002d5 -//======================= -// PAGE_a -//======================= -0xa00 0x00d047c8 -0xa04 0x01ff000c -0xa08 0x8c838300 -0xa0c 0x2e7f000f -0xa10 0x9500bb78 -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00900000 -0xa70 0x101fff00 -0xa74 0x00000008 -0xa78 0x00000900 -0xa7c 0x225b0606 -0xa80 0x218075b2 -0xa84 0x001f8c80 -//======================= -// PAGE_b -//======================= -//0xb00 0x03100100 // PMC mode 0xb00[8]=1 -0xb00 0x03100000 // TMAC mode 0xb00[8]=0 -0xb04 0x0000b000 -0xb08 0xae0201eb -0xb0c 0x01003207 -0xb10 0x00009807 -0xb14 0x01000000 -0xb18 0x00000002 -0xb1c 0x00000002 -0xb20 0x0000001f -0xb24 0x03020100 -0xb28 0x07060504 -0xb2c 0x0b0a0908 -0xb30 0x0f0e0d0c -0xb34 0x13121110 -0xb38 0x17161514 -0xb3c 0x0000003a -0xb40 0x00000000 -0xb44 0x00000000 -0xb48 0x13000032 -0xb4c 0x48080000 -0xb50 0x00000000 -0xb54 0x00000000 -0xb58 0x00000000 -0xb5c 0x00000000 -//======================= -// PAGE_C : Path_A setting -//======================= -//0xc00 0x00000003 // RF: RLE442C/D format with SI -0xc00 0x00000007 // RF: RLE442C/D format with PI -//0xc00 0x00040003 // RF: z2 format -0xc04 0x00042020 -0xc08 0x80410231 // RF: RLE442C format -//0xc08 0x80410121 // RF: z2 format -0xc0c 0x00000000 -//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C -0xc10 0x00000100 // RF: RX IQ is correct -0xc14 0x01000000 // RF: RX IQ is correct -0xc1c 0x40000003 -0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xc50 0x00000020 -0xc54 0x0008121c -0xc58 0x30000c1c -0xc5c 0x00000058 -0xc60 0x34344443 -0xc64 0x07003333 -0xc68 0x59791979 -0xc6c 0x59795979 -0xc70 0x19795979 -0xc74 0x19795979 -0xc78 0x19791979 -0xc7c 0x19791979 -0xc80 0x19791979 -0xc84 0x19791979 -0xc94 0x0100005c -0xc98 0x00000000 -0xc9c 0x00000000 -0xca0 0x00000029 // TRSW mapping table -0xca4 0x08040201 -0xca8 0x80402010 -0xcb0 0x77547777 -0xcb4 0x00000077 -0xcb8 0x00508242 -//======================= -// PAGE_E : Path_B setting -//======================= -//0xe00 0x00000003 // RF: RLE442C/D format with SI -0xe00 0x00000007 // RF: RLE442C/D format with PI -//0xe00 0x00040003 // RF: z2 format -0xe04 0x00042020 -0xe08 0x80410231 // RF: RLE442C format -//0xe08 0x80410121 // RF: z2 format -0xe0c 0x00000000 -//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C -//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C -0xe10 0x00000100 // RF: RX IQ is correct -0xe14 0x01000000 // RF: RX IQ is correct -0xe1c 0x40000003 -0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xe50 0x00000020 -0xe54 0x0008121c -0xe58 0x30000c1c -0xe5c 0x00000058 -0xe60 0x34344443 -0xe64 0x07003333 -0xe68 0x59791979 -0xe6c 0x59795979 -0xe70 0x19795979 -0xe74 0x19795979 -0xe78 0x19791979 -0xe7c 0x19791979 -0xe80 0x19791979 -0xe84 0x19791979 -0xe94 0x0100005c -0xe98 0x00000000 -0xe9c 0x00000000 -0xea0 0x00000029 // TRSW mapping table -0xea4 0x08040201 -0xea8 0x80402010 -0xeb0 0x77547777 -0xeb4 0x00000077 -0xeb8 0x00508242 +//RL6286_MAC_PHY_Parameter_v042_20131128 +//======================= +// PAGE_8 +//======================= +0x800 0x8020d010 +0x804 0x080112e0 +0x808 0x0e028233 // cck_en=0 ofdm_en=0 +0x80c 0x12131113 +0x810 0x20101263 +0x814 0x020c3d10 +0x818 0x03a00385 +0x820 0x00000000 +0x824 0x00030fe0 +0x828 0x00000000 +0x82c 0x002083dd +0x830 0x2aaa6c86 +0x834 0x0037a706 +0x838 0x06c89b44 +0x83c 0x0000095b +0x840 0xc0000001 +0x844 0x40003cde +0x848 0x6210ff8b +0x84c 0x6cfdffb8 +0x850 0x28874706 +0x854 0x0001520c +0x858 0x8060e000 +0x85c 0x74210168 +0x860 0x6929c321 +0x864 0x79727432 +0x868 0x8ca7a314 +0x86c 0x338c2878 +0x870 0x03333333 +0x874 0x31602c2e +0x878 0x00003152 +0x87c 0x000fc000 +0x8a0 0x00000013 +0x8a4 0x7f7f7f7f +0x8a8 0xa202033e +0x8ac 0x0ff0fa0a +0x8b0 0x00000600 +0x8b4 0x000fc080 +0x8b8 0x6c0057ff +0x8bc 0x4ca520a3 +0x8c0 0x27f00020 +0x8c4 0x00000000 +0x8c8 0x00012D69 +0x8cc 0x08248492 +0x8d0 0x0000b800 +0x8dc 0x00000000 +0x8d4 0x940008a0 +0x8d8 0x290b5612 +0x8f8 0x400002c0 // RF: RLE442C format (30-bit) +//0x8f8 0x400000c0 // RF: z2 format (16-bit) +0x8fc 0x00000000 +//======================= +// PAGE_9 +//======================= +0x900 0x00000701 +0x90c 0x00000000 +0x910 0x0000fc00 +0x914 0x00000404 +0x918 0x1c1028c0 +0x91c 0x64b11a1c +0x920 0xe0767233 +0x924 0x055aa500 +0x928 0x00000004 +0x92c 0xfffe0000 +0x930 0xfffffffe +0x934 0x001fffff +0x960 0x00000000 +0x964 0x00000000 +0x968 0x00000000 +0x96c 0x00000000 +0x970 0x801fffff +0x978 0x00000000 +0x97c 0x00000000 +0x980 0x00000000 +0x984 0x00000000 +0x988 0x00000000 +0x990 0x27100000 +0x994 0xffff0100 +0x998 0xffffff5c +0x99c 0xffffffff +0x9a0 0x000000ff +0x9a4 0x00080080 +0x9a8 0x00000000 +0x9ac 0x00000000 +0x9b0 0x81081008 +0x9b4 0x00000000 +0x9b8 0x01081008 +0x9bc 0x01081008 +0x9d0 0x00000000 +0x9d4 0x00000000 +0x9d8 0x00000000 +0x9dc 0x00000000 +0x9e4 0x00000003 +0x9e8 0x000002d5 +//======================= +// PAGE_a +//======================= +0xa00 0x00d047c8 +0xa04 0x01ff000c +0xa08 0x8c838300 +0xa0c 0x2e7f000f +0xa10 0x9500bb78 +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00900000 +0xa70 0x101fff00 +0xa74 0x00000008 +0xa78 0x00000900 +0xa7c 0x225b0606 +0xa80 0x218075b2 +0xa84 0x001f8c80 +//======================= +// PAGE_b +//======================= +//0xb00 0x03100100 // PMC mode 0xb00[8]=1 +0xb00 0x03100000 // TMAC mode 0xb00[8]=0 +0xb04 0x0000b000 +0xb08 0xae0201eb +0xb0c 0x01003207 +0xb10 0x00009807 +0xb14 0x01000000 +0xb18 0x00000002 +0xb1c 0x00000002 +0xb20 0x0000001f +0xb24 0x03020100 +0xb28 0x07060504 +0xb2c 0x0b0a0908 +0xb30 0x0f0e0d0c +0xb34 0x13121110 +0xb38 0x17161514 +0xb3c 0x0000003a +0xb40 0x00000000 +0xb44 0x00000000 +0xb48 0x13000032 +0xb4c 0x48080000 +0xb50 0x00000000 +0xb54 0x00000000 +0xb58 0x00000000 +0xb5c 0x00000000 +//======================= +// PAGE_C : Path_A setting +//======================= +//0xc00 0x00000003 // RF: RLE442C/D format with SI +0xc00 0x00000007 // RF: RLE442C/D format with PI +//0xc00 0x00040003 // RF: z2 format +0xc04 0x00042020 +0xc08 0x80410231 // RF: RLE442C format +//0xc08 0x80410121 // RF: z2 format +0xc0c 0x00000000 +//0xc10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xc14 0x00000100 // RF: RX IQ is switched for RLE442C +0xc10 0x00000100 // RF: RX IQ is correct +0xc14 0x01000000 // RF: RX IQ is correct +0xc1c 0x40000003 +0xc20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xc50 0x00000020 +0xc54 0x0008121c +0xc58 0x30000c1c +0xc5c 0x00000058 +0xc60 0x34344443 +0xc64 0x07003333 +0xc68 0x59791979 +0xc6c 0x59795979 +0xc70 0x19795979 +0xc74 0x19795979 +0xc78 0x19791979 +0xc7c 0x19791979 +0xc80 0x19791979 +0xc84 0x19791979 +0xc94 0x0100005c +0xc98 0x00000000 +0xc9c 0x00000000 +0xca0 0x00000029 // TRSW mapping table +0xca4 0x08040201 +0xca8 0x80402010 +0xcb0 0x77547777 +0xcb4 0x00000077 +0xcb8 0x00508242 +//======================= +// PAGE_E : Path_B setting +//======================= +//0xe00 0x00000003 // RF: RLE442C/D format with SI +0xe00 0x00000007 // RF: RLE442C/D format with PI +//0xe00 0x00040003 // RF: z2 format +0xe04 0x00042020 +0xe08 0x80410231 // RF: RLE442C format +//0xe08 0x80410121 // RF: z2 format +0xe0c 0x00000000 +//0xe10 0x01000000 // RF: RX IQ is switched for RLE442C +//0xe14 0x00000100 // RF: RX IQ is switched for RLE442C +0xe10 0x00000100 // RF: RX IQ is correct +0xe14 0x01000000 // RF: RX IQ is correct +0xe1c 0x40000003 +0xe20 0x12121212 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 0x12121212 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 0x12121212 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 0x12121212 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 0x12121212 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 0x12121212 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xe50 0x00000020 +0xe54 0x0008121c +0xe58 0x30000c1c +0xe5c 0x00000058 +0xe60 0x34344443 +0xe64 0x07003333 +0xe68 0x59791979 +0xe6c 0x59795979 +0xe70 0x19795979 +0xe74 0x19795979 +0xe78 0x19791979 +0xe7c 0x19791979 +0xe80 0x19791979 +0xe84 0x19791979 +0xe94 0x0100005c +0xe98 0x00000000 +0xe9c 0x00000000 +0xea0 0x00000029 // TRSW mapping table +0xea4 0x08040201 +0xea8 0x80402010 +0xeb0 0x77547777 +0xeb4 0x00000077 +0xeb8 0x00508242 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_MP_8812.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_MP_8812.txt old mode 100755 new mode 100644 index 2a295f6d5a6..c566e71c178 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_MP_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_MP_8812.txt @@ -1,5 +1,5 @@ -//RL6286_MAC_PHY_Parameter_v043_20131129 -0x800 0x8020d410 // disable adc_mask -0x830 0x2EAA8EB8 // for false alarm -0xc90 0x01E00000 // 80M RCK for ACPR problem -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v043_20131129 +0x800 0x8020d410 // disable adc_mask +0x830 0x2EAA8EB8 // for false alarm +0xc90 0x01E00000 // 80M RCK for ACPR problem +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812.txt old mode 100755 new mode 100644 index cb371795f02..793e2dbf82e --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812.txt @@ -1,42 +1,42 @@ -//RL6286_MAC_PHY_Parameter_v026_20130314 -#Exact -0xc20 17.0 18.0 19.0 20.0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xe20 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} - -0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v026_20130314 +#Exact +0xc20 17.0 18.0 19.0 20.0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xe20 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} + +0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812_new.txt b/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812_new.txt index cb371795f02..793e2dbf82e 100644 --- a/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812_new.txt +++ b/package/kernel/rtl8192cd/data_8812/PHY_REG_PG_8812_new.txt @@ -1,42 +1,42 @@ -//RL6286_MAC_PHY_Parameter_v026_20130314 -#Exact -0xc20 17.0 18.0 19.0 20.0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xc28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xe20 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} -0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xc28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xc3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xc40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xc44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xc48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} - -0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} -0xe28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} -0xe3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} -0xe40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} -0xe44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} -0xe48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} -0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v026_20130314 +#Exact +0xc20 17.0 18.0 19.0 20.0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xc28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xe20 17 18 19 20 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M 1M} +0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe28 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xc24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xc28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xc2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xc30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xc34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xc38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xc3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xc40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xc44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xc48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xc4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} + +0xe24 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={8M 12M 9M 6M} +0xe28 15 16 18 20 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe2c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe30 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe34 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe38 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} +0xe3c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS3 MCS2 MCS1 MCS0} +0xe40 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=VHT1SS_{MCS7 MCS6 MCS5 MCS4} +0xe44 21 21 12 13 // TXAGC codeword (H-byte->L-byte)={VHT2SS{MCS1 MCS0} VHT1SS_{MC9 MCS8}} +0xe48 15 17 19 20 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS5 MCS4 MCS3 MCS2} +0xe4c 11 12 13 14 // TXAGC codeword (H-byte->L-byte)=VHT2SS_{MCS9 MCS8 MCS7 MCS6} +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812.txt b/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812.txt old mode 100755 new mode 100644 index de6d2ce2a86..1cacb7235aa --- a/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GCCKA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 -2GCCKB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GCCKB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 - -//============== 2G PathA&B =============== - -2GA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 -2GB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 -5GLA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 -5GLB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 -5GLB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 -5GMA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 -5GMB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 -5GMB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 -5GHA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 -5GHB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 -5GHB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GCCKA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 +2GCCKB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GCCKB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 + +//============== 2G PathA&B =============== + +2GA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 +2GB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 +5GLA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 +5GLB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 +5GLB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 +5GMA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 +5GMB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 +5GMB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 1 1 2 2 3 4 4 5 6 6 7 7 8 8 9 9 10 11 11 12 13 13 14 14 15 15 16 17 +5GHA_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 +5GHB_P 1 2 3 3 4 5 5 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 17 +5GHB_N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 + + diff --git a/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812_hp.txt b/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812_hp.txt old mode 100755 new mode 100644 index 171f57bfc42..175084e8d50 --- a/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/REG_TXPWR_TRK_8812_hp.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GCCKA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 -2GCCKB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GCCKB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 - -//============== 2G PathA&B =============== - -2GA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 -2GB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 -2GB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 1 1 2 2 3 4 5 5 6 7 8 8 9 10 11 11 12 13 14 14 15 15 16 16 17 18 19 19 -5GLA_N 1 2 3 3 4 4 5 5 6 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 -5GLB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 16 17 17 18 19 20 20 -5GLB_N 1 1 2 2 3 4 5 5 6 6 7 7 8 8 9 9 10 11 12 12 13 13 14 14 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 -5GMA_N 1 2 3 3 4 5 6 6 6 7 7 8 8 9 10 11 11 12 13 13 14 15 16 16 -5GMB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 19 20 20 -5GMB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 -5GHA_N 1 2 3 3 4 5 6 6 7 8 9 9 10 10 11 11 12 13 14 14 15 15 16 16 -5GHB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 -5GHB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GCCKA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 +2GCCKB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GCCKB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 + +//============== 2G PathA&B =============== + +2GA_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GA_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 8 9 9 9 10 10 10 10 +2GB_P 0 1 1 2 2 2 2 3 3 3 4 4 5 5 6 6 6 7 7 7 8 8 8 9 9 9 9 +2GB_N 1 1 1 2 2 2 3 3 3 4 4 5 5 5 6 6 6 7 8 9 9 9 9 10 10 10 10 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 1 1 2 2 3 4 5 5 6 7 8 8 9 10 11 11 12 13 14 14 15 15 16 16 17 18 19 19 +5GLA_N 1 2 3 3 4 4 5 5 6 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 +5GLB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 16 17 17 18 19 20 20 +5GLB_N 1 1 2 2 3 4 5 5 6 6 7 7 8 8 9 9 10 11 12 12 13 13 14 14 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 +5GMA_N 1 2 3 3 4 5 6 6 6 7 7 8 8 9 10 11 11 12 13 13 14 15 16 16 +5GMB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 19 20 20 +5GMB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 +5GHA_N 1 2 3 3 4 5 6 6 7 8 9 9 10 10 11 11 12 13 14 14 15 15 16 16 +5GHB_P 1 2 3 3 4 5 6 6 7 8 9 9 10 11 12 12 13 14 15 15 16 17 18 18 19 20 21 21 +5GHB_N 1 2 3 3 4 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 + + diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812.txt old mode 100755 new mode 100644 index 2f10525474e..791951c378a --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812.txt @@ -1,314 +1,314 @@ -//Release version: RLE442D.0702.2012 -//A MODE S0:5210 - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0xf8000 // RX 80M RCK offset - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x00380 -0x3E 0x00080 -0x3F 0x00320 -0x3E 0x00100 -0x3F 0x00300 -0x3E 0x00180 -0x3F 0x002A0 -0x3E 0x00200 -0x3F 0x00260 -0x3E 0x00280 -0x3F 0x00220 -0x3E 0x00300 -0x3F 0x00200 -0x3E 0x00380 -0x3F 0x000C0 -0xEF 0x00000 - -//Ioffset setting -0xEF 0x40000 -0x3E 0x00000 -0x3F 0x00017 //old:0x0000D -0x3E 0x00020 -0x3F 0x00015 //old:0x0000C -0x3E 0x00040 -0x3F 0x00014 //old:0x0000B -0xEF 0x00000 -//SYN setting -0xB0 0xFFFFF -0xB1 0x1FC1A -0xB2 0x4103F -0xB3 0xF0350 //Ires; F0340:Ibg -0xB4 0x1E68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg -0xB5 0x04BFF -0xB6 0x0A138 -0xB7 0x30008 //binary search -0xB8 0x86000 //A7458,Div to latch & PFD noninvter:A7440 -0xB9 0x08A00 -0xBA 0x86180 -0xBB 0x2CE80 -0xBC 0x40000 -0x18 0x1F12A //set ch42, do LCK -0xfe -0xfe -0xfe -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg -0x18 0x1712A //set ch42 - - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 //HG1 -0x3B 0x37a58 //HG2 -0x3B 0x2a590 //MG1 -0x3B 0x27a50 //MG2 -0x3B 0x18248 //LG -0x3B 0x10240 //ULG -0x3B 0x08240 //ULG -0x3B 0x00240 //ULG - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ACF7 -0x34 0x09CF4 -0x34 0x08CF1 -0x34 0x07CEE -0x34 0x06CEB -0x34 0x05CE8 -0x34 0x04C6B -0x34 0x03C68 -0x34 0x0246b -0x34 0x01468 -0x34 0x0006b -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00040 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07), -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -0x3A 0x00400 //HG1 -0x3B 0x3a02c -0x3A 0x00420 //HG2 -0x3B 0x33064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x2b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x22a70 -0x3A 0x00410 //LG0 -0x3B 0x1a872 -0x3A 0x00418 //LG1 -0x3B 0x12080 -0x3A 0x00410 //ULG -0x3B 0x0b082 -0x3A 0x00410 //ULG -0x3B 0x03082 -//MB -0x3A 0x00400 //HG1 -0x3B 0x7a02c -0x3A 0x00420 //HG2 -0x3B 0x73064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x6b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x62a70 -0x3A 0x00410 //LG0 -0x3B 0x5a872 -0x3A 0x00418 //LG1 -0x3B 0x52080 -0x3A 0x00410 //ULG -0x3B 0x4b082 -0x3A 0x00410 //ULG -0x3B 0x43082 -//HB -0x3A 0x00400 //HG1 -0x3B 0xba02c -0x3A 0x00420 //HG2 -0x3B 0xb3064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0xab270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0xa2a70 -0x3A 0x00410 //LG0 -0x3B 0x9a872 -0x3A 0x00418 //LG1 -0x3B 0x92080 -0x3A 0x00410 //ULG -0x3B 0x8b082 -0x3A 0x00410 //ULG -0x3B 0x83082 - -//RX BandCap Setting // Shold set 0x3B, then 0x3A -0xEF 0x00800 -//LB -0x3B 0x00000 -0x3A 0x00003 -//MB -0x3B 0x40000 -0x3A 0x00002 -//HB -0x3B 0x80000 -0x3A 0x00002 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49CF6 -0x34 0x48CF3 -0x34 0x47CF1 -0x34 0x46CED -0x34 0x45CEA -0x34 0x448E9 -0x34 0x438C9 -0x34 0x424C9 -0x34 0x4144C -0x34 0x4004F -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29CF6 -0x34 0x28CF3 -0x34 0x27CF1 -0x34 0x26CED -0x34 0x25CEA -0x34 0x248EA -0x34 0x238C9 -0x34 0x224C9 -0x34 0x2144D -0x34 0x20050 -//TX AGC 5GL -0x34 0x0ACF7 -0x34 0x09CF3 -0x34 0x08CF1 -0x34 0x07CEE -0x34 0x06CEB -0x34 0x058EA -0x34 0x048C9 -0x34 0x034CA -0x34 0x0244D -0x34 0x01050 -0x34 0x0004D -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0xB4000 -0xEF 0x00000 - - -0xDF 0x00040 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -//0x58 0xE288C //LO leakage -//0x59 0x63082 //IQGEN -//0x61 0xF4C43 //0xEFC67 //PA -//0x62 0x38F48 //0x29B45 //PA -//0x63 0x72117 //0x72337 //PAD -//0x64 0x1A4AC //0x1A92C //PAD -//0x65 0x931DE //0x931DE //PAD -//0x61 0xF4C43 -//0x62 0x38F48 -//0x63 0x72117 -//0x64 0x1A4AC -//0x65 0x931DE - - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x72117 -0x64 0x194AC -0x65 0x931D5 - -//APK -0x63 0x721D7 //LB -//0x63 0x72117 //MB -//0x63 0x72317 //HB - -//LOK -0x58 0xE1F98 //LB -//0X58 0XDA184 //MB -//0X58 0XDA184 //HB - -//IQK -//0x59 0x63082 //LB -//0x59 0x63082 //MB -//0x59 0x63082 //HB - -0xffff 0xffff +//Release version: RLE442D.0702.2012 +//A MODE S0:5210 + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0xf8000 // RX 80M RCK offset + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x00380 +0x3E 0x00080 +0x3F 0x00320 +0x3E 0x00100 +0x3F 0x00300 +0x3E 0x00180 +0x3F 0x002A0 +0x3E 0x00200 +0x3F 0x00260 +0x3E 0x00280 +0x3F 0x00220 +0x3E 0x00300 +0x3F 0x00200 +0x3E 0x00380 +0x3F 0x000C0 +0xEF 0x00000 + +//Ioffset setting +0xEF 0x40000 +0x3E 0x00000 +0x3F 0x00017 //old:0x0000D +0x3E 0x00020 +0x3F 0x00015 //old:0x0000C +0x3E 0x00040 +0x3F 0x00014 //old:0x0000B +0xEF 0x00000 +//SYN setting +0xB0 0xFFFFF +0xB1 0x1FC1A +0xB2 0x4103F +0xB3 0xF0350 //Ires; F0340:Ibg +0xB4 0x1E68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg +0xB5 0x04BFF +0xB6 0x0A138 +0xB7 0x30008 //binary search +0xB8 0x86000 //A7458,Div to latch & PFD noninvter:A7440 +0xB9 0x08A00 +0xBA 0x86180 +0xBB 0x2CE80 +0xBC 0x40000 +0x18 0x1F12A //set ch42, do LCK +0xfe +0xfe +0xfe +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg +0x18 0x1712A //set ch42 + + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 //HG1 +0x3B 0x37a58 //HG2 +0x3B 0x2a590 //MG1 +0x3B 0x27a50 //MG2 +0x3B 0x18248 //LG +0x3B 0x10240 //ULG +0x3B 0x08240 //ULG +0x3B 0x00240 //ULG + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ACF7 +0x34 0x09CF4 +0x34 0x08CF1 +0x34 0x07CEE +0x34 0x06CEB +0x34 0x05CE8 +0x34 0x04C6B +0x34 0x03C68 +0x34 0x0246b +0x34 0x01468 +0x34 0x0006b +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00040 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07), +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +0x3A 0x00400 //HG1 +0x3B 0x3a02c +0x3A 0x00420 //HG2 +0x3B 0x33064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x2b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x22a70 +0x3A 0x00410 //LG0 +0x3B 0x1a872 +0x3A 0x00418 //LG1 +0x3B 0x12080 +0x3A 0x00410 //ULG +0x3B 0x0b082 +0x3A 0x00410 //ULG +0x3B 0x03082 +//MB +0x3A 0x00400 //HG1 +0x3B 0x7a02c +0x3A 0x00420 //HG2 +0x3B 0x73064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x6b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x62a70 +0x3A 0x00410 //LG0 +0x3B 0x5a872 +0x3A 0x00418 //LG1 +0x3B 0x52080 +0x3A 0x00410 //ULG +0x3B 0x4b082 +0x3A 0x00410 //ULG +0x3B 0x43082 +//HB +0x3A 0x00400 //HG1 +0x3B 0xba02c +0x3A 0x00420 //HG2 +0x3B 0xb3064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0xab270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0xa2a70 +0x3A 0x00410 //LG0 +0x3B 0x9a872 +0x3A 0x00418 //LG1 +0x3B 0x92080 +0x3A 0x00410 //ULG +0x3B 0x8b082 +0x3A 0x00410 //ULG +0x3B 0x83082 + +//RX BandCap Setting // Shold set 0x3B, then 0x3A +0xEF 0x00800 +//LB +0x3B 0x00000 +0x3A 0x00003 +//MB +0x3B 0x40000 +0x3A 0x00002 +//HB +0x3B 0x80000 +0x3A 0x00002 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49CF6 +0x34 0x48CF3 +0x34 0x47CF1 +0x34 0x46CED +0x34 0x45CEA +0x34 0x448E9 +0x34 0x438C9 +0x34 0x424C9 +0x34 0x4144C +0x34 0x4004F +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29CF6 +0x34 0x28CF3 +0x34 0x27CF1 +0x34 0x26CED +0x34 0x25CEA +0x34 0x248EA +0x34 0x238C9 +0x34 0x224C9 +0x34 0x2144D +0x34 0x20050 +//TX AGC 5GL +0x34 0x0ACF7 +0x34 0x09CF3 +0x34 0x08CF1 +0x34 0x07CEE +0x34 0x06CEB +0x34 0x058EA +0x34 0x048C9 +0x34 0x034CA +0x34 0x0244D +0x34 0x01050 +0x34 0x0004D +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0xB4000 +0xEF 0x00000 + + +0xDF 0x00040 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +//0x58 0xE288C //LO leakage +//0x59 0x63082 //IQGEN +//0x61 0xF4C43 //0xEFC67 //PA +//0x62 0x38F48 //0x29B45 //PA +//0x63 0x72117 //0x72337 //PAD +//0x64 0x1A4AC //0x1A92C //PAD +//0x65 0x931DE //0x931DE //PAD +//0x61 0xF4C43 +//0x62 0x38F48 +//0x63 0x72117 +//0x64 0x1A4AC +//0x65 0x931DE + + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x72117 +0x64 0x194AC +0x65 0x931D5 + +//APK +0x63 0x721D7 //LB +//0x63 0x72117 //MB +//0x63 0x72317 //HB + +//LOK +0x58 0xE1F98 //LB +//0X58 0XDA184 //MB +//0X58 0XDA184 //HB + +//IQK +//0x59 0x63082 //LB +//0x59 0x63082 //MB +//0x59 0x63082 //HB + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_hp.txt index 89c3dc17874..743a716cb16 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_hp.txt @@ -1,314 +1,314 @@ -//Release version: RLE442D.0702.2012 -//A MODE S0:5210 - -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0xf8000 // RX 80M RCK offset - -//VCO current -0xEF 0x20000 -0x3E 0x00380 -0x3F 0x90018 //old:0x80018 -0x3E 0x20380 -0x3F 0xA0018 //old:0x90018 -0x3E 0x40308 -0x3F 0xA0018 //old:0x90018 -0x3E 0x60018 -0x3F 0xA0018 -0xEF 0x00000 - -//Kvco setting -0xEF 0x10000 -0x3E 0x00000 -0x3F 0x00380 -0x3E 0x00080 -0x3F 0x00320 -0x3E 0x00100 -0x3F 0x00300 -0x3E 0x00180 -0x3F 0x002A0 -0x3E 0x00200 -0x3F 0x00260 -0x3E 0x00280 -0x3F 0x00220 -0x3E 0x00300 -0x3F 0x00200 -0x3E 0x00380 -0x3F 0x000C0 -0xEF 0x00000 - -//Ioffset setting -0xEF 0x40000 -0x3E 0x00000 -0x3F 0x00017 //old:0x0000D -0x3E 0x00020 -0x3F 0x00015 //old:0x0000C -0x3E 0x00040 -0x3F 0x00014 //old:0x0000B -0xEF 0x00000 -//SYN setting -0xB0 0xFFFFF -0xB1 0x1FC1A -0xB2 0x4103F -0xB3 0xF0350 //Ires; F0340:Ibg -0xB4 0x1E68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg -0xB5 0x04BFF -0xB6 0x0A138 -0xB7 0x30008 //binary search -0xB8 0x86000 //A7458,Div to latch & PFD noninvter:A7440 -0xB9 0x08A00 -0xBA 0x86180 -0xBB 0x2CE80 -0xBC 0x40000 -0x18 0x1F12A //set ch42, do LCK -0xfe -0xfe -0xfe -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg -0x18 0x1712A //set ch42 - - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 //HG1 -0x3B 0x37a58 //HG2 -0x3B 0x2a590 //MG1 -0x3B 0x27a50 //MG2 -0x3B 0x18248 //LG -0x3B 0x10240 //ULG -0x3B 0x08240 //ULG -0x3B 0x00240 //ULG - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ACF7 -0x34 0x09CF4 -0x34 0x08CF1 -0x34 0x07CEE -0x34 0x06CEB -0x34 0x05CE8 -0x34 0x04C6B -0x34 0x03C68 -0x34 0x0246b -0x34 0x01468 -0x34 0x0006b -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00040 // APK setting in debug mode -0x35 0x00120 -0x35 0x08120 -0x35 0x10120 -0x36 0x00085 //(ch11 bandedge 00685) -0x36 0x08085 //(ch11 bandedge 00685) -0x36 0x10085 //(ch11 bandedge 00685) -0x36 0x18085 //(ch11 bandedge 00685) -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x00622 -0x53 0xFC70B //APK -0x54 0x0017E //LC tank (ch01~ch07), -//0x54 0x0013E //LC tank (ch08~ch13) - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//RX AGC 5GL -0x3A 0x00400 //HG1 -0x3B 0x3a02c -0x3A 0x00420 //HG2 -0x3B 0x33064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x2b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x22a70 -0x3A 0x00410 //LG0 -0x3B 0x1a872 -0x3A 0x00418 //LG1 -0x3B 0x12080 -0x3A 0x00410 //ULG -0x3B 0x0b082 -0x3A 0x00410 //ULG -0x3B 0x03082 -//MB -0x3A 0x00400 //HG1 -0x3B 0x7a02c -0x3A 0x00420 //HG2 -0x3B 0x73064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x6b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x62a70 -0x3A 0x00410 //LG0 -0x3B 0x5a872 -0x3A 0x00418 //LG1 -0x3B 0x52080 -0x3A 0x00410 //ULG -0x3B 0x4b082 -0x3A 0x00410 //ULG -0x3B 0x43082 -//HB -0x3A 0x00400 //HG1 -0x3B 0xba02c -0x3A 0x00420 //HG2 -0x3B 0xb3064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0xab270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0xa2a70 -0x3A 0x00410 //LG0 -0x3B 0x9a872 -0x3A 0x00418 //LG1 -0x3B 0x92080 -0x3A 0x00410 //ULG -0x3B 0x8b082 -0x3A 0x00410 //ULG -0x3B 0x83082 - -//RX BandCap Setting // Shold set 0x3B, then 0x3A -0xEF 0x00800 -//LB -0x3B 0x00000 -0x3A 0x00003 -//MB -0x3B 0x40000 -0x3A 0x00002 -//HB -0x3B 0x80000 -0x3A 0x00002 - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A03B -0x34 0x49038 -0x34 0x48036 -0x34 0x47033 -0x34 0x46030 -0x34 0x4502D -0x34 0x44010 -0x34 0x4300D -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A03B -0x34 0x29038 -0x34 0x28036 -0x34 0x27033 -0x34 0x26030 -0x34 0x2502D -0x34 0x24010 -0x34 0x2300D -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A03B -0x34 0x09038 -0x34 0x08036 -0x34 0x07033 -0x34 0x06030 -0x34 0x0502D -0x34 0x04010 -0x34 0x0300D -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0xB4000 -0xEF 0x00000 - - -0xDF 0x00040 //0x00FC0 -0x1F 0x40064 //RC BW for 80M -//0x58 0xE288C //LO leakage -//0x59 0x63082 //IQGEN -//0x61 0xF4C43 //0xEFC67 //PA -//0x62 0x38F48 //0x29B45 //PA -//0x63 0x72117 //0x72337 //PAD -//0x64 0x1A4AC //0x1A92C //PAD -//0x65 0x931DE //0x931DE //PAD -//0x61 0xF4C43 -//0x62 0x38F48 -//0x63 0x72117 -//0x64 0x1A4AC -//0x65 0x931DE - - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x72117 -0x64 0x194AC -0x65 0x931D1 - -//APK -0x63 0x721D7 //LB -//0x63 0x72117 //MB -//0x63 0x72317 //HB - -//LOK -0x58 0xE1F98 //LB -//0X58 0XDA184 //MB -//0X58 0XDA184 //HB - -//IQK -//0x59 0x6A082 //LB -//0x59 0x63082 //MB -//0x59 0x63082 //HB - -0xffff 0xffff +//Release version: RLE442D.0702.2012 +//A MODE S0:5210 + +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0xf8000 // RX 80M RCK offset + +//VCO current +0xEF 0x20000 +0x3E 0x00380 +0x3F 0x90018 //old:0x80018 +0x3E 0x20380 +0x3F 0xA0018 //old:0x90018 +0x3E 0x40308 +0x3F 0xA0018 //old:0x90018 +0x3E 0x60018 +0x3F 0xA0018 +0xEF 0x00000 + +//Kvco setting +0xEF 0x10000 +0x3E 0x00000 +0x3F 0x00380 +0x3E 0x00080 +0x3F 0x00320 +0x3E 0x00100 +0x3F 0x00300 +0x3E 0x00180 +0x3F 0x002A0 +0x3E 0x00200 +0x3F 0x00260 +0x3E 0x00280 +0x3F 0x00220 +0x3E 0x00300 +0x3F 0x00200 +0x3E 0x00380 +0x3F 0x000C0 +0xEF 0x00000 + +//Ioffset setting +0xEF 0x40000 +0x3E 0x00000 +0x3F 0x00017 //old:0x0000D +0x3E 0x00020 +0x3F 0x00015 //old:0x0000C +0x3E 0x00040 +0x3F 0x00014 //old:0x0000B +0xEF 0x00000 +//SYN setting +0xB0 0xFFFFF +0xB1 0x1FC1A +0xB2 0x4103F +0xB3 0xF0350 //Ires; F0340:Ibg +0xB4 0x1E68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg +0xB5 0x04BFF +0xB6 0x0A138 +0xB7 0x30008 //binary search +0xB8 0x86000 //A7458,Div to latch & PFD noninvter:A7440 +0xB9 0x08A00 +0xBA 0x86180 +0xBB 0x2CE80 +0xBC 0x40000 +0x18 0x1F12A //set ch42, do LCK +0xfe +0xfe +0xfe +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A68D //LC CAL, NORMAL OPERATION:1A68D(Ires); 1A689:Ibg +0x18 0x1712A //set ch42 + + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 //HG1 +0x3B 0x37a58 //HG2 +0x3B 0x2a590 //MG1 +0x3B 0x27a50 //MG2 +0x3B 0x18248 //LG +0x3B 0x10240 //ULG +0x3B 0x08240 //ULG +0x3B 0x00240 //ULG + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ACF7 +0x34 0x09CF4 +0x34 0x08CF1 +0x34 0x07CEE +0x34 0x06CEB +0x34 0x05CE8 +0x34 0x04C6B +0x34 0x03C68 +0x34 0x0246b +0x34 0x01468 +0x34 0x0006b +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00040 // APK setting in debug mode +0x35 0x00120 +0x35 0x08120 +0x35 0x10120 +0x36 0x00085 //(ch11 bandedge 00685) +0x36 0x08085 //(ch11 bandedge 00685) +0x36 0x10085 //(ch11 bandedge 00685) +0x36 0x18085 //(ch11 bandedge 00685) +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x00622 +0x53 0xFC70B //APK +0x54 0x0017E //LC tank (ch01~ch07), +//0x54 0x0013E //LC tank (ch08~ch13) + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//RX AGC 5GL +0x3A 0x00400 //HG1 +0x3B 0x3a02c +0x3A 0x00420 //HG2 +0x3B 0x33064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x2b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x22a70 +0x3A 0x00410 //LG0 +0x3B 0x1a872 +0x3A 0x00418 //LG1 +0x3B 0x12080 +0x3A 0x00410 //ULG +0x3B 0x0b082 +0x3A 0x00410 //ULG +0x3B 0x03082 +//MB +0x3A 0x00400 //HG1 +0x3B 0x7a02c +0x3A 0x00420 //HG2 +0x3B 0x73064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x6b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x62a70 +0x3A 0x00410 //LG0 +0x3B 0x5a872 +0x3A 0x00418 //LG1 +0x3B 0x52080 +0x3A 0x00410 //ULG +0x3B 0x4b082 +0x3A 0x00410 //ULG +0x3B 0x43082 +//HB +0x3A 0x00400 //HG1 +0x3B 0xba02c +0x3A 0x00420 //HG2 +0x3B 0xb3064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0xab270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0xa2a70 +0x3A 0x00410 //LG0 +0x3B 0x9a872 +0x3A 0x00418 //LG1 +0x3B 0x92080 +0x3A 0x00410 //ULG +0x3B 0x8b082 +0x3A 0x00410 //ULG +0x3B 0x83082 + +//RX BandCap Setting // Shold set 0x3B, then 0x3A +0xEF 0x00800 +//LB +0x3B 0x00000 +0x3A 0x00003 +//MB +0x3B 0x40000 +0x3A 0x00002 +//HB +0x3B 0x80000 +0x3A 0x00002 + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A03B +0x34 0x49038 +0x34 0x48036 +0x34 0x47033 +0x34 0x46030 +0x34 0x4502D +0x34 0x44010 +0x34 0x4300D +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A03B +0x34 0x29038 +0x34 0x28036 +0x34 0x27033 +0x34 0x26030 +0x34 0x2502D +0x34 0x24010 +0x34 0x2300D +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A03B +0x34 0x09038 +0x34 0x08036 +0x34 0x07033 +0x34 0x06030 +0x34 0x0502D +0x34 0x04010 +0x34 0x0300D +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0xB4000 +0xEF 0x00000 + + +0xDF 0x00040 //0x00FC0 +0x1F 0x40064 //RC BW for 80M +//0x58 0xE288C //LO leakage +//0x59 0x63082 //IQGEN +//0x61 0xF4C43 //0xEFC67 //PA +//0x62 0x38F48 //0x29B45 //PA +//0x63 0x72117 //0x72337 //PAD +//0x64 0x1A4AC //0x1A92C //PAD +//0x65 0x931DE //0x931DE //PAD +//0x61 0xF4C43 +//0x62 0x38F48 +//0x63 0x72117 +//0x64 0x1A4AC +//0x65 0x931DE + + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x72117 +0x64 0x194AC +0x65 0x931D1 + +//APK +0x63 0x721D7 //LB +//0x63 0x72117 //MB +//0x63 0x72317 //HB + +//LOK +0x58 0xE1F98 //LB +//0X58 0XDA184 //MB +//0X58 0XDA184 //HB + +//IQK +//0x59 0x6A082 //LB +//0x59 0x63082 //MB +//0x59 0x63082 //HB + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_default.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_default.txt index f70f16d85eb..a24936c46f9 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_default.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_default.txt @@ -1,279 +1,279 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x00 0x10000 // enter standby mode -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0x80000 // RX 80M RCK offset -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x87180 - -//SYN setting -//0xB0 0xFFFFF -0xB1 0x1FC1A -//0xB2 0x4103F -0xB3 0xF0810 -0xB4 0x1A78D -//0xB5 0x04BFF -//0xB6 0x0A138 -//0xB7 0x30008 //binary search -//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 -//0xB9 0x08A00 -0xBA 0x86180 -//0xBB 0x2CE80 -//0xBC 0x40000 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S0 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write 2G LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DF2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x24DE3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0AFF7 -0x34 0x09DF7 -0x34 0x08DF4 -0x34 0x07DF1 -0x34 0x06DEE -0x34 0x05DEB -0x34 0x04DE8 -0x34 0x038CC -0x34 0x028C9 -0x34 0x018C6 -0x34 0x008C3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00188 -0x35 0x08147 -0x35 0x10147 -0x35 0x201D7 -0x35 0x281D7 -0x35 0x301D7 -0x35 0x401D8 -0x35 0x481D8 -0x35 0x501D8 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x84EB4 // LB 80M -0x36 0x8CC35 // LB 40M -0x36 0x94C35 // LB NA -0x36 0x9CC35 // LB 20M -0x36 0xA4C35 // MB 80M -0x36 0xACC35 // MB 40M -0x36 0xB4C35 // MB NA -0x36 0xBCC35 // MB 20M -0x36 0xC4C34 // HB 80M -0x36 0xCCC35 // HB 40M -0x36 0xD4C35 // HB NA -0x36 0xDCC35 // HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002A8 -0x3C 0x005A2 -0x3C 0x00880 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xB4000 -//0xEF 0x00000 - -0xDF 0x00080 //0x00FC0 -0x1F 0x00064 //RC BW for 80M - -0x61 0xE5D53 -0x62 0x38FCD -0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 -0x64 0x196AC -0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 - -//LOK -0x08 0x08400 //write 5G LOK table default value - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0xB4 0x1E78D -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A78D -0x18 0x1712A //set channel again - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x00 0x10000 // enter standby mode +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0x80000 // RX 80M RCK offset +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x87180 + +//SYN setting +//0xB0 0xFFFFF +0xB1 0x1FC1A +//0xB2 0x4103F +0xB3 0xF0810 +0xB4 0x1A78D +//0xB5 0x04BFF +//0xB6 0x0A138 +//0xB7 0x30008 //binary search +//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 +//0xB9 0x08A00 +0xBA 0x86180 +//0xBB 0x2CE80 +//0xBC 0x40000 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S0 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write 2G LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DF2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x24DE3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0AFF7 +0x34 0x09DF7 +0x34 0x08DF4 +0x34 0x07DF1 +0x34 0x06DEE +0x34 0x05DEB +0x34 0x04DE8 +0x34 0x038CC +0x34 0x028C9 +0x34 0x018C6 +0x34 0x008C3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00188 +0x35 0x08147 +0x35 0x10147 +0x35 0x201D7 +0x35 0x281D7 +0x35 0x301D7 +0x35 0x401D8 +0x35 0x481D8 +0x35 0x501D8 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x84EB4 // LB 80M +0x36 0x8CC35 // LB 40M +0x36 0x94C35 // LB NA +0x36 0x9CC35 // LB 20M +0x36 0xA4C35 // MB 80M +0x36 0xACC35 // MB 40M +0x36 0xB4C35 // MB NA +0x36 0xBCC35 // MB 20M +0x36 0xC4C34 // HB 80M +0x36 0xCCC35 // HB 40M +0x36 0xD4C35 // HB NA +0x36 0xDCC35 // HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002A8 +0x3C 0x005A2 +0x3C 0x00880 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xB4000 +//0xEF 0x00000 + +0xDF 0x00080 //0x00FC0 +0x1F 0x00064 //RC BW for 80M + +0x61 0xE5D53 +0x62 0x38FCD +0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 +0x64 0x196AC +0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 + +//LOK +0x08 0x08400 //write 5G LOK table default value + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0xB4 0x1E78D +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A78D +0x18 0x1712A //set channel again + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extlna.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extlna.txt index dd83f8bdf12..d62affeb94d 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extlna.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extlna.txt @@ -1,279 +1,279 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x00 0x10000 // enter standby mode -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0x80000 // RX 80M RCK offset -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -//SYN setting -//0xB0 0xFFFFF -0xB1 0x1FC1A -//0xB2 0x4103F -0xB3 0xF0810 -0xB4 0x1A78D -//0xB5 0x04BFF -//0xB6 0x0A138 -//0xB7 0x30008 //binary search -//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 -//0xB9 0x08A00 -0xBA 0x86180 -//0xBB 0x2CE80 -//0xBC 0x40000 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S0 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write 2G LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DF2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x24DE3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0AFF7 -0x34 0x09DF7 -0x34 0x08DF4 -0x34 0x07DF1 -0x34 0x06DEE -0x34 0x05DEB -0x34 0x04DE8 -0x34 0x038CC -0x34 0x028C9 -0x34 0x018C6 -0x34 0x008C3 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00188 -0x35 0x08147 -0x35 0x10147 -0x35 0x201D7 -0x35 0x281D7 -0x35 0x301D7 -0x35 0x401D8 -0x35 0x481D8 -0x35 0x501D8 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x84EB4 // LB 80M -0x36 0x8CC35 // LB 40M -0x36 0x94C35 // LB NA -0x36 0x9CC35 // LB 20M -0x36 0xA4C35 // MB 80M -0x36 0xACC35 // MB 40M -0x36 0xB4C35 // MB NA -0x36 0xBCC35 // MB 20M -0x36 0xC4C34 // HB 80M -0x36 0xCCC35 // HB 40M -0x36 0xD4C35 // HB NA -0x36 0xDCC35 // HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002A8 -0x3C 0x005A2 -0x3C 0x00880 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xB4000 -//0xEF 0x00000 - -0xDF 0x00080 //0x00FC0 -0x1F 0x00064 //RC BW for 80M - -0x61 0xE5D53 -0x62 0x38FCD -0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 -0x64 0x196AC -0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 - -//LOK -0x08 0x08400 //write 5G LOK table default value - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0xB4 0x1E78D -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A78D -0x18 0x1712A //set channel again - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x00 0x10000 // enter standby mode +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0x80000 // RX 80M RCK offset +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +//SYN setting +//0xB0 0xFFFFF +0xB1 0x1FC1A +//0xB2 0x4103F +0xB3 0xF0810 +0xB4 0x1A78D +//0xB5 0x04BFF +//0xB6 0x0A138 +//0xB7 0x30008 //binary search +//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 +//0xB9 0x08A00 +0xBA 0x86180 +//0xBB 0x2CE80 +//0xBC 0x40000 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S0 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write 2G LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DF2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x24DE3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0AFF7 +0x34 0x09DF7 +0x34 0x08DF4 +0x34 0x07DF1 +0x34 0x06DEE +0x34 0x05DEB +0x34 0x04DE8 +0x34 0x038CC +0x34 0x028C9 +0x34 0x018C6 +0x34 0x008C3 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00188 +0x35 0x08147 +0x35 0x10147 +0x35 0x201D7 +0x35 0x281D7 +0x35 0x301D7 +0x35 0x401D8 +0x35 0x481D8 +0x35 0x501D8 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x84EB4 // LB 80M +0x36 0x8CC35 // LB 40M +0x36 0x94C35 // LB NA +0x36 0x9CC35 // LB 20M +0x36 0xA4C35 // MB 80M +0x36 0xACC35 // MB 40M +0x36 0xB4C35 // MB NA +0x36 0xBCC35 // MB 20M +0x36 0xC4C34 // HB 80M +0x36 0xCCC35 // HB 40M +0x36 0xD4C35 // HB NA +0x36 0xDCC35 // HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002A8 +0x3C 0x005A2 +0x3C 0x00880 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xB4000 +//0xEF 0x00000 + +0xDF 0x00080 //0x00FC0 +0x1F 0x00064 //RC BW for 80M + +0x61 0xE5D53 +0x62 0x38FCD +0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 +0x64 0x196AC +0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 + +//LOK +0x08 0x08400 //write 5G LOK table default value + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0xB4 0x1E78D +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A78D +0x18 0x1712A //set channel again + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extpa.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extpa.txt index e7f3ec8e521..3e48f93d072 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extpa.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_extpa.txt @@ -1,279 +1,279 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x00 0x10000 // enter standby mode -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0x80000 // RX 80M RCK offset -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x87180 - -//SYN setting -//0xB0 0xFFFFF -0xB1 0x1FC1A -//0xB2 0x4103F -0xB3 0xF0810 -0xB4 0x1A78D -//0xB5 0x04BFF -//0xB6 0x0A138 -//0xB7 0x30008 //binary search -//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 -//0xB9 0x08A00 -0xBA 0x86180 -//0xBB 0x2CE80 -//0xBC 0x40000 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S0 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write 2G LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xB4000 -//0xEF 0x00000 - -0xDF 0x00080 //0x00FC0 -0x1F 0x00064 //RC BW for 80M - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - -//LOK -0x08 0x08400 //write 5G LOK table default value - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0xB4 0x1E78D -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A78D -0x18 0x1712A //set channel again - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x00 0x10000 // enter standby mode +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0x80000 // RX 80M RCK offset +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x87180 + +//SYN setting +//0xB0 0xFFFFF +0xB1 0x1FC1A +//0xB2 0x4103F +0xB3 0xF0810 +0xB4 0x1A78D +//0xB5 0x04BFF +//0xB6 0x0A138 +//0xB7 0x30008 //binary search +//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 +//0xB9 0x08A00 +0xBA 0x86180 +//0xBB 0x2CE80 +//0xBC 0x40000 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S0 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write 2G LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xB4000 +//0xEF 0x00000 + +0xDF 0x00080 //0x00FC0 +0x1F 0x00064 //RC BW for 80M + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + +//LOK +0x08 0x08400 //write 5G LOK table default value + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0xB4 0x1E78D +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A78D +0x18 0x1712A //set channel again + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_hp.txt index 045a86a2a00..43c8998617b 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_hp.txt @@ -1,279 +1,279 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x00 0x10000 // enter standby mode -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0x80000 // RX 80M RCK offset -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -//SYN setting -//0xB0 0xFFFFF -0xB1 0x1FC1A -//0xB2 0x4103F -0xB3 0xF0810 -0xB4 0x1A78D -//0xB5 0x04BFF -//0xB6 0x0A138 -//0xB7 0x30008 //binary search -//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 -//0xB9 0x08A00 -0xBA 0x86180 -//0xBB 0x2CE80 -//0xBC 0x40000 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S0 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write 2G LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xB4000 -//0xEF 0x00000 - -0xDF 0x00080 //0x00FC0 -0x1F 0x00064 //RC BW for 80M - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x32117 -0x64 0x194AC -0x65 0x931D1 - -//LOK -0x08 0x08400 //write 5G LOK table default value - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0xB4 0x1E78D -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A78D -0x18 0x1712A //set channel again - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x00 0x10000 // enter standby mode +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0x80000 // RX 80M RCK offset +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +//SYN setting +//0xB0 0xFFFFF +0xB1 0x1FC1A +//0xB2 0x4103F +0xB3 0xF0810 +0xB4 0x1A78D +//0xB5 0x04BFF +//0xB6 0x0A138 +//0xB7 0x30008 //binary search +//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 +//0xB9 0x08A00 +0xBA 0x86180 +//0xBB 0x2CE80 +//0xBC 0x40000 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S0 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write 2G LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xB4000 +//0xEF 0x00000 + +0xDF 0x00080 //0x00FC0 +0x1F 0x00064 //RC BW for 80M + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x32117 +0x64 0x194AC +0x65 0x931D1 + +//LOK +0x08 0x08400 //write 5G LOK table default value + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0xB4 0x1E78D +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A78D +0x18 0x1712A //set channel again + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_ultra_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_ultra_hp.txt old mode 100755 new mode 100644 index c5db82085a5..053af6ceb9b --- a/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_ultra_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioA_8812_n_ultra_hp.txt @@ -1,279 +1,279 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x00 0x10000 // enter standby mode -0x18 0x1712A //set ch42 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x1E 0x80000 // RX 80M RCK offset -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -//SYN setting -//0xB0 0xFFFFF -0xB1 0x1FC1A -//0xB2 0x4103F -0xB3 0xF0810 -0xB4 0x1A78D -//0xB5 0x04BFF -//0xB6 0x0A138 -//0xB7 0x30008 //binary search -//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 -//0xB9 0x08A00 -0xBA 0x86180 -//0xBB 0x2CE80 -//0xBC 0x40000 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S0 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write 2G LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S0 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x4604D -0x34 0x4504A -0x34 0x44047 -0x34 0x43044 -0x34 0x42007 -0x34 0x41004 -0x34 0x40001 -//TX AGC 5GM -0x34 0x2A0B4 -0x34 0x290B1 -0x34 0x28072 -0x34 0x2706F -0x34 0x2604F -0x34 0x2504C -0x34 0x24049 -0x34 0x23046 -0x34 0x22009 -0x34 0x21006 -0x34 0x20003 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x0604D -0x34 0x0504A -0x34 0x04047 -0x34 0x03044 -0x34 0x02007 -0x34 0x01004 -0x34 0x00001 -0xEF 0x00000 - -//Table_5G_Bias_I_S0 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S0 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S0 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xB4000 -//0xEF 0x00000 - -0xDF 0x00080 //0x00FC0 -0x1F 0x00064 //RC BW for 80M - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x32117 -0x64 0x194AC -0x65 0x931D2 - -//LOK -0x08 0x08400 //write 5G LOK table default value - -//RCK -0x1C 0x739D2 // 0x1c[1]=1 - -//LCK -0xB4 0x1E78D -0x18 0x1F12A //set ch42; do LCK -0xfe -0xfe -0xfe -0xfe -0xB4 0x1A78D -0x18 0x1712A //set channel again - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x00 0x10000 // enter standby mode +0x18 0x1712A //set ch42 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x1E 0x80000 // RX 80M RCK offset +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +//SYN setting +//0xB0 0xFFFFF +0xB1 0x1FC1A +//0xB2 0x4103F +0xB3 0xF0810 +0xB4 0x1A78D +//0xB5 0x04BFF +//0xB6 0x0A138 +//0xB7 0x30008 //binary search +//0xB8 0x86000 //A7458; Div to latch & PFD noninvter:A7440 +//0xB9 0x08A00 +0xBA 0x86180 +//0xBB 0x2CE80 +//0xBC 0x40000 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S0 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write 2G LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S0 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x4604D +0x34 0x4504A +0x34 0x44047 +0x34 0x43044 +0x34 0x42007 +0x34 0x41004 +0x34 0x40001 +//TX AGC 5GM +0x34 0x2A0B4 +0x34 0x290B1 +0x34 0x28072 +0x34 0x2706F +0x34 0x2604F +0x34 0x2504C +0x34 0x24049 +0x34 0x23046 +0x34 0x22009 +0x34 0x21006 +0x34 0x20003 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x0604D +0x34 0x0504A +0x34 0x04047 +0x34 0x03044 +0x34 0x02007 +0x34 0x01004 +0x34 0x00001 +0xEF 0x00000 + +//Table_5G_Bias_I_S0 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S0 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S0 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xB4000 +//0xEF 0x00000 + +0xDF 0x00080 //0x00FC0 +0x1F 0x00064 //RC BW for 80M + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x32117 +0x64 0x194AC +0x65 0x931D2 + +//LOK +0x08 0x08400 //write 5G LOK table default value + +//RCK +0x1C 0x739D2 // 0x1c[1]=1 + +//LCK +0xB4 0x1E78D +0x18 0x1F12A //set ch42; do LCK +0xfe +0xfe +0xfe +0xfe +0xB4 0x1A78D +0x18 0x1712A //set channel again + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812.txt old mode 100755 new mode 100644 index 1c328d1f4b0..9c61983600a --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812.txt @@ -1,250 +1,250 @@ -//Release version: RLE442D.0702.2012 -//A MODE S0:5210 - -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -//0x1C 0x039d0 // Set max RX RCK offset - - - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 //HG1 -0x3B 0x37a58 //HG2 -0x3B 0x2a590 //MG1 -0x3B 0x27a50 //MG2 -0x3B 0x18248 //LG -0x3B 0x10240 //ULG -0x3B 0x08240 //ULG -0x3B 0x00240 //ULG - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0AD37 -0x34 0x09D34 -0x34 0x08D31 -0x34 0x07D2e -0x34 0x06D2b -0x34 0x05D28 -0x34 0x04Cab -0x34 0x03Ca8 -0x34 0x024ab -0x34 0x014a8 -0x34 0x000ab -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00040 // APK setting in debug mode -0x35 0x00123 -0x35 0x08123 -0x35 0x10123 -0x36 0x00085 -0x36 0x08085 -0x36 0x10085 -0x36 0x18085 -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x01222 -0x53 0xFC10B //APK path B -0x54 0x0017E //LC tank (ch01~ch07), -//0x54 0x0013E //LC tank (ch08~ch13) - - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//RX AGC 5GL -0x3A 0x00400 //HG1 -0x3B 0x3a02c -0x3A 0x00420 //HG2 -0x3B 0x33064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x2b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x22a70 -0x3A 0x00410 //LG0 -0x3B 0x1a872 -0x3A 0x00418 //LG1 -0x3B 0x12080 -0x3A 0x00410 //ULG -0x3B 0x0b082 -0x3A 0x00410 //ULG -0x3B 0x03082 -//RX AGC 5GM -0x3A 0x00400 //HG1 -0x3B 0x7a02c -0x3A 0x00420 //HG2 -0x3B 0x73064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x6b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x62a70 -0x3A 0x00410 //LG0 -0x3B 0x5a872 -0x3A 0x00418 //LG1 -0x3B 0x52080 -0x3A 0x00410 //ULG -0x3B 0x4b082 -0x3A 0x00410 //ULG -0x3B 0x43082 -//RX AGC 5GH -0x3A 0x00400 //HG1 -0x3B 0xBa02c -0x3A 0x00420 //HG2 -0x3B 0xB3064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0xAb270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0xA2a70 -0x3A 0x00410 //LG0 -0x3B 0x9a872 -0x3A 0x00418 //LG1 -0x3B 0x92080 -0x3A 0x00410 //ULG -0x3B 0x8b082 -0x3A 0x00410 //ULG -0x3B 0x83082 - -//RX BandCap Setting // Shold set 0x3B, then 0x3A -0xEF 0x00800 -//LB -0x3B 0x00000 -0x3A 0x00003 -//MB -0x3B 0x40000 -0x3A 0x00002 -//HB -0x3B 0x80000 -0x3A 0x00002 - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49CF6 -0x34 0x48CF3 -0x34 0x47CF1 -0x34 0x46CED -0x34 0x45CEA -0x34 0x448E9 -0x34 0x438C9 -0x34 0x424C9 -0x34 0x4144C -0x34 0x4004F -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29CF6 -0x34 0x28CF3 -0x34 0x27CF1 -0x34 0x26CED -0x34 0x25CEA -0x34 0x248EA -0x34 0x238C9 -0x34 0x224C9 -0x34 0x2144D -0x34 0x20050 -//TX AGC 5GL -0x34 0x0ACF7 -0x34 0x09CF3 -0x34 0x08CF1 -0x34 0x07CEE -0x34 0x06CEB -0x34 0x058EA -0x34 0x048C9 -0x34 0x034CA -0x34 0x0244D -0x34 0x01050 -0x34 0x0004D -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001D4 -0x35 0x081D4 -0x35 0x101D4 -0x35 0x201B4 -0x35 0x281B4 -0x35 0x301B4 -0x35 0x401B4 -0x35 0x481B4 -0x35 0x501B4 -0xEF 0x00000 - -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x04BFB -0x36 0x0CBFB -0x36 0x14BFB -0x36 0x1CBFB -0x36 0x24F4B -0x36 0x2CF4B -0x36 0x34F4B -0x36 0x3CF4B -0x36 0x44F4B -0x36 0x4CF4B -0x36 0x54F4B -0x36 0x5CF4B -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002CC -0x3C 0x00522 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0xFC400 -0xEF 0x00000 - - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00040 -0x58 0xE1F98 //LO leakage -//0x59 0x6A002 //IQGEN -0x1C 0x339D0 //S1 RC BW for 80M -//0x61 0xF4C43 //0xEFC67 //PA -//0x62 0x38F48 //0x29B45 //PA -//0x63 0x72117 //0x72337 //PAD -//0x64 0x1A4AC //0x1A92C //PAD -//0x65 0x931DE //0x931DE //PAD -//0x61 0xF4C43 -//0x62 0x38F48 -//0x63 0x72117 -//0x64 0x1A4AC -//0x65 0x931DE - - -0x61 0xFDD43 -0x62 0x38F4B -0x63 0x72117 -0x64 0x194AC -0x65 0x931D5 - -//APK -0x63 0x721D7 //LB -//0x63 0x72117 //MB -//0x63 0x72317 //HB - -//LOK -0x58 0xE1F98 //LB -//0X58 0XDA184 //MB -//0X58 0XDA184 //HB - -//IQK -//0x59 0x6A002 //LB -//0x59 0x6A002 //MB -//0x59 0x69002 //HB - -0xffff 0xffff +//Release version: RLE442D.0702.2012 +//A MODE S0:5210 + +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +//0x1C 0x039d0 // Set max RX RCK offset + + + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 //HG1 +0x3B 0x37a58 //HG2 +0x3B 0x2a590 //MG1 +0x3B 0x27a50 //MG2 +0x3B 0x18248 //LG +0x3B 0x10240 //ULG +0x3B 0x08240 //ULG +0x3B 0x00240 //ULG + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0AD37 +0x34 0x09D34 +0x34 0x08D31 +0x34 0x07D2e +0x34 0x06D2b +0x34 0x05D28 +0x34 0x04Cab +0x34 0x03Ca8 +0x34 0x024ab +0x34 0x014a8 +0x34 0x000ab +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00040 // APK setting in debug mode +0x35 0x00123 +0x35 0x08123 +0x35 0x10123 +0x36 0x00085 +0x36 0x08085 +0x36 0x10085 +0x36 0x18085 +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x01222 +0x53 0xFC10B //APK path B +0x54 0x0017E //LC tank (ch01~ch07), +//0x54 0x0013E //LC tank (ch08~ch13) + + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//RX AGC 5GL +0x3A 0x00400 //HG1 +0x3B 0x3a02c +0x3A 0x00420 //HG2 +0x3B 0x33064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x2b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x22a70 +0x3A 0x00410 //LG0 +0x3B 0x1a872 +0x3A 0x00418 //LG1 +0x3B 0x12080 +0x3A 0x00410 //ULG +0x3B 0x0b082 +0x3A 0x00410 //ULG +0x3B 0x03082 +//RX AGC 5GM +0x3A 0x00400 //HG1 +0x3B 0x7a02c +0x3A 0x00420 //HG2 +0x3B 0x73064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x6b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x62a70 +0x3A 0x00410 //LG0 +0x3B 0x5a872 +0x3A 0x00418 //LG1 +0x3B 0x52080 +0x3A 0x00410 //ULG +0x3B 0x4b082 +0x3A 0x00410 //ULG +0x3B 0x43082 +//RX AGC 5GH +0x3A 0x00400 //HG1 +0x3B 0xBa02c +0x3A 0x00420 //HG2 +0x3B 0xB3064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0xAb270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0xA2a70 +0x3A 0x00410 //LG0 +0x3B 0x9a872 +0x3A 0x00418 //LG1 +0x3B 0x92080 +0x3A 0x00410 //ULG +0x3B 0x8b082 +0x3A 0x00410 //ULG +0x3B 0x83082 + +//RX BandCap Setting // Shold set 0x3B, then 0x3A +0xEF 0x00800 +//LB +0x3B 0x00000 +0x3A 0x00003 +//MB +0x3B 0x40000 +0x3A 0x00002 +//HB +0x3B 0x80000 +0x3A 0x00002 + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49CF6 +0x34 0x48CF3 +0x34 0x47CF1 +0x34 0x46CED +0x34 0x45CEA +0x34 0x448E9 +0x34 0x438C9 +0x34 0x424C9 +0x34 0x4144C +0x34 0x4004F +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29CF6 +0x34 0x28CF3 +0x34 0x27CF1 +0x34 0x26CED +0x34 0x25CEA +0x34 0x248EA +0x34 0x238C9 +0x34 0x224C9 +0x34 0x2144D +0x34 0x20050 +//TX AGC 5GL +0x34 0x0ACF7 +0x34 0x09CF3 +0x34 0x08CF1 +0x34 0x07CEE +0x34 0x06CEB +0x34 0x058EA +0x34 0x048C9 +0x34 0x034CA +0x34 0x0244D +0x34 0x01050 +0x34 0x0004D +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001D4 +0x35 0x081D4 +0x35 0x101D4 +0x35 0x201B4 +0x35 0x281B4 +0x35 0x301B4 +0x35 0x401B4 +0x35 0x481B4 +0x35 0x501B4 +0xEF 0x00000 + +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x04BFB +0x36 0x0CBFB +0x36 0x14BFB +0x36 0x1CBFB +0x36 0x24F4B +0x36 0x2CF4B +0x36 0x34F4B +0x36 0x3CF4B +0x36 0x44F4B +0x36 0x4CF4B +0x36 0x54F4B +0x36 0x5CF4B +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002CC +0x3C 0x00522 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0xFC400 +0xEF 0x00000 + + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00040 +0x58 0xE1F98 //LO leakage +//0x59 0x6A002 //IQGEN +0x1C 0x339D0 //S1 RC BW for 80M +//0x61 0xF4C43 //0xEFC67 //PA +//0x62 0x38F48 //0x29B45 //PA +//0x63 0x72117 //0x72337 //PAD +//0x64 0x1A4AC //0x1A92C //PAD +//0x65 0x931DE //0x931DE //PAD +//0x61 0xF4C43 +//0x62 0x38F48 +//0x63 0x72117 +//0x64 0x1A4AC +//0x65 0x931DE + + +0x61 0xFDD43 +0x62 0x38F4B +0x63 0x72117 +0x64 0x194AC +0x65 0x931D5 + +//APK +0x63 0x721D7 //LB +//0x63 0x72117 //MB +//0x63 0x72317 //HB + +//LOK +0x58 0xE1F98 //LB +//0X58 0XDA184 //MB +//0X58 0XDA184 //HB + +//IQK +//0x59 0x6A002 //LB +//0x59 0x6A002 //MB +//0x59 0x69002 //HB + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_hp.txt index ac1be17139a..4e2bba98554 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_hp.txt @@ -1,249 +1,249 @@ -//Release version: RLE442D.0702.2012 -//A MODE S0:5210 - -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -//0x1C 0x039d0 // Set max RX RCK offset - - - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 //HG1 -0x3B 0x37a58 //HG2 -0x3B 0x2a590 //MG1 -0x3B 0x27a50 //MG2 -0x3B 0x18248 //LG -0x3B 0x10240 //ULG -0x3B 0x08240 //ULG -0x3B 0x00240 //ULG - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0AD37 -0x34 0x09D34 -0x34 0x08D31 -0x34 0x07D2e -0x34 0x06D2b -0x34 0x05D28 -0x34 0x04Cab -0x34 0x03Ca8 -0x34 0x024ab -0x34 0x014a8 -0x34 0x000ab -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00040 // APK setting in debug mode -0x35 0x00123 -0x35 0x08123 -0x35 0x10123 -0x36 0x00085 -0x36 0x08085 -0x36 0x10085 -0x36 0x18085 -0xEF 0x00000 - -0x51 0x00C31 -0x52 0x01222 -0x53 0xFC10B //APK path B -0x54 0x0017E //LC tank (ch01~ch07), -//0x54 0x0013E //LC tank (ch08~ch13) - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//RX AGC 5GL -0x3A 0x00400 //HG1 -0x3B 0x3a02c -0x3A 0x00420 //HG2 -0x3B 0x33064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x2b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x22a70 -0x3A 0x00410 //LG0 -0x3B 0x1a872 -0x3A 0x00418 //LG1 -0x3B 0x12080 -0x3A 0x00410 //ULG -0x3B 0x0b082 -0x3A 0x00410 //ULG -0x3B 0x03082 -//RX AGC 5GM -0x3A 0x00400 //HG1 -0x3B 0x7a02c -0x3A 0x00420 //HG2 -0x3B 0x73064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0x6b270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0x62a70 -0x3A 0x00410 //LG0 -0x3B 0x5a872 -0x3A 0x00418 //LG1 -0x3B 0x52080 -0x3A 0x00410 //ULG -0x3B 0x4b082 -0x3A 0x00410 //ULG -0x3B 0x43082 -//RX AGC 5GH -0x3A 0x00400 //HG1 -0x3B 0xBa02c -0x3A 0x00420 //HG2 -0x3B 0xB3064 -0x3A 0x00458 //MG1 original 00448 -0x3B 0xAb270 -0x3A 0x00458 //MG2 original 00448 -0x3B 0xA2a70 -0x3A 0x00410 //LG0 -0x3B 0x9a872 -0x3A 0x00418 //LG1 -0x3B 0x92080 -0x3A 0x00410 //ULG -0x3B 0x8b082 -0x3A 0x00410 //ULG -0x3B 0x83082 - -//RX BandCap Setting // Shold set 0x3B, then 0x3A -0xEF 0x00800 -//LB -0x3B 0x00000 -0x3A 0x00003 -//MB -0x3B 0x40000 -0x3A 0x00002 -//HB -0x3B 0x80000 -0x3A 0x00002 - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A03B -0x34 0x49038 -0x34 0x48036 -0x34 0x47033 -0x34 0x46030 -0x34 0x4502D -0x34 0x44010 -0x34 0x4300D -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A03B -0x34 0x29038 -0x34 0x28036 -0x34 0x27033 -0x34 0x26030 -0x34 0x2502D -0x34 0x24010 -0x34 0x2300D -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A03B -0x34 0x09038 -0x34 0x08036 -0x34 0x07033 -0x34 0x06030 -0x34 0x0502D -0x34 0x04010 -0x34 0x0300D -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C5 -0x35 0x081C5 -0x35 0x101C5 -0x35 0x20174 -0x35 0x28174 -0x35 0x30174 -0x35 0x40185 -0x35 0x48185 -0x35 0x50185 -0xEF 0x00000 - -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x05B8B -0x36 0x0DB8B -0x36 0x15B8B -0x36 0x1DB8B -0x36 0x262DB -0x36 0x2E2DB -0x36 0x362DB -0x36 0x3E2DB -0x36 0x4553B -0x36 0x4D53B -0x36 0x5553B -0x36 0x5D53B -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002DC -0x3C 0x00524 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -0x08 0xFC400 -0xEF 0x00000 - - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00040 -0x58 0xE1F98 //LO leakage -//0x59 0x6A002 //IQGEN -0x1C 0x339D0 //S1 RC BW for 80M -//0x61 0xF4C43 //0xEFC67 //PA -//0x62 0x38F48 //0x29B45 //PA -//0x63 0x72117 //0x72337 //PAD -//0x64 0x1A4AC //0x1A92C //PAD -//0x65 0x931DE //0x931DE //PAD -//0x61 0xF4C43 -//0x62 0x38F48 -//0x63 0x72117 -//0x64 0x1A4AC -//0x65 0x931DE - - -0x61 0xEAC43 -0x62 0x38F47 -0x63 0x71157 -0x64 0x1C4AC -0x65 0x931D1 - -//APK -0x63 0x721D7 //LB -//0x63 0x72117 //MB -//0x63 0x72317 //HB - -//LOK -0x58 0xE1F98 //LB -//0X58 0XDA184 //MB -//0X58 0XDA184 //HB - -//IQK -//0x59 0x62082 //LB -//0x59 0x6A002 //MB -//0x59 0x69002 //HB - +//Release version: RLE442D.0702.2012 +//A MODE S0:5210 + +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +//0x1C 0x039d0 // Set max RX RCK offset + + + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 //HG1 +0x3B 0x37a58 //HG2 +0x3B 0x2a590 //MG1 +0x3B 0x27a50 //MG2 +0x3B 0x18248 //LG +0x3B 0x10240 //ULG +0x3B 0x08240 //ULG +0x3B 0x00240 //ULG + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0AD37 +0x34 0x09D34 +0x34 0x08D31 +0x34 0x07D2e +0x34 0x06D2b +0x34 0x05D28 +0x34 0x04Cab +0x34 0x03Ca8 +0x34 0x024ab +0x34 0x014a8 +0x34 0x000ab +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00040 // APK setting in debug mode +0x35 0x00123 +0x35 0x08123 +0x35 0x10123 +0x36 0x00085 +0x36 0x08085 +0x36 0x10085 +0x36 0x18085 +0xEF 0x00000 + +0x51 0x00C31 +0x52 0x01222 +0x53 0xFC10B //APK path B +0x54 0x0017E //LC tank (ch01~ch07), +//0x54 0x0013E //LC tank (ch08~ch13) + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//RX AGC 5GL +0x3A 0x00400 //HG1 +0x3B 0x3a02c +0x3A 0x00420 //HG2 +0x3B 0x33064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x2b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x22a70 +0x3A 0x00410 //LG0 +0x3B 0x1a872 +0x3A 0x00418 //LG1 +0x3B 0x12080 +0x3A 0x00410 //ULG +0x3B 0x0b082 +0x3A 0x00410 //ULG +0x3B 0x03082 +//RX AGC 5GM +0x3A 0x00400 //HG1 +0x3B 0x7a02c +0x3A 0x00420 //HG2 +0x3B 0x73064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0x6b270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0x62a70 +0x3A 0x00410 //LG0 +0x3B 0x5a872 +0x3A 0x00418 //LG1 +0x3B 0x52080 +0x3A 0x00410 //ULG +0x3B 0x4b082 +0x3A 0x00410 //ULG +0x3B 0x43082 +//RX AGC 5GH +0x3A 0x00400 //HG1 +0x3B 0xBa02c +0x3A 0x00420 //HG2 +0x3B 0xB3064 +0x3A 0x00458 //MG1 original 00448 +0x3B 0xAb270 +0x3A 0x00458 //MG2 original 00448 +0x3B 0xA2a70 +0x3A 0x00410 //LG0 +0x3B 0x9a872 +0x3A 0x00418 //LG1 +0x3B 0x92080 +0x3A 0x00410 //ULG +0x3B 0x8b082 +0x3A 0x00410 //ULG +0x3B 0x83082 + +//RX BandCap Setting // Shold set 0x3B, then 0x3A +0xEF 0x00800 +//LB +0x3B 0x00000 +0x3A 0x00003 +//MB +0x3B 0x40000 +0x3A 0x00002 +//HB +0x3B 0x80000 +0x3A 0x00002 + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A03B +0x34 0x49038 +0x34 0x48036 +0x34 0x47033 +0x34 0x46030 +0x34 0x4502D +0x34 0x44010 +0x34 0x4300D +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A03B +0x34 0x29038 +0x34 0x28036 +0x34 0x27033 +0x34 0x26030 +0x34 0x2502D +0x34 0x24010 +0x34 0x2300D +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A03B +0x34 0x09038 +0x34 0x08036 +0x34 0x07033 +0x34 0x06030 +0x34 0x0502D +0x34 0x04010 +0x34 0x0300D +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C5 +0x35 0x081C5 +0x35 0x101C5 +0x35 0x20174 +0x35 0x28174 +0x35 0x30174 +0x35 0x40185 +0x35 0x48185 +0x35 0x50185 +0xEF 0x00000 + +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x05B8B +0x36 0x0DB8B +0x36 0x15B8B +0x36 0x1DB8B +0x36 0x262DB +0x36 0x2E2DB +0x36 0x362DB +0x36 0x3E2DB +0x36 0x4553B +0x36 0x4D53B +0x36 0x5553B +0x36 0x5D53B +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002DC +0x3C 0x00524 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +0x08 0xFC400 +0xEF 0x00000 + + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00040 +0x58 0xE1F98 //LO leakage +//0x59 0x6A002 //IQGEN +0x1C 0x339D0 //S1 RC BW for 80M +//0x61 0xF4C43 //0xEFC67 //PA +//0x62 0x38F48 //0x29B45 //PA +//0x63 0x72117 //0x72337 //PAD +//0x64 0x1A4AC //0x1A92C //PAD +//0x65 0x931DE //0x931DE //PAD +//0x61 0xF4C43 +//0x62 0x38F48 +//0x63 0x72117 +//0x64 0x1A4AC +//0x65 0x931DE + + +0x61 0xEAC43 +0x62 0x38F47 +0x63 0x71157 +0x64 0x1C4AC +0x65 0x931D1 + +//APK +0x63 0x721D7 //LB +//0x63 0x72117 //MB +//0x63 0x72317 //HB + +//LOK +0x58 0xE1F98 //LB +//0X58 0XDA184 //MB +//0X58 0XDA184 //HB + +//IQK +//0x59 0x62082 //LB +//0x59 0x6A002 //MB +//0x59 0x69002 //HB + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_default.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_default.txt index b2ca5f7c05f..56f12b08dee 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_default.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_default.txt @@ -1,250 +1,250 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x87180 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK path B -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S1 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DF2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x24DE3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0AFF7 -0x34 0x09DF7 -0x34 0x08DF4 -0x34 0x07DF1 -0x34 0x06DEE -0x34 0x05DEB -0x34 0x04DE8 -0x34 0x038CC -0x34 0x028C9 -0x34 0x018C6 -0x34 0x008C3 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00188 -0x35 0x08147 -0x35 0x10147 -0x35 0x201D7 -0x35 0x281D7 -0x35 0x301D7 -0x35 0x401D8 -0x35 0x481D8 -0x35 0x501D8 -0xEF 0x00000 -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x84EB4 // LB 80M -0x36 0x8CC35 // LB 40M -0x36 0x94C35 // LB NA -0x36 0x9CC35 // LB 20M -0x36 0xA4C35 // MB 80M -0x36 0xACC35 // MB 40M -0x36 0xB4C35 // MB NA -0x36 0xBCC35 // MB 20M -0x36 0xC4C34 // HB 80M -0x36 0xCCC35 // HB 40M -0x36 0xD4C35 // HB NA -0x36 0xDCC35 // HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002A8 -0x3C 0x005A2 -0x3C 0x00880 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xFC400 -//0xEF 0x00000 - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00080 - - - -0x61 0xE5D53 -0x62 0x38FCD -0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 -0x64 0x196AC -0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 - - -//LOK -0x08 0x08400 //write 5G LOK table default value - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x87180 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK path B +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S1 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DF2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x24DE3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0AFF7 +0x34 0x09DF7 +0x34 0x08DF4 +0x34 0x07DF1 +0x34 0x06DEE +0x34 0x05DEB +0x34 0x04DE8 +0x34 0x038CC +0x34 0x028C9 +0x34 0x018C6 +0x34 0x008C3 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00188 +0x35 0x08147 +0x35 0x10147 +0x35 0x201D7 +0x35 0x281D7 +0x35 0x301D7 +0x35 0x401D8 +0x35 0x481D8 +0x35 0x501D8 +0xEF 0x00000 +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x84EB4 // LB 80M +0x36 0x8CC35 // LB 40M +0x36 0x94C35 // LB NA +0x36 0x9CC35 // LB 20M +0x36 0xA4C35 // MB 80M +0x36 0xACC35 // MB 40M +0x36 0xB4C35 // MB NA +0x36 0xBCC35 // MB 20M +0x36 0xC4C34 // HB 80M +0x36 0xCCC35 // HB 40M +0x36 0xD4C35 // HB NA +0x36 0xDCC35 // HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002A8 +0x3C 0x005A2 +0x3C 0x00880 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xFC400 +//0xEF 0x00000 + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00080 + + + +0x61 0xE5D53 +0x62 0x38FCD +0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 +0x64 0x196AC +0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 + + +//LOK +0x08 0x08400 //write 5G LOK table default value + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extlna.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extlna.txt index 56886909eba..c89eb3638cd 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extlna.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extlna.txt @@ -1,250 +1,250 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK path B -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S1 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4ADF5 -0x34 0x49DF2 -0x34 0x48DEF -0x34 0x47DEC -0x34 0x46DE9 -0x34 0x45DE6 -0x34 0x44DE3 -0x34 0x438C8 -0x34 0x428C5 -0x34 0x418C2 -0x34 0x408C0 -//TX AGC 5GM -0x34 0x2ADF5 -0x34 0x29DF2 -0x34 0x28DEF -0x34 0x27DEC -0x34 0x26DE9 -0x34 0x25DE6 -0x34 0x24DE3 -0x34 0x238C8 -0x34 0x228C5 -0x34 0x218C2 -0x34 0x208C0 -//TX AGC 5GL -0x34 0x0AFF7 -0x34 0x09DF7 -0x34 0x08DF4 -0x34 0x07DF1 -0x34 0x06DEE -0x34 0x05DEB -0x34 0x04DE8 -0x34 0x038CC -0x34 0x028C9 -0x34 0x018C6 -0x34 0x008C3 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x00188 -0x35 0x08147 -0x35 0x10147 -0x35 0x201D7 -0x35 0x281D7 -0x35 0x301D7 -0x35 0x401D8 -0x35 0x481D8 -0x35 0x501D8 -0xEF 0x00000 -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x84EB4 // LB 80M -0x36 0x8CC35 // LB 40M -0x36 0x94C35 // LB NA -0x36 0x9CC35 // LB 20M -0x36 0xA4C35 // MB 80M -0x36 0xACC35 // MB 40M -0x36 0xB4C35 // MB NA -0x36 0xBCC35 // MB 20M -0x36 0xC4C34 // HB 80M -0x36 0xCCC35 // HB 40M -0x36 0xD4C35 // HB NA -0x36 0xDCC35 // HB 20M -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002A8 -0x3C 0x005A2 -0x3C 0x00880 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xFC400 -//0xEF 0x00000 - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00080 - - - -0x61 0xE5D53 -0x62 0x38FCD -0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 -0x64 0x196AC -0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 - - -//LOK -0x08 0x08400 //write 5G LOK table default value - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK path B +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S1 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4ADF5 +0x34 0x49DF2 +0x34 0x48DEF +0x34 0x47DEC +0x34 0x46DE9 +0x34 0x45DE6 +0x34 0x44DE3 +0x34 0x438C8 +0x34 0x428C5 +0x34 0x418C2 +0x34 0x408C0 +//TX AGC 5GM +0x34 0x2ADF5 +0x34 0x29DF2 +0x34 0x28DEF +0x34 0x27DEC +0x34 0x26DE9 +0x34 0x25DE6 +0x34 0x24DE3 +0x34 0x238C8 +0x34 0x228C5 +0x34 0x218C2 +0x34 0x208C0 +//TX AGC 5GL +0x34 0x0AFF7 +0x34 0x09DF7 +0x34 0x08DF4 +0x34 0x07DF1 +0x34 0x06DEE +0x34 0x05DEB +0x34 0x04DE8 +0x34 0x038CC +0x34 0x028C9 +0x34 0x018C6 +0x34 0x008C3 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x00188 +0x35 0x08147 +0x35 0x10147 +0x35 0x201D7 +0x35 0x281D7 +0x35 0x301D7 +0x35 0x401D8 +0x35 0x481D8 +0x35 0x501D8 +0xEF 0x00000 +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x84EB4 // LB 80M +0x36 0x8CC35 // LB 40M +0x36 0x94C35 // LB NA +0x36 0x9CC35 // LB 20M +0x36 0xA4C35 // MB 80M +0x36 0xACC35 // MB 40M +0x36 0xB4C35 // MB NA +0x36 0xBCC35 // MB 20M +0x36 0xC4C34 // HB 80M +0x36 0xCCC35 // HB 40M +0x36 0xD4C35 // HB NA +0x36 0xDCC35 // HB 20M +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002A8 +0x3C 0x005A2 +0x3C 0x00880 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xFC400 +//0xEF 0x00000 + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00080 + + + +0x61 0xE5D53 +0x62 0x38FCD +0x63 0x114EB //improved OFDM EVM with IPA gate bias = 00 +0x64 0x196AC +0x65 0x911D7 //BBSW=0dB with per_PAD gain=5 BBSW=-3dB with per_PAD gain=7 + + +//LOK +0x08 0x08400 //write 5G LOK table default value + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extpa.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extpa.txt index 27b9e51503f..c3b5f7279d8 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extpa.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_extpa.txt @@ -1,250 +1,250 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x87180 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK path B -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S1 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C5 -0x35 0x081C5 -0x35 0x101C5 -0x35 0x20174 -0x35 0x28174 -0x35 0x30174 -0x35 0x40185 -0x35 0x48185 -0x35 0x50185 -0xEF 0x00000 -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x05B8B -0x36 0x0DB8B -0x36 0x15B8B -0x36 0x1DB8B -0x36 0x262DB -0x36 0x2E2DB -0x36 0x362DB -0x36 0x3E2DB -0x36 0x4553B -0x36 0x4D53B -0x36 0x5553B -0x36 0x5D53B -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002DC -0x3C 0x00524 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xFC400 -//0xEF 0x00000 - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00080 - - - -0x61 0xEAC43 -0x62 0x38F47 -0x63 0x31157 -0x64 0x1C4AC -0x65 0x931D1 - - -//LOK -0x08 0x08400 //write 5G LOK table default value - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x87180 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK path B +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S1 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C5 +0x35 0x081C5 +0x35 0x101C5 +0x35 0x20174 +0x35 0x28174 +0x35 0x30174 +0x35 0x40185 +0x35 0x48185 +0x35 0x50185 +0xEF 0x00000 +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x05B8B +0x36 0x0DB8B +0x36 0x15B8B +0x36 0x1DB8B +0x36 0x262DB +0x36 0x2E2DB +0x36 0x362DB +0x36 0x3E2DB +0x36 0x4553B +0x36 0x4D53B +0x36 0x5553B +0x36 0x5D53B +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002DC +0x3C 0x00524 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xFC400 +//0xEF 0x00000 + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00080 + + + +0x61 0xEAC43 +0x62 0x38F47 +0x63 0x31157 +0x64 0x1C4AC +0x65 0x931D1 + + +//LOK +0x08 0x08400 //write 5G LOK table default value + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_hp.txt index 49806bf6cab..a31206e5527 100644 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_hp.txt @@ -1,250 +1,250 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK path B -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S1 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B2 -0x34 0x490AF -0x34 0x48070 -0x34 0x4706D -0x34 0x46050 -0x34 0x4504D -0x34 0x4404A -0x34 0x43047 -0x34 0x4200A -0x34 0x41007 -0x34 0x40004 -//TX AGC 5GM -0x34 0x2A0B2 -0x34 0x290AF -0x34 0x28070 -0x34 0x2706D -0x34 0x26050 -0x34 0x2504D -0x34 0x2404A -0x34 0x23047 -0x34 0x2200A -0x34 0x21007 -0x34 0x20004 -//TX AGC 5GL -0x34 0x0A0B2 -0x34 0x090AF -0x34 0x08070 -0x34 0x0706D -0x34 0x06050 -0x34 0x0504D -0x34 0x0404A -0x34 0x03047 -0x34 0x0200A -0x34 0x01007 -0x34 0x00004 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C5 -0x35 0x081C5 -0x35 0x101C5 -0x35 0x20174 -0x35 0x28174 -0x35 0x30174 -0x35 0x40185 -0x35 0x48185 -0x35 0x50185 -0xEF 0x00000 -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x05B8B -0x36 0x0DB8B -0x36 0x15B8B -0x36 0x1DB8B -0x36 0x262DB -0x36 0x2E2DB -0x36 0x362DB -0x36 0x3E2DB -0x36 0x4553B -0x36 0x4D53B -0x36 0x5553B -0x36 0x5D53B -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002DC -0x3C 0x00524 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xFC400 -//0xEF 0x00000 - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00080 - - - -0x61 0xEAC43 -0x62 0x38F47 -0x63 0x31157 -0x64 0x1C4AC -0x65 0x931D1 - - -//LOK -0x08 0x08400 //write 5G LOK table default value - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK path B +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S1 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B2 +0x34 0x490AF +0x34 0x48070 +0x34 0x4706D +0x34 0x46050 +0x34 0x4504D +0x34 0x4404A +0x34 0x43047 +0x34 0x4200A +0x34 0x41007 +0x34 0x40004 +//TX AGC 5GM +0x34 0x2A0B2 +0x34 0x290AF +0x34 0x28070 +0x34 0x2706D +0x34 0x26050 +0x34 0x2504D +0x34 0x2404A +0x34 0x23047 +0x34 0x2200A +0x34 0x21007 +0x34 0x20004 +//TX AGC 5GL +0x34 0x0A0B2 +0x34 0x090AF +0x34 0x08070 +0x34 0x0706D +0x34 0x06050 +0x34 0x0504D +0x34 0x0404A +0x34 0x03047 +0x34 0x0200A +0x34 0x01007 +0x34 0x00004 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C5 +0x35 0x081C5 +0x35 0x101C5 +0x35 0x20174 +0x35 0x28174 +0x35 0x30174 +0x35 0x40185 +0x35 0x48185 +0x35 0x50185 +0xEF 0x00000 +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x05B8B +0x36 0x0DB8B +0x36 0x15B8B +0x36 0x1DB8B +0x36 0x262DB +0x36 0x2E2DB +0x36 0x362DB +0x36 0x3E2DB +0x36 0x4553B +0x36 0x4D53B +0x36 0x5553B +0x36 0x5D53B +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002DC +0x3C 0x00524 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xFC400 +//0xEF 0x00000 + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00080 + + + +0x61 0xEAC43 +0x62 0x38F47 +0x63 0x31157 +0x64 0x1C4AC +0x65 0x931D1 + + +//LOK +0x08 0x08400 //write 5G LOK table default value + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_ultra_hp.txt b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_ultra_hp.txt old mode 100755 new mode 100644 index 6fe331e4bd7..a5dfc6a16a6 --- a/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_ultra_hp.txt +++ b/package/kernel/rtl8192cd/data_8812/RadioB_8812_n_ultra_hp.txt @@ -1,250 +1,250 @@ -//RL6286_MAC_PHY_Parameter_v041_20131127 -//A MODE S0:5210 -0x56 0x51CF2 //R2T turbo_EN[18]=1 -0x66 0x40000 //TRIQ bus floating -0x89 0x00080 // for RX LNA setting -0x86 0x14B38 -0x8B 0x80180 - -// G mode TRx Setting -//RX_G AGC Table -0x18 0x00006 -0xEF 0x02000 -0x3B 0x38a58 // LNA=3b111 -0x3B 0x37a58 // LNA=3b110 -0x3B 0x2a590 // LNA=3b101 -0x3B 0x27a50 // LNA=3b100 -0x3B 0x18248 // LNA=3b011 -0x3B 0x10240 // LNA=3b010 -0x3B 0x08240 // LNA=3b001 - -//TX_G GainTable -0xEF 0x00100 -0x34 0x0ADF4 -0x34 0x09DF1 -0x34 0x08DEE -0x34 0x07DEB -0x34 0x06DE8 -0x34 0x05CEC -0x34 0x04CE9 -0x34 0x034EA -0x34 0x024E7 -0x34 0x0146B -0x34 0x0006D -0xEF 0x00000 - - -//2G PA bias setting -0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table -0xDF 0x00080 // APK setting in debug mode -0x35 0x00192 -0x35 0x08192 -0x35 0x10192 -0x36 0x00024 -0x36 0x08024 -0x36 0x10024 -0x36 0x18024 -0xEF 0x00000 - -0x51 0x00C21 -0x52 0x006D9 -0x53 0xFC649 //APK path B -0x54 0x0017E //LC tank (ch01~ch07) -//0x54 0x0013E //LC tank (ch08~ch13) - -//Table_LOK_S1 -0xEF 0x00002 - -//LOK -0x08 0x08400 //write LOK table default value - -// A mode TRx Setting - -//RX_A AGC Table -0x18 0x1712a -0xEF 0x01000 -//LB -0x3A 0x00080 //HG1-1 -0x3B 0x3A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x3202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x2B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x23064 -//0x3C 0x10000 -0x3A 0x000d8 // MG1-2 -0x3B 0x23070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x1B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x12085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x0A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x02080 -0x3C 0x10000 -//MB -0x3A 0x00080 //HG1-1 -0x3B 0x7A02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0x7202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0x6B064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0x63064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0x63070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x5B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x52085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x4A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x42080 -0x3C 0x10000 -//HB -0x3A 0x00080 //HG1-1 -0x3B 0xBA02C -0x3C 0x04000 -0x3A 0x00400 //HG1 -0x3B 0xB202C -0x3C 0x10000 -0x3A 0x000A0 // HG2-1 -0x3B 0xAB064 -0x3C 0x04000 -//0x3A 0x00420 //HG2 -//0x3B 0xA3064 -//0x3C 0x10000 -0x3A 0x000d8 //MG1-2 -0x3B 0xA3070 -0x3C 0x04000 -0x3A 0x00468 //MG1-3 -0x3B 0x9B870 -0x3C 0x10000 -0x3A 0x00098 //LG0-3 -0x3B 0x92085 -0x3C 0xE4000 -0x3A 0x00418 //LG0-2 -0x3B 0x8A080 -0x3C 0xf0000 -0x3A 0x00418 //LG1 -0x3B 0x82080 -0x3C 0x10000 - - -// Table_5G_TXAGC_S1 -0xEF 0x01100 -//TX AGC 5GH -0x34 0x4A0B1 -0x34 0x490AE -0x34 0x4806F -0x34 0x4706C -0x34 0x4604C -0x34 0x45049 -0x34 0x44046 -0x34 0x43043 -0x34 0x42006 -0x34 0x41003 -0x34 0x40000 -//TX AGC 5GM -0x34 0x2A0B3 -0x34 0x290B0 -0x34 0x28071 -0x34 0x2706E -0x34 0x2604E -0x34 0x2504B -0x34 0x24048 -0x34 0x23045 -0x34 0x22008 -0x34 0x21005 -0x34 0x20002 -//TX AGC 5GL -0x34 0x0A0B3 -0x34 0x090B0 -0x34 0x08070 -0x34 0x0706D -0x34 0x0604D -0x34 0x0504A -0x34 0x04047 -0x34 0x03044 -0x34 0x02007 -0x34 0x01004 -0x34 0x00001 -0xEF 0x00000 - -//Table_5G_Bias_I_S1 -0x18 0x1712A -0xEF 0x00040 -0x35 0x001C5 -0x35 0x081C5 -0x35 0x101C5 -0x35 0x20174 -0x35 0x28174 -0x35 0x30174 -0x35 0x40185 -0x35 0x48185 -0x35 0x50185 -0xEF 0x00000 -//Table_5G_Bias_II_S1 -0x18 0x1712A -0xEF 0x00010 -0x36 0x05B8B -0x36 0x0DB8B -0x36 0x15B8B -0x36 0x1DB8B -0x36 0x262DB -0x36 0x2E2DB -0x36 0x362DB -0x36 0x3E2DB -0x36 0x4553B -0x36 0x4D53B -0x36 0x5553B -0x36 0x5D53B -0xEF 0x00000 - -//Table_5G_Tank_S1 -0xEF 0x00008 -0x3C 0x002DC -0x3C 0x00524 -0x3C 0x00902 -0xEF 0x00000 - -//Table_LOK_S0 -0x18 0x1712A -0xEF 0x00002 -//0x08 0xFC400 -//0xEF 0x00000 - -//0x1F 0x40200 //RC BW for 80M -0xDF 0x00080 - - - -0x61 0xEAC43 -0x62 0x38F47 -0x63 0x31157 -0x64 0x1C4AC -0x65 0x931D2 - - -//LOK -0x08 0x08400 //write 5G LOK table default value - +//RL6286_MAC_PHY_Parameter_v041_20131127 +//A MODE S0:5210 +0x56 0x51CF2 //R2T turbo_EN[18]=1 +0x66 0x40000 //TRIQ bus floating +0x89 0x00080 // for RX LNA setting +0x86 0x14B38 +0x8B 0x80180 + +// G mode TRx Setting +//RX_G AGC Table +0x18 0x00006 +0xEF 0x02000 +0x3B 0x38a58 // LNA=3b111 +0x3B 0x37a58 // LNA=3b110 +0x3B 0x2a590 // LNA=3b101 +0x3B 0x27a50 // LNA=3b100 +0x3B 0x18248 // LNA=3b011 +0x3B 0x10240 // LNA=3b010 +0x3B 0x08240 // LNA=3b001 + +//TX_G GainTable +0xEF 0x00100 +0x34 0x0ADF4 +0x34 0x09DF1 +0x34 0x08DEE +0x34 0x07DEB +0x34 0x06DE8 +0x34 0x05CEC +0x34 0x04CE9 +0x34 0x034EA +0x34 0x024E7 +0x34 0x0146B +0x34 0x0006D +0xEF 0x00000 + + +//2G PA bias setting +0xEF 0x020A2 // Wenable biasI/biasII/gain table/LO table +0xDF 0x00080 // APK setting in debug mode +0x35 0x00192 +0x35 0x08192 +0x35 0x10192 +0x36 0x00024 +0x36 0x08024 +0x36 0x10024 +0x36 0x18024 +0xEF 0x00000 + +0x51 0x00C21 +0x52 0x006D9 +0x53 0xFC649 //APK path B +0x54 0x0017E //LC tank (ch01~ch07) +//0x54 0x0013E //LC tank (ch08~ch13) + +//Table_LOK_S1 +0xEF 0x00002 + +//LOK +0x08 0x08400 //write LOK table default value + +// A mode TRx Setting + +//RX_A AGC Table +0x18 0x1712a +0xEF 0x01000 +//LB +0x3A 0x00080 //HG1-1 +0x3B 0x3A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x3202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x2B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x23064 +//0x3C 0x10000 +0x3A 0x000d8 // MG1-2 +0x3B 0x23070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x1B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x12085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x0A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x02080 +0x3C 0x10000 +//MB +0x3A 0x00080 //HG1-1 +0x3B 0x7A02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0x7202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0x6B064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0x63064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0x63070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x5B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x52085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x4A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x42080 +0x3C 0x10000 +//HB +0x3A 0x00080 //HG1-1 +0x3B 0xBA02C +0x3C 0x04000 +0x3A 0x00400 //HG1 +0x3B 0xB202C +0x3C 0x10000 +0x3A 0x000A0 // HG2-1 +0x3B 0xAB064 +0x3C 0x04000 +//0x3A 0x00420 //HG2 +//0x3B 0xA3064 +//0x3C 0x10000 +0x3A 0x000d8 //MG1-2 +0x3B 0xA3070 +0x3C 0x04000 +0x3A 0x00468 //MG1-3 +0x3B 0x9B870 +0x3C 0x10000 +0x3A 0x00098 //LG0-3 +0x3B 0x92085 +0x3C 0xE4000 +0x3A 0x00418 //LG0-2 +0x3B 0x8A080 +0x3C 0xf0000 +0x3A 0x00418 //LG1 +0x3B 0x82080 +0x3C 0x10000 + + +// Table_5G_TXAGC_S1 +0xEF 0x01100 +//TX AGC 5GH +0x34 0x4A0B1 +0x34 0x490AE +0x34 0x4806F +0x34 0x4706C +0x34 0x4604C +0x34 0x45049 +0x34 0x44046 +0x34 0x43043 +0x34 0x42006 +0x34 0x41003 +0x34 0x40000 +//TX AGC 5GM +0x34 0x2A0B3 +0x34 0x290B0 +0x34 0x28071 +0x34 0x2706E +0x34 0x2604E +0x34 0x2504B +0x34 0x24048 +0x34 0x23045 +0x34 0x22008 +0x34 0x21005 +0x34 0x20002 +//TX AGC 5GL +0x34 0x0A0B3 +0x34 0x090B0 +0x34 0x08070 +0x34 0x0706D +0x34 0x0604D +0x34 0x0504A +0x34 0x04047 +0x34 0x03044 +0x34 0x02007 +0x34 0x01004 +0x34 0x00001 +0xEF 0x00000 + +//Table_5G_Bias_I_S1 +0x18 0x1712A +0xEF 0x00040 +0x35 0x001C5 +0x35 0x081C5 +0x35 0x101C5 +0x35 0x20174 +0x35 0x28174 +0x35 0x30174 +0x35 0x40185 +0x35 0x48185 +0x35 0x50185 +0xEF 0x00000 +//Table_5G_Bias_II_S1 +0x18 0x1712A +0xEF 0x00010 +0x36 0x05B8B +0x36 0x0DB8B +0x36 0x15B8B +0x36 0x1DB8B +0x36 0x262DB +0x36 0x2E2DB +0x36 0x362DB +0x36 0x3E2DB +0x36 0x4553B +0x36 0x4D53B +0x36 0x5553B +0x36 0x5D53B +0xEF 0x00000 + +//Table_5G_Tank_S1 +0xEF 0x00008 +0x3C 0x002DC +0x3C 0x00524 +0x3C 0x00902 +0xEF 0x00000 + +//Table_LOK_S0 +0x18 0x1712A +0xEF 0x00002 +//0x08 0xFC400 +//0xEF 0x00000 + +//0x1F 0x40200 //RC BW for 80M +0xDF 0x00080 + + + +0x61 0xEAC43 +0x62 0x38F47 +0x63 0x31157 +0x64 0x1C4AC +0x65 0x931D2 + + +//LOK +0x08 0x08400 //write 5G LOK table default value + 0xffff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_8812/TXPWR_LMT_8812_new.txt b/package/kernel/rtl8192cd/data_8812/TXPWR_LMT_8812_new.txt index 070f9c0b3dc..0ba452c136a 100644 --- a/package/kernel/rtl8192cd/data_8812/TXPWR_LMT_8812_new.txt +++ b/package/kernel/rtl8192cd/data_8812/TXPWR_LMT_8812_new.txt @@ -1,327 +1,327 @@ -//RL6286_MAC_PHY_Parameter_v024_20130125 -//RL6286_MAC_PHY_Parameter_v024_20130125 -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 17 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH104 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH104 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH104 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 18 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 18 16 NA -CH159 18 16 NA -## END -// -//Table 11: =========================================== -// -## 5G;, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 18 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +//RL6286_MAC_PHY_Parameter_v024_20130125 +//RL6286_MAC_PHY_Parameter_v024_20130125 +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 17 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH104 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH104 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH104 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 18 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 18 16 NA +CH159 18 16 NA +## END +// +//Table 11: =========================================== +// +## 5G;, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 18 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/data_8812/rtl8812fw.bin b/package/kernel/rtl8192cd/data_8812/rtl8812fw.bin old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E.txt b/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E.txt index 49ae5c6ccc3..e21e30b0394 100644 --- a/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E.txt +++ b/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E.txt @@ -1,144 +1,144 @@ -//========================= -// PHY_related MAC register by channel, Wilson 091016 -// Related from willis 090406 PHY_REG_PG.txt for 92S -//========================= -//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// For Ant A -0xe00 0xffffffff 0x0e0e1010 // base on 0x30 // for 18M,12M,09M,06M -0xe04 0xffffffff 0x0204080a // base on 0x30 // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x06 // base on 0x30 // for CCK 1M -0x86c 0xffffff00 0x000204 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB -0xe10 0xffffffff 0x0e101414 // base on 0x30 // for MCS=03,02,01,00 -0xe14 0xffffffff 0x0204060a // base on 0x30 // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M -0x838 0xffffff00 0x00000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 -//========================= -//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 -//========================= -//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M -0x83c 0xffffffff 0x06060606 // base on 0x32 // for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 //for MCS=15,14,13,12 -//========================= -//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 -//========================= -// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -//========================= -// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -0xff //end of file +//========================= +// PHY_related MAC register by channel, Wilson 091016 +// Related from willis 090406 PHY_REG_PG.txt for 92S +//========================= +//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// For Ant A +0xe00 0xffffffff 0x0e0e1010 // base on 0x30 // for 18M,12M,09M,06M +0xe04 0xffffffff 0x0204080a // base on 0x30 // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x06 // base on 0x30 // for CCK 1M +0x86c 0xffffff00 0x000204 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB +0xe10 0xffffffff 0x0e101414 // base on 0x30 // for MCS=03,02,01,00 +0xe14 0xffffffff 0x0204060a // base on 0x30 // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M +0x838 0xffffff00 0x00000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 +//========================= +//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 +//========================= +//Offset talbe_2 for Mode EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M +0x83c 0xffffffff 0x06060606 // base on 0x32 // for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 //for MCS=15,14,13,12 +//========================= +//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x30 // for CCK 11M, 5.5M, 2M use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 // for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 // for CCK 5.5M, 2M, 1M use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x32 // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 // for MCS=15,14,13,12 +//========================= +// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +//========================= +// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +0xff //end of file diff --git a/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E_new.txt b/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E_new.txt index e45e94c8ac3..8457fe1d2fc 100644 --- a/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E_new.txt +++ b/package/kernel/rtl8192cd/data_88e/PHY_REG_PG_88E_new.txt @@ -1,21 +1,21 @@ -//RL6286_MAC_PHY_Parameter_v024_20130125 -#Exact -0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} -0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} -0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} -0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} -0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} -0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} -0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} -0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} -0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} -0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} - -0xffff 0xffff +//RL6286_MAC_PHY_Parameter_v024_20130125 +#Exact +0xe00 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0xe04 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0xe08 0 0 20 0 // TXAGC codeword (H-byte->L-byte)={NA NA 1M NA} +0x86c 17 18 19 0 // TXAGC codeword (H-byte->L-byte)={11M 5.5M 2M NA} +0xe10 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0xe14 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0xe18 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0xe1c 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0x830 21 21 22 22 // TXAGC codeword (H-byte->L-byte)={18M 12M 9M 6M} +0x834 15 16 18 19 // TXAGC codeword (H-byte->L-byte)={54M 48M 36M 24M} +0x838 18 19 20 0 // TXAGC codeword (H-byte->L-byte)={5.5M 2M 1M NA} +0x86c 0 0 0 17 // TXAGC codeword (H-byte->L-byte)={NA NA NA NA 11M} +0x83c 20 21 22 22 // TXAGC codeword (H-byte->L-byte)=HT_{MCS3 MCS2 MCS1 MCS0} +0x848 14 15 16 18 // TXAGC codeword (H-byte->L-byte)=HT_{MCS7 MCS6 MCS5 MCS4} +0x84c 19 20 21 21 // TXAGC codeword (H-byte->L-byte)=HT_{MCS11 MCS10 MCS9 MCS8} +0x868 13 14 15 17 // TXAGC codeword (H-byte->L-byte)=HT_{MCS15 MCS14 MCS13 MCS12} + +0xffff 0xffff diff --git a/package/kernel/rtl8192cd/data_88e/TXPWR_LMT_88E_new.txt b/package/kernel/rtl8192cd/data_88e/TXPWR_LMT_88E_new.txt index cd9e6d61fab..5a716b8b466 100644 --- a/package/kernel/rtl8192cd/data_88e/TXPWR_LMT_88E_new.txt +++ b/package/kernel/rtl8192cd/data_88e/TXPWR_LMT_88E_new.txt @@ -1,326 +1,326 @@ -// Tx Power Limit Table -// Format: -// -// Note: The order of the tables MUST match the definition in WLAN driver. -// -// Power Limit Table Parameter Definition -// Band: 2.4G/5G -// Bandwidth: 20/40/80/160 MHZ -// RF Path: 1/2/3/4 Transmit RF -// Rate Section: CCK/OFDM/HT/VHT -// Regulation: FCC/ETSI/MKK -// -// Description: -// 1. IF in 1T test -// 2. power is real dBm. -// 3. // is for comment. -// -// NA is non-release channle. -// -// -//Table 1: =========================================== -// -## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) -## START -## #3# FCC ETSI MKK -CH01 18 16 16 -CH02 18 16 16 -CH03 18 16 16 -CH04 18 16 16 -CH05 18 16 16 -CH06 18 16 16 -CH07 18 16 16 -CH08 18 16 16 -CH09 18 16 16 -CH10 18 16 16 -CH11 18 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA 16 -## END -// -//Table 2: =========================================== -// -## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 3: =========================================== -// -## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 16 16 16 -CH02 17 16 16 -CH03 17 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 4: =========================================== -// -## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 15 16 16 -CH02 16 16 16 -CH03 16 16 16 -CH04 16 16 16 -CH05 16 16 16 -CH06 16 16 16 -CH07 16 16 16 -CH08 16 16 16 -CH09 16 16 16 -CH10 16 16 16 -CH11 15 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 5: =========================================== -// -## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 16 16 16 -CH04 17 16 16 -CH05 17 16 16 -CH06 17 16 16 -CH07 17 16 16 -CH08 17 16 16 -CH09 17 16 16 -CH10 17 16 16 -CH11 16 16 16 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 6: =========================================== -// -## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -CH01 NA NA NA -CH02 NA NA NA -CH03 15 15 15 -CH04 17 15 15 -CH05 17 15 15 -CH06 17 15 15 -CH07 17 15 15 -CH08 17 15 15 -CH09 17 15 15 -CH10 17 15 15 -CH11 15 15 15 -CH12 NA 16 16 -CH13 NA 16 16 -CH14 NA NA NA -## END -// -//Table 7: =========================================== -// -## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 8: ====================================== -// -## 5G, 20M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 15 16 16 -CH40 15 16 16 -CH44 15 16 16 -CH48 15 16 16 -//5G Band 2 -CH52 18 16 16 -CH56 17 16 16 -CH60 16 16 16 -CH64 14 16 16 -//5G Band 3 -CH100 15 16 16 -CH114 15 16 16 -CH108 16 16 16 -CH112 17 16 16 -CH116 17 16 16 -CH120 18 16 16 -CH124 17 16 16 -CH128 16 16 16 -CH132 15 16 16 -CH136 15 16 16 -CH140 14 16 16 -//5G Band 4 -CH149 18 16 NA -CH153 18 16 NA -CH157 18 16 NA -CH161 18 16 NA -CH165 18 16 NA -## END -// -//Table 9: =========================================== -// -## 5G, 20M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH36 14 15 15 -CH40 14 15 15 -CH44 14 15 15 -CH48 14 15 15 -//5G Band 2 -CH52 17 15 15 -CH56 16 15 15 -CH60 15 15 15 -CH64 13 15 15 -//5G Band 3 -CH100 14 15 15 -CH114 14 15 15 -CH108 15 15 15 -CH112 16 15 15 -CH116 16 15 15 -CH120 17 15 15 -CH124 16 15 15 -CH128 15 15 15 -CH132 14 15 15 -CH136 14 15 15 -CH140 13 15 15 -//5G Band 4 -CH149 17 15 NA -CH153 17 15 NA -CH157 17 15 NA -CH161 17 15 NA -CH165 17 15 NA -## END -// -//Table 10: =========================================== -// -## 5G, 40M, 1T, HT, //(MCS0~MCS7) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 15 16 16 -CH46 15 16 16 -//5G Band 2 -CH54 16 16 16 -CH62 16 16 16 -//5G Band 3 -CH102 14 16 16 -CH110 16 16 16 -CH118 18 16 16 -CH126 17 16 16 -CH134 16 16 16 -//5G Band 4 -CH151 18 16 NA -CH159 18 16 NA -## END -// -//Table 11: =========================================== -// -## 5G;, 40M, 2T, HT, //(MCS8~MCS15) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH38 14 15 15 -CH46 14 15 15 -//5G Band 2 -CH54 15 15 15 -CH62 15 15 15 -//5G Band 3 -CH102 13 15 15 -CH110 15 15 15 -CH118 17 15 15 -CH126 16 15 15 -CH134 15 15 15 -//5G Band 4 -CH151 17 15 NA -CH159 17 15 NA -## END -// -//Table 12: =========================================== -// -## 5G, 80M, 1T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 15 16 16 -//5G Band 2 -CH58 14 16 16 -//5G Band 3 -CH106 15 16 16 -CH122 17 16 16 -//5G Band 4 -CH155 18 16 NA -## END -// -//Table 13: =========================================== -// -## 5G, 80M, 2T, VHT, //(MCS0~MCS9) -## START -## #3# FCC ETSI MKK -//5G Band 1 -CH42 14 15 15 -//5G Band 2 -CH58 13 15 15 -//5G Band 3 -CH106 14 15 15 -CH122 16 15 15 -//5G Band 4 -CH155 17 15 NA -## END +// Tx Power Limit Table +// Format: +// +// Note: The order of the tables MUST match the definition in WLAN driver. +// +// Power Limit Table Parameter Definition +// Band: 2.4G/5G +// Bandwidth: 20/40/80/160 MHZ +// RF Path: 1/2/3/4 Transmit RF +// Rate Section: CCK/OFDM/HT/VHT +// Regulation: FCC/ETSI/MKK +// +// Description: +// 1. IF in 1T test +// 2. power is real dBm. +// 3. // is for comment. +// +// NA is non-release channle. +// +// +//Table 1: =========================================== +// +## 2.4G, 20M, 1T, CCK, //(1M;2M;5.5M;11M) +## START +## #3# FCC ETSI MKK +CH01 18 16 16 +CH02 18 16 16 +CH03 18 16 16 +CH04 18 16 16 +CH05 18 16 16 +CH06 18 16 16 +CH07 18 16 16 +CH08 18 16 16 +CH09 18 16 16 +CH10 18 16 16 +CH11 18 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA 16 +## END +// +//Table 2: =========================================== +// +## 2.4G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 3: =========================================== +// +## 2.4G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 16 16 16 +CH02 17 16 16 +CH03 17 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 4: =========================================== +// +## 2.4G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 15 16 16 +CH02 16 16 16 +CH03 16 16 16 +CH04 16 16 16 +CH05 16 16 16 +CH06 16 16 16 +CH07 16 16 16 +CH08 16 16 16 +CH09 16 16 16 +CH10 16 16 16 +CH11 15 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 5: =========================================== +// +## 2.4G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 16 16 16 +CH04 17 16 16 +CH05 17 16 16 +CH06 17 16 16 +CH07 17 16 16 +CH08 17 16 16 +CH09 17 16 16 +CH10 17 16 16 +CH11 16 16 16 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 6: =========================================== +// +## 2.4G, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +CH01 NA NA NA +CH02 NA NA NA +CH03 15 15 15 +CH04 17 15 15 +CH05 17 15 15 +CH06 17 15 15 +CH07 17 15 15 +CH08 17 15 15 +CH09 17 15 15 +CH10 17 15 15 +CH11 15 15 15 +CH12 NA 16 16 +CH13 NA 16 16 +CH14 NA NA NA +## END +// +//Table 7: =========================================== +// +## 5G, 20M, 1T, OFDM, //(6M;9M;12M;18M;24M;36M;48M;54M) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 8: ====================================== +// +## 5G, 20M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 15 16 16 +CH40 15 16 16 +CH44 15 16 16 +CH48 15 16 16 +//5G Band 2 +CH52 18 16 16 +CH56 17 16 16 +CH60 16 16 16 +CH64 14 16 16 +//5G Band 3 +CH100 15 16 16 +CH114 15 16 16 +CH108 16 16 16 +CH112 17 16 16 +CH116 17 16 16 +CH120 18 16 16 +CH124 17 16 16 +CH128 16 16 16 +CH132 15 16 16 +CH136 15 16 16 +CH140 14 16 16 +//5G Band 4 +CH149 18 16 NA +CH153 18 16 NA +CH157 18 16 NA +CH161 18 16 NA +CH165 18 16 NA +## END +// +//Table 9: =========================================== +// +## 5G, 20M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH36 14 15 15 +CH40 14 15 15 +CH44 14 15 15 +CH48 14 15 15 +//5G Band 2 +CH52 17 15 15 +CH56 16 15 15 +CH60 15 15 15 +CH64 13 15 15 +//5G Band 3 +CH100 14 15 15 +CH114 14 15 15 +CH108 15 15 15 +CH112 16 15 15 +CH116 16 15 15 +CH120 17 15 15 +CH124 16 15 15 +CH128 15 15 15 +CH132 14 15 15 +CH136 14 15 15 +CH140 13 15 15 +//5G Band 4 +CH149 17 15 NA +CH153 17 15 NA +CH157 17 15 NA +CH161 17 15 NA +CH165 17 15 NA +## END +// +//Table 10: =========================================== +// +## 5G, 40M, 1T, HT, //(MCS0~MCS7) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 15 16 16 +CH46 15 16 16 +//5G Band 2 +CH54 16 16 16 +CH62 16 16 16 +//5G Band 3 +CH102 14 16 16 +CH110 16 16 16 +CH118 18 16 16 +CH126 17 16 16 +CH134 16 16 16 +//5G Band 4 +CH151 18 16 NA +CH159 18 16 NA +## END +// +//Table 11: =========================================== +// +## 5G;, 40M, 2T, HT, //(MCS8~MCS15) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH38 14 15 15 +CH46 14 15 15 +//5G Band 2 +CH54 15 15 15 +CH62 15 15 15 +//5G Band 3 +CH102 13 15 15 +CH110 15 15 15 +CH118 17 15 15 +CH126 16 15 15 +CH134 15 15 15 +//5G Band 4 +CH151 17 15 NA +CH159 17 15 NA +## END +// +//Table 12: =========================================== +// +## 5G, 80M, 1T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 15 16 16 +//5G Band 2 +CH58 14 16 16 +//5G Band 3 +CH106 15 16 16 +CH122 17 16 16 +//5G Band 4 +CH155 18 16 NA +## END +// +//Table 13: =========================================== +// +## 5G, 80M, 2T, VHT, //(MCS0~MCS9) +## START +## #3# FCC ETSI MKK +//5G Band 1 +CH42 14 15 15 +//5G Band 2 +CH58 13 15 15 +//5G Band 3 +CH106 14 15 15 +CH122 16 15 15 +//5G Band 4 +CH155 17 15 NA +## END diff --git a/package/kernel/rtl8192cd/data_92d/AGC_TAB_2G_n.txt b/package/kernel/rtl8192cd/data_92d/AGC_TAB_2G_n.txt index 9ac9ca76f64..d09eaaa8ab8 100644 --- a/package/kernel/rtl8192cd/data_92d/AGC_TAB_2G_n.txt +++ b/package/kernel/rtl8192cd/data_92d/AGC_TAB_2G_n.txt @@ -1,265 +1,265 @@ -// AGC_TABLE 100319 -0xc78 0x7B000001 //-110 -0xc78 0x7B010001 -0xc78 0x7B020001 -0xc78 0x7B030001 -0xc78 0x7B040001 -0xc78 0x7B050001 //-100 -0xc78 0x7B060001 -0xc78 0x7A070001 -0xc78 0x79080001 -0xc78 0x78090001 -0xc78 0x770A0001 //-90 -0xc78 0x760B0001 -0xc78 0x750C0001 -0xc78 0x740D0001 -0xc78 0x730E0001 -0xc78 0x720F0001 //-80 -0xc78 0x71100001 -0xc78 0x70110001 -0xc78 0x6F120001 -0xc78 0x6E130001 -0xc78 0x6D140001 //-70 -0xc78 0x6C150001 -0xc78 0x6B160001 -0xc78 0x6A170001 -0xc78 0x69180001 -0xc78 0x68190001 //-60 -0xc78 0x671A0001 -0xc78 0x661B0001 -0xc78 0x651C0001 -0xc78 0x641D0001 -0xc78 0x631E0001 //-50 -0xc78 0x621F0001 -0xc78 0x61200001 -0xc78 0x60210001 -0xc78 0x49220001 -0xc78 0x48230001 //-40 -0xc78 0x47240001 -0xc78 0x46250001 -0xc78 0x45260001 -0xc78 0x44270001 -0xc78 0x43280001 //-30 -0xc78 0x42290001 -0xc78 0x412A0001 -0xc78 0x402B0001 -0xc78 0x262C0001 -0xc78 0x252D0001 //-20 -0xc78 0x242E0001 -0xc78 0x232F0001 -0xc78 0x22300001 -0xc78 0x21310001 -0xc78 0x20320001 //-10 -0xc78 0x06330001 -0xc78 0x05340001 -0xc78 0x04350001 -0xc78 0x03360001 -0xc78 0x02370001 //0 -0xc78 0x01380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -//// AGC_TABLE 2 -//0xc78 0x7B400001 //-110 -//0xc78 0x7B410001 -//0xc78 0x7B420001 -//0xc78 0x7B430001 -//0xc78 0x7B440001 -//0xc78 0x7B450001 //-100 -//0xc78 0x7B460001 -//0xc78 0x7A470001 -//0xc78 0x79480001 -//0xc78 0x78490001 -//0xc78 0x774a0001 //-90 -//0xc78 0x764b0001 -//0xc78 0x754c0001 -//0xc78 0x744d0001 -//0xc78 0x734e0001 -//0xc78 0x724f0001 //-80 -//0xc78 0x71500001 -//0xc78 0x70510001 -//0xc78 0x6F520001 -//0xc78 0x6E530001 -//0xc78 0x6D540001 //-70 -//0xc78 0x6C550001 -//0xc78 0x6B560001 -//0xc78 0x6A570001 -//0xc78 0x69580001 -//0xc78 0x68590001 //-60 -//0xc78 0x675a0001 -//0xc78 0x665b0001 -//0xc78 0x655c0001 -//0xc78 0x645d0001 -//0xc78 0x635e0001 //-50 -//0xc78 0x625f0001 -//0xc78 0x61600001 -//0xc78 0x60610001 -//0xc78 0x49620001 -//0xc78 0x48630001 //-40 -//0xc78 0x47640001 -//0xc78 0x46650001 -//0xc78 0x45660001 -//0xc78 0x44670001 -//0xc78 0x43680001 //-30 -//0xc78 0x42690001 -//0xc78 0x416a0001 -//0xc78 0x406b0001 -//0xc78 0x266c0001 -//0xc78 0x256d0001 //-20 -//0xc78 0x246e0001 -//0xc78 0x236f0001 -//0xc78 0x22700001 -//0xc78 0x21710001 -//0xc78 0x20720001 //-10 -//0xc78 0x06730001 -//0xc78 0x05740001 -//0xc78 0x04750001 -//0xc78 0x03760001 -//0xc78 0x02770001 //0 -//0xc78 0x01780001 -//0xc78 0x00790001 -//0xc78 0x007a0001 -//0xc78 0x007b0001 -//0xc78 0x007c0001 //10 -//0xc78 0x007d0001 -//0xc78 0x007e0001 -//0xc78 0x007f0001 //16 -// RSSI TABLE_0 (for 2G) -0xc78 0x38000002 -0xc78 0x38010002 -0xc78 0x38020002 -0xc78 0x38030002 -0xc78 0x38040002 -0xc78 0x38050002 -0xc78 0x38060002 -0xc78 0x38070002 -0xc78 0x38080002 //-54 -0xc78 0x3C090002 //-50 -0xc78 0x3E0A0002 -0xc78 0x400B0002 //-46 -0xc78 0x440C0002 //-42 -0xc78 0x480D0002 //-38 -0xc78 0x4C0E0002 -0xc78 0x500F0002 //-30 -0xc78 0x52100002 -0xc78 0x56110002 //-24 -0xc78 0x5A120002 //-20 -0xc78 0x5E130002 -0xc78 0x60140002 //-14 -0xc78 0x60150002 -0xc78 0x60160002 -0xc78 0x62170002 -0xc78 0x62180002 -0xc78 0x62190002 -0xc78 0x621A0002 -0xc78 0x621B0002 -0xc78 0x621C0002 -0xc78 0x621D0002 -0xc78 0x621E0002 -0xc78 0x621F0002 -//// RSSI TABLE_1 (for 5G) -//0xc78 0x28000044 -//0xc78 0x28010044 -//0xc78 0x28020044 -//0xc78 0x28030044 -//0xc78 0x28040044 -//0xc78 0x28050044 -//0xc78 0x30060044 -//0xc78 0x31070044 -//0xc78 0x32080044 -//0xc78 0x35090044 -//0xc78 0x370a0044 -//0xc78 0x3a0b0044 -//0xc78 0x3c0c0044 -//0xc78 0x3f0d0044 -//0xc78 0x410e0044 -//0xc78 0x440f0044 -//0xc78 0x46100044 -//0xc78 0x4b110044 -//0xc78 0x50120044 -//0xc78 0x52130044 -//0xc78 0x55140044 -//0xc78 0x57150044 -//0xc78 0x5a160044 -//0xc78 0x5c170044 -//0xc78 0x5e180044 -//0xc78 0x60190044 -//0xc78 0x621A0044 -//0xc78 0x651B0044 -//0xc78 0x681C0044 -//0xc78 0x6b1D0044 -//0xc78 0x6e1E0044 -//0xc78 0x6e1F0044 -//// RSSI TABLE_2 -//0xc78 0x28000088 -//0xc78 0x28010088 -//0xc78 0x28020088 -//0xc78 0x28030088 -//0xc78 0x28040088 -//0xc78 0x28050088 -//0xc78 0x30060088 -//0xc78 0x31070088 -//0xc78 0x32080088 -//0xc78 0x35090088 -//0xc78 0x370a0088 -//0xc78 0x3a0b0088 -//0xc78 0x3c0c0088 -//0xc78 0x3f0d0088 -//0xc78 0x410e0088 -//0xc78 0x440f0088 -//0xc78 0x46100088 -//0xc78 0x4b110088 -//0xc78 0x50120088 -//0xc78 0x52130088 -//0xc78 0x55140088 -//0xc78 0x57150088 -//0xc78 0x5a160088 -//0xc78 0x5c170088 -//0xc78 0x5e180088 -//0xc78 0x60190088 -//0xc78 0x621A0088 -//0xc78 0x651B0088 -//0xc78 0x681C0088 -//0xc78 0x6b1D0088 -//0xc78 0x6e1E0088 -//0xc78 0x6e1F0088 -//// RSSI TABLE_3 -//0xc78 0x280000d0 -//0xc78 0x280100d0 -//0xc78 0x280200d0 -//0xc78 0x280300d0 -//0xc78 0x280400d0 -//0xc78 0x280500d0 -//0xc78 0x300600d0 -//0xc78 0x310700d0 -//0xc78 0x320800d0 -//0xc78 0x350900d0 -//0xc78 0x370a00d0 -//0xc78 0x3a0b00d0 -//0xc78 0x3c0c00d0 -//0xc78 0x3f0d00d0 -//0xc78 0x410e00d0 -//0xc78 0x440f00d0 -//0xc78 0x461000d0 -//0xc78 0x4b1100d0 -//0xc78 0x501200d0 -//0xc78 0x521300d0 -//0xc78 0x551400d0 -//0xc78 0x571500d0 -//0xc78 0x5a1600d0 -//0xc78 0x5c1700d0 -//0xc78 0x5e1800d0 -//0xc78 0x601900d0 -//0xc78 0x621A00d0 -//0xc78 0x651B00d0 -//0xc78 0x681C00d0 -//0xc78 0x6b1D00d0 -//0xc78 0x6e1E00d0 -//0xc78 0x6e1F00d0 -// disable all AGC& RSSI table select -0xc78 0x6e1f0000 +// AGC_TABLE 100319 +0xc78 0x7B000001 //-110 +0xc78 0x7B010001 +0xc78 0x7B020001 +0xc78 0x7B030001 +0xc78 0x7B040001 +0xc78 0x7B050001 //-100 +0xc78 0x7B060001 +0xc78 0x7A070001 +0xc78 0x79080001 +0xc78 0x78090001 +0xc78 0x770A0001 //-90 +0xc78 0x760B0001 +0xc78 0x750C0001 +0xc78 0x740D0001 +0xc78 0x730E0001 +0xc78 0x720F0001 //-80 +0xc78 0x71100001 +0xc78 0x70110001 +0xc78 0x6F120001 +0xc78 0x6E130001 +0xc78 0x6D140001 //-70 +0xc78 0x6C150001 +0xc78 0x6B160001 +0xc78 0x6A170001 +0xc78 0x69180001 +0xc78 0x68190001 //-60 +0xc78 0x671A0001 +0xc78 0x661B0001 +0xc78 0x651C0001 +0xc78 0x641D0001 +0xc78 0x631E0001 //-50 +0xc78 0x621F0001 +0xc78 0x61200001 +0xc78 0x60210001 +0xc78 0x49220001 +0xc78 0x48230001 //-40 +0xc78 0x47240001 +0xc78 0x46250001 +0xc78 0x45260001 +0xc78 0x44270001 +0xc78 0x43280001 //-30 +0xc78 0x42290001 +0xc78 0x412A0001 +0xc78 0x402B0001 +0xc78 0x262C0001 +0xc78 0x252D0001 //-20 +0xc78 0x242E0001 +0xc78 0x232F0001 +0xc78 0x22300001 +0xc78 0x21310001 +0xc78 0x20320001 //-10 +0xc78 0x06330001 +0xc78 0x05340001 +0xc78 0x04350001 +0xc78 0x03360001 +0xc78 0x02370001 //0 +0xc78 0x01380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +//// AGC_TABLE 2 +//0xc78 0x7B400001 //-110 +//0xc78 0x7B410001 +//0xc78 0x7B420001 +//0xc78 0x7B430001 +//0xc78 0x7B440001 +//0xc78 0x7B450001 //-100 +//0xc78 0x7B460001 +//0xc78 0x7A470001 +//0xc78 0x79480001 +//0xc78 0x78490001 +//0xc78 0x774a0001 //-90 +//0xc78 0x764b0001 +//0xc78 0x754c0001 +//0xc78 0x744d0001 +//0xc78 0x734e0001 +//0xc78 0x724f0001 //-80 +//0xc78 0x71500001 +//0xc78 0x70510001 +//0xc78 0x6F520001 +//0xc78 0x6E530001 +//0xc78 0x6D540001 //-70 +//0xc78 0x6C550001 +//0xc78 0x6B560001 +//0xc78 0x6A570001 +//0xc78 0x69580001 +//0xc78 0x68590001 //-60 +//0xc78 0x675a0001 +//0xc78 0x665b0001 +//0xc78 0x655c0001 +//0xc78 0x645d0001 +//0xc78 0x635e0001 //-50 +//0xc78 0x625f0001 +//0xc78 0x61600001 +//0xc78 0x60610001 +//0xc78 0x49620001 +//0xc78 0x48630001 //-40 +//0xc78 0x47640001 +//0xc78 0x46650001 +//0xc78 0x45660001 +//0xc78 0x44670001 +//0xc78 0x43680001 //-30 +//0xc78 0x42690001 +//0xc78 0x416a0001 +//0xc78 0x406b0001 +//0xc78 0x266c0001 +//0xc78 0x256d0001 //-20 +//0xc78 0x246e0001 +//0xc78 0x236f0001 +//0xc78 0x22700001 +//0xc78 0x21710001 +//0xc78 0x20720001 //-10 +//0xc78 0x06730001 +//0xc78 0x05740001 +//0xc78 0x04750001 +//0xc78 0x03760001 +//0xc78 0x02770001 //0 +//0xc78 0x01780001 +//0xc78 0x00790001 +//0xc78 0x007a0001 +//0xc78 0x007b0001 +//0xc78 0x007c0001 //10 +//0xc78 0x007d0001 +//0xc78 0x007e0001 +//0xc78 0x007f0001 //16 +// RSSI TABLE_0 (for 2G) +0xc78 0x38000002 +0xc78 0x38010002 +0xc78 0x38020002 +0xc78 0x38030002 +0xc78 0x38040002 +0xc78 0x38050002 +0xc78 0x38060002 +0xc78 0x38070002 +0xc78 0x38080002 //-54 +0xc78 0x3C090002 //-50 +0xc78 0x3E0A0002 +0xc78 0x400B0002 //-46 +0xc78 0x440C0002 //-42 +0xc78 0x480D0002 //-38 +0xc78 0x4C0E0002 +0xc78 0x500F0002 //-30 +0xc78 0x52100002 +0xc78 0x56110002 //-24 +0xc78 0x5A120002 //-20 +0xc78 0x5E130002 +0xc78 0x60140002 //-14 +0xc78 0x60150002 +0xc78 0x60160002 +0xc78 0x62170002 +0xc78 0x62180002 +0xc78 0x62190002 +0xc78 0x621A0002 +0xc78 0x621B0002 +0xc78 0x621C0002 +0xc78 0x621D0002 +0xc78 0x621E0002 +0xc78 0x621F0002 +//// RSSI TABLE_1 (for 5G) +//0xc78 0x28000044 +//0xc78 0x28010044 +//0xc78 0x28020044 +//0xc78 0x28030044 +//0xc78 0x28040044 +//0xc78 0x28050044 +//0xc78 0x30060044 +//0xc78 0x31070044 +//0xc78 0x32080044 +//0xc78 0x35090044 +//0xc78 0x370a0044 +//0xc78 0x3a0b0044 +//0xc78 0x3c0c0044 +//0xc78 0x3f0d0044 +//0xc78 0x410e0044 +//0xc78 0x440f0044 +//0xc78 0x46100044 +//0xc78 0x4b110044 +//0xc78 0x50120044 +//0xc78 0x52130044 +//0xc78 0x55140044 +//0xc78 0x57150044 +//0xc78 0x5a160044 +//0xc78 0x5c170044 +//0xc78 0x5e180044 +//0xc78 0x60190044 +//0xc78 0x621A0044 +//0xc78 0x651B0044 +//0xc78 0x681C0044 +//0xc78 0x6b1D0044 +//0xc78 0x6e1E0044 +//0xc78 0x6e1F0044 +//// RSSI TABLE_2 +//0xc78 0x28000088 +//0xc78 0x28010088 +//0xc78 0x28020088 +//0xc78 0x28030088 +//0xc78 0x28040088 +//0xc78 0x28050088 +//0xc78 0x30060088 +//0xc78 0x31070088 +//0xc78 0x32080088 +//0xc78 0x35090088 +//0xc78 0x370a0088 +//0xc78 0x3a0b0088 +//0xc78 0x3c0c0088 +//0xc78 0x3f0d0088 +//0xc78 0x410e0088 +//0xc78 0x440f0088 +//0xc78 0x46100088 +//0xc78 0x4b110088 +//0xc78 0x50120088 +//0xc78 0x52130088 +//0xc78 0x55140088 +//0xc78 0x57150088 +//0xc78 0x5a160088 +//0xc78 0x5c170088 +//0xc78 0x5e180088 +//0xc78 0x60190088 +//0xc78 0x621A0088 +//0xc78 0x651B0088 +//0xc78 0x681C0088 +//0xc78 0x6b1D0088 +//0xc78 0x6e1E0088 +//0xc78 0x6e1F0088 +//// RSSI TABLE_3 +//0xc78 0x280000d0 +//0xc78 0x280100d0 +//0xc78 0x280200d0 +//0xc78 0x280300d0 +//0xc78 0x280400d0 +//0xc78 0x280500d0 +//0xc78 0x300600d0 +//0xc78 0x310700d0 +//0xc78 0x320800d0 +//0xc78 0x350900d0 +//0xc78 0x370a00d0 +//0xc78 0x3a0b00d0 +//0xc78 0x3c0c00d0 +//0xc78 0x3f0d00d0 +//0xc78 0x410e00d0 +//0xc78 0x440f00d0 +//0xc78 0x461000d0 +//0xc78 0x4b1100d0 +//0xc78 0x501200d0 +//0xc78 0x521300d0 +//0xc78 0x551400d0 +//0xc78 0x571500d0 +//0xc78 0x5a1600d0 +//0xc78 0x5c1700d0 +//0xc78 0x5e1800d0 +//0xc78 0x601900d0 +//0xc78 0x621A00d0 +//0xc78 0x651B00d0 +//0xc78 0x681C00d0 +//0xc78 0x6b1D00d0 +//0xc78 0x6e1E00d0 +//0xc78 0x6e1F00d0 +// disable all AGC& RSSI table select +0xc78 0x6e1f0000 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/AGC_TAB_5G_n.txt b/package/kernel/rtl8192cd/data_92d/AGC_TAB_5G_n.txt index 9a4d9e9e377..709e289ff2b 100644 --- a/package/kernel/rtl8192cd/data_92d/AGC_TAB_5G_n.txt +++ b/package/kernel/rtl8192cd/data_92d/AGC_TAB_5G_n.txt @@ -1,265 +1,265 @@ -// AGC_TABLE 101222 -0xc78 0x7b000001 //-110 -0xc78 0x7b010001 -0xc78 0x7a020001 -0xc78 0x79030001 -0xc78 0x78040001 -0xc78 0x77050001 //-100 -0xc78 0x76060001 -0xc78 0x75070001 -0xc78 0x74080001 -0xc78 0x73090001 -0xc78 0x720A0001 //-90 -0xc78 0x710B0001 -0xc78 0x700C0001 -0xc78 0x6f0D0001 -0xc78 0x6e0E0001 -0xc78 0x6d0F0001 //-80 -0xc78 0x6c100001 -0xc78 0x6b110001 -0xc78 0x6a120001 -0xc78 0x69130001 -0xc78 0x68140001 //-70 -0xc78 0x67150001 -0xc78 0x66160001 -0xc78 0x65170001 -0xc78 0x64180001 -0xc78 0x63190001 //-60 -0xc78 0x621A0001 -0xc78 0x611B0001 -0xc78 0x601C0001 -0xc78 0x481D0001 -0xc78 0x471E0001 //-50 -0xc78 0x461F0001 -0xc78 0x45200001 -0xc78 0x44210001 -0xc78 0x43220001 -0xc78 0x42230001 //-40 -0xc78 0x41240001 -0xc78 0x40250001 -0xc78 0x27260001 -0xc78 0x26270001 -0xc78 0x25280001 //-30 -0xc78 0x24290001 -0xc78 0x232A0001 -0xc78 0x222B0001 -0xc78 0x212C0001 -0xc78 0x202D0001 //-20 -0xc78 0x202E0001 -0xc78 0x202F0001 -0xc78 0x20300001 -0xc78 0x20310001 -0xc78 0x20320001 //-10 -0xc78 0x20330001 -0xc78 0x20340001 -0xc78 0x20350001 -0xc78 0x20360001 -0xc78 0x20370001 //0 -0xc78 0x20380001 -0xc78 0x20390001 -0xc78 0x203A0001 -0xc78 0x203B0001 -0xc78 0x203C0001 //10 -0xc78 0x203D0001 -0xc78 0x203E0001 -0xc78 0x203F0001 //16 -//// AGC_TABLE 2 -//0xc78 0x7b400001 //-110 -//0xc78 0x7b410001 -//0xc78 0x7b420001 -//0xc78 0x7a430001 -//0xc78 0x79440001 -//0xc78 0x78450001 //-100 -//0xc78 0x77460001 -//0xc78 0x76470001 -//0xc78 0x75480001 -//0xc78 0x74490001 -//0xc78 0x734a0001 //-90 -//0xc78 0x724b0001 -//0xc78 0x714c0001 -//0xc78 0x704d0001 -//0xc78 0x6f4e0001 -//0xc78 0x6e4f0001 //-80 -//0xc78 0x6d500001 -//0xc78 0x6c510001 -//0xc78 0x6b520001 -//0xc78 0x6a530001 -//0xc78 0x69540001 //-70 -//0xc78 0x68550001 -//0xc78 0x67560001 -//0xc78 0x66570001 -//0xc78 0x65580001 -//0xc78 0x64590001 //-60 -//0xc78 0x635a0001 -//0xc78 0x625b0001 -//0xc78 0x615c0001 -//0xc78 0x605d0001 -//0xc78 0x435e0001 //-50 -//0xc78 0x425f0001 -//0xc78 0x41600001 -//0xc78 0x40610001 -//0xc78 0x27620001 -//0xc78 0x26630001 //-40 -//0xc78 0x25640001 -//0xc78 0x24650001 -//0xc78 0x23660001 -//0xc78 0x22670001 -//0xc78 0x21680001 //-30 -//0xc78 0x20690001 -//0xc78 0x206a0001 -//0xc78 0x206b0001 -//0xc78 0x206c0001 -//0xc78 0x206d0001 //-20 -//0xc78 0x206e0001 -//0xc78 0x206f0001 -//0xc78 0x20700001 -//0xc78 0x20710001 -//0xc78 0x20720001 //-10 -//0xc78 0x20730001 -//0xc78 0x20740001 -//0xc78 0x20750001 -//0xc78 0x20760001 -//0xc78 0x20770001 //0 -//0xc78 0x20780001 -//0xc78 0x20790001 -//0xc78 0x207a0001 -//0xc78 0x207b0001 -//0xc78 0x207c0001 //10 -//0xc78 0x207d0001 -//0xc78 0x207e0001 -//0xc78 0x207f0001 //16 -//// RSSI TABLE_0 (for 2G) -//0xc78 0x38000002 -//0xc78 0x38010002 -//0xc78 0x38020002 -//0xc78 0x38030002 -//0xc78 0x38040002 -//0xc78 0x38050002 -//0xc78 0x38060002 -//0xc78 0x38070002 -//0xc78 0x38080002 //-54 -//0xc78 0x3C090002 //-50 -//0xc78 0x3E0A0002 -//0xc78 0x400B0002 //-46 -//0xc78 0x440C0002 //-42 -//0xc78 0x480D0002 //-38 -//0xc78 0x4C0E0002 -//0xc78 0x500F0002 //-30 -//0xc78 0x52100002 -//0xc78 0x56110002 //-24 -//0xc78 0x5A120002 //-20 -//0xc78 0x5E130002 -//0xc78 0x60140002 //-14 -//0xc78 0x60150002 -//0xc78 0x60160002 -//0xc78 0x62170002 -//0xc78 0x62180002 -//0xc78 0x62190002 -//0xc78 0x621A0002 -//0xc78 0x621B0002 -//0xc78 0x621C0002 -//0xc78 0x621D0002 -//0xc78 0x621E0002 -//0xc78 0x621F0002 -// RSSI TABLE_1 (for 5G) -0xc78 0x32000044 -0xc78 0x32010044 -0xc78 0x32020044 -0xc78 0x32030044 -0xc78 0x32040044 -0xc78 0x32050044 -0xc78 0x32060044 -0xc78 0x32070044 -0xc78 0x32080044 //-60 32 -0xc78 0x34090044 -0xc78 0x350a0044 -0xc78 0x360b0044 -0xc78 0x370c0044 -0xc78 0x380d0044 -0xc78 0x390e0044 -0xc78 0x3a0f0044 //-50 3a -0xc78 0x3e100044 -0xc78 0x42110044 -0xc78 0x44120044 -0xc78 0x46130044 //-40 46 -0xc78 0x4a140044 -0xc78 0x4e150044 -0xc78 0x50160044 //-30 50 -0xc78 0x55170044 -0xc78 0x5a180044 //-20 5a -0xc78 0x5e190044 -0xc78 0x641A0044 //-10 64 -0xc78 0x6e1B0044 //0 6e -0xc78 0x6e1C0044 -0xc78 0x6e1D0044 -0xc78 0x6e1E0044 -0xc78 0x6e1F0044 -//// RSSI TABLE_2 -//0xc78 0x32000088 -//0xc78 0x32010088 -//0xc78 0x32020088 -//0xc78 0x32030088 -//0xc78 0x32040088 -//0xc78 0x32050088 -//0xc78 0x38060088 -//0xc78 0x38070088 -//0xc78 0x38080088 -//0xc78 0x40090088 -//0xc78 0x460a0088 -//0xc78 0x4a0b0088 -//0xc78 0x4e0c0088 -//0xc78 0x540d0088 -//0xc78 0x560e0088 -//0xc78 0x580f0088 -//0xc78 0x5c100088 -//0xc78 0x64110088 -//0xc78 0x6a120088 -//0xc78 0x6e130088 -//0xc78 0x6e140088 -//0xc78 0x6e150088 -//0xc78 0x6e160088 -//0xc78 0x6e170088 -//0xc78 0x6e180088 -//0xc78 0x6e190088 -//0xc78 0x6e1A0088 -//0xc78 0x6e1B0088 -//0xc78 0x6e1C0088 -//0xc78 0x6e1D0088 -//0xc78 0x6e1E0088 -//0xc78 0x6e1F0088 -//// RSSI TABLE_3 -//0xc78 0x320000d0 -//0xc78 0x320100d0 -//0xc78 0x320200d0 -//0xc78 0x320300d0 -//0xc78 0x320400d0 -//0xc78 0x320500d0 -//0xc78 0x380600d0 -//0xc78 0x380700d0 -//0xc78 0x380800d0 -//0xc78 0x400900d0 -//0xc78 0x460a00d0 -//0xc78 0x4a0b00d0 -//0xc78 0x4e0c00d0 -//0xc78 0x540d00d0 -//0xc78 0x560e00d0 -//0xc78 0x580f00d0 -//0xc78 0x5c1000d0 -//0xc78 0x641100d0 -//0xc78 0x6a1200d0 -//0xc78 0x6e1300d0 -//0xc78 0x6e1400d0 -//0xc78 0x6e1500d0 -//0xc78 0x6e1600d0 -//0xc78 0x6e1700d0 -//0xc78 0x6e1800d0 -//0xc78 0x6e1900d0 -//0xc78 0x6e1A00d0 -//0xc78 0x6e1B00d0 -//0xc78 0x6e1C00d0 -//0xc78 0x6e1D00d0 -//0xc78 0x6e1E00d0 -//0xc78 0x6e1F00d0 -// disable all AGC& RSSI table select -0xc78 0x6e1f0000 +// AGC_TABLE 101222 +0xc78 0x7b000001 //-110 +0xc78 0x7b010001 +0xc78 0x7a020001 +0xc78 0x79030001 +0xc78 0x78040001 +0xc78 0x77050001 //-100 +0xc78 0x76060001 +0xc78 0x75070001 +0xc78 0x74080001 +0xc78 0x73090001 +0xc78 0x720A0001 //-90 +0xc78 0x710B0001 +0xc78 0x700C0001 +0xc78 0x6f0D0001 +0xc78 0x6e0E0001 +0xc78 0x6d0F0001 //-80 +0xc78 0x6c100001 +0xc78 0x6b110001 +0xc78 0x6a120001 +0xc78 0x69130001 +0xc78 0x68140001 //-70 +0xc78 0x67150001 +0xc78 0x66160001 +0xc78 0x65170001 +0xc78 0x64180001 +0xc78 0x63190001 //-60 +0xc78 0x621A0001 +0xc78 0x611B0001 +0xc78 0x601C0001 +0xc78 0x481D0001 +0xc78 0x471E0001 //-50 +0xc78 0x461F0001 +0xc78 0x45200001 +0xc78 0x44210001 +0xc78 0x43220001 +0xc78 0x42230001 //-40 +0xc78 0x41240001 +0xc78 0x40250001 +0xc78 0x27260001 +0xc78 0x26270001 +0xc78 0x25280001 //-30 +0xc78 0x24290001 +0xc78 0x232A0001 +0xc78 0x222B0001 +0xc78 0x212C0001 +0xc78 0x202D0001 //-20 +0xc78 0x202E0001 +0xc78 0x202F0001 +0xc78 0x20300001 +0xc78 0x20310001 +0xc78 0x20320001 //-10 +0xc78 0x20330001 +0xc78 0x20340001 +0xc78 0x20350001 +0xc78 0x20360001 +0xc78 0x20370001 //0 +0xc78 0x20380001 +0xc78 0x20390001 +0xc78 0x203A0001 +0xc78 0x203B0001 +0xc78 0x203C0001 //10 +0xc78 0x203D0001 +0xc78 0x203E0001 +0xc78 0x203F0001 //16 +//// AGC_TABLE 2 +//0xc78 0x7b400001 //-110 +//0xc78 0x7b410001 +//0xc78 0x7b420001 +//0xc78 0x7a430001 +//0xc78 0x79440001 +//0xc78 0x78450001 //-100 +//0xc78 0x77460001 +//0xc78 0x76470001 +//0xc78 0x75480001 +//0xc78 0x74490001 +//0xc78 0x734a0001 //-90 +//0xc78 0x724b0001 +//0xc78 0x714c0001 +//0xc78 0x704d0001 +//0xc78 0x6f4e0001 +//0xc78 0x6e4f0001 //-80 +//0xc78 0x6d500001 +//0xc78 0x6c510001 +//0xc78 0x6b520001 +//0xc78 0x6a530001 +//0xc78 0x69540001 //-70 +//0xc78 0x68550001 +//0xc78 0x67560001 +//0xc78 0x66570001 +//0xc78 0x65580001 +//0xc78 0x64590001 //-60 +//0xc78 0x635a0001 +//0xc78 0x625b0001 +//0xc78 0x615c0001 +//0xc78 0x605d0001 +//0xc78 0x435e0001 //-50 +//0xc78 0x425f0001 +//0xc78 0x41600001 +//0xc78 0x40610001 +//0xc78 0x27620001 +//0xc78 0x26630001 //-40 +//0xc78 0x25640001 +//0xc78 0x24650001 +//0xc78 0x23660001 +//0xc78 0x22670001 +//0xc78 0x21680001 //-30 +//0xc78 0x20690001 +//0xc78 0x206a0001 +//0xc78 0x206b0001 +//0xc78 0x206c0001 +//0xc78 0x206d0001 //-20 +//0xc78 0x206e0001 +//0xc78 0x206f0001 +//0xc78 0x20700001 +//0xc78 0x20710001 +//0xc78 0x20720001 //-10 +//0xc78 0x20730001 +//0xc78 0x20740001 +//0xc78 0x20750001 +//0xc78 0x20760001 +//0xc78 0x20770001 //0 +//0xc78 0x20780001 +//0xc78 0x20790001 +//0xc78 0x207a0001 +//0xc78 0x207b0001 +//0xc78 0x207c0001 //10 +//0xc78 0x207d0001 +//0xc78 0x207e0001 +//0xc78 0x207f0001 //16 +//// RSSI TABLE_0 (for 2G) +//0xc78 0x38000002 +//0xc78 0x38010002 +//0xc78 0x38020002 +//0xc78 0x38030002 +//0xc78 0x38040002 +//0xc78 0x38050002 +//0xc78 0x38060002 +//0xc78 0x38070002 +//0xc78 0x38080002 //-54 +//0xc78 0x3C090002 //-50 +//0xc78 0x3E0A0002 +//0xc78 0x400B0002 //-46 +//0xc78 0x440C0002 //-42 +//0xc78 0x480D0002 //-38 +//0xc78 0x4C0E0002 +//0xc78 0x500F0002 //-30 +//0xc78 0x52100002 +//0xc78 0x56110002 //-24 +//0xc78 0x5A120002 //-20 +//0xc78 0x5E130002 +//0xc78 0x60140002 //-14 +//0xc78 0x60150002 +//0xc78 0x60160002 +//0xc78 0x62170002 +//0xc78 0x62180002 +//0xc78 0x62190002 +//0xc78 0x621A0002 +//0xc78 0x621B0002 +//0xc78 0x621C0002 +//0xc78 0x621D0002 +//0xc78 0x621E0002 +//0xc78 0x621F0002 +// RSSI TABLE_1 (for 5G) +0xc78 0x32000044 +0xc78 0x32010044 +0xc78 0x32020044 +0xc78 0x32030044 +0xc78 0x32040044 +0xc78 0x32050044 +0xc78 0x32060044 +0xc78 0x32070044 +0xc78 0x32080044 //-60 32 +0xc78 0x34090044 +0xc78 0x350a0044 +0xc78 0x360b0044 +0xc78 0x370c0044 +0xc78 0x380d0044 +0xc78 0x390e0044 +0xc78 0x3a0f0044 //-50 3a +0xc78 0x3e100044 +0xc78 0x42110044 +0xc78 0x44120044 +0xc78 0x46130044 //-40 46 +0xc78 0x4a140044 +0xc78 0x4e150044 +0xc78 0x50160044 //-30 50 +0xc78 0x55170044 +0xc78 0x5a180044 //-20 5a +0xc78 0x5e190044 +0xc78 0x641A0044 //-10 64 +0xc78 0x6e1B0044 //0 6e +0xc78 0x6e1C0044 +0xc78 0x6e1D0044 +0xc78 0x6e1E0044 +0xc78 0x6e1F0044 +//// RSSI TABLE_2 +//0xc78 0x32000088 +//0xc78 0x32010088 +//0xc78 0x32020088 +//0xc78 0x32030088 +//0xc78 0x32040088 +//0xc78 0x32050088 +//0xc78 0x38060088 +//0xc78 0x38070088 +//0xc78 0x38080088 +//0xc78 0x40090088 +//0xc78 0x460a0088 +//0xc78 0x4a0b0088 +//0xc78 0x4e0c0088 +//0xc78 0x540d0088 +//0xc78 0x560e0088 +//0xc78 0x580f0088 +//0xc78 0x5c100088 +//0xc78 0x64110088 +//0xc78 0x6a120088 +//0xc78 0x6e130088 +//0xc78 0x6e140088 +//0xc78 0x6e150088 +//0xc78 0x6e160088 +//0xc78 0x6e170088 +//0xc78 0x6e180088 +//0xc78 0x6e190088 +//0xc78 0x6e1A0088 +//0xc78 0x6e1B0088 +//0xc78 0x6e1C0088 +//0xc78 0x6e1D0088 +//0xc78 0x6e1E0088 +//0xc78 0x6e1F0088 +//// RSSI TABLE_3 +//0xc78 0x320000d0 +//0xc78 0x320100d0 +//0xc78 0x320200d0 +//0xc78 0x320300d0 +//0xc78 0x320400d0 +//0xc78 0x320500d0 +//0xc78 0x380600d0 +//0xc78 0x380700d0 +//0xc78 0x380800d0 +//0xc78 0x400900d0 +//0xc78 0x460a00d0 +//0xc78 0x4a0b00d0 +//0xc78 0x4e0c00d0 +//0xc78 0x540d00d0 +//0xc78 0x560e00d0 +//0xc78 0x580f00d0 +//0xc78 0x5c1000d0 +//0xc78 0x641100d0 +//0xc78 0x6a1200d0 +//0xc78 0x6e1300d0 +//0xc78 0x6e1400d0 +//0xc78 0x6e1500d0 +//0xc78 0x6e1600d0 +//0xc78 0x6e1700d0 +//0xc78 0x6e1800d0 +//0xc78 0x6e1900d0 +//0xc78 0x6e1A00d0 +//0xc78 0x6e1B00d0 +//0xc78 0x6e1C00d0 +//0xc78 0x6e1D00d0 +//0xc78 0x6e1E00d0 +//0xc78 0x6e1F00d0 +// disable all AGC& RSSI table select +0xc78 0x6e1f0000 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/AGC_TAB_n.txt b/package/kernel/rtl8192cd/data_92d/AGC_TAB_n.txt index e52cd5a38c4..52ed769c05b 100644 --- a/package/kernel/rtl8192cd/data_92d/AGC_TAB_n.txt +++ b/package/kernel/rtl8192cd/data_92d/AGC_TAB_n.txt @@ -1,265 +1,265 @@ -// AGC_TABLE 101222 -0xc78 0x7B000001 //-110 -0xc78 0x7B010001 -0xc78 0x7B020001 -0xc78 0x7B030001 -0xc78 0x7B040001 -0xc78 0x7B050001 //-100 -0xc78 0x7B060001 -0xc78 0x7A070001 -0xc78 0x79080001 -0xc78 0x78090001 -0xc78 0x770A0001 //-90 -0xc78 0x760B0001 -0xc78 0x750C0001 -0xc78 0x740D0001 -0xc78 0x730E0001 -0xc78 0x720F0001 //-80 -0xc78 0x71100001 -0xc78 0x70110001 -0xc78 0x6F120001 -0xc78 0x6E130001 -0xc78 0x6D140001 //-70 -0xc78 0x6C150001 -0xc78 0x6B160001 -0xc78 0x6A170001 -0xc78 0x69180001 -0xc78 0x68190001 //-60 -0xc78 0x671A0001 -0xc78 0x661B0001 -0xc78 0x651C0001 -0xc78 0x641D0001 -0xc78 0x631E0001 //-50 -0xc78 0x621F0001 -0xc78 0x61200001 -0xc78 0x60210001 -0xc78 0x49220001 -0xc78 0x48230001 //-40 -0xc78 0x47240001 -0xc78 0x46250001 -0xc78 0x45260001 -0xc78 0x44270001 -0xc78 0x43280001 //-30 -0xc78 0x42290001 -0xc78 0x412A0001 -0xc78 0x402B0001 -0xc78 0x262C0001 -0xc78 0x252D0001 //-20 -0xc78 0x242E0001 -0xc78 0x232F0001 -0xc78 0x22300001 -0xc78 0x21310001 -0xc78 0x20320001 //-10 -0xc78 0x06330001 -0xc78 0x05340001 -0xc78 0x04350001 -0xc78 0x03360001 -0xc78 0x02370001 //0 -0xc78 0x01380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -// AGC_TABLE 2 -0xc78 0x7b400001 //-110 -0xc78 0x7b410001 -0xc78 0x7a420001 -0xc78 0x79430001 -0xc78 0x78440001 -0xc78 0x77450001 //-100 -0xc78 0x76460001 -0xc78 0x75470001 -0xc78 0x74480001 -0xc78 0x73490001 -0xc78 0x724a0001 //-90 -0xc78 0x714b0001 -0xc78 0x704c0001 -0xc78 0x6f4d0001 -0xc78 0x6e4e0001 -0xc78 0x6d4f0001 //-80 -0xc78 0x6c500001 -0xc78 0x6b510001 -0xc78 0x6a520001 -0xc78 0x69530001 -0xc78 0x68540001 //-70 -0xc78 0x67550001 -0xc78 0x66560001 -0xc78 0x65570001 -0xc78 0x64580001 -0xc78 0x63590001 //-60 -0xc78 0x625a0001 -0xc78 0x615b0001 -0xc78 0x605c0001 -0xc78 0x485d0001 -0xc78 0x475e0001 //-50 -0xc78 0x465f0001 -0xc78 0x45600001 -0xc78 0x44610001 -0xc78 0x43620001 -0xc78 0x42630001 //-40 -0xc78 0x41640001 -0xc78 0x40650001 -0xc78 0x27660001 -0xc78 0x26670001 -0xc78 0x25680001 //-30 -0xc78 0x24690001 -0xc78 0x236a0001 -0xc78 0x226b0001 -0xc78 0x216c0001 -0xc78 0x206d0001 //-20 -0xc78 0x206e0001 -0xc78 0x206f0001 -0xc78 0x20700001 -0xc78 0x20710001 -0xc78 0x20720001 //-10 -0xc78 0x20730001 -0xc78 0x20740001 -0xc78 0x20750001 -0xc78 0x20760001 -0xc78 0x20770001 //0 -0xc78 0x20780001 -0xc78 0x20790001 -0xc78 0x207a0001 -0xc78 0x207b0001 -0xc78 0x207c0001 //10 -0xc78 0x207d0001 -0xc78 0x207e0001 -0xc78 0x207f0001 //16 -// RSSI TABLE_0 (for 2G) -0xc78 0x38000002 -0xc78 0x38010002 -0xc78 0x38020002 -0xc78 0x38030002 -0xc78 0x38040002 -0xc78 0x38050002 -0xc78 0x38060002 -0xc78 0x38070002 -0xc78 0x38080002 //-54 -0xc78 0x3C090002 //-50 -0xc78 0x3E0A0002 -0xc78 0x400B0002 //-46 -0xc78 0x440C0002 //-42 -0xc78 0x480D0002 //-38 -0xc78 0x4C0E0002 -0xc78 0x500F0002 //-30 -0xc78 0x52100002 -0xc78 0x56110002 //-24 -0xc78 0x5A120002 //-20 -0xc78 0x5E130002 -0xc78 0x60140002 //-14 -0xc78 0x60150002 -0xc78 0x60160002 -0xc78 0x62170002 -0xc78 0x62180002 -0xc78 0x62190002 -0xc78 0x621A0002 -0xc78 0x621B0002 -0xc78 0x621C0002 -0xc78 0x621D0002 -0xc78 0x621E0002 -0xc78 0x621F0002 -// RSSI TABLE_1 (for 5G) -0xc78 0x32000044 -0xc78 0x32010044 -0xc78 0x32020044 -0xc78 0x32030044 -0xc78 0x32040044 -0xc78 0x32050044 -0xc78 0x32060044 -0xc78 0x32070044 -0xc78 0x32080044 //-60 32 -0xc78 0x34090044 -0xc78 0x350a0044 -0xc78 0x360b0044 -0xc78 0x370c0044 -0xc78 0x380d0044 -0xc78 0x390e0044 -0xc78 0x3a0f0044 //-50 3a -0xc78 0x3e100044 -0xc78 0x42110044 -0xc78 0x44120044 -0xc78 0x46130044 //-40 46 -0xc78 0x4a140044 -0xc78 0x4e150044 -0xc78 0x50160044 //-30 50 -0xc78 0x55170044 -0xc78 0x5a180044 //-20 5a -0xc78 0x5e190044 -0xc78 0x641A0044 //-10 64 -0xc78 0x6e1B0044 //0 6e -0xc78 0x6e1C0044 -0xc78 0x6e1D0044 -0xc78 0x6e1E0044 -0xc78 0x6e1F0044 -// RSSI TABLE_2 -//0xc78 0x32000088 -//0xc78 0x32010088 -//0xc78 0x32020088 -//0xc78 0x32030088 -//0xc78 0x32040088 -//0xc78 0x32050088 -//0xc78 0x38060088 -//0xc78 0x38070088 -//0xc78 0x38080088 -//0xc78 0x40090088 -//0xc78 0x460a0088 -//0xc78 0x4a0b0088 -//0xc78 0x4e0c0088 -//0xc78 0x540d0088 -//0xc78 0x560e0088 -//0xc78 0x580f0088 -//0xc78 0x5c100088 -//0xc78 0x64110088 -//0xc78 0x6a120088 -//0xc78 0x6e130088 -//0xc78 0x6e140088 -//0xc78 0x6e150088 -//0xc78 0x6e160088 -//0xc78 0x6e170088 -//0xc78 0x6e180088 -//0xc78 0x6e190088 -//0xc78 0x6e1A0088 -//0xc78 0x6e1B0088 -//0xc78 0x6e1C0088 -//0xc78 0x6e1D0088 -//0xc78 0x6e1E0088 -//0xc78 0x6e1F0088 -//// RSSI TABLE_3 -//0xc78 0x320000d0 -//0xc78 0x320100d0 -//0xc78 0x320200d0 -//0xc78 0x320300d0 -//0xc78 0x320400d0 -//0xc78 0x320500d0 -//0xc78 0x380600d0 -//0xc78 0x380700d0 -//0xc78 0x380800d0 -//0xc78 0x400900d0 -//0xc78 0x460a00d0 -//0xc78 0x4a0b00d0 -//0xc78 0x4e0c00d0 -//0xc78 0x540d00d0 -//0xc78 0x560e00d0 -//0xc78 0x580f00d0 -//0xc78 0x5c1000d0 -//0xc78 0x641100d0 -//0xc78 0x6a1200d0 -//0xc78 0x6e1300d0 -//0xc78 0x6e1400d0 -//0xc78 0x6e1500d0 -//0xc78 0x6e1600d0 -//0xc78 0x6e1700d0 -//0xc78 0x6e1800d0 -//0xc78 0x6e1900d0 -//0xc78 0x6e1A00d0 -//0xc78 0x6e1B00d0 -//0xc78 0x6e1C00d0 -//0xc78 0x6e1D00d0 -//0xc78 0x6e1E00d0 -//0xc78 0x6e1F00d0 -// disable all AGC& RSSI table select -0xc78 0x6e1f0000 +// AGC_TABLE 101222 +0xc78 0x7B000001 //-110 +0xc78 0x7B010001 +0xc78 0x7B020001 +0xc78 0x7B030001 +0xc78 0x7B040001 +0xc78 0x7B050001 //-100 +0xc78 0x7B060001 +0xc78 0x7A070001 +0xc78 0x79080001 +0xc78 0x78090001 +0xc78 0x770A0001 //-90 +0xc78 0x760B0001 +0xc78 0x750C0001 +0xc78 0x740D0001 +0xc78 0x730E0001 +0xc78 0x720F0001 //-80 +0xc78 0x71100001 +0xc78 0x70110001 +0xc78 0x6F120001 +0xc78 0x6E130001 +0xc78 0x6D140001 //-70 +0xc78 0x6C150001 +0xc78 0x6B160001 +0xc78 0x6A170001 +0xc78 0x69180001 +0xc78 0x68190001 //-60 +0xc78 0x671A0001 +0xc78 0x661B0001 +0xc78 0x651C0001 +0xc78 0x641D0001 +0xc78 0x631E0001 //-50 +0xc78 0x621F0001 +0xc78 0x61200001 +0xc78 0x60210001 +0xc78 0x49220001 +0xc78 0x48230001 //-40 +0xc78 0x47240001 +0xc78 0x46250001 +0xc78 0x45260001 +0xc78 0x44270001 +0xc78 0x43280001 //-30 +0xc78 0x42290001 +0xc78 0x412A0001 +0xc78 0x402B0001 +0xc78 0x262C0001 +0xc78 0x252D0001 //-20 +0xc78 0x242E0001 +0xc78 0x232F0001 +0xc78 0x22300001 +0xc78 0x21310001 +0xc78 0x20320001 //-10 +0xc78 0x06330001 +0xc78 0x05340001 +0xc78 0x04350001 +0xc78 0x03360001 +0xc78 0x02370001 //0 +0xc78 0x01380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +// AGC_TABLE 2 +0xc78 0x7b400001 //-110 +0xc78 0x7b410001 +0xc78 0x7a420001 +0xc78 0x79430001 +0xc78 0x78440001 +0xc78 0x77450001 //-100 +0xc78 0x76460001 +0xc78 0x75470001 +0xc78 0x74480001 +0xc78 0x73490001 +0xc78 0x724a0001 //-90 +0xc78 0x714b0001 +0xc78 0x704c0001 +0xc78 0x6f4d0001 +0xc78 0x6e4e0001 +0xc78 0x6d4f0001 //-80 +0xc78 0x6c500001 +0xc78 0x6b510001 +0xc78 0x6a520001 +0xc78 0x69530001 +0xc78 0x68540001 //-70 +0xc78 0x67550001 +0xc78 0x66560001 +0xc78 0x65570001 +0xc78 0x64580001 +0xc78 0x63590001 //-60 +0xc78 0x625a0001 +0xc78 0x615b0001 +0xc78 0x605c0001 +0xc78 0x485d0001 +0xc78 0x475e0001 //-50 +0xc78 0x465f0001 +0xc78 0x45600001 +0xc78 0x44610001 +0xc78 0x43620001 +0xc78 0x42630001 //-40 +0xc78 0x41640001 +0xc78 0x40650001 +0xc78 0x27660001 +0xc78 0x26670001 +0xc78 0x25680001 //-30 +0xc78 0x24690001 +0xc78 0x236a0001 +0xc78 0x226b0001 +0xc78 0x216c0001 +0xc78 0x206d0001 //-20 +0xc78 0x206e0001 +0xc78 0x206f0001 +0xc78 0x20700001 +0xc78 0x20710001 +0xc78 0x20720001 //-10 +0xc78 0x20730001 +0xc78 0x20740001 +0xc78 0x20750001 +0xc78 0x20760001 +0xc78 0x20770001 //0 +0xc78 0x20780001 +0xc78 0x20790001 +0xc78 0x207a0001 +0xc78 0x207b0001 +0xc78 0x207c0001 //10 +0xc78 0x207d0001 +0xc78 0x207e0001 +0xc78 0x207f0001 //16 +// RSSI TABLE_0 (for 2G) +0xc78 0x38000002 +0xc78 0x38010002 +0xc78 0x38020002 +0xc78 0x38030002 +0xc78 0x38040002 +0xc78 0x38050002 +0xc78 0x38060002 +0xc78 0x38070002 +0xc78 0x38080002 //-54 +0xc78 0x3C090002 //-50 +0xc78 0x3E0A0002 +0xc78 0x400B0002 //-46 +0xc78 0x440C0002 //-42 +0xc78 0x480D0002 //-38 +0xc78 0x4C0E0002 +0xc78 0x500F0002 //-30 +0xc78 0x52100002 +0xc78 0x56110002 //-24 +0xc78 0x5A120002 //-20 +0xc78 0x5E130002 +0xc78 0x60140002 //-14 +0xc78 0x60150002 +0xc78 0x60160002 +0xc78 0x62170002 +0xc78 0x62180002 +0xc78 0x62190002 +0xc78 0x621A0002 +0xc78 0x621B0002 +0xc78 0x621C0002 +0xc78 0x621D0002 +0xc78 0x621E0002 +0xc78 0x621F0002 +// RSSI TABLE_1 (for 5G) +0xc78 0x32000044 +0xc78 0x32010044 +0xc78 0x32020044 +0xc78 0x32030044 +0xc78 0x32040044 +0xc78 0x32050044 +0xc78 0x32060044 +0xc78 0x32070044 +0xc78 0x32080044 //-60 32 +0xc78 0x34090044 +0xc78 0x350a0044 +0xc78 0x360b0044 +0xc78 0x370c0044 +0xc78 0x380d0044 +0xc78 0x390e0044 +0xc78 0x3a0f0044 //-50 3a +0xc78 0x3e100044 +0xc78 0x42110044 +0xc78 0x44120044 +0xc78 0x46130044 //-40 46 +0xc78 0x4a140044 +0xc78 0x4e150044 +0xc78 0x50160044 //-30 50 +0xc78 0x55170044 +0xc78 0x5a180044 //-20 5a +0xc78 0x5e190044 +0xc78 0x641A0044 //-10 64 +0xc78 0x6e1B0044 //0 6e +0xc78 0x6e1C0044 +0xc78 0x6e1D0044 +0xc78 0x6e1E0044 +0xc78 0x6e1F0044 +// RSSI TABLE_2 +//0xc78 0x32000088 +//0xc78 0x32010088 +//0xc78 0x32020088 +//0xc78 0x32030088 +//0xc78 0x32040088 +//0xc78 0x32050088 +//0xc78 0x38060088 +//0xc78 0x38070088 +//0xc78 0x38080088 +//0xc78 0x40090088 +//0xc78 0x460a0088 +//0xc78 0x4a0b0088 +//0xc78 0x4e0c0088 +//0xc78 0x540d0088 +//0xc78 0x560e0088 +//0xc78 0x580f0088 +//0xc78 0x5c100088 +//0xc78 0x64110088 +//0xc78 0x6a120088 +//0xc78 0x6e130088 +//0xc78 0x6e140088 +//0xc78 0x6e150088 +//0xc78 0x6e160088 +//0xc78 0x6e170088 +//0xc78 0x6e180088 +//0xc78 0x6e190088 +//0xc78 0x6e1A0088 +//0xc78 0x6e1B0088 +//0xc78 0x6e1C0088 +//0xc78 0x6e1D0088 +//0xc78 0x6e1E0088 +//0xc78 0x6e1F0088 +//// RSSI TABLE_3 +//0xc78 0x320000d0 +//0xc78 0x320100d0 +//0xc78 0x320200d0 +//0xc78 0x320300d0 +//0xc78 0x320400d0 +//0xc78 0x320500d0 +//0xc78 0x380600d0 +//0xc78 0x380700d0 +//0xc78 0x380800d0 +//0xc78 0x400900d0 +//0xc78 0x460a00d0 +//0xc78 0x4a0b00d0 +//0xc78 0x4e0c00d0 +//0xc78 0x540d00d0 +//0xc78 0x560e00d0 +//0xc78 0x580f00d0 +//0xc78 0x5c1000d0 +//0xc78 0x641100d0 +//0xc78 0x6a1200d0 +//0xc78 0x6e1300d0 +//0xc78 0x6e1400d0 +//0xc78 0x6e1500d0 +//0xc78 0x6e1600d0 +//0xc78 0x6e1700d0 +//0xc78 0x6e1800d0 +//0xc78 0x6e1900d0 +//0xc78 0x6e1A00d0 +//0xc78 0x6e1B00d0 +//0xc78 0x6e1C00d0 +//0xc78 0x6e1D00d0 +//0xc78 0x6e1E00d0 +//0xc78 0x6e1F00d0 +// disable all AGC& RSSI table select +0xc78 0x6e1f0000 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt index dbaa0ad9b5e..d441f4453fa 100644 --- a/package/kernel/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt @@ -1,265 +1,265 @@ -// AGC_TABLE 101222 -0xc78 0x7B000001 //-110 -0xc78 0x7A010001 -0xc78 0x79020001 -0xc78 0x78030001 -0xc78 0x77040001 -0xc78 0x76050001 //-100 -0xc78 0x75060001 -0xc78 0x74070001 -0xc78 0x73080001 -0xc78 0x72090001 -0xc78 0x710A0001 //-90 -0xc78 0x700B0001 -0xc78 0x6F0C0001 -0xc78 0x6E0D0001 -0xc78 0x6D0E0001 -0xc78 0x6C0F0001 //-80 -0xc78 0x6B100001 -0xc78 0x6A110001 -0xc78 0x69120001 -0xc78 0x68130001 -0xc78 0x67140001 //-70 -0xc78 0x66150001 -0xc78 0x65160001 -0xc78 0x64170001 -0xc78 0x63180001 -0xc78 0x62190001 //-60 -0xc78 0x611A0001 -0xc78 0x601B0001 -0xc78 0x491C0001 -0xc78 0x481D0001 -0xc78 0x471E0001 //-50 -0xc78 0x461F0001 -0xc78 0x45200001 -0xc78 0x44210001 -0xc78 0x43220001 -0xc78 0x42230001 //-40 -0xc78 0x41240001 -0xc78 0x40250001 -0xc78 0x26260001 -0xc78 0x25270001 -0xc78 0x24280001 //-30 -0xc78 0x23290001 -0xc78 0x222A0001 -0xc78 0x212B0001 -0xc78 0x202C0001 -0xc78 0x062D0001 //-20 -0xc78 0x052E0001 -0xc78 0x042F0001 -0xc78 0x03300001 -0xc78 0x02310001 -0xc78 0x01320001 //-10 -0xc78 0x00330001 -0xc78 0x00340001 -0xc78 0x00350001 -0xc78 0x00360001 -0xc78 0x00370001 //0 -0xc78 0x00380001 -0xc78 0x00390001 -0xc78 0x003A0001 -0xc78 0x003B0001 -0xc78 0x003C0001 //10 -0xc78 0x003D0001 -0xc78 0x003E0001 -0xc78 0x003F0001 //16 -// AGC_TABLE 2 -0xc78 0x7b400001 //-110 -0xc78 0x7b410001 -0xc78 0x7a420001 -0xc78 0x79430001 -0xc78 0x78440001 -0xc78 0x77450001 //-100 -0xc78 0x76460001 -0xc78 0x75470001 -0xc78 0x74480001 -0xc78 0x73490001 -0xc78 0x724a0001 //-90 -0xc78 0x714b0001 -0xc78 0x704c0001 -0xc78 0x6f4d0001 -0xc78 0x6e4e0001 -0xc78 0x6d4f0001 //-80 -0xc78 0x6c500001 -0xc78 0x6b510001 -0xc78 0x6a520001 -0xc78 0x69530001 -0xc78 0x68540001 //-70 -0xc78 0x67550001 -0xc78 0x66560001 -0xc78 0x65570001 -0xc78 0x64580001 -0xc78 0x63590001 //-60 -0xc78 0x625a0001 -0xc78 0x615b0001 -0xc78 0x605c0001 -0xc78 0x485d0001 -0xc78 0x475e0001 //-50 -0xc78 0x465f0001 -0xc78 0x45600001 -0xc78 0x44610001 -0xc78 0x43620001 -0xc78 0x42630001 //-40 -0xc78 0x41640001 -0xc78 0x40650001 -0xc78 0x27660001 -0xc78 0x26670001 -0xc78 0x25680001 //-30 -0xc78 0x24690001 -0xc78 0x236a0001 -0xc78 0x226b0001 -0xc78 0x216c0001 -0xc78 0x206d0001 //-20 -0xc78 0x206e0001 -0xc78 0x206f0001 -0xc78 0x20700001 -0xc78 0x20710001 -0xc78 0x20720001 //-10 -0xc78 0x20730001 -0xc78 0x20740001 -0xc78 0x20750001 -0xc78 0x20760001 -0xc78 0x20770001 //0 -0xc78 0x20780001 -0xc78 0x20790001 -0xc78 0x207a0001 -0xc78 0x207b0001 -0xc78 0x207c0001 //10 -0xc78 0x207d0001 -0xc78 0x207e0001 -0xc78 0x207f0001 //16 -// RSSI TABLE_0 (for 2G) -0xc78 0x2C000002 -0xc78 0x2C010002 -0xc78 0x2C020002 -0xc78 0x2C030002 -0xc78 0x2C040002 -0xc78 0x2C050002 -0xc78 0x2C060002 -0xc78 0x2C070002 -0xc78 0x2C080002 //-54 -0xc78 0x30090002 //-50 -0xc78 0x320A0002 -0xc78 0x340B0002 //-46 -0xc78 0x380C0002 //-42 -0xc78 0x3C0D0002 //-38 -0xc78 0x400E0002 -0xc78 0x440F0002 //-30 -0xc78 0x48100002 -0xc78 0x4A110002 //-24 -0xc78 0x4E120002 //-20 -0xc78 0x50130002 -0xc78 0x54140002 //-14 -0xc78 0x58150002 -0xc78 0x5C160002 -0xc78 0x60170002 -0xc78 0x62180002 -0xc78 0x62190002 -0xc78 0x621A0002 -0xc78 0x621B0002 -0xc78 0x621C0002 -0xc78 0x621D0002 -0xc78 0x621E0002 -0xc78 0x621F0002 -// RSSI TABLE_1 (for 5G) -0xc78 0x32000044 -0xc78 0x32010044 -0xc78 0x32020044 -0xc78 0x32030044 -0xc78 0x32040044 -0xc78 0x32050044 -0xc78 0x32060044 -0xc78 0x32070044 -0xc78 0x32080044 //-60 32 -0xc78 0x34090044 -0xc78 0x350a0044 -0xc78 0x360b0044 -0xc78 0x370c0044 -0xc78 0x380d0044 -0xc78 0x390e0044 -0xc78 0x3a0f0044 //-50 3a -0xc78 0x3e100044 -0xc78 0x42110044 -0xc78 0x44120044 -0xc78 0x46130044 //-40 46 -0xc78 0x4a140044 -0xc78 0x4e150044 -0xc78 0x50160044 //-30 50 -0xc78 0x55170044 -0xc78 0x5a180044 //-20 5a -0xc78 0x5e190044 -0xc78 0x641A0044 //-10 64 -0xc78 0x6e1B0044 //0 6e -0xc78 0x6e1C0044 -0xc78 0x6e1D0044 -0xc78 0x6e1E0044 -0xc78 0x6e1F0044 -// RSSI TABLE_2 -//0xc78 0x32000088 -//0xc78 0x32010088 -//0xc78 0x32020088 -//0xc78 0x32030088 -//0xc78 0x32040088 -//0xc78 0x32050088 -//0xc78 0x38060088 -//0xc78 0x38070088 -//0xc78 0x38080088 -//0xc78 0x40090088 -//0xc78 0x460a0088 -//0xc78 0x4a0b0088 -//0xc78 0x4e0c0088 -//0xc78 0x540d0088 -//0xc78 0x560e0088 -//0xc78 0x580f0088 -//0xc78 0x5c100088 -//0xc78 0x64110088 -//0xc78 0x6a120088 -//0xc78 0x6e130088 -//0xc78 0x6e140088 -//0xc78 0x6e150088 -//0xc78 0x6e160088 -//0xc78 0x6e170088 -//0xc78 0x6e180088 -//0xc78 0x6e190088 -//0xc78 0x6e1A0088 -//0xc78 0x6e1B0088 -//0xc78 0x6e1C0088 -//0xc78 0x6e1D0088 -//0xc78 0x6e1E0088 -//0xc78 0x6e1F0088 -//// RSSI TABLE_3 -//0xc78 0x320000d0 -//0xc78 0x320100d0 -//0xc78 0x320200d0 -//0xc78 0x320300d0 -//0xc78 0x320400d0 -//0xc78 0x320500d0 -//0xc78 0x380600d0 -//0xc78 0x380700d0 -//0xc78 0x380800d0 -//0xc78 0x400900d0 -//0xc78 0x460a00d0 -//0xc78 0x4a0b00d0 -//0xc78 0x4e0c00d0 -//0xc78 0x540d00d0 -//0xc78 0x560e00d0 -//0xc78 0x580f00d0 -//0xc78 0x5c1000d0 -//0xc78 0x641100d0 -//0xc78 0x6a1200d0 -//0xc78 0x6e1300d0 -//0xc78 0x6e1400d0 -//0xc78 0x6e1500d0 -//0xc78 0x6e1600d0 -//0xc78 0x6e1700d0 -//0xc78 0x6e1800d0 -//0xc78 0x6e1900d0 -//0xc78 0x6e1A00d0 -//0xc78 0x6e1B00d0 -//0xc78 0x6e1C00d0 -//0xc78 0x6e1D00d0 -//0xc78 0x6e1E00d0 -//0xc78 0x6e1F00d0 -// disable all AGC& RSSI table select -0xc78 0x6e1f0000 +// AGC_TABLE 101222 +0xc78 0x7B000001 //-110 +0xc78 0x7A010001 +0xc78 0x79020001 +0xc78 0x78030001 +0xc78 0x77040001 +0xc78 0x76050001 //-100 +0xc78 0x75060001 +0xc78 0x74070001 +0xc78 0x73080001 +0xc78 0x72090001 +0xc78 0x710A0001 //-90 +0xc78 0x700B0001 +0xc78 0x6F0C0001 +0xc78 0x6E0D0001 +0xc78 0x6D0E0001 +0xc78 0x6C0F0001 //-80 +0xc78 0x6B100001 +0xc78 0x6A110001 +0xc78 0x69120001 +0xc78 0x68130001 +0xc78 0x67140001 //-70 +0xc78 0x66150001 +0xc78 0x65160001 +0xc78 0x64170001 +0xc78 0x63180001 +0xc78 0x62190001 //-60 +0xc78 0x611A0001 +0xc78 0x601B0001 +0xc78 0x491C0001 +0xc78 0x481D0001 +0xc78 0x471E0001 //-50 +0xc78 0x461F0001 +0xc78 0x45200001 +0xc78 0x44210001 +0xc78 0x43220001 +0xc78 0x42230001 //-40 +0xc78 0x41240001 +0xc78 0x40250001 +0xc78 0x26260001 +0xc78 0x25270001 +0xc78 0x24280001 //-30 +0xc78 0x23290001 +0xc78 0x222A0001 +0xc78 0x212B0001 +0xc78 0x202C0001 +0xc78 0x062D0001 //-20 +0xc78 0x052E0001 +0xc78 0x042F0001 +0xc78 0x03300001 +0xc78 0x02310001 +0xc78 0x01320001 //-10 +0xc78 0x00330001 +0xc78 0x00340001 +0xc78 0x00350001 +0xc78 0x00360001 +0xc78 0x00370001 //0 +0xc78 0x00380001 +0xc78 0x00390001 +0xc78 0x003A0001 +0xc78 0x003B0001 +0xc78 0x003C0001 //10 +0xc78 0x003D0001 +0xc78 0x003E0001 +0xc78 0x003F0001 //16 +// AGC_TABLE 2 +0xc78 0x7b400001 //-110 +0xc78 0x7b410001 +0xc78 0x7a420001 +0xc78 0x79430001 +0xc78 0x78440001 +0xc78 0x77450001 //-100 +0xc78 0x76460001 +0xc78 0x75470001 +0xc78 0x74480001 +0xc78 0x73490001 +0xc78 0x724a0001 //-90 +0xc78 0x714b0001 +0xc78 0x704c0001 +0xc78 0x6f4d0001 +0xc78 0x6e4e0001 +0xc78 0x6d4f0001 //-80 +0xc78 0x6c500001 +0xc78 0x6b510001 +0xc78 0x6a520001 +0xc78 0x69530001 +0xc78 0x68540001 //-70 +0xc78 0x67550001 +0xc78 0x66560001 +0xc78 0x65570001 +0xc78 0x64580001 +0xc78 0x63590001 //-60 +0xc78 0x625a0001 +0xc78 0x615b0001 +0xc78 0x605c0001 +0xc78 0x485d0001 +0xc78 0x475e0001 //-50 +0xc78 0x465f0001 +0xc78 0x45600001 +0xc78 0x44610001 +0xc78 0x43620001 +0xc78 0x42630001 //-40 +0xc78 0x41640001 +0xc78 0x40650001 +0xc78 0x27660001 +0xc78 0x26670001 +0xc78 0x25680001 //-30 +0xc78 0x24690001 +0xc78 0x236a0001 +0xc78 0x226b0001 +0xc78 0x216c0001 +0xc78 0x206d0001 //-20 +0xc78 0x206e0001 +0xc78 0x206f0001 +0xc78 0x20700001 +0xc78 0x20710001 +0xc78 0x20720001 //-10 +0xc78 0x20730001 +0xc78 0x20740001 +0xc78 0x20750001 +0xc78 0x20760001 +0xc78 0x20770001 //0 +0xc78 0x20780001 +0xc78 0x20790001 +0xc78 0x207a0001 +0xc78 0x207b0001 +0xc78 0x207c0001 //10 +0xc78 0x207d0001 +0xc78 0x207e0001 +0xc78 0x207f0001 //16 +// RSSI TABLE_0 (for 2G) +0xc78 0x2C000002 +0xc78 0x2C010002 +0xc78 0x2C020002 +0xc78 0x2C030002 +0xc78 0x2C040002 +0xc78 0x2C050002 +0xc78 0x2C060002 +0xc78 0x2C070002 +0xc78 0x2C080002 //-54 +0xc78 0x30090002 //-50 +0xc78 0x320A0002 +0xc78 0x340B0002 //-46 +0xc78 0x380C0002 //-42 +0xc78 0x3C0D0002 //-38 +0xc78 0x400E0002 +0xc78 0x440F0002 //-30 +0xc78 0x48100002 +0xc78 0x4A110002 //-24 +0xc78 0x4E120002 //-20 +0xc78 0x50130002 +0xc78 0x54140002 //-14 +0xc78 0x58150002 +0xc78 0x5C160002 +0xc78 0x60170002 +0xc78 0x62180002 +0xc78 0x62190002 +0xc78 0x621A0002 +0xc78 0x621B0002 +0xc78 0x621C0002 +0xc78 0x621D0002 +0xc78 0x621E0002 +0xc78 0x621F0002 +// RSSI TABLE_1 (for 5G) +0xc78 0x32000044 +0xc78 0x32010044 +0xc78 0x32020044 +0xc78 0x32030044 +0xc78 0x32040044 +0xc78 0x32050044 +0xc78 0x32060044 +0xc78 0x32070044 +0xc78 0x32080044 //-60 32 +0xc78 0x34090044 +0xc78 0x350a0044 +0xc78 0x360b0044 +0xc78 0x370c0044 +0xc78 0x380d0044 +0xc78 0x390e0044 +0xc78 0x3a0f0044 //-50 3a +0xc78 0x3e100044 +0xc78 0x42110044 +0xc78 0x44120044 +0xc78 0x46130044 //-40 46 +0xc78 0x4a140044 +0xc78 0x4e150044 +0xc78 0x50160044 //-30 50 +0xc78 0x55170044 +0xc78 0x5a180044 //-20 5a +0xc78 0x5e190044 +0xc78 0x641A0044 //-10 64 +0xc78 0x6e1B0044 //0 6e +0xc78 0x6e1C0044 +0xc78 0x6e1D0044 +0xc78 0x6e1E0044 +0xc78 0x6e1F0044 +// RSSI TABLE_2 +//0xc78 0x32000088 +//0xc78 0x32010088 +//0xc78 0x32020088 +//0xc78 0x32030088 +//0xc78 0x32040088 +//0xc78 0x32050088 +//0xc78 0x38060088 +//0xc78 0x38070088 +//0xc78 0x38080088 +//0xc78 0x40090088 +//0xc78 0x460a0088 +//0xc78 0x4a0b0088 +//0xc78 0x4e0c0088 +//0xc78 0x540d0088 +//0xc78 0x560e0088 +//0xc78 0x580f0088 +//0xc78 0x5c100088 +//0xc78 0x64110088 +//0xc78 0x6a120088 +//0xc78 0x6e130088 +//0xc78 0x6e140088 +//0xc78 0x6e150088 +//0xc78 0x6e160088 +//0xc78 0x6e170088 +//0xc78 0x6e180088 +//0xc78 0x6e190088 +//0xc78 0x6e1A0088 +//0xc78 0x6e1B0088 +//0xc78 0x6e1C0088 +//0xc78 0x6e1D0088 +//0xc78 0x6e1E0088 +//0xc78 0x6e1F0088 +//// RSSI TABLE_3 +//0xc78 0x320000d0 +//0xc78 0x320100d0 +//0xc78 0x320200d0 +//0xc78 0x320300d0 +//0xc78 0x320400d0 +//0xc78 0x320500d0 +//0xc78 0x380600d0 +//0xc78 0x380700d0 +//0xc78 0x380800d0 +//0xc78 0x400900d0 +//0xc78 0x460a00d0 +//0xc78 0x4a0b00d0 +//0xc78 0x4e0c00d0 +//0xc78 0x540d00d0 +//0xc78 0x560e00d0 +//0xc78 0x580f00d0 +//0xc78 0x5c1000d0 +//0xc78 0x641100d0 +//0xc78 0x6a1200d0 +//0xc78 0x6e1300d0 +//0xc78 0x6e1400d0 +//0xc78 0x6e1500d0 +//0xc78 0x6e1600d0 +//0xc78 0x6e1700d0 +//0xc78 0x6e1800d0 +//0xc78 0x6e1900d0 +//0xc78 0x6e1A00d0 +//0xc78 0x6e1B00d0 +//0xc78 0x6e1C00d0 +//0xc78 0x6e1D00d0 +//0xc78 0x6e1E00d0 +//0xc78 0x6e1F00d0 +// disable all AGC& RSSI table select +0xc78 0x6e1f0000 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/MACPHY_REG.txt b/package/kernel/rtl8192cd/data_92d/MACPHY_REG.txt index 35d95b765c8..19d0f6ea774 100644 --- a/package/kernel/rtl8192cd/data_92d/MACPHY_REG.txt +++ b/package/kernel/rtl8192cd/data_92d/MACPHY_REG.txt @@ -1,111 +1,111 @@ -//version 04 modify: -//1. set Reg0x605 0x80, -// Reg0x605[7]: Use phytxend_ps to reset mactx state machine - - -//TX and RX packet buffer init, this is done before MAC TRX register init, the following -// register setting is done in Power on flow - -//0x200 0x29 //RQPN -//0x201 0x29 -//0x202 0xA3 -//0x203 0x80 -//0x10C 0x71 // for normal chip setting -//0x10D 0xF7 //HPQ_SEL mapping for Normal chip -//0x114 0xF6 //TXRKTBUG_PG_BNDY -//0x209 0xF6 //Beacon Head Page -//0x115 0x00 -//0x116 0xFF -//0x117 0x27 -//0x424 0xF6 //BCNQ_PGBNDY -//0x45D 0xF6 //WMAC_LBK_BF_HD -//0x60F 0x04 //enable PHY status RCR[28] = 1, 0x60F = 0x04 - -//EDCA and WMAC related -0x420 0x80 //0x420[7] = 1 BK_AMPDU_RTY_NEW -0x423 0x00 -0x430 0x00 //DARFRC, AS 92S -0x431 0x00 -0x432 0x00 -0x433 0x01 -0x434 0x04 //DARFRC, AS 92S -0x435 0x05 -0x436 0x06 -0x437 0x07 -0x438 0x00 //RARFRC, AS 92S -0x439 0x00 -0x43A 0x00 -0x43B 0x01 -0x43C 0x04 //RARFRC, AS 92S -0x43D 0x05 -0x43E 0x06 -0x43F 0x07 -//0x440 0x5D //RRSR -0x441 0x01 -0x442 0x00 -0x444 0x15 // -0x445 0xF0 -0x446 0x0F -0x447 0x00 -//0x458 0x41 //AGG_LMT -//0x459 0xa8 //a8 -//0x45A 0x72 //82 -//0x45B 0xb9 //b9 -//0x460 0x66 //DMDP /SMSP different -//0x461 0x66 //DMDP /SMSP different -0x462 0x08 -0x463 0x03 -0x4C8 0xff //PROT_MODE_CTRL need tuning -0x4C9 0x08 -0x4CC 0xff //Disable BAR retry need tuning -0x4CD 0xff -0x4CE 0x01 -0x500 0x26 //VO EDCA -0x501 0xA2 -0x502 0x2f -0x503 0x00 -0x504 0x28 //VI EDCA -0x505 0xA3 -0x506 0x5E -0x507 0x00 -0x508 0x2B //BE -0x509 0xA4 -0x50A 0x5E -0x50B 0x00 -0x50c 0x4f //BK EDCA -0x50D 0xA4 -0x50E 0x00 -0x50F 0x00 -0x512 0x1C //PIFS -0x514 0x0a -0x515 0x10 -0x516 0x0a -0x517 0x10 -0x51A 0x16 //AGGR_BK_TIME -0x524 0x0F -0x525 0x4F //disable CFE -0x546 0x40 //NAC_PROT_LEN -0x547 0x00 -0x550 0x10 // disable auto sync, and initially disable all beacon function, disable beacon update -0x551 0x10 -0x559 0x02 //BCNDMATIM -0x55A 0x02 //ATIMWND -0x55D 0xFF //disable BCN MAX threshold -0x605 0x80 -0x608 0x0E //RCR -0x609 0x2A //RCR+1 -0x652 0xC8 // enable NAV update upper bound -0x63C 0x08 -0x63D 0x08 -0x63E 0x0C -0x63F 0x0C -0x66E 0x05 // RX BAR IOT issue for Atheros NIC, where atheros BAR has bus -0x700 0x21 -0x701 0x43 -0x702 0x65 -0x703 0x87 -0x708 0x21 -0x709 0x43 -0x70a 0x65 -0x70b 0x87 - +//version 04 modify: +//1. set Reg0x605 0x80, +// Reg0x605[7]: Use phytxend_ps to reset mactx state machine + + +//TX and RX packet buffer init, this is done before MAC TRX register init, the following +// register setting is done in Power on flow + +//0x200 0x29 //RQPN +//0x201 0x29 +//0x202 0xA3 +//0x203 0x80 +//0x10C 0x71 // for normal chip setting +//0x10D 0xF7 //HPQ_SEL mapping for Normal chip +//0x114 0xF6 //TXRKTBUG_PG_BNDY +//0x209 0xF6 //Beacon Head Page +//0x115 0x00 +//0x116 0xFF +//0x117 0x27 +//0x424 0xF6 //BCNQ_PGBNDY +//0x45D 0xF6 //WMAC_LBK_BF_HD +//0x60F 0x04 //enable PHY status RCR[28] = 1, 0x60F = 0x04 + +//EDCA and WMAC related +0x420 0x80 //0x420[7] = 1 BK_AMPDU_RTY_NEW +0x423 0x00 +0x430 0x00 //DARFRC, AS 92S +0x431 0x00 +0x432 0x00 +0x433 0x01 +0x434 0x04 //DARFRC, AS 92S +0x435 0x05 +0x436 0x06 +0x437 0x07 +0x438 0x00 //RARFRC, AS 92S +0x439 0x00 +0x43A 0x00 +0x43B 0x01 +0x43C 0x04 //RARFRC, AS 92S +0x43D 0x05 +0x43E 0x06 +0x43F 0x07 +//0x440 0x5D //RRSR +0x441 0x01 +0x442 0x00 +0x444 0x15 // +0x445 0xF0 +0x446 0x0F +0x447 0x00 +//0x458 0x41 //AGG_LMT +//0x459 0xa8 //a8 +//0x45A 0x72 //82 +//0x45B 0xb9 //b9 +//0x460 0x66 //DMDP /SMSP different +//0x461 0x66 //DMDP /SMSP different +0x462 0x08 +0x463 0x03 +0x4C8 0xff //PROT_MODE_CTRL need tuning +0x4C9 0x08 +0x4CC 0xff //Disable BAR retry need tuning +0x4CD 0xff +0x4CE 0x01 +0x500 0x26 //VO EDCA +0x501 0xA2 +0x502 0x2f +0x503 0x00 +0x504 0x28 //VI EDCA +0x505 0xA3 +0x506 0x5E +0x507 0x00 +0x508 0x2B //BE +0x509 0xA4 +0x50A 0x5E +0x50B 0x00 +0x50c 0x4f //BK EDCA +0x50D 0xA4 +0x50E 0x00 +0x50F 0x00 +0x512 0x1C //PIFS +0x514 0x0a +0x515 0x10 +0x516 0x0a +0x517 0x10 +0x51A 0x16 //AGGR_BK_TIME +0x524 0x0F +0x525 0x4F //disable CFE +0x546 0x40 //NAC_PROT_LEN +0x547 0x00 +0x550 0x10 // disable auto sync, and initially disable all beacon function, disable beacon update +0x551 0x10 +0x559 0x02 //BCNDMATIM +0x55A 0x02 //ATIMWND +0x55D 0xFF //disable BCN MAX threshold +0x605 0x80 +0x608 0x0E //RCR +0x609 0x2A //RCR+1 +0x652 0xC8 // enable NAV update upper bound +0x63C 0x08 +0x63D 0x08 +0x63E 0x0C +0x63F 0x0C +0x66E 0x05 // RX BAR IOT issue for Atheros NIC, where atheros BAR has bus +0x700 0x21 +0x701 0x43 +0x702 0x65 +0x703 0x87 +0x708 0x21 +0x709 0x43 +0x70a 0x65 +0x70b 0x87 + diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_MP_n.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_MP_n.txt index 83c510bc1b3..89d9aa42533 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_MP_n.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_MP_n.txt @@ -1,9 +1,9 @@ -//Release version: RTL8192D.0.0222.2013 -0xc64 0x5116848b // L1-DC_TH for sensitivity -0xc30 0x69e9ac4a //RX false alarm issue -0xd04 0x80020403 // d04[31:30]=2'b10 for cfo mask threshold -0xd14 0x3333bc53 // d14[4]=1 for cfo mask threshold -0X840 0X03cff456 //MP RX sensitivity improvement -0x844 0x03cff456 //MP RX sensitivity improvement -0xc04 0x03a07633 //Rx OFDM54M high max input power improvement +//Release version: RTL8192D.0.0222.2013 +0xc64 0x5116848b // L1-DC_TH for sensitivity +0xc30 0x69e9ac4a //RX false alarm issue +0xd04 0x80020403 // d04[31:30]=2'b10 for cfo mask threshold +0xd14 0x3333bc53 // d14[4]=1 for cfo mask threshold +0X840 0X03cff456 //MP RX sensitivity improvement +0x844 0x03cff456 //MP RX sensitivity improvement +0xc04 0x03a07633 //Rx OFDM54M high max input power improvement 0xff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG.txt index a965555aac7..9721538b8cd 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG.txt @@ -1,287 +1,287 @@ -//========================= -// PHY_related MAC register by channel, -// Related from willis 090406 PHY_REG_PG.txt for 92D -//========================= - -//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// USB_POWER_SUPPORT use this table ONLY! -// For Ant A -0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - - -//========================= 11a mode -//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -0xff //end of file +//========================= +// PHY_related MAC register by channel, +// Related from willis 090406 PHY_REG_PG.txt for 92D +//========================= + +//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// USB_POWER_SUPPORT use this table ONLY! +// For Ant A +0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + + +//========================= 11a mode +//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +0xff //end of file diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt index f610a173d07..3951fe008cb 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt @@ -1,287 +1,287 @@ -//========================= -// PHY_related MAC register by channel, -// Related from willis 090406 PHY_REG_PG.txt for 92D -//========================= - -//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// USB_POWER_SUPPORT use this table ONLY! -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - - -//========================= 11a mode -//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -0xff //end of file +//========================= +// PHY_related MAC register by channel, +// Related from willis 090406 PHY_REG_PG.txt for 92D +//========================= + +//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// USB_POWER_SUPPORT use this table ONLY! +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + + +//========================= 11a mode +//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +0xff //end of file diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_CE.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_CE.txt index a965555aac7..9721538b8cd 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_CE.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_CE.txt @@ -1,287 +1,287 @@ -//========================= -// PHY_related MAC register by channel, -// Related from willis 090406 PHY_REG_PG.txt for 92D -//========================= - -//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// USB_POWER_SUPPORT use this table ONLY! -// For Ant A -0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - - -//========================= 11a mode -//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -0xff //end of file +//========================= +// PHY_related MAC register by channel, +// Related from willis 090406 PHY_REG_PG.txt for 92D +//========================= + +//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// USB_POWER_SUPPORT use this table ONLY! +// For Ant A +0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + + +//========================= 11a mode +//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +0xff //end of file diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_FCC.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_FCC.txt index a965555aac7..9721538b8cd 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_FCC.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_PG_FCC.txt @@ -1,287 +1,287 @@ -//========================= -// PHY_related MAC register by channel, -// Related from willis 090406 PHY_REG_PG.txt for 92D -//========================= - -//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) -// USB_POWER_SUPPORT use this table ONLY! -// For Ant A -0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) -// For Ant A -0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - -//========================= -// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) -// For Ant_A -0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - -//========================= -// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) -// For Ant_A -0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M -0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M -0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 -// For Ant_B -0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M -0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M -0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M -0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M -0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 -0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - - -//========================= 11a mode -//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -//========================= 11a mode -//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) -// For Ant A -0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M -0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M -0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB -0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB -0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 -0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 -0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 -0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 -// For Ant B -0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M -0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M -0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB -0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB -0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 -0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 -0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 -0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 - - -0xff //end of file +//========================= +// PHY_related MAC register by channel, +// Related from willis 090406 PHY_REG_PG.txt for 92D +//========================= + +//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel) +// USB_POWER_SUPPORT use this table ONLY! +// For Ant A +0xe00 0xffffffff 0x07090c0c // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x01020405 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x000000 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x00 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x0b0c0c0e // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x01030506 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x0b0c0d0e // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x01030509 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x07090c0c // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x01020405 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x0b0c0c0e // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x01030506 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x0b0c0d0e // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x01030509 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x06060606 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00020406 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x06060606 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00020406 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14) +// For Ant A +0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + +//========================= +// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09) +// For Ant_A +0xe00 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a //for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x04040404 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + +//========================= +// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14) +// For Ant_A +0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M +0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M +0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 +// For Ant_B +0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M +0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M +0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M +0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M +0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00 +0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + + +//========================= 11a mode +//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +//========================= 11a mode +//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163) +// For Ant A +0xe00 0xffffffff 0x04040404 // base on 0x30 //for 18M,12M,09M,06M +0xe04 0xffffffff 0x00020204 // base on 0x30 //for 54M,48M,36M,24M +0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB +0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB +0xe10 0xffffffff 0x08080808 // base on 0x30 //for MCS=03,02,01,00 +0xe14 0xffffffff 0x00040408 // base on 0x30 //for MCS=07,06,05,04 +0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08 +0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12 +// For Ant B +0x830 0xffffffff 0x04040404 // base on 0x32 //for 18M,12M,09M,06M +0x834 0xffffffff 0x00020204 // base on 0x32 //for 54M,48M,36M,24M +0x838 0xffffff00 0x00 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB +0x86c 0x000000ff 0x000000 // base on 0x34 //for CCK 11M, use 17dB +0x83c 0xffffffff 0x08080808 // base on 0x32 //for MCS=03,02,01,00 +0x848 0xffffffff 0x00040408 // base on 0x32 //for MCS=07,06,05,04 +0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08 +0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12 + + +0xff //end of file diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_n.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_n.txt index b27816d2bbe..a047a879461 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_n.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_n.txt @@ -1,221 +1,221 @@ -//Release version: RTL8192D.0.0206.2012 -//0x024 0x0011800d //syn CLK enable, Xtal_bsel=nand -//0x028 0x00ffdb83 //320MHz CLK enable -//0x014 0x088ba955 //SPS=1.537V -//0x010 0x49022b03 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390004 -0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60250 //88CE default left anatenna -0x864 0x061f0150 -0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22188000 //AD3 must be off for 92D testchip -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x0001fff8 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x00000cd5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c // CCK 1T for power saving -0xa08 0x8c8a8300 // -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x1a1b0000 -0xa24 0x090e1317 -0xa28 0x00000204 -0xa2c 0x00d30000 -0xa70 0x101fff00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x40071d40 // initial gain @ CCA negedge -0xc04 0x03a05633 -0xc08 0x001000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652af -0xc38 0x49795994 -0xc3c 0x0a979718 -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc009e -0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c00a8 -0xc60 0x00000000 // DTR TH -0xc64 0x7112848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x258610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x40b95612 // enable ht rxhp -0xc80 0x40000100 -0xc84 0x20f60000 -0xc88 0x40000100 -0xc8c 0xa0e40000 -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000007 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b11e20 // DFS -0xcdc 0xe0767533 // DFS -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608404 -0xd38 0x00000000 -0xd3c 0x00027353 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 //AFE ctrl reg (ASIC) Ultra low power -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c126da4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf1c 0x64 // Pkt Interval = 100us -0xf4c 0x00000004 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//Release version: RTL8192D.0.0206.2012 +//0x024 0x0011800d //syn CLK enable, Xtal_bsel=nand +//0x028 0x00ffdb83 //320MHz CLK enable +//0x014 0x088ba955 //SPS=1.537V +//0x010 0x49022b03 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390004 +0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60250 //88CE default left anatenna +0x864 0x061f0150 +0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22188000 //AD3 must be off for 92D testchip +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x0001fff8 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x00000cd5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c // CCK 1T for power saving +0xa08 0x8c8a8300 // +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x1a1b0000 +0xa24 0x090e1317 +0xa28 0x00000204 +0xa2c 0x00d30000 +0xa70 0x101fff00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x40071d40 // initial gain @ CCA negedge +0xc04 0x03a05633 +0xc08 0x001000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652af +0xc38 0x49795994 +0xc3c 0x0a979718 +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x43bc009e +0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c00a8 +0xc60 0x00000000 // DTR TH +0xc64 0x7112848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x258610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x40b95612 // enable ht rxhp +0xc80 0x40000100 +0xc84 0x20f60000 +0xc88 0x40000100 +0xc8c 0xa0e40000 +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000007 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b11e20 // DFS +0xcdc 0xe0767533 // DFS +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608404 +0xd38 0x00000000 +0xd3c 0x00027353 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 //AFE ctrl reg (ASIC) Ultra low power +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c126da4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf1c 0x64 // Pkt Interval = 100us +0xf4c 0x00000004 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt index 81e6b1ea008..1bf414cc584 100644 --- a/package/kernel/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt @@ -1,222 +1,222 @@ -//Release version: RTL8192D.0.1006.2011 -//100909 -//0x024 0x0011800d //syn CLK enable, Xtal_bsel=nand -//0x028 0x00ffdb83 //320MHz CLK enable -//0x014 0x088ba955 //SPS=1.537V -//0x010 0x49022b03 -//======================= -// PAGE_8 ( FPGA_PHY0 ) -//======================= -0x800 0x80040002 // turn off RF when 1R CCA -0x804 0x00000003 -0x808 0x0000fc00 -0x80c 0x0000000A -0x810 0x10001331 -0x814 0x020c3d10 -0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 -0x81c 0x00000000 -0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x824 0x00390004 -0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) -0x82c 0x00390004 -0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M -0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M -0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M -0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0x840 0x00010000 //RF to standby mode -0x844 0x00010000 //RF to standby mode -0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0x850 0x00000000 // RF wakeup, TBD -0x854 0x00000000 // RF sleep, TBD -0x858 0x569a569a -0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode -0x860 0x66e60250 //88CE default left anatenna -0x864 0x061f0150 -0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword -0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) -0x874 0x22188000 //AD3 must be off for 92D testchip -0x878 0x08080808 // RF mode for standby & rx_low_power codeword -0x87c 0x0001fff8 // TST mode -0x880 0xc0083070 // AFE ctrl reg (ASIC) -0x884 0x00000cd5 // AFE ctrl reg (ASIC) -0x888 0x00000000 // AFE ctrl reg (ASIC) -0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND -0x890 0x00000800 -0x894 0xfffffffe -0x898 0x40302010 -0x89c 0x00706050 -// -//======================= -// PAGE_9 ( FPGA_PHY1 ) -//======================= -0x900 0x00000000 -0x904 0x00000023 -0x908 0x00000000 -0x90c 0x81121313 // tx antenna by contorl register -// -//======================= -// PAGE_A ( CCK_PHY0 ) -//======================= -0xa00 0x00d047c8 -0xa04 0x80ff000c // CCK 1T for power saving -0xa08 0x8c8a8300 // -0xa0c 0x2e68120f -0xa10 0x9500bb78 // -0xa14 0x11144028 -0xa18 0x00881117 -0xa1c 0x89140f00 -0xa20 0x15160000 //Arthur-power tracking for high-power -0xa24 0x070b0f12 //Arthur-power tracking for high-power -0xa28 0x00000104 //Arthur-power tracking for high-power -0xa2c 0x00d30000 -0xa70 0x101fbf00 -0xa74 0x00000007 -// -//======================= -// PAGE_B -//======================= -// -// -//======================= -// PAGE_C ( OFDM_PHY0 ) -//======================= -0xc00 0x40071d40 // initial gain @ CCA negedge -0xc04 0x03a05633 -0xc08 0x001000e4 // [8:4] is about DBG_GPIO selection -0xc0c 0x6c6c6c6c -0xc10 0x08800000 -0xc14 0x40000100 -0xc18 0x08800000 -0xc1c 0x40000100 -0xc20 0x00000000 // DTR TH -0xc24 0x00000000 // DTR TH -0xc28 0x00000000 // DTR TH -0xc2c 0x00000000 // DTR TH -0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 -0xc34 0x469652cf -0xc38 0x49795994 -0xc3c 0x0a979718 -0xc40 0x1f7c403f -0xc44 0x000100b7 -0xc48 0xec020107 //[1]=1:enable L1_SBD -0xc4c 0x007f037f // turn off edcca -0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc54 0x43bc009e -0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 -0xc5c 0x433c00a8 -0xc60 0x00000000 // DTR TH -0xc64 0x7116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b -0xc68 0x47c00bff //L1-SBD -0xc6c 0x00000036 //L1-SBD -0xc70 0x2c7f000d // disable AGC flow-1 -0xc74 0x258610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b -0xc78 0x0000001f -0xc7c 0x40b95612 // enable ht rxhp -0xc80 0x24000090 //2011.11.16 Arthur-power tracking for high-power -0xc84 0x20f60000 -0xc88 0x24000090 //2011.11.16 Arthur-power tracking for high-power -0xc8c 0xa0e40000 -0xc90 0x00121820 // TX Power Training for path-A -0xc94 0x00000007 -0xc98 0x00121820// TX Power Training for path-B -0xc9c 0x00007f7f // turn off pre-cca -0xca0 0x00000000 -0xca4 0x00000080 // reserved -0xca8 0x00000000 // reserved -0xcac 0x00000000 // reserved -0xcb0 0x00000000 // reserved -0xcb4 0x00000000 // reserved -0xcb8 0x00000000 // reserved -0xcbc 0x28000000 -0xcc0 0x00000000 // reserved -0xcc4 0x00000000 // reserved -0xcc8 0x00000000 // reserved -0xccc 0x00000000 // reserved -0xcd0 0x00000000 // reserved -0xcd4 0x00000000 // reserved -0xcd8 0x64b11e20 // DFS -0xcdc 0xe0767533 // DFS -0xce0 0x00222222 -0xce4 0x00000000 -0xce8 0x37644302 -0xcec 0x2f97d40c -// -//======================= -// PAGE_D ( OFDM_PHY1 ) -//======================= -0xd00 0x00080740 -0xd04 0x00020403 -0xd08 0x0000907f -0xd0c 0x20010201 -0xd10 0xa0633333 -0xd14 0x3333bc43 -0xd18 0x7a8f5b6b -0xd2c 0xcc979975 -0xd30 0x00000000 -0xd34 0x80608404 -0xd38 0x00000000 -0xd3c 0x00027353 -0xd40 0x00000000 -0xd44 0x00000000 -0xd48 0x00000000 -0xd4c 0x00000000 -0xd50 0x6437140a -0xd54 0x00000000 -0xd58 0x00000000 -0xd5c 0x30032064 -0xd60 0x4653de68 -0xd64 0x04518a3c //[26]=1:enable L1-SBD// -0xd68 0x00002101 -0xd6c 0x2a201c16 // DTR -0xd70 0x1812362e // DTR -0xd74 0x322c2220 // DTR -0xd78 0x000e3c24 // DTR -//======================= -// PAGE_E -//======================= -0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M -0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M -0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M -0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 -0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 -0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 -0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 -0xe28 0x00000000 -0xe30 0x1000dc1f // 0xe30~0xe60: IQK -0xe34 0x10008c1f -0xe38 0x02140102 -0xe3C 0x681604c2 -0xe40 0x01007c00 -0xe44 0x01004800 -0xe48 0xfb000000 -0xe4c 0x000028d1 -0xe50 0x1000dc1f -0xe54 0x10008c1f -0xe58 0x02140102 -0xe5C 0x28160d05 -0xe60 0x00000010 -//0xe64 0x281600a0 // Reserved in 92C/88C -0xe68 0x001b25a4 //AFE ctrl reg (ASIC) Ultra low power -0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth -0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA -0xe74 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_RFON -0xe78 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_BBON -0xe7c 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_RFON -0xe80 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_BBON -0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX -0xe88 0x0c126da4 // AFE ctrl reg (ASIC) TX_TO_TX -0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK -0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM -0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS -0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX -0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby -0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep -0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN -// -0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG -0xf1c 0x64 // Pkt Interval = 100us -0xf4c 0x00000004 // Only for FPGA PMAC -0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb -0xff +//Release version: RTL8192D.0.1006.2011 +//100909 +//0x024 0x0011800d //syn CLK enable, Xtal_bsel=nand +//0x028 0x00ffdb83 //320MHz CLK enable +//0x014 0x088ba955 //SPS=1.537V +//0x010 0x49022b03 +//======================= +// PAGE_8 ( FPGA_PHY0 ) +//======================= +0x800 0x80040002 // turn off RF when 1R CCA +0x804 0x00000003 +0x808 0x0000fc00 +0x80c 0x0000000A +0x810 0x10001331 +0x814 0x020c3d10 +0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385 +0x81c 0x00000000 +0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x824 0x00390004 +0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI) +0x82c 0x00390004 +0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M +0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M +0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M +0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0x840 0x00010000 //RF to standby mode +0x844 0x00010000 //RF to standby mode +0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0x850 0x00000000 // RF wakeup, TBD +0x854 0x00000000 // RF sleep, TBD +0x858 0x569a569a +0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode +0x860 0x66e60250 //88CE default left anatenna +0x864 0x061f0150 +0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword +0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA) +0x874 0x22188000 //AD3 must be off for 92D testchip +0x878 0x08080808 // RF mode for standby & rx_low_power codeword +0x87c 0x0001fff8 // TST mode +0x880 0xc0083070 // AFE ctrl reg (ASIC) +0x884 0x00000cd5 // AFE ctrl reg (ASIC) +0x888 0x00000000 // AFE ctrl reg (ASIC) +0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND +0x890 0x00000800 +0x894 0xfffffffe +0x898 0x40302010 +0x89c 0x00706050 +// +//======================= +// PAGE_9 ( FPGA_PHY1 ) +//======================= +0x900 0x00000000 +0x904 0x00000023 +0x908 0x00000000 +0x90c 0x81121313 // tx antenna by contorl register +// +//======================= +// PAGE_A ( CCK_PHY0 ) +//======================= +0xa00 0x00d047c8 +0xa04 0x80ff000c // CCK 1T for power saving +0xa08 0x8c8a8300 // +0xa0c 0x2e68120f +0xa10 0x9500bb78 // +0xa14 0x11144028 +0xa18 0x00881117 +0xa1c 0x89140f00 +0xa20 0x15160000 //Arthur-power tracking for high-power +0xa24 0x070b0f12 //Arthur-power tracking for high-power +0xa28 0x00000104 //Arthur-power tracking for high-power +0xa2c 0x00d30000 +0xa70 0x101fbf00 +0xa74 0x00000007 +// +//======================= +// PAGE_B +//======================= +// +// +//======================= +// PAGE_C ( OFDM_PHY0 ) +//======================= +0xc00 0x40071d40 // initial gain @ CCA negedge +0xc04 0x03a05633 +0xc08 0x001000e4 // [8:4] is about DBG_GPIO selection +0xc0c 0x6c6c6c6c +0xc10 0x08800000 +0xc14 0x40000100 +0xc18 0x08800000 +0xc1c 0x40000100 +0xc20 0x00000000 // DTR TH +0xc24 0x00000000 // DTR TH +0xc28 0x00000000 // DTR TH +0xc2c 0x00000000 // DTR TH +0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44 +0xc34 0x469652cf +0xc38 0x49795994 +0xc3c 0x0a979718 +0xc40 0x1f7c403f +0xc44 0x000100b7 +0xc48 0xec020107 //[1]=1:enable L1_SBD +0xc4c 0x007f037f // turn off edcca +0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc54 0x43bc009e +0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 +0xc5c 0x433c00a8 +0xc60 0x00000000 // DTR TH +0xc64 0x7116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b +0xc68 0x47c00bff //L1-SBD +0xc6c 0x00000036 //L1-SBD +0xc70 0x2c7f000d // disable AGC flow-1 +0xc74 0x258610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b +0xc78 0x0000001f +0xc7c 0x40b95612 // enable ht rxhp +0xc80 0x24000090 //2011.11.16 Arthur-power tracking for high-power +0xc84 0x20f60000 +0xc88 0x24000090 //2011.11.16 Arthur-power tracking for high-power +0xc8c 0xa0e40000 +0xc90 0x00121820 // TX Power Training for path-A +0xc94 0x00000007 +0xc98 0x00121820// TX Power Training for path-B +0xc9c 0x00007f7f // turn off pre-cca +0xca0 0x00000000 +0xca4 0x00000080 // reserved +0xca8 0x00000000 // reserved +0xcac 0x00000000 // reserved +0xcb0 0x00000000 // reserved +0xcb4 0x00000000 // reserved +0xcb8 0x00000000 // reserved +0xcbc 0x28000000 +0xcc0 0x00000000 // reserved +0xcc4 0x00000000 // reserved +0xcc8 0x00000000 // reserved +0xccc 0x00000000 // reserved +0xcd0 0x00000000 // reserved +0xcd4 0x00000000 // reserved +0xcd8 0x64b11e20 // DFS +0xcdc 0xe0767533 // DFS +0xce0 0x00222222 +0xce4 0x00000000 +0xce8 0x37644302 +0xcec 0x2f97d40c +// +//======================= +// PAGE_D ( OFDM_PHY1 ) +//======================= +0xd00 0x00080740 +0xd04 0x00020403 +0xd08 0x0000907f +0xd0c 0x20010201 +0xd10 0xa0633333 +0xd14 0x3333bc43 +0xd18 0x7a8f5b6b +0xd2c 0xcc979975 +0xd30 0x00000000 +0xd34 0x80608404 +0xd38 0x00000000 +0xd3c 0x00027353 +0xd40 0x00000000 +0xd44 0x00000000 +0xd48 0x00000000 +0xd4c 0x00000000 +0xd50 0x6437140a +0xd54 0x00000000 +0xd58 0x00000000 +0xd5c 0x30032064 +0xd60 0x4653de68 +0xd64 0x04518a3c //[26]=1:enable L1-SBD// +0xd68 0x00002101 +0xd6c 0x2a201c16 // DTR +0xd70 0x1812362e // DTR +0xd74 0x322c2220 // DTR +0xd78 0x000e3c24 // DTR +//======================= +// PAGE_E +//======================= +0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M +0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M +0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M +0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 +0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 +0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 +0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 +0xe28 0x00000000 +0xe30 0x1000dc1f // 0xe30~0xe60: IQK +0xe34 0x10008c1f +0xe38 0x02140102 +0xe3C 0x681604c2 +0xe40 0x01007c00 +0xe44 0x01004800 +0xe48 0xfb000000 +0xe4c 0x000028d1 +0xe50 0x1000dc1f +0xe54 0x10008c1f +0xe58 0x02140102 +0xe5C 0x28160d05 +0xe60 0x00000010 +//0xe64 0x281600a0 // Reserved in 92C/88C +0xe68 0x001b25a4 //AFE ctrl reg (ASIC) Ultra low power +0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth +0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA +0xe74 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_RFON +0xe78 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_BBON +0xe7c 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_RFON +0xe80 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_BBON +0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX +0xe88 0x0c126da4 // AFE ctrl reg (ASIC) TX_TO_TX +0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK +0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM +0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS +0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX +0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby +0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep +0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN +// +0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG +0xf1c 0x64 // Pkt Interval = 100us +0xf4c 0x00000004 // Only for FPGA PMAC +0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb +0xff diff --git a/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt b/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt index 54fb34af9cf..28fea6b8525 100644 --- a/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt +++ b/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 2G PathA&B =============== - -2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 2 4 7 8 10 11 15 17 19 21 23 -5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18 -5GLB_P 2 4 7 8 10 11 15 17 19 21 23 -5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 2 4 5 7 9 13 15 19 21 22 23 -5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20 -5GMB_P 2 4 5 7 9 13 15 19 21 22 23 -5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 2 4 6 8 10 14 16 19 21 22 24 -5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21 -5GHB_P 3 5 7 9 11 13 17 19 21 22 23 -5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 2G PathA&B =============== + +2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 2 4 7 8 10 11 15 17 19 21 23 +5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18 +5GLB_P 2 4 7 8 10 11 15 17 19 21 23 +5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 2 4 5 7 9 13 15 19 21 22 23 +5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20 +5GMB_P 2 4 5 7 9 13 15 19 21 22 23 +5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 2 4 6 8 10 14 16 19 21 22 24 +5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21 +5GHB_P 3 5 7 9 11 13 17 19 21 22 23 +5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19 + + diff --git a/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt index 54fb34af9cf..28fea6b8525 100644 --- a/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt @@ -1,40 +1,40 @@ - -// , refer to thermal delta value between read and PG. -// , refer to thermal delta value between read and PG. - -//============== 2G CCK PathA&B =============== - -2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 2G PathA&B =============== - -2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 -2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 -2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 -2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 - -//============== 5GL PathA&B =============== -// 5G bane1&2 -5GLA_P 2 4 7 8 10 11 15 17 19 21 23 -5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18 -5GLB_P 2 4 7 8 10 11 15 17 19 21 23 -5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17 - -//============== 5GM PathA&B =============== -// 5G bane3 -5GMA_P 2 4 5 7 9 13 15 19 21 22 23 -5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20 -5GMB_P 2 4 5 7 9 13 15 19 21 22 23 -5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19 - -//============== 5GH PathA&B =============== -// 5G bane4 -5GHA_P 2 4 6 8 10 14 16 19 21 22 24 -5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21 -5GHB_P 3 5 7 9 11 13 17 19 21 22 23 -5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19 - - + +// , refer to thermal delta value between read and PG. +// , refer to thermal delta value between read and PG. + +//============== 2G CCK PathA&B =============== + +2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 2G PathA&B =============== + +2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22 +2GA_N 1 3 4 6 7 9 10 12 13 15 16 18 +2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23 +2GB_N 1 3 4 6 7 9 10 12 13 15 16 18 + +//============== 5GL PathA&B =============== +// 5G bane1&2 +5GLA_P 2 4 7 8 10 11 15 17 19 21 23 +5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18 +5GLB_P 2 4 7 8 10 11 15 17 19 21 23 +5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17 + +//============== 5GM PathA&B =============== +// 5G bane3 +5GMA_P 2 4 5 7 9 13 15 19 21 22 23 +5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20 +5GMB_P 2 4 5 7 9 13 15 19 21 22 23 +5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19 + +//============== 5GH PathA&B =============== +// 5G bane4 +5GHA_P 2 4 6 8 10 14 16 19 21 22 24 +5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21 +5GHB_P 3 5 7 9 11 13 17 19 21 22 23 +5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19 + + diff --git a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d.txt b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d.txt index 5851a7ce42f..ef000ed8966 100644 --- a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d.txt +++ b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d.txt @@ -1,75 +1,75 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: FCC, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1 17 17// band edge -11 17 17// band edge - - -//=========================================== -// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 15.5 15// band edge -11 13.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: FCC, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 15.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: FCC, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 15 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: FCC, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: FCC, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: FCC, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1 17 17// band edge +11 17 17// band edge + + +//=========================================== +// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 15.5 15// band edge +11 13.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: FCC, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 15.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: FCC, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 15 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: FCC, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: FCC, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_1.txt b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_1.txt index 5851a7ce42f..ef000ed8966 100644 --- a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_1.txt +++ b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_1.txt @@ -1,75 +1,75 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: FCC, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1 17 17// band edge -11 17 17// band edge - - -//=========================================== -// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 15.5 15// band edge -11 13.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: FCC, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 15.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: FCC, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 15 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: FCC, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: FCC, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13.5 13// band edge -9 12.5 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: FCC, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1 17 17// band edge +11 17 17// band edge + + +//=========================================== +// Table 2: FCC, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 15.5 15// band edge +11 13.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: FCC, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 15.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: FCC, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 15 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: FCC, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: FCC, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13.5 13// band edge +9 12.5 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_2.txt b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_2.txt index 47f0a89ffb9..16e996b9460 100644 --- a/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_2.txt +++ b/package/kernel/rtl8192cd/data_92d/TXPWR_LMT_92d_2.txt @@ -1,74 +1,74 @@ -// Tx Power Limit Table - beta 03 -// Format: -// table index-> table -// channel limmit-> channel -// (optional) start:end - -// Note: The order of the tables MUST match the definition -// in WLAN driver. -//=========================================== -// Table 1: CE, CCK (1M,2M,5.5M,11M) -// start from here -table 1 -1:13 16 17// band edge - - -//=========================================== -// Table 2: CE, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) -// start from here -table 2 -1 16.5 15// band edge -13 16.5 15// band edge - -// 5G band 1 & 2 -36 16 15// band edge - -//=========================================== -// Table 3: CE, 20M 1T (MCS0~MCS7) -// start from here -table 3 -1 16 13// band edge -13 16 13// band edge - -// 5G band 1 & 2 -36 15.5 13// band edge - - - -//=========================================== -// Table 4: CE, 20M 2T (MCS8~MCS15) -// start from here -table 4 -1 13 13// band edge -13 13 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - -//=========================================== -// Table 5: CE, 40M 1T (MCS0~MCS7) -// start from here -table 5 -3 13.5 13// band edge -11 13.5 13// band edge - -// 5G band 1 & 2 -38 15.5 13// band edge - - -//=========================================== -// Table 6: CE, 40M 2T (MCS8~MCS15) -// start from here -table 6 -3 13 13// band edge -11 13 13// band edge - -// 5G band 1 & 2 - -// 5G band 3 - - - - +// Tx Power Limit Table - beta 03 +// Format: +// table index-> table +// channel limmit-> channel +// (optional) start:end + +// Note: The order of the tables MUST match the definition +// in WLAN driver. +//=========================================== +// Table 1: CE, CCK (1M,2M,5.5M,11M) +// start from here +table 1 +1:13 16 17// band edge + + +//=========================================== +// Table 2: CE, OFDM (6M,9M,12M,18M,24M,36M,48M,54M) +// start from here +table 2 +1 16.5 15// band edge +13 16.5 15// band edge + +// 5G band 1 & 2 +36 16 15// band edge + +//=========================================== +// Table 3: CE, 20M 1T (MCS0~MCS7) +// start from here +table 3 +1 16 13// band edge +13 16 13// band edge + +// 5G band 1 & 2 +36 15.5 13// band edge + + + +//=========================================== +// Table 4: CE, 20M 2T (MCS8~MCS15) +// start from here +table 4 +1 13 13// band edge +13 13 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + +//=========================================== +// Table 5: CE, 40M 1T (MCS0~MCS7) +// start from here +table 5 +3 13.5 13// band edge +11 13.5 13// band edge + +// 5G band 1 & 2 +38 15.5 13// band edge + + +//=========================================== +// Table 6: CE, 40M 2T (MCS8~MCS15) +// start from here +table 6 +3 13 13// band edge +11 13 13// band edge + +// 5G band 1 & 2 + +// 5G band 3 + + + + diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_intPA.txt b/package/kernel/rtl8192cd/data_92d/radio_a_intPA.txt index a4f7895358a..424aef7f113 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_intPA.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_intPA.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM.txt b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM.txt index 5fa7604b23b..6d8f1803b95 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 //0x1039d //0x10399 -0x13 0x0c3ad //0x0c399 //0x0c38d -0x13 0x081b9 //0x0819d //0x08199 -0x13 0x041ad //0x04199 //0x0418d -0x13 0x000b9 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 //0x1039d //0x10399 +0x13 0x0c3ad //0x0c399 //0x0c38d +0x13 0x081b9 //0x0819d //0x08199 +0x13 0x041ad //0x04199 //0x0418d +0x13 0x000b9 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt index 617a70c2cce..0c62f24f153 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 //0x1039d //0x10399 -0x13 0x0c3ad //0x0c399 //0x0c38d -0x13 0x081b9 //0x0819d //0x08199 -0x13 0x041ad //0x04199 //0x0418d -0x13 0x000b9 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 //0x1039d //0x10399 +0x13 0x0c3ad //0x0c399 //0x0c38d +0x13 0x081b9 //0x0819d //0x08199 +0x13 0x041ad //0x04199 //0x0418d +0x13 0x000b9 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt index 3f72bcd4659..9f08f6b5216 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_new.txt b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_new.txt index 2588184a714..f833065a92c 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_intPA_new.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_intPA_new.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8eb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_n.txt b/package/kernel/rtl8192cd/data_92d/radio_a_n.txt index a13d9ea83c7..29025f2aa13 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_n.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_n.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control -0x48 0xf9c43 -0x49 0x02e0c -0x4a 0x546eb -0x4b 0x8966C -0x4c 0x0dde9 - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GM_channel -0x18 0x37524 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GH_channel -0x18 0x57568 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 // set RF 18[19]=1 for DMSP SYN OFF -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control +0x48 0xf9c43 +0x49 0x02e0c +0x4a 0x546eb +0x4b 0x8966C +0x4c 0x0dde9 + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GM_channel +0x18 0x37524 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GH_channel +0x18 0x57568 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 // set RF 18[19]=1 for DMSP SYN OFF +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_a_n_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/radio_a_n_92d_hp.txt index 1ff0ea88b29..ae0d59868cc 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_a_n_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_a_n_92d_hp.txt @@ -1,244 +1,244 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0xf0000 //HSSI_SYN2_power_control -0x18 0x17524 //channel_band_control -0x19 0x00000 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb //0xfd7eb -0x3b 0x20000 //0xe0000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x04529 //2011.11.16 Arthur 452c intpa 4529 extpa -//5G_PA_control -0x48 0xf9c43 -0x49 0x02e0c -0x4a 0x546eb -0x4b 0x8966C -0x4c 0x0dde9 - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - -//High Power - Arthur - 0627 -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GM_channel -0x18 0x37524 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GH_channel -0x18 0x57568 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x97524 // set RF 18[19]=1 for DMSP SYN OFF -0xfe -0xfe -0xfe -0xfe -0x2b 0x41289 -0xfe -0x2d 0x6aaaa -0x2e 0xb4d01 -0x2d 0x80000 -0x2e 0x04d02 -0x2d 0x95555 -0x2e 0x54d03 -0x2d 0xaaaaa -0x2e 0xb4d04 -0x2d 0xc0000 -0x2e 0x04d05 -0x2d 0xd5555 -0x2e 0x54d06 -0x2d 0xeaaaa -0x2e 0xb4d07 -0x2d 0x00000 -0x2e 0x05108 -0x2d 0x15555 -0x2e 0x55109 -0x2d 0x2aaaa -0x2e 0xb510a -0x2d 0x40000 -0x2e 0x0510b -0x2d 0x55555 -0x2e 0x5510c -//end -//0x18 0x17524 -0xff 0xffff +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0xf0000 //HSSI_SYN2_power_control +0x18 0x17524 //channel_band_control +0x19 0x00000 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb //0xfd7eb +0x3b 0x20000 //0xe0000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x04529 //2011.11.16 Arthur 452c intpa 4529 extpa +//5G_PA_control +0x48 0xf9c43 +0x49 0x02e0c +0x4a 0x546eb +0x4b 0x8966C +0x4c 0x0dde9 + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + +//High Power - Arthur - 0627 +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GM_channel +0x18 0x37524 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GH_channel +0x18 0x57568 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x97524 // set RF 18[19]=1 for DMSP SYN OFF +0xfe +0xfe +0xfe +0xfe +0x2b 0x41289 +0xfe +0x2d 0x6aaaa +0x2e 0xb4d01 +0x2d 0x80000 +0x2e 0x04d02 +0x2d 0x95555 +0x2e 0x54d03 +0x2d 0xaaaaa +0x2e 0xb4d04 +0x2d 0xc0000 +0x2e 0x04d05 +0x2d 0xd5555 +0x2e 0x54d06 +0x2d 0xeaaaa +0x2e 0xb4d07 +0x2d 0x00000 +0x2e 0x05108 +0x2d 0x15555 +0x2e 0x55109 +0x2d 0x2aaaa +0x2e 0xb510a +0x2d 0x40000 +0x2e 0x0510b +0x2d 0x55555 +0x2e 0x5510c +//end +//0x18 0x17524 +0xff 0xffff diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_intPA.txt b/package/kernel/rtl8192cd/data_92d/radio_b_intPA.txt index 45fb4c35a3d..8357888d950 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_intPA.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_intPA.txt @@ -1,247 +1,247 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM.txt b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM.txt index f31e4008bfa..7c721bd907e 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM.txt @@ -1,247 +1,247 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 //0x1039d //0x10399 -0x13 0x0c3ad //0x0c399 //0x0c38d -0x13 0x081b9 //0x0819d //0x08199 -0x13 0x041ad //0x04199 //0x0418d -0x13 0x000b9 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 //0x1039d //0x10399 +0x13 0x0c3ad //0x0c399 //0x0c38d +0x13 0x081b9 //0x0819d //0x08199 +0x13 0x041ad //0x04199 //0x0418d +0x13 0x000b9 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt index 5a9c4e9a341..a07930cbb62 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt @@ -1,247 +1,247 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 -0x13 0x0c3ad -0x13 0x081b9 -0x13 0x041ad -0x13 0x000b9 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x103b9 //0x1039d //0x10399 -0x13 0x0c3ad //0x0c399 //0x0c38d -0x13 0x081b9 //0x0819d //0x08199 -0x13 0x041ad //0x04199 //0x0418d -0x13 0x000b9 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 +0x13 0x0c3ad +0x13 0x081b9 +0x13 0x041ad +0x13 0x000b9 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x103b9 //0x1039d //0x10399 +0x13 0x0c3ad //0x0c399 //0x0c38d +0x13 0x081b9 //0x0819d //0x08199 +0x13 0x041ad //0x04199 //0x0418d +0x13 0x000b9 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt index c530cb8ec55..125efc7a2b1 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt @@ -1,247 +1,247 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power -0x13 0x24fb3 -0x13 0x20fa7 -0x13 0x1cf9b -0x13 0x18f8f -0x13 0x1478f -0x13 0x10692 -0x13 0x0c399 -0x13 0x0838d -0x13 0x04199 -0x13 0x0018d -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power +0x13 0x24fb3 +0x13 0x20fa7 +0x13 0x1cf9b +0x13 0x18f8f +0x13 0x1478f +0x13 0x10692 +0x13 0x0c399 +0x13 0x0838d +0x13 0x04199 +0x13 0x0018d +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_new.txt b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_new.txt index 8d54f7a97ca..dd5aafd66f2 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_intPA_new.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_intPA_new.txt @@ -1,247 +1,247 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control_intPA -0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 -0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 -0x4a 0x50f0f -0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee -0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 -0x13 0x247ab -0x13 0x2079f -0x13 0x1c793 -0x13 0x1839f -0x13 0x14396 -0x13 0x1019e -0x13 0x0c195 -0x13 0x08198 -0x13 0x040a4 -0x13 0x0001c -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GM_channel -0x18 0x37564 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain - -//5GH_channel -0x18 0x57595 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table_intPA -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table_intPA -0x15 0x0f495 -0x15 0x4f495 -0x15 0x8f495 -//5G_TX_table_II_intPA -0x16 0xe1874 //High gain -0x16 0xa1874 //middle gain -0x16 0x61874 //low gain -0x16 0x21874 //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 //for DMSP EVM [bit19]=1 -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //for Tx 40M spur//0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control_intPA +0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443 +0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730 +0x4a 0x50f0f +0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee +0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40 +0x13 0x247ab +0x13 0x2079f +0x13 0x1c793 +0x13 0x1839f +0x13 0x14396 +0x13 0x1019e +0x13 0x0c195 +0x13 0x08198 +0x13 0x040a4 +0x13 0x0001c +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GM_channel +0x18 0x37564 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain + +//5GH_channel +0x18 0x57595 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table_intPA +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table_intPA +0x15 0x0f495 +0x15 0x4f495 +0x15 0x8f495 +//5G_TX_table_II_intPA +0x16 0xe1874 //High gain +0x16 0xa1874 //middle gain +0x16 0x61874 //low gain +0x16 0x21874 //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 //for DMSP EVM [bit19]=1 +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_n.txt b/package/kernel/rtl8192cd/data_92d/radio_b_n.txt index bdbf2ad72b0..b0d0b3e2c21 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_n.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_n.txt @@ -1,248 +1,248 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x0452c -//5G_PA_control -0x48 0xf9c43 -0x49 0x02e0c -0x4a 0x546eb -0x4b 0x8966C -0x4c 0x0dde9 - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - - -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GM_channel -0x18 0x37524 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GH_channel -0x18 0x57524 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table -0x13 0x287bc //0x287b7 -0x13 0x247b0 -0x13 0x203b4 -0x13 0x1c3a8 -0x13 0x181b4 -0x13 0x141a8 -0x13 0x100b0 -0x13 0x0c0a4 -0x13 0x0b02c -0x13 0x04020 -0x13 0x00014 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 - -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 // set RF 18[19]=1 for DMSP SYN OFF -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x0452c +//5G_PA_control +0x48 0xf9c43 +0x49 0x02e0c +0x4a 0x546eb +0x4b 0x8966C +0x4c 0x0dde9 + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + + +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GM_channel +0x18 0x37524 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GH_channel +0x18 0x57524 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table +0x13 0x287bc //0x287b7 +0x13 0x247b0 +0x13 0x203b4 +0x13 0x1c3a8 +0x13 0x181b4 +0x13 0x141a8 +0x13 0x100b0 +0x13 0x0c0a4 +0x13 0x0b02c +0x13 0x04020 +0x13 0x00014 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 + +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 // set RF 18[19]=1 for DMSP SYN OFF +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/data_92d/radio_b_n_92d_hp.txt b/package/kernel/rtl8192cd/data_92d/radio_b_n_92d_hp.txt index 8d834eb2b9d..ae016cd8e7f 100644 --- a/package/kernel/rtl8192cd/data_92d/radio_b_n_92d_hp.txt +++ b/package/kernel/rtl8192cd/data_92d/radio_b_n_92d_hp.txt @@ -1,248 +1,248 @@ -//100909 -0x00 0x30000 //HSSI_AGC -0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN -0x02 0x00000 //2G_TXIQGEN -0x03 0x18c63 -0x04 0x18c63 //0x70000 -//0x05 0xfd800 //HSSI_power_control -//0x06 0xf001c //HSSI_2G_5G_RX_gain_control -//0x07 0x3c800 //HSSI_TX_gain_control -0x08 0x84000 //2G_LO_leakage -0x0b 0x1c000 //24000//2G_5G_TX_PA -0x0e 0x18c67 //APK default 0x18c63 -0x0f 0x00851 //2G_TXRX_IQGEN -0x14 0x21440 //TX_bias_table_I -//0x15 0x00430 //TX_IPA_table -//0x16 0xe0332 //TX_bias_table_II -//0x17 0x90000 //HSSI_SYN2_power_control -0x18 0x07401 //channel_band_control -0x19 0x00060 //TRXIQ control -0x1d 0xa1290 //RXBB_contorl -//0x22 0x00000 -0x23 0x01558 //TXBB_control -//0x24 0x00000 -//0x3d 0x00000 -//0x3e 0x00000 -//0x3f 0x00000 -//0x42 0x08400 //thermal meter - -//2G_RFE_control -0x1a 0x30a99 -0x1b 0x40b00 -0x1c 0xfc339 -//5G_RFE_control -0x3a 0xa57eb -0x3b 0x20000 -0x3c 0xff454 //0xff7d4 -//2G_TX_RFE_control -0x20 0x0aa52 -0x21 0x54000 -//5G_TX_RFE_control -0x40 0x0aa52 -0x41 0x14000 -//SYN control -0x25 0x803be -0x26 0xfc638 -0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting -0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting -0x29 0xd7110 -0x2a 0xaeb04 //0x8cb04 -0x2b 0x4128b -0x2c 0x01840 -//0x2f 0x22ff0 -//2G_PA_control -0x43 0x2444f -0x44 0x1adb0 -0x45 0x56467 -0x46 0x8992c -0x47 0x04529 //2011.11.16 Arthur 452c intpa 4529 extpa -//5G_PA_control -0x48 0xf9c43 -0x49 0x02e0c -0x4a 0x546eb -0x4b 0x8966C -0x4c 0x0dde9 - -////2G_table_start//// -0x18 0x07401 -0x00 0x70000 -//2G_RX_gain_table -0x12 0xdc000 -0x12 0x90000 -0x12 0x51000 -0x12 0x12000 -//2G_TX_gain_table -0x13 0x287B7 -0x13 0x247AB -0x13 0x2079F -0x13 0x1C793 -0x13 0x1839B -0x13 0x14392 -0x13 0x1019A -0x13 0x0C191 -0x13 0x08194 -0x13 0x040A0 -0x13 0x00018 -//2G_IPA_bias_table -0x15 0x0f424 -0x15 0x4f424 -0x15 0x8f424 -//2G_TX_table_II -0x16 0xe1330 //High gain -0x16 0xa1330 //middle gain -0x16 0x61330 //low gain -0x16 0x21330 //ultra low gain - -//High Power - Arthur - 0627 -////5G_table_start//// -//5GL_channel -0x18 0x17524 -0x00 0x70000 -//5GL_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GL_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GM_channel -0x18 0x37524 -0x00 0x70000 -//5GM_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GM_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 -0x13 0x0c38d -0x13 0x08199 -0x13 0x0418d -0x13 0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain - -//5GH_channel -0x18 0x57524 -0x00 0x70000 -//5GH_RX_gain_table -0x12 0xcf000 -0x12 0xbc000 -0x12 0x78000 -0x12 0x00000 -//5GH_TX_gain_table -0x13 0x287bf -0x13 0x247b3 -0x13 0x207a7 -0x13 0x1c79b -0x13 0x1839f -0x13 0x14393 -0x13 0x10399 //0x1039d //0x10399 -0x13 0x0c38d //0x0c399 //0x0c38d -0x13 0x08199 //0x0819d //0x08199 -0x13 0x0418d //0x04199 //0x0418d -0x13 0x00099 //0x00099 //0x00099 -//5G_IPA_bias_table -0x15 0x0f4C3 -0x15 0x4f4C3 -0x15 0x8f4C3 -//5G_TX_table_II -0x16 0xe085F //High gain -0x16 0xa085F //middle gain -0x16 0x6085F //low gain -0x16 0x2085F //ultra low gain -// 5G_IMR_tank_start -0x30 0x4470f -0x31 0x44ff0 -0x32 0x00070 -0x33 0xdd480 -0x34 0xffac0 -0x35 0xb80c0 -0x36 0x77000 -0x37 0x64ff2 -0x38 0xe7661 -0x39 0x00e90 -//end - -0x00 0x30000 - -0x18 0x0f401 //2G channel -0xfe -0xfe -0x1e 0x88009 -0x1f 0x80003 -0xfe -0x1e 0x88001 -0x1f 0x80000 -0xfe -//Rewrite Syn-table -0x18 0x87401 // set RF 18[19]=1 for DMSP SYN OFF -0xfe -0xfe -0xfe -0x2b 0x41289 //02b4128b -0xfe -0x2d 0x66666 -0x2e 0x64001 -0x2d 0x91111 -0x2e 0x14002 -0x2d 0xbbbbb -0x2e 0xb4003 -0x2d 0xe6666 -0x2e 0x64004 -0x2d 0x88888 //0x11111 -0x2e 0x84005 //0x14405 -0x2d 0x9dddd //0x3bbbb -0x2e 0xd4006 //0xb4406 -0x2d 0xb3333 //0x66666 -0x2e 0x34007 //0x64407 -0x2d 0x48888 //0x91111 -0x2e 0x84408 //0x14408 -0x2d 0xbbbbb -0x2e 0xb4409 -0x2d 0xe6666 -0x2e 0x6440a -0x2d 0x11111 -0x2e 0x1480b -0x2d 0x3bbbb -0x2e 0xb480c -0x2d 0x66666 -0x2e 0x6480d -0x2d 0xccccc -0x2e 0xc480e -//end -//0x18 0x0f401 //2G channel +//100909 +0x00 0x30000 //HSSI_AGC +0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN +0x02 0x00000 //2G_TXIQGEN +0x03 0x18c63 +0x04 0x18c63 //0x70000 +//0x05 0xfd800 //HSSI_power_control +//0x06 0xf001c //HSSI_2G_5G_RX_gain_control +//0x07 0x3c800 //HSSI_TX_gain_control +0x08 0x84000 //2G_LO_leakage +0x0b 0x1c000 //24000//2G_5G_TX_PA +0x0e 0x18c67 //APK default 0x18c63 +0x0f 0x00851 //2G_TXRX_IQGEN +0x14 0x21440 //TX_bias_table_I +//0x15 0x00430 //TX_IPA_table +//0x16 0xe0332 //TX_bias_table_II +//0x17 0x90000 //HSSI_SYN2_power_control +0x18 0x07401 //channel_band_control +0x19 0x00060 //TRXIQ control +0x1d 0xa1290 //RXBB_contorl +//0x22 0x00000 +0x23 0x01558 //TXBB_control +//0x24 0x00000 +//0x3d 0x00000 +//0x3e 0x00000 +//0x3f 0x00000 +//0x42 0x08400 //thermal meter + +//2G_RFE_control +0x1a 0x30a99 +0x1b 0x40b00 +0x1c 0xfc339 +//5G_RFE_control +0x3a 0xa57eb +0x3b 0x20000 +0x3c 0xff454 //0xff7d4 +//2G_TX_RFE_control +0x20 0x0aa52 +0x21 0x54000 +//5G_TX_RFE_control +0x40 0x0aa52 +0x41 0x14000 +//SYN control +0x25 0x803be +0x26 0xfc638 +0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting +0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting +0x29 0xd7110 +0x2a 0xaeb04 //0x8cb04 +0x2b 0x4128b +0x2c 0x01840 +//0x2f 0x22ff0 +//2G_PA_control +0x43 0x2444f +0x44 0x1adb0 +0x45 0x56467 +0x46 0x8992c +0x47 0x04529 //2011.11.16 Arthur 452c intpa 4529 extpa +//5G_PA_control +0x48 0xf9c43 +0x49 0x02e0c +0x4a 0x546eb +0x4b 0x8966C +0x4c 0x0dde9 + +////2G_table_start//// +0x18 0x07401 +0x00 0x70000 +//2G_RX_gain_table +0x12 0xdc000 +0x12 0x90000 +0x12 0x51000 +0x12 0x12000 +//2G_TX_gain_table +0x13 0x287B7 +0x13 0x247AB +0x13 0x2079F +0x13 0x1C793 +0x13 0x1839B +0x13 0x14392 +0x13 0x1019A +0x13 0x0C191 +0x13 0x08194 +0x13 0x040A0 +0x13 0x00018 +//2G_IPA_bias_table +0x15 0x0f424 +0x15 0x4f424 +0x15 0x8f424 +//2G_TX_table_II +0x16 0xe1330 //High gain +0x16 0xa1330 //middle gain +0x16 0x61330 //low gain +0x16 0x21330 //ultra low gain + +//High Power - Arthur - 0627 +////5G_table_start//// +//5GL_channel +0x18 0x17524 +0x00 0x70000 +//5GL_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GL_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GM_channel +0x18 0x37524 +0x00 0x70000 +//5GM_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GM_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 +0x13 0x0c38d +0x13 0x08199 +0x13 0x0418d +0x13 0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain + +//5GH_channel +0x18 0x57524 +0x00 0x70000 +//5GH_RX_gain_table +0x12 0xcf000 +0x12 0xbc000 +0x12 0x78000 +0x12 0x00000 +//5GH_TX_gain_table +0x13 0x287bf +0x13 0x247b3 +0x13 0x207a7 +0x13 0x1c79b +0x13 0x1839f +0x13 0x14393 +0x13 0x10399 //0x1039d //0x10399 +0x13 0x0c38d //0x0c399 //0x0c38d +0x13 0x08199 //0x0819d //0x08199 +0x13 0x0418d //0x04199 //0x0418d +0x13 0x00099 //0x00099 //0x00099 +//5G_IPA_bias_table +0x15 0x0f4C3 +0x15 0x4f4C3 +0x15 0x8f4C3 +//5G_TX_table_II +0x16 0xe085F //High gain +0x16 0xa085F //middle gain +0x16 0x6085F //low gain +0x16 0x2085F //ultra low gain +// 5G_IMR_tank_start +0x30 0x4470f +0x31 0x44ff0 +0x32 0x00070 +0x33 0xdd480 +0x34 0xffac0 +0x35 0xb80c0 +0x36 0x77000 +0x37 0x64ff2 +0x38 0xe7661 +0x39 0x00e90 +//end + +0x00 0x30000 + +0x18 0x0f401 //2G channel +0xfe +0xfe +0x1e 0x88009 +0x1f 0x80003 +0xfe +0x1e 0x88001 +0x1f 0x80000 +0xfe +//Rewrite Syn-table +0x18 0x87401 // set RF 18[19]=1 for DMSP SYN OFF +0xfe +0xfe +0xfe +0x2b 0x41289 //02b4128b +0xfe +0x2d 0x66666 +0x2e 0x64001 +0x2d 0x91111 +0x2e 0x14002 +0x2d 0xbbbbb +0x2e 0xb4003 +0x2d 0xe6666 +0x2e 0x64004 +0x2d 0x88888 //0x11111 +0x2e 0x84005 //0x14405 +0x2d 0x9dddd //0x3bbbb +0x2e 0xd4006 //0xb4406 +0x2d 0xb3333 //0x66666 +0x2e 0x34007 //0x64407 +0x2d 0x48888 //0x91111 +0x2e 0x84408 //0x14408 +0x2d 0xbbbbb +0x2e 0xb4409 +0x2d 0xe6666 +0x2e 0x6440a +0x2d 0x11111 +0x2e 0x1480b +0x2d 0x3bbbb +0x2e 0xb480c +0x2d 0x66666 +0x2e 0x6480d +0x2d 0xccccc +0x2e 0xc480e +//end +//0x18 0x0f401 //2G channel 0xff 0xffff \ No newline at end of file diff --git a/package/kernel/rtl8192cd/efuse_97f/common.h b/package/kernel/rtl8192cd/efuse_97f/common.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/efuse_97f/efuse.c b/package/kernel/rtl8192cd/efuse_97f/efuse.c old mode 100755 new mode 100644 index 27052a94e04..4ad0bd34537 --- a/package/kernel/rtl8192cd/efuse_97f/efuse.c +++ b/package/kernel/rtl8192cd/efuse_97f/efuse.c @@ -1,416 +1,416 @@ -//#include "common.h" -#include "phydm_precomp.h" - -#include "rom_def.h" -#include "efuse.h" -//#include -//#include -#include "sys_reg.h" - - - - -static void load_efuse_word_data(u1Byte word_enb, pu4Byte pidx, pu1Byte data); -static void dump_efuse_word_data(u4Byte loc, pu1Byte data); - -//extern u4Byte get_cpu_freq(u4Byte strap_pin); -//extern void set_rom_progress(u1Byte value); -inline void set_rom_progress(u1Byte value) -{ - REG32(REG_ENABLE_IP) = (REG32(REG_ENABLE_IP) & BIT_INV_ROM_OK_CHECK) | BIT_ROM_OK_CHECK(value); - DBG_MSG(COMP_MONITOR, DBG_TRACE, ("rom_progress: 0x%x\n", REG32(REG_ENABLE_IP))); - panic_printk("rom_progress: 0x%x\n", REG32(REG_ENABLE_IP)); -} - -void get_efuse_data(u1Byte offset, u1Byte len, pu1Byte value) -{ - // TODO: endian issue ???????// - // beforce calling this function, you must guarantee that the function "load_efuse_data_to_reg" has been called - u1Byte UNIT = 4; - u1Byte cnt = len / UNIT; - u4Byte i; - - if ((len % UNIT) != 0) { - cnt += 1; - } - - for (i = 0; i < cnt; i++) { - memcpy(REG32(REG_EFUSE_P0_0 + offset + i), value, UNIT); - value += UNIT; - } -} - -#if 0 -void set_efuse_options(PEFUSE_DATA pefuse_data) -{ - u4Byte strap_pin, cpu_freq; - //globalDebugLevel = BIT_GET_EFUSE_BOOT_CTRL_DEBUG_MSG(pefuse_data->ctrl); - - if (pefuse_data->ctrl & BIT_EFUSE_BOOT_CTRL_CHANGE_CPU_FREQ) { - // set REG_HW_STRAP[19:18] = 2'b00; - REG32(REG_HW_STRAP) = REG32(REG_HW_STRAP) & ~(BIT_SHIFT_STRAP_PIN_CK_CPU_DIV_SEL_0|BIT_SHIFT_STRAP_PIN_CK_CPU_DIV_SEL_1); - strap_pin = REG32(REG_HW_STRAP); - cpu_freq = get_cpu_freq(strap_pin); - DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("cpu:%d MHz, strap:0x%x \n", cpu_freq, strap_pin)); - } -} -#endif -#if FPGA_VERIFY_EFUSE -void efuse_test_data(void) -{ - // Note: if you want to write different data, you must reset FPGA - // Note: the last entry must write 0x00000000 - -#if 0 - write_efuse_byte(0x8F81290E, 0xFFFFFFFF, 0, 0); - write_efuse_byte(0xAF3C1137, 0xFFFFFFFF, 0, 1); - write_efuse_byte(0x0F00273E, 0xFFFFFFFF, 0, 2); - write_efuse_byte(0xEF300057, 0xFFFFFFFF, 0, 3); - - write_efuse_byte(0xEF05814E, 0xFFFFFFFF, 1, 0); - write_efuse_byte(0xFF80B04B, 0xFFFFFFFF, 1, 1); - write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 2); - write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 3); -#endif - -#if 1 - // efuse default value is 0x00000000 - - // 0F 8E (addr: 0x200) - C3 00 - - // verify change cpu freq - //write_efuse_byte(0x00D08E0F, 0xFFFFFFFF, 0, 0); - - // verify execute from SRAM and load address is 0xBFE00500 - //write_efuse_byte(0x00C78E0F, 0xFFFFFFFF, 0, 0); - - // 2F 8C (addr: 0x208) - 10 05 E0 BF - // 4F 8C (addr: 0x210) - 00 10 60 A0 - //write_efuse_byte(0x05008C2F, 0xFFFFFFFF, 0, 1); - //write_efuse_byte(0x8C4FBFE0, 0xFFFFFFFF, 0, 2); - //write_efuse_byte(0xA0600000, 0xFFFFFFFF, 0, 3); - //write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 0); - //write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 1); - - // verify initial heap address - // 0F 8E (addr: 0x200) - 00 01 - // AF 8C (addr: 0x228) - 00 00 00 80 - // CF 8E (addr: 0x230) - 50 00 - //write_efuse_byte(0x01008E0F, 0xFFFFFFFF, 0, 0); - //write_efuse_byte(0x00008CAF, 0xFFFFFFFF, 0, 1); - //write_efuse_byte(0x8ECF8000, 0xFFFFFFFF, 0, 2); - //write_efuse_byte(0x00000050, 0xFFFFFFFF, 0, 3); - - // verify erase spi-nor-flash - // 0F 8E (addr: 0x200) - C0 02 - // CF 8C (addr: 0x230) - 00 10 00 B0 - // test image len and heap len - // 6F 8C (addr: 0x218) - 06 00 03 00 - write_efuse_byte(0x02C08E0F, 0xFFFFFFFF, 0, 0); - write_efuse_byte(0x10008CCF, 0xFFFFFFFF, 0, 1); - write_efuse_byte(0x8C6FB000, 0xFFFFFFFF, 0, 2); - write_efuse_byte(0x00030006, 0xFFFFFFFF, 0, 3); - -#endif - -#if 0 - // 0F 8E (addr: 0x200) - 07 00 - write_efuse_byte(0x00078E0F, 0xFFFFFFFF, 1, 0); - // 4F 8C (addr: 0x210) - 00 00 70 A0 - write_efuse_byte(0x00008C4F, 0xFFFFFFFF, 1, 1); - write_efuse_byte(0x0000A070, 0xFFFFFFFF, 1, 2); - write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 3); -#endif -} -#endif // FPGA_VERIFY_EFUSE - -void dump_efuse_reg_data(u4Byte max_num) -{ - u4Byte i, reg; - for(i = 0; i < EFUSE_PORT_MAX*EFUSE_PORT_IDX_MAX && i < max_num; i++) { - reg = REG_EFUSE_P0_0 + i*4; - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("0x%x: 0x%x\n", reg, REG32(reg))); - } -} - -#if EFUSE_WRITE_CMD -// dataPort: 0~7, dataIdx: 0~3 -u1Byte write_efuse_byte(u4Byte data, u4Byte mask, u4Byte dataPort, u4Byte dataIdx) -{ - u4Byte cnt = 0; - u4Byte cnt_max = 1000; - - REG32(REG_EFUSE_CONFIG) = REG32(REG_EFUSE_CONFIG) | BIT_EFUSE_CONFIG_PWR_GATE_EN | BIT_EFUSE_CONFIG_BURN_CHECK; - - // suggest delay 1 us on spec. - //udelay(1); - delay_us(1); - - // clear all mask - REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_0) = 0; - REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_1) = 0; - REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_2) = 0; - REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_3) = 0; - - REG32(REG_EFUSE_WRITE_DATA_0 + dataIdx * 0x4) = data; - REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_0 + dataIdx * 0x4) = mask; - - REG32(REG_EFUSE_CMD) = (REG32(REG_EFUSE_CMD) & (~0x7)) | BIT_EFUSE_CMD_ADDR(dataPort) | BIT_EFUSE_RW_CTRL; - - do { - if ((REG32(REG_EFUSE_CMD) & BIT_EFUSE_CTRL_STATE) == BIT_EFUSE_CTRL_STATE) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): 0x%x, cnt:0x%02x \n", __FUNCTION__, __LINE__, REG32(REG_EFUSE_CMD), cnt)); - break; - } - cnt++; - mdelay(10); - } while(cnt < cnt_max); - - if (cnt >= cnt_max) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write fail (timeout) !!!\n")); - return STATUS_EFUSE_TIMEOUT; - } else { - u4Byte resultFlag = REG32(REG_EFUSE_BURN_CHECK_FAIL_0) | REG32(REG_EFUSE_BURN_CHECK_FAIL_1) | - REG32(REG_EFUSE_BURN_CHECK_FAIL_2) | REG32(REG_EFUSE_BURN_CHECK_FAIL_3); - - if (resultFlag == 0) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write data done. p[%d]_[%d] = 0x%x & 0x%x, 0x%02x\n", dataPort, dataIdx, data, mask, cnt)); - return STATUS_EFUSE_SUCCESS; - } else { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write fail (0x%x) !!!\n", resultFlag)); - return STATUS_EFUSE_FAIL; - } - } -} -#endif - -//inline u1Byte load_efuse_data_to_reg(void) -u1Byte load_efuse_data_to_reg(void) -{ - u4Byte cnt = 0; - u4Byte cnt_max = 5000; - -//#ifdef CONFIG_RTL8197F -#if 1 - // patch default REG_EFUSE_TIMING_CTRL value to 0x01040A4F for RTL 8197F - REG32(REG_EFUSE_TIMING_CTRL) = 0x01040A4F; -#endif - - REG32(REG_EFUSE_CONFIG) = REG32(REG_EFUSE_CONFIG) & (~BIT_EFUSE_CONFIG_PWR_GATE_EN); - REG32(REG_EFUSE_CMD) = REG32(REG_EFUSE_CMD) & (~BIT_EFUSE_RW_CTRL); - - do { - if ((REG32(REG_EFUSE_CMD) & BIT_EFUSE_CTRL_STATE) == BIT_EFUSE_CTRL_STATE) { - break; - } - cnt++; - //udelay(1); - delay_us(1); - } while(cnt < cnt_max); - - if (cnt < cnt_max) { - DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("load efuse ok\n")); - panic_printk("load efuse ok\n"); - set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_REG_OK); - return STATUS_EFUSE_SUCCESS; - } else { - DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("load efuse fail. 0x%x(0x%x) \n", REG_EFUSE_CMD, REG32(REG_EFUSE_CMD))); - panic_printk("load efuse fail. 0x%x(0x%x) \n", REG_EFUSE_CMD, REG32(REG_EFUSE_CMD)); - set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_REG_FAIL); - return STATUS_EFUSE_FAIL; - } -} - -// dataPort: 0~7, dataIdx: 0~3 -u4Byte read_efuse_byte(u4Byte idx) -{ - // efuse controller only support read 4 bytes operation. - u4Byte addr = (REG_EFUSE_P0_0 + idx) & (~0x3); - u4Byte value = REG32(addr); - u1Byte retval = 0; - - switch(idx%4) { - case 0: - retval = value & 0xFF; - break; - case 1: - retval = (value >> 8) & 0xFF; - break; - case 2: - retval = (value >> 16) & 0xFF; - break; - case 3: - retval = (value >> 24) & 0xFF; - break; - default: - ; - } - - return retval; -} - -static void load_efuse_word_data(u1Byte word_enb, pu4Byte pidx, pu1Byte data) -{ - u1Byte tmpIdx = 0, j; - for (j = 0; j < EFUSE_FORMAT_WORD_UNIT; j++) { - if ((word_enb & (0x01<ctrl = data[0] & 0xFF; - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, ctrl:0x%x\n", loc, pefuse_data->ctrl)); - pefuse_data->ctrl2 = data[1] & 0xFF; - pefuse_data->special = data[4]; - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, ctrl2:0x%x\n", loc, pefuse_data->ctrl2)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_BOOT_INIT_DDR_FROM_EXT_ADDR, loc)) { - pefuse_data->exec_from_sram_addr = ( data[0] & 0xFF) | - ( (data[1] << 8) & 0xFF00 ) | - ( (data[2] << 16) & 0xFF0000 ) | - ( (data[3] << 24) & 0xFF000000 ); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, exec_from_sram_addr:0x%x\n", loc, pefuse_data->exec_from_sram_addr)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_BOOT_UBOOT_ADDR, loc)) { - pefuse_data->boot_addr = ( data[0] & 0xFF) | - ( (data[1] << 8) & 0xFF00 ) | - ( (data[2] << 16) & 0xFF0000 ) | - ( (data[3] << 24) & 0xFF000000 ); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, boot_addr:0x%x\n", loc, pefuse_data->boot_addr)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_IMG_OFFSET, loc)) { - pefuse_data->img_offset = ( data[0] & 0xFF) | - ( (data[1] << 8) & 0xFF00 ); - pefuse_data->heap_len = ( data[2] & 0xFF) | - ( (data[3] << 8) & 0xFF00); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, img_offset:0x%x\n", loc, pefuse_data->img_offset)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, heap_len:0x%x\n", loc, pefuse_data->heap_len)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_DRAM, loc)) { - pefuse_data->init_dram_val = data[0] & 0xFF; - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, init_dram_val:0x%x\n", loc, pefuse_data->init_dram_val)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_HEAP, loc)) { - pefuse_data->heap_start_addr = ( data[0] & 0xFF) | - ( (data[1] << 8) & 0xFF00 ) | - ( (data[2] << 16) & 0xFF0000 ) | - ( (data[3] << 24) & 0xFF000000 ); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, heap_addr:0x%x\n", loc, pefuse_data->heap_start_addr)); - } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_ERASE_SPI_NOR_FLASH_ADDR, loc)) { - pefuse_data->erase_start_addr = ( data[0] & 0xFF) | - ( (data[1] << 8) & 0xFF00 ) | - ( (data[2] << 16) & 0xFF0000 ) | - ( (data[3] << 24) & 0xFF000000 ); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, erase_start_addr:0x%x\n", loc, pefuse_data->erase_start_addr)); - } -} - -static void dump_efuse_content(PEFUSE_DATA pefuse_data) -{ - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("ctrl:\t\t\t0x%x\n", pefuse_data->ctrl)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("ctrl2:\t\t\t0x%x\n", pefuse_data->ctrl2)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("exec_from_sram_addr:\t0x%x\n", pefuse_data->exec_from_sram_addr)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("boot_addr:\t\t0x%x\n", pefuse_data->boot_addr)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("img_offset:\t\t0x%x\n", pefuse_data->img_offset)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("init_dram_val:\t\t0x%x\n", pefuse_data->init_dram_val)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("heap_start_addr:\t\t0x%x\n", pefuse_data->heap_start_addr)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("heap_len:\t\t0x%x\n", pefuse_data->heap_len)); - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("erase_start_addr:\t\t0x%x\n", pefuse_data->erase_start_addr)); -} - -static void dump_efuse_word_data(u4Byte loc, pu1Byte data) -{ - u1Byte i; - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("0x%03x\t", loc)); - for (i = 0; i < EFUSE_FORMAT_WORD_UNIT*2; i++) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%02x ", data[i])); - } - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("\n")); -} - -u1Byte load_efuse_data(PEFUSE_DATA pefuse_data, u1Byte bPrint) -{ - u4Byte i = 0; - u1Byte efuse_val; - u1Byte word_enb, offset; - u1Byte offset_2_0; - u4Byte loc; - u1Byte efuse_temp_data[EFUSE_FORMAT_WORD_UNIT * 2]; - - while (i < EFUSE_DATA_SIZE_MAX) { - efuse_val = read_efuse_byte(i); - i++; - - // 1). get header - // a) extened mode : 2 byte - // b) normal mode : 1 byte - if (efuse_val != 0x00) { - if (EXT_HEADER(efuse_val)) { - offset_2_0 = GET_HDR_OFFSET_2_0(efuse_val); - - efuse_val = read_efuse_byte(i); - i++; - - if (efuse_val != 0x00) { - offset = ((efuse_val & 0xF0) >> 1) | offset_2_0; - word_enb = (efuse_val & 0x0F); - - if (word_enb == 0xF) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: all words disabled in extended mode\n", __FUNCTION__, __LINE__)); - } - } else { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: extended = 0xFF \n", __FUNCTION__, __LINE__)); - break; - } - - } else { - offset = ((efuse_val >> 4) & 0x0F); - word_enb = (efuse_val & 0x0F); - - if (word_enb == 0xF) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: all words disabled in normal mode\n", __FUNCTION__, __LINE__)); - } - } - } else { - if (i == 1) { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): eFuse is empty.\n", __FUNCTION__, __LINE__)); - set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_MEM_FAIL); - return STATUS_EFUSE_EMPTY; - } else { - DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): read eFuse done 0x%03x bytes \n", __FUNCTION__, __LINE__, i)); - break; - } - } - - // 2). get data 1~4 bytes - loc = offset * 8; - - DBG_MSG(COMP_MONITOR, DBG_TRACE, ("%s(%d): loc:0x%x, offset:0x%x, word_enb:0x%x\n", __FUNCTION__, __LINE__, loc, offset, word_enb)); - - // put 8 bytes data to efuse_temp_data[] - load_efuse_word_data(word_enb, &i, &efuse_temp_data[0]); - read_efuse_word_data(&efuse_temp_data[0], pefuse_data, loc); - - if (bPrint == 1) { - dump_efuse_word_data(loc, &efuse_temp_data[0]); - } - } - - if(bPrint == 1) { - dump_efuse_content(pefuse_data); - } - - set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_MEM_OK); - return STATUS_EFUSE_SUCCESS; -} - +//#include "common.h" +#include "phydm_precomp.h" + +#include "rom_def.h" +#include "efuse.h" +//#include +//#include +#include "sys_reg.h" + + + + +static void load_efuse_word_data(u1Byte word_enb, pu4Byte pidx, pu1Byte data); +static void dump_efuse_word_data(u4Byte loc, pu1Byte data); + +//extern u4Byte get_cpu_freq(u4Byte strap_pin); +//extern void set_rom_progress(u1Byte value); +inline void set_rom_progress(u1Byte value) +{ + REG32(REG_ENABLE_IP) = (REG32(REG_ENABLE_IP) & BIT_INV_ROM_OK_CHECK) | BIT_ROM_OK_CHECK(value); + DBG_MSG(COMP_MONITOR, DBG_TRACE, ("rom_progress: 0x%x\n", REG32(REG_ENABLE_IP))); + panic_printk("rom_progress: 0x%x\n", REG32(REG_ENABLE_IP)); +} + +void get_efuse_data(u1Byte offset, u1Byte len, pu1Byte value) +{ + // TODO: endian issue ???????// + // beforce calling this function, you must guarantee that the function "load_efuse_data_to_reg" has been called + u1Byte UNIT = 4; + u1Byte cnt = len / UNIT; + u4Byte i; + + if ((len % UNIT) != 0) { + cnt += 1; + } + + for (i = 0; i < cnt; i++) { + memcpy(REG32(REG_EFUSE_P0_0 + offset + i), value, UNIT); + value += UNIT; + } +} + +#if 0 +void set_efuse_options(PEFUSE_DATA pefuse_data) +{ + u4Byte strap_pin, cpu_freq; + //globalDebugLevel = BIT_GET_EFUSE_BOOT_CTRL_DEBUG_MSG(pefuse_data->ctrl); + + if (pefuse_data->ctrl & BIT_EFUSE_BOOT_CTRL_CHANGE_CPU_FREQ) { + // set REG_HW_STRAP[19:18] = 2'b00; + REG32(REG_HW_STRAP) = REG32(REG_HW_STRAP) & ~(BIT_SHIFT_STRAP_PIN_CK_CPU_DIV_SEL_0|BIT_SHIFT_STRAP_PIN_CK_CPU_DIV_SEL_1); + strap_pin = REG32(REG_HW_STRAP); + cpu_freq = get_cpu_freq(strap_pin); + DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("cpu:%d MHz, strap:0x%x \n", cpu_freq, strap_pin)); + } +} +#endif +#if FPGA_VERIFY_EFUSE +void efuse_test_data(void) +{ + // Note: if you want to write different data, you must reset FPGA + // Note: the last entry must write 0x00000000 + +#if 0 + write_efuse_byte(0x8F81290E, 0xFFFFFFFF, 0, 0); + write_efuse_byte(0xAF3C1137, 0xFFFFFFFF, 0, 1); + write_efuse_byte(0x0F00273E, 0xFFFFFFFF, 0, 2); + write_efuse_byte(0xEF300057, 0xFFFFFFFF, 0, 3); + + write_efuse_byte(0xEF05814E, 0xFFFFFFFF, 1, 0); + write_efuse_byte(0xFF80B04B, 0xFFFFFFFF, 1, 1); + write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 2); + write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 3); +#endif + +#if 1 + // efuse default value is 0x00000000 + + // 0F 8E (addr: 0x200) - C3 00 + + // verify change cpu freq + //write_efuse_byte(0x00D08E0F, 0xFFFFFFFF, 0, 0); + + // verify execute from SRAM and load address is 0xBFE00500 + //write_efuse_byte(0x00C78E0F, 0xFFFFFFFF, 0, 0); + + // 2F 8C (addr: 0x208) - 10 05 E0 BF + // 4F 8C (addr: 0x210) - 00 10 60 A0 + //write_efuse_byte(0x05008C2F, 0xFFFFFFFF, 0, 1); + //write_efuse_byte(0x8C4FBFE0, 0xFFFFFFFF, 0, 2); + //write_efuse_byte(0xA0600000, 0xFFFFFFFF, 0, 3); + //write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 0); + //write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 1); + + // verify initial heap address + // 0F 8E (addr: 0x200) - 00 01 + // AF 8C (addr: 0x228) - 00 00 00 80 + // CF 8E (addr: 0x230) - 50 00 + //write_efuse_byte(0x01008E0F, 0xFFFFFFFF, 0, 0); + //write_efuse_byte(0x00008CAF, 0xFFFFFFFF, 0, 1); + //write_efuse_byte(0x8ECF8000, 0xFFFFFFFF, 0, 2); + //write_efuse_byte(0x00000050, 0xFFFFFFFF, 0, 3); + + // verify erase spi-nor-flash + // 0F 8E (addr: 0x200) - C0 02 + // CF 8C (addr: 0x230) - 00 10 00 B0 + // test image len and heap len + // 6F 8C (addr: 0x218) - 06 00 03 00 + write_efuse_byte(0x02C08E0F, 0xFFFFFFFF, 0, 0); + write_efuse_byte(0x10008CCF, 0xFFFFFFFF, 0, 1); + write_efuse_byte(0x8C6FB000, 0xFFFFFFFF, 0, 2); + write_efuse_byte(0x00030006, 0xFFFFFFFF, 0, 3); + +#endif + +#if 0 + // 0F 8E (addr: 0x200) - 07 00 + write_efuse_byte(0x00078E0F, 0xFFFFFFFF, 1, 0); + // 4F 8C (addr: 0x210) - 00 00 70 A0 + write_efuse_byte(0x00008C4F, 0xFFFFFFFF, 1, 1); + write_efuse_byte(0x0000A070, 0xFFFFFFFF, 1, 2); + write_efuse_byte(0x00000000, 0xFFFFFFFF, 1, 3); +#endif +} +#endif // FPGA_VERIFY_EFUSE + +void dump_efuse_reg_data(u4Byte max_num) +{ + u4Byte i, reg; + for(i = 0; i < EFUSE_PORT_MAX*EFUSE_PORT_IDX_MAX && i < max_num; i++) { + reg = REG_EFUSE_P0_0 + i*4; + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("0x%x: 0x%x\n", reg, REG32(reg))); + } +} + +#if EFUSE_WRITE_CMD +// dataPort: 0~7, dataIdx: 0~3 +u1Byte write_efuse_byte(u4Byte data, u4Byte mask, u4Byte dataPort, u4Byte dataIdx) +{ + u4Byte cnt = 0; + u4Byte cnt_max = 1000; + + REG32(REG_EFUSE_CONFIG) = REG32(REG_EFUSE_CONFIG) | BIT_EFUSE_CONFIG_PWR_GATE_EN | BIT_EFUSE_CONFIG_BURN_CHECK; + + // suggest delay 1 us on spec. + //udelay(1); + delay_us(1); + + // clear all mask + REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_0) = 0; + REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_1) = 0; + REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_2) = 0; + REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_3) = 0; + + REG32(REG_EFUSE_WRITE_DATA_0 + dataIdx * 0x4) = data; + REG32(REG_EFUSE_WRITE_DATA_BIT_MASK_0 + dataIdx * 0x4) = mask; + + REG32(REG_EFUSE_CMD) = (REG32(REG_EFUSE_CMD) & (~0x7)) | BIT_EFUSE_CMD_ADDR(dataPort) | BIT_EFUSE_RW_CTRL; + + do { + if ((REG32(REG_EFUSE_CMD) & BIT_EFUSE_CTRL_STATE) == BIT_EFUSE_CTRL_STATE) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): 0x%x, cnt:0x%02x \n", __FUNCTION__, __LINE__, REG32(REG_EFUSE_CMD), cnt)); + break; + } + cnt++; + mdelay(10); + } while(cnt < cnt_max); + + if (cnt >= cnt_max) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write fail (timeout) !!!\n")); + return STATUS_EFUSE_TIMEOUT; + } else { + u4Byte resultFlag = REG32(REG_EFUSE_BURN_CHECK_FAIL_0) | REG32(REG_EFUSE_BURN_CHECK_FAIL_1) | + REG32(REG_EFUSE_BURN_CHECK_FAIL_2) | REG32(REG_EFUSE_BURN_CHECK_FAIL_3); + + if (resultFlag == 0) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write data done. p[%d]_[%d] = 0x%x & 0x%x, 0x%02x\n", dataPort, dataIdx, data, mask, cnt)); + return STATUS_EFUSE_SUCCESS; + } else { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("Efuse write fail (0x%x) !!!\n", resultFlag)); + return STATUS_EFUSE_FAIL; + } + } +} +#endif + +//inline u1Byte load_efuse_data_to_reg(void) +u1Byte load_efuse_data_to_reg(void) +{ + u4Byte cnt = 0; + u4Byte cnt_max = 5000; + +//#ifdef CONFIG_RTL8197F +#if 1 + // patch default REG_EFUSE_TIMING_CTRL value to 0x01040A4F for RTL 8197F + REG32(REG_EFUSE_TIMING_CTRL) = 0x01040A4F; +#endif + + REG32(REG_EFUSE_CONFIG) = REG32(REG_EFUSE_CONFIG) & (~BIT_EFUSE_CONFIG_PWR_GATE_EN); + REG32(REG_EFUSE_CMD) = REG32(REG_EFUSE_CMD) & (~BIT_EFUSE_RW_CTRL); + + do { + if ((REG32(REG_EFUSE_CMD) & BIT_EFUSE_CTRL_STATE) == BIT_EFUSE_CTRL_STATE) { + break; + } + cnt++; + //udelay(1); + delay_us(1); + } while(cnt < cnt_max); + + if (cnt < cnt_max) { + DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("load efuse ok\n")); + panic_printk("load efuse ok\n"); + set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_REG_OK); + return STATUS_EFUSE_SUCCESS; + } else { + DBG_MSG(COMP_EFUSE, DBG_MESSAGE, ("load efuse fail. 0x%x(0x%x) \n", REG_EFUSE_CMD, REG32(REG_EFUSE_CMD))); + panic_printk("load efuse fail. 0x%x(0x%x) \n", REG_EFUSE_CMD, REG32(REG_EFUSE_CMD)); + set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_REG_FAIL); + return STATUS_EFUSE_FAIL; + } +} + +// dataPort: 0~7, dataIdx: 0~3 +u4Byte read_efuse_byte(u4Byte idx) +{ + // efuse controller only support read 4 bytes operation. + u4Byte addr = (REG_EFUSE_P0_0 + idx) & (~0x3); + u4Byte value = REG32(addr); + u1Byte retval = 0; + + switch(idx%4) { + case 0: + retval = value & 0xFF; + break; + case 1: + retval = (value >> 8) & 0xFF; + break; + case 2: + retval = (value >> 16) & 0xFF; + break; + case 3: + retval = (value >> 24) & 0xFF; + break; + default: + ; + } + + return retval; +} + +static void load_efuse_word_data(u1Byte word_enb, pu4Byte pidx, pu1Byte data) +{ + u1Byte tmpIdx = 0, j; + for (j = 0; j < EFUSE_FORMAT_WORD_UNIT; j++) { + if ((word_enb & (0x01<ctrl = data[0] & 0xFF; + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, ctrl:0x%x\n", loc, pefuse_data->ctrl)); + pefuse_data->ctrl2 = data[1] & 0xFF; + pefuse_data->special = data[4]; + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, ctrl2:0x%x\n", loc, pefuse_data->ctrl2)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_BOOT_INIT_DDR_FROM_EXT_ADDR, loc)) { + pefuse_data->exec_from_sram_addr = ( data[0] & 0xFF) | + ( (data[1] << 8) & 0xFF00 ) | + ( (data[2] << 16) & 0xFF0000 ) | + ( (data[3] << 24) & 0xFF000000 ); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, exec_from_sram_addr:0x%x\n", loc, pefuse_data->exec_from_sram_addr)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_BOOT_UBOOT_ADDR, loc)) { + pefuse_data->boot_addr = ( data[0] & 0xFF) | + ( (data[1] << 8) & 0xFF00 ) | + ( (data[2] << 16) & 0xFF0000 ) | + ( (data[3] << 24) & 0xFF000000 ); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, boot_addr:0x%x\n", loc, pefuse_data->boot_addr)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_IMG_OFFSET, loc)) { + pefuse_data->img_offset = ( data[0] & 0xFF) | + ( (data[1] << 8) & 0xFF00 ); + pefuse_data->heap_len = ( data[2] & 0xFF) | + ( (data[3] << 8) & 0xFF00); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, img_offset:0x%x\n", loc, pefuse_data->img_offset)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, heap_len:0x%x\n", loc, pefuse_data->heap_len)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_DRAM, loc)) { + pefuse_data->init_dram_val = data[0] & 0xFF; + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, init_dram_val:0x%x\n", loc, pefuse_data->init_dram_val)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_HEAP, loc)) { + pefuse_data->heap_start_addr = ( data[0] & 0xFF) | + ( (data[1] << 8) & 0xFF00 ) | + ( (data[2] << 16) & 0xFF0000 ) | + ( (data[3] << 24) & 0xFF000000 ); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, heap_addr:0x%x\n", loc, pefuse_data->heap_start_addr)); + } else if (DATA_IN_THIS_OFFSET(OFFSET_EFUSE_ERASE_SPI_NOR_FLASH_ADDR, loc)) { + pefuse_data->erase_start_addr = ( data[0] & 0xFF) | + ( (data[1] << 8) & 0xFF00 ) | + ( (data[2] << 16) & 0xFF0000 ) | + ( (data[3] << 24) & 0xFF000000 ); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("loc:0x%x, erase_start_addr:0x%x\n", loc, pefuse_data->erase_start_addr)); + } +} + +static void dump_efuse_content(PEFUSE_DATA pefuse_data) +{ + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("ctrl:\t\t\t0x%x\n", pefuse_data->ctrl)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("ctrl2:\t\t\t0x%x\n", pefuse_data->ctrl2)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("exec_from_sram_addr:\t0x%x\n", pefuse_data->exec_from_sram_addr)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("boot_addr:\t\t0x%x\n", pefuse_data->boot_addr)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("img_offset:\t\t0x%x\n", pefuse_data->img_offset)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("init_dram_val:\t\t0x%x\n", pefuse_data->init_dram_val)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("heap_start_addr:\t\t0x%x\n", pefuse_data->heap_start_addr)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("heap_len:\t\t0x%x\n", pefuse_data->heap_len)); + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("erase_start_addr:\t\t0x%x\n", pefuse_data->erase_start_addr)); +} + +static void dump_efuse_word_data(u4Byte loc, pu1Byte data) +{ + u1Byte i; + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("0x%03x\t", loc)); + for (i = 0; i < EFUSE_FORMAT_WORD_UNIT*2; i++) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%02x ", data[i])); + } + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("\n")); +} + +u1Byte load_efuse_data(PEFUSE_DATA pefuse_data, u1Byte bPrint) +{ + u4Byte i = 0; + u1Byte efuse_val; + u1Byte word_enb, offset; + u1Byte offset_2_0; + u4Byte loc; + u1Byte efuse_temp_data[EFUSE_FORMAT_WORD_UNIT * 2]; + + while (i < EFUSE_DATA_SIZE_MAX) { + efuse_val = read_efuse_byte(i); + i++; + + // 1). get header + // a) extened mode : 2 byte + // b) normal mode : 1 byte + if (efuse_val != 0x00) { + if (EXT_HEADER(efuse_val)) { + offset_2_0 = GET_HDR_OFFSET_2_0(efuse_val); + + efuse_val = read_efuse_byte(i); + i++; + + if (efuse_val != 0x00) { + offset = ((efuse_val & 0xF0) >> 1) | offset_2_0; + word_enb = (efuse_val & 0x0F); + + if (word_enb == 0xF) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: all words disabled in extended mode\n", __FUNCTION__, __LINE__)); + } + } else { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: extended = 0xFF \n", __FUNCTION__, __LINE__)); + break; + } + + } else { + offset = ((efuse_val >> 4) & 0x0F); + word_enb = (efuse_val & 0x0F); + + if (word_enb == 0xF) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): Error: all words disabled in normal mode\n", __FUNCTION__, __LINE__)); + } + } + } else { + if (i == 1) { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): eFuse is empty.\n", __FUNCTION__, __LINE__)); + set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_MEM_FAIL); + return STATUS_EFUSE_EMPTY; + } else { + DBG_MSG(COMP_EFUSE, DBG_TRACE, ("%s(%d): read eFuse done 0x%03x bytes \n", __FUNCTION__, __LINE__, i)); + break; + } + } + + // 2). get data 1~4 bytes + loc = offset * 8; + + DBG_MSG(COMP_MONITOR, DBG_TRACE, ("%s(%d): loc:0x%x, offset:0x%x, word_enb:0x%x\n", __FUNCTION__, __LINE__, loc, offset, word_enb)); + + // put 8 bytes data to efuse_temp_data[] + load_efuse_word_data(word_enb, &i, &efuse_temp_data[0]); + read_efuse_word_data(&efuse_temp_data[0], pefuse_data, loc); + + if (bPrint == 1) { + dump_efuse_word_data(loc, &efuse_temp_data[0]); + } + } + + if(bPrint == 1) { + dump_efuse_content(pefuse_data); + } + + set_rom_progress(ROM_PROGRESS_LOAD_EFUSE_TO_MEM_OK); + return STATUS_EFUSE_SUCCESS; +} + diff --git a/package/kernel/rtl8192cd/efuse_97f/efuse.h b/package/kernel/rtl8192cd/efuse_97f/efuse.h old mode 100755 new mode 100644 index 96975c411de..2eaa32f8314 --- a/package/kernel/rtl8192cd/efuse_97f/efuse.h +++ b/package/kernel/rtl8192cd/efuse_97f/efuse.h @@ -1,165 +1,165 @@ - -#ifndef __EFUSE_H__ -#define __EFUSE_H__ - -//#define REG_EFUSE_BASE_ADDR EFUSE_BASE_ADDR // 0x18000700 -//#define REG_EFUSE_BASE_ADDR 0x18000700 -#define REG_EFUSE_BASE_ADDR 0xB8000700 - -#define REG_EFUSE_CMD (REG_EFUSE_BASE_ADDR + 0x00000000) -#define REG_EFUSE_CONFIG (REG_EFUSE_BASE_ADDR + 0x00000004) -#define REG_EFUSE_TIMING_CTRL (REG_EFUSE_BASE_ADDR + 0x00000008) -#define REG_EFUSE_WRITE_DATA_0 (REG_EFUSE_BASE_ADDR + 0x0000000C) -#define REG_EFUSE_WRITE_DATA_1 (REG_EFUSE_BASE_ADDR + 0x00000010) -#define REG_EFUSE_WRITE_DATA_2 (REG_EFUSE_BASE_ADDR + 0x00000014) -#define REG_EFUSE_WRITE_DATA_3 (REG_EFUSE_BASE_ADDR + 0x00000018) -#define REG_EFUSE_WRITE_DATA_BIT_MASK_0 (REG_EFUSE_BASE_ADDR + 0x0000001C) -#define REG_EFUSE_WRITE_DATA_BIT_MASK_1 (REG_EFUSE_BASE_ADDR + 0x00000020) -#define REG_EFUSE_WRITE_DATA_BIT_MASK_2 (REG_EFUSE_BASE_ADDR + 0x00000024) -#define REG_EFUSE_WRITE_DATA_BIT_MASK_3 (REG_EFUSE_BASE_ADDR + 0x00000028) -#define REG_EFUSE_BURN_CHECK_FAIL_0 (REG_EFUSE_BASE_ADDR + 0x0000002C) -#define REG_EFUSE_BURN_CHECK_FAIL_1 (REG_EFUSE_BASE_ADDR + 0x00000030) -#define REG_EFUSE_BURN_CHECK_FAIL_2 (REG_EFUSE_BASE_ADDR + 0x00000034) -#define REG_EFUSE_BURN_CHECK_FAIL_3 (REG_EFUSE_BASE_ADDR + 0x00000038) - -#define REG_EFUSE_P0_0 (REG_EFUSE_BASE_ADDR + 0x00000080) -#define REG_EFUSE_P0_1 (REG_EFUSE_BASE_ADDR + 0x00000084) -#define REG_EFUSE_P0_2 (REG_EFUSE_BASE_ADDR + 0x00000088) -#define REG_EFUSE_P0_3 (REG_EFUSE_BASE_ADDR + 0x0000008C) -#define REG_EFUSE_P1_0 (REG_EFUSE_BASE_ADDR + 0x00000090) -#define REG_EFUSE_P1_1 (REG_EFUSE_BASE_ADDR + 0x00000094) -#define REG_EFUSE_P1_2 (REG_EFUSE_BASE_ADDR + 0x00000098) -#define REG_EFUSE_P1_3 (REG_EFUSE_BASE_ADDR + 0x0000009C) -#define REG_EFUSE_P2_0 (REG_EFUSE_BASE_ADDR + 0x000000A0) -#define REG_EFUSE_P2_1 (REG_EFUSE_BASE_ADDR + 0x000000A4) -#define REG_EFUSE_P2_2 (REG_EFUSE_BASE_ADDR + 0x000000A8) -#define REG_EFUSE_P2_3 (REG_EFUSE_BASE_ADDR + 0x000000AC) -#define REG_EFUSE_P3_0 (REG_EFUSE_BASE_ADDR + 0x000000B0) -#define REG_EFUSE_P3_1 (REG_EFUSE_BASE_ADDR + 0x000000B4) -#define REG_EFUSE_P3_2 (REG_EFUSE_BASE_ADDR + 0x000000B8) -#define REG_EFUSE_P3_3 (REG_EFUSE_BASE_ADDR + 0x000000BC) -#define REG_EFUSE_P4_0 (REG_EFUSE_BASE_ADDR + 0x000000C0) -#define REG_EFUSE_P4_1 (REG_EFUSE_BASE_ADDR + 0x000000C4) -#define REG_EFUSE_P4_2 (REG_EFUSE_BASE_ADDR + 0x000000C8) -#define REG_EFUSE_P4_3 (REG_EFUSE_BASE_ADDR + 0x000000CC) -#define REG_EFUSE_P5_0 (REG_EFUSE_BASE_ADDR + 0x000000D0) -#define REG_EFUSE_P5_1 (REG_EFUSE_BASE_ADDR + 0x000000D4) -#define REG_EFUSE_P5_2 (REG_EFUSE_BASE_ADDR + 0x000000D8) -#define REG_EFUSE_P5_3 (REG_EFUSE_BASE_ADDR + 0x000000DC) -#define REG_EFUSE_P6_0 (REG_EFUSE_BASE_ADDR + 0x000000E0) -#define REG_EFUSE_P6_1 (REG_EFUSE_BASE_ADDR + 0x000000E4) -#define REG_EFUSE_P6_2 (REG_EFUSE_BASE_ADDR + 0x000000E8) -#define REG_EFUSE_P6_3 (REG_EFUSE_BASE_ADDR + 0x000000EC) -#define REG_EFUSE_P7_0 (REG_EFUSE_BASE_ADDR + 0x000000F0) -#define REG_EFUSE_P7_1 (REG_EFUSE_BASE_ADDR + 0x000000F4) -#define REG_EFUSE_P7_2 (REG_EFUSE_BASE_ADDR + 0x000000F8) -#define REG_EFUSE_P7_3 (REG_EFUSE_BASE_ADDR + 0x000000FC) - -#define EFUSE_PORT_MAX 8 -#define EFUSE_PORT_IDX_MAX 4 - -// REG_EFUSE_CMD -#define BIT_SHIFT_EFUSE_CMD_ADDR 0 -#define BIT_MASK_EFUSE_CMD_ADDR 0x7 -#define BIT_EFUSE_CMD_ADDR(x) (((x) & BIT_MASK_EFUSE_CMD_ADDR) << BIT_SHIFT_EFUSE_CMD_ADDR) -#define BIT_EFUSE_RW_CTRL BIT(15) -#define BIT_EFUSE_CTRL_STATE BIT(16) - -// REG_EFUSE_CONFIG -#define BIT_EFUSE_CONFIG_PWR_GATE_EN BIT(0) -#define BIT_EFUSE_CONFIG_BURN_CHECK BIT(31) - - -// return status -#define STATUS_EFUSE_SUCCESS 0 -#define STATUS_EFUSE_FAIL 1 -#define STATUS_EFUSE_TIMEOUT 2 -#define STATUS_EFUSE_EMPTY 3 - - -typedef struct _EFUSE_DATA_ -{ - u1Byte ctrl; - u1Byte ctrl2; - u1Byte special; - u4Byte exec_from_sram_addr; - u4Byte boot_addr; - u2Byte img_offset; - u1Byte init_dram_val; - u4Byte heap_start_addr; - u2Byte heap_len; - u4Byte erase_start_addr; -} EFUSE_DATA, *PEFUSE_DATA; - -#define EXT_HEADER(hdr) ((hdr & 0x1F ) == 0x0F) -#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) -#define GET_HDR_OFFSET_2_0(hdr) ((hdr & 0xE0) >> 5) -#define DATA_IN_THIS_OFFSET(addr, loc) ((loc <= addr) && (addr < (loc+EFUSE_FORMAT_WORD_UNIT))) - -#define EFUSE_DATA_SIZE_MAX 0x80 -#define EFUSE_FORMAT_WORD_UNIT 4 -#define EFUSE_IMG_OFFSET_UNIT 1024 -#define EFUSE_HEAP_LEN_UNIT 1024 - - -// function list -u1Byte write_efuse_byte(u4Byte data, u4Byte mask, u4Byte dataPort, u4Byte dataIdx); -u1Byte load_efuse_data_to_reg(void); -u4Byte read_efuse_byte(u4Byte idx); -u1Byte load_efuse_data(PEFUSE_DATA pefuse_data, u1Byte bPrint); -void dump_efuse_reg_data(u4Byte max_num); -void set_efuse_options(PEFUSE_DATA pefuse_data); -void get_efuse_data(u1Byte offset, u1Byte len, pu1Byte value); - -// define efuse virtual map -// Note: each offset must be 8 byte alignment currently -#define OFFSET_EFUSE_BOOT_CTRL 0x200 - -#define BIT_SHIFT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM 0 -#define BIT_MASK_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM 0x3 -#define BIT_GET_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM(x) (((x) >> BIT_SHIFT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM) & BIT_MASK_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM) -#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_INIT_RAM 0x0 -#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_EXEC_SRAM 0x1 -#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_INIT_RAM_EXEC_SRAM 0x2 -#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_EXEC_SRAM_INIT_RAM 0x3 - -#define BIT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_ADDR BIT(2) -#define BIT_EFUSE_BOOT_CTRL_UBOOT_ADDR BIT(3) -#define BIT_EFUSE_BOOT_CTRL_CHANGE_CPU_FREQ BIT(4) -#define BIT_EFUSE_BOOT_CTRL_IMG_OFFSET BIT(5) - -#define BIT_SHIFT_EFUSE_BOOT_CTRL_DEBUG_MSG 6 -#define BIT_MASK_EFUSE_BOOT_CTRL_DEBUG_MSG 0x3 -#define BIT_GET_EFUSE_BOOT_CTRL_DEBUG_MSG(x) (((x) >> BIT_SHIFT_EFUSE_BOOT_CTRL_DEBUG_MSG) & BIT_MASK_EFUSE_BOOT_CTRL_DEBUG_MSG) - -#define BIT_EFUSE_BOOT_CTRL_INIT_HEAP BIT(0) -#define BIT_EFUSE_BOOT_CTRL_ERASE_SPI_NOR_FLASH_ADDR BIT(1) - -#define OFFSET_EFUSE_BOOT_INIT_DDR_FROM_EXT_ADDR 0x208 -#define OFFSET_EFUSE_BOOT_UBOOT_ADDR 0x210 -#define OFFSET_EFUSE_IMG_OFFSET 0x218 - -#define OFFSET_EFUSE_DRAM 0x220 -#define BIT_EFUSE_DRAM_DDR2_CLK200 BIT(0) -#define BIT_EFUSE_DRAM_ENABLE_ODT BIT(1) - -#define OFFSET_EFUSE_HEAP 0x228 -#define OFFSET_EFUSE_ERASE_SPI_NOR_FLASH_ADDR 0x230 - -// efuse physical map offset -// each offset 4 byte alignment currently -#define OFFSET_EFUSE_PHYSICAL_AES_MODE 0x2C -#define EFUSE_AES_MODE_SIZE 4 -#define BIT_SHIFT_EFUSE_AES_MODE 24 -#define BIT_MASK_EFUSE_AES_MODE 0x3 -#define BIT_GET_EFUSE_AES_MODE(x) (((x) >> BIT_SHIFT_EFUSE_AES_MODE) & BIT_MASK_EFUSE_AES_MODE) -#define EFUSE_AES_MODE_ECB 0x0 -#define EFUSE_AES_MODE_CBC 0x1 -#define EFUSE_AES_MODE_CTR 0x2 - -#define OFFSET_EFUSE_PHYSICAL_CURVE_SECURE_KEY 0x30 -#define EFUSE_CURVE_KEY_SIZE 32 - - -#endif //_EFUSE_H_ - + +#ifndef __EFUSE_H__ +#define __EFUSE_H__ + +//#define REG_EFUSE_BASE_ADDR EFUSE_BASE_ADDR // 0x18000700 +//#define REG_EFUSE_BASE_ADDR 0x18000700 +#define REG_EFUSE_BASE_ADDR 0xB8000700 + +#define REG_EFUSE_CMD (REG_EFUSE_BASE_ADDR + 0x00000000) +#define REG_EFUSE_CONFIG (REG_EFUSE_BASE_ADDR + 0x00000004) +#define REG_EFUSE_TIMING_CTRL (REG_EFUSE_BASE_ADDR + 0x00000008) +#define REG_EFUSE_WRITE_DATA_0 (REG_EFUSE_BASE_ADDR + 0x0000000C) +#define REG_EFUSE_WRITE_DATA_1 (REG_EFUSE_BASE_ADDR + 0x00000010) +#define REG_EFUSE_WRITE_DATA_2 (REG_EFUSE_BASE_ADDR + 0x00000014) +#define REG_EFUSE_WRITE_DATA_3 (REG_EFUSE_BASE_ADDR + 0x00000018) +#define REG_EFUSE_WRITE_DATA_BIT_MASK_0 (REG_EFUSE_BASE_ADDR + 0x0000001C) +#define REG_EFUSE_WRITE_DATA_BIT_MASK_1 (REG_EFUSE_BASE_ADDR + 0x00000020) +#define REG_EFUSE_WRITE_DATA_BIT_MASK_2 (REG_EFUSE_BASE_ADDR + 0x00000024) +#define REG_EFUSE_WRITE_DATA_BIT_MASK_3 (REG_EFUSE_BASE_ADDR + 0x00000028) +#define REG_EFUSE_BURN_CHECK_FAIL_0 (REG_EFUSE_BASE_ADDR + 0x0000002C) +#define REG_EFUSE_BURN_CHECK_FAIL_1 (REG_EFUSE_BASE_ADDR + 0x00000030) +#define REG_EFUSE_BURN_CHECK_FAIL_2 (REG_EFUSE_BASE_ADDR + 0x00000034) +#define REG_EFUSE_BURN_CHECK_FAIL_3 (REG_EFUSE_BASE_ADDR + 0x00000038) + +#define REG_EFUSE_P0_0 (REG_EFUSE_BASE_ADDR + 0x00000080) +#define REG_EFUSE_P0_1 (REG_EFUSE_BASE_ADDR + 0x00000084) +#define REG_EFUSE_P0_2 (REG_EFUSE_BASE_ADDR + 0x00000088) +#define REG_EFUSE_P0_3 (REG_EFUSE_BASE_ADDR + 0x0000008C) +#define REG_EFUSE_P1_0 (REG_EFUSE_BASE_ADDR + 0x00000090) +#define REG_EFUSE_P1_1 (REG_EFUSE_BASE_ADDR + 0x00000094) +#define REG_EFUSE_P1_2 (REG_EFUSE_BASE_ADDR + 0x00000098) +#define REG_EFUSE_P1_3 (REG_EFUSE_BASE_ADDR + 0x0000009C) +#define REG_EFUSE_P2_0 (REG_EFUSE_BASE_ADDR + 0x000000A0) +#define REG_EFUSE_P2_1 (REG_EFUSE_BASE_ADDR + 0x000000A4) +#define REG_EFUSE_P2_2 (REG_EFUSE_BASE_ADDR + 0x000000A8) +#define REG_EFUSE_P2_3 (REG_EFUSE_BASE_ADDR + 0x000000AC) +#define REG_EFUSE_P3_0 (REG_EFUSE_BASE_ADDR + 0x000000B0) +#define REG_EFUSE_P3_1 (REG_EFUSE_BASE_ADDR + 0x000000B4) +#define REG_EFUSE_P3_2 (REG_EFUSE_BASE_ADDR + 0x000000B8) +#define REG_EFUSE_P3_3 (REG_EFUSE_BASE_ADDR + 0x000000BC) +#define REG_EFUSE_P4_0 (REG_EFUSE_BASE_ADDR + 0x000000C0) +#define REG_EFUSE_P4_1 (REG_EFUSE_BASE_ADDR + 0x000000C4) +#define REG_EFUSE_P4_2 (REG_EFUSE_BASE_ADDR + 0x000000C8) +#define REG_EFUSE_P4_3 (REG_EFUSE_BASE_ADDR + 0x000000CC) +#define REG_EFUSE_P5_0 (REG_EFUSE_BASE_ADDR + 0x000000D0) +#define REG_EFUSE_P5_1 (REG_EFUSE_BASE_ADDR + 0x000000D4) +#define REG_EFUSE_P5_2 (REG_EFUSE_BASE_ADDR + 0x000000D8) +#define REG_EFUSE_P5_3 (REG_EFUSE_BASE_ADDR + 0x000000DC) +#define REG_EFUSE_P6_0 (REG_EFUSE_BASE_ADDR + 0x000000E0) +#define REG_EFUSE_P6_1 (REG_EFUSE_BASE_ADDR + 0x000000E4) +#define REG_EFUSE_P6_2 (REG_EFUSE_BASE_ADDR + 0x000000E8) +#define REG_EFUSE_P6_3 (REG_EFUSE_BASE_ADDR + 0x000000EC) +#define REG_EFUSE_P7_0 (REG_EFUSE_BASE_ADDR + 0x000000F0) +#define REG_EFUSE_P7_1 (REG_EFUSE_BASE_ADDR + 0x000000F4) +#define REG_EFUSE_P7_2 (REG_EFUSE_BASE_ADDR + 0x000000F8) +#define REG_EFUSE_P7_3 (REG_EFUSE_BASE_ADDR + 0x000000FC) + +#define EFUSE_PORT_MAX 8 +#define EFUSE_PORT_IDX_MAX 4 + +// REG_EFUSE_CMD +#define BIT_SHIFT_EFUSE_CMD_ADDR 0 +#define BIT_MASK_EFUSE_CMD_ADDR 0x7 +#define BIT_EFUSE_CMD_ADDR(x) (((x) & BIT_MASK_EFUSE_CMD_ADDR) << BIT_SHIFT_EFUSE_CMD_ADDR) +#define BIT_EFUSE_RW_CTRL BIT(15) +#define BIT_EFUSE_CTRL_STATE BIT(16) + +// REG_EFUSE_CONFIG +#define BIT_EFUSE_CONFIG_PWR_GATE_EN BIT(0) +#define BIT_EFUSE_CONFIG_BURN_CHECK BIT(31) + + +// return status +#define STATUS_EFUSE_SUCCESS 0 +#define STATUS_EFUSE_FAIL 1 +#define STATUS_EFUSE_TIMEOUT 2 +#define STATUS_EFUSE_EMPTY 3 + + +typedef struct _EFUSE_DATA_ +{ + u1Byte ctrl; + u1Byte ctrl2; + u1Byte special; + u4Byte exec_from_sram_addr; + u4Byte boot_addr; + u2Byte img_offset; + u1Byte init_dram_val; + u4Byte heap_start_addr; + u2Byte heap_len; + u4Byte erase_start_addr; +} EFUSE_DATA, *PEFUSE_DATA; + +#define EXT_HEADER(hdr) ((hdr & 0x1F ) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(hdr) ((hdr & 0xE0) >> 5) +#define DATA_IN_THIS_OFFSET(addr, loc) ((loc <= addr) && (addr < (loc+EFUSE_FORMAT_WORD_UNIT))) + +#define EFUSE_DATA_SIZE_MAX 0x80 +#define EFUSE_FORMAT_WORD_UNIT 4 +#define EFUSE_IMG_OFFSET_UNIT 1024 +#define EFUSE_HEAP_LEN_UNIT 1024 + + +// function list +u1Byte write_efuse_byte(u4Byte data, u4Byte mask, u4Byte dataPort, u4Byte dataIdx); +u1Byte load_efuse_data_to_reg(void); +u4Byte read_efuse_byte(u4Byte idx); +u1Byte load_efuse_data(PEFUSE_DATA pefuse_data, u1Byte bPrint); +void dump_efuse_reg_data(u4Byte max_num); +void set_efuse_options(PEFUSE_DATA pefuse_data); +void get_efuse_data(u1Byte offset, u1Byte len, pu1Byte value); + +// define efuse virtual map +// Note: each offset must be 8 byte alignment currently +#define OFFSET_EFUSE_BOOT_CTRL 0x200 + +#define BIT_SHIFT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM 0 +#define BIT_MASK_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM 0x3 +#define BIT_GET_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM(x) (((x) >> BIT_SHIFT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM) & BIT_MASK_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM) +#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_INIT_RAM 0x0 +#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_EXEC_SRAM 0x1 +#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_INIT_RAM_EXEC_SRAM 0x2 +#define EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_VAL_EXEC_SRAM_INIT_RAM 0x3 + +#define BIT_EFUSE_BOOT_CTRL_EXEC_FROM_SRAM_ADDR BIT(2) +#define BIT_EFUSE_BOOT_CTRL_UBOOT_ADDR BIT(3) +#define BIT_EFUSE_BOOT_CTRL_CHANGE_CPU_FREQ BIT(4) +#define BIT_EFUSE_BOOT_CTRL_IMG_OFFSET BIT(5) + +#define BIT_SHIFT_EFUSE_BOOT_CTRL_DEBUG_MSG 6 +#define BIT_MASK_EFUSE_BOOT_CTRL_DEBUG_MSG 0x3 +#define BIT_GET_EFUSE_BOOT_CTRL_DEBUG_MSG(x) (((x) >> BIT_SHIFT_EFUSE_BOOT_CTRL_DEBUG_MSG) & BIT_MASK_EFUSE_BOOT_CTRL_DEBUG_MSG) + +#define BIT_EFUSE_BOOT_CTRL_INIT_HEAP BIT(0) +#define BIT_EFUSE_BOOT_CTRL_ERASE_SPI_NOR_FLASH_ADDR BIT(1) + +#define OFFSET_EFUSE_BOOT_INIT_DDR_FROM_EXT_ADDR 0x208 +#define OFFSET_EFUSE_BOOT_UBOOT_ADDR 0x210 +#define OFFSET_EFUSE_IMG_OFFSET 0x218 + +#define OFFSET_EFUSE_DRAM 0x220 +#define BIT_EFUSE_DRAM_DDR2_CLK200 BIT(0) +#define BIT_EFUSE_DRAM_ENABLE_ODT BIT(1) + +#define OFFSET_EFUSE_HEAP 0x228 +#define OFFSET_EFUSE_ERASE_SPI_NOR_FLASH_ADDR 0x230 + +// efuse physical map offset +// each offset 4 byte alignment currently +#define OFFSET_EFUSE_PHYSICAL_AES_MODE 0x2C +#define EFUSE_AES_MODE_SIZE 4 +#define BIT_SHIFT_EFUSE_AES_MODE 24 +#define BIT_MASK_EFUSE_AES_MODE 0x3 +#define BIT_GET_EFUSE_AES_MODE(x) (((x) >> BIT_SHIFT_EFUSE_AES_MODE) & BIT_MASK_EFUSE_AES_MODE) +#define EFUSE_AES_MODE_ECB 0x0 +#define EFUSE_AES_MODE_CBC 0x1 +#define EFUSE_AES_MODE_CTR 0x2 + +#define OFFSET_EFUSE_PHYSICAL_CURVE_SECURE_KEY 0x30 +#define EFUSE_CURVE_KEY_SIZE 32 + + +#endif //_EFUSE_H_ + diff --git a/package/kernel/rtl8192cd/efuse_97f/rom_def.h b/package/kernel/rtl8192cd/efuse_97f/rom_def.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/efuse_97f/string.c b/package/kernel/rtl8192cd/efuse_97f/string.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/efuse_97f/sys_reg.h b/package/kernel/rtl8192cd/efuse_97f/sys_reg.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/ieee802_mib.h b/package/kernel/rtl8192cd/ieee802_mib.h index 49364f56e94..2b3ab9fbb6a 100644 --- a/package/kernel/rtl8192cd/ieee802_mib.h +++ b/package/kernel/rtl8192cd/ieee802_mib.h @@ -1,1131 +1,1131 @@ -/* - * Header file defines IEEE802.11 MIB - * - * $Id: ieee802_mib.h,v 1.12.2.5 2010/12/16 05:32:20 bruce Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Note: Should not use compiler flag in this header file in order for - * flash utility to get correct mib size. - */ - -#ifndef _IEEE802_MIB_H_ -#define _IEEE802_MIB_H_ - -#ifdef __ECOS -#include -#include -#endif -#if defined(RTK_NL80211) -#include "wifi.h" -#endif -#define MIB_VERSION 32 - -#define MAX_2G_CHANNEL_NUM 14 -#define MAX_5G_CHANNEL_NUM 196 -#define MACADDRLEN 6 - -#if 1//def CONFIG_SDIO_HCI -#define SDIOTYPELEN 5 -#endif - -//------------------------------------------------------------- -// Support add or remove ACL list at run time -//------------------------------------------------------------- -#define D_ACL - -#ifdef D_ACL -#define NUM_ACL 128 -#else -#ifdef CONFIG_RTL8196B_TLD -#define NUM_ACL 64 -#else -#define NUM_ACL 32 -#endif -#endif - -#define NUM_GBWC 64 -#define NUM_SBWC 64 - -#ifdef __ECOS -#ifdef CONFIG_RTL_WDS_SUPPORT -#define NUM_WDS RTLPKG_DEVS_ETH_RLTK_819X_WLAN_WDS_NUM -#else -#define NUM_WDS 0 -#endif -#else -#if defined(CONFIG_RTL8196C_EC) //no WDS or only one WDS -#define NUM_WDS 1 -#else -#if defined(CONFIG_RTL8196B_GW_8M) || defined(CONFIG_RTL8196C_AP_ROOT) || defined(CONFIG_RTL8198_AP_ROOT) -#define NUM_WDS 4 -#else -#define NUM_WDS 8 -#endif -#endif -#endif - -#define MESH_ID_LEN 32 - -#if !defined(_LITTLE_ENDIAN_) && !defined(_BIG_ENDIAN_) - #define _BIG_ENDIAN_ -#ifdef __MIPSEL__ //eric-8822 97f - #undef _BIG_ENDIAN_ - #define _LITTLE_ENDIAN_ -#endif -#endif - -struct Dot11StationConfigEntry { - unsigned char dot11Bssid[MACADDRLEN]; - unsigned char dot11DesiredSSID[32]; - unsigned int dot11DesiredSSIDLen; - unsigned char dot11DefaultSSID[32]; - unsigned int dot11DefaultSSIDLen; - unsigned char dot11SSIDtoScan[32]; - unsigned int dot11SSIDtoScanLen; - unsigned char dot11DesiredBssid[6]; - unsigned char dot11OperationalRateSet[32]; - unsigned int dot11OperationalRateSetLen; - - unsigned int dot11BeaconPeriod; - unsigned int dot11DTIMPeriod; - unsigned int dot11swcrypto; - unsigned int dot11AclMode; // 1: positive check 2: negative check - unsigned char dot11AclAddr[NUM_ACL][MACADDRLEN]; - unsigned int dot11AclNum; // acl entry number, this field should be followed to dot11AclAddr - unsigned int dot11SupportedRates; // bit mask value. bit0-bit11 as 1,2,5.5,11,6,9,12,18,24,36,48,54 - unsigned int dot11BasicRates; // bit mask value. bit0-bit11 as 1,2,5.5,11,6,9,12,18,24,36,48,54 - unsigned int dot11RegDomain; // reguration domain - int txpwr_lmt_index; // TX Power Limit Index - unsigned int autoRate; // enable/disable auto rate - unsigned int fixedTxRate; // fix tx rate - int swTkipMic; - int protectionDisabled; // force disable protection - int olbcDetectDisabled; // david, force disable olbc dection - int nmlscDetectDisabled; // hf, force disable no member legacy station condition detection - int legacySTADeny; // deny association from legacy (11B) STA - - //unsigned int w52_passive_scan; - int fastRoaming; // 1: enable fast-roaming, 0: disable - unsigned int lowestMlcstRate; // 1: use lowest basic rate to send multicast - unsigned int supportedStaNum; // limit supported station number - unsigned int staAssociateRSSIThreshold; - unsigned int staRoamingRSSIGap; - unsigned int staRoamingTimeGap; - unsigned int RmStaRSSIThreshold; - unsigned int probe_info_enable; // proc probe_info - unsigned int sc_enabled; //0 is disable, 1 is enable - int sc_duration_time; //-1 is always parse, 0 stop parse, >0 parse all packets. - int sc_get_sync_time; //unit is second - int sc_get_profile_time; //unit is second - int sc_vxd_rescan_time; //unit is second - int sc_connect_timeout; //unit is second - int sc_pin_enabled; // 1, MUST have PIN for SIMPLE CONFIG - int sc_status; //0 is not running, -1 is timeout, 1<=x<10 runing, >10 finish - int sc_debug; - unsigned char sc_pin[65]; - unsigned char sc_default_pin[65]; - unsigned char sc_passwd[65]; - unsigned char sc_device_name[64]; - unsigned short sc_device_type; - int sc_ack_round; - int sc_check_link_time; - int sc_sync_vxd_to_root; - unsigned int sc_control_ip; - int sc_check_level; //default value is 2. 0, don't check packet length; 1, check the first profile packet length; 2, check all profile packet length - int sc_ignore_overlap; //0, Simple Config will fail when more than one Smart Phone send config packet. 1, ignore overlap device packet. - int sc_reset_beacon_psk; //0, close/open interface when receive profile and try to connect remote AP; 1. reset psk and beacon only when try to connect remote AP - int sc_security_type; - int sc_fix_channel; //0, don't fix channel; others, the remote AP's channel - int sc_fix_encrypt; //0, not fix; >0, fix - int sc_config_type; - - int sc_fix_bw; - int sc_fix_offset; - int del_expire_station; - unsigned int limit_rxloop; - unsigned char wnmtest; - unsigned char deauth_mac[MACADDRLEN]; //CONFIG_IEEE80211W - unsigned char sa_req_mac[MACADDRLEN]; //CONFIG_IEEE80211W_CLI - unsigned char pmf_cli_test; // CONFIG_IEEE80211W_CLI - unsigned char pmftest; // CONFIG_IEEE80211W - unsigned int bcastSSID_inherit; - unsigned int beacon_rate; - unsigned int prsp_rate; - unsigned int disable_prsp; - //unsigned int channel_utili_beaconIntval; - - /* below is for 802.11k radio measurement*/ - unsigned char dot11RadioMeasurementActivated; - unsigned char dot11RMLinkMeasurementActivated; - unsigned char dot11RMNeighborReportActivated; - unsigned char dot11RMBeaconPassiveMeasurementActivated; - unsigned char dot11RMBeaconActiveMeasurementActivated; - unsigned char dot11RMBeaconTableMeasurementActivated; - unsigned char dot11RMAPChannelReportActivated; - unsigned int dot11RMNeighborReportExpireTime; - - /*below is for BT Config*/ - unsigned int rtkBtconfig; - unsigned char cu_enable; /*[CLM, channel loading measurement] channel utilization calculated enable/disable*/ - -}; - -/* add for 802.11d */ -struct Dot1180211CountryCodeEntry { - unsigned int dot11CountryCodeSwitch; // 1=enabled; 0=disabled - unsigned char dot11CountryString[3]; -}; - -// Detect STA for disappearing; added by Annie, 2010-08-10. -struct StaDetectInfo { - unsigned char txRprDetectPeriod; // period to send H2C command for Tx report infoormation; in second. -}; - -struct Dot1180211AuthEntry { - unsigned int dot11AuthAlgrthm; // 802.11 auth, could be open, shared, auto - unsigned char dot11PrivacyAlgrthm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 - unsigned int dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. - unsigned int dot11PrivacyKeyLen; // this could be 40 or 104 - int dot11EnablePSK; // 0: disable, bit0: WPA, bit1: WPA2 - int dot11WPACipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 - int dot11WPA2Cipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 - unsigned char dot11PassPhrase[65]; // passphrase - unsigned char dot11PassPhraseGuest[65]; // passphrase of guest - unsigned long dot11GKRekeyTime; // group key rekey time, 0 - disable - unsigned long dot11UKRekeyTime; // unicast key rekey time, 0 - disable - unsigned char dot11IEEE80211W; // 0: disabled, 1: capable, 2:required - unsigned char dot11EnableSHA256; // 0: disabled, 1: enabled -}; - -struct Dot118021xAuthEntry { - unsigned int dot118021xAlgrthm; // could be null, 802.1x/PSK - unsigned int dot118021xDefaultPort; // used as AP mode for default ieee8021x control port - unsigned int dot118021xcontrolport; - unsigned int acct_enabled; - unsigned long acct_timeout_period; - unsigned int acct_timeout_throughput; -}; - -union Keytype { - unsigned char skey[16]; - unsigned int lkey[4]; -}; - -struct Dot11DefaultKeysTable { - union Keytype keytype[4]; -}; - -union TSC48 { - unsigned long long val48; - -#if defined _LITTLE_ENDIAN_ - struct { - unsigned char TSC0; - unsigned char TSC1; - unsigned char TSC2; - unsigned char TSC3; - unsigned char TSC4; - unsigned char TSC5; - unsigned char TSC6; - unsigned char TSC7; - } _byte_; - -#elif defined _BIG_ENDIAN_ - struct { - unsigned char TSC7; - unsigned char TSC6; - unsigned char TSC5; - unsigned char TSC4; - unsigned char TSC3; - unsigned char TSC2; - unsigned char TSC1; - unsigned char TSC0; - } _byte_; - -#endif -}; - -union PN48 { - unsigned long long val48; - -#if defined _LITTLE_ENDIAN_ - struct { - unsigned char TSC0; - unsigned char TSC1; - unsigned char TSC2; - unsigned char TSC3; - unsigned char TSC4; - unsigned char TSC5; - unsigned char TSC6; - unsigned char TSC7; - } _byte_; - -#elif defined _BIG_ENDIAN_ - struct { - unsigned char TSC7; - unsigned char TSC6; - unsigned char TSC5; - unsigned char TSC4; - unsigned char TSC3; - unsigned char TSC2; - unsigned char TSC1; - unsigned char TSC0; - } _byte_; - -#endif -}; - -struct Dot11EncryptKey -{ - unsigned int dot11TTKeyLen; - unsigned int dot11TMicKeyLen; - union Keytype dot11TTKey; - union Keytype dot11TMicKey1; - union Keytype dot11TMicKey2; - union PN48 dot11TXPN48; - union PN48 dot11RXPN48; -}; - -struct Dot11KeyMappingsEntry { - unsigned int dot11Privacy; - unsigned int keyInCam; // Is my key in CAM? - unsigned int keyid; - struct Dot11EncryptKey dot11EncryptKey; - struct Dot11EncryptKey dot11EncryptKey2; -}; - -struct Dot11RsnIE { - unsigned char rsnie[128]; - unsigned char rsnielen; -}; - -struct Dot11OperationEntry { - unsigned char hwaddr[MACADDRLEN]; - unsigned int opmode; - unsigned int hiddenAP; - unsigned int dot11RTSThreshold; - unsigned int dot11FragmentationThreshold; - unsigned int dot11ShortRetryLimit; - unsigned int dot11LongRetryLimit; - unsigned int expiretime; - unsigned int ledtype; - unsigned int ledroute; - unsigned int iapp_enable; - unsigned int block_relay; - unsigned int deny_any; - unsigned int crc_log; - unsigned int wifi_specific; - unsigned int disable_txsc; - unsigned int disable_amsdu_txsc; - unsigned int disable_rxsc; - unsigned int disable_brsc; - int keep_rsnie; - int guest_access; - unsigned char tdls_prohibited; - unsigned char tdls_cs_prohibited; -//#ifdef CONFIG_POWER_SAVE - unsigned int ps_level; - unsigned int ps_timeout; -//#endif -//#ifdef LIFETIME_FEATURE - unsigned int lifetime; //unit: millisecond -//#endif -}; - -struct Dot11RFEntry { - unsigned int dot11RFType; - unsigned char dot11channel; - unsigned char band5GSelected; // bit0: Band1, bit1: Band2, bit2: Band3, bit3: Band4 - unsigned int dot11ch_low; - unsigned int dot11ch_hi; - unsigned char pwrlevelCCK_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelCCK_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelCCK_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelCCK_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelHT40_1S_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelHT40_1S_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelHT40_1S_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevelHT40_1S_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiffHT40_2S[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiffHT20[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiffOFDM[MAX_2G_CHANNEL_NUM]; - unsigned char pwrlevel5GHT40_1S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrlevel5GHT40_1S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrlevel5GHT40_1S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrlevel5GHT40_1S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff5GHT40_2S[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff5GHT20[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff5GOFDM[MAX_5G_CHANNEL_NUM]; -// RTK_AC_SUPPORT - unsigned char pwrdiff_20BW1S_OFDM1T_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW2S_20BW2S_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM2T_CCK2T_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW3S_20BW3S_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_4OFDM3T_CCK3T_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW4S_20BW4S_A[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM4T_CCK4T_A[MAX_2G_CHANNEL_NUM]; - - unsigned char pwrdiff_5G_20BW1S_OFDM1T_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW2S_20BW2S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW3S_20BW3S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW4S_20BW4S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_RSVD_OFDM4T_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW1S_160BW1S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW2S_160BW2S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW3S_160BW3S_A[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW4S_160BW4S_A[MAX_5G_CHANNEL_NUM]; - - unsigned char pwrdiff_20BW1S_OFDM1T_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW2S_20BW2S_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM2T_CCK2T_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW3S_20BW3S_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM3T_CCK3T_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW4S_20BW4S_B[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM4T_CCK4T_B[MAX_2G_CHANNEL_NUM]; - - unsigned char pwrdiff_5G_20BW1S_OFDM1T_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW2S_20BW2S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW3S_20BW3S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW4S_20BW4S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_RSVD_OFDM4T_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW1S_160BW1S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW2S_160BW2S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW3S_160BW3S_B[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW4S_160BW4S_B[MAX_5G_CHANNEL_NUM]; - - unsigned char pwrdiff_20BW1S_OFDM1T_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW2S_20BW2S_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM2T_CCK2T_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW3S_20BW3S_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_4OFDM3T_CCK3T_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW4S_20BW4S_C[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM4T_CCK4T_C[MAX_2G_CHANNEL_NUM]; - - unsigned char pwrdiff_5G_20BW1S_OFDM1T_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW2S_20BW2S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW3S_20BW3S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW4S_20BW4S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_RSVD_OFDM4T_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW1S_160BW1S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW2S_160BW2S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW3S_160BW3S_C[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW4S_160BW4S_C[MAX_5G_CHANNEL_NUM]; - - unsigned char pwrdiff_20BW1S_OFDM1T_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW2S_20BW2S_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM2T_CCK2T_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW3S_20BW3S_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_4OFDM3T_CCK3T_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_40BW4S_20BW4S_D[MAX_2G_CHANNEL_NUM]; - unsigned char pwrdiff_OFDM4T_CCK4T_D[MAX_2G_CHANNEL_NUM]; - - unsigned char pwrdiff_5G_20BW1S_OFDM1T_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW2S_20BW2S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW3S_20BW3S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_40BW4S_20BW4S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_RSVD_OFDM4T_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW1S_160BW1S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW2S_160BW2S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW3S_160BW3S_D[MAX_5G_CHANNEL_NUM]; - unsigned char pwrdiff_5G_80BW4S_160BW4S_D[MAX_5G_CHANNEL_NUM]; - - unsigned int defaultAntennaB; - unsigned int dot11DiversitySupport; - unsigned int shortpreamble; - unsigned int trswitch; - unsigned int disable_ch14_ofdm; - unsigned int disable_scan_ch14; - unsigned int disable_ch1213; - unsigned int xcap; - unsigned int xcap2; - unsigned int share_xcap; - unsigned int tssi1; - unsigned int tssi2; - unsigned int ther; - unsigned int ther2; - unsigned int deltaIQK; - unsigned int deltaLCK; - unsigned int MIMO_TR_mode; - unsigned char phyBandSelect; - unsigned char macPhyMode; - unsigned int smcc; - unsigned int smcc_t; - unsigned int smcc_p; - unsigned char trsw_pape_C9; - unsigned char trsw_pape_CC; - unsigned int tx2path; - unsigned int tx3path; - unsigned int tx4path; - unsigned int txbf; - unsigned int txbfer; - unsigned int txbfee; - unsigned int txbf_mu; - unsigned int target_pwr; - unsigned char bcn2path; - unsigned char bcnagc; - unsigned char add_cck1M_pwr; - unsigned int pa_type; - unsigned char txpwr_reduction; - unsigned char rfe_type; - unsigned int acs_type; - unsigned int acs2_dis_clean_channel; - unsigned int acs2_round; // 200ms per round - unsigned int acs2_clm_weighting_mode; - unsigned int acs2_cca_cap_db; - unsigned char power_percent; - unsigned char kfree_enable; - unsigned int periodicAutochannel; - unsigned int dynamicACS_noise; - unsigned int dynamicACS_idle; -}; - -struct ibss_priv { - unsigned short atim_win; -}; - -#if defined(CONFIG_RTL_WAPI_SUPPORT) -#define SECURITY_INFO_WAPI 0xa5a56789 -#endif -struct bss_desc { - unsigned char bssid[MACADDRLEN]; - unsigned char ssid[32]; - unsigned char *ssidptr; // unused, for backward compatible - unsigned short ssidlen; - unsigned char meshid[MESH_ID_LEN]; - unsigned char *meshidptr; // unused, for backward compatible - unsigned short meshidlen; - unsigned int bsstype; - unsigned short beacon_prd; - unsigned char dtim_prd; - unsigned int t_stamp[2]; - struct ibss_priv ibss_par; - unsigned short capability; - unsigned char channel; - unsigned int basicrate; - unsigned int supportrate; - unsigned char bdsa[MACADDRLEN]; - unsigned char rssi; - unsigned char sq; - unsigned char network; - /*add for P2P_SUPPORT ; for sync; it exist no matter p2p enabled or not*/ - unsigned char p2pdevname[33]; - unsigned char p2prole; - unsigned short p2pwscconfig; - unsigned char p2paddress[MACADDRLEN]; - /* multi-stage 2.3.0 */ - unsigned char stage; - /*cfg p2p cfg p2p*/ - #if defined(WIFI_WPAS) || defined(RTK_NL80211) - #if 0 - unsigned char p2p_ie_len; - unsigned char p2p_ie[256]; - unsigned char wscie_len; - unsigned char wscie[256]; - #endif - struct ht_info_elmt ht_info; - struct ht_cap_elmt ht_cap; - #endif - #if defined(WIFI_WPAS) || defined(RTK_NL80211) || defined(CONFIG_RTL_COMAPI_WLTOOLS) - unsigned char wpa_ie_len; - unsigned char wpa_ie[256]; - unsigned char rsn_ie_len; - unsigned char rsn_ie[256]; - #endif - /*cfg p2p cfg p2p*/ -}; - -struct bss_type -{ - unsigned char net_work_type; -}; - -struct erp_mib { - int protection; // protection mechanism flag - int nonErpStaNum; // none ERP client assoication num - int olbcDetected; // OLBC detected - int olbcExpired; // expired time of OLBC state - int shortSlot; // short slot time flag - int ctsToSelf; // CTStoSelf flag - int longPreambleStaNum; // number of assocated STA using long preamble -}; - -struct wdsEntry { - unsigned char macAddr [MACADDRLEN]; - unsigned int txRate __attribute__ ((packed)); -}; - -struct wds_info { - int wdsEnabled; - int wdsPure; // act as WDS bridge only, no AP function - int wdsPriority; // WDS packets have higer priority - struct wdsEntry entry[NUM_WDS]; - int wdsNum; // number of WDS used - int wdsPrivacy; - unsigned char wdsWepKey[32]; - unsigned char wdsMapingKey[NUM_WDS][32]; - int wdsMappingKeyLen[NUM_WDS]; - int wdsKeyId; - unsigned char wdsPskPassPhrase[65]; -}; - -struct br_ext_info { - unsigned int nat25_disable; - unsigned int macclone_enable; - unsigned int dhcp_bcst_disable; - int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable - unsigned char nat25_dmzMac[MACADDRLEN]; - unsigned int nat25sc_disable; - unsigned int macclone_method; // WiFi STA clone method - unsigned int macclone_eth_method; // Eth STA clone method -}; - -struct Dot11DFSEntry { - unsigned int disable_DFS; // 1 or 0 - unsigned int disable_tx; // 1 or 0 - unsigned int DFS_timeout; // set to 10 ms - unsigned int DFS_detected; // 1 or 0 - unsigned int NOP_timeout; // set to 30 mins - unsigned int DFS_TXPAUSE_timeout; - unsigned int CAC_enable; // 1 or 0 - unsigned int CAC_ss_counter; - unsigned int reserved1; - unsigned int reserved2; - unsigned int reserved3; - unsigned int reserved4; -}; - -struct Dot11hTPCEntry { - unsigned char tpc_enable; // 1 or 0 - unsigned char tpc_tx_power; - unsigned char tpc_link_margin; - unsigned char min_tx_power; - unsigned char max_tx_power; -}; - - -struct MiscEntry { - unsigned int show_hidden_bss; - unsigned int ack_timeout; - unsigned int reserved1; - unsigned int reserved2; - unsigned char private_ie[32]; - unsigned int private_ie_len; - unsigned int set_vlanid; - unsigned int rxInt_thrd; - unsigned int drvmac_lb; - unsigned char lb_da[6]; - unsigned int lb_tps; - unsigned int lb_mlmp; - unsigned int groupID; - unsigned int vap_enable; - unsigned int rsv_txdesc; // 1: enable "reserve tx desc for each interface" function; 0: disable. - unsigned int use_txq; - unsigned int func_off; - unsigned int auto_rts_mode; - //TCP_ACK_ACC - unsigned int tcpack_acc; - unsigned int tcpack_to; - unsigned int tcpack_to_2g; - unsigned int tcpack_use_hw_timer; - unsigned int tcpack_delay_start; - unsigned int tcpack_cnt_th1; - unsigned int tcpack_cnt_th2; - unsigned int tcpack_rx_th1; - unsigned int tcpack_rx_th2; - unsigned int tcpack_rx_th3; - - unsigned int raku_only; - unsigned int tv_mode; // 0: disable, 1: enable, 2: auto - unsigned int stage; - unsigned int forward_streaming; // 0: disable, 1: enable - unsigned int passive_ss_int; - unsigned int ss_delay; - unsigned int ss_loop_delay; - unsigned int chan_switch_time; - unsigned int chan_switch_disable; - unsigned int pkt_filter_len; - unsigned int autoch_ss_to;//AUTOCH_SS_SPEEDUP - unsigned int autoch_ss_cnt;//AUTOCH_SS_SPEEDUP - unsigned int autoch_1611_enable;//AUTOCH_SS_SPEEDUP - unsigned int max_xmitbuf_agg; - unsigned int max_recvbuf_agg; - unsigned int max_handle_xmitbuf; - unsigned int max_handle_recvbuf; - unsigned int drop_rxpkt_en; - unsigned int drop_rxpkt_len; - unsigned int drop_rxpkt_rate; - unsigned int G5_drop_rxpkt_rate; - unsigned int G5G24_drop_rxpkt_rate; - unsigned int client_host_sniffer_enable; - unsigned int manual_priority; - unsigned int clm; - unsigned int nhm; -}; - -struct ParaRecord { - unsigned int ACM; - unsigned int AIFSN; - unsigned int ECWmin; - unsigned int ECWmax; - unsigned int TXOPlimit; -}; - -struct Dot11QosEntry { - unsigned int dot11QosEnable; // 0=disable, 1=enable - unsigned int dot11QosAPSD; // 0=disable, 1=enable - unsigned int EDCAparaUpdateCount; // default=0, increases if any STA_AC_XX_paraRecord updated - unsigned int EDCA_STA_config; // WMM STA, default=0, will be set when assoc AP's EDCA para have been set - unsigned char WMM_IE[7]; // WMM STA, WMM IE - unsigned char WMM_PARA_IE[24]; // WMM EDCA Parameter IE - unsigned int UAPSD_AC_BE; - unsigned int UAPSD_AC_BK; - unsigned int UAPSD_AC_VI; - unsigned int UAPSD_AC_VO; - - struct ParaRecord STA_AC_BE_paraRecord; - struct ParaRecord STA_AC_BK_paraRecord; - struct ParaRecord STA_AC_VI_paraRecord; - struct ParaRecord STA_AC_VO_paraRecord; -//#ifdef RTL_MANUAL_EDCA - unsigned int ManualEDCA; // 0=disable, 1=enable - struct ParaRecord AP_manualEDCA[4]; - struct ParaRecord STA_manualEDCA[4]; - unsigned char TID_mapping[8]; // 1: BK, 2: BE, 3: VI, 4: VO -}; - -struct WifiSimpleConfigEntry { - unsigned int wsc_enable; - unsigned char beacon_ie[256]; - int beacon_ielen; - unsigned char probe_rsp_ie[256]; - int probe_rsp_ielen; - unsigned char probe_req_ie[256]; - int probe_req_ielen; - unsigned char assoc_ie[256]; - int assoc_ielen; - unsigned int both_band_multicredential; -}; - -struct GroupBandWidthControl { - unsigned int GBWCMode; // 0: disable 1: inner limitation 2: outer limitation 3: tx interface 4: rx interface 5: tx+rx interface - unsigned char GBWCAddr[NUM_GBWC][MACADDRLEN]; - unsigned int GBWCNum; // GBWC entry number, this field should be followed to GBWCAddr - unsigned int GBWCThrd_tx; // Tx Threshold, in unit of kbps - unsigned int GBWCThrd_rx; // Rx Threshold, in unit of kbps -}; - -struct SBWC_ENTRY { - unsigned char mac[MACADDRLEN]; - unsigned int tx_lmt; - unsigned int rx_lmt; -}; - -struct StaBandwidthControl { - unsigned int count; - struct SBWC_ENTRY entry[NUM_SBWC]; -}; - -struct Dot11nConfigEntry { - unsigned int dot11nSupportedMCS; - unsigned int dot11nBasicMCS; - unsigned int dot11nUse40M; // 0: 20M, 1: 40M - unsigned int dot11n2ndChOffset; // 0: don't care, 1: below the primary, 2: above the primary - unsigned int dot11nShortGIfor20M; - unsigned int dot11nShortGIfor40M; - unsigned int dot11nShortGIfor80M; - unsigned int dot11nSTBC; - unsigned int dot11nLDPC; - unsigned int dot11nAMPDU; - unsigned int dot11nAMSDU; - unsigned int dot11nAMPDUSendSz; // 8: 8K, 16: 16K, 32: 32K, 64: 64K, other: auto - unsigned int dot11nAMPDURevSz; - unsigned int dot11nAMSDURecvMax; // 0: 4K, 1: 8K - unsigned int dot11nAMSDUSendTimeout; // timeout value to queue AMSDU packets - unsigned int dot11nAMSDUSendNum; // max aggregation packet number - unsigned int dot11curAMSDUSendNum; // current AMSDU packet number - unsigned int dot11nLgyEncRstrct; // bit0: Wep, bit1: TKIP, bit2: restrict Realtek client, bit3: forbid N mode for legacy enc - unsigned int dot11nCoexist; - unsigned int dot11nCoexist_ch_chk; // coexist channel chaek - unsigned int dot11nCoexist_obss_scan;// 0: disable, 1: active scan, 2: passive scan - unsigned int dot11nBGAPRssiChkTh; - unsigned int dot11nTxNoAck; - unsigned int dot11nAddBAreject; //add for support sigma test - unsigned int dot11nDisable2RCCA; -}; - -struct Dot11acConfigEntry { - unsigned int dot11SupportedVHT; // b[1:0]: NSS1, b[3:2]: NSS2 - unsigned int dot11VHT_TxMap; // b[19:10]: NSS2 MCS9~0, b[9:0]: NSS1 MCS9~0 -}; - -struct ReorderControlEntry { - unsigned int ReorderCtrlEnable; - unsigned int reserved; - unsigned int ReorderCtrlWinSz; - unsigned int ReorderCtrlTimeout; - unsigned int ReorderCtrlTimeoutCli; -}; - -struct Dot1180211sInfo{ - unsigned char meshSilence; // active when pure Mesh Mode but not enabled - unsigned char mesh_enable; - unsigned char mesh_root_enable; - unsigned char mesh_ap_enable; - unsigned char mesh_portal_enable; - unsigned char mesh_id[32]; - unsigned short mesh_max_neightbor; - unsigned char log_enabled; // content from webpage setting MIB_LOG_ENABLED (bitmap) - unsigned char dot11PassPhrase[65]; // passphrase - - unsigned int mesh_acl_mode; - unsigned char mesh_acl_addr[NUM_ACL][MACADDRLEN]; - unsigned int mesh_acl_num; - - unsigned short mesh_reserved1; - unsigned short mesh_reserved2; - unsigned short mesh_reserved3; - unsigned short mesh_reserved4; - unsigned short mesh_reserved5; - unsigned short mesh_reserved6; - unsigned short mesh_reserved7; - unsigned short mesh_reserved8; - unsigned short mesh_reserved9; - unsigned short mesh_reserveda; - unsigned short mesh_reservedb; - unsigned short mesh_reservedc; - unsigned short mesh_reservedd; - unsigned short mesh_reservede; - unsigned short mesh_reservedf; - unsigned char mesh_reservedstr1[16]; -}; - -struct EfuseEntry { - unsigned int enable_efuse; -}; - -struct VlanConfig { - int global_vlan; // 0/1 - global vlan disable/enable - int is_lan; // 1: LAN port, 0: WAN port (per-port) - int vlan_enable; // 0/1: disable/enable vlan (per-port) - int vlan_tag; // 0/1: disable/enable tagging (per-port) - int vlan_id; // 1~4090: vlan id (per-port) - int vlan_pri; // 0~7: priority; (per-port) - int vlan_cfi; // 0/1: cfi (per-port) - int forwarding_rule; // 0: disable 1:L2 bridged 2:NAT -}; - -/* type define must accordint to the wapi standard */ -typedef enum __wapiMibType { - wapiDisable = 0, - wapiTypeCert = 1, - wapiTypePSK = 2 -} wapiMibType; - -#define WAPI_PSK_LEN 32 -typedef struct __wapiMibPSK { - unsigned char octet[WAPI_PSK_LEN]; - unsigned int len; -} wapiMibPSK; - -typedef enum __wapiMibTimeoutType { - wapiTimeoutStart = 0, - wapiTimeoutTotalNum = 1 -} wapiMibTimeoutType; - -typedef unsigned int wapiMibTimeout; - -/* Currently only one encrypt algorithm was supported, -* we need NOT to record it -*/ -typedef enum __wapiMibEncryptAlgorithm { - wapi_SMS4 = 1 -} wapiMibEncryptAlgorithm; - -typedef enum __wapiMibKeyUpdateType { - wapi_disable_update = 1, - wapi_time_update = 2, - wapi_pktnum_update = 3, - wapi_all_update = 4 -} wapiMibKeyUpdateType; - -typedef struct __wapiMibInfo { - wapiMibType wapiType; - wapiMibEncryptAlgorithm wapiUCastEncodeType; - wapiMibEncryptAlgorithm wapiMCastEncodeType; - wapiMibPSK wapiPsk; - wapiMibKeyUpdateType wapiUpdateUCastKeyType; - unsigned long wapiUpdateUCastKeyTimeout; - unsigned long wapiUpdateUCastKeyPktNum; - wapiMibKeyUpdateType wapiUpdateMCastKeyType; - unsigned long wapiUpdateMCastKeyTimeout; - unsigned long wapiUpdateMCastKeyPktNum; - wapiMibTimeout wapiTimeout[wapiTimeoutTotalNum]; -} wapiMibInfo; - -/*for HS2_SUPPORT*/ -#define MAX_DSCP_EXCEPT 4 -#define MAX_QOS_PRIORITY 8 -struct HotSpotConfigEntry { - unsigned int hs_enable; - unsigned char hs2_ie[256]; - int hs2_ielen; - unsigned char interworking_ie[256]; - int interworking_ielen; - unsigned char QoSMap_ie[2][256]; - unsigned char QoSMap_ielen[2]; - unsigned char QoSMAP_range[MAX_QOS_PRIORITY][2]; - unsigned char QoSMAP_except[MAX_DSCP_EXCEPT][2]; - unsigned char nQoSMap; - unsigned char curQoSMap; - unsigned char advt_proto_ie[256]; - int advt_proto_ielen; - unsigned char roam_ie[256]; - int roam_ielen; - unsigned char timeadvt_ie[20]; - int timeadvt_ielen; - unsigned char timezone_ie[10]; - int timezone_ielen; - unsigned char MBSSID_ie[256]; - int MBSSID_ielen; - unsigned char remedSvrURL[256]; - - unsigned char serverMethod; - - unsigned char SessionInfoURL[256]; - unsigned char bssload_ie[5]; - // unsigned int channel_utili_beaconIntval; - unsigned int timeadvt_DTIMIntval; - unsigned int reqmode; - unsigned int disassoc_timer; - unsigned int validity_intval; - unsigned char session_url[50]; - unsigned char sta_mac[MACADDRLEN]; - unsigned char redir_mac[MACADDRLEN]; - unsigned char remed_mac[MACADDRLEN]; - unsigned int roam_enable; - unsigned int mmpdu_limit; - unsigned int bssload; - unsigned int radioOff; - unsigned int ICMPv4ECHO; -}; - -/*for P2P_SUPPORT*/ -struct P2P_Direct { -/*cfg p2p cfg p2p*/ - unsigned char p2p_enabled; - unsigned char p2p_type; - unsigned char p2p_state; - unsigned char p2p_on_discovery; - unsigned char p2p_intent; - unsigned char p2p_listen_channel; - unsigned char p2p_op_channel; -/*cfg p2p cfg p2p*/ - unsigned char p2p_event_indiate; - - unsigned char p2p_device_name[33]; - unsigned char p2p_wsc_pin_code[9]; - unsigned short p2p_wsc_config_method; - -}; - - -#define PROFILE_NUM 5 // must reserve one for root profile. - -struct ap_profile { - char ssid[33]; // desired SSID in string - int encryption; // 0: open, 1:wep40, 2:wep128, 3:wpa, 4:wpa2 - int auth_type; // authentication type. 0: open, 1: shared, 2: auto - int wpa_cipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 - unsigned char wpa_psk[65]; // wpa psk - int wep_default_key; // wep default tx key index, 0~3 - unsigned char wep_key1[13]; // WEP key1 in hex - unsigned char wep_key2[13]; // WEP key2 in hex - unsigned char wep_key3[13]; // WEP key3 in hex - unsigned char wep_key4[13]; // WEP key4 in hex - int MulticastCipher; - unsigned char bss_PMF; -}; - -struct ap_conn_profile { // ap connection profile - int enable_profile; - int profile_num; // profile number, except root profile. - int sortbyprofile; - struct ap_profile profile[PROFILE_NUM]; -}; - -struct StaControl { - unsigned char stactrl_enable; //0:disable, 1:enable - unsigned char stactrl_groupID; - unsigned char stactrl_prefer_band; //0: disable, 1: enable - unsigned int stactrl_param_1; // rssi threshold - unsigned int stactrl_param_2; // rssi threshold tolerance - unsigned int stactrl_param_3; // timer X - unsigned int stactrl_param_4; // retry Y - unsigned int stactrl_param_5; // timer Z - unsigned int stactrl_param_6; // rssi threshold for non-prefer band - unsigned int stactrl_param_7; // kickoff times //20170103 - unsigned int stactrl_param_8; // kickoff times //20170106 - unsigned int stactrl_param_9; - unsigned char stactrl_param_10; - unsigned char stactrl_functions; // BIT(0)-block5G feature, BIT(1)-hiddenAP feature -}; - -struct SmartRoamingProfile { - unsigned char block_aging; - unsigned int tp_max; - unsigned char signal_max; - unsigned char signal_min; - unsigned char load_min; - unsigned char speed_weight; - unsigned char signal_weight; - unsigned char load_weight; - unsigned char enable; -}; - -struct MeshPathsel{ - unsigned char mesh_crossbandEnable; - unsigned char mesh_rssiThreshold; - unsigned char mesh_cuThreshold; - unsigned char mesh_noiseThreshold; - unsigned char mesh_rssiWeight; - unsigned char mesh_cuWeight; - unsigned char mesh_noiseWeight; -}; - -struct CrossBand{ - unsigned char crossband_enable; //0:disable, 1:enable - unsigned char crossband_prefer; //1: preferred interface 0: not preferred interface - unsigned char crossband_assoc; //1: Yes, 0: no, interface is associated to remote AP - unsigned char crossband_pathReady; //1: Yes, 0: No, both interfaces are connected - unsigned char crossband_cuThreshold; //channel utilization threshold - unsigned char crossband_noiseThreshold; //noise threshold - unsigned char crossband_rssiThreshold; //rssi threshold - unsigned char crossband_cuWeight; //channel utilization weight - unsigned char crossband_noiseWeight; //noise weight - unsigned char crossband_rssiWeight; //rssi weight -}; - -struct Dot11FastBSSTransitionEntry { - int dot11FastBSSTransitionEnabled; - unsigned char dot11FTMobilityDomainID[2]; - int dot11FTOverDSEnabled; - int dot11FTResourceRequestSupported; - unsigned char dot11FTR0KeyHolderID[49]; - unsigned int dot11FTR0KeyHolderIDLen; - int dot11FTReassociationDeadline; - int dot11FTR0KeyLifetime; - int dot11FTR1KeyPushEnable; - int dot11FT4way; -}; - -//RTK_ATM -/* Airtime Management Config Entry*/ -struct atm_stainfo { - unsigned char hwaddr[MACADDRLEN]; - unsigned char ipaddr[4]; - int atm_time; -}; - -struct ATMConfigEntry { - int atm_en; //enable/disable - int atm_mode; //0:auto 1:interface 2:client - int atm_iftime[1+4+1]; //Root+4*VAP+VXD, interface mode - struct atm_stainfo atm_sta[64]; //64 client list, clietn dmoe -}; - -struct Dot11WNMEntry { - unsigned char dot11vBssTransEnable; - unsigned char dot11vReqMode; - unsigned char dot11vDiassocImminent; - unsigned char sta_mac[MACADDRLEN]; - unsigned short dot11vDiassocDeadline; - unsigned char bssTransExpiredTime; - unsigned char Is11kDaemonOn; - unsigned char algoType; - unsigned char defaultPrefVal; -}; - -struct HalQcDebug { - unsigned int HalDbgCom; - unsigned int HalDbgLev; -}; - -struct Dot11RFDPKEntry { - /* DPK 2G parameters */ - unsigned char bDPPathAOK; - unsigned char bDPPathBOK; - unsigned char pwsf_2g_a[3]; - unsigned char pwsf_2g_b[3]; - unsigned int lut_2g_even_a[3][64]; - unsigned int lut_2g_odd_a[3][64]; - unsigned int lut_2g_even_b[3][64]; - unsigned int lut_2g_odd_b[3][64]; - - /* DPK 5G parameters */ - unsigned char is_5g_pdk_patha_ok; - unsigned char is_5g_pdk_pathb_ok; - unsigned int pwsf_5g_a[9]; - unsigned int pwsf_5g_b[9]; - unsigned int lut_5g_even_a[9][16]; - unsigned int lut_5g_odd_a[9][16]; - unsigned int lut_5g_even_b[9][16]; - unsigned int lut_5g_odd_b[9][16]; -}; - - -// driver mib -struct wifi_mib { - unsigned int mib_version; - struct Dot11StationConfigEntry dot11StationConfigEntry; - struct Dot1180211AuthEntry dot1180211AuthEntry; - struct Dot118021xAuthEntry dot118021xAuthEntry; - struct Dot11DefaultKeysTable dot11DefaultKeysTable; - struct Dot11KeyMappingsEntry dot11GroupKeysTable; - struct Dot11KeyMappingsEntry dot11IGTKTable; //CONFIG_IEEE80211W - struct Dot11RsnIE dot11RsnIE; - struct Dot11OperationEntry dot11OperationEntry; - struct Dot11RFEntry dot11RFEntry; - struct bss_desc dot11Bss; - struct bss_type dot11BssType; - struct erp_mib dot11ErpInfo; - struct wds_info dot11WdsInfo; - struct br_ext_info ethBrExtInfo; - struct Dot11DFSEntry dot11DFSEntry; - struct Dot11hTPCEntry dot11hTPCEntry; - struct MiscEntry miscEntry; - struct Dot11QosEntry dot11QosEntry; - struct WifiSimpleConfigEntry wscEntry; - struct GroupBandWidthControl gbwcEntry; - struct StaBandwidthControl sbwcEntry; - struct Dot11nConfigEntry dot11nConfigEntry; - struct Dot11acConfigEntry dot11acConfigEntry; - struct ReorderControlEntry reorderCtrlEntry; - struct VlanConfig vlan; - struct Dot1180211sInfo dot1180211sInfo; - struct Dot11KeyMappingsEntry dot11sKeysTable; - struct __wapiMibInfo wapiInfo; - struct Dot1180211CountryCodeEntry dot11dCountry; - struct EfuseEntry efuseEntry; - struct StaDetectInfo staDetectInfo; - struct P2P_Direct p2p_mib; // add for P2P_SUPPORT - struct ap_conn_profile ap_profile; - struct HotSpotConfigEntry hs2Entry; // add for HS2_SUPPORT, Hotspot 2.0 Release 1 - struct Dot11FastBSSTransitionEntry dot11FTEntry; - struct StaControl staControl; // add for sta control - struct SmartRoamingProfile sr_profile; //add for smart roaming - struct MeshPathsel meshPathsel; - struct CrossBand crossBand; //add for crossband - keith - struct Dot11WNMEntry wnmEntry; - struct HalQcDebug qc_debug; // add for qc debug - struct Dot11RFDPKEntry dot11RFDPKEntry; -}; - -#endif // _IEEE802_MIB_H_ - +/* + * Header file defines IEEE802.11 MIB + * + * $Id: ieee802_mib.h,v 1.12.2.5 2010/12/16 05:32:20 bruce Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Note: Should not use compiler flag in this header file in order for + * flash utility to get correct mib size. + */ + +#ifndef _IEEE802_MIB_H_ +#define _IEEE802_MIB_H_ + +#ifdef __ECOS +#include +#include +#endif +#if defined(RTK_NL80211) +#include "wifi.h" +#endif +#define MIB_VERSION 32 + +#define MAX_2G_CHANNEL_NUM 14 +#define MAX_5G_CHANNEL_NUM 196 +#define MACADDRLEN 6 + +#if 1//def CONFIG_SDIO_HCI +#define SDIOTYPELEN 5 +#endif + +//------------------------------------------------------------- +// Support add or remove ACL list at run time +//------------------------------------------------------------- +#define D_ACL + +#ifdef D_ACL +#define NUM_ACL 128 +#else +#ifdef CONFIG_RTL8196B_TLD +#define NUM_ACL 64 +#else +#define NUM_ACL 32 +#endif +#endif + +#define NUM_GBWC 64 +#define NUM_SBWC 64 + +#ifdef __ECOS +#ifdef CONFIG_RTL_WDS_SUPPORT +#define NUM_WDS RTLPKG_DEVS_ETH_RLTK_819X_WLAN_WDS_NUM +#else +#define NUM_WDS 0 +#endif +#else +#if defined(CONFIG_RTL8196C_EC) //no WDS or only one WDS +#define NUM_WDS 1 +#else +#if defined(CONFIG_RTL8196B_GW_8M) || defined(CONFIG_RTL8196C_AP_ROOT) || defined(CONFIG_RTL8198_AP_ROOT) +#define NUM_WDS 4 +#else +#define NUM_WDS 8 +#endif +#endif +#endif + +#define MESH_ID_LEN 32 + +#if !defined(_LITTLE_ENDIAN_) && !defined(_BIG_ENDIAN_) + #define _BIG_ENDIAN_ +#ifdef __MIPSEL__ //eric-8822 97f + #undef _BIG_ENDIAN_ + #define _LITTLE_ENDIAN_ +#endif +#endif + +struct Dot11StationConfigEntry { + unsigned char dot11Bssid[MACADDRLEN]; + unsigned char dot11DesiredSSID[32]; + unsigned int dot11DesiredSSIDLen; + unsigned char dot11DefaultSSID[32]; + unsigned int dot11DefaultSSIDLen; + unsigned char dot11SSIDtoScan[32]; + unsigned int dot11SSIDtoScanLen; + unsigned char dot11DesiredBssid[6]; + unsigned char dot11OperationalRateSet[32]; + unsigned int dot11OperationalRateSetLen; + + unsigned int dot11BeaconPeriod; + unsigned int dot11DTIMPeriod; + unsigned int dot11swcrypto; + unsigned int dot11AclMode; // 1: positive check 2: negative check + unsigned char dot11AclAddr[NUM_ACL][MACADDRLEN]; + unsigned int dot11AclNum; // acl entry number, this field should be followed to dot11AclAddr + unsigned int dot11SupportedRates; // bit mask value. bit0-bit11 as 1,2,5.5,11,6,9,12,18,24,36,48,54 + unsigned int dot11BasicRates; // bit mask value. bit0-bit11 as 1,2,5.5,11,6,9,12,18,24,36,48,54 + unsigned int dot11RegDomain; // reguration domain + int txpwr_lmt_index; // TX Power Limit Index + unsigned int autoRate; // enable/disable auto rate + unsigned int fixedTxRate; // fix tx rate + int swTkipMic; + int protectionDisabled; // force disable protection + int olbcDetectDisabled; // david, force disable olbc dection + int nmlscDetectDisabled; // hf, force disable no member legacy station condition detection + int legacySTADeny; // deny association from legacy (11B) STA + + //unsigned int w52_passive_scan; + int fastRoaming; // 1: enable fast-roaming, 0: disable + unsigned int lowestMlcstRate; // 1: use lowest basic rate to send multicast + unsigned int supportedStaNum; // limit supported station number + unsigned int staAssociateRSSIThreshold; + unsigned int staRoamingRSSIGap; + unsigned int staRoamingTimeGap; + unsigned int RmStaRSSIThreshold; + unsigned int probe_info_enable; // proc probe_info + unsigned int sc_enabled; //0 is disable, 1 is enable + int sc_duration_time; //-1 is always parse, 0 stop parse, >0 parse all packets. + int sc_get_sync_time; //unit is second + int sc_get_profile_time; //unit is second + int sc_vxd_rescan_time; //unit is second + int sc_connect_timeout; //unit is second + int sc_pin_enabled; // 1, MUST have PIN for SIMPLE CONFIG + int sc_status; //0 is not running, -1 is timeout, 1<=x<10 runing, >10 finish + int sc_debug; + unsigned char sc_pin[65]; + unsigned char sc_default_pin[65]; + unsigned char sc_passwd[65]; + unsigned char sc_device_name[64]; + unsigned short sc_device_type; + int sc_ack_round; + int sc_check_link_time; + int sc_sync_vxd_to_root; + unsigned int sc_control_ip; + int sc_check_level; //default value is 2. 0, don't check packet length; 1, check the first profile packet length; 2, check all profile packet length + int sc_ignore_overlap; //0, Simple Config will fail when more than one Smart Phone send config packet. 1, ignore overlap device packet. + int sc_reset_beacon_psk; //0, close/open interface when receive profile and try to connect remote AP; 1. reset psk and beacon only when try to connect remote AP + int sc_security_type; + int sc_fix_channel; //0, don't fix channel; others, the remote AP's channel + int sc_fix_encrypt; //0, not fix; >0, fix + int sc_config_type; + + int sc_fix_bw; + int sc_fix_offset; + int del_expire_station; + unsigned int limit_rxloop; + unsigned char wnmtest; + unsigned char deauth_mac[MACADDRLEN]; //CONFIG_IEEE80211W + unsigned char sa_req_mac[MACADDRLEN]; //CONFIG_IEEE80211W_CLI + unsigned char pmf_cli_test; // CONFIG_IEEE80211W_CLI + unsigned char pmftest; // CONFIG_IEEE80211W + unsigned int bcastSSID_inherit; + unsigned int beacon_rate; + unsigned int prsp_rate; + unsigned int disable_prsp; + //unsigned int channel_utili_beaconIntval; + + /* below is for 802.11k radio measurement*/ + unsigned char dot11RadioMeasurementActivated; + unsigned char dot11RMLinkMeasurementActivated; + unsigned char dot11RMNeighborReportActivated; + unsigned char dot11RMBeaconPassiveMeasurementActivated; + unsigned char dot11RMBeaconActiveMeasurementActivated; + unsigned char dot11RMBeaconTableMeasurementActivated; + unsigned char dot11RMAPChannelReportActivated; + unsigned int dot11RMNeighborReportExpireTime; + + /*below is for BT Config*/ + unsigned int rtkBtconfig; + unsigned char cu_enable; /*[CLM, channel loading measurement] channel utilization calculated enable/disable*/ + +}; + +/* add for 802.11d */ +struct Dot1180211CountryCodeEntry { + unsigned int dot11CountryCodeSwitch; // 1=enabled; 0=disabled + unsigned char dot11CountryString[3]; +}; + +// Detect STA for disappearing; added by Annie, 2010-08-10. +struct StaDetectInfo { + unsigned char txRprDetectPeriod; // period to send H2C command for Tx report infoormation; in second. +}; + +struct Dot1180211AuthEntry { + unsigned int dot11AuthAlgrthm; // 802.11 auth, could be open, shared, auto + unsigned char dot11PrivacyAlgrthm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 + unsigned int dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. + unsigned int dot11PrivacyKeyLen; // this could be 40 or 104 + int dot11EnablePSK; // 0: disable, bit0: WPA, bit1: WPA2 + int dot11WPACipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 + int dot11WPA2Cipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 + unsigned char dot11PassPhrase[65]; // passphrase + unsigned char dot11PassPhraseGuest[65]; // passphrase of guest + unsigned long dot11GKRekeyTime; // group key rekey time, 0 - disable + unsigned long dot11UKRekeyTime; // unicast key rekey time, 0 - disable + unsigned char dot11IEEE80211W; // 0: disabled, 1: capable, 2:required + unsigned char dot11EnableSHA256; // 0: disabled, 1: enabled +}; + +struct Dot118021xAuthEntry { + unsigned int dot118021xAlgrthm; // could be null, 802.1x/PSK + unsigned int dot118021xDefaultPort; // used as AP mode for default ieee8021x control port + unsigned int dot118021xcontrolport; + unsigned int acct_enabled; + unsigned long acct_timeout_period; + unsigned int acct_timeout_throughput; +}; + +union Keytype { + unsigned char skey[16]; + unsigned int lkey[4]; +}; + +struct Dot11DefaultKeysTable { + union Keytype keytype[4]; +}; + +union TSC48 { + unsigned long long val48; + +#if defined _LITTLE_ENDIAN_ + struct { + unsigned char TSC0; + unsigned char TSC1; + unsigned char TSC2; + unsigned char TSC3; + unsigned char TSC4; + unsigned char TSC5; + unsigned char TSC6; + unsigned char TSC7; + } _byte_; + +#elif defined _BIG_ENDIAN_ + struct { + unsigned char TSC7; + unsigned char TSC6; + unsigned char TSC5; + unsigned char TSC4; + unsigned char TSC3; + unsigned char TSC2; + unsigned char TSC1; + unsigned char TSC0; + } _byte_; + +#endif +}; + +union PN48 { + unsigned long long val48; + +#if defined _LITTLE_ENDIAN_ + struct { + unsigned char TSC0; + unsigned char TSC1; + unsigned char TSC2; + unsigned char TSC3; + unsigned char TSC4; + unsigned char TSC5; + unsigned char TSC6; + unsigned char TSC7; + } _byte_; + +#elif defined _BIG_ENDIAN_ + struct { + unsigned char TSC7; + unsigned char TSC6; + unsigned char TSC5; + unsigned char TSC4; + unsigned char TSC3; + unsigned char TSC2; + unsigned char TSC1; + unsigned char TSC0; + } _byte_; + +#endif +}; + +struct Dot11EncryptKey +{ + unsigned int dot11TTKeyLen; + unsigned int dot11TMicKeyLen; + union Keytype dot11TTKey; + union Keytype dot11TMicKey1; + union Keytype dot11TMicKey2; + union PN48 dot11TXPN48; + union PN48 dot11RXPN48; +}; + +struct Dot11KeyMappingsEntry { + unsigned int dot11Privacy; + unsigned int keyInCam; // Is my key in CAM? + unsigned int keyid; + struct Dot11EncryptKey dot11EncryptKey; + struct Dot11EncryptKey dot11EncryptKey2; +}; + +struct Dot11RsnIE { + unsigned char rsnie[128]; + unsigned char rsnielen; +}; + +struct Dot11OperationEntry { + unsigned char hwaddr[MACADDRLEN]; + unsigned int opmode; + unsigned int hiddenAP; + unsigned int dot11RTSThreshold; + unsigned int dot11FragmentationThreshold; + unsigned int dot11ShortRetryLimit; + unsigned int dot11LongRetryLimit; + unsigned int expiretime; + unsigned int ledtype; + unsigned int ledroute; + unsigned int iapp_enable; + unsigned int block_relay; + unsigned int deny_any; + unsigned int crc_log; + unsigned int wifi_specific; + unsigned int disable_txsc; + unsigned int disable_amsdu_txsc; + unsigned int disable_rxsc; + unsigned int disable_brsc; + int keep_rsnie; + int guest_access; + unsigned char tdls_prohibited; + unsigned char tdls_cs_prohibited; +//#ifdef CONFIG_POWER_SAVE + unsigned int ps_level; + unsigned int ps_timeout; +//#endif +//#ifdef LIFETIME_FEATURE + unsigned int lifetime; //unit: millisecond +//#endif +}; + +struct Dot11RFEntry { + unsigned int dot11RFType; + unsigned char dot11channel; + unsigned char band5GSelected; // bit0: Band1, bit1: Band2, bit2: Band3, bit3: Band4 + unsigned int dot11ch_low; + unsigned int dot11ch_hi; + unsigned char pwrlevelCCK_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelCCK_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelCCK_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelCCK_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelHT40_1S_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelHT40_1S_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelHT40_1S_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevelHT40_1S_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiffHT40_2S[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiffHT20[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiffOFDM[MAX_2G_CHANNEL_NUM]; + unsigned char pwrlevel5GHT40_1S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrlevel5GHT40_1S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrlevel5GHT40_1S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrlevel5GHT40_1S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff5GHT40_2S[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff5GHT20[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff5GOFDM[MAX_5G_CHANNEL_NUM]; +// RTK_AC_SUPPORT + unsigned char pwrdiff_20BW1S_OFDM1T_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW2S_20BW2S_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM2T_CCK2T_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW3S_20BW3S_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_4OFDM3T_CCK3T_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW4S_20BW4S_A[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM4T_CCK4T_A[MAX_2G_CHANNEL_NUM]; + + unsigned char pwrdiff_5G_20BW1S_OFDM1T_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW2S_20BW2S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW3S_20BW3S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW4S_20BW4S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_RSVD_OFDM4T_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW1S_160BW1S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW2S_160BW2S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW3S_160BW3S_A[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW4S_160BW4S_A[MAX_5G_CHANNEL_NUM]; + + unsigned char pwrdiff_20BW1S_OFDM1T_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW2S_20BW2S_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM2T_CCK2T_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW3S_20BW3S_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM3T_CCK3T_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW4S_20BW4S_B[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM4T_CCK4T_B[MAX_2G_CHANNEL_NUM]; + + unsigned char pwrdiff_5G_20BW1S_OFDM1T_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW2S_20BW2S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW3S_20BW3S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW4S_20BW4S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_RSVD_OFDM4T_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW1S_160BW1S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW2S_160BW2S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW3S_160BW3S_B[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW4S_160BW4S_B[MAX_5G_CHANNEL_NUM]; + + unsigned char pwrdiff_20BW1S_OFDM1T_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW2S_20BW2S_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM2T_CCK2T_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW3S_20BW3S_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_4OFDM3T_CCK3T_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW4S_20BW4S_C[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM4T_CCK4T_C[MAX_2G_CHANNEL_NUM]; + + unsigned char pwrdiff_5G_20BW1S_OFDM1T_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW2S_20BW2S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW3S_20BW3S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW4S_20BW4S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_RSVD_OFDM4T_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW1S_160BW1S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW2S_160BW2S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW3S_160BW3S_C[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW4S_160BW4S_C[MAX_5G_CHANNEL_NUM]; + + unsigned char pwrdiff_20BW1S_OFDM1T_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW2S_20BW2S_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM2T_CCK2T_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW3S_20BW3S_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_4OFDM3T_CCK3T_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_40BW4S_20BW4S_D[MAX_2G_CHANNEL_NUM]; + unsigned char pwrdiff_OFDM4T_CCK4T_D[MAX_2G_CHANNEL_NUM]; + + unsigned char pwrdiff_5G_20BW1S_OFDM1T_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW2S_20BW2S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW3S_20BW3S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_40BW4S_20BW4S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_RSVD_OFDM4T_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW1S_160BW1S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW2S_160BW2S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW3S_160BW3S_D[MAX_5G_CHANNEL_NUM]; + unsigned char pwrdiff_5G_80BW4S_160BW4S_D[MAX_5G_CHANNEL_NUM]; + + unsigned int defaultAntennaB; + unsigned int dot11DiversitySupport; + unsigned int shortpreamble; + unsigned int trswitch; + unsigned int disable_ch14_ofdm; + unsigned int disable_scan_ch14; + unsigned int disable_ch1213; + unsigned int xcap; + unsigned int xcap2; + unsigned int share_xcap; + unsigned int tssi1; + unsigned int tssi2; + unsigned int ther; + unsigned int ther2; + unsigned int deltaIQK; + unsigned int deltaLCK; + unsigned int MIMO_TR_mode; + unsigned char phyBandSelect; + unsigned char macPhyMode; + unsigned int smcc; + unsigned int smcc_t; + unsigned int smcc_p; + unsigned char trsw_pape_C9; + unsigned char trsw_pape_CC; + unsigned int tx2path; + unsigned int tx3path; + unsigned int tx4path; + unsigned int txbf; + unsigned int txbfer; + unsigned int txbfee; + unsigned int txbf_mu; + unsigned int target_pwr; + unsigned char bcn2path; + unsigned char bcnagc; + unsigned char add_cck1M_pwr; + unsigned int pa_type; + unsigned char txpwr_reduction; + unsigned char rfe_type; + unsigned int acs_type; + unsigned int acs2_dis_clean_channel; + unsigned int acs2_round; // 200ms per round + unsigned int acs2_clm_weighting_mode; + unsigned int acs2_cca_cap_db; + unsigned char power_percent; + unsigned char kfree_enable; + unsigned int periodicAutochannel; + unsigned int dynamicACS_noise; + unsigned int dynamicACS_idle; +}; + +struct ibss_priv { + unsigned short atim_win; +}; + +#if defined(CONFIG_RTL_WAPI_SUPPORT) +#define SECURITY_INFO_WAPI 0xa5a56789 +#endif +struct bss_desc { + unsigned char bssid[MACADDRLEN]; + unsigned char ssid[32]; + unsigned char *ssidptr; // unused, for backward compatible + unsigned short ssidlen; + unsigned char meshid[MESH_ID_LEN]; + unsigned char *meshidptr; // unused, for backward compatible + unsigned short meshidlen; + unsigned int bsstype; + unsigned short beacon_prd; + unsigned char dtim_prd; + unsigned int t_stamp[2]; + struct ibss_priv ibss_par; + unsigned short capability; + unsigned char channel; + unsigned int basicrate; + unsigned int supportrate; + unsigned char bdsa[MACADDRLEN]; + unsigned char rssi; + unsigned char sq; + unsigned char network; + /*add for P2P_SUPPORT ; for sync; it exist no matter p2p enabled or not*/ + unsigned char p2pdevname[33]; + unsigned char p2prole; + unsigned short p2pwscconfig; + unsigned char p2paddress[MACADDRLEN]; + /* multi-stage 2.3.0 */ + unsigned char stage; + /*cfg p2p cfg p2p*/ + #if defined(WIFI_WPAS) || defined(RTK_NL80211) + #if 0 + unsigned char p2p_ie_len; + unsigned char p2p_ie[256]; + unsigned char wscie_len; + unsigned char wscie[256]; + #endif + struct ht_info_elmt ht_info; + struct ht_cap_elmt ht_cap; + #endif + #if defined(WIFI_WPAS) || defined(RTK_NL80211) || defined(CONFIG_RTL_COMAPI_WLTOOLS) + unsigned char wpa_ie_len; + unsigned char wpa_ie[256]; + unsigned char rsn_ie_len; + unsigned char rsn_ie[256]; + #endif + /*cfg p2p cfg p2p*/ +}; + +struct bss_type +{ + unsigned char net_work_type; +}; + +struct erp_mib { + int protection; // protection mechanism flag + int nonErpStaNum; // none ERP client assoication num + int olbcDetected; // OLBC detected + int olbcExpired; // expired time of OLBC state + int shortSlot; // short slot time flag + int ctsToSelf; // CTStoSelf flag + int longPreambleStaNum; // number of assocated STA using long preamble +}; + +struct wdsEntry { + unsigned char macAddr [MACADDRLEN]; + unsigned int txRate __attribute__ ((packed)); +}; + +struct wds_info { + int wdsEnabled; + int wdsPure; // act as WDS bridge only, no AP function + int wdsPriority; // WDS packets have higer priority + struct wdsEntry entry[NUM_WDS]; + int wdsNum; // number of WDS used + int wdsPrivacy; + unsigned char wdsWepKey[32]; + unsigned char wdsMapingKey[NUM_WDS][32]; + int wdsMappingKeyLen[NUM_WDS]; + int wdsKeyId; + unsigned char wdsPskPassPhrase[65]; +}; + +struct br_ext_info { + unsigned int nat25_disable; + unsigned int macclone_enable; + unsigned int dhcp_bcst_disable; + int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable + unsigned char nat25_dmzMac[MACADDRLEN]; + unsigned int nat25sc_disable; + unsigned int macclone_method; // WiFi STA clone method + unsigned int macclone_eth_method; // Eth STA clone method +}; + +struct Dot11DFSEntry { + unsigned int disable_DFS; // 1 or 0 + unsigned int disable_tx; // 1 or 0 + unsigned int DFS_timeout; // set to 10 ms + unsigned int DFS_detected; // 1 or 0 + unsigned int NOP_timeout; // set to 30 mins + unsigned int DFS_TXPAUSE_timeout; + unsigned int CAC_enable; // 1 or 0 + unsigned int CAC_ss_counter; + unsigned int reserved1; + unsigned int reserved2; + unsigned int reserved3; + unsigned int reserved4; +}; + +struct Dot11hTPCEntry { + unsigned char tpc_enable; // 1 or 0 + unsigned char tpc_tx_power; + unsigned char tpc_link_margin; + unsigned char min_tx_power; + unsigned char max_tx_power; +}; + + +struct MiscEntry { + unsigned int show_hidden_bss; + unsigned int ack_timeout; + unsigned int reserved1; + unsigned int reserved2; + unsigned char private_ie[32]; + unsigned int private_ie_len; + unsigned int set_vlanid; + unsigned int rxInt_thrd; + unsigned int drvmac_lb; + unsigned char lb_da[6]; + unsigned int lb_tps; + unsigned int lb_mlmp; + unsigned int groupID; + unsigned int vap_enable; + unsigned int rsv_txdesc; // 1: enable "reserve tx desc for each interface" function; 0: disable. + unsigned int use_txq; + unsigned int func_off; + unsigned int auto_rts_mode; + //TCP_ACK_ACC + unsigned int tcpack_acc; + unsigned int tcpack_to; + unsigned int tcpack_to_2g; + unsigned int tcpack_use_hw_timer; + unsigned int tcpack_delay_start; + unsigned int tcpack_cnt_th1; + unsigned int tcpack_cnt_th2; + unsigned int tcpack_rx_th1; + unsigned int tcpack_rx_th2; + unsigned int tcpack_rx_th3; + + unsigned int raku_only; + unsigned int tv_mode; // 0: disable, 1: enable, 2: auto + unsigned int stage; + unsigned int forward_streaming; // 0: disable, 1: enable + unsigned int passive_ss_int; + unsigned int ss_delay; + unsigned int ss_loop_delay; + unsigned int chan_switch_time; + unsigned int chan_switch_disable; + unsigned int pkt_filter_len; + unsigned int autoch_ss_to;//AUTOCH_SS_SPEEDUP + unsigned int autoch_ss_cnt;//AUTOCH_SS_SPEEDUP + unsigned int autoch_1611_enable;//AUTOCH_SS_SPEEDUP + unsigned int max_xmitbuf_agg; + unsigned int max_recvbuf_agg; + unsigned int max_handle_xmitbuf; + unsigned int max_handle_recvbuf; + unsigned int drop_rxpkt_en; + unsigned int drop_rxpkt_len; + unsigned int drop_rxpkt_rate; + unsigned int G5_drop_rxpkt_rate; + unsigned int G5G24_drop_rxpkt_rate; + unsigned int client_host_sniffer_enable; + unsigned int manual_priority; + unsigned int clm; + unsigned int nhm; +}; + +struct ParaRecord { + unsigned int ACM; + unsigned int AIFSN; + unsigned int ECWmin; + unsigned int ECWmax; + unsigned int TXOPlimit; +}; + +struct Dot11QosEntry { + unsigned int dot11QosEnable; // 0=disable, 1=enable + unsigned int dot11QosAPSD; // 0=disable, 1=enable + unsigned int EDCAparaUpdateCount; // default=0, increases if any STA_AC_XX_paraRecord updated + unsigned int EDCA_STA_config; // WMM STA, default=0, will be set when assoc AP's EDCA para have been set + unsigned char WMM_IE[7]; // WMM STA, WMM IE + unsigned char WMM_PARA_IE[24]; // WMM EDCA Parameter IE + unsigned int UAPSD_AC_BE; + unsigned int UAPSD_AC_BK; + unsigned int UAPSD_AC_VI; + unsigned int UAPSD_AC_VO; + + struct ParaRecord STA_AC_BE_paraRecord; + struct ParaRecord STA_AC_BK_paraRecord; + struct ParaRecord STA_AC_VI_paraRecord; + struct ParaRecord STA_AC_VO_paraRecord; +//#ifdef RTL_MANUAL_EDCA + unsigned int ManualEDCA; // 0=disable, 1=enable + struct ParaRecord AP_manualEDCA[4]; + struct ParaRecord STA_manualEDCA[4]; + unsigned char TID_mapping[8]; // 1: BK, 2: BE, 3: VI, 4: VO +}; + +struct WifiSimpleConfigEntry { + unsigned int wsc_enable; + unsigned char beacon_ie[256]; + int beacon_ielen; + unsigned char probe_rsp_ie[256]; + int probe_rsp_ielen; + unsigned char probe_req_ie[256]; + int probe_req_ielen; + unsigned char assoc_ie[256]; + int assoc_ielen; + unsigned int both_band_multicredential; +}; + +struct GroupBandWidthControl { + unsigned int GBWCMode; // 0: disable 1: inner limitation 2: outer limitation 3: tx interface 4: rx interface 5: tx+rx interface + unsigned char GBWCAddr[NUM_GBWC][MACADDRLEN]; + unsigned int GBWCNum; // GBWC entry number, this field should be followed to GBWCAddr + unsigned int GBWCThrd_tx; // Tx Threshold, in unit of kbps + unsigned int GBWCThrd_rx; // Rx Threshold, in unit of kbps +}; + +struct SBWC_ENTRY { + unsigned char mac[MACADDRLEN]; + unsigned int tx_lmt; + unsigned int rx_lmt; +}; + +struct StaBandwidthControl { + unsigned int count; + struct SBWC_ENTRY entry[NUM_SBWC]; +}; + +struct Dot11nConfigEntry { + unsigned int dot11nSupportedMCS; + unsigned int dot11nBasicMCS; + unsigned int dot11nUse40M; // 0: 20M, 1: 40M + unsigned int dot11n2ndChOffset; // 0: don't care, 1: below the primary, 2: above the primary + unsigned int dot11nShortGIfor20M; + unsigned int dot11nShortGIfor40M; + unsigned int dot11nShortGIfor80M; + unsigned int dot11nSTBC; + unsigned int dot11nLDPC; + unsigned int dot11nAMPDU; + unsigned int dot11nAMSDU; + unsigned int dot11nAMPDUSendSz; // 8: 8K, 16: 16K, 32: 32K, 64: 64K, other: auto + unsigned int dot11nAMPDURevSz; + unsigned int dot11nAMSDURecvMax; // 0: 4K, 1: 8K + unsigned int dot11nAMSDUSendTimeout; // timeout value to queue AMSDU packets + unsigned int dot11nAMSDUSendNum; // max aggregation packet number + unsigned int dot11curAMSDUSendNum; // current AMSDU packet number + unsigned int dot11nLgyEncRstrct; // bit0: Wep, bit1: TKIP, bit2: restrict Realtek client, bit3: forbid N mode for legacy enc + unsigned int dot11nCoexist; + unsigned int dot11nCoexist_ch_chk; // coexist channel chaek + unsigned int dot11nCoexist_obss_scan;// 0: disable, 1: active scan, 2: passive scan + unsigned int dot11nBGAPRssiChkTh; + unsigned int dot11nTxNoAck; + unsigned int dot11nAddBAreject; //add for support sigma test + unsigned int dot11nDisable2RCCA; +}; + +struct Dot11acConfigEntry { + unsigned int dot11SupportedVHT; // b[1:0]: NSS1, b[3:2]: NSS2 + unsigned int dot11VHT_TxMap; // b[19:10]: NSS2 MCS9~0, b[9:0]: NSS1 MCS9~0 +}; + +struct ReorderControlEntry { + unsigned int ReorderCtrlEnable; + unsigned int reserved; + unsigned int ReorderCtrlWinSz; + unsigned int ReorderCtrlTimeout; + unsigned int ReorderCtrlTimeoutCli; +}; + +struct Dot1180211sInfo{ + unsigned char meshSilence; // active when pure Mesh Mode but not enabled + unsigned char mesh_enable; + unsigned char mesh_root_enable; + unsigned char mesh_ap_enable; + unsigned char mesh_portal_enable; + unsigned char mesh_id[32]; + unsigned short mesh_max_neightbor; + unsigned char log_enabled; // content from webpage setting MIB_LOG_ENABLED (bitmap) + unsigned char dot11PassPhrase[65]; // passphrase + + unsigned int mesh_acl_mode; + unsigned char mesh_acl_addr[NUM_ACL][MACADDRLEN]; + unsigned int mesh_acl_num; + + unsigned short mesh_reserved1; + unsigned short mesh_reserved2; + unsigned short mesh_reserved3; + unsigned short mesh_reserved4; + unsigned short mesh_reserved5; + unsigned short mesh_reserved6; + unsigned short mesh_reserved7; + unsigned short mesh_reserved8; + unsigned short mesh_reserved9; + unsigned short mesh_reserveda; + unsigned short mesh_reservedb; + unsigned short mesh_reservedc; + unsigned short mesh_reservedd; + unsigned short mesh_reservede; + unsigned short mesh_reservedf; + unsigned char mesh_reservedstr1[16]; +}; + +struct EfuseEntry { + unsigned int enable_efuse; +}; + +struct VlanConfig { + int global_vlan; // 0/1 - global vlan disable/enable + int is_lan; // 1: LAN port, 0: WAN port (per-port) + int vlan_enable; // 0/1: disable/enable vlan (per-port) + int vlan_tag; // 0/1: disable/enable tagging (per-port) + int vlan_id; // 1~4090: vlan id (per-port) + int vlan_pri; // 0~7: priority; (per-port) + int vlan_cfi; // 0/1: cfi (per-port) + int forwarding_rule; // 0: disable 1:L2 bridged 2:NAT +}; + +/* type define must accordint to the wapi standard */ +typedef enum __wapiMibType { + wapiDisable = 0, + wapiTypeCert = 1, + wapiTypePSK = 2 +} wapiMibType; + +#define WAPI_PSK_LEN 32 +typedef struct __wapiMibPSK { + unsigned char octet[WAPI_PSK_LEN]; + unsigned int len; +} wapiMibPSK; + +typedef enum __wapiMibTimeoutType { + wapiTimeoutStart = 0, + wapiTimeoutTotalNum = 1 +} wapiMibTimeoutType; + +typedef unsigned int wapiMibTimeout; + +/* Currently only one encrypt algorithm was supported, +* we need NOT to record it +*/ +typedef enum __wapiMibEncryptAlgorithm { + wapi_SMS4 = 1 +} wapiMibEncryptAlgorithm; + +typedef enum __wapiMibKeyUpdateType { + wapi_disable_update = 1, + wapi_time_update = 2, + wapi_pktnum_update = 3, + wapi_all_update = 4 +} wapiMibKeyUpdateType; + +typedef struct __wapiMibInfo { + wapiMibType wapiType; + wapiMibEncryptAlgorithm wapiUCastEncodeType; + wapiMibEncryptAlgorithm wapiMCastEncodeType; + wapiMibPSK wapiPsk; + wapiMibKeyUpdateType wapiUpdateUCastKeyType; + unsigned long wapiUpdateUCastKeyTimeout; + unsigned long wapiUpdateUCastKeyPktNum; + wapiMibKeyUpdateType wapiUpdateMCastKeyType; + unsigned long wapiUpdateMCastKeyTimeout; + unsigned long wapiUpdateMCastKeyPktNum; + wapiMibTimeout wapiTimeout[wapiTimeoutTotalNum]; +} wapiMibInfo; + +/*for HS2_SUPPORT*/ +#define MAX_DSCP_EXCEPT 4 +#define MAX_QOS_PRIORITY 8 +struct HotSpotConfigEntry { + unsigned int hs_enable; + unsigned char hs2_ie[256]; + int hs2_ielen; + unsigned char interworking_ie[256]; + int interworking_ielen; + unsigned char QoSMap_ie[2][256]; + unsigned char QoSMap_ielen[2]; + unsigned char QoSMAP_range[MAX_QOS_PRIORITY][2]; + unsigned char QoSMAP_except[MAX_DSCP_EXCEPT][2]; + unsigned char nQoSMap; + unsigned char curQoSMap; + unsigned char advt_proto_ie[256]; + int advt_proto_ielen; + unsigned char roam_ie[256]; + int roam_ielen; + unsigned char timeadvt_ie[20]; + int timeadvt_ielen; + unsigned char timezone_ie[10]; + int timezone_ielen; + unsigned char MBSSID_ie[256]; + int MBSSID_ielen; + unsigned char remedSvrURL[256]; + + unsigned char serverMethod; + + unsigned char SessionInfoURL[256]; + unsigned char bssload_ie[5]; + // unsigned int channel_utili_beaconIntval; + unsigned int timeadvt_DTIMIntval; + unsigned int reqmode; + unsigned int disassoc_timer; + unsigned int validity_intval; + unsigned char session_url[50]; + unsigned char sta_mac[MACADDRLEN]; + unsigned char redir_mac[MACADDRLEN]; + unsigned char remed_mac[MACADDRLEN]; + unsigned int roam_enable; + unsigned int mmpdu_limit; + unsigned int bssload; + unsigned int radioOff; + unsigned int ICMPv4ECHO; +}; + +/*for P2P_SUPPORT*/ +struct P2P_Direct { +/*cfg p2p cfg p2p*/ + unsigned char p2p_enabled; + unsigned char p2p_type; + unsigned char p2p_state; + unsigned char p2p_on_discovery; + unsigned char p2p_intent; + unsigned char p2p_listen_channel; + unsigned char p2p_op_channel; +/*cfg p2p cfg p2p*/ + unsigned char p2p_event_indiate; + + unsigned char p2p_device_name[33]; + unsigned char p2p_wsc_pin_code[9]; + unsigned short p2p_wsc_config_method; + +}; + + +#define PROFILE_NUM 5 // must reserve one for root profile. + +struct ap_profile { + char ssid[33]; // desired SSID in string + int encryption; // 0: open, 1:wep40, 2:wep128, 3:wpa, 4:wpa2 + int auth_type; // authentication type. 0: open, 1: shared, 2: auto + int wpa_cipher; // bit0-wep64, bit1-tkip, bit2-wrap,bit3-ccmp, bit4-wep128 + unsigned char wpa_psk[65]; // wpa psk + int wep_default_key; // wep default tx key index, 0~3 + unsigned char wep_key1[13]; // WEP key1 in hex + unsigned char wep_key2[13]; // WEP key2 in hex + unsigned char wep_key3[13]; // WEP key3 in hex + unsigned char wep_key4[13]; // WEP key4 in hex + int MulticastCipher; + unsigned char bss_PMF; +}; + +struct ap_conn_profile { // ap connection profile + int enable_profile; + int profile_num; // profile number, except root profile. + int sortbyprofile; + struct ap_profile profile[PROFILE_NUM]; +}; + +struct StaControl { + unsigned char stactrl_enable; //0:disable, 1:enable + unsigned char stactrl_groupID; + unsigned char stactrl_prefer_band; //0: disable, 1: enable + unsigned int stactrl_param_1; // rssi threshold + unsigned int stactrl_param_2; // rssi threshold tolerance + unsigned int stactrl_param_3; // timer X + unsigned int stactrl_param_4; // retry Y + unsigned int stactrl_param_5; // timer Z + unsigned int stactrl_param_6; // rssi threshold for non-prefer band + unsigned int stactrl_param_7; // kickoff times //20170103 + unsigned int stactrl_param_8; // kickoff times //20170106 + unsigned int stactrl_param_9; + unsigned char stactrl_param_10; + unsigned char stactrl_functions; // BIT(0)-block5G feature, BIT(1)-hiddenAP feature +}; + +struct SmartRoamingProfile { + unsigned char block_aging; + unsigned int tp_max; + unsigned char signal_max; + unsigned char signal_min; + unsigned char load_min; + unsigned char speed_weight; + unsigned char signal_weight; + unsigned char load_weight; + unsigned char enable; +}; + +struct MeshPathsel{ + unsigned char mesh_crossbandEnable; + unsigned char mesh_rssiThreshold; + unsigned char mesh_cuThreshold; + unsigned char mesh_noiseThreshold; + unsigned char mesh_rssiWeight; + unsigned char mesh_cuWeight; + unsigned char mesh_noiseWeight; +}; + +struct CrossBand{ + unsigned char crossband_enable; //0:disable, 1:enable + unsigned char crossband_prefer; //1: preferred interface 0: not preferred interface + unsigned char crossband_assoc; //1: Yes, 0: no, interface is associated to remote AP + unsigned char crossband_pathReady; //1: Yes, 0: No, both interfaces are connected + unsigned char crossband_cuThreshold; //channel utilization threshold + unsigned char crossband_noiseThreshold; //noise threshold + unsigned char crossband_rssiThreshold; //rssi threshold + unsigned char crossband_cuWeight; //channel utilization weight + unsigned char crossband_noiseWeight; //noise weight + unsigned char crossband_rssiWeight; //rssi weight +}; + +struct Dot11FastBSSTransitionEntry { + int dot11FastBSSTransitionEnabled; + unsigned char dot11FTMobilityDomainID[2]; + int dot11FTOverDSEnabled; + int dot11FTResourceRequestSupported; + unsigned char dot11FTR0KeyHolderID[49]; + unsigned int dot11FTR0KeyHolderIDLen; + int dot11FTReassociationDeadline; + int dot11FTR0KeyLifetime; + int dot11FTR1KeyPushEnable; + int dot11FT4way; +}; + +//RTK_ATM +/* Airtime Management Config Entry*/ +struct atm_stainfo { + unsigned char hwaddr[MACADDRLEN]; + unsigned char ipaddr[4]; + int atm_time; +}; + +struct ATMConfigEntry { + int atm_en; //enable/disable + int atm_mode; //0:auto 1:interface 2:client + int atm_iftime[1+4+1]; //Root+4*VAP+VXD, interface mode + struct atm_stainfo atm_sta[64]; //64 client list, clietn dmoe +}; + +struct Dot11WNMEntry { + unsigned char dot11vBssTransEnable; + unsigned char dot11vReqMode; + unsigned char dot11vDiassocImminent; + unsigned char sta_mac[MACADDRLEN]; + unsigned short dot11vDiassocDeadline; + unsigned char bssTransExpiredTime; + unsigned char Is11kDaemonOn; + unsigned char algoType; + unsigned char defaultPrefVal; +}; + +struct HalQcDebug { + unsigned int HalDbgCom; + unsigned int HalDbgLev; +}; + +struct Dot11RFDPKEntry { + /* DPK 2G parameters */ + unsigned char bDPPathAOK; + unsigned char bDPPathBOK; + unsigned char pwsf_2g_a[3]; + unsigned char pwsf_2g_b[3]; + unsigned int lut_2g_even_a[3][64]; + unsigned int lut_2g_odd_a[3][64]; + unsigned int lut_2g_even_b[3][64]; + unsigned int lut_2g_odd_b[3][64]; + + /* DPK 5G parameters */ + unsigned char is_5g_pdk_patha_ok; + unsigned char is_5g_pdk_pathb_ok; + unsigned int pwsf_5g_a[9]; + unsigned int pwsf_5g_b[9]; + unsigned int lut_5g_even_a[9][16]; + unsigned int lut_5g_odd_a[9][16]; + unsigned int lut_5g_even_b[9][16]; + unsigned int lut_5g_odd_b[9][16]; +}; + + +// driver mib +struct wifi_mib { + unsigned int mib_version; + struct Dot11StationConfigEntry dot11StationConfigEntry; + struct Dot1180211AuthEntry dot1180211AuthEntry; + struct Dot118021xAuthEntry dot118021xAuthEntry; + struct Dot11DefaultKeysTable dot11DefaultKeysTable; + struct Dot11KeyMappingsEntry dot11GroupKeysTable; + struct Dot11KeyMappingsEntry dot11IGTKTable; //CONFIG_IEEE80211W + struct Dot11RsnIE dot11RsnIE; + struct Dot11OperationEntry dot11OperationEntry; + struct Dot11RFEntry dot11RFEntry; + struct bss_desc dot11Bss; + struct bss_type dot11BssType; + struct erp_mib dot11ErpInfo; + struct wds_info dot11WdsInfo; + struct br_ext_info ethBrExtInfo; + struct Dot11DFSEntry dot11DFSEntry; + struct Dot11hTPCEntry dot11hTPCEntry; + struct MiscEntry miscEntry; + struct Dot11QosEntry dot11QosEntry; + struct WifiSimpleConfigEntry wscEntry; + struct GroupBandWidthControl gbwcEntry; + struct StaBandwidthControl sbwcEntry; + struct Dot11nConfigEntry dot11nConfigEntry; + struct Dot11acConfigEntry dot11acConfigEntry; + struct ReorderControlEntry reorderCtrlEntry; + struct VlanConfig vlan; + struct Dot1180211sInfo dot1180211sInfo; + struct Dot11KeyMappingsEntry dot11sKeysTable; + struct __wapiMibInfo wapiInfo; + struct Dot1180211CountryCodeEntry dot11dCountry; + struct EfuseEntry efuseEntry; + struct StaDetectInfo staDetectInfo; + struct P2P_Direct p2p_mib; // add for P2P_SUPPORT + struct ap_conn_profile ap_profile; + struct HotSpotConfigEntry hs2Entry; // add for HS2_SUPPORT, Hotspot 2.0 Release 1 + struct Dot11FastBSSTransitionEntry dot11FTEntry; + struct StaControl staControl; // add for sta control + struct SmartRoamingProfile sr_profile; //add for smart roaming + struct MeshPathsel meshPathsel; + struct CrossBand crossBand; //add for crossband - keith + struct Dot11WNMEntry wnmEntry; + struct HalQcDebug qc_debug; // add for qc debug + struct Dot11RFDPKEntry dot11RFDPKEntry; +}; + +#endif // _IEEE802_MIB_H_ + diff --git a/package/kernel/rtl8192cd/mesh_ext/mesh_route.h b/package/kernel/rtl8192cd/mesh_ext/mesh_route.h index fcebb141976..4819fb965b8 100644 --- a/package/kernel/rtl8192cd/mesh_ext/mesh_route.h +++ b/package/kernel/rtl8192cd/mesh_ext/mesh_route.h @@ -1,172 +1,172 @@ -#ifndef PATHSELECTION_H -#define PATHSELECTION_H - -#include "./mesh.h" - -#ifndef CONFIG_RTK_MESH //if"N"def For 8190n.h wlan_device[] -#define MESH_SHIFT 0 -#define MESH_NUM_CFG 0 -#else -#define MESH_SHIFT 8 // ACCESS_MASK uses 2 bits, WDS_MASK use 4 bits -#define MESH_MASK 0x3 -#define MESH_NUM_CFG NUM_MESH - -#define HWMP_MAX_PREQ_RETRIES 2 - -#define PROXY_TBL_AGING_LIMIT 300 //proxy table expire time -#define HWMP_ACTIVE_PATH_TIMEOUT 300 //pathsel table expire time, chuangch -#define HWMP_PREQ_REFRESH_PERIOD 60 //route maintenance, chuangch 10.19 -#define HWMP_PREQ_REFRESH_PERIOD2 200 //route maintenance, chuangch 10.19 - - -#if defined(RTK_MESH_AODV_STANDALONE_TIMER) -#define HWMP_NETDIAMETER_TRAVERSAL_TIME MESH_AODV_EXPIRE_TO*3 //miliseconds -#else -#define HWMP_NETDIAMETER_TRAVERSAL_TIME HZ -#endif - -#ifdef PU_STANDARD // For 802.11 Mesh proxy update -enum PU_flag -{ - PU_add, - PU_delete -}; -#endif - -__PACK struct mesh_rreq_retry_entry { - unsigned char MACAddr[MACADDRLEN]; - long int TimeStamp; - long int createTime; - unsigned char Retries; // add by chuangch, the num of rreq retries - struct pkt_queue pktqueue; - struct mesh_rreq_retry_entry *rreq_next; - struct mesh_rreq_retry_entry *rreq_prev; -}__WLAN_ATTRIB_PACK__; - - -__PACK struct lls_mesh_header { - unsigned char mesh_flag; - INT8 TTL; - UINT16 segNum; - unsigned char DestMACAddr[MACADDRLEN]; // modify for 6 address - unsigned char SrcMACAddr[MACADDRLEN]; -} __WLAN_ATTRIB_PACK__; - - -__PACK struct proxy_table_entry { - unsigned char sta[MACADDRLEN]; - unsigned char owner[MACADDRLEN]; - // unsigned char type; // 0: others, 1: my_sta, 2: my bridge - short aging_time; -}; - - -__PACK struct proxyupdate_table_entry { - UINT8 PUflag, isMultihop, PUSN, retry; - unsigned short STAcount; - unsigned char nexthopmac[MACADDRLEN]; - unsigned char destproxymac[MACADDRLEN]; - unsigned char proxymac[MACADDRLEN]; - unsigned char proxiedmac[MACADDRLEN]; - DRV_PRIV *priv; - unsigned long update_time; -}; - -#ifdef SUPPORT_TX_MCAST2UNI -__PACK struct mesh_ip_mcast_info { - int used; - unsigned char mcmac[MACADDRLEN]; - - /*src record*/ - unsigned char srcCount; - unsigned char srcValid[MAX_IP_SRC_ENTRY]; - unsigned char srcMac[MAX_IP_SRC_ENTRY][MACADDRLEN]; -}; -#endif - -__PACK struct path_sel_entry { - unsigned char destMAC[MACADDRLEN]; - unsigned char nexthopMAC[MACADDRLEN]; - unsigned int dsn; - unsigned int metric; - unsigned char hopcount; - // the following entries are NOT shared by daemon and driver - // unsigned char isvalid; - // unsigned char modify_time[8]; - unsigned int start, end; - unsigned short RecentSeq[SZ_HASH_IDX2]; - DRV_PRIV *priv; - unsigned long update_time; - unsigned long routeMaintain; - #ifdef SUPPORT_TX_MCAST2UNI - int ipmc_num; - struct mesh_ip_mcast_info ipmc[MAX_IP_MC_ENTRY]; - #endif -} __WLAN_ATTRIB_PACK__; - - -struct pann_mpp_tb_entry { - unsigned char mac[MACADDRLEN]; - unsigned int timeout; - unsigned int seqNum; - short int flag; - int beRoot; -}; - - -struct mpp_tb { - struct pann_mpp_tb_entry pann_mpp_pool[MAX_MPP_NUM]; - unsigned int pool_count ; -}; - - - -// _DOT11s_XXX serires struct size need less than MAXDATALEN(1560) , which defined in iwreq.c -typedef __PACK struct _DOT11s_GEN_RREQ_PACKET{ - unsigned char EventId; - unsigned char IsMoreEvent; - unsigned char MyMACAddr[MACADDRLEN]; - unsigned char destMACAddr[MACADDRLEN]; - unsigned char TTL; - unsigned short Seq_num; -}__WLAN_ATTRIB_PACK__ DOT11s_GEN_RREQ_PACKET; - -typedef __PACK struct _DOT11s_GEN_RERR_PACKET{ - unsigned char EventId; - unsigned char IsMoreEvent; - unsigned char MyMACAddr[MACADDRLEN]; - unsigned char SorNMACAddr[MACADDRLEN]; //this address is the neighbor that hello message finds it is unreachabel. - // if flag == 1, this field means disconnected neighbor MAC addr - // if flag == 2, this field means source MAC addr of the data frame - unsigned char DataDestMAC[MACADDRLEN]; // this field is valid if and only if flag == 2 - unsigned char PrehopMAC[MACADDRLEN]; // this field is valid if and only if flag == 2 - unsigned char TTL; - unsigned short Seq_num; - unsigned char Flag; // flag = 1 means the link to neighbor has broken - // flag = 2 means this MP doesn't have the nexthop information for the destination in pathseleciton table -}__WLAN_ATTRIB_PACK__ DOT11s_GEN_RERR_PACKET; - -typedef __PACK struct _DOT11s_RECV_PACKET{ - unsigned char EventId; - unsigned char IsMoreEvent; - unsigned char MyMACAddr[MACADDRLEN]; - unsigned char PreHopMACAddr[MACADDRLEN]; - unsigned char DesMACAddr[MACADDRLEN]; - unsigned int Pre_Hop_Metric; - unsigned char ReceiveData[128]; - unsigned char TTL; - unsigned short Seq_num; - unsigned char Is6AddrFormat; - unsigned char MACAddr5[MACADDRLEN]; - unsigned char MACAddr6[MACADDRLEN]; -#ifdef RTK_MESH_METRIC_REFINE - unsigned char InterfaceMACAddr[MACADDRLEN]; - unsigned int RSSI_Metric; - unsigned int Cu_Metric; - unsigned int Noise_Metric; -#endif -}__WLAN_ATTRIB_PACK__ DOT11s_RECV_PACKET; - -#endif // end of not define CONFIG_RTK_MESH - -#endif//PATHSELECTION_H +#ifndef PATHSELECTION_H +#define PATHSELECTION_H + +#include "./mesh.h" + +#ifndef CONFIG_RTK_MESH //if"N"def For 8190n.h wlan_device[] +#define MESH_SHIFT 0 +#define MESH_NUM_CFG 0 +#else +#define MESH_SHIFT 8 // ACCESS_MASK uses 2 bits, WDS_MASK use 4 bits +#define MESH_MASK 0x3 +#define MESH_NUM_CFG NUM_MESH + +#define HWMP_MAX_PREQ_RETRIES 2 + +#define PROXY_TBL_AGING_LIMIT 300 //proxy table expire time +#define HWMP_ACTIVE_PATH_TIMEOUT 300 //pathsel table expire time, chuangch +#define HWMP_PREQ_REFRESH_PERIOD 60 //route maintenance, chuangch 10.19 +#define HWMP_PREQ_REFRESH_PERIOD2 200 //route maintenance, chuangch 10.19 + + +#if defined(RTK_MESH_AODV_STANDALONE_TIMER) +#define HWMP_NETDIAMETER_TRAVERSAL_TIME MESH_AODV_EXPIRE_TO*3 //miliseconds +#else +#define HWMP_NETDIAMETER_TRAVERSAL_TIME HZ +#endif + +#ifdef PU_STANDARD // For 802.11 Mesh proxy update +enum PU_flag +{ + PU_add, + PU_delete +}; +#endif + +__PACK struct mesh_rreq_retry_entry { + unsigned char MACAddr[MACADDRLEN]; + long int TimeStamp; + long int createTime; + unsigned char Retries; // add by chuangch, the num of rreq retries + struct pkt_queue pktqueue; + struct mesh_rreq_retry_entry *rreq_next; + struct mesh_rreq_retry_entry *rreq_prev; +}__WLAN_ATTRIB_PACK__; + + +__PACK struct lls_mesh_header { + unsigned char mesh_flag; + INT8 TTL; + UINT16 segNum; + unsigned char DestMACAddr[MACADDRLEN]; // modify for 6 address + unsigned char SrcMACAddr[MACADDRLEN]; +} __WLAN_ATTRIB_PACK__; + + +__PACK struct proxy_table_entry { + unsigned char sta[MACADDRLEN]; + unsigned char owner[MACADDRLEN]; + // unsigned char type; // 0: others, 1: my_sta, 2: my bridge + short aging_time; +}; + + +__PACK struct proxyupdate_table_entry { + UINT8 PUflag, isMultihop, PUSN, retry; + unsigned short STAcount; + unsigned char nexthopmac[MACADDRLEN]; + unsigned char destproxymac[MACADDRLEN]; + unsigned char proxymac[MACADDRLEN]; + unsigned char proxiedmac[MACADDRLEN]; + DRV_PRIV *priv; + unsigned long update_time; +}; + +#ifdef SUPPORT_TX_MCAST2UNI +__PACK struct mesh_ip_mcast_info { + int used; + unsigned char mcmac[MACADDRLEN]; + + /*src record*/ + unsigned char srcCount; + unsigned char srcValid[MAX_IP_SRC_ENTRY]; + unsigned char srcMac[MAX_IP_SRC_ENTRY][MACADDRLEN]; +}; +#endif + +__PACK struct path_sel_entry { + unsigned char destMAC[MACADDRLEN]; + unsigned char nexthopMAC[MACADDRLEN]; + unsigned int dsn; + unsigned int metric; + unsigned char hopcount; + // the following entries are NOT shared by daemon and driver + // unsigned char isvalid; + // unsigned char modify_time[8]; + unsigned int start, end; + unsigned short RecentSeq[SZ_HASH_IDX2]; + DRV_PRIV *priv; + unsigned long update_time; + unsigned long routeMaintain; + #ifdef SUPPORT_TX_MCAST2UNI + int ipmc_num; + struct mesh_ip_mcast_info ipmc[MAX_IP_MC_ENTRY]; + #endif +} __WLAN_ATTRIB_PACK__; + + +struct pann_mpp_tb_entry { + unsigned char mac[MACADDRLEN]; + unsigned int timeout; + unsigned int seqNum; + short int flag; + int beRoot; +}; + + +struct mpp_tb { + struct pann_mpp_tb_entry pann_mpp_pool[MAX_MPP_NUM]; + unsigned int pool_count ; +}; + + + +// _DOT11s_XXX serires struct size need less than MAXDATALEN(1560) , which defined in iwreq.c +typedef __PACK struct _DOT11s_GEN_RREQ_PACKET{ + unsigned char EventId; + unsigned char IsMoreEvent; + unsigned char MyMACAddr[MACADDRLEN]; + unsigned char destMACAddr[MACADDRLEN]; + unsigned char TTL; + unsigned short Seq_num; +}__WLAN_ATTRIB_PACK__ DOT11s_GEN_RREQ_PACKET; + +typedef __PACK struct _DOT11s_GEN_RERR_PACKET{ + unsigned char EventId; + unsigned char IsMoreEvent; + unsigned char MyMACAddr[MACADDRLEN]; + unsigned char SorNMACAddr[MACADDRLEN]; //this address is the neighbor that hello message finds it is unreachabel. + // if flag == 1, this field means disconnected neighbor MAC addr + // if flag == 2, this field means source MAC addr of the data frame + unsigned char DataDestMAC[MACADDRLEN]; // this field is valid if and only if flag == 2 + unsigned char PrehopMAC[MACADDRLEN]; // this field is valid if and only if flag == 2 + unsigned char TTL; + unsigned short Seq_num; + unsigned char Flag; // flag = 1 means the link to neighbor has broken + // flag = 2 means this MP doesn't have the nexthop information for the destination in pathseleciton table +}__WLAN_ATTRIB_PACK__ DOT11s_GEN_RERR_PACKET; + +typedef __PACK struct _DOT11s_RECV_PACKET{ + unsigned char EventId; + unsigned char IsMoreEvent; + unsigned char MyMACAddr[MACADDRLEN]; + unsigned char PreHopMACAddr[MACADDRLEN]; + unsigned char DesMACAddr[MACADDRLEN]; + unsigned int Pre_Hop_Metric; + unsigned char ReceiveData[128]; + unsigned char TTL; + unsigned short Seq_num; + unsigned char Is6AddrFormat; + unsigned char MACAddr5[MACADDRLEN]; + unsigned char MACAddr6[MACADDRLEN]; +#ifdef RTK_MESH_METRIC_REFINE + unsigned char InterfaceMACAddr[MACADDRLEN]; + unsigned int RSSI_Metric; + unsigned int Cu_Metric; + unsigned int Noise_Metric; +#endif +}__WLAN_ATTRIB_PACK__ DOT11s_RECV_PACKET; + +#endif // end of not define CONFIG_RTK_MESH + +#endif//PATHSELECTION_H diff --git a/package/kernel/rtl8192cd/mesh_ext/mesh_security.h b/package/kernel/rtl8192cd/mesh_ext/mesh_security.h index b75bd936582..94766559416 100644 --- a/package/kernel/rtl8192cd/mesh_ext/mesh_security.h +++ b/package/kernel/rtl8192cd/mesh_ext/mesh_security.h @@ -1,28 +1,28 @@ -#ifndef _MESH_SECURITY_H_ -#define _MESH_SECURITY_H_ - -#include "./mesh.h" - - -// enough for DOT11s_RECV_PACKET -#define MAXDATALEN2 256 -// 6 entries should be enough -#define MAXQUEUESIZE2 6 - -typedef struct _DOT11_QUEUE_NODE2 -{ - unsigned short ItemSize; - unsigned char Item[MAXDATALEN2]; -}DOT11_QUEUE_NODE2; - -typedef struct _DOT11_QUEUE2 -{ - int Head; - int Tail; - int NumItem; - int MaxItem; - DOT11_QUEUE_NODE2 ItemArray[MAXQUEUESIZE2]; - int MaxData; -}DOT11_QUEUE2; - -#endif //_MESH_SECURITY_H_ +#ifndef _MESH_SECURITY_H_ +#define _MESH_SECURITY_H_ + +#include "./mesh.h" + + +// enough for DOT11s_RECV_PACKET +#define MAXDATALEN2 256 +// 6 entries should be enough +#define MAXQUEUESIZE2 6 + +typedef struct _DOT11_QUEUE_NODE2 +{ + unsigned short ItemSize; + unsigned char Item[MAXDATALEN2]; +}DOT11_QUEUE_NODE2; + +typedef struct _DOT11_QUEUE2 +{ + int Head; + int Tail; + int NumItem; + int MaxItem; + DOT11_QUEUE_NODE2 ItemArray[MAXQUEUESIZE2]; + int MaxData; +}DOT11_QUEUE2; + +#endif //_MESH_SECURITY_H_ diff --git a/package/kernel/rtl8192cd/mesh_ext/mesh_util.c b/package/kernel/rtl8192cd/mesh_ext/mesh_util.c index b0492cbd4ce..8f6bf0d749f 100644 --- a/package/kernel/rtl8192cd/mesh_ext/mesh_util.c +++ b/package/kernel/rtl8192cd/mesh_ext/mesh_util.c @@ -1,403 +1,403 @@ -/* - * Handling routines for Mesh in 802.11 Utils - * - * PS: All extern function in ../8190n_headers.h - */ -#define _MESH_UTIL_C_ - -#ifdef CONFIG_RTL8192CD -#include "../8192cd.h" -#include "../8192cd_headers.h" -#else -#include "../rtl8190/8190n.h" -#include "../rtl8190/8190n_headers.h" -#endif -#include "./mesh_util.h" -#include - -#ifdef CONFIG_RTK_MESH -int clear_route_info(struct rtl8192cd_priv *priv, unsigned char *delMAC) -{ - struct path_sel_entry *pEntry = 0; - unsigned long flags, i=0; - int tbl_sz; - unsigned char destMAC[MACADDRLEN]; - int is_delete; -#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) - priv = (DRV_PRIV *)priv->mesh_priv_first; -#endif //CONFIG_RTL_MESH_SINGLE_IFACE - tbl_sz = (1 << priv->pathsel_table->table_size_power); - - //clean up path relative to invalid neighbor - for(;ipathsel_table->entry_array[i].dirty) { - pEntry = (struct path_sel_entry *)(priv->pathsel_table->entry_array[i].data); - if(memcmp(delMAC, pEntry->nexthopMAC,MACADDRLEN)==0) { - priv->pathsel_table->entry_array[i].dirty = 0; - memcpy(destMAC, pEntry->destMAC, MACADDRLEN); - is_delete = 1; - } - } - RESTORE_INT(flags); - SMP_UNLOCK_MESH_PATH(flags); - - if(is_delete) { - #if defined(RTL_MESH_TXCACHE) - expire_mesh_txcache(priv, destMAC); - #endif - } - } - - remove_proxy_owner(priv, delMAC); - - return SUCCESS; -} - -void mac12_to_6(unsigned char *mac1, unsigned char *mac2) -{ - short m=0; - for( ; m='a')?(mac1[1|(m<<1)]-('a'-0xa)):(mac1[1|(m<<1)]-'0'))|((((mac1[m<<1])>='a')?(mac1[m<<1]-('a'-0xa)):(mac1[m<<1]-'0'))<<4); -} - -/* - * @brief Count MESH Association number and display - * - * @param priv:priv - * @param pstat: pstat - * @param act: action - * INCREASE = New peer MP (action: minus peer cap) - * DECREASE = Delete exist connect MP (acton: Plus peer cap) - * - * @retval void - */ -void mesh_cnt_ASSOC_PeerLink_CAP(DRV_PRIV *priv, struct stat_info *pstat, int act) -{ - UINT8 modify = TRUE; - struct list_head *phead, *plist; - INT16 mesh_assoc_sum = 0; - -//we need to recalculate to prevent peer running out accidently - phead = &priv->mesh_mp_hdr; - plist = phead->next; - while (plist != phead) { - mesh_assoc_sum++; - plist = plist->next; - } - MESH_PEER_LINK_CAP_NUM(priv) = MAX_MPP_NUM - mesh_assoc_sum; - - if (DECREASE == act) { - if (MESH_PEER_LINK_CAP_NUM(priv) < GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor) - MESH_PEER_LINK_CAP_NUM(priv)++; - else { - modify = FALSE; - MESH_DEBUG_MSG("MESH PeerLink CAP Number Error (%d)!\n", GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor); - } - } else { - if (MESH_PEER_LINK_CAP_NUM(priv) <= 0) { - modify = FALSE; - printk("MESH PeerLink CAP Number Error (0)!\n"); - } - } - - if (TRUE == modify) - update_beacon(priv); // Because MESH_PEER_LINK_CAP_NUM modify (beacon include WLAN Mesh Capacity) - - mesh_sme_debug("Mesh assoc_num: %s(Max:%d, Remain:%d) %02X:%02X:%02X:%02X:%02X:%02X\n", - act?"++":"--", - GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor, - MESH_PEER_LINK_CAP_NUM(priv), - pstat->hwaddr[0], - pstat->hwaddr[1], - pstat->hwaddr[2], - pstat->hwaddr[3], - pstat->hwaddr[4], - pstat->hwaddr[5]); - -} - -/* - * @brief Set MESH Association Max number (call by web interface?) - * Note: If setting value(meshCapSetValue) less system current connection number, MESH_PEER_LINK_CAP_NUM become negative, Denied any new connection. - * Delete exist connect ONLY!! - * SO - * MESH_PEER_LINK_CAP_NUM = 0 : setting = connection, Denied any new connection - * MESH_PEER_LINK_CAP_NUM > 0 (< MAX_MPP_NUM) : setting > connection ,Allow new connect - * MESH_PEER_LINK_CAP_NUM = MAX_MPP_NUM : connection = 0 ,Allow new connect - * - * @param priv:priv - * @param meshCapSetValue: set connect number - * - * @retval void - */ -void mesh_set_PeerLink_CAP(DRV_PRIV *priv, UINT16 meshCapSetValue) -{ - struct list_head *plist; - -#ifndef SMP_SYNC - unsigned long flags; -#endif - - UINT16 count = 0; - - SAVE_INT_AND_CLI(flags); - - meshCapSetValue &= MESH_PEER_LINK_CAP_CAPACITY_MASK; - - if (MAX_MPP_NUM < meshCapSetValue) - meshCapSetValue = MAX_MPP_NUM; // Exceed hard code MAX number, Lock on hardcode MAX number - - GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor = meshCapSetValue; // Writeback runtime Max value (Avoid web interface fault) - - // Recalculate current connection number by association list (Avoid problem when CAP value error) - plist = &(priv->mesh_mp_hdr); - while (plist->next != &(priv->mesh_mp_hdr)) // 1.Check index 2.Check is it least element? (Because next pointer to mesh_mp_hdr itself) - { - count++; - plist = plist->next; // pointer to next element's list_head struct - } - - MESH_PEER_LINK_CAP_NUM(priv) = (INT16)(meshCapSetValue - count); // Setting - current connection number -> CAP (NOTE: Allow POS/NEG value) - RESTORE_INT(flags); - init_beacon(priv); - return; -} - -int remove_proxy_owner(DRV_PRIV *priv, unsigned char *owner) -{ -#ifdef SMP_SYNC - unsigned long flags; -#endif - struct proxy_table_entry *pxEntry = 0; - int i, tbl_sz; -#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) - priv = (DRV_PRIV *)priv->mesh_priv_first; -#endif //CONFIG_RTL_MESH_SINGLE_IFACE - - SMP_LOCK_MESH_PROXY(flags); - //clean up proxy entry relative to invalid neighbor - tbl_sz = (1 << priv->proxy_table->table_size_power); - for(i=0;iproxy_table->entry_array[i].dirty) { - pxEntry = (struct proxy_table_entry *)(priv->proxy_table->entry_array[i].data); - if(memcmp(owner,pxEntry->owner,MACADDRLEN)==0){ - priv->proxy_table->entry_array[i].dirty = 0; - mesh_proxy_debug("[%s %d]Delete Proxy entry of %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - __func__,__LINE__,pxEntry->owner[0],pxEntry->owner[1],pxEntry->owner[2],pxEntry->owner[3],pxEntry->owner[4],pxEntry->owner[5], - pxEntry->sta[0],pxEntry->sta[1],pxEntry->sta[2],pxEntry->sta[3],pxEntry->sta[4],pxEntry->sta[5]); - } - } - } - SMP_UNLOCK_MESH_PROXY(flags); - - - return 0; -} - - -int remove_proxy_entry(DRV_PRIV *priv, unsigned char *owner, unsigned char* sta) -{ -#ifdef SMP_SYNC - unsigned long flags; -#endif - struct proxy_table_entry* pPXEntry; - int process = 0; -#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) - priv = (DRV_PRIV *)priv->mesh_priv_first; -#endif //CONFIG_RTL_MESH_SINGLE_IFACE - SMP_LOCK_MESH_PROXY(flags); - - pPXEntry = HASH_SEARCH(priv->proxy_table, sta); - if( pPXEntry ) { - if( owner == NULL) { - if(memcmp(pPXEntry->owner, GET_MY_HWADDR, MACADDRLEN) == 0) - process = 1; - } - else{ - if(memcmp(pPXEntry->owner, owner, MACADDRLEN) == 0) - process = 1; - } - - if(process) - { - HASH_DELETE(priv->proxy_table,sta); - mesh_proxy_debug("[%s %d]Delete Proxy entry of %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - __func__,__LINE__, pPXEntry->owner[0], pPXEntry->owner[1],pPXEntry->owner[2],pPXEntry->owner[3],pPXEntry->owner[4],pPXEntry->owner[5], - sta[0],sta[1],sta[2],sta[3],sta[4],sta[5]); - #if defined(CONFIG_RTL_MESH_CROSSBAND) - sync_proxy_info(priv->mesh_priv_sc, sta, 2); //delete proxy info of another band - #endif - - #if defined(RTL_MESH_TXCACHE) - priv->mesh_txcache.dirty = 0; - #endif - } - } - - SMP_UNLOCK_MESH_PROXY(flags); - - return 0; -} - - -int mesh_proxy_update(DRV_PRIV *priv, unsigned char* owner, unsigned char* sta) { -#ifdef SMP_SYNC - unsigned long flags; -#endif - struct proxy_table_entry* pProxyEntry = NULL, Entry; -#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) - priv = (DRV_PRIV *)priv->mesh_priv_first; -#endif //CONFIG_RTL_MESH_SINGLE_IFACE - SMP_LOCK_MESH_PROXY(flags); - - pProxyEntry = (struct proxy_table_entry*) HASH_SEARCH(priv->proxy_table, sta); - if(!pProxyEntry) { - struct path_sel_entry *path_entry = NULL; - path_entry = HASH_SEARCH(priv->pathsel_table, sta); - if (path_entry) - return 0; - memcpy(Entry.sta, sta, MACADDRLEN); - memcpy(Entry.owner, owner, MACADDRLEN); - Entry.aging_time = 0; - HASH_INSERT(priv->proxy_table, Entry.sta, &Entry); - - mesh_proxy_debug("[A6 forwardding]Insert Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - Entry.owner[0],Entry.owner[1],Entry.owner[2],Entry.owner[3],Entry.owner[4],Entry.owner[5], - Entry.sta[0],Entry.sta[1],Entry.sta[2],Entry.sta[3],Entry.sta[4],Entry.sta[5]); - - #if defined(CONFIG_RTL_MESH_CROSSBAND) - sync_proxy_info(priv->mesh_priv_sc,Entry.sta, 0); //refresh proxy info of another band - #endif - } else if(memcmp(pProxyEntry->owner, owner, MACADDRLEN)) { - - mesh_proxy_debug("[A6 forwardding]Update Proxy table:from %02x:%02x:%02x:%02x:%02x:%02x to %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - pProxyEntry->owner[0],pProxyEntry->owner[1],pProxyEntry->owner[2],pProxyEntry->owner[3],pProxyEntry->owner[4],pProxyEntry->owner[5], - owner[0],owner[1],owner[2],owner[3],owner[4],owner[5], - pProxyEntry->sta[0],pProxyEntry->sta[1],pProxyEntry->sta[2],pProxyEntry->sta[3],pProxyEntry->sta[4],pProxyEntry->sta[5]); - - - - memcpy(pProxyEntry->owner, owner, MACADDRLEN); - pProxyEntry->aging_time = 0; - - #if defined(RTL_MESH_TXCACHE) - priv->mesh_txcache.dirty = 0; - #endif - - #if defined(CONFIG_RTL_MESH_CROSSBAND) - sync_proxy_info(priv->mesh_priv_sc,pProxyEntry->sta, 2); //delete proxy info of another band - #endif - } else { - pProxyEntry->aging_time = 0; - mesh_proxy_debug("[A6 forwardding]Refresh Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - pProxyEntry->owner[0],pProxyEntry->owner[1],pProxyEntry->owner[2],pProxyEntry->owner[3],pProxyEntry->owner[4],pProxyEntry->owner[5], - pProxyEntry->sta[0],pProxyEntry->sta[1],pProxyEntry->sta[2],pProxyEntry->sta[3],pProxyEntry->sta[4],pProxyEntry->sta[5]); - - #if defined(CONFIG_RTL_MESH_CROSSBAND) - sync_proxy_info(priv->mesh_priv_sc, pProxyEntry->sta, 0); //refresh proxy info of another band - #endif - - } - - SMP_UNLOCK_MESH_PROXY(flags); - return 0; - -} - - -static int __mesh_proxy_insert(struct rtl8192cd_priv *priv, unsigned char *sta) { -#ifdef SMP_SYNC - unsigned long flags; -#endif - struct proxy_table_entry Entry, *pEntry; - - if(!IS_DRV_OPEN(priv) || GET_MIB(priv)->dot1180211sInfo.mesh_enable == 0) { - return -1; - } - - SMP_LOCK_MESH_PROXY(flags); - pEntry = HASH_SEARCH(priv->proxy_table, sta); - if(pEntry) { - - pEntry->aging_time = -1; /*never timeout*/ - - if(memcmp(pEntry->owner, GET_MY_HWADDR, MACADDRLEN)) { - mesh_proxy_debug("[%s %d]Update Proxy table from %02x:%02x:%02x:%02x:%02x:%02x to %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - __func__,__LINE__, pEntry->owner[0],pEntry->owner[1],pEntry->owner[2],pEntry->owner[3],pEntry->owner[4],pEntry->owner[5], - priv->pmib->dot11OperationEntry.hwaddr[0], priv->pmib->dot11OperationEntry.hwaddr[1], - priv->pmib->dot11OperationEntry.hwaddr[2], priv->pmib->dot11OperationEntry.hwaddr[3], - priv->pmib->dot11OperationEntry.hwaddr[4], priv->pmib->dot11OperationEntry.hwaddr[5], - pEntry->sta[0],pEntry->sta[1],pEntry->sta[2],pEntry->sta[3],pEntry->sta[4],pEntry->sta[5]); - memcpy(pEntry->owner, GET_MY_HWADDR, MACADDRLEN); - - #if defined(RTL_MESH_TXCACHE) - priv->mesh_txcache.dirty = 0; - #endif - - SMP_UNLOCK_MESH_PROXY(flags); - - #if defined(PU_STANDARD_SME) - issue_proxyupdate_ADD(priv, sta); - #endif - } - else { - mesh_proxy_debug("[%s %d]Refresh Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - __func__,__LINE__,pEntry->owner[0],pEntry->owner[1],pEntry->owner[2],pEntry->owner[3],pEntry->owner[4],pEntry->owner[5], - pEntry->sta[0],pEntry->sta[1],pEntry->sta[2],pEntry->sta[3],pEntry->sta[4],pEntry->sta[5]); - SMP_UNLOCK_MESH_PROXY(flags); - - } - - } - else { - struct path_sel_entry *path_entry = NULL; - path_entry = HASH_SEARCH(priv->pathsel_table, sta); - if (path_entry) - return 0; - memcpy(Entry.sta, sta, MACADDRLEN); - memcpy(Entry.owner, GET_MY_HWADDR, MACADDRLEN); - Entry.aging_time = -1; /*never timeout*/ - HASH_INSERT(priv->proxy_table, Entry.sta, &Entry); - - SMP_UNLOCK_MESH_PROXY(flags); - - mesh_proxy_debug("[%s %d]Insert Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", - __func__,__LINE__,Entry.owner[0],Entry.owner[1],Entry.owner[2],Entry.owner[3],Entry.owner[4],Entry.owner[5], - Entry.sta[0],Entry.sta[1],Entry.sta[2],Entry.sta[3],Entry.sta[4],Entry.sta[5]); - - #if defined(PU_STANDARD_SME) - issue_proxyupdate_ADD(priv, sta); - #endif - } - - return 0; - -} - -void mesh_proxy_insert(struct rtl8192cd_priv *priv, unsigned char *sta) -{ - if(netif_running(priv->mesh_dev)) { -#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) - priv = priv->mesh_priv_first; -#endif //CONFIG_RTL_MESH_SINGLE_IFACE - if(priv->pmib->dot1180211sInfo.mesh_portal_enable) { - __mesh_proxy_insert(priv, sta); - - #if defined(CONFIG_RTL_MESH_CROSSBAND) - if(priv->mesh_priv_sc) { - if(__mesh_proxy_insert(priv->mesh_priv_sc, sta)) //insert proxy info - mesh_proxy_debug("Sync proxy information to %s failed\n",priv->mesh_priv_sc->dev->name); - } - #endif - } - } -} - -#endif // _DOT11_MESH_MODE - +/* + * Handling routines for Mesh in 802.11 Utils + * + * PS: All extern function in ../8190n_headers.h + */ +#define _MESH_UTIL_C_ + +#ifdef CONFIG_RTL8192CD +#include "../8192cd.h" +#include "../8192cd_headers.h" +#else +#include "../rtl8190/8190n.h" +#include "../rtl8190/8190n_headers.h" +#endif +#include "./mesh_util.h" +#include + +#ifdef CONFIG_RTK_MESH +int clear_route_info(struct rtl8192cd_priv *priv, unsigned char *delMAC) +{ + struct path_sel_entry *pEntry = 0; + unsigned long flags, i=0; + int tbl_sz; + unsigned char destMAC[MACADDRLEN]; + int is_delete; +#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) + priv = (DRV_PRIV *)priv->mesh_priv_first; +#endif //CONFIG_RTL_MESH_SINGLE_IFACE + tbl_sz = (1 << priv->pathsel_table->table_size_power); + + //clean up path relative to invalid neighbor + for(;ipathsel_table->entry_array[i].dirty) { + pEntry = (struct path_sel_entry *)(priv->pathsel_table->entry_array[i].data); + if(memcmp(delMAC, pEntry->nexthopMAC,MACADDRLEN)==0) { + priv->pathsel_table->entry_array[i].dirty = 0; + memcpy(destMAC, pEntry->destMAC, MACADDRLEN); + is_delete = 1; + } + } + RESTORE_INT(flags); + SMP_UNLOCK_MESH_PATH(flags); + + if(is_delete) { + #if defined(RTL_MESH_TXCACHE) + expire_mesh_txcache(priv, destMAC); + #endif + } + } + + remove_proxy_owner(priv, delMAC); + + return SUCCESS; +} + +void mac12_to_6(unsigned char *mac1, unsigned char *mac2) +{ + short m=0; + for( ; m='a')?(mac1[1|(m<<1)]-('a'-0xa)):(mac1[1|(m<<1)]-'0'))|((((mac1[m<<1])>='a')?(mac1[m<<1]-('a'-0xa)):(mac1[m<<1]-'0'))<<4); +} + +/* + * @brief Count MESH Association number and display + * + * @param priv:priv + * @param pstat: pstat + * @param act: action + * INCREASE = New peer MP (action: minus peer cap) + * DECREASE = Delete exist connect MP (acton: Plus peer cap) + * + * @retval void + */ +void mesh_cnt_ASSOC_PeerLink_CAP(DRV_PRIV *priv, struct stat_info *pstat, int act) +{ + UINT8 modify = TRUE; + struct list_head *phead, *plist; + INT16 mesh_assoc_sum = 0; + +//we need to recalculate to prevent peer running out accidently + phead = &priv->mesh_mp_hdr; + plist = phead->next; + while (plist != phead) { + mesh_assoc_sum++; + plist = plist->next; + } + MESH_PEER_LINK_CAP_NUM(priv) = MAX_MPP_NUM - mesh_assoc_sum; + + if (DECREASE == act) { + if (MESH_PEER_LINK_CAP_NUM(priv) < GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor) + MESH_PEER_LINK_CAP_NUM(priv)++; + else { + modify = FALSE; + MESH_DEBUG_MSG("MESH PeerLink CAP Number Error (%d)!\n", GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor); + } + } else { + if (MESH_PEER_LINK_CAP_NUM(priv) <= 0) { + modify = FALSE; + printk("MESH PeerLink CAP Number Error (0)!\n"); + } + } + + if (TRUE == modify) + update_beacon(priv); // Because MESH_PEER_LINK_CAP_NUM modify (beacon include WLAN Mesh Capacity) + + mesh_sme_debug("Mesh assoc_num: %s(Max:%d, Remain:%d) %02X:%02X:%02X:%02X:%02X:%02X\n", + act?"++":"--", + GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor, + MESH_PEER_LINK_CAP_NUM(priv), + pstat->hwaddr[0], + pstat->hwaddr[1], + pstat->hwaddr[2], + pstat->hwaddr[3], + pstat->hwaddr[4], + pstat->hwaddr[5]); + +} + +/* + * @brief Set MESH Association Max number (call by web interface?) + * Note: If setting value(meshCapSetValue) less system current connection number, MESH_PEER_LINK_CAP_NUM become negative, Denied any new connection. + * Delete exist connect ONLY!! + * SO + * MESH_PEER_LINK_CAP_NUM = 0 : setting = connection, Denied any new connection + * MESH_PEER_LINK_CAP_NUM > 0 (< MAX_MPP_NUM) : setting > connection ,Allow new connect + * MESH_PEER_LINK_CAP_NUM = MAX_MPP_NUM : connection = 0 ,Allow new connect + * + * @param priv:priv + * @param meshCapSetValue: set connect number + * + * @retval void + */ +void mesh_set_PeerLink_CAP(DRV_PRIV *priv, UINT16 meshCapSetValue) +{ + struct list_head *plist; + +#ifndef SMP_SYNC + unsigned long flags; +#endif + + UINT16 count = 0; + + SAVE_INT_AND_CLI(flags); + + meshCapSetValue &= MESH_PEER_LINK_CAP_CAPACITY_MASK; + + if (MAX_MPP_NUM < meshCapSetValue) + meshCapSetValue = MAX_MPP_NUM; // Exceed hard code MAX number, Lock on hardcode MAX number + + GET_MIB(priv)->dot1180211sInfo.mesh_max_neightbor = meshCapSetValue; // Writeback runtime Max value (Avoid web interface fault) + + // Recalculate current connection number by association list (Avoid problem when CAP value error) + plist = &(priv->mesh_mp_hdr); + while (plist->next != &(priv->mesh_mp_hdr)) // 1.Check index 2.Check is it least element? (Because next pointer to mesh_mp_hdr itself) + { + count++; + plist = plist->next; // pointer to next element's list_head struct + } + + MESH_PEER_LINK_CAP_NUM(priv) = (INT16)(meshCapSetValue - count); // Setting - current connection number -> CAP (NOTE: Allow POS/NEG value) + RESTORE_INT(flags); + init_beacon(priv); + return; +} + +int remove_proxy_owner(DRV_PRIV *priv, unsigned char *owner) +{ +#ifdef SMP_SYNC + unsigned long flags; +#endif + struct proxy_table_entry *pxEntry = 0; + int i, tbl_sz; +#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) + priv = (DRV_PRIV *)priv->mesh_priv_first; +#endif //CONFIG_RTL_MESH_SINGLE_IFACE + + SMP_LOCK_MESH_PROXY(flags); + //clean up proxy entry relative to invalid neighbor + tbl_sz = (1 << priv->proxy_table->table_size_power); + for(i=0;iproxy_table->entry_array[i].dirty) { + pxEntry = (struct proxy_table_entry *)(priv->proxy_table->entry_array[i].data); + if(memcmp(owner,pxEntry->owner,MACADDRLEN)==0){ + priv->proxy_table->entry_array[i].dirty = 0; + mesh_proxy_debug("[%s %d]Delete Proxy entry of %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + __func__,__LINE__,pxEntry->owner[0],pxEntry->owner[1],pxEntry->owner[2],pxEntry->owner[3],pxEntry->owner[4],pxEntry->owner[5], + pxEntry->sta[0],pxEntry->sta[1],pxEntry->sta[2],pxEntry->sta[3],pxEntry->sta[4],pxEntry->sta[5]); + } + } + } + SMP_UNLOCK_MESH_PROXY(flags); + + + return 0; +} + + +int remove_proxy_entry(DRV_PRIV *priv, unsigned char *owner, unsigned char* sta) +{ +#ifdef SMP_SYNC + unsigned long flags; +#endif + struct proxy_table_entry* pPXEntry; + int process = 0; +#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) + priv = (DRV_PRIV *)priv->mesh_priv_first; +#endif //CONFIG_RTL_MESH_SINGLE_IFACE + SMP_LOCK_MESH_PROXY(flags); + + pPXEntry = HASH_SEARCH(priv->proxy_table, sta); + if( pPXEntry ) { + if( owner == NULL) { + if(memcmp(pPXEntry->owner, GET_MY_HWADDR, MACADDRLEN) == 0) + process = 1; + } + else{ + if(memcmp(pPXEntry->owner, owner, MACADDRLEN) == 0) + process = 1; + } + + if(process) + { + HASH_DELETE(priv->proxy_table,sta); + mesh_proxy_debug("[%s %d]Delete Proxy entry of %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + __func__,__LINE__, pPXEntry->owner[0], pPXEntry->owner[1],pPXEntry->owner[2],pPXEntry->owner[3],pPXEntry->owner[4],pPXEntry->owner[5], + sta[0],sta[1],sta[2],sta[3],sta[4],sta[5]); + #if defined(CONFIG_RTL_MESH_CROSSBAND) + sync_proxy_info(priv->mesh_priv_sc, sta, 2); //delete proxy info of another band + #endif + + #if defined(RTL_MESH_TXCACHE) + priv->mesh_txcache.dirty = 0; + #endif + } + } + + SMP_UNLOCK_MESH_PROXY(flags); + + return 0; +} + + +int mesh_proxy_update(DRV_PRIV *priv, unsigned char* owner, unsigned char* sta) { +#ifdef SMP_SYNC + unsigned long flags; +#endif + struct proxy_table_entry* pProxyEntry = NULL, Entry; +#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) + priv = (DRV_PRIV *)priv->mesh_priv_first; +#endif //CONFIG_RTL_MESH_SINGLE_IFACE + SMP_LOCK_MESH_PROXY(flags); + + pProxyEntry = (struct proxy_table_entry*) HASH_SEARCH(priv->proxy_table, sta); + if(!pProxyEntry) { + struct path_sel_entry *path_entry = NULL; + path_entry = HASH_SEARCH(priv->pathsel_table, sta); + if (path_entry) + return 0; + memcpy(Entry.sta, sta, MACADDRLEN); + memcpy(Entry.owner, owner, MACADDRLEN); + Entry.aging_time = 0; + HASH_INSERT(priv->proxy_table, Entry.sta, &Entry); + + mesh_proxy_debug("[A6 forwardding]Insert Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + Entry.owner[0],Entry.owner[1],Entry.owner[2],Entry.owner[3],Entry.owner[4],Entry.owner[5], + Entry.sta[0],Entry.sta[1],Entry.sta[2],Entry.sta[3],Entry.sta[4],Entry.sta[5]); + + #if defined(CONFIG_RTL_MESH_CROSSBAND) + sync_proxy_info(priv->mesh_priv_sc,Entry.sta, 0); //refresh proxy info of another band + #endif + } else if(memcmp(pProxyEntry->owner, owner, MACADDRLEN)) { + + mesh_proxy_debug("[A6 forwardding]Update Proxy table:from %02x:%02x:%02x:%02x:%02x:%02x to %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + pProxyEntry->owner[0],pProxyEntry->owner[1],pProxyEntry->owner[2],pProxyEntry->owner[3],pProxyEntry->owner[4],pProxyEntry->owner[5], + owner[0],owner[1],owner[2],owner[3],owner[4],owner[5], + pProxyEntry->sta[0],pProxyEntry->sta[1],pProxyEntry->sta[2],pProxyEntry->sta[3],pProxyEntry->sta[4],pProxyEntry->sta[5]); + + + + memcpy(pProxyEntry->owner, owner, MACADDRLEN); + pProxyEntry->aging_time = 0; + + #if defined(RTL_MESH_TXCACHE) + priv->mesh_txcache.dirty = 0; + #endif + + #if defined(CONFIG_RTL_MESH_CROSSBAND) + sync_proxy_info(priv->mesh_priv_sc,pProxyEntry->sta, 2); //delete proxy info of another band + #endif + } else { + pProxyEntry->aging_time = 0; + mesh_proxy_debug("[A6 forwardding]Refresh Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + pProxyEntry->owner[0],pProxyEntry->owner[1],pProxyEntry->owner[2],pProxyEntry->owner[3],pProxyEntry->owner[4],pProxyEntry->owner[5], + pProxyEntry->sta[0],pProxyEntry->sta[1],pProxyEntry->sta[2],pProxyEntry->sta[3],pProxyEntry->sta[4],pProxyEntry->sta[5]); + + #if defined(CONFIG_RTL_MESH_CROSSBAND) + sync_proxy_info(priv->mesh_priv_sc, pProxyEntry->sta, 0); //refresh proxy info of another band + #endif + + } + + SMP_UNLOCK_MESH_PROXY(flags); + return 0; + +} + + +static int __mesh_proxy_insert(struct rtl8192cd_priv *priv, unsigned char *sta) { +#ifdef SMP_SYNC + unsigned long flags; +#endif + struct proxy_table_entry Entry, *pEntry; + + if(!IS_DRV_OPEN(priv) || GET_MIB(priv)->dot1180211sInfo.mesh_enable == 0) { + return -1; + } + + SMP_LOCK_MESH_PROXY(flags); + pEntry = HASH_SEARCH(priv->proxy_table, sta); + if(pEntry) { + + pEntry->aging_time = -1; /*never timeout*/ + + if(memcmp(pEntry->owner, GET_MY_HWADDR, MACADDRLEN)) { + mesh_proxy_debug("[%s %d]Update Proxy table from %02x:%02x:%02x:%02x:%02x:%02x to %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + __func__,__LINE__, pEntry->owner[0],pEntry->owner[1],pEntry->owner[2],pEntry->owner[3],pEntry->owner[4],pEntry->owner[5], + priv->pmib->dot11OperationEntry.hwaddr[0], priv->pmib->dot11OperationEntry.hwaddr[1], + priv->pmib->dot11OperationEntry.hwaddr[2], priv->pmib->dot11OperationEntry.hwaddr[3], + priv->pmib->dot11OperationEntry.hwaddr[4], priv->pmib->dot11OperationEntry.hwaddr[5], + pEntry->sta[0],pEntry->sta[1],pEntry->sta[2],pEntry->sta[3],pEntry->sta[4],pEntry->sta[5]); + memcpy(pEntry->owner, GET_MY_HWADDR, MACADDRLEN); + + #if defined(RTL_MESH_TXCACHE) + priv->mesh_txcache.dirty = 0; + #endif + + SMP_UNLOCK_MESH_PROXY(flags); + + #if defined(PU_STANDARD_SME) + issue_proxyupdate_ADD(priv, sta); + #endif + } + else { + mesh_proxy_debug("[%s %d]Refresh Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + __func__,__LINE__,pEntry->owner[0],pEntry->owner[1],pEntry->owner[2],pEntry->owner[3],pEntry->owner[4],pEntry->owner[5], + pEntry->sta[0],pEntry->sta[1],pEntry->sta[2],pEntry->sta[3],pEntry->sta[4],pEntry->sta[5]); + SMP_UNLOCK_MESH_PROXY(flags); + + } + + } + else { + struct path_sel_entry *path_entry = NULL; + path_entry = HASH_SEARCH(priv->pathsel_table, sta); + if (path_entry) + return 0; + memcpy(Entry.sta, sta, MACADDRLEN); + memcpy(Entry.owner, GET_MY_HWADDR, MACADDRLEN); + Entry.aging_time = -1; /*never timeout*/ + HASH_INSERT(priv->proxy_table, Entry.sta, &Entry); + + SMP_UNLOCK_MESH_PROXY(flags); + + mesh_proxy_debug("[%s %d]Insert Proxy table: %02x:%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x:%02x\n", + __func__,__LINE__,Entry.owner[0],Entry.owner[1],Entry.owner[2],Entry.owner[3],Entry.owner[4],Entry.owner[5], + Entry.sta[0],Entry.sta[1],Entry.sta[2],Entry.sta[3],Entry.sta[4],Entry.sta[5]); + + #if defined(PU_STANDARD_SME) + issue_proxyupdate_ADD(priv, sta); + #endif + } + + return 0; + +} + +void mesh_proxy_insert(struct rtl8192cd_priv *priv, unsigned char *sta) +{ + if(netif_running(priv->mesh_dev)) { +#if defined(CONFIG_RTL_MESH_SINGLE_IFACE) + priv = priv->mesh_priv_first; +#endif //CONFIG_RTL_MESH_SINGLE_IFACE + if(priv->pmib->dot1180211sInfo.mesh_portal_enable) { + __mesh_proxy_insert(priv, sta); + + #if defined(CONFIG_RTL_MESH_CROSSBAND) + if(priv->mesh_priv_sc) { + if(__mesh_proxy_insert(priv->mesh_priv_sc, sta)) //insert proxy info + mesh_proxy_debug("Sync proxy information to %s failed\n",priv->mesh_priv_sc->dev->name); + } + #endif + } + } +} + +#endif // _DOT11_MESH_MODE + diff --git a/package/kernel/rtl8192cd/odm_inc.h b/package/kernel/rtl8192cd/odm_inc.h old mode 100755 new mode 100644 index b0f755f9080..141c4d1e7d9 --- a/package/kernel/rtl8192cd/odm_inc.h +++ b/package/kernel/rtl8192cd/odm_inc.h @@ -1,349 +1,349 @@ -//============================================================ -// File Name: AP_precomp.h -// -// Description: -// -//============================================================ - - -#ifndef __AP_PRECOMP_H__ -#define __AP_PRECOMP_H__ - -#define DM_ODM_SUPPORT_TYPE ODM_AP -#if defined(CONFIG_PCI_HCI) -#define DEV_BUS_TYPE RT_PCI_INTERFACE -#elif defined(CONFIG_USB_HCI) -#define DEV_BUS_TYPE RT_USB_INTERFACE -#elif defined(CONFIG_SDIO_HCI) -#define DEV_BUS_TYPE RT_SDIO_INTERFACE -#endif -#ifdef __ECOS -#define DBG 0 -#else -#define DBG 1 -#endif -//----------------------------------------------------------------------------------------- -// Use one of the following value to define the flag, RT_PLATFORM. -//----------------------------------------------------------------------------------------- -#define PLATFORM_WINDOWS 0 -#define PLATFORM_LINUX 1 -#define PLATFORM_FREEBSD 3 -#define PLATFORM_MACOSX 4 - -#define RT_PLATFORM PLATFORM_LINUX - - -//2 [HAL\HWIMG\HalHWImg.h] - -#define RTL8192CU_HWIMG_SUPPORT 0 -#define RTL8192CU_TEST_HWIMG_SUPPORT 0 - -#define RTL8192D_HWIMG_SUPPORT 0 - -#define RTL8723_FPGA_VERIFICATION 0 -#define RTL8723S_HWIMG_SUPPORT 0 -#define RTL8723U_HWIMG_SUPPORT 0 -#define RTL8723A_HWIMG_SUPPORT 0 - -#ifdef CONFIG_RTL_88E_SUPPORT -#define RTL8188E_SUPPORT 1 -#define RTL8188ES_HWIMG_SUPPORT 1 -#define RATE_ADAPTIVE_SUPPORT 1 - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) || defined(RATEADAPTIVE_BY_ODM) -#define RATE_ADAPTIVE_SUPPORT 1 -#endif -#define RTL8188E_FOR_TEST_CHIP 0 - -#else -#define RTL8188E_SUPPORT 0 -#define RTL8188ES_HWIMG_SUPPORT 0 -#define RATE_ADAPTIVE_SUPPORT 0 -#endif - -#if defined(CONFIG_RTL_92C_SUPPORT) && !defined(_OUTSRC_COEXIST) -#define RTL8192C_SUPPORT 1 -#define RTL8192C_HWIMG_SUPPORT 1 -#define RTL8192CE_HWIMG_SUPPORT 1 -#define RTL8192CE_TEST_HWIMG_SUPPORT 1 -#else -#define RTL8192C_SUPPORT 0 -#define RTL8192C_HWIMG_SUPPORT 0 -#define RTL8192CE_HWIMG_SUPPORT 0 -#define RTL8192CE_TEST_HWIMG_SUPPORT 0 -#endif - -#if defined(CONFIG_RTL_92D_SUPPORT) && !defined(_OUTSRC_COEXIST) -#define RTL8192D_SUPPORT 1 -#else -#define RTL8192D_SUPPORT 0 -#endif - -#ifdef CONFIG_RTL_8812_SUPPORT //FOR_8812_IQK -#define RTL8812A_SUPPORT 1 -#else -#define RTL8812A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8881A -#define RTL8881A_SUPPORT 1 -#else -#define RTL8881A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8192EE -#define RTL8192E_SUPPORT 1 -#else -#define RTL8192E_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8814AE -#define RTL8814A_SUPPORT 1 -#else -#define RTL8814A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8195A -#define RTL8195A_SUPPORT 1 -#else -#define RTL8195A_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8822BE -#define RTL8822B_SUPPORT 1 -#else -#define RTL8822B_SUPPORT 0 -#endif - -#ifdef CONFIG_WLAN_HAL_8197F -#define RTL8197F_SUPPORT 1 -#else -#define RTL8197F_SUPPORT 0 -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#define RTL8723A_SUPPORT 0 -#ifdef CONFIG_RTL_8723B_SUPPORT -#define RTL8723B_SUPPORT 1 -#else -#define RTL8723B_SUPPORT 0 -#endif -#define RTL8821A_SUPPORT 0 -#ifdef BT_COEXIST_HAL -#define BT_30_SUPPORT 1 -#else -#define BT_30_SUPPORT 0 -#endif -#define RTL8188F_SUPPORT 0 -#define RTL8703B_SUPPORT 0 -#define RTL8723D_SUPPORT 0 -#define RTL8821C_SUPPORT 0 -#endif - -//2 [HEADER\TypeDef.h] - -#define IN -#define OUT - -//#define TRUE 1 -//#define FALSE 0 - -#define TxPwrTrk_OFDM_SwingTbl_Len 37 -#define TxPwrTrk_CCK_SwingTbl_Len 23 -#define TxPwrTrk_E_Val 3 - -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM_MAX 10 -#define HP_THERMAL_NUM 8 -#define DM_Type_ByFW 0 -#define DM_Type_ByDriver 1 -#define MAX_TX_COUNT 4 -#define index_mapping_NUM 13 -#define index_mapping_DPK_NUM 15 -#define Rx_index_mapping_NUM 15 -#define CCK_TABLE_SIZE_92D 33 - - -#define RT_MEM_SIZE_LEVEL 2 // ? -#define RT_MEM_SIZE_MINIMUM 3 // ? - -#define USE_WORKITEM 0 - -// -// Customer ID, note that: -// This variable is initiailzed through EEPROM or registry, -// however, its definition may be different with that in EEPROM for -// EEPROM size consideration. So, we have to perform proper translation between them. -// Besides, CustomerID of registry has precedence of that of EEPROM. -// defined below. 060703, by rcnjko. -// -typedef enum _RT_CUSTOMER_ID -{ - RT_CID_DEFAULT = 0, - RT_CID_8187_ALPHA0 = 1, - RT_CID_8187_SERCOMM_PS = 2, - RT_CID_8187_HW_LED = 3, - RT_CID_8187_NETGEAR = 4, - RT_CID_WHQL = 5, - RT_CID_819x_CAMEO = 6, - RT_CID_819x_RUNTOP = 7, - RT_CID_819x_Senao = 8, - RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. - RT_CID_819x_Netcore = 10, - RT_CID_Nettronix = 11, - RT_CID_DLINK = 12, - RT_CID_PRONET = 13, - RT_CID_COREGA = 14, - RT_CID_CHINA_MOBILE = 15, - RT_CID_819x_ALPHA = 16, - RT_CID_819x_Sitecom = 17, - RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. - RT_CID_819x_Lenovo = 19, - RT_CID_819x_QMI = 20, - RT_CID_819x_Edimax_Belkin = 21, - RT_CID_819x_Sercomm_Belkin = 22, - RT_CID_819x_CAMEO1 = 23, - RT_CID_819x_MSI = 24, - RT_CID_819x_Acer = 25, - RT_CID_819x_AzWave_ASUS = 26, - RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus - RT_CID_819x_HP = 28, - RT_CID_819x_WNC_COREGA = 29, - RT_CID_819x_Arcadyan_Belkin = 30, - RT_CID_819x_SAMSUNG = 31, - RT_CID_819x_CLEVO = 32, - RT_CID_819x_DELL = 33, - RT_CID_819x_PRONETS = 34, - RT_CID_819x_Edimax_ASUS = 35, - RT_CID_NETGEAR = 36, - RT_CID_PLANEX = 37, - RT_CID_CC_C = 38, -}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; - - -typedef enum _RF_RADIO_PATH{ - RF_PATH_A = 0, //Radio Path A - RF_PATH_B = 1, //Radio Path B - RF_PATH_C = 2, //Radio Path C - RF_PATH_D = 3, //Radio Path D - RF_PATH_MAX //Max RF number 90 support -}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; - - -// Rx smooth factor -#define Rx_Smooth_Factor 20 - -typedef struct _HAL_DATA_TYPE{ - u1Byte temp; -} HAL_DATA_TYPE; - -#define GET_HAL_DATA(pa) (pa->temp2) - -typedef struct _RFD { - u1Byte temp; -} RFD, *PRT_RFD; - -typedef struct _RSSI_STA{ - s4Byte UndecoratedSmoothedPWDB; - s4Byte UndecoratedSmoothedCCK; - s4Byte UndecoratedSmoothedOFDM; - u4Byte OFDM_pkt; - u1Byte CCK_pkt; - u2Byte CCK_sum_power; - u1Byte bsend_rssi; - u8Byte PacketMap; - u1Byte ValidBit; -}RSSI_STA, *PRSSI_STA; - - -/* Define different debug flag for dedicated service modules in debug flag array. */ -// Each module has independt 32 bit debug flag you cnn define the flag as yout require. -typedef enum tag_DBGP_Flag_Type_Definition -{ - FQoS = 0, - FTX = 1, - FRX = 2, - FSEC = 3, - FMGNT = 4, - FMLME = 5, - FRESOURCE = 6, - FBEACON = 7, - FISR = 8, - FPHY = 9, - FMP = 10, - FEEPROM = 11, - FPWR = 12, - FDM = 13, - FDBG_CTRL = 14, - FC2H = 15, - FBT = 16, - FINIT = 17, - FIOCTL = 18, - FSHORT_CUT = 19, - DBGP_TYPE_MAX -}DBGP_FLAG_E; - - -//extern u8Byte GlobalDebugComponents; - -#define RTL8192DE_HWIMG_SUPPORT 0 -#define RTL8192DU_HWIMG_SUPPORT 0 -#define RTL8723U_HWIMG_SUPPORT 0 -#define RTL8723S_HWIMG_SUPPORT 0 - -#define VISTA_USB_RX_REVISE 0 - - -#if 0 -typedef enum _RT_STATUS{ - RT_STATUS_SUCCESS, - RT_STATUS_FAILURE, - RT_STATUS_PENDING, - RT_STATUS_RESOURCE, - RT_STATUS_INVALID_CONTEXT, - RT_STATUS_INVALID_PARAMETER, - RT_STATUS_NOT_SUPPORT, - RT_STATUS_OS_API_FAILED, -}RT_STATUS,*PRT_STATUS; -#endif - - typedef enum _RF_CONTENT{ - radioa_txt = 0x1000, - radiob_txt = 0x1001, - radioc_txt = 0x1002, - radiod_txt = 0x1003 -} RF_CONTENT; - -/* -#define REG_EDCA_VI_PARAM EDCA_VI_PARA -#define REG_EDCA_VO_PARAM EDCA_VO_PARA -#define REG_EDCA_BE_PARAM EDCA_BE_PARA -#define REG_EDCA_BK_PARAM EDCA_BK_PARA -*/ - -#define bRFRegOffsetMask 0xfffff - -#define odm_ConfigMAC_8192C(...) {} -#define odm_ConfigRF_RadioA_8192C(...) {} -#define odm_ConfigRF_RadioB_8192C(...) {} -#define odm_ConfigBB_PHY_8192C(...) {} -#define odm_ConfigBB_AGC_8192C(...) {} - -#define PlatformStallExecution ODM_StallExecution - -#ifndef WLAN_HAL_INTERNAL_USED -#define REG_ARFR0 ARFR0 -#define REG_ARFR1 ARFR1 -#define REG_ARFR2 ARFR2 -#define REG_ARFR3 ARFR3 - -#define REG_TX_RPT_TIME REG_88E_TXRPT_TIM -#endif //#ifndef WLAN_HAL_INTERNAL_USED - -/*put the line at the end*/ -#include "phydm/phydm_features.h" - - - -#endif +//============================================================ +// File Name: AP_precomp.h +// +// Description: +// +//============================================================ + + +#ifndef __AP_PRECOMP_H__ +#define __AP_PRECOMP_H__ + +#define DM_ODM_SUPPORT_TYPE ODM_AP +#if defined(CONFIG_PCI_HCI) +#define DEV_BUS_TYPE RT_PCI_INTERFACE +#elif defined(CONFIG_USB_HCI) +#define DEV_BUS_TYPE RT_USB_INTERFACE +#elif defined(CONFIG_SDIO_HCI) +#define DEV_BUS_TYPE RT_SDIO_INTERFACE +#endif +#ifdef __ECOS +#define DBG 0 +#else +#define DBG 1 +#endif +//----------------------------------------------------------------------------------------- +// Use one of the following value to define the flag, RT_PLATFORM. +//----------------------------------------------------------------------------------------- +#define PLATFORM_WINDOWS 0 +#define PLATFORM_LINUX 1 +#define PLATFORM_FREEBSD 3 +#define PLATFORM_MACOSX 4 + +#define RT_PLATFORM PLATFORM_LINUX + + +//2 [HAL\HWIMG\HalHWImg.h] + +#define RTL8192CU_HWIMG_SUPPORT 0 +#define RTL8192CU_TEST_HWIMG_SUPPORT 0 + +#define RTL8192D_HWIMG_SUPPORT 0 + +#define RTL8723_FPGA_VERIFICATION 0 +#define RTL8723S_HWIMG_SUPPORT 0 +#define RTL8723U_HWIMG_SUPPORT 0 +#define RTL8723A_HWIMG_SUPPORT 0 + +#ifdef CONFIG_RTL_88E_SUPPORT +#define RTL8188E_SUPPORT 1 +#define RTL8188ES_HWIMG_SUPPORT 1 +#define RATE_ADAPTIVE_SUPPORT 1 + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) || defined(RATEADAPTIVE_BY_ODM) +#define RATE_ADAPTIVE_SUPPORT 1 +#endif +#define RTL8188E_FOR_TEST_CHIP 0 + +#else +#define RTL8188E_SUPPORT 0 +#define RTL8188ES_HWIMG_SUPPORT 0 +#define RATE_ADAPTIVE_SUPPORT 0 +#endif + +#if defined(CONFIG_RTL_92C_SUPPORT) && !defined(_OUTSRC_COEXIST) +#define RTL8192C_SUPPORT 1 +#define RTL8192C_HWIMG_SUPPORT 1 +#define RTL8192CE_HWIMG_SUPPORT 1 +#define RTL8192CE_TEST_HWIMG_SUPPORT 1 +#else +#define RTL8192C_SUPPORT 0 +#define RTL8192C_HWIMG_SUPPORT 0 +#define RTL8192CE_HWIMG_SUPPORT 0 +#define RTL8192CE_TEST_HWIMG_SUPPORT 0 +#endif + +#if defined(CONFIG_RTL_92D_SUPPORT) && !defined(_OUTSRC_COEXIST) +#define RTL8192D_SUPPORT 1 +#else +#define RTL8192D_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL_8812_SUPPORT //FOR_8812_IQK +#define RTL8812A_SUPPORT 1 +#else +#define RTL8812A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8881A +#define RTL8881A_SUPPORT 1 +#else +#define RTL8881A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8192EE +#define RTL8192E_SUPPORT 1 +#else +#define RTL8192E_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8814AE +#define RTL8814A_SUPPORT 1 +#else +#define RTL8814A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8195A +#define RTL8195A_SUPPORT 1 +#else +#define RTL8195A_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8822BE +#define RTL8822B_SUPPORT 1 +#else +#define RTL8822B_SUPPORT 0 +#endif + +#ifdef CONFIG_WLAN_HAL_8197F +#define RTL8197F_SUPPORT 1 +#else +#define RTL8197F_SUPPORT 0 +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#define RTL8723A_SUPPORT 0 +#ifdef CONFIG_RTL_8723B_SUPPORT +#define RTL8723B_SUPPORT 1 +#else +#define RTL8723B_SUPPORT 0 +#endif +#define RTL8821A_SUPPORT 0 +#ifdef BT_COEXIST_HAL +#define BT_30_SUPPORT 1 +#else +#define BT_30_SUPPORT 0 +#endif +#define RTL8188F_SUPPORT 0 +#define RTL8703B_SUPPORT 0 +#define RTL8723D_SUPPORT 0 +#define RTL8821C_SUPPORT 0 +#endif + +//2 [HEADER\TypeDef.h] + +#define IN +#define OUT + +//#define TRUE 1 +//#define FALSE 0 + +#define TxPwrTrk_OFDM_SwingTbl_Len 37 +#define TxPwrTrk_CCK_SwingTbl_Len 23 +#define TxPwrTrk_E_Val 3 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#define HP_THERMAL_NUM 8 +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 +#define MAX_TX_COUNT 4 +#define index_mapping_NUM 13 +#define index_mapping_DPK_NUM 15 +#define Rx_index_mapping_NUM 15 +#define CCK_TABLE_SIZE_92D 33 + + +#define RT_MEM_SIZE_LEVEL 2 // ? +#define RT_MEM_SIZE_MINIMUM 3 // ? + +#define USE_WORKITEM 0 + +// +// Customer ID, note that: +// This variable is initiailzed through EEPROM or registry, +// however, its definition may be different with that in EEPROM for +// EEPROM size consideration. So, we have to perform proper translation between them. +// Besides, CustomerID of registry has precedence of that of EEPROM. +// defined below. 060703, by rcnjko. +// +typedef enum _RT_CUSTOMER_ID +{ + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_CHINA_MOBILE = 15, + RT_CID_819x_ALPHA = 16, + RT_CID_819x_Sitecom = 17, + RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. + RT_CID_819x_Lenovo = 19, + RT_CID_819x_QMI = 20, + RT_CID_819x_Edimax_Belkin = 21, + RT_CID_819x_Sercomm_Belkin = 22, + RT_CID_819x_CAMEO1 = 23, + RT_CID_819x_MSI = 24, + RT_CID_819x_Acer = 25, + RT_CID_819x_AzWave_ASUS = 26, + RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus + RT_CID_819x_HP = 28, + RT_CID_819x_WNC_COREGA = 29, + RT_CID_819x_Arcadyan_Belkin = 30, + RT_CID_819x_SAMSUNG = 31, + RT_CID_819x_CLEVO = 32, + RT_CID_819x_DELL = 33, + RT_CID_819x_PRONETS = 34, + RT_CID_819x_Edimax_ASUS = 35, + RT_CID_NETGEAR = 36, + RT_CID_PLANEX = 37, + RT_CID_CC_C = 38, +}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; + + +typedef enum _RF_RADIO_PATH{ + RF_PATH_A = 0, //Radio Path A + RF_PATH_B = 1, //Radio Path B + RF_PATH_C = 2, //Radio Path C + RF_PATH_D = 3, //Radio Path D + RF_PATH_MAX //Max RF number 90 support +}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; + + +// Rx smooth factor +#define Rx_Smooth_Factor 20 + +typedef struct _HAL_DATA_TYPE{ + u1Byte temp; +} HAL_DATA_TYPE; + +#define GET_HAL_DATA(pa) (pa->temp2) + +typedef struct _RFD { + u1Byte temp; +} RFD, *PRT_RFD; + +typedef struct _RSSI_STA{ + s4Byte UndecoratedSmoothedPWDB; + s4Byte UndecoratedSmoothedCCK; + s4Byte UndecoratedSmoothedOFDM; + u4Byte OFDM_pkt; + u1Byte CCK_pkt; + u2Byte CCK_sum_power; + u1Byte bsend_rssi; + u8Byte PacketMap; + u1Byte ValidBit; +}RSSI_STA, *PRSSI_STA; + + +/* Define different debug flag for dedicated service modules in debug flag array. */ +// Each module has independt 32 bit debug flag you cnn define the flag as yout require. +typedef enum tag_DBGP_Flag_Type_Definition +{ + FQoS = 0, + FTX = 1, + FRX = 2, + FSEC = 3, + FMGNT = 4, + FMLME = 5, + FRESOURCE = 6, + FBEACON = 7, + FISR = 8, + FPHY = 9, + FMP = 10, + FEEPROM = 11, + FPWR = 12, + FDM = 13, + FDBG_CTRL = 14, + FC2H = 15, + FBT = 16, + FINIT = 17, + FIOCTL = 18, + FSHORT_CUT = 19, + DBGP_TYPE_MAX +}DBGP_FLAG_E; + + +//extern u8Byte GlobalDebugComponents; + +#define RTL8192DE_HWIMG_SUPPORT 0 +#define RTL8192DU_HWIMG_SUPPORT 0 +#define RTL8723U_HWIMG_SUPPORT 0 +#define RTL8723S_HWIMG_SUPPORT 0 + +#define VISTA_USB_RX_REVISE 0 + + +#if 0 +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif + + typedef enum _RF_CONTENT{ + radioa_txt = 0x1000, + radiob_txt = 0x1001, + radioc_txt = 0x1002, + radiod_txt = 0x1003 +} RF_CONTENT; + +/* +#define REG_EDCA_VI_PARAM EDCA_VI_PARA +#define REG_EDCA_VO_PARAM EDCA_VO_PARA +#define REG_EDCA_BE_PARAM EDCA_BE_PARA +#define REG_EDCA_BK_PARAM EDCA_BK_PARA +*/ + +#define bRFRegOffsetMask 0xfffff + +#define odm_ConfigMAC_8192C(...) {} +#define odm_ConfigRF_RadioA_8192C(...) {} +#define odm_ConfigRF_RadioB_8192C(...) {} +#define odm_ConfigBB_PHY_8192C(...) {} +#define odm_ConfigBB_AGC_8192C(...) {} + +#define PlatformStallExecution ODM_StallExecution + +#ifndef WLAN_HAL_INTERNAL_USED +#define REG_ARFR0 ARFR0 +#define REG_ARFR1 ARFR1 +#define REG_ARFR2 ARFR2 +#define REG_ARFR3 ARFR3 + +#define REG_TX_RPT_TIME REG_88E_TXRPT_TIM +#endif //#ifndef WLAN_HAL_INTERNAL_USED + +/*put the line at the end*/ +#include "phydm/phydm_features.h" + + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/halhwimg.h b/package/kernel/rtl8192cd/phydm/halhwimg.h index 108f7150912..4c5c88160dc 100644 --- a/package/kernel/rtl8192cd/phydm/halhwimg.h +++ b/package/kernel/rtl8192cd/phydm/halhwimg.h @@ -1,123 +1,123 @@ -#pragma once -#ifndef __INC_HW_IMG_H -#define __INC_HW_IMG_H - -// -// 2011/03/15 MH Add for different IC HW image file selection. code size consideration. -// -#if RT_PLATFORM == PLATFORM_LINUX - - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 1 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 0 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - - // For 92D - #define RTL8192DE_HWIMG_SUPPORT 1 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 0 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 1 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 0 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - - #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 0 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 1 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - - //For 92D - #define RTL8192DE_HWIMG_SUPPORT 0 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 1 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 1 - #define RTL8723S_HWIMG_SUPPORT 0 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - - #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 0 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 1 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - - //For 92D - #define RTL8192DE_HWIMG_SUPPORT 0 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 1 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 1 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - #endif - -#else // PLATFORM_WINDOWS & MacOSX - -//For 92C -#define RTL8192CE_HWIMG_SUPPORT 1 -#define RTL8192CE_TEST_HWIMG_SUPPORT 1 -#define RTL8192CU_HWIMG_SUPPORT 1 -#define RTL8192CU_TEST_HWIMG_SUPPORT 1 - -// For 92D -#define RTL8192DE_HWIMG_SUPPORT 1 -#define RTL8192DE_TEST_HWIMG_SUPPORT 1 -#define RTL8192DU_HWIMG_SUPPORT 1 -#define RTL8192DU_TEST_HWIMG_SUPPORT 1 - - #if defined(UNDER_CE) - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 1 - - // For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - - #else - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 1 - //#define RTL_8723E_TEST_HWIMG_SUPPORT 1 - #define RTL8723U_HWIMG_SUPPORT 1 - //#define RTL_8723U_TEST_HWIMG_SUPPORT 1 - #define RTL8723S_HWIMG_SUPPORT 1 - //#define RTL_8723S_TEST_HWIMG_SUPPORT 1 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 1 - #define RTL8188EU_HWIMG_SUPPORT 1 - #define RTL8188ES_HWIMG_SUPPORT 1 - #endif - -#endif - -#endif //__INC_HW_IMG_H +#pragma once +#ifndef __INC_HW_IMG_H +#define __INC_HW_IMG_H + +// +// 2011/03/15 MH Add for different IC HW image file selection. code size consideration. +// +#if RT_PLATFORM == PLATFORM_LINUX + + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 0 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + // For 92D + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 0 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + #endif + +#else // PLATFORM_WINDOWS & MacOSX + +//For 92C +#define RTL8192CE_HWIMG_SUPPORT 1 +#define RTL8192CE_TEST_HWIMG_SUPPORT 1 +#define RTL8192CU_HWIMG_SUPPORT 1 +#define RTL8192CU_TEST_HWIMG_SUPPORT 1 + +// For 92D +#define RTL8192DE_HWIMG_SUPPORT 1 +#define RTL8192DE_TEST_HWIMG_SUPPORT 1 +#define RTL8192DU_HWIMG_SUPPORT 1 +#define RTL8192DU_TEST_HWIMG_SUPPORT 1 + + #if defined(UNDER_CE) + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + // For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #else + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + //#define RTL_8723E_TEST_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 1 + //#define RTL_8723U_TEST_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 1 + //#define RTL_8723S_TEST_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 1 + #define RTL8188EU_HWIMG_SUPPORT 1 + #define RTL8188ES_HWIMG_SUPPORT 1 + #endif + +#endif + +#endif //__INC_HW_IMG_H diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_ap.c b/package/kernel/rtl8192cd/phydm/halphyrf_ap.c index f80cce790e8..9b6d1322dd9 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_ap.c +++ b/package/kernel/rtl8192cd/phydm/halphyrf_ap.c @@ -1,2802 +1,2802 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #include "mp_precomp.h" - #include "phydm_precomp.h" - -#ifndef index_mapping_NUM_88E - #define index_mapping_NUM_88E 15 -#endif - -//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - - -void ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if RTL8812A_SUPPORT -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if (IS_HARDWARE_TYPE_8812(pDM_Odm->Adapter)) - if(pDM_Odm->SupportICType==ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); - //else -#endif -#endif - -#if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType== ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - - -#if RTL8188E_SUPPORT - if(pDM_Odm->SupportICType==ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8197F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8197F) - ConfigureTxpowerTrack_8197F(pConfig); -#endif - -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - - -} - -#if (RTL8192E_SUPPORT==1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; - u1Byte ThermalValue_AVG_count = 0; - u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur - s1Byte OFDM_index[2], index ; - u4Byte ThermalValue_AVG = 0, Reg0x18; - u4Byte i = 0, j = 0, rf; - s4Byte value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; - prtl8192cd_priv priv = pDM_Odm->priv; - - rf_mimo_mode = pDM_Odm->RFType; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ThermalValue = (unsigned char)ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - - switch (rf_mimo_mode) { - case MIMO_1T1R: - rf = 1; - break; - case MIMO_2T2R: - rf = 2; - break; - default: - rf = 2; - break; - } - - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); - break; - } - } - - //Query OFDM path B default setting - if (rf_mimo_mode == MIMO_2T2R) { - ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskOFDM_D); - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); - break; - } - } - } - - /* calculate average thermal meter */ - { - priv->pshare->ThermalValue_AVG_88XX[priv->pshare->ThermalValue_AVG_index_88XX] = ThermalValue; - priv->pshare->ThermalValue_AVG_index_88XX++; - if (priv->pshare->ThermalValue_AVG_index_88XX == AVG_THERMAL_NUM_88XX) - priv->pshare->ThermalValue_AVG_index_88XX = 0; - - for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { - if (priv->pshare->ThermalValue_AVG_88XX[i]) { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG_88XX[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); - } - } - - /* Initialize */ - if (!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_IQK = ThermalValue; - priv->pshare->ThermalValue_LCK = ThermalValue; - } - - if (ThermalValue != priv->pshare->ThermalValue) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - - if (is_decrease) { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); - CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); - } - } else { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); - CCK_index = ((CCK_index < 0 )? 0 : CCK_index); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); - } - } - } -#endif //CFG_TRACKING_TABLE_FILE - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); - - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; - X = priv->pshare->RegE94; - Y = priv->pshare->RegE9C; - - if (X != 0) { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); - } else { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); - } - - set_CCK_swing_index(priv, CCK_index); - - if (rf == 2) { - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; - X = priv->pshare->RegEB4; - Y = priv->pshare->RegEBC; - - if (X != 0) { - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D) >> 7) & 0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); - } else { - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); - } - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord))); - - if (delta_IQK > 3) { - priv->pshare->ThermalValue_IQK = ThermalValue; -#ifdef MP_TEST - if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) -#endif - PHY_IQCalibrate_8192E(pDM_Odm,false); - } - - if (delta_LCK > 8) { - RTL_W8(0x522, 0xff); - Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); - delay_ms(1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); - RTL_W8(0x522, 0x0); - priv->pshare->ThermalValue_LCK = ThermalValue; - } - } - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - for (i = 0 ; i < rf ; i++) - priv->pshare->OFDM_index[i] = OFDM_index[i]; - priv->pshare->CCK_index = CCK_index; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); -} -#endif - - - -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ -#if 1 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; - u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; - u4Byte ThermalValue_AVG = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - TXPWRTRACK_CFG c; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/ - pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_A = NULL, deltaSwingTableIdx_TDOWN_CCK_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_B = NULL, deltaSwingTableIdx_TDOWN_CCK_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_C = NULL, deltaSwingTableIdx_TDOWN_CCK_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_D = NULL, deltaSwingTableIdx_TDOWN_CCK_D = NULL; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaAllSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B, - (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_B); - - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ -#ifdef THER_TRIM - if(GET_CHIP_VER(priv) == VERSION_8197F){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Orig ThermalValue=%d, ther_trim_val=%d\n", ThermalValue, priv->pshare->rf_ft_var.ther_trim_val)); - ThermalValue += priv->pshare->rf_ft_var.ther_trim_val; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("After thermal trim, ThermalValue=%d\n", ThermalValue)); - } -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" - , ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); - - /* Initialize */ - if (!pDM_Odm->RFCalibrateInfo.ThermalValue) - pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; - - /* calculate average thermal meter */ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - - if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for (i = 0; i < c.AverageThermalNum; i++) { - if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) {/*Calculate Average ThermalValue after average enough times*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("ThermalValue_AVG=0x%x(%d) ThermalValue_AVG_count = %d\n" - , ThermalValue_AVG, ThermalValue_AVG, ThermalValue_AVG_count)); - - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); - } - - /*4 Calculate delta, delta_LCK, delta_IQK.*/ - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); - is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); - - if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta)); - delta = 29; - } - - - /*4 if necessary, do LCK.*/ - - if (delta_LCK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - if (GET_CHIP_VER(priv) != VERSION_8822B) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - - if (GET_CHIP_VER(priv) != VERSION_8197F) { - if (delta_IQK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - if (c.DoIQK) - (*c.DoIQK)(pDM_Odm, FALSE, 0, 0); - } - } - - if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - /*4 Do Power Tracking*/ - - if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", - ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - if (is_increase) { /*thermal is higher than base*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d deltaSwingTableIdx_TUP_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta], delta, deltaSwingTableIdx_TUP_CCK_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_B[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d deltaSwingTableIdx_TUP_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta], delta, deltaSwingTableIdx_TUP_CCK_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_C[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d deltaSwingTableIdx_TUP_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta], delta, deltaSwingTableIdx_TUP_CCK_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_D[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d deltaSwingTableIdx_TUP_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta], delta, deltaSwingTableIdx_TUP_CCK_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_A[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - } - } - } else { /* thermal is lower than base*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d deltaSwingTableIdx_TDOWN_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta], delta, deltaSwingTableIdx_TDOWN_CCK_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_B[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d deltaSwingTableIdx_TDOWN_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta], delta, deltaSwingTableIdx_TDOWN_CCK_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_C[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d deltaSwingTableIdx_TDOWN_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta], delta, deltaSwingTableIdx_TDOWN_CCK_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_D[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d deltaSwingTableIdx_TDOWN_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta], delta, deltaSwingTableIdx_TDOWN_CCK_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_A[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - } - } - } - - if (is_increase) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); - if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); - } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); - if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); - } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } - } -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__)); - /*update thermal meter value*/ - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } - -#endif -} -#endif - -/*#if (RTL8814A_SUPPORT == 1)*/ -#if (RTL8814A_SUPPORT == 1) - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; - u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; - u4Byte ThermalValue_AVG = 0, Reg0x18; - u4Byte BBSwingReg[4] = {rA_TxScale_Jaguar,rB_TxScale_Jaguar,rC_TxScale_Jaguar2,rD_TxScale_Jaguar2}; - s4Byte ele_D; - u4Byte BBswingIdx; - prtl8192cd_priv priv = pDM_Odm->priv; - TXPWRTRACK_CFG c; - BOOLEAN bTSSIenable = FALSE; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; - //for 8814 add by Yu Chen - pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ConfigureTxpowerTrack(pDM_Odm, &c); - pRFCalibrateInfo->DefaultOfdmIndex = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); - - if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D); - - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - - /* Initialize */ - if (!pDM_Odm->RFCalibrateInfo.ThermalValue) { - pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; - } - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) { - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; - } - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) { - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; - } - - bTSSIenable = (BOOLEAN)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, rRF_TxGainOffset, BIT7); // check TSSI enable - - //4 Query OFDM BB swing default setting Bit[31:21] - for(p = ODM_RF_PATH_A ; p < c.RfPathCount ; p++) - { - ele_D = ODM_GetBBReg(pDM_Odm, BBSwingReg[p], 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("0x%x:0x%x ([31:21] = 0x%x)\n", BBSwingReg[p], ODM_GetBBReg(pDM_Odm, BBSwingReg[p], bMaskDWord), ele_D)); - - for (BBswingIdx = 0; BBswingIdx < TXSCALE_TABLE_SIZE; BBswingIdx++) {//4 - if (ele_D == TxScalingTable_Jaguar[BBswingIdx]) { - pDM_Odm->RFCalibrateInfo.OFDM_index[p] = (u1Byte)BBswingIdx; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("OFDM_index[%d]=%d\n",p, pDM_Odm->RFCalibrateInfo.OFDM_index[p])); - break; - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("KfreeOffset[%d]=%d\n",p, pRFCalibrateInfo->KfreeOffset[p])); - - } - - /* calculate average thermal meter */ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) - { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", ThermalValue, priv->pmib->dot11RFEntry.ther)); - } - - //4 Calculate delta, delta_LCK, delta_IQK. - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); - is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); - - //4 if necessary, do LCK. - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { - if (delta_LCK > c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - #if (RTL8814A_SUPPORT != 1) - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - #endif - } - } - - if (delta_IQK > c.Threshold_IQK) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - if(c.DoIQK) - (*c.DoIQK)(pDM_Odm, TRUE, 0, 0); - } - - if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - //4 Do Power Tracking - - if(bTSSIenable == TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter PURE TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - else if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) - { - if (is_increase) // thermal is higher than base - { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - { - switch(p) - { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - } - else // thermal is lower than base - { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - { - switch(p) - { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - } - - if (is_increase) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> \n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power --->\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); - //update thermal meter value - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } -} -#endif - -#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - unsigned char ThermalValue = 0, delta, delta_LCK, channel, is_decrease; - unsigned char ThermalValue_AVG_count = 0; - unsigned int ThermalValue_AVG = 0, Reg0x18; - unsigned int BBSwingReg[4]={0xc1c,0xe1c,0x181c,0x1a1c}; - int ele_D, value32; - char OFDM_index[2], index; - unsigned int i = 0, j = 0, rf_path, max_rf_path =2 ,rf; - prtl8192cd_priv priv = pDM_Odm->priv; - unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic - - - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - -#if RTL8881A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8881A) { - max_rf_path = 1; - if ((get_bonding_type_8881A() == BOND_8881AM ||get_bonding_type_8881A() == BOND_8881AN) - && priv->pshare->rf_ft_var.use_intpa8881A && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) - OFDM_min_index = 6; // intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phyBandSelect == PHY_BAND_2G)) - else - OFDM_min_index = 10; //OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic - } -#endif - - - ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - - //4 Query OFDM BB swing default setting Bit[31:21] - for(rf_path = 0 ; rf_path < max_rf_path ; rf_path++){ - ele_D = PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0x%x:0x%x ([31:21] = 0x%x)\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[rf_path] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[%d]=%d\n",rf_path, OFDM_index[rf_path])); - break; - } - } - } -#if 0 - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xc1c:0x%x ([31:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xc1c, bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[0]=%d\n", OFDM_index[0])); - break; - } - } - //Query OFDM path B default setting - if (rf == 2) { - ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xe1c:0x%x ([32:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xe1c, bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[1]=%d\n", OFDM_index[1])); - break; - } - } - } -#endif - /* Initialize */ - if (!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_LCK = ThermalValue; - } - - /* calculate average thermal meter */ - { - priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; - priv->pshare->ThermalValue_AVG_index_8812++; - if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) - priv->pshare->ThermalValue_AVG_index_8812 = 0; - - for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { - if (priv->pshare->ThermalValue_AVG_8812[i]) { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); - } - } - - - //4 If necessary, do power tracking - - if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - if (ThermalValue != priv->pshare->ThermalValue) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - //if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - for (rf_path = 0; rf_path < max_rf_path; rf_path++) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); - if (is_decrease) { - OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); - OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); -#if 0// RTL8881A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8881A){ - if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ - if(priv->pshare->AddTxAGC){//TxAGC has been added - AddTxPower88XX_AC(priv,0); - priv->pshare->AddTxAGC = 0; - priv->pshare->AddTxAGC_index = 0; - } - } - } -#endif - } else { - - OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); -#if 0// RTL8881A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8881A){ - if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ - if(OFDM_index[i] < OFDM_min_index){ - priv->pshare->AddTxAGC_index = (OFDM_min_index - OFDM_index[i])/2; // Calculate Remnant TxAGC Value, 2 index for 1 TxAGC - AddTxPower88XX_AC(priv,priv->pshare->AddTxAGC_index); - priv->pshare->AddTxAGC = 1; //AddTxAGC Flag = 1 - OFDM_index[i] = OFDM_min_index; - } - else{ - if(priv->pshare->AddTxAGC){// TxAGC been added - priv->pshare->AddTxAGC = 0; - priv->pshare->AddTxAGC_index = 0; - AddTxPower88XX_AC(priv,0); //minus the added TPI - } - } - } - } -#else - OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); - } - } - } -#endif - //4 Set new BB swing index - for (rf_path = 0; rf_path < max_rf_path; rf_path++) { - PHY_SetBBReg(priv, BBSwingReg[rf_path], 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[rf_path]]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000), OFDM_index[rf_path])); - } - - } - if (delta_LCK > 8) { - RTL_W8(0x522, 0xff); - Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); - delay_ms(200); // frequency deviation - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); - #ifdef CONFIG_RTL_8812_SUPPORT - if (GET_CHIP_VER(priv)== VERSION_8812E) - UpdateBBRFVal8812(priv, priv->pmib->dot11RFEntry.dot11channel); - #endif - RTL_W8(0x522, 0x0); - priv->pshare->ThermalValue_LCK = ThermalValue; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - for (rf_path = 0; rf_path < max_rf_path; rf_path++) - priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; - } -} - -#endif - - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F || pDM_Odm->SupportICType == ODM_RTL8822B) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(pDM_Odm); - return; - } -#endif -#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(pDM_Odm); - return; - } -#endif -#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8812 || pDM_Odm->SupportICType & ODM_RTL8881A) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(pDM_Odm); - return; - } -#endif - -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType==ODM_RTL8192E) { - ODM_TXPowerTrackingCallback_ThermalMeter_92E(pDM_Odm); - return; - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; -#endif - - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0; -// s4Byte ele_A=0, ele_D, TempCCk, X, value32; -// s4Byte Y, ele_C=0; -// s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; -// s1Byte deltaPowerIndex = 0; - u4Byte i = 0;//, j = 0; - BOOLEAN is2T = FALSE; -// BOOLEAN bInteralPA = FALSE; - - u1Byte OFDM_max_index = 34, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ - enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - TXPWRTRACK_CFG c; - - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = { - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} - {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,1,2,3,4,4,4,4,5,7,8,9,9,10} - }; - u1Byte thermalThreshold[2][index_mapping_NUM_88E]={ - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} - {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} - }; - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; -#endif - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; - -#if (MP_DRIVER == 1) - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. - // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. - pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) - if ((OPMODE & WIFI_MP_STATE) || pDM_Odm->priv->pshare->rf_ft_var.mp_specific) { - if(pDM_Odm->priv->pshare->mp_txpwr_tracking == FALSE) - return; - } -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase)); -/* - if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, BIT17 | BIT16, 0x3); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - } -*/ - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) -#else - if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) -#endif - return; - - //4 3. Initialize ThermalValues of RFCalibrateInfo - - if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) - { - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - } - - if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - } - - //4 4. Calculate average thermal meter - - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) - { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) - { - // Give the new thermo value a weighting - ThermalValue_AVG += (ThermalValue*4); - - ThermalValue = (u1Byte)(ThermalValue_AVG / (ThermalValue_AVG_count+4)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); - - //4 6. If necessary, do LCK. - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { - /*if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))*/ - if (delta_LCK >= c.Threshold_IQK) { - /*Delta temperature is equal to or larger than 20 centigrade.*/ - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - - //3 7. If necessary, move the index of swing table to adjust Tx power. - - if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - - - //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = deltaSwingTableIdx[POWER_INC][offset]; - - } else { - - CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = (-1)*deltaSwingTableIdx[POWER_DEC][offset]; - } - - if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast) - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - else - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast; - - for(i = 0; i < rf; i++) - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pRFCalibrateInfo->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; - pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; - - pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A] = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A]; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); - - //4 7.1 Handle boundary conditions of index. - - - for(i = 0; i < rf; i++) - { - if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_max_index) - { - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_max_index; - } - else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < 0) - { - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = 0; - } - } - - if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1) - pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1; - else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) - pDM_Odm->RFCalibrateInfo.CCK_index = 0; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase)); - - if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) - { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - // ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); - } - else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - // ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TXAGC, 0, 0); - } - else - { - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); - if(is2T) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; - pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A]; - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) - if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); - - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - -VOID -phy_PathAStandBy( - IN PADAPTER pAdapter - ) -{ - RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); - - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x0); - PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -//1 7. IQK -//#define MAX_TOLERANCE 5 -//#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8192C( - IN PADAPTER pAdapter, - IN BOOLEAN configPathB - ) -{ - - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); - - //path-A IQK setting - RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); - if(pAdapter->interfaceIndex == 0) - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - } - else - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); - } - - PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); - - PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : - IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); - - //path-B IQK setting - if(configPathB) - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); - PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); - } - - //LO calibration setting - RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); - - //One shot, path A LOK & IQK - RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); - PlatformStallExecution(IQK_DELAY_TIME*1000); - - // Check failed - regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); - regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); - regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); - regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8192C( - IN PADAPTER pAdapter - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; - RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); - PlatformStallExecution(IQK_DELAY_TIME*1000); - - // Check failed - regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); - regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); - regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); - regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID -phy_PathAFillIQKMatrix( - IN PADAPTER pAdapter, - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - //path B IQK result + 3 - if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G) - Y += 3; - - TX0_C = (Y * Oldval_0) >> 8; - RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -phy_PathBFillIQKMatrix( - IN PADAPTER pAdapter, - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - if(pHalData->CurrentBandType == BAND_ON_5G) - Y += 3; //temp modify for preformance - TX1_C = (Y * Oldval_1) >> 8; - RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - - -BOOLEAN -phy_SimularityCompare_92C( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); - - if(is2T) - bound = 8; - else - bound = 4; - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1< do IQK again -*/ -BOOLEAN -phy_SimularityCompare( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - return phy_SimularityCompare_92C(pAdapter, result, c1, c2); - -} - -VOID -phy_IQCalibrate_8192C( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte t, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u4Byte i; - u1Byte PathAOK, PathBOK; - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting - }; - - u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, - /*rFPGA0_RFMOD*/ rCCK0_AFESetting, rFPGA0_AnalogParameter4, - rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 - }; -#if MP_DRIVER - const u4Byte retryCount = 9; -#else - const u4Byte retryCount = 2; -#endif - //Neil Chen--2011--05--19-- - //3 Path Div - u1Byte rfPathSwitch=0x0; - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - u4Byte bbvalue; - - if(t==0) - { - //bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); - // RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); - - RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - - // Save ADDA parameters, turn Path A ADDA on - phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); - phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); - } - - phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); - - if(t==0) - { - pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pHalData->bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. - phy_PIModeSwitch(pAdapter, TRUE); - } - - //MAC settings - phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - - //PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); - PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord))) ); - PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - } - - if(is2T) - { - PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - { - //Page B init - PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); - - if(is2T) - { - PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); - } - } - // IQ calibration setting - RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); - PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); - - for(i = 0 ; i < retryCount ; i++){ - PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); - if(PathAOK == 0x03){ - RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); - result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathAOK){ - RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); - } - - if(is2T){ - phy_PathAStandBy(pAdapter); - - // Turn Path B ADDA on - phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); - - for(i = 0 ; i < retryCount ; i++){ - PathBOK = phy_PathB_IQK_8192C(pAdapter); - if(PathBOK == 0x03){ - RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { - RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ - RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - - if(t!=0) - { - if(!pHalData->bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. - phy_PIModeSwitch(pAdapter, FALSE); - } - - // Reload ADDA power saving parameters - phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - - // Reload BB parameters - phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); - - /*Restore RX initial gain*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if (is2T) - PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - //load 0xe30 IQC default value - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); - -} - - -VOID -phy_LCCalibrate92C( - IN PADAPTER pAdapter, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //Check continuous TX and Packet TX - tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A - RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); - - //2. Set RF mode = standby mode - //Path-A - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 - LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); - - //4. Set LC calibration begin bit15 - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - delay_ms(100); - - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); - } -} - - -VOID -phy_LCCalibrate( - IN PADAPTER pAdapter, - IN BOOLEAN is2T - ) -{ - phy_LCCalibrate92C(pAdapter, is2T); -} - - - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8192C( - IN PADAPTER pAdapter, - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, i, apkbound; - u1Byte path, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; -#if 0 - u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { - {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, - {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} - }; -#endif - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; -#endif - - RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); - RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); - } - - //save MAC default value - phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - for(path = 0; path < pathbound; path++) - { - - - if(path == RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - } - else if(path == RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); - } - - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); - - //MAC settings - phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); - - if(path == RF_PATH_A) //Path B to standby mode - { - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); - } - else //Path A to standby mode - { - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pHalData->bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - -#if DEV_BUS_TYPE==RT_PCI_INTERFACE - if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) - PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); - else -#endif - PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); - PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); - PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); - - // PA11+PAD01111, one shot - i = 0; - do - { - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x800000); - { - PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); - delay_ms(3); - PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); - - delay_ms(20); - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - - if(path == RF_PATH_A) - tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); - else - tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value - phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value - phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); - if(path == RF_PATH_B) - { - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - RTPRINT(FINIT, INIT_IQK, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == RF_PATH_A) - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); - - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); - } - - pHalData->bAPKdone = TRUE; - - RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); -} - - -VOID -PHY_IQCalibrate_8192C( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - -#if MP_DRIVER == 1 - bStartContTx = pAdapter->MptCtx.bStartContTx; - bSingleTone = pAdapter->MptCtx.bSingleTone; - bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; -#endif - - //ignore IQK when continuous Tx - if(bStartContTx || bSingleTone || bCarrierSuppression) - return; - -#ifdef DISABLE_BB_RF - return; -#endif - if(pAdapter->bSlaveOfDMSP) - return; - - if (bReCovery) - { - phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); - return; - - } - - RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - AcquireCCKAndRWPageAControl(pAdapter); - /*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/ - for (i=0; i<3; i++) - { - /*For 88C 1T1R*/ - phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); - - if(i == 1) - { - is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); - if(is12simular) - { - final_candidate = 0; - break; - } - } - - if(i == 2) - { - is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); - if(is13simular) - { - final_candidate = 0; - break; - } - - is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); - if(is23simular) - final_candidate = 1; - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - ReleaseCCKAndRWPageAControl(pAdapter); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pHalData->RegE94 = RegE94 = result[final_candidate][0]; - pHalData->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; - pHalData->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); - RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value - RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - { - if(pHalData->CurrentBandType == BAND_ON_5G) - phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - else - phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - - } - - if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) - { - if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) - { - if(pHalData->CurrentBandType == BAND_ON_5G) - phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - else - phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - } - } - - phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); - -} - - -VOID -PHY_LCCalibrate_8192C( - IN PADAPTER pAdapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; - PMGNT_INFO pMgntInfoBuddyAdapter; - u4Byte timeout = 2000, timecount = 0; - PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; - -#if MP_DRIVER == 1 - bStartContTx = pAdapter->MptCtx.bStartContTx; - bSingleTone = pAdapter->MptCtx.bSingleTone; - bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; -#endif - -#ifdef DISABLE_BB_RF - return; -#endif - - //ignore LCK when continuous Tx - if(bStartContTx || bSingleTone || bCarrierSuppression) - return; - - if(BuddyAdapter != NULL && - ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType == BAND_ON_2_4G) || - (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G))) - { - pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; - while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) - { - delay_ms(50); - timecount += 50; - } - } - - while(pMgntInfo->bScanInProgress && timecount < timeout) - { - delay_ms(50); - timecount += 50; - } - - pHalData->bLCKInProgress = TRUE; - - RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType, timecount)); - - //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) - if(IS_2T2R(pHalData->VersionID)) - { - phy_LCCalibrate(pAdapter, TRUE); - } - else{ - // For 88C 1T1R - phy_LCCalibrate(pAdapter, FALSE); - } - - pHalData->bLCKInProgress = FALSE; - - RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); - - -} - -VOID -PHY_APCalibrate_8192C( - IN PADAPTER pAdapter, - IN s1Byte delta - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 - return; - -#ifdef DISABLE_BB_RF - return; -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pHalData->bAPKdone) -#endif - return; - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8192C(pAdapter, delta, TRUE); - } - else{ - // For 88C 1T1R - phy_APCalibrate_8192C(pAdapter, delta, FALSE); - } -} - - -#endif - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -) -{ - return; -} -#if 1//!(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - - - - if (pDM_Odm->bLinked) { - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - - #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - PHY_IQCalibrate_8814A(pDM_Odm, FALSE); - #endif - - #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - PHY_IQCalibrate_8822B(pDM_Odm, FALSE); - #endif - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - PHY_IQCalibrate_8821C(pDM_Odm, FALSE); - #endif - - #if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); - #endif - - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - phy_IQCalibrate_8812A(pDM_Odm, FALSE); - #endif - } - } else - pDM_Odm->LinkedInterval = 0; - -} - -void phydm_rf_init(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #include "mp_precomp.h" + #include "phydm_precomp.h" + +#ifndef index_mapping_NUM_88E + #define index_mapping_NUM_88E 15 +#endif + +//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if RTL8812A_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if (IS_HARDWARE_TYPE_8812(pDM_Odm->Adapter)) + if(pDM_Odm->SupportICType==ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); + //else +#endif +#endif + +#if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType== ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + + +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif + +#if RTL8197F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8197F) + ConfigureTxpowerTrack_8197F(pConfig); +#endif + +#if RTL8822B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8822B) + ConfigureTxpowerTrack_8822B(pConfig); +#endif + + +} + +#if (RTL8192E_SUPPORT==1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ThermalValue = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; + u1Byte ThermalValue_AVG_count = 0; + u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur + s1Byte OFDM_index[2], index ; + u4Byte ThermalValue_AVG = 0, Reg0x18; + u4Byte i = 0, j = 0, rf; + s4Byte value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; + prtl8192cd_priv priv = pDM_Odm->priv; + + rf_mimo_mode = pDM_Odm->RFType; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ThermalValue = (unsigned char)ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + + switch (rf_mimo_mode) { + case MIMO_1T1R: + rf = 1; + break; + case MIMO_2T2R: + rf = 2; + break; + default: + rf = 2; + break; + } + + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); + break; + } + } + + //Query OFDM path B default setting + if (rf_mimo_mode == MIMO_2T2R) { + ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); + break; + } + } + } + + /* calculate average thermal meter */ + { + priv->pshare->ThermalValue_AVG_88XX[priv->pshare->ThermalValue_AVG_index_88XX] = ThermalValue; + priv->pshare->ThermalValue_AVG_index_88XX++; + if (priv->pshare->ThermalValue_AVG_index_88XX == AVG_THERMAL_NUM_88XX) + priv->pshare->ThermalValue_AVG_index_88XX = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { + if (priv->pshare->ThermalValue_AVG_88XX[i]) { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG_88XX[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); + } + } + + /* Initialize */ + if (!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_IQK = ThermalValue; + priv->pshare->ThermalValue_LCK = ThermalValue; + } + + if (ThermalValue != priv->pshare->ThermalValue) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index < 0 )? 0 : CCK_index); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } + } +#endif //CFG_TRACKING_TABLE_FILE + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; + X = priv->pshare->RegE94; + Y = priv->pshare->RegE9C; + + if (X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); + } else { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); + } + + set_CCK_swing_index(priv, CCK_index); + + if (rf == 2) { + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; + X = priv->pshare->RegEB4; + Y = priv->pshare->RegEBC; + + if (X != 0) { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); + } else { + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); + } + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord))); + + if (delta_IQK > 3) { + priv->pshare->ThermalValue_IQK = ThermalValue; +#ifdef MP_TEST + if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) +#endif + PHY_IQCalibrate_8192E(pDM_Odm,false); + } + + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); + RTL_W8(0x522, 0x0); + priv->pshare->ThermalValue_LCK = ThermalValue; + } + } + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + for (i = 0 ; i < rf ; i++) + priv->pshare->OFDM_index[i] = OFDM_index[i]; + priv->pshare->CCK_index = CCK_index; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); +} +#endif + + + +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ +#if 1 + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; + u4Byte ThermalValue_AVG = 0; + prtl8192cd_priv priv = pDM_Odm->priv; + TXPWRTRACK_CFG c; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/ + pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; + pu1Byte deltaSwingTableIdx_TUP_CCK_A = NULL, deltaSwingTableIdx_TDOWN_CCK_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_CCK_B = NULL, deltaSwingTableIdx_TDOWN_CCK_B = NULL; + /*for 8814 add by Yu Chen*/ + pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; + pu1Byte deltaSwingTableIdx_TUP_CCK_C = NULL, deltaSwingTableIdx_TDOWN_CCK_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_CCK_D = NULL, deltaSwingTableIdx_TDOWN_CCK_D = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ConfigureTxpowerTrack(pDM_Odm, &c); + + (*c.GetDeltaAllSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B, + (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_A, + (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_B); + + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ +#ifdef THER_TRIM + if(GET_CHIP_VER(priv) == VERSION_8197F){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Orig ThermalValue=%d, ther_trim_val=%d\n", ThermalValue, priv->pshare->rf_ft_var.ther_trim_val)); + ThermalValue += priv->pshare->rf_ft_var.ther_trim_val; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("After thermal trim, ThermalValue=%d\n", ThermalValue)); + } +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" + , ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + + /* Initialize */ + if (!pDM_Odm->RFCalibrateInfo.ThermalValue) + pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; + + /* calculate average thermal meter */ + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + + if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for (i = 0; i < c.AverageThermalNum; i++) { + if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) {/*Calculate Average ThermalValue after average enough times*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("ThermalValue_AVG=0x%x(%d) ThermalValue_AVG_count = %d\n" + , ThermalValue_AVG, ThermalValue_AVG, ThermalValue_AVG_count)); + + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + } + + /*4 Calculate delta, delta_LCK, delta_IQK.*/ + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); + delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); + is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta)); + delta = 29; + } + + + /*4 if necessary, do LCK.*/ + + if (delta_LCK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + if (GET_CHIP_VER(priv) != VERSION_8822B) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + + if (GET_CHIP_VER(priv) != VERSION_8197F) { + if (delta_IQK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + if (c.DoIQK) + (*c.DoIQK)(pDM_Odm, FALSE, 0, 0); + } + } + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + /*4 Do Power Tracking*/ + + if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", + ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_increase) { /*thermal is higher than base*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d deltaSwingTableIdx_TUP_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta], delta, deltaSwingTableIdx_TUP_CCK_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_B[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d deltaSwingTableIdx_TUP_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta], delta, deltaSwingTableIdx_TUP_CCK_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_C[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d deltaSwingTableIdx_TUP_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta], delta, deltaSwingTableIdx_TUP_CCK_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_D[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d deltaSwingTableIdx_TUP_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta], delta, deltaSwingTableIdx_TUP_CCK_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_A[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + } + } + } else { /* thermal is lower than base*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d deltaSwingTableIdx_TDOWN_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta], delta, deltaSwingTableIdx_TDOWN_CCK_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_B[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d deltaSwingTableIdx_TDOWN_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta], delta, deltaSwingTableIdx_TDOWN_CCK_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_C[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d deltaSwingTableIdx_TDOWN_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta], delta, deltaSwingTableIdx_TDOWN_CCK_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_D[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d deltaSwingTableIdx_TDOWN_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta], delta, deltaSwingTableIdx_TDOWN_CCK_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; + pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_A[delta]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); + break; + } + } + } + + if (is_increase) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + } + } +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__)); + /*update thermal meter value*/ + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + + } + +#endif +} +#endif + +/*#if (RTL8814A_SUPPORT == 1)*/ +#if (RTL8814A_SUPPORT == 1) + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; + u4Byte ThermalValue_AVG = 0, Reg0x18; + u4Byte BBSwingReg[4] = {rA_TxScale_Jaguar,rB_TxScale_Jaguar,rC_TxScale_Jaguar2,rD_TxScale_Jaguar2}; + s4Byte ele_D; + u4Byte BBswingIdx; + prtl8192cd_priv priv = pDM_Odm->priv; + TXPWRTRACK_CFG c; + BOOLEAN bTSSIenable = FALSE; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; + //for 8814 add by Yu Chen + pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ConfigureTxpowerTrack(pDM_Odm, &c); + pRFCalibrateInfo->DefaultOfdmIndex = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); + + if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D); + + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); + + /* Initialize */ + if (!pDM_Odm->RFCalibrateInfo.ThermalValue) { + pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; + } + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) { + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; + } + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) { + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; + } + + bTSSIenable = (BOOLEAN)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, rRF_TxGainOffset, BIT7); // check TSSI enable + + //4 Query OFDM BB swing default setting Bit[31:21] + for(p = ODM_RF_PATH_A ; p < c.RfPathCount ; p++) + { + ele_D = ODM_GetBBReg(pDM_Odm, BBSwingReg[p], 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("0x%x:0x%x ([31:21] = 0x%x)\n", BBSwingReg[p], ODM_GetBBReg(pDM_Odm, BBSwingReg[p], bMaskDWord), ele_D)); + + for (BBswingIdx = 0; BBswingIdx < TXSCALE_TABLE_SIZE; BBswingIdx++) {//4 + if (ele_D == TxScalingTable_Jaguar[BBswingIdx]) { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = (u1Byte)BBswingIdx; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("OFDM_index[%d]=%d\n",p, pDM_Odm->RFCalibrateInfo.OFDM_index[p])); + break; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("KfreeOffset[%d]=%d\n",p, pRFCalibrateInfo->KfreeOffset[p])); + + } + + /* calculate average thermal meter */ + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", ThermalValue, priv->pmib->dot11RFEntry.ther)); + } + + //4 Calculate delta, delta_LCK, delta_IQK. + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); + delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); + is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + //4 if necessary, do LCK. + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + if (delta_LCK > c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + + /*Use RTLCK, so close power tracking driver LCK*/ + #if (RTL8814A_SUPPORT != 1) + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + #endif + } + } + + if (delta_IQK > c.Threshold_IQK) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + if(c.DoIQK) + (*c.DoIQK)(pDM_Odm, TRUE, 0, 0); + } + + if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + //4 Do Power Tracking + + if(bTSSIenable == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter PURE TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); + } + else if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) + { + if (is_increase) // thermal is higher than base + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } + else // thermal is lower than base + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } + + if (is_increase) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> \n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power --->\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); + //update thermal meter value + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + + } +} +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + unsigned char ThermalValue = 0, delta, delta_LCK, channel, is_decrease; + unsigned char ThermalValue_AVG_count = 0; + unsigned int ThermalValue_AVG = 0, Reg0x18; + unsigned int BBSwingReg[4]={0xc1c,0xe1c,0x181c,0x1a1c}; + int ele_D, value32; + char OFDM_index[2], index; + unsigned int i = 0, j = 0, rf_path, max_rf_path =2 ,rf; + prtl8192cd_priv priv = pDM_Odm->priv; + unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic + + + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + +#if RTL8881A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8881A) { + max_rf_path = 1; + if ((get_bonding_type_8881A() == BOND_8881AM ||get_bonding_type_8881A() == BOND_8881AN) + && priv->pshare->rf_ft_var.use_intpa8881A && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) + OFDM_min_index = 6; // intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phyBandSelect == PHY_BAND_2G)) + else + OFDM_min_index = 10; //OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic + } +#endif + + + ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + + //4 Query OFDM BB swing default setting Bit[31:21] + for(rf_path = 0 ; rf_path < max_rf_path ; rf_path++){ + ele_D = PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0x%x:0x%x ([31:21] = 0x%x)\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[rf_path] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[%d]=%d\n",rf_path, OFDM_index[rf_path])); + break; + } + } + } +#if 0 + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xc1c:0x%x ([31:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xc1c, bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[0]=%d\n", OFDM_index[0])); + break; + } + } + //Query OFDM path B default setting + if (rf == 2) { + ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xe1c:0x%x ([32:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xe1c, bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[1]=%d\n", OFDM_index[1])); + break; + } + } + } +#endif + /* Initialize */ + if (!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_LCK = ThermalValue; + } + + /* calculate average thermal meter */ + { + priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; + priv->pshare->ThermalValue_AVG_index_8812++; + if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) + priv->pshare->ThermalValue_AVG_index_8812 = 0; + + for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { + if (priv->pshare->ThermalValue_AVG_8812[i]) { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); + } + } + + + //4 If necessary, do power tracking + + if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + if (ThermalValue != priv->pshare->ThermalValue) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + //if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + if (is_decrease) { + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); + OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); +#if 0// RTL8881A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8881A){ + if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ + if(priv->pshare->AddTxAGC){//TxAGC has been added + AddTxPower88XX_AC(priv,0); + priv->pshare->AddTxAGC = 0; + priv->pshare->AddTxAGC_index = 0; + } + } + } +#endif + } else { + + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); +#if 0// RTL8881A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8881A){ + if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ + if(OFDM_index[i] < OFDM_min_index){ + priv->pshare->AddTxAGC_index = (OFDM_min_index - OFDM_index[i])/2; // Calculate Remnant TxAGC Value, 2 index for 1 TxAGC + AddTxPower88XX_AC(priv,priv->pshare->AddTxAGC_index); + priv->pshare->AddTxAGC = 1; //AddTxAGC Flag = 1 + OFDM_index[i] = OFDM_min_index; + } + else{ + if(priv->pshare->AddTxAGC){// TxAGC been added + priv->pshare->AddTxAGC = 0; + priv->pshare->AddTxAGC_index = 0; + AddTxPower88XX_AC(priv,0); //minus the added TPI + } + } + } + } +#else + OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + } + } + } +#endif + //4 Set new BB swing index + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + PHY_SetBBReg(priv, BBSwingReg[rf_path], 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[rf_path]]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000), OFDM_index[rf_path])); + } + + } + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(200); // frequency deviation + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); + #ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv)== VERSION_8812E) + UpdateBBRFVal8812(priv, priv->pmib->dot11RFEntry.dot11channel); + #endif + RTL_W8(0x522, 0x0); + priv->pshare->ThermalValue_LCK = ThermalValue; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + for (rf_path = 0; rf_path < max_rf_path; rf_path++) + priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; + } +} + +#endif + + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F || pDM_Odm->SupportICType == ODM_RTL8822B) { + ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(pDM_Odm); + return; + } +#endif +#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ + if (pDM_Odm->SupportICType & ODM_RTL8814A) { + ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(pDM_Odm); + return; + } +#endif +#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8812 || pDM_Odm->SupportICType & ODM_RTL8881A) { + ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(pDM_Odm); + return; + } +#endif + +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType==ODM_RTL8192E) { + ODM_TXPowerTrackingCallback_ThermalMeter_92E(pDM_Odm); + return; + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; +#endif + + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0; +// s4Byte ele_A=0, ele_D, TempCCk, X, value32; +// s4Byte Y, ele_C=0; +// s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; +// s1Byte deltaPowerIndex = 0; + u4Byte i = 0;//, j = 0; + BOOLEAN is2T = FALSE; +// BOOLEAN bInteralPA = FALSE; + + u1Byte OFDM_max_index = 34, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ + enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + TXPWRTRACK_CFG c; + + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = { + // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,1,2,3,4,4,4,4,5,7,8,9,9,10} + }; + u1Byte thermalThreshold[2][index_mapping_NUM_88E]={ + // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} + }; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; +#endif + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. + // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) + if ((OPMODE & WIFI_MP_STATE) || pDM_Odm->priv->pshare->rf_ft_var.mp_specific) { + if(pDM_Odm->priv->pshare->mp_txpwr_tracking == FALSE) + return; + } +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase)); +/* + if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, BIT17 | BIT16, 0x3); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + } +*/ + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) +#else + if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) +#endif + return; + + //4 3. Initialize ThermalValues of RFCalibrateInfo + + if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) + { + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + } + + if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + } + + //4 4. Calculate average thermal meter + + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) + { + // Give the new thermo value a weighting + ThermalValue_AVG += (ThermalValue*4); + + ThermalValue = (u1Byte)(ThermalValue_AVG / (ThermalValue_AVG_count+4)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); + + //4 6. If necessary, do LCK. + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + /*if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))*/ + if (delta_LCK >= c.Threshold_IQK) { + /*Delta temperature is equal to or larger than 20 centigrade.*/ + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + + //3 7. If necessary, move the index of swing table to adjust Tx power. + + if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + + + //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = deltaSwingTableIdx[POWER_INC][offset]; + + } else { + + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = (-1)*deltaSwingTableIdx[POWER_DEC][offset]; + } + + if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast) + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + else + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast; + + for(i = 0; i < rf; i++) + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pRFCalibrateInfo->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; + pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; + + pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A] = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); + + //4 7.1 Handle boundary conditions of index. + + + for(i = 0; i < rf; i++) + { + if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_max_index) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_max_index; + } + else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < 0) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = 0; + } + } + + if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1) + pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1; + else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) + pDM_Odm->RFCalibrateInfo.CCK_index = 0; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase)); + + if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + // ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } + else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + // ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TXAGC, 0, 0); + } + else + { + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); + if(is2T) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; + pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A]; + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) + if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); + + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + +VOID +phy_PathAStandBy( + IN PADAPTER pAdapter + ) +{ + RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); + + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x0); + PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +//1 7. IQK +//#define MAX_TOLERANCE 5 +//#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN configPathB + ) +{ + + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); + + //path-A IQK setting + RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); + if(pAdapter->interfaceIndex == 0) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + } + else + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); + + PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : + IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); + + //path-B IQK setting + if(configPathB) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); + PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); + } + + //LO calibration setting + RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); + + //One shot, path A LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); + regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); + regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192C( + IN PADAPTER pAdapter + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; + RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); + regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); + regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +phy_PathAFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //path B IQK result + 3 + if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G) + Y += 3; + + TX0_C = (Y * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +phy_PathBFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + if(pHalData->CurrentBandType == BAND_ON_5G) + Y += 3; //temp modify for preformance + TX1_C = (Y * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + + +BOOLEAN +phy_SimularityCompare_92C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); + + if(is2T) + bound = 8; + else + bound = 4; + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1< do IQK again +*/ +BOOLEAN +phy_SimularityCompare( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + return phy_SimularityCompare_92C(pAdapter, result, c1, c2); + +} + +VOID +phy_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting + }; + + u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, + /*rFPGA0_RFMOD*/ rCCK0_AFESetting, rFPGA0_AnalogParameter4, + rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 + }; +#if MP_DRIVER + const u4Byte retryCount = 9; +#else + const u4Byte retryCount = 2; +#endif + //Neil Chen--2011--05--19-- + //3 Path Div + u1Byte rfPathSwitch=0x0; + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + u4Byte bbvalue; + + if(t==0) + { + //bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); + // RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); + + RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + + // Save ADDA parameters, turn Path A ADDA on + phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + } + + phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); + + if(t==0) + { + pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pHalData->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + phy_PIModeSwitch(pAdapter, TRUE); + } + + //MAC settings + phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + //PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); + PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord))) ); + PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + } + + if(is2T) + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + { + //Page B init + PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); + + if(is2T) + { + PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); + } + } + // IQ calibration setting + RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); + PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); + + for(i = 0 ; i < retryCount ; i++){ + PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); + if(PathAOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathAOK){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); + } + + if(is2T){ + phy_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); + + for(i = 0 ; i < retryCount ; i++){ + PathBOK = phy_PathB_IQK_8192C(pAdapter); + if(PathBOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + + if(t!=0) + { + if(!pHalData->bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. + phy_PIModeSwitch(pAdapter, FALSE); + } + + // Reload ADDA power saving parameters + phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + // Reload BB parameters + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + + /*Restore RX initial gain*/ + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if (is2T) + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + //load 0xe30 IQC default value + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); + +} + + +VOID +phy_LCCalibrate92C( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //Check continuous TX and Packet TX + tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); + + //2. Set RF mode = standby mode + //Path-A + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); + + //4. Set LC calibration begin bit15 + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); + } +} + + +VOID +phy_LCCalibrate( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + phy_LCCalibrate92C(pAdapter, is2T); +} + + + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, i, apkbound; + u1Byte path, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; +#if 0 + u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { + {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, + {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} + }; +#endif + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; +#endif + + RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); + RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); + } + + //save MAC default value + phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); + + //MAC settings + phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); + + if(path == RF_PATH_A) //Path B to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); + } + else //Path A to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pHalData->bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); + else +#endif + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); + + // PA11+PAD01111, one shot + i = 0; + do + { + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x800000); + { + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + delay_ms(3); + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + + delay_ms(20); + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + + if(path == RF_PATH_A) + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); + else + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value + phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); + if(path == RF_PATH_B) + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + RTPRINT(FINIT, INIT_IQK, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); + + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); + } + + pHalData->bAPKdone = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); +} + + +VOID +PHY_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + +#if MP_DRIVER == 1 + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +#endif + + //ignore IQK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + +#ifdef DISABLE_BB_RF + return; +#endif + if(pAdapter->bSlaveOfDMSP) + return; + + if (bReCovery) + { + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + return; + + } + + RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + AcquireCCKAndRWPageAControl(pAdapter); + /*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/ + for (i=0; i<3; i++) + { + /*For 88C 1T1R*/ + phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); + + if(i == 1) + { + is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); + if(is12simular) + { + final_candidate = 0; + break; + } + } + + if(i == 2) + { + is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); + if(is13simular) + { + final_candidate = 0; + break; + } + + is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); + if(is23simular) + final_candidate = 1; + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + ReleaseCCKAndRWPageAControl(pAdapter); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pHalData->RegE94 = RegE94 = result[final_candidate][0]; + pHalData->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; + pHalData->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value + RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { + if(pHalData->CurrentBandType == BAND_ON_5G) + phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + else + phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + + } + + if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + if(pHalData->CurrentBandType == BAND_ON_5G) + phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + else + phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } + + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + +} + + +VOID +PHY_LCCalibrate_8192C( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; + PMGNT_INFO pMgntInfoBuddyAdapter; + u4Byte timeout = 2000, timecount = 0; + PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; + +#if MP_DRIVER == 1 + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +#endif + +#ifdef DISABLE_BB_RF + return; +#endif + + //ignore LCK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + + if(BuddyAdapter != NULL && + ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType == BAND_ON_2_4G) || + (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G))) + { + pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; + while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + } + + while(pMgntInfo->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + + pHalData->bLCKInProgress = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType, timecount)); + + //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + if(IS_2T2R(pHalData->VersionID)) + { + phy_LCCalibrate(pAdapter, TRUE); + } + else{ + // For 88C 1T1R + phy_LCCalibrate(pAdapter, FALSE); + } + + pHalData->bLCKInProgress = FALSE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); + + +} + +VOID +PHY_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 + return; + +#ifdef DISABLE_BB_RF + return; +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pHalData->bAPKdone) +#endif + return; + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8192C(pAdapter, delta, TRUE); + } + else{ + // For 88C 1T1R + phy_APCalibrate_8192C(pAdapter, delta, FALSE); + } +} + + +#endif + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +) +{ + return; +} +#if 1//!(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + + + + if (pDM_Odm->bLinked) { + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + + #if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + PHY_IQCalibrate_8814A(pDM_Odm, FALSE); + #endif + + #if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + PHY_IQCalibrate_8822B(pDM_Odm, FALSE); + #endif + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + PHY_IQCalibrate_8821C(pDM_Odm, FALSE); + #endif + + #if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); + #endif + + #if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + phy_IQCalibrate_8812A(pDM_Odm, FALSE); + #endif + } + } else + pDM_Odm->LinkedInterval = 0; + +} + +void phydm_rf_init(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_ap.h b/package/kernel/rtl8192cd/phydm/halphyrf_ap.h index e4813cec273..8281e5548ce 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_ap.h +++ b/package/kernel/rtl8192cd/phydm/halphyrf_ap.h @@ -1,179 +1,179 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_powertracking_ap.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#endif - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8821c.h" -#endif - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE -} PWRTRACK_METHOD; - -typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID (*FuncLCK)(PVOID); - //refine by YuChen for 8814A -typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); - - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncAllSwing GetDeltaAllSwingTable; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#if (RTL8192E_SUPPORT==1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); -#endif - -#if (RTL8814A_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#elif ODM_IC_11AC_SERIES_SUPPORT -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#endif - -#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M ) - - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - - // -// BB/MAC/RF other monitor API -// - -void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, - IN BOOLEAN bEnableMonitorMode ); - -// -// IQ calibrate -// -void -PHY_IQCalibrate_8192C( IN PADAPTER pAdapter, - IN BOOLEAN bReCovery); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8192C( IN PADAPTER pAdapter); - -// -// AP calibrate -// -void -PHY_APCalibrate_8192C( IN PADAPTER pAdapter, - IN s1Byte delta); -#endif - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -void phydm_rf_init(IN PVOID pDM_VOID); -void phydm_rf_watchdog(IN PVOID pDM_VOID); - -#endif // #ifndef __HAL_PHY_RF_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +#include "phydm_powertracking_ap.h" +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8821c.h" +#endif + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); + //refine by YuChen for 8814A +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; + FuncAllSwing GetDeltaAllSwingTable; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#if (RTL8192E_SUPPORT==1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); +#endif + +#if (RTL8814A_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#elif ODM_IC_11AC_SERIES_SUPPORT +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#endif + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M ) + + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + + // +// BB/MAC/RF other monitor API +// + +void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, + IN BOOLEAN bEnableMonitorMode ); + +// +// IQ calibrate +// +void +PHY_IQCalibrate_8192C( IN PADAPTER pAdapter, + IN BOOLEAN bReCovery); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192C( IN PADAPTER pAdapter); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192C( IN PADAPTER pAdapter, + IN s1Byte delta); +#endif + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init(IN PVOID pDM_VOID); +void phydm_rf_watchdog(IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_ce.c b/package/kernel/rtl8192cd/phydm/halphyrf_ce.c index fa931779fed..8b7322ebe33 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_ce.c +++ b/package/kernel/rtl8192cd/phydm/halphyrf_ce.c @@ -1,801 +1,801 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - -void ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if RTL8192E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8192E) - ConfigureTxpowerTrack_8192E(pConfig); -#endif -#if RTL8821A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821) - ConfigureTxpowerTrack_8821A(pConfig); -#endif -#if RTL8812A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); -#endif -#if RTL8188E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ConfigureTxpowerTrack_8723B(pConfig); -#endif - -#if RTL8814A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - -#if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) - ConfigureTxpowerTrack_8703B(pConfig); -#endif - -#if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) - ConfigureTxpowerTrack_8188F(pConfig); -#endif -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) - ConfigureTxpowerTrack_8723D(pConfig); -#endif -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - -} - -//====================================================================== -// <20121113, Kordan> This function should be called when TxAGC changed. -// Otherwise the previous compensation is gone, because we record the -// delta of temperature between two TxPowerTracking watch dogs. -// -// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still -// need to call this function. -//====================================================================== -VOID -ODM_ClearTxPowerTrackingState( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - pDM_Odm->RFCalibrateInfo.CCK_index = 0; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - - pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo - -} - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ) -{ - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; - s1Byte diff_DPK[4] = {0}; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; - - u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) - u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; - u1Byte XtalOffsetEanble = 0; - - TXPWRTRACK_CFG c; - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; - /*for Xtal Offset by James.Tung*/ - ps1Byte deltaSwingTableXtal_UP = NULL; - ps1Byte deltaSwingTableXtal_DOWN = NULL; - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); - - if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ - (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); - - pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ - pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; - - /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; - We should keep updating the control variable according to HalData. - RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->mp_mode == TRUE) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", - pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - - /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); - RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); - RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); - Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); - } - - if (!pRFCalibrateInfo->TxPowerTrackControl) - return; - - - /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ - - if (pRFCalibrateInfo->bReloadtxpowerindex) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - - /*4 4. Calculate average thermal meter*/ - - pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; - pRFCalibrateInfo->ThermalValue_AVG_index++; - if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pRFCalibrateInfo->ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if (pRFCalibrateInfo->ThermalValue_AVG[i]) { - ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - //"delta" here is used to determine whether thermal value changes or not. - delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - - if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; - - /*4 6. If necessary, do LCK.*/ - - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ - if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); - - /* Delta temperature is equal to or larger than 20 centigrade.*/ - if (delta_LCK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - } - - /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - - if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) - { - //"delta" here is used to record the absolute value of differrence. -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - if (delta >= TXPWR_TRACK_TABLE_SIZE) - delta = TXPWR_TRACK_TABLE_SIZE - 1; - - /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } else { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); - - if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - else - pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); - - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; - - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; - - /*************Print BB Swing Base and Index Offset*************/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); - - /*4 7.1 Handle boundary conditions of index.*/ - - if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) - pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; - else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) - pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); - - if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) - pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; - else if (pRFCalibrateInfo->CCK_index <= 0) - pRFCalibrateInfo->CCK_index = 0; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", - pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", - pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", - pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); - } - - if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); - - if (PowerTrackingType == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else if (PowerTrackingType == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); - } else if (PowerTrackingType == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); - } else if (PowerTrackingType == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pRFCalibrateInfo->ThermalValue) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); - - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } - - - if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (!IS_HARDWARE_TYPE_8723B(Adapter)) { - /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ - if (delta_IQK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - if (!pRFCalibrateInfo->bIQKInProgress) - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); - - pRFCalibrateInfo->TXPowercount = 0; -} - - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -) -{ - return; -} -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (IS_HARDWARE_TYPE_8812AU(Adapter)) - return; -#endif - - if (pDM_Odm->bLinked) { - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - #if (RTL8814A_SUPPORT == 1) - PHY_IQCalibrate_8814A(pDM_Odm, FALSE); - #endif - } - - #if (RTL8822B_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8822B(Adapter)) - PHY_IQCalibrate_8822B(pDM_Odm, FALSE); - #endif - - #if (RTL8821C_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821C(Adapter)) - PHY_IQCalibrate_8821C(pDM_Odm, FALSE); - #endif - - #if (RTL8821A_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821(Adapter)) - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); - #endif - } - } else - pDM_Odm->LinkedInterval = 0; -} - -void phydm_rf_init(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if RTL8192E_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8192E) + ConfigureTxpowerTrack_8192E(pConfig); +#endif +#if RTL8821A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8821) + ConfigureTxpowerTrack_8821A(pConfig); +#endif +#if RTL8812A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); +#endif +#if RTL8188E_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif + +#if RTL8723B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723B) + ConfigureTxpowerTrack_8723B(pConfig); +#endif + +#if RTL8814A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + +#if RTL8703B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8703B) + ConfigureTxpowerTrack_8703B(pConfig); +#endif + +#if RTL8188F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188F) + ConfigureTxpowerTrack_8188F(pConfig); +#endif +#if RTL8723D_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723D) + ConfigureTxpowerTrack_8723D(pConfig); +#endif +#if RTL8822B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8822B) + ConfigureTxpowerTrack_8822B(pConfig); +#endif + +} + +//====================================================================== +// <20121113, Kordan> This function should be called when TxAGC changed. +// Otherwise the previous compensation is gone, because we record the +// delta of temperature between two TxPowerTracking watch dogs. +// +// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still +// need to call this function. +//====================================================================== +VOID +ODM_ClearTxPowerTrackingState( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + pDM_Odm->RFCalibrateInfo.CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo + +} + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s1Byte diff_DPK[4] = {0}; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; + + u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) + u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; + u1Byte XtalOffsetEanble = 0; + + TXPWRTRACK_CFG c; + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_B = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; + /*for 8814 add by Yu Chen*/ + pu1Byte deltaSwingTableIdx_TUP_C = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; + /*for Xtal Offset by James.Tung*/ + ps1Byte deltaSwingTableXtal_UP = NULL; + ps1Byte deltaSwingTableXtal_DOWN = NULL; + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); + + if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ + (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); + + pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ + pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; + + /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; + We should keep updating the control variable according to HalData. + RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + pRFCalibrateInfo->RegA24 = 0x090e1317; + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->mp_mode == TRUE) + pRFCalibrateInfo->RegA24 = 0x090e1317; + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", + pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); + RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); + RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); + Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); + } + + if (!pRFCalibrateInfo->TxPowerTrackControl) + return; + + + /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ + + if (pRFCalibrateInfo->bReloadtxpowerindex) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + + /*4 4. Calculate average thermal meter*/ + + pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; + pRFCalibrateInfo->ThermalValue_AVG_index++; + if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ + pRFCalibrateInfo->ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if (pRFCalibrateInfo->ThermalValue_AVG[i]) { + ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + //"delta" here is used to determine whether thermal value changes or not. + delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + + if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ + pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ + if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) + { + //"delta" here is used to record the absolute value of differrence. +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { + /*Save XtalOffset from Xtal table*/ + pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); + pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; + + if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) + XtalOffsetEanble = 0; + else + XtalOffsetEanble = 1; + } + + } else { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ + + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { + /*Save XtalOffset from Xtal table*/ + pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); + pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; + + if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) + XtalOffsetEanble = 0; + else + XtalOffsetEanble = 1; + } + + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); + + if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + else + pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); + + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; + + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; + + /*************Print BB Swing Base and Index Offset*************/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) + pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; + else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) + pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + + if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) + pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; + else if (pRFCalibrateInfo->CCK_index <= 0) + pRFCalibrateInfo->CCK_index = 0; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", + pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", + pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", + pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); + } + + if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); + + if (PowerTrackingType == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } else if (PowerTrackingType == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (PowerTrackingType == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (PowerTrackingType == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); + } + pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ + + } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pRFCalibrateInfo->ThermalValue) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); + + pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ + + } + + + if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { + + if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (!IS_HARDWARE_TYPE_8723B(Adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); + if (!pRFCalibrateInfo->bIQKInProgress) + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); + + pRFCalibrateInfo->TXPowercount = 0; +} + + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + return; +#endif + + if (pDM_Odm->bLinked) { + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + #if (RTL8814A_SUPPORT == 1) + PHY_IQCalibrate_8814A(pDM_Odm, FALSE); + #endif + } + + #if (RTL8822B_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8822B(Adapter)) + PHY_IQCalibrate_8822B(pDM_Odm, FALSE); + #endif + + #if (RTL8821C_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8821C(Adapter)) + PHY_IQCalibrate_8821C(pDM_Odm, FALSE); + #endif + + #if (RTL8821A_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8821(Adapter)) + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); + #endif + } + } else + pDM_Odm->LinkedInterval = 0; +} + +void phydm_rf_init(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_ce.h b/package/kernel/rtl8192cd/phydm/halphyrf_ce.h index 2ed5764a8b9..a0ed5dcac68 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_ce.h +++ b/package/kernel/rtl8192cd/phydm/halphyrf_ce.h @@ -1,118 +1,118 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_kfree.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#endif - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8821c/phydm_iqk_8821c.h" -#endif - -#include "phydm_powertracking_ce.h" - - -typedef enum _SPUR_CAL_METHOD { - PLL_RESET, - AFE_PHASE_SEL -} SPUR_CAL_METHOD; - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE, - MIX_2G_TSSI_5G_MODE, - MIX_5G_TSSI_2G_MODE -} PWRTRACK_METHOD; - -typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID (*FuncLCK)(PVOID); -typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID(*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); -typedef VOID(*FuncSetXtal)(PVOID); - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncSwingXtal GetDeltaSwingXtalTable; - FuncSetXtal ODM_TxXtalTrackSetXtal; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_ClearTxPowerTrackingState( - IN PVOID pDM_VOID - ); - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - - - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -void phydm_rf_init( IN PVOID pDM_VOID); -void phydm_rf_watchdog( IN PVOID pDM_VOID); - -#endif // #ifndef __HAL_PHY_RF_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +#include "phydm_kfree.h" +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) +#include "rtl8821c/phydm_iqk_8821c.h" +#endif + +#include "phydm_powertracking_ce.h" + + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID(*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); +typedef VOID(*FuncSetXtal)(PVOID); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; + FuncSwingXtal GetDeltaSwingXtalTable; + FuncSetXtal ODM_TxXtalTrackSetXtal; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init( IN PVOID pDM_VOID); +void phydm_rf_watchdog( IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_win.c b/package/kernel/rtl8192cd/phydm/halphyrf_win.c index 8f0d9921681..a93860fb95c 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_win.c +++ b/package/kernel/rtl8192cd/phydm/halphyrf_win.c @@ -1,780 +1,780 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - -void ConfigureTxpowerTrack( - IN PDM_ODM_T pDM_Odm, - OUT PTXPWRTRACK_CFG pConfig - ) -{ -#if RTL8192E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8192E) - ConfigureTxpowerTrack_8192E(pConfig); -#endif -#if RTL8821A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821) - ConfigureTxpowerTrack_8821A(pConfig); -#endif -#if RTL8812A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); -#endif -#if RTL8188E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) - ConfigureTxpowerTrack_8188F(pConfig); -#endif - -#if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ConfigureTxpowerTrack_8723B(pConfig); -#endif - -#if RTL8814A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - -#if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) - ConfigureTxpowerTrack_8703B(pConfig); -#endif - -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) - ConfigureTxpowerTrack_8723D(pConfig); -#endif -} - -//====================================================================== -// <20121113, Kordan> This function should be called when TxAGC changed. -// Otherwise the previous compensation is gone, because we record the -// delta of temperature between two TxPowerTracking watch dogs. -// -// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still -// need to call this function. -//====================================================================== -VOID -ODM_ClearTxPowerTrackingState( - IN PDM_ODM_T pDM_Odm - ) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = 0; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - - pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo - -} - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; - s1Byte diff_DPK[4] = {0}; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; - - u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) - u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; - u1Byte XtalOffsetEanble = 0; - - TXPWRTRACK_CFG c; - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; - /*for Xtal Offset by James.Tung*/ - ps1Byte deltaSwingTableXtal_UP = NULL; - ps1Byte deltaSwingTableXtal_DOWN = NULL; - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); - - if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ - (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); - - - pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ - pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; - - /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; - We should keep updating the control variable according to HalData. - RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->mp_mode == TRUE) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", - pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - - /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); - RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); - RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); - Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); - } - - if (!pRFCalibrateInfo->TxPowerTrackControl) - return; - - - /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ - - if (pRFCalibrateInfo->bReloadtxpowerindex) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - - /*4 4. Calculate average thermal meter*/ - - pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; - pRFCalibrateInfo->ThermalValue_AVG_index++; - if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pRFCalibrateInfo->ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if (pRFCalibrateInfo->ThermalValue_AVG[i]) { - ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - //"delta" here is used to determine whether thermal value changes or not. - delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - - if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; - - /*4 6. If necessary, do LCK.*/ - - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ - if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); - - /* Delta temperature is equal to or larger than 20 centigrade.*/ - if (delta_LCK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - } - - /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - - if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) - { - //"delta" here is used to record the absolute value of differrence. -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - if (delta >= TXPWR_TRACK_TABLE_SIZE) - delta = TXPWR_TRACK_TABLE_SIZE - 1; - - /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } else { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); - - if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - else - pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); - - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; - - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; - - /*************Print BB Swing Base and Index Offset*************/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); - - /*4 7.1 Handle boundary conditions of index.*/ - - if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) - pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; - else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) - pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); - - if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) - pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; - else if (pRFCalibrateInfo->CCK_index <= 0) - pRFCalibrateInfo->CCK_index = 0; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", - pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", - pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", - pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); - } - - if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); - - if (PowerTrackingType == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else if (PowerTrackingType == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); - } else if (PowerTrackingType == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); - } else if (PowerTrackingType == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pRFCalibrateInfo->ThermalValue) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || - pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || - pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); - - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } - - - if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (!IS_HARDWARE_TYPE_8723B(Adapter)) { - /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ - if (delta_IQK >= c.Threshold_IQK) { - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - if (!pRFCalibrateInfo->bIQKInProgress) - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); - - pRFCalibrateInfo->TXPowercount = 0; -} - - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PDM_ODM_T pDM_Odm -) -{ - return; -} -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - - if (pDM_Odm->bLinked) { - - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - PHY_IQCalibrate(Adapter, FALSE); - } - } else - pDM_Odm->LinkedInterval = 0; - -} - -void phydm_rf_init(IN PDM_ODM_T pDM_Odm) -{ - - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm) -{ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + +void ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ) +{ +#if RTL8192E_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8192E) + ConfigureTxpowerTrack_8192E(pConfig); +#endif +#if RTL8821A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8821) + ConfigureTxpowerTrack_8821A(pConfig); +#endif +#if RTL8812A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); +#endif +#if RTL8188E_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif + +#if RTL8188F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188F) + ConfigureTxpowerTrack_8188F(pConfig); +#endif + +#if RTL8723B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723B) + ConfigureTxpowerTrack_8723B(pConfig); +#endif + +#if RTL8814A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + +#if RTL8703B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8703B) + ConfigureTxpowerTrack_8703B(pConfig); +#endif + +#if RTL8822B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8822B) + ConfigureTxpowerTrack_8822B(pConfig); +#endif + +#if RTL8723D_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723D) + ConfigureTxpowerTrack_8723D(pConfig); +#endif +} + +//====================================================================== +// <20121113, Kordan> This function should be called when TxAGC changed. +// Otherwise the previous compensation is gone, because we record the +// delta of temperature between two TxPowerTracking watch dogs. +// +// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still +// need to call this function. +//====================================================================== +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo + +} + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#endif + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s1Byte diff_DPK[4] = {0}; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; + + u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) + u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; + u1Byte XtalOffsetEanble = 0; + + TXPWRTRACK_CFG c; + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_B = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; + /*for 8814 add by Yu Chen*/ + pu1Byte deltaSwingTableIdx_TUP_C = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D = NULL; + pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; + /*for Xtal Offset by James.Tung*/ + ps1Byte deltaSwingTableXtal_UP = NULL; + ps1Byte deltaSwingTableXtal_DOWN = NULL; + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); + + if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ + (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); + + + pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ + pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; + + /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; + We should keep updating the control variable according to HalData. + RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + pRFCalibrateInfo->RegA24 = 0x090e1317; + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->mp_mode == TRUE) + pRFCalibrateInfo->RegA24 = 0x090e1317; + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", + pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); + RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); + RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); + Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); + } + + if (!pRFCalibrateInfo->TxPowerTrackControl) + return; + + + /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ + + if (pRFCalibrateInfo->bReloadtxpowerindex) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + + /*4 4. Calculate average thermal meter*/ + + pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; + pRFCalibrateInfo->ThermalValue_AVG_index++; + if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ + pRFCalibrateInfo->ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if (pRFCalibrateInfo->ThermalValue_AVG[i]) { + ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + //"delta" here is used to determine whether thermal value changes or not. + delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + + if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ + pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ + if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) + { + //"delta" here is used to record the absolute value of differrence. +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { + /*Save XtalOffset from Xtal table*/ + pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); + pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; + + if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) + XtalOffsetEanble = 0; + else + XtalOffsetEanble = 1; + } + + } else { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ + + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + + if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { + /*Save XtalOffset from Xtal table*/ + pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); + pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; + + if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) + XtalOffsetEanble = 0; + else + XtalOffsetEanble = 1; + } + + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); + + if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + else + pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); + + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; + + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; + + /*************Print BB Swing Base and Index Offset*************/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) + pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; + else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) + pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + + if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) + pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; + else if (pRFCalibrateInfo->CCK_index <= 0) + pRFCalibrateInfo->CCK_index = 0; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", + pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", + pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", + pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); + } + + if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); + + if (PowerTrackingType == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } else if (PowerTrackingType == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (PowerTrackingType == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (PowerTrackingType == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); + } + pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ + + } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pRFCalibrateInfo->ThermalValue) { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || + pDM_Odm->SupportICType == ODM_RTL8723D) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || + pDM_Odm->SupportICType == ODM_RTL8723D) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); + + pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ + + } + + + if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { + + if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (!IS_HARDWARE_TYPE_8723B(Adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.Threshold_IQK) { + pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); + if (!pRFCalibrateInfo->bIQKInProgress) + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); + + pRFCalibrateInfo->TXPowercount = 0; +} + + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + + if (pDM_Odm->bLinked) { + + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + PHY_IQCalibrate(Adapter, FALSE); + } + } else + pDM_Odm->LinkedInterval = 0; + +} + +void phydm_rf_init(IN PDM_ODM_T pDM_Odm) +{ + + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm) +{ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} diff --git a/package/kernel/rtl8192cd/phydm/halphyrf_win.h b/package/kernel/rtl8192cd/phydm/halphyrf_win.h index bf145920f21..783643b13c5 100644 --- a/package/kernel/rtl8192cd/phydm/halphyrf_win.h +++ b/package/kernel/rtl8192cd/phydm/halphyrf_win.h @@ -1,120 +1,120 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_kfree.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#include "../mac/Halmac_type.h" -#endif -#include "phydm_powertracking_win.h" - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8821c/phydm_iqk_8821c.h" -#endif - -typedef enum _SPUR_CAL_METHOD { - PLL_RESET, - AFE_PHASE_SEL -} SPUR_CAL_METHOD; - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE, - MIX_2G_TSSI_5G_MODE, - MIX_5G_TSSI_2G_MODE -} PWRTRACK_METHOD; - -typedef VOID(*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID(*FuncLCK)(PVOID); -typedef VOID(*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID(*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); -typedef VOID (*FuncSetXtal)(PVOID); -typedef VOID(*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncSwingXtal GetDeltaSwingXtalTable; - FuncSetXtal ODM_TxXtalTrackSetXtal; - FuncAllSwing GetDeltaAllSwingTable; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PDM_ODM_T pDM_Odm, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_ClearTxPowerTrackingState( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ); - - - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PDM_ODM_T pDM_Odm -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm); -VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm); -VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm); - -#endif // #ifndef __HAL_PHY_RF_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +#include "phydm_kfree.h" +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#include "../mac/Halmac_type.h" +#endif +#include "phydm_powertracking_win.h" + +#if (RTL8821C_SUPPORT == 1) +#include "rtl8821c/phydm_iqk_8821c.h" +#endif + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +} PWRTRACK_METHOD; + +typedef VOID(*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID(*FuncLCK)(PVOID); +typedef VOID(*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID(*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); +typedef VOID (*FuncSetXtal)(PVOID); +typedef VOID(*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; + FuncSwingXtal GetDeltaSwingXtalTable; + FuncSetXtal ODM_TxXtalTrackSetXtal; + FuncAllSwing GetDeltaAllSwingTable; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/package/kernel/rtl8192cd/phydm/mp_precomp.h b/package/kernel/rtl8192cd/phydm/mp_precomp.h index 2ae81105aaa..2e950cb2eb9 100644 --- a/package/kernel/rtl8192cd/phydm/mp_precomp.h +++ b/package/kernel/rtl8192cd/phydm/mp_precomp.h @@ -1,20 +1,20 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + diff --git a/package/kernel/rtl8192cd/phydm/phydm.c b/package/kernel/rtl8192cd/phydm/phydm.c index 8be6f61ebf2..ae0a3e1c14b 100644 --- a/package/kernel/rtl8192cd/phydm/phydm.c +++ b/package/kernel/rtl8192cd/phydm/phydm.c @@ -1,3347 +1,3347 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -//#include "mp_precomp.h" -#include "phydm_precomp.h" -#include "phydm.h" -const u2Byte dB_Invert_Table[12][8] = { - { 1, 1, 1, 2, 2, 2, 2, 3}, - { 3, 3, 4, 4, 4, 5, 6, 6}, - { 7, 8, 9, 10, 11, 13, 14, 16}, - { 18, 20, 22, 25, 28, 32, 35, 40}, - { 45, 50, 56, 63, 71, 79, 89, 100}, - { 112, 126, 141, 158, 178, 200, 224, 251}, - { 282, 316, 355, 398, 447, 501, 562, 631}, - { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, - { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, - { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, - { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, - { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} -}; - -const u2Byte phy_rate_table[28] = { /*20M*/ - 1, 2, 5, 11, - 6, 9, 12, 18, 24, 36, 48, 54, - 6, 13, 19, 26, 39, 52, 58, 65, /*MCS0~7*/ - 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/ -}; - - -//============================================================ -// Local Function predefine. -//============================================================ - -/* START------------COMMON INFO RELATED--------------- */ - -VOID -odm_GlobalAdapterCheck( - IN VOID - ); - -//move to odm_PowerTacking.h by YuChen - - - -VOID -odm_UpdatePowerTrainingState( - IN PDM_ODM_T pDM_Odm -); - -//============================================================ -//3 Export Interface -//============================================================ - -/*Y = 10*log(X)*/ -s4Byte -ODM_PWdB_Conversion( - IN s4Byte X, - IN u4Byte TotalBit, - IN u4Byte DecimalBit - ) -{ - s4Byte Y, integer = 0, decimal = 0; - u4Byte i; - - if(X == 0) - X = 1; // log2(x), x can't be 0 - - for(i = (TotalBit-1); i > 0; i--) - { - if(X & BIT(i)) - { - integer = i; - if(i > 0) - decimal = (X & BIT(i-1))?2:0; //decimal is 0.5dB*3=1.5dB~=2dB - break; - } - } - - Y = 3*(integer-DecimalBit)+decimal; //10*log(x)=3*log2(x), - - return Y; -} - -s4Byte -ODM_SignConversion( - IN s4Byte value, - IN u4Byte TotalBit - ) -{ - if(value&BIT(TotalBit-1)) - value -= BIT(TotalBit); - return value; -} - -void -phydm_seq_sorting( - IN PVOID pDM_VOID, - IN OUT u4Byte *p_value, - IN OUT u4Byte *rank_idx, - IN OUT u4Byte *p_idx_out, - IN u1Byte seq_length -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0 , j = 0; - u4Byte tmp_a, tmp_b; - u4Byte tmp_idx_a, tmp_idx_b; - - for (i = 0; i < seq_length; i++) { - rank_idx[i] = i; - /**/ - } - - for (i = 0; i < (seq_length - 1); i++) { - - for (j = 0; j < (seq_length - 1 - i); j++) { - - tmp_a = p_value[j]; - tmp_b = p_value[j+1]; - - tmp_idx_a = rank_idx[j]; - tmp_idx_b = rank_idx[j+1]; - - if (tmp_a < tmp_b) { - p_value[j] = tmp_b; - p_value[j+1] = tmp_a; - - rank_idx[j] = tmp_idx_b; - rank_idx[j+1] = tmp_idx_a; - } - } - } - - for (i = 0; i < seq_length; i++) { - p_idx_out[rank_idx[i]] = i+1; - /**/ - } - - - -} - -VOID -ODM_InitMpDriverStatus( - IN PDM_ODM_T pDM_Odm -) -{ -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - - // Decide when compile time - #if(MP_DRIVER == 1) - pDM_Odm->mp_mode = TRUE; - #else - pDM_Odm->mp_mode = FALSE; - #endif - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - - PADAPTER Adapter = pDM_Odm->Adapter; - - // Update information every period - pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; - -#else - - prtl8192cd_priv priv = pDM_Odm->priv; - - pDM_Odm->mp_mode = (BOOLEAN)priv->pshare->rf_ft_var.mp_specific; - -#endif -} - -VOID -ODM_UpdateMpDriverStatus( - IN PDM_ODM_T pDM_Odm -) -{ -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - - // Do nothing. - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - - // Update information erery period - pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; - -#else - - // Do nothing. - -#endif -} - -VOID -PHYDM_InitTRXAntennaSetting( - IN PDM_ODM_T pDM_Odm -) -{ -/*#if (RTL8814A_SUPPORT == 1)*/ - - if (pDM_Odm->SupportICType & (ODM_RTL8814A)) { - u1Byte RxAnt = 0, TxAnt = 0; - - RxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm)); - TxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_TX_PATH, pDM_Odm), ODM_BIT(BB_TX_PATH, pDM_Odm)); - pDM_Odm->TXAntStatus = (TxAnt & 0xf); - pDM_Odm->RXAntStatus = (RxAnt & 0xf); - } else if (pDM_Odm->SupportICType & (ODM_RTL8723D | ODM_RTL8821C)) { - pDM_Odm->TXAntStatus = 0x1; - pDM_Odm->RXAntStatus = 0x1; - - } -/*#endif*/ -} - -void -phydm_traffic_load_decision( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - /*---trafic load decision---*/ - pDM_Odm->curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->lastTxOkCnt; - pDM_Odm->curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->lastRxOkCnt; - pDM_Odm->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); - pDM_Odm->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ - pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ - #else - pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - #endif - pDM_Odm->total_tp = pDM_Odm->tx_tp + pDM_Odm->rx_tp; - - /*[Calculate consecutive idlel time]*/ - if (pDM_Odm->total_tp == 0) - pDM_Odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; - else - pDM_Odm->consecutive_idlel_time = 0; - - pDM_Odm->pre_TrafficLoad = pDM_Odm->TrafficLoad; - - if (pDM_Odm->curTxOkCnt > 1875000 || pDM_Odm->curRxOkCnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_HIGH; - /**/ - } else if (pDM_Odm->curTxOkCnt > 500000 || pDM_Odm->curRxOkCnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_MID; - /**/ - } else if (pDM_Odm->curTxOkCnt > 100000 || pDM_Odm->curRxOkCnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_LOW; - /**/ - } else { - - pDM_Odm->TrafficLoad = TRAFFIC_ULTRA_LOW; - /**/ - } -} - -VOID -phydm_config_ofdm_tx_path( - IN PDM_ODM_T pDM_Odm, - IN u4Byte path -) -{ - u1Byte ofdm_rx_path; - - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - - if (path == PHYDM_A) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x81121111); - /**/ - } else if (path == PHYDM_B) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x82221222); - /**/ - } else if (path == PHYDM_AB) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x83321333); - /**/ - } - - - } - #endif -} - -VOID -phydm_config_ofdm_rx_path( - IN PDM_ODM_T pDM_Odm, - IN u4Byte path -) -{ - u1Byte ofdm_rx_path = 0; - - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - - if (path == PHYDM_A) { - ofdm_rx_path = 1; - /**/ - } else if (path == PHYDM_B) { - ofdm_rx_path = 2; - /**/ - } else if (path == PHYDM_AB) { - ofdm_rx_path = 3; - /**/ - } - - ODM_SetBBReg(pDM_Odm, 0xC04 , 0xff, (((ofdm_rx_path)<<4)|ofdm_rx_path)); - ODM_SetBBReg(pDM_Odm, 0xD04 , 0xf, ofdm_rx_path); - } - #endif -} - -VOID -phydm_config_cck_rx_antenna_init( - IN PDM_ODM_T pDM_Odm -) -{ - /*CCK 2R CCA parameters*/ - ODM_SetBBReg(pDM_Odm, 0xa00, BIT(15), 0x0); /*Disable antenna diversity*/ - ODM_SetBBReg(pDM_Odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ - ODM_SetBBReg(pDM_Odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ - ODM_SetBBReg(pDM_Odm, 0xa14, BIT(7), 0); /*r_en_mrc_antsel*/ - ODM_SetBBReg(pDM_Odm, 0xa20, (BIT(5) | BIT(4)), 1); /*MBC weighting*/ - - if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) { - ODM_SetBBReg(pDM_Odm, 0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/ - /**/ - } else if(pDM_Odm->SupportICType & (ODM_RTL8814A)) { - ODM_SetBBReg(pDM_Odm, 0xa84, BIT(28), 1); /*2R CCA only*/ - /**/ - } -} - -VOID -phydm_config_cck_rx_path( - IN PDM_ODM_T pDM_Odm, - IN u1Byte path, - IN u1Byte path_div_en -) -{ - u8 path_div_select = 0; - u8 cck_path[2] = {0}; - u8 en_2R_path = 0; - u8 en_2R_mrc = 0; - u8 i = 0, j =0; - u8 num_enable_path = 0; - u8 cck_mrc_max_path = 2; - - for (i = 0; i < 4; i++) { - if (path & BIT(i)) { /*ex: PHYDM_ABCD*/ - num_enable_path++; - cck_path[j] = i; - j++; - } - if (num_enable_path >= cck_mrc_max_path) - break; - } - - if (num_enable_path > 1) { - path_div_select = 1; - en_2R_path = 1; - en_2R_mrc = 1; - } else { - path_div_select = 0; - en_2R_path = 0; - en_2R_mrc = 0; - } - -#if 0 - if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8197F | ODM_RTL8822B)) { - - if (path == PHYDM_A) { - path_div_select = 0; - cck_1_path = 0; - cck_2_path = 0; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_B) { - path_div_select = 0; - cck_1_path = 1; - cck_2_path = 1; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_AB) { - path_div_select = 1; - cck_1_path = 0; - cck_2_path = 1; - en_2R_path = 1; - en_2R_mrc = 1; - } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { - - if (path == PHYDM_A) { - path_div_select = 0; - cck_1_path = 0; - cck_2_path = 0; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_B) { - path_div_select = 0; - cck_1_path = 1; - cck_2_path = 1; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_C) { - path_div_select = 0; - cck_1_path = 2; - cck_2_path = 2; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_D) { - path_div_select = 0; - cck_1_path = 3; - cck_2_path = 3; - en_2R_path = 0; - en_2R_mrc = 0; - } else if (path == PHYDM_AB) { - path_div_select = 1; - cck_1_path = 0; - cck_2_path = 1; - en_2R_path = 1; - en_2R_mrc = 1; - } else if (path == PHYDM_AC) { - path_div_select = 1; - cck_1_path = 0; - cck_2_path = 2; - en_2R_path = 1; - en_2R_mrc = 1; - } else if (path == PHYDM_AD) { - path_div_select = 1; - cck_1_path = 0; - cck_2_path = 3; - en_2R_path = 1; - en_2R_mrc = 1; - } else if (path == PHYDM_BC) { - path_div_select = 1; - cck_1_path = 1; - cck_2_path = 2; - en_2R_path = 1; - en_2R_mrc = 1; - } else if (path == PHYDM_BD) { - path_div_select = 1; - cck_1_path = 1; - cck_2_path = 3; - en_2R_path = 1; - en_2R_mrc = 1; - } else if (path == PHYDM_CD) { - path_div_select = 1; - cck_1_path = 2; - cck_2_path = 3; - en_2R_path = 1; - en_2R_mrc = 1; - } - } -#endif - - ODM_SetBBReg(pDM_Odm, 0xa04, (BIT(27) | BIT(26)), cck_path[0]); /*CCK_1 input signal path*/ - ODM_SetBBReg(pDM_Odm, 0xa04, (BIT(25) | BIT(24)), cck_path[1]); /*CCK_2 input signal path*/ - ODM_SetBBReg(pDM_Odm, 0xa74, BIT(8), path_div_select); /*enable Rx path diversity*/ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT(18), en_2R_path); /*enable 2R Rx path*/ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT(22), en_2R_mrc); /*enable 2R MRC*/ -} - -VOID -phydm_config_trx_path( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_support_ability; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - /* CCK */ - if (dm_value[0] == 0) { - - if (dm_value[1] == 1) { /*TX*/ - if (dm_value[2] == 1) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); - else if (dm_value[2] == 2) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); - else if (dm_value[2] == 3) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); - } else if (dm_value[1] == 2) { /*RX*/ - - phydm_config_cck_rx_antenna_init(pDM_Odm); - - if (dm_value[2] == 1) { - phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); - } else if (dm_value[2] == 2) { - phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); - } else if (dm_value[2] == 3) { - if (dm_value[3] == 1) /*enable path diversity*/ - phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE); - else - phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); - } - } - } - /* OFDM */ - else if (dm_value[0] == 1) { - - if (dm_value[1] == 1) { /*TX*/ - phydm_config_ofdm_tx_path(pDM_Odm, dm_value[2]); - /**/ - } else if (dm_value[1] == 2) { /*RX*/ - phydm_config_ofdm_rx_path(pDM_Odm, dm_value[2]); - /**/ - } - } - - PHYDM_SNPRINTF((output+used, out_len-used, "PHYDM Set Path [%s] [%s] = [%s%s%s%s]\n", - (dm_value[0] == 1) ? "OFDM" : "CCK", - (dm_value[1] == 1) ? "TX" : "RX", - (dm_value[2] & 0x1)?"A":"", - (dm_value[2] & 0x2)?"B":"", - (dm_value[2] & 0x4)?"C":"", - (dm_value[2] & 0x8)?"D":"" - )); - -} - -VOID -phydm_Init_cck_setting( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value_824,value_82c; - - pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm)); - - - phydm_config_cck_rx_antenna_init(pDM_Odm); -#if 0//(RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType & (ODM_RTL8192E)) - phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE); - else -#endif - phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); - - #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType & (ODM_RTL8192E)) - { - /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ - value_824 = ODM_GetBBReg(pDM_Odm, 0x824, BIT9); - value_82c = ODM_GetBBReg(pDM_Odm, 0x82c, BIT9); - - if(value_824 != value_82c) - { - ODM_SetBBReg(pDM_Odm, 0x82c , BIT9, value_824); - } - ODM_SetBBReg(pDM_Odm, 0xa80 , BIT7, value_824); - pDM_Odm->cck_agc_report_type = (BOOLEAN)value_824; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ExtLNAGain = (( %d ))\n", pDM_Odm->cck_agc_report_type, pDM_Odm->ExtLNAGain)); - } - #endif - -#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723D)) { - - pDM_Odm->cck_agc_report_type = ODM_GetBBReg(pDM_Odm, 0x950, BIT11) ? 1 : 0; /*1: 4bit LNA , 0: 3bit LNA */ - - if (pDM_Odm->cck_agc_report_type != 1) { - DbgPrint("[Warning] 8703B/8723D CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); - /**/ - } - } -#endif - -#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - - if (pDM_Odm->SupportICType & (ODM_RTL8723D|ODM_RTL8822B|ODM_RTL8197F)) { - pDM_Odm->cck_new_agc = ODM_GetBBReg(pDM_Odm, 0xa9c, BIT17)?TRUE:FALSE; /*1: new agc 0: old agc*/ - } else -#endif - pDM_Odm->cck_new_agc = FALSE; - - phydm_get_cck_rssi_table_from_reg(pDM_Odm); -} - -VOID -PHYDM_InitSoftMLSetting( - IN PDM_ODM_T pDM_Odm -) -{ -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->mp_mode == FALSE) { - if (pDM_Odm->SupportICType & ODM_RTL8822B) - /*ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xd10a0000);*/ - phydm_somlrxhp_setting(pDM_Odm, TRUE); - } -#endif -} - -VOID -PHYDM_InitHwInfoByRfe( - IN PDM_ODM_T pDM_Odm -) -{ -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - phydm_init_hw_info_by_rfe_type_8822b(pDM_Odm); -#endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - phydm_init_hw_info_by_rfe_type_8197f(pDM_Odm); -#endif -} - -VOID -odm_CommonInfoSelfInit( - IN PDM_ODM_T pDM_Odm - ) -{ - phydm_Init_cck_setting(pDM_Odm); - pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm)); -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) - pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; - - PHYDM_InitDebugSetting(pDM_Odm); -#endif - ODM_InitMpDriverStatus(pDM_Odm); - PHYDM_InitTRXAntennaSetting(pDM_Odm); - PHYDM_InitSoftMLSetting(pDM_Odm); - - pDM_Odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; - pDM_Odm->phydm_sys_up_time = 0; - - if (pDM_Odm->SupportICType & ODM_IC_1SS) - pDM_Odm->num_rf_path = 1; - else if (pDM_Odm->SupportICType & ODM_IC_2SS) - pDM_Odm->num_rf_path = 2; - else if(pDM_Odm->SupportICType & ODM_IC_3SS ) - pDM_Odm->num_rf_path = 3; - else if(pDM_Odm->SupportICType & ODM_IC_4SS ) - pDM_Odm->num_rf_path = 4; - - pDM_Odm->TxRate = 0xFF; - pDM_Odm->RSSI_Min = 0xFF; - pDM_Odm->RSSI_Min_ByPath = 0xFF; - - pDM_Odm->number_linked_client = 0; - pDM_Odm->pre_number_linked_client = 0; - pDM_Odm->number_active_client = 0; - pDM_Odm->pre_number_active_client = 0; - - pDM_Odm->lastTxOkCnt = 0; - pDM_Odm->lastRxOkCnt = 0; - pDM_Odm->tx_tp = 0; - pDM_Odm->rx_tp = 0; - pDM_Odm->total_tp = 0; - pDM_Odm->TrafficLoad = TRAFFIC_LOW; - - pDM_Odm->nbi_set_result = 0; - pDM_Odm->bInitHwInfoByRfe = FALSE; - pDM_Odm->tp_active_th = 5; - -} - -VOID -odm_CommonInfoSelfUpdate( - IN PDM_ODM_T pDM_Odm - ) -{ - u1Byte EntryCnt = 0, num_active_client = 0; - u4Byte i, OneEntry_MACID = 0, ma_rx_tp = 0; - PSTA_INFO_T pEntry; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - - pEntry = pDM_Odm->pODM_StaInfo[0]; - if (pMgntInfo->mAssoc) { - pEntry->bUsed = TRUE; - for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; - } else if (GetFirstClientPort(Adapter)) { - PADAPTER pClientAdapter = GetFirstClientPort(Adapter); - - pEntry->bUsed = TRUE; - for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = pClientAdapter->MgntInfo.Bssid[i]; - } else { - pEntry->bUsed = FALSE; - for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = 0; - } - - //STA mode is linked to AP - if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(Adapter)) - pDM_Odm->bsta_state = TRUE; - else - pDM_Odm->bsta_state = FALSE; -#endif - -/* THis variable cannot be used because it is wrong*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; - } else if (*(pDM_Odm->pBandWidth) == ODM_BW80M) { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 6; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 6; - } else - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); -#else - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; - } else - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); -#endif - - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - EntryCnt++; - if(EntryCnt==1) - { - OneEntry_MACID=i; - } - - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ma_rx_tp = (pEntry->rx_byte_cnt_LowMAW)>>17; /* low moving average RX TP ( bit /sec), <<3(8bit), >>20(10^6,M)*/ - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); - - if (ma_rx_tp > ACTIVE_TP_THRESHOLD) - num_active_client++; - #endif - } - } - - if(EntryCnt == 1) - { - pDM_Odm->bOneEntryOnly = TRUE; - pDM_Odm->OneEntry_MACID=OneEntry_MACID; - pDM_Odm->one_entry_tp = ma_rx_tp; - - pDM_Odm->tp_active_occur = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", - pDM_Odm->one_entry_tp, pDM_Odm->pre_one_entry_tp)); - - if ((pDM_Odm->one_entry_tp > pDM_Odm->pre_one_entry_tp) && (pDM_Odm->pre_one_entry_tp <= 2)) { - if ((pDM_Odm->one_entry_tp - pDM_Odm->pre_one_entry_tp) > pDM_Odm->tp_active_th) { - pDM_Odm->tp_active_occur = 1; - } - } - } - else - pDM_Odm->bOneEntryOnly = FALSE; - - pDM_Odm->pre_number_linked_client = pDM_Odm->number_linked_client; - pDM_Odm->pre_number_active_client = pDM_Odm->number_active_client; - - pDM_Odm->number_linked_client = EntryCnt; - pDM_Odm->number_active_client = num_active_client; - - /* Update MP driver status*/ - ODM_UpdateMpDriverStatus(pDM_Odm); - - /*Traffic load information update*/ - phydm_traffic_load_decision(pDM_Odm); - - pDM_Odm->phydm_sys_up_time += pDM_Odm->phydm_period; -} - -VOID -odm_CommonInfoSelfReset( - IN PDM_ODM_T pDM_Odm - ) -{ -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0; -#endif -} - -PVOID -PhyDM_Get_Structure( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Structure_Type -) - -{ - PVOID pStruct = NULL; -#if RTL8195A_SUPPORT - switch (Structure_Type){ - case PHYDM_FALSEALMCNT: - pStruct = &FalseAlmCnt; - break; - - case PHYDM_CFOTRACK: - pStruct = &DM_CfoTrack; - break; - - case PHYDM_ADAPTIVITY: - pStruct = &(pDM_Odm->Adaptivity); - break; - - default: - break; - } - -#else - switch (Structure_Type){ - case PHYDM_FALSEALMCNT: - pStruct = &(pDM_Odm->FalseAlmCnt); - break; - - case PHYDM_CFOTRACK: - pStruct = &(pDM_Odm->DM_CfoTrack); - break; - - case PHYDM_ADAPTIVITY: - pStruct = &(pDM_Odm->Adaptivity); - break; - - default: - break; - } - -#endif - return pStruct; -} - -VOID -odm_HWSetting( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (RTL8821A_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_RTL8821) - odm_HWSetting_8821A(pDM_Odm); -#endif - -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_hwsetting_8814a(pDM_Odm); -#endif - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - phydm_hwsetting_8822b(pDM_Odm); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - phydm_hwsetting_8197f(pDM_Odm); -#endif -} - -// -// 2011/09/21 MH Add to describe different team necessary resource allocate?? -// -VOID -ODM_DMInit( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - odm_CommonInfoSelfInit(pDM_Odm); - odm_DIGInit(pDM_Odm); - Phydm_NHMCounterStatisticsInit(pDM_Odm); - Phydm_AdaptivityInit(pDM_Odm); - phydm_ra_info_init(pDM_Odm); - odm_RateAdaptiveMaskInit(pDM_Odm); - ODM_CfoTrackingInit(pDM_Odm); - ODM_EdcaTurboInit(pDM_Odm); - odm_RSSIMonitorInit(pDM_Odm); - phydm_rf_init(pDM_Odm); - odm_TXPowerTrackingInit(pDM_Odm); - odm_AntennaDiversityInit(pDM_Odm); - phydm_adaptive_soml_init(pDM_Odm); - odm_AutoChannelSelectInit(pDM_Odm); - odm_PathDiversityInit(pDM_Odm); - odm_DynamicTxPowerInit(pDM_Odm); - phydm_initRaInfo(pDM_Odm); - phydm_lna_sat_chk_init(pDM_Odm); - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - phydm_lna_sat_chk_type2_init(pDM_Odm); -#endif - -#if (PHYDM_LA_MODE_SUPPORT == 1) - ADCSmp_Init(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#ifdef BEAMFORMING_VERSION_1 - if (pHalData->BeamformingVersion == BEAMFORMING_VERSION_1) -#endif - { - phydm_Beamforming_Init(pDM_Odm); - } -#endif - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { -#if (defined(CONFIG_BB_POWER_SAVING)) - odm_DynamicBBPowerSavingInit(pDM_Odm); -#endif - -#if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8188E) - { - ODM_PrimaryCCA_Init(pDM_Odm); - ODM_RAInfo_Init_all(pDM_Odm); - } -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - - #if (RTL8723B_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8723B) - odm_SwAntDetectInit(pDM_Odm); - #endif - - #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8192E) - odm_PrimaryCCA_Check_Init(pDM_Odm); - #endif - -#endif - - } - -} - -VOID -ODM_DMReset( - IN PDM_ODM_T pDM_Odm - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - ODM_AntDivReset(pDM_Odm); - phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue); -} - - -VOID -phydm_support_ability_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_support_ability; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pre_support_ability = pDM_Odm->SupportAbility ; - PHYDM_SNPRINTF((output+used, out_len-used,"\n%s\n", "================================")); - if(dm_value[0] == 100) - { - PHYDM_SNPRINTF((output+used, out_len-used, "[Supportability] PhyDM Selection\n")); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); - PHYDM_SNPRINTF((output+used, out_len-used, "00. (( %s ))DIG\n", ((pDM_Odm->SupportAbility & ODM_BB_DIG)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->SupportAbility & ODM_BB_RA_MASK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_FA_CNT)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "05. (( %s ))CCK_PD\n", ((pDM_Odm->SupportAbility & ODM_BB_CCK_PD)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "08. (( %s ))PWR_TRAIN\n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->SupportAbility & ODM_BB_RATE_ADAPTIVE)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "11. (( %s ))LNA_SAT_CHK\n", ((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "12. (( %s ))LNA_SAT_CHK_TYPE2\n", ((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK_TYPE2)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "13. (( %s ))ADAPTIVITY\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "14. (( %s ))CFO_TRACKING\n", ((pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "15. (( %s ))NHM_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "16. (( %s ))PRIMARY_CCA\n", ((pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "17. (( %s ))TXBF\n", ((pDM_Odm->SupportAbility & ODM_BB_TXBF)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "18. (( %s ))DYNAMIC_ARFR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "19. (( %s ))DYNAMIC_PSD_TOOL\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_PSDTOOL)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "21. (( %s ))EARLY_MODE\n", ((pDM_Odm->SupportAbility & ODM_MAC_EARLY_MODE)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "23. (( %s ))ADAPTIVE_SOML\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVE_SOML)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_RX_GAIN_TRACK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "26. (( %s ))RF_CALIBRATION\n", ((pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); - } - /* - else if(dm_value[0] == 101) - { - pDM_Odm->SupportAbility = 0 ; - DbgPrint("Disable all SupportAbility components \n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all SupportAbility components")); - } - */ - else - { - - if(dm_value[1] == 1) //enable - { - pDM_Odm->SupportAbility |= BIT(dm_value[0]) ; - if(BIT(dm_value[0]) & ODM_BB_PATH_DIV) - { - odm_PathDiversityInit(pDM_Odm); - } - } - else if(dm_value[1] == 2) //disable - { - pDM_Odm->SupportAbility &= ~(BIT(dm_value[0])) ; - } - else - { - //DbgPrint("\n[Warning!!!] 1:enable, 2:disable \n\n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "[Warning!!!] 1:enable, 2:disable")); - } - } - PHYDM_SNPRINTF((output+used, out_len-used,"pre-SupportAbility = 0x%x\n", pre_support_ability )); - PHYDM_SNPRINTF((output+used, out_len-used,"Curr-SupportAbility = 0x%x\n", pDM_Odm->SupportAbility )); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -// -//tmp modify for LC Only -// -VOID -ODM_DMWatchdog_LPS( - IN PDM_ODM_T pDM_Odm - ) -{ - odm_CommonInfoSelfUpdate(pDM_Odm); - odm_FalseAlarmCounterStatistics(pDM_Odm); - odm_RSSIMonitorCheck(pDM_Odm); - odm_DIGbyRSSI_LPS(pDM_Odm); - odm_CCKPacketDetectionThresh(pDM_Odm); - odm_CommonInfoSelfReset(pDM_Odm); - - if(*(pDM_Odm->pbPowerSaving)==TRUE) - return; -} -#endif -// -// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. -// You can not add any dummy function here, be care, you can only use DM structure -// to perform any new ODM_DM. -// -VOID -ODM_DMWatchdog( - IN PDM_ODM_T pDM_Odm - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - odm_CommonInfoSelfUpdate(pDM_Odm); - phydm_BasicDbgMessage(pDM_Odm); - odm_HWSetting(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - { - prtl8192cd_priv priv = pDM_Odm->priv; - if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )//if ACS running, do not do FA/CCA counter read - return; - } -#endif - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if(pDM_Odm->original_dig_restore) -#endif - { - odm_FalseAlarmCounterStatistics(pDM_Odm); - } - - phydm_NoisyDetection(pDM_Odm); - - odm_RSSIMonitorCheck(pDM_Odm); - - phydm_adaptive_soml(pDM_Odm); - - if(*(pDM_Odm->pbPowerSaving) == TRUE) - { - odm_DIGbyRSSI_LPS(pDM_Odm); - { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); - } - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - odm_AntennaDiversity(pDM_Odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ - #endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); - return; - } - - Phydm_CheckAdaptivity(pDM_Odm); - odm_UpdatePowerTrainingState(pDM_Odm); - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if(pDM_Odm->original_dig_restore == 0) - phydm_tdma_dig_timer_check(pDM_Odm); - else -#endif - { - odm_DIG(pDM_Odm); - } - - Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); - - phydm_lna_sat_chk_watchdog(pDM_Odm); - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - phydm_lna_sat_type2_sm(pDM_Odm); -#endif - odm_CCKPacketDetectionThresh(pDM_Odm); - - phydm_ra_info_watchdog(pDM_Odm); - phydm_receiver_blocking(pDM_Odm); - odm_EdcaTurboCheck(pDM_Odm); - odm_PathDiversity(pDM_Odm); - ODM_CfoTracking(pDM_Odm); - odm_DynamicTxPower(pDM_Odm); - odm_AntennaDiversity(pDM_Odm); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - phydm_Beamforming_Watchdog(pDM_Odm); -#endif - - phydm_rf_watchdog(pDM_Odm); - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ODM_DynamicPrimaryCCA(pDM_Odm); -#endif - -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - - #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8192E) - odm_DynamicPrimaryCCA_Check(pDM_Odm); - #endif -#endif - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - odm_dtc(pDM_Odm); -#endif - - odm_CommonInfoSelfReset(pDM_Odm); - -} - - -// -// Init /.. Fixed HW value. Only init time. -// -VOID -ODM_CmnInfoInit( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u4Byte Value - ) -{ - // - // This section is used for init value - // - switch (CmnInfo) - { - // - // Fixed ODM value. - // - case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility = (u4Byte)Value; - break; - - case ODM_CMNINFO_RF_TYPE: - pDM_Odm->RFType = (u1Byte)Value; - break; - - case ODM_CMNINFO_PLATFORM: - pDM_Odm->SupportPlatform = (u1Byte)Value; - break; - - case ODM_CMNINFO_INTERFACE: - pDM_Odm->SupportInterface = (u1Byte)Value; - break; - - case ODM_CMNINFO_MP_TEST_CHIP: - pDM_Odm->bIsMPChip= (u1Byte)Value; - break; - - case ODM_CMNINFO_IC_TYPE: - pDM_Odm->SupportICType = Value; - break; - - case ODM_CMNINFO_CUT_VER: - pDM_Odm->CutVersion = (u1Byte)Value; - break; - - case ODM_CMNINFO_FAB_VER: - pDM_Odm->FabVersion = (u1Byte)Value; - break; - - case ODM_CMNINFO_RFE_TYPE: - pDM_Odm->RFEType = (u1Byte)Value; - PHYDM_InitHwInfoByRfe(pDM_Odm); - break; - - case ODM_CMNINFO_RF_ANTENNA_TYPE: - pDM_Odm->AntDivType= (u1Byte)Value; - break; - - case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: - pDM_Odm->with_extenal_ant_switch = (u1Byte)Value; - break; - - case ODM_CMNINFO_BE_FIX_TX_ANT: - pDM_Odm->DM_FatTable.b_fix_tx_ant = (u1Byte)Value; - break; - - case ODM_CMNINFO_BOARD_TYPE: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->BoardType = (u1Byte)Value; - break; - - case ODM_CMNINFO_PACKAGE_TYPE: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->PackageType = (u1Byte)Value; - break; - - case ODM_CMNINFO_EXT_LNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtLNA = (u1Byte)Value; - break; - - case ODM_CMNINFO_5G_EXT_LNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtLNA5G = (u1Byte)Value; - break; - - case ODM_CMNINFO_EXT_PA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtPA = (u1Byte)Value; - break; - - case ODM_CMNINFO_5G_EXT_PA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtPA5G = (u1Byte)Value; - break; - - case ODM_CMNINFO_GPA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeGPA = (u2Byte)Value; - break; - - case ODM_CMNINFO_APA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeAPA = (u2Byte)Value; - break; - - case ODM_CMNINFO_GLNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeGLNA = (u2Byte)Value; - break; - - case ODM_CMNINFO_ALNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeALNA = (u2Byte)Value; - break; - - case ODM_CMNINFO_EXT_TRSW: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtTRSW = (u1Byte)Value; - break; - case ODM_CMNINFO_EXT_LNA_GAIN: - pDM_Odm->ExtLNAGain = (u1Byte)Value; - break; - case ODM_CMNINFO_PATCH_ID: - pDM_Odm->PatchID = (u1Byte)Value; - break; - case ODM_CMNINFO_BINHCT_TEST: - pDM_Odm->bInHctTest = (BOOLEAN)Value; - break; - case ODM_CMNINFO_BWIFI_TEST: - pDM_Odm->WIFITest = (u1Byte)Value; - break; - case ODM_CMNINFO_SMART_CONCURRENT: - pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; - break; - case ODM_CMNINFO_DOMAIN_CODE_2G: - pDM_Odm->odm_Regulation2_4G = (u1Byte)Value; - break; - case ODM_CMNINFO_DOMAIN_CODE_5G: - pDM_Odm->odm_Regulation5G = (u1Byte)Value; - break; - case ODM_CMNINFO_CONFIG_BB_RF: - pDM_Odm->ConfigBBRF = (BOOLEAN)Value; - break; - case ODM_CMNINFO_IQKFWOFFLOAD: - pDM_Odm->IQKFWOffload = (u1Byte)Value; - break; - case ODM_CMNINFO_IQKPAOFF: - pDM_Odm->RFCalibrateInfo.bIQKPAoff = (BOOLEAN )Value; - break; - case ODM_CMNINFO_REGRFKFREEENABLE: - pDM_Odm->RFCalibrateInfo.RegRfKFreeEnable = (u1Byte)Value; - break; - case ODM_CMNINFO_RFKFREEENABLE: - pDM_Odm->RFCalibrateInfo.RfKFreeEnable = (u1Byte)Value; - break; - case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: - pDM_Odm->Normalrxpath = (u1Byte)Value; - break; -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - pDM_Odm->DFS_RegionDomain = (u1Byte)Value; - break; -#endif - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - - } - -} - - -VOID -ODM_CmnInfoHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN PVOID pValue - ) -{ - // - // Hook call by reference pointer. - // - switch (CmnInfo) - { - // - // Dynamic call by reference pointer. - // - case ODM_CMNINFO_MAC_PHY_MODE: - pDM_Odm->pMacPhyMode = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_TX_UNI: - pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; - break; - - case ODM_CMNINFO_RX_UNI: - pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; - break; - - case ODM_CMNINFO_WM_MODE: - pDM_Odm->pWirelessMode = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_BAND: - pDM_Odm->pBandType = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->pSecChOffset = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_SEC_MODE: - pDM_Odm->pSecurity = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_BW: - pDM_Odm->pBandWidth = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_CHNL: - pDM_Odm->pChannel = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_DMSP_GET_VALUE: - pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_BUDDY_ADAPTOR: - pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; - break; - - case ODM_CMNINFO_DMSP_IS_MASTER: - pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_SCAN: - pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_POWER_SAVING: - pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_ONE_PATH_CCA: - pDM_Odm->pOnePathCCA = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_DRV_STOP: - pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_PNP_IN: - pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_INIT_ON: - pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_ANT_TEST: - pDM_Odm->pAntennaTest = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_NET_CLOSED: - pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_FORCED_RATE: - pDM_Odm->pForcedDataRate = (pu2Byte)pValue; - break; - - case ODM_CMNINFO_FORCED_IGI_LB: - pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_P2P_LINK: - pDM_Odm->DM_DigTable.bP2PInProcess = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_IS1ANTENNA: - pDM_Odm->pIs1Antenna = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_RFDEFAULTPATH: - pDM_Odm->pRFDefaultPath= (u1Byte *)pValue; - break; - - case ODM_CMNINFO_FCS_MODE: - pDM_Odm->pIsFcsModeEnable = (BOOLEAN *)pValue; - break; - /*add by YuChen for beamforming PhyDM*/ - case ODM_CMNINFO_HUBUSBMODE: - pDM_Odm->HubUsbMode = (u1Byte *)pValue; - break; - case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: - pDM_Odm->pbFwDwRsvdPageInProgress = (BOOLEAN *)pValue; - break; - case ODM_CMNINFO_TX_TP: - pDM_Odm->pCurrentTxTP = (u4Byte *)pValue; - break; - case ODM_CMNINFO_RX_TP: - pDM_Odm->pCurrentRxTP = (u4Byte *)pValue; - break; - case ODM_CMNINFO_SOUNDING_SEQ: - pDM_Odm->pSoundingSeq = (u1Byte *)pValue; - break; -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_MASTER_ENABLE: - pDM_Odm->dfs_master_enabled = (u1Byte *)pValue; - break; -#endif - case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: - pDM_Odm->DM_FatTable.pForceTxAntByDesc = (u1Byte *)pValue; - break; - //case ODM_CMNINFO_RTSTA_AID: - // pDM_Odm->pAidMap = (u1Byte *)pValue; - // break; - - //case ODM_CMNINFO_BT_COEXIST: - // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; - - //case ODM_CMNINFO_STA_STATUS: - //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; - //break; - - //case ODM_CMNINFO_PHY_STATUS: - // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; - // break; - - //case ODM_CMNINFO_MAC_STATUS: - // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; - // break; - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - - } - -} - - -VOID -ODM_CmnInfoPtrArrayHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u2Byte Index, - IN PVOID pValue - ) -{ - // - // Hook call by reference pointer. - // - switch (CmnInfo) - { - // - // Dynamic call by reference pointer. - // - case ODM_CMNINFO_STA_STATUS: - pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; - - if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[Index])) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->AssociatedMacId] = Index; /*AssociatedMacId are unique bttween different Adapter*/ - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->aid] = Index; - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->mac_id] = Index; - #endif - - break; - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - } - -} - - -// -// Update Band/CHannel/.. The values are dynamic but non-per-packet. -// -VOID -ODM_CmnInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte CmnInfo, - IN u8Byte Value - ) -{ - // - // This init variable may be changed in run time. - // - switch (CmnInfo) - { - case ODM_CMNINFO_LINK_IN_PROGRESS: - pDM_Odm->bLinkInProcess = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility = (u4Byte)Value; - break; - - case ODM_CMNINFO_RF_TYPE: - pDM_Odm->RFType = (u1Byte)Value; - break; - - case ODM_CMNINFO_WIFI_DIRECT: - pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_WIFI_DISPLAY: - pDM_Odm->bWIFI_Display = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_LINK: - pDM_Odm->bLinked = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_STATION_STATE: - pDM_Odm->bsta_state = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_RSSI_MIN: - pDM_Odm->RSSI_Min= (u1Byte)Value; - break; - - case ODM_CMNINFO_MACID_RSSI_MIN: - pDM_Odm->macid_rssi_min = (u1Byte)Value; - break; - - case ODM_CMNINFO_RSSI_MIN_BY_PATH: - pDM_Odm->RSSI_Min_ByPath= (u1Byte)Value; - break; - - case ODM_CMNINFO_DBG_COMP: - pDM_Odm->DebugComponents = (u4Byte)Value; - break; - - case ODM_CMNINFO_DBG_LEVEL: - pDM_Odm->DebugLevel = (u4Byte)Value; - break; - case ODM_CMNINFO_RA_THRESHOLD_HIGH: - pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; - break; - - case ODM_CMNINFO_RA_THRESHOLD_LOW: - pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; - break; -#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) - // The following is for BT HS mode and BT coexist mechanism. - case ODM_CMNINFO_BT_ENABLED: - pDM_Odm->bBtEnabled = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: - pDM_Odm->bBtConnectProcess = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_HS_RSSI: - pDM_Odm->btHsRssi = (u1Byte)Value; - break; - - case ODM_CMNINFO_BT_OPERATION: - pDM_Odm->bBtHsOperation = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_LIMITED_DIG: - pDM_Odm->bBtLimitedDig = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_DIG: - pDM_Odm->btHsDigVal = (u1Byte)Value; - break; - - case ODM_CMNINFO_BT_BUSY: - pDM_Odm->bBtBusy = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_DISABLE_EDCA: - pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; - break; -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - case ODM_CMNINFO_VXD_LINK: - pDM_Odm->VXD_bLinked= (BOOLEAN)Value; - break; -#endif -#endif - - case ODM_CMNINFO_AP_TOTAL_NUM: - pDM_Odm->APTotalNum = (u1Byte)Value; - break; - - case ODM_CMNINFO_POWER_TRAINING: - pDM_Odm->bDisablePowerTraining = (BOOLEAN)Value; - break; - -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - pDM_Odm->DFS_RegionDomain = (u1Byte)Value; - break; -#endif - -/* - case ODM_CMNINFO_OP_MODE: - pDM_Odm->OPMode = (u1Byte)Value; - break; - - case ODM_CMNINFO_WM_MODE: - pDM_Odm->WirelessMode = (u1Byte)Value; - break; - - case ODM_CMNINFO_BAND: - pDM_Odm->BandType = (u1Byte)Value; - break; - - case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->SecChOffset = (u1Byte)Value; - break; - - case ODM_CMNINFO_SEC_MODE: - pDM_Odm->Security = (u1Byte)Value; - break; - - case ODM_CMNINFO_BW: - pDM_Odm->BandWidth = (u1Byte)Value; - break; - - case ODM_CMNINFO_CHNL: - pDM_Odm->Channel = (u1Byte)Value; - break; -*/ - default: - //do nothing - break; - } - - -} - -u4Byte -PHYDM_CmnInfoQuery( - IN PDM_ODM_T pDM_Odm, - IN PHYDM_INFO_QUERY_E info_type - ) -{ - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT); - - switch (info_type) { - case PHYDM_INFO_FA_OFDM: - return FalseAlmCnt->Cnt_Ofdm_fail; - - case PHYDM_INFO_FA_CCK: - return FalseAlmCnt->Cnt_Cck_fail; - - case PHYDM_INFO_FA_TOTAL: - return FalseAlmCnt->Cnt_all; - - case PHYDM_INFO_CCA_OFDM: - return FalseAlmCnt->Cnt_OFDM_CCA; - - case PHYDM_INFO_CCA_CCK: - return FalseAlmCnt->Cnt_CCK_CCA; - - case PHYDM_INFO_CCA_ALL: - return FalseAlmCnt->Cnt_CCA_all; - - case PHYDM_INFO_CRC32_OK_VHT: - return FalseAlmCnt->cnt_vht_crc32_ok; - - case PHYDM_INFO_CRC32_OK_HT: - return FalseAlmCnt->cnt_ht_crc32_ok; - - case PHYDM_INFO_CRC32_OK_LEGACY: - return FalseAlmCnt->cnt_ofdm_crc32_ok; - - case PHYDM_INFO_CRC32_OK_CCK: - return FalseAlmCnt->cnt_cck_crc32_ok; - - case PHYDM_INFO_CRC32_ERROR_VHT: - return FalseAlmCnt->cnt_vht_crc32_error; - - case PHYDM_INFO_CRC32_ERROR_HT: - return FalseAlmCnt->cnt_ht_crc32_error; - - case PHYDM_INFO_CRC32_ERROR_LEGACY: - return FalseAlmCnt->cnt_ofdm_crc32_error; - - case PHYDM_INFO_CRC32_ERROR_CCK: - return FalseAlmCnt->cnt_cck_crc32_error; - - case PHYDM_INFO_EDCCA_FLAG: - return FalseAlmCnt->edcca_flag; - - case PHYDM_INFO_OFDM_ENABLE: - return FalseAlmCnt->ofdm_block_enable; - - case PHYDM_INFO_CCK_ENABLE: - return FalseAlmCnt->cck_block_enable; - - case PHYDM_INFO_DBG_PORT_0: - return FalseAlmCnt->dbg_port0; - - default: - return 0xffffffff; - - } -} - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) -{ - - PADAPTER pAdapter = pDM_Odm->Adapter; -#if USE_WORKITEM - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_InitializeWorkItem( pDM_Odm, - &pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem, - (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback, - (PVOID)pAdapter, - "AntennaSwitchWorkitem"); - #endif - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - ODM_InitializeWorkItem(pDM_Odm, - &pDM_Odm->dm_sat_table.hl_smart_antenna_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, - (PVOID)pAdapter, - "hl_smart_ant_workitem"); - - ODM_InitializeWorkItem(pDM_Odm, - &pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, - (PVOID)pAdapter, - "hl_smart_ant_decision_workitem"); - #endif - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->PathDivSwitchWorkitem), - (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, - (PVOID)pAdapter, - "SWAS_WorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->CCKPathDiversityWorkitem), - (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, - (PVOID)pAdapter, - "CCKTXPathDiversityWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->MPT_DIGWorkitem), - (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback, - (PVOID)pAdapter, - "MPT_DIGWorkitem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->RaRptWorkitem), - (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback, - (PVOID)pAdapter, - "RaRptWorkitem"); - -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->FastAntTrainingWorkitem), - (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, - (PVOID)pAdapter, - "FastAntTrainingWorkitem"); -#endif - -#endif /*#if USE_WORKITEM*/ - -#if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_EnterWorkItemCallback, - (PVOID)pAdapter, - "Txbf_EnterWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_LeaveWorkItemCallback, - (PVOID)pAdapter, - "Txbf_LeaveWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_FwNdpaWorkItemCallback, - (PVOID)pAdapter, - "Txbf_FwNdpaWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_ClkWorkItemCallback, - (PVOID)pAdapter, - "Txbf_ClkWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_RateWorkItemCallback, - (PVOID)pAdapter, - "Txbf_RateWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_StatusWorkItemCallback, - (PVOID)pAdapter, - "Txbf_StatusWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_ResetTxPathWorkItemCallback, - (PVOID)pAdapter, - "Txbf_ResetTxPathWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_GetTxRateWorkItemCallback, - (PVOID)pAdapter, - "Txbf_GetTxRateWorkItem"); -#endif - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem), - (RT_WORKITEM_CALL_BACK)phydm_pauseEDCCA_WorkItemCallback, - (PVOID)pAdapter, - "phydm_pauseEDCCAWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem), - (RT_WORKITEM_CALL_BACK)phydm_resumeEDCCA_WorkItemCallback, - (PVOID)pAdapter, - "phydm_resumeEDCCAWorkItem"); - -} - -VOID -ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) -{ -#if USE_WORKITEM - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_FreeWorkItem(&(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem)); -#endif - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_workitem)); - ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem)); -#endif - - ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); - ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); -#endif - ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem)); - ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem)); - /*ODM_FreeWorkItem((&pDM_Odm->sbdcnt_workitem));*/ -#endif - -#if (BEAMFORMING_SUPPORT == 1) - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem)); -#endif - - ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem)); - -} -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - -/* -VOID -odm_FindMinimumRSSI( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte i; - u1Byte RSSI_Min = 0xFF; - - for(i=0; ipODM_StaInfo[i] != NULL) - if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) - { - if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) - { - RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; - } - } - } - - pDM_Odm->RSSI_Min = RSSI_Min; - -} - -VOID -odm_IsLinked( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte i; - BOOLEAN Linked = FALSE; - - for(i=0; ipODM_StaInfo[i]) ) - { - Linked = TRUE; - break; - } - - } - - pDM_Odm->bLinked = Linked; -} -*/ - -VOID -ODM_InitAllTimers( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,INIT_ANTDIV_TIMMER); -#endif - -#if (CONFIG_ADAPTIVE_SOML) - phydm_adaptive_soml_timers(pDM_Odm, INIT_SOML_TIMMER); -#endif - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - phydm_tdma_dig_timers(pDM_Odm, INIT_TDMA_DIG_TIMMER); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - - phydm_lna_sat_chk_timers(pDM_Odm, INIT_LNA_SAT_CHK_TIMMER); - -#ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, - (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); -#endif -#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, - (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, - (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, - (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, - (RT_TIMER_CALL_BACK)phydm_sbd_callback, NULL, "SbdTimer"); -#if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer, - (RT_TIMER_CALL_BACK)halComTxbf_FwNdpaTimerCallback, NULL, "Txbf_FwNdpaTimer"); -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer, - (RT_TIMER_CALL_BACK)Beamforming_SWTimerCallback, NULL, "BeamformingTimer"); -#endif -#endif -} - -VOID -ODM_CancelAllTimers( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // - // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in - // win7 platform. - // - HAL_ADAPTER_STS_CHK(pDM_Odm) -#endif - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,CANCEL_ANTDIV_TIMMER); -#endif - -#if (CONFIG_ADAPTIVE_SOML) - phydm_adaptive_soml_timers(pDM_Odm, CANCEL_SOML_TIMMER); -#endif - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - phydm_tdma_dig_timers(pDM_Odm, CANCEL_TDMA_DIG_TIMMER); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - phydm_lna_sat_chk_timers(pDM_Odm, CANCEL_LNA_SAT_CHK_TIMMER); -#ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); -#endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); -#if (BEAMFORMING_SUPPORT == 1) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); -#endif -#endif - -} - - -VOID -ODM_ReleaseAllTimers( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,RELEASE_ANTDIV_TIMMER); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - #endif -#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) -ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); -#endif - -#if (CONFIG_ADAPTIVE_SOML) - phydm_adaptive_soml_timers(pDM_Odm, RELEASE_SOML_TIMMER); -#endif - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - phydm_tdma_dig_timers(pDM_Odm, RELEASE_TDMA_DIG_TIMMER); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); -#if (BEAMFORMING_SUPPORT == 1) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); -#endif -#endif -} - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_InitAllThreads( - IN PDM_ODM_T pDM_Odm - ) -{ - #ifdef TPT_THREAD - kTPT_task_init(pDM_Odm->priv); - #endif -} - -VOID -ODM_StopAllThreads( - IN PDM_ODM_T pDM_Odm - ) -{ - #ifdef TPT_THREAD - kTPT_task_stop(pDM_Odm->priv); - #endif -} -#endif - - -#if( DM_ODM_SUPPORT_TYPE == ODM_WIN) -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter\n")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - return TRUE; -} -#elif( DM_ODM_SUPPORT_TYPE == ODM_AP) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -// need to ODM CE Platform -//move to here for ANT detection mechanism using - -#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) -u4Byte -GetPSDData( - IN PDM_ODM_T pDM_Odm, - unsigned int point, - u1Byte initial_gain_psd) -{ - //unsigned int val, rfval; - //int psd_report; - u4Byte psd_report; - - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //Debug Message - //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); - //DbgPrint("Reg908 = 0x%x\n",val); - //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); - //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); - //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); - //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", - //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); - - //Set DCO frequency index, offset=(40MHz/SamplePts)*point - ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); - - //Start PSD calculation, Reg808[22]=0->1 - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); - //Need to wait for HW PSD report - ODM_StallExecution(1000); - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); - //Read PSD report, Reg8B4[15:0] - psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; - -#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) - psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); -#else - psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); -#endif - - return psd_report; - -} -#endif - -u4Byte -odm_ConvertTo_dB( - u4Byte Value) -{ - u1Byte i; - u1Byte j; - u4Byte dB; - - Value = Value & 0xFFFF; - - for (i = 0; i < 12; i++) - { - if (Value <= dB_Invert_Table[i][7]) - { - break; - } - } - - if (i >= 12) - { - return (96); // maximum 96 dB - } - - for (j = 0; j < 8; j++) - { - if (Value <= dB_Invert_Table[i][j]) - { - break; - } - } - - dB = (i << 3) + j + 1; - - return (dB); -} - -u4Byte -odm_ConvertTo_linear( - u4Byte Value) -{ - u1Byte i; - u1Byte j; - u4Byte linear; - - /* 1dB~96dB */ - - Value = Value & 0xFF; - - i = (u1Byte)((Value - 1) >> 3); - j = (u1Byte)(Value - 1) - (i << 3); - - linear = dB_Invert_Table[i][j]; - - return (linear); -} - -// -// ODM multi-port consideration, added by Roger, 2013.10.01. -// -VOID -ODM_AsocEntry_Init( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER pLoopAdapter = GetDefaultAdapter(pDM_Odm->Adapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pLoopAdapter); - PDM_ODM_T pDM_OutSrc = &pHalData->DM_OutSrc; - u1Byte TotalAssocEntryNum = 0; - u1Byte index = 0; - u1Byte adaptercount = 0; - - ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, 0, &pLoopAdapter->MgntInfo.DefaultPort[0]); - pLoopAdapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = TotalAssocEntryNum; - - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - TotalAssocEntryNum +=1; - - while(pLoopAdapter) - { - for (index = 0; index MgntInfo.AsocEntry[index]); - pLoopAdapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = TotalAssocEntryNum+index; - } - - TotalAssocEntryNum+= index; - if(IS_HARDWARE_TYPE_8188E((pDM_Odm->Adapter))) - pLoopAdapter->RASupport = TRUE; - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - } - - RT_TRACE(COMP_INIT, DBG_LOUD, ("TotalAssocEntryNum = %d\n", TotalAssocEntryNum)); - if (TotalAssocEntryNum < (ODM_ASSOCIATE_ENTRY_NUM-1)) { - - RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n")); - for (index = TotalAssocEntryNum; index < ODM_ASSOCIATE_ENTRY_NUM; index++) - ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, index, NULL); - } -#endif -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ -void odm_dtc(PDM_ODM_T pDM_Odm) -{ -#ifdef CONFIG_DM_RESP_TXAGC - #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ - #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ - - /* RSSI vs TX power step mapping: decade TX power */ - static const u8 dtc_table_down[]={ - DTC_BASE, - (DTC_BASE+5), - (DTC_BASE+10), - (DTC_BASE+15), - (DTC_BASE+20), - (DTC_BASE+25) - }; - - /* RSSI vs TX power step mapping: increase TX power */ - static const u8 dtc_table_up[]={ - DTC_DWN_BASE, - (DTC_DWN_BASE-5), - (DTC_DWN_BASE-10), - (DTC_DWN_BASE-15), - (DTC_DWN_BASE-15), - (DTC_DWN_BASE-20), - (DTC_DWN_BASE-20), - (DTC_DWN_BASE-25), - (DTC_DWN_BASE-25), - (DTC_DWN_BASE-30), - (DTC_DWN_BASE-35) - }; - - u8 i; - u8 dtc_steps=0; - u8 sign; - u8 resp_txagc=0; - - #if 0 - /* As DIG is disabled, DTC is also disable */ - if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) - return; - #endif - - if (DTC_BASE < pDM_Odm->RSSI_Min) { - /* need to decade the CTS TX power */ - sign = 1; - for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) - break; - else - dtc_steps++; - } - } -#if 0 - else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) - { - /* needs to increase the CTS TX power */ - sign = 0; - dtc_steps = 1; - for (i=0;iRSSI_Min) || (dtc_steps>=10)) - break; - else - dtc_steps++; - } - } -#endif - else - { - sign = 0; - dtc_steps = 0; - } - - resp_txagc = dtc_steps | (sign << 4); - resp_txagc = resp_txagc | (resp_txagc << 5); - ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", - __func__, pDM_Odm->RSSI_Min, sign ? "minus" : "plus", dtc_steps)); -#endif /* CONFIG_RESP_TXAGC_ADJUST */ -} - -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - -VOID -odm_UpdatePowerTrainingState( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte score = 0; - - if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState()============>\n")); - pDM_Odm->bChangeState = FALSE; - - // Debug command - if(pDM_Odm->ForcePowerTrainingState) - { - if(pDM_Odm->ForcePowerTrainingState == 1 && !pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = TRUE; - } - else if(pDM_Odm->ForcePowerTrainingState == 2 && pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = FALSE; - } - - pDM_Odm->PT_score = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): ForcePowerTrainingState = %d\n", - pDM_Odm->ForcePowerTrainingState)); - return; - } - - if(!pDM_Odm->bLinked) - return; - - // First connect - if((pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE)) - { - pDM_Odm->PT_score = 0; - pDM_Odm->bChangeState = TRUE; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): First Connect\n")); - return; - } - - // Compute score - if(pDM_Odm->NHM_cnt_0 >= 215) - score = 2; - else if(pDM_Odm->NHM_cnt_0 >= 190) - score = 1; // unknow state - else - { - u4Byte RX_Pkt_Cnt; - - RX_Pkt_Cnt = (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM) + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK); - - if((FalseAlmCnt->Cnt_CCA_all > 31 && RX_Pkt_Cnt > 31) && (FalseAlmCnt->Cnt_CCA_all >= RX_Pkt_Cnt)) - { - if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 1)) <= FalseAlmCnt->Cnt_CCA_all) - score = 0; - else if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 2)) <= FalseAlmCnt->Cnt_CCA_all) - score = 1; - else - score = 2; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): RX_Pkt_Cnt = %d, Cnt_CCA_all = %d\n", - RX_Pkt_Cnt, FalseAlmCnt->Cnt_CCA_all)); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NumQryPhyStatusOFDM = %d, NumQryPhyStatusCCK = %d\n", - (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM), (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NHM_cnt_0 = %d, score = %d\n", - pDM_Odm->NHM_cnt_0, score)); - - // smoothing - pDM_Odm->PT_score = (score << 4) + (pDM_Odm->PT_score>>1) + (pDM_Odm->PT_score>>2); - score = (pDM_Odm->PT_score + 32) >> 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): PT_score = %d, score after smoothing = %d\n", - pDM_Odm->PT_score, score)); - - // Mode decision - if(score == 2) - { - if(pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Enable Power Training\n")); - } - else if(score == 0) - { - if(!pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Disable Power Training\n")); - } - - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; -#endif -} - - - -/*===========================================================*/ -/* The following is for compile only*/ -/*===========================================================*/ -/*#define TARGET_CHNL_NUM_2G_5G 59*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -u1Byte GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, - 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165}; - u1Byte place = chnl; - - - if (chnl > 14) { - for (place = 14; place < sizeof(channel_all); place++) { - if (channel_all[place] == chnl) - return place-13; - } - } - - return 0; -} - -#endif -/*===========================================================*/ - -VOID -phydm_NoisyDetection( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte Total_FA_Cnt, Total_CCA_Cnt; - u4Byte Score = 0, i, Score_Smooth; - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if (pDM_Odm->original_dig_restore == 0) { - Total_CCA_Cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_CCA_all_1sec; - Total_FA_Cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_all_1sec; - } else -#endif - { - Total_CCA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_CCA_all; - Total_FA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_all; - } - -/* - if( Total_FA_Cnt*16>=Total_CCA_Cnt*14 ) // 87.5 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*12 ) // 75 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*10 ) // 56.25 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*8 ) // 50 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*7 ) // 43.75 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*6 ) // 37.5 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*5 ) // 31.25% - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*4 ) // 25% - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*3 ) // 18.75% - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*2 ) // 12.5% - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*1 ) // 6.25% -*/ - for(i=0;i<=16;i++) - { - if( Total_FA_Cnt*16>=Total_CCA_Cnt*(16-i) ) - { - Score = 16-i; - break; - } - } - - // NoisyDecision_Smooth = NoisyDecision_Smooth>>1 + (Score<<3)>>1; - pDM_Odm->NoisyDecision_Smooth = (pDM_Odm->NoisyDecision_Smooth>>1) + (Score<<2); - - // Round the NoisyDecision_Smooth: +"3" comes from (2^3)/2-1 - Score_Smooth = (Total_CCA_Cnt>=300)?((pDM_Odm->NoisyDecision_Smooth+3)>>3):0; - - pDM_Odm->NoisyDecision = (Score_Smooth>=3)?1:0; -/* - switch(Score_Smooth) - { - case 0: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=0%%\n")); - break; - case 1: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=6.25%%\n")); - break; - case 2: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=12.5%%\n")); - break; - case 3: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=18.75%%\n")); - break; - case 4: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=25%%\n")); - break; - case 5: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=31.25%%\n")); - break; - case 6: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=37.5%%\n")); - break; - case 7: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=43.75%%\n")); - break; - case 8: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=50%%\n")); - break; - case 9: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=56.25%%\n")); - break; - case 10: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=62.5%%\n")); - break; - case 11: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=68.75%%\n")); - break; - case 12: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=75%%\n")); - break; - case 13: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=81.25%%\n")); - break; - case 14: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=87.5%%\n")); - break; - case 15: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=93.75%%\n")); - break; - case 16: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=100%%\n")); - break; - default: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Unknown Value!! Need Check!!\n")); - } -*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, - ("[NoisyDetection] Total_CCA_Cnt=%d, Total_FA_Cnt=%d, NoisyDecision_Smooth=%d, Score=%d, Score_Smooth=%d, pDM_Odm->NoisyDecision=%d\n", - Total_CCA_Cnt, Total_FA_Cnt, pDM_Odm->NoisyDecision_Smooth, Score, Score_Smooth, pDM_Odm->NoisyDecision)); - -} - -VOID -phydm_csi_mask_enable( - IN PVOID pDM_VOID, - IN u4Byte enable -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte reg_value = 0; - - reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0x874, BIT0, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); - } - -} - -VOID -phydm_clean_all_csi_mask( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD4c, bMaskDWord, 0); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0); - } -} - -VOID -phydm_set_csi_mask_reg( - IN PVOID pDM_VOID, - IN u4Byte tone_idx_tmp, - IN u1Byte tone_direction -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte byte_offset, bit_offset; - u4Byte target_reg; - u1Byte reg_tmp_value; - u4Byte tone_num = 64; - u4Byte tone_num_shift = 0; - u4Byte csi_mask_reg_p = 0, csi_mask_reg_n = 0; - - /* calculate real tone idx*/ - if ((tone_idx_tmp % 10) >= 5) - tone_idx_tmp += 10; - - tone_idx_tmp = (tone_idx_tmp/10); - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - tone_num = 64; - csi_mask_reg_p = 0xD40; - csi_mask_reg_n = 0xD48; - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - tone_num = 128; - csi_mask_reg_p = 0x880; - csi_mask_reg_n = 0x890; - } - - if (tone_direction == FREQ_POSITIVE) { - - if (tone_idx_tmp >= (tone_num - 1)) - tone_idx_tmp = (tone_num - 1); - - byte_offset = (u1Byte)(tone_idx_tmp >> 3); - bit_offset = (u1Byte)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_p + byte_offset; - - } else { - tone_num_shift = tone_num; - - if (tone_idx_tmp >= tone_num) - tone_idx_tmp = tone_num; - - tone_idx_tmp = tone_num - tone_idx_tmp; - - byte_offset = (u1Byte)(tone_idx_tmp >> 3); - bit_offset = (u1Byte)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_n + byte_offset; - } - - reg_tmp_value = ODM_Read1Byte(pDM_Odm, target_reg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); - reg_tmp_value |= BIT(bit_offset); - ODM_Write1Byte(pDM_Odm, target_reg, reg_tmp_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); -} - -VOID -phydm_set_nbi_reg( - IN PVOID pDM_VOID, - IN u4Byte tone_idx_tmp, - IN u4Byte bw -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ - 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ - 485, 505, 525, 555, 585, 615, 635}; /*21~27*/ - - u4Byte nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ - 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ - 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ - 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ - 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ - 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/ - - u4Byte reg_idx = 0; - u4Byte i; - u1Byte nbi_table_idx = FFT_128_TYPE; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - nbi_table_idx = FFT_128_TYPE; - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_1_SERIES) { - - nbi_table_idx = FFT_256_TYPE; - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_2_SERIES) { - - if (bw == 80) - nbi_table_idx = FFT_256_TYPE; - else /*20M, 40M*/ - nbi_table_idx = FFT_128_TYPE; - } - - if (nbi_table_idx == FFT_128_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_128; i++) { - if (tone_idx_tmp < nbi_table_128[i]) { - reg_idx = i+1; - break; - } - } - - } else if (nbi_table_idx == FFT_256_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_256; i++) { - if (tone_idx_tmp < nbi_table_256[i]) { - reg_idx = i+1; - break; - } - } - } - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, 0xc40, 0x1f000000, reg_idx); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); - /**/ - } else { - ODM_SetBBReg(pDM_Odm, 0x87c, 0xfc000, reg_idx); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); - /**/ - } -} - - -VOID -phydm_nbi_enable( - IN PVOID pDM_VOID, - IN u4Byte enable -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte reg_value = 0; - - reg_value = (enable == NBI_ENABLE) ? 1 : 0; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0xc40, BIT9, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { - ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT(28), reg_value); - if (pDM_Odm->RFType > ODM_1T1R) - ODM_SetBBReg(pDM_Odm, 0xe20, BIT(28), reg_value); - } else - ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); - } -} - -u1Byte -phydm_calculate_fc( - IN PVOID pDM_VOID, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte Second_ch, - IN OUT u4Byte *fc_in -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc = *fc_in; - u4Byte start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; - u4Byte start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; - pu4Byte p_start_ch = &(start_ch_per_40m[0]); - u4Byte num_start_channel = NUM_START_CH_40M; - u4Byte channel_offset = 0; - u4Byte i; - - /*2.4G*/ - if (channel <= 14 && channel > 0) { - - if (bw == 80) { - return SET_ERROR; - } - - fc = 2412 + (channel - 1)*5; - - if (bw == 40 && (Second_ch == PHYDM_ABOVE)) { - - if (channel >= 10) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); - return SET_ERROR; - } - fc += 10; - } else if (bw == 40 && (Second_ch == PHYDM_BELOW)) { - - if (channel <= 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); - return SET_ERROR; - } - fc -= 10; - } - } - /*5G*/ - else if (channel >= 36 && channel <= 177) { - - if (bw != 20) { - - if (bw == 40) { - num_start_channel = NUM_START_CH_40M; - p_start_ch = &(start_ch_per_40m[0]); - channel_offset = CH_OFFSET_40M; - } else if (bw == 80) { - num_start_channel = NUM_START_CH_80M; - p_start_ch = &(start_ch_per_80m[0]); - channel_offset = CH_OFFSET_80M; - } - - for (i = 0; i < num_start_channel; i++) { - - if (channel < p_start_ch[i+1]) { - channel = p_start_ch[i] + channel_offset; - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); - } - - fc = 5180 + (channel-36)*5; - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error Setting\n", channel)); - return SET_ERROR; - } - - *fc_in = fc; - - return SET_SUCCESS; -} - - -u1Byte -phydm_calculate_intf_distance( - IN PVOID pDM_VOID, - IN u4Byte bw, - IN u4Byte fc, - IN u4Byte f_interference, - IN OUT u4Byte *p_tone_idx_tmp_in -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte bw_up, bw_low; - u4Byte int_distance; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_NO_NEED; - - bw_up = fc + bw/2; - bw_low = fc - bw/2; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); - - if ((f_interference >= bw_low) && (f_interference <= bw_up)) { - - int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); - tone_idx_tmp = (int_distance<<5); /* =10*(int_distance /0.3125) */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp/10), (tone_idx_tmp%10))); - *p_tone_idx_tmp_in = tone_idx_tmp; - set_result = SET_SUCCESS; - } - - return set_result; - -} - - -u1Byte -phydm_csi_mask_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc; - u4Byte int_distance; - u1Byte tone_direction; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_SUCCESS; - - if (enable == CSI_MASK_DISABLE) { - set_result = SET_SUCCESS; - phydm_clean_all_csi_mask(pDM_Odm); - - } else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; - phydm_set_csi_mask_reg(pDM_Odm, tone_idx_tmp, tone_direction); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; - } - } - - if (set_result == SET_SUCCESS) - phydm_csi_mask_enable(pDM_Odm, enable); - else - phydm_csi_mask_enable(pDM_Odm, CSI_MASK_DISABLE); - - return set_result; -} - -u1Byte -phydm_nbi_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc; - u4Byte int_distance; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_SUCCESS; - u4Byte bw_max = 40; - - if (enable == NBI_DISABLE) - set_result = SET_SUCCESS; - - else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - phydm_set_nbi_reg(pDM_Odm, tone_idx_tmp, bw); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; - } - } - - if (set_result == SET_SUCCESS) - phydm_nbi_enable(pDM_Odm, enable); - else - phydm_nbi_enable(pDM_Odm, NBI_DISABLE); - - return set_result; -} - -VOID -phydm_api_debug( - IN PVOID pDM_VOID, - IN u4Byte function_map, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte channel = dm_value[1]; - u4Byte bw = dm_value[2]; - u4Byte f_interference = dm_value[3]; - u4Byte Second_ch = dm_value[4]; - u1Byte set_result = 0; - - /*PHYDM_API_NBI*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - if (function_map == PHYDM_API_NBI) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == NBI_ENABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, ((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((Second_ch == PHYDM_ABOVE) ? "H" : "L"))); - set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, channel, bw, f_interference, Second_ch); - - } else if (dm_value[0] == NBI_DISABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Disable NBI]\n")); - set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, channel, bw, f_interference, Second_ch); - - } else { - - set_result = SET_ERROR; - } - PHYDM_SNPRINTF((output+used, out_len-used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - - } - - /*PHYDM_CSI_MASK*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - else if (function_map == PHYDM_API_CSI_MASK) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == CSI_MASK_ENABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (channel > 14)?"Don't care":(((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); - set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, channel, bw, f_interference, Second_ch); - - } else if (dm_value[0] == CSI_MASK_DISABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Disable CSI MASK]\n")); - set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_DISABLE, channel, bw, f_interference, Second_ch); - - } else { - - set_result = SET_ERROR; - } - PHYDM_SNPRINTF((output+used, out_len-used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - } -} - - -void -phydm_receiver_blocking( - void *p_dm_void -) -{ -#ifdef CONFIG_RECEIVER_BLOCKING - PDM_ODM_T p_dm_odm= (PDM_ODM_T)p_dm_void; - u4Byte channel = *p_dm_odm->pChannel; - u1Byte bw = *p_dm_odm->pBandWidth; - u1Byte set_result = 0; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_LOUD, ("p_dm_odm->consecutive_idlel_time %d\n",p_dm_odm->consecutive_idlel_time )); - if (p_dm_odm->consecutive_idlel_time > 10 && (p_dm_odm->priv->pshare->rf_ft_var.mp_specific) == false && p_dm_odm->Adaptivity_enable == true) { - if ((bw == ODM_BW20M) && (channel == 1)) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); - } else if ((bw == ODM_BW20M) && (channel == 13)) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); - } else { - if (1) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - ODM_SetBBReg(p_dm_odm,0xc40,0x1f000000,0x1f); - } - } - } else { - if (1) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - ODM_SetBBReg(p_dm_odm,0xc40,0x1f000000,0x1f); - } - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, - ("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error")))); -#endif -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +//#include "mp_precomp.h" +#include "phydm_precomp.h" +#include "phydm.h" +const u2Byte dB_Invert_Table[12][8] = { + { 1, 1, 1, 2, 2, 2, 2, 3}, + { 3, 3, 4, 4, 4, 5, 6, 6}, + { 7, 8, 9, 10, 11, 13, 14, 16}, + { 18, 20, 22, 25, 28, 32, 35, 40}, + { 45, 50, 56, 63, 71, 79, 89, 100}, + { 112, 126, 141, 158, 178, 200, 224, 251}, + { 282, 316, 355, 398, 447, 501, 562, 631}, + { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, + { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, + { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, + { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, + { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} +}; + +const u2Byte phy_rate_table[28] = { /*20M*/ + 1, 2, 5, 11, + 6, 9, 12, 18, 24, 36, 48, 54, + 6, 13, 19, 26, 39, 52, 58, 65, /*MCS0~7*/ + 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/ +}; + + +//============================================================ +// Local Function predefine. +//============================================================ + +/* START------------COMMON INFO RELATED--------------- */ + +VOID +odm_GlobalAdapterCheck( + IN VOID + ); + +//move to odm_PowerTacking.h by YuChen + + + +VOID +odm_UpdatePowerTrainingState( + IN PDM_ODM_T pDM_Odm +); + +//============================================================ +//3 Export Interface +//============================================================ + +/*Y = 10*log(X)*/ +s4Byte +ODM_PWdB_Conversion( + IN s4Byte X, + IN u4Byte TotalBit, + IN u4Byte DecimalBit + ) +{ + s4Byte Y, integer = 0, decimal = 0; + u4Byte i; + + if(X == 0) + X = 1; // log2(x), x can't be 0 + + for(i = (TotalBit-1); i > 0; i--) + { + if(X & BIT(i)) + { + integer = i; + if(i > 0) + decimal = (X & BIT(i-1))?2:0; //decimal is 0.5dB*3=1.5dB~=2dB + break; + } + } + + Y = 3*(integer-DecimalBit)+decimal; //10*log(x)=3*log2(x), + + return Y; +} + +s4Byte +ODM_SignConversion( + IN s4Byte value, + IN u4Byte TotalBit + ) +{ + if(value&BIT(TotalBit-1)) + value -= BIT(TotalBit); + return value; +} + +void +phydm_seq_sorting( + IN PVOID pDM_VOID, + IN OUT u4Byte *p_value, + IN OUT u4Byte *rank_idx, + IN OUT u4Byte *p_idx_out, + IN u1Byte seq_length +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0 , j = 0; + u4Byte tmp_a, tmp_b; + u4Byte tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) { + rank_idx[i] = i; + /**/ + } + + for (i = 0; i < (seq_length - 1); i++) { + + for (j = 0; j < (seq_length - 1 - i); j++) { + + tmp_a = p_value[j]; + tmp_b = p_value[j+1]; + + tmp_idx_a = rank_idx[j]; + tmp_idx_b = rank_idx[j+1]; + + if (tmp_a < tmp_b) { + p_value[j] = tmp_b; + p_value[j+1] = tmp_a; + + rank_idx[j] = tmp_idx_b; + rank_idx[j+1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) { + p_idx_out[rank_idx[i]] = i+1; + /**/ + } + + + +} + +VOID +ODM_InitMpDriverStatus( + IN PDM_ODM_T pDM_Odm +) +{ +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + // Decide when compile time + #if(MP_DRIVER == 1) + pDM_Odm->mp_mode = TRUE; + #else + pDM_Odm->mp_mode = FALSE; + #endif + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + + PADAPTER Adapter = pDM_Odm->Adapter; + + // Update information every period + pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; + +#else + + prtl8192cd_priv priv = pDM_Odm->priv; + + pDM_Odm->mp_mode = (BOOLEAN)priv->pshare->rf_ft_var.mp_specific; + +#endif +} + +VOID +ODM_UpdateMpDriverStatus( + IN PDM_ODM_T pDM_Odm +) +{ +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + // Do nothing. + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + + // Update information erery period + pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; + +#else + + // Do nothing. + +#endif +} + +VOID +PHYDM_InitTRXAntennaSetting( + IN PDM_ODM_T pDM_Odm +) +{ +/*#if (RTL8814A_SUPPORT == 1)*/ + + if (pDM_Odm->SupportICType & (ODM_RTL8814A)) { + u1Byte RxAnt = 0, TxAnt = 0; + + RxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm)); + TxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_TX_PATH, pDM_Odm), ODM_BIT(BB_TX_PATH, pDM_Odm)); + pDM_Odm->TXAntStatus = (TxAnt & 0xf); + pDM_Odm->RXAntStatus = (RxAnt & 0xf); + } else if (pDM_Odm->SupportICType & (ODM_RTL8723D | ODM_RTL8821C)) { + pDM_Odm->TXAntStatus = 0x1; + pDM_Odm->RXAntStatus = 0x1; + + } +/*#endif*/ +} + +void +phydm_traffic_load_decision( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + /*---trafic load decision---*/ + pDM_Odm->curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->lastTxOkCnt; + pDM_Odm->curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->lastRxOkCnt; + pDM_Odm->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + pDM_Odm->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ + pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ + #else + pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + #endif + pDM_Odm->total_tp = pDM_Odm->tx_tp + pDM_Odm->rx_tp; + + /*[Calculate consecutive idlel time]*/ + if (pDM_Odm->total_tp == 0) + pDM_Odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + pDM_Odm->consecutive_idlel_time = 0; + + pDM_Odm->pre_TrafficLoad = pDM_Odm->TrafficLoad; + + if (pDM_Odm->curTxOkCnt > 1875000 || pDM_Odm->curRxOkCnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ + + pDM_Odm->TrafficLoad = TRAFFIC_HIGH; + /**/ + } else if (pDM_Odm->curTxOkCnt > 500000 || pDM_Odm->curRxOkCnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + + pDM_Odm->TrafficLoad = TRAFFIC_MID; + /**/ + } else if (pDM_Odm->curTxOkCnt > 100000 || pDM_Odm->curRxOkCnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + + pDM_Odm->TrafficLoad = TRAFFIC_LOW; + /**/ + } else { + + pDM_Odm->TrafficLoad = TRAFFIC_ULTRA_LOW; + /**/ + } +} + +VOID +phydm_config_ofdm_tx_path( + IN PDM_ODM_T pDM_Odm, + IN u4Byte path +) +{ + u1Byte ofdm_rx_path; + + #if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { + + if (path == PHYDM_A) { + ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x81121111); + /**/ + } else if (path == PHYDM_B) { + ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x82221222); + /**/ + } else if (path == PHYDM_AB) { + ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x83321333); + /**/ + } + + + } + #endif +} + +VOID +phydm_config_ofdm_rx_path( + IN PDM_ODM_T pDM_Odm, + IN u4Byte path +) +{ + u1Byte ofdm_rx_path = 0; + + #if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { + + if (path == PHYDM_A) { + ofdm_rx_path = 1; + /**/ + } else if (path == PHYDM_B) { + ofdm_rx_path = 2; + /**/ + } else if (path == PHYDM_AB) { + ofdm_rx_path = 3; + /**/ + } + + ODM_SetBBReg(pDM_Odm, 0xC04 , 0xff, (((ofdm_rx_path)<<4)|ofdm_rx_path)); + ODM_SetBBReg(pDM_Odm, 0xD04 , 0xf, ofdm_rx_path); + } + #endif +} + +VOID +phydm_config_cck_rx_antenna_init( + IN PDM_ODM_T pDM_Odm +) +{ + /*CCK 2R CCA parameters*/ + ODM_SetBBReg(pDM_Odm, 0xa00, BIT(15), 0x0); /*Disable antenna diversity*/ + ODM_SetBBReg(pDM_Odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ + ODM_SetBBReg(pDM_Odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ + ODM_SetBBReg(pDM_Odm, 0xa14, BIT(7), 0); /*r_en_mrc_antsel*/ + ODM_SetBBReg(pDM_Odm, 0xa20, (BIT(5) | BIT(4)), 1); /*MBC weighting*/ + + if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) { + ODM_SetBBReg(pDM_Odm, 0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/ + /**/ + } else if(pDM_Odm->SupportICType & (ODM_RTL8814A)) { + ODM_SetBBReg(pDM_Odm, 0xa84, BIT(28), 1); /*2R CCA only*/ + /**/ + } +} + +VOID +phydm_config_cck_rx_path( + IN PDM_ODM_T pDM_Odm, + IN u1Byte path, + IN u1Byte path_div_en +) +{ + u8 path_div_select = 0; + u8 cck_path[2] = {0}; + u8 en_2R_path = 0; + u8 en_2R_mrc = 0; + u8 i = 0, j =0; + u8 num_enable_path = 0; + u8 cck_mrc_max_path = 2; + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) { /*ex: PHYDM_ABCD*/ + num_enable_path++; + cck_path[j] = i; + j++; + } + if (num_enable_path >= cck_mrc_max_path) + break; + } + + if (num_enable_path > 1) { + path_div_select = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } else { + path_div_select = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } + +#if 0 + if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8197F | ODM_RTL8822B)) { + + if (path == PHYDM_A) { + path_div_select = 0; + cck_1_path = 0; + cck_2_path = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_B) { + path_div_select = 0; + cck_1_path = 1; + cck_2_path = 1; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_AB) { + path_div_select = 1; + cck_1_path = 0; + cck_2_path = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } + } else if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { + + if (path == PHYDM_A) { + path_div_select = 0; + cck_1_path = 0; + cck_2_path = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_B) { + path_div_select = 0; + cck_1_path = 1; + cck_2_path = 1; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_C) { + path_div_select = 0; + cck_1_path = 2; + cck_2_path = 2; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_D) { + path_div_select = 0; + cck_1_path = 3; + cck_2_path = 3; + en_2R_path = 0; + en_2R_mrc = 0; + } else if (path == PHYDM_AB) { + path_div_select = 1; + cck_1_path = 0; + cck_2_path = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } else if (path == PHYDM_AC) { + path_div_select = 1; + cck_1_path = 0; + cck_2_path = 2; + en_2R_path = 1; + en_2R_mrc = 1; + } else if (path == PHYDM_AD) { + path_div_select = 1; + cck_1_path = 0; + cck_2_path = 3; + en_2R_path = 1; + en_2R_mrc = 1; + } else if (path == PHYDM_BC) { + path_div_select = 1; + cck_1_path = 1; + cck_2_path = 2; + en_2R_path = 1; + en_2R_mrc = 1; + } else if (path == PHYDM_BD) { + path_div_select = 1; + cck_1_path = 1; + cck_2_path = 3; + en_2R_path = 1; + en_2R_mrc = 1; + } else if (path == PHYDM_CD) { + path_div_select = 1; + cck_1_path = 2; + cck_2_path = 3; + en_2R_path = 1; + en_2R_mrc = 1; + } + } +#endif + + ODM_SetBBReg(pDM_Odm, 0xa04, (BIT(27) | BIT(26)), cck_path[0]); /*CCK_1 input signal path*/ + ODM_SetBBReg(pDM_Odm, 0xa04, (BIT(25) | BIT(24)), cck_path[1]); /*CCK_2 input signal path*/ + ODM_SetBBReg(pDM_Odm, 0xa74, BIT(8), path_div_select); /*enable Rx path diversity*/ + ODM_SetBBReg(pDM_Odm, 0xa2c, BIT(18), en_2R_path); /*enable 2R Rx path*/ + ODM_SetBBReg(pDM_Odm, 0xa2c, BIT(22), en_2R_mrc); /*enable 2R MRC*/ +} + +VOID +phydm_config_trx_path( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte pre_support_ability; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + /* CCK */ + if (dm_value[0] == 0) { + + if (dm_value[1] == 1) { /*TX*/ + if (dm_value[2] == 1) + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); + else if (dm_value[2] == 2) + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); + else if (dm_value[2] == 3) + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); + } else if (dm_value[1] == 2) { /*RX*/ + + phydm_config_cck_rx_antenna_init(pDM_Odm); + + if (dm_value[2] == 1) { + phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); + } else if (dm_value[2] == 2) { + phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); + } else if (dm_value[2] == 3) { + if (dm_value[3] == 1) /*enable path diversity*/ + phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE); + else + phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); + } + } + } + /* OFDM */ + else if (dm_value[0] == 1) { + + if (dm_value[1] == 1) { /*TX*/ + phydm_config_ofdm_tx_path(pDM_Odm, dm_value[2]); + /**/ + } else if (dm_value[1] == 2) { /*RX*/ + phydm_config_ofdm_rx_path(pDM_Odm, dm_value[2]); + /**/ + } + } + + PHYDM_SNPRINTF((output+used, out_len-used, "PHYDM Set Path [%s] [%s] = [%s%s%s%s]\n", + (dm_value[0] == 1) ? "OFDM" : "CCK", + (dm_value[1] == 1) ? "TX" : "RX", + (dm_value[2] & 0x1)?"A":"", + (dm_value[2] & 0x2)?"B":"", + (dm_value[2] & 0x4)?"C":"", + (dm_value[2] & 0x8)?"D":"" + )); + +} + +VOID +phydm_Init_cck_setting( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value_824,value_82c; + + pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm)); + + + phydm_config_cck_rx_antenna_init(pDM_Odm); +#if 0//(RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType & (ODM_RTL8192E)) + phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE); + else +#endif + phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType & (ODM_RTL8192E)) + { + /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ + value_824 = ODM_GetBBReg(pDM_Odm, 0x824, BIT9); + value_82c = ODM_GetBBReg(pDM_Odm, 0x82c, BIT9); + + if(value_824 != value_82c) + { + ODM_SetBBReg(pDM_Odm, 0x82c , BIT9, value_824); + } + ODM_SetBBReg(pDM_Odm, 0xa80 , BIT7, value_824); + pDM_Odm->cck_agc_report_type = (BOOLEAN)value_824; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ExtLNAGain = (( %d ))\n", pDM_Odm->cck_agc_report_type, pDM_Odm->ExtLNAGain)); + } + #endif + +#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1)) + if (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723D)) { + + pDM_Odm->cck_agc_report_type = ODM_GetBBReg(pDM_Odm, 0x950, BIT11) ? 1 : 0; /*1: 4bit LNA , 0: 3bit LNA */ + + if (pDM_Odm->cck_agc_report_type != 1) { + DbgPrint("[Warning] 8703B/8723D CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); + /**/ + } + } +#endif + +#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + + if (pDM_Odm->SupportICType & (ODM_RTL8723D|ODM_RTL8822B|ODM_RTL8197F)) { + pDM_Odm->cck_new_agc = ODM_GetBBReg(pDM_Odm, 0xa9c, BIT17)?TRUE:FALSE; /*1: new agc 0: old agc*/ + } else +#endif + pDM_Odm->cck_new_agc = FALSE; + + phydm_get_cck_rssi_table_from_reg(pDM_Odm); +} + +VOID +PHYDM_InitSoftMLSetting( + IN PDM_ODM_T pDM_Odm +) +{ +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->mp_mode == FALSE) { + if (pDM_Odm->SupportICType & ODM_RTL8822B) + /*ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xd10a0000);*/ + phydm_somlrxhp_setting(pDM_Odm, TRUE); + } +#endif +} + +VOID +PHYDM_InitHwInfoByRfe( + IN PDM_ODM_T pDM_Odm +) +{ +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + phydm_init_hw_info_by_rfe_type_8822b(pDM_Odm); +#endif +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + phydm_init_hw_info_by_rfe_type_8197f(pDM_Odm); +#endif +} + +VOID +odm_CommonInfoSelfInit( + IN PDM_ODM_T pDM_Odm + ) +{ + phydm_Init_cck_setting(pDM_Odm); + pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm)); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; + + PHYDM_InitDebugSetting(pDM_Odm); +#endif + ODM_InitMpDriverStatus(pDM_Odm); + PHYDM_InitTRXAntennaSetting(pDM_Odm); + PHYDM_InitSoftMLSetting(pDM_Odm); + + pDM_Odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; + pDM_Odm->phydm_sys_up_time = 0; + + if (pDM_Odm->SupportICType & ODM_IC_1SS) + pDM_Odm->num_rf_path = 1; + else if (pDM_Odm->SupportICType & ODM_IC_2SS) + pDM_Odm->num_rf_path = 2; + else if(pDM_Odm->SupportICType & ODM_IC_3SS ) + pDM_Odm->num_rf_path = 3; + else if(pDM_Odm->SupportICType & ODM_IC_4SS ) + pDM_Odm->num_rf_path = 4; + + pDM_Odm->TxRate = 0xFF; + pDM_Odm->RSSI_Min = 0xFF; + pDM_Odm->RSSI_Min_ByPath = 0xFF; + + pDM_Odm->number_linked_client = 0; + pDM_Odm->pre_number_linked_client = 0; + pDM_Odm->number_active_client = 0; + pDM_Odm->pre_number_active_client = 0; + + pDM_Odm->lastTxOkCnt = 0; + pDM_Odm->lastRxOkCnt = 0; + pDM_Odm->tx_tp = 0; + pDM_Odm->rx_tp = 0; + pDM_Odm->total_tp = 0; + pDM_Odm->TrafficLoad = TRAFFIC_LOW; + + pDM_Odm->nbi_set_result = 0; + pDM_Odm->bInitHwInfoByRfe = FALSE; + pDM_Odm->tp_active_th = 5; + +} + +VOID +odm_CommonInfoSelfUpdate( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte EntryCnt = 0, num_active_client = 0; + u4Byte i, OneEntry_MACID = 0, ma_rx_tp = 0; + PSTA_INFO_T pEntry; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + pEntry = pDM_Odm->pODM_StaInfo[0]; + if (pMgntInfo->mAssoc) { + pEntry->bUsed = TRUE; + for (i = 0; i < 6; i++) + pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; + } else if (GetFirstClientPort(Adapter)) { + PADAPTER pClientAdapter = GetFirstClientPort(Adapter); + + pEntry->bUsed = TRUE; + for (i = 0; i < 6; i++) + pEntry->MacAddr[i] = pClientAdapter->MgntInfo.Bssid[i]; + } else { + pEntry->bUsed = FALSE; + for (i = 0; i < 6; i++) + pEntry->MacAddr[i] = 0; + } + + //STA mode is linked to AP + if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(Adapter)) + pDM_Odm->bsta_state = TRUE; + else + pDM_Odm->bsta_state = FALSE; +#endif + +/* THis variable cannot be used because it is wrong*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; + } else if (*(pDM_Odm->pBandWidth) == ODM_BW80M) { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 6; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 6; + } else + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); +#else + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; + } else + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); +#endif + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + EntryCnt++; + if(EntryCnt==1) + { + OneEntry_MACID=i; + } + + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ma_rx_tp = (pEntry->rx_byte_cnt_LowMAW)>>17; /* low moving average RX TP ( bit /sec), <<3(8bit), >>20(10^6,M)*/ + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); + + if (ma_rx_tp > ACTIVE_TP_THRESHOLD) + num_active_client++; + #endif + } + } + + if(EntryCnt == 1) + { + pDM_Odm->bOneEntryOnly = TRUE; + pDM_Odm->OneEntry_MACID=OneEntry_MACID; + pDM_Odm->one_entry_tp = ma_rx_tp; + + pDM_Odm->tp_active_occur = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", + pDM_Odm->one_entry_tp, pDM_Odm->pre_one_entry_tp)); + + if ((pDM_Odm->one_entry_tp > pDM_Odm->pre_one_entry_tp) && (pDM_Odm->pre_one_entry_tp <= 2)) { + if ((pDM_Odm->one_entry_tp - pDM_Odm->pre_one_entry_tp) > pDM_Odm->tp_active_th) { + pDM_Odm->tp_active_occur = 1; + } + } + } + else + pDM_Odm->bOneEntryOnly = FALSE; + + pDM_Odm->pre_number_linked_client = pDM_Odm->number_linked_client; + pDM_Odm->pre_number_active_client = pDM_Odm->number_active_client; + + pDM_Odm->number_linked_client = EntryCnt; + pDM_Odm->number_active_client = num_active_client; + + /* Update MP driver status*/ + ODM_UpdateMpDriverStatus(pDM_Odm); + + /*Traffic load information update*/ + phydm_traffic_load_decision(pDM_Odm); + + pDM_Odm->phydm_sys_up_time += pDM_Odm->phydm_period; +} + +VOID +odm_CommonInfoSelfReset( + IN PDM_ODM_T pDM_Odm + ) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0; +#endif +} + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +) + +{ + PVOID pStruct = NULL; +#if RTL8195A_SUPPORT + switch (Structure_Type){ + case PHYDM_FALSEALMCNT: + pStruct = &FalseAlmCnt; + break; + + case PHYDM_CFOTRACK: + pStruct = &DM_CfoTrack; + break; + + case PHYDM_ADAPTIVITY: + pStruct = &(pDM_Odm->Adaptivity); + break; + + default: + break; + } + +#else + switch (Structure_Type){ + case PHYDM_FALSEALMCNT: + pStruct = &(pDM_Odm->FalseAlmCnt); + break; + + case PHYDM_CFOTRACK: + pStruct = &(pDM_Odm->DM_CfoTrack); + break; + + case PHYDM_ADAPTIVITY: + pStruct = &(pDM_Odm->Adaptivity); + break; + + default: + break; + } + +#endif + return pStruct; +} + +VOID +odm_HWSetting( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (RTL8821A_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_RTL8821) + odm_HWSetting_8821A(pDM_Odm); +#endif + +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_hwsetting_8814a(pDM_Odm); +#endif + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + phydm_hwsetting_8822b(pDM_Odm); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + phydm_hwsetting_8197f(pDM_Odm); +#endif +} + +// +// 2011/09/21 MH Add to describe different team necessary resource allocate?? +// +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + odm_CommonInfoSelfInit(pDM_Odm); + odm_DIGInit(pDM_Odm); + Phydm_NHMCounterStatisticsInit(pDM_Odm); + Phydm_AdaptivityInit(pDM_Odm); + phydm_ra_info_init(pDM_Odm); + odm_RateAdaptiveMaskInit(pDM_Odm); + ODM_CfoTrackingInit(pDM_Odm); + ODM_EdcaTurboInit(pDM_Odm); + odm_RSSIMonitorInit(pDM_Odm); + phydm_rf_init(pDM_Odm); + odm_TXPowerTrackingInit(pDM_Odm); + odm_AntennaDiversityInit(pDM_Odm); + phydm_adaptive_soml_init(pDM_Odm); + odm_AutoChannelSelectInit(pDM_Odm); + odm_PathDiversityInit(pDM_Odm); + odm_DynamicTxPowerInit(pDM_Odm); + phydm_initRaInfo(pDM_Odm); + phydm_lna_sat_chk_init(pDM_Odm); + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + phydm_lna_sat_chk_type2_init(pDM_Odm); +#endif + +#if (PHYDM_LA_MODE_SUPPORT == 1) + ADCSmp_Init(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#ifdef BEAMFORMING_VERSION_1 + if (pHalData->BeamformingVersion == BEAMFORMING_VERSION_1) +#endif + { + phydm_Beamforming_Init(pDM_Odm); + } +#endif + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { +#if (defined(CONFIG_BB_POWER_SAVING)) + odm_DynamicBBPowerSavingInit(pDM_Odm); +#endif + +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8188E) + { + ODM_PrimaryCCA_Init(pDM_Odm); + ODM_RAInfo_Init_all(pDM_Odm); + } +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + #if (RTL8723B_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8723B) + odm_SwAntDetectInit(pDM_Odm); + #endif + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8192E) + odm_PrimaryCCA_Check_Init(pDM_Odm); + #endif + +#endif + + } + +} + +VOID +ODM_DMReset( + IN PDM_ODM_T pDM_Odm + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_AntDivReset(pDM_Odm); + phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue); +} + + +VOID +phydm_support_ability_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte pre_support_ability; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pre_support_ability = pDM_Odm->SupportAbility ; + PHYDM_SNPRINTF((output+used, out_len-used,"\n%s\n", "================================")); + if(dm_value[0] == 100) + { + PHYDM_SNPRINTF((output+used, out_len-used, "[Supportability] PhyDM Selection\n")); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + PHYDM_SNPRINTF((output+used, out_len-used, "00. (( %s ))DIG\n", ((pDM_Odm->SupportAbility & ODM_BB_DIG)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->SupportAbility & ODM_BB_RA_MASK)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_FA_CNT)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "05. (( %s ))CCK_PD\n", ((pDM_Odm->SupportAbility & ODM_BB_CCK_PD)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "08. (( %s ))PWR_TRAIN\n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->SupportAbility & ODM_BB_RATE_ADAPTIVE)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "11. (( %s ))LNA_SAT_CHK\n", ((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "12. (( %s ))LNA_SAT_CHK_TYPE2\n", ((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK_TYPE2)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "13. (( %s ))ADAPTIVITY\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "14. (( %s ))CFO_TRACKING\n", ((pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "15. (( %s ))NHM_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "16. (( %s ))PRIMARY_CCA\n", ((pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "17. (( %s ))TXBF\n", ((pDM_Odm->SupportAbility & ODM_BB_TXBF)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "18. (( %s ))DYNAMIC_ARFR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "19. (( %s ))DYNAMIC_PSD_TOOL\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_PSDTOOL)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "21. (( %s ))EARLY_MODE\n", ((pDM_Odm->SupportAbility & ODM_MAC_EARLY_MODE)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "23. (( %s ))ADAPTIVE_SOML\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVE_SOML)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_RX_GAIN_TRACK)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "26. (( %s ))RF_CALIBRATION\n", ((pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + } + /* + else if(dm_value[0] == 101) + { + pDM_Odm->SupportAbility = 0 ; + DbgPrint("Disable all SupportAbility components \n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all SupportAbility components")); + } + */ + else + { + + if(dm_value[1] == 1) //enable + { + pDM_Odm->SupportAbility |= BIT(dm_value[0]) ; + if(BIT(dm_value[0]) & ODM_BB_PATH_DIV) + { + odm_PathDiversityInit(pDM_Odm); + } + } + else if(dm_value[1] == 2) //disable + { + pDM_Odm->SupportAbility &= ~(BIT(dm_value[0])) ; + } + else + { + //DbgPrint("\n[Warning!!!] 1:enable, 2:disable \n\n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + } + PHYDM_SNPRINTF((output+used, out_len-used,"pre-SupportAbility = 0x%x\n", pre_support_ability )); + PHYDM_SNPRINTF((output+used, out_len-used,"Curr-SupportAbility = 0x%x\n", pDM_Odm->SupportAbility )); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +// +//tmp modify for LC Only +// +VOID +ODM_DMWatchdog_LPS( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_CommonInfoSelfUpdate(pDM_Odm); + odm_FalseAlarmCounterStatistics(pDM_Odm); + odm_RSSIMonitorCheck(pDM_Odm); + odm_DIGbyRSSI_LPS(pDM_Odm); + odm_CCKPacketDetectionThresh(pDM_Odm); + odm_CommonInfoSelfReset(pDM_Odm); + + if(*(pDM_Odm->pbPowerSaving)==TRUE) + return; +} +#endif +// +// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. +// You can not add any dummy function here, be care, you can only use DM structure +// to perform any new ODM_DM. +// +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + odm_CommonInfoSelfUpdate(pDM_Odm); + phydm_BasicDbgMessage(pDM_Odm); + odm_HWSetting(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + { + prtl8192cd_priv priv = pDM_Odm->priv; + if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )//if ACS running, do not do FA/CCA counter read + return; + } +#endif + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if(pDM_Odm->original_dig_restore) +#endif + { + odm_FalseAlarmCounterStatistics(pDM_Odm); + } + + phydm_NoisyDetection(pDM_Odm); + + odm_RSSIMonitorCheck(pDM_Odm); + + phydm_adaptive_soml(pDM_Odm); + + if(*(pDM_Odm->pbPowerSaving) == TRUE) + { + odm_DIGbyRSSI_LPS(pDM_Odm); + { + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); + } + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + odm_AntennaDiversity(pDM_Odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + #endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + return; + } + + Phydm_CheckAdaptivity(pDM_Odm); + odm_UpdatePowerTrainingState(pDM_Odm); + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if(pDM_Odm->original_dig_restore == 0) + phydm_tdma_dig_timer_check(pDM_Odm); + else +#endif + { + odm_DIG(pDM_Odm); + } + + Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); + + phydm_lna_sat_chk_watchdog(pDM_Odm); + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + phydm_lna_sat_type2_sm(pDM_Odm); +#endif + odm_CCKPacketDetectionThresh(pDM_Odm); + + phydm_ra_info_watchdog(pDM_Odm); + phydm_receiver_blocking(pDM_Odm); + odm_EdcaTurboCheck(pDM_Odm); + odm_PathDiversity(pDM_Odm); + ODM_CfoTracking(pDM_Odm); + odm_DynamicTxPower(pDM_Odm); + odm_AntennaDiversity(pDM_Odm); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phydm_Beamforming_Watchdog(pDM_Odm); +#endif + + phydm_rf_watchdog(pDM_Odm); + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + ODM_DynamicPrimaryCCA(pDM_Odm); +#endif + +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8192E) + odm_DynamicPrimaryCCA_Check(pDM_Odm); + #endif +#endif + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_dtc(pDM_Odm); +#endif + + odm_CommonInfoSelfReset(pDM_Odm); + +} + + +// +// Init /.. Fixed HW value. Only init time. +// +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ) +{ + // + // This section is used for init value + // + switch (CmnInfo) + { + // + // Fixed ODM value. + // + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_PLATFORM: + pDM_Odm->SupportPlatform = (u1Byte)Value; + break; + + case ODM_CMNINFO_INTERFACE: + pDM_Odm->SupportInterface = (u1Byte)Value; + break; + + case ODM_CMNINFO_MP_TEST_CHIP: + pDM_Odm->bIsMPChip= (u1Byte)Value; + break; + + case ODM_CMNINFO_IC_TYPE: + pDM_Odm->SupportICType = Value; + break; + + case ODM_CMNINFO_CUT_VER: + pDM_Odm->CutVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_FAB_VER: + pDM_Odm->FabVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_RFE_TYPE: + pDM_Odm->RFEType = (u1Byte)Value; + PHYDM_InitHwInfoByRfe(pDM_Odm); + break; + + case ODM_CMNINFO_RF_ANTENNA_TYPE: + pDM_Odm->AntDivType= (u1Byte)Value; + break; + + case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: + pDM_Odm->with_extenal_ant_switch = (u1Byte)Value; + break; + + case ODM_CMNINFO_BE_FIX_TX_ANT: + pDM_Odm->DM_FatTable.b_fix_tx_ant = (u1Byte)Value; + break; + + case ODM_CMNINFO_BOARD_TYPE: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->BoardType = (u1Byte)Value; + break; + + case ODM_CMNINFO_PACKAGE_TYPE: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->PackageType = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_LNA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->ExtLNA = (u1Byte)Value; + break; + + case ODM_CMNINFO_5G_EXT_LNA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->ExtLNA5G = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_PA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->ExtPA = (u1Byte)Value; + break; + + case ODM_CMNINFO_5G_EXT_PA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->ExtPA5G = (u1Byte)Value; + break; + + case ODM_CMNINFO_GPA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->TypeGPA = (u2Byte)Value; + break; + + case ODM_CMNINFO_APA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->TypeAPA = (u2Byte)Value; + break; + + case ODM_CMNINFO_GLNA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->TypeGLNA = (u2Byte)Value; + break; + + case ODM_CMNINFO_ALNA: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->TypeALNA = (u2Byte)Value; + break; + + case ODM_CMNINFO_EXT_TRSW: + if (!pDM_Odm->bInitHwInfoByRfe) + pDM_Odm->ExtTRSW = (u1Byte)Value; + break; + case ODM_CMNINFO_EXT_LNA_GAIN: + pDM_Odm->ExtLNAGain = (u1Byte)Value; + break; + case ODM_CMNINFO_PATCH_ID: + pDM_Odm->PatchID = (u1Byte)Value; + break; + case ODM_CMNINFO_BINHCT_TEST: + pDM_Odm->bInHctTest = (BOOLEAN)Value; + break; + case ODM_CMNINFO_BWIFI_TEST: + pDM_Odm->WIFITest = (u1Byte)Value; + break; + case ODM_CMNINFO_SMART_CONCURRENT: + pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; + break; + case ODM_CMNINFO_DOMAIN_CODE_2G: + pDM_Odm->odm_Regulation2_4G = (u1Byte)Value; + break; + case ODM_CMNINFO_DOMAIN_CODE_5G: + pDM_Odm->odm_Regulation5G = (u1Byte)Value; + break; + case ODM_CMNINFO_CONFIG_BB_RF: + pDM_Odm->ConfigBBRF = (BOOLEAN)Value; + break; + case ODM_CMNINFO_IQKFWOFFLOAD: + pDM_Odm->IQKFWOffload = (u1Byte)Value; + break; + case ODM_CMNINFO_IQKPAOFF: + pDM_Odm->RFCalibrateInfo.bIQKPAoff = (BOOLEAN )Value; + break; + case ODM_CMNINFO_REGRFKFREEENABLE: + pDM_Odm->RFCalibrateInfo.RegRfKFreeEnable = (u1Byte)Value; + break; + case ODM_CMNINFO_RFKFREEENABLE: + pDM_Odm->RFCalibrateInfo.RfKFreeEnable = (u1Byte)Value; + break; + case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: + pDM_Odm->Normalrxpath = (u1Byte)Value; + break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + pDM_Odm->DFS_RegionDomain = (u1Byte)Value; + break; +#endif + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + +} + + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_MAC_PHY_MODE: + pDM_Odm->pMacPhyMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_TX_UNI: + pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_RX_UNI: + pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_WM_MODE: + pDM_Odm->pWirelessMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BAND: + pDM_Odm->pBandType = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + pDM_Odm->pSecChOffset = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_MODE: + pDM_Odm->pSecurity = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BW: + pDM_Odm->pBandWidth = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_CHNL: + pDM_Odm->pChannel = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DMSP_GET_VALUE: + pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_BUDDY_ADAPTOR: + pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; + break; + + case ODM_CMNINFO_DMSP_IS_MASTER: + pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_SCAN: + pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_POWER_SAVING: + pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + pDM_Odm->pOnePathCCA = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DRV_STOP: + pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_PNP_IN: + pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_INIT_ON: + pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ANT_TEST: + pDM_Odm->pAntennaTest = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_NET_CLOSED: + pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_FORCED_RATE: + pDM_Odm->pForcedDataRate = (pu2Byte)pValue; + break; + + case ODM_CMNINFO_FORCED_IGI_LB: + pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_P2P_LINK: + pDM_Odm->DM_DigTable.bP2PInProcess = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_IS1ANTENNA: + pDM_Odm->pIs1Antenna = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_RFDEFAULTPATH: + pDM_Odm->pRFDefaultPath= (u1Byte *)pValue; + break; + + case ODM_CMNINFO_FCS_MODE: + pDM_Odm->pIsFcsModeEnable = (BOOLEAN *)pValue; + break; + /*add by YuChen for beamforming PhyDM*/ + case ODM_CMNINFO_HUBUSBMODE: + pDM_Odm->HubUsbMode = (u1Byte *)pValue; + break; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + pDM_Odm->pbFwDwRsvdPageInProgress = (BOOLEAN *)pValue; + break; + case ODM_CMNINFO_TX_TP: + pDM_Odm->pCurrentTxTP = (u4Byte *)pValue; + break; + case ODM_CMNINFO_RX_TP: + pDM_Odm->pCurrentRxTP = (u4Byte *)pValue; + break; + case ODM_CMNINFO_SOUNDING_SEQ: + pDM_Odm->pSoundingSeq = (u1Byte *)pValue; + break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_MASTER_ENABLE: + pDM_Odm->dfs_master_enabled = (u1Byte *)pValue; + break; +#endif + case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: + pDM_Odm->DM_FatTable.pForceTxAntByDesc = (u1Byte *)pValue; + break; + //case ODM_CMNINFO_RTSTA_AID: + // pDM_Odm->pAidMap = (u1Byte *)pValue; + // break; + + //case ODM_CMNINFO_BT_COEXIST: + // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; + + //case ODM_CMNINFO_STA_STATUS: + //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; + //break; + + //case ODM_CMNINFO_PHY_STATUS: + // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; + // break; + + //case ODM_CMNINFO_MAC_STATUS: + // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; + // break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + +} + + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_STA_STATUS: + pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; + + if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[Index])) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->AssociatedMacId] = Index; /*AssociatedMacId are unique bttween different Adapter*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->aid] = Index; + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->mac_id] = Index; + #endif + + break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + } + +} + + +// +// Update Band/CHannel/.. The values are dynamic but non-per-packet. +// +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ) +{ + // + // This init variable may be changed in run time. + // + switch (CmnInfo) + { + case ODM_CMNINFO_LINK_IN_PROGRESS: + pDM_Odm->bLinkInProcess = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + pDM_Odm->bWIFI_Display = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_LINK: + pDM_Odm->bLinked = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_STATION_STATE: + pDM_Odm->bsta_state = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_RSSI_MIN: + pDM_Odm->RSSI_Min= (u1Byte)Value; + break; + + case ODM_CMNINFO_MACID_RSSI_MIN: + pDM_Odm->macid_rssi_min = (u1Byte)Value; + break; + + case ODM_CMNINFO_RSSI_MIN_BY_PATH: + pDM_Odm->RSSI_Min_ByPath= (u1Byte)Value; + break; + + case ODM_CMNINFO_DBG_COMP: + pDM_Odm->DebugComponents = (u4Byte)Value; + break; + + case ODM_CMNINFO_DBG_LEVEL: + pDM_Odm->DebugLevel = (u4Byte)Value; + break; + case ODM_CMNINFO_RA_THRESHOLD_HIGH: + pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; + break; + + case ODM_CMNINFO_RA_THRESHOLD_LOW: + pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; + break; +#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) + // The following is for BT HS mode and BT coexist mechanism. + case ODM_CMNINFO_BT_ENABLED: + pDM_Odm->bBtEnabled = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: + pDM_Odm->bBtConnectProcess = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_HS_RSSI: + pDM_Odm->btHsRssi = (u1Byte)Value; + break; + + case ODM_CMNINFO_BT_OPERATION: + pDM_Odm->bBtHsOperation = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_LIMITED_DIG: + pDM_Odm->bBtLimitedDig = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DIG: + pDM_Odm->btHsDigVal = (u1Byte)Value; + break; + + case ODM_CMNINFO_BT_BUSY: + pDM_Odm->bBtBusy = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DISABLE_EDCA: + pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; + break; +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + case ODM_CMNINFO_VXD_LINK: + pDM_Odm->VXD_bLinked= (BOOLEAN)Value; + break; +#endif +#endif + + case ODM_CMNINFO_AP_TOTAL_NUM: + pDM_Odm->APTotalNum = (u1Byte)Value; + break; + + case ODM_CMNINFO_POWER_TRAINING: + pDM_Odm->bDisablePowerTraining = (BOOLEAN)Value; + break; + +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + pDM_Odm->DFS_RegionDomain = (u1Byte)Value; + break; +#endif + +/* + case ODM_CMNINFO_OP_MODE: + pDM_Odm->OPMode = (u1Byte)Value; + break; + + case ODM_CMNINFO_WM_MODE: + pDM_Odm->WirelessMode = (u1Byte)Value; + break; + + case ODM_CMNINFO_BAND: + pDM_Odm->BandType = (u1Byte)Value; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + pDM_Odm->SecChOffset = (u1Byte)Value; + break; + + case ODM_CMNINFO_SEC_MODE: + pDM_Odm->Security = (u1Byte)Value; + break; + + case ODM_CMNINFO_BW: + pDM_Odm->BandWidth = (u1Byte)Value; + break; + + case ODM_CMNINFO_CHNL: + pDM_Odm->Channel = (u1Byte)Value; + break; +*/ + default: + //do nothing + break; + } + + +} + +u4Byte +PHYDM_CmnInfoQuery( + IN PDM_ODM_T pDM_Odm, + IN PHYDM_INFO_QUERY_E info_type + ) +{ + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT); + + switch (info_type) { + case PHYDM_INFO_FA_OFDM: + return FalseAlmCnt->Cnt_Ofdm_fail; + + case PHYDM_INFO_FA_CCK: + return FalseAlmCnt->Cnt_Cck_fail; + + case PHYDM_INFO_FA_TOTAL: + return FalseAlmCnt->Cnt_all; + + case PHYDM_INFO_CCA_OFDM: + return FalseAlmCnt->Cnt_OFDM_CCA; + + case PHYDM_INFO_CCA_CCK: + return FalseAlmCnt->Cnt_CCK_CCA; + + case PHYDM_INFO_CCA_ALL: + return FalseAlmCnt->Cnt_CCA_all; + + case PHYDM_INFO_CRC32_OK_VHT: + return FalseAlmCnt->cnt_vht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_HT: + return FalseAlmCnt->cnt_ht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_LEGACY: + return FalseAlmCnt->cnt_ofdm_crc32_ok; + + case PHYDM_INFO_CRC32_OK_CCK: + return FalseAlmCnt->cnt_cck_crc32_ok; + + case PHYDM_INFO_CRC32_ERROR_VHT: + return FalseAlmCnt->cnt_vht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_HT: + return FalseAlmCnt->cnt_ht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_LEGACY: + return FalseAlmCnt->cnt_ofdm_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_CCK: + return FalseAlmCnt->cnt_cck_crc32_error; + + case PHYDM_INFO_EDCCA_FLAG: + return FalseAlmCnt->edcca_flag; + + case PHYDM_INFO_OFDM_ENABLE: + return FalseAlmCnt->ofdm_block_enable; + + case PHYDM_INFO_CCK_ENABLE: + return FalseAlmCnt->cck_block_enable; + + case PHYDM_INFO_DBG_PORT_0: + return FalseAlmCnt->dbg_port0; + + default: + return 0xffffffff; + + } +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ + + PADAPTER pAdapter = pDM_Odm->Adapter; +#if USE_WORKITEM + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_InitializeWorkItem( pDM_Odm, + &pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem, + (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback, + (PVOID)pAdapter, + "AntennaSwitchWorkitem"); + #endif + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + ODM_InitializeWorkItem(pDM_Odm, + &pDM_Odm->dm_sat_table.hl_smart_antenna_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, + (PVOID)pAdapter, + "hl_smart_ant_workitem"); + + ODM_InitializeWorkItem(pDM_Odm, + &pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, + (PVOID)pAdapter, + "hl_smart_ant_decision_workitem"); + #endif + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->PathDivSwitchWorkitem), + (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, + (PVOID)pAdapter, + "SWAS_WorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->CCKPathDiversityWorkitem), + (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, + (PVOID)pAdapter, + "CCKTXPathDiversityWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->MPT_DIGWorkitem), + (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback, + (PVOID)pAdapter, + "MPT_DIGWorkitem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->RaRptWorkitem), + (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback, + (PVOID)pAdapter, + "RaRptWorkitem"); + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->FastAntTrainingWorkitem), + (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, + (PVOID)pAdapter, + "FastAntTrainingWorkitem"); +#endif + +#endif /*#if USE_WORKITEM*/ + +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_EnterWorkItemCallback, + (PVOID)pAdapter, + "Txbf_EnterWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_LeaveWorkItemCallback, + (PVOID)pAdapter, + "Txbf_LeaveWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_FwNdpaWorkItemCallback, + (PVOID)pAdapter, + "Txbf_FwNdpaWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_ClkWorkItemCallback, + (PVOID)pAdapter, + "Txbf_ClkWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_RateWorkItemCallback, + (PVOID)pAdapter, + "Txbf_RateWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_StatusWorkItemCallback, + (PVOID)pAdapter, + "Txbf_StatusWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_ResetTxPathWorkItemCallback, + (PVOID)pAdapter, + "Txbf_ResetTxPathWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_GetTxRateWorkItemCallback, + (PVOID)pAdapter, + "Txbf_GetTxRateWorkItem"); +#endif + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem), + (RT_WORKITEM_CALL_BACK)phydm_pauseEDCCA_WorkItemCallback, + (PVOID)pAdapter, + "phydm_pauseEDCCAWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem), + (RT_WORKITEM_CALL_BACK)phydm_resumeEDCCA_WorkItemCallback, + (PVOID)pAdapter, + "phydm_resumeEDCCAWorkItem"); + +} + +VOID +ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ +#if USE_WORKITEM + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_FreeWorkItem(&(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem)); +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_workitem)); + ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem)); +#endif + + ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); + ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); +#endif + ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem)); + ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem)); + /*ODM_FreeWorkItem((&pDM_Odm->sbdcnt_workitem));*/ +#endif + +#if (BEAMFORMING_SUPPORT == 1) + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem)); +#endif + + ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem)); + +} +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +/* +VOID +odm_FindMinimumRSSI( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + u1Byte RSSI_Min = 0xFF; + + for(i=0; ipODM_StaInfo[i] != NULL) + if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) + { + if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) + { + RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; + } + } + } + + pDM_Odm->RSSI_Min = RSSI_Min; + +} + +VOID +odm_IsLinked( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + BOOLEAN Linked = FALSE; + + for(i=0; ipODM_StaInfo[i]) ) + { + Linked = TRUE; + break; + } + + } + + pDM_Odm->bLinked = Linked; +} +*/ + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,INIT_ANTDIV_TIMMER); +#endif + +#if (CONFIG_ADAPTIVE_SOML) + phydm_adaptive_soml_timers(pDM_Odm, INIT_SOML_TIMMER); +#endif + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + phydm_tdma_dig_timers(pDM_Odm, INIT_TDMA_DIG_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + phydm_lna_sat_chk_timers(pDM_Odm, INIT_LNA_SAT_CHK_TIMMER); + +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, + (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); +#endif +#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, + (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, + (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, + (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, + (RT_TIMER_CALL_BACK)phydm_sbd_callback, NULL, "SbdTimer"); +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer, + (RT_TIMER_CALL_BACK)halComTxbf_FwNdpaTimerCallback, NULL, "Txbf_FwNdpaTimer"); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer, + (RT_TIMER_CALL_BACK)Beamforming_SWTimerCallback, NULL, "BeamformingTimer"); +#endif +#endif +} + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // + // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in + // win7 platform. + // + HAL_ADAPTER_STS_CHK(pDM_Odm) +#endif + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,CANCEL_ANTDIV_TIMMER); +#endif + +#if (CONFIG_ADAPTIVE_SOML) + phydm_adaptive_soml_timers(pDM_Odm, CANCEL_SOML_TIMMER); +#endif + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + phydm_tdma_dig_timers(pDM_Odm, CANCEL_TDMA_DIG_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + phydm_lna_sat_chk_timers(pDM_Odm, CANCEL_LNA_SAT_CHK_TIMMER); +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); +#if (BEAMFORMING_SUPPORT == 1) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); +#endif +#endif + +} + + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,RELEASE_ANTDIV_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + #endif +#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) +ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif + +#if (CONFIG_ADAPTIVE_SOML) + phydm_adaptive_soml_timers(pDM_Odm, RELEASE_SOML_TIMMER); +#endif + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + phydm_tdma_dig_timers(pDM_Odm, RELEASE_TDMA_DIG_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); +#if (BEAMFORMING_SUPPORT == 1) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); +#endif +#endif +} + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_InitAllThreads( + IN PDM_ODM_T pDM_Odm + ) +{ + #ifdef TPT_THREAD + kTPT_task_init(pDM_Odm->priv); + #endif +} + +VOID +ODM_StopAllThreads( + IN PDM_ODM_T pDM_Odm + ) +{ + #ifdef TPT_THREAD + kTPT_task_stop(pDM_Odm->priv); + #endif +} +#endif + + +#if( DM_ODM_SUPPORT_TYPE == ODM_WIN) +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter\n")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + return TRUE; +} +#elif( DM_ODM_SUPPORT_TYPE == ODM_AP) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +// need to ODM CE Platform +//move to here for ANT detection mechanism using + +#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) +u4Byte +GetPSDData( + IN PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd) +{ + //unsigned int val, rfval; + //int psd_report; + u4Byte psd_report; + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //Debug Message + //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); + //DbgPrint("Reg908 = 0x%x\n",val); + //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); + //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); + //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); + //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", + //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); + + //Set DCO frequency index, offset=(40MHz/SamplePts)*point + ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); + + //Start PSD calculation, Reg808[22]=0->1 + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); + //Need to wait for HW PSD report + ODM_StallExecution(1000); + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); + //Read PSD report, Reg8B4[15:0] + psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; + +#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) + psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); +#else + psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); +#endif + + return psd_report; + +} +#endif + +u4Byte +odm_ConvertTo_dB( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte dB; + + Value = Value & 0xFFFF; + + for (i = 0; i < 12; i++) + { + if (Value <= dB_Invert_Table[i][7]) + { + break; + } + } + + if (i >= 12) + { + return (96); // maximum 96 dB + } + + for (j = 0; j < 8; j++) + { + if (Value <= dB_Invert_Table[i][j]) + { + break; + } + } + + dB = (i << 3) + j + 1; + + return (dB); +} + +u4Byte +odm_ConvertTo_linear( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte linear; + + /* 1dB~96dB */ + + Value = Value & 0xFF; + + i = (u1Byte)((Value - 1) >> 3); + j = (u1Byte)(Value - 1) - (i << 3); + + linear = dB_Invert_Table[i][j]; + + return (linear); +} + +// +// ODM multi-port consideration, added by Roger, 2013.10.01. +// +VOID +ODM_AsocEntry_Init( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER pLoopAdapter = GetDefaultAdapter(pDM_Odm->Adapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pLoopAdapter); + PDM_ODM_T pDM_OutSrc = &pHalData->DM_OutSrc; + u1Byte TotalAssocEntryNum = 0; + u1Byte index = 0; + u1Byte adaptercount = 0; + + ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, 0, &pLoopAdapter->MgntInfo.DefaultPort[0]); + pLoopAdapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = TotalAssocEntryNum; + + adaptercount += 1; + RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + TotalAssocEntryNum +=1; + + while(pLoopAdapter) + { + for (index = 0; index MgntInfo.AsocEntry[index]); + pLoopAdapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = TotalAssocEntryNum+index; + } + + TotalAssocEntryNum+= index; + if(IS_HARDWARE_TYPE_8188E((pDM_Odm->Adapter))) + pLoopAdapter->RASupport = TRUE; + adaptercount += 1; + RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } + + RT_TRACE(COMP_INIT, DBG_LOUD, ("TotalAssocEntryNum = %d\n", TotalAssocEntryNum)); + if (TotalAssocEntryNum < (ODM_ASSOCIATE_ENTRY_NUM-1)) { + + RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n")); + for (index = TotalAssocEntryNum; index < ODM_ASSOCIATE_ENTRY_NUM; index++) + ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, index, NULL); + } +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ +void odm_dtc(PDM_ODM_T pDM_Odm) +{ +#ifdef CONFIG_DM_RESP_TXAGC + #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ + #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ + + /* RSSI vs TX power step mapping: decade TX power */ + static const u8 dtc_table_down[]={ + DTC_BASE, + (DTC_BASE+5), + (DTC_BASE+10), + (DTC_BASE+15), + (DTC_BASE+20), + (DTC_BASE+25) + }; + + /* RSSI vs TX power step mapping: increase TX power */ + static const u8 dtc_table_up[]={ + DTC_DWN_BASE, + (DTC_DWN_BASE-5), + (DTC_DWN_BASE-10), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-30), + (DTC_DWN_BASE-35) + }; + + u8 i; + u8 dtc_steps=0; + u8 sign; + u8 resp_txagc=0; + + #if 0 + /* As DIG is disabled, DTC is also disable */ + if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) + return; + #endif + + if (DTC_BASE < pDM_Odm->RSSI_Min) { + /* need to decade the CTS TX power */ + sign = 1; + for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) + break; + else + dtc_steps++; + } + } +#if 0 + else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) + { + /* needs to increase the CTS TX power */ + sign = 0; + dtc_steps = 1; + for (i=0;iRSSI_Min) || (dtc_steps>=10)) + break; + else + dtc_steps++; + } + } +#endif + else + { + sign = 0; + dtc_steps = 0; + } + + resp_txagc = dtc_steps | (sign << 4); + resp_txagc = resp_txagc | (resp_txagc << 5); + ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", + __func__, pDM_Odm->RSSI_Min, sign ? "minus" : "plus", dtc_steps)); +#endif /* CONFIG_RESP_TXAGC_ADJUST */ +} + +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + +VOID +odm_UpdatePowerTrainingState( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u4Byte score = 0; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState()============>\n")); + pDM_Odm->bChangeState = FALSE; + + // Debug command + if(pDM_Odm->ForcePowerTrainingState) + { + if(pDM_Odm->ForcePowerTrainingState == 1 && !pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = TRUE; + } + else if(pDM_Odm->ForcePowerTrainingState == 2 && pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = FALSE; + } + + pDM_Odm->PT_score = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): ForcePowerTrainingState = %d\n", + pDM_Odm->ForcePowerTrainingState)); + return; + } + + if(!pDM_Odm->bLinked) + return; + + // First connect + if((pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE)) + { + pDM_Odm->PT_score = 0; + pDM_Odm->bChangeState = TRUE; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): First Connect\n")); + return; + } + + // Compute score + if(pDM_Odm->NHM_cnt_0 >= 215) + score = 2; + else if(pDM_Odm->NHM_cnt_0 >= 190) + score = 1; // unknow state + else + { + u4Byte RX_Pkt_Cnt; + + RX_Pkt_Cnt = (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM) + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK); + + if((FalseAlmCnt->Cnt_CCA_all > 31 && RX_Pkt_Cnt > 31) && (FalseAlmCnt->Cnt_CCA_all >= RX_Pkt_Cnt)) + { + if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 1)) <= FalseAlmCnt->Cnt_CCA_all) + score = 0; + else if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 2)) <= FalseAlmCnt->Cnt_CCA_all) + score = 1; + else + score = 2; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): RX_Pkt_Cnt = %d, Cnt_CCA_all = %d\n", + RX_Pkt_Cnt, FalseAlmCnt->Cnt_CCA_all)); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NumQryPhyStatusOFDM = %d, NumQryPhyStatusCCK = %d\n", + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM), (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NHM_cnt_0 = %d, score = %d\n", + pDM_Odm->NHM_cnt_0, score)); + + // smoothing + pDM_Odm->PT_score = (score << 4) + (pDM_Odm->PT_score>>1) + (pDM_Odm->PT_score>>2); + score = (pDM_Odm->PT_score + 32) >> 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): PT_score = %d, score after smoothing = %d\n", + pDM_Odm->PT_score, score)); + + // Mode decision + if(score == 2) + { + if(pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Enable Power Training\n")); + } + else if(score == 0) + { + if(!pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Disable Power Training\n")); + } + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; +#endif +} + + + +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ +/*#define TARGET_CHNL_NUM_2G_5G 59*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +u1Byte GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, + 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165}; + u1Byte place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place-13; + } + } + + return 0; +} + +#endif +/*===========================================================*/ + +VOID +phydm_NoisyDetection( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte Total_FA_Cnt, Total_CCA_Cnt; + u4Byte Score = 0, i, Score_Smooth; + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if (pDM_Odm->original_dig_restore == 0) { + Total_CCA_Cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_CCA_all_1sec; + Total_FA_Cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_all_1sec; + } else +#endif + { + Total_CCA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_CCA_all; + Total_FA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_all; + } + +/* + if( Total_FA_Cnt*16>=Total_CCA_Cnt*14 ) // 87.5 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*12 ) // 75 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*10 ) // 56.25 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*8 ) // 50 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*7 ) // 43.75 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*6 ) // 37.5 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*5 ) // 31.25% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*4 ) // 25% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*3 ) // 18.75% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*2 ) // 12.5% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*1 ) // 6.25% +*/ + for(i=0;i<=16;i++) + { + if( Total_FA_Cnt*16>=Total_CCA_Cnt*(16-i) ) + { + Score = 16-i; + break; + } + } + + // NoisyDecision_Smooth = NoisyDecision_Smooth>>1 + (Score<<3)>>1; + pDM_Odm->NoisyDecision_Smooth = (pDM_Odm->NoisyDecision_Smooth>>1) + (Score<<2); + + // Round the NoisyDecision_Smooth: +"3" comes from (2^3)/2-1 + Score_Smooth = (Total_CCA_Cnt>=300)?((pDM_Odm->NoisyDecision_Smooth+3)>>3):0; + + pDM_Odm->NoisyDecision = (Score_Smooth>=3)?1:0; +/* + switch(Score_Smooth) + { + case 0: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=0%%\n")); + break; + case 1: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=6.25%%\n")); + break; + case 2: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=12.5%%\n")); + break; + case 3: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=18.75%%\n")); + break; + case 4: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=25%%\n")); + break; + case 5: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=31.25%%\n")); + break; + case 6: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=37.5%%\n")); + break; + case 7: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=43.75%%\n")); + break; + case 8: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=50%%\n")); + break; + case 9: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=56.25%%\n")); + break; + case 10: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=62.5%%\n")); + break; + case 11: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=68.75%%\n")); + break; + case 12: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=75%%\n")); + break; + case 13: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=81.25%%\n")); + break; + case 14: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=87.5%%\n")); + break; + case 15: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=93.75%%\n")); + break; + case 16: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=100%%\n")); + break; + default: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Unknown Value!! Need Check!!\n")); + } +*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, + ("[NoisyDetection] Total_CCA_Cnt=%d, Total_FA_Cnt=%d, NoisyDecision_Smooth=%d, Score=%d, Score_Smooth=%d, pDM_Odm->NoisyDecision=%d\n", + Total_CCA_Cnt, Total_FA_Cnt, pDM_Odm->NoisyDecision_Smooth, Score, Score_Smooth, pDM_Odm->NoisyDecision)); + +} + +VOID +phydm_csi_mask_enable( + IN PVOID pDM_VOID, + IN u4Byte enable +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte reg_value = 0; + + reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, reg_value); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); + + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + ODM_SetBBReg(pDM_Odm, 0x874, BIT0, reg_value); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); + } + +} + +VOID +phydm_clean_all_csi_mask( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0xD4c, bMaskDWord, 0); + + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0); + } +} + +VOID +phydm_set_csi_mask_reg( + IN PVOID pDM_VOID, + IN u4Byte tone_idx_tmp, + IN u1Byte tone_direction +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte byte_offset, bit_offset; + u4Byte target_reg; + u1Byte reg_tmp_value; + u4Byte tone_num = 64; + u4Byte tone_num_shift = 0; + u4Byte csi_mask_reg_p = 0, csi_mask_reg_n = 0; + + /* calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp/10); + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + tone_num = 64; + csi_mask_reg_p = 0xD40; + csi_mask_reg_n = 0xD48; + + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + tone_num = 128; + csi_mask_reg_p = 0x880; + csi_mask_reg_n = 0x890; + } + + if (tone_direction == FREQ_POSITIVE) { + + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + + byte_offset = (u1Byte)(tone_idx_tmp >> 3); + bit_offset = (u1Byte)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_p + byte_offset; + + } else { + tone_num_shift = tone_num; + + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = tone_num - tone_idx_tmp; + + byte_offset = (u1Byte)(tone_idx_tmp >> 3); + bit_offset = (u1Byte)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_n + byte_offset; + } + + reg_tmp_value = ODM_Read1Byte(pDM_Odm, target_reg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); + reg_tmp_value |= BIT(bit_offset); + ODM_Write1Byte(pDM_Odm, target_reg, reg_tmp_value); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); +} + +VOID +phydm_set_nbi_reg( + IN PVOID pDM_VOID, + IN u4Byte tone_idx_tmp, + IN u4Byte bw +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ + 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ + 485, 505, 525, 555, 585, 615, 635}; /*21~27*/ + + u4Byte nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ + 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ + 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ + 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ + 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ + 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/ + + u4Byte reg_idx = 0; + u4Byte i; + u1Byte nbi_table_idx = FFT_128_TYPE; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + nbi_table_idx = FFT_128_TYPE; + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_1_SERIES) { + + nbi_table_idx = FFT_256_TYPE; + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_2_SERIES) { + + if (bw == 80) + nbi_table_idx = FFT_256_TYPE; + else /*20M, 40M*/ + nbi_table_idx = FFT_128_TYPE; + } + + if (nbi_table_idx == FFT_128_TYPE) { + + for (i = 0; i < NBI_TABLE_SIZE_128; i++) { + if (tone_idx_tmp < nbi_table_128[i]) { + reg_idx = i+1; + break; + } + } + + } else if (nbi_table_idx == FFT_256_TYPE) { + + for (i = 0; i < NBI_TABLE_SIZE_256; i++) { + if (tone_idx_tmp < nbi_table_256[i]) { + reg_idx = i+1; + break; + } + } + } + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, 0xc40, 0x1f000000, reg_idx); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); + /**/ + } else { + ODM_SetBBReg(pDM_Odm, 0x87c, 0xfc000, reg_idx); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); + /**/ + } +} + + +VOID +phydm_nbi_enable( + IN PVOID pDM_VOID, + IN u4Byte enable +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte reg_value = 0; + + reg_value = (enable == NBI_ENABLE) ? 1 : 0; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + ODM_SetBBReg(pDM_Odm, 0xc40, BIT9, reg_value); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); + + } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { + ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT(28), reg_value); + if (pDM_Odm->RFType > ODM_1T1R) + ODM_SetBBReg(pDM_Odm, 0xe20, BIT(28), reg_value); + } else + ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); + } +} + +u1Byte +phydm_calculate_fc( + IN PVOID pDM_VOID, + IN u4Byte channel, + IN u4Byte bw, + IN u4Byte Second_ch, + IN OUT u4Byte *fc_in +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte fc = *fc_in; + u4Byte start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; + u4Byte start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; + pu4Byte p_start_ch = &(start_ch_per_40m[0]); + u4Byte num_start_channel = NUM_START_CH_40M; + u4Byte channel_offset = 0; + u4Byte i; + + /*2.4G*/ + if (channel <= 14 && channel > 0) { + + if (bw == 80) { + return SET_ERROR; + } + + fc = 2412 + (channel - 1)*5; + + if (bw == 40 && (Second_ch == PHYDM_ABOVE)) { + + if (channel >= 10) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); + return SET_ERROR; + } + fc += 10; + } else if (bw == 40 && (Second_ch == PHYDM_BELOW)) { + + if (channel <= 2) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); + return SET_ERROR; + } + fc -= 10; + } + } + /*5G*/ + else if (channel >= 36 && channel <= 177) { + + if (bw != 20) { + + if (bw == 40) { + num_start_channel = NUM_START_CH_40M; + p_start_ch = &(start_ch_per_40m[0]); + channel_offset = CH_OFFSET_40M; + } else if (bw == 80) { + num_start_channel = NUM_START_CH_80M; + p_start_ch = &(start_ch_per_80m[0]); + channel_offset = CH_OFFSET_80M; + } + + for (i = 0; i < num_start_channel; i++) { + + if (channel < p_start_ch[i+1]) { + channel = p_start_ch[i] + channel_offset; + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); + } + + fc = 5180 + (channel-36)*5; + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error Setting\n", channel)); + return SET_ERROR; + } + + *fc_in = fc; + + return SET_SUCCESS; +} + + +u1Byte +phydm_calculate_intf_distance( + IN PVOID pDM_VOID, + IN u4Byte bw, + IN u4Byte fc, + IN u4Byte f_interference, + IN OUT u4Byte *p_tone_idx_tmp_in +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte bw_up, bw_low; + u4Byte int_distance; + u4Byte tone_idx_tmp; + u1Byte set_result = SET_NO_NEED; + + bw_up = fc + bw/2; + bw_low = fc - bw/2; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); + + if ((f_interference >= bw_low) && (f_interference <= bw_up)) { + + int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); + tone_idx_tmp = (int_distance<<5); /* =10*(int_distance /0.3125) */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp/10), (tone_idx_tmp%10))); + *p_tone_idx_tmp_in = tone_idx_tmp; + set_result = SET_SUCCESS; + } + + return set_result; + +} + + +u1Byte +phydm_csi_mask_setting( + IN PVOID pDM_VOID, + IN u4Byte enable, + IN u4Byte channel, + IN u4Byte bw, + IN u4Byte f_interference, + IN u4Byte Second_ch +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte fc; + u4Byte int_distance; + u1Byte tone_direction; + u4Byte tone_idx_tmp; + u1Byte set_result = SET_SUCCESS; + + if (enable == CSI_MASK_DISABLE) { + set_result = SET_SUCCESS; + phydm_clean_all_csi_mask(pDM_Odm); + + } else { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); + + /*calculate fc*/ + if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) + set_result = SET_ERROR; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + + tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; + phydm_set_csi_mask_reg(pDM_Odm, tone_idx_tmp, tone_direction); + set_result = SET_SUCCESS; + } else + set_result = SET_NO_NEED; + } + } + + if (set_result == SET_SUCCESS) + phydm_csi_mask_enable(pDM_Odm, enable); + else + phydm_csi_mask_enable(pDM_Odm, CSI_MASK_DISABLE); + + return set_result; +} + +u1Byte +phydm_nbi_setting( + IN PVOID pDM_VOID, + IN u4Byte enable, + IN u4Byte channel, + IN u4Byte bw, + IN u4Byte f_interference, + IN u4Byte Second_ch +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte fc; + u4Byte int_distance; + u4Byte tone_idx_tmp; + u1Byte set_result = SET_SUCCESS; + u4Byte bw_max = 40; + + if (enable == NBI_DISABLE) + set_result = SET_SUCCESS; + + else { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); + + /*calculate fc*/ + if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) + set_result = SET_ERROR; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + + phydm_set_nbi_reg(pDM_Odm, tone_idx_tmp, bw); + set_result = SET_SUCCESS; + } else + set_result = SET_NO_NEED; + } + } + + if (set_result == SET_SUCCESS) + phydm_nbi_enable(pDM_Odm, enable); + else + phydm_nbi_enable(pDM_Odm, NBI_DISABLE); + + return set_result; +} + +VOID +phydm_api_debug( + IN PVOID pDM_VOID, + IN u4Byte function_map, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + u4Byte channel = dm_value[1]; + u4Byte bw = dm_value[2]; + u4Byte f_interference = dm_value[3]; + u4Byte Second_ch = dm_value[4]; + u1Byte set_result = 0; + + /*PHYDM_API_NBI*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + if (function_map == PHYDM_API_NBI) { + + if (dm_value[0] == 100) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + return; + + } else if (dm_value[0] == NBI_ENABLE) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, ((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((Second_ch == PHYDM_ABOVE) ? "H" : "L"))); + set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, channel, bw, f_interference, Second_ch); + + } else if (dm_value[0] == NBI_DISABLE) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[Disable NBI]\n")); + set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, channel, bw, f_interference, Second_ch); + + } else { + + set_result = SET_ERROR; + } + PHYDM_SNPRINTF((output+used, out_len-used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + + } + + /*PHYDM_CSI_MASK*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + else if (function_map == PHYDM_API_CSI_MASK) { + + if (dm_value[0] == 100) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + return; + + } else if (dm_value[0] == CSI_MASK_ENABLE) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (channel > 14)?"Don't care":(((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); + set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, channel, bw, f_interference, Second_ch); + + } else if (dm_value[0] == CSI_MASK_DISABLE) { + + PHYDM_SNPRINTF((output+used, out_len-used, "[Disable CSI MASK]\n")); + set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_DISABLE, channel, bw, f_interference, Second_ch); + + } else { + + set_result = SET_ERROR; + } + PHYDM_SNPRINTF((output+used, out_len-used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + } +} + + +void +phydm_receiver_blocking( + void *p_dm_void +) +{ +#ifdef CONFIG_RECEIVER_BLOCKING + PDM_ODM_T p_dm_odm= (PDM_ODM_T)p_dm_void; + u4Byte channel = *p_dm_odm->pChannel; + u1Byte bw = *p_dm_odm->pBandWidth; + u1Byte set_result = 0; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_LOUD, ("p_dm_odm->consecutive_idlel_time %d\n",p_dm_odm->consecutive_idlel_time )); + if (p_dm_odm->consecutive_idlel_time > 10 && (p_dm_odm->priv->pshare->rf_ft_var.mp_specific) == false && p_dm_odm->Adaptivity_enable == true) { + if ((bw == ODM_BW20M) && (channel == 1)) { + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); + } else if ((bw == ODM_BW20M) && (channel == 13)) { + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); + } else { + if (1) { + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); + ODM_SetBBReg(p_dm_odm,0xc40,0x1f000000,0x1f); + } + } + } else { + if (1) { + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); + ODM_SetBBReg(p_dm_odm,0xc40,0x1f000000,0x1f); + } + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, + ("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error")))); +#endif +} + diff --git a/package/kernel/rtl8192cd/phydm/phydm.h b/package/kernel/rtl8192cd/phydm/phydm.h index 69a7bc00d6a..90bf240ed33 100644 --- a/package/kernel/rtl8192cd/phydm/phydm.h +++ b/package/kernel/rtl8192cd/phydm/phydm.h @@ -1,1533 +1,1533 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __HALDMOUTSRC_H__ -#define __HALDMOUTSRC_H__ - -//============================================================ -// include files -//============================================================ -#include "phydm_pre_define.h" -#include "phydm_dig.h" -#include "phydm_edcaturbocheck.h" -#include "phydm_pathdiv.h" -#include "phydm_antdiv.h" -#include "phydm_antdect.h" -#include "phydm_soml.h" -#include "phydm_dynamicbbpowersaving.h" -#include "phydm_rainfo.h" -#include "phydm_dynamictxpower.h" -#include "phydm_cfotracking.h" -#include "phydm_acs.h" -#include "phydm_adaptivity.h" -#include "phydm_iqk.h" -#include "phydm_dfs.h" -#include "phydm_ccx.h" -#include "txbf/phydm_hal_txbf_api.h" -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) -#include "phydm_beamforming.h" -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#include "halphyrf_ap.h" -#include "phydm_adc_sampling.h" -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#include "halphyrf_ce.h" -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -#include "halphyrf_win.h" -#endif -#include "phydm_noisemonitor.h" - -//============================================================ -// Definition -//============================================================ -// -// 2011/09/22 MH Define all team supprt ability. -// - -/* Traffic load decision */ -#define TRAFFIC_ULTRA_LOW 1 -#define TRAFFIC_LOW 2 -#define TRAFFIC_MID 3 -#define TRAFFIC_HIGH 4 - -#define NONE 0 - -/*NBI API------------------------------------*/ -#define NBI_ENABLE 1 -#define NBI_DISABLE 2 - -#define NBI_TABLE_SIZE_128 27 -#define NBI_TABLE_SIZE_256 59 - -#define NUM_START_CH_80M 7 -#define NUM_START_CH_40M 14 - -#define CH_OFFSET_40M 2 -#define CH_OFFSET_80M 6 - -/*CSI MASK API------------------------------------*/ -#define CSI_MASK_ENABLE 1 -#define CSI_MASK_DISABLE 2 - -/*------------------------------------------------*/ - -#define FFT_128_TYPE 1 -#define FFT_256_TYPE 2 - -#define SET_SUCCESS 1 -#define SET_ERROR 2 -#define SET_NO_NEED 3 - -#define FREQ_POSITIVE 1 -#define FREQ_NEGATIVE 2 - - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#define PHYDM_WATCH_DOG_PERIOD 1 -#else -#define PHYDM_WATCH_DOG_PERIOD 2 -#endif - -#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) -#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) -#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) - -#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) -#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) - -#define BYTE_2_DWORD(B3, B2, B1, B0) ((B3 << 24) | (B2 << 16) | (B1 << 8) | B0) -#define BIT_2_BYTE(B3, B2, B1, B0) ((B3 << 3) | (B2 << 2) | (B1 << 1) | B0) - -//============================================================ -// structure and define -//============================================================ - -// -// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. -// We need to remove to other position??? -// -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) -typedef struct rtl8192cd_priv { - u1Byte temp; - -}rtl8192cd_priv, *prtl8192cd_priv; -#endif - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -typedef struct _ADAPTER{ - u1Byte temp; - #ifdef AP_BUILD_WORKAROUND - HAL_DATA_TYPE* temp2; - prtl8192cd_priv priv; - #endif -}ADAPTER, *PADAPTER; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -typedef struct _WLAN_STA{ - u1Byte temp; -} WLAN_STA, *PRT_WLAN_STA; - -#endif - -typedef struct _Dynamic_Primary_CCA{ - u1Byte PriCCA_flag; - u1Byte intf_flag; - u1Byte intf_type; - u1Byte DupRTS_flag; - u1Byte Monitor_flag; - u1Byte CH_offset; - u1Byte MF_state; -}Pri_CCA_T, *pPri_CCA_T; - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef ADSL_AP_BUILD_WORKAROUND - #define MAX_TOLERANCE 5 - #define IQK_DELAY_TIME 1 /*ms*/ - #endif -#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ - -#define DM_Type_ByFW 0 -#define DM_Type_ByDriver 1 - -// -// Declare for common info -// - -#define IQK_THRESHOLD 8 -#define DPK_THRESHOLD 4 - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -__PACK typedef struct _ODM_Phy_Status_Info_ -{ - u1Byte RxPWDBAll; - u1Byte SignalQuality; /* in 0-100 index. */ - u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ - s1Byte RxMIMOSignalQuality[4]; /* EVM */ - u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - s1Byte RxSNR[4]; /* per-path's SNR */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte RxCount:2; /* RX path counter---*/ - u1Byte BandWidth:2; - u1Byte rxsc:4; /* sub-channel---*/ -#else - u1Byte BandWidth; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; /* BF packet---*/ -#endif -} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; - -typedef struct _ODM_Phy_Status_Info_Append_ -{ - u1Byte MAC_CRC32; - -}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; - -#else - -typedef struct _ODM_Phy_Status_Info_ -{ - // - // Be care, if you want to add any element please insert between - // RxPWDBAll & SignalStrength. - // -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPWDBAll; -#else - u1Byte RxPWDBAll; -#endif - u1Byte SignalQuality; /* in 0-100 index. */ - s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ - u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ - s2Byte Cfo_short[4]; /* per-path's Cfo_short */ - s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ - s1Byte RxPower; /* in dBm Translate from PWdB */ - s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u1Byte BTRxRSSIPercentage; - u1Byte SignalStrength; /* in 0-100 index. */ - s1Byte RxPwr[4]; /* per-path's pwdb */ - s1Byte RxSNR[4]; /* per-path's SNR */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte RxCount:2; /* RX path counter---*/ - u1Byte BandWidth:2; - u1Byte rxsc:4; /* sub-channel---*/ -#else - u1Byte BandWidth; -#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte btCoexPwrAdjust; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; /* BF packet---*/ -#endif -}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; -#endif - -typedef struct _ODM_Per_Pkt_Info_ -{ - //u1Byte Rate; - u1Byte DataRate; - u1Byte StationID; - BOOLEAN bPacketMatchBSSID; - BOOLEAN bPacketToSelf; - BOOLEAN bPacketBeacon; - BOOLEAN bToSelf; -}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; - - -typedef struct _ODM_Phy_Dbg_Info_ -{ - //ODM Write,debug info - s1Byte RxSNRdB[4]; - u4Byte NumQryPhyStatus; - u4Byte NumQryPhyStatusCCK; - u4Byte NumQryPhyStatusOFDM; -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u4Byte NumQryMuPkt; - u4Byte NumQryBfPkt; - u4Byte NumQryMuVhtPkt[40]; - u4Byte NumQryVhtPkt[40]; -#endif - u1Byte NumQryBeaconPkt; - //Others - s4Byte RxEVM[4]; - -}ODM_PHY_DBG_INFO_T; - - -typedef struct _ODM_Mac_Status_Info_ -{ - u1Byte test; - -}ODM_MAC_INFO; - -// -// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T -// Please declare below ODM relative info in your STA info structure. -// -#if 1 -typedef struct _ODM_STA_INFO{ - // Driver Write - BOOLEAN bUsed; // record the sta status link or not? - //u1Byte WirelessMode; // - u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E - - // ODM Write - //1 PHY_STATUS_INFO - u1Byte RSSI_Path[4]; // - u1Byte RSSI_Ave; - u1Byte RXEVM[4]; - u1Byte RXSNR[4]; - - // ODM Write - //1 TX_INFO (may changed by IC) - //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. -#if 0 - u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit - u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit - u1Byte ANTSEL_C; //only in Jagar: 4bit - u1Byte ANTSEL_D; //only in Jagar: 4bit - u1Byte TX_ANTL; //not in Jagar: 2bit - u1Byte TX_ANT_HT; //not in Jagar: 2bit - u1Byte TX_ANT_CCK; //not in Jagar: 2bit - u1Byte TXAGC_A; //not in Jagar: 4bit - u1Byte TXAGC_B; //not in Jagar: 4bit - u1Byte TXPWR_OFFSET; //only in Jagar: 3bit - u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK -#endif - - // - // Please use compile flag to disabe the strcutrue for other IC except 88E. - // Move To lower layer. - // - // ODM Write Wilson will handle this part(said by Luke.Lee) - //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. -#if 0 - //1 For 88E RA (don't redefine the naming) - u1Byte rate_id; - u1Byte rate_SGI; - u1Byte rssi_sta_ra; - u1Byte SGI_enable; - u1Byte Decision_rate; - u1Byte Pre_rate; - u1Byte Active; - - // Driver write Wilson handle. - //1 TX_RPT (don't redefine the naming) - u2Byte RTY[4]; // ??? - u2Byte TOTAL; // ??? - u2Byte DROP; // ??? - // - // Please use compile flag to disabe the strcutrue for other IC except 88E. - // -#endif - -}ODM_STA_INFO_T, *PODM_STA_INFO_T; -#endif - -// -// 2011/10/20 MH Define Common info enum for all team. -// -typedef enum _ODM_Common_Info_Definition -{ -//-------------REMOVED CASE-----------// - //ODM_CMNINFO_CCK_HP, - //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? - //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E - //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E -//-------------REMOVED CASE-----------// - - // - // Fixed value: - // - - //-----------HOOK BEFORE REG INIT-----------// - ODM_CMNINFO_PLATFORM = 0, - ODM_CMNINFO_ABILITY, // ODM_ABILITY_E - ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E - ODM_CMNINFO_MP_TEST_CHIP, - ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E - ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E - ODM_CMNINFO_FAB_VER, // ODM_FAB_E - ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? - ODM_CMNINFO_RFE_TYPE, - ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E - ODM_CMNINFO_PACKAGE_TYPE, - ODM_CMNINFO_EXT_LNA, // TRUE - ODM_CMNINFO_5G_EXT_LNA, - ODM_CMNINFO_EXT_PA, - ODM_CMNINFO_5G_EXT_PA, - ODM_CMNINFO_GPA, - ODM_CMNINFO_APA, - ODM_CMNINFO_GLNA, - ODM_CMNINFO_ALNA, - ODM_CMNINFO_EXT_TRSW, - ODM_CMNINFO_EXT_LNA_GAIN, - ODM_CMNINFO_PATCH_ID, //CUSTOMER ID - ODM_CMNINFO_BINHCT_TEST, - ODM_CMNINFO_BWIFI_TEST, - ODM_CMNINFO_SMART_CONCURRENT, - ODM_CMNINFO_CONFIG_BB_RF, - ODM_CMNINFO_DOMAIN_CODE_2G, - ODM_CMNINFO_DOMAIN_CODE_5G, - ODM_CMNINFO_IQKFWOFFLOAD, - ODM_CMNINFO_IQKPAOFF, - ODM_CMNINFO_HUBUSBMODE, - ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, - ODM_CMNINFO_TX_TP, - ODM_CMNINFO_RX_TP, - ODM_CMNINFO_SOUNDING_SEQ, - ODM_CMNINFO_REGRFKFREEENABLE, - ODM_CMNINFO_RFKFREEENABLE, - ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, - //-----------HOOK BEFORE REG INIT-----------// - - - // - // Dynamic value: - // -//--------- POINTER REFERENCE-----------// - ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E - ODM_CMNINFO_TX_UNI, - ODM_CMNINFO_RX_UNI, - ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E - ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E - ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E - ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E - ODM_CMNINFO_BW, // ODM_BW_E - ODM_CMNINFO_CHNL, - ODM_CMNINFO_FORCED_RATE, - - ODM_CMNINFO_DMSP_GET_VALUE, - ODM_CMNINFO_BUDDY_ADAPTOR, - ODM_CMNINFO_DMSP_IS_MASTER, - ODM_CMNINFO_SCAN, - ODM_CMNINFO_POWER_SAVING, - ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E - ODM_CMNINFO_DRV_STOP, - ODM_CMNINFO_PNP_IN, - ODM_CMNINFO_INIT_ON, - ODM_CMNINFO_ANT_TEST, - ODM_CMNINFO_NET_CLOSED, - //ODM_CMNINFO_RTSTA_AID, // For win driver only? - ODM_CMNINFO_FORCED_IGI_LB, - ODM_CMNINFO_P2P_LINK, - ODM_CMNINFO_FCS_MODE, - ODM_CMNINFO_IS1ANTENNA, - ODM_CMNINFO_RFDEFAULTPATH, - ODM_CMNINFO_DFS_MASTER_ENABLE, - ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, -//--------- POINTER REFERENCE-----------// - -//------------CALL BY VALUE-------------// - ODM_CMNINFO_WIFI_DIRECT, - ODM_CMNINFO_WIFI_DISPLAY, - ODM_CMNINFO_LINK_IN_PROGRESS, - ODM_CMNINFO_LINK, - ODM_CMNINFO_STATION_STATE, - ODM_CMNINFO_RSSI_MIN, - ODM_CMNINFO_MACID_RSSI_MIN, - ODM_CMNINFO_RSSI_MIN_BY_PATH, - ODM_CMNINFO_DBG_COMP, /* u4SByte*/ - ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/ - ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/ - ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/ - ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/ - ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, - ODM_CMNINFO_BE_FIX_TX_ANT, - ODM_CMNINFO_BT_ENABLED, - ODM_CMNINFO_BT_HS_CONNECT_PROCESS, - ODM_CMNINFO_BT_HS_RSSI, - ODM_CMNINFO_BT_OPERATION, - ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not - ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil - ODM_CMNINFO_BT_DISABLE_EDCA, -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - ODM_CMNINFO_VXD_LINK, -#endif -#endif - ODM_CMNINFO_AP_TOTAL_NUM, - ODM_CMNINFO_POWER_TRAINING, - ODM_CMNINFO_DFS_REGION_DOMAIN, -//------------CALL BY VALUE-------------// - - // - // Dynamic ptr array hook itms. - // - ODM_CMNINFO_STA_STATUS, - ODM_CMNINFO_PHY_STATUS, - ODM_CMNINFO_MAC_STATUS, - - ODM_CMNINFO_MAX, - - -}ODM_CMNINFO_E; - - -typedef enum _PHYDM_Info_query_type { - PHYDM_INFO_FA_OFDM, - PHYDM_INFO_FA_CCK, - PHYDM_INFO_FA_TOTAL, - PHYDM_INFO_CCA_OFDM, - PHYDM_INFO_CCA_CCK, - PHYDM_INFO_CCA_ALL, - PHYDM_INFO_CRC32_OK_VHT, - PHYDM_INFO_CRC32_OK_HT, - PHYDM_INFO_CRC32_OK_LEGACY, - PHYDM_INFO_CRC32_OK_CCK, - PHYDM_INFO_CRC32_ERROR_VHT, - PHYDM_INFO_CRC32_ERROR_HT, - PHYDM_INFO_CRC32_ERROR_LEGACY, - PHYDM_INFO_CRC32_ERROR_CCK, - PHYDM_INFO_EDCCA_FLAG, - PHYDM_INFO_OFDM_ENABLE, - PHYDM_INFO_CCK_ENABLE, - PHYDM_INFO_DBG_PORT_0 -} PHYDM_INFO_QUERY_E; - -typedef enum _PHYDM_API_Definition { - - PHYDM_API_NBI = 1, - PHYDM_API_CSI_MASK, - - -} PHYDM_API_E; - - -// -// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY -// -typedef enum _ODM_Support_Ability_Definition -{ - // - // BB ODM section BIT 0-19 - // - ODM_BB_DIG = BIT0, - ODM_BB_RA_MASK = BIT1, - ODM_BB_DYNAMIC_TXPWR = BIT2, - ODM_BB_FA_CNT = BIT3, - ODM_BB_RSSI_MONITOR = BIT4, - ODM_BB_CCK_PD = BIT5, - ODM_BB_ANT_DIV = BIT6, - ODM_BB_PWR_TRAIN = BIT8, - ODM_BB_RATE_ADAPTIVE = BIT9, - ODM_BB_PATH_DIV = BIT10, - ODM_BB_LNA_SAT_CHK = BIT11, - ODM_BB_LNA_SAT_CHK_TYPE2 = BIT12, - ODM_BB_ADAPTIVITY = BIT13, - ODM_BB_CFO_TRACKING = BIT14, - ODM_BB_NHM_CNT = BIT15, - ODM_BB_PRIMARY_CCA = BIT16, - ODM_BB_TXBF = BIT17, - ODM_BB_DYNAMIC_ARFR = BIT18, - ODM_BB_DYNAMIC_PSDTOOL = BIT19, - // - // MAC DM section BIT 20-23 - // - ODM_MAC_EDCA_TURBO = BIT20, - ODM_MAC_EARLY_MODE = BIT21, - ODM_BB_ADAPTIVE_SOML = BIT23, - - // - // RF ODM section BIT 24-31 - // - ODM_RF_TX_PWR_TRACK = BIT24, - ODM_RF_RX_GAIN_TRACK = BIT25, - ODM_RF_CALIBRATION = BIT26, - -}ODM_ABILITY_E; - - -// ODM_CMNINFO_ONE_PATH_CCA -typedef enum tag_CCA_Path -{ - ODM_CCA_2R = 0, - ODM_CCA_1R_A = 1, - ODM_CCA_1R_B = 2, -}ODM_CCA_PATH_E; - -typedef enum CCA_PATHDIV_EN { - CCA_PATHDIV_DISABLE = 0, - CCA_PATHDIV_ENABLE = 1, - -} CCA_PATHDIV_EN_E; - - -typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ - PHY_REG_PG_RELATIVE_VALUE = 0, - PHY_REG_PG_EXACT_VALUE = 1 -} PHY_REG_PG_TYPE; - -// -// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. -// -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (RT_PLATFORM != PLATFORM_LINUX) -typedef -#endif - -struct DM_Out_Source_Dynamic_Mechanism_Structure -#else// for AP,ADSL,CE Team -typedef struct DM_Out_Source_Dynamic_Mechanism_Structure -#endif -{ - // Add for different team use temporarily - // - PADAPTER Adapter; // For CE/NIC team - prtl8192cd_priv priv; // For AP/ADSL team - // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. - BOOLEAN odm_ready; - -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - rtl8192cd_priv fake_priv; -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - // ADSL_AP_BUILD_WORKAROUND - ADAPTER fake_adapter; -#endif - - PHY_REG_PG_TYPE PhyRegPgValueType; - u1Byte PhyRegPgVersion; - - u4Byte DebugComponents; - u4Byte fw_DebugComponents; - u4Byte DebugLevel; - - u4Byte NumQryPhyStatusAll; //CCK + OFDM - u4Byte LastNumQryPhyStatusAll; - u4Byte RxPWDBAve; - BOOLEAN MPDIG_2G; //off MPDIG - u1Byte Times_2G; - BOOLEAN bInitHwInfoByRfe; - -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// - BOOLEAN bCckHighPower; - u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE - u1Byte ControlChannel; -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// - -//--------REMOVED COMMON INFO----------// - //u1Byte PseudoMacPhyMode; - //BOOLEAN *BTCoexist; - //BOOLEAN PseudoBtCoexist; - //u1Byte OPMode; - //BOOLEAN bAPMode; - //BOOLEAN bClientMode; - //BOOLEAN bAdHocMode; - //BOOLEAN bSlaveOfDMSP; -//--------REMOVED COMMON INFO----------// - - -//1 COMMON INFORMATION - - // - // Init Value - // -//-----------HOOK BEFORE REG INIT-----------// - // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 - u1Byte SupportPlatform; - // ODM Platform info WIN/AP/CE - u1Byte Normalrxpath; - // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K - u4Byte SupportAbility; - // ODM PCIE/USB/SDIO = 1/2/3 - u1Byte SupportInterface; - // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... - u4Byte SupportICType; - // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... - u1Byte CutVersion; - // Fab Version TSMC/UMC = 0/1 - u1Byte FabVersion; - // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... - u1Byte RFType; - u1Byte RFEType; - // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... - u1Byte BoardType; - u1Byte PackageType; - u2Byte TypeGLNA; - u2Byte TypeGPA; - u2Byte TypeALNA; - u2Byte TypeAPA; - // with external LNA NO/Yes = 0/1 - u1Byte ExtLNA; // 2G - u1Byte ExtLNA5G; //5G - // with external PA NO/Yes = 0/1 - u1Byte ExtPA; // 2G - u1Byte ExtPA5G; //5G - // with external TRSW NO/Yes = 0/1 - u1Byte ExtTRSW; - u1Byte ExtLNAGain; // 2G - u1Byte PatchID; //Customer ID - BOOLEAN bInHctTest; - u1Byte WIFITest; - - BOOLEAN bDualMacSmartConcurrent; - u4Byte BK_SupportAbility; - u1Byte AntDivType; - u1Byte with_extenal_ant_switch; - BOOLEAN ConfigBBRF; - u1Byte odm_Regulation2_4G; - u1Byte odm_Regulation5G; - u1Byte IQKFWOffload; - BOOLEAN cck_new_agc; - BOOLEAN use_new_agc; - s8 cck_lna_gain_table[8]; - u1Byte phydm_period; - u4Byte phydm_sys_up_time; - u1Byte num_rf_path; - u2Byte consecutive_idlel_time; /*unit: second*/ -//-----------HOOK BEFORE REG INIT-----------// - - // - // Dynamic Value - // -//--------- POINTER REFERENCE-----------// - - u1Byte u1Byte_temp; - BOOLEAN BOOLEAN_temp; - PADAPTER PADAPTER_temp; - - // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 - u1Byte *pMacPhyMode; - //TX Unicast byte count - u8Byte *pNumTxBytesUnicast; - //RX Unicast byte count - u8Byte *pNumRxBytesUnicast; - // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 - u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E - // Frequence band 2.4G/5G = 0/1 - u1Byte *pBandType; - // Secondary channel offset don't_care/below/above = 0/1/2 - u1Byte *pSecChOffset; - // Security mode Open/WEP/AES/TKIP = 0/1/2/3 - u1Byte *pSecurity; - // BW info 20M/40M/80M = 0/1/2 - u1Byte *pBandWidth; - // Central channel location Ch1/Ch2/.... - u1Byte *pChannel; //central channel number - BOOLEAN DPK_Done; - // Common info for 92D DMSP - - BOOLEAN *pbGetValueFromOtherMac; - PADAPTER *pBuddyAdapter; - BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave - // Common info for Status - BOOLEAN *pbScanInProcess; - BOOLEAN *pbPowerSaving; - // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. - u1Byte *pOnePathCCA; - //pMgntInfo->AntennaTest - u1Byte *pAntennaTest; - BOOLEAN *pbNet_closed; - //u1Byte *pAidMap; - u1Byte *pu1ForcedIgiLb; - BOOLEAN *pIsFcsModeEnable; -/*--------- For 8723B IQK-----------*/ - BOOLEAN *pIs1Antenna; - u1Byte *pRFDefaultPath; - // 0:S1, 1:S0 - -//--------- POINTER REFERENCE-----------// - pu2Byte pForcedDataRate; - pu1Byte HubUsbMode; - BOOLEAN *pbFwDwRsvdPageInProgress; - u4Byte *pCurrentTxTP; - u4Byte *pCurrentRxTP; - u1Byte *pSoundingSeq; -//------------CALL BY VALUE-------------// - BOOLEAN bLinkInProcess; - BOOLEAN bWIFI_Direct; - BOOLEAN bWIFI_Display; - BOOLEAN bLinked; - BOOLEAN bsta_state; -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - BOOLEAN VXD_bLinked; -#endif -#endif // for repeater mode add by YuChen 2014.06.23 - u1Byte RSSI_Min; - u1Byte macid_rssi_min; - u1Byte RSSI_Min_ByPath; - u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ - BOOLEAN bIsMPChip; - BOOLEAN bOneEntryOnly; - BOOLEAN mp_mode; - u4Byte OneEntry_MACID; - u32 one_entry_tp; - u32 pre_one_entry_tp; - u1Byte pre_number_linked_client; - u1Byte number_linked_client; - u1Byte pre_number_active_client; - u1Byte number_active_client; - // Common info for BTDM - BOOLEAN bBtEnabled; // BT is enabled - BOOLEAN bBtConnectProcess; // BT HS is under connection progress. - u1Byte btHsRssi; // BT HS mode wifi rssi value. - BOOLEAN bBtHsOperation; // BT HS mode is under progress - u1Byte btHsDigVal; // use BT rssi to decide the DIG value - BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo - BOOLEAN bBtBusy; // BT is busy. - BOOLEAN bBtLimitedDig; // BT is busy. - BOOLEAN bDisablePhyApi; -//------------CALL BY VALUE-------------// - u1Byte RSSI_A; - u1Byte RSSI_B; - u1Byte RSSI_C; - u1Byte RSSI_D; - u8Byte RSSI_TRSW; - u8Byte RSSI_TRSW_H; - u8Byte RSSI_TRSW_L; - u8Byte RSSI_TRSW_iso; - u1Byte TXAntStatus; - u1Byte RXAntStatus; - u1Byte cck_lna_idx; - u1Byte cck_vga_idx; - u1Byte curr_station_id; - u1Byte ofdm_agc_idx[4]; - - u1Byte RxRate; - u8 rate_ss; - BOOLEAN bNoisyState; - u1Byte TxRate; - u1Byte LinkedInterval; - u1Byte preChannel; - u4Byte TxagcOffsetValueA; - BOOLEAN IsTxagcOffsetPositiveA; - u4Byte TxagcOffsetValueB; - BOOLEAN IsTxagcOffsetPositiveB; - u4Byte tx_tp; - u4Byte rx_tp; - u4Byte total_tp; - u8Byte curTxOkCnt; - u8Byte curRxOkCnt; - u8Byte lastTxOkCnt; - u8Byte lastRxOkCnt; - u4Byte BbSwingOffsetA; - BOOLEAN IsBbSwingOffsetPositiveA; - u4Byte BbSwingOffsetB; - BOOLEAN IsBbSwingOffsetPositiveB; - u1Byte antdiv_rssi; - u1Byte fat_comb_a; - u1Byte fat_comb_b; - u1Byte antdiv_intvl; - u1Byte AntType; - u1Byte pre_AntType; - u1Byte antdiv_period; - u1Byte evm_antdiv_period; - u1Byte antdiv_tp_period; - u1Byte antdiv_select; - u1Byte path_select; - u8 antdiv_train_num;/*training time for each antenna in EVM method*/ - u8 stop_antdiv_rssi_th; - u16 stop_antdiv_tp_diff_th; - u16 stop_antdiv_tp_th; - u16 tp_active_th; - u8 tp_active_occur; - u1Byte antdiv_evm_en; - u1Byte bdc_holdstate; - u1Byte NdpaPeriod; - BOOLEAN H2C_RARpt_connect; - BOOLEAN cck_agc_report_type; - - u1Byte dm_dig_max_TH; - u1Byte dm_dig_min_TH; - u1Byte print_agc; - u1Byte TrafficLoad; - u1Byte pre_TrafficLoad; - u1Byte la_mode; - - - //For Adaptivtiy - u2Byte NHM_cnt_0; - u2Byte NHM_cnt_1; - s1Byte TH_L2H_default; - s1Byte TH_EDCCA_HL_diff_default; - s1Byte TH_L2H_ini; - s1Byte TH_EDCCA_HL_diff; - s1Byte TH_L2H_ini_mode2; - s1Byte TH_EDCCA_HL_diff_mode2; - BOOLEAN Carrier_Sense_enable; - u1Byte Adaptivity_IGI_upper; - BOOLEAN adaptivity_flag; - u1Byte DCbackoff; - BOOLEAN Adaptivity_enable; - u1Byte APTotalNum; - BOOLEAN EDCCA_enable; - ADAPTIVITY_STATISTICS Adaptivity; - //For Adaptivtiy - u1Byte LastUSBHub; - u1Byte TxBfDataRate; - - u1Byte nbi_set_result; - u1Byte csi_set_result; - u1Byte csi_set_result_2; - - u1Byte c2h_cmd_start; - u1Byte fw_debug_trace[60]; - u1Byte pre_c2h_seq; - BOOLEAN fw_buff_is_enpty; - u4Byte data_frame_num; - - /*for noise detection*/ - BOOLEAN NoisyDecision; /*b_noisy*/ - BOOLEAN pre_b_noisy; - u4Byte NoisyDecision_Smooth; - BOOLEAN is_disable_dym_ecs; - u4Byte original_pd_threshold; - BOOLEAN is_disable_dym_ant_weighting; - BOOLEAN is_disable_primary_cca; - u1Byte lna_sat_chk_cnt; - u1Byte lna_sat_chk_duty_cycle; - u4Byte lna_sat_chk_period_ms; - BOOLEAN is_disable_lna_sat_chk; - BOOLEAN is_disable_gain_table_switch; - - /*TDMA-DIG*/ - u1Byte force_low_igi; - u1Byte force_high_igi; - bool rx_gain_min_dbg_switch; - u1Byte tdma_low_fa_cca_ratio_l2h; - u1Byte tdma_low_fa_cca_ratio_h2l; - u1Byte tdma_high_fa_cca_ratio_l2h; - u1Byte tdma_high_fa_cca_ratio_h2l; - u1Byte tdma_is_enough_fa_th; - bool is_disable_rx_gain_min_check; - u1Byte rssi_to_igi_upper_offset; - bool tdma_dig_turbo; - u1Byte tdma_dig_timer_ms; - bool original_dig_restore; - u8 tdma_dig_low_upper_bond; - u8 total_state_number; - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - u1Byte snr_var_thd; - u1Byte delta_snr_mean; - u1Byte delta_snr_var; - u1Byte total_bit_shift; - u1Byte is_force_lna_sat_table; - u1Byte is_force_lna_sat_macid; - u1Byte is_snr_detail_en; - u1Byte lwr_snr_ratio_bit_shift; - u1Byte force_change_period; -#endif - - ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; - - // - //2 Define STA info. - // _ODM_STA_INFO - // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? - PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM]; -#endif - -#if (RATE_ADAPTIVE_SUPPORT == 1) - u2Byte CurrminRptTime; - ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 -#endif - // - // 2012/02/14 MH Add to share 88E ra with other SW team. - // We need to colelct all support abilit to a proper area. - // - BOOLEAN RaSupport88E; - - // Define ........... - - // Latest packet phy info (ODM write) - ODM_PHY_DBG_INFO_T PhyDbgInfo; - //PHY_INFO_88E PhyInfo; - - // Latest packet phy info (ODM write) - ODM_MAC_INFO *pMacInfo; - //MAC_INFO_88E MacInfo; - - // Different Team independt structure?? - - // - //TX_RTP_CMN TX_retrpo; - //TX_RTP_88E TX_retrpo; - //TX_RTP_8195 TX_retrpo; - - // - //ODM Structure - // -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - BDC_T DM_BdcTable; - #endif - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - SAT_T dm_sat_table; - #endif - -#endif - FAT_T DM_FatTable; - DIG_T DM_DigTable; -#if (defined(CONFIG_BB_POWER_SAVING)) - PS_T DM_PSTable; -#endif - Pri_CCA_T DM_PriCCA; - RA_T DM_RA_Table; - FALSE_ALARM_STATISTICS FalseAlmCnt; -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - FALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc; -#endif - FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; - SWAT_T DM_SWAT_Table; - CFO_TRACKING DM_CfoTrack; - ACS DM_ACS; - CCX_INFO DM_CCX_INFO; - LNA_SATURATION_INFO DM_LNA_SAT_INFO; - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - LNA_SAT_TYPE2_INFO DM_LNA_SAT_TYPE2_INFO; -#endif - -#if (CONFIG_ADAPTIVE_SOML) - struct _ADAPTIVE_SOML_ dm_soml_table; -#endif -#if (PHYDM_LA_MODE_SUPPORT == 1) - RT_ADCSMP adcsmp; -#endif - -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - IQK_INFO IQK_info; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - //Path Div Struct - PATHDIV_PARA pathIQK; -#endif -#if(defined(CONFIG_PATH_DIVERSITY)) - PATHDIV_T DM_PathDiv; -#endif - - EDCA_T DM_EDCA_Table; - u4Byte WMMEDCA_BE; - - // Copy from SD4 structure - // - // ================================================== - // - - //common - //u1Byte DM_Type; - //u1Byte PSD_Report_RXHP[80]; // Add By Gary - //u1Byte PSD_func_flag; // Add By Gary - //for DIG - //u1Byte bDMInitialGainEnable; - //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. - - BOOLEAN *pbDriverStopped; - BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; - BOOLEAN *pinit_adpt_in_progress; - - //PSD - BOOLEAN bUserAssignLevel; - u1Byte RSSI_BT; /*come from BT*/ - BOOLEAN bPSDinProcess; - BOOLEAN bPSDactive; - BOOLEAN bDMInitialGainEnable; - - //MPT DIG - RT_TIMER MPT_DIGTimer; - - //for rate adaptive, in fact, 88c/92c fw will handle this - u1Byte bUseRAMask; - - ODM_RATE_ADAPTIVE RateAdaptive; - #if (defined(CONFIG_ANT_DETECTION)) - ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/ - #endif - ODM_RF_CAL_T RFCalibrateInfo; - u4Byte nIQK_Cnt; - u4Byte nIQK_OK_Cnt; - u4Byte nIQK_Fail_Cnt; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - // - // Power Training - // - u1Byte ForcePowerTrainingState; - BOOLEAN bChangeState; - u4Byte PT_score; - u8Byte OFDM_RX_Cnt; - u8Byte CCK_RX_Cnt; -#endif - BOOLEAN bDisablePowerTraining; - u1Byte DynamicTxHighPowerLvl; - u1Byte LastDTPLvl; - u4Byte tx_agc_ofdm_18_6; - u1Byte rx_pkt_type; - - // - // ODM system resource. - // - - // ODM relative time. - RT_TIMER PathDivSwitchTimer; - //2011.09.27 add for Path Diversity - RT_TIMER CCKPathDiversityTimer; - RT_TIMER FastAntTrainingTimer; - #ifdef ODM_EVM_ENHANCE_ANTDIV - RT_TIMER EVM_FastAntTrainingTimer; - #endif - RT_TIMER sbdcnt_timer; - - // ODM relative workitem. -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if USE_WORKITEM - RT_WORK_ITEM PathDivSwitchWorkitem; - RT_WORK_ITEM CCKPathDiversityWorkitem; - RT_WORK_ITEM FastAntTrainingWorkitem; - RT_WORK_ITEM MPT_DIGWorkitem; - RT_WORK_ITEM RaRptWorkitem; - RT_WORK_ITEM sbdcnt_workitem; -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - RT_BEAMFORMING_INFO BeamformingInfo; -#endif -#endif - -#ifdef CONFIG_PHYDM_DFS_MASTER - u1Byte DFS_RegionDomain; - pu1Byte dfs_master_enabled; - - /*====== phydm_radar_detect_with_dbg_parm start ======*/ - u1Byte radar_detect_dbg_parm_en; - u4Byte radar_detect_reg_918; - u4Byte radar_detect_reg_91c; - u4Byte radar_detect_reg_920; - u4Byte radar_detect_reg_924; - /*====== phydm_radar_detect_with_dbg_parm end ======*/ -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - -#if (RT_PLATFORM != PLATFORM_LINUX) -} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure -#else -}; -#endif - -#else// for AP,ADSL,CE Team -} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure -#endif - - -typedef enum _PHYDM_STRUCTURE_TYPE{ - PHYDM_FALSEALMCNT, - PHYDM_CFOTRACK, - PHYDM_ADAPTIVITY, - PHYDM_ROMINFO, - -}PHYDM_STRUCTURE_TYPE; - - - - typedef enum _ODM_RF_CONTENT{ - odm_radioa_txt = 0x1000, - odm_radiob_txt = 0x1001, - odm_radioc_txt = 0x1002, - odm_radiod_txt = 0x1003 -} ODM_RF_CONTENT; - -typedef enum _ODM_BB_Config_Type{ - CONFIG_BB_PHY_REG, - CONFIG_BB_AGC_TAB, - CONFIG_BB_AGC_TAB_2G, - CONFIG_BB_AGC_TAB_5G, - CONFIG_BB_PHY_REG_PG, - CONFIG_BB_PHY_REG_MP, - CONFIG_BB_AGC_TAB_DIFF, -} ODM_BB_Config_Type, *PODM_BB_Config_Type; - -typedef enum _ODM_RF_Config_Type{ - CONFIG_RF_RADIO, - CONFIG_RF_TXPWR_LMT, -} ODM_RF_Config_Type, *PODM_RF_Config_Type; - -typedef enum _ODM_FW_Config_Type{ - CONFIG_FW_NIC, - CONFIG_FW_NIC_2, - CONFIG_FW_AP, - CONFIG_FW_AP_2, - CONFIG_FW_MP, - CONFIG_FW_WoWLAN, - CONFIG_FW_WoWLAN_2, - CONFIG_FW_AP_WoWLAN, - CONFIG_FW_BT, -} ODM_FW_Config_Type; - -// Status code -#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -typedef enum _RT_STATUS{ - RT_STATUS_SUCCESS, - RT_STATUS_FAILURE, - RT_STATUS_PENDING, - RT_STATUS_RESOURCE, - RT_STATUS_INVALID_CONTEXT, - RT_STATUS_INVALID_PARAMETER, - RT_STATUS_NOT_SUPPORT, - RT_STATUS_OS_API_FAILED, -}RT_STATUS,*PRT_STATUS; -#endif // end of RT_STATUS definition - -#ifdef REMOVE_PACK -#pragma pack() -#endif - -//3=========================================================== -//3 AGC RX High Power Mode -//3=========================================================== -#define LNA_Low_Gain_1 0x64 -#define LNA_Low_Gain_2 0x5A -#define LNA_Low_Gain_3 0x58 - -#define FA_RXHP_TH1 5000 -#define FA_RXHP_TH2 1500 -#define FA_RXHP_TH3 800 -#define FA_RXHP_TH4 600 -#define FA_RXHP_TH5 500 - -typedef enum tag_1R_CCA_Type_Definition -{ - CCA_1R =0, - CCA_2R = 1, - CCA_MAX = 2, -}DM_1R_CCA_E; - -typedef enum tag_RF_Type_Definition -{ - RF_Save =0, - RF_Normal = 1, - RF_MAX = 2, -}DM_RF_E; - -// -// check Sta pointer valid or not -// -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) -#else -#define IS_STA_VALID(pSta) (pSta) -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) - -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter - ); - -#endif - - - -u4Byte odm_ConvertTo_dB(u4Byte Value); - -u4Byte odm_ConvertTo_linear(u4Byte Value); - -#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) - -u4Byte -GetPSDData( - PDM_ODM_T pDM_Odm, - unsigned int point, - u1Byte initial_gain_psd); - -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ODM_DMWatchdog_LPS( - IN PDM_ODM_T pDM_Odm -); -#endif - - -s4Byte -ODM_PWdB_Conversion( - IN s4Byte X, - IN u4Byte TotalBit, - IN u4Byte DecimalBit - ); - -s4Byte -ODM_SignConversion( - IN s4Byte value, - IN u4Byte TotalBit - ); - -void -phydm_seq_sorting( - IN PVOID pDM_VOID, - IN OUT u4Byte *p_value, - IN OUT u4Byte *rank_idx, - IN OUT u4Byte *p_idx_out, - IN u1Byte seq_length -); - -VOID -ODM_DMInit( - IN PDM_ODM_T pDM_Odm -); - -VOID -ODM_DMReset( - IN PDM_ODM_T pDM_Odm - ); - -VOID -phydm_support_ability_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - -VOID -phydm_config_trx_path( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - -VOID -ODM_DMWatchdog( - IN PDM_ODM_T pDM_Odm // For common use in the future - ); - -VOID -ODM_CmnInfoInit( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u4Byte Value - ); - -VOID -ODM_CmnInfoHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN PVOID pValue - ); - -VOID -ODM_CmnInfoPtrArrayHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u2Byte Index, - IN PVOID pValue - ); - -VOID -ODM_CmnInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte CmnInfo, - IN u8Byte Value - ); - -u4Byte -PHYDM_CmnInfoQuery( - IN PDM_ODM_T pDM_Odm, - IN PHYDM_INFO_QUERY_E info_type - ); - -#if(DM_ODM_SUPPORT_TYPE==ODM_AP) -VOID -ODM_InitAllThreads( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_StopAllThreads( - IN PDM_ODM_T pDM_Odm - ); -#endif - -VOID -ODM_InitAllTimers( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_CancelAllTimers( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_ReleaseAllTimers( - IN PDM_ODM_T pDM_Odm - ); - - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); -VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); - - - -u8Byte -PlatformDivision64( - IN u8Byte x, - IN u8Byte y -); - -//==================================================== -//3 PathDiV End -//==================================================== - - -#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh - -typedef enum tag_DIG_Connect_Definition -{ - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - DIG_MultiSTA_DISCONNECT = 3, - DIG_MultiSTA_CONNECT = 4, - DIG_CONNECT_MAX -}DM_DIG_CONNECT_E; - - -// -// 2012/01/12 MH Check afapter status. Temp fix BSOD. -// -#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ - if (pDM_Odm->Adapter == NULL)\ - {\ - return;\ - }\ - -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -ODM_AsocEntry_Init( - IN PDM_ODM_T pDM_Odm - ); - - -PVOID -PhyDM_Get_Structure( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Structure_Type -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) -/*===========================================================*/ -/* The following is for compile only*/ -/*===========================================================*/ - -#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE -#define RF_T_METER_92D 0x42 - - -#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) - -#define rConfig_ram64x16 0xb2c - -#define TARGET_CHNL_NUM_2G_5G 59 - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); -#endif - -//=========================================================== -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -void odm_dtc(PDM_ODM_T pDM_Odm); -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - - -VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); - - -#endif - -VOID -phydm_api_debug( - IN PVOID pDM_VOID, - IN u4Byte function_map, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -); - -u1Byte -phydm_csi_mask_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch -); - -u1Byte -phydm_nbi_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch -); - -void -phydm_receiver_blocking( - void *p_dm_void -); - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +//============================================================ +// include files +//============================================================ +#include "phydm_pre_define.h" +#include "phydm_dig.h" +#include "phydm_edcaturbocheck.h" +#include "phydm_pathdiv.h" +#include "phydm_antdiv.h" +#include "phydm_antdect.h" +#include "phydm_soml.h" +#include "phydm_dynamicbbpowersaving.h" +#include "phydm_rainfo.h" +#include "phydm_dynamictxpower.h" +#include "phydm_cfotracking.h" +#include "phydm_acs.h" +#include "phydm_adaptivity.h" +#include "phydm_iqk.h" +#include "phydm_dfs.h" +#include "phydm_ccx.h" +#include "txbf/phydm_hal_txbf_api.h" +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +#include "phydm_beamforming.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#include "halphyrf_ap.h" +#include "phydm_adc_sampling.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#include "halphyrf_ce.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#include "halphyrf_win.h" +#endif +#include "phydm_noisemonitor.h" + +//============================================================ +// Definition +//============================================================ +// +// 2011/09/22 MH Define all team supprt ability. +// + +/* Traffic load decision */ +#define TRAFFIC_ULTRA_LOW 1 +#define TRAFFIC_LOW 2 +#define TRAFFIC_MID 3 +#define TRAFFIC_HIGH 4 + +#define NONE 0 + +/*NBI API------------------------------------*/ +#define NBI_ENABLE 1 +#define NBI_DISABLE 2 + +#define NBI_TABLE_SIZE_128 27 +#define NBI_TABLE_SIZE_256 59 + +#define NUM_START_CH_80M 7 +#define NUM_START_CH_40M 14 + +#define CH_OFFSET_40M 2 +#define CH_OFFSET_80M 6 + +/*CSI MASK API------------------------------------*/ +#define CSI_MASK_ENABLE 1 +#define CSI_MASK_DISABLE 2 + +/*------------------------------------------------*/ + +#define FFT_128_TYPE 1 +#define FFT_256_TYPE 2 + +#define SET_SUCCESS 1 +#define SET_ERROR 2 +#define SET_NO_NEED 3 + +#define FREQ_POSITIVE 1 +#define FREQ_NEGATIVE 2 + + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define PHYDM_WATCH_DOG_PERIOD 1 +#else +#define PHYDM_WATCH_DOG_PERIOD 2 +#endif + +#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) +#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) + +#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) +#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) + +#define BYTE_2_DWORD(B3, B2, B1, B0) ((B3 << 24) | (B2 << 16) | (B1 << 8) | B0) +#define BIT_2_BYTE(B3, B2, B1, B0) ((B3 << 3) | (B2 << 2) | (B1 << 1) | B0) + +//============================================================ +// structure and define +//============================================================ + +// +// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. +// We need to remove to other position??? +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +typedef struct rtl8192cd_priv { + u1Byte temp; + +}rtl8192cd_priv, *prtl8192cd_priv; +#endif + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +typedef struct _ADAPTER{ + u1Byte temp; + #ifdef AP_BUILD_WORKAROUND + HAL_DATA_TYPE* temp2; + prtl8192cd_priv priv; + #endif +}ADAPTER, *PADAPTER; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +typedef struct _WLAN_STA{ + u1Byte temp; +} WLAN_STA, *PRT_WLAN_STA; + +#endif + +typedef struct _Dynamic_Primary_CCA{ + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; + u1Byte CH_offset; + u1Byte MF_state; +}Pri_CCA_T, *pPri_CCA_T; + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #ifdef ADSL_AP_BUILD_WORKAROUND + #define MAX_TOLERANCE 5 + #define IQK_DELAY_TIME 1 /*ms*/ + #endif +#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +// +// Declare for common info +// + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +__PACK typedef struct _ODM_Phy_Status_Info_ +{ + u1Byte RxPWDBAll; + u1Byte SignalQuality; /* in 0-100 index. */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s1Byte RxMIMOSignalQuality[4]; /* EVM */ + u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; + +typedef struct _ODM_Phy_Status_Info_Append_ +{ + u1Byte MAC_CRC32; + +}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; + +#else + +typedef struct _ODM_Phy_Status_Info_ +{ + // + // Be care, if you want to add any element please insert between + // RxPWDBAll & SignalStrength. + // +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPWDBAll; +#else + u1Byte RxPWDBAll; +#endif + u1Byte SignalQuality; /* in 0-100 index. */ + s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ + u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s2Byte Cfo_short[4]; /* per-path's Cfo_short */ + s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ + s1Byte RxPower; /* in dBm Translate from PWdB */ + s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; /* in 0-100 index. */ + s1Byte RxPwr[4]; /* per-path's pwdb */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte btCoexPwrAdjust; +#endif +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; +#endif + +typedef struct _ODM_Per_Pkt_Info_ +{ + //u1Byte Rate; + u1Byte DataRate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; + BOOLEAN bToSelf; +}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; + + +typedef struct _ODM_Phy_Dbg_Info_ +{ + //ODM Write,debug info + s1Byte RxSNRdB[4]; + u4Byte NumQryPhyStatus; + u4Byte NumQryPhyStatusCCK; + u4Byte NumQryPhyStatusOFDM; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u4Byte NumQryMuPkt; + u4Byte NumQryBfPkt; + u4Byte NumQryMuVhtPkt[40]; + u4Byte NumQryVhtPkt[40]; +#endif + u1Byte NumQryBeaconPkt; + //Others + s4Byte RxEVM[4]; + +}ODM_PHY_DBG_INFO_T; + + +typedef struct _ODM_Mac_Status_Info_ +{ + u1Byte test; + +}ODM_MAC_INFO; + +// +// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T +// Please declare below ODM relative info in your STA info structure. +// +#if 1 +typedef struct _ODM_STA_INFO{ + // Driver Write + BOOLEAN bUsed; // record the sta status link or not? + //u1Byte WirelessMode; // + u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E + + // ODM Write + //1 PHY_STATUS_INFO + u1Byte RSSI_Path[4]; // + u1Byte RSSI_Ave; + u1Byte RXEVM[4]; + u1Byte RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. +#if 0 + u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_C; //only in Jagar: 4bit + u1Byte ANTSEL_D; //only in Jagar: 4bit + u1Byte TX_ANTL; //not in Jagar: 2bit + u1Byte TX_ANT_HT; //not in Jagar: 2bit + u1Byte TX_ANT_CCK; //not in Jagar: 2bit + u1Byte TXAGC_A; //not in Jagar: 4bit + u1Byte TXAGC_B; //not in Jagar: 4bit + u1Byte TXPWR_OFFSET; //only in Jagar: 3bit + u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK +#endif + + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // Move To lower layer. + // + // ODM Write Wilson will handle this part(said by Luke.Lee) + //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. +#if 0 + //1 For 88E RA (don't redefine the naming) + u1Byte rate_id; + u1Byte rate_SGI; + u1Byte rssi_sta_ra; + u1Byte SGI_enable; + u1Byte Decision_rate; + u1Byte Pre_rate; + u1Byte Active; + + // Driver write Wilson handle. + //1 TX_RPT (don't redefine the naming) + u2Byte RTY[4]; // ??? + u2Byte TOTAL; // ??? + u2Byte DROP; // ??? + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // +#endif + +}ODM_STA_INFO_T, *PODM_STA_INFO_T; +#endif + +// +// 2011/10/20 MH Define Common info enum for all team. +// +typedef enum _ODM_Common_Info_Definition +{ +//-------------REMOVED CASE-----------// + //ODM_CMNINFO_CCK_HP, + //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? + //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E + //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E +//-------------REMOVED CASE-----------// + + // + // Fixed value: + // + + //-----------HOOK BEFORE REG INIT-----------// + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, // ODM_ABILITY_E + ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E + ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E + ODM_CMNINFO_FAB_VER, // ODM_FAB_E + ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_EXT_LNA_GAIN, + ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_CONFIG_BB_RF, + ODM_CMNINFO_DOMAIN_CODE_2G, + ODM_CMNINFO_DOMAIN_CODE_5G, + ODM_CMNINFO_IQKFWOFFLOAD, + ODM_CMNINFO_IQKPAOFF, + ODM_CMNINFO_HUBUSBMODE, + ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, + ODM_CMNINFO_TX_TP, + ODM_CMNINFO_RX_TP, + ODM_CMNINFO_SOUNDING_SEQ, + ODM_CMNINFO_REGRFKFREEENABLE, + ODM_CMNINFO_RFKFREEENABLE, + ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, + //-----------HOOK BEFORE REG INIT-----------// + + + // + // Dynamic value: + // +//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E + ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E + ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E + ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E + ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + //ODM_CMNINFO_RTSTA_AID, // For win driver only? + ODM_CMNINFO_FORCED_IGI_LB, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, + ODM_CMNINFO_IS1ANTENNA, + ODM_CMNINFO_RFDEFAULTPATH, + ODM_CMNINFO_DFS_MASTER_ENABLE, + ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, +//--------- POINTER REFERENCE-----------// + +//------------CALL BY VALUE-------------// + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_MACID_RSSI_MIN, + ODM_CMNINFO_RSSI_MIN_BY_PATH, + ODM_CMNINFO_DBG_COMP, /* u4SByte*/ + ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/ + ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/ + ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/ + ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/ + ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, + ODM_CMNINFO_BE_FIX_TX_ANT, + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_DISABLE_EDCA, +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + ODM_CMNINFO_VXD_LINK, +#endif +#endif + ODM_CMNINFO_AP_TOTAL_NUM, + ODM_CMNINFO_POWER_TRAINING, + ODM_CMNINFO_DFS_REGION_DOMAIN, +//------------CALL BY VALUE-------------// + + // + // Dynamic ptr array hook itms. + // + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + + ODM_CMNINFO_MAX, + + +}ODM_CMNINFO_E; + + +typedef enum _PHYDM_Info_query_type { + PHYDM_INFO_FA_OFDM, + PHYDM_INFO_FA_CCK, + PHYDM_INFO_FA_TOTAL, + PHYDM_INFO_CCA_OFDM, + PHYDM_INFO_CCA_CCK, + PHYDM_INFO_CCA_ALL, + PHYDM_INFO_CRC32_OK_VHT, + PHYDM_INFO_CRC32_OK_HT, + PHYDM_INFO_CRC32_OK_LEGACY, + PHYDM_INFO_CRC32_OK_CCK, + PHYDM_INFO_CRC32_ERROR_VHT, + PHYDM_INFO_CRC32_ERROR_HT, + PHYDM_INFO_CRC32_ERROR_LEGACY, + PHYDM_INFO_CRC32_ERROR_CCK, + PHYDM_INFO_EDCCA_FLAG, + PHYDM_INFO_OFDM_ENABLE, + PHYDM_INFO_CCK_ENABLE, + PHYDM_INFO_DBG_PORT_0 +} PHYDM_INFO_QUERY_E; + +typedef enum _PHYDM_API_Definition { + + PHYDM_API_NBI = 1, + PHYDM_API_CSI_MASK, + + +} PHYDM_API_E; + + +// +// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY +// +typedef enum _ODM_Support_Ability_Definition +{ + // + // BB ODM section BIT 0-19 + // + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_TRAIN = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_LNA_SAT_CHK = BIT11, + ODM_BB_LNA_SAT_CHK_TYPE2 = BIT12, + ODM_BB_ADAPTIVITY = BIT13, + ODM_BB_CFO_TRACKING = BIT14, + ODM_BB_NHM_CNT = BIT15, + ODM_BB_PRIMARY_CCA = BIT16, + ODM_BB_TXBF = BIT17, + ODM_BB_DYNAMIC_ARFR = BIT18, + ODM_BB_DYNAMIC_PSDTOOL = BIT19, + // + // MAC DM section BIT 20-23 + // + ODM_MAC_EDCA_TURBO = BIT20, + ODM_MAC_EARLY_MODE = BIT21, + ODM_BB_ADAPTIVE_SOML = BIT23, + + // + // RF ODM section BIT 24-31 + // + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, + +}ODM_ABILITY_E; + + +// ODM_CMNINFO_ONE_PATH_CCA +typedef enum tag_CCA_Path +{ + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}ODM_CCA_PATH_E; + +typedef enum CCA_PATHDIV_EN { + CCA_PATHDIV_DISABLE = 0, + CCA_PATHDIV_ENABLE = 1, + +} CCA_PATHDIV_EN_E; + + +typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +} PHY_REG_PG_TYPE; + +// +// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. +// +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RT_PLATFORM != PLATFORM_LINUX) +typedef +#endif + +struct DM_Out_Source_Dynamic_Mechanism_Structure +#else// for AP,ADSL,CE Team +typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +#endif +{ + // Add for different team use temporarily + // + PADAPTER Adapter; // For CE/NIC team + prtl8192cd_priv priv; // For AP/ADSL team + // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + BOOLEAN odm_ready; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + rtl8192cd_priv fake_priv; +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + // ADSL_AP_BUILD_WORKAROUND + ADAPTER fake_adapter; +#endif + + PHY_REG_PG_TYPE PhyRegPgValueType; + u1Byte PhyRegPgVersion; + + u4Byte DebugComponents; + u4Byte fw_DebugComponents; + u4Byte DebugLevel; + + u4Byte NumQryPhyStatusAll; //CCK + OFDM + u4Byte LastNumQryPhyStatusAll; + u4Byte RxPWDBAve; + BOOLEAN MPDIG_2G; //off MPDIG + u1Byte Times_2G; + BOOLEAN bInitHwInfoByRfe; + +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u1Byte ControlChannel; +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + +//--------REMOVED COMMON INFO----------// + //u1Byte PseudoMacPhyMode; + //BOOLEAN *BTCoexist; + //BOOLEAN PseudoBtCoexist; + //u1Byte OPMode; + //BOOLEAN bAPMode; + //BOOLEAN bClientMode; + //BOOLEAN bAdHocMode; + //BOOLEAN bSlaveOfDMSP; +//--------REMOVED COMMON INFO----------// + + +//1 COMMON INFORMATION + + // + // Init Value + // +//-----------HOOK BEFORE REG INIT-----------// + // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + u1Byte SupportPlatform; + // ODM Platform info WIN/AP/CE + u1Byte Normalrxpath; + // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K + u4Byte SupportAbility; + // ODM PCIE/USB/SDIO = 1/2/3 + u1Byte SupportInterface; + // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + u4Byte SupportICType; + // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + u1Byte CutVersion; + // Fab Version TSMC/UMC = 0/1 + u1Byte FabVersion; + // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + u1Byte RFType; + u1Byte RFEType; + // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + u1Byte BoardType; + u1Byte PackageType; + u2Byte TypeGLNA; + u2Byte TypeGPA; + u2Byte TypeALNA; + u2Byte TypeAPA; + // with external LNA NO/Yes = 0/1 + u1Byte ExtLNA; // 2G + u1Byte ExtLNA5G; //5G + // with external PA NO/Yes = 0/1 + u1Byte ExtPA; // 2G + u1Byte ExtPA5G; //5G + // with external TRSW NO/Yes = 0/1 + u1Byte ExtTRSW; + u1Byte ExtLNAGain; // 2G + u1Byte PatchID; //Customer ID + BOOLEAN bInHctTest; + u1Byte WIFITest; + + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; + u1Byte with_extenal_ant_switch; + BOOLEAN ConfigBBRF; + u1Byte odm_Regulation2_4G; + u1Byte odm_Regulation5G; + u1Byte IQKFWOffload; + BOOLEAN cck_new_agc; + BOOLEAN use_new_agc; + s8 cck_lna_gain_table[8]; + u1Byte phydm_period; + u4Byte phydm_sys_up_time; + u1Byte num_rf_path; + u2Byte consecutive_idlel_time; /*unit: second*/ +//-----------HOOK BEFORE REG INIT-----------// + + // + // Dynamic Value + // +//--------- POINTER REFERENCE-----------// + + u1Byte u1Byte_temp; + BOOLEAN BOOLEAN_temp; + PADAPTER PADAPTER_temp; + + // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + u1Byte *pMacPhyMode; + //TX Unicast byte count + u8Byte *pNumTxBytesUnicast; + //RX Unicast byte count + u8Byte *pNumRxBytesUnicast; + // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 + u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E + // Frequence band 2.4G/5G = 0/1 + u1Byte *pBandType; + // Secondary channel offset don't_care/below/above = 0/1/2 + u1Byte *pSecChOffset; + // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + u1Byte *pSecurity; + // BW info 20M/40M/80M = 0/1/2 + u1Byte *pBandWidth; + // Central channel location Ch1/Ch2/.... + u1Byte *pChannel; //central channel number + BOOLEAN DPK_Done; + // Common info for 92D DMSP + + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave + // Common info for Status + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + u1Byte *pOnePathCCA; + //pMgntInfo->AntennaTest + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; + //u1Byte *pAidMap; + u1Byte *pu1ForcedIgiLb; + BOOLEAN *pIsFcsModeEnable; +/*--------- For 8723B IQK-----------*/ + BOOLEAN *pIs1Antenna; + u1Byte *pRFDefaultPath; + // 0:S1, 1:S0 + +//--------- POINTER REFERENCE-----------// + pu2Byte pForcedDataRate; + pu1Byte HubUsbMode; + BOOLEAN *pbFwDwRsvdPageInProgress; + u4Byte *pCurrentTxTP; + u4Byte *pCurrentRxTP; + u1Byte *pSoundingSeq; +//------------CALL BY VALUE-------------// + BOOLEAN bLinkInProcess; + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + BOOLEAN bsta_state; +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + BOOLEAN VXD_bLinked; +#endif +#endif // for repeater mode add by YuChen 2014.06.23 + u1Byte RSSI_Min; + u1Byte macid_rssi_min; + u1Byte RSSI_Min_ByPath; + u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + BOOLEAN mp_mode; + u4Byte OneEntry_MACID; + u32 one_entry_tp; + u32 pre_one_entry_tp; + u1Byte pre_number_linked_client; + u1Byte number_linked_client; + u1Byte pre_number_active_client; + u1Byte number_active_client; + // Common info for BTDM + BOOLEAN bBtEnabled; // BT is enabled + BOOLEAN bBtConnectProcess; // BT HS is under connection progress. + u1Byte btHsRssi; // BT HS mode wifi rssi value. + BOOLEAN bBtHsOperation; // BT HS mode is under progress + u1Byte btHsDigVal; // use BT rssi to decide the DIG value + BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo + BOOLEAN bBtBusy; // BT is busy. + BOOLEAN bBtLimitedDig; // BT is busy. + BOOLEAN bDisablePhyApi; +//------------CALL BY VALUE-------------// + u1Byte RSSI_A; + u1Byte RSSI_B; + u1Byte RSSI_C; + u1Byte RSSI_D; + u8Byte RSSI_TRSW; + u8Byte RSSI_TRSW_H; + u8Byte RSSI_TRSW_L; + u8Byte RSSI_TRSW_iso; + u1Byte TXAntStatus; + u1Byte RXAntStatus; + u1Byte cck_lna_idx; + u1Byte cck_vga_idx; + u1Byte curr_station_id; + u1Byte ofdm_agc_idx[4]; + + u1Byte RxRate; + u8 rate_ss; + BOOLEAN bNoisyState; + u1Byte TxRate; + u1Byte LinkedInterval; + u1Byte preChannel; + u4Byte TxagcOffsetValueA; + BOOLEAN IsTxagcOffsetPositiveA; + u4Byte TxagcOffsetValueB; + BOOLEAN IsTxagcOffsetPositiveB; + u4Byte tx_tp; + u4Byte rx_tp; + u4Byte total_tp; + u8Byte curTxOkCnt; + u8Byte curRxOkCnt; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u4Byte BbSwingOffsetA; + BOOLEAN IsBbSwingOffsetPositiveA; + u4Byte BbSwingOffsetB; + BOOLEAN IsBbSwingOffsetPositiveB; + u1Byte antdiv_rssi; + u1Byte fat_comb_a; + u1Byte fat_comb_b; + u1Byte antdiv_intvl; + u1Byte AntType; + u1Byte pre_AntType; + u1Byte antdiv_period; + u1Byte evm_antdiv_period; + u1Byte antdiv_tp_period; + u1Byte antdiv_select; + u1Byte path_select; + u8 antdiv_train_num;/*training time for each antenna in EVM method*/ + u8 stop_antdiv_rssi_th; + u16 stop_antdiv_tp_diff_th; + u16 stop_antdiv_tp_th; + u16 tp_active_th; + u8 tp_active_occur; + u1Byte antdiv_evm_en; + u1Byte bdc_holdstate; + u1Byte NdpaPeriod; + BOOLEAN H2C_RARpt_connect; + BOOLEAN cck_agc_report_type; + + u1Byte dm_dig_max_TH; + u1Byte dm_dig_min_TH; + u1Byte print_agc; + u1Byte TrafficLoad; + u1Byte pre_TrafficLoad; + u1Byte la_mode; + + + //For Adaptivtiy + u2Byte NHM_cnt_0; + u2Byte NHM_cnt_1; + s1Byte TH_L2H_default; + s1Byte TH_EDCCA_HL_diff_default; + s1Byte TH_L2H_ini; + s1Byte TH_EDCCA_HL_diff; + s1Byte TH_L2H_ini_mode2; + s1Byte TH_EDCCA_HL_diff_mode2; + BOOLEAN Carrier_Sense_enable; + u1Byte Adaptivity_IGI_upper; + BOOLEAN adaptivity_flag; + u1Byte DCbackoff; + BOOLEAN Adaptivity_enable; + u1Byte APTotalNum; + BOOLEAN EDCCA_enable; + ADAPTIVITY_STATISTICS Adaptivity; + //For Adaptivtiy + u1Byte LastUSBHub; + u1Byte TxBfDataRate; + + u1Byte nbi_set_result; + u1Byte csi_set_result; + u1Byte csi_set_result_2; + + u1Byte c2h_cmd_start; + u1Byte fw_debug_trace[60]; + u1Byte pre_c2h_seq; + BOOLEAN fw_buff_is_enpty; + u4Byte data_frame_num; + + /*for noise detection*/ + BOOLEAN NoisyDecision; /*b_noisy*/ + BOOLEAN pre_b_noisy; + u4Byte NoisyDecision_Smooth; + BOOLEAN is_disable_dym_ecs; + u4Byte original_pd_threshold; + BOOLEAN is_disable_dym_ant_weighting; + BOOLEAN is_disable_primary_cca; + u1Byte lna_sat_chk_cnt; + u1Byte lna_sat_chk_duty_cycle; + u4Byte lna_sat_chk_period_ms; + BOOLEAN is_disable_lna_sat_chk; + BOOLEAN is_disable_gain_table_switch; + + /*TDMA-DIG*/ + u1Byte force_low_igi; + u1Byte force_high_igi; + bool rx_gain_min_dbg_switch; + u1Byte tdma_low_fa_cca_ratio_l2h; + u1Byte tdma_low_fa_cca_ratio_h2l; + u1Byte tdma_high_fa_cca_ratio_l2h; + u1Byte tdma_high_fa_cca_ratio_h2l; + u1Byte tdma_is_enough_fa_th; + bool is_disable_rx_gain_min_check; + u1Byte rssi_to_igi_upper_offset; + bool tdma_dig_turbo; + u1Byte tdma_dig_timer_ms; + bool original_dig_restore; + u8 tdma_dig_low_upper_bond; + u8 total_state_number; + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + u1Byte snr_var_thd; + u1Byte delta_snr_mean; + u1Byte delta_snr_var; + u1Byte total_bit_shift; + u1Byte is_force_lna_sat_table; + u1Byte is_force_lna_sat_macid; + u1Byte is_snr_detail_en; + u1Byte lwr_snr_ratio_bit_shift; + u1Byte force_change_period; +#endif + + ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; + + // + //2 Define STA info. + // _ODM_STA_INFO + // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM]; +#endif + +#if (RATE_ADAPTIVE_SUPPORT == 1) + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 +#endif + // + // 2012/02/14 MH Add to share 88E ra with other SW team. + // We need to colelct all support abilit to a proper area. + // + BOOLEAN RaSupport88E; + + // Define ........... + + // Latest packet phy info (ODM write) + ODM_PHY_DBG_INFO_T PhyDbgInfo; + //PHY_INFO_88E PhyInfo; + + // Latest packet phy info (ODM write) + ODM_MAC_INFO *pMacInfo; + //MAC_INFO_88E MacInfo; + + // Different Team independt structure?? + + // + //TX_RTP_CMN TX_retrpo; + //TX_RTP_88E TX_retrpo; + //TX_RTP_8195 TX_retrpo; + + // + //ODM Structure + // +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + BDC_T DM_BdcTable; + #endif + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + SAT_T dm_sat_table; + #endif + +#endif + FAT_T DM_FatTable; + DIG_T DM_DigTable; +#if (defined(CONFIG_BB_POWER_SAVING)) + PS_T DM_PSTable; +#endif + Pri_CCA_T DM_PriCCA; + RA_T DM_RA_Table; + FALSE_ALARM_STATISTICS FalseAlmCnt; +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + FALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc; +#endif + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + SWAT_T DM_SWAT_Table; + CFO_TRACKING DM_CfoTrack; + ACS DM_ACS; + CCX_INFO DM_CCX_INFO; + LNA_SATURATION_INFO DM_LNA_SAT_INFO; + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + LNA_SAT_TYPE2_INFO DM_LNA_SAT_TYPE2_INFO; +#endif + +#if (CONFIG_ADAPTIVE_SOML) + struct _ADAPTIVE_SOML_ dm_soml_table; +#endif +#if (PHYDM_LA_MODE_SUPPORT == 1) + RT_ADCSMP adcsmp; +#endif + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + IQK_INFO IQK_info; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + //Path Div Struct + PATHDIV_PARA pathIQK; +#endif +#if(defined(CONFIG_PATH_DIVERSITY)) + PATHDIV_T DM_PathDiv; +#endif + + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; + + // Copy from SD4 structure + // + // ================================================== + // + + //common + //u1Byte DM_Type; + //u1Byte PSD_Report_RXHP[80]; // Add By Gary + //u1Byte PSD_func_flag; // Add By Gary + //for DIG + //u1Byte bDMInitialGainEnable; + //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. + + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + + //PSD + BOOLEAN bUserAssignLevel; + u1Byte RSSI_BT; /*come from BT*/ + BOOLEAN bPSDinProcess; + BOOLEAN bPSDactive; + BOOLEAN bDMInitialGainEnable; + + //MPT DIG + RT_TIMER MPT_DIGTimer; + + //for rate adaptive, in fact, 88c/92c fw will handle this + u1Byte bUseRAMask; + + ODM_RATE_ADAPTIVE RateAdaptive; + #if (defined(CONFIG_ANT_DETECTION)) + ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/ + #endif + ODM_RF_CAL_T RFCalibrateInfo; + u4Byte nIQK_Cnt; + u4Byte nIQK_OK_Cnt; + u4Byte nIQK_Fail_Cnt; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + // + // Power Training + // + u1Byte ForcePowerTrainingState; + BOOLEAN bChangeState; + u4Byte PT_score; + u8Byte OFDM_RX_Cnt; + u8Byte CCK_RX_Cnt; +#endif + BOOLEAN bDisablePowerTraining; + u1Byte DynamicTxHighPowerLvl; + u1Byte LastDTPLvl; + u4Byte tx_agc_ofdm_18_6; + u1Byte rx_pkt_type; + + // + // ODM system resource. + // + + // ODM relative time. + RT_TIMER PathDivSwitchTimer; + //2011.09.27 add for Path Diversity + RT_TIMER CCKPathDiversityTimer; + RT_TIMER FastAntTrainingTimer; + #ifdef ODM_EVM_ENHANCE_ANTDIV + RT_TIMER EVM_FastAntTrainingTimer; + #endif + RT_TIMER sbdcnt_timer; + + // ODM relative workitem. +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM PathDivSwitchWorkitem; + RT_WORK_ITEM CCKPathDiversityWorkitem; + RT_WORK_ITEM FastAntTrainingWorkitem; + RT_WORK_ITEM MPT_DIGWorkitem; + RT_WORK_ITEM RaRptWorkitem; + RT_WORK_ITEM sbdcnt_workitem; +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + RT_BEAMFORMING_INFO BeamformingInfo; +#endif +#endif + +#ifdef CONFIG_PHYDM_DFS_MASTER + u1Byte DFS_RegionDomain; + pu1Byte dfs_master_enabled; + + /*====== phydm_radar_detect_with_dbg_parm start ======*/ + u1Byte radar_detect_dbg_parm_en; + u4Byte radar_detect_reg_918; + u4Byte radar_detect_reg_91c; + u4Byte radar_detect_reg_920; + u4Byte radar_detect_reg_924; + /*====== phydm_radar_detect_with_dbg_parm end ======*/ +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else +}; +#endif + +#else// for AP,ADSL,CE Team +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#endif + + +typedef enum _PHYDM_STRUCTURE_TYPE{ + PHYDM_FALSEALMCNT, + PHYDM_CFOTRACK, + PHYDM_ADAPTIVITY, + PHYDM_ROMINFO, + +}PHYDM_STRUCTURE_TYPE; + + + + typedef enum _ODM_RF_CONTENT{ + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +} ODM_RF_CONTENT; + +typedef enum _ODM_BB_Config_Type{ + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, +} ODM_BB_Config_Type, *PODM_BB_Config_Type; + +typedef enum _ODM_RF_Config_Type{ + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, +} ODM_RF_Config_Type, *PODM_RF_Config_Type; + +typedef enum _ODM_FW_Config_Type{ + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_AP_2, + CONFIG_FW_MP, + CONFIG_FW_WoWLAN, + CONFIG_FW_WoWLAN_2, + CONFIG_FW_AP_WoWLAN, + CONFIG_FW_BT, +} ODM_FW_Config_Type; + +// Status code +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif // end of RT_STATUS definition + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +//3=========================================================== +//3 AGC RX High Power Mode +//3=========================================================== +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +typedef enum tag_1R_CCA_Type_Definition +{ + CCA_1R =0, + CCA_2R = 1, + CCA_MAX = 2, +}DM_1R_CCA_E; + +typedef enum tag_RF_Type_Definition +{ + RF_Save =0, + RF_Normal = 1, + RF_MAX = 2, +}DM_RF_E; + +// +// check Sta pointer valid or not +// +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) +#else +#define IS_STA_VALID(pSta) (pSta) +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) + +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter + ); + +#endif + + + +u4Byte odm_ConvertTo_dB(u4Byte Value); + +u4Byte odm_ConvertTo_linear(u4Byte Value); + +#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +u4Byte +GetPSDData( + PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +VOID +ODM_DMWatchdog_LPS( + IN PDM_ODM_T pDM_Odm +); +#endif + + +s4Byte +ODM_PWdB_Conversion( + IN s4Byte X, + IN u4Byte TotalBit, + IN u4Byte DecimalBit + ); + +s4Byte +ODM_SignConversion( + IN s4Byte value, + IN u4Byte TotalBit + ); + +void +phydm_seq_sorting( + IN PVOID pDM_VOID, + IN OUT u4Byte *p_value, + IN OUT u4Byte *rank_idx, + IN OUT u4Byte *p_idx_out, + IN u1Byte seq_length +); + +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_DMReset( + IN PDM_ODM_T pDM_Odm + ); + +VOID +phydm_support_ability_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + +VOID +phydm_config_trx_path( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm // For common use in the future + ); + +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ); + +u4Byte +PHYDM_CmnInfoQuery( + IN PDM_ODM_T pDM_Odm, + IN PHYDM_INFO_QUERY_E info_type + ); + +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) +VOID +ODM_InitAllThreads( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_StopAllThreads( + IN PDM_ODM_T pDM_Odm + ); +#endif + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ); + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); +VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); + + + +u8Byte +PlatformDivision64( + IN u8Byte x, + IN u8Byte y +); + +//==================================================== +//3 PathDiV End +//==================================================== + + +#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +// +// 2012/01/12 MH Check afapter status. Temp fix BSOD. +// +#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ + if (pDM_Odm->Adapter == NULL)\ + {\ + return;\ + }\ + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +ODM_AsocEntry_Init( + IN PDM_ODM_T pDM_Odm + ); + + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ + +#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE +#define RF_T_METER_92D 0x42 + + +#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) + +#define rConfig_ram64x16 0xb2c + +#define TARGET_CHNL_NUM_2G_5G 59 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); +#endif + +//=========================================================== +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_dtc(PDM_ODM_T pDM_Odm); +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + + +VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); + + +#endif + +VOID +phydm_api_debug( + IN PVOID pDM_VOID, + IN u4Byte function_map, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +u1Byte +phydm_csi_mask_setting( + IN PVOID pDM_VOID, + IN u4Byte enable, + IN u4Byte channel, + IN u4Byte bw, + IN u4Byte f_interference, + IN u4Byte Second_ch +); + +u1Byte +phydm_nbi_setting( + IN PVOID pDM_VOID, + IN u4Byte enable, + IN u4Byte channel, + IN u4Byte bw, + IN u4Byte f_interference, + IN u4Byte Second_ch +); + +void +phydm_receiver_blocking( + void *p_dm_void +); + diff --git a/package/kernel/rtl8192cd/phydm/phydm_acs.c b/package/kernel/rtl8192cd/phydm/phydm_acs.c index 5227a3adfb7..021702c21a1 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_acs.c +++ b/package/kernel/rtl8192cd/phydm/phydm_acs.c @@ -1,1226 +1,1226 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - - -u1Byte -ODM_GetAutoChannelSelectResult( - IN PVOID pDM_VOID, - IN u1Byte Band -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(Band == ODM_BAND_2_4G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G)); - return (u1Byte)pACS->CleanChannel_2G; - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G)); - return (u1Byte)pACS->CleanChannel_5G; - } -#else - return (u1Byte)pACS->CleanChannel_2G; -#endif - -} - -VOID -odm_AutoChannelSelectSetting( - IN PVOID pDM_VOID, - IN BOOLEAN IsEnable -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte period = 0x2710;// 40ms in default - u2Byte NHMType = 0x7; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n")); - - if(IsEnable) - {//20 ms - period = 0x1388; - NHMType = 0x1; - } - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //PHY parameters initialize for ac series - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms - //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //PHY parameters initialize for n series - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms - //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX - } -#endif -} - -VOID -odm_AutoChannelSelectInit( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - u1Byte i; - - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) - return; - - if(pACS->bForceACSResult) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n")); - - pACS->CleanChannel_2G = 1; - pACS->CleanChannel_5G = 36; - - for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) - { - pACS->Channel_Info_2G[0][i] = 0; - pACS->Channel_Info_2G[1][i] = 0; - } - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) - { - pACS->Channel_Info_5G[0][i] = 0; - pACS->Channel_Info_5G[1][i] = 0; - } - } -#endif -} - -VOID -odm_AutoChannelSelectReset( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) - return; - - if(pACS->bForceACSResult) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n")); - - odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement - Phydm_NHMCounterStatisticsReset(pDM_Odm); -#endif -} - -VOID -odm_AutoChannelSelect( - IN PVOID pDM_VOID, - IN u1Byte Channel -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - u1Byte ChannelIDX = 0, SearchIDX = 0; - u2Byte MaxScore=0; - - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n")); - return; - } - - if(pACS->bForceACSResult) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n", - pACS->CleanChannel_2G, pACS->CleanChannel_5G)); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel)); - - Phydm_GetNHMCounterStatistics(pDM_Odm); - odm_AutoChannelSelectSetting(pDM_Odm,FALSE); - - if(Channel >=1 && Channel <=14) - { - ChannelIDX = Channel - 1; - pACS->Channel_Info_2G[1][ChannelIDX]++; - - if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2) - pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) + - (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2); - else - pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX])); - - for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++) - { - if(pACS->Channel_Info_2G[1][SearchIDX] != 0) - { - if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore) - { - MaxScore = pACS->Channel_Info_2G[0][SearchIDX]; - pACS->CleanChannel_2G = SearchIDX+1; - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n", - pACS->CleanChannel_2G, MaxScore)); - - } - else if(Channel >= 36) - { - // Need to do - pACS->CleanChannel_5G = Channel; - } -#endif -} - -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) - -VOID -phydm_AutoChannelSelectSettingAP( - IN PVOID pDM_VOID, - IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING - IN u4Byte acs_step -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - PACS pACS = &pDM_Odm->DM_ACS; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n")); - - //3 Store Default Setting - if(setting == STORE_DEFAULT_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 - { - pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC); // Reg0x990 - pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994 - pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998 - pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c - pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte - } - else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890 - pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N); // Reg0x894 - pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898 - pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c - pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte - } - } - - //3 Restore Default Setting - else if(setting == RESTORE_DEFAULT_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 - { - ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x990); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0); - } - else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890); - ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x894); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28); - } - } - - //3 ACS Setting - else if(setting == ACS_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); - u2Byte period; - period = 0x61a8; - pACS->ACS_Step = acs_step; - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); - //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3); - - if(pACS->ACS_Step == 0) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff); - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); - - } - else if(pACS->ACS_Step == 1) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); - - } - - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); - //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3); - - if(pACS->ACS_Step == 0) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff); - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); - - } - else if(pACS->ACS_Step == 1) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); - - } - } - } - -} - -VOID -phydm_GetNHMStatisticsAP( - IN PVOID pDM_VOID, - IN u4Byte idx, // @ 2G, Real channel number = idx+1 - IN u4Byte acs_step -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - PACS pACS = &pDM_Odm->DM_ACS; - u4Byte value32 = 0; - u1Byte i; - - pACS->ACS_Step = acs_step; - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //4 Check if NHM result is ready - for (i=0; i<20; i++) { - - ODM_delay_ms(1); - if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) ) - break; - } - - //4 Get NHM Statistics - if ( pACS->ACS_Step==1 ) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N); - - pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N - - pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; - - } else if (pACS->ACS_Step==2) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N - - pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); - } - } - else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //4 Check if NHM result is ready - for (i=0; i<20; i++) { - - ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16)) - break; - } - - if ( pACS->ACS_Step==1 ) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC); - - pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC - - pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; - - } else if (pACS->ACS_Step==2) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC - - pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); - } - } - -} - - -//#define ACS_DEBUG_INFO //acs debug default off -/* -int phydm_AutoChannelSelectAP( - IN PVOID pDM_VOID, - IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type - IN u4Byte available_chnl_num // amount of all channels - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - prtl8192cd_priv priv = pDM_Odm->priv; - - static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; - u4Byte score[MAX_BSS_NUM], use_nhm = 0; - u4Byte minScore=0xffffffff; - u4Byte tmpScore, tmpIdx=0; - u4Byte traffic_check = 0; - u4Byte fa_count_weighting = 1; - int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0; - struct bss_desc *pBss=NULL; - -#ifdef _DEBUG_RTL8192CD_ - char tmpbuf[400]; - int len=0; -#endif - - memset(score2G, '\0', sizeof(score2G)); - memset(score5G, '\0', sizeof(score5G)); - - for (i=0; iavailable_chnl_num; i++) { - if (priv->available_chnl[i] <= 14) - idx_2G_end = i; - else - break; - } - - for (i=0; iavailable_chnl_num; i++) { - if (priv->available_chnl[i] > 14) { - idx_5G_begin = i; - break; - } - } - -// DELETE -#ifndef CONFIG_RTL_NEW_AUTOCH - for (i=0; isite_survey->count; i++) { - pBss = &priv->site_survey->bss[i]; - for (idx=0; idxavailable_chnl_num; idx++) { - if (pBss->channel == priv->available_chnl[idx]) { - if (pBss->channel <= 14) - setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1); - else - score5G[idx - idx_5G_begin] += 5; - break; - } - } - } -#endif - - if (idx_2G_end >= 0) - for (i=0; i<=idx_2G_end; i++) - score[i] = score2G[i]; - if (idx_5G_begin >= 0) - for (i=idx_5G_begin; iavailable_chnl_num; i++) - score[i] = score5G[i - idx_5G_begin]; - -#ifdef CONFIG_RTL_NEW_AUTOCH - { - u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num; - - u4Byte do_ap_check = 1, ap_ratio = 0; - - if (idx_2G_end >= 0) - ch_end = idx_2G_end+1; - if (idx_5G_begin >= 0) - ch_begin = idx_5G_begin; - -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - for (y=ch_begin; yavailable_chnl[y], - priv->chnl_ss_mac_rx_count[y], - priv->chnl_ss_mac_rx_count_40M[y], - priv->chnl_ss_fa_count[y], - score[y]); - printk("\n"); -#endif - -#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) - if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type ) - { - u4Byte tmp_score[MAX_BSS_NUM]; - memcpy(tmp_score, score, sizeof(score)); - if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) { - //memcpy(score, tmp_score, sizeof(score)); -#ifdef _DEBUG_RTL8192CD_ - printk("!! Found clean channel, select minimum FA channel\n"); -#endif - goto USE_CLN_CH; - } -#ifdef _DEBUG_RTL8192CD_ - printk("!! Not found clean channel, use NHM algorithm\n"); -#endif - use_nhm = 1; -USE_CLN_CH: - for (y=ch_begin; ynhm_cnt[y][i]; - for (j=0; jL, score: %d\n", - y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7], - priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4], - priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1], - priv->nhm_cnt[y][0], score[y]); -#endif - } - - if (!use_nhm) - memcpy(score, tmp_score, sizeof(score)); - - goto choose_ch; - } -#endif - - // For each channel, weighting behind channels with MAC RX counter - //For each channel, weighting the channel with FA counter - - for (y=ch_begin; ychnl_ss_mac_rx_count[y]; - if (priv->chnl_ss_mac_rx_count[y] > 30) - do_ap_check = 0; - if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD ) - traffic_check = 1; - -#ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) -#endif - { - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y]; - } - - //this is for CH_LOAD caculation - if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y]) - priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y]; - else - priv->chnl_ss_cca_count[y] = 0; - } - -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); - printk("\n"); -#endif - - for (y=ch_begin; ychnl_ss_mac_rx_count_40M[y]) { - score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if (priv->chnl_ss_mac_rx_count_40M[y] > 30) - do_ap_check = 0; - if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD ) - traffic_check = 1; - -#ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) -#endif - { - if ((int)(y-6) >= (int)ch_begin) - score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-5) >= (int)ch_begin) - score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+2) < (int)ch_end) - score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+5) < (int)ch_end) - score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+6) < (int)ch_end) - score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; - } - } - } - -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); - printk("\n"); - printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check); - printk("\n"); -#endif - - if( traffic_check == 0) - fa_count_weighting = 5; - else - fa_count_weighting = 1; - - for (y=ch_begin; ychnl_ss_fa_count[y]; - } - -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); - printk("\n"); -#endif - - if (do_ap_check) { - for (i=0; isite_survey->count; i++) { - pBss = &priv->site_survey->bss[i]; - for (y=ch_begin; ychannel == priv->available_chnl[y]) { - if (pBss->channel <= 14) { -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n", - pBss->channel, pBss->rssi, pBss->t_stamp[1]); - printk("\n"); -#endif - if (pBss->rssi > 60) - ap_ratio = 4; - else if (pBss->rssi > 35) - ap_ratio = 2; - else - ap_ratio = 1; - - if ((pBss->t_stamp[1] & 0x6) == 0) { - score[y] += 50 * ap_ratio; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 10 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 20 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 30 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 40 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 40 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 30 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 20 * ap_ratio; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 10 * ap_ratio; - } - else if ((pBss->t_stamp[1] & 0x4) == 0) { - score[y] += 50 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 20 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 30 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 40 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 50 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 50 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 50 * ap_ratio; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 50 * ap_ratio; - if ((int)(y+5) < (int)ch_end) - score[y+5] += 40 * ap_ratio; - if ((int)(y+6) < (int)ch_end) - score[y+6] += 30 * ap_ratio; - if ((int)(y+7) < (int)ch_end) - score[y+7] += 20 * ap_ratio; - } - else { - score[y] += 50 * ap_ratio; - if ((int)(y-7) >= (int)ch_begin) - score[y-7] += 20 * ap_ratio; - if ((int)(y-6) >= (int)ch_begin) - score[y-6] += 30 * ap_ratio; - if ((int)(y-5) >= (int)ch_begin) - score[y-5] += 40 * ap_ratio; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 50 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 50 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 50 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 50 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 40 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 30 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 20 * ap_ratio; - } - } - else { - if ((pBss->t_stamp[1] & 0x6) == 0) { - score[y] += 500; - } - else if ((pBss->t_stamp[1] & 0x4) == 0) { - score[y] += 500; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 500; - } - else { - score[y] += 500; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 500; - } - } - break; - } - } - } - } - -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - for (y=ch_begin; yavailable_chnl[y],score[y]); - printk("\n"); -#endif - -#ifdef SS_CH_LOAD_PROC - - // caculate noise level -- suggested by wilson - for (y=ch_begin; ychnl_ss_fa_count[y]>1000) { - fa_lv = 100; - } else if (priv->chnl_ss_fa_count[y]>500) { - fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66; - } else if (priv->chnl_ss_fa_count[y]>200) { - fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33; - } else if (priv->chnl_ss_fa_count[y]>100) { - fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15; - } else { - fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100; - } - if (priv->chnl_ss_cca_count[y]>400) { - cca_lv = 100; - } else if (priv->chnl_ss_cca_count[y]>200) { - cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66; - } else if (priv->chnl_ss_cca_count[y]>80) { - cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33; - } else if (priv->chnl_ss_cca_count[y]>40) { - cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15; - } else { - cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40; - } - - priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100; - - DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n", - priv->available_chnl[y], - priv->chnl_ss_fa_count[y], fa_thd, - priv->chnl_ss_cca_count[y], cca_thd, - fa_lv, - cca_lv, - score[y], - priv->chnl_ss_load[y]); - - } -#endif - } -#endif - -choose_ch: - -#ifdef DFS - // heavy weighted DFS channel - if (idx_5G_begin >= 0){ - for (i=idx_5G_begin; iavailable_chnl_num; i++) { - if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i]) - && (score[i]!= 0xffffffff)){ - score[i] += 1600; - } - } - } -#endif - - -//prevent Auto Channel selecting wrong channel in 40M mode----------------- - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) - && priv->pshare->is_40m_bw) { -#if 0 - if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) { - //Upper Primary Channel, cannot select the two lowest channels - if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { - score[0] = 0xffffffff; - score[1] = 0xffffffff; - score[2] = 0xffffffff; - score[3] = 0xffffffff; - score[4] = 0xffffffff; - - score[13] = 0xffffffff; - score[12] = 0xffffffff; - score[11] = 0xffffffff; - } - -// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { -// score[idx_5G_begin] = 0xffffffff; -// score[idx_5G_begin + 1] = 0xffffffff; -// } - } - else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) { - //Lower Primary Channel, cannot select the two highest channels - if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { - score[0] = 0xffffffff; - score[1] = 0xffffffff; - score[2] = 0xffffffff; - - score[13] = 0xffffffff; - score[12] = 0xffffffff; - score[11] = 0xffffffff; - score[10] = 0xffffffff; - score[9] = 0xffffffff; - } - -// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { -// score[priv->available_chnl_num - 2] = 0xffffffff; -// score[priv->available_chnl_num - 1] = 0xffffffff; -// } - } -#endif - for (i=0; i<=idx_2G_end; ++i) - if (priv->available_chnl[i] == 14) - score[i] = 0xffffffff; // mask chan14 - -#ifdef RTK_5G_SUPPORT - if (idx_5G_begin >= 0) { - for (i=idx_5G_begin; iavailable_chnl_num; i++) { - int ch = priv->available_chnl[i]; - if(priv->available_chnl[i] > 144) - --ch; - if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184... - score[i] = 0xffffffff; - } - } -#endif - - - } - - if (priv->pmib->dot11RFEntry.disable_ch1213) { - for (i=0; i<=idx_2G_end; ++i) { - int ch = priv->available_chnl[i]; - if ((ch == 12) || (ch == 13)) - score[i] = 0xffffffff; - } - } - - if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) || - (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) && - (idx_2G_end >= 11) && (idx_2G_end < 14)) { - score[13] = 0xffffffff; // mask chan14 - score[12] = 0xffffffff; // mask chan13 - score[11] = 0xffffffff; // mask chan12 - } - -//------------------------------------------------------------------ - -#ifdef _DEBUG_RTL8192CD_ - for (i=0; iavailable_chnl_num; i++) { - len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]); - } - strcat(tmpbuf, "\n"); - panic_printk("%s", tmpbuf); - -#endif - - if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) - { - for (i=0; iavailable_chnl_num; i++) { - if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { - tmpScore = 0; - for (j=0; j<4; j++) { - if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) - tmpScore += score[i+j]; - else - tmpScore = 0xffffffff; - } - tmpScore = tmpScore / 4; - if (minScore > tmpScore) { - minScore = tmpScore; - - tmpScore = 0xffffffff; - for (j=0; j<4; j++) { - if (score[i+j] < tmpScore) { - tmpScore = score[i+j]; - tmpIdx = i+j; - } - } - - idx = tmpIdx; - } - i += 3; - } - } - if (minScore == 0xffffffff) { - // there is no 80M channels - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; - for (i=0; iavailable_chnl_num; i++) { - if (score[i] < minScore) { - minScore = score[i]; - idx = i; - } - } - } - } - else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) - { - for (i=0; iavailable_chnl_num; i++) { - if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) { - tmpScore = 0; - for(j=0;j<2;j++) { - if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) - tmpScore += score[i+j]; - else - tmpScore = 0xffffffff; - } - tmpScore = tmpScore / 2; - if(minScore > tmpScore) { - minScore = tmpScore; - - tmpScore = 0xffffffff; - for (j=0; j<2; j++) { - if (score[i+j] < tmpScore) { - tmpScore = score[i+j]; - tmpIdx = i+j; - } - } - - idx = tmpIdx; - } - i += 1; - } - } - if (minScore == 0xffffffff) { - // there is no 40M channels - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; - for (i=0; iavailable_chnl_num; i++) { - if (score[i] < minScore) { - minScore = score[i]; - idx = i; - } - } - } - } - else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) - && (priv->available_chnl_num >= 8) ) - { - u4Byte groupScore[14]; - - memset(groupScore, 0xff , sizeof(groupScore)); - for (i=0; iavailable_chnl_num-4; i++) { - if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) { - groupScore[i] = score[i] + score[i+4]; - DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]); - if (groupScore[i] < minScore) { -#ifdef AUTOCH_SS_SPEEDUP - if(priv->pmib->miscEntry.autoch_1611_enable) - { - if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) - { - minScore = groupScore[i]; - idx = i; - } - } - else -#endif - { - minScore = groupScore[i]; - idx = i; - } - } - } - } - - if (score[idx] < score[idx+4]) { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } else { - idx = idx + 4; - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; - } - } - else - { - for (i=0; iavailable_chnl_num; i++) { - if (score[i] < minScore) { -#ifdef AUTOCH_SS_SPEEDUP - if(priv->pmib->miscEntry.autoch_1611_enable) - { - if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) - { - minScore = score[i]; - idx = i; - } - } - else -#endif - { - minScore = score[i]; - idx = i; - } - } - } - } - - if (IS_A_CUT_8881A(priv) && - (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { - if ((priv->available_chnl[idx] == 36) || - (priv->available_chnl[idx] == 52) || - (priv->available_chnl[idx] == 100) || - (priv->available_chnl[idx] == 116) || - (priv->available_chnl[idx] == 132) || - (priv->available_chnl[idx] == 149) || - (priv->available_chnl[idx] == 165)) - idx++; - else if ((priv->available_chnl[idx] == 48) || - (priv->available_chnl[idx] == 64) || - (priv->available_chnl[idx] == 112) || - (priv->available_chnl[idx] == 128) || - (priv->available_chnl[idx] == 144) || - (priv->available_chnl[idx] == 161) || - (priv->available_chnl[idx] == 177)) - idx--; - } - - minChan = priv->available_chnl[idx]; - - // skip channel 14 if don't support ofdm - if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) && - (minChan == 14)) { - score[idx] = 0xffffffff; - - minScore = 0xffffffff; - for (i=0; iavailable_chnl_num; i++) { - if (score[i] < minScore) { - minScore = score[i]; - idx = i; - } - } - minChan = priv->available_chnl[idx]; - } - -#if 0 - //Check if selected channel available for 80M/40M BW or NOT ? - if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { - if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) - { - if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) - { - //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan); - //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40; - } - } - - if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) - { - if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) - { - //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan); - //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20; - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; - } - } - } -#endif - -#ifdef CONFIG_RTL_NEW_AUTOCH - RTL_W32(RXERR_RPT, RXERR_RPT_RST); -#endif - -// auto adjust contro-sideband - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) - && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) { - -#ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { - if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } else { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; - } - - } else -#endif - { -#if 0 -#ifdef CONFIG_RTL_NEW_AUTOCH - unsigned int ch_max; - - if (priv->available_chnl[idx_2G_end] >= 13) - ch_max = 13; - else - ch_max = priv->available_chnl[idx_2G_end]; - - if ((minChan >= 5) && (minChan <= (ch_max-5))) { - if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled? - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; - } else { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } - } else -#endif - { - if (minChan < 5) { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } - else if (minChan > 7) { - GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; - } - } -#endif - } - } -//----------------------- - -#if defined(__ECOS) && defined(CONFIG_SDIO_HCI) - panic_printk("Auto channel choose ch:%d\n", minChan); -#else -#ifdef _DEBUG_RTL8192CD_ - panic_printk("Auto channel choose ch:%d\n", minChan); -#endif -#endif -#ifdef ACS_DEBUG_INFO//for debug - printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan); -#endif - - return minChan; -} -*/ - -#endif - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +u1Byte +ODM_GetAutoChannelSelectResult( + IN PVOID pDM_VOID, + IN u1Byte Band +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(Band == ODM_BAND_2_4G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G)); + return (u1Byte)pACS->CleanChannel_2G; + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G)); + return (u1Byte)pACS->CleanChannel_5G; + } +#else + return (u1Byte)pACS->CleanChannel_2G; +#endif + +} + +VOID +odm_AutoChannelSelectSetting( + IN PVOID pDM_VOID, + IN BOOLEAN IsEnable +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte period = 0x2710;// 40ms in default + u2Byte NHMType = 0x7; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n")); + + if(IsEnable) + {//20 ms + period = 0x1388; + NHMType = 0x1; + } + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //PHY parameters initialize for ac series + ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms + //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //PHY parameters initialize for n series + ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms + //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX + } +#endif +} + +VOID +odm_AutoChannelSelectInit( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + u1Byte i; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + return; + + if(pACS->bForceACSResult) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n")); + + pACS->CleanChannel_2G = 1; + pACS->CleanChannel_5G = 36; + + for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) + { + pACS->Channel_Info_2G[0][i] = 0; + pACS->Channel_Info_2G[1][i] = 0; + } + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) + { + pACS->Channel_Info_5G[0][i] = 0; + pACS->Channel_Info_5G[1][i] = 0; + } + } +#endif +} + +VOID +odm_AutoChannelSelectReset( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + return; + + if(pACS->bForceACSResult) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n")); + + odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement + Phydm_NHMCounterStatisticsReset(pDM_Odm); +#endif +} + +VOID +odm_AutoChannelSelect( + IN PVOID pDM_VOID, + IN u1Byte Channel +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + u1Byte ChannelIDX = 0, SearchIDX = 0; + u2Byte MaxScore=0; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n")); + return; + } + + if(pACS->bForceACSResult) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n", + pACS->CleanChannel_2G, pACS->CleanChannel_5G)); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel)); + + Phydm_GetNHMCounterStatistics(pDM_Odm); + odm_AutoChannelSelectSetting(pDM_Odm,FALSE); + + if(Channel >=1 && Channel <=14) + { + ChannelIDX = Channel - 1; + pACS->Channel_Info_2G[1][ChannelIDX]++; + + if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2) + pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) + + (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2); + else + pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX])); + + for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++) + { + if(pACS->Channel_Info_2G[1][SearchIDX] != 0) + { + if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore) + { + MaxScore = pACS->Channel_Info_2G[0][SearchIDX]; + pACS->CleanChannel_2G = SearchIDX+1; + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n", + pACS->CleanChannel_2G, MaxScore)); + + } + else if(Channel >= 36) + { + // Need to do + pACS->CleanChannel_5G = Channel; + } +#endif +} + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + +VOID +phydm_AutoChannelSelectSettingAP( + IN PVOID pDM_VOID, + IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING + IN u4Byte acs_step +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + PACS pACS = &pDM_Odm->DM_ACS; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n")); + + //3 Store Default Setting + if(setting == STORE_DEFAULT_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 + { + pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC); // Reg0x990 + pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994 + pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998 + pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c + pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890 + pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N); // Reg0x894 + pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898 + pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c + pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte + } + } + + //3 Restore Default Setting + else if(setting == RESTORE_DEFAULT_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 + { + ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x990); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0); + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890); + ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x894); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28); + } + } + + //3 ACS Setting + else if(setting == ACS_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); + u2Byte period; + period = 0x61a8; + pACS->ACS_Step = acs_step; + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms + ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); + //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3); + + if(pACS->ACS_Step == 0) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff); + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); + + } + else if(pACS->ACS_Step == 1) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); + + } + + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms + ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); + //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3); + + if(pACS->ACS_Step == 0) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff); + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); + + } + else if(pACS->ACS_Step == 1) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); + + } + } + } + +} + +VOID +phydm_GetNHMStatisticsAP( + IN PVOID pDM_VOID, + IN u4Byte idx, // @ 2G, Real channel number = idx+1 + IN u4Byte acs_step +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + PACS pACS = &pDM_Odm->DM_ACS; + u4Byte value32 = 0; + u1Byte i; + + pACS->ACS_Step = acs_step; + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //4 Check if NHM result is ready + for (i=0; i<20; i++) { + + ODM_delay_ms(1); + if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) ) + break; + } + + //4 Get NHM Statistics + if ( pACS->ACS_Step==1 ) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N); + + pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N + + pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; + + } else if (pACS->ACS_Step==2) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N + + pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); + } + } + else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //4 Check if NHM result is ready + for (i=0; i<20; i++) { + + ODM_delay_ms(1); + if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16)) + break; + } + + if ( pACS->ACS_Step==1 ) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC); + + pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC + + pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; + + } else if (pACS->ACS_Step==2) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC + + pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); + } + } + +} + + +//#define ACS_DEBUG_INFO //acs debug default off +/* +int phydm_AutoChannelSelectAP( + IN PVOID pDM_VOID, + IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type + IN u4Byte available_chnl_num // amount of all channels + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + prtl8192cd_priv priv = pDM_Odm->priv; + + static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; + u4Byte score[MAX_BSS_NUM], use_nhm = 0; + u4Byte minScore=0xffffffff; + u4Byte tmpScore, tmpIdx=0; + u4Byte traffic_check = 0; + u4Byte fa_count_weighting = 1; + int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0; + struct bss_desc *pBss=NULL; + +#ifdef _DEBUG_RTL8192CD_ + char tmpbuf[400]; + int len=0; +#endif + + memset(score2G, '\0', sizeof(score2G)); + memset(score5G, '\0', sizeof(score5G)); + + for (i=0; iavailable_chnl_num; i++) { + if (priv->available_chnl[i] <= 14) + idx_2G_end = i; + else + break; + } + + for (i=0; iavailable_chnl_num; i++) { + if (priv->available_chnl[i] > 14) { + idx_5G_begin = i; + break; + } + } + +// DELETE +#ifndef CONFIG_RTL_NEW_AUTOCH + for (i=0; isite_survey->count; i++) { + pBss = &priv->site_survey->bss[i]; + for (idx=0; idxavailable_chnl_num; idx++) { + if (pBss->channel == priv->available_chnl[idx]) { + if (pBss->channel <= 14) + setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1); + else + score5G[idx - idx_5G_begin] += 5; + break; + } + } + } +#endif + + if (idx_2G_end >= 0) + for (i=0; i<=idx_2G_end; i++) + score[i] = score2G[i]; + if (idx_5G_begin >= 0) + for (i=idx_5G_begin; iavailable_chnl_num; i++) + score[i] = score5G[i - idx_5G_begin]; + +#ifdef CONFIG_RTL_NEW_AUTOCH + { + u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num; + + u4Byte do_ap_check = 1, ap_ratio = 0; + + if (idx_2G_end >= 0) + ch_end = idx_2G_end+1; + if (idx_5G_begin >= 0) + ch_begin = idx_5G_begin; + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], + priv->chnl_ss_mac_rx_count[y], + priv->chnl_ss_mac_rx_count_40M[y], + priv->chnl_ss_fa_count[y], + score[y]); + printk("\n"); +#endif + +#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) + if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type ) + { + u4Byte tmp_score[MAX_BSS_NUM]; + memcpy(tmp_score, score, sizeof(score)); + if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) { + //memcpy(score, tmp_score, sizeof(score)); +#ifdef _DEBUG_RTL8192CD_ + printk("!! Found clean channel, select minimum FA channel\n"); +#endif + goto USE_CLN_CH; + } +#ifdef _DEBUG_RTL8192CD_ + printk("!! Not found clean channel, use NHM algorithm\n"); +#endif + use_nhm = 1; +USE_CLN_CH: + for (y=ch_begin; ynhm_cnt[y][i]; + for (j=0; jL, score: %d\n", + y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7], + priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4], + priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1], + priv->nhm_cnt[y][0], score[y]); +#endif + } + + if (!use_nhm) + memcpy(score, tmp_score, sizeof(score)); + + goto choose_ch; + } +#endif + + // For each channel, weighting behind channels with MAC RX counter + //For each channel, weighting the channel with FA counter + + for (y=ch_begin; ychnl_ss_mac_rx_count[y]; + if (priv->chnl_ss_mac_rx_count[y] > 30) + do_ap_check = 0; + if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD ) + traffic_check = 1; + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) +#endif + { + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y]; + } + + //this is for CH_LOAD caculation + if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y]) + priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y]; + else + priv->chnl_ss_cca_count[y] = 0; + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); +#endif + + for (y=ch_begin; ychnl_ss_mac_rx_count_40M[y]) { + score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if (priv->chnl_ss_mac_rx_count_40M[y] > 30) + do_ap_check = 0; + if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD ) + traffic_check = 1; + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) +#endif + { + if ((int)(y-6) >= (int)ch_begin) + score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-5) >= (int)ch_begin) + score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+2) < (int)ch_end) + score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+5) < (int)ch_end) + score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+6) < (int)ch_end) + score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + } + } + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); + printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check); + printk("\n"); +#endif + + if( traffic_check == 0) + fa_count_weighting = 5; + else + fa_count_weighting = 1; + + for (y=ch_begin; ychnl_ss_fa_count[y]; + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); +#endif + + if (do_ap_check) { + for (i=0; isite_survey->count; i++) { + pBss = &priv->site_survey->bss[i]; + for (y=ch_begin; ychannel == priv->available_chnl[y]) { + if (pBss->channel <= 14) { +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n", + pBss->channel, pBss->rssi, pBss->t_stamp[1]); + printk("\n"); +#endif + if (pBss->rssi > 60) + ap_ratio = 4; + else if (pBss->rssi > 35) + ap_ratio = 2; + else + ap_ratio = 1; + + if ((pBss->t_stamp[1] & 0x6) == 0) { + score[y] += 50 * ap_ratio; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 10 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 20 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 30 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 40 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 40 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 30 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 20 * ap_ratio; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 10 * ap_ratio; + } + else if ((pBss->t_stamp[1] & 0x4) == 0) { + score[y] += 50 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 20 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 30 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 40 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 50 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 50 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 50 * ap_ratio; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 50 * ap_ratio; + if ((int)(y+5) < (int)ch_end) + score[y+5] += 40 * ap_ratio; + if ((int)(y+6) < (int)ch_end) + score[y+6] += 30 * ap_ratio; + if ((int)(y+7) < (int)ch_end) + score[y+7] += 20 * ap_ratio; + } + else { + score[y] += 50 * ap_ratio; + if ((int)(y-7) >= (int)ch_begin) + score[y-7] += 20 * ap_ratio; + if ((int)(y-6) >= (int)ch_begin) + score[y-6] += 30 * ap_ratio; + if ((int)(y-5) >= (int)ch_begin) + score[y-5] += 40 * ap_ratio; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 50 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 50 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 50 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 50 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 40 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 30 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 20 * ap_ratio; + } + } + else { + if ((pBss->t_stamp[1] & 0x6) == 0) { + score[y] += 500; + } + else if ((pBss->t_stamp[1] & 0x4) == 0) { + score[y] += 500; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 500; + } + else { + score[y] += 500; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 500; + } + } + break; + } + } + } + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y],score[y]); + printk("\n"); +#endif + +#ifdef SS_CH_LOAD_PROC + + // caculate noise level -- suggested by wilson + for (y=ch_begin; ychnl_ss_fa_count[y]>1000) { + fa_lv = 100; + } else if (priv->chnl_ss_fa_count[y]>500) { + fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66; + } else if (priv->chnl_ss_fa_count[y]>200) { + fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33; + } else if (priv->chnl_ss_fa_count[y]>100) { + fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15; + } else { + fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100; + } + if (priv->chnl_ss_cca_count[y]>400) { + cca_lv = 100; + } else if (priv->chnl_ss_cca_count[y]>200) { + cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66; + } else if (priv->chnl_ss_cca_count[y]>80) { + cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33; + } else if (priv->chnl_ss_cca_count[y]>40) { + cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15; + } else { + cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40; + } + + priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100; + + DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n", + priv->available_chnl[y], + priv->chnl_ss_fa_count[y], fa_thd, + priv->chnl_ss_cca_count[y], cca_thd, + fa_lv, + cca_lv, + score[y], + priv->chnl_ss_load[y]); + + } +#endif + } +#endif + +choose_ch: + +#ifdef DFS + // heavy weighted DFS channel + if (idx_5G_begin >= 0){ + for (i=idx_5G_begin; iavailable_chnl_num; i++) { + if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i]) + && (score[i]!= 0xffffffff)){ + score[i] += 1600; + } + } + } +#endif + + +//prevent Auto Channel selecting wrong channel in 40M mode----------------- + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) + && priv->pshare->is_40m_bw) { +#if 0 + if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) { + //Upper Primary Channel, cannot select the two lowest channels + if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { + score[0] = 0xffffffff; + score[1] = 0xffffffff; + score[2] = 0xffffffff; + score[3] = 0xffffffff; + score[4] = 0xffffffff; + + score[13] = 0xffffffff; + score[12] = 0xffffffff; + score[11] = 0xffffffff; + } + +// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { +// score[idx_5G_begin] = 0xffffffff; +// score[idx_5G_begin + 1] = 0xffffffff; +// } + } + else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) { + //Lower Primary Channel, cannot select the two highest channels + if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { + score[0] = 0xffffffff; + score[1] = 0xffffffff; + score[2] = 0xffffffff; + + score[13] = 0xffffffff; + score[12] = 0xffffffff; + score[11] = 0xffffffff; + score[10] = 0xffffffff; + score[9] = 0xffffffff; + } + +// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { +// score[priv->available_chnl_num - 2] = 0xffffffff; +// score[priv->available_chnl_num - 1] = 0xffffffff; +// } + } +#endif + for (i=0; i<=idx_2G_end; ++i) + if (priv->available_chnl[i] == 14) + score[i] = 0xffffffff; // mask chan14 + +#ifdef RTK_5G_SUPPORT + if (idx_5G_begin >= 0) { + for (i=idx_5G_begin; iavailable_chnl_num; i++) { + int ch = priv->available_chnl[i]; + if(priv->available_chnl[i] > 144) + --ch; + if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184... + score[i] = 0xffffffff; + } + } +#endif + + + } + + if (priv->pmib->dot11RFEntry.disable_ch1213) { + for (i=0; i<=idx_2G_end; ++i) { + int ch = priv->available_chnl[i]; + if ((ch == 12) || (ch == 13)) + score[i] = 0xffffffff; + } + } + + if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) || + (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) && + (idx_2G_end >= 11) && (idx_2G_end < 14)) { + score[13] = 0xffffffff; // mask chan14 + score[12] = 0xffffffff; // mask chan13 + score[11] = 0xffffffff; // mask chan12 + } + +//------------------------------------------------------------------ + +#ifdef _DEBUG_RTL8192CD_ + for (i=0; iavailable_chnl_num; i++) { + len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]); + } + strcat(tmpbuf, "\n"); + panic_printk("%s", tmpbuf); + +#endif + + if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) + { + for (i=0; iavailable_chnl_num; i++) { + if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { + tmpScore = 0; + for (j=0; j<4; j++) { + if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) + tmpScore += score[i+j]; + else + tmpScore = 0xffffffff; + } + tmpScore = tmpScore / 4; + if (minScore > tmpScore) { + minScore = tmpScore; + + tmpScore = 0xffffffff; + for (j=0; j<4; j++) { + if (score[i+j] < tmpScore) { + tmpScore = score[i+j]; + tmpIdx = i+j; + } + } + + idx = tmpIdx; + } + i += 3; + } + } + if (minScore == 0xffffffff) { + // there is no 80M channels + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + } + } + else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) + { + for (i=0; iavailable_chnl_num; i++) { + if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) { + tmpScore = 0; + for(j=0;j<2;j++) { + if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) + tmpScore += score[i+j]; + else + tmpScore = 0xffffffff; + } + tmpScore = tmpScore / 2; + if(minScore > tmpScore) { + minScore = tmpScore; + + tmpScore = 0xffffffff; + for (j=0; j<2; j++) { + if (score[i+j] < tmpScore) { + tmpScore = score[i+j]; + tmpIdx = i+j; + } + } + + idx = tmpIdx; + } + i += 1; + } + } + if (minScore == 0xffffffff) { + // there is no 40M channels + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + } + } + else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + && (priv->available_chnl_num >= 8) ) + { + u4Byte groupScore[14]; + + memset(groupScore, 0xff , sizeof(groupScore)); + for (i=0; iavailable_chnl_num-4; i++) { + if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) { + groupScore[i] = score[i] + score[i+4]; + DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]); + if (groupScore[i] < minScore) { +#ifdef AUTOCH_SS_SPEEDUP + if(priv->pmib->miscEntry.autoch_1611_enable) + { + if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) + { + minScore = groupScore[i]; + idx = i; + } + } + else +#endif + { + minScore = groupScore[i]; + idx = i; + } + } + } + } + + if (score[idx] < score[idx+4]) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } else { + idx = idx + 4; + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + } + else + { + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { +#ifdef AUTOCH_SS_SPEEDUP + if(priv->pmib->miscEntry.autoch_1611_enable) + { + if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) + { + minScore = score[i]; + idx = i; + } + } + else +#endif + { + minScore = score[i]; + idx = i; + } + } + } + } + + if (IS_A_CUT_8881A(priv) && + (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + if ((priv->available_chnl[idx] == 36) || + (priv->available_chnl[idx] == 52) || + (priv->available_chnl[idx] == 100) || + (priv->available_chnl[idx] == 116) || + (priv->available_chnl[idx] == 132) || + (priv->available_chnl[idx] == 149) || + (priv->available_chnl[idx] == 165)) + idx++; + else if ((priv->available_chnl[idx] == 48) || + (priv->available_chnl[idx] == 64) || + (priv->available_chnl[idx] == 112) || + (priv->available_chnl[idx] == 128) || + (priv->available_chnl[idx] == 144) || + (priv->available_chnl[idx] == 161) || + (priv->available_chnl[idx] == 177)) + idx--; + } + + minChan = priv->available_chnl[idx]; + + // skip channel 14 if don't support ofdm + if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) && + (minChan == 14)) { + score[idx] = 0xffffffff; + + minScore = 0xffffffff; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + minChan = priv->available_chnl[idx]; + } + +#if 0 + //Check if selected channel available for 80M/40M BW or NOT ? + if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { + if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) + { + if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) + { + //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan); + //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40; + } + } + + if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + { + if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) + { + //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan); + //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20; + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + } + } + } +#endif + +#ifdef CONFIG_RTL_NEW_AUTOCH + RTL_W32(RXERR_RPT, RXERR_RPT_RST); +#endif + +// auto adjust contro-sideband + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) + && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) { + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { + if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } else { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + + } else +#endif + { +#if 0 +#ifdef CONFIG_RTL_NEW_AUTOCH + unsigned int ch_max; + + if (priv->available_chnl[idx_2G_end] >= 13) + ch_max = 13; + else + ch_max = priv->available_chnl[idx_2G_end]; + + if ((minChan >= 5) && (minChan <= (ch_max-5))) { + if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled? + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } else { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } + } else +#endif + { + if (minChan < 5) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } + else if (minChan > 7) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + } +#endif + } + } +//----------------------- + +#if defined(__ECOS) && defined(CONFIG_SDIO_HCI) + panic_printk("Auto channel choose ch:%d\n", minChan); +#else +#ifdef _DEBUG_RTL8192CD_ + panic_printk("Auto channel choose ch:%d\n", minChan); +#endif +#endif +#ifdef ACS_DEBUG_INFO//for debug + printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan); +#endif + + return minChan; +} +*/ + +#endif + + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_acs.h b/package/kernel/rtl8192cd/phydm/phydm_acs.h index 92efdf3cb09..a12e120d97c 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_acs.h +++ b/package/kernel/rtl8192cd/phydm/phydm_acs.h @@ -1,106 +1,106 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMACS_H__ -#define __PHYDMACS_H__ - -#define ACS_VERSION "1.1" /*20150729 by YuChen*/ -#define CLM_VERSION "1.0" - -#define ODM_MAX_CHANNEL_2G 14 -#define ODM_MAX_CHANNEL_5G 24 - -// For phydm_AutoChannelSelectSettingAP() -#define STORE_DEFAULT_NHM_SETTING 0 -#define RESTORE_DEFAULT_NHM_SETTING 1 -#define ACS_NHM_SETTING 2 - -typedef struct _ACS_ -{ - BOOLEAN bForceACSResult; - u1Byte CleanChannel_2G; - u1Byte CleanChannel_5G; - u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times - u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; - -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) - u1Byte ACS_Step; - // NHM Count 0-11 - u1Byte NHM_Cnt[14][11]; - - // AC-Series, for storing previous setting - u4Byte Reg0x990; - u4Byte Reg0x994; - u4Byte Reg0x998; - u4Byte Reg0x99C; - u1Byte Reg0x9A0; // u1Byte - - // N-Series, for storing previous setting - u4Byte Reg0x890; - u4Byte Reg0x894; - u4Byte Reg0x898; - u4Byte Reg0x89C; - u1Byte Reg0xE28; // u1Byte -#endif - -}ACS, *PACS; - - -VOID -odm_AutoChannelSelectInit( - IN PVOID pDM_VOID -); - -VOID -odm_AutoChannelSelectReset( - IN PVOID pDM_VOID -); - -VOID -odm_AutoChannelSelect( - IN PVOID pDM_VOID, - IN u1Byte Channel -); - -u1Byte -ODM_GetAutoChannelSelectResult( - IN PVOID pDM_VOID, - IN u1Byte Band -); - -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) - -VOID -phydm_AutoChannelSelectSettingAP( - IN PVOID pDM_VOID, - IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING - IN u4Byte acs_step -); - -VOID -phydm_GetNHMStatisticsAP( - IN PVOID pDM_VOID, - IN u4Byte idx, // @ 2G, Real channel number = idx+1 - IN u4Byte acs_step -); - -#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMACS_H__ +#define __PHYDMACS_H__ + +#define ACS_VERSION "1.1" /*20150729 by YuChen*/ +#define CLM_VERSION "1.0" + +#define ODM_MAX_CHANNEL_2G 14 +#define ODM_MAX_CHANNEL_5G 24 + +// For phydm_AutoChannelSelectSettingAP() +#define STORE_DEFAULT_NHM_SETTING 0 +#define RESTORE_DEFAULT_NHM_SETTING 1 +#define ACS_NHM_SETTING 2 + +typedef struct _ACS_ +{ + BOOLEAN bForceACSResult; + u1Byte CleanChannel_2G; + u1Byte CleanChannel_5G; + u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times + u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + u1Byte ACS_Step; + // NHM Count 0-11 + u1Byte NHM_Cnt[14][11]; + + // AC-Series, for storing previous setting + u4Byte Reg0x990; + u4Byte Reg0x994; + u4Byte Reg0x998; + u4Byte Reg0x99C; + u1Byte Reg0x9A0; // u1Byte + + // N-Series, for storing previous setting + u4Byte Reg0x890; + u4Byte Reg0x894; + u4Byte Reg0x898; + u4Byte Reg0x89C; + u1Byte Reg0xE28; // u1Byte +#endif + +}ACS, *PACS; + + +VOID +odm_AutoChannelSelectInit( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelectReset( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelect( + IN PVOID pDM_VOID, + IN u1Byte Channel +); + +u1Byte +ODM_GetAutoChannelSelectResult( + IN PVOID pDM_VOID, + IN u1Byte Band +); + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + +VOID +phydm_AutoChannelSelectSettingAP( + IN PVOID pDM_VOID, + IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING + IN u4Byte acs_step +); + +VOID +phydm_GetNHMStatisticsAP( + IN PVOID pDM_VOID, + IN u4Byte idx, // @ 2G, Real channel number = idx+1 + IN u4Byte acs_step +); + +#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + #endif //#ifndef __PHYDMACS_H__ \ No newline at end of file diff --git a/package/kernel/rtl8192cd/phydm/phydm_adaptivity.h b/package/kernel/rtl8192cd/phydm/phydm_adaptivity.h index b4ea9f4c0a1..769ff58e97d 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_adaptivity.h +++ b/package/kernel/rtl8192cd/phydm/phydm_adaptivity.h @@ -1,228 +1,228 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMADAPTIVITY_H__ -#define __PHYDMADAPTIVITY_H__ - -#define ADAPTIVITY_VERSION "9.3.4" /*20160512 changed by Kevin, modify 0xce8[13]=1 for 8197F when adaptivity is enabled*/ - -#define PwdBUpperBound 7 -#define DFIRloss 5 - -#define L2H_TH_AbsUpperBound_mode2 0x46 -#define L2H_TH_AbsLowerBound_mode2 0x30 -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -typedef enum _tag_PhyDM_REGULATION_Type { - REGULATION_FCC = 0, - REGULATION_MKK = 1, - REGULATION_ETSI = 2, - REGULATION_WW = 3, - - MAX_REGULATION_NUM = 4 -} PhyDM_REGULATION_TYPE; -#endif - -typedef enum _PHYDM_ADAPTIVITY_Info_Definition { - PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, - PHYDM_ADAPINFO_DCBACKOFF, - PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, - PHYDM_ADAPINFO_TH_L2H_INI, - PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, - PHYDM_ADAPINFO_AP_NUM_TH - -} PHYDM_ADAPINFO_E; - - -typedef enum tag_PhyDM_set_LNA { - PhyDM_disable_LNA = 0, - PhyDM_enable_LNA = 1, -} PhyDM_set_LNA; - - -typedef enum tag_PhyDM_TRx_MUX_Type -{ - PhyDM_SHUTDOWN = 0, - PhyDM_STANDBY_MODE = 1, - PhyDM_TX_MODE = 2, - PhyDM_RX_MODE = 3 -}PhyDM_Trx_MUX_Type; - -typedef enum tag_PhyDM_MACEDCCA_Type -{ - PhyDM_IGNORE_EDCCA = 0, - PhyDM_DONT_IGNORE_EDCCA = 1 -}PhyDM_MACEDCCA_Type; - -typedef struct _ADAPTIVITY_STATISTICS { - s1Byte TH_L2H_ini_backup; - s1Byte TH_EDCCA_HL_diff_backup; - s1Byte IGI_Base; - u1Byte IGI_target; - u1Byte NHMWait; - s1Byte H2L_lb; - s1Byte L2H_lb; - BOOLEAN bFirstLink; - BOOLEAN bCheck; - BOOLEAN DynamicLinkAdaptivity; - u1Byte APNumTH; - u1Byte AdajustIGILevel; - BOOLEAN AcsForAdaptivity; - s1Byte backupL2H; - s1Byte backupH2L; - BOOLEAN bStopEDCCA; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_WORK_ITEM phydm_pauseEDCCAWorkItem; - RT_WORK_ITEM phydm_resumeEDCCAWorkItem; -#endif -} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; - -VOID -phydm_pauseEDCCA( - IN PVOID pDM_VOID, - IN BOOLEAN bPasueEDCCA -); - -VOID -Phydm_CheckAdaptivity( - IN PVOID pDM_VOID - ); - -VOID -Phydm_CheckEnvironment( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatisticsInit( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatistics( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatisticsReset( - IN PVOID pDM_VOID -); - -VOID -Phydm_GetNHMCounterStatistics( - IN PVOID pDM_VOID -); - -VOID -Phydm_MACEDCCAState( - IN PVOID pDM_VOID, - IN PhyDM_MACEDCCA_Type State -); - -VOID -Phydm_SetEDCCAThreshold( - IN PVOID pDM_VOID, - IN s1Byte H2L, - IN s1Byte L2H -); - -VOID -Phydm_SetTRxMux( - IN PVOID pDM_VOID, - IN PhyDM_Trx_MUX_Type txMode, - IN PhyDM_Trx_MUX_Type rxMode -); - -BOOLEAN -Phydm_CalNHMcnt( - IN PVOID pDM_VOID -); - -VOID -Phydm_SearchPwdBLowerBound( - IN PVOID pDM_VOID -); - -VOID -phydm_adaptivityInfoInit( - IN PVOID pDM_VOID, - IN PHYDM_ADAPINFO_E CmnInfo, - IN u4Byte Value - ); - -VOID -Phydm_AdaptivityInit( - IN PVOID pDM_VOID - ); - -VOID -Phydm_Adaptivity( - IN PVOID pDM_VOID, - IN u1Byte IGI - ); - -VOID -phydm_setEDCCAThresholdAPI( - IN PVOID pDM_VOID, - IN u1Byte IGI -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Phydm_DisableEDCCA( - IN PVOID pDM_VOID -); - -VOID -Phydm_DynamicEDCCA( - IN PVOID pDM_VOID -); - -VOID -Phydm_AdaptivityBSOD( - IN PVOID pDM_VOID -); - -#endif - -VOID -phydm_pauseEDCCA_WorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -phydm_resumeEDCCA_WorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -void -phydm_set_forgetting_factor( - IN PVOID pDM_VOID -); - -#endif + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.3.4" /*20160512 changed by Kevin, modify 0xce8[13]=1 for 8197F when adaptivity is enabled*/ + +#define PwdBUpperBound 7 +#define DFIRloss 5 + +#define L2H_TH_AbsUpperBound_mode2 0x46 +#define L2H_TH_AbsLowerBound_mode2 0x30 +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +typedef enum _tag_PhyDM_REGULATION_Type { + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + + MAX_REGULATION_NUM = 4 +} PhyDM_REGULATION_TYPE; +#endif + +typedef enum _PHYDM_ADAPTIVITY_Info_Definition { + PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, + PHYDM_ADAPINFO_DCBACKOFF, + PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, + PHYDM_ADAPINFO_TH_L2H_INI, + PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, + PHYDM_ADAPINFO_AP_NUM_TH + +} PHYDM_ADAPINFO_E; + + +typedef enum tag_PhyDM_set_LNA { + PhyDM_disable_LNA = 0, + PhyDM_enable_LNA = 1, +} PhyDM_set_LNA; + + +typedef enum tag_PhyDM_TRx_MUX_Type +{ + PhyDM_SHUTDOWN = 0, + PhyDM_STANDBY_MODE = 1, + PhyDM_TX_MODE = 2, + PhyDM_RX_MODE = 3 +}PhyDM_Trx_MUX_Type; + +typedef enum tag_PhyDM_MACEDCCA_Type +{ + PhyDM_IGNORE_EDCCA = 0, + PhyDM_DONT_IGNORE_EDCCA = 1 +}PhyDM_MACEDCCA_Type; + +typedef struct _ADAPTIVITY_STATISTICS { + s1Byte TH_L2H_ini_backup; + s1Byte TH_EDCCA_HL_diff_backup; + s1Byte IGI_Base; + u1Byte IGI_target; + u1Byte NHMWait; + s1Byte H2L_lb; + s1Byte L2H_lb; + BOOLEAN bFirstLink; + BOOLEAN bCheck; + BOOLEAN DynamicLinkAdaptivity; + u1Byte APNumTH; + u1Byte AdajustIGILevel; + BOOLEAN AcsForAdaptivity; + s1Byte backupL2H; + s1Byte backupH2L; + BOOLEAN bStopEDCCA; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_WORK_ITEM phydm_pauseEDCCAWorkItem; + RT_WORK_ITEM phydm_resumeEDCCAWorkItem; +#endif +} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; + +VOID +phydm_pauseEDCCA( + IN PVOID pDM_VOID, + IN BOOLEAN bPasueEDCCA +); + +VOID +Phydm_CheckAdaptivity( + IN PVOID pDM_VOID + ); + +VOID +Phydm_CheckEnvironment( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +); + +VOID +Phydm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +Phydm_MACEDCCAState( + IN PVOID pDM_VOID, + IN PhyDM_MACEDCCA_Type State +); + +VOID +Phydm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +Phydm_SetTRxMux( + IN PVOID pDM_VOID, + IN PhyDM_Trx_MUX_Type txMode, + IN PhyDM_Trx_MUX_Type rxMode +); + +BOOLEAN +Phydm_CalNHMcnt( + IN PVOID pDM_VOID +); + +VOID +Phydm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +); + +VOID +phydm_adaptivityInfoInit( + IN PVOID pDM_VOID, + IN PHYDM_ADAPINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +Phydm_AdaptivityInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI + ); + +VOID +phydm_setEDCCAThresholdAPI( + IN PVOID pDM_VOID, + IN u1Byte IGI +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Phydm_DisableEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_DynamicEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityBSOD( + IN PVOID pDM_VOID +); + +#endif + +VOID +phydm_pauseEDCCA_WorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +phydm_resumeEDCCA_WorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +void +phydm_set_forgetting_factor( + IN PVOID pDM_VOID +); + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.c b/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.c index 16779fa2493..5f1c21db900 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.c +++ b/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.c @@ -1,764 +1,764 @@ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8197F_SUPPORT == 1)||(RTL8822B_SUPPORT == 1)) -#include "rtl8197f/Hal8197FPhyReg.h" -#include "WlanHAL/HalMac88XX/halmac_reg2.h" -#else -#include "WlanHAL/HalHeader/HalComReg.h" -#endif -#endif - -#if (PHYDM_LA_MODE_SUPPORT == 1) - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - -#if WPP_SOFTWARE_TRACE -#include "phydm_adc_sampling.tmh" -#endif - -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -BOOLEAN -phydm_la_buffer_allocate( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - DbgPrint("[LA mode BufferAllocate]\n"); - - if (ADCSmpBuf->Length == 0) { - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (PlatformAllocateMemoryWithZero(Adapter, (void **)&(ADCSmpBuf->Octet), ADCSmpBuf->buffer_size) != RT_STATUS_SUCCESS) { - #else - ODM_AllocateMemory(pDM_Odm, (PVOID*)&ADCSmpBuf->Octet, ADCSmpBuf->buffer_size); - if (!ADCSmpBuf->Octet) { - #endif - return FALSE; - } else - ADCSmpBuf->Length = ADCSmpBuf->buffer_size; - } - - return TRUE; -} -#endif - -VOID -phydm_la_get_tx_pkt_buf( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - u4Byte i = 0, value32, DataL = 0, DataH = 0; - u4Byte Addr, Finish_Addr; - u4Byte End_Addr = (ADCSmpBuf->start_pos + ADCSmpBuf->buffer_size)-1; /*End_Addr = 0x3ffff;*/ - BOOLEAN bRoundUp; - static u4Byte page = 0xFF; - u4Byte smp_cnt = 0, smp_number = 0, Addr_8byte = 0; - u1Byte backup_DMA; - - ODM_Memory_Set(pDM_Odm, ADCSmpBuf->Octet, 0, ADCSmpBuf->Length); - ODM_Write1Byte(pDM_Odm, 0x0106, 0x69); - - DbgPrint("GetTxPktBuf\n"); - - value32 = ODM_Read4Byte(pDM_Odm, 0x7c0); - bRoundUp = (BOOLEAN)((value32 & BIT31) >> 31); - Finish_Addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ - -#if (RTL8197F_SUPPORT) - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ODM_SetBBReg(pDM_Odm, 0x7c0, BIT0, 0x0); - - /*Stop DMA*/ - backup_DMA = ODM_GetMACReg(pDM_Odm, 0x300, bMaskLWord); - ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA|0x7fff); - - /*move LA mode content from IMEM to TxPktBuffer - Source : OCPBASE_IMEM 0x00000000 - Destination : OCPBASE_TXBUF 0x18780000 - Length : 64K*/ - GET_HAL_INTERFACE(pDM_Odm->priv)->InitDDMAHandler(pDM_Odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); - } -#endif - - if(bRoundUp) { - Addr = (Finish_Addr+1)<<3; - DbgPrint("bRoundUp = ((%d)), Finish_Addr=((0x%x)), 0x7c0=((0x%x)) \n", bRoundUp, Finish_Addr, value32); - smp_number = ((ADCSmpBuf->buffer_size)>>3); /*Byte to 64Byte*/ - } else { - Addr = ADCSmpBuf->start_pos; - - Addr_8byte = Addr>>3; - if(Addr_8byte > Finish_Addr) - smp_number = Addr_8byte - Finish_Addr; - else - smp_number = Finish_Addr - Addr_8byte; - - DbgPrint("bRoundUp = ((%d)), Finish_Addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", bRoundUp, Finish_Addr, Addr_8byte, smp_number); - - } - /* - DbgPrint("bRoundUp = %d, Finish_Addr=0x%x, value32=0x%x\n", bRoundUp, Finish_Addr, value32); - DbgPrint("End_Addr = %x, ADCSmpBuf->start_pos = 0x%x, ADCSmpBuf->buffer_size = 0x%x\n", End_Addr, ADCSmpBuf->start_pos, ADCSmpBuf->buffer_size); - */ - - - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - for (Addr = 0x0, i = 0; Addr < End_Addr; Addr += 8, i += 2) { /*64K byte*/ - if ((Addr&0xfff) == 0) - ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+(Addr >> 12)); - DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord); - DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord); - - DbgPrint("%08x%08x\n", DataH, DataL); - } - } else { - while (Addr != (Finish_Addr<<3)) { - if (page != (Addr >> 12)) { - /*Reg140=0x780+(Addr>>12), Addr=0x30~0x3F, total 16 pages*/ - page = (Addr >> 12); - } - ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+page); - - /*pDataL = 0x8000+(Addr&0xfff);*/ - DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord); - DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord); - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - ADCSmpBuf->Octet[i] = DataH; - ADCSmpBuf->Octet[i+1] = DataL; - #endif - - #if DBG - DbgPrint("%08x%08x\n", DataH, DataL); - #else - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1])); - #endif - #endif - - i = i + 2; - - if ((Addr+8) >= End_Addr) - Addr = ADCSmpBuf->start_pos; - else - Addr = Addr + 8; - - smp_cnt ++; - if (smp_cnt >= (smp_number-1)) - break; - } - DbgPrint("smp_cnt = ((%d))\n", smp_cnt); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt)); - #endif - } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/ -#endif - -} - -VOID -phydm_la_mode_set_mac_iq_dump( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - u4Byte reg_value; - - ODM_Write1Byte(pDM_Odm, 0x7c0, 0); /*clear all 0x7c0*/ - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT0, 1); /*Enable LA mode HW block*/ - - if (AdcSmp->la_trig_mode == PHYDM_MAC_TRIG) { - - AdcSmp->is_bb_trigger = 0; - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT2, 1); /*polling bit for MAC mode*/ - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT4|BIT3, AdcSmp->la_trigger_edge); /*trigger mode for MAC*/ - - DbgPrint("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", AdcSmp->la_mac_ref_mask, AdcSmp->la_TrigSigSel, AdcSmp->la_dbg_port); - /*[Set MAC Debug Port]*/ - ODM_SetMACReg(pDM_Odm, 0xF4, BIT16, 1); - ODM_SetMACReg(pDM_Odm, 0x38, 0xff0000, AdcSmp->la_dbg_port); - ODM_SetMACReg(pDM_Odm, 0x7c4, bMaskDWord, AdcSmp->la_mac_ref_mask); - ODM_SetMACReg(pDM_Odm, 0x7c8, bMaskDWord, AdcSmp->la_TrigSigSel); - - } else { - - AdcSmp->is_bb_trigger = 1; - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT1, 1); /*polling bit for BB ADC mode*/ - - if (AdcSmp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { - - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT3, 1); /*polling bit for MAC trigger event*/ - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT7|BIT6, AdcSmp->la_TrigSigSel); - - if (AdcSmp->la_TrigSigSel == ADCSMP_TRIG_REG) - ODM_SetMACReg(pDM_Odm, 0x7c0, BIT5, 1); /* manual trigger 0x7C0[5] = 0 -> 1*/ - } - } - - reg_value = ODM_GetBBReg(pDM_Odm, 0x7c0, 0xff); - DbgPrint("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value)); - #endif - -} - -void -phydm_la_mode_set_dma_type( - IN PVOID pDM_VOID, - IN u1Byte la_dma_type -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - DbgPrint("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type)); - #endif - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0xf00, la_dma_type); /*0x95C[11:8]*/ - else - ODM_SetBBReg(pDM_Odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ -} - -VOID -phydm_adc_smp_start( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - u1Byte tmpU1b; - u1Byte while_cnt = 0; - u1Byte polling_ok = FALSE, target_polling_bit; - - phydm_la_mode_bb_setting(pDM_Odm); - phydm_la_mode_set_dma_type(pDM_Odm, AdcSmp->la_dma_type); - phydm_la_mode_set_trigger_time(pDM_Odm, AdcSmp->la_TriggerTime); - - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, 0xd00, BIT26, 0x1); - else { /*for 8814A and 8822B?*/ - ODM_Write1Byte(pDM_Odm, 0x198c, 0x7); - ODM_Write1Byte(pDM_Odm, 0x8b4, 0x80); - //ODM_SetBBReg(pDM_Odm, 0x8b4, BIT7, 1); - } - - phydm_la_mode_set_mac_iq_dump(pDM_Odm); -//return; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(pDM_Odm->priv); -#endif - - target_polling_bit = (AdcSmp->is_bb_trigger) ? BIT1 : BIT2; - do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ - tmpU1b = ODM_Read1Byte(pDM_Odm, 0x7c0); - - if (AdcSmp->ADCSmpState != ADCSMP_STATE_SET) { - DbgPrint("[State Error] ADCSmpState != ADCSMP_STATE_SET\n"); - break; - - } else if (tmpU1b & target_polling_bit) { - ODM_delay_ms(100); - while_cnt = while_cnt + 1; - continue; - } else { - DbgPrint("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); - polling_ok = TRUE; - break; - } - } while (while_cnt < 20); - - if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) { - - if (polling_ok) - phydm_la_get_tx_pkt_buf(pDM_Odm); - else { - DbgPrint("[Polling timeout]\n"); - } - } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(pDM_Odm->priv); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) - AdcSmp->ADCSmpState = ADCSMP_STATE_QUERY; -#endif - - DbgPrint("[LA mode] LA_pattern_count = ((%d))\n", AdcSmp->la_count); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", AdcSmp->la_count)); - #endif - - - ADCSmp_Stop(pDM_Odm); - - if (AdcSmp->la_count == 0) { - DbgPrint("LA Dump finished ---------->\n\n\n"); - /**/ - } else { - AdcSmp->la_count --; - DbgPrint("LA Dump more ---------->\n\n\n"); - ADCSmp_Set(pDM_Odm, AdcSmp->la_trig_mode, AdcSmp->la_TrigSigSel, AdcSmp->la_dma_type, AdcSmp->la_TriggerTime, 0); - } - -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmpWorkItemCallback( - IN PVOID pContext - ) -{ - PADAPTER Adapter = (PADAPTER)pContext; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - - DbgPrint("[WorkItem Call back] LA_State=((%d))\n", AdcSmp->ADCSmpState); - phydm_adc_smp_start(pDM_Odm); -} -#endif - -VOID -ADCSmp_Set( - IN PVOID pDM_VOID, - IN u1Byte trig_mode, - IN u4Byte TrigSigSel, - IN u1Byte DmaDataSigSel, - IN u4Byte TriggerTime, - IN u2Byte PollingTime - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN is_set_success = TRUE; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - - AdcSmp->la_trig_mode = trig_mode; - AdcSmp->la_TrigSigSel = TrigSigSel; - AdcSmp->la_dma_type = DmaDataSigSel; - AdcSmp->la_TriggerTime = TriggerTime; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) - if (AdcSmp->ADCSmpState != ADCSMP_STATE_IDLE) - is_set_success = FALSE; - else if (AdcSmp->ADCSmpBuf.Length == 0) - is_set_success = phydm_la_buffer_allocate(pDM_Odm); -#endif - - if (is_set_success) { - AdcSmp->ADCSmpState = ADCSMP_STATE_SET; - - DbgPrint("[LA Set Success] LA_State=((%d))\n", AdcSmp->ADCSmpState); - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - DbgPrint("ADCSmp_work_item_index = ((%d))\n", AdcSmp->la_work_item_index); - if (AdcSmp->la_work_item_index != 0) { - ODM_ScheduleWorkItem(&(AdcSmp->ADCSmpWorkItem_1)); - AdcSmp->la_work_item_index = 0; - } else { - ODM_ScheduleWorkItem(&(AdcSmp->ADCSmpWorkItem)); - AdcSmp->la_work_item_index = 1; - } - #else - phydm_adc_smp_start(pDM_Odm); - #endif - } else { - DbgPrint("[LA Set Fail] LA_State=((%d))\n", AdcSmp->ADCSmpState); - } - - -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -RT_STATUS -ADCSmp_Query( - IN PVOID pDM_VOID, - IN ULONG InformationBufferLength, - OUT PVOID InformationBuffer, - OUT PULONG BytesWritten - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - RT_STATUS retStatus = RT_STATUS_SUCCESS; - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - DbgPrint("[%s] LA_State=((%d))", __func__, AdcSmp->ADCSmpState); - - if (InformationBufferLength != ADCSmpBuf->buffer_size) { - *BytesWritten = 0; - retStatus = RT_STATUS_RESOURCE; - } else if (ADCSmpBuf->Length != ADCSmpBuf->buffer_size) { - *BytesWritten = 0; - retStatus = RT_STATUS_RESOURCE; - } else if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY) { - *BytesWritten = 0; - retStatus = RT_STATUS_PENDING; - } else { - ODM_MoveMemory(pDM_Odm, InformationBuffer, ADCSmpBuf->Octet, ADCSmpBuf->buffer_size); - *BytesWritten = ADCSmpBuf->buffer_size; - - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; - } - - DbgPrint("Return Status %d\n", retStatus); - - return retStatus; -} -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - -VOID -ADCSmp_Query( - IN PVOID pDM_VOID, - OUT PVOID output, - IN u4Byte out_len, - IN pu4Byte pused - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - u4Byte used = *pused; - u4Byte i; - /* struct timespec t; */ - /* rtw_get_current_timespec(&t); */ - - DbgPrint("%s ADCSmpState %d", __func__, AdcSmp->ADCSmpState); - - for (i=0;i<(ADCSmpBuf->Length>>2)-2;i+=2) { - PHYDM_SNPRINTF((output+used, out_len-used, - "%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1])); - } - - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); - /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ - *pused = used; -} - -s4Byte -ADCSmp_Get_SampleCounts( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - return ((ADCSmpBuf->Length>>2)-2); -} - -s4Byte -ADCSmp_Query_SingleData( - IN PVOID pDM_VOID, - OUT PVOID output, - IN u4Byte out_len, - IN u4Byte index - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - u4Byte used = 0; - - //DbgPrint("%s ADCSmpState %d\n", __func__, AdcSmp->ADCSmpState); - if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY ) { - PHYDM_SNPRINTF((output+used, out_len-used, - "Error: la data is not ready yet ...\n")); - return -1; - } - - if (index < ((ADCSmpBuf->Length>>2)-2)) { - PHYDM_SNPRINTF((output+used, out_len-used, "%08x%08x\n", - ADCSmpBuf->Octet[index], ADCSmpBuf->Octet[index+1])); - } - return 0; -} - -#endif - -VOID -ADCSmp_Stop( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; - DbgPrint("[LA_Stop] LA_state = ((%d))\n", AdcSmp->ADCSmpState); -} - -VOID -ADCSmp_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ADCSmpBuf->start_pos = 0x30000; - ADCSmpBuf->buffer_size = 0x10000; - } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { - ADCSmpBuf->start_pos = 0x20000; - ADCSmpBuf->buffer_size = 0x20000; - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ADCSmpBuf->start_pos = 0x00000; - ADCSmpBuf->buffer_size = 0x10000; - } else if (pDM_Odm->SupportICType & ODM_RTL8821C) { - ADCSmpBuf->start_pos = 0x8000; - ADCSmpBuf->buffer_size = 0x8000; - } - -} - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -VOID -ADCSmp_DeInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - ADCSmp_Stop(pDM_Odm); - - if (ADCSmpBuf->Length != 0x0) { - ODM_FreeMemory(pDM_Odm, ADCSmpBuf->Octet, ADCSmpBuf->Length); - ADCSmpBuf->Length = 0x0; - } -} - -#endif - - -VOID -phydm_la_mode_bb_setting( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - - u1Byte trig_mode = AdcSmp->la_trig_mode; - u4Byte TrigSigSel = AdcSmp->la_TrigSigSel; - u4Byte DbgPort = AdcSmp->la_dbg_port; - u1Byte bTriggerEdge = AdcSmp->la_trigger_edge; - u1Byte sampling_rate = AdcSmp->la_smp_rate; - - DbgPrint("1. [LA mode bb_setting] trig_mode = ((%d)), DbgPort = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", - trig_mode, DbgPort, bTriggerEdge, sampling_rate, TrigSigSel); - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), DbgPort = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", - trig_mode, DbgPort, bTriggerEdge, sampling_rate, TrigSigSel)); - #endif - - if (trig_mode == PHYDM_MAC_TRIG) - TrigSigSel = 0; /*ignore this setting*/ - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - if (trig_mode == PHYDM_ADC_RF0_TRIG) { - ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 9); /*DBGOUT_RFC_a[31:0]*/ - } else if (trig_mode == PHYDM_ADC_RF1_TRIG) { - ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 8); /*DBGOUT_RFC_b[31:0]*/ - } else { - ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 0); - } - /* - (0:) '{ofdm_dbg[31:0]}' - (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' - (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' - (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' - (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' - (5:) '{dbg_iqk_anta}' - (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' - (7:) '{dbg_iqk_antb}' - (8:) '{DBGOUT_RFC_b[31:0]}' - (9:) '{DBGOUT_RFC_a[31:0]}' - (a:) '{dbg_ofdm}' - (b:) '{dbg_cck}' - */ - - ODM_SetBBReg(pDM_Odm, 0x198C , BIT2|BIT1|BIT0, 7); /*disable dbg clk gating*/ - - /*dword= ODM_GetBBReg(pDM_Odm, 0x8FC, bMaskDWord);*/ - /*DbgPrint("dbg_port = ((0x%x))\n", dword);*/ - ODM_SetBBReg(pDM_Odm , 0x95C, 0x1f, TrigSigSel); /*0x95C[4:0], BB debug port bit*/ - ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, DbgPort); - ODM_SetBBReg(pDM_Odm, 0x95C , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ - ODM_SetBBReg(pDM_Odm, 0x95c, 0xe0, sampling_rate); - /* (0:) '80MHz' - (1:) '40MHz' - (2:) '20MHz' - (3:) '10MHz' - (4:) '5MHz' - (5:) '2.5MHz' - (6:) '1.25MHz' - (7:) '160MHz (for BW160 ic)' - */ - } else { - ODM_SetBBReg(pDM_Odm, 0x9a0, 0x1f, TrigSigSel); /*0x9A0[4:0], BB debug port bit*/ - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, DbgPort); - ODM_SetBBReg(pDM_Odm, 0x9A0 , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ - ODM_SetBBReg(pDM_Odm, 0x9A0, 0xe0, sampling_rate); - /* (0:) '80MHz' - (1:) '40MHz' - (2:) '20MHz' - (3:) '10MHz' - (4:) '5MHz' - (5:) '2.5MHz' - (6:) '1.25MHz' - (7:) '160MHz (for BW160 ic)' - */ - } -} - -void -phydm_la_mode_set_trigger_time( - IN PVOID pDM_VOID, - IN u4Byte TriggerTime_mu_sec -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte TriggerTime_unit_num; - u4Byte time_unit = 0; - - if (TriggerTime_mu_sec < 128) { - time_unit = 0; /*unit: 1mu sec*/ - } else if (TriggerTime_mu_sec < 256) { - time_unit = 1; /*unit: 2mu sec*/ - } else if (TriggerTime_mu_sec < 512) { - time_unit = 2; /*unit: 4mu sec*/ - } else if (TriggerTime_mu_sec < 1024) { - time_unit = 3; /*unit: 8mu sec*/ - } else if (TriggerTime_mu_sec < 2048) { - time_unit = 4; /*unit: 16mu sec*/ - } else if (TriggerTime_mu_sec < 4096) { - time_unit = 5; /*unit: 32mu sec*/ - } else if (TriggerTime_mu_sec < 8192) { - time_unit = 6; /*unit: 64mu sec*/ - } - - TriggerTime_unit_num = (u1Byte)(TriggerTime_mu_sec>>time_unit); - - DbgPrint("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", TriggerTime_unit_num, time_unit); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", TriggerTime_unit_num, time_unit)); - #endif - - ODM_SetMACReg(pDM_Odm, 0x7cc , BIT20|BIT19|BIT18, time_unit); - ODM_SetMACReg(pDM_Odm, 0x7c0, 0x7f00, (TriggerTime_unit_num& 0x7f)); - -} - - -VOID -phydm_lamode_trigger_setting( - IN PVOID pDM_VOID, - IN char input[][16], - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len, - IN u4Byte input_num - ) - { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - u1Byte trig_mode, DmaDataSigSel; - u4Byte TrigSigSel; - BOOLEAN bEnableLaMode, bTriggerEdge; - u4Byte DbgPort, TriggerTime_mu_sec; - u4Byte mac_ref_signal_mask; - u1Byte sampling_rate = 0, i; - char help[] = "-h"; - u4Byte var1[10] = {0}; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - if (pDM_Odm->SupportICType & PHYDM_IC_SUPPORT_LA_MODE) { - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - bEnableLaMode = (BOOLEAN)var1[0]; - /*DbgPrint("echo cmd input_num = %d\n", input_num);*/ - - if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output+used, out_len-used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:DbgPort[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {PollingTime/ref_mask} {DbgPort} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); - /**/ - } else if ((bEnableLaMode == 1)) { - - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); - - trig_mode = (u1Byte)var1[1]; - - if (trig_mode == PHYDM_MAC_TRIG) { - PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); - } else { - PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); - } - TrigSigSel = var1[2]; - - PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); - PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); - PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); - PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); - PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); - PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]); - PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]); - - DmaDataSigSel = (u1Byte)var1[3]; - TriggerTime_mu_sec = var1[4]; /*unit: us*/ - - AdcSmp->la_mac_ref_mask = var1[5]; - AdcSmp->la_dbg_port = var1[6]; - AdcSmp->la_trigger_edge = (u1Byte) var1[7]; - AdcSmp->la_smp_rate = (u1Byte)(var1[8] & 0x7); - AdcSmp->la_count = var1[9]; - - - DbgPrint("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9])); - #endif - - PHYDM_SNPRINTF((output+used, out_len-used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, TrigSigSel, DmaDataSigSel)); - PHYDM_SNPRINTF((output+used, out_len-used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", TriggerTime_mu_sec, AdcSmp->la_mac_ref_mask, AdcSmp->la_dbg_port)); - PHYDM_SNPRINTF((output+used, out_len-used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", AdcSmp->la_trigger_edge, (80>>AdcSmp->la_smp_rate), AdcSmp->la_count )); - - ADCSmp_Set(pDM_Odm, trig_mode, TrigSigSel, DmaDataSigSel, TriggerTime_mu_sec, 0); - - } else { - ADCSmp_Stop(pDM_Odm); - PHYDM_SNPRINTF((output+used, out_len-used, "Disable LA mode\n")); - } - } - } - -#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/ - +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8197F_SUPPORT == 1)||(RTL8822B_SUPPORT == 1)) +#include "rtl8197f/Hal8197FPhyReg.h" +#include "WlanHAL/HalMac88XX/halmac_reg2.h" +#else +#include "WlanHAL/HalHeader/HalComReg.h" +#endif +#endif + +#if (PHYDM_LA_MODE_SUPPORT == 1) + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if WPP_SOFTWARE_TRACE +#include "phydm_adc_sampling.tmh" +#endif + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +BOOLEAN +phydm_la_buffer_allocate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + + DbgPrint("[LA mode BufferAllocate]\n"); + + if (ADCSmpBuf->Length == 0) { + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (PlatformAllocateMemoryWithZero(Adapter, (void **)&(ADCSmpBuf->Octet), ADCSmpBuf->buffer_size) != RT_STATUS_SUCCESS) { + #else + ODM_AllocateMemory(pDM_Odm, (PVOID*)&ADCSmpBuf->Octet, ADCSmpBuf->buffer_size); + if (!ADCSmpBuf->Octet) { + #endif + return FALSE; + } else + ADCSmpBuf->Length = ADCSmpBuf->buffer_size; + } + + return TRUE; +} +#endif + +VOID +phydm_la_get_tx_pkt_buf( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + u4Byte i = 0, value32, DataL = 0, DataH = 0; + u4Byte Addr, Finish_Addr; + u4Byte End_Addr = (ADCSmpBuf->start_pos + ADCSmpBuf->buffer_size)-1; /*End_Addr = 0x3ffff;*/ + BOOLEAN bRoundUp; + static u4Byte page = 0xFF; + u4Byte smp_cnt = 0, smp_number = 0, Addr_8byte = 0; + u1Byte backup_DMA; + + ODM_Memory_Set(pDM_Odm, ADCSmpBuf->Octet, 0, ADCSmpBuf->Length); + ODM_Write1Byte(pDM_Odm, 0x0106, 0x69); + + DbgPrint("GetTxPktBuf\n"); + + value32 = ODM_Read4Byte(pDM_Odm, 0x7c0); + bRoundUp = (BOOLEAN)((value32 & BIT31) >> 31); + Finish_Addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + +#if (RTL8197F_SUPPORT) + if (pDM_Odm->SupportICType & ODM_RTL8197F) { + ODM_SetBBReg(pDM_Odm, 0x7c0, BIT0, 0x0); + + /*Stop DMA*/ + backup_DMA = ODM_GetMACReg(pDM_Odm, 0x300, bMaskLWord); + ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA|0x7fff); + + /*move LA mode content from IMEM to TxPktBuffer + Source : OCPBASE_IMEM 0x00000000 + Destination : OCPBASE_TXBUF 0x18780000 + Length : 64K*/ + GET_HAL_INTERFACE(pDM_Odm->priv)->InitDDMAHandler(pDM_Odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); + } +#endif + + if(bRoundUp) { + Addr = (Finish_Addr+1)<<3; + DbgPrint("bRoundUp = ((%d)), Finish_Addr=((0x%x)), 0x7c0=((0x%x)) \n", bRoundUp, Finish_Addr, value32); + smp_number = ((ADCSmpBuf->buffer_size)>>3); /*Byte to 64Byte*/ + } else { + Addr = ADCSmpBuf->start_pos; + + Addr_8byte = Addr>>3; + if(Addr_8byte > Finish_Addr) + smp_number = Addr_8byte - Finish_Addr; + else + smp_number = Finish_Addr - Addr_8byte; + + DbgPrint("bRoundUp = ((%d)), Finish_Addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", bRoundUp, Finish_Addr, Addr_8byte, smp_number); + + } + /* + DbgPrint("bRoundUp = %d, Finish_Addr=0x%x, value32=0x%x\n", bRoundUp, Finish_Addr, value32); + DbgPrint("End_Addr = %x, ADCSmpBuf->start_pos = 0x%x, ADCSmpBuf->buffer_size = 0x%x\n", End_Addr, ADCSmpBuf->start_pos, ADCSmpBuf->buffer_size); + */ + + + if (pDM_Odm->SupportICType & ODM_RTL8197F) { + for (Addr = 0x0, i = 0; Addr < End_Addr; Addr += 8, i += 2) { /*64K byte*/ + if ((Addr&0xfff) == 0) + ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+(Addr >> 12)); + DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord); + DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord); + + DbgPrint("%08x%08x\n", DataH, DataL); + } + } else { + while (Addr != (Finish_Addr<<3)) { + if (page != (Addr >> 12)) { + /*Reg140=0x780+(Addr>>12), Addr=0x30~0x3F, total 16 pages*/ + page = (Addr >> 12); + } + ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+page); + + /*pDataL = 0x8000+(Addr&0xfff);*/ + DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord); + DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + ADCSmpBuf->Octet[i] = DataH; + ADCSmpBuf->Octet[i+1] = DataL; + #endif + + #if DBG + DbgPrint("%08x%08x\n", DataH, DataL); + #else + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1])); + #endif + #endif + + i = i + 2; + + if ((Addr+8) >= End_Addr) + Addr = ADCSmpBuf->start_pos; + else + Addr = Addr + 8; + + smp_cnt ++; + if (smp_cnt >= (smp_number-1)) + break; + } + DbgPrint("smp_cnt = ((%d))\n", smp_cnt); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt)); + #endif + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/ +#endif + +} + +VOID +phydm_la_mode_set_mac_iq_dump( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + u4Byte reg_value; + + ODM_Write1Byte(pDM_Odm, 0x7c0, 0); /*clear all 0x7c0*/ + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT0, 1); /*Enable LA mode HW block*/ + + if (AdcSmp->la_trig_mode == PHYDM_MAC_TRIG) { + + AdcSmp->is_bb_trigger = 0; + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT2, 1); /*polling bit for MAC mode*/ + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT4|BIT3, AdcSmp->la_trigger_edge); /*trigger mode for MAC*/ + + DbgPrint("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", AdcSmp->la_mac_ref_mask, AdcSmp->la_TrigSigSel, AdcSmp->la_dbg_port); + /*[Set MAC Debug Port]*/ + ODM_SetMACReg(pDM_Odm, 0xF4, BIT16, 1); + ODM_SetMACReg(pDM_Odm, 0x38, 0xff0000, AdcSmp->la_dbg_port); + ODM_SetMACReg(pDM_Odm, 0x7c4, bMaskDWord, AdcSmp->la_mac_ref_mask); + ODM_SetMACReg(pDM_Odm, 0x7c8, bMaskDWord, AdcSmp->la_TrigSigSel); + + } else { + + AdcSmp->is_bb_trigger = 1; + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT1, 1); /*polling bit for BB ADC mode*/ + + if (AdcSmp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT3, 1); /*polling bit for MAC trigger event*/ + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT7|BIT6, AdcSmp->la_TrigSigSel); + + if (AdcSmp->la_TrigSigSel == ADCSMP_TRIG_REG) + ODM_SetMACReg(pDM_Odm, 0x7c0, BIT5, 1); /* manual trigger 0x7C0[5] = 0 -> 1*/ + } + } + + reg_value = ODM_GetBBReg(pDM_Odm, 0x7c0, 0xff); + DbgPrint("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value)); + #endif + +} + +void +phydm_la_mode_set_dma_type( + IN PVOID pDM_VOID, + IN u1Byte la_dma_type +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + DbgPrint("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type)); + #endif + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0xf00, la_dma_type); /*0x95C[11:8]*/ + else + ODM_SetBBReg(pDM_Odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ +} + +VOID +phydm_adc_smp_start( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + u1Byte tmpU1b; + u1Byte while_cnt = 0; + u1Byte polling_ok = FALSE, target_polling_bit; + + phydm_la_mode_bb_setting(pDM_Odm); + phydm_la_mode_set_dma_type(pDM_Odm, AdcSmp->la_dma_type); + phydm_la_mode_set_trigger_time(pDM_Odm, AdcSmp->la_TriggerTime); + + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ODM_SetBBReg(pDM_Odm, 0xd00, BIT26, 0x1); + else { /*for 8814A and 8822B?*/ + ODM_Write1Byte(pDM_Odm, 0x198c, 0x7); + ODM_Write1Byte(pDM_Odm, 0x8b4, 0x80); + //ODM_SetBBReg(pDM_Odm, 0x8b4, BIT7, 1); + } + + phydm_la_mode_set_mac_iq_dump(pDM_Odm); +//return; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(pDM_Odm->priv); +#endif + + target_polling_bit = (AdcSmp->is_bb_trigger) ? BIT1 : BIT2; + do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ + tmpU1b = ODM_Read1Byte(pDM_Odm, 0x7c0); + + if (AdcSmp->ADCSmpState != ADCSMP_STATE_SET) { + DbgPrint("[State Error] ADCSmpState != ADCSMP_STATE_SET\n"); + break; + + } else if (tmpU1b & target_polling_bit) { + ODM_delay_ms(100); + while_cnt = while_cnt + 1; + continue; + } else { + DbgPrint("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); + polling_ok = TRUE; + break; + } + } while (while_cnt < 20); + + if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) { + + if (polling_ok) + phydm_la_get_tx_pkt_buf(pDM_Odm); + else { + DbgPrint("[Polling timeout]\n"); + } + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_resume(pDM_Odm->priv); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) + AdcSmp->ADCSmpState = ADCSMP_STATE_QUERY; +#endif + + DbgPrint("[LA mode] LA_pattern_count = ((%d))\n", AdcSmp->la_count); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", AdcSmp->la_count)); + #endif + + + ADCSmp_Stop(pDM_Odm); + + if (AdcSmp->la_count == 0) { + DbgPrint("LA Dump finished ---------->\n\n\n"); + /**/ + } else { + AdcSmp->la_count --; + DbgPrint("LA Dump more ---------->\n\n\n"); + ADCSmp_Set(pDM_Odm, AdcSmp->la_trig_mode, AdcSmp->la_TrigSigSel, AdcSmp->la_dma_type, AdcSmp->la_TriggerTime, 0); + } + +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +VOID +ADCSmpWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + + DbgPrint("[WorkItem Call back] LA_State=((%d))\n", AdcSmp->ADCSmpState); + phydm_adc_smp_start(pDM_Odm); +} +#endif + +VOID +ADCSmp_Set( + IN PVOID pDM_VOID, + IN u1Byte trig_mode, + IN u4Byte TrigSigSel, + IN u1Byte DmaDataSigSel, + IN u4Byte TriggerTime, + IN u2Byte PollingTime + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN is_set_success = TRUE; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + + AdcSmp->la_trig_mode = trig_mode; + AdcSmp->la_TrigSigSel = TrigSigSel; + AdcSmp->la_dma_type = DmaDataSigSel; + AdcSmp->la_TriggerTime = TriggerTime; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) + if (AdcSmp->ADCSmpState != ADCSMP_STATE_IDLE) + is_set_success = FALSE; + else if (AdcSmp->ADCSmpBuf.Length == 0) + is_set_success = phydm_la_buffer_allocate(pDM_Odm); +#endif + + if (is_set_success) { + AdcSmp->ADCSmpState = ADCSMP_STATE_SET; + + DbgPrint("[LA Set Success] LA_State=((%d))\n", AdcSmp->ADCSmpState); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + DbgPrint("ADCSmp_work_item_index = ((%d))\n", AdcSmp->la_work_item_index); + if (AdcSmp->la_work_item_index != 0) { + ODM_ScheduleWorkItem(&(AdcSmp->ADCSmpWorkItem_1)); + AdcSmp->la_work_item_index = 0; + } else { + ODM_ScheduleWorkItem(&(AdcSmp->ADCSmpWorkItem)); + AdcSmp->la_work_item_index = 1; + } + #else + phydm_adc_smp_start(pDM_Odm); + #endif + } else { + DbgPrint("[LA Set Fail] LA_State=((%d))\n", AdcSmp->ADCSmpState); + } + + +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +RT_STATUS +ADCSmp_Query( + IN PVOID pDM_VOID, + IN ULONG InformationBufferLength, + OUT PVOID InformationBuffer, + OUT PULONG BytesWritten + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + RT_STATUS retStatus = RT_STATUS_SUCCESS; + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + + DbgPrint("[%s] LA_State=((%d))", __func__, AdcSmp->ADCSmpState); + + if (InformationBufferLength != ADCSmpBuf->buffer_size) { + *BytesWritten = 0; + retStatus = RT_STATUS_RESOURCE; + } else if (ADCSmpBuf->Length != ADCSmpBuf->buffer_size) { + *BytesWritten = 0; + retStatus = RT_STATUS_RESOURCE; + } else if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY) { + *BytesWritten = 0; + retStatus = RT_STATUS_PENDING; + } else { + ODM_MoveMemory(pDM_Odm, InformationBuffer, ADCSmpBuf->Octet, ADCSmpBuf->buffer_size); + *BytesWritten = ADCSmpBuf->buffer_size; + + AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; + } + + DbgPrint("Return Status %d\n", retStatus); + + return retStatus; +} +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +VOID +ADCSmp_Query( + IN PVOID pDM_VOID, + OUT PVOID output, + IN u4Byte out_len, + IN pu4Byte pused + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + u4Byte used = *pused; + u4Byte i; + /* struct timespec t; */ + /* rtw_get_current_timespec(&t); */ + + DbgPrint("%s ADCSmpState %d", __func__, AdcSmp->ADCSmpState); + + for (i=0;i<(ADCSmpBuf->Length>>2)-2;i+=2) { + PHYDM_SNPRINTF((output+used, out_len-used, + "%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1])); + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ + *pused = used; +} + +s4Byte +ADCSmp_Get_SampleCounts( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + + return ((ADCSmpBuf->Length>>2)-2); +} + +s4Byte +ADCSmp_Query_SingleData( + IN PVOID pDM_VOID, + OUT PVOID output, + IN u4Byte out_len, + IN u4Byte index + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + u4Byte used = 0; + + //DbgPrint("%s ADCSmpState %d\n", __func__, AdcSmp->ADCSmpState); + if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY ) { + PHYDM_SNPRINTF((output+used, out_len-used, + "Error: la data is not ready yet ...\n")); + return -1; + } + + if (index < ((ADCSmpBuf->Length>>2)-2)) { + PHYDM_SNPRINTF((output+used, out_len-used, "%08x%08x\n", + ADCSmpBuf->Octet[index], ADCSmpBuf->Octet[index+1])); + } + return 0; +} + +#endif + +VOID +ADCSmp_Stop( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + + AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; + DbgPrint("[LA_Stop] LA_state = ((%d))\n", AdcSmp->ADCSmpState); +} + +VOID +ADCSmp_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + + AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; + + if (pDM_Odm->SupportICType & ODM_RTL8814A) { + ADCSmpBuf->start_pos = 0x30000; + ADCSmpBuf->buffer_size = 0x10000; + } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { + ADCSmpBuf->start_pos = 0x20000; + ADCSmpBuf->buffer_size = 0x20000; + } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { + ADCSmpBuf->start_pos = 0x00000; + ADCSmpBuf->buffer_size = 0x10000; + } else if (pDM_Odm->SupportICType & ODM_RTL8821C) { + ADCSmpBuf->start_pos = 0x8000; + ADCSmpBuf->buffer_size = 0x8000; + } + +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +VOID +ADCSmp_DeInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + + ADCSmp_Stop(pDM_Odm); + + if (ADCSmpBuf->Length != 0x0) { + ODM_FreeMemory(pDM_Odm, ADCSmpBuf->Octet, ADCSmpBuf->Length); + ADCSmpBuf->Length = 0x0; + } +} + +#endif + + +VOID +phydm_la_mode_bb_setting( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + + u1Byte trig_mode = AdcSmp->la_trig_mode; + u4Byte TrigSigSel = AdcSmp->la_TrigSigSel; + u4Byte DbgPort = AdcSmp->la_dbg_port; + u1Byte bTriggerEdge = AdcSmp->la_trigger_edge; + u1Byte sampling_rate = AdcSmp->la_smp_rate; + + DbgPrint("1. [LA mode bb_setting] trig_mode = ((%d)), DbgPort = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", + trig_mode, DbgPort, bTriggerEdge, sampling_rate, TrigSigSel); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), DbgPort = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", + trig_mode, DbgPort, bTriggerEdge, sampling_rate, TrigSigSel)); + #endif + + if (trig_mode == PHYDM_MAC_TRIG) + TrigSigSel = 0; /*ignore this setting*/ + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + if (trig_mode == PHYDM_ADC_RF0_TRIG) { + ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 9); /*DBGOUT_RFC_a[31:0]*/ + } else if (trig_mode == PHYDM_ADC_RF1_TRIG) { + ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 8); /*DBGOUT_RFC_b[31:0]*/ + } else { + ODM_SetBBReg(pDM_Odm, 0x8f8, BIT25|BIT24|BIT23|BIT22, 0); + } + /* + (0:) '{ofdm_dbg[31:0]}' + (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' + (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' + (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' + (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' + (5:) '{dbg_iqk_anta}' + (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' + (7:) '{dbg_iqk_antb}' + (8:) '{DBGOUT_RFC_b[31:0]}' + (9:) '{DBGOUT_RFC_a[31:0]}' + (a:) '{dbg_ofdm}' + (b:) '{dbg_cck}' + */ + + ODM_SetBBReg(pDM_Odm, 0x198C , BIT2|BIT1|BIT0, 7); /*disable dbg clk gating*/ + + /*dword= ODM_GetBBReg(pDM_Odm, 0x8FC, bMaskDWord);*/ + /*DbgPrint("dbg_port = ((0x%x))\n", dword);*/ + ODM_SetBBReg(pDM_Odm , 0x95C, 0x1f, TrigSigSel); /*0x95C[4:0], BB debug port bit*/ + ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, DbgPort); + ODM_SetBBReg(pDM_Odm, 0x95C , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ + ODM_SetBBReg(pDM_Odm, 0x95c, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ + } else { + ODM_SetBBReg(pDM_Odm, 0x9a0, 0x1f, TrigSigSel); /*0x9A0[4:0], BB debug port bit*/ + ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, DbgPort); + ODM_SetBBReg(pDM_Odm, 0x9A0 , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ + ODM_SetBBReg(pDM_Odm, 0x9A0, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ + } +} + +void +phydm_la_mode_set_trigger_time( + IN PVOID pDM_VOID, + IN u4Byte TriggerTime_mu_sec +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte TriggerTime_unit_num; + u4Byte time_unit = 0; + + if (TriggerTime_mu_sec < 128) { + time_unit = 0; /*unit: 1mu sec*/ + } else if (TriggerTime_mu_sec < 256) { + time_unit = 1; /*unit: 2mu sec*/ + } else if (TriggerTime_mu_sec < 512) { + time_unit = 2; /*unit: 4mu sec*/ + } else if (TriggerTime_mu_sec < 1024) { + time_unit = 3; /*unit: 8mu sec*/ + } else if (TriggerTime_mu_sec < 2048) { + time_unit = 4; /*unit: 16mu sec*/ + } else if (TriggerTime_mu_sec < 4096) { + time_unit = 5; /*unit: 32mu sec*/ + } else if (TriggerTime_mu_sec < 8192) { + time_unit = 6; /*unit: 64mu sec*/ + } + + TriggerTime_unit_num = (u1Byte)(TriggerTime_mu_sec>>time_unit); + + DbgPrint("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", TriggerTime_unit_num, time_unit); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", TriggerTime_unit_num, time_unit)); + #endif + + ODM_SetMACReg(pDM_Odm, 0x7cc , BIT20|BIT19|BIT18, time_unit); + ODM_SetMACReg(pDM_Odm, 0x7c0, 0x7f00, (TriggerTime_unit_num& 0x7f)); + +} + + +VOID +phydm_lamode_trigger_setting( + IN PVOID pDM_VOID, + IN char input[][16], + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len, + IN u4Byte input_num + ) + { + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + u1Byte trig_mode, DmaDataSigSel; + u4Byte TrigSigSel; + BOOLEAN bEnableLaMode, bTriggerEdge; + u4Byte DbgPort, TriggerTime_mu_sec; + u4Byte mac_ref_signal_mask; + u1Byte sampling_rate = 0, i; + char help[] = "-h"; + u4Byte var1[10] = {0}; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + if (pDM_Odm->SupportICType & PHYDM_IC_SUPPORT_LA_MODE) { + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + bEnableLaMode = (BOOLEAN)var1[0]; + /*DbgPrint("echo cmd input_num = %d\n", input_num);*/ + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output+used, out_len-used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:DbgPort[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {PollingTime/ref_mask} {DbgPort} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); + /**/ + } else if ((bEnableLaMode == 1)) { + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + trig_mode = (u1Byte)var1[1]; + + if (trig_mode == PHYDM_MAC_TRIG) { + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); + } else { + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + } + TrigSigSel = var1[2]; + + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); + PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); + PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); + PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]); + PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]); + + DmaDataSigSel = (u1Byte)var1[3]; + TriggerTime_mu_sec = var1[4]; /*unit: us*/ + + AdcSmp->la_mac_ref_mask = var1[5]; + AdcSmp->la_dbg_port = var1[6]; + AdcSmp->la_trigger_edge = (u1Byte) var1[7]; + AdcSmp->la_smp_rate = (u1Byte)(var1[8] & 0x7); + AdcSmp->la_count = var1[9]; + + + DbgPrint("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9])); + #endif + + PHYDM_SNPRINTF((output+used, out_len-used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, TrigSigSel, DmaDataSigSel)); + PHYDM_SNPRINTF((output+used, out_len-used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", TriggerTime_mu_sec, AdcSmp->la_mac_ref_mask, AdcSmp->la_dbg_port)); + PHYDM_SNPRINTF((output+used, out_len-used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", AdcSmp->la_trigger_edge, (80>>AdcSmp->la_smp_rate), AdcSmp->la_count )); + + ADCSmp_Set(pDM_Odm, trig_mode, TrigSigSel, DmaDataSigSel, TriggerTime_mu_sec, 0); + + } else { + ADCSmp_Stop(pDM_Odm); + PHYDM_SNPRINTF((output+used, out_len-used, "Disable LA mode\n")); + } + } + } + +#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.h b/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.h index b2bf195ce05..760b951e22c 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.h +++ b/package/kernel/rtl8192cd/phydm/phydm_adc_sampling.h @@ -1,148 +1,148 @@ -#ifndef __INC_ADCSMP_H -#define __INC_ADCSMP_H - -#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */ - -#if (PHYDM_LA_MODE_SUPPORT == 1) - -typedef struct _RT_ADCSMP_STRING { - pu4Byte Octet; - u4Byte Length; - u4Byte buffer_size; - u4Byte start_pos; -} RT_ADCSMP_STRING, *PRT_ADCSMP_STRING; - - -typedef enum _RT_ADCSMP_TRIG_SEL { - PHYDM_ADC_BB_TRIG = 0, - PHYDM_ADC_MAC_TRIG = 1, - PHYDM_ADC_RF0_TRIG = 2, - PHYDM_ADC_RF1_TRIG = 3, - PHYDM_MAC_TRIG = 4 -} RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL; - - -typedef enum _RT_ADCSMP_TRIG_SIG_SEL { - ADCSMP_TRIG_CRCOK = 0, - ADCSMP_TRIG_CRCFAIL = 1, - ADCSMP_TRIG_CCA = 2, - ADCSMP_TRIG_REG = 3 -} RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL; - - -typedef enum _RT_ADCSMP_STATE { - ADCSMP_STATE_IDLE = 0, - ADCSMP_STATE_SET = 1, - ADCSMP_STATE_QUERY = 2 -} RT_ADCSMP_STATE, *PRT_ADCSMP_STATE; - - -typedef struct _RT_ADCSMP { - RT_ADCSMP_STRING ADCSmpBuf; - RT_ADCSMP_STATE ADCSmpState; - u1Byte la_trig_mode; - u4Byte la_TrigSigSel; - u1Byte la_dma_type; - u4Byte la_TriggerTime; - u4Byte la_mac_ref_mask; - u4Byte la_dbg_port; - u1Byte la_trigger_edge; - u1Byte la_smp_rate; - u4Byte la_count; - u1Byte is_bb_trigger; - u1Byte la_work_item_index; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM ADCSmpWorkItem; - RT_WORK_ITEM ADCSmpWorkItem_1; - #endif -} RT_ADCSMP, *PRT_ADCSMP; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmpWorkItemCallback( - IN PVOID pContext -); -#endif - -VOID -ADCSmp_Set( - IN PVOID pDM_VOID, - IN u1Byte trig_mode, - IN u4Byte TrigSigSel, - IN u1Byte DmaDataSigSel, - IN u4Byte TriggerTime, - IN u2Byte PollingTime -); - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -RT_STATUS -ADCSmp_Query( - IN PVOID pDM_VOID, - IN ULONG InformationBufferLength, - OUT PVOID InformationBuffer, - OUT PULONG BytesWritten -); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -VOID -ADCSmp_Query( - IN PVOID pDM_VOID, - OUT PVOID output, - IN u4Byte out_len, - IN pu4Byte pused -); - -s4Byte -ADCSmp_Get_SampleCounts( - IN PVOID pDM_VOID -); - -s4Byte -ADCSmp_Query_SingleData( - IN PVOID pDM_VOID, - OUT PVOID output, - IN u4Byte out_len, - IN u4Byte index -); - -#endif -VOID -ADCSmp_Stop( - IN PVOID pDM_VOID -); - -VOID -ADCSmp_Init( - IN PVOID pDM_VOID -); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -VOID -ADCSmp_DeInit( - IN PVOID pDM_VOID -); -#endif - -VOID -phydm_la_mode_bb_setting( - IN PVOID pDM_VOID -); - -void -phydm_la_mode_set_trigger_time( - IN PVOID pDM_VOID, - IN u4Byte TriggerTime_mu_sec -); - -VOID -phydm_lamode_trigger_setting( - IN PVOID pDM_VOID, - IN char input[][16], - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len, - IN u4Byte input_num - ); -#endif -#endif - +#ifndef __INC_ADCSMP_H +#define __INC_ADCSMP_H + +#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */ + +#if (PHYDM_LA_MODE_SUPPORT == 1) + +typedef struct _RT_ADCSMP_STRING { + pu4Byte Octet; + u4Byte Length; + u4Byte buffer_size; + u4Byte start_pos; +} RT_ADCSMP_STRING, *PRT_ADCSMP_STRING; + + +typedef enum _RT_ADCSMP_TRIG_SEL { + PHYDM_ADC_BB_TRIG = 0, + PHYDM_ADC_MAC_TRIG = 1, + PHYDM_ADC_RF0_TRIG = 2, + PHYDM_ADC_RF1_TRIG = 3, + PHYDM_MAC_TRIG = 4 +} RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL; + + +typedef enum _RT_ADCSMP_TRIG_SIG_SEL { + ADCSMP_TRIG_CRCOK = 0, + ADCSMP_TRIG_CRCFAIL = 1, + ADCSMP_TRIG_CCA = 2, + ADCSMP_TRIG_REG = 3 +} RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL; + + +typedef enum _RT_ADCSMP_STATE { + ADCSMP_STATE_IDLE = 0, + ADCSMP_STATE_SET = 1, + ADCSMP_STATE_QUERY = 2 +} RT_ADCSMP_STATE, *PRT_ADCSMP_STATE; + + +typedef struct _RT_ADCSMP { + RT_ADCSMP_STRING ADCSmpBuf; + RT_ADCSMP_STATE ADCSmpState; + u1Byte la_trig_mode; + u4Byte la_TrigSigSel; + u1Byte la_dma_type; + u4Byte la_TriggerTime; + u4Byte la_mac_ref_mask; + u4Byte la_dbg_port; + u1Byte la_trigger_edge; + u1Byte la_smp_rate; + u4Byte la_count; + u1Byte is_bb_trigger; + u1Byte la_work_item_index; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM ADCSmpWorkItem; + RT_WORK_ITEM ADCSmpWorkItem_1; + #endif +} RT_ADCSMP, *PRT_ADCSMP; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +VOID +ADCSmpWorkItemCallback( + IN PVOID pContext +); +#endif + +VOID +ADCSmp_Set( + IN PVOID pDM_VOID, + IN u1Byte trig_mode, + IN u4Byte TrigSigSel, + IN u1Byte DmaDataSigSel, + IN u4Byte TriggerTime, + IN u2Byte PollingTime +); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +RT_STATUS +ADCSmp_Query( + IN PVOID pDM_VOID, + IN ULONG InformationBufferLength, + OUT PVOID InformationBuffer, + OUT PULONG BytesWritten +); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +VOID +ADCSmp_Query( + IN PVOID pDM_VOID, + OUT PVOID output, + IN u4Byte out_len, + IN pu4Byte pused +); + +s4Byte +ADCSmp_Get_SampleCounts( + IN PVOID pDM_VOID +); + +s4Byte +ADCSmp_Query_SingleData( + IN PVOID pDM_VOID, + OUT PVOID output, + IN u4Byte out_len, + IN u4Byte index +); + +#endif +VOID +ADCSmp_Stop( + IN PVOID pDM_VOID +); + +VOID +ADCSmp_Init( + IN PVOID pDM_VOID +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +VOID +ADCSmp_DeInit( + IN PVOID pDM_VOID +); +#endif + +VOID +phydm_la_mode_bb_setting( + IN PVOID pDM_VOID +); + +void +phydm_la_mode_set_trigger_time( + IN PVOID pDM_VOID, + IN u4Byte TriggerTime_mu_sec +); + +VOID +phydm_lamode_trigger_setting( + IN PVOID pDM_VOID, + IN char input[][16], + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len, + IN u4Byte input_num + ); +#endif +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_antdect.c b/package/kernel/rtl8192cd/phydm/phydm_antdect.c index 862c5971fae..afa478cb432 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_antdect.c +++ b/package/kernel/rtl8192cd/phydm/phydm_antdect.c @@ -1,964 +1,964 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) -#if(defined(CONFIG_ANT_DETECTION)) - -//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter) -//IS_ANT_DETECT_SUPPORT_RSSI(Adapter) -//IS_ANT_DETECT_SUPPORT_PSD(Adapter) - -//1 [1. Single Tone Method] =================================================== - -// -// Description: -// Set Single/Dual Antenna default setting for products that do not do detection in advance. -// -// Added by Joseph, 2012.03.22 -// -VOID -ODM_SingleDualAntennaDefaultSetting( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - PADAPTER pAdapter = pDM_Odm->Adapter; - - u1Byte btAntNum=BT_GetPgAntNum(pAdapter); - // Set default antenna A and B status - if(btAntNum == 2) - { - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=TRUE; - - } - else if(btAntNum == 1) - {// Set antenna A as default - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=FALSE; - - } - else - { - RT_ASSERT(FALSE, ("Incorrect antenna number!!\n")); - } -} - - -//2 8723A ANT DETECT -// -// Description: -// Implement IQK single tone for RF DPK loopback and BB PSD scanning. -// This function is cooperated with BB team Neil. -// -// Added by Roger, 2011.12.15 -// -BOOLEAN -ODM_SingleDualAntennaDetection( - IN PVOID pDM_VOID, - IN u1Byte mode - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u4Byte CurrentChannel,RfLoopReg; - u1Byte n; - u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA; - u1Byte initial_gain = 0x5a; - u4Byte PSD_report_tmp; - u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; - BOOLEAN bResult = TRUE; - u4Byte AFE_Backup[16]; - u4Byte AFE_REG_8723A[16] = { - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN, - rFPGA0_XCD_SwitchControl, rBlue_Tooth}; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n")); - - - if (!(pDM_Odm->SupportICType & ODM_RTL8723B)) - return bResult; - - // Retrieve antenna detection registry info, added by Roger, 2012.11.27. - if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter)) - return bResult; - - //1 Backup Current RF/BB Settings - - CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); - RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord); - Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord); - Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); - Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); - Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29); - ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1); - ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77); - ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7 - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8 - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0); - } - - ODM_StallExecution(10); - - //Store A Path Register 88c, c08, 874, c50 - Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); - Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); - Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); - Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); - - // Store AFE Registers - if (pDM_Odm->SupportICType & ODM_RTL8723B) - AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord); - - //Set PSD 128 pts - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts - - // To SET CH1 to do - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1 - - // AFE all on step - if (pDM_Odm->SupportICType & ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016); - - // 3 wire Disable - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); - - //BB IQK Setting - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); - - //IQK setting tone@ 4.34Mhz - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - - //Page B init - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016); - } - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain); - - //IQK Single tone start - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_StallExecution(10000); - - // PSD report of antenna A - PSD_report_tmp=0x0; - for (n=0;n<2;n++) - { - PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); - if(PSD_report_tmp >AntA_report) - AntA_report=PSD_report_tmp; - } - - // change to Antenna B - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - //ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2); - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); - } - - ODM_StallExecution(10); - - // PSD report of antenna B - PSD_report_tmp=0x0; - for (n=0;n<2;n++) - { - PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); - if(PSD_report_tmp > AntB_report) - AntB_report=PSD_report_tmp; - } - - //Close IQK Single Tone function - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //1 Return to antanna A - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - // external DPDT - ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c); - - //internal S0/S1 - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); - ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930); - ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064); - } - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); - - //Reload AFE Registers - if (pDM_Odm->SupportICType & ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA); - - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); - - //2 Test Ant B based on Ant A is ON - if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135)) - { - u1Byte TH1=2, TH2=6; - - if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1)) - { - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); - } - else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) || - ((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2))) - { - pDM_SWAT_Table->ANTA_ON=FALSE; - pDM_SWAT_Table->ANTB_ON=FALSE; - bResult = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); - } - else - { - pDM_SWAT_Table->ANTA_ON = TRUE; - pDM_SWAT_Table->ANTB_ON=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n")); - } - pDM_Odm->AntDetectedInfo.bAntDetected= TRUE; - pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report; - pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report; - pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report; - - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n")); - bResult = FALSE; - } - } - return bResult; - -} - - - -//1 [2. Scan AP RSSI Method] ================================================== - - - - -BOOLEAN -ODM_SwAntDivCheckBeforeLink( - IN PVOID pDM_VOID - ) -{ - -#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - s1Byte Score = 0; - PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc; - u1Byte power_target_L = 9, power_target_H = 16; - u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff; - u2Byte index, counter = 0; - static u1Byte ScanChannel; - u4Byte tmp_SWAS_NoLink_BK_Reg948; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON)); - - //if(HP id) - { - if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); - return FALSE; - } - - if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff) - pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch ); - } - } - - if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 - { // The ODM structure is not initialized. - return FALSE; - } - - // Retrieve antenna detection registry info, added by Roger, 2012.11.27. - if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter)) - { - return FALSE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n")); - } - - // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. - PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) - { - PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n", - pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState)); - - pDM_SWAT_Table->SWAS_NoLink_State = 0; - - return FALSE; - } - else - { - PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State)); - //1 Run AntDiv mechanism "Before Link" part. - if(pDM_SWAT_Table->SWAS_NoLink_State == 0) - { - //1 Prepare to do Scan again to check current antenna state. - - // Set check state to next step. - pDM_SWAT_Table->SWAS_NoLink_State = 1; - - // Copy Current Scan list. - pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc; - PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); - - // Go back to scan function again. - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n")); - pMgntInfo->ScanStep=0; - pMgntInfo->bScanAntDetect = TRUE; - ScanChannel = odm_SwAntDivSelectScanChnl(Adapter); - - - if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) - { - if(pDM_FatTable->RxIdleAnt == MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); - else - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - if(ScanChannel == 0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); - - if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) - { - pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - return FALSE; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); - } else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { - /*Switch Antenna to another one.*/ - - tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch); - - if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) { - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); - pDM_SWAT_Table->CurAntenna = AUX_ANT; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948)); - return FALSE; - } - ODM_StallExecution(10); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX")); - } - - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - - return TRUE; - } - else //pDM_SWAT_Table->SWAS_NoLink_State == 1 - { - //1 ScanComple() is called after antenna swiched. - //1 Check scan result and determine which antenna is going - //1 to be used. - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino - - for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++) - { - pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1 - pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2 - - if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n")); - continue; - } - - if(pDM_Odm->SupportICType != ODM_RTL8723B) - { - if(pTmpBssDesc->ChannelNumber == ScanChannel) - { - if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n")); - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - - Score++; - PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); - } - else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n")); - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - Score--; - } - else - { - if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000) - { - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n")); - } - } - } - } - else // 8723B - { - if(pTmpBssDesc->ChannelNumber == ScanChannel) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber )); - - if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2) - { - counter++; - tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower); - power_diff = power_diff + tmp_power_diff; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff)); - if(tmp_power_diff > max_power_diff) - max_power_diff=tmp_power_diff; - if(tmp_power_diff < min_power_diff) - min_power_diff=tmp_power_diff; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff)); - - PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); - } - else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2) - { - counter++; - tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower); - power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); - if(tmp_power_diff > max_power_diff) - max_power_diff=tmp_power_diff; - if(tmp_power_diff < min_power_diff) - min_power_diff=tmp_power_diff; - } - else // Pow(Ant1) = Pow(Ant2) - { - if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); - if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000) - { - counter++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); - min_power_diff = 0; - } - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); - } - } - } - } - } - - if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) - { - if(pMgntInfo->NumBssDesc!=0 && Score<0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); - - if(pDM_FatTable->RxIdleAnt == MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); - else - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - } - - if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) - { - pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - } - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if(counter == 0) - { - if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE) - { - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE; - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n")); - - //3 [ Scan again ] - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - return TRUE; - } - else// Pre_Aux_FailDetec == TRUE - { - //2 [ Single Antenna ] - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - } - pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++; - } - else - { - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; - - if(counter==3) - { - avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); - } - else if(counter>=4) - { - avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); - - } - else//counter==1,2 - { - avg_power_diff=power_diff/counter; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff)); - } - - //2 [ Retry ] - if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) ) - { - pDM_Odm->DM_SWAT_Table.Retry_Counter++; - - if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff)); - - //3 [ Scan again ] - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - return TRUE; - } - else - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - } - - } - //2 [ Dual Antenna ] - else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) ) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); - pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++; - - // set bt coexDM from 1ant coexDM to 2ant coexDM - BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2); - - //3 [ Init antenna diversity ] - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_AntDivInit(pDM_Odm); - } - //2 [ Single Antenna ] - else if(avg_power_diff > power_target_H) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; - //BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++; - } - } - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n", - pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter)); - - //2 recover the antenna setting - - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 )); - - - } - - // Check state reset to default and wait for next time. - pDM_SWAT_Table->SWAS_NoLink_State = 0; - pMgntInfo->bScanAntDetect = FALSE; - - return FALSE; - } - -#else - return FALSE; -#endif - -return FALSE; -} - - - - - - -//1 [3. PSD Method] ========================================================== - - - - -u4Byte -odm_GetPSDData( - IN PVOID pDM_VOID, - IN u2Byte point, - IN u1Byte initial_gain) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte psd_report; - - ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1 - ODM_StallExecution(150);//Wait for HW PSD report - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0 - psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0] - - psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain); - return psd_report; -} - - - -VOID -ODM_SingleDualAntennaDetection_PSD( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Channel_ori; - u1Byte initial_gain = 0x36; - u1Byte tone_idx; - u1Byte Tone_lenth_1=7, Tone_lenth_2=4; - u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56}; - u2Byte Tone_idx_2[4]={8, 24, 40, 56}; - u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0}; - //u1Byte Tone_lenth_1=4, Tone_lenth_2=2; - //u2Byte Tone_idx_1[4]={88, 120, 24, 56}; - //u2Byte Tone_idx_2[2]={ 24, 56}; - //u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0}; - - u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0; - u4Byte PSD_power_threshold; - u4Byte Main_psd_result=0, Aux_psd_result=0; - u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908; - u4Byte i=0,test_num=8; - - - if(pDM_Odm->SupportICType != ODM_RTL8723B) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n")); - - //2 [ Backup Current RF/BB Settings ] - - Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); - Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); - Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); - Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); - Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); - Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord); - - //2 [ Setting for doing PSD function (CH4)] - ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue - ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] - - // PHYTXON while loop - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803); - while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6)) - { - i++; - if (i > 1000000) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); - break; - } - } - - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss - ODM_StallExecution(3000); - - - //2 [ Doing PSD Function in (CH4)] - - //Antenna A - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); - ODM_StallExecution(10); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); - for (i=0;iPSD_report_Main[tone_idx] ) - PSD_report_Main[tone_idx]+=PSD_report_temp; - } - } - //Antenna B - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); - ODM_StallExecution(10); - for (i=0;iPSD_report_Aux[tone_idx] ) - PSD_report_Aux[tone_idx]+=PSD_report_temp; - } - } - //2 [ Doing PSD Function in (CH8)] - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 - ODM_StallExecution(3000); - - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf - ODM_StallExecution(3000); - - //Antenna A - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); - ODM_StallExecution(10); - - for (i=0;iPSD_report_Main[tone_idx] ) - PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp; - } - } - - //Antenna B - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); - ODM_StallExecution(10); - - for (i=0;iPSD_report_Aux[tone_idx] ) - PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp; - } - } - - //2 [ Calculate Result ] - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n")); - for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] )); - Main_psd_result+= PSD_report_Main[tone_idx]; - if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main) - MAX_PSD_report_Main=PSD_report_Main[tone_idx]; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main)); - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n")); - for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] )); - Aux_psd_result+= PSD_report_Aux[tone_idx]; - if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux) - MAX_PSD_report_Aux=PSD_report_Aux[tone_idx]; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux)); - - //Main_psd_result=Main_psd_result-MAX_PSD_report_Main; - //Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux; - PSD_power_threshold=(Main_psd_result*7)>>3; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold)); - - //3 [ Dual Antenna ] - if(Aux_psd_result >= PSD_power_threshold ) - { - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); - - // set bt coexDM from 1ant coexDM to 2ant coexDM - //BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2); - - // Init antenna diversity - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_AntDivInit(pDM_Odm); - } - //3 [ Single Antenna ] - else - { - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - } - - //2 [ Recover all parameters ] - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori); - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50); - - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); - - ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue - ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908); - - return; - -} - -#endif -void -odm_SwAntDetectInit( - IN PVOID pDM_VOID - ) -{ -#if(defined(CONFIG_ANT_DETECTION)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - //pDM_SWAT_Table->PreAntenna = MAIN_ANT; - //pDM_SWAT_Table->CurAntenna = MAIN_ANT; - pDM_SWAT_Table->SWAS_NoLink_State = 0; - pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE; - pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff; -#endif -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +#if(defined(CONFIG_ANT_DETECTION)) + +//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter) +//IS_ANT_DETECT_SUPPORT_RSSI(Adapter) +//IS_ANT_DETECT_SUPPORT_PSD(Adapter) + +//1 [1. Single Tone Method] =================================================== + +// +// Description: +// Set Single/Dual Antenna default setting for products that do not do detection in advance. +// +// Added by Joseph, 2012.03.22 +// +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + PADAPTER pAdapter = pDM_Odm->Adapter; + + u1Byte btAntNum=BT_GetPgAntNum(pAdapter); + // Set default antenna A and B status + if(btAntNum == 2) + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; + + } + else if(btAntNum == 1) + {// Set antenna A as default + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=FALSE; + + } + else + { + RT_ASSERT(FALSE, ("Incorrect antenna number!!\n")); + } +} + + +//2 8723A ANT DETECT +// +// Description: +// Implement IQK single tone for RF DPK loopback and BB PSD scanning. +// This function is cooperated with BB team Neil. +// +// Added by Roger, 2011.12.15 +// +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PVOID pDM_VOID, + IN u1Byte mode + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte CurrentChannel,RfLoopReg; + u1Byte n; + u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA; + u1Byte initial_gain = 0x5a; + u4Byte PSD_report_tmp; + u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; + BOOLEAN bResult = TRUE; + u4Byte AFE_Backup[16]; + u4Byte AFE_REG_8723A[16] = { + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN, + rFPGA0_XCD_SwitchControl, rBlue_Tooth}; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n")); + + + if (!(pDM_Odm->SupportICType & ODM_RTL8723B)) + return bResult; + + // Retrieve antenna detection registry info, added by Roger, 2012.11.27. + if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter)) + return bResult; + + //1 Backup Current RF/BB Settings + + CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); + RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord); + Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord); + Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); + Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); + Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29); + ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1); + ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77); + ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7 + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8 + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0); + } + + ODM_StallExecution(10); + + //Store A Path Register 88c, c08, 874, c50 + Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); + Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); + Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); + Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); + + // Store AFE Registers + if (pDM_Odm->SupportICType & ODM_RTL8723B) + AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord); + + //Set PSD 128 pts + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts + + // To SET CH1 to do + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1 + + // AFE all on step + if (pDM_Odm->SupportICType & ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016); + + // 3 wire Disable + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); + + //BB IQK Setting + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); + + //IQK setting tone@ 4.34Mhz + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + + //Page B init + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016); + } + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain); + + //IQK Single tone start + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_StallExecution(10000); + + // PSD report of antenna A + PSD_report_tmp=0x0; + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp >AntA_report) + AntA_report=PSD_report_tmp; + } + + // change to Antenna B + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + //ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2); + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); + } + + ODM_StallExecution(10); + + // PSD report of antenna B + PSD_report_tmp=0x0; + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp > AntB_report) + AntB_report=PSD_report_tmp; + } + + //Close IQK Single Tone function + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //1 Return to antanna A + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + // external DPDT + ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c); + + //internal S0/S1 + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); + ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930); + ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064); + } + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); + + //Reload AFE Registers + if (pDM_Odm->SupportICType & ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA); + + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); + + //2 Test Ant B based on Ant A is ON + if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135)) + { + u1Byte TH1=2, TH2=6; + + if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1)) + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); + } + else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) || + ((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2))) + { + pDM_SWAT_Table->ANTA_ON=FALSE; + pDM_SWAT_Table->ANTB_ON=FALSE; + bResult = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); + } + else + { + pDM_SWAT_Table->ANTA_ON = TRUE; + pDM_SWAT_Table->ANTB_ON=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n")); + } + pDM_Odm->AntDetectedInfo.bAntDetected= TRUE; + pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report; + pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report; + pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report; + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n")); + bResult = FALSE; + } + } + return bResult; + +} + + + +//1 [2. Scan AP RSSI Method] ================================================== + + + + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PVOID pDM_VOID + ) +{ + +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + s1Byte Score = 0; + PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc; + u1Byte power_target_L = 9, power_target_H = 16; + u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff; + u2Byte index, counter = 0; + static u1Byte ScanChannel; + u4Byte tmp_SWAS_NoLink_BK_Reg948; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON)); + + //if(HP id) + { + if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); + return FALSE; + } + + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff) + pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch ); + } + } + + if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 + { // The ODM structure is not initialized. + return FALSE; + } + + // Retrieve antenna detection registry info, added by Roger, 2012.11.27. + if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter)) + { + return FALSE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n")); + } + + // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. + PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n", + pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState)); + + pDM_SWAT_Table->SWAS_NoLink_State = 0; + + return FALSE; + } + else + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State)); + //1 Run AntDiv mechanism "Before Link" part. + if(pDM_SWAT_Table->SWAS_NoLink_State == 0) + { + //1 Prepare to do Scan again to check current antenna state. + + // Set check state to next step. + pDM_SWAT_Table->SWAS_NoLink_State = 1; + + // Copy Current Scan list. + pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc; + PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); + + // Go back to scan function again. + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n")); + pMgntInfo->ScanStep=0; + pMgntInfo->bScanAntDetect = TRUE; + ScanChannel = odm_SwAntDivSelectScanChnl(Adapter); + + + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) + { + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + if(ScanChannel == 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + + if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) + { + pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); + } else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { + /*Switch Antenna to another one.*/ + + tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch); + + if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) { + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); + pDM_SWAT_Table->CurAntenna = AUX_ANT; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948)); + return FALSE; + } + ODM_StallExecution(10); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX")); + } + + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + + return TRUE; + } + else //pDM_SWAT_Table->SWAS_NoLink_State == 1 + { + //1 ScanComple() is called after antenna swiched. + //1 Check scan result and determine which antenna is going + //1 to be used. + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino + + for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++) + { + pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1 + pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2 + + if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n")); + continue; + } + + if(pDM_Odm->SupportICType != ODM_RTL8723B) + { + if(pTmpBssDesc->ChannelNumber == ScanChannel) + { + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + + Score++; + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + Score--; + } + else + { + if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000) + { + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n")); + } + } + } + } + else // 8723B + { + if(pTmpBssDesc->ChannelNumber == ScanChannel) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber )); + + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2) + { + counter++; + tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff)); + if(tmp_power_diff > max_power_diff) + max_power_diff=tmp_power_diff; + if(tmp_power_diff < min_power_diff) + min_power_diff=tmp_power_diff; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff)); + + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2) + { + counter++; + tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + if(tmp_power_diff > max_power_diff) + max_power_diff=tmp_power_diff; + if(tmp_power_diff < min_power_diff) + min_power_diff=tmp_power_diff; + } + else // Pow(Ant1) = Pow(Ant2) + { + if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); + if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000) + { + counter++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + min_power_diff = 0; + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); + } + } + } + } + } + + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) + { + if(pMgntInfo->NumBssDesc!=0 && Score<0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + } + + if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) + { + pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + } + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(counter == 0) + { + if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE) + { + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE; + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n")); + + //3 [ Scan again ] + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + return TRUE; + } + else// Pre_Aux_FailDetec == TRUE + { + //2 [ Single Antenna ] + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++; + } + else + { + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; + + if(counter==3) + { + avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); + } + else if(counter>=4) + { + avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); + + } + else//counter==1,2 + { + avg_power_diff=power_diff/counter; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff)); + } + + //2 [ Retry ] + if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) ) + { + pDM_Odm->DM_SWAT_Table.Retry_Counter++; + + if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff)); + + //3 [ Scan again ] + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + return TRUE; + } + else + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + + } + //2 [ Dual Antenna ] + else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) ) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); + pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++; + + // set bt coexDM from 1ant coexDM to 2ant coexDM + BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + //3 [ Init antenna diversity ] + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + ODM_AntDivInit(pDM_Odm); + } + //2 [ Single Antenna ] + else if(avg_power_diff > power_target_H) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; + //BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++; + } + } + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n", + pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter)); + + //2 recover the antenna setting + + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 )); + + + } + + // Check state reset to default and wait for next time. + pDM_SWAT_Table->SWAS_NoLink_State = 0; + pMgntInfo->bScanAntDetect = FALSE; + + return FALSE; + } + +#else + return FALSE; +#endif + +return FALSE; +} + + + + + + +//1 [3. PSD Method] ========================================================== + + + + +u4Byte +odm_GetPSDData( + IN PVOID pDM_VOID, + IN u2Byte point, + IN u1Byte initial_gain) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte psd_report; + + ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1 + ODM_StallExecution(150);//Wait for HW PSD report + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0 + psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0] + + psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain); + return psd_report; +} + + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Channel_ori; + u1Byte initial_gain = 0x36; + u1Byte tone_idx; + u1Byte Tone_lenth_1=7, Tone_lenth_2=4; + u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56}; + u2Byte Tone_idx_2[4]={8, 24, 40, 56}; + u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0}; + //u1Byte Tone_lenth_1=4, Tone_lenth_2=2; + //u2Byte Tone_idx_1[4]={88, 120, 24, 56}; + //u2Byte Tone_idx_2[2]={ 24, 56}; + //u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0}; + + u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0; + u4Byte PSD_power_threshold; + u4Byte Main_psd_result=0, Aux_psd_result=0; + u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908; + u4Byte i=0,test_num=8; + + + if(pDM_Odm->SupportICType != ODM_RTL8723B) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n")); + + //2 [ Backup Current RF/BB Settings ] + + Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); + Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); + Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); + Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); + Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); + Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord); + + //2 [ Setting for doing PSD function (CH4)] + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] + + // PHYTXON while loop + ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803); + while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6)) + { + i++; + if (i > 1000000) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); + break; + } + } + + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss + ODM_StallExecution(3000); + + + //2 [ Doing PSD Function in (CH4)] + + //Antenna A + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); + ODM_StallExecution(10); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); + for (i=0;iPSD_report_Main[tone_idx] ) + PSD_report_Main[tone_idx]+=PSD_report_temp; + } + } + //Antenna B + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); + ODM_StallExecution(10); + for (i=0;iPSD_report_Aux[tone_idx] ) + PSD_report_Aux[tone_idx]+=PSD_report_temp; + } + } + //2 [ Doing PSD Function in (CH8)] + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 + ODM_StallExecution(3000); + + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf + ODM_StallExecution(3000); + + //Antenna A + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); + ODM_StallExecution(10); + + for (i=0;iPSD_report_Main[tone_idx] ) + PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp; + } + } + + //Antenna B + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); + ODM_StallExecution(10); + + for (i=0;iPSD_report_Aux[tone_idx] ) + PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp; + } + } + + //2 [ Calculate Result ] + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n")); + for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] )); + Main_psd_result+= PSD_report_Main[tone_idx]; + if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main) + MAX_PSD_report_Main=PSD_report_Main[tone_idx]; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main)); + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n")); + for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] )); + Aux_psd_result+= PSD_report_Aux[tone_idx]; + if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux) + MAX_PSD_report_Aux=PSD_report_Aux[tone_idx]; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux)); + + //Main_psd_result=Main_psd_result-MAX_PSD_report_Main; + //Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux; + PSD_power_threshold=(Main_psd_result*7)>>3; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold)); + + //3 [ Dual Antenna ] + if(Aux_psd_result >= PSD_power_threshold ) + { + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); + + // set bt coexDM from 1ant coexDM to 2ant coexDM + //BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + // Init antenna diversity + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + ODM_AntDivInit(pDM_Odm); + } + //3 [ Single Antenna ] + else + { + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + + //2 [ Recover all parameters ] + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori); + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50); + + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); + + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] + ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908); + + return; + +} + +#endif +void +odm_SwAntDetectInit( + IN PVOID pDM_VOID + ) +{ +#if(defined(CONFIG_ANT_DETECTION)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + //pDM_SWAT_Table->PreAntenna = MAIN_ANT; + //pDM_SWAT_Table->CurAntenna = MAIN_ANT; + pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE; + pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff; +#endif +} + diff --git a/package/kernel/rtl8192cd/phydm/phydm_antdect.h b/package/kernel/rtl8192cd/phydm/phydm_antdect.h index 419d9ea956c..8cf60e8f9a3 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_antdect.h +++ b/package/kernel/rtl8192cd/phydm/phydm_antdect.h @@ -1,98 +1,98 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMANTDECT_H__ -#define __PHYDMANTDECT_H__ - -#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/ - -#if(defined(CONFIG_ANT_DETECTION)) -//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) -//ANT Test -#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/ -#define ANTTESTA 0x01 /*Ant A will be Testing*/ -#define ANTTESTB 0x02 /*Ant B will be testing*/ - -#define MAX_ANTENNA_DETECTION_CNT 10 - - -typedef struct _ANT_DETECTED_INFO{ - BOOLEAN bAntDetected; - u4Byte dBForAntA; - u4Byte dBForAntB; - u4Byte dBForAntO; -}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; - - -typedef enum tag_SW_Antenna_Switch_Definition -{ - Antenna_A = 1, - Antenna_B = 2, - Antenna_MAX = 3, -}DM_SWAS_E; - - - -//1 [1. Single Tone Method] =================================================== - - - -VOID -ODM_SingleDualAntennaDefaultSetting( - IN PVOID pDM_VOID - ); - -BOOLEAN -ODM_SingleDualAntennaDetection( - IN PVOID pDM_VOID, - IN u1Byte mode - ); - -//1 [2. Scan AP RSSI Method] ================================================== - -#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink - -BOOLEAN -ODM_SwAntDivCheckBeforeLink( - IN PVOID pDM_VOID - ); - - - - -//1 [3. PSD Method] ========================================================== - - -VOID -ODM_SingleDualAntennaDetection_PSD( - IN PVOID pDM_VOID -); - -#endif - -VOID -odm_SwAntDetectInit( - IN PVOID pDM_VOID - ); - - -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ + +#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/ + +#if(defined(CONFIG_ANT_DETECTION)) +//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +//ANT Test +#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*Ant A will be Testing*/ +#define ANTTESTB 0x02 /*Ant B will be testing*/ + +#define MAX_ANTENNA_DETECTION_CNT 10 + + +typedef struct _ANT_DETECTED_INFO{ + BOOLEAN bAntDetected; + u4Byte dBForAntA; + u4Byte dBForAntB; + u4Byte dBForAntO; +}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; + + +typedef enum tag_SW_Antenna_Switch_Definition +{ + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}DM_SWAS_E; + + + +//1 [1. Single Tone Method] =================================================== + + + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PVOID pDM_VOID + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PVOID pDM_VOID, + IN u1Byte mode + ); + +//1 [2. Scan AP RSSI Method] ================================================== + +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PVOID pDM_VOID + ); + + + + +//1 [3. PSD Method] ========================================================== + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PVOID pDM_VOID +); + +#endif + +VOID +odm_SwAntDetectInit( + IN PVOID pDM_VOID + ); + + +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_antdiv.c b/package/kernel/rtl8192cd/phydm/phydm_antdiv.c index 4c46ab9fb19..d03889e7fb3 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_antdiv.c +++ b/package/kernel/rtl8192cd/phydm/phydm_antdiv.c @@ -1,5611 +1,5611 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -extern u2Byte phy_rate_table[28]; - -//====================================================== -// when antenna test utility is on or some testing need to disable antenna diversity -// call this function to disable all ODM related mechanisms which will switch antenna. -//====================================================== -VOID -ODM_StopAntennaSwitchDm( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - // disable ODM antenna diversity - pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n")); -} - -VOID -phydm_enable_antenna_diversity( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); - odm_AntennaDiversityInit(pDM_Odm); -} - -VOID -ODM_SetAntConfig( - IN PVOID pDM_VOID, - IN u1Byte antSetting // 0=A, 1=B, 2=C, .... - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (antSetting == 0) /* ant A*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else if (antSetting == 1) - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (antSetting == 0) /* ant A*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0000); - else if (antSetting == 1) - ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0280); - } -} - -//====================================================== - - -VOID -ODM_SwAntDivRestAfterLink( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte i; - - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->RSSI_Trying = 0; - pDM_SWAT_Table->Double_chk_flag= 0; - - pDM_FatTable->RxIdleAnt=MAIN_ANT; - - for (i=0; iMainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; - } - - } -} - - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -VOID -odm_AntDiv_on_off( - IN PVOID pDM_VOID , - IN u1Byte swch - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_FatTable->AntDiv_OnOff != swch) - { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) - return; - - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); - ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); - - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - if (pDM_Odm->SupportICType == ODM_RTL8812) { - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable - ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable - } else { - ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable - - if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable - } - } - } - } - pDM_FatTable->AntDiv_OnOff =swch; - -} - -VOID -phydm_FastTraining_enable( - IN PVOID pDM_VOID, - IN u1Byte swch - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte enable; - - if (swch == FAT_ON) - enable=1; - else - enable=0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast Ant Training_en = ((%d))\n", enable)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); /*enable fast training*/ - /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); /*enable fast training (path-A)*/ - /*ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable);*/ /*enable fast training (path-B)*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8821) { - ODM_SetBBReg(pDM_Odm, 0x900 , BIT19, enable); /*enable fast training */ - /**/ - } -} - -phydm_keep_RxAckAnt_By_TxAnt_time( - IN PVOID pDM_VOID, - IN u4Byte time - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ - if (pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) { - - ODM_SetBBReg(pDM_Odm, 0xE20, BIT23|BIT22|BIT21|BIT20, time); - /**/ - } else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) { - - ODM_SetBBReg(pDM_Odm, 0x818, BIT23|BIT22|BIT21|BIT20, time); - /**/ - } -} - -VOID -odm_Tx_By_TxDesc_or_Reg( - IN PVOID pDM_VOID, - IN u1Byte swch - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte enable; - - if (pDM_FatTable->b_fix_tx_ant == NO_FIX_TX_ANT) - enable = (swch == TX_BY_DESC) ? 1 : 0; - else - enable = 0;/*Force TX by Reg*/ - - if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) - { - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable); - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC":"REG")); - } -} - -VOID -ODM_UpdateRxIdleAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte DefaultAnt, OptionalAnt, value32, Default_tx_Ant; - - if(pDM_FatTable->RxIdleAnt != Ant) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - if(!(pDM_Odm->SupportICType & ODM_RTL8723B)) - pDM_FatTable->RxIdleAnt = Ant; - - if(Ant == MAIN_ANT) - { - DefaultAnt = ANT1_2G; - OptionalAnt = ANT2_2G; - } - else - { - DefaultAnt = ANT2_2G; - OptionalAnt = ANT1_2G; - } - - if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) - Default_tx_Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; - else - Default_tx_Ant = DefaultAnt; - - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - if(pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX - } - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - - value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF); - - if(value32 !=0x280) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt); - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); - } - #endif - else { /*8188E & 8188F*/ - - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - #if (RTL8723D_SUPPORT == 1) - phydm_set_tx_ant_pwr_8723d(pDM_Odm, Ant); - #endif - } - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - phydm_update_rx_idle_antenna_8188F(pDM_Odm, DefaultAnt); - /**/ - } - #endif - - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, Default_tx_Ant); /*Default TX*/ - } - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - u2Byte value16 = ODM_Read2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2); - // - // 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt - // incorrect 0xc08 bit0-15 .We still not know why it is changed. - // - value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); - value16 |= ((u2Byte)DefaultAnt <<3); - value16 |= ((u2Byte)OptionalAnt <<6); - value16 |= ((u2Byte)DefaultAnt <<9); - ODM_Write2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2, value16); - /* - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT21|BIT20|BIT19, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX - */ - } - - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, Default_tx_Ant); /*PathA Resp Tx*/ - /**/ - } - else - { - ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, Default_tx_Ant); /*PathA Resp Tx*/ - /**/ - } - - } - else// pDM_FatTable->RxIdleAnt == Ant - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - pDM_FatTable->RxIdleAnt = Ant; - } -} - -VOID -odm_UpdateTxAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte MacId - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte TxAnt; - - if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) - Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; - - if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - { - TxAnt=Ant; - } - else - { - if(Ant == MAIN_ANT) - TxAnt = ANT1_2G; - else - TxAnt = ANT2_2G; - } - - pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0; - pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1; - pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId, (Ant == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); - -} - -#ifdef BEAMFORMING_SUPPORT -#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - -VOID -odm_BDC_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n")); - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Mode=BDC_MODE_NULL; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDCcoexType_wBfer=0; - pDM_Odm->bdc_holdstate=0xff; - - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008); - ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0); - } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008 - ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000 - } - -} - - -VOID -odm_CSI_on_off( - IN PVOID pDM_VOID, - IN u1Byte CSI_en - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(CSI_en==CSI_ON) - { - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1 - } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1 - } - - } - else if(CSI_en==CSI_OFF) - { - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0 - } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0 - } - } -} - -VOID -odm_BDCcoexType_withBferClient( - IN PVOID pDM_VOID, - IN u1Byte swch - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u1Byte BDCcoexType_wBfer; - - if(swch==DIVON_CSIOFF) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n")); - BDCcoexType_wBfer=1; - - if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - odm_CSI_on_off(pDM_Odm,CSI_OFF); - pDM_BdcTable->BDCcoexType_wBfer=1; - } - } - else if(swch==DIVOFF_CSION) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); - BDCcoexType_wBfer=2; - - if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_CSI_on_off(pDM_Odm,CSI_ON); - pDM_BdcTable->BDCcoexType_wBfer=2; - } - } -} - -VOID -odm_BF_AntDiv_ModeArbitration( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u1Byte current_BDC_Mode; - - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); - - //2 Mode 1 - if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0)) - { - current_BDC_Mode=BDC_MODE_1; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_1; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - pDM_BdcTable->BDC_RxIdleUpdate_counter=1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n")); - } - //2 Mode 2 - else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0)) - { - current_BDC_Mode=BDC_MODE_2; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_2; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Try_flag=0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n")); - } - //2 Mode 3 - else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0)) - { - current_BDC_Mode=BDC_MODE_3; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_3; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_RxIdleUpdate_counter=1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n")); - } - //2 Mode 4 - else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0)) - { - current_BDC_Mode=BDC_MODE_4; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_4; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n")); - } - #endif - -} - -VOID -odm_DivTrainState_setting( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n")); - pDM_BdcTable->BDC_Try_counter =2; - pDM_BdcTable->BDC_Try_flag=1; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); -} - -VOID -odm_BDCcoex_BFeeRxDiv_Arbitration( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - BOOLEAN StopBF_flag; - u1Byte BDC_active_Mode; - - - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar )); - - //2 [ MIB control ] - if (pDM_Odm->bdc_holdstate==2) - { - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n")); - return; - } - else if (pDM_Odm->bdc_holdstate==1) - { - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); - return; - } - - //------------------------------------------------------------ - - - - //2 Mode 2 & 3 - if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer)); - - // All Client have Bfer-Cap------------------------------- - if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - return; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); - } - // - if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - return; - } - else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - return; - } - - //Select active mode-------------------------------------- - if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2 - { - if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n")); - pDM_BdcTable->BDC_active_Mode=1; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); - pDM_BdcTable->BDC_active_Mode=2; - } - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - return; - } - else // num_BfTar > 0 - { - if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); - pDM_BdcTable->BDC_active_Mode=3; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - return; - } - else // Selsect_4 - { - BDC_active_Mode=4; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); - - if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode) - { - pDM_BdcTable->BDC_active_Mode=4; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n")); - return; - } - } - } - -#if 1 - if (pDM_Odm->bdc_holdstate==0xff) - { - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); - return; - } -#endif - - // Does Client number changed ? ------------------------------- - if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client) - { - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n")); - } - pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client; - - if( pDM_BdcTable->BDC_Try_flag==0) - { - //2 DIV_TRAIN_STATE (Mode 2-0) - if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE) - { - odm_DivTrainState_setting( pDM_Odm); - } - //2 BFer_TRAIN_STATE (Mode 2-1) - else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n")); - - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - pDM_BdcTable->BDC_Try_counter=2; - pDM_BdcTable->BDC_Try_flag=1; - pDM_BdcTable->BDC_state=BDC_DECISION_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n")); - //} - } - //2 DECISION_STATE (Mode 2-2) - else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n")); - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE) - StopBF_flag=TRUE; - else - StopBF_flag=FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag)); - - if(StopBF_flag==TRUE) //DIV_en - { - pDM_BdcTable->BDC_Hold_counter=10; //20 - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); - } - else //BF_en - { - pDM_BdcTable->BDC_Hold_counter=10; //20 - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n")); - } - //} - } - //2 BF-HOLD_STATE (Mode 2-3) - else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); - - if(pDM_BdcTable->BDC_Hold_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - odm_DivTrainState_setting( pDM_Odm); - } - else - { - pDM_BdcTable->BDC_Hold_counter--; - - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n")); - //} - } - - } - //2 DIV-HOLD_STATE (Mode 2-4) - else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); - - if(pDM_BdcTable->BDC_Hold_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - odm_DivTrainState_setting( pDM_Odm); - } - else - { - pDM_BdcTable->BDC_Hold_counter--; - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); - } - - } - - } - else if( pDM_BdcTable->BDC_Try_flag==1) - { - //2 Set Training Counter - if(pDM_BdcTable->BDC_Try_counter >1) - { - pDM_BdcTable->BDC_Try_counter--; - if(pDM_BdcTable->BDC_Try_counter ==1) - pDM_BdcTable->BDC_Try_flag=0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); - //return ; - } - - } - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); - - #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - - - - - - -} - -#endif -#endif //#ifdef BEAMFORMING_SUPPORT - -#ifdef ODM_EVM_ENHANCE_ANTDIV -VOID -phydm_evm_sw_antdiv_init( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - /*EVM enhance AntDiv method init----------------------------------------------------------------------*/ - pDM_FatTable->EVM_method_enable = 0; - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - pDM_FatTable->FAT_State_cnt = 0; - pDM_FatTable->pre_antdiv_rssi = 0; - - pDM_Odm->antdiv_intvl = 30; - pDM_Odm->antdiv_train_num = 2; - ODM_SetBBReg(pDM_Odm, 0x910, 0x3f, 0xf); - pDM_Odm->antdiv_evm_en = 1; - /*pDM_Odm->antdiv_period=1;*/ - pDM_Odm->evm_antdiv_period = 3; - pDM_Odm->stop_antdiv_rssi_th = 3; - pDM_Odm->stop_antdiv_tp_th = 80; - pDM_Odm->antdiv_tp_period = 3; - pDM_Odm->stop_antdiv_tp_diff_th = 5; -} - - -VOID -odm_EVM_FastAnt_Reset( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - pDM_FatTable->EVM_method_enable=0; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - pDM_FatTable->FAT_State_cnt = 0; - pDM_Odm->antdiv_period=0; - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0); -} - - -VOID -odm_EVM_Enhance_AntDiv( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Main_RSSI, Aux_RSSI ; - u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1; - u4Byte main_evm, aux_evm,Diff_RSSI=0,diff_EVM=0; - u4Byte main_2ss_evm[2], aux_2ss_evm[2]; - u4Byte main_1ss_evm, aux_1ss_evm; - u4Byte main_2ss_evm_sum, aux_2ss_evm_sum; - u1Byte score_EVM=0,score_CRC=0; - u1Byte rssi_larger_ant = 0; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte value32, i; - BOOLEAN Main_above1=FALSE,Aux_above1=FALSE; - BOOLEAN Force_antenna=FALSE; - PSTA_INFO_T pEntry; - u32 antdiv_tp_main_avg, antdiv_tp_aux_avg; - u8 curr_rssi, rssi_diff; - u32 tp_diff; - u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0; - u8 target_ant_evm_1ss, target_ant_evm_2ss; - u8 decision_evm_ss; - u8 next_ant; - - pDM_FatTable->TargetAnt_enhance=0xFF; - - - if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) - { - if(pDM_Odm->number_active_client == 1) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n")); - i = pDM_Odm->OneEntry_MACID; - pEntry = pDM_Odm->pODM_StaInfo[i]; - - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; - - if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF)) - { - Diff_RSSI=FORCE_RSSI_DIFF; - } - else if(Main_RSSI!=0 && Aux_RSSI !=0) - { - Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI); - } - - if (Main_RSSI >= Aux_RSSI) - rssi_larger_ant = MAIN_ANT; - else - rssi_larger_ant = AUX_ANT; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d ))\n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d ))\n", pDM_FatTable->AuxAnt_Cnt[i], Aux_RSSI)); - - if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) ) - //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1) - ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && ")); - - if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) )) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_L, State_cnt =((%d))\n", pDM_FatTable->FAT_State_cnt)); - - /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)==============================================================*/ - if (pDM_FatTable->FAT_State_cnt < ((pDM_Odm->antdiv_train_num)<<1)) { - - if (pDM_FatTable->FAT_State_cnt == 0) { - /*Reset EVM 1SS Method */ - pDM_FatTable->MainAntEVM_Sum[i] = 0; - pDM_FatTable->AuxAntEVM_Sum[i] = 0; - pDM_FatTable->MainAntEVM_Cnt[i] = 0; - pDM_FatTable->AuxAntEVM_Cnt[i] = 0; - /*Reset EVM 2SS Method */ - pDM_FatTable->MainAntEVM_2ss_Sum[i][0] =0; - pDM_FatTable->MainAntEVM_2ss_Sum[i][1] =0; - pDM_FatTable->AuxAntEVM_2ss_Sum[i][0] = 0; - pDM_FatTable->AuxAntEVM_2ss_Sum[i][1] = 0; - pDM_FatTable->MainAntEVM_2ss_Cnt[i] = 0; - pDM_FatTable->AuxAntEVM_2ss_Cnt[i] = 0; - #if 0 - /*Reset TP Method */ - pDM_FatTable->antdiv_tp_main = 0; - pDM_FatTable->antdiv_tp_aux = 0; - pDM_FatTable->antdiv_tp_main_cnt = 0; - pDM_FatTable->antdiv_tp_aux_cnt = 0; - #endif - /*Reset CRC Method */ - pDM_FatTable->MainCRC32_Ok_Cnt = 0; - pDM_FatTable->MainCRC32_Fail_Cnt = 0; - pDM_FatTable->AuxCRC32_Ok_Cnt = 0; - pDM_FatTable->AuxCRC32_Fail_Cnt = 0; - - #if SKIP_EVM_ANTDIV_TRAINING_PATCH - if ((*pDM_Odm->pBandWidth == ODM_BW20M) && (pEntry->rf_mimo_mode == MIMO_2T2R)) { - /*1. Skip training: RSSI*/ - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt)); - curr_rssi = (u8)((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? Main_RSSI : Aux_RSSI); - rssi_diff = (curr_rssi > pDM_FatTable->pre_antdiv_rssi) ? (curr_rssi - pDM_FatTable->pre_antdiv_rssi) : (pDM_FatTable->pre_antdiv_rssi - curr_rssi); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, pDM_FatTable->pre_antdiv_rssi)); - - pDM_FatTable->pre_antdiv_rssi = curr_rssi; - if ((rssi_diff < (pDM_Odm->stop_antdiv_rssi_th)) && (curr_rssi != 0)) { - rssi_return = 1; - } - - /*2. Skip training: TP Diff*/ - tp_diff = (pDM_Odm->rx_tp > pDM_FatTable->pre_antdiv_tp) ? (pDM_Odm->rx_tp - pDM_FatTable->pre_antdiv_tp) : (pDM_FatTable->pre_antdiv_tp - pDM_Odm->rx_tp); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", pDM_Odm->rx_tp, pDM_FatTable->pre_antdiv_tp)); - pDM_FatTable->pre_antdiv_tp = pDM_Odm->rx_tp; - if ((tp_diff < (u32)(pDM_Odm->stop_antdiv_tp_diff_th) && (pDM_Odm->rx_tp != 0))) { - tp_diff_return = 1; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[3] tp_return, curr_rx_tp=((%d))\n", pDM_Odm->rx_tp)); - /*3. Skip training: TP*/ - if (pDM_Odm->rx_tp >= (u32)(pDM_Odm->stop_antdiv_tp_th)) { - tp_return = 1; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return)); - /*4. Joint Return Decision*/ - if (tp_return) { - if (tp_diff_return || rssi_diff) { - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Return EVM SW AntDiv\n")); - return; - } - } - } - #endif - - pDM_FatTable->EVM_method_enable = 1; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - pDM_Odm->antdiv_period = pDM_Odm->evm_antdiv_period; - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); /*RCR accepts CRC32-Error packets*/ - } - - pDM_FatTable->FAT_State_cnt++; - - next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); - ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms - } - /*Decision state: 4==============================================================*/ - else { - - pDM_FatTable->FAT_State_cnt = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Decisoin state ] \n")); - - //3 [CRC32 statistic] - #if 0 - if ((pDM_FatTable->MainCRC32_Ok_Cnt > ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 40) && (rssi_larger_ant == MAIN_ANT))) { - pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; - Force_antenna=TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); - } else if ((pDM_FatTable->AuxCRC32_Ok_Cnt > ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 40) && (rssi_larger_ant == AUX_ANT))) { - pDM_FatTable->TargetAnt_CRC32=AUX_ANT; - Force_antenna=TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); - } - else - #endif - { - if(pDM_FatTable->MainCRC32_Fail_Cnt<=5) - pDM_FatTable->MainCRC32_Fail_Cnt=5; - - if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5) - pDM_FatTable->AuxCRC32_Fail_Cnt=5; - - if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt ) - Main_above1=TRUE; - - if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt ) - Aux_above1=TRUE; - - if(Main_above1==TRUE && Aux_above1==FALSE) - { - Force_antenna=TRUE; - pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; - } - else if(Main_above1==FALSE && Aux_above1==TRUE) - { - Force_antenna=TRUE; - pDM_FatTable->TargetAnt_CRC32=AUX_ANT; - } - else if(Main_above1==TRUE && Aux_above1==TRUE) - { - Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt; - Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt; - pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); - - if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) - { - if(Main_CRC_utility>=Aux_CRC_utility) - utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility; - else - utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility; - } - } - else if(Main_above1==FALSE && Aux_above1==FALSE) - { - if(pDM_FatTable->MainCRC32_Ok_Cnt==0) - pDM_FatTable->MainCRC32_Ok_Cnt=1; - if(pDM_FatTable->AuxCRC32_Ok_Cnt==0) - pDM_FatTable->AuxCRC32_Ok_Cnt=1; - - Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt; - Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt; - pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); - - if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) - { - if(Main_CRC_utility>=Aux_CRC_utility) - utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility); - else - utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility); - } - } - } - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets. - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt, Main_CRC_utility)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt, Aux_CRC_utility)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***1.TargetAnt_CRC32 = ((%s))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - //3 [EVM statistic] - /*1SS EVM*/ - main_1ss_evm = (pDM_FatTable->MainAntEVM_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_Sum[i] / pDM_FatTable->MainAntEVM_Cnt[i]) : 0; - aux_1ss_evm = (pDM_FatTable->AuxAntEVM_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_Sum[i] / pDM_FatTable->AuxAntEVM_Cnt[i]) : 0; - target_ant_evm_1ss = (main_1ss_evm==aux_1ss_evm) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main1ss_EVM= (( %d )) \n", pDM_FatTable->MainAntEVM_Cnt[i], main_1ss_evm)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_1ss_EVM = (( %d )) \n", pDM_FatTable->AuxAntEVM_Cnt[i], aux_1ss_evm)); - - /*2SS EVM*/ - main_2ss_evm[0] = (pDM_FatTable->MainAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_2ss_Sum[i][0] / pDM_FatTable->MainAntEVM_2ss_Cnt[i]) : 0; - main_2ss_evm[1] = (pDM_FatTable->MainAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_2ss_Sum[i][1] / pDM_FatTable->MainAntEVM_2ss_Cnt[i]) : 0; - main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; - - aux_2ss_evm[0] = (pDM_FatTable->AuxAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_2ss_Sum[i][0] / pDM_FatTable->AuxAntEVM_2ss_Cnt[i]) : 0; - aux_2ss_evm[1] = (pDM_FatTable->AuxAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_2ss_Sum[i][1] / pDM_FatTable->AuxAntEVM_2ss_Cnt[i]) : 0; - aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; - target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", - pDM_FatTable->MainAntEVM_2ss_Cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", - pDM_FatTable->AuxAntEVM_2ss_Cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum)); - - if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) - { - decision_evm_ss = 2; - main_evm = main_2ss_evm_sum; - aux_evm = aux_2ss_evm_sum; - pDM_FatTable->TargetAnt_EVM = target_ant_evm_2ss; - } else { - decision_evm_ss = 1; - main_evm = main_1ss_evm; - aux_evm = aux_1ss_evm; - pDM_FatTable->TargetAnt_EVM = target_ant_evm_1ss; - } - - if((main_evm == 0 || aux_evm == 0)) - diff_EVM = 100; - else if(main_evm >= aux_evm) - diff_EVM = main_evm - aux_evm; - else - diff_EVM = aux_evm - main_evm; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (pDM_FatTable->TargetAnt_EVM == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - - //3 [TP statistic] - antdiv_tp_main_avg = (pDM_FatTable->antdiv_tp_main_cnt != 0) ? (pDM_FatTable->antdiv_tp_main / pDM_FatTable->antdiv_tp_main_cnt) : 0; - antdiv_tp_aux_avg = (pDM_FatTable->antdiv_tp_aux_cnt != 0) ? (pDM_FatTable->antdiv_tp_aux / pDM_FatTable->antdiv_tp_aux_cnt) : 0; - pDM_FatTable->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main_TP = ((%d))\n", pDM_FatTable->antdiv_tp_main_cnt, antdiv_tp_main_avg)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_TP = ((%d))\n", pDM_FatTable->antdiv_tp_aux_cnt, antdiv_tp_aux_avg)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***3.TargetAnt_TP = ((%s))\n", (pDM_FatTable->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - - /*Reset TP Method */ - pDM_FatTable->antdiv_tp_main = 0; - pDM_FatTable->antdiv_tp_aux = 0; - pDM_FatTable->antdiv_tp_main_cnt = 0; - pDM_FatTable->antdiv_tp_aux_cnt = 0; - - //2 [ Decision state ] - if (pDM_FatTable->TargetAnt_EVM == pDM_FatTable->TargetAnt_CRC32) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - - if ((utility_ratio < 2 && Force_antenna == FALSE) && diff_EVM <= 30) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; - else - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; - } - #if 0 - else if ((diff_EVM <= 50 && (utility_ratio > 4 && Force_antenna == FALSE)) || (Force_antenna == TRUE)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; - } - #endif - else if (diff_EVM >= 20) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; - } else if (utility_ratio >= 6 && Force_antenna == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; - } else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - - if (Force_antenna == TRUE) - score_CRC = 2; - else if (utility_ratio >= 5) /*>2.5*/ - score_CRC = 2; - else if (utility_ratio >= 4) /*>2*/ - score_CRC = 1; - else - score_CRC = 0; - - if (diff_EVM >= 15) - score_EVM = 3; - else if (diff_EVM >= 10) - score_EVM = 2; - else if (diff_EVM >= 5) - score_EVM = 1; - else - score_EVM = 0; - - if (score_CRC > score_EVM) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; - else if (score_CRC < score_EVM) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; - else - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; - } - pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** 4.TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - } - else // RSSI< = Evm_RSSI_TH_Low - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); - } - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); - } - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[num_active_client != 1] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); - } - } -} - -VOID -odm_EVM_FastAntTrainingCallback( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******AntDiv Callback****** \n")); - odm_HW_AntDiv(pDM_Odm); -} -#endif - -#if (RTL8188E_SUPPORT == 1) - - -VOID -odm_RX_HWAntDiv_Init_88E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - - if(pDM_Odm->mp_mode == TRUE) - { - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS - return; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); - - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0001); //antenna mapping table - - pDM_FatTable->enable_ctrl_frame_antdiv = 1; -} - -VOID -odm_TRX_HWAntDiv_Init_88E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) - return; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n")); - - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - //antenna mapping table - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 - } - else //MPchip - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ - - pDM_FatTable->enable_ctrl_frame_antdiv = 1; -} - - -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_Smart_HWAntDiv_Init_88E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32, i; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); - - if(pDM_Odm->mp_mode == TRUE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); - return; - } - - pDM_FatTable->TrainIdx = 0; - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - - pDM_Odm->fat_comb_a=5; - pDM_Odm->antdiv_intvl = 0x64; // 100ms - - for(i=0; i<6; i++) - { - pDM_FatTable->Bssid[i] = 0; - } - for(i=0; i< (pDM_Odm->fat_comb_a) ; i++) - { - pDM_FatTable->antSumRSSI[i] = 0; - pDM_FatTable->antRSSIcnt[i] = 0; - pDM_FatTable->antAveRSSI[i] = 0; - } - - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match - //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); - //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet - - //Match MAC ADDR - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); - - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only - ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); - - //antenna mapping table - if(pDM_Odm->fat_comb_a == 2) - { - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 - } - else //MPchip - { - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); - } - } - else - { - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); - ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 - } - else //MPchip - { - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111 - } - } - - //Default Ant Setting when no fast training - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX - ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX - - //Enter Traing state - ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 - - //SW Control - //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); - //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); - //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); - //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); -} -#endif - -#endif //#if (RTL8188E_SUPPORT == 1) - - -#if (RTL8192E_SUPPORT == 1) -VOID -odm_RX_HWAntDiv_Init_92E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS - return; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); - - //Pin Settings - ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs - - //Mapping table - ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table - - //OFDM Settings - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias - - //CCK Settings - ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 - ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - #ifdef ODM_EVM_ENHANCE_ANTDIV - phydm_evm_sw_antdiv_init(pDM_Odm); - #endif - -} - -VOID -odm_TRX_HWAntDiv_Init_92E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS - return; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); - - //3 --RFE pin setting--------- - //[MAC] - ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8) - ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 - ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8 - //[BB] - ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer - ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1); - ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3) - ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8) - ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer - ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3) - ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8) - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3 - ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8 - //3 ------------------------- - - //Pin Settings - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch - -/* Let it follows PHY_REG for bit9 setting - if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna) - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS - else - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power -*/ - - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW - - //Mapping table - ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table - - //OFDM Settings - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias - - //CCK Settings - ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 - ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - #ifdef ODM_EVM_ENHANCE_ANTDIV - phydm_evm_sw_antdiv_init(pDM_Odm); - #endif -} - -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_Smart_HWAntDiv_Init_92E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); -} -#endif - -#endif //#if (RTL8192E_SUPPORT == 1) - -#if (RTL8197F_SUPPORT == 1) - -VOID -odm_RX_HWAntDiv_Init_97F( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS - return; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8197F AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); - - //Pin Settings - ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs - - //Mapping table - ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table - - //OFDM Settings - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias - - //CCK Settings - ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 - ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - #ifdef ODM_EVM_ENHANCE_ANTDIV - phydm_evm_sw_antdiv_init(pDM_Odm); - #endif - -} - - -#endif //#if (RTL8197F_SUPPORT == 1) - - -#if (RTL8723D_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8723D( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => AntDivType=[S0S1_HW_TRX_AntDiv]\n")); - - /*BT Coexistence*/ - /*keep antsel_map when GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 1); - /* //Disable hw antsw & fast_train.antsw when GNT_BT=1*/ - ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); - /*//Disable hw antsw & fast_train.antsw when BT TX/RX*/ - ODM_SetBBReg(pDM_Odm, 0xE64 , 0xFFFF0000, 0x000c); - - - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); - /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ - /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0);*/ - /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT8, 0);*/ - /*GNT_WL tx*/ - ODM_SetBBReg(pDM_Odm, 0x950 , BIT29, 0); - - - /*Mapping Table*/ - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 3); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); - - /* //Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0]*/ - ODM_SetBBReg(pDM_Odm, 0xCcc, BIT12, 0); - /* //Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable*/ - ODM_SetBBReg(pDM_Odm, 0xCcc , 0x0F, 0x01); - /*//High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable*/ - ODM_SetBBReg(pDM_Odm, 0xCcc , 0xF0, 0x0); - /* //b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ - ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF, 0x06); - /* //High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ - ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF00, 0x00); - - - /*OFDM HW AntDiv Parameters*/ - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); - ODM_SetBBReg(pDM_Odm, 0xC5C , BIT20|BIT19|BIT18, 0x04); - - /*CCK HW AntDiv Parameters*/ - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); - ODM_SetBBReg(pDM_Odm, 0xAA8 , BIT8, 0); - - ODM_SetBBReg(pDM_Odm, 0xA0C , 0x0F, 0xf); - ODM_SetBBReg(pDM_Odm, 0xA14 , 0x1F, 0x8); - ODM_SetBBReg(pDM_Odm, 0xA10 , BIT13, 0x1); - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT8, 0x0); - ODM_SetBBReg(pDM_Odm, 0xB34 , BIT30, 0x1); - - /*disable antenna training */ - ODM_SetBBReg(pDM_Odm, 0xE08 , BIT16, 0); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); - -} - -VOID -phydm_set_tx_ant_pwr_8723d( - IN PVOID pDM_VOID, - IN u1Byte Ant -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - pDM_FatTable->RxIdleAnt = Ant; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); - #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); - #endif - -} -#endif - -#if (RTL8723B_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8723B( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n")); - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1 - - //Output Pin Settings - ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); // - - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) - ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0); - - ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1); - ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1); - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin - - ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out - ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); // - - ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse - - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] - - //2 [--For HW Bug Setting] - if(pDM_Odm->AntType == ODM_AUTO_ANT) - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable - -} - - - -VOID -odm_S0S1_SWAntDiv_Init_8723B( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n")); - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); - - //Output Pin Settings - //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); - - pDM_FatTable->bBecomeLinked =FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; - - //2 [--For HW Bug Setting] - ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg - -} - -VOID -ODM_UpdateRxIdleAnt_8723B( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte DefaultAnt, - IN u4Byte OptionalAnt -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte count=0; - u1Byte u1Temp; - u1Byte H2C_Parameter; - - if ((!pDM_Odm->bLinked) && (pDM_Odm->AntType == ODM_AUTO_ANT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to no link\n")); - return; - } - -#if 0 - // Send H2C command to FW - // Enable wifi calibration - H2C_Parameter = TRUE; - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); - - // Check if H2C command sucess or not (0x1e6) - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); - while((u1Temp != 0x1) && (count < 100)) - { - ODM_delay_us(10); - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); - count++; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: H2C command status = %d, count = %d\n", u1Temp, count)); - - if(u1Temp == 0x1) - { - // Check if BT is doing IQK (0x1e7) - count = 0; - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); - while((!(u1Temp & BIT0)) && (count < 100)) - { - ODM_delay_us(50); - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); - count++; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: BT IQK status = %d, count = %d\n", u1Temp, count)); - - if(u1Temp & BIT0) - { - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX - pDM_FatTable->RxIdleAnt = Ant; - - // Set TX AGC by S0/S1 - // Need to consider Linux driver -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); -#endif - - // Set IQC by S0/S1 - ODM_SetIQCbyRFpath(pDM_Odm,DefaultAnt); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Sucess to set RX antenna\n")); - } - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); - } - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); - - // Send H2C command to FW - // Disable wifi calibration - H2C_Parameter = FALSE; - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); -#else - - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/ - pDM_FatTable->RxIdleAnt = Ant; - - /* Set TX AGC by S0/S1 */ - /* Need to consider Linux driver */ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); - #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); - #endif - - /* Set IQC by S0/S1 */ - ODM_SetIQCbyRFpath(pDM_Odm, DefaultAnt); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Success to set RX antenna\n")); - -#endif -} - -BOOLEAN -phydm_IsBtEnable_8723b( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte bt_state; - /*u4Byte reg75;*/ - - /*reg75 = ODM_GetBBReg(pDM_Odm, 0x74 , BIT8);*/ - /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0xa0 , BIT24|BIT25|BIT26, 0x5); - bt_state = ODM_GetBBReg(pDM_Odm, 0xa0 , (BIT3|BIT2|BIT1|BIT0)); - /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, reg75);*/ - - if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) - return TRUE; - else - return FALSE; -} -#endif //#if (RTL8723B_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -VOID -phydm_hl_smart_ant_type1_init_8821a( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte value32; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => AntDivType=[Hong-Lin Smart Ant Type1]\n")); - - /*---------------------------------------- - GPIO 2-3 for Beam control - reg0x66[2]=0 - reg0x44[27:26] = 0 - reg0x44[23:16] //enable_output for P_GPIO[7:0] - reg0x44[15:8] //output_value for P_GPIO[7:0] - reg0x40[1:0] = 0 //GPIO function - ------------------------------------------*/ - - /*GPIO Setting*/ - ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT27|BIT26, 0); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT19|BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, 0);*/ /*output value*/ - ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW Setting*/ - pdm_sat_table->data_codeword_bit_num = 24;/*max=32*/ - pdm_sat_table->beam_patten_num_each_ant = 4; - - #if DEV_BUS_TYPE == RT_SDIO_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ - #elif DEV_BUS_TYPE == RT_USB_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ - #endif - pdm_sat_table->pkt_skip_statistic_en = 0; - - pdm_sat_table->ant_num = 1;/*max=8*/ - pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A; - pdm_sat_table->first_train_ant = MAIN_ANT; - - pdm_sat_table->rfu_codeword_table[0] = 0x0; - pdm_sat_table->rfu_codeword_table[1] = 0x4; - pdm_sat_table->rfu_codeword_table[2] = 0x8; - pdm_sat_table->rfu_codeword_table[3] = 0xc; - - pdm_sat_table->rfu_codeword_table_5g[0] = 0x1; - pdm_sat_table->rfu_codeword_table_5g[1] = 0x2; - pdm_sat_table->rfu_codeword_table_5g[2] = 0x4; - pdm_sat_table->rfu_codeword_table_5g[3] = 0x8; - - pdm_sat_table->fix_beam_pattern_en = 0; - pdm_sat_table->decision_holding_period = 0; - - /*beam training setting*/ - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->per_beam_training_pkt_num = 10; - - /*set default beam*/ - pdm_sat_table->fast_training_beam_num = 0; - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - phydm_set_all_ant_same_beam_num(pDM_Odm); - - pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; - - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskDWord, 0x01000100); - ODM_SetBBReg(pDM_Odm, 0xCA8 , bMaskDWord, 0x01000100); - - /*[BB] FAT Setting*/ - ODM_SetBBReg(pDM_Odm, 0xc08 , BIT18|BIT17|BIT16, pdm_sat_table->ant_num); - ODM_SetBBReg(pDM_Odm, 0xc08 , BIT31, 0); /*increase ant num every FAT period 0:+1, 1+2*/ - ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT2|BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ - ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT0, 1); /*FAT_watchdog_en*/ - - value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /*Reg7B4[16]=1 enable antenna training */ - /*Reg7B4[17]=1 enable match MAC Addr*/ - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); - -} -#endif - -VOID -odm_TRX_HWAntDiv_Init_8821A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); - - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); - - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control - - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable - - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 - - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); - -} - -VOID -odm_S0S1_SWAntDiv_Init_8821A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); - - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); - - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control - - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable - - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 - - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); - - - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); - - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; - pDM_SWAT_Table->CurAntenna = MAIN_ANT; - pDM_SWAT_Table->PreAntenna = MAIN_ANT; - pDM_SWAT_Table->SWAS_NoLink_State = 0; - -} -#endif //#if (RTL8821A_SUPPORT == 1) - -#if (RTL8821C_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8821C( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); - - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control - - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable - - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 - - //Timming issue - ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); - -} -#endif //#if (RTL8821C_SUPPORT == 1) - - -#if (RTL8881A_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8881A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); - - //Output Pin Settings - // [SPDT related] - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); - ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1); - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0] - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - //2 [--For HW Bug Setting] - - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug -} - -#endif //#if (RTL8881A_SUPPORT == 1) - - -#if (RTL8812A_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8812A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); - - //3 //3 --RFE pin setting--------- - //[BB] - ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch - ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0); - ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1); - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0] - //3 ------------------------- - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - //2 [--For HW Bug Setting] - - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug - -} - -#endif //#if (RTL8812A_SUPPORT == 1) - -#if (RTL8188F_SUPPORT == 1) -VOID -odm_S0S1_SWAntDiv_Init_8188F( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); - - - /*GPIO Setting*/ - /*ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); */ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT28|BIT27, 0);*/ - ODM_SetMACReg(pDM_Odm, 0x44 , BIT20|BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT12|BIT11, 0);*/ /*output value*/ - /*ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0);*/ /*GPIO function*/ - - pDM_FatTable->bBecomeLinked = FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; -} - -VOID -phydm_update_rx_idle_antenna_8188F( - IN PVOID pDM_VOID, - IN u4Byte default_ant -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte codeword; - - if (default_ant == ANT1_2G) - codeword = 1; /*2'b01*/ - else - codeword = 2;/*2'b10*/ - - ODM_SetMACReg(pDM_Odm, 0x44 , (BIT12|BIT11), codeword); /*GPIO[4:3] output value*/ -} - -#endif - -VOID -odm_HW_AntDiv( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI; - u4Byte Main_RSSI, Aux_RSSI; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte RxIdleAnt = pDM_FatTable->RxIdleAnt, TargetAnt = 7; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PSTA_INFO_T pEntry; - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u4Byte TH1=500000; - u4Byte TH2=10000000; - u4Byte MA_rx_Temp, degrade_TP_temp, improve_TP_temp; - u1Byte Monitor_RSSI_threshold=30; - - pDM_BdcTable->BF_pass=TRUE; - pDM_BdcTable->DIV_pass=TRUE; - pDM_BdcTable->bAll_DivSta_Idle=TRUE; - pDM_BdcTable->bAll_BFSta_Idle=TRUE; - pDM_BdcTable->num_BfTar=0 ; - pDM_BdcTable->num_DivTar=0; - pDM_BdcTable->num_Client=0; - #endif - #endif - - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - pDM_Odm->antdiv_period=0; - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - /*odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);*/ - - //if(pDM_Odm->SupportICType == ODM_RTL8821 ) - //ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable - - //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - //else if(pDM_Odm->SupportICType == ODM_RTL8881A) - // ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable - //#endif - - //else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812) - //ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - - if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - { - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412 - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] - } - - //2 BDC Init - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_BDC_Init(pDM_Odm); - #endif - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_EVM_FastAnt_Reset(pDM_Odm); - #endif - } - } - - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n AntDiv Start =>\n")); - - #ifdef ODM_EVM_ENHANCE_ANTDIV - if(pDM_Odm->antdiv_evm_en==1) - { - odm_EVM_Enhance_AntDiv(pDM_Odm); - if(pDM_FatTable->FAT_State_cnt != 0) - return; - } - else - { - odm_EVM_FastAnt_Reset(pDM_Odm); - } - #endif - - //2 BDC Mode Arbitration - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_Odm->antdiv_evm_en == 0 ||pDM_FatTable->EVM_method_enable==0) - { - odm_BF_AntDiv_ModeArbitration(pDM_Odm); - } - #endif - #endif - - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - //2 Caculate RSSI per Antenna - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; - TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%d] \n",pDM_Odm->SupportICType)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI)); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2, - // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0))); - - LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; - //2 Select MaxRSSI for DIG - if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) - AntDivMaxRSSI = LocalMaxRSSI; - if(LocalMaxRSSI > MaxRSSI) - MaxRSSI = LocalMaxRSSI; - - //2 Select RX Idle Antenna - if ( (LocalMaxRSSI != 0) && (LocalMaxRSSI < MinMaxRSSI) ) - { - RxIdleAnt = TargetAnt; - MinMaxRSSI = LocalMaxRSSI; - } - - #ifdef ODM_EVM_ENHANCE_ANTDIV - if(pDM_Odm->antdiv_evm_en==1) - { - if(pDM_FatTable->TargetAnt_enhance!=0xFF) - { - TargetAnt=pDM_FatTable->TargetAnt_enhance; - RxIdleAnt = pDM_FatTable->TargetAnt_enhance; - } - } - #endif - - //2 Select TX Antenna - if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) - { - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->w_BFee_Client[i]==0) - #endif - #endif - { - odm_UpdateTxAnt(pDM_Odm, TargetAnt, i); - } - } - - //------------------------------------------------------------ - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - - pDM_BdcTable->num_Client++; - - if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - //2 Byte Counter - - MA_rx_Temp= (pEntry->rx_byte_cnt_LowMAW)<<3 ; // RX TP ( bit /sec) - - if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - pDM_BdcTable->MA_rx_TP_DIV[i]= MA_rx_Temp ; - } - else - { - pDM_BdcTable->MA_rx_TP[i] =MA_rx_Temp ; - } - - if( (MA_rx_Temp < TH2) && (MA_rx_Temp > TH1) && (LocalMaxRSSI<=Monitor_RSSI_threshold)) - { - if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target - { - pDM_BdcTable->num_BfTar++; - - if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) - { - improve_TP_temp = (pDM_BdcTable->MA_rx_TP_DIV[i] * 9)>>3 ; //* 1.125 - pDM_BdcTable->BF_pass = (pDM_BdcTable->MA_rx_TP[i] > improve_TP_temp)?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp , MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],improve_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->BF_pass )); - } - } - else// DIV_Target - { - pDM_BdcTable->num_DivTar++; - - if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) - { - degrade_TP_temp=(pDM_BdcTable->MA_rx_TP_DIV[i]*5)>>3;//* 0.625 - pDM_BdcTable->DIV_pass = (pDM_BdcTable->MA_rx_TP[i] >degrade_TP_temp)?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp , MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],degrade_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->DIV_pass )); - } - } - } - - if(MA_rx_Temp > TH1) - { - if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target - { - pDM_BdcTable->bAll_BFSta_Idle=FALSE; - } - else// DIV_Target - { - pDM_BdcTable->bAll_DivSta_Idle=FALSE; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap , BFmerCap} = { %d , %d } \n" ,i, pDM_BdcTable->w_BFee_Client[i] , pDM_BdcTable->w_BFer_Client[i])); - - if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP_DIV[i] )); - - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP[i] )); - } - - } - #endif - #endif - - } - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->BDC_Try_flag==0) - #endif - #endif - { - pDM_FatTable->MainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; - } - } - - - - //2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP ) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** RxIdleAnt = (( %s ))\n\n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->BDC_Mode==BDC_MODE_1 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** BDC_RxIdleUpdate_counter = (( %d ))\n", pDM_BdcTable->BDC_RxIdleUpdate_counter)); - - if(pDM_BdcTable->BDC_RxIdleUpdate_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!! \n")); - pDM_BdcTable->BDC_RxIdleUpdate_counter=30; - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - } - else - { - pDM_BdcTable->BDC_RxIdleUpdate_counter--; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); - } - } - else - #endif - #endif - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - #else - - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - - #endif//#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - - - - //2 BDC Main Algorithm - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_Odm->antdiv_evm_en ==0 ||pDM_FatTable->EVM_method_enable==0) - { - odm_BDCcoex_BFeeRxDiv_Arbitration(pDM_Odm); - } - #endif - #endif - - if(AntDivMaxRSSI == 0) - pDM_DigTable->AntDiv_RSSI_max = pDM_Odm->RSSI_Min; - else - pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; - - pDM_DigTable->RSSI_max = MaxRSSI; -} - - - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - -VOID -odm_S0S1_SWAntDiv_Reset( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - pDM_FatTable->bBecomeLinked = FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SWAntDiv_Reset(): pDM_FatTable->bBecomeLinked = %d\n", pDM_FatTable->bBecomeLinked)); -} - -VOID -odm_S0S1_SwAntDiv( - IN PVOID pDM_VOID, - IN u1Byte Step - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte i, MinMaxRSSI = 0xFF, LocalMaxRSSI, LocalMinRSSI; - u4Byte Main_RSSI, Aux_RSSI; - u1Byte HighTraffic_TrainTime_U = 0x32, HighTraffic_TrainTime_L = 0, Train_time_temp; - u1Byte LowTraffic_TrainTime_U = 200, LowTraffic_TrainTime_L = 0; - u1Byte RxIdleAnt = pDM_SWAT_Table->PreAntenna, TargetAnt, nextAnt = 0; - PSTA_INFO_T pEntry = NULL; - u4Byte value32; - - - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - ODM_SetBBReg(pDM_Odm, 0x948 , (BIT9|BIT8|BIT7|BIT6), 0x0); - } - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3); - - #if (RTL8723B_SUPPORT == 1) - if (value32 == 0x0) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, MAIN_ANT, ANT1_2G, ANT2_2G); - else if (value32 == 0x1) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, AUX_ANT, ANT2_2G, ANT1_2G); - #endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n",(value32 == 0x0?"MAIN":"AUX") )); - } - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - } - - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n", - __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag)); - - // Handling step mismatch condition. - // Peak step is not finished at last time. Recover the variable and check again. - if( Step != pDM_SWAT_Table->try_flag ) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag] Need to Reset After Link\n")); - ODM_SwAntDivRestAfterLink(pDM_Odm); - } - - if (pDM_SWAT_Table->try_flag == SWAW_STEP_INIT) { - - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - pDM_SWAT_Table->Train_time_flag=0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); - return; - - } else { - - //1 Normal State (Begin Trying) - if (pDM_SWAT_Table->try_flag == SWAW_STEP_PEEK) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), TrafficLoad = (%d))\n", pDM_Odm->curTxOkCnt, pDM_Odm->curRxOkCnt, pDM_Odm->TrafficLoad)); - - if (pDM_Odm->TrafficLoad == TRAFFIC_HIGH) - { - Train_time_temp = pDM_SWAT_Table->Train_time ; - - if(pDM_SWAT_Table->Train_time_flag==3) - { - HighTraffic_TrainTime_L=0xa; - - if(Train_time_temp<=16) - Train_time_temp=HighTraffic_TrainTime_L; - else - Train_time_temp-=16; - - } - else if(pDM_SWAT_Table->Train_time_flag==2) - { - Train_time_temp-=8; - HighTraffic_TrainTime_L=0xf; - } - else if(pDM_SWAT_Table->Train_time_flag==1) - { - Train_time_temp-=4; - HighTraffic_TrainTime_L=0x1e; - } - else if(pDM_SWAT_Table->Train_time_flag==0) - { - Train_time_temp+=8; - HighTraffic_TrainTime_L=0x28; - } - - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp)); - - //-- - if(Train_time_temp > HighTraffic_TrainTime_U) - Train_time_temp=HighTraffic_TrainTime_U; - - else if(Train_time_temp < HighTraffic_TrainTime_L) - Train_time_temp=HighTraffic_TrainTime_L; - - pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)), Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); - - } else if ((pDM_Odm->TrafficLoad == TRAFFIC_MID) || (pDM_Odm->TrafficLoad == TRAFFIC_LOW)) { - - Train_time_temp=pDM_SWAT_Table->Train_time ; - - if(pDM_SWAT_Table->Train_time_flag==3) - { - LowTraffic_TrainTime_L=10; - if(Train_time_temp<50) - Train_time_temp=LowTraffic_TrainTime_L; - else - Train_time_temp-=50; - } - else if(pDM_SWAT_Table->Train_time_flag==2) - { - Train_time_temp-=30; - LowTraffic_TrainTime_L=36; - } - else if(pDM_SWAT_Table->Train_time_flag==1) - { - Train_time_temp-=10; - LowTraffic_TrainTime_L=40; - } else { - - Train_time_temp += 10; - LowTraffic_TrainTime_L = 50; - } - - //-- - if(Train_time_temp >= LowTraffic_TrainTime_U) - Train_time_temp=LowTraffic_TrainTime_U; - - else if(Train_time_temp <= LowTraffic_TrainTime_L) - Train_time_temp=LowTraffic_TrainTime_L; - - pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)) , Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); - - } else { - pDM_SWAT_Table->Train_time = 0xc8; /*200ms*/ - - } - - //----------------- - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current MinMaxRSSI is ((%d))\n", pDM_FatTable->MinMaxRSSI)); - - //---reset index--- - if (pDM_SWAT_Table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { - - pDM_FatTable->MinMaxRSSI = 0; - pDM_SWAT_Table->reset_idx = 0; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", pDM_SWAT_Table->reset_idx)); - - pDM_SWAT_Table->reset_idx++; - - //---double check flag--- - if ((pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) && (pDM_SWAT_Table->Double_chk_flag == 0)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" MinMaxRSSI is ((%d)), and > %d\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); - - pDM_SWAT_Table->Double_chk_flag =1; - pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; - pDM_SWAT_Table->RSSI_Trying = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current Ant for (( %d )) ms again\n", pDM_SWAT_Table->Train_time)); - ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt); - ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ - return; - } - - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - - pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; - - if(pDM_SWAT_Table->reset_idx<=1) - pDM_SWAT_Table->RSSI_Trying = 2; - else - pDM_SWAT_Table->RSSI_Trying = 1; - - odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_PEEK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal State: Begin Trying!!\n")); - - } else if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->Double_chk_flag == 0)) { - - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - pDM_SWAT_Table->RSSI_Trying--; - } - - //1 Decision State - if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->RSSI_Trying == 0)) { - - BOOLEAN bByCtrlFrame = FALSE; - u8Byte pkt_cnt_total = 0; - - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - //2 Caculate RSSI per Antenna - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; - - if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1) - Main_RSSI=0; - - if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1) - Aux_RSSI=0; - - TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; - LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI )); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - //2 Select RX Idle Antenna - - if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI) - { - RxIdleAnt = TargetAnt; - MinMaxRSSI = LocalMaxRSSI; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI))); - - if((LocalMaxRSSI-LocalMinRSSI)>8) - { - if(LocalMinRSSI != 0) - pDM_SWAT_Table->Train_time_flag=3; - else - { - if (MinMaxRSSI > RSSI_CHECK_THRESHOLD) - pDM_SWAT_Table->Train_time_flag=0; - else - pDM_SWAT_Table->Train_time_flag=3; - } - } - else if((LocalMaxRSSI-LocalMinRSSI)>5) - pDM_SWAT_Table->Train_time_flag=2; - else if((LocalMaxRSSI-LocalMinRSSI)>2) - pDM_SWAT_Table->Train_time_flag=1; - else - pDM_SWAT_Table->Train_time_flag=0; - - } - - //2 Select TX Antenna - if(TargetAnt == MAIN_ANT) - pDM_FatTable->antsel_a[i] = ANT1_2G; - else - pDM_FatTable->antsel_a[i] = ANT2_2G; - - } - pDM_FatTable->MainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; - } - - if(pDM_SWAT_Table->bSWAntDivByCtrlFrame) - { - odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_DETERMINE); - bByCtrlFrame = TRUE; - } - - pkt_cnt_total = pDM_FatTable->CCK_counter_main + pDM_FatTable->CCK_counter_aux + - pDM_FatTable->OFDM_counter_main + pDM_FatTable->OFDM_counter_aux; - pDM_FatTable->CCK_counter_main=0; - pDM_FatTable->CCK_counter_aux=0; - pDM_FatTable->OFDM_counter_main=0; - pDM_FatTable->OFDM_counter_aux=0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame packet counter = %d, Data frame packet counter = %llu\n", - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame, pkt_cnt_total)); - - if(MinMaxRSSI == 0xff || ((pkt_cnt_total < (pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame >> 1)) && pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)) - { - MinMaxRSSI = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Check RSSI of control frame because MinMaxRSSI == 0xff\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bByCtrlFrame = %d\n", bByCtrlFrame)); - - if(bByCtrlFrame) - { - Main_RSSI = (pDM_FatTable->MainAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->MainAnt_CtrlFrame_Sum/pDM_FatTable->MainAnt_CtrlFrame_Cnt):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->AuxAnt_CtrlFrame_Sum/pDM_FatTable->AuxAnt_CtrlFrame_Cnt):0; - - if(pDM_FatTable->MainAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_main>=1) - Main_RSSI=0; - - if(pDM_FatTable->AuxAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_aux>=1) - Aux_RSSI=0; - - if (Main_RSSI != 0 || Aux_RSSI != 0) - { - RxIdleAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; - LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; - - if((LocalMaxRSSI-LocalMinRSSI)>8) - pDM_SWAT_Table->Train_time_flag=3; - else if((LocalMaxRSSI-LocalMinRSSI)>5) - pDM_SWAT_Table->Train_time_flag=2; - else if((LocalMaxRSSI-LocalMinRSSI)>2) - pDM_SWAT_Table->Train_time_flag=1; - else - pDM_SWAT_Table->Train_time_flag=0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame: Main_RSSI = %d, Aux_RSSI = %d\n", Main_RSSI, Aux_RSSI)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt decided by control frame = %s\n", (RxIdleAnt == MAIN_ANT?"MAIN":"AUX"))); - } - } - } - - pDM_FatTable->MinMaxRSSI = MinMaxRSSI; - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - - if( pDM_SWAT_Table->Double_chk_flag==1) - { - pDM_SWAT_Table->Double_chk_flag=0; - - if (pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) > %d again!!\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); - - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); - return; - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) <= %d !!\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); - - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal State: Need to tryg again!!\n\n\n")); - return; - } - } - else - { - if (pDM_FatTable->MinMaxRSSI < RSSI_CHECK_THRESHOLD) - pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; - - pDM_SWAT_Table->PreAntenna =RxIdleAnt; - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt ); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); - return; - } - - } - - } - - //1 4.Change TRX antenna - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )), Ant: (( %s )) >>> (( %s )) \n", - pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX"))); - - ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt); - - //1 5.Reset Statistics - - pDM_FatTable->RxIdleAnt = nextAnt; - - //1 6.Set next timer (Trying State) - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms\n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time)); - ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ -} - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_SW_AntDiv_Callback( - PRT_TIMER pTimer -) -{ - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; - - #if DEV_BUS_TYPE==RT_PCI_INTERFACE - #if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); - #else - { - //DbgPrint("SW_antdiv_Callback"); - odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); - } - #endif - #else - ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); - #endif -} -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext - ) -{ - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //DbgPrint("SW_antdiv_Workitem_Callback"); - odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); -} - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext -) -{ - PADAPTER - pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE - *pHalData = GET_HAL_DATA(pAdapter); - - /*DbgPrint("SW_antdiv_Workitem_Callback");*/ - odm_S0S1_SwAntDiv(&pHalData->odmpriv, SWAW_STEP_DETERMINE); -} - -VOID -ODM_SW_AntDiv_Callback(void *FunctionContext) -{ - PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; - PADAPTER padapter = pDM_Odm->Adapter; - if(padapter->net_closed == _TRUE) - return; - - #if 0 /* Can't do I/O in timer callback*/ - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE); - #else - rtw_run_in_thread_cmd(padapter, ODM_SW_AntDiv_WorkitemCallback, padapter); - #endif -} - - -#endif - -VOID -odm_S0S1_SwAntDivByCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte Step - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - switch(Step) - { - case SWAW_STEP_PEEK: - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame = 0; - pDM_SWAT_Table->bSWAntDivByCtrlFrame = TRUE; - pDM_FatTable->MainAnt_CtrlFrame_Cnt = 0; - pDM_FatTable->AuxAnt_CtrlFrame_Cnt = 0; - pDM_FatTable->MainAnt_CtrlFrame_Sum = 0; - pDM_FatTable->AuxAnt_CtrlFrame_Sum = 0; - pDM_FatTable->CCK_CtrlFrame_Cnt_main = 0; - pDM_FatTable->CCK_CtrlFrame_Cnt_aux = 0; - pDM_FatTable->OFDM_CtrlFrame_Cnt_main = 0; - pDM_FatTable->OFDM_CtrlFrame_Cnt_aux = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); - break; - case SWAW_STEP_DETERMINE: - pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); - break; - default: - pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; - break; - } -} - -VOID -odm_AntselStatisticsOfCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte RxPWDBAll - - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(antsel_tr_mux == ANT1_2G) - { - pDM_FatTable->MainAnt_CtrlFrame_Sum+=RxPWDBAll; - pDM_FatTable->MainAnt_CtrlFrame_Cnt++; - } - else - { - pDM_FatTable->AuxAnt_CtrlFrame_Sum+=RxPWDBAll; - pDM_FatTable->AuxAnt_CtrlFrame_Cnt++; - } -} - -VOID -odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - //IN PODM_PHY_INFO_T pPhyInfo, - //IN PODM_PACKET_INFO_T pPktinfo - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - BOOLEAN isCCKrate; - - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - return; - - if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV) - return; - - // In try state - if(!pDM_SWAT_Table->bSWAntDivByCtrlFrame) - return; - - // No HW error and match receiver address - if(!pPktinfo->bToSelf) - return; - - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame++; - isCCKrate = ((pPktinfo->DataRate >= DESC_RATE1M ) && (pPktinfo->DataRate <= DESC_RATE11M ))?TRUE :FALSE; - - if(isCCKrate) - { - pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; - - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->CCK_CtrlFrame_Cnt_main++; - else - pDM_FatTable->CCK_CtrlFrame_Cnt_aux++; - - odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); - } - else - { - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->OFDM_CtrlFrame_Cnt_main++; - else - pDM_FatTable->OFDM_CtrlFrame_Cnt_aux++; - - odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxPWDBAll); - } -} - -#endif //#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) - - - - -VOID -odm_SetNextMACAddrTarget( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PSTA_INFO_T pEntry; - u4Byte value32, i; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); - - if (pDM_Odm->bLinked) - { - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - if ((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) - pDM_FatTable->TrainIdx = 0; - else - pDM_FatTable->TrainIdx++; - - pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; - - if (IS_STA_VALID(pEntry)) { - - /*Match MAC ADDR*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; - #else - value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; - #endif - - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; - #else - value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; - #endif - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);/*0x7b0~0x7b3*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n", pDM_FatTable->TrainIdx)); - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", - pEntry->hwaddr[5], pEntry->hwaddr[4], pEntry->hwaddr[3], pEntry->hwaddr[2], pEntry->hwaddr[1], pEntry->hwaddr[0])); - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", - pEntry->MacAddr[5], pEntry->MacAddr[4], pEntry->MacAddr[3], pEntry->MacAddr[2], pEntry->MacAddr[1], pEntry->MacAddr[0])); - #endif - - break; - } - } - } - -#if 0 - // - //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn - // - #if( DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - - for (i=0; i<6; i++) - { - Bssid[i] = pMgntInfo->Bssid[i]; - //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); - } - } - #endif - - //odm_SetNextMACAddrTarget(pDM_Odm); - - //1 Select MAC Address Filter - for (i=0; i<6; i++) - { - if(Bssid[i] != pDM_FatTable->Bssid[i]) - { - bMatchBSSID = FALSE; - break; - } - } - if(bMatchBSSID == FALSE) - { - //Match MAC ADDR - value32 = (Bssid[5]<<8)|Bssid[4]; - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); - value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); - } - - return bMatchBSSID; -#endif - -} - -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - -VOID -odm_FastAntTraining( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - u4Byte MaxRSSI_pathA=0, Pckcnt_pathA=0; - u1Byte i,TargetAnt_pathA=0; - BOOLEAN bPktFilterMacth_pathA = FALSE; - #if(RTL8192E_SUPPORT == 1) - u4Byte MaxRSSI_pathB=0, Pckcnt_pathB=0; - u1Byte TargetAnt_pathB=0; - BOOLEAN bPktFilterMacth_pathB = FALSE; - #endif - - - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - } - - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - - - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1)); - } - #if(RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1) ); //path-A // ant combination=regB38[2:0]+1 - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT18|BIT17|BIT16, ((pDM_Odm->fat_comb_b)-1) ); //path-B // ant combination=regB38[18:16]+1 - } - #endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); - - //1 TRAINING STATE - if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) - { - //2 Caculate RSSI per Antenna - - //3 [path-A]--------------------------- - for (i=0; i<(pDM_Odm->fat_comb_a); i++) // i : antenna index - { - if(pDM_FatTable->antRSSIcnt[i] == 0) - pDM_FatTable->antAveRSSI[i] = 0; - else - { - pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; - bPktFilterMacth_pathA = TRUE; - } - - if(pDM_FatTable->antAveRSSI[i] > MaxRSSI_pathA) - { - MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; - Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; - TargetAnt_pathA = i ; - } - else if(pDM_FatTable->antAveRSSI[i] == MaxRSSI_pathA) - { - if( (pDM_FatTable->antRSSIcnt[i] ) > Pckcnt_pathA) - { - MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; - Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; - TargetAnt_pathA = i ; - } - } - - ODM_RT_TRACE("*** Ant-Index : [ %d ], Counter = (( %d )), Avg RSSI = (( %d )) \n", i, pDM_FatTable->antRSSIcnt[i], pDM_FatTable->antAveRSSI[i] ); - } - - - /* - #if(RTL8192E_SUPPORT == 1) - //3 [path-B]--------------------------- - for (i=0; i<(pDM_Odm->fat_comb_b); i++) - { - if(pDM_FatTable->antRSSIcnt_pathB[i] == 0) - pDM_FatTable->antAveRSSI_pathB[i] = 0; - else // (antRSSIcnt[i] != 0) - { - pDM_FatTable->antAveRSSI_pathB[i] = pDM_FatTable->antSumRSSI_pathB[i] /pDM_FatTable->antRSSIcnt_pathB[i]; - bPktFilterMacth_pathB = TRUE; - } - if(pDM_FatTable->antAveRSSI_pathB[i] > MaxRSSI_pathB) - { - MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; - Pckcnt_pathB = pDM_FatTable ->antRSSIcnt_pathB[i]; - TargetAnt_pathB = (u1Byte) i; - } - if(pDM_FatTable->antAveRSSI_pathB[i] == MaxRSSI_pathB) - { - if(pDM_FatTable ->antRSSIcnt_pathB > Pckcnt_pathB) - { - MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; - TargetAnt_pathB = (u1Byte) i; - } - } - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{Path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d )) \n", - i, pDM_FatTable->antSumRSSI_pathB[i], i, pDM_FatTable->antRSSIcnt_pathB[i], i, pDM_FatTable->antAveRSSI_pathB[i])); - } - } - #endif - */ - - //1 DECISION STATE - - //2 Select TRX Antenna - - phydm_FastTraining_enable(pDM_Odm, FAT_OFF); - - //3 [path-A]--------------------------- - if(bPktFilterMacth_pathA == FALSE) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } - else - { - ODM_RT_TRACE("TargetAnt_pathA = (( %d )) , MaxRSSI_pathA = (( %d )) \n",TargetAnt_pathA,MaxRSSI_pathA); - - //3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt_pathA); - } - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, TargetAnt_pathA);//Optional RX [pth-A] - } - //3 [ update TX ant ] - odm_UpdateTxAnt(pDM_Odm, TargetAnt_pathA, (pDM_FatTable->TrainIdx)); - - if(TargetAnt_pathA == 0) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } - /* - #if(RTL8192E_SUPPORT == 1) - //3 [path-B]--------------------------- - if(bPktFilterMacth_pathB == FALSE) - { - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{Path-B}: None Packet is matched\n\n\n",__LINE__)); - } - } - else - { - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - (" ***TargetAnt_pathB = (( %d )) *** MaxRSSI = (( %d ))***\n\n\n",TargetAnt_pathB,MaxRSSI_pathB)); - } - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT21|BIT20|BIT19, TargetAnt_pathB); //Default RX is Omni, Optional RX is the best decision by FAT - ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info - - pDM_FatTable->antsel_pathB[pDM_FatTable->TrainIdx] = TargetAnt_pathB; - } - #endif - */ - - //2 Reset Counter - for(i=0; i<(pDM_Odm->fat_comb_a); i++) - { - pDM_FatTable->antSumRSSI[i] = 0; - pDM_FatTable->antRSSIcnt[i] = 0; - } - /* - #if(RTL8192E_SUPPORT == 1) - for(i=0; i<=(pDM_Odm->fat_comb_b); i++) - { - pDM_FatTable->antSumRSSI_pathB[i] = 0; - pDM_FatTable->antRSSIcnt_pathB[i] = 0; - } - #endif - */ - - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - return; - } - - //1 NORMAL STATE - if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare State ]\n")); - - odm_SetNextMACAddrTarget(pDM_Odm); - - //2 Prepare Training - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - phydm_FastTraining_enable(pDM_Odm , FAT_ON); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); //enable HW AntDiv - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training State]\n")); - - ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms - } - -} - -VOID -odm_FastAntTrainingCallback( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER padapter = pDM_Odm->Adapter; - if(padapter->net_closed == _TRUE) - return; - //if(*pDM_Odm->pbNet_closed == TRUE) - // return; -#endif - -#if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingCallback****** \n")); - odm_FastAntTraining(pDM_Odm); -#endif -} - -VOID -odm_FastAntTrainingWorkItemCallback( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingWorkItemCallback****** \n")); - odm_FastAntTraining(pDM_Odm); -} - -#endif - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - -u4Byte -phydm_construct_hl_beam_codeword( - IN PVOID pDM_VOID, - IN u4Byte *beam_pattern_idx, - IN u4Byte ant_num - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte codeword = 0; - u4Byte data_tmp; - u4Byte i; - u4Byte break_counter = 0; - - if (ant_num < 8) { - for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ - if ((i < (pdm_sat_table->first_train_ant-1)) || (break_counter >= (pdm_sat_table->ant_num))) { - data_tmp = 0; - /**/ - } else { - - break_counter++; - - if (beam_pattern_idx[i] == 0) { - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[0]; - - } else if (beam_pattern_idx[i] == 1) { - - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[1]; - - } else if (beam_pattern_idx[i] == 2) { - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[2]; - - } else if (beam_pattern_idx[i] == 3) { - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[3]; - } - } - - - codeword |= (data_tmp<<(i*4)); - - } - } - - return codeword; -} - -VOID -phydm_update_beam_pattern( - IN PVOID pDM_VOID, - IN u4Byte codeword, - IN u4Byte codeword_length - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u1Byte i; - BOOLEAN beam_ctrl_signal; - u4Byte one = 0x1; - u4Byte reg44_tmp_p, reg44_tmp_n, reg44_ori; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); - - reg44_ori = ODM_GetMACReg(pDM_Odm, 0x44, bMaskDWord); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ - - for (i = 0; i <= (codeword_length-1); i++) { - beam_ctrl_signal = (BOOLEAN)((codeword&BIT(i)) >> i); - - if (pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length-1)) { - DbgPrint("%d ]\n", beam_ctrl_signal); - /**/ - } else if (i == 0) { - DbgPrint("Send codeword[1:24] ---> [ %d ", beam_ctrl_signal); - /**/ - } else if ((i % 4) == 3) { - DbgPrint("%d | ", beam_ctrl_signal); - /**/ - } else { - DbgPrint("%d ", beam_ctrl_signal); - /**/ - } - } - - #if 1 - reg44_tmp_p = reg44_ori & (~(BIT11|BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1<<11) | (beam_ctrl_signal<<10)); - reg44_tmp_n = reg44_ori & (~(BIT11|BIT10)); - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_p); - ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_n); - #else - ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, ((1<<1) | beam_ctrl_signal)); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT11, 0); - #endif - - } -} - -VOID -phydm_update_rx_idle_beam( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte i; - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - - for (i = 0; i < (pdm_sat_table->ant_num); i++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); - /**/ - } - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ - #endif - - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; -} - -VOID -phydm_hl_smart_ant_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte one = 0x1; - u4Byte codeword_length = pdm_sat_table->data_codeword_bit_num; - u4Byte beam_ctrl_signal, i; - - if (dm_value[0] == 1) { /*fix beam pattern*/ - - pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - - if (pdm_sat_table->fix_beam_pattern_en == 1) { - - pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - - if (pdm_sat_table->fix_beam_pattern_codeword > (one<fix_beam_pattern_codeword, codeword_length)); - (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); - } - - pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; - - /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output+used, out_len-used, "Fix Beam Pattern\n")); - for (i = 0; i <= (codeword_length-1); i++) { - beam_ctrl_signal = (BOOLEAN)((pdm_sat_table->update_beam_codeword&BIT(i)) >> i); - - if (i == (codeword_length-1)) { - PHYDM_SNPRINTF((output+used, out_len-used, "%d]\n", beam_ctrl_signal)); - /**/ - } else if (i == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); - /**/ - } else if ((i % 4) == 3) { - PHYDM_SNPRINTF((output+used, out_len-used, "%d|", beam_ctrl_signal)); - /**/ - } else { - PHYDM_SNPRINTF((output+used, out_len-used, "%d", beam_ctrl_signal)); - /**/ - } - } - /*---------------------------------------------------------*/ - - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ - #endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Smart Antenna: Enable\n")); - } - - } else if (dm_value[0] == 2) { /*set latch time*/ - - pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); - } else if (dm_value[0] == 3) { - - pdm_sat_table->fix_training_num_en = dm_value[1]; - - if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u1Byte)dm_value[2]; - pdm_sat_table->decision_holding_period = (u1Byte)dm_value[3]; - - PHYDM_SNPRINTF((output+used, out_len-used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); - /**/ - } - } else if (dm_value[0] == 4) { - - if (dm_value[1] == 1) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = MAIN_ANT; - - } else if (dm_value[1] == 2) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = AUX_ANT; - - } else if (dm_value[1] == 3) { - pdm_sat_table->ant_num = 2; - pdm_sat_table->first_train_ant = MAIN_ANT; - } - - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant-1))); - } else if (dm_value[0] == 5) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table[i])); - } - } - } else if (dm_value[0] == 6) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table_5g[i])); - } - } - } else if (dm_value[0] == 7) { - - if (dm_value[1] <= 4) { - - pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } else { - - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } - } - -} - - -void -phydm_set_all_ant_same_beam_num( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { /*2Ant for 8821A*/ - - pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; - } - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ - #endif -} - -VOID -odm_FastAntTraining_hl_smart_antenna_type1( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - pFAT_T pDM_FatTable = &(pDM_Odm->DM_FatTable); - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u4Byte codeword = 0, i, j; - u4Byte TargetAnt; - u4Byte avg_rssi_tmp, avg_rssi_tmp_ma; - u4Byte target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; - u4Byte max_beam_ant_rssi = 0; - u4Byte target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; - u4Byte beam_tmp; - u1Byte next_ant; - u4Byte rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u4Byte rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u4Byte rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u1Byte per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; - u4Byte break_counter = 0; - u4Byte used_ant; - - - if (!pDM_Odm->bLinked) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (pDM_FatTable->bBecomeLinked == TRUE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link -> no Link\n")); - pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - return; - - } else { - if (pDM_FatTable->bBecomeLinked == FALSE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); - - /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_all_ant_same_beam_num(pDM_Odm);*/ - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; - } - } - - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart Ant Training: State (( %d ))\n", pDM_FatTable->FAT_State));*/ - - /* [DECISION STATE] */ - /*=======================================================================================*/ - if (pDM_FatTable->FAT_State == FAT_DECISION_STATE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision State]\n")); - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); - - break_counter = 0; - /*compute target beam in each antenna*/ - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { - avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j])>>1; - } - - rssi_sorting_seq[j] = avg_rssi_tmp; - pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", - i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); - - if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { - target_ant_beam[i] = j; - target_ant_beam_max_rssi[i] = avg_rssi_tmp; - } - - /*reset counter value*/ - pdm_sat_table->pkt_rssi_sum[i][j] = 0; - pdm_sat_table->pkt_rssi_cnt[i][j] = 0; - - } - pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of Ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", - i, target_ant_beam[i], target_ant_beam_max_rssi[i])); - - /*sorting*/ - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - */ - - /*phydm_seq_sorting(pDM_Odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ - - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); - */ - - if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { - TargetAnt = i; - max_beam_ant_rssi = target_ant_beam_max_rssi[i]; - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of Ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", - TargetAnt, max_beam_ant_rssi));*/ - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - - #ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = (u1Byte)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); - pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", - i, j, per_beam_rssi_diff_tmp)); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - #endif - - if (TargetAnt == 0) - TargetAnt = MAIN_ANT; - else if (TargetAnt == 1) - TargetAnt = AUX_ANT; - - if (pdm_sat_table->ant_num > 1) { - /* [ update RX ant ]*/ - ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)TargetAnt); - - /* [ update TX ant ]*/ - odm_UpdateTxAnt(pDM_Odm, (u1Byte)TargetAnt, (pDM_FatTable->TrainIdx)); - } - - /*set beam in each antenna*/ - phydm_update_rx_idle_beam(pDM_Odm); - - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - - } - /* [TRAINING STATE] */ - else if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training State]\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", - pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); - - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) { - - pdm_sat_table->force_update_beam_en = 0; - - } else { - - pdm_sat_table->force_update_beam_en = 1; - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); - - } else { - pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(pDM_Odm); - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - - } - } - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); - } - /* [Prepare State] */ - /*=======================================================================================*/ - else if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare State]\n")); - - if (pDM_Odm->pre_TrafficLoad == (pDM_Odm->TrafficLoad)) { - if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); - pdm_sat_table->decision_holding_period--; - return; - } - } - - - /* Set training packet number*/ - if (pdm_sat_table->fix_training_num_en == 0) { - - switch (pDM_Odm->TrafficLoad) { - - case TRAFFIC_HIGH: - pdm_sat_table->per_beam_training_pkt_num = 8; - pdm_sat_table->decision_holding_period = 2; - break; - case TRAFFIC_MID: - pdm_sat_table->per_beam_training_pkt_num = 6; - pdm_sat_table->decision_holding_period = 3; - break; - case TRAFFIC_LOW: - pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ - pdm_sat_table->decision_holding_period = 4; - break; - case TRAFFIC_ULTRA_LOW: - pdm_sat_table->per_beam_training_pkt_num = 1; - pdm_sat_table->decision_holding_period = 6; - break; - default: - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", - pdm_sat_table->fix_training_num_en , pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - - #ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; - training_pkt_num_offset = per_beam_rssi_diff_tmp; - - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_train_cnt[i][j] = 1; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", - i, j, pdm_sat_table->beam_train_cnt[i][j])); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - - - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - - if (*pDM_Odm->pBandType == ODM_BAND_5G) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); - /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ - used_ant = pdm_sat_table->first_train_ant; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); - used_ant = pdm_sat_table->first_train_ant; - } - - ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)used_ant); - - #else - /* Set training MAC Addr. of target */ - odm_SetNextMACAddrTarget(pDM_Odm); - phydm_FastTraining_enable(pDM_Odm , FAT_ON); - #endif - - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->fast_training_beam_num = 0; - phydm_set_all_ant_same_beam_num(pDM_Odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - } - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -phydm_beam_switch_workitem_callback( - IN PVOID pContext - ) -{ - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - - #if DEV_BUS_TYPE != RT_PCI_INTERFACE - pdm_sat_table->pkt_skip_statistic_en = 1; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); - - #if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*ODM_StallExecution(pdm_sat_table->latch_time);*/ - pdm_sat_table->pkt_skip_statistic_en = 0; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); -} - -VOID -phydm_beam_decision_workitem_callback( - IN PVOID pContext - ) -{ - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); -} -#endif - -#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ - -VOID -ODM_AntDivInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } - //--- -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) - return; - } - else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) - return; - } - else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); - } - -#endif - //--- - - //2 [--General---] - pDM_Odm->antdiv_period=0; - - pDM_FatTable->bBecomeLinked =FALSE; - pDM_FatTable->AntDiv_OnOff =0xff; - - //3 - AP - - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_BDC_Init(pDM_Odm); - #endif - #endif - - //3 - WIN - - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_SWAT_Table->Ant5G = MAIN_ANT; - pDM_SWAT_Table->Ant2G = MAIN_ANT; - pDM_FatTable->CCK_counter_main=0; - pDM_FatTable->CCK_counter_aux=0; - pDM_FatTable->OFDM_counter_main=0; - pDM_FatTable->OFDM_counter_aux=0; - #endif - - //2 [---Set MAIN_ANT as default antenna if Auto-Ant enable---] - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - - pDM_Odm->AntType = ODM_AUTO_ANT; - - pDM_FatTable->RxIdleAnt = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - phydm_keep_RxAckAnt_By_TxAnt_time( pDM_Odm, 5); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ - - //2 [---Set TX Antenna---] - pDM_FatTable->ForceTxAntByDesc = 0; - pDM_FatTable->pForceTxAntByDesc = &(pDM_FatTable->ForceTxAntByDesc); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("pForceTxAntByDesc = %d\n", *pDM_FatTable->pForceTxAntByDesc)); - - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - - - //2 [--88E---] - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - #if (RTL8188E_SUPPORT == 1) - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - - if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 88E Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - odm_RX_HWAntDiv_Init_88E(pDM_Odm); - else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_88E(pDM_Odm); - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) - odm_Smart_HWAntDiv_Init_88E(pDM_Odm); - #endif - #endif - } - - //2 [--92E---] - #if (RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - - if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8192E Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - odm_RX_HWAntDiv_Init_92E(pDM_Odm); - else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_92E(pDM_Odm); - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) - odm_Smart_HWAntDiv_Init_92E(pDM_Odm); - #endif - - } - #endif - - //2 [--97F---] - #if (RTL8197F_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8197F) - { - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if( pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8197F Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - odm_RX_HWAntDiv_Init_97F(pDM_Odm); - - } - #endif - - //2 [--8723B---] - #if (RTL8723B_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV) - odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm); - else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8723B(pDM_Odm); - } - #endif - /*2 [--8723D---]*/ - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (pDM_Odm->AntDivType == S0S1_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8723D(pDM_Odm); - else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - } - #endif - //2 [--8811A 8821A---] - #if (RTL8821A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8821) - { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pDM_Odm->AntDivType = HL_SW_SMART_ANT_TYPE1; - - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { - - odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); - phydm_hl_smart_ant_type1_init_8821a(pDM_Odm); - } else - #endif - { - /*pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;*/ - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - - if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); - else if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) - odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm); - } - } - #endif - - //2 [--8821C---] - #if (RTL8821C_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8821C) - { - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV ) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - odm_TRX_HWAntDiv_Init_8821C(pDM_Odm); - } - #endif - - //2 [--8881A---] - #if (RTL8881A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8881A) - { - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { - - odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); - /**/ - } else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); - } - #endif - - //2 [--8812---] - #if (RTL8812A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - odm_TRX_HWAntDiv_Init_8812A(pDM_Odm); - } - #endif - - /*[--8188F---]*/ - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - odm_S0S1_SWAntDiv_Init_8188F(pDM_Odm); - } - #endif - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** SupportICType=[%lu]\n",pDM_Odm->SupportICType)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv SupportAbility=[%lu]\n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv Type=[%d]\n",pDM_Odm->AntDivType)); - */ -} - -VOID -ODM_AntDiv( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - #endif - - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period ) - { - pDM_FatTable->idx_AntDiv_counter_5G++; - return; - } - else - pDM_FatTable->idx_AntDiv_counter_5G=0; - } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - if(pDM_FatTable->idx_AntDiv_counter_2G < pDM_Odm->antdiv_period ) - { - pDM_FatTable->idx_AntDiv_counter_2G++; - return; - } - else - pDM_FatTable->idx_AntDiv_counter_2G=0; - } - - //---------- - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } - - //---------- -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - if (pDM_FatTable->enable_ctrl_frame_antdiv) { - - if ((pDM_Odm->data_frame_num <= 10) && (pDM_Odm->bLinked)) - pDM_FatTable->use_ctrl_frame_antdiv = 1; - else - pDM_FatTable->use_ctrl_frame_antdiv = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", pDM_FatTable->use_ctrl_frame_antdiv, pDM_Odm->data_frame_num)); - pDM_Odm->data_frame_num = 0; - } - - if(pAdapter->MgntInfo.AntennaTest) - return; - - { - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); - - if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n")); - if(pDM_FatTable->fix_ant_bfee == 0) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - pDM_FatTable->fix_ant_bfee = 1; - } - return; - } - else // BFmee Off && Div Off -> Div On - { - if((pDM_FatTable->fix_ant_bfee == 1) && pDM_Odm->bLinked) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); - if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) ) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - - pDM_FatTable->fix_ant_bfee = 0; - } - } - #endif - } -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - //----------just for fool proof - - if(pDM_Odm->antdiv_rssi) - pDM_Odm->DebugComponents |= ODM_COMP_ANT_DIV; - else - pDM_Odm->DebugComponents &= ~ODM_COMP_ANT_DIV; - - if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) - { - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) - return; - } - else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) - { - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) - return; - } - //else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) - //{ - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); - //} -#endif - - //---------- - - if (pDM_Odm->antdiv_select==1) - pDM_Odm->AntType = ODM_FIX_MAIN_ANT; - else if (pDM_Odm->antdiv_select==2) - pDM_Odm->AntType = ODM_FIX_AUX_ANT; - else //if (pDM_Odm->antdiv_select==0) - pDM_Odm->AntType = ODM_AUTO_ANT; - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType)); - - if(pDM_Odm->AntType != ODM_AUTO_ANT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX")); - - if(pDM_Odm->AntType != pDM_Odm->pre_AntType) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - - if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); - } - pDM_Odm->pre_AntType=pDM_Odm->AntType; - return; - } - else - { - if(pDM_Odm->AntType != pDM_Odm->pre_AntType) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - pDM_Odm->pre_AntType=pDM_Odm->AntType; - } - - - //3 ----------------------------------------------------------------------------------------------------------- - //2 [--88E---] - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - #if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - odm_FastAntTraining(pDM_Odm); - #endif - - #endif - - } - //2 [--92E---] - #if (RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV || pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - odm_FastAntTraining(pDM_Odm); - #endif - - } - #endif - - //2 [--97F---] - #if (RTL8197F_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8197F) - { - if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - } - #endif - - #if (RTL8723B_SUPPORT == 1) - //2 [--8723B---] - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if (phydm_IsBtEnable_8723b(pDM_Odm)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); - if (pDM_FatTable->bBecomeLinked == TRUE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); - - pDM_FatTable->bBecomeLinked = FALSE; - } - } else { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - } - } - #endif - /*8723D*/ - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - - odm_HW_AntDiv(pDM_Odm); - /**/ - } - #endif - - //2 [--8821A---] - #if (RTL8821A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821) - { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { - - if (pdm_sat_table->fix_beam_pattern_en != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); - /*return;*/ - } else { - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] AntDivType = HL_SW_SMART_ANT_TYPE1\n"));*/ - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); - } - - } else - #endif - { - - if (!pDM_Odm->bBtEnabled) /*BT disabled*/ - { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); - /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); */ - if (pDM_FatTable->bBecomeLinked == TRUE) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - } - - } else { /*BT enabled*/ - - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); - /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);*/ - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } - } - - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - } - } - #endif - - //2 [--8821C---] - #if (RTL8821C_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821C) - { - odm_HW_AntDiv(pDM_Odm); - } - #endif - - //2 [--8881A---] - #if (RTL8881A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8881A) - odm_HW_AntDiv(pDM_Odm); - #endif - - //2 [--8812A---] - #if (RTL8812A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8812) - odm_HW_AntDiv(pDM_Odm); - #endif - - #if (RTL8188F_SUPPORT == 1) - /* [--8188F---]*/ - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } - #endif - -} - - -VOID -odm_AntselStatistics( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN u1Byte antsel_tr_mux, - IN u4Byte MacId, - IN u4Byte utility, - IN u1Byte method, - IN u1Byte isCCKrate - - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - - if (method == RSSI_METHOD) { - - #ifdef ODM_EVM_ENHANCE_ANTDIV - if (isCCKrate) { - if (antsel_tr_mux == ANT1_2G) { - if (pDM_FatTable->MainAnt_Sum_cck[MacId] > 65435) /*to prevent u2Byte overflow, max(RSSI)=100, 65435+100 = 65535 (u2Byte)*/ - return; - - pDM_FatTable->MainAnt_Sum_cck[MacId] += (u2Byte)utility; - pDM_FatTable->MainAnt_Cnt_cck[MacId]++; - } else { - if (pDM_FatTable->AuxAnt_Sum_cck[MacId] > 65435) - return; - - pDM_FatTable->AuxAnt_Sum_cck[MacId] += (u2Byte)utility; - pDM_FatTable->AuxAnt_Cnt_cck[MacId]++; - } - - } else - #endif - { /*ofdm rate*/ - - if (antsel_tr_mux == ANT1_2G) { - if (pDM_FatTable->MainAnt_Sum[MacId] > 65435) - return; - - pDM_FatTable->MainAnt_Sum[MacId] += (u2Byte)utility; - pDM_FatTable->MainAnt_Cnt[MacId]++; - } else { - if (pDM_FatTable->AuxAnt_Sum[MacId] > 65435) - return; - - pDM_FatTable->AuxAnt_Sum[MacId] += (u2Byte)utility; - pDM_FatTable->AuxAnt_Cnt[MacId]++; - } - } - } - #ifdef ODM_EVM_ENHANCE_ANTDIV - else if(method==EVM_METHOD) - { - if (pDM_Odm->rate_ss == 1) { - - if(antsel_tr_mux == ANT1_2G) - { - pDM_FatTable->MainAntEVM_Sum[MacId]+=((pPhyInfo->RxMIMOEVMdbm[0])<<5); - pDM_FatTable->MainAntEVM_Cnt[MacId]++; - } - else - { - pDM_FatTable->AuxAntEVM_Sum[MacId]+=((pPhyInfo->RxMIMOEVMdbm[0])<<5); - pDM_FatTable->AuxAntEVM_Cnt[MacId]++; - } - - } else { /*>= 2SS*/ - - if (antsel_tr_mux == ANT1_2G) { - - pDM_FatTable->MainAntEVM_2ss_Sum[MacId][0] += (pPhyInfo->RxMIMOEVMdbm[0]<<5); - pDM_FatTable->MainAntEVM_2ss_Sum[MacId][1] += (pPhyInfo->RxMIMOEVMdbm[1]<<5); - pDM_FatTable->MainAntEVM_2ss_Cnt[MacId]++; - - } else { - - pDM_FatTable->AuxAntEVM_2ss_Sum[MacId][0] += (pPhyInfo->RxMIMOEVMdbm[0]<<5); - pDM_FatTable->AuxAntEVM_2ss_Sum[MacId][1] += (pPhyInfo->RxMIMOEVMdbm[1]<<5); - pDM_FatTable->AuxAntEVM_2ss_Cnt[MacId]++; - } - } - } - else if(method==CRC32_METHOD) - { - if (antsel_tr_mux == ANT1_2G) { - pDM_FatTable->MainCRC32_Ok_Cnt += utility; - pDM_FatTable->MainCRC32_Fail_Cnt ++; - } else { - pDM_FatTable->AuxCRC32_Ok_Cnt += utility; - pDM_FatTable->AuxCRC32_Fail_Cnt ++; - } - } - else if(method==TP_METHOD) - { - if (((utility <= ODM_RATEMCS15) && (utility >= ODM_RATEMCS0)) && - (pDM_FatTable->FAT_State_cnt <= pDM_Odm->antdiv_tp_period) - ) { - - if (antsel_tr_mux == ANT1_2G) { - pDM_FatTable->antdiv_tp_main += (phy_rate_table[utility])<<5; - pDM_FatTable->antdiv_tp_main_cnt++; - } else { - pDM_FatTable->antdiv_tp_aux += (phy_rate_table[utility])<<5; - pDM_FatTable->antdiv_tp_aux_cnt++; - } - } - } - #endif -} - - -VOID -ODM_Process_RSSIForAntDiv( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - //IN PODM_PHY_INFO_T pPhyInfo, - //IN PODM_PACKET_INFO_T pPktinfo - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - u1Byte isCCKrate=0,CCKMaxRate=ODM_RATE11M; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte beam_tmp; - u1Byte next_ant; - u1Byte train_pkt_number; - #endif - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPower_Ant0, RxPower_Ant1; - u4Byte RxEVM_Ant0, RxEVM_Ant1; - #else - u1Byte RxPower_Ant0, RxPower_Ant1; - u1Byte RxEVM_Ant0, RxEVM_Ant1; - #endif - u8 rate_ss; - - CCKMaxRate=ODM_RATE11M; - isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE; - - if ((pDM_Odm->SupportICType & ODM_IC_2SS) && (pPktinfo->DataRate > CCKMaxRate)) - { - RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0]; - RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1]; - - RxEVM_Ant0 =pPhyInfo->RxMIMOSignalQuality[0]; - RxEVM_Ant1 =pPhyInfo->RxMIMOSignalQuality[1]; - } - else - RxPower_Ant0=pPhyInfo->RxPWDBAll; - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - #ifdef CONFIG_FAT_PATCH - if ((pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) { - - /*[Beacon]*/ - if (pPktinfo->bPacketBeacon) { - - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - - if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { - - if (pdm_sat_table->ant_num > 1) { - next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); - } - - pdm_sat_table->update_beam_idx++; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; - } - } - /*[Data]*/ - else if (pPktinfo->bPacketToSelf) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); - */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", - pPktinfo->StationID, pdm_sat_table->pkt_counter, pDM_FatTable->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); - - pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; - pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; - - #if 1 - train_pkt_number = pdm_sat_table->beam_train_cnt[pDM_FatTable->RxIdleAnt-1][pdm_sat_table->fast_training_beam_num]; - #else - train_pkt_number = pdm_sat_table->per_beam_training_pkt_num; - #endif - - /*Swich Antenna erery N pkts*/ - if (pdm_sat_table->pkt_counter == train_pkt_number) { - - if (pdm_sat_table->ant_num > 1) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); - next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); - } - - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; - } - } - } - - /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/ - if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) { - - pdm_sat_table->update_beam_idx = 0; - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif - - - } else { - pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(pDM_Odm); - - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - } - } - - } - #else - - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) - { - if ((pDM_Odm->SupportICType & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && - (pPktinfo->bPacketToSelf) && - (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) - ) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); - */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), bPacketToSelf = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pPktinfo->bPacketToSelf, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); - - - pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; - pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; - - /*swich beam every N pkt*/ - if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif - - - } else { - pdm_sat_table->fast_training_beam_num++; - phydm_set_all_ant_same_beam_num(pDM_Odm); - - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - } - } - } - } - } - #endif - else - #endif - if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { - if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && (pPktinfo->bPacketToSelf) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) - { - u1Byte antsel_tr_mux; - antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; - pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0; - pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; - } - } - else //AntDivType != CG_TRX_SMART_ANTDIV - { - if ((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pPktinfo->bPacketToSelf || pDM_FatTable->use_ctrl_frame_antdiv)) { - - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - if (isCCKrate) - pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; - - odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0, RSSI_METHOD, isCCKrate); - - } else { - - odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0, RSSI_METHOD, isCCKrate); - - #ifdef ODM_EVM_ENHANCE_ANTDIV - if (pDM_Odm->SupportICType == ODM_RTL8192E|ODM_RTL8197F) { - if (!isCCKrate) { - odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxEVM_Ant0, EVM_METHOD, isCCKrate); - odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, pPktinfo->DataRate, TP_METHOD, isCCKrate); - } - } - #endif - } - } - } - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); -} - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -ODM_SetTxAntByTxInfo( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId - - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - return; - - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - return; - - - if (pDM_Odm->SupportICType == ODM_RTL8723B) { -#if (RTL8723B_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ -#endif - } else if (pDM_Odm->SupportICType == ODM_RTL8821) { -#if (RTL8821A_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ -#endif - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); - SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); - SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ -#endif - } -} -#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) - -VOID -ODM_SetTxAntByTxInfo( - struct rtl8192cd_priv *priv, - struct tx_desc *pdesc, - unsigned short aid -) -{ - PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); - pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; - u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; - - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - return; - - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - return; - - if (SupportICType == ODM_RTL8881A) { - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ - pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - } else if (SupportICType == ODM_RTL8192E) { - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ - pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - } else if (SupportICType == ODM_RTL8188E) { - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ - pdesc->Dword2 &= set_desc(~BIT(24)); - pdesc->Dword2 &= set_desc(~BIT(25)); - pdesc->Dword7 &= set_desc(~BIT(29)); - - pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_a[aid]<<24); - pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_b[aid]<<25); - pdesc->Dword7 |= set_desc(pDM_FatTable->antsel_c[aid]<<29); - - - } else if (SupportICType == ODM_RTL8812) { - /*[path-A]*/ - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ - - pdesc->Dword6 &= set_desc(~BIT(16)); - pdesc->Dword6 &= set_desc(~BIT(17)); - pdesc->Dword6 &= set_desc(~BIT(18)); - - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18); - - } -} - - -#if 1 /*def CONFIG_WLAN_HAL*/ -VOID -ODM_SetTxAntByTxInfo_HAL( - struct rtl8192cd_priv *priv, - PVOID pdesc_data, - u2Byte aid -) -{ - PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); - pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; - u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; - PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; - - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - return; - - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - return; - - if (SupportICType == ODM_RTL8881A || SupportICType == ODM_RTL8192E || SupportICType == ODM_RTL8814A) { - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_HAL******\n",__FUNCTION__,__LINE__);*/ - pdescdata->antSel = 1; - pdescdata->antSel_A = pDM_FatTable->antsel_a[aid]; - } -} -#endif /*#ifdef CONFIG_WLAN_HAL*/ - -#endif - - -VOID -ODM_AntDiv_Config( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE (pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); - /* - if(pDM_Odm->SupportICType==ODM_RTL8723B) - { - if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON)) - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - */ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - - pDM_Odm->AntDivType = S0S1_TRX_HW_ANTDIV; - /**/ - } -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); - - if(pDM_Odm->SupportICType==ODM_RTL8723B) - { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - - - } - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); - - //2 [ NOT_SUPPORT_ANTDIV ] - #if(defined(CONFIG_NOT_SUPPORT_ANTDIV)) - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); - - //2 [ 2G&5G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n")); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G); - - if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY)||defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - - //2 [ 5G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); - panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G); - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - - //2 [ 2G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_2G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G); - if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - #endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) ? 1 : 0))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", pDM_Odm->DM_FatTable.b_fix_tx_ant)); - -} - - -VOID -ODM_AntDivTimers( - IN PVOID pDM_VOID, - IN u1Byte state - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(state==INIT_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_InitializeTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer), - (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "phydm_SwAntennaSwitchTimer"); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, - (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_InitializeTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, - (RT_TIMER_CALL_BACK)odm_EVM_FastAntTrainingCallback, NULL, "EVM_FastAntTrainingTimer"); - #endif - } - else if(state==CANCEL_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_CancelTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_CancelTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); - #endif - } - else if(state==RELEASE_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_ReleaseTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); - #endif - } - -} - -VOID -phydm_antdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - /*pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;*/ - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - if (dm_value[0] == 1) { /*fixed or auto antenna*/ - - if (dm_value[1] == 0) { - pDM_Odm->antdiv_select = 0; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Auto\n")); - } else if (dm_value[1] == 1) { - pDM_Odm->antdiv_select = 1; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix MAin\n")); - } else if (dm_value[1] == 2) { - pDM_Odm->antdiv_select = 2; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix Aux\n")); - } - } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/ - - pDM_Odm->antdiv_period = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv_period = ((%d))\n", pDM_Odm->antdiv_period)); - } -} - -#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ - -VOID -ODM_AntDivReset( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SWAntDiv_Reset(pDM_Odm); - #endif - } - -} - -VOID -odm_AntennaDiversityInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(pDM_Odm->mp_mode == TRUE) - return; - - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDiv_Config(pDM_Odm); - ODM_AntDivInit(pDM_Odm); - #endif -} - -VOID -odm_AntennaDiversity( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(pDM_Odm->mp_mode == TRUE) - return; - - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDiv(pDM_Odm); - #endif -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +extern u2Byte phy_rate_table[28]; + +//====================================================== +// when antenna test utility is on or some testing need to disable antenna diversity +// call this function to disable all ODM related mechanisms which will switch antenna. +//====================================================== +VOID +ODM_StopAntennaSwitchDm( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + // disable ODM antenna diversity + pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n")); +} + +VOID +phydm_enable_antenna_diversity( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); + odm_AntennaDiversityInit(pDM_Odm); +} + +VOID +ODM_SetAntConfig( + IN PVOID pDM_VOID, + IN u1Byte antSetting // 0=A, 1=B, 2=C, .... + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + if (antSetting == 0) /* ant A*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else if (antSetting == 1) + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (antSetting == 0) /* ant A*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0000); + else if (antSetting == 1) + ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0280); + } +} + +//====================================================== + + +VOID +ODM_SwAntDivRestAfterLink( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte i; + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->RSSI_Trying = 0; + pDM_SWAT_Table->Double_chk_flag= 0; + + pDM_FatTable->RxIdleAnt=MAIN_ANT; + + for (i=0; iMainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + + } +} + + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +VOID +odm_AntDiv_on_off( + IN PVOID pDM_VOID , + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_FatTable->AntDiv_OnOff != swch) + { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + return; + + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); + ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); + + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + if (pDM_Odm->SupportICType == ODM_RTL8812) { + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable + ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable + } else { + ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable + + if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable + } + } + } + } + pDM_FatTable->AntDiv_OnOff =swch; + +} + +VOID +phydm_FastTraining_enable( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte enable; + + if (swch == FAT_ON) + enable=1; + else + enable=0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast Ant Training_en = ((%d))\n", enable)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); /*enable fast training*/ + /**/ + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); /*enable fast training (path-A)*/ + /*ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable);*/ /*enable fast training (path-B)*/ + } else if (pDM_Odm->SupportICType == ODM_RTL8821) { + ODM_SetBBReg(pDM_Odm, 0x900 , BIT19, enable); /*enable fast training */ + /**/ + } +} + +phydm_keep_RxAckAnt_By_TxAnt_time( + IN PVOID pDM_VOID, + IN u4Byte time + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ + if (pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) { + + ODM_SetBBReg(pDM_Odm, 0xE20, BIT23|BIT22|BIT21|BIT20, time); + /**/ + } else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) { + + ODM_SetBBReg(pDM_Odm, 0x818, BIT23|BIT22|BIT21|BIT20, time); + /**/ + } +} + +VOID +odm_Tx_By_TxDesc_or_Reg( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte enable; + + if (pDM_FatTable->b_fix_tx_ant == NO_FIX_TX_ANT) + enable = (swch == TX_BY_DESC) ? 1 : 0; + else + enable = 0;/*Force TX by Reg*/ + + if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) + { + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable); + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC":"REG")); + } +} + +VOID +ODM_UpdateRxIdleAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte DefaultAnt, OptionalAnt, value32, Default_tx_Ant; + + if(pDM_FatTable->RxIdleAnt != Ant) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + if(!(pDM_Odm->SupportICType & ODM_RTL8723B)) + pDM_FatTable->RxIdleAnt = Ant; + + if(Ant == MAIN_ANT) + { + DefaultAnt = ANT1_2G; + OptionalAnt = ANT2_2G; + } + else + { + DefaultAnt = ANT2_2G; + OptionalAnt = ANT1_2G; + } + + if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) + Default_tx_Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; + else + Default_tx_Ant = DefaultAnt; + + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + if(pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX + } + #if (RTL8723B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723B) { + + value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF); + + if(value32 !=0x280) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt); + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); + } + #endif + else { /*8188E & 8188F*/ + + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + #if (RTL8723D_SUPPORT == 1) + phydm_set_tx_ant_pwr_8723d(pDM_Odm, Ant); + #endif + } + #if (RTL8188F_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + phydm_update_rx_idle_antenna_8188F(pDM_Odm, DefaultAnt); + /**/ + } + #endif + + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, Default_tx_Ant); /*Default TX*/ + } + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + u2Byte value16 = ODM_Read2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2); + // + // 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt + // incorrect 0xc08 bit0-15 .We still not know why it is changed. + // + value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); + value16 |= ((u2Byte)DefaultAnt <<3); + value16 |= ((u2Byte)OptionalAnt <<6); + value16 |= ((u2Byte)DefaultAnt <<9); + ODM_Write2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2, value16); + /* + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT21|BIT20|BIT19, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX + */ + } + + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, Default_tx_Ant); /*PathA Resp Tx*/ + /**/ + } + else + { + ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, Default_tx_Ant); /*PathA Resp Tx*/ + /**/ + } + + } + else// pDM_FatTable->RxIdleAnt == Ant + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + pDM_FatTable->RxIdleAnt = Ant; + } +} + +VOID +odm_UpdateTxAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte MacId + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte TxAnt; + + if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) + Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; + + if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + { + TxAnt=Ant; + } + else + { + if(Ant == MAIN_ANT) + TxAnt = ANT1_2G; + else + TxAnt = ANT2_2G; + } + + pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0; + pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1; + pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId, (Ant == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); + +} + +#ifdef BEAMFORMING_SUPPORT +#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +odm_BDC_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n")); + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Mode=BDC_MODE_NULL; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDCcoexType_wBfer=0; + pDM_Odm->bdc_holdstate=0xff; + + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008); + ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0); + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008 + ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000 + } + +} + + +VOID +odm_CSI_on_off( + IN PVOID pDM_VOID, + IN u1Byte CSI_en + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(CSI_en==CSI_ON) + { + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1 + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1 + } + + } + else if(CSI_en==CSI_OFF) + { + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0 + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0 + } + } +} + +VOID +odm_BDCcoexType_withBferClient( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u1Byte BDCcoexType_wBfer; + + if(swch==DIVON_CSIOFF) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n")); + BDCcoexType_wBfer=1; + + if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + odm_CSI_on_off(pDM_Odm,CSI_OFF); + pDM_BdcTable->BDCcoexType_wBfer=1; + } + } + else if(swch==DIVOFF_CSION) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); + BDCcoexType_wBfer=2; + + if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_CSI_on_off(pDM_Odm,CSI_ON); + pDM_BdcTable->BDCcoexType_wBfer=2; + } + } +} + +VOID +odm_BF_AntDiv_ModeArbitration( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u1Byte current_BDC_Mode; + + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); + + //2 Mode 1 + if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0)) + { + current_BDC_Mode=BDC_MODE_1; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_1; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + pDM_BdcTable->BDC_RxIdleUpdate_counter=1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n")); + } + //2 Mode 2 + else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0)) + { + current_BDC_Mode=BDC_MODE_2; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_2; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Try_flag=0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n")); + } + //2 Mode 3 + else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0)) + { + current_BDC_Mode=BDC_MODE_3; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_3; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_RxIdleUpdate_counter=1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n")); + } + //2 Mode 4 + else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0)) + { + current_BDC_Mode=BDC_MODE_4; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_4; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n")); + } + #endif + +} + +VOID +odm_DivTrainState_setting( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n")); + pDM_BdcTable->BDC_Try_counter =2; + pDM_BdcTable->BDC_Try_flag=1; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); +} + +VOID +odm_BDCcoex_BFeeRxDiv_Arbitration( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + BOOLEAN StopBF_flag; + u1Byte BDC_active_Mode; + + + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar )); + + //2 [ MIB control ] + if (pDM_Odm->bdc_holdstate==2) + { + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n")); + return; + } + else if (pDM_Odm->bdc_holdstate==1) + { + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); + return; + } + + //------------------------------------------------------------ + + + + //2 Mode 2 & 3 + if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer)); + + // All Client have Bfer-Cap------------------------------- + if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); + } + // + if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + return; + } + + //Select active mode-------------------------------------- + if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2 + { + if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n")); + pDM_BdcTable->BDC_active_Mode=1; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); + pDM_BdcTable->BDC_active_Mode=2; + } + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + return; + } + else // num_BfTar > 0 + { + if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); + pDM_BdcTable->BDC_active_Mode=3; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else // Selsect_4 + { + BDC_active_Mode=4; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); + + if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode) + { + pDM_BdcTable->BDC_active_Mode=4; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n")); + return; + } + } + } + +#if 1 + if (pDM_Odm->bdc_holdstate==0xff) + { + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); + return; + } +#endif + + // Does Client number changed ? ------------------------------- + if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client) + { + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n")); + } + pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client; + + if( pDM_BdcTable->BDC_Try_flag==0) + { + //2 DIV_TRAIN_STATE (Mode 2-0) + if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE) + { + odm_DivTrainState_setting( pDM_Odm); + } + //2 BFer_TRAIN_STATE (Mode 2-1) + else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n")); + + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + pDM_BdcTable->BDC_Try_counter=2; + pDM_BdcTable->BDC_Try_flag=1; + pDM_BdcTable->BDC_state=BDC_DECISION_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n")); + //} + } + //2 DECISION_STATE (Mode 2-2) + else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n")); + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE) + StopBF_flag=TRUE; + else + StopBF_flag=FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag)); + + if(StopBF_flag==TRUE) //DIV_en + { + pDM_BdcTable->BDC_Hold_counter=10; //20 + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); + } + else //BF_en + { + pDM_BdcTable->BDC_Hold_counter=10; //20 + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n")); + } + //} + } + //2 BF-HOLD_STATE (Mode 2-3) + else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); + + if(pDM_BdcTable->BDC_Hold_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + odm_DivTrainState_setting( pDM_Odm); + } + else + { + pDM_BdcTable->BDC_Hold_counter--; + + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n")); + //} + } + + } + //2 DIV-HOLD_STATE (Mode 2-4) + else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); + + if(pDM_BdcTable->BDC_Hold_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + odm_DivTrainState_setting( pDM_Odm); + } + else + { + pDM_BdcTable->BDC_Hold_counter--; + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); + } + + } + + } + else if( pDM_BdcTable->BDC_Try_flag==1) + { + //2 Set Training Counter + if(pDM_BdcTable->BDC_Try_counter >1) + { + pDM_BdcTable->BDC_Try_counter--; + if(pDM_BdcTable->BDC_Try_counter ==1) + pDM_BdcTable->BDC_Try_flag=0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); + //return ; + } + + } + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); + + #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + + + + + +} + +#endif +#endif //#ifdef BEAMFORMING_SUPPORT + +#ifdef ODM_EVM_ENHANCE_ANTDIV +VOID +phydm_evm_sw_antdiv_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + /*EVM enhance AntDiv method init----------------------------------------------------------------------*/ + pDM_FatTable->EVM_method_enable = 0; + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + pDM_FatTable->FAT_State_cnt = 0; + pDM_FatTable->pre_antdiv_rssi = 0; + + pDM_Odm->antdiv_intvl = 30; + pDM_Odm->antdiv_train_num = 2; + ODM_SetBBReg(pDM_Odm, 0x910, 0x3f, 0xf); + pDM_Odm->antdiv_evm_en = 1; + /*pDM_Odm->antdiv_period=1;*/ + pDM_Odm->evm_antdiv_period = 3; + pDM_Odm->stop_antdiv_rssi_th = 3; + pDM_Odm->stop_antdiv_tp_th = 80; + pDM_Odm->antdiv_tp_period = 3; + pDM_Odm->stop_antdiv_tp_diff_th = 5; +} + + +VOID +odm_EVM_FastAnt_Reset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + pDM_FatTable->EVM_method_enable=0; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + pDM_FatTable->FAT_State_cnt = 0; + pDM_Odm->antdiv_period=0; + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0); +} + + +VOID +odm_EVM_Enhance_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Main_RSSI, Aux_RSSI ; + u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1; + u4Byte main_evm, aux_evm,Diff_RSSI=0,diff_EVM=0; + u4Byte main_2ss_evm[2], aux_2ss_evm[2]; + u4Byte main_1ss_evm, aux_1ss_evm; + u4Byte main_2ss_evm_sum, aux_2ss_evm_sum; + u1Byte score_EVM=0,score_CRC=0; + u1Byte rssi_larger_ant = 0; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte value32, i; + BOOLEAN Main_above1=FALSE,Aux_above1=FALSE; + BOOLEAN Force_antenna=FALSE; + PSTA_INFO_T pEntry; + u32 antdiv_tp_main_avg, antdiv_tp_aux_avg; + u8 curr_rssi, rssi_diff; + u32 tp_diff; + u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0; + u8 target_ant_evm_1ss, target_ant_evm_2ss; + u8 decision_evm_ss; + u8 next_ant; + + pDM_FatTable->TargetAnt_enhance=0xFF; + + + if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) + { + if(pDM_Odm->number_active_client == 1) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n")); + i = pDM_Odm->OneEntry_MACID; + pEntry = pDM_Odm->pODM_StaInfo[i]; + + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + + if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF)) + { + Diff_RSSI=FORCE_RSSI_DIFF; + } + else if(Main_RSSI!=0 && Aux_RSSI !=0) + { + Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI); + } + + if (Main_RSSI >= Aux_RSSI) + rssi_larger_ant = MAIN_ANT; + else + rssi_larger_ant = AUX_ANT; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d ))\n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d ))\n", pDM_FatTable->AuxAnt_Cnt[i], Aux_RSSI)); + + if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) ) + //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1) + ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && ")); + + if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) )) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_L, State_cnt =((%d))\n", pDM_FatTable->FAT_State_cnt)); + + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)==============================================================*/ + if (pDM_FatTable->FAT_State_cnt < ((pDM_Odm->antdiv_train_num)<<1)) { + + if (pDM_FatTable->FAT_State_cnt == 0) { + /*Reset EVM 1SS Method */ + pDM_FatTable->MainAntEVM_Sum[i] = 0; + pDM_FatTable->AuxAntEVM_Sum[i] = 0; + pDM_FatTable->MainAntEVM_Cnt[i] = 0; + pDM_FatTable->AuxAntEVM_Cnt[i] = 0; + /*Reset EVM 2SS Method */ + pDM_FatTable->MainAntEVM_2ss_Sum[i][0] =0; + pDM_FatTable->MainAntEVM_2ss_Sum[i][1] =0; + pDM_FatTable->AuxAntEVM_2ss_Sum[i][0] = 0; + pDM_FatTable->AuxAntEVM_2ss_Sum[i][1] = 0; + pDM_FatTable->MainAntEVM_2ss_Cnt[i] = 0; + pDM_FatTable->AuxAntEVM_2ss_Cnt[i] = 0; + #if 0 + /*Reset TP Method */ + pDM_FatTable->antdiv_tp_main = 0; + pDM_FatTable->antdiv_tp_aux = 0; + pDM_FatTable->antdiv_tp_main_cnt = 0; + pDM_FatTable->antdiv_tp_aux_cnt = 0; + #endif + /*Reset CRC Method */ + pDM_FatTable->MainCRC32_Ok_Cnt = 0; + pDM_FatTable->MainCRC32_Fail_Cnt = 0; + pDM_FatTable->AuxCRC32_Ok_Cnt = 0; + pDM_FatTable->AuxCRC32_Fail_Cnt = 0; + + #if SKIP_EVM_ANTDIV_TRAINING_PATCH + if ((*pDM_Odm->pBandWidth == ODM_BW20M) && (pEntry->rf_mimo_mode == MIMO_2T2R)) { + /*1. Skip training: RSSI*/ + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt)); + curr_rssi = (u8)((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? Main_RSSI : Aux_RSSI); + rssi_diff = (curr_rssi > pDM_FatTable->pre_antdiv_rssi) ? (curr_rssi - pDM_FatTable->pre_antdiv_rssi) : (pDM_FatTable->pre_antdiv_rssi - curr_rssi); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, pDM_FatTable->pre_antdiv_rssi)); + + pDM_FatTable->pre_antdiv_rssi = curr_rssi; + if ((rssi_diff < (pDM_Odm->stop_antdiv_rssi_th)) && (curr_rssi != 0)) { + rssi_return = 1; + } + + /*2. Skip training: TP Diff*/ + tp_diff = (pDM_Odm->rx_tp > pDM_FatTable->pre_antdiv_tp) ? (pDM_Odm->rx_tp - pDM_FatTable->pre_antdiv_tp) : (pDM_FatTable->pre_antdiv_tp - pDM_Odm->rx_tp); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", pDM_Odm->rx_tp, pDM_FatTable->pre_antdiv_tp)); + pDM_FatTable->pre_antdiv_tp = pDM_Odm->rx_tp; + if ((tp_diff < (u32)(pDM_Odm->stop_antdiv_tp_diff_th) && (pDM_Odm->rx_tp != 0))) { + tp_diff_return = 1; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[3] tp_return, curr_rx_tp=((%d))\n", pDM_Odm->rx_tp)); + /*3. Skip training: TP*/ + if (pDM_Odm->rx_tp >= (u32)(pDM_Odm->stop_antdiv_tp_th)) { + tp_return = 1; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return)); + /*4. Joint Return Decision*/ + if (tp_return) { + if (tp_diff_return || rssi_diff) { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Return EVM SW AntDiv\n")); + return; + } + } + } + #endif + + pDM_FatTable->EVM_method_enable = 1; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pDM_Odm->antdiv_period = pDM_Odm->evm_antdiv_period; + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); /*RCR accepts CRC32-Error packets*/ + } + + pDM_FatTable->FAT_State_cnt++; + + next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); + ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms + } + /*Decision state: 4==============================================================*/ + else { + + pDM_FatTable->FAT_State_cnt = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Decisoin state ] \n")); + + //3 [CRC32 statistic] + #if 0 + if ((pDM_FatTable->MainCRC32_Ok_Cnt > ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 40) && (rssi_larger_ant == MAIN_ANT))) { + pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; + Force_antenna=TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); + } else if ((pDM_FatTable->AuxCRC32_Ok_Cnt > ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 40) && (rssi_larger_ant == AUX_ANT))) { + pDM_FatTable->TargetAnt_CRC32=AUX_ANT; + Force_antenna=TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); + } + else + #endif + { + if(pDM_FatTable->MainCRC32_Fail_Cnt<=5) + pDM_FatTable->MainCRC32_Fail_Cnt=5; + + if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5) + pDM_FatTable->AuxCRC32_Fail_Cnt=5; + + if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt ) + Main_above1=TRUE; + + if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt ) + Aux_above1=TRUE; + + if(Main_above1==TRUE && Aux_above1==FALSE) + { + Force_antenna=TRUE; + pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; + } + else if(Main_above1==FALSE && Aux_above1==TRUE) + { + Force_antenna=TRUE; + pDM_FatTable->TargetAnt_CRC32=AUX_ANT; + } + else if(Main_above1==TRUE && Aux_above1==TRUE) + { + Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt; + Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt; + pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); + + if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) + { + if(Main_CRC_utility>=Aux_CRC_utility) + utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility; + else + utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility; + } + } + else if(Main_above1==FALSE && Aux_above1==FALSE) + { + if(pDM_FatTable->MainCRC32_Ok_Cnt==0) + pDM_FatTable->MainCRC32_Ok_Cnt=1; + if(pDM_FatTable->AuxCRC32_Ok_Cnt==0) + pDM_FatTable->AuxCRC32_Ok_Cnt=1; + + Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt; + Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt; + pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); + + if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) + { + if(Main_CRC_utility>=Aux_CRC_utility) + utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility); + else + utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility); + } + } + } + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets. + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt, Main_CRC_utility)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt, Aux_CRC_utility)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***1.TargetAnt_CRC32 = ((%s))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + //3 [EVM statistic] + /*1SS EVM*/ + main_1ss_evm = (pDM_FatTable->MainAntEVM_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_Sum[i] / pDM_FatTable->MainAntEVM_Cnt[i]) : 0; + aux_1ss_evm = (pDM_FatTable->AuxAntEVM_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_Sum[i] / pDM_FatTable->AuxAntEVM_Cnt[i]) : 0; + target_ant_evm_1ss = (main_1ss_evm==aux_1ss_evm) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main1ss_EVM= (( %d )) \n", pDM_FatTable->MainAntEVM_Cnt[i], main_1ss_evm)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_1ss_EVM = (( %d )) \n", pDM_FatTable->AuxAntEVM_Cnt[i], aux_1ss_evm)); + + /*2SS EVM*/ + main_2ss_evm[0] = (pDM_FatTable->MainAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_2ss_Sum[i][0] / pDM_FatTable->MainAntEVM_2ss_Cnt[i]) : 0; + main_2ss_evm[1] = (pDM_FatTable->MainAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->MainAntEVM_2ss_Sum[i][1] / pDM_FatTable->MainAntEVM_2ss_Cnt[i]) : 0; + main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; + + aux_2ss_evm[0] = (pDM_FatTable->AuxAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_2ss_Sum[i][0] / pDM_FatTable->AuxAntEVM_2ss_Cnt[i]) : 0; + aux_2ss_evm[1] = (pDM_FatTable->AuxAntEVM_2ss_Cnt[i] != 0) ? (pDM_FatTable->AuxAntEVM_2ss_Sum[i][1] / pDM_FatTable->AuxAntEVM_2ss_Cnt[i]) : 0; + aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; + target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + pDM_FatTable->MainAntEVM_2ss_Cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + pDM_FatTable->AuxAntEVM_2ss_Cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum)); + + if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) + { + decision_evm_ss = 2; + main_evm = main_2ss_evm_sum; + aux_evm = aux_2ss_evm_sum; + pDM_FatTable->TargetAnt_EVM = target_ant_evm_2ss; + } else { + decision_evm_ss = 1; + main_evm = main_1ss_evm; + aux_evm = aux_1ss_evm; + pDM_FatTable->TargetAnt_EVM = target_ant_evm_1ss; + } + + if((main_evm == 0 || aux_evm == 0)) + diff_EVM = 100; + else if(main_evm >= aux_evm) + diff_EVM = main_evm - aux_evm; + else + diff_EVM = aux_evm - main_evm; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (pDM_FatTable->TargetAnt_EVM == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + + //3 [TP statistic] + antdiv_tp_main_avg = (pDM_FatTable->antdiv_tp_main_cnt != 0) ? (pDM_FatTable->antdiv_tp_main / pDM_FatTable->antdiv_tp_main_cnt) : 0; + antdiv_tp_aux_avg = (pDM_FatTable->antdiv_tp_aux_cnt != 0) ? (pDM_FatTable->antdiv_tp_aux / pDM_FatTable->antdiv_tp_aux_cnt) : 0; + pDM_FatTable->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (pDM_FatTable->pre_TargetAnt_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main_TP = ((%d))\n", pDM_FatTable->antdiv_tp_main_cnt, antdiv_tp_main_avg)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_TP = ((%d))\n", pDM_FatTable->antdiv_tp_aux_cnt, antdiv_tp_aux_avg)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***3.TargetAnt_TP = ((%s))\n", (pDM_FatTable->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + + /*Reset TP Method */ + pDM_FatTable->antdiv_tp_main = 0; + pDM_FatTable->antdiv_tp_aux = 0; + pDM_FatTable->antdiv_tp_main_cnt = 0; + pDM_FatTable->antdiv_tp_aux_cnt = 0; + + //2 [ Decision state ] + if (pDM_FatTable->TargetAnt_EVM == pDM_FatTable->TargetAnt_CRC32) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + + if ((utility_ratio < 2 && Force_antenna == FALSE) && diff_EVM <= 30) + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; + else + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; + } + #if 0 + else if ((diff_EVM <= 50 && (utility_ratio > 4 && Force_antenna == FALSE)) || (Force_antenna == TRUE)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; + } + #endif + else if (diff_EVM >= 20) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; + } else if (utility_ratio >= 6 && Force_antenna == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; + } else { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + + if (Force_antenna == TRUE) + score_CRC = 2; + else if (utility_ratio >= 5) /*>2.5*/ + score_CRC = 2; + else if (utility_ratio >= 4) /*>2*/ + score_CRC = 1; + else + score_CRC = 0; + + if (diff_EVM >= 15) + score_EVM = 3; + else if (diff_EVM >= 10) + score_EVM = 2; + else if (diff_EVM >= 5) + score_EVM = 1; + else + score_EVM = 0; + + if (score_CRC > score_EVM) + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; + else if (score_CRC < score_EVM) + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; + else + pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; + } + pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** 4.TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + } + else // RSSI< = Evm_RSSI_TH_Low + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[num_active_client != 1] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } +} + +VOID +odm_EVM_FastAntTrainingCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******AntDiv Callback****** \n")); + odm_HW_AntDiv(pDM_Odm); +} +#endif + +#if (RTL8188E_SUPPORT == 1) + + +VOID +odm_RX_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0001); //antenna mapping table + + pDM_FatTable->enable_ctrl_frame_antdiv = 1; +} + +VOID +odm_TRX_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + //antenna mapping table + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ + + pDM_FatTable->enable_ctrl_frame_antdiv = 1; +} + + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_Smart_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32, i; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); + return; + } + + pDM_FatTable->TrainIdx = 0; + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + + pDM_Odm->fat_comb_a=5; + pDM_Odm->antdiv_intvl = 0x64; // 100ms + + for(i=0; i<6; i++) + { + pDM_FatTable->Bssid[i] = 0; + } + for(i=0; i< (pDM_Odm->fat_comb_a) ; i++) + { + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + pDM_FatTable->antAveRSSI[i] = 0; + } + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match + //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); + //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet + + //Match MAC ADDR + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only + ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); + + //antenna mapping table + if(pDM_Odm->fat_comb_a == 2) + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); + } + } + else + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); + ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111 + } + } + + //Default Ant Setting when no fast training + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX + ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX + + //Enter Traing state + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 + + //SW Control + //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); + //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); + //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); + //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); +} +#endif + +#endif //#if (RTL8188E_SUPPORT == 1) + + +#if (RTL8192E_SUPPORT == 1) +VOID +odm_RX_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); + + //Pin Settings + ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs + + //Mapping table + ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table + + //OFDM Settings + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias + + //CCK Settings + ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 + ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 + ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + #ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(pDM_Odm); + #endif + +} + +VOID +odm_TRX_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); + + //3 --RFE pin setting--------- + //[MAC] + ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8) + ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 + ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8 + //[BB] + ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer + ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1); + ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3) + ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8) + ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer + ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3) + ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8) + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3 + ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8 + //3 ------------------------- + + //Pin Settings + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch + +/* Let it follows PHY_REG for bit9 setting + if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna) + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS + else + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power +*/ + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW + + //Mapping table + ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table + + //OFDM Settings + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias + + //CCK Settings + ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 + ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 + ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + #ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(pDM_Odm); + #endif +} + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_Smart_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); +} +#endif + +#endif //#if (RTL8192E_SUPPORT == 1) + +#if (RTL8197F_SUPPORT == 1) + +VOID +odm_RX_HWAntDiv_Init_97F( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8197F AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); + + //Pin Settings + ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs + + //Mapping table + ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table + + //OFDM Settings + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias + + //CCK Settings + ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 + ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 + ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + #ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(pDM_Odm); + #endif + +} + + +#endif //#if (RTL8197F_SUPPORT == 1) + + +#if (RTL8723D_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8723D( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => AntDivType=[S0S1_HW_TRX_AntDiv]\n")); + + /*BT Coexistence*/ + /*keep antsel_map when GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 1); + /* //Disable hw antsw & fast_train.antsw when GNT_BT=1*/ + ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); + /*//Disable hw antsw & fast_train.antsw when BT TX/RX*/ + ODM_SetBBReg(pDM_Odm, 0xE64 , 0xFFFF0000, 0x000c); + + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); + /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ + /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0);*/ + /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT8, 0);*/ + /*GNT_WL tx*/ + ODM_SetBBReg(pDM_Odm, 0x950 , BIT29, 0); + + + /*Mapping Table*/ + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 3); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); + + /* //Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0]*/ + ODM_SetBBReg(pDM_Odm, 0xCcc, BIT12, 0); + /* //Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable*/ + ODM_SetBBReg(pDM_Odm, 0xCcc , 0x0F, 0x01); + /*//High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable*/ + ODM_SetBBReg(pDM_Odm, 0xCcc , 0xF0, 0x0); + /* //b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ + ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF, 0x06); + /* //High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ + ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF00, 0x00); + + + /*OFDM HW AntDiv Parameters*/ + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); + ODM_SetBBReg(pDM_Odm, 0xC5C , BIT20|BIT19|BIT18, 0x04); + + /*CCK HW AntDiv Parameters*/ + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); + ODM_SetBBReg(pDM_Odm, 0xAA8 , BIT8, 0); + + ODM_SetBBReg(pDM_Odm, 0xA0C , 0x0F, 0xf); + ODM_SetBBReg(pDM_Odm, 0xA14 , 0x1F, 0x8); + ODM_SetBBReg(pDM_Odm, 0xA10 , BIT13, 0x1); + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT8, 0x0); + ODM_SetBBReg(pDM_Odm, 0xB34 , BIT30, 0x1); + + /*disable antenna training */ + ODM_SetBBReg(pDM_Odm, 0xE08 , BIT16, 0); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); + +} + +VOID +phydm_set_tx_ant_pwr_8723d( + IN PVOID pDM_VOID, + IN u1Byte Ant +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + pDM_FatTable->RxIdleAnt = Ant; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); + #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); + #endif + +} +#endif + +#if (RTL8723B_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8723B( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n")); + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + //Output Pin Settings + ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); // + + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) + ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0); + + ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1); + ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1); + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin + + ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out + ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); // + + ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse + + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + + //2 [--For HW Bug Setting] + if(pDM_Odm->AntType == ODM_AUTO_ANT) + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + +} + + + +VOID +odm_S0S1_SWAntDiv_Init_8723B( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n")); + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); + + //Output Pin Settings + //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); + + pDM_FatTable->bBecomeLinked =FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + + //2 [--For HW Bug Setting] + ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg + +} + +VOID +ODM_UpdateRxIdleAnt_8723B( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte DefaultAnt, + IN u4Byte OptionalAnt +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte count=0; + u1Byte u1Temp; + u1Byte H2C_Parameter; + + if ((!pDM_Odm->bLinked) && (pDM_Odm->AntType == ODM_AUTO_ANT)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to no link\n")); + return; + } + +#if 0 + // Send H2C command to FW + // Enable wifi calibration + H2C_Parameter = TRUE; + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); + + // Check if H2C command sucess or not (0x1e6) + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); + while((u1Temp != 0x1) && (count < 100)) + { + ODM_delay_us(10); + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); + count++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: H2C command status = %d, count = %d\n", u1Temp, count)); + + if(u1Temp == 0x1) + { + // Check if BT is doing IQK (0x1e7) + count = 0; + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); + while((!(u1Temp & BIT0)) && (count < 100)) + { + ODM_delay_us(50); + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); + count++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: BT IQK status = %d, count = %d\n", u1Temp, count)); + + if(u1Temp & BIT0) + { + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX + pDM_FatTable->RxIdleAnt = Ant; + + // Set TX AGC by S0/S1 + // Need to consider Linux driver +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); +#endif + + // Set IQC by S0/S1 + ODM_SetIQCbyRFpath(pDM_Odm,DefaultAnt); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Sucess to set RX antenna\n")); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); + + // Send H2C command to FW + // Disable wifi calibration + H2C_Parameter = FALSE; + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); +#else + + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/ + pDM_FatTable->RxIdleAnt = Ant; + + /* Set TX AGC by S0/S1 */ + /* Need to consider Linux driver */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); + #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); + #endif + + /* Set IQC by S0/S1 */ + ODM_SetIQCbyRFpath(pDM_Odm, DefaultAnt); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Success to set RX antenna\n")); + +#endif +} + +BOOLEAN +phydm_IsBtEnable_8723b( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte bt_state; + /*u4Byte reg75;*/ + + /*reg75 = ODM_GetBBReg(pDM_Odm, 0x74 , BIT8);*/ + /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, 0x0);*/ + ODM_SetBBReg(pDM_Odm, 0xa0 , BIT24|BIT25|BIT26, 0x5); + bt_state = ODM_GetBBReg(pDM_Odm, 0xa0 , (BIT3|BIT2|BIT1|BIT0)); + /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, reg75);*/ + + if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) + return TRUE; + else + return FALSE; +} +#endif //#if (RTL8723B_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +VOID +phydm_hl_smart_ant_type1_init_8821a( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte value32; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => AntDivType=[Hong-Lin Smart Ant Type1]\n")); + + /*---------------------------------------- + GPIO 2-3 for Beam control + reg0x66[2]=0 + reg0x44[27:26] = 0 + reg0x44[23:16] //enable_output for P_GPIO[7:0] + reg0x44[15:8] //output_value for P_GPIO[7:0] + reg0x40[1:0] = 0 //GPIO function + ------------------------------------------*/ + + /*GPIO Setting*/ + ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT27|BIT26, 0); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT19|BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, 0);*/ /*output value*/ + ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW Setting*/ + pdm_sat_table->data_codeword_bit_num = 24;/*max=32*/ + pdm_sat_table->beam_patten_num_each_ant = 4; + + #if DEV_BUS_TYPE == RT_SDIO_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ + #elif DEV_BUS_TYPE == RT_USB_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ + #endif + pdm_sat_table->pkt_skip_statistic_en = 0; + + pdm_sat_table->ant_num = 1;/*max=8*/ + pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A; + pdm_sat_table->first_train_ant = MAIN_ANT; + + pdm_sat_table->rfu_codeword_table[0] = 0x0; + pdm_sat_table->rfu_codeword_table[1] = 0x4; + pdm_sat_table->rfu_codeword_table[2] = 0x8; + pdm_sat_table->rfu_codeword_table[3] = 0xc; + + pdm_sat_table->rfu_codeword_table_5g[0] = 0x1; + pdm_sat_table->rfu_codeword_table_5g[1] = 0x2; + pdm_sat_table->rfu_codeword_table_5g[2] = 0x4; + pdm_sat_table->rfu_codeword_table_5g[3] = 0x8; + + pdm_sat_table->fix_beam_pattern_en = 0; + pdm_sat_table->decision_holding_period = 0; + + /*beam training setting*/ + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->per_beam_training_pkt_num = 10; + + /*set default beam*/ + pdm_sat_table->fast_training_beam_num = 0; + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + phydm_set_all_ant_same_beam_num(pDM_Odm); + + pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; + + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskDWord, 0x01000100); + ODM_SetBBReg(pDM_Odm, 0xCA8 , bMaskDWord, 0x01000100); + + /*[BB] FAT Setting*/ + ODM_SetBBReg(pDM_Odm, 0xc08 , BIT18|BIT17|BIT16, pdm_sat_table->ant_num); + ODM_SetBBReg(pDM_Odm, 0xc08 , BIT31, 0); /*increase ant num every FAT period 0:+1, 1+2*/ + ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT2|BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT0, 1); /*FAT_watchdog_en*/ + + value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC Addr*/ + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + +} +#endif + +VOID +odm_TRX_HWAntDiv_Init_8821A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); + + //Output Pin Settings + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + + ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control + ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + + ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); + ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); + + ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //response TX ant by RX ant + ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + +} + +VOID +odm_S0S1_SWAntDiv_Init_8821A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + + //Output Pin Settings + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + + ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control + ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + + ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); + ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); + + ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //response TX ant by RX ant + ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); + + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + pDM_SWAT_Table->CurAntenna = MAIN_ANT; + pDM_SWAT_Table->PreAntenna = MAIN_ANT; + pDM_SWAT_Table->SWAS_NoLink_State = 0; + +} +#endif //#if (RTL8821A_SUPPORT == 1) + +#if (RTL8821C_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8821C( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); + //Output Pin Settings + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + + ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control + ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + + ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); + ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); + + ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //response TX ant by RX ant + ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + +} +#endif //#if (RTL8821C_SUPPORT == 1) + + +#if (RTL8881A_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8881A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); + + //Output Pin Settings + // [SPDT related] + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1); + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0] + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //2 [--For HW Bug Setting] + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug +} + +#endif //#if (RTL8881A_SUPPORT == 1) + + +#if (RTL8812A_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8812A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); + + //3 //3 --RFE pin setting--------- + //[BB] + ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch + ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0); + ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1); + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0] + //3 ------------------------- + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //2 [--For HW Bug Setting] + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug + +} + +#endif //#if (RTL8812A_SUPPORT == 1) + +#if (RTL8188F_SUPPORT == 1) +VOID +odm_S0S1_SWAntDiv_Init_8188F( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + + + /*GPIO Setting*/ + /*ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); */ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT28|BIT27, 0);*/ + ODM_SetMACReg(pDM_Odm, 0x44 , BIT20|BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT12|BIT11, 0);*/ /*output value*/ + /*ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0);*/ /*GPIO function*/ + + pDM_FatTable->bBecomeLinked = FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; +} + +VOID +phydm_update_rx_idle_antenna_8188F( + IN PVOID pDM_VOID, + IN u4Byte default_ant +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte codeword; + + if (default_ant == ANT1_2G) + codeword = 1; /*2'b01*/ + else + codeword = 2;/*2'b10*/ + + ODM_SetMACReg(pDM_Odm, 0x44 , (BIT12|BIT11), codeword); /*GPIO[4:3] output value*/ +} + +#endif + +VOID +odm_HW_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI; + u4Byte Main_RSSI, Aux_RSSI; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte RxIdleAnt = pDM_FatTable->RxIdleAnt, TargetAnt = 7; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PSTA_INFO_T pEntry; + + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u4Byte TH1=500000; + u4Byte TH2=10000000; + u4Byte MA_rx_Temp, degrade_TP_temp, improve_TP_temp; + u1Byte Monitor_RSSI_threshold=30; + + pDM_BdcTable->BF_pass=TRUE; + pDM_BdcTable->DIV_pass=TRUE; + pDM_BdcTable->bAll_DivSta_Idle=TRUE; + pDM_BdcTable->bAll_BFSta_Idle=TRUE; + pDM_BdcTable->num_BfTar=0 ; + pDM_BdcTable->num_DivTar=0; + pDM_BdcTable->num_Client=0; + #endif + #endif + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + pDM_Odm->antdiv_period=0; + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + /*odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);*/ + + //if(pDM_Odm->SupportICType == ODM_RTL8821 ) + //ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable + + //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + //else if(pDM_Odm->SupportICType == ODM_RTL8881A) + // ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable + //#endif + + //else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812) + //ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + + if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412 + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + } + + //2 BDC Init + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_BDC_Init(pDM_Odm); + #endif + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + odm_EVM_FastAnt_Reset(pDM_Odm); + #endif + } + } + + if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } + + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n AntDiv Start =>\n")); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if(pDM_Odm->antdiv_evm_en==1) + { + odm_EVM_Enhance_AntDiv(pDM_Odm); + if(pDM_FatTable->FAT_State_cnt != 0) + return; + } + else + { + odm_EVM_FastAnt_Reset(pDM_Odm); + } + #endif + + //2 BDC Mode Arbitration + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_Odm->antdiv_evm_en == 0 ||pDM_FatTable->EVM_method_enable==0) + { + odm_BF_AntDiv_ModeArbitration(pDM_Odm); + } + #endif + #endif + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Antenna + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%d] \n",pDM_Odm->SupportICType)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI)); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2, + // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0))); + + LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; + //2 Select MaxRSSI for DIG + if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) + AntDivMaxRSSI = LocalMaxRSSI; + if(LocalMaxRSSI > MaxRSSI) + MaxRSSI = LocalMaxRSSI; + + //2 Select RX Idle Antenna + if ( (LocalMaxRSSI != 0) && (LocalMaxRSSI < MinMaxRSSI) ) + { + RxIdleAnt = TargetAnt; + MinMaxRSSI = LocalMaxRSSI; + } + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if(pDM_Odm->antdiv_evm_en==1) + { + if(pDM_FatTable->TargetAnt_enhance!=0xFF) + { + TargetAnt=pDM_FatTable->TargetAnt_enhance; + RxIdleAnt = pDM_FatTable->TargetAnt_enhance; + } + } + #endif + + //2 Select TX Antenna + if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) + { + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->w_BFee_Client[i]==0) + #endif + #endif + { + odm_UpdateTxAnt(pDM_Odm, TargetAnt, i); + } + } + + //------------------------------------------------------------ + + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + pDM_BdcTable->num_Client++; + + if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + //2 Byte Counter + + MA_rx_Temp= (pEntry->rx_byte_cnt_LowMAW)<<3 ; // RX TP ( bit /sec) + + if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + pDM_BdcTable->MA_rx_TP_DIV[i]= MA_rx_Temp ; + } + else + { + pDM_BdcTable->MA_rx_TP[i] =MA_rx_Temp ; + } + + if( (MA_rx_Temp < TH2) && (MA_rx_Temp > TH1) && (LocalMaxRSSI<=Monitor_RSSI_threshold)) + { + if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target + { + pDM_BdcTable->num_BfTar++; + + if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) + { + improve_TP_temp = (pDM_BdcTable->MA_rx_TP_DIV[i] * 9)>>3 ; //* 1.125 + pDM_BdcTable->BF_pass = (pDM_BdcTable->MA_rx_TP[i] > improve_TP_temp)?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp , MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],improve_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->BF_pass )); + } + } + else// DIV_Target + { + pDM_BdcTable->num_DivTar++; + + if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) + { + degrade_TP_temp=(pDM_BdcTable->MA_rx_TP_DIV[i]*5)>>3;//* 0.625 + pDM_BdcTable->DIV_pass = (pDM_BdcTable->MA_rx_TP[i] >degrade_TP_temp)?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp , MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],degrade_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->DIV_pass )); + } + } + } + + if(MA_rx_Temp > TH1) + { + if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target + { + pDM_BdcTable->bAll_BFSta_Idle=FALSE; + } + else// DIV_Target + { + pDM_BdcTable->bAll_DivSta_Idle=FALSE; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap , BFmerCap} = { %d , %d } \n" ,i, pDM_BdcTable->w_BFee_Client[i] , pDM_BdcTable->w_BFer_Client[i])); + + if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP_DIV[i] )); + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP[i] )); + } + + } + #endif + #endif + + } + + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->BDC_Try_flag==0) + #endif + #endif + { + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + } + + + + //2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP ) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** RxIdleAnt = (( %s ))\n\n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->BDC_Mode==BDC_MODE_1 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** BDC_RxIdleUpdate_counter = (( %d ))\n", pDM_BdcTable->BDC_RxIdleUpdate_counter)); + + if(pDM_BdcTable->BDC_RxIdleUpdate_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!! \n")); + pDM_BdcTable->BDC_RxIdleUpdate_counter=30; + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + } + else + { + pDM_BdcTable->BDC_RxIdleUpdate_counter--; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); + } + } + else + #endif + #endif + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + #else + + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + + #endif//#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + + + //2 BDC Main Algorithm + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_Odm->antdiv_evm_en ==0 ||pDM_FatTable->EVM_method_enable==0) + { + odm_BDCcoex_BFeeRxDiv_Arbitration(pDM_Odm); + } + #endif + #endif + + if(AntDivMaxRSSI == 0) + pDM_DigTable->AntDiv_RSSI_max = pDM_Odm->RSSI_Min; + else + pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; + + pDM_DigTable->RSSI_max = MaxRSSI; +} + + + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +VOID +odm_S0S1_SWAntDiv_Reset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + pDM_FatTable->bBecomeLinked = FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SWAntDiv_Reset(): pDM_FatTable->bBecomeLinked = %d\n", pDM_FatTable->bBecomeLinked)); +} + +VOID +odm_S0S1_SwAntDiv( + IN PVOID pDM_VOID, + IN u1Byte Step + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte i, MinMaxRSSI = 0xFF, LocalMaxRSSI, LocalMinRSSI; + u4Byte Main_RSSI, Aux_RSSI; + u1Byte HighTraffic_TrainTime_U = 0x32, HighTraffic_TrainTime_L = 0, Train_time_temp; + u1Byte LowTraffic_TrainTime_U = 200, LowTraffic_TrainTime_L = 0; + u1Byte RxIdleAnt = pDM_SWAT_Table->PreAntenna, TargetAnt, nextAnt = 0; + PSTA_INFO_T pEntry = NULL; + u4Byte value32; + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + ODM_SetBBReg(pDM_Odm, 0x948 , (BIT9|BIT8|BIT7|BIT6), 0x0); + } + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3); + + #if (RTL8723B_SUPPORT == 1) + if (value32 == 0x0) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, MAIN_ANT, ANT1_2G, ANT2_2G); + else if (value32 == 0x1) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, AUX_ANT, ANT2_2G, ANT1_2G); + #endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n",(value32 == 0x0?"MAIN":"AUX") )); + } + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n", + __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag)); + + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != pDM_SWAT_Table->try_flag ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag] Need to Reset After Link\n")); + ODM_SwAntDivRestAfterLink(pDM_Odm); + } + + if (pDM_SWAT_Table->try_flag == SWAW_STEP_INIT) { + + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + pDM_SWAT_Table->Train_time_flag=0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); + return; + + } else { + + //1 Normal State (Begin Trying) + if (pDM_SWAT_Table->try_flag == SWAW_STEP_PEEK) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), TrafficLoad = (%d))\n", pDM_Odm->curTxOkCnt, pDM_Odm->curRxOkCnt, pDM_Odm->TrafficLoad)); + + if (pDM_Odm->TrafficLoad == TRAFFIC_HIGH) + { + Train_time_temp = pDM_SWAT_Table->Train_time ; + + if(pDM_SWAT_Table->Train_time_flag==3) + { + HighTraffic_TrainTime_L=0xa; + + if(Train_time_temp<=16) + Train_time_temp=HighTraffic_TrainTime_L; + else + Train_time_temp-=16; + + } + else if(pDM_SWAT_Table->Train_time_flag==2) + { + Train_time_temp-=8; + HighTraffic_TrainTime_L=0xf; + } + else if(pDM_SWAT_Table->Train_time_flag==1) + { + Train_time_temp-=4; + HighTraffic_TrainTime_L=0x1e; + } + else if(pDM_SWAT_Table->Train_time_flag==0) + { + Train_time_temp+=8; + HighTraffic_TrainTime_L=0x28; + } + + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp)); + + //-- + if(Train_time_temp > HighTraffic_TrainTime_U) + Train_time_temp=HighTraffic_TrainTime_U; + + else if(Train_time_temp < HighTraffic_TrainTime_L) + Train_time_temp=HighTraffic_TrainTime_L; + + pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)), Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + + } else if ((pDM_Odm->TrafficLoad == TRAFFIC_MID) || (pDM_Odm->TrafficLoad == TRAFFIC_LOW)) { + + Train_time_temp=pDM_SWAT_Table->Train_time ; + + if(pDM_SWAT_Table->Train_time_flag==3) + { + LowTraffic_TrainTime_L=10; + if(Train_time_temp<50) + Train_time_temp=LowTraffic_TrainTime_L; + else + Train_time_temp-=50; + } + else if(pDM_SWAT_Table->Train_time_flag==2) + { + Train_time_temp-=30; + LowTraffic_TrainTime_L=36; + } + else if(pDM_SWAT_Table->Train_time_flag==1) + { + Train_time_temp-=10; + LowTraffic_TrainTime_L=40; + } else { + + Train_time_temp += 10; + LowTraffic_TrainTime_L = 50; + } + + //-- + if(Train_time_temp >= LowTraffic_TrainTime_U) + Train_time_temp=LowTraffic_TrainTime_U; + + else if(Train_time_temp <= LowTraffic_TrainTime_L) + Train_time_temp=LowTraffic_TrainTime_L; + + pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)) , Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + + } else { + pDM_SWAT_Table->Train_time = 0xc8; /*200ms*/ + + } + + //----------------- + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current MinMaxRSSI is ((%d))\n", pDM_FatTable->MinMaxRSSI)); + + //---reset index--- + if (pDM_SWAT_Table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + + pDM_FatTable->MinMaxRSSI = 0; + pDM_SWAT_Table->reset_idx = 0; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", pDM_SWAT_Table->reset_idx)); + + pDM_SWAT_Table->reset_idx++; + + //---double check flag--- + if ((pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) && (pDM_SWAT_Table->Double_chk_flag == 0)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" MinMaxRSSI is ((%d)), and > %d\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + pDM_SWAT_Table->Double_chk_flag =1; + pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; + pDM_SWAT_Table->RSSI_Trying = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current Ant for (( %d )) ms again\n", pDM_SWAT_Table->Train_time)); + ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt); + ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ + return; + } + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + + pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; + + if(pDM_SWAT_Table->reset_idx<=1) + pDM_SWAT_Table->RSSI_Trying = 2; + else + pDM_SWAT_Table->RSSI_Trying = 1; + + odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_PEEK); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal State: Begin Trying!!\n")); + + } else if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->Double_chk_flag == 0)) { + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->RSSI_Trying--; + } + + //1 Decision State + if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->RSSI_Trying == 0)) { + + BOOLEAN bByCtrlFrame = FALSE; + u8Byte pkt_cnt_total = 0; + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Antenna + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + + if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1) + Main_RSSI=0; + + if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1) + Aux_RSSI=0; + + TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; + LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI )); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + //2 Select RX Idle Antenna + + if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI) + { + RxIdleAnt = TargetAnt; + MinMaxRSSI = LocalMaxRSSI; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI))); + + if((LocalMaxRSSI-LocalMinRSSI)>8) + { + if(LocalMinRSSI != 0) + pDM_SWAT_Table->Train_time_flag=3; + else + { + if (MinMaxRSSI > RSSI_CHECK_THRESHOLD) + pDM_SWAT_Table->Train_time_flag=0; + else + pDM_SWAT_Table->Train_time_flag=3; + } + } + else if((LocalMaxRSSI-LocalMinRSSI)>5) + pDM_SWAT_Table->Train_time_flag=2; + else if((LocalMaxRSSI-LocalMinRSSI)>2) + pDM_SWAT_Table->Train_time_flag=1; + else + pDM_SWAT_Table->Train_time_flag=0; + + } + + //2 Select TX Antenna + if(TargetAnt == MAIN_ANT) + pDM_FatTable->antsel_a[i] = ANT1_2G; + else + pDM_FatTable->antsel_a[i] = ANT2_2G; + + } + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + + if(pDM_SWAT_Table->bSWAntDivByCtrlFrame) + { + odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_DETERMINE); + bByCtrlFrame = TRUE; + } + + pkt_cnt_total = pDM_FatTable->CCK_counter_main + pDM_FatTable->CCK_counter_aux + + pDM_FatTable->OFDM_counter_main + pDM_FatTable->OFDM_counter_aux; + pDM_FatTable->CCK_counter_main=0; + pDM_FatTable->CCK_counter_aux=0; + pDM_FatTable->OFDM_counter_main=0; + pDM_FatTable->OFDM_counter_aux=0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame packet counter = %d, Data frame packet counter = %llu\n", + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame, pkt_cnt_total)); + + if(MinMaxRSSI == 0xff || ((pkt_cnt_total < (pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame >> 1)) && pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)) + { + MinMaxRSSI = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Check RSSI of control frame because MinMaxRSSI == 0xff\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bByCtrlFrame = %d\n", bByCtrlFrame)); + + if(bByCtrlFrame) + { + Main_RSSI = (pDM_FatTable->MainAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->MainAnt_CtrlFrame_Sum/pDM_FatTable->MainAnt_CtrlFrame_Cnt):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->AuxAnt_CtrlFrame_Sum/pDM_FatTable->AuxAnt_CtrlFrame_Cnt):0; + + if(pDM_FatTable->MainAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_main>=1) + Main_RSSI=0; + + if(pDM_FatTable->AuxAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_aux>=1) + Aux_RSSI=0; + + if (Main_RSSI != 0 || Aux_RSSI != 0) + { + RxIdleAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; + LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; + + if((LocalMaxRSSI-LocalMinRSSI)>8) + pDM_SWAT_Table->Train_time_flag=3; + else if((LocalMaxRSSI-LocalMinRSSI)>5) + pDM_SWAT_Table->Train_time_flag=2; + else if((LocalMaxRSSI-LocalMinRSSI)>2) + pDM_SWAT_Table->Train_time_flag=1; + else + pDM_SWAT_Table->Train_time_flag=0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame: Main_RSSI = %d, Aux_RSSI = %d\n", Main_RSSI, Aux_RSSI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt decided by control frame = %s\n", (RxIdleAnt == MAIN_ANT?"MAIN":"AUX"))); + } + } + } + + pDM_FatTable->MinMaxRSSI = MinMaxRSSI; + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + + if( pDM_SWAT_Table->Double_chk_flag==1) + { + pDM_SWAT_Table->Double_chk_flag=0; + + if (pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) > %d again!!\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); + return; + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) <= %d !!\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal State: Need to tryg again!!\n\n\n")); + return; + } + } + else + { + if (pDM_FatTable->MinMaxRSSI < RSSI_CHECK_THRESHOLD) + pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; + + pDM_SWAT_Table->PreAntenna =RxIdleAnt; + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt ); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); + return; + } + + } + + } + + //1 4.Change TRX antenna + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )), Ant: (( %s )) >>> (( %s )) \n", + pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX"))); + + ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt); + + //1 5.Reset Statistics + + pDM_FatTable->RxIdleAnt = nextAnt; + + //1 6.Set next timer (Trying State) + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms\n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time)); + ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; + + #if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); + #else + { + //DbgPrint("SW_antdiv_Callback"); + odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); + } + #endif + #else + ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); + #endif +} +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //DbgPrint("SW_antdiv_Workitem_Callback"); + odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +) +{ + PADAPTER + pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE + *pHalData = GET_HAL_DATA(pAdapter); + + /*DbgPrint("SW_antdiv_Workitem_Callback");*/ + odm_S0S1_SwAntDiv(&pHalData->odmpriv, SWAW_STEP_DETERMINE); +} + +VOID +ODM_SW_AntDiv_Callback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + + #if 0 /* Can't do I/O in timer callback*/ + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE); + #else + rtw_run_in_thread_cmd(padapter, ODM_SW_AntDiv_WorkitemCallback, padapter); + #endif +} + + +#endif + +VOID +odm_S0S1_SwAntDivByCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte Step + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + switch(Step) + { + case SWAW_STEP_PEEK: + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame = 0; + pDM_SWAT_Table->bSWAntDivByCtrlFrame = TRUE; + pDM_FatTable->MainAnt_CtrlFrame_Cnt = 0; + pDM_FatTable->AuxAnt_CtrlFrame_Cnt = 0; + pDM_FatTable->MainAnt_CtrlFrame_Sum = 0; + pDM_FatTable->AuxAnt_CtrlFrame_Sum = 0; + pDM_FatTable->CCK_CtrlFrame_Cnt_main = 0; + pDM_FatTable->CCK_CtrlFrame_Cnt_aux = 0; + pDM_FatTable->OFDM_CtrlFrame_Cnt_main = 0; + pDM_FatTable->OFDM_CtrlFrame_Cnt_aux = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); + break; + case SWAW_STEP_DETERMINE: + pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); + break; + default: + pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; + break; + } +} + +VOID +odm_AntselStatisticsOfCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte RxPWDBAll + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(antsel_tr_mux == ANT1_2G) + { + pDM_FatTable->MainAnt_CtrlFrame_Sum+=RxPWDBAll; + pDM_FatTable->MainAnt_CtrlFrame_Cnt++; + } + else + { + pDM_FatTable->AuxAnt_CtrlFrame_Sum+=RxPWDBAll; + pDM_FatTable->AuxAnt_CtrlFrame_Cnt++; + } +} + +VOID +odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + //IN PODM_PHY_INFO_T pPhyInfo, + //IN PODM_PACKET_INFO_T pPktinfo + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + BOOLEAN isCCKrate; + + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV) + return; + + // In try state + if(!pDM_SWAT_Table->bSWAntDivByCtrlFrame) + return; + + // No HW error and match receiver address + if(!pPktinfo->bToSelf) + return; + + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame++; + isCCKrate = ((pPktinfo->DataRate >= DESC_RATE1M ) && (pPktinfo->DataRate <= DESC_RATE11M ))?TRUE :FALSE; + + if(isCCKrate) + { + pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->CCK_CtrlFrame_Cnt_main++; + else + pDM_FatTable->CCK_CtrlFrame_Cnt_aux++; + + odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); + } + else + { + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->OFDM_CtrlFrame_Cnt_main++; + else + pDM_FatTable->OFDM_CtrlFrame_Cnt_aux++; + + odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxPWDBAll); + } +} + +#endif //#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) + + + + +VOID +odm_SetNextMACAddrTarget( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PSTA_INFO_T pEntry; + u4Byte value32, i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); + + if (pDM_Odm->bLinked) + { + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + + if ((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) + pDM_FatTable->TrainIdx = 0; + else + pDM_FatTable->TrainIdx++; + + pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; + + if (IS_STA_VALID(pEntry)) { + + /*Match MAC ADDR*/ + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; + #else + value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; + #endif + + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; + #else + value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; + #endif + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);/*0x7b0~0x7b3*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n", pDM_FatTable->TrainIdx)); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->hwaddr[5], pEntry->hwaddr[4], pEntry->hwaddr[3], pEntry->hwaddr[2], pEntry->hwaddr[1], pEntry->hwaddr[0])); + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->MacAddr[5], pEntry->MacAddr[4], pEntry->MacAddr[3], pEntry->MacAddr[2], pEntry->MacAddr[1], pEntry->MacAddr[0])); + #endif + + break; + } + } + } + +#if 0 + // + //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn + // + #if( DM_ODM_SUPPORT_TYPE & ODM_WIN) + { + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + for (i=0; i<6; i++) + { + Bssid[i] = pMgntInfo->Bssid[i]; + //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); + } + } + #endif + + //odm_SetNextMACAddrTarget(pDM_Odm); + + //1 Select MAC Address Filter + for (i=0; i<6; i++) + { + if(Bssid[i] != pDM_FatTable->Bssid[i]) + { + bMatchBSSID = FALSE; + break; + } + } + if(bMatchBSSID == FALSE) + { + //Match MAC ADDR + value32 = (Bssid[5]<<8)|Bssid[4]; + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); + value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); + } + + return bMatchBSSID; +#endif + +} + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + +VOID +odm_FastAntTraining( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + u4Byte MaxRSSI_pathA=0, Pckcnt_pathA=0; + u1Byte i,TargetAnt_pathA=0; + BOOLEAN bPktFilterMacth_pathA = FALSE; + #if(RTL8192E_SUPPORT == 1) + u4Byte MaxRSSI_pathB=0, Pckcnt_pathB=0; + u1Byte TargetAnt_pathB=0; + BOOLEAN bPktFilterMacth_pathB = FALSE; + #endif + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } + + + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1)); + } + #if(RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1) ); //path-A // ant combination=regB38[2:0]+1 + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT18|BIT17|BIT16, ((pDM_Odm->fat_comb_b)-1) ); //path-B // ant combination=regB38[18:16]+1 + } + #endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); + + //1 TRAINING STATE + if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + { + //2 Caculate RSSI per Antenna + + //3 [path-A]--------------------------- + for (i=0; i<(pDM_Odm->fat_comb_a); i++) // i : antenna index + { + if(pDM_FatTable->antRSSIcnt[i] == 0) + pDM_FatTable->antAveRSSI[i] = 0; + else + { + pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; + bPktFilterMacth_pathA = TRUE; + } + + if(pDM_FatTable->antAveRSSI[i] > MaxRSSI_pathA) + { + MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; + Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; + TargetAnt_pathA = i ; + } + else if(pDM_FatTable->antAveRSSI[i] == MaxRSSI_pathA) + { + if( (pDM_FatTable->antRSSIcnt[i] ) > Pckcnt_pathA) + { + MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; + Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; + TargetAnt_pathA = i ; + } + } + + ODM_RT_TRACE("*** Ant-Index : [ %d ], Counter = (( %d )), Avg RSSI = (( %d )) \n", i, pDM_FatTable->antRSSIcnt[i], pDM_FatTable->antAveRSSI[i] ); + } + + + /* + #if(RTL8192E_SUPPORT == 1) + //3 [path-B]--------------------------- + for (i=0; i<(pDM_Odm->fat_comb_b); i++) + { + if(pDM_FatTable->antRSSIcnt_pathB[i] == 0) + pDM_FatTable->antAveRSSI_pathB[i] = 0; + else // (antRSSIcnt[i] != 0) + { + pDM_FatTable->antAveRSSI_pathB[i] = pDM_FatTable->antSumRSSI_pathB[i] /pDM_FatTable->antRSSIcnt_pathB[i]; + bPktFilterMacth_pathB = TRUE; + } + if(pDM_FatTable->antAveRSSI_pathB[i] > MaxRSSI_pathB) + { + MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; + Pckcnt_pathB = pDM_FatTable ->antRSSIcnt_pathB[i]; + TargetAnt_pathB = (u1Byte) i; + } + if(pDM_FatTable->antAveRSSI_pathB[i] == MaxRSSI_pathB) + { + if(pDM_FatTable ->antRSSIcnt_pathB > Pckcnt_pathB) + { + MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; + TargetAnt_pathB = (u1Byte) i; + } + } + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{Path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d )) \n", + i, pDM_FatTable->antSumRSSI_pathB[i], i, pDM_FatTable->antRSSIcnt_pathB[i], i, pDM_FatTable->antAveRSSI_pathB[i])); + } + } + #endif + */ + + //1 DECISION STATE + + //2 Select TRX Antenna + + phydm_FastTraining_enable(pDM_Odm, FAT_OFF); + + //3 [path-A]--------------------------- + if(bPktFilterMacth_pathA == FALSE) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + else + { + ODM_RT_TRACE("TargetAnt_pathA = (( %d )) , MaxRSSI_pathA = (( %d )) \n",TargetAnt_pathA,MaxRSSI_pathA); + + //3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt_pathA); + } + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, TargetAnt_pathA);//Optional RX [pth-A] + } + //3 [ update TX ant ] + odm_UpdateTxAnt(pDM_Odm, TargetAnt_pathA, (pDM_FatTable->TrainIdx)); + + if(TargetAnt_pathA == 0) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + /* + #if(RTL8192E_SUPPORT == 1) + //3 [path-B]--------------------------- + if(bPktFilterMacth_pathB == FALSE) + { + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{Path-B}: None Packet is matched\n\n\n",__LINE__)); + } + } + else + { + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + (" ***TargetAnt_pathB = (( %d )) *** MaxRSSI = (( %d ))***\n\n\n",TargetAnt_pathB,MaxRSSI_pathB)); + } + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT21|BIT20|BIT19, TargetAnt_pathB); //Default RX is Omni, Optional RX is the best decision by FAT + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + + pDM_FatTable->antsel_pathB[pDM_FatTable->TrainIdx] = TargetAnt_pathB; + } + #endif + */ + + //2 Reset Counter + for(i=0; i<(pDM_Odm->fat_comb_a); i++) + { + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + } + /* + #if(RTL8192E_SUPPORT == 1) + for(i=0; i<=(pDM_Odm->fat_comb_b); i++) + { + pDM_FatTable->antSumRSSI_pathB[i] = 0; + pDM_FatTable->antRSSIcnt_pathB[i] = 0; + } + #endif + */ + + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + return; + } + + //1 NORMAL STATE + if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare State ]\n")); + + odm_SetNextMACAddrTarget(pDM_Odm); + + //2 Prepare Training + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + phydm_FastTraining_enable(pDM_Odm , FAT_ON); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); //enable HW AntDiv + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training State]\n")); + + ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms + } + +} + +VOID +odm_FastAntTrainingCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + //if(*pDM_Odm->pbNet_closed == TRUE) + // return; +#endif + +#if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingCallback****** \n")); + odm_FastAntTraining(pDM_Odm); +#endif +} + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingWorkItemCallback****** \n")); + odm_FastAntTraining(pDM_Odm); +} + +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + +u4Byte +phydm_construct_hl_beam_codeword( + IN PVOID pDM_VOID, + IN u4Byte *beam_pattern_idx, + IN u4Byte ant_num + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte codeword = 0; + u4Byte data_tmp; + u4Byte i; + u4Byte break_counter = 0; + + if (ant_num < 8) { + for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ + if ((i < (pdm_sat_table->first_train_ant-1)) || (break_counter >= (pdm_sat_table->ant_num))) { + data_tmp = 0; + /**/ + } else { + + break_counter++; + + if (beam_pattern_idx[i] == 0) { + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[0]; + + } else if (beam_pattern_idx[i] == 1) { + + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[1]; + + } else if (beam_pattern_idx[i] == 2) { + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[2]; + + } else if (beam_pattern_idx[i] == 3) { + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[3]; + } + } + + + codeword |= (data_tmp<<(i*4)); + + } + } + + return codeword; +} + +VOID +phydm_update_beam_pattern( + IN PVOID pDM_VOID, + IN u4Byte codeword, + IN u4Byte codeword_length + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u1Byte i; + BOOLEAN beam_ctrl_signal; + u4Byte one = 0x1; + u4Byte reg44_tmp_p, reg44_tmp_n, reg44_ori; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); + + reg44_ori = ODM_GetMACReg(pDM_Odm, 0x44, bMaskDWord); + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ + + for (i = 0; i <= (codeword_length-1); i++) { + beam_ctrl_signal = (BOOLEAN)((codeword&BIT(i)) >> i); + + if (pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) { + + if (i == (codeword_length-1)) { + DbgPrint("%d ]\n", beam_ctrl_signal); + /**/ + } else if (i == 0) { + DbgPrint("Send codeword[1:24] ---> [ %d ", beam_ctrl_signal); + /**/ + } else if ((i % 4) == 3) { + DbgPrint("%d | ", beam_ctrl_signal); + /**/ + } else { + DbgPrint("%d ", beam_ctrl_signal); + /**/ + } + } + + #if 1 + reg44_tmp_p = reg44_ori & (~(BIT11|BIT10)); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1<<11) | (beam_ctrl_signal<<10)); + reg44_tmp_n = reg44_ori & (~(BIT11|BIT10)); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ + ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_p); + ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_n); + #else + ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, ((1<<1) | beam_ctrl_signal)); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT11, 0); + #endif + + } +} + +VOID +phydm_update_rx_idle_beam( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte i; + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + + for (i = 0; i < (pdm_sat_table->ant_num); i++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); + /**/ + } + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif + + pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; +} + +VOID +phydm_hl_smart_ant_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte used = *_used; + u4Byte out_len = *_out_len; + u4Byte one = 0x1; + u4Byte codeword_length = pdm_sat_table->data_codeword_bit_num; + u4Byte beam_ctrl_signal, i; + + if (dm_value[0] == 1) { /*fix beam pattern*/ + + pdm_sat_table->fix_beam_pattern_en = dm_value[1]; + + if (pdm_sat_table->fix_beam_pattern_en == 1) { + + pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; + + if (pdm_sat_table->fix_beam_pattern_codeword > (one<fix_beam_pattern_codeword, codeword_length)); + (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); + } + + pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; + + /*---------------------------------------------------------*/ + PHYDM_SNPRINTF((output+used, out_len-used, "Fix Beam Pattern\n")); + for (i = 0; i <= (codeword_length-1); i++) { + beam_ctrl_signal = (BOOLEAN)((pdm_sat_table->update_beam_codeword&BIT(i)) >> i); + + if (i == (codeword_length-1)) { + PHYDM_SNPRINTF((output+used, out_len-used, "%d]\n", beam_ctrl_signal)); + /**/ + } else if (i == 0) { + PHYDM_SNPRINTF((output+used, out_len-used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); + /**/ + } else if ((i % 4) == 3) { + PHYDM_SNPRINTF((output+used, out_len-used, "%d|", beam_ctrl_signal)); + /**/ + } else { + PHYDM_SNPRINTF((output+used, out_len-used, "%d", beam_ctrl_signal)); + /**/ + } + } + /*---------------------------------------------------------*/ + + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif + } else if (pdm_sat_table->fix_beam_pattern_en == 0) { + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Smart Antenna: Enable\n")); + } + + } else if (dm_value[0] == 2) { /*set latch time*/ + + pdm_sat_table->latch_time = dm_value[1]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); + } else if (dm_value[0] == 3) { + + pdm_sat_table->fix_training_num_en = dm_value[1]; + + if (pdm_sat_table->fix_training_num_en == 1) { + pdm_sat_table->per_beam_training_pkt_num = (u1Byte)dm_value[2]; + pdm_sat_table->decision_holding_period = (u1Byte)dm_value[3]; + + PHYDM_SNPRINTF((output+used, out_len-used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); + + } else if (pdm_sat_table->fix_training_num_en == 0) { + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); + /**/ + } + } else if (dm_value[0] == 4) { + + if (dm_value[1] == 1) { + pdm_sat_table->ant_num = 1; + pdm_sat_table->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + pdm_sat_table->ant_num = 1; + pdm_sat_table->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + pdm_sat_table->ant_num = 2; + pdm_sat_table->first_train_ant = MAIN_ANT; + } + + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Ant Num = (( %d )), first_train_ant = (( %d ))\n", + pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant-1))); + } else if (dm_value[0] == 5) { + + if (dm_value[1] <= 3) { + pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2])); + } else { + for (i = 0; i < 4; i++) { + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, pdm_sat_table->rfu_codeword_table[i])); + } + } + } else if (dm_value[0] == 6) { + + if (dm_value[1] <= 3) { + pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2])); + } else { + for (i = 0; i < 4; i++) { + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, pdm_sat_table->rfu_codeword_table_5g[i])); + } + } + } else if (dm_value[0] == 7) { + + if (dm_value[1] <= 4) { + + pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam number = (( %d ))\n", + pdm_sat_table->beam_patten_num_each_ant)); + } else { + + PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam number = (( %d ))\n", + pdm_sat_table->beam_patten_num_each_ant)); + } + } + +} + + +void +phydm_set_all_ant_same_beam_num( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { /*2Ant for 8821A*/ + + pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; + pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; + } + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif +} + +VOID +odm_FastAntTraining_hl_smart_antenna_type1( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + pFAT_T pDM_FatTable = &(pDM_Odm->DM_FatTable); + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte codeword = 0, i, j; + u4Byte TargetAnt; + u4Byte avg_rssi_tmp, avg_rssi_tmp_ma; + u4Byte target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u4Byte max_beam_ant_rssi = 0; + u4Byte target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u4Byte beam_tmp; + u1Byte next_ant; + u4Byte rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u4Byte rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u4Byte rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u1Byte per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; + u4Byte break_counter = 0; + u4Byte used_ant; + + + if (!pDM_Odm->bLinked) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if (pDM_FatTable->bBecomeLinked == TRUE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link -> no Link\n")); + pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + + } else { + if (pDM_FatTable->bBecomeLinked == FALSE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); + + /*pdm_sat_table->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(pDM_Odm);*/ + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart Ant Training: State (( %d ))\n", pDM_FatTable->FAT_State));*/ + + /* [DECISION STATE] */ + /*=======================================================================================*/ + if (pDM_FatTable->FAT_State == FAT_DECISION_STATE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision State]\n")); + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + + break_counter = 0; + /*compute target beam in each antenna*/ + for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); + avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j])>>1; + } + + rssi_sorting_seq[j] = avg_rssi_tmp; + pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", + i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + pdm_sat_table->pkt_rssi_sum[i][j] = 0; + pdm_sat_table->pkt_rssi_cnt[i][j] = 0; + + } + pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of Ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], target_ant_beam_max_rssi[i])); + + /*sorting*/ + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); + */ + + /*phydm_seq_sorting(pDM_Odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ + + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); + */ + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + TargetAnt = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of Ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + TargetAnt, max_beam_ant_rssi));*/ + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } + + #ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + per_beam_rssi_diff_tmp = (u1Byte)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); + pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", + i, j, per_beam_rssi_diff_tmp)); + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } + #endif + + if (TargetAnt == 0) + TargetAnt = MAIN_ANT; + else if (TargetAnt == 1) + TargetAnt = AUX_ANT; + + if (pdm_sat_table->ant_num > 1) { + /* [ update RX ant ]*/ + ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)TargetAnt); + + /* [ update TX ant ]*/ + odm_UpdateTxAnt(pDM_Odm, (u1Byte)TargetAnt, (pDM_FatTable->TrainIdx)); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(pDM_Odm); + + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + + } + /* [TRAINING STATE] */ + else if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training State]\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); + + if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) { + + pdm_sat_table->force_update_beam_en = 0; + + } else { + + pdm_sat_table->force_update_beam_en = 1; + + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); + pDM_FatTable->FAT_State = FAT_DECISION_STATE; + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + + } else { + pdm_sat_table->fast_training_beam_num++; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(pDM_Odm); + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + + } + } + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); + } + /* [Prepare State] */ + /*=======================================================================================*/ + else if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare State]\n")); + + if (pDM_Odm->pre_TrafficLoad == (pDM_Odm->TrafficLoad)) { + if (pdm_sat_table->decision_holding_period != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); + pdm_sat_table->decision_holding_period--; + return; + } + } + + + /* Set training packet number*/ + if (pdm_sat_table->fix_training_num_en == 0) { + + switch (pDM_Odm->TrafficLoad) { + + case TRAFFIC_HIGH: + pdm_sat_table->per_beam_training_pkt_num = 8; + pdm_sat_table->decision_holding_period = 2; + break; + case TRAFFIC_MID: + pdm_sat_table->per_beam_training_pkt_num = 6; + pdm_sat_table->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ + pdm_sat_table->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + pdm_sat_table->per_beam_training_pkt_num = 1; + pdm_sat_table->decision_holding_period = 6; + break; + default: + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", + pdm_sat_table->fix_training_num_en , pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); + + + #ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; + training_pkt_num_offset = per_beam_rssi_diff_tmp; + + if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) + pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; + else + pdm_sat_table->beam_train_cnt[i][j] = 1; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", + i, j, pdm_sat_table->beam_train_cnt[i][j])); + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } + + + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->update_beam_idx = 0; + + if (*pDM_Odm->pBandType == ODM_BAND_5G) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); + /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ + used_ant = pdm_sat_table->first_train_ant; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); + used_ant = pdm_sat_table->first_train_ant; + } + + ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)used_ant); + + #else + /* Set training MAC Addr. of target */ + odm_SetNextMACAddrTarget(pDM_Odm); + phydm_FastTraining_enable(pDM_Odm , FAT_ON); + #endif + + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(pDM_Odm); + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + } + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +phydm_beam_switch_workitem_callback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + + #if DEV_BUS_TYPE != RT_PCI_INTERFACE + pdm_sat_table->pkt_skip_statistic_en = 1; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); + + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + + #if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*ODM_StallExecution(pdm_sat_table->latch_time);*/ + pdm_sat_table->pkt_skip_statistic_en = 0; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); +} + +VOID +phydm_beam_decision_workitem_callback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); +} +#endif + +#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +VOID +ODM_AntDivInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); + return; + } + //--- +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); + } + +#endif + //--- + + //2 [--General---] + pDM_Odm->antdiv_period=0; + + pDM_FatTable->bBecomeLinked =FALSE; + pDM_FatTable->AntDiv_OnOff =0xff; + + //3 - AP - + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #if (BEAMFORMING_SUPPORT == 1) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_BDC_Init(pDM_Odm); + #endif + #endif + + //3 - WIN - + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_SWAT_Table->Ant5G = MAIN_ANT; + pDM_SWAT_Table->Ant2G = MAIN_ANT; + pDM_FatTable->CCK_counter_main=0; + pDM_FatTable->CCK_counter_aux=0; + pDM_FatTable->OFDM_counter_main=0; + pDM_FatTable->OFDM_counter_aux=0; + #endif + + //2 [---Set MAIN_ANT as default antenna if Auto-Ant enable---] + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + + pDM_Odm->AntType = ODM_AUTO_ANT; + + pDM_FatTable->RxIdleAnt = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + phydm_keep_RxAckAnt_By_TxAnt_time( pDM_Odm, 5); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ + + //2 [---Set TX Antenna---] + pDM_FatTable->ForceTxAntByDesc = 0; + pDM_FatTable->pForceTxAntByDesc = &(pDM_FatTable->ForceTxAntByDesc); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("pForceTxAntByDesc = %d\n", *pDM_FatTable->pForceTxAntByDesc)); + + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + + + //2 [--88E---] + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + #if (RTL8188E_SUPPORT == 1) + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + + if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 88E Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDiv_Init_88E(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_88E(pDM_Odm); + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_Smart_HWAntDiv_Init_88E(pDM_Odm); + #endif + #endif + } + + //2 [--92E---] + #if (RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + + if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8192E Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDiv_Init_92E(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_92E(pDM_Odm); + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_Smart_HWAntDiv_Init_92E(pDM_Odm); + #endif + + } + #endif + + //2 [--97F---] + #if (RTL8197F_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8197F) + { + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if( pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8197F Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + odm_RX_HWAntDiv_Init_97F(pDM_Odm); + + } + #endif + + //2 [--8723B---] + #if (RTL8723B_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV) + odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm); + else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8723B(pDM_Odm); + } + #endif + /*2 [--8723D---]*/ + #if (RTL8723D_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (pDM_Odm->AntDivType == S0S1_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8723D(pDM_Odm); + else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + } + #endif + //2 [--8811A 8821A---] + #if (RTL8821A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8821) + { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pDM_Odm->AntDivType = HL_SW_SMART_ANT_TYPE1; + + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { + + odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); + phydm_hl_smart_ant_type1_init_8821a(pDM_Odm); + } else + #endif + { + /*pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;*/ + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + + if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); + else if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm); + } + } + #endif + + //2 [--8821C---] + #if (RTL8821C_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8821C) + { + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV ) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + odm_TRX_HWAntDiv_Init_8821C(pDM_Odm); + } + #endif + + //2 [--8881A---] + #if (RTL8881A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8881A) + { + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { + + odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); + /**/ + } else { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); + } + #endif + + //2 [--8812---] + #if (RTL8812A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + odm_TRX_HWAntDiv_Init_8812A(pDM_Odm); + } + #endif + + /*[--8188F---]*/ + #if (RTL8188F_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + odm_S0S1_SWAntDiv_Init_8188F(pDM_Odm); + } + #endif + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** SupportICType=[%lu]\n",pDM_Odm->SupportICType)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv SupportAbility=[%lu]\n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv Type=[%d]\n",pDM_Odm->AntDivType)); + */ +} + +VOID +ODM_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + #endif + + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period ) + { + pDM_FatTable->idx_AntDiv_counter_5G++; + return; + } + else + pDM_FatTable->idx_AntDiv_counter_5G=0; + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + if(pDM_FatTable->idx_AntDiv_counter_2G < pDM_Odm->antdiv_period ) + { + pDM_FatTable->idx_AntDiv_counter_2G++; + return; + } + else + pDM_FatTable->idx_AntDiv_counter_2G=0; + } + + //---------- + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); + return; + } + + //---------- +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (pDM_FatTable->enable_ctrl_frame_antdiv) { + + if ((pDM_Odm->data_frame_num <= 10) && (pDM_Odm->bLinked)) + pDM_FatTable->use_ctrl_frame_antdiv = 1; + else + pDM_FatTable->use_ctrl_frame_antdiv = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", pDM_FatTable->use_ctrl_frame_antdiv, pDM_Odm->data_frame_num)); + pDM_Odm->data_frame_num = 0; + } + + if(pAdapter->MgntInfo.AntennaTest) + return; + + { + #if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); + + if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n")); + if(pDM_FatTable->fix_ant_bfee == 0) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pDM_FatTable->fix_ant_bfee = 1; + } + return; + } + else // BFmee Off && Div Off -> Div On + { + if((pDM_FatTable->fix_ant_bfee == 1) && pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); + if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) ) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + + pDM_FatTable->fix_ant_bfee = 0; + } + } + #endif + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //----------just for fool proof + + if(pDM_Odm->antdiv_rssi) + pDM_Odm->DebugComponents |= ODM_COMP_ANT_DIV; + else + pDM_Odm->DebugComponents &= ~ODM_COMP_ANT_DIV; + + if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) + { + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) + { + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } + //else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) + //{ + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); + //} +#endif + + //---------- + + if (pDM_Odm->antdiv_select==1) + pDM_Odm->AntType = ODM_FIX_MAIN_ANT; + else if (pDM_Odm->antdiv_select==2) + pDM_Odm->AntType = ODM_FIX_AUX_ANT; + else //if (pDM_Odm->antdiv_select==0) + pDM_Odm->AntType = ODM_AUTO_ANT; + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType)); + + if(pDM_Odm->AntType != ODM_AUTO_ANT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX")); + + if(pDM_Odm->AntType != pDM_Odm->pre_AntType) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + + if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + } + pDM_Odm->pre_AntType=pDM_Odm->AntType; + return; + } + else + { + if(pDM_Odm->AntType != pDM_Odm->pre_AntType) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } + pDM_Odm->pre_AntType=pDM_Odm->AntType; + } + + + //3 ----------------------------------------------------------------------------------------------------------- + //2 [--88E---] + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + #if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + odm_FastAntTraining(pDM_Odm); + #endif + + #endif + + } + //2 [--92E---] + #if (RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV || pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + odm_FastAntTraining(pDM_Odm); + #endif + + } + #endif + + //2 [--97F---] + #if (RTL8197F_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8197F) + { + if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + } + #endif + + #if (RTL8723B_SUPPORT == 1) + //2 [--8723B---] + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if (phydm_IsBtEnable_8723b(pDM_Odm)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); + if (pDM_FatTable->bBecomeLinked == TRUE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + if (pDM_Odm->SupportICType == ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); + + pDM_FatTable->bBecomeLinked = FALSE; + } + } else { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + } + } + #endif + /*8723D*/ + #if (RTL8723D_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723D) { + + odm_HW_AntDiv(pDM_Odm); + /**/ + } + #endif + + //2 [--8821A---] + #if (RTL8821A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8821) + { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { + + if (pdm_sat_table->fix_beam_pattern_en != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + /*return;*/ + } else { + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] AntDivType = HL_SW_SMART_ANT_TYPE1\n"));*/ + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + } + + } else + #endif + { + + if (!pDM_Odm->bBtEnabled) /*BT disabled*/ + { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); + /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); */ + if (pDM_FatTable->bBecomeLinked == TRUE) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + } + + } else { /*BT enabled*/ + + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); + /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);*/ + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + } + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + } + } + #endif + + //2 [--8821C---] + #if (RTL8821C_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8821C) + { + odm_HW_AntDiv(pDM_Odm); + } + #endif + + //2 [--8881A---] + #if (RTL8881A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8881A) + odm_HW_AntDiv(pDM_Odm); + #endif + + //2 [--8812A---] + #if (RTL8812A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8812) + odm_HW_AntDiv(pDM_Odm); + #endif + + #if (RTL8188F_SUPPORT == 1) + /* [--8188F---]*/ + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } + #endif + +} + + +VOID +odm_AntselStatistics( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte utility, + IN u1Byte method, + IN u1Byte isCCKrate + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + + if (method == RSSI_METHOD) { + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (isCCKrate) { + if (antsel_tr_mux == ANT1_2G) { + if (pDM_FatTable->MainAnt_Sum_cck[MacId] > 65435) /*to prevent u2Byte overflow, max(RSSI)=100, 65435+100 = 65535 (u2Byte)*/ + return; + + pDM_FatTable->MainAnt_Sum_cck[MacId] += (u2Byte)utility; + pDM_FatTable->MainAnt_Cnt_cck[MacId]++; + } else { + if (pDM_FatTable->AuxAnt_Sum_cck[MacId] > 65435) + return; + + pDM_FatTable->AuxAnt_Sum_cck[MacId] += (u2Byte)utility; + pDM_FatTable->AuxAnt_Cnt_cck[MacId]++; + } + + } else + #endif + { /*ofdm rate*/ + + if (antsel_tr_mux == ANT1_2G) { + if (pDM_FatTable->MainAnt_Sum[MacId] > 65435) + return; + + pDM_FatTable->MainAnt_Sum[MacId] += (u2Byte)utility; + pDM_FatTable->MainAnt_Cnt[MacId]++; + } else { + if (pDM_FatTable->AuxAnt_Sum[MacId] > 65435) + return; + + pDM_FatTable->AuxAnt_Sum[MacId] += (u2Byte)utility; + pDM_FatTable->AuxAnt_Cnt[MacId]++; + } + } + } + #ifdef ODM_EVM_ENHANCE_ANTDIV + else if(method==EVM_METHOD) + { + if (pDM_Odm->rate_ss == 1) { + + if(antsel_tr_mux == ANT1_2G) + { + pDM_FatTable->MainAntEVM_Sum[MacId]+=((pPhyInfo->RxMIMOEVMdbm[0])<<5); + pDM_FatTable->MainAntEVM_Cnt[MacId]++; + } + else + { + pDM_FatTable->AuxAntEVM_Sum[MacId]+=((pPhyInfo->RxMIMOEVMdbm[0])<<5); + pDM_FatTable->AuxAntEVM_Cnt[MacId]++; + } + + } else { /*>= 2SS*/ + + if (antsel_tr_mux == ANT1_2G) { + + pDM_FatTable->MainAntEVM_2ss_Sum[MacId][0] += (pPhyInfo->RxMIMOEVMdbm[0]<<5); + pDM_FatTable->MainAntEVM_2ss_Sum[MacId][1] += (pPhyInfo->RxMIMOEVMdbm[1]<<5); + pDM_FatTable->MainAntEVM_2ss_Cnt[MacId]++; + + } else { + + pDM_FatTable->AuxAntEVM_2ss_Sum[MacId][0] += (pPhyInfo->RxMIMOEVMdbm[0]<<5); + pDM_FatTable->AuxAntEVM_2ss_Sum[MacId][1] += (pPhyInfo->RxMIMOEVMdbm[1]<<5); + pDM_FatTable->AuxAntEVM_2ss_Cnt[MacId]++; + } + } + } + else if(method==CRC32_METHOD) + { + if (antsel_tr_mux == ANT1_2G) { + pDM_FatTable->MainCRC32_Ok_Cnt += utility; + pDM_FatTable->MainCRC32_Fail_Cnt ++; + } else { + pDM_FatTable->AuxCRC32_Ok_Cnt += utility; + pDM_FatTable->AuxCRC32_Fail_Cnt ++; + } + } + else if(method==TP_METHOD) + { + if (((utility <= ODM_RATEMCS15) && (utility >= ODM_RATEMCS0)) && + (pDM_FatTable->FAT_State_cnt <= pDM_Odm->antdiv_tp_period) + ) { + + if (antsel_tr_mux == ANT1_2G) { + pDM_FatTable->antdiv_tp_main += (phy_rate_table[utility])<<5; + pDM_FatTable->antdiv_tp_main_cnt++; + } else { + pDM_FatTable->antdiv_tp_aux += (phy_rate_table[utility])<<5; + pDM_FatTable->antdiv_tp_aux_cnt++; + } + } + } + #endif +} + + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + //IN PODM_PHY_INFO_T pPhyInfo, + //IN PODM_PACKET_INFO_T pPktinfo + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + u1Byte isCCKrate=0,CCKMaxRate=ODM_RATE11M; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte beam_tmp; + u1Byte next_ant; + u1Byte train_pkt_number; + #endif + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPower_Ant0, RxPower_Ant1; + u4Byte RxEVM_Ant0, RxEVM_Ant1; + #else + u1Byte RxPower_Ant0, RxPower_Ant1; + u1Byte RxEVM_Ant0, RxEVM_Ant1; + #endif + u8 rate_ss; + + CCKMaxRate=ODM_RATE11M; + isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE; + + if ((pDM_Odm->SupportICType & ODM_IC_2SS) && (pPktinfo->DataRate > CCKMaxRate)) + { + RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0]; + RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1]; + + RxEVM_Ant0 =pPhyInfo->RxMIMOSignalQuality[0]; + RxEVM_Ant1 =pPhyInfo->RxMIMOSignalQuality[1]; + } + else + RxPower_Ant0=pPhyInfo->RxPWDBAll; + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + #ifdef CONFIG_FAT_PATCH + if ((pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) { + + /*[Beacon]*/ + if (pPktinfo->bPacketBeacon) { + + pdm_sat_table->beacon_counter++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); + + if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { + + if (pdm_sat_table->ant_num > 1) { + next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); + } + + pdm_sat_table->update_beam_idx++; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); + + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->pkt_counter = 0; + } + } + /*[Data]*/ + else if (pPktinfo->bPacketToSelf) { + + if (pdm_sat_table->pkt_skip_statistic_en == 0) { + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", + pPktinfo->StationID, pdm_sat_table->pkt_counter, pDM_FatTable->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + + pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; + pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; + pdm_sat_table->pkt_counter++; + + #if 1 + train_pkt_number = pdm_sat_table->beam_train_cnt[pDM_FatTable->RxIdleAnt-1][pdm_sat_table->fast_training_beam_num]; + #else + train_pkt_number = pdm_sat_table->per_beam_training_pkt_num; + #endif + + /*Swich Antenna erery N pkts*/ + if (pdm_sat_table->pkt_counter == train_pkt_number) { + + if (pdm_sat_table->ant_num > 1) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); + next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); + } + + pdm_sat_table->update_beam_idx++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", + pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); + + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->pkt_counter = 0; + } + } + } + + /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/ + if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) { + + pdm_sat_table->update_beam_idx = 0; + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { + + pDM_FatTable->FAT_State = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); + #endif + + + } else { + pdm_sat_table->fast_training_beam_num++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(pDM_Odm); + + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + } + } + + } + #else + + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) + { + if ((pDM_Odm->SupportICType & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + (pPktinfo->bPacketToSelf) && + (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + ) { + + if (pdm_sat_table->pkt_skip_statistic_en == 0) { + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), bPacketToSelf = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pPktinfo->bPacketToSelf, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + + + pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; + pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; + pdm_sat_table->pkt_counter++; + + /*swich beam every N pkt*/ + if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { + + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { + + pDM_FatTable->FAT_State = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); + #endif + + + } else { + pdm_sat_table->fast_training_beam_num++; + phydm_set_all_ant_same_beam_num(pDM_Odm); + + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + } + } + } + } + } + #endif + else + #endif + if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { + if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && (pPktinfo->bPacketToSelf) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) + { + u1Byte antsel_tr_mux; + antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; + pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0; + pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; + } + } + else //AntDivType != CG_TRX_SMART_ANTDIV + { + if ((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pPktinfo->bPacketToSelf || pDM_FatTable->use_ctrl_frame_antdiv)) { + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + if (isCCKrate) + pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0, RSSI_METHOD, isCCKrate); + + } else { + + odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0, RSSI_METHOD, isCCKrate); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (pDM_Odm->SupportICType == ODM_RTL8192E|ODM_RTL8197F) { + if (!isCCKrate) { + odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxEVM_Ant0, EVM_METHOD, isCCKrate); + odm_AntselStatistics(pDM_Odm,pPhyInfo, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, pPktinfo->DataRate, TP_METHOD, isCCKrate); + } + } + #endif + } + } + } + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + return; + + + if (pDM_Odm->SupportICType == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); + SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); + SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } +} +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +ODM_SetTxAntByTxInfo( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid +) +{ + PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); + pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; + u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; + + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + return; + + if (SupportICType == ODM_RTL8881A) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ + pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + } else if (SupportICType == ODM_RTL8192E) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ + pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + } else if (SupportICType == ODM_RTL8188E) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ + pdesc->Dword2 &= set_desc(~BIT(24)); + pdesc->Dword2 &= set_desc(~BIT(25)); + pdesc->Dword7 &= set_desc(~BIT(29)); + + pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_a[aid]<<24); + pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_b[aid]<<25); + pdesc->Dword7 |= set_desc(pDM_FatTable->antsel_c[aid]<<29); + + + } else if (SupportICType == ODM_RTL8812) { + /*[path-A]*/ + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ + + pdesc->Dword6 &= set_desc(~BIT(16)); + pdesc->Dword6 &= set_desc(~BIT(17)); + pdesc->Dword6 &= set_desc(~BIT(18)); + + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18); + + } +} + + +#if 1 /*def CONFIG_WLAN_HAL*/ +VOID +ODM_SetTxAntByTxInfo_HAL( + struct rtl8192cd_priv *priv, + PVOID pdesc_data, + u2Byte aid +) +{ + PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); + pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; + u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; + PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; + + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + return; + + if (SupportICType == ODM_RTL8881A || SupportICType == ODM_RTL8192E || SupportICType == ODM_RTL8814A) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_HAL******\n",__FUNCTION__,__LINE__);*/ + pdescdata->antSel = 1; + pdescdata->antSel_A = pDM_FatTable->antsel_a[aid]; + } +} +#endif /*#ifdef CONFIG_WLAN_HAL*/ + +#endif + + +VOID +ODM_AntDiv_Config( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + ODM_RT_TRACE (pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); + /* + if(pDM_Odm->SupportICType==ODM_RTL8723B) + { + if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON)) + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } + */ + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + + pDM_Odm->AntDivType = S0S1_TRX_HW_ANTDIV; + /**/ + } +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); + + if(pDM_Odm->SupportICType==ODM_RTL8723B) + { + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + + + } + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + + //2 [ NOT_SUPPORT_ANTDIV ] + #if(defined(CONFIG_NOT_SUPPORT_ANTDIV)) + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); + + //2 [ 2G&5G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n")); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G); + + if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY)||defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + + //2 [ 5G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); + panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G); + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } + + //2 [ 2G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_2G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G); + if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } + #endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) ? 1 : 0))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", pDM_Odm->DM_FatTable.b_fix_tx_ant)); + +} + + +VOID +ODM_AntDivTimers( + IN PVOID pDM_VOID, + IN u1Byte state + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(state==INIT_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_InitializeTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer), + (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "phydm_SwAntennaSwitchTimer"); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, + (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, + (RT_TIMER_CALL_BACK)odm_EVM_FastAntTrainingCallback, NULL, "EVM_FastAntTrainingTimer"); + #endif + } + else if(state==CANCEL_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_CancelTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_CancelTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); + #endif + } + else if(state==RELEASE_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_ReleaseTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); + #endif + } + +} + +VOID +phydm_antdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + /*pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;*/ + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + if (dm_value[0] == 1) { /*fixed or auto antenna*/ + + if (dm_value[1] == 0) { + pDM_Odm->antdiv_select = 0; + PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Auto\n")); + } else if (dm_value[1] == 1) { + pDM_Odm->antdiv_select = 1; + PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix MAin\n")); + } else if (dm_value[1] == 2) { + pDM_Odm->antdiv_select = 2; + PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix Aux\n")); + } + } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/ + + pDM_Odm->antdiv_period = (u1Byte)dm_value[1]; + PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv_period = ((%d))\n", pDM_Odm->antdiv_period)); + } +} + +#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ + +VOID +ODM_AntDivReset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SWAntDiv_Reset(pDM_Odm); + #endif + } + +} + +VOID +odm_AntennaDiversityInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->mp_mode == TRUE) + return; + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDiv_Config(pDM_Odm); + ODM_AntDivInit(pDM_Odm); + #endif +} + +VOID +odm_AntennaDiversity( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->mp_mode == TRUE) + return; + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDiv(pDM_Odm); + #endif +} + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_antdiv.h b/package/kernel/rtl8192cd/phydm/phydm_antdiv.h index 08dca7eaa2e..f3b58dc547b 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_antdiv.h +++ b/package/kernel/rtl8192cd/phydm/phydm_antdiv.h @@ -1,652 +1,652 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMANTDIV_H__ -#define __PHYDMANTDIV_H__ - -/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ -/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ -/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ -/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ -/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ -/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, - because antenna diversity only works when BT is disable or radio off*/ -/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ -/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ -/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ -/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ -/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ -#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ - -//1 ============================================================ -//1 Definition -//1 ============================================================ - -#define ANTDIV_INIT 0xff -#define MAIN_ANT 1 /*Ant A or Ant Main or S1*/ -#define AUX_ANT 2 /*AntB or Ant Aux or S0*/ -#define MAX_ANT 3 /* 3 for AP using*/ - -#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ -#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ -/*smart antenna*/ -#define SUPPORT_RF_PATH_NUM 4 -#define SUPPORT_BEAM_PATTERN_NUM 4 -#define NUM_ANTENNA_8821A 2 - -#define NO_FIX_TX_ANT 0 -#define FIX_TX_AT_MAIN 1 -#define FIX_AUX_AT_MAIN 2 - -//Antenna Diversty Control Type -#define ODM_AUTO_ANT 0 -#define ODM_FIX_MAIN_ANT 1 -#define ODM_FIX_AUX_ANT 2 - -#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) -#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT) -#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) -#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821) - -#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) - -#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8197F) - -#define ODM_ANTDIV_2G BIT0 -#define ODM_ANTDIV_5G BIT1 - -#define ANTDIV_ON 1 -#define ANTDIV_OFF 0 - -#define FAT_ON 1 -#define FAT_OFF 0 - -#define TX_BY_DESC 1 -#define TX_BY_REG 0 - -#define RSSI_METHOD 0 -#define EVM_METHOD 1 -#define CRC32_METHOD 2 -#define TP_METHOD 3 - -#define INIT_ANTDIV_TIMMER 0 -#define CANCEL_ANTDIV_TIMMER 1 -#define RELEASE_ANTDIV_TIMMER 2 - -#define CRC32_FAIL 1 -#define CRC32_OK 0 - -#define Evm_RSSI_TH_High 25 -#define Evm_RSSI_TH_Low 20 - -#define NORMAL_STATE_MIAN 1 -#define NORMAL_STATE_AUX 2 -#define TRAINING_STATE 3 - -#define FORCE_RSSI_DIFF 10 - -#define CSI_ON 1 -#define CSI_OFF 0 - -#define DIVON_CSIOFF 1 -#define DIVOFF_CSION 2 - -#define BDC_DIV_TRAIN_STATE 0 -#define BDC_BFer_TRAIN_STATE 1 -#define BDC_DECISION_STATE 2 -#define BDC_BF_HOLD_STATE 3 -#define BDC_DIV_HOLD_STATE 4 - -#define BDC_MODE_1 1 -#define BDC_MODE_2 2 -#define BDC_MODE_3 3 -#define BDC_MODE_4 4 -#define BDC_MODE_NULL 0xff - -/*SW S0S1 antenna diversity*/ -#define SWAW_STEP_INIT 0xff -#define SWAW_STEP_PEEK 0 -#define SWAW_STEP_DETERMINE 1 - -#define RSSI_CHECK_RESET_PERIOD 10 -#define RSSI_CHECK_THRESHOLD 50 - -/*Hong Lin Smart antenna*/ -#define HL_SMTANT_2WIRE_DATA_LEN 24 - -//1 ============================================================ -//1 structure -//1 ============================================================ - - -typedef struct _SW_Antenna_Switch_ -{ - u1Byte Double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ - u1Byte try_flag; - s4Byte PreRSSI; - u1Byte CurAntenna; - u1Byte PreAntenna; - u1Byte RSSI_Trying; - u1Byte reset_idx; - u1Byte Train_time; - u1Byte Train_time_flag; /*base on RSSI difference between two antennas*/ - RT_TIMER phydm_SwAntennaSwitchTimer; - u4Byte PktCnt_SWAntDivByCtrlFrame; - BOOLEAN bSWAntDivByCtrlFrame; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if USE_WORKITEM - RT_WORK_ITEM phydm_SwAntennaSwitchWorkitem; - #endif - #endif - - /* AntDect (Before link Antenna Switch check) need to be moved*/ - u2Byte Single_Ant_Counter; - u2Byte Dual_Ant_Counter; - u2Byte Aux_FailDetec_Counter; - u2Byte Retry_Counter; - u1Byte SWAS_NoLink_State; - u4Byte SWAS_NoLink_BK_Reg948; - BOOLEAN ANTA_ON; /*To indicate Ant A is or not*/ - BOOLEAN ANTB_ON; /*To indicate Ant B is on or not*/ - BOOLEAN Pre_Aux_FailDetec; - BOOLEAN RSSI_AntDect_bResult; - u1Byte Ant5G; - u1Byte Ant2G; - - -}SWAT_T, *pSWAT_T; - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -typedef struct _BF_DIV_COEX_ -{ - BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; - BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; - - u1Byte BDCcoexType_wBfer; - u1Byte num_Txbfee_Client; - u1Byte num_Txbfer_Client; - u1Byte BDC_Try_counter; - u1Byte BDC_Hold_counter; - u1Byte BDC_Mode; - u1Byte BDC_active_Mode; - u1Byte BDC_state; - u1Byte BDC_RxIdleUpdate_counter; - u1Byte num_Client; - u1Byte pre_num_Client; - u1Byte num_BfTar; - u1Byte num_DivTar; - - BOOLEAN bAll_DivSta_Idle; - BOOLEAN bAll_BFSta_Idle; - BOOLEAN BDC_Try_flag; - BOOLEAN BF_pass; - BOOLEAN DIV_pass; -}BDC_T,*pBDC_T; -#endif -#endif - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -typedef struct _SMART_ANTENNA_TRAINNING_ { - u4Byte latch_time; - BOOLEAN pkt_skip_statistic_en; - u4Byte fix_beam_pattern_en; - u4Byte fix_training_num_en; - u4Byte fix_beam_pattern_codeword; - u4Byte update_beam_codeword; - u4Byte ant_num; /*number of used smart beam antenna*/ - u4Byte ant_num_total;/*number of total smart beam antenna*/ - u4Byte first_train_ant; /*decide witch antenna to train first*/ - u4Byte rfu_codeword_table[4]; /*2G beam truth table*/ - u4Byte rfu_codeword_table_5g[4]; /*5G beam truth table*/ - u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ - u4Byte data_codeword_bit_num; - u1Byte per_beam_training_pkt_num; - u1Byte decision_holding_period; - u1Byte pkt_counter; - u4Byte fast_training_beam_num; - u4Byte pre_fast_training_beam_num; - u4Byte pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u1Byte beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u1Byte beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM]; - u4Byte pre_codeword; - BOOLEAN force_update_beam_en; - u4Byte beacon_counter; - u4Byte pre_beacon_counter; - u1Byte update_beam_idx; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM hl_smart_antenna_workitem; - RT_WORK_ITEM hl_smart_antenna_decision_workitem; - #endif - -} SAT_T, *pSAT_T; -#endif - -typedef struct _FAST_ANTENNA_TRAINNING_ -{ - u1Byte Bssid[6]; - u1Byte antsel_rx_keep_0; - u1Byte antsel_rx_keep_1; - u1Byte antsel_rx_keep_2; - u1Byte antsel_rx_keep_3; - u4Byte antSumRSSI[7]; - u4Byte antRSSIcnt[7]; - u4Byte antAveRSSI[7]; - u1Byte FAT_State; - u1Byte FAT_State_cnt; - u4Byte TrainIdx; - u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte RxIdleAnt; - u1Byte AntDiv_OnOff; - BOOLEAN bBecomeLinked; - u4Byte MinMaxRSSI; - u1Byte idx_AntDiv_counter_2G; - u1Byte idx_AntDiv_counter_5G; - u1Byte AntDiv_2G_5G; - u4Byte CCK_counter_main; - u4Byte CCK_counter_aux; - u4Byte OFDM_counter_main; - u4Byte OFDM_counter_aux; - - #ifdef ODM_EVM_ENHANCE_ANTDIV - - /*For 1SS RX phy rate*/ - u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - - /*For 2SS RX phy rate*/ - u4Byte MainAntEVM_2ss_Sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/ - u4Byte AuxAntEVM_2ss_Sum[ODM_ASSOCIATE_ENTRY_NUM][2]; - u4Byte MainAntEVM_2ss_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; /*2SS with A2+B*/ - u4Byte AuxAntEVM_2ss_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - - BOOLEAN EVM_method_enable; - u1Byte TargetAnt_EVM; - u1Byte TargetAnt_CRC32; - u8 target_ant_tp; - u1Byte TargetAnt_enhance; - u1Byte pre_TargetAnt_enhance; - u2Byte Main_MPDU_OK_cnt; - u2Byte Aux_MPDU_OK_cnt; - - u4Byte CRC32_Ok_Cnt; - u4Byte CRC32_Fail_Cnt; - u4Byte MainCRC32_Ok_Cnt; - u4Byte AuxCRC32_Ok_Cnt; - u4Byte MainCRC32_Fail_Cnt; - u4Byte AuxCRC32_Fail_Cnt; - - u4Byte antdiv_tp_main; - u4Byte antdiv_tp_aux; - u4Byte antdiv_tp_main_cnt; - u4Byte antdiv_tp_aux_cnt; - - u1Byte pre_antdiv_rssi; - u1Byte pre_antdiv_tp; - - #endif - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u4Byte CCK_CtrlFrame_Cnt_main; - u4Byte CCK_CtrlFrame_Cnt_aux; - u4Byte OFDM_CtrlFrame_Cnt_main; - u4Byte OFDM_CtrlFrame_Cnt_aux; - u4Byte MainAnt_CtrlFrame_Sum; - u4Byte AuxAnt_CtrlFrame_Sum; - u4Byte MainAnt_CtrlFrame_Cnt; - u4Byte AuxAnt_CtrlFrame_Cnt; - #endif - u1Byte b_fix_tx_ant; - BOOLEAN fix_ant_bfee; - BOOLEAN enable_ctrl_frame_antdiv; - BOOLEAN use_ctrl_frame_antdiv; - u1Byte hw_antsw_occur; - u1Byte *pForceTxAntByDesc; - u1Byte ForceTxAntByDesc; /*A temp value, will hook to driver team's outer parameter later*/ -}FAT_T,*pFAT_T; - - -//1 ============================================================ -//1 enumeration -//1 ============================================================ - - - -typedef enum _FAT_STATE /*Fast antenna training*/ -{ - FAT_BEFORE_LINK_STATE = 0, - FAT_PREPARE_STATE = 1, - FAT_TRAINING_STATE = 2, - FAT_DECISION_STATE = 3 -}FAT_STATE_E, *PFAT_STATE_E; - -typedef enum _ANT_DIV_TYPE -{ - NO_ANTDIV = 0xFF, - CG_TRX_HW_ANTDIV = 0x01, - CGCS_RX_HW_ANTDIV = 0x02, - FIXED_HW_ANTDIV = 0x03, - CG_TRX_SMART_ANTDIV = 0x04, - CGCS_RX_SW_ANTDIV = 0x05, - S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ - S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ - HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/ -}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; - - -//1 ============================================================ -//1 function prototype -//1 ============================================================ - - -VOID -ODM_StopAntennaSwitchDm( - IN PVOID pDM_VOID - ); - -VOID -phydm_enable_antenna_diversity( - IN PVOID pDM_VOID - ); - -VOID -ODM_SetAntConfig( - IN PVOID pDM_VOID, - IN u1Byte antSetting // 0=A, 1=B, 2=C, .... - ); - - -#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink - -VOID ODM_SwAntDivRestAfterLink( - IN PVOID pDM_VOID - ); - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - -VOID -ODM_UpdateRxIdleAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant -); - -#if (RTL8723B_SUPPORT == 1) -VOID -ODM_UpdateRxIdleAnt_8723B( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte DefaultAnt, - IN u4Byte OptionalAnt -); -#endif - -#if (RTL8188F_SUPPORT == 1) -VOID -phydm_update_rx_idle_antenna_8188F( - IN PVOID pDM_VOID, - IN u4Byte default_ant -); -#endif - -#if (RTL8723D_SUPPORT == 1) - -VOID -phydm_set_tx_ant_pwr_8723d( - IN PVOID pDM_VOID, - IN u1Byte Ant -); - -#endif - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_SW_AntDiv_Callback( - IN PRT_TIMER pTimer - ); - -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext - ); - - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext -); - -VOID -ODM_SW_AntDiv_Callback( - void *FunctionContext - ); - -#endif - -VOID -odm_S0S1_SwAntDivByCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte Step -); - -VOID -odm_AntselStatisticsOfCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte RxPWDBAll -); - -VOID -odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void -); - -#endif - -#ifdef ODM_EVM_ENHANCE_ANTDIV -VOID -odm_EVM_FastAntTrainingCallback( - IN PVOID pDM_VOID -); -#endif - -VOID -odm_HW_AntDiv( - IN PVOID pDM_VOID -); - -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_FastAntTraining( - IN PVOID pDM_VOID -); - -VOID -odm_FastAntTrainingCallback( - IN PVOID pDM_VOID -); - -VOID -odm_FastAntTrainingWorkItemCallback( - IN PVOID pDM_VOID -); -#endif - - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -phydm_beam_switch_workitem_callback( - IN PVOID pContext - ); - -VOID -phydm_beam_decision_workitem_callback( - IN PVOID pContext - ); - -#endif - -VOID -phydm_update_beam_pattern( - IN PVOID pDM_VOID, - IN u4Byte codeword, - IN u4Byte codeword_length - ); - -void -phydm_set_all_ant_same_beam_num( - IN PVOID pDM_VOID - ); - -VOID -phydm_hl_smart_ant_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -); - -#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ - -VOID -ODM_AntDivInit( - IN PVOID pDM_VOID -); - -VOID -ODM_AntDiv( - IN PVOID pDM_VOID -); - -VOID -odm_AntselStatistics( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN u1Byte antsel_tr_mux, - IN u4Byte MacId, - IN u4Byte utility, - IN u1Byte method, - IN u1Byte isCCKrate -); - -VOID -ODM_Process_RSSIForAntDiv( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void -); - - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -ODM_SetTxAntByTxInfo( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId -); - -#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) - -VOID -ODM_SetTxAntByTxInfo( - struct rtl8192cd_priv *priv, - struct tx_desc *pdesc, - unsigned short aid -); - -#if 1/*def def CONFIG_WLAN_HAL*/ -VOID -ODM_SetTxAntByTxInfo_HAL( - struct rtl8192cd_priv *priv, - PVOID pdesc_data, - u2Byte aid -); -#endif /*#ifdef CONFIG_WLAN_HAL*/ -#endif - - -VOID -ODM_AntDiv_Config( - IN PVOID pDM_VOID -); - -VOID -ODM_AntDivTimers( - IN PVOID pDM_VOID, - IN u1Byte state -); - -VOID -phydm_antdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -); - -#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ - -VOID -ODM_AntDivReset( - IN PVOID pDM_VOID -); - -VOID -odm_AntennaDiversityInit( - IN PVOID pDM_VOID -); - -VOID -odm_AntennaDiversity( - IN PVOID pDM_VOID -); - -#endif /*#ifndef __ODMANTDIV_H__*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ +/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ +/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, + because antenna diversity only works when BT is disable or radio off*/ +/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ +/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ +/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ +/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ +/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ +#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +#define ANTDIV_INIT 0xff +#define MAIN_ANT 1 /*Ant A or Ant Main or S1*/ +#define AUX_ANT 2 /*AntB or Ant Aux or S0*/ +#define MAX_ANT 3 /* 3 for AP using*/ + +#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ +/*smart antenna*/ +#define SUPPORT_RF_PATH_NUM 4 +#define SUPPORT_BEAM_PATTERN_NUM 4 +#define NUM_ANTENNA_8821A 2 + +#define NO_FIX_TX_ANT 0 +#define FIX_TX_AT_MAIN 1 +#define FIX_AUX_AT_MAIN 2 + +//Antenna Diversty Control Type +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) + +#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8197F) + +#define ODM_ANTDIV_2G BIT0 +#define ODM_ANTDIV_5G BIT1 + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define FAT_ON 1 +#define FAT_OFF 0 + +#define TX_BY_DESC 1 +#define TX_BY_REG 0 + +#define RSSI_METHOD 0 +#define EVM_METHOD 1 +#define CRC32_METHOD 2 +#define TP_METHOD 3 + +#define INIT_ANTDIV_TIMMER 0 +#define CANCEL_ANTDIV_TIMMER 1 +#define RELEASE_ANTDIV_TIMMER 2 + +#define CRC32_FAIL 1 +#define CRC32_OK 0 + +#define Evm_RSSI_TH_High 25 +#define Evm_RSSI_TH_Low 20 + +#define NORMAL_STATE_MIAN 1 +#define NORMAL_STATE_AUX 2 +#define TRAINING_STATE 3 + +#define FORCE_RSSI_DIFF 10 + +#define CSI_ON 1 +#define CSI_OFF 0 + +#define DIVON_CSIOFF 1 +#define DIVOFF_CSION 2 + +#define BDC_DIV_TRAIN_STATE 0 +#define BDC_BFer_TRAIN_STATE 1 +#define BDC_DECISION_STATE 2 +#define BDC_BF_HOLD_STATE 3 +#define BDC_DIV_HOLD_STATE 4 + +#define BDC_MODE_1 1 +#define BDC_MODE_2 2 +#define BDC_MODE_3 3 +#define BDC_MODE_4 4 +#define BDC_MODE_NULL 0xff + +/*SW S0S1 antenna diversity*/ +#define SWAW_STEP_INIT 0xff +#define SWAW_STEP_PEEK 0 +#define SWAW_STEP_DETERMINE 1 + +#define RSSI_CHECK_RESET_PERIOD 10 +#define RSSI_CHECK_THRESHOLD 50 + +/*Hong Lin Smart antenna*/ +#define HL_SMTANT_2WIRE_DATA_LEN 24 + +//1 ============================================================ +//1 structure +//1 ============================================================ + + +typedef struct _SW_Antenna_Switch_ +{ + u1Byte Double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte reset_idx; + u1Byte Train_time; + u1Byte Train_time_flag; /*base on RSSI difference between two antennas*/ + RT_TIMER phydm_SwAntennaSwitchTimer; + u4Byte PktCnt_SWAntDivByCtrlFrame; + BOOLEAN bSWAntDivByCtrlFrame; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM phydm_SwAntennaSwitchWorkitem; + #endif + #endif + + /* AntDect (Before link Antenna Switch check) need to be moved*/ + u2Byte Single_Ant_Counter; + u2Byte Dual_Ant_Counter; + u2Byte Aux_FailDetec_Counter; + u2Byte Retry_Counter; + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg948; + BOOLEAN ANTA_ON; /*To indicate Ant A is or not*/ + BOOLEAN ANTB_ON; /*To indicate Ant B is on or not*/ + BOOLEAN Pre_Aux_FailDetec; + BOOLEAN RSSI_AntDect_bResult; + u1Byte Ant5G; + u1Byte Ant2G; + + +}SWAT_T, *pSWAT_T; + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +typedef struct _BF_DIV_COEX_ +{ + BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; + BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + + u1Byte BDCcoexType_wBfer; + u1Byte num_Txbfee_Client; + u1Byte num_Txbfer_Client; + u1Byte BDC_Try_counter; + u1Byte BDC_Hold_counter; + u1Byte BDC_Mode; + u1Byte BDC_active_Mode; + u1Byte BDC_state; + u1Byte BDC_RxIdleUpdate_counter; + u1Byte num_Client; + u1Byte pre_num_Client; + u1Byte num_BfTar; + u1Byte num_DivTar; + + BOOLEAN bAll_DivSta_Idle; + BOOLEAN bAll_BFSta_Idle; + BOOLEAN BDC_Try_flag; + BOOLEAN BF_pass; + BOOLEAN DIV_pass; +}BDC_T,*pBDC_T; +#endif +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +typedef struct _SMART_ANTENNA_TRAINNING_ { + u4Byte latch_time; + BOOLEAN pkt_skip_statistic_en; + u4Byte fix_beam_pattern_en; + u4Byte fix_training_num_en; + u4Byte fix_beam_pattern_codeword; + u4Byte update_beam_codeword; + u4Byte ant_num; /*number of used smart beam antenna*/ + u4Byte ant_num_total;/*number of total smart beam antenna*/ + u4Byte first_train_ant; /*decide witch antenna to train first*/ + u4Byte rfu_codeword_table[4]; /*2G beam truth table*/ + u4Byte rfu_codeword_table_5g[4]; /*5G beam truth table*/ + u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ + u4Byte data_codeword_bit_num; + u1Byte per_beam_training_pkt_num; + u1Byte decision_holding_period; + u1Byte pkt_counter; + u4Byte fast_training_beam_num; + u4Byte pre_fast_training_beam_num; + u4Byte pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u1Byte beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u1Byte beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u4Byte pre_codeword; + BOOLEAN force_update_beam_en; + u4Byte beacon_counter; + u4Byte pre_beacon_counter; + u1Byte update_beam_idx; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + +} SAT_T, *pSAT_T; +#endif + +typedef struct _FAST_ANTENNA_TRAINNING_ +{ + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u1Byte antsel_rx_keep_3; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u1Byte FAT_State_cnt; + u4Byte TrainIdx; + u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte RxIdleAnt; + u1Byte AntDiv_OnOff; + BOOLEAN bBecomeLinked; + u4Byte MinMaxRSSI; + u1Byte idx_AntDiv_counter_2G; + u1Byte idx_AntDiv_counter_5G; + u1Byte AntDiv_2G_5G; + u4Byte CCK_counter_main; + u4Byte CCK_counter_aux; + u4Byte OFDM_counter_main; + u4Byte OFDM_counter_aux; + + #ifdef ODM_EVM_ENHANCE_ANTDIV + + /*For 1SS RX phy rate*/ + u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + /*For 2SS RX phy rate*/ + u4Byte MainAntEVM_2ss_Sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/ + u4Byte AuxAntEVM_2ss_Sum[ODM_ASSOCIATE_ENTRY_NUM][2]; + u4Byte MainAntEVM_2ss_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; /*2SS with A2+B*/ + u4Byte AuxAntEVM_2ss_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + BOOLEAN EVM_method_enable; + u1Byte TargetAnt_EVM; + u1Byte TargetAnt_CRC32; + u8 target_ant_tp; + u1Byte TargetAnt_enhance; + u1Byte pre_TargetAnt_enhance; + u2Byte Main_MPDU_OK_cnt; + u2Byte Aux_MPDU_OK_cnt; + + u4Byte CRC32_Ok_Cnt; + u4Byte CRC32_Fail_Cnt; + u4Byte MainCRC32_Ok_Cnt; + u4Byte AuxCRC32_Ok_Cnt; + u4Byte MainCRC32_Fail_Cnt; + u4Byte AuxCRC32_Fail_Cnt; + + u4Byte antdiv_tp_main; + u4Byte antdiv_tp_aux; + u4Byte antdiv_tp_main_cnt; + u4Byte antdiv_tp_aux_cnt; + + u1Byte pre_antdiv_rssi; + u1Byte pre_antdiv_tp; + + #endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u4Byte CCK_CtrlFrame_Cnt_main; + u4Byte CCK_CtrlFrame_Cnt_aux; + u4Byte OFDM_CtrlFrame_Cnt_main; + u4Byte OFDM_CtrlFrame_Cnt_aux; + u4Byte MainAnt_CtrlFrame_Sum; + u4Byte AuxAnt_CtrlFrame_Sum; + u4Byte MainAnt_CtrlFrame_Cnt; + u4Byte AuxAnt_CtrlFrame_Cnt; + #endif + u1Byte b_fix_tx_ant; + BOOLEAN fix_ant_bfee; + BOOLEAN enable_ctrl_frame_antdiv; + BOOLEAN use_ctrl_frame_antdiv; + u1Byte hw_antsw_occur; + u1Byte *pForceTxAntByDesc; + u1Byte ForceTxAntByDesc; /*A temp value, will hook to driver team's outer parameter later*/ +}FAT_T,*pFAT_T; + + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + + +typedef enum _FAT_STATE /*Fast antenna training*/ +{ + FAT_BEFORE_LINK_STATE = 0, + FAT_PREPARE_STATE = 1, + FAT_TRAINING_STATE = 2, + FAT_DECISION_STATE = 3 +}FAT_STATE_E, *PFAT_STATE_E; + +typedef enum _ANT_DIV_TYPE +{ + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ + S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ + HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/ +}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + + +//1 ============================================================ +//1 function prototype +//1 ============================================================ + + +VOID +ODM_StopAntennaSwitchDm( + IN PVOID pDM_VOID + ); + +VOID +phydm_enable_antenna_diversity( + IN PVOID pDM_VOID + ); + +VOID +ODM_SetAntConfig( + IN PVOID pDM_VOID, + IN u1Byte antSetting // 0=A, 1=B, 2=C, .... + ); + + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink + +VOID ODM_SwAntDivRestAfterLink( + IN PVOID pDM_VOID + ); + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + +VOID +ODM_UpdateRxIdleAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant +); + +#if (RTL8723B_SUPPORT == 1) +VOID +ODM_UpdateRxIdleAnt_8723B( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte DefaultAnt, + IN u4Byte OptionalAnt +); +#endif + +#if (RTL8188F_SUPPORT == 1) +VOID +phydm_update_rx_idle_antenna_8188F( + IN PVOID pDM_VOID, + IN u4Byte default_ant +); +#endif + +#if (RTL8723D_SUPPORT == 1) + +VOID +phydm_set_tx_ant_pwr_8723d( + IN PVOID pDM_VOID, + IN u1Byte Ant +); + +#endif + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + IN PRT_TIMER pTimer + ); + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext + ); + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +); + +VOID +ODM_SW_AntDiv_Callback( + void *FunctionContext + ); + +#endif + +VOID +odm_S0S1_SwAntDivByCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte Step +); + +VOID +odm_AntselStatisticsOfCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte RxPWDBAll +); + +VOID +odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV +VOID +odm_EVM_FastAntTrainingCallback( + IN PVOID pDM_VOID +); +#endif + +VOID +odm_HW_AntDiv( + IN PVOID pDM_VOID +); + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_FastAntTraining( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingCallback( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PVOID pDM_VOID +); +#endif + + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +phydm_beam_switch_workitem_callback( + IN PVOID pContext + ); + +VOID +phydm_beam_decision_workitem_callback( + IN PVOID pContext + ); + +#endif + +VOID +phydm_update_beam_pattern( + IN PVOID pDM_VOID, + IN u4Byte codeword, + IN u4Byte codeword_length + ); + +void +phydm_set_all_ant_same_beam_num( + IN PVOID pDM_VOID + ); + +VOID +phydm_hl_smart_ant_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +VOID +ODM_AntDivInit( + IN PVOID pDM_VOID +); + +VOID +ODM_AntDiv( + IN PVOID pDM_VOID +); + +VOID +odm_AntselStatistics( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte utility, + IN u1Byte method, + IN u1Byte isCCKrate +); + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId +); + +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +ODM_SetTxAntByTxInfo( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid +); + +#if 1/*def def CONFIG_WLAN_HAL*/ +VOID +ODM_SetTxAntByTxInfo_HAL( + struct rtl8192cd_priv *priv, + PVOID pdesc_data, + u2Byte aid +); +#endif /*#ifdef CONFIG_WLAN_HAL*/ +#endif + + +VOID +ODM_AntDiv_Config( + IN PVOID pDM_VOID +); + +VOID +ODM_AntDivTimers( + IN PVOID pDM_VOID, + IN u1Byte state +); + +VOID +phydm_antdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ + +VOID +ODM_AntDivReset( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversityInit( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversity( + IN PVOID pDM_VOID +); + +#endif /*#ifndef __ODMANTDIV_H__*/ diff --git a/package/kernel/rtl8192cd/phydm/phydm_beamforming.c b/package/kernel/rtl8192cd/phydm/phydm_beamforming.c index 1078cc906f9..8c4ef07776a 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_beamforming.c +++ b/package/kernel/rtl8192cd/phydm/phydm_beamforming.c @@ -1,1959 +1,1959 @@ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if WPP_SOFTWARE_TRACE -#include "phydm_beamforming.tmh" -#endif -#endif - -#if (BEAMFORMING_SUPPORT == 1) - -PRT_BEAMFORM_STAINFO -phydm_staInfoInit( - IN PDM_ODM_T pDM_Odm, - IN u2Byte staIdx - ) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORM_STAINFO pEntry = &(pBeamInfo->BeamformSTAinfo); - PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; - PADAPTER Adapter = pDM_Odm->Adapter; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); - PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo); - - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, Adapter->CurrentAddress, 6); - - pEntry->HtBeamformCap = pHTInfo->HtBeamformCap; - pEntry->VhtBeamformCap = pVHTInfo->VhtBeamformCap; - - /*IBSS, AP mode*/ - if (staIdx != 0) { - pEntry->AID = pSTA->AID; - pEntry->RA = pSTA->MacAddr; - pEntry->MacID = pSTA->AssociatedMacId; - pEntry->WirelessMode = pSTA->WirelessMode; - pEntry->BW = pSTA->BandWidth; - pEntry->CurBeamform = pSTA->HTInfo.HtCurBeamform; - } else {/*client mode*/ - pEntry->AID = pMgntInfo->mAId; - pEntry->RA = pMgntInfo->Bssid; - pEntry->MacID = pMgntInfo->mMacId; - pEntry->WirelessMode = pMgntInfo->dot11CurrentWirelessMode; - pEntry->BW = pMgntInfo->dot11CurrentChannelBandWidth; - pEntry->CurBeamform = pHTInfo->HtCurBeamform; - } - - if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { - if (staIdx != 0) - pEntry->CurBeamformVHT = pSTA->VHTInfo.VhtCurBeamform; - else - pEntry->CurBeamformVHT = pVHTInfo->VhtCurBeamform; - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->WirelessMode, staIdx)); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (!IS_STA_VALID(pSTA)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, staIdx)); - rtw_warn_on(1); - return pEntry; - } - - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, adapter_mac_addr(pSTA->padapter), 6); - pEntry->HtBeamformCap = pSTA->htpriv.beamform_cap; - - pEntry->AID = pSTA->aid; - pEntry->RA = pSTA->hwaddr; - pEntry->MacID = pSTA->mac_id; - pEntry->WirelessMode = pSTA->wireless_mode; - pEntry->BW = pSTA->bw_mode; - - pEntry->CurBeamform = pSTA->htpriv.beamform_cap; -#if ODM_IC_11AC_SERIES_SUPPORT - if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { - pEntry->CurBeamformVHT = pSTA->vhtpriv.beamform_cap; - pEntry->VhtBeamformCap = pSTA->vhtpriv.beamform_cap; - } -#endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->wireless_mode, staIdx)); -#endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pEntry->CurBeamform = 0x%x, pEntry->CurBeamformVHT = 0x%x\n", pEntry->CurBeamform, pEntry->CurBeamformVHT)); - return pEntry; - -} -void phydm_staInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u2Byte staIdx, - PRT_BEAMFORMEE_ENTRY pBeamformEntry - ) -{ - PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; - - if (!IS_STA_VALID(pSTA)) - return; - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - pSTA->txbf_paid = pBeamformEntry->P_AID; - pSTA->txbf_gid = pBeamformEntry->G_ID; -#endif -} - - -u1Byte -Beamforming_GetHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nr_index = 0; - u1Byte NDPTxRate; - /*Find Nr*/ - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); - else - Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); - - switch (Nr_index) { - case 1: - NDPTxRate = MGN_MCS8; - break; - - case 2: - NDPTxRate = MGN_MCS16; - break; - - case 3: - NDPTxRate = MGN_MCS24; - break; - - default: - NDPTxRate = MGN_MCS8; - break; - } - -return NDPTxRate; - -} - -u1Byte -Beamforming_GetVHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nr_index = 0; - u1Byte NDPTxRate; - /*Find Nr*/ - if (pDM_Odm->SupportICType & ODM_RTL8814A) - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); - else - Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); - - switch (Nr_index) { - case 1: - NDPTxRate = MGN_VHT2SS_MCS0; - break; - - case 2: - NDPTxRate = MGN_VHT3SS_MCS0; - break; - - case 3: - NDPTxRate = MGN_VHT4SS_MCS0; - break; - - default: - NDPTxRate = MGN_VHT2SS_MCS0; - break; - } - -return NDPTxRate; - -} - - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetBFeeEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte RA, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (eqMacAddr(RA, pBeamInfo->BeamformeeEntry[i].MacAddr))) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); - } - } - - return NULL; -} - -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetBFerEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte TA, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformerEntry[i].bUsed && (eqMacAddr(TA, pBeamInfo->BeamformerEntry[i].MacAddr))) { - *Idx = i; - return &(pBeamInfo->BeamformerEntry[i]); - } - } - - return NULL; -} - - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetEntryByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); - } - } - - return NULL; -} - - -BEAMFORMING_CAP -phydm_Beamforming_GetEntryBeamCapByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - BEAMFORMING_CAP BeamformEntryCap = BEAMFORMING_CAP_NONE; - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { - BeamformEntryCap = pBeamInfo->BeamformeeEntry[i].BeamformEntryCap; - i = BEAMFORMEE_ENTRY_NUM; - } - } - - return BeamformEntryCap; -} - - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetFreeBFeeEntry( - IN PVOID pDM_VOID, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed == FALSE) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); - } - } - return NULL; -} - -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetFreeBFerEntry( - IN PVOID pDM_VOID, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); - - for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformerEntry[i].bUsed == FALSE) { - *Idx = i; - return &(pBeamInfo->BeamformerEntry[i]); - } - } - return NULL; -} - -/* -// Description: Get the first entry index of MU Beamformee. -// -// Return Value: Index of the first MU sta. -// -// 2015.05.25. Created by tynli. -// -*/ -u1Byte -phydm_Beamforming_GetFirstMUBFeeEntryIdx( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte idx = 0xFF; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - BOOLEAN bFound = FALSE; - - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (pBeamInfo->BeamformeeEntry[idx].bUsed && pBeamInfo->BeamformeeEntry[idx].is_mu_sta) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); - bFound = TRUE; - break; - } - } - - if (!bFound) - idx = 0xFF; - - return idx; -} - - -/*Add SU BFee and MU BFee*/ -PRT_BEAMFORMEE_ENTRY -Beamforming_AddBFeeEntry( - IN PVOID pDM_VOID, - IN PRT_BEAMFORM_STAINFO pSTA, - IN BEAMFORMING_CAP BeamformCap, - IN u1Byte NumofSoundingDim, - IN u1Byte CompSteeringNumofBFer, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetFreeBFeeEntry(pDM_Odm, Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pEntry != NULL) { - pEntry->bUsed = TRUE; - pEntry->AID = pSTA->AID; - pEntry->MacId = pSTA->MacID; - pEntry->SoundBW = pSTA->BW; - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { - /*BSSID[44:47] xor BSSID[40:43]*/ - u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); - /*(dec(A) + dec(B)*32) mod 512*/ - pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; - pEntry->G_ID = 63; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, pEntry->P_AID)); - } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { - /*ad hoc mode*/ - pEntry->P_AID = 0; - pEntry->G_ID = 63; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, pEntry->P_AID)); - } else { - /*client mode*/ - pEntry->P_AID = pSTA->RA[5]; - /*BSSID[39:47]*/ - pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); - pEntry->G_ID = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); - } - cpMacAddr(pEntry->MacAddr, pSTA->RA); - pEntry->bTxBF = FALSE; - pEntry->bSound = FALSE; - pEntry->SoundPeriod = 400; - pEntry->BeamformEntryCap = BeamformCap; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - -/* pEntry->LogSeq = 0xff; Move to Beamforming_AddBFerEntry*/ -/* pEntry->LogRetryCnt = 0; Move to Beamforming_AddBFerEntry*/ -/* pEntry->LogSuccessCnt = 0; Move to Beamforming_AddBFerEntry*/ - - pEntry->LogStatusFailCnt = 0; - - pEntry->NumofSoundingDim = NumofSoundingDim; - pEntry->CompSteeringNumofBFer = CompSteeringNumofBFer; - - if (BeamformCap & BEAMFORMER_CAP_VHT_MU) { - pDM_Odm->BeamformingInfo.beamformee_mu_cnt += 1; - pEntry->is_mu_sta = TRUE; - pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); - } else if (BeamformCap & (BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - pDM_Odm->BeamformingInfo.beamformee_su_cnt += 1; - pEntry->is_mu_sta = FALSE; - } - - return pEntry; - } - else - return NULL; -} - -/*Add SU BFee and MU BFer*/ -PRT_BEAMFORMER_ENTRY -Beamforming_AddBFerEntry( - IN PVOID pDM_VOID, - IN PRT_BEAMFORM_STAINFO pSTA, - IN BEAMFORMING_CAP BeamformCap, - IN u1Byte NumofSoundingDim, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMER_ENTRY pEntry = phydm_Beamforming_GetFreeBFerEntry(pDM_Odm, Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pEntry != NULL) { - pEntry->bUsed = TRUE; - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { - /*BSSID[44:47] xor BSSID[40:43]*/ - u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); - - pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; - pEntry->G_ID = 63; - /*(dec(A) + dec(B)*32) mod 512*/ - } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { - pEntry->P_AID = 0; - pEntry->G_ID = 63; - } else { - pEntry->P_AID = pSTA->RA[5]; - /*BSSID[39:47]*/ - pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); - pEntry->G_ID = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); - } - - cpMacAddr(pEntry->MacAddr, pSTA->RA); - pEntry->BeamformEntryCap = BeamformCap; - - pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/ - pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/ - pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/ - pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/ - pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/ - - pEntry->NumofSoundingDim = NumofSoundingDim; - - if (BeamformCap & BEAMFORMEE_CAP_VHT_MU) { - pDM_Odm->BeamformingInfo.beamformer_mu_cnt += 1; - pEntry->is_mu_ap = TRUE; - pEntry->AID = pSTA->AID; - } else if (BeamformCap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - pDM_Odm->BeamformingInfo.beamformer_su_cnt += 1; - pEntry->is_mu_ap = FALSE; - } - - return pEntry; - } - else - return NULL; -} - -#if 0 -BOOLEAN -Beamforming_RemoveEntry( - IN PADAPTER Adapter, - IN pu1Byte RA, - OUT pu1Byte Idx - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, Idx); - PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, Idx); - BOOLEAN ret = FALSE; - - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pBFerEntry=0x%x\n", __func__, pBFerEntry)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pEntry=0x%x\n", __func__, pEntry)); - - if (pEntry != NULL) { - pEntry->bUsed = FALSE; - pEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - /*pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ - pEntry->bBeamformingInProgress = FALSE; - ret = TRUE; - } - if (pBFerEntry != NULL) { - pBFerEntry->bUsed = FALSE; - pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - ret = TRUE; - } - return ret; - -} -#endif - -/* Used for BeamformingStart_V1 */ -VOID -phydm_Beamforming_NDPARate( - IN PVOID pDM_VOID, - CHANNEL_WIDTH BW, - u1Byte Rate -) -{ - u2Byte NDPARate = Rate; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (NDPARate == 0) { - if(pDM_Odm->RSSI_Min > 30) // link RSSI > 30% - NDPARate = ODM_RATE24M; - else - NDPARate = ODM_RATE6M; - } - - if (NDPARate < ODM_RATEMCS0) - BW = (CHANNEL_WIDTH)ODM_BW20M; - - NDPARate = (NDPARate << 8) | BW; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); - -} - - -/* Used for BeamformingStart_SW and BeamformingStart_FW */ -VOID -phydm_Beamforming_DymNDPARate( - IN PVOID pDM_VOID -) -{ - u2Byte NDPARate = ODM_RATE6M, BW; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pDM_Odm->RSSI_Min > 30) /*link RSSI > 30%*/ - NDPARate = ODM_RATE24M; - else - NDPARate = ODM_RATE6M; - - BW = ODM_BW20M; - NDPARate = NDPARate << 8 | BW; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA Rate = 0x%X\n", __func__, NDPARate)); -} - -/* -* SW Sounding : SW Timer unit 1ms -* HW Timer unit (1/32000) s 32k is clock. -* FW Sounding : FW Timer unit 10ms -*/ -VOID -Beamforming_DymPeriod( - IN PVOID pDM_VOID, - IN u8 status -) -{ - u1Byte Idx; - BOOLEAN bChangePeriod = FALSE; - u2Byte SoundPeriod_SW, SoundPeriod_FW; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - PRT_BEAMFORMEE_ENTRY pBeamformEntry; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - //3 TODO per-client throughput caculation. - - if ((*(pDM_Odm->pCurrentTxTP) + *(pDM_Odm->pCurrentRxTP) > 2) && ((pEntry->LogStatusFailCnt <= 20) || status)) { - SoundPeriod_SW = 40; /* 40ms */ - SoundPeriod_FW = 40; /* From H2C cmd, unit = 10ms */ - } else { - SoundPeriod_SW = 4000;/* 4s */ - SoundPeriod_FW = 400; - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]SoundPeriod_SW=%d, SoundPeriod_FW=%d\n", __func__, SoundPeriod_SW, SoundPeriod_FW)); - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - if (pBeamformEntry->DefaultCSICnt > 20) { - /*Modified by David*/ - SoundPeriod_SW = 4000; - SoundPeriod_FW = 400; - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Period = %d\n", __func__, SoundPeriod_SW)); - if (pBeamformEntry->BeamformEntryCap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) { - if (pBeamformEntry->SoundPeriod != SoundPeriod_FW) { - pBeamformEntry->SoundPeriod = SoundPeriod_FW; - bChangePeriod = TRUE; /*Only FW sounding need to send H2C packet to change sound period. */ - } - } else if (pBeamformEntry->SoundPeriod != SoundPeriod_SW) { - pBeamformEntry->SoundPeriod = SoundPeriod_SW; - } - } - } - - if (bChangePeriod) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); -} - - - - -BOOLEAN -Beamforming_SendHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ) -{ - BOOLEAN ret = TRUE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (QIdx == BEACON_QUEUE) - ret = SendFWHTNDPAPacket(pDM_Odm, RA, BW); - else - ret = SendSWHTNDPAPacket(pDM_Odm, RA, BW); - - return ret; -} - - - -BOOLEAN -Beamforming_SendVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - HalComTxbf_Set(pDM_Odm, TXBF_SET_GET_TX_RATE, NULL); - - if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); - - } else { - if (QIdx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ - ret = SendFWVHTNDPAPacket(pDM_Odm, RA, AID, BW); - else { -#ifdef SUPPORT_MU_BF - #if (SUPPORT_MU_BF == 1) - pBeamInfo->is_mu_sounding = TRUE; - ret = SendSWVHTMUNDPAPacket(pDM_Odm, BW); - #else - pBeamInfo->is_mu_sounding = FALSE; - ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); - #endif -#else - pBeamInfo->is_mu_sounding = FALSE; - ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); -#endif - } - } - return ret; -} - - -BEAMFORMING_NOTIFY_STATE -phydm_beamfomring_bSounding( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - pu1Byte Idx - ) -{ - BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - /*if(( Beamforming_GetBeamCap(pBeamInfo) & BEAMFORMER_CAP) == 0)*/ - /*bSounding = BEAMFORMING_NOTIFY_RESET;*/ - if (BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER) - bSounding = BEAMFORMING_NOTIFY_RESET; - else { - u1Byte i; - - for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d bUsed=%d, bSound=%d\n", __func__, i, pBeamInfo->BeamformeeEntry[i].bUsed, pBeamInfo->BeamformeeEntry[i].bSound)); - if (pBeamInfo->BeamformeeEntry[i].bUsed && (!pBeamInfo->BeamformeeEntry[i].bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); - *Idx = i; - if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) - bSounding = BEAMFORMEE_NOTIFY_ADD_MU; - else - bSounding = BEAMFORMEE_NOTIFY_ADD_SU; - } - - if ((!pBeamInfo->BeamformeeEntry[i].bUsed) && pBeamInfo->BeamformeeEntry[i].bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); - *Idx = i; - if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) - bSounding = BEAMFORMEE_NOTIFY_DELETE_MU; - else - bSounding = BEAMFORMEE_NOTIFY_DELETE_SU; - } - } - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, bSounding = %d\n", __func__, bSounding)); - return bSounding; -} - - -//This function is unused -u1Byte -phydm_beamforming_SoundingIdx( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo - ) -{ - u1Byte Idx = 0; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || - BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) - Idx = BeamOidInfo.SoundOidIdx; - else { - u1Byte i; - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (FALSE == pBeamInfo->BeamformeeEntry[i].bSound)) { - Idx = i; - break; - } - } - } - - return Idx; -} - - -SOUNDING_MODE -phydm_beamforming_SoundingMode( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - u1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte SupportInterface = pDM_Odm->SupportInterface; - - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - SOUNDING_MODE Mode = BeamOidInfo.SoundOidMode; - - if (BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) { - if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Mode = BeamOidInfo.SoundOidMode; - else - Mode = SOUNDING_STOP_All_TIMER; - } else if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER) { - if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) - Mode = BeamOidInfo.SoundOidMode; - else - Mode = SOUNDING_STOP_All_TIMER; - } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) { - if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) - Mode = SOUNDING_FW_VHT_TIMER; - else - Mode = SOUNDING_SW_VHT_TIMER; - } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) { - if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) - Mode = SOUNDING_FW_HT_TIMER; - else - Mode = SOUNDING_SW_HT_TIMER; - } else - Mode = SOUNDING_STOP_All_TIMER; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SupportInterface=%d, Mode=%d\n", __func__, SupportInterface, Mode)); - - return Mode; -} - - -u2Byte -phydm_beamforming_SoundingTime( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - SOUNDING_MODE Mode, - u1Byte Idx - ) -{ - u2Byte SoundingTime = 0xffff; - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) - SoundingTime = BeamOidInfo.SoundOidPeriod * 32; - else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) - /*Modified by David*/ - SoundingTime = BeamEntry.SoundPeriod; /*BeamOidInfo.SoundOidPeriod;*/ - else - SoundingTime = BeamEntry.SoundPeriod; - - return SoundingTime; -} - - -CHANNEL_WIDTH -phydm_beamforming_SoundingBW( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - SOUNDING_MODE Mode, - u1Byte Idx - ) -{ - CHANNEL_WIDTH SoundingBW = CHANNEL_WIDTH_20; - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) - SoundingBW = BeamOidInfo.SoundOidBW; - else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) - /*Modified by David*/ - SoundingBW = BeamEntry.SoundBW; /*BeamOidInfo.SoundOidBW;*/ - else - SoundingBW = BeamEntry.SoundBW; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, SoundingBW=0x%X\n", __func__, SoundingBW)); - - return SoundingBW; -} - - -BOOLEAN -phydm_Beamforming_SelectBeamEntry( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo - ) -{ - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*pEntry.bSound is different between first and latter NDPA, and should not be used as BFee entry selection*/ - /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed SoundIdx.*/ - pSoundInfo->SoundIdx = phydm_beamforming_SoundingIdx(pDM_Odm, pBeamInfo); - /*pSoundInfo->SoundIdx = 0;*/ - - if (pSoundInfo->SoundIdx < BEAMFORMEE_ENTRY_NUM) - pSoundInfo->SoundMode = phydm_beamforming_SoundingMode(pDM_Odm, pBeamInfo, pSoundInfo->SoundIdx); - else - pSoundInfo->SoundMode = SOUNDING_STOP_All_TIMER; - - if (SOUNDING_STOP_All_TIMER == pSoundInfo->SoundMode) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of SOUNDING_STOP_All_TIMER\n", __func__)); - return FALSE; - } else { - pSoundInfo->SoundBW = phydm_beamforming_SoundingBW(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); - pSoundInfo->SoundPeriod = phydm_beamforming_SoundingTime(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); - return TRUE; - } -} - -/*SU BFee Entry Only*/ -BOOLEAN -phydm_beamforming_StartPeriod( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - BOOLEAN Ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - phydm_Beamforming_DymNDPARate(pDM_Odm); - - phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); // Modified - - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); - else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || - pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) { - HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; - u4Byte val = (pSoundInfo->SoundPeriod | (TimerType<<16)); - - //HW timer stop: All IC has the same setting - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); - //ODM_Write1Byte(pDM_Odm, 0x15F, 0); - //HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_INIT, (pu1Byte)(&val)); - //ODM_Write1Byte(pDM_Odm, 0x164, 1); - //ODM_Write4Byte(pDM_Odm, 0x15C, val); - //HW timer start: All IC has the same setting - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_START, (pu1Byte)(&TimerType)); - //ODM_Write1Byte(pDM_Odm, 0x15F, 0x5); - } else if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) - Ret = BeamformingStart_FW(pDM_Odm, pSoundInfo->SoundIdx); - else - Ret = FALSE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SoundIdx=%d, SoundMode=%d, SoundBW=%d, SoundPeriod=%d\n", __func__, - pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW, pSoundInfo->SoundPeriod)); - - return Ret; -} - -// Used after Beamforming_Leave, and will clear the setting of the "already deleted" entry -/*SU BFee Entry Only*/ -VOID -phydm_beamforming_EndPeriod_SW( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); - else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || - pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) - /*HW timer stop: All IC has the same setting*/ - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); - /*ODM_Write1Byte(pDM_Odm, 0x15F, 0);*/ -} - -VOID -phydm_beamforming_EndPeriod_FW( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); -} - - -/*SU BFee Entry Only*/ -VOID -phydm_beamforming_ClearEntry_SW( - IN PVOID pDM_VOID, - BOOLEAN IsDelete, - u1Byte DeleteIdx - ) -{ - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - if (IsDelete) { - if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { - pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; - if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW DeleteIdx is wrong!!!!!\n", __func__)); - return; - } - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, DeleteIdx)); - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) { - pBeamformEntry->bBeamformingInProgress = FALSE; - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - } else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&DeleteIdx); - } - pBeamformEntry->bSound = FALSE; - } else { - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ - /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ - - if (pBeamformEntry->bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, Idx)); - /* - * If End procedure is - * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. - * - * 2. After C2H packet, then reset state to initialized and clear status bit. - */ - - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - phydm_Beamforming_End_SW(pDM_Odm, 0); - else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); - } - - pBeamformEntry->bSound = FALSE; - } - } - } -} - -VOID -phydm_beamforming_ClearEntry_FW( - IN PVOID pDM_VOID, - BOOLEAN IsDelete, - u1Byte DeleteIdx - ) -{ - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - if (IsDelete) { - if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { - pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; - - if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW DeleteIdx is wrong!!!!!\n", __func__)); - return; - } - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, DeleteIdx)); - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - pBeamformEntry->bSound = FALSE; - } else { - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ - /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ - - if (pBeamformEntry->bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, Idx)); - /* - * If End procedure is - * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. - * - * 2. After C2H packet, then reset state to initialized and clear status bit. - */ - - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - pBeamformEntry->bSound = FALSE; - } - } - } -} - -/* -* Called : -* 1. Add and delete entry : Beamforming_Enter/Beamforming_Leave -* 2. FW trigger : Beamforming_SetTxBFen -* 3. Set OID_RT_BEAMFORMING_PERIOD : BeamformingControl_V2 -*/ -VOID -phydm_Beamforming_Notify( - IN PVOID pDM_VOID - ) -{ - u1Byte Idx=BEAMFORMEE_ENTRY_NUM; - BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - bSounding = phydm_beamfomring_bSounding(pDM_Odm, pBeamInfo, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, bSounding=%d, Idx=%d\n", __func__, bSounding, Idx)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: pBeamInfo->beamformee_su_cnt = %d\n", __func__, pBeamInfo->beamformee_su_cnt)); - - - switch (bSounding) { - case BEAMFORMEE_NOTIFY_ADD_SU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); - phydm_beamforming_StartPeriod(pDM_Odm); - break; - - case BEAMFORMEE_NOTIFY_DELETE_SU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); - if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_ClearEntry_FW(pDM_Odm, TRUE, Idx); - if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_EndPeriod_FW(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); - } - } else { - phydm_beamforming_ClearEntry_SW(pDM_Odm, TRUE, Idx); - if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_EndPeriod_SW(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); - } - } - break; - - case BEAMFORMEE_NOTIFY_ADD_MU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); - if (pBeamInfo->beamformee_mu_cnt == 2) { - /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod);*/ - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, 1000); /*Do MU sounding every 1sec*/ - } else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); - break; - - case BEAMFORMEE_NOTIFY_DELETE_MU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); - if (pBeamInfo->beamformee_mu_cnt == 1) { - /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER)*/{ - ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); - } - } - break; - - case BEAMFORMING_NOTIFY_RESET: - if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_ClearEntry_FW(pDM_Odm, FALSE, Idx); - phydm_beamforming_EndPeriod_FW(pDM_Odm); - } else { - phydm_beamforming_ClearEntry_SW(pDM_Odm, FALSE, Idx); - phydm_beamforming_EndPeriod_SW(pDM_Odm); - } - - break; - - default: - break; - } - -} - - - -BOOLEAN -Beamforming_InitEntry( - IN PVOID pDM_VOID, - IN u2Byte staIdx, - pu1Byte BFerBFeeIdx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; - PRT_BEAMFORM_STAINFO pSTA = NULL; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - u1Byte BFerIdx=0xF, BFeeIdx=0xF; - u1Byte NumofSoundingDim = 0, CompSteeringNumofBFer = 0; - - pSTA = phydm_staInfoInit(pDM_Odm, staIdx); - - /*The current setting does not support Beaforming*/ - if (BEAMFORMING_CAP_NONE == pSTA->HtBeamformCap && BEAMFORMING_CAP_NONE == pSTA->VhtBeamformCap) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); - return FALSE; - } - - if (pSTA->WirelessMode < WIRELESS_MODE_N_24G) - return FALSE; - else { - if (pSTA->WirelessMode & WIRELESS_MODE_N_5G || pSTA->WirelessMode & WIRELESS_MODE_N_24G) {/*HT*/ - if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_HT_EXPLICIT); - NumofSoundingDim = (pSTA->CurBeamform&BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP)>>6; - } - /*We are Beamformer because the STA is Beamformee*/ - if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || - TEST_FLAG(pSTA->HtBeamformCap, BEAMFORMING_HT_BEAMFORMER_TEST)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_HT_EXPLICIT); - CompSteeringNumofBFer = (pSTA->CurBeamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM)>>4; - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT CurBeamform=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamform, BeamformCap)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT NumofSoundingDim=%d, CompSteeringNumofBFer=%d\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); - } -#if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (pSTA->WirelessMode & WIRELESS_MODE_AC_5G || pSTA->WirelessMode & WIRELESS_MODE_AC_24G) { /*VHT*/ - - /* We are Beamformee because the STA is SU Beamformer*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { - BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMEE_CAP_VHT_SU); - NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; - } - /* We are Beamformer because the STA is SU Beamformee*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || - TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMER_CAP_VHT_SU); - CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; - } - /* We are Beamformee because the STA is MU Beamformer*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_VHT_MU); - NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; - } - /* We are Beamformer because the STA is MU Beamformee*/ - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { /* Only AP mode supports to act an MU beamformer */ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || - TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_VHT_MU); - CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; - } - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT CurBeamformVHT=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamformVHT, BeamformCap)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT NumofSoundingDim=0x%X, CompSteeringNumofBFer=0x%X\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); - - } -#endif - } - - - if(BeamformCap == BEAMFORMING_CAP_NONE) - return FALSE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, BeamformCap)); - - /*We are BFee, so the entry is BFer*/ - if (BeamformCap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, pSTA->RA, &BFerIdx); - - if (pBeamformerEntry == NULL) { - pBeamformerEntry = Beamforming_AddBFerEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim , &BFerIdx); - if (pBeamformerEntry == NULL) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); - } - } - - /*We are BFer, so the entry is BFee*/ - if (BeamformCap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, pSTA->RA, &BFeeIdx); - - /*¦pªGBFeeIdx = 0xF «h¥Nªí¥Ø«eentry·í¤¤¨S¦³¬Û¦PªºMACID¦b¤º*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, BFeeIdx)); - if (pBeamformEntry == NULL) { - pBeamformEntry = Beamforming_AddBFeeEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim, CompSteeringNumofBFer, &BFeeIdx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: pSTA->AID=%d, pSTA->MacID=%d\n", __func__, pSTA->AID, pSTA->MacID)); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, BFeeIdx)); - - if (pBeamformEntry == NULL) - return FALSE; - else - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; - } else { - /*Entry has been created. If entry is initialing or progressing then errors occur.*/ - if (pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && - pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - return FALSE; - } else - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; - } - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - phydm_staInfoUpdate(pDM_Odm, staIdx, pBeamformEntry); - } - - *BFerBFeeIdx = (BFerIdx<<4) | BFeeIdx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: BFerIdx=0x%X, BFeeIdx=0x%X, BFerBFeeIdx=0x%X\n", __func__, BFerIdx, BFeeIdx, *BFerBFeeIdx)); - - return TRUE; -} - - -VOID -Beamforming_DeInitEntry( - IN PVOID pDM_VOID, - pu1Byte RA - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - - PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, &Idx); - PRT_BEAMFORMEE_ENTRY pBFeeEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - BOOLEAN ret = FALSE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pBFeeEntry != NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFeeEntry\n", __func__)); - pBFeeEntry->bUsed = FALSE; - pBFeeEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - pBFeeEntry->bBeamformingInProgress = FALSE; - if (pBFeeEntry->is_mu_sta) { - pDM_Odm->BeamformingInfo.beamformee_mu_cnt -= 1; - pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); - } else { - pDM_Odm->BeamformingInfo.beamformee_su_cnt -= 1; - } - ret = TRUE; - } - - if (pBFerEntry != NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFerEntry\n", __func__)); - pBFerEntry->bUsed = FALSE; - pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - if (pBFerEntry->is_mu_ap) - pDM_Odm->BeamformingInfo.beamformer_mu_cnt -= 1; - else - pDM_Odm->BeamformingInfo.beamformer_su_cnt -= 1; - ret = TRUE; - } - - if (ret == TRUE) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_LEAVE, (pu1Byte)&Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, Idx = 0x%X\n", __func__, Idx)); -} - - -BOOLEAN -BeamformingStart_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - BOOLEAN Mode, - CHANNEL_WIDTH BW, - u1Byte Rate - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pEntry; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - if (pEntry->bUsed == FALSE) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } else { - if (pEntry->bBeamformingInProgress) - return FALSE; - - pEntry->bBeamformingInProgress = TRUE; - - if (Mode == 1) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } - } else if (Mode == 0) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } - } - - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } else { - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; - } - } - - pEntry->SoundBW = BW; - pBeamInfo->BeamformeeCurIdx = Idx; - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); - - if (Mode == 1) - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); - else - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, pEntry->AID, BW, NORMAL_QUEUE); - - if (ret == FALSE) { - Beamforming_Leave(pDM_Odm, RA); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Idx %d\n", __func__, Idx)); - return TRUE; -} - - -BOOLEAN -BeamformingStart_SW( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, - CHANNEL_WIDTH BW - ) -{ - pu1Byte RA = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - if (pBeamInfo->is_mu_sounding) { - pBeamInfo->is_mu_sounding_in_progress = TRUE; - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); - RA = pEntry->MacAddr; - - } else { - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); - - if (pEntry->bUsed == FALSE) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } else { - if (pEntry->bBeamformingInProgress) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, skip...\n")); - return FALSE; - } - - pEntry->bBeamformingInProgress = TRUE; - RA = pEntry->MacAddr; - - if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); - return FALSE; - } - } else if (Mode == SOUNDING_SW_VHT_TIMER || Mode == SOUNDING_HW_VHT_TIMER || Mode == SOUNDING_AUTO_VHT_TIMER) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); - return FALSE; - } - } - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect BeamformEntryState(%d) <==\n", __func__, pEntry->BeamformEntryState)); - return FALSE; - } else { - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; - } - } - - pBeamInfo->BeamformeeCurIdx = Idx; - } - - /*2014.12.22 Luke: Need to be checked*/ - /*GET_TXBF_INFO(Adapter)->fTxbfSet(Adapter, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx);*/ - - if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA , BW, NORMAL_QUEUE); - else - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA , pEntry->AID, BW, NORMAL_QUEUE); - - if (ret == FALSE) { - Beamforming_Leave(pDM_Odm, RA); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; - } - - - /*-------------------------- - // Send BF Report Poll for MU BF - --------------------------*/ -#ifdef SUPPORT_MU_BF -#if (SUPPORT_MU_BF == 1) -{ - u1Byte idx, PollSTACnt = 0; - BOOLEAN bGetFirstBFee = FALSE; - - if (pBeamInfo->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ - - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - if (bGetFirstBFee) { - PollSTACnt++; - if (PollSTACnt == (pBeamInfo->beamformee_mu_cnt - 1))/* The last STA*/ - SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, TRUE); - else - SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, FALSE); - } else { - bGetFirstBFee = TRUE; - } - } - } - } -} -#endif -#endif - return TRUE; -} - - -BOOLEAN -BeamformingStart_FW( - IN PVOID pDM_VOID, - u1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); - if (pEntry->bUsed == FALSE) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); - return FALSE; - } - - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, Idx=0x%X\n", __func__, Idx)); - return TRUE; -} - -VOID -Beamforming_CheckSoundingSuccess( - IN PVOID pDM_VOID, - BOOLEAN Status -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); - - if (Status == 1) { - if (pEntry->LogStatusFailCnt == 21) - Beamforming_DymPeriod(pDM_Odm, Status); - pEntry->LogStatusFailCnt = 0; - } else if (pEntry->LogStatusFailCnt <= 20) { - pEntry->LogStatusFailCnt++; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); - } - if (pEntry->LogStatusFailCnt > 20) { - pEntry->LogStatusFailCnt = 21; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __func__)); - Beamforming_DymPeriod(pDM_Odm, Status); - } -} - -VOID -phydm_Beamforming_End_SW( - IN PVOID pDM_VOID, - BOOLEAN Status - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - if (pBeamInfo->is_mu_sounding) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); - pBeamInfo->is_mu_sounding_in_progress = FALSE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - } else { - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSING) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, pEntry->BeamformEntryState)); - return; - } - - if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - } else if (Status == 1) { - pEntry->LogStatusFailCnt = 0; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - } else { - pEntry->LogStatusFailCnt++; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_TX_PATH_RESET, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); - } - - if (pEntry->LogStatusFailCnt > 50) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 50, Stop SOUNDING\n", __func__)); - pEntry->bSound = FALSE; - Beamforming_DeInitEntry(pDM_Odm, pEntry->MacAddr); - - /*Modified by David - Every action of deleting entry should follow by Notify*/ - phydm_Beamforming_Notify(pDM_Odm); - } - - pEntry->bBeamformingInProgress = FALSE; - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Status=%d\n", __func__, Status)); -} - - -VOID -Beamforming_TimerCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PVOID pDM_VOID -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - IN PVOID pContext -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = (PADAPTER)pContext; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif - BOOLEAN ret = FALSE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - BOOLEAN bBeamformingInProgress; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pBeamInfo->is_mu_sounding) - bBeamformingInProgress = pBeamInfo->is_mu_sounding_in_progress; - else - bBeamformingInProgress = pEntry->bBeamformingInProgress; - - if (bBeamformingInProgress) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, reset it\n")); - phydm_Beamforming_End_SW(pDM_Odm, 0); - } - - ret = phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); -#if (SUPPORT_MU_BF == 1) - if (ret && pBeamInfo->beamformee_mu_cnt > 1) - ret = 1; - else - ret = 0; -#endif - if (ret) - ret = BeamformingStart_SW(pDM_Odm, pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW); - else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); - - if ((pBeamInfo->beamformee_su_cnt != 0) || (pBeamInfo->beamformee_mu_cnt > 1)) { - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); - else { - u4Byte val = (pSoundInfo->SoundPeriod << 16) | HAL_TIMER_TXBF; - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_RESTART, (pu1Byte)(&val)); - } - } -} - - -VOID -Beamforming_SWTimerCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PRT_TIMER pTimer -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - void *FunctionContext -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - Beamforming_TimerCallback(pDM_Odm); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)FunctionContext; - PADAPTER Adapter = pDM_Odm->Adapter; - - if (Adapter->net_closed == TRUE) - return; - rtw_run_in_thread_cmd(Adapter, Beamforming_TimerCallback, Adapter); -#endif - -} - - -VOID -phydm_Beamforming_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); - - pBeamOidInfo->SoundOidMode = SOUNDING_STOP_OID_TIMER; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Mode (%d)\n", __func__, pBeamOidInfo->SoundOidMode)); - - pBeamInfo->beamformee_su_cnt = 0; - pBeamInfo->beamformer_su_cnt = 0; - pBeamInfo->beamformee_mu_cnt = 0; - pBeamInfo->beamformer_mu_cnt = 0; - pBeamInfo->beamformee_mu_reg_maping = 0; - pBeamInfo->mu_ap_index = 0; - pBeamInfo->is_mu_sounding = FALSE; - pBeamInfo->FirstMUBFeeIndex = 0xFF; - pBeamInfo->applyVmatrix = TRUE; - pBeamInfo->snding3SS = FALSE; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pBeamInfo->SourceAdapter = pDM_Odm->Adapter; -#endif - halComTxbf_beamformInit(pDM_Odm); -} - - -BOOLEAN -phydm_actingDetermine( - IN PVOID pDM_VOID, - IN PHYDM_ACTING_TYPE type - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = FALSE; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->BeamformingInfo.SourceAdapter; -#else - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (type == PhyDM_ACTING_AS_AP) - ret = ACTING_AS_AP(Adapter); - else if (type == PhyDM_ACTING_AS_IBSS) - ret = ACTING_AS_IBSS(Adapter); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - - if (type == PhyDM_ACTING_AS_AP) - ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); - else if (type == PhyDM_ACTING_AS_IBSS) - ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); -#endif - - return ret; - -} - -VOID -Beamforming_Enter( - IN PVOID pDM_VOID, - IN u2Byte staIdx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte BFerBFeeIdx = 0xff; - - if (Beamforming_InitEntry(pDM_Odm, staIdx, &BFerBFeeIdx)) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_ENTER, (pu1Byte)&BFerBFeeIdx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); -} - - -VOID -Beamforming_Leave( - IN PVOID pDM_VOID, - pu1Byte RA - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (RA != NULL) { - Beamforming_DeInitEntry(pDM_Odm, RA); - phydm_Beamforming_Notify(pDM_Odm); - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); -} - -#if 0 -//Nobody calls this function -VOID -phydm_Beamforming_SetTxBFen( - IN PVOID pDM_VOID, - u1Byte MacId, - BOOLEAN bTxBF - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pEntry; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - pEntry = phydm_Beamforming_GetEntryByMacId(pDM_Odm, MacId, &Idx); - - if(pEntry == NULL) - return; - else - pEntry->bTxBF = bTxBF; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s MacId %d TxBF %d\n", __func__, pEntry->MacId, pEntry->bTxBF)); - - phydm_Beamforming_Notify(pDM_Odm); -} -#endif - -BEAMFORMING_CAP -phydm_Beamforming_GetBeamCap( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo - ) -{ - u1Byte i; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - BeamformeeEntry = pBeamInfo->BeamformeeEntry[i]; - - if (BeamformeeEntry.bUsed) { - bSelfBeamformer = TRUE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d bUsed=TRUE\n", __func__, i)); - break; - } - } - - for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - BeamformerEntry = pBeamInfo->BeamformerEntry[i]; - - if (BeamformerEntry.bUsed) { - bSelfBeamformee = TRUE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d bUsed=TRUE\n", __func__, i)); - break; - } - } - - if (bSelfBeamformer) - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP); - if (bSelfBeamformee) - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP); - - return BeamformCap; -} - - -BOOLEAN -BeamformingControl_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - u1Byte AID, - u1Byte Mode, - CHANNEL_WIDTH BW, - u1Byte Rate - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = TRUE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), Mode (%d), BW (%d)\n", AID, Mode, BW)); - - switch (Mode) { - case 0: - ret = BeamformingStart_V1(pDM_Odm, RA, 0, BW, Rate); - break; - case 1: - ret = BeamformingStart_V1(pDM_Odm, RA, 1, BW, Rate); - break; - case 2: - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, AID, BW, NORMAL_QUEUE); - break; - case 3: - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); - break; - } - return ret; -} - -/*Only OID uses this function*/ -BOOLEAN -phydm_BeamformingControl_V2( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, - CHANNEL_WIDTH BW, - u2Byte Period - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Idx (%d), Mode (%d), BW (%d), Period (%d)\n", Idx, Mode, BW, Period)); - - pBeamOidInfo->SoundOidIdx = Idx; - pBeamOidInfo->SoundOidMode = (SOUNDING_MODE) Mode; - pBeamOidInfo->SoundOidBW = BW; - pBeamOidInfo->SoundOidPeriod = Period; - - phydm_Beamforming_Notify(pDM_Odm); - - return TRUE; -} - - -VOID -phydm_Beamforming_Watchdog( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); - - if (pBeamInfo->beamformee_su_cnt == 0) - return; - - Beamforming_DymPeriod(pDM_Odm,0); - phydm_Beamforming_DymNDPARate(pDM_Odm); - -} - - -#endif +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if WPP_SOFTWARE_TRACE +#include "phydm_beamforming.tmh" +#endif +#endif + +#if (BEAMFORMING_SUPPORT == 1) + +PRT_BEAMFORM_STAINFO +phydm_staInfoInit( + IN PDM_ODM_T pDM_Odm, + IN u2Byte staIdx + ) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORM_STAINFO pEntry = &(pBeamInfo->BeamformSTAinfo); + PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; + PADAPTER Adapter = pDM_Odm->Adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); + PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo); + + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, Adapter->CurrentAddress, 6); + + pEntry->HtBeamformCap = pHTInfo->HtBeamformCap; + pEntry->VhtBeamformCap = pVHTInfo->VhtBeamformCap; + + /*IBSS, AP mode*/ + if (staIdx != 0) { + pEntry->AID = pSTA->AID; + pEntry->RA = pSTA->MacAddr; + pEntry->MacID = pSTA->AssociatedMacId; + pEntry->WirelessMode = pSTA->WirelessMode; + pEntry->BW = pSTA->BandWidth; + pEntry->CurBeamform = pSTA->HTInfo.HtCurBeamform; + } else {/*client mode*/ + pEntry->AID = pMgntInfo->mAId; + pEntry->RA = pMgntInfo->Bssid; + pEntry->MacID = pMgntInfo->mMacId; + pEntry->WirelessMode = pMgntInfo->dot11CurrentWirelessMode; + pEntry->BW = pMgntInfo->dot11CurrentChannelBandWidth; + pEntry->CurBeamform = pHTInfo->HtCurBeamform; + } + + if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { + if (staIdx != 0) + pEntry->CurBeamformVHT = pSTA->VHTInfo.VhtCurBeamform; + else + pEntry->CurBeamformVHT = pVHTInfo->VhtCurBeamform; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->WirelessMode, staIdx)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (!IS_STA_VALID(pSTA)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, staIdx)); + rtw_warn_on(1); + return pEntry; + } + + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, adapter_mac_addr(pSTA->padapter), 6); + pEntry->HtBeamformCap = pSTA->htpriv.beamform_cap; + + pEntry->AID = pSTA->aid; + pEntry->RA = pSTA->hwaddr; + pEntry->MacID = pSTA->mac_id; + pEntry->WirelessMode = pSTA->wireless_mode; + pEntry->BW = pSTA->bw_mode; + + pEntry->CurBeamform = pSTA->htpriv.beamform_cap; +#if ODM_IC_11AC_SERIES_SUPPORT + if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { + pEntry->CurBeamformVHT = pSTA->vhtpriv.beamform_cap; + pEntry->VhtBeamformCap = pSTA->vhtpriv.beamform_cap; + } +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->wireless_mode, staIdx)); +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pEntry->CurBeamform = 0x%x, pEntry->CurBeamformVHT = 0x%x\n", pEntry->CurBeamform, pEntry->CurBeamformVHT)); + return pEntry; + +} +void phydm_staInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u2Byte staIdx, + PRT_BEAMFORMEE_ENTRY pBeamformEntry + ) +{ + PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; + + if (!IS_STA_VALID(pSTA)) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + pSTA->txbf_paid = pBeamformEntry->P_AID; + pSTA->txbf_gid = pBeamformEntry->G_ID; +#endif +} + + +u1Byte +Beamforming_GetHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nr_index = 0; + u1Byte NDPTxRate; + /*Find Nr*/ + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); + else + Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); + + switch (Nr_index) { + case 1: + NDPTxRate = MGN_MCS8; + break; + + case 2: + NDPTxRate = MGN_MCS16; + break; + + case 3: + NDPTxRate = MGN_MCS24; + break; + + default: + NDPTxRate = MGN_MCS8; + break; + } + +return NDPTxRate; + +} + +u1Byte +Beamforming_GetVHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nr_index = 0; + u1Byte NDPTxRate; + /*Find Nr*/ + if (pDM_Odm->SupportICType & ODM_RTL8814A) + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); + else + Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); + + switch (Nr_index) { + case 1: + NDPTxRate = MGN_VHT2SS_MCS0; + break; + + case 2: + NDPTxRate = MGN_VHT3SS_MCS0; + break; + + case 3: + NDPTxRate = MGN_VHT4SS_MCS0; + break; + + default: + NDPTxRate = MGN_VHT2SS_MCS0; + break; + } + +return NDPTxRate; + +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetBFeeEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte RA, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (eqMacAddr(RA, pBeamInfo->BeamformeeEntry[i].MacAddr))) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + + return NULL; +} + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetBFerEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte TA, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformerEntry[i].bUsed && (eqMacAddr(TA, pBeamInfo->BeamformerEntry[i].MacAddr))) { + *Idx = i; + return &(pBeamInfo->BeamformerEntry[i]); + } + } + + return NULL; +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetEntryByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + + return NULL; +} + + +BEAMFORMING_CAP +phydm_Beamforming_GetEntryBeamCapByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + BEAMFORMING_CAP BeamformEntryCap = BEAMFORMING_CAP_NONE; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { + BeamformEntryCap = pBeamInfo->BeamformeeEntry[i].BeamformEntryCap; + i = BEAMFORMEE_ENTRY_NUM; + } + } + + return BeamformEntryCap; +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetFreeBFeeEntry( + IN PVOID pDM_VOID, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed == FALSE) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + return NULL; +} + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetFreeBFerEntry( + IN PVOID pDM_VOID, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformerEntry[i].bUsed == FALSE) { + *Idx = i; + return &(pBeamInfo->BeamformerEntry[i]); + } + } + return NULL; +} + +/* +// Description: Get the first entry index of MU Beamformee. +// +// Return Value: Index of the first MU sta. +// +// 2015.05.25. Created by tynli. +// +*/ +u1Byte +phydm_Beamforming_GetFirstMUBFeeEntryIdx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte idx = 0xFF; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + BOOLEAN bFound = FALSE; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (pBeamInfo->BeamformeeEntry[idx].bUsed && pBeamInfo->BeamformeeEntry[idx].is_mu_sta) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); + bFound = TRUE; + break; + } + } + + if (!bFound) + idx = 0xFF; + + return idx; +} + + +/*Add SU BFee and MU BFee*/ +PRT_BEAMFORMEE_ENTRY +Beamforming_AddBFeeEntry( + IN PVOID pDM_VOID, + IN PRT_BEAMFORM_STAINFO pSTA, + IN BEAMFORMING_CAP BeamformCap, + IN u1Byte NumofSoundingDim, + IN u1Byte CompSteeringNumofBFer, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetFreeBFeeEntry(pDM_Odm, Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pEntry != NULL) { + pEntry->bUsed = TRUE; + pEntry->AID = pSTA->AID; + pEntry->MacId = pSTA->MacID; + pEntry->SoundBW = pSTA->BW; + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + /*BSSID[44:47] xor BSSID[40:43]*/ + u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); + /*(dec(A) + dec(B)*32) mod 512*/ + pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; + pEntry->G_ID = 63; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, pEntry->P_AID)); + } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { + /*ad hoc mode*/ + pEntry->P_AID = 0; + pEntry->G_ID = 63; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, pEntry->P_AID)); + } else { + /*client mode*/ + pEntry->P_AID = pSTA->RA[5]; + /*BSSID[39:47]*/ + pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); + pEntry->G_ID = 0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + } + cpMacAddr(pEntry->MacAddr, pSTA->RA); + pEntry->bTxBF = FALSE; + pEntry->bSound = FALSE; + pEntry->SoundPeriod = 400; + pEntry->BeamformEntryCap = BeamformCap; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + +/* pEntry->LogSeq = 0xff; Move to Beamforming_AddBFerEntry*/ +/* pEntry->LogRetryCnt = 0; Move to Beamforming_AddBFerEntry*/ +/* pEntry->LogSuccessCnt = 0; Move to Beamforming_AddBFerEntry*/ + + pEntry->LogStatusFailCnt = 0; + + pEntry->NumofSoundingDim = NumofSoundingDim; + pEntry->CompSteeringNumofBFer = CompSteeringNumofBFer; + + if (BeamformCap & BEAMFORMER_CAP_VHT_MU) { + pDM_Odm->BeamformingInfo.beamformee_mu_cnt += 1; + pEntry->is_mu_sta = TRUE; + pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); + } else if (BeamformCap & (BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { + pDM_Odm->BeamformingInfo.beamformee_su_cnt += 1; + pEntry->is_mu_sta = FALSE; + } + + return pEntry; + } + else + return NULL; +} + +/*Add SU BFee and MU BFer*/ +PRT_BEAMFORMER_ENTRY +Beamforming_AddBFerEntry( + IN PVOID pDM_VOID, + IN PRT_BEAMFORM_STAINFO pSTA, + IN BEAMFORMING_CAP BeamformCap, + IN u1Byte NumofSoundingDim, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMER_ENTRY pEntry = phydm_Beamforming_GetFreeBFerEntry(pDM_Odm, Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pEntry != NULL) { + pEntry->bUsed = TRUE; + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + /*BSSID[44:47] xor BSSID[40:43]*/ + u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); + + pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; + pEntry->G_ID = 63; + /*(dec(A) + dec(B)*32) mod 512*/ + } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { + pEntry->P_AID = 0; + pEntry->G_ID = 63; + } else { + pEntry->P_AID = pSTA->RA[5]; + /*BSSID[39:47]*/ + pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); + pEntry->G_ID = 0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + } + + cpMacAddr(pEntry->MacAddr, pSTA->RA); + pEntry->BeamformEntryCap = BeamformCap; + + pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/ + pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/ + pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/ + + pEntry->NumofSoundingDim = NumofSoundingDim; + + if (BeamformCap & BEAMFORMEE_CAP_VHT_MU) { + pDM_Odm->BeamformingInfo.beamformer_mu_cnt += 1; + pEntry->is_mu_ap = TRUE; + pEntry->AID = pSTA->AID; + } else if (BeamformCap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { + pDM_Odm->BeamformingInfo.beamformer_su_cnt += 1; + pEntry->is_mu_ap = FALSE; + } + + return pEntry; + } + else + return NULL; +} + +#if 0 +BOOLEAN +Beamforming_RemoveEntry( + IN PADAPTER Adapter, + IN pu1Byte RA, + OUT pu1Byte Idx + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, Idx); + PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, Idx); + BOOLEAN ret = FALSE; + + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pBFerEntry=0x%x\n", __func__, pBFerEntry)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pEntry=0x%x\n", __func__, pEntry)); + + if (pEntry != NULL) { + pEntry->bUsed = FALSE; + pEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + /*pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + pEntry->bBeamformingInProgress = FALSE; + ret = TRUE; + } + if (pBFerEntry != NULL) { + pBFerEntry->bUsed = FALSE; + pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + ret = TRUE; + } + return ret; + +} +#endif + +/* Used for BeamformingStart_V1 */ +VOID +phydm_Beamforming_NDPARate( + IN PVOID pDM_VOID, + CHANNEL_WIDTH BW, + u1Byte Rate +) +{ + u2Byte NDPARate = Rate; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (NDPARate == 0) { + if(pDM_Odm->RSSI_Min > 30) // link RSSI > 30% + NDPARate = ODM_RATE24M; + else + NDPARate = ODM_RATE6M; + } + + if (NDPARate < ODM_RATEMCS0) + BW = (CHANNEL_WIDTH)ODM_BW20M; + + NDPARate = (NDPARate << 8) | BW; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); + +} + + +/* Used for BeamformingStart_SW and BeamformingStart_FW */ +VOID +phydm_Beamforming_DymNDPARate( + IN PVOID pDM_VOID +) +{ + u2Byte NDPARate = ODM_RATE6M, BW; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pDM_Odm->RSSI_Min > 30) /*link RSSI > 30%*/ + NDPARate = ODM_RATE24M; + else + NDPARate = ODM_RATE6M; + + BW = ODM_BW20M; + NDPARate = NDPARate << 8 | BW; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA Rate = 0x%X\n", __func__, NDPARate)); +} + +/* +* SW Sounding : SW Timer unit 1ms +* HW Timer unit (1/32000) s 32k is clock. +* FW Sounding : FW Timer unit 10ms +*/ +VOID +Beamforming_DymPeriod( + IN PVOID pDM_VOID, + IN u8 status +) +{ + u1Byte Idx; + BOOLEAN bChangePeriod = FALSE; + u2Byte SoundPeriod_SW, SoundPeriod_FW; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + PRT_BEAMFORMEE_ENTRY pBeamformEntry; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + //3 TODO per-client throughput caculation. + + if ((*(pDM_Odm->pCurrentTxTP) + *(pDM_Odm->pCurrentRxTP) > 2) && ((pEntry->LogStatusFailCnt <= 20) || status)) { + SoundPeriod_SW = 40; /* 40ms */ + SoundPeriod_FW = 40; /* From H2C cmd, unit = 10ms */ + } else { + SoundPeriod_SW = 4000;/* 4s */ + SoundPeriod_FW = 400; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]SoundPeriod_SW=%d, SoundPeriod_FW=%d\n", __func__, SoundPeriod_SW, SoundPeriod_FW)); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + if (pBeamformEntry->DefaultCSICnt > 20) { + /*Modified by David*/ + SoundPeriod_SW = 4000; + SoundPeriod_FW = 400; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Period = %d\n", __func__, SoundPeriod_SW)); + if (pBeamformEntry->BeamformEntryCap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) { + if (pBeamformEntry->SoundPeriod != SoundPeriod_FW) { + pBeamformEntry->SoundPeriod = SoundPeriod_FW; + bChangePeriod = TRUE; /*Only FW sounding need to send H2C packet to change sound period. */ + } + } else if (pBeamformEntry->SoundPeriod != SoundPeriod_SW) { + pBeamformEntry->SoundPeriod = SoundPeriod_SW; + } + } + } + + if (bChangePeriod) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); +} + + + + +BOOLEAN +Beamforming_SendHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ) +{ + BOOLEAN ret = TRUE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (QIdx == BEACON_QUEUE) + ret = SendFWHTNDPAPacket(pDM_Odm, RA, BW); + else + ret = SendSWHTNDPAPacket(pDM_Odm, RA, BW); + + return ret; +} + + + +BOOLEAN +Beamforming_SendVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + HalComTxbf_Set(pDM_Odm, TXBF_SET_GET_TX_RATE, NULL); + + if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); + + } else { + if (QIdx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ + ret = SendFWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + else { +#ifdef SUPPORT_MU_BF + #if (SUPPORT_MU_BF == 1) + pBeamInfo->is_mu_sounding = TRUE; + ret = SendSWVHTMUNDPAPacket(pDM_Odm, BW); + #else + pBeamInfo->is_mu_sounding = FALSE; + ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + #endif +#else + pBeamInfo->is_mu_sounding = FALSE; + ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); +#endif + } + } + return ret; +} + + +BEAMFORMING_NOTIFY_STATE +phydm_beamfomring_bSounding( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + pu1Byte Idx + ) +{ + BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + /*if(( Beamforming_GetBeamCap(pBeamInfo) & BEAMFORMER_CAP) == 0)*/ + /*bSounding = BEAMFORMING_NOTIFY_RESET;*/ + if (BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER) + bSounding = BEAMFORMING_NOTIFY_RESET; + else { + u1Byte i; + + for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d bUsed=%d, bSound=%d\n", __func__, i, pBeamInfo->BeamformeeEntry[i].bUsed, pBeamInfo->BeamformeeEntry[i].bSound)); + if (pBeamInfo->BeamformeeEntry[i].bUsed && (!pBeamInfo->BeamformeeEntry[i].bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); + *Idx = i; + if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) + bSounding = BEAMFORMEE_NOTIFY_ADD_MU; + else + bSounding = BEAMFORMEE_NOTIFY_ADD_SU; + } + + if ((!pBeamInfo->BeamformeeEntry[i].bUsed) && pBeamInfo->BeamformeeEntry[i].bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); + *Idx = i; + if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) + bSounding = BEAMFORMEE_NOTIFY_DELETE_MU; + else + bSounding = BEAMFORMEE_NOTIFY_DELETE_SU; + } + } + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, bSounding = %d\n", __func__, bSounding)); + return bSounding; +} + + +//This function is unused +u1Byte +phydm_beamforming_SoundingIdx( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + u1Byte Idx = 0; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || + BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) + Idx = BeamOidInfo.SoundOidIdx; + else { + u1Byte i; + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (FALSE == pBeamInfo->BeamformeeEntry[i].bSound)) { + Idx = i; + break; + } + } + } + + return Idx; +} + + +SOUNDING_MODE +phydm_beamforming_SoundingMode( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte SupportInterface = pDM_Odm->SupportInterface; + + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + SOUNDING_MODE Mode = BeamOidInfo.SoundOidMode; + + if (BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) { + if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Mode = BeamOidInfo.SoundOidMode; + else + Mode = SOUNDING_STOP_All_TIMER; + } else if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER) { + if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) + Mode = BeamOidInfo.SoundOidMode; + else + Mode = SOUNDING_STOP_All_TIMER; + } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) { + if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) + Mode = SOUNDING_FW_VHT_TIMER; + else + Mode = SOUNDING_SW_VHT_TIMER; + } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) { + if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) + Mode = SOUNDING_FW_HT_TIMER; + else + Mode = SOUNDING_SW_HT_TIMER; + } else + Mode = SOUNDING_STOP_All_TIMER; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SupportInterface=%d, Mode=%d\n", __func__, SupportInterface, Mode)); + + return Mode; +} + + +u2Byte +phydm_beamforming_SoundingTime( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + SOUNDING_MODE Mode, + u1Byte Idx + ) +{ + u2Byte SoundingTime = 0xffff; + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) + SoundingTime = BeamOidInfo.SoundOidPeriod * 32; + else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + /*Modified by David*/ + SoundingTime = BeamEntry.SoundPeriod; /*BeamOidInfo.SoundOidPeriod;*/ + else + SoundingTime = BeamEntry.SoundPeriod; + + return SoundingTime; +} + + +CHANNEL_WIDTH +phydm_beamforming_SoundingBW( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + SOUNDING_MODE Mode, + u1Byte Idx + ) +{ + CHANNEL_WIDTH SoundingBW = CHANNEL_WIDTH_20; + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) + SoundingBW = BeamOidInfo.SoundOidBW; + else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + /*Modified by David*/ + SoundingBW = BeamEntry.SoundBW; /*BeamOidInfo.SoundOidBW;*/ + else + SoundingBW = BeamEntry.SoundBW; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, SoundingBW=0x%X\n", __func__, SoundingBW)); + + return SoundingBW; +} + + +BOOLEAN +phydm_Beamforming_SelectBeamEntry( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*pEntry.bSound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed SoundIdx.*/ + pSoundInfo->SoundIdx = phydm_beamforming_SoundingIdx(pDM_Odm, pBeamInfo); + /*pSoundInfo->SoundIdx = 0;*/ + + if (pSoundInfo->SoundIdx < BEAMFORMEE_ENTRY_NUM) + pSoundInfo->SoundMode = phydm_beamforming_SoundingMode(pDM_Odm, pBeamInfo, pSoundInfo->SoundIdx); + else + pSoundInfo->SoundMode = SOUNDING_STOP_All_TIMER; + + if (SOUNDING_STOP_All_TIMER == pSoundInfo->SoundMode) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of SOUNDING_STOP_All_TIMER\n", __func__)); + return FALSE; + } else { + pSoundInfo->SoundBW = phydm_beamforming_SoundingBW(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); + pSoundInfo->SoundPeriod = phydm_beamforming_SoundingTime(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); + return TRUE; + } +} + +/*SU BFee Entry Only*/ +BOOLEAN +phydm_beamforming_StartPeriod( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + BOOLEAN Ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + phydm_Beamforming_DymNDPARate(pDM_Odm); + + phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); // Modified + + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); + else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || + pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) { + HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; + u4Byte val = (pSoundInfo->SoundPeriod | (TimerType<<16)); + + //HW timer stop: All IC has the same setting + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); + //ODM_Write1Byte(pDM_Odm, 0x15F, 0); + //HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_INIT, (pu1Byte)(&val)); + //ODM_Write1Byte(pDM_Odm, 0x164, 1); + //ODM_Write4Byte(pDM_Odm, 0x15C, val); + //HW timer start: All IC has the same setting + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_START, (pu1Byte)(&TimerType)); + //ODM_Write1Byte(pDM_Odm, 0x15F, 0x5); + } else if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) + Ret = BeamformingStart_FW(pDM_Odm, pSoundInfo->SoundIdx); + else + Ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SoundIdx=%d, SoundMode=%d, SoundBW=%d, SoundPeriod=%d\n", __func__, + pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW, pSoundInfo->SoundPeriod)); + + return Ret; +} + +// Used after Beamforming_Leave, and will clear the setting of the "already deleted" entry +/*SU BFee Entry Only*/ +VOID +phydm_beamforming_EndPeriod_SW( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); + else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || + pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) + /*HW timer stop: All IC has the same setting*/ + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); + /*ODM_Write1Byte(pDM_Odm, 0x15F, 0);*/ +} + +VOID +phydm_beamforming_EndPeriod_FW( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); +} + + +/*SU BFee Entry Only*/ +VOID +phydm_beamforming_ClearEntry_SW( + IN PVOID pDM_VOID, + BOOLEAN IsDelete, + u1Byte DeleteIdx + ) +{ + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + if (IsDelete) { + if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { + pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; + if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW DeleteIdx is wrong!!!!!\n", __func__)); + return; + } + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, DeleteIdx)); + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + pBeamformEntry->bBeamformingInProgress = FALSE; + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&DeleteIdx); + } + pBeamformEntry->bSound = FALSE; + } else { + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ + /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ + + if (pBeamformEntry->bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, Idx)); + /* + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_Beamforming_End_SW(pDM_Odm, 0); + else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + } + + pBeamformEntry->bSound = FALSE; + } + } + } +} + +VOID +phydm_beamforming_ClearEntry_FW( + IN PVOID pDM_VOID, + BOOLEAN IsDelete, + u1Byte DeleteIdx + ) +{ + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + if (IsDelete) { + if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { + pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; + + if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW DeleteIdx is wrong!!!!!\n", __func__)); + return; + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, DeleteIdx)); + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + pBeamformEntry->bSound = FALSE; + } else { + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ + /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ + + if (pBeamformEntry->bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, Idx)); + /* + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + pBeamformEntry->bSound = FALSE; + } + } + } +} + +/* +* Called : +* 1. Add and delete entry : Beamforming_Enter/Beamforming_Leave +* 2. FW trigger : Beamforming_SetTxBFen +* 3. Set OID_RT_BEAMFORMING_PERIOD : BeamformingControl_V2 +*/ +VOID +phydm_Beamforming_Notify( + IN PVOID pDM_VOID + ) +{ + u1Byte Idx=BEAMFORMEE_ENTRY_NUM; + BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + bSounding = phydm_beamfomring_bSounding(pDM_Odm, pBeamInfo, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, bSounding=%d, Idx=%d\n", __func__, bSounding, Idx)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: pBeamInfo->beamformee_su_cnt = %d\n", __func__, pBeamInfo->beamformee_su_cnt)); + + + switch (bSounding) { + case BEAMFORMEE_NOTIFY_ADD_SU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); + phydm_beamforming_StartPeriod(pDM_Odm); + break; + + case BEAMFORMEE_NOTIFY_DELETE_SU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); + if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_ClearEntry_FW(pDM_Odm, TRUE, Idx); + if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_EndPeriod_FW(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + } + } else { + phydm_beamforming_ClearEntry_SW(pDM_Odm, TRUE, Idx); + if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_EndPeriod_SW(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + } + } + break; + + case BEAMFORMEE_NOTIFY_ADD_MU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); + if (pBeamInfo->beamformee_mu_cnt == 2) { + /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod);*/ + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, 1000); /*Do MU sounding every 1sec*/ + } else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); + break; + + case BEAMFORMEE_NOTIFY_DELETE_MU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); + if (pBeamInfo->beamformee_mu_cnt == 1) { + /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER)*/{ + ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); + } + } + break; + + case BEAMFORMING_NOTIFY_RESET: + if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_ClearEntry_FW(pDM_Odm, FALSE, Idx); + phydm_beamforming_EndPeriod_FW(pDM_Odm); + } else { + phydm_beamforming_ClearEntry_SW(pDM_Odm, FALSE, Idx); + phydm_beamforming_EndPeriod_SW(pDM_Odm); + } + + break; + + default: + break; + } + +} + + + +BOOLEAN +Beamforming_InitEntry( + IN PVOID pDM_VOID, + IN u2Byte staIdx, + pu1Byte BFerBFeeIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; + PRT_BEAMFORM_STAINFO pSTA = NULL; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + u1Byte BFerIdx=0xF, BFeeIdx=0xF; + u1Byte NumofSoundingDim = 0, CompSteeringNumofBFer = 0; + + pSTA = phydm_staInfoInit(pDM_Odm, staIdx); + + /*The current setting does not support Beaforming*/ + if (BEAMFORMING_CAP_NONE == pSTA->HtBeamformCap && BEAMFORMING_CAP_NONE == pSTA->VhtBeamformCap) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); + return FALSE; + } + + if (pSTA->WirelessMode < WIRELESS_MODE_N_24G) + return FALSE; + else { + if (pSTA->WirelessMode & WIRELESS_MODE_N_5G || pSTA->WirelessMode & WIRELESS_MODE_N_24G) {/*HT*/ + if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_HT_EXPLICIT); + NumofSoundingDim = (pSTA->CurBeamform&BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP)>>6; + } + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(pSTA->HtBeamformCap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_HT_EXPLICIT); + CompSteeringNumofBFer = (pSTA->CurBeamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM)>>4; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT CurBeamform=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamform, BeamformCap)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT NumofSoundingDim=%d, CompSteeringNumofBFer=%d\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); + } +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (pSTA->WirelessMode & WIRELESS_MODE_AC_5G || pSTA->WirelessMode & WIRELESS_MODE_AC_24G) { /*VHT*/ + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMEE_CAP_VHT_SU); + NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + } + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMER_CAP_VHT_SU); + CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + } + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_VHT_MU); + NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + } + /* We are Beamformer because the STA is MU Beamformee*/ + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_VHT_MU); + CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT CurBeamformVHT=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamformVHT, BeamformCap)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT NumofSoundingDim=0x%X, CompSteeringNumofBFer=0x%X\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); + + } +#endif + } + + + if(BeamformCap == BEAMFORMING_CAP_NONE) + return FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, BeamformCap)); + + /*We are BFee, so the entry is BFer*/ + if (BeamformCap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, pSTA->RA, &BFerIdx); + + if (pBeamformerEntry == NULL) { + pBeamformerEntry = Beamforming_AddBFerEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim , &BFerIdx); + if (pBeamformerEntry == NULL) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); + } + } + + /*We are BFer, so the entry is BFee*/ + if (BeamformCap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, pSTA->RA, &BFeeIdx); + + /*¦pªGBFeeIdx = 0xF «h¥Nªí¥Ø«eentry·í¤¤¨S¦³¬Û¦PªºMACID¦b¤º*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, BFeeIdx)); + if (pBeamformEntry == NULL) { + pBeamformEntry = Beamforming_AddBFeeEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim, CompSteeringNumofBFer, &BFeeIdx); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: pSTA->AID=%d, pSTA->MacID=%d\n", __func__, pSTA->AID, pSTA->MacID)); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, BFeeIdx)); + + if (pBeamformEntry == NULL) + return FALSE; + else + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } else { + /*Entry has been created. If entry is initialing or progressing then errors occur.*/ + if (pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && + pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + return FALSE; + } else + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_staInfoUpdate(pDM_Odm, staIdx, pBeamformEntry); + } + + *BFerBFeeIdx = (BFerIdx<<4) | BFeeIdx; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: BFerIdx=0x%X, BFeeIdx=0x%X, BFerBFeeIdx=0x%X\n", __func__, BFerIdx, BFeeIdx, *BFerBFeeIdx)); + + return TRUE; +} + + +VOID +Beamforming_DeInitEntry( + IN PVOID pDM_VOID, + pu1Byte RA + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + + PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, &Idx); + PRT_BEAMFORMEE_ENTRY pBFeeEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + BOOLEAN ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pBFeeEntry != NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFeeEntry\n", __func__)); + pBFeeEntry->bUsed = FALSE; + pBFeeEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + pBFeeEntry->bBeamformingInProgress = FALSE; + if (pBFeeEntry->is_mu_sta) { + pDM_Odm->BeamformingInfo.beamformee_mu_cnt -= 1; + pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); + } else { + pDM_Odm->BeamformingInfo.beamformee_su_cnt -= 1; + } + ret = TRUE; + } + + if (pBFerEntry != NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFerEntry\n", __func__)); + pBFerEntry->bUsed = FALSE; + pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + if (pBFerEntry->is_mu_ap) + pDM_Odm->BeamformingInfo.beamformer_mu_cnt -= 1; + else + pDM_Odm->BeamformingInfo.beamformer_su_cnt -= 1; + ret = TRUE; + } + + if (ret == TRUE) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_LEAVE, (pu1Byte)&Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, Idx = 0x%X\n", __func__, Idx)); +} + + +BOOLEAN +BeamformingStart_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + BOOLEAN Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pEntry; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + if (pEntry->bUsed == FALSE) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + if (pEntry->bBeamformingInProgress) + return FALSE; + + pEntry->bBeamformingInProgress = TRUE; + + if (Mode == 1) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + } else if (Mode == 0) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + } + + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + } + } + + pEntry->SoundBW = BW; + pBeamInfo->BeamformeeCurIdx = Idx; + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + + if (Mode == 1) + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); + else + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, pEntry->AID, BW, NORMAL_QUEUE); + + if (ret == FALSE) { + Beamforming_Leave(pDM_Odm, RA); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Idx %d\n", __func__, Idx)); + return TRUE; +} + + +BOOLEAN +BeamformingStart_SW( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW + ) +{ + pu1Byte RA = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pEntry; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + if (pBeamInfo->is_mu_sounding) { + pBeamInfo->is_mu_sounding_in_progress = TRUE; + pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + RA = pEntry->MacAddr; + + } else { + pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + + if (pEntry->bUsed == FALSE) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + if (pEntry->bBeamformingInProgress) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, skip...\n")); + return FALSE; + } + + pEntry->bBeamformingInProgress = TRUE; + RA = pEntry->MacAddr; + + if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); + return FALSE; + } + } else if (Mode == SOUNDING_SW_VHT_TIMER || Mode == SOUNDING_HW_VHT_TIMER || Mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); + return FALSE; + } + } + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect BeamformEntryState(%d) <==\n", __func__, pEntry->BeamformEntryState)); + return FALSE; + } else { + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + } + } + + pBeamInfo->BeamformeeCurIdx = Idx; + } + + /*2014.12.22 Luke: Need to be checked*/ + /*GET_TXBF_INFO(Adapter)->fTxbfSet(Adapter, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx);*/ + + if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA , BW, NORMAL_QUEUE); + else + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA , pEntry->AID, BW, NORMAL_QUEUE); + + if (ret == FALSE) { + Beamforming_Leave(pDM_Odm, RA); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + + + /*-------------------------- + // Send BF Report Poll for MU BF + --------------------------*/ +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +{ + u1Byte idx, PollSTACnt = 0; + BOOLEAN bGetFirstBFee = FALSE; + + if (pBeamInfo->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + if (bGetFirstBFee) { + PollSTACnt++; + if (PollSTACnt == (pBeamInfo->beamformee_mu_cnt - 1))/* The last STA*/ + SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, TRUE); + else + SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, FALSE); + } else { + bGetFirstBFee = TRUE; + } + } + } + } +} +#endif +#endif + return TRUE; +} + + +BOOLEAN +BeamformingStart_FW( + IN PVOID pDM_VOID, + u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pEntry; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + if (pEntry->bUsed == FALSE) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); + return FALSE; + } + + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, Idx=0x%X\n", __func__, Idx)); + return TRUE; +} + +VOID +Beamforming_CheckSoundingSuccess( + IN PVOID pDM_VOID, + BOOLEAN Status +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); + + if (Status == 1) { + if (pEntry->LogStatusFailCnt == 21) + Beamforming_DymPeriod(pDM_Odm, Status); + pEntry->LogStatusFailCnt = 0; + } else if (pEntry->LogStatusFailCnt <= 20) { + pEntry->LogStatusFailCnt++; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + } + if (pEntry->LogStatusFailCnt > 20) { + pEntry->LogStatusFailCnt = 21; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __func__)); + Beamforming_DymPeriod(pDM_Odm, Status); + } +} + +VOID +phydm_Beamforming_End_SW( + IN PVOID pDM_VOID, + BOOLEAN Status + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + if (pBeamInfo->is_mu_sounding) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); + pBeamInfo->is_mu_sounding_in_progress = FALSE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + } else { + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, pEntry->BeamformEntryState)); + return; + } + + if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + } else if (Status == 1) { + pEntry->LogStatusFailCnt = 0; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + } else { + pEntry->LogStatusFailCnt++; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_TX_PATH_RESET, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + } + + if (pEntry->LogStatusFailCnt > 50) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 50, Stop SOUNDING\n", __func__)); + pEntry->bSound = FALSE; + Beamforming_DeInitEntry(pDM_Odm, pEntry->MacAddr); + + /*Modified by David - Every action of deleting entry should follow by Notify*/ + phydm_Beamforming_Notify(pDM_Odm); + } + + pEntry->bBeamformingInProgress = FALSE; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Status=%d\n", __func__, Status)); +} + + +VOID +Beamforming_TimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PVOID pDM_VOID +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + IN PVOID pContext +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = (PADAPTER)pContext; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + BOOLEAN ret = FALSE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + BOOLEAN bBeamformingInProgress; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pBeamInfo->is_mu_sounding) + bBeamformingInProgress = pBeamInfo->is_mu_sounding_in_progress; + else + bBeamformingInProgress = pEntry->bBeamformingInProgress; + + if (bBeamformingInProgress) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, reset it\n")); + phydm_Beamforming_End_SW(pDM_Odm, 0); + } + + ret = phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); +#if (SUPPORT_MU_BF == 1) + if (ret && pBeamInfo->beamformee_mu_cnt > 1) + ret = 1; + else + ret = 0; +#endif + if (ret) + ret = BeamformingStart_SW(pDM_Odm, pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW); + else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); + + if ((pBeamInfo->beamformee_su_cnt != 0) || (pBeamInfo->beamformee_mu_cnt > 1)) { + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); + else { + u4Byte val = (pSoundInfo->SoundPeriod << 16) | HAL_TIMER_TXBF; + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_RESTART, (pu1Byte)(&val)); + } + } +} + + +VOID +Beamforming_SWTimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PRT_TIMER pTimer +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + void *FunctionContext +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + Beamforming_TimerCallback(pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)FunctionContext; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (Adapter->net_closed == TRUE) + return; + rtw_run_in_thread_cmd(Adapter, Beamforming_TimerCallback, Adapter); +#endif + +} + + +VOID +phydm_Beamforming_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); + + pBeamOidInfo->SoundOidMode = SOUNDING_STOP_OID_TIMER; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Mode (%d)\n", __func__, pBeamOidInfo->SoundOidMode)); + + pBeamInfo->beamformee_su_cnt = 0; + pBeamInfo->beamformer_su_cnt = 0; + pBeamInfo->beamformee_mu_cnt = 0; + pBeamInfo->beamformer_mu_cnt = 0; + pBeamInfo->beamformee_mu_reg_maping = 0; + pBeamInfo->mu_ap_index = 0; + pBeamInfo->is_mu_sounding = FALSE; + pBeamInfo->FirstMUBFeeIndex = 0xFF; + pBeamInfo->applyVmatrix = TRUE; + pBeamInfo->snding3SS = FALSE; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pBeamInfo->SourceAdapter = pDM_Odm->Adapter; +#endif + halComTxbf_beamformInit(pDM_Odm); +} + + +BOOLEAN +phydm_actingDetermine( + IN PVOID pDM_VOID, + IN PHYDM_ACTING_TYPE type + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN ret = FALSE; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->BeamformingInfo.SourceAdapter; +#else + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (type == PhyDM_ACTING_AS_AP) + ret = ACTING_AS_AP(Adapter); + else if (type == PhyDM_ACTING_AS_IBSS) + ret = ACTING_AS_IBSS(Adapter); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + if (type == PhyDM_ACTING_AS_AP) + ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); + else if (type == PhyDM_ACTING_AS_IBSS) + ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); +#endif + + return ret; + +} + +VOID +Beamforming_Enter( + IN PVOID pDM_VOID, + IN u2Byte staIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte BFerBFeeIdx = 0xff; + + if (Beamforming_InitEntry(pDM_Odm, staIdx, &BFerBFeeIdx)) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_ENTER, (pu1Byte)&BFerBFeeIdx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); +} + + +VOID +Beamforming_Leave( + IN PVOID pDM_VOID, + pu1Byte RA + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (RA != NULL) { + Beamforming_DeInitEntry(pDM_Odm, RA); + phydm_Beamforming_Notify(pDM_Odm); + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); +} + +#if 0 +//Nobody calls this function +VOID +phydm_Beamforming_SetTxBFen( + IN PVOID pDM_VOID, + u1Byte MacId, + BOOLEAN bTxBF + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pEntry; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + pEntry = phydm_Beamforming_GetEntryByMacId(pDM_Odm, MacId, &Idx); + + if(pEntry == NULL) + return; + else + pEntry->bTxBF = bTxBF; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s MacId %d TxBF %d\n", __func__, pEntry->MacId, pEntry->bTxBF)); + + phydm_Beamforming_Notify(pDM_Odm); +} +#endif + +BEAMFORMING_CAP +phydm_Beamforming_GetBeamCap( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + u1Byte i; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + BeamformeeEntry = pBeamInfo->BeamformeeEntry[i]; + + if (BeamformeeEntry.bUsed) { + bSelfBeamformer = TRUE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d bUsed=TRUE\n", __func__, i)); + break; + } + } + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + BeamformerEntry = pBeamInfo->BeamformerEntry[i]; + + if (BeamformerEntry.bUsed) { + bSelfBeamformee = TRUE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d bUsed=TRUE\n", __func__, i)); + break; + } + } + + if (bSelfBeamformer) + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP); + if (bSelfBeamformee) + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP); + + return BeamformCap; +} + + +BOOLEAN +BeamformingControl_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + u1Byte AID, + u1Byte Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN ret = TRUE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), Mode (%d), BW (%d)\n", AID, Mode, BW)); + + switch (Mode) { + case 0: + ret = BeamformingStart_V1(pDM_Odm, RA, 0, BW, Rate); + break; + case 1: + ret = BeamformingStart_V1(pDM_Odm, RA, 1, BW, Rate); + break; + case 2: + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, AID, BW, NORMAL_QUEUE); + break; + case 3: + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); + break; + } + return ret; +} + +/*Only OID uses this function*/ +BOOLEAN +phydm_BeamformingControl_V2( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW, + u2Byte Period + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Idx (%d), Mode (%d), BW (%d), Period (%d)\n", Idx, Mode, BW, Period)); + + pBeamOidInfo->SoundOidIdx = Idx; + pBeamOidInfo->SoundOidMode = (SOUNDING_MODE) Mode; + pBeamOidInfo->SoundOidBW = BW; + pBeamOidInfo->SoundOidPeriod = Period; + + phydm_Beamforming_Notify(pDM_Odm); + + return TRUE; +} + + +VOID +phydm_Beamforming_Watchdog( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); + + if (pBeamInfo->beamformee_su_cnt == 0) + return; + + Beamforming_DymPeriod(pDM_Odm,0); + phydm_Beamforming_DymNDPARate(pDM_Odm); + +} + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_beamforming.h b/package/kernel/rtl8192cd/phydm/phydm_beamforming.h index a92b0562c44..8fe74d89ef9 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_beamforming.h +++ b/package/kernel/rtl8192cd/phydm/phydm_beamforming.h @@ -1,383 +1,383 @@ -#ifndef __INC_PHYDM_BEAMFORMING_H -#define __INC_PHYDM_BEAMFORMING_H - -#ifndef BEAMFORMING_SUPPORT -#define BEAMFORMING_SUPPORT 0 -#endif - -/*Beamforming Related*/ -#include "txbf/halcomtxbf.h" -#include "txbf/haltxbfjaguar.h" -#include "txbf/haltxbf8192e.h" -#include "txbf/haltxbf8814a.h" -#include "txbf/haltxbf8822b.h" -#include "txbf/haltxbfinterface.h" - -#if (BEAMFORMING_SUPPORT == 1) - -#define MAX_BEAMFORMEE_SU 2 -#define MAX_BEAMFORMER_SU 2 -#if (RTL8822B_SUPPORT == 1) -#define MAX_BEAMFORMEE_MU 6 -#define MAX_BEAMFORMER_MU 1 -#else -#define MAX_BEAMFORMEE_MU 0 -#define MAX_BEAMFORMER_MU 0 -#endif - -#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) -#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/*for different naming between WIN and CE*/ -#define BEACON_QUEUE BCN_QUEUE_INX -#define NORMAL_QUEUE MGT_QUEUE_INX -#define RT_DISABLE_FUNC RTW_DISABLE_FUNC -#define RT_ENABLE_FUNC RTW_ENABLE_FUNC -#endif - -typedef enum _BEAMFORMING_ENTRY_STATE { - BEAMFORMING_ENTRY_STATE_UNINITIALIZE, - BEAMFORMING_ENTRY_STATE_INITIALIZEING, - BEAMFORMING_ENTRY_STATE_INITIALIZED, - BEAMFORMING_ENTRY_STATE_PROGRESSING, - BEAMFORMING_ENTRY_STATE_PROGRESSED -} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; - - -typedef enum _BEAMFORMING_NOTIFY_STATE { - BEAMFORMING_NOTIFY_NONE, - BEAMFORMING_NOTIFY_ADD, - BEAMFORMING_NOTIFY_DELETE, - BEAMFORMEE_NOTIFY_ADD_SU, - BEAMFORMEE_NOTIFY_DELETE_SU, - BEAMFORMEE_NOTIFY_ADD_MU, - BEAMFORMEE_NOTIFY_DELETE_MU, - BEAMFORMING_NOTIFY_RESET -} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE; - -typedef enum _BEAMFORMING_CAP { - BEAMFORMING_CAP_NONE = 0x0, - BEAMFORMER_CAP_HT_EXPLICIT = BIT1, - BEAMFORMEE_CAP_HT_EXPLICIT = BIT2, - BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP = BIT9, - BEAMFORMEE_CAP = BIT10, -}BEAMFORMING_CAP, *PBEAMFORMING_CAP; - - -typedef enum _SOUNDING_MODE { - SOUNDING_SW_VHT_TIMER = 0x0, - SOUNDING_SW_HT_TIMER = 0x1, - SOUNDING_STOP_All_TIMER = 0x2, - SOUNDING_HW_VHT_TIMER = 0x3, - SOUNDING_HW_HT_TIMER = 0x4, - SOUNDING_STOP_OID_TIMER = 0x5, - SOUNDING_AUTO_VHT_TIMER = 0x6, - SOUNDING_AUTO_HT_TIMER = 0x7, - SOUNDING_FW_VHT_TIMER = 0x8, - SOUNDING_FW_HT_TIMER = 0x9, -}SOUNDING_MODE, *PSOUNDING_MODE; - -typedef struct _RT_BEAMFORM_STAINFO { - pu1Byte RA; - u2Byte AID; - u2Byte MacID; - u1Byte MyMacAddr[6]; - WIRELESS_MODE WirelessMode; - CHANNEL_WIDTH BW; - BEAMFORMING_CAP BeamformCap; - u1Byte HtBeamformCap; - u2Byte VhtBeamformCap; - u1Byte CurBeamform; - u2Byte CurBeamformVHT; -} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO; - - -typedef struct _RT_BEAMFORMEE_ENTRY { - BOOLEAN bUsed; - BOOLEAN bTxBF; - BOOLEAN bSound; - u2Byte AID; /*Used to construct AID field of NDPA packet.*/ - u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */ - u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u2Byte G_ID; /*Used to fill Tx DESC*/ - u1Byte MyMacAddr[6]; - u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ - CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/ - u2Byte SoundPeriod; - BEAMFORMING_CAP BeamformEntryCap; - BEAMFORMING_ENTRY_STATE BeamformEntryState; - BOOLEAN bBeamformingInProgress; - /*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/ - /*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ - /*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ - u2Byte LogStatusFailCnt:5; // 0~21 - u2Byte DefaultCSICnt:5; // 0~21 - u1Byte CSIMatrix[327]; - u2Byte CSIMatrixLen; - u1Byte NumofSoundingDim; - u1Byte CompSteeringNumofBFer; - u1Byte su_reg_index; -#if (MU_BEAMFORMING_SUPPORT == 1) - /*For MU-MIMO*/ - BOOLEAN is_mu_sta; - u1Byte mu_reg_index; - u1Byte gid_valid[8]; - u1Byte user_position[16]; -#endif -} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY; - -typedef struct _RT_BEAMFORMER_ENTRY { - BOOLEAN bUsed; - /*P_AID of BFer entry is probably not used*/ - u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u2Byte G_ID; - u1Byte MyMacAddr[6]; - u1Byte MacAddr[6]; - BEAMFORMING_CAP BeamformEntryCap; - u1Byte NumofSoundingDim; - u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ - u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/ - u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/ - u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ - u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ - u1Byte su_reg_index; -#if (MU_BEAMFORMING_SUPPORT == 1) - /*For MU-MIMO*/ - BOOLEAN is_mu_ap; - u1Byte gid_valid[8]; - u1Byte user_position[16]; - u2Byte AID; -#endif -} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY; - -typedef struct _RT_SOUNDING_INFO { - u1Byte SoundIdx; - CHANNEL_WIDTH SoundBW; - SOUNDING_MODE SoundMode; - u2Byte SoundPeriod; -} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO; - - - -typedef struct _RT_BEAMFORMING_OID_INFO { - u1Byte SoundOidIdx; - CHANNEL_WIDTH SoundOidBW; - SOUNDING_MODE SoundOidMode; - u2Byte SoundOidPeriod; -} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO; - - -typedef struct _RT_BEAMFORMING_INFO { - BEAMFORMING_CAP BeamformCap; - RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM]; - RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM]; - RT_BEAMFORM_STAINFO BeamformSTAinfo; - u1Byte BeamformeeCurIdx; - RT_TIMER BeamformingTimer; - RT_TIMER mu_timer; - RT_SOUNDING_INFO SoundingInfo; - RT_BEAMFORMING_OID_INFO BeamformingOidInfo; - HAL_TXBF_INFO TxbfInfo; - u1Byte SoundingSequence; - u1Byte beamformee_su_cnt; - u1Byte beamformer_su_cnt; - u4Byte beamformee_su_reg_maping; - u4Byte beamformer_su_reg_maping; - /*For MU-MINO*/ - u1Byte beamformee_mu_cnt; - u1Byte beamformer_mu_cnt; - u4Byte beamformee_mu_reg_maping; - u1Byte mu_ap_index; - BOOLEAN is_mu_sounding; - u1Byte FirstMUBFeeIndex; - BOOLEAN is_mu_sounding_in_progress; - BOOLEAN dbg_disable_mu_tx; - BOOLEAN applyVmatrix; - BOOLEAN snding3SS; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER SourceAdapter; -#endif - /* Control register */ - u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */ -} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO; - - -typedef struct _RT_NDPA_STA_INFO { - u2Byte AID:12; - u2Byte FeedbackType:1; - u2Byte NcIndex:3; -} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO; - -typedef enum _PHYDM_ACTING_TYPE { - PhyDM_ACTING_AS_IBSS = 0, - PhyDM_ACTING_AS_AP = 1 -} PHYDM_ACTING_TYPE; - - -BEAMFORMING_CAP -phydm_Beamforming_GetEntryBeamCapByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId - ); - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetBFeeEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte RA, - OUT pu1Byte Idx - ); - -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetBFerEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte TA, - OUT pu1Byte Idx - ); - -u1Byte -Beamforming_GetHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer -); - -u1Byte -Beamforming_GetVHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer -); - -VOID -phydm_Beamforming_Notify( - IN PVOID pDM_VOID - ); - -BOOLEAN -phydm_actingDetermine( - IN PVOID pDM_VOID, - IN PHYDM_ACTING_TYPE type - ); - -VOID -Beamforming_Enter( - IN PVOID pDM_VOID, - IN u2Byte staIdx - ); - -VOID -Beamforming_Leave( - IN PVOID pDM_VOID, - pu1Byte RA - ); - -BOOLEAN -BeamformingStart_FW( - IN PVOID pDM_VOID, - u1Byte Idx - ); - -VOID -Beamforming_CheckSoundingSuccess( - IN PVOID pDM_VOID, - BOOLEAN Status -); - -VOID -phydm_Beamforming_End_SW( - IN PVOID pDM_VOID, - BOOLEAN Status - ); - -VOID -Beamforming_TimerCallback( - IN PVOID pDM_VOID - ); - -VOID -phydm_Beamforming_Init( - IN PVOID pDM_VOID - ); - - - -BEAMFORMING_CAP -phydm_Beamforming_GetBeamCap( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo - ); - - -BOOLEAN -BeamformingControl_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - u1Byte AID, - u1Byte Mode, - CHANNEL_WIDTH BW, - u1Byte Rate - ); - - -BOOLEAN -phydm_BeamformingControl_V2( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, - CHANNEL_WIDTH BW, - u2Byte Period - ); - -VOID -phydm_Beamforming_Watchdog( - IN PVOID pDM_VOID - ); - -VOID -Beamforming_SWTimerCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PRT_TIMER pTimer -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - void *FunctionContext -#endif - ); - -BOOLEAN -Beamforming_SendHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ); - - -BOOLEAN -Beamforming_SendVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ); - -#else -#define Beamforming_GidPAid(Adapter, pTcb) -#define phydm_actingDetermine(pDM_Odm, type) FALSE -#define Beamforming_Enter(pDM_Odm, staIdx) -#define Beamforming_Leave(pDM_Odm, RA) -#define Beamforming_End_FW(pDMOdm) -#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE -#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE -#define phydm_Beamforming_End_SW(pDM_Odm, _Status) -#define Beamforming_TimerCallback(pDM_Odm) -#define phydm_Beamforming_Init(pDM_Odm) -#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE -#define Beamforming_Watchdog(pDM_Odm) -#define phydm_Beamforming_Watchdog(pDM_Odm) - - -#endif -#endif +#ifndef __INC_PHYDM_BEAMFORMING_H +#define __INC_PHYDM_BEAMFORMING_H + +#ifndef BEAMFORMING_SUPPORT +#define BEAMFORMING_SUPPORT 0 +#endif + +/*Beamforming Related*/ +#include "txbf/halcomtxbf.h" +#include "txbf/haltxbfjaguar.h" +#include "txbf/haltxbf8192e.h" +#include "txbf/haltxbf8814a.h" +#include "txbf/haltxbf8822b.h" +#include "txbf/haltxbfinterface.h" + +#if (BEAMFORMING_SUPPORT == 1) + +#define MAX_BEAMFORMEE_SU 2 +#define MAX_BEAMFORMER_SU 2 +#if (RTL8822B_SUPPORT == 1) +#define MAX_BEAMFORMEE_MU 6 +#define MAX_BEAMFORMER_MU 1 +#else +#define MAX_BEAMFORMEE_MU 0 +#define MAX_BEAMFORMER_MU 0 +#endif + +#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) +#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*for different naming between WIN and CE*/ +#define BEACON_QUEUE BCN_QUEUE_INX +#define NORMAL_QUEUE MGT_QUEUE_INX +#define RT_DISABLE_FUNC RTW_DISABLE_FUNC +#define RT_ENABLE_FUNC RTW_ENABLE_FUNC +#endif + +typedef enum _BEAMFORMING_ENTRY_STATE { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED +} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; + + +typedef enum _BEAMFORMING_NOTIFY_STATE { + BEAMFORMING_NOTIFY_NONE, + BEAMFORMING_NOTIFY_ADD, + BEAMFORMING_NOTIFY_DELETE, + BEAMFORMEE_NOTIFY_ADD_SU, + BEAMFORMEE_NOTIFY_DELETE_SU, + BEAMFORMEE_NOTIFY_ADD_MU, + BEAMFORMEE_NOTIFY_DELETE_MU, + BEAMFORMING_NOTIFY_RESET +} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE; + +typedef enum _BEAMFORMING_CAP { + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = BIT1, + BEAMFORMEE_CAP_HT_EXPLICIT = BIT2, + BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = BIT9, + BEAMFORMEE_CAP = BIT10, +}BEAMFORMING_CAP, *PBEAMFORMING_CAP; + + +typedef enum _SOUNDING_MODE { + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + SOUNDING_STOP_All_TIMER = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +}SOUNDING_MODE, *PSOUNDING_MODE; + +typedef struct _RT_BEAMFORM_STAINFO { + pu1Byte RA; + u2Byte AID; + u2Byte MacID; + u1Byte MyMacAddr[6]; + WIRELESS_MODE WirelessMode; + CHANNEL_WIDTH BW; + BEAMFORMING_CAP BeamformCap; + u1Byte HtBeamformCap; + u2Byte VhtBeamformCap; + u1Byte CurBeamform; + u2Byte CurBeamformVHT; +} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO; + + +typedef struct _RT_BEAMFORMEE_ENTRY { + BOOLEAN bUsed; + BOOLEAN bTxBF; + BOOLEAN bSound; + u2Byte AID; /*Used to construct AID field of NDPA packet.*/ + u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; /*Used to fill Tx DESC*/ + u1Byte MyMacAddr[6]; + u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/ + u2Byte SoundPeriod; + BEAMFORMING_CAP BeamformEntryCap; + BEAMFORMING_ENTRY_STATE BeamformEntryState; + BOOLEAN bBeamformingInProgress; + /*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u2Byte LogStatusFailCnt:5; // 0~21 + u2Byte DefaultCSICnt:5; // 0~21 + u1Byte CSIMatrix[327]; + u2Byte CSIMatrixLen; + u1Byte NumofSoundingDim; + u1Byte CompSteeringNumofBFer; + u1Byte su_reg_index; +#if (MU_BEAMFORMING_SUPPORT == 1) + /*For MU-MIMO*/ + BOOLEAN is_mu_sta; + u1Byte mu_reg_index; + u1Byte gid_valid[8]; + u1Byte user_position[16]; +#endif +} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY; + +typedef struct _RT_BEAMFORMER_ENTRY { + BOOLEAN bUsed; + /*P_AID of BFer entry is probably not used*/ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; + u1Byte MyMacAddr[6]; + u1Byte MacAddr[6]; + BEAMFORMING_CAP BeamformEntryCap; + u1Byte NumofSoundingDim; + u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ + u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/ + u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ + u1Byte su_reg_index; +#if (MU_BEAMFORMING_SUPPORT == 1) + /*For MU-MIMO*/ + BOOLEAN is_mu_ap; + u1Byte gid_valid[8]; + u1Byte user_position[16]; + u2Byte AID; +#endif +} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY; + +typedef struct _RT_SOUNDING_INFO { + u1Byte SoundIdx; + CHANNEL_WIDTH SoundBW; + SOUNDING_MODE SoundMode; + u2Byte SoundPeriod; +} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO; + + + +typedef struct _RT_BEAMFORMING_OID_INFO { + u1Byte SoundOidIdx; + CHANNEL_WIDTH SoundOidBW; + SOUNDING_MODE SoundOidMode; + u2Byte SoundOidPeriod; +} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO; + + +typedef struct _RT_BEAMFORMING_INFO { + BEAMFORMING_CAP BeamformCap; + RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM]; + RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM]; + RT_BEAMFORM_STAINFO BeamformSTAinfo; + u1Byte BeamformeeCurIdx; + RT_TIMER BeamformingTimer; + RT_TIMER mu_timer; + RT_SOUNDING_INFO SoundingInfo; + RT_BEAMFORMING_OID_INFO BeamformingOidInfo; + HAL_TXBF_INFO TxbfInfo; + u1Byte SoundingSequence; + u1Byte beamformee_su_cnt; + u1Byte beamformer_su_cnt; + u4Byte beamformee_su_reg_maping; + u4Byte beamformer_su_reg_maping; + /*For MU-MINO*/ + u1Byte beamformee_mu_cnt; + u1Byte beamformer_mu_cnt; + u4Byte beamformee_mu_reg_maping; + u1Byte mu_ap_index; + BOOLEAN is_mu_sounding; + u1Byte FirstMUBFeeIndex; + BOOLEAN is_mu_sounding_in_progress; + BOOLEAN dbg_disable_mu_tx; + BOOLEAN applyVmatrix; + BOOLEAN snding3SS; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER SourceAdapter; +#endif + /* Control register */ + u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */ +} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO; + + +typedef struct _RT_NDPA_STA_INFO { + u2Byte AID:12; + u2Byte FeedbackType:1; + u2Byte NcIndex:3; +} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO; + +typedef enum _PHYDM_ACTING_TYPE { + PhyDM_ACTING_AS_IBSS = 0, + PhyDM_ACTING_AS_AP = 1 +} PHYDM_ACTING_TYPE; + + +BEAMFORMING_CAP +phydm_Beamforming_GetEntryBeamCapByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId + ); + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetBFeeEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte RA, + OUT pu1Byte Idx + ); + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetBFerEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte TA, + OUT pu1Byte Idx + ); + +u1Byte +Beamforming_GetHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +u1Byte +Beamforming_GetVHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +VOID +phydm_Beamforming_Notify( + IN PVOID pDM_VOID + ); + +BOOLEAN +phydm_actingDetermine( + IN PVOID pDM_VOID, + IN PHYDM_ACTING_TYPE type + ); + +VOID +Beamforming_Enter( + IN PVOID pDM_VOID, + IN u2Byte staIdx + ); + +VOID +Beamforming_Leave( + IN PVOID pDM_VOID, + pu1Byte RA + ); + +BOOLEAN +BeamformingStart_FW( + IN PVOID pDM_VOID, + u1Byte Idx + ); + +VOID +Beamforming_CheckSoundingSuccess( + IN PVOID pDM_VOID, + BOOLEAN Status +); + +VOID +phydm_Beamforming_End_SW( + IN PVOID pDM_VOID, + BOOLEAN Status + ); + +VOID +Beamforming_TimerCallback( + IN PVOID pDM_VOID + ); + +VOID +phydm_Beamforming_Init( + IN PVOID pDM_VOID + ); + + + +BEAMFORMING_CAP +phydm_Beamforming_GetBeamCap( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo + ); + + +BOOLEAN +BeamformingControl_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + u1Byte AID, + u1Byte Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ); + + +BOOLEAN +phydm_BeamformingControl_V2( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW, + u2Byte Period + ); + +VOID +phydm_Beamforming_Watchdog( + IN PVOID pDM_VOID + ); + +VOID +Beamforming_SWTimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PRT_TIMER pTimer +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + void *FunctionContext +#endif + ); + +BOOLEAN +Beamforming_SendHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + + +BOOLEAN +Beamforming_SendVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + +#else +#define Beamforming_GidPAid(Adapter, pTcb) +#define phydm_actingDetermine(pDM_Odm, type) FALSE +#define Beamforming_Enter(pDM_Odm, staIdx) +#define Beamforming_Leave(pDM_Odm, RA) +#define Beamforming_End_FW(pDMOdm) +#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE +#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE +#define phydm_Beamforming_End_SW(pDM_Odm, _Status) +#define Beamforming_TimerCallback(pDM_Odm) +#define phydm_Beamforming_Init(pDM_Odm) +#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE +#define Beamforming_Watchdog(pDM_Odm) +#define phydm_Beamforming_Watchdog(pDM_Odm) + + +#endif +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_ccx.c b/package/kernel/rtl8192cd/phydm/phydm_ccx.c index ed139c06189..0fda865fd5f 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_ccx.c +++ b/package/kernel/rtl8192cd/phydm/phydm_ccx.c @@ -1,629 +1,629 @@ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ -VOID -phydm_NHMsetting( - IN PVOID pDM_VOID, - u1Byte NHMsetting -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - if (NHMsetting == SET_NHM_SETTING){ - - /*Set inexclude_cca, inexclude_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon); - - /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); - - /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th[10]); - - /*CCX EN*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8, CCX_EN); - - } - else if (NHMsetting == STORE_NHM_SETTING) { - - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9); - CCX_INFO->NHM_inexclude_txon_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10); - - /*Store pervious NHM period*/ - CCX_INFO->NHM_period_restore = (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord); - - /*Store NHM threshold*/ - CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1); - CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3); - CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1); - CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3); - CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3); - } - else if (NHMsetting == RESTORE_NHM_SETTING) { - - /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca_restore); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon_restore); - - /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); - - /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[10]); - } - else - return; - } - - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - if (NHMsetting == SET_NHM_SETTING){ - - /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon); - - /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period); - - /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th[10]); - - /*CCX EN*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT8, CCX_EN); - } - else if (NHMsetting == STORE_NHM_SETTING) { - - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9); - CCX_INFO->NHM_inexclude_txon_restore= (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10); - - /*Store pervious NHM period*/ - CCX_INFO->NHM_period_restore= (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord); - - /*Store NHM threshold*/ - CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1); - CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3); - CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1); - CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3); - CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3); - - } - else if (NHMsetting == RESTORE_NHM_SETTING) { - - /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca_restore); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon_restore); - - /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period_restore); - - /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th_restore[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th_restore[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th_restore[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th_restore[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th_restore[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th_restore[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th_restore[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th_restore[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th_restore[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th_restore[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th_restore[10]); - } - else - return; - - } -} - -VOID -phydm_NHMtrigger( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - /*Trigger NHM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - /*Trigger NHM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); - } -} - -VOID -phydm_getNHMresult( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - u1Byte i; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - prtl8192cd_priv priv = pDM_Odm->priv; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11AC); - CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); - CCX_INFO->NHM_result[8] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); - - /*Get NHM duration*/ - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC); - CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); - - } - - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11N); - CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); - CCX_INFO->NHM_result[8] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); - - /*Get NHM duration*/ - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); - - } - - CCX_INFO->NHM_result_total = 0; - - for (i = 0; i <= 11; i++) - CCX_INFO->NHM_result_total += CCX_INFO->NHM_result[i]; - - priv->pmib->miscEntry.nhm = 0; - for (i = 1; i <= 11; i++){ - priv->pmib->miscEntry.nhm += (CCX_INFO->NHM_result[i] * CCX_INFO->NHM_th[i-1]); - //GDEBUG("NHM_result[%d]=%d, NHM_th[%d]=%d\n", i, CCX_INFO->NHM_result[i], i-1, CCX_INFO->NHM_th[i-1] ); - } - priv->pmib->miscEntry.nhm = priv->pmib->miscEntry.nhm >> 8; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, - ("nhm_result=(H->L)[%d %d %d %d (igi) %d %d %d %d %d %d %d %d]\n", - CCX_INFO->NHM_result[11], CCX_INFO->NHM_result[10], CCX_INFO->NHM_result[9], - CCX_INFO->NHM_result[8], CCX_INFO->NHM_result[7], CCX_INFO->NHM_result[6], - CCX_INFO->NHM_result[5], CCX_INFO->NHM_result[4], CCX_INFO->NHM_result[3], - CCX_INFO->NHM_result[2], CCX_INFO->NHM_result[1], CCX_INFO->NHM_result[0])); - - -} - -BOOLEAN -phydm_checkNHMready( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32 = 0; - u1Byte i; - BOOLEAN ret = FALSE; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); - - //for (i = 0; i < 200; i ++) { - //ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16)) { - ret = 1; - //break; - } - //} - } - - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); - - //for (i = 0; i < 200; i ++) { - //ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17) ) { - ret = 1; - //break; - } - //} - } - return ret; -} - -VOID -phydm_storeNHMsetting( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - - - } -} - -VOID -phydm_CLMInit( - IN PVOID pDM_VOID, - u2Byte clm_sample_num -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// prtl8192cd_priv priv = pDM_Odm->priv; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11AC, bMaskLWord, clm_sample_num); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11N, bMaskLWord, clm_sample_num); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("CLM sampleNum = %d\n", clm_sample_num)); -} - - -VOID -phydm_CLMsetting( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ - - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, CCX_INFO->CLM_period*4)); - -} - -VOID -phydm_CLMtrigger( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1); - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1); - } -} - -BOOLEAN -phydm_checkCLMready( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32 = 0; - BOOLEAN ret = FALSE; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/ - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/ - - if ((value32 & BIT16)) - ret = TRUE; - else - ret = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); - - return ret; -} - -u2Byte -phydm_getCLMresult( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - u4Byte value32 = 0; -// u2Byte results = 0; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/ - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/ - - CCX_INFO->CLM_result = (u2Byte)(value32 & bMaskLWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, CCX_INFO->CLM_result*4)); - - return CCX_INFO->CLM_result; -} - - -void -phydm_set_nhm_th_by_igi( - IN PVOID pDM_VOID, - u8 igi -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - u8 i, cca_cap = 14; - - CCX_INFO->echo_IGI = igi; - CCX_INFO->NHM_th[0] = (CCX_INFO->echo_IGI - cca_cap) * IGI_TO_NHM_TH_MULTIPLIER; - for (i = 1; i <= 10; i++) - CCX_INFO->NHM_th[i] = CCX_INFO->NHM_th[0] + 2 * IGI_TO_NHM_TH_MULTIPLIER * i; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]echo_igi=0x%x\n", __func__, CCX_INFO->echo_IGI)); -} - -bool -phydm_ccx_chk_rdy( - IN PVOID pDM_VOID, - u16 monitor_time /*unit ms*/ -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - bool NHM_rdy, CLM_rdy; - - NHM_rdy = phydm_checkNHMready(pDM_Odm); - CLM_rdy = phydm_checkCLMready(pDM_Odm); - - if (NHM_rdy & CLM_rdy) - return TRUE; - else - return FALSE; -} - - -void -phydm_ccx_trigger( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - -/* - if (!(pDM_Odm->support_ability & ODM_BB_ENV_MONITOR)) - return; -*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]===>\n", __FUNCTION__)); - - phydm_NHMtrigger(pDM_Odm); - phydm_CLMtrigger(pDM_Odm); -} - -void -phydm_ccx_setting( - IN PVOID pDM_VOID, - u16 monitor_time, /*unit ms*/ - u8 IGI, - bool NHM_inexclude_cca -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - u8 nhm_th[11], i, ms_to_four_us = 250; - - /* check if NHM threshold is changed */ - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - nhm_th[0] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0); - nhm_th[1] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1); - nhm_th[2] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2); - nhm_th[3] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3); - nhm_th[4] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0); - nhm_th[5] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1); - nhm_th[6] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2); - nhm_th[7] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3); - nhm_th[8] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0); - nhm_th[9] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2); - nhm_th[10] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3); - - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - nhm_th[0] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0); - nhm_th[1] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1); - nhm_th[2] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2); - nhm_th[3] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3); - nhm_th[4] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0); - nhm_th[5] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1); - nhm_th[6] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2); - nhm_th[7] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3); - nhm_th[8] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0); - nhm_th[9] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2); - nhm_th[10] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3); - } - - for (i = 0; i <= 10; i++) { - - if (nhm_th[i] != CCX_INFO->NHM_th[i]) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, - ("nhm_th[%d] != CCX_INFO->nhm_th[%d]!!\n", i, i)); - } - } - - if (monitor_time == CCX_PERIOD_FULL) { - CCX_INFO->NHM_period = 0xffff; - CCX_INFO->CLM_period = 0xffff; - } else { - CCX_INFO->NHM_period = monitor_time * ms_to_four_us; - CCX_INFO->CLM_period = CCX_INFO->NHM_period; - } - - phydm_set_nhm_th_by_igi(pDM_Odm, IGI); - - CCX_INFO->NHM_inexclude_cca = NHM_inexclude_cca; //NHM_EXCLUDE_CCA; - CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; - - phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); - - CCX_INFO->echo_CLM_en = true; - phydm_CLMsetting(pDM_Odm); - -} - -VOID -phydm_ccx_result( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - u4Byte clm_ratio = 0, nhm_ratio = 0; - - phydm_getNHMresult(pDM_Odm); - phydm_getCLMresult(pDM_Odm); - - if (CCX_INFO->CLM_period != 0) { - if (CCX_INFO->NHM_period == 0xffff) - clm_ratio = (CCX_INFO->CLM_result * 100) >> 16; - else - clm_ratio = (CCX_INFO->CLM_result * 100) / CCX_INFO->CLM_period; - } - - nhm_ratio = ((CCX_INFO->NHM_result_total - CCX_INFO->NHM_result[0])*100) >> 8; - - CCX_INFO->CLM_ratio = (u8)clm_ratio; - CCX_INFO->NHM_ratio = (u8)nhm_ratio; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]echo_igi=0x%x, nhm_ratio=%d, clm_ratio=%d\n", - __FUNCTION__, CCX_INFO->echo_IGI, nhm_ratio, clm_ratio)); -} - -#if (PHYDM_CCX_LNA_CHK_SUPPORT == 1) -VOID -phydm_ccx_lna_chk_setting( - IN PVOID pDM_VOID - -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1 ,IGI_FOR_SAT_SCAN); - phydm_ccx_setting(pDM_Odm, CCX_PERIOD_FOR_SCAN, IGI_FOR_SAT_SCAN, NHM_INCLUDE_CCA); -} - -void -phydm_ccx_lna_chk_trigger( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - phydm_ccx_trigger(pDM_Odm); -} - -void -phydm_ccx_lna_chk_result( - IN PVOID pDM_VOID - -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - phydm_ccx_result(pDM_Odm); - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1 ,IGI_FOR_SAT_SCAN); -} -#endif +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ +VOID +phydm_NHMsetting( + IN PVOID pDM_VOID, + u1Byte NHMsetting +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + if (NHMsetting == SET_NHM_SETTING){ + + /*Set inexclude_cca, inexclude_txon*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon); + + /*Set NHM period*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); + + /*Set NHM threshold*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th[0]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th[1]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th[2]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th[3]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th[4]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th[5]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th[6]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th[7]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th[8]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th[9]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th[10]); + + /*CCX EN*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8, CCX_EN); + + } + else if (NHMsetting == STORE_NHM_SETTING) { + + /*Store pervious disable_ignore_cca, disable_ignore_txon*/ + CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9); + CCX_INFO->NHM_inexclude_txon_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10); + + /*Store pervious NHM period*/ + CCX_INFO->NHM_period_restore = (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord); + + /*Store NHM threshold*/ + CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0); + CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1); + CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2); + CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3); + CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0); + CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1); + CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2); + CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3); + CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0); + CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2); + CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3); + } + else if (NHMsetting == RESTORE_NHM_SETTING) { + + /*Set disable_ignore_cca, disable_ignore_txon*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca_restore); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon_restore); + + /*Set NHM period*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); + + /*Set NHM threshold*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[0]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[1]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[2]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[3]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[4]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[5]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[6]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[7]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[8]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[9]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[10]); + } + else + return; + } + + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + if (NHMsetting == SET_NHM_SETTING){ + + /*Set disable_ignore_cca, disable_ignore_txon*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon); + + /*Set NHM period*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period); + + /*Set NHM threshold*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th[0]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th[1]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th[2]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th[3]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th[4]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th[5]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th[6]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th[7]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th[8]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th[9]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th[10]); + + /*CCX EN*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT8, CCX_EN); + } + else if (NHMsetting == STORE_NHM_SETTING) { + + /*Store pervious disable_ignore_cca, disable_ignore_txon*/ + CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9); + CCX_INFO->NHM_inexclude_txon_restore= (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10); + + /*Store pervious NHM period*/ + CCX_INFO->NHM_period_restore= (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord); + + /*Store NHM threshold*/ + CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0); + CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1); + CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2); + CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3); + CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0); + CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1); + CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2); + CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3); + CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0); + CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2); + CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3); + + } + else if (NHMsetting == RESTORE_NHM_SETTING) { + + /*Set disable_ignore_cca, disable_ignore_txon*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca_restore); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon_restore); + + /*Set NHM period*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period_restore); + + /*Set NHM threshold*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th_restore[0]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th_restore[1]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th_restore[2]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th_restore[3]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th_restore[4]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th_restore[5]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th_restore[6]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th_restore[7]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th_restore[8]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th_restore[9]); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th_restore[10]); + } + else + return; + + } +} + +VOID +phydm_NHMtrigger( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + /*Trigger NHM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + /*Trigger NHM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); + } +} + +VOID +phydm_getNHMresult( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32; + u1Byte i; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + prtl8192cd_priv priv = pDM_Odm->priv; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11AC); + CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); + CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); + CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); + CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); + CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); + CCX_INFO->NHM_result[8] = (u1Byte)(value32 & bMaskByte0); + CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte1) >> 8); + CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); + + /*Get NHM duration*/ + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC); + CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); + + } + + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11N); + CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); + CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); + CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); + CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); + CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); + CCX_INFO->NHM_result[8] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte3) >> 24); + + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); + CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); + + /*Get NHM duration*/ + value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); + + } + + CCX_INFO->NHM_result_total = 0; + + for (i = 0; i <= 11; i++) + CCX_INFO->NHM_result_total += CCX_INFO->NHM_result[i]; + + priv->pmib->miscEntry.nhm = 0; + for (i = 1; i <= 11; i++){ + priv->pmib->miscEntry.nhm += (CCX_INFO->NHM_result[i] * CCX_INFO->NHM_th[i-1]); + //GDEBUG("NHM_result[%d]=%d, NHM_th[%d]=%d\n", i, CCX_INFO->NHM_result[i], i-1, CCX_INFO->NHM_th[i-1] ); + } + priv->pmib->miscEntry.nhm = priv->pmib->miscEntry.nhm >> 8; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, + ("nhm_result=(H->L)[%d %d %d %d (igi) %d %d %d %d %d %d %d %d]\n", + CCX_INFO->NHM_result[11], CCX_INFO->NHM_result[10], CCX_INFO->NHM_result[9], + CCX_INFO->NHM_result[8], CCX_INFO->NHM_result[7], CCX_INFO->NHM_result[6], + CCX_INFO->NHM_result[5], CCX_INFO->NHM_result[4], CCX_INFO->NHM_result[3], + CCX_INFO->NHM_result[2], CCX_INFO->NHM_result[1], CCX_INFO->NHM_result[0])); + + +} + +BOOLEAN +phydm_checkNHMready( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32 = 0; + u1Byte i; + BOOLEAN ret = FALSE; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); + + //for (i = 0; i < 200; i ++) { + //ODM_delay_ms(1); + if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16)) { + ret = 1; + //break; + } + //} + } + + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); + + //for (i = 0; i < 200; i ++) { + //ODM_delay_ms(1); + if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17) ) { + ret = 1; + //break; + } + //} + } + return ret; +} + +VOID +phydm_storeNHMsetting( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + + + } +} + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + u2Byte clm_sample_num +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// prtl8192cd_priv priv = pDM_Odm->priv; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11AC, bMaskLWord, clm_sample_num); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11N, bMaskLWord, clm_sample_num); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("CLM sampleNum = %d\n", clm_sample_num)); +} + + +VOID +phydm_CLMsetting( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ + + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, CCX_INFO->CLM_period*4)); + +} + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1); + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1); + } +} + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32 = 0; + BOOLEAN ret = FALSE; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/ + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/ + + if ((value32 & BIT16)) + ret = TRUE; + else + ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + + return ret; +} + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + u4Byte value32 = 0; +// u2Byte results = 0; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/ + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/ + + CCX_INFO->CLM_result = (u2Byte)(value32 & bMaskLWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, CCX_INFO->CLM_result*4)); + + return CCX_INFO->CLM_result; +} + + +void +phydm_set_nhm_th_by_igi( + IN PVOID pDM_VOID, + u8 igi +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + u8 i, cca_cap = 14; + + CCX_INFO->echo_IGI = igi; + CCX_INFO->NHM_th[0] = (CCX_INFO->echo_IGI - cca_cap) * IGI_TO_NHM_TH_MULTIPLIER; + for (i = 1; i <= 10; i++) + CCX_INFO->NHM_th[i] = CCX_INFO->NHM_th[0] + 2 * IGI_TO_NHM_TH_MULTIPLIER * i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]echo_igi=0x%x\n", __func__, CCX_INFO->echo_IGI)); +} + +bool +phydm_ccx_chk_rdy( + IN PVOID pDM_VOID, + u16 monitor_time /*unit ms*/ +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + bool NHM_rdy, CLM_rdy; + + NHM_rdy = phydm_checkNHMready(pDM_Odm); + CLM_rdy = phydm_checkCLMready(pDM_Odm); + + if (NHM_rdy & CLM_rdy) + return TRUE; + else + return FALSE; +} + + +void +phydm_ccx_trigger( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + +/* + if (!(pDM_Odm->support_ability & ODM_BB_ENV_MONITOR)) + return; +*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]===>\n", __FUNCTION__)); + + phydm_NHMtrigger(pDM_Odm); + phydm_CLMtrigger(pDM_Odm); +} + +void +phydm_ccx_setting( + IN PVOID pDM_VOID, + u16 monitor_time, /*unit ms*/ + u8 IGI, + bool NHM_inexclude_cca +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + u8 nhm_th[11], i, ms_to_four_us = 250; + + /* check if NHM threshold is changed */ + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + + nhm_th[0] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0); + nhm_th[1] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1); + nhm_th[2] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2); + nhm_th[3] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3); + nhm_th[4] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0); + nhm_th[5] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1); + nhm_th[6] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2); + nhm_th[7] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3); + nhm_th[8] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0); + nhm_th[9] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2); + nhm_th[10] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3); + + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + + nhm_th[0] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0); + nhm_th[1] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1); + nhm_th[2] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2); + nhm_th[3] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3); + nhm_th[4] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0); + nhm_th[5] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1); + nhm_th[6] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2); + nhm_th[7] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3); + nhm_th[8] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0); + nhm_th[9] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2); + nhm_th[10] = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3); + } + + for (i = 0; i <= 10; i++) { + + if (nhm_th[i] != CCX_INFO->NHM_th[i]) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, + ("nhm_th[%d] != CCX_INFO->nhm_th[%d]!!\n", i, i)); + } + } + + if (monitor_time == CCX_PERIOD_FULL) { + CCX_INFO->NHM_period = 0xffff; + CCX_INFO->CLM_period = 0xffff; + } else { + CCX_INFO->NHM_period = monitor_time * ms_to_four_us; + CCX_INFO->CLM_period = CCX_INFO->NHM_period; + } + + phydm_set_nhm_th_by_igi(pDM_Odm, IGI); + + CCX_INFO->NHM_inexclude_cca = NHM_inexclude_cca; //NHM_EXCLUDE_CCA; + CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; + + phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); + + CCX_INFO->echo_CLM_en = true; + phydm_CLMsetting(pDM_Odm); + +} + +VOID +phydm_ccx_result( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + u4Byte clm_ratio = 0, nhm_ratio = 0; + + phydm_getNHMresult(pDM_Odm); + phydm_getCLMresult(pDM_Odm); + + if (CCX_INFO->CLM_period != 0) { + if (CCX_INFO->NHM_period == 0xffff) + clm_ratio = (CCX_INFO->CLM_result * 100) >> 16; + else + clm_ratio = (CCX_INFO->CLM_result * 100) / CCX_INFO->CLM_period; + } + + nhm_ratio = ((CCX_INFO->NHM_result_total - CCX_INFO->NHM_result[0])*100) >> 8; + + CCX_INFO->CLM_ratio = (u8)clm_ratio; + CCX_INFO->NHM_ratio = (u8)nhm_ratio; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s]echo_igi=0x%x, nhm_ratio=%d, clm_ratio=%d\n", + __FUNCTION__, CCX_INFO->echo_IGI, nhm_ratio, clm_ratio)); +} + +#if (PHYDM_CCX_LNA_CHK_SUPPORT == 1) +VOID +phydm_ccx_lna_chk_setting( + IN PVOID pDM_VOID + +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1 ,IGI_FOR_SAT_SCAN); + phydm_ccx_setting(pDM_Odm, CCX_PERIOD_FOR_SCAN, IGI_FOR_SAT_SCAN, NHM_INCLUDE_CCA); +} + +void +phydm_ccx_lna_chk_trigger( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + phydm_ccx_trigger(pDM_Odm); +} + +void +phydm_ccx_lna_chk_result( + IN PVOID pDM_VOID + +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + phydm_ccx_result(pDM_Odm); + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1 ,IGI_FOR_SAT_SCAN); +} +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_ccx.h b/package/kernel/rtl8192cd/phydm/phydm_ccx.h index f84fb89c44e..fbe6a554648 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_ccx.h +++ b/package/kernel/rtl8192cd/phydm/phydm_ccx.h @@ -1,133 +1,133 @@ -#ifndef __PHYDMCCX_H__ -#define __PHYDMCCX_H__ - -#define CCX_EN 1 -#define CCX_PERIOD_FULL 0xff -#define CCX_PERIOD_FOR_SCAN 10 // 10ms -#define IGI_FOR_SAT_SCAN 0x46 - -#define SET_NHM_SETTING 0 -#define STORE_NHM_SETTING 1 -#define RESTORE_NHM_SETTING 2 - -/* -#define NHM_EXCLUDE_CCA 0 -#define NHM_INCLUDE_CCA 1 -#define NHM_EXCLUDE_TXON 0 -#define NHM_INCLUDE_TXON 1 -*/ - -typedef enum NHM_inexclude_cca { - NHM_EXCLUDE_CCA, - NHM_INCLUDE_CCA -}NHM_INEXCLUDE_CCA; - -typedef enum NHM_inexclude_txon { - NHM_EXCLUDE_TXON, - NHM_INCLUDE_TXON -}NHM_INEXCLUDE_TXON; - - -typedef struct _CCX_INFO{ - - /*Settings*/ - u1Byte NHM_th[11]; - u2Byte NHM_period; /* 4us per unit */ - u2Byte CLM_period; /* 4us per unit */ - NHM_INEXCLUDE_TXON NHM_inexclude_txon; - NHM_INEXCLUDE_CCA NHM_inexclude_cca; - - /*Previous Settings*/ - u1Byte NHM_th_restore[11]; - u2Byte NHM_period_restore; /* 4us per unit */ - u2Byte CLM_period_restore; /* 4us per unit */ - NHM_INEXCLUDE_TXON NHM_inexclude_txon_restore; - NHM_INEXCLUDE_CCA NHM_inexclude_cca_restore; - - /*Report*/ - u1Byte NHM_result[12]; - u1Byte NHM_result_total; - u2Byte NHM_duration; - u2Byte CLM_result; - u1Byte CLM_ratio; - u1Byte NHM_ratio; - - BOOLEAN echo_NHM_en; - BOOLEAN echo_CLM_en; - u1Byte echo_IGI; - -}CCX_INFO, *PCCX_INFO; - -/*NHM*/ - -VOID -phydm_NHMsetting( - IN PVOID pDM_VOID, - u1Byte NHMsetting -); - -VOID -phydm_NHMtrigger( - IN PVOID pDM_VOID -); - -VOID -phydm_getNHMresult( - IN PVOID pDM_VOID -); - -BOOLEAN -phydm_checkNHMready( - IN PVOID pDM_VOID -); - -/*CLM*/ - -VOID -phydm_CLMInit( - IN PVOID pDM_VOID, - u2Byte clm_sample_num -); - -VOID -phydm_CLMsetting( - IN PVOID pDM_VOID -); - -VOID -phydm_CLMtrigger( - IN PVOID pDM_VOID -); - -BOOLEAN -phydm_checkCLMready( - IN PVOID pDM_VOID -); - -u2Byte -phydm_getCLMresult( - IN PVOID pDM_VOID -); - -#if (PHYDM_CCX_LNA_CHK_SUPPORT == 1) - -VOID -phydm_ccx_lna_chk_setting( - IN PVOID pDM_VOID - -); - -void -phydm_ccx_lna_chk_trigger( - IN PVOID pDM_VOID -); - -void -phydm_ccx_lna_chk_result( - IN PVOID pDM_VOID - -); - -#endif - -#endif +#ifndef __PHYDMCCX_H__ +#define __PHYDMCCX_H__ + +#define CCX_EN 1 +#define CCX_PERIOD_FULL 0xff +#define CCX_PERIOD_FOR_SCAN 10 // 10ms +#define IGI_FOR_SAT_SCAN 0x46 + +#define SET_NHM_SETTING 0 +#define STORE_NHM_SETTING 1 +#define RESTORE_NHM_SETTING 2 + +/* +#define NHM_EXCLUDE_CCA 0 +#define NHM_INCLUDE_CCA 1 +#define NHM_EXCLUDE_TXON 0 +#define NHM_INCLUDE_TXON 1 +*/ + +typedef enum NHM_inexclude_cca { + NHM_EXCLUDE_CCA, + NHM_INCLUDE_CCA +}NHM_INEXCLUDE_CCA; + +typedef enum NHM_inexclude_txon { + NHM_EXCLUDE_TXON, + NHM_INCLUDE_TXON +}NHM_INEXCLUDE_TXON; + + +typedef struct _CCX_INFO{ + + /*Settings*/ + u1Byte NHM_th[11]; + u2Byte NHM_period; /* 4us per unit */ + u2Byte CLM_period; /* 4us per unit */ + NHM_INEXCLUDE_TXON NHM_inexclude_txon; + NHM_INEXCLUDE_CCA NHM_inexclude_cca; + + /*Previous Settings*/ + u1Byte NHM_th_restore[11]; + u2Byte NHM_period_restore; /* 4us per unit */ + u2Byte CLM_period_restore; /* 4us per unit */ + NHM_INEXCLUDE_TXON NHM_inexclude_txon_restore; + NHM_INEXCLUDE_CCA NHM_inexclude_cca_restore; + + /*Report*/ + u1Byte NHM_result[12]; + u1Byte NHM_result_total; + u2Byte NHM_duration; + u2Byte CLM_result; + u1Byte CLM_ratio; + u1Byte NHM_ratio; + + BOOLEAN echo_NHM_en; + BOOLEAN echo_CLM_en; + u1Byte echo_IGI; + +}CCX_INFO, *PCCX_INFO; + +/*NHM*/ + +VOID +phydm_NHMsetting( + IN PVOID pDM_VOID, + u1Byte NHMsetting +); + +VOID +phydm_NHMtrigger( + IN PVOID pDM_VOID +); + +VOID +phydm_getNHMresult( + IN PVOID pDM_VOID +); + +BOOLEAN +phydm_checkNHMready( + IN PVOID pDM_VOID +); + +/*CLM*/ + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + u2Byte clm_sample_num +); + +VOID +phydm_CLMsetting( + IN PVOID pDM_VOID +); + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +); + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +); + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +); + +#if (PHYDM_CCX_LNA_CHK_SUPPORT == 1) + +VOID +phydm_ccx_lna_chk_setting( + IN PVOID pDM_VOID + +); + +void +phydm_ccx_lna_chk_trigger( + IN PVOID pDM_VOID +); + +void +phydm_ccx_lna_chk_result( + IN PVOID pDM_VOID + +); + +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_cfotracking.c b/package/kernel/rtl8192cd/phydm/phydm_cfotracking.c index 9b4e1a50bb2..c507d99a367 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_cfotracking.c +++ b/package/kernel/rtl8192cd/phydm/phydm_cfotracking.c @@ -1,387 +1,387 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -odm_SetCrystalCap( - IN PVOID pDM_VOID, - IN u1Byte CrystalCap -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - - if(pCfoTrack->CrystalCap == CrystalCap) - return; - - pCfoTrack->CrystalCap = CrystalCap; - - if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { - /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8812) { - /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); - } else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { - /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { - /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8822B|ODM_RTL8197F) { - /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); - ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); -#endif -} - -u1Byte -odm_GetDefaultCrytaltalCap( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte CrystalCap = 0x20; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - CrystalCap = pHalData->CrystalCap; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - - if(priv->pmib->dot11RFEntry.xcap > 0) - CrystalCap = priv->pmib->dot11RFEntry.xcap; -#endif - - CrystalCap = CrystalCap & 0x3f; - - return CrystalCap; -} - -VOID -odm_SetATCStatus( - IN PVOID pDM_VOID, - IN BOOLEAN ATCStatus -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - - if(pCfoTrack->bATCStatus == ATCStatus) - return; - - ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus); - pCfoTrack->bATCStatus = ATCStatus; -} - -BOOLEAN -odm_GetATCStatus( - IN PVOID pDM_VOID -) -{ - BOOLEAN ATCStatus; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm)); - return ATCStatus; -} - -VOID -ODM_CfoTrackingReset( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - - pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bAdjust = TRUE; - - if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) - { - odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); - } else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap) - { - odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); - } - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) - odm_SetATCStatus(pDM_Odm, TRUE); - #endif -} - -VOID -ODM_CfoTrackingInit( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - - pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); - pCfoTrack->bAdjust = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x\n", pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); - -#if RTL8822B_SUPPORT - /* Crystal cap. control by WiFi */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x10, 0x40, 0x1); -#endif -} - -VOID -ODM_CfoTracking( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - s4Byte CFO_ave = 0; - u4Byte CFO_rpt_sum, CFO_kHz_avg[2] = {0}; - s4Byte CFO_ave_diff; - s1Byte CrystalCap = pCfoTrack->CrystalCap; - u1Byte Adjust_Xtal = 1, i, valid_path_cnt = 0; -/* - //4 Support ability - if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n")); - return; - } -*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n")); - - if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) - { - //4 No link or more than one entry - ODM_CfoTrackingReset(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n", - pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly)); - } - else - { - //3 1. CFO Tracking - //4 1.1 No new packet - if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n")); - return; - } - pCfoTrack->packetCount_pre = pCfoTrack->packetCount; - - //4 1.2 Calculate CFO - for (i = 0; i < pDM_Odm->num_rf_path; i++) { - - if (pCfoTrack->CFO_cnt[i] == 0) - continue; - - valid_path_cnt++; - CFO_rpt_sum = (u4Byte)((pCfoTrack->CFO_tail[i] < 0) ? (0 - pCfoTrack->CFO_tail[i]) : pCfoTrack->CFO_tail[i]); - CFO_kHz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / pCfoTrack->CFO_cnt[i]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[Path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", - i, CFO_rpt_sum, pCfoTrack->CFO_cnt[i],((pCfoTrack->CFO_tail[i] < 0) ? "-" : " ") ,CFO_kHz_avg[i])); - } - - for (i = 0; i < valid_path_cnt; i++) { - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], pCfoTrack->CFO_tail = %d\n", i, pCfoTrack->CFO_tail[i])); - if (pCfoTrack->CFO_tail[i] < 0) { - CFO_ave += (0-(s4Byte)CFO_kHz_avg[i]); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); - } - else - CFO_ave += (s4Byte)CFO_kHz_avg[i]; - } - - if (valid_path_cnt == 2) - CFO_ave = (CFO_ave>>1); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); - - /*reset counter*/ - for (i = 0; i < pDM_Odm->num_rf_path; i++) { - pCfoTrack->CFO_tail[i] = 0; - pCfoTrack->CFO_cnt[i] = 0; - } - - //4 Support ability - if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) - { - odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled & use default crystal cap!!\n")); - return; - } - - //4 1.3 Avoid abnormal large CFO - CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre); - if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n")); - pCfoTrack->largeCFOHit = 1; - return; - } - else - pCfoTrack->largeCFOHit = 0; - pCfoTrack->CFO_ave_pre = CFO_ave; - - //4 1.4 Dynamic Xtal threshold - if(pCfoTrack->bAdjust == FALSE) - { - if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) - pCfoTrack->bAdjust = TRUE; - } - else - { - if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) - pCfoTrack->bAdjust = FALSE; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) - //4 1.5 BT case: Disable CFO tracking - -#ifdef ENABLE_BT_COEXIST -// extern u8 halbtc8812a2ant_getBTdisable(void); -// pDM_Odm->bBtEnabled = rtw_btcoex_IsBtDisabled(priv); -#else - pDM_Odm->bBtEnabled = true; -#endif - if(pDM_Odm->bBtEnabled) - { - pCfoTrack->bAdjust = FALSE; - odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n")); - } - -/* - //4 1.6 Big jump - if(pCfoTrack->bAdjust) - { - if(CFO_ave > CFO_TH_XTAL_LOW) - Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); - else if(CFO_ave < (-CFO_TH_XTAL_LOW)) - Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal)); - } -*/ -#endif - - //4 1.7 Adjust Crystal Cap. - if(pCfoTrack->bAdjust) - { - if(CFO_ave > CFO_TH_XTAL_LOW) - CrystalCap = CrystalCap + Adjust_Xtal; - else if(CFO_ave < (-CFO_TH_XTAL_LOW)) - CrystalCap = CrystalCap - Adjust_Xtal; - - if(CrystalCap > 0x3f) - CrystalCap = 0x3f; - else if (CrystalCap < 0) - CrystalCap = 0; - - odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", - pCfoTrack->CrystalCap, pCfoTrack->DefXCap)); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - return; - - //3 2. Dynamic ATC switch - if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) - { - odm_SetATCStatus(pDM_Odm, FALSE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n")); - } - else - { - odm_SetATCStatus(pDM_Odm, TRUE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n")); - } -#endif - } -} - -VOID -ODM_ParsingCFO( - IN PVOID pDM_VOID, - IN PVOID pPktinfo_VOID, - IN s1Byte* pcfotail, - IN u1Byte num_ss - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - u1Byte i; -/* - if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) - return; -*/ -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pPktinfo->bPacketMatchBSSID) -#else - if(pPktinfo->StationID != 0) -#endif - { - if (num_ss > pDM_Odm->num_rf_path) /*For fool proof*/ - num_ss = pDM_Odm->num_rf_path; - - //3 Update CFO report for path-A & path-B - // Only paht-A and path-B have CFO tail and short CFO - for(i = 0; i < num_ss; i++) - { - pCfoTrack->CFO_tail[i] += pcfotail[i]; - pCfoTrack->CFO_cnt[i] ++; - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][Rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", - // pPktinfo->StationID, i, pPktinfo->DataRate, pcfotail[i], pCfoTrack->CFO_tail[i], pCfoTrack->CFO_cnt[i])); - } - - //3 Update packet counter - if(pCfoTrack->packetCount == 0xffffffff) - pCfoTrack->packetCount = 0; - else - pCfoTrack->packetCount++; - } -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +odm_SetCrystalCap( + IN PVOID pDM_VOID, + IN u1Byte CrystalCap +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + if(pCfoTrack->CrystalCap == CrystalCap) + return; + + pCfoTrack->CrystalCap = CrystalCap; + + if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { + /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8812) { + /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); + } else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { + /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { + /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8822B|ODM_RTL8197F) { + /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); + ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); +#endif +} + +u1Byte +odm_GetDefaultCrytaltalCap( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte CrystalCap = 0x20; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + CrystalCap = pHalData->CrystalCap; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + + if(priv->pmib->dot11RFEntry.xcap > 0) + CrystalCap = priv->pmib->dot11RFEntry.xcap; +#endif + + CrystalCap = CrystalCap & 0x3f; + + return CrystalCap; +} + +VOID +odm_SetATCStatus( + IN PVOID pDM_VOID, + IN BOOLEAN ATCStatus +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + if(pCfoTrack->bATCStatus == ATCStatus) + return; + + ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus); + pCfoTrack->bATCStatus = ATCStatus; +} + +BOOLEAN +odm_GetATCStatus( + IN PVOID pDM_VOID +) +{ + BOOLEAN ATCStatus; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm)); + return ATCStatus; +} + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm); + pCfoTrack->bAdjust = TRUE; + + if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) + { + odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); + } else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap) + { + odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); + } + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) + odm_SetATCStatus(pDM_Odm, TRUE); + #endif +} + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); + pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); + pCfoTrack->bAdjust = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x\n", pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); + +#if RTL8822B_SUPPORT + /* Crystal cap. control by WiFi */ + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ODM_SetBBReg(pDM_Odm, 0x10, 0x40, 0x1); +#endif +} + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + s4Byte CFO_ave = 0; + u4Byte CFO_rpt_sum, CFO_kHz_avg[2] = {0}; + s4Byte CFO_ave_diff; + s1Byte CrystalCap = pCfoTrack->CrystalCap; + u1Byte Adjust_Xtal = 1, i, valid_path_cnt = 0; +/* + //4 Support ability + if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n")); + return; + } +*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n")); + + if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) + { + //4 No link or more than one entry + ODM_CfoTrackingReset(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n", + pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly)); + } + else + { + //3 1. CFO Tracking + //4 1.1 No new packet + if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n")); + return; + } + pCfoTrack->packetCount_pre = pCfoTrack->packetCount; + + //4 1.2 Calculate CFO + for (i = 0; i < pDM_Odm->num_rf_path; i++) { + + if (pCfoTrack->CFO_cnt[i] == 0) + continue; + + valid_path_cnt++; + CFO_rpt_sum = (u4Byte)((pCfoTrack->CFO_tail[i] < 0) ? (0 - pCfoTrack->CFO_tail[i]) : pCfoTrack->CFO_tail[i]); + CFO_kHz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / pCfoTrack->CFO_cnt[i]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[Path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", + i, CFO_rpt_sum, pCfoTrack->CFO_cnt[i],((pCfoTrack->CFO_tail[i] < 0) ? "-" : " ") ,CFO_kHz_avg[i])); + } + + for (i = 0; i < valid_path_cnt; i++) { + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], pCfoTrack->CFO_tail = %d\n", i, pCfoTrack->CFO_tail[i])); + if (pCfoTrack->CFO_tail[i] < 0) { + CFO_ave += (0-(s4Byte)CFO_kHz_avg[i]); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); + } + else + CFO_ave += (s4Byte)CFO_kHz_avg[i]; + } + + if (valid_path_cnt == 2) + CFO_ave = (CFO_ave>>1); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); + + /*reset counter*/ + for (i = 0; i < pDM_Odm->num_rf_path; i++) { + pCfoTrack->CFO_tail[i] = 0; + pCfoTrack->CFO_cnt[i] = 0; + } + + //4 Support ability + if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + { + odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled & use default crystal cap!!\n")); + return; + } + + //4 1.3 Avoid abnormal large CFO + CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre); + if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n")); + pCfoTrack->largeCFOHit = 1; + return; + } + else + pCfoTrack->largeCFOHit = 0; + pCfoTrack->CFO_ave_pre = CFO_ave; + + //4 1.4 Dynamic Xtal threshold + if(pCfoTrack->bAdjust == FALSE) + { + if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) + pCfoTrack->bAdjust = TRUE; + } + else + { + if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) + pCfoTrack->bAdjust = FALSE; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) + //4 1.5 BT case: Disable CFO tracking + +#ifdef ENABLE_BT_COEXIST +// extern u8 halbtc8812a2ant_getBTdisable(void); +// pDM_Odm->bBtEnabled = rtw_btcoex_IsBtDisabled(priv); +#else + pDM_Odm->bBtEnabled = true; +#endif + if(pDM_Odm->bBtEnabled) + { + pCfoTrack->bAdjust = FALSE; + odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n")); + } + +/* + //4 1.6 Big jump + if(pCfoTrack->bAdjust) + { + if(CFO_ave > CFO_TH_XTAL_LOW) + Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); + else if(CFO_ave < (-CFO_TH_XTAL_LOW)) + Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal)); + } +*/ +#endif + + //4 1.7 Adjust Crystal Cap. + if(pCfoTrack->bAdjust) + { + if(CFO_ave > CFO_TH_XTAL_LOW) + CrystalCap = CrystalCap + Adjust_Xtal; + else if(CFO_ave < (-CFO_TH_XTAL_LOW)) + CrystalCap = CrystalCap - Adjust_Xtal; + + if(CrystalCap > 0x3f) + CrystalCap = 0x3f; + else if (CrystalCap < 0) + CrystalCap = 0; + + odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", + pCfoTrack->CrystalCap, pCfoTrack->DefXCap)); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP)) + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + return; + + //3 2. Dynamic ATC switch + if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) + { + odm_SetATCStatus(pDM_Odm, FALSE); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n")); + } + else + { + odm_SetATCStatus(pDM_Odm, TRUE); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n")); + } +#endif + } +} + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail, + IN u1Byte num_ss + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + u1Byte i; +/* + if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + return; +*/ +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pPktinfo->bPacketMatchBSSID) +#else + if(pPktinfo->StationID != 0) +#endif + { + if (num_ss > pDM_Odm->num_rf_path) /*For fool proof*/ + num_ss = pDM_Odm->num_rf_path; + + //3 Update CFO report for path-A & path-B + // Only paht-A and path-B have CFO tail and short CFO + for(i = 0; i < num_ss; i++) + { + pCfoTrack->CFO_tail[i] += pcfotail[i]; + pCfoTrack->CFO_cnt[i] ++; + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][Rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", + // pPktinfo->StationID, i, pPktinfo->DataRate, pcfotail[i], pCfoTrack->CFO_tail[i], pCfoTrack->CFO_cnt[i])); + } + + //3 Update packet counter + if(pCfoTrack->packetCount == 0xffffffff) + pCfoTrack->packetCount = 0; + else + pCfoTrack->packetCount++; + } +} + diff --git a/package/kernel/rtl8192cd/phydm/phydm_cfotracking.h b/package/kernel/rtl8192cd/phydm/phydm_cfotracking.h index 2b902cbf197..80b90e61a98 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_cfotracking.h +++ b/package/kernel/rtl8192cd/phydm/phydm_cfotracking.h @@ -1,70 +1,70 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMCFOTRACK_H__ -#define __PHYDMCFOTRACK_H__ - -#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ - -#define CFO_TH_XTAL_HIGH 5 //20 // kHz -#define CFO_TH_XTAL_LOW 5//10 // kHz -#define CFO_TH_ATC 80 // kHz - -typedef struct _CFO_TRACKING_ -{ - BOOLEAN bATCStatus; - BOOLEAN largeCFOHit; - BOOLEAN bAdjust; - u1Byte CrystalCap; - u1Byte DefXCap; - s4Byte CFO_tail[4]; - u4Byte CFO_cnt[4]; - s4Byte CFO_ave_pre; - u4Byte packetCount; - u4Byte packetCount_pre; - - BOOLEAN bForceXtalCap; - BOOLEAN bReset; -}CFO_TRACKING, *PCFO_TRACKING; - -VOID -ODM_CfoTrackingReset( - IN PVOID pDM_VOID -); - -VOID -ODM_CfoTrackingInit( - IN PVOID pDM_VOID -); - -VOID -ODM_CfoTracking( - IN PVOID pDM_VOID -); - -VOID -ODM_ParsingCFO( - IN PVOID pDM_VOID, - IN PVOID pPktinfo_VOID, - IN s1Byte* pcfotail, - IN u1Byte num_ss -); - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ + +#define CFO_TH_XTAL_HIGH 5 //20 // kHz +#define CFO_TH_XTAL_LOW 5//10 // kHz +#define CFO_TH_ATC 80 // kHz + +typedef struct _CFO_TRACKING_ +{ + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + s4Byte CFO_tail[4]; + u4Byte CFO_cnt[4]; + s4Byte CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + + BOOLEAN bForceXtalCap; + BOOLEAN bReset; +}CFO_TRACKING, *PCFO_TRACKING; + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +); + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail, + IN u1Byte num_ss +); + #endif \ No newline at end of file diff --git a/package/kernel/rtl8192cd/phydm/phydm_debug.c b/package/kernel/rtl8192cd/phydm/phydm_debug.c index 265dc9136f5..f4b9eed8d8f 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_debug.c +++ b/package/kernel/rtl8192cd/phydm/phydm_debug.c @@ -1,3023 +1,3023 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -PHYDM_InitDebugSetting( - IN PDM_ODM_T pDM_Odm -) -{ - pDM_Odm->DebugLevel = ODM_DBG_TRACE; - - pDM_Odm->fw_DebugComponents = 0; - pDM_Odm->DebugComponents = - \ -#if DBG -/*BB Functions*/ -/* ODM_COMP_DIG |*/ -/* ODM_COMP_RA_MASK |*/ -/* ODM_COMP_DYNAMIC_TXPWR |*/ -/* ODM_COMP_FA_CNT |*/ -/* ODM_COMP_RSSI_MONITOR |*/ -/* ODM_COMP_SNIFFER |*/ -/* ODM_COMP_ANT_DIV |*/ -/* ODM_COMP_NOISY_DETECT |*/ -/* ODM_COMP_RATE_ADAPTIVE |*/ -/* ODM_COMP_PATH_DIV |*/ -/* ODM_COMP_DYNAMIC_PRICCA |*/ -/* ODM_COMP_DYNAMIC_ANT_WEIGHTING |*/ -/* ODM_COMP_MP |*/ -/* ODM_COMP_CFO_TRACKING |*/ -/* ODM_COMP_ACS |*/ -/* PHYDM_COMP_ADAPTIVITY |*/ -/* PHYDM_COMP_RA_DBG |*/ -/* PHYDM_COMP_TXBF |*/ -/* ODM_COMP_TDMA_DIG |*/ - -/*MAC Functions*/ -/* ODM_COMP_EDCA_TURBO |*/ -/* ODM_FW_DEBUG_TRACE |*/ - -/*RF Functions*/ -/* ODM_COMP_TX_PWR_TRACK |*/ -/* ODM_COMP_CALIBRATION |*/ - -/*Common*/ -/* ODM_PHY_CONFIG |*/ -/* ODM_COMP_INIT |*/ -/* ODM_COMP_COMMON |*/ -/* ODM_COMP_API |*/ - - -#endif - 0; - - pDM_Odm->fw_buff_is_enpty = TRUE; - pDM_Odm->pre_c2h_seq = 0; -} - -VOID -phydm_BB_RxHang_Info( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - u4Byte value32 = 0; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - return; - - value32 = ODM_GetBBReg(pDM_Odm, 0xF80 , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32)); - - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x198c , BIT2|BIT1|BIT0, 7); - - /* dbg_port = basic state machine */ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x000); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "basic state machine", value32)); - } - - /* dbg_port = state machine */ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x007); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "state machine", value32)); - } - - /* dbg_port = CCA-related*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x204); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "CCA-related", value32)); - } - - - /* dbg_port = edcca/rxd*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x278); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "edcca/rxd", value32)); - } - - /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x290); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", value32)); - } - - /* dbg_port = bf-related*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B2); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = bf-related*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B8); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = txon/rxd*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA03); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "txon/rxd", value32)); - } - - /* dbg_port = l_rate/l_length*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0B); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "l_rate/l_length", value32)); - } - - /* dbg_port = rxd/rxd_hit*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0D); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32)); - } - - /* dbg_port = dis_cca*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAA0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "dis_cca", value32)); - } - - - /* dbg_port = tx*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAB0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "tx", value32)); - } - - /* dbg_port = rx plcp*/ - { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD1); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD2); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD3); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - } - -} - -VOID -phydm_bb_debug_info_n_series( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - u4Byte value32 = 0, value32_1 = 0, value32_2 = 0, value32_3 = 0; - u1Byte rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; - u1Byte rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; - - s1Byte rxevm_0 = 0, rxevm_1 = 0; - s4Byte short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; - s4Byte scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; - s4Byte cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a= 0, acq_cfo_b = 0; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); - - /*AGC result*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xdd0, bMaskDWord); - rf_gain_a = value32 & 0x3f; - rf_gain_a = rf_gain_a << 1; - - rf_gain_b = (value32 >> 8) & 0x3f; - rf_gain_b = rf_gain_b << 1; - - rf_gain_c = (value32 >> 16) & 0x3f; - rf_gain_c = rf_gain_c << 1; - - rf_gain_d = (value32 >> 24) & 0x3f; - rf_gain_d = rf_gain_d << 1; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d)); - - /*SNR report*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xdd4, bMaskDWord); - rx_snr_a = value32 & 0xff; - rx_snr_a = rx_snr_a >> 1; - - rx_snr_b = (value32>>8) & 0xff; - rx_snr_b = rx_snr_b >> 1; - - rx_snr_c = (value32>>16) & 0xff; - rx_snr_c = rx_snr_c >> 1; - - rx_snr_d = (value32>>24) & 0xff; - rx_snr_d = rx_snr_d >> 1; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d)); - - /* PostFFT related info*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xdd8 , bMaskDWord); - - rxevm_0 = (s1Byte)((value32 & bMaskByte2) >> 16); - rxevm_0 /= 2; - if (rxevm_0 < -63) - rxevm_0 = 0; - - rxevm_1 = (s1Byte)((value32 & bMaskByte3) >> 24); - rxevm_1 /= 2; - if (rxevm_1 < -63) - rxevm_1 = 0; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1)); - - /*CFO Report Info*/ - ODM_SetBBReg(pDM_Odm, 0xd00, BIT26, 1); - - /*Short CFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xdac , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xdb0 , bMaskDWord); - - short_cfo_b = (s4Byte)(value32 & 0xfff); /*S(12,11)*/ - short_cfo_a = (s4Byte)((value32 & 0x0fff0000)>>16); - - long_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ - long_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); - - /*SFO 2's to dec*/ - if (short_cfo_a > 2047) - short_cfo_a = short_cfo_a - 4096; - if (short_cfo_b > 2047) - short_cfo_b = short_cfo_b - 4096; - - short_cfo_a = (short_cfo_a * 312500) / 2048; - short_cfo_b = (short_cfo_b * 312500) / 2048; - - /*LFO 2's to dec*/ - - if (long_cfo_a > 4095) - long_cfo_a = long_cfo_a - 8192; - - if (long_cfo_b > 4095) - long_cfo_b = long_cfo_b - 8192; - - long_cfo_a = long_cfo_a * 312500 / 4096; - long_cfo_b = long_cfo_b * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, short_cfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, long_cfo_b)); - - /*SCFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xdb8 , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xdb4 , bMaskDWord); - - scfo_b = (s4Byte)(value32 & 0x7ff); /*S(11,10)*/ - scfo_a = (s4Byte)((value32 & 0x07ff0000)>>16); - - if (scfo_a > 1023) - scfo_a = scfo_a - 2048; - - if (scfo_b > 1023) - scfo_b = scfo_b - 2048; - - scfo_a = scfo_a * 312500 / 1024; - scfo_b = scfo_b * 312500 / 1024; - - avg_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ - avg_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); - - if (avg_cfo_a > 4095) - avg_cfo_a = avg_cfo_a - 8192; - - if (avg_cfo_b > 4095) - avg_cfo_b = avg_cfo_b - 8192; - - avg_cfo_a = avg_cfo_a * 312500 / 4096; - avg_cfo_b = avg_cfo_b * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Value SCFO(Hz) ", scfo_a, scfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, avg_cfo_b)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xdbc , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xde0 , bMaskDWord); - - cfo_end_b = (s4Byte)(value32 & 0x1fff); /*S(13,12)*/ - cfo_end_a = (s4Byte)((value32 & 0x1fff0000)>>16); - - if (cfo_end_a > 4095) - cfo_end_a = cfo_end_a - 8192; - - if (cfo_end_b > 4095) - cfo_end_b = cfo_end_b - 8192; - - cfo_end_a = cfo_end_a * 312500 / 4096; - cfo_end_b = cfo_end_b * 312500 / 4096; - - acq_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ - acq_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); - - if (acq_cfo_a > 4095) - acq_cfo_a = acq_cfo_a - 8192; - - if (acq_cfo_b > 4095) - acq_cfo_b = acq_cfo_b - 8192; - - acq_cfo_a = acq_cfo_a * 312500 / 4096; - acq_cfo_b = acq_cfo_b * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, cfo_end_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, acq_cfo_b)); - -} - - -VOID -phydm_BB_Debug_Info( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - char *tmp_string = NULL; - - u1Byte RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; - static u1Byte vRX_BW ; - u4Byte value32, value32_1, value32_2, value32_3; - s4Byte SFO_A, SFO_B, SFO_C, SFO_D; - s4Byte LFO_A, LFO_B, LFO_C, LFO_D; - static u1Byte MCSS, Tail, Parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, vNsts, vtxops, vrsv2, vbrsv, bf, vbcrc; - static u2Byte HLength, htcrc8, Length; - static u2Byte vpaid; - static u2Byte vLength, vhtcrc8, vMCSS, vTail, vbTail; - static u1Byte HMCSS, HRX_BW; - - u1Byte pwDB; - s1Byte RXEVM_0, RXEVM_1, RXEVM_2 ; - u1Byte RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD; - u1Byte RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD; - s4Byte sig_power; - - const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"}; - - /* - const double evm_comp_20M = 0.579919469776867; //10*log10(64.0/56.0) - const double evm_comp_40M = 0.503051183113957; //10*log10(128.0/114.0) - const double evm_comp_80M = 0.244245993314183; //10*log10(256.0/242.0) - const double evm_comp_160M = 0.244245993314183; //10*log10(512.0/484.0) - */ - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - phydm_bb_debug_info_n_series(pDM_Odm, &used, output, &out_len); - return; - } - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); - - /*BW & Mode Detection*/ - - value32 = ODM_GetBBReg(pDM_Odm, 0xf80 , bMaskDWord); - value32_2 = value32; - RX_HT_BW = (u1Byte)(value32 & 0x1); - RX_VHT_BW = (u1Byte)((value32 >> 1) & 0x3); - RXSC = (u1Byte)(value32 & 0x78); - value32_1 = (value32 & 0x180) >> 7; - RX_HT = (u1Byte)(value32_1); - - RX_BW = 0; - - if (RX_HT == 2) { - if (RX_VHT_BW == 0) { - tmp_string = "20M"; - } else if (RX_VHT_BW == 1) { - tmp_string = "40M"; - } else { - tmp_string = "80M"; - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "VHT", tmp_string)); - RX_BW = RX_VHT_BW; - } else if (RX_HT == 1) { - if (RX_HT_BW == 0) { - tmp_string = "20M"; - } else if (RX_HT_BW == 1) { - tmp_string = "40M"; - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "HT", tmp_string)); - RX_BW = RX_HT_BW; - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "Mode", "Legacy")); - } - - if (RX_HT != 0) { - if (RXSC == 0) - tmp_string = "duplicate/full bw"; - else if (RXSC == 1) - tmp_string = "usc20-1"; - else if (RXSC == 2) - tmp_string = "lsc20-1"; - else if (RXSC == 3) - tmp_string = "usc20-2"; - else if (RXSC == 4) - tmp_string = "lsc20-2"; - else if (RXSC == 9) - tmp_string = "usc40"; - else if (RXSC == 10) - tmp_string = "lsc40"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s", tmp_string)); - } - - /* RX signal power and AGC related info*/ - - value32 = ODM_GetBBReg(pDM_Odm, 0xF90 , bMaskDWord); - pwDB = (u1Byte)((value32 & bMaskByte1) >> 8); - pwDB = pwDB >> 1; - sig_power = -110 + pwDB; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); - RX_SNR_pathA = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathA = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathA *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); - RX_SNR_pathB = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathB = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathB *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); - RX_SNR_pathC = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathC = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathC *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); - RX_SNR_pathD = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathD = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathD *= 2; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD)); - - - /* RX Counter related info*/ - - value32 = ODM_GetBBReg(pDM_Odm, 0xF08, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA Counter", ((value32&0xFFFF0000)>>16))); - - value32 = ODM_GetBBReg(pDM_Odm, 0xFD0, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail Counter", value32&0xFFFF)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xFC4, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); - - value32 = ODM_GetBBReg(pDM_Odm, 0xFCC, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA Counter", value32&0xFFFF)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xFBC, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (Parity Fail/Rate Illegal) Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); - - value32_1 = ODM_GetBBReg(pDM_Odm, 0xFC8, bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xFC0, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2&0xFFFF0000)>>16), value32_1&0xFFFF)); - - /* PostFFT related info*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xF8c , bMaskDWord); - RXEVM_0 = (s1Byte)((value32 & bMaskByte2) >> 16); - RXEVM_0 /= 2; - if (RXEVM_0 < -63) - RXEVM_0 = 0; - - RXEVM_1 = (s1Byte)((value32 & bMaskByte3) >> 24); - RXEVM_1 /= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xF88 , bMaskDWord); - RXEVM_2 = (s1Byte)((value32 & bMaskByte2) >> 16); - RXEVM_2 /= 2; - - if (RXEVM_1 < -63) - RXEVM_1 = 0; - if (RXEVM_2 < -63) - RXEVM_2 = 0; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xF8C , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); - - /*BW & Mode Detection*/ - - /*Reset Page F Counter*/ - ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 1); - ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 0); - - /*CFO Report Info*/ - /*Short CFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xd0c , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd4c , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd8c , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdcc , bMaskDWord); - - SFO_A = (s4Byte)(value32 & 0xfff); - SFO_B = (s4Byte)(value32_1 & 0xfff); - SFO_C = (s4Byte)(value32_2 & 0xfff); - SFO_D = (s4Byte)(value32_3 & 0xfff); - - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); - - /*SFO 2's to dec*/ - if (SFO_A > 2047) - SFO_A = SFO_A - 4096; - SFO_A = (SFO_A * 312500) / 2048; - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; - SFO_B = (SFO_B * 312500) / 2048; - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; - SFO_C = (SFO_C * 312500) / 2048; - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; - SFO_D = (SFO_D * 312500) / 2048; - - /*LFO 2's to dec*/ - - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; - - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; - - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; - - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Short CFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); - - /*SCFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xd10 , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd50 , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd90 , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd0 , bMaskDWord); - - SFO_A = (s4Byte)(value32 & 0x7ff); - SFO_B = (s4Byte)(value32_1 & 0x7ff); - SFO_C = (s4Byte)(value32_2 & 0x7ff); - SFO_D = (s4Byte)(value32_3 & 0x7ff); - - if (SFO_A > 1023) - SFO_A = SFO_A - 2048; - - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; - - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; - - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; - - SFO_A = SFO_A * 312500 / 1024; - SFO_B = SFO_B * 312500 / 1024; - SFO_C = SFO_C * 312500 / 1024; - SFO_D = SFO_D * 312500 / 1024; - - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); - - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; - - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; - - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; - - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); - - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); - - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; - - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; - - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; - - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf20 , bMaskDWord); /*L SIG*/ - - Tail = (u1Byte)((value32 & 0xfc0000) >> 16); - Parity = (u1Byte)((value32 & 0x20000) >> 16); - Length = (u2Byte)((value32 & 0x1ffe00) >> 8); - rsv = (u1Byte)(value32 & 0x10); - MCSS = (u1Byte)(value32 & 0x0f); - - switch (MCSS) { - case 0x0b: - idx = 0; - break; - case 0x0f: - idx = 1; - break; - case 0x0a: - idx = 2; - break; - case 0x0e: - idx = 3; - break; - case 0x09: - idx = 4; - break; - case 0x08: - idx = 5; - break; - case 0x0c: - idx = 6; - break; - default: - idx = 6; - break; - - } - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "L-SIG")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "Rate", L_rate[idx])); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/Length/Parity", rsv, RX_BW, Length)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*HT SIG*/ - if (RX_HT == 1) { - - HMCSS = (u1Byte)(value32 & 0x7F); - HRX_BW = (u1Byte)(value32 & 0x80); - HLength = (u2Byte)((value32 >> 8) & 0xffff); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/Length", HMCSS, HRX_BW, HLength)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*HT SIG*/ - - if (RX_HT == 1) { - smooth = (u1Byte)(value32 & 0x01); - htsound = (u1Byte)(value32 & 0x02); - rsv = (u1Byte)(value32 & 0x04); - agg = (u1Byte)(value32 & 0x08); - stbc = (u1Byte)(value32 & 0x30); - fec = (u1Byte)(value32 & 0x40); - sgi = (u1Byte)(value32 & 0x80); - htltf = (u1Byte)((value32 & 0x300) >> 8); - htcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); - Tail = (u1Byte)((value32 & 0xfc0000) >> 16); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x", "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/Tail", sgi, htltf, htcrc8, Tail)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*VHT SIG A1*/ - if (RX_HT == 2) { - /* value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord);*/ - vRX_BW = (u1Byte)(value32 & 0x03); - vrsv = (u1Byte)(value32 & 0x04); - vstbc = (u1Byte)(value32 & 0x08); - vgid = (u1Byte)((value32 & 0x3f0) >> 4); - vNsts = (u1Byte)(((value32 & 0x1c00) >> 8) + 1); - vpaid = (u2Byte)(value32 & 0x3fe); - vtxops = (u1Byte)((value32 & 0x400000) >> 20); - vrsv2 = (u1Byte)((value32 & 0x800000) >> 20); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", vRX_BW, vrsv, vstbc, vgid, vNsts, vpaid, vtxops, vrsv2)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*VHT SIG*/ - - if (RX_HT == 2) { - /*value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); */ /*VHT SIG*/ - - //sgi=(u1Byte)(value32&0x01); - sgiext = (u1Byte)(value32 & 0x03); - //fec = (u1Byte)(value32&0x04); - fecext = (u1Byte)(value32 & 0x0C); - - vMCSS = (u1Byte)(value32 & 0xf0); - bf = (u1Byte)((value32 & 0x100) >> 8); - vrsv = (u1Byte)((value32 & 0x200) >> 8); - vhtcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); - vTail = (u1Byte)((value32 & 0xfc0000) >> 16); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/Tail", sgiext, fecext, vMCSS, bf, vrsv, vhtcrc8, vTail)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf34 , bMaskDWord); /*VHT SIG*/ - { - vLength = (u2Byte)(value32 & 0x1fffff); - vbrsv = (u1Byte)((value32 & 0x600000) >> 20); - vbTail = (u2Byte)((value32 & 0x1f800000) >> 20); - vbcrc = (u1Byte)((value32 & 0x80000000) >> 28); - - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-B")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "Length/Rsv/Tail/CRC", vLength, vbrsv, vbTail, vbcrc)); - - /*for Condition number*/ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - s4Byte condition_num = 0; - char *factor = NULL; - - ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x1); /*enable report condition number*/ - - condition_num = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); - condition_num = (condition_num & 0x3ffff) >> 4; - - if (*pDM_Odm->pBandWidth == ODM_BW80M) - factor = "256/234"; - else if (*pDM_Odm->pBandWidth == ODM_BW40M) - factor = "128/108"; - else if (*pDM_Odm->pBandWidth == ODM_BW20M) { - if (RX_HT != 2 || RX_HT != 1) - factor = "64/52"; /*HT or VHT*/ - else - factor = "64/48"; /*legacy*/ - } - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition Number", condition_num, factor)); - - } - -} -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -void phydm_sbd_check( - IN PDM_ODM_T pDM_Odm -) -{ - static u4Byte pkt_cnt = 0; - static BOOLEAN sbd_state = 0; - u4Byte sym_count, count, value32; - - if (sbd_state == 0) { - pkt_cnt++; - if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ - ODM_SetTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, 0); /*ms*/ - sbd_state = 1; - } - } else { /*read counter*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xF98, bMaskDWord); - sym_count = (value32 & 0x7C000000) >> 26; - count = (value32 & 0x3F00000) >> 20; - DbgPrint("#SBD# sym_count %d count %d\n", sym_count, count); - sbd_state = 0; - } -} - -void phydm_sbd_callback( - PRT_TIMER pTimer -) -{ - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - -#if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_Odm->sbdcnt_workitem); -#else - phydm_sbd_check(pDM_Odm); -#endif -} - -void phydm_sbd_workitem_callback( - IN PVOID pContext -) -{ - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - phydm_sbd_check(pDM_Odm); -} -#endif -VOID -phydm_BasicDbgMessage -( - IN PVOID pDM_VOID -) -{ -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm , PHYDM_FALSEALMCNT); - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u2Byte macid, phydm_macid, client_cnt = 0; - PSTA_INFO_T pEntry; - s4Byte tmp_val = 0; - u1Byte tmp_val_u1 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", pDM_Odm->phydm_sys_up_time)); - - if (pDM_Odm->bLinked) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Curr_STA_ID = 0x%x\n", pDM_Odm->curr_station_id)); - - /*Print RX Rate*/ - if (pDM_Odm->RxRate <= ODM_RATE11M) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", - pDM_Odm->cck_lna_idx, pDM_Odm->cck_vga_idx)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", - pDM_Odm->ofdm_agc_idx[0], pDM_Odm->ofdm_agc_idx[1], pDM_Odm->ofdm_agc_idx[2], pDM_Odm->ofdm_agc_idx[3])); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, RxRate:", - (pDM_Odm->RSSI_A == 0xff) ? 0 : pDM_Odm->RSSI_A , - (pDM_Odm->RSSI_B == 0xff) ? 0 : pDM_Odm->RSSI_B , - (pDM_Odm->RSSI_C == 0xff) ? 0 : pDM_Odm->RSSI_C, - (pDM_Odm->RSSI_D == 0xff) ? 0 : pDM_Odm->RSSI_D)); - - phydm_print_rate(pDM_Odm, pDM_Odm->RxRate, ODM_COMP_COMMON); - - /*Print TX Rate*/ - for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { - - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (IS_STA_VALID(pEntry)) { - - phydm_macid = (pDM_Odm->platform2phydm_macid_table[macid]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TXRate [%d]:", macid)); - phydm_print_rate(pDM_Odm, pRA_Table->link_tx_rate[macid], ODM_COMP_COMMON); - - client_cnt++; - - if (client_cnt == pDM_Odm->number_linked_client) - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP { TX, RX, total} = {%d, %d, %d }Mbps, TrafficLoad = (%d))\n", - pDM_Odm->tx_tp, pDM_Odm->rx_tp, pDM_Odm->total_tp, pDM_Odm->TrafficLoad)); - - tmp_val_u1 = (pCfoTrack->CrystalCap > pCfoTrack->DefXCap) ? (pCfoTrack->CrystalCap - pCfoTrack->DefXCap) : (pCfoTrack->DefXCap - pCfoTrack->CrystalCap); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n", - pCfoTrack->CFO_ave_pre, ((pCfoTrack->CrystalCap > pCfoTrack->DefXCap)?"+":"-"),tmp_val_u1)); - - /* Condition number */ - #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - tmp_val = phydm_get_condition_number_8822B(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condition number = ((%d))\n", tmp_val)); - } - #endif - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - FalseAlmCnt->Cnt_CCK_CCA, FalseAlmCnt->Cnt_OFDM_CCA, FalseAlmCnt->Cnt_CCA_all)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all)); - - #if (ODM_IC_11N_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail, FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); - } - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, Num_client = %d, RSSI_Min = %d, CurrentIGI = 0x%x, bNoisy=%d\n\n", - pDM_Odm->bLinked, pDM_Odm->number_linked_client, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue, pDM_Odm->NoisyDecision)); - -/* - temp_reg = ODM_GetBBReg(pDM_Odm, 0xDD0, bMaskByte0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg)); - - temp_reg = ODM_GetBBReg(pDM_Odm, 0xDDc, bMaskByte1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg)); - - temp_reg = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg)); - - temp_reg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0x3fe0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg)); -*/ - -#endif -} - - -VOID phydm_BasicProfile( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - char *Cut = NULL; - char *ICType = NULL; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte commit_ver = 0; - u4Byte date = 0; - char *commit_by = NULL; - u4Byte release_ver = 0; - - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); - - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - #if (RTL8188E_SUPPORT == 1) - ICType = "RTL8188E"; - date = RELEASE_DATE_8188E; - commit_by = COMMIT_BY_8188E; - release_ver = RELEASE_VERSION_8188E; - #endif - } - #if (RTL8812A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8812) { - ICType = "RTL8812A"; - date = RELEASE_DATE_8812A; - commit_by = COMMIT_BY_8812A; - release_ver = RELEASE_VERSION_8812A; - } - #endif - #if (RTL8821A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821) { - ICType = "RTL8821A"; - date = RELEASE_DATE_8821A; - commit_by = COMMIT_BY_8821A; - release_ver = RELEASE_VERSION_8821A; - } - #endif - #if (RTL8192E_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - ICType = "RTL8192E"; - date = RELEASE_DATE_8192E; - commit_by = COMMIT_BY_8192E; - release_ver = RELEASE_VERSION_8192E; - } - #endif - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - ICType = "RTL8723B"; - date = RELEASE_DATE_8723B; - commit_by = COMMIT_BY_8723B; - release_ver = RELEASE_VERSION_8723B; - } - #endif - #if (RTL8814A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8814A) { - ICType = "RTL8814A"; - date = RELEASE_DATE_8814A; - commit_by = COMMIT_BY_8814A; - release_ver = RELEASE_VERSION_8814A; - } - #endif - #if (RTL8881A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8881A) { - ICType = "RTL8881A"; - /**/ - } - #endif - #if (RTL8822B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8822B) { - ICType = "RTL8822B"; - date = RELEASE_DATE_8822B; - commit_by = COMMIT_BY_8822B; - release_ver = RELEASE_VERSION_8822B; - } - #endif - #if (RTL8197F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8197F) { - ICType = "RTL8197F"; - date = RELEASE_DATE_8197F; - commit_by = COMMIT_BY_8197F; - release_ver = RELEASE_VERSION_8197F; - } - #endif - - #if (RTL8703B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8703B) { - - ICType = "RTL8703B"; - date = RELEASE_DATE_8703B; - commit_by = COMMIT_BY_8703B; - release_ver = RELEASE_VERSION_8703B; - - } - #endif - #if (RTL8195A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8195A) { - ICType = "RTL8195A"; - /**/ - } - #endif - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - ICType = "RTL8188F"; - date = RELEASE_DATE_8188F; - commit_by = COMMIT_BY_8188F; - release_ver = RELEASE_VERSION_8188F; - } - #endif - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - ICType = "RTL8723D"; - /**/ - } - #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC Type", ICType, pDM_Odm->bIsMPChip ? "Yes" : "No")); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - Cut = "A"; - else if (pDM_Odm->CutVersion == ODM_CUT_B) - Cut = "B"; - else if (pDM_Odm->CutVersion == ODM_CUT_C) - Cut = "C"; - else if (pDM_Odm->CutVersion == ODM_CUT_D) - Cut = "D"; - else if (pDM_Odm->CutVersion == ODM_CUT_E) - Cut = "E"; - else if (pDM_Odm->CutVersion == ODM_CUT_F) - Cut = "F"; - else if (pDM_Odm->CutVersion == ODM_CUT_I) - Cut = "I"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Cut Version", Cut)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Version", ODM_GetHWImgVersion(pDM_Odm))); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release Version", release_ver)); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - PADAPTER Adapter = pDM_Odm->Adapter; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", Adapter->MgntInfo.FirmwareVersion, Adapter->MgntInfo.FirmwareSubVersion)); - } -#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - { - struct rtl8192cd_priv *priv = pDM_Odm->priv; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); - } -#else - { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", pHalData->FirmwareVersion, pHalData->FirmwareSubVersion)); - } -#endif - //1 PHY DM Version List - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM Version %")); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code Base", PHYDM_CODE_BASE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Adaptivity", ADAPTIVITY_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); -#endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto Channel Selection", ACS_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Path Diversity", PATHDIV_VERSION)); - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); - -#endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F)); -#endif - *_used = used; - *_out_len = out_len; - -} - -VOID -phydm_fw_trace_en_h2c( - IN PVOID pDM_VOID, - IN BOOLEAN enable, - IN u4Byte fw_debug_component, - IN u4Byte monitor_mode, - IN u4Byte macid -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte H2C_Parameter[7] = {0}; - u1Byte cmd_length; - - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES){ - - H2C_Parameter[0] = enable; - H2C_Parameter[1] = (u1Byte)(fw_debug_component & bMaskByte0); - H2C_Parameter[2] = (u1Byte)((fw_debug_component & bMaskByte1)>>8); - H2C_Parameter[3] = (u1Byte)((fw_debug_component & bMaskByte2)>>16); - H2C_Parameter[4] = (u1Byte)((fw_debug_component & bMaskByte3)>>24); - H2C_Parameter[5] = (u1Byte)monitor_mode; - H2C_Parameter[6] = (u1Byte)macid; - cmd_length = 7; - - } else { - - H2C_Parameter[0] = enable; - H2C_Parameter[1] = (u1Byte)monitor_mode; - H2C_Parameter[2] = (u1Byte)macid; - cmd_length = 3; - } - - - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); - if (monitor_mode == 0){ - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); - } - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_FW_TRACE_EN, cmd_length, H2C_Parameter); -} - - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) -BOOLEAN -phydm_api_set_txagc( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate, - IN BOOLEAN bSingleRate - ) -{ - BOOLEAN ret = FALSE; - -#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { - if (bSingleRate) { -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ret = phydm_write_txagc_1byte_8822b(pDM_Odm, PowerIndex, Path, HwRate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - ret = phydm_write_txagc_1byte_8821c(pDM_Odm, PowerIndex, Path, HwRate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - SetCurrentTxAGC(pDM_Odm->priv, Path, HwRate, (u1Byte)PowerIndex); -#endif - - } else { - u1Byte i; -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ret = config_phydm_write_txagc_8822b(pDM_Odm, PowerIndex, Path, HwRate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - ret = config_phydm_write_txagc_8821c(pDM_Odm, PowerIndex, Path, HwRate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - for (i = 0; i < 4; i++) - SetCurrentTxAGC(pDM_Odm->priv, Path, (HwRate + i), (u1Byte)PowerIndex); -#endif - } - } -#endif - - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_write_txagc_8197f(pDM_Odm, PowerIndex, Path, HwRate); -#endif - - return ret; -} - -u1Byte -phydm_api_get_txagc( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u1Byte ret = 0; - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_read_txagc_8822b(pDM_Odm, Path, HwRate); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_read_txagc_8197f(pDM_Odm, Path, HwRate); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8821C) - ret = config_phydm_read_txagc_8821c(pDM_Odm, Path, HwRate); -#endif - - return ret; -} - - -BOOLEAN -phydm_api_switch_bw_channel( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - BOOLEAN ret = FALSE; - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_switch_channel_bw_8822b(pDM_Odm, central_ch, primary_ch_idx, bandwidth); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_switch_channel_bw_8197f(pDM_Odm, central_ch, primary_ch_idx, bandwidth); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8821C) - ret = config_phydm_switch_channel_bw_8821c(pDM_Odm, central_ch, primary_ch_idx, bandwidth); -#endif - - return ret; -} - -BOOLEAN -phydm_api_trx_mode( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) -{ - BOOLEAN ret = FALSE; - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_trx_mode_8822b(pDM_Odm, TxPath, RxPath, bTx2Path); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_trx_mode_8197f(pDM_Odm, TxPath, RxPath, bTx2Path); -#endif - - return ret; -} -#endif - -VOID -phydm_get_per_path_txagc( - IN PVOID pDM_VOID, - IN u1Byte path, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_idx; - u1Byte txagc; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - -#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (((pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || - ((pDM_Odm->SupportICType & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { - for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { - if (rate_idx == ODM_RATE1M) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); - else if (rate_idx == ODM_RATE6M) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "OFDM====>")); - else if (rate_idx == ODM_RATEMCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 1ss====>")); - else if (rate_idx == ODM_RATEMCS8) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 2ss====>")); - else if (rate_idx == ODM_RATEMCS16) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 3ss====>")); - else if (rate_idx == ODM_RATEMCS24) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 4ss====>")); - else if (rate_idx == ODM_RATEVHTSS1MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 1ss====>")); - else if (rate_idx == ODM_RATEVHTSS2MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 2ss====>")); - else if (rate_idx == ODM_RATEVHTSS3MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); - else if (rate_idx == ODM_RATEVHTSS4MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); - - txagc = phydm_api_get_txagc(pDM_Odm, (ODM_RF_RADIO_PATH_E) path, rate_idx); - if (config_phydm_read_txagc_check(txagc)) - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); - else - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%s ", "xx")); - } - } -#endif -} - - -VOID -phydm_get_txagc( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - /* Path-A */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "Path-A====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_A, _used, output, _out_len); - - /* Path-B */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-B====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_B, _used, output, _out_len); - - /* Path-C */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-C====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_C, _used, output, _out_len); - - /* Path-D */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-D====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_D, _used, output, _out_len); - -} - -VOID -phydm_set_txagc( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - -/*dm_value[1] = Path*/ -/*dm_value[2] = HwRate*/ -/*dm_value[3] = PowerIndex*/ - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)) { - if (dm_value[1] <= 1) { - if ((u1Byte)dm_value[2] != 0xff) { - if (phydm_api_set_txagc(pDM_Odm, dm_value[3], (ODM_RF_RADIO_PATH_E) dm_value[1], (u1Byte)dm_value[2], TRUE)) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[1], "rate index-0x", dm_value[2], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); - } else { - u1Byte i; - u4Byte power_index; - BOOLEAN status = TRUE; - - power_index = (dm_value[3] & 0x3f); - - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { - power_index = (power_index << 24)|(power_index << 16)|(power_index << 8)|(power_index); - - for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) - status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { - for (i = 0; i <= ODM_RATEMCS15; i++) - status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); - } - - if (status) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x\n", "Write all TXAGC of path-", dm_value[1], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); - } - } else { - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); - } - } -#endif -} - -VOID -phydm_debug_trace( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_debug_components, one = 1; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pre_debug_components = pDM_Odm->DebugComponents; - - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->DebugComponents & ODM_COMP_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->DebugComponents & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((pDM_Odm->DebugComponents & ODM_COMP_SNIFFER) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((pDM_Odm->DebugComponents & ODM_COMP_DFS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((pDM_Odm->DebugComponents & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->DebugComponents & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "11. (( %s ))CCX\n", ((pDM_Odm->DebugComponents & ODM_COMP_CCX) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))LNA_SAT_CHK\n", ((pDM_Odm->DebugComponents & ODM_COMP_LNA_SAT_CHK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((pDM_Odm->DebugComponents & ODM_COMP_MP) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((pDM_Odm->DebugComponents & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((pDM_Odm->DebugComponents & ODM_COMP_ACS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->DebugComponents & ODM_COMP_EDCA_TURBO) ? ("V") : (".")))); - - PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))TDMA_DIG_CALL_BACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_DIG_CALL_BACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((pDM_Odm->DebugComponents & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "23. (( %s ))ADAPTIVE_SOML\n", ((pDM_Odm->DebugComponents & ODM_COMP_ADAPTIVE_SOML) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))TDMA_HDIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_HDIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((pDM_Odm->DebugComponents & ODM_COMP_CALIBRATION) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "27. (( %s ))TDMA_LDIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_LDIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((pDM_Odm->DebugComponents & ODM_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((pDM_Odm->DebugComponents & ODM_COMP_INIT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((pDM_Odm->DebugComponents & ODM_COMP_COMMON) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((pDM_Odm->DebugComponents & ODM_COMP_API) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - - } else if (dm_value[0] == 101) { - pDM_Odm->DebugComponents = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); - } else { - if (dm_value[1] == 1) { /*enable*/ - pDM_Odm->DebugComponents |= (one << dm_value[0]); - } else if (dm_value[1] == 2) { /*disable*/ - pDM_Odm->DebugComponents &= ~(one << dm_value[0]); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); - } - PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", pre_debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", pDM_Odm->DebugComponents)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); -} - -VOID -phydm_fw_debug_trace( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_fw_debug_components, one = 1; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pre_fw_debug_components = pDM_Odm->fw_DebugComponents; - - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[FW Debug Component]")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))RA\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_RA) ? ("V") : (".")))); - - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES){ - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))MU\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_MU) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))Path Div\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))Phy Config\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - } - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - - } else { - if (dm_value[0] == 101) { - pDM_Odm->fw_DebugComponents = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Clear all fw debug components")); - } else { - if (dm_value[1] == 1) { /*enable*/ - pDM_Odm->fw_DebugComponents |= (one << dm_value[0]); - } else if (dm_value[1] == 2) { /*disable*/ - pDM_Odm->fw_DebugComponents &= ~(one << dm_value[0]); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); - } - - if (pDM_Odm->fw_DebugComponents == 0) { - pDM_Odm->DebugComponents &= ~ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(pDM_Odm, FALSE, pDM_Odm->fw_DebugComponents, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ - } else { - pDM_Odm->DebugComponents |= ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(pDM_Odm, TRUE, pDM_Odm->fw_DebugComponents, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ - } - } -} - -VOID -phydm_DumpBbReg( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Addr = 0; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - - /* BB Reg, For Nseries IC we only need to dump page8 to pageF using 3 digits*/ - for (Addr = 0x800; Addr < 0xfff; Addr += 4) { - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%03x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - else - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - } - - if (pDM_Odm->SupportICType & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { - - if (pDM_Odm->RFType > ODM_2T2R) { - for (Addr = 0x1800; Addr < 0x18ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - } - - if (pDM_Odm->RFType > ODM_3T3R) { - for (Addr = 0x1a00; Addr < 0x1aff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - } - - for (Addr = 0x1900; Addr < 0x19ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - - for (Addr = 0x1c00; Addr < 0x1cff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - - for (Addr = 0x1f00; Addr < 0x1fff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - } -} - -VOID -phydm_DumpAllReg( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Addr = 0; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - /* dump MAC register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "MAC==========\n")); - for (Addr = 0; Addr < 0x7ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - - for (Addr = 0x1000; Addr < 0x17ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); - - /* dump BB register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "BB==========\n")); - phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); - - /* dump RF register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-A==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Addr, bRFRegOffsetMask))); - - if (pDM_Odm->RFType > ODM_1T1R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-B==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Addr, bRFRegOffsetMask))); - } - - if (pDM_Odm->RFType > ODM_2T2R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-C==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Addr, bRFRegOffsetMask))); - } - - if (pDM_Odm->RFType > ODM_3T3R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-D==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Addr, bRFRegOffsetMask))); - } -} - -VOID -phydm_EnableBigJump( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN state - ) -{ -#if (RTL8822B_SUPPORT == 1) - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if (state == FALSE) { - pDM_Odm->DM_DigTable.enableAdjustBigJump = FALSE; - ODM_SetBBReg(pDM_Odm, 0x8c8, 0xfe, ((pDM_DigTable->bigJumpStep3<<5)|(pDM_DigTable->bigJumpStep2<<3)|pDM_DigTable->bigJumpStep1)); - } else - pDM_Odm->DM_DigTable.enableAdjustBigJump = TRUE; -#endif -} - -#if (RTL8822B_SUPPORT == 1) - -VOID -phydm_showRxRate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx SU Rate Statistics=====\n")); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[3])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[7])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[9])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[13])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[17])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[19])); - - PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx MU Rate Statistics=====\n")); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[3])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[7])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[9])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[13])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[17])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[19])); - -} - -#endif - - -struct _PHYDM_COMMAND { - char name[16]; - u1Byte id; -}; - -enum PHYDM_CMD_ID { - PHYDM_HELP, - PHYDM_DEMO, - PHYDM_RA, - PHYDM_PROFILE, - PHYDM_ANTDIV, - PHYDM_PATHDIV, - PHYDM_DEBUG, - PHYDM_FW_DEBUG, - PHYDM_SUPPORT_ABILITY, - PHYDM_GET_TXAGC, - PHYDM_SET_TXAGC, - PHYDM_SMART_ANT, - PHYDM_API, - PHYDM_TRX_PATH, - PHYDM_LA_MODE, - PHYDM_DUMP_REG, - PHYDM_MU_MIMO, - PHYDM_HANG, - PHYDM_BIG_JUMP, - PHYDM_SHOW_RXRATE, - PHYDM_NBI_EN, - PHYDM_CSI_MASK_EN, - PHYDM_ADAPTIVE_SOML, - PHYDM_DFS, - PHYDM_IQK, - PHYDM_NHM, - PHYDM_CLM, - PHYDM_BB_INFO, - PHYDM_TXBF, - PHYDM_PAUSE_DIG_EN, - PHYDM_H2C -}; - -struct _PHYDM_COMMAND phy_dm_ary[] = { - {"-h", PHYDM_HELP}, /*do not move this element to other position*/ - {"demo", PHYDM_DEMO}, /*do not move this element to other position*/ - {"ra", PHYDM_RA}, - {"profile", PHYDM_PROFILE}, - {"antdiv", PHYDM_ANTDIV}, - {"pathdiv", PHYDM_PATHDIV}, - {"dbg", PHYDM_DEBUG}, - {"fw_dbg", PHYDM_FW_DEBUG}, - {"ability", PHYDM_SUPPORT_ABILITY}, - {"get_txagc", PHYDM_GET_TXAGC}, - {"set_txagc", PHYDM_SET_TXAGC}, - {"smtant", PHYDM_SMART_ANT}, - {"api", PHYDM_API}, - {"trxpath", PHYDM_TRX_PATH}, - {"lamode", PHYDM_LA_MODE}, - {"dumpreg", PHYDM_DUMP_REG}, - {"mu", PHYDM_MU_MIMO}, - {"hang", PHYDM_HANG}, - {"bigjump", PHYDM_BIG_JUMP}, - {"rxrate", PHYDM_SHOW_RXRATE}, - {"nbi", PHYDM_NBI_EN}, - {"csi_mask", PHYDM_CSI_MASK_EN}, - {"soml", PHYDM_ADAPTIVE_SOML}, - {"dfs", PHYDM_DFS}, - {"iqk", PHYDM_IQK}, - {"nhm", PHYDM_NHM}, - {"clm", PHYDM_CLM}, - {"bbinfo", PHYDM_BB_INFO}, - {"txbf", PHYDM_TXBF}, - {"pause_dig", PHYDM_PAUSE_DIG_EN}, - {"h2c", PHYDM_H2C} -}; - -VOID -phydm_cmd_parser( - IN PDM_ODM_T pDM_Odm, - IN char input[][MAX_ARGV], - IN u4Byte input_num, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len -) -{ - u4Byte used = 0; - u1Byte id = 0; - int var1[10] = {0}; - int i, input_idx = 0, phydm_ary_size; - char help[] = "-h"; - - if (flag == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); - return; - } - - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); - - //Parsing Cmd ID - if (input_num) { - - phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); - for (i = 0; i < phydm_ary_size; i++) { - if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { - id = phy_dm_ary[i].id; - break; - } - } - if (i == phydm_ary_size) { - PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); - return; - } - } - - switch (id) { - - case PHYDM_HELP: - { - PHYDM_SNPRINTF((output + used, out_len - used, "BB cmd ==>\n")); - for (i=0; i < phydm_ary_size-2; i++) { - - PHYDM_SNPRINTF((output + used, out_len - used, " %-5d: %s\n", i, phy_dm_ary[i+2].name)); - /**/ - } - } - break; - - case PHYDM_DEMO: /*echo demo 10 0x3a z abcde >cmd*/ - { - u4Byte directory = 0; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - char char_temp; - #else - u4Byte char_temp = ' '; - #endif - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Decimal Value = %d\n", directory)); - PHYDM_SSCANF(input[2], DCMD_HEX, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Hex Value = 0x%x\n", directory)); - PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); - PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); - PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); - } - break; - - case PHYDM_RA: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - - /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ - #if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_debug((PVOID)pDM_Odm, (pu4Byte) var1); - #else - phydm_RA_debug_PCR(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif - } - - - break; - - case PHYDM_ADAPTIVE_SOML: - -#if (CONFIG_ADAPTIVE_SOML) - for (i = 0; i < 8; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) - phydm_soml_debug(pDM_Odm, (u32 *)var1, &used, output, &out_len); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); -#endif - - break; - - case PHYDM_ANTDIV: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - phydm_antdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif - } - - break; - - case PHYDM_PATHDIV: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ -#if (defined(CONFIG_PATH_DIVERSITY)) - odm_pathdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); -#endif - } - - break; - - case PHYDM_DEBUG: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ - phydm_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - } - - - break; - - case PHYDM_FW_DEBUG: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) - phydm_fw_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - - break; - - case PHYDM_SUPPORT_ABILITY: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i , var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ - phydm_support_ability_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - } - - break; - - case PHYDM_SMART_ANT: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - phydm_hl_smart_ant_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif - #endif - } - - break; - - case PHYDM_API: -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - { - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F | ODM_RTL8821C)) { - BOOLEAN bEnableDbgMode; - u1Byte central_ch, primary_ch_idx, bandwidth; - - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - - bEnableDbgMode = (BOOLEAN)var1[0]; - central_ch = (u1Byte) var1[1]; - primary_ch_idx = (u1Byte) var1[2]; - bandwidth = (ODM_BW_E) var1[3]; - - if (bEnableDbgMode) { - pDM_Odm->bDisablePhyApi = FALSE; - phydm_api_switch_bw_channel(pDM_Odm, central_ch, primary_ch_idx, (ODM_BW_E) bandwidth); - pDM_Odm->bDisablePhyApi = TRUE; - PHYDM_SNPRINTF((output+used, out_len-used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); - } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); - } - } else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); - } -#else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); -#endif - break; - - case PHYDM_PROFILE: /*echo profile, >cmd*/ - phydm_BasicProfile(pDM_Odm, &used, output, &out_len); - break; - - case PHYDM_GET_TXAGC: - phydm_get_txagc(pDM_Odm, &used, output, &out_len); - break; - - case PHYDM_SET_TXAGC: - { - BOOLEAN bEnableDbgMode; - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - bEnableDbgMode = (BOOLEAN)var1[0]; - if (bEnableDbgMode) { - pDM_Odm->bDisablePhyApi = FALSE; - phydm_set_txagc(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - pDM_Odm->bDisablePhyApi = TRUE; - } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); - } - } - break; - - case PHYDM_TRX_PATH: - - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { - u1Byte TxPath, RxPath; - BOOLEAN bEnableDbgMode, bTx2Path; - - bEnableDbgMode = (BOOLEAN)var1[0]; - TxPath = (u1Byte) var1[1]; - RxPath = (u1Byte) var1[2]; - bTx2Path = (BOOLEAN) var1[3]; - - if (bEnableDbgMode) { - u1Byte bTmp = pDM_Odm->bDisablePhyApi; - pDM_Odm->bDisablePhyApi = FALSE; - phydm_api_trx_mode(pDM_Odm, (ODM_RF_PATH_E) TxPath, (ODM_RF_PATH_E) RxPath, bTx2Path); - if(bTmp) - pDM_Odm->bDisablePhyApi = bTmp; - PHYDM_SNPRINTF((output+used, out_len-used, "TxPath = 0x%x, RxPath = 0x%x, bTx2Path = %d\n", TxPath, RxPath, bTx2Path)); - } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); - } - } else - #endif - phydm_config_trx_path(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - - break; - - case PHYDM_LA_MODE: - #if (PHYDM_LA_MODE_SUPPORT == 1) - pDM_Odm->SupportAbility &= ~(ODM_BB_FA_CNT); - phydm_lamode_trigger_setting(pDM_Odm, &input[0], &used, output, &out_len, input_num); - pDM_Odm->SupportAbility |= ODM_BB_FA_CNT; - #else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); - #endif - break; - - case PHYDM_DUMP_REG: - { - u1Byte type = 0; - - if (input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - type = (u1Byte)var1[0]; - } - - if (type == 0) - phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); - else if (type == 1) - phydm_DumpAllReg(pDM_Odm, &used, output, &out_len); - } - break; - - case PHYDM_MU_MIMO: -#if (RTL8822B_SUPPORT == 1) - - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - else - var1[0] = 0; - - if (var1[0] == 1) { - int index, ptr; - u4Byte Dword_H, Dword_L; - - PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFee CSI\n")); - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT17|BIT16, 2); /*Read BFee*/ - ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 1); /*Select BFee's CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x19b8, BIT6, 1); /*set as CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x19a8, 0xFFFF, 0xFFFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); - Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); - if (index % 2 == 0) - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - else - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - } - } else if (var1[0] == 2) { - int index, ptr; - u4Byte Dword_H, Dword_L; - - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); - PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFer's STA%d CSI\n", var1[1])); - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT24, 0); /*Read BFer*/ - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT25, 1); /*enable Read/Write RAM*/ - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT30|BIT29|BIT28, var1[1]); /*read which STA's CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 0); /*select BFer's CSI*/ - ODM_SetBBReg(pDM_Odm, 0x19e0, 0x00003FC0, 0xFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); - Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); - if (index % 2 == 0) - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - else - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - - PHYDM_SNPRINTF((output+used, out_len-used, "ptr=%d : 0x%8x %8x\n", ptr, Dword_H, Dword_L)); - } - - } -#endif - break; - - case PHYDM_BIG_JUMP: - { -#if (RTL8822B_SUPPORT == 1) - if (input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - phydm_EnableBigJump(pDM_Odm, (BOOLEAN)(var1[0])); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); -#endif - break; - } - - case PHYDM_HANG: - phydm_BB_RxHang_Info(pDM_Odm, &used, output, &out_len); - break; - - case PHYDM_SHOW_RXRATE: -#if (RTL8822B_SUPPORT == 1) - { - u1Byte rate_idx; - - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (var1[0] == 1) - phydm_showRxRate(pDM_Odm, &used, output, &out_len); - else { - PHYDM_SNPRINTF((output+used, out_len-used, "Reset Rx rate counter\n")); - - for (rate_idx = 0; rate_idx < 40; rate_idx++) { - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[rate_idx] = 0; - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[rate_idx] = 0; - } - } - } -#endif - break; - - case PHYDM_NBI_EN: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) { - - phydm_api_debug(pDM_Odm, PHYDM_API_NBI, (u4Byte *)var1, &used, output, &out_len); - /**/ - } - - - break; - - case PHYDM_CSI_MASK_EN: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) { - - phydm_api_debug(pDM_Odm, PHYDM_API_CSI_MASK, (u4Byte *)var1, &used, output, &out_len); - /**/ - } - - - break; - - case PHYDM_DFS: -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - { - u4Byte var[6] = {0}; - - for (i = 0; i < 6; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); - input_idx++; - } - } - - if (input_idx >= 1) - phydm_dfs_debug(pDM_Odm, var, &used, output, &out_len); - } -#endif - break; - - case PHYDM_IQK: -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate(pDM_Odm->priv); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_IQCalibrate(pDM_Odm->Adapter, FALSE); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); -#endif - break; - - case PHYDM_NHM: - { - u1Byte target_rssi; - u4Byte value32; - u2Byte nhm_period = 0xC350; //200ms - u1Byte IGI; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if(input_num == 1) { - - CCX_INFO->echo_NHM_en = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - - return; - } - - /* NMH trigger */ - if ((var1[0] <= 2) && (var1[0] != 0)) { - - CCX_INFO->echo_NHM_en = TRUE; - CCX_INFO->echo_IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - - target_rssi = CCX_INFO->echo_IGI - 10; - - CCX_INFO->NHM_th[0] = (target_rssi -15 + 10) * 2; - - for(i = 1; i <= 10; i ++) { - CCX_INFO->NHM_th[i] = CCX_INFO->NHM_th[0] + 6 * i; - } - - //4 1. store previous NHM setting - phydm_NHMsetting(pDM_Odm, STORE_NHM_SETTING); - - //4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms - CCX_INFO->NHM_period = nhm_period; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period*4)); - - //4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en - - - CCX_INFO->NHM_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; - CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; - - phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); - - for(i = 0; i <= 10; i ++) { - - if (i == 5) { - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, CCX_INFO->NHM_th[i], CCX_INFO->echo_IGI)); - } - else if (i == 10) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, CCX_INFO->NHM_th[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, CCX_INFO->NHM_th[i])); - } - - //4 4. Trigger NHM - phydm_NHMtrigger(pDM_Odm); - - } - - /*Get NHM results*/ - else if (var1[0] == 3) { - - IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); - - phydm_getNHMresult(pDM_Odm); - - //4 Resotre NHM setting - phydm_NHMsetting(pDM_Odm, RESTORE_NHM_SETTING); - - for(i = 0; i <= 11; i++) { - - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, CCX_INFO->NHM_result[i], CCX_INFO->echo_IGI)); - else if (i == 11) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, CCX_INFO->NHM_result[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, CCX_INFO->NHM_result[i])); - } - - CCX_INFO->echo_NHM_en = FALSE; - } - else { - - CCX_INFO->echo_NHM_en = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - - return; - } - } - break; - - case PHYDM_CLM: - { - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - //PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); - - if (input_num == 1) { - - CCX_INFO->echo_CLM_en = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - return; - } - - /* Set & trigger CLM */ - if (var1[0] == 1) { - - CCX_INFO->echo_CLM_en = TRUE; - CCX_INFO->CLM_period = 0xC350; /*100ms*/ - phydm_CLMsetting(pDM_Odm); - phydm_CLMtrigger(pDM_Odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor CLM for 200ms\n")); - } - - /* Get CLM results */ - else if (var1[0] == 2) { - - CCX_INFO->echo_CLM_en = FALSE; - phydm_getCLMresult(pDM_Odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", CCX_INFO->CLM_result*4)); - - } else { - - CCX_INFO->echo_CLM_en = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\n\r Error command !\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - } - } - break; - - case PHYDM_BB_INFO: - { - s4Byte value32 = 0; - - phydm_BB_Debug_Info(pDM_Odm, &used, output, &out_len); - - if (pDM_Odm->SupportICType & ODM_RTL8822B && input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - ODM_SetBBReg(pDM_Odm, 0x1988, 0x003fff00, var1[0]); - value32 = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); - value32 = (value32 & 0xff000000)>>24; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = condition num = %d, subcarriers = %d\n", "Over condition num subcarrier", var1[0], value32)); - ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x0); /*disable report condition number*/ - } - } - break; - - case PHYDM_TXBF: - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - if (var1[0] == 1) { - pBeamformingInfo->applyVmatrix = TRUE; - pBeamformingInfo->snding3SS = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 dont snding\n")); - } else if (var1[0] == 0) { - pBeamformingInfo->applyVmatrix = FALSE; - pBeamformingInfo->snding3SS = TRUE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n dont apply V matrix and 3SS 789 snding\n")); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n")); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n no TxBF !!\n")); -#endif -#endif - } - break; - - case PHYDM_PAUSE_DIG_EN: - - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) { - if (var1[0] == 0) { - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, (u1Byte)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Set IGI_value = ((%x))\n", var1[1])); - } else if (var1[0] == 1) { - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, (u1Byte)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Resume IGI_value\n")); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "echo (1:pause, 2resume) (IGI_value)\n")); - } - - break; - - case PHYDM_H2C: - - for (i = 0; i < 8; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) - phydm_h2C_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - - - break; - - default: - PHYDM_SNPRINTF((output + used, out_len - used, "SET, unknown command!\n")); - break; - - } -} - -#ifdef __ECOS -char *strsep(char **s, const char *ct) -{ - char *sbegin = *s; - char *end; - - if (sbegin == NULL) - return NULL; - - end = strpbrk(sbegin, ct); - if (end) - *end++ = '\0'; - *s = end; - return sbegin; -} -#endif - -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) -s4Byte -phydm_cmd( - IN PDM_ODM_T pDM_Odm, - IN char *input, - IN u4Byte in_len, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len -) -{ - char *token; - u4Byte Argc = 0; - char Argv[MAX_ARGC][MAX_ARGV]; - - do { - token = strsep(&input, ", "); - if (token) { - strcpy(Argv[Argc], token); - Argc++; - } else - break; - } while (Argc < MAX_ARGC); - - if (Argc == 1) - Argv[0][strlen(Argv[0]) - 1] = '\0'; - - phydm_cmd_parser(pDM_Odm, Argv, Argc, flag, output, out_len); - - return 0; -} -#endif - - -VOID -phydm_fw_trace_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*u1Byte debug_trace_11byte[60];*/ - u1Byte freg_num, c2h_seq, buf_0 = 0; - - if (!(pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)) - return; - - if (CmdLen > 12) - return; - - buf_0 = CmdBuf[0]; - freg_num = (buf_0 & 0xf); - c2h_seq = (buf_0 & 0xf0) >> 4; - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ - - /*strncpy(debug_trace_11byte,&CmdBuf[1],(CmdLen-1));*/ - /*debug_trace_11byte[CmdLen-1] = '\0';*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] CmdLen = (( %d ))\n", CmdLen));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", pDM_Odm->c2h_cmd_start));*/ - - - - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", pDM_Odm->pre_c2h_seq, c2h_seq));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", pDM_Odm->fw_buff_is_enpty));*/ - - if ((c2h_seq != pDM_Odm->pre_c2h_seq) && pDM_Odm->fw_buff_is_enpty == FALSE) { - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", pDM_Odm->fw_debug_trace)); - pDM_Odm->c2h_cmd_start = 0; - } - - if ((CmdLen - 1) > (60 - pDM_Odm->c2h_cmd_start)) { - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", pDM_Odm->fw_debug_trace)); - pDM_Odm->c2h_cmd_start = 0; - return; - } - - strncpy((char *)&(pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start]), (char *)&CmdBuf[1], (CmdLen-1)); - pDM_Odm->c2h_cmd_start += (CmdLen - 1); - pDM_Odm->fw_buff_is_enpty = FALSE; - - if (freg_num == 0 || pDM_Odm->c2h_cmd_start >= 60) { - if (pDM_Odm->c2h_cmd_start < 60) - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; - else - pDM_Odm->fw_debug_trace[59] = '\0'; - - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace)); - /*DbgPrint("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace);*/ - pDM_Odm->c2h_cmd_start = 0; - pDM_Odm->fw_buff_is_enpty = TRUE; - } - - pDM_Odm->pre_c2h_seq = c2h_seq; -} - -VOID -phydm_fw_trace_handler_code( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte function = Buffer[0]; - u1Byte dbg_num = Buffer[1]; - u2Byte content_0 = (((u2Byte)Buffer[3])<<8)|((u2Byte)Buffer[2]); - u2Byte content_1 = (((u2Byte)Buffer[5])<<8)|((u2Byte)Buffer[4]); - u2Byte content_2 = (((u2Byte)Buffer[7])<<8)|((u2Byte)Buffer[6]); - u2Byte content_3 = (((u2Byte)Buffer[9])<<8)|((u2Byte)Buffer[8]); - u2Byte content_4 = (((u2Byte)Buffer[11])<<8)|((u2Byte)Buffer[10]); - - if(CmdLen >12) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Invalid cmd length (( %d )) >12 \n", CmdLen)); - } - - //ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", - // function, dbg_num, content_0, content_1, content_2, content_3, content_4)); - - /*--------------------------------------------*/ -#if (CONFIG_RA_FW_DBG_CODE) - if(function == RATE_DECISION) { - if(dbg_num == 0) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); - } else if(content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); - } - } else if(dbg_num == 1) { - if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); - } else if (content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); - phydm_print_rate(pDM_Odm, (u1Byte)content_4, ODM_FW_DEBUG_TRACE); - } else if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); - } else if (content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); - } - } - - else if(dbg_num == 3) { - if (content_0 == 1) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); - else if (content_0 == 2) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); - else if (content_0 == 3) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((Rate Down Hold)) RA_CNT=((%d))\n", content_1)); - else if (content_0 == 4) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); - else if (content_0 == 8) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); - } - - else if (dbg_num == 4) { - if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); - /**/ - } else if (content_0 == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); - /**/ - } - } - - else if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); - } else if(content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); - } - } - else if(dbg_num == 0x60) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); - } else if(content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); - } - } - } - /*--------------------------------------------*/ - else if (function == INIT_RA_TABLE){ - if(dbg_num == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); - } - - } - /*--------------------------------------------*/ - else if (function == RATE_UP) { - if(dbg_num == 2) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate -> return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); - } - } else if(dbg_num == 5) { - if (content_0 == 0) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); - else if (content_0 == 1) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); - } - - } - /*--------------------------------------------*/ - else if (function == RATE_DOWN) { - if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((Rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); - } - } - } else if (function == TRY_DONE) { - if (dbg_num == 1) { - if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); - /**/ - } - } else if (dbg_num == 2) { - if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } - } - } - /*--------------------------------------------*/ - else if (function == RA_H2C) { - if (dbg_num == 1) { - if (content_0 == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); - /**/ - /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid , 0); //RA MASK*/ - } - #if 0 - else if (dbg_num == 2) { - - if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), Rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); - /**/ - } - } - #endif - } - } - /*--------------------------------------------*/ - else if (function == F_RATE_AP_RPT) { - if(dbg_num == 1) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); - } - } else if(dbg_num == 2) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); - } - } else if(dbg_num == 3) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 4) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 6) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); - } - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); - /**/ - } -#else - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); -#endif - /*--------------------------------------------*/ - - -} - -VOID -phydm_fw_trace_handler_8051( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if 0 - if (CmdLen >= 3) - CmdBuf[CmdLen - 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(CmdBuf[3]))); -#else - - int i = 0; - u1Byte Extend_c2hSubID = 0, Extend_c2hDbgLen = 0, Extend_c2hDbgSeq = 0; - u1Byte fw_debug_trace[128]; - pu1Byte Extend_c2hDbgContent = 0; - - if (CmdLen > 127) - return; - - Extend_c2hSubID = Buffer[0]; - Extend_c2hDbgLen = Buffer[1]; - Extend_c2hDbgContent = Buffer + 2; /*DbgSeq+DbgContent for show HEX*/ - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, Extend_c2hDbgLen=%d\n", - Extend_c2hSubID, Extend_c2hDbgLen)); - - RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", Extend_c2hDbgContent, CmdLen-2); - #endif - -GoBackforAggreDbgPkt: - i = 0; - Extend_c2hDbgSeq = Buffer[2]; - Extend_c2hDbgContent = Buffer + 3; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", Extend_c2hDbgSeq)); - #endif - - for (; ; i++) { - fw_debug_trace[i] = Extend_c2hDbgContent[i]; - if (Extend_c2hDbgContent[i + 1] == '\0') { - fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); - break; - } else if (Extend_c2hDbgContent[i] == '\n') { - fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); - Buffer = Extend_c2hDbgContent + i + 3; - goto GoBackforAggreDbgPkt; - } - } - - -#endif -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +PHYDM_InitDebugSetting( + IN PDM_ODM_T pDM_Odm +) +{ + pDM_Odm->DebugLevel = ODM_DBG_TRACE; + + pDM_Odm->fw_DebugComponents = 0; + pDM_Odm->DebugComponents = + \ +#if DBG +/*BB Functions*/ +/* ODM_COMP_DIG |*/ +/* ODM_COMP_RA_MASK |*/ +/* ODM_COMP_DYNAMIC_TXPWR |*/ +/* ODM_COMP_FA_CNT |*/ +/* ODM_COMP_RSSI_MONITOR |*/ +/* ODM_COMP_SNIFFER |*/ +/* ODM_COMP_ANT_DIV |*/ +/* ODM_COMP_NOISY_DETECT |*/ +/* ODM_COMP_RATE_ADAPTIVE |*/ +/* ODM_COMP_PATH_DIV |*/ +/* ODM_COMP_DYNAMIC_PRICCA |*/ +/* ODM_COMP_DYNAMIC_ANT_WEIGHTING |*/ +/* ODM_COMP_MP |*/ +/* ODM_COMP_CFO_TRACKING |*/ +/* ODM_COMP_ACS |*/ +/* PHYDM_COMP_ADAPTIVITY |*/ +/* PHYDM_COMP_RA_DBG |*/ +/* PHYDM_COMP_TXBF |*/ +/* ODM_COMP_TDMA_DIG |*/ + +/*MAC Functions*/ +/* ODM_COMP_EDCA_TURBO |*/ +/* ODM_FW_DEBUG_TRACE |*/ + +/*RF Functions*/ +/* ODM_COMP_TX_PWR_TRACK |*/ +/* ODM_COMP_CALIBRATION |*/ + +/*Common*/ +/* ODM_PHY_CONFIG |*/ +/* ODM_COMP_INIT |*/ +/* ODM_COMP_COMMON |*/ +/* ODM_COMP_API |*/ + + +#endif + 0; + + pDM_Odm->fw_buff_is_enpty = TRUE; + pDM_Odm->pre_c2h_seq = 0; +} + +VOID +phydm_BB_RxHang_Info( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + u4Byte value32 = 0; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + return; + + value32 = ODM_GetBBReg(pDM_Odm, 0xF80 , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32)); + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ODM_SetBBReg(pDM_Odm, 0x198c , BIT2|BIT1|BIT0, 7); + + /* dbg_port = basic state machine */ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x000); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "basic state machine", value32)); + } + + /* dbg_port = state machine */ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x007); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "state machine", value32)); + } + + /* dbg_port = CCA-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x204); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "CCA-related", value32)); + } + + + /* dbg_port = edcca/rxd*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x278); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "edcca/rxd", value32)); + } + + /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x290); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", value32)); + } + + /* dbg_port = bf-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B2); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); + } + + /* dbg_port = bf-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B8); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); + } + + /* dbg_port = txon/rxd*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA03); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "txon/rxd", value32)); + } + + /* dbg_port = l_rate/l_length*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0B); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "l_rate/l_length", value32)); + } + + /* dbg_port = rxd/rxd_hit*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0D); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32)); + } + + /* dbg_port = dis_cca*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAA0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "dis_cca", value32)); + } + + + /* dbg_port = tx*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAB0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "tx", value32)); + } + + /* dbg_port = rx plcp*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD1); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD2); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD3); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); + } + +} + +VOID +phydm_bb_debug_info_n_series( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + u4Byte value32 = 0, value32_1 = 0, value32_2 = 0, value32_3 = 0; + u1Byte rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; + u1Byte rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; + + s1Byte rxevm_0 = 0, rxevm_1 = 0; + s4Byte short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; + s4Byte scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; + s4Byte cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a= 0, acq_cfo_b = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + + /*AGC result*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xdd0, bMaskDWord); + rf_gain_a = value32 & 0x3f; + rf_gain_a = rf_gain_a << 1; + + rf_gain_b = (value32 >> 8) & 0x3f; + rf_gain_b = rf_gain_b << 1; + + rf_gain_c = (value32 >> 16) & 0x3f; + rf_gain_c = rf_gain_c << 1; + + rf_gain_d = (value32 >> 24) & 0x3f; + rf_gain_d = rf_gain_d << 1; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d)); + + /*SNR report*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xdd4, bMaskDWord); + rx_snr_a = value32 & 0xff; + rx_snr_a = rx_snr_a >> 1; + + rx_snr_b = (value32>>8) & 0xff; + rx_snr_b = rx_snr_b >> 1; + + rx_snr_c = (value32>>16) & 0xff; + rx_snr_c = rx_snr_c >> 1; + + rx_snr_d = (value32>>24) & 0xff; + rx_snr_d = rx_snr_d >> 1; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d)); + + /* PostFFT related info*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xdd8 , bMaskDWord); + + rxevm_0 = (s1Byte)((value32 & bMaskByte2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s1Byte)((value32 & bMaskByte3) >> 24); + rxevm_1 /= 2; + if (rxevm_1 < -63) + rxevm_1 = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1)); + + /*CFO Report Info*/ + ODM_SetBBReg(pDM_Odm, 0xd00, BIT26, 1); + + /*Short CFO*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xdac , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xdb0 , bMaskDWord); + + short_cfo_b = (s4Byte)(value32 & 0xfff); /*S(12,11)*/ + short_cfo_a = (s4Byte)((value32 & 0x0fff0000)>>16); + + long_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ + long_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); + + /*SFO 2's to dec*/ + if (short_cfo_a > 2047) + short_cfo_a = short_cfo_a - 4096; + if (short_cfo_b > 2047) + short_cfo_b = short_cfo_b - 4096; + + short_cfo_a = (short_cfo_a * 312500) / 2048; + short_cfo_b = (short_cfo_b * 312500) / 2048; + + /*LFO 2's to dec*/ + + if (long_cfo_a > 4095) + long_cfo_a = long_cfo_a - 8192; + + if (long_cfo_b > 4095) + long_cfo_b = long_cfo_b - 8192; + + long_cfo_a = long_cfo_a * 312500 / 4096; + long_cfo_b = long_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, short_cfo_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, long_cfo_b)); + + /*SCFO*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xdb8 , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xdb4 , bMaskDWord); + + scfo_b = (s4Byte)(value32 & 0x7ff); /*S(11,10)*/ + scfo_a = (s4Byte)((value32 & 0x07ff0000)>>16); + + if (scfo_a > 1023) + scfo_a = scfo_a - 2048; + + if (scfo_b > 1023) + scfo_b = scfo_b - 2048; + + scfo_a = scfo_a * 312500 / 1024; + scfo_b = scfo_b * 312500 / 1024; + + avg_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ + avg_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); + + if (avg_cfo_a > 4095) + avg_cfo_a = avg_cfo_a - 8192; + + if (avg_cfo_b > 4095) + avg_cfo_b = avg_cfo_b - 8192; + + avg_cfo_a = avg_cfo_a * 312500 / 4096; + avg_cfo_b = avg_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Value SCFO(Hz) ", scfo_a, scfo_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, avg_cfo_b)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xdbc , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xde0 , bMaskDWord); + + cfo_end_b = (s4Byte)(value32 & 0x1fff); /*S(13,12)*/ + cfo_end_a = (s4Byte)((value32 & 0x1fff0000)>>16); + + if (cfo_end_a > 4095) + cfo_end_a = cfo_end_a - 8192; + + if (cfo_end_b > 4095) + cfo_end_b = cfo_end_b - 8192; + + cfo_end_a = cfo_end_a * 312500 / 4096; + cfo_end_b = cfo_end_b * 312500 / 4096; + + acq_cfo_b = (s4Byte)(value32_1 & 0x1fff); /*S(13,12)*/ + acq_cfo_a = (s4Byte)((value32_1 & 0x1fff0000)>>16); + + if (acq_cfo_a > 4095) + acq_cfo_a = acq_cfo_a - 8192; + + if (acq_cfo_b > 4095) + acq_cfo_b = acq_cfo_b - 8192; + + acq_cfo_a = acq_cfo_a * 312500 / 4096; + acq_cfo_b = acq_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, cfo_end_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, acq_cfo_b)); + +} + + +VOID +phydm_BB_Debug_Info( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + char *tmp_string = NULL; + + u1Byte RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; + static u1Byte vRX_BW ; + u4Byte value32, value32_1, value32_2, value32_3; + s4Byte SFO_A, SFO_B, SFO_C, SFO_D; + s4Byte LFO_A, LFO_B, LFO_C, LFO_D; + static u1Byte MCSS, Tail, Parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, vNsts, vtxops, vrsv2, vbrsv, bf, vbcrc; + static u2Byte HLength, htcrc8, Length; + static u2Byte vpaid; + static u2Byte vLength, vhtcrc8, vMCSS, vTail, vbTail; + static u1Byte HMCSS, HRX_BW; + + u1Byte pwDB; + s1Byte RXEVM_0, RXEVM_1, RXEVM_2 ; + u1Byte RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD; + u1Byte RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD; + s4Byte sig_power; + + const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"}; + + /* + const double evm_comp_20M = 0.579919469776867; //10*log10(64.0/56.0) + const double evm_comp_40M = 0.503051183113957; //10*log10(128.0/114.0) + const double evm_comp_80M = 0.244245993314183; //10*log10(256.0/242.0) + const double evm_comp_160M = 0.244245993314183; //10*log10(512.0/484.0) + */ + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + phydm_bb_debug_info_n_series(pDM_Odm, &used, output, &out_len); + return; + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + + /*BW & Mode Detection*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xf80 , bMaskDWord); + value32_2 = value32; + RX_HT_BW = (u1Byte)(value32 & 0x1); + RX_VHT_BW = (u1Byte)((value32 >> 1) & 0x3); + RXSC = (u1Byte)(value32 & 0x78); + value32_1 = (value32 & 0x180) >> 7; + RX_HT = (u1Byte)(value32_1); + + RX_BW = 0; + + if (RX_HT == 2) { + if (RX_VHT_BW == 0) { + tmp_string = "20M"; + } else if (RX_VHT_BW == 1) { + tmp_string = "40M"; + } else { + tmp_string = "80M"; + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "VHT", tmp_string)); + RX_BW = RX_VHT_BW; + } else if (RX_HT == 1) { + if (RX_HT_BW == 0) { + tmp_string = "20M"; + } else if (RX_HT_BW == 1) { + tmp_string = "40M"; + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "HT", tmp_string)); + RX_BW = RX_HT_BW; + } else { + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "Mode", "Legacy")); + } + + if (RX_HT != 0) { + if (RXSC == 0) + tmp_string = "duplicate/full bw"; + else if (RXSC == 1) + tmp_string = "usc20-1"; + else if (RXSC == 2) + tmp_string = "lsc20-1"; + else if (RXSC == 3) + tmp_string = "usc20-2"; + else if (RXSC == 4) + tmp_string = "lsc20-2"; + else if (RXSC == 9) + tmp_string = "usc40"; + else if (RXSC == 10) + tmp_string = "lsc40"; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s", tmp_string)); + } + + /* RX signal power and AGC related info*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xF90 , bMaskDWord); + pwDB = (u1Byte)((value32 & bMaskByte1) >> 8); + pwDB = pwDB >> 1; + sig_power = -110 + pwDB; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); + RX_SNR_pathA = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathA = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathA *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); + RX_SNR_pathB = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathB = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathB *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); + RX_SNR_pathC = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathC = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathC *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); + RX_SNR_pathD = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathD = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathD *= 2; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD)); + + + /* RX Counter related info*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xF08, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA Counter", ((value32&0xFFFF0000)>>16))); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFD0, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail Counter", value32&0xFFFF)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFC4, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFCC, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA Counter", value32&0xFFFF)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFBC, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (Parity Fail/Rate Illegal) Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + + value32_1 = ODM_GetBBReg(pDM_Odm, 0xFC8, bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xFC0, bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2&0xFFFF0000)>>16), value32_1&0xFFFF)); + + /* PostFFT related info*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xF8c , bMaskDWord); + RXEVM_0 = (s1Byte)((value32 & bMaskByte2) >> 16); + RXEVM_0 /= 2; + if (RXEVM_0 < -63) + RXEVM_0 = 0; + + RXEVM_1 = (s1Byte)((value32 & bMaskByte3) >> 24); + RXEVM_1 /= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xF88 , bMaskDWord); + RXEVM_2 = (s1Byte)((value32 & bMaskByte2) >> 16); + RXEVM_2 /= 2; + + if (RXEVM_1 < -63) + RXEVM_1 = 0; + if (RXEVM_2 < -63) + RXEVM_2 = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xF8C , bMaskDWord); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + + /*BW & Mode Detection*/ + + /*Reset Page F Counter*/ + ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 0); + + /*CFO Report Info*/ + /*Short CFO*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xd0c , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd4c , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd8c , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdcc , bMaskDWord); + + SFO_A = (s4Byte)(value32 & 0xfff); + SFO_B = (s4Byte)(value32_1 & 0xfff); + SFO_C = (s4Byte)(value32_2 & 0xfff); + SFO_D = (s4Byte)(value32_3 & 0xfff); + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + /*SFO 2's to dec*/ + if (SFO_A > 2047) + SFO_A = SFO_A - 4096; + SFO_A = (SFO_A * 312500) / 2048; + if (SFO_B > 2047) + SFO_B = SFO_B - 4096; + SFO_B = (SFO_B * 312500) / 2048; + if (SFO_C > 2047) + SFO_C = SFO_C - 4096; + SFO_C = (SFO_C * 312500) / 2048; + if (SFO_D > 2047) + SFO_D = SFO_D - 4096; + SFO_D = (SFO_D * 312500) / 2048; + + /*LFO 2's to dec*/ + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Short CFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + + /*SCFO*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xd10 , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd50 , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd90 , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd0 , bMaskDWord); + + SFO_A = (s4Byte)(value32 & 0x7ff); + SFO_B = (s4Byte)(value32_1 & 0x7ff); + SFO_C = (s4Byte)(value32_2 & 0x7ff); + SFO_D = (s4Byte)(value32_3 & 0x7ff); + + if (SFO_A > 1023) + SFO_A = SFO_A - 2048; + + if (SFO_B > 2047) + SFO_B = SFO_B - 4096; + + if (SFO_C > 2047) + SFO_C = SFO_C - 4096; + + if (SFO_D > 2047) + SFO_D = SFO_D - 4096; + + SFO_A = SFO_A * 312500 / 1024; + SFO_B = SFO_B * 312500 / 1024; + SFO_C = SFO_C * 312500 / 1024; + SFO_D = SFO_D * 312500 / 1024; + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf20 , bMaskDWord); /*L SIG*/ + + Tail = (u1Byte)((value32 & 0xfc0000) >> 16); + Parity = (u1Byte)((value32 & 0x20000) >> 16); + Length = (u2Byte)((value32 & 0x1ffe00) >> 8); + rsv = (u1Byte)(value32 & 0x10); + MCSS = (u1Byte)(value32 & 0x0f); + + switch (MCSS) { + case 0x0b: + idx = 0; + break; + case 0x0f: + idx = 1; + break; + case 0x0a: + idx = 2; + break; + case 0x0e: + idx = 3; + break; + case 0x09: + idx = 4; + break; + case 0x08: + idx = 5; + break; + case 0x0c: + idx = 6; + break; + default: + idx = 6; + break; + + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "L-SIG")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "Rate", L_rate[idx])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/Length/Parity", rsv, RX_BW, Length)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*HT SIG*/ + if (RX_HT == 1) { + + HMCSS = (u1Byte)(value32 & 0x7F); + HRX_BW = (u1Byte)(value32 & 0x80); + HLength = (u2Byte)((value32 >> 8) & 0xffff); + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG1")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/Length", HMCSS, HRX_BW, HLength)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*HT SIG*/ + + if (RX_HT == 1) { + smooth = (u1Byte)(value32 & 0x01); + htsound = (u1Byte)(value32 & 0x02); + rsv = (u1Byte)(value32 & 0x04); + agg = (u1Byte)(value32 & 0x08); + stbc = (u1Byte)(value32 & 0x30); + fec = (u1Byte)(value32 & 0x40); + sgi = (u1Byte)(value32 & 0x80); + htltf = (u1Byte)((value32 & 0x300) >> 8); + htcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); + Tail = (u1Byte)((value32 & 0xfc0000) >> 16); + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG2")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x", "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/Tail", sgi, htltf, htcrc8, Tail)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*VHT SIG A1*/ + if (RX_HT == 2) { + /* value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord);*/ + vRX_BW = (u1Byte)(value32 & 0x03); + vrsv = (u1Byte)(value32 & 0x04); + vstbc = (u1Byte)(value32 & 0x08); + vgid = (u1Byte)((value32 & 0x3f0) >> 4); + vNsts = (u1Byte)(((value32 & 0x1c00) >> 8) + 1); + vpaid = (u2Byte)(value32 & 0x3fe); + vtxops = (u1Byte)((value32 & 0x400000) >> 20); + vrsv2 = (u1Byte)((value32 & 0x800000) >> 20); + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A1")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", vRX_BW, vrsv, vstbc, vgid, vNsts, vpaid, vtxops, vrsv2)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*VHT SIG*/ + + if (RX_HT == 2) { + /*value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); */ /*VHT SIG*/ + + //sgi=(u1Byte)(value32&0x01); + sgiext = (u1Byte)(value32 & 0x03); + //fec = (u1Byte)(value32&0x04); + fecext = (u1Byte)(value32 & 0x0C); + + vMCSS = (u1Byte)(value32 & 0xf0); + bf = (u1Byte)((value32 & 0x100) >> 8); + vrsv = (u1Byte)((value32 & 0x200) >> 8); + vhtcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); + vTail = (u1Byte)((value32 & 0xfc0000) >> 16); + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A2")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/Tail", sgiext, fecext, vMCSS, bf, vrsv, vhtcrc8, vTail)); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf34 , bMaskDWord); /*VHT SIG*/ + { + vLength = (u2Byte)(value32 & 0x1fffff); + vbrsv = (u1Byte)((value32 & 0x600000) >> 20); + vbTail = (u2Byte)((value32 & 0x1f800000) >> 20); + vbcrc = (u1Byte)((value32 & 0x80000000) >> 28); + + } + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-B")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "Length/Rsv/Tail/CRC", vLength, vbrsv, vbTail, vbcrc)); + + /*for Condition number*/ + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + s4Byte condition_num = 0; + char *factor = NULL; + + ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x1); /*enable report condition number*/ + + condition_num = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); + condition_num = (condition_num & 0x3ffff) >> 4; + + if (*pDM_Odm->pBandWidth == ODM_BW80M) + factor = "256/234"; + else if (*pDM_Odm->pBandWidth == ODM_BW40M) + factor = "128/108"; + else if (*pDM_Odm->pBandWidth == ODM_BW20M) { + if (RX_HT != 2 || RX_HT != 1) + factor = "64/52"; /*HT or VHT*/ + else + factor = "64/48"; /*legacy*/ + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition Number", condition_num, factor)); + + } + +} +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void phydm_sbd_check( + IN PDM_ODM_T pDM_Odm +) +{ + static u4Byte pkt_cnt = 0; + static BOOLEAN sbd_state = 0; + u4Byte sym_count, count, value32; + + if (sbd_state == 0) { + pkt_cnt++; + if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ + ODM_SetTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, 0); /*ms*/ + sbd_state = 1; + } + } else { /*read counter*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xF98, bMaskDWord); + sym_count = (value32 & 0x7C000000) >> 26; + count = (value32 & 0x3F00000) >> 20; + DbgPrint("#SBD# sym_count %d count %d\n", sym_count, count); + sbd_state = 0; + } +} + +void phydm_sbd_callback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + +#if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_Odm->sbdcnt_workitem); +#else + phydm_sbd_check(pDM_Odm); +#endif +} + +void phydm_sbd_workitem_callback( + IN PVOID pContext +) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + phydm_sbd_check(pDM_Odm); +} +#endif +VOID +phydm_BasicDbgMessage +( + IN PVOID pDM_VOID +) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm , PHYDM_FALSEALMCNT); + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u2Byte macid, phydm_macid, client_cnt = 0; + PSTA_INFO_T pEntry; + s4Byte tmp_val = 0; + u1Byte tmp_val_u1 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", pDM_Odm->phydm_sys_up_time)); + + if (pDM_Odm->bLinked) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Curr_STA_ID = 0x%x\n", pDM_Odm->curr_station_id)); + + /*Print RX Rate*/ + if (pDM_Odm->RxRate <= ODM_RATE11M) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", + pDM_Odm->cck_lna_idx, pDM_Odm->cck_vga_idx)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", + pDM_Odm->ofdm_agc_idx[0], pDM_Odm->ofdm_agc_idx[1], pDM_Odm->ofdm_agc_idx[2], pDM_Odm->ofdm_agc_idx[3])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, RxRate:", + (pDM_Odm->RSSI_A == 0xff) ? 0 : pDM_Odm->RSSI_A , + (pDM_Odm->RSSI_B == 0xff) ? 0 : pDM_Odm->RSSI_B , + (pDM_Odm->RSSI_C == 0xff) ? 0 : pDM_Odm->RSSI_C, + (pDM_Odm->RSSI_D == 0xff) ? 0 : pDM_Odm->RSSI_D)); + + phydm_print_rate(pDM_Odm, pDM_Odm->RxRate, ODM_COMP_COMMON); + + /*Print TX Rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (IS_STA_VALID(pEntry)) { + + phydm_macid = (pDM_Odm->platform2phydm_macid_table[macid]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TXRate [%d]:", macid)); + phydm_print_rate(pDM_Odm, pRA_Table->link_tx_rate[macid], ODM_COMP_COMMON); + + client_cnt++; + + if (client_cnt == pDM_Odm->number_linked_client) + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP { TX, RX, total} = {%d, %d, %d }Mbps, TrafficLoad = (%d))\n", + pDM_Odm->tx_tp, pDM_Odm->rx_tp, pDM_Odm->total_tp, pDM_Odm->TrafficLoad)); + + tmp_val_u1 = (pCfoTrack->CrystalCap > pCfoTrack->DefXCap) ? (pCfoTrack->CrystalCap - pCfoTrack->DefXCap) : (pCfoTrack->DefXCap - pCfoTrack->CrystalCap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n", + pCfoTrack->CFO_ave_pre, ((pCfoTrack->CrystalCap > pCfoTrack->DefXCap)?"+":"-"),tmp_val_u1)); + + /* Condition number */ + #if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + tmp_val = phydm_get_condition_number_8822B(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condition number = ((%d))\n", tmp_val)); + } + #endif + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + FalseAlmCnt->Cnt_CCK_CCA, FalseAlmCnt->Cnt_OFDM_CCA, FalseAlmCnt->Cnt_CCA_all)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all)); + + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail, FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); + } + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, Num_client = %d, RSSI_Min = %d, CurrentIGI = 0x%x, bNoisy=%d\n\n", + pDM_Odm->bLinked, pDM_Odm->number_linked_client, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue, pDM_Odm->NoisyDecision)); + +/* + temp_reg = ODM_GetBBReg(pDM_Odm, 0xDD0, bMaskByte0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetBBReg(pDM_Odm, 0xDDc, bMaskByte1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0x3fe0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg)); +*/ + +#endif +} + + +VOID phydm_BasicProfile( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + char *Cut = NULL; + char *ICType = NULL; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + u4Byte commit_ver = 0; + u4Byte date = 0; + char *commit_by = NULL; + u4Byte release_ver = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); + + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + ICType = "RTL8188E"; + date = RELEASE_DATE_8188E; + commit_by = COMMIT_BY_8188E; + release_ver = RELEASE_VERSION_8188E; + #endif + } + #if (RTL8812A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8812) { + ICType = "RTL8812A"; + date = RELEASE_DATE_8812A; + commit_by = COMMIT_BY_8812A; + release_ver = RELEASE_VERSION_8812A; + } + #endif + #if (RTL8821A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8821) { + ICType = "RTL8821A"; + date = RELEASE_DATE_8821A; + commit_by = COMMIT_BY_8821A; + release_ver = RELEASE_VERSION_8821A; + } + #endif + #if (RTL8192E_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + ICType = "RTL8192E"; + date = RELEASE_DATE_8192E; + commit_by = COMMIT_BY_8192E; + release_ver = RELEASE_VERSION_8192E; + } + #endif + #if (RTL8723B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723B) { + ICType = "RTL8723B"; + date = RELEASE_DATE_8723B; + commit_by = COMMIT_BY_8723B; + release_ver = RELEASE_VERSION_8723B; + } + #endif + #if (RTL8814A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8814A) { + ICType = "RTL8814A"; + date = RELEASE_DATE_8814A; + commit_by = COMMIT_BY_8814A; + release_ver = RELEASE_VERSION_8814A; + } + #endif + #if (RTL8881A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8881A) { + ICType = "RTL8881A"; + /**/ + } + #endif + #if (RTL8822B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8822B) { + ICType = "RTL8822B"; + date = RELEASE_DATE_8822B; + commit_by = COMMIT_BY_8822B; + release_ver = RELEASE_VERSION_8822B; + } + #endif + #if (RTL8197F_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8197F) { + ICType = "RTL8197F"; + date = RELEASE_DATE_8197F; + commit_by = COMMIT_BY_8197F; + release_ver = RELEASE_VERSION_8197F; + } + #endif + + #if (RTL8703B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8703B) { + + ICType = "RTL8703B"; + date = RELEASE_DATE_8703B; + commit_by = COMMIT_BY_8703B; + release_ver = RELEASE_VERSION_8703B; + + } + #endif + #if (RTL8195A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8195A) { + ICType = "RTL8195A"; + /**/ + } + #endif + #if (RTL8188F_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + ICType = "RTL8188F"; + date = RELEASE_DATE_8188F; + commit_by = COMMIT_BY_8188F; + release_ver = RELEASE_VERSION_8188F; + } + #endif + #if (RTL8723D_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723D) { + ICType = "RTL8723D"; + /**/ + } + #endif + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC Type", ICType, pDM_Odm->bIsMPChip ? "Yes" : "No")); + + if (pDM_Odm->CutVersion == ODM_CUT_A) + Cut = "A"; + else if (pDM_Odm->CutVersion == ODM_CUT_B) + Cut = "B"; + else if (pDM_Odm->CutVersion == ODM_CUT_C) + Cut = "C"; + else if (pDM_Odm->CutVersion == ODM_CUT_D) + Cut = "D"; + else if (pDM_Odm->CutVersion == ODM_CUT_E) + Cut = "E"; + else if (pDM_Odm->CutVersion == ODM_CUT_F) + Cut = "F"; + else if (pDM_Odm->CutVersion == ODM_CUT_I) + Cut = "I"; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Cut Version", Cut)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Version", ODM_GetHWImgVersion(pDM_Odm))); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release Version", release_ver)); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + { + PADAPTER Adapter = pDM_Odm->Adapter; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", Adapter->MgntInfo.FirmwareVersion, Adapter->MgntInfo.FirmwareSubVersion)); + } +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + { + struct rtl8192cd_priv *priv = pDM_Odm->priv; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); + } +#else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", pHalData->FirmwareVersion, pHalData->FirmwareSubVersion)); + } +#endif + //1 PHY DM Version List + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM Version %")); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code Base", PHYDM_CODE_BASE)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Adaptivity", ADAPTIVITY_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); +#endif + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto Channel Selection", ACS_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Path Diversity", PATHDIV_VERSION)); + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); + +#endif +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F)); +#endif + *_used = used; + *_out_len = out_len; + +} + +VOID +phydm_fw_trace_en_h2c( + IN PVOID pDM_VOID, + IN BOOLEAN enable, + IN u4Byte fw_debug_component, + IN u4Byte monitor_mode, + IN u4Byte macid +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte H2C_Parameter[7] = {0}; + u1Byte cmd_length; + + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES){ + + H2C_Parameter[0] = enable; + H2C_Parameter[1] = (u1Byte)(fw_debug_component & bMaskByte0); + H2C_Parameter[2] = (u1Byte)((fw_debug_component & bMaskByte1)>>8); + H2C_Parameter[3] = (u1Byte)((fw_debug_component & bMaskByte2)>>16); + H2C_Parameter[4] = (u1Byte)((fw_debug_component & bMaskByte3)>>24); + H2C_Parameter[5] = (u1Byte)monitor_mode; + H2C_Parameter[6] = (u1Byte)macid; + cmd_length = 7; + + } else { + + H2C_Parameter[0] = enable; + H2C_Parameter[1] = (u1Byte)monitor_mode; + H2C_Parameter[2] = (u1Byte)macid; + cmd_length = 3; + } + + + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); + if (monitor_mode == 0){ + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); + } + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_FW_TRACE_EN, cmd_length, H2C_Parameter); +} + + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) +BOOLEAN +phydm_api_set_txagc( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate, + IN BOOLEAN bSingleRate + ) +{ + BOOLEAN ret = FALSE; + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { + if (bSingleRate) { +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + ret = phydm_write_txagc_1byte_8822b(pDM_Odm, PowerIndex, Path, HwRate); +#endif +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + ret = phydm_write_txagc_1byte_8821c(pDM_Odm, PowerIndex, Path, HwRate); +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + SetCurrentTxAGC(pDM_Odm->priv, Path, HwRate, (u1Byte)PowerIndex); +#endif + + } else { + u1Byte i; +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + ret = config_phydm_write_txagc_8822b(pDM_Odm, PowerIndex, Path, HwRate); +#endif +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + ret = config_phydm_write_txagc_8821c(pDM_Odm, PowerIndex, Path, HwRate); +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + for (i = 0; i < 4; i++) + SetCurrentTxAGC(pDM_Odm->priv, Path, (HwRate + i), (u1Byte)PowerIndex); +#endif + } + } +#endif + + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ret = config_phydm_write_txagc_8197f(pDM_Odm, PowerIndex, Path, HwRate); +#endif + + return ret; +} + +u1Byte +phydm_api_get_txagc( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u1Byte ret = 0; + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ret = config_phydm_read_txagc_8822b(pDM_Odm, Path, HwRate); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ret = config_phydm_read_txagc_8197f(pDM_Odm, Path, HwRate); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8821C) + ret = config_phydm_read_txagc_8821c(pDM_Odm, Path, HwRate); +#endif + + return ret; +} + + +BOOLEAN +phydm_api_switch_bw_channel( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + BOOLEAN ret = FALSE; + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ret = config_phydm_switch_channel_bw_8822b(pDM_Odm, central_ch, primary_ch_idx, bandwidth); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ret = config_phydm_switch_channel_bw_8197f(pDM_Odm, central_ch, primary_ch_idx, bandwidth); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8821C) + ret = config_phydm_switch_channel_bw_8821c(pDM_Odm, central_ch, primary_ch_idx, bandwidth); +#endif + + return ret; +} + +BOOLEAN +phydm_api_trx_mode( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ) +{ + BOOLEAN ret = FALSE; + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ret = config_phydm_trx_mode_8822b(pDM_Odm, TxPath, RxPath, bTx2Path); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + ret = config_phydm_trx_mode_8197f(pDM_Odm, TxPath, RxPath, bTx2Path); +#endif + + return ret; +} +#endif + +VOID +phydm_get_per_path_txagc( + IN PVOID pDM_VOID, + IN u1Byte path, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte rate_idx; + u1Byte txagc; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + +#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) + if (((pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || + ((pDM_Odm->SupportICType & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { + for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { + if (rate_idx == ODM_RATE1M) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); + else if (rate_idx == ODM_RATE6M) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "OFDM====>")); + else if (rate_idx == ODM_RATEMCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 1ss====>")); + else if (rate_idx == ODM_RATEMCS8) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 2ss====>")); + else if (rate_idx == ODM_RATEMCS16) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 3ss====>")); + else if (rate_idx == ODM_RATEMCS24) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 4ss====>")); + else if (rate_idx == ODM_RATEVHTSS1MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 1ss====>")); + else if (rate_idx == ODM_RATEVHTSS2MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 2ss====>")); + else if (rate_idx == ODM_RATEVHTSS3MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); + else if (rate_idx == ODM_RATEVHTSS4MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); + + txagc = phydm_api_get_txagc(pDM_Odm, (ODM_RF_RADIO_PATH_E) path, rate_idx); + if (config_phydm_read_txagc_check(txagc)) + PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); + else + PHYDM_SNPRINTF((output + used, out_len - used, " 0x%s ", "xx")); + } + } +#endif +} + + +VOID +phydm_get_txagc( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + /* Path-A */ + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "Path-A====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_A, _used, output, _out_len); + + /* Path-B */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-B====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_B, _used, output, _out_len); + + /* Path-C */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-C====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_C, _used, output, _out_len); + + /* Path-D */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-D====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_D, _used, output, _out_len); + +} + +VOID +phydm_set_txagc( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + +/*dm_value[1] = Path*/ +/*dm_value[2] = HwRate*/ +/*dm_value[3] = PowerIndex*/ + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)) { + if (dm_value[1] <= 1) { + if ((u1Byte)dm_value[2] != 0xff) { + if (phydm_api_set_txagc(pDM_Odm, dm_value[3], (ODM_RF_RADIO_PATH_E) dm_value[1], (u1Byte)dm_value[2], TRUE)) + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[1], "rate index-0x", dm_value[2], " = 0x", dm_value[3])); + else + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); + } else { + u1Byte i; + u4Byte power_index; + BOOLEAN status = TRUE; + + power_index = (dm_value[3] & 0x3f); + + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { + power_index = (power_index << 24)|(power_index << 16)|(power_index << 8)|(power_index); + + for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) + status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); + } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { + for (i = 0; i <= ODM_RATEMCS15; i++) + status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); + } + + if (status) + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x\n", "Write all TXAGC of path-", dm_value[1], " = 0x", dm_value[3])); + else + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); + } + } else { + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); + } + } +#endif +} + +VOID +phydm_debug_trace( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte pre_debug_components, one = 1; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pre_debug_components = pDM_Odm->DebugComponents; + + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_DIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RA_MASK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->DebugComponents & ODM_COMP_FA_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->DebugComponents & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((pDM_Odm->DebugComponents & ODM_COMP_SNIFFER) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((pDM_Odm->DebugComponents & ODM_COMP_DFS) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((pDM_Odm->DebugComponents & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->DebugComponents & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_PATH_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "11. (( %s ))CCX\n", ((pDM_Odm->DebugComponents & ODM_COMP_CCX) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))LNA_SAT_CHK\n", ((pDM_Odm->DebugComponents & ODM_COMP_LNA_SAT_CHK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((pDM_Odm->DebugComponents & ODM_COMP_MP) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((pDM_Odm->DebugComponents & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((pDM_Odm->DebugComponents & ODM_COMP_ACS) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_TXBF) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->DebugComponents & ODM_COMP_EDCA_TURBO) ? ("V") : (".")))); + + PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))TDMA_DIG_CALL_BACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_DIG_CALL_BACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((pDM_Odm->DebugComponents & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "23. (( %s ))ADAPTIVE_SOML\n", ((pDM_Odm->DebugComponents & ODM_COMP_ADAPTIVE_SOML) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))TDMA_HDIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_HDIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((pDM_Odm->DebugComponents & ODM_COMP_CALIBRATION) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "27. (( %s ))TDMA_LDIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_TDMA_LDIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((pDM_Odm->DebugComponents & ODM_PHY_CONFIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((pDM_Odm->DebugComponents & ODM_COMP_INIT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((pDM_Odm->DebugComponents & ODM_COMP_COMMON) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((pDM_Odm->DebugComponents & ODM_COMP_API) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + + } else if (dm_value[0] == 101) { + pDM_Odm->DebugComponents = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); + } else { + if (dm_value[1] == 1) { /*enable*/ + pDM_Odm->DebugComponents |= (one << dm_value[0]); + } else if (dm_value[1] == 2) { /*disable*/ + pDM_Odm->DebugComponents &= ~(one << dm_value[0]); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", pre_debug_components)); + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", pDM_Odm->DebugComponents)); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); +} + +VOID +phydm_fw_debug_trace( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte pre_fw_debug_components, one = 1; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pre_fw_debug_components = pDM_Odm->fw_DebugComponents; + + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[FW Debug Component]")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))RA\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_RA) ? ("V") : (".")))); + + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES){ + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))MU\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_MU) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))Path Div\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))Phy Config\n", ((pDM_Odm->fw_DebugComponents & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); + } + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + + } else { + if (dm_value[0] == 101) { + pDM_Odm->fw_DebugComponents = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Clear all fw debug components")); + } else { + if (dm_value[1] == 1) { /*enable*/ + pDM_Odm->fw_DebugComponents |= (one << dm_value[0]); + } else if (dm_value[1] == 2) { /*disable*/ + pDM_Odm->fw_DebugComponents &= ~(one << dm_value[0]); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + + if (pDM_Odm->fw_DebugComponents == 0) { + pDM_Odm->DebugComponents &= ~ODM_FW_DEBUG_TRACE; + phydm_fw_trace_en_h2c(pDM_Odm, FALSE, pDM_Odm->fw_DebugComponents, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } else { + pDM_Odm->DebugComponents |= ODM_FW_DEBUG_TRACE; + phydm_fw_trace_en_h2c(pDM_Odm, TRUE, pDM_Odm->fw_DebugComponents, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } + } +} + +VOID +phydm_DumpBbReg( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Addr = 0; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + + /* BB Reg, For Nseries IC we only need to dump page8 to pageF using 3 digits*/ + for (Addr = 0x800; Addr < 0xfff; Addr += 4) { + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%03x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + else + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + } + + if (pDM_Odm->SupportICType & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { + + if (pDM_Odm->RFType > ODM_2T2R) { + for (Addr = 0x1800; Addr < 0x18ff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + } + + if (pDM_Odm->RFType > ODM_3T3R) { + for (Addr = 0x1a00; Addr < 0x1aff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + } + + for (Addr = 0x1900; Addr < 0x19ff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + + for (Addr = 0x1c00; Addr < 0x1cff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + + for (Addr = 0x1f00; Addr < 0x1fff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + } +} + +VOID +phydm_DumpAllReg( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Addr = 0; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + /* dump MAC register */ + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "MAC==========\n")); + for (Addr = 0; Addr < 0x7ff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + + for (Addr = 0x1000; Addr < 0x17ff; Addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + + /* dump BB register */ + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "BB==========\n")); + phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); + + /* dump RF register */ + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-A==========\n")); + for (Addr = 0; Addr < 0xFF; Addr++) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Addr, bRFRegOffsetMask))); + + if (pDM_Odm->RFType > ODM_1T1R) { + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-B==========\n")); + for (Addr = 0; Addr < 0xFF; Addr++) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Addr, bRFRegOffsetMask))); + } + + if (pDM_Odm->RFType > ODM_2T2R) { + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-C==========\n")); + for (Addr = 0; Addr < 0xFF; Addr++) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Addr, bRFRegOffsetMask))); + } + + if (pDM_Odm->RFType > ODM_3T3R) { + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-D==========\n")); + for (Addr = 0; Addr < 0xFF; Addr++) + PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Addr, bRFRegOffsetMask))); + } +} + +VOID +phydm_EnableBigJump( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN state + ) +{ +#if (RTL8822B_SUPPORT == 1) + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (state == FALSE) { + pDM_Odm->DM_DigTable.enableAdjustBigJump = FALSE; + ODM_SetBBReg(pDM_Odm, 0x8c8, 0xfe, ((pDM_DigTable->bigJumpStep3<<5)|(pDM_DigTable->bigJumpStep2<<3)|pDM_DigTable->bigJumpStep1)); + } else + pDM_Odm->DM_DigTable.enableAdjustBigJump = TRUE; +#endif +} + +#if (RTL8822B_SUPPORT == 1) + +VOID +phydm_showRxRate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx SU Rate Statistics=====\n")); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[3])); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[7])); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[9])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[13])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[17])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[19])); + + PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx MU Rate Statistics=====\n")); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[3])); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[7])); + PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[9])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[13])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[17])); + PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[19])); + +} + +#endif + + +struct _PHYDM_COMMAND { + char name[16]; + u1Byte id; +}; + +enum PHYDM_CMD_ID { + PHYDM_HELP, + PHYDM_DEMO, + PHYDM_RA, + PHYDM_PROFILE, + PHYDM_ANTDIV, + PHYDM_PATHDIV, + PHYDM_DEBUG, + PHYDM_FW_DEBUG, + PHYDM_SUPPORT_ABILITY, + PHYDM_GET_TXAGC, + PHYDM_SET_TXAGC, + PHYDM_SMART_ANT, + PHYDM_API, + PHYDM_TRX_PATH, + PHYDM_LA_MODE, + PHYDM_DUMP_REG, + PHYDM_MU_MIMO, + PHYDM_HANG, + PHYDM_BIG_JUMP, + PHYDM_SHOW_RXRATE, + PHYDM_NBI_EN, + PHYDM_CSI_MASK_EN, + PHYDM_ADAPTIVE_SOML, + PHYDM_DFS, + PHYDM_IQK, + PHYDM_NHM, + PHYDM_CLM, + PHYDM_BB_INFO, + PHYDM_TXBF, + PHYDM_PAUSE_DIG_EN, + PHYDM_H2C +}; + +struct _PHYDM_COMMAND phy_dm_ary[] = { + {"-h", PHYDM_HELP}, /*do not move this element to other position*/ + {"demo", PHYDM_DEMO}, /*do not move this element to other position*/ + {"ra", PHYDM_RA}, + {"profile", PHYDM_PROFILE}, + {"antdiv", PHYDM_ANTDIV}, + {"pathdiv", PHYDM_PATHDIV}, + {"dbg", PHYDM_DEBUG}, + {"fw_dbg", PHYDM_FW_DEBUG}, + {"ability", PHYDM_SUPPORT_ABILITY}, + {"get_txagc", PHYDM_GET_TXAGC}, + {"set_txagc", PHYDM_SET_TXAGC}, + {"smtant", PHYDM_SMART_ANT}, + {"api", PHYDM_API}, + {"trxpath", PHYDM_TRX_PATH}, + {"lamode", PHYDM_LA_MODE}, + {"dumpreg", PHYDM_DUMP_REG}, + {"mu", PHYDM_MU_MIMO}, + {"hang", PHYDM_HANG}, + {"bigjump", PHYDM_BIG_JUMP}, + {"rxrate", PHYDM_SHOW_RXRATE}, + {"nbi", PHYDM_NBI_EN}, + {"csi_mask", PHYDM_CSI_MASK_EN}, + {"soml", PHYDM_ADAPTIVE_SOML}, + {"dfs", PHYDM_DFS}, + {"iqk", PHYDM_IQK}, + {"nhm", PHYDM_NHM}, + {"clm", PHYDM_CLM}, + {"bbinfo", PHYDM_BB_INFO}, + {"txbf", PHYDM_TXBF}, + {"pause_dig", PHYDM_PAUSE_DIG_EN}, + {"h2c", PHYDM_H2C} +}; + +VOID +phydm_cmd_parser( + IN PDM_ODM_T pDM_Odm, + IN char input[][MAX_ARGV], + IN u4Byte input_num, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +) +{ + u4Byte used = 0; + u1Byte id = 0; + int var1[10] = {0}; + int i, input_idx = 0, phydm_ary_size; + char help[] = "-h"; + + if (flag == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); + return; + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + + //Parsing Cmd ID + if (input_num) { + + phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); + for (i = 0; i < phydm_ary_size; i++) { + if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { + id = phy_dm_ary[i].id; + break; + } + } + if (i == phydm_ary_size) { + PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); + return; + } + } + + switch (id) { + + case PHYDM_HELP: + { + PHYDM_SNPRINTF((output + used, out_len - used, "BB cmd ==>\n")); + for (i=0; i < phydm_ary_size-2; i++) { + + PHYDM_SNPRINTF((output + used, out_len - used, " %-5d: %s\n", i, phy_dm_ary[i+2].name)); + /**/ + } + } + break; + + case PHYDM_DEMO: /*echo demo 10 0x3a z abcde >cmd*/ + { + u4Byte directory = 0; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + char char_temp; + #else + u4Byte char_temp = ' '; + #endif + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); + PHYDM_SNPRINTF((output + used, out_len - used, "Decimal Value = %d\n", directory)); + PHYDM_SSCANF(input[2], DCMD_HEX, &directory); + PHYDM_SNPRINTF((output + used, out_len - used, "Hex Value = 0x%x\n", directory)); + PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); + PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); + PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); + } + break; + + case PHYDM_RA: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ + #if (defined(CONFIG_RA_DBG_CMD)) + odm_RA_debug((PVOID)pDM_Odm, (pu4Byte) var1); + #else + phydm_RA_debug_PCR(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + #endif + } + + + break; + + case PHYDM_ADAPTIVE_SOML: + +#if (CONFIG_ADAPTIVE_SOML) + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_soml_debug(pDM_Odm, (u32 *)var1, &used, output, &out_len); +#else + PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); +#endif + + break; + + case PHYDM_ANTDIV: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + phydm_antdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + #endif + } + + break; + + case PHYDM_PATHDIV: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ +#if (defined(CONFIG_PATH_DIVERSITY)) + odm_pathdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); +#endif + } + + break; + + case PHYDM_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ + phydm_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + } + + + break; + + case PHYDM_FW_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_fw_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + + break; + + case PHYDM_SUPPORT_ABILITY: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ + phydm_support_ability_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + } + + break; + + case PHYDM_SMART_ANT: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + phydm_hl_smart_ant_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + #endif + #endif + } + + break; + + case PHYDM_API: +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + { + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F | ODM_RTL8821C)) { + BOOLEAN bEnableDbgMode; + u1Byte central_ch, primary_ch_idx, bandwidth; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + bEnableDbgMode = (BOOLEAN)var1[0]; + central_ch = (u1Byte) var1[1]; + primary_ch_idx = (u1Byte) var1[2]; + bandwidth = (ODM_BW_E) var1[3]; + + if (bEnableDbgMode) { + pDM_Odm->bDisablePhyApi = FALSE; + phydm_api_switch_bw_channel(pDM_Odm, central_ch, primary_ch_idx, (ODM_BW_E) bandwidth); + pDM_Odm->bDisablePhyApi = TRUE; + PHYDM_SNPRINTF((output+used, out_len-used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); + } else { + pDM_Odm->bDisablePhyApi = FALSE; + PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + } + } else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); + } +#else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); +#endif + break; + + case PHYDM_PROFILE: /*echo profile, >cmd*/ + phydm_BasicProfile(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_GET_TXAGC: + phydm_get_txagc(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_SET_TXAGC: + { + BOOLEAN bEnableDbgMode; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + bEnableDbgMode = (BOOLEAN)var1[0]; + if (bEnableDbgMode) { + pDM_Odm->bDisablePhyApi = FALSE; + phydm_set_txagc(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + pDM_Odm->bDisablePhyApi = TRUE; + } else { + pDM_Odm->bDisablePhyApi = FALSE; + PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + } + } + break; + + case PHYDM_TRX_PATH: + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { + u1Byte TxPath, RxPath; + BOOLEAN bEnableDbgMode, bTx2Path; + + bEnableDbgMode = (BOOLEAN)var1[0]; + TxPath = (u1Byte) var1[1]; + RxPath = (u1Byte) var1[2]; + bTx2Path = (BOOLEAN) var1[3]; + + if (bEnableDbgMode) { + u1Byte bTmp = pDM_Odm->bDisablePhyApi; + pDM_Odm->bDisablePhyApi = FALSE; + phydm_api_trx_mode(pDM_Odm, (ODM_RF_PATH_E) TxPath, (ODM_RF_PATH_E) RxPath, bTx2Path); + if(bTmp) + pDM_Odm->bDisablePhyApi = bTmp; + PHYDM_SNPRINTF((output+used, out_len-used, "TxPath = 0x%x, RxPath = 0x%x, bTx2Path = %d\n", TxPath, RxPath, bTx2Path)); + } else { + pDM_Odm->bDisablePhyApi = FALSE; + PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + } + } else + #endif + phydm_config_trx_path(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + + break; + + case PHYDM_LA_MODE: + #if (PHYDM_LA_MODE_SUPPORT == 1) + pDM_Odm->SupportAbility &= ~(ODM_BB_FA_CNT); + phydm_lamode_trigger_setting(pDM_Odm, &input[0], &used, output, &out_len, input_num); + pDM_Odm->SupportAbility |= ODM_BB_FA_CNT; + #else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); + #endif + break; + + case PHYDM_DUMP_REG: + { + u1Byte type = 0; + + if (input[1]) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + type = (u1Byte)var1[0]; + } + + if (type == 0) + phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); + else if (type == 1) + phydm_DumpAllReg(pDM_Odm, &used, output, &out_len); + } + break; + + case PHYDM_MU_MIMO: +#if (RTL8822B_SUPPORT == 1) + + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + else + var1[0] = 0; + + if (var1[0] == 1) { + int index, ptr; + u4Byte Dword_H, Dword_L; + + PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFee CSI\n")); + ODM_SetBBReg(pDM_Odm, 0x9e8, BIT17|BIT16, 2); /*Read BFee*/ + ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 1); /*Select BFee's CSI report*/ + ODM_SetBBReg(pDM_Odm, 0x19b8, BIT6, 1); /*set as CSI report*/ + ODM_SetBBReg(pDM_Odm, 0x19a8, 0xFFFF, 0xFFFF); /*disable gated_clk*/ + + for (index = 0; index < 80; index++) { + ptr = index + 256; + if (ptr > 311) + ptr -= 312; + ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ + Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); + Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); + if (index % 2 == 0) + PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", + Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, + Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); + else + PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", + Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, + Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); + } + } else if (var1[0] == 2) { + int index, ptr; + u4Byte Dword_H, Dword_L; + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFer's STA%d CSI\n", var1[1])); + ODM_SetBBReg(pDM_Odm, 0x9e8, BIT24, 0); /*Read BFer*/ + ODM_SetBBReg(pDM_Odm, 0x9e8, BIT25, 1); /*enable Read/Write RAM*/ + ODM_SetBBReg(pDM_Odm, 0x9e8, BIT30|BIT29|BIT28, var1[1]); /*read which STA's CSI report*/ + ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 0); /*select BFer's CSI*/ + ODM_SetBBReg(pDM_Odm, 0x19e0, 0x00003FC0, 0xFF); /*disable gated_clk*/ + + for (index = 0; index < 80; index++) { + ptr = index + 256; + if (ptr > 311) + ptr -= 312; + ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ + Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); + Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); + if (index % 2 == 0) + PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", + Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, + Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); + else + PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", + Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, + Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); + + PHYDM_SNPRINTF((output+used, out_len-used, "ptr=%d : 0x%8x %8x\n", ptr, Dword_H, Dword_L)); + } + + } +#endif + break; + + case PHYDM_BIG_JUMP: + { +#if (RTL8822B_SUPPORT == 1) + if (input[1]) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + phydm_EnableBigJump(pDM_Odm, (BOOLEAN)(var1[0])); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); +#else + PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); +#endif + break; + } + + case PHYDM_HANG: + phydm_BB_RxHang_Info(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_SHOW_RXRATE: +#if (RTL8822B_SUPPORT == 1) + { + u1Byte rate_idx; + + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) + phydm_showRxRate(pDM_Odm, &used, output, &out_len); + else { + PHYDM_SNPRINTF((output+used, out_len-used, "Reset Rx rate counter\n")); + + for (rate_idx = 0; rate_idx < 40; rate_idx++) { + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[rate_idx] = 0; + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[rate_idx] = 0; + } + } + } +#endif + break; + + case PHYDM_NBI_EN: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + + phydm_api_debug(pDM_Odm, PHYDM_API_NBI, (u4Byte *)var1, &used, output, &out_len); + /**/ + } + + + break; + + case PHYDM_CSI_MASK_EN: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + + phydm_api_debug(pDM_Odm, PHYDM_API_CSI_MASK, (u4Byte *)var1, &used, output, &out_len); + /**/ + } + + + break; + + case PHYDM_DFS: +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + { + u4Byte var[6] = {0}; + + for (i = 0; i < 6; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_dfs_debug(pDM_Odm, var, &used, output, &out_len); + } +#endif + break; + + case PHYDM_IQK: +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate(pDM_Odm->priv); + PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHY_IQCalibrate(pDM_Odm->Adapter, FALSE); + PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); +#endif + break; + + case PHYDM_NHM: + { + u1Byte target_rssi; + u4Byte value32; + u2Byte nhm_period = 0xC350; //200ms + u1Byte IGI; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if(input_num == 1) { + + CCX_INFO->echo_NHM_en = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); + + return; + } + + /* NMH trigger */ + if ((var1[0] <= 2) && (var1[0] != 0)) { + + CCX_INFO->echo_NHM_en = TRUE; + CCX_INFO->echo_IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + + target_rssi = CCX_INFO->echo_IGI - 10; + + CCX_INFO->NHM_th[0] = (target_rssi -15 + 10) * 2; + + for(i = 1; i <= 10; i ++) { + CCX_INFO->NHM_th[i] = CCX_INFO->NHM_th[0] + 6 * i; + } + + //4 1. store previous NHM setting + phydm_NHMsetting(pDM_Odm, STORE_NHM_SETTING); + + //4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms + CCX_INFO->NHM_period = nhm_period; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period*4)); + + //4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en + + + CCX_INFO->NHM_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; + CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; + + phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); + + for(i = 0; i <= 10; i ++) { + + if (i == 5) { + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, CCX_INFO->NHM_th[i], CCX_INFO->echo_IGI)); + } + else if (i == 10) + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, CCX_INFO->NHM_th[i])); + else + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, CCX_INFO->NHM_th[i])); + } + + //4 4. Trigger NHM + phydm_NHMtrigger(pDM_Odm); + + } + + /*Get NHM results*/ + else if (var1[0] == 3) { + + IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); + + phydm_getNHMresult(pDM_Odm); + + //4 Resotre NHM setting + phydm_NHMsetting(pDM_Odm, RESTORE_NHM_SETTING); + + for(i = 0; i <= 11; i++) { + + if (i == 5) + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, CCX_INFO->NHM_result[i], CCX_INFO->echo_IGI)); + else if (i == 11) + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, CCX_INFO->NHM_result[i])); + else + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, CCX_INFO->NHM_result[i])); + } + + CCX_INFO->echo_NHM_en = FALSE; + } + else { + + CCX_INFO->echo_NHM_en = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); + + return; + } + } + break; + + case PHYDM_CLM: + { + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + //PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); + + if (input_num == 1) { + + CCX_INFO->echo_CLM_en = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger CLM: echo clm 1\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); + return; + } + + /* Set & trigger CLM */ + if (var1[0] == 1) { + + CCX_INFO->echo_CLM_en = TRUE; + CCX_INFO->CLM_period = 0xC350; /*100ms*/ + phydm_CLMsetting(pDM_Odm); + phydm_CLMtrigger(pDM_Odm); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor CLM for 200ms\n")); + } + + /* Get CLM results */ + else if (var1[0] == 2) { + + CCX_INFO->echo_CLM_en = FALSE; + phydm_getCLMresult(pDM_Odm); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", CCX_INFO->CLM_result*4)); + + } else { + + CCX_INFO->echo_CLM_en = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "\n\r Error command !\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger CLM: echo clm 1\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); + } + } + break; + + case PHYDM_BB_INFO: + { + s4Byte value32 = 0; + + phydm_BB_Debug_Info(pDM_Odm, &used, output, &out_len); + + if (pDM_Odm->SupportICType & ODM_RTL8822B && input[1]) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + ODM_SetBBReg(pDM_Odm, 0x1988, 0x003fff00, var1[0]); + value32 = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); + value32 = (value32 & 0xff000000)>>24; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = condition num = %d, subcarriers = %d\n", "Over condition num subcarrier", var1[0], value32)); + ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x0); /*disable report condition number*/ + } + } + break; + + case PHYDM_TXBF: + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + if (var1[0] == 1) { + pBeamformingInfo->applyVmatrix = TRUE; + pBeamformingInfo->snding3SS = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 dont snding\n")); + } else if (var1[0] == 0) { + pBeamformingInfo->applyVmatrix = FALSE; + pBeamformingInfo->snding3SS = TRUE; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n dont apply V matrix and 3SS 789 snding\n")); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n")); +#else + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n no TxBF !!\n")); +#endif +#endif + } + break; + + case PHYDM_PAUSE_DIG_EN: + + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + if (var1[0] == 0) { + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, (u1Byte)var1[1]); + PHYDM_SNPRINTF((output + used, out_len - used, "Set IGI_value = ((%x))\n", var1[1])); + } else if (var1[0] == 1) { + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, (u1Byte)var1[1]); + PHYDM_SNPRINTF((output + used, out_len - used, "Resume IGI_value\n")); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "echo (1:pause, 2resume) (IGI_value)\n")); + } + + break; + + case PHYDM_H2C: + + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_h2C_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + + + break; + + default: + PHYDM_SNPRINTF((output + used, out_len - used, "SET, unknown command!\n")); + break; + + } +} + +#ifdef __ECOS +char *strsep(char **s, const char *ct) +{ + char *sbegin = *s; + char *end; + + if (sbegin == NULL) + return NULL; + + end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + return sbegin; +} +#endif + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) +s4Byte +phydm_cmd( + IN PDM_ODM_T pDM_Odm, + IN char *input, + IN u4Byte in_len, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +) +{ + char *token; + u4Byte Argc = 0; + char Argv[MAX_ARGC][MAX_ARGV]; + + do { + token = strsep(&input, ", "); + if (token) { + strcpy(Argv[Argc], token); + Argc++; + } else + break; + } while (Argc < MAX_ARGC); + + if (Argc == 1) + Argv[0][strlen(Argv[0]) - 1] = '\0'; + + phydm_cmd_parser(pDM_Odm, Argv, Argc, flag, output, out_len); + + return 0; +} +#endif + + +VOID +phydm_fw_trace_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*u1Byte debug_trace_11byte[60];*/ + u1Byte freg_num, c2h_seq, buf_0 = 0; + + if (!(pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)) + return; + + if (CmdLen > 12) + return; + + buf_0 = CmdBuf[0]; + freg_num = (buf_0 & 0xf); + c2h_seq = (buf_0 & 0xf0) >> 4; + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ + + /*strncpy(debug_trace_11byte,&CmdBuf[1],(CmdLen-1));*/ + /*debug_trace_11byte[CmdLen-1] = '\0';*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] CmdLen = (( %d ))\n", CmdLen));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", pDM_Odm->c2h_cmd_start));*/ + + + + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", pDM_Odm->pre_c2h_seq, c2h_seq));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", pDM_Odm->fw_buff_is_enpty));*/ + + if ((c2h_seq != pDM_Odm->pre_c2h_seq) && pDM_Odm->fw_buff_is_enpty == FALSE) { + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", pDM_Odm->fw_debug_trace)); + pDM_Odm->c2h_cmd_start = 0; + } + + if ((CmdLen - 1) > (60 - pDM_Odm->c2h_cmd_start)) { + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", pDM_Odm->fw_debug_trace)); + pDM_Odm->c2h_cmd_start = 0; + return; + } + + strncpy((char *)&(pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start]), (char *)&CmdBuf[1], (CmdLen-1)); + pDM_Odm->c2h_cmd_start += (CmdLen - 1); + pDM_Odm->fw_buff_is_enpty = FALSE; + + if (freg_num == 0 || pDM_Odm->c2h_cmd_start >= 60) { + if (pDM_Odm->c2h_cmd_start < 60) + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + else + pDM_Odm->fw_debug_trace[59] = '\0'; + + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace)); + /*DbgPrint("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace);*/ + pDM_Odm->c2h_cmd_start = 0; + pDM_Odm->fw_buff_is_enpty = TRUE; + } + + pDM_Odm->pre_c2h_seq = c2h_seq; +} + +VOID +phydm_fw_trace_handler_code( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte function = Buffer[0]; + u1Byte dbg_num = Buffer[1]; + u2Byte content_0 = (((u2Byte)Buffer[3])<<8)|((u2Byte)Buffer[2]); + u2Byte content_1 = (((u2Byte)Buffer[5])<<8)|((u2Byte)Buffer[4]); + u2Byte content_2 = (((u2Byte)Buffer[7])<<8)|((u2Byte)Buffer[6]); + u2Byte content_3 = (((u2Byte)Buffer[9])<<8)|((u2Byte)Buffer[8]); + u2Byte content_4 = (((u2Byte)Buffer[11])<<8)|((u2Byte)Buffer[10]); + + if(CmdLen >12) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Invalid cmd length (( %d )) >12 \n", CmdLen)); + } + + //ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", + // function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + + /*--------------------------------------------*/ +#if (CONFIG_RA_FW_DBG_CODE) + if(function == RATE_DECISION) { + if(dbg_num == 0) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); + } else if(content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); + } + } else if(dbg_num == 1) { + if (content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); + } else if (content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); + phydm_print_rate(pDM_Odm, (u1Byte)content_4, ODM_FW_DEBUG_TRACE); + } else if (content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); + } else if (content_0 == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); + } + } + + else if(dbg_num == 3) { + if (content_0 == 1) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 2) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 3) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((Rate Down Hold)) RA_CNT=((%d))\n", content_1)); + else if (content_0 == 4) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); + else if (content_0 == 8) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); + } + + else if (dbg_num == 4) { + if (content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); + /**/ + } else if (content_0 == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); + /**/ + } else if (content_0 == 5) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); + /**/ + } + } + + else if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); + } else if(content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); + } + } + else if(dbg_num == 0x60) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); + } else if(content_0 == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 5) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); + } + } + } + /*--------------------------------------------*/ + else if (function == INIT_RA_TABLE){ + if(dbg_num == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); + } + + } + /*--------------------------------------------*/ + else if (function == RATE_UP) { + if(dbg_num == 2) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate -> return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); + } + } else if(dbg_num == 5) { + if (content_0 == 0) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 1) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); + } + + } + /*--------------------------------------------*/ + else if (function == RATE_DOWN) { + if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((Rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); + } + } + } else if (function == TRY_DONE) { + if (dbg_num == 1) { + if (content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); + /**/ + } + } else if (dbg_num == 2) { + if (content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); + /**/ + } + } + } + /*--------------------------------------------*/ + else if (function == RA_H2C) { + if (dbg_num == 1) { + if (content_0 == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); + /**/ + /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid , 0); //RA MASK*/ + } + #if 0 + else if (dbg_num == 2) { + + if (content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), Rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); + /**/ + } else if (content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); + /**/ + } else if (content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); + /**/ + } + } + #endif + } + } + /*--------------------------------------------*/ + else if (function == F_RATE_AP_RPT) { + if(dbg_num == 1) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); + } + } else if(dbg_num == 2) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); + } + } else if(dbg_num == 3) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 4) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 6) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + } + } + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + /**/ + } +#else + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); +#endif + /*--------------------------------------------*/ + + +} + +VOID +phydm_fw_trace_handler_8051( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if 0 + if (CmdLen >= 3) + CmdBuf[CmdLen - 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(CmdBuf[3]))); +#else + + int i = 0; + u1Byte Extend_c2hSubID = 0, Extend_c2hDbgLen = 0, Extend_c2hDbgSeq = 0; + u1Byte fw_debug_trace[128]; + pu1Byte Extend_c2hDbgContent = 0; + + if (CmdLen > 127) + return; + + Extend_c2hSubID = Buffer[0]; + Extend_c2hDbgLen = Buffer[1]; + Extend_c2hDbgContent = Buffer + 2; /*DbgSeq+DbgContent for show HEX*/ + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, Extend_c2hDbgLen=%d\n", + Extend_c2hSubID, Extend_c2hDbgLen)); + + RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", Extend_c2hDbgContent, CmdLen-2); + #endif + +GoBackforAggreDbgPkt: + i = 0; + Extend_c2hDbgSeq = Buffer[2]; + Extend_c2hDbgContent = Buffer + 3; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", Extend_c2hDbgSeq)); + #endif + + for (; ; i++) { + fw_debug_trace[i] = Extend_c2hDbgContent[i]; + if (Extend_c2hDbgContent[i + 1] == '\0') { + fw_debug_trace[i + 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + break; + } else if (Extend_c2hDbgContent[i] == '\n') { + fw_debug_trace[i + 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + Buffer = Extend_c2hDbgContent + i + 3; + goto GoBackforAggreDbgPkt; + } + } + + +#endif +} + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_debug.h b/package/kernel/rtl8192cd/phydm/phydm_debug.h index d0ce2a574cc..d258c73119d 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_debug.h +++ b/package/kernel/rtl8192cd/phydm/phydm_debug.h @@ -1,354 +1,354 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __ODM_DBG_H__ -#define __ODM_DBG_H__ - -/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ -/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ -#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ -//----------------------------------------------------------------------------- -// Define the debug levels -// -// 1. DBG_TRACE and DBG_LOUD are used for normal cases. -// So that, they can help SW engineer to develope or trace states changed -// and also help HW enginner to trace every operation to and from HW, -// e.g IO, Tx, Rx. -// -// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, -// which help us to debug SW or HW. -// -//----------------------------------------------------------------------------- -// -// Never used in a call to ODM_RT_TRACE()! -// -#define ODM_DBG_OFF 1 - -// -// Fatal bug. -// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, -// resource allocation failed, unexpected HW behavior, HW BUG and so on. -// -#define ODM_DBG_SERIOUS 2 - -// -// Abnormal, rare, or unexpeted cases. -// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. -// -#define ODM_DBG_WARNING 3 - -// -// Normal case with useful information about current SW or HW state. -// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, -// SW protocol state change, dynamic mechanism state change and so on. -// -#define ODM_DBG_LOUD 4 - -// -// Normal case with detail execution flow or information. -// -#define ODM_DBG_TRACE 5 - -/*FW DBG MSG*/ -#define RATE_DECISION BIT0 -#define INIT_RA_TABLE BIT1 -#define RATE_UP BIT2 -#define RATE_DOWN BIT3 -#define TRY_DONE BIT4 -#define RA_H2C BIT5 -#define F_RATE_AP_RPT BIT7 - -//----------------------------------------------------------------------------- -// Define the tracing components -// -//----------------------------------------------------------------------------- -/*BB FW Functions*/ -#define PHYDM_FW_COMP_RA BIT0 -#define PHYDM_FW_COMP_MU BIT1 -#define PHYDM_FW_COMP_PATH_DIV BIT2 -#define PHYDM_FW_COMP_PHY_CONFIG BIT3 - - -/*BB Driver Functions*/ -#define ODM_COMP_DIG BIT0 -#define ODM_COMP_RA_MASK BIT1 -#define ODM_COMP_DYNAMIC_TXPWR BIT2 -#define ODM_COMP_FA_CNT BIT3 -#define ODM_COMP_RSSI_MONITOR BIT4 -#define ODM_COMP_SNIFFER BIT5 -#define ODM_COMP_ANT_DIV BIT6 -#define ODM_COMP_DFS BIT7 -#define ODM_COMP_NOISY_DETECT BIT8 -#define ODM_COMP_RATE_ADAPTIVE BIT9 -#define ODM_COMP_PATH_DIV BIT10 -#define ODM_COMP_CCX BIT11 -#define ODM_COMP_DYNAMIC_ANT_WEIGHTING BIT10 -#define ODM_COMP_DYNAMIC_PRICCA BIT12 -#define ODM_COMP_LNA_SAT_CHK BIT13 /*BIT13 TBD*/ -#define ODM_COMP_MP BIT14 -#define ODM_COMP_CFO_TRACKING BIT15 -#define ODM_COMP_ACS BIT16 -#define PHYDM_COMP_ADAPTIVITY BIT17 -#define PHYDM_COMP_RA_DBG BIT18 -#define PHYDM_COMP_TXBF BIT19 -//MAC Functions -#define ODM_COMP_EDCA_TURBO BIT20 -#define ODM_COMP_TDMA_DIG_CALL_BACK BIT21 -#define ODM_FW_DEBUG_TRACE BIT22 - -//RF Functions - -#define ODM_COMP_ADAPTIVE_SOML BIT23 -#define ODM_COMP_TX_PWR_TRACK BIT24 -#define ODM_COMP_TDMA_HDIG BIT25 -#define ODM_COMP_CALIBRATION BIT26 -#define ODM_COMP_TDMA_LDIG BIT27 -//Common Functions - /*BIT27 TBD*/ -#define ODM_PHY_CONFIG BIT28 -#define ODM_COMP_INIT BIT29 -#define ODM_COMP_COMMON BIT30 -#define ODM_COMP_API BIT31 - - -/*------------------------Export Marco Definition---------------------------*/ - -#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define RT_PRINTK DbgPrint -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define DbgPrint printk - #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); - #define RT_DISP(dbgtype, dbgflag, printstr) -#else - #define DbgPrint panic_printk - #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); -#endif - -#ifndef ASSERT - #define ASSERT(expr) -#endif - -#if DBG -#define PHYDM_DBG(dm, comp, fmt, args...) \ - do { \ - if ((comp) & dm->DebugComponents) { \ - DbgPrint("[PHYDM] "); \ - RT_PRINTK(fmt, ## args); \ - } \ - } while (0) - -#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ - do { \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \ - { \ - if (pDM_Odm->SupportICType == ODM_RTL8188E) \ - DbgPrint("[PhyDM-8188E] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8192E) \ - DbgPrint("[PhyDM-8192E] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8812) \ - DbgPrint("[PhyDM-8812A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8821) \ - DbgPrint("[PhyDM-8821A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8814A) \ - DbgPrint("[PhyDM-8814A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8703B) \ - DbgPrint("[PhyDM-8703B] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8822B) \ - DbgPrint("[PhyDM-8822B] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8188F) \ - DbgPrint("[PhyDM-8188F] "); \ - RT_PRINTK fmt; \ - } \ - } while (0) - -#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - RT_PRINTK fmt; \ - } - -#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ - if(!(expr)) { \ - DbgPrint( "Assertion failed! %s at ......\n", #expr); \ - DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ - RT_PRINTK fmt; \ - ASSERT(FALSE); \ - } -#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } -#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } -#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } - -#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - int __i; \ - pu1Byte __ptr = (pu1Byte)ptr; \ - DbgPrint("[ODM] "); \ - DbgPrint(title_str); \ - DbgPrint(" "); \ - for( __i=0; __i<6; __i++ ) \ - DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ - DbgPrint("\n"); \ - } -#else -#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) -#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) -#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) -#define ODM_dbg_enter() -#define ODM_dbg_exit() -#define ODM_dbg_trace(str) -#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) -#endif - - -VOID -PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm); - -VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define PHYDM_DBGPRINT 0 -#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z) -#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF -#if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - DbgPrint(output);\ - } while (0) -#else -#define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - DCMD_Printf(output);\ - } while (0) -#endif -#else -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) -#define PHYDM_DBGPRINT 0 -#else -#define PHYDM_DBGPRINT 1 -#endif -#define MAX_ARGC 20 -#define MAX_ARGV 16 -#define DCMD_DECIMAL "%d" -#define DCMD_CHAR "%c" -#define DCMD_HEX "%x" - -#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) - -#define PHYDM_VAST_INFO_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - DbgPrint(output);\ - } while (0) - -#if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - DbgPrint(output);\ - } while (0) -#else -#define PHYDM_SNPRINTF(msg)\ - do {\ - if(out_len > used)\ - used+=snprintf msg;\ - } while (0) -#endif -#endif - - -VOID phydm_BasicProfile( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) -s4Byte -phydm_cmd( - IN PDM_ODM_T pDM_Odm, - IN char *input, - IN u4Byte in_len, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len -); -#endif -VOID -phydm_cmd_parser( - IN PDM_ODM_T pDM_Odm, - IN char input[][16], - IN u4Byte input_num, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void phydm_sbd_check( - IN PDM_ODM_T pDM_Odm - ); - -void phydm_sbd_callback( - PRT_TIMER pTimer - ); - -void phydm_sbd_workitem_callback( - IN PVOID pContext - ); -#endif - -VOID -phydm_fw_trace_en_h2c( - IN PVOID pDM_VOID, - IN BOOLEAN enable, - IN u4Byte fw_debug_component, - IN u4Byte monitor_mode, - IN u4Byte macid -); - -VOID -phydm_fw_trace_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -); - -VOID -phydm_fw_trace_handler_code( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen -); - -VOID -phydm_fw_trace_handler_8051( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -); - -#endif // __ODM_DBG_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + +/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ +/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ +#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE()! +// +#define ODM_DBG_OFF 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define ODM_DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define ODM_DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define ODM_DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define ODM_DBG_TRACE 5 + +/*FW DBG MSG*/ +#define RATE_DECISION BIT0 +#define INIT_RA_TABLE BIT1 +#define RATE_UP BIT2 +#define RATE_DOWN BIT3 +#define TRY_DONE BIT4 +#define RA_H2C BIT5 +#define F_RATE_AP_RPT BIT7 + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +/*BB FW Functions*/ +#define PHYDM_FW_COMP_RA BIT0 +#define PHYDM_FW_COMP_MU BIT1 +#define PHYDM_FW_COMP_PATH_DIV BIT2 +#define PHYDM_FW_COMP_PHY_CONFIG BIT3 + + +/*BB Driver Functions*/ +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_SNIFFER BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_DFS BIT7 +#define ODM_COMP_NOISY_DETECT BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_CCX BIT11 +#define ODM_COMP_DYNAMIC_ANT_WEIGHTING BIT10 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_LNA_SAT_CHK BIT13 /*BIT13 TBD*/ +#define ODM_COMP_MP BIT14 +#define ODM_COMP_CFO_TRACKING BIT15 +#define ODM_COMP_ACS BIT16 +#define PHYDM_COMP_ADAPTIVITY BIT17 +#define PHYDM_COMP_RA_DBG BIT18 +#define PHYDM_COMP_TXBF BIT19 +//MAC Functions +#define ODM_COMP_EDCA_TURBO BIT20 +#define ODM_COMP_TDMA_DIG_CALL_BACK BIT21 +#define ODM_FW_DEBUG_TRACE BIT22 + +//RF Functions + +#define ODM_COMP_ADAPTIVE_SOML BIT23 +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_TDMA_HDIG BIT25 +#define ODM_COMP_CALIBRATION BIT26 +#define ODM_COMP_TDMA_LDIG BIT27 +//Common Functions + /*BIT27 TBD*/ +#define ODM_PHY_CONFIG BIT28 +#define ODM_COMP_INIT BIT29 +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_API BIT31 + + +/*------------------------Export Marco Definition---------------------------*/ + +#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define RT_PRINTK DbgPrint +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define DbgPrint printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define RT_DISP(dbgtype, dbgflag, printstr) +#else + #define DbgPrint panic_printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->DebugComponents) { \ + DbgPrint("[PHYDM] "); \ + RT_PRINTK(fmt, ## args); \ + } \ + } while (0) + +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + do { \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \ + { \ + if (pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[PhyDM-8188E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192E) \ + DbgPrint("[PhyDM-8192E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[PhyDM-8812A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[PhyDM-8821A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8814A) \ + DbgPrint("[PhyDM-8814A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8703B) \ + DbgPrint("[PhyDM-8703B] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8822B) \ + DbgPrint("[PhyDM-8822B] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8188F) \ + DbgPrint("[PhyDM-8188F] "); \ + RT_PRINTK fmt; \ + } \ + } while (0) + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if(!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + RT_PRINTK fmt; \ + ASSERT(FALSE); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + int __i; \ + pu1Byte __ptr = (pu1Byte)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + } +#else +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_dbg_enter() +#define ODM_dbg_exit() +#define ODM_dbg_trace(str) +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#endif + + +VOID +PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm); + +VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define PHYDM_DBGPRINT 0 +#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z) +#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DCMD_Printf(output);\ + } while (0) +#endif +#else +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) +#define PHYDM_DBGPRINT 0 +#else +#define PHYDM_DBGPRINT 1 +#endif +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" + +#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) + +#define PHYDM_VAST_INFO_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + DbgPrint(output);\ + } while (0) + +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg)\ + do {\ + if(out_len > used)\ + used+=snprintf msg;\ + } while (0) +#endif +#endif + + +VOID phydm_BasicProfile( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) +s4Byte +phydm_cmd( + IN PDM_ODM_T pDM_Odm, + IN char *input, + IN u4Byte in_len, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); +#endif +VOID +phydm_cmd_parser( + IN PDM_ODM_T pDM_Odm, + IN char input[][16], + IN u4Byte input_num, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_sbd_check( + IN PDM_ODM_T pDM_Odm + ); + +void phydm_sbd_callback( + PRT_TIMER pTimer + ); + +void phydm_sbd_workitem_callback( + IN PVOID pContext + ); +#endif + +VOID +phydm_fw_trace_en_h2c( + IN PVOID pDM_VOID, + IN BOOLEAN enable, + IN u4Byte fw_debug_component, + IN u4Byte monitor_mode, + IN u4Byte macid +); + +VOID +phydm_fw_trace_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_code( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_8051( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +#endif // __ODM_DBG_H__ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_dfs.c b/package/kernel/rtl8192cd/phydm/phydm_dfs.c index 12f7e6fdd2a..b6482311b6a 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dfs.c +++ b/package/kernel/rtl8192cd/phydm/phydm_dfs.c @@ -1,46 +1,46 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/* -============================================================ - include files -============================================================ -*/ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if defined(CONFIG_PHYDM_DFS_MASTER) -VOID phydm_radar_detect_reset(PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1); +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* +============================================================ + include files +============================================================ +*/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if defined(CONFIG_PHYDM_DFS_MASTER) +VOID phydm_radar_detect_reset(PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1); } -VOID phydm_radar_detect_disable(PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); +VOID phydm_radar_detect_disable(PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); } static VOID phydm_radar_detect_with_dbg_parm(PVOID pDM_VOID) @@ -53,20 +53,20 @@ static VOID phydm_radar_detect_with_dbg_parm(PVOID pDM_VOID) ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, pDM_Odm->radar_detect_reg_924); } -/* Init radar detection parameters, called after ch, bw is set */ -VOID phydm_radar_detect_enable(PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +/* Init radar detection parameters, called after ch, bw is set */ +VOID phydm_radar_detect_enable(PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; u1Byte region_domain = pDM_Odm->DFS_RegionDomain; u1Byte c_channel = *(pDM_Odm->pChannel); if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); return; } - if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { - + if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10); ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06); @@ -97,7 +97,7 @@ VOID phydm_radar_detect_enable(PVOID pDM_VOID) } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf); + ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf); ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500); ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231); if (pDM_Odm->pBandWidth == ODM_BW20M) @@ -106,16 +106,16 @@ VOID phydm_radar_detect_enable(PVOID pDM_VOID) ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20); } else { /* not supported */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); } - } else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) { - + } else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) { + ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10); ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06); - /* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { + /* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */ + if (pDM_Odm->SupportICType & ODM_RTL8822B) { if (pDM_Odm->pBandWidth == ODM_BW20M) ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 1); else @@ -157,48 +157,48 @@ VOID phydm_radar_detect_enable(PVOID pDM_VOID) ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20); } else { /* not supported */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); } } else { /* not supported IC type*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC Type:%d\n", pDM_Odm->SupportICType)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC Type:%d\n", pDM_Odm->SupportICType)); } exit: - phydm_radar_detect_reset(pDM_Odm); + phydm_radar_detect_reset(pDM_Odm); } -BOOLEAN phydm_radar_detect(PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +BOOLEAN phydm_radar_detect(PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; BOOLEAN enable_DFS = FALSE; - BOOLEAN radar_detected = FALSE; + BOOLEAN radar_detected = FALSE; u1Byte region_domain = pDM_Odm->DFS_RegionDomain; - + if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); return FALSE; } - - if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15)) - enable_DFS = TRUE; - if ((ODM_GetBBReg(pDM_Odm , 0xf98, BIT17)) - || (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (ODM_GetBBReg(pDM_Odm , 0xf98, BIT19)))) - radar_detected = TRUE; + if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15)) + enable_DFS = TRUE; + + if ((ODM_GetBBReg(pDM_Odm , 0xf98, BIT17)) + || (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (ODM_GetBBReg(pDM_Odm , 0xf98, BIT19)))) + radar_detected = TRUE; if (enable_DFS && radar_detected) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD , ("Radar detect: enable_DFS:%d, radar_detected:%d\n" , enable_DFS, radar_detected)); - - phydm_radar_detect_reset(pDM_Odm); + + phydm_radar_detect_reset(pDM_Odm); } exit: return (enable_DFS && radar_detected); -} -#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ +} +#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ BOOLEAN phydm_dfs_master_enabled( diff --git a/package/kernel/rtl8192cd/phydm/phydm_dfs.h b/package/kernel/rtl8192cd/phydm/phydm_dfs.h index bc55a439088..9a625bbcd1e 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dfs.h +++ b/package/kernel/rtl8192cd/phydm/phydm_dfs.h @@ -1,76 +1,76 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDM_DFS_H__ -#define __PHYDM_DFS_H__ - -#define DFS_VERSION "0.0" - -/* ============================================================ - Definition - ============================================================ -*/ - -/* -============================================================ -1 structure - ============================================================ -*/ - -/* ============================================================ - enumeration - ============================================================ -*/ - -typedef enum _tag_PhyDM_DFS_REGION_DOMAIN { - PHYDM_DFS_DOMAIN_UNKNOWN = 0, - PHYDM_DFS_DOMAIN_FCC = 1, - PHYDM_DFS_DOMAIN_MKK = 2, - PHYDM_DFS_DOMAIN_ETSI = 3, -} PHYDM_DFS_REGION_DOMAIN; - -/* -============================================================ - function prototype -============================================================ -*/ -#if defined(CONFIG_PHYDM_DFS_MASTER) -VOID phydm_radar_detect_reset(PVOID pDM_VOID); -VOID phydm_radar_detect_disable(PVOID pDM_VOID); -VOID phydm_radar_detect_enable(PVOID pDM_VOID); -BOOLEAN phydm_radar_detect(PVOID pDM_VOID); -#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ - -BOOLEAN -phydm_dfs_master_enabled( - IN PVOID pDM_VOID - ); - -VOID -phydm_dfs_debug( - IN PVOID pDM_VOID, - IN u4Byte *const argv, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - -#endif /*#ifndef __PHYDM_DFS_H__ */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_DFS_H__ +#define __PHYDM_DFS_H__ + +#define DFS_VERSION "0.0" + +/* ============================================================ + Definition + ============================================================ +*/ + +/* +============================================================ +1 structure + ============================================================ +*/ + +/* ============================================================ + enumeration + ============================================================ +*/ + +typedef enum _tag_PhyDM_DFS_REGION_DOMAIN { + PHYDM_DFS_DOMAIN_UNKNOWN = 0, + PHYDM_DFS_DOMAIN_FCC = 1, + PHYDM_DFS_DOMAIN_MKK = 2, + PHYDM_DFS_DOMAIN_ETSI = 3, +} PHYDM_DFS_REGION_DOMAIN; + +/* +============================================================ + function prototype +============================================================ +*/ +#if defined(CONFIG_PHYDM_DFS_MASTER) +VOID phydm_radar_detect_reset(PVOID pDM_VOID); +VOID phydm_radar_detect_disable(PVOID pDM_VOID); +VOID phydm_radar_detect_enable(PVOID pDM_VOID); +BOOLEAN phydm_radar_detect(PVOID pDM_VOID); +#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ + +BOOLEAN +phydm_dfs_master_enabled( + IN PVOID pDM_VOID + ); + +VOID +phydm_dfs_debug( + IN PVOID pDM_VOID, + IN u4Byte *const argv, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + +#endif /*#ifndef __PHYDM_DFS_H__ */ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_dig.c b/package/kernel/rtl8192cd/phydm/phydm_dig.c index 2609874ef7e..e707565bd15 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dig.c +++ b/package/kernel/rtl8192cd/phydm/phydm_dig.c @@ -1,4519 +1,4519 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#ifdef CFG_DIG_DAMPING_CHK -void phydm_dig_recorder_reset(void *dm_void) -{ - PDM_ODM_T dm = (PDM_ODM_T)dm_void; - pDIG_T dig_t = &dm->DM_DigTable; - struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; - - PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); - - ODM_Memory_Set(dm, &dig_rc->igi_bitmap, 0, - sizeof(struct phydm_dig_recoder_strcut)); -} - -void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr, u32 fa_cnt) -{ - PDM_ODM_T dm = (PDM_ODM_T)dm_void; - pDIG_T dig_t = &dm->DM_DigTable; - struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; - u8 igi_pre = dig_rc->igi_history[0]; - u8 igi_up = 0; - - if (!dm->bLinked) - return; - - PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); - - if (first_connect) { - phydm_dig_recorder_reset(dm); - dig_rc->igi_history[0] = igi_curr; - dig_rc->fa_history[0] = fa_cnt; - return; - } - - igi_pre = dig_rc->igi_history[0]; - igi_up = (igi_curr > igi_pre) ? 1 : 0; - dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up; - - dig_rc->igi_history[3] = dig_rc->igi_history[2]; - dig_rc->igi_history[2] = dig_rc->igi_history[1]; - dig_rc->igi_history[1] = dig_rc->igi_history[0]; - dig_rc->igi_history[0] = igi_curr; - - dig_rc->fa_history[3] = dig_rc->fa_history[2]; - dig_rc->fa_history[2] = dig_rc->fa_history[1]; - dig_rc->fa_history[1] = dig_rc->fa_history[0]; - dig_rc->fa_history[0] = fa_cnt; - - PHYDM_DBG(dm, ODM_COMP_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n", - dig_rc->igi_history[3], dig_rc->igi_history[2], - dig_rc->igi_history[1], dig_rc->igi_history[0]); - PHYDM_DBG(dm, ODM_COMP_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n", - dig_rc->fa_history[3], dig_rc->fa_history[2], - dig_rc->fa_history[1], dig_rc->fa_history[0]); - PHYDM_DBG(dm, ODM_COMP_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n", - (dig_rc->igi_bitmap & BIT(3)) >> 3, - (dig_rc->igi_bitmap & BIT(2)) >> 2, - (dig_rc->igi_bitmap & BIT(1)) >> 1, - dig_rc->igi_bitmap & BIT(0), - dig_rc->igi_bitmap); -} - -void phydm_dig_damping_chk(void *dm_void) -{ - PDM_ODM_T dm = (PDM_ODM_T)dm_void; - pDIG_T dig_t = &dm->DM_DigTable; - struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; - u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf; - u8 diff1 = 0, diff2 = 0; - u32 fa_low_th = dig_t->fa_th[0]; - u32 fa_high_th = dig_t->fa_th[1]; - u8 fa_pattern_match = 0; - u32 time_tmp; - - if (!dm->bLinked) - return; - - PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); - - /*== Release Damping ================================================*/ - if (dig_rc->damping_limit_en) { - PHYDM_DBG(dm, ODM_COMP_DIG, - "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n", - dig_rc->limit_time, dm->phydm_sys_up_time); - - time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD; - - if (DIFF_2(dm->RSSI_Min, dig_rc->limit_rssi) > 3 || - time_tmp < dm->phydm_sys_up_time) { - dig_rc->damping_limit_en = 0; - PHYDM_DBG(dm, ODM_COMP_DIG, "rssi_min=%d, limit_rssi=%d\n", - dm->RSSI_Min, dig_rc->limit_rssi); - } - return; - } - - /*== Damping Pattern Check============================================*/ - PHYDM_DBG(dm, ODM_COMP_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th); - - switch (igi_bitmap_4bit) { - case 0x5: /*4b'0101 ex:down(0x24)->up(0x28)->down(0x24)->up(0x28)*/ - if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) - diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; - - if (dig_rc->igi_history[2] > dig_rc->igi_history[3]) - diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3]; - - if (dig_rc->fa_history[0] < fa_low_th && - dig_rc->fa_history[1] > fa_high_th && - dig_rc->fa_history[2] < fa_low_th && - dig_rc->fa_history[3] > fa_high_th) { - /*Check each fa element*/ - fa_pattern_match = 1; - } - break; - case 0x9: /*4b'1001 ex:up(0x28)->down(0x26)->down(0x24)->up(0x28)*/ - if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) - diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; - - if (dig_rc->igi_history[2] < dig_rc->igi_history[3]) - diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2]; - - if (dig_rc->fa_history[0] < fa_low_th && - dig_rc->fa_history[1] > fa_high_th && - dig_rc->fa_history[2] > fa_low_th && - dig_rc->fa_history[3] < fa_high_th) { - /*Check each fa element*/ - fa_pattern_match = 1; - } - break; - default: - break; - } - - if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) { - dig_rc->damping_limit_en = 1; - dig_rc->damping_limit_val = dig_rc->igi_history[0]; - dig_rc->limit_time = dm->phydm_sys_up_time; - dig_rc->limit_rssi = dm->RSSI_Min; - - PHYDM_DBG(dm, ODM_COMP_DIG, - "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n", - dig_rc->damping_limit_val, - dig_rc->limit_time, dig_rc->limit_rssi); - } - - PHYDM_DBG(dm, ODM_COMP_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en); -} -#endif - - -VOID -ODM_ChangeDynamicInitGainThresh( - IN PVOID pDM_VOID, - IN u4Byte DM_Type, - IN u4Byte DM_Value - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if (DM_Type == DIG_TYPE_THRESH_HIGH) - { - pDM_DigTable->RssiHighThresh = DM_Value; - } - else if (DM_Type == DIG_TYPE_THRESH_LOW) - { - pDM_DigTable->RssiLowThresh = DM_Value; - } - else if (DM_Type == DIG_TYPE_ENABLE) - { - pDM_DigTable->Dig_Enable_Flag = TRUE; - } - else if (DM_Type == DIG_TYPE_DISABLE) - { - pDM_DigTable->Dig_Enable_Flag = FALSE; - } - else if (DM_Type == DIG_TYPE_BACKOFF) - { - if(DM_Value > 30) - DM_Value = 30; - pDM_DigTable->BackoffVal = (u1Byte)DM_Value; - } - else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) - { - if(DM_Value == 0) - DM_Value = 0x1; - pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; - } - else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) - { - if(DM_Value > 0x50) - DM_Value = 0x50; - pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; - } -} // DM_ChangeDynamicInitGainThresh // - -int -getIGIForDiff(int value_IGI) -{ - #define ONERCCA_LOW_TH 0x30 - #define ONERCCA_LOW_DIFF 8 - - if (value_IGI < ONERCCA_LOW_TH) { - if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) - return ONERCCA_LOW_TH; - else - return value_IGI + ONERCCA_LOW_DIFF; - } else { - return value_IGI; - } -} - -VOID -odm_FAThresholdCheck( - IN PVOID pDM_VOID, - IN BOOLEAN bDFSBand, - IN BOOLEAN bPerformance, - IN u4Byte RxTp, - IN u4Byte TxTp, - OUT u4Byte* dm_FA_thres - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if(pDM_Odm->bLinked && (bPerformance||bDFSBand)) - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /*For AP*/ -#if (DIG_HW == 1) - dm_FA_thres[0] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th1; - dm_FA_thres[1] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th2; - dm_FA_thres[2] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th3; -#else - if ((RxTp>>2) > TxTp && RxTp < 10000 && RxTp > 500) { /*10Mbps & 0.5Mbps*/ - dm_FA_thres[0] = 0x080; - dm_FA_thres[1] = 0x100; - dm_FA_thres[2] = 0x200; - } else { - dm_FA_thres[0] = 0x100; - dm_FA_thres[1] = 0x200; - dm_FA_thres[2] = 0x300; - } -#endif -#else - /*For NIC*/ - dm_FA_thres[0] = DM_DIG_FA_TH0; - dm_FA_thres[1] = DM_DIG_FA_TH1; - dm_FA_thres[2] = DM_DIG_FA_TH2; -#endif - } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bDFSBand) - { - // For DFS band and no link - dm_FA_thres[0] = 250; - dm_FA_thres[1] = 1000; - dm_FA_thres[2] = 2000; - } - else -#endif - { - dm_FA_thres[0] = 2000; - dm_FA_thres[1] = 4000; - dm_FA_thres[2] = 5000; - } - } - return; -} - -u1Byte -odm_ForbiddenIGICheck( - IN PVOID pDM_VOID, - IN u1Byte dym_min, - IN u1Byte CurrentIGI - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte rx_gain_min = pDM_DigTable->rx_gain_range_min; - - if (pDM_DigTable->LargeFA_Timeout) { - if (--pDM_DigTable->LargeFA_Timeout == 0) - pDM_DigTable->LargeFAHit = 0; - } - - if (pFalseAlmCnt->Cnt_all > 10000) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); - - if(pDM_DigTable->LargeFAHit != 3) - pDM_DigTable->LargeFAHit++; - - if(pDM_DigTable->ForbiddenIGI < CurrentIGI) { - pDM_DigTable->ForbiddenIGI = CurrentIGI; - pDM_DigTable->LargeFAHit = 1; - pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; - } - - if(pDM_DigTable->LargeFAHit >= 3) { - if((pDM_DigTable->ForbiddenIGI + 2) > pDM_DigTable->rx_gain_range_max) - rx_gain_min = pDM_DigTable->rx_gain_range_max; - else - rx_gain_min = (pDM_DigTable->ForbiddenIGI + 2); - pDM_DigTable->Recover_cnt = 1800; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); - } - } - - else if (pFalseAlmCnt->Cnt_all > 2000) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Cnt_all=%d, Cnt_all_pre=%d, CurrentIGI=0x%x, PreIGValue=0x%x\n", - pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_all_pre, CurrentIGI, pDM_DigTable->PreIGValue)); - - /* pFalseAlmCnt->Cnt_all = 1.1875*pFalseAlmCnt->Cnt_all_pre */ - if ((pFalseAlmCnt->Cnt_all > (pFalseAlmCnt->Cnt_all_pre + (pFalseAlmCnt->Cnt_all_pre >> 3) + (pFalseAlmCnt->Cnt_all_pre >> 4))) && (CurrentIGI < pDM_DigTable->PreIGValue)) { - if (pDM_DigTable->LargeFAHit != 3) - pDM_DigTable->LargeFAHit++; - - if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("Updating ForbiddenIGI by CurrentIGI, ForbiddenIGI=0x%x, CurrentIGI=0x%x\n", - pDM_DigTable->ForbiddenIGI, CurrentIGI)); - - pDM_DigTable->ForbiddenIGI = CurrentIGI; /*pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;*/ - pDM_DigTable->LargeFAHit = 1; - pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; - } - - } - - if (pDM_DigTable->LargeFAHit >= 3) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, ForbiddenIGI=0x%x\n", - pDM_DigTable->rx_gain_range_max, rx_gain_min, pDM_DigTable->ForbiddenIGI)); - - if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max) - rx_gain_min = pDM_DigTable->rx_gain_range_max; - else - rx_gain_min = (pDM_DigTable->ForbiddenIGI + 1); - - pDM_DigTable->Recover_cnt = 1200; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("Abnormal fa case: Recover_cnt = %d, rx_gain_min = 0x%x\n", - pDM_DigTable->Recover_cnt, rx_gain_min)); - } - } else { - if (pDM_DigTable->Recover_cnt != 0) { - - pDM_DigTable->Recover_cnt --; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); - } else { - - if(pDM_DigTable->LargeFAHit < 3) { - if((pDM_DigTable->ForbiddenIGI - 2) < dym_min) { - pDM_DigTable->ForbiddenIGI = dym_min; - rx_gain_min = dym_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); - } else { - if (pDM_DigTable->LargeFAHit == 0) { - pDM_DigTable->ForbiddenIGI -= 2; - rx_gain_min = (pDM_DigTable->ForbiddenIGI + 2); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); - } - } - } else { - pDM_DigTable->LargeFAHit = 0; - } - } - } - - return rx_gain_min; - -} - - -VOID -odm_InbandNoiseCalculate ( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte IGIBackup, TimeCnt = 0, ValidCnt = 0; - BOOLEAN bTimeout = TRUE; - s1Byte sNoise_A, sNoise_B; - s4Byte NoiseRpt_A = 0,NoiseRpt_B = 0; - u4Byte tmp = 0; - static u1Byte failCnt = 0; - - if(!(pDM_Odm->SupportICType & (ODM_RTL8192E))) - return; - - if(pDM_Odm->RFType == ODM_1T1R || *(pDM_Odm->pOnePathCCA) != ODM_CCA_2R) - return; - - if(!pDM_DigTable->bNoiseEst) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); - - //1 Set initial gain. - IGIBackup = pDM_DigTable->CurIGValue; - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = 0; - ODM_Write_DIG(pDM_Odm, 0x24); - - //1 Update idle time power report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x0); - - delay_ms(2); - - //1 Get noise power level - while(1) - { - //2 Read Noise Floor Report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - tmp = ODM_GetBBReg(pDM_Odm, 0x8f8, bMaskLWord); - - sNoise_A = (s1Byte)(tmp & 0xff); - sNoise_B = (s1Byte)((tmp & 0xff00)>>8); - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); - - if((sNoise_A < 20 && sNoise_A >= -70) && (sNoise_B < 20 && sNoise_B >= -70)) - { - ValidCnt++; - NoiseRpt_A += sNoise_A; - NoiseRpt_B += sNoise_B; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); - } - - TimeCnt++; - bTimeout = (TimeCnt >= 150)?TRUE:FALSE; - - if(ValidCnt == 20 || bTimeout) - break; - - delay_ms(2); - - } - - //1 Keep idle time power report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x1); - - //1 Recover IGI - ODM_Write_DIG(pDM_Odm, IGIBackup); - - //1 Calculate Noise Floor - if(ValidCnt != 0) - { - NoiseRpt_A /= (ValidCnt<<1); - NoiseRpt_B /= (ValidCnt<<1); - } - - if(bTimeout) - { - NoiseRpt_A = 0; - NoiseRpt_B = 0; - - failCnt ++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", failCnt)); - - if(failCnt == 3) - { - failCnt = 0; - pDM_DigTable->bNoiseEst = FALSE; - } - } - else - { - NoiseRpt_A = -110 + 0x24 + NoiseRpt_A -6; - NoiseRpt_B = -110 + 0x24 + NoiseRpt_B -6; - pDM_DigTable->bNoiseEst = FALSE; - failCnt = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NoiseRpt_A = %d, NoiseRpt_B = %d\n", NoiseRpt_A, NoiseRpt_B)); - } - - //1 Calculate IGI Offset - if(NoiseRpt_A > NoiseRpt_B) - { - pDM_DigTable->IGIOffset_A = NoiseRpt_A - NoiseRpt_B; - pDM_DigTable->IGIOffset_B = 0; - } - else - { - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = NoiseRpt_B - NoiseRpt_A; - } - -#endif - return; -} - -VOID -odm_DigForBtHsMode( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable=&pDM_Odm->DM_DigTable; - u1Byte digForBtHs=0; - u1Byte digUpBound=0x5a; - - if (pDM_Odm->bBtConnectProcess) { - digForBtHs = 0x22; - } else { - // - // Decide DIG value by BT HS RSSI. - // - digForBtHs = pDM_Odm->btHsRssi+4; - - //DIG Bound - if(digForBtHs > digUpBound) - digForBtHs = digUpBound; - if(digForBtHs < 0x1c) - digForBtHs = 0x1c; - - // update Current IGI - pDM_DigTable->BT30_CurIGI = digForBtHs; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs)); -#endif -} - -VOID -phydm_setBigJumpStep( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI -) -{ -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; - u1Byte i; - - if (pDM_DigTable->enableAdjustBigJump == 0) - return; - - for (i = 0; i <= pDM_DigTable->bigJumpStep1; i++) { - if ((CurrentIGI + step1[i]) > pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx]) { - if (i != 0) - i = i - 1; - break; - } else if (i == pDM_DigTable->bigJumpStep1) - break; - } - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x8c8, 0xe, i); - else if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_setBigJumpStep(): bigjump = %d (ori = 0x%d), LMT=0x%x\n", i, pDM_DigTable->bigJumpStep1, pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx])); -#endif -} - -VOID -ODM_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if (pDM_DigTable->bStopDIG) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Stop Writing IGI\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", - ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); - - //1 Check initial gain by upper bound - if ((!pDM_DigTable->bPSDInProgress) && pDM_Odm->bLinked) - { - if(0) - { - if (CurrentIGI > pDM_DigTable->rx_gain_range_max) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x) is larger than upper bound !!\n", CurrentIGI)); - CurrentIGI = pDM_DigTable->rx_gain_range_max; - } - } - if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE) - { - if(CurrentIGI > pDM_Odm->Adaptivity_IGI_upper) - CurrentIGI = pDM_Odm->Adaptivity_IGI_upper; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", CurrentIGI)); - } - } - - if(pDM_DigTable->CurIGValue != CurrentIGI) - { - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - /* Modify big jump step for 8822B and 8197F */ - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) - phydm_setBigJumpStep(pDM_Odm, CurrentIGI); -#endif - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - /* Set IGI value of CCK for new CCK AGC */ - if (pDM_Odm->cck_new_agc) { - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) - ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurrentIGI>>1)); - } -#endif - - /*Add by YuChen for USB IO too slow issue*/ - if ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) && (CurrentIGI > pDM_DigTable->CurIGValue)) - Phydm_Adaptivity(pDM_Odm, CurrentIGI); - - //1 Set IGI value - if (pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - - if(pDM_Odm->RFType > ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - } -#endif - } else if (pDM_Odm->SupportPlatform & (ODM_AP)) { - switch(*(pDM_Odm->pOnePathCCA)) - { - case ODM_CCA_2R: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - - if(pDM_Odm->RFType > ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - } -#endif - break; - case ODM_CCA_1R_A: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - if(pDM_Odm->RFType != ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); - break; - case ODM_CCA_1R_B: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); - if(pDM_Odm->RFType != ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - break; - } - } - - pDM_DigTable->CurIGValue = CurrentIGI; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x).\n", CurrentIGI)); - -} - -VOID -odm_PauseDIG( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte IGIValue -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG()=========> level = %d\n", pause_level)); - - if ((pDM_DigTable->pause_dig_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_DIG) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseDIG(): Return: SupportAbility DIG or FA is disabled !!\n")); - return; - } - - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseDIG(): Return: Wrong pause level !!\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], - pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); - - switch (PauseType) { - /* Pause DIG */ - case PHYDM_PAUSE: - { - /* Disable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_DIG)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Pause DIG !!\n")); - - /* Backup IGI value */ - if (pDM_DigTable->pause_dig_level == 0) { - pDM_DigTable->IGIBackup = pDM_DigTable->CurIGValue; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Backup IGI = 0x%x, new IGI = 0x%x\n", pDM_DigTable->IGIBackup, IGIValue)); - } - - /* Record IGI value */ - pDM_DigTable->pause_dig_value[pause_level] = IGIValue; - - /* Update pause level */ - pDM_DigTable->pause_dig_level = (pDM_DigTable->pause_dig_level | BIT(pause_level)); - - /* Write new IGI value */ - if (BIT(pause_level + 1) > pDM_DigTable->pause_dig_level) { - ODM_Write_DIG(pDM_Odm, IGIValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): IGI of higher level = 0x%x\n", IGIValue)); - } - break; - } - /* Resume DIG */ - case PHYDM_RESUME: - { - /* check if the level is illegal or not */ - if ((pDM_DigTable->pause_dig_level & (BIT(pause_level))) != 0) { - pDM_DigTable->pause_dig_level = pDM_DigTable->pause_dig_level & (~(BIT(pause_level))); - pDM_DigTable->pause_dig_value[pause_level] = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Resume DIG !!\n")); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong resume level !!\n")); - break; - } - - /* Resume DIG */ - if (pDM_DigTable->pause_dig_level == 0) { - /* Write backup IGI value */ - ODM_Write_DIG(pDM_Odm, pDM_DigTable->IGIBackup); - pDM_DigTable->bIgnoreDIG = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write original IGI = 0x%x\n", pDM_DigTable->IGIBackup)); - - /* Enable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_DIG); - break; - } - - if (BIT(pause_level) > pDM_DigTable->pause_dig_level) { - s1Byte max_level; - - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((pDM_DigTable->pause_dig_level & BIT(max_level)) > 0) - break; - } - - /* write IGI of lower level */ - ODM_Write_DIG(pDM_Odm, pDM_DigTable->pause_dig_value[max_level]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write IGI (0x%x) of level (%d)\n", - pDM_DigTable->pause_dig_value[max_level], max_level)); - break; - } - break; - } - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong type !!\n")); - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], - pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); - -} - -BOOLEAN -odm_DigAbort( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - - //SupportAbility - if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_FA_CNT is disabled\n")); - return TRUE; - } - - //SupportAbility - if(!(pDM_Odm->SupportAbility & ODM_BB_DIG)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_DIG is disabled\n")); - return TRUE; - } - - //ScanInProcess - if(*(pDM_Odm->pbScanInProcess)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress \n")); - return TRUE; - } - - if(pDM_DigTable->bIgnoreDIG) - { - pDM_DigTable->bIgnoreDIG = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG \n")); - return TRUE; - } - - //add by Neil Chen to avoid PSD is processing - if(pDM_Odm->bDMInitialGainEnable == FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing \n")); - return TRUE; - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if OS_WIN_FROM_WIN7(OS_VERSION) - if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test \n")); - return TRUE; - } - #endif - - if(pDM_Odm->bBtHsOperation) - { - odm_DigForBtHsMode(pDM_Odm); - } - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) - { - printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); - ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); - return TRUE; - } - #endif -#else - if (!(priv->up_time > 5)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG Operation Period \n")); - return TRUE; - } -#endif - - return FALSE; -} - -VOID -odm_DIGInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); -#endif - u4Byte ret_value; - u1Byte i; - - pDM_DigTable->bStopDIG = FALSE; - pDM_DigTable->bIgnoreDIG = FALSE; - pDM_DigTable->bPSDInProgress = FALSE; - pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); - pDM_DigTable->PreIGValue = 0; - pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; - pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; - pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; - pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; - pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; - pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; - pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; - pDM_DigTable->PreCCK_CCAThres = 0xFF; - pDM_DigTable->CurCCK_CCAThres = 0x83; - pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; - pDM_DigTable->LargeFAHit = 0; - pDM_DigTable->LargeFA_Timeout = 0; - pDM_DigTable->Recover_cnt = 0; - pDM_DigTable->bMediaConnect_0 = FALSE; - pDM_DigTable->bMediaConnect_1 = FALSE; -#if (DIG_HW == 1) - pDM_DigTable->pre_rssi_min = 0; -#endif - //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error - pDM_Odm->bDMInitialGainEnable = TRUE; - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - pDM_DigTable->tdma_dig_cnt = 0; - pDM_DigTable->pre_tdma_dig_cnt = 0; - pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE] = pDM_DigTable->CurIGValue; - pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] = pDM_DigTable->CurIGValue; - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = DM_DIG_MAX_NIC; - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = DM_DIG_MIN_NIC; - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = DM_DIG_MIN_NIC; - - for(i = 0; i <= 1; i++) { - pDM_DigTable->stay_check_state_cnt[i] = 0; // check state - pDM_DigTable->goto_lock_state_cnt[i] = 0; // check state - pDM_DigTable->goto_release_state_cnt[i] = 0; // lock state - pDM_DigTable->stay_release_state_cnt[i] = 0; // release state - } -#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - pDM_DigTable->DIG_Dynamic_MIN_0 = 0x25; - pDM_DigTable->DIG_Dynamic_MIN_1 = 0x25; - - // For AP\ ADSL modified DIG - pDM_DigTable->bTpTarget = FALSE; - pDM_DigTable->bNoiseEst = TRUE; - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = 0; - pDM_DigTable->TpTrainTH_min = 0; - - // For RTL8881A - FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; - - //Dyanmic EDCCA - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - ODM_SetBBReg(pDM_Odm, 0xC50, 0xFFFF0000, 0xfafd); - } -#else - pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; - pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; - - //To Initi BT30 IGI - pDM_DigTable->BT30_CurIGI=0x32; - - ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - pDM_DigTable->pause_dig_level = 0; - ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - pDM_DigTable->pause_cckpd_level = 0; -#endif - - if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)) - { - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; - pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; - } - else - { - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; - pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; - } - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - pDM_DigTable->enableAdjustBigJump = 1; - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - ret_value = ODM_GetBBReg(pDM_Odm, 0x8c8, bMaskLWord); - pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; - pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; - pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; - - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, bMaskLWord); - pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; - pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; - pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; - } - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { - for (i = 0; i < sizeof(pDM_DigTable->bigJumpLmt); i++) { - if (pDM_DigTable->bigJumpLmt[i] == 0) - pDM_DigTable->bigJumpLmt[i] = 0x64; /* Set -10dBm as default value */ - } - } -#endif - - -#if (DIG_HW == 1) - pDM_DigTable->pre_rssi_min = 0; -#endif -#ifdef CFG_DIG_DAMPING_CHK - phydm_dig_recorder_reset(pDM_Odm); - pDM_DigTable->dig_dl_en = 1; -#endif -} - -u1Byte -phydm_igi_chkby_upper_lower_bond( - u1Byte igi, - u1Byte upper_bond, - u1Byte lower_bond - ) -{ - u1Byte igi_tmp = igi; - - if (igi < lower_bond) - igi_tmp = lower_bond; - else if (igi > upper_bond) - igi_tmp = upper_bond; - - return igi_tmp; -} - -VOID -odm_DIG( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - PSTA_INFO_T pEntry; -#endif - - // Common parameters - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; -#ifdef CFG_DIG_DAMPING_CHK - struct phydm_dig_recoder_strcut *dig_rc = &pDM_DigTable->dig_recoder_t; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); -#endif -// PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte CurrentIGI; - BOOLEAN FirstConnect,FirstDisConnect; - u1Byte DIG_MaxOfMin, DIG_Dynamic_MIN; - u1Byte dm_dig_max, dm_dig_min; - u1Byte offset; - u1Byte rssi_min = pDM_Odm->RSSI_Min; - u1Byte igi_upper_rssi_min; - u4Byte dm_FA_thres[3]; - u4Byte TxTp = 0, RxTp = 0; - BOOLEAN bDFSBand = FALSE; - BOOLEAN bPerformance = TRUE, bFirstTpTarget = FALSE, bFirstCoverage = FALSE; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte TpTrainTH_MIN = DM_DIG_TP_Target_TH0; - static u1Byte TimeCnt = 0; - u1Byte i; -#endif -#if (DIG_HW == 1) - BOOLEAN DIG_GoUpCheck = TRUE; - u1Byte step_size[3] = {0}; -#endif - - CurrentIGI = pDM_DigTable->CurIGValue; - - if(odm_DigAbort(pDM_Odm) == TRUE) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI=0x%x\n", CurrentIGI)); - -#if (DIG_HW == 1) - if (pDM_Odm->bLinked) { - if (pDM_DigTable->pre_rssi_min <= rssi_min) { - step_size[2] = 2; - step_size[1] = 1; - step_size[0] = 2; - } else { - step_size[2] = 4; - step_size[1] = 2; - step_size[0] = 2; - } - pDM_DigTable->pre_rssi_min = rssi_min; - } else { - step_size[2] = 2; - step_size[1] = 1; - step_size[0] = 2; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI_Min = %d, pre_rssi_min = %d\n", - rssi_min, pDM_DigTable->pre_rssi_min)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", - step_size[0], step_size[1], step_size[2])); -#endif - - //1 Update status - { - DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; - FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); - FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); - } - -#ifdef CFG_DIG_DAMPING_CHK - /*Record IGI History*/ - phydm_dig_recorder(pDM_Odm, FirstConnect, CurrentIGI, pFalseAlmCnt->Cnt_all); - - /*DIG Damping Check*/ - phydm_dig_damping_chk(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - //1 Noise Floor Estimate - //pDM_DigTable->bNoiseEst = (FirstConnect)?TRUE:pDM_DigTable->bNoiseEst; - //odm_InbandNoiseCalculate (pDM_Odm); - - //1 Mode decision - if(pDM_Odm->bLinked) - { - //2 Calculate total TP - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - RxTp += (u4Byte)(pEntry->rx_byte_cnt_LowMAW>>7); - TxTp += (u4Byte)(pEntry->tx_byte_cnt_LowMAW>>7); //Kbps - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TX TP = %dkbps, RX TP = %dkbps\n", TxTp, RxTp)); - } - - switch(pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable) - { - case 0: - { - bPerformance = TRUE; - break; - } - case 1: - { - bPerformance = FALSE; - break; - } - case 2: - { - if(pDM_Odm->bLinked) - { - if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH0) - TpTrainTH_MIN = pDM_DigTable->TpTrainTH_min; - - if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH1) - TpTrainTH_MIN = DM_DIG_TP_Target_TH1; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TP training mode lower bound = %dkbps\n", TpTrainTH_MIN)); - - //2 Decide DIG mode by total TP - if((TxTp + RxTp) > DM_DIG_TP_Target_TH1) // change to performance mode - { - bFirstTpTarget = (!pDM_DigTable->bTpTarget)?TRUE:FALSE; - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - } - else if((TxTp + RxTp) < TpTrainTH_MIN) // change to coverage mode - { - bFirstCoverage = (pDM_DigTable->bTpTarget)?TRUE:FALSE; - - if(TimeCnt < DM_DIG_TP_Training_Period) - { - pDM_DigTable->bTpTarget = FALSE; - bPerformance = FALSE; - TimeCnt++; - } - else - { - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - bFirstTpTarget = TRUE; - TimeCnt = 0; - } - } - else // remain previous mode - { - bPerformance = pDM_DigTable->bTpTarget; - - if(!bPerformance) - { - if(TimeCnt < DM_DIG_TP_Training_Period) - TimeCnt++; - else - { - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - bFirstTpTarget = TRUE; - TimeCnt = 0; - } - } - } - - if(!bPerformance) - pDM_DigTable->TpTrainTH_min = RxTp + TxTp; - - } - else - { - bPerformance = FALSE; - pDM_DigTable->TpTrainTH_min = 0; - } - break; - } - default: - bPerformance = TRUE; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== bPerformance = %d ======\n", bPerformance)); -#endif - - //1 Boundary Decision - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - //2 For AP\ADSL - if(!bPerformance) - { - dm_dig_max = DM_DIG_MAX_AP_COVERAGR; - dm_dig_min = DM_DIG_MIN_AP_COVERAGE; -#if (DIG_HW == 1) - DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; -#else - DIG_MaxOfMin = DM_DIG_MAX_OF_MIN_COVERAGE; -#endif - - } - else - { - if (pDM_Odm->RFType == ODM_1T1R) - dm_dig_max = DM_DIG_MAX_AP - 6; - else - dm_dig_max = DM_DIG_MAX_AP; - - if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && (pDM_Odm->SupportICType & ODM_RTL8814A)) /* for 2G 8814 */ - dm_dig_min = 0x1c; - else if (pDM_Odm->SupportICType & ODM_RTL8197F) /*refine by YuChen 20160815 asked by RF Arthur*/ - dm_dig_min = 0x1e; - else - dm_dig_min = DM_DIG_MIN_AP; - -#if (DIG_HW == 1) - DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; -#else - DIG_MaxOfMin = DM_DIG_MAX_OF_MIN; -#endif - - } - - //4 TX2path - if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) - dm_dig_max = 0x2A; - -#if RTL8192E_SUPPORT -#ifdef HIGH_POWER_EXT_LNA - if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) - dm_dig_max = 0x42; -#endif -#endif - -#else //#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - - //2 For WIN\CE - if(pDM_Odm->SupportICType >= ODM_RTL8188E) - dm_dig_max = 0x5A; - else - dm_dig_max = DM_DIG_MAX_NIC; - - if(pDM_Odm->SupportICType != ODM_RTL8821) - dm_dig_min = DM_DIG_MIN_NIC; - else - dm_dig_min = 0x1C; - - DIG_MaxOfMin = DM_DIG_MAX_AP; -#endif - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - /* Modify lower bound for DFS band */ - if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || - ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - && phydm_dfs_master_enabled(pDM_Odm) == TRUE - #endif - ) { - bDFSBand = TRUE; - if (*pDM_Odm->pBandWidth == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS+2; - else - dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): ====== In DFS band ======\n")); - } -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (pDM_Odm->pu1ForcedIgiLb && (0 < *pDM_Odm->pu1ForcedIgiLb)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Force IGI lb to: 0x%02x !!!!!!\n", *pDM_Odm->pu1ForcedIgiLb)); - dm_dig_min = *pDM_Odm->pu1ForcedIgiLb; - dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); - } -#endif - - //1 Adjust boundary by RSSI - if(pDM_Odm->bLinked && bPerformance) - { - //2 Modify DIG upper bound -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - offset = 15; -#else - //4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT - if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig == 1)) - { - offset = 10; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Coex. case: Force upper bound to RSSI + %d !!!!!!\n", offset)); - } - else - offset = 15; -#endif - igi_upper_rssi_min = rssi_min + offset; - - /*rx_gain_range_max*/ - if((igi_upper_rssi_min) > dm_dig_max) - pDM_DigTable->rx_gain_range_max = dm_dig_max; - else if((igi_upper_rssi_min) < dm_dig_min) - pDM_DigTable->rx_gain_range_max = dm_dig_min; - else - pDM_DigTable->rx_gain_range_max = igi_upper_rssi_min; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - //2 Modify DIG lower bound - //if(pDM_Odm->bOneEntryOnly) - { - /*DIG_Dynamic_MIN()*/ - if(rssi_min < dm_dig_min) - DIG_Dynamic_MIN = dm_dig_min; - else if (rssi_min > DIG_MaxOfMin) - DIG_Dynamic_MIN = DIG_MaxOfMin; - else - DIG_Dynamic_MIN = rssi_min; - -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (bDFSBand) { - DIG_Dynamic_MIN = dm_dig_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } -#endif - } -#else - { - //4 For AP -#ifdef __ECOS - HAL_REORDER_BARRIER(); -#else - rmb(); -#endif - if (bDFSBand) - { - DIG_Dynamic_MIN = dm_dig_min; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } else { - - /*DIG_Dynamic_MIN(rx_gain_range_min)*/ - if(rssi_min < dm_dig_min) - DIG_Dynamic_MIN = dm_dig_min; - else if (rssi_min > DIG_MaxOfMin) - DIG_Dynamic_MIN = DIG_MaxOfMin; - else - DIG_Dynamic_MIN = rssi_min; - } - } -#endif - } - else - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bPerformance && bDFSBand) - { - pDM_DigTable->rx_gain_range_max = 0x28; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, - ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->rx_gain_range_max)); - } - else -#endif - { - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_OF_MIN; - } - DIG_Dynamic_MIN = dm_dig_min; - } - - //1 Force Lower Bound for AntDiv - if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) - { - if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { - if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) { - DIG_Dynamic_MIN = DIG_MaxOfMin; - } - else { - DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Antenna diversity case: Force lower bound to 0x%x\n", - DIG_Dynamic_MIN)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Antenna diversity case: RSSI_max=0x%x\n", - pDM_DigTable->AntDiv_RSSI_max)); - } - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, - ("Adjust boundary by RSSI rx_gain_range_max=0x%x, DIG_Dynamic_MIN = 0x%x\n", - pDM_DigTable->rx_gain_range_max, DIG_Dynamic_MIN)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, - ("Link status: bLinked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n\n", - pDM_Odm->bLinked, rssi_min, FirstConnect, FirstDisConnect)); - - //1 Modify DIG lower bound, deal with abnormal case - //2 Abnormal false alarm case - if(!pDM_Odm->bLinked) - { - pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; - - if (FirstDisConnect) - pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; - } - else { - pDM_DigTable->rx_gain_range_min = odm_ForbiddenIGICheck(pDM_Odm, DIG_Dynamic_MIN, CurrentIGI); - } - //2 Abnormal # beacon case -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pDM_Odm->bLinked && !FirstConnect) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", pDM_Odm->PhyDbgInfo.NumQryBeaconPkt)); - if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pDM_Odm->bsta_state)) - { - pDM_DigTable->rx_gain_range_min = 0x1c; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x !!!!!!\n\n", - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, pDM_DigTable->rx_gain_range_min)); - } - } -#endif - - //2 Abnormal lower bound case - if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) - { - pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnrormal rx_gain_range_min: force to 0x%x\n\n", - pDM_DigTable->rx_gain_range_min)); - } - -#ifdef CFG_DIG_DAMPING_CHK - /*Limit Dyn min by damping*/ - if (pDM_DigTable->dig_dl_en && - dig_rc->damping_limit_en && - pDM_DigTable->rx_gain_range_min < dig_rc->damping_limit_val) { - PHYDM_DBG(pDM_Odm, ODM_COMP_DIG, - "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n", - pDM_DigTable->rx_gain_range_min, dig_rc->damping_limit_val); - - pDM_DigTable->rx_gain_range_min = dig_rc->damping_limit_val; - } -#endif - - //1 False alarm threshold decision - odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); - - pDM_DigTable->fa_th[0] = dm_FA_thres[0]; - pDM_DigTable->fa_th[1] = dm_FA_thres[1]; - pDM_DigTable->fa_th[2] = dm_FA_thres[2]; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", - dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - //1 Adjust initial gain by false alarm - if(pDM_Odm->bLinked && bPerformance) - { - //2 After link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); - - if(bFirstTpTarget || (FirstConnect && bPerformance)) { - pDM_DigTable->LargeFAHit = 0; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bDFSBand) - { - if(rssi_min > 0x28) { - CurrentIGI = 0x28; - } - else { - CurrentIGI = rssi_min; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band:One-shot to 0x28 upmost\n")); - } - else -#endif - { - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -#if (RTL8812A_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); -#endif -#endif - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First connect case: IGI does on-shot to 0x%x\n", CurrentIGI)); - - } - else { - -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); - - CurrentIGI = phydm_dig_current_igi_by_fa_th(pDM_Odm, CurrentIGI, dm_FA_thres, step_size, DIG_GoUpCheck, NORMAL_DIG); -#endif - //4 Abnormal # beacon case -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) - { - CurrentIGI = pDM_DigTable->rx_gain_range_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, CurrentIGI)); - } -#endif - } - } else { - //2 Before link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); - - if(FirstDisConnect || bFirstCoverage) { - CurrentIGI = dm_dig_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First disconnect case: IGI does on-shot to lower bound\n")); - } else { -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); - - CurrentIGI = phydm_dig_current_igi_by_fa_th(pDM_Odm, CurrentIGI, dm_FA_thres, step_size, DIG_GoUpCheck, NORMAL_DIG); -#endif - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("before check igi by ULbond, CurrentIGI=0x%x\n", CurrentIGI)); - - //1 Check initial gain by upper/lower bound - CurrentIGI = phydm_igi_chkby_upper_lower_bond(CurrentIGI, pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("after ULbond check,CurrentIGI=0x%x,\n", CurrentIGI)); - - //1 Update status - { -#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) - if(pDM_Odm->bBtHsOperation) - { - if(pDM_Odm->bLinked) - { - if(pDM_DigTable->BT30_CurIGI > (CurrentIGI)) - ODM_Write_DIG(pDM_Odm, CurrentIGI); - else - ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI); - - pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; - pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; - } - else - { - if(pDM_Odm->bLinkInProcess) - ODM_Write_DIG(pDM_Odm, 0x1c); - else if(pDM_Odm->bBtConnectProcess) - ODM_Write_DIG(pDM_Odm, 0x28); - else - ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); - } - } - else // BT is not using -#endif - { - ODM_Write_DIG(pDM_Odm, CurrentIGI); - pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; - pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; - } - } -} - -void -phydm_lna_sat_chk_watchdog( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; - u1Byte rssi_min = pDM_Odm->RSSI_Min; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); - - if(!(pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("SupportAbility ODM_BB_LNA_SAT_CHK is disabled, return.\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n", - pDM_LNA_info->pre_timer_check_cnt, - pDM_LNA_info->cur_timer_check_cnt)); - - if(pDM_Odm->is_disable_lna_sat_chk) { - phydm_lna_sat_chk_init(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("is_disable_lna_sat_chk=%d, return.\n", pDM_Odm->is_disable_lna_sat_chk)); - return; - } - - if ((pDM_Odm->SupportICType & ODM_RTL8197F) == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("SupportICType != ODM_RTL8197F, return.\n")); - return; - } - - if ((rssi_min == 0) || (rssi_min == 0xff)) { - // adapt agc table 0 - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); - phydm_lna_sat_chk_init(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("rssi_min=%d, return.\n", rssi_min)); - return; - } - - if(pDM_LNA_info->cur_timer_check_cnt == pDM_LNA_info->pre_timer_check_cnt) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("Timer check fail, restart timer.\n")); - phydm_lna_sat_chk(pDM_Odm); - } - else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("Timer check pass.\n")); - } - pDM_LNA_info->pre_timer_check_cnt = pDM_LNA_info->cur_timer_check_cnt; -} - -void -phydm_lna_sat_chk_init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); - - pDM_LNA_info->check_time = 0; - pDM_LNA_info->sat_cnt_acc_patha = 0; - pDM_LNA_info->sat_cnt_acc_pathb = 0; - pDM_LNA_info->cur_sat_status = 0; - pDM_LNA_info->pre_sat_status = 0; - pDM_LNA_info->cur_timer_check_cnt = 0; - pDM_LNA_info->pre_timer_check_cnt = 0; -} - -void -phydm_set_ofdm_agc_tab( - IN PVOID pDM_VOID, - IN u1Byte tab_sel -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - /* table sel:0/2, 1 is used for CCK */ - if (tab_sel == OFDM_AGC_TAB_0) - ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); - else if (tab_sel == OFDM_AGC_TAB_2) - ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_2); - else - ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); -} - -u1Byte -phydm_get_ofdm_agc_tab( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - return (u1Byte)ODM_GetBBReg(pDM_Odm, 0xc70, 0x1e00); -} - - -void -phydm_lna_sat_chk( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; - u1Byte igi_rssi_min, rssi_min = pDM_Odm->RSSI_Min; - u4Byte sat_status_patha, sat_status_pathb; - u1Byte igi_restore = pDM_DigTable->CurIGValue; - u1Byte i, lna_sat_chk_cnt = pDM_Odm->lna_sat_chk_cnt; - u4Byte lna_sat_cnt_thd = 0; - u1Byte agc_tab; - u4Byte max_check_time = 0; -// u4Byte func_start, func_end; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); - - if(!(pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("SupportAbility ODM_BB_LNA_SAT_CHK is disabled, return.\n")); - return; - } - - if(pDM_Odm->is_disable_lna_sat_chk) { - phydm_lna_sat_chk_init(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("is_disable_lna_sat_chk=%d, return.\n", pDM_Odm->is_disable_lna_sat_chk)); - return; - } - - //func_start = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); - - // move igi to target pin of rssi_min - if ((rssi_min == 0) || (rssi_min == 0xff)) { - // adapt agc table 0 - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); - phydm_lna_sat_chk_init(pDM_Odm); - return; - } - else if (rssi_min % 2 != 0) - igi_rssi_min = rssi_min + RSSI_TO_IGI - 1; - else - igi_rssi_min = rssi_min + RSSI_TO_IGI; - - if ((pDM_Odm->lna_sat_chk_period_ms > 0) && (pDM_Odm->lna_sat_chk_period_ms <= ONE_SEC_MS)) - max_check_time = lna_sat_chk_cnt*(ONE_SEC_MS/(pDM_Odm->lna_sat_chk_period_ms))*5; - else - max_check_time = lna_sat_chk_cnt * 5; - - lna_sat_cnt_thd = (max_check_time * pDM_Odm->lna_sat_chk_duty_cycle)/100; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nlna_sat_chk_cnt=%d, lna_sat_chk_period_ms=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n", - pDM_LNA_info->check_time, - rssi_min, - igi_rssi_min, - lna_sat_chk_cnt, - pDM_Odm->lna_sat_chk_period_ms, - max_check_time, - lna_sat_cnt_thd)); - - ODM_Write_DIG(pDM_VOID, igi_rssi_min); - - // adapt agc table 0 check saturation status - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); - // open rf power detection ckt & set detection range - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x86, 0x1f, 0x10); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x86, 0x1f, 0x10); - - // check saturation status - for(i = 0; i < lna_sat_chk_cnt; i++) { - sat_status_patha = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0xae, 0xc0000); - sat_status_pathb = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0xae, 0xc0000); - if(sat_status_patha != 0) - pDM_LNA_info->sat_cnt_acc_patha++; - if(sat_status_pathb != 0) - pDM_LNA_info->sat_cnt_acc_pathb++; - - if ((pDM_LNA_info->sat_cnt_acc_patha >= lna_sat_cnt_thd) || - (pDM_LNA_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd)) { - pDM_LNA_info->cur_sat_status= 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("cur_sat_status=%d, check_time=%d\n", - pDM_LNA_info->cur_sat_status, - pDM_LNA_info->check_time)); - break; - } else - pDM_LNA_info->cur_sat_status= 0; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n", - pDM_LNA_info->cur_sat_status, - pDM_LNA_info->pre_sat_status, - pDM_LNA_info->sat_cnt_acc_patha, - pDM_LNA_info->sat_cnt_acc_pathb)); - - // agc table decision - if (pDM_LNA_info->cur_sat_status) { - if(!pDM_Odm->is_disable_gain_table_switch) - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_2); - pDM_LNA_info->check_time = 0; - pDM_LNA_info->sat_cnt_acc_patha = 0; - pDM_LNA_info->sat_cnt_acc_pathb = 0; - pDM_LNA_info->pre_sat_status = pDM_LNA_info->cur_sat_status; - - } else if (pDM_LNA_info->check_time <= (max_check_time - 1)) { - if (pDM_LNA_info->pre_sat_status && (!pDM_Odm->is_disable_gain_table_switch)) - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_2); - pDM_LNA_info->check_time++; - - } else if (pDM_LNA_info->check_time == max_check_time) { - if(!pDM_Odm->is_disable_gain_table_switch && (pDM_LNA_info->pre_sat_status == 1)) - phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); - pDM_LNA_info->check_time = 0; - pDM_LNA_info->sat_cnt_acc_patha = 0; - pDM_LNA_info->sat_cnt_acc_pathb = 0; - pDM_LNA_info->pre_sat_status = pDM_LNA_info->cur_sat_status; - } - - agc_tab = phydm_get_ofdm_agc_tab(pDM_Odm); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("use AGC table %d\n", agc_tab)); - //func_end = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("function process time=%d\n", - // func_end - func_start)); - - // restore previous igi - ODM_Write_DIG(pDM_VOID, igi_restore); - - pDM_LNA_info->cur_timer_check_cnt++; - ODM_SetTimer(pDM_Odm, &pDM_LNA_info->phydm_lna_sat_chk_timer, pDM_Odm->lna_sat_chk_period_ms); -} - -void -phydm_lna_sat_chk_callback( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); - phydm_lna_sat_chk(pDM_Odm); -} - -void -phydm_lna_sat_chk_timers( - IN PVOID pDM_VOID, - u8 state - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; - - if (state == INIT_LNA_SAT_CHK_TIMMER) { - ODM_InitializeTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer), - (RT_TIMER_CALL_BACK)phydm_lna_sat_chk_callback, NULL, "phydm_lna_sat_chk_timer"); - } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) { - ODM_CancelTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer)); - } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) { - ODM_ReleaseTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer)); - } -} - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - -void -phydm_reset_state_cnt( - IN PVOID pDM_VOID, - bool is_high_low_sel - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - pDM_DigTable->stay_check_state_cnt[is_high_low_sel] = 0; - pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] = 0; - pDM_DigTable->goto_release_state_cnt[is_high_low_sel] = 0; - pDM_DigTable->stay_release_state_cnt[is_high_low_sel] = 0; -} - -u1Byte -phydm_rx_gain_min_check( - IN PVOID pDM_VOID, - IN u1Byte dym_min, - IN u1Byte CurrentIGI, - IN u1Byte rx_gain_min, - bool is_high_low_sel - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS_ACC pFalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); - u4Byte fa_cca_ratio = pFalseAlmCntAcc->fa_cca_ratio[is_high_low_sel]; - u1Byte ori_check_state = pDM_DigTable->rx_gain_min_check_state[is_high_low_sel]; -// u1Byte ori_goto_lock_state_cnt = pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]; - bool is_enough_fa = (pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] >= pDM_Odm->tdma_is_enough_fa_th) ? 1 : 0; - bool high_fa_cca_ratio; - bool low_fa_cca_ratio; - /*rgm = rx_gain_min*/ - bool is_igi_less_eq_rgm = (CurrentIGI <= rx_gain_min) ? 1 : 0; - u4Byte debug_component; - - if (pDM_Odm->is_disable_rx_gain_min_check) { - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; - return dym_min; - } - - if (is_high_low_sel) { - high_fa_cca_ratio = ((fa_cca_ratio >= pDM_Odm->tdma_high_fa_cca_ratio_l2h) && (is_enough_fa==1)) ? 1 : 0; - low_fa_cca_ratio = ((fa_cca_ratio <= pDM_Odm->tdma_high_fa_cca_ratio_h2l) || (is_enough_fa==0)) ? 1 : 0; - - if (pDM_Odm->rx_gain_min_dbg_switch == TDMA_DIG_HIGH_STATE) - debug_component = ODM_COMP_TDMA_HDIG; - else - debug_component = 0; - } else { - high_fa_cca_ratio = ((fa_cca_ratio >= pDM_Odm->tdma_low_fa_cca_ratio_l2h) && (is_enough_fa==1)) ? 1 : 0; - low_fa_cca_ratio = ((fa_cca_ratio <= pDM_Odm->tdma_low_fa_cca_ratio_h2l) || (is_enough_fa==0)) ? 1 : 0; - if (pDM_Odm->rx_gain_min_dbg_switch == TDMA_DIG_LOW_STATE) - debug_component = ODM_COMP_TDMA_LDIG; - else - debug_component = 0; - } - - ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, - ("dym_min=0x%x,CurrentIGI=0x%x,rx_gain_min=0x%x,fa_cca_ratio=%d,is_high_low_sel=%d,is_enough_fa=%d\n", - dym_min, - CurrentIGI, - rx_gain_min, - fa_cca_ratio, - is_high_low_sel, - is_enough_fa)); - - ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, - ("check_state=%d,stay_check_state_cnt=%d,goto_lock_cnt=%d,goto_release_cnt=%d,stay_release_state_cnt=%d\n", - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel], - pDM_DigTable->stay_check_state_cnt[is_high_low_sel], - pDM_DigTable->goto_lock_state_cnt[is_high_low_sel], - pDM_DigTable->goto_release_state_cnt[is_high_low_sel], - pDM_DigTable->stay_release_state_cnt[is_high_low_sel])); - - if (ori_check_state == OSC_CHECK_STATE) { - - if (high_fa_cca_ratio) { - - if (pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] > 0) - pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]--; - - pDM_DigTable->stay_check_state_cnt[is_high_low_sel]++; - - if (pDM_DigTable->stay_check_state_cnt[is_high_low_sel] >= 3) { - rx_gain_min = rx_gain_min + 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; - ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, ("stay check_state.\n")); - } - } else if (low_fa_cca_ratio) { - - /*"if (CurrentIGI <= rx_gain_min)" is to avoid osc.*/ - - if (is_igi_less_eq_rgm) { - if (pDM_DigTable->stay_check_state_cnt[is_high_low_sel] > 0) - pDM_DigTable->stay_check_state_cnt[is_high_low_sel]--; - - pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]++; - if (pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] >= 3) { - rx_gain_min = rx_gain_min; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; - } - } - } - } - else if (ori_check_state == OSC_LOCK_STATE) { - /*rgm = rx_gain_min*/ - if (is_igi_less_eq_rgm) { - if (high_fa_cca_ratio) { - rx_gain_min = rx_gain_min + 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; - } else if (low_fa_cca_ratio) { - if ((rx_gain_min - 2) >= dym_min) { - pDM_DigTable->goto_release_state_cnt[is_high_low_sel]++; - if (pDM_DigTable->goto_release_state_cnt[is_high_low_sel] >= 6) { - - /*translate to RELEASE_STATE*/ - rx_gain_min = rx_gain_min - 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_RELEASE_STATE; - } - } else { - rx_gain_min = dym_min; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; - } - } - } - else { - /*not update rx_gain_min, back to check state to find suitable one.*/ - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; - } - } - - else if (ori_check_state == OSC_RELEASE_STATE) { - /*rgm = rx_gain_min*/ - if (is_igi_less_eq_rgm) { - if (low_fa_cca_ratio) { - - pDM_DigTable->stay_release_state_cnt[is_high_low_sel]++; - - if (pDM_DigTable->stay_release_state_cnt[is_high_low_sel] >= 3) { - if ((rx_gain_min - 2) >= dym_min) { - /*test success, keep trying lower rx_gain_min*/ - rx_gain_min = rx_gain_min - 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_RELEASE_STATE; - } else { - rx_gain_min= dym_min; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; - } - } - } else { - /*test fail, resume rx_gain_min*/ - rx_gain_min = rx_gain_min + 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; - } - } - else { - /*wait igi comes down*/ - if (!low_fa_cca_ratio) { - rx_gain_min = rx_gain_min + 2; - phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; - } - } - } - - ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, - ("check_state=%d,stay_check_state_cnt=%d,goto_lock_cnt=%d,goto_release_cnt=%d,stay_release_state_cnt=%d\n", - pDM_DigTable->rx_gain_min_check_state[is_high_low_sel], - pDM_DigTable->stay_check_state_cnt[is_high_low_sel], - pDM_DigTable->goto_lock_state_cnt[is_high_low_sel], - pDM_DigTable->goto_release_state_cnt[is_high_low_sel], - pDM_DigTable->stay_release_state_cnt[is_high_low_sel])); - - ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, - ("rx_gain_min=0x%x\n", rx_gain_min)); - - return rx_gain_min; - -} - -void -phydm_tdma_dig_timers( - IN PVOID pDM_VOID, - u8 state - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - -// if (pDM_Odm->original_dig_restore) - { - if (state == INIT_TDMA_DIG_TIMMER) { - ODM_InitializeTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer), - (RT_TIMER_CALL_BACK)phydm_tdma_dig_call_back, NULL, "phydm_tdma_dig_timer"); - } else if (state == CANCEL_TDMA_DIG_TIMMER) { - ODM_CancelTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer)); - } else if (state == RELEASE_TDMA_DIG_TIMMER) { - ODM_ReleaseTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer)); - } - } -} - -void -phydm_tdma_low_dig( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - // Common parameters - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte tdma_low_igi = pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]; - u1Byte DIG_MaxOfMin; - u1Byte tdma_low_dym_min; - u1Byte dm_dig_max, dm_dig_min; - u1Byte offset; - u1Byte rssi_min = pDM_Odm->RSSI_Min; - u1Byte igi_upper_rssi_min; - u4Byte dm_FA_thres[3]; - u4Byte TxTp = 0, RxTp = 0; - BOOLEAN bDFSBand = FALSE; - BOOLEAN bPerformance = TRUE; - BOOLEAN DIG_GoUpCheck = TRUE; - u1Byte step_size[3] = {0}; - - if(odm_DigAbort(pDM_Odm) == TRUE) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("%s ==>\n",__FUNCTION__)); - - step_size[2] = 2; - step_size[1] = 2; - step_size[0] = 2; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", - step_size[0], step_size[1], step_size[2])); - - //1 Mode decision - - bPerformance = TRUE; - - //1 Boundary Decision - { - dm_dig_max = DM_DIG_MAX_AP_COVERAGR; - dm_dig_min = DM_DIG_MIN_AP_COVERAGE; - DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; - - /* Modify lower bound for DFS band */ - if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || - ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) - ) { - bDFSBand = TRUE; - if (*pDM_Odm->pBandWidth == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS+2; - else - dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("In DFS band\n")); - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("abs UB=0x%x,LB=0x%x\n", dm_dig_max, dm_dig_min)); - - //1 Adjust boundary by RSSI - if(pDM_Odm->bLinked && bPerformance) - { - //2 Modify DIG upper bound - - offset = 15; - - igi_upper_rssi_min = rssi_min + offset; - - /*rx_gain_range_max*/ - if((igi_upper_rssi_min) > dm_dig_max) - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = dm_dig_max; - else if((igi_upper_rssi_min) < dm_dig_min) - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = dm_dig_min; - else - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = igi_upper_rssi_min; - - if (bDFSBand) - { - tdma_low_dym_min = dm_dig_min; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("DFS band: Force LB to 0x%x after link\n", dm_dig_min)); - } else { - tdma_low_dym_min = dm_dig_min; - } - } - else - { - if(bPerformance && bDFSBand) - { - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, - ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE])); - } - else - { - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; - } - tdma_low_dym_min = dm_dig_min; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("tdma_rx_gain_max=0x%x, tdma_low_dym_min=0x%x\n", - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], tdma_low_dym_min)); - - //1 Modify DIG lower bound, deal with abnormal case - //2 Abnormal false alarm case - if(!pDM_Odm->bLinked) - { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_low_dym_min; - } - else { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] - = phydm_rx_gain_min_check(pDM_Odm, tdma_low_dym_min, tdma_low_igi, pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE], TDMA_DIG_LOW_STATE); - } - - //2 Abnormal lower bound case - /*tdma_high_rx_gain_min*/ - if(pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] > pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]) - { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Abnrormal tdma_rx_gain_min: force to 0x%x\n\n", - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE])); - } - - //1 False alarm threshold decision - odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, - ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", - dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - //1 Adjust initial gain by false alarm - if(pDM_Odm->bLinked && bPerformance) - { - //2 After link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); - tdma_low_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_low_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_LOW_STATE); - - } else { - //2 Before link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Adjust IGI before link\n")); - - tdma_low_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_low_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_LOW_STATE); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, - ("before check igi by ULbond, tdma_low_igi=0x%x\n\n", tdma_low_igi)); - - //1 Check initial gain by upper/lower bound - pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] = phydm_igi_chkby_upper_lower_bond(tdma_low_igi, pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, - ("ULbond,tdma_rx_gain_max=0x%x, tdma_rx_gain_min=0x%x\n", - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, - ("after ULbond check, tdma_igi=0x%x\n", - pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] - )); - - //1 Update status - - if (pDM_Odm->force_low_igi == 0xff) - ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]); - else - ODM_Write_DIG(pDM_Odm, pDM_Odm->force_low_igi); -} - - - -VOID -phydm_tdma_high_dig( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - // Common parameters - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte tdma_high_igi = pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE]; - u1Byte DIG_MaxOfMin; - u1Byte tdma_high_dym_min; - u1Byte dm_dig_max, dm_dig_min; - u1Byte offset; - u1Byte rssi_min = pDM_Odm->RSSI_Min; - u1Byte igi_upper_rssi_min; - u4Byte dm_FA_thres[3]; - u4Byte TxTp = 0, RxTp = 0; - BOOLEAN bDFSBand = FALSE; - BOOLEAN bPerformance = TRUE; - BOOLEAN DIG_GoUpCheck = TRUE; - u1Byte step_size[3] = {0}; - - if(odm_DigAbort(pDM_Odm) == TRUE) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("%s ==>\n\n",__FUNCTION__)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("tdma_high_igi=0x%x\n", tdma_high_igi)); - - step_size[2] = 2; - step_size[1] = 2; - step_size[0] = 2; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", - step_size[0], step_size[1], step_size[2])); - - //1 Mode decision - - bPerformance = TRUE; - - //1 Boundary Decision - { - if(!bPerformance) - { - dm_dig_max = DM_DIG_MAX_AP_COVERAGR; - dm_dig_min = DM_DIG_MIN_AP_COVERAGE; - DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; - } - else - { - if (pDM_Odm->RFType == ODM_1T1R) - dm_dig_max = DM_DIG_MAX_AP - 6; - else - dm_dig_max = 0x50; - - if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && (pDM_Odm->SupportICType & ODM_RTL8814A)) /* for 2G 8814 */ - dm_dig_min = 0x1c; - else if (pDM_Odm->SupportICType & ODM_RTL8197F) /*refine by YuChen 20160815 asked by RF Arthur*/ - dm_dig_min = 0x1e; - else - dm_dig_min = DM_DIG_MIN_AP; - - DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; - } - - //4 TX2path - if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) - dm_dig_max = 0x2A; - -#if RTL8192E_SUPPORT -#ifdef HIGH_POWER_EXT_LNA - if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) - dm_dig_max = 0x42; -#endif -#endif - /* Modify lower bound for DFS band */ - if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || - ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - && phydm_dfs_master_enabled(pDM_Odm) == TRUE - #endif - ) { - bDFSBand = TRUE; - if (*pDM_Odm->pBandWidth == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS+2; - else - dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("====== In DFS band ======\n")); - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); - - //1 Adjust boundary by RSSI - if(pDM_Odm->bLinked && bPerformance) - { - //2 Modify DIG upper bound - - //offset = 15; - - offset = pDM_Odm->rssi_to_igi_upper_offset; - - igi_upper_rssi_min = rssi_min + offset; - - /*tdma_high_rx_gain_max*/ - if((igi_upper_rssi_min) > dm_dig_max) - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = dm_dig_max; - else if((igi_upper_rssi_min) < dm_dig_min) - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = dm_dig_min; - else - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = igi_upper_rssi_min; - - if (bDFSBand) - { - tdma_high_dym_min = dm_dig_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } else { - /*tdma_high_dym_min(tdma_high_rx_gain_min)*/ - if(rssi_min < dm_dig_min) - tdma_high_dym_min = dm_dig_min; - else { - tdma_high_dym_min = (pDM_Odm->tdma_dig_turbo == 1) ? rssi_min : dm_dig_min; - } - } - } - else - { - if(bPerformance && bDFSBand) - { - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = 0x28; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] )); - } - else - { - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = DM_DIG_MAX_OF_MIN; - } - tdma_high_dym_min = dm_dig_min; - } - - //1 Force Lower Bound for AntDiv - if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) - { - if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { - if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) { - tdma_high_dym_min = DIG_MaxOfMin; - } - else { - tdma_high_dym_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Antenna diversity case: Force lower bound to 0x%x\n", - tdma_high_dym_min)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Antenna diversity case: RSSI_max=0x%x\n", - pDM_DigTable->AntDiv_RSSI_max)); - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("tdma_high_rx_gain_max=0x%x, tdma_high_dym_min = 0x%x\n", - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , tdma_high_dym_min)); - - //1 Modify DIG lower bound, deal with abnormal case - //2 Abnormal false alarm case - if(!pDM_Odm->bLinked) - { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_high_dym_min; - } - else { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] - = phydm_rx_gain_min_check(pDM_Odm, tdma_high_dym_min, tdma_high_igi, pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE], TDMA_DIG_HIGH_STATE); - } - - //2 Abnormal lower bound case - /*tdma_high_rx_gain_min*/ - if(pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] > pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] ) - { - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] ; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Abnrormal tdma_high_rx_gain_min: force to 0x%x\n\n", - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE])); - } - - //1 False alarm threshold decision - odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("False alarm threshold = %d, %d, %d \n\n", - dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - //1 Adjust initial gain by false alarm - if(pDM_Odm->bLinked && bPerformance) - { - //2 After link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); - - tdma_high_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_high_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_HIGH_STATE); - } else { - //2 Before link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); - - tdma_high_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_high_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_HIGH_STATE); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("before check igi by ULbond, tdma_high_igi=0x%x\n\n",tdma_high_igi)); - - //1 Check initial gain by upper/lower bound - pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE] = phydm_igi_chkby_upper_lower_bond(tdma_high_igi, pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("ULbond, tdma, high_rx_gain_max=0x%x high_rx_gain_min=0x%x\n", - pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , - pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("after ULbond check,tdma_high_igi=0x%x\n", pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE])); - -} - -void -phydm_tdma_dig_timer_check( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if ((odm_DigAbort(pDM_Odm) == TRUE) || (pDM_Odm->original_dig_restore == 1)) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, - ("tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d, tdma_dig_timer_ms=%d\n", - pDM_DigTable->tdma_dig_cnt, - pDM_DigTable->pre_tdma_dig_cnt, - pDM_Odm->tdma_dig_timer_ms)); - - if((pDM_DigTable->tdma_dig_cnt == 0) || (pDM_DigTable->tdma_dig_cnt == pDM_DigTable->pre_tdma_dig_cnt)) { - - if(ODMPTR->SupportAbility & ODM_BB_DIG) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, - ("\ntdma dig timer Check fail, restart tdma_dig_timer!\n\n")); - - ODM_SetTimer(pDM_Odm, &pDM_DigTable->phydm_tdma_dig_timer, pDM_Odm->tdma_dig_timer_ms); - } - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, ("Check pass, update pre_tdma_dig_cnt\n")); - - pDM_DigTable->pre_tdma_dig_cnt = pDM_DigTable->tdma_dig_cnt; -} - -void -phydm_tdma_dig_call_back( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte reg_c50; - u1Byte total_state_number = pDM_Odm->total_state_number; - - if((odm_DigAbort(pDM_Odm) == TRUE) || (pDM_Odm->original_dig_restore == TRUE)) - return; - - // prevent dumb - if((total_state_number == 0) || (total_state_number == 1)) { - pDM_Odm->total_state_number = 2; - total_state_number = pDM_Odm->total_state_number; - } - - reg_c50 = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); - - pDM_DigTable->tdma_dig_state = (pDM_DigTable->tdma_dig_cnt % total_state_number); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, - ("tdma_dig_state=%d, regc50=0x%x, tdma_high_igi=0x%x, tdma_low_igi=0x%x\n", - pDM_DigTable->tdma_dig_state, - reg_c50, - pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE], - pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE])); - - pDM_DigTable->tdma_dig_cnt++; - - if (pDM_DigTable->tdma_dig_state == 1) { - - if (pDM_Odm->force_high_igi == 0xff) - ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE]); - else - ODM_Write_DIG(pDM_Odm, pDM_Odm->force_high_igi); - } else if (pDM_DigTable->tdma_dig_state == 0) { - - if (pDM_Odm->force_low_igi == 0xff) - ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]); - else - ODM_Write_DIG(pDM_Odm, pDM_Odm->force_low_igi); - } - phydm_TDMA_FalseAlarmCounterCheck(pDM_Odm); - ODM_SetTimer(pDM_Odm, &pDM_DigTable->phydm_tdma_dig_timer, pDM_Odm->tdma_dig_timer_ms); -} - -VOID -phydm_TDMA_FalseAlarmCounterCheck( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - BOOLEAN one_sec_dump = pDM_DigTable->one_sec_dump; - u1Byte total_state_number = pDM_Odm->total_state_number; - u1Byte tdma_dig_state = pDM_DigTable->tdma_dig_state; - u1Byte i = 0; - u4Byte tdma_dig_block_period_ms = pDM_Odm->tdma_dig_timer_ms * total_state_number; - - /*caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms, or FA will be fewer.*/ - u4Byte tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms; - /*tdma_dig_state == 1, collect L-state FA, else, collect H-state FA*/ - bool is_high_low_sel = (tdma_dig_state == TDMA_DIG_HIGH_STATE)? 0: 1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, - ("tdma_dig_state=%d,tdma_dig_block_cnt=%d,one_sec_dump=%d,tdma_dig_block_cnt_thd=%d\n", - tdma_dig_state, - pDM_DigTable->tdma_dig_block_cnt, - pDM_DigTable->one_sec_dump, - tdma_dig_block_cnt_thd - )); - - if (tdma_dig_state == 0) { - - odm_FalseAlarmCounterStatistics(pDM_Odm); - /*collect to high/low FA by is_high_low_sel*/ - odm_FalseAlarmCounterAcc(pDM_Odm, one_sec_dump, is_high_low_sel); - odm_FalseAlarmCounterReset(pDM_Odm); - - if (one_sec_dump) { /*1sec H-state FA collect end*/ - - phydm_NoisyDetection(pDM_Odm); - odm_CCKPacketDetectionThresh(pDM_Odm); - // tdma dig - phydm_tdma_high_dig(pDM_Odm); - phydm_tdma_low_dig(pDM_Odm); - - for(i=0;i<=1;i++) - odm_FalseAlarmCounterAccReset(pDM_Odm, i); - pDM_DigTable->one_sec_dump = 0; - pDM_DigTable->tdma_dig_block_cnt = 0; - } - pDM_DigTable->tdma_dig_block_cnt++; - - /*1sec dump decision*/ - if (pDM_DigTable->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd){ - pDM_DigTable->one_sec_dump = 1; /*collect FA till this block end*/ - } - }else if (tdma_dig_state == 1) { - odm_FalseAlarmCounterStatistics(pDM_Odm); - /*collect to high/low FA by is_high_low_sel*/ - odm_FalseAlarmCounterAcc(pDM_Odm, one_sec_dump, is_high_low_sel); - odm_FalseAlarmCounterReset(pDM_Odm); - } -} - -VOID -odm_FalseAlarmCounterAcc( - IN PVOID pDM_VOID, - IN BOOLEAN one_sec_dump_en, - bool is_high_low_sel - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - PFALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc = &(pDM_Odm->FalseAlmCnt_Acc); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; -// u4Byte ret_value; - u8 one_sec_numerator, one_sec_denumerator; - u8 total_state_number = pDM_Odm->total_state_number; - u32 Cnt_CCA_all_1sec, Cnt_all_1sec; - - FalseAlmCnt_Acc->Cnt_Parity_Fail[is_high_low_sel] += FalseAlmCnt->Cnt_Parity_Fail; - FalseAlmCnt_Acc->Cnt_Rate_Illegal[is_high_low_sel] += FalseAlmCnt->Cnt_Rate_Illegal; - FalseAlmCnt_Acc->Cnt_Crc8_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Crc8_fail; - FalseAlmCnt_Acc->Cnt_Mcs_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Mcs_fail; - FalseAlmCnt_Acc->Cnt_Ofdm_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Ofdm_fail; -// FalseAlmCnt_Acc->Cnt_Ofdm_fail_pre += FalseAlmCnt->Cnt_Parity_Fail; - FalseAlmCnt_Acc->Cnt_Cck_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Cck_fail; - FalseAlmCnt_Acc->Cnt_all[is_high_low_sel] += FalseAlmCnt->Cnt_all; -// FalseAlmCnt_Acc->Cnt_all_pre += FalseAlmCnt->Cnt_all_pre; - FalseAlmCnt_Acc->Cnt_Fast_Fsync[is_high_low_sel] += FalseAlmCnt->Cnt_Fast_Fsync; - FalseAlmCnt_Acc->Cnt_SB_Search_fail[is_high_low_sel] += FalseAlmCnt->Cnt_SB_Search_fail; - FalseAlmCnt_Acc->Cnt_OFDM_CCA[is_high_low_sel] += FalseAlmCnt->Cnt_OFDM_CCA; - FalseAlmCnt_Acc->Cnt_CCK_CCA[is_high_low_sel] += FalseAlmCnt->Cnt_CCK_CCA; - FalseAlmCnt_Acc->Cnt_CCA_all[is_high_low_sel] += FalseAlmCnt->Cnt_CCA_all; -// FalseAlmCnt_Acc->Cnt_BW_USC += FalseAlmCnt->Cnt_BW_USC; -// FalseAlmCnt_Acc->Cnt_BW_LSC += FalseAlmCnt->Cnt_BW_LSC; - FalseAlmCnt_Acc->cnt_cck_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_cck_crc32_error; - FalseAlmCnt_Acc->cnt_cck_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_cck_crc32_ok; - FalseAlmCnt_Acc->cnt_ofdm_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_ofdm_crc32_error; - FalseAlmCnt_Acc->cnt_ofdm_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_ofdm_crc32_ok; - FalseAlmCnt_Acc->cnt_ht_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_ht_crc32_error; - FalseAlmCnt_Acc->cnt_ht_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_ht_crc32_ok; - FalseAlmCnt_Acc->cnt_vht_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_vht_crc32_error; - FalseAlmCnt_Acc->cnt_vht_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_vht_crc32_ok; - FalseAlmCnt_Acc->cnt_crc32_error_all[is_high_low_sel] += FalseAlmCnt->cnt_crc32_error_all; - FalseAlmCnt_Acc->cnt_crc32_ok_all[is_high_low_sel] += FalseAlmCnt->cnt_crc32_ok_all; - - if(one_sec_dump_en == 1) { - - if(is_high_low_sel == TDMA_DIG_HIGH_STATE) { - one_sec_numerator = total_state_number; - one_sec_denumerator = total_state_number-1; - } else { - one_sec_numerator = total_state_number; - one_sec_denumerator = 1; - } - FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_all[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; - FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_CCA_all[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; - FalseAlmCnt_Acc->Cnt_Cck_fail_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_Cck_fail[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; - FalseAlmCnt_Acc->Cnt_Ofdm_fail_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_Ofdm_fail[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; - - Cnt_all_1sec = FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]; - Cnt_CCA_all_1sec = FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel]; - - if (Cnt_CCA_all_1sec != 0) - FalseAlmCnt_Acc->fa_cca_ratio[is_high_low_sel] = (FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]*100) / FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel]; - else - FalseAlmCnt_Acc->fa_cca_ratio[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]; - - FalseAlmCnt_Acc->is_fa_bigger_cca[is_high_low_sel] = (Cnt_all_1sec > Cnt_CCA_all_1sec) ? 1 : 0; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, - ("[%s] ==> tdma_dig_state=%d,one_sec_dump_en=%d,is_high_low_sel=%d,Cnt_all=%d,Cnt_all_1sec=%d\n\n", - __FUNCTION__, - pDM_DigTable->tdma_dig_state, - one_sec_dump_en, - is_high_low_sel, - FalseAlmCnt_Acc->Cnt_all[is_high_low_sel], - FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel] - )); - - -} - -VOID -odm_FalseAlarmCounterAccReset( - IN PVOID pDM_VOID, - u8 high_low_idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc = &(pDM_Odm->FalseAlmCnt_Acc); - - //memset(FalseAlmCnt_Acc, 0, sizeof(pDM_Odm->FalseAlmCnt_Acc)); - - // Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump do NOT need to be reset - - FalseAlmCnt_Acc->Cnt_Parity_Fail[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_Rate_Illegal[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_Crc8_fail[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_Mcs_fail[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_Ofdm_fail[high_low_idx] = 0; -// FalseAlmCnt_Acc->Cnt_Ofdm_fail_pre = 0; - FalseAlmCnt_Acc->Cnt_Cck_fail[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_all[high_low_idx] = 0; -// FalseAlmCnt_Acc->Cnt_all_pre = 0; - FalseAlmCnt_Acc->Cnt_Fast_Fsync[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_SB_Search_fail[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_OFDM_CCA[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_CCK_CCA[high_low_idx] = 0; - FalseAlmCnt_Acc->Cnt_CCA_all[high_low_idx] = 0; -// FalseAlmCnt_Acc->Cnt_BW_USC = 0; -// FalseAlmCnt_Acc->Cnt_BW_LSC = 0; - FalseAlmCnt_Acc->cnt_cck_crc32_error[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_cck_crc32_ok[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_ofdm_crc32_error[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_ofdm_crc32_ok[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_ht_crc32_error[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_ht_crc32_ok[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_vht_crc32_error[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_vht_crc32_ok[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_crc32_error_all[high_low_idx] = 0; - FalseAlmCnt_Acc->cnt_crc32_ok_all[high_low_idx] = 0; - -} - - -#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) - -u1Byte -phydm_dig_current_igi_by_fa_th( - IN PVOID pDM_VOID, - u1Byte CurrentIGI, - pu4Byte dm_FA_thres, - pu1Byte step_size, - bool DIG_GoUpCheck, - u1Byte is_high_low_sel - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - PFALSE_ALARM_STATISTICS_ACC pFalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); - u1Byte tdma_dig_state = pDM_DigTable->tdma_dig_state; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("%s ==>\n",__FUNCTION__)); - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if ((pDM_Odm->original_dig_restore == 0) && (is_high_low_sel != NORMAL_DIG)) { - if((pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] > dm_FA_thres[2])) - CurrentIGI = CurrentIGI + step_size[2]; - else if ((pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] > dm_FA_thres[1])) - CurrentIGI = CurrentIGI + step_size[1]; - else if(pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] < dm_FA_thres[0]) - CurrentIGI = CurrentIGI - step_size[0]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("tdma_dig_state=%d,is_high_low_sel=%d\n", - tdma_dig_state, - is_high_low_sel)); - } else -#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) - { - if((pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + step_size[2]; - else if ((pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + step_size[1]; - else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) - CurrentIGI = CurrentIGI - step_size[0]; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, - ("final igi=0x%x,fa=%d,th0=%d th1=%d th2=%d\n", - CurrentIGI, - pFalseAlmCnt->Cnt_all, - dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - return CurrentIGI; - -} - -VOID -odm_DIGbyRSSI_LPS( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - - u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C - u1Byte CurrentIGI=pDM_Odm->RSSI_Min; - - if(odm_DigAbort(pDM_Odm) == TRUE) - return; - - CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS()==>\n")); - - // Using FW PS mode to make IGI - //Adjust by FA in LPS MODE - if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) - CurrentIGI = CurrentIGI+4; - else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) - CurrentIGI = CurrentIGI+2; - else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) - CurrentIGI = CurrentIGI-2; - - - //Lower bound checking - - //RSSI Lower bound check - if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) - RSSI_Lower =(pDM_Odm->RSSI_Min-10); - else - RSSI_Lower =DM_DIG_MIN_NIC; - - //Upper and Lower Bound checking - if(CurrentIGI > DM_DIG_MAX_NIC) - CurrentIGI = DM_DIG_MAX_NIC; - else if(CurrentIGI < RSSI_Lower) - CurrentIGI = RSSI_Lower; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pFalseAlmCnt->Cnt_all = %d\n",pFalseAlmCnt->Cnt_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pDM_Odm->RSSI_Min = %d\n",pDM_Odm->RSSI_Min)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): CurrentIGI = 0x%x\n",CurrentIGI)); - - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); -#endif -} - - -VOID -odm_FalseAlarmCounterStatistics( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - #if (PHYDM_LA_MODE_SUPPORT == 1) - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - #endif - u4Byte ret_value; - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -//Mark there, and check this in odm_DMWatchDog -#if 0 //(DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) - return; -#endif -#endif - - if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics()======>\n")); - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - odm_FalseAlarmCounterRegHold(pDM_Odm); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); - FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); - FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); - FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); - FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); - FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); - FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); - FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); - - FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + - FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + - FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; - - /* read CCK CRC32 counter */ - FalseAlmCnt->cnt_cck_crc32_error = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_cck_crc32_ok= ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_OK_CNT_11N, bMaskDWord); - - /* read OFDM CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; - - /* read HT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; - - /* read VHT CRC32 counter */ - FalseAlmCnt->cnt_vht_crc32_error = 0; - FalseAlmCnt->cnt_vht_crc32_ok= 0; - -#if (RTL8188E_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); - FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); - FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); - } -#endif - - { - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); - FalseAlmCnt->Cnt_Cck_fail = ret_value; - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); - FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); - FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); - } - - FalseAlmCnt->Cnt_all_pre = FalseAlmCnt->Cnt_all; - - FalseAlmCnt->time_fa_all = (FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail) * 12 + - (FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal) * 28 + - FalseAlmCnt->Cnt_Crc8_fail * 36 + - FalseAlmCnt->Cnt_Mcs_fail * 32 + - FalseAlmCnt->Cnt_Cck_fail * 80; - - FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + - FalseAlmCnt->Cnt_SB_Search_fail + - FalseAlmCnt->Cnt_Parity_Fail + - FalseAlmCnt->Cnt_Rate_Illegal + - FalseAlmCnt->Cnt_Crc8_fail + - FalseAlmCnt->Cnt_Mcs_fail + - FalseAlmCnt->Cnt_Cck_fail); - - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; - - /* Get debug port 0 */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x0); - FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord); - - /* Get EDCCA flag */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); - FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, BIT30); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", - FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", - FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", - FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); - } -#endif - -#if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - u4Byte CCKenable; - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11AC, bMaskDWord); - FalseAlmCnt->Cnt_Fast_Fsync = ((ret_value & 0xffff0000) >> 16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11AC, bMaskDWord); - FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11AC, bMaskDWord); - FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff); - FalseAlmCnt->Cnt_Rate_Illegal = ((ret_value & 0xffff0000) >> 16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11AC, bMaskDWord); - FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff); - FalseAlmCnt->Cnt_Mcs_fail = ((ret_value & 0xffff0000) >> 16); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE5_11AC, bMaskDWord); - FalseAlmCnt->cnt_crc8_fail_vht = (ret_value & 0xffff); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE6_11AC, bMaskDWord); - FalseAlmCnt->cnt_mcs_fail_vht = (ret_value & 0xffff); - - - /* read OFDM FA counter */ - FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); - - /* Read CCK FA counter */ - FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); - - /* read CCK/OFDM CCA counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11AC, bMaskDWord); - FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->Cnt_CCK_CCA = ret_value & 0xffff; - - /* read CCK CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_cck_crc32_ok= ret_value & 0xffff; - - /* read OFDM CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; - - /* read HT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; - - /* read VHT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_VHT_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_vht_crc32_ok= ret_value & 0xffff; - -#if (RTL8881A_SUPPORT==1) - /* For 8881A */ - if(pDM_Odm->SupportICType == ODM_RTL8881A) - { - u4Byte Cnt_Ofdm_fail_temp = 0; - - if(FalseAlmCnt->Cnt_Ofdm_fail >= FalseAlmCnt->Cnt_Ofdm_fail_pre) - { - Cnt_Ofdm_fail_temp = FalseAlmCnt->Cnt_Ofdm_fail_pre; - FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; - FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Ofdm_fail - Cnt_Ofdm_fail_temp; - } - else - FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail_pre)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail_pre=%d\n", Cnt_Ofdm_fail_temp)); - - /* Reset FA counter by enable/disable OFDM */ - if(FalseAlmCnt->Cnt_Ofdm_fail_pre >= 0x7fff) - { - // reset OFDM - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,1); - FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Reset false alarm counter\n")); - } - } -#endif - CCKenable = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28); - if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G) - { - FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_CCK_CCA + FalseAlmCnt->Cnt_OFDM_CCA; - } - else - { - FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail; - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA; - } - - #if (PHYDM_LA_MODE_SUPPORT == 1) - if (AdcSmp->ADCSmpState == ADCSMP_STATE_IDLE) - #endif - { - /* Get debug port 0 */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x0); - FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord); - - /* Get EDCCA flag */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); - FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, BIT30); - } - } -#endif - - odm_FalseAlarmCounterRegReset(pDM_Odm); - - FalseAlmCnt->time_fa_all = (FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail) * 12 + - (FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal) * 28 + - (FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->cnt_crc8_fail_vht + FalseAlmCnt->cnt_mcs_fail_vht) * 36 + - FalseAlmCnt->Cnt_Mcs_fail * 32 + - FalseAlmCnt->Cnt_Cck_fail * 80; - - FalseAlmCnt->cnt_crc32_error_all = FalseAlmCnt->cnt_vht_crc32_error + FalseAlmCnt->cnt_ht_crc32_error + FalseAlmCnt->cnt_ofdm_crc32_error + FalseAlmCnt->cnt_cck_crc32_error; - FalseAlmCnt->cnt_crc32_ok_all = FalseAlmCnt->cnt_vht_crc32_ok + FalseAlmCnt->cnt_ht_crc32_ok + FalseAlmCnt->cnt_ofdm_crc32_ok + FalseAlmCnt->cnt_cck_crc32_ok; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_OFDM_CCA=%d\n", FalseAlmCnt->Cnt_OFDM_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCK_CCA=%d\n", FalseAlmCnt->Cnt_CCK_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCA_all=%d\n", FalseAlmCnt->Cnt_CCA_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): CCK CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_cck_crc32_error, FalseAlmCnt->cnt_cck_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): OFDM CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ofdm_crc32_error, FalseAlmCnt->cnt_ofdm_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): HT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ht_crc32_error, FalseAlmCnt->cnt_ht_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): VHT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_vht_crc32_error, FalseAlmCnt->cnt_vht_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_crc32_error_all, FalseAlmCnt->cnt_crc32_ok_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): dbg port 0x0 = 0x%x, EDCCA = %d\n\n", FalseAlmCnt->dbg_port0, FalseAlmCnt->edcca_flag)); - -} - -// reset FA TSF also -VOID -odm_FalseAlarmCounterReset( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - prtl8192cd_priv priv = pDM_Odm->priv; - u4Byte TSF; - - memset(FalseAlmCnt, 0, sizeof(pDM_Odm->FalseAlmCnt)); - odm_FalseAlarmCounterRegReset(pDM_Odm); -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if(pDM_DigTable->tdma_dig_state != 1) - pDM_DigTable->fa_acc_1sec_tsf = 0; - else -#endif - pDM_DigTable->fa_acc_1sec_tsf = pDM_DigTable->fa_acc_1sec_tsf; - - GET_HAL_INTERFACE(priv)->GetHwRegHandler(priv, HW_VAR_TSF_TIMER, (pu1Byte)&TSF); - pDM_DigTable->fa_start_tsf = TSF; - pDM_DigTable->fa_end_tsf = TSF; - -} - -VOID -odm_FalseAlarmCounterRegReset( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - if (pDM_Odm->SupportICType >= ODM_RTL8188E) { - /*reset false alarm counter registers*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); - - /*update ofdm counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /*update page C counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /*update page D counter*/ - - /*reset CCK CCA counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); - - /*reset CCK FA counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); - - /*reset CRC32 counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 0); - } - } -#endif // #if (ODM_IC_11N_SERIES_SUPPORT == 1) - -#if (ODM_IC_11AC_SERIES_SUPPORT == 1) - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - /* reset OFDM FA coutner */ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); - - /* reset CCK FA counter */ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); - - /* reset CCA counter */ - ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 0); - } -#endif // #if (ODM_IC_11AC_SERIES_SUPPORT == 1) - -} - -VOID -odm_FalseAlarmCounterRegHold( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //hold ofdm counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter - - //hold cck counter - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); - } -} - -//3============================================================ -//3 CCK Packet Detect Threshold -//3============================================================ - -VOID -odm_PauseCCKPacketDetection( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte CCKPDThreshold -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection()=========> level = %d\n", pause_level)); - - if ((pDM_DigTable->pause_cckpd_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: SupportAbility ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); - return; - } - - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseCCKPacketDetection(): Return: Wrong pause level !!\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], - pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); - - switch (PauseType) { - /* Pause CCK Packet Detection Threshold */ - case PHYDM_PAUSE: - { - /* Disable CCK PD */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_CCK_PD)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Pause CCK packet detection threshold !!\n")); - - /* Backup original CCK PD threshold decided by CCK PD mechanism */ - if (pDM_DigTable->pause_cckpd_level == 0) { - pDM_DigTable->CCKPDBackup = pDM_DigTable->CurCCK_CCAThres; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseCCKPacketDetection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup, CCKPDThreshold)); - } - - /* Update pause level */ - pDM_DigTable->pause_cckpd_level = (pDM_DigTable->pause_cckpd_level | BIT(pause_level)); - - /* Record CCK PD threshold */ - pDM_DigTable->pause_cckpd_value[pause_level] = CCKPDThreshold; - - /* Write new CCK PD threshold */ - if (BIT(pause_level + 1) > pDM_DigTable->pause_cckpd_level) { - ODM_Write_CCK_CCA_Thres(pDM_Odm, CCKPDThreshold); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): CCKPD of higher level = 0x%x\n", CCKPDThreshold)); - } - break; - } - /* Resume CCK Packet Detection Threshold */ - case PHYDM_RESUME: - { - /* check if the level is illegal or not */ - if ((pDM_DigTable->pause_cckpd_level & (BIT(pause_level))) != 0) { - pDM_DigTable->pause_cckpd_level = pDM_DigTable->pause_cckpd_level & (~(BIT(pause_level))); - pDM_DigTable->pause_cckpd_value[pause_level] = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Resume CCK PD !!\n")); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong resume level !!\n")); - break; - } - - /* Resume DIG */ - if (pDM_DigTable->pause_cckpd_level == 0) { - /* Write backup IGI value */ - ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->CCKPDBackup); - /* pDM_DigTable->bIgnoreDIG = TRUE; */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write original CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup)); - - /* Enable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_CCK_PD); - break; - } - - if (BIT(pause_level) > pDM_DigTable->pause_cckpd_level) { - s1Byte max_level; - - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((pDM_DigTable->pause_cckpd_level & BIT(max_level)) > 0) - break; - } - - /* write CCKPD of lower level */ - ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->pause_cckpd_value[max_level]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write CCKPD (0x%x) of level (%d)\n", - pDM_DigTable->pause_cckpd_value[max_level], max_level)); - break; - } - break; - } - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong type !!\n")); - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], - pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); -} - - -VOID -odm_CCKPacketDetectionThresh( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - PFALSE_ALARM_STATISTICS_ACC FalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); -#endif - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte CurCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres, RSSI_thd = 35; - u1Byte pd_th = 0, cs_ration = 0; - BOOLEAN en_2rcca; - - en_2rcca = ((BOOLEAN)ODM_GetBBReg(pDM_Odm, 0xa2c, BIT(18)) && (BOOLEAN)ODM_GetBBReg(pDM_Odm, 0xa2c, BIT(22))); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//modify by Guo.Mingzhi 2011-12-29 - if (pDM_Odm->bDualMacSmartConcurrent == TRUE) -// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) - return; - if(pDM_Odm->bBtHsOperation) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); - ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); - return; - } -#endif - - if((!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD)) ||(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() return==========\n")); -#ifdef MCR_WIRELESS_EXTEND - ODM_Write_CCK_CCA_Thres(pDM_Odm, 0x43); -#endif - return; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pDM_Odm->ExtLNA) - return; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() ==========>\n")); - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - if(pDM_Odm->original_dig_restore == 0) { - if (pDM_DigTable->cckFaMa == 0xffffffff) - pDM_DigTable->cckFaMa = FalseAlmCntAcc->Cnt_Cck_fail_1sec[TDMA_DIG_HIGH_STATE]; - else - pDM_DigTable->cckFaMa = ((pDM_DigTable->cckFaMa<<1) + pDM_DigTable->cckFaMa + FalseAlmCntAcc->Cnt_Cck_fail_1sec[TDMA_DIG_HIGH_STATE]) >> 2; - } else -#endif - { - if (pDM_DigTable->cckFaMa == 0xffffffff) - pDM_DigTable->cckFaMa = FalseAlmCnt->Cnt_Cck_fail; - else - pDM_DigTable->cckFaMa = ((pDM_DigTable->cckFaMa<<1) + pDM_DigTable->cckFaMa + FalseAlmCnt->Cnt_Cck_fail) >> 2; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh(): CCK FA moving average = %d\n", pDM_DigTable->cckFaMa)); - - if (pDM_Odm->bLinked) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (pDM_Odm->RSSI_Min > (RSSI_thd + 14)) - CurCCK_CCAThres = 0xed; - else if (pDM_Odm->RSSI_Min > (RSSI_thd + 6)) - CurCCK_CCAThres = 0xdd; - else if (pDM_Odm->RSSI_Min > RSSI_thd) - CurCCK_CCAThres = 0xcd; - else if (pDM_Odm->RSSI_Min > 20) { - if (pDM_DigTable->cckFaMa > ((DM_DIG_FA_TH1>>1) + (DM_DIG_FA_TH1>>3))) - CurCCK_CCAThres = 0xcd; - else if (pDM_DigTable->cckFaMa < (DM_DIG_FA_TH0>>1)) - CurCCK_CCAThres = 0x83; - } else if (pDM_Odm->RSSI_Min > 7) - CurCCK_CCAThres = 0x83; - else - CurCCK_CCAThres = 0x40; -#else - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - if ((pDM_DigTable->CurIGValue > (0x24 + 14)) || (pDM_Odm->RSSI_Min > 26)) - CurCCK_CCAThres = 0xed; - else if ((pDM_DigTable->CurIGValue > (0x24 + 6)) || (pDM_Odm->RSSI_Min > 26)) - CurCCK_CCAThres = 0xdd; - else if ((pDM_DigTable->CurIGValue > 0x24) || (pDM_Odm->RSSI_Min > 20 && pDM_Odm->RSSI_Min <= 24)) - CurCCK_CCAThres = 0xcd; - else if ((pDM_DigTable->CurIGValue <= 0x24) || (pDM_Odm->RSSI_Min < 18)){ - if (pDM_DigTable->cckFaMa > 0x400) - CurCCK_CCAThres = 0x83; - else if (pDM_DigTable->cckFaMa < 0x200) - CurCCK_CCAThres = 0x40; - } - } else { - if (pDM_DigTable->CurIGValue > (0x24 + 14)) - CurCCK_CCAThres = 0xed; - else if (pDM_DigTable->CurIGValue > (0x24 + 6)) - CurCCK_CCAThres = 0xdd; - else if (pDM_DigTable->CurIGValue > 0x24) - CurCCK_CCAThres = 0xcd; - else { - if (pDM_DigTable->cckFaMa > 0x400) - CurCCK_CCAThres = 0x83; - else if (pDM_DigTable->cckFaMa < 0x200) - CurCCK_CCAThres = 0x40; - } - } -#endif - } else { - if (pDM_DigTable->cckFaMa > 0x400) - CurCCK_CCAThres = 0x83; - else if (pDM_DigTable->cckFaMa < 0x200) - CurCCK_CCAThres = 0x40; - } - - /*Add by Yu Chen 20160902, pd_th for 0xa0a, cs_ration for 0xaaa*/ - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - switch (CurCCK_CCAThres) { - case 0xed: - cs_ration = pDM_DigTable->aaa_default + AAA_BASE + AAA_STEP*2; - if (en_2rcca) {cs_ration = cs_ration - 5;} - pd_th = 0xd; - break; - - case 0xdd: - cs_ration = pDM_DigTable->aaa_default + AAA_BASE + AAA_STEP; - if (en_2rcca) {cs_ration = cs_ration - 4;} - pd_th = 0xd; - break; - - case 0xcd: - cs_ration = pDM_DigTable->aaa_default + AAA_BASE; - if (en_2rcca) {cs_ration = cs_ration - 3;} - pd_th = 0xd; - break; - - case 0x83: - cs_ration = pDM_DigTable->aaa_default + AAA_STEP; - if (en_2rcca) {cs_ration = cs_ration - 1;} - pd_th = 0x3; - break; - - case 0x40: - cs_ration = pDM_DigTable->aaa_default; - pd_th = 0x3; - break; - - default: - cs_ration = pDM_DigTable->aaa_default; - pd_th = 0x3; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cck pd use default\n")); - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s : cs_ration = 0x%x, pd_th = 0x%x\n", __func__, cs_ration, pd_th)); - - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ODM_SetBBReg(pDM_Odm, 0xa08, 0xf0000, pd_th); - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, cs_ration); - } else - ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() CurCCK_CCAThres = 0x%x\n", CurCCK_CCAThres)); -} - -VOID -ODM_Write_CCK_CCA_Thres( - IN PVOID pDM_VOID, - IN u1Byte CurCCK_CCAThres - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 - { - ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); - pDM_DigTable->cckFaMa = 0xffffffff; - } - pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; - pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; -} - -BOOLEAN -phydm_DIG_GoUpCheck( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte CurIGValue = pDM_DigTable->CurIGValue; - u1Byte max_DIG_cover_bond; - u1Byte current_IGI_MaxUp_resolution; - u1Byte rx_gain_range_max; - u1Byte i = 0; - - u4Byte total_NHM_cnt; - u4Byte DIG_cover_cnt; - u4Byte over_DIG_cover_cnt; - BOOLEAN ret = TRUE; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - - max_DIG_cover_bond = DM_DIG_MAX_AP - priv->pshare->rf_ft_var.dig_upcheck_initial_value; - current_IGI_MaxUp_resolution = CurIGValue + 6; - rx_gain_range_max = pDM_DigTable->rx_gain_range_max; - - phydm_getNHMresult(pDM_Odm); - - total_NHM_cnt = CCX_INFO->NHM_result[0] + CCX_INFO->NHM_result[1]; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Get NHM results*****\n")); - - if (total_NHM_cnt != 0) { - - /* CurIGValue < max_DIG_cover_bond - 6 */ - if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_0) { - DIG_cover_cnt = CCX_INFO->NHM_result[1]; - ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? TRUE : FALSE; - } - - /* (max_DIG_cover_bond - 6) <= CurIGValue < DM_DIG_MAX_AP */ - else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_1) { - over_DIG_cover_cnt = CCX_INFO->NHM_result[1]; - ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? TRUE : FALSE; - - if (!ret) { - /* update pDM_DigTable->rx_gain_range_max */ - pDM_DigTable->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", - pDM_DigTable->rx_gain_range_max)); - } - } - - /* CurIGValue > DM_DIG_MAX_AP, foolproof */ - else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_2) { - ret = TRUE; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n, current_IGI_MaxUp_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", - pDM_DigTable->DIG_GoUpCheck_Level, - current_IGI_MaxUp_resolution, - max_DIG_cover_bond, - pDM_DigTable->rx_gain_range_max, - ret)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_result = %d, %d, %d, %d\n", - CCX_INFO->NHM_result[0], CCX_INFO->NHM_result[1], CCX_INFO->NHM_result[2], CCX_INFO->NHM_result[3])); - - } - else - ret = TRUE; - - for (i = 0 ; i <= 10 ; i ++) { - CCX_INFO->NHM_th[i] = 0xFF; - } - - if (CurIGValue < max_DIG_cover_bond - 6){ - CCX_INFO->NHM_th[0] = 2 * (CurIGValue - priv->pshare->rf_ft_var.dig_upcheck_initial_value); - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_0; - } - else if (CurIGValue <= DM_DIG_MAX_AP) { - CCX_INFO->NHM_th[0] = 2 * max_DIG_cover_bond; - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_1; - } - /* CurIGValue > DM_DIG_MAX_AP, foolproof */ - else { - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_2; - ret = TRUE; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Set NHM settings*****\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n", - pDM_DigTable->DIG_GoUpCheck_Level)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_th = 0x%x, 0x%x, 0x%x\n", - CCX_INFO->NHM_th[0], CCX_INFO->NHM_th[1], CCX_INFO->NHM_th[2])); - - CCX_INFO->NHM_inexclude_cca = NHM_EXCLUDE_CCA; - CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; - CCX_INFO->NHM_period = 0xC350; - - phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); - phydm_NHMtrigger(pDM_Odm); -#endif - - return ret; -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -// <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) -VOID -odm_RFEControl( - IN PDM_ODM_T pDM_Odm, - IN u8Byte RSSIVal - ) -{ - PADAPTER Adapter = (PADAPTER)pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - static u1Byte TRSW_HighPwr = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n", - RSSIVal, TRSW_HighPwr, pHalData->RFEType )); - - if (pHalData->RFEType == 3) { - - pDM_Odm->RSSI_TRSW = RSSIVal; - - if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H) - { - TRSW_HighPwr = 1; // Switch to - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); // Set ANTSW=1/ANTSWB=0 for SW control - - } - else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L) - { - TRSW_HighPwr = 0; // Switched back - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0); // Set ANTSW=1/ANTSWB=0 for SW control - - } - } - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", - RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr)); -} - -VOID -odm_MPT_DIGWorkItemCallback( - IN PVOID pContext - ) -{ - PADAPTER Adapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_MPT_DIG(pDM_Odm); -} - -VOID -odm_MPT_DIGCallback( - PRT_TIMER pTimer -) -{ - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - - #if DEV_BUS_TYPE==RT_PCI_INTERFACE - #if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); - #else - ODM_MPT_DIG(pDM_Odm); - #endif - #else - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); - #endif - -} - -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -VOID -odm_MPT_DIGCallback( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); -#else - ODM_MPT_DIG(pDM_Odm); -#endif -} -#endif - -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) -VOID -odm_MPT_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurIGValue -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), CurIGValue); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - /* Set IGI value of CCK for new CCK AGC */ - if (pDM_Odm->cck_new_agc) { - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) - ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurIGValue>>1)); - } - -#endif - - if(pDM_Odm->RFType > ODM_1T1R) - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), CurIGValue); - - if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) - { - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_C,pDM_Odm), CurIGValue); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_D,pDM_Odm), CurIGValue); - } - - pDM_DigTable->CurIGValue = CurIGValue; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurIGValue = 0x%x\n", CurIGValue)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("pDM_Odm->RFType = 0x%x\n", pDM_Odm->RFType)); -} - -VOID -ODM_MPT_DIG( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte CurrentIGI = pDM_DigTable->CurIGValue; - u1Byte DIG_Upper = 0x40, DIG_Lower = 0x20; - u4Byte RXOK_cal; - u4Byte RxPWDBAve_final; - u1Byte IGI_A = 0x20, IGI_B = 0x20; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - #if ODM_FIX_2G_DIG - IGI_A = 0x22; - IGI_B = 0x24; - #endif - -#else - if (!(pDM_Odm->priv->pshare->rf_ft_var.mp_specific && pDM_Odm->priv->pshare->mp_dig_on)) - return; - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - DIG_Lower = 0x22; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType)); - -#if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) - if (*pDM_Odm->pBandType == ODM_BAND_5G || (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) // for 5G or 8814 -#else - if (1) // for both 2G/5G -#endif - { - odm_FalseAlarmCounterStatistics(pDM_Odm); - - RXOK_cal = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM; - RxPWDBAve_final = (RXOK_cal != 0)?pDM_Odm->RxPWDBAve/RXOK_cal:0; - - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->RxPWDBAve = 0; - pDM_Odm->MPDIG_2G = FALSE; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->Times_2G = 0; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", RXOK_cal)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", RxPWDBAve_final)); - - if (RXOK_cal >= 70 && RxPWDBAve_final <= 40) - { - if (CurrentIGI > 0x24) - odm_MPT_Write_DIG(pDM_Odm, 0x24); - } - else - { - if(pFalseAlmCnt->Cnt_all > 1000){ - CurrentIGI = CurrentIGI + 8; - } - else if(pFalseAlmCnt->Cnt_all > 200){ - CurrentIGI = CurrentIGI + 4; - } - else if (pFalseAlmCnt->Cnt_all > 50){ - CurrentIGI = CurrentIGI + 2; - } - else if (pFalseAlmCnt->Cnt_all < 2){ - CurrentIGI = CurrentIGI - 2; - } - - if (CurrentIGI < DIG_Lower ){ - CurrentIGI = DIG_Lower; - } - - if(CurrentIGI > DIG_Upper){ - CurrentIGI = DIG_Upper; - } - - odm_MPT_Write_DIG(pDM_Odm, CurrentIGI); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", - CurrentIGI, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail)); - } - } - else - { - if(pDM_Odm->MPDIG_2G == FALSE) - { - if((pDM_Odm->SupportPlatform & ODM_WIN) && !(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), IGI_A); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), IGI_B); - pDM_DigTable->CurIGValue = IGI_B; - } - else - odm_MPT_Write_DIG(pDM_Odm, IGI_A); - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->Times_2G++; - - if (pDM_Odm->Times_2G == 3) -#endif - { - pDM_Odm->MPDIG_2G = TRUE; - } - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8812) - odm_RFEControl(pDM_Odm, RxPWDBAve_final); -#endif - - ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700); -} -#endif - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - -void -phydm_lna_sat_chk_type2_init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; -// u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; - - u1Byte real_shift = pDM_Odm->total_bit_shift; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); - - pinfo->total_cnt_snr_statistic = 1 << real_shift; - pinfo->is_sm_done = TRUE; - pinfo->is_snr_done = FALSE; - pinfo->cur_snr_mean = 0; - pinfo->cur_snr_var = 0; - pinfo->cur_lower_snr_mean = 0; - pinfo->pre_snr_mean = 0; - pinfo->pre_snr_var = 0; - pinfo->pre_lower_snr_mean = 0; - pinfo->nxt_state = ORI_TABLE_MONITOR; - pinfo->pre_state = ORI_TABLE_MONITOR; - -} - -void -phydm_snr_collect( - IN PVOID pDM_VOID, - IN u8 rx_snr - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - if (pinfo->is_sm_done == TRUE) { - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); - - /* adapt only path-A for calculation */ - pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr; -// pinfo->sum_snr_statistic += rx_snr; - - if(pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr_statistic - 1)) { - pinfo->is_snr_done = TRUE; - pinfo->cnt_snr_statistic = 0; - } else { - pinfo->cnt_snr_statistic++; - } - } else { - return; - } -} - - -void -phydm_snr_data_processing( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - -// u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; - u1Byte real_shift = pDM_Odm->total_bit_shift; - u2Byte total_snr_cnt = pinfo->total_cnt_snr_statistic; - u2Byte total_loop_cnt = (total_snr_cnt - 1), i; - u4Byte temp; - u4Byte sum_snr_statistic = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("total_loop_cnt=%d\n", total_loop_cnt)); - - for(i = 0; (i <= total_loop_cnt); i++) { - - if (pDM_Odm->is_snr_detail_en) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("snr[%d]=%d\n", i, pinfo->snr_statistic[i])); - } - - sum_snr_statistic += pinfo->snr_statistic[i]; - - pinfo->snr_statistic_sqr[i] = - pinfo->snr_statistic[i] * pinfo->snr_statistic[i]; - } - - phydm_bubble_sort(pDM_Odm, pinfo->snr_statistic, pinfo->total_cnt_snr_statistic); - - /*update SNR's cur mean*/ - pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift); - - for(i = 0; (i <= total_loop_cnt); i++) { - - if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean) - temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean; - else - temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i]; - - pinfo->cur_snr_var += (temp*temp); - } -/* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("snr_higher_cnt=%d, snr_lower_cnt=%d\n", snr_higher_cnt, snr_lower_cnt)); -*/ - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("pinfo->cur_snr_var\n", pinfo->cur_snr_var)); - - /*update SNR's VAR*/ - pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift); - - /*acquire lower SNR's statistics*/ - temp = 0; - pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pDM_Odm->lwr_snr_ratio_bit_shift); - for(i = 0; i <= pinfo->cnt_lower_snr_statistic; i++) { - temp += pinfo->snr_statistic[i]; - } - - pinfo->cur_lower_snr_mean = temp >> (real_shift - pDM_Odm->lwr_snr_ratio_bit_shift); - - /*update cnt_lower_snr_statistic*/ - -} - - -bool -phydm_is_snr_improve( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; -// bool is_mean_improve = FALSE, is_var_improve = FALSE; - bool is_snr_improve; - u1Byte cur_state = pinfo->nxt_state; - u4Byte cur_mean = pinfo->cur_snr_mean; - u4Byte pre_mean = pinfo->pre_snr_mean; - u4Byte cur_lower_mean = pinfo->cur_lower_snr_mean; - u4Byte pre_lower_mean = pinfo->pre_lower_snr_mean; - u4Byte cur_var = pinfo->cur_snr_var; -// u4Byte pre_var = pinfo->pre_snr_var; -// u4Byte diff_var=0, diff_mean=0; - - /*special case, zero VAR, interference is gone*/ - if ((cur_state == SAT_TABLE_MONITOR) || (cur_state == ORI_TABLE_TRAINING)) { /*make sure pre_var is larger enough*/ - if (cur_mean >= pre_mean) { - if (cur_var == 0) - return TRUE; - } - } - - /*special case, mean degrade less than VAR improvement*/ -/* - if (cur_state == ORI_TABLE_MONITOR) { //make sure pre_var is larger enough - if (cur_mean < pre_mean) { - if (cur_var < pre_var) { - diff_mean = pre_mean - cur_mean; - diff_var = pre_var - cur_var; - return (diff_var > (2*diff_mean*diff_mean)) ? TRUE:FALSE; - } - } - } -*/ - - if (cur_lower_mean >= (pre_lower_mean + pDM_Odm->delta_snr_mean)) { - is_snr_improve = TRUE; - } else { - is_snr_improve = FALSE; - } - - /* condition refine, mean is bigger enough or VAR is smaller enough */ - /* 1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/ -/* - if (cur_mean > (pre_mean + pDM_Odm->delta_snr_mean)) { - is_mean_improve = TRUE; - is_var_improve = (cur_var <= pre_var + pDM_Odm->delta_snr_var) ? TRUE : FALSE; - - } else if (cur_var + pDM_Odm->delta_snr_var <= pre_var) { - is_var_improve = TRUE; - is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE; - } else { - return false; - } -*/ - return is_snr_improve; -} - -bool -phydm_is_snr_degrade( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; -// bool is_mean_dgrade = FALSE, is_var_degrade = FALSE; - u4Byte cur_lower_mean = pinfo->cur_lower_snr_mean; - u4Byte pre_lower_mean = pinfo->pre_lower_snr_mean; - bool is_degrade; - - if (cur_lower_mean <= (pre_lower_mean - pDM_Odm->delta_snr_mean)) { - is_degrade = TRUE; - } else { - is_degrade = FALSE; - } - -/* - is_mean_dgrade = (pinfo->cur_snr_mean + pDM_Odm->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE; - is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pDM_Odm->delta_snr_mean)) ? TRUE : FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n", - __FUNCTION__, - pinfo->cur_snr_mean, - pinfo->pre_snr_mean, - pinfo->cur_snr_var, - pinfo->pre_snr_var)); - - return (is_mean_dgrade & is_var_degrade); -*/ - return is_degrade; -} - -bool -phydm_is_large_var( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - bool is_large_var = (pinfo->cur_snr_var >= pDM_Odm->snr_var_thd) ? TRUE : FALSE; - - return is_large_var; -} - -void -phydm_update_pre_status( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean; - pinfo->pre_snr_mean = pinfo->cur_snr_mean; - pinfo->pre_snr_var = pinfo->cur_snr_var; -} - -void -phydm_ori_table_monitor( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - if (phydm_is_large_var(pDM_Odm)) { - pinfo->nxt_state = SAT_TABLE_TRAINING; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - else { - pinfo->nxt_state = ORI_TABLE_MONITOR; - /*switch to anti-sat table*/ - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - } - phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = ORI_TABLE_MONITOR; - -} - -void -phydm_sat_table_training( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - /* if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL, - "pre" adapt ori-table, "cur" adapt sat-table */ - - /*adapt ori table*/ -/* - if (pinfo->pre_state == ORI_TABLE_MONITOR) { - pinfo->nxt_state = SAT_TABLE_TRAINING; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s bypass update pre status statistics once.\n", __FUNCTION__)); - } else { - */ - if (phydm_is_snr_improve(pDM_Odm)) { - pinfo->nxt_state = SAT_TABLE_MONITOR; - } else { - pinfo->nxt_state = SAT_TABLE_TRY_FAIL; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - } -// } - - phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = SAT_TABLE_TRAINING; - -} - -void -phydm_sat_table_try_fail( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - /* if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */ - /* if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */ - - if (phydm_is_large_var(pDM_Odm)) { - if (phydm_is_snr_degrade(pDM_Odm)) { - pinfo->nxt_state = SAT_TABLE_TRAINING; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - else { - pinfo->nxt_state = SAT_TABLE_TRY_FAIL; - } - } else { - pinfo->nxt_state = ORI_TABLE_MONITOR; - } - phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = SAT_TABLE_TRY_FAIL; -} - -void -phydm_sat_table_monitor( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - if (phydm_is_snr_improve(pDM_Odm)) { - - pinfo->sat_table_monitor_times = 0; - - /* if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */ - if (pinfo->pre_state == SAT_TABLE_MONITOR) { - pinfo->nxt_state = ORI_TABLE_TRAINING; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - //phydm_update_pre_status(pDM_Odm); - } else { - pinfo->nxt_state = SAT_TABLE_MONITOR; - } - - /* if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */ - /* if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */ - /*pre_state above is no need to update*/ - } else { - - if (pinfo->sat_table_monitor_times == pDM_Odm->force_change_period) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("%s: sat_table_monitor_times=%d\n", __FUNCTION__, pinfo->sat_table_monitor_times)); - - pinfo->nxt_state = ORI_TABLE_TRAINING; - pinfo->sat_table_monitor_times = 0; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - } else { - pinfo->nxt_state = SAT_TABLE_MONITOR; - pinfo->sat_table_monitor_times++; - } - } - phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = SAT_TABLE_MONITOR; -} - -void -phydm_ori_table_training( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - /* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */ - - if (phydm_is_snr_degrade(pDM_Odm) == FALSE) { - pinfo->nxt_state = ORI_TABLE_MONITOR; - } else { - if (pinfo->pre_snr_var == 0) { - pinfo->nxt_state = ORI_TABLE_TRY_FAIL; - } else { - pinfo->nxt_state = SAT_TABLE_MONITOR; - } - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = ORI_TABLE_TRAINING; -} - -void -phydm_ori_table_try_fail( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - - // if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table - // if pre_state = ORI_TABLE_TRY_FAIL, "pre" adapt sat-table, "cur" adapt sat-table - - if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) { - if (phydm_is_snr_improve(pDM_Odm)) { - pinfo->nxt_state = ORI_TABLE_TRAINING; - pinfo->ori_table_try_fail_times = 0; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - } else { - if (pinfo->ori_table_try_fail_times == pDM_Odm->force_change_period) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("%s: ori_table_try_fail_times=%d\n",__FUNCTION__, pinfo->ori_table_try_fail_times)); - - pinfo->nxt_state = ORI_TABLE_TRAINING; - pinfo->ori_table_try_fail_times = 0; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - phydm_update_pre_status(pDM_Odm); - } else { - pinfo->nxt_state = ORI_TABLE_TRY_FAIL; - pinfo->ori_table_try_fail_times++; - phydm_update_pre_status(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("%s: ori_table_try_fail_times=%d\n",__FUNCTION__, pinfo->ori_table_try_fail_times)); - //config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - } - } else { - pinfo->nxt_state = ORI_TABLE_TRY_FAIL; - pinfo->ori_table_try_fail_times = 0; - phydm_update_pre_status(pDM_Odm); - //config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - -/* - if (phydm_is_large_var(pDM_Odm)) { - if (phydm_is_snr_degrade(pDM_Odm)) { - pinfo->nxt_state = SAT_TABLE_TRAINING; - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - } - else { - pinfo->nxt_state = SAT_TABLE_TRY_FAIL; - } - } else { - pinfo->nxt_state = ORI_TABLE_MONITOR; - } -*/ - //phydm_update_pre_status(pDM_Odm); - pinfo->pre_state = ORI_TABLE_TRY_FAIL; -} - -char * phydm_lna_sat_state_msg( - IN PVOID pDM_VOID, - IN u1Byte state - ) -{ - char *dbg_message; - - switch(state) { - - case ORI_TABLE_MONITOR: - dbg_message = "ORI_TABLE_MONITOR"; - break; - - case SAT_TABLE_TRAINING: - dbg_message = "SAT_TABLE_TRAINING"; - break; - - case SAT_TABLE_TRY_FAIL: - dbg_message = "SAT_TABLE_TRY_FAIL"; - break; - - case SAT_TABLE_MONITOR: - dbg_message = "SAT_TABLE_MONITOR"; - break; - - case ORI_TABLE_TRAINING: - dbg_message = "ORI_TABLE_TRAINING"; - break; - - case ORI_TABLE_TRY_FAIL: - dbg_message = "ORI_TABLE_TRY_FAIL"; - break; - - default: - dbg_message = "ORI_TABLE_MONITOR"; - break; - } - - return dbg_message; -} - -void -phydm_lna_sat_type2_sm( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -// pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; - u1Byte state = pinfo->nxt_state; - u1Byte agc_tab = ODM_GetBBReg(pDM_Odm, 0x958, 0x1f); - char *dbg_message,*nxt_dbg_message; - //u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; - u1Byte real_shift = pDM_Odm->total_bit_shift; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n\n%s ==>\n", __FUNCTION__)); - - if ((pDM_Odm->SupportICType & ODM_RTL8822B) == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n")); - return; - } - - if((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK_TYPE2) == FALSE) { - phydm_lna_sat_chk_type2_init(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n",agc_tab)); - return; - } - - if (pinfo->is_snr_done) - phydm_snr_data_processing(pDM_Odm); - else - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("cur agc table %d\n", agc_tab)); - - if (pDM_Odm->is_force_lna_sat_table != AUTO_AGC_TABLE) { - - //reset state machine - pinfo->nxt_state = ORI_TABLE_MONITOR; - if (pinfo->is_snr_done) { - - if (pDM_Odm->is_force_lna_sat_table == DEFAULT_AGC_TABLE) - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - else if (pDM_Odm->is_force_lna_sat_table == LNA_SAT_AGC_TABLE) - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); - else - config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", - __FUNCTION__, - pinfo->cur_snr_mean, - pinfo->pre_snr_mean, - pinfo->cur_snr_var, - pinfo->pre_snr_var, - pinfo->cur_lower_snr_mean, - pinfo->pre_lower_snr_mean, - pinfo->cnt_lower_snr_statistic)); - - pinfo->is_snr_done = FALSE; - pinfo->is_sm_done = TRUE; - phydm_update_pre_status(pDM_Odm); - } else - return; - } else if (pinfo->is_snr_done) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, - ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", - __FUNCTION__, - pinfo->cur_snr_mean, - pinfo->pre_snr_mean, - pinfo->cur_snr_var, - pinfo->pre_snr_var, - pinfo->cur_lower_snr_mean, - pinfo->pre_lower_snr_mean, - pinfo->cnt_lower_snr_statistic)); - - switch(state) { - - case ORI_TABLE_MONITOR: - dbg_message = "ORI_TABLE_MONITOR"; - phydm_ori_table_monitor(pDM_Odm); - break; - - case SAT_TABLE_TRAINING: - dbg_message = "SAT_TABLE_TRAINING"; - phydm_sat_table_training(pDM_Odm); - break; - - case SAT_TABLE_TRY_FAIL: - dbg_message = "SAT_TABLE_TRY_FAIL"; - phydm_sat_table_try_fail(pDM_Odm); - break; - - case SAT_TABLE_MONITOR: - dbg_message = "SAT_TABLE_MONITOR"; - phydm_sat_table_monitor(pDM_Odm); - break; - - case ORI_TABLE_TRAINING: - dbg_message = "ORI_TABLE_TRAINING"; - phydm_ori_table_training(pDM_Odm); - break; - - case ORI_TABLE_TRY_FAIL: - dbg_message = "ORI_TABLE_TRAINING"; - phydm_ori_table_try_fail(pDM_Odm); - break; - - default: - dbg_message = "ORI_TABLE_MONITOR"; - phydm_ori_table_monitor(pDM_Odm); - break; - - } - - dbg_message = phydm_lna_sat_state_msg(pDM_Odm, state); - nxt_dbg_message = phydm_lna_sat_state_msg(pDM_Odm, pinfo->nxt_state); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("state: [%s]->[%s], \n", dbg_message, nxt_dbg_message)); - - pinfo->is_snr_done = FALSE; - pinfo->is_sm_done = TRUE; - pinfo->total_cnt_snr_statistic = 1 << real_shift; - - }else { - return; - } - -} - -void -phydm_bubble_sort( - IN PVOID pDM_VOID, - IN u1Byte *array, - IN u2Byte array_length -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte i, j; // iterator - u1Byte temp; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); - for(i = 0; i < (array_length-1); i++){ - for (j = (i+1); j < (array_length); j++) { - if(array[i] > array[j]) { - //phydm_bubble_swap(array, i, j); - temp = array[i]; - array[i] = array[j]; - array[j] = temp; - } - } - } -} - -#endif //#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CFG_DIG_DAMPING_CHK +void phydm_dig_recorder_reset(void *dm_void) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + pDIG_T dig_t = &dm->DM_DigTable; + struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; + + PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); + + ODM_Memory_Set(dm, &dig_rc->igi_bitmap, 0, + sizeof(struct phydm_dig_recoder_strcut)); +} + +void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr, u32 fa_cnt) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + pDIG_T dig_t = &dm->DM_DigTable; + struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; + u8 igi_pre = dig_rc->igi_history[0]; + u8 igi_up = 0; + + if (!dm->bLinked) + return; + + PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); + + if (first_connect) { + phydm_dig_recorder_reset(dm); + dig_rc->igi_history[0] = igi_curr; + dig_rc->fa_history[0] = fa_cnt; + return; + } + + igi_pre = dig_rc->igi_history[0]; + igi_up = (igi_curr > igi_pre) ? 1 : 0; + dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up; + + dig_rc->igi_history[3] = dig_rc->igi_history[2]; + dig_rc->igi_history[2] = dig_rc->igi_history[1]; + dig_rc->igi_history[1] = dig_rc->igi_history[0]; + dig_rc->igi_history[0] = igi_curr; + + dig_rc->fa_history[3] = dig_rc->fa_history[2]; + dig_rc->fa_history[2] = dig_rc->fa_history[1]; + dig_rc->fa_history[1] = dig_rc->fa_history[0]; + dig_rc->fa_history[0] = fa_cnt; + + PHYDM_DBG(dm, ODM_COMP_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n", + dig_rc->igi_history[3], dig_rc->igi_history[2], + dig_rc->igi_history[1], dig_rc->igi_history[0]); + PHYDM_DBG(dm, ODM_COMP_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n", + dig_rc->fa_history[3], dig_rc->fa_history[2], + dig_rc->fa_history[1], dig_rc->fa_history[0]); + PHYDM_DBG(dm, ODM_COMP_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n", + (dig_rc->igi_bitmap & BIT(3)) >> 3, + (dig_rc->igi_bitmap & BIT(2)) >> 2, + (dig_rc->igi_bitmap & BIT(1)) >> 1, + dig_rc->igi_bitmap & BIT(0), + dig_rc->igi_bitmap); +} + +void phydm_dig_damping_chk(void *dm_void) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + pDIG_T dig_t = &dm->DM_DigTable; + struct phydm_dig_recoder_strcut *dig_rc = &dig_t->dig_recoder_t; + u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf; + u8 diff1 = 0, diff2 = 0; + u32 fa_low_th = dig_t->fa_th[0]; + u32 fa_high_th = dig_t->fa_th[1]; + u8 fa_pattern_match = 0; + u32 time_tmp; + + if (!dm->bLinked) + return; + + PHYDM_DBG(dm, ODM_COMP_DIG, "%s ======>\n", __func__); + + /*== Release Damping ================================================*/ + if (dig_rc->damping_limit_en) { + PHYDM_DBG(dm, ODM_COMP_DIG, + "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n", + dig_rc->limit_time, dm->phydm_sys_up_time); + + time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD; + + if (DIFF_2(dm->RSSI_Min, dig_rc->limit_rssi) > 3 || + time_tmp < dm->phydm_sys_up_time) { + dig_rc->damping_limit_en = 0; + PHYDM_DBG(dm, ODM_COMP_DIG, "rssi_min=%d, limit_rssi=%d\n", + dm->RSSI_Min, dig_rc->limit_rssi); + } + return; + } + + /*== Damping Pattern Check============================================*/ + PHYDM_DBG(dm, ODM_COMP_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th); + + switch (igi_bitmap_4bit) { + case 0x5: /*4b'0101 ex:down(0x24)->up(0x28)->down(0x24)->up(0x28)*/ + if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] > dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] > fa_high_th) { + /*Check each fa element*/ + fa_pattern_match = 1; + } + break; + case 0x9: /*4b'1001 ex:up(0x28)->down(0x26)->down(0x24)->up(0x28)*/ + if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] < dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th && + dig_rc->fa_history[2] > fa_low_th && + dig_rc->fa_history[3] < fa_high_th) { + /*Check each fa element*/ + fa_pattern_match = 1; + } + break; + default: + break; + } + + if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) { + dig_rc->damping_limit_en = 1; + dig_rc->damping_limit_val = dig_rc->igi_history[0]; + dig_rc->limit_time = dm->phydm_sys_up_time; + dig_rc->limit_rssi = dm->RSSI_Min; + + PHYDM_DBG(dm, ODM_COMP_DIG, + "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n", + dig_rc->damping_limit_val, + dig_rc->limit_time, dig_rc->limit_rssi); + } + + PHYDM_DBG(dm, ODM_COMP_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en); +} +#endif + + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (DM_Type == DIG_TYPE_THRESH_HIGH) + { + pDM_DigTable->RssiHighThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_THRESH_LOW) + { + pDM_DigTable->RssiLowThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_ENABLE) + { + pDM_DigTable->Dig_Enable_Flag = TRUE; + } + else if (DM_Type == DIG_TYPE_DISABLE) + { + pDM_DigTable->Dig_Enable_Flag = FALSE; + } + else if (DM_Type == DIG_TYPE_BACKOFF) + { + if(DM_Value > 30) + DM_Value = 30; + pDM_DigTable->BackoffVal = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) + { + if(DM_Value == 0) + DM_Value = 0x1; + pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) + { + if(DM_Value > 0x50) + DM_Value = 0x50; + pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; + } +} // DM_ChangeDynamicInitGainThresh // + +int +getIGIForDiff(int value_IGI) +{ + #define ONERCCA_LOW_TH 0x30 + #define ONERCCA_LOW_DIFF 8 + + if (value_IGI < ONERCCA_LOW_TH) { + if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) + return ONERCCA_LOW_TH; + else + return value_IGI + ONERCCA_LOW_DIFF; + } else { + return value_IGI; + } +} + +VOID +odm_FAThresholdCheck( + IN PVOID pDM_VOID, + IN BOOLEAN bDFSBand, + IN BOOLEAN bPerformance, + IN u4Byte RxTp, + IN u4Byte TxTp, + OUT u4Byte* dm_FA_thres + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if(pDM_Odm->bLinked && (bPerformance||bDFSBand)) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + /*For AP*/ +#if (DIG_HW == 1) + dm_FA_thres[0] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th1; + dm_FA_thres[1] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th2; + dm_FA_thres[2] = pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_th3; +#else + if ((RxTp>>2) > TxTp && RxTp < 10000 && RxTp > 500) { /*10Mbps & 0.5Mbps*/ + dm_FA_thres[0] = 0x080; + dm_FA_thres[1] = 0x100; + dm_FA_thres[2] = 0x200; + } else { + dm_FA_thres[0] = 0x100; + dm_FA_thres[1] = 0x200; + dm_FA_thres[2] = 0x300; + } +#endif +#else + /*For NIC*/ + dm_FA_thres[0] = DM_DIG_FA_TH0; + dm_FA_thres[1] = DM_DIG_FA_TH1; + dm_FA_thres[2] = DM_DIG_FA_TH2; +#endif + } else { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) + if(bDFSBand) + { + // For DFS band and no link + dm_FA_thres[0] = 250; + dm_FA_thres[1] = 1000; + dm_FA_thres[2] = 2000; + } + else +#endif + { + dm_FA_thres[0] = 2000; + dm_FA_thres[1] = 4000; + dm_FA_thres[2] = 5000; + } + } + return; +} + +u1Byte +odm_ForbiddenIGICheck( + IN PVOID pDM_VOID, + IN u1Byte dym_min, + IN u1Byte CurrentIGI + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte rx_gain_min = pDM_DigTable->rx_gain_range_min; + + if (pDM_DigTable->LargeFA_Timeout) { + if (--pDM_DigTable->LargeFA_Timeout == 0) + pDM_DigTable->LargeFAHit = 0; + } + + if (pFalseAlmCnt->Cnt_all > 10000) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); + + if(pDM_DigTable->LargeFAHit != 3) + pDM_DigTable->LargeFAHit++; + + if(pDM_DigTable->ForbiddenIGI < CurrentIGI) { + pDM_DigTable->ForbiddenIGI = CurrentIGI; + pDM_DigTable->LargeFAHit = 1; + pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; + } + + if(pDM_DigTable->LargeFAHit >= 3) { + if((pDM_DigTable->ForbiddenIGI + 2) > pDM_DigTable->rx_gain_range_max) + rx_gain_min = pDM_DigTable->rx_gain_range_max; + else + rx_gain_min = (pDM_DigTable->ForbiddenIGI + 2); + pDM_DigTable->Recover_cnt = 1800; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); + } + } + + else if (pFalseAlmCnt->Cnt_all > 2000) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Cnt_all=%d, Cnt_all_pre=%d, CurrentIGI=0x%x, PreIGValue=0x%x\n", + pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_all_pre, CurrentIGI, pDM_DigTable->PreIGValue)); + + /* pFalseAlmCnt->Cnt_all = 1.1875*pFalseAlmCnt->Cnt_all_pre */ + if ((pFalseAlmCnt->Cnt_all > (pFalseAlmCnt->Cnt_all_pre + (pFalseAlmCnt->Cnt_all_pre >> 3) + (pFalseAlmCnt->Cnt_all_pre >> 4))) && (CurrentIGI < pDM_DigTable->PreIGValue)) { + if (pDM_DigTable->LargeFAHit != 3) + pDM_DigTable->LargeFAHit++; + + if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("Updating ForbiddenIGI by CurrentIGI, ForbiddenIGI=0x%x, CurrentIGI=0x%x\n", + pDM_DigTable->ForbiddenIGI, CurrentIGI)); + + pDM_DigTable->ForbiddenIGI = CurrentIGI; /*pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;*/ + pDM_DigTable->LargeFAHit = 1; + pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; + } + + } + + if (pDM_DigTable->LargeFAHit >= 3) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, ForbiddenIGI=0x%x\n", + pDM_DigTable->rx_gain_range_max, rx_gain_min, pDM_DigTable->ForbiddenIGI)); + + if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max) + rx_gain_min = pDM_DigTable->rx_gain_range_max; + else + rx_gain_min = (pDM_DigTable->ForbiddenIGI + 1); + + pDM_DigTable->Recover_cnt = 1200; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("Abnormal fa case: Recover_cnt = %d, rx_gain_min = 0x%x\n", + pDM_DigTable->Recover_cnt, rx_gain_min)); + } + } else { + if (pDM_DigTable->Recover_cnt != 0) { + + pDM_DigTable->Recover_cnt --; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); + } else { + + if(pDM_DigTable->LargeFAHit < 3) { + if((pDM_DigTable->ForbiddenIGI - 2) < dym_min) { + pDM_DigTable->ForbiddenIGI = dym_min; + rx_gain_min = dym_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); + } else { + if (pDM_DigTable->LargeFAHit == 0) { + pDM_DigTable->ForbiddenIGI -= 2; + rx_gain_min = (pDM_DigTable->ForbiddenIGI + 2); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } + } + } else { + pDM_DigTable->LargeFAHit = 0; + } + } + } + + return rx_gain_min; + +} + + +VOID +odm_InbandNoiseCalculate ( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte IGIBackup, TimeCnt = 0, ValidCnt = 0; + BOOLEAN bTimeout = TRUE; + s1Byte sNoise_A, sNoise_B; + s4Byte NoiseRpt_A = 0,NoiseRpt_B = 0; + u4Byte tmp = 0; + static u1Byte failCnt = 0; + + if(!(pDM_Odm->SupportICType & (ODM_RTL8192E))) + return; + + if(pDM_Odm->RFType == ODM_1T1R || *(pDM_Odm->pOnePathCCA) != ODM_CCA_2R) + return; + + if(!pDM_DigTable->bNoiseEst) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); + + //1 Set initial gain. + IGIBackup = pDM_DigTable->CurIGValue; + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = 0; + ODM_Write_DIG(pDM_Odm, 0x24); + + //1 Update idle time power report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x0); + + delay_ms(2); + + //1 Get noise power level + while(1) + { + //2 Read Noise Floor Report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + tmp = ODM_GetBBReg(pDM_Odm, 0x8f8, bMaskLWord); + + sNoise_A = (s1Byte)(tmp & 0xff); + sNoise_B = (s1Byte)((tmp & 0xff00)>>8); + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + + if((sNoise_A < 20 && sNoise_A >= -70) && (sNoise_B < 20 && sNoise_B >= -70)) + { + ValidCnt++; + NoiseRpt_A += sNoise_A; + NoiseRpt_B += sNoise_B; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + } + + TimeCnt++; + bTimeout = (TimeCnt >= 150)?TRUE:FALSE; + + if(ValidCnt == 20 || bTimeout) + break; + + delay_ms(2); + + } + + //1 Keep idle time power report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x1); + + //1 Recover IGI + ODM_Write_DIG(pDM_Odm, IGIBackup); + + //1 Calculate Noise Floor + if(ValidCnt != 0) + { + NoiseRpt_A /= (ValidCnt<<1); + NoiseRpt_B /= (ValidCnt<<1); + } + + if(bTimeout) + { + NoiseRpt_A = 0; + NoiseRpt_B = 0; + + failCnt ++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", failCnt)); + + if(failCnt == 3) + { + failCnt = 0; + pDM_DigTable->bNoiseEst = FALSE; + } + } + else + { + NoiseRpt_A = -110 + 0x24 + NoiseRpt_A -6; + NoiseRpt_B = -110 + 0x24 + NoiseRpt_B -6; + pDM_DigTable->bNoiseEst = FALSE; + failCnt = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NoiseRpt_A = %d, NoiseRpt_B = %d\n", NoiseRpt_A, NoiseRpt_B)); + } + + //1 Calculate IGI Offset + if(NoiseRpt_A > NoiseRpt_B) + { + pDM_DigTable->IGIOffset_A = NoiseRpt_A - NoiseRpt_B; + pDM_DigTable->IGIOffset_B = 0; + } + else + { + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = NoiseRpt_B - NoiseRpt_A; + } + +#endif + return; +} + +VOID +odm_DigForBtHsMode( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable=&pDM_Odm->DM_DigTable; + u1Byte digForBtHs=0; + u1Byte digUpBound=0x5a; + + if (pDM_Odm->bBtConnectProcess) { + digForBtHs = 0x22; + } else { + // + // Decide DIG value by BT HS RSSI. + // + digForBtHs = pDM_Odm->btHsRssi+4; + + //DIG Bound + if(digForBtHs > digUpBound) + digForBtHs = digUpBound; + if(digForBtHs < 0x1c) + digForBtHs = 0x1c; + + // update Current IGI + pDM_DigTable->BT30_CurIGI = digForBtHs; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs)); +#endif +} + +VOID +phydm_setBigJumpStep( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI +) +{ +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; + u1Byte i; + + if (pDM_DigTable->enableAdjustBigJump == 0) + return; + + for (i = 0; i <= pDM_DigTable->bigJumpStep1; i++) { + if ((CurrentIGI + step1[i]) > pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx]) { + if (i != 0) + i = i - 1; + break; + } else if (i == pDM_DigTable->bigJumpStep1) + break; + } + if (pDM_Odm->SupportICType & ODM_RTL8822B) + ODM_SetBBReg(pDM_Odm, 0x8c8, 0xe, i); + else if (pDM_Odm->SupportICType & ODM_RTL8197F) + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_setBigJumpStep(): bigjump = %d (ori = 0x%d), LMT=0x%x\n", i, pDM_DigTable->bigJumpStep1, pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx])); +#endif +} + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (pDM_DigTable->bStopDIG) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Stop Writing IGI\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", + ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); + + //1 Check initial gain by upper bound + if ((!pDM_DigTable->bPSDInProgress) && pDM_Odm->bLinked) + { + if(0) + { + if (CurrentIGI > pDM_DigTable->rx_gain_range_max) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x) is larger than upper bound !!\n", CurrentIGI)); + CurrentIGI = pDM_DigTable->rx_gain_range_max; + } + } + if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE) + { + if(CurrentIGI > pDM_Odm->Adaptivity_IGI_upper) + CurrentIGI = pDM_Odm->Adaptivity_IGI_upper; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", CurrentIGI)); + } + } + + if(pDM_DigTable->CurIGValue != CurrentIGI) + { + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + /* Modify big jump step for 8822B and 8197F */ + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) + phydm_setBigJumpStep(pDM_Odm, CurrentIGI); +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + /* Set IGI value of CCK for new CCK AGC */ + if (pDM_Odm->cck_new_agc) { + if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) + ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurrentIGI>>1)); + } +#endif + + /*Add by YuChen for USB IO too slow issue*/ + if ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) && (CurrentIGI > pDM_DigTable->CurIGValue)) + Phydm_Adaptivity(pDM_Odm, CurrentIGI); + + //1 Set IGI value + if (pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)) { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + } +#endif + } else if (pDM_Odm->SupportPlatform & (ODM_AP)) { + switch(*(pDM_Odm->pOnePathCCA)) + { + case ODM_CCA_2R: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + } +#endif + break; + case ODM_CCA_1R_A: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if(pDM_Odm->RFType != ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + break; + case ODM_CCA_1R_B: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + if(pDM_Odm->RFType != ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + break; + } + } + + pDM_DigTable->CurIGValue = CurrentIGI; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x).\n", CurrentIGI)); + +} + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte IGIValue +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG()=========> level = %d\n", pause_level)); + + if ((pDM_DigTable->pause_dig_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_DIG) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseDIG(): Return: SupportAbility DIG or FA is disabled !!\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseDIG(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], + pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); + + switch (PauseType) { + /* Pause DIG */ + case PHYDM_PAUSE: + { + /* Disable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_DIG)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Pause DIG !!\n")); + + /* Backup IGI value */ + if (pDM_DigTable->pause_dig_level == 0) { + pDM_DigTable->IGIBackup = pDM_DigTable->CurIGValue; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Backup IGI = 0x%x, new IGI = 0x%x\n", pDM_DigTable->IGIBackup, IGIValue)); + } + + /* Record IGI value */ + pDM_DigTable->pause_dig_value[pause_level] = IGIValue; + + /* Update pause level */ + pDM_DigTable->pause_dig_level = (pDM_DigTable->pause_dig_level | BIT(pause_level)); + + /* Write new IGI value */ + if (BIT(pause_level + 1) > pDM_DigTable->pause_dig_level) { + ODM_Write_DIG(pDM_Odm, IGIValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): IGI of higher level = 0x%x\n", IGIValue)); + } + break; + } + /* Resume DIG */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((pDM_DigTable->pause_dig_level & (BIT(pause_level))) != 0) { + pDM_DigTable->pause_dig_level = pDM_DigTable->pause_dig_level & (~(BIT(pause_level))); + pDM_DigTable->pause_dig_value[pause_level] = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Resume DIG !!\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (pDM_DigTable->pause_dig_level == 0) { + /* Write backup IGI value */ + ODM_Write_DIG(pDM_Odm, pDM_DigTable->IGIBackup); + pDM_DigTable->bIgnoreDIG = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write original IGI = 0x%x\n", pDM_DigTable->IGIBackup)); + + /* Enable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_DIG); + break; + } + + if (BIT(pause_level) > pDM_DigTable->pause_dig_level) { + s1Byte max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((pDM_DigTable->pause_dig_level & BIT(max_level)) > 0) + break; + } + + /* write IGI of lower level */ + ODM_Write_DIG(pDM_Odm, pDM_DigTable->pause_dig_value[max_level]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write IGI (0x%x) of level (%d)\n", + pDM_DigTable->pause_dig_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], + pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); + +} + +BOOLEAN +odm_DigAbort( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + + //SupportAbility + if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_FA_CNT is disabled\n")); + return TRUE; + } + + //SupportAbility + if(!(pDM_Odm->SupportAbility & ODM_BB_DIG)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_DIG is disabled\n")); + return TRUE; + } + + //ScanInProcess + if(*(pDM_Odm->pbScanInProcess)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress \n")); + return TRUE; + } + + if(pDM_DigTable->bIgnoreDIG) + { + pDM_DigTable->bIgnoreDIG = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG \n")); + return TRUE; + } + + //add by Neil Chen to avoid PSD is processing + if(pDM_Odm->bDMInitialGainEnable == FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing \n")); + return TRUE; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if OS_WIN_FROM_WIN7(OS_VERSION) + if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test \n")); + return TRUE; + } + #endif + + if(pDM_Odm->bBtHsOperation) + { + odm_DigForBtHsMode(pDM_Odm); + } + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) + { + printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); + ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); + return TRUE; + } + #endif +#else + if (!(priv->up_time > 5)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG Operation Period \n")); + return TRUE; + } +#endif + + return FALSE; +} + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); +#endif + u4Byte ret_value; + u1Byte i; + + pDM_DigTable->bStopDIG = FALSE; + pDM_DigTable->bIgnoreDIG = FALSE; + pDM_DigTable->bPSDInProgress = FALSE; + pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); + pDM_DigTable->PreIGValue = 0; + pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; + pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; + pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; + pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; + pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; + pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; + pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; + pDM_DigTable->PreCCK_CCAThres = 0xFF; + pDM_DigTable->CurCCK_CCAThres = 0x83; + pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; + pDM_DigTable->LargeFAHit = 0; + pDM_DigTable->LargeFA_Timeout = 0; + pDM_DigTable->Recover_cnt = 0; + pDM_DigTable->bMediaConnect_0 = FALSE; + pDM_DigTable->bMediaConnect_1 = FALSE; +#if (DIG_HW == 1) + pDM_DigTable->pre_rssi_min = 0; +#endif + //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error + pDM_Odm->bDMInitialGainEnable = TRUE; + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + pDM_DigTable->tdma_dig_cnt = 0; + pDM_DigTable->pre_tdma_dig_cnt = 0; + pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE] = pDM_DigTable->CurIGValue; + pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] = pDM_DigTable->CurIGValue; + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = DM_DIG_MAX_NIC; + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = DM_DIG_MIN_NIC; + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = DM_DIG_MIN_NIC; + + for(i = 0; i <= 1; i++) { + pDM_DigTable->stay_check_state_cnt[i] = 0; // check state + pDM_DigTable->goto_lock_state_cnt[i] = 0; // check state + pDM_DigTable->goto_release_state_cnt[i] = 0; // lock state + pDM_DigTable->stay_release_state_cnt[i] = 0; // release state + } +#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + pDM_DigTable->DIG_Dynamic_MIN_0 = 0x25; + pDM_DigTable->DIG_Dynamic_MIN_1 = 0x25; + + // For AP\ ADSL modified DIG + pDM_DigTable->bTpTarget = FALSE; + pDM_DigTable->bNoiseEst = TRUE; + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = 0; + pDM_DigTable->TpTrainTH_min = 0; + + // For RTL8881A + FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; + + //Dyanmic EDCCA + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + ODM_SetBBReg(pDM_Odm, 0xC50, 0xFFFF0000, 0xfafd); + } +#else + pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; + pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; + + //To Initi BT30 IGI + pDM_DigTable->BT30_CurIGI=0x32; + + ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + pDM_DigTable->pause_dig_level = 0; + ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + pDM_DigTable->pause_cckpd_level = 0; +#endif + + if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)) + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + else + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + pDM_DigTable->enableAdjustBigJump = 1; + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + ret_value = ODM_GetBBReg(pDM_Odm, 0x8c8, bMaskLWord); + pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; + pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; + pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; + + } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, bMaskLWord); + pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; + pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; + pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; + } + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { + for (i = 0; i < sizeof(pDM_DigTable->bigJumpLmt); i++) { + if (pDM_DigTable->bigJumpLmt[i] == 0) + pDM_DigTable->bigJumpLmt[i] = 0x64; /* Set -10dBm as default value */ + } + } +#endif + + +#if (DIG_HW == 1) + pDM_DigTable->pre_rssi_min = 0; +#endif +#ifdef CFG_DIG_DAMPING_CHK + phydm_dig_recorder_reset(pDM_Odm); + pDM_DigTable->dig_dl_en = 1; +#endif +} + +u1Byte +phydm_igi_chkby_upper_lower_bond( + u1Byte igi, + u1Byte upper_bond, + u1Byte lower_bond + ) +{ + u1Byte igi_tmp = igi; + + if (igi < lower_bond) + igi_tmp = lower_bond; + else if (igi > upper_bond) + igi_tmp = upper_bond; + + return igi_tmp; +} + +VOID +odm_DIG( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + PSTA_INFO_T pEntry; +#endif + + // Common parameters + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recoder_strcut *dig_rc = &pDM_DigTable->dig_recoder_t; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); +#endif +// PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte CurrentIGI; + BOOLEAN FirstConnect,FirstDisConnect; + u1Byte DIG_MaxOfMin, DIG_Dynamic_MIN; + u1Byte dm_dig_max, dm_dig_min; + u1Byte offset; + u1Byte rssi_min = pDM_Odm->RSSI_Min; + u1Byte igi_upper_rssi_min; + u4Byte dm_FA_thres[3]; + u4Byte TxTp = 0, RxTp = 0; + BOOLEAN bDFSBand = FALSE; + BOOLEAN bPerformance = TRUE, bFirstTpTarget = FALSE, bFirstCoverage = FALSE; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte TpTrainTH_MIN = DM_DIG_TP_Target_TH0; + static u1Byte TimeCnt = 0; + u1Byte i; +#endif +#if (DIG_HW == 1) + BOOLEAN DIG_GoUpCheck = TRUE; + u1Byte step_size[3] = {0}; +#endif + + CurrentIGI = pDM_DigTable->CurIGValue; + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI=0x%x\n", CurrentIGI)); + +#if (DIG_HW == 1) + if (pDM_Odm->bLinked) { + if (pDM_DigTable->pre_rssi_min <= rssi_min) { + step_size[2] = 2; + step_size[1] = 1; + step_size[0] = 2; + } else { + step_size[2] = 4; + step_size[1] = 2; + step_size[0] = 2; + } + pDM_DigTable->pre_rssi_min = rssi_min; + } else { + step_size[2] = 2; + step_size[1] = 1; + step_size[0] = 2; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI_Min = %d, pre_rssi_min = %d\n", + rssi_min, pDM_DigTable->pre_rssi_min)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", + step_size[0], step_size[1], step_size[2])); +#endif + + //1 Update status + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + +#ifdef CFG_DIG_DAMPING_CHK + /*Record IGI History*/ + phydm_dig_recorder(pDM_Odm, FirstConnect, CurrentIGI, pFalseAlmCnt->Cnt_all); + + /*DIG Damping Check*/ + phydm_dig_damping_chk(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + //1 Noise Floor Estimate + //pDM_DigTable->bNoiseEst = (FirstConnect)?TRUE:pDM_DigTable->bNoiseEst; + //odm_InbandNoiseCalculate (pDM_Odm); + + //1 Mode decision + if(pDM_Odm->bLinked) + { + //2 Calculate total TP + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + RxTp += (u4Byte)(pEntry->rx_byte_cnt_LowMAW>>7); + TxTp += (u4Byte)(pEntry->tx_byte_cnt_LowMAW>>7); //Kbps + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TX TP = %dkbps, RX TP = %dkbps\n", TxTp, RxTp)); + } + + switch(pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable) + { + case 0: + { + bPerformance = TRUE; + break; + } + case 1: + { + bPerformance = FALSE; + break; + } + case 2: + { + if(pDM_Odm->bLinked) + { + if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH0) + TpTrainTH_MIN = pDM_DigTable->TpTrainTH_min; + + if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH1) + TpTrainTH_MIN = DM_DIG_TP_Target_TH1; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TP training mode lower bound = %dkbps\n", TpTrainTH_MIN)); + + //2 Decide DIG mode by total TP + if((TxTp + RxTp) > DM_DIG_TP_Target_TH1) // change to performance mode + { + bFirstTpTarget = (!pDM_DigTable->bTpTarget)?TRUE:FALSE; + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + } + else if((TxTp + RxTp) < TpTrainTH_MIN) // change to coverage mode + { + bFirstCoverage = (pDM_DigTable->bTpTarget)?TRUE:FALSE; + + if(TimeCnt < DM_DIG_TP_Training_Period) + { + pDM_DigTable->bTpTarget = FALSE; + bPerformance = FALSE; + TimeCnt++; + } + else + { + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + bFirstTpTarget = TRUE; + TimeCnt = 0; + } + } + else // remain previous mode + { + bPerformance = pDM_DigTable->bTpTarget; + + if(!bPerformance) + { + if(TimeCnt < DM_DIG_TP_Training_Period) + TimeCnt++; + else + { + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + bFirstTpTarget = TRUE; + TimeCnt = 0; + } + } + } + + if(!bPerformance) + pDM_DigTable->TpTrainTH_min = RxTp + TxTp; + + } + else + { + bPerformance = FALSE; + pDM_DigTable->TpTrainTH_min = 0; + } + break; + } + default: + bPerformance = TRUE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== bPerformance = %d ======\n", bPerformance)); +#endif + + //1 Boundary Decision + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + //2 For AP\ADSL + if(!bPerformance) + { + dm_dig_max = DM_DIG_MAX_AP_COVERAGR; + dm_dig_min = DM_DIG_MIN_AP_COVERAGE; +#if (DIG_HW == 1) + DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; +#else + DIG_MaxOfMin = DM_DIG_MAX_OF_MIN_COVERAGE; +#endif + + } + else + { + if (pDM_Odm->RFType == ODM_1T1R) + dm_dig_max = DM_DIG_MAX_AP - 6; + else + dm_dig_max = DM_DIG_MAX_AP; + + if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && (pDM_Odm->SupportICType & ODM_RTL8814A)) /* for 2G 8814 */ + dm_dig_min = 0x1c; + else if (pDM_Odm->SupportICType & ODM_RTL8197F) /*refine by YuChen 20160815 asked by RF Arthur*/ + dm_dig_min = 0x1e; + else + dm_dig_min = DM_DIG_MIN_AP; + +#if (DIG_HW == 1) + DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; +#else + DIG_MaxOfMin = DM_DIG_MAX_OF_MIN; +#endif + + } + + //4 TX2path + if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) + dm_dig_max = 0x2A; + +#if RTL8192E_SUPPORT +#ifdef HIGH_POWER_EXT_LNA + if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) + dm_dig_max = 0x42; +#endif +#endif + +#else //#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + //2 For WIN\CE + if(pDM_Odm->SupportICType >= ODM_RTL8188E) + dm_dig_max = 0x5A; + else + dm_dig_max = DM_DIG_MAX_NIC; + + if(pDM_Odm->SupportICType != ODM_RTL8821) + dm_dig_min = DM_DIG_MIN_NIC; + else + dm_dig_min = 0x1C; + + DIG_MaxOfMin = DM_DIG_MAX_AP; +#endif + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) + /* Modify lower bound for DFS band */ + if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || + ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + && phydm_dfs_master_enabled(pDM_Odm) == TRUE + #endif + ) { + bDFSBand = TRUE; + if (*pDM_Odm->pBandWidth == ODM_BW20M) + dm_dig_min = DM_DIG_MIN_AP_DFS+2; + else + dm_dig_min = DM_DIG_MIN_AP_DFS; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): ====== In DFS band ======\n")); + } +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (pDM_Odm->pu1ForcedIgiLb && (0 < *pDM_Odm->pu1ForcedIgiLb)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Force IGI lb to: 0x%02x !!!!!!\n", *pDM_Odm->pu1ForcedIgiLb)); + dm_dig_min = *pDM_Odm->pu1ForcedIgiLb; + dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); + } +#endif + + //1 Adjust boundary by RSSI + if(pDM_Odm->bLinked && bPerformance) + { + //2 Modify DIG upper bound +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + offset = 15; +#else + //4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT + if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig == 1)) + { + offset = 10; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Coex. case: Force upper bound to RSSI + %d !!!!!!\n", offset)); + } + else + offset = 15; +#endif + igi_upper_rssi_min = rssi_min + offset; + + /*rx_gain_range_max*/ + if((igi_upper_rssi_min) > dm_dig_max) + pDM_DigTable->rx_gain_range_max = dm_dig_max; + else if((igi_upper_rssi_min) < dm_dig_min) + pDM_DigTable->rx_gain_range_max = dm_dig_min; + else + pDM_DigTable->rx_gain_range_max = igi_upper_rssi_min; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + //2 Modify DIG lower bound + //if(pDM_Odm->bOneEntryOnly) + { + /*DIG_Dynamic_MIN()*/ + if(rssi_min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (rssi_min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = rssi_min; + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (bDFSBand) { + DIG_Dynamic_MIN = dm_dig_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); + } +#endif + } +#else + { + //4 For AP +#ifdef __ECOS + HAL_REORDER_BARRIER(); +#else + rmb(); +#endif + if (bDFSBand) + { + DIG_Dynamic_MIN = dm_dig_min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); + } else { + + /*DIG_Dynamic_MIN(rx_gain_range_min)*/ + if(rssi_min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (rssi_min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = rssi_min; + } + } +#endif + } + else + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) + if(bPerformance && bDFSBand) + { + pDM_DigTable->rx_gain_range_max = 0x28; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, + ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->rx_gain_range_max)); + } + else +#endif + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_OF_MIN; + } + DIG_Dynamic_MIN = dm_dig_min; + } + + //1 Force Lower Bound for AntDiv + if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) + { + if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { + if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) { + DIG_Dynamic_MIN = DIG_MaxOfMin; + } + else { + DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Antenna diversity case: Force lower bound to 0x%x\n", + DIG_Dynamic_MIN)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Antenna diversity case: RSSI_max=0x%x\n", + pDM_DigTable->AntDiv_RSSI_max)); + } + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, + ("Adjust boundary by RSSI rx_gain_range_max=0x%x, DIG_Dynamic_MIN = 0x%x\n", + pDM_DigTable->rx_gain_range_max, DIG_Dynamic_MIN)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, + ("Link status: bLinked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n\n", + pDM_Odm->bLinked, rssi_min, FirstConnect, FirstDisConnect)); + + //1 Modify DIG lower bound, deal with abnormal case + //2 Abnormal false alarm case + if(!pDM_Odm->bLinked) + { + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; + + if (FirstDisConnect) + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; + } + else { + pDM_DigTable->rx_gain_range_min = odm_ForbiddenIGICheck(pDM_Odm, DIG_Dynamic_MIN, CurrentIGI); + } + //2 Abnormal # beacon case +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pDM_Odm->bLinked && !FirstConnect) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", pDM_Odm->PhyDbgInfo.NumQryBeaconPkt)); + if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pDM_Odm->bsta_state)) + { + pDM_DigTable->rx_gain_range_min = 0x1c; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x !!!!!!\n\n", + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, pDM_DigTable->rx_gain_range_min)); + } + } +#endif + + //2 Abnormal lower bound case + if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) + { + pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnrormal rx_gain_range_min: force to 0x%x\n\n", + pDM_DigTable->rx_gain_range_min)); + } + +#ifdef CFG_DIG_DAMPING_CHK + /*Limit Dyn min by damping*/ + if (pDM_DigTable->dig_dl_en && + dig_rc->damping_limit_en && + pDM_DigTable->rx_gain_range_min < dig_rc->damping_limit_val) { + PHYDM_DBG(pDM_Odm, ODM_COMP_DIG, + "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n", + pDM_DigTable->rx_gain_range_min, dig_rc->damping_limit_val); + + pDM_DigTable->rx_gain_range_min = dig_rc->damping_limit_val; + } +#endif + + //1 False alarm threshold decision + odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); + + pDM_DigTable->fa_th[0] = dm_FA_thres[0]; + pDM_DigTable->fa_th[1] = dm_FA_thres[1]; + pDM_DigTable->fa_th[2] = dm_FA_thres[2]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", + dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + //1 Adjust initial gain by false alarm + if(pDM_Odm->bLinked && bPerformance) + { + //2 After link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); + + if(bFirstTpTarget || (FirstConnect && bPerformance)) { + pDM_DigTable->LargeFAHit = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) + if(bDFSBand) + { + if(rssi_min > 0x28) { + CurrentIGI = 0x28; + } + else { + CurrentIGI = rssi_min; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DFS band:One-shot to 0x28 upmost\n")); + } + else +#endif + { + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); +#endif +#endif + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First connect case: IGI does on-shot to 0x%x\n", CurrentIGI)); + + } + else { + +#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) + if (priv->pshare->rf_ft_var.dig_upcheck_enable) + DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); + + CurrentIGI = phydm_dig_current_igi_by_fa_th(pDM_Odm, CurrentIGI, dm_FA_thres, step_size, DIG_GoUpCheck, NORMAL_DIG); +#endif + //4 Abnormal # beacon case +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) + { + CurrentIGI = pDM_DigTable->rx_gain_range_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, CurrentIGI)); + } +#endif + } + } else { + //2 Before link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); + + if(FirstDisConnect || bFirstCoverage) { + CurrentIGI = dm_dig_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First disconnect case: IGI does on-shot to lower bound\n")); + } else { +#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) + if (priv->pshare->rf_ft_var.dig_upcheck_enable) + DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); + + CurrentIGI = phydm_dig_current_igi_by_fa_th(pDM_Odm, CurrentIGI, dm_FA_thres, step_size, DIG_GoUpCheck, NORMAL_DIG); +#endif + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("before check igi by ULbond, CurrentIGI=0x%x\n", CurrentIGI)); + + //1 Check initial gain by upper/lower bound + CurrentIGI = phydm_igi_chkby_upper_lower_bond(CurrentIGI, pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("after ULbond check,CurrentIGI=0x%x,\n", CurrentIGI)); + + //1 Update status + { +#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) + if(pDM_Odm->bBtHsOperation) + { + if(pDM_Odm->bLinked) + { + if(pDM_DigTable->BT30_CurIGI > (CurrentIGI)) + ODM_Write_DIG(pDM_Odm, CurrentIGI); + else + ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI); + + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + if(pDM_Odm->bLinkInProcess) + ODM_Write_DIG(pDM_Odm, 0x1c); + else if(pDM_Odm->bBtConnectProcess) + ODM_Write_DIG(pDM_Odm, 0x28); + else + ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + } + } + else // BT is not using +#endif + { + ODM_Write_DIG(pDM_Odm, CurrentIGI); + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + } +} + +void +phydm_lna_sat_chk_watchdog( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; + u1Byte rssi_min = pDM_Odm->RSSI_Min; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); + + if(!(pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("SupportAbility ODM_BB_LNA_SAT_CHK is disabled, return.\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n", + pDM_LNA_info->pre_timer_check_cnt, + pDM_LNA_info->cur_timer_check_cnt)); + + if(pDM_Odm->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("is_disable_lna_sat_chk=%d, return.\n", pDM_Odm->is_disable_lna_sat_chk)); + return; + } + + if ((pDM_Odm->SupportICType & ODM_RTL8197F) == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("SupportICType != ODM_RTL8197F, return.\n")); + return; + } + + if ((rssi_min == 0) || (rssi_min == 0xff)) { + // adapt agc table 0 + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("rssi_min=%d, return.\n", rssi_min)); + return; + } + + if(pDM_LNA_info->cur_timer_check_cnt == pDM_LNA_info->pre_timer_check_cnt) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("Timer check fail, restart timer.\n")); + phydm_lna_sat_chk(pDM_Odm); + } + else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("Timer check pass.\n")); + } + pDM_LNA_info->pre_timer_check_cnt = pDM_LNA_info->cur_timer_check_cnt; +} + +void +phydm_lna_sat_chk_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); + + pDM_LNA_info->check_time = 0; + pDM_LNA_info->sat_cnt_acc_patha = 0; + pDM_LNA_info->sat_cnt_acc_pathb = 0; + pDM_LNA_info->cur_sat_status = 0; + pDM_LNA_info->pre_sat_status = 0; + pDM_LNA_info->cur_timer_check_cnt = 0; + pDM_LNA_info->pre_timer_check_cnt = 0; +} + +void +phydm_set_ofdm_agc_tab( + IN PVOID pDM_VOID, + IN u1Byte tab_sel +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + /* table sel:0/2, 1 is used for CCK */ + if (tab_sel == OFDM_AGC_TAB_0) + ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); + else if (tab_sel == OFDM_AGC_TAB_2) + ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_2); + else + ODM_SetBBReg(pDM_Odm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); +} + +u1Byte +phydm_get_ofdm_agc_tab( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + return (u1Byte)ODM_GetBBReg(pDM_Odm, 0xc70, 0x1e00); +} + + +void +phydm_lna_sat_chk( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; + u1Byte igi_rssi_min, rssi_min = pDM_Odm->RSSI_Min; + u4Byte sat_status_patha, sat_status_pathb; + u1Byte igi_restore = pDM_DigTable->CurIGValue; + u1Byte i, lna_sat_chk_cnt = pDM_Odm->lna_sat_chk_cnt; + u4Byte lna_sat_cnt_thd = 0; + u1Byte agc_tab; + u4Byte max_check_time = 0; +// u4Byte func_start, func_end; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); + + if(!(pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("SupportAbility ODM_BB_LNA_SAT_CHK is disabled, return.\n")); + return; + } + + if(pDM_Odm->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("is_disable_lna_sat_chk=%d, return.\n", pDM_Odm->is_disable_lna_sat_chk)); + return; + } + + //func_start = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); + + // move igi to target pin of rssi_min + if ((rssi_min == 0) || (rssi_min == 0xff)) { + // adapt agc table 0 + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(pDM_Odm); + return; + } + else if (rssi_min % 2 != 0) + igi_rssi_min = rssi_min + RSSI_TO_IGI - 1; + else + igi_rssi_min = rssi_min + RSSI_TO_IGI; + + if ((pDM_Odm->lna_sat_chk_period_ms > 0) && (pDM_Odm->lna_sat_chk_period_ms <= ONE_SEC_MS)) + max_check_time = lna_sat_chk_cnt*(ONE_SEC_MS/(pDM_Odm->lna_sat_chk_period_ms))*5; + else + max_check_time = lna_sat_chk_cnt * 5; + + lna_sat_cnt_thd = (max_check_time * pDM_Odm->lna_sat_chk_duty_cycle)/100; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nlna_sat_chk_cnt=%d, lna_sat_chk_period_ms=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n", + pDM_LNA_info->check_time, + rssi_min, + igi_rssi_min, + lna_sat_chk_cnt, + pDM_Odm->lna_sat_chk_period_ms, + max_check_time, + lna_sat_cnt_thd)); + + ODM_Write_DIG(pDM_VOID, igi_rssi_min); + + // adapt agc table 0 check saturation status + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); + // open rf power detection ckt & set detection range + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x86, 0x1f, 0x10); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x86, 0x1f, 0x10); + + // check saturation status + for(i = 0; i < lna_sat_chk_cnt; i++) { + sat_status_patha = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0xae, 0xc0000); + sat_status_pathb = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0xae, 0xc0000); + if(sat_status_patha != 0) + pDM_LNA_info->sat_cnt_acc_patha++; + if(sat_status_pathb != 0) + pDM_LNA_info->sat_cnt_acc_pathb++; + + if ((pDM_LNA_info->sat_cnt_acc_patha >= lna_sat_cnt_thd) || + (pDM_LNA_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd)) { + pDM_LNA_info->cur_sat_status= 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("cur_sat_status=%d, check_time=%d\n", + pDM_LNA_info->cur_sat_status, + pDM_LNA_info->check_time)); + break; + } else + pDM_LNA_info->cur_sat_status= 0; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n", + pDM_LNA_info->cur_sat_status, + pDM_LNA_info->pre_sat_status, + pDM_LNA_info->sat_cnt_acc_patha, + pDM_LNA_info->sat_cnt_acc_pathb)); + + // agc table decision + if (pDM_LNA_info->cur_sat_status) { + if(!pDM_Odm->is_disable_gain_table_switch) + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_2); + pDM_LNA_info->check_time = 0; + pDM_LNA_info->sat_cnt_acc_patha = 0; + pDM_LNA_info->sat_cnt_acc_pathb = 0; + pDM_LNA_info->pre_sat_status = pDM_LNA_info->cur_sat_status; + + } else if (pDM_LNA_info->check_time <= (max_check_time - 1)) { + if (pDM_LNA_info->pre_sat_status && (!pDM_Odm->is_disable_gain_table_switch)) + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_2); + pDM_LNA_info->check_time++; + + } else if (pDM_LNA_info->check_time == max_check_time) { + if(!pDM_Odm->is_disable_gain_table_switch && (pDM_LNA_info->pre_sat_status == 1)) + phydm_set_ofdm_agc_tab(pDM_Odm, OFDM_AGC_TAB_0); + pDM_LNA_info->check_time = 0; + pDM_LNA_info->sat_cnt_acc_patha = 0; + pDM_LNA_info->sat_cnt_acc_pathb = 0; + pDM_LNA_info->pre_sat_status = pDM_LNA_info->cur_sat_status; + } + + agc_tab = phydm_get_ofdm_agc_tab(pDM_Odm); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("use AGC table %d\n", agc_tab)); + //func_end = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("function process time=%d\n", + // func_end - func_start)); + + // restore previous igi + ODM_Write_DIG(pDM_VOID, igi_restore); + + pDM_LNA_info->cur_timer_check_cnt++; + ODM_SetTimer(pDM_Odm, &pDM_LNA_info->phydm_lna_sat_chk_timer, pDM_Odm->lna_sat_chk_period_ms); +} + +void +phydm_lna_sat_chk_callback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n%s ==>\n", __FUNCTION__)); + phydm_lna_sat_chk(pDM_Odm); +} + +void +phydm_lna_sat_chk_timers( + IN PVOID pDM_VOID, + u8 state + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SATURATION_INFO pDM_LNA_info = &pDM_Odm->DM_LNA_SAT_INFO; + + if (state == INIT_LNA_SAT_CHK_TIMMER) { + ODM_InitializeTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer), + (RT_TIMER_CALL_BACK)phydm_lna_sat_chk_callback, NULL, "phydm_lna_sat_chk_timer"); + } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) { + ODM_CancelTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer)); + } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) { + ODM_ReleaseTimer(pDM_Odm, &(pDM_LNA_info->phydm_lna_sat_chk_timer)); + } +} + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + +void +phydm_reset_state_cnt( + IN PVOID pDM_VOID, + bool is_high_low_sel + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + pDM_DigTable->stay_check_state_cnt[is_high_low_sel] = 0; + pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] = 0; + pDM_DigTable->goto_release_state_cnt[is_high_low_sel] = 0; + pDM_DigTable->stay_release_state_cnt[is_high_low_sel] = 0; +} + +u1Byte +phydm_rx_gain_min_check( + IN PVOID pDM_VOID, + IN u1Byte dym_min, + IN u1Byte CurrentIGI, + IN u1Byte rx_gain_min, + bool is_high_low_sel + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS_ACC pFalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); + u4Byte fa_cca_ratio = pFalseAlmCntAcc->fa_cca_ratio[is_high_low_sel]; + u1Byte ori_check_state = pDM_DigTable->rx_gain_min_check_state[is_high_low_sel]; +// u1Byte ori_goto_lock_state_cnt = pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]; + bool is_enough_fa = (pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] >= pDM_Odm->tdma_is_enough_fa_th) ? 1 : 0; + bool high_fa_cca_ratio; + bool low_fa_cca_ratio; + /*rgm = rx_gain_min*/ + bool is_igi_less_eq_rgm = (CurrentIGI <= rx_gain_min) ? 1 : 0; + u4Byte debug_component; + + if (pDM_Odm->is_disable_rx_gain_min_check) { + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; + return dym_min; + } + + if (is_high_low_sel) { + high_fa_cca_ratio = ((fa_cca_ratio >= pDM_Odm->tdma_high_fa_cca_ratio_l2h) && (is_enough_fa==1)) ? 1 : 0; + low_fa_cca_ratio = ((fa_cca_ratio <= pDM_Odm->tdma_high_fa_cca_ratio_h2l) || (is_enough_fa==0)) ? 1 : 0; + + if (pDM_Odm->rx_gain_min_dbg_switch == TDMA_DIG_HIGH_STATE) + debug_component = ODM_COMP_TDMA_HDIG; + else + debug_component = 0; + } else { + high_fa_cca_ratio = ((fa_cca_ratio >= pDM_Odm->tdma_low_fa_cca_ratio_l2h) && (is_enough_fa==1)) ? 1 : 0; + low_fa_cca_ratio = ((fa_cca_ratio <= pDM_Odm->tdma_low_fa_cca_ratio_h2l) || (is_enough_fa==0)) ? 1 : 0; + if (pDM_Odm->rx_gain_min_dbg_switch == TDMA_DIG_LOW_STATE) + debug_component = ODM_COMP_TDMA_LDIG; + else + debug_component = 0; + } + + ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, + ("dym_min=0x%x,CurrentIGI=0x%x,rx_gain_min=0x%x,fa_cca_ratio=%d,is_high_low_sel=%d,is_enough_fa=%d\n", + dym_min, + CurrentIGI, + rx_gain_min, + fa_cca_ratio, + is_high_low_sel, + is_enough_fa)); + + ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, + ("check_state=%d,stay_check_state_cnt=%d,goto_lock_cnt=%d,goto_release_cnt=%d,stay_release_state_cnt=%d\n", + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel], + pDM_DigTable->stay_check_state_cnt[is_high_low_sel], + pDM_DigTable->goto_lock_state_cnt[is_high_low_sel], + pDM_DigTable->goto_release_state_cnt[is_high_low_sel], + pDM_DigTable->stay_release_state_cnt[is_high_low_sel])); + + if (ori_check_state == OSC_CHECK_STATE) { + + if (high_fa_cca_ratio) { + + if (pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] > 0) + pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]--; + + pDM_DigTable->stay_check_state_cnt[is_high_low_sel]++; + + if (pDM_DigTable->stay_check_state_cnt[is_high_low_sel] >= 3) { + rx_gain_min = rx_gain_min + 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; + ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, ("stay check_state.\n")); + } + } else if (low_fa_cca_ratio) { + + /*"if (CurrentIGI <= rx_gain_min)" is to avoid osc.*/ + + if (is_igi_less_eq_rgm) { + if (pDM_DigTable->stay_check_state_cnt[is_high_low_sel] > 0) + pDM_DigTable->stay_check_state_cnt[is_high_low_sel]--; + + pDM_DigTable->goto_lock_state_cnt[is_high_low_sel]++; + if (pDM_DigTable->goto_lock_state_cnt[is_high_low_sel] >= 3) { + rx_gain_min = rx_gain_min; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; + } + } + } + } + else if (ori_check_state == OSC_LOCK_STATE) { + /*rgm = rx_gain_min*/ + if (is_igi_less_eq_rgm) { + if (high_fa_cca_ratio) { + rx_gain_min = rx_gain_min + 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; + } else if (low_fa_cca_ratio) { + if ((rx_gain_min - 2) >= dym_min) { + pDM_DigTable->goto_release_state_cnt[is_high_low_sel]++; + if (pDM_DigTable->goto_release_state_cnt[is_high_low_sel] >= 6) { + + /*translate to RELEASE_STATE*/ + rx_gain_min = rx_gain_min - 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_RELEASE_STATE; + } + } else { + rx_gain_min = dym_min; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; + } + } + } + else { + /*not update rx_gain_min, back to check state to find suitable one.*/ + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; + } + } + + else if (ori_check_state == OSC_RELEASE_STATE) { + /*rgm = rx_gain_min*/ + if (is_igi_less_eq_rgm) { + if (low_fa_cca_ratio) { + + pDM_DigTable->stay_release_state_cnt[is_high_low_sel]++; + + if (pDM_DigTable->stay_release_state_cnt[is_high_low_sel] >= 3) { + if ((rx_gain_min - 2) >= dym_min) { + /*test success, keep trying lower rx_gain_min*/ + rx_gain_min = rx_gain_min - 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_RELEASE_STATE; + } else { + rx_gain_min= dym_min; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; + } + } + } else { + /*test fail, resume rx_gain_min*/ + rx_gain_min = rx_gain_min + 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_LOCK_STATE; + } + } + else { + /*wait igi comes down*/ + if (!low_fa_cca_ratio) { + rx_gain_min = rx_gain_min + 2; + phydm_reset_state_cnt(pDM_Odm, is_high_low_sel); + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel] = OSC_CHECK_STATE; + } + } + } + + ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, + ("check_state=%d,stay_check_state_cnt=%d,goto_lock_cnt=%d,goto_release_cnt=%d,stay_release_state_cnt=%d\n", + pDM_DigTable->rx_gain_min_check_state[is_high_low_sel], + pDM_DigTable->stay_check_state_cnt[is_high_low_sel], + pDM_DigTable->goto_lock_state_cnt[is_high_low_sel], + pDM_DigTable->goto_release_state_cnt[is_high_low_sel], + pDM_DigTable->stay_release_state_cnt[is_high_low_sel])); + + ODM_RT_TRACE(pDM_Odm, debug_component, ODM_DBG_LOUD, + ("rx_gain_min=0x%x\n", rx_gain_min)); + + return rx_gain_min; + +} + +void +phydm_tdma_dig_timers( + IN PVOID pDM_VOID, + u8 state + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + +// if (pDM_Odm->original_dig_restore) + { + if (state == INIT_TDMA_DIG_TIMMER) { + ODM_InitializeTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer), + (RT_TIMER_CALL_BACK)phydm_tdma_dig_call_back, NULL, "phydm_tdma_dig_timer"); + } else if (state == CANCEL_TDMA_DIG_TIMMER) { + ODM_CancelTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer)); + } else if (state == RELEASE_TDMA_DIG_TIMMER) { + ODM_ReleaseTimer(pDM_Odm, &(pDM_DigTable->phydm_tdma_dig_timer)); + } + } +} + +void +phydm_tdma_low_dig( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + // Common parameters + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte tdma_low_igi = pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]; + u1Byte DIG_MaxOfMin; + u1Byte tdma_low_dym_min; + u1Byte dm_dig_max, dm_dig_min; + u1Byte offset; + u1Byte rssi_min = pDM_Odm->RSSI_Min; + u1Byte igi_upper_rssi_min; + u4Byte dm_FA_thres[3]; + u4Byte TxTp = 0, RxTp = 0; + BOOLEAN bDFSBand = FALSE; + BOOLEAN bPerformance = TRUE; + BOOLEAN DIG_GoUpCheck = TRUE; + u1Byte step_size[3] = {0}; + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("%s ==>\n",__FUNCTION__)); + + step_size[2] = 2; + step_size[1] = 2; + step_size[0] = 2; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", + step_size[0], step_size[1], step_size[2])); + + //1 Mode decision + + bPerformance = TRUE; + + //1 Boundary Decision + { + dm_dig_max = DM_DIG_MAX_AP_COVERAGR; + dm_dig_min = DM_DIG_MIN_AP_COVERAGE; + DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; + + /* Modify lower bound for DFS band */ + if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || + ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) + ) { + bDFSBand = TRUE; + if (*pDM_Odm->pBandWidth == ODM_BW20M) + dm_dig_min = DM_DIG_MIN_AP_DFS+2; + else + dm_dig_min = DM_DIG_MIN_AP_DFS; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("In DFS band\n")); + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("abs UB=0x%x,LB=0x%x\n", dm_dig_max, dm_dig_min)); + + //1 Adjust boundary by RSSI + if(pDM_Odm->bLinked && bPerformance) + { + //2 Modify DIG upper bound + + offset = 15; + + igi_upper_rssi_min = rssi_min + offset; + + /*rx_gain_range_max*/ + if((igi_upper_rssi_min) > dm_dig_max) + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = dm_dig_max; + else if((igi_upper_rssi_min) < dm_dig_min) + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = dm_dig_min; + else + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = igi_upper_rssi_min; + + if (bDFSBand) + { + tdma_low_dym_min = dm_dig_min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("DFS band: Force LB to 0x%x after link\n", dm_dig_min)); + } else { + tdma_low_dym_min = dm_dig_min; + } + } + else + { + if(bPerformance && bDFSBand) + { + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, + ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE])); + } + else + { + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = 0x26; + } + tdma_low_dym_min = dm_dig_min; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("tdma_rx_gain_max=0x%x, tdma_low_dym_min=0x%x\n", + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], tdma_low_dym_min)); + + //1 Modify DIG lower bound, deal with abnormal case + //2 Abnormal false alarm case + if(!pDM_Odm->bLinked) + { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_low_dym_min; + } + else { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] + = phydm_rx_gain_min_check(pDM_Odm, tdma_low_dym_min, tdma_low_igi, pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE], TDMA_DIG_LOW_STATE); + } + + //2 Abnormal lower bound case + /*tdma_high_rx_gain_min*/ + if(pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] > pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]) + { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Abnrormal tdma_rx_gain_min: force to 0x%x\n\n", + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE])); + } + + //1 False alarm threshold decision + odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, + ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", + dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + //1 Adjust initial gain by false alarm + if(pDM_Odm->bLinked && bPerformance) + { + //2 After link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); + tdma_low_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_low_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_LOW_STATE); + + } else { + //2 Before link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, ("Adjust IGI before link\n")); + + tdma_low_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_low_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_LOW_STATE); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, + ("before check igi by ULbond, tdma_low_igi=0x%x\n\n", tdma_low_igi)); + + //1 Check initial gain by upper/lower bound + pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] = phydm_igi_chkby_upper_lower_bond(tdma_low_igi, pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, + ("ULbond,tdma_rx_gain_max=0x%x, tdma_rx_gain_min=0x%x\n", + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_LOW_STATE], + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_LDIG, ODM_DBG_LOUD, + ("after ULbond check, tdma_igi=0x%x\n", + pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE] + )); + + //1 Update status + + if (pDM_Odm->force_low_igi == 0xff) + ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]); + else + ODM_Write_DIG(pDM_Odm, pDM_Odm->force_low_igi); +} + + + +VOID +phydm_tdma_high_dig( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + // Common parameters + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte tdma_high_igi = pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE]; + u1Byte DIG_MaxOfMin; + u1Byte tdma_high_dym_min; + u1Byte dm_dig_max, dm_dig_min; + u1Byte offset; + u1Byte rssi_min = pDM_Odm->RSSI_Min; + u1Byte igi_upper_rssi_min; + u4Byte dm_FA_thres[3]; + u4Byte TxTp = 0, RxTp = 0; + BOOLEAN bDFSBand = FALSE; + BOOLEAN bPerformance = TRUE; + BOOLEAN DIG_GoUpCheck = TRUE; + u1Byte step_size[3] = {0}; + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("%s ==>\n\n",__FUNCTION__)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("tdma_high_igi=0x%x\n", tdma_high_igi)); + + step_size[2] = 2; + step_size[1] = 2; + step_size[0] = 2; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("step_size[0] = %d, step_size[1] = %d, step_size[2] = %d\n", + step_size[0], step_size[1], step_size[2])); + + //1 Mode decision + + bPerformance = TRUE; + + //1 Boundary Decision + { + if(!bPerformance) + { + dm_dig_max = DM_DIG_MAX_AP_COVERAGR; + dm_dig_min = DM_DIG_MIN_AP_COVERAGE; + DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; + } + else + { + if (pDM_Odm->RFType == ODM_1T1R) + dm_dig_max = DM_DIG_MAX_AP - 6; + else + dm_dig_max = 0x50; + + if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && (pDM_Odm->SupportICType & ODM_RTL8814A)) /* for 2G 8814 */ + dm_dig_min = 0x1c; + else if (pDM_Odm->SupportICType & ODM_RTL8197F) /*refine by YuChen 20160815 asked by RF Arthur*/ + dm_dig_min = 0x1e; + else + dm_dig_min = DM_DIG_MIN_AP; + + DIG_MaxOfMin = DM_DIG_MIN_AP_COVERAGE; + } + + //4 TX2path + if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) + dm_dig_max = 0x2A; + +#if RTL8192E_SUPPORT +#ifdef HIGH_POWER_EXT_LNA + if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) + dm_dig_max = 0x42; +#endif +#endif + /* Modify lower bound for DFS band */ + if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || + ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + && phydm_dfs_master_enabled(pDM_Odm) == TRUE + #endif + ) { + bDFSBand = TRUE; + if (*pDM_Odm->pBandWidth == ODM_BW20M) + dm_dig_min = DM_DIG_MIN_AP_DFS+2; + else + dm_dig_min = DM_DIG_MIN_AP_DFS; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("====== In DFS band ======\n")); + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); + + //1 Adjust boundary by RSSI + if(pDM_Odm->bLinked && bPerformance) + { + //2 Modify DIG upper bound + + //offset = 15; + + offset = pDM_Odm->rssi_to_igi_upper_offset; + + igi_upper_rssi_min = rssi_min + offset; + + /*tdma_high_rx_gain_max*/ + if((igi_upper_rssi_min) > dm_dig_max) + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = dm_dig_max; + else if((igi_upper_rssi_min) < dm_dig_min) + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = dm_dig_min; + else + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = igi_upper_rssi_min; + + if (bDFSBand) + { + tdma_high_dym_min = dm_dig_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); + } else { + /*tdma_high_dym_min(tdma_high_rx_gain_min)*/ + if(rssi_min < dm_dig_min) + tdma_high_dym_min = dm_dig_min; + else { + tdma_high_dym_min = (pDM_Odm->tdma_dig_turbo == 1) ? rssi_min : dm_dig_min; + } + } + } + else + { + if(bPerformance && bDFSBand) + { + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = 0x28; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("DFS band:Force upper bound to 0x%x before link.\n", pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] )); + } + else + { + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = DM_DIG_MAX_OF_MIN; + } + tdma_high_dym_min = dm_dig_min; + } + + //1 Force Lower Bound for AntDiv + if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) + { + if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { + if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) { + tdma_high_dym_min = DIG_MaxOfMin; + } + else { + tdma_high_dym_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Antenna diversity case: Force lower bound to 0x%x\n", + tdma_high_dym_min)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Antenna diversity case: RSSI_max=0x%x\n", + pDM_DigTable->AntDiv_RSSI_max)); + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("tdma_high_rx_gain_max=0x%x, tdma_high_dym_min = 0x%x\n", + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , tdma_high_dym_min)); + + //1 Modify DIG lower bound, deal with abnormal case + //2 Abnormal false alarm case + if(!pDM_Odm->bLinked) + { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_high_dym_min; + } + else { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] + = phydm_rx_gain_min_check(pDM_Odm, tdma_high_dym_min, tdma_high_igi, pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE], TDMA_DIG_HIGH_STATE); + } + + //2 Abnormal lower bound case + /*tdma_high_rx_gain_min*/ + if(pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] > pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] ) + { + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] ; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Abnrormal tdma_high_rx_gain_min: force to 0x%x\n\n", + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE])); + } + + //1 False alarm threshold decision + odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("False alarm threshold = %d, %d, %d \n\n", + dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + //1 Adjust initial gain by false alarm + if(pDM_Odm->bLinked && bPerformance) + { + //2 After link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("Adjust IGI after link\n")); + + tdma_high_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_high_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_HIGH_STATE); + } else { + //2 Before link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); + + tdma_high_igi = phydm_dig_current_igi_by_fa_th(pDM_Odm, tdma_high_igi, dm_FA_thres, step_size, DIG_GoUpCheck, TDMA_DIG_HIGH_STATE); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("before check igi by ULbond, tdma_high_igi=0x%x\n\n",tdma_high_igi)); + + //1 Check initial gain by upper/lower bound + pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE] = phydm_igi_chkby_upper_lower_bond(tdma_high_igi, pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("ULbond, tdma, high_rx_gain_max=0x%x high_rx_gain_min=0x%x\n", + pDM_DigTable->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] , + pDM_DigTable->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("after ULbond check,tdma_high_igi=0x%x\n", pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE])); + +} + +void +phydm_tdma_dig_timer_check( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if ((odm_DigAbort(pDM_Odm) == TRUE) || (pDM_Odm->original_dig_restore == 1)) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, + ("tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d, tdma_dig_timer_ms=%d\n", + pDM_DigTable->tdma_dig_cnt, + pDM_DigTable->pre_tdma_dig_cnt, + pDM_Odm->tdma_dig_timer_ms)); + + if((pDM_DigTable->tdma_dig_cnt == 0) || (pDM_DigTable->tdma_dig_cnt == pDM_DigTable->pre_tdma_dig_cnt)) { + + if(ODMPTR->SupportAbility & ODM_BB_DIG) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, + ("\ntdma dig timer Check fail, restart tdma_dig_timer!\n\n")); + + ODM_SetTimer(pDM_Odm, &pDM_DigTable->phydm_tdma_dig_timer, pDM_Odm->tdma_dig_timer_ms); + } + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, ("Check pass, update pre_tdma_dig_cnt\n")); + + pDM_DigTable->pre_tdma_dig_cnt = pDM_DigTable->tdma_dig_cnt; +} + +void +phydm_tdma_dig_call_back( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte reg_c50; + u1Byte total_state_number = pDM_Odm->total_state_number; + + if((odm_DigAbort(pDM_Odm) == TRUE) || (pDM_Odm->original_dig_restore == TRUE)) + return; + + // prevent dumb + if((total_state_number == 0) || (total_state_number == 1)) { + pDM_Odm->total_state_number = 2; + total_state_number = pDM_Odm->total_state_number; + } + + reg_c50 = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); + + pDM_DigTable->tdma_dig_state = (pDM_DigTable->tdma_dig_cnt % total_state_number); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, + ("tdma_dig_state=%d, regc50=0x%x, tdma_high_igi=0x%x, tdma_low_igi=0x%x\n", + pDM_DigTable->tdma_dig_state, + reg_c50, + pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE], + pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE])); + + pDM_DigTable->tdma_dig_cnt++; + + if (pDM_DigTable->tdma_dig_state == 1) { + + if (pDM_Odm->force_high_igi == 0xff) + ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_HIGH_STATE]); + else + ODM_Write_DIG(pDM_Odm, pDM_Odm->force_high_igi); + } else if (pDM_DigTable->tdma_dig_state == 0) { + + if (pDM_Odm->force_low_igi == 0xff) + ODM_Write_DIG(pDM_Odm, pDM_DigTable->tdma_igi[TDMA_DIG_LOW_STATE]); + else + ODM_Write_DIG(pDM_Odm, pDM_Odm->force_low_igi); + } + phydm_TDMA_FalseAlarmCounterCheck(pDM_Odm); + ODM_SetTimer(pDM_Odm, &pDM_DigTable->phydm_tdma_dig_timer, pDM_Odm->tdma_dig_timer_ms); +} + +VOID +phydm_TDMA_FalseAlarmCounterCheck( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + BOOLEAN one_sec_dump = pDM_DigTable->one_sec_dump; + u1Byte total_state_number = pDM_Odm->total_state_number; + u1Byte tdma_dig_state = pDM_DigTable->tdma_dig_state; + u1Byte i = 0; + u4Byte tdma_dig_block_period_ms = pDM_Odm->tdma_dig_timer_ms * total_state_number; + + /*caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms, or FA will be fewer.*/ + u4Byte tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms; + /*tdma_dig_state == 1, collect L-state FA, else, collect H-state FA*/ + bool is_high_low_sel = (tdma_dig_state == TDMA_DIG_HIGH_STATE)? 0: 1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, + ("tdma_dig_state=%d,tdma_dig_block_cnt=%d,one_sec_dump=%d,tdma_dig_block_cnt_thd=%d\n", + tdma_dig_state, + pDM_DigTable->tdma_dig_block_cnt, + pDM_DigTable->one_sec_dump, + tdma_dig_block_cnt_thd + )); + + if (tdma_dig_state == 0) { + + odm_FalseAlarmCounterStatistics(pDM_Odm); + /*collect to high/low FA by is_high_low_sel*/ + odm_FalseAlarmCounterAcc(pDM_Odm, one_sec_dump, is_high_low_sel); + odm_FalseAlarmCounterReset(pDM_Odm); + + if (one_sec_dump) { /*1sec H-state FA collect end*/ + + phydm_NoisyDetection(pDM_Odm); + odm_CCKPacketDetectionThresh(pDM_Odm); + // tdma dig + phydm_tdma_high_dig(pDM_Odm); + phydm_tdma_low_dig(pDM_Odm); + + for(i=0;i<=1;i++) + odm_FalseAlarmCounterAccReset(pDM_Odm, i); + pDM_DigTable->one_sec_dump = 0; + pDM_DigTable->tdma_dig_block_cnt = 0; + } + pDM_DigTable->tdma_dig_block_cnt++; + + /*1sec dump decision*/ + if (pDM_DigTable->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd){ + pDM_DigTable->one_sec_dump = 1; /*collect FA till this block end*/ + } + }else if (tdma_dig_state == 1) { + odm_FalseAlarmCounterStatistics(pDM_Odm); + /*collect to high/low FA by is_high_low_sel*/ + odm_FalseAlarmCounterAcc(pDM_Odm, one_sec_dump, is_high_low_sel); + odm_FalseAlarmCounterReset(pDM_Odm); + } +} + +VOID +odm_FalseAlarmCounterAcc( + IN PVOID pDM_VOID, + IN BOOLEAN one_sec_dump_en, + bool is_high_low_sel + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + PFALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc = &(pDM_Odm->FalseAlmCnt_Acc); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +// u4Byte ret_value; + u8 one_sec_numerator, one_sec_denumerator; + u8 total_state_number = pDM_Odm->total_state_number; + u32 Cnt_CCA_all_1sec, Cnt_all_1sec; + + FalseAlmCnt_Acc->Cnt_Parity_Fail[is_high_low_sel] += FalseAlmCnt->Cnt_Parity_Fail; + FalseAlmCnt_Acc->Cnt_Rate_Illegal[is_high_low_sel] += FalseAlmCnt->Cnt_Rate_Illegal; + FalseAlmCnt_Acc->Cnt_Crc8_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Crc8_fail; + FalseAlmCnt_Acc->Cnt_Mcs_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Mcs_fail; + FalseAlmCnt_Acc->Cnt_Ofdm_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Ofdm_fail; +// FalseAlmCnt_Acc->Cnt_Ofdm_fail_pre += FalseAlmCnt->Cnt_Parity_Fail; + FalseAlmCnt_Acc->Cnt_Cck_fail[is_high_low_sel] += FalseAlmCnt->Cnt_Cck_fail; + FalseAlmCnt_Acc->Cnt_all[is_high_low_sel] += FalseAlmCnt->Cnt_all; +// FalseAlmCnt_Acc->Cnt_all_pre += FalseAlmCnt->Cnt_all_pre; + FalseAlmCnt_Acc->Cnt_Fast_Fsync[is_high_low_sel] += FalseAlmCnt->Cnt_Fast_Fsync; + FalseAlmCnt_Acc->Cnt_SB_Search_fail[is_high_low_sel] += FalseAlmCnt->Cnt_SB_Search_fail; + FalseAlmCnt_Acc->Cnt_OFDM_CCA[is_high_low_sel] += FalseAlmCnt->Cnt_OFDM_CCA; + FalseAlmCnt_Acc->Cnt_CCK_CCA[is_high_low_sel] += FalseAlmCnt->Cnt_CCK_CCA; + FalseAlmCnt_Acc->Cnt_CCA_all[is_high_low_sel] += FalseAlmCnt->Cnt_CCA_all; +// FalseAlmCnt_Acc->Cnt_BW_USC += FalseAlmCnt->Cnt_BW_USC; +// FalseAlmCnt_Acc->Cnt_BW_LSC += FalseAlmCnt->Cnt_BW_LSC; + FalseAlmCnt_Acc->cnt_cck_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_cck_crc32_error; + FalseAlmCnt_Acc->cnt_cck_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_cck_crc32_ok; + FalseAlmCnt_Acc->cnt_ofdm_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_ofdm_crc32_error; + FalseAlmCnt_Acc->cnt_ofdm_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_ofdm_crc32_ok; + FalseAlmCnt_Acc->cnt_ht_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_ht_crc32_error; + FalseAlmCnt_Acc->cnt_ht_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_ht_crc32_ok; + FalseAlmCnt_Acc->cnt_vht_crc32_error[is_high_low_sel] += FalseAlmCnt->cnt_vht_crc32_error; + FalseAlmCnt_Acc->cnt_vht_crc32_ok[is_high_low_sel] += FalseAlmCnt->cnt_vht_crc32_ok; + FalseAlmCnt_Acc->cnt_crc32_error_all[is_high_low_sel] += FalseAlmCnt->cnt_crc32_error_all; + FalseAlmCnt_Acc->cnt_crc32_ok_all[is_high_low_sel] += FalseAlmCnt->cnt_crc32_ok_all; + + if(one_sec_dump_en == 1) { + + if(is_high_low_sel == TDMA_DIG_HIGH_STATE) { + one_sec_numerator = total_state_number; + one_sec_denumerator = total_state_number-1; + } else { + one_sec_numerator = total_state_number; + one_sec_denumerator = 1; + } + FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_all[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; + FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_CCA_all[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; + FalseAlmCnt_Acc->Cnt_Cck_fail_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_Cck_fail[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; + FalseAlmCnt_Acc->Cnt_Ofdm_fail_1sec[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_Ofdm_fail[is_high_low_sel] * one_sec_numerator / one_sec_denumerator; + + Cnt_all_1sec = FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]; + Cnt_CCA_all_1sec = FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel]; + + if (Cnt_CCA_all_1sec != 0) + FalseAlmCnt_Acc->fa_cca_ratio[is_high_low_sel] = (FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]*100) / FalseAlmCnt_Acc->Cnt_CCA_all_1sec[is_high_low_sel]; + else + FalseAlmCnt_Acc->fa_cca_ratio[is_high_low_sel] = FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel]; + + FalseAlmCnt_Acc->is_fa_bigger_cca[is_high_low_sel] = (Cnt_all_1sec > Cnt_CCA_all_1sec) ? 1 : 0; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TDMA_DIG_CALL_BACK, ODM_DBG_LOUD, + ("[%s] ==> tdma_dig_state=%d,one_sec_dump_en=%d,is_high_low_sel=%d,Cnt_all=%d,Cnt_all_1sec=%d\n\n", + __FUNCTION__, + pDM_DigTable->tdma_dig_state, + one_sec_dump_en, + is_high_low_sel, + FalseAlmCnt_Acc->Cnt_all[is_high_low_sel], + FalseAlmCnt_Acc->Cnt_all_1sec[is_high_low_sel] + )); + + +} + +VOID +odm_FalseAlarmCounterAccReset( + IN PVOID pDM_VOID, + u8 high_low_idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS_ACC FalseAlmCnt_Acc = &(pDM_Odm->FalseAlmCnt_Acc); + + //memset(FalseAlmCnt_Acc, 0, sizeof(pDM_Odm->FalseAlmCnt_Acc)); + + // Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump do NOT need to be reset + + FalseAlmCnt_Acc->Cnt_Parity_Fail[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_Rate_Illegal[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_Crc8_fail[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_Mcs_fail[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_Ofdm_fail[high_low_idx] = 0; +// FalseAlmCnt_Acc->Cnt_Ofdm_fail_pre = 0; + FalseAlmCnt_Acc->Cnt_Cck_fail[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_all[high_low_idx] = 0; +// FalseAlmCnt_Acc->Cnt_all_pre = 0; + FalseAlmCnt_Acc->Cnt_Fast_Fsync[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_SB_Search_fail[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_OFDM_CCA[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_CCK_CCA[high_low_idx] = 0; + FalseAlmCnt_Acc->Cnt_CCA_all[high_low_idx] = 0; +// FalseAlmCnt_Acc->Cnt_BW_USC = 0; +// FalseAlmCnt_Acc->Cnt_BW_LSC = 0; + FalseAlmCnt_Acc->cnt_cck_crc32_error[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_cck_crc32_ok[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_ofdm_crc32_error[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_ofdm_crc32_ok[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_ht_crc32_error[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_ht_crc32_ok[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_vht_crc32_error[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_vht_crc32_ok[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_crc32_error_all[high_low_idx] = 0; + FalseAlmCnt_Acc->cnt_crc32_ok_all[high_low_idx] = 0; + +} + + +#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) + +u1Byte +phydm_dig_current_igi_by_fa_th( + IN PVOID pDM_VOID, + u1Byte CurrentIGI, + pu4Byte dm_FA_thres, + pu1Byte step_size, + bool DIG_GoUpCheck, + u1Byte is_high_low_sel + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + PFALSE_ALARM_STATISTICS_ACC pFalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); + u1Byte tdma_dig_state = pDM_DigTable->tdma_dig_state; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("%s ==>\n",__FUNCTION__)); + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if ((pDM_Odm->original_dig_restore == 0) && (is_high_low_sel != NORMAL_DIG)) { + if((pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] > dm_FA_thres[2])) + CurrentIGI = CurrentIGI + step_size[2]; + else if ((pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] > dm_FA_thres[1])) + CurrentIGI = CurrentIGI + step_size[1]; + else if(pFalseAlmCntAcc->Cnt_all_1sec[is_high_low_sel] < dm_FA_thres[0]) + CurrentIGI = CurrentIGI - step_size[0]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("tdma_dig_state=%d,is_high_low_sel=%d\n", + tdma_dig_state, + is_high_low_sel)); + } else +#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) + { + if((pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) && DIG_GoUpCheck) + CurrentIGI = CurrentIGI + step_size[2]; + else if ((pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) && DIG_GoUpCheck) + CurrentIGI = CurrentIGI + step_size[1]; + else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) + CurrentIGI = CurrentIGI - step_size[0]; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG|ODM_COMP_TDMA_LDIG|ODM_COMP_TDMA_HDIG, ODM_DBG_LOUD, + ("final igi=0x%x,fa=%d,th0=%d th1=%d th2=%d\n", + CurrentIGI, + pFalseAlmCnt->Cnt_all, + dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + return CurrentIGI; + +} + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + + u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C + u1Byte CurrentIGI=pDM_Odm->RSSI_Min; + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS()==>\n")); + + // Using FW PS mode to make IGI + //Adjust by FA in LPS MODE + if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) + CurrentIGI = CurrentIGI+4; + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) + CurrentIGI = CurrentIGI+2; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) + CurrentIGI = CurrentIGI-2; + + + //Lower bound checking + + //RSSI Lower bound check + if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) + RSSI_Lower =(pDM_Odm->RSSI_Min-10); + else + RSSI_Lower =DM_DIG_MIN_NIC; + + //Upper and Lower Bound checking + if(CurrentIGI > DM_DIG_MAX_NIC) + CurrentIGI = DM_DIG_MAX_NIC; + else if(CurrentIGI < RSSI_Lower) + CurrentIGI = RSSI_Lower; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pFalseAlmCnt->Cnt_all = %d\n",pFalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pDM_Odm->RSSI_Min = %d\n",pDM_Odm->RSSI_Min)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): CurrentIGI = 0x%x\n",CurrentIGI)); + + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); +#endif +} + + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + #if (PHYDM_LA_MODE_SUPPORT == 1) + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + #endif + u4Byte ret_value; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +//Mark there, and check this in odm_DMWatchDog +#if 0 //(DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) + return; +#endif +#endif + + if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics()======>\n")); + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + odm_FalseAlarmCounterRegHold(pDM_Odm); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); + FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); + FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); + FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); + FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); + FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); + FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); + + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; + + /* read CCK CRC32 counter */ + FalseAlmCnt->cnt_cck_crc32_error = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, bMaskDWord); + FalseAlmCnt->cnt_cck_crc32_ok= ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_OK_CNT_11N, bMaskDWord); + + /* read OFDM CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11N, bMaskDWord); + FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; + + /* read HT CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11N, bMaskDWord); + FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; + + /* read VHT CRC32 counter */ + FalseAlmCnt->cnt_vht_crc32_error = 0; + FalseAlmCnt->cnt_vht_crc32_ok= 0; + +#if (RTL8188E_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); + FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); + } +#endif + + { + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); + FalseAlmCnt->Cnt_Cck_fail = ret_value; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); + FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); + } + + FalseAlmCnt->Cnt_all_pre = FalseAlmCnt->Cnt_all; + + FalseAlmCnt->time_fa_all = (FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail) * 12 + + (FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal) * 28 + + FalseAlmCnt->Cnt_Crc8_fail * 36 + + FalseAlmCnt->Cnt_Mcs_fail * 32 + + FalseAlmCnt->Cnt_Cck_fail * 80; + + FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + + FalseAlmCnt->Cnt_SB_Search_fail + + FalseAlmCnt->Cnt_Parity_Fail + + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Cck_fail); + + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; + + /* Get debug port 0 */ + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x0); + FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord); + + /* Get EDCCA flag */ + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); + FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, BIT30); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", + FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", + FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", + FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); + } +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + u4Byte CCKenable; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11AC, bMaskDWord); + FalseAlmCnt->Cnt_Fast_Fsync = ((ret_value & 0xffff0000) >> 16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11AC, bMaskDWord); + FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11AC, bMaskDWord); + FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff); + FalseAlmCnt->Cnt_Rate_Illegal = ((ret_value & 0xffff0000) >> 16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11AC, bMaskDWord); + FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff); + FalseAlmCnt->Cnt_Mcs_fail = ((ret_value & 0xffff0000) >> 16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE5_11AC, bMaskDWord); + FalseAlmCnt->cnt_crc8_fail_vht = (ret_value & 0xffff); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE6_11AC, bMaskDWord); + FalseAlmCnt->cnt_mcs_fail_vht = (ret_value & 0xffff); + + + /* read OFDM FA counter */ + FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); + + /* Read CCK FA counter */ + FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); + + /* read CCK/OFDM CCA counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11AC, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->Cnt_CCK_CCA = ret_value & 0xffff; + + /* read CCK CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_CNT_11AC, bMaskDWord); + FalseAlmCnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_cck_crc32_ok= ret_value & 0xffff; + + /* read OFDM CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11AC, bMaskDWord); + FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; + + /* read HT CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11AC, bMaskDWord); + FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; + + /* read VHT CRC32 counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_VHT_CRC32_CNT_11AC, bMaskDWord); + FalseAlmCnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->cnt_vht_crc32_ok= ret_value & 0xffff; + +#if (RTL8881A_SUPPORT==1) + /* For 8881A */ + if(pDM_Odm->SupportICType == ODM_RTL8881A) + { + u4Byte Cnt_Ofdm_fail_temp = 0; + + if(FalseAlmCnt->Cnt_Ofdm_fail >= FalseAlmCnt->Cnt_Ofdm_fail_pre) + { + Cnt_Ofdm_fail_temp = FalseAlmCnt->Cnt_Ofdm_fail_pre; + FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Ofdm_fail - Cnt_Ofdm_fail_temp; + } + else + FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail_pre)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail_pre=%d\n", Cnt_Ofdm_fail_temp)); + + /* Reset FA counter by enable/disable OFDM */ + if(FalseAlmCnt->Cnt_Ofdm_fail_pre >= 0x7fff) + { + // reset OFDM + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,1); + FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Reset false alarm counter\n")); + } + } +#endif + CCKenable = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28); + if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G) + { + FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_CCK_CCA + FalseAlmCnt->Cnt_OFDM_CCA; + } + else + { + FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail; + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA; + } + + #if (PHYDM_LA_MODE_SUPPORT == 1) + if (AdcSmp->ADCSmpState == ADCSMP_STATE_IDLE) + #endif + { + /* Get debug port 0 */ + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x0); + FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord); + + /* Get EDCCA flag */ + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); + FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, BIT30); + } + } +#endif + + odm_FalseAlarmCounterRegReset(pDM_Odm); + + FalseAlmCnt->time_fa_all = (FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail) * 12 + + (FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal) * 28 + + (FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->cnt_crc8_fail_vht + FalseAlmCnt->cnt_mcs_fail_vht) * 36 + + FalseAlmCnt->Cnt_Mcs_fail * 32 + + FalseAlmCnt->Cnt_Cck_fail * 80; + + FalseAlmCnt->cnt_crc32_error_all = FalseAlmCnt->cnt_vht_crc32_error + FalseAlmCnt->cnt_ht_crc32_error + FalseAlmCnt->cnt_ofdm_crc32_error + FalseAlmCnt->cnt_cck_crc32_error; + FalseAlmCnt->cnt_crc32_ok_all = FalseAlmCnt->cnt_vht_crc32_ok + FalseAlmCnt->cnt_ht_crc32_ok + FalseAlmCnt->cnt_ofdm_crc32_ok + FalseAlmCnt->cnt_cck_crc32_ok; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_OFDM_CCA=%d\n", FalseAlmCnt->Cnt_OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCK_CCA=%d\n", FalseAlmCnt->Cnt_CCK_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCA_all=%d\n", FalseAlmCnt->Cnt_CCA_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): CCK CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_cck_crc32_error, FalseAlmCnt->cnt_cck_crc32_ok)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): OFDM CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ofdm_crc32_error, FalseAlmCnt->cnt_ofdm_crc32_ok)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): HT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ht_crc32_error, FalseAlmCnt->cnt_ht_crc32_ok)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): VHT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_vht_crc32_error, FalseAlmCnt->cnt_vht_crc32_ok)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_crc32_error_all, FalseAlmCnt->cnt_crc32_ok_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): dbg port 0x0 = 0x%x, EDCCA = %d\n\n", FalseAlmCnt->dbg_port0, FalseAlmCnt->edcca_flag)); + +} + +// reset FA TSF also +VOID +odm_FalseAlarmCounterReset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + prtl8192cd_priv priv = pDM_Odm->priv; + u4Byte TSF; + + memset(FalseAlmCnt, 0, sizeof(pDM_Odm->FalseAlmCnt)); + odm_FalseAlarmCounterRegReset(pDM_Odm); +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if(pDM_DigTable->tdma_dig_state != 1) + pDM_DigTable->fa_acc_1sec_tsf = 0; + else +#endif + pDM_DigTable->fa_acc_1sec_tsf = pDM_DigTable->fa_acc_1sec_tsf; + + GET_HAL_INTERFACE(priv)->GetHwRegHandler(priv, HW_VAR_TSF_TIMER, (pu1Byte)&TSF); + pDM_DigTable->fa_start_tsf = TSF; + pDM_DigTable->fa_end_tsf = TSF; + +} + +VOID +odm_FalseAlarmCounterRegReset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + if (pDM_Odm->SupportICType >= ODM_RTL8188E) { + /*reset false alarm counter registers*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); + + /*update ofdm counter*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /*update page C counter*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /*update page D counter*/ + + /*reset CCK CCA counter*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); + + /*reset CCK FA counter*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); + + /*reset CRC32 counter*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 0); + } + } +#endif // #if (ODM_IC_11N_SERIES_SUPPORT == 1) + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + /* reset OFDM FA coutner */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); + + /* reset CCK FA counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); + + /* reset CCA counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 0); + } +#endif // #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + +} + +VOID +odm_FalseAlarmCounterRegHold( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //hold ofdm counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter + + //hold cck counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); + } +} + +//3============================================================ +//3 CCK Packet Detect Threshold +//3============================================================ + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte CCKPDThreshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection()=========> level = %d\n", pause_level)); + + if ((pDM_DigTable->pause_cckpd_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: SupportAbility ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseCCKPacketDetection(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], + pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); + + switch (PauseType) { + /* Pause CCK Packet Detection Threshold */ + case PHYDM_PAUSE: + { + /* Disable CCK PD */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_CCK_PD)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Pause CCK packet detection threshold !!\n")); + + /* Backup original CCK PD threshold decided by CCK PD mechanism */ + if (pDM_DigTable->pause_cckpd_level == 0) { + pDM_DigTable->CCKPDBackup = pDM_DigTable->CurCCK_CCAThres; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseCCKPacketDetection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup, CCKPDThreshold)); + } + + /* Update pause level */ + pDM_DigTable->pause_cckpd_level = (pDM_DigTable->pause_cckpd_level | BIT(pause_level)); + + /* Record CCK PD threshold */ + pDM_DigTable->pause_cckpd_value[pause_level] = CCKPDThreshold; + + /* Write new CCK PD threshold */ + if (BIT(pause_level + 1) > pDM_DigTable->pause_cckpd_level) { + ODM_Write_CCK_CCA_Thres(pDM_Odm, CCKPDThreshold); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): CCKPD of higher level = 0x%x\n", CCKPDThreshold)); + } + break; + } + /* Resume CCK Packet Detection Threshold */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((pDM_DigTable->pause_cckpd_level & (BIT(pause_level))) != 0) { + pDM_DigTable->pause_cckpd_level = pDM_DigTable->pause_cckpd_level & (~(BIT(pause_level))); + pDM_DigTable->pause_cckpd_value[pause_level] = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Resume CCK PD !!\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (pDM_DigTable->pause_cckpd_level == 0) { + /* Write backup IGI value */ + ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->CCKPDBackup); + /* pDM_DigTable->bIgnoreDIG = TRUE; */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write original CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup)); + + /* Enable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_CCK_PD); + break; + } + + if (BIT(pause_level) > pDM_DigTable->pause_cckpd_level) { + s1Byte max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((pDM_DigTable->pause_cckpd_level & BIT(max_level)) > 0) + break; + } + + /* write CCKPD of lower level */ + ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->pause_cckpd_value[max_level]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write CCKPD (0x%x) of level (%d)\n", + pDM_DigTable->pause_cckpd_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], + pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); +} + + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + PFALSE_ALARM_STATISTICS_ACC FalseAlmCntAcc = &(pDM_Odm->FalseAlmCnt_Acc); +#endif + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte CurCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres, RSSI_thd = 35; + u1Byte pd_th = 0, cs_ration = 0; + BOOLEAN en_2rcca; + + en_2rcca = ((BOOLEAN)ODM_GetBBReg(pDM_Odm, 0xa2c, BIT(18)) && (BOOLEAN)ODM_GetBBReg(pDM_Odm, 0xa2c, BIT(22))); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//modify by Guo.Mingzhi 2011-12-29 + if (pDM_Odm->bDualMacSmartConcurrent == TRUE) +// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) + return; + if(pDM_Odm->bBtHsOperation) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); + ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); + return; + } +#endif + + if((!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD)) ||(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() return==========\n")); +#ifdef MCR_WIRELESS_EXTEND + ODM_Write_CCK_CCA_Thres(pDM_Odm, 0x43); +#endif + return; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pDM_Odm->ExtLNA) + return; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() ==========>\n")); + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + if(pDM_Odm->original_dig_restore == 0) { + if (pDM_DigTable->cckFaMa == 0xffffffff) + pDM_DigTable->cckFaMa = FalseAlmCntAcc->Cnt_Cck_fail_1sec[TDMA_DIG_HIGH_STATE]; + else + pDM_DigTable->cckFaMa = ((pDM_DigTable->cckFaMa<<1) + pDM_DigTable->cckFaMa + FalseAlmCntAcc->Cnt_Cck_fail_1sec[TDMA_DIG_HIGH_STATE]) >> 2; + } else +#endif + { + if (pDM_DigTable->cckFaMa == 0xffffffff) + pDM_DigTable->cckFaMa = FalseAlmCnt->Cnt_Cck_fail; + else + pDM_DigTable->cckFaMa = ((pDM_DigTable->cckFaMa<<1) + pDM_DigTable->cckFaMa + FalseAlmCnt->Cnt_Cck_fail) >> 2; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh(): CCK FA moving average = %d\n", pDM_DigTable->cckFaMa)); + + if (pDM_Odm->bLinked) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (pDM_Odm->RSSI_Min > (RSSI_thd + 14)) + CurCCK_CCAThres = 0xed; + else if (pDM_Odm->RSSI_Min > (RSSI_thd + 6)) + CurCCK_CCAThres = 0xdd; + else if (pDM_Odm->RSSI_Min > RSSI_thd) + CurCCK_CCAThres = 0xcd; + else if (pDM_Odm->RSSI_Min > 20) { + if (pDM_DigTable->cckFaMa > ((DM_DIG_FA_TH1>>1) + (DM_DIG_FA_TH1>>3))) + CurCCK_CCAThres = 0xcd; + else if (pDM_DigTable->cckFaMa < (DM_DIG_FA_TH0>>1)) + CurCCK_CCAThres = 0x83; + } else if (pDM_Odm->RSSI_Min > 7) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; +#else + if (pDM_Odm->SupportICType & ODM_RTL8197F) { + if ((pDM_DigTable->CurIGValue > (0x24 + 14)) || (pDM_Odm->RSSI_Min > 26)) + CurCCK_CCAThres = 0xed; + else if ((pDM_DigTable->CurIGValue > (0x24 + 6)) || (pDM_Odm->RSSI_Min > 26)) + CurCCK_CCAThres = 0xdd; + else if ((pDM_DigTable->CurIGValue > 0x24) || (pDM_Odm->RSSI_Min > 20 && pDM_Odm->RSSI_Min <= 24)) + CurCCK_CCAThres = 0xcd; + else if ((pDM_DigTable->CurIGValue <= 0x24) || (pDM_Odm->RSSI_Min < 18)){ + if (pDM_DigTable->cckFaMa > 0x400) + CurCCK_CCAThres = 0x83; + else if (pDM_DigTable->cckFaMa < 0x200) + CurCCK_CCAThres = 0x40; + } + } else { + if (pDM_DigTable->CurIGValue > (0x24 + 14)) + CurCCK_CCAThres = 0xed; + else if (pDM_DigTable->CurIGValue > (0x24 + 6)) + CurCCK_CCAThres = 0xdd; + else if (pDM_DigTable->CurIGValue > 0x24) + CurCCK_CCAThres = 0xcd; + else { + if (pDM_DigTable->cckFaMa > 0x400) + CurCCK_CCAThres = 0x83; + else if (pDM_DigTable->cckFaMa < 0x200) + CurCCK_CCAThres = 0x40; + } + } +#endif + } else { + if (pDM_DigTable->cckFaMa > 0x400) + CurCCK_CCAThres = 0x83; + else if (pDM_DigTable->cckFaMa < 0x200) + CurCCK_CCAThres = 0x40; + } + + /*Add by Yu Chen 20160902, pd_th for 0xa0a, cs_ration for 0xaaa*/ + if (pDM_Odm->SupportICType & ODM_RTL8197F) { + switch (CurCCK_CCAThres) { + case 0xed: + cs_ration = pDM_DigTable->aaa_default + AAA_BASE + AAA_STEP*2; + if (en_2rcca) {cs_ration = cs_ration - 5;} + pd_th = 0xd; + break; + + case 0xdd: + cs_ration = pDM_DigTable->aaa_default + AAA_BASE + AAA_STEP; + if (en_2rcca) {cs_ration = cs_ration - 4;} + pd_th = 0xd; + break; + + case 0xcd: + cs_ration = pDM_DigTable->aaa_default + AAA_BASE; + if (en_2rcca) {cs_ration = cs_ration - 3;} + pd_th = 0xd; + break; + + case 0x83: + cs_ration = pDM_DigTable->aaa_default + AAA_STEP; + if (en_2rcca) {cs_ration = cs_ration - 1;} + pd_th = 0x3; + break; + + case 0x40: + cs_ration = pDM_DigTable->aaa_default; + pd_th = 0x3; + break; + + default: + cs_ration = pDM_DigTable->aaa_default; + pd_th = 0x3; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cck pd use default\n")); + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s : cs_ration = 0x%x, pd_th = 0x%x\n", __func__, cs_ration, pd_th)); + + if (pDM_Odm->SupportICType & ODM_RTL8197F) { + ODM_SetBBReg(pDM_Odm, 0xa08, 0xf0000, pd_th); + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, cs_ration); + } else + ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() CurCCK_CCAThres = 0x%x\n", CurCCK_CCAThres)); +} + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 + { + ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); + pDM_DigTable->cckFaMa = 0xffffffff; + } + pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; + pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; +} + +BOOLEAN +phydm_DIG_GoUpCheck( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte CurIGValue = pDM_DigTable->CurIGValue; + u1Byte max_DIG_cover_bond; + u1Byte current_IGI_MaxUp_resolution; + u1Byte rx_gain_range_max; + u1Byte i = 0; + + u4Byte total_NHM_cnt; + u4Byte DIG_cover_cnt; + u4Byte over_DIG_cover_cnt; + BOOLEAN ret = TRUE; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + + max_DIG_cover_bond = DM_DIG_MAX_AP - priv->pshare->rf_ft_var.dig_upcheck_initial_value; + current_IGI_MaxUp_resolution = CurIGValue + 6; + rx_gain_range_max = pDM_DigTable->rx_gain_range_max; + + phydm_getNHMresult(pDM_Odm); + + total_NHM_cnt = CCX_INFO->NHM_result[0] + CCX_INFO->NHM_result[1]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Get NHM results*****\n")); + + if (total_NHM_cnt != 0) { + + /* CurIGValue < max_DIG_cover_bond - 6 */ + if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_0) { + DIG_cover_cnt = CCX_INFO->NHM_result[1]; + ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? TRUE : FALSE; + } + + /* (max_DIG_cover_bond - 6) <= CurIGValue < DM_DIG_MAX_AP */ + else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_1) { + over_DIG_cover_cnt = CCX_INFO->NHM_result[1]; + ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? TRUE : FALSE; + + if (!ret) { + /* update pDM_DigTable->rx_gain_range_max */ + pDM_DigTable->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", + pDM_DigTable->rx_gain_range_max)); + } + } + + /* CurIGValue > DM_DIG_MAX_AP, foolproof */ + else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_2) { + ret = TRUE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n, current_IGI_MaxUp_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", + pDM_DigTable->DIG_GoUpCheck_Level, + current_IGI_MaxUp_resolution, + max_DIG_cover_bond, + pDM_DigTable->rx_gain_range_max, + ret)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_result = %d, %d, %d, %d\n", + CCX_INFO->NHM_result[0], CCX_INFO->NHM_result[1], CCX_INFO->NHM_result[2], CCX_INFO->NHM_result[3])); + + } + else + ret = TRUE; + + for (i = 0 ; i <= 10 ; i ++) { + CCX_INFO->NHM_th[i] = 0xFF; + } + + if (CurIGValue < max_DIG_cover_bond - 6){ + CCX_INFO->NHM_th[0] = 2 * (CurIGValue - priv->pshare->rf_ft_var.dig_upcheck_initial_value); + pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_0; + } + else if (CurIGValue <= DM_DIG_MAX_AP) { + CCX_INFO->NHM_th[0] = 2 * max_DIG_cover_bond; + pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_1; + } + /* CurIGValue > DM_DIG_MAX_AP, foolproof */ + else { + pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_2; + ret = TRUE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Set NHM settings*****\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n", + pDM_DigTable->DIG_GoUpCheck_Level)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_th = 0x%x, 0x%x, 0x%x\n", + CCX_INFO->NHM_th[0], CCX_INFO->NHM_th[1], CCX_INFO->NHM_th[2])); + + CCX_INFO->NHM_inexclude_cca = NHM_EXCLUDE_CCA; + CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; + CCX_INFO->NHM_period = 0xC350; + + phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); + phydm_NHMtrigger(pDM_Odm); +#endif + + return ret; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +// <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) +VOID +odm_RFEControl( + IN PDM_ODM_T pDM_Odm, + IN u8Byte RSSIVal + ) +{ + PADAPTER Adapter = (PADAPTER)pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + static u1Byte TRSW_HighPwr = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n", + RSSIVal, TRSW_HighPwr, pHalData->RFEType )); + + if (pHalData->RFEType == 3) { + + pDM_Odm->RSSI_TRSW = RSSIVal; + + if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H) + { + TRSW_HighPwr = 1; // Switch to + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); // Set ANTSW=1/ANTSWB=0 for SW control + + } + else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L) + { + TRSW_HighPwr = 0; // Switched back + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0); // Set ANTSW=1/ANTSWB=0 for SW control + + } + } + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", + RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr)); +} + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_MPT_DIG(pDM_Odm); +} + +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + + #if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); + #else + ODM_MPT_DIG(pDM_Odm); + #endif + #else + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); + #endif + +} + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); +#else + ODM_MPT_DIG(pDM_Odm); +#endif +} +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) +VOID +odm_MPT_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurIGValue +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), CurIGValue); + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + /* Set IGI value of CCK for new CCK AGC */ + if (pDM_Odm->cck_new_agc) { + if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) + ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurIGValue>>1)); + } + +#endif + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), CurIGValue); + + if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) + { + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_C,pDM_Odm), CurIGValue); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_D,pDM_Odm), CurIGValue); + } + + pDM_DigTable->CurIGValue = CurIGValue; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurIGValue = 0x%x\n", CurIGValue)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("pDM_Odm->RFType = 0x%x\n", pDM_Odm->RFType)); +} + +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte CurrentIGI = pDM_DigTable->CurIGValue; + u1Byte DIG_Upper = 0x40, DIG_Lower = 0x20; + u4Byte RXOK_cal; + u4Byte RxPWDBAve_final; + u1Byte IGI_A = 0x20, IGI_B = 0x20; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #if ODM_FIX_2G_DIG + IGI_A = 0x22; + IGI_B = 0x24; + #endif + +#else + if (!(pDM_Odm->priv->pshare->rf_ft_var.mp_specific && pDM_Odm->priv->pshare->mp_dig_on)) + return; + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + DIG_Lower = 0x22; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType)); + +#if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) + if (*pDM_Odm->pBandType == ODM_BAND_5G || (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) // for 5G or 8814 +#else + if (1) // for both 2G/5G +#endif + { + odm_FalseAlarmCounterStatistics(pDM_Odm); + + RXOK_cal = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM; + RxPWDBAve_final = (RXOK_cal != 0)?pDM_Odm->RxPWDBAve/RXOK_cal:0; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->RxPWDBAve = 0; + pDM_Odm->MPDIG_2G = FALSE; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->Times_2G = 0; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", RXOK_cal)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", RxPWDBAve_final)); + + if (RXOK_cal >= 70 && RxPWDBAve_final <= 40) + { + if (CurrentIGI > 0x24) + odm_MPT_Write_DIG(pDM_Odm, 0x24); + } + else + { + if(pFalseAlmCnt->Cnt_all > 1000){ + CurrentIGI = CurrentIGI + 8; + } + else if(pFalseAlmCnt->Cnt_all > 200){ + CurrentIGI = CurrentIGI + 4; + } + else if (pFalseAlmCnt->Cnt_all > 50){ + CurrentIGI = CurrentIGI + 2; + } + else if (pFalseAlmCnt->Cnt_all < 2){ + CurrentIGI = CurrentIGI - 2; + } + + if (CurrentIGI < DIG_Lower ){ + CurrentIGI = DIG_Lower; + } + + if(CurrentIGI > DIG_Upper){ + CurrentIGI = DIG_Upper; + } + + odm_MPT_Write_DIG(pDM_Odm, CurrentIGI); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", + CurrentIGI, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail)); + } + } + else + { + if(pDM_Odm->MPDIG_2G == FALSE) + { + if((pDM_Odm->SupportPlatform & ODM_WIN) && !(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), IGI_A); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), IGI_B); + pDM_DigTable->CurIGValue = IGI_B; + } + else + odm_MPT_Write_DIG(pDM_Odm, IGI_A); + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->Times_2G++; + + if (pDM_Odm->Times_2G == 3) +#endif + { + pDM_Odm->MPDIG_2G = TRUE; + } + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8812) + odm_RFEControl(pDM_Odm, RxPWDBAve_final); +#endif + + ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700); +} +#endif + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + +void +phydm_lna_sat_chk_type2_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; +// u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; + + u1Byte real_shift = pDM_Odm->total_bit_shift; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); + + pinfo->total_cnt_snr_statistic = 1 << real_shift; + pinfo->is_sm_done = TRUE; + pinfo->is_snr_done = FALSE; + pinfo->cur_snr_mean = 0; + pinfo->cur_snr_var = 0; + pinfo->cur_lower_snr_mean = 0; + pinfo->pre_snr_mean = 0; + pinfo->pre_snr_var = 0; + pinfo->pre_lower_snr_mean = 0; + pinfo->nxt_state = ORI_TABLE_MONITOR; + pinfo->pre_state = ORI_TABLE_MONITOR; + +} + +void +phydm_snr_collect( + IN PVOID pDM_VOID, + IN u8 rx_snr + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + if (pinfo->is_sm_done == TRUE) { + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); + + /* adapt only path-A for calculation */ + pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr; +// pinfo->sum_snr_statistic += rx_snr; + + if(pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr_statistic - 1)) { + pinfo->is_snr_done = TRUE; + pinfo->cnt_snr_statistic = 0; + } else { + pinfo->cnt_snr_statistic++; + } + } else { + return; + } +} + + +void +phydm_snr_data_processing( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + +// u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; + u1Byte real_shift = pDM_Odm->total_bit_shift; + u2Byte total_snr_cnt = pinfo->total_cnt_snr_statistic; + u2Byte total_loop_cnt = (total_snr_cnt - 1), i; + u4Byte temp; + u4Byte sum_snr_statistic = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("total_loop_cnt=%d\n", total_loop_cnt)); + + for(i = 0; (i <= total_loop_cnt); i++) { + + if (pDM_Odm->is_snr_detail_en) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("snr[%d]=%d\n", i, pinfo->snr_statistic[i])); + } + + sum_snr_statistic += pinfo->snr_statistic[i]; + + pinfo->snr_statistic_sqr[i] = + pinfo->snr_statistic[i] * pinfo->snr_statistic[i]; + } + + phydm_bubble_sort(pDM_Odm, pinfo->snr_statistic, pinfo->total_cnt_snr_statistic); + + /*update SNR's cur mean*/ + pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift); + + for(i = 0; (i <= total_loop_cnt); i++) { + + if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean) + temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean; + else + temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i]; + + pinfo->cur_snr_var += (temp*temp); + } +/* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("snr_higher_cnt=%d, snr_lower_cnt=%d\n", snr_higher_cnt, snr_lower_cnt)); +*/ + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("pinfo->cur_snr_var\n", pinfo->cur_snr_var)); + + /*update SNR's VAR*/ + pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift); + + /*acquire lower SNR's statistics*/ + temp = 0; + pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pDM_Odm->lwr_snr_ratio_bit_shift); + for(i = 0; i <= pinfo->cnt_lower_snr_statistic; i++) { + temp += pinfo->snr_statistic[i]; + } + + pinfo->cur_lower_snr_mean = temp >> (real_shift - pDM_Odm->lwr_snr_ratio_bit_shift); + + /*update cnt_lower_snr_statistic*/ + +} + + +bool +phydm_is_snr_improve( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; +// bool is_mean_improve = FALSE, is_var_improve = FALSE; + bool is_snr_improve; + u1Byte cur_state = pinfo->nxt_state; + u4Byte cur_mean = pinfo->cur_snr_mean; + u4Byte pre_mean = pinfo->pre_snr_mean; + u4Byte cur_lower_mean = pinfo->cur_lower_snr_mean; + u4Byte pre_lower_mean = pinfo->pre_lower_snr_mean; + u4Byte cur_var = pinfo->cur_snr_var; +// u4Byte pre_var = pinfo->pre_snr_var; +// u4Byte diff_var=0, diff_mean=0; + + /*special case, zero VAR, interference is gone*/ + if ((cur_state == SAT_TABLE_MONITOR) || (cur_state == ORI_TABLE_TRAINING)) { /*make sure pre_var is larger enough*/ + if (cur_mean >= pre_mean) { + if (cur_var == 0) + return TRUE; + } + } + + /*special case, mean degrade less than VAR improvement*/ +/* + if (cur_state == ORI_TABLE_MONITOR) { //make sure pre_var is larger enough + if (cur_mean < pre_mean) { + if (cur_var < pre_var) { + diff_mean = pre_mean - cur_mean; + diff_var = pre_var - cur_var; + return (diff_var > (2*diff_mean*diff_mean)) ? TRUE:FALSE; + } + } + } +*/ + + if (cur_lower_mean >= (pre_lower_mean + pDM_Odm->delta_snr_mean)) { + is_snr_improve = TRUE; + } else { + is_snr_improve = FALSE; + } + + /* condition refine, mean is bigger enough or VAR is smaller enough */ + /* 1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/ +/* + if (cur_mean > (pre_mean + pDM_Odm->delta_snr_mean)) { + is_mean_improve = TRUE; + is_var_improve = (cur_var <= pre_var + pDM_Odm->delta_snr_var) ? TRUE : FALSE; + + } else if (cur_var + pDM_Odm->delta_snr_var <= pre_var) { + is_var_improve = TRUE; + is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE; + } else { + return false; + } +*/ + return is_snr_improve; +} + +bool +phydm_is_snr_degrade( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; +// bool is_mean_dgrade = FALSE, is_var_degrade = FALSE; + u4Byte cur_lower_mean = pinfo->cur_lower_snr_mean; + u4Byte pre_lower_mean = pinfo->pre_lower_snr_mean; + bool is_degrade; + + if (cur_lower_mean <= (pre_lower_mean - pDM_Odm->delta_snr_mean)) { + is_degrade = TRUE; + } else { + is_degrade = FALSE; + } + +/* + is_mean_dgrade = (pinfo->cur_snr_mean + pDM_Odm->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE; + is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pDM_Odm->delta_snr_mean)) ? TRUE : FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n", + __FUNCTION__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var)); + + return (is_mean_dgrade & is_var_degrade); +*/ + return is_degrade; +} + +bool +phydm_is_large_var( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + bool is_large_var = (pinfo->cur_snr_var >= pDM_Odm->snr_var_thd) ? TRUE : FALSE; + + return is_large_var; +} + +void +phydm_update_pre_status( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean; + pinfo->pre_snr_mean = pinfo->cur_snr_mean; + pinfo->pre_snr_var = pinfo->cur_snr_var; +} + +void +phydm_ori_table_monitor( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + if (phydm_is_large_var(pDM_Odm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + /*switch to anti-sat table*/ + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + } + phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = ORI_TABLE_MONITOR; + +} + +void +phydm_sat_table_training( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + /* if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL, + "pre" adapt ori-table, "cur" adapt sat-table */ + + /*adapt ori table*/ +/* + if (pinfo->pre_state == ORI_TABLE_MONITOR) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s bypass update pre status statistics once.\n", __FUNCTION__)); + } else { + */ + if (phydm_is_snr_improve(pDM_Odm)) { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + } +// } + + phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = SAT_TABLE_TRAINING; + +} + +void +phydm_sat_table_try_fail( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + /* if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */ + /* if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */ + + if (phydm_is_large_var(pDM_Odm)) { + if (phydm_is_snr_degrade(pDM_Odm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } + phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = SAT_TABLE_TRY_FAIL; +} + +void +phydm_sat_table_monitor( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + if (phydm_is_snr_improve(pDM_Odm)) { + + pinfo->sat_table_monitor_times = 0; + + /* if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */ + if (pinfo->pre_state == SAT_TABLE_MONITOR) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + //phydm_update_pre_status(pDM_Odm); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } + + /* if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */ + /* if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */ + /*pre_state above is no need to update*/ + } else { + + if (pinfo->sat_table_monitor_times == pDM_Odm->force_change_period) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("%s: sat_table_monitor_times=%d\n", __FUNCTION__, pinfo->sat_table_monitor_times)); + + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->sat_table_monitor_times = 0; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + pinfo->sat_table_monitor_times++; + } + } + phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = SAT_TABLE_MONITOR; +} + +void +phydm_ori_table_training( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + /* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */ + + if (phydm_is_snr_degrade(pDM_Odm) == FALSE) { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } else { + if (pinfo->pre_snr_var == 0) { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = ORI_TABLE_TRAINING; +} + +void +phydm_ori_table_try_fail( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + + // if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table + // if pre_state = ORI_TABLE_TRY_FAIL, "pre" adapt sat-table, "cur" adapt sat-table + + if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) { + if (phydm_is_snr_improve(pDM_Odm)) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->ori_table_try_fail_times = 0; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + } else { + if (pinfo->ori_table_try_fail_times == pDM_Odm->force_change_period) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("%s: ori_table_try_fail_times=%d\n",__FUNCTION__, pinfo->ori_table_try_fail_times)); + + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->ori_table_try_fail_times = 0; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + phydm_update_pre_status(pDM_Odm); + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times++; + phydm_update_pre_status(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("%s: ori_table_try_fail_times=%d\n",__FUNCTION__, pinfo->ori_table_try_fail_times)); + //config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + } + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times = 0; + phydm_update_pre_status(pDM_Odm); + //config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + +/* + if (phydm_is_large_var(pDM_Odm)) { + if (phydm_is_snr_degrade(pDM_Odm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + } + else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } +*/ + //phydm_update_pre_status(pDM_Odm); + pinfo->pre_state = ORI_TABLE_TRY_FAIL; +} + +char * phydm_lna_sat_state_msg( + IN PVOID pDM_VOID, + IN u1Byte state + ) +{ + char *dbg_message; + + switch(state) { + + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRY_FAIL"; + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + break; + } + + return dbg_message; +} + +void +phydm_lna_sat_type2_sm( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +// pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PLNA_SAT_TYPE2_INFO pinfo = &pDM_Odm->DM_LNA_SAT_TYPE2_INFO; + u1Byte state = pinfo->nxt_state; + u1Byte agc_tab = ODM_GetBBReg(pDM_Odm, 0x958, 0x1f); + char *dbg_message,*nxt_dbg_message; + //u1Byte real_shift = (pDM_Odm->total_bit_shift!=0)? (pDM_Odm->total_bit_shift): SNR_STATISTIC_SHIFT; + u1Byte real_shift = pDM_Odm->total_bit_shift; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("\n\n%s ==>\n", __FUNCTION__)); + + if ((pDM_Odm->SupportICType & ODM_RTL8822B) == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n")); + return; + } + + if((pDM_Odm->SupportAbility & ODM_BB_LNA_SAT_CHK_TYPE2) == FALSE) { + phydm_lna_sat_chk_type2_init(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n",agc_tab)); + return; + } + + if (pinfo->is_snr_done) + phydm_snr_data_processing(pDM_Odm); + else + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("cur agc table %d\n", agc_tab)); + + if (pDM_Odm->is_force_lna_sat_table != AUTO_AGC_TABLE) { + + //reset state machine + pinfo->nxt_state = ORI_TABLE_MONITOR; + if (pinfo->is_snr_done) { + + if (pDM_Odm->is_force_lna_sat_table == DEFAULT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + else if (pDM_Odm->is_force_lna_sat_table == LNA_SAT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, LNA_SAT_AGC_TABLE); + else + config_phydm_switch_agc_tab_8822b(pDM_Odm, *pDM_Odm->pChannel, DEFAULT_AGC_TABLE); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __FUNCTION__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic)); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + phydm_update_pre_status(pDM_Odm); + } else + return; + } else if (pinfo->is_snr_done) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, + ("%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __FUNCTION__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic)); + + switch(state) { + + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(pDM_Odm); + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + phydm_sat_table_training(pDM_Odm); + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + phydm_sat_table_try_fail(pDM_Odm); + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + phydm_sat_table_monitor(pDM_Odm); + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_training(pDM_Odm); + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_try_fail(pDM_Odm); + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(pDM_Odm); + break; + + } + + dbg_message = phydm_lna_sat_state_msg(pDM_Odm, state); + nxt_dbg_message = phydm_lna_sat_state_msg(pDM_Odm, pinfo->nxt_state); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("state: [%s]->[%s], \n", dbg_message, nxt_dbg_message)); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + pinfo->total_cnt_snr_statistic = 1 << real_shift; + + }else { + return; + } + +} + +void +phydm_bubble_sort( + IN PVOID pDM_VOID, + IN u1Byte *array, + IN u2Byte array_length +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte i, j; // iterator + u1Byte temp; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_LNA_SAT_CHK, ODM_DBG_LOUD, ("%s ==>\n", __FUNCTION__)); + for(i = 0; i < (array_length-1); i++){ + for (j = (i+1); j < (array_length); j++) { + if(array[i] > array[j]) { + //phydm_bubble_swap(array, i, j); + temp = array[i]; + array[i] = array[j]; + array[j] = temp; + } + } + } +} + +#endif //#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) diff --git a/package/kernel/rtl8192cd/phydm/phydm_dig.h b/package/kernel/rtl8192cd/phydm/phydm_dig.h index 1d4c64e81ad..1c97ff2055e 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dig.h +++ b/package/kernel/rtl8192cd/phydm/phydm_dig.h @@ -1,726 +1,726 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMDIG_H__ -#define __PHYDMDIG_H__ - -#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ -#define DIG_HW 1 - -enum lna_sat_chk_timmer { - INIT_LNA_SAT_CHK_TIMMER, - CANCEL_LNA_SAT_CHK_TIMMER, - RELEASE_LNA_SAT_CHK_TIMMER -}; -enum tdma_dig_timer { - INIT_TDMA_DIG_TIMMER, - CANCEL_TDMA_DIG_TIMMER, - RELEASE_TDMA_DIG_TIMMER -}; -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - - #define DELTA_STD 2 - #define DELTA_MEAN 2 - #define SNR_STATISTIC_SHIFT 8 - - enum lna_sat_chk_type2_status { - - ORI_TABLE_MONITOR, - ORI_TABLE_TRAINING, - SAT_TABLE_MONITOR, - SAT_TABLE_TRAINING, - SAT_TABLE_TRY_FAIL, - ORI_TABLE_TRY_FAIL - }; - - -#endif -#define RSSI_TO_IGI 10 -#define ONE_SEC_MS 1000 -#define OFDM_AGC_TAB_0 0 -#define OFDM_AGC_TAB_2 2 - -/* Pause DIG & CCKPD */ -#define DM_DIG_MAX_PAUSE_TYPE 0x7 -#define ONE_SEC_MS 1000 - -enum is_high_low_sel { - TDMA_DIG_LOW_STATE = 0, - TDMA_DIG_HIGH_STATE = 1, - NORMAL_DIG = 2 -}; - -enum rx_gain_min_check_state { - OSC_CHECK_STATE = 0, - OSC_LOCK_STATE = 1, - OSC_RELEASE_STATE = 2 -}; - -enum fa_cca_ratio_thd { - FA_CCA_RATIO_L2H = 50, - FA_CCA_RATIO_H2L = 40 -}; -typedef enum tag_DIG_GoUpCheck_Level { - - DIG_GOUPCHECK_LEVEL_0, - DIG_GOUPCHECK_LEVEL_1, - DIG_GOUPCHECK_LEVEL_2 - -} DIG_GOUPCHECK_LEVEL; - -#ifdef CFG_DIG_DAMPING_CHK -#define DIG_RECORD_NUM 4 -#define DIG_LIMIT_PERIOD 60 /*60 sec*/ - -struct phydm_dig_recoder_strcut { - u8 igi_bitmap; /*Do not add any new parameter before this*/ - u8 igi_history[DIG_RECORD_NUM]; - u32 fa_history[DIG_RECORD_NUM]; - u8 damping_limit_en; - u8 damping_limit_val; /*Limit IGI_dyn_min*/ - u32 limit_time; - u8 limit_rssi; -}; -#endif - -typedef struct _Dynamic_Initial_Gain_Threshold_ -{ -#ifdef CFG_DIG_DAMPING_CHK - struct phydm_dig_recoder_strcut dig_recoder_t; - u8 dig_dl_en; /*damping limit function enable*/ -#endif - u16 fa_th[3]; - BOOLEAN bStopDIG; // for debug - BOOLEAN bIgnoreDIG; - BOOLEAN bPSDInProgress; - - u1Byte Dig_Enable_Flag; - u1Byte Dig_Ext_Port_Stage; - - int RssiLowThresh; - int RssiHighThresh; - - u4Byte FALowThresh; - u4Byte FAHighThresh; - - u1Byte CurSTAConnectState; - u1Byte PreSTAConnectState; - u1Byte CurMultiSTAConnectState; - - u1Byte PreIGValue; - u1Byte CurIGValue; -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - u1Byte tdma_igi[2]; - RT_TIMER phydm_tdma_dig_timer; - u1Byte tdma_rx_gain_max[2]; - u1Byte tdma_rx_gain_min[2]; - - /*phydm_rx_gain_min_check*/ - u1Byte rx_gain_min_check_state[2]; //for tdma use - u1Byte stay_check_state_cnt[2]; // check state - u1Byte goto_lock_state_cnt[2]; // check state - u1Byte goto_release_state_cnt[2]; // lock state - u1Byte stay_release_state_cnt[2]; // release state -#endif - - u1Byte BackupIGValue; //MP DIG - u1Byte BT30_CurIGI; - u1Byte IGIBackup; - - s1Byte BackoffVal; - s1Byte BackoffVal_range_max; - s1Byte BackoffVal_range_min; - u1Byte rx_gain_range_max; - u1Byte rx_gain_range_min; - u1Byte Rssi_val_min; - - u1Byte PreCCK_CCAThres; - u1Byte CurCCK_CCAThres; - u1Byte PreCCKPDState; - u1Byte CurCCKPDState; - u1Byte CCKPDBackup; - u1Byte pause_cckpd_level; - u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - - u1Byte LargeFAHit; - u1Byte LargeFA_Timeout; /*if (LargeFAHit), monitor "LargeFA_Timeout" sec, if timeout, LargeFAHit=0*/ - u1Byte ForbiddenIGI; - u4Byte Recover_cnt; - - u1Byte DIG_Dynamic_MIN_0; - u1Byte DIG_Dynamic_MIN_1; - BOOLEAN bMediaConnect_0; - BOOLEAN bMediaConnect_1; - - u4Byte AntDiv_RSSI_max; - u4Byte RSSI_max; - - u1Byte *bP2PInProcess; - - u1Byte pause_dig_level; - u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - - u4Byte cckFaMa; - DIG_GOUPCHECK_LEVEL DIG_GoUpCheck_Level; - u1Byte aaa_default; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - BOOLEAN bTpTarget; - BOOLEAN bNoiseEst; - u4Byte TpTrainTH_min; - u1Byte IGIOffset_A; - u1Byte IGIOffset_B; -#endif - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - u1Byte rfGainIdx; - u1Byte agcTableIdx; - u1Byte bigJumpLmt[16]; - u1Byte enableAdjustBigJump:1; - u1Byte bigJumpStep1:3; - u1Byte bigJumpStep2:2; - u1Byte bigJumpStep3:2; -#endif - -#if (DIG_HW == 1) - u1Byte pre_rssi_min; -#endif - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - u1Byte tdma_dig_state; - u1Byte tdma_dig_cnt; // for timer check - u1Byte tdma_dig_block_cnt; // for high/low state false alarm statistics - bool one_sec_dump; - u1Byte pre_tdma_dig_cnt; -#endif - u1Byte normalize_1sec_factor; - u4Byte pre_tsf; - u4Byte cur_tsf; - u4Byte fa_start_tsf; - u4Byte fa_end_tsf; - u4Byte fa_acc_1sec_tsf; -}DIG_T,*pDIG_T; - -typedef struct _FALSE_ALARM_STATISTICS{ - u4Byte Cnt_Parity_Fail; - u4Byte Cnt_Rate_Illegal; - u4Byte Cnt_Crc8_fail; - u4Byte cnt_crc8_fail_vht; - u4Byte Cnt_Mcs_fail; - u4Byte cnt_mcs_fail_vht; - u4Byte Cnt_Ofdm_fail; - u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A - u4Byte Cnt_Cck_fail; - u4Byte Cnt_all; - u4Byte Cnt_all_pre; - u4Byte Cnt_Fast_Fsync; - u4Byte Cnt_SB_Search_fail; - u4Byte Cnt_OFDM_CCA; - u4Byte Cnt_CCK_CCA; - u4Byte Cnt_CCA_all; - u4Byte Cnt_BW_USC; //Gary - u4Byte Cnt_BW_LSC; //Gary - u4Byte cnt_cck_crc32_error; - u4Byte cnt_cck_crc32_ok; - u4Byte cnt_ofdm_crc32_error; - u4Byte cnt_ofdm_crc32_ok; - u4Byte cnt_ht_crc32_error; - u4Byte cnt_ht_crc32_ok; - u4Byte cnt_vht_crc32_error; - u4Byte cnt_vht_crc32_ok; - u4Byte cnt_crc32_error_all; - u4Byte cnt_crc32_ok_all; - u4Byte time_fa_all; - BOOLEAN cck_block_enable; - BOOLEAN ofdm_block_enable; - u4Byte dbg_port0; - BOOLEAN edcca_flag; -}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) -typedef struct _FALSE_ALARM_STATISTICS_ACC{ - u4Byte Cnt_Parity_Fail[2]; - u4Byte Cnt_Rate_Illegal[2]; - u4Byte Cnt_Crc8_fail[2]; - u4Byte Cnt_Mcs_fail[2]; - u4Byte Cnt_Ofdm_fail[2]; - u4Byte Cnt_Ofdm_fail_pre[2]; //For RTL8881A - u4Byte Cnt_Cck_fail[2]; - u4Byte Cnt_all[2]; - u4Byte Cnt_all_pre[2]; - - u4Byte Cnt_Fast_Fsync[2]; - u4Byte Cnt_SB_Search_fail[2]; - u4Byte Cnt_OFDM_CCA[2]; - u4Byte Cnt_CCK_CCA[2]; - u4Byte Cnt_CCA_all[2]; - - u4Byte cnt_cck_crc32_error[2]; - u4Byte cnt_cck_crc32_ok[2]; - u4Byte cnt_ofdm_crc32_error[2]; - u4Byte cnt_ofdm_crc32_ok[2]; - u4Byte cnt_ht_crc32_error[2]; - u4Byte cnt_ht_crc32_ok[2]; - u4Byte cnt_vht_crc32_error[2]; - u4Byte cnt_vht_crc32_ok[2]; - u4Byte cnt_crc32_error_all[2]; - u4Byte cnt_crc32_ok_all[2]; - - u4Byte Cnt_all_1sec[2]; - u4Byte Cnt_CCA_all_1sec[2]; - u4Byte Cnt_Cck_fail_1sec[2]; - u4Byte Cnt_Ofdm_fail_1sec[2]; - u4Byte fa_cca_ratio[2]; - bool is_fa_bigger_cca[2]; -}FALSE_ALARM_STATISTICS_ACC, *PFALSE_ALARM_STATISTICS_ACC; -#endif - -typedef struct _LNA_SATURATION_INFO{ - u4Byte sat_cnt_acc_patha; - u4Byte sat_cnt_acc_pathb; - u4Byte check_time; - bool pre_sat_status; - bool cur_sat_status; - RT_TIMER phydm_lna_sat_chk_timer; - u4Byte cur_timer_check_cnt; - u4Byte pre_timer_check_cnt; -}LNA_SATURATION_INFO, *PLNA_SATURATION_INFO; - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - - typedef struct _LNA_SAT_TYPE2_INFO{ - u4Byte cur_snr_mean; - u4Byte pre_snr_mean; - u4Byte cur_lower_snr_mean; - u4Byte pre_lower_snr_mean; - u1Byte cnt_lower_snr_statistic; - u4Byte cur_snr_var; - u4Byte pre_snr_var; - u1Byte nxt_state; - u1Byte pre_state; - bool is_sm_done; - bool is_snr_done; - bool is_force_table; - - s1Byte snr_statistic[1024]; - u2Byte snr_statistic_sqr[1024]; - u4Byte cnt_snr_statistic; - u2Byte total_cnt_snr_statistic; - u1Byte ori_table_try_fail_times; - u1Byte sat_table_monitor_times; - u1Byte force_change_period; -// u4Byte sum_snr_statistic; - }LNA_SAT_TYPE2_INFO, *PLNA_SAT_TYPE2_INFO; - -#endif //#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - -typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition -{ - DIG_TYPE_THRESH_HIGH = 0, - DIG_TYPE_THRESH_LOW = 1, - DIG_TYPE_BACKOFF = 2, - DIG_TYPE_RX_GAIN_MIN = 3, - DIG_TYPE_RX_GAIN_MAX = 4, - DIG_TYPE_ENABLE = 5, - DIG_TYPE_DISABLE = 6, - DIG_OP_TYPE_MAX -}DM_DIG_OP_E; - -/* -typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition -{ - CCK_PD_STAGE_LowRssi = 0, - CCK_PD_STAGE_HighRssi = 1, - CCK_PD_STAGE_MAX = 3, -}DM_CCK_PDTH_E; - -typedef enum tag_DIG_EXT_PORT_ALGO_Definition -{ - DIG_EXT_PORT_STAGE_0 = 0, - DIG_EXT_PORT_STAGE_1 = 1, - DIG_EXT_PORT_STAGE_2 = 2, - DIG_EXT_PORT_STAGE_3 = 3, - DIG_EXT_PORT_STAGE_MAX = 4, -}DM_DIG_EXT_PORT_ALG_E; - -typedef enum tag_DIG_Connect_Definition -{ - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - DIG_MultiSTA_DISCONNECT = 3, - DIG_MultiSTA_CONNECT = 4, - DIG_CONNECT_MAX -}DM_DIG_CONNECT_E; - - -#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} - -#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) - -#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) -*/ - -typedef enum tag_PHYDM_Pause_Type { - PHYDM_PAUSE = BIT0, - PHYDM_RESUME = BIT1 -} PHYDM_PAUSE_TYPE; - -typedef enum tag_PHYDM_Pause_Level { -/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ - PHYDM_PAUSE_LEVEL_0 = 0, - PHYDM_PAUSE_LEVEL_1 = 1, - PHYDM_PAUSE_LEVEL_2 = 2, - PHYDM_PAUSE_LEVEL_3 = 3, - PHYDM_PAUSE_LEVEL_4 = 4, - PHYDM_PAUSE_LEVEL_5 = 5, - PHYDM_PAUSE_LEVEL_6 = 6, - PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ -} PHYDM_PAUSE_LEVEL; - -#define DM_DIG_THRESH_HIGH 40 -#define DM_DIG_THRESH_LOW 35 - -#define DM_FALSEALARM_THRESH_LOW 400 -#define DM_FALSEALARM_THRESH_HIGH 1000 - -#define DM_DIG_MAX_NIC 0x3e -#define DM_DIG_MIN_NIC 0x20 -#define DM_DIG_MAX_OF_MIN_NIC 0x3e - -#if (DIG_HW == 1) -#define DM_DIG_MAX_AP pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_upper //0x3e -#define DM_DIG_MIN_AP ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8822B))?0x1c:0x20)//0x1c -#else -#define DM_DIG_MAX_AP 0x3e -#define DM_DIG_MIN_AP ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8822B))?0x1c:0x20)//0x20 -#endif -#define DM_DIG_MAX_OF_MIN 0x2A //0x32 -#define DM_DIG_MIN_AP_DFS 0x20 - -#define DM_DIG_MAX_NIC_HP 0x46 -#define DM_DIG_MIN_NIC_HP 0x2e - -#define DM_DIG_MAX_AP_HP 0x42 -#define DM_DIG_MIN_AP_HP 0x30 - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#define DM_DIG_MAX_AP_COVERAGR 0x26 -#if (DIG_HW == 1) -#define DM_DIG_MIN_AP_COVERAGE ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8822B))?0x1c:0x20) -#else -#define DM_DIG_MIN_AP_COVERAGE 0x1c -#endif -#define DM_DIG_MAX_OF_MIN_COVERAGE 0x2A//0x22 - -#define DM_DIG_TP_Target_TH0 500 -#define DM_DIG_TP_Target_TH1 1000 -#define DM_DIG_TP_Training_Period 10 -#endif - -#define AAA_BASE pDM_Odm->priv->pshare->rf_ft_var.dbg_aaa_base/*4*/ -#define AAA_STEP pDM_Odm->priv->pshare->rf_ft_var.dbg_aaa_step/*2*/ - -//vivi 92c&92d has different definition, 20110504 -//this is for 92c -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - #define DM_DIG_FA_TH0 0x80//0x20 - #else - #define DM_DIG_FA_TH0 0x200//0x20 - #endif -#else - #define DM_DIG_FA_TH0 0x200//0x20 -#endif - -#define DM_DIG_FA_TH1 0x300 -#define DM_DIG_FA_TH2 0x400 -//this is for 92d -#define DM_DIG_FA_TH0_92D 0x100 -#define DM_DIG_FA_TH1_92D 0x400 -#define DM_DIG_FA_TH2_92D 0x600 - -#define DM_DIG_BACKOFF_MAX 12 -#define DM_DIG_BACKOFF_MIN -4 -#define DM_DIG_BACKOFF_DEFAULT 10 - -#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps -#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps -#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps -#define RSSI_OFFSET_DIG 0x05 -#define LARGE_FA_TIMEOUT 60 - - -VOID -ODM_ChangeDynamicInitGainThresh( - IN PVOID pDM_VOID, - IN u4Byte DM_Type, - IN u4Byte DM_Value - ); - -VOID -ODM_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI - ); - -VOID -odm_PauseDIG( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte IGIValue - ); - -VOID -odm_DIGInit( - IN PVOID pDM_VOID - ); - -VOID -odm_DIG( - IN PVOID pDM_VOID - ); - -void -phydm_lna_sat_chk_watchdog( - IN PVOID pDM_VOID -); - -void -phydm_lna_sat_chk_init( - IN PVOID pDM_VOID -); - -void -phydm_lna_sat_chk_callback( - IN PVOID pDM_VOID -); - -void -phydm_lna_sat_chk_timers( - IN PVOID pDM_VOID, - u8 state -); - -void -phydm_lna_sat_chk( - IN PVOID pDM_VOID -); - -void -phydm_set_ofdm_agc_tab( - IN PVOID pDM_VOID, - IN u1Byte tab_sel -); - -u1Byte -phydm_get_ofdm_agc_tab( - IN PVOID pDM_VOID -); - - -u1Byte -phydm_dig_current_igi_by_fa_th( - IN PVOID pDM_VOID, - u1Byte CurrentIGI, - pu4Byte dm_FA_thres, - pu1Byte step_size, - bool DIG_GoUpCheck, - u1Byte is_high_low_sel - ); - -BOOLEAN -odm_DigAbort( - IN PVOID pDM_VOID - ); - -VOID -odm_DIGbyRSSI_LPS( - IN PVOID pDM_VOID - ); - -VOID -odm_FalseAlarmCounterStatistics( - IN PVOID pDM_VOID - ); - -#if (PHYDM_TDMA_DIG_SUPPORT == 1) - -u1Byte -phydm_rx_gain_min_check( - IN PVOID pDM_VOID, - IN u1Byte dym_min, - IN u1Byte CurrentIGI, - IN u1Byte rx_gain_min, - bool is_high_low_sel - ); - -void -phydm_tdma_dig_timers( - IN PVOID pDM_VOID, - u8 state - ); - -VOID -phydm_tdma_low_dig( - IN PVOID pDM_VOID - ); - -VOID -phydm_tdma_high_dig( - IN PVOID pDM_VOID - ); - -VOID -phydm_tdma_dig_timer_check( - IN PVOID pDM_VOID - ); - -VOID -phydm_tdma_dig_call_back( - IN PVOID pDM_VOID - ); - -VOID -phydm_TDMA_FalseAlarmCounterCheck( - IN PVOID pDM_VOID - ); - -VOID -odm_FalseAlarmCounterAcc( - IN PVOID pDM_VOID, - IN BOOLEAN rssi_dump_en, - bool high_low_state - ); - -VOID -odm_FalseAlarmCounterAccReset( - IN PVOID pDM_VOID, - u8 high_low_idx - ); - -#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) - -VOID -odm_FalseAlarmCounterReset( - IN PVOID pDM_VOID - ); - - -VOID -odm_FalseAlarmCounterRegReset( - IN PVOID pDM_VOID - ); - -VOID -odm_FalseAlarmCounterRegHold( - IN PVOID pDM_VOID - ); - -VOID -odm_PauseCCKPacketDetection( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte CCKPDThreshold - ); - -VOID -odm_CCKPacketDetectionThresh( - IN PVOID pDM_VOID - ); - -VOID -ODM_Write_CCK_CCA_Thres( - IN PVOID pDM_VOID, - IN u1Byte CurCCK_CCAThres - ); - -BOOLEAN -phydm_DIG_GoUpCheck( - IN PVOID pDM_VOID - ); - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_MPT_DIGCallback( - PRT_TIMER pTimer -); - -VOID -odm_MPT_DIGWorkItemCallback( - IN PVOID pContext - ); - -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -VOID -odm_MPT_DIGCallback( - IN PVOID pDM_VOID -); -#endif - -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) -VOID -ODM_MPT_DIG( - IN PVOID pDM_VOID -); -#endif - - -#endif - -#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) - -void -phydm_snr_collect( - IN PVOID pDM_VOID, - IN u8 rx_snr - ); - -void -phydm_lna_sat_type2_sm( - IN PVOID pDM_VOID - ); - -void -phydm_lna_sat_chk_type2_init( - IN PVOID pDM_VOID - ); - -void -phydm_snr_data_processing( - IN PVOID pDM_VOID - ); - -void -phydm_bubble_sort( - IN PVOID pDM_VOID, - IN u1Byte *array, - IN u2Byte array_length -); - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ +#define DIG_HW 1 + +enum lna_sat_chk_timmer { + INIT_LNA_SAT_CHK_TIMMER, + CANCEL_LNA_SAT_CHK_TIMMER, + RELEASE_LNA_SAT_CHK_TIMMER +}; +enum tdma_dig_timer { + INIT_TDMA_DIG_TIMMER, + CANCEL_TDMA_DIG_TIMMER, + RELEASE_TDMA_DIG_TIMMER +}; +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + + #define DELTA_STD 2 + #define DELTA_MEAN 2 + #define SNR_STATISTIC_SHIFT 8 + + enum lna_sat_chk_type2_status { + + ORI_TABLE_MONITOR, + ORI_TABLE_TRAINING, + SAT_TABLE_MONITOR, + SAT_TABLE_TRAINING, + SAT_TABLE_TRY_FAIL, + ORI_TABLE_TRY_FAIL + }; + + +#endif +#define RSSI_TO_IGI 10 +#define ONE_SEC_MS 1000 +#define OFDM_AGC_TAB_0 0 +#define OFDM_AGC_TAB_2 2 + +/* Pause DIG & CCKPD */ +#define DM_DIG_MAX_PAUSE_TYPE 0x7 +#define ONE_SEC_MS 1000 + +enum is_high_low_sel { + TDMA_DIG_LOW_STATE = 0, + TDMA_DIG_HIGH_STATE = 1, + NORMAL_DIG = 2 +}; + +enum rx_gain_min_check_state { + OSC_CHECK_STATE = 0, + OSC_LOCK_STATE = 1, + OSC_RELEASE_STATE = 2 +}; + +enum fa_cca_ratio_thd { + FA_CCA_RATIO_L2H = 50, + FA_CCA_RATIO_H2L = 40 +}; +typedef enum tag_DIG_GoUpCheck_Level { + + DIG_GOUPCHECK_LEVEL_0, + DIG_GOUPCHECK_LEVEL_1, + DIG_GOUPCHECK_LEVEL_2 + +} DIG_GOUPCHECK_LEVEL; + +#ifdef CFG_DIG_DAMPING_CHK +#define DIG_RECORD_NUM 4 +#define DIG_LIMIT_PERIOD 60 /*60 sec*/ + +struct phydm_dig_recoder_strcut { + u8 igi_bitmap; /*Do not add any new parameter before this*/ + u8 igi_history[DIG_RECORD_NUM]; + u32 fa_history[DIG_RECORD_NUM]; + u8 damping_limit_en; + u8 damping_limit_val; /*Limit IGI_dyn_min*/ + u32 limit_time; + u8 limit_rssi; +}; +#endif + +typedef struct _Dynamic_Initial_Gain_Threshold_ +{ +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recoder_strcut dig_recoder_t; + u8 dig_dl_en; /*damping limit function enable*/ +#endif + u16 fa_th[3]; + BOOLEAN bStopDIG; // for debug + BOOLEAN bIgnoreDIG; + BOOLEAN bPSDInProgress; + + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u4Byte FALowThresh; + u4Byte FAHighThresh; + + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + + u1Byte PreIGValue; + u1Byte CurIGValue; +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + u1Byte tdma_igi[2]; + RT_TIMER phydm_tdma_dig_timer; + u1Byte tdma_rx_gain_max[2]; + u1Byte tdma_rx_gain_min[2]; + + /*phydm_rx_gain_min_check*/ + u1Byte rx_gain_min_check_state[2]; //for tdma use + u1Byte stay_check_state_cnt[2]; // check state + u1Byte goto_lock_state_cnt[2]; // check state + u1Byte goto_release_state_cnt[2]; // lock state + u1Byte stay_release_state_cnt[2]; // release state +#endif + + u1Byte BackupIGValue; //MP DIG + u1Byte BT30_CurIGI; + u1Byte IGIBackup; + + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + u1Byte CCKPDBackup; + u1Byte pause_cckpd_level; + u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u1Byte LargeFAHit; + u1Byte LargeFA_Timeout; /*if (LargeFAHit), monitor "LargeFA_Timeout" sec, if timeout, LargeFAHit=0*/ + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; + + u1Byte *bP2PInProcess; + + u1Byte pause_dig_level; + u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u4Byte cckFaMa; + DIG_GOUPCHECK_LEVEL DIG_GoUpCheck_Level; + u1Byte aaa_default; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + BOOLEAN bTpTarget; + BOOLEAN bNoiseEst; + u4Byte TpTrainTH_min; + u1Byte IGIOffset_A; + u1Byte IGIOffset_B; +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + u1Byte rfGainIdx; + u1Byte agcTableIdx; + u1Byte bigJumpLmt[16]; + u1Byte enableAdjustBigJump:1; + u1Byte bigJumpStep1:3; + u1Byte bigJumpStep2:2; + u1Byte bigJumpStep3:2; +#endif + +#if (DIG_HW == 1) + u1Byte pre_rssi_min; +#endif + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + u1Byte tdma_dig_state; + u1Byte tdma_dig_cnt; // for timer check + u1Byte tdma_dig_block_cnt; // for high/low state false alarm statistics + bool one_sec_dump; + u1Byte pre_tdma_dig_cnt; +#endif + u1Byte normalize_1sec_factor; + u4Byte pre_tsf; + u4Byte cur_tsf; + u4Byte fa_start_tsf; + u4Byte fa_end_tsf; + u4Byte fa_acc_1sec_tsf; +}DIG_T,*pDIG_T; + +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte cnt_crc8_fail_vht; + u4Byte Cnt_Mcs_fail; + u4Byte cnt_mcs_fail_vht; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_all_pre; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary + u4Byte cnt_cck_crc32_error; + u4Byte cnt_cck_crc32_ok; + u4Byte cnt_ofdm_crc32_error; + u4Byte cnt_ofdm_crc32_ok; + u4Byte cnt_ht_crc32_error; + u4Byte cnt_ht_crc32_ok; + u4Byte cnt_vht_crc32_error; + u4Byte cnt_vht_crc32_ok; + u4Byte cnt_crc32_error_all; + u4Byte cnt_crc32_ok_all; + u4Byte time_fa_all; + BOOLEAN cck_block_enable; + BOOLEAN ofdm_block_enable; + u4Byte dbg_port0; + BOOLEAN edcca_flag; +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) +typedef struct _FALSE_ALARM_STATISTICS_ACC{ + u4Byte Cnt_Parity_Fail[2]; + u4Byte Cnt_Rate_Illegal[2]; + u4Byte Cnt_Crc8_fail[2]; + u4Byte Cnt_Mcs_fail[2]; + u4Byte Cnt_Ofdm_fail[2]; + u4Byte Cnt_Ofdm_fail_pre[2]; //For RTL8881A + u4Byte Cnt_Cck_fail[2]; + u4Byte Cnt_all[2]; + u4Byte Cnt_all_pre[2]; + + u4Byte Cnt_Fast_Fsync[2]; + u4Byte Cnt_SB_Search_fail[2]; + u4Byte Cnt_OFDM_CCA[2]; + u4Byte Cnt_CCK_CCA[2]; + u4Byte Cnt_CCA_all[2]; + + u4Byte cnt_cck_crc32_error[2]; + u4Byte cnt_cck_crc32_ok[2]; + u4Byte cnt_ofdm_crc32_error[2]; + u4Byte cnt_ofdm_crc32_ok[2]; + u4Byte cnt_ht_crc32_error[2]; + u4Byte cnt_ht_crc32_ok[2]; + u4Byte cnt_vht_crc32_error[2]; + u4Byte cnt_vht_crc32_ok[2]; + u4Byte cnt_crc32_error_all[2]; + u4Byte cnt_crc32_ok_all[2]; + + u4Byte Cnt_all_1sec[2]; + u4Byte Cnt_CCA_all_1sec[2]; + u4Byte Cnt_Cck_fail_1sec[2]; + u4Byte Cnt_Ofdm_fail_1sec[2]; + u4Byte fa_cca_ratio[2]; + bool is_fa_bigger_cca[2]; +}FALSE_ALARM_STATISTICS_ACC, *PFALSE_ALARM_STATISTICS_ACC; +#endif + +typedef struct _LNA_SATURATION_INFO{ + u4Byte sat_cnt_acc_patha; + u4Byte sat_cnt_acc_pathb; + u4Byte check_time; + bool pre_sat_status; + bool cur_sat_status; + RT_TIMER phydm_lna_sat_chk_timer; + u4Byte cur_timer_check_cnt; + u4Byte pre_timer_check_cnt; +}LNA_SATURATION_INFO, *PLNA_SATURATION_INFO; + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + + typedef struct _LNA_SAT_TYPE2_INFO{ + u4Byte cur_snr_mean; + u4Byte pre_snr_mean; + u4Byte cur_lower_snr_mean; + u4Byte pre_lower_snr_mean; + u1Byte cnt_lower_snr_statistic; + u4Byte cur_snr_var; + u4Byte pre_snr_var; + u1Byte nxt_state; + u1Byte pre_state; + bool is_sm_done; + bool is_snr_done; + bool is_force_table; + + s1Byte snr_statistic[1024]; + u2Byte snr_statistic_sqr[1024]; + u4Byte cnt_snr_statistic; + u2Byte total_cnt_snr_statistic; + u1Byte ori_table_try_fail_times; + u1Byte sat_table_monitor_times; + u1Byte force_change_period; +// u4Byte sum_snr_statistic; + }LNA_SAT_TYPE2_INFO, *PLNA_SAT_TYPE2_INFO; + +#endif //#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + +typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}DM_DIG_OP_E; + +/* +typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}DM_CCK_PDTH_E; + +typedef enum tag_DIG_EXT_PORT_ALGO_Definition +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}DM_DIG_EXT_PORT_ALG_E; + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) +*/ + +typedef enum tag_PHYDM_Pause_Type { + PHYDM_PAUSE = BIT0, + PHYDM_RESUME = BIT1 +} PHYDM_PAUSE_TYPE; + +typedef enum tag_PHYDM_Pause_Level { +/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ + PHYDM_PAUSE_LEVEL_0 = 0, + PHYDM_PAUSE_LEVEL_1 = 1, + PHYDM_PAUSE_LEVEL_2 = 2, + PHYDM_PAUSE_LEVEL_3 = 3, + PHYDM_PAUSE_LEVEL_4 = 4, + PHYDM_PAUSE_LEVEL_5 = 5, + PHYDM_PAUSE_LEVEL_6 = 6, + PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ +} PHYDM_PAUSE_LEVEL; + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x20 +#define DM_DIG_MAX_OF_MIN_NIC 0x3e + +#if (DIG_HW == 1) +#define DM_DIG_MAX_AP pDM_Odm->priv->pshare->rf_ft_var.dbg_dig_upper //0x3e +#define DM_DIG_MIN_AP ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8822B))?0x1c:0x20)//0x1c +#else +#define DM_DIG_MAX_AP 0x3e +#define DM_DIG_MIN_AP ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8822B))?0x1c:0x20)//0x20 +#endif +#define DM_DIG_MAX_OF_MIN 0x2A //0x32 +#define DM_DIG_MIN_AP_DFS 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#define DM_DIG_MAX_AP_COVERAGR 0x26 +#if (DIG_HW == 1) +#define DM_DIG_MIN_AP_COVERAGE ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8822B))?0x1c:0x20) +#else +#define DM_DIG_MIN_AP_COVERAGE 0x1c +#endif +#define DM_DIG_MAX_OF_MIN_COVERAGE 0x2A//0x22 + +#define DM_DIG_TP_Target_TH0 500 +#define DM_DIG_TP_Target_TH1 1000 +#define DM_DIG_TP_Training_Period 10 +#endif + +#define AAA_BASE pDM_Odm->priv->pshare->rf_ft_var.dbg_aaa_base/*4*/ +#define AAA_STEP pDM_Odm->priv->pshare->rf_ft_var.dbg_aaa_step/*2*/ + +//vivi 92c&92d has different definition, 20110504 +//this is for 92c +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + #define DM_DIG_FA_TH0 0x80//0x20 + #else + #define DM_DIG_FA_TH0 0x200//0x20 + #endif +#else + #define DM_DIG_FA_TH0 0x200//0x20 +#endif + +#define DM_DIG_FA_TH1 0x300 +#define DM_DIG_FA_TH2 0x400 +//this is for 92d +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps +#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps +#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +#define RSSI_OFFSET_DIG 0x05 +#define LARGE_FA_TIMEOUT 60 + + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ); + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ); + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte IGIValue + ); + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DIG( + IN PVOID pDM_VOID + ); + +void +phydm_lna_sat_chk_watchdog( + IN PVOID pDM_VOID +); + +void +phydm_lna_sat_chk_init( + IN PVOID pDM_VOID +); + +void +phydm_lna_sat_chk_callback( + IN PVOID pDM_VOID +); + +void +phydm_lna_sat_chk_timers( + IN PVOID pDM_VOID, + u8 state +); + +void +phydm_lna_sat_chk( + IN PVOID pDM_VOID +); + +void +phydm_set_ofdm_agc_tab( + IN PVOID pDM_VOID, + IN u1Byte tab_sel +); + +u1Byte +phydm_get_ofdm_agc_tab( + IN PVOID pDM_VOID +); + + +u1Byte +phydm_dig_current_igi_by_fa_th( + IN PVOID pDM_VOID, + u1Byte CurrentIGI, + pu4Byte dm_FA_thres, + pu1Byte step_size, + bool DIG_GoUpCheck, + u1Byte is_high_low_sel + ); + +BOOLEAN +odm_DigAbort( + IN PVOID pDM_VOID + ); + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ); + +#if (PHYDM_TDMA_DIG_SUPPORT == 1) + +u1Byte +phydm_rx_gain_min_check( + IN PVOID pDM_VOID, + IN u1Byte dym_min, + IN u1Byte CurrentIGI, + IN u1Byte rx_gain_min, + bool is_high_low_sel + ); + +void +phydm_tdma_dig_timers( + IN PVOID pDM_VOID, + u8 state + ); + +VOID +phydm_tdma_low_dig( + IN PVOID pDM_VOID + ); + +VOID +phydm_tdma_high_dig( + IN PVOID pDM_VOID + ); + +VOID +phydm_tdma_dig_timer_check( + IN PVOID pDM_VOID + ); + +VOID +phydm_tdma_dig_call_back( + IN PVOID pDM_VOID + ); + +VOID +phydm_TDMA_FalseAlarmCounterCheck( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterAcc( + IN PVOID pDM_VOID, + IN BOOLEAN rssi_dump_en, + bool high_low_state + ); + +VOID +odm_FalseAlarmCounterAccReset( + IN PVOID pDM_VOID, + u8 high_low_idx + ); + +#endif //#if (PHYDM_TDMA_DIG_SUPPORT == 1) + +VOID +odm_FalseAlarmCounterReset( + IN PVOID pDM_VOID + ); + + +VOID +odm_FalseAlarmCounterRegReset( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterRegHold( + IN PVOID pDM_VOID + ); + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte CCKPDThreshold + ); + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ); + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ); + +BOOLEAN +phydm_DIG_GoUpCheck( + IN PVOID pDM_VOID + ); + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +); + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +); +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID +); +#endif + + +#endif + +#if (PHYDM_LNA_SAT_CHK_TYPE2 == 1) + +void +phydm_snr_collect( + IN PVOID pDM_VOID, + IN u8 rx_snr + ); + +void +phydm_lna_sat_type2_sm( + IN PVOID pDM_VOID + ); + +void +phydm_lna_sat_chk_type2_init( + IN PVOID pDM_VOID + ); + +void +phydm_snr_data_processing( + IN PVOID pDM_VOID + ); + +void +phydm_bubble_sort( + IN PVOID pDM_VOID, + IN u1Byte *array, + IN u2Byte array_length +); + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.c b/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.c index 1b38560ff92..b3c2a905a94 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.c +++ b/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.c @@ -1,124 +1,124 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (defined(CONFIG_BB_POWER_SAVING)) - -VOID -odm_DynamicBBPowerSavingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; - - pDM_PSTable->PreCCAState = CCA_MAX; - pDM_PSTable->CurCCAState = CCA_MAX; - pDM_PSTable->PreRFState = RF_MAX; - pDM_PSTable->CurRFState = RF_MAX; - pDM_PSTable->Rssi_val_min = 0; - pDM_PSTable->initialize = 0; -} - -void -ODM_RF_Saving( - IN PVOID pDM_VOID, - IN u1Byte bForceInNormal - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; - u1Byte Rssi_Up_bound = 30 ; - u1Byte Rssi_Low_bound = 25; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV - { - Rssi_Up_bound = 50 ; - Rssi_Low_bound = 45; - } -#endif - if(pDM_PSTable->initialize == 0){ - - pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; - pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; - pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; - pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; - //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); - pDM_PSTable->initialize = 1; - } - - if(!bForceInNormal) - { - if(pDM_Odm->RSSI_Min != 0xFF) - { - if(pDM_PSTable->PreRFState == RF_Normal) - { - if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) - pDM_PSTable->CurRFState = RF_Save; - else - pDM_PSTable->CurRFState = RF_Normal; - } - else{ - if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) - pDM_PSTable->CurRFState = RF_Normal; - else - pDM_PSTable->CurRFState = RF_Save; - } - } - else - pDM_PSTable->CurRFState=RF_MAX; - } - else - { - pDM_PSTable->CurRFState = RF_Normal; - } - - if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) - { - if(pDM_PSTable->CurRFState == RF_Save) - { - ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 - ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 - ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 - } - else - { - ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); - ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); - ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); - } - pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; - } -#endif -} - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (defined(CONFIG_BB_POWER_SAVING)) + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + + pDM_PSTable->PreCCAState = CCA_MAX; + pDM_PSTable->CurCCAState = CCA_MAX; + pDM_PSTable->PreRFState = RF_MAX; + pDM_PSTable->CurRFState = RF_MAX; + pDM_PSTable->Rssi_val_min = 0; + pDM_PSTable->initialize = 0; +} + +void +ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + u1Byte Rssi_Up_bound = 30 ; + u1Byte Rssi_Low_bound = 25; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV + { + Rssi_Up_bound = 50 ; + Rssi_Low_bound = 45; + } +#endif + if(pDM_PSTable->initialize == 0){ + + pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; + pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; + pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; + pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; + //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); + pDM_PSTable->initialize = 1; + } + + if(!bForceInNormal) + { + if(pDM_Odm->RSSI_Min != 0xFF) + { + if(pDM_PSTable->PreRFState == RF_Normal) + { + if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) + pDM_PSTable->CurRFState = RF_Save; + else + pDM_PSTable->CurRFState = RF_Normal; + } + else{ + if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) + pDM_PSTable->CurRFState = RF_Normal; + else + pDM_PSTable->CurRFState = RF_Save; + } + } + else + pDM_PSTable->CurRFState=RF_MAX; + } + else + { + pDM_PSTable->CurRFState = RF_Normal; + } + + if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) + { + if(pDM_PSTable->CurRFState == RF_Save) + { + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 + ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 + } + else + { + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); + ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); + } + pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; + } +#endif +} + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.h b/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.h index aa0b9b3ed92..28109dacb45 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.h +++ b/package/kernel/rtl8192cd/phydm/phydm_dynamicbbpowersaving.h @@ -1,58 +1,58 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ -#define __PHYDMDYNAMICBBPOWERSAVING_H__ - -#define DYNAMIC_BBPWRSAV_VERSION "1.1" - -#if (defined(CONFIG_BB_POWER_SAVING)) - -typedef struct _Dynamic_Power_Saving_ -{ - u1Byte PreCCAState; - u1Byte CurCCAState; - - u1Byte PreRFState; - u1Byte CurRFState; - - int Rssi_val_min; - - u1Byte initialize; - u4Byte Reg874,RegC70,Reg85C,RegA74; - -}PS_T,*pPS_T; - -#define dm_RF_Saving ODM_RF_Saving - -void ODM_RF_Saving( - IN PVOID pDM_VOID, - IN u1Byte bForceInNormal -); - -VOID -odm_DynamicBBPowerSavingInit( - IN PVOID pDM_VOID - ); -#else -#define dm_RF_Saving(pDM_VOID, bForceInNormal) -#endif - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ +#define __PHYDMDYNAMICBBPOWERSAVING_H__ + +#define DYNAMIC_BBPWRSAV_VERSION "1.1" + +#if (defined(CONFIG_BB_POWER_SAVING)) + +typedef struct _Dynamic_Power_Saving_ +{ + u1Byte PreCCAState; + u1Byte CurCCAState; + + u1Byte PreRFState; + u1Byte CurRFState; + + int Rssi_val_min; + + u1Byte initialize; + u4Byte Reg874,RegC70,Reg85C,RegA74; + +}PS_T,*pPS_T; + +#define dm_RF_Saving ODM_RF_Saving + +void ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal +); + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ); +#else +#define dm_RF_Saving(pDM_VOID, bForceInNormal) +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.c b/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.c index 5add8dcef0b..3ed4efb935b 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.c +++ b/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.c @@ -1,559 +1,559 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -odm_DynamicTxPowerInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - /*if (!IS_HARDWARE_TYPE_8814A(Adapter)) {*/ - /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ - /* ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));*/ - /* return;*/ - /*} else*/ - { - pMgntInfo->bDynamicTxPowerEnable = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable)); - } - - #if DEV_BUS_TYPE==RT_USB_INTERFACE - if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) - { - odm_DynamicTxPowerSavePowerIndex(pDM_Odm); - pMgntInfo->bDynamicTxPowerEnable = TRUE; - } - else - #else - //so 92c pci do not need dynamic tx power? vivi check it later - pMgntInfo->bDynamicTxPowerEnable = FALSE; - #endif - - - pHalData->LastDTPLvl = TxHighPwrLevel_Normal; - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - pDM_Odm->LastDTPLvl = TxHighPwrLevel_Normal; - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - pDM_Odm->tx_agc_ofdm_18_6 = ODM_GetBBReg(pDM_Odm, 0xC24, bMaskDWord); /*TXAGC {18M 12M 9M 6M}*/ - -#endif - -} - -VOID -odm_DynamicTxPowerSavePowerIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - u1Byte index; - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - for(index = 0; index< 6; index++) - pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); - - -#endif -#endif -} - -VOID -odm_DynamicTxPowerRestorePowerIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - u1Byte index; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for(index = 0; index< 6; index++) - PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); - - -#endif -#endif -} - -VOID -odm_DynamicTxPowerWritePowerIndex( - IN PVOID pDM_VOID, - IN u1Byte Value) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte index; - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; - - for(index = 0; index< 6; index++) - //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); - ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); - -} - -VOID -odm_DynamicTxPowerNIC_CE( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#if (RTL8821A_SUPPORT == 1) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte val; - u1Byte rssi_tmp = pDM_Odm->RSSI_Min; - - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) - return; - - if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; - /**/ - } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; - /**/ - } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - /**/ - } - - if (pDM_Odm->LastDTPLvl != pDM_Odm->DynamicTxHighPowerLvl) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", pDM_Odm->LastDTPLvl, pDM_Odm->DynamicTxHighPowerLvl)); - - pDM_Odm->LastDTPLvl = pDM_Odm->DynamicTxHighPowerLvl; - - if (pDM_Odm->SupportICType & (ODM_RTL8821)) { - - if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { - - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ - - val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x16; - - ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); - } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { - - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ - - val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x10; - - ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); - } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) { - - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 0); /* Resp TXAGC offset = 0dB*/ - ODM_SetBBReg(pDM_Odm, 0xC24, bMaskDWord, pDM_Odm->tx_agc_ofdm_18_6); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); - } - } - } - -#endif -#endif -} - - -VOID -odm_DynamicTxPower( - IN PVOID pDM_VOID - ) -{ - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - //PADAPTER pAdapter = pDM_Odm->Adapter; -// prtl8192cd_priv priv = pDM_Odm->priv; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) - return; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_DynamicTxPowerNIC(pDM_Odm); - break; - case ODM_CE: - odm_DynamicTxPowerNIC_CE(pDM_Odm); - break; - case ODM_AP: - odm_DynamicTxPowerAP(pDM_Odm); - break; - default: - break; - } - - -} - - -VOID -odm_DynamicTxPowerNIC( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) - return; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (pDM_Odm->SupportICType == ODM_RTL8814A) { - odm_DynamicTxPower_8814A(pDM_Odm); - } else if (pDM_Odm->SupportICType & ODM_RTL8821) { - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); - - if (pMgntInfo->RegRspPwr == 1) { - if (pDM_Odm->RSSI_Min > 60) - ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); /*Resp TXAGC offset = -3dB*/ - else if (pDM_Odm->RSSI_Min < 55) - ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); /*Resp TXAGC offset = 0dB*/ - } - } -#endif -} - -VOID -odm_DynamicTxPowerAP( - IN PVOID pDM_VOID - - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) - - - prtl8192cd_priv priv = pDM_Odm->priv; - s4Byte i; - s2Byte pwr_thd = 63; - - if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) - return; - -#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8822B)) - pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1; -#endif - - /* - * Check if station is near by to use lower tx power - */ - - if ((priv->up_time % 3) == 0 ) { - - u1Byte igi; - u4Byte fa_cnt; - - #if (PHYDM_TDMA_DIG_SUPPORT == 1) - if (ODMPTR->original_dig_restore == 0) - { - fa_cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_all_1sec[TDMA_DIG_HIGH_STATE]; - igi = ODMPTR->DM_DigTable.tdma_igi[TDMA_DIG_HIGH_STATE]; - } - else - #endif - { - fa_cnt = pDM_Odm->FalseAlmCnt.Cnt_all; - igi = (RTL_R8(0xc50) & 0x7f); - } - - int disable_pwr_ctrl = ((fa_cnt > 1000 ) || ((fa_cnt > 300 ) && (igi >= 0x32))) ? 1 : 0; - - for(i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pstat) ) { - if(disable_pwr_ctrl) - pstat->hp_level = 0; - else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) - pstat->hp_level = 1; - else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8))) - pstat->hp_level = 0; - } - } - -#if defined(CONFIG_WLAN_HAL_8192EE) || defined(CONFIG_WLAN_HAL_8822BE) - if (GET_CHIP_VER(priv) == VERSION_8192E || GET_CHIP_VER(priv) == VERSION_8822B) { - if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) { - if(pDM_Odm->RSSI_Min > pwr_thd) - RRSR_power_control_11n(priv, 1 ); - else if(pDM_Odm->RSSI_Min < (pwr_thd-8)) - RRSR_power_control_11n(priv, 0 ); - } else { - RRSR_power_control_11n(priv, 0 ); - } - } -#endif - -#ifdef CONFIG_WLAN_HAL_8814AE - if (GET_CHIP_VER(priv) == VERSION_8814A) { - if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) { - if (pDM_Odm->RSSI_Min > pwr_thd) - RRSR_power_control_14(priv, 1); - else if (pDM_Odm->RSSI_Min < (pwr_thd-8)) - RRSR_power_control_14(priv, 0); - } else { - RRSR_power_control_14(priv, 0); - } - } -#endif - - } -//#endif - -#endif -} - -VOID -odm_DynamicTxPower_8821( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId - ) -{ -#if (RTL8821A_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u1Byte reg0xc56_byte; - u1Byte txpwr_offset = 0; - - pEntry = pDM_Odm->pODM_StaInfo[macId]; - - reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); - - if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) { - - /* Avoid TXAGC error after TX power offset is applied. - For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) - Total power = 6-11= -5( overflow!! ), PA may be burned ! - so txpwr_offset should be adjusted by Reg0xc56*/ - - if (reg0xc56_byte < 7) - txpwr_offset = 1; - else if (reg0xc56_byte < 11) - txpwr_offset = 2; - else - txpwr_offset = 3; - - SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); - - } else{ - SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); - - } -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -#endif /*#if (RTL8821A_SUPPORT==1)*/ -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_DynamicTxPower_8814A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s4Byte UndecoratedSmoothedPWDB; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("TxLevel=%d pMgntInfo->IOTAction=%x pMgntInfo->bDynamicTxPowerEnable=%d\n", - pHalData->DynamicTxHighPowerLvl, pMgntInfo->IOTAction, pMgntInfo->bDynamicTxPowerEnable)); - - /*STA not connected and AP not connected*/ - if ((!pMgntInfo->bMediaConnect) && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - return; - } - - - if ((pMgntInfo->bDynamicTxPowerEnable != TRUE) || pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - } else { - if (pMgntInfo->bMediaConnect) { /*Default port*/ - if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) { - UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); - } else { - UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); - } - } else {/*associated entry pwdb*/ - UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); - } - - /*Should we separate as 2.4G/5G band?*/ - - if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); - } else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && - (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); - } else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); - } - } - - - if (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8814A() Channel = %d\n" , pHalData->CurrentChannel)); - odm_SetTxPowerLevel8814(Adapter, pHalData->CurrentChannel, pHalData->DynamicTxHighPowerLvl); - } - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_DynamicTxPower_8814A() Channel = %d TXpower lvl=%d/%d\n" , - pHalData->CurrentChannel, pHalData->LastDTPLvl, pHalData->DynamicTxHighPowerLvl)); - - pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; - -} - - - -/**/ -/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/ -/**/ -/**/ -VOID -odm_SetTxPowerLevel8814( - IN PADAPTER Adapter, - IN u1Byte Channel, - IN u1Byte PwrLvl - ) -{ -#if (DEV_BUS_TYPE == RT_USB_INTERFACE) - u4Byte i, j, k = 0; - u4Byte value[264] = {0}; - u4Byte path = 0, PowerIndex, txagc_table_wd = 0x00801000; - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - u1Byte jaguar2Rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, - {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, - {MGN_24M, MGN_36M, MGN_48M, MGN_54M}, - {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3}, - {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, - {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11}, - {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, - {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19}, - {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, - {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3}, - {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7}, - {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1}, - {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5}, - {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, - {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3}, - {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7}, - {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} }; - - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - - u1Byte usb_host = UsbModeQueryHubUsbType(Adapter); - u1Byte usb_rfset = UsbModeQueryRfSet(Adapter); - u1Byte usb_rf_type = RT_GetRFType(Adapter); - - for (i = 0; i <= 16; i++) { - for (j = 0; j <= 3; j++) { - if (jaguar2Rates[i][j] == 0) - continue; - - txagc_table_wd = 0x00801000; - PowerIndex = (u4Byte) PHY_GetTxPowerIndex(Adapter, (u1Byte)path, jaguar2Rates[i][j], pHalData->CurrentChannelBW, Channel); - - /*for Query bus type to recude tx power.*/ - if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(Adapter) && usb_rf_type == RF_3T3R) { - if (Channel <= 14) { - if (PowerIndex >= 16) - PowerIndex -= 16; - else - PowerIndex = 0; - } else - PowerIndex = 0; - } - - if (PwrLvl == TxHighPwrLevel_Level1) { - if (PowerIndex >= 0x10) - PowerIndex -= 0x10; - else - PowerIndex = 0; - } else if (PwrLvl == TxHighPwrLevel_Level2) { - PowerIndex = 0; - } - - txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2Rates[i][j]) | (PowerIndex << 24); - - PHY_SetTxPowerIndexShadow(Adapter, (u1Byte)PowerIndex, (u1Byte)path, jaguar2Rates[i][j]); - - value[k++] = txagc_table_wd; - } - } - } - - if (Adapter->MgntInfo.bScanInProgress == FALSE && Adapter->MgntInfo.RegFWOffload == 2) - HalDownloadTxPowerLevel8814(Adapter, value); -#endif -} -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /*if (!IS_HARDWARE_TYPE_8814A(Adapter)) {*/ + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ + /* ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));*/ + /* return;*/ + /*} else*/ + { + pMgntInfo->bDynamicTxPowerEnable = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable)); + } + + #if DEV_BUS_TYPE==RT_USB_INTERFACE + if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) + { + odm_DynamicTxPowerSavePowerIndex(pDM_Odm); + pMgntInfo->bDynamicTxPowerEnable = TRUE; + } + else + #else + //so 92c pci do not need dynamic tx power? vivi check it later + pMgntInfo->bDynamicTxPowerEnable = FALSE; + #endif + + + pHalData->LastDTPLvl = TxHighPwrLevel_Normal; + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + pDM_Odm->LastDTPLvl = TxHighPwrLevel_Normal; + pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + pDM_Odm->tx_agc_ofdm_18_6 = ODM_GetBBReg(pDM_Odm, 0xC24, bMaskDWord); /*TXAGC {18M 12M 9M 6M}*/ + +#endif + +} + +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + for(index = 0; index< 6; index++) + pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); + + +#endif +#endif +} + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + u1Byte index; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + for(index = 0; index< 6; index++) + PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); + + +#endif +#endif +} + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + + for(index = 0; index< 6; index++) + //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); + ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); + +} + +VOID +odm_DynamicTxPowerNIC_CE( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#if (RTL8821A_SUPPORT == 1) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte val; + u1Byte rssi_tmp = pDM_Odm->RSSI_Min; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + + if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { + pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + /**/ + } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { + pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + /**/ + } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { + pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + /**/ + } + + if (pDM_Odm->LastDTPLvl != pDM_Odm->DynamicTxHighPowerLvl) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", pDM_Odm->LastDTPLvl, pDM_Odm->DynamicTxHighPowerLvl)); + + pDM_Odm->LastDTPLvl = pDM_Odm->DynamicTxHighPowerLvl; + + if (pDM_Odm->SupportICType & (ODM_RTL8821)) { + + if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { + + ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ + + val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; + if (val >= 0x20) + val -= 0x16; + + ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); + } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { + + ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ + + val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; + if (val >= 0x20) + val -= 0x10; + + ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); + } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) { + + ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 0); /* Resp TXAGC offset = 0dB*/ + ODM_SetBBReg(pDM_Odm, 0xC24, bMaskDWord, pDM_Odm->tx_agc_ofdm_18_6); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); + } + } + } + +#endif +#endif +} + + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + //PADAPTER pAdapter = pDM_Odm->Adapter; +// prtl8192cd_priv priv = pDM_Odm->priv; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_DynamicTxPowerNIC(pDM_Odm); + break; + case ODM_CE: + odm_DynamicTxPowerNIC_CE(pDM_Odm); + break; + case ODM_AP: + odm_DynamicTxPowerAP(pDM_Odm); + break; + default: + break; + } + + +} + + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if (pDM_Odm->SupportICType == ODM_RTL8814A) { + odm_DynamicTxPower_8814A(pDM_Odm); + } else if (pDM_Odm->SupportICType & ODM_RTL8821) { + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); + + if (pMgntInfo->RegRspPwr == 1) { + if (pDM_Odm->RSSI_Min > 60) + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); /*Resp TXAGC offset = -3dB*/ + else if (pDM_Odm->RSSI_Min < 55) + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); /*Resp TXAGC offset = 0dB*/ + } + } +#endif +} + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) + + + prtl8192cd_priv priv = pDM_Odm->priv; + s4Byte i; + s2Byte pwr_thd = 63; + + if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) + return; + +#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8822B)) + pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1; +#endif + + /* + * Check if station is near by to use lower tx power + */ + + if ((priv->up_time % 3) == 0 ) { + + u1Byte igi; + u4Byte fa_cnt; + + #if (PHYDM_TDMA_DIG_SUPPORT == 1) + if (ODMPTR->original_dig_restore == 0) + { + fa_cnt = pDM_Odm->FalseAlmCnt_Acc.Cnt_all_1sec[TDMA_DIG_HIGH_STATE]; + igi = ODMPTR->DM_DigTable.tdma_igi[TDMA_DIG_HIGH_STATE]; + } + else + #endif + { + fa_cnt = pDM_Odm->FalseAlmCnt.Cnt_all; + igi = (RTL_R8(0xc50) & 0x7f); + } + + int disable_pwr_ctrl = ((fa_cnt > 1000 ) || ((fa_cnt > 300 ) && (igi >= 0x32))) ? 1 : 0; + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) { + if(disable_pwr_ctrl) + pstat->hp_level = 0; + else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) + pstat->hp_level = 1; + else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8))) + pstat->hp_level = 0; + } + } + +#if defined(CONFIG_WLAN_HAL_8192EE) || defined(CONFIG_WLAN_HAL_8822BE) + if (GET_CHIP_VER(priv) == VERSION_8192E || GET_CHIP_VER(priv) == VERSION_8822B) { + if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) { + if(pDM_Odm->RSSI_Min > pwr_thd) + RRSR_power_control_11n(priv, 1 ); + else if(pDM_Odm->RSSI_Min < (pwr_thd-8)) + RRSR_power_control_11n(priv, 0 ); + } else { + RRSR_power_control_11n(priv, 0 ); + } + } +#endif + +#ifdef CONFIG_WLAN_HAL_8814AE + if (GET_CHIP_VER(priv) == VERSION_8814A) { + if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) { + if (pDM_Odm->RSSI_Min > pwr_thd) + RRSR_power_control_14(priv, 1); + else if (pDM_Odm->RSSI_Min < (pwr_thd-8)) + RRSR_power_control_14(priv, 0); + } else { + RRSR_power_control_14(priv, 0); + } + } +#endif + + } +//#endif + +#endif +} + +VOID +odm_DynamicTxPower_8821( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + ) +{ +#if (RTL8821A_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u1Byte reg0xc56_byte; + u1Byte txpwr_offset = 0; + + pEntry = pDM_Odm->pODM_StaInfo[macId]; + + reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); + + if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) { + + /* Avoid TXAGC error after TX power offset is applied. + For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) + Total power = 6-11= -5( overflow!! ), PA may be burned ! + so txpwr_offset should be adjusted by Reg0xc56*/ + + if (reg0xc56_byte < 7) + txpwr_offset = 1; + else if (reg0xc56_byte < 11) + txpwr_offset = 2; + else + txpwr_offset = 3; + + SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); + + } else{ + SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); + + } +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ +#endif /*#if (RTL8821A_SUPPORT==1)*/ +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_DynamicTxPower_8814A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s4Byte UndecoratedSmoothedPWDB; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("TxLevel=%d pMgntInfo->IOTAction=%x pMgntInfo->bDynamicTxPowerEnable=%d\n", + pHalData->DynamicTxHighPowerLvl, pMgntInfo->IOTAction, pMgntInfo->bDynamicTxPowerEnable)); + + /*STA not connected and AP not connected*/ + if ((!pMgntInfo->bMediaConnect) && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + return; + } + + + if ((pMgntInfo->bDynamicTxPowerEnable != TRUE) || pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + } else { + if (pMgntInfo->bMediaConnect) { /*Default port*/ + if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); + } else { + UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); + } + } else {/*associated entry pwdb*/ + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); + } + + /*Should we separate as 2.4G/5G band?*/ + + if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + } + + + if (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8814A() Channel = %d\n" , pHalData->CurrentChannel)); + odm_SetTxPowerLevel8814(Adapter, pHalData->CurrentChannel, pHalData->DynamicTxHighPowerLvl); + } + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("odm_DynamicTxPower_8814A() Channel = %d TXpower lvl=%d/%d\n" , + pHalData->CurrentChannel, pHalData->LastDTPLvl, pHalData->DynamicTxHighPowerLvl)); + + pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; + +} + + + +/**/ +/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/ +/**/ +/**/ +VOID +odm_SetTxPowerLevel8814( + IN PADAPTER Adapter, + IN u1Byte Channel, + IN u1Byte PwrLvl + ) +{ +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + u4Byte i, j, k = 0; + u4Byte value[264] = {0}; + u4Byte path = 0, PowerIndex, txagc_table_wd = 0x00801000; + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + u1Byte jaguar2Rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, + {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, + {MGN_24M, MGN_36M, MGN_48M, MGN_54M}, + {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3}, + {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, + {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11}, + {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, + {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19}, + {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, + {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3}, + {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7}, + {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1}, + {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5}, + {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, + {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3}, + {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7}, + {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} }; + + for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { + + u1Byte usb_host = UsbModeQueryHubUsbType(Adapter); + u1Byte usb_rfset = UsbModeQueryRfSet(Adapter); + u1Byte usb_rf_type = RT_GetRFType(Adapter); + + for (i = 0; i <= 16; i++) { + for (j = 0; j <= 3; j++) { + if (jaguar2Rates[i][j] == 0) + continue; + + txagc_table_wd = 0x00801000; + PowerIndex = (u4Byte) PHY_GetTxPowerIndex(Adapter, (u1Byte)path, jaguar2Rates[i][j], pHalData->CurrentChannelBW, Channel); + + /*for Query bus type to recude tx power.*/ + if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(Adapter) && usb_rf_type == RF_3T3R) { + if (Channel <= 14) { + if (PowerIndex >= 16) + PowerIndex -= 16; + else + PowerIndex = 0; + } else + PowerIndex = 0; + } + + if (PwrLvl == TxHighPwrLevel_Level1) { + if (PowerIndex >= 0x10) + PowerIndex -= 0x10; + else + PowerIndex = 0; + } else if (PwrLvl == TxHighPwrLevel_Level2) { + PowerIndex = 0; + } + + txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2Rates[i][j]) | (PowerIndex << 24); + + PHY_SetTxPowerIndexShadow(Adapter, (u1Byte)PowerIndex, (u1Byte)path, jaguar2Rates[i][j]); + + value[k++] = txagc_table_wd; + } + } + } + + if (Adapter->MgntInfo.bScanInProgress == FALSE && Adapter->MgntInfo.RegFWOffload == 2) + HalDownloadTxPowerLevel8814(Adapter, value); +#endif +} +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.h b/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.h index 9d1c7f52a4a..0e47fc2f923 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.h +++ b/package/kernel/rtl8192cd/phydm/phydm_dynamictxpower.h @@ -1,110 +1,110 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMDYNAMICTXPOWER_H__ -#define __PHYDMDYNAMICTXPOWER_H__ - -/*#define DYNAMIC_TXPWR_VERSION "1.0"*/ -/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/ -#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/ - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 - #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 -#endif - -#define TxHighPwrLevel_Normal 0 -#define TxHighPwrLevel_Level1 1 -#define TxHighPwrLevel_Level2 2 - -#define TxHighPwrLevel_BT1 3 -#define TxHighPwrLevel_BT2 4 -#define TxHighPwrLevel_15 5 -#define TxHighPwrLevel_35 6 -#define TxHighPwrLevel_50 7 -#define TxHighPwrLevel_70 8 -#define TxHighPwrLevel_100 9 - -VOID -odm_DynamicTxPowerInit( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerRestorePowerIndex( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerNIC( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -odm_DynamicTxPowerSavePowerIndex( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerWritePowerIndex( - IN PVOID pDM_VOID, - IN u1Byte Value); - -VOID -odm_DynamicTxPower_8821( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId - ); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_DynamicTxPower_8814A( - IN PVOID pDM_VOID - ); - - -VOID -odm_SetTxPowerLevel8814( - IN PADAPTER Adapter, - IN u1Byte Channel, - IN u1Byte PwrLvl - ); -#endif -#endif - -VOID -odm_DynamicTxPower( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerAP( - IN PVOID pDM_VOID - ); - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ + +/*#define DYNAMIC_TXPWR_VERSION "1.0"*/ +/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/ +#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 + #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 + #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 + #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 + #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 +#endif + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 + +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value); + +VOID +odm_DynamicTxPower_8821( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + ); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_DynamicTxPower_8814A( + IN PVOID pDM_VOID + ); + + +VOID +odm_SetTxPowerLevel8814( + IN PADAPTER Adapter, + IN u1Byte Channel, + IN u1Byte PwrLvl + ); +#endif +#endif + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + ); + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.c b/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.c index 9020839965f..7662e76149f 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.c +++ b/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.c @@ -1,763 +1,763 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -ODM_EdcaTurboInit( - IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if (DM_ODM_SUPPORT_TYPE==ODM_WIN) - PADAPTER Adapter = NULL; - HAL_DATA_TYPE *pHalData = NULL; - - if(pDM_Odm->Adapter==NULL) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); - return; - } - - Adapter=pDM_Odm->Adapter; - pHalData=GET_HAL_DATA(Adapter); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; - pHalData->bIsAnyNonBEPkts = FALSE; - -#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; - Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; - -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); - - -} // ODM_InitEdcaTurbo - -VOID -odm_EdcaTurboCheck( - IN PVOID pDM_VOID - ) -{ - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); - - if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) - return; - - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - odm_EdcaTurboCheckMP(pDM_Odm); -#endif - break; - - case ODM_CE: -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - odm_EdcaTurboCheckCE(pDM_Odm); -#endif - break; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); - -} // odm_CheckEdcaTurbo - -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - - -VOID -odm_EdcaTurboCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; - u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; - u32 ICType=pDM_Odm->SupportICType; - u32 IOTPeer=0; - u8 WirelessMode=0xFF; //invalid value - u32 trafficIndex; - u32 edca_param; - u64 cur_tx_bytes = 0; - u64 cur_rx_bytes = 0; - u8 bbtchange = _FALSE; - u8 bBiasOnRx = _FALSE; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct recv_priv *precvpriv = &(Adapter->recvpriv); - struct registry_priv *pregpriv = &Adapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if(pDM_Odm->bLinked != _TRUE) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if(pDM_Odm->pWirelessMode!=NULL) - WirelessMode=*(pDM_Odm->pWirelessMode); - - IOTPeer = pmlmeinfo->assoc_AP_vendor; - - if (IOTPeer >= HT_IOT_PEER_MAX) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if (pDM_Odm->SupportICType & ODM_RTL8188E) { - if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS)) - bBiasOnRx = _TRUE; - } - - // Check if the status needs to be changed. - if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) - { - cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes; - cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes; - - //traffic, TX or RX - if(bBiasOnRx) - { - if (cur_tx_bytes > (cur_rx_bytes << 2)) - { // Uplink TP is present. - trafficIndex = UP_LINK; - } - else - { // Balance TP is present. - trafficIndex = DOWN_LINK; - } - } - else - { - if (cur_rx_bytes > (cur_tx_bytes << 2)) - { // Downlink TP is present. - trafficIndex = DOWN_LINK; - } - else - { // Balance TP is present. - trafficIndex = UP_LINK; - } - } - - //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { - EDCA_BE_UL = 0x6ea42b; - EDCA_BE_DL = 0x6ea42b; - } - - //92D txop can't be set to 0x3e for cisco1250 - if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) - { - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - EDCA_BE_UL = edca_setting_UL[IOTPeer]; - } - //merge from 92s_92c_merge temp brunch v2445 20120215 - else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) - { - EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer]; - } - else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) - { - EDCA_BE_DL = 0xa630; - } - else if(IOTPeer == HT_IOT_PEER_MARVELL) - { - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - EDCA_BE_UL = edca_setting_UL[IOTPeer]; - } - else if(IOTPeer == HT_IOT_PEER_ATHEROS) - { - // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - } - - if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE - { - EDCA_BE_UL = 0x5ea42b; - EDCA_BE_DL = 0x5ea42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL)); - } - - if (trafficIndex == DOWN_LINK) - edca_param = EDCA_BE_DL; - else - edca_param = EDCA_BE_UL; - - rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); - - pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; - } - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; - } - else - { - // - // Turn Off EDCA turbo here. - // Restore original EDCA according to the declaration of AP. - // - if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) - { - rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; - } - } - -} - - -#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN) -VOID -odm_EdcaTurboCheckMP( - IN PVOID pDM_VOID - ) -{ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); - PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; - //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn - u8Byte Ext_curTxOkCnt = 0; - u8Byte Ext_curRxOkCnt = 0; - //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. - u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; - - // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. - u8Byte curTxOkCnt = 0; - u8Byte curRxOkCnt = 0; - u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; - u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; - u4Byte EDCA_BE = 0x5ea42b; - u1Byte IOTPeer=0; - BOOLEAN *pbIsCurRDLState=NULL; - BOOLEAN bLastIsCurRDLState=FALSE; - BOOLEAN bBiasOnRx=FALSE; - BOOLEAN bEdcaTurboOn=FALSE; - u1Byte TxRate = 0xFF; - u8Byte value64; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); - -////=============================== -////list paramter for different platform -////=============================== - bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; - pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); - - //2012/09/14 MH Add - if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !(Adapter->MgntInfo.bWiFiConfg & RT_WIFI_LOGO)) - pHalData->bIsAnyNonBEPkts = TRUE; - - pMgntInfo->NumNonBePkt = 0; - - // Caculate TX/RX TP: - curTxOkCnt = pDM_Odm->curTxOkCnt; - curRxOkCnt = pDM_Odm->curRxOkCnt; - - - if(pExtAdapter == NULL) - pExtAdapter = pDefaultAdapter; - - Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; - Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; - GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); - //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. - if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) - { - curTxOkCnt = Ext_curTxOkCnt ; - curRxOkCnt = Ext_curRxOkCnt ; - } - // - IOTPeer=pMgntInfo->IOTPeer; - bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; - bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts)); - - -////=============================== -////check if edca turbo is disabled -////=============================== - if(odm_IsEdcaTurboDisable(pDM_Odm)) - { - pHalData->bIsAnyNonBEPkts = FALSE; - pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; - pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; - pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; - pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; - - } - -////=============================== -////remove iot case out -////=============================== - ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); - - -////=============================== -////Check if the status needs to be changed. -////=============================== - if(bEdcaTurboOn) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); - if(bBiasOnRx) - odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); - else - odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); - -//modify by Guo.Mingzhi 2011-12-29 - EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; - if(IS_HARDWARE_TYPE_8821U(Adapter)) - { - if(pMgntInfo->RegTxDutyEnable) - { - //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) - if(!pMgntInfo->ForcedDataRate) //auto rate - { - if(pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } - else //force rate - { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } - - value64 = (curRxOkCnt<<2); - if(curTxOkCnt < value64) //Downlink - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else //Uplink - { - /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ - /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ - if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else - { - switch (TxRate) - { - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS5: - case MGN_MCS6: - case MGN_MCS5: - case MGN_48M: - case MGN_54M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b); - break; - case MGN_VHT1SS_MCS4: - case MGN_MCS4: - case MGN_36M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b); - break; - case MGN_VHT1SS_MCS3: - case MGN_MCS3: - case MGN_24M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f); - break; - case MGN_VHT1SS_MCS2: - case MGN_MCS2: - case MGN_18M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f); - break; - case MGN_VHT1SS_MCS1: - case MGN_MCS1: - case MGN_9M: - case MGN_12M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f); - break; - case MGN_VHT1SS_MCS0: - case MGN_MCS0: - case MGN_6M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); - break; - default: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - break; - } - } - } - } - else - { - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - } - - } - else if (IS_HARDWARE_TYPE_8812AU(Adapter)){ - if(pMgntInfo->RegTxDutyEnable) - { - //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) - // it;s the same issue as 8811AU - if(!pMgntInfo->ForcedDataRate) //auto rate - { - if(pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } - else //force rate - { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } - - value64 = (curRxOkCnt<<2); - if(curTxOkCnt < value64) //Downlink - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else //Uplink - { - /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ - /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ - if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else - { - switch (TxRate) - { - case MGN_VHT2SS_MCS9: - case MGN_VHT1SS_MCS9: - case MGN_VHT1SS_MCS8: - case MGN_MCS15: - case MGN_MCS7: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f); - case MGN_VHT2SS_MCS8: - case MGN_VHT1SS_MCS7: - case MGN_MCS14: - case MGN_MCS6: - case MGN_54M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f); - case MGN_VHT2SS_MCS7: - case MGN_VHT2SS_MCS6: - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS5: - case MGN_MCS13: - case MGN_MCS5: - case MGN_48M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630); - break; - case MGN_VHT2SS_MCS5: - case MGN_VHT2SS_MCS4: - case MGN_VHT1SS_MCS4: - case MGN_VHT1SS_MCS3: - case MGN_MCS12: - case MGN_MCS4: - case MGN_MCS3: - case MGN_36M: - case MGN_24M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730); - break; - case MGN_VHT2SS_MCS3: - case MGN_VHT2SS_MCS2: - case MGN_VHT2SS_MCS1: - case MGN_VHT1SS_MCS2: - case MGN_VHT1SS_MCS1: - case MGN_MCS11: - case MGN_MCS10: - case MGN_MCS9: - case MGN_MCS2: - case MGN_MCS1: - case MGN_18M: - case MGN_12M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830); - break; - case MGN_VHT2SS_MCS0: - case MGN_VHT1SS_MCS0: - case MGN_MCS0: - case MGN_MCS8: - case MGN_9M: - case MGN_6M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); - break; - default: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - break; - } - } - } - } - else - { - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - } - } - else - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); - - } - else - { - // Turn Off EDCA turbo here. - // Restore original EDCA according to the declaration of AP. - if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) - { - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); - - } - } - -} - - -//check if edca turbo is disabled -BOOLEAN -odm_IsEdcaTurboDisable( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - u4Byte IOTPeer=pMgntInfo->IOTPeer; - - if(pDM_Odm->bBtDisableEdcaTurbo) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); - return TRUE; - } - - if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| - (pDM_Odm->WIFITest & RT_WIFI_LOGO)|| - (IOTPeer>= HT_IOT_PEER_MAX)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); - return TRUE; - } - - - // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue - // 2. User may disable EDCA Turbo mode with OID settings. - if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); - return TRUE; - } - - return FALSE; - - -} - -//add iot case here: for MP/CE -VOID -ODM_EdcaParaSelByIot( - IN PVOID pDM_VOID, - OUT u4Byte *EDCA_BE_UL, - OUT u4Byte *EDCA_BE_DL - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - u4Byte IOTPeer=0; - u4Byte ICType=pDM_Odm->SupportICType; - u1Byte WirelessMode=0xFF; //invalid value - u4Byte IOTPeerSubType = 0; - - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; - - if(pDM_Odm->pWirelessMode!=NULL) - WirelessMode=*(pDM_Odm->pWirelessMode); - -/////////////////////////////////////////////////////////// -////list paramter for different platform - - IOTPeer=pMgntInfo->IOTPeer; - IOTPeerSubType=pMgntInfo->IOTPeerSubtype; - GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); - -////============================ -/// IOT case for MP -////============================ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { - (*EDCA_BE_UL) = 0x6ea42b; - (*EDCA_BE_DL) = 0x6ea42b; - } - - if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) - { - (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; - (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; - } - - #if (INTEL_PROXIMITY_SUPPORT == 1) - if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) - { - (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; - } - else - #endif - { - if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) - {// To check whether we shall force turn on TXOP configuration. - if(!((*EDCA_BE_UL) & 0xffff0000)) - (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. - if(!((*EDCA_BE_DL) & 0xffff0000)) - (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. - } - - //92D txop can't be set to 0x3e for cisco1250 - if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) - { - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; - } - //merge from 92s_92c_merge temp brunch v2445 20120215 - else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) - { - (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; - } - else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) - { - (*EDCA_BE_DL) = 0xa630; - } - - else if(IOTPeer == HT_IOT_PEER_MARVELL) - { - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; - } - else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750) - { - // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. - if(WirelessMode==ODM_WM_G) - (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; - else - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - - if(ICType == ODM_RTL8821) - (*EDCA_BE_DL) = 0x5ea630; - - } - } - - if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE - { - (*EDCA_BE_UL) = 0x5ea42b; - (*EDCA_BE_DL) = 0x5ea42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); - } - - if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/ - { - (*EDCA_BE_UL) = 0x5ea42b; - (*EDCA_BE_DL) = 0xa42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer)); - -} - - -VOID -odm_EdcaChooseTrafficIdx( - IN PVOID pDM_VOID, - IN u8Byte cur_tx_bytes, - IN u8Byte cur_rx_bytes, - IN BOOLEAN bBiasOnRx, - OUT BOOLEAN *pbIsCurRDLState - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if(bBiasOnRx) - { - - if(cur_tx_bytes>(cur_rx_bytes*4)) - { - *pbIsCurRDLState=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); - - } - else - { - *pbIsCurRDLState=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); - - } - } - else - { - if(cur_rx_bytes>(cur_tx_bytes*4)) - { - *pbIsCurRDLState=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); - - } - else - { - *pbIsCurRDLState=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); - } - } - - return ; -} - -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (DM_ODM_SUPPORT_TYPE==ODM_WIN) + PADAPTER Adapter = NULL; + HAL_DATA_TYPE *pHalData = NULL; + + if(pDM_Odm->Adapter==NULL) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); + return; + } + + Adapter=pDM_Odm->Adapter; + pHalData=GET_HAL_DATA(Adapter); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + pHalData->bIsAnyNonBEPkts = FALSE; + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; + +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); + + +} // ODM_InitEdcaTurbo + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); + + if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) + return; + + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + odm_EdcaTurboCheckMP(pDM_Odm); +#endif + break; + + case ODM_CE: +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + odm_EdcaTurboCheckCE(pDM_Odm); +#endif + break; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); + +} // odm_CheckEdcaTurbo + +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + + +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; + u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; + u32 ICType=pDM_Odm->SupportICType; + u32 IOTPeer=0; + u8 WirelessMode=0xFF; //invalid value + u32 trafficIndex; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = _FALSE; + u8 bBiasOnRx = _FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct recv_priv *precvpriv = &(Adapter->recvpriv); + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if(pDM_Odm->bLinked != _TRUE) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + + IOTPeer = pmlmeinfo->assoc_AP_vendor; + + if (IOTPeer >= HT_IOT_PEER_MAX) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if (pDM_Odm->SupportICType & ODM_RTL8188E) { + if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS)) + bBiasOnRx = _TRUE; + } + + // Check if the status needs to be changed. + if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) + { + cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes; + cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes; + + //traffic, TX or RX + if(bBiasOnRx) + { + if (cur_tx_bytes > (cur_rx_bytes << 2)) + { // Uplink TP is present. + trafficIndex = UP_LINK; + } + else + { // Balance TP is present. + trafficIndex = DOWN_LINK; + } + } + else + { + if (cur_rx_bytes > (cur_tx_bytes << 2)) + { // Downlink TP is present. + trafficIndex = DOWN_LINK; + } + else + { // Balance TP is present. + trafficIndex = UP_LINK; + } + } + + //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + + //92D txop can't be set to 0x3e for cisco1250 + if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) + { + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + EDCA_BE_UL = edca_setting_UL[IOTPeer]; + } + //merge from 92s_92c_merge temp brunch v2445 20120215 + else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) + { + EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer]; + } + else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) + { + EDCA_BE_DL = 0xa630; + } + else if(IOTPeer == HT_IOT_PEER_MARVELL) + { + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + EDCA_BE_UL = edca_setting_UL[IOTPeer]; + } + else if(IOTPeer == HT_IOT_PEER_ATHEROS) + { + // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + } + + if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE + { + EDCA_BE_UL = 0x5ea42b; + EDCA_BE_DL = 0x5ea42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL)); + } + + if (trafficIndex == DOWN_LINK) + edca_param = EDCA_BE_DL; + else + edca_param = EDCA_BE_UL; + + rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); + + pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; + } + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; + } + else + { + // + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + // + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { + rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; + } + } + +} + + +#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); + PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; + //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn + u8Byte Ext_curTxOkCnt = 0; + u8Byte Ext_curRxOkCnt = 0; + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + + // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. + u8Byte curTxOkCnt = 0; + u8Byte curRxOkCnt = 0; + u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE = 0x5ea42b; + u1Byte IOTPeer=0; + BOOLEAN *pbIsCurRDLState=NULL; + BOOLEAN bLastIsCurRDLState=FALSE; + BOOLEAN bBiasOnRx=FALSE; + BOOLEAN bEdcaTurboOn=FALSE; + u1Byte TxRate = 0xFF; + u8Byte value64; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + +////=============================== +////list paramter for different platform +////=============================== + bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; + pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); + + //2012/09/14 MH Add + if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !(Adapter->MgntInfo.bWiFiConfg & RT_WIFI_LOGO)) + pHalData->bIsAnyNonBEPkts = TRUE; + + pMgntInfo->NumNonBePkt = 0; + + // Caculate TX/RX TP: + curTxOkCnt = pDM_Odm->curTxOkCnt; + curRxOkCnt = pDM_Odm->curRxOkCnt; + + + if(pExtAdapter == NULL) + pExtAdapter = pDefaultAdapter; + + Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; + Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + curTxOkCnt = Ext_curTxOkCnt ; + curRxOkCnt = Ext_curRxOkCnt ; + } + // + IOTPeer=pMgntInfo->IOTPeer; + bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; + bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts)); + + +////=============================== +////check if edca turbo is disabled +////=============================== + if(odm_IsEdcaTurboDisable(pDM_Odm)) + { + pHalData->bIsAnyNonBEPkts = FALSE; + pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; + pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; + + } + +////=============================== +////remove iot case out +////=============================== + ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); + + +////=============================== +////Check if the status needs to be changed. +////=============================== + if(bEdcaTurboOn) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); + if(bBiasOnRx) + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); + else + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); + +//modify by Guo.Mingzhi 2011-12-29 + EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; + if(IS_HARDWARE_TYPE_8821U(Adapter)) + { + if(pMgntInfo->RegTxDutyEnable) + { + //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) + if(!pMgntInfo->ForcedDataRate) //auto rate + { + if(pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } + else //force rate + { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } + + value64 = (curRxOkCnt<<2); + if(curTxOkCnt < value64) //Downlink + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else //Uplink + { + /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ + /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ + if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else + { + switch (TxRate) + { + case MGN_VHT1SS_MCS6: + case MGN_VHT1SS_MCS5: + case MGN_MCS6: + case MGN_MCS5: + case MGN_48M: + case MGN_54M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b); + break; + case MGN_VHT1SS_MCS4: + case MGN_MCS4: + case MGN_36M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b); + break; + case MGN_VHT1SS_MCS3: + case MGN_MCS3: + case MGN_24M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f); + break; + case MGN_VHT1SS_MCS2: + case MGN_MCS2: + case MGN_18M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f); + break; + case MGN_VHT1SS_MCS1: + case MGN_MCS1: + case MGN_9M: + case MGN_12M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f); + break; + case MGN_VHT1SS_MCS0: + case MGN_MCS0: + case MGN_6M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); + break; + default: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + break; + } + } + } + } + else + { + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + } + + } + else if (IS_HARDWARE_TYPE_8812AU(Adapter)){ + if(pMgntInfo->RegTxDutyEnable) + { + //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) + // it;s the same issue as 8811AU + if(!pMgntInfo->ForcedDataRate) //auto rate + { + if(pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } + else //force rate + { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } + + value64 = (curRxOkCnt<<2); + if(curTxOkCnt < value64) //Downlink + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else //Uplink + { + /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ + /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ + if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else + { + switch (TxRate) + { + case MGN_VHT2SS_MCS9: + case MGN_VHT1SS_MCS9: + case MGN_VHT1SS_MCS8: + case MGN_MCS15: + case MGN_MCS7: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f); + case MGN_VHT2SS_MCS8: + case MGN_VHT1SS_MCS7: + case MGN_MCS14: + case MGN_MCS6: + case MGN_54M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f); + case MGN_VHT2SS_MCS7: + case MGN_VHT2SS_MCS6: + case MGN_VHT1SS_MCS6: + case MGN_VHT1SS_MCS5: + case MGN_MCS13: + case MGN_MCS5: + case MGN_48M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630); + break; + case MGN_VHT2SS_MCS5: + case MGN_VHT2SS_MCS4: + case MGN_VHT1SS_MCS4: + case MGN_VHT1SS_MCS3: + case MGN_MCS12: + case MGN_MCS4: + case MGN_MCS3: + case MGN_36M: + case MGN_24M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730); + break; + case MGN_VHT2SS_MCS3: + case MGN_VHT2SS_MCS2: + case MGN_VHT2SS_MCS1: + case MGN_VHT1SS_MCS2: + case MGN_VHT1SS_MCS1: + case MGN_MCS11: + case MGN_MCS10: + case MGN_MCS9: + case MGN_MCS2: + case MGN_MCS1: + case MGN_18M: + case MGN_12M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830); + break; + case MGN_VHT2SS_MCS0: + case MGN_VHT1SS_MCS0: + case MGN_MCS0: + case MGN_MCS8: + case MGN_9M: + case MGN_6M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); + break; + default: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + break; + } + } + } + } + else + { + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + } + } + else + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); + + } + else + { + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); + + } + } + +} + + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u4Byte IOTPeer=pMgntInfo->IOTPeer; + + if(pDM_Odm->bBtDisableEdcaTurbo) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); + return TRUE; + } + + if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| + (pDM_Odm->WIFITest & RT_WIFI_LOGO)|| + (IOTPeer>= HT_IOT_PEER_MAX)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); + return TRUE; + } + + + // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue + // 2. User may disable EDCA Turbo mode with OID settings. + if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); + return TRUE; + } + + return FALSE; + + +} + +//add iot case here: for MP/CE +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + u4Byte IOTPeer=0; + u4Byte ICType=pDM_Odm->SupportICType; + u1Byte WirelessMode=0xFF; //invalid value + u4Byte IOTPeerSubType = 0; + + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + +/////////////////////////////////////////////////////////// +////list paramter for different platform + + IOTPeer=pMgntInfo->IOTPeer; + IOTPeerSubType=pMgntInfo->IOTPeerSubtype; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + +////============================ +/// IOT case for MP +////============================ + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; + (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; + } + + #if (INTEL_PROXIMITY_SUPPORT == 1) + if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) + { + (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; + } + else + #endif + { + if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) + {// To check whether we shall force turn on TXOP configuration. + if(!((*EDCA_BE_UL) & 0xffff0000)) + (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. + if(!((*EDCA_BE_DL) & 0xffff0000)) + (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. + } + + //92D txop can't be set to 0x3e for cisco1250 + if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + //merge from 92s_92c_merge temp brunch v2445 20120215 + else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) + { + (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; + } + else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) + { + (*EDCA_BE_DL) = 0xa630; + } + + else if(IOTPeer == HT_IOT_PEER_MARVELL) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750) + { + // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. + if(WirelessMode==ODM_WM_G) + (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; + else + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + + if(ICType == ODM_RTL8821) + (*EDCA_BE_DL) = 0x5ea630; + + } + } + + if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE + { + (*EDCA_BE_UL) = 0x5ea42b; + (*EDCA_BE_DL) = 0x5ea42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); + } + + if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/ + { + (*EDCA_BE_UL) = 0x5ea42b; + (*EDCA_BE_DL) = 0xa42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer)); + +} + + +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if(bBiasOnRx) + { + + if(cur_tx_bytes>(cur_rx_bytes*4)) + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); + + } + else + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + + } + } + else + { + if(cur_rx_bytes>(cur_tx_bytes*4)) + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); + + } + else + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + } + } + + return ; +} + +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.h b/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.h index 2671f863eef..7dd0997143d 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.h +++ b/package/kernel/rtl8192cd/phydm/phydm_edcaturbocheck.h @@ -1,100 +1,100 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMEDCATURBOCHECK_H__ -#define __PHYDMEDCATURBOCHECK_H__ - -/*#define EDCATURBO_VERSION "2.1"*/ -#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/ - -typedef struct _EDCA_TURBO_ -{ - BOOLEAN bCurrentTurboEDCA; - BOOLEAN bIsCurRDLState; - - #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) - u4Byte prv_traffic_idx; // edca turbo - #endif - -}EDCA_T,*pEDCA_T; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) -{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; - - -static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) -{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; - -static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP -{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; - -#endif - - - -VOID -odm_EdcaTurboCheck( - IN PVOID pDM_VOID - ); -VOID -ODM_EdcaTurboInit( - IN PVOID pDM_VOID -); - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) -VOID -odm_EdcaTurboCheckMP( - IN PVOID pDM_VOID - ); - -//check if edca turbo is disabled -BOOLEAN -odm_IsEdcaTurboDisable( - IN PVOID pDM_VOID -); -//choose edca paramter for special IOT case -VOID -ODM_EdcaParaSelByIot( - IN PVOID pDM_VOID, - OUT u4Byte *EDCA_BE_UL, - OUT u4Byte *EDCA_BE_DL - ); -//check if it is UL or DL -VOID -odm_EdcaChooseTrafficIdx( - IN PVOID pDM_VOID, - IN u8Byte cur_tx_bytes, - IN u8Byte cur_rx_bytes, - IN BOOLEAN bBiasOnRx, - OUT BOOLEAN *pbIsCurRDLState - ); - -#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) -VOID -odm_EdcaTurboCheckCE( - IN PVOID pDM_VOID - ); -#endif - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMEDCATURBOCHECK_H__ +#define __PHYDMEDCATURBOCHECK_H__ + +/*#define EDCATURBO_VERSION "2.1"*/ +#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/ + +typedef struct _EDCA_TURBO_ +{ + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; + + #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) + u4Byte prv_traffic_idx; // edca turbo + #endif + +}EDCA_T,*pEDCA_T; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + + +static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + +#endif + + + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ); +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID +); + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ); + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +); +//choose edca paramter for special IOT case +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ); +//check if it is UL or DL +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ); + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ); +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_features.h b/package/kernel/rtl8192cd/phydm/phydm_features.h index 8ea6f349d6b..facf5f54bdf 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_features.h +++ b/package/kernel/rtl8192cd/phydm/phydm_features.h @@ -1,169 +1,169 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDM_FEATURES_H__ -#define __PHYDM_FEATURES - -#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - #define PHYDM_LA_MODE_SUPPORT 1 -#else - #define PHYDM_LA_MODE_SUPPORT 0 -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*Antenna Diversity*/ - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #define CONFIG_FAT_PATCH - #endif - #endif - - #define RA_MASK_PHYDMLIZE_WIN 1 - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_ANT_DETECTION - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 1 - /*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/ - #define CONFIG_BB_POWER_SAVING - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #define PHYDM_CCX_LNA_CHK_SUPPORT 1 - - #if ((RTL8197F_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) - #define PHYDM_TDMA_DIG_SUPPORT 1 - #endif - -#if (RTL8822B_SUPPORT == 1) - #define PHYDM_LNA_SAT_CHK_TYPE2 1 -#endif - - #define RA_MASK_PHYDMLIZE_AP 1 - - /* #define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_RA_DYNAMIC_RATE_ID - /*#define CONFIG_BB_POWER_SAVING*/ - #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - #define CONFIG_ADAPTIVE_SOML 1 - #else - #define CONFIG_ADAPTIVE_SOML 0 - #endif - - /* [ Configure Antenna Diversity ] */ - #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #define ODM_EVM_ENHANCE_ANTDIV - #define SKIP_EVM_ANTDIV_TRAINING_PATCH 1 - - /*----------*/ - #ifdef CONFIG_NO_2G_DIVERSITY_8197F - #define CONFIG_NO_2G_DIVERSITY - #elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F) - #define CONFIG_2G_CGCS_RX_DIVERSITY - #elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F) - #define CONFIG_2G_CG_TRX_DIVERSITY - #endif - - #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_2G_DIVERSITY - #endif - - #ifdef CONFIG_NO_5G_DIVERSITY_8881A - #define CONFIG_NO_5G_DIVERSITY - #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) - #define CONFIG_5G_CGCS_RX_DIVERSITY - #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_5G_CG_TRX_DIVERSITY - #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_2G5G_CG_TRX_DIVERSITY - #endif - #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_5G_DIVERSITY - #endif - /*----------*/ - #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_NOT_SUPPORT_ANTDIV - #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_2G_SUPPORT_ANTDIV - #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_5G_SUPPORT_ANTDIV - #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) - #define CONFIG_2G5G_SUPPORT_ANTDIV - #endif - /*----------*/ - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) - #define CONFIG_RECEIVER_BLOCKING - #endif - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - #define RA_MASK_PHYDMLIZE_CE 1 - - /*Antenna Diversity*/ - #ifdef CONFIG_ANTENNA_DIVERSITY - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #endif - #endif - #endif - - #ifdef CONFIG_DFS_MASTER - #define CONFIG_PHYDM_DFS_MASTER - #endif - - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - /*#define CONFIG_ANT_DETECTION*/ - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_BB_POWER_SAVING - - #ifdef CONFIG_BT_COEXIST - #define BT_SUPPORT 1 - #endif - - -#endif - - //#define CFG_DIG_DAMPING_CHK - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_FEATURES_H__ +#define __PHYDM_FEATURES + +#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*Antenna Diversity*/ + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #define CONFIG_FAT_PATCH + #endif + #endif + + #define RA_MASK_PHYDMLIZE_WIN 1 + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_ANT_DETECTION + /*#define CONFIG_RA_DBG_CMD*/ + #define CONFIG_RA_FW_DBG_CODE 1 + /*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/ + #define CONFIG_BB_POWER_SAVING + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #define PHYDM_CCX_LNA_CHK_SUPPORT 1 + + #if ((RTL8197F_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) + #define PHYDM_TDMA_DIG_SUPPORT 1 + #endif + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_LNA_SAT_CHK_TYPE2 1 +#endif + + #define RA_MASK_PHYDMLIZE_AP 1 + + /* #define CONFIG_RA_DBG_CMD*/ + #define CONFIG_RA_FW_DBG_CODE 0 + + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_RA_DYNAMIC_RATE_ID + /*#define CONFIG_BB_POWER_SAVING*/ + #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + #define CONFIG_ADAPTIVE_SOML 1 + #else + #define CONFIG_ADAPTIVE_SOML 0 + #endif + + /* [ Configure Antenna Diversity ] */ + #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + #define SKIP_EVM_ANTDIV_TRAINING_PATCH 1 + + /*----------*/ + #ifdef CONFIG_NO_2G_DIVERSITY_8197F + #define CONFIG_NO_2G_DIVERSITY + #elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F) + #define CONFIG_2G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F) + #define CONFIG_2G_CG_TRX_DIVERSITY + #endif + + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + /*----------*/ + #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + /*----------*/ + #endif + + #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define CONFIG_RECEIVER_BLOCKING + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + #define RA_MASK_PHYDMLIZE_CE 1 + + /*Antenna Diversity*/ + #ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + #endif + #endif + + #ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER + #endif + + /*#define CONFIG_RA_DBG_CMD*/ + #define CONFIG_RA_FW_DBG_CODE 0 + /*#define CONFIG_ANT_DETECTION*/ + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_BB_POWER_SAVING + + #ifdef CONFIG_BT_COEXIST + #define BT_SUPPORT 1 + #endif + + +#endif + + //#define CFG_DIG_DAMPING_CHK + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_hwconfig.c b/package/kernel/rtl8192cd/phydm/phydm_hwconfig.c index 8f52a2fd7ac..b9c1fca75d4 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_hwconfig.c +++ b/package/kernel/rtl8192cd/phydm/phydm_hwconfig.c @@ -1,3669 +1,3669 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig_MP_##ic##txt(pDM_Odm)) -#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC_##ic##txt(pDM_Odm)) - - -#if (PHYDM_TESTCHIP_SUPPORT == 1) -#define READ_AND_CONFIG(ic, txt) do {\ - if (pDM_Odm->bIsMPChip)\ - READ_AND_CONFIG_MP(ic,txt);\ - else\ - READ_AND_CONFIG_TC(ic,txt);\ - } while(0) -#else - #define READ_AND_CONFIG READ_AND_CONFIG_MP -#endif - - -#define READ_FIRMWARE_MP(ic, txt) (ODM_ReadFirmware_MP_##ic##txt(pDM_Odm, pFirmware, pSize)) -#define READ_FIRMWARE_TC(ic, txt) (ODM_ReadFirmware_TC_##ic##txt(pDM_Odm, pFirmware, pSize)) - -#if (PHYDM_TESTCHIP_SUPPORT == 1) -#define READ_FIRMWARE(ic, txt) do {\ - if (pDM_Odm->bIsMPChip)\ - READ_FIRMWARE_MP(ic,txt);\ - else\ - READ_FIRMWARE_TC(ic,txt);\ - } while(0) -#else -#define READ_FIRMWARE READ_FIRMWARE_MP -#endif - -#define GET_VERSION_MP(ic, txt) (ODM_GetVersion_MP_##ic##txt()) -#define GET_VERSION_TC(ic, txt) (ODM_GetVersion_TC_##ic##txt()) -#define GET_VERSION(ic, txt) (pDM_Odm->bIsMPChip?GET_VERSION_MP(ic,txt):GET_VERSION_TC(ic,txt)) - -u1Byte -odm_QueryRxPwrPercentage( - IN s1Byte AntPower - ) -{ - if ((AntPower <= -100) || (AntPower >= 20)) - return 0; - else if (AntPower >= 0) - return 100; - else - return (100 + AntPower); -} - - -// -// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. -// IF other SW team do not support the feature, remove this section.?? -// -s4Byte -odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( - IN OUT PDM_ODM_T pDM_Odm, - s4Byte CurrSig -) -{ - s4Byte RetSig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - { - // Step 1. Scale mapping. - // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. - // 20100426 Joseph: Modify Signal strength mapping. - // This modification makes the RSSI indication similar to Intel solution. - // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. - if (CurrSig >= 54 && CurrSig <= 100) - RetSig = 100; - else if (CurrSig >= 42 && CurrSig <= 53) - RetSig = 95; - else if (CurrSig >= 36 && CurrSig <= 41) - RetSig = 74 + ((CurrSig - 36) * 20) / 6; - else if (CurrSig >= 33 && CurrSig <= 35) - RetSig = 65 + ((CurrSig - 33) * 8) / 2; - else if (CurrSig >= 18 && CurrSig <= 32) - RetSig = 62 + ((CurrSig - 18) * 2) / 15; - else if (CurrSig >= 15 && CurrSig <= 17) - RetSig = 33 + ((CurrSig - 15) * 28) / 2; - else if (CurrSig >= 10 && CurrSig <= 14) - RetSig = 39; - else if (CurrSig >= 8 && CurrSig <= 9) - RetSig = 33; - else if (CurrSig <= 8) - RetSig = 19; - } -#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) - return RetSig; -} - -s4Byte -odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( - IN OUT PDM_ODM_T pDM_Odm, - s4Byte CurrSig -) -{ - s4Byte RetSig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) - { - // Netcore request this modification because 2009.04.13 SU driver use it. - if (CurrSig >= 31 && CurrSig <= 100) - RetSig = 100; - else if (CurrSig >= 21 && CurrSig <= 30) - RetSig = 90 + ((CurrSig - 20) / 1); - else if (CurrSig >= 11 && CurrSig <= 20) - RetSig = 80 + ((CurrSig - 10) / 1); - else if (CurrSig >= 7 && CurrSig <= 10) - RetSig = 69 + (CurrSig - 7); - else if (CurrSig == 6) - RetSig = 54; - else if (CurrSig == 5) - RetSig = 45; - else if (CurrSig == 4) - RetSig = 36; - else if (CurrSig == 3) - RetSig = 27; - else if (CurrSig == 2) - RetSig = 18; - else if (CurrSig == 1) - RetSig = 9; - else - RetSig = CurrSig; - } -#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) - return RetSig; -} - - -s4Byte -odm_SignalScaleMapping_92CSeries( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig -) -{ - s4Byte RetSig = 0; -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - { - // Step 1. Scale mapping. - if(CurrSig >= 61 && CurrSig <= 100) - { - RetSig = 90 + ((CurrSig - 60) / 4); - } - else if(CurrSig >= 41 && CurrSig <= 60) - { - RetSig = 78 + ((CurrSig - 40) / 2); - } - else if(CurrSig >= 31 && CurrSig <= 40) - { - RetSig = 66 + (CurrSig - 30); - } - else if(CurrSig >= 21 && CurrSig <= 30) - { - RetSig = 54 + (CurrSig - 20); - } - else if(CurrSig >= 5 && CurrSig <= 20) - { - RetSig = 42 + (((CurrSig - 5) * 2) / 3); - } - else if(CurrSig == 4) - { - RetSig = 36; - } - else if(CurrSig == 3) - { - RetSig = 27; - } - else if(CurrSig == 2) - { - RetSig = 18; - } - else if(CurrSig == 1) - { - RetSig = 9; - } - else - { - RetSig = CurrSig; - } - } -#endif - -#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) - { - if(CurrSig >= 51 && CurrSig <= 100) - { - RetSig = 100; - } - else if(CurrSig >= 41 && CurrSig <= 50) - { - RetSig = 80 + ((CurrSig - 40)*2); - } - else if(CurrSig >= 31 && CurrSig <= 40) - { - RetSig = 66 + (CurrSig - 30); - } - else if(CurrSig >= 21 && CurrSig <= 30) - { - RetSig = 54 + (CurrSig - 20); - } - else if(CurrSig >= 10 && CurrSig <= 20) - { - RetSig = 42 + (((CurrSig - 10) * 2) / 3); - } - else if(CurrSig >= 5 && CurrSig <= 9) - { - RetSig = 22 + (((CurrSig - 5) * 3) / 2); - } - else if(CurrSig >= 1 && CurrSig <= 4) - { - RetSig = 6 + (((CurrSig - 1) * 3) / 2); - } - else - { - RetSig = CurrSig; - } - } - -#endif - return RetSig; -} -s4Byte -odm_SignalScaleMapping( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if( (pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO - (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore - { - return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); - } - else if( (pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && - (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) - { - return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); - }else -#endif - { -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); -#else - return CurrSig; -#endif - } - -} - - - -static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( - IN PDM_ODM_T pDM_Odm, - IN u1Byte isCCKrate, - IN u1Byte PWDB_ALL, - IN u1Byte path, - IN u1Byte RSSI -) -{ - u1Byte SQ = 0; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if(isCCKrate){ - - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - - // - // Expected signal strength and bars indication at Lenovo lab. 2013.04.11 - // 802.11n, 802.11b, 802.11g only at channel 6 - // - // Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) - // 50 5 -49 - // 55 5 -49 - // 60 5 -50 - // 65 5 -51 - // 70 5 -52 - // 75 5 -54 - // 80 5 -55 - // 85 4 -60 - // 90 3 -63 - // 95 3 -65 - // 100 2 -67 - // 102 2 -67 - // 104 1 -70 - // - - if(PWDB_ALL >= 50) - SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if(PWDB_ALL >= 31 && PWDB_ALL < 35) - SQ = 60; - else if(PWDB_ALL >= 22 && PWDB_ALL < 31) - SQ = 40; - else if(PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 20; - else - SQ = 10; - } else { - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 22 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 40; - else - SQ = 10; - } - - } - else - {//OFDM rate - - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - if(RSSI >= 45) - SQ = 100; - else if(RSSI >= 22 && RSSI < 45) - SQ = 80; - else if(RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } else { - if(RSSI >= 45) - SQ = 100; - else if(RSSI >= 22 && RSSI < 45) - SQ = 80; - else if(RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_TRACE, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} - -static u1Byte odm_SQ_process_patch_RT_CID_819x_Acer( - IN PDM_ODM_T pDM_Odm, - IN u1Byte isCCKrate, - IN u1Byte PWDB_ALL, - IN u1Byte path, - IN u1Byte RSSI -) -{ - u1Byte SQ = 0; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if(isCCKrate){ - - RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); - -#if OS_WIN_FROM_WIN8(OS_VERSION) - - if(PWDB_ALL >= 50) - SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if(PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if(PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if(PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; -#else - if(PWDB_ALL >= 50) - SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if(PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if(PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if(PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; - - if(PWDB_ALL == 0)// Abnormal case, do not indicate the value above 20 on Win7 - SQ = 20; -#endif - - - - } - else - {//OFDM rate - - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - if(RSSI >= 45) - SQ = 100; - else if(RSSI >= 22 && RSSI < 45) - SQ = 80; - else if(RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } - else - { - if(RSSI >= 35) - SQ = 100; - else if(RSSI >= 30 && RSSI < 35) - SQ = 80; - else if(RSSI >= 25 && RSSI < 30) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_LOUD, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} - -static u1Byte -odm_EVMdbToPercentage( - IN s1Byte Value - ) -{ - // - // -33dB~0dB to 0%~99% - // - s1Byte ret_val; - - ret_val = Value; - ret_val /= 2; - - /*DbgPrint("Value=%d\n", Value);*/ - /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val));*/ -#ifdef ODM_EVM_ENHANCE_ANTDIV - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -40) - ret_val = -40; - - ret_val = 0 - ret_val; - ret_val *= 3; -#else - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -33) - ret_val = -33; - - ret_val = 0 - ret_val; - ret_val *= 3; - - if (ret_val == 99) - ret_val = 100; -#endif - - return (u1Byte)ret_val; -} - -static u1Byte -odm_EVMdbm_JaguarSeries( - IN s1Byte Value - ) -{ - s1Byte ret_val = Value; - - // -33dB~0dB to 33dB ~ 0dB - if(ret_val == -128) - ret_val = 127; - else if (ret_val < 0) - ret_val = 0 - ret_val; - - ret_val = ret_val >> 1; - return (u1Byte)ret_val; -} - -static s2Byte -odm_Cfo( - IN s1Byte Value -) -{ - s2Byte ret_val; - - if (Value < 0) - { - ret_val = 0 - Value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; // *2.5~=312.5/2^7 - ret_val = ret_val | BIT12; // set bit12 as 1 for negative cfo - } - else - { - ret_val = Value; - ret_val = (ret_val << 1) + (ret_val>>1) ; // *2.5~=312.5/2^7 - } - return ret_val; -} - -u1Byte -phydm_rate_to_num_ss( - IN OUT PDM_ODM_T pDM_Odm, - IN u1Byte DataRate -) -{ - u1Byte num_ss = 1; - - if (DataRate <= ODM_RATE54M) - num_ss = 1; - else if (DataRate <= ODM_RATEMCS31) - num_ss = ((DataRate - ODM_RATEMCS0) >> 3)+1; - else if (DataRate <= ODM_RATEVHTSS1MCS9) - num_ss = 1; - else if (DataRate <= ODM_RATEVHTSS2MCS9) - num_ss = 2; - else if (DataRate <= ODM_RATEVHTSS3MCS9) - num_ss = 3; - else if (DataRate <= ODM_RATEVHTSS4MCS9) - num_ss = 4; - - return num_ss; -} - -#if(ODM_IC_11N_SERIES_SUPPORT == 1) - -s1Byte -odm_CCKRSSI_8703B( - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) -{ - s1Byte rx_pwr_all = 0x00; - - switch (LNA_idx) { - case 0xf: - rx_pwr_all = -48 - (2 * VGA_idx); - break; - case 0xb: - rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ - break; - case 0xa: - rx_pwr_all = -36 - (2 * VGA_idx); - break; - case 8: - rx_pwr_all = -32 - (2 * VGA_idx); - break; - case 7: - rx_pwr_all = -19 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = -6 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = -2 - (2 * VGA_idx); - break; - default: - /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ - /*DbgPrint("wrong LNA index\n");*/ - break; - - } - return rx_pwr_all; -} - -s1Byte -odm_CCKRSSI_8192E( - IN OUT PDM_ODM_T pDM_Odm, - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) -{ - s1Byte rx_pwr_all = 0; - s1Byte lna_gain = 0; - s1Byte lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; - s1Byte lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ - - if (pDM_Odm->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[LNA_idx]; - else - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} - -s1Byte -odm_CCKRSSI_8188E( - IN OUT PDM_ODM_T pDM_Odm, - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) -{ - s1Byte rx_pwr_all = 0; - s1Byte lna_gain = 0; - s1Byte lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ - s1Byte lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ - - if (pDM_Odm->CutVersion >= ODM_CUT_I) /*SMIC*/ - lna_gain = lna_gain_table_0[LNA_idx]; - else /*TSMC*/ - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} - -s8 -phydm_cck_rssi_convert( - IN OUT PDM_ODM_T pDM_Odm, - u16 lna_idx, - u8 vga_idx -) -{ - return (pDM_Odm->cck_lna_gain_table[lna_idx] - (vga_idx << 1)); -} - -void -phydm_get_cck_rssi_table_from_reg( - IN OUT PDM_ODM_T pDM_Odm -) -{ - u8 used_lna_idx_tmp; - u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; /*example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ /*{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/ - u8 i; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("CCK LNA Gain table init\n")); - - if (!(pDM_Odm->SupportICType & (ODM_RTL8197F))) - return; - - reg_0xa80 = ODM_GetBBReg(pDM_Odm, 0xa80, 0xFFFF); - reg_0xabc = ODM_GetBBReg(pDM_Odm, 0xabc, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("reg_0xa80 = 0x%x\n", reg_0xa80)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("reg_0xabc = 0x%x\n", reg_0xabc)); - - for (i = 0; i<=3; i++) { - used_lna_idx_tmp = ((reg_0xa80 >> (4*i)) & 0x7); - pDM_Odm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)((reg_0xabc >> (8*i)) & 0xff); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n", - pDM_Odm->cck_lna_gain_table[0], - pDM_Odm->cck_lna_gain_table[1], - pDM_Odm->cck_lna_gain_table[2], - pDM_Odm->cck_lna_gain_table[3], - pDM_Odm->cck_lna_gain_table[4], - pDM_Odm->cck_lna_gain_table[5], - pDM_Odm->cck_lna_gain_table[6], - pDM_Odm->cck_lna_gain_table[7])); - -} - -VOID -odm_RxPhyStatus92CSeries_Parsing( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u1Byte i, Max_spatial_stream; - s1Byte rx_pwr[4], rx_pwr_all=0; - u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; - u1Byte RSSI, total_rssi=0; - BOOLEAN isCCKrate=FALSE; - u1Byte rf_rx_num = 0; - u1Byte cck_highpwr = 0; - u1Byte LNA_idx = 0; - u1Byte VGA_idx = 0; - u1Byte cck_agc_rpt; - u1Byte num_ss; - u8 stream_rxevm_tmp; - PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; - - isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M) ? TRUE : FALSE; - - if (pPktinfo->bToSelf) - pDM_Odm->curr_station_id = pPktinfo->StationID; - - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; - - - if(isCCKrate) - { - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; - cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; - - if (pDM_Odm->SupportICType & (ODM_RTL8703B)) { - - #if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->cck_agc_report_type == 1) { /*4 bit LNA*/ - - u1Byte cck_agc_rpt_b = (pPhyStaRpt->cck_rpt_b_ofdm_cfosho_b & BIT7) ? 1 : 0; - - LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); - } - #endif - } else { /*3 bit LNA*/ - - LNA_idx = ((cck_agc_rpt & 0xE0) >>5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (pDM_Odm->SupportICType & (ODM_RTL8188E)) { - - #if (RTL8188E_SUPPORT == 1) - rx_pwr_all = odm_CCKRSSI_8188E(pDM_Odm, LNA_idx, VGA_idx); - /**/ - #endif - } - #if (RTL8192E_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - - rx_pwr_all = odm_CCKRSSI_8192E(pDM_Odm, LNA_idx, VGA_idx); - /**/ - } - #endif - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { - - rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx,VGA_idx); - /**/ - } - #endif - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8188F)) { - - rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); - /**/ - } - #endif - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ExtLNAGain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", - pDM_Odm->ExtLNAGain, LNA_idx, VGA_idx, rx_pwr_all)); - - if (pDM_Odm->BoardType & ODM_BOARD_EXT_LNA) - rx_pwr_all -= pDM_Odm->ExtLNAGain; - - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - if (pPktinfo->bToSelf) { - pDM_Odm->cck_lna_idx = LNA_idx; - pDM_Odm->cck_vga_idx = VGA_idx; - } - pPhyInfo->RxPWDBAll = PWDB_ALL; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; - pPhyInfo->RecvSignalPower = rx_pwr_all; -#endif - // - // (3) Get Signal Quality (EVM) - // - //if(pPktinfo->bPacketMatchBSSID) - { - u1Byte SQ,SQ_rpt; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Lenovo)){ - SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); - }else if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Acer)) - { - SQ = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,0); - }else -#endif - if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ - SQ = 100; - } - else{ - SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; - - if(SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64-SQ_rpt) * 100) / 44; - - } - - //DbgPrint("cck SQ = %d\n", SQ); - pPhyInfo->SignalQuality = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - if (i == 0) - pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; - else - pPhyInfo->RxMIMOSignalStrength[1] = 0; - } - } - else //2 is OFDM rate - { - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; - - // - // (1)Get RSSI for HT rate - // - - for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) - { - // 2008/01/30 MH we will judge RF RX path now. - if (pDM_Odm->RFPathRxEnable & BIT(i)) - rf_rx_num++; - //else - //continue; - - rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; - - if (pPktinfo->bToSelf) { - pDM_Odm->ofdm_agc_idx[i] = (pPhyStaRpt->path_agc[i].gain & 0x3F); - /**/ - } - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[i] = rx_pwr[i]; - #endif - - /* Translate DBM to percentage. */ - RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); - total_rssi += RSSI; - //RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); - - pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; - - #if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) - //Get Rx snr value in DB - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); - #endif - - /* Record Signal Strength for next packet */ - //if(pPktinfo->bPacketMatchBSSID) - { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Lenovo)) - { - if(i==ODM_RF_PATH_A) - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); - - } - else if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Acer)) - { - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,RSSI); - } -#endif - } - } - - - // - // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) - // - rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; - - PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - - pPhyInfo->RxPWDBAll = PWDB_ALL; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; - pPhyInfo->RxPower = rx_pwr_all; - pPhyInfo->RecvSignalPower = rx_pwr_all; - #endif - - if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==19)){ - //do nothing - }else if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==25)){ - //do nothing - } - else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo - // - // (3)EVM of HT rate - // - if(pPktinfo->DataRate >=ODM_RATEMCS8 && pPktinfo->DataRate <=ODM_RATEMCS15) - Max_spatial_stream = 2; //both spatial stream make sense - else - Max_spatial_stream = 1; //only spatial stream 1 makes sense - - for(i=0; i>= 1" because the compilor of free build environment - // fill most significant bit to "zero" when doing shifting operation which may change a negative - // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. - EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm - - //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); - - //if(pPktinfo->bPacketMatchBSSID) - { - if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only - { - pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); - } - pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); - - if (pPhyStaRpt->stream_rxevm[i] < 0) { - - stream_rxevm_tmp = (u8 )(0 - (pPhyStaRpt->stream_rxevm[i])); - } - - if (stream_rxevm_tmp == 64) - stream_rxevm_tmp = 0; - - pPhyInfo->RxMIMOEVMdbm[i] = stream_rxevm_tmp; - } - } - } - - num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->path_cfotail, num_ss); - - } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - //UI BSS List signal strength(in percentage), make it good looking, from 0~100. - //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). - if(isCCKrate) - { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, TRUE, TRUE); -#else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - } - else - { - if (rf_rx_num != 0) - { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, (total_rssi /= rf_rx_num), TRUE, FALSE); - #else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num)); - #endif - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ - - //DbgPrint("isCCKrate = %d, pPhyInfo->RxPWDBAll = %d, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", - //isCCKrate, pPhyInfo->RxPWDBAll, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a); - - //For 92C/92D HW (Hybrid) Antenna Diversity -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - //For 88E HW Antenna Diversity - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; -#endif -} -#endif - -#if ODM_IC_11AC_SERIES_SUPPORT - -VOID -odm_RxPhyBWJaguarSeries_Parsing( - OUT PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo, - IN PPHY_STATUS_RPT_8812_T pPhyStaRpt -) -{ - - if(pPktinfo->DataRate <= ODM_RATE54M) { - switch (pPhyStaRpt->r_RFMOD) { - case 1: - if (pPhyStaRpt->sub_chnl == 0) - pPhyInfo->BandWidth = 1; - else - pPhyInfo->BandWidth = 0; - break; - - case 2: - if (pPhyStaRpt->sub_chnl == 0) - pPhyInfo->BandWidth = 2; - else if (pPhyStaRpt->sub_chnl == 9 || pPhyStaRpt->sub_chnl == 10) - pPhyInfo->BandWidth = 1; - else - pPhyInfo->BandWidth = 0; - break; - - default: - case 0: - pPhyInfo->BandWidth = 0; - break; - } - } - -} - -VOID -odm_RxPhyStatusJaguarSeries_Parsing( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo -) -{ - u1Byte i, Max_spatial_stream; - s1Byte rx_pwr[4], rx_pwr_all = 0; - u1Byte EVM, EVMdbm, PWDB_ALL = 0, PWDB_ALL_BT; - u1Byte RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; - u1Byte isCCKrate = 0; - u1Byte rf_rx_num = 0; - u1Byte cck_highpwr = 0; - u1Byte LNA_idx, VGA_idx; - PPHY_STATUS_RPT_8812_T pPhyStaRpt = (PPHY_STATUS_RPT_8812_T)pPhyStatus; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte num_ss; - - odm_RxPhyBWJaguarSeries_Parsing(pPhyInfo, pPktinfo, pPhyStaRpt); - - if (pPktinfo->DataRate <= ODM_RATE11M) - isCCKrate = TRUE; - else - isCCKrate = FALSE; - - if (pPktinfo->bToSelf) - pDM_Odm->curr_station_id = pPktinfo->StationID; - else - pDM_Odm->curr_station_id = 0xff; - - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_C] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_D] = -1; - - if (isCCKrate) { - u1Byte cck_agc_rpt; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; - - /*(1)Hardware does not provide RSSI for CCK*/ - /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*if(pHalData->eRFPowerState == eRfOn)*/ - cck_highpwr = pDM_Odm->bCckHighPower; - /*else*/ - /*cck_highpwr = FALSE;*/ - - cck_agc_rpt = pPhyStaRpt->cfosho[0] ; - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (pDM_Odm->SupportICType == ODM_RTL8812) { - switch (LNA_idx) { - case 7: - if (VGA_idx <= 27) - rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ - else - rx_pwr_all = -100; - break; - case 6: - rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ - break; - case 5: - rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ - break; - case 4: - rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ - break; - case 3: - /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ - rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ - break; - case 2: - if (cck_highpwr) - rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ - else - rx_pwr_all = -6 + 2 * (5 - VGA_idx); - break; - case 1: - rx_pwr_all = 8 - 2 * VGA_idx; - break; - case 0: - rx_pwr_all = 14 - 2 * VGA_idx; - break; - default: - /*DbgPrint("CCK Exception default\n");*/ - break; - } - rx_pwr_all += 6; - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - if (cck_highpwr == FALSE) { - if (PWDB_ALL >= 80) - PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; - else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) - PWDB_ALL += 3; - if (PWDB_ALL > 100) - PWDB_ALL = 100; - } - } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { - s1Byte Pout = -6; - - switch (LNA_idx) { - case 5: - rx_pwr_all = Pout - 32 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = Pout - 24 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = Pout - 11 - (2 * VGA_idx); - break; - case 1: - rx_pwr_all = Pout + 5 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = Pout + 21 - (2 * VGA_idx); - break; - } - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - } else if (pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8822B) { - s1Byte Pout = -6; - - switch (LNA_idx) { - /*CCK only use LNA: 2, 3, 5, 7*/ - case 7: - rx_pwr_all = Pout - 32 - (2 * VGA_idx); - break; - case 5: - rx_pwr_all = Pout - 22 - (2 * VGA_idx); - break; - case 3: - rx_pwr_all = Pout - 2 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = Pout + 5 - (2 * VGA_idx); - break; - /*case 6:*/ - /*rx_pwr_all = Pout -26 - (2*VGA_idx);*/ - /*break;*/ - /*case 4:*/ - /*rx_pwr_all = Pout - 8 - (2*VGA_idx);*/ - /*break;*/ - /*case 1:*/ - /*rx_pwr_all = Pout + 21 - (2*VGA_idx);*/ - /*break;*/ - /*case 0:*/ - /*rx_pwr_all = Pout + 10 - (2*VGA_idx);*/ -/* // break;*/ - default: -/* //DbgPrint("CCK Exception default\n");*/ - break; - } - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - } - - pDM_Odm->cck_lna_idx = LNA_idx; - pDM_Odm->cck_vga_idx = VGA_idx; - pPhyInfo->RxPWDBAll = PWDB_ALL; -/* //if(pPktinfo->StationID == 0)*/ -/* //{*/ -/* // DbgPrint("CCK: LNA_idx = %d, VGA_idx = %d, pPhyInfo->RxPWDBAll = %d\n",*/ -/* // LNA_idx, VGA_idx, pPhyInfo->RxPWDBAll);*/ -/* //}*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; - pPhyInfo->RecvSignalPower = rx_pwr_all; -#endif - /*(3) Get Signal Quality (EVM)*/ - /*if (pPktinfo->bPacketMatchBSSID)*/ - { - u1Byte SQ, SQ_rpt; - - if ((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { - SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, 0, 0); - } else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest) { - SQ = 100; - } else { - SQ_rpt = pPhyStaRpt->pwdb_all; - - if (SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64 - SQ_rpt) * 100) / 44; - } - -/* //DbgPrint("cck SQ = %d\n", SQ);*/ - pPhyInfo->SignalQuality = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (i == 0) - pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; - else - pPhyInfo->RxMIMOSignalStrength[i] = 0; - } - } else { - /*is OFDM rate*/ - pDM_FatTable->hw_antsw_occur = pPhyStaRpt->hw_antsw_occur; - - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; - - /*(1)Get RSSI for OFDM rate*/ - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - /*2008/01/30 MH we will judge RF RX path now.*/ -/* //DbgPrint("pDM_Odm->RFPathRxEnable = %x\n", pDM_Odm->RFPathRxEnable);*/ - if (pDM_Odm->RFPathRxEnable & BIT(i)) - rf_rx_num++; -/* //else*/ -/* //continue;*/ - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ -/* //if((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) && (!pDM_Odm->bIsMPChip))*/ - if (i < ODM_RF_PATH_C) - rx_pwr[i] = (pPhyStaRpt->gain_trsw[i] & 0x7F) - 110; - else - rx_pwr[i] = (pPhyStaRpt->gain_trsw_cd[i - 2] & 0x7F) - 110; -/* //else*/ - /*rx_pwr[i] = ((pPhyStaRpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[i] = rx_pwr[i]; -#endif - - /* Translate DBM to percentage. */ - RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); - - /*total_rssi += RSSI;*/ - /*Get the best two RSSI*/ - if (RSSI > best_rssi && RSSI > second_rssi) { - second_rssi = best_rssi; - best_rssi = RSSI; - } else if (RSSI > second_rssi && RSSI <= best_rssi) - second_rssi = RSSI; - - /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ - - pPhyInfo->RxMIMOSignalStrength[i] = (u1Byte) RSSI; - - - /*Get Rx snr value in DB*/ - if (i < ODM_RF_PATH_C) - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->rxsnr[i] / 2; - else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->csi_current[i - 2] / 2; - -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - /*(2) CFO_short & CFO_tail*/ - if (i < ODM_RF_PATH_C) { - pPhyInfo->Cfo_short[i] = odm_Cfo((pPhyStaRpt->cfosho[i])); - pPhyInfo->Cfo_tail[i] = odm_Cfo((pPhyStaRpt->cfotail[i])); - } -#endif - /* Record Signal Strength for next packet */ - if (pPktinfo->bPacketMatchBSSID) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { - if (i == ODM_RF_PATH_A) - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, i, RSSI); - - } -#endif - } - } - - /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - if ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!pDM_Odm->bIsMPChip)) - rx_pwr_all = (pPhyStaRpt->pwdb_all & 0x7f) - 110; - else - rx_pwr_all = (((pPhyStaRpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ - - PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - pPhyInfo->RxPWDBAll = PWDB_ALL; - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll));*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; - pPhyInfo->RxPower = rx_pwr_all; - pPhyInfo->RecvSignalPower = rx_pwr_all; -#endif - - if ((pDM_Odm->SupportPlatform == ODM_WIN) && (pDM_Odm->PatchID == 19)) { - /*do nothing*/ - } else { - /*pMgntInfo->CustomerID != RT_CID_819x_Lenovo*/ - - /*(4)EVM of OFDM rate*/ - - if ((pPktinfo->DataRate >= ODM_RATEMCS8) && - (pPktinfo->DataRate <= ODM_RATEMCS15)) - Max_spatial_stream = 2; - else if ((pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0) && - (pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) - Max_spatial_stream = 2; - else if ((pPktinfo->DataRate >= ODM_RATEMCS16) && - (pPktinfo->DataRate <= ODM_RATEMCS23)) - Max_spatial_stream = 3; - else if ((pPktinfo->DataRate >= ODM_RATEVHTSS3MCS0) && - (pPktinfo->DataRate <= ODM_RATEVHTSS3MCS9)) - Max_spatial_stream = 3; - else - Max_spatial_stream = 1; - - /*if (pPktinfo->bPacketMatchBSSID) */ - { - /*DbgPrint("pPktinfo->DataRate = %d\n", pPktinfo->DataRate);*/ - - for (i = 0; i < Max_spatial_stream; i++) { - /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ - /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ - /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ - - if (pPktinfo->DataRate >= ODM_RATE6M && pPktinfo->DataRate <= ODM_RATE54M) { - if (i == ODM_RF_PATH_A) { - EVM = odm_EVMdbToPercentage((pPhyStaRpt->sigevm)); /*dbm*/ - EVM += 20; - if (EVM > 100) - EVM = 100; - } - } else { - if (i < ODM_RF_PATH_C) { - if (pPhyStaRpt->rxevm[i] == -128) - pPhyStaRpt->rxevm[i] = -25; - EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm[i])); /*dbm*/ - } else { - if (pPhyStaRpt->rxevm_cd[i - 2] == -128){ - pPhyStaRpt->rxevm_cd[i - 2] = -25; - } - EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm_cd[i - 2])); /*dbm*/ - } - } - - if (i < ODM_RF_PATH_C) - EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm[i]); - else - EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm_cd[i - 2]); - /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ - /*pPktinfo->DataRate, pPhyStaRpt->rxevm[i], "%", EVM));*/ - - { - if (i == ODM_RF_PATH_A) { - /*Fill value in RFD, Get the first spatial stream only*/ - pPhyInfo->SignalQuality = EVM; - } - pPhyInfo->RxMIMOSignalQuality[i] = EVM; -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - pPhyInfo->RxMIMOEVMdbm[i] = EVMdbm; -#endif - } - } - } - } - - num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfotail, num_ss); - - } -/* //DbgPrint("isCCKrate= %d, pPhyInfo->SignalStrength=%d % PWDB_AL=%d rf_rx_num=%d\n", isCCKrate, pPhyInfo->SignalStrength, PWDB_ALL, rf_rx_num);*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ - /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ - if (isCCKrate) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, FALSE, TRUE); -#else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif - } else { - if (rf_rx_num != 0) { - /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ - if (rf_rx_num == 1) - avg_rssi = best_rssi; - else - avg_rssi = (best_rssi + second_rssi)/2; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, avg_rssi, FALSE, FALSE); -#else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, avg_rssi)); -#endif - } - } -#endif - pDM_Odm->RxPWDBAve = pDM_Odm->RxPWDBAve + pPhyInfo->RxPWDBAll; - - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_anta; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_antb; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_antc; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_antd; - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", pPktinfo->StationID, pPhyStaRpt->antidx_anta, pPktinfo->bPacketMatchBSSID));*/ - - -/* DbgPrint("pPhyStaRpt->antidx_anta = %d, pPhyStaRpt->antidx_antb = %d\n",*/ -/* pPhyStaRpt->antidx_anta, pPhyStaRpt->antidx_antb);*/ -/* DbgPrint("----------------------------\n");*/ -/* DbgPrint("pPktinfo->StationID=%d, pPktinfo->DataRate=0x%x\n",pPktinfo->StationID, pPktinfo->DataRate);*/ -/* DbgPrint("pPhyStaRpt->r_RFMOD = %d\n", pPhyStaRpt->r_RFMOD);*/ -/* DbgPrint("pPhyStaRpt->gain_trsw[0]=0x%x, pPhyStaRpt->gain_trsw[1]=0x%x\n",*/ -/* pPhyStaRpt->gain_trsw[0],pPhyStaRpt->gain_trsw[1]);*/ -/* DbgPrint("pPhyStaRpt->gain_trsw[2]=0x%x, pPhyStaRpt->gain_trsw[3]=0x%x\n",*/ -/* pPhyStaRpt->gain_trsw_cd[0],pPhyStaRpt->gain_trsw_cd[1]);*/ -/* DbgPrint("pPhyStaRpt->pwdb_all = 0x%x, pPhyInfo->RxPWDBAll = %d\n", pPhyStaRpt->pwdb_all, pPhyInfo->RxPWDBAll);*/ -/* DbgPrint("pPhyStaRpt->cfotail[i] = 0x%x, pPhyStaRpt->CFO_tail[i] = 0x%x\n", pPhyStaRpt->cfotail[0], pPhyStaRpt->cfotail[1]);*/ -/* DbgPrint("pPhyStaRpt->rxevm[0] = %d, pPhyStaRpt->rxevm[1] = %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1]);*/ -/* DbgPrint("pPhyStaRpt->rxevm[2] = %d, pPhyStaRpt->rxevm[3] = %d\n", pPhyStaRpt->rxevm_cd[0], pPhyStaRpt->rxevm_cd[1]);*/ -/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[0]=%d, pPhyInfo->RxMIMOSignalStrength[1]=%d, RxPWDBAll=%d\n",*/ -/* pPhyInfo->RxMIMOSignalStrength[0], pPhyInfo->RxMIMOSignalStrength[1], pPhyInfo->RxPWDBAll);*/ -/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[2]=%d, pPhyInfo->RxMIMOSignalStrength[3]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalStrength[2], pPhyInfo->RxMIMOSignalStrength[3]);*/ -/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[0]=%d, pPhyInfo->RxMIMOSignalQuality[1]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalQuality[0], pPhyInfo->RxMIMOSignalQuality[1]);*/ -/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[2]=%d, pPhyInfo->RxMIMOSignalQuality[3]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalQuality[2], pPhyInfo->RxMIMOSignalQuality[3]);*/ - -} - -#endif - -VOID -phydm_reset_rssi_for_dm( - IN OUT PDM_ODM_T pDM_Odm, - IN u1Byte station_id - ) -{ - PSTA_INFO_T pEntry; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif - - pEntry = pDM_Odm->pODM_StaInfo[station_id]; - - if (!IS_STA_VALID(pEntry)) { - /**/ - return; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); - - - pEntry->rssi_stat.UndecoratedSmoothedCCK = -1; - pEntry->rssi_stat.UndecoratedSmoothedOFDM = -1; - pEntry->rssi_stat.UndecoratedSmoothedPWDB = -1; - pEntry->rssi_stat.OFDM_pkt = 0; - pEntry->rssi_stat.CCK_pkt = 0; - pEntry->rssi_stat.CCK_sum_power = 0; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_INIT; - pEntry->rssi_stat.PacketMap = 0; - pEntry->rssi_stat.ValidBit = 0; - - /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - pEntry->bUsed = 0; - if (station_id == 0) { - - pHalData->UndecoratedSmoothedPWDB = -1; - /**/ - } - #endif - -} - -VOID -odm_Init_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm - ) -{ - -} - -VOID -odm_Process_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - - s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave, CCK_pkt; - u1Byte i, isCCKrate=0; - u1Byte RSSI_max, RSSI_min; - u4Byte Weighting=0; - u1Byte send_rssi_2_fw = 0; - PSTA_INFO_T pEntry; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif - - if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) - return; - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(pDM_Odm, pPhyInfo, pPktinfo); - #endif - - // - // 2012/05/30 MH/Luke.Lee Add some description - // In windows driver: AP/IBSS mode STA - // - //if (pDM_Odm->SupportPlatform == ODM_WIN) - //{ - // pEntry = pDM_Odm->pODM_StaInfo[pDM_Odm->pAidMap[pPktinfo->StationID-1]]; - //} - //else - pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; - - if (!IS_STA_VALID(pEntry)) { - return; - /**/ - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && - (pDM_FatTable->enable_ctrl_frame_antdiv) - ) - { - if (pPktinfo->bPacketMatchBSSID) - pDM_Odm->data_frame_num++; - - if ((pDM_FatTable->use_ctrl_frame_antdiv)) { - if (!pPktinfo->bToSelf)/*data frame + CTRL frame*/ - return; - } else { - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ - return; - } - } else -#endif - { - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ - return; - } - - if(pPktinfo->bPacketBeacon) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; - - isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M )?TRUE :FALSE; - pDM_Odm->RxRate = pPktinfo->DataRate; - - if ((pPktinfo->DataRate >= ODM_RATEMCS8 && pPktinfo->DataRate <= ODM_RATEMCS15) || - (pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0 && pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) { - - pDM_Odm->rate_ss = 2; - } else { - - pDM_Odm->rate_ss = 1; - } - - //--------------Statistic for antenna/path diversity------------------ - if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) - { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_Process_RSSIForAntDiv(pDM_Odm,pPhyInfo,pPktinfo); - #endif - } - #if(defined(CONFIG_PATH_DIVERSITY)) - else if(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV) - { - phydm_process_rssi_for_path_div(pDM_Odm,pPhyInfo,pPktinfo); - } - #endif - //-----------------Smart Antenna Debug Message------------------// - - UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; - UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; - UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - - if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) - { - - if(!isCCKrate)//ofdm rate - { -#if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) { - u1Byte RX_count = 0; - u4Byte RSSI_linear = 0; - - if (pDM_Odm->RXAntStatus & ODM_RF_A) { - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); - } else - pDM_Odm->RSSI_A = 0; - - if (pDM_Odm->RXAntStatus & ODM_RF_B) { - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]); - } else - pDM_Odm->RSSI_B = 0; - - if (pDM_Odm->RXAntStatus & ODM_RF_C) { - pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; - RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]); - } else - pDM_Odm->RSSI_C = 0; - - if (pDM_Odm->RXAntStatus & ODM_RF_D) { - pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; - RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]); - } else - pDM_Odm->RSSI_D = 0; - - /* Calculate average RSSI */ - switch (RX_count) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); - } else -#endif - { - if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) { - RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = 0; - } else { - /*DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n",*/ - /*pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);*/ - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - - if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) { - RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - } else { - RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - } - if ((RSSI_max - RSSI_min) < 3) - RSSI_Ave = RSSI_max; - else if ((RSSI_max - RSSI_min) < 6) - RSSI_Ave = RSSI_max - 1; - else if ((RSSI_max - RSSI_min) < 10) - RSSI_Ave = RSSI_max - 2; - else - RSSI_Ave = RSSI_max - 3; - } - } - - //1 Process OFDM RSSI - if(UndecoratedSmoothedOFDM <= 0) // initialize - { - UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", UndecoratedSmoothedOFDM)); - } - else - { - if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) - { - UndecoratedSmoothedOFDM = - ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + - (RSSI_Ave)) /(Rx_Smooth_Factor); - UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", UndecoratedSmoothedOFDM)); - } - else - { - UndecoratedSmoothedOFDM = - ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + - (RSSI_Ave)) /(Rx_Smooth_Factor); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", UndecoratedSmoothedOFDM)); - } - } - if (pEntry->rssi_stat.OFDM_pkt != 64) { - i = 63; - pEntry->rssi_stat.OFDM_pkt -= (u1Byte)(((pEntry->rssi_stat.PacketMap>>i)&BIT0)-1); - } - pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; - - } - else - { - RSSI_Ave = pPhyInfo->RxPWDBAll; - pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll; - pDM_Odm->RSSI_B = 0xFF; - pDM_Odm->RSSI_C = 0xFF; - pDM_Odm->RSSI_D = 0xFF; - - if (pEntry->rssi_stat.CCK_pkt <= 63) - pEntry->rssi_stat.CCK_pkt++; - - //1 Process CCK RSSI - if(UndecoratedSmoothedCCK <= 0) // initialize - { - UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; - pEntry->rssi_stat.CCK_sum_power = (u2Byte)pPhyInfo->RxPWDBAll ; /*reset*/ - pEntry->rssi_stat.CCK_pkt = 1; /*reset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", UndecoratedSmoothedCCK)); - } else if (pEntry->rssi_stat.CCK_pkt <= CCK_RSSI_INIT_COUNT) { - - pEntry->rssi_stat.CCK_sum_power = pEntry->rssi_stat.CCK_sum_power + (u2Byte)pPhyInfo->RxPWDBAll; - UndecoratedSmoothedCCK = pEntry->rssi_stat.CCK_sum_power/pEntry->rssi_stat.CCK_pkt; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), CCK_pkt = (( %d ))\n", - UndecoratedSmoothedCCK, pEntry->rssi_stat.CCK_sum_power, pEntry->rssi_stat.CCK_pkt)); - } - else - { - if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) - { - UndecoratedSmoothedCCK = - ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + - (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); - UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", UndecoratedSmoothedCCK)); - } - else - { - UndecoratedSmoothedCCK = - ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + - (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", UndecoratedSmoothedCCK)); - } - } - i = 63; - pEntry->rssi_stat.OFDM_pkt -= (u1Byte)((pEntry->rssi_stat.PacketMap>>i)&BIT0); - pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; - } - - //if(pEntry) - { - //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI - if (pEntry->rssi_stat.OFDM_pkt == 64) { /* speed up when all packets are OFDM*/ - UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK)); - } else { - if (pEntry->rssi_stat.ValidBit < 64) - pEntry->rssi_stat.ValidBit++; - - if (pEntry->rssi_stat.ValidBit == 64) { - Weighting = ((pEntry->rssi_stat.OFDM_pkt) > 4) ? 64 : (pEntry->rssi_stat.OFDM_pkt<<4); - UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, Weighting)); - } else { - if (pEntry->rssi_stat.ValidBit != 0) - UndecoratedSmoothedPWDB = (pEntry->rssi_stat.OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-pEntry->rssi_stat.OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; - else - UndecoratedSmoothedPWDB = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), OFDM_pkt = (( %d )), Valid_Bit = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.ValidBit)); - } - } - - - if ((pEntry->rssi_stat.OFDM_pkt >= 1 || pEntry->rssi_stat.CCK_pkt >= 5) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_INIT)) { - - send_rssi_2_fw = 1; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_SEND; - } - - pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; - pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - - - - if (send_rssi_2_fw) /* Trigger init rate by RSSI */ { - - if (pEntry->rssi_stat.OFDM_pkt != 0) - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), OFDM_pkt = (( %d )), CCK_pkt = (( %d ))\n", - UndecoratedSmoothedPWDB, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.CCK_pkt)); - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - phydm_ra_rssi_rpt_wk(pDM_Odm); - #endif - } - - - /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - if (pPktinfo->StationID == 0) { - /**/ - pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - } - #endif - - //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); - //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", - // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); - - } - - } -} - - -#if(ODM_IC_11N_SERIES_SUPPORT ==1) -// -// Endianness before calling this API -// -VOID -ODM_PhyStatusQuery_92CSeries( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); - odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); -} -#endif - - -// -// Endianness before calling this API -// -#if ODM_IC_11AC_SERIES_SUPPORT - -VOID -ODM_PhyStatusQuery_JaguarSeries( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - odm_RxPhyStatusJaguarSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); - odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*phydm_sbd_check(pDM_Odm);*/ - #endif -} -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -phydm_normal_driver_rx_sniffer( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN PRT_RFD_STATUS pRtRfdStatus, - IN pu1Byte pDrvInfo, - IN u1Byte PHYStatus - ) -{ - #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) - u4Byte *pMsg; - u2Byte seq_num; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if (pRtRfdStatus->PacketReportType != NORMAL_RX) - return; - - if (!pDM_Odm->bLinked) { - if (pRtRfdStatus->bHwError) - return; - } - - if (!(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) - return; - - if (PHYStatus == TRUE) { - - if ((pDM_Odm->rx_pkt_type == Type_BlockAck) || (pDM_Odm->rx_pkt_type == Type_RTS) || (pDM_Odm->rx_pkt_type == Type_CTS)) - seq_num = 0; - else - seq_num = pRtRfdStatus->Seq_Num; - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s", - seq_num, - /*pRtRfdStatus->MacID,*/ - ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), - pRtRfdStatus->DataRate, - pRtRfdStatus->Length, - ((pRtRfdStatus->BandWidth == 0) ? "20M":((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), - ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") - )); - - if (pDM_Odm->rx_pkt_type == Type_Asoc_Req) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Asoc_Rsp) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Probe_Req) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Probe_Rsp) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Deauth) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Beacon) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_BlockAckReq) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_RTS) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_CTS) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Ack) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_BlockAck) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Data) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Data_Ack) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); - /**/ - } else if (pDM_Odm->rx_pkt_type == Type_QosData) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); - /**/ - } else { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", pDM_Odm->rx_pkt_type)); - /**/ - } - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", - pDM_Odm->RSSI_A, - pDM_Odm->RSSI_B, - pDM_Odm->RSSI_C, - pDM_Odm->RSSI_D - )); - - pMsg = (pu4Byte)pDrvInfo; - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", - pMsg[6], pMsg[5], pMsg[4], pMsg[3], pMsg[2], pMsg[1], pMsg[1])); - } else { - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s\n", - pRtRfdStatus->Seq_Num, - /*pRtRfdStatus->MacID,*/ - ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), - pRtRfdStatus->DataRate, - pRtRfdStatus->Length, - ((pRtRfdStatus->BandWidth == 0) ? "20M" : ((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), - ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") - )); - } - - - #endif -} -#endif - -VOID -ODM_PhyStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) { - phydm_RxPhyStatusNewType(pDM_Odm, pPhyStatus, pPktinfo, pPhyInfo); - return; - } -#endif - -#if ODM_IC_11AC_SERIES_SUPPORT - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_PhyStatusQuery_JaguarSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); -#endif - -#if ODM_IC_11N_SERIES_SUPPORT - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES ) - ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); -#endif -} - -// For future use. -VOID -ODM_MacStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pMacStatus, - IN u1Byte MacID, - IN BOOLEAN bPacketMatchBSSID, - IN BOOLEAN bPacketToSelf, - IN BOOLEAN bPacketBeacon - ) -{ - // 2011/10/19 Driver team will handle in the future. - -} - - -// -// If you want to add a new IC, Please follow below template and generate a new one. -// -// - -HAL_STATUS -ODM_ConfigRFWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_Config_Type ConfigType, - IN ODM_RF_RADIO_PATH_E eRFPath - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigRFWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); - -//1 AP doesn't use PHYDM power tracking table in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A){ - READ_AND_CONFIG_MP(8812A,_RadioA); - } - else if(eRFPath == ODM_RF_PATH_B){ - READ_AND_CONFIG_MP(8812A,_RadioB); - } - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - if ((pHalData->EEPROMSVID == 0x17AA && pHalData->EEPROMSMID == 0xA811) || - (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0xA812) || - (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0x8812)) - READ_AND_CONFIG_MP(8812A,_TXPWR_LMT_HM812A03); - else - #endif - READ_AND_CONFIG_MP(8812A,_TXPWR_LMT); - } - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A){ - READ_AND_CONFIG_MP(8821A,_RadioA); - } - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (pDM_Odm->ExtPA5G || pDM_Odm->ExtLNA5G) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_FEM); - else - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_IPA); - } - else { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pMgntInfo->CustomerID == RT_CID_8821AE_ASUS_MB) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_8mm); - else if (pMgntInfo->CustomerID == RT_CID_ASUS_NB) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_5mm); - else - #endif - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); - } -#endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8192E,_RadioA); - else if(eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8192E,_RadioB); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if ((pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8192) || - (pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8193)) - READ_AND_CONFIG_MP(8192E, _TXPWR_LMT_8192E_SAR_5mm); - else -#endif - READ_AND_CONFIG_MP(8192E, _TXPWR_LMT); - } - } -#endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8723D, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8723D, _TXPWR_LMT); - } -#endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - -//1 All platforms support -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8188E,_RadioA); - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8188E,_TXPWR_LMT); - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (ConfigType == CONFIG_RF_RADIO) - READ_AND_CONFIG_MP(8723B, _RadioA); - else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8723B, _TXPWR_LMT); - } -#endif -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8814A,_RadioA); - else if(eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8814A,_RadioB); - else if(eRFPath == ODM_RF_PATH_C) - READ_AND_CONFIG_MP(8814A,_RadioC); - else if(eRFPath == ODM_RF_PATH_D) - READ_AND_CONFIG_MP(8814A,_RadioD); - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8814A,_TXPWR_LMT); - } -#endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8703B, _RadioA); - } - } -#endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8188F, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8188F, _TXPWR_LMT); - } -#endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8822B, _RadioA); - else if (eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8822B, _RadioB); - } - } -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8197F, _RadioA); - else if (eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8197F, _RadioB); - } - } -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_TC(8821C, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_TC(8821C, _TXPWR_LMT); - } -#endif - - return HAL_STATUS_SUCCESS; -} - -HAL_STATUS -ODM_ConfigRFWithTxPwrTrackHeaderFile( - IN PDM_ODM_T pDM_Odm - ) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigRFWithTxPwrTrackHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); - - -//1 AP doesn't use PHYDM power tracking table in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if RTL8821A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8821) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_SDIO); - } -#endif -#if RTL8812A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8812) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_RFE3); - else - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_USB); - } - - } -#endif -#if RTL8192E_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_SDIO); - } -#endif -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_SDIO); - - READ_AND_CONFIG_MP(8723D, _TxXtalTrack); - } -#endif -#if RTL8188E_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - if (PHY_QueryMacReg(pDM_Odm->Adapter, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE_ICUT); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB_ICUT); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO_ICUT); - } else { /*else 0xF0[15:12] < 8, TSMC*/ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO); - } - - } -#endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - -//1 All platforms support -#if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_SDIO); - } -#endif -#if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type0); - else if(pDM_Odm->RFEType == 1) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type1); - else if(pDM_Odm->RFEType == 2) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type2); - else if(pDM_Odm->RFEType == 3) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type3); - else if(pDM_Odm->RFEType == 4) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type4); - else if(pDM_Odm->RFEType == 5) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type5); - else if(pDM_Odm->RFEType == 6) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type6); - else if(pDM_Odm->RFEType == 7) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type7); - else if(pDM_Odm->RFEType == 8) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type8); - else if(pDM_Odm->RFEType == 9) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type9); - else - READ_AND_CONFIG_MP(8814A,_TxPowerTrack); - - READ_AND_CONFIG_MP(8814A, _TxPowerTSSI); - } -#endif -#if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8703B, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8703B, _TxPowerTrack_SDIO); - - READ_AND_CONFIG_MP(8703B, _TxXtalTrack); - } -#endif - -#if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188F, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188F, _TxPowerTrack_SDIO); - } -#endif - -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type0); - else if (pDM_Odm->RFEType == 1) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type1); - else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_Type3_Type5); - else if (pDM_Odm->RFEType == 6) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type6); - else if (pDM_Odm->RFEType == 7) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type7); - else if (pDM_Odm->RFEType == 8) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type8); - else if (pDM_Odm->RFEType == 9) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type9); - else if (pDM_Odm->RFEType == 10) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type10); - else if (pDM_Odm->RFEType == 11) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type11); - else if (pDM_Odm->RFEType == 12) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type12); - else if (pDM_Odm->RFEType == 13) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type13); - else if (pDM_Odm->RFEType == 14) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type14); - else - READ_AND_CONFIG_MP(8822B, _TxPowerTrack); - } -#endif - -#if RTL8197F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type0); - else if (pDM_Odm->RFEType == 1) - READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type1); - else - READ_AND_CONFIG_MP(8197F, _TxPowerTrack); - } -#endif - -#if RTL8821C_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821C) - READ_AND_CONFIG_TC(8821C, _TxPowerTrack); -#endif - - return HAL_STATUS_SUCCESS; -} - -HAL_STATUS -ODM_ConfigBBWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_BB_Config_Type ConfigType - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); -#endif - -//1 AP doesn't use PHYDM initialization in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8812A_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8812A, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8812A, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_ASUS); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - else if (pMgntInfo->CustomerID == RT_CID_WNC_NEC && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_NEC); - #if RT_PLATFORM == PLATFORM_MACOSX - /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ - else if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_DNI); - /* TP-Link T4UH, Isaiah 2015-03-16*/ - else if (pMgntInfo->CustomerID == RT_CID_TPLINK_HPWR) { - DbgPrint("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_TPLINK); - } - #endif - #endif - else - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG); - } - else if(ConfigType == CONFIG_BB_PHY_REG_MP){ - READ_AND_CONFIG_MP(8812A,_PHY_REG_MP); - } - else if(ConfigType == CONFIG_BB_AGC_TAB_DIFF) - { - if ((36 <= *pDM_Odm->pChannel) && (*pDM_Odm->pChannel <= 64)) - AGC_DIFF_CONFIG_MP(8812A,LB); - else if (100 <= *pDM_Odm->pChannel) - AGC_DIFF_CONFIG_MP(8812A,HB); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n")); - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8821A, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8821A, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if ((pHalData->EEPROMSVID == 0x1043 && pHalData->EEPROMSMID == 0x207F)) - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_E202SA); - else - #endif - #if (RT_PLATFORM == PLATFORM_MACOSX) - /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ - if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) { - /*{1024} for BUFFALO power by rate table. (JP/US)*/ - if (pMgntInfo->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_US); - else - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_JP); - } else - #endif - #endif - READ_AND_CONFIG_MP(8821A,_PHY_REG_PG); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n")); - } -#endif -#if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(ConfigType == CONFIG_BB_PHY_REG){ - READ_AND_CONFIG_MP(8192E,_PHY_REG); - }else if(ConfigType == CONFIG_BB_AGC_TAB){ - READ_AND_CONFIG_MP(8192E,_AGC_TAB); - }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ - READ_AND_CONFIG_MP(8192E,_PHY_REG_PG); - } - } -#endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8723D, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8723D, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8723D, _PHY_REG_PG); - } -#endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - - -//1 All platforms support -#if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - if(ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8188E,_PHY_REG); - else if(ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8188E,_AGC_TAB); - else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8188E,_PHY_REG_PG); - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8723B, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8723B, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - READ_AND_CONFIG_MP(8723B, _PHY_REG_PG); - } - } -#endif -#if (RTL8814A_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(ConfigType == CONFIG_BB_PHY_REG){ - READ_AND_CONFIG_MP(8814A,_PHY_REG); - }else if(ConfigType == CONFIG_BB_AGC_TAB){ - READ_AND_CONFIG_MP(8814A,_AGC_TAB); - }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ - READ_AND_CONFIG_MP(8814A,_PHY_REG_PG); - }else if(ConfigType == CONFIG_BB_PHY_REG_MP){ - READ_AND_CONFIG_MP(8814A,_PHY_REG_MP); - } - } -#endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8703B, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8703B, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8703B, _PHY_REG_PG); - } -#endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8188F, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8188F, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8188F, _PHY_REG_PG); - } -#endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8822B, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8822B, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8822B, _PHY_REG_PG); - /*else if (ConfigType == CONFIG_BB_PHY_REG_MP)*/ - /*READ_AND_CONFIG_MP(8822B, _PHY_REG_MP);*/ - } -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8197F, _PHY_REG); - if (pDM_Odm->CutVersion == ODM_CUT_A) - phydm_phypara_a_cut(pDM_Odm); - } else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8197F, _AGC_TAB); -/* else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8197F, _PHY_REG_PG); - else if(ConfigType == CONFIG_BB_PHY_REG_MP) - READ_AND_CONFIG_MP(8197F, _PHY_REG_MP); */ - } -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_TC(8821C, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_TC(8821C, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - READ_AND_CONFIG_TC(8821C, _PHY_REG_PG); - } - } -#endif - -#if (RTL8195A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8195A) - { - if(ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG(8195A, _PHY_REG); - else if(ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG(8195A, _AGC_TAB); - else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG(8195A, _PHY_REG_PG); - } -#endif - - return HAL_STATUS_SUCCESS; -} - -HAL_STATUS -ODM_ConfigMACWithHeaderFile( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigMACWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); - -//1 AP doesn't use PHYDM initialization in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812){ - READ_AND_CONFIG_MP(8812A, _MAC_REG); - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821){ - READ_AND_CONFIG_MP(8821A, _MAC_REG); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n")); - } -#endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E){ - READ_AND_CONFIG_MP(8192E, _MAC_REG); - } -#endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) - READ_AND_CONFIG_MP(8723D, _MAC_REG); -#endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - -//1 All platforms support -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E){ - READ_AND_CONFIG_MP(8188E, _MAC_REG); - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - READ_AND_CONFIG_MP(8723B, _MAC_REG); - } -#endif -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A){ - READ_AND_CONFIG_MP(8814A, _MAC_REG); - } -#endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) - READ_AND_CONFIG_MP(8703B, _MAC_REG); -#endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) - READ_AND_CONFIG_MP(8188F, _MAC_REG); -#endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - READ_AND_CONFIG_MP(8822B, _MAC_REG); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) - READ_AND_CONFIG_MP(8197F, _MAC_REG); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - READ_AND_CONFIG_TC(8821C, _MAC_REG); -#endif - -#if (RTL8195A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8195A) - READ_AND_CONFIG_MP(8195A, _MAC_REG); -#endif - - return HAL_STATUS_SUCCESS; -} - -HAL_STATUS -ODM_ConfigFWWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_FW_Config_Type ConfigType, - OUT u1Byte *pFirmware, - OUT u4Byte *pSize - ) -{ -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - #ifdef CONFIG_SFW_SUPPORTED - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188E_T,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); - else if(ConfigType == CONFIG_FW_NIC_2) - READ_FIRMWARE_MP(8188E_S,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN_2) - READ_FIRMWARE_MP(8188E_S,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188E_T,_FW_AP); - else if (ConfigType == CONFIG_FW_AP_2) - READ_FIRMWARE_MP(8188E_S,_FW_AP); - #endif //CONFIG_AP_WOWLAN - #else - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188E_T,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188E_T,_FW_AP); - #endif //CONFIG_AP_WOWLAN - #endif - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723B,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8723B,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8723B,_FW_AP_WoWLAN); - #endif - - } -#endif //#if (RTL8723B_SUPPORT == 1) -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8812A,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8812A,_FW_WoWLAN); - else if (ConfigType == CONFIG_FW_BT) - READ_FIRMWARE_MP(8812A,_FW_NIC_BT); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8812A,_FW_AP); - #endif - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821){ - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821A,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8821A,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8821A , _FW_AP); - #endif /*CONFIG_AP_WOWLAN*/ - else if (ConfigType == CONFIG_FW_BT) - READ_FIRMWARE_MP(8821A,_FW_NIC_BT); - } -#endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8192E,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8192E,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8192E,_FW_AP); - #endif - } -#endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_FW_NIC) { - READ_FIRMWARE_MP(8723D, _FW_NIC); - } else if (ConfigType == CONFIG_FW_WoWLAN) { - READ_FIRMWARE_MP(8723D, _FW_WoWLAN); - } - } -#endif -/*#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814A, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8814A, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8814A, _FW_AP); - #endif - } -#endif */ - -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814A,_FW_NIC); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8814A,_FW_AP); - #endif - } -#endif - -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8703B, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8703B, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8703B, _FW_AP_WoWLAN); - #endif - } -#endif - -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188F, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188F, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188F, _FW_AP); - #endif - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8822B,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8822B, _FW_WOWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8822B,_FW_AP); - #endif - } -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8197F, _FW_NIC); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8197F , _FW_AP); - #endif - } -#endif - -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - return HAL_STATUS_SUCCESS; -} - -u4Byte -ODM_GetHWImgVersion( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte Version=0; - -//1 AP doesn't use PHYDM initialization in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - Version = GET_VERSION_MP(8821A,_MAC_REG); -#endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - Version = GET_VERSION_MP(8192E,_MAC_REG); -#endif -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - Version = GET_VERSION_MP(8812A,_MAC_REG); -#endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) - Version = GET_VERSION_MP(8723D, _MAC_REG); -#endif -#endif //(DM_ODM_SUPPORT_TYPE != ODM_AP) - -/*1 All platforms support*/ -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - Version = GET_VERSION_MP(8188E,_MAC_REG); -#endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) - Version = GET_VERSION_MP(8723B, _MAC_REG); -#endif -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - Version = GET_VERSION_MP(8814A,_MAC_REG); -#endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) - Version = GET_VERSION_MP(8703B, _MAC_REG); -#endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) - Version = GET_VERSION_MP(8188F, _MAC_REG); -#endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - Version = GET_VERSION_MP(8822B, _MAC_REG); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) - Version = GET_VERSION_MP(8197F, _MAC_REG); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - Version = GET_VERSION_TC(8821C, _MAC_REG); -#endif - - return Version; -} - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/* For 8822B only!! need to move to FW finally */ -/*==============================================*/ - -VOID -phydm_ResetPhyInfo( - IN PDM_ODM_T pPhydm, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - pPhyInfo->RxPWDBAll = 0; - pPhyInfo->SignalQuality = 0; - pPhyInfo->BandWidth = 0; - pPhyInfo->RxCount = 0; - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalQuality, 0 , 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalStrength, 0, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxSNR, 0, 4); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPower = -110; - pPhyInfo->RecvSignalPower = -110; - pPhyInfo->BTRxRSSIPercentage = 0; - pPhyInfo->SignalStrength = 0; - pPhyInfo->btCoexPwrAdjust = 0; - pPhyInfo->channel = 0; - pPhyInfo->bMuPacket = 0; - pPhyInfo->bBeamformed = 0; - pPhyInfo->rxsc = 0; - ODM_Memory_Set(pPhydm, pPhyInfo->RxPwr, -110, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOEVMdbm, 0, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_short, 0, 8); - ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_tail, 0, 8); -#endif -} - -VOID -phydm_SetPerPathPhyInfo( - IN u1Byte RxPath, - IN s1Byte RxPwr, - IN s1Byte RxEVM, - IN s1Byte Cfo_tail, - IN s1Byte RxSNR, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - u1Byte EVMdBm = 0; - u1Byte EVMPercentage = 0; - - /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ - - if (RxEVM < 0) { - /* Calculate EVM in dBm */ - EVMdBm = ((u1Byte)(0 - RxEVM) >> 1); - - /* Calculate EVM in percentage */ - if (EVMdBm >= 33) - EVMPercentage = 100; - else - EVMPercentage = (EVMdBm << 1) + (EVMdBm); - } - - if (EVMdBm == 64) - EVMdBm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[RxPath] = RxPwr; - pPhyInfo->RxMIMOEVMdbm[RxPath] = EVMdBm; - - /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ - pPhyInfo->Cfo_tail[RxPath] = Cfo_tail; - pPhyInfo->Cfo_tail[RxPath] = ((pPhyInfo->Cfo_tail[RxPath] << 5) + (pPhyInfo->Cfo_tail[RxPath] << 2) + - (pPhyInfo->Cfo_tail[RxPath] << 1) + (pPhyInfo->Cfo_tail[RxPath])) >> 9; -#endif - - pPhyInfo->RxMIMOSignalStrength[RxPath] = odm_QueryRxPwrPercentage(RxPwr); - pPhyInfo->RxMIMOSignalQuality[RxPath] = EVMPercentage; - pPhyInfo->RxSNR[RxPath] = RxSNR >> 1; - -/* - //if (pPktinfo->bPacketMatchBSSID) - { - DbgPrint("Path (%d)--------\n", RxPath); - DbgPrint("RxPwr = %d, Signal strength = %d\n", pPhyInfo->RxPwr[RxPath], pPhyInfo->RxMIMOSignalStrength[RxPath]); - DbgPrint("EVMdBm = %d, Signal quality = %d\n", pPhyInfo->RxMIMOEVMdbm[RxPath], pPhyInfo->RxMIMOSignalQuality[RxPath]); - DbgPrint("CFO = %d, SNR = %d\n", pPhyInfo->Cfo_tail[RxPath], pPhyInfo->RxSNR[RxPath]); - } -*/ -} - -VOID -phydm_SetCommonPhyInfo( - IN s1Byte RxPower, - IN u1Byte channel, - IN BOOLEAN bBeamformed, - IN BOOLEAN bMuPacket, - IN u1Byte bandwidth, - IN u1Byte signalQuality, - IN u1Byte rxsc, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPower = RxPower; /* RSSI in dB */ - pPhyInfo->RecvSignalPower = RxPower; /* RSSI in dB */ - pPhyInfo->channel = channel; /* channel number */ - pPhyInfo->bBeamformed = bBeamformed; /* apply BF */ - pPhyInfo->bMuPacket = bMuPacket; /* MU packet */ - pPhyInfo->rxsc = rxsc; -#endif - pPhyInfo->RxPWDBAll = odm_QueryRxPwrPercentage(RxPower); /* RSSI in percentage */ - pPhyInfo->SignalQuality = signalQuality; /* signal quality */ - pPhyInfo->BandWidth = bandwidth; /* bandwidth */ - -/* - //if (pPktinfo->bPacketMatchBSSID) - { - DbgPrint("RxPWDBAll = %d, RxPower = %d, RecvSignalPower = %d\n", pPhyInfo->RxPWDBAll, pPhyInfo->RxPower, pPhyInfo->RecvSignalPower); - DbgPrint("SignalQuality = %d\n", pPhyInfo->SignalQuality); - DbgPrint("bBeamformed = %d, bMuPacket = %d, RxCount = %d\n", pPhyInfo->bBeamformed, pPhyInfo->bMuPacket, pPhyInfo->RxCount + 1); - DbgPrint("channel = %d, rxsc = %d, BandWidth = %d\n", channel, rxsc, bandwidth); - } -*/ -} - -VOID -phydm_GetRxPhyStatusType0( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - /* Type 0 is used for cck packet */ - - PPHY_STATUS_RPT_JAGUAR2_TYPE0 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE0)pPhyStatus; - u1Byte i, SQ = 0; - s1Byte RxPower = pPhyStaRpt->pwdb - 110; - - /* Calculate Signal Quality*/ - if (pPktinfo->bPacketMatchBSSID) { - if (pPhyStaRpt->signal_quality >= 64) - SQ = 0; - else if (pPhyStaRpt->signal_quality <= 20) - SQ = 100; - else { - /* mapping to 2~99% */ - SQ = 64 - pPhyStaRpt->signal_quality; - SQ = ((SQ << 3) + SQ) >> 2; - } - } - - /* Modify CCK PWDB if old AGC */ - if (pDM_Odm->cck_new_agc == FALSE) { - u1Byte LNA_idx, VGA_idx; - -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - LNA_idx = pPhyStaRpt->lna_l; - else -#endif - LNA_idx = ((pPhyStaRpt->lna_h << 3) | pPhyStaRpt->lna_l); - VGA_idx = pPhyStaRpt->vga; - -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8723D) - RxPower = odm_CCKRSSI_8723D(LNA_idx, VGA_idx); -#endif -#if (RTL8822B_SUPPORT == 1) - /* Need to do !! */ - /*if (pDM_Odm->SupportICType & ODM_RTL8822B) */ - /*RxPower = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ -#endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - RxPower = phydm_cck_rssi_convert(pDM_Odm, LNA_idx, VGA_idx); -#endif - } - - /* Update CCK packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; - - /* Update Common information */ - phydm_SetCommonPhyInfo(RxPower, pPhyStaRpt->channel, FALSE, - FALSE, ODM_BW20M, SQ, pPhyStaRpt->rxsc, pPhyInfo); - - /* Update CCK pwdb */ - phydm_SetPerPathPhyInfo(ODM_RF_PATH_A, RxPower, 0, 0, 0, pPhyInfo); /* Update per-path information */ - - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; -/* - //if (pPktinfo->bPacketMatchBSSID) - { - DbgPrint("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", pPhyStaRpt->pwdb, pPhyStaRpt->gain, pPhyStaRpt->trsw); - DbgPrint("channel = %d, band = %d, rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->rxsc); - DbgPrint("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", pPhyStaRpt->agc_table, pPhyStaRpt->agc_rpt, pPhyStaRpt->bb_power); - DbgPrint("length = %d, SQ = %d\n", pPhyStaRpt->length, pPhyStaRpt->signal_quality); - DbgPrint("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); - DbgPrint("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2); - DbgPrint("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); - DbgPrint("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7, pPhyStaRpt->rsvd_8); - } -*/ -} - -VOID -phydm_GetRxPhyStatusType1( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - /* Type 1 is used for ofdm packet */ - - PPHY_STATUS_RPT_JAGUAR2_TYPE1 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE1)pPhyStatus; - s1Byte rx_pwr_db = -120; - u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; - BOOLEAN bMU; - u1Byte num_ss; - - /* Update OFDM packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pDM_Odm->RXAntStatus & BIT(i)) { - s1Byte rx_path_pwr_db; - - /* RX path counter */ - RxCount++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ - /* EVM report is reported by stream, not path */ - rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, pPhyStaRpt->rxevm[RxCount - 1], - pPhyStaRpt->cfo_tail[i], pPhyStaRpt->rxsnr[i], pPhyInfo); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (RxCount > 0) - pPhyInfo->RxCount = RxCount - 1; - - /* Check if MU packet or not */ - if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { - bMU = TRUE; - pDM_Odm->PhyDbgInfo.NumQryMuPkt++; - } else - bMU = FALSE; - - /* Count BF packet */ - pDM_Odm->PhyDbgInfo.NumQryBfPkt = pDM_Odm->PhyDbgInfo.NumQryBfPkt + pPhyStaRpt->beamformed; - - /* Check sub-channel */ - if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) - rxsc = pPhyStaRpt->l_rxsc; - else - rxsc = pPhyStaRpt->ht_rxsc; - - /* Check RX bandwidth */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = pPhyStaRpt->rf_mode; - } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { - if (pPhyStaRpt->rf_mode == 0) - bw = ODM_BW20M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW40M; - } - - /* Update packet information */ - phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, - bMU, bw, odm_EVMdbToPercentage(pPhyStaRpt->rxevm[0]), rxsc, pPhyInfo); - - num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); - - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfo_tail, num_ss); - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; - - if (pPktinfo->bPacketMatchBSSID) { -/* - DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc, pPhyStaRpt->rf_mode); - DbgPrint("Antidx A = %d, B = %d, C = %d, D = %d\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); - DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); - DbgPrint("EVM A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1], pPhyStaRpt->rxevm[2], pPhyStaRpt->rxevm[3]); - DbgPrint("SNR A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxsnr[0], pPhyStaRpt->rxsnr[1], pPhyStaRpt->rxsnr[2], pPhyStaRpt->rxsnr[3]); - DbgPrint("CFO A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->cfo_tail[0], pPhyStaRpt->cfo_tail[1], pPhyStaRpt->cfo_tail[2], pPhyStaRpt->cfo_tail[3]); - DbgPrint("paid = %d, gid = %d, length = %d\n", (pPhyStaRpt->paid + (pPhyStaRpt->paid_msb<<8)), pPhyStaRpt->gid, pPhyStaRpt->lsig_length); - DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); - DbgPrint("NBI: %d, pos: %d\n", pPhyStaRpt->nb_intf_flag, (pPhyStaRpt->intf_pos + (pPhyStaRpt->intf_pos_msb<<8))); - DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); -*/ - if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { - if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[pPktinfo->DataRate - 0x2C]++; - } else { - if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[pPktinfo->DataRate - 0x2C]++; - } - } -/* - DbgPrint("phydm_GetRxPhyStatusType1 pPktinfo->bPacketMatchBSSID = %d\n", pPktinfo->bPacketMatchBSSID); - DbgPrint("pPktinfo->DataRate = 0x%x\n", pPktinfo->DataRate); -*/ -} - -VOID -phydm_GetRxPhyStatusType2( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - PPHY_STATUS_RPT_JAGUAR2_TYPE2 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE2)pPhyStatus; - s1Byte rx_pwr_db = -120; - u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; - - /* Update OFDM packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pDM_Odm->RXAntStatus & BIT(i)) { - s1Byte rx_path_pwr_db; - - /* RX path counter */ - RxCount++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ -#if (RTL8197F_SUPPORT == 1) - if ((pDM_Odm->SupportICType & ODM_RTL8197F) && (pPhyStaRpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ - - if (i == ODM_RF_PATH_A) { - rx_path_pwr_db = (pPhyStaRpt->gain_a)<<1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else if (i == ODM_RF_PATH_B) { - rx_path_pwr_db = (pPhyStaRpt->gain_b)<<1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else - rx_path_pwr_db = 0; - } else -#endif - rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - - phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, 0, 0, 0, pPhyInfo); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (RxCount > 0) - pPhyInfo->RxCount = RxCount - 1; - - /* Check RX sub-channel */ - if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) - rxsc = pPhyStaRpt->l_rxsc; - else - rxsc = pPhyStaRpt->ht_rxsc; - - /* Check RX bandwidth */ - /* the BW information of sc=0 is useless, because there is no information of RF mode*/ - - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = ODM_BW20M; - } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { - if (rxsc == 3) - bw = ODM_BW40M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW20M; - } - - /* Update packet information */ - phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, - FALSE, bw, 0, rxsc, pPhyInfo); - -/* - //if (pPktinfo->bPacketMatchBSSID) - { - DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc); - DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); - DbgPrint("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->agc_table_a, pPhyStaRpt->agc_table_b, pPhyStaRpt->agc_table_c, pPhyStaRpt->agc_table_d); - DbgPrint("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->gain_a, pPhyStaRpt->gain_b, pPhyStaRpt->gain_c, pPhyStaRpt->gain_d); - DbgPrint("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->trsw_a, pPhyStaRpt->trsw_b, pPhyStaRpt->trsw_c, pPhyStaRpt->trsw_d); - DbgPrint("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->aagc_step_a, pPhyStaRpt->aagc_step_b, pPhyStaRpt->aagc_step_c, pPhyStaRpt->aagc_step_d); - DbgPrint("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->ht_aagc_gain[0], pPhyStaRpt->ht_aagc_gain[1], pPhyStaRpt->ht_aagc_gain[2], pPhyStaRpt->ht_aagc_gain[3]); - DbgPrint("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->dagc_gain[0], pPhyStaRpt->dagc_gain[1], pPhyStaRpt->dagc_gain[2], pPhyStaRpt->dagc_gain[3]); - DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); - DbgPrint("counter: %d, syn_count: %d\n", pPhyStaRpt->counter, pPhyStaRpt->syn_count); - DbgPrint("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", pPhyStaRpt->cnt_cca2agc_rdy, pPhyStaRpt->cnt_pw2cca, pPhyStaRpt->shift_l_map); - DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4); - DbgPrint("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", pPhyStaRpt->rsvd_5, pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7); - } -*/ -} - -VOID -phydm_GetRxPhyStatusType5( - IN pu1Byte pPhyStatus -) -{ -/* - DbgPrint("DW0: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 3), *(pPhyStatus + 2), *(pPhyStatus + 1), *(pPhyStatus + 0)); - DbgPrint("DW1: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 7), *(pPhyStatus + 6), *(pPhyStatus + 5), *(pPhyStatus + 4)); - DbgPrint("DW2: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 11), *(pPhyStatus + 10), *(pPhyStatus + 9), *(pPhyStatus + 8)); - DbgPrint("DW3: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 15), *(pPhyStatus + 14), *(pPhyStatus + 13), *(pPhyStatus + 12)); - DbgPrint("DW4: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 19), *(pPhyStatus + 18), *(pPhyStatus + 17), *(pPhyStatus + 16)); - DbgPrint("DW5: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 23), *(pPhyStatus + 22), *(pPhyStatus + 21), *(pPhyStatus + 20)); - DbgPrint("DW6: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 27), *(pPhyStatus + 26), *(pPhyStatus + 25), *(pPhyStatus + 24)); -*/ -} - -VOID -phydm_Process_RSSIForDMNewType( - IN OUT PDM_ODM_T pDM_Odm, - IN PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - s4Byte UndecoratedSmoothedPWDB, AccumulatePWDB; - u4Byte RSSI_Ave; - u1Byte i; - PSTA_INFO_T pEntry; - u1Byte scaling_factor = 4; - - if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) - return; - - pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; - - if (!IS_STA_VALID(pEntry)) - return; - - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ - return; - - if (pPktinfo->bPacketBeacon) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; - - if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { - u4Byte RSSI_linear = 0; - - pDM_Odm->RxRate = pPktinfo->DataRate; - UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - AccumulatePWDB = pDM_Odm->AccumulatePWDB[pPktinfo->StationID]; - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; - pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pPhyInfo->RxMIMOSignalStrength[i] != 0) - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[i]); - } - - switch (pPhyInfo->RxCount + 1) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); - - if (UndecoratedSmoothedPWDB <= 0) { - AccumulatePWDB = (pPhyInfo->RxPWDBAll << scaling_factor); - UndecoratedSmoothedPWDB = pPhyInfo->RxPWDBAll; - } else { - AccumulatePWDB = AccumulatePWDB - (AccumulatePWDB>>scaling_factor) + RSSI_Ave; - UndecoratedSmoothedPWDB = (AccumulatePWDB + (1<<(scaling_factor - 1)))>>scaling_factor; - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == -1) - phydm_ra_rssi_rpt_wk(pDM_Odm); -#endif - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - pDM_Odm->AccumulatePWDB[pPktinfo->StationID] = AccumulatePWDB; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (pPktinfo->StationID == 0) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - - pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - } -#endif - } -} - -VOID -phydm_RxPhyStatusNewType( - IN PDM_ODM_T pPhydm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo -) -{ - u1Byte phy_status_type = (*pPhyStatus & 0xf); - - /*DbgPrint("phydm_RxPhyStatusNewType================> (page: %d)\n", phy_status_type);*/ - - /* Memory reset */ - phydm_ResetPhyInfo(pPhydm, pPhyInfo); - - /* Phy status parsing */ - switch (phy_status_type) { - case 0: - { - phydm_GetRxPhyStatusType0(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); - break; - } - case 1: - { - phydm_GetRxPhyStatusType1(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); - break; - } - case 2: - { - phydm_GetRxPhyStatusType2(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); - break; - } -/* - case 5: - { - phydm_GetRxPhyStatusType5(pPhyStatus); - return; - } -*/ - default: - return; - } - - #if ((RTL8723D_SUPPORT == 1)||(RTL8197F_SUPPORT == 1)) - if (pPhydm->SupportAbility & ODM_BB_ANT_DIV) { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_Process_RSSIForAntDiv(pPhydm, pPhyInfo, pPktinfo); - #endif - } - #endif - /* Update signal strength to UI, and pPhyInfo->RxPWDBAll is the maximum RSSI of all path */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pPhyInfo->SignalStrength = SignalScaleProc(pPhydm->Adapter, pPhyInfo->RxPWDBAll, FALSE, FALSE); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pPhydm, pPhyInfo->RxPWDBAll)); -#endif - - /* Calculate average RSSI and smoothed RSSI */ - phydm_Process_RSSIForDMNewType(pPhydm, pPhyInfo, pPktinfo); - -} -/*==============================================*/ -#endif - -u4Byte -query_phydm_trx_capability( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value32 = 0xFFFFFFFF; - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_trx_capability_8821c(pDM_Odm); - #endif - - return value32; -} - -u4Byte -query_phydm_stbc_capability( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value32 = 0xFFFFFFFF; - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_stbc_capability_8821c(pDM_Odm); - #endif - - return value32; -} - -u4Byte -query_phydm_ldpc_capability( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value32 = 0xFFFFFFFF; - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_ldpc_capability_8821c(pDM_Odm); - #endif - - return value32; -} - -u4Byte -query_phydm_txbf_parameters( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value32 = 0xFFFFFFFF; - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_txbf_parameters_8821c(pDM_Odm); - #endif - - return value32; -} - -u4Byte -query_phydm_txbf_capability( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte value32 = 0xFFFFFFFF; - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_txbf_capability_8821c(pDM_Odm); - #endif - - return value32; -} +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig_MP_##ic##txt(pDM_Odm)) +#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC_##ic##txt(pDM_Odm)) + + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_AND_CONFIG(ic, txt) do {\ + if (pDM_Odm->bIsMPChip)\ + READ_AND_CONFIG_MP(ic,txt);\ + else\ + READ_AND_CONFIG_TC(ic,txt);\ + } while(0) +#else + #define READ_AND_CONFIG READ_AND_CONFIG_MP +#endif + + +#define READ_FIRMWARE_MP(ic, txt) (ODM_ReadFirmware_MP_##ic##txt(pDM_Odm, pFirmware, pSize)) +#define READ_FIRMWARE_TC(ic, txt) (ODM_ReadFirmware_TC_##ic##txt(pDM_Odm, pFirmware, pSize)) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_FIRMWARE(ic, txt) do {\ + if (pDM_Odm->bIsMPChip)\ + READ_FIRMWARE_MP(ic,txt);\ + else\ + READ_FIRMWARE_TC(ic,txt);\ + } while(0) +#else +#define READ_FIRMWARE READ_FIRMWARE_MP +#endif + +#define GET_VERSION_MP(ic, txt) (ODM_GetVersion_MP_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (ODM_GetVersion_TC_##ic##txt()) +#define GET_VERSION(ic, txt) (pDM_Odm->bIsMPChip?GET_VERSION_MP(ic,txt):GET_VERSION_TC(ic,txt)) + +u1Byte +odm_QueryRxPwrPercentage( + IN s1Byte AntPower + ) +{ + if ((AntPower <= -100) || (AntPower >= 20)) + return 0; + else if (AntPower >= 0) + return 100; + else + return (100 + AntPower); +} + + +// +// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. +// IF other SW team do not support the feature, remove this section.?? +// +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. + // 20100426 Joseph: Modify Signal strength mapping. + // This modification makes the RSSI indication similar to Intel solution. + // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. + if (CurrSig >= 54 && CurrSig <= 100) + RetSig = 100; + else if (CurrSig >= 42 && CurrSig <= 53) + RetSig = 95; + else if (CurrSig >= 36 && CurrSig <= 41) + RetSig = 74 + ((CurrSig - 36) * 20) / 6; + else if (CurrSig >= 33 && CurrSig <= 35) + RetSig = 65 + ((CurrSig - 33) * 8) / 2; + else if (CurrSig >= 18 && CurrSig <= 32) + RetSig = 62 + ((CurrSig - 18) * 2) / 15; + else if (CurrSig >= 15 && CurrSig <= 17) + RetSig = 33 + ((CurrSig - 15) * 28) / 2; + else if (CurrSig >= 10 && CurrSig <= 14) + RetSig = 39; + else if (CurrSig >= 8 && CurrSig <= 9) + RetSig = 33; + else if (CurrSig <= 8) + RetSig = 19; + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) + return RetSig; +} + +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) + { + // Netcore request this modification because 2009.04.13 SU driver use it. + if (CurrSig >= 31 && CurrSig <= 100) + RetSig = 100; + else if (CurrSig >= 21 && CurrSig <= 30) + RetSig = 90 + ((CurrSig - 20) / 1); + else if (CurrSig >= 11 && CurrSig <= 20) + RetSig = 80 + ((CurrSig - 10) / 1); + else if (CurrSig >= 7 && CurrSig <= 10) + RetSig = 69 + (CurrSig - 7); + else if (CurrSig == 6) + RetSig = 54; + else if (CurrSig == 5) + RetSig = 45; + else if (CurrSig == 4) + RetSig = 36; + else if (CurrSig == 3) + RetSig = 27; + else if (CurrSig == 2) + RetSig = 18; + else if (CurrSig == 1) + RetSig = 9; + else + RetSig = CurrSig; + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) + return RetSig; +} + + +s4Byte +odm_SignalScaleMapping_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + if(CurrSig >= 61 && CurrSig <= 100) + { + RetSig = 90 + ((CurrSig - 60) / 4); + } + else if(CurrSig >= 41 && CurrSig <= 60) + { + RetSig = 78 + ((CurrSig - 40) / 2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 5 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 5) * 2) / 3); + } + else if(CurrSig == 4) + { + RetSig = 36; + } + else if(CurrSig == 3) + { + RetSig = 27; + } + else if(CurrSig == 2) + { + RetSig = 18; + } + else if(CurrSig == 1) + { + RetSig = 9; + } + else + { + RetSig = CurrSig; + } + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) + { + if(CurrSig >= 51 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig >= 41 && CurrSig <= 50) + { + RetSig = 80 + ((CurrSig - 40)*2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 10 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 10) * 2) / 3); + } + else if(CurrSig >= 5 && CurrSig <= 9) + { + RetSig = 22 + (((CurrSig - 5) * 3) / 2); + } + else if(CurrSig >= 1 && CurrSig <= 4) + { + RetSig = 6 + (((CurrSig - 1) * 3) / 2); + } + else + { + RetSig = CurrSig; + } + } + +#endif + return RetSig; +} +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if( (pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO + (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); + } + else if( (pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && + (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); + }else +#endif + { +#ifdef CONFIG_SIGNAL_SCALE_MAPPING + return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); +#else + return CurrSig; +#endif + } + +} + + + +static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( + IN PDM_ODM_T pDM_Odm, + IN u1Byte isCCKrate, + IN u1Byte PWDB_ALL, + IN u1Byte path, + IN u1Byte RSSI +) +{ + u1Byte SQ = 0; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if(isCCKrate){ + + if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { + + // + // Expected signal strength and bars indication at Lenovo lab. 2013.04.11 + // 802.11n, 802.11b, 802.11g only at channel 6 + // + // Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) + // 50 5 -49 + // 55 5 -49 + // 60 5 -50 + // 65 5 -51 + // 70 5 -52 + // 75 5 -54 + // 80 5 -55 + // 85 4 -60 + // 90 3 -63 + // 95 3 -65 + // 100 2 -67 + // 102 2 -67 + // 104 1 -70 + // + + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 31 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 22 && PWDB_ALL < 31) + SQ = 40; + else if(PWDB_ALL >= 18 && PWDB_ALL < 22) + SQ = 20; + else + SQ = 10; + } else { + if (PWDB_ALL >= 50) + SQ = 100; + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if (PWDB_ALL >= 22 && PWDB_ALL < 35) + SQ = 60; + else if (PWDB_ALL >= 18 && PWDB_ALL < 22) + SQ = 40; + else + SQ = 10; + } + + } + else + {//OFDM rate + + if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } else { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_TRACE, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); + +#endif + return SQ; +} + +static u1Byte odm_SQ_process_patch_RT_CID_819x_Acer( + IN PDM_ODM_T pDM_Odm, + IN u1Byte isCCKrate, + IN u1Byte PWDB_ALL, + IN u1Byte path, + IN u1Byte RSSI +) +{ + u1Byte SQ = 0; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if(isCCKrate){ + + RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); + +#if OS_WIN_FROM_WIN8(OS_VERSION) + + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if(PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; +#else + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if(PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; + + if(PWDB_ALL == 0)// Abnormal case, do not indicate the value above 20 on Win7 + SQ = 20; +#endif + + + + } + else + {//OFDM rate + + if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } + else + { + if(RSSI >= 35) + SQ = 100; + else if(RSSI >= 30 && RSSI < 35) + SQ = 80; + else if(RSSI >= 25 && RSSI < 30) + SQ = 40; + else + SQ = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_LOUD, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); + +#endif + return SQ; +} + +static u1Byte +odm_EVMdbToPercentage( + IN s1Byte Value + ) +{ + // + // -33dB~0dB to 0%~99% + // + s1Byte ret_val; + + ret_val = Value; + ret_val /= 2; + + /*DbgPrint("Value=%d\n", Value);*/ + /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val));*/ +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -40) + ret_val = -40; + + ret_val = 0 - ret_val; + ret_val *= 3; +#else + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; +#endif + + return (u1Byte)ret_val; +} + +static u1Byte +odm_EVMdbm_JaguarSeries( + IN s1Byte Value + ) +{ + s1Byte ret_val = Value; + + // -33dB~0dB to 33dB ~ 0dB + if(ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u1Byte)ret_val; +} + +static s2Byte +odm_Cfo( + IN s1Byte Value +) +{ + s2Byte ret_val; + + if (Value < 0) + { + ret_val = 0 - Value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; // *2.5~=312.5/2^7 + ret_val = ret_val | BIT12; // set bit12 as 1 for negative cfo + } + else + { + ret_val = Value; + ret_val = (ret_val << 1) + (ret_val>>1) ; // *2.5~=312.5/2^7 + } + return ret_val; +} + +u1Byte +phydm_rate_to_num_ss( + IN OUT PDM_ODM_T pDM_Odm, + IN u1Byte DataRate +) +{ + u1Byte num_ss = 1; + + if (DataRate <= ODM_RATE54M) + num_ss = 1; + else if (DataRate <= ODM_RATEMCS31) + num_ss = ((DataRate - ODM_RATEMCS0) >> 3)+1; + else if (DataRate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (DataRate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (DataRate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (DataRate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} + +#if(ODM_IC_11N_SERIES_SUPPORT == 1) + +s1Byte +odm_CCKRSSI_8703B( + IN u2Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all = 0x00; + + switch (LNA_idx) { + case 0xf: + rx_pwr_all = -48 - (2 * VGA_idx); + break; + case 0xb: + rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ + break; + case 0xa: + rx_pwr_all = -36 - (2 * VGA_idx); + break; + case 8: + rx_pwr_all = -32 - (2 * VGA_idx); + break; + case 7: + rx_pwr_all = -19 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = -6 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = -2 - (2 * VGA_idx); + break; + default: + /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ + /*DbgPrint("wrong LNA index\n");*/ + break; + + } + return rx_pwr_all; +} + +s1Byte +odm_CCKRSSI_8192E( + IN OUT PDM_ODM_T pDM_Odm, + IN u2Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all = 0; + s1Byte lna_gain = 0; + s1Byte lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; + s1Byte lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ + + if (pDM_Odm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[LNA_idx]; + else + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} + +s1Byte +odm_CCKRSSI_8188E( + IN OUT PDM_ODM_T pDM_Odm, + IN u2Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all = 0; + s1Byte lna_gain = 0; + s1Byte lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ + s1Byte lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ + + if (pDM_Odm->CutVersion >= ODM_CUT_I) /*SMIC*/ + lna_gain = lna_gain_table_0[LNA_idx]; + else /*TSMC*/ + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} + +s8 +phydm_cck_rssi_convert( + IN OUT PDM_ODM_T pDM_Odm, + u16 lna_idx, + u8 vga_idx +) +{ + return (pDM_Odm->cck_lna_gain_table[lna_idx] - (vga_idx << 1)); +} + +void +phydm_get_cck_rssi_table_from_reg( + IN OUT PDM_ODM_T pDM_Odm +) +{ + u8 used_lna_idx_tmp; + u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; /*example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ /*{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/ + u8 i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("CCK LNA Gain table init\n")); + + if (!(pDM_Odm->SupportICType & (ODM_RTL8197F))) + return; + + reg_0xa80 = ODM_GetBBReg(pDM_Odm, 0xa80, 0xFFFF); + reg_0xabc = ODM_GetBBReg(pDM_Odm, 0xabc, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("reg_0xa80 = 0x%x\n", reg_0xa80)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("reg_0xabc = 0x%x\n", reg_0xabc)); + + for (i = 0; i<=3; i++) { + used_lna_idx_tmp = ((reg_0xa80 >> (4*i)) & 0x7); + pDM_Odm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)((reg_0xabc >> (8*i)) & 0xff); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n", + pDM_Odm->cck_lna_gain_table[0], + pDM_Odm->cck_lna_gain_table[1], + pDM_Odm->cck_lna_gain_table[2], + pDM_Odm->cck_lna_gain_table[3], + pDM_Odm->cck_lna_gain_table[4], + pDM_Odm->cck_lna_gain_table[5], + pDM_Odm->cck_lna_gain_table[6], + pDM_Odm->cck_lna_gain_table[7])); + +} + +VOID +odm_RxPhyStatus92CSeries_Parsing( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u1Byte i, Max_spatial_stream; + s1Byte rx_pwr[4], rx_pwr_all=0; + u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; + u1Byte RSSI, total_rssi=0; + BOOLEAN isCCKrate=FALSE; + u1Byte rf_rx_num = 0; + u1Byte cck_highpwr = 0; + u1Byte LNA_idx = 0; + u1Byte VGA_idx = 0; + u1Byte cck_agc_rpt; + u1Byte num_ss; + u8 stream_rxevm_tmp; + PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; + + isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M) ? TRUE : FALSE; + + if (pPktinfo->bToSelf) + pDM_Odm->curr_station_id = pPktinfo->StationID; + + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + + + if(isCCKrate) + { + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; + + if (pDM_Odm->SupportICType & (ODM_RTL8703B)) { + + #if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->cck_agc_report_type == 1) { /*4 bit LNA*/ + + u1Byte cck_agc_rpt_b = (pPhyStaRpt->cck_rpt_b_ofdm_cfosho_b & BIT7) ? 1 : 0; + + LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); + } + #endif + } else { /*3 bit LNA*/ + + LNA_idx = ((cck_agc_rpt & 0xE0) >>5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (pDM_Odm->SupportICType & (ODM_RTL8188E)) { + + #if (RTL8188E_SUPPORT == 1) + rx_pwr_all = odm_CCKRSSI_8188E(pDM_Odm, LNA_idx, VGA_idx); + /**/ + #endif + } + #if (RTL8192E_SUPPORT == 1) + else if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { + + rx_pwr_all = odm_CCKRSSI_8192E(pDM_Odm, LNA_idx, VGA_idx); + /**/ + } + #endif + #if (RTL8723B_SUPPORT == 1) + else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { + + rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx,VGA_idx); + /**/ + } + #endif + #if (RTL8188F_SUPPORT == 1) + else if (pDM_Odm->SupportICType & (ODM_RTL8188F)) { + + rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); + /**/ + } + #endif + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ExtLNAGain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", + pDM_Odm->ExtLNAGain, LNA_idx, VGA_idx, rx_pwr_all)); + + if (pDM_Odm->BoardType & ODM_BOARD_EXT_LNA) + rx_pwr_all -= pDM_Odm->ExtLNAGain; + + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + if (pPktinfo->bToSelf) { + pDM_Odm->cck_lna_idx = LNA_idx; + pDM_Odm->cck_vga_idx = VGA_idx; + } + pPhyInfo->RxPWDBAll = PWDB_ALL; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + // + // (3) Get Signal Quality (EVM) + // + //if(pPktinfo->bPacketMatchBSSID) + { + u1Byte SQ,SQ_rpt; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Lenovo)){ + SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); + }else if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Acer)) + { + SQ = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,0); + }else +#endif + if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ + SQ = 100; + } + else{ + SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; + + if(SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64-SQ_rpt) * 100) / 44; + + } + + //DbgPrint("cck SQ = %d\n", SQ); + pPhyInfo->SignalQuality = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { + if (i == 0) + pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + else + pPhyInfo->RxMIMOSignalStrength[1] = 0; + } + } + else //2 is OFDM rate + { + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + // + // (1)Get RSSI for HT rate + // + + for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) + { + // 2008/01/30 MH we will judge RF RX path now. + if (pDM_Odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; + //else + //continue; + + rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; + + if (pPktinfo->bToSelf) { + pDM_Odm->ofdm_agc_idx[i] = (pPhyStaRpt->path_agc[i].gain & 0x3F); + /**/ + } + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[i] = rx_pwr[i]; + #endif + + /* Translate DBM to percentage. */ + RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + total_rssi += RSSI; + //RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); + + pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; + + #if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) + //Get Rx snr value in DB + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); + #endif + + /* Record Signal Strength for next packet */ + //if(pPktinfo->bPacketMatchBSSID) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Lenovo)) + { + if(i==ODM_RF_PATH_A) + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); + + } + else if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Acer)) + { + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,RSSI); + } +#endif + } + } + + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; + + PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + + pPhyInfo->RxPWDBAll = PWDB_ALL; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->RecvSignalPower = rx_pwr_all; + #endif + + if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==19)){ + //do nothing + }else if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==25)){ + //do nothing + } + else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo + // + // (3)EVM of HT rate + // + if(pPktinfo->DataRate >=ODM_RATEMCS8 && pPktinfo->DataRate <=ODM_RATEMCS15) + Max_spatial_stream = 2; //both spatial stream make sense + else + Max_spatial_stream = 1; //only spatial stream 1 makes sense + + for(i=0; i>= 1" because the compilor of free build environment + // fill most significant bit to "zero" when doing shifting operation which may change a negative + // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. + EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm + + //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); + + //if(pPktinfo->bPacketMatchBSSID) + { + if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only + { + pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); + } + pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); + + if (pPhyStaRpt->stream_rxevm[i] < 0) { + + stream_rxevm_tmp = (u8 )(0 - (pPhyStaRpt->stream_rxevm[i])); + } + + if (stream_rxevm_tmp == 64) + stream_rxevm_tmp = 0; + + pPhyInfo->RxMIMOEVMdbm[i] = stream_rxevm_tmp; + } + } + } + + num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); + ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->path_cfotail, num_ss); + + } +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + //UI BSS List signal strength(in percentage), make it good looking, from 0~100. + //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + if(isCCKrate) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, TRUE, TRUE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + } + else + { + if (rf_rx_num != 0) + { + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, (total_rssi /= rf_rx_num), TRUE, FALSE); + #else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num)); + #endif + } + } +#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ + + //DbgPrint("isCCKrate = %d, pPhyInfo->RxPWDBAll = %d, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", + //isCCKrate, pPhyInfo->RxPWDBAll, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a); + + //For 92C/92D HW (Hybrid) Antenna Diversity +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + //For 88E HW Antenna Diversity + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; +#endif +} +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + +VOID +odm_RxPhyBWJaguarSeries_Parsing( + OUT PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo, + IN PPHY_STATUS_RPT_8812_T pPhyStaRpt +) +{ + + if(pPktinfo->DataRate <= ODM_RATE54M) { + switch (pPhyStaRpt->r_RFMOD) { + case 1: + if (pPhyStaRpt->sub_chnl == 0) + pPhyInfo->BandWidth = 1; + else + pPhyInfo->BandWidth = 0; + break; + + case 2: + if (pPhyStaRpt->sub_chnl == 0) + pPhyInfo->BandWidth = 2; + else if (pPhyStaRpt->sub_chnl == 9 || pPhyStaRpt->sub_chnl == 10) + pPhyInfo->BandWidth = 1; + else + pPhyInfo->BandWidth = 0; + break; + + default: + case 0: + pPhyInfo->BandWidth = 0; + break; + } + } + +} + +VOID +odm_RxPhyStatusJaguarSeries_Parsing( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo +) +{ + u1Byte i, Max_spatial_stream; + s1Byte rx_pwr[4], rx_pwr_all = 0; + u1Byte EVM, EVMdbm, PWDB_ALL = 0, PWDB_ALL_BT; + u1Byte RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; + u1Byte isCCKrate = 0; + u1Byte rf_rx_num = 0; + u1Byte cck_highpwr = 0; + u1Byte LNA_idx, VGA_idx; + PPHY_STATUS_RPT_8812_T pPhyStaRpt = (PPHY_STATUS_RPT_8812_T)pPhyStatus; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte num_ss; + + odm_RxPhyBWJaguarSeries_Parsing(pPhyInfo, pPktinfo, pPhyStaRpt); + + if (pPktinfo->DataRate <= ODM_RATE11M) + isCCKrate = TRUE; + else + isCCKrate = FALSE; + + if (pPktinfo->bToSelf) + pDM_Odm->curr_station_id = pPktinfo->StationID; + else + pDM_Odm->curr_station_id = 0xff; + + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_C] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_D] = -1; + + if (isCCKrate) { + u1Byte cck_agc_rpt; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + + /*(1)Hardware does not provide RSSI for CCK*/ + /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*if(pHalData->eRFPowerState == eRfOn)*/ + cck_highpwr = pDM_Odm->bCckHighPower; + /*else*/ + /*cck_highpwr = FALSE;*/ + + cck_agc_rpt = pPhyStaRpt->cfosho[0] ; + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (pDM_Odm->SupportICType == ODM_RTL8812) { + switch (LNA_idx) { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ + break; + case 5: + rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ + break; + case 4: + rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ + break; + case 3: + /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ + rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ + break; + case 2: + if (cck_highpwr) + rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ + else + rx_pwr_all = -6 + 2 * (5 - VGA_idx); + break; + case 1: + rx_pwr_all = 8 - 2 * VGA_idx; + break; + case 0: + rx_pwr_all = 14 - 2 * VGA_idx; + break; + default: + /*DbgPrint("CCK Exception default\n");*/ + break; + } + rx_pwr_all += 6; + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + if (cck_highpwr == FALSE) { + if (PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; + else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if (PWDB_ALL > 100) + PWDB_ALL = 100; + } + } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { + s1Byte Pout = -6; + + switch (LNA_idx) { + case 5: + rx_pwr_all = Pout - 32 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = Pout - 24 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = Pout - 11 - (2 * VGA_idx); + break; + case 1: + rx_pwr_all = Pout + 5 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = Pout + 21 - (2 * VGA_idx); + break; + } + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + } else if (pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8822B) { + s1Byte Pout = -6; + + switch (LNA_idx) { + /*CCK only use LNA: 2, 3, 5, 7*/ + case 7: + rx_pwr_all = Pout - 32 - (2 * VGA_idx); + break; + case 5: + rx_pwr_all = Pout - 22 - (2 * VGA_idx); + break; + case 3: + rx_pwr_all = Pout - 2 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = Pout + 5 - (2 * VGA_idx); + break; + /*case 6:*/ + /*rx_pwr_all = Pout -26 - (2*VGA_idx);*/ + /*break;*/ + /*case 4:*/ + /*rx_pwr_all = Pout - 8 - (2*VGA_idx);*/ + /*break;*/ + /*case 1:*/ + /*rx_pwr_all = Pout + 21 - (2*VGA_idx);*/ + /*break;*/ + /*case 0:*/ + /*rx_pwr_all = Pout + 10 - (2*VGA_idx);*/ +/* // break;*/ + default: +/* //DbgPrint("CCK Exception default\n");*/ + break; + } + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + } + + pDM_Odm->cck_lna_idx = LNA_idx; + pDM_Odm->cck_vga_idx = VGA_idx; + pPhyInfo->RxPWDBAll = PWDB_ALL; +/* //if(pPktinfo->StationID == 0)*/ +/* //{*/ +/* // DbgPrint("CCK: LNA_idx = %d, VGA_idx = %d, pPhyInfo->RxPWDBAll = %d\n",*/ +/* // LNA_idx, VGA_idx, pPhyInfo->RxPWDBAll);*/ +/* //}*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + /*(3) Get Signal Quality (EVM)*/ + /*if (pPktinfo->bPacketMatchBSSID)*/ + { + u1Byte SQ, SQ_rpt; + + if ((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { + SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, 0, 0); + } else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest) { + SQ = 100; + } else { + SQ_rpt = pPhyStaRpt->pwdb_all; + + if (SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64 - SQ_rpt) * 100) / 44; + } + +/* //DbgPrint("cck SQ = %d\n", SQ);*/ + pPhyInfo->SignalQuality = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (i == 0) + pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + else + pPhyInfo->RxMIMOSignalStrength[i] = 0; + } + } else { + /*is OFDM rate*/ + pDM_FatTable->hw_antsw_occur = pPhyStaRpt->hw_antsw_occur; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /*(1)Get RSSI for OFDM rate*/ + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + /*2008/01/30 MH we will judge RF RX path now.*/ +/* //DbgPrint("pDM_Odm->RFPathRxEnable = %x\n", pDM_Odm->RFPathRxEnable);*/ + if (pDM_Odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; +/* //else*/ +/* //continue;*/ + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ +/* //if((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) && (!pDM_Odm->bIsMPChip))*/ + if (i < ODM_RF_PATH_C) + rx_pwr[i] = (pPhyStaRpt->gain_trsw[i] & 0x7F) - 110; + else + rx_pwr[i] = (pPhyStaRpt->gain_trsw_cd[i - 2] & 0x7F) - 110; +/* //else*/ + /*rx_pwr[i] = ((pPhyStaRpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[i] = rx_pwr[i]; +#endif + + /* Translate DBM to percentage. */ + RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + + /*total_rssi += RSSI;*/ + /*Get the best two RSSI*/ + if (RSSI > best_rssi && RSSI > second_rssi) { + second_rssi = best_rssi; + best_rssi = RSSI; + } else if (RSSI > second_rssi && RSSI <= best_rssi) + second_rssi = RSSI; + + /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ + + pPhyInfo->RxMIMOSignalStrength[i] = (u1Byte) RSSI; + + + /*Get Rx snr value in DB*/ + if (i < ODM_RF_PATH_C) + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->rxsnr[i] / 2; + else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->csi_current[i - 2] / 2; + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + /*(2) CFO_short & CFO_tail*/ + if (i < ODM_RF_PATH_C) { + pPhyInfo->Cfo_short[i] = odm_Cfo((pPhyStaRpt->cfosho[i])); + pPhyInfo->Cfo_tail[i] = odm_Cfo((pPhyStaRpt->cfotail[i])); + } +#endif + /* Record Signal Strength for next packet */ + if (pPktinfo->bPacketMatchBSSID) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if ((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { + if (i == ODM_RF_PATH_A) + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, i, RSSI); + + } +#endif + } + } + + /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + if ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!pDM_Odm->bIsMPChip)) + rx_pwr_all = (pPhyStaRpt->pwdb_all & 0x7f) - 110; + else + rx_pwr_all = (((pPhyStaRpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ + + PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + pPhyInfo->RxPWDBAll = PWDB_ALL; + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll));*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + + if ((pDM_Odm->SupportPlatform == ODM_WIN) && (pDM_Odm->PatchID == 19)) { + /*do nothing*/ + } else { + /*pMgntInfo->CustomerID != RT_CID_819x_Lenovo*/ + + /*(4)EVM of OFDM rate*/ + + if ((pPktinfo->DataRate >= ODM_RATEMCS8) && + (pPktinfo->DataRate <= ODM_RATEMCS15)) + Max_spatial_stream = 2; + else if ((pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0) && + (pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) + Max_spatial_stream = 2; + else if ((pPktinfo->DataRate >= ODM_RATEMCS16) && + (pPktinfo->DataRate <= ODM_RATEMCS23)) + Max_spatial_stream = 3; + else if ((pPktinfo->DataRate >= ODM_RATEVHTSS3MCS0) && + (pPktinfo->DataRate <= ODM_RATEVHTSS3MCS9)) + Max_spatial_stream = 3; + else + Max_spatial_stream = 1; + + /*if (pPktinfo->bPacketMatchBSSID) */ + { + /*DbgPrint("pPktinfo->DataRate = %d\n", pPktinfo->DataRate);*/ + + for (i = 0; i < Max_spatial_stream; i++) { + /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ + /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ + /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ + + if (pPktinfo->DataRate >= ODM_RATE6M && pPktinfo->DataRate <= ODM_RATE54M) { + if (i == ODM_RF_PATH_A) { + EVM = odm_EVMdbToPercentage((pPhyStaRpt->sigevm)); /*dbm*/ + EVM += 20; + if (EVM > 100) + EVM = 100; + } + } else { + if (i < ODM_RF_PATH_C) { + if (pPhyStaRpt->rxevm[i] == -128) + pPhyStaRpt->rxevm[i] = -25; + EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm[i])); /*dbm*/ + } else { + if (pPhyStaRpt->rxevm_cd[i - 2] == -128){ + pPhyStaRpt->rxevm_cd[i - 2] = -25; + } + EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm_cd[i - 2])); /*dbm*/ + } + } + + if (i < ODM_RF_PATH_C) + EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm[i]); + else + EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm_cd[i - 2]); + /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ + /*pPktinfo->DataRate, pPhyStaRpt->rxevm[i], "%", EVM));*/ + + { + if (i == ODM_RF_PATH_A) { + /*Fill value in RFD, Get the first spatial stream only*/ + pPhyInfo->SignalQuality = EVM; + } + pPhyInfo->RxMIMOSignalQuality[i] = EVM; +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + pPhyInfo->RxMIMOEVMdbm[i] = EVMdbm; +#endif + } + } + } + } + + num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); + ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfotail, num_ss); + + } +/* //DbgPrint("isCCKrate= %d, pPhyInfo->SignalStrength=%d % PWDB_AL=%d rf_rx_num=%d\n", isCCKrate, pPhyInfo->SignalStrength, PWDB_ALL, rf_rx_num);*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ + /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ + if (isCCKrate) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, FALSE, TRUE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ +#endif + } else { + if (rf_rx_num != 0) { + /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ + if (rf_rx_num == 1) + avg_rssi = best_rssi; + else + avg_rssi = (best_rssi + second_rssi)/2; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, avg_rssi, FALSE, FALSE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, avg_rssi)); +#endif + } + } +#endif + pDM_Odm->RxPWDBAve = pDM_Odm->RxPWDBAve + pPhyInfo->RxPWDBAll; + + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_anta; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_antb; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_antc; + pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_antd; + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", pPktinfo->StationID, pPhyStaRpt->antidx_anta, pPktinfo->bPacketMatchBSSID));*/ + + +/* DbgPrint("pPhyStaRpt->antidx_anta = %d, pPhyStaRpt->antidx_antb = %d\n",*/ +/* pPhyStaRpt->antidx_anta, pPhyStaRpt->antidx_antb);*/ +/* DbgPrint("----------------------------\n");*/ +/* DbgPrint("pPktinfo->StationID=%d, pPktinfo->DataRate=0x%x\n",pPktinfo->StationID, pPktinfo->DataRate);*/ +/* DbgPrint("pPhyStaRpt->r_RFMOD = %d\n", pPhyStaRpt->r_RFMOD);*/ +/* DbgPrint("pPhyStaRpt->gain_trsw[0]=0x%x, pPhyStaRpt->gain_trsw[1]=0x%x\n",*/ +/* pPhyStaRpt->gain_trsw[0],pPhyStaRpt->gain_trsw[1]);*/ +/* DbgPrint("pPhyStaRpt->gain_trsw[2]=0x%x, pPhyStaRpt->gain_trsw[3]=0x%x\n",*/ +/* pPhyStaRpt->gain_trsw_cd[0],pPhyStaRpt->gain_trsw_cd[1]);*/ +/* DbgPrint("pPhyStaRpt->pwdb_all = 0x%x, pPhyInfo->RxPWDBAll = %d\n", pPhyStaRpt->pwdb_all, pPhyInfo->RxPWDBAll);*/ +/* DbgPrint("pPhyStaRpt->cfotail[i] = 0x%x, pPhyStaRpt->CFO_tail[i] = 0x%x\n", pPhyStaRpt->cfotail[0], pPhyStaRpt->cfotail[1]);*/ +/* DbgPrint("pPhyStaRpt->rxevm[0] = %d, pPhyStaRpt->rxevm[1] = %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1]);*/ +/* DbgPrint("pPhyStaRpt->rxevm[2] = %d, pPhyStaRpt->rxevm[3] = %d\n", pPhyStaRpt->rxevm_cd[0], pPhyStaRpt->rxevm_cd[1]);*/ +/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[0]=%d, pPhyInfo->RxMIMOSignalStrength[1]=%d, RxPWDBAll=%d\n",*/ +/* pPhyInfo->RxMIMOSignalStrength[0], pPhyInfo->RxMIMOSignalStrength[1], pPhyInfo->RxPWDBAll);*/ +/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[2]=%d, pPhyInfo->RxMIMOSignalStrength[3]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalStrength[2], pPhyInfo->RxMIMOSignalStrength[3]);*/ +/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[0]=%d, pPhyInfo->RxMIMOSignalQuality[1]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalQuality[0], pPhyInfo->RxMIMOSignalQuality[1]);*/ +/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[2]=%d, pPhyInfo->RxMIMOSignalQuality[3]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalQuality[2], pPhyInfo->RxMIMOSignalQuality[3]);*/ + +} + +#endif + +VOID +phydm_reset_rssi_for_dm( + IN OUT PDM_ODM_T pDM_Odm, + IN u1Byte station_id + ) +{ + PSTA_INFO_T pEntry; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #endif + + pEntry = pDM_Odm->pODM_StaInfo[station_id]; + + if (!IS_STA_VALID(pEntry)) { + /**/ + return; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); + + + pEntry->rssi_stat.UndecoratedSmoothedCCK = -1; + pEntry->rssi_stat.UndecoratedSmoothedOFDM = -1; + pEntry->rssi_stat.UndecoratedSmoothedPWDB = -1; + pEntry->rssi_stat.OFDM_pkt = 0; + pEntry->rssi_stat.CCK_pkt = 0; + pEntry->rssi_stat.CCK_sum_power = 0; + pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_INIT; + pEntry->rssi_stat.PacketMap = 0; + pEntry->rssi_stat.ValidBit = 0; + + /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + pEntry->bUsed = 0; + if (station_id == 0) { + + pHalData->UndecoratedSmoothedPWDB = -1; + /**/ + } + #endif + +} + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ) +{ + +} + +VOID +odm_Process_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + + s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave, CCK_pkt; + u1Byte i, isCCKrate=0; + u1Byte RSSI_max, RSSI_min; + u4Byte Weighting=0; + u1Byte send_rssi_2_fw = 0; + PSTA_INFO_T pEntry; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #endif + + if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(pDM_Odm, pPhyInfo, pPktinfo); + #endif + + // + // 2012/05/30 MH/Luke.Lee Add some description + // In windows driver: AP/IBSS mode STA + // + //if (pDM_Odm->SupportPlatform == ODM_WIN) + //{ + // pEntry = pDM_Odm->pODM_StaInfo[pDM_Odm->pAidMap[pPktinfo->StationID-1]]; + //} + //else + pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + + if (!IS_STA_VALID(pEntry)) { + return; + /**/ + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && + (pDM_FatTable->enable_ctrl_frame_antdiv) + ) + { + if (pPktinfo->bPacketMatchBSSID) + pDM_Odm->data_frame_num++; + + if ((pDM_FatTable->use_ctrl_frame_antdiv)) { + if (!pPktinfo->bToSelf)/*data frame + CTRL frame*/ + return; + } else { + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + } + } else +#endif + { + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + } + + if(pPktinfo->bPacketBeacon) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; + + isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M )?TRUE :FALSE; + pDM_Odm->RxRate = pPktinfo->DataRate; + + if ((pPktinfo->DataRate >= ODM_RATEMCS8 && pPktinfo->DataRate <= ODM_RATEMCS15) || + (pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0 && pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) { + + pDM_Odm->rate_ss = 2; + } else { + + pDM_Odm->rate_ss = 1; + } + + //--------------Statistic for antenna/path diversity------------------ + if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) + { + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_Process_RSSIForAntDiv(pDM_Odm,pPhyInfo,pPktinfo); + #endif + } + #if(defined(CONFIG_PATH_DIVERSITY)) + else if(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV) + { + phydm_process_rssi_for_path_div(pDM_Odm,pPhyInfo,pPktinfo); + } + #endif + //-----------------Smart Antenna Debug Message------------------// + + UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; + UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; + UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) + { + + if(!isCCKrate)//ofdm rate + { +#if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) { + u1Byte RX_count = 0; + u4Byte RSSI_linear = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_A) { + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); + } else + pDM_Odm->RSSI_A = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_B) { + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]); + } else + pDM_Odm->RSSI_B = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_C) { + pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]); + } else + pDM_Odm->RSSI_C = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_D) { + pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]); + } else + pDM_Odm->RSSI_D = 0; + + /* Calculate average RSSI */ + switch (RX_count) { + case 2: + RSSI_linear = (RSSI_linear >> 1); + break; + case 3: + RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ + break; + case 4: + RSSI_linear = (RSSI_linear >> 2); + break; + } + RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + } else +#endif + { + if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) { + RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = 0; + } else { + /*DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n",*/ + /*pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);*/ + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + + if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + } else { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + } + if ((RSSI_max - RSSI_min) < 3) + RSSI_Ave = RSSI_max; + else if ((RSSI_max - RSSI_min) < 6) + RSSI_Ave = RSSI_max - 1; + else if ((RSSI_max - RSSI_min) < 10) + RSSI_Ave = RSSI_max - 2; + else + RSSI_Ave = RSSI_max - 3; + } + } + + //1 Process OFDM RSSI + if(UndecoratedSmoothedOFDM <= 0) // initialize + { + UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", UndecoratedSmoothedOFDM)); + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", UndecoratedSmoothedOFDM)); + } + else + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", UndecoratedSmoothedOFDM)); + } + } + if (pEntry->rssi_stat.OFDM_pkt != 64) { + i = 63; + pEntry->rssi_stat.OFDM_pkt -= (u1Byte)(((pEntry->rssi_stat.PacketMap>>i)&BIT0)-1); + } + pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; + + } + else + { + RSSI_Ave = pPhyInfo->RxPWDBAll; + pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll; + pDM_Odm->RSSI_B = 0xFF; + pDM_Odm->RSSI_C = 0xFF; + pDM_Odm->RSSI_D = 0xFF; + + if (pEntry->rssi_stat.CCK_pkt <= 63) + pEntry->rssi_stat.CCK_pkt++; + + //1 Process CCK RSSI + if(UndecoratedSmoothedCCK <= 0) // initialize + { + UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; + pEntry->rssi_stat.CCK_sum_power = (u2Byte)pPhyInfo->RxPWDBAll ; /*reset*/ + pEntry->rssi_stat.CCK_pkt = 1; /*reset*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", UndecoratedSmoothedCCK)); + } else if (pEntry->rssi_stat.CCK_pkt <= CCK_RSSI_INIT_COUNT) { + + pEntry->rssi_stat.CCK_sum_power = pEntry->rssi_stat.CCK_sum_power + (u2Byte)pPhyInfo->RxPWDBAll; + UndecoratedSmoothedCCK = pEntry->rssi_stat.CCK_sum_power/pEntry->rssi_stat.CCK_pkt; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), CCK_pkt = (( %d ))\n", + UndecoratedSmoothedCCK, pEntry->rssi_stat.CCK_sum_power, pEntry->rssi_stat.CCK_pkt)); + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", UndecoratedSmoothedCCK)); + } + else + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", UndecoratedSmoothedCCK)); + } + } + i = 63; + pEntry->rssi_stat.OFDM_pkt -= (u1Byte)((pEntry->rssi_stat.PacketMap>>i)&BIT0); + pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; + } + + //if(pEntry) + { + //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI + if (pEntry->rssi_stat.OFDM_pkt == 64) { /* speed up when all packets are OFDM*/ + UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK)); + } else { + if (pEntry->rssi_stat.ValidBit < 64) + pEntry->rssi_stat.ValidBit++; + + if (pEntry->rssi_stat.ValidBit == 64) { + Weighting = ((pEntry->rssi_stat.OFDM_pkt) > 4) ? 64 : (pEntry->rssi_stat.OFDM_pkt<<4); + UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, Weighting)); + } else { + if (pEntry->rssi_stat.ValidBit != 0) + UndecoratedSmoothedPWDB = (pEntry->rssi_stat.OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-pEntry->rssi_stat.OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; + else + UndecoratedSmoothedPWDB = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), OFDM_pkt = (( %d )), Valid_Bit = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.ValidBit)); + } + } + + + if ((pEntry->rssi_stat.OFDM_pkt >= 1 || pEntry->rssi_stat.CCK_pkt >= 5) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_INIT)) { + + send_rssi_2_fw = 1; + pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_SEND; + } + + pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; + pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + + + + if (send_rssi_2_fw) /* Trigger init rate by RSSI */ { + + if (pEntry->rssi_stat.OFDM_pkt != 0) + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), OFDM_pkt = (( %d )), CCK_pkt = (( %d ))\n", + UndecoratedSmoothedPWDB, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.CCK_pkt)); + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + phydm_ra_rssi_rpt_wk(pDM_Odm); + #endif + } + + + /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + if (pPktinfo->StationID == 0) { + /**/ + pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + } + #endif + + //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); + //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", + // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); + + } + + } +} + + +#if(ODM_IC_11N_SERIES_SUPPORT ==1) +// +// Endianness before calling this API +// +VOID +ODM_PhyStatusQuery_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); + odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); +} +#endif + + +// +// Endianness before calling this API +// +#if ODM_IC_11AC_SERIES_SUPPORT + +VOID +ODM_PhyStatusQuery_JaguarSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + odm_RxPhyStatusJaguarSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); + odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*phydm_sbd_check(pDM_Odm);*/ + #endif +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +phydm_normal_driver_rx_sniffer( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN PRT_RFD_STATUS pRtRfdStatus, + IN pu1Byte pDrvInfo, + IN u1Byte PHYStatus + ) +{ + #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) + u4Byte *pMsg; + u2Byte seq_num; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if (pRtRfdStatus->PacketReportType != NORMAL_RX) + return; + + if (!pDM_Odm->bLinked) { + if (pRtRfdStatus->bHwError) + return; + } + + if (!(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) + return; + + if (PHYStatus == TRUE) { + + if ((pDM_Odm->rx_pkt_type == Type_BlockAck) || (pDM_Odm->rx_pkt_type == Type_RTS) || (pDM_Odm->rx_pkt_type == Type_CTS)) + seq_num = 0; + else + seq_num = pRtRfdStatus->Seq_Num; + + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s", + seq_num, + /*pRtRfdStatus->MacID,*/ + ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), + pRtRfdStatus->DataRate, + pRtRfdStatus->Length, + ((pRtRfdStatus->BandWidth == 0) ? "20M":((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), + ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") + )); + + if (pDM_Odm->rx_pkt_type == Type_Asoc_Req) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Asoc_Rsp) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Probe_Req) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Probe_Rsp) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Deauth) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Beacon) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_BlockAckReq) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_RTS) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_CTS) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Ack) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_BlockAck) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Data) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_Data_Ack) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); + /**/ + } else if (pDM_Odm->rx_pkt_type == Type_QosData) { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); + /**/ + } else { + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", pDM_Odm->rx_pkt_type)); + /**/ + } + + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", + pDM_Odm->RSSI_A, + pDM_Odm->RSSI_B, + pDM_Odm->RSSI_C, + pDM_Odm->RSSI_D + )); + + pMsg = (pu4Byte)pDrvInfo; + + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", + pMsg[6], pMsg[5], pMsg[4], pMsg[3], pMsg[2], pMsg[1], pMsg[1])); + } else { + + ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s\n", + pRtRfdStatus->Seq_Num, + /*pRtRfdStatus->MacID,*/ + ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), + pRtRfdStatus->DataRate, + pRtRfdStatus->Length, + ((pRtRfdStatus->BandWidth == 0) ? "20M" : ((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), + ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") + )); + } + + + #endif +} +#endif + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) { + phydm_RxPhyStatusNewType(pDM_Odm, pPhyStatus, pPktinfo, pPhyInfo); + return; + } +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + ODM_PhyStatusQuery_JaguarSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); +#endif + +#if ODM_IC_11N_SERIES_SUPPORT + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES ) + ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); +#endif +} + +// For future use. +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ) +{ + // 2011/10/19 Driver team will handle in the future. + +} + + +// +// If you want to add a new IC, Please follow below template and generate a new one. +// +// + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigRFWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + +//1 AP doesn't use PHYDM power tracking table in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A){ + READ_AND_CONFIG_MP(8812A,_RadioA); + } + else if(eRFPath == ODM_RF_PATH_B){ + READ_AND_CONFIG_MP(8812A,_RadioB); + } + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + if ((pHalData->EEPROMSVID == 0x17AA && pHalData->EEPROMSMID == 0xA811) || + (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0xA812) || + (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0x8812)) + READ_AND_CONFIG_MP(8812A,_TXPWR_LMT_HM812A03); + else + #endif + READ_AND_CONFIG_MP(8812A,_TXPWR_LMT); + } + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A){ + READ_AND_CONFIG_MP(8821A,_RadioA); + } + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (pDM_Odm->ExtPA5G || pDM_Odm->ExtLNA5G) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_FEM); + else + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_IPA); + } + else { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pMgntInfo->CustomerID == RT_CID_8821AE_ASUS_MB) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_8mm); + else if (pMgntInfo->CustomerID == RT_CID_ASUS_NB) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_5mm); + else + #endif + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8192E,_RadioA); + else if(eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8192E,_RadioB); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if ((pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8192) || + (pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8193)) + READ_AND_CONFIG_MP(8192E, _TXPWR_LMT_8192E_SAR_5mm); + else +#endif + READ_AND_CONFIG_MP(8192E, _TXPWR_LMT); + } + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8723D, _RadioA); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723D, _TXPWR_LMT); + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188E,_RadioA); + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188E,_TXPWR_LMT); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + if (ConfigType == CONFIG_RF_RADIO) + READ_AND_CONFIG_MP(8723B, _RadioA); + else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723B, _TXPWR_LMT); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8814A,_RadioA); + else if(eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8814A,_RadioB); + else if(eRFPath == ODM_RF_PATH_C) + READ_AND_CONFIG_MP(8814A,_RadioC); + else if(eRFPath == ODM_RF_PATH_D) + READ_AND_CONFIG_MP(8814A,_RadioD); + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8814A,_TXPWR_LMT); + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8703B, _RadioA); + } + } +#endif +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188F, _RadioA); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188F, _TXPWR_LMT); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8822B, _RadioA); + else if (eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8822B, _RadioB); + } + } +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8197F, _RadioA); + else if (eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8197F, _RadioB); + } + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_TC(8821C, _RadioA); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_TC(8821C, _TXPWR_LMT); + } +#endif + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigRFWithTxPwrTrackHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + + +//1 AP doesn't use PHYDM power tracking table in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if RTL8821A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8821) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_SDIO); + } +#endif +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_RFE3); + else + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_USB); + } + + } +#endif +#if RTL8192E_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_SDIO); + } +#endif +#if RTL8723D_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723D, _TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723D, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723D, _TxPowerTrack_SDIO); + + READ_AND_CONFIG_MP(8723D, _TxXtalTrack); + } +#endif +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if (PHY_QueryMacReg(pDM_Odm->Adapter, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE_ICUT); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB_ICUT); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO_ICUT); + } else { /*else 0xF0[15:12] < 8, TSMC*/ + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO); + } + + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if RTL8723B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723B, _TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723B, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723B, _TxPowerTrack_SDIO); + } +#endif +#if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(pDM_Odm->RFEType == 0) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type0); + else if(pDM_Odm->RFEType == 1) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type1); + else if(pDM_Odm->RFEType == 2) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type2); + else if(pDM_Odm->RFEType == 3) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type3); + else if(pDM_Odm->RFEType == 4) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type4); + else if(pDM_Odm->RFEType == 5) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type5); + else if(pDM_Odm->RFEType == 6) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type6); + else if(pDM_Odm->RFEType == 7) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type7); + else if(pDM_Odm->RFEType == 8) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type8); + else if(pDM_Odm->RFEType == 9) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type9); + else + READ_AND_CONFIG_MP(8814A,_TxPowerTrack); + + READ_AND_CONFIG_MP(8814A, _TxPowerTSSI); + } +#endif +#if RTL8703B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8703B, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8703B, _TxPowerTrack_SDIO); + + READ_AND_CONFIG_MP(8703B, _TxXtalTrack); + } +#endif + +#if RTL8188F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188F, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188F, _TxPowerTrack_SDIO); + } +#endif + +#if RTL8822B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + if (pDM_Odm->RFEType == 0) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type0); + else if (pDM_Odm->RFEType == 1) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type1); + else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_Type3_Type5); + else if (pDM_Odm->RFEType == 6) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type6); + else if (pDM_Odm->RFEType == 7) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type7); + else if (pDM_Odm->RFEType == 8) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type8); + else if (pDM_Odm->RFEType == 9) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type9); + else if (pDM_Odm->RFEType == 10) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type10); + else if (pDM_Odm->RFEType == 11) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type11); + else if (pDM_Odm->RFEType == 12) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type12); + else if (pDM_Odm->RFEType == 13) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type13); + else if (pDM_Odm->RFEType == 14) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type14); + else + READ_AND_CONFIG_MP(8822B, _TxPowerTrack); + } +#endif + +#if RTL8197F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8197F) { + if (pDM_Odm->RFEType == 0) + READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type0); + else if (pDM_Odm->RFEType == 1) + READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type1); + else + READ_AND_CONFIG_MP(8197F, _TxPowerTrack); + } +#endif + +#if RTL8821C_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8821C) + READ_AND_CONFIG_TC(8821C, _TxPowerTrack); +#endif + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#endif + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8812A, _PHY_REG); + } else if (ConfigType == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8812A, _AGC_TAB); + } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { + if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_ASUS); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + else if (pMgntInfo->CustomerID == RT_CID_WNC_NEC && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_NEC); + #if RT_PLATFORM == PLATFORM_MACOSX + /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ + else if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) + READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_DNI); + /* TP-Link T4UH, Isaiah 2015-03-16*/ + else if (pMgntInfo->CustomerID == RT_CID_TPLINK_HPWR) { + DbgPrint("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); + READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_TPLINK); + } + #endif + #endif + else + READ_AND_CONFIG_MP(8812A, _PHY_REG_PG); + } + else if(ConfigType == CONFIG_BB_PHY_REG_MP){ + READ_AND_CONFIG_MP(8812A,_PHY_REG_MP); + } + else if(ConfigType == CONFIG_BB_AGC_TAB_DIFF) + { + if ((36 <= *pDM_Odm->pChannel) && (*pDM_Odm->pChannel <= 64)) + AGC_DIFF_CONFIG_MP(8812A,LB); + else if (100 <= *pDM_Odm->pChannel) + AGC_DIFF_CONFIG_MP(8812A,HB); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n")); + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8821A, _PHY_REG); + } else if (ConfigType == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8821A, _AGC_TAB); + } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if ((pHalData->EEPROMSVID == 0x1043 && pHalData->EEPROMSMID == 0x207F)) + READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_E202SA); + else + #endif + #if (RT_PLATFORM == PLATFORM_MACOSX) + /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ + if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) { + /*{1024} for BUFFALO power by rate table. (JP/US)*/ + if (pMgntInfo->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) + READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_US); + else + READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_JP); + } else + #endif + #endif + READ_AND_CONFIG_MP(8821A,_PHY_REG_PG); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n")); + } +#endif +#if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8192E,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8192E,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8192E,_PHY_REG_PG); + } + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723D, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723D, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8723D, _PHY_REG_PG); + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188E,_PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188E,_AGC_TAB); + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188E,_PHY_REG_PG); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8723B, _PHY_REG); + } else if (ConfigType == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8723B, _AGC_TAB); + } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { + READ_AND_CONFIG_MP(8723B, _PHY_REG_PG); + } + } +#endif +#if (RTL8814A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8814A,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8814A,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8814A,_PHY_REG_PG); + }else if(ConfigType == CONFIG_BB_PHY_REG_MP){ + READ_AND_CONFIG_MP(8814A,_PHY_REG_MP); + } + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8703B, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8703B, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8703B, _PHY_REG_PG); + } +#endif +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188F, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188F, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188F, _PHY_REG_PG); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8822B, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8822B, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8822B, _PHY_REG_PG); + /*else if (ConfigType == CONFIG_BB_PHY_REG_MP)*/ + /*READ_AND_CONFIG_MP(8822B, _PHY_REG_MP);*/ + } +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F) { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8197F, _PHY_REG); + if (pDM_Odm->CutVersion == ODM_CUT_A) + phydm_phypara_a_cut(pDM_Odm); + } else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8197F, _AGC_TAB); +/* else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8197F, _PHY_REG_PG); + else if(ConfigType == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8197F, _PHY_REG_MP); */ + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_TC(8821C, _PHY_REG); + } else if (ConfigType == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_TC(8821C, _AGC_TAB); + } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { + READ_AND_CONFIG_TC(8821C, _PHY_REG_PG); + } + } +#endif + +#if (RTL8195A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8195A) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8195A, _PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG(8195A, _AGC_TAB); + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8195A, _PHY_REG_PG); + } +#endif + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigMACWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812){ + READ_AND_CONFIG_MP(8812A, _MAC_REG); + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821){ + READ_AND_CONFIG_MP(8821A, _MAC_REG); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n")); + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E){ + READ_AND_CONFIG_MP(8192E, _MAC_REG); + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723D) + READ_AND_CONFIG_MP(8723D, _MAC_REG); +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E){ + READ_AND_CONFIG_MP(8188E, _MAC_REG); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + READ_AND_CONFIG_MP(8723B, _MAC_REG); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A){ + READ_AND_CONFIG_MP(8814A, _MAC_REG); + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) + READ_AND_CONFIG_MP(8703B, _MAC_REG); +#endif +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + READ_AND_CONFIG_MP(8188F, _MAC_REG); +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822B, _MAC_REG); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F) + READ_AND_CONFIG_MP(8197F, _MAC_REG); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + READ_AND_CONFIG_TC(8821C, _MAC_REG); +#endif + +#if (RTL8195A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8195A) + READ_AND_CONFIG_MP(8195A, _MAC_REG); +#endif + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigFWWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_FW_Config_Type ConfigType, + OUT u1Byte *pFirmware, + OUT u4Byte *pSize + ) +{ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + #ifdef CONFIG_SFW_SUPPORTED + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188E_T,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); + else if(ConfigType == CONFIG_FW_NIC_2) + READ_FIRMWARE_MP(8188E_S,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN_2) + READ_FIRMWARE_MP(8188E_S,_FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + if (ConfigType == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188E_T,_FW_AP); + else if (ConfigType == CONFIG_FW_AP_2) + READ_FIRMWARE_MP(8188E_S,_FW_AP); + #endif //CONFIG_AP_WOWLAN + #else + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188E_T,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188E_T,_FW_AP); + #endif //CONFIG_AP_WOWLAN + #endif + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) + { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8723B,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8723B,_FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE(8723B,_FW_AP_WoWLAN); + #endif + + } +#endif //#if (RTL8723B_SUPPORT == 1) +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8812A,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8812A,_FW_WoWLAN); + else if (ConfigType == CONFIG_FW_BT) + READ_FIRMWARE_MP(8812A,_FW_NIC_BT); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE(8812A,_FW_AP); + #endif + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821){ + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8821A,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8821A,_FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE_MP(8821A , _FW_AP); + #endif /*CONFIG_AP_WOWLAN*/ + else if (ConfigType == CONFIG_FW_BT) + READ_FIRMWARE_MP(8821A,_FW_NIC_BT); + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E) + { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8192E,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8192E,_FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE_MP(8192E,_FW_AP); + #endif + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723D) { + if (ConfigType == CONFIG_FW_NIC) { + READ_FIRMWARE_MP(8723D, _FW_NIC); + } else if (ConfigType == CONFIG_FW_WoWLAN) { + READ_FIRMWARE_MP(8723D, _FW_WoWLAN); + } + } +#endif +/*#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8814A, _FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8814A, _FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE_MP(8814A, _FW_AP); + #endif + } +#endif */ + +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8814A,_FW_NIC); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE_MP(8814A,_FW_AP); + #endif + } +#endif + +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8703B, _FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8703B, _FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE(8703B, _FW_AP_WoWLAN); + #endif + } +#endif + +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188F, _FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8188F, _FW_WoWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188F, _FW_AP); + #endif + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8822B,_FW_NIC); + else if (ConfigType == CONFIG_FW_WoWLAN) + READ_FIRMWARE_MP(8822B, _FW_WOWLAN); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE(8822B,_FW_AP); + #endif + } +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F) { + if (ConfigType == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8197F, _FW_NIC); + #ifdef CONFIG_AP_WOWLAN + else if (ConfigType == CONFIG_FW_AP_WoWLAN) + READ_FIRMWARE(8197F , _FW_AP); + #endif + } +#endif + +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + return HAL_STATUS_SUCCESS; +} + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte Version=0; + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) + Version = GET_VERSION_MP(8821A,_MAC_REG); +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E) + Version = GET_VERSION_MP(8192E,_MAC_REG); +#endif +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + Version = GET_VERSION_MP(8812A,_MAC_REG); +#endif +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723D) + Version = GET_VERSION_MP(8723D, _MAC_REG); +#endif +#endif //(DM_ODM_SUPPORT_TYPE != ODM_AP) + +/*1 All platforms support*/ +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + Version = GET_VERSION_MP(8188E,_MAC_REG); +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) + Version = GET_VERSION_MP(8723B, _MAC_REG); +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + Version = GET_VERSION_MP(8814A,_MAC_REG); +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) + Version = GET_VERSION_MP(8703B, _MAC_REG); +#endif +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + Version = GET_VERSION_MP(8188F, _MAC_REG); +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + Version = GET_VERSION_MP(8822B, _MAC_REG); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8197F) + Version = GET_VERSION_MP(8197F, _MAC_REG); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + Version = GET_VERSION_TC(8821C, _MAC_REG); +#endif + + return Version; +} + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +/* For 8822B only!! need to move to FW finally */ +/*==============================================*/ + +VOID +phydm_ResetPhyInfo( + IN PDM_ODM_T pPhydm, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + pPhyInfo->RxPWDBAll = 0; + pPhyInfo->SignalQuality = 0; + pPhyInfo->BandWidth = 0; + pPhyInfo->RxCount = 0; + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalQuality, 0 , 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalStrength, 0, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxSNR, 0, 4); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPower = -110; + pPhyInfo->RecvSignalPower = -110; + pPhyInfo->BTRxRSSIPercentage = 0; + pPhyInfo->SignalStrength = 0; + pPhyInfo->btCoexPwrAdjust = 0; + pPhyInfo->channel = 0; + pPhyInfo->bMuPacket = 0; + pPhyInfo->bBeamformed = 0; + pPhyInfo->rxsc = 0; + ODM_Memory_Set(pPhydm, pPhyInfo->RxPwr, -110, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOEVMdbm, 0, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_short, 0, 8); + ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_tail, 0, 8); +#endif +} + +VOID +phydm_SetPerPathPhyInfo( + IN u1Byte RxPath, + IN s1Byte RxPwr, + IN s1Byte RxEVM, + IN s1Byte Cfo_tail, + IN s1Byte RxSNR, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + u1Byte EVMdBm = 0; + u1Byte EVMPercentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (RxEVM < 0) { + /* Calculate EVM in dBm */ + EVMdBm = ((u1Byte)(0 - RxEVM) >> 1); + + /* Calculate EVM in percentage */ + if (EVMdBm >= 33) + EVMPercentage = 100; + else + EVMPercentage = (EVMdBm << 1) + (EVMdBm); + } + + if (EVMdBm == 64) + EVMdBm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[RxPath] = RxPwr; + pPhyInfo->RxMIMOEVMdbm[RxPath] = EVMdBm; + + /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ + pPhyInfo->Cfo_tail[RxPath] = Cfo_tail; + pPhyInfo->Cfo_tail[RxPath] = ((pPhyInfo->Cfo_tail[RxPath] << 5) + (pPhyInfo->Cfo_tail[RxPath] << 2) + + (pPhyInfo->Cfo_tail[RxPath] << 1) + (pPhyInfo->Cfo_tail[RxPath])) >> 9; +#endif + + pPhyInfo->RxMIMOSignalStrength[RxPath] = odm_QueryRxPwrPercentage(RxPwr); + pPhyInfo->RxMIMOSignalQuality[RxPath] = EVMPercentage; + pPhyInfo->RxSNR[RxPath] = RxSNR >> 1; + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("Path (%d)--------\n", RxPath); + DbgPrint("RxPwr = %d, Signal strength = %d\n", pPhyInfo->RxPwr[RxPath], pPhyInfo->RxMIMOSignalStrength[RxPath]); + DbgPrint("EVMdBm = %d, Signal quality = %d\n", pPhyInfo->RxMIMOEVMdbm[RxPath], pPhyInfo->RxMIMOSignalQuality[RxPath]); + DbgPrint("CFO = %d, SNR = %d\n", pPhyInfo->Cfo_tail[RxPath], pPhyInfo->RxSNR[RxPath]); + } +*/ +} + +VOID +phydm_SetCommonPhyInfo( + IN s1Byte RxPower, + IN u1Byte channel, + IN BOOLEAN bBeamformed, + IN BOOLEAN bMuPacket, + IN u1Byte bandwidth, + IN u1Byte signalQuality, + IN u1Byte rxsc, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPower = RxPower; /* RSSI in dB */ + pPhyInfo->RecvSignalPower = RxPower; /* RSSI in dB */ + pPhyInfo->channel = channel; /* channel number */ + pPhyInfo->bBeamformed = bBeamformed; /* apply BF */ + pPhyInfo->bMuPacket = bMuPacket; /* MU packet */ + pPhyInfo->rxsc = rxsc; +#endif + pPhyInfo->RxPWDBAll = odm_QueryRxPwrPercentage(RxPower); /* RSSI in percentage */ + pPhyInfo->SignalQuality = signalQuality; /* signal quality */ + pPhyInfo->BandWidth = bandwidth; /* bandwidth */ + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("RxPWDBAll = %d, RxPower = %d, RecvSignalPower = %d\n", pPhyInfo->RxPWDBAll, pPhyInfo->RxPower, pPhyInfo->RecvSignalPower); + DbgPrint("SignalQuality = %d\n", pPhyInfo->SignalQuality); + DbgPrint("bBeamformed = %d, bMuPacket = %d, RxCount = %d\n", pPhyInfo->bBeamformed, pPhyInfo->bMuPacket, pPhyInfo->RxCount + 1); + DbgPrint("channel = %d, rxsc = %d, BandWidth = %d\n", channel, rxsc, bandwidth); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType0( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + /* Type 0 is used for cck packet */ + + PPHY_STATUS_RPT_JAGUAR2_TYPE0 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE0)pPhyStatus; + u1Byte i, SQ = 0; + s1Byte RxPower = pPhyStaRpt->pwdb - 110; + + /* Calculate Signal Quality*/ + if (pPktinfo->bPacketMatchBSSID) { + if (pPhyStaRpt->signal_quality >= 64) + SQ = 0; + else if (pPhyStaRpt->signal_quality <= 20) + SQ = 100; + else { + /* mapping to 2~99% */ + SQ = 64 - pPhyStaRpt->signal_quality; + SQ = ((SQ << 3) + SQ) >> 2; + } + } + + /* Modify CCK PWDB if old AGC */ + if (pDM_Odm->cck_new_agc == FALSE) { + u1Byte LNA_idx, VGA_idx; + +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + LNA_idx = pPhyStaRpt->lna_l; + else +#endif + LNA_idx = ((pPhyStaRpt->lna_h << 3) | pPhyStaRpt->lna_l); + VGA_idx = pPhyStaRpt->vga; + +#if (RTL8723D_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8723D) + RxPower = odm_CCKRSSI_8723D(LNA_idx, VGA_idx); +#endif +#if (RTL8822B_SUPPORT == 1) + /* Need to do !! */ + /*if (pDM_Odm->SupportICType & ODM_RTL8822B) */ + /*RxPower = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ +#endif +#if (RTL8197F_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8197F) + RxPower = phydm_cck_rssi_convert(pDM_Odm, LNA_idx, VGA_idx); +#endif + } + + /* Update CCK packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + + /* Update Common information */ + phydm_SetCommonPhyInfo(RxPower, pPhyStaRpt->channel, FALSE, + FALSE, ODM_BW20M, SQ, pPhyStaRpt->rxsc, pPhyInfo); + + /* Update CCK pwdb */ + phydm_SetPerPathPhyInfo(ODM_RF_PATH_A, RxPower, 0, 0, 0, pPhyInfo); /* Update per-path information */ + + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; + pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", pPhyStaRpt->pwdb, pPhyStaRpt->gain, pPhyStaRpt->trsw); + DbgPrint("channel = %d, band = %d, rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->rxsc); + DbgPrint("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", pPhyStaRpt->agc_table, pPhyStaRpt->agc_rpt, pPhyStaRpt->bb_power); + DbgPrint("length = %d, SQ = %d\n", pPhyStaRpt->length, pPhyStaRpt->signal_quality); + DbgPrint("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); + DbgPrint("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2); + DbgPrint("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); + DbgPrint("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7, pPhyStaRpt->rsvd_8); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType1( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + /* Type 1 is used for ofdm packet */ + + PPHY_STATUS_RPT_JAGUAR2_TYPE1 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE1)pPhyStatus; + s1Byte rx_pwr_db = -120; + u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; + BOOLEAN bMU; + u1Byte num_ss; + + /* Update OFDM packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pDM_Odm->RXAntStatus & BIT(i)) { + s1Byte rx_path_pwr_db; + + /* RX path counter */ + RxCount++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ + /* EVM report is reported by stream, not path */ + rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, pPhyStaRpt->rxevm[RxCount - 1], + pPhyStaRpt->cfo_tail[i], pPhyStaRpt->rxsnr[i], pPhyInfo); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (RxCount > 0) + pPhyInfo->RxCount = RxCount - 1; + + /* Check if MU packet or not */ + if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { + bMU = TRUE; + pDM_Odm->PhyDbgInfo.NumQryMuPkt++; + } else + bMU = FALSE; + + /* Count BF packet */ + pDM_Odm->PhyDbgInfo.NumQryBfPkt = pDM_Odm->PhyDbgInfo.NumQryBfPkt + pPhyStaRpt->beamformed; + + /* Check sub-channel */ + if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) + rxsc = pPhyStaRpt->l_rxsc; + else + rxsc = pPhyStaRpt->ht_rxsc; + + /* Check RX bandwidth */ + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = pPhyStaRpt->rf_mode; + } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { + if (pPhyStaRpt->rf_mode == 0) + bw = ODM_BW20M; + else if ((rxsc == 1) || (rxsc == 2)) + bw = ODM_BW20M; + else + bw = ODM_BW40M; + } + + /* Update packet information */ + phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, + bMU, bw, odm_EVMdbToPercentage(pPhyStaRpt->rxevm[0]), rxsc, pPhyInfo); + + num_ss =phydm_rate_to_num_ss(pDM_Odm, pPktinfo->DataRate ); + + ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfo_tail, num_ss); + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; + pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; + + if (pPktinfo->bPacketMatchBSSID) { +/* + DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc, pPhyStaRpt->rf_mode); + DbgPrint("Antidx A = %d, B = %d, C = %d, D = %d\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); + DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); + DbgPrint("EVM A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1], pPhyStaRpt->rxevm[2], pPhyStaRpt->rxevm[3]); + DbgPrint("SNR A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxsnr[0], pPhyStaRpt->rxsnr[1], pPhyStaRpt->rxsnr[2], pPhyStaRpt->rxsnr[3]); + DbgPrint("CFO A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->cfo_tail[0], pPhyStaRpt->cfo_tail[1], pPhyStaRpt->cfo_tail[2], pPhyStaRpt->cfo_tail[3]); + DbgPrint("paid = %d, gid = %d, length = %d\n", (pPhyStaRpt->paid + (pPhyStaRpt->paid_msb<<8)), pPhyStaRpt->gid, pPhyStaRpt->lsig_length); + DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); + DbgPrint("NBI: %d, pos: %d\n", pPhyStaRpt->nb_intf_flag, (pPhyStaRpt->intf_pos + (pPhyStaRpt->intf_pos_msb<<8))); + DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); +*/ + if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { + if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) + pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[pPktinfo->DataRate - 0x2C]++; + } else { + if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) + pDM_Odm->PhyDbgInfo.NumQryVhtPkt[pPktinfo->DataRate - 0x2C]++; + } + } +/* + DbgPrint("phydm_GetRxPhyStatusType1 pPktinfo->bPacketMatchBSSID = %d\n", pPktinfo->bPacketMatchBSSID); + DbgPrint("pPktinfo->DataRate = 0x%x\n", pPktinfo->DataRate); +*/ +} + +VOID +phydm_GetRxPhyStatusType2( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + PPHY_STATUS_RPT_JAGUAR2_TYPE2 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE2)pPhyStatus; + s1Byte rx_pwr_db = -120; + u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; + + /* Update OFDM packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pDM_Odm->RXAntStatus & BIT(i)) { + s1Byte rx_path_pwr_db; + + /* RX path counter */ + RxCount++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ +#if (RTL8197F_SUPPORT == 1) + if ((pDM_Odm->SupportICType & ODM_RTL8197F) && (pPhyStaRpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ + + if (i == ODM_RF_PATH_A) { + rx_path_pwr_db = (pPhyStaRpt->gain_a)<<1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else if (i == ODM_RF_PATH_B) { + rx_path_pwr_db = (pPhyStaRpt->gain_b)<<1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else + rx_path_pwr_db = 0; + } else +#endif + rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + + phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, 0, 0, 0, pPhyInfo); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (RxCount > 0) + pPhyInfo->RxCount = RxCount - 1; + + /* Check RX sub-channel */ + if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) + rxsc = pPhyStaRpt->l_rxsc; + else + rxsc = pPhyStaRpt->ht_rxsc; + + /* Check RX bandwidth */ + /* the BW information of sc=0 is useless, because there is no information of RF mode*/ + + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = ODM_BW20M; + } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { + if (rxsc == 3) + bw = ODM_BW40M; + else if ((rxsc == 1) || (rxsc == 2)) + bw = ODM_BW20M; + else + bw = ODM_BW20M; + } + + /* Update packet information */ + phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, + FALSE, bw, 0, rxsc, pPhyInfo); + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc); + DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); + DbgPrint("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->agc_table_a, pPhyStaRpt->agc_table_b, pPhyStaRpt->agc_table_c, pPhyStaRpt->agc_table_d); + DbgPrint("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->gain_a, pPhyStaRpt->gain_b, pPhyStaRpt->gain_c, pPhyStaRpt->gain_d); + DbgPrint("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->trsw_a, pPhyStaRpt->trsw_b, pPhyStaRpt->trsw_c, pPhyStaRpt->trsw_d); + DbgPrint("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->aagc_step_a, pPhyStaRpt->aagc_step_b, pPhyStaRpt->aagc_step_c, pPhyStaRpt->aagc_step_d); + DbgPrint("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->ht_aagc_gain[0], pPhyStaRpt->ht_aagc_gain[1], pPhyStaRpt->ht_aagc_gain[2], pPhyStaRpt->ht_aagc_gain[3]); + DbgPrint("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->dagc_gain[0], pPhyStaRpt->dagc_gain[1], pPhyStaRpt->dagc_gain[2], pPhyStaRpt->dagc_gain[3]); + DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); + DbgPrint("counter: %d, syn_count: %d\n", pPhyStaRpt->counter, pPhyStaRpt->syn_count); + DbgPrint("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", pPhyStaRpt->cnt_cca2agc_rdy, pPhyStaRpt->cnt_pw2cca, pPhyStaRpt->shift_l_map); + DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4); + DbgPrint("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", pPhyStaRpt->rsvd_5, pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType5( + IN pu1Byte pPhyStatus +) +{ +/* + DbgPrint("DW0: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 3), *(pPhyStatus + 2), *(pPhyStatus + 1), *(pPhyStatus + 0)); + DbgPrint("DW1: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 7), *(pPhyStatus + 6), *(pPhyStatus + 5), *(pPhyStatus + 4)); + DbgPrint("DW2: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 11), *(pPhyStatus + 10), *(pPhyStatus + 9), *(pPhyStatus + 8)); + DbgPrint("DW3: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 15), *(pPhyStatus + 14), *(pPhyStatus + 13), *(pPhyStatus + 12)); + DbgPrint("DW4: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 19), *(pPhyStatus + 18), *(pPhyStatus + 17), *(pPhyStatus + 16)); + DbgPrint("DW5: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 23), *(pPhyStatus + 22), *(pPhyStatus + 21), *(pPhyStatus + 20)); + DbgPrint("DW6: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 27), *(pPhyStatus + 26), *(pPhyStatus + 25), *(pPhyStatus + 24)); +*/ +} + +VOID +phydm_Process_RSSIForDMNewType( + IN OUT PDM_ODM_T pDM_Odm, + IN PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + s4Byte UndecoratedSmoothedPWDB, AccumulatePWDB; + u4Byte RSSI_Ave; + u1Byte i; + PSTA_INFO_T pEntry; + u1Byte scaling_factor = 4; + + if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + + if (!IS_STA_VALID(pEntry)) + return; + + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + + if (pPktinfo->bPacketBeacon) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; + + if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { + u4Byte RSSI_linear = 0; + + pDM_Odm->RxRate = pPktinfo->DataRate; + UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + AccumulatePWDB = pDM_Odm->AccumulatePWDB[pPktinfo->StationID]; + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; + pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pPhyInfo->RxMIMOSignalStrength[i] != 0) + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[i]); + } + + switch (pPhyInfo->RxCount + 1) { + case 2: + RSSI_linear = (RSSI_linear >> 1); + break; + case 3: + RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ + break; + case 4: + RSSI_linear = (RSSI_linear >> 2); + break; + } + RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + + if (UndecoratedSmoothedPWDB <= 0) { + AccumulatePWDB = (pPhyInfo->RxPWDBAll << scaling_factor); + UndecoratedSmoothedPWDB = pPhyInfo->RxPWDBAll; + } else { + AccumulatePWDB = AccumulatePWDB - (AccumulatePWDB>>scaling_factor) + RSSI_Ave; + UndecoratedSmoothedPWDB = (AccumulatePWDB + (1<<(scaling_factor - 1)))>>scaling_factor; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == -1) + phydm_ra_rssi_rpt_wk(pDM_Odm); +#endif + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + pDM_Odm->AccumulatePWDB[pPktinfo->StationID] = AccumulatePWDB; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (pPktinfo->StationID == 0) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + + pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + } +#endif + } +} + +VOID +phydm_RxPhyStatusNewType( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + u1Byte phy_status_type = (*pPhyStatus & 0xf); + + /*DbgPrint("phydm_RxPhyStatusNewType================> (page: %d)\n", phy_status_type);*/ + + /* Memory reset */ + phydm_ResetPhyInfo(pPhydm, pPhyInfo); + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: + { + phydm_GetRxPhyStatusType0(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } + case 1: + { + phydm_GetRxPhyStatusType1(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } + case 2: + { + phydm_GetRxPhyStatusType2(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } +/* + case 5: + { + phydm_GetRxPhyStatusType5(pPhyStatus); + return; + } +*/ + default: + return; + } + + #if ((RTL8723D_SUPPORT == 1)||(RTL8197F_SUPPORT == 1)) + if (pPhydm->SupportAbility & ODM_BB_ANT_DIV) { + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_Process_RSSIForAntDiv(pPhydm, pPhyInfo, pPktinfo); + #endif + } + #endif + /* Update signal strength to UI, and pPhyInfo->RxPWDBAll is the maximum RSSI of all path */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pPhyInfo->SignalStrength = SignalScaleProc(pPhydm->Adapter, pPhyInfo->RxPWDBAll, FALSE, FALSE); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pPhydm, pPhyInfo->RxPWDBAll)); +#endif + + /* Calculate average RSSI and smoothed RSSI */ + phydm_Process_RSSIForDMNewType(pPhydm, pPhyInfo, pPktinfo); + +} +/*==============================================*/ +#endif + +u4Byte +query_phydm_trx_capability( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32 = 0xFFFFFFFF; + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(pDM_Odm); + #endif + + return value32; +} + +u4Byte +query_phydm_stbc_capability( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32 = 0xFFFFFFFF; + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(pDM_Odm); + #endif + + return value32; +} + +u4Byte +query_phydm_ldpc_capability( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32 = 0xFFFFFFFF; + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(pDM_Odm); + #endif + + return value32; +} + +u4Byte +query_phydm_txbf_parameters( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32 = 0xFFFFFFFF; + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(pDM_Odm); + #endif + + return value32; +} + +u4Byte +query_phydm_txbf_capability( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value32 = 0xFFFFFFFF; + + #if (RTL8821C_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(pDM_Odm); + #endif + + return value32; +} diff --git a/package/kernel/rtl8192cd/phydm/phydm_hwconfig.h b/package/kernel/rtl8192cd/phydm/phydm_hwconfig.h index 960c1b93560..bcb961b2f99 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_hwconfig.h +++ b/package/kernel/rtl8192cd/phydm/phydm_hwconfig.h @@ -1,573 +1,573 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __HALHWOUTSRC_H__ -#define __HALHWOUTSRC_H__ - - -/*--------------------------Define -------------------------------------------*/ -#define CCK_RSSI_INIT_COUNT 5 - -#define RA_RSSI_STATE_INIT 0 -#define RA_RSSI_STATE_SEND 1 -#define RA_RSSI_STATE_HOLD 2 - -#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) -/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ - -#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ - sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) -#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ - sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) - -#define AGC_DIFF_CONFIG(ic, band) do {\ - if (pDM_Odm->bIsMPChip)\ - AGC_DIFF_CONFIG_MP(ic,band);\ - else\ - AGC_DIFF_CONFIG_TC(ic,band);\ - } while(0) - - -//============================================================ -// structure and define -//============================================================ - -__PACK typedef struct _Phy_Rx_AGC_Info -{ - #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain:7,trsw:1; - #else - u1Byte trsw:1,gain:7; - #endif -} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T; - -__PACK typedef struct _Phy_Status_Rpt_8192cd { - PHY_RX_AGC_INFO_T path_agc[2]; - u1Byte ch_corr[2]; - u1Byte cck_sig_qual_ofdm_pwdb_all; - u1Byte cck_agc_rpt_ofdm_cfosho_a; - u1Byte cck_rpt_b_ofdm_cfosho_b; - u1Byte rsvd_1;/*ch_corr_msb;*/ - u1Byte noise_power_db_msb; - s1Byte path_cfotail[2]; - u1Byte pcts_mask[2]; - s1Byte stream_rxevm[2]; - u1Byte path_rxsnr[2]; - u1Byte noise_power_db_lsb; - u1Byte rsvd_2[3]; - u1Byte stream_csi[2]; - u1Byte stream_target_csi[2]; - s1Byte sig_evm; - u1Byte rsvd_3; - -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ - u1Byte sgi_en: 1; - u1Byte rxsc: 2; - u1Byte idle_long: 1; - u1Byte r_ant_train_en: 1; - u1Byte ant_sel_b: 1; - u1Byte ant_sel: 1; -#else /*_BIG_ENDIAN_ */ - u1Byte ant_sel: 1; - u1Byte ant_sel_b: 1; - u1Byte r_ant_train_en: 1; - u1Byte idle_long: 1; - u1Byte rxsc: 2; - u1Byte sgi_en: 1; - u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ -#endif -} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T; - - -typedef struct _Phy_Status_Rpt_8812 { -/* DWORD 0*/ - u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ - u1Byte chl_num_LSB; /*channel number[7:0]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte chl_num_MSB: 2; /*channel number[9:8]*/ - u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/ - u1Byte r_RFMOD: 2; /*RF mode[1:0]*/ -#else /*_BIG_ENDIAN_ */ - u1Byte r_RFMOD: 2; - u1Byte sub_chnl: 4; - u1Byte chl_num_MSB: 2; -#endif - -/* DWORD 1*/ - u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/ - s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - /*this should be checked again because the definition of 8812 and 8814 is different*/ -/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ -/* u1Byte cck_rx_path:4; cck rx path[3:0]*/ - u1Byte resvd_0: 6; - u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ -#else /*_BIG_ENDIAN_*/ - u1Byte bt_RF_ch_MSB: 2; - u1Byte resvd_0: 6; -#endif - -/* DWORD 2*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ - u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ - u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ -#else /*_BIG_ENDIAN_ */ - u1Byte bt_RF_ch_LSB: 6; - u1Byte ant_div_sw_b: 1; - u1Byte ant_div_sw_a: 1; -#endif - s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ - u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ - u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ - -/* DWORD 3*/ - s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ - s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ - -/* DWORD 4*/ - u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ - u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/ - u1Byte resvd_1: 1; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u1Byte resvd_1: 1; - u1Byte pcts_rpt_valid: 1; - u1Byte PCTS_MSK_RPT_3: 6; -#endif - s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ - -/* DWORD 5*/ - u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ - u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ - -/* DWORD 6*/ - s1Byte sigevm; /*signal field EVM*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ - u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ - u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ - u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ -#else /*_BIG_ENDIAN_*/ - u1Byte GNT_BT_keep: 1; - u1Byte dpdt_ctrl_keep: 1; - u1Byte antidx_antd: 3; - u1Byte antidx_antc: 3; -#endif -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/ - u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/ - u1Byte hw_antsw_occur: 2; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u1Byte hw_antsw_occur: 2; - u1Byte antidx_antb: 3; - u1Byte antidx_anta: 3; -#endif -} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T; - -VOID -phydm_reset_rssi_for_dm( - IN OUT PDM_ODM_T pDM_Odm, - IN u1Byte station_id -); - -VOID -odm_Init_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -phydm_normal_driver_rx_sniffer( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN PRT_RFD_STATUS pRtRfdStatus, - IN pu1Byte pDrvInfo, - IN u1Byte PHYStatus - ); -#endif - -void -phydm_get_cck_rssi_table_from_reg( - IN OUT PDM_ODM_T pDM_Odm -); - -VOID -ODM_PhyStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ); - -VOID -ODM_MacStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pMacStatus, - IN u1Byte MacID, - IN BOOLEAN bPacketMatchBSSID, - IN BOOLEAN bPacketToSelf, - IN BOOLEAN bPacketBeacon - ); - -HAL_STATUS -ODM_ConfigRFWithTxPwrTrackHeaderFile( - IN PDM_ODM_T pDM_Odm - ); - -HAL_STATUS -ODM_ConfigRFWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_Config_Type ConfigType, - IN ODM_RF_RADIO_PATH_E eRFPath - ); - -HAL_STATUS -ODM_ConfigBBWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_BB_Config_Type ConfigType - ); - -HAL_STATUS -ODM_ConfigMACWithHeaderFile( - IN PDM_ODM_T pDM_Odm - ); - -HAL_STATUS -ODM_ConfigFWWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_FW_Config_Type ConfigType, - OUT u1Byte *pFirmware, - OUT u4Byte *pSize - ); - -u4Byte -ODM_GetHWImgVersion( - IN PDM_ODM_T pDM_Odm - ); - -s4Byte -odm_SignalScaleMapping( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig - ); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/*For 8822B only!! need to move to FW finally */ -/*==============================================*/ -VOID -phydm_RxPhyStatusNewType( - IN PDM_ODM_T pPhydm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo -); - -typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { - /* DW0 */ - u1Byte page_num; - u1Byte pwdb; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain: 6; - u1Byte rsvd_0: 1; - u1Byte trsw: 1; -#else - u1Byte trsw: 1; - u1Byte rsvd_0: 1; - u1Byte gain: 6; -#endif - u1Byte rsvd_1; - - /* DW1 */ - u1Byte rsvd_2; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte rxsc: 4; - u1Byte agc_table: 4; -#else - u1Byte agc_table: 4; - u1Byte rxsc: 4; -#endif - u1Byte channel; - u1Byte band; - - /* DW2 */ - u2Byte length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_a: 3; - u1Byte antidx_b: 3; - u1Byte rsvd_3: 2; - u1Byte antidx_c: 3; - u1Byte antidx_d: 3; - u1Byte rsvd_4:2; -#else - u1Byte rsvd_3: 2; - u1Byte antidx_b: 3; - u1Byte antidx_a: 3; - u1Byte rsvd_4:2; - u1Byte antidx_d: 3; - u1Byte antidx_c: 3; -#endif - - /* DW3 */ - u1Byte signal_quality; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte vga:5; - u1Byte lna_l:3; - u1Byte bb_power:6; - u1Byte rsvd_9:1; - u1Byte lna_h:1; -#else - u1Byte lna_l:3; - u1Byte vga:5; - u1Byte lna_h:1; - u1Byte rsvd_9:1; - u1Byte bb_power:6; -#endif - u1Byte rsvd_5; - - /* DW4 */ - u4Byte rsvd_6; - - /* DW5 */ - u4Byte rsvd_7; - - /* DW6 */ - u4Byte rsvd_8; -} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; - -typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { - /* DW0 and DW1 */ - u1Byte page_num; - u1Byte pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte l_rxsc: 4; - u1Byte ht_rxsc: 4; -#else - u1Byte ht_rxsc: 4; - u1Byte l_rxsc: 4; -#endif - u1Byte channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte band: 2; - u1Byte rsvd_0: 1; - u1Byte hw_antsw_occu: 1; - u1Byte gnt_bt: 1; - u1Byte ldpc: 1; - u1Byte stbc: 1; - u1Byte beamformed: 1; -#else - u1Byte beamformed: 1; - u1Byte stbc: 1; - u1Byte ldpc: 1; - u1Byte gnt_bt: 1; - u1Byte hw_antsw_occu: 1; - u1Byte rsvd_0: 1; - u1Byte band: 2; -#endif - - /* DW2 */ - u2Byte lsig_length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_a: 3; - u1Byte antidx_b: 3; - u1Byte rsvd_1: 2; - u1Byte antidx_c: 3; - u1Byte antidx_d: 3; - u1Byte rsvd_2: 2; -#else - u1Byte rsvd_1: 2; - u1Byte antidx_b: 3; - u1Byte antidx_a: 3; - u1Byte rsvd_2: 2; - u1Byte antidx_d: 3; - u1Byte antidx_c: 3; -#endif - - /* DW3 */ - u1Byte paid; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte paid_msb: 1; - u1Byte gid: 6; - u1Byte rsvd_3: 1; -#else - u1Byte rsvd_3: 1; - u1Byte gid: 6; - u1Byte paid_msb: 1; -#endif - u1Byte intf_pos; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte intf_pos_msb: 1; - u1Byte rsvd_4: 2; - u1Byte nb_intf_flag: 1; - u1Byte rf_mode: 2; - u1Byte rsvd_5: 2; -#else - u1Byte rsvd_5: 2; - u1Byte rf_mode: 2; - u1Byte nb_intf_flag: 1; - u1Byte rsvd_4: 2; - u1Byte intf_pos_msb: 1; -#endif - - /* DW4 */ - s1Byte rxevm[4]; /* s(8,1) */ - - /* DW5 */ - s1Byte cfo_tail[4]; /* s(8,7) */ - - /* DW6 */ - s1Byte rxsnr[4]; /* s(8,1) */ -} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1; - -typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { - /* DW0 ane DW1 */ - u1Byte page_num; - u1Byte pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte l_rxsc: 4; - u1Byte ht_rxsc: 4; -#else - u1Byte ht_rxsc: 4; - u1Byte l_rxsc: 4; -#endif - u1Byte channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte band: 2; - u1Byte rsvd_0: 1; - u1Byte hw_antsw_occu: 1; - u1Byte gnt_bt: 1; - u1Byte ldpc: 1; - u1Byte stbc: 1; - u1Byte beamformed: 1; -#else - u1Byte beamformed: 1; - u1Byte stbc: 1; - u1Byte ldpc: 1; - u1Byte gnt_bt: 1; - u1Byte hw_antsw_occu: 1; - u1Byte rsvd_0: 1; - u1Byte band: 2; -#endif - - /* DW2 */ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte shift_l_map: 6; - u1Byte rsvd_1: 2; -#else - u1Byte rsvd_1: 2; - u1Byte shift_l_map: 6; -#endif - u1Byte cnt_pw2cca; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte agc_table_a: 4; - u1Byte agc_table_b: 4; - u1Byte agc_table_c: 4; - u1Byte agc_table_d: 4; -#else - u1Byte agc_table_b: 4; - u1Byte agc_table_a: 4; - u1Byte agc_table_d: 4; - u1Byte agc_table_c: 4; -#endif - - /* DW3 ~ DW6*/ - u1Byte cnt_cca2agc_rdy; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain_a: 6; - u1Byte rsvd_2: 1; - u1Byte trsw_a: 1; - u1Byte gain_b: 6; - u1Byte rsvd_3: 1; - u1Byte trsw_b: 1; - u1Byte gain_c: 6; - u1Byte rsvd_4: 1; - u1Byte trsw_c: 1; - u1Byte gain_d: 6; - u1Byte rsvd_5: 1; - u1Byte trsw_d: 1; - u1Byte aagc_step_a: 2; - u1Byte aagc_step_b: 2; - u1Byte aagc_step_c: 2; - u1Byte aagc_step_d: 2; -#else - u1Byte trsw_a: 1; - u1Byte rsvd_2: 1; - u1Byte gain_a: 6; - u1Byte trsw_b: 1; - u1Byte rsvd_3: 1; - u1Byte gain_b: 6; - u1Byte trsw_c: 1; - u1Byte rsvd_4: 1; - u1Byte gain_c: 6; - u1Byte trsw_d: 1; - u1Byte rsvd_5: 1; - u1Byte gain_d: 6; - u1Byte aagc_step_d: 2; - u1Byte aagc_step_c: 2; - u1Byte aagc_step_b: 2; - u1Byte aagc_step_a: 2; -#endif - u1Byte ht_aagc_gain[4]; - u1Byte dagc_gain[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte counter: 6; - u1Byte rsvd_6: 2; - u1Byte syn_count: 5; - u1Byte rsvd_7:3; -#else - u1Byte rsvd_6: 2; - u1Byte counter: 6; - u1Byte rsvd_7:3; - u1Byte syn_count: 5; -#endif -} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2; -/*==============================================*/ -#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ - -u4Byte -query_phydm_trx_capability( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_stbc_capability( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_ldpc_capability( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_txbf_parameters( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_txbf_capability( - IN PDM_ODM_T pDM_Odm -); - -#endif /*#ifndef __HALHWOUTSRC_H__*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + + +/*--------------------------Define -------------------------------------------*/ +#define CCK_RSSI_INIT_COUNT 5 + +#define RA_RSSI_STATE_INIT 0 +#define RA_RSSI_STATE_SEND 1 +#define RA_RSSI_STATE_HOLD 2 + +#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) +/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ + +#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) +#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) + +#define AGC_DIFF_CONFIG(ic, band) do {\ + if (pDM_Odm->bIsMPChip)\ + AGC_DIFF_CONFIG_MP(ic,band);\ + else\ + AGC_DIFF_CONFIG_TC(ic,band);\ + } while(0) + + +//============================================================ +// structure and define +//============================================================ + +__PACK typedef struct _Phy_Rx_AGC_Info +{ + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain:7,trsw:1; + #else + u1Byte trsw:1,gain:7; + #endif +} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T; + +__PACK typedef struct _Phy_Status_Rpt_8192cd { + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_corr[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_rpt_b_ofdm_cfosho_b; + u1Byte rsvd_1;/*ch_corr_msb;*/ + u1Byte noise_power_db_msb; + s1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte noise_power_db_lsb; + u1Byte rsvd_2[3]; + u1Byte stream_csi[2]; + u1Byte stream_target_csi[2]; + s1Byte sig_evm; + u1Byte rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u1Byte sgi_en: 1; + u1Byte rxsc: 2; + u1Byte idle_long: 1; + u1Byte r_ant_train_en: 1; + u1Byte ant_sel_b: 1; + u1Byte ant_sel: 1; +#else /*_BIG_ENDIAN_ */ + u1Byte ant_sel: 1; + u1Byte ant_sel_b: 1; + u1Byte r_ant_train_en: 1; + u1Byte idle_long: 1; + u1Byte rxsc: 2; + u1Byte sgi_en: 1; + u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ +#endif +} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T; + + +typedef struct _Phy_Status_Rpt_8812 { +/* DWORD 0*/ + u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u1Byte chl_num_LSB; /*channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte chl_num_MSB: 2; /*channel number[9:8]*/ + u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/ + u1Byte r_RFMOD: 2; /*RF mode[1:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte r_RFMOD: 2; + u1Byte sub_chnl: 4; + u1Byte chl_num_MSB: 2; +#endif + +/* DWORD 1*/ + u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + /*this should be checked again because the definition of 8812 and 8814 is different*/ +/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ +/* u1Byte cck_rx_path:4; cck rx path[3:0]*/ + u1Byte resvd_0: 6; + u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*_BIG_ENDIAN_*/ + u1Byte bt_RF_ch_MSB: 2; + u1Byte resvd_0: 6; +#endif + +/* DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte bt_RF_ch_LSB: 6; + u1Byte ant_div_sw_b: 1; + u1Byte ant_div_sw_a: 1; +#endif + s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + +/* DWORD 3*/ + s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + +/* DWORD 4*/ + u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u1Byte resvd_1: 1; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte resvd_1: 1; + u1Byte pcts_rpt_valid: 1; + u1Byte PCTS_MSK_RPT_3: 6; +#endif + s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + +/* DWORD 5*/ + u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + +/* DWORD 6*/ + s1Byte sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*_BIG_ENDIAN_*/ + u1Byte GNT_BT_keep: 1; + u1Byte dpdt_ctrl_keep: 1; + u1Byte antidx_antd: 3; + u1Byte antidx_antc: 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/ + u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/ + u1Byte hw_antsw_occur: 2; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte hw_antsw_occur: 2; + u1Byte antidx_antb: 3; + u1Byte antidx_anta: 3; +#endif +} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T; + +VOID +phydm_reset_rssi_for_dm( + IN OUT PDM_ODM_T pDM_Odm, + IN u1Byte station_id +); + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +phydm_normal_driver_rx_sniffer( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN PRT_RFD_STATUS pRtRfdStatus, + IN pu1Byte pDrvInfo, + IN u1Byte PHYStatus + ); +#endif + +void +phydm_get_cck_rssi_table_from_reg( + IN OUT PDM_ODM_T pDM_Odm +); + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ); + +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ); + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ); + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ); + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigFWWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_FW_Config_Type ConfigType, + OUT u1Byte *pFirmware, + OUT u4Byte *pSize + ); + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ); + +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig + ); + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +/*For 8822B only!! need to move to FW finally */ +/*==============================================*/ +VOID +phydm_RxPhyStatusNewType( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +); + +typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { + /* DW0 */ + u1Byte page_num; + u1Byte pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain: 6; + u1Byte rsvd_0: 1; + u1Byte trsw: 1; +#else + u1Byte trsw: 1; + u1Byte rsvd_0: 1; + u1Byte gain: 6; +#endif + u1Byte rsvd_1; + + /* DW1 */ + u1Byte rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte rxsc: 4; + u1Byte agc_table: 4; +#else + u1Byte agc_table: 4; + u1Byte rxsc: 4; +#endif + u1Byte channel; + u1Byte band; + + /* DW2 */ + u2Byte length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_3: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_4:2; +#else + u1Byte rsvd_3: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_4:2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte vga:5; + u1Byte lna_l:3; + u1Byte bb_power:6; + u1Byte rsvd_9:1; + u1Byte lna_h:1; +#else + u1Byte lna_l:3; + u1Byte vga:5; + u1Byte lna_h:1; + u1Byte rsvd_9:1; + u1Byte bb_power:6; +#endif + u1Byte rsvd_5; + + /* DW4 */ + u4Byte rsvd_6; + + /* DW5 */ + u4Byte rsvd_7; + + /* DW6 */ + u4Byte rsvd_8; +} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { + /* DW0 and DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ + u2Byte lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_1: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_2: 2; +#else + u1Byte rsvd_1: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_2: 2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte paid_msb: 1; + u1Byte gid: 6; + u1Byte rsvd_3: 1; +#else + u1Byte rsvd_3: 1; + u1Byte gid: 6; + u1Byte paid_msb: 1; +#endif + u1Byte intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte intf_pos_msb: 1; + u1Byte rsvd_4: 2; + u1Byte nb_intf_flag: 1; + u1Byte rf_mode: 2; + u1Byte rsvd_5: 2; +#else + u1Byte rsvd_5: 2; + u1Byte rf_mode: 2; + u1Byte nb_intf_flag: 1; + u1Byte rsvd_4: 2; + u1Byte intf_pos_msb: 1; +#endif + + /* DW4 */ + s1Byte rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s1Byte cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s1Byte rxsnr[4]; /* s(8,1) */ +} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { + /* DW0 ane DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte shift_l_map: 6; + u1Byte rsvd_1: 2; +#else + u1Byte rsvd_1: 2; + u1Byte shift_l_map: 6; +#endif + u1Byte cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte agc_table_a: 4; + u1Byte agc_table_b: 4; + u1Byte agc_table_c: 4; + u1Byte agc_table_d: 4; +#else + u1Byte agc_table_b: 4; + u1Byte agc_table_a: 4; + u1Byte agc_table_d: 4; + u1Byte agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u1Byte cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain_a: 6; + u1Byte rsvd_2: 1; + u1Byte trsw_a: 1; + u1Byte gain_b: 6; + u1Byte rsvd_3: 1; + u1Byte trsw_b: 1; + u1Byte gain_c: 6; + u1Byte rsvd_4: 1; + u1Byte trsw_c: 1; + u1Byte gain_d: 6; + u1Byte rsvd_5: 1; + u1Byte trsw_d: 1; + u1Byte aagc_step_a: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_d: 2; +#else + u1Byte trsw_a: 1; + u1Byte rsvd_2: 1; + u1Byte gain_a: 6; + u1Byte trsw_b: 1; + u1Byte rsvd_3: 1; + u1Byte gain_b: 6; + u1Byte trsw_c: 1; + u1Byte rsvd_4: 1; + u1Byte gain_c: 6; + u1Byte trsw_d: 1; + u1Byte rsvd_5: 1; + u1Byte gain_d: 6; + u1Byte aagc_step_d: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_a: 2; +#endif + u1Byte ht_aagc_gain[4]; + u1Byte dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte counter: 6; + u1Byte rsvd_6: 2; + u1Byte syn_count: 5; + u1Byte rsvd_7:3; +#else + u1Byte rsvd_6: 2; + u1Byte counter: 6; + u1Byte rsvd_7:3; + u1Byte syn_count: 5; +#endif +} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2; +/*==============================================*/ +#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ + +u4Byte +query_phydm_trx_capability( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_stbc_capability( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_ldpc_capability( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_txbf_parameters( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_txbf_capability( + IN PDM_ODM_T pDM_Odm +); + +#endif /*#ifndef __HALHWOUTSRC_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_interface.c b/package/kernel/rtl8192cd/phydm/phydm_interface.c index fd0a2646456..3585be3854b 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_interface.c +++ b/package/kernel/rtl8192cd/phydm/phydm_interface.c @@ -1,958 +1,958 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -// -// ODM IO Relative API. -// - -u1Byte -ODM_Read1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R8(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read8(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead1Byte(Adapter, RegAddr); -#endif - -} - - -u2Byte -ODM_Read2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R16(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read16(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead2Byte(Adapter, RegAddr); -#endif - -} - - -u4Byte -ODM_Read4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R32(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read32(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead4Byte(Adapter, RegAddr); -#endif - -} - - -VOID -ODM_Write1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u1Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W8(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write8(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); -#endif - -} - - -VOID -ODM_Write2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u2Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W16(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write16(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); -#endif - -} - - -VOID -ODM_Write4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W32(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write32(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); -#endif - -} - - -VOID -ODM_SetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); -#endif -} - - -u4Byte -ODM_GetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask); -#endif -} - - -VOID -ODM_SetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); -#endif -} - - -u4Byte -ODM_GetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - return PHY_QueryBBReg(Adapter, RegAddr, BitMask); -#endif -} - - -VOID -ODM_SetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); - ODM_delay_us(2); - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PHY_SetRFReg(pDM_Odm->Adapter, eRFPath, RegAddr, BitMask, Data); -#endif -} - -u4Byte -ODM_GetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); -#endif -} - - - - -// -// ODM Memory relative API. -// -VOID -ODM_AllocateMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID *pPtr, - IN u4Byte length - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - *pPtr = kmalloc(length, GFP_ATOMIC); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - *pPtr = rtw_zvmalloc(length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformAllocateMemory(Adapter, pPtr, length); -#endif -} - -// length could be ignored, used to detect memory leakage. -VOID -ODM_FreeMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pPtr, - IN u4Byte length - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - kfree(pPtr); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - rtw_vmfree(pPtr, length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - //PADAPTER Adapter = pDM_Odm->Adapter; - PlatformFreeMemory(pPtr, length); -#endif -} - -VOID -ODM_MoveMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pDest, - IN PVOID pSrc, - IN u4Byte Length - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - memcpy(pDest, pSrc, Length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - _rtw_memcpy(pDest, pSrc, Length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformMoveMemory(pDest, pSrc, Length); -#endif -} - -void ODM_Memory_Set( - IN PDM_ODM_T pDM_Odm, - IN PVOID pbuf, - IN s1Byte value, - IN u4Byte length -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - memset(pbuf, value, length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - _rtw_memset(pbuf,value, length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformFillMemory(pbuf,length,value); -#endif -} -s4Byte ODM_CompareMemory( - IN PDM_ODM_T pDM_Odm, - IN PVOID pBuf1, - IN PVOID pBuf2, - IN u4Byte length - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return memcmp(pBuf1,pBuf2,length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - return _rtw_memcmp(pBuf1,pBuf2,length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformCompareMemory(pBuf1,pBuf2,length); -#endif -} - - - -// -// ODM MISC relative API. -// -VOID -ODM_AcquireSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_odm_acquirespinlock(Adapter, type); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformAcquireSpinLock(Adapter, type); -#endif -} -VOID -ODM_ReleaseSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_odm_releasespinlock(Adapter, type); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformReleaseSpinLock(Adapter, type); -#endif -} - -// -// Work item relative API. FOr MP driver only~! -// -VOID -ODM_InitializeWorkItem( - IN PDM_ODM_T pDM_Odm, - IN PRT_WORK_ITEM pRtWorkItem, - IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, - IN PVOID pContext, - IN const char* szID - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); -#endif -} - - -VOID -ODM_StartWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStartWorkItem(pRtWorkItem); -#endif -} - - -VOID -ODM_StopWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStopWorkItem(pRtWorkItem); -#endif -} - - -VOID -ODM_FreeWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformFreeWorkItem(pRtWorkItem); -#endif -} - - -VOID -ODM_ScheduleWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformScheduleWorkItem(pRtWorkItem); -#endif -} - - -VOID -ODM_IsWorkItemScheduled( - IN PRT_WORK_ITEM pRtWorkItem - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformIsWorkItemScheduled(pRtWorkItem); -#endif -} - - - -// -// ODM Timer relative API. -// -VOID -ODM_StallExecution( - IN u4Byte usDelay - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(usDelay); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStallExecution(usDelay); -#endif -} - -VOID -ODM_delay_ms(IN u4Byte ms) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - delay_ms(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_mdelay_os(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - delay_ms(ms); -#endif -} - -VOID -ODM_delay_us(IN u4Byte us) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - delay_us(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStallExecution(us); -#endif -} - -VOID -ODM_sleep_ms(IN u4Byte ms) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_msleep_os(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#endif -} - -VOID -ODM_sleep_us(IN u4Byte us) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_usleep_os(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#endif -} - -VOID -ODM_SetTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN u4Byte msDelay - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay)); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - _set_timer(pTimer,msDelay ); //ms -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformSetTimer(Adapter, pTimer, msDelay); -#endif - -} - -VOID -ODM_InitializeTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN RT_TIMER_CALL_BACK CallBackFunc, - IN PVOID pContext, - IN const char* szID - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - init_timer(pTimer); - pTimer->function = CallBackFunc; - pTimer->data = (unsigned long)pDM_Odm; - /*mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); -#endif -} - - -VOID -ODM_CancelTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - del_timer(pTimer); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - _cancel_timer_ex(pTimer); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformCancelTimer(Adapter, pTimer); -#endif -} - - -VOID -ODM_ReleaseTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - - PADAPTER Adapter = pDM_Odm->Adapter; - - // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. - // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. - if (pTimer == 0) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); - return; - } - - PlatformReleaseTimer(Adapter, pTimer); -#endif -} - - -u1Byte -phydm_trans_h2c_id( - IN PDM_ODM_T pDM_Odm, - IN u1Byte phydm_h2c_id -) -{ - u1Byte platform_h2c_id = phydm_h2c_id; - - switch (phydm_h2c_id) - { - //1 [0] - case ODM_H2C_RSSI_REPORT: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - platform_h2c_id = H2C_88E_RSSI_REPORT; - else if(pDM_Odm->SupportICType == ODM_RTL8814A) - platform_h2c_id =H2C_8814A_RSSI_REPORT; - else - platform_h2c_id = H2C_RSSI_REPORT; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - platform_h2c_id = H2C_RSSI_SETTING; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_RSSI_REPORT; - else - #endif - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_RSSI_REPORT; - else - #endif - {} - #endif - - break; - - //1 [3] - case ODM_H2C_WIFI_CALIBRATION: - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - platform_h2c_id =H2C_WIFI_CALIBRATION; - - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - #if (RTL8723B_SUPPORT == 1) - platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; - #endif - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - break; - - - //1 [4] - case ODM_H2C_IQ_CALIBRATION: - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - platform_h2c_id =H2C_IQ_CALIBRATION; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) - platform_h2c_id = H2C_8812_IQ_CALIBRATION; - #endif - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - - break; - //1 [5] - case ODM_H2C_RA_PARA_ADJUST: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) - platform_h2c_id =H2C_8814A_RA_PARA_ADJUST; - else - platform_h2c_id = H2C_RA_PARA_ADJUST; - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) - platform_h2c_id = H2C_8812_RA_PARA_ADJUST; - #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - platform_h2c_id = H2C_RA_PARA_ADJUST; - #elif(RTL8192E_SUPPORT==1) - platform_h2c_id =H2C_8192E_RA_PARA_ADJUST; - #elif(RTL8723B_SUPPORT==1) - platform_h2c_id =H2C_8723B_RA_PARA_ADJUST; - #endif - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; - else - #endif - #if(RTL8812A_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_RA_PARA_ADJUST; - else - #endif - {} - #endif - - break; - - - //1 [6] - case PHYDM_H2C_DYNAMIC_TX_PATH: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - platform_h2c_id =H2C_8814A_DYNAMIC_TX_PATH; - } - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - platform_h2c_id = H2C_DYNAMIC_TX_PATH; - #endif - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #if(RTL8814A_SUPPORT==1) - if( pDM_Odm->SupportICType == ODM_RTL8814A) - { - platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; - } - #endif - - #endif - - break; - - /* [7]*/ - case PHYDM_H2C_FW_TRACE_EN: - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) - platform_h2c_id = H2C_8814A_FW_TRACE_EN; - else - platform_h2c_id = H2C_FW_TRACE_EN; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - - platform_h2c_id = 0x49; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_FW_TRACE_EN; - else - #endif - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_FW_TRACE_EN; - else - #endif - {} - - #endif - - break; - - case PHYDM_H2C_TXBF: - #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - platform_h2c_id = 0x41; /*H2C_TxBF*/ - #endif - break; - - case PHYDM_H2C_MU: - #if (RTL8822B_SUPPORT == 1) - platform_h2c_id = 0x4a; /*H2C_MU*/ - #endif - break; - - default: - platform_h2c_id = phydm_h2c_id; - break; - } - - return platform_h2c_id; - -} - -/*ODM FW relative API.*/ - -VOID -ODM_FillH2CCmd( - IN PDM_ODM_T pDM_Odm, - IN u1Byte phydm_h2c_id, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer -) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte platform_h2c_id; - - platform_h2c_id=phydm_trans_h2c_id(pDM_Odm, phydm_h2c_id); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - if (!pDM_Odm->RaSupport88E) - FillH2CCmd88E(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - } else if (pDM_Odm->SupportICType == ODM_RTL8814A) - FillH2CCmd8814A(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - else if (pDM_Odm->SupportICType == ODM_RTL8822B) -#if (RTL8822B_SUPPORT == 1) - FillH2CCmd8822B(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); -#endif - else - FillH2CCmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_hal_fill_h2c_cmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - -#elif(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - GET_HAL_INTERFACE(pDM_Odm->priv)->FillH2CCmdHandler(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); - else -#endif -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - FillH2CCmd8812(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); - else -#endif - {} -#endif -} - -u1Byte -phydm_c2H_content_parsing( - IN PVOID pDM_VOID, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - #endif - u1Byte Extend_c2hSubID = 0; - u1Byte find_c2h_cmd = TRUE; - - switch (c2hCmdId) { - case PHYDM_C2H_DBG: - phydm_fw_trace_handler(pDM_Odm, tmpBuf, c2hCmdLen); - break; - - case PHYDM_C2H_RA_RPT: - phydm_c2h_ra_report_handler(pDM_Odm, tmpBuf, c2hCmdLen); - break; - - case PHYDM_C2H_RA_PARA_RPT: - ODM_C2HRaParaReportHandler(pDM_Odm, tmpBuf, c2hCmdLen); - break; - - case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: - if (pDM_Odm->SupportICType & (ODM_RTL8814A)) - phydm_c2h_dtp_handler(pDM_Odm, tmpBuf, c2hCmdLen); - break; - - case PHYDM_C2H_IQK_FINISH: - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) { - - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); - PlatformAcquireSpinLock(Adapter, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - PlatformReleaseSpinLock(Adapter, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = 0; - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - } - - #endif - break; - - case PHYDM_C2H_DBG_CODE: - phydm_fw_trace_handler_code(pDM_Odm, tmpBuf, c2hCmdLen); - break; - - case PHYDM_C2H_EXTEND: - Extend_c2hSubID= tmpBuf[0]; - if (Extend_c2hSubID == PHYDM_EXTEND_C2H_DBG_PRINT) - phydm_fw_trace_handler_8051(pDM_Odm, tmpBuf, c2hCmdLen); - - break; - - default: - find_c2h_cmd = FALSE; - break; - } - - return find_c2h_cmd; - -} - -u8Byte -ODM_GetCurrentTime( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return (u8Byte)rtw_get_current_time(); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - return (u8Byte)rtw_get_current_time(); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformGetCurrentTime(); -#endif -} - -u8Byte -ODM_GetProgressingTime( - IN PDM_ODM_T pDM_Odm, - IN u8Byte Start_Time - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return rtw_get_passing_time_ms((u32)Start_Time); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - return rtw_get_passing_time_ms((u4Byte)Start_Time); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - return ((PlatformGetCurrentTime() - Start_Time)>>10); -#endif -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +// +// ODM IO Relative API. +// + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R8(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read8(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead1Byte(Adapter, RegAddr); +#endif + +} + + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R16(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read16(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead2Byte(Adapter, RegAddr); +#endif + +} + + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R32(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read32(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead4Byte(Adapter, RegAddr); +#endif + +} + + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W8(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write8(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W16(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write16(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W32(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write32(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryBBReg(Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); + ODM_delay_us(2); + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PHY_SetRFReg(pDM_Odm->Adapter, eRFPath, RegAddr, BitMask, Data); +#endif +} + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); +#endif +} + + + + +// +// ODM Memory relative API. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + *pPtr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + *pPtr = rtw_zvmalloc(length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAllocateMemory(Adapter, pPtr, length); +#endif +} + +// length could be ignored, used to detect memory leakage. +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + kfree(pPtr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + rtw_vmfree(pPtr, length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + //PADAPTER Adapter = pDM_Odm->Adapter; + PlatformFreeMemory(pPtr, length); +#endif +} + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memcpy(pDest, pSrc, Length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + _rtw_memcpy(pDest, pSrc, Length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformMoveMemory(pDest, pSrc, Length); +#endif +} + +void ODM_Memory_Set( + IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length +) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + _rtw_memset(pbuf,value, length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFillMemory(pbuf,length,value); +#endif +} +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return memcmp(pBuf1,pBuf2,length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + return _rtw_memcmp(pBuf1,pBuf2,length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformCompareMemory(pBuf1,pBuf2,length); +#endif +} + + + +// +// ODM MISC relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_odm_acquirespinlock(Adapter, type); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAcquireSpinLock(Adapter, type); +#endif +} +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_odm_releasespinlock(Adapter, type); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformReleaseSpinLock(Adapter, type); +#endif +} + +// +// Work item relative API. FOr MP driver only~! +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); +#endif +} + + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStartWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStopWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFreeWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformScheduleWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformIsWorkItemScheduled(pRtWorkItem); +#endif +} + + + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(usDelay); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(usDelay); +#endif +} + +VOID +ODM_delay_ms(IN u4Byte ms) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_ms(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_mdelay_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); +#endif +} + +VOID +ODM_delay_us(IN u4Byte us) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_us(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); +#endif +} + +VOID +ODM_sleep_ms(IN u4Byte ms) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_msleep_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif +} + +VOID +ODM_sleep_us(IN u4Byte us) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_usleep_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif +} + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay)); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + _set_timer(pTimer,msDelay ); //ms +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformSetTimer(Adapter, pTimer, msDelay); +#endif + +} + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + init_timer(pTimer); + pTimer->function = CallBackFunc; + pTimer->data = (unsigned long)pDM_Odm; + /*mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); +#endif +} + + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + del_timer(pTimer); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + _cancel_timer_ex(pTimer); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformCancelTimer(Adapter, pTimer); +#endif +} + + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + PADAPTER Adapter = pDM_Odm->Adapter; + + // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. + // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. + if (pTimer == 0) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); + return; + } + + PlatformReleaseTimer(Adapter, pTimer); +#endif +} + + +u1Byte +phydm_trans_h2c_id( + IN PDM_ODM_T pDM_Odm, + IN u1Byte phydm_h2c_id +) +{ + u1Byte platform_h2c_id = phydm_h2c_id; + + switch (phydm_h2c_id) + { + //1 [0] + case ODM_H2C_RSSI_REPORT: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + platform_h2c_id = H2C_88E_RSSI_REPORT; + else if(pDM_Odm->SupportICType == ODM_RTL8814A) + platform_h2c_id =H2C_8814A_RSSI_REPORT; + else + platform_h2c_id = H2C_RSSI_REPORT; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + platform_h2c_id = H2C_RSSI_SETTING; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_RSSI_REPORT; + else + #endif + #if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + platform_h2c_id = H2C_8812_RSSI_REPORT; + else + #endif + {} + #endif + + break; + + //1 [3] + case ODM_H2C_WIFI_CALIBRATION: + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id =H2C_WIFI_CALIBRATION; + + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + #if (RTL8723B_SUPPORT == 1) + platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; + #endif + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #endif + break; + + + //1 [4] + case ODM_H2C_IQ_CALIBRATION: + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id =H2C_IQ_CALIBRATION; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) + platform_h2c_id = H2C_8812_IQ_CALIBRATION; + #endif + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #endif + + break; + //1 [5] + case ODM_H2C_RA_PARA_ADJUST: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) + platform_h2c_id =H2C_8814A_RA_PARA_ADJUST; + else + platform_h2c_id = H2C_RA_PARA_ADJUST; + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + platform_h2c_id = H2C_RA_PARA_ADJUST; + #elif(RTL8192E_SUPPORT==1) + platform_h2c_id =H2C_8192E_RA_PARA_ADJUST; + #elif(RTL8723B_SUPPORT==1) + platform_h2c_id =H2C_8723B_RA_PARA_ADJUST; + #endif + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; + else + #endif + #if(RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + else + #endif + {} + #endif + + break; + + + //1 [6] + case PHYDM_H2C_DYNAMIC_TX_PATH: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + platform_h2c_id =H2C_8814A_DYNAMIC_TX_PATH; + } + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + platform_h2c_id = H2C_DYNAMIC_TX_PATH; + #endif + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if(RTL8814A_SUPPORT==1) + if( pDM_Odm->SupportICType == ODM_RTL8814A) + { + platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; + } + #endif + + #endif + + break; + + /* [7]*/ + case PHYDM_H2C_FW_TRACE_EN: + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) + platform_h2c_id = H2C_8814A_FW_TRACE_EN; + else + platform_h2c_id = H2C_FW_TRACE_EN; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + + platform_h2c_id = 0x49; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_FW_TRACE_EN; + else + #endif + #if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + platform_h2c_id = H2C_8812_FW_TRACE_EN; + else + #endif + {} + + #endif + + break; + + case PHYDM_H2C_TXBF: + #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + platform_h2c_id = 0x41; /*H2C_TxBF*/ + #endif + break; + + case PHYDM_H2C_MU: + #if (RTL8822B_SUPPORT == 1) + platform_h2c_id = 0x4a; /*H2C_MU*/ + #endif + break; + + default: + platform_h2c_id = phydm_h2c_id; + break; + } + + return platform_h2c_id; + +} + +/*ODM FW relative API.*/ + +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte phydm_h2c_id, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte platform_h2c_id; + + platform_h2c_id=phydm_trans_h2c_id(pDM_Odm, phydm_h2c_id); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + if (!pDM_Odm->RaSupport88E) + FillH2CCmd88E(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + } else if (pDM_Odm->SupportICType == ODM_RTL8814A) + FillH2CCmd8814A(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + else if (pDM_Odm->SupportICType == ODM_RTL8822B) +#if (RTL8822B_SUPPORT == 1) + FillH2CCmd8822B(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); +#endif + else + FillH2CCmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_hal_fill_h2c_cmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + +#elif(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) + GET_HAL_INTERFACE(pDM_Odm->priv)->FillH2CCmdHandler(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + FillH2CCmd8812(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); + else +#endif + {} +#endif +} + +u1Byte +phydm_c2H_content_parsing( + IN PVOID pDM_VOID, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + #endif + u1Byte Extend_c2hSubID = 0; + u1Byte find_c2h_cmd = TRUE; + + switch (c2hCmdId) { + case PHYDM_C2H_DBG: + phydm_fw_trace_handler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_RA_RPT: + phydm_c2h_ra_report_handler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_RA_PARA_RPT: + ODM_C2HRaParaReportHandler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: + if (pDM_Odm->SupportICType & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_IQK_FINISH: + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) { + + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); + PlatformAcquireSpinLock(Adapter, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + PlatformReleaseSpinLock(Adapter, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = 0; + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + } + + #endif + break; + + case PHYDM_C2H_DBG_CODE: + phydm_fw_trace_handler_code(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_EXTEND: + Extend_c2hSubID= tmpBuf[0]; + if (Extend_c2hSubID == PHYDM_EXTEND_C2H_DBG_PRINT) + phydm_fw_trace_handler_8051(pDM_Odm, tmpBuf, c2hCmdLen); + + break; + + default: + find_c2h_cmd = FALSE; + break; + } + + return find_c2h_cmd; + +} + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return (u8Byte)rtw_get_current_time(); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + return (u8Byte)rtw_get_current_time(); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformGetCurrentTime(); +#endif +} + +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return rtw_get_passing_time_ms((u32)Start_Time); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_passing_time_ms((u4Byte)Start_Time); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return ((PlatformGetCurrentTime() - Start_Time)>>10); +#endif +} + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_interface.h b/package/kernel/rtl8192cd/phydm/phydm_interface.h index 510c128f301..a08eb7ec72f 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_interface.h +++ b/package/kernel/rtl8192cd/phydm/phydm_interface.h @@ -1,426 +1,426 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __ODM_INTERFACE_H__ -#define __ODM_INTERFACE_H__ - -#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ - -// -// =========== Constant/Structure/Enum/... Define -// - - - -// -// =========== Macro Define -// - -#define _reg_all(_name) ODM_##_name -#define _reg_ic(_name, _ic) ODM_##_name##_ic -#define _bit_all(_name) BIT_##_name -#define _bit_ic(_name, _ic) BIT_##_name##_ic - -// _cat: implemented by Token-Pasting Operator. -#if 0 -#define _cat(_name, _ic_type, _func) \ - ( \ - _func##_all(_name) \ - ) -#endif - -/*=================================== - -#define ODM_REG_DIG_11N 0xC50 -#define ODM_REG_DIG_11AC 0xDDD - -ODM_REG(DIG,_pDM_Odm) -=====================================*/ - -#define _reg_11N(_name) ODM_REG_##_name##_11N -#define _reg_11AC(_name) ODM_REG_##_name##_11AC -#define _bit_11N(_name) ODM_BIT_##_name##_11N -#define _bit_11AC(_name) ODM_BIT_##_name##_11AC - -#ifdef __ECOS -#define _rtk_cat(_name, _ic_type, _func) \ - ( \ - ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ - _func##_11AC(_name) \ - ) -#else - -#define _cat(_name, _ic_type, _func) \ - ( \ - ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ - _func##_11AC(_name) \ - ) -#endif -/* -// only sample code -//#define _cat(_name, _ic_type, _func) \ -// ( \ -// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ -// _func##_ic(_name, _8195) \ -// ) -*/ - -// _name: name of register or bit. -// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" -// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. -#ifdef __ECOS -#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) -#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) -#else -#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) -#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) -#endif -typedef enum _PHYDM_H2C_CMD { - PHYDM_H2C_TXBF = 0x41, - ODM_H2C_RSSI_REPORT = 0x42, - ODM_H2C_IQ_CALIBRATION = 0x45, - ODM_H2C_RA_PARA_ADJUST = 0x47, - PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, - PHYDM_H2C_FW_TRACE_EN = 0x49, - ODM_H2C_WIFI_CALIBRATION = 0x6d, - PHYDM_H2C_MU = 0x4a, - ODM_MAX_H2CCMD -}PHYDM_H2C_CMD; - -typedef enum _PHYDM_C2H_EVT { - PHYDM_C2H_DBG = 0, - PHYDM_C2H_LB = 1, - PHYDM_C2H_XBF = 2, - PHYDM_C2H_TX_REPORT = 3, - PHYDM_C2H_INFO = 9, - PHYDM_C2H_BT_MP = 11, - PHYDM_C2H_RA_RPT = 12, - PHYDM_C2H_RA_PARA_RPT=14, - PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, - PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ - PHYDM_C2H_DBG_CODE = 0xFE, - PHYDM_C2H_EXTEND = 0xFF, -}PHYDM_C2H_EVT; - -typedef enum _PHYDM_EXTEND_C2H_EVT { - PHYDM_EXTEND_C2H_DBG_PRINT = 0 - -}PHYDM_EXTEND_C2H_EVT; - - -// -// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. -// Suggest HW team to use thread instead of workitem. Windows also support the feature. -// -#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -typedef void *PRT_WORK_ITEM ; -typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; -typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); - -#if 0 -typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; - -typedef struct _RT_WORK_ITEM -{ - - RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. - PVOID Adapter; // Pointer to Adapter object. - PVOID pContext; // Parameter to passed to CallBackFunc(). - RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. - u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. - PVOID pPlatformExt; // Pointer to platform-dependent extension. - BOOLEAN bFree; - char szID[36]; // An identity string of this workitem. -}RT_WORK_ITEM, *PRT_WORK_ITEM; - -#endif - - -#endif - -// -// =========== Extern Variable ??? It should be forbidden. -// - - -// -// =========== EXtern Function Prototype -// - - -u1Byte -ODM_Read1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); - -u2Byte -ODM_Read2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); - -u4Byte -ODM_Read4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); - -VOID -ODM_Write1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u1Byte Data - ); - -VOID -ODM_Write2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u2Byte Data - ); - -VOID -ODM_Write4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte Data - ); - -VOID -ODM_SetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -u4Byte -ODM_GetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - -VOID -ODM_SetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -u4Byte -ODM_GetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - -VOID -ODM_SetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -u4Byte -ODM_GetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - - -// -// Memory Relative Function. -// -VOID -ODM_AllocateMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID *pPtr, - IN u4Byte length - ); -VOID -ODM_FreeMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pPtr, - IN u4Byte length - ); - -VOID -ODM_MoveMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pDest, - IN PVOID pSrc, - IN u4Byte Length - ); - -s4Byte ODM_CompareMemory( - IN PDM_ODM_T pDM_Odm, - IN PVOID pBuf1, - IN PVOID pBuf2, - IN u4Byte length - ); - -void ODM_Memory_Set - (IN PDM_ODM_T pDM_Odm, - IN PVOID pbuf, - IN s1Byte value, - IN u4Byte length); - -// -// ODM MISC-spin lock relative API. -// -VOID -ODM_AcquireSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ); - -VOID -ODM_ReleaseSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ); - - -// -// ODM MISC-workitem relative API. -// -VOID -ODM_InitializeWorkItem( - IN PDM_ODM_T pDM_Odm, - IN PRT_WORK_ITEM pRtWorkItem, - IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, - IN PVOID pContext, - IN const char* szID - ); - -VOID -ODM_StartWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); - -VOID -ODM_StopWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); - -VOID -ODM_FreeWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); - -VOID -ODM_ScheduleWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); - -VOID -ODM_IsWorkItemScheduled( - IN PRT_WORK_ITEM pRtWorkItem - ); - -// -// ODM Timer relative API. -// -VOID -ODM_StallExecution( - IN u4Byte usDelay - ); - -VOID -ODM_delay_ms(IN u4Byte ms); - - - -VOID -ODM_delay_us(IN u4Byte us); - -VOID -ODM_sleep_ms(IN u4Byte ms); - -VOID -ODM_sleep_us(IN u4Byte us); - -VOID -ODM_SetTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN u4Byte msDelay - ); - -VOID -ODM_InitializeTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN RT_TIMER_CALL_BACK CallBackFunc, - IN PVOID pContext, - IN const char* szID - ); - -VOID -ODM_CancelTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ); - -VOID -ODM_ReleaseTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ); - -// -// ODM FW relative API. -// -VOID -ODM_FillH2CCmd( - IN PDM_ODM_T pDM_Odm, - IN u1Byte ElementID, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer -); - -u1Byte -phydm_c2H_content_parsing( - IN PVOID pDM_VOID, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf -); - -u8Byte -ODM_GetCurrentTime( - IN PDM_ODM_T pDM_Odm - ); -u8Byte -ODM_GetProgressingTime( - IN PDM_ODM_T pDM_Odm, - IN u8Byte Start_Time - ); - -#endif // __ODM_INTERFACE_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ + +// +// =========== Constant/Structure/Enum/... Define +// + + + +// +// =========== Macro Define +// + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +// _cat: implemented by Token-Pasting Operator. +#if 0 +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name) \ + ) +#endif + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#ifdef __ECOS +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#else + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#endif +/* +// only sample code +//#define _cat(_name, _ic_type, _func) \ +// ( \ +// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ +// _func##_ic(_name, _8195) \ +// ) +*/ + +// _name: name of register or bit. +// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" +// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +#ifdef __ECOS +#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) +#else +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) +#endif +typedef enum _PHYDM_H2C_CMD { + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + ODM_MAX_H2CCMD +}PHYDM_H2C_CMD; + +typedef enum _PHYDM_C2H_EVT { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT=14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}PHYDM_C2H_EVT; + +typedef enum _PHYDM_EXTEND_C2H_EVT { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +}PHYDM_EXTEND_C2H_EVT; + + +// +// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. +// Suggest HW team to use thread instead of workitem. Windows also support the feature. +// +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef void *PRT_WORK_ITEM ; +typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; +typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); + +#if 0 +typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; + +typedef struct _RT_WORK_ITEM +{ + + RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. + PVOID Adapter; // Pointer to Adapter object. + PVOID pContext; // Parameter to passed to CallBackFunc(). + RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. + u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. + PVOID pPlatformExt; // Pointer to platform-dependent extension. + BOOLEAN bFree; + char szID[36]; // An identity string of this workitem. +}RT_WORK_ITEM, *PRT_WORK_ITEM; + +#endif + + +#endif + +// +// =========== Extern Variable ??? It should be forbidden. +// + + +// +// =========== EXtern Function Prototype +// + + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ); + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ); + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ); + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +// +// Memory Relative Function. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ); +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ); + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ); + +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ); + +void ODM_Memory_Set + (IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length); + +// +// ODM MISC-spin lock relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + + +// +// ODM MISC-workitem relative API. +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ); + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ); + +VOID +ODM_delay_ms(IN u4Byte ms); + + + +VOID +ODM_delay_us(IN u4Byte us); + +VOID +ODM_sleep_ms(IN u4Byte ms); + +VOID +ODM_sleep_us(IN u4Byte us); + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ); + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +// +// ODM FW relative API. +// +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +u1Byte +phydm_c2H_content_parsing( + IN PVOID pDM_VOID, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +); + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ); +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ); + +#endif // __ODM_INTERFACE_H__ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_iqk.h b/package/kernel/rtl8192cd/phydm/phydm_iqk.h index 5315435e308..7eb0d892c4a 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_iqk.h +++ b/package/kernel/rtl8192cd/phydm/phydm_iqk.h @@ -1,67 +1,67 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMIQK_H__ -#define __PHYDMIQK_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define LOK_delay 1 -#define WBIQK_delay 10 -#define TX_IQK 0 -#define RX_IQK 1 -#define TXIQK 0 -#define RXIQK1 1 -#define RXIQK2 2 -#define kcount_limit_80m 2 -#define kcount_limit_others 4 -#define rxiqk_gs_limit 4 - - -#define NUM 4 -/*---------------------------End Define Parameters-------------------------------*/ - -typedef struct _IQK_INFORMATION { - BOOLEAN LOK_fail[NUM]; - BOOLEAN IQK_fail[2][NUM]; - u4Byte IQC_Matrix[2][NUM]; - u1Byte IQKtimes; - u4Byte RFReg18; - u4Byte lna_idx; - u1Byte rxiqk_step; - u1Byte tmp1bcc; - u1Byte kcount; - - u4Byte IQK_Channel[2]; - BOOLEAN IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ - u4Byte IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ - u4Byte IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ - u1Byte retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ - u1Byte gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ - u1Byte RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ - u4Byte LOK_IDAC[2][4]; /*channel / path*/ - u2Byte RXIQK_AGC[2][4]; /*channel / path*/ - u4Byte bypassIQK[2][4]; /*channel / 0xc94/0xe94*/ - u4Byte tmp_GNTWL; - BOOLEAN is_BTG; - BOOLEAN isbnd; - -} IQK_INFO, *PIQK_INFO; - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMIQK_H__ +#define __PHYDMIQK_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOK_delay 1 +#define WBIQK_delay 10 +#define TX_IQK 0 +#define RX_IQK 1 +#define TXIQK 0 +#define RXIQK1 1 +#define RXIQK2 2 +#define kcount_limit_80m 2 +#define kcount_limit_others 4 +#define rxiqk_gs_limit 4 + + +#define NUM 4 +/*---------------------------End Define Parameters-------------------------------*/ + +typedef struct _IQK_INFORMATION { + BOOLEAN LOK_fail[NUM]; + BOOLEAN IQK_fail[2][NUM]; + u4Byte IQC_Matrix[2][NUM]; + u1Byte IQKtimes; + u4Byte RFReg18; + u4Byte lna_idx; + u1Byte rxiqk_step; + u1Byte tmp1bcc; + u1Byte kcount; + + u4Byte IQK_Channel[2]; + BOOLEAN IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ + u4Byte IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ + u4Byte IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ + u1Byte retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ + u1Byte gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ + u1Byte RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ + u4Byte LOK_IDAC[2][4]; /*channel / path*/ + u2Byte RXIQK_AGC[2][4]; /*channel / path*/ + u4Byte bypassIQK[2][4]; /*channel / 0xc94/0xe94*/ + u4Byte tmp_GNTWL; + BOOLEAN is_BTG; + BOOLEAN isbnd; + +} IQK_INFO, *PIQK_INFO; + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_kfree.c b/package/kernel/rtl8192cd/phydm/phydm_kfree.c index a91cdee9b19..071064a44bd 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_kfree.c +++ b/package/kernel/rtl8192cd/phydm/phydm_kfree.c @@ -1,191 +1,191 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================*/ -/*include files*/ -/*============================================================*/ -#include "mp_precomp.h" -#include "phydm_precomp.h" - - -/* Add for KFree Feature Requested by RF David.*/ -/*This is a phydm API*/ - -VOID -phydm_SetKfreeToRF_8814A( - IN PVOID pDM_VOID, - IN u1Byte eRFPath, - IN u1Byte Data - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - BOOLEAN bOdd; - - if ((Data%2) != 0) { /*odd -> positive*/ - Data = Data - 1; - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 1); - bOdd = TRUE; - } else { /*even -> negative*/ - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 0); - bOdd = FALSE; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", bOdd)); - switch (Data) { - case 0: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; - break; - case 2: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; - break; - case 4: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; - break; - case 6: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; - break; - case 8: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; - break; - case 10: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; - break; - case 12: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; - break; - case 14: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; - break; - case 16: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; - break; - case 18: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; - break; - case 20: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 5); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 5; - break; - - default: - break; - } - - if (bOdd == FALSE) { - /*that means Kfree offset is negative, we need to record it.*/ - pRFCalibrateInfo->KfreeOffset[eRFPath] = (-1)*pRFCalibrateInfo->KfreeOffset[eRFPath]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); - -} - - -VOID -phydm_SetKfreeToRF( - IN PVOID pDM_VOID, - IN u1Byte eRFPath, - IN u1Byte Data - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_SetKfreeToRF_8814A(pDM_Odm, eRFPath, Data); -} - -VOID -phydm_ConfigKFree( - IN PVOID pDM_VOID, - IN u1Byte channelToSW, - IN pu1Byte kfreeTable - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte rfpath = 0, maxRFpath = 0; - u1Byte channelIdx = 0; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - maxRFpath = 4; /*0~3*/ - else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) - maxRFpath = 2; /*0~1*/ - else - maxRFpath = 1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n")); - - if (pRFCalibrateInfo->RegRfKFreeEnable == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == 2, Disable\n")); - return; - } else if (pRFCalibrateInfo->RegRfKFreeEnable == 1 || pRFCalibrateInfo->RegRfKFreeEnable == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == TRUE\n")); - /*Make sure the targetval is defined*/ - if (((pRFCalibrateInfo->RegRfKFreeEnable == 1) && (kfreeTable[0] != 0xFF)) || (pRFCalibrateInfo->RfKFreeEnable == TRUE)) { - /*if kfreeTable[0] == 0xff, means no Kfree*/ - if (*pDM_Odm->pBandType == ODM_BAND_2_4G) { - if (channelToSW <= 14 && channelToSW >= 1) - channelIdx = PHYDM_2G; - } else if (*pDM_Odm->pBandType == ODM_BAND_5G) { - if (channelToSW >= 36 && channelToSW <= 48) - channelIdx = PHYDM_5GLB1; - if (channelToSW >= 52 && channelToSW <= 64) - channelIdx = PHYDM_5GLB2; - if (channelToSW >= 100 && channelToSW <= 120) - channelIdx = PHYDM_5GMB1; - if (channelToSW >= 124 && channelToSW <= 144) - channelIdx = PHYDM_5GMB2; - if (channelToSW >= 149 && channelToSW <= 177) - channelIdx = PHYDM_5GHB; - } - - for (rfpath = ODM_RF_PATH_A; rfpath < maxRFpath; rfpath++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfreeTable[channelIdx*maxRFpath + rfpath])); - phydm_SetKfreeToRF(pDM_Odm, rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]); - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n")); - return; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n")); -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +/* Add for KFree Feature Requested by RF David.*/ +/*This is a phydm API*/ + +VOID +phydm_SetKfreeToRF_8814A( + IN PVOID pDM_VOID, + IN u1Byte eRFPath, + IN u1Byte Data + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + BOOLEAN bOdd; + + if ((Data%2) != 0) { /*odd -> positive*/ + Data = Data - 1; + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 1); + bOdd = TRUE; + } else { /*even -> negative*/ + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 0); + bOdd = FALSE; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", bOdd)); + switch (Data) { + case 0: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; + break; + case 2: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; + break; + case 4: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; + break; + case 6: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; + break; + case 8: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; + break; + case 10: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; + break; + case 12: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; + break; + case 14: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; + break; + case 16: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; + break; + case 18: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; + break; + case 20: + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); + ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 5); + pRFCalibrateInfo->KfreeOffset[eRFPath] = 5; + break; + + default: + break; + } + + if (bOdd == FALSE) { + /*that means Kfree offset is negative, we need to record it.*/ + pRFCalibrateInfo->KfreeOffset[eRFPath] = (-1)*pRFCalibrateInfo->KfreeOffset[eRFPath]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); + +} + + +VOID +phydm_SetKfreeToRF( + IN PVOID pDM_VOID, + IN u1Byte eRFPath, + IN u1Byte Data + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_SetKfreeToRF_8814A(pDM_Odm, eRFPath, Data); +} + +VOID +phydm_ConfigKFree( + IN PVOID pDM_VOID, + IN u1Byte channelToSW, + IN pu1Byte kfreeTable + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte rfpath = 0, maxRFpath = 0; + u1Byte channelIdx = 0; + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + maxRFpath = 4; /*0~3*/ + else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) + maxRFpath = 2; /*0~1*/ + else + maxRFpath = 1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n")); + + if (pRFCalibrateInfo->RegRfKFreeEnable == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == 2, Disable\n")); + return; + } else if (pRFCalibrateInfo->RegRfKFreeEnable == 1 || pRFCalibrateInfo->RegRfKFreeEnable == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == TRUE\n")); + /*Make sure the targetval is defined*/ + if (((pRFCalibrateInfo->RegRfKFreeEnable == 1) && (kfreeTable[0] != 0xFF)) || (pRFCalibrateInfo->RfKFreeEnable == TRUE)) { + /*if kfreeTable[0] == 0xff, means no Kfree*/ + if (*pDM_Odm->pBandType == ODM_BAND_2_4G) { + if (channelToSW <= 14 && channelToSW >= 1) + channelIdx = PHYDM_2G; + } else if (*pDM_Odm->pBandType == ODM_BAND_5G) { + if (channelToSW >= 36 && channelToSW <= 48) + channelIdx = PHYDM_5GLB1; + if (channelToSW >= 52 && channelToSW <= 64) + channelIdx = PHYDM_5GLB2; + if (channelToSW >= 100 && channelToSW <= 120) + channelIdx = PHYDM_5GMB1; + if (channelToSW >= 124 && channelToSW <= 144) + channelIdx = PHYDM_5GMB2; + if (channelToSW >= 149 && channelToSW <= 177) + channelIdx = PHYDM_5GHB; + } + + for (rfpath = ODM_RF_PATH_A; rfpath < maxRFpath; rfpath++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfreeTable[channelIdx*maxRFpath + rfpath])); + phydm_SetKfreeToRF(pDM_Odm, rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]); + } + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n")); + return; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n")); +} + diff --git a/package/kernel/rtl8192cd/phydm/phydm_kfree.h b/package/kernel/rtl8192cd/phydm/phydm_kfree.h index d95e7cb8af6..d2c75add7a8 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_kfree.h +++ b/package/kernel/rtl8192cd/phydm/phydm_kfree.h @@ -1,45 +1,45 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMKFREE_H__ -#define __PHYDKFREE_H__ - -#define KFREE_VERSION "1.0" - -typedef enum tag_phydm_kfree_channeltosw { - PHYDM_2G = 0, - PHYDM_5GLB1 = 1, - PHYDM_5GLB2 = 2, - PHYDM_5GMB1 = 3, - PHYDM_5GMB2 = 4, - PHYDM_5GHB = 5, -} PHYDM_KFREE_CHANNELTOSW; - - -VOID -phydm_ConfigKFree( - IN PVOID pDM_VOID, - IN u1Byte channelToSW, - IN pu1Byte kfreeTable -); - - -#endif + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMKFREE_H__ +#define __PHYDKFREE_H__ + +#define KFREE_VERSION "1.0" + +typedef enum tag_phydm_kfree_channeltosw { + PHYDM_2G = 0, + PHYDM_5GLB1 = 1, + PHYDM_5GLB2 = 2, + PHYDM_5GMB1 = 3, + PHYDM_5GMB2 = 4, + PHYDM_5GHB = 5, +} PHYDM_KFREE_CHANNELTOSW; + + +VOID +phydm_ConfigKFree( + IN PVOID pDM_VOID, + IN u1Byte channelToSW, + IN pu1Byte kfreeTable +); + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.c b/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.c index b3c15a99180..baa1098808c 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.c +++ b/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.c @@ -1,376 +1,376 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//================================================= -// This function is for inband noise test utility only -// To obtain the inband noise level(dbm), do the following. -// 1. disable DIG and Power Saving -// 2. Set initial gain = 0x1a -// 3. Stop updating idle time pwer report (for driver read) -// - 0x80c[25] -// -//================================================= - -#define Valid_Min -35 -#define Valid_Max 10 -#define ValidCnt 5 - -s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time) -{ - u4Byte tmp4b; - u1Byte max_rf_path=0,rf_path; - u1Byte reg_c50, reg_c58,valid_done=0; - struct noise_level noise_data; - u8Byte start = 0, func_start = 0, func_end = 0; - - func_start = ODM_GetCurrentTime(pDM_Odm); - pDM_Odm->noise_level.noise_all = 0; - - if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) - max_rf_path = 2; - else - max_rf_path = 1; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n")); - - ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level)); - - // Step 1. Disable DIG && Set initial gain. - - if (bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); - - start = ODM_GetCurrentTime(pDM_Odm); - while(1) { - - //Stop updating idle time pwer report (for driver read) - ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1); - - //Read Noise Floor Report - tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord ); - - //update idle time pwer report per 5us - ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0); - - ODM_delay_us(5); - - noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff); - noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8); - - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path]; - noise_data.sval[rf_path] /= 2; - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n", - noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); - - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if (!(noise_data.valid_cnt[rf_path] < ValidCnt) || !(noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) { - continue; - } - - noise_data.valid_cnt[rf_path]++; - noise_data.sum[rf_path] += noise_data.sval[rf_path]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path])); - if (noise_data.valid_cnt[rf_path] == ValidCnt) { - valid_done++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); - } - } - - if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time)) { - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if(noise_data.valid_cnt[rf_path]) - noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; - else - noise_data.sum[rf_path] = 0; - } - break; - } - } - reg_c50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); - reg_c50 &= ~BIT7; - pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (s1Byte)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; - - if (max_rf_path == 2) { - reg_c58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); - reg_c58 &= ~BIT7; - pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (s1Byte)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; - } - pDM_Odm->noise_level.noise_all /= max_rf_path; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n", - pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B])); - - // - // Step 4. Recover the Dig - // - if(bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); - - func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); - return pDM_Odm->noise_level.noise_all; - -} - -s16 -phydm_idle_noise_measurement_ac( - PDM_ODM_T pDM_Odm, - u8 is_pause_dig, - u8 igi_value, - u32 max_time - ) -{ - u32 tmp4b; - u8 max_rf_path = 0, rf_path; - u8 reg_c50, reg_e50, valid_done=0; - u64 start = 0, func_start = 0, func_end = 0; - struct noise_level noise_data; - - func_start = ODM_GetCurrentTime(pDM_Odm); - pDM_Odm->noise_level.noise_all = 0; - - if ((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) - max_rf_path = 2; - else - max_rf_path = 1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("phydm_idle_noise_measurement_ac==>\n")); - - ODM_Memory_Set(pDM_Odm, &noise_data, 0, sizeof(struct noise_level)); - - /*Step 1. Disable DIG && Set initial gain.*/ - - if (is_pause_dig) - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - - /*Step 2. Get noise power level*/ - start = ODM_GetCurrentTime(pDM_Odm); - - while(1) { - - /*Stop updating idle time pwer report (for driver read)*/ - ODM_SetBBReg(pDM_Odm, 0x9e4, BIT(30), 0x1); - - /*Read Noise Floor Report*/ - tmp4b = ODM_GetBBReg(pDM_Odm, 0xff0, bMaskDWord); - - /*update idle time pwer report per 5us*/ - ODM_SetBBReg(pDM_Odm, 0x9e4, BIT(30), 0x0); - - ODM_delay_us(5); - - noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff); - noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); - - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; - noise_data.sval[rf_path] = noise_data.sval[rf_path] >> 1; - } - - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if (!(noise_data.valid_cnt[rf_path] < ValidCnt) || !(noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) { - continue; - } - - noise_data.valid_cnt[rf_path]++; - noise_data.sum[rf_path] += noise_data.sval[rf_path]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path])); - if (noise_data.valid_cnt[rf_path] == ValidCnt) { - valid_done++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); - } - } - - if ((valid_done == max_rf_path) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if (noise_data.valid_cnt[rf_path]) - noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; - else - noise_data.sum[rf_path] = 0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Path%d, avg of sval = %d\n", rf_path, noise_data.sum[rf_path])); - } - break; - } - } - reg_c50 = (u8)ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); - reg_c50 &= ~ BIT(7); - pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; - - if (max_rf_path == 2) { - reg_e50 = (u8)ODM_GetBBReg(pDM_Odm, 0xe50, bMaskByte0); - reg_e50 &= ~ BIT(7); - pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (s8)(-110 + reg_e50 + noise_data.sum[ODM_RF_PATH_B]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; - } - pDM_Odm->noise_level.noise_all /= max_rf_path; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("noise_a = %d, noise_b = %d, noise_all = %d\n", - pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B], - pDM_Odm->noise_level.noise_all)); - - /*Step 3. Recover the Dig*/ - if (is_pause_dig) - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); - func_end = ODM_GetProgressingTime(pDM_Odm, func_start) ; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("phydm_idle_noise_measurement_ac<==\n")); - return pDM_Odm->noise_level.noise_all; - -} - -s2Byte -odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time - ) -{ - s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ - s4Byte value32, pwdb_A = 0, sval, noise, sum = 0; - BOOLEAN pd_flag; - u1Byte valid_cnt = 0; - u8Byte start = 0, func_start = 0, func_end = 0; - - if (pDM_Odm->SupportICType & ODM_RTL8822B) - return phydm_idle_noise_measurement_ac(pDM_Odm, bPauseDIG, IGIValue, max_time); - - if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) - return 0; - - func_start = ODM_GetCurrentTime(pDM_Odm); - pDM_Odm->noise_level.noise_all = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n")); - - /* Step 1. Disable DIG && Set initial gain. */ - if (bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); - - /* Step 2. Disable all power save for read registers */ - /*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */ - - /* Step 3. Get noise power level */ - start = ODM_GetCurrentTime(pDM_Odm); - - /* Step 4. Get noise power level */ - while (1) { - /*Set IGI=0x1C */ - ODM_Write_DIG(pDM_Odm, 0x1C); - /*stop CK320&CK88 */ - ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1); - /*Read Path-A */ - ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/ - - rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ - rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ - - pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31); - - /*Not in packet detection period or Tx state */ - if ((!pd_flag) || (rxi_buf_anta != 0x200)) { - /*sign conversion*/ - rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10); - rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10); - - pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); - } - /*Start CK320&CK88*/ - ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0); - /*BB Reset*/ - ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0)); - ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0); - /*PMAC Reset*/ - ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) & (~BIT0)); - ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) | BIT0); - /*CCK Reset*/ - if (ODM_Read1Byte(pDM_Odm, 0x80B) & BIT4) { - ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) & (~BIT4)); - ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) | BIT4); - } - - sval = pwdb_A; - - if (sval < 0 && sval >= -27) { - if (valid_cnt < ValidCnt) { - valid_cnt++; - sum += sval; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); - if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { - sum /= valid_cnt; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); - break; - } - } - } - } - - /*ADC backoff is 12dB,*/ - /*Ptarget=0x1C-110=-82dBm*/ - noise = sum + 12 + 0x1C - 110; - - /*Offset*/ - noise = noise - 3; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); - pDM_Odm->noise_level.noise_all = (s2Byte)noise; - - /* Step 4. Recover the Dig*/ - if (bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); - - func_end = ODM_GetProgressingTime(pDM_Odm, func_start); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n")); - - return pDM_Odm->noise_level.noise_all; -} - - - -s2Byte -ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time) -{ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); - else - return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//================================================= +// This function is for inband noise test utility only +// To obtain the inband noise level(dbm), do the following. +// 1. disable DIG and Power Saving +// 2. Set initial gain = 0x1a +// 3. Stop updating idle time pwer report (for driver read) +// - 0x80c[25] +// +//================================================= + +#define Valid_Min -35 +#define Valid_Max 10 +#define ValidCnt 5 + +s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time) +{ + u4Byte tmp4b; + u1Byte max_rf_path=0,rf_path; + u1Byte reg_c50, reg_c58,valid_done=0; + struct noise_level noise_data; + u8Byte start = 0, func_start = 0, func_end = 0; + + func_start = ODM_GetCurrentTime(pDM_Odm); + pDM_Odm->noise_level.noise_all = 0; + + if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) + max_rf_path = 2; + else + max_rf_path = 1; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n")); + + ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level)); + + // Step 1. Disable DIG && Set initial gain. + + if (bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); + + start = ODM_GetCurrentTime(pDM_Odm); + while(1) { + + //Stop updating idle time pwer report (for driver read) + ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1); + + //Read Noise Floor Report + tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord ); + + //update idle time pwer report per 5us + ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0); + + ODM_delay_us(5); + + noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff); + noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8); + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path]; + noise_data.sval[rf_path] /= 2; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n", + noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (!(noise_data.valid_cnt[rf_path] < ValidCnt) || !(noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) { + continue; + } + + noise_data.valid_cnt[rf_path]++; + noise_data.sum[rf_path] += noise_data.sval[rf_path]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path])); + if (noise_data.valid_cnt[rf_path] == ValidCnt) { + valid_done++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); + } + } + + if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time)) { + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if(noise_data.valid_cnt[rf_path]) + noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; + else + noise_data.sum[rf_path] = 0; + } + break; + } + } + reg_c50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); + reg_c50 &= ~BIT7; + pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (s1Byte)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; + + if (max_rf_path == 2) { + reg_c58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); + reg_c58 &= ~BIT7; + pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (s1Byte)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; + } + pDM_Odm->noise_level.noise_all /= max_rf_path; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n", + pDM_Odm->noise_level.noise[ODM_RF_PATH_A], + pDM_Odm->noise_level.noise[ODM_RF_PATH_B])); + + // + // Step 4. Recover the Dig + // + if(bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); + + func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); + return pDM_Odm->noise_level.noise_all; + +} + +s16 +phydm_idle_noise_measurement_ac( + PDM_ODM_T pDM_Odm, + u8 is_pause_dig, + u8 igi_value, + u32 max_time + ) +{ + u32 tmp4b; + u8 max_rf_path = 0, rf_path; + u8 reg_c50, reg_e50, valid_done=0; + u64 start = 0, func_start = 0, func_end = 0; + struct noise_level noise_data; + + func_start = ODM_GetCurrentTime(pDM_Odm); + pDM_Odm->noise_level.noise_all = 0; + + if ((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) + max_rf_path = 2; + else + max_rf_path = 1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("phydm_idle_noise_measurement_ac==>\n")); + + ODM_Memory_Set(pDM_Odm, &noise_data, 0, sizeof(struct noise_level)); + + /*Step 1. Disable DIG && Set initial gain.*/ + + if (is_pause_dig) + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); + + /*Step 2. Get noise power level*/ + start = ODM_GetCurrentTime(pDM_Odm); + + while(1) { + + /*Stop updating idle time pwer report (for driver read)*/ + ODM_SetBBReg(pDM_Odm, 0x9e4, BIT(30), 0x1); + + /*Read Noise Floor Report*/ + tmp4b = ODM_GetBBReg(pDM_Odm, 0xff0, bMaskDWord); + + /*update idle time pwer report per 5us*/ + ODM_SetBBReg(pDM_Odm, 0x9e4, BIT(30), 0x0); + + ODM_delay_us(5); + + noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; + noise_data.sval[rf_path] = noise_data.sval[rf_path] >> 1; + } + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (!(noise_data.valid_cnt[rf_path] < ValidCnt) || !(noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) { + continue; + } + + noise_data.valid_cnt[rf_path]++; + noise_data.sum[rf_path] += noise_data.sval[rf_path]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path])); + if (noise_data.valid_cnt[rf_path] == ValidCnt) { + valid_done++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); + } + } + + if ((valid_done == max_rf_path) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (noise_data.valid_cnt[rf_path]) + noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; + else + noise_data.sum[rf_path] = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Path%d, avg of sval = %d\n", rf_path, noise_data.sum[rf_path])); + } + break; + } + } + reg_c50 = (u8)ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); + reg_c50 &= ~ BIT(7); + pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; + + if (max_rf_path == 2) { + reg_e50 = (u8)ODM_GetBBReg(pDM_Odm, 0xe50, bMaskByte0); + reg_e50 &= ~ BIT(7); + pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (s8)(-110 + reg_e50 + noise_data.sum[ODM_RF_PATH_B]); + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; + } + pDM_Odm->noise_level.noise_all /= max_rf_path; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("noise_a = %d, noise_b = %d, noise_all = %d\n", + pDM_Odm->noise_level.noise[ODM_RF_PATH_A], + pDM_Odm->noise_level.noise[ODM_RF_PATH_B], + pDM_Odm->noise_level.noise_all)); + + /*Step 3. Recover the Dig*/ + if (is_pause_dig) + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + func_end = ODM_GetProgressingTime(pDM_Odm, func_start) ; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("phydm_idle_noise_measurement_ac<==\n")); + return pDM_Odm->noise_level.noise_all; + +} + +s2Byte +odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time + ) +{ + s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ + s4Byte value32, pwdb_A = 0, sval, noise, sum = 0; + BOOLEAN pd_flag; + u1Byte valid_cnt = 0; + u8Byte start = 0, func_start = 0, func_end = 0; + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + return phydm_idle_noise_measurement_ac(pDM_Odm, bPauseDIG, IGIValue, max_time); + + if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) + return 0; + + func_start = ODM_GetCurrentTime(pDM_Odm); + pDM_Odm->noise_level.noise_all = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n")); + + /* Step 1. Disable DIG && Set initial gain. */ + if (bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); + + /* Step 2. Disable all power save for read registers */ + /*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */ + + /* Step 3. Get noise power level */ + start = ODM_GetCurrentTime(pDM_Odm); + + /* Step 4. Get noise power level */ + while (1) { + /*Set IGI=0x1C */ + ODM_Write_DIG(pDM_Odm, 0x1C); + /*stop CK320&CK88 */ + ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1); + /*Read Path-A */ + ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/ + + rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ + rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ + + pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31); + + /*Not in packet detection period or Tx state */ + if ((!pd_flag) || (rxi_buf_anta != 0x200)) { + /*sign conversion*/ + rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10); + rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10); + + pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); + } + /*Start CK320&CK88*/ + ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0); + /*BB Reset*/ + ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0); + /*PMAC Reset*/ + ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) & (~BIT0)); + ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) | BIT0); + /*CCK Reset*/ + if (ODM_Read1Byte(pDM_Odm, 0x80B) & BIT4) { + ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) & (~BIT4)); + ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) | BIT4); + } + + sval = pwdb_A; + + if (sval < 0 && sval >= -27) { + if (valid_cnt < ValidCnt) { + valid_cnt++; + sum += sval; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); + if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { + sum /= valid_cnt; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); + break; + } + } + } + } + + /*ADC backoff is 12dB,*/ + /*Ptarget=0x1C-110=-82dBm*/ + noise = sum + 12 + 0x1C - 110; + + /*Offset*/ + noise = noise - 3; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); + pDM_Odm->noise_level.noise_all = (s2Byte)noise; + + /* Step 4. Recover the Dig*/ + if (bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); + + func_end = ODM_GetProgressingTime(pDM_Odm, func_start); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n")); + + return pDM_Odm->noise_level.noise_all; +} + + + +s2Byte +ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); + else + return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); +} + diff --git a/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.h b/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.h index 1ae0c548b05..9303d2c2106 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.h +++ b/package/kernel/rtl8192cd/phydm/phydm_noisemonitor.h @@ -1,41 +1,41 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - *****************************************************************************/ -#ifndef __ODMNOISEMONITOR_H__ -#define __ODMNOISEMONITOR_H__ - -#define ODM_MAX_CHANNEL_NUM 38//14+24 -struct noise_level -{ - u1Byte value[MAX_RF_PATH]; - s1Byte sval[MAX_RF_PATH]; - s4Byte sum[MAX_RF_PATH]; - u1Byte valid[MAX_RF_PATH]; - u1Byte valid_cnt[MAX_RF_PATH]; -}; - - -typedef struct _ODM_NOISE_MONITOR_ -{ - s1Byte noise[MAX_RF_PATH]; - s2Byte noise_all; -}ODM_NOISE_MONITOR; - -s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define ODM_MAX_CHANNEL_NUM 38//14+24 +struct noise_level +{ + u1Byte value[MAX_RF_PATH]; + s1Byte sval[MAX_RF_PATH]; + s4Byte sum[MAX_RF_PATH]; + u1Byte valid[MAX_RF_PATH]; + u1Byte valid_cnt[MAX_RF_PATH]; +}; + + +typedef struct _ODM_NOISE_MONITOR_ +{ + s1Byte noise[MAX_RF_PATH]; + s2Byte noise_all; +}ODM_NOISE_MONITOR; + +s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_pathdiv.c b/package/kernel/rtl8192cd/phydm/phydm_pathdiv.c index 0ddeba391a6..96faddff1c8 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_pathdiv.c +++ b/package/kernel/rtl8192cd/phydm/phydm_pathdiv.c @@ -1,810 +1,810 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if(defined(CONFIG_PATH_DIVERSITY)) -#if RTL8814A_SUPPORT - -VOID -phydm_dtp_fix_tx_path( - IN PVOID pDM_VOID, - IN u1Byte path - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - u1Byte i,num_enable_path=0; - - if(path==pDM_PathDiv->pre_tx_path) - { - return; - } - else - { - pDM_PathDiv->pre_tx_path=path; - } - - ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3); - - for(i=0; i<4; i++) - { - if(path&BIT(i)) - num_enable_path++; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path)); - - if(num_enable_path == 1) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - - if(path==PHYDM_A)//1-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - } - else if(path==PHYDM_B)//1-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - } - else if(path==PHYDM_C)//1-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); - - } - else if(path==PHYDM_D)//1-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0); - } - - } - else if(num_enable_path == 2) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); - - if(path==PHYDM_AB)//2-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - } - else if(path==PHYDM_AC)//2-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - } - else if(path==PHYDM_AD)//2-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); - } - else if(path==PHYDM_BC)//2-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - } - else if(path==PHYDM_BD)//2-5 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); - } - else if(path==PHYDM_CD)//2-6 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); - } - - } - else if(num_enable_path == 3) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path); - - if(path==PHYDM_ABC)//3-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2); - } - else if(path==PHYDM_ABD)//3-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); - - } - else if(path==PHYDM_ACD)//3-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); - } - else if(path==PHYDM_BCD)//3-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); - } - } - else if(num_enable_path == 4) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); - } - -} - -VOID -phydm_find_default_path( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0; - u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0; - - //2 Default Path Selection By RSSI - - rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ; - rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ; - rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ; - rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ; - - - pDM_PathDiv->path_a_sum_all = 0; - pDM_PathDiv->path_a_cnt_all = 0; - pDM_PathDiv->path_b_sum_all = 0; - pDM_PathDiv->path_b_cnt_all = 0; - pDM_PathDiv->path_c_sum_all = 0; - pDM_PathDiv->path_c_cnt_all = 0; - pDM_PathDiv->path_d_sum_all = 0; - pDM_PathDiv->path_d_cnt_all = 0; - - if(pDM_PathDiv->use_path_a_as_default_ant == 1) - { - rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3; - - if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd ) - { - pDM_PathDiv->is_pathA_exist=TRUE; - pDM_PathDiv->default_path=PATH_A; - } - else - { - pDM_PathDiv->is_pathA_exist=FALSE; - } - } - else - { - if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d)) - pDM_PathDiv->default_path=PATH_A; - else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d)) - pDM_PathDiv->default_path=PATH_B; - else if( rssi_avg_c >=rssi_avg_d) - pDM_PathDiv->default_path=PATH_C; - else - pDM_PathDiv->default_path=PATH_D; - } - - -} - - -VOID -phydm_candidate_dtp_update( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - pDM_PathDiv->num_candidate=3; - - if(pDM_PathDiv->use_path_a_as_default_ant == 1) - { - if(pDM_PathDiv->num_tx_path==3) - { - if(pDM_PathDiv->is_pathA_exist) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; - } - else // use path BCD - { - pDM_PathDiv->num_candidate=1; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD); - return; - } - } - else if(pDM_PathDiv->num_tx_path==2) - { - if(pDM_PathDiv->is_pathA_exist) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_AC; - pDM_PathDiv->ant_candidate_3 = PHYDM_AD; - } - else - { - pDM_PathDiv->ant_candidate_1 = PHYDM_BC; - pDM_PathDiv->ant_candidate_2 = PHYDM_BD; - pDM_PathDiv->ant_candidate_3 = PHYDM_CD; - } - } - } - else - { - //2 3 TX Mode - if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4 - { - if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; - } - else if(pDM_PathDiv->default_path==PATH_B) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; - } - else if(pDM_PathDiv->default_path == PATH_C) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; - } - else if(pDM_PathDiv->default_path == PATH_D) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; - } - } - - //2 2 TX Mode - else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4 - { - if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_AC; - pDM_PathDiv->ant_candidate_3 = PHYDM_AD; - } - else if(pDM_PathDiv->default_path==PATH_B) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_BC; - pDM_PathDiv->ant_candidate_3 = PHYDM_BD; - } - else if(pDM_PathDiv->default_path == PATH_C) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AC; - pDM_PathDiv->ant_candidate_2 = PHYDM_BC; - pDM_PathDiv->ant_candidate_3 = PHYDM_CD; - } - else if(pDM_PathDiv->default_path == PATH_D) - { - pDM_PathDiv->ant_candidate_1= PHYDM_AD; - pDM_PathDiv->ant_candidate_2 = PHYDM_BD; - pDM_PathDiv->ant_candidate_3= PHYDM_CD; - } - } - } -} - - -VOID -phydm_dynamic_tx_path( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - PSTA_INFO_T pEntry; - u4Byte i; - u1Byte num_client=0; - u1Byte H2C_Parameter[6] ={0}; - - - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); - - if(pDM_PathDiv->bBecomeLinked == TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); - pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; - } - return; - } - else - { - if(pDM_PathDiv->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); - pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; - } - } - - //2 [Period CTRL] - if(pDM_PathDiv->dtp_period >=2) - { - pDM_PathDiv->dtp_period=0; - } - else - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period)); - pDM_PathDiv->dtp_period++; - return; - } - - - //2 [Fix Path] - if (pDM_Odm->path_select != PHYDM_AUTO_PATH) - { - return; - } - - //2 [Check Bfer] - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (BEAMFORMING_SUPPORT == 1) - { - BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); - - if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off - { - if( pDM_PathDiv->fix_path_bfer == 0) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n")); - pDM_PathDiv->fix_path_bfer = 1 ; - } - return; - } - else // BFmer Off && Div Off -> Div On - { - if( pDM_PathDiv->fix_path_bfer == 1 ) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n")); - pDM_PathDiv->fix_path_bfer = 0; - } - } - } - #endif - #endif - - if(pDM_PathDiv->use_path_a_as_default_ant ==1) - { - phydm_find_default_path(pDM_Odm); - phydm_candidate_dtp_update(pDM_Odm); - } - else - { - if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT) - { - phydm_find_default_path(pDM_Odm); - phydm_candidate_dtp_update(pDM_Odm); - pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1; - } - - else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1) - { - pDM_PathDiv->dtp_check_patha_counter++; - - if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD) - { - pDM_PathDiv->dtp_check_patha_counter=0; - pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; - } - //2 Search space update - else - { - // 1. find the worst candidate - - - // 2. repalce the worst candidate - } - } - } - - //2 Dynamic Path Selection H2C - - if(pDM_PathDiv->num_candidate == 1) - { - return; - } - else - { - H2C_Parameter[0] = pDM_PathDiv->num_candidate; - H2C_Parameter[1] = pDM_PathDiv->num_tx_path; - H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1; - H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2; - H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3; - - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter); - } - -} - - - -VOID -phydm_dynamic_tx_path_init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - PADAPTER pAdapter = pDM_Odm->Adapter; - #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism; - #endif - u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; - u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; - - #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ; - #else - pDM_PathDiv->is_u3_mode = 1; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode)); - - memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); - memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); - - pDM_PathDiv->use_path_a_as_default_ant= 1; - pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; - pDM_Odm->path_select = PHYDM_AUTO_PATH; - pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV; - - - if(pDM_PathDiv->is_u3_mode ) - { - pDM_PathDiv->num_tx_path=3; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/ - - } - else - { - pDM_PathDiv->num_tx_path=2; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/ - } - -} - - -VOID -phydm_process_rssi_for_path_div( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - - if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) - { - if(pPktinfo->DataRate > ODM_RATE11M) - { - if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV) - { - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - { - pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0]; - pDM_PathDiv->path_a_cnt_all++; - - pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1]; - pDM_PathDiv->path_b_cnt_all++; - - pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2]; - pDM_PathDiv->path_c_cnt_all++; - - pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3]; - pDM_PathDiv->path_d_cnt_all++; - } - #endif - } - else - { - pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0]; - pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++; - - pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1]; - pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++; - } - } - } - - -} - -#endif //#if RTL8814A_SUPPORT - -VOID -odm_pathdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pDM_Odm->path_select = (dm_value[0] & 0xf); - PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select )); - - //2 [Fix Path] - if (pDM_Odm->path_select != PHYDM_AUTO_PATH) - { - PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n", - ((pDM_Odm->path_select) & 0x1)?"A":"", - ((pDM_Odm->path_select) & 0x2)?"B":"", - ((pDM_Odm->path_select) & 0x4)?"C":"", - ((pDM_Odm->path_select) & 0x8)?"D":"" )); - - phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select ); - } - else - { - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path")); - } -} - -#endif // #if(defined(CONFIG_PATH_DIVERSITY)) - -VOID -phydm_c2h_dtp_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -) -{ -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - - u1Byte macid = CmdBuf[0]; - u1Byte target = CmdBuf[1]; - u1Byte nsc_1 = CmdBuf[2]; - u1Byte nsc_2 = CmdBuf[3]; - u1Byte nsc_3 = CmdBuf[4]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target)); - /* - if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) - { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1); - } - else if( nsc_2 >= nsc_3) - { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2); - } - else - { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3); - } - */ -#endif -} - -VOID -odm_PathDiversity( - IN PVOID pDM_VOID -) -{ -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); - return; - } - - #if RTL8812A_SUPPORT - - if(pDM_Odm->SupportICType & ODM_RTL8812) - ODM_PathDiversity_8812A(pDM_Odm); - else - #endif - - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_dynamic_tx_path(pDM_Odm); - else - #endif - {} -#endif -} - -VOID -odm_PathDiversityInit( - IN PVOID pDM_VOID -) -{ -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/ - - if(pDM_Odm->mp_mode == TRUE) - return; - - if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); - return; - } - -#if RTL8812A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8812) - ODM_PathDiversityInit_8812A(pDM_Odm); - else - #endif - - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_dynamic_tx_path_init(pDM_Odm); - else - #endif - {} -#endif -} - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -// -// 2011/12/02 MH Copy from MP oursrc for temporarily test. -// - -VOID -odm_PathDivChkAntSwitchCallback( - PRT_TIMER pTimer -) -{ -} - -VOID -odm_PathDivChkAntSwitchWorkitemCallback( - IN PVOID pContext - ) -{ -} - -VOID -odm_CCKTXPathDiversityCallback( - PRT_TIMER pTimer -) -{ -} - -VOID -odm_CCKTXPathDiversityWorkItemCallback( - IN PVOID pContext - ) -{ -} -u1Byte -odm_SwAntDivSelectScanChnl( - IN PADAPTER Adapter - ) -{ - return 0; -} -VOID -odm_SwAntDivConstructScanChnl( - IN PADAPTER Adapter, - IN u1Byte ScanChnl - ) -{ -} - -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if(defined(CONFIG_PATH_DIVERSITY)) +#if RTL8814A_SUPPORT + +VOID +phydm_dtp_fix_tx_path( + IN PVOID pDM_VOID, + IN u1Byte path + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + u1Byte i,num_enable_path=0; + + if(path==pDM_PathDiv->pre_tx_path) + { + return; + } + else + { + pDM_PathDiv->pre_tx_path=path; + } + + ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3); + + for(i=0; i<4; i++) + { + if(path&BIT(i)) + num_enable_path++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path)); + + if(num_enable_path == 1) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + + if(path==PHYDM_A)//1-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + } + else if(path==PHYDM_B)//1-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + } + else if(path==PHYDM_C)//1-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); + + } + else if(path==PHYDM_D)//1-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0); + } + + } + else if(num_enable_path == 2) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); + + if(path==PHYDM_AB)//2-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + } + else if(path==PHYDM_AC)//2-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + } + else if(path==PHYDM_AD)//2-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + else if(path==PHYDM_BC)//2-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + } + else if(path==PHYDM_BD)//2-5 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + else if(path==PHYDM_CD)//2-6 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + + } + else if(num_enable_path == 3) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path); + + if(path==PHYDM_ABC)//3-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2); + } + else if(path==PHYDM_ABD)//3-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + + } + else if(path==PHYDM_ACD)//3-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + } + else if(path==PHYDM_BCD)//3-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + } + } + else if(num_enable_path == 4) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); + } + +} + +VOID +phydm_find_default_path( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0; + u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0; + + //2 Default Path Selection By RSSI + + rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ; + rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ; + rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ; + rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ; + + + pDM_PathDiv->path_a_sum_all = 0; + pDM_PathDiv->path_a_cnt_all = 0; + pDM_PathDiv->path_b_sum_all = 0; + pDM_PathDiv->path_b_cnt_all = 0; + pDM_PathDiv->path_c_sum_all = 0; + pDM_PathDiv->path_c_cnt_all = 0; + pDM_PathDiv->path_d_sum_all = 0; + pDM_PathDiv->path_d_cnt_all = 0; + + if(pDM_PathDiv->use_path_a_as_default_ant == 1) + { + rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3; + + if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd ) + { + pDM_PathDiv->is_pathA_exist=TRUE; + pDM_PathDiv->default_path=PATH_A; + } + else + { + pDM_PathDiv->is_pathA_exist=FALSE; + } + } + else + { + if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d)) + pDM_PathDiv->default_path=PATH_A; + else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d)) + pDM_PathDiv->default_path=PATH_B; + else if( rssi_avg_c >=rssi_avg_d) + pDM_PathDiv->default_path=PATH_C; + else + pDM_PathDiv->default_path=PATH_D; + } + + +} + + +VOID +phydm_candidate_dtp_update( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + pDM_PathDiv->num_candidate=3; + + if(pDM_PathDiv->use_path_a_as_default_ant == 1) + { + if(pDM_PathDiv->num_tx_path==3) + { + if(pDM_PathDiv->is_pathA_exist) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; + } + else // use path BCD + { + pDM_PathDiv->num_candidate=1; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD); + return; + } + } + else if(pDM_PathDiv->num_tx_path==2) + { + if(pDM_PathDiv->is_pathA_exist) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_AC; + pDM_PathDiv->ant_candidate_3 = PHYDM_AD; + } + else + { + pDM_PathDiv->ant_candidate_1 = PHYDM_BC; + pDM_PathDiv->ant_candidate_2 = PHYDM_BD; + pDM_PathDiv->ant_candidate_3 = PHYDM_CD; + } + } + } + else + { + //2 3 TX Mode + if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4 + { + if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; + } + else if(pDM_PathDiv->default_path==PATH_B) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + else if(pDM_PathDiv->default_path == PATH_C) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + else if(pDM_PathDiv->default_path == PATH_D) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + } + + //2 2 TX Mode + else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4 + { + if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_AC; + pDM_PathDiv->ant_candidate_3 = PHYDM_AD; + } + else if(pDM_PathDiv->default_path==PATH_B) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_BC; + pDM_PathDiv->ant_candidate_3 = PHYDM_BD; + } + else if(pDM_PathDiv->default_path == PATH_C) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AC; + pDM_PathDiv->ant_candidate_2 = PHYDM_BC; + pDM_PathDiv->ant_candidate_3 = PHYDM_CD; + } + else if(pDM_PathDiv->default_path == PATH_D) + { + pDM_PathDiv->ant_candidate_1= PHYDM_AD; + pDM_PathDiv->ant_candidate_2 = PHYDM_BD; + pDM_PathDiv->ant_candidate_3= PHYDM_CD; + } + } + } +} + + +VOID +phydm_dynamic_tx_path( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + PSTA_INFO_T pEntry; + u4Byte i; + u1Byte num_client=0; + u1Byte H2C_Parameter[6] ={0}; + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); + + if(pDM_PathDiv->bBecomeLinked == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); + pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_PathDiv->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); + pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; + } + } + + //2 [Period CTRL] + if(pDM_PathDiv->dtp_period >=2) + { + pDM_PathDiv->dtp_period=0; + } + else + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period)); + pDM_PathDiv->dtp_period++; + return; + } + + + //2 [Fix Path] + if (pDM_Odm->path_select != PHYDM_AUTO_PATH) + { + return; + } + + //2 [Check Bfer] + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (BEAMFORMING_SUPPORT == 1) + { + BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); + + if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off + { + if( pDM_PathDiv->fix_path_bfer == 0) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n")); + pDM_PathDiv->fix_path_bfer = 1 ; + } + return; + } + else // BFmer Off && Div Off -> Div On + { + if( pDM_PathDiv->fix_path_bfer == 1 ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n")); + pDM_PathDiv->fix_path_bfer = 0; + } + } + } + #endif + #endif + + if(pDM_PathDiv->use_path_a_as_default_ant ==1) + { + phydm_find_default_path(pDM_Odm); + phydm_candidate_dtp_update(pDM_Odm); + } + else + { + if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT) + { + phydm_find_default_path(pDM_Odm); + phydm_candidate_dtp_update(pDM_Odm); + pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1; + } + + else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1) + { + pDM_PathDiv->dtp_check_patha_counter++; + + if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD) + { + pDM_PathDiv->dtp_check_patha_counter=0; + pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; + } + //2 Search space update + else + { + // 1. find the worst candidate + + + // 2. repalce the worst candidate + } + } + } + + //2 Dynamic Path Selection H2C + + if(pDM_PathDiv->num_candidate == 1) + { + return; + } + else + { + H2C_Parameter[0] = pDM_PathDiv->num_candidate; + H2C_Parameter[1] = pDM_PathDiv->num_tx_path; + H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1; + H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2; + H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3; + + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter); + } + +} + + + +VOID +phydm_dynamic_tx_path_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + PADAPTER pAdapter = pDM_Odm->Adapter; + #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) + USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism; + #endif + u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; + u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; + + #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) + pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ; + #else + pDM_PathDiv->is_u3_mode = 1; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode)); + + memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); + memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); + + pDM_PathDiv->use_path_a_as_default_ant= 1; + pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; + pDM_Odm->path_select = PHYDM_AUTO_PATH; + pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV; + + + if(pDM_PathDiv->is_u3_mode ) + { + pDM_PathDiv->num_tx_path=3; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/ + + } + else + { + pDM_PathDiv->num_tx_path=2; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/ + } + +} + + +VOID +phydm_process_rssi_for_path_div( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) + { + if(pPktinfo->DataRate > ODM_RATE11M) + { + if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV) + { + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + { + pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0]; + pDM_PathDiv->path_a_cnt_all++; + + pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1]; + pDM_PathDiv->path_b_cnt_all++; + + pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2]; + pDM_PathDiv->path_c_cnt_all++; + + pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3]; + pDM_PathDiv->path_d_cnt_all++; + } + #endif + } + else + { + pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0]; + pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++; + + pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1]; + pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++; + } + } + } + + +} + +#endif //#if RTL8814A_SUPPORT + +VOID +odm_pathdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pDM_Odm->path_select = (dm_value[0] & 0xf); + PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select )); + + //2 [Fix Path] + if (pDM_Odm->path_select != PHYDM_AUTO_PATH) + { + PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n", + ((pDM_Odm->path_select) & 0x1)?"A":"", + ((pDM_Odm->path_select) & 0x2)?"B":"", + ((pDM_Odm->path_select) & 0x4)?"C":"", + ((pDM_Odm->path_select) & 0x8)?"D":"" )); + + phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select ); + } + else + { + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path")); + } +} + +#endif // #if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +phydm_c2h_dtp_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + + u1Byte macid = CmdBuf[0]; + u1Byte target = CmdBuf[1]; + u1Byte nsc_1 = CmdBuf[2]; + u1Byte nsc_2 = CmdBuf[3]; + u1Byte nsc_3 = CmdBuf[4]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target)); + /* + if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1); + } + else if( nsc_2 >= nsc_3) + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2); + } + else + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3); + } + */ +#endif +} + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); + return; + } + + #if RTL8812A_SUPPORT + + if(pDM_Odm->SupportICType & ODM_RTL8812) + ODM_PathDiversity_8812A(pDM_Odm); + else + #endif + + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_dynamic_tx_path(pDM_Odm); + else + #endif + {} +#endif +} + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/ + + if(pDM_Odm->mp_mode == TRUE) + return; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); + return; + } + +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8812) + ODM_PathDiversityInit_8812A(pDM_Odm); + else + #endif + + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_dynamic_tx_path_init(pDM_Odm); + else + #endif + {} +#endif +} + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// +// 2011/12/02 MH Copy from MP oursrc for temporarily test. +// + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer +) +{ +} + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ) +{ +} + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer +) +{ +} + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ) +{ +} +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ) +{ + return 0; +} +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ) +{ +} + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + diff --git a/package/kernel/rtl8192cd/phydm/phydm_pathdiv.h b/package/kernel/rtl8192cd/phydm/phydm_pathdiv.h index 63a26410ede..4ce42140f64 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_pathdiv.h +++ b/package/kernel/rtl8192cd/phydm/phydm_pathdiv.h @@ -1,324 +1,324 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPATHDIV_H__ -#define __PHYDMPATHDIV_H__ -/*#define PATHDIV_VERSION "2.0" //2014.11.04*/ -#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/ - -#if(defined(CONFIG_PATH_DIVERSITY)) -#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection - -#define NUM_RESET_DTP_PERIOD 5 -#define ANT_DECT_RSSI_TH 3 - -#define PATH_A 1 -#define PATH_B 2 -#define PATH_C 3 -#define PATH_D 4 - -#define PHYDM_AUTO_PATH 0 -#define PHYDM_FIX_PATH 1 - -#define NUM_CHOOSE2_FROM4 6 -#define NUM_CHOOSE3_FROM4 4 - - -#define PHYDM_A BIT0 -#define PHYDM_B BIT1 -#define PHYDM_C BIT2 -#define PHYDM_D BIT3 -#define PHYDM_AB (BIT0 | BIT1) // 0 -#define PHYDM_AC (BIT0 | BIT2) // 1 -#define PHYDM_AD (BIT0 | BIT3) // 2 -#define PHYDM_BC (BIT1 | BIT2) // 3 -#define PHYDM_BD (BIT1 | BIT3) // 4 -#define PHYDM_CD (BIT2 | BIT3) // 5 - -#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/ -#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/ -#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/ -#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/ - -#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) - - -typedef enum dtp_state -{ - PHYDM_DTP_INIT=1, - PHYDM_DTP_RUNNING_1 - -}PHYDM_DTP_STATE; - -typedef enum path_div_type -{ - PHYDM_2R_PATH_DIV = 1, - PHYDM_4R_PATH_DIV = 2 -}PHYDM_PATH_DIV_TYPE; - -VOID -phydm_process_rssi_for_path_div( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - ); - -typedef struct _ODM_PATH_DIVERSITY_ -{ - u1Byte RespTxPath; - u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte path_div_type; - #if RTL8814A_SUPPORT - - u4Byte path_a_sum_all; - u4Byte path_b_sum_all; - u4Byte path_c_sum_all; - u4Byte path_d_sum_all; - - u4Byte path_a_cnt_all; - u4Byte path_b_cnt_all; - u4Byte path_c_cnt_all; - u4Byte path_d_cnt_all; - - u1Byte dtp_period; - BOOLEAN bBecomeLinked; - BOOLEAN is_u3_mode; - u1Byte num_tx_path; - u1Byte default_path; - u1Byte num_candidate; - u1Byte ant_candidate_1; - u1Byte ant_candidate_2; - u1Byte ant_candidate_3; - u1Byte dtp_state; - u1Byte dtp_check_patha_counter; - BOOLEAN fix_path_bfer; - u1Byte search_space_2[NUM_CHOOSE2_FROM4]; - u1Byte search_space_3[NUM_CHOOSE3_FROM4]; - - u1Byte pre_tx_path; - u1Byte use_path_a_as_default_ant; - BOOLEAN is_pathA_exist; - - #endif -}PATHDIV_T, *pPATHDIV_T; - - -#endif //#if(defined(CONFIG_PATH_DIVERSITY)) - -VOID -phydm_c2h_dtp_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen - ); - -VOID -odm_PathDiversityInit( - IN PVOID pDM_VOID - ); - -VOID -odm_PathDiversity( - IN PVOID pDM_VOID - ); - -VOID -odm_pathdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - - - -//1 [OLD IC]-------------------------------------------------------------------------------- - - - - - - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -//#define PATHDIV_ENABLE 1 -#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi -#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C - - - - -typedef struct _PathDiv_Parameter_define_ -{ - u4Byte org_5g_RegE30; - u4Byte org_5g_RegC14; - u4Byte org_5g_RegCA0; - u4Byte swt_5g_RegE30; - u4Byte swt_5g_RegC14; - u4Byte swt_5g_RegCA0; - //for 2G IQK information - u4Byte org_2g_RegC80; - u4Byte org_2g_RegC4C; - u4Byte org_2g_RegC94; - u4Byte org_2g_RegC14; - u4Byte org_2g_RegCA0; - - u4Byte swt_2g_RegC80; - u4Byte swt_2g_RegC4C; - u4Byte swt_2g_RegC94; - u4Byte swt_2g_RegC14; - u4Byte swt_2g_RegCA0; -}PATHDIV_PARA,*pPATHDIV_PARA; - -VOID -odm_PathDiversityInit_92C( - IN PADAPTER Adapter - ); - -VOID -odm_2TPathDiversityInit_92C( - IN PADAPTER Adapter - ); - -VOID -odm_1TPathDiversityInit_92C( - IN PADAPTER Adapter - ); - -BOOLEAN -odm_IsConnected_92C( - IN PADAPTER Adapter - ); - -BOOLEAN -ODM_PathDiversityBeforeLink92C( - //IN PADAPTER Adapter - IN PDM_ODM_T pDM_Odm - ); - -VOID -odm_PathDiversityAfterLink_92C( - IN PADAPTER Adapter - ); - -VOID -odm_SetRespPath_92C( - IN PADAPTER Adapter, - IN u1Byte DefaultRespPath - ); - -VOID -odm_OFDMTXPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_CCKTXPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_ResetPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_CCKTXPathDiversityCallback( - PRT_TIMER pTimer - ); - -VOID -odm_CCKTXPathDiversityWorkItemCallback( - IN PVOID pContext - ); - -VOID -odm_PathDivChkAntSwitchCallback( - PRT_TIMER pTimer - ); - -VOID -odm_PathDivChkAntSwitchWorkitemCallback( - IN PVOID pContext - ); - - -VOID -odm_PathDivChkAntSwitch( - PDM_ODM_T pDM_Odm - ); - -VOID -ODM_CCKPathDiversityChkPerPktRssi( - PADAPTER Adapter, - BOOLEAN bIsDefPort, - BOOLEAN bMatchBSSID, - PRT_WLAN_STA pEntry, - PRT_RFD pRfd, - pu1Byte pDesc - ); - -VOID -ODM_PathDivChkPerPktRssi( - PADAPTER Adapter, - BOOLEAN bIsDefPort, - BOOLEAN bMatchBSSID, - PRT_WLAN_STA pEntry, - PRT_RFD pRfd - ); - -VOID -ODM_PathDivRestAfterLink( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_FillTXPathInTXDESC( - IN PADAPTER Adapter, - IN PRT_TCB pTcb, - IN pu1Byte pDesc - ); - -VOID -odm_PathDivInit_92D( - IN PDM_ODM_T pDM_Odm - ); - -u1Byte -odm_SwAntDivSelectScanChnl( - IN PADAPTER Adapter - ); - -VOID -odm_SwAntDivConstructScanChnl( - IN PADAPTER Adapter, - IN u1Byte ScanChnl - ); - - #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - - #endif //#ifndef __ODMPATHDIV_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ +/*#define PATHDIV_VERSION "2.0" //2014.11.04*/ +#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/ + +#if(defined(CONFIG_PATH_DIVERSITY)) +#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection + +#define NUM_RESET_DTP_PERIOD 5 +#define ANT_DECT_RSSI_TH 3 + +#define PATH_A 1 +#define PATH_B 2 +#define PATH_C 3 +#define PATH_D 4 + +#define PHYDM_AUTO_PATH 0 +#define PHYDM_FIX_PATH 1 + +#define NUM_CHOOSE2_FROM4 6 +#define NUM_CHOOSE3_FROM4 4 + + +#define PHYDM_A BIT0 +#define PHYDM_B BIT1 +#define PHYDM_C BIT2 +#define PHYDM_D BIT3 +#define PHYDM_AB (BIT0 | BIT1) // 0 +#define PHYDM_AC (BIT0 | BIT2) // 1 +#define PHYDM_AD (BIT0 | BIT3) // 2 +#define PHYDM_BC (BIT1 | BIT2) // 3 +#define PHYDM_BD (BIT1 | BIT3) // 4 +#define PHYDM_CD (BIT2 | BIT3) // 5 + +#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/ +#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/ +#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/ +#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/ + +#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) + + +typedef enum dtp_state +{ + PHYDM_DTP_INIT=1, + PHYDM_DTP_RUNNING_1 + +}PHYDM_DTP_STATE; + +typedef enum path_div_type +{ + PHYDM_2R_PATH_DIV = 1, + PHYDM_4R_PATH_DIV = 2 +}PHYDM_PATH_DIV_TYPE; + +VOID +phydm_process_rssi_for_path_div( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + ); + +typedef struct _ODM_PATH_DIVERSITY_ +{ + u1Byte RespTxPath; + u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte path_div_type; + #if RTL8814A_SUPPORT + + u4Byte path_a_sum_all; + u4Byte path_b_sum_all; + u4Byte path_c_sum_all; + u4Byte path_d_sum_all; + + u4Byte path_a_cnt_all; + u4Byte path_b_cnt_all; + u4Byte path_c_cnt_all; + u4Byte path_d_cnt_all; + + u1Byte dtp_period; + BOOLEAN bBecomeLinked; + BOOLEAN is_u3_mode; + u1Byte num_tx_path; + u1Byte default_path; + u1Byte num_candidate; + u1Byte ant_candidate_1; + u1Byte ant_candidate_2; + u1Byte ant_candidate_3; + u1Byte dtp_state; + u1Byte dtp_check_patha_counter; + BOOLEAN fix_path_bfer; + u1Byte search_space_2[NUM_CHOOSE2_FROM4]; + u1Byte search_space_3[NUM_CHOOSE3_FROM4]; + + u1Byte pre_tx_path; + u1Byte use_path_a_as_default_ant; + BOOLEAN is_pathA_exist; + + #endif +}PATHDIV_T, *pPATHDIV_T; + + +#endif //#if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +phydm_c2h_dtp_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen + ); + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID + ); + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID + ); + +VOID +odm_pathdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + + + +//1 [OLD IC]-------------------------------------------------------------------------------- + + + + + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +//#define PATHDIV_ENABLE 1 +#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi +#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C + + + + +typedef struct _PathDiv_Parameter_define_ +{ + u4Byte org_5g_RegE30; + u4Byte org_5g_RegC14; + u4Byte org_5g_RegCA0; + u4Byte swt_5g_RegE30; + u4Byte swt_5g_RegC14; + u4Byte swt_5g_RegCA0; + //for 2G IQK information + u4Byte org_2g_RegC80; + u4Byte org_2g_RegC4C; + u4Byte org_2g_RegC94; + u4Byte org_2g_RegC14; + u4Byte org_2g_RegCA0; + + u4Byte swt_2g_RegC80; + u4Byte swt_2g_RegC4C; + u4Byte swt_2g_RegC94; + u4Byte swt_2g_RegC14; + u4Byte swt_2g_RegCA0; +}PATHDIV_PARA,*pPATHDIV_PARA; + +VOID +odm_PathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_2TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_1TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter + ); + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ); + +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer + ); + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ); + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer + ); + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); + + +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ); + +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ); + +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc + ); + +VOID +odm_PathDivInit_92D( + IN PDM_ODM_T pDM_Odm + ); + +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ); + +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ); + + #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + + #endif //#ifndef __ODMPATHDIV_H__ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.c b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.c index acac2598840..ccc3fa1f6c6 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.c +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.c @@ -1,1254 +1,1254 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if !defined(_OUTSRC_COEXIST) -//============================================================ -// Global var -//============================================================ - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ -{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ -{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ -{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ -{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ -{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ -{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ -{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ -{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ -{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ -{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ -{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ -{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ -{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ -{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ -{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ -{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ -{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ -{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - - -#if 0 -u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { - /* Index0 6 dB */ 0x7fc001ff, - /* Index1 5.7dB */ 0x7b4001ed, - /* Index2 5.4dB */ 0x774001dd, - /* Index3 5.1dB */ 0x734001cd, - /* Index4 4.8dB */ 0x6f4001bd, - /* Index5 4.5dB */ 0x6b8001ae, - /* Index6 4.2dB */ 0x67c0019f, - /* Index7 3.9dB */ 0x64400191, - /* Index8 3.6dB */ 0x60c00183, - /* Index9 3.3dB */ 0x5d800176, - /* Index10 3 dB */ 0x5a80016a, - /* Index11 2.7dB */ 0x5740015d, - /* Index12 2.4dB */ 0x54400151, - /* Index13 2.1dB */ 0x51800146, - /* Index14 1.8dB */ 0x4ec0013b, - /* Index15 1.5dB */ 0x4c000130, - /* Index16 1.2dB */ 0x49800126, - /* Index17 0.9dB */ 0x4700011c, - /* Index18 0.6dB */ 0x44800112, - /* Index19 0.3dB */ 0x42000108, - /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index - /* Index21 -0.3dB */ 0x3dc000f7, - /* Index22 -0.6dB */ 0x3bc000ef, - /* Index23 -0.9dB */ 0x39c000e7, - /* Index24 -1.2dB */ 0x37c000df, - /* Index25 -1.5dB */ 0x35c000d7, - /* Index26 -1.8dB */ 0x340000d0, - /* Index27 -2.1dB */ 0x324000c9, - /* Index28 -2.4dB */ 0x308000c2, - /* Index29 -2.7dB */ 0x2f0000bc, - /* Index30 -3 dB */ 0x2d4000b5, - /* Index31 -3.3dB */ 0x2bc000af, - /* Index32 -3.6dB */ 0x2a4000a9, - /* Index33 -3.9dB */ 0x28c000a3, - /* Index34 -4.2dB */ 0x2780009e, - /* Index35 -4.5dB */ 0x26000098, - /* Index36 -4.8dB */ 0x24c00093, - /* Index37 -5.1dB */ 0x2380008e, - /* Index38 -5.4dB */ 0x22400089, - /* Index39 -5.7dB */ 0x21400085, - /* Index40 -6 dB */ 0x20000080, - /* Index41 -6.3dB */ 0x1f00007c, - /* Index42 -6.6dB */ 0x1e000078, - /* Index43 -6.9dB */ 0x1d000074, - /* Index44 -7.2dB */ 0x1c000070, - /* Index45 -7.5dB */ 0x1b00006c, - /* Index46 -7.8dB */ 0x1a000068, - /* Index47 -8.1dB */ 0x19400065, - /* Index48 -8.4dB */ 0x18400061, - /* Index49 -8.7dB */ 0x1780005e, - /* Index50 -9 dB */ 0x16c0005b, - /* Index51 -9.3dB */ 0x16000058, - /* Index52 -9.6dB */ 0x15400055, - /* Index53 -9.9dB */ 0x14800052 -}; -u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, - /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} -}; -u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} -}; -#endif - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; -#endif - -#endif - - -u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 -, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 -, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - - -#ifdef CONFIG_WLAN_HAL_8192EE -u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { - /* Index0 6 dB */ 0x7fc001ff, - /* Index1 5.7dB */ 0x7b4001ed, - /* Index2 5.4dB */ 0x774001dd, - /* Index3 5.1dB */ 0x734001cd, - /* Index4 4.8dB */ 0x6f4001bd, - /* Index5 4.5dB */ 0x6b8001ae, - /* Index6 4.2dB */ 0x67c0019f, - /* Index7 3.9dB */ 0x64400191, - /* Index8 3.6dB */ 0x60c00183, - /* Index9 3.3dB */ 0x5d800176, - /* Index10 3 dB */ 0x5a80016a, - /* Index11 2.7dB */ 0x5740015d, - /* Index12 2.4dB */ 0x54400151, - /* Index13 2.1dB */ 0x51800146, - /* Index14 1.8dB */ 0x4ec0013b, - /* Index15 1.5dB */ 0x4c000130, - /* Index16 1.2dB */ 0x49800126, - /* Index17 0.9dB */ 0x4700011c, - /* Index18 0.6dB */ 0x44800112, - /* Index19 0.3dB */ 0x42000108, - /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index - /* Index21 -0.3dB */ 0x3dc000f7, - /* Index22 -0.6dB */ 0x3bc000ef, - /* Index23 -0.9dB */ 0x39c000e7, - /* Index24 -1.2dB */ 0x37c000df, - /* Index25 -1.5dB */ 0x35c000d7, - /* Index26 -1.8dB */ 0x340000d0, - /* Index27 -2.1dB */ 0x324000c9, - /* Index28 -2.4dB */ 0x308000c2, - /* Index29 -2.7dB */ 0x2f0000bc, - /* Index30 -3 dB */ 0x2d4000b5, - /* Index31 -3.3dB */ 0x2bc000af, - /* Index32 -3.6dB */ 0x2a4000a9, - /* Index33 -3.9dB */ 0x28c000a3, - /* Index34 -4.2dB */ 0x2780009e, - /* Index35 -4.5dB */ 0x26000098, - /* Index36 -4.8dB */ 0x24c00093, - /* Index37 -5.1dB */ 0x2380008e, - /* Index38 -5.4dB */ 0x22400089, - /* Index39 -5.7dB */ 0x21400085, - /* Index40 -6 dB */ 0x20000080, - /* Index41 -6.3dB */ 0x1f00007c, - /* Index42 -6.6dB */ 0x1e000078, - /* Index43 -6.9dB */ 0x1d000074, - /* Index44 -7.2dB */ 0x1c000070, - /* Index45 -7.5dB */ 0x1b00006c, - /* Index46 -7.8dB */ 0x1a000068, - /* Index47 -8.1dB */ 0x19400065, - /* Index48 -8.4dB */ 0x18400061, - /* Index49 -8.7dB */ 0x1780005e, - /* Index50 -9 dB */ 0x16c0005b, - /* Index51 -9.3dB */ 0x16000058, - /* Index52 -9.6dB */ 0x15400055, - /* Index53 -9.9dB */ 0x14800052 -}; -u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, - /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} -}; -u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} -}; -#endif - -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, // 0, -12.0dB - 0x088, // 1, -11.5dB - 0x090, // 2, -11.0dB - 0x099, // 3, -10.5dB - 0x0A2, // 4, -10.0dB - 0x0AC, // 5, -9.5dB - 0x0B6, // 6, -9.0dB - 0x0C0, // 7, -8.5dB - 0x0CC, // 8, -8.0dB - 0x0D8, // 9, -7.5dB - 0x0E5, // 10, -7.0dB - 0x0F2, // 11, -6.5dB - 0x101, // 12, -6.0dB - 0x110, // 13, -5.5dB - 0x120, // 14, -5.0dB - 0x131, // 15, -4.5dB - 0x143, // 16, -4.0dB - 0x156, // 17, -3.5dB - 0x16A, // 18, -3.0dB - 0x180, // 19, -2.5dB - 0x197, // 20, -2.0dB - 0x1AF, // 21, -1.5dB - 0x1C8, // 22, -1.0dB - 0x1E3, // 23, -0.5dB - 0x200, // 24, +0 dB - 0x21E, // 25, +0.5dB - 0x23E, // 26, +1.0dB - 0x261, // 27, +1.5dB - 0x285, // 28, +2.0dB - 0x2AB, // 29, +2.5dB - 0x2D3, // 30, +3.0dB - 0x2FE, // 31, +3.5dB - 0x32B, // 32, +4.0dB - 0x35C, // 33, +4.5dB - 0x38E, // 34, +5.0dB - 0x3C4, // 35, +5.5dB - 0x3FE // 36, +6.0dB -}; -#elif(ODM_IC_11AC_SERIES_SUPPORT) -u4Byte OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812] = { - 0x3FE, // 0, (6dB) - 0x3C4, // 1, (5.5dB) - 0x38E, // 2, (5dB) - 0x35C, // 3, (4.5dB) - 0x32B, // 4, (4dB) - 0x2FE, // 5, (3.5dB) - 0x2D3, // 6, (3dB) - 0x2AB, // 7, (2.5dB) - 0x285, // 8, (2dB) - 0x261, // 9, (1.5dB - 0x23E, // 10, (1dB) - 0x21E, // 11, (0.5dB) - 0x200, // 12, (0dB) 8814 int PA 2G default - 0x1E3, // 13, (-0.5dB) - 0x1C8, // 14, (-1dB) - 0x1AF, // 15, (-1.5dB) - 0x197, // 16, (-2dB) - 0x180, // 17, (-2.5dB) - 0x16A, // 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default - 0x156, // 19, (-3.5dB) - 0x143, // 20, (-4dB) 8812 HP default - 0x131, // 21, (-4.5dB) - 0x120, // 22, (-5dB) - 0x110, // 23, (-5.5dB) - 0x101, // 24, (-6dB) - 0x0F2, // 25, (-6.5dB) - 0x0E5, // 26, (-7dB) - 0x0D8, // 27, (-7.5dB) - 0x0CC, // 28, (-8dB) - 0x0C0, // 29, (-8.5dB) - 0x0B6, // 30, (-9dB) - 0x0AC, // 31, (-9.5dB) - 0x0A2, // 32, (-10dB) - 0x099, // 33, (-10.5dB) - 0x090, // 34, (-11dB) - 0x088, // 35, (-11.5dB) - 0x081, // 36, (-12dB) - 0x079, // 37, (-12.5dB) - 0x072, // 38, (-13dB) - 0x06c, // 39, (-13.5dB) - 0x066, // 40, (-14dB) - 0x060, // 41, (-14.5dB) - 0x05B // 42, (-15dB) -}; -#endif - -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -//#endif -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - -u1Byte -getCckSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0, CckBBswingMask = 0; - u4Byte CckbbSwing = 0; - u4Byte CckswingTableSize = 0; - pu4Byte pCckSwingTable = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) { - CckbbSwing = PHY_QueryBBReg(priv, 0xab4, 0X7ff); - pCckSwingTable = CCKSwingTable_Ch1_Ch14_8723D; - CckswingTableSize = CCK_TABLE_SIZE_8723D; - CckBBswingMask = 0; - } -#endif - - for (i = 0; i < CckswingTableSize - 1; i++) { - u4Byte tableValue = pCckSwingTable[i] >> CckBBswingMask; - - if (CckbbSwing == tableValue) - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CckbbSwing=0x%x Cckbbswing_index=%d\n", CckbbSwing, i)); - return i; -} - - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0, BBswingMask = 0; - u4Byte bbSwing = 0; - u4Byte swingTableSize = 0; - pu4Byte pSwingTable = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) { - bbSwing = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE_92D; - BBswingMask = 22; - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8822B) { - bbSwing = PHY_QueryBBReg(priv, rA_TxScale_Jaguar, 0xFFE00000); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - BBswingMask = 0; - } -#endif - - for (i = 0; i < swingTableSize-1; i++) { - u4Byte tableValue = pSwingTable[i] >> BBswingMask; - - if (bbSwing == tableValue) - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bbSwing=0x%x bbswing_index=%d\n", bbSwing, i)); - - - return i; -} - - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - prtl8192cd_priv priv = pDM_Odm->priv; - u1Byte p; - u1Byte defaultSwingIndex, defaultCckSwingIndex; -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B)) - defaultSwingIndex = getSwingIndex(pDM_Odm); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) - defaultCckSwingIndex = getCckSwingIndex(pDM_Odm); -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pMgntInfo->bTXPowerTracking = TRUE; - pHalData->TXPowercount = 0; - pHalData->bTXPowerTrackingInit = FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pHalData->TxPowerTrackControl = TRUE; - ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_RTL8188E - { - pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; - - MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); - } - #else - { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - //if(IS_HARDWARE_TYPE_8192C(pHalData)) - { - pdmpriv->bTXPowerTracking = _TRUE; - pdmpriv->TXPowercount = 0; - pdmpriv->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) //for mp driver, turn off txpwrtracking as default - pdmpriv->TxPowerTrackControl = _TRUE; - - } - MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); - - } - #endif//endif (CONFIG_RTL8188E==1) -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - - #ifdef RTL8188E_SUPPORT - { - pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - #endif -#endif - - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = 0; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = 0; - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - pDM_Odm->RFCalibrateInfo.ThermalValue = 0; - pRFCalibrateInfo->DefaultOfdmIndex = 28; - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = (defaultCckSwingIndex >= (CCK_TABLE_SIZE_8723D - 1)) ? 28 : defaultCckSwingIndex; - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8822B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } -#endif - - -#if RTL8188E_SUPPORT - pRFCalibrateInfo->DefaultCckIndex = 20; // -6 dB -#elif RTL8192E_SUPPORT - pRFCalibrateInfo->DefaultCckIndex = 8; // -12 dB -#endif - pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = 0; p < MAX_RF_PATH; p++) { - pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->KfreeOffset[p] = 0; /* for 8814 kfree*/ - } - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d pRFCalibrateInfo->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex , pRFCalibrateInfo->DefaultCckIndex)); - - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - return; - - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - case ODM_ADSL: - /*odm_DIGAP(pDM_Odm);*/ - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - - #if(RTL8188E_SUPPORT==1) - - //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) - if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - { - return; - } - - if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec - { - //pHalData->TxPowerCheckCnt++; //cosa add for debug - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - //DBG_8192C("Trigger 92C Thermal Meter!!\n"); - - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - - } - else - { - //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); - odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - #endif - -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - return; - - if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) - odm_TXPowerTrackingThermalMeterCheck(Adapter); -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - -#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) - ODM_TXPowerTrackingCallback_ThermalMeter(pDM_Odm); - else -#endif - { - } -#endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND -#if (HAL_CODE_BASE==RTL8192_C) - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - static u1Byte TM_Trigger = 0; - //u1Byte TxPowerCheckCnt = 5; //10 sec - - if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) - { - return; - } - - if(!TM_Trigger) //at least delay 1 sec - { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8812(Adapter)) - PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } - else - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. - TM_Trigger = 0; - } -#endif -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if !defined(_OUTSRC_COEXIST) +//============================================================ +// Global var +//============================================================ + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ +{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ +{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ +{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ +{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ +{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ +{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ +{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ +{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ +{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { +{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ +{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ +{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ +{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ +{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ +{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ +{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ +{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ +{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ +{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + + +#if 0 +u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} +}; +u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} +}; +#endif + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + +#endif + + +u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 +, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 +, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + + +#ifdef CONFIG_WLAN_HAL_8192EE +u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} +}; +u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} +}; +#endif + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, // 0, -12.0dB + 0x088, // 1, -11.5dB + 0x090, // 2, -11.0dB + 0x099, // 3, -10.5dB + 0x0A2, // 4, -10.0dB + 0x0AC, // 5, -9.5dB + 0x0B6, // 6, -9.0dB + 0x0C0, // 7, -8.5dB + 0x0CC, // 8, -8.0dB + 0x0D8, // 9, -7.5dB + 0x0E5, // 10, -7.0dB + 0x0F2, // 11, -6.5dB + 0x101, // 12, -6.0dB + 0x110, // 13, -5.5dB + 0x120, // 14, -5.0dB + 0x131, // 15, -4.5dB + 0x143, // 16, -4.0dB + 0x156, // 17, -3.5dB + 0x16A, // 18, -3.0dB + 0x180, // 19, -2.5dB + 0x197, // 20, -2.0dB + 0x1AF, // 21, -1.5dB + 0x1C8, // 22, -1.0dB + 0x1E3, // 23, -0.5dB + 0x200, // 24, +0 dB + 0x21E, // 25, +0.5dB + 0x23E, // 26, +1.0dB + 0x261, // 27, +1.5dB + 0x285, // 28, +2.0dB + 0x2AB, // 29, +2.5dB + 0x2D3, // 30, +3.0dB + 0x2FE, // 31, +3.5dB + 0x32B, // 32, +4.0dB + 0x35C, // 33, +4.5dB + 0x38E, // 34, +5.0dB + 0x3C4, // 35, +5.5dB + 0x3FE // 36, +6.0dB +}; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +u4Byte OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812] = { + 0x3FE, // 0, (6dB) + 0x3C4, // 1, (5.5dB) + 0x38E, // 2, (5dB) + 0x35C, // 3, (4.5dB) + 0x32B, // 4, (4dB) + 0x2FE, // 5, (3.5dB) + 0x2D3, // 6, (3dB) + 0x2AB, // 7, (2.5dB) + 0x285, // 8, (2dB) + 0x261, // 9, (1.5dB + 0x23E, // 10, (1dB) + 0x21E, // 11, (0.5dB) + 0x200, // 12, (0dB) 8814 int PA 2G default + 0x1E3, // 13, (-0.5dB) + 0x1C8, // 14, (-1dB) + 0x1AF, // 15, (-1.5dB) + 0x197, // 16, (-2dB) + 0x180, // 17, (-2.5dB) + 0x16A, // 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default + 0x156, // 19, (-3.5dB) + 0x143, // 20, (-4dB) 8812 HP default + 0x131, // 21, (-4.5dB) + 0x120, // 22, (-5dB) + 0x110, // 23, (-5.5dB) + 0x101, // 24, (-6dB) + 0x0F2, // 25, (-6.5dB) + 0x0E5, // 26, (-7dB) + 0x0D8, // 27, (-7.5dB) + 0x0CC, // 28, (-8dB) + 0x0C0, // 29, (-8.5dB) + 0x0B6, // 30, (-9dB) + 0x0AC, // 31, (-9.5dB) + 0x0A2, // 32, (-10dB) + 0x099, // 33, (-10.5dB) + 0x090, // 34, (-11dB) + 0x088, // 35, (-11.5dB) + 0x081, // 36, (-12dB) + 0x079, // 37, (-12.5dB) + 0x072, // 38, (-13dB) + 0x06c, // 39, (-13.5dB) + 0x066, // 40, (-14dB) + 0x060, // 41, (-14.5dB) + 0x05B // 42, (-15dB) +}; +#endif + +u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +//#endif +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + +u1Byte +getCckSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0, CckBBswingMask = 0; + u4Byte CckbbSwing = 0; + u4Byte CckswingTableSize = 0; + pu4Byte pCckSwingTable = 0; + prtl8192cd_priv priv = pDM_Odm->priv; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + CckbbSwing = PHY_QueryBBReg(priv, 0xab4, 0X7ff); + pCckSwingTable = CCKSwingTable_Ch1_Ch14_8723D; + CckswingTableSize = CCK_TABLE_SIZE_8723D; + CckBBswingMask = 0; + } +#endif + + for (i = 0; i < CckswingTableSize - 1; i++) { + u4Byte tableValue = pCckSwingTable[i] >> CckBBswingMask; + + if (CckbbSwing == tableValue) + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CckbbSwing=0x%x Cckbbswing_index=%d\n", CckbbSwing, i)); + return i; +} + + +u1Byte +getSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0, BBswingMask = 0; + u4Byte bbSwing = 0; + u4Byte swingTableSize = 0; + pu4Byte pSwingTable = 0; + prtl8192cd_priv priv = pDM_Odm->priv; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + bbSwing = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); + pSwingTable = OFDMSwingTable_New; + swingTableSize = OFDM_TABLE_SIZE_92D; + BBswingMask = 22; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + bbSwing = PHY_QueryBBReg(priv, rA_TxScale_Jaguar, 0xFFE00000); + pSwingTable = TxScalingTable_Jaguar; + swingTableSize = TXSCALE_TABLE_SIZE; + BBswingMask = 0; + } +#endif + + for (i = 0; i < swingTableSize-1; i++) { + u4Byte tableValue = pSwingTable[i] >> BBswingMask; + + if (bbSwing == tableValue) + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bbSwing=0x%x bbswing_index=%d\n", bbSwing, i)); + + + return i; +} + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + prtl8192cd_priv priv = pDM_Odm->priv; + u1Byte p; + u1Byte defaultSwingIndex, defaultCckSwingIndex; +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B)) + defaultSwingIndex = getSwingIndex(pDM_Odm); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) + defaultCckSwingIndex = getCckSwingIndex(pDM_Odm); +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pMgntInfo->bTXPowerTracking = TRUE; + pHalData->TXPowercount = 0; + pHalData->bTXPowerTrackingInit = FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pHalData->TxPowerTrackControl = TRUE; + ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_RTL8188E + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); + } + #else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + //if(IS_HARDWARE_TYPE_8192C(pHalData)) + { + pdmpriv->bTXPowerTracking = _TRUE; + pdmpriv->TXPowercount = 0; + pdmpriv->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) //for mp driver, turn off txpwrtracking as default + pdmpriv->TxPowerTrackControl = _TRUE; + + } + MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); + + } + #endif//endif (CONFIG_RTL8188E==1) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + #ifdef RTL8188E_SUPPORT + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + #endif +#endif + + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = 0; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = 0; + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + pDM_Odm->RFCalibrateInfo.ThermalValue = 0; + pRFCalibrateInfo->DefaultOfdmIndex = 28; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = (defaultCckSwingIndex >= (CCK_TABLE_SIZE_8723D - 1)) ? 28 : defaultCckSwingIndex; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 20; + } +#endif + + +#if RTL8188E_SUPPORT + pRFCalibrateInfo->DefaultCckIndex = 20; // -6 dB +#elif RTL8192E_SUPPORT + pRFCalibrateInfo->DefaultCckIndex = 8; // -12 dB +#endif + pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->DefaultCckIndex; + + for (p = 0; p < MAX_RF_PATH; p++) { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->KfreeOffset[p] = 0; /* for 8814 kfree*/ + } + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d pRFCalibrateInfo->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex , pRFCalibrateInfo->DefaultCckIndex)); + + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + + + if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + return; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + case ODM_ADSL: + /*odm_DIGAP(pDM_Odm);*/ + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + #if(RTL8188E_SUPPORT==1) + + //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) + if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + return; + } + + if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec + { + //pHalData->TxPowerCheckCnt++; //cosa add for debug + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + //DBG_8192C("Trigger 92C Thermal Meter!!\n"); + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + + } + else + { + //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + #endif + +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + return; + + if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) + odm_TXPowerTrackingThermalMeterCheck(Adapter); +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + +#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) + ODM_TXPowerTrackingCallback_ThermalMeter(pDM_Odm); + else +#endif + { + } +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND +#if (HAL_CODE_BASE==RTL8192_C) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + static u1Byte TM_Trigger = 0; + //u1Byte TxPowerCheckCnt = 5; //10 sec + + if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) + { + return; + } + + if(!TM_Trigger) //at least delay 1 sec + { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8812(Adapter)) + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } + else + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. + TM_Trigger = 0; + } +#endif +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.h b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.h index 6573d150d15..cfcd5a5f3ac 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.h +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ap.h @@ -1,368 +1,368 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef RTK_AC_SUPPORT -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#else -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#endif -#else -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#endif - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 3 -#define MAX_RF_PATH 4 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 - -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM_MAX 10 - -#define IQK_BB_REG_NUM 9 - -#define HP_THERMAL_NUM 8 - -#define AVG_THERMAL_NUM 8 -#define AVG_THERMAL_NUM_DPK 8 -#define Thermal_DPK_AVG_num 4 - -#define IQK_Matrix_REG_NUM 8 -//#define IQK_Matrix_Settings_NUM 1+24+21 -#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G - -#if !defined(_OUTSRC_COEXIST) -#define OFDM_TABLE_SIZE_92D 43 -#define OFDM_TABLE_SIZE 37 -#define CCK_TABLE_SIZE 33 -#define CCK_TABLE_SIZE_88F 21 - - - -//#define OFDM_TABLE_SIZE_92E 54 -//#define CCK_TABLE_SIZE_92E 54 -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; - -#endif - -#define ODM_OFDM_TABLE_SIZE 37 -#define ODM_CCK_TABLE_SIZE 33 -// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE]; -extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE]; - -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; -//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; -//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; - -#ifdef CONFIG_WLAN_HAL_8192EE -#define OFDM_TABLE_SIZE_92E 54 -#define CCK_TABLE_SIZE_92E 54 -extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; -extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; -extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; -#endif - -#define OFDM_TABLE_SIZE_8812 43 -#define AVG_THERMAL_NUM_8812 4 - -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; -#elif(ODM_IC_11AC_SERIES_SUPPORT) -extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812]; -#endif - -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[1][IQK_Matrix_REG_NUM]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - - //u1Byte bTXPowerTracking; - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - u1Byte ThermalValue_Crystal; - u1Byte ThermalValue_DPKstore; - u1Byte ThermalValue_DPKtrack; - BOOLEAN TxPowerTrackingInProgress; - BOOLEAN bDPKenable; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset; - s1Byte DeltaPowerIndex; - s1Byte DeltaPowerIndexLast; - BOOLEAN bTxPowerChanged; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ - u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u8Byte IQK_StartTime; - u8Byte IQK_TotalProgressingTime; - u8Byte IQK_ProgressingTime; - u4Byte LOK_Result; - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - u1Byte DPPathAResult[3]; - u1Byte DPPathBResult[3]; - u1Byte bDPKEnable; - u4Byte Txrate[11]; - u1Byte pwsf_2g_a[3]; - - u1Byte pwsf_2g_b[3]; - u4Byte lut_2g_even_a[3][64]; - u4Byte lut_2g_odd_a[3][64]; - u4Byte lut_2g_even_b[3][64]; - u4Byte lut_2g_odd_b[3][64]; - u1Byte ThermalValue_DPK; - u1Byte ThermalValue_DPK_AVG[AVG_THERMAL_NUM_DPK]; - u1Byte ThermalValue_DPK_AVG_index; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - u4Byte TxLOK[2]; -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -VOID -odm_TXPowerTrackingCallbackThermalMeter92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackRXGainThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingDirectCall92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - - - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif +#else +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define AVG_THERMAL_NUM_DPK 8 +#define Thermal_DPK_AVG_num 4 + +#define IQK_Matrix_REG_NUM 8 +//#define IQK_Matrix_Settings_NUM 1+24+21 +#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +#if !defined(_OUTSRC_COEXIST) +#define OFDM_TABLE_SIZE_92D 43 +#define OFDM_TABLE_SIZE 37 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 + + + +//#define OFDM_TABLE_SIZE_92E 54 +//#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE]; +extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE]; + +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; + +#ifdef CONFIG_WLAN_HAL_8192EE +#define OFDM_TABLE_SIZE_92E 54 +#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812]; +#endif + +extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[1][IQK_Matrix_REG_NUM]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + BOOLEAN bDPKenable; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset; + s1Byte DeltaPowerIndex; + s1Byte DeltaPowerIndexLast; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + BOOLEAN bIQKPAoff; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u8Byte IQK_StartTime; + u8Byte IQK_TotalProgressingTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + u1Byte IQKstep; + u1Byte Kcount; + u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + BOOLEAN isMPmode; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + u1Byte DPPathAResult[3]; + u1Byte DPPathBResult[3]; + u1Byte bDPKEnable; + u4Byte Txrate[11]; + u1Byte pwsf_2g_a[3]; + + u1Byte pwsf_2g_b[3]; + u4Byte lut_2g_even_a[3][64]; + u4Byte lut_2g_odd_a[3][64]; + u4Byte lut_2g_even_b[3][64]; + u4Byte lut_2g_odd_b[3][64]; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_DPK_AVG[AVG_THERMAL_NUM_DPK]; + u1Byte ThermalValue_DPK_AVG_index; + + /*Add by Yuchen for Kfree Phydm*/ + u1Byte RegRfKFreeEnable; /*for registry*/ + u1Byte RfKFreeEnable; /*for efuse enable check*/ + u4Byte TxLOK[2]; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.c b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.c index fa4f7000ab3..1b9c34c4f28 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.c +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.c @@ -1,756 +1,756 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================ */ -/* include files */ -/*============================================================ */ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//============================================================ -// Global var -//============================================================ - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { - 0x7f8001fe, /* 0, +6.0dB */ - 0x788001e2, /* 1, +5.5dB */ - 0x71c001c7, /* 2, +5.0dB*/ - 0x6b8001ae, /* 3, +4.5dB*/ - 0x65400195, /* 4, +4.0dB*/ - 0x5fc0017f, /* 5, +3.5dB*/ - 0x5a400169, /* 6, +3.0dB*/ - 0x55400155, /* 7, +2.5dB*/ - 0x50800142, /* 8, +2.0dB*/ - 0x4c000130, /* 9, +1.5dB*/ - 0x47c0011f, /* 10, +1.0dB*/ - 0x43c0010f, /* 11, +0.5dB*/ - 0x40000100, /* 12, +0dB*/ - 0x3c8000f2, /* 13, -0.5dB*/ - 0x390000e4, /* 14, -1.0dB*/ - 0x35c000d7, /* 15, -1.5dB*/ - 0x32c000cb, /* 16, -2.0dB*/ - 0x300000c0, /* 17, -2.5dB*/ - 0x2d4000b5, /* 18, -3.0dB*/ - 0x2ac000ab, /* 19, -3.5dB*/ - 0x288000a2, /* 20, -4.0dB*/ - 0x26000098, /* 21, -4.5dB*/ - 0x24000090, /* 22, -5.0dB*/ - 0x22000088, /* 23, -5.5dB*/ - 0x20000080, /* 24, -6.0dB*/ - 0x1e400079, /* 25, -6.5dB*/ - 0x1c800072, /* 26, -7.0dB*/ - 0x1b00006c, /* 27. -7.5dB*/ - 0x19800066, /* 28, -8.0dB*/ - 0x18000060, /* 29, -8.5dB*/ - 0x16c0005b, /* 30, -9.0dB*/ - 0x15800056, /* 31, -9.5dB*/ - 0x14400051, /* 32, -10.0dB*/ - 0x1300004c, /* 33, -10.5dB*/ - 0x12000048, /* 34, -11.0dB*/ - 0x11000044, /* 35, -11.5dB*/ - 0x10000040, /* 36, -12.0dB*/ -}; - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ -}; - - -u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ -}; - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { - 0x0b40002d, /* 0, -15.0dB */ - 0x0c000030, /* 1, -14.5dB*/ - 0x0cc00033, /* 2, -14.0dB*/ - 0x0d800036, /* 3, -13.5dB*/ - 0x0e400039, /* 4, -13.0dB */ - 0x0f00003c, /* 5, -12.5dB*/ - 0x10000040, /* 6, -12.0dB*/ - 0x11000044, /* 7, -11.5dB*/ - 0x12000048, /* 8, -11.0dB*/ - 0x1300004c, /* 9, -10.5dB*/ - 0x14400051, /* 10, -10.0dB*/ - 0x15800056, /* 11, -9.5dB*/ - 0x16c0005b, /* 12, -9.0dB*/ - 0x18000060, /* 13, -8.5dB*/ - 0x19800066, /* 14, -8.0dB*/ - 0x1b00006c, /* 15, -7.5dB*/ - 0x1c800072, /* 16, -7.0dB*/ - 0x1e400079, /* 17, -6.5dB*/ - 0x20000080, /* 18, -6.0dB*/ - 0x22000088, /* 19, -5.5dB*/ - 0x24000090, /* 20, -5.0dB*/ - 0x26000098, /* 21, -4.5dB*/ - 0x288000a2, /* 22, -4.0dB*/ - 0x2ac000ab, /* 23, -3.5dB*/ - 0x2d4000b5, /* 24, -3.0dB*/ - 0x300000c0, /* 25, -2.5dB*/ - 0x32c000cb, /* 26, -2.0dB*/ - 0x35c000d7, /* 27, -1.5dB*/ - 0x390000e4, /* 28, -1.0dB*/ - 0x3c8000f2, /* 29, -0.5dB*/ - 0x40000100, /* 30, +0dB*/ - 0x43c0010f, /* 31, +0.5dB*/ - 0x47c0011f, /* 32, +1.0dB*/ - 0x4c000130, /* 33, +1.5dB*/ - 0x50800142, /* 34, +2.0dB*/ - 0x55400155, /* 35, +2.5dB*/ - 0x5a400169, /* 36, +3.0dB*/ - 0x5fc0017f, /* 37, +3.5dB*/ - 0x65400195, /* 38, +4.0dB*/ - 0x6b8001ae, /* 39, +4.5dB*/ - 0x71c001c7, /* 40, +5.0dB*/ - 0x788001e2, /* 41, +5.5dB*/ - 0x7f8001fe /* 42, +6.0dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ -}; -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, /*0 , -20dB*/ - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, /* 0, -12.0dB*/ - 0x088, /* 1, -11.5dB*/ - 0x090, /* 2, -11.0dB*/ - 0x099, /* 3, -10.5dB*/ - 0x0A2, /* 4, -10.0dB*/ - 0x0AC, /* 5, -9.5dB*/ - 0x0B6, /* 6, -9.0dB*/ - 0x0C0, /*7, -8.5dB*/ - 0x0CC, /* 8, -8.0dB*/ - 0x0D8, /* 9, -7.5dB*/ - 0x0E5, /* 10, -7.0dB*/ - 0x0F2, /* 11, -6.5dB*/ - 0x101, /* 12, -6.0dB*/ - 0x110, /* 13, -5.5dB*/ - 0x120, /* 14, -5.0dB*/ - 0x131, /* 15, -4.5dB*/ - 0x143, /* 16, -4.0dB*/ - 0x156, /* 17, -3.5dB*/ - 0x16A, /* 18, -3.0dB*/ - 0x180, /* 19, -2.5dB*/ - 0x197, /* 20, -2.0dB*/ - 0x1AF, /* 21, -1.5dB*/ - 0x1C8, /* 22, -1.0dB*/ - 0x1E3, /* 23, -0.5dB*/ - 0x200, /* 24, +0 dB*/ - 0x21E, /* 25, +0.5dB*/ - 0x23E, /* 26, +1.0dB*/ - 0x261, /* 27, +1.5dB*/ - 0x285,/* 28, +2.0dB*/ - 0x2AB, /* 29, +2.5dB*/ - 0x2D3, /*30, +3.0dB*/ - 0x2FE, /* 31, +3.5dB*/ - 0x32B, /* 32, +4.0dB*/ - 0x35C, /* 33, +4.5dB*/ - 0x38E, /* 34, +5.0dB*/ - 0x3C4, /* 35, +5.5dB*/ - 0x3FE /* 36, +6.0dB */ -}; - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; -#endif - - - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_IC_11N_SERIES))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte i = 0; - u4Byte bbSwing; - u4Byte swingTableSize; - pu4Byte pSwingTable; - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B - || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B - ) { - bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); - - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE; - } else { -#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1)) - if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821) - { - bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - } - else -#endif - { - bbSwing = 0; - pSwingTable = OFDMSwingTable; - swingTableSize = OFDM_TABLE_SIZE; - } - } - - for (i = 0; i < swingTableSize; ++i) { - u4Byte tableValue = pSwingTable[i]; - - if (tableValue >= 0x100000 ) - tableValue >>= 22; - if (bbSwing == tableValue) - break; - } - return i; -} - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if(pDM_Odm->mp_mode == FALSE) - pHalData->TxPowerTrackControl = TRUE; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - else - pRFCalibrateInfo->TxPowerTrackControl = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl)); - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #ifdef RTL8188E_SUPPORT - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - } - #endif -#endif - - //pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; - - if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { - /*The index of "0 dB" in SwingTable.*/ - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ - } else { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 24; - } - pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; - pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - at the same time. In the stage2/3, we need to prive universal interface and merge all - HW dynamic mechanism. */ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - default: - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - return; - - if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { - - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) - || IS_HARDWARE_TYPE_8723B(Adapter) - || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) - || IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter) - ) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60); - } - - - - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - } - else - { - - ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); - return; - } - - odm_TXPowerTrackingThermalMeterCheck(Adapter); -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - - return; - -#endif -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND - static u1Byte TM_Trigger = 0; - - if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); - return; - } - - if (!TM_Trigger) { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) - || IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } else { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); - TM_Trigger = 0; - } -#endif -} -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//============================================================ +// Global var +//============================================================ + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB*/ + 0x6b8001ae, /* 3, +4.5dB*/ + 0x65400195, /* 4, +4.0dB*/ + 0x5fc0017f, /* 5, +3.5dB*/ + 0x5a400169, /* 6, +3.0dB*/ + 0x55400155, /* 7, +2.5dB*/ + 0x50800142, /* 8, +2.0dB*/ + 0x4c000130, /* 9, +1.5dB*/ + 0x47c0011f, /* 10, +1.0dB*/ + 0x43c0010f, /* 11, +0.5dB*/ + 0x40000100, /* 12, +0dB*/ + 0x3c8000f2, /* 13, -0.5dB*/ + 0x390000e4, /* 14, -1.0dB*/ + 0x35c000d7, /* 15, -1.5dB*/ + 0x32c000cb, /* 16, -2.0dB*/ + 0x300000c0, /* 17, -2.5dB*/ + 0x2d4000b5, /* 18, -3.0dB*/ + 0x2ac000ab, /* 19, -3.5dB*/ + 0x288000a2, /* 20, -4.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x24000090, /* 22, -5.0dB*/ + 0x22000088, /* 23, -5.5dB*/ + 0x20000080, /* 24, -6.0dB*/ + 0x1e400079, /* 25, -6.5dB*/ + 0x1c800072, /* 26, -7.0dB*/ + 0x1b00006c, /* 27. -7.5dB*/ + 0x19800066, /* 28, -8.0dB*/ + 0x18000060, /* 29, -8.5dB*/ + 0x16c0005b, /* 30, -9.0dB*/ + 0x15800056, /* 31, -9.5dB*/ + 0x14400051, /* 32, -10.0dB*/ + 0x1300004c, /* 33, -10.5dB*/ + 0x12000048, /* 34, -11.0dB*/ + 0x11000044, /* 35, -11.5dB*/ + 0x10000040, /* 36, -12.0dB*/ +}; + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ +}; + + +u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ +}; + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB*/ + 0x0cc00033, /* 2, -14.0dB*/ + 0x0d800036, /* 3, -13.5dB*/ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB*/ + 0x10000040, /* 6, -12.0dB*/ + 0x11000044, /* 7, -11.5dB*/ + 0x12000048, /* 8, -11.0dB*/ + 0x1300004c, /* 9, -10.5dB*/ + 0x14400051, /* 10, -10.0dB*/ + 0x15800056, /* 11, -9.5dB*/ + 0x16c0005b, /* 12, -9.0dB*/ + 0x18000060, /* 13, -8.5dB*/ + 0x19800066, /* 14, -8.0dB*/ + 0x1b00006c, /* 15, -7.5dB*/ + 0x1c800072, /* 16, -7.0dB*/ + 0x1e400079, /* 17, -6.5dB*/ + 0x20000080, /* 18, -6.0dB*/ + 0x22000088, /* 19, -5.5dB*/ + 0x24000090, /* 20, -5.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x288000a2, /* 22, -4.0dB*/ + 0x2ac000ab, /* 23, -3.5dB*/ + 0x2d4000b5, /* 24, -3.0dB*/ + 0x300000c0, /* 25, -2.5dB*/ + 0x32c000cb, /* 26, -2.0dB*/ + 0x35c000d7, /* 27, -1.5dB*/ + 0x390000e4, /* 28, -1.0dB*/ + 0x3c8000f2, /* 29, -0.5dB*/ + 0x40000100, /* 30, +0dB*/ + 0x43c0010f, /* 31, +0.5dB*/ + 0x47c0011f, /* 32, +1.0dB*/ + 0x4c000130, /* 33, +1.5dB*/ + 0x50800142, /* 34, +2.0dB*/ + 0x55400155, /* 35, +2.5dB*/ + 0x5a400169, /* 36, +3.0dB*/ + 0x5fc0017f, /* 37, +3.5dB*/ + 0x65400195, /* 38, +4.0dB*/ + 0x6b8001ae, /* 39, +4.5dB*/ + 0x71c001c7, /* 40, +5.0dB*/ + 0x788001e2, /* 41, +5.5dB*/ + 0x7f8001fe /* 42, +6.0dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; +u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, /* 0, -12.0dB*/ + 0x088, /* 1, -11.5dB*/ + 0x090, /* 2, -11.0dB*/ + 0x099, /* 3, -10.5dB*/ + 0x0A2, /* 4, -10.0dB*/ + 0x0AC, /* 5, -9.5dB*/ + 0x0B6, /* 6, -9.0dB*/ + 0x0C0, /*7, -8.5dB*/ + 0x0CC, /* 8, -8.0dB*/ + 0x0D8, /* 9, -7.5dB*/ + 0x0E5, /* 10, -7.0dB*/ + 0x0F2, /* 11, -6.5dB*/ + 0x101, /* 12, -6.0dB*/ + 0x110, /* 13, -5.5dB*/ + 0x120, /* 14, -5.0dB*/ + 0x131, /* 15, -4.5dB*/ + 0x143, /* 16, -4.0dB*/ + 0x156, /* 17, -3.5dB*/ + 0x16A, /* 18, -3.0dB*/ + 0x180, /* 19, -2.5dB*/ + 0x197, /* 20, -2.0dB*/ + 0x1AF, /* 21, -1.5dB*/ + 0x1C8, /* 22, -1.0dB*/ + 0x1E3, /* 23, -0.5dB*/ + 0x200, /* 24, +0 dB*/ + 0x21E, /* 25, +0.5dB*/ + 0x23E, /* 26, +1.0dB*/ + 0x261, /* 27, +1.5dB*/ + 0x285,/* 28, +2.0dB*/ + 0x2AB, /* 29, +2.5dB*/ + 0x2D3, /*30, +3.0dB*/ + 0x2FE, /* 31, +3.5dB*/ + 0x32B, /* 32, +4.0dB*/ + 0x35C, /* 33, +4.5dB*/ + 0x38E, /* 34, +5.0dB*/ + 0x3C4, /* 35, +5.5dB*/ + 0x3FE /* 36, +6.0dB */ +}; + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_IC_11N_SERIES))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + +u1Byte +getSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte i = 0; + u4Byte bbSwing; + u4Byte swingTableSize; + pu4Byte pSwingTable; + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B + || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B + ) { + bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); + + pSwingTable = OFDMSwingTable_New; + swingTableSize = OFDM_TABLE_SIZE; + } else { +#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1)) + if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821) + { + bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); + pSwingTable = TxScalingTable_Jaguar; + swingTableSize = TXSCALE_TABLE_SIZE; + } + else +#endif + { + bbSwing = 0; + pSwingTable = OFDMSwingTable; + swingTableSize = OFDM_TABLE_SIZE; + } + } + + for (i = 0; i < swingTableSize; ++i) { + u4Byte tableValue = pSwingTable[i]; + + if (tableValue >= 0x100000 ) + tableValue >>= 22; + if (bbSwing == tableValue) + break; + } + return i; +} + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if(pDM_Odm->mp_mode == FALSE) + pHalData->TxPowerTrackControl = TRUE; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + else + pRFCalibrateInfo->TxPowerTrackControl = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl)); + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef RTL8188E_SUPPORT + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + } + #endif +#endif + + //pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; + + if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { + /*The index of "0 dB" in SwingTable.*/ + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 20; + } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ + pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ + } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ + pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ + } else { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 24; + } + pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; + pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + at the same time. In the stage2/3, we need to prive universal interface and merge all + HW dynamic mechanism. */ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + default: + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + return; + + if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { + + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) + || IS_HARDWARE_TYPE_8723B(Adapter) + || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) + || IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter) + ) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60); + } + + + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + } + else + { + + ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); + return; + } + + odm_TXPowerTrackingThermalMeterCheck(Adapter); +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + + return; + +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND + static u1Byte TM_Trigger = 0; + + if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); + return; + } + + if (!TM_Trigger) { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) + || IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); + TM_Trigger = 0; + } +#endif +} +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.h b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.h index 47ecf4ff34d..015b0484301 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.h +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_ce.h @@ -1,334 +1,334 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define OFDM_TABLE_SIZE 43 -#define CCK_TABLE_SIZE 33 -#define CCK_TABLE_SIZE_88F 21 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 - -#define TXPWR_TRACK_TABLE_SIZE 30 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 4 - -#define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM_MAX 10 - -#define IQK_BB_REG_NUM 9 - - - -#define IQK_Matrix_REG_NUM 8 -#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G - -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; - -// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[3][IQK_Matrix_REG_NUM]; - BOOLEAN bBWIqkResultSaved[3]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_DPK; - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - u1Byte ThermalValue_Crystal; - u1Byte ThermalValue_DPKstore; - u1Byte ThermalValue_DPKtrack; - BOOLEAN TxPowerTrackingInProgress; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - - //------------------------- Tx power Tracking -------------------------// - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset[MAX_RF_PATH]; - s1Byte DeltaPowerIndex[MAX_RF_PATH]; - s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; - BOOLEAN bTxPowerChanged; - s1Byte XtalOffset; - s1Byte XtalOffsetLast; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; - s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN DefaultBbSwingIndexFlag; - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} - u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - - - // IQK time measurement - u8Byte IQK_StartTime; - u8Byte IQK_ProgressingTime; - u8Byte IQK_TotalProgressingTime; - - u4Byte LOK_Result; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - - // DPK - BOOLEAN bDPKFail; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - - u4Byte TxLOK[2]; - u4Byte DpkTxAGC; - s4Byte DpkGain; - u4Byte DpkThermal[4]; - s1Byte Modify_TxAGC_Value_OFDM; - s1Byte Modify_TxAGC_Value_CCK; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -VOID -odm_TXPowerTrackingCallbackThermalMeter92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackRXGainThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingDirectCall92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + + + +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + s1Byte XtalOffset; + s1Byte XtalOffsetLast; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN DefaultBbSwingIndexFlag; + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + BOOLEAN bIQKPAoff; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} + u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u1Byte IQKstep; + u1Byte Kcount; + u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + BOOLEAN isMPmode; + + + + // IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u8Byte IQK_TotalProgressingTime; + + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; + s1Byte Modify_TxAGC_Value_OFDM; + s1Byte Modify_TxAGC_Value_CCK; + + /*Add by Yuchen for Kfree Phydm*/ + u1Byte RegRfKFreeEnable; /*for registry*/ + u1Byte RfKFreeEnable; /*for efuse enable check*/ + +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.c b/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.c index 993500754af..15a243b0813 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.c +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.c @@ -1,788 +1,788 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//============================================================ -// Global var -//============================================================ - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { - 0x7f8001fe, // 0, +6.0dB - 0x788001e2, // 1, +5.5dB - 0x71c001c7, // 2, +5.0dB - 0x6b8001ae, // 3, +4.5dB - 0x65400195, // 4, +4.0dB - 0x5fc0017f, // 5, +3.5dB - 0x5a400169, // 6, +3.0dB - 0x55400155, // 7, +2.5dB - 0x50800142, // 8, +2.0dB - 0x4c000130, // 9, +1.5dB - 0x47c0011f, // 10, +1.0dB - 0x43c0010f, // 11, +0.5dB - 0x40000100, // 12, +0dB - 0x3c8000f2, // 13, -0.5dB - 0x390000e4, // 14, -1.0dB - 0x35c000d7, // 15, -1.5dB - 0x32c000cb, // 16, -2.0dB - 0x300000c0, // 17, -2.5dB - 0x2d4000b5, // 18, -3.0dB - 0x2ac000ab, // 19, -3.5dB - 0x288000a2, // 20, -4.0dB - 0x26000098, // 21, -4.5dB - 0x24000090, // 22, -5.0dB - 0x22000088, // 23, -5.5dB - 0x20000080, // 24, -6.0dB - 0x1e400079, // 25, -6.5dB - 0x1c800072, // 26, -7.0dB - 0x1b00006c, // 27. -7.5dB - 0x19800066, // 28, -8.0dB - 0x18000060, // 29, -8.5dB - 0x16c0005b, // 30, -9.0dB - 0x15800056, // 31, -9.5dB - 0x14400051, // 32, -10.0dB - 0x1300004c, // 33, -10.5dB - 0x12000048, // 34, -11.0dB - 0x11000044, // 35, -11.5dB - 0x10000040, // 36, -12.0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB -}; - - -u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB -}; - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - - - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, // 0, -12.0dB - 0x088, // 1, -11.5dB - 0x090, // 2, -11.0dB - 0x099, // 3, -10.5dB - 0x0A2, // 4, -10.0dB - 0x0AC, // 5, -9.5dB - 0x0B6, // 6, -9.0dB - 0x0C0, // 7, -8.5dB - 0x0CC, // 8, -8.0dB - 0x0D8, // 9, -7.5dB - 0x0E5, // 10, -7.0dB - 0x0F2, // 11, -6.5dB - 0x101, // 12, -6.0dB - 0x110, // 13, -5.5dB - 0x120, // 14, -5.0dB - 0x131, // 15, -4.5dB - 0x143, // 16, -4.0dB - 0x156, // 17, -3.5dB - 0x16A, // 18, -3.0dB - 0x180, // 19, -2.5dB - 0x197, // 20, -2.0dB - 0x1AF, // 21, -1.5dB - 0x1C8, // 22, -1.0dB - 0x1E3, // 23, -0.5dB - 0x200, // 24, +0 dB - 0x21E, // 25, +0.5dB - 0x23E, // 26, +1.0dB - 0x261, // 27, +1.5dB - 0x285, // 28, +2.0dB - 0x2AB, // 29, +2.5dB - 0x2D3, // 30, +3.0dB - 0x2FE, // 31, +3.5dB - 0x32B, // 32, +4.0dB - 0x35C, // 33, +4.5dB - 0x38E, // 34, +5.0dB - 0x3C4, // 35, +5.5dB - 0x3FE // 36, +6.0dB -}; -u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 -, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 -, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; - -#endif - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES|ODM_RTL8822B))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte i = 0; - u4Byte bbSwing; - u4Byte swingTableSize; - pu4Byte pSwingTable; - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) - { - bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); - - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE; - } else { - bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - } - - for (i = 0; i < swingTableSize; ++i) { - u4Byte tableValue = pSwingTable[i]; - - if (tableValue >= 0x100000 ) - tableValue >>= 22; - if (bbSwing == tableValue) - break; - } - return i; -} - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte p = 0; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = TRUE; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_RTL8188E - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - - MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl); - } - #else - { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - pdmpriv->bTXPowerTracking = _TRUE; - pdmpriv->TXPowercount = 0; - pdmpriv->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pdmpriv->TxPowerTrackControl = _TRUE; - - MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); - - } - #endif -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #ifdef RTL8188E_SUPPORT - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - } - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->TxPowerTrackControl = FALSE; - #else - pRFCalibrateInfo->TxPowerTrackControl = TRUE; - #endif -#else - pRFCalibrateInfo->TxPowerTrackControl = TRUE; -#endif - - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; - - if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { - /*The index of "0 dB" in SwingTable.*/ - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ - } else { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 24; - } - pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; - pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism.*/ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - default: - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - #if ((RTL8188F_SUPPORT == 1)) - rtl8192c_odm_CheckTXPowerTracking(Adapter); - #endif - - #if(RTL8188E_SUPPORT==1) - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) { - return; - } - - if (!pRFCalibrateInfo->TM_Trigger) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ - - pRFCalibrateInfo->TM_Trigger = 1; - return; - - } else { - /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ - odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); - pRFCalibrateInfo->TM_Trigger = 0; - } - #endif -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (*pDM_Odm->pIsFcsModeEnable) - return; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); - return; - } - - if (IS_HARDWARE_TYPE_8821B(Adapter)) /* TODO: Don't Do PowerTracking*/ - return; - - odm_TXPowerTrackingThermalMeterCheck(Adapter); - - -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ -return; - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_TXPowerTrackingDirectCall( - IN PADAPTER Adapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); -} - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND - static u1Byte TM_Trigger = 0; - - if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); - return; - } - - if (!TM_Trigger) - { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8703B(Adapter) - || IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } else { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); - TM_Trigger = 0; - } -#endif -} - -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//============================================================ +// Global var +//============================================================ + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB +}; + + +u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB +}; + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + + + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; +u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, // 0, -12.0dB + 0x088, // 1, -11.5dB + 0x090, // 2, -11.0dB + 0x099, // 3, -10.5dB + 0x0A2, // 4, -10.0dB + 0x0AC, // 5, -9.5dB + 0x0B6, // 6, -9.0dB + 0x0C0, // 7, -8.5dB + 0x0CC, // 8, -8.0dB + 0x0D8, // 9, -7.5dB + 0x0E5, // 10, -7.0dB + 0x0F2, // 11, -6.5dB + 0x101, // 12, -6.0dB + 0x110, // 13, -5.5dB + 0x120, // 14, -5.0dB + 0x131, // 15, -4.5dB + 0x143, // 16, -4.0dB + 0x156, // 17, -3.5dB + 0x16A, // 18, -3.0dB + 0x180, // 19, -2.5dB + 0x197, // 20, -2.0dB + 0x1AF, // 21, -1.5dB + 0x1C8, // 22, -1.0dB + 0x1E3, // 23, -0.5dB + 0x200, // 24, +0 dB + 0x21E, // 25, +0.5dB + 0x23E, // 26, +1.0dB + 0x261, // 27, +1.5dB + 0x285, // 28, +2.0dB + 0x2AB, // 29, +2.5dB + 0x2D3, // 30, +3.0dB + 0x2FE, // 31, +3.5dB + 0x32B, // 32, +4.0dB + 0x35C, // 33, +4.5dB + 0x38E, // 34, +5.0dB + 0x3C4, // 35, +5.5dB + 0x3FE // 36, +6.0dB +}; +u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 +, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 +, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; + +#endif + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES|ODM_RTL8822B))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + +u1Byte +getSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte i = 0; + u4Byte bbSwing; + u4Byte swingTableSize; + pu4Byte pSwingTable; + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) + { + bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); + + pSwingTable = OFDMSwingTable_New; + swingTableSize = OFDM_TABLE_SIZE; + } else { + bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); + pSwingTable = TxScalingTable_Jaguar; + swingTableSize = TXSCALE_TABLE_SIZE; + } + + for (i = 0; i < swingTableSize; ++i) { + u4Byte tableValue = pSwingTable[i]; + + if (tableValue >= 0x100000 ) + tableValue >>= 22; + if (bbSwing == tableValue) + break; + } + return i; +} + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte p = 0; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = TRUE; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_RTL8188E + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl); + } + #else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + pdmpriv->bTXPowerTracking = _TRUE; + pdmpriv->TXPowercount = 0; + pdmpriv->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pdmpriv->TxPowerTrackControl = _TRUE; + + MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); + + } + #endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef RTL8188E_SUPPORT + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + } + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (MP_DRIVER == 1) + pRFCalibrateInfo->TxPowerTrackControl = FALSE; + #else + pRFCalibrateInfo->TxPowerTrackControl = TRUE; + #endif +#else + pRFCalibrateInfo->TxPowerTrackControl = TRUE; +#endif + + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; + + if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { + /*The index of "0 dB" in SwingTable.*/ + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 20; + } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ + pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ + } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ + pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ + } else { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 24; + } + pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; + pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism.*/ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + default: + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + #if ((RTL8188F_SUPPORT == 1)) + rtl8192c_odm_CheckTXPowerTracking(Adapter); + #endif + + #if(RTL8188E_SUPPORT==1) + + if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) { + return; + } + + if (!pRFCalibrateInfo->TM_Trigger) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ + + pRFCalibrateInfo->TM_Trigger = 1; + return; + + } else { + /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pRFCalibrateInfo->TM_Trigger = 0; + } + #endif +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (*pDM_Odm->pIsFcsModeEnable) + return; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); + return; + } + + if (IS_HARDWARE_TYPE_8821B(Adapter)) /* TODO: Don't Do PowerTracking*/ + return; + + odm_TXPowerTrackingThermalMeterCheck(Adapter); + + +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ +return; + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_TXPowerTrackingDirectCall( + IN PADAPTER Adapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); +} + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND + static u1Byte TM_Trigger = 0; + + if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); + return; + } + + if (!TM_Trigger) + { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8703B(Adapter) + || IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); + TM_Trigger = 0; + } +#endif +} + +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.h b/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.h index 27e0253c1db..3ee9dc1e927 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.h +++ b/package/kernel/rtl8192cd/phydm/phydm_powertracking_win.h @@ -1,299 +1,299 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 -#define TXPWR_TRACK_TABLE_SIZE 30 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 3 -#define MAX_RF_PATH 4 -#define CCK_TABLE_SIZE_88F 21 - - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G -#define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 -#define IQK_Matrix_REG_NUM 8 -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 - -#define IQK_BB_REG_NUM 9 - - -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; - -// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[3][IQK_Matrix_REG_NUM]; - BOOLEAN bBWIqkResultSaved[3]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - //u1Byte bTXPowerTracking; - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - - //------------------------- Tx power Tracking -------------------------// - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset[MAX_RF_PATH]; - s1Byte DeltaPowerIndex[MAX_RF_PATH]; - s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; - BOOLEAN bTxPowerChanged; - s1Byte XtalOffset; - s1Byte XtalOffsetLast; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; - s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN DefaultBbSwingIndexFlag; - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ - u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u8Byte IQK_StartTime; - u8Byte IQK_TotalProgressingTime; - u8Byte IQK_ProgressingTime; - u4Byte LOK_Result; - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - - // DPK - BOOLEAN bDPKFail; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - - u4Byte TxLOK[2]; - u4Byte DpkTxAGC; - s4Byte DpkGain; - u4Byte DpkThermal[4]; - - s1Byte Modify_TxAGC_Value_OFDM; - s1Byte Modify_TxAGC_Value_CCK; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - - HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO; -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - - - - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define CCK_TABLE_SIZE_88F 21 + + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 + +#define IQK_BB_REG_NUM 9 + + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; +extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; +extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + s1Byte XtalOffset; + s1Byte XtalOffsetLast; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN DefaultBbSwingIndexFlag; + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + BOOLEAN bIQKPAoff; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u8Byte IQK_StartTime; + u8Byte IQK_TotalProgressingTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + u1Byte IQKstep; + u1Byte Kcount; + u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + BOOLEAN isMPmode; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; + + s1Byte Modify_TxAGC_Value_OFDM; + s1Byte Modify_TxAGC_Value_CCK; + + /*Add by Yuchen for Kfree Phydm*/ + u1Byte RegRfKFreeEnable; /*for registry*/ + u1Byte RfKFreeEnable; /*for efuse enable check*/ + + HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_pre_define.h b/package/kernel/rtl8192cd/phydm/phydm_pre_define.h index f0feaee89b8..8c320fc1899 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_pre_define.h +++ b/package/kernel/rtl8192cd/phydm/phydm_pre_define.h @@ -1,653 +1,653 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __PHYDMPREDEFINE_H__ -#define __PHYDMPREDEFINE_H__ - -//1 ============================================================ -//1 Definition -//1 ============================================================ - -#define PHYDM_CODE_BASE "PHYDM_TRUNK" -#define PHYDM_RELEASE_DATE "00000000" - -//Max path of IC -#define MAX_PATH_NUM_8188E 1 -#define MAX_PATH_NUM_8192E 2 -#define MAX_PATH_NUM_8723B 1 -#define MAX_PATH_NUM_8812A 2 -#define MAX_PATH_NUM_8821A 1 -#define MAX_PATH_NUM_8814A 4 -#define MAX_PATH_NUM_8822B 2 -#define MAX_PATH_NUM_8821B 2 -#define MAX_PATH_NUM_8703B 1 -#define MAX_PATH_NUM_8188F 1 -#define MAX_PATH_NUM_8723D 1 -#define MAX_PATH_NUM_8197F 2 - -//Max RF path -#define ODM_RF_PATH_MAX 2 -#define ODM_RF_PATH_MAX_JAGUAR 4 - -/*Bit define path*/ -#define PHYDM_A BIT0 -#define PHYDM_B BIT1 -#define PHYDM_C BIT2 -#define PHYDM_D BIT3 -#define PHYDM_AB (BIT0 | BIT1) -#define PHYDM_AC (BIT0 | BIT2) -#define PHYDM_AD (BIT0 | BIT3) -#define PHYDM_BC (BIT1 | BIT2) -#define PHYDM_BD (BIT1 | BIT3) -#define PHYDM_CD (BIT2 | BIT3) -#define PHYDM_ABC (BIT0 | BIT1 | BIT2) -#define PHYDM_ABD (BIT0 | BIT1 | BIT3) -#define PHYDM_ACD (BIT0 | BIT2 | BIT3) -#define PHYDM_BCD (BIT1 | BIT2 | BIT3) -#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) - -//number of entry -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) - #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ - #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM -#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define ASSOCIATE_ENTRY_NUM NUM_STAT - #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) -#else - #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) -#endif - -/* -----MGN rate--------------------------------- */ - -#define ODM_MGN_1M 0x02 -#define ODM_MGN_2M 0x04 -#define ODM_MGN_5_5M 0x0b -#define ODM_MGN_11M 0x16 - -#define ODM_MGN_6M 0x0c -#define ODM_MGN_9M 0x12 -#define ODM_MGN_12M 0x18 -#define ODM_MGN_18M 0x24 -#define ODM_MGN_24M 0x30 -#define ODM_MGN_36M 0x48 -#define ODM_MGN_48M 0x60 -#define ODM_MGN_54M 0x6c - -/*TxHT = 1*/ -#define ODM_MGN_MCS0 0x80 -#define ODM_MGN_MCS1 0x81 -#define ODM_MGN_MCS2 0x82 -#define ODM_MGN_MCS3 0x83 -#define ODM_MGN_MCS4 0x84 -#define ODM_MGN_MCS5 0x85 -#define ODM_MGN_MCS6 0x86 -#define ODM_MGN_MCS7 0x87 -#define ODM_MGN_MCS8 0x88 -#define ODM_MGN_MCS9 0x89 -#define ODM_MGN_MCS10 0x8a -#define ODM_MGN_MCS11 0x8b -#define ODM_MGN_MCS12 0x8c -#define ODM_MGN_MCS13 0x8d -#define ODM_MGN_MCS14 0x8e -#define ODM_MGN_MCS15 0x8f -#define ODM_MGN_VHT1SS_MCS0 0x90 -#define ODM_MGN_VHT1SS_MCS1 0x91 -#define ODM_MGN_VHT1SS_MCS2 0x92 -#define ODM_MGN_VHT1SS_MCS3 0x93 -#define ODM_MGN_VHT1SS_MCS4 0x94 -#define ODM_MGN_VHT1SS_MCS5 0x95 -#define ODM_MGN_VHT1SS_MCS6 0x96 -#define ODM_MGN_VHT1SS_MCS7 0x97 -#define ODM_MGN_VHT1SS_MCS8 0x98 -#define ODM_MGN_VHT1SS_MCS9 0x99 -#define ODM_MGN_VHT2SS_MCS0 0x9a -#define ODM_MGN_VHT2SS_MCS1 0x9b -#define ODM_MGN_VHT2SS_MCS2 0x9c -#define ODM_MGN_VHT2SS_MCS3 0x9d -#define ODM_MGN_VHT2SS_MCS4 0x9e -#define ODM_MGN_VHT2SS_MCS5 0x9f -#define ODM_MGN_VHT2SS_MCS6 0xa0 -#define ODM_MGN_VHT2SS_MCS7 0xa1 -#define ODM_MGN_VHT2SS_MCS8 0xa2 -#define ODM_MGN_VHT2SS_MCS9 0xa3 - -#define ODM_MGN_MCS0_SG 0xc0 -#define ODM_MGN_MCS1_SG 0xc1 -#define ODM_MGN_MCS2_SG 0xc2 -#define ODM_MGN_MCS3_SG 0xc3 -#define ODM_MGN_MCS4_SG 0xc4 -#define ODM_MGN_MCS5_SG 0xc5 -#define ODM_MGN_MCS6_SG 0xc6 -#define ODM_MGN_MCS7_SG 0xc7 -#define ODM_MGN_MCS8_SG 0xc8 -#define ODM_MGN_MCS9_SG 0xc9 -#define ODM_MGN_MCS10_SG 0xca -#define ODM_MGN_MCS11_SG 0xcb -#define ODM_MGN_MCS12_SG 0xcc -#define ODM_MGN_MCS13_SG 0xcd -#define ODM_MGN_MCS14_SG 0xce -#define ODM_MGN_MCS15_SG 0xcf - -/* -----DESC rate--------------------------------- */ - -#define ODM_RATEMCS15_SG 0x1c -#define ODM_RATEMCS32 0x20 - - -// CCK Rates, TxHT = 0 -#define ODM_RATE1M 0x00 -#define ODM_RATE2M 0x01 -#define ODM_RATE5_5M 0x02 -#define ODM_RATE11M 0x03 -// OFDM Rates, TxHT = 0 -#define ODM_RATE6M 0x04 -#define ODM_RATE9M 0x05 -#define ODM_RATE12M 0x06 -#define ODM_RATE18M 0x07 -#define ODM_RATE24M 0x08 -#define ODM_RATE36M 0x09 -#define ODM_RATE48M 0x0A -#define ODM_RATE54M 0x0B -// MCS Rates, TxHT = 1 -#define ODM_RATEMCS0 0x0C -#define ODM_RATEMCS1 0x0D -#define ODM_RATEMCS2 0x0E -#define ODM_RATEMCS3 0x0F -#define ODM_RATEMCS4 0x10 -#define ODM_RATEMCS5 0x11 -#define ODM_RATEMCS6 0x12 -#define ODM_RATEMCS7 0x13 -#define ODM_RATEMCS8 0x14 -#define ODM_RATEMCS9 0x15 -#define ODM_RATEMCS10 0x16 -#define ODM_RATEMCS11 0x17 -#define ODM_RATEMCS12 0x18 -#define ODM_RATEMCS13 0x19 -#define ODM_RATEMCS14 0x1A -#define ODM_RATEMCS15 0x1B -#define ODM_RATEMCS16 0x1C -#define ODM_RATEMCS17 0x1D -#define ODM_RATEMCS18 0x1E -#define ODM_RATEMCS19 0x1F -#define ODM_RATEMCS20 0x20 -#define ODM_RATEMCS21 0x21 -#define ODM_RATEMCS22 0x22 -#define ODM_RATEMCS23 0x23 -#define ODM_RATEMCS24 0x24 -#define ODM_RATEMCS25 0x25 -#define ODM_RATEMCS26 0x26 -#define ODM_RATEMCS27 0x27 -#define ODM_RATEMCS28 0x28 -#define ODM_RATEMCS29 0x29 -#define ODM_RATEMCS30 0x2A -#define ODM_RATEMCS31 0x2B -#define ODM_RATEVHTSS1MCS0 0x2C -#define ODM_RATEVHTSS1MCS1 0x2D -#define ODM_RATEVHTSS1MCS2 0x2E -#define ODM_RATEVHTSS1MCS3 0x2F -#define ODM_RATEVHTSS1MCS4 0x30 -#define ODM_RATEVHTSS1MCS5 0x31 -#define ODM_RATEVHTSS1MCS6 0x32 -#define ODM_RATEVHTSS1MCS7 0x33 -#define ODM_RATEVHTSS1MCS8 0x34 -#define ODM_RATEVHTSS1MCS9 0x35 -#define ODM_RATEVHTSS2MCS0 0x36 -#define ODM_RATEVHTSS2MCS1 0x37 -#define ODM_RATEVHTSS2MCS2 0x38 -#define ODM_RATEVHTSS2MCS3 0x39 -#define ODM_RATEVHTSS2MCS4 0x3A -#define ODM_RATEVHTSS2MCS5 0x3B -#define ODM_RATEVHTSS2MCS6 0x3C -#define ODM_RATEVHTSS2MCS7 0x3D -#define ODM_RATEVHTSS2MCS8 0x3E -#define ODM_RATEVHTSS2MCS9 0x3F -#define ODM_RATEVHTSS3MCS0 0x40 -#define ODM_RATEVHTSS3MCS1 0x41 -#define ODM_RATEVHTSS3MCS2 0x42 -#define ODM_RATEVHTSS3MCS3 0x43 -#define ODM_RATEVHTSS3MCS4 0x44 -#define ODM_RATEVHTSS3MCS5 0x45 -#define ODM_RATEVHTSS3MCS6 0x46 -#define ODM_RATEVHTSS3MCS7 0x47 -#define ODM_RATEVHTSS3MCS8 0x48 -#define ODM_RATEVHTSS3MCS9 0x49 -#define ODM_RATEVHTSS4MCS0 0x4A -#define ODM_RATEVHTSS4MCS1 0x4B -#define ODM_RATEVHTSS4MCS2 0x4C -#define ODM_RATEVHTSS4MCS3 0x4D -#define ODM_RATEVHTSS4MCS4 0x4E -#define ODM_RATEVHTSS4MCS5 0x4F -#define ODM_RATEVHTSS4MCS6 0x50 -#define ODM_RATEVHTSS4MCS7 0x51 -#define ODM_RATEVHTSS4MCS8 0x52 -#define ODM_RATEVHTSS4MCS9 0x53 - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) -#else - #if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) - #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) - #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) - #elif (RTL8812A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) - #elif(RTL8814A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) - #else - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define CONFIG_SFW_SUPPORTED -#endif - -//1 ============================================================ -//1 enumeration -//1 ============================================================ - - -// ODM_CMNINFO_INTERFACE -typedef enum tag_ODM_Support_Interface_Definition -{ - ODM_ITRF_PCIE = 0x1, - ODM_ITRF_USB = 0x2, - ODM_ITRF_SDIO = 0x4, - ODM_ITRF_ALL = 0x7, -}ODM_INTERFACE_E; - -// ODM_CMNINFO_IC_TYPE -typedef enum tag_ODM_Support_IC_Type_Definition -{ - ODM_RTL8188E = BIT0, - ODM_RTL8812 = BIT1, - ODM_RTL8821 = BIT2, - ODM_RTL8192E = BIT3, - ODM_RTL8723B = BIT4, - ODM_RTL8814A = BIT5, - ODM_RTL8881A = BIT6, - ODM_RTL8822B = BIT7, - ODM_RTL8703B = BIT8, - ODM_RTL8195A = BIT9, - ODM_RTL8188F = BIT10, - ODM_RTL8723D = BIT11, - ODM_RTL8197F = BIT12, - ODM_RTL8821C = BIT13, - ODM_RTL8814B = BIT14, - ODM_RTL8198F = BIT15 -}ODM_IC_TYPE_E; - - -#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A) -#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B) -#define ODM_IC_3SS (ODM_RTL8814A) -#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) - - -#define ODM_IC_11N_SERIES (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_11AC_1_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8881A) -#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) -#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F|ODM_RTL8822B|ODM_RTL8723D|ODM_RTL8821C) - -#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F) -#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) - -#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#ifdef RTK_AC_SUPPORT -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#else -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#endif - -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 0 - -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 1 - -#else - -#if ((RTL8188E_SUPPORT == 1) || \ -(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ -(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#else -#define ODM_IC_11N_SERIES_SUPPORT 0 -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#endif - -#ifdef CONFIG_BT_COEXIST -#define ODM_CONFIG_BT_COEXIST 1 -#else -#define ODM_CONFIG_BT_COEXIST 0 -#endif - -#endif - -#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) -#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 -#else -#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 -#endif - -//ODM_CMNINFO_CUT_VER -typedef enum tag_ODM_Cut_Version_Definition -{ - ODM_CUT_A = 0, - ODM_CUT_B = 1, - ODM_CUT_C = 2, - ODM_CUT_D = 3, - ODM_CUT_E = 4, - ODM_CUT_F = 5, - - ODM_CUT_I = 8, - ODM_CUT_J = 9, - ODM_CUT_K = 10, - ODM_CUT_TEST = 15, -}ODM_CUT_VERSION_E; - -// ODM_CMNINFO_FAB_VER -typedef enum tag_ODM_Fab_Version_Definition -{ - ODM_TSMC = 0, - ODM_UMC = 1, -}ODM_FAB_E; - -// ODM_CMNINFO_RF_TYPE -// -// For example 1T2R (A+AB = BIT0|BIT4|BIT5) -// -typedef enum tag_ODM_RF_Path_Bit_Definition -{ - ODM_RF_A = BIT0, - ODM_RF_B = BIT1, - ODM_RF_C = BIT2, - ODM_RF_D = BIT3, -}ODM_RF_PATH_E; - -typedef enum tag_PHYDM_RF_TX_NUM { - ODM_1T = 1, - ODM_2T = 2, - ODM_3T = 3, - ODM_4T = 4, -} ODM_RF_TX_NUM_E; - -typedef enum tag_ODM_RF_Type_Definition { - ODM_1T1R, - ODM_1T2R, - ODM_2T2R, - ODM_2T2R_GREEN, - ODM_2T3R, - ODM_2T4R, - ODM_3T3R, - ODM_3T4R, - ODM_4T4R, - ODM_XTXR -}ODM_RF_TYPE_E; - - -typedef enum tag_ODM_MAC_PHY_Mode_Definition -{ - ODM_SMSP = 0, - ODM_DMSP = 1, - ODM_DMDP = 2, -}ODM_MAC_PHY_MODE_E; - - -typedef enum tag_BT_Coexist_Definition -{ - ODM_BT_BUSY = 1, - ODM_BT_ON = 2, - ODM_BT_OFF = 3, - ODM_BT_NONE = 4, -}ODM_BT_COEXIST_E; - -// ODM_CMNINFO_OP_MODE -typedef enum tag_Operation_Mode_Definition -{ - ODM_NO_LINK = BIT0, - ODM_LINK = BIT1, - ODM_SCAN = BIT2, - ODM_POWERSAVE = BIT3, - ODM_AP_MODE = BIT4, - ODM_CLIENT_MODE = BIT5, - ODM_AD_HOC = BIT6, - ODM_WIFI_DIRECT = BIT7, - ODM_WIFI_DISPLAY = BIT8, -}ODM_OPERATION_MODE_E; - -// ODM_CMNINFO_WM_MODE -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -typedef enum tag_Wireless_Mode_Definition -{ - ODM_WM_UNKNOW = 0x0, - ODM_WM_B = BIT0, - ODM_WM_G = BIT1, - ODM_WM_A = BIT2, - ODM_WM_N24G = BIT3, - ODM_WM_N5G = BIT4, - ODM_WM_AUTO = BIT5, - ODM_WM_AC = BIT6, -}ODM_WIRELESS_MODE_E; -#else -typedef enum tag_Wireless_Mode_Definition -{ - ODM_WM_UNKNOWN = 0x00,/*0x0*/ - ODM_WM_A = BIT0, /* 0x1*/ - ODM_WM_B = BIT1, /* 0x2*/ - ODM_WM_G = BIT2,/* 0x4*/ - ODM_WM_AUTO = BIT3,/* 0x8*/ - ODM_WM_N24G = BIT4,/* 0x10*/ - ODM_WM_N5G = BIT5,/* 0x20*/ - ODM_WM_AC_5G = BIT6,/* 0x40*/ - ODM_WM_AC_24G = BIT7,/* 0x80*/ - ODM_WM_AC_ONLY = BIT8,/* 0x100*/ - ODM_WM_MAX = BIT11/* 0x800*/ - -}ODM_WIRELESS_MODE_E; -#endif - -// ODM_CMNINFO_BAND -typedef enum tag_Band_Type_Definition -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_BAND_2_4G = BIT0, - ODM_BAND_5G = BIT1, -#else - ODM_BAND_2_4G = 0, - ODM_BAND_5G, - ODM_BAND_ON_BOTH, - ODM_BANDMAX -#endif -}ODM_BAND_TYPE_E; - - -// ODM_CMNINFO_SEC_CHNL_OFFSET -typedef enum tag_Secondary_Channel_Offset_Definition { - - PHYDM_DONT_CARE = 0, - PHYDM_BELOW = 1, - PHYDM_ABOVE = 2 -} PHYDM_SEC_CHNL_OFFSET_E; - -// ODM_CMNINFO_SEC_MODE -typedef enum tag_Security_Definition -{ - ODM_SEC_OPEN = 0, - ODM_SEC_WEP40 = 1, - ODM_SEC_TKIP = 2, - ODM_SEC_RESERVE = 3, - ODM_SEC_AESCCMP = 4, - ODM_SEC_WEP104 = 5, - ODM_WEP_WPA_MIXED = 6, // WEP + WPA - ODM_SEC_SMS4 = 7, -}ODM_SECURITY_E; - -// ODM_CMNINFO_BW -typedef enum tag_Bandwidth_Definition -{ - ODM_BW20M = 0, - ODM_BW40M = 1, - ODM_BW80M = 2, - ODM_BW160M = 3, - ODM_BW5M = 4, - ODM_BW10M = 5, - ODM_BW_MAX = 6 -}ODM_BW_E; - -// ODM_CMNINFO_CHNL - -// ODM_CMNINFO_BOARD_TYPE -typedef enum tag_Board_Definition -{ - ODM_BOARD_DEFAULT = 0, // The DEFAULT case. - ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. - ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card - ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT - ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA - ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA - ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW - ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA - ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA -}ODM_BOARD_TYPE_E; - -typedef enum tag_ODM_Package_Definition -{ - ODM_PACKAGE_DEFAULT = 0, - ODM_PACKAGE_QFN68 = BIT(0), - ODM_PACKAGE_TFBGA90 = BIT(1), - ODM_PACKAGE_TFBGA79 = BIT(2), -}ODM_Package_TYPE_E; - -typedef enum tag_ODM_TYPE_GPA_Definition { - TYPE_GPA0 = 0x0000, - TYPE_GPA1 = 0x0055, - TYPE_GPA2 = 0x00AA, - TYPE_GPA3 = 0x00FF, - TYPE_GPA4 = 0x5500, - TYPE_GPA5 = 0x5555, - TYPE_GPA6 = 0x55AA, - TYPE_GPA7 = 0x55FF, - TYPE_GPA8 = 0xAA00, - TYPE_GPA9 = 0xAA55, - TYPE_GPA10 = 0xAAAA, - TYPE_GPA11 = 0xAAFF, - TYPE_GPA12 = 0xFF00, - TYPE_GPA13 = 0xFF55, - TYPE_GPA14 = 0xFFAA, - TYPE_GPA15 = 0xFFFF, -}ODM_TYPE_GPA_E; - -typedef enum tag_ODM_TYPE_APA_Definition { - TYPE_APA0 = 0x0000, - TYPE_APA1 = 0x0055, - TYPE_APA2 = 0x00AA, - TYPE_APA3 = 0x00FF, - TYPE_APA4 = 0x5500, - TYPE_APA5 = 0x5555, - TYPE_APA6 = 0x55AA, - TYPE_APA7 = 0x55FF, - TYPE_APA8 = 0xAA00, - TYPE_APA9 = 0xAA55, - TYPE_APA10 = 0xAAAA, - TYPE_APA11 = 0xAAFF, - TYPE_APA12 = 0xFF00, - TYPE_APA13 = 0xFF55, - TYPE_APA14 = 0xFFAA, - TYPE_APA15 = 0xFFFF, -}ODM_TYPE_APA_E; - -typedef enum tag_ODM_TYPE_GLNA_Definition { - TYPE_GLNA0 = 0x0000, - TYPE_GLNA1 = 0x0055, - TYPE_GLNA2 = 0x00AA, - TYPE_GLNA3 = 0x00FF, - TYPE_GLNA4 = 0x5500, - TYPE_GLNA5 = 0x5555, - TYPE_GLNA6 = 0x55AA, - TYPE_GLNA7 = 0x55FF, - TYPE_GLNA8 = 0xAA00, - TYPE_GLNA9 = 0xAA55, - TYPE_GLNA10 = 0xAAAA, - TYPE_GLNA11 = 0xAAFF, - TYPE_GLNA12 = 0xFF00, - TYPE_GLNA13 = 0xFF55, - TYPE_GLNA14 = 0xFFAA, - TYPE_GLNA15 = 0xFFFF, -}ODM_TYPE_GLNA_E; - -typedef enum tag_ODM_TYPE_ALNA_Definition { - TYPE_ALNA0 = 0x0000, - TYPE_ALNA1 = 0x0055, - TYPE_ALNA2 = 0x00AA, - TYPE_ALNA3 = 0x00FF, - TYPE_ALNA4 = 0x5500, - TYPE_ALNA5 = 0x5555, - TYPE_ALNA6 = 0x55AA, - TYPE_ALNA7 = 0x55FF, - TYPE_ALNA8 = 0xAA00, - TYPE_ALNA9 = 0xAA55, - TYPE_ALNA10 = 0xAAAA, - TYPE_ALNA11 = 0xAAFF, - TYPE_ALNA12 = 0xFF00, - TYPE_ALNA13 = 0xFF55, - TYPE_ALNA14 = 0xFFAA, - TYPE_ALNA15 = 0xFFFF, -}ODM_TYPE_ALNA_E; - - -typedef enum _ODM_RF_RADIO_PATH { - ODM_RF_PATH_A = 0, //Radio Path A - ODM_RF_PATH_B = 1, //Radio Path B - ODM_RF_PATH_C = 2, //Radio Path C - ODM_RF_PATH_D = 3, //Radio Path D - ODM_RF_PATH_AB, - ODM_RF_PATH_AC, - ODM_RF_PATH_AD, - ODM_RF_PATH_BC, - ODM_RF_PATH_BD, - ODM_RF_PATH_CD, - ODM_RF_PATH_ABC, - ODM_RF_PATH_ACD, - ODM_RF_PATH_BCD, - ODM_RF_PATH_ABCD, - // ODM_RF_PATH_MAX, //Max RF number 90 support -} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; - -typedef enum _ODM_PARAMETER_INIT { - ODM_PRE_SETTING = 0, - ODM_POST_SETTING = 1, -} ODM_PARAMETER_INIT_E; - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +#define PHYDM_CODE_BASE "PHYDM_TRUNK" +#define PHYDM_RELEASE_DATE "00000000" + +//Max path of IC +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8821B 2 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8188F 1 +#define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8197F 2 + +//Max RF path +#define ODM_RF_PATH_MAX 2 +#define ODM_RF_PATH_MAX_JAGUAR 4 + +/*Bit define path*/ +#define PHYDM_A BIT0 +#define PHYDM_B BIT1 +#define PHYDM_C BIT2 +#define PHYDM_D BIT3 +#define PHYDM_AB (BIT0 | BIT1) +#define PHYDM_AC (BIT0 | BIT2) +#define PHYDM_AD (BIT0 | BIT3) +#define PHYDM_BC (BIT1 | BIT2) +#define PHYDM_BD (BIT1 | BIT3) +#define PHYDM_CD (BIT2 | BIT3) +#define PHYDM_ABC (BIT0 | BIT1 | BIT2) +#define PHYDM_ABD (BIT0 | BIT1 | BIT3) +#define PHYDM_ACD (BIT0 | BIT2 | BIT3) +#define PHYDM_BCD (BIT1 | BIT2 | BIT3) +#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) + +//number of entry +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) +#else + #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) +#endif + +/* -----MGN rate--------------------------------- */ + +#define ODM_MGN_1M 0x02 +#define ODM_MGN_2M 0x04 +#define ODM_MGN_5_5M 0x0b +#define ODM_MGN_11M 0x16 + +#define ODM_MGN_6M 0x0c +#define ODM_MGN_9M 0x12 +#define ODM_MGN_12M 0x18 +#define ODM_MGN_18M 0x24 +#define ODM_MGN_24M 0x30 +#define ODM_MGN_36M 0x48 +#define ODM_MGN_48M 0x60 +#define ODM_MGN_54M 0x6c + +/*TxHT = 1*/ +#define ODM_MGN_MCS0 0x80 +#define ODM_MGN_MCS1 0x81 +#define ODM_MGN_MCS2 0x82 +#define ODM_MGN_MCS3 0x83 +#define ODM_MGN_MCS4 0x84 +#define ODM_MGN_MCS5 0x85 +#define ODM_MGN_MCS6 0x86 +#define ODM_MGN_MCS7 0x87 +#define ODM_MGN_MCS8 0x88 +#define ODM_MGN_MCS9 0x89 +#define ODM_MGN_MCS10 0x8a +#define ODM_MGN_MCS11 0x8b +#define ODM_MGN_MCS12 0x8c +#define ODM_MGN_MCS13 0x8d +#define ODM_MGN_MCS14 0x8e +#define ODM_MGN_MCS15 0x8f +#define ODM_MGN_VHT1SS_MCS0 0x90 +#define ODM_MGN_VHT1SS_MCS1 0x91 +#define ODM_MGN_VHT1SS_MCS2 0x92 +#define ODM_MGN_VHT1SS_MCS3 0x93 +#define ODM_MGN_VHT1SS_MCS4 0x94 +#define ODM_MGN_VHT1SS_MCS5 0x95 +#define ODM_MGN_VHT1SS_MCS6 0x96 +#define ODM_MGN_VHT1SS_MCS7 0x97 +#define ODM_MGN_VHT1SS_MCS8 0x98 +#define ODM_MGN_VHT1SS_MCS9 0x99 +#define ODM_MGN_VHT2SS_MCS0 0x9a +#define ODM_MGN_VHT2SS_MCS1 0x9b +#define ODM_MGN_VHT2SS_MCS2 0x9c +#define ODM_MGN_VHT2SS_MCS3 0x9d +#define ODM_MGN_VHT2SS_MCS4 0x9e +#define ODM_MGN_VHT2SS_MCS5 0x9f +#define ODM_MGN_VHT2SS_MCS6 0xa0 +#define ODM_MGN_VHT2SS_MCS7 0xa1 +#define ODM_MGN_VHT2SS_MCS8 0xa2 +#define ODM_MGN_VHT2SS_MCS9 0xa3 + +#define ODM_MGN_MCS0_SG 0xc0 +#define ODM_MGN_MCS1_SG 0xc1 +#define ODM_MGN_MCS2_SG 0xc2 +#define ODM_MGN_MCS3_SG 0xc3 +#define ODM_MGN_MCS4_SG 0xc4 +#define ODM_MGN_MCS5_SG 0xc5 +#define ODM_MGN_MCS6_SG 0xc6 +#define ODM_MGN_MCS7_SG 0xc7 +#define ODM_MGN_MCS8_SG 0xc8 +#define ODM_MGN_MCS9_SG 0xc9 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* -----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + + +// CCK Rates, TxHT = 0 +#define ODM_RATE1M 0x00 +#define ODM_RATE2M 0x01 +#define ODM_RATE5_5M 0x02 +#define ODM_RATE11M 0x03 +// OFDM Rates, TxHT = 0 +#define ODM_RATE6M 0x04 +#define ODM_RATE9M 0x05 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +// MCS Rates, TxHT = 1 +#define ODM_RATEMCS0 0x0C +#define ODM_RATEMCS1 0x0D +#define ODM_RATEMCS2 0x0E +#define ODM_RATEMCS3 0x0F +#define ODM_RATEMCS4 0x10 +#define ODM_RATEMCS5 0x11 +#define ODM_RATEMCS6 0x12 +#define ODM_RATEMCS7 0x13 +#define ODM_RATEMCS8 0x14 +#define ODM_RATEMCS9 0x15 +#define ODM_RATEMCS10 0x16 +#define ODM_RATEMCS11 0x17 +#define ODM_RATEMCS12 0x18 +#define ODM_RATEMCS13 0x19 +#define ODM_RATEMCS14 0x1A +#define ODM_RATEMCS15 0x1B +#define ODM_RATEMCS16 0x1C +#define ODM_RATEMCS17 0x1D +#define ODM_RATEMCS18 0x1E +#define ODM_RATEMCS19 0x1F +#define ODM_RATEMCS20 0x20 +#define ODM_RATEMCS21 0x21 +#define ODM_RATEMCS22 0x22 +#define ODM_RATEMCS23 0x23 +#define ODM_RATEMCS24 0x24 +#define ODM_RATEMCS25 0x25 +#define ODM_RATEMCS26 0x26 +#define ODM_RATEMCS27 0x27 +#define ODM_RATEMCS28 0x28 +#define ODM_RATEMCS29 0x29 +#define ODM_RATEMCS30 0x2A +#define ODM_RATEMCS31 0x2B +#define ODM_RATEVHTSS1MCS0 0x2C +#define ODM_RATEVHTSS1MCS1 0x2D +#define ODM_RATEVHTSS1MCS2 0x2E +#define ODM_RATEVHTSS1MCS3 0x2F +#define ODM_RATEVHTSS1MCS4 0x30 +#define ODM_RATEVHTSS1MCS5 0x31 +#define ODM_RATEVHTSS1MCS6 0x32 +#define ODM_RATEVHTSS1MCS7 0x33 +#define ODM_RATEVHTSS1MCS8 0x34 +#define ODM_RATEVHTSS1MCS9 0x35 +#define ODM_RATEVHTSS2MCS0 0x36 +#define ODM_RATEVHTSS2MCS1 0x37 +#define ODM_RATEVHTSS2MCS2 0x38 +#define ODM_RATEVHTSS2MCS3 0x39 +#define ODM_RATEVHTSS2MCS4 0x3A +#define ODM_RATEVHTSS2MCS5 0x3B +#define ODM_RATEVHTSS2MCS6 0x3C +#define ODM_RATEVHTSS2MCS7 0x3D +#define ODM_RATEVHTSS2MCS8 0x3E +#define ODM_RATEVHTSS2MCS9 0x3F +#define ODM_RATEVHTSS3MCS0 0x40 +#define ODM_RATEVHTSS3MCS1 0x41 +#define ODM_RATEVHTSS3MCS2 0x42 +#define ODM_RATEVHTSS3MCS3 0x43 +#define ODM_RATEVHTSS3MCS4 0x44 +#define ODM_RATEVHTSS3MCS5 0x45 +#define ODM_RATEVHTSS3MCS6 0x46 +#define ODM_RATEVHTSS3MCS7 0x47 +#define ODM_RATEVHTSS3MCS8 0x48 +#define ODM_RATEVHTSS3MCS9 0x49 +#define ODM_RATEVHTSS4MCS0 0x4A +#define ODM_RATEVHTSS4MCS1 0x4B +#define ODM_RATEVHTSS4MCS2 0x4C +#define ODM_RATEVHTSS4MCS3 0x4D +#define ODM_RATEVHTSS4MCS4 0x4E +#define ODM_RATEVHTSS4MCS5 0x4F +#define ODM_RATEVHTSS4MCS6 0x50 +#define ODM_RATEVHTSS4MCS7 0x51 +#define ODM_RATEVHTSS4MCS8 0x52 +#define ODM_RATEVHTSS4MCS9 0x53 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) +#else + #if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) + #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) + #elif (RTL8812A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) + #elif(RTL8814A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) + #else + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define CONFIG_SFW_SUPPORTED +#endif + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + +// ODM_CMNINFO_INTERFACE +typedef enum tag_ODM_Support_Interface_Definition +{ + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}ODM_INTERFACE_E; + +// ODM_CMNINFO_IC_TYPE +typedef enum tag_ODM_Support_IC_Type_Definition +{ + ODM_RTL8188E = BIT0, + ODM_RTL8812 = BIT1, + ODM_RTL8821 = BIT2, + ODM_RTL8192E = BIT3, + ODM_RTL8723B = BIT4, + ODM_RTL8814A = BIT5, + ODM_RTL8881A = BIT6, + ODM_RTL8822B = BIT7, + ODM_RTL8703B = BIT8, + ODM_RTL8195A = BIT9, + ODM_RTL8188F = BIT10, + ODM_RTL8723D = BIT11, + ODM_RTL8197F = BIT12, + ODM_RTL8821C = BIT13, + ODM_RTL8814B = BIT14, + ODM_RTL8198F = BIT15 +}ODM_IC_TYPE_E; + + +#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A) +#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B) +#define ODM_IC_3SS (ODM_RTL8814A) +#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) + + +#define ODM_IC_11N_SERIES (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) +#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8821C) +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) +#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F|ODM_RTL8822B|ODM_RTL8723D|ODM_RTL8821C) + +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) + +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif + +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 1 + +#else + +#if ((RTL8188E_SUPPORT == 1) || \ +(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ +(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#else +#define ODM_IC_11N_SERIES_SUPPORT 0 +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#ifdef CONFIG_BT_COEXIST +#define ODM_CONFIG_BT_COEXIST 1 +#else +#define ODM_CONFIG_BT_COEXIST 0 +#endif + +#endif + +#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) +#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 +#else +#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 +#endif + +//ODM_CMNINFO_CUT_VER +typedef enum tag_ODM_Cut_Version_Definition +{ + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}ODM_CUT_VERSION_E; + +// ODM_CMNINFO_FAB_VER +typedef enum tag_ODM_Fab_Version_Definition +{ + ODM_TSMC = 0, + ODM_UMC = 1, +}ODM_FAB_E; + +// ODM_CMNINFO_RF_TYPE +// +// For example 1T2R (A+AB = BIT0|BIT4|BIT5) +// +typedef enum tag_ODM_RF_Path_Bit_Definition +{ + ODM_RF_A = BIT0, + ODM_RF_B = BIT1, + ODM_RF_C = BIT2, + ODM_RF_D = BIT3, +}ODM_RF_PATH_E; + +typedef enum tag_PHYDM_RF_TX_NUM { + ODM_1T = 1, + ODM_2T = 2, + ODM_3T = 3, + ODM_4T = 4, +} ODM_RF_TX_NUM_E; + +typedef enum tag_ODM_RF_Type_Definition { + ODM_1T1R, + ODM_1T2R, + ODM_2T2R, + ODM_2T2R_GREEN, + ODM_2T3R, + ODM_2T4R, + ODM_3T3R, + ODM_3T4R, + ODM_4T4R, + ODM_XTXR +}ODM_RF_TYPE_E; + + +typedef enum tag_ODM_MAC_PHY_Mode_Definition +{ + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}ODM_MAC_PHY_MODE_E; + + +typedef enum tag_BT_Coexist_Definition +{ + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}ODM_BT_COEXIST_E; + +// ODM_CMNINFO_OP_MODE +typedef enum tag_Operation_Mode_Definition +{ + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}ODM_OPERATION_MODE_E; + +// ODM_CMNINFO_WM_MODE +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}ODM_WIRELESS_MODE_E; +#else +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOWN = 0x00,/*0x0*/ + ODM_WM_A = BIT0, /* 0x1*/ + ODM_WM_B = BIT1, /* 0x2*/ + ODM_WM_G = BIT2,/* 0x4*/ + ODM_WM_AUTO = BIT3,/* 0x8*/ + ODM_WM_N24G = BIT4,/* 0x10*/ + ODM_WM_N5G = BIT5,/* 0x20*/ + ODM_WM_AC_5G = BIT6,/* 0x40*/ + ODM_WM_AC_24G = BIT7,/* 0x80*/ + ODM_WM_AC_ONLY = BIT8,/* 0x100*/ + ODM_WM_MAX = BIT11/* 0x800*/ + +}ODM_WIRELESS_MODE_E; +#endif + +// ODM_CMNINFO_BAND +typedef enum tag_Band_Type_Definition +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + ODM_BAND_2_4G = BIT0, + ODM_BAND_5G = BIT1, +#else + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX +#endif +}ODM_BAND_TYPE_E; + + +// ODM_CMNINFO_SEC_CHNL_OFFSET +typedef enum tag_Secondary_Channel_Offset_Definition { + + PHYDM_DONT_CARE = 0, + PHYDM_BELOW = 1, + PHYDM_ABOVE = 2 +} PHYDM_SEC_CHNL_OFFSET_E; + +// ODM_CMNINFO_SEC_MODE +typedef enum tag_Security_Definition +{ + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_SEC_SMS4 = 7, +}ODM_SECURITY_E; + +// ODM_CMNINFO_BW +typedef enum tag_Bandwidth_Definition +{ + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW5M = 4, + ODM_BW10M = 5, + ODM_BW_MAX = 6 +}ODM_BW_E; + +// ODM_CMNINFO_CHNL + +// ODM_CMNINFO_BOARD_TYPE +typedef enum tag_Board_Definition +{ + ODM_BOARD_DEFAULT = 0, // The DEFAULT case. + ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. + ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card + ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT + ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA + ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA + ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW + ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA + ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA +}ODM_BOARD_TYPE_E; + +typedef enum tag_ODM_Package_Definition +{ + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}ODM_Package_TYPE_E; + +typedef enum tag_ODM_TYPE_GPA_Definition { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, +}ODM_TYPE_GPA_E; + +typedef enum tag_ODM_TYPE_APA_Definition { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, +}ODM_TYPE_APA_E; + +typedef enum tag_ODM_TYPE_GLNA_Definition { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, +}ODM_TYPE_GLNA_E; + +typedef enum tag_ODM_TYPE_ALNA_Definition { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, +}ODM_TYPE_ALNA_E; + + +typedef enum _ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, //Radio Path A + ODM_RF_PATH_B = 1, //Radio Path B + ODM_RF_PATH_C = 2, //Radio Path C + ODM_RF_PATH_D = 3, //Radio Path D + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + // ODM_RF_PATH_MAX, //Max RF number 90 support +} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; + +typedef enum _ODM_PARAMETER_INIT { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, +} ODM_PARAMETER_INIT_E; + +#endif diff --git a/package/kernel/rtl8192cd/phydm/phydm_precomp.h b/package/kernel/rtl8192cd/phydm/phydm_precomp.h index 6dab34253ac..2942692f943 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_precomp.h +++ b/package/kernel/rtl8192cd/phydm/phydm_precomp.h @@ -1,348 +1,348 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __ODM_PRECOMP_H__ -#define __ODM_PRECOMP_H__ - -#include "phydm_types.h" - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. -#else -#define TEST_FALG___ 1 -#endif - -//2 Config Flags and Structs - defined by each ODM Type - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "../8192cd_cfg.h" - #include "../odm_inc.h" - - #include "../8192cd.h" - #include "../8192cd_util.h" - #ifdef _BIG_ENDIAN_ - #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG - #else - #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE - #endif - - #ifdef AP_BUILD_WORKAROUND - #include "../8192cd_headers.h" - #include "../8192cd_debug.h" - #endif - -#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) - #define __PACK - #define __WLAN_ATTRIB_PACK__ -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "mp_precomp.h" - #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE - #define __PACK - #define __WLAN_ATTRIB_PACK__ -#endif - -//2 OutSrc Header Files - -#include "phydm.h" -#include "phydm_hwconfig.h" -#include "phydm_debug.h" -#include "phydm_regdefine11ac.h" -#include "phydm_regdefine11n.h" -#include "phydm_interface.h" -#include "phydm_reg.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#include "phydm_adc_sampling.h" -#endif - - -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -VOID -PHY_SetTxPowerLimit( - IN PDM_ODM_T pDM_Odm, - IN u8 *Regulation, - IN u8 *Band, - IN u8 *Bandwidth, - IN u8 *RateSection, - IN u8 *RfPath, - IN u8 *Channel, - IN u8 *PowerLimit -); - -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#define RTL8703B_SUPPORT 0 -#define RTL8188F_SUPPORT 0 -#define RTL8723D_SUPPORT 0 -#endif - -#if RTL8188E_SUPPORT == 1 -#define RTL8188E_T_SUPPORT 1 -#ifdef CONFIG_SFW_SUPPORTED -#define RTL8188E_S_SUPPORT 1 -#else -#define RTL8188E_S_SUPPORT 0 -#endif -#endif - -#if (RTL8188E_SUPPORT==1) -#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training -#include "rtl8188e/halhwimg8188e_mac.h" -#include "rtl8188e/halhwimg8188e_rf.h" -#include "rtl8188e/halhwimg8188e_bb.h" -#include "rtl8188e/halhwimg8188e_t_fw.h" -#include "rtl8188e/halhwimg8188e_s_fw.h" -#include "rtl8188e/phydm_regconfig8188e.h" -#include "rtl8188e/phydm_rtl8188e.h" -#include "rtl8188e/hal8188ereg.h" -#include "rtl8188e/version_rtl8188e.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8188e_hal.h" - #include "rtl8188e/halphyrf_8188e_ce.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8188e/halphyrf_8188e_win.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8188e/halphyrf_8188e_ap.h" -#endif -#endif //88E END - -#if (RTL8192E_SUPPORT==1) - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ - #endif - -#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK -#include "rtl8192e/version_rtl8192e.h" -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8192e/halhwimg8192e_bb.h" - #include "rtl8192e/halhwimg8192e_mac.h" - #include "rtl8192e/halhwimg8192e_rf.h" - #include "rtl8192e/phydm_regconfig8192e.h" - #include "rtl8192e/halhwimg8192e_fw.h" - #include "rtl8192e/hal8192ereg.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8192e_hal.h" -#endif -#endif //92E END - -#if (RTL8812A_SUPPORT==1) - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8812a/halphyrf_8812a_win.h" - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8812a/halphyrf_8812a_ap.h" - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8812a/halphyrf_8812a_ce.h" - #endif - - //#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8812a/halhwimg8812a_bb.h" - #include "rtl8812a/halhwimg8812a_mac.h" - #include "rtl8812a/halhwimg8812a_rf.h" - #include "rtl8812a/phydm_regconfig8812a.h" - #include "rtl8812a/halhwimg8812a_fw.h" - #include "rtl8812a/phydm_rtl8812a.h" - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8812a_hal.h" - #endif - #include "rtl8812a/version_rtl8812a.h" - -#endif //8812 END - -#if (RTL8814A_SUPPORT==1) - -#include "rtl8814a/halhwimg8814a_mac.h" -#include "rtl8814a/halhwimg8814a_rf.h" -#include "rtl8814a/halhwimg8814a_bb.h" -#include "rtl8814a/version_rtl8814a.h" -#include "rtl8814a/phydm_rtl8814a.h" -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8814a/halhwimg8814a_fw.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8814a/halphyrf_8814a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8814a/halphyrf_8814a_ce.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8814a/halphyrf_8814a_ap.h" -#endif - #include "rtl8814a/phydm_regconfig8814a.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8814a_hal.h" - #include "rtl8814a/phydm_iqk_8814a.h" -#endif -#endif //8814 END - -#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "rtl8821a/phydm_iqk_8821a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8821a/phydm_iqk_8821a_ce.h" -#else -#include "rtl8821a/phydm_iqk_8821a_ap.h" -#endif -//#include "rtl8881a/HalHWImg8881A_BB.h" -//#include "rtl8881a/HalHWImg8881A_MAC.h" -//#include "rtl8881a/HalHWImg8881A_RF.h" -//#include "rtl8881a/odm_RegConfig8881A.h" -#endif - -#if (RTL8723B_SUPPORT==1) -#include "rtl8723b/halhwimg8723b_mac.h" -#include "rtl8723b/halhwimg8723b_rf.h" -#include "rtl8723b/halhwimg8723b_bb.h" -#include "rtl8723b/halhwimg8723b_fw.h" -#include "rtl8723b/phydm_regconfig8723b.h" -#include "rtl8723b/phydm_rtl8723b.h" -#include "rtl8723b/hal8723breg.h" -#include "rtl8723b/version_rtl8723b.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8723b/halphyrf_8723b_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8723b/halphyrf_8723b_ce.h" - #include "rtl8723b/halhwimg8723b_mp.h" - #include "rtl8723b_hal.h" -#else - #include "rtl8723b/halphyrf_8723b_ap.h" -#endif -#endif - -#if (RTL8821A_SUPPORT==1) -#include "rtl8821a/halhwimg8821a_mac.h" -#include "rtl8821a/halhwimg8821a_rf.h" -#include "rtl8821a/halhwimg8821a_bb.h" -#include "rtl8821a/halhwimg8821a_fw.h" -#include "rtl8821a/phydm_regconfig8821a.h" -#include "rtl8821a/phydm_rtl8821a.h" -#include "rtl8821a/version_rtl8821a.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8821a/halphyrf_8821a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821a/halphyrf_8821a_ce.h" - #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ - #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ - #include "rtl8812a_hal.h" -#else -#endif -#endif - -#if (RTL8822B_SUPPORT==1) -#include "rtl8822b/halhwimg8822b_mac.h" -#include "rtl8822b/halhwimg8822b_rf.h" -#include "rtl8822b/halhwimg8822b_bb.h" -#include "rtl8822b/halhwimg8822b_fw.h" -#include "rtl8822b/phydm_regconfig8822b.h" -#include "rtl8822b/halphyrf_8822b.h" -#include "rtl8822b/phydm_rtl8822b.h" -#include "rtl8822b/phydm_hal_api8822b.h" -#include "rtl8822b/version_rtl8822b.h" - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include /* struct HAL_DATA_TYPE */ -#include /* Rx_Smooth_Factor, reg definition and etc.*/ -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -#endif - -#endif - -#if (RTL8703B_SUPPORT==1) -#include "rtl8703b/phydm_regconfig8703b.h" -#include "rtl8703b/halhwimg8703b_mac.h" -#include "rtl8703b/halhwimg8703b_rf.h" -#include "rtl8703b/halhwimg8703b_bb.h" -#include "rtl8703b/halhwimg8703b_fw.h" -#include "rtl8703b/halphyrf_8703b.h" -#include "rtl8703b/version_rtl8703b.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8703b_hal.h" -#endif -#endif - -#if (RTL8188F_SUPPORT == 1) -#include "rtl8188f/halhwimg8188f_mac.h" -#include "rtl8188f/halhwimg8188f_rf.h" -#include "rtl8188f/halhwimg8188f_bb.h" -#include "rtl8188f/halhwimg8188f_fw.h" -#include "rtl8188f/hal8188freg.h" -#include "rtl8188f/phydm_rtl8188f.h" -#include "rtl8188f/phydm_regconfig8188f.h" -#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ -#include "rtl8188f/version_rtl8188f.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8188f_hal.h" -#endif -#endif - -#if (RTL8723D_SUPPORT==1) - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - - #include "rtl8723d/halhwimg8723d_bb.h" - #include "rtl8723d/halhwimg8723d_mac.h" - #include "rtl8723d/halhwimg8723d_rf.h" - #include "rtl8723d/phydm_regconfig8723d.h" - #include "rtl8723d/halhwimg8723d_fw.h" - #include "rtl8723d/hal8723dreg.h" - #include "rtl8723d/phydm_rtl8723d.h" - #include "rtl8723d/halphyrf_8723d.h" - #include "rtl8723d/version_rtl8723d.h" - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8723d_hal.h" - #endif -#endif //8723D End - -#if (RTL8197F_SUPPORT == 1) -#include "rtl8197f/halhwimg8197f_mac.h" -#include "rtl8197f/halhwimg8197f_rf.h" -#include "rtl8197f/halhwimg8197f_bb.h" -#include "rtl8197f/phydm_hal_api8197f.h" -#include "rtl8197f/version_rtl8197f.h" -#include "rtl8197f/phydm_rtl8197f.h" -#include "rtl8197f/phydm_regconfig8197f.h" -#include "rtl8197f/halphyrf_8197f.h" -#include "rtl8197f/phydm_iqk_8197f.h" -#endif - -#if (RTL8821C_SUPPORT==1) -#include "rtl8821c/phydm_hal_api8821c.h" -#include "rtl8821c/halhwimg8821c_testchip_mac.h" -#include "rtl8821c/halhwimg8821c_testchip_rf.h" -#include "rtl8821c/halhwimg8821c_testchip_bb.h" -#include "rtl8821c/phydm_regconfig8821c.h" -#include "rtl8821c/version_rtl8821c.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821c_hal.h" -#endif -#endif - -#endif // __ODM_PRECOMP_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. +#else +#define TEST_FALG___ 1 +#endif + +//2 Config Flags and Structs - defined by each ODM Type + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef AP_BUILD_WORKAROUND + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "mp_precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#endif + +//2 OutSrc Header Files + +#include "phydm.h" +#include "phydm_hwconfig.h" +#include "phydm_debug.h" +#include "phydm_regdefine11ac.h" +#include "phydm_regdefine11n.h" +#include "phydm_interface.h" +#include "phydm_reg.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#include "phydm_adc_sampling.h" +#endif + + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +VOID +PHY_SetTxPowerLimit( + IN PDM_ODM_T pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *RfPath, + IN u8 *Channel, + IN u8 *PowerLimit +); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#define RTL8703B_SUPPORT 0 +#define RTL8188F_SUPPORT 0 +#define RTL8723D_SUPPORT 0 +#endif + +#if RTL8188E_SUPPORT == 1 +#define RTL8188E_T_SUPPORT 1 +#ifdef CONFIG_SFW_SUPPORTED +#define RTL8188E_S_SUPPORT 1 +#else +#define RTL8188E_S_SUPPORT 0 +#endif +#endif + +#if (RTL8188E_SUPPORT==1) +#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training +#include "rtl8188e/halhwimg8188e_mac.h" +#include "rtl8188e/halhwimg8188e_rf.h" +#include "rtl8188e/halhwimg8188e_bb.h" +#include "rtl8188e/halhwimg8188e_t_fw.h" +#include "rtl8188e/halhwimg8188e_s_fw.h" +#include "rtl8188e/phydm_regconfig8188e.h" +#include "rtl8188e/phydm_rtl8188e.h" +#include "rtl8188e/hal8188ereg.h" +#include "rtl8188e/version_rtl8188e.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188e_hal.h" + #include "rtl8188e/halphyrf_8188e_ce.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8188e/halphyrf_8188e_win.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8188e/halphyrf_8188e_ap.h" +#endif +#endif //88E END + +#if (RTL8192E_SUPPORT==1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ + #endif + +#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK +#include "rtl8192e/version_rtl8192e.h" +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8192e/halhwimg8192e_bb.h" + #include "rtl8192e/halhwimg8192e_mac.h" + #include "rtl8192e/halhwimg8192e_rf.h" + #include "rtl8192e/phydm_regconfig8192e.h" + #include "rtl8192e/halhwimg8192e_fw.h" + #include "rtl8192e/hal8192ereg.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e_hal.h" +#endif +#endif //92E END + +#if (RTL8812A_SUPPORT==1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8812a/halphyrf_8812a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8812a/halphyrf_8812a_ap.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a/halphyrf_8812a_ce.h" + #endif + + //#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8812a/halhwimg8812a_bb.h" + #include "rtl8812a/halhwimg8812a_mac.h" + #include "rtl8812a/halhwimg8812a_rf.h" + #include "rtl8812a/phydm_regconfig8812a.h" + #include "rtl8812a/halhwimg8812a_fw.h" + #include "rtl8812a/phydm_rtl8812a.h" + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a_hal.h" + #endif + #include "rtl8812a/version_rtl8812a.h" + +#endif //8812 END + +#if (RTL8814A_SUPPORT==1) + +#include "rtl8814a/halhwimg8814a_mac.h" +#include "rtl8814a/halhwimg8814a_rf.h" +#include "rtl8814a/halhwimg8814a_bb.h" +#include "rtl8814a/version_rtl8814a.h" +#include "rtl8814a/phydm_rtl8814a.h" +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8814a/halhwimg8814a_fw.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8814a/halphyrf_8814a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a/halphyrf_8814a_ce.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8814a/halphyrf_8814a_ap.h" +#endif + #include "rtl8814a/phydm_regconfig8814a.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a_hal.h" + #include "rtl8814a/phydm_iqk_8814a.h" +#endif +#endif //8814 END + +#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "rtl8821a/phydm_iqk_8821a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8821a/phydm_iqk_8821a_ce.h" +#else +#include "rtl8821a/phydm_iqk_8821a_ap.h" +#endif +//#include "rtl8881a/HalHWImg8881A_BB.h" +//#include "rtl8881a/HalHWImg8881A_MAC.h" +//#include "rtl8881a/HalHWImg8881A_RF.h" +//#include "rtl8881a/odm_RegConfig8881A.h" +#endif + +#if (RTL8723B_SUPPORT==1) +#include "rtl8723b/halhwimg8723b_mac.h" +#include "rtl8723b/halhwimg8723b_rf.h" +#include "rtl8723b/halhwimg8723b_bb.h" +#include "rtl8723b/halhwimg8723b_fw.h" +#include "rtl8723b/phydm_regconfig8723b.h" +#include "rtl8723b/phydm_rtl8723b.h" +#include "rtl8723b/hal8723breg.h" +#include "rtl8723b/version_rtl8723b.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8723b/halphyrf_8723b_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8723b/halphyrf_8723b_ce.h" + #include "rtl8723b/halhwimg8723b_mp.h" + #include "rtl8723b_hal.h" +#else + #include "rtl8723b/halphyrf_8723b_ap.h" +#endif +#endif + +#if (RTL8821A_SUPPORT==1) +#include "rtl8821a/halhwimg8821a_mac.h" +#include "rtl8821a/halhwimg8821a_rf.h" +#include "rtl8821a/halhwimg8821a_bb.h" +#include "rtl8821a/halhwimg8821a_fw.h" +#include "rtl8821a/phydm_regconfig8821a.h" +#include "rtl8821a/phydm_rtl8821a.h" +#include "rtl8821a/version_rtl8821a.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8821a/halphyrf_8821a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8821a/halphyrf_8821a_ce.h" + #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ + #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ + #include "rtl8812a_hal.h" +#else +#endif +#endif + +#if (RTL8822B_SUPPORT==1) +#include "rtl8822b/halhwimg8822b_mac.h" +#include "rtl8822b/halhwimg8822b_rf.h" +#include "rtl8822b/halhwimg8822b_bb.h" +#include "rtl8822b/halhwimg8822b_fw.h" +#include "rtl8822b/phydm_regconfig8822b.h" +#include "rtl8822b/halphyrf_8822b.h" +#include "rtl8822b/phydm_rtl8822b.h" +#include "rtl8822b/phydm_hal_api8822b.h" +#include "rtl8822b/version_rtl8822b.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include /* struct HAL_DATA_TYPE */ +#include /* Rx_Smooth_Factor, reg definition and etc.*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +#endif + +#endif + +#if (RTL8703B_SUPPORT==1) +#include "rtl8703b/phydm_regconfig8703b.h" +#include "rtl8703b/halhwimg8703b_mac.h" +#include "rtl8703b/halhwimg8703b_rf.h" +#include "rtl8703b/halhwimg8703b_bb.h" +#include "rtl8703b/halhwimg8703b_fw.h" +#include "rtl8703b/halphyrf_8703b.h" +#include "rtl8703b/version_rtl8703b.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8703b_hal.h" +#endif +#endif + +#if (RTL8188F_SUPPORT == 1) +#include "rtl8188f/halhwimg8188f_mac.h" +#include "rtl8188f/halhwimg8188f_rf.h" +#include "rtl8188f/halhwimg8188f_bb.h" +#include "rtl8188f/halhwimg8188f_fw.h" +#include "rtl8188f/hal8188freg.h" +#include "rtl8188f/phydm_rtl8188f.h" +#include "rtl8188f/phydm_regconfig8188f.h" +#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ +#include "rtl8188f/version_rtl8188f.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8188f_hal.h" +#endif +#endif + +#if (RTL8723D_SUPPORT==1) + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + + #include "rtl8723d/halhwimg8723d_bb.h" + #include "rtl8723d/halhwimg8723d_mac.h" + #include "rtl8723d/halhwimg8723d_rf.h" + #include "rtl8723d/phydm_regconfig8723d.h" + #include "rtl8723d/halhwimg8723d_fw.h" + #include "rtl8723d/hal8723dreg.h" + #include "rtl8723d/phydm_rtl8723d.h" + #include "rtl8723d/halphyrf_8723d.h" + #include "rtl8723d/version_rtl8723d.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8723d_hal.h" + #endif +#endif //8723D End + +#if (RTL8197F_SUPPORT == 1) +#include "rtl8197f/halhwimg8197f_mac.h" +#include "rtl8197f/halhwimg8197f_rf.h" +#include "rtl8197f/halhwimg8197f_bb.h" +#include "rtl8197f/phydm_hal_api8197f.h" +#include "rtl8197f/version_rtl8197f.h" +#include "rtl8197f/phydm_rtl8197f.h" +#include "rtl8197f/phydm_regconfig8197f.h" +#include "rtl8197f/halphyrf_8197f.h" +#include "rtl8197f/phydm_iqk_8197f.h" +#endif + +#if (RTL8821C_SUPPORT==1) +#include "rtl8821c/phydm_hal_api8821c.h" +#include "rtl8821c/halhwimg8821c_testchip_mac.h" +#include "rtl8821c/halhwimg8821c_testchip_rf.h" +#include "rtl8821c/halhwimg8821c_testchip_bb.h" +#include "rtl8821c/phydm_regconfig8821c.h" +#include "rtl8821c/version_rtl8821c.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8821c_hal.h" +#endif +#endif + +#endif // __ODM_PRECOMP_H__ + diff --git a/package/kernel/rtl8192cd/phydm/phydm_rainfo.c b/package/kernel/rtl8192cd/phydm/phydm_rainfo.c old mode 100755 new mode 100644 index cb666deb303..580f9aa0795 --- a/package/kernel/rtl8192cd/phydm/phydm_rainfo.c +++ b/package/kernel/rtl8192cd/phydm/phydm_rainfo.c @@ -1,3411 +1,3411 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -phydm_h2C_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte H2C_Parameter[H2C_MAX_LENGTH] = {0}; - u1Byte phydm_h2c_id = (u1Byte)dm_value[0]; - u1Byte i; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - PHYDM_SNPRINTF((output+used, out_len-used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); - for (i = 0; i < H2C_MAX_LENGTH; i++) { - - H2C_Parameter[i] = (u1Byte)dm_value[i+1]; - PHYDM_SNPRINTF((output+used, out_len-used, "H2C: Byte[%d] = ((0x%x))\n", i, H2C_Parameter[i])); - } - - ODM_FillH2CCmd(pDM_Odm, phydm_h2c_id, H2C_MAX_LENGTH, H2C_Parameter); - -} - -#if (defined(CONFIG_RA_DBG_CMD)) -VOID -odm_RA_ParaAdjust_Send_H2C( - IN PVOID pDM_VOID -) -{ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte H2C_Parameter[6] = {0}; - - H2C_Parameter[0] = RA_FIRST_MACID; - - if (pRA_Table->RA_Para_feedback_req) { /*H2C_Parameter[5]=1 ; ask FW for all RA parameters*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); - H2C_Parameter[5] |= BIT1; /*ask FW to report RA parameters*/ - H2C_Parameter[1] = pRA_Table->para_idx; /*pRA_Table->para_idx;*/ - pRA_Table->RA_Para_feedback_req = 0; - } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); - - H2C_Parameter[1] = pRA_Table->para_idx; - H2C_Parameter[2] = pRA_Table->rate_idx; - /* [8 bit]*/ - if (pRA_Table->para_idx == RADBG_RTY_PENALTY || pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO || pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - H2C_Parameter[3] = pRA_Table->value; - H2C_Parameter[4] = 0; - } - /* [16 bit]*/ - else { - H2C_Parameter[3] = (u1Byte)(((pRA_Table->value_16) & 0xf0) >> 4); /*byte1*/ - H2C_Parameter[4] = (u1Byte)((pRA_Table->value_16) & 0x0f); /*byte0*/ - } - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[1] = 0x%x\n", H2C_Parameter[1])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[2] = 0x%x\n", H2C_Parameter[2])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[3] = 0x%x\n", H2C_Parameter[3])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[4] = 0x%x\n", H2C_Parameter[4])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[5] = 0x%x\n", H2C_Parameter[5])); - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RA_PARA_ADJUST, 6, H2C_Parameter); - -} - - -VOID -odm_RA_ParaAdjust( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte rate_idx = pRA_Table->rate_idx; - u1Byte value = pRA_Table->value; - u1Byte Pre_value = 0xff; - - if (pRA_Table->para_idx == RADBG_RTY_PENALTY) { - Pre_value = pRA_Table->RTY_P[rate_idx]; - pRA_Table->RTY_P[rate_idx] = value; - pRA_Table->RTY_P_modify_note[rate_idx] = 1; - } else if (pRA_Table->para_idx == RADBG_N_HIGH) { - - } else if (pRA_Table->para_idx == RADBG_N_LOW) { - - } else if (pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO) { - Pre_value = pRA_Table->RATE_UP_RTY_RATIO[rate_idx]; - pRA_Table->RATE_UP_RTY_RATIO[rate_idx] = value; - pRA_Table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; - } else if (pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - Pre_value = pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx]; - pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx] = value; - pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], Rate[ %d ], ((%d)) -> ((%d))\n", pRA_Table->para_idx, rate_idx, Pre_value, value)); - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); -} - -VOID -phydm_ra_print_msg( - IN PVOID pDM_VOID, - IN u1Byte *value, - IN u1Byte *value_default, - IN u1Byte *modify_note -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u4Byte i; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate index| |Current-value| |Default-value| |Modify?|\n")); - for (i = 0 ; i <= (pRA_Table->rate_length); i++) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#endif - } - -} - -VOID -odm_RA_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - pRA_Table->is_ra_dbg_init = FALSE; - - if (dm_value[0] == 100) { /*1 Print RA Parameters*/ - u1Byte default_pointer_value; - u1Byte *pvalue; - u1Byte *pvalue_default; - u1Byte *pmodify_note; - - pvalue = pvalue_default = pmodify_note = &default_pointer_value; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); - - if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); - pvalue = &(pRA_Table->RTY_P[0]); - pvalue_default = &(pRA_Table->RTY_P_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RTY_P_modify_note[0]); - } else if (dm_value[1] == RADBG_N_HIGH) { /* [2]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); - - } else if (dm_value[1] == RADBG_N_LOW) { /*[3]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); - - } else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); - pvalue = &(pRA_Table->RATE_UP_RTY_RATIO[0]); - pvalue_default = &(pRA_Table->RATE_UP_RTY_RATIO_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RATE_UP_RTY_RATIO_modify_note[0]); - } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); - pvalue = &(pRA_Table->RATE_DOWN_RTY_RATIO[0]); - pvalue_default = &(pRA_Table->RATE_DOWN_RTY_RATIO_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[0]); - } - - phydm_ra_print_msg(pDM_Odm, pvalue, pvalue_default, pmodify_note); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); - - } else if (dm_value[0] == 101) { - pRA_Table->para_idx = (u1Byte)dm_value[1]; - - pRA_Table->RA_Para_feedback_req = 1; - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); - } else { - pRA_Table->para_idx = (u1Byte)dm_value[0]; - pRA_Table->rate_idx = (u1Byte)dm_value[1]; - pRA_Table->value = (u1Byte)dm_value[2]; - - odm_RA_ParaAdjust(pDM_Odm); - } -} - -VOID -odm_RA_ParaAdjust_init( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte i; - u1Byte ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; - u1Byte RateSize_HT_1ss = 20, RateSize_HT_2ss = 28, RateSize_HT_3ss = 36; /*4+8+8+8+8 =36*/ - u1Byte RateSize_VHT_1ss = 10, RateSize_VHT_2ss = 20, RateSize_VHT_3ss = 30; /*10 + 10 +10 =30*/ - /* - RTY_PENALTY = 1, //u8 - N_HIGH = 2, - N_LOW = 3, - RATE_UP_TABLE = 4, - RATE_DOWN_TABLE = 5, - TRYING_NECESSARY = 6, - DROPING_NECESSARY = 7, - RATE_UP_RTY_RATIO = 8, //u8 - RATE_DOWN_RTY_RATIO= 9, //u8 - ALL_PARA = 0xff - - */ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_RA_ParaAdjust_init\n")); - - if (pDM_Odm->SupportICType & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D)) - pRA_Table->rate_length = RateSize_HT_1ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) - pRA_Table->rate_length = RateSize_HT_2ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) - pRA_Table->rate_length = RateSize_HT_1ss + RateSize_VHT_1ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8822B)) - pRA_Table->rate_length = RateSize_HT_2ss + RateSize_VHT_2ss; - else if (pDM_Odm->SupportICType == ODM_RTL8814A) - pRA_Table->rate_length = RateSize_HT_3ss + RateSize_VHT_3ss; - else - pRA_Table->rate_length = RateSize_HT_1ss; - - pRA_Table->is_ra_dbg_init = TRUE; - for (i = 0; i < 3; i++) { - pRA_Table->RA_Para_feedback_req = 1; - pRA_Table->para_idx = ra_para_pool_u8[i]; - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); - } -} - -#else - -VOID -phydm_RA_debug_PCR( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output+used, out_len-used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); - /**/ - } else if (dm_value[0] == 0) { - pRA_Table->RA_offset_direction = 0; - pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", pRA_Table->RA_threshold_offset)); - } else if (dm_value[0] == 1) { - pRA_Table->RA_offset_direction = 1; - pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", pRA_Table->RA_threshold_offset)); - } else { - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] Error\n")); - /**/ - } - -} - -#endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ - -VOID -ODM_C2HRaParaReportHandler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - u1Byte para_idx = CmdBuf[0]; /*Retry Penalty, NH, NL*/ - u1Byte RateTypeStart = CmdBuf[1]; - u1Byte RateTypeLength = CmdLen - 2; - u1Byte i; - - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] CmdBuf[0]= (( %d ))\n", CmdBuf[0])); - -#if (defined(CONFIG_RA_DBG_CMD)) - if (para_idx == RADBG_RTY_PENALTY) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |RTY Penality Index|\n")); - - for (i = 0 ; i < (RateTypeLength) ; i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RTY_P_default[RateTypeStart + i] = CmdBuf[2 + i]; - - pRA_Table->RTY_P[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RTY_P[RateTypeStart + i])); - } - - } else if (para_idx == RADBG_N_HIGH) { - /**/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-High|\n")); - - - } else if (para_idx == RADBG_N_LOW) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-Low|\n")); - /**/ - } - else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Up RTY Ratio|\n")); - - for (i = 0; i < (RateTypeLength); i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RATE_UP_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; - - pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i])); - } - } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Down RTY Ratio|\n")); - - for (i = 0; i < (RateTypeLength); i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RATE_DOWN_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; - - pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i])); - } - } else -#endif - if (para_idx == RADBG_DEBUG_MONITOR1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { - - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Rate =", CmdBuf[2] & 0x7f)); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (CmdBuf[2] & 0x80) >> 7)); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", CmdBuf[5])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[7])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[8])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", CmdBuf[9])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", CmdBuf[10])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", CmdBuf[11])); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest Rate =", CmdBuf[5])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest Rate =", CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", CmdBuf[7])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", CmdBuf[8]));; - } - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RateID =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", CmdBuf[3])); - - for (i = 4; i <= 11; i++) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", CmdBuf[i])); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", - CmdBuf[8], CmdBuf[7], CmdBuf[6], CmdBuf[5], CmdBuf[4], CmdBuf[3], CmdBuf[2], CmdBuf[1])); - } - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR3) { - - for (i = 0; i < (CmdLen - 1); i++) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, CmdBuf[1 + i])); - } else if (para_idx == RADBG_DEBUG_MONITOR4) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA Version =", CmdBuf[1], CmdBuf[2])); - else if (para_idx == RADBG_DEBUG_MONITOR5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate down ratio =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", CmdBuf[5], CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", CmdBuf[11], CmdBuf[10], CmdBuf[9], CmdBuf[8], CmdBuf[7])); - } -} - -VOID -phydm_ra_dynamic_retry_count( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - PSTA_INFO_T pEntry; - u1Byte i, retry_offset; - u4Byte ma_rx_tp; - - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)) { - return; - } - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pDM_Odm->pre_b_noisy = %d\n", pDM_Odm->pre_b_noisy ));*/ - if (pDM_Odm->pre_b_noisy != pDM_Odm->NoisyDecision) { - - if (pDM_Odm->NoisyDecision) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); - ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x0); - ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x04030201); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); - ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x01000000); - ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x06050402); - } - pDM_Odm->pre_b_noisy = pDM_Odm->NoisyDecision; - } -} - -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - -VOID -phydm_retry_limit_table_bound( - IN PVOID pDM_VOID, - IN u1Byte *retry_limit, - IN u1Byte offset -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - if (*retry_limit > offset) { - - *retry_limit -= offset; - - if (*retry_limit < pRA_Table->retrylimit_low) - *retry_limit = pRA_Table->retrylimit_low; - else if (*retry_limit > pRA_Table->retrylimit_high) - *retry_limit = pRA_Table->retrylimit_high; - } else - *retry_limit = pRA_Table->retrylimit_low; -} - -VOID -phydm_reset_retry_limit_table( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte i; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ - - #else - #if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) - u1Byte per_rate_retrylimit_table_20M[ODM_RATEMCS15+1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ - 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ - }; - u1Byte per_rate_retrylimit_table_40M[ODM_RATEMCS15+1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ - 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ - }; - - #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) - - #elif (RTL8812A_SUPPORT == 1) - - #elif(RTL8814A_SUPPORT == 1) - - #else - - #endif - #endif - - memcpy(&(pRA_Table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); - memcpy(&(pRA_Table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); - - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), 0); - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), 0); - } -} - -VOID -phydm_ra_dynamic_retry_limit_init( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - pRA_Table->retry_descend_num = RA_RETRY_DESCEND_NUM; - pRA_Table->retrylimit_low = RA_RETRY_LIMIT_LOW; - pRA_Table->retrylimit_high = RA_RETRY_LIMIT_HIGH; - - phydm_reset_retry_limit_table(pDM_Odm); - -} - -#endif - -VOID -phydm_ra_dynamic_retry_limit( - IN PVOID pDM_VOID -) -{ -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - PSTA_INFO_T pEntry; - u1Byte i, retry_offset; - u4Byte ma_rx_tp; - - - if (pDM_Odm->pre_number_active_client == pDM_Odm->number_active_client) { - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); - return; - - } else { - if (pDM_Odm->number_active_client == 1) { - phydm_reset_retry_limit_table(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); - } else { - - retry_offset = pDM_Odm->number_active_client * pRA_Table->retry_descend_num; - - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), retry_offset); - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), retry_offset); - } - } - } -#endif -} - -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) -VOID -phydm_ra_dynamic_rate_id_on_assoc( - IN PVOID pDM_VOID, - IN u1Byte wireless_mode, - IN u1Byte init_rate_id -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", pDM_Odm->RFType, wireless_mode, init_rate_id)); - - if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { - - if ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) && - (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) - ){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); - ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - } else if ((pDM_Odm->SupportICType & (ODM_RTL8812)) && - (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) - ){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); - ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ - } - } - -} - -VOID -phydm_ra_dynamic_rate_id_init( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) { - - ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - - ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ - } -} - -VOID -phydm_update_rate_id( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u1Byte platform_macid -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte current_tx_ss; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte wireless_mode; - u1Byte phydm_macid; - PSTA_INFO_T pEntry; - - -#if 0 - if (rate_idx >= ODM_RATEVHTSS2MCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS2MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS1MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEMCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEMCS0))); - /*dummy for SD4 check patch*/ - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); - /*dummy for SD4 check patch*/ - } -#endif - - phydm_macid = pDM_Odm->platform2phydm_macid_table[platform_macid]; - pEntry = pDM_Odm->pODM_StaInfo[phydm_macid]; - - if (IS_STA_VALID(pEntry)) { - wireless_mode = pEntry->WirelessMode; - - if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { - - pEntry->ratr_idx = pEntry->ratr_idx_init; - if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ - if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ - - pEntry->ratr_idx = ARFR_5_RATE_ID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); - } - } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ - if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ - - pEntry->ratr_idx = ARFR_0_RATE_ID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, pEntry->ratr_idx)); - } - } - -} -#endif - -VOID -phydm_print_rate( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u4Byte dbg_component -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; - u1Byte b_sgi = (rate & 0x80)>>7; - - ODM_RT_TRACE_F(pDM_Odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", - ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", - ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", - ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", - (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", - (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0)%10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M)?legacy_table[rate_idx]:0)), - (b_sgi) ? "-S" : " ", - (rate_idx >= ODM_RATEMCS0) ? "" : "M")); -} - -VOID -phydm_c2h_ra_report_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte legacy_table[12] = {1,2,5,11,6,9,12,18,24,36,48,54}; - u1Byte isMU_RPT=0; - u1Byte macid = CmdBuf[1]; - u1Byte rate = CmdBuf[0]; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte pre_rate = pRA_Table->link_tx_rate[macid]; - u1Byte rate_order; - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - GET_HAL_DATA(Adapter)->CurrentRARate = HwRateToMRate(rate_idx); - #endif - - - if (CmdLen >= 4) { - if (CmdBuf[3] == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-Rate Update[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate Back[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); - /**/ - } else if (CmdBuf[3] == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); - /**/ - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx Rate Update[%d]:", macid)); - /**/ - } - - /*phydm_print_rate(pDM_Odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ - phydm_print_rate(pDM_Odm, rate, ODM_COMP_RATE_ADAPTIVE); - if (macid >= 128) { - u1Byte gid_index = macid - 128; - pRA_Table->mu1_rate[gid_index] = rate; - } - pre_rate = pRA_Table->link_tx_rate[macid]; - pRA_Table->link_tx_rate[macid] = rate; - - /*trigger power training*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - - rate_order = phydm_rate_order_compute(pDM_Odm, rate_idx); - - if ((pDM_Odm->bOneEntryOnly) || - ((rate_order > pRA_Table->highest_client_tx_order) && (pRA_Table->power_tracking_flag == 1)) - ) { - phydm_update_pwr_track(pDM_Odm, rate_idx); - pRA_Table->power_tracking_flag = 0; - } - - #endif - - /*trigger dynamic rate ID*/ - #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) - phydm_update_rate_id(pDM_Odm, rate, macid); - #endif - -} - -VOID -odm_RSSIMonitorInit( - IN PVOID pDM_VOID -) -{ -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pRA_Table->PT_collision_pre = TRUE; /*used in ODM_DynamicARFBSelect(WIN only)*/ - - pHalData->UndecoratedSmoothedPWDB = -1; - pHalData->ra_rpt_linked = FALSE; - #endif - - pRA_Table->firstconnect = FALSE; - - -#endif -} - -VOID -ODM_RAPostActionOnAssoc( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -/* - pDM_Odm->H2C_RARpt_connect = 1; - odm_RSSIMonitorCheck(pDM_Odm); - pDM_Odm->H2C_RARpt_connect = 0; -*/ -} - -VOID -phydm_initRaInfo( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - u4Byte ret_value; - - ret_value = ODM_GetBBReg(pDM_Odm, 0x4c8, bMaskByte2); - ODM_SetBBReg(pDM_Odm, 0x4cc, bMaskByte3, (ret_value - 1)); - } -#endif -} - -VOID -phydm_modify_RA_PCR_threshold( - IN PVOID pDM_VOID, - IN u1Byte RA_offset_direction, - IN u1Byte RA_threshold_offset - -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - pRA_Table->RA_offset_direction = RA_offset_direction; - pRA_Table->RA_threshold_offset = RA_threshold_offset; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); -} - -VOID -odm_RSSIMonitorCheckMP( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; - u4Byte i; - BOOLEAN bExtRAInfo = TRUE; - u1Byte cmdlen = H2C_0X42_LENGTH; - u1Byte TxBF_EN = 0, stbc_en = 0; - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PSTA_INFO_T pEntry = NULL; - s4Byte tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PMGNT_INFO pDefaultMgntInfo = &Adapter->MgntInfo; - u8Byte curTxOkCnt = 0, curRxOkCnt = 0; -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE; -#endif -#endif - PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); - - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - bExtRAInfo = FALSE; - cmdlen = 3; - } - - while (pLoopAdapter) { - - if (pLoopAdapter != NULL) { - pMgntInfo = &pLoopAdapter->MgntInfo; - curTxOkCnt = pLoopAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; - curRxOkCnt = pLoopAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; - pMgntInfo->lastTxOkCnt = curTxOkCnt; - pMgntInfo->lastRxOkCnt = curRxOkCnt; - } - - for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { - - if (IsAPModeExist(pLoopAdapter)) { - if (GetFirstExtAdapter(pLoopAdapter) != NULL && - GetFirstExtAdapter(pLoopAdapter) == pLoopAdapter) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); - else if (GetFirstGOPort(pLoopAdapter) != NULL && - IsFirstGoAdapter(pLoopAdapter)) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); - } else { - if (GetDefaultAdapter(pLoopAdapter) == pLoopAdapter) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); - } - - if (pEntry != NULL) { - if (pEntry->bAssociated) { - - RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); - RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", - pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - //2 BF_en -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->AssociatedMacId); - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; -#else - if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), pEntry)) - TxBF_EN = 1; -#endif -#endif - //2 STBC_en - if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) - tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) - tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - - H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")),pRA_Table->RA_threshold_offset)); - - if (bExtRAInfo) { - if (curRxOkCnt > (curTxOkCnt * 6)) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; - - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; - } - - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); - #if 1 - if (pDM_Odm->H2C_RARpt_connect) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); - } - #else - - if (pEntry->rssi_stat.ra_rpt_linked == FALSE) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pEntry->rssi_stat.ra_rpt_linked = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", - pEntry->AssociatedMacId, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - } - #endif - } - - H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF); - //H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 - H2C_Parameter[0] = (pEntry->AssociatedMacId); - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); - } - } else - break; - } - - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - } - - - /*Default port*/ - if (tmpEntryMaxPWDB != 0) { // If associated entry is found - pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; - RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmpEntryMaxPWDB, tmpEntryMaxPWDB)); - } else - pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; - - if (tmpEntryMinPWDB != 0xff) { // If associated entry is found - pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; - RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB)); - - } else - pHalData->EntryMinUndecoratedSmoothedPWDB = 0; - - /* Default porti sent RSSI to FW */ - if (pHalData->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - if (pHalData->UndecoratedSmoothedPWDB > 0) { - - PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pDefaultMgntInfo); - PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pDefaultMgntInfo); - - /* BF_en*/ - #if (BEAMFORMING_SUPPORT == 1) - #ifndef BEAMFORMING_VERSION_1 - Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pDefaultMgntInfo->mMacId); - - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; - #else - if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), NULL)) - TxBF_EN = 1; - #endif - #endif - - /* STBC_en*/ - if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); - - if (bExtRAInfo) { - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; - } - - #if 1 - if (pDM_Odm->H2C_RARpt_connect) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); - } - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - - if (pHalData->ra_rpt_linked == FALSE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pHalData->ra_rpt_linked = TRUE; - - - } - #endif - - if (pDM_Odm->NoisyDecision == 1) { - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); - } else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] H2C_Parameter=%x\n", H2C_Parameter[3])); - } - - H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); - /*H2C_Parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - H2C_Parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); - } - - // BT 3.0 HS mode Rssi - if (pDM_Odm->bBtHsOperation) { - H2C_Parameter[2] = pDM_Odm->btHsRssi; - //H2C_Parameter[1] = 0x0; - H2C_Parameter[0] = WIN_BT_PORT_MACID; - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); - } - } else - PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); - - if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8192E)) - odm_RSSIDumpToRegister(pDM_Odm); - - - { - PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); - BOOLEAN default_pointer_value, *pbLink_temp = &default_pointer_value; - s4Byte GlobalRSSI_min = 0xFF, LocalRSSI_Min; - BOOLEAN bLink = FALSE; - - while (pLoopAdapter) { - LocalRSSI_Min = phydm_FindMinimumRSSI(pDM_Odm, pLoopAdapter, pbLink_temp); - //DbgPrint("pHalData->bLinked=%d, LocalRSSI_Min=%d\n", pHalData->bLinked, LocalRSSI_Min); - - if (*pbLink_temp) - bLink = TRUE; - - if ((LocalRSSI_Min < GlobalRSSI_min) && (*pbLink_temp)) - GlobalRSSI_min = LocalRSSI_Min; - - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - } - - pHalData->bLinked = bLink; - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc , ODM_CMNINFO_LINK, (u8Byte)bLink); - - if (bLink) - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u8Byte)GlobalRSSI_min); - else - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); - - } - -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/*H2C_RSSI_REPORT*/ -s8 phydm_rssi_report(PDM_ODM_T pDM_Odm, u8 mac_id) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 H2C_Parameter[4] = {0}; - u8 UL_DL_STATE = 0, STBC_TX = 0, TxBF_EN = 0; - u8 cmdlen = 4, first_connect = _FALSE; - u64 curTxOkCnt = 0, curRxOkCnt = 0; - PSTA_INFO_T pEntry = pDM_Odm->pODM_StaInfo[mac_id]; - - if (!IS_STA_VALID(pEntry)) - return _FAIL; - - if (mac_id != pEntry->mac_id) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, pEntry->mac_id)); - rtw_warn_on(1); - return _FAIL; - } - - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ - return _FAIL; - - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, pEntry->mac_id, MAC_ARG(pEntry->hwaddr))); - return _FAIL; - } - - curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes; - curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes; - if (curRxOkCnt > (curTxOkCnt * 6)) - UL_DL_STATE = 1; - else - UL_DL_STATE = 0; - - #ifdef CONFIG_BEAMFORMING - { - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->mac_id); - #else/*for drv beamforming*/ - BEAMFORMING_CAP Beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&Adapter->mlmepriv, pEntry->mac_id); - #endif - - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; - else - TxBF_EN = 0; - } - #endif /*#ifdef CONFIG_BEAMFORMING*/ - - if (TxBF_EN) - STBC_TX = 0; - else { - #ifdef CONFIG_80211AC_VHT - if (IsSupportedVHT(pEntry->wireless_mode)) - STBC_TX = TEST_FLAG(pEntry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); - else - #endif - STBC_TX = TEST_FLAG(pEntry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); - } - - H2C_Parameter[0] = (u8)(pEntry->mac_id & 0xFF); - H2C_Parameter[2] = pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F; - - if (UL_DL_STATE) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; - - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; - if (STBC_TX) - H2C_Parameter[3] |= RAINFO_STBC_STATE; - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - - if ((pEntry->ra_rpt_linked == _FALSE) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_SEND)) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pEntry->ra_rpt_linked = _TRUE; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_HOLD; - first_connect = _TRUE; - } - - #if 1 - if (first_connect) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, - pEntry->mac_id, MAC_ARG(pEntry->hwaddr), pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, - (UL_DL_STATE) ? "DL" : "UL", (TxBF_EN) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", - (pDM_Odm->NoisyDecision) ? "True" : "False", (first_connect) ? "True" : "False")); - } - #endif - - if (pHalData->fw_ractrl == _TRUE) { - #if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - cmdlen = 3; - #endif - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); - } else { - #if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ODM_RA_SetRSSI_8188E(pDM_Odm, (u8)(pEntry->mac_id & 0xFF), pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F); - #endif - } - return _SUCCESS; -} - -void phydm_ra_rssi_rpt_wk_hdl(PVOID pContext) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; - int i; - u8 mac_id = 0xFF; - PSTA_INFO_T pEntry = NULL; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) { - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; - if (pEntry->ra_rpt_linked == _FALSE) { - mac_id = i; - break; - } - } - } - if (mac_id != 0xFF) - phydm_rssi_report(pDM_Odm, mac_id); -} -void phydm_ra_rssi_rpt_wk(PVOID pContext) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; - - rtw_run_in_thread_cmd(pDM_Odm->Adapter, phydm_ra_rssi_rpt_wk_hdl, pDM_Odm); -} -#endif - -VOID -odm_RSSIMonitorCheckCE( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PSTA_INFO_T pEntry; - int i; - int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; - u8 sta_cnt = 0; - - if (pDM_Odm->bLinked != _TRUE) - return; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) { - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; - - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) - continue; - - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) - tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) - tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - - if (phydm_rssi_report(pDM_Odm, i)) - sta_cnt++; - } - } - - if (tmpEntryMaxPWDB != 0) // If associated entry is found - pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; - else - pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; - - if (tmpEntryMinPWDB != 0xff) // If associated entry is found - pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; - else - pHalData->EntryMinUndecoratedSmoothedPWDB = 0; - - FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM - - pDM_Odm->RSSI_Min = pHalData->MinUndecoratedPWDBForDM; - //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); -#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) -} - - -VOID -odm_RSSIMonitorCheckAP( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; - u4Byte i; - BOOLEAN bExtRAInfo = TRUE; - u1Byte cmdlen = H2C_0X42_LENGTH; - u1Byte TxBF_EN = 0, stbc_en = 0; - - prtl8192cd_priv priv = pDM_Odm->priv; - PSTA_INFO_T pstat; - BOOLEAN act_bfer = FALSE; - -#if (BEAMFORMING_SUPPORT == 1) - u1Byte Idx=0xff; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - pDM_BdcTable->num_Txbfee_Client = 0; - pDM_BdcTable->num_Txbfer_Client = 0; -#endif -#endif - if (!pDM_Odm->H2C_RARpt_connect && (priv->up_time % 2)) - return; - - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - bExtRAInfo = FALSE; - cmdlen = 3; - } - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pstat = pDM_Odm->pODM_StaInfo[i]; - - if (IS_STA_VALID(pstat)) { - if (pstat->sta_in_firmware != 1) - continue; - - //2 BF_en - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP Beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); - PRT_BEAMFORMING_ENTRY pEntry = Beamforming_GetEntryByMacId(priv, pstat->aid, &Idx); - - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - - if (pEntry->Sounding_En) - TxBF_EN = 1; - else - TxBF_EN = 0; - - act_bfer = TRUE; - } - - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ - if (act_bfer == TRUE) { - pDM_BdcTable->w_BFee_Client[i] = 1; //AP act as BFer - pDM_BdcTable->num_Txbfee_Client++; - } else { - pDM_BdcTable->w_BFee_Client[i] = 0; //AP act as BFer - } - - if ((Beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (Beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { - pDM_BdcTable->w_BFer_Client[i] = 1; //AP act as BFee - pDM_BdcTable->num_Txbfer_Client++; - } else { - pDM_BdcTable->w_BFer_Client[i] = 0; //AP act as BFer - } - #endif - #endif - - //2 STBC_en - if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && - ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) - #ifdef RTK_AC_SUPPORT - || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) - #endif - )) - stbc_en = 1; - - //2 RAINFO - - if (bExtRAInfo) { - if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; - - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; - } - - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); - - if (pstat->H2C_rssi_rpt) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); - } - - /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",H2C_Parameter[3]));*/ - } - - H2C_Parameter[2] = (u1Byte)(pstat->rssi & 0xFF); - H2C_Parameter[0] = REMAP_AID(pstat); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("H2C_Parameter[3]=%d\n", H2C_Parameter[3])); - - //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x, \n",H2C_Parameter[2])); - //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x, \n",H2C_Parameter[0])); - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); - - } - } - -#endif -#endif - -} - -VOID -odm_RSSIMonitorCheck( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) - return; - - switch (pDM_Odm->SupportPlatform) { - case ODM_WIN: - odm_RSSIMonitorCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_RSSIMonitorCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_RSSIMonitorCheckAP(pDM_Odm); - break; - - default: - break; - } - -} - -VOID -odm_RateAdaptiveMaskInit( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - - pMgntInfo->Ratr_State = DM_RATR_STA_INIT; - - if (pMgntInfo->DM_Type == DM_Type_ByDriver) - pHalData->bUseRAMask = TRUE; - else - pHalData->bUseRAMask = FALSE; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pOdmRA->Type = DM_Type_ByDriver; - if (pOdmRA->Type == DM_Type_ByDriver) - pDM_Odm->bUseRAMask = _TRUE; - else - pDM_Odm->bUseRAMask = _FALSE; -#endif - - pOdmRA->RATRState = DM_RATR_STA_INIT; - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8812) - pOdmRA->LdpcThres = 50; - else - pOdmRA->LdpcThres = 35; - - pOdmRA->RtsThres = 35; - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - pOdmRA->LdpcThres = 35; - pOdmRA->bUseLdpc = FALSE; - -#else - pOdmRA->UltraLowRSSIThresh = 9; - -#endif - - pOdmRA->HighRSSIThresh = 50; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pOdmRA->LowRSSIThresh = 23; -#else - pOdmRA->LowRSSIThresh = 20; -#endif -} -/*----------------------------------------------------------------------------- - * Function: odm_RefreshRateAdaptiveMask() - * - * Overview: Update rate table mask according to rssi - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 05/27/2009 hpfan Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -odm_RefreshRateAdaptiveMask( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!pDM_Odm->bLinked) - return; - - if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n")); - return; - } - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) { - case ODM_WIN: - odm_RefreshRateAdaptiveMaskMP(pDM_Odm); - break; - - case ODM_CE: - odm_RefreshRateAdaptiveMaskCE(pDM_Odm); - break; - - case ODM_AP: - odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); - break; - } - -} - -u1Byte -phydm_trans_platform_bw( - IN PVOID pDM_VOID, - IN u1Byte BW -) -{ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (BW == HT_CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == HT_CHANNEL_WIDTH_20_40) - BW = PHYDM_BW_40; - - else if (BW == HT_CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == HT_CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == HT_CHANNEL_WIDTH_10) - BW = PHYDM_BW_10; - - else if (BW == HT_CHANNEL_WIDTH_5) - BW = PHYDM_BW_5; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - #endif - - return BW; - -} - -u1Byte -phydm_trans_platform_rf_type( - IN PVOID pDM_VOID, - IN u1Byte RfType -) -{ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (RfType == RF_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == RF_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == RF_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == RF_2T2R_GREEN) - RfType = PHYDM_RF_2T2R_GREEN; - - else if (RfType == RF_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == RF_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == RF_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_3T4R) - RfType = PHYDM_RF_3T4R; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (RfType == MIMO_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == MIMO_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == MIMO_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == MIMO_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == MIMO_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == MIMO_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == MIMO_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == MIMO_3T4R) - RfType = PHYDM_RF_3T4R; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (RfType == RF_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == RF_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == RF_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == RF_2T2R_GREEN) - RfType = PHYDM_RF_2T2R_GREEN; - - else if (RfType == RF_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == RF_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == RF_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_3T4R) - RfType = PHYDM_RF_3T4R; - - #endif - - return RfType; - -} - -u4Byte -phydm_trans_platform_wireless_mode( - IN PVOID pDM_VOID, - IN u4Byte wireless_mode -) -{ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (wireless_mode == WIRELESS_11A) - wireless_mode = PHYDM_WIRELESS_MODE_A; - - else if (wireless_mode == WIRELESS_11B) - wireless_mode = PHYDM_WIRELESS_MODE_B; - - else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) - wireless_mode = PHYDM_WIRELESS_MODE_G; - - else if (wireless_mode == WIRELESS_AUTO) - wireless_mode = PHYDM_WIRELESS_MODE_AUTO; - - else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || - (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) - wireless_mode = PHYDM_WIRELESS_MODE_N_24G; - - else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) - wireless_mode = PHYDM_WIRELESS_MODE_N_5G; - - else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) - wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; - - else if (wireless_mode == WIRELESS_11_24AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; - - else if (wireless_mode == WIRELESS_11AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; - - else if (wireless_mode == WIRELESS_MODE_MAX) - wireless_mode = PHYDM_WIRELESS_MODE_MAX; - else - wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; - #endif - - return wireless_mode; - -} - -u1Byte -phydm_vht_en_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte vht_en_out = 0; - - if ((WirelessMode == PHYDM_WIRELESS_MODE_AC_5G) || - (WirelessMode == PHYDM_WIRELESS_MODE_AC_24G) || - (WirelessMode == PHYDM_WIRELESS_MODE_AC_ONLY) - ) { - vht_en_out = 1; - /**/ - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("WirelessMode= (( 0x%x )), VHT_EN= (( %d ))\n", WirelessMode, vht_en_out)); - return vht_en_out; -} - -u1Byte -phydm_rate_id_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode, - IN u1Byte RfType, - IN u1Byte bw -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_id_idx = 0; - u1Byte phydm_BW; - u1Byte phydm_RfType; - - phydm_BW = phydm_trans_platform_bw(pDM_Odm, bw); - phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - WirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, WirelessMode); - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x ))\n", - WirelessMode, phydm_RfType, phydm_BW)); - - - switch (WirelessMode) { - - case PHYDM_WIRELESS_MODE_N_24G: - { - - if (phydm_BW == PHYDM_BW_40) { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_40M_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_BGN_40M_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - - } else { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_20M_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_BGN_20M_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } - } - break; - - case PHYDM_WIRELESS_MODE_N_5G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_GN_N1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_GN_N2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } - - break; - - case PHYDM_WIRELESS_MODE_G: - rate_id_idx = PHYDM_BG; - break; - - case PHYDM_WIRELESS_MODE_A: - rate_id_idx = PHYDM_G; - break; - - case PHYDM_WIRELESS_MODE_B: - rate_id_idx = PHYDM_B_20M; - break; - - - case PHYDM_WIRELESS_MODE_AC_5G: - case PHYDM_WIRELESS_MODE_AC_ONLY: - { - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR0_AC_2SS; - else - rate_id_idx = PHYDM_ARFR4_AC_3SS; - } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_BW >= PHYDM_BW_80) { - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR0_AC_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } else { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; - else - rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; - } - } - break; - - default: - rate_id_idx = 0; - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA Rate ID = (( 0x%d ))\n", rate_id_idx)); - - return rate_id_idx; -} - -VOID -phydm_UpdateHalRAMask( - IN PVOID pDM_VOID, - IN u4Byte wirelessMode, - IN u1Byte RfType, - IN u1Byte BW, - IN u1Byte MimoPs_enable, - IN u1Byte disable_cck_rate, - IN u4Byte *ratr_bitmap_msb_in, - IN u4Byte *ratr_bitmap_lsb_in, - IN u1Byte tx_rate_level - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte mask_rate_threshold; - u1Byte phydm_RfType; - u1Byte phydm_BW; - u4Byte ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; - /*PODM_RATE_ADAPTIVE pRA = &(pDM_Odm->RateAdaptive);*/ - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, wirelessMode); - #endif - - phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); - phydm_BW = phydm_trans_platform_bw(pDM_Odm, BW); - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_RfType = (( %x )), RfType = (( %x ))\n", phydm_RfType, RfType));*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); - - if (MimoPs_enable) - phydm_RfType = PHYDM_RF_1T1R; - - switch (wirelessMode) { - - case PHYDM_WIRELESS_MODE_B: - { - ratr_bitmap &= 0x0000000f; - } - break; - - case PHYDM_WIRELESS_MODE_G: - { - ratr_bitmap &= 0x00000ff5; - } - break; - - case PHYDM_WIRELESS_MODE_A: - { - ratr_bitmap &= 0x00000ff0; - } - break; - - case PHYDM_WIRELESS_MODE_N_24G: - case PHYDM_WIRELESS_MODE_N_5G: - { - if (phydm_RfType == PHYDM_RF_1T1R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x000ff015; - else - ratr_bitmap &= 0x000ff005; - } else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x0ffff015; - else - ratr_bitmap &= 0x0ffff005; - } else { /*3T*/ - - ratr_bitmap &= 0xfffff015; - ratr_bitmap_msb &= 0xf; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff015; - else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff015; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_5G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff010; - else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff010; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - default: - break; - } - - if (wirelessMode != PHYDM_WIRELESS_MODE_B) { - - if (tx_rate_level == 0) - ratr_bitmap &= 0xffffffff; - else if (tx_rate_level == 1) - ratr_bitmap &= 0xfffffff0; - else if (tx_rate_level == 2) - ratr_bitmap &= 0xffffefe0; - else if (tx_rate_level == 3) - ratr_bitmap &= 0xffffcfc0; - else if (tx_rate_level == 4) - ratr_bitmap &= 0xffff8f80; - else if (tx_rate_level >= 5) - ratr_bitmap &= 0xffff0f00; - - } - - if (disable_cck_rate) - ratr_bitmap &= 0xfffffff0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%d ))\n", - wirelessMode, phydm_RfType, phydm_BW, MimoPs_enable, tx_rate_level)); - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ - - *ratr_bitmap_lsb_in = ratr_bitmap; - *ratr_bitmap_msb_in = ratr_bitmap_msb; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); - -} - -u1Byte -phydm_RA_level_decision( - IN PVOID pDM_VOID, - IN u4Byte rssi, - IN u1Byte Ratr_State - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ra_lowest_rate; - u1Byte ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ - u1Byte new_Ratr_State = 0; - u1Byte i; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", Ratr_State, - ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (i >= (Ratr_State)) - ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", - rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (rssi < ra_rate_floor_table[i]) { - new_Ratr_State = i; - break; - } - } - - - - return new_Ratr_State; - -} - -VOID -odm_RefreshRateAdaptiveMaskMP( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PADAPTER pTargetAdapter = NULL; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - - if (pAdapter->bDriverStopped) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); - return; - } - - if (!pHalData->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); - return; - } - - // if default port is connected, update RA table for default port (infrastructure mode only) - if (pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter))) { - odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pMgntInfo->mMacId, pMgntInfo->IOTPeer, pHalData->UndecoratedSmoothedPWDB); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture Mode\n"));*/ - - #if RA_MASK_PHYDMLIZE_WIN - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State); - - if (pMgntInfo->Ratr_State != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", - pMgntInfo->Ratr_State, Ratr_State_new, pHalData->UndecoratedSmoothedPWDB)); - - pMgntInfo->Ratr_State = Ratr_State_new; - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, Ratr_State_new); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); - /**/ - } - - #else - if (ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); - } else if (pDM_Odm->bChangeState) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); - } - #endif - } - - // - // The following part configure AP/VWifi/IBSS rate adaptive mask. - // - - if (pMgntInfo->mIbss) // Target: AP/IBSS peer. - pTargetAdapter = GetDefaultAdapter(pAdapter); - else - pTargetAdapter = GetFirstAPAdapter(pAdapter); - - // if extension port (softap) is started, updaet RA table for more than one clients associate - if (pTargetAdapter != NULL) { - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - pEntry = AsocEntry_EnumStation(pTargetAdapter, i); - - if (IS_STA_VALID(pEntry)) { - - odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pEntry->AssociatedMacId, pEntry->IOTPeer, pEntry->rssi_stat.UndecoratedSmoothedPWDB); - - #if RA_MASK_PHYDMLIZE_WIN - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State); - - if (pEntry->Ratr_State != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->MacAddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - pEntry->Ratr_State, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - pEntry->Ratr_State = Ratr_State_new; - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pEntry->AssociatedMacId, NULL, Ratr_State_new); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); - /**/ - } - - - #else - - if (ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State); - } else if (pDM_Odm->bChangeState) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); - } - #endif - - } - } - } - - #if RA_MASK_PHYDMLIZE_WIN - - #else - if (pMgntInfo->bSetTXPowerTrainingByOid) - pMgntInfo->bSetTXPowerTrainingByOid = FALSE; - #endif -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -} - - -VOID -odm_RefreshRateAdaptiveMaskCE( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - - if (RTW_CANNOT_RUN(pAdapter)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); - return; - } - - if (!pDM_Odm->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); - return; - } - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - pEntry = pDM_Odm->pODM_StaInfo[i]; - - if (IS_STA_VALID(pEntry)) { - - if (IS_MCAST(pEntry->hwaddr)) - continue; - - #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8821)) { - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres) { - pRA->bUseLdpc = TRUE; - pRA->bLowerRtsRate = TRUE; - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - Set_RA_LDPC_8812(pEntry, TRUE); - //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB); - } else if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres - 5)) { - pRA->bUseLdpc = FALSE; - pRA->bLowerRtsRate = FALSE; - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - Set_RA_LDPC_8812(pEntry, FALSE); - //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB); - } - } - #endif - - #if RA_MASK_PHYDMLIZE_CE - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level); - - if (pEntry->rssi_level != Ratr_State_new) { - - /*ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - pEntry->rssi_level, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - pEntry->rssi_level = Ratr_State_new; - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); - /**/ - } - #else - if (TRUE == ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pEntry->rssi_level)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level)); - //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); - } else if (pDM_Odm->bChangeState) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); - } - #endif - - } - } - -#endif -} - -VOID -odm_RefreshRateAdaptiveMaskAPADSL( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - struct rtl8192cd_priv *priv = pDM_Odm->priv; - struct aid_obj *aidarray; - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - - if (priv->up_time % 2) - return; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; - - if (IS_STA_VALID(pEntry)) { - - #if defined(UNIVERSAL_REPEATER) || defined(MBSSID) - aidarray = container_of(pEntry, struct aid_obj, station); - priv = aidarray->priv; - #endif - - if (!priv->pmib->dot11StationConfigEntry.autoRate) - continue; - -#if RA_MASK_PHYDMLIZE_AP - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, (u4Byte)pEntry->rssi, pEntry->rssi_level); - - if (pEntry->rssi_level != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->hwaddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", pEntry->rssi_level, Ratr_State_new, pEntry->rssi)); - - pEntry->rssi_level = Ratr_State_new; - phydm_gen_ramask_h2c_AP(pDM_Odm, priv, pEntry, pEntry->rssi_level); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); - /**/ - } - -#else - if (ODM_RAStateCheck(pDM_Odm, (s4Byte)pEntry->rssi, FALSE, &pEntry->rssi_level)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->hwaddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi, pEntry->rssi_level)); - - #ifdef CONFIG_WLAN_HAL - if (IS_HAL_CHIP(priv)) { - #ifdef WDS - /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ - #endif - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, pEntry->rssi_level); - } else - #endif - - #ifdef CONFIG_RTL_8812_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8812E) - UpdateHalRAMask8812(priv, pEntry, 3); - else - #endif - { - #ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8188E) { - #ifdef TXREPORT - add_RATid(priv, pEntry); - #endif - } - #endif - - - } - } -#endif /*#ifdef RA_MASK_PHYDMLIZE*/ - - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -} - -VOID -odm_RefreshBasicRateMask( - IN PVOID pDM_VOID -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - static u1Byte Stage = 0; - u1Byte CurStage = 0; - OCTET_STRING osRateSet; - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); - u1Byte RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; - - if (pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821) - return; - - if (pDM_Odm->bLinked == FALSE) // unlink Default port information - CurStage = 0; - else if (pDM_Odm->RSSI_Min < 40) // link RSSI < 40% - CurStage = 1; - else if (pDM_Odm->RSSI_Min > 45) // link RSSI > 45% - CurStage = 3; - else - CurStage = 2; // link 25% <= RSSI <= 30% - - if (CurStage != Stage) { - if (CurStage == 1) { - FillOctetString(osRateSet, RateSet, 5); - FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE); - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet); - } else if (CurStage == 3 && (Stage == 1 || Stage == 2)) - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates)); - } - - Stage = CurStage; -#endif -} - -u1Byte -phydm_rate_order_compute( - IN PVOID pDM_VOID, - IN u1Byte rate_idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_order = 0; - - if (rate_idx >= ODM_RATEVHTSS4MCS0) { - - rate_idx -= ODM_RATEVHTSS4MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { - - rate_idx -= ODM_RATEVHTSS3MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { - - rate_idx -= ODM_RATEVHTSS2MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - - rate_idx -= ODM_RATEVHTSS1MCS0; - /**/ - } else if (rate_idx >= ODM_RATEMCS24) { - - rate_idx -= ODM_RATEMCS24; - /**/ - } else if (rate_idx >= ODM_RATEMCS16) { - - rate_idx -= ODM_RATEMCS16; - /**/ - } else if (rate_idx >= ODM_RATEMCS8) { - - rate_idx -= ODM_RATEMCS8; - /**/ - } - rate_order = rate_idx; - - return rate_order; - -} - -VOID -phydm_ra_common_info_update( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u2Byte macid; - u1Byte rate_order_tmp; - u1Byte cnt = 0; - - pRA_Table->highest_client_tx_order = 0; - pRA_Table->power_tracking_flag = 1; - - if (pDM_Odm->number_linked_client != 0) { - for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { - - rate_order_tmp = phydm_rate_order_compute(pDM_Odm, ((pRA_Table->link_tx_rate[macid]) & 0x7f)); - - if (rate_order_tmp >= (pRA_Table->highest_client_tx_order)) { - pRA_Table->highest_client_tx_order = rate_order_tmp; - pRA_Table->highest_client_tx_rate_order = macid; - } - - cnt++; - - if (cnt == pDM_Odm->number_linked_client) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (pRA_Table->highest_client_tx_rate_order), (pRA_Table->highest_client_tx_order))); - } -} - -VOID -phydm_ra_info_watchdog( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - phydm_ra_common_info_update(pDM_Odm); - phydm_ra_dynamic_retry_limit(pDM_Odm); - phydm_ra_dynamic_retry_count(pDM_Odm); - odm_RefreshRateAdaptiveMask(pDM_Odm); - odm_RefreshBasicRateMask(pDM_Odm); -} - -VOID -phydm_ra_info_init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - pRA_Table->highest_client_tx_rate_order = 0; - pRA_Table->highest_client_tx_order = 0; - pRA_Table->RA_threshold_offset = 0; - pRA_Table->RA_offset_direction = 0; - - #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - phydm_ra_dynamic_retry_limit_init(pDM_Odm); - #endif - - #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - phydm_ra_dynamic_rate_id_init(pDM_Odm); - #endif - #if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_ParaAdjust_init(pDM_Odm); - #endif - -} - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -u1Byte -odm_Find_RTS_Rate( - IN PVOID pDM_VOID, - IN u1Byte Tx_Rate, - IN BOOLEAN bErpProtect -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte RTS_Ini_Rate = ODM_RATE6M; - - if (bErpProtect) /* use CCK rate as RTS*/ - RTS_Ini_Rate = ODM_RATE1M; - else { - switch (Tx_Rate) { - case ODM_RATEVHTSS3MCS9: - case ODM_RATEVHTSS3MCS8: - case ODM_RATEVHTSS3MCS7: - case ODM_RATEVHTSS3MCS6: - case ODM_RATEVHTSS3MCS5: - case ODM_RATEVHTSS3MCS4: - case ODM_RATEVHTSS3MCS3: - case ODM_RATEVHTSS2MCS9: - case ODM_RATEVHTSS2MCS8: - case ODM_RATEVHTSS2MCS7: - case ODM_RATEVHTSS2MCS6: - case ODM_RATEVHTSS2MCS5: - case ODM_RATEVHTSS2MCS4: - case ODM_RATEVHTSS2MCS3: - case ODM_RATEVHTSS1MCS9: - case ODM_RATEVHTSS1MCS8: - case ODM_RATEVHTSS1MCS7: - case ODM_RATEVHTSS1MCS6: - case ODM_RATEVHTSS1MCS5: - case ODM_RATEVHTSS1MCS4: - case ODM_RATEVHTSS1MCS3: - case ODM_RATEMCS15: - case ODM_RATEMCS14: - case ODM_RATEMCS13: - case ODM_RATEMCS12: - case ODM_RATEMCS11: - case ODM_RATEMCS7: - case ODM_RATEMCS6: - case ODM_RATEMCS5: - case ODM_RATEMCS4: - case ODM_RATEMCS3: - case ODM_RATE54M: - case ODM_RATE48M: - case ODM_RATE36M: - case ODM_RATE24M: - RTS_Ini_Rate = ODM_RATE24M; - break; - case ODM_RATEVHTSS3MCS2: - case ODM_RATEVHTSS3MCS1: - case ODM_RATEVHTSS2MCS2: - case ODM_RATEVHTSS2MCS1: - case ODM_RATEVHTSS1MCS2: - case ODM_RATEVHTSS1MCS1: - case ODM_RATEMCS10: - case ODM_RATEMCS9: - case ODM_RATEMCS2: - case ODM_RATEMCS1: - case ODM_RATE18M: - case ODM_RATE12M: - RTS_Ini_Rate = ODM_RATE12M; - break; - case ODM_RATEVHTSS3MCS0: - case ODM_RATEVHTSS2MCS0: - case ODM_RATEVHTSS1MCS0: - case ODM_RATEMCS8: - case ODM_RATEMCS0: - case ODM_RATE9M: - case ODM_RATE6M: - RTS_Ini_Rate = ODM_RATE6M; - break; - case ODM_RATE11M: - case ODM_RATE5_5M: - case ODM_RATE2M: - case ODM_RATE1M: - RTS_Ini_Rate = ODM_RATE1M; - break; - default: - RTS_Ini_Rate = ODM_RATE6M; - break; - } - } - - if (*pDM_Odm->pBandType == 1) { - if (RTS_Ini_Rate < ODM_RATE6M) - RTS_Ini_Rate = ODM_RATE6M; - } - return RTS_Ini_Rate; - -} - -VOID -odm_Set_RA_DM_ARFB_by_Noisy( - IN PDM_ODM_T pDM_Odm -) -{ -#if 0 - - /*DbgPrint("DM_ARFB ====>\n");*/ - if (pDM_Odm->bNoisyState) { - ODM_Write4Byte(pDM_Odm, 0x430, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0x434, 0x05040200); - /*DbgPrint("DM_ARFB ====> Noisy State\n");*/ - } else { - ODM_Write4Byte(pDM_Odm, 0x430, 0x02010000); - ODM_Write4Byte(pDM_Odm, 0x434, 0x07050403); - /*DbgPrint("DM_ARFB ====> Clean State\n");*/ - } -#endif -} - -VOID -ODM_UpdateNoisyState( - IN PVOID pDM_VOID, - IN BOOLEAN bNoisyStateFromC2H -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);*/ - if (pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || - pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723D) - pDM_Odm->bNoisyState = bNoisyStateFromC2H; - odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm); -}; - -VOID -phydm_update_pwr_track( - IN PVOID pDM_VOID, - IN u1Byte Rate -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte pathIdx = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get Rate=0x%x\n", Rate)); - - pDM_Odm->TxRate = Rate; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - #if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); - #else - if (pDM_Odm->SupportICType == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8812) { - for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8812A; pathIdx++) { - #if (RTL8812A_SUPPORT == 1) - ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, pathIdx, 0); - #endif - } - } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - #if (RTL8723B_SUPPORT == 1) - ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8192E; pathIdx++) { - #if (RTL8192E_SUPPORT == 1) - ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, pathIdx, 0); - #endif - } - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - #if (RTL8188E_SUPPORT == 1) - ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } - #endif - #else - PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); - #endif - #endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -s4Byte -phydm_FindMinimumRSSI( -IN PDM_ODM_T pDM_Odm, -IN PADAPTER pAdapter, -IN OUT BOOLEAN *pbLink_temp - - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - BOOLEAN act_as_ap = ACTING_AS_AP(pAdapter); - - /* 1.Determine the minimum RSSI */ - if ((!pMgntInfo->bMediaConnect) || - (act_as_ap && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ - - pHalData->MinUndecoratedPWDBForDM = 0; - *pbLink_temp = FALSE; - - } else - *pbLink_temp = TRUE; - - - if (pMgntInfo->bMediaConnect) { /* Default port*/ - - if (act_as_ap || pMgntInfo->mIbss) { - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; - /**/ - } else { - pHalData->MinUndecoratedPWDBForDM = pHalData->UndecoratedSmoothedPWDB; - /**/ - } - } else { /* associated entry pwdb*/ - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; - /**/ - } - - return pHalData->MinUndecoratedPWDBForDM; -} - -VOID -ODM_UpdateInitRateWorkItemCallback( - IN PVOID pContext -) -{ - PADAPTER Adapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - u1Byte p = 0; - - if (pDM_Odm->SupportICType == ODM_RTL8821) { - ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8812) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ - - ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0); - /**/ - } - } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ - ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0); - /**/ - } - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } -} - -VOID -odm_RSSIDumpToRegister( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - - if (pDM_Odm->SupportICType == ODM_RTL8812) { - PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]); - - /* Rx EVM*/ - PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]); - - /* Rx SNR*/ - PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); - - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]); - - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]); - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]); - /* Rx EVM*/ - PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]); - /* Rx SNR*/ - PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]); - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]); - } -} - -VOID -odm_RefreshLdpcRtsMP( - IN PADAPTER pAdapter, - IN PDM_ODM_T pDM_Odm, - IN u1Byte mMacId, - IN u1Byte IOTPeer, - IN s4Byte UndecoratedSmoothedPWDB -) -{ - BOOLEAN bCtlLdpc = FALSE; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; - - if (pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8812) - return; - - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - bCtlLdpc = TRUE; - else if (pDM_Odm->SupportICType == ODM_RTL8812 && - IOTPeer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) - bCtlLdpc = TRUE; - - if (bCtlLdpc) { - if (UndecoratedSmoothedPWDB < (pRA->LdpcThres - 5)) - MgntSet_TX_LDPC(pAdapter, mMacId, TRUE); - else if (UndecoratedSmoothedPWDB > pRA->LdpcThres) - MgntSet_TX_LDPC(pAdapter, mMacId, FALSE); - } - - if (UndecoratedSmoothedPWDB < (pRA->RtsThres - 5)) - pRA->bLowerRtsRate = TRUE; - else if (UndecoratedSmoothedPWDB > pRA->RtsThres) - pRA->bLowerRtsRate = FALSE; -} - -#if 0 -VOID -ODM_DynamicARFBSelect( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN BOOLEAN Collision_State -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - - if (pDM_Odm->SupportICType != ODM_RTL8192E) - return; - - if (Collision_State == pRA_Table->PT_collision_pre) - return; - - if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { - if (Collision_State == 1) { - if (rate == DESC_RATEMCS12) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501); - } else if (rate == DESC_RATEMCS11) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605); - } else if (rate == DESC_RATEMCS10) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706); - } else if (rate == DESC_RATEMCS9) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707); - } else { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808); - } - } else { /* Collision_State == 0*/ - if (rate == DESC_RATEMCS12) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); - } else if (rate == DESC_RATEMCS11) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807); - } else if (rate == DESC_RATEMCS10) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908); - } else if (rate == DESC_RATEMCS9) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808); - } else { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909); - } - } - } else { /* MCS13~MCS15, 1SS, G-mode*/ - if (Collision_State == 1) { - if (rate == DESC_RATEMCS15) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302); - } else if (rate == DESC_RATEMCS14) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302); - } else if (rate == DESC_RATEMCS13) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502); - } else { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402); - } - } else { // Collision_State == 0 - if (rate == DESC_RATEMCS15) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504); - } else if (rate == DESC_RATEMCS14) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); - } else if (rate == DESC_RATEMCS13) { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); - } else { - - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); - } - } - } - pRA_Table->PT_collision_pre = Collision_State; -} -#endif - -VOID -ODM_RateAdaptiveStateApInit( - IN PVOID PADAPTER_VOID, - IN PRT_WLAN_STA pEntry -) -{ - PADAPTER Adapter = (PADAPTER)PADAPTER_VOID; - pEntry->Ratr_State = DM_RATR_STA_INIT; -} -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - -static void -FindMinimumRSSI( - IN PADAPTER pAdapter -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - - /*Determine the minimum RSSI*/ - - if ((pDM_Odm->bLinked != _TRUE) && - (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { - pHalData->MinUndecoratedPWDBForDM = 0; - /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ - } else - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; - - /*DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);*/ - /*ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));*/ -} - -u8Byte -PhyDM_Get_Rate_Bitmap_Ex( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u8Byte ra_mask, - IN u1Byte rssi_level, - OUT u8Byte *dm_RA_Mask, - OUT u1Byte *dm_RteID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u8Byte rate_bitmap = 0; - u1Byte WirelessMode; - - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (!IS_STA_VALID(pEntry)) - return ra_mask; - WirelessMode = pEntry->wireless_mode; - switch (WirelessMode) { - case ODM_WM_B: - if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ - rate_bitmap = 0x000000000000000d; - else - rate_bitmap = 0x000000000000000f; - break; - - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else - rate_bitmap = 0x0000000000000ff0; - break; - - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000000000ff0; - else - rate_bitmap = 0x0000000000000ff5; - break; - - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_B|ODM_WM_N24G): - case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): { - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000000000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000000000ff000; - else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - rate_bitmap = 0x00000000000ff015; - else - rate_bitmap = 0x00000000000ff005; - } - } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000000000f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000000000f8ff000; - else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - rate_bitmap = 0x000000000f8ff015; - else - rate_bitmap = 0x000000000f8ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000f0f0f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000fcfcfe000; - else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - rate_bitmap = 0x0000000ffffff015; - else - rate_bitmap = 0x0000000ffffff005; - } - } - } - break; - - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0x00000000fc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; - else - rate_bitmap = 0x00000000ffffffff; - break; - - case (ODM_WM_AC|ODM_WM_A): - - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000003fe000; - else - rate_bitmap = 0x00000000003ff010; - } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ - else - rate_bitmap = 0x00000000fffff010; /* All */ - } else { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ - else - rate_bitmap = 0x000003fffffff010ULL; /* All */ - } - break; - - default: - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) - rate_bitmap = 0x00000000000fffff; - else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) - rate_bitmap = 0x000000000fffffff; - else - rate_bitmap = 0x0000003fffffffffULL; - break; - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, WirelessMode, rate_bitmap)); - - return (ra_mask & rate_bitmap); -} - - -u4Byte -ODM_Get_Rate_Bitmap( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u4Byte ra_mask, - IN u1Byte rssi_level -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u4Byte rate_bitmap = 0; - u1Byte WirelessMode; - //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); - - - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (!IS_STA_VALID(pEntry)) - return ra_mask; - - WirelessMode = pEntry->wireless_mode; - - switch (WirelessMode) { - case ODM_WM_B: - if (ra_mask & 0x0000000c) //11M or 5.5M enable - rate_bitmap = 0x0000000d; - else - rate_bitmap = 0x0000000f; - break; - - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else - rate_bitmap = 0x00000ff0; - break; - - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000ff0; - else - rate_bitmap = 0x00000ff5; - break; - - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : - case (ODM_WM_B|ODM_WM_N24G) : - case (ODM_WM_G|ODM_WM_N24G) : - case (ODM_WM_A|ODM_WM_N5G) : { - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000ff000; - else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - rate_bitmap = 0x000ff015; - else - rate_bitmap = 0x000ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0f8ff000; - else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - rate_bitmap = 0x0f8ff015; - else - rate_bitmap = 0x0f8ff005; - } - } - } - break; - - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0xfc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; - else - rate_bitmap = 0xffffffff; - break; - - case (ODM_WM_AC|ODM_WM_A): - - if (pDM_Odm->RFType == RF_1T1R) { - if (rssi_level == 1) // add by Gary for ac-series - rate_bitmap = 0x003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x003ff000; - else - rate_bitmap = 0x003ff010; - } else { - if (rssi_level == 1) // add by Gary for ac-series - rate_bitmap = 0xfe3f8000; // VHT 2SS MCS3~9 - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; // VHT 2SS MCS0~9 - else - rate_bitmap = 0xfffff010; // All - } - break; - - default: - if (pDM_Odm->RFType == RF_1T2R) - rate_bitmap = 0x000fffff; - else - rate_bitmap = 0x0fffffff; - break; - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, WirelessMode, rate_bitmap)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, WirelessMode, rate_bitmap)); - - return (ra_mask & rate_bitmap); - -} - -#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -VOID -phydm_gen_ramask_h2c_AP( - IN PVOID pDM_VOID, - IN struct rtl8192cd_priv *priv, - IN PSTA_INFO_T *pEntry, - IN u1Byte rssi_level -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType == ODM_RTL8812) { - - #if (RTL8812A_SUPPORT == 1) - UpdateHalRAMask8812(priv, pEntry, rssi_level); - /**/ - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - - #if (RTL8188E_SUPPORT == 1) - #ifdef TXREPORT - add_RATid(priv, pEntry); - /**/ - #endif - #endif - } else { - - #ifdef CONFIG_WLAN_HAL - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, rssi_level); - #endif - } -} - - -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ - - -/* RA_MASK_PHYDMLIZE, will delete it later*/ - -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) - -BOOLEAN -ODM_RAStateCheck( - IN PVOID pDM_VOID, - IN s4Byte RSSI, - IN BOOLEAN bForceUpdate, - OUT pu1Byte pRATRState -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; - const u1Byte GoUpGap = 5; - u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; - u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; - u1Byte RATRState; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *pRATRState)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); - /* Threshold Adjustment:*/ - /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ - /* Here GoUpGap is added to solve the boundary's level alternation issue.*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u1Byte UltraLowRSSIThreshForRA = pRA->UltraLowRSSIThresh; - - if (pDM_Odm->SupportICType == ODM_RTL8881A) - LowRSSIThreshForRA = 30; /* for LDPC / BCC switch*/ -#endif - - switch (*pRATRState) { - case DM_RATR_STA_INIT: - case DM_RATR_STA_HIGH: - break; - - case DM_RATR_STA_MIDDLE: - HighRSSIThreshForRA += GoUpGap; - break; - - case DM_RATR_STA_LOW: - HighRSSIThreshForRA += GoUpGap; - LowRSSIThreshForRA += GoUpGap; - break; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - case DM_RATR_STA_ULTRA_LOW: - HighRSSIThreshForRA += GoUpGap; - LowRSSIThreshForRA += GoUpGap; - UltraLowRSSIThreshForRA += GoUpGap; - break; -#endif - - default: - ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState)); - break; - } - - /* Decide RATRState by RSSI.*/ - if (RSSI > HighRSSIThreshForRA) - RATRState = DM_RATR_STA_HIGH; - else if (RSSI > LowRSSIThreshForRA) - RATRState = DM_RATR_STA_MIDDLE; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - else if (RSSI > UltraLowRSSIThreshForRA) - RATRState = DM_RATR_STA_LOW; - else - RATRState = DM_RATR_STA_ULTRA_LOW; -#else - else - RATRState = DM_RATR_STA_LOW; -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); - /*printk("==>%s,RATRState:0x%02x ,RSSI:%d\n",__FUNCTION__,RATRState,RSSI);*/ - - if (*pRATRState != RATRState || bForceUpdate) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d -> %d\n", *pRATRState, RATRState)); - *pRATRState = RATRState; - return TRUE; - } - - return FALSE; -} - -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +phydm_h2C_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte H2C_Parameter[H2C_MAX_LENGTH] = {0}; + u1Byte phydm_h2c_id = (u1Byte)dm_value[0]; + u1Byte i; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + PHYDM_SNPRINTF((output+used, out_len-used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); + for (i = 0; i < H2C_MAX_LENGTH; i++) { + + H2C_Parameter[i] = (u1Byte)dm_value[i+1]; + PHYDM_SNPRINTF((output+used, out_len-used, "H2C: Byte[%d] = ((0x%x))\n", i, H2C_Parameter[i])); + } + + ODM_FillH2CCmd(pDM_Odm, phydm_h2c_id, H2C_MAX_LENGTH, H2C_Parameter); + +} + +#if (defined(CONFIG_RA_DBG_CMD)) +VOID +odm_RA_ParaAdjust_Send_H2C( + IN PVOID pDM_VOID +) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte H2C_Parameter[6] = {0}; + + H2C_Parameter[0] = RA_FIRST_MACID; + + if (pRA_Table->RA_Para_feedback_req) { /*H2C_Parameter[5]=1 ; ask FW for all RA parameters*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); + H2C_Parameter[5] |= BIT1; /*ask FW to report RA parameters*/ + H2C_Parameter[1] = pRA_Table->para_idx; /*pRA_Table->para_idx;*/ + pRA_Table->RA_Para_feedback_req = 0; + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); + + H2C_Parameter[1] = pRA_Table->para_idx; + H2C_Parameter[2] = pRA_Table->rate_idx; + /* [8 bit]*/ + if (pRA_Table->para_idx == RADBG_RTY_PENALTY || pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO || pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + H2C_Parameter[3] = pRA_Table->value; + H2C_Parameter[4] = 0; + } + /* [16 bit]*/ + else { + H2C_Parameter[3] = (u1Byte)(((pRA_Table->value_16) & 0xf0) >> 4); /*byte1*/ + H2C_Parameter[4] = (u1Byte)((pRA_Table->value_16) & 0x0f); /*byte0*/ + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[1] = 0x%x\n", H2C_Parameter[1])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[2] = 0x%x\n", H2C_Parameter[2])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[3] = 0x%x\n", H2C_Parameter[3])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[4] = 0x%x\n", H2C_Parameter[4])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[5] = 0x%x\n", H2C_Parameter[5])); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RA_PARA_ADJUST, 6, H2C_Parameter); + +} + + +VOID +odm_RA_ParaAdjust( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte rate_idx = pRA_Table->rate_idx; + u1Byte value = pRA_Table->value; + u1Byte Pre_value = 0xff; + + if (pRA_Table->para_idx == RADBG_RTY_PENALTY) { + Pre_value = pRA_Table->RTY_P[rate_idx]; + pRA_Table->RTY_P[rate_idx] = value; + pRA_Table->RTY_P_modify_note[rate_idx] = 1; + } else if (pRA_Table->para_idx == RADBG_N_HIGH) { + + } else if (pRA_Table->para_idx == RADBG_N_LOW) { + + } else if (pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO) { + Pre_value = pRA_Table->RATE_UP_RTY_RATIO[rate_idx]; + pRA_Table->RATE_UP_RTY_RATIO[rate_idx] = value; + pRA_Table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; + } else if (pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + Pre_value = pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx]; + pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx] = value; + pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], Rate[ %d ], ((%d)) -> ((%d))\n", pRA_Table->para_idx, rate_idx, Pre_value, value)); + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); +} + +VOID +phydm_ra_print_msg( + IN PVOID pDM_VOID, + IN u1Byte *value, + IN u1Byte *value_default, + IN u1Byte *modify_note +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u4Byte i; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate index| |Current-value| |Default-value| |Modify?|\n")); + for (i = 0 ; i <= (pRA_Table->rate_length); i++) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); +#else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); +#endif + } + +} + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->is_ra_dbg_init = FALSE; + + if (dm_value[0] == 100) { /*1 Print RA Parameters*/ + u1Byte default_pointer_value; + u1Byte *pvalue; + u1Byte *pvalue_default; + u1Byte *pmodify_note; + + pvalue = pvalue_default = pmodify_note = &default_pointer_value; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); + + if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); + pvalue = &(pRA_Table->RTY_P[0]); + pvalue_default = &(pRA_Table->RTY_P_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RTY_P_modify_note[0]); + } else if (dm_value[1] == RADBG_N_HIGH) { /* [2]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); + + } else if (dm_value[1] == RADBG_N_LOW) { /*[3]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); + + } else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); + pvalue = &(pRA_Table->RATE_UP_RTY_RATIO[0]); + pvalue_default = &(pRA_Table->RATE_UP_RTY_RATIO_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RATE_UP_RTY_RATIO_modify_note[0]); + } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); + pvalue = &(pRA_Table->RATE_DOWN_RTY_RATIO[0]); + pvalue_default = &(pRA_Table->RATE_DOWN_RTY_RATIO_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[0]); + } + + phydm_ra_print_msg(pDM_Odm, pvalue, pvalue_default, pmodify_note); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); + + } else if (dm_value[0] == 101) { + pRA_Table->para_idx = (u1Byte)dm_value[1]; + + pRA_Table->RA_Para_feedback_req = 1; + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + } else { + pRA_Table->para_idx = (u1Byte)dm_value[0]; + pRA_Table->rate_idx = (u1Byte)dm_value[1]; + pRA_Table->value = (u1Byte)dm_value[2]; + + odm_RA_ParaAdjust(pDM_Odm); + } +} + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte i; + u1Byte ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; + u1Byte RateSize_HT_1ss = 20, RateSize_HT_2ss = 28, RateSize_HT_3ss = 36; /*4+8+8+8+8 =36*/ + u1Byte RateSize_VHT_1ss = 10, RateSize_VHT_2ss = 20, RateSize_VHT_3ss = 30; /*10 + 10 +10 =30*/ + /* + RTY_PENALTY = 1, //u8 + N_HIGH = 2, + N_LOW = 3, + RATE_UP_TABLE = 4, + RATE_DOWN_TABLE = 5, + TRYING_NECESSARY = 6, + DROPING_NECESSARY = 7, + RATE_UP_RTY_RATIO = 8, //u8 + RATE_DOWN_RTY_RATIO= 9, //u8 + ALL_PARA = 0xff + + */ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_RA_ParaAdjust_init\n")); + + if (pDM_Odm->SupportICType & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D)) + pRA_Table->rate_length = RateSize_HT_1ss; + else if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) + pRA_Table->rate_length = RateSize_HT_2ss; + else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) + pRA_Table->rate_length = RateSize_HT_1ss + RateSize_VHT_1ss; + else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8822B)) + pRA_Table->rate_length = RateSize_HT_2ss + RateSize_VHT_2ss; + else if (pDM_Odm->SupportICType == ODM_RTL8814A) + pRA_Table->rate_length = RateSize_HT_3ss + RateSize_VHT_3ss; + else + pRA_Table->rate_length = RateSize_HT_1ss; + + pRA_Table->is_ra_dbg_init = TRUE; + for (i = 0; i < 3; i++) { + pRA_Table->RA_Para_feedback_req = 1; + pRA_Table->para_idx = ra_para_pool_u8[i]; + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + } +} + +#else + +VOID +phydm_RA_debug_PCR( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output+used, out_len-used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); + /**/ + } else if (dm_value[0] == 0) { + pRA_Table->RA_offset_direction = 0; + pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; + PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", pRA_Table->RA_threshold_offset)); + } else if (dm_value[0] == 1) { + pRA_Table->RA_offset_direction = 1; + pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; + PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", pRA_Table->RA_threshold_offset)); + } else { + PHYDM_SNPRINTF((output+used, out_len-used, "[Set] Error\n")); + /**/ + } + +} + +#endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ + +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + u1Byte para_idx = CmdBuf[0]; /*Retry Penalty, NH, NL*/ + u1Byte RateTypeStart = CmdBuf[1]; + u1Byte RateTypeLength = CmdLen - 2; + u1Byte i; + + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] CmdBuf[0]= (( %d ))\n", CmdBuf[0])); + +#if (defined(CONFIG_RA_DBG_CMD)) + if (para_idx == RADBG_RTY_PENALTY) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |RTY Penality Index|\n")); + + for (i = 0 ; i < (RateTypeLength) ; i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RTY_P_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RTY_P[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RTY_P[RateTypeStart + i])); + } + + } else if (para_idx == RADBG_N_HIGH) { + /**/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-High|\n")); + + + } else if (para_idx == RADBG_N_LOW) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-Low|\n")); + /**/ + } + else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Up RTY Ratio|\n")); + + for (i = 0; i < (RateTypeLength); i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RATE_UP_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i])); + } + } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Down RTY Ratio|\n")); + + for (i = 0; i < (RateTypeLength); i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RATE_DOWN_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i])); + } + } else +#endif + if (para_idx == RADBG_DEBUG_MONITOR1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { + + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Rate =", CmdBuf[2] & 0x7f)); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (CmdBuf[2] & 0x80) >> 7)); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", CmdBuf[3])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", CmdBuf[4])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", CmdBuf[5])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", CmdBuf[6])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[7])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[8])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", CmdBuf[9])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", CmdBuf[10])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", CmdBuf[11])); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", CmdBuf[2])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[3])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[4])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest Rate =", CmdBuf[5])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest Rate =", CmdBuf[6])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", CmdBuf[7])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", CmdBuf[8]));; + } + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RateID =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", CmdBuf[2])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", CmdBuf[3])); + + for (i = 4; i <= 11; i++) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", CmdBuf[i])); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + CmdBuf[8], CmdBuf[7], CmdBuf[6], CmdBuf[5], CmdBuf[4], CmdBuf[3], CmdBuf[2], CmdBuf[1])); + } + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR3) { + + for (i = 0; i < (CmdLen - 1); i++) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, CmdBuf[1 + i])); + } else if (para_idx == RADBG_DEBUG_MONITOR4) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA Version =", CmdBuf[1], CmdBuf[2])); + else if (para_idx == RADBG_DEBUG_MONITOR5) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", CmdBuf[2])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate down ratio =", CmdBuf[3])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", CmdBuf[4])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", CmdBuf[5], CmdBuf[6])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", CmdBuf[11], CmdBuf[10], CmdBuf[9], CmdBuf[8], CmdBuf[7])); + } +} + +VOID +phydm_ra_dynamic_retry_count( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + PSTA_INFO_T pEntry; + u1Byte i, retry_offset; + u4Byte ma_rx_tp; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)) { + return; + } + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pDM_Odm->pre_b_noisy = %d\n", pDM_Odm->pre_b_noisy ));*/ + if (pDM_Odm->pre_b_noisy != pDM_Odm->NoisyDecision) { + + if (pDM_Odm->NoisyDecision) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); + ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x0); + ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x04030201); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); + ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x01000000); + ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x06050402); + } + pDM_Odm->pre_b_noisy = pDM_Odm->NoisyDecision; + } +} + +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + +VOID +phydm_retry_limit_table_bound( + IN PVOID pDM_VOID, + IN u1Byte *retry_limit, + IN u1Byte offset +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + if (*retry_limit > offset) { + + *retry_limit -= offset; + + if (*retry_limit < pRA_Table->retrylimit_low) + *retry_limit = pRA_Table->retrylimit_low; + else if (*retry_limit > pRA_Table->retrylimit_high) + *retry_limit = pRA_Table->retrylimit_high; + } else + *retry_limit = pRA_Table->retrylimit_low; +} + +VOID +phydm_reset_retry_limit_table( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte i; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ + + #else + #if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) + u1Byte per_rate_retrylimit_table_20M[ODM_RATEMCS15+1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ + }; + u1Byte per_rate_retrylimit_table_40M[ODM_RATEMCS15+1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ + }; + + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + + #elif (RTL8812A_SUPPORT == 1) + + #elif(RTL8814A_SUPPORT == 1) + + #else + + #endif + #endif + + memcpy(&(pRA_Table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); + memcpy(&(pRA_Table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); + + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), 0); + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), 0); + } +} + +VOID +phydm_ra_dynamic_retry_limit_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->retry_descend_num = RA_RETRY_DESCEND_NUM; + pRA_Table->retrylimit_low = RA_RETRY_LIMIT_LOW; + pRA_Table->retrylimit_high = RA_RETRY_LIMIT_HIGH; + + phydm_reset_retry_limit_table(pDM_Odm); + +} + +#endif + +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +) +{ +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + PSTA_INFO_T pEntry; + u1Byte i, retry_offset; + u4Byte ma_rx_tp; + + + if (pDM_Odm->pre_number_active_client == pDM_Odm->number_active_client) { + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); + return; + + } else { + if (pDM_Odm->number_active_client == 1) { + phydm_reset_retry_limit_table(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); + } else { + + retry_offset = pDM_Odm->number_active_client * pRA_Table->retry_descend_num; + + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), retry_offset); + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), retry_offset); + } + } + } +#endif +} + +#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) +VOID +phydm_ra_dynamic_rate_id_on_assoc( + IN PVOID pDM_VOID, + IN u1Byte wireless_mode, + IN u1Byte init_rate_id +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", pDM_Odm->RFType, wireless_mode, init_rate_id)); + + if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { + + if ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) + ){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); + ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((pDM_Odm->SupportICType & (ODM_RTL8812)) && + (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) + ){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); + ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } + } + +} + +VOID +phydm_ra_dynamic_rate_id_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) { + + ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + + ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } +} + +VOID +phydm_update_rate_id( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN u1Byte platform_macid +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte current_tx_ss; + u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u1Byte wireless_mode; + u1Byte phydm_macid; + PSTA_INFO_T pEntry; + + +#if 0 + if (rate_idx >= ODM_RATEVHTSS2MCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS2MCS0))); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS1MCS0))); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEMCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEMCS0))); + /*dummy for SD4 check patch*/ + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); + /*dummy for SD4 check patch*/ + } +#endif + + phydm_macid = pDM_Odm->platform2phydm_macid_table[platform_macid]; + pEntry = pDM_Odm->pODM_StaInfo[phydm_macid]; + + if (IS_STA_VALID(pEntry)) { + wireless_mode = pEntry->WirelessMode; + + if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { + + pEntry->ratr_idx = pEntry->ratr_idx_init; + if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ + if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ + + pEntry->ratr_idx = ARFR_5_RATE_ID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); + } + } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ + if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ + + pEntry->ratr_idx = ARFR_0_RATE_ID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, pEntry->ratr_idx)); + } + } + +} +#endif + +VOID +phydm_print_rate( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN u4Byte dbg_component +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u1Byte vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; + u1Byte b_sgi = (rate & 0x80)>>7; + + ODM_RT_TRACE_F(pDM_Odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", + ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0)%10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M)?legacy_table[rate_idx]:0)), + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M")); +} + +VOID +phydm_c2h_ra_report_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte legacy_table[12] = {1,2,5,11,6,9,12,18,24,36,48,54}; + u1Byte isMU_RPT=0; + u1Byte macid = CmdBuf[1]; + u1Byte rate = CmdBuf[0]; + u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u1Byte pre_rate = pRA_Table->link_tx_rate[macid]; + u1Byte rate_order; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + GET_HAL_DATA(Adapter)->CurrentRARate = HwRateToMRate(rate_idx); + #endif + + + if (CmdLen >= 4) { + if (CmdBuf[3] == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-Rate Update[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 0xff) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate Back[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); + /**/ + } else if (CmdBuf[3] == 5) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); + /**/ + } + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx Rate Update[%d]:", macid)); + /**/ + } + + /*phydm_print_rate(pDM_Odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ + phydm_print_rate(pDM_Odm, rate, ODM_COMP_RATE_ADAPTIVE); + if (macid >= 128) { + u1Byte gid_index = macid - 128; + pRA_Table->mu1_rate[gid_index] = rate; + } + pre_rate = pRA_Table->link_tx_rate[macid]; + pRA_Table->link_tx_rate[macid] = rate; + + /*trigger power training*/ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + + rate_order = phydm_rate_order_compute(pDM_Odm, rate_idx); + + if ((pDM_Odm->bOneEntryOnly) || + ((rate_order > pRA_Table->highest_client_tx_order) && (pRA_Table->power_tracking_flag == 1)) + ) { + phydm_update_pwr_track(pDM_Odm, rate_idx); + pRA_Table->power_tracking_flag = 0; + } + + #endif + + /*trigger dynamic rate ID*/ + #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) + phydm_update_rate_id(pDM_Odm, rate, macid); + #endif + +} + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID +) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pRA_Table->PT_collision_pre = TRUE; /*used in ODM_DynamicARFBSelect(WIN only)*/ + + pHalData->UndecoratedSmoothedPWDB = -1; + pHalData->ra_rpt_linked = FALSE; + #endif + + pRA_Table->firstconnect = FALSE; + + +#endif +} + +VOID +ODM_RAPostActionOnAssoc( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +/* + pDM_Odm->H2C_RARpt_connect = 1; + odm_RSSIMonitorCheck(pDM_Odm); + pDM_Odm->H2C_RARpt_connect = 0; +*/ +} + +VOID +phydm_initRaInfo( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) { + u4Byte ret_value; + + ret_value = ODM_GetBBReg(pDM_Odm, 0x4c8, bMaskByte2); + ODM_SetBBReg(pDM_Odm, 0x4cc, bMaskByte3, (ret_value - 1)); + } +#endif +} + +VOID +phydm_modify_RA_PCR_threshold( + IN PVOID pDM_VOID, + IN u1Byte RA_offset_direction, + IN u1Byte RA_threshold_offset + +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->RA_offset_direction = RA_offset_direction; + pRA_Table->RA_threshold_offset = RA_threshold_offset; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); +} + +VOID +odm_RSSIMonitorCheckMP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; + u4Byte i; + BOOLEAN bExtRAInfo = TRUE; + u1Byte cmdlen = H2C_0X42_LENGTH; + u1Byte TxBF_EN = 0, stbc_en = 0; + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PSTA_INFO_T pEntry = NULL; + s4Byte tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PMGNT_INFO pDefaultMgntInfo = &Adapter->MgntInfo; + u8Byte curTxOkCnt = 0, curRxOkCnt = 0; +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE; +#endif +#endif + PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); + + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + bExtRAInfo = FALSE; + cmdlen = 3; + } + + while (pLoopAdapter) { + + if (pLoopAdapter != NULL) { + pMgntInfo = &pLoopAdapter->MgntInfo; + curTxOkCnt = pLoopAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; + curRxOkCnt = pLoopAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; + pMgntInfo->lastTxOkCnt = curTxOkCnt; + pMgntInfo->lastRxOkCnt = curRxOkCnt; + } + + for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { + + if (IsAPModeExist(pLoopAdapter)) { + if (GetFirstExtAdapter(pLoopAdapter) != NULL && + GetFirstExtAdapter(pLoopAdapter) == pLoopAdapter) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + else if (GetFirstGOPort(pLoopAdapter) != NULL && + IsFirstGoAdapter(pLoopAdapter)) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + } else { + if (GetDefaultAdapter(pLoopAdapter) == pLoopAdapter) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + } + + if (pEntry != NULL) { + if (pEntry->bAssociated) { + + RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); + RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", + pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + + //2 BF_en +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->AssociatedMacId); + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; +#else + if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), pEntry)) + TxBF_EN = 1; +#endif +#endif + //2 STBC_en + if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")),pRA_Table->RA_threshold_offset)); + + if (bExtRAInfo) { + if (curRxOkCnt > (curTxOkCnt * 6)) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + if (pDM_Odm->NoisyDecision) + H2C_Parameter[3] |= RAINFO_NOISY_STATE; + else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + #if 1 + if (pDM_Odm->H2C_RARpt_connect) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); + } + #else + + if (pEntry->rssi_stat.ra_rpt_linked == FALSE) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + pEntry->rssi_stat.ra_rpt_linked = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", + pEntry->AssociatedMacId, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + } + #endif + } + + H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF); + //H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 + H2C_Parameter[0] = (pEntry->AssociatedMacId); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } + } else + break; + } + + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } + + + /*Default port*/ + if (tmpEntryMaxPWDB != 0) { // If associated entry is found + pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmpEntryMaxPWDB, tmpEntryMaxPWDB)); + } else + pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + + if (tmpEntryMinPWDB != 0xff) { // If associated entry is found + pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB)); + + } else + pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + + /* Default porti sent RSSI to FW */ + if (pHalData->bUseRAMask) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); + if (pHalData->UndecoratedSmoothedPWDB > 0) { + + PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pDefaultMgntInfo); + PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pDefaultMgntInfo); + + /* BF_en*/ + #if (BEAMFORMING_SUPPORT == 1) + #ifndef BEAMFORMING_VERSION_1 + Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pDefaultMgntInfo->mMacId); + + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; + #else + if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), NULL)) + TxBF_EN = 1; + #endif + #endif + + /* STBC_en*/ + if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); + + if (bExtRAInfo) { + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + #if 1 + if (pDM_Odm->H2C_RARpt_connect) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); + } + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); + + if (pHalData->ra_rpt_linked == FALSE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); + + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + pHalData->ra_rpt_linked = TRUE; + + + } + #endif + + if (pDM_Odm->NoisyDecision == 1) { + H2C_Parameter[3] |= RAINFO_NOISY_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); + } else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] H2C_Parameter=%x\n", H2C_Parameter[3])); + } + + H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); + /*H2C_Parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + H2C_Parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } + + // BT 3.0 HS mode Rssi + if (pDM_Odm->bBtHsOperation) { + H2C_Parameter[2] = pDM_Odm->btHsRssi; + //H2C_Parameter[1] = 0x0; + H2C_Parameter[0] = WIN_BT_PORT_MACID; + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } + } else + PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); + + if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8192E)) + odm_RSSIDumpToRegister(pDM_Odm); + + + { + PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); + BOOLEAN default_pointer_value, *pbLink_temp = &default_pointer_value; + s4Byte GlobalRSSI_min = 0xFF, LocalRSSI_Min; + BOOLEAN bLink = FALSE; + + while (pLoopAdapter) { + LocalRSSI_Min = phydm_FindMinimumRSSI(pDM_Odm, pLoopAdapter, pbLink_temp); + //DbgPrint("pHalData->bLinked=%d, LocalRSSI_Min=%d\n", pHalData->bLinked, LocalRSSI_Min); + + if (*pbLink_temp) + bLink = TRUE; + + if ((LocalRSSI_Min < GlobalRSSI_min) && (*pbLink_temp)) + GlobalRSSI_min = LocalRSSI_Min; + + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } + + pHalData->bLinked = bLink; + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc , ODM_CMNINFO_LINK, (u8Byte)bLink); + + if (bLink) + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u8Byte)GlobalRSSI_min); + else + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); + + } + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*H2C_RSSI_REPORT*/ +s8 phydm_rssi_report(PDM_ODM_T pDM_Odm, u8 mac_id) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 H2C_Parameter[4] = {0}; + u8 UL_DL_STATE = 0, STBC_TX = 0, TxBF_EN = 0; + u8 cmdlen = 4, first_connect = _FALSE; + u64 curTxOkCnt = 0, curRxOkCnt = 0; + PSTA_INFO_T pEntry = pDM_Odm->pODM_StaInfo[mac_id]; + + if (!IS_STA_VALID(pEntry)) + return _FAIL; + + if (mac_id != pEntry->mac_id) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, pEntry->mac_id)); + rtw_warn_on(1); + return _FAIL; + } + + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + return _FAIL; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, pEntry->mac_id, MAC_ARG(pEntry->hwaddr))); + return _FAIL; + } + + curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes; + curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes; + if (curRxOkCnt > (curTxOkCnt * 6)) + UL_DL_STATE = 1; + else + UL_DL_STATE = 0; + + #ifdef CONFIG_BEAMFORMING + { + #if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->mac_id); + #else/*for drv beamforming*/ + BEAMFORMING_CAP Beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&Adapter->mlmepriv, pEntry->mac_id); + #endif + + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; + else + TxBF_EN = 0; + } + #endif /*#ifdef CONFIG_BEAMFORMING*/ + + if (TxBF_EN) + STBC_TX = 0; + else { + #ifdef CONFIG_80211AC_VHT + if (IsSupportedVHT(pEntry->wireless_mode)) + STBC_TX = TEST_FLAG(pEntry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); + else + #endif + STBC_TX = TEST_FLAG(pEntry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); + } + + H2C_Parameter[0] = (u8)(pEntry->mac_id & 0xFF); + H2C_Parameter[2] = pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F; + + if (UL_DL_STATE) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + if (STBC_TX) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + if (pDM_Odm->NoisyDecision) + H2C_Parameter[3] |= RAINFO_NOISY_STATE; + + if ((pEntry->ra_rpt_linked == _FALSE) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_SEND)) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + pEntry->ra_rpt_linked = _TRUE; + pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_HOLD; + first_connect = _TRUE; + } + + #if 1 + if (first_connect) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, + pEntry->mac_id, MAC_ARG(pEntry->hwaddr), pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, + (UL_DL_STATE) ? "DL" : "UL", (TxBF_EN) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", + (pDM_Odm->NoisyDecision) ? "True" : "False", (first_connect) ? "True" : "False")); + } + #endif + + if (pHalData->fw_ractrl == _TRUE) { + #if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + cmdlen = 3; + #endif + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } else { + #if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + ODM_RA_SetRSSI_8188E(pDM_Odm, (u8)(pEntry->mac_id & 0xFF), pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F); + #endif + } + return _SUCCESS; +} + +void phydm_ra_rssi_rpt_wk_hdl(PVOID pContext) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; + int i; + u8 mac_id = 0xFF; + PSTA_INFO_T pEntry = NULL; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + if (pEntry->ra_rpt_linked == _FALSE) { + mac_id = i; + break; + } + } + } + if (mac_id != 0xFF) + phydm_rssi_report(pDM_Odm, mac_id); +} +void phydm_ra_rssi_rpt_wk(PVOID pContext) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; + + rtw_run_in_thread_cmd(pDM_Odm->Adapter, phydm_ra_rssi_rpt_wk_hdl, pDM_Odm); +} +#endif + +VOID +odm_RSSIMonitorCheckCE( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PSTA_INFO_T pEntry; + int i; + int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + u8 sta_cnt = 0; + + if (pDM_Odm->bLinked != _TRUE) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) + continue; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (phydm_rssi_report(pDM_Odm, i)) + sta_cnt++; + } + } + + if (tmpEntryMaxPWDB != 0) // If associated entry is found + pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + else + pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + + if (tmpEntryMinPWDB != 0xff) // If associated entry is found + pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + else + pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + + FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM + + pDM_Odm->RSSI_Min = pHalData->MinUndecoratedPWDBForDM; + //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); +#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) +} + + +VOID +odm_RSSIMonitorCheckAP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; + u4Byte i; + BOOLEAN bExtRAInfo = TRUE; + u1Byte cmdlen = H2C_0X42_LENGTH; + u1Byte TxBF_EN = 0, stbc_en = 0; + + prtl8192cd_priv priv = pDM_Odm->priv; + PSTA_INFO_T pstat; + BOOLEAN act_bfer = FALSE; + +#if (BEAMFORMING_SUPPORT == 1) + u1Byte Idx=0xff; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + pDM_BdcTable->num_Txbfee_Client = 0; + pDM_BdcTable->num_Txbfer_Client = 0; +#endif +#endif + if (!pDM_Odm->H2C_RARpt_connect && (priv->up_time % 2)) + return; + + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + bExtRAInfo = FALSE; + cmdlen = 3; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pstat = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pstat)) { + if (pstat->sta_in_firmware != 1) + continue; + + //2 BF_en + #if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP Beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); + PRT_BEAMFORMING_ENTRY pEntry = Beamforming_GetEntryByMacId(priv, pstat->aid, &Idx); + + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + + if (pEntry->Sounding_En) + TxBF_EN = 1; + else + TxBF_EN = 0; + + act_bfer = TRUE; + } + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ + if (act_bfer == TRUE) { + pDM_BdcTable->w_BFee_Client[i] = 1; //AP act as BFer + pDM_BdcTable->num_Txbfee_Client++; + } else { + pDM_BdcTable->w_BFee_Client[i] = 0; //AP act as BFer + } + + if ((Beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (Beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { + pDM_BdcTable->w_BFer_Client[i] = 1; //AP act as BFee + pDM_BdcTable->num_Txbfer_Client++; + } else { + pDM_BdcTable->w_BFer_Client[i] = 0; //AP act as BFer + } + #endif + #endif + + //2 STBC_en + if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && + ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) + #ifdef RTK_AC_SUPPORT + || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) + #endif + )) + stbc_en = 1; + + //2 RAINFO + + if (bExtRAInfo) { + if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + if (pDM_Odm->NoisyDecision) + H2C_Parameter[3] |= RAINFO_NOISY_STATE; + else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + + if (pstat->H2C_rssi_rpt) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); + } + + /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",H2C_Parameter[3]));*/ + } + + H2C_Parameter[2] = (u1Byte)(pstat->rssi & 0xFF); + H2C_Parameter[0] = REMAP_AID(pstat); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("H2C_Parameter[3]=%d\n", H2C_Parameter[3])); + + //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x, \n",H2C_Parameter[2])); + //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x, \n",H2C_Parameter[0])); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + + } + } + +#endif +#endif + +} + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + return; + + switch (pDM_Odm->SupportPlatform) { + case ODM_WIN: + odm_RSSIMonitorCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_RSSIMonitorCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_RSSIMonitorCheckAP(pDM_Odm); + break; + + default: + break; + } + +} + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + + pMgntInfo->Ratr_State = DM_RATR_STA_INIT; + + if (pMgntInfo->DM_Type == DM_Type_ByDriver) + pHalData->bUseRAMask = TRUE; + else + pHalData->bUseRAMask = FALSE; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pOdmRA->Type = DM_Type_ByDriver; + if (pOdmRA->Type == DM_Type_ByDriver) + pDM_Odm->bUseRAMask = _TRUE; + else + pDM_Odm->bUseRAMask = _FALSE; +#endif + + pOdmRA->RATRState = DM_RATR_STA_INIT; + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8812) + pOdmRA->LdpcThres = 50; + else + pOdmRA->LdpcThres = 35; + + pOdmRA->RtsThres = 35; + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + pOdmRA->LdpcThres = 35; + pOdmRA->bUseLdpc = FALSE; + +#else + pOdmRA->UltraLowRSSIThresh = 9; + +#endif + + pOdmRA->HighRSSIThresh = 50; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pOdmRA->LowRSSIThresh = 23; +#else + pOdmRA->LowRSSIThresh = 20; +#endif +} +/*----------------------------------------------------------------------------- + * Function: odm_RefreshRateAdaptiveMask() + * + * Overview: Update rate table mask according to rssi + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/27/2009 hpfan Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (!pDM_Odm->bLinked) + return; + + if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n")); + return; + } + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) { + case ODM_WIN: + odm_RefreshRateAdaptiveMaskMP(pDM_Odm); + break; + + case ODM_CE: + odm_RefreshRateAdaptiveMaskCE(pDM_Odm); + break; + + case ODM_AP: + odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); + break; + } + +} + +u1Byte +phydm_trans_platform_bw( + IN PVOID pDM_VOID, + IN u1Byte BW +) +{ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (BW == CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == CHANNEL_WIDTH_40) + BW = PHYDM_BW_40; + + else if (BW == CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == CHANNEL_WIDTH_80_80) + BW = PHYDM_BW_80_80; + + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + if (BW == HT_CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == HT_CHANNEL_WIDTH_20_40) + BW = PHYDM_BW_40; + + else if (BW == HT_CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == HT_CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == HT_CHANNEL_WIDTH_10) + BW = PHYDM_BW_10; + + else if (BW == HT_CHANNEL_WIDTH_5) + BW = PHYDM_BW_5; + + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (BW == CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == CHANNEL_WIDTH_40) + BW = PHYDM_BW_40; + + else if (BW == CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == CHANNEL_WIDTH_80_80) + BW = PHYDM_BW_80_80; + #endif + + return BW; + +} + +u1Byte +phydm_trans_platform_rf_type( + IN PVOID pDM_VOID, + IN u1Byte RfType +) +{ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (RfType == RF_1T2R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == RF_2T4R) + RfType = PHYDM_RF_2T4R; + + else if (RfType == RF_2T2R) + RfType = PHYDM_RF_2T2R; + + else if (RfType == RF_1T1R) + RfType = PHYDM_RF_1T1R; + + else if (RfType == RF_2T2R_GREEN) + RfType = PHYDM_RF_2T2R_GREEN; + + else if (RfType == RF_3T3R) + RfType = PHYDM_RF_3T3R; + + else if (RfType == RF_4T4R) + RfType = PHYDM_RF_4T4R; + + else if (RfType == RF_2T3R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == RF_3T4R) + RfType = PHYDM_RF_3T4R; + + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + if (RfType == MIMO_1T2R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == MIMO_2T4R) + RfType = PHYDM_RF_2T4R; + + else if (RfType == MIMO_2T2R) + RfType = PHYDM_RF_2T2R; + + else if (RfType == MIMO_1T1R) + RfType = PHYDM_RF_1T1R; + + else if (RfType == MIMO_3T3R) + RfType = PHYDM_RF_3T3R; + + else if (RfType == MIMO_4T4R) + RfType = PHYDM_RF_4T4R; + + else if (RfType == MIMO_2T3R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == MIMO_3T4R) + RfType = PHYDM_RF_3T4R; + + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (RfType == RF_1T2R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == RF_2T4R) + RfType = PHYDM_RF_2T4R; + + else if (RfType == RF_2T2R) + RfType = PHYDM_RF_2T2R; + + else if (RfType == RF_1T1R) + RfType = PHYDM_RF_1T1R; + + else if (RfType == RF_2T2R_GREEN) + RfType = PHYDM_RF_2T2R_GREEN; + + else if (RfType == RF_3T3R) + RfType = PHYDM_RF_3T3R; + + else if (RfType == RF_4T4R) + RfType = PHYDM_RF_4T4R; + + else if (RfType == RF_2T3R) + RfType = PHYDM_RF_1T2R; + + else if (RfType == RF_3T4R) + RfType = PHYDM_RF_3T4R; + + #endif + + return RfType; + +} + +u4Byte +phydm_trans_platform_wireless_mode( + IN PVOID pDM_VOID, + IN u4Byte wireless_mode +) +{ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (wireless_mode == WIRELESS_11A) + wireless_mode = PHYDM_WIRELESS_MODE_A; + + else if (wireless_mode == WIRELESS_11B) + wireless_mode = PHYDM_WIRELESS_MODE_B; + + else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) + wireless_mode = PHYDM_WIRELESS_MODE_G; + + else if (wireless_mode == WIRELESS_AUTO) + wireless_mode = PHYDM_WIRELESS_MODE_AUTO; + + else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || + (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) + wireless_mode = PHYDM_WIRELESS_MODE_N_24G; + + else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) + wireless_mode = PHYDM_WIRELESS_MODE_N_5G; + + else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) + wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; + + else if (wireless_mode == WIRELESS_11_24AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; + + else if (wireless_mode == WIRELESS_11AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; + + else if (wireless_mode == WIRELESS_MODE_MAX) + wireless_mode = PHYDM_WIRELESS_MODE_MAX; + else + wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; + #endif + + return wireless_mode; + +} + +u1Byte +phydm_vht_en_mapping( + IN PVOID pDM_VOID, + IN u4Byte WirelessMode +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte vht_en_out = 0; + + if ((WirelessMode == PHYDM_WIRELESS_MODE_AC_5G) || + (WirelessMode == PHYDM_WIRELESS_MODE_AC_24G) || + (WirelessMode == PHYDM_WIRELESS_MODE_AC_ONLY) + ) { + vht_en_out = 1; + /**/ + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("WirelessMode= (( 0x%x )), VHT_EN= (( %d ))\n", WirelessMode, vht_en_out)); + return vht_en_out; +} + +u1Byte +phydm_rate_id_mapping( + IN PVOID pDM_VOID, + IN u4Byte WirelessMode, + IN u1Byte RfType, + IN u1Byte bw +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte rate_id_idx = 0; + u1Byte phydm_BW; + u1Byte phydm_RfType; + + phydm_BW = phydm_trans_platform_bw(pDM_Odm, bw); + phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + WirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, WirelessMode); + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x ))\n", + WirelessMode, phydm_RfType, phydm_BW)); + + + switch (WirelessMode) { + + case PHYDM_WIRELESS_MODE_N_24G: + { + + if (phydm_BW == PHYDM_BW_40) { + + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (phydm_RfType == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_40M_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + + } else { + + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (phydm_RfType == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_20M_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + } + break; + + case PHYDM_WIRELESS_MODE_N_5G: + { + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_GN_N1SS; + else if (phydm_RfType == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_GN_N2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + + break; + + case PHYDM_WIRELESS_MODE_G: + rate_id_idx = PHYDM_BG; + break; + + case PHYDM_WIRELESS_MODE_A: + rate_id_idx = PHYDM_G; + break; + + case PHYDM_WIRELESS_MODE_B: + rate_id_idx = PHYDM_B_20M; + break; + + + case PHYDM_WIRELESS_MODE_AC_5G: + case PHYDM_WIRELESS_MODE_AC_ONLY: + { + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (phydm_RfType == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } + break; + + case PHYDM_WIRELESS_MODE_AC_24G: + { + if (phydm_BW >= PHYDM_BW_80) { + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (phydm_RfType == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } else { + + if (phydm_RfType == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + } + } + break; + + default: + rate_id_idx = 0; + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA Rate ID = (( 0x%d ))\n", rate_id_idx)); + + return rate_id_idx; +} + +VOID +phydm_UpdateHalRAMask( + IN PVOID pDM_VOID, + IN u4Byte wirelessMode, + IN u1Byte RfType, + IN u1Byte BW, + IN u1Byte MimoPs_enable, + IN u1Byte disable_cck_rate, + IN u4Byte *ratr_bitmap_msb_in, + IN u4Byte *ratr_bitmap_lsb_in, + IN u1Byte tx_rate_level + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte mask_rate_threshold; + u1Byte phydm_RfType; + u1Byte phydm_BW; + u4Byte ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; + /*PODM_RATE_ADAPTIVE pRA = &(pDM_Odm->RateAdaptive);*/ + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + wirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, wirelessMode); + #endif + + phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); + phydm_BW = phydm_trans_platform_bw(pDM_Odm, BW); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_RfType = (( %x )), RfType = (( %x ))\n", phydm_RfType, RfType));*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); + + if (MimoPs_enable) + phydm_RfType = PHYDM_RF_1T1R; + + switch (wirelessMode) { + + case PHYDM_WIRELESS_MODE_B: + { + ratr_bitmap &= 0x0000000f; + } + break; + + case PHYDM_WIRELESS_MODE_G: + { + ratr_bitmap &= 0x00000ff5; + } + break; + + case PHYDM_WIRELESS_MODE_A: + { + ratr_bitmap &= 0x00000ff0; + } + break; + + case PHYDM_WIRELESS_MODE_N_24G: + case PHYDM_WIRELESS_MODE_N_5G: + { + if (phydm_RfType == PHYDM_RF_1T1R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x000ff015; + else + ratr_bitmap &= 0x000ff005; + } else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x0ffff015; + else + ratr_bitmap &= 0x0ffff005; + } else { /*3T*/ + + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; + } + } + break; + + case PHYDM_WIRELESS_MODE_AC_24G: + { + if (phydm_RfType == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff015; + else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff015; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; + + case PHYDM_WIRELESS_MODE_AC_5G: + { + if (phydm_RfType == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff010; + else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff010; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; + + default: + break; + } + + if (wirelessMode != PHYDM_WIRELESS_MODE_B) { + + if (tx_rate_level == 0) + ratr_bitmap &= 0xffffffff; + else if (tx_rate_level == 1) + ratr_bitmap &= 0xfffffff0; + else if (tx_rate_level == 2) + ratr_bitmap &= 0xffffefe0; + else if (tx_rate_level == 3) + ratr_bitmap &= 0xffffcfc0; + else if (tx_rate_level == 4) + ratr_bitmap &= 0xffff8f80; + else if (tx_rate_level >= 5) + ratr_bitmap &= 0xffff0f00; + + } + + if (disable_cck_rate) + ratr_bitmap &= 0xfffffff0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%d ))\n", + wirelessMode, phydm_RfType, phydm_BW, MimoPs_enable, tx_rate_level)); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ + + *ratr_bitmap_lsb_in = ratr_bitmap; + *ratr_bitmap_msb_in = ratr_bitmap_msb; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); + +} + +u1Byte +phydm_RA_level_decision( + IN PVOID pDM_VOID, + IN u4Byte rssi, + IN u1Byte Ratr_State + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ra_lowest_rate; + u1Byte ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u1Byte new_Ratr_State = 0; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", Ratr_State, + ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + + if (i >= (Ratr_State)) + ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", + rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + + if (rssi < ra_rate_floor_table[i]) { + new_Ratr_State = i; + break; + } + } + + + + return new_Ratr_State; + +} + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + PADAPTER pTargetAdapter = NULL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); + u4Byte i; + PSTA_INFO_T pEntry; + u1Byte Ratr_State_new; + + if (pAdapter->bDriverStopped) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if (!pHalData->bUseRAMask) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + // if default port is connected, update RA table for default port (infrastructure mode only) + if (pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter))) { + odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pMgntInfo->mMacId, pMgntInfo->IOTPeer, pHalData->UndecoratedSmoothedPWDB); + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture Mode\n"));*/ + + #if RA_MASK_PHYDMLIZE_WIN + Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State); + + if (pMgntInfo->Ratr_State != Ratr_State_new) { + + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", + pMgntInfo->Ratr_State, Ratr_State_new, pHalData->UndecoratedSmoothedPWDB)); + + pMgntInfo->Ratr_State = Ratr_State_new; + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, Ratr_State_new); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + /**/ + } + + #else + if (ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } else if (pDM_Odm->bChangeState) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } + #endif + } + + // + // The following part configure AP/VWifi/IBSS rate adaptive mask. + // + + if (pMgntInfo->mIbss) // Target: AP/IBSS peer. + pTargetAdapter = GetDefaultAdapter(pAdapter); + else + pTargetAdapter = GetFirstAPAdapter(pAdapter); + + // if extension port (softap) is started, updaet RA table for more than one clients associate + if (pTargetAdapter != NULL) { + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + + pEntry = AsocEntry_EnumStation(pTargetAdapter, i); + + if (IS_STA_VALID(pEntry)) { + + odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pEntry->AssociatedMacId, pEntry->IOTPeer, pEntry->rssi_stat.UndecoratedSmoothedPWDB); + + #if RA_MASK_PHYDMLIZE_WIN + Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State); + + if (pEntry->Ratr_State != Ratr_State_new) { + + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->MacAddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + pEntry->Ratr_State, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + + pEntry->Ratr_State = Ratr_State_new; + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pEntry->AssociatedMacId, NULL, Ratr_State_new); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + /**/ + } + + + #else + + if (ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State); + } else if (pDM_Odm->bChangeState) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } + #endif + + } + } + } + + #if RA_MASK_PHYDMLIZE_WIN + + #else + if (pMgntInfo->bSetTXPowerTrainingByOid) + pMgntInfo->bSetTXPowerTrainingByOid = FALSE; + #endif +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +} + + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + u4Byte i; + PSTA_INFO_T pEntry; + u1Byte Ratr_State_new; + + if (RTW_CANNOT_RUN(pAdapter)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if (!pDM_Odm->bUseRAMask) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + + pEntry = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pEntry)) { + + if (IS_MCAST(pEntry->hwaddr)) + continue; + + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8821)) { + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres) { + pRA->bUseLdpc = TRUE; + pRA->bLowerRtsRate = TRUE; + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + Set_RA_LDPC_8812(pEntry, TRUE); + //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB); + } else if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres - 5)) { + pRA->bUseLdpc = FALSE; + pRA->bLowerRtsRate = FALSE; + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + Set_RA_LDPC_8812(pEntry, FALSE); + //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB); + } + } + #endif + + #if RA_MASK_PHYDMLIZE_CE + Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level); + + if (pEntry->rssi_level != Ratr_State_new) { + + /*ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + pEntry->rssi_level, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + + pEntry->rssi_level = Ratr_State_new; + rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + /**/ + } + #else + if (TRUE == ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pEntry->rssi_level)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level)); + //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); + rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); + } else if (pDM_Odm->bChangeState) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); + } + #endif + + } + } + +#endif +} + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct rtl8192cd_priv *priv = pDM_Odm->priv; + struct aid_obj *aidarray; + u4Byte i; + PSTA_INFO_T pEntry; + u1Byte Ratr_State_new; + + if (priv->up_time % 2) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pEntry)) { + + #if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + aidarray = container_of(pEntry, struct aid_obj, station); + priv = aidarray->priv; + #endif + + if (!priv->pmib->dot11StationConfigEntry.autoRate) + continue; + +#if RA_MASK_PHYDMLIZE_AP + Ratr_State_new = phydm_RA_level_decision(pDM_Odm, (u4Byte)pEntry->rssi, pEntry->rssi_level); + + if (pEntry->rssi_level != Ratr_State_new) { + + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->hwaddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", pEntry->rssi_level, Ratr_State_new, pEntry->rssi)); + + pEntry->rssi_level = Ratr_State_new; + phydm_gen_ramask_h2c_AP(pDM_Odm, priv, pEntry, pEntry->rssi_level); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + /**/ + } + +#else + if (ODM_RAStateCheck(pDM_Odm, (s4Byte)pEntry->rssi, FALSE, &pEntry->rssi_level)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->hwaddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi, pEntry->rssi_level)); + + #ifdef CONFIG_WLAN_HAL + if (IS_HAL_CHIP(priv)) { + #ifdef WDS + /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ + #endif + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, pEntry->rssi_level); + } else + #endif + + #ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8812E) + UpdateHalRAMask8812(priv, pEntry, 3); + else + #endif + { + #ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8188E) { + #ifdef TXREPORT + add_RATid(priv, pEntry); + #endif + } + #endif + + + } + } +#endif /*#ifdef RA_MASK_PHYDMLIZE*/ + + } + } +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/ +} + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + static u1Byte Stage = 0; + u1Byte CurStage = 0; + OCTET_STRING osRateSet; + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); + u1Byte RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; + + if (pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821) + return; + + if (pDM_Odm->bLinked == FALSE) // unlink Default port information + CurStage = 0; + else if (pDM_Odm->RSSI_Min < 40) // link RSSI < 40% + CurStage = 1; + else if (pDM_Odm->RSSI_Min > 45) // link RSSI > 45% + CurStage = 3; + else + CurStage = 2; // link 25% <= RSSI <= 30% + + if (CurStage != Stage) { + if (CurStage == 1) { + FillOctetString(osRateSet, RateSet, 5); + FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE); + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet); + } else if (CurStage == 3 && (Stage == 1 || Stage == 2)) + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates)); + } + + Stage = CurStage; +#endif +} + +u1Byte +phydm_rate_order_compute( + IN PVOID pDM_VOID, + IN u1Byte rate_idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte rate_order = 0; + + if (rate_idx >= ODM_RATEVHTSS4MCS0) { + + rate_idx -= ODM_RATEVHTSS4MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { + + rate_idx -= ODM_RATEVHTSS3MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { + + rate_idx -= ODM_RATEVHTSS2MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + + rate_idx -= ODM_RATEVHTSS1MCS0; + /**/ + } else if (rate_idx >= ODM_RATEMCS24) { + + rate_idx -= ODM_RATEMCS24; + /**/ + } else if (rate_idx >= ODM_RATEMCS16) { + + rate_idx -= ODM_RATEMCS16; + /**/ + } else if (rate_idx >= ODM_RATEMCS8) { + + rate_idx -= ODM_RATEMCS8; + /**/ + } + rate_order = rate_idx; + + return rate_order; + +} + +VOID +phydm_ra_common_info_update( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u2Byte macid; + u1Byte rate_order_tmp; + u1Byte cnt = 0; + + pRA_Table->highest_client_tx_order = 0; + pRA_Table->power_tracking_flag = 1; + + if (pDM_Odm->number_linked_client != 0) { + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + + rate_order_tmp = phydm_rate_order_compute(pDM_Odm, ((pRA_Table->link_tx_rate[macid]) & 0x7f)); + + if (rate_order_tmp >= (pRA_Table->highest_client_tx_order)) { + pRA_Table->highest_client_tx_order = rate_order_tmp; + pRA_Table->highest_client_tx_rate_order = macid; + } + + cnt++; + + if (cnt == pDM_Odm->number_linked_client) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (pRA_Table->highest_client_tx_rate_order), (pRA_Table->highest_client_tx_order))); + } +} + +VOID +phydm_ra_info_watchdog( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + phydm_ra_common_info_update(pDM_Odm); + phydm_ra_dynamic_retry_limit(pDM_Odm); + phydm_ra_dynamic_retry_count(pDM_Odm); + odm_RefreshRateAdaptiveMask(pDM_Odm); + odm_RefreshBasicRateMask(pDM_Odm); +} + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->highest_client_tx_rate_order = 0; + pRA_Table->highest_client_tx_order = 0; + pRA_Table->RA_threshold_offset = 0; + pRA_Table->RA_offset_direction = 0; + + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + phydm_ra_dynamic_retry_limit_init(pDM_Odm); + #endif + + #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) + phydm_ra_dynamic_rate_id_init(pDM_Odm); + #endif + #if (defined(CONFIG_RA_DBG_CMD)) + odm_RA_ParaAdjust_init(pDM_Odm); + #endif + +} + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +u1Byte +odm_Find_RTS_Rate( + IN PVOID pDM_VOID, + IN u1Byte Tx_Rate, + IN BOOLEAN bErpProtect +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte RTS_Ini_Rate = ODM_RATE6M; + + if (bErpProtect) /* use CCK rate as RTS*/ + RTS_Ini_Rate = ODM_RATE1M; + else { + switch (Tx_Rate) { + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + RTS_Ini_Rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + RTS_Ini_Rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + RTS_Ini_Rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + RTS_Ini_Rate = ODM_RATE1M; + break; + default: + RTS_Ini_Rate = ODM_RATE6M; + break; + } + } + + if (*pDM_Odm->pBandType == 1) { + if (RTS_Ini_Rate < ODM_RATE6M) + RTS_Ini_Rate = ODM_RATE6M; + } + return RTS_Ini_Rate; + +} + +VOID +odm_Set_RA_DM_ARFB_by_Noisy( + IN PDM_ODM_T pDM_Odm +) +{ +#if 0 + + /*DbgPrint("DM_ARFB ====>\n");*/ + if (pDM_Odm->bNoisyState) { + ODM_Write4Byte(pDM_Odm, 0x430, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0x434, 0x05040200); + /*DbgPrint("DM_ARFB ====> Noisy State\n");*/ + } else { + ODM_Write4Byte(pDM_Odm, 0x430, 0x02010000); + ODM_Write4Byte(pDM_Odm, 0x434, 0x07050403); + /*DbgPrint("DM_ARFB ====> Clean State\n");*/ + } +#endif +} + +VOID +ODM_UpdateNoisyState( + IN PVOID pDM_VOID, + IN BOOLEAN bNoisyStateFromC2H +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);*/ + if (pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || + pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723D) + pDM_Odm->bNoisyState = bNoisyStateFromC2H; + odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm); +}; + +VOID +phydm_update_pwr_track( + IN PVOID pDM_VOID, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte pathIdx = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get Rate=0x%x\n", Rate)); + + pDM_Odm->TxRate = Rate; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); + #else + if (pDM_Odm->SupportICType == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + #endif + } else if (pDM_Odm->SupportICType == ODM_RTL8812) { + for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8812A; pathIdx++) { + #if (RTL8812A_SUPPORT == 1) + ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, pathIdx, 0); + #endif + } + } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { + #if (RTL8723B_SUPPORT == 1) + ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + #endif + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8192E; pathIdx++) { + #if (RTL8192E_SUPPORT == 1) + ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, pathIdx, 0); + #endif + } + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + #endif + } + #endif + #else + PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); + #endif + #endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +s4Byte +phydm_FindMinimumRSSI( +IN PDM_ODM_T pDM_Odm, +IN PADAPTER pAdapter, +IN OUT BOOLEAN *pbLink_temp + + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + BOOLEAN act_as_ap = ACTING_AS_AP(pAdapter); + + /* 1.Determine the minimum RSSI */ + if ((!pMgntInfo->bMediaConnect) || + (act_as_ap && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ + + pHalData->MinUndecoratedPWDBForDM = 0; + *pbLink_temp = FALSE; + + } else + *pbLink_temp = TRUE; + + + if (pMgntInfo->bMediaConnect) { /* Default port*/ + + if (act_as_ap || pMgntInfo->mIbss) { + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /**/ + } else { + pHalData->MinUndecoratedPWDBForDM = pHalData->UndecoratedSmoothedPWDB; + /**/ + } + } else { /* associated entry pwdb*/ + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /**/ + } + + return pHalData->MinUndecoratedPWDBForDM; +} + +VOID +ODM_UpdateInitRateWorkItemCallback( + IN PVOID pContext +) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + u1Byte p = 0; + + if (pDM_Odm->SupportICType == ODM_RTL8821) { + ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + /**/ + } else if (pDM_Odm->SupportICType == ODM_RTL8812) { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ + + ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0); + /**/ + } + } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { + ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + /**/ + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ + ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0); + /**/ + } + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { + ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + /**/ + } +} + +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (pDM_Odm->SupportICType == ODM_RTL8812) { + PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]); + + /* Rx EVM*/ + PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]); + + /* Rx SNR*/ + PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + + /* Rx Cfo_Short*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]); + + /* Rx Cfo_Tail*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]); + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]); + /* Rx EVM*/ + PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]); + /* Rx SNR*/ + PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + /* Rx Cfo_Short*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]); + /* Rx Cfo_Tail*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]); + } +} + +VOID +odm_RefreshLdpcRtsMP( + IN PADAPTER pAdapter, + IN PDM_ODM_T pDM_Odm, + IN u1Byte mMacId, + IN u1Byte IOTPeer, + IN s4Byte UndecoratedSmoothedPWDB +) +{ + BOOLEAN bCtlLdpc = FALSE; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + + if (pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8812) + return; + + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + bCtlLdpc = TRUE; + else if (pDM_Odm->SupportICType == ODM_RTL8812 && + IOTPeer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) + bCtlLdpc = TRUE; + + if (bCtlLdpc) { + if (UndecoratedSmoothedPWDB < (pRA->LdpcThres - 5)) + MgntSet_TX_LDPC(pAdapter, mMacId, TRUE); + else if (UndecoratedSmoothedPWDB > pRA->LdpcThres) + MgntSet_TX_LDPC(pAdapter, mMacId, FALSE); + } + + if (UndecoratedSmoothedPWDB < (pRA->RtsThres - 5)) + pRA->bLowerRtsRate = TRUE; + else if (UndecoratedSmoothedPWDB > pRA->RtsThres) + pRA->bLowerRtsRate = FALSE; +} + +#if 0 +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + if (pDM_Odm->SupportICType != ODM_RTL8192E) + return; + + if (Collision_State == pRA_Table->PT_collision_pre) + return; + + if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { + if (Collision_State == 1) { + if (rate == DESC_RATEMCS12) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501); + } else if (rate == DESC_RATEMCS11) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605); + } else if (rate == DESC_RATEMCS10) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706); + } else if (rate == DESC_RATEMCS9) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808); + } + } else { /* Collision_State == 0*/ + if (rate == DESC_RATEMCS12) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + } else if (rate == DESC_RATEMCS11) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807); + } else if (rate == DESC_RATEMCS10) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908); + } else if (rate == DESC_RATEMCS9) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909); + } + } + } else { /* MCS13~MCS15, 1SS, G-mode*/ + if (Collision_State == 1) { + if (rate == DESC_RATEMCS15) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302); + } else if (rate == DESC_RATEMCS14) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302); + } else if (rate == DESC_RATEMCS13) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402); + } + } else { // Collision_State == 0 + if (rate == DESC_RATEMCS15) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504); + } else if (rate == DESC_RATEMCS14) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + } else if (rate == DESC_RATEMCS13) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + } + } + } + pRA_Table->PT_collision_pre = Collision_State; +} +#endif + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry +) +{ + PADAPTER Adapter = (PADAPTER)PADAPTER_VOID; + pEntry->Ratr_State = DM_RATR_STA_INIT; +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +static void +FindMinimumRSSI( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + /*Determine the minimum RSSI*/ + + if ((pDM_Odm->bLinked != _TRUE) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { + pHalData->MinUndecoratedPWDBForDM = 0; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ + } else + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + + /*DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);*/ + /*ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));*/ +} + +u8Byte +PhyDM_Get_Rate_Bitmap_Ex( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u8Byte ra_mask, + IN u1Byte rssi_level, + OUT u8Byte *dm_RA_Mask, + OUT u1Byte *dm_RteID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u8Byte rate_bitmap = 0; + u1Byte WirelessMode; + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(pEntry)) + return ra_mask; + WirelessMode = pEntry->wireless_mode; + switch (WirelessMode) { + case ODM_WM_B: + if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ + rate_bitmap = 0x000000000000000d; + else + rate_bitmap = 0x000000000000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else + rate_bitmap = 0x0000000000000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000000000ff0; + else + rate_bitmap = 0x0000000000000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_B|ODM_WM_N24G): + case (ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_A|ODM_WM_N5G): { + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000000000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000000000ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x00000000000ff015; + else + rate_bitmap = 0x00000000000ff005; + } + } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000000000f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000000000f8ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x000000000f8ff015; + else + rate_bitmap = 0x000000000f8ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000f0f0f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000fcfcfe000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x0000000ffffff015; + else + rate_bitmap = 0x0000000ffffff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0x00000000fc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; + else + rate_bitmap = 0x00000000ffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000003fe000; + else + rate_bitmap = 0x00000000003ff010; + } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ + else + rate_bitmap = 0x00000000fffff010; /* All */ + } else { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ + else + rate_bitmap = 0x000003fffffff010ULL; /* All */ + } + break; + + default: + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) + rate_bitmap = 0x00000000000fffff; + else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) + rate_bitmap = 0x000000000fffffff; + else + rate_bitmap = 0x0000003fffffffffULL; + break; + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, WirelessMode, rate_bitmap)); + + return (ra_mask & rate_bitmap); +} + + +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u4Byte rate_bitmap = 0; + u1Byte WirelessMode; + //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); + + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(pEntry)) + return ra_mask; + + WirelessMode = pEntry->wireless_mode; + + switch (WirelessMode) { + case ODM_WM_B: + if (ra_mask & 0x0000000c) //11M or 5.5M enable + rate_bitmap = 0x0000000d; + else + rate_bitmap = 0x0000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else + rate_bitmap = 0x00000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000ff0; + else + rate_bitmap = 0x00000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : + case (ODM_WM_B|ODM_WM_N24G) : + case (ODM_WM_G|ODM_WM_N24G) : + case (ODM_WM_A|ODM_WM_N5G) : { + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x000ff015; + else + rate_bitmap = 0x000ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0f8ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x0f8ff015; + else + rate_bitmap = 0x0f8ff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0xfc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; + else + rate_bitmap = 0xffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (pDM_Odm->RFType == RF_1T1R) { + if (rssi_level == 1) // add by Gary for ac-series + rate_bitmap = 0x003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x003ff000; + else + rate_bitmap = 0x003ff010; + } else { + if (rssi_level == 1) // add by Gary for ac-series + rate_bitmap = 0xfe3f8000; // VHT 2SS MCS3~9 + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; // VHT 2SS MCS0~9 + else + rate_bitmap = 0xfffff010; // All + } + break; + + default: + if (pDM_Odm->RFType == RF_1T2R) + rate_bitmap = 0x000fffff; + else + rate_bitmap = 0x0fffffff; + break; + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, WirelessMode, rate_bitmap)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, WirelessMode, rate_bitmap)); + + return (ra_mask & rate_bitmap); + +} + +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +VOID +phydm_gen_ramask_h2c_AP( + IN PVOID pDM_VOID, + IN struct rtl8192cd_priv *priv, + IN PSTA_INFO_T *pEntry, + IN u1Byte rssi_level +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType == ODM_RTL8812) { + + #if (RTL8812A_SUPPORT == 1) + UpdateHalRAMask8812(priv, pEntry, rssi_level); + /**/ + #endif + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { + + #if (RTL8188E_SUPPORT == 1) + #ifdef TXREPORT + add_RATid(priv, pEntry); + /**/ + #endif + #endif + } else { + + #ifdef CONFIG_WLAN_HAL + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, rssi_level); + #endif + } +} + + +#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + + +/* RA_MASK_PHYDMLIZE, will delete it later*/ + +#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) + +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + const u1Byte GoUpGap = 5; + u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; + u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; + u1Byte RATRState; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *pRATRState)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); + /* Threshold Adjustment:*/ + /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ + /* Here GoUpGap is added to solve the boundary's level alternation issue.*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u1Byte UltraLowRSSIThreshForRA = pRA->UltraLowRSSIThresh; + + if (pDM_Odm->SupportICType == ODM_RTL8881A) + LowRSSIThreshForRA = 30; /* for LDPC / BCC switch*/ +#endif + + switch (*pRATRState) { + case DM_RATR_STA_INIT: + case DM_RATR_STA_HIGH: + break; + + case DM_RATR_STA_MIDDLE: + HighRSSIThreshForRA += GoUpGap; + break; + + case DM_RATR_STA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + break; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + case DM_RATR_STA_ULTRA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + UltraLowRSSIThreshForRA += GoUpGap; + break; +#endif + + default: + ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState)); + break; + } + + /* Decide RATRState by RSSI.*/ + if (RSSI > HighRSSIThreshForRA) + RATRState = DM_RATR_STA_HIGH; + else if (RSSI > LowRSSIThreshForRA) + RATRState = DM_RATR_STA_MIDDLE; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + else if (RSSI > UltraLowRSSIThreshForRA) + RATRState = DM_RATR_STA_LOW; + else + RATRState = DM_RATR_STA_ULTRA_LOW; +#else + else + RATRState = DM_RATR_STA_LOW; +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); + /*printk("==>%s,RATRState:0x%02x ,RSSI:%d\n",__FUNCTION__,RATRState,RSSI);*/ + + if (*pRATRState != RATRState || bForceUpdate) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d -> %d\n", *pRATRState, RATRState)); + *pRATRState = RATRState; + return TRUE; + } + + return FALSE; +} + +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_rainfo.h b/package/kernel/rtl8192cd/phydm/phydm_rainfo.h index 0ce9a48d7b5..13f2e953919 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_rainfo.h +++ b/package/kernel/rtl8192cd/phydm/phydm_rainfo.h @@ -1,584 +1,584 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMRAINFO_H__ -#define __PHYDMRAINFO_H__ - -/*#define RAINFO_VERSION "2.0" //2014.11.04*/ -/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ -/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ -/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ -/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ -/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ -/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ -#define RAINFO_VERSION "4.2" /*2016.05.17 Dino, Add H2C debug cmd */ - -#define H2C_0X42_LENGTH 5 -#define H2C_MAX_LENGTH 7 - -#define RA_FLOOR_UP_GAP 3 -#define RA_FLOOR_TABLE_SIZE 7 - -#define ACTIVE_TP_THRESHOLD 1 -#define RA_RETRY_DESCEND_NUM 2 -#define RA_RETRY_LIMIT_LOW 4 -#define RA_RETRY_LIMIT_HIGH 32 - -#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL -#define RAINFO_STBC_STATE BIT1 -//#define RAINFO_LDPC_STATE BIT2 -#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection -#define RAINFO_SHURTCUT_STATE BIT3 -#define RAINFO_SHURTCUT_FLAG BIT4 -#define RAINFO_INIT_RSSI_RATE_STATE BIT5 -#define RAINFO_BF_STATE BIT6 -#define RAINFO_BE_TX_STATE BIT7 // 1:TX - -#define RA_MASK_CCK 0xf -#define RA_MASK_OFDM 0xff0 -#define RA_MASK_HT1SS 0xff000 -#define RA_MASK_HT2SS 0xff00000 -/*#define RA_MASK_MCS3SS */ -#define RA_MASK_HT4SS 0xff0 -#define RA_MASK_VHT1SS 0x3ff000 -#define RA_MASK_VHT2SS 0xffc00000 - -#if(DM_ODM_SUPPORT_TYPE == ODM_AP) -#define RA_FIRST_MACID 1 -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define RA_FIRST_MACID 0 -#define WIN_DEFAULT_PORT_MACID 0 -#define WIN_BT_PORT_MACID 2 -#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ -#define RA_FIRST_MACID 0 -#endif - -#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit - -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) -#define DM_RATR_STA_INIT 0 -#define DM_RATR_STA_HIGH 1 -#define DM_RATR_STA_MIDDLE 2 -#define DM_RATR_STA_LOW 3 -#define DM_RATR_STA_ULTRA_LOW 4 -#endif - -typedef enum _phydm_arfr_num { - ARFR_0_RATE_ID = 0x9, - ARFR_1_RATE_ID = 0xa, - ARFR_2_RATE_ID = 0xb, - ARFR_3_RATE_ID = 0xc, - ARFR_4_RATE_ID = 0xd, - ARFR_5_RATE_ID = 0xe -} PHYDM_RA_ARFR_NUM_E; - -typedef enum _Phydm_ra_dbg_para { - RADBG_PCR_TH_OFFSET = 0, - RADBG_RTY_PENALTY = 1, - RADBG_N_HIGH = 2, - RADBG_N_LOW = 3, - RADBG_TRATE_UP_TABLE = 4, - RADBG_TRATE_DOWN_TABLE = 5, - RADBG_TRYING_NECESSARY = 6, - RADBG_TDROPING_NECESSARY = 7, - RADBG_RATE_UP_RTY_RATIO = 8, - RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 - - RADBG_DEBUG_MONITOR1 = 0xc, - RADBG_DEBUG_MONITOR2 = 0xd, - RADBG_DEBUG_MONITOR3 = 0xe, - RADBG_DEBUG_MONITOR4 = 0xf, - RADBG_DEBUG_MONITOR5 = 0x10, - NUM_RA_PARA -} PHYDM_RA_DBG_PARA_E; - -typedef enum PHYDM_WIRELESS_MODE { - - PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, - PHYDM_WIRELESS_MODE_A = 0x01, - PHYDM_WIRELESS_MODE_B = 0x02, - PHYDM_WIRELESS_MODE_G = 0x04, - PHYDM_WIRELESS_MODE_AUTO = 0x08, - PHYDM_WIRELESS_MODE_N_24G = 0x10, - PHYDM_WIRELESS_MODE_N_5G = 0x20, - PHYDM_WIRELESS_MODE_AC_5G = 0x40, - PHYDM_WIRELESS_MODE_AC_24G = 0x80, - PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, - PHYDM_WIRELESS_MODE_MAX = 0x800, - PHYDM_WIRELESS_MODE_ALL = 0xFFFF -} PHYDM_WIRELESS_MODE_E; - -typedef enum PHYDM_RATEID_IDX_ { - - PHYDM_BGN_40M_2SS = 0, - PHYDM_BGN_40M_1SS = 1, - PHYDM_BGN_20M_2SS = 2, - PHYDM_BGN_20M_1SS = 3, - PHYDM_GN_N2SS = 4, - PHYDM_GN_N1SS = 5, - PHYDM_BG = 6, - PHYDM_G = 7, - PHYDM_B_20M = 8, - PHYDM_ARFR0_AC_2SS = 9, - PHYDM_ARFR1_AC_1SS = 10, - PHYDM_ARFR2_AC_2G_1SS = 11, - PHYDM_ARFR3_AC_2G_2SS = 12, - PHYDM_ARFR4_AC_3SS = 13, - PHYDM_ARFR5_N_3SS = 14 -} PHYDM_RATEID_IDX_E; - -typedef enum _PHYDM_RF_TYPE_DEFINITION { - PHYDM_RF_1T1R = 0, - PHYDM_RF_1T2R, - PHYDM_RF_2T2R, - PHYDM_RF_2T2R_GREEN, - PHYDM_RF_2T3R, - PHYDM_RF_2T4R, - PHYDM_RF_3T3R, - PHYDM_RF_3T4R, - PHYDM_RF_4T4R, - PHYDM_RF_MAX_TYPE -} PHYDM_RF_TYPE_DEF_E; - -typedef enum _PHYDM_BW { - PHYDM_BW_20 = 0, - PHYDM_BW_40, - PHYDM_BW_80, - PHYDM_BW_80_80, - PHYDM_BW_160, - PHYDM_BW_10, - PHYDM_BW_5 -} PHYDM_BW_E; - - -#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA -typedef struct _ODM_RA_Info_ { - u1Byte RateID; - u4Byte RateMask; - u4Byte RAUseRate; - u1Byte RateSGI; - u1Byte RssiStaRA; - u1Byte PreRssiStaRA; - u1Byte SGIEnable; - u1Byte DecisionRate; - u1Byte PreRate; - u1Byte HighestRate; - u1Byte LowestRate; - u4Byte NscUp; - u4Byte NscDown; - u2Byte RTY[5]; - u4Byte TOTAL; - u2Byte DROP; - u1Byte Active; - u2Byte RptTime; - u1Byte RAWaitingCounter; - u1Byte RAPendingCounter; - u1Byte RADropAfterDown; -#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! - u1Byte PTActive; // on or off - u1Byte PTTryState; // 0 trying state, 1 for decision state - u1Byte PTStage; // 0~6 - u1Byte PTStopCount; //Stop PT counter - u1Byte PTPreRate; // if rate change do PT - u1Byte PTPreRssi; // if RSSI change 5% do PT - u1Byte PTModeSS; // decide whitch rate should do PT - u1Byte RAstage; // StageRA, decide how many times RA will be done between PT - u1Byte PTSmoothFactor; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - u1Byte RateDownCounter; - u1Byte RateUpCounter; - u1Byte RateDirection; - u1Byte BoundingType; - u1Byte BoundingCounter; - u1Byte BoundingLearningTime; - u1Byte RateDownStartTime; -#endif -} ODM_RA_INFO_T, *PODM_RA_INFO_T; -#endif - - -typedef struct _Rate_Adaptive_Table_ { - u1Byte firstconnect; -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - BOOLEAN PT_collision_pre; -#endif - -#if (defined(CONFIG_RA_DBG_CMD)) - BOOLEAN is_ra_dbg_init; - - u1Byte RTY_P[ODM_NUM_RATE_IDX]; - u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; - BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; - - u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; - u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; - - u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; - u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; - - BOOLEAN RA_Para_feedback_req; - - u1Byte para_idx; - u1Byte rate_idx; - u1Byte value; - u2Byte value_16; - u1Byte rate_length; -#endif - u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte mu1_rate[30]; - u1Byte highest_client_tx_order; - u2Byte highest_client_tx_rate_order; - u1Byte power_tracking_flag; - u1Byte RA_threshold_offset; - u1Byte RA_offset_direction; - - #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; - u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; - u1Byte retry_descend_num; - u1Byte retrylimit_low; - u1Byte retrylimit_high; - #endif - - -} RA_T, *pRA_T; - -typedef struct _ODM_RATE_ADAPTIVE { - u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver - u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH - u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW - u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC - BOOLEAN bLowerRtsRate; -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - u1Byte RtsThres; -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - BOOLEAN bUseLdpc; -#else - u1Byte UltraLowRSSIThresh; - u4Byte LastRATR; // RATR Register Content -#endif - -} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; - -VOID -phydm_h2C_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -); - -#if (defined(CONFIG_RA_DBG_CMD)) - -VOID -odm_RA_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value -); - -VOID -odm_RA_ParaAdjust_init( - IN PVOID pDM_VOID -); - -#else - -VOID -phydm_RA_debug_PCR( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len -); - -#endif - -VOID -ODM_C2HRaParaReportHandler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -); - -VOID -odm_RA_ParaAdjust( - IN PVOID pDM_VOID -); - -VOID -phydm_ra_dynamic_retry_count( - IN PVOID pDM_VOID -); - -VOID -phydm_ra_dynamic_retry_limit( - IN PVOID pDM_VOID -); - -VOID -phydm_ra_dynamic_rate_id_on_assoc( - IN PVOID pDM_VOID, - IN u1Byte wireless_mode, - IN u1Byte init_rate_id -); - -VOID -phydm_print_rate( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u4Byte dbg_component -); - -VOID -phydm_c2h_ra_report_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen -); - -u1Byte -phydm_rate_order_compute( - IN PVOID pDM_VOID, - IN u1Byte rate_idx - ); - -VOID -phydm_ra_info_watchdog( - IN PVOID pDM_VOID -); - -VOID -phydm_ra_info_init( - IN PVOID pDM_VOID -); - -VOID -odm_RSSIMonitorInit( - IN PVOID pDM_VOID -); - -VOID -phydm_modify_RA_PCR_threshold( - IN PVOID pDM_VOID, - IN u1Byte RA_offset_direction, - IN u1Byte RA_threshold_offset -); - -VOID -odm_RSSIMonitorCheck( - IN PVOID pDM_VOID -); - -VOID -phydm_initRaInfo( - IN PVOID pDM_VOID -); - -u1Byte -phydm_vht_en_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode -); - -u1Byte -phydm_rate_id_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode, - IN u1Byte RfType, - IN u1Byte bw -); - -VOID -phydm_UpdateHalRAMask( - IN PVOID pDM_VOID, - IN u4Byte wirelessMode, - IN u1Byte RfType, - IN u1Byte BW, - IN u1Byte MimoPs_enable, - IN u1Byte disable_cck_rate, - IN u4Byte *ratr_bitmap_msb_in, - IN u4Byte *ratr_bitmap_in, - IN u1Byte tx_rate_level -); - -VOID -odm_RateAdaptiveMaskInit( - IN PVOID pDM_VOID -); - -VOID -odm_RefreshRateAdaptiveMask( - IN PVOID pDM_VOID -); - -VOID -odm_RefreshRateAdaptiveMaskMP( - IN PVOID pDM_VOID -); - -VOID -odm_RefreshRateAdaptiveMaskCE( - IN PVOID pDM_VOID -); - -VOID -odm_RefreshRateAdaptiveMaskAPADSL( - IN PVOID pDM_VOID -); - -u1Byte -phydm_RA_level_decision( - IN PVOID pDM_VOID, - IN u4Byte rssi, - IN u1Byte Ratr_State -); - -BOOLEAN -ODM_RAStateCheck( - IN PVOID pDM_VOID, - IN s4Byte RSSI, - IN BOOLEAN bForceUpdate, - OUT pu1Byte pRATRState -); - -VOID -odm_RefreshBasicRateMask( - IN PVOID pDM_VOID -); -VOID -ODM_RAPostActionOnAssoc( - IN PVOID pDM_Odm -); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - -u1Byte -odm_Find_RTS_Rate( - IN PVOID pDM_VOID, - IN u1Byte Tx_Rate, - IN BOOLEAN bErpProtect -); - -VOID -ODM_UpdateNoisyState( - IN PVOID pDM_VOID, - IN BOOLEAN bNoisyStateFromC2H -); - -VOID -phydm_update_pwr_track( - IN PVOID pDM_VOID, - IN u1Byte Rate -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -s4Byte -phydm_FindMinimumRSSI( -IN PDM_ODM_T pDM_Odm, -IN PADAPTER pAdapter, -IN OUT BOOLEAN *pbLink_temp -); - -VOID -ODM_UpdateInitRateWorkItemCallback( - IN PVOID pContext -); - -VOID -odm_RSSIDumpToRegister( - IN PVOID pDM_VOID -); - -VOID -odm_RefreshLdpcRtsMP( - IN PADAPTER pAdapter, - IN PDM_ODM_T pDM_Odm, - IN u1Byte mMacId, - IN u1Byte IOTPeer, - IN s4Byte UndecoratedSmoothedPWDB -); - -#if 0 -VOID -ODM_DynamicARFBSelect( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN BOOLEAN Collision_State -); -#endif - -VOID -ODM_RateAdaptiveStateApInit( - IN PVOID PADAPTER_VOID, - IN PRT_WLAN_STA pEntry -); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -static void -FindMinimumRSSI( - IN PADAPTER pAdapter -); - -u8Byte -PhyDM_Get_Rate_Bitmap_Ex( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u8Byte ra_mask, - IN u1Byte rssi_level, - OUT u8Byte *dm_RA_Mask, - OUT u1Byte *dm_RteID -); -u4Byte -ODM_Get_Rate_Bitmap( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u4Byte ra_mask, - IN u1Byte rssi_level -); - -void phydm_ra_rssi_rpt_wk(PVOID pContext); -#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -VOID -phydm_gen_ramask_h2c_AP( - IN PVOID pDM_VOID, - IN struct rtl8192cd_priv *priv, - IN PSTA_INFO_T *pEntry, - IN u1Byte rssi_level -); - -#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ - -#endif /*#ifndef __ODMRAINFO_H__*/ - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +/*#define RAINFO_VERSION "2.0" //2014.11.04*/ +/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ +/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ +/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ +/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ +/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ +/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ +#define RAINFO_VERSION "4.2" /*2016.05.17 Dino, Add H2C debug cmd */ + +#define H2C_0X42_LENGTH 5 +#define H2C_MAX_LENGTH 7 + +#define RA_FLOOR_UP_GAP 3 +#define RA_FLOOR_TABLE_SIZE 7 + +#define ACTIVE_TP_THRESHOLD 1 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL +#define RAINFO_STBC_STATE BIT1 +//#define RAINFO_LDPC_STATE BIT2 +#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection +#define RAINFO_SHURTCUT_STATE BIT3 +#define RAINFO_SHURTCUT_FLAG BIT4 +#define RAINFO_INIT_RSSI_RATE_STATE BIT5 +#define RAINFO_BF_STATE BIT6 +#define RAINFO_BE_TX_STATE BIT7 // 1:TX + +#define RA_MASK_CCK 0xf +#define RA_MASK_OFDM 0xff0 +#define RA_MASK_HT1SS 0xff000 +#define RA_MASK_HT2SS 0xff00000 +/*#define RA_MASK_MCS3SS */ +#define RA_MASK_HT4SS 0xff0 +#define RA_MASK_VHT1SS 0x3ff000 +#define RA_MASK_VHT2SS 0xffc00000 + +#if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#define RA_FIRST_MACID 1 +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define RA_FIRST_MACID 0 +#define WIN_DEFAULT_PORT_MACID 0 +#define WIN_BT_PORT_MACID 2 +#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ +#define RA_FIRST_MACID 0 +#endif + +#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit + +#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 +#define DM_RATR_STA_ULTRA_LOW 4 +#endif + +typedef enum _phydm_arfr_num { + ARFR_0_RATE_ID = 0x9, + ARFR_1_RATE_ID = 0xa, + ARFR_2_RATE_ID = 0xb, + ARFR_3_RATE_ID = 0xc, + ARFR_4_RATE_ID = 0xd, + ARFR_5_RATE_ID = 0xe +} PHYDM_RA_ARFR_NUM_E; + +typedef enum _Phydm_ra_dbg_para { + RADBG_PCR_TH_OFFSET = 0, + RADBG_RTY_PENALTY = 1, + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, + RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + RADBG_DEBUG_MONITOR5 = 0x10, + NUM_RA_PARA +} PHYDM_RA_DBG_PARA_E; + +typedef enum PHYDM_WIRELESS_MODE { + + PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, + PHYDM_WIRELESS_MODE_A = 0x01, + PHYDM_WIRELESS_MODE_B = 0x02, + PHYDM_WIRELESS_MODE_G = 0x04, + PHYDM_WIRELESS_MODE_AUTO = 0x08, + PHYDM_WIRELESS_MODE_N_24G = 0x10, + PHYDM_WIRELESS_MODE_N_5G = 0x20, + PHYDM_WIRELESS_MODE_AC_5G = 0x40, + PHYDM_WIRELESS_MODE_AC_24G = 0x80, + PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, + PHYDM_WIRELESS_MODE_MAX = 0x800, + PHYDM_WIRELESS_MODE_ALL = 0xFFFF +} PHYDM_WIRELESS_MODE_E; + +typedef enum PHYDM_RATEID_IDX_ { + + PHYDM_BGN_40M_2SS = 0, + PHYDM_BGN_40M_1SS = 1, + PHYDM_BGN_20M_2SS = 2, + PHYDM_BGN_20M_1SS = 3, + PHYDM_GN_N2SS = 4, + PHYDM_GN_N1SS = 5, + PHYDM_BG = 6, + PHYDM_G = 7, + PHYDM_B_20M = 8, + PHYDM_ARFR0_AC_2SS = 9, + PHYDM_ARFR1_AC_1SS = 10, + PHYDM_ARFR2_AC_2G_1SS = 11, + PHYDM_ARFR3_AC_2G_2SS = 12, + PHYDM_ARFR4_AC_3SS = 13, + PHYDM_ARFR5_N_3SS = 14 +} PHYDM_RATEID_IDX_E; + +typedef enum _PHYDM_RF_TYPE_DEFINITION { + PHYDM_RF_1T1R = 0, + PHYDM_RF_1T2R, + PHYDM_RF_2T2R, + PHYDM_RF_2T2R_GREEN, + PHYDM_RF_2T3R, + PHYDM_RF_2T4R, + PHYDM_RF_3T3R, + PHYDM_RF_3T4R, + PHYDM_RF_4T4R, + PHYDM_RF_MAX_TYPE +} PHYDM_RF_TYPE_DEF_E; + +typedef enum _PHYDM_BW { + PHYDM_BW_20 = 0, + PHYDM_BW_40, + PHYDM_BW_80, + PHYDM_BW_80_80, + PHYDM_BW_160, + PHYDM_BW_10, + PHYDM_BW_5 +} PHYDM_BW_E; + + +#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA +typedef struct _ODM_RA_Info_ { + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; + u1Byte RADropAfterDown; +#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! + u1Byte PTActive; // on or off + u1Byte PTTryState; // 0 trying state, 1 for decision state + u1Byte PTStage; // 0~6 + u1Byte PTStopCount; //Stop PT counter + u1Byte PTPreRate; // if rate change do PT + u1Byte PTPreRssi; // if RSSI change 5% do PT + u1Byte PTModeSS; // decide whitch rate should do PT + u1Byte RAstage; // StageRA, decide how many times RA will be done between PT + u1Byte PTSmoothFactor; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u1Byte RateDownCounter; + u1Byte RateUpCounter; + u1Byte RateDirection; + u1Byte BoundingType; + u1Byte BoundingCounter; + u1Byte BoundingLearningTime; + u1Byte RateDownStartTime; +#endif +} ODM_RA_INFO_T, *PODM_RA_INFO_T; +#endif + + +typedef struct _Rate_Adaptive_Table_ { + u1Byte firstconnect; +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + BOOLEAN PT_collision_pre; +#endif + +#if (defined(CONFIG_RA_DBG_CMD)) + BOOLEAN is_ra_dbg_init; + + u1Byte RTY_P[ODM_NUM_RATE_IDX]; + u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; + BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + BOOLEAN RA_Para_feedback_req; + + u1Byte para_idx; + u1Byte rate_idx; + u1Byte value; + u2Byte value_16; + u1Byte rate_length; +#endif + u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte mu1_rate[30]; + u1Byte highest_client_tx_order; + u2Byte highest_client_tx_rate_order; + u1Byte power_tracking_flag; + u1Byte RA_threshold_offset; + u1Byte RA_offset_direction; + + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u1Byte retry_descend_num; + u1Byte retrylimit_low; + u1Byte retrylimit_high; + #endif + + +} RA_T, *pRA_T; + +typedef struct _ODM_RATE_ADAPTIVE { + u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver + u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH + u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW + u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC + BOOLEAN bLowerRtsRate; +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + u1Byte RtsThres; +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + BOOLEAN bUseLdpc; +#else + u1Byte UltraLowRSSIThresh; + u4Byte LastRATR; // RATR Register Content +#endif + +} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; + +VOID +phydm_h2C_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#if (defined(CONFIG_RA_DBG_CMD)) + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +); + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +); + +#else + +VOID +phydm_RA_debug_PCR( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#endif + +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +odm_RA_ParaAdjust( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_count( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_rate_id_on_assoc( + IN PVOID pDM_VOID, + IN u1Byte wireless_mode, + IN u1Byte init_rate_id +); + +VOID +phydm_print_rate( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN u4Byte dbg_component +); + +VOID +phydm_c2h_ra_report_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +u1Byte +phydm_rate_order_compute( + IN PVOID pDM_VOID, + IN u1Byte rate_idx + ); + +VOID +phydm_ra_info_watchdog( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID +); + +VOID +phydm_modify_RA_PCR_threshold( + IN PVOID pDM_VOID, + IN u1Byte RA_offset_direction, + IN u1Byte RA_threshold_offset +); + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID +); + +VOID +phydm_initRaInfo( + IN PVOID pDM_VOID +); + +u1Byte +phydm_vht_en_mapping( + IN PVOID pDM_VOID, + IN u4Byte WirelessMode +); + +u1Byte +phydm_rate_id_mapping( + IN PVOID pDM_VOID, + IN u4Byte WirelessMode, + IN u1Byte RfType, + IN u1Byte bw +); + +VOID +phydm_UpdateHalRAMask( + IN PVOID pDM_VOID, + IN u4Byte wirelessMode, + IN u1Byte RfType, + IN u1Byte BW, + IN u1Byte MimoPs_enable, + IN u1Byte disable_cck_rate, + IN u4Byte *ratr_bitmap_msb_in, + IN u4Byte *ratr_bitmap_in, + IN u1Byte tx_rate_level +); + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID +); + +u1Byte +phydm_RA_level_decision( + IN PVOID pDM_VOID, + IN u4Byte rssi, + IN u1Byte Ratr_State +); + +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState +); + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID +); +VOID +ODM_RAPostActionOnAssoc( + IN PVOID pDM_Odm +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + +u1Byte +odm_Find_RTS_Rate( + IN PVOID pDM_VOID, + IN u1Byte Tx_Rate, + IN BOOLEAN bErpProtect +); + +VOID +ODM_UpdateNoisyState( + IN PVOID pDM_VOID, + IN BOOLEAN bNoisyStateFromC2H +); + +VOID +phydm_update_pwr_track( + IN PVOID pDM_VOID, + IN u1Byte Rate +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +s4Byte +phydm_FindMinimumRSSI( +IN PDM_ODM_T pDM_Odm, +IN PADAPTER pAdapter, +IN OUT BOOLEAN *pbLink_temp +); + +VOID +ODM_UpdateInitRateWorkItemCallback( + IN PVOID pContext +); + +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshLdpcRtsMP( + IN PADAPTER pAdapter, + IN PDM_ODM_T pDM_Odm, + IN u1Byte mMacId, + IN u1Byte IOTPeer, + IN s4Byte UndecoratedSmoothedPWDB +); + +#if 0 +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State +); +#endif + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry +); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +static void +FindMinimumRSSI( + IN PADAPTER pAdapter +); + +u8Byte +PhyDM_Get_Rate_Bitmap_Ex( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u8Byte ra_mask, + IN u1Byte rssi_level, + OUT u8Byte *dm_RA_Mask, + OUT u1Byte *dm_RteID +); +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level +); + +void phydm_ra_rssi_rpt_wk(PVOID pContext); +#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +VOID +phydm_gen_ramask_h2c_AP( + IN PVOID pDM_VOID, + IN struct rtl8192cd_priv *priv, + IN PSTA_INFO_T *pEntry, + IN u1Byte rssi_level +); + +#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + +#endif /*#ifndef __ODMRAINFO_H__*/ + + diff --git a/package/kernel/rtl8192cd/phydm/phydm_reg.h b/package/kernel/rtl8192cd/phydm/phydm_reg.h index 019b28ee81e..542a1b7ef31 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_reg.h +++ b/package/kernel/rtl8192cd/phydm/phydm_reg.h @@ -1,215 +1,215 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -//============================================================ -// File Name: odm_reg.h -// -// Description: -// -// This file is for general register definition. -// -// -//============================================================ -#ifndef __HAL_ODM_REG_H__ -#define __HAL_ODM_REG_H__ - -// -// Register Definition -// - -//MAC REG -#define ODM_BB_RESET 0x002 -#define ODM_DUMMY 0x4fe -#define RF_T_METER_OLD 0x24 -#define RF_T_METER_NEW 0x42 - -#define ODM_EDCA_VO_PARAM 0x500 -#define ODM_EDCA_VI_PARAM 0x504 -#define ODM_EDCA_BE_PARAM 0x508 -#define ODM_EDCA_BK_PARAM 0x50C -#define ODM_TXPAUSE 0x522 - -/* LTE_COEX */ -#define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 -#define REG_LTECOEX_READ_DATA 0x07C8 -#define REG_LTECOEX_PATH_CONTROL 0x70 - -//BB REG -#define ODM_FPGA_PHY0_PAGE8 0x800 -#define ODM_PSD_SETTING 0x808 -#define ODM_AFE_SETTING 0x818 -#define ODM_TXAGC_B_6_18 0x830 -#define ODM_TXAGC_B_24_54 0x834 -#define ODM_TXAGC_B_MCS32_5 0x838 -#define ODM_TXAGC_B_MCS0_MCS3 0x83c -#define ODM_TXAGC_B_MCS4_MCS7 0x848 -#define ODM_TXAGC_B_MCS8_MCS11 0x84c -#define ODM_ANALOG_REGISTER 0x85c -#define ODM_RF_INTERFACE_OUTPUT 0x860 -#define ODM_TXAGC_B_MCS12_MCS15 0x868 -#define ODM_TXAGC_B_11_A_2_11 0x86c -#define ODM_AD_DA_LSB_MASK 0x874 -#define ODM_ENABLE_3_WIRE 0x88c -#define ODM_PSD_REPORT 0x8b4 -#define ODM_R_ANT_SELECT 0x90c -#define ODM_CCK_ANT_SELECT 0xa07 -#define ODM_CCK_PD_THRESH 0xa0a -#define ODM_CCK_RF_REG1 0xa11 -#define ODM_CCK_MATCH_FILTER 0xa20 -#define ODM_CCK_RAKE_MAC 0xa2e -#define ODM_CCK_CNT_RESET 0xa2d -#define ODM_CCK_TX_DIVERSITY 0xa2f -#define ODM_CCK_FA_CNT_MSB 0xa5b -#define ODM_CCK_FA_CNT_LSB 0xa5c -#define ODM_CCK_NEW_FUNCTION 0xa75 -#define ODM_OFDM_PHY0_PAGE_C 0xc00 -#define ODM_OFDM_RX_ANT 0xc04 -#define ODM_R_A_RXIQI 0xc14 -#define ODM_R_A_AGC_CORE1 0xc50 -#define ODM_R_A_AGC_CORE2 0xc54 -#define ODM_R_B_AGC_CORE1 0xc58 -#define ODM_R_AGC_PAR 0xc70 -#define ODM_R_HTSTF_AGC_PAR 0xc7c -#define ODM_TX_PWR_TRAINING_A 0xc90 -#define ODM_TX_PWR_TRAINING_B 0xc98 -#define ODM_OFDM_FA_CNT1 0xcf0 -#define ODM_OFDM_PHY0_PAGE_D 0xd00 -#define ODM_OFDM_FA_CNT2 0xda0 -#define ODM_OFDM_FA_CNT3 0xda4 -#define ODM_OFDM_FA_CNT4 0xda8 -#define ODM_TXAGC_A_6_18 0xe00 -#define ODM_TXAGC_A_24_54 0xe04 -#define ODM_TXAGC_A_1_MCS32 0xe08 -#define ODM_TXAGC_A_MCS0_MCS3 0xe10 -#define ODM_TXAGC_A_MCS4_MCS7 0xe14 -#define ODM_TXAGC_A_MCS8_MCS11 0xe18 -#define ODM_TXAGC_A_MCS12_MCS15 0xe1c - -//RF REG -#define ODM_GAIN_SETTING 0x00 -#define ODM_CHANNEL 0x18 -#define ODM_RF_T_METER 0x24 -#define ODM_RF_T_METER_92D 0x42 -#define ODM_RF_T_METER_88E 0x42 -#define ODM_RF_T_METER_92E 0x42 -#define ODM_RF_T_METER_8812 0x42 -#define rRF_TxGainOffset 0x55 - -//Ant Detect Reg -#define ODM_DPDT 0x300 - -//PSD Init -#define ODM_PSDREG 0x808 - -//92D Path Div -#define PATHDIV_REG 0xB30 -#define PATHDIV_TRI 0xBA0 - - -// -// Bitmap Definition -// -#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) -// TX AGC -#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 -#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 -#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 -#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c -#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 -#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 -#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 -#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c -#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 -#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 -#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 -#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c -#if defined(CONFIG_WLAN_HAL_8814AE) -#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 -#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc -#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 -#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 -#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 -#endif -#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 -#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 -#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 -#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c -#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 -#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 -#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 -#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c -#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 -#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 -#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 -#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c -#if defined(CONFIG_WLAN_HAL_8814AE) -#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 -#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc -#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 -#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 -#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 -#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 -#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 -#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 -#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c -#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 -#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 -#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 -#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c -#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 -#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 -#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 -#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c -#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 -#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc -#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 -#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 -#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 -#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 -#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 -#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 -#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c -#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 -#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 -#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 -#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c -#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 -#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 -#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 -#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c -#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 -#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc -#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 -#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 -#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 -#endif - -#define bTxAGC_byte0_Jaguar 0xff -#define bTxAGC_byte1_Jaguar 0xff00 -#define bTxAGC_byte2_Jaguar 0xff0000 -#define bTxAGC_byte3_Jaguar 0xff000000 -#endif - -#define BIT_FA_RESET BIT0 - - - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: odm_reg.h +// +// Description: +// +// This file is for general register definition. +// +// +//============================================================ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +// +// Register Definition +// + +//MAC REG +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +/* LTE_COEX */ +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 + +//BB REG +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +//RF REG +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 +#define rRF_TxGainOffset 0x55 + +//Ant Detect Reg +#define ODM_DPDT 0x300 + +//PSD Init +#define ODM_PSDREG 0x808 + +//92D Path Div +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +// +// Bitmap Definition +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) +// TX AGC +#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 +#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c +#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 +#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 +#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 +#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 +#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc +#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 +#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 +#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 +#endif +#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 +#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c +#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 +#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 +#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 +#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 +#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc +#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 +#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 +#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 +#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 +#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 +#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 +#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c +#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 +#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 +#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 +#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c +#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 +#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 +#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 +#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c +#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 +#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc +#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 +#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 +#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 +#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 +#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 +#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 +#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c +#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 +#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 +#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 +#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c +#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 +#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 +#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 +#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c +#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 +#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc +#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 +#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 +#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 +#endif + +#define bTxAGC_byte0_Jaguar 0xff +#define bTxAGC_byte1_Jaguar 0xff00 +#define bTxAGC_byte2_Jaguar 0xff0000 +#define bTxAGC_byte3_Jaguar 0xff000000 +#endif + +#define BIT_FA_RESET BIT0 + + + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_regdefine11ac.h b/package/kernel/rtl8192cd/phydm/phydm_regdefine11ac.h index 2e7a9e840a9..336d72d9771 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_regdefine11ac.h +++ b/package/kernel/rtl8192cd/phydm/phydm_regdefine11ac.h @@ -1,100 +1,100 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __ODM_REGDEFINE11AC_H__ -#define __ODM_REGDEFINE11AC_H__ - -//2 RF REG LIST - - - -//2 BB REG LIST -//PAGE 8 -#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 -#define ODM_REG_BB_RX_PATH_11AC 0x808 -#define ODM_REG_BB_TX_PATH_11AC 0x80c -#define ODM_REG_BB_ATC_11AC 0x860 -#define ODM_REG_EDCCA_POWER_CAL 0x8dc -#define ODM_REG_DBG_RPT_11AC 0x8fc -//PAGE 9 -#define ODM_REG_EDCCA_DOWN_OPT 0x900 -#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 -#define ODM_ADC_TRIGGER_Jaguar2 0x95C /*ADC sample mode*/ -#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 -#define ODM_REG_CCX_PERIOD_11AC 0x990 -#define ODM_REG_NHM_TH9_TH10_11AC 0x994 -#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990 -#define ODM_REG_CLM_11AC 0x994 -#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 -#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c -#define ODM_REG_NHM_TH8_11AC 0x9a0 -#define ODM_REG_NHM_9E8_11AC 0x9e8 -#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 -//PAGE A -#define ODM_REG_CCK_CCA_11AC 0xA0A -#define ODM_REG_CCK_FA_RST_11AC 0xA2C -#define ODM_REG_CCK_FA_11AC 0xA5C -//PAGE B -#define ODM_REG_RST_RPT_11AC 0xB58 -//PAGE C -#define ODM_REG_TRMUX_11AC 0xC08 -#define ODM_REG_IGI_A_11AC 0xC50 -//PAGE E -#define ODM_REG_IGI_B_11AC 0xE50 -#define ODM_REG_TRMUX_11AC_B 0xE08 -//PAGE F -#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 -#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 -#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c -#define ODM_REG_HT_CRC32_CNT_11AC 0xF10 -#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 -#define ODM_REG_OFDM_FA_11AC 0xF48 -#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC -#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 -#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC -#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 -#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 -#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 -#define ODM_REG_RPT_11AC 0xfa0 -#define ODM_REG_CLM_RESULT_11AC 0xfa4 -#define ODM_REG_NHM_CNT_11AC 0xfa8 -#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 - -#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac -#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 -//PAGE 18 -#define ODM_REG_IGI_C_11AC 0x1850 -//PAGE 1A -#define ODM_REG_IGI_D_11AC 0x1A50 - -//2 MAC REG LIST -#define ODM_REG_RESP_TX_11AC 0x6D8 -#define ODM_REG_PS_TIMER2 0x588 - - -//DIG Related -#define ODM_BIT_IGI_11AC 0xFFFFFFFF -#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 -#define ODM_BIT_BB_RX_PATH_11AC 0xF -#define ODM_BIT_BB_TX_PATH_11AC 0xF -#define ODM_BIT_BB_ATC_11AC BIT14 - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +//2 RF REG LIST + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +//PAGE 9 +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define ODM_ADC_TRIGGER_Jaguar2 0x95C /*ADC sample mode*/ +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_CCX_PERIOD_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 +//PAGE A +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +//PAGE B +#define ODM_REG_RST_RPT_11AC 0xB58 +//PAGE C +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +//PAGE E +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_TRMUX_11AC_B 0xE08 +//PAGE F +#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c +#define ODM_REG_HT_CRC32_CNT_11AC 0xF10 +#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC +#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 +#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 +#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 + +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 +//PAGE 18 +#define ODM_REG_IGI_C_11AC 0x1850 +//PAGE 1A +#define ODM_REG_IGI_D_11AC 0x1A50 + +//2 MAC REG LIST +#define ODM_REG_RESP_TX_11AC 0x6D8 +#define ODM_REG_PS_TIMER2 0x588 + + +//DIG Related +#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT14 + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_regdefine11n.h b/package/kernel/rtl8192cd/phydm/phydm_regdefine11n.h index 17a1aa478f0..0757078e5e6 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_regdefine11n.h +++ b/package/kernel/rtl8192cd/phydm/phydm_regdefine11n.h @@ -1,215 +1,215 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __ODM_REGDEFINE11N_H__ -#define __ODM_REGDEFINE11N_H__ - - -//2 RF REG LIST -#define ODM_REG_RF_MODE_11N 0x00 -#define ODM_REG_RF_0B_11N 0x0B -#define ODM_REG_CHNBW_11N 0x18 -#define ODM_REG_T_METER_11N 0x24 -#define ODM_REG_RF_25_11N 0x25 -#define ODM_REG_RF_26_11N 0x26 -#define ODM_REG_RF_27_11N 0x27 -#define ODM_REG_RF_2B_11N 0x2B -#define ODM_REG_RF_2C_11N 0x2C -#define ODM_REG_RXRF_A3_11N 0x3C -#define ODM_REG_T_METER_92D_11N 0x42 -#define ODM_REG_T_METER_88E_11N 0x42 - - - -//2 BB REG LIST -//PAGE 8 -#define ODM_REG_BB_CTRL_11N 0x800 -#define ODM_REG_RF_PIN_11N 0x804 -#define ODM_REG_PSD_CTRL_11N 0x808 -#define ODM_REG_TX_ANT_CTRL_11N 0x80C -#define ODM_REG_BB_PWR_SAV5_11N 0x818 -#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 -#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C -#define ODM_REG_RX_DEFUALT_A_11N 0x858 -#define ODM_REG_RX_DEFUALT_B_11N 0x85A -#define ODM_REG_BB_PWR_SAV3_11N 0x85C -#define ODM_REG_ANTSEL_CTRL_11N 0x860 -#define ODM_REG_RX_ANT_CTRL_11N 0x864 -#define ODM_REG_PIN_CTRL_11N 0x870 -#define ODM_REG_BB_PWR_SAV1_11N 0x874 -#define ODM_REG_ANTSEL_PATH_11N 0x878 -#define ODM_REG_BB_3WIRE_11N 0x88C -#define ODM_REG_SC_CNT_11N 0x8C4 -#define ODM_REG_PSD_DATA_11N 0x8B4 -#define ODM_REG_CCX_PERIOD_11N 0x894 -#define ODM_REG_NHM_TH9_TH10_11N 0x890 -#define ODM_REG_CLM_11N 0x890 -#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 -#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c -#define ODM_REG_NHM_TH8_11N 0xe28 -#define ODM_REG_CLM_READY_11N 0x8b4 -#define ODM_REG_CLM_RESULT_11N 0x8d0 -#define ODM_REG_NHM_CNT_11N 0x8d8 -#define ODM_REG_CLM_TIME_PERIOD_11N 0x894 - -// For ACS, Jeffery, 2014-12-26 -#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc -#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 -#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 - -//PAGE 9 -#define ODM_REG_BB_CTRL_PAGE9_11N 0x900 -#define ODM_REG_DBG_RPT_11N 0x908 -#define ODM_REG_BB_TX_PATH_11N 0x90c -#define ODM_REG_ANT_MAPPING1_11N 0x914 -#define ODM_REG_ANT_MAPPING2_11N 0x918 -#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 -#define ODM_REG_RX_DFIR_MOD_97F 0x948 - -//PAGE A -#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 -#define ODM_REG_CCK_ANT_SEL_11N 0xA04 -#define ODM_REG_CCK_CCA_11N 0xA0A -#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C -#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 -#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 -#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 -#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 -#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 -#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 -#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 -#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 -#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 -#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 -#define ODM_REG_CCK_FA_RST_11N 0xA2C -#define ODM_REG_CCK_FA_MSB_11N 0xA58 -#define ODM_REG_CCK_FA_LSB_11N 0xA5C -#define ODM_REG_CCK_CCA_CNT_11N 0xA60 -#define ODM_REG_BB_PWR_SAV4_11N 0xA74 -//PAGE B -#define ODM_REG_LNA_SWITCH_11N 0xB2C -#define ODM_REG_PATH_SWITCH_11N 0xB30 -#define ODM_REG_RSSI_CTRL_11N 0xB38 -#define ODM_REG_CONFIG_ANTA_11N 0xB68 -#define ODM_REG_RSSI_BT_11N 0xB9C -#define ODM_REG_RXCK_RFMOD 0xBB0 -#define ODM_REG_EDCCA_DCNF_97F 0xBC0 - -//PAGE C -#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 -#define ODM_REG_BB_RX_PATH_11N 0xC04 -#define ODM_REG_TRMUX_11N 0xC08 -#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C -#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 -#define ODM_REG_RXIQI_MATRIX_11N 0xC14 -#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C -#define ODM_REG_IGI_A_11N 0xC50 -#define ODM_REG_ANTDIV_PARA2_11N 0xC54 -#define ODM_REG_IGI_B_11N 0xC58 -#define ODM_REG_ANTDIV_PARA3_11N 0xC5C -#define ODM_REG_L1SBD_PD_CH_11N 0XC6C -#define ODM_REG_BB_PWR_SAV2_11N 0xC70 -#define ODM_REG_BB_AGC_SET_2_11N 0xc74 -#define ODM_REG_RX_OFF_11N 0xC7C -#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 -#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 -#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 -#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C -#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 -#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 -#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 -#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 -//PAGE D -#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 -#define ODM_REG_BB_RX_ANT_11N 0xD04 -#define ODM_REG_BB_ATC_11N 0xD2C -#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 -#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 -#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 -#define ODM_REG_RPT_11N 0xDF4 -//PAGE E -#define ODM_REG_TXAGC_A_6_18_11N 0xE00 -#define ODM_REG_TXAGC_A_24_54_11N 0xE04 -#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 -#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 -#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 -#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 -#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C -#define ODM_REG_EDCCA_DCNF_11N 0xE24 -#define ODM_REG_TAP_UPD_97F 0xE24 -#define ODM_REG_FPGA0_IQK_11N 0xE28 -#define ODM_REG_PAGE_B1_97F 0xE28 -#define ODM_REG_TXIQK_TONE_A_11N 0xE30 -#define ODM_REG_RXIQK_TONE_A_11N 0xE34 -#define ODM_REG_TXIQK_PI_A_11N 0xE38 -#define ODM_REG_RXIQK_PI_A_11N 0xE3C -#define ODM_REG_TXIQK_11N 0xE40 -#define ODM_REG_RXIQK_11N 0xE44 -#define ODM_REG_IQK_AGC_PTS_11N 0xE48 -#define ODM_REG_IQK_AGC_RSP_11N 0xE4C -#define ODM_REG_BLUETOOTH_11N 0xE6C -#define ODM_REG_RX_WAIT_CCA_11N 0xE70 -#define ODM_REG_TX_CCK_RFON_11N 0xE74 -#define ODM_REG_TX_CCK_BBON_11N 0xE78 -#define ODM_REG_OFDM_RFON_11N 0xE7C -#define ODM_REG_OFDM_BBON_11N 0xE80 -#define ODM_REG_TX2RX_11N 0xE84 -#define ODM_REG_TX2TX_11N 0xE88 -#define ODM_REG_RX_CCK_11N 0xE8C -#define ODM_REG_RX_OFDM_11N 0xED0 -#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 -#define ODM_REG_RX2RX_11N 0xED8 -#define ODM_REG_STANDBY_11N 0xEDC -#define ODM_REG_SLEEP_11N 0xEE0 -#define ODM_REG_PMPD_ANAEN_11N 0xEEC -/* PAGE F */ -#define ODM_REG_PAGE_F_RST_11N 0xF14 -#define ODM_REG_IGI_C_11N 0xF84 -#define ODM_REG_IGI_D_11N 0xF88 -#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 -#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 -#define ODM_REG_HT_CRC32_CNT_11N 0xF90 -#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 - -//2 MAC REG LIST -#define ODM_REG_BB_RST_11N 0x02 -#define ODM_REG_ANTSEL_PIN_11N 0x4C -#define ODM_REG_EARLY_MODE_11N 0x4D0 -#define ODM_REG_RSSI_MONITOR_11N 0x4FE -#define ODM_REG_EDCA_VO_11N 0x500 -#define ODM_REG_EDCA_VI_11N 0x504 -#define ODM_REG_EDCA_BE_11N 0x508 -#define ODM_REG_EDCA_BK_11N 0x50C -#define ODM_REG_TXPAUSE_11N 0x522 -#define ODM_REG_PS_TIMER2 0x588 -#define ODM_REG_RESP_TX_11N 0x6D8 -#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 -#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 - - -//DIG Related -#define ODM_BIT_IGI_11N 0x0000007F -#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 -#define ODM_BIT_BB_RX_PATH_11N 0xF -#define ODM_BIT_BB_TX_PATH_11N 0xF -#define ODM_BIT_BB_ATC_11N BIT11 - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +//2 RF REG LIST +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_CCX_PERIOD_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_CLM_READY_11N 0x8b4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_NHM_CNT_11N 0x8d8 +#define ODM_REG_CLM_TIME_PERIOD_11N 0x894 + +// For ACS, Jeffery, 2014-12-26 +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 + +//PAGE 9 +#define ODM_REG_BB_CTRL_PAGE9_11N 0x900 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 +#define ODM_REG_RX_DFIR_MOD_97F 0x948 + +//PAGE A +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_ANT_SEL_11N 0xA04 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +//PAGE B +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +#define ODM_REG_RXCK_RFMOD 0xBB0 +#define ODM_REG_EDCCA_DCNF_97F 0xBC0 + +//PAGE C +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_BB_AGC_SET_2_11N 0xc74 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +//PAGE D +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_RX_ANT_11N 0xD04 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +//PAGE E +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_TAP_UPD_97F 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_PAGE_B1_97F 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +/* PAGE F */ +#define ODM_REG_PAGE_F_RST_11N 0xF14 +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 +#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 +#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 +#define ODM_REG_HT_CRC32_CNT_11N 0xF90 +#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 + +//2 MAC REG LIST +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_PS_TIMER2 0x588 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +//DIG Related +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT11 + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/phydm_types.h b/package/kernel/rtl8192cd/phydm/phydm_types.h index a5382fb9c07..dcc07f56c03 100644 --- a/package/kernel/rtl8192cd/phydm/phydm_types.h +++ b/package/kernel/rtl8192cd/phydm/phydm_types.h @@ -1,261 +1,261 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_TYPES_H__ -#define __ODM_TYPES_H__ - - -/*Define Different SW team support*/ -#define ODM_AP 0x01 /*BIT0*/ -#define ODM_CE 0x04 /*BIT2*/ -#define ODM_WIN 0x08 /*BIT3*/ -#define ODM_ADSL 0x10 /*BIT4*/ -#define ODM_IOT 0x20 /*BIT5*/ - -/*Deifne HW endian support*/ -#define ODM_ENDIAN_BIG 0 -#define ODM_ENDIAN_LITTLE 1 - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) -#endif - -#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -#define RT_PCI_INTERFACE 1 -#define RT_USB_INTERFACE 2 -#define RT_SDIO_INTERFACE 3 -#endif - -typedef enum _HAL_STATUS{ - HAL_STATUS_SUCCESS, - HAL_STATUS_FAILURE, - /*RT_STATUS_PENDING, - RT_STATUS_RESOURCE, - RT_STATUS_INVALID_CONTEXT, - RT_STATUS_INVALID_PARAMETER, - RT_STATUS_NOT_SUPPORT, - RT_STATUS_OS_API_FAILED,*/ -}HAL_STATUS,*PHAL_STATUS; - -#if( DM_ODM_SUPPORT_TYPE == ODM_AP) -#define MP_DRIVER 0 -#endif -#if(DM_ODM_SUPPORT_TYPE != ODM_WIN) - -#define VISTA_USB_RX_REVISE 0 - -// -// Declare for ODM spin lock defintion temporarily fro compile pass. -// -typedef enum _RT_SPINLOCK_TYPE{ - RT_TX_SPINLOCK = 1, - RT_RX_SPINLOCK = 2, - RT_RM_SPINLOCK = 3, - RT_CAM_SPINLOCK = 4, - RT_SCAN_SPINLOCK = 5, - RT_LOG_SPINLOCK = 7, - RT_BW_SPINLOCK = 8, - RT_CHNLOP_SPINLOCK = 9, - RT_RF_OPERATE_SPINLOCK = 10, - RT_INITIAL_SPINLOCK = 11, - RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. -#if VISTA_USB_RX_REVISE - RT_USBRX_CONTEXT_SPINLOCK = 13, - RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR -#endif - //Shall we define Ndis 6.2 SpinLock Here ? - RT_PORT_SPINLOCK=16, - RT_VNIC_SPINLOCK=17, - RT_HVL_SPINLOCK=18, - RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. - - RT_BTData_SPINLOCK=25, - - RT_WAPI_OPTION_SPINLOCK=26, - RT_WAPI_RX_SPINLOCK=27, - - // add for 92D CCK control issue - RT_CCK_PAGEA_SPINLOCK = 28, - RT_BUFFER_SPINLOCK = 29, - RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, - RT_GEN_TEMP_BUF_SPINLOCK = 31, - RT_AWB_SPINLOCK = 32, - RT_FW_PS_SPINLOCK = 33, - RT_HW_TIMER_SPIN_LOCK = 34, - RT_MPT_WI_SPINLOCK = 35, - RT_P2P_SPIN_LOCK = 36, // Protect P2P context - RT_DBG_SPIN_LOCK = 37, - RT_IQK_SPINLOCK = 38, - RT_PENDED_OID_SPINLOCK = 39, - RT_CHNLLIST_SPINLOCK = 40, - RT_INDIC_SPINLOCK = 41, //protect indication - RT_RFD_SPINLOCK = 42, - RT_SYNC_IO_CNT_SPINLOCK = 43, - RT_LAST_SPINLOCK, -}RT_SPINLOCK_TYPE; - -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define STA_INFO_T RT_WLAN_STA - #define PSTA_INFO_T PRT_WLAN_STA - #define __func__ __FUNCTION__ - #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT - #define bMaskH3Bytes 0xffffff00 - #define SUCCESS 0 - #define FAIL (-1) - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. - #define ADSL_AP_BUILD_WORKAROUND - #define AP_BUILD_WORKAROUND - - #ifdef AP_BUILD_WORKAROUND - #include "../typedef.h" - #else - typedef void VOID,*PVOID; - typedef unsigned char BOOLEAN,*PBOOLEAN; - typedef unsigned char u1Byte,*pu1Byte; - typedef unsigned short u2Byte,*pu2Byte; - typedef unsigned int u4Byte,*pu4Byte; - typedef unsigned long long u8Byte,*pu8Byte; -#if 1 -/* In ARM platform, system would use the type -- "char" as "unsigned char" - * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/ - typedef signed char s1Byte,*ps1Byte; -#else - typedef char s1Byte,*ps1Byte; -#endif - typedef short s2Byte,*ps2Byte; - typedef long s4Byte,*ps4Byte; - typedef long long s8Byte,*ps8Byte; - #endif - - typedef struct rtl8192cd_priv *prtl8192cd_priv; - typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; - typedef struct timer_list RT_TIMER, *PRT_TIMER; - typedef void * RT_TIMER_CALL_BACK; - -#ifdef CONFIG_PCI_HCI - #define DEV_BUS_TYPE RT_PCI_INTERFACE -#endif - - #define _TRUE 1 - #define _FALSE 0 - - #if (defined(TESTCHIP_SUPPORT)) - #define PHYDM_TESTCHIP_SUPPORT 1 - #else - #define PHYDM_TESTCHIP_SUPPORT 0 - #endif - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include -#if 0 - typedef u8 u1Byte, *pu1Byte; - typedef u16 u2Byte,*pu2Byte; - typedef u32 u4Byte,*pu4Byte; - typedef u64 u8Byte,*pu8Byte; - typedef s8 s1Byte,*ps1Byte; - typedef s16 s2Byte,*ps2Byte; - typedef s32 s4Byte,*ps4Byte; - typedef s64 s8Byte,*ps8Byte; -#else - #define u1Byte u8 - #define pu1Byte u8* - - #define u2Byte u16 - #define pu2Byte u16* - - #define u4Byte u32 - #define pu4Byte u32* - - #define u8Byte u64 - #define pu8Byte u64* - - #define s1Byte s8 - #define ps1Byte s8* - - #define s2Byte s16 - #define ps2Byte s16* - - #define s4Byte s32 - #define ps4Byte s32* - - #define s8Byte s64 - #define ps8Byte s64* - -#endif - #ifdef CONFIG_USB_HCI - #define DEV_BUS_TYPE RT_USB_INTERFACE - #elif defined(CONFIG_PCI_HCI) - #define DEV_BUS_TYPE RT_PCI_INTERFACE - #elif defined(CONFIG_SDIO_HCI) - #define DEV_BUS_TYPE RT_SDIO_INTERFACE - #elif defined(CONFIG_GSPI_HCI) - #define DEV_BUS_TYPE RT_SDIO_INTERFACE - #endif - - - #if defined(CONFIG_LITTLE_ENDIAN) - #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE - #elif defined (CONFIG_BIG_ENDIAN) - #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG - #endif - - typedef struct timer_list RT_TIMER, *PRT_TIMER; - typedef void * RT_TIMER_CALL_BACK; - #define STA_INFO_T struct sta_info - #define PSTA_INFO_T struct sta_info * - - - - #define TRUE _TRUE - #define FALSE _FALSE - - - #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) - #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) - #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) - - //define useless flag to avoid compile warning - #define USE_WORKITEM 0 - #define FOR_BRAZIL_PRETEST 0 - #define FPGA_TWO_MAC_VERIFICATION 0 - #define RTL8881A_SUPPORT 0 - - #if (defined(TESTCHIP_SUPPORT)) - #define PHYDM_TESTCHIP_SUPPORT 1 - #else - #define PHYDM_TESTCHIP_SUPPORT 0 - #endif -#endif - -#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) -#define COND_ELSE 2 -#define COND_ENDIF 3 - -#include "phydm_features.h" - -#endif // __ODM_TYPES_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + + +/*Define Different SW team support*/ +#define ODM_AP 0x01 /*BIT0*/ +#define ODM_CE 0x04 /*BIT2*/ +#define ODM_WIN 0x08 /*BIT3*/ +#define ODM_ADSL 0x10 /*BIT4*/ +#define ODM_IOT 0x20 /*BIT5*/ + +/*Deifne HW endian support*/ +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 +#endif + +typedef enum _HAL_STATUS{ + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}HAL_STATUS,*PHAL_STATUS; + +#if( DM_ODM_SUPPORT_TYPE == ODM_AP) +#define MP_DRIVER 0 +#endif +#if(DM_ODM_SUPPORT_TYPE != ODM_WIN) + +#define VISTA_USB_RX_REVISE 0 + +// +// Declare for ODM spin lock defintion temporarily fro compile pass. +// +typedef enum _RT_SPINLOCK_TYPE{ + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR +#endif + //Shall we define Ndis 6.2 SpinLock Here ? + RT_PORT_SPINLOCK=16, + RT_VNIC_SPINLOCK=17, + RT_HVL_SPINLOCK=18, + RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + + RT_BTData_SPINLOCK=25, + + RT_WAPI_OPTION_SPINLOCK=26, + RT_WAPI_RX_SPINLOCK=27, + + // add for 92D CCK control issue + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, // Protect P2P context + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, //protect indication + RT_RFD_SPINLOCK = 42, + RT_SYNC_IO_CNT_SPINLOCK = 43, + RT_LAST_SPINLOCK, +}RT_SPINLOCK_TYPE; + +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define STA_INFO_T RT_WLAN_STA + #define PSTA_INFO_T PRT_WLAN_STA + #define __func__ __FUNCTION__ + #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT + #define bMaskH3Bytes 0xffffff00 + #define SUCCESS 0 + #define FAIL (-1) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define AP_BUILD_WORKAROUND + + #ifdef AP_BUILD_WORKAROUND + #include "../typedef.h" + #else + typedef void VOID,*PVOID; + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; +#if 1 +/* In ARM platform, system would use the type -- "char" as "unsigned char" + * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/ + typedef signed char s1Byte,*ps1Byte; +#else + typedef char s1Byte,*ps1Byte; +#endif + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + #endif + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + +#ifdef CONFIG_PCI_HCI + #define DEV_BUS_TYPE RT_PCI_INTERFACE +#endif + + #define _TRUE 1 + #define _FALSE 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include +#if 0 + typedef u8 u1Byte, *pu1Byte; + typedef u16 u2Byte,*pu2Byte; + typedef u32 u4Byte,*pu4Byte; + typedef u64 u8Byte,*pu8Byte; + typedef s8 s1Byte,*ps1Byte; + typedef s16 s2Byte,*ps2Byte; + typedef s32 s4Byte,*ps4Byte; + typedef s64 s8Byte,*ps8Byte; +#else + #define u1Byte u8 + #define pu1Byte u8* + + #define u2Byte u16 + #define pu2Byte u16* + + #define u4Byte u32 + #define pu4Byte u32* + + #define u8Byte u64 + #define pu8Byte u64* + + #define s1Byte s8 + #define ps1Byte s8* + + #define s2Byte s16 + #define ps2Byte s16* + + #define s4Byte s32 + #define ps4Byte s32* + + #define s8Byte s64 + #define ps8Byte s64* + +#endif + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + #define STA_INFO_T struct sta_info + #define PSTA_INFO_T struct sta_info * + + + + #define TRUE _TRUE + #define FALSE _FALSE + + + #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) + #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) + #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + + //define useless flag to avoid compile warning + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif +#endif + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#include "phydm_features.h" + +#endif // __ODM_TYPES_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtchnlplan.c b/package/kernel/rtl8192cd/phydm/rtchnlplan.c index 4b41ff111f1..9c2914571f3 100644 --- a/package/kernel/rtl8192cd/phydm/rtchnlplan.c +++ b/package/kernel/rtl8192cd/phydm/rtchnlplan.c @@ -1,481 +1,481 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/****************************************************************************** - - History: - Data Who Remark (Internal History) - - 05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft. - -******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" -#include "rtchnlplan.h" - - - -// -// Channel Plan Domain Code -// - -/* - Channel Plan Contents - Domain Code EEPROM Countries in Specific Domain - 2G RD 5G RD Bit[6:0] 2G 5G - Case Old Define 00h~1Fh Old Define Old Define - 1 2G_WORLD 5G_NULL 20h Worldwird 13 NA - 2 2G_ETSI1 5G_NULL 21h Europe 2G NA - 3 2G_FCC1 5G_NULL 22h US 2G NA - 4 2G_MKK1 5G_NULL 23h Japan 2G NA - 5 2G_ETSI2 5G_NULL 24h France 2G NA - 6 2G_FCC1 5G_FCC1 25h US 2G US 5G ¤K¤j°ê»{ÃÒ - 7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe ¤K¤j°ê»{ÃÒ - 8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G ¤K¤j°ê»{ÃÒ - 9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea ¤K¤j°ê»{ÃÒ - 10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels - 11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico - 12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela - 13 2G_WORLD 5G_FCC5 32h Worldwird 13 China - 14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel - 15 2G_FCC1 5G_FCC7 34h US 2G US/Canada ¤K¤j°ê»{ÃÒ - 16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand ¤K¤j°ê»{ÃÒ - 17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia - 18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53) - 19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56) - 20 2G_FCC1 5G_NCC1 39h US 2G Taiwan ¤K¤j°ê»{ÃÒ - - NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define - - - - - - 2.4G Regulatory Domains - Case 2G RD Regulation Channels Frequencyes Note Countries in Specific Domain - 1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13 - 2 2G_ETSI1 ETSI 1~13 2412~2472 Europe - 3 2G_FCC1 FCC 1~11 2412~2462 US - 4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan - 5 2G_ETSI2 ETSI 10~13 2457~2472 France - - - - - 5G Regulatory Domains - Case 5G RD Regulation Channels Frequencyes Note Countries in Specific Domain - 1 5G_NULL NA NA NA Do not support 5GHz - 2 5G_ETSI1 ETSI "36~48, 52~64, - 100~140" "5180~5240, 5260~5230 - 5500~5700" Band1, Ban2, Band3 Europe - 3 5G_ETSI2 ETSI "36~48, 52~64, - 100~140, 149~165" "5180~5240, 5260~5230 - 5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand - 4 5G_ETSI3 ETSI "36~48, 52~64, - 100~132, 149~165" - "5180~5240, 5260~5230 - 5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia - 5 5G_FCC1 FCC "36~48, 52~64, - 100~140, 149~165" - "5180~5240, 5260~5230 - 5500~5700, 5745~5825" Band1(5150~5250MHz), - Band2(5250~5350MHz), - Band3(5470~5725MHz), - Band4(5725~5850MHz)" US - 6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels - 7 5G_FCC3 FCC "36~48, 52~64, - 149~165" "5180~5240, 5260~5230 - 5745~5825" Band1, Ban2, Band4 India, Mexico - 8 5G_FCC4 FCC "36~48, 52~64, - 149~161" "5180~5240, 5260~5230 - 5745~5805" Band1, Ban2, - Band4(except CH 165)" Venezuela - 9 5G_FCC5 FCC 149~165 5745~5825 Band4 China - 10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel - 11 5G_FCC7 - 5G_IC1 FCC - IC" "36~48, 52~64, - 100~116, 136, 140, - 149~165" "5180~5240, 5260~5230 - 5500~5580, 5680, 5700, - 5745~5825" "Band1, Band2, - Band3(except 5600~5650MHz), - Band4" "US - Canada" - 12 5G_KCC1 KCC "36~48, 52~64, - 100~124, 149~165" "5180~5240, 5260~5230 - 5500~5620, 5745~5825" "Band1, Ban2, - Band3(5470~5650MHz), - Band4" Korea - 13 5G_MKK1 MKK "36~48, 52~64, - 100~140" "5180~5240, 5260~5230 - 5500~5700" W52, W53, W56 Japan - 14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53) - 15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56) - 16 5G_NCC1 NCC "56~64, - 100~116, 136, 140, - 149~165" "5260~5320 - 5500~5580, 5680, 5700, - 5745~5825" "Band2(except CH 52), - Band3(except 5600~5650MHz), - Band4" Taiwan - - -*/ - -// -// 2.4G CHannel -// -/* - - 2.4G Band Regulatory Domains RTL8192D - Channel Number Channel Frequency US Canada Europe Spain France Japan Japan 20M 40M - (MHz) (FCC) (IC) (ETSI) (MPHPT) - 1 2412 v v v v v - 2 2417 v v v v v - 3 2422 v v v v v v - 4 2427 v v v v v v - 5 2432 v v v v v v - 6 2437 v v v v v v - 7 2442 v v v v v v - 8 2447 v v v v v v - 9 2452 v v v v v v - 10 2457 v v v v v v v v - 11 2462 v v v v v v v v - 12 2467 v v v v v - 13 2472 v v v v - 14 2484 v v - - -*/ - - -// -// 5G Operating Channel -// -/* - - 5G Band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains - Channel Number Channel Frequency Global Global Global "US -(FCC 15.407)" "Canada -(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe -(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan -(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan -(NCC)" Venezuela - (MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) -"Band 1 -5.15GHz -~ -5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v -"Band 2 -5.25GHz -~ -5.35GHz -(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v - 56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v - 60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v - 64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v - -"Band 3 -5.47GHz -~ -5.725GHz -(DFS)" 100 5500 v v v v v v v v v v v v v - 104 5520 v v v v v v v v v v v - 108 5540 v v v v v v v v v v v v - 112 5560 v v v v v v v v v v v - 116 5580 v v v v v v v v v v v v v - 120 5600 v v v Indoor v Indoor v v v - 124 5620 v v v v Indoor v Indoor v v v - 128 5640 v v v Indoor v Indoor v v - 132 5660 v v v E v Indoor v Indoor v v - 136 5680 v v v v v v v v v - 140 5700 v v E v v v v v v v - 144 5720 E E E -"Band 4 -5.725GHz -~ -5.85GHz -(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v - 153 5765 v v v v v v v v v v v v - 157 5785 v v v v v v v v v v v v v - 161 5805 v v v v v v v v v v v v - 165 5825 v v P P v v v v v v v v v - 169 5845 P P P - 173 5865 P P P P - 177 5885 P P P -Channel Count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12 - E: FCC accepted the ask for CH144 from Accord. PS: 160MHz ¥Î 80MHz+80MHz¹ê²{¡H Argentina Belgium (¤ñ§Q®É) India Israel Russia - P: Customer's requirement from James. Australia The Netherlands (²üÄõ) Mexico Turkey Ukraine - New Zealand UK (­^°ê) Singapore - Brazil Switzerland (·ç¤h) - - -*/ - -/*---------------------------Define Local Constant---------------------------*/ - - -// define Maximum Power v.s each band for each region -// ISRAEL -// Format: -// RT_CHANNEL_DOMAIN_Region ={{{Chnl_Start, Chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num} */ -// RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} -// "NR" is non-release channle. -// Issue--- Israel--Russia--New Zealand -// DOMAIN_01= (2G_WORLD, 5G_NULL) -// DOMAIN_02= (2G_ETSI1, 5G_NULL) -// DOMAIN_03= (2G_FCC1, 5G_NULL) -// DOMAIN_04= (2G_MKK1, 5G_NULL) -// DOMAIN_05= (2G_ETSI2, 5G_NULL) -// DOMAIN_06= (2G_FCC1, 5G_FCC1) -// DOMAIN_07= (2G_WORLD, 5G_ETSI1) -// DOMAIN_08= (2G_MKK1, 5G_MKK1) -// DOMAIN_09= (2G_WORLD, 5G_KCC1) -// DOMAIN_10= (2G_WORLD, 5G_FCC2) -// DOMAIN_11= (2G_WORLD, 5G_FCC3)----india -// DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela -// DOMAIN_13= (2G_WORLD, 5G_FCC5)----China -// DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel -// DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada -// DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia -// DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia -// DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan -// DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan -// DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan -// DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan - - -static RT_CHANNEL_PLAN_MAXPWR ChnlPlanPwrMax_2G[] = { - - // 2G_WORLD, - {{1, 13, 20}, 1}, - - // 2G_ETSI1 - {{1, 13, 20}, 1}, - - /* RT_CHANNEL_DOMAIN_ETSI */ - {{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4}, - - // RT_CHANNEL_DOMAIN_MKK - {{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1}, - - // Add new channel plan mex power table. - // ...... - }; - - -/* -//===========================================1:(2G_WORLD, 5G_NULL) - -RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================2:(2G_ETSI1, 5G_NULL) - -RT_DOMAIN_02 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================3:(2G_FCC1, 5G_NULL) - -RT_DOMAIN_03 ={{{01,11,30}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================4:(2G_MKK1, 5G_NULL) - -RT_DOMAIN_04 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================5:(2G_ETSI2, 5G_NULL) - -RT_DOMAIN_05 ={{{10,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================6:(2G_FCC1, 5G_FCC1) - -RT_DOMAIN_06 ={{{01,13,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} - -//===========================================7:(2G_WORLD, 5G_ETSI1) - -RT_DOMAIN_07 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {NR,NR,0}}, 4} - -//===========================================8:(2G_MKK1, 5G_MKK1) - -RT_DOMAIN_08 ={{{01,14,23}, {36,48,23}, {52,64,23}, {100,140,23}, {NR,NR,0}}, 4} - -//===========================================9:(2G_WORLD, 5G_KCC1) - -RT_DOMAIN_09 ={{{01,13,20}, {36,48,17}, {52,64,23}, {100,124,23}, {149,165,23}}, 5} - -//===========================================10:(2G_WORLD, 5G_FCC2) - -RT_DOMAIN_10 ={{{01,13,20}, {36,48,17}, {NR,NR,0}, {NR,NR,0}, {149,165,30}}, 3} - -//===========================================11:(2G_WORLD, 5G_FCC3) -RT_DOMAIN_11 ={{{01,13,20}, {36,48,23}, {52,64,23}, {NR,NR,0}, {149,165,23}}, 4} - -//===========================================12:(2G_WORLD, 5G_FCC4) -RT_DOMAIN_12 ={{{01,13,20}, {36,48,24}, {52,64,24}, {NR,NR,0}, {149,161,27}}, 4} - -//===========================================13:(2G_WORLD, 5G_FCC5) -RT_DOMAIN_13 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {149,165,27}}, 2} - -//===========================================14:(2G_WORLD, 5G_FCC6) -RT_DOMAIN_14 ={{{01,13,20}, {36,48,17}, {52,64,17}, {NR,NR,0}, {NR,NR,0}}, 3} - -//===========================================15:(2G_FCC1, 5G_FCC7) -RT_DOMAIN_15 ={{{01,11,30}, {36,48,23}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} - -//===========================================16:(2G_WORLD, 5G_ETSI2) -RT_DOMAIN_16 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} - -//===========================================17:(2G_WORLD, 5G_ETSI3) -RT_DOMAIN_17 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,132,30}, {149,165,20}}, 5} - -//===========================================18:(2G_MKK1, 5G_MKK2) -RT_DOMAIN_18 ={{{01,14,23}, {36,48,23}, {52,64,23}, {NR,NR,0}, {NR,NR,0}}, 3} - -//===========================================19:(2G_MKK1, 5G_MKK3) -RT_DOMAIN_19 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {100,140,23}, {NR,NR,0}}, 2} - -//===========================================20:(2G_FCC1, 5G_NCC1) -RT_DOMAIN_20 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {100,140,24}, {149,165,30}}, 4} - -//===========================================21:(2G_FCC1, 5G_NCC2) -RT_DOMAIN_21 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {NR,NR,0}, {149,165,30}}, 3} - -//===========================================22:(2G_WORLD, 5G_FCC3) -RT_DOMAIN_22 ={{{01,13,24}, {36,48,20}, {52,64,24}, {NR,NR,0}, {149,165,30}}, 4} - -//===========================================23:(2G_WORLD, 5G_ETSI2) -RT_DOMAIN_23 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} - -*/ - -// -// Counter & Realtek Channel plan transfer table. -// -RT_CHNL_CTRY_TBL RtCtryChnlTbl[] = -{ - - { - RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" - "AL", - RT_2G_WORLD, - RT_5G_WORLD, - RT_CHANNEL_DOMAIN_UNDEFINED // 2G/5G world. - }, -#if 0 - { - RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" - "BB", - RT_2G_WORLD, - RT_5G_NULL, - RT_CHANNEL_DOMAIN_EFUSE_0x20 // 2G world. 5G_NULL - }, - - { - RT_CTRY_DE, // "Germany¼w°ê" - "DE", - RT_2G_WORLD, - RT_5G_ETSI1, - RT_CHANNEL_DOMAIN_EFUSE_0x26 - }, - - { - RT_CTRY_US, // "Germany¼w°ê" - "US", - RT_2G_FCC1, - RT_5G_FCC7, - RT_CHANNEL_DOMAIN_EFUSE_0x34 - }, - - { - RT_CTRY_JP, // "Germany¼w°ê" - "JP", - RT_2G_MKK1, - RT_5G_MKK1, - RT_CHANNEL_DOMAIN_EFUSE_0x34 - }, - - { - RT_CTRY_TW, // "Germany¼w°ê" - "TW", - RT_2G_FCC1, - RT_5G_NCC1, - RT_CHANNEL_DOMAIN_EFUSE_0x39 - }, -#endif - -}; // RtCtryChnlTbl - -// -// Realtek Defined Channel plan. -// -#if 0 - -static RT_CHANNEL_PLAN_NEW RtChnlPlan[] = -{ - // Channel Plan 0x20. - { - &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. - RT_CHANNEL_DOMAIN_EFUSE_0x20, // RT_CHANNEL_DOMAIN RT Channel Plan Define - RT_2G_WORLD, // RT_REGULATION_2G - RT_5G_NULL, // RT_REGULATION_5G - RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. - RT_SREQ_NA, // RT Channel plan special & customerize requirement. - - CHNL_RT_2G_WORLD, - CHNL_RT_2G_WORLD_SCAN_TYPE, - &ChnlPlanPwrMax_2G[0], - - CHNL_RT_5G_NULL, - CHNL_RT_5G_NULL_SCAN_TYPE, - - - }, - - // Channel Plan 0x26. - { - &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. - RT_CHANNEL_DOMAIN_EFUSE_0x26, // RT_CHANNEL_DOMAIN RT Channel Plan Define - RT_2G_WORLD, // RT_REGULATION_2G - RT_5G_ETSI1, // RT_REGULATION_5G - RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. - RT_SREQ_NA, // RT Channel plan special & customerize requirement. - - CHNL_RT_2G_WORLD, // 2G workd cannel - CHNL_RT_2G_WORLD_SCAN_TYPE, - &ChnlPlanPwrMax_2G[1], - - CHNL_RT_5G_ETSI1, - CHNL_RT_5G_ETSI1_SCAN_TYPE, - - } - - -}; -#endif - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/****************************************************************************** + + History: + Data Who Remark (Internal History) + + 05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft. + +******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" +#include "rtchnlplan.h" + + + +// +// Channel Plan Domain Code +// + +/* + Channel Plan Contents + Domain Code EEPROM Countries in Specific Domain + 2G RD 5G RD Bit[6:0] 2G 5G + Case Old Define 00h~1Fh Old Define Old Define + 1 2G_WORLD 5G_NULL 20h Worldwird 13 NA + 2 2G_ETSI1 5G_NULL 21h Europe 2G NA + 3 2G_FCC1 5G_NULL 22h US 2G NA + 4 2G_MKK1 5G_NULL 23h Japan 2G NA + 5 2G_ETSI2 5G_NULL 24h France 2G NA + 6 2G_FCC1 5G_FCC1 25h US 2G US 5G ¤K¤j°ê»{ÃÒ + 7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe ¤K¤j°ê»{ÃÒ + 8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G ¤K¤j°ê»{ÃÒ + 9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea ¤K¤j°ê»{ÃÒ + 10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels + 11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico + 12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela + 13 2G_WORLD 5G_FCC5 32h Worldwird 13 China + 14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel + 15 2G_FCC1 5G_FCC7 34h US 2G US/Canada ¤K¤j°ê»{ÃÒ + 16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand ¤K¤j°ê»{ÃÒ + 17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia + 18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53) + 19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56) + 20 2G_FCC1 5G_NCC1 39h US 2G Taiwan ¤K¤j°ê»{ÃÒ + + NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define + + + + + + 2.4G Regulatory Domains + Case 2G RD Regulation Channels Frequencyes Note Countries in Specific Domain + 1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13 + 2 2G_ETSI1 ETSI 1~13 2412~2472 Europe + 3 2G_FCC1 FCC 1~11 2412~2462 US + 4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan + 5 2G_ETSI2 ETSI 10~13 2457~2472 France + + + + + 5G Regulatory Domains + Case 5G RD Regulation Channels Frequencyes Note Countries in Specific Domain + 1 5G_NULL NA NA NA Do not support 5GHz + 2 5G_ETSI1 ETSI "36~48, 52~64, + 100~140" "5180~5240, 5260~5230 + 5500~5700" Band1, Ban2, Band3 Europe + 3 5G_ETSI2 ETSI "36~48, 52~64, + 100~140, 149~165" "5180~5240, 5260~5230 + 5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand + 4 5G_ETSI3 ETSI "36~48, 52~64, + 100~132, 149~165" + "5180~5240, 5260~5230 + 5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia + 5 5G_FCC1 FCC "36~48, 52~64, + 100~140, 149~165" + "5180~5240, 5260~5230 + 5500~5700, 5745~5825" Band1(5150~5250MHz), + Band2(5250~5350MHz), + Band3(5470~5725MHz), + Band4(5725~5850MHz)" US + 6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels + 7 5G_FCC3 FCC "36~48, 52~64, + 149~165" "5180~5240, 5260~5230 + 5745~5825" Band1, Ban2, Band4 India, Mexico + 8 5G_FCC4 FCC "36~48, 52~64, + 149~161" "5180~5240, 5260~5230 + 5745~5805" Band1, Ban2, + Band4(except CH 165)" Venezuela + 9 5G_FCC5 FCC 149~165 5745~5825 Band4 China + 10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel + 11 5G_FCC7 + 5G_IC1 FCC + IC" "36~48, 52~64, + 100~116, 136, 140, + 149~165" "5180~5240, 5260~5230 + 5500~5580, 5680, 5700, + 5745~5825" "Band1, Band2, + Band3(except 5600~5650MHz), + Band4" "US + Canada" + 12 5G_KCC1 KCC "36~48, 52~64, + 100~124, 149~165" "5180~5240, 5260~5230 + 5500~5620, 5745~5825" "Band1, Ban2, + Band3(5470~5650MHz), + Band4" Korea + 13 5G_MKK1 MKK "36~48, 52~64, + 100~140" "5180~5240, 5260~5230 + 5500~5700" W52, W53, W56 Japan + 14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53) + 15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56) + 16 5G_NCC1 NCC "56~64, + 100~116, 136, 140, + 149~165" "5260~5320 + 5500~5580, 5680, 5700, + 5745~5825" "Band2(except CH 52), + Band3(except 5600~5650MHz), + Band4" Taiwan + + +*/ + +// +// 2.4G CHannel +// +/* + + 2.4G Band Regulatory Domains RTL8192D + Channel Number Channel Frequency US Canada Europe Spain France Japan Japan 20M 40M + (MHz) (FCC) (IC) (ETSI) (MPHPT) + 1 2412 v v v v v + 2 2417 v v v v v + 3 2422 v v v v v v + 4 2427 v v v v v v + 5 2432 v v v v v v + 6 2437 v v v v v v + 7 2442 v v v v v v + 8 2447 v v v v v v + 9 2452 v v v v v v + 10 2457 v v v v v v v v + 11 2462 v v v v v v v v + 12 2467 v v v v v + 13 2472 v v v v + 14 2484 v v + + +*/ + + +// +// 5G Operating Channel +// +/* + + 5G Band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains + Channel Number Channel Frequency Global Global Global "US +(FCC 15.407)" "Canada +(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe +(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan +(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan +(NCC)" Venezuela + (MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) +"Band 1 +5.15GHz +~ +5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v +"Band 2 +5.25GHz +~ +5.35GHz +(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v + 56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v + 60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v + 64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v + +"Band 3 +5.47GHz +~ +5.725GHz +(DFS)" 100 5500 v v v v v v v v v v v v v + 104 5520 v v v v v v v v v v v + 108 5540 v v v v v v v v v v v v + 112 5560 v v v v v v v v v v v + 116 5580 v v v v v v v v v v v v v + 120 5600 v v v Indoor v Indoor v v v + 124 5620 v v v v Indoor v Indoor v v v + 128 5640 v v v Indoor v Indoor v v + 132 5660 v v v E v Indoor v Indoor v v + 136 5680 v v v v v v v v v + 140 5700 v v E v v v v v v v + 144 5720 E E E +"Band 4 +5.725GHz +~ +5.85GHz +(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v + 153 5765 v v v v v v v v v v v v + 157 5785 v v v v v v v v v v v v v + 161 5805 v v v v v v v v v v v v + 165 5825 v v P P v v v v v v v v v + 169 5845 P P P + 173 5865 P P P P + 177 5885 P P P +Channel Count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12 + E: FCC accepted the ask for CH144 from Accord. PS: 160MHz ¥Î 80MHz+80MHz¹ê²{¡H Argentina Belgium (¤ñ§Q®É) India Israel Russia + P: Customer's requirement from James. Australia The Netherlands (²üÄõ) Mexico Turkey Ukraine + New Zealand UK (­^°ê) Singapore + Brazil Switzerland (·ç¤h) + + +*/ + +/*---------------------------Define Local Constant---------------------------*/ + + +// define Maximum Power v.s each band for each region +// ISRAEL +// Format: +// RT_CHANNEL_DOMAIN_Region ={{{Chnl_Start, Chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num} */ +// RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} +// "NR" is non-release channle. +// Issue--- Israel--Russia--New Zealand +// DOMAIN_01= (2G_WORLD, 5G_NULL) +// DOMAIN_02= (2G_ETSI1, 5G_NULL) +// DOMAIN_03= (2G_FCC1, 5G_NULL) +// DOMAIN_04= (2G_MKK1, 5G_NULL) +// DOMAIN_05= (2G_ETSI2, 5G_NULL) +// DOMAIN_06= (2G_FCC1, 5G_FCC1) +// DOMAIN_07= (2G_WORLD, 5G_ETSI1) +// DOMAIN_08= (2G_MKK1, 5G_MKK1) +// DOMAIN_09= (2G_WORLD, 5G_KCC1) +// DOMAIN_10= (2G_WORLD, 5G_FCC2) +// DOMAIN_11= (2G_WORLD, 5G_FCC3)----india +// DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela +// DOMAIN_13= (2G_WORLD, 5G_FCC5)----China +// DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel +// DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada +// DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia +// DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia +// DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan +// DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan +// DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan +// DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan + + +static RT_CHANNEL_PLAN_MAXPWR ChnlPlanPwrMax_2G[] = { + + // 2G_WORLD, + {{1, 13, 20}, 1}, + + // 2G_ETSI1 + {{1, 13, 20}, 1}, + + /* RT_CHANNEL_DOMAIN_ETSI */ + {{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4}, + + // RT_CHANNEL_DOMAIN_MKK + {{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1}, + + // Add new channel plan mex power table. + // ...... + }; + + +/* +//===========================================1:(2G_WORLD, 5G_NULL) + +RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================2:(2G_ETSI1, 5G_NULL) + +RT_DOMAIN_02 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================3:(2G_FCC1, 5G_NULL) + +RT_DOMAIN_03 ={{{01,11,30}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================4:(2G_MKK1, 5G_NULL) + +RT_DOMAIN_04 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================5:(2G_ETSI2, 5G_NULL) + +RT_DOMAIN_05 ={{{10,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================6:(2G_FCC1, 5G_FCC1) + +RT_DOMAIN_06 ={{{01,13,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} + +//===========================================7:(2G_WORLD, 5G_ETSI1) + +RT_DOMAIN_07 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {NR,NR,0}}, 4} + +//===========================================8:(2G_MKK1, 5G_MKK1) + +RT_DOMAIN_08 ={{{01,14,23}, {36,48,23}, {52,64,23}, {100,140,23}, {NR,NR,0}}, 4} + +//===========================================9:(2G_WORLD, 5G_KCC1) + +RT_DOMAIN_09 ={{{01,13,20}, {36,48,17}, {52,64,23}, {100,124,23}, {149,165,23}}, 5} + +//===========================================10:(2G_WORLD, 5G_FCC2) + +RT_DOMAIN_10 ={{{01,13,20}, {36,48,17}, {NR,NR,0}, {NR,NR,0}, {149,165,30}}, 3} + +//===========================================11:(2G_WORLD, 5G_FCC3) +RT_DOMAIN_11 ={{{01,13,20}, {36,48,23}, {52,64,23}, {NR,NR,0}, {149,165,23}}, 4} + +//===========================================12:(2G_WORLD, 5G_FCC4) +RT_DOMAIN_12 ={{{01,13,20}, {36,48,24}, {52,64,24}, {NR,NR,0}, {149,161,27}}, 4} + +//===========================================13:(2G_WORLD, 5G_FCC5) +RT_DOMAIN_13 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {149,165,27}}, 2} + +//===========================================14:(2G_WORLD, 5G_FCC6) +RT_DOMAIN_14 ={{{01,13,20}, {36,48,17}, {52,64,17}, {NR,NR,0}, {NR,NR,0}}, 3} + +//===========================================15:(2G_FCC1, 5G_FCC7) +RT_DOMAIN_15 ={{{01,11,30}, {36,48,23}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} + +//===========================================16:(2G_WORLD, 5G_ETSI2) +RT_DOMAIN_16 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} + +//===========================================17:(2G_WORLD, 5G_ETSI3) +RT_DOMAIN_17 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,132,30}, {149,165,20}}, 5} + +//===========================================18:(2G_MKK1, 5G_MKK2) +RT_DOMAIN_18 ={{{01,14,23}, {36,48,23}, {52,64,23}, {NR,NR,0}, {NR,NR,0}}, 3} + +//===========================================19:(2G_MKK1, 5G_MKK3) +RT_DOMAIN_19 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {100,140,23}, {NR,NR,0}}, 2} + +//===========================================20:(2G_FCC1, 5G_NCC1) +RT_DOMAIN_20 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {100,140,24}, {149,165,30}}, 4} + +//===========================================21:(2G_FCC1, 5G_NCC2) +RT_DOMAIN_21 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {NR,NR,0}, {149,165,30}}, 3} + +//===========================================22:(2G_WORLD, 5G_FCC3) +RT_DOMAIN_22 ={{{01,13,24}, {36,48,20}, {52,64,24}, {NR,NR,0}, {149,165,30}}, 4} + +//===========================================23:(2G_WORLD, 5G_ETSI2) +RT_DOMAIN_23 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} + +*/ + +// +// Counter & Realtek Channel plan transfer table. +// +RT_CHNL_CTRY_TBL RtCtryChnlTbl[] = +{ + + { + RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" + "AL", + RT_2G_WORLD, + RT_5G_WORLD, + RT_CHANNEL_DOMAIN_UNDEFINED // 2G/5G world. + }, +#if 0 + { + RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" + "BB", + RT_2G_WORLD, + RT_5G_NULL, + RT_CHANNEL_DOMAIN_EFUSE_0x20 // 2G world. 5G_NULL + }, + + { + RT_CTRY_DE, // "Germany¼w°ê" + "DE", + RT_2G_WORLD, + RT_5G_ETSI1, + RT_CHANNEL_DOMAIN_EFUSE_0x26 + }, + + { + RT_CTRY_US, // "Germany¼w°ê" + "US", + RT_2G_FCC1, + RT_5G_FCC7, + RT_CHANNEL_DOMAIN_EFUSE_0x34 + }, + + { + RT_CTRY_JP, // "Germany¼w°ê" + "JP", + RT_2G_MKK1, + RT_5G_MKK1, + RT_CHANNEL_DOMAIN_EFUSE_0x34 + }, + + { + RT_CTRY_TW, // "Germany¼w°ê" + "TW", + RT_2G_FCC1, + RT_5G_NCC1, + RT_CHANNEL_DOMAIN_EFUSE_0x39 + }, +#endif + +}; // RtCtryChnlTbl + +// +// Realtek Defined Channel plan. +// +#if 0 + +static RT_CHANNEL_PLAN_NEW RtChnlPlan[] = +{ + // Channel Plan 0x20. + { + &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. + RT_CHANNEL_DOMAIN_EFUSE_0x20, // RT_CHANNEL_DOMAIN RT Channel Plan Define + RT_2G_WORLD, // RT_REGULATION_2G + RT_5G_NULL, // RT_REGULATION_5G + RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. + RT_SREQ_NA, // RT Channel plan special & customerize requirement. + + CHNL_RT_2G_WORLD, + CHNL_RT_2G_WORLD_SCAN_TYPE, + &ChnlPlanPwrMax_2G[0], + + CHNL_RT_5G_NULL, + CHNL_RT_5G_NULL_SCAN_TYPE, + + + }, + + // Channel Plan 0x26. + { + &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. + RT_CHANNEL_DOMAIN_EFUSE_0x26, // RT_CHANNEL_DOMAIN RT Channel Plan Define + RT_2G_WORLD, // RT_REGULATION_2G + RT_5G_ETSI1, // RT_REGULATION_5G + RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. + RT_SREQ_NA, // RT Channel plan special & customerize requirement. + + CHNL_RT_2G_WORLD, // 2G workd cannel + CHNL_RT_2G_WORLD_SCAN_TYPE, + &ChnlPlanPwrMax_2G[1], + + CHNL_RT_5G_ETSI1, + CHNL_RT_5G_ETSI1_SCAN_TYPE, + + } + + +}; +#endif + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtchnlplan.h b/package/kernel/rtl8192cd/phydm/rtchnlplan.h index 37786cf8f00..78a31dcd12e 100644 --- a/package/kernel/rtl8192cd/phydm/rtchnlplan.h +++ b/package/kernel/rtl8192cd/phydm/rtchnlplan.h @@ -1,699 +1,699 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __RT_CHANNELPLAN_H__ -#define __RT_CHANNELPLAN_H__ - -typedef enum _RT_CHANNEL_DOMAIN_NEW -{ - - //===== Add new channel plan above this line ===============// - - // For new architecture we define different 2G/5G CH area for all country. - // 2.4 G only - RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, - RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, - RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, - RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, - RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, - // 2.4 G + 5G type 1 - RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, - RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, - //RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, - // ..... - - RT_CHANNEL_DOMAIN_MAX_NEW, - -}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW; - - -#if 0 -#define DOMAIN_CODE_2G_WORLD \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define DOMAIN_CODE_2G_ETSI1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define DOMAIN_CODE_2G_ETSI2 \ - {1,2,3,4,5,6,7,8,9,10,11}, 11 -#define DOMAIN_CODE_2G_FCC1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 -#define DOMAIN_CODE_2G_MKK1 \ - {10,11,12,13}, 4 - -#define DOMAIN_CODE_5G_ETSI1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define DOMAIN_CODE_5G_ETSI2 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_ETSI3 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define DOMAIN_CODE_5G_FCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_FCC2 \ - {36,40,44,48,149,153,157,161,165}, 9 -#define DOMAIN_CODE_5G_FCC3 \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define DOMAIN_CODE_5G_FCC4 \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define DOMAIN_CODE_5G_FCC5 \ - {149,153,157,161,165}, 5 -#define DOMAIN_CODE_5G_FCC6 \ - {36,40,44,48,52,56,60,64}, 8 -#define DOMAIN_CODE_5G_FCC7 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_IC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_KCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_MKK1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define DOMAIN_CODE_5G_MKK2 \ - {36,40,44,48,52,56,60,64}, 8 -#define DOMAIN_CODE_5G_MKK3 \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define DOMAIN_CODE_5G_NCC1 \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_NCC2 \ - {56,60,64,149,153,157,161,165}, 8 -#define UNDEFINED \ - {0}, 0 -#endif - -// -// -// -/* - -Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz - 2G 5G Ch# of 40MHz -"Albaniaªüº¸¤Ú¥§¨È" AL Local Test - -"Algeriaªüº¸¤Î§Q¨È" DZ CE TCF - -"Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" AG 2G_WORLD FCC TCF - -"Argentinaªü®Ú§Ê" AR 2G_WORLD Local Test - -"Armenia¨È¬ü¥§¨È" AM 2G_WORLD ETSI - -"Arubaªü¾|¤Ú®q" AW 2G_WORLD FCC TCF - -"Australia¿D¬w" AU 2G_WORLD 5G_ETSI2 - -"Austria¶ø¦a§Q" AT 2G_WORLD 5G_ETSI1 CE - -"Azerbaijanªü¶ë«ô¾Ê" AZ 2G_WORLD CE TCF - -"Bahamas¤Ú«¢°¨" BS 2G_WORLD - -"Barbados¤Ú¤Ú¦h´µ" BB 2G_WORLD FCC TCF - -"Belgium¤ñ§Q®É" BE 2G_WORLD 5G_ETSI1 CE - -"Bermuda¦Ê¼}¹F" BM 2G_WORLD FCC TCF - -"Brazil¤Ú¦è" BR 2G_WORLD Local Test - -"Bulgaria«O¥[§Q¨È" BG 2G_WORLD 5G_ETSI1 CE - -"Canada¥[®³¤j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC - -"Cayman Islands¶}°Ò¸s®q" KY 2G_WORLD 5G_ETSI1 CE - -"Chile´¼§Q" CL 2G_WORLD FCC TCF - -"China¤¤°ê" CN 2G_WORLD 5G_FCC5 «H³¡?¡i2002¡j353? - -"Columbia­ô­Û¤ñ¨È" CO 2G_WORLD Voluntary - -"Costa Rica­ô´µ¹F¾¤¥[" CR 2G_WORLD FCC TCF - -"Cyprus¶ë®ú¸ô´µ" CY 2G_WORLD 5G_ETSI1 CE - -"Czech ±¶§J" CZ 2G_WORLD 5G_ETSI1 CE - -"Denmark¤¦³Á" DK 2G_WORLD 5G_ETSI1 CE - -"Dominican Republic¦h©ú¥§¥[¦@©M°ê" DO 2G_WORLD FCC TCF - -"Egypt®J¤Î" EG 2G_WORLD CE T CF - -"El SalvadorÂĺ¸¥Ë¦h" SV 2G_WORLD Voluntary - -"Estonia·R¨F¥§¨È" EE 2G_WORLD 5G_ETSI1 CE - -"FinlandªâÄõ" FI 2G_WORLD 5G_ETSI1 CE - -"Franceªk°ê" FR 5G_E TSI1 CE - -"Germany¼w°ê" DE 2G_WORLD 5G_ETSI1 CE - -"Greece §Æþ" GR 2G_WORLD 5G_ETSI1 CE - -"GuamÃö®q" GU 2G_WORLD - -"Guatemala¥Ê¦a°¨©Ô" GT 2G_WORLD - -"Haiti®ü¦a" HT 2G_WORLD FCC TCF - -"Honduras§»³£©Ô´µ" HN 2G_WORLD FCC TCF - -"Hungary¦I¤ú§Q" HU 2G_WORLD 5G_ETSI1 CE - -"Iceland¦B®q" IS 2G_WORLD 5G_ETSI1 CE - -"India¦L«×" IN 2G_WORLD 5G_FCC3 FCC/CE TCF - -"Ireland·Rº¸Äõ" IE 2G_WORLD 5G_ETSI1 CE - -"Israel¥H¦â¦C" IL 5G_F CC6 CE TCF - -"Italy¸q¤j§Q" IT 2G_WORLD 5G_ETSI1 CE - -"Japan¤é¥»" JP 2G_MKK1 5G_MKK1 MKK MKK - -"KoreaÁú°ê" KR 2G_WORLD 5G_KCC1 KCC KCC - -"Latvia©Ô²æºû¨È" LV 2G_WORLD 5G_ETSI1 CE - -"Lithuania¥ß³³©{" LT 2G_WORLD 5G_ETSI1 CE - -"Luxembourg¿c´Ë³ù" LU 2G_WORLD 5G_ETSI1 CE - -"Malaysia°¨¨Ó¦è¨È" MY 2G_WORLD Local Test - -"Malta°¨º¸¥L" MT 2G_WORLD 5G_ETSI1 CE - -"Mexico¾¥¦è­ô" MX 2G_WORLD 5G_FCC3 Local Test - -"Morocco¼¯¬¥­ô" MA CE TCF - -"Netherlands²üÄõ" NL 2G_WORLD 5G_ETSI1 CE - -"New Zealand¯Ã¦èÄõ" NZ 2G_WORLD 5G_ETSI2 - -"Norway®¿«Â" NO 2G_WORLD 5G_ETSI1 CE - -"Panama¤Ú®³°¨ " PA 2G_FCC1 Voluntary - -"Philippinesµá«ß»«" PH 2G_WORLD FCC TCF - -"PolandªiÄõ" PL 2G_WORLD 5G_ETSI1 CE - -"Portugal¸²µå¤ú" PT 2G_WORLD 5G_ETSI1 CE - -"Romaniaù°¨¥§¨È" RO 2G_WORLD 5G_ETSI1 CE - -"Russia«Xù´µ" RU 2G_WORLD 5G_ETSI3 CE TCF - -"Saudi Arabia¨F¦aªü©Ô§B" SA 2G_WORLD CE TCF - -"Singapore·s¥[©Y" SG 2G_WORLD - -"Slovakia´µ¬¥¥ï§J" SK 2G_WORLD 5G_ETSI1 CE - -"Slovenia´µ¬¥ºû¥§¨È" SI 2G_WORLD 5G_ETSI1 CE - -"South Africa«n«D" ZA 2G_WORLD CE TCF - -"Spain¦è¯Z¤ú" ES 5G_ETSI1 CE - -"Sweden·ç¨å" SE 2G_WORLD 5G_ETSI1 CE - -"Switzerland·ç¤h" CH 2G_WORLD 5G_ETSI1 CE - -"Taiwan»OÆW" TW 2G_FCC1 5G_NCC1 NCC - -"Thailand®õ°ê" TH 2G_WORLD FCC/CE TCF - -"Turkey¤g¦Õ¨ä" TR 2G_WORLD - -"Ukraine¯Q§JÄõ" UA 2G_WORLD Local Test - -"United Kingdom­^°ê" GB 2G_WORLD 5G_ETSI1 CE ETSI - -"United States¬ü°ê" US 2G_FCC1 5G_FCC7 FCC FCC - -"Venezuela©e¤º·ç©Ô" VE 2G_WORLD 5G_FCC4 FCC TCF - -"Vietnam¶V«n" VN 2G_WORLD FCC/CE TCF - - - -*/ - -// Counter abbervation. -typedef enum _RT_COUNTRY_DEFINE_NUM -{ - RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" - RT_CTRY_DZ, // "Algeriaªüº¸¤Î§Q¨È" - RT_CTRY_AG, // "Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" - RT_CTRY_AR, // "Argentinaªü®Ú§Ê" - RT_CTRY_AM, // "Armenia¨È¬ü¥§¨È" - RT_CTRY_AW, // "Arubaªü¾|¤Ú®q" - RT_CTRY_AU, // "Australia¿D¬w" - RT_CTRY_AT, // "Austria¶ø¦a§Q" - RT_CTRY_AZ, // "Azerbaijanªü¶ë«ô¾Ê" - RT_CTRY_BS, // "Bahamas¤Ú«¢°¨" - RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" - RT_CTRY_BE, // "Belgium¤ñ§Q®É" - RT_CTRY_BM, // "Bermuda¦Ê¼}¹F" - RT_CTRY_BR, // "Brazil¤Ú¦è" - RT_CTRY_BG, // "Bulgaria«O¥[§Q¨È" - RT_CTRY_CA, // "Canada¥[®³¤j" - RT_CTRY_KY, // "Cayman Islands¶}°Ò¸s®q" - RT_CTRY_CL, // "Chile´¼§Q" - RT_CTRY_CN, // "China¤¤°ê" - RT_CTRY_CO, // "Columbia­ô­Û¤ñ¨È" - RT_CTRY_CR, // "Costa Rica­ô´µ¹F¾¤¥[" - RT_CTRY_CY, // "Cyprus¶ë®ú¸ô´µ" - RT_CTRY_CZ, // "Czech ±¶§J" - RT_CTRY_DK, // "Denmark¤¦³Á" - RT_CTRY_DO, // "Dominican Republic¦h©ú¥§¥[¦@©M°ê" - RT_CTRY_CE, // "Egypt®J¤Î" EG 2G_WORLD - RT_CTRY_SV, // "El SalvadorÂĺ¸¥Ë¦h" - RT_CTRY_EE, // "Estonia·R¨F¥§¨È" - RT_CTRY_FI, // "FinlandªâÄõ" - RT_CTRY_FR, // "Franceªk°ê" - RT_CTRY_DE, // "Germany¼w°ê" - RT_CTRY_GR, // "Greece §Æþ" - RT_CTRY_GU, // "GuamÃö®q" - RT_CTRY_GT, // "Guatemala¥Ê¦a°¨©Ô" - RT_CTRY_HT, // "Haiti®ü¦a" - RT_CTRY_HN, // "Honduras§»³£©Ô´µ" - RT_CTRY_HU, // "Hungary¦I¤ú§Q" - RT_CTRY_IS, // "Iceland¦B®q" - RT_CTRY_IN, // "India¦L«×" - RT_CTRY_IE, // "Ireland·Rº¸Äõ" - RT_CTRY_IL, // "Israel¥H¦â¦C" - RT_CTRY_IT, // "Italy¸q¤j§Q" - RT_CTRY_JP, // "Japan¤é¥»" - RT_CTRY_KR, // "KoreaÁú°ê" - RT_CTRY_LV, // "Latvia©Ô²æºû¨È" - RT_CTRY_LT, // "Lithuania¥ß³³©{" - RT_CTRY_LU, // "Luxembourg¿c´Ë³ù" - RT_CTRY_MY, // "Malaysia°¨¨Ó¦è¨È" - RT_CTRY_MT, // "Malta°¨º¸¥L" - RT_CTRY_MX, // "Mexico¾¥¦è­ô" - RT_CTRY_MA, // "Morocco¼¯¬¥­ô" - RT_CTRY_NL, // "Netherlands²üÄõ" - RT_CTRY_NZ, // "New Zealand¯Ã¦èÄõ" - RT_CTRY_NO, // "Norway®¿«Â" - RT_CTRY_PA, // "Panama¤Ú®³°¨ " - RT_CTRY_PH, // "Philippinesµá«ß»«" - RT_CTRY_PL, // "PolandªiÄõ" - RT_CTRY_PT, // "Portugal¸²µå¤ú" - RT_CTRY_RO, // "Romaniaù°¨¥§¨È" - RT_CTRY_RU, // "Russia«Xù´µ" - RT_CTRY_SA, // "Saudi Arabia¨F¦aªü©Ô§B" - RT_CTRY_SG, // "Singapore·s¥[©Y" - RT_CTRY_SK, // "Slovakia´µ¬¥¥ï§J" - RT_CTRY_SI, // "Slovenia´µ¬¥ºû¥§¨È" - RT_CTRY_ZA, // "South Africa«n«D" - RT_CTRY_ES, // "Spain¦è¯Z¤ú" - RT_CTRY_SE, // "Sweden·ç¨å" - RT_CTRY_CH, // "Switzerland·ç¤h" - RT_CTRY_TW, // "Taiwan»OÆW" - RT_CTRY_TH, // "Thailand®õ°ê" - RT_CTRY_TR, // "Turkey¤g¦Õ¨ä" - RT_CTRY_UA, // "Ukraine¯Q§JÄõ" - RT_CTRY_GB, // "United Kingdom­^°ê" - RT_CTRY_US, // "United States¬ü°ê" - RT_CTRY_VE, // "Venezuela©e¤º·ç©Ô" - RT_CTRY_VN, // "Vietnam¶V«n" - RT_CTRY_MAX, // - -}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME; - -// Scan type including active and passive scan. -typedef enum _RT_SCAN_TYPE_NEW -{ - SCAN_NULL, - SCAN_ACT, - SCAN_PAS, - SCAN_BOTH, -}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW; - - -// Power table sample. - -typedef struct _RT_CHNL_PLAN_LIMIT -{ - u2Byte Chnl_Start; - u2Byte Chnl_end; - - u2Byte Freq_Start; - u2Byte Freq_end; -}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT; - - -// -// 2.4G Regulatory Domains -// -typedef enum _RT_REGULATION_DOMAIN_2G -{ - RT_2G_NULL, - RT_2G_WORLD, - RT_2G_ETSI1, - RT_2G_FCC1, - RT_2G_MKK1, - RT_2G_ETSI2 - -}RT_REGULATION_2G, *PRT_REGULATION_2G; - - -//typedef struct _RT_CHANNEL_BEHAVIOR -//{ -// u1Byte Chnl; -// RT_SCAN_TYPE_NEW -// -//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; - -//typedef struct _RT_CHANNEL_PLAN_TYPE -//{ -// RT_CHANNEL_BEHAVIOR -// u1Byte Chnl_num; -//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; - -// -// 2.4G Channel Number -// Channel definition & number -// -#define CHNL_RT_2G_NULL \ - {0}, 0 -#define CHNL_RT_2G_WORLD \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define CHNL_RT_2G_WORLD_TEST \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 - -#define CHNL_RT_2G_EFSI1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define CHNL_RT_2G_FCC1 \ - {1,2,3,4,5,6,7,8,9,10,11}, 11 -#define CHNL_RT_2G_MKK1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 -#define CHNL_RT_2G_ETSI2 \ - {10,11,12,13}, 4 - -// -// 2.4G Channel Active or passive scan. -// -#define CHNL_RT_2G_NULL_SCAN_TYPE \ - {SCAN_NULL} -#define CHNL_RT_2G_WORLD_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,0,0} -#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_FCC1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_MKK1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ - {1,1,1,1} - - -// -// 2.4G Band & Frequency Section -// Freqency start & end / band number -// -#define FREQ_RT_2G_NULL \ - {0}, 0 - // Passive scan CH 12, 13 -#define FREQ_RT_2G_WORLD \ - {2412, 2472}, 1 -#define FREQ_RT_2G_EFSI1 \ - {2412, 2472}, 1 -#define FREQ_RT_2G_FCC1 \ - {2412, 2462}, 1 -#define FREQ_RT_2G_MKK1 \ - {2412, 2484}, 1 -#define FREQ_RT_2G_ETSI2 \ - {2457, 2472}, 1 - - -// -// 5G Regulatory Domains -// -typedef enum _RT_REGULATION_DOMAIN_5G -{ - RT_5G_NULL, - RT_5G_WORLD, - RT_5G_ETSI1, - RT_5G_ETSI2, - RT_5G_ETSI3, - RT_5G_FCC1, - RT_5G_FCC2, - RT_5G_FCC3, - RT_5G_FCC4, - RT_5G_FCC5, - RT_5G_FCC6, - RT_5G_FCC7, - RT_5G_IC1, - RT_5G_KCC1, - RT_5G_MKK1, - RT_5G_MKK2, - RT_5G_MKK3, - RT_5G_NCC1, - -}RT_REGULATION_5G, *PRT_REGULATION_5G; - -// -// 5G Channel Number -// -#define CHNL_RT_5G_NULL \ - {0}, 0 -#define CHNL_RT_5G_WORLD \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_ETSI1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_ETSI2 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define CHNL_RT_5G_ETSI3 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_FCC1 \ - {36,40,44,48,149,153,157,161,165}, 9 -#define CHNL_RT_5G_FCC2 \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define CHNL_RT_5G_FCC3 \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define CHNL_RT_5G_FCC4 \ - {149,153,157,161,165}, 5 -#define CHNL_RT_5G_FCC5 \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_FCC6 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_FCC7 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_IC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define CHNL_RT_5G_KCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_MKK1 \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_MKK2 \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define CHNL_RT_5G_MKK3 \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_NCC1 \ - {56,60,64,149,153,157,161,165}, 8 - -// -// 5G Channel Active or passive scan. -// -#define CHNL_RT_5G_NULL_SCAN_TYPE \ - {SCAN_NULL} -#define CHNL_RT_5G_WORLD_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_FCC1_SCAN_TYPE \ - {36,40,44,48,149,153,157,161,165}, 9 -#define CHNL_RT_5G_FCC2_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define CHNL_RT_5G_FCC3_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define CHNL_RT_5G_FCC4_SCAN_TYPE \ - {149,153,157,161,165}, 5 -#define CHNL_RT_5G_FCC5_SCAN_TYPE \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_FCC6_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_FCC7_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_IC1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define CHNL_RT_5G_KCC1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_MKK1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_MKK2_SCAN_TYPE \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define CHNL_RT_5G_MKK3_SCAN_TYPE \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_NCC1_SCAN_TYPE \ - {56,60,64,149,153,157,161,165}, 8 - -// -// Global Regulation -// -typedef enum _RT_REGULATION_COMMON -{ - RT_WORLD, - RT_FCC, - RT_MKK, - RT_ETSI, - RT_IC, - RT_CE, - RT_NCC, - -}RT_REGULATION_CMN, *PRT_REGULATION_CMN; - - - -// -// Special requirement for different regulation domain. -// For internal test or customerize special request. -// -typedef enum _RT_CHNLPLAN_SREQ -{ - RT_SREQ_NA = 0x0, - RT_SREQ_2G_ADHOC_11N = 0x00000001, - RT_SREQ_2G_ADHOC_11B = 0x00000002, - RT_SREQ_2G_ALL_PASS = 0x00000004, - RT_SREQ_2G_ALL_ACT = 0x00000008, - RT_SREQ_5G_ADHOC_11N = 0x00000010, - RT_SREQ_5G_ADHOC_11AC = 0x00000020, - RT_SREQ_5G_ALL_PASS = 0x00000040, - RT_SREQ_5G_ALL_ACT = 0x00000080, - RT_SREQ_C1_PLAN = 0x00000100, - RT_SREQ_C2_PLAN = 0x00000200, - RT_SREQ_C3_PLAN = 0x00000400, - RT_SREQ_C4_PLAN = 0x00000800, - RT_SREQ_NFC_ON = 0x00001000, - RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ - -}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ; - - -// -// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table -// -// -typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE -{ - // - // Define countery domain and corresponding - // - RT_COUNTRY_NAME Country_Enum; - char Country_Name[3]; - - //char Domain_Name[12]; - RT_REGULATION_2G Domain_2G; - - RT_REGULATION_5G Domain_5G; - - RT_CHANNEL_DOMAIN RtChDomain; - //u1Byte Country_Area; - -}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL; - - -#define RT_MAX_CHNL_NUM_2G 13 -#define RT_MAX_CHNL_NUM_5G 44 - -// Power table sample. - -typedef struct _RT_CHNL_PLAN_PWR_LIMIT -{ - u2Byte Chnl_Start; - u2Byte Chnl_end; - u1Byte dB_Max; - u2Byte mW_Max; -}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT; - - -#define RT_MAX_BAND_NUM 5 - -typedef struct _RT_CHANNEL_PLAN_MAXPWR -{ -// STRING_T - RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM]; - u1Byte Band_Useful_Num; - - -}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR; - - -// -// Power By Rate Table. -// - - - -typedef struct _RT_CHANNEL_PLAN_NEW -{ - // - // Define countery domain and corresponding - // - //char Country_Name[36]; - //u1Byte Country_Enum; - - //char Domain_Name[12]; - - - PRT_CHNL_CTRY_TBL pCtryTransfer; - - RT_CHANNEL_DOMAIN RtChDomain; - - RT_REGULATION_2G Domain_2G; - - RT_REGULATION_5G Domain_5G; - - RT_REGULATION_CMN Regulator; - - RT_CHNLPLAN_SREQ ChnlSreq; - - //RT_CHNL_PLAN_LIMIT RtChnl; - - u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD - u1Byte Len2G; - u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE - //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD - - u1Byte Chnl5G[MAX_CHANNEL_NUM]; - u1Byte Len5G; - u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM]; - //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD - - RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr; - - -}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW; - - -#endif // __RT_CHANNELPLAN_H__ - - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __RT_CHANNELPLAN_H__ +#define __RT_CHANNELPLAN_H__ + +typedef enum _RT_CHANNEL_DOMAIN_NEW +{ + + //===== Add new channel plan above this line ===============// + + // For new architecture we define different 2G/5G CH area for all country. + // 2.4 G only + RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, + RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, + RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, + RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, + RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, + // 2.4 G + 5G type 1 + RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, + //RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, + // ..... + + RT_CHANNEL_DOMAIN_MAX_NEW, + +}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW; + + +#if 0 +#define DOMAIN_CODE_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI2 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define DOMAIN_CODE_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define DOMAIN_CODE_2G_MKK1 \ + {10,11,12,13}, 4 + +#define DOMAIN_CODE_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define DOMAIN_CODE_5G_FCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_FCC2 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define DOMAIN_CODE_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define DOMAIN_CODE_5G_FCC4 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define DOMAIN_CODE_5G_FCC5 \ + {149,153,157,161,165}, 5 +#define DOMAIN_CODE_5G_FCC6 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_MKK1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_MKK2 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_MKK3 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define DOMAIN_CODE_5G_NCC1 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_NCC2 \ + {56,60,64,149,153,157,161,165}, 8 +#define UNDEFINED \ + {0}, 0 +#endif + +// +// +// +/* + +Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz + 2G 5G Ch# of 40MHz +"Albaniaªüº¸¤Ú¥§¨È" AL Local Test + +"Algeriaªüº¸¤Î§Q¨È" DZ CE TCF + +"Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" AG 2G_WORLD FCC TCF + +"Argentinaªü®Ú§Ê" AR 2G_WORLD Local Test + +"Armenia¨È¬ü¥§¨È" AM 2G_WORLD ETSI + +"Arubaªü¾|¤Ú®q" AW 2G_WORLD FCC TCF + +"Australia¿D¬w" AU 2G_WORLD 5G_ETSI2 + +"Austria¶ø¦a§Q" AT 2G_WORLD 5G_ETSI1 CE + +"Azerbaijanªü¶ë«ô¾Ê" AZ 2G_WORLD CE TCF + +"Bahamas¤Ú«¢°¨" BS 2G_WORLD + +"Barbados¤Ú¤Ú¦h´µ" BB 2G_WORLD FCC TCF + +"Belgium¤ñ§Q®É" BE 2G_WORLD 5G_ETSI1 CE + +"Bermuda¦Ê¼}¹F" BM 2G_WORLD FCC TCF + +"Brazil¤Ú¦è" BR 2G_WORLD Local Test + +"Bulgaria«O¥[§Q¨È" BG 2G_WORLD 5G_ETSI1 CE + +"Canada¥[®³¤j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC + +"Cayman Islands¶}°Ò¸s®q" KY 2G_WORLD 5G_ETSI1 CE + +"Chile´¼§Q" CL 2G_WORLD FCC TCF + +"China¤¤°ê" CN 2G_WORLD 5G_FCC5 «H³¡?¡i2002¡j353? + +"Columbia­ô­Û¤ñ¨È" CO 2G_WORLD Voluntary + +"Costa Rica­ô´µ¹F¾¤¥[" CR 2G_WORLD FCC TCF + +"Cyprus¶ë®ú¸ô´µ" CY 2G_WORLD 5G_ETSI1 CE + +"Czech ±¶§J" CZ 2G_WORLD 5G_ETSI1 CE + +"Denmark¤¦³Á" DK 2G_WORLD 5G_ETSI1 CE + +"Dominican Republic¦h©ú¥§¥[¦@©M°ê" DO 2G_WORLD FCC TCF + +"Egypt®J¤Î" EG 2G_WORLD CE T CF + +"El SalvadorÂĺ¸¥Ë¦h" SV 2G_WORLD Voluntary + +"Estonia·R¨F¥§¨È" EE 2G_WORLD 5G_ETSI1 CE + +"FinlandªâÄõ" FI 2G_WORLD 5G_ETSI1 CE + +"Franceªk°ê" FR 5G_E TSI1 CE + +"Germany¼w°ê" DE 2G_WORLD 5G_ETSI1 CE + +"Greece §Æþ" GR 2G_WORLD 5G_ETSI1 CE + +"GuamÃö®q" GU 2G_WORLD + +"Guatemala¥Ê¦a°¨©Ô" GT 2G_WORLD + +"Haiti®ü¦a" HT 2G_WORLD FCC TCF + +"Honduras§»³£©Ô´µ" HN 2G_WORLD FCC TCF + +"Hungary¦I¤ú§Q" HU 2G_WORLD 5G_ETSI1 CE + +"Iceland¦B®q" IS 2G_WORLD 5G_ETSI1 CE + +"India¦L«×" IN 2G_WORLD 5G_FCC3 FCC/CE TCF + +"Ireland·Rº¸Äõ" IE 2G_WORLD 5G_ETSI1 CE + +"Israel¥H¦â¦C" IL 5G_F CC6 CE TCF + +"Italy¸q¤j§Q" IT 2G_WORLD 5G_ETSI1 CE + +"Japan¤é¥»" JP 2G_MKK1 5G_MKK1 MKK MKK + +"KoreaÁú°ê" KR 2G_WORLD 5G_KCC1 KCC KCC + +"Latvia©Ô²æºû¨È" LV 2G_WORLD 5G_ETSI1 CE + +"Lithuania¥ß³³©{" LT 2G_WORLD 5G_ETSI1 CE + +"Luxembourg¿c´Ë³ù" LU 2G_WORLD 5G_ETSI1 CE + +"Malaysia°¨¨Ó¦è¨È" MY 2G_WORLD Local Test + +"Malta°¨º¸¥L" MT 2G_WORLD 5G_ETSI1 CE + +"Mexico¾¥¦è­ô" MX 2G_WORLD 5G_FCC3 Local Test + +"Morocco¼¯¬¥­ô" MA CE TCF + +"Netherlands²üÄõ" NL 2G_WORLD 5G_ETSI1 CE + +"New Zealand¯Ã¦èÄõ" NZ 2G_WORLD 5G_ETSI2 + +"Norway®¿«Â" NO 2G_WORLD 5G_ETSI1 CE + +"Panama¤Ú®³°¨ " PA 2G_FCC1 Voluntary + +"Philippinesµá«ß»«" PH 2G_WORLD FCC TCF + +"PolandªiÄõ" PL 2G_WORLD 5G_ETSI1 CE + +"Portugal¸²µå¤ú" PT 2G_WORLD 5G_ETSI1 CE + +"Romaniaù°¨¥§¨È" RO 2G_WORLD 5G_ETSI1 CE + +"Russia«Xù´µ" RU 2G_WORLD 5G_ETSI3 CE TCF + +"Saudi Arabia¨F¦aªü©Ô§B" SA 2G_WORLD CE TCF + +"Singapore·s¥[©Y" SG 2G_WORLD + +"Slovakia´µ¬¥¥ï§J" SK 2G_WORLD 5G_ETSI1 CE + +"Slovenia´µ¬¥ºû¥§¨È" SI 2G_WORLD 5G_ETSI1 CE + +"South Africa«n«D" ZA 2G_WORLD CE TCF + +"Spain¦è¯Z¤ú" ES 5G_ETSI1 CE + +"Sweden·ç¨å" SE 2G_WORLD 5G_ETSI1 CE + +"Switzerland·ç¤h" CH 2G_WORLD 5G_ETSI1 CE + +"Taiwan»OÆW" TW 2G_FCC1 5G_NCC1 NCC + +"Thailand®õ°ê" TH 2G_WORLD FCC/CE TCF + +"Turkey¤g¦Õ¨ä" TR 2G_WORLD + +"Ukraine¯Q§JÄõ" UA 2G_WORLD Local Test + +"United Kingdom­^°ê" GB 2G_WORLD 5G_ETSI1 CE ETSI + +"United States¬ü°ê" US 2G_FCC1 5G_FCC7 FCC FCC + +"Venezuela©e¤º·ç©Ô" VE 2G_WORLD 5G_FCC4 FCC TCF + +"Vietnam¶V«n" VN 2G_WORLD FCC/CE TCF + + + +*/ + +// Counter abbervation. +typedef enum _RT_COUNTRY_DEFINE_NUM +{ + RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" + RT_CTRY_DZ, // "Algeriaªüº¸¤Î§Q¨È" + RT_CTRY_AG, // "Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" + RT_CTRY_AR, // "Argentinaªü®Ú§Ê" + RT_CTRY_AM, // "Armenia¨È¬ü¥§¨È" + RT_CTRY_AW, // "Arubaªü¾|¤Ú®q" + RT_CTRY_AU, // "Australia¿D¬w" + RT_CTRY_AT, // "Austria¶ø¦a§Q" + RT_CTRY_AZ, // "Azerbaijanªü¶ë«ô¾Ê" + RT_CTRY_BS, // "Bahamas¤Ú«¢°¨" + RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" + RT_CTRY_BE, // "Belgium¤ñ§Q®É" + RT_CTRY_BM, // "Bermuda¦Ê¼}¹F" + RT_CTRY_BR, // "Brazil¤Ú¦è" + RT_CTRY_BG, // "Bulgaria«O¥[§Q¨È" + RT_CTRY_CA, // "Canada¥[®³¤j" + RT_CTRY_KY, // "Cayman Islands¶}°Ò¸s®q" + RT_CTRY_CL, // "Chile´¼§Q" + RT_CTRY_CN, // "China¤¤°ê" + RT_CTRY_CO, // "Columbia­ô­Û¤ñ¨È" + RT_CTRY_CR, // "Costa Rica­ô´µ¹F¾¤¥[" + RT_CTRY_CY, // "Cyprus¶ë®ú¸ô´µ" + RT_CTRY_CZ, // "Czech ±¶§J" + RT_CTRY_DK, // "Denmark¤¦³Á" + RT_CTRY_DO, // "Dominican Republic¦h©ú¥§¥[¦@©M°ê" + RT_CTRY_CE, // "Egypt®J¤Î" EG 2G_WORLD + RT_CTRY_SV, // "El SalvadorÂĺ¸¥Ë¦h" + RT_CTRY_EE, // "Estonia·R¨F¥§¨È" + RT_CTRY_FI, // "FinlandªâÄõ" + RT_CTRY_FR, // "Franceªk°ê" + RT_CTRY_DE, // "Germany¼w°ê" + RT_CTRY_GR, // "Greece §Æþ" + RT_CTRY_GU, // "GuamÃö®q" + RT_CTRY_GT, // "Guatemala¥Ê¦a°¨©Ô" + RT_CTRY_HT, // "Haiti®ü¦a" + RT_CTRY_HN, // "Honduras§»³£©Ô´µ" + RT_CTRY_HU, // "Hungary¦I¤ú§Q" + RT_CTRY_IS, // "Iceland¦B®q" + RT_CTRY_IN, // "India¦L«×" + RT_CTRY_IE, // "Ireland·Rº¸Äõ" + RT_CTRY_IL, // "Israel¥H¦â¦C" + RT_CTRY_IT, // "Italy¸q¤j§Q" + RT_CTRY_JP, // "Japan¤é¥»" + RT_CTRY_KR, // "KoreaÁú°ê" + RT_CTRY_LV, // "Latvia©Ô²æºû¨È" + RT_CTRY_LT, // "Lithuania¥ß³³©{" + RT_CTRY_LU, // "Luxembourg¿c´Ë³ù" + RT_CTRY_MY, // "Malaysia°¨¨Ó¦è¨È" + RT_CTRY_MT, // "Malta°¨º¸¥L" + RT_CTRY_MX, // "Mexico¾¥¦è­ô" + RT_CTRY_MA, // "Morocco¼¯¬¥­ô" + RT_CTRY_NL, // "Netherlands²üÄõ" + RT_CTRY_NZ, // "New Zealand¯Ã¦èÄõ" + RT_CTRY_NO, // "Norway®¿«Â" + RT_CTRY_PA, // "Panama¤Ú®³°¨ " + RT_CTRY_PH, // "Philippinesµá«ß»«" + RT_CTRY_PL, // "PolandªiÄõ" + RT_CTRY_PT, // "Portugal¸²µå¤ú" + RT_CTRY_RO, // "Romaniaù°¨¥§¨È" + RT_CTRY_RU, // "Russia«Xù´µ" + RT_CTRY_SA, // "Saudi Arabia¨F¦aªü©Ô§B" + RT_CTRY_SG, // "Singapore·s¥[©Y" + RT_CTRY_SK, // "Slovakia´µ¬¥¥ï§J" + RT_CTRY_SI, // "Slovenia´µ¬¥ºû¥§¨È" + RT_CTRY_ZA, // "South Africa«n«D" + RT_CTRY_ES, // "Spain¦è¯Z¤ú" + RT_CTRY_SE, // "Sweden·ç¨å" + RT_CTRY_CH, // "Switzerland·ç¤h" + RT_CTRY_TW, // "Taiwan»OÆW" + RT_CTRY_TH, // "Thailand®õ°ê" + RT_CTRY_TR, // "Turkey¤g¦Õ¨ä" + RT_CTRY_UA, // "Ukraine¯Q§JÄõ" + RT_CTRY_GB, // "United Kingdom­^°ê" + RT_CTRY_US, // "United States¬ü°ê" + RT_CTRY_VE, // "Venezuela©e¤º·ç©Ô" + RT_CTRY_VN, // "Vietnam¶V«n" + RT_CTRY_MAX, // + +}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME; + +// Scan type including active and passive scan. +typedef enum _RT_SCAN_TYPE_NEW +{ + SCAN_NULL, + SCAN_ACT, + SCAN_PAS, + SCAN_BOTH, +}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW; + + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + + u2Byte Freq_Start; + u2Byte Freq_end; +}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT; + + +// +// 2.4G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_2G +{ + RT_2G_NULL, + RT_2G_WORLD, + RT_2G_ETSI1, + RT_2G_FCC1, + RT_2G_MKK1, + RT_2G_ETSI2 + +}RT_REGULATION_2G, *PRT_REGULATION_2G; + + +//typedef struct _RT_CHANNEL_BEHAVIOR +//{ +// u1Byte Chnl; +// RT_SCAN_TYPE_NEW +// +//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; + +//typedef struct _RT_CHANNEL_PLAN_TYPE +//{ +// RT_CHANNEL_BEHAVIOR +// u1Byte Chnl_num; +//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; + +// +// 2.4G Channel Number +// Channel definition & number +// +#define CHNL_RT_2G_NULL \ + {0}, 0 +#define CHNL_RT_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_WORLD_TEST \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 + +#define CHNL_RT_2G_EFSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define CHNL_RT_2G_MKK1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define CHNL_RT_2G_ETSI2 \ + {10,11,12,13}, 4 + +// +// 2.4G Channel Active or passive scan. +// +#define CHNL_RT_2G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_2G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,0,0} +#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_FCC1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_MKK1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ + {1,1,1,1} + + +// +// 2.4G Band & Frequency Section +// Freqency start & end / band number +// +#define FREQ_RT_2G_NULL \ + {0}, 0 + // Passive scan CH 12, 13 +#define FREQ_RT_2G_WORLD \ + {2412, 2472}, 1 +#define FREQ_RT_2G_EFSI1 \ + {2412, 2472}, 1 +#define FREQ_RT_2G_FCC1 \ + {2412, 2462}, 1 +#define FREQ_RT_2G_MKK1 \ + {2412, 2484}, 1 +#define FREQ_RT_2G_ETSI2 \ + {2457, 2472}, 1 + + +// +// 5G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_5G +{ + RT_5G_NULL, + RT_5G_WORLD, + RT_5G_ETSI1, + RT_5G_ETSI2, + RT_5G_ETSI3, + RT_5G_FCC1, + RT_5G_FCC2, + RT_5G_FCC3, + RT_5G_FCC4, + RT_5G_FCC5, + RT_5G_FCC6, + RT_5G_FCC7, + RT_5G_IC1, + RT_5G_KCC1, + RT_5G_MKK1, + RT_5G_MKK2, + RT_5G_MKK3, + RT_5G_NCC1, + +}RT_REGULATION_5G, *PRT_REGULATION_5G; + +// +// 5G Channel Number +// +#define CHNL_RT_5G_NULL \ + {0}, 0 +#define CHNL_RT_5G_WORLD \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4 \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1 \ + {56,60,64,149,153,157,161,165}, 8 + +// +// 5G Channel Active or passive scan. +// +#define CHNL_RT_5G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_5G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1_SCAN_TYPE \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4_SCAN_TYPE \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2_SCAN_TYPE \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3_SCAN_TYPE \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1_SCAN_TYPE \ + {56,60,64,149,153,157,161,165}, 8 + +// +// Global Regulation +// +typedef enum _RT_REGULATION_COMMON +{ + RT_WORLD, + RT_FCC, + RT_MKK, + RT_ETSI, + RT_IC, + RT_CE, + RT_NCC, + +}RT_REGULATION_CMN, *PRT_REGULATION_CMN; + + + +// +// Special requirement for different regulation domain. +// For internal test or customerize special request. +// +typedef enum _RT_CHNLPLAN_SREQ +{ + RT_SREQ_NA = 0x0, + RT_SREQ_2G_ADHOC_11N = 0x00000001, + RT_SREQ_2G_ADHOC_11B = 0x00000002, + RT_SREQ_2G_ALL_PASS = 0x00000004, + RT_SREQ_2G_ALL_ACT = 0x00000008, + RT_SREQ_5G_ADHOC_11N = 0x00000010, + RT_SREQ_5G_ADHOC_11AC = 0x00000020, + RT_SREQ_5G_ALL_PASS = 0x00000040, + RT_SREQ_5G_ALL_ACT = 0x00000080, + RT_SREQ_C1_PLAN = 0x00000100, + RT_SREQ_C2_PLAN = 0x00000200, + RT_SREQ_C3_PLAN = 0x00000400, + RT_SREQ_C4_PLAN = 0x00000800, + RT_SREQ_NFC_ON = 0x00001000, + RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ + +}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ; + + +// +// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table +// +// +typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE +{ + // + // Define countery domain and corresponding + // + RT_COUNTRY_NAME Country_Enum; + char Country_Name[3]; + + //char Domain_Name[12]; + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_CHANNEL_DOMAIN RtChDomain; + //u1Byte Country_Area; + +}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL; + + +#define RT_MAX_CHNL_NUM_2G 13 +#define RT_MAX_CHNL_NUM_5G 44 + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_PWR_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + u1Byte dB_Max; + u2Byte mW_Max; +}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT; + + +#define RT_MAX_BAND_NUM 5 + +typedef struct _RT_CHANNEL_PLAN_MAXPWR +{ +// STRING_T + RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM]; + u1Byte Band_Useful_Num; + + +}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR; + + +// +// Power By Rate Table. +// + + + +typedef struct _RT_CHANNEL_PLAN_NEW +{ + // + // Define countery domain and corresponding + // + //char Country_Name[36]; + //u1Byte Country_Enum; + + //char Domain_Name[12]; + + + PRT_CHNL_CTRY_TBL pCtryTransfer; + + RT_CHANNEL_DOMAIN RtChDomain; + + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_REGULATION_CMN Regulator; + + RT_CHNLPLAN_SREQ ChnlSreq; + + //RT_CHNL_PLAN_LIMIT RtChnl; + + u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD + u1Byte Len2G; + u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + u1Byte Chnl5G[MAX_CHANNEL_NUM]; + u1Byte Len5G; + u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM]; + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr; + + +}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW; + + +#endif // __RT_CHANNELPLAN_H__ + + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.c b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.c index ead854ff95b..e275cdf0620 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.c @@ -1,1441 +1,1441 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - RateAdaptive.c - -Abstract: - Implement Rate Adaptive functions for common operations. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-12 Page Create. - 2015-04-23 Wilson Fine tune (SD9 Family) - ---*/ -#include "mp_precomp.h" - -#include "../phydm_precomp.h" - - -#if (RATE_ADAPTIVE_SUPPORT == 1) -// Rate adaptive parameters - - -static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 - {6,5,4,3,0,4},//86 , idx=1 - {6,5,4,2,0,4},//81 , idx=2 - {8,7,6,4,0,6},//75 , idx=3 -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - {10, 9, 7, 6, 0, 8},/*71 , idx=4*/ - {10, 9, 7, 4, 0, 8},/*66 , idx=5*/ -#else - {10,9,8,6,0,8},//71 , idx=4 - {10,9,8,4,0,8},//66 , idx=5 -#endif - {10,9,8,2,0,8},//62 , idx=6 - {10,9,8,0,0,8},//59 , idx=7 - {18,17,16,8,0,16},//53 , idx=8 - {26,25,24,16,0,24},//50 , idx=9 - {34,33,32,24,0,32},//47 , idx=0x0a - //{34,33,32,16,0,32},//43 , idx=0x0b - //{34,33,32,8,0,32},//40 , idx=0x0c - //{34,33,28,8,0,32},//37 , idx=0x0d - //{34,33,20,8,0,32},//32 , idx=0x0e - //{34,32,24,8,0,32},//26 , idx=0x0f - //{49,48,32,16,0,48},//20 , idx=0x10 - //{49,48,24,0,0,48},//17 , idx=0x11 - //{49,47,16,16,0,48},//15 , idx=0x12 - //{49,44,16,16,0,48},//12 , idx=0x13 - //{49,40,16,0,0,48},//9 , idx=0x14 - {34,31,28,20,0,32},//43 , idx=0x0b - {34,31,27,18,0,32},//40 , idx=0x0c - {34,31,26,16,0,32},//37 , idx=0x0d - {34,30,22,16,0,32},//32 , idx=0x0e - {34,30,24,16,0,32},//26 , idx=0x0f - {49,46,40,16,0,48},//20 , idx=0x10 - {49,45,32,0,0,48},//17 , idx=0x11 - {49,45,22,18,0,48},//15 , idx=0x12 -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - {49,40,28,18,0,48},//12 , idx=0x13 - {49,34,20,16,0,48},//9 , idx=0x14 -#else - {49,40,24,16,0,48},//12 , idx=0x13 - {49,32,18,12,0,48},//9 , idx=0x14 -#endif - {49,22,18,14,0,48},//6 , idx=0x15 - {49,16,16,0,0,48}};//3 //3, idx=0x16 - -static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up - -static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; - -#if 0 -static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH -#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - 4,4,4,4,0x0d,0x0d,0x0f,0x0f, -#else - 4,4,4,4,6,0x0a,0x0b,0x0d, -#endif - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH - 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, - 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; - -static u1Byte RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0, - 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, - 0x17, 0x1a, 0x1c, 0x1f, 0x23, 0x28, 0x2a, 0x2c, - 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c}; -#else - -// wilson modify -/*static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SSTH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x13, // SSTH - 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, - 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; - -static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, - 0,0,0,0,0,0x24,0x26,0x2a, - 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, - 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; - -#endif - -/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, - 0,0,0,0,0,0x24,0x26,0x2a, - 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, - 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ -/*static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, - 24,36,48,72,96,144,192,216, - 60,80,100,160,240,400,560,640, - 300,320,480,720,1000,1200,1600,2000}; -static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, - 12,18,24,36,48,72,96,108, - 30,40,50,80,120,200,280,320, - 150,160,240,360,500,600,800,1000};*/ -static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, - 24,36,48,72,96,144,192,216, - 60,80,100,160,240,400,600,800, - 300,320,480,720,1000,1200,1600,2000}; -static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, - 12,18,24,36,48,72,96,108, - 30,40,50,80,120,200,300,400, - 150,160,240,360,500,600,800,1000}; -static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2, - 2,2,3,3,4,4,5,7, - 4,4,7,10,10,12,12,18, - 5,7,7,8,11,18,36,60}; // 0329 // 1207 -#if 0 -static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, - 30,30,25,25,20,15,15,10, - 30,25,25,20,15,10,10,10, - 30,25,25,20,15,10,10,10}; -#endif - -static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1, - 1,2,3,4,5,6,7,8, - 1,2,3,4,5,6,7,8, - 5,6,7,8,9,10,11,12}; - - -static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode - 0x0f8ff010, // 1: 40M GN mode - 0x0f8ff005, // 2: BN mode/ 40M BGN mode - 0x0f8ff000, // 3: N mode - 0x00000ff5, // 4: BG mode - 0x00000ff0, // 5: G mode - 0x0000000d, // 6: B mode - 0, // 7: - 0, // 8: - 0, // 9: - 0, // 10: - 0, // 11: - 0, // 12: - 0, // 13: - 0, // 14: - 0, // 15: - - }; -static u1Byte PendingForRateUpFail[5] = {2, 10, 24, 40, 60}; -static u2Byte DynamicTxRPTTiming[6] = {0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*200ms-1200ms*/ - -// End Rate adaptive parameters - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) -static int -odm_RA_LearnBounding( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" odm_RA_LearnBounding\n")); - if (DM_RA_RATE_UP != pRaInfo->RateDirection) { - /* Check if previous RA adjustment trend as +++--- or ++++----*/ - if (((3 == pRaInfo->RateUpCounter && pRaInfo->BoundingLearningTime <= 10) - || (4 == pRaInfo->RateUpCounter && pRaInfo->BoundingLearningTime <= 16)) - && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { - if (1 != pRaInfo->BoundingType) { - pRaInfo->BoundingType = 1; - pRaInfo->BoundingCounter = 0; - } - pRaInfo->BoundingCounter++; - /* Check if previous RA adjustment trend as ++--*/ - } else if ((2 == pRaInfo->RateUpCounter) && (pRaInfo->BoundingLearningTime <= 7) - && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { - if (2 != pRaInfo->BoundingType) { - pRaInfo->BoundingType = 2; - pRaInfo->BoundingCounter = 0; - } - pRaInfo->BoundingCounter++; - /* Check if previous RA adjustment trend as +++++-----*/ - } else if ((5 == pRaInfo->RateUpCounter) && (pRaInfo->BoundingLearningTime <= 17) - && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { - if (3 != pRaInfo->BoundingType) { - pRaInfo->BoundingType = 3; - pRaInfo->BoundingCounter = 0; - } - pRaInfo->BoundingCounter++; - } else { - pRaInfo->BoundingType = 0; - } - - pRaInfo->RateDownCounter = 0; - pRaInfo->RateUpCounter = 0; - pRaInfo->BoundingLearningTime = 1; - } else if (pRaInfo->BoundingType) { - /* Check if RA adjustment trend as +++---++(+) or ++++----++(+)*/ - if ((1 == pRaInfo->BoundingType) && (1 == pRaInfo->BoundingCounter) - && (2 == pRaInfo->RateUpCounter)) { - pRaInfo->BoundingType = 0; - if (pRaInfo->BoundingLearningTime <= 5) - return 1; - /* Check if RA adjustment trend as ++--++--+(+)*/ - } else if ((2 == pRaInfo->BoundingType) && (2 == pRaInfo->BoundingCounter) - && (1 == pRaInfo->RateUpCounter)) { - pRaInfo->BoundingType = 0; - if (pRaInfo->BoundingLearningTime <= 2) - return 1; - /* Check if RA adjustment trend as +++++-----++(+)*/ - } else if ((3 == pRaInfo->BoundingType) && (1 == pRaInfo->BoundingCounter) - && (2 == pRaInfo->RateUpCounter)) { - pRaInfo->BoundingType = 0; - if (pRaInfo->BoundingLearningTime <= 4) - return 1; - } - } - - return 0; -} -#endif - -static void -odm_SetTxRPTTiming_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo, - IN u1Byte extend - ) -{ - u1Byte idx = 0; - - for(idx=0; idx<5; idx++) - if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) - break; - - if (extend==0) // back to default timing - idx=0; //200ms - else if (extend==1) {// increase the timing - idx+=1; - if (idx>5) - idx=5; - } - else if (extend==2) {// decrease the timing - if(idx!=0) - idx-=1; - } - pRaInfo->RptTime=DynamicTxRPTTiming[idx]; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime)); -} - -static int -odm_RateDown_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ - u1Byte RateID, LowestRate, HighestRate; - s1Byte i; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); - if(NULL == pRaInfo) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); - return -1; - } - RateID = pRaInfo->PreRate; - LowestRate = pRaInfo->LowestRate; - HighestRate = pRaInfo->HighestRate; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", - RateID, LowestRate, HighestRate, pRaInfo->RateSGI)); - if (RateID > HighestRate) - { - RateID=HighestRate; - } - else if(pRaInfo->RateSGI) - { - pRaInfo->RateSGI=0; - } - else if (RateID > LowestRate) - { - if (RateID > 0) { - for (i = RateID - 1; i >= LowestRate; i--) { - if (pRaInfo->RAUseRate & BIT(i)) { -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pRaInfo->RateDownCounter++; - pRaInfo->RateDirection = DM_RA_RATE_DOWN; - - /* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/ - if (0xFF == pRaInfo->RateDownStartTime) { - if ((0 == pRaInfo->RateUpCounter) || (pRaInfo->RateUpCounter+2 < pRaInfo->BoundingLearningTime)) - pRaInfo->RateDownStartTime = 0; - else - pRaInfo->RateDownStartTime = pRaInfo->BoundingLearningTime; - } -#endif - RateID=i; - goto RateDownFinish; - - } - } - } - } - else if (RateID <= LowestRate) - { - RateID = LowestRate; - } -RateDownFinish: -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - /*if (pRaInfo->RTY[2] >= 100) { - pRaInfo->RAWaitingCounter = 2; - pRaInfo->RAPendingCounter += 1; - } else */if ((0 != pRaInfo->RateDownStartTime) && (0xFF != pRaInfo->RateDownStartTime)) { - /* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/ - if (pRaInfo->RateDownCounter < pRaInfo->RateUpCounter) { - - } else if (pRaInfo->RateDownCounter == pRaInfo->RateUpCounter) { - pRaInfo->RAWaitingCounter = 2; - pRaInfo->RAPendingCounter += 1; - } else if (pRaInfo->RateDownCounter <= pRaInfo->RateUpCounter+2) { - RateID = pRaInfo->PreRate; - } else { - pRaInfo->RAWaitingCounter = 0; - pRaInfo->RAPendingCounter = 0; - pRaInfo->RateDownStartTime = 0; - } - } else -#endif - if (pRaInfo->RAWaitingCounter==1){ - pRaInfo->RAWaitingCounter+=1; - pRaInfo->RAPendingCounter+=1; - } - else if(pRaInfo->RAWaitingCounter==0){ - } - else{ - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - } - - if(pRaInfo->RAPendingCounter>=4) - pRaInfo->RAPendingCounter=4; - pRaInfo->RADropAfterDown = 1; - pRaInfo->DecisionRate = RateID; - odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 2); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, Decrease RPT Timing\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d RADrop %d", pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter, pRaInfo->RADropAfterDown)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDown_8188E()\n")); - return 0; -} - -static int -odm_RateUp_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ - u1Byte RateID, HighestRate; - u1Byte i; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n")); - if(NULL == pRaInfo) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); - return -1; - } - RateID = pRaInfo->PreRate; - HighestRate = pRaInfo->HighestRate; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" RateID=%d HighestRate=%d\n", - RateID, HighestRate)); - if (pRaInfo->RAWaitingCounter==1){ - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - } - else if (pRaInfo->RAWaitingCounter>1){ - pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pRaInfo->RateDownStartTime = 0; -#endif - goto RateUpfinish; - } - odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): default RPT Timing\n")); - - if (RateID < HighestRate) - { - for (i=RateID+1; i<=HighestRate; i++) - { - if (pRaInfo->RAUseRate & BIT(i)) - { -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if (odm_RA_LearnBounding(pDM_Odm, pRaInfo)) { - pRaInfo->RAWaitingCounter = 2; - pRaInfo->RAPendingCounter = 1; - goto RateUpfinish; - } - pRaInfo->RateUpCounter++; - pRaInfo->RateDirection = DM_RA_RATE_UP; -#endif - RateID=i; - goto RateUpfinish; - } - } - } - else if(RateID == HighestRate) - { - if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) - pRaInfo->RateSGI = 1; - else if((pRaInfo->SGIEnable) !=1 ) - pRaInfo->RateSGI = 0; - } - else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) - { - RateID = HighestRate; - - } -RateUpfinish: - //if(pRaInfo->RAWaitingCounter==10) - if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter])) { - pRaInfo->RAWaitingCounter=0; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - /* Mark persistence expiration state*/ - pRaInfo->RateDownStartTime = 0xFF; - /* Clear state to avoid wrong bounding check*/ - pRaInfo->RateDownCounter = 0; - pRaInfo->RateUpCounter = 0; - pRaInfo->RateDirection = 0; -#endif - } - else - pRaInfo->RAWaitingCounter++; - - pRaInfo->DecisionRate=RateID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateUp_8188E() \n")); - return 0; -} - -static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){ - u1Byte RateID; - RateID=pRaInfo->DecisionRate; - pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; - pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; -} - -static void -odm_RateDecision_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ - u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; - //u4Byte pool_retry; - static u1Byte DynamicTxRPTTimingCounter=0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); - - if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits - { -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if (((pRaInfo->RssiStaRA <= 17) && (pRaInfo->RssiStaRA > pRaInfo->PreRssiStaRA)) - || ((pRaInfo->PreRssiStaRA <= 17) && (pRaInfo->PreRssiStaRA > pRaInfo->RssiStaRA))) { - /* don't reset state in low signal due to the power different between CCK and MCS is large.*/ - } else -#endif - if (pRaInfo->RADropAfterDown) { - pRaInfo->RADropAfterDown--; - odm_ResetRaCounter_8188E(pRaInfo); - return; - } - if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ - pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA; - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pRaInfo->BoundingType = 0; -#endif - } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (0xff != pDM_Odm->priv->pshare->rf_ft_var.txforce) { - pRaInfo->PreRate = pDM_Odm->priv->pshare->rf_ft_var.txforce; - odm_ResetRaCounter_8188E(pRaInfo); - } -#endif - - // Start RA decision - if (pRaInfo->PreRate > pRaInfo->HighestRate) - RateID = pRaInfo->HighestRate; - else - RateID = pRaInfo->PreRate; - if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) - RtyPtID=0; - else - RtyPtID=1; - PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" NscDown init is %d\n", pRaInfo->NscDown)); - //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; - pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; - pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; - pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; - pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; - pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" NscDown is %d, total*penalty[5] is %d\n", - pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); - if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) - pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; - else - pRaInfo->NscDown=0; - - // rate up - PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" NscUp init is %d\n", pRaInfo->NscUp)); - pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; - pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; - pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; - pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; - pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - ("NscUp is %d, total*up[5] is %d\n", - pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); - if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) - pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; - else - pRaInfo->NscUp = 0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE|ODM_COMP_INIT, ODM_DBG_LOUD, - (" RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d SGI=%d\n", - pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if (0xFF != pRaInfo->BoundingLearningTime) - pRaInfo->BoundingLearningTime++; -#endif - if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) - odm_RateDown_8188E(pDM_Odm,pRaInfo); - //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) - odm_RateUp_8188E(pDM_Odm,pRaInfo); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - else if ((pRaInfo->RTY[2] >= 100) && (ODM_BW20M == *pDM_Odm->pBandWidth)) - odm_RateDown_8188E(pDM_Odm,pRaInfo); -#endif - - if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) - DynamicTxRPTTimingCounter+=1; - else - DynamicTxRPTTimingCounter=0; - - if (DynamicTxRPTTimingCounter>=4) { - odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<=====Rate don't change 4 times, Extend RPT Timing\n")); - DynamicTxRPTTimingCounter=0; - } - - pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 - - odm_ResetRaCounter_8188E( pRaInfo); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDecision_8188E() \n")); -} - -static int -odm_ARFBRefresh_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ // Wilson 2011/10/26 - u4Byte MaskFromReg; - u1Byte i; - - switch(pRaInfo->RateID){ - case RATR_INX_WIRELESS_NGB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8fe00f; - break; - case RATR_INX_WIRELESS_NG: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; - break; - case RATR_INX_WIRELESS_NB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8fe00f; - break; - case RATR_INX_WIRELESS_N: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; - break; - case RATR_INX_WIRELESS_GB: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000fef; - break; - case RATR_INX_WIRELESS_G: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; - break; - case RATR_INX_WIRELESS_B: - pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; - break; - case 12: - MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR0); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 13: - MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR1); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 14: - MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR2); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - case 15: - MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR3); - pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; - break; - - default: - pRaInfo->RAUseRate=(pRaInfo->RateMask); - break; - } - // Highest rate - if (pRaInfo->RAUseRate) - for (i = RATESIZE ; i >= 0 ; i--) - { - if((pRaInfo->RAUseRate)&BIT(i)){ - pRaInfo->HighestRate=i; - break; - } - } - else - pRaInfo->HighestRate=0; - // Lowest rate - if (pRaInfo->RAUseRate) - for (i=0;iRAUseRate)&BIT(i)) { - pRaInfo->LowestRate=i; - break; - } - } - else - pRaInfo->LowestRate=0; - -#if POWER_TRAINING_ACTIVE == 1 - if (pRaInfo->HighestRate >0x13) - pRaInfo->PTModeSS=3; - else if(pRaInfo->HighestRate >0x0b) - pRaInfo->PTModeSS=2; - else if(pRaInfo->HighestRate >0x0b) - pRaInfo->PTModeSS=1; - else - pRaInfo->PTModeSS=0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - ("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS)); - -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - ("ODM_ARFBRefresh_8188E(): RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", - pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate)); - return 0; -} - -#if POWER_TRAINING_ACTIVE == 1 -static void -odm_PTTryState_8188E( - IN PDM_ODM_T pDM_Odm, - IN PODM_RA_INFO_T pRaInfo - ) -{ - pRaInfo->PTTryState=0; - switch (pRaInfo->PTModeSS) - { - case 3: - if (pRaInfo->DecisionRate>=0x19) - pRaInfo->PTTryState=1; - break; - case 2: - if (pRaInfo->DecisionRate>=0x11) - pRaInfo->PTTryState=1; - break; - case 1: - if (pRaInfo->DecisionRate>=0x0a) - pRaInfo->PTTryState=1; - break; - case 0: - if (pRaInfo->DecisionRate>=0x03) - pRaInfo->PTTryState=1; - break; - default: - pRaInfo->PTTryState=0; - } - - if (pRaInfo->RssiStaRA<48) - { - pRaInfo->PTStage=0; - } - else if (pRaInfo->PTTryState==1) - { - if ((pRaInfo->PTStopCount>=10)||(pRaInfo->PTPreRssi>pRaInfo->RssiStaRA+5) - ||(pRaInfo->PTPreRssiRssiStaRA-5)||(pRaInfo->DecisionRate!=pRaInfo->PTPreRate)) - { - if (pRaInfo->PTStage==0) - pRaInfo->PTStage=1; - else if(pRaInfo->PTStage==1) - pRaInfo->PTStage=3; - else - pRaInfo->PTStage=5; - - pRaInfo->PTPreRssi=pRaInfo->RssiStaRA; - pRaInfo->PTStopCount=0; - - } - else{ - pRaInfo->RAstage=0; - pRaInfo->PTStopCount++; - } - } - else{ - pRaInfo->PTStage=0; - pRaInfo->RAstage=0; - } - pRaInfo->PTPreRate=pRaInfo->DecisionRate; - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - // Disable power training when noisy environment - if(pDM_Odm->bDisablePowerTraining) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_PTTryState_8188E(): Disable power training when noisy environment\n")); - pRaInfo->PTStage = 0; - pRaInfo->RAstage = 0; - pRaInfo->PTStopCount = 0; - } -#endif -} - -static void -odm_PTDecision_8188E( - IN PODM_RA_INFO_T pRaInfo - ) -{ - u1Byte stage_BUF; - u1Byte j; - u1Byte temp_stage; - u4Byte numsc; - u4Byte num_total; - u1Byte stage_id; - - stage_BUF=pRaInfo->PTStage; - numsc = 0; - num_total= pRaInfo->TOTAL* PT_PENALTY[5]; - for(j=0;j<=4;j++) - { - numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; - if(numsc>num_total) - break; - } - - j=j>>1; - temp_stage= (pRaInfo->PTStage +1)>>1; - if (temp_stage>j) - stage_id=temp_stage-j; - else - stage_id=0; - - pRaInfo->PTSmoothFactor=(pRaInfo->PTSmoothFactor>>1) + (pRaInfo->PTSmoothFactor>>2) + stage_id*16+2; - if (pRaInfo->PTSmoothFactor>192) - pRaInfo->PTSmoothFactor=192; - stage_id =pRaInfo->PTSmoothFactor>>6; - temp_stage=stage_id*2; - if (temp_stage!=0) - temp_stage-=1; - if (pRaInfo->DROP>3) - temp_stage=0; - pRaInfo->PTStage=temp_stage; - -} -#endif - -static VOID -odm_RATxRPTTimerSetting( - IN PDM_ODM_T pDM_Odm, - IN u2Byte minRptTime -) -{ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n")); - - - if(pDM_Odm->CurrminRptTime != minRptTime){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - (" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime)); - #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) - ODM_RA_Set_TxRPT_Time(pDM_Odm,minRptTime); - #else - rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime); - #endif - pDM_Odm->CurrminRptTime = minRptTime; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" <=====odm_RATxRPTTimerSetting()\n")); -} - - -VOID -ODM_RASupport_Init( - IN PDM_ODM_T pDM_Odm - ) -{ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); - - // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! - if (pDM_Odm->SupportICType == ODM_RTL8188E) - pDM_Odm->RaSupport88E = TRUE; - - } - - - -int -ODM_RAInfo_Init( - IN PDM_ODM_T pDM_Odm, - IN u4Byte MacID - ) -{ - PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; - #if 0 - u1Byte WirelessMode=0xFF; //invalid value - u1Byte max_rate_idx = 0x13; //MCS7 - if(pDM_Odm->pWirelessMode!=NULL){ - WirelessMode=*(pDM_Odm->pWirelessMode); - } - - if(WirelessMode != 0xFF ){ - if(WirelessMode & ODM_WM_N24G) - max_rate_idx = 0x13; - else if(WirelessMode & ODM_WM_G) - max_rate_idx = 0x0b; - else if(WirelessMode & ODM_WM_B) - max_rate_idx = 0x03; - } - - //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", - WirelessMode,max_rate_idx)); - - pRaInfo->DecisionRate = max_rate_idx; - pRaInfo->PreRate = max_rate_idx; - pRaInfo->HighestRate=max_rate_idx; - #else - pRaInfo->DecisionRate = 0x13; - pRaInfo->PreRate = 0x13; - pRaInfo->HighestRate=0x13; - #endif - pRaInfo->LowestRate=0; - pRaInfo->RateID=0; - pRaInfo->RateMask=0xffffffff; - pRaInfo->RssiStaRA=0; - pRaInfo->PreRssiStaRA=0; - pRaInfo->SGIEnable=0; - pRaInfo->RAUseRate=0xffffffff; - pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; - pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; - pRaInfo->RateSGI=0; - pRaInfo->Active=1; //Active is not used at present. by page, 110819 - pRaInfo->RptTime = 0x927c; - pRaInfo->DROP=0; - pRaInfo->RTY[0]=0; - pRaInfo->RTY[1]=0; - pRaInfo->RTY[2]=0; - pRaInfo->RTY[3]=0; - pRaInfo->RTY[4]=0; - pRaInfo->TOTAL=0; - pRaInfo->RAWaitingCounter=0; - pRaInfo->RAPendingCounter=0; - pRaInfo->RADropAfterDown = 0; -#if POWER_TRAINING_ACTIVE == 1 - pRaInfo->PTActive=1; // Active when this STA is use - pRaInfo->PTTryState=0; - pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS - pRaInfo->PTSmoothFactor=192; - pRaInfo->PTStopCount=0; - pRaInfo->PTPreRate=0; - pRaInfo->PTPreRssi=0; - pRaInfo->PTModeSS=0; - pRaInfo->RAstage=0; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pRaInfo->RateDownCounter = 0; - pRaInfo->RateUpCounter = 0; - pRaInfo->RateDirection = 0; - pRaInfo->BoundingType = 0; - pRaInfo->BoundingCounter = 0; - pRaInfo->BoundingLearningTime = 0; - pRaInfo->RateDownStartTime = 0; -#endif - return 0; -} - -int -ODM_RAInfo_Init_all( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte MacID = 0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n")); - pDM_Odm->CurrminRptTime = 0; - - for(MacID=0; MacIDCutVersion == ODM_CUT_I) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - u1Byte i; - u1Byte RETRY_PENALTY_IDX_S[2][RATESIZE] = {{4,4,4,5, - 4,4,5,7,7,7,8,0x0a, // SS>TH - 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0b,0x0c, - 0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x13, // SSTH - 0x0b,0x0b,0x11,0x11,0x12,0x12,0x12,0x12, - 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; - - for( i=0; iAdapter; - - //DbgPrint("Adapter->MgntInfo.RegRALvl = %d\n", Adapter->MgntInfo.RegRALvl); - - // - // 2012/09/14 MH Add for different Ra pattern init. For TPLINK case, we - // need to to adjust different RA pattern for middle range RA. 20-30dB degarde - // 88E rate adptve will raise too slow. - // - if (Adapter->MgntInfo.RegRALvl == 0) - { - RETRY_PENALTY_UP_IDX[11] = 0x14; - - RETRY_PENALTY_UP_IDX[17] = 0x13; - RETRY_PENALTY_UP_IDX[18] = 0x14; - RETRY_PENALTY_UP_IDX[19] = 0x15; - - RETRY_PENALTY_UP_IDX[23] = 0x13; - RETRY_PENALTY_UP_IDX[24] = 0x13; - RETRY_PENALTY_UP_IDX[25] = 0x13; - RETRY_PENALTY_UP_IDX[26] = 0x14; - RETRY_PENALTY_UP_IDX[27] = 0x15; - } - else if (Adapter->MgntInfo.RegRALvl == 1) - { - RETRY_PENALTY_UP_IDX[17] = 0x13; - RETRY_PENALTY_UP_IDX[18] = 0x13; - RETRY_PENALTY_UP_IDX[19] = 0x14; - - RETRY_PENALTY_UP_IDX[23] = 0x12; - RETRY_PENALTY_UP_IDX[24] = 0x13; - RETRY_PENALTY_UP_IDX[25] = 0x13; - RETRY_PENALTY_UP_IDX[26] = 0x13; - RETRY_PENALTY_UP_IDX[27] = 0x14; - } - else if (Adapter->MgntInfo.RegRALvl == 2) - { - // Compile flag default is lvl2, we need not to update. - } - else if (Adapter->MgntInfo.RegRALvl >= 0x80) - { - u1Byte index = 0, offset = Adapter->MgntInfo.RegRALvl - 0x80; - - // Reset to default rate adaptive value. - RETRY_PENALTY_UP_IDX[11] = 0x14; - - RETRY_PENALTY_UP_IDX[17] = 0x13; - RETRY_PENALTY_UP_IDX[18] = 0x14; - RETRY_PENALTY_UP_IDX[19] = 0x15; - - RETRY_PENALTY_UP_IDX[23] = 0x13; - RETRY_PENALTY_UP_IDX[24] = 0x13; - RETRY_PENALTY_UP_IDX[25] = 0x13; - RETRY_PENALTY_UP_IDX[26] = 0x14; - RETRY_PENALTY_UP_IDX[27] = 0x15; - - if (Adapter->MgntInfo.RegRALvl >= 0x90) - { - offset = Adapter->MgntInfo.RegRALvl - 0x90; - // Lazy mode. - for (index = 0; index < 28; index++) - { - RETRY_PENALTY_UP_IDX[index] += (offset); - } - } - else - { - // Aggrasive side. - for (index = 0; index < 28; index++) - { - RETRY_PENALTY_UP_IDX[index] -= (offset); - } - } - - } -} -#endif - return 0; -} - - -u1Byte -ODM_RA_GetShortGI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID -) -{ - if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) - return 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - ("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI)); - return pDM_Odm->RAInfo[MacID].RateSGI; -} - -u1Byte -ODM_RA_GetDecisionRate_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ) -{ - u1Byte DecisionRate = 0; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte CmdBuf[3]; - - if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) - return 0; - DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate); - - if (DecisionRate != pRA_Table->link_tx_rate[MacID]) { - - CmdBuf[1] = MacID; - CmdBuf[0] = DecisionRate; - phydm_c2h_ra_report_handler(pDM_Odm, &(CmdBuf[0]), 3); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" MacID=%d DecisionRate=0x%x\n", MacID, DecisionRate)); - return DecisionRate; -} - -u1Byte -ODM_RA_GetHwPwrStatus_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ) -{ - u1Byte PTStage = 5; - if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) - return 0; - PTStage = (pDM_Odm->RAInfo[MacID].PTStage); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - ("MacID=%d PTStage=0x%x\n", MacID, PTStage)); - return PTStage; -} - -VOID -ODM_RA_UpdateRateInfo_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte RateID, - IN u4Byte RateMask, - IN u1Byte SGIEnable - ) -{ - PODM_RA_INFO_T pRaInfo = NULL; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - ("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n", - MacID, RateID, RateMask, SGIEnable)); - if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) - return; - - pRaInfo = &(pDM_Odm->RAInfo[MacID]); - pRaInfo->RateID = RateID; - pRaInfo->RateMask = RateMask; - pRaInfo->SGIEnable = SGIEnable; - odm_ARFBRefresh_8188E(pDM_Odm, pRaInfo); -} - -VOID -ODM_RA_SetRSSI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte Rssi - ) -{ - PODM_RA_INFO_T pRaInfo = NULL; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, - (" MacID=%d Rssi=%d\n", MacID, Rssi)); - if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) - return; - - pRaInfo = &(pDM_Odm->RAInfo[MacID]); - pRaInfo->RssiStaRA = Rssi; -} - -VOID -ODM_RA_Set_TxRPT_Time( - IN PDM_ODM_T pDM_Odm, - IN u2Byte minRptTime - ) -{ -#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (minRptTime != 0xffff) - { -#if defined(CONFIG_PCI_HCI) - ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); -#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) - notify_tx_report_interval_change(pDM_Odm->priv, minRptTime); -#endif - } -#else - ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); -#endif - -} - - -VOID -ODM_RA_TxRPT2Handle_8188E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte TxRPT_Buf, - IN u2Byte TxRPT_Len, - IN u4Byte MacIDValidEntry0, - IN u4Byte MacIDValidEntry1 - ) -{ - PODM_RA_INFO_T pRAInfo = NULL; - u1Byte MacId = 0; - pu1Byte pBuffer = NULL; - u4Byte valid = 0, ItemNum = 0; - u2Byte minRptTime = 0x927c; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n", - MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len)); - - ItemNum = TxRPT_Len >> 3; - pBuffer = TxRPT_Buf; - - do - { - valid = 0; - if(MacId < 32) - valid = (1<RAInfo[MacId]); - if(valid) - { - - - pRAInfo->RTY[0] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer); - pRAInfo->RTY[1] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_1(pBuffer); - pRAInfo->RTY[2] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_2(pBuffer); - pRAInfo->RTY[3] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_3(pBuffer); - pRAInfo->RTY[4] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_4(pBuffer); - pRAInfo->DROP = (u2Byte)GET_TX_REPORT_TYPE1_DROP_0(pBuffer); - - pRAInfo->TOTAL = pRAInfo->RTY[0] + \ - pRAInfo->RTY[1] + \ - pRAInfo->RTY[2] + \ - pRAInfo->RTY[3] + \ - pRAInfo->RTY[4] + \ - pRAInfo->DROP; -#if defined(TXRETRY_CNT) - extern struct stat_info *get_macidinfo(struct rtl8192cd_priv *priv, unsigned int aid); - - { - struct stat_info *pstat = get_macidinfo(pDM_Odm->priv, MacId); - if (pstat) { - pstat->cur_tx_ok += pRAInfo->RTY[0]; - pstat->cur_tx_retry_pkts += pRAInfo->RTY[1] + pRAInfo->RTY[2] + pRAInfo->RTY[3] + pRAInfo->RTY[4]; - pstat->cur_tx_retry_cnt += pRAInfo->RTY[1] + pRAInfo->RTY[2] * 2 + pRAInfo->RTY[3] * 3 + pRAInfo->RTY[4] * 4; - pstat->total_tx_retry_cnt += pstat->cur_tx_retry_cnt; - pstat->total_tx_retry_pkts += pstat->cur_tx_retry_pkts; - pstat->cur_tx_fail += pRAInfo->DROP; - } - } -#endif - if(pRAInfo->TOTAL != 0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, - ("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", - MacId, - pRAInfo->TOTAL, - pRAInfo->RTY[0], - pRAInfo->RTY[1], - pRAInfo->RTY[2], - pRAInfo->RTY[3], - pRAInfo->RTY[4], - pRAInfo->DROP, - MacIDValidEntry0 , - MacIDValidEntry1)); -#if POWER_TRAINING_ACTIVE == 1 - if (pRAInfo->PTActive){ - if(pRAInfo->RAstage<5){ - odm_RateDecision_8188E(pDM_Odm,pRAInfo); - } - else if(pRAInfo->RAstage==5){ // Power training try state - odm_PTTryState_8188E(pDM_Odm, pRAInfo); - } - else {// RAstage==6 - odm_PTDecision_8188E(pRAInfo); - } - - // Stage_RA counter - if (pRAInfo->RAstage<=5) - pRAInfo->RAstage++; - else - pRAInfo->RAstage=0; - } - else{ - odm_RateDecision_8188E(pDM_Odm,pRAInfo); - } -#else - odm_RateDecision_8188E(pDM_Odm, pRAInfo); -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - extern void RTL8188E_SetStationTxRateInfo(PDM_ODM_T, PODM_RA_INFO_T, int); - RTL8188E_SetStationTxRateInfo(pDM_Odm, pRAInfo, MacId); -#ifdef DETECT_STA_EXISTANCE - void RTL8188E_DetectSTAExistance(PDM_ODM_T pDM_Odm, PODM_RA_INFO_T pRAInfo, int MacID); - RTL8188E_DetectSTAExistance(pDM_Odm, pRAInfo, MacId); -#endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x RateID=%d SGI=%d\n", - MacId, - pRAInfo->RTY[0], - pRAInfo->RTY[1], - pRAInfo->RTY[2], - pRAInfo->RTY[3], - pRAInfo->RTY[4], - pRAInfo->DROP, - MacIDValidEntry0, - pRAInfo->DecisionRate, - pRAInfo->RateSGI)); - } - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n")); - } - - if (minRptTime > pRAInfo->RptTime) - minRptTime = pRAInfo->RptTime; - - pBuffer += TX_RPT2_ITEM_SIZE; - MacId++; - }while(MacId < ItemNum); - - odm_RATxRPTTimerSetting(pDM_Odm,minRptTime); - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<===== ODM_RA_TxRPT2Handle_8188E()\n")); -} - -#else - -static VOID -odm_RATxRPTTimerSetting( - IN PDM_ODM_T pDM_Odm, - IN u2Byte minRptTime -) -{ - return; -} - - -VOID -ODM_RASupport_Init( - IN PDM_ODM_T pDM_Odm - ) -{ - return; -} - -int -ODM_RAInfo_Init( - IN PDM_ODM_T pDM_Odm, - IN u4Byte MacID - ) -{ - return 0; -} - -int -ODM_RAInfo_Init_all( - IN PDM_ODM_T pDM_Odm - ) -{ - return 0; -} - -u1Byte -ODM_RA_GetShortGI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ) -{ - return 0; -} - -u1Byte -ODM_RA_GetDecisionRate_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ) -{ - return 0; -} -u1Byte -ODM_RA_GetHwPwrStatus_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ) -{ - return 0; -} - -VOID -ODM_RA_UpdateRateInfo_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte RateID, - IN u4Byte RateMask, - IN u1Byte SGIEnable - ) -{ - return; -} - -VOID -ODM_RA_SetRSSI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte Rssi - ) -{ - return; -} - -VOID -ODM_RA_Set_TxRPT_Time( - IN PDM_ODM_T pDM_Odm, - IN u2Byte minRptTime - ) -{ - return; -} - -VOID -ODM_RA_TxRPT2Handle_8188E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte TxRPT_Buf, - IN u2Byte TxRPT_Len, - IN u4Byte MacIDValidEntry0, - IN u4Byte MacIDValidEntry1 - ) -{ - return; -} - - -#endif - +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.c + +Abstract: + Implement Rate Adaptive functions for common operations. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. + 2015-04-23 Wilson Fine tune (SD9 Family) + +--*/ +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + + +#if (RATE_ADAPTIVE_SUPPORT == 1) +// Rate adaptive parameters + + +static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 + {6,5,4,3,0,4},//86 , idx=1 + {6,5,4,2,0,4},//81 , idx=2 + {8,7,6,4,0,6},//75 , idx=3 +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + {10, 9, 7, 6, 0, 8},/*71 , idx=4*/ + {10, 9, 7, 4, 0, 8},/*66 , idx=5*/ +#else + {10,9,8,6,0,8},//71 , idx=4 + {10,9,8,4,0,8},//66 , idx=5 +#endif + {10,9,8,2,0,8},//62 , idx=6 + {10,9,8,0,0,8},//59 , idx=7 + {18,17,16,8,0,16},//53 , idx=8 + {26,25,24,16,0,24},//50 , idx=9 + {34,33,32,24,0,32},//47 , idx=0x0a + //{34,33,32,16,0,32},//43 , idx=0x0b + //{34,33,32,8,0,32},//40 , idx=0x0c + //{34,33,28,8,0,32},//37 , idx=0x0d + //{34,33,20,8,0,32},//32 , idx=0x0e + //{34,32,24,8,0,32},//26 , idx=0x0f + //{49,48,32,16,0,48},//20 , idx=0x10 + //{49,48,24,0,0,48},//17 , idx=0x11 + //{49,47,16,16,0,48},//15 , idx=0x12 + //{49,44,16,16,0,48},//12 , idx=0x13 + //{49,40,16,0,0,48},//9 , idx=0x14 + {34,31,28,20,0,32},//43 , idx=0x0b + {34,31,27,18,0,32},//40 , idx=0x0c + {34,31,26,16,0,32},//37 , idx=0x0d + {34,30,22,16,0,32},//32 , idx=0x0e + {34,30,24,16,0,32},//26 , idx=0x0f + {49,46,40,16,0,48},//20 , idx=0x10 + {49,45,32,0,0,48},//17 , idx=0x11 + {49,45,22,18,0,48},//15 , idx=0x12 +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + {49,40,28,18,0,48},//12 , idx=0x13 + {49,34,20,16,0,48},//9 , idx=0x14 +#else + {49,40,24,16,0,48},//12 , idx=0x13 + {49,32,18,12,0,48},//9 , idx=0x14 +#endif + {49,22,18,14,0,48},//6 , idx=0x15 + {49,16,16,0,0,48}};//3 //3, idx=0x16 + +static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up + +static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; + +#if 0 +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SSTH +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + 4,4,4,4,0x0d,0x0d,0x0f,0x0f, +#else + 4,4,4,4,6,0x0a,0x0b,0x0d, +#endif + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SSTH + 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0, + 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, + 0x17, 0x1a, 0x1c, 0x1f, 0x23, 0x28, 0x2a, 0x2c, + 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c}; +#else + +// wilson modify +/*static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SSTH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x13, // SSTH + 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; + +#endif + +/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ +/*static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,560,640, + 300,320,480,720,1000,1200,1600,2000}; +static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,280,320, + 150,160,240,360,500,600,800,1000};*/ +static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,600,800, + 300,320,480,720,1000,1200,1600,2000}; +static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,300,400, + 150,160,240,360,500,600,800,1000}; +static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2, + 2,2,3,3,4,4,5,7, + 4,4,7,10,10,12,12,18, + 5,7,7,8,11,18,36,60}; // 0329 // 1207 +#if 0 +static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, + 30,30,25,25,20,15,15,10, + 30,25,25,20,15,10,10,10, + 30,25,25,20,15,10,10,10}; +#endif + +static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1, + 1,2,3,4,5,6,7,8, + 1,2,3,4,5,6,7,8, + 5,6,7,8,9,10,11,12}; + + +static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode + 0x0f8ff010, // 1: 40M GN mode + 0x0f8ff005, // 2: BN mode/ 40M BGN mode + 0x0f8ff000, // 3: N mode + 0x00000ff5, // 4: BG mode + 0x00000ff0, // 5: G mode + 0x0000000d, // 6: B mode + 0, // 7: + 0, // 8: + 0, // 9: + 0, // 10: + 0, // 11: + 0, // 12: + 0, // 13: + 0, // 14: + 0, // 15: + + }; +static u1Byte PendingForRateUpFail[5] = {2, 10, 24, 40, 60}; +static u2Byte DynamicTxRPTTiming[6] = {0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*200ms-1200ms*/ + +// End Rate adaptive parameters + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +static int +odm_RA_LearnBounding( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" odm_RA_LearnBounding\n")); + if (DM_RA_RATE_UP != pRaInfo->RateDirection) { + /* Check if previous RA adjustment trend as +++--- or ++++----*/ + if (((3 == pRaInfo->RateUpCounter && pRaInfo->BoundingLearningTime <= 10) + || (4 == pRaInfo->RateUpCounter && pRaInfo->BoundingLearningTime <= 16)) + && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { + if (1 != pRaInfo->BoundingType) { + pRaInfo->BoundingType = 1; + pRaInfo->BoundingCounter = 0; + } + pRaInfo->BoundingCounter++; + /* Check if previous RA adjustment trend as ++--*/ + } else if ((2 == pRaInfo->RateUpCounter) && (pRaInfo->BoundingLearningTime <= 7) + && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { + if (2 != pRaInfo->BoundingType) { + pRaInfo->BoundingType = 2; + pRaInfo->BoundingCounter = 0; + } + pRaInfo->BoundingCounter++; + /* Check if previous RA adjustment trend as +++++-----*/ + } else if ((5 == pRaInfo->RateUpCounter) && (pRaInfo->BoundingLearningTime <= 17) + && (pRaInfo->RateUpCounter == pRaInfo->RateDownCounter)) { + if (3 != pRaInfo->BoundingType) { + pRaInfo->BoundingType = 3; + pRaInfo->BoundingCounter = 0; + } + pRaInfo->BoundingCounter++; + } else { + pRaInfo->BoundingType = 0; + } + + pRaInfo->RateDownCounter = 0; + pRaInfo->RateUpCounter = 0; + pRaInfo->BoundingLearningTime = 1; + } else if (pRaInfo->BoundingType) { + /* Check if RA adjustment trend as +++---++(+) or ++++----++(+)*/ + if ((1 == pRaInfo->BoundingType) && (1 == pRaInfo->BoundingCounter) + && (2 == pRaInfo->RateUpCounter)) { + pRaInfo->BoundingType = 0; + if (pRaInfo->BoundingLearningTime <= 5) + return 1; + /* Check if RA adjustment trend as ++--++--+(+)*/ + } else if ((2 == pRaInfo->BoundingType) && (2 == pRaInfo->BoundingCounter) + && (1 == pRaInfo->RateUpCounter)) { + pRaInfo->BoundingType = 0; + if (pRaInfo->BoundingLearningTime <= 2) + return 1; + /* Check if RA adjustment trend as +++++-----++(+)*/ + } else if ((3 == pRaInfo->BoundingType) && (1 == pRaInfo->BoundingCounter) + && (2 == pRaInfo->RateUpCounter)) { + pRaInfo->BoundingType = 0; + if (pRaInfo->BoundingLearningTime <= 4) + return 1; + } + } + + return 0; +} +#endif + +static void +odm_SetTxRPTTiming_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo, + IN u1Byte extend + ) +{ + u1Byte idx = 0; + + for(idx=0; idx<5; idx++) + if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) + break; + + if (extend==0) // back to default timing + idx=0; //200ms + else if (extend==1) {// increase the timing + idx+=1; + if (idx>5) + idx=5; + } + else if (extend==2) {// decrease the timing + if(idx!=0) + idx-=1; + } + pRaInfo->RptTime=DynamicTxRPTTiming[idx]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime)); +} + +static int +odm_RateDown_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, LowestRate, HighestRate; + s1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + LowestRate = pRaInfo->LowestRate; + HighestRate = pRaInfo->HighestRate; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", + RateID, LowestRate, HighestRate, pRaInfo->RateSGI)); + if (RateID > HighestRate) + { + RateID=HighestRate; + } + else if(pRaInfo->RateSGI) + { + pRaInfo->RateSGI=0; + } + else if (RateID > LowestRate) + { + if (RateID > 0) { + for (i = RateID - 1; i >= LowestRate; i--) { + if (pRaInfo->RAUseRate & BIT(i)) { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pRaInfo->RateDownCounter++; + pRaInfo->RateDirection = DM_RA_RATE_DOWN; + + /* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/ + if (0xFF == pRaInfo->RateDownStartTime) { + if ((0 == pRaInfo->RateUpCounter) || (pRaInfo->RateUpCounter+2 < pRaInfo->BoundingLearningTime)) + pRaInfo->RateDownStartTime = 0; + else + pRaInfo->RateDownStartTime = pRaInfo->BoundingLearningTime; + } +#endif + RateID=i; + goto RateDownFinish; + + } + } + } + } + else if (RateID <= LowestRate) + { + RateID = LowestRate; + } +RateDownFinish: +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + /*if (pRaInfo->RTY[2] >= 100) { + pRaInfo->RAWaitingCounter = 2; + pRaInfo->RAPendingCounter += 1; + } else */if ((0 != pRaInfo->RateDownStartTime) && (0xFF != pRaInfo->RateDownStartTime)) { + /* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/ + if (pRaInfo->RateDownCounter < pRaInfo->RateUpCounter) { + + } else if (pRaInfo->RateDownCounter == pRaInfo->RateUpCounter) { + pRaInfo->RAWaitingCounter = 2; + pRaInfo->RAPendingCounter += 1; + } else if (pRaInfo->RateDownCounter <= pRaInfo->RateUpCounter+2) { + RateID = pRaInfo->PreRate; + } else { + pRaInfo->RAWaitingCounter = 0; + pRaInfo->RAPendingCounter = 0; + pRaInfo->RateDownStartTime = 0; + } + } else +#endif + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter+=1; + pRaInfo->RAPendingCounter+=1; + } + else if(pRaInfo->RAWaitingCounter==0){ + } + else{ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + + if(pRaInfo->RAPendingCounter>=4) + pRaInfo->RAPendingCounter=4; + pRaInfo->RADropAfterDown = 1; + pRaInfo->DecisionRate = RateID; + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 2); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, Decrease RPT Timing\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d RADrop %d", pRaInfo->RAWaitingCounter, pRaInfo->RAPendingCounter, pRaInfo->RADropAfterDown)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDown_8188E()\n")); + return 0; +} + +static int +odm_RateUp_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, HighestRate; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + HighestRate = pRaInfo->HighestRate; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d HighestRate=%d\n", + RateID, HighestRate)); + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + else if (pRaInfo->RAWaitingCounter>1){ + pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pRaInfo->RateDownStartTime = 0; +#endif + goto RateUpfinish; + } + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): default RPT Timing\n")); + + if (RateID < HighestRate) + { + for (i=RateID+1; i<=HighestRate; i++) + { + if (pRaInfo->RAUseRate & BIT(i)) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if (odm_RA_LearnBounding(pDM_Odm, pRaInfo)) { + pRaInfo->RAWaitingCounter = 2; + pRaInfo->RAPendingCounter = 1; + goto RateUpfinish; + } + pRaInfo->RateUpCounter++; + pRaInfo->RateDirection = DM_RA_RATE_UP; +#endif + RateID=i; + goto RateUpfinish; + } + } + } + else if(RateID == HighestRate) + { + if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) + pRaInfo->RateSGI = 1; + else if((pRaInfo->SGIEnable) !=1 ) + pRaInfo->RateSGI = 0; + } + else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) + { + RateID = HighestRate; + + } +RateUpfinish: + //if(pRaInfo->RAWaitingCounter==10) + if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter])) { + pRaInfo->RAWaitingCounter=0; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + /* Mark persistence expiration state*/ + pRaInfo->RateDownStartTime = 0xFF; + /* Clear state to avoid wrong bounding check*/ + pRaInfo->RateDownCounter = 0; + pRaInfo->RateUpCounter = 0; + pRaInfo->RateDirection = 0; +#endif + } + else + pRaInfo->RAWaitingCounter++; + + pRaInfo->DecisionRate=RateID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateUp_8188E() \n")); + return 0; +} + +static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){ + u1Byte RateID; + RateID=pRaInfo->DecisionRate; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; +} + +static void +odm_RateDecision_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + //u4Byte pool_retry; + static u1Byte DynamicTxRPTTimingCounter=0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); + + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits + { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if (((pRaInfo->RssiStaRA <= 17) && (pRaInfo->RssiStaRA > pRaInfo->PreRssiStaRA)) + || ((pRaInfo->PreRssiStaRA <= 17) && (pRaInfo->PreRssiStaRA > pRaInfo->RssiStaRA))) { + /* don't reset state in low signal due to the power different between CCK and MCS is large.*/ + } else +#endif + if (pRaInfo->RADropAfterDown) { + pRaInfo->RADropAfterDown--; + odm_ResetRaCounter_8188E(pRaInfo); + return; + } + if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ + pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA; + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pRaInfo->BoundingType = 0; +#endif + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + if (0xff != pDM_Odm->priv->pshare->rf_ft_var.txforce) { + pRaInfo->PreRate = pDM_Odm->priv->pshare->rf_ft_var.txforce; + odm_ResetRaCounter_8188E(pRaInfo); + } +#endif + + // Start RA decision + if (pRaInfo->PreRate > pRaInfo->HighestRate) + RateID = pRaInfo->HighestRate; + else + RateID = pRaInfo->PreRate; + if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) + RtyPtID=0; + else + RtyPtID=1; + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown init is %d\n", pRaInfo->NscDown)); + //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; + pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; + pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; + pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; + pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown is %d, total*penalty[5] is %d\n", + pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) + pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; + else + pRaInfo->NscDown=0; + + // rate up + PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscUp init is %d\n", pRaInfo->NscUp)); + pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; + pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; + pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; + pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; + pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("NscUp is %d, total*up[5] is %d\n", + pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) + pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; + else + pRaInfo->NscUp = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE|ODM_COMP_INIT, ODM_DBG_LOUD, + (" RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d SGI=%d\n", + pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if (0xFF != pRaInfo->BoundingLearningTime) + pRaInfo->BoundingLearningTime++; +#endif + if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) + odm_RateDown_8188E(pDM_Odm,pRaInfo); + //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) + odm_RateUp_8188E(pDM_Odm,pRaInfo); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + else if ((pRaInfo->RTY[2] >= 100) && (ODM_BW20M == *pDM_Odm->pBandWidth)) + odm_RateDown_8188E(pDM_Odm,pRaInfo); +#endif + + if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) + DynamicTxRPTTimingCounter+=1; + else + DynamicTxRPTTimingCounter=0; + + if (DynamicTxRPTTimingCounter>=4) { + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<=====Rate don't change 4 times, Extend RPT Timing\n")); + DynamicTxRPTTimingCounter=0; + } + + pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 + + odm_ResetRaCounter_8188E( pRaInfo); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDecision_8188E() \n")); +} + +static int +odm_ARFBRefresh_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ // Wilson 2011/10/26 + u4Byte MaskFromReg; + u1Byte i; + + switch(pRaInfo->RateID){ + case RATR_INX_WIRELESS_NGB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8fe00f; + break; + case RATR_INX_WIRELESS_NG: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8fe00f; + break; + case RATR_INX_WIRELESS_N: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000fef; + break; + case RATR_INX_WIRELESS_G: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; + break; + case 12: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR0); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 13: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR1); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 14: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR2); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 15: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR3); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + + default: + pRaInfo->RAUseRate=(pRaInfo->RateMask); + break; + } + // Highest rate + if (pRaInfo->RAUseRate) + for (i = RATESIZE ; i >= 0 ; i--) + { + if((pRaInfo->RAUseRate)&BIT(i)){ + pRaInfo->HighestRate=i; + break; + } + } + else + pRaInfo->HighestRate=0; + // Lowest rate + if (pRaInfo->RAUseRate) + for (i=0;iRAUseRate)&BIT(i)) { + pRaInfo->LowestRate=i; + break; + } + } + else + pRaInfo->LowestRate=0; + +#if POWER_TRAINING_ACTIVE == 1 + if (pRaInfo->HighestRate >0x13) + pRaInfo->PTModeSS=3; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=2; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=1; + else + pRaInfo->PTModeSS=0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS)); + +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", + pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate)); + return 0; +} + +#if POWER_TRAINING_ACTIVE == 1 +static void +odm_PTTryState_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + pRaInfo->PTTryState=0; + switch (pRaInfo->PTModeSS) + { + case 3: + if (pRaInfo->DecisionRate>=0x19) + pRaInfo->PTTryState=1; + break; + case 2: + if (pRaInfo->DecisionRate>=0x11) + pRaInfo->PTTryState=1; + break; + case 1: + if (pRaInfo->DecisionRate>=0x0a) + pRaInfo->PTTryState=1; + break; + case 0: + if (pRaInfo->DecisionRate>=0x03) + pRaInfo->PTTryState=1; + break; + default: + pRaInfo->PTTryState=0; + } + + if (pRaInfo->RssiStaRA<48) + { + pRaInfo->PTStage=0; + } + else if (pRaInfo->PTTryState==1) + { + if ((pRaInfo->PTStopCount>=10)||(pRaInfo->PTPreRssi>pRaInfo->RssiStaRA+5) + ||(pRaInfo->PTPreRssiRssiStaRA-5)||(pRaInfo->DecisionRate!=pRaInfo->PTPreRate)) + { + if (pRaInfo->PTStage==0) + pRaInfo->PTStage=1; + else if(pRaInfo->PTStage==1) + pRaInfo->PTStage=3; + else + pRaInfo->PTStage=5; + + pRaInfo->PTPreRssi=pRaInfo->RssiStaRA; + pRaInfo->PTStopCount=0; + + } + else{ + pRaInfo->RAstage=0; + pRaInfo->PTStopCount++; + } + } + else{ + pRaInfo->PTStage=0; + pRaInfo->RAstage=0; + } + pRaInfo->PTPreRate=pRaInfo->DecisionRate; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + // Disable power training when noisy environment + if(pDM_Odm->bDisablePowerTraining) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_PTTryState_8188E(): Disable power training when noisy environment\n")); + pRaInfo->PTStage = 0; + pRaInfo->RAstage = 0; + pRaInfo->PTStopCount = 0; + } +#endif +} + +static void +odm_PTDecision_8188E( + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte stage_BUF; + u1Byte j; + u1Byte temp_stage; + u4Byte numsc; + u4Byte num_total; + u1Byte stage_id; + + stage_BUF=pRaInfo->PTStage; + numsc = 0; + num_total= pRaInfo->TOTAL* PT_PENALTY[5]; + for(j=0;j<=4;j++) + { + numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; + if(numsc>num_total) + break; + } + + j=j>>1; + temp_stage= (pRaInfo->PTStage +1)>>1; + if (temp_stage>j) + stage_id=temp_stage-j; + else + stage_id=0; + + pRaInfo->PTSmoothFactor=(pRaInfo->PTSmoothFactor>>1) + (pRaInfo->PTSmoothFactor>>2) + stage_id*16+2; + if (pRaInfo->PTSmoothFactor>192) + pRaInfo->PTSmoothFactor=192; + stage_id =pRaInfo->PTSmoothFactor>>6; + temp_stage=stage_id*2; + if (temp_stage!=0) + temp_stage-=1; + if (pRaInfo->DROP>3) + temp_stage=0; + pRaInfo->PTStage=temp_stage; + +} +#endif + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n")); + + + if(pDM_Odm->CurrminRptTime != minRptTime){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + (" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime)); + #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) + ODM_RA_Set_TxRPT_Time(pDM_Odm,minRptTime); + #else + rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime); + #endif + pDM_Odm->CurrminRptTime = minRptTime; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" <=====odm_RATxRPTTimerSetting()\n")); +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); + + // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! + if (pDM_Odm->SupportICType == ODM_RTL8188E) + pDM_Odm->RaSupport88E = TRUE; + + } + + + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u4Byte MacID + ) +{ + PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; + #if 0 + u1Byte WirelessMode=0xFF; //invalid value + u1Byte max_rate_idx = 0x13; //MCS7 + if(pDM_Odm->pWirelessMode!=NULL){ + WirelessMode=*(pDM_Odm->pWirelessMode); + } + + if(WirelessMode != 0xFF ){ + if(WirelessMode & ODM_WM_N24G) + max_rate_idx = 0x13; + else if(WirelessMode & ODM_WM_G) + max_rate_idx = 0x0b; + else if(WirelessMode & ODM_WM_B) + max_rate_idx = 0x03; + } + + //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", + WirelessMode,max_rate_idx)); + + pRaInfo->DecisionRate = max_rate_idx; + pRaInfo->PreRate = max_rate_idx; + pRaInfo->HighestRate=max_rate_idx; + #else + pRaInfo->DecisionRate = 0x13; + pRaInfo->PreRate = 0x13; + pRaInfo->HighestRate=0x13; + #endif + pRaInfo->LowestRate=0; + pRaInfo->RateID=0; + pRaInfo->RateMask=0xffffffff; + pRaInfo->RssiStaRA=0; + pRaInfo->PreRssiStaRA=0; + pRaInfo->SGIEnable=0; + pRaInfo->RAUseRate=0xffffffff; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->RateSGI=0; + pRaInfo->Active=1; //Active is not used at present. by page, 110819 + pRaInfo->RptTime = 0x927c; + pRaInfo->DROP=0; + pRaInfo->RTY[0]=0; + pRaInfo->RTY[1]=0; + pRaInfo->RTY[2]=0; + pRaInfo->RTY[3]=0; + pRaInfo->RTY[4]=0; + pRaInfo->TOTAL=0; + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + pRaInfo->RADropAfterDown = 0; +#if POWER_TRAINING_ACTIVE == 1 + pRaInfo->PTActive=1; // Active when this STA is use + pRaInfo->PTTryState=0; + pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS + pRaInfo->PTSmoothFactor=192; + pRaInfo->PTStopCount=0; + pRaInfo->PTPreRate=0; + pRaInfo->PTPreRssi=0; + pRaInfo->PTModeSS=0; + pRaInfo->RAstage=0; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pRaInfo->RateDownCounter = 0; + pRaInfo->RateUpCounter = 0; + pRaInfo->RateDirection = 0; + pRaInfo->BoundingType = 0; + pRaInfo->BoundingCounter = 0; + pRaInfo->BoundingLearningTime = 0; + pRaInfo->RateDownStartTime = 0; +#endif + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte MacID = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n")); + pDM_Odm->CurrminRptTime = 0; + + for(MacID=0; MacIDCutVersion == ODM_CUT_I) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + u1Byte i; + u1Byte RETRY_PENALTY_IDX_S[2][RATESIZE] = {{4,4,4,5, + 4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0b,0x0c, + 0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x13, // SSTH + 0x0b,0x0b,0x11,0x11,0x12,0x12,0x12,0x12, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + + for( i=0; iAdapter; + + //DbgPrint("Adapter->MgntInfo.RegRALvl = %d\n", Adapter->MgntInfo.RegRALvl); + + // + // 2012/09/14 MH Add for different Ra pattern init. For TPLINK case, we + // need to to adjust different RA pattern for middle range RA. 20-30dB degarde + // 88E rate adptve will raise too slow. + // + if (Adapter->MgntInfo.RegRALvl == 0) + { + RETRY_PENALTY_UP_IDX[11] = 0x14; + + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x14; + RETRY_PENALTY_UP_IDX[19] = 0x15; + + RETRY_PENALTY_UP_IDX[23] = 0x13; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x14; + RETRY_PENALTY_UP_IDX[27] = 0x15; + } + else if (Adapter->MgntInfo.RegRALvl == 1) + { + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x13; + RETRY_PENALTY_UP_IDX[19] = 0x14; + + RETRY_PENALTY_UP_IDX[23] = 0x12; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x13; + RETRY_PENALTY_UP_IDX[27] = 0x14; + } + else if (Adapter->MgntInfo.RegRALvl == 2) + { + // Compile flag default is lvl2, we need not to update. + } + else if (Adapter->MgntInfo.RegRALvl >= 0x80) + { + u1Byte index = 0, offset = Adapter->MgntInfo.RegRALvl - 0x80; + + // Reset to default rate adaptive value. + RETRY_PENALTY_UP_IDX[11] = 0x14; + + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x14; + RETRY_PENALTY_UP_IDX[19] = 0x15; + + RETRY_PENALTY_UP_IDX[23] = 0x13; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x14; + RETRY_PENALTY_UP_IDX[27] = 0x15; + + if (Adapter->MgntInfo.RegRALvl >= 0x90) + { + offset = Adapter->MgntInfo.RegRALvl - 0x90; + // Lazy mode. + for (index = 0; index < 28; index++) + { + RETRY_PENALTY_UP_IDX[index] += (offset); + } + } + else + { + // Aggrasive side. + for (index = 0; index < 28; index++) + { + RETRY_PENALTY_UP_IDX[index] -= (offset); + } + } + + } +} +#endif + return 0; +} + + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID +) +{ + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI)); + return pDM_Odm->RAInfo[MacID].RateSGI; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte DecisionRate = 0; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte CmdBuf[3]; + + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate); + + if (DecisionRate != pRA_Table->link_tx_rate[MacID]) { + + CmdBuf[1] = MacID; + CmdBuf[0] = DecisionRate; + phydm_c2h_ra_report_handler(pDM_Odm, &(CmdBuf[0]), 3); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d DecisionRate=0x%x\n", MacID, DecisionRate)); + return DecisionRate; +} + +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte PTStage = 5; + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + PTStage = (pDM_Odm->RAInfo[MacID].PTStage); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d PTStage=0x%x\n", MacID, PTStage)); + return PTStage; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n", + MacID, RateID, RateMask, SGIEnable)); + if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RateID = RateID; + pRaInfo->RateMask = RateMask; + pRaInfo->SGIEnable = SGIEnable; + odm_ARFBRefresh_8188E(pDM_Odm, pRaInfo); +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d Rssi=%d\n", MacID, Rssi)); + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RssiStaRA = Rssi; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (minRptTime != 0xffff) + { +#if defined(CONFIG_PCI_HCI) + ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + notify_tx_report_interval_change(pDM_Odm->priv, minRptTime); +#endif + } +#else + ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); +#endif + +} + + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + PODM_RA_INFO_T pRAInfo = NULL; + u1Byte MacId = 0; + pu1Byte pBuffer = NULL; + u4Byte valid = 0, ItemNum = 0; + u2Byte minRptTime = 0x927c; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n", + MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len)); + + ItemNum = TxRPT_Len >> 3; + pBuffer = TxRPT_Buf; + + do + { + valid = 0; + if(MacId < 32) + valid = (1<RAInfo[MacId]); + if(valid) + { + + + pRAInfo->RTY[0] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer); + pRAInfo->RTY[1] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_1(pBuffer); + pRAInfo->RTY[2] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_2(pBuffer); + pRAInfo->RTY[3] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_3(pBuffer); + pRAInfo->RTY[4] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_4(pBuffer); + pRAInfo->DROP = (u2Byte)GET_TX_REPORT_TYPE1_DROP_0(pBuffer); + + pRAInfo->TOTAL = pRAInfo->RTY[0] + \ + pRAInfo->RTY[1] + \ + pRAInfo->RTY[2] + \ + pRAInfo->RTY[3] + \ + pRAInfo->RTY[4] + \ + pRAInfo->DROP; +#if defined(TXRETRY_CNT) + extern struct stat_info *get_macidinfo(struct rtl8192cd_priv *priv, unsigned int aid); + + { + struct stat_info *pstat = get_macidinfo(pDM_Odm->priv, MacId); + if (pstat) { + pstat->cur_tx_ok += pRAInfo->RTY[0]; + pstat->cur_tx_retry_pkts += pRAInfo->RTY[1] + pRAInfo->RTY[2] + pRAInfo->RTY[3] + pRAInfo->RTY[4]; + pstat->cur_tx_retry_cnt += pRAInfo->RTY[1] + pRAInfo->RTY[2] * 2 + pRAInfo->RTY[3] * 3 + pRAInfo->RTY[4] * 4; + pstat->total_tx_retry_cnt += pstat->cur_tx_retry_cnt; + pstat->total_tx_retry_pkts += pstat->cur_tx_retry_pkts; + pstat->cur_tx_fail += pRAInfo->DROP; + } + } +#endif + if(pRAInfo->TOTAL != 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", + MacId, + pRAInfo->TOTAL, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0 , + MacIDValidEntry1)); +#if POWER_TRAINING_ACTIVE == 1 + if (pRAInfo->PTActive){ + if(pRAInfo->RAstage<5){ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } + else if(pRAInfo->RAstage==5){ // Power training try state + odm_PTTryState_8188E(pDM_Odm, pRAInfo); + } + else {// RAstage==6 + odm_PTDecision_8188E(pRAInfo); + } + + // Stage_RA counter + if (pRAInfo->RAstage<=5) + pRAInfo->RAstage++; + else + pRAInfo->RAstage=0; + } + else{ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } +#else + odm_RateDecision_8188E(pDM_Odm, pRAInfo); +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + extern void RTL8188E_SetStationTxRateInfo(PDM_ODM_T, PODM_RA_INFO_T, int); + RTL8188E_SetStationTxRateInfo(pDM_Odm, pRAInfo, MacId); +#ifdef DETECT_STA_EXISTANCE + void RTL8188E_DetectSTAExistance(PDM_ODM_T pDM_Odm, PODM_RA_INFO_T pRAInfo, int MacID); + RTL8188E_DetectSTAExistance(pDM_Odm, pRAInfo, MacId); +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x RateID=%d SGI=%d\n", + MacId, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0, + pRAInfo->DecisionRate, + pRAInfo->RateSGI)); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n")); + } + + if (minRptTime > pRAInfo->RptTime) + minRptTime = pRAInfo->RptTime; + + pBuffer += TX_RPT2_ITEM_SIZE; + MacId++; + }while(MacId < ItemNum); + + odm_RATxRPTTimerSetting(pDM_Odm,minRptTime); + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<===== ODM_RA_TxRPT2Handle_8188E()\n")); +} + +#else + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + return; +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + return; +} + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u4Byte MacID + ) +{ + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + return; +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + return; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ + return; +} + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + return; +} + + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.h b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.h index 823b5613ee0..3a6963dd07c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188erateadaptive.h @@ -1,111 +1,111 @@ -#ifndef __INC_RA_H -#define __INC_RA_H -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - RateAdaptive.h - -Abstract: - Prototype of RA and related data structure. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-12 Page Create. ---*/ - -// Rate adaptive define -#define PERENTRY 23 -#define RETRYSIZE 5 -#define RATESIZE 28 -#define TX_RPT2_ITEM_SIZE 8 - -#define DM_RA_RATE_UP 1 -#define DM_RA_RATE_DOWN 2 - -#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -// -// TX report 2 format in Rx desc -// -#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) -#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) -#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) - -#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) -#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) -#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) -#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) -#endif - -// End rate adaptive define - -VOID -ODM_RASupport_Init( - IN PDM_ODM_T pDM_Odm - ); - -int -ODM_RAInfo_Init_all( - IN PDM_ODM_T pDM_Odm - ); - -int -ODM_RAInfo_Init( - IN PDM_ODM_T pDM_Odm, - IN u4Byte MacID - ); - -u1Byte -ODM_RA_GetShortGI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ); - -u1Byte -ODM_RA_GetDecisionRate_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ); - -u1Byte -ODM_RA_GetHwPwrStatus_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID - ); -VOID -ODM_RA_UpdateRateInfo_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte RateID, - IN u4Byte RateMask, - IN u1Byte SGIEnable - ); - -VOID -ODM_RA_SetRSSI_8188E( - IN PDM_ODM_T pDM_Odm, - IN u1Byte MacID, - IN u1Byte Rssi - ); - -VOID -ODM_RA_TxRPT2Handle_8188E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte TxRPT_Buf, - IN u2Byte TxRPT_Len, - IN u4Byte MacIDValidEntry0, - IN u4Byte MacIDValidEntry1 - ); - - -VOID -ODM_RA_Set_TxRPT_Time( - IN PDM_ODM_T pDM_Odm, - IN u2Byte minRptTime - ); -#endif - +#ifndef __INC_RA_H +#define __INC_RA_H +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.h + +Abstract: + Prototype of RA and related data structure. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. +--*/ + +// Rate adaptive define +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +#define TX_RPT2_ITEM_SIZE 8 + +#define DM_RA_RATE_UP 1 +#define DM_RA_RATE_DOWN 2 + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +// +// TX report 2 format in Rx desc +// +#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) +#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) +#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) +#endif + +// End rate adaptive define + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ); + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ); + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u4Byte MacID + ); + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); + +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ); +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ); + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ); + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ); + + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ); +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188ereg.h b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188ereg.h index cdfe9e8a4dc..c3550878985 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188ereg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/hal8188ereg.h @@ -1,65 +1,65 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -//============================================================ -// File Name: hal8188ereg.h -// -// Description: -// -// This file is for RTL8188E register definition. -// -// -//============================================================ -#ifndef __HAL_8188E_REG_H__ -#define __HAL_8188E_REG_H__ - -// -// Register Definition -// -#define TRX_ANTDIV_PATH 0x860 -#define RX_ANTDIV_PATH 0xb2c -#define ODM_R_A_AGC_CORE1_8188E 0xc50 - -#define REG_GPIO_EXT_CTRL 0x0060 - -#define REG_MCUFWDL_8188E 0x0080 -#define REG_FW_DBG_STATUS_8188E 0x0088 -#define REG_FW_DBG_CTRL_8188E 0x008F - -#define REG_CR_8188E 0x0100 - - -// -// Bitmap Definition -// -#define BIT_FA_RESET_8188E BIT0 -#define REG_ADAPTIVE_DATA_RATE_0 0x2B0 -#define REG_DBI_WDATA_8188 0x0348 // DBI Write Data -#define REG_DBI_RDATA_8188 0x034C // DBI Read Data -#define REG_DBI_ADDR_8188 0x0350 // DBI Address -#define REG_DBI_FLAG_8188 0x0352 // DBI Read/Write Flag -#define REG_MDIO_WDATA_8188E 0x0354 // MDIO for Write PCIE PHY -#define REG_MDIO_RDATA_8188E 0x0356 // MDIO for Reads PCIE PHY -#define REG_MDIO_CTL_8188E 0x0358 // MDIO for Control - -// [0-63] -#define REG_MACID_NO_LINK 0x484 // No Link register (bit[x] enabled means dropping packets for MACID in HW queue) - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: hal8188ereg.h +// +// Description: +// +// This file is for RTL8188E register definition. +// +// +//============================================================ +#ifndef __HAL_8188E_REG_H__ +#define __HAL_8188E_REG_H__ + +// +// Register Definition +// +#define TRX_ANTDIV_PATH 0x860 +#define RX_ANTDIV_PATH 0xb2c +#define ODM_R_A_AGC_CORE1_8188E 0xc50 + +#define REG_GPIO_EXT_CTRL 0x0060 + +#define REG_MCUFWDL_8188E 0x0080 +#define REG_FW_DBG_STATUS_8188E 0x0088 +#define REG_FW_DBG_CTRL_8188E 0x008F + +#define REG_CR_8188E 0x0100 + + +// +// Bitmap Definition +// +#define BIT_FA_RESET_8188E BIT0 +#define REG_ADAPTIVE_DATA_RATE_0 0x2B0 +#define REG_DBI_WDATA_8188 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8188 0x034C // DBI Read Data +#define REG_DBI_ADDR_8188 0x0350 // DBI Address +#define REG_DBI_FLAG_8188 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8188E 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8188E 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8188E 0x0358 // MDIO for Control + +// [0-63] +#define REG_MACID_NO_LINK 0x484 // No Link register (bit[x] enabled means dropping packets for MACID in HW queue) + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.c index 0d2eaa8a3f2..594d3921012 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.c @@ -1,1371 +1,1371 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8188E_AGC_TAB[] = { - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xF6000001, - 0xC78, 0xF5010001, - 0xC78, 0xF4020001, - 0xC78, 0xF3030001, - 0xC78, 0xF2040001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xF7000001, - 0xC78, 0xF6010001, - 0xC78, 0xF5020001, - 0xC78, 0xF4030001, - 0xC78, 0xF3040001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFA010001, - 0xC78, 0xF9020001, - 0xC78, 0xF8030001, - 0xC78, 0xF7040001, - 0xA0000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFB010001, - 0xC78, 0xFB020001, - 0xC78, 0xFB030001, - 0xC78, 0xFB040001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xF1050001, - 0xC78, 0xF0060001, - 0xC78, 0xEF070001, - 0xC78, 0xEE080001, - 0xC78, 0xED090001, - 0xC78, 0xEC0A0001, - 0xC78, 0xEB0B0001, - 0xC78, 0xEA0C0001, - 0xC78, 0xE90D0001, - 0xC78, 0xE80E0001, - 0xC78, 0xE70F0001, - 0xC78, 0xE6100001, - 0xC78, 0xE5110001, - 0xC78, 0xE4120001, - 0xC78, 0xE3130001, - 0xC78, 0xE2140001, - 0xC78, 0xC5150001, - 0xC78, 0xC4160001, - 0xC78, 0xC3170001, - 0xC78, 0xC2180001, - 0xC78, 0x88190001, - 0xC78, 0x871A0001, - 0xC78, 0x861B0001, - 0xC78, 0x851C0001, - 0xC78, 0x841D0001, - 0xC78, 0x831E0001, - 0xC78, 0x821F0001, - 0xC78, 0x81200001, - 0xC78, 0x80210001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xF2050001, - 0xC78, 0xF1060001, - 0xC78, 0xF0070001, - 0xC78, 0xEF080001, - 0xC78, 0xEE090001, - 0xC78, 0xED0A0001, - 0xC78, 0xEC0B0001, - 0xC78, 0xEB0C0001, - 0xC78, 0xEA0D0001, - 0xC78, 0xE90E0001, - 0xC78, 0xE80F0001, - 0xC78, 0xE7100001, - 0xC78, 0xE6110001, - 0xC78, 0xE5120001, - 0xC78, 0xE4130001, - 0xC78, 0xE3140001, - 0xC78, 0xE2150001, - 0xC78, 0xE1160001, - 0xC78, 0x89170001, - 0xC78, 0x88180001, - 0xC78, 0x87190001, - 0xC78, 0x861A0001, - 0xC78, 0x851B0001, - 0xC78, 0x841C0001, - 0xC78, 0x831D0001, - 0xC78, 0x821E0001, - 0xC78, 0x811F0001, - 0xC78, 0x6B200001, - 0xC78, 0x6A210001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0xF6050001, - 0xC78, 0xF5060001, - 0xC78, 0xF4070001, - 0xC78, 0xF3080001, - 0xC78, 0xF2090001, - 0xC78, 0xF10A0001, - 0xC78, 0xF00B0001, - 0xC78, 0xEF0C0001, - 0xC78, 0xEE0D0001, - 0xC78, 0xED0E0001, - 0xC78, 0xEC0F0001, - 0xC78, 0xEB100001, - 0xC78, 0xEA110001, - 0xC78, 0xE9120001, - 0xC78, 0xE8130001, - 0xC78, 0xE7140001, - 0xC78, 0xE6150001, - 0xC78, 0xE5160001, - 0xC78, 0xE4170001, - 0xC78, 0xE3180001, - 0xC78, 0xE2190001, - 0xC78, 0xE11A0001, - 0xC78, 0x8A1B0001, - 0xC78, 0x891C0001, - 0xC78, 0x881D0001, - 0xC78, 0x871E0001, - 0xC78, 0x861F0001, - 0xC78, 0x85200001, - 0xC78, 0x84210001, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xFA050001, - 0xC78, 0xF9060001, - 0xC78, 0xF8070001, - 0xC78, 0xF7080001, - 0xC78, 0xF6090001, - 0xC78, 0xF50A0001, - 0xC78, 0xF40B0001, - 0xC78, 0xF30C0001, - 0xC78, 0xF20D0001, - 0xC78, 0xF10E0001, - 0xC78, 0xF00F0001, - 0xC78, 0xEF100001, - 0xC78, 0xEE110001, - 0xC78, 0xED120001, - 0xC78, 0xEC130001, - 0xC78, 0xEB140001, - 0xC78, 0xEA150001, - 0xC78, 0xE9160001, - 0xC78, 0xE8170001, - 0xC78, 0xE7180001, - 0xC78, 0xE6190001, - 0xC78, 0xE51A0001, - 0xC78, 0xE41B0001, - 0xC78, 0xC71C0001, - 0xC78, 0xC61D0001, - 0xC78, 0xC51E0001, - 0xC78, 0xC41F0001, - 0xC78, 0xC3200001, - 0xC78, 0xC2210001, - 0xA0000000, 0x00000000, - 0xC78, 0xFB050001, - 0xC78, 0xFA060001, - 0xC78, 0xF9070001, - 0xC78, 0xF8080001, - 0xC78, 0xF7090001, - 0xC78, 0xF60A0001, - 0xC78, 0xF50B0001, - 0xC78, 0xF40C0001, - 0xC78, 0xF30D0001, - 0xC78, 0xF20E0001, - 0xC78, 0xF10F0001, - 0xC78, 0xF0100001, - 0xC78, 0xEF110001, - 0xC78, 0xEE120001, - 0xC78, 0xED130001, - 0xC78, 0xEC140001, - 0xC78, 0xEB150001, - 0xC78, 0xEA160001, - 0xC78, 0xE9170001, - 0xC78, 0xE8180001, - 0xC78, 0xE7190001, - 0xC78, 0xE61A0001, - 0xC78, 0xE51B0001, - 0xC78, 0xE41C0001, - 0xC78, 0xE31D0001, - 0xC78, 0xE21E0001, - 0xC78, 0xE11F0001, - 0xC78, 0x8A200001, - 0xC78, 0x89210001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x66220001, - 0xC78, 0x65230001, - 0xC78, 0x64240001, - 0xC78, 0x63250001, - 0xC78, 0x62260001, - 0xC78, 0x61270001, - 0xC78, 0x60280001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x69220001, - 0xC78, 0x68230001, - 0xC78, 0x67240001, - 0xC78, 0x66250001, - 0xC78, 0x65260001, - 0xC78, 0x64270001, - 0xC78, 0x63280001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x83220001, - 0xC78, 0x82230001, - 0xC78, 0x6B240001, - 0xC78, 0x6A250001, - 0xC78, 0x69260001, - 0xC78, 0x68270001, - 0xC78, 0x67280001, - 0xA0000000, 0x00000000, - 0xC78, 0x88220001, - 0xC78, 0x87230001, - 0xC78, 0x86240001, - 0xC78, 0x85250001, - 0xC78, 0x84260001, - 0xC78, 0x83270001, - 0xC78, 0x82280001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x4A290001, - 0xC78, 0x492A0001, - 0xC78, 0x482B0001, - 0xC78, 0x472C0001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x62290001, - 0xC78, 0x612A0001, - 0xC78, 0x462B0001, - 0xC78, 0x452C0001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x66290001, - 0xC78, 0x652A0001, - 0xC78, 0x642B0001, - 0xC78, 0x632C0001, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x81290001, - 0xC78, 0x242A0001, - 0xC78, 0x232B0001, - 0xC78, 0x222C0001, - 0xA0000000, 0x00000000, - 0xC78, 0x6B290001, - 0xC78, 0x6A2A0001, - 0xC78, 0x692B0001, - 0xC78, 0x682C0001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x462D0001, - 0xC78, 0x452E0001, - 0xC78, 0x442F0001, - 0xC78, 0x43300001, - 0xC78, 0x42310001, - 0xC78, 0x41320001, - 0xC78, 0x40330001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x442D0001, - 0xC78, 0x432E0001, - 0xC78, 0x422F0001, - 0xC78, 0x41300001, - 0xC78, 0x40310001, - 0xC78, 0x40320001, - 0xC78, 0x40330001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x622D0001, - 0xC78, 0x612E0001, - 0xC78, 0x462F0001, - 0xC78, 0x45300001, - 0xC78, 0x44310001, - 0xC78, 0x43320001, - 0xC78, 0x42330001, - 0xA0000000, 0x00000000, - 0xC78, 0x672D0001, - 0xC78, 0x662E0001, - 0xC78, 0x652F0001, - 0xC78, 0x64300001, - 0xC78, 0x63310001, - 0xC78, 0x62320001, - 0xC78, 0x61330001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x40340001, - 0xC78, 0x40350001, - 0xC78, 0x40360001, - 0xC78, 0x40370001, - 0xC78, 0x40380001, - 0xC78, 0x40390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x40340001, - 0xC78, 0x40350001, - 0xC78, 0x40360001, - 0xC78, 0x40370001, - 0xC78, 0x40380001, - 0xC78, 0x40390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x41340001, - 0xC78, 0x40350001, - 0xC78, 0x40360001, - 0xC78, 0x40370001, - 0xC78, 0x40380001, - 0xC78, 0x40390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x60340001, - 0xC78, 0x4A350001, - 0xC78, 0x49360001, - 0xC78, 0x48370001, - 0xC78, 0x47380001, - 0xC78, 0x46390001, - 0xC78, 0x453A0001, - 0xC78, 0x443B0001, - 0xC78, 0x433C0001, - 0xC78, 0x423D0001, - 0xC78, 0x413E0001, - 0xA0000000, 0x00000000, - 0xC78, 0x46340001, - 0xC78, 0x45350001, - 0xC78, 0x44360001, - 0xC78, 0x43370001, - 0xC78, 0x42380001, - 0xC78, 0x41390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x403F0001, - 0xA0000000, 0x00000000, - 0xC78, 0x403F0001, - 0xB0000000, 0x00000000, - 0x88000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xFB400001, - 0xC78, 0xFA410001, - 0xC78, 0xF9420001, - 0xC78, 0xF8430001, - 0xC78, 0xF7440001, - 0xC78, 0xF6450001, - 0xC78, 0xF5460001, - 0xC78, 0xF4470001, - 0xC78, 0xF3480001, - 0xC78, 0xF2490001, - 0xC78, 0xF14A0001, - 0xC78, 0xF04B0001, - 0xC78, 0xEF4C0001, - 0xC78, 0xEE4D0001, - 0xC78, 0xED4E0001, - 0xC78, 0xEC4F0001, - 0xC78, 0xEB500001, - 0xC78, 0xEA510001, - 0xC78, 0xE9520001, - 0xC78, 0xE8530001, - 0xC78, 0xE7540001, - 0xC78, 0xE6550001, - 0xC78, 0xE5560001, - 0xC78, 0xC6570001, - 0xC78, 0xC5580001, - 0xC78, 0xC4590001, - 0xC78, 0xC35A0001, - 0xC78, 0xC25B0001, - 0xC78, 0xC15C0001, - 0xC78, 0xC05D0001, - 0xC78, 0xA35E0001, - 0xC78, 0xA25F0001, - 0xC78, 0xA1600001, - 0xC78, 0x88610001, - 0xC78, 0x87620001, - 0xC78, 0x86630001, - 0xC78, 0x85640001, - 0xC78, 0x84650001, - 0xC78, 0x83660001, - 0xC78, 0x82670001, - 0xC78, 0x66680001, - 0xC78, 0x65690001, - 0xC78, 0x646A0001, - 0xC78, 0x636B0001, - 0xC78, 0x626C0001, - 0xC78, 0x616D0001, - 0xC78, 0x486E0001, - 0xC78, 0x476F0001, - 0xC78, 0x46700001, - 0xC78, 0x45710001, - 0xC78, 0x44720001, - 0xC78, 0x43730001, - 0xC78, 0x42740001, - 0xC78, 0x41750001, - 0xC78, 0x40760001, - 0xC78, 0x40770001, - 0xC78, 0x40780001, - 0xC78, 0x40790001, - 0xC78, 0x407A0001, - 0xC78, 0x407B0001, - 0xC78, 0x407C0001, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xFB400001, - 0xC78, 0xFA410001, - 0xC78, 0xF9420001, - 0xC78, 0xF8430001, - 0xC78, 0xF7440001, - 0xC78, 0xF6450001, - 0xC78, 0xF5460001, - 0xC78, 0xF4470001, - 0xC78, 0xF3480001, - 0xC78, 0xF2490001, - 0xC78, 0xF14A0001, - 0xC78, 0xF04B0001, - 0xC78, 0xEF4C0001, - 0xC78, 0xEE4D0001, - 0xC78, 0xED4E0001, - 0xC78, 0xEC4F0001, - 0xC78, 0xEB500001, - 0xC78, 0xEA510001, - 0xC78, 0xE9520001, - 0xC78, 0xE8530001, - 0xC78, 0xE7540001, - 0xC78, 0xE6550001, - 0xC78, 0xE5560001, - 0xC78, 0xE4570001, - 0xC78, 0xE3580001, - 0xC78, 0xE2590001, - 0xC78, 0xC35A0001, - 0xC78, 0xC25B0001, - 0xC78, 0xC15C0001, - 0xC78, 0x8B5D0001, - 0xC78, 0x8A5E0001, - 0xC78, 0x895F0001, - 0xC78, 0x88600001, - 0xC78, 0x87610001, - 0xC78, 0x86620001, - 0xC78, 0x85630001, - 0xC78, 0x84640001, - 0xC78, 0x67650001, - 0xC78, 0x66660001, - 0xC78, 0x65670001, - 0xC78, 0x64680001, - 0xC78, 0x63690001, - 0xC78, 0x626A0001, - 0xC78, 0x616B0001, - 0xC78, 0x606C0001, - 0xC78, 0x466D0001, - 0xC78, 0x456E0001, - 0xC78, 0x446F0001, - 0xC78, 0x43700001, - 0xC78, 0x42710001, - 0xC78, 0x41720001, - 0xC78, 0x40730001, - 0xC78, 0x40740001, - 0xC78, 0x40750001, - 0xC78, 0x40760001, - 0xC78, 0x40770001, - 0xC78, 0x40780001, - 0xC78, 0x40790001, - 0xC78, 0x407A0001, - 0xC78, 0x407B0001, - 0xC78, 0x407C0001, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0xFB400001, - 0xC78, 0xFB410001, - 0xC78, 0xFB420001, - 0xC78, 0xFB430001, - 0xC78, 0xFB440001, - 0xC78, 0xFB450001, - 0xC78, 0xFA460001, - 0xC78, 0xF9470001, - 0xC78, 0xF8480001, - 0xC78, 0xF7490001, - 0xC78, 0xF64A0001, - 0xC78, 0xF54B0001, - 0xC78, 0xF44C0001, - 0xC78, 0xF34D0001, - 0xC78, 0xF24E0001, - 0xC78, 0xF14F0001, - 0xC78, 0xF0500001, - 0xC78, 0xEF510001, - 0xC78, 0xEE520001, - 0xC78, 0xED530001, - 0xC78, 0xEC540001, - 0xC78, 0xEB550001, - 0xC78, 0xEA560001, - 0xC78, 0xE9570001, - 0xC78, 0xE8580001, - 0xC78, 0xE7590001, - 0xC78, 0xE65A0001, - 0xC78, 0xE55B0001, - 0xC78, 0xC65C0001, - 0xC78, 0xC55D0001, - 0xC78, 0xC45E0001, - 0xC78, 0xC35F0001, - 0xC78, 0xC2600001, - 0xC78, 0xC1610001, - 0xC78, 0xC0620001, - 0xC78, 0xA3630001, - 0xC78, 0xA2640001, - 0xC78, 0xA1650001, - 0xC78, 0x88660001, - 0xC78, 0x87670001, - 0xC78, 0x86680001, - 0xC78, 0x85690001, - 0xC78, 0x846A0001, - 0xC78, 0x836B0001, - 0xC78, 0x826C0001, - 0xC78, 0x666D0001, - 0xC78, 0x656E0001, - 0xC78, 0x646F0001, - 0xC78, 0x63700001, - 0xC78, 0x62710001, - 0xC78, 0x61720001, - 0xC78, 0x48730001, - 0xC78, 0x47740001, - 0xC78, 0x46750001, - 0xC78, 0x45760001, - 0xC78, 0x44770001, - 0xC78, 0x43780001, - 0xC78, 0x42790001, - 0xC78, 0x417A0001, - 0xC78, 0x407B0001, - 0xC78, 0x407C0001, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xFF400001, - 0xC78, 0xFF410001, - 0xC78, 0xFE420001, - 0xC78, 0xFD430001, - 0xC78, 0xFC440001, - 0xC78, 0xFB450001, - 0xC78, 0xFA460001, - 0xC78, 0xF9470001, - 0xC78, 0xF8480001, - 0xC78, 0xF7490001, - 0xC78, 0xF64A0001, - 0xC78, 0xF54B0001, - 0xC78, 0xF44C0001, - 0xC78, 0xF34D0001, - 0xC78, 0xF24E0001, - 0xC78, 0xF14F0001, - 0xC78, 0xF0500001, - 0xC78, 0xEF510001, - 0xC78, 0xEE520001, - 0xC78, 0xED530001, - 0xC78, 0xEC540001, - 0xC78, 0xEB550001, - 0xC78, 0xEA560001, - 0xC78, 0xE9570001, - 0xC78, 0xE8580001, - 0xC78, 0xE7590001, - 0xC78, 0xE65A0001, - 0xC78, 0xE55B0001, - 0xC78, 0xE45C0001, - 0xC78, 0xA85D0001, - 0xC78, 0xA75E0001, - 0xC78, 0xA65F0001, - 0xC78, 0xA5600001, - 0xC78, 0xA4610001, - 0xC78, 0xA3620001, - 0xC78, 0xA2630001, - 0xC78, 0xA1640001, - 0xC78, 0x28650001, - 0xC78, 0x27660001, - 0xC78, 0x26670001, - 0xC78, 0x07680001, - 0xC78, 0x06690001, - 0xC78, 0x056A0001, - 0xC78, 0x046B0001, - 0xC78, 0x036C0001, - 0xC78, 0x026D0001, - 0xC78, 0x016E0001, - 0xC78, 0x646F0001, - 0xC78, 0x63700001, - 0xC78, 0x62710001, - 0xC78, 0x61720001, - 0xC78, 0x47730001, - 0xC78, 0x46740001, - 0xC78, 0x45750001, - 0xC78, 0x44760001, - 0xC78, 0x43770001, - 0xC78, 0x42780001, - 0xC78, 0x41790001, - 0xC78, 0x407A0001, - 0xC78, 0x407B0001, - 0xC78, 0x407C0001, - 0xA0000000, 0x00000000, - 0xC78, 0xFB400001, - 0xC78, 0xFB410001, - 0xC78, 0xFB420001, - 0xC78, 0xFB430001, - 0xC78, 0xFB440001, - 0xC78, 0xFB450001, - 0xC78, 0xFB460001, - 0xC78, 0xFB470001, - 0xC78, 0xFB480001, - 0xC78, 0xFA490001, - 0xC78, 0xF94A0001, - 0xC78, 0xF84B0001, - 0xC78, 0xF74C0001, - 0xC78, 0xF64D0001, - 0xC78, 0xF54E0001, - 0xC78, 0xF44F0001, - 0xC78, 0xF3500001, - 0xC78, 0xF2510001, - 0xC78, 0xF1520001, - 0xC78, 0xF0530001, - 0xC78, 0xEF540001, - 0xC78, 0xEE550001, - 0xC78, 0xED560001, - 0xC78, 0xEC570001, - 0xC78, 0xEB580001, - 0xC78, 0xEA590001, - 0xC78, 0xE95A0001, - 0xC78, 0xE85B0001, - 0xC78, 0xE75C0001, - 0xC78, 0xE65D0001, - 0xC78, 0xE55E0001, - 0xC78, 0xE45F0001, - 0xC78, 0xE3600001, - 0xC78, 0xE2610001, - 0xC78, 0xC3620001, - 0xC78, 0xC2630001, - 0xC78, 0xC1640001, - 0xC78, 0x8B650001, - 0xC78, 0x8A660001, - 0xC78, 0x89670001, - 0xC78, 0x88680001, - 0xC78, 0x87690001, - 0xC78, 0x866A0001, - 0xC78, 0x856B0001, - 0xC78, 0x846C0001, - 0xC78, 0x676D0001, - 0xC78, 0x666E0001, - 0xC78, 0x656F0001, - 0xC78, 0x64700001, - 0xC78, 0x63710001, - 0xC78, 0x62720001, - 0xC78, 0x61730001, - 0xC78, 0x60740001, - 0xC78, 0x46750001, - 0xC78, 0x45760001, - 0xC78, 0x44770001, - 0xC78, 0x43780001, - 0xC78, 0x42790001, - 0xC78, 0x417A0001, - 0xC78, 0x407B0001, - 0xC78, 0x407C0001, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000001, 0x40000000, 0x00000000, - 0xC78, 0x407D0001, - 0xC78, 0x407E0001, - 0xC78, 0x407F0001, - 0xA0000000, 0x00000000, - 0xC78, 0x407D0001, - 0xC78, 0x407E0001, - 0xC78, 0x407F0001, - 0xB0000000, 0x00000000, - 0xC50, 0x69553422, - 0xC50, 0x69553420, - -}; - -void -ODM_ReadAndConfig_MP_8188E_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188E_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188E_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188E_AGC_TAB(void) -{ - return 69; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188E_PHY_REG[] = { - 0x800, 0x80040000, - 0x804, 0x00000003, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x02200385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390204, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390004, - 0xA0000000, 0x00000000, - 0x824, 0x00390204, - 0xB0000000, 0x00000000, - 0x828, 0x00000000, - 0x82C, 0x00000000, - 0x830, 0x00000000, - 0x834, 0x00000000, - 0x838, 0x00000000, - 0x83C, 0x00000000, - 0x840, 0x00010000, - 0x844, 0x00000000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00000000, - 0x854, 0x00000000, - 0x858, 0x569A11A9, - 0x85C, 0x01000014, - 0x860, 0x66F60110, - 0x864, 0x061F0649, - 0x868, 0x00000000, - 0x86C, 0x27272700, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x870, 0x07000300, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x870, 0x07000760, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x870, 0x07000760, - 0xA0000000, 0x00000000, - 0x870, 0x07000760, - 0xB0000000, 0x00000000, - 0x874, 0x25004000, - 0x878, 0x00000808, - 0x87C, 0x00000000, - 0x880, 0xB0000C1C, - 0x884, 0x00000001, - 0x888, 0x00000000, - 0x88C, 0xCCC000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121111, - 0x910, 0x00000002, - 0x914, 0x00000201, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0xA08, 0x8C838300, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E34120F, - 0xA0000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0xB0000000, 0x00000000, - 0xA10, 0x9500BB7E, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x13130000, - 0xA24, 0x060A0D10, - 0xA28, 0x00000103, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xA20, 0x13130000, - 0xA24, 0x060A0D10, - 0xA28, 0x00000103, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x13130000, - 0xA24, 0x060A0D10, - 0xA28, 0x00000103, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0xA0000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0xB0000000, 0x00000000, - 0xA2C, 0x00D30000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000007, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x218075B1, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x21807531, - 0xA0000000, 0x00000000, - 0xA80, 0x218075B1, - 0xB0000000, 0x00000000, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xB2C, 0x00000000, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xB2C, 0x80000000, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xB2C, 0x80000000, - 0xA0000000, 0x00000000, - 0xB2C, 0x80000000, - 0xB0000000, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05611, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x08800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9AC47, - 0xC34, 0x469652AF, - 0xC38, 0x49795994, - 0xC3C, 0x0A97971C, - 0xC40, 0x1F7C403F, - 0xC44, 0x000100B7, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0xC50, 0x69553420, - 0xC54, 0x43BC0094, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00013169, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC58, 0x00013169, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00013159, - 0xA0000000, 0x00000000, - 0xC58, 0x00013169, - 0xB0000000, 0x00000000, - 0xC5C, 0x00250492, - 0xC60, 0x00000000, - 0xC64, 0x7112848B, - 0xC68, 0x47C00BFF, - 0xC6C, 0x00000036, - 0xC70, 0x2C7F000D, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC74, 0x020610DB, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC74, 0x020610DB, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC74, 0x028610DB, - 0xA0000000, 0x00000000, - 0xC74, 0x020610DB, - 0xB0000000, 0x00000000, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x2D4000B5, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x390000E4, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xC80, 0x2D4000B5, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xC80, 0x390000E4, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x2D4000B5, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xC80, 0x390000E4, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x390000E4, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x390000E4, - 0xA0000000, 0x00000000, - 0xC80, 0x390000E4, - 0xB0000000, 0x00000000, - 0xC84, 0x21F60000, - 0xC88, 0x40000100, - 0xC8C, 0x20200000, - 0xC90, 0x00091521, - 0xC94, 0x00000000, - 0xC98, 0x00121820, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00000000, - 0xCA4, 0x000300A0, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xCA8, 0x00000000, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xCA8, 0x00000000, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xCA8, 0xFFFF0000, - 0xA0000000, 0x00000000, - 0xCA8, 0x00000000, - 0xB0000000, 0x00000000, - 0xCAC, 0x00000000, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x00222222, - 0xCE4, 0x00000000, - 0xCE8, 0x37644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x00000740, - 0xD04, 0x00020401, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC43, - 0xD18, 0x7A8F5B6F, - 0xD2C, 0xCC979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x00000000, - 0xD3C, 0x00127353, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xD6C, 0x2A201C16, - 0xD70, 0x1812362E, - 0xD74, 0x322C2220, - 0xD78, 0x000E3C24, - 0xE00, 0x2D2D2D2D, - 0xE04, 0x2D2D2D2D, - 0xE08, 0x0390272D, - 0xE10, 0x2D2D2D2D, - 0xE14, 0x2D2D2D2D, - 0xE18, 0x2D2D2D2D, - 0xE1C, 0x2D2D2D2D, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000048, - 0xE68, 0x001B25A4, - 0xE6C, 0x00C00014, - 0xE70, 0x00C00014, - 0xE74, 0x01000014, - 0xE78, 0x01000014, - 0xE7C, 0x01000014, - 0xE80, 0x01000014, - 0xE84, 0x00C00014, - 0xE88, 0x01000014, - 0xE8C, 0x00C00014, - 0xED0, 0x00C00014, - 0xED4, 0x00C00014, - 0xED8, 0x00C00014, - 0xEDC, 0x00000014, - 0xEE0, 0x00000014, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x98000003, 0x00000001, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x98000001, 0x00000001, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0xEE8, 0x32555448, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0xEE8, 0x21555448, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0xEE8, 0x21555448, - 0xA0000000, 0x00000000, - 0xEE8, 0x21555448, - 0xB0000000, 0x00000000, - 0xEEC, 0x01C00014, - 0xF14, 0x00000003, - 0xF4C, 0x00000000, - 0xF00, 0x00000300, - -}; - -void -ODM_ReadAndConfig_MP_8188E_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188E_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188E_PHY_REG(void) -{ - return 69; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188E_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x40424446, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 -}; - -void -ODM_ReadAndConfig_MP_8188E_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188E_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8188E_AGC_TAB[] = { + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF6000001, + 0xC78, 0xF5010001, + 0xC78, 0xF4020001, + 0xC78, 0xF3030001, + 0xC78, 0xF2040001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF7000001, + 0xC78, 0xF6010001, + 0xC78, 0xF5020001, + 0xC78, 0xF4030001, + 0xC78, 0xF3040001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFA010001, + 0xC78, 0xF9020001, + 0xC78, 0xF8030001, + 0xC78, 0xF7040001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF1050001, + 0xC78, 0xF0060001, + 0xC78, 0xEF070001, + 0xC78, 0xEE080001, + 0xC78, 0xED090001, + 0xC78, 0xEC0A0001, + 0xC78, 0xEB0B0001, + 0xC78, 0xEA0C0001, + 0xC78, 0xE90D0001, + 0xC78, 0xE80E0001, + 0xC78, 0xE70F0001, + 0xC78, 0xE6100001, + 0xC78, 0xE5110001, + 0xC78, 0xE4120001, + 0xC78, 0xE3130001, + 0xC78, 0xE2140001, + 0xC78, 0xC5150001, + 0xC78, 0xC4160001, + 0xC78, 0xC3170001, + 0xC78, 0xC2180001, + 0xC78, 0x88190001, + 0xC78, 0x871A0001, + 0xC78, 0x861B0001, + 0xC78, 0x851C0001, + 0xC78, 0x841D0001, + 0xC78, 0x831E0001, + 0xC78, 0x821F0001, + 0xC78, 0x81200001, + 0xC78, 0x80210001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF2050001, + 0xC78, 0xF1060001, + 0xC78, 0xF0070001, + 0xC78, 0xEF080001, + 0xC78, 0xEE090001, + 0xC78, 0xED0A0001, + 0xC78, 0xEC0B0001, + 0xC78, 0xEB0C0001, + 0xC78, 0xEA0D0001, + 0xC78, 0xE90E0001, + 0xC78, 0xE80F0001, + 0xC78, 0xE7100001, + 0xC78, 0xE6110001, + 0xC78, 0xE5120001, + 0xC78, 0xE4130001, + 0xC78, 0xE3140001, + 0xC78, 0xE2150001, + 0xC78, 0xE1160001, + 0xC78, 0x89170001, + 0xC78, 0x88180001, + 0xC78, 0x87190001, + 0xC78, 0x861A0001, + 0xC78, 0x851B0001, + 0xC78, 0x841C0001, + 0xC78, 0x831D0001, + 0xC78, 0x821E0001, + 0xC78, 0x811F0001, + 0xC78, 0x6B200001, + 0xC78, 0x6A210001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xF6050001, + 0xC78, 0xF5060001, + 0xC78, 0xF4070001, + 0xC78, 0xF3080001, + 0xC78, 0xF2090001, + 0xC78, 0xF10A0001, + 0xC78, 0xF00B0001, + 0xC78, 0xEF0C0001, + 0xC78, 0xEE0D0001, + 0xC78, 0xED0E0001, + 0xC78, 0xEC0F0001, + 0xC78, 0xEB100001, + 0xC78, 0xEA110001, + 0xC78, 0xE9120001, + 0xC78, 0xE8130001, + 0xC78, 0xE7140001, + 0xC78, 0xE6150001, + 0xC78, 0xE5160001, + 0xC78, 0xE4170001, + 0xC78, 0xE3180001, + 0xC78, 0xE2190001, + 0xC78, 0xE11A0001, + 0xC78, 0x8A1B0001, + 0xC78, 0x891C0001, + 0xC78, 0x881D0001, + 0xC78, 0x871E0001, + 0xC78, 0x861F0001, + 0xC78, 0x85200001, + 0xC78, 0x84210001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFA050001, + 0xC78, 0xF9060001, + 0xC78, 0xF8070001, + 0xC78, 0xF7080001, + 0xC78, 0xF6090001, + 0xC78, 0xF50A0001, + 0xC78, 0xF40B0001, + 0xC78, 0xF30C0001, + 0xC78, 0xF20D0001, + 0xC78, 0xF10E0001, + 0xC78, 0xF00F0001, + 0xC78, 0xEF100001, + 0xC78, 0xEE110001, + 0xC78, 0xED120001, + 0xC78, 0xEC130001, + 0xC78, 0xEB140001, + 0xC78, 0xEA150001, + 0xC78, 0xE9160001, + 0xC78, 0xE8170001, + 0xC78, 0xE7180001, + 0xC78, 0xE6190001, + 0xC78, 0xE51A0001, + 0xC78, 0xE41B0001, + 0xC78, 0xC71C0001, + 0xC78, 0xC61D0001, + 0xC78, 0xC51E0001, + 0xC78, 0xC41F0001, + 0xC78, 0xC3200001, + 0xC78, 0xC2210001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xE51B0001, + 0xC78, 0xE41C0001, + 0xC78, 0xE31D0001, + 0xC78, 0xE21E0001, + 0xC78, 0xE11F0001, + 0xC78, 0x8A200001, + 0xC78, 0x89210001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x66220001, + 0xC78, 0x65230001, + 0xC78, 0x64240001, + 0xC78, 0x63250001, + 0xC78, 0x62260001, + 0xC78, 0x61270001, + 0xC78, 0x60280001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x69220001, + 0xC78, 0x68230001, + 0xC78, 0x67240001, + 0xC78, 0x66250001, + 0xC78, 0x65260001, + 0xC78, 0x64270001, + 0xC78, 0x63280001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x83220001, + 0xC78, 0x82230001, + 0xC78, 0x6B240001, + 0xC78, 0x6A250001, + 0xC78, 0x69260001, + 0xC78, 0x68270001, + 0xC78, 0x67280001, + 0xA0000000, 0x00000000, + 0xC78, 0x88220001, + 0xC78, 0x87230001, + 0xC78, 0x86240001, + 0xC78, 0x85250001, + 0xC78, 0x84260001, + 0xC78, 0x83270001, + 0xC78, 0x82280001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x4A290001, + 0xC78, 0x492A0001, + 0xC78, 0x482B0001, + 0xC78, 0x472C0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x62290001, + 0xC78, 0x612A0001, + 0xC78, 0x462B0001, + 0xC78, 0x452C0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x66290001, + 0xC78, 0x652A0001, + 0xC78, 0x642B0001, + 0xC78, 0x632C0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x81290001, + 0xC78, 0x242A0001, + 0xC78, 0x232B0001, + 0xC78, 0x222C0001, + 0xA0000000, 0x00000000, + 0xC78, 0x6B290001, + 0xC78, 0x6A2A0001, + 0xC78, 0x692B0001, + 0xC78, 0x682C0001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x462D0001, + 0xC78, 0x452E0001, + 0xC78, 0x442F0001, + 0xC78, 0x43300001, + 0xC78, 0x42310001, + 0xC78, 0x41320001, + 0xC78, 0x40330001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x442D0001, + 0xC78, 0x432E0001, + 0xC78, 0x422F0001, + 0xC78, 0x41300001, + 0xC78, 0x40310001, + 0xC78, 0x40320001, + 0xC78, 0x40330001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x622D0001, + 0xC78, 0x612E0001, + 0xC78, 0x462F0001, + 0xC78, 0x45300001, + 0xC78, 0x44310001, + 0xC78, 0x43320001, + 0xC78, 0x42330001, + 0xA0000000, 0x00000000, + 0xC78, 0x672D0001, + 0xC78, 0x662E0001, + 0xC78, 0x652F0001, + 0xC78, 0x64300001, + 0xC78, 0x63310001, + 0xC78, 0x62320001, + 0xC78, 0x61330001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x40340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x40340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x41340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x60340001, + 0xC78, 0x4A350001, + 0xC78, 0x49360001, + 0xC78, 0x48370001, + 0xC78, 0x47380001, + 0xC78, 0x46390001, + 0xC78, 0x453A0001, + 0xC78, 0x443B0001, + 0xC78, 0x433C0001, + 0xC78, 0x423D0001, + 0xC78, 0x413E0001, + 0xA0000000, 0x00000000, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x403F0001, + 0xA0000000, 0x00000000, + 0xC78, 0x403F0001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFA410001, + 0xC78, 0xF9420001, + 0xC78, 0xF8430001, + 0xC78, 0xF7440001, + 0xC78, 0xF6450001, + 0xC78, 0xF5460001, + 0xC78, 0xF4470001, + 0xC78, 0xF3480001, + 0xC78, 0xF2490001, + 0xC78, 0xF14A0001, + 0xC78, 0xF04B0001, + 0xC78, 0xEF4C0001, + 0xC78, 0xEE4D0001, + 0xC78, 0xED4E0001, + 0xC78, 0xEC4F0001, + 0xC78, 0xEB500001, + 0xC78, 0xEA510001, + 0xC78, 0xE9520001, + 0xC78, 0xE8530001, + 0xC78, 0xE7540001, + 0xC78, 0xE6550001, + 0xC78, 0xE5560001, + 0xC78, 0xC6570001, + 0xC78, 0xC5580001, + 0xC78, 0xC4590001, + 0xC78, 0xC35A0001, + 0xC78, 0xC25B0001, + 0xC78, 0xC15C0001, + 0xC78, 0xC05D0001, + 0xC78, 0xA35E0001, + 0xC78, 0xA25F0001, + 0xC78, 0xA1600001, + 0xC78, 0x88610001, + 0xC78, 0x87620001, + 0xC78, 0x86630001, + 0xC78, 0x85640001, + 0xC78, 0x84650001, + 0xC78, 0x83660001, + 0xC78, 0x82670001, + 0xC78, 0x66680001, + 0xC78, 0x65690001, + 0xC78, 0x646A0001, + 0xC78, 0x636B0001, + 0xC78, 0x626C0001, + 0xC78, 0x616D0001, + 0xC78, 0x486E0001, + 0xC78, 0x476F0001, + 0xC78, 0x46700001, + 0xC78, 0x45710001, + 0xC78, 0x44720001, + 0xC78, 0x43730001, + 0xC78, 0x42740001, + 0xC78, 0x41750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFA410001, + 0xC78, 0xF9420001, + 0xC78, 0xF8430001, + 0xC78, 0xF7440001, + 0xC78, 0xF6450001, + 0xC78, 0xF5460001, + 0xC78, 0xF4470001, + 0xC78, 0xF3480001, + 0xC78, 0xF2490001, + 0xC78, 0xF14A0001, + 0xC78, 0xF04B0001, + 0xC78, 0xEF4C0001, + 0xC78, 0xEE4D0001, + 0xC78, 0xED4E0001, + 0xC78, 0xEC4F0001, + 0xC78, 0xEB500001, + 0xC78, 0xEA510001, + 0xC78, 0xE9520001, + 0xC78, 0xE8530001, + 0xC78, 0xE7540001, + 0xC78, 0xE6550001, + 0xC78, 0xE5560001, + 0xC78, 0xE4570001, + 0xC78, 0xE3580001, + 0xC78, 0xE2590001, + 0xC78, 0xC35A0001, + 0xC78, 0xC25B0001, + 0xC78, 0xC15C0001, + 0xC78, 0x8B5D0001, + 0xC78, 0x8A5E0001, + 0xC78, 0x895F0001, + 0xC78, 0x88600001, + 0xC78, 0x87610001, + 0xC78, 0x86620001, + 0xC78, 0x85630001, + 0xC78, 0x84640001, + 0xC78, 0x67650001, + 0xC78, 0x66660001, + 0xC78, 0x65670001, + 0xC78, 0x64680001, + 0xC78, 0x63690001, + 0xC78, 0x626A0001, + 0xC78, 0x616B0001, + 0xC78, 0x606C0001, + 0xC78, 0x466D0001, + 0xC78, 0x456E0001, + 0xC78, 0x446F0001, + 0xC78, 0x43700001, + 0xC78, 0x42710001, + 0xC78, 0x41720001, + 0xC78, 0x40730001, + 0xC78, 0x40740001, + 0xC78, 0x40750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xC65C0001, + 0xC78, 0xC55D0001, + 0xC78, 0xC45E0001, + 0xC78, 0xC35F0001, + 0xC78, 0xC2600001, + 0xC78, 0xC1610001, + 0xC78, 0xC0620001, + 0xC78, 0xA3630001, + 0xC78, 0xA2640001, + 0xC78, 0xA1650001, + 0xC78, 0x88660001, + 0xC78, 0x87670001, + 0xC78, 0x86680001, + 0xC78, 0x85690001, + 0xC78, 0x846A0001, + 0xC78, 0x836B0001, + 0xC78, 0x826C0001, + 0xC78, 0x666D0001, + 0xC78, 0x656E0001, + 0xC78, 0x646F0001, + 0xC78, 0x63700001, + 0xC78, 0x62710001, + 0xC78, 0x61720001, + 0xC78, 0x48730001, + 0xC78, 0x47740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFF400001, + 0xC78, 0xFF410001, + 0xC78, 0xFE420001, + 0xC78, 0xFD430001, + 0xC78, 0xFC440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xE45C0001, + 0xC78, 0xA85D0001, + 0xC78, 0xA75E0001, + 0xC78, 0xA65F0001, + 0xC78, 0xA5600001, + 0xC78, 0xA4610001, + 0xC78, 0xA3620001, + 0xC78, 0xA2630001, + 0xC78, 0xA1640001, + 0xC78, 0x28650001, + 0xC78, 0x27660001, + 0xC78, 0x26670001, + 0xC78, 0x07680001, + 0xC78, 0x06690001, + 0xC78, 0x056A0001, + 0xC78, 0x046B0001, + 0xC78, 0x036C0001, + 0xC78, 0x026D0001, + 0xC78, 0x016E0001, + 0xC78, 0x646F0001, + 0xC78, 0x63700001, + 0xC78, 0x62710001, + 0xC78, 0x61720001, + 0xC78, 0x47730001, + 0xC78, 0x46740001, + 0xC78, 0x45750001, + 0xC78, 0x44760001, + 0xC78, 0x43770001, + 0xC78, 0x42780001, + 0xC78, 0x41790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xA0000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xB0000000, 0x00000000, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +ODM_ReadAndConfig_MP_8188E_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188E_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188E_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188E_AGC_TAB(void) +{ + return 69; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188E_PHY_REG[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0xA0000000, 0x00000000, + 0x824, 0x00390204, + 0xB0000000, 0x00000000, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000760, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000760, + 0xA0000000, 0x00000000, + 0x870, 0x07000760, + 0xB0000000, 0x00000000, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x8C838300, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E34120F, + 0xA0000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0xB0000000, 0x00000000, + 0xA10, 0x9500BB7E, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA0000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xB0000000, 0x00000000, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0xA0000000, 0x00000000, + 0xA80, 0x218075B1, + 0xB0000000, 0x00000000, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x80000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x80000000, + 0xA0000000, 0x00000000, + 0xB2C, 0x80000000, + 0xB0000000, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC47, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0xA0000000, 0x00000000, + 0xC58, 0x00013169, + 0xB0000000, 0x00000000, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0xA0000000, 0x00000000, + 0xC74, 0x020610DB, + 0xB0000000, 0x00000000, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0xA0000000, 0x00000000, + 0xC80, 0x390000E4, + 0xB0000000, 0x00000000, + 0xC84, 0x21F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0xA0000000, 0x00000000, + 0xCA8, 0x00000000, + 0xB0000000, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00000740, + 0xD04, 0x00020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC43, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000048, + 0xE68, 0x001B25A4, + 0xE6C, 0x00C00014, + 0xE70, 0x00C00014, + 0xE74, 0x01000014, + 0xE78, 0x01000014, + 0xE7C, 0x01000014, + 0xE80, 0x01000014, + 0xE84, 0x00C00014, + 0xE88, 0x01000014, + 0xE8C, 0x00C00014, + 0xED0, 0x00C00014, + 0xED4, 0x00C00014, + 0xED8, 0x00C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x21555448, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x21555448, + 0xA0000000, 0x00000000, + 0xEE8, 0x21555448, + 0xB0000000, 0x00000000, + 0xEEC, 0x01C00014, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +ODM_ReadAndConfig_MP_8188E_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188E_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188E_PHY_REG(void) +{ + return 69; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188E_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 +}; + +void +ODM_ReadAndConfig_MP_8188E_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188E_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.h index 33378a1c3c1..5fa7850cd2c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188E_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8188E_H -#define __INC_MP_BB_HW_IMG_8188E_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8188E_H +#define __INC_MP_BB_HW_IMG_8188E_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.c index eeaeef7c8a4..91be2d28b05 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.c @@ -1,287 +1,287 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188E_MAC_REG[] = { - 0x026, 0x00000041, - 0x027, 0x00000035, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x040, 0x0000000C, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x040, 0x0000000C, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x040, 0x0000000C, - 0xA0000000, 0x00000000, - 0x040, 0x00000000, - 0xB0000000, 0x00000000, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000001, - 0x432, 0x00000002, - 0x433, 0x00000004, - 0x434, 0x00000005, - 0x435, 0x00000006, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x438, 0x00000000, - 0x439, 0x00000000, - 0x43A, 0x00000001, - 0x43B, 0x00000002, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000006, - 0x43F, 0x00000007, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000015, - 0x445, 0x000000F0, - 0x446, 0x0000000F, - 0x447, 0x00000000, - 0x458, 0x00000041, - 0x459, 0x000000A8, - 0x45A, 0x00000072, - 0x45B, 0x000000B9, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x480, 0x00000008, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4D3, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x63C, 0x00000008, - 0x63D, 0x00000008, - 0x63E, 0x0000000C, - 0x63F, 0x0000000C, - 0x640, 0x00000040, - 0x652, 0x00000020, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - -}; - -void -ODM_ReadAndConfig_MP_8188E_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188E_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188E_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188E_MAC_REG(void) -{ - return 69; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188E_MAC_REG[] = { + 0x026, 0x00000041, + 0x027, 0x00000035, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0xA0000000, 0x00000000, + 0x040, 0x00000000, + 0xB0000000, 0x00000000, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000001, + 0x432, 0x00000002, + 0x433, 0x00000004, + 0x434, 0x00000005, + 0x435, 0x00000006, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x438, 0x00000000, + 0x439, 0x00000000, + 0x43A, 0x00000001, + 0x43B, 0x00000002, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000006, + 0x43F, 0x00000007, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000015, + 0x445, 0x000000F0, + 0x446, 0x0000000F, + 0x447, 0x00000000, + 0x458, 0x00000041, + 0x459, 0x000000A8, + 0x45A, 0x00000072, + 0x45B, 0x000000B9, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x480, 0x00000008, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4D3, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x63C, 0x00000008, + 0x63D, 0x00000008, + 0x63E, 0x0000000C, + 0x63F, 0x0000000C, + 0x640, 0x00000040, + 0x652, 0x00000020, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + +}; + +void +ODM_ReadAndConfig_MP_8188E_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188E_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188E_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188E_MAC_REG(void) +{ + return 69; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.h index 1769373785d..be58a9e3385 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188E_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8188E_H -#define __INC_MP_MAC_HW_IMG_8188E_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8188E_H +#define __INC_MP_MAC_HW_IMG_8188E_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.c index 97c829fef80..f5c4f4336d3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.c @@ -1,2149 +1,2149 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8188E_RadioA[] = { - 0x000, 0x00030000, - 0x008, 0x00084000, - 0x018, 0x00000407, - 0x019, 0x00000012, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000084, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000084, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000084, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000084, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0xA0000000, 0x00000000, - 0xB0000000, 0x00000000, - 0x01E, 0x00080009, - 0x01F, 0x00000880, - 0x02F, 0x0001A060, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000C0000, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000C0000, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000C0000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000000, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x03F, 0x00000000, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000C0000, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000000, - 0xB0000000, 0x00000000, - 0x042, 0x000060C0, - 0x057, 0x000D0000, - 0x058, 0x000BE180, - 0x067, 0x00001552, - 0x083, 0x00000000, - 0x0B0, 0x000FF8FC, - 0x0B1, 0x00054400, - 0x0B2, 0x000CCC19, - 0x0B4, 0x00043003, - 0x0B6, 0x0004953E, - 0x0B7, 0x0001C718, - 0x0B8, 0x000060FF, - 0x0B9, 0x00080001, - 0x0BA, 0x00040000, - 0x0BB, 0x00000400, - 0x0BF, 0x000C0000, - 0x0C2, 0x00002400, - 0x0C3, 0x00000009, - 0x0C4, 0x00040C91, - 0x0C5, 0x00099999, - 0x0C6, 0x000000A3, - 0x0C7, 0x00088820, - 0x0C8, 0x00076C06, - 0x0C9, 0x00000000, - 0x0CA, 0x00080000, - 0x0DF, 0x00000180, - 0x0EF, 0x000001A0, - 0x051, 0x0006B27D, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E49D, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E49D, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E4DD, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E49D, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x052, 0x0007E49D, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E49D, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x0007E4DD, - 0xA0000000, 0x00000000, - 0x052, 0x0007E49D, - 0xB0000000, 0x00000000, - 0x053, 0x00000073, - 0x056, 0x00051FF3, - 0x035, 0x00000086, - 0x035, 0x00000186, - 0x035, 0x00000286, - 0x036, 0x00001C25, - 0x036, 0x00009C25, - 0x036, 0x00011C25, - 0x036, 0x00019C25, - 0x0B6, 0x00048538, - 0x018, 0x00000C07, - 0x05A, 0x0004BD00, - 0x019, 0x000739D0, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A095, - 0x034, 0x00009092, - 0x034, 0x0000808E, - 0x034, 0x0000704F, - 0x034, 0x0000604C, - 0x034, 0x00005049, - 0x034, 0x0000400C, - 0x034, 0x00003009, - 0x034, 0x00002006, - 0x034, 0x00001003, - 0x034, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A095, - 0x034, 0x00009092, - 0x034, 0x0000808E, - 0x034, 0x0000704F, - 0x034, 0x0000604C, - 0x034, 0x00005049, - 0x034, 0x0000400C, - 0x034, 0x00003009, - 0x034, 0x00002006, - 0x034, 0x00001003, - 0x034, 0x00000000, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF3, - 0x034, 0x00009DF0, - 0x034, 0x00008DED, - 0x034, 0x00007DEA, - 0x034, 0x00006DE7, - 0x034, 0x000054EE, - 0x034, 0x000044EB, - 0x034, 0x000034E8, - 0x034, 0x0000246B, - 0x034, 0x00001468, - 0x034, 0x0000006D, - 0xB0000000, 0x00000000, - 0x000, 0x00030159, - 0x084, 0x00068200, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0008014E, - 0x087, 0x0004DF80, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0xA0000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00048A00, - 0xB0000000, 0x00000000, - 0x08E, 0x00065540, - 0x08F, 0x00088000, - 0x0EF, 0x000020A0, - 0x88000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x98000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x98000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x90000001, 0x00000001, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0x98000000, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F6030, - 0x03B, 0x000E6030, - 0x03B, 0x000D6030, - 0x03B, 0x000C6030, - 0x03B, 0x000BF030, - 0x03B, 0x000A0020, - 0x03B, 0x00090090, - 0x03B, 0x0008F080, - 0x03B, 0x0007A730, - 0x03B, 0x000607B0, - 0x03B, 0x0005F770, - 0x03B, 0x00040060, - 0x03B, 0x00030090, - 0x03B, 0x00020780, - 0x03B, 0x000107A0, - 0x03B, 0x0000F760, - 0x0EF, 0x000000A0, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0xA0000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0x03B, 0x000722B0, - 0x03B, 0x0006F7B0, - 0x03B, 0x00054FB0, - 0x03B, 0x0004F060, - 0x03B, 0x00030090, - 0x03B, 0x00020080, - 0x03B, 0x00010080, - 0x03B, 0x0000F780, - 0x0EF, 0x000000A0, - 0xB0000000, 0x00000000, - 0x000, 0x00010159, - 0x018, 0x0000F407, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01F, 0x00080003, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01E, 0x00000001, - 0x01F, 0x00080000, - 0x000, 0x00033E60, - -}; - -void -ODM_ReadAndConfig_MP_8188E_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188E_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188E_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188E_RadioA(void) -{ - return 69; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -#endif - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -#endif - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE_ICUT.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE_ICUT( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -#endif - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO_ICUT.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO_ICUT( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -#endif - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB_ICUT.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB_ICUT( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8188E_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "30", - "FCC", "2.4G", "20M", "HT", "1T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "30", - "FCC", "2.4G", "20M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "30", - "FCC", "2.4G", "20M", "HT", "1T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "30", - "FCC", "2.4G", "20M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "30", - "FCC", "2.4G", "20M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "30", - "FCC", "2.4G", "20M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "30", - "FCC", "2.4G", "20M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "30", - "FCC", "2.4G", "20M", "HT", "1T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "30", - "FCC", "2.4G", "20M", "HT", "1T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "30", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "30", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "30", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "30", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "26", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", - "MKK", "2.4G", "40M", "HT", "1T", "04", "26", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", - "MKK", "2.4G", "40M", "HT", "1T", "05", "26", - "FCC", "2.4G", "40M", "HT", "1T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", - "MKK", "2.4G", "40M", "HT", "1T", "06", "26", - "FCC", "2.4G", "40M", "HT", "1T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", - "MKK", "2.4G", "40M", "HT", "1T", "07", "26", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", - "MKK", "2.4G", "40M", "HT", "1T", "08", "26", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", - "MKK", "2.4G", "40M", "HT", "1T", "09", "26", - "FCC", "2.4G", "40M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", - "MKK", "2.4G", "40M", "HT", "1T", "10", "26", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "26", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", - "MKK", "2.4G", "40M", "HT", "1T", "12", "26", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", - "MKK", "2.4G", "40M", "HT", "1T", "13", "26", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", - "MKK", "2.4G", "40M", "HT", "2T", "12", "26", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", - "MKK", "2.4G", "40M", "HT", "2T", "13", "26", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "30", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "28", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8188E_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8188E_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8188E_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8188E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_88EE_M2_for_MSI.TXT -******************************************************************************/ - -const char *Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "30", - "FCC", "2.4G", "20M", "HT", "1T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "30", - "FCC", "2.4G", "20M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "30", - "FCC", "2.4G", "20M", "HT", "1T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "30", - "FCC", "2.4G", "20M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "30", - "FCC", "2.4G", "20M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "30", - "FCC", "2.4G", "20M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "30", - "FCC", "2.4G", "20M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "30", - "FCC", "2.4G", "20M", "HT", "1T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "30", - "FCC", "2.4G", "20M", "HT", "1T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "30", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "30", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "30", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "30", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "26", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", - "MKK", "2.4G", "40M", "HT", "1T", "04", "26", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", - "MKK", "2.4G", "40M", "HT", "1T", "05", "26", - "FCC", "2.4G", "40M", "HT", "1T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", - "MKK", "2.4G", "40M", "HT", "1T", "06", "26", - "FCC", "2.4G", "40M", "HT", "1T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", - "MKK", "2.4G", "40M", "HT", "1T", "07", "26", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", - "MKK", "2.4G", "40M", "HT", "1T", "08", "26", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", - "MKK", "2.4G", "40M", "HT", "1T", "09", "26", - "FCC", "2.4G", "40M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", - "MKK", "2.4G", "40M", "HT", "1T", "10", "26", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "26", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", - "MKK", "2.4G", "40M", "HT", "1T", "12", "26", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", - "MKK", "2.4G", "40M", "HT", "1T", "13", "26", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", - "MKK", "2.4G", "40M", "HT", "2T", "12", "26", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", - "MKK", "2.4G", "40M", "HT", "2T", "13", "26", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "30", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "28", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8188E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8188E_RadioA[] = { + 0x000, 0x00030000, + 0x008, 0x00084000, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000000, + 0xB0000000, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF8FC, + 0x0B1, 0x00054400, + 0x0B2, 0x000CCC19, + 0x0B4, 0x00043003, + 0x0B6, 0x0004953E, + 0x0B7, 0x0001C718, + 0x0B8, 0x000060FF, + 0x0B9, 0x00080001, + 0x0BA, 0x00040000, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x0006B27D, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E4DD, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E4DD, + 0xA0000000, 0x00000000, + 0x052, 0x0007E49D, + 0xB0000000, 0x00000000, + 0x053, 0x00000073, + 0x056, 0x00051FF3, + 0x035, 0x00000086, + 0x035, 0x00000186, + 0x035, 0x00000286, + 0x036, 0x00001C25, + 0x036, 0x00009C25, + 0x036, 0x00011C25, + 0x036, 0x00019C25, + 0x0B6, 0x00048538, + 0x018, 0x00000C07, + 0x05A, 0x0004BD00, + 0x019, 0x000739D0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008DED, + 0x034, 0x00007DEA, + 0x034, 0x00006DE7, + 0x034, 0x000054EE, + 0x034, 0x000044EB, + 0x034, 0x000034E8, + 0x034, 0x0000246B, + 0x034, 0x00001468, + 0x034, 0x0000006D, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00068200, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0008014E, + 0x087, 0x0004DF80, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0xA0000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0xB0000000, 0x00000000, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F6030, + 0x03B, 0x000E6030, + 0x03B, 0x000D6030, + 0x03B, 0x000C6030, + 0x03B, 0x000BF030, + 0x03B, 0x000A0020, + 0x03B, 0x00090090, + 0x03B, 0x0008F080, + 0x03B, 0x0007A730, + 0x03B, 0x000607B0, + 0x03B, 0x0005F770, + 0x03B, 0x00040060, + 0x03B, 0x00030090, + 0x03B, 0x00020780, + 0x03B, 0x000107A0, + 0x03B, 0x0000F760, + 0x0EF, 0x000000A0, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0xA0000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0xB0000000, 0x00000000, + 0x000, 0x00010159, + 0x018, 0x0000F407, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E60, + +}; + +void +ODM_ReadAndConfig_MP_8188E_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188E_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188E_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188E_RadioA(void) +{ + return 69; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188E[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188E[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8188E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE_ICUT.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE_ICUT( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO_ICUT.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO_ICUT( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188E[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188E[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB_ICUT.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_ICUT_8188E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_ICUT_8188E[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_ICUT_8188E[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB_ICUT( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_ICUT_8188E, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8188E_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8188E_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188E_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8188E_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8188E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_88EE_M2_for_MSI.TXT +******************************************************************************/ + +const char *Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8188E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.h index 4b6ba835a39..63886feefeb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_rf.h @@ -1,129 +1,129 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188E_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8188E_H -#define __INC_MP_RF_HW_IMG_8188E_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_PCIE_ICUT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE_ICUT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_PCIE_ICUT(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_SDIO_ICUT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO_ICUT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_SDIO_ICUT(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_USB(void); - -/****************************************************************************** -* TxPowerTrack_USB_ICUT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB_ICUT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_USB_ICUT(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT(void); - -/****************************************************************************** -* TXPWR_LMT_88EE_M2_for_MSI.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8188E_H +#define __INC_MP_RF_HW_IMG_8188E_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_PCIE_ICUT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE_ICUT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_PCIE_ICUT(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_SDIO_ICUT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO_ICUT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_SDIO_ICUT(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_USB(void); + +/****************************************************************************** +* TxPowerTrack_USB_ICUT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB_ICUT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_USB_ICUT(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT(void); + +/****************************************************************************** +* TXPWR_LMT_88EE_M2_for_MSI.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.c index 6cc55d11d21..04e2efd7874 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.c @@ -1,3648 +1,3648 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8188e/hal8188e_s_fw.h" -#endif - - -#if (RTL8188E_S_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188E_S_FW_AP[] = { -0xE3, 0x88, 0x20, 0x00, 0x17, 0x00, 0x00, 0x00, 0x10, 0x27, 0x15, 0x22, 0xEE, 0x3C, 0x02, 0x00, -0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x47, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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(ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_S_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_S_FW_NIC, ArrayLength_MP_8188E_S_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8188E_S_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188E_S_FW_WoWLAN[] = { -0xE3, 0x88, 0x30, 0x00, 0x17, 0x00, 0x00, 0x00, 0x10, 0x27, 0x15, 0x22, 0x38, 0x55, 0x02, 0x00, -0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x49, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x4A, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x57, 0xFD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x49, 0xBE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, -0x00, 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(SIZE_PTR)Array_MP_8188E_S_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_S_FW_WoWLAN, ArrayLength_MP_8188E_S_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8188E_S_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8188e/hal8188e_s_fw.h" +#endif + + +#if (RTL8188E_S_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_S_FW_AP[] = { +0xE3, 0x88, 0x20, 0x00, 0x17, 0x00, 0x00, 0x00, 0x10, 0x27, 0x15, 0x22, 0xEE, 0x3C, 0x02, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x47, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x01, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x44, 0x40, 0xF0, 0xE0, 0x44, +0x80, 0xF0, 0x22, 0xEF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0xFE, 0xEF, 0x54, 0x07, 0xFF, 0x22, 0x90, +0x81, 0x6D, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x22, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, +0x83, 0xE0, 0x22, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x22, 0xE4, 0x90, 0x81, 0x49, +0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x77, 0xE0, 0x90, 0x05, 0x73, 0x22, 0x72, 0x75, +}; +u4Byte ArrayLength_MP_8188E_S_FW_AP = 15630; + +#endif + +void +ODM_ReadFirmware_MP_8188E_S_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_S_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_S_FW_AP, ArrayLength_MP_8188E_S_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_S_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_S_FW_NIC[] = { +0xE3, 0x88, 0x10, 0x00, 0x17, 0x00, 0x00, 0x00, 0x10, 0x27, 0x15, 0x22, 0x68, 0x4A, 0x02, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x49, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x57, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x48, 0xF3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x01, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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(ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_S_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_S_FW_NIC, ArrayLength_MP_8188E_S_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_S_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_S_FW_WoWLAN[] = { +0xE3, 0x88, 0x30, 0x00, 0x17, 0x00, 0x00, 0x00, 0x10, 0x27, 0x15, 0x22, 0x38, 0x55, 0x02, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x49, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x4A, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x57, 0xFD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x49, 0xBE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, +0x00, 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(SIZE_PTR)Array_MP_8188E_S_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_S_FW_WoWLAN, ArrayLength_MP_8188E_S_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_S_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.h index 2bc3cf8620b..18336cd53b7 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_s_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8188E_S_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8188E_S_H -#define __INC_MP_FW_HW_IMG_8188E_S_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_S_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_S_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_S_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8188E_S_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8188E_S_H +#define __INC_MP_FW_HW_IMG_8188E_S_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_S_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_S_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_S_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.c index 91701166956..5ed22c83bc4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.c @@ -1,3902 +1,3902 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8188e/hal8188e_t_fw.h" -#endif - - -#if (RTL8188E_T_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188E_T_FW_AP[] = { -0xE1, 0x88, 0x20, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0xEC, 0x3A, 0x00, 0x00, -0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x45, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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*pFirmwareSize = ArrayLength_MP_8188E_T_FW_NIC_89EM; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188E_T_FW_WoWLAN[] = { -0xE1, 0x88, 0x30, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0x0E, 0x3E, 0x00, 0x00, -0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x47, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0xE1, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x22, 0x90, 0x83, 0xEC, 0xE0, 0xFF, 0xC3, -0x94, 0x04, 0x22, 0x90, 0x83, 0xEC, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x22, 0x7E, 0x00, 0x7F, 0x06, -0x12, 0x44, 0x1A, 0xEF, 0x22, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0x22, 0x90, 0x81, 0x3B, -0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x83, 0xC3, 0xE0, 0xFC, 0xA3, 0xE0, 0x22, 0xF0, 0x90, 0x81, -0x66, 0xE0, 0xFF, 0xC3, 0x22, 0x90, 0x81, 0x47, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x49, -0xE0, 0xC4, 0x54, 0x0F, 0x22, 0x7D, 0x01, 0x7F, 0x02, 0x02, 0x51, 0x51, 0x90, 0x81, 0x51, 0xE0, -0x90, 0x05, 0x73, 0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0x22, 0xC4, 0x11, -}; -u4Byte ArrayLength_MP_8188E_T_FW_WoWLAN = 15918; - -#endif - -void -ODM_ReadFirmware_MP_8188E_T_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_T_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_T_FW_WoWLAN, ArrayLength_MP_8188E_T_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8188E_T_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8188e/hal8188e_t_fw.h" +#endif + + +#if (RTL8188E_T_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_T_FW_AP[] = { +0xE1, 0x88, 0x20, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0xEC, 0x3A, 0x00, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x45, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xC3, 0x22, 0xEF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0xFE, 0xEF, +0x54, 0x07, 0xFF, 0x22, 0x90, 0x81, 0x6D, 0xE0, 0xFF, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x22, 0xF5, +0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x22, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E, +0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0x22, 0x00, 0x00, 0x66, +}; +u4Byte ArrayLength_MP_8188E_T_FW_AP = 15116; + +#endif + +void +ODM_ReadFirmware_MP_8188E_T_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_T_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_T_FW_AP, ArrayLength_MP_8188E_T_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_T_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_T_FW_NIC[] = { +0xE1, 0x88, 0x10, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0x94, 0x3A, 0x00, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x45, 0x9F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xC1, 0xC2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xC1, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0xFC, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x81, 0x87, 0xE0, 0x13, 0x13, 0x13, 0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, +0x22, 0x00, 0x7C, 0xBD, +}; +u4Byte ArrayLength_MP_8188E_T_FW_NIC = 15028; + + +#endif + +void +ODM_ReadFirmware_MP_8188E_T_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_T_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_T_FW_NIC, ArrayLength_MP_8188E_T_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_T_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_T_FW_NIC_89EM[] = { +0xE1, 0x88, 0x40, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0x40, 0x37, 0x00, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x45, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xC1, 0x97, 0x00, 0x00, 0x00, 0x00, 0x00, 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*pFirmwareSize = ArrayLength_MP_8188E_T_FW_NIC_89EM; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188E_T_FW_WoWLAN[] = { +0xE1, 0x88, 0x30, 0x00, 0x17, 0x00, 0x00, 0x00, 0x03, 0x25, 0x13, 0x14, 0x0E, 0x3E, 0x00, 0x00, +0x0C, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x47, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0xE1, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x50, 0x03, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x22, 0x90, 0x83, 0xEC, 0xE0, 0xFF, 0xC3, +0x94, 0x04, 0x22, 0x90, 0x83, 0xEC, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x22, 0x7E, 0x00, 0x7F, 0x06, +0x12, 0x44, 0x1A, 0xEF, 0x22, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0x22, 0x90, 0x81, 0x3B, +0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x83, 0xC3, 0xE0, 0xFC, 0xA3, 0xE0, 0x22, 0xF0, 0x90, 0x81, +0x66, 0xE0, 0xFF, 0xC3, 0x22, 0x90, 0x81, 0x47, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x81, 0x49, +0xE0, 0xC4, 0x54, 0x0F, 0x22, 0x7D, 0x01, 0x7F, 0x02, 0x02, 0x51, 0x51, 0x90, 0x81, 0x51, 0xE0, +0x90, 0x05, 0x73, 0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0x22, 0xC4, 0x11, +}; +u4Byte ArrayLength_MP_8188E_T_FW_WoWLAN = 15918; + +#endif + +void +ODM_ReadFirmware_MP_8188E_T_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188E_T_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188E_T_FW_WoWLAN, ArrayLength_MP_8188E_T_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8188E_T_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.h index 19d71f4e2a4..280057a3990 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halhwimg8188e_t_fw.h @@ -1,73 +1,73 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8188E_T_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8188E_T_H -#define __INC_MP_FW_HW_IMG_8188E_T_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_T_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_T_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC_89EM.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_T_FW_NIC_89EM( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188E_T_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8188E_T_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8188E_T_H +#define __INC_MP_FW_HW_IMG_8188E_T_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_T_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_T_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC_89EM.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_T_FW_NIC_89EM( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188E_T_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.c index 897f0db45d9..899011bffd7 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.c @@ -1,3146 +1,3146 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "../mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_88E 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8188E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A=0, ele_D, ele_C=0, /*TempCCk,*/ value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - //new element A = element D x X - if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - - if (RFPath == RF_PATH_A) - switch (RFPath) - { - case RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } - else - { - switch (RFPath) - { - case RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8188E(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8188E(Adapter, FALSE); -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr88E( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - if (Method == TXAGC) - { -// u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT]; -// u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; -// u1Byte rf = 0; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - #if (MP_DRIVER != 1) - PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - #else - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - #endif - -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); -#endif - - } - else if (Method == BBSWING) - { - // Adjust BB swing by OFDM IQ matrix - if (RFPath == RF_PATH_A) - { - setIqkMatrix_8188E(pDM_Odm, pDM_Odm->RFCalibrateInfo.BbSwingIdxOfdm[RF_PATH_A], RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - } - else if (RFPath == RF_PATH_B) - { - setIqkMatrix_8188E(pDM_Odm, pDM_Odm->RFCalibrateInfo.BbSwingIdxOfdm[RF_PATH_B], RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - } - /*Adjust BB swing by CCK filter coefficient*/ - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][7]); - } - } - else - { - return; - } - - - - -} // odm_TxPwrTrackSetPwr88E - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE_92D; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; - pConfig->RfPathCount = 1; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; - pConfig->DoIQK = DoIQK_8188E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#ifndef SMP_SYNC - unsigned long x; -#endif - struct rtl8192cd_priv *priv = pDM_Odm->priv; - SAVE_INT_AND_CLI(x); -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - //1 Tx IQK - //path-A IQK setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); - ODM_delay_ms(IQK_DELAY_TIME_88E); - SAVE_INT_AND_CLI(x); -#else - ODM_delay_ms(IQK_DELAY_TIME_88E); -#endif - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; -// else //if Tx not OK, ignore Rx -// return result; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); -#endif - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - - return result; - - - } - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#ifndef SMP_SYNC - unsigned long x; -#endif - struct rtl8192cd_priv *priv = pDM_Odm->priv; - SAVE_INT_AND_CLI(x); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); - ODM_delay_ms(IQK_DELAY_TIME_88E); - SAVE_INT_AND_CLI(x); -#else - ODM_delay_ms(IQK_DELAY_TIME_88E); -#endif - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else { //if Tx not OK, ignore Rx -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); -#endif - return result; - } - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); - ODM_delay_ms(IQK_DELAY_TIME_88E); - SAVE_INT_AND_CLI(x); -#else - ODM_delay_ms(IQK_DELAY_TIME_88E); -#endif - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - -#if 0 - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); -#endif - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); - regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); - regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID -_PHY_PathAFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if 0 // !(DM_ODM_SUPPORT_TYPE & ODM_WIN) //0824 -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; - if(FALSE == is2T){ - pathOn = 0x0bdb25a0; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -#else - BOOLEAN is2T = 0; -#endif - - if(is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte i; - u1Byte PathAOK, PathBOK; - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting - }; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifndef SMP_SYNC - unsigned long x; -#endif - struct rtl8192cd_priv *priv = pDM_Odm->priv; - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 9; -#else - const u4Byte retryCount = 2; -#endif -#endif - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif - SAVE_INT_AND_CLI(x); -#endif - - - if(t==0) - { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - // Save ADDA parameters, turn Path A ADDA on -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - - - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, TRUE); -#else - _PHY_PIModeSwitch(pDM_Odm, TRUE); -#endif - } - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (ODM_GetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskDWord))) ); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - //Page B init - //AP or IQK - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } - - // IQ calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); -#endif - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); -#else - PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); -#endif -// if(PathAOK == 0x03){ - if(PathAOK == 0x01){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } -#if 0 - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK(pAdapter, is2T); -#else - PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); -#endif - if(PathAOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - SAVE_INT_AND_CLI(x); -#endif - - if(0x00 == PathAOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } - - if(is2T){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy(pAdapter); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); -#else - _PHY_PathAStandBy(pDM_Odm); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8188E(pAdapter); -#else - PathBOK = phy_PathB_IQK_8188E(pDM_Odm); -#endif - if(PathBOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - if(t!=0) - { - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, FALSE); -#else - _PHY_PIModeSwitch(pDM_Odm, FALSE); -#endif - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if(is2T){ - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - RESTORE_INT(x); -#endif - -} - - -VOID -phy_LCCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#ifndef SMP_SYNC - unsigned long x; -#endif - struct rtl8192cd_priv *priv = pDM_Odm->priv; - SAVE_INT_AND_CLI(x); -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ;// ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask20Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask20Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask20Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask20Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask20Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask20Bits, LC_Cal|0x08000); - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - RESTORE_INT(x); - ODM_delay_ms(100); - SAVE_INT_AND_CLI(x); -#else - ODM_delay_ms(100); -#endif - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - //ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask20Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - RESTORE_INT(x); -#endif -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - else if(path == RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - if(path == RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); - if(path == RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == RF_PATH_A) - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - -VOID -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; -// u1Byte channelToIQK = 7; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN /*bStartContTx = FALSE,*/ bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else -#ifndef SMP_SYNC - unsigned long x; -#endif - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; - -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if MP_DRIVER == 1 -// bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - -#ifdef DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(bReCovery) -#else//for ODM_WIN - if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - return; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - priv->pshare->IQK_total_cnt++; -#if 0//Suggested by Edlu,120413 - - // IQK on channel 7, should switch back when completed. - //originChannel = pHalData->CurrentChannel; - originChannel = *(pDM_Odm->pChannel); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK); -#endif - -#endif - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i=0; i<3; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)) - { - phy_IQCalibrate_8188E(pAdapter, result, i, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); -#else - phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); -#endif - } - - if(i == 1) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); -#endif - if(is12simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if(i == 2) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); -#endif - if(is13simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); -#endif - if(is23simular) - { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); - } - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - SAVE_INT_AND_CLI(x); -#endif - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - priv->pshare->IQK_fail_cnt++; - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#else - _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#endif - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) - { - _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - } - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if(final_candidate < 4) - { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); -#if 0 //Suggested by Edlu,120413 - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel); - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel); - #endif - -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - RESTORE_INT(x); -#endif - -} - - -VOID -PHY_LCCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - BOOLEAN /*bStartContTx = FALSE,*/ bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - - - - -#if MP_DRIVER == 1 -// bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#ifdef DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_2T2R(pHalData->VersionID)) - { - phy_LCCalibrate_8188E(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8188E(pAdapter, FALSE); -#else - phy_LCCalibrate_8188E(pDM_Odm, FALSE); -#endif - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - -#if 0 -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8188E(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8188E(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); -#endif - } -#endif -} -VOID phy_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(!pAdapter->bHWInitReady) - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pAdapter->hw_init_completed == _FALSE) - #endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - -#endif - - if(is2T) //92C - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else //88C - { - - // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), - // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); - ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table - - if(bMain) - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna - - } - else - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna - } - - } -} -VOID PHY_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#endif - -#ifdef DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); -#else - phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); -#endif - } -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8188E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - - return; - - if(pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_DigitalPredistortion(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - if(!pAdapter->bHWInitReady) - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) // - { - if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return TRUE; - else - return FALSE; - } - else - { - if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#ifdef DISABLE_BB_RF - return TRUE; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - //if(IS_92C_SERIAL( pHalData->VersionID)){ - if(IS_2T2R( pHalData->VersionID)){ - return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); -#endif - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8188E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A=0, ele_D, ele_C=0, /*TempCCk,*/ value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + //new element A = element D x X + if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + + if (RFPath == RF_PATH_A) + switch (RFPath) + { + case RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } + else + { + switch (RFPath) + { + case RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8188E(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8188E(Adapter, FALSE); +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr88E( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + if (Method == TXAGC) + { +// u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT]; +// u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; +// u1Byte rf = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + #if (MP_DRIVER != 1) + PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + #else + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + #endif + +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + + } + else if (Method == BBSWING) + { + // Adjust BB swing by OFDM IQ matrix + if (RFPath == RF_PATH_A) + { + setIqkMatrix_8188E(pDM_Odm, pDM_Odm->RFCalibrateInfo.BbSwingIdxOfdm[RF_PATH_A], RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + } + else if (RFPath == RF_PATH_B) + { + setIqkMatrix_8188E(pDM_Odm, pDM_Odm->RFCalibrateInfo.BbSwingIdxOfdm[RF_PATH_B], RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + } + /*Adjust BB swing by CCK filter coefficient*/ + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[pDM_Odm->RFCalibrateInfo.BbSwingIdxCck][7]); + } + } + else + { + return; + } + + + + +} // odm_TxPwrTrackSetPwr88E + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE_92D; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; + pConfig->RfPathCount = 1; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; + pConfig->DoIQK = DoIQK_8188E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = pDM_Odm->priv; + SAVE_INT_AND_CLI(x); +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //1 Tx IQK + //path-A IQK setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); + ODM_delay_ms(IQK_DELAY_TIME_88E); + SAVE_INT_AND_CLI(x); +#else + ODM_delay_ms(IQK_DELAY_TIME_88E); +#endif + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; +// else //if Tx not OK, ignore Rx +// return result; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); +#endif + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + + return result; + + + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = pDM_Odm->priv; + SAVE_INT_AND_CLI(x); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); + ODM_delay_ms(IQK_DELAY_TIME_88E); + SAVE_INT_AND_CLI(x); +#else + ODM_delay_ms(IQK_DELAY_TIME_88E); +#endif + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else { //if Tx not OK, ignore Rx +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); +#endif + return result; + } + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); + ODM_delay_ms(IQK_DELAY_TIME_88E); + SAVE_INT_AND_CLI(x); +#else + ODM_delay_ms(IQK_DELAY_TIME_88E); +#endif + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + +#if 0 + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); +#endif + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); + regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); + regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +_PHY_PathAFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if 0 // !(DM_ODM_SUPPORT_TYPE & ODM_WIN) //0824 +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; + if(FALSE == is2T){ + pathOn = 0x0bdb25a0; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +#else + BOOLEAN is2T = 0; +#endif + + if(is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting + }; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = pDM_Odm->priv; + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 9; +#else + const u4Byte retryCount = 2; +#endif +#endif + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif + SAVE_INT_AND_CLI(x); +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, TRUE); +#else + _PHY_PIModeSwitch(pDM_Odm, TRUE); +#endif + } + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (ODM_GetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskDWord))) ); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); +#endif + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); +#else + PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK(pAdapter, is2T); +#else + PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); +#endif + if(PathAOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + SAVE_INT_AND_CLI(x); +#endif + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } + + if(is2T){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8188E(pAdapter); +#else + PathBOK = phy_PathB_IQK_8188E(pDM_Odm); +#endif + if(PathBOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + if(t!=0) + { + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, FALSE); +#else + _PHY_PIModeSwitch(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if(is2T){ + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + RESTORE_INT(x); +#endif + +} + + +VOID +phy_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = pDM_Odm->priv; + SAVE_INT_AND_CLI(x); +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ;// ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask20Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask20Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask20Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask20Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask20Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask20Bits, LC_Cal|0x08000); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + RESTORE_INT(x); + ODM_delay_ms(100); + SAVE_INT_AND_CLI(x); +#else + ODM_delay_ms(100); +#endif + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + //ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask20Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask20Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + RESTORE_INT(x); +#endif +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + if(path == RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); + if(path == RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + +VOID +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; +// u1Byte channelToIQK = 7; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN /*bStartContTx = FALSE,*/ bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else +#ifndef SMP_SYNC + unsigned long x; +#endif + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if MP_DRIVER == 1 +// bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + +#ifdef DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_WIN + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + priv->pshare->IQK_total_cnt++; +#if 0//Suggested by Edlu,120413 + + // IQK on channel 7, should switch back when completed. + //originChannel = pHalData->CurrentChannel; + originChannel = *(pDM_Odm->pChannel); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK); +#endif + +#endif + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i=0; i<3; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)) + { + phy_IQCalibrate_8188E(pAdapter, result, i, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); +#else + phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); +#endif + } + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + SAVE_INT_AND_CLI(x); +#endif + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + priv->pshare->IQK_fail_cnt++; + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); +#if 0 //Suggested by Edlu,120413 + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel); + #endif + +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + RESTORE_INT(x); +#endif + +} + + +VOID +PHY_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + BOOLEAN /*bStartContTx = FALSE,*/ bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + + + +#if MP_DRIVER == 1 +// bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#ifdef DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_2T2R(pHalData->VersionID)) + { + phy_LCCalibrate_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8188E(pAdapter, FALSE); +#else + phy_LCCalibrate_8188E(pDM_Odm, FALSE); +#endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + +#if 0 +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8188E(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8188E(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); +#endif + } +#endif +} +VOID phy_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(!pAdapter->bHWInitReady) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pAdapter->hw_init_completed == _FALSE) + #endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), + // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); + ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table + + if(bMain) + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna + + } + else + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna + } + + } +} +VOID PHY_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#endif + +#ifdef DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); +#endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8188E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_DigitalPredistortion(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#ifdef DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + //if(IS_92C_SERIAL( pHalData->VersionID)){ + if(IS_2T2R( pHalData->VersionID)){ + return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); +#endif + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.h index 2f05e22b87b..e0ee84151fe 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ap.h @@ -1,136 +1,136 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8188E_H__ -#define __HAL_PHY_RF_8188E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_88E 10 //ms -#define index_mapping_NUM_88E 15 -#define AVG_THERMAL_NUM_88E 4 - -#include "../halphyrf_ap.h" - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr88E( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ); - - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8188E_H__ +#define __HAL_PHY_RF_8188E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_88E 10 //ms +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 + +#include "../halphyrf_ap.h" + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr88E( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.c index 6dcc20cb4d4..53d1204720a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.c @@ -1,3323 +1,3323 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_88E 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8188E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A=0, ele_D, ele_C=0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - //new element A = element D x X - if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - - //if (RFPath == ODM_RF_PATH_A) - switch (RFPath) - { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } - else - { - switch (RFPath) - { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8188E(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8188E(Adapter, FALSE); -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr88E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 30; //+0dB - u1Byte PwrTrackingLimit_CCK= 28; //-2dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8188E\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = 28; //-2dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM= 36; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit_OFDM= 34; //+2dB - - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit_OFDM= 38; //+4dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit_OFDM= 36; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit_OFDM= 34; //+2dB - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) - { - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*Remnant index equal to aboslute compensate value.*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - if (pDM_Odm->mp_mode == TRUE) - { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); - //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RF_PATH_A]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } - else - { - //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - if (RFPath == ODM_RF_PATH_A) - { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - } - } - - -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); -#endif - - } - else if (Method == BBSWING) - { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index <= 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) - Final_CCK_Swing_Index = 0; - - // Adjust BB swing by OFDM IQ matrix - if (RFPath == ODM_RF_PATH_A) - { - setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - // Adjust BB swing by CCK filter coefficient - if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){ - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - } - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index <= 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - - if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - // Adjust BB swing by CCK filter coefficient - - if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - - } - else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0 - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); - - if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); - } - } - } - else - { - return; - } -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8188E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - -} - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; - pConfig->RfPathCount = MAX_PATH_NUM_8188E; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; - pConfig->DoIQK = DoIQK_8188E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - //1 Tx IQK - //path-A IQK setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - - return result; - - - } - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - -#if 0 - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); - regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); - regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID -_PHY_PathAFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop: %s /%d/%d\n", - rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; - if(FALSE == is2T){ - pathOn = 0x0bdb25a0; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); -} - -VOID -_PHY_PIModeSwitch( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - BOOLEAN is2T = IS_2T2R( pHalData->VersionID); -#else - BOOLEAN is2T = 0; -#endif - - if(is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte i; - u1Byte PathAOK=0, PathBOK=0; - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - - u4Byte retryCount = 2; - - if (pDM_Odm->mp_mode == TRUE) - retryCount = 9; - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if(t==0) - { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - // Save ADDA parameters, turn Path A ADDA on -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - - - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, TRUE); -#else - _PHY_PIModeSwitch(pDM_Odm, TRUE); -#endif - } - - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - //Page B init - //AP or IQK - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } - - // IQ calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); -#else - PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); -#endif -// if(PathAOK == 0x03){ - if(PathAOK == 0x01){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } -#if 0 - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK(pAdapter, is2T); -#else - PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); -#endif - if(PathAOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - - if(0x00 == PathAOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } - - if(is2T){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy(pAdapter); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); -#else - _PHY_PathAStandBy(pDM_Odm); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8188E(pAdapter); -#else - PathBOK = phy_PathB_IQK_8188E(pDM_Odm); -#endif - if(PathBOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); - - if(t!=0) - { - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, FALSE); -#else - _PHY_PIModeSwitch(pDM_Odm, FALSE); -#endif - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if(is2T){ - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); - -} - - -VOID -phy_LCCalibrate_8188E( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - - if (pDM_Odm->mp_mode == TRUE) - { - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - } -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -//#if MP_DRIVER != 1 - if (pDM_Odm->mp_mode == FALSE) - return; -//#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == ODM_RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - } - else if(path == ODM_RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#endif - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == ODM_RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - if(path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if(path == ODM_RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - u1Byte channelToIQK = 7; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - u4Byte StartTime; - s4Byte ProgressingTime; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; - -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if MP_DRIVER == 1 - if (pDM_Odm->mp_mode == TRUE) - { - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - } -#endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - -#if DISABLE_BB_RF - return; -#endif - - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) -#else//for ODM_WIN - if (bReCovery && (!pAdapter->bInHctTest)) /* YJ,add for PowerTest,120405 */ -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - return; - } - - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - - - StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - - - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i=0; i<3; i++) - { - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); -#else - phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); -#endif - } - - if(i == 1) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); -#endif - if(is12simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if(i == 2) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); -#endif - if(is13simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); -#endif - if(is23simular) - { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); - } - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#else - _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#endif - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if(final_candidate < 4) - { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); - -} - - -VOID -PHY_LCCalibrate_8188E( - PVOID pDM_VOID - ) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - u4Byte StartTime; - s4Byte ProgressingTime; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - -#if MP_DRIVER == 1 - if (pDM_Odm->mp_mode == TRUE) - { - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - } -#endif - - -#if DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - StartTime = ODM_GetCurrentTime( pDM_Odm); - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); - phy_LCCalibrate_8188E(pDM_Odm, FALSE); - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); -} - -#if 0 -VOID -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - -#if 0 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8188E(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); -#endif - } -#endif -} -#endif - -VOID phy_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(!pAdapter->bHWInitReady) - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!rtw_is_hw_init_completed(pAdapter)) - #endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - -#endif - - if(is2T) //92C - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else //88C - { - - // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), - // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); - ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table - - if(bMain) - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna - - } - else - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna - } - - } -} -VOID PHY_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#endif - -#if DISABLE_BB_RF - return; -#endif - - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); -#else - phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); -#endif - } -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8188E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; - - if(pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(pDM_Odm->RFType == ODM_2T2R){ - phy_DigitalPredistortion(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - if(!pAdapter->bHWInitReady) - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) // - { - if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return TRUE; - else - return FALSE; - } - else - { - if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return TRUE; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_2T2R( pHalData->VersionID)){ - return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); -#endif - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8188E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A=0, ele_D, ele_C=0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + //new element A = element D x X + if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + + //if (RFPath == ODM_RF_PATH_A) + switch (RFPath) + { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } + else + { + switch (RFPath) + { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8188E(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8188E(Adapter, FALSE); +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr88E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 30; //+0dB + u1Byte PwrTrackingLimit_CCK= 28; //-2dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8188E\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = 28; //-2dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM= 36; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit_OFDM= 34; //+2dB + + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM= 38; //+4dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM= 36; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM= 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) + { + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*Remnant index equal to aboslute compensate value.*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + if (pDM_Odm->mp_mode == TRUE) + { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); + //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RF_PATH_A]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } + else + { + //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + if (RFPath == ODM_RF_PATH_A) + { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + } + } + + +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + + } + else if (Method == BBSWING) + { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index <= 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) + Final_CCK_Swing_Index = 0; + + // Adjust BB swing by OFDM IQ matrix + if (RFPath == ODM_RF_PATH_A) + { + setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + // Adjust BB swing by CCK filter coefficient + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){ + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + } + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index <= 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + + if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + // Adjust BB swing by CCK filter coefficient + + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + + } + else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0 + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); + } + } + } + else + { + return; + } +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8188E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + +} + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; + pConfig->RfPathCount = MAX_PATH_NUM_8188E; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; + pConfig->DoIQK = DoIQK_8188E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //1 Tx IQK + //path-A IQK setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + + return result; + + + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + +#if 0 + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); + regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); + regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +_PHY_PathAFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop: %s /%d/%d\n", + rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; + if(FALSE == is2T){ + pathOn = 0x0bdb25a0; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); +} + +VOID +_PHY_PIModeSwitch( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + BOOLEAN is2T = IS_2T2R( pHalData->VersionID); +#else + BOOLEAN is2T = 0; +#endif + + if(is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathAOK=0, PathBOK=0; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + + u4Byte retryCount = 2; + + if (pDM_Odm->mp_mode == TRUE) + retryCount = 9; + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, TRUE); +#else + _PHY_PIModeSwitch(pDM_Odm, TRUE); +#endif + } + + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T); +#else + PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK(pAdapter, is2T); +#else + PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); +#endif + if(PathAOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } + + if(is2T){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8188E(pAdapter); +#else + PathBOK = phy_PathB_IQK_8188E(pDM_Odm); +#endif + if(PathBOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + + if(t!=0) + { + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, FALSE); +#else + _PHY_PIModeSwitch(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if(is2T){ + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8188E( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + + if (pDM_Odm->mp_mode == TRUE) + { + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +//#if MP_DRIVER != 1 + if (pDM_Odm->mp_mode == FALSE) + return; +//#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == ODM_RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } + else if(path == ODM_RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == ODM_RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + if(path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if(path == ODM_RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + u1Byte channelToIQK = 7; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + u4Byte StartTime; + s4Byte ProgressingTime; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if MP_DRIVER == 1 + if (pDM_Odm->mp_mode == TRUE) + { + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + } +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) +#else//for ODM_WIN + if (bReCovery && (!pAdapter->bInHctTest)) /* YJ,add for PowerTest,120405 */ +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + + + StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + + + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i=0; i<3; i++) + { + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); +#else + phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); +#endif + } + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); + +} + + +VOID +PHY_LCCalibrate_8188E( + PVOID pDM_VOID + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + u4Byte StartTime; + s4Byte ProgressingTime; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + +#if MP_DRIVER == 1 + if (pDM_Odm->mp_mode == TRUE) + { + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + } +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + StartTime = ODM_GetCurrentTime( pDM_Odm); + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + phy_LCCalibrate_8188E(pDM_Odm, FALSE); + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); +} + +#if 0 +VOID +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + +#if 0 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8188E(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); +#endif + } +#endif +} +#endif + +VOID phy_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(!pAdapter->bHWInitReady) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!rtw_is_hw_init_completed(pAdapter)) + #endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), + // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); + ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table + + if(bMain) + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna + + } + else + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna + } + + } +} +VOID PHY_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#endif + +#if DISABLE_BB_RF + return; +#endif + + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); +#endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8188E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(pDM_Odm->RFType == ODM_2T2R){ + phy_DigitalPredistortion(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_2T2R( pHalData->VersionID)){ + return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); +#endif + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.h index 9376cfecbc1..c4befba5af3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_ce.h @@ -1,143 +1,143 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8188E_H__ -#define __HAL_PHY_RF_8188E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_88E 10 //ms -#define index_mapping_NUM_88E 15 -#define AVG_THERMAL_NUM_88E 4 - -#include "../halphyrf_ce.h" - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8188E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr88E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8188E( - IN PVOID pDM_VOID -); -#if 0 -// -// AP calibrate -// -void -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -#endif - -void -PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ); - - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8188E_H__ +#define __HAL_PHY_RF_8188E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_88E 10 //ms +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 + +#include "../halphyrf_ce.h" + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8188E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr88E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188E( + IN PVOID pDM_VOID +); +#if 0 +// +// AP calibrate +// +void +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +#endif + +void +PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.c b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.c index 46b0da3a010..bb87806780d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.c @@ -1,3371 +1,3371 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_88E 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8188E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A=0, ele_D, ele_C=0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - //new element A = element D x X - if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - - if (RFPath == ODM_RF_PATH_A) - switch (RFPath) - { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } - else - { - switch (RFPath) - { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8188E(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8188E(Adapter, FALSE); -#endif - -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr88E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 30; //+0dB - u1Byte PwrTrackingLimit_CCK= 28; //-2dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8188E\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = 28; //-2dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM= 36; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit_OFDM= 34; //+2dB - - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit_OFDM= 38; //+4dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit_OFDM= 36; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit_OFDM= 34; //+2dB - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) - { - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - #if (MP_DRIVER != 1) - //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - if (RFPath == ODM_RF_PATH_A) - { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - } - - #else - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - #endif - -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); -#endif - - } - else if (Method == BBSWING) - { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck < 0) - Final_CCK_Swing_Index = 0; - - // Adjust BB swing by OFDM IQ matrix - if (RFPath == ODM_RF_PATH_A) - { - setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - // Adjust BB swing by CCK filter coefficient - if(!pRFCalibrateInfo->bCCKinCH14){ - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - } - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index < 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - - if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - // Adjust BB swing by CCK filter coefficient - - if(!pRFCalibrateInfo->bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - - } - else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0 - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - if(!pRFCalibrateInfo->bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); - - if(!pRFCalibrateInfo->bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK= FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); - } - - } - } - else - { - return; - } -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8188E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - } - } - else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } -} - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; - pConfig->RfPathCount = MAX_PATH_NUM_8188E; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; - pConfig->DoIQK = DoIQK_8188E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB, - IN u4Byte Ktimes - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - //1 Tx IQK - //path-A IQK setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - if (Ktimes == 0x0) - { - //LO calibration on - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - } - else - { - //LO calibration off - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - } - - //TX IQK mode setting - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f7f ); - - //PA,PAD gain adjust - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510f0 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - if (Ktimes == 0) - { - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E*2); - - } - else - { - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - } - - //reload RF 0xdf - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); - - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - - return result; - - - } - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117b ); - - //PA,PAD gain adjust - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510f0 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160fff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - //reload RF 0xdf - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); - - //PA,PAD gain adjust - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160fff); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - //reload RF 0xdf - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - -#if 0 - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_88E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); - regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); - regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID -_PHY_PathAFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; - if(FALSE == is2T){ - pathOn = 0x0bdb25a0; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -#else - BOOLEAN is2T = 0; -#endif - - if(is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte i; - u1Byte PathAOK, PathBOK; - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 2; -#else - const u4Byte retryCount = 2; -#endif -#endif - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if(t==0) - { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - // Save ADDA parameters, turn Path A ADDA on -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - - - if(t==0) - { - pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pRFCalibrateInfo->bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, TRUE); -#else - _PHY_PIModeSwitch(pDM_Odm, TRUE); -#endif - } - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); -#endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - - - - //Page B init - //AP or IQK - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } - - // IQ calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T, t + i); -#else - PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T, t + i); -#endif -// if(PathAOK == 0x03){ - if(PathAOK == 0x01){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } -#if 0 - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK(pAdapter, is2T); -#else - PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); -#endif - if(PathAOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - - if(0x00 == PathAOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } - - if(is2T){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy(pAdapter); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); -#else - _PHY_PathAStandBy(pDM_Odm); - - // Turn Path B ADDA on - _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8188E(pAdapter); -#else - PathBOK = phy_PathB_IQK_8188E(pDM_Odm); -#endif - if(PathBOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if(t!=0) - { - if(!pRFCalibrateInfo->bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch(pAdapter, FALSE); -#else - _PHY_PIModeSwitch(pDM_Odm, FALSE); -#endif - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#else - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if(is2T){ - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); - -} - - -VOID -phy_LCCalibrate_8188E( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == ODM_RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - else if(path == ODM_RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#endif - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == ODM_RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pRFCalibrateInfo->bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if(path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if(path == ODM_RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pRFCalibrateInfo->bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ) -{ - -//20131031 -//V2.0 -//fine tune TXIQK/RXIQK loop gain for SMIC. -//LOK only perform 1 time. -//IQK retry count 10-->2 - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; - -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if MP_DRIVER == 1 - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - -#if DISABLE_BB_RF - return; -#endif - - if (pRFCalibrateInfo->bIQKInProgress) - return; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(bReCovery) -#else//for ODM_WIN - if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#endif - return; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i=0; i<3; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)) - { - phy_IQCalibrate_8188E(pAdapter, result, i, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); -#else - phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); -#endif - } - - if(i == 1) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); -#endif - if(is12simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if(i == 2) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); -#endif - if(is13simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); -#endif - if(is23simular) - { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); - } - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; - pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; - pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value - pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#else - _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#endif - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) - { - _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - } - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if(final_candidate < 4) - { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - -} - - -VOID -PHY_LCCalibrate_8188E( - PVOID pDM_VOID - ) -{ - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if MP_DRIVER == 1 - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#if DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pRFCalibrateInfo->bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); - phy_LCCalibrate_8188E(pDM_Odm, FALSE); - - pRFCalibrateInfo->bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pRFCalibrateInfo->bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8188E(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8188E(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); -#endif - } -} -VOID phy_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(!pAdapter->bHWInitReady) - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pAdapter->hw_init_completed == _FALSE) - #endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - -#endif - - if(is2T) //92C - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else //88C - { - - // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), - // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); - ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table - - if(bMain) - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna - - } - else - { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna - } - - } -} -VOID PHY_SetRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#endif - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); -#else - phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); -#endif - } -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pRFCalibrateInfo->bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pRFCalibrateInfo->bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pRFCalibrateInfo->bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pRFCalibrateInfo->bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexbDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8188E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if DISABLE_BB_RF - return; -#endif - - return; - - if(pRFCalibrateInfo->bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_DigitalPredistortion(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - if(!pAdapter->bHWInitReady) - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) // - { - if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return TRUE; - else - return FALSE; - } - else - { - if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return TRUE; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - //if(IS_92C_SERIAL( pHalData->VersionID)){ - if(IS_2T2R( pHalData->VersionID)){ - return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); -#endif - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8188E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A=0, ele_D, ele_C=0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + //new element A = element D x X + if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + + if (RFPath == ODM_RF_PATH_A) + switch (RFPath) + { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } + else + { + switch (RFPath) + { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8188E(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8188E(Adapter, FALSE); +#endif + +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr88E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 30; //+0dB + u1Byte PwrTrackingLimit_CCK= 28; //-2dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8188E\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = 28; //-2dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM= 36; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit_OFDM= 34; //+2dB + + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM= 38; //+4dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM= 36; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM= 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) + { + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + #if (MP_DRIVER != 1) + //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + if (RFPath == ODM_RF_PATH_A) + { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + } + + #else + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + #endif + +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + + } + else if (Method == BBSWING) + { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + // Adjust BB swing by OFDM IQ matrix + if (RFPath == ODM_RF_PATH_A) + { + setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + // Adjust BB swing by CCK filter coefficient + if(!pRFCalibrateInfo->bCCKinCH14){ + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + } + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + + if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + // Adjust BB swing by CCK filter coefficient + + if(!pRFCalibrateInfo->bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + + } + else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0 + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + if(!pRFCalibrateInfo->bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + + if(!pRFCalibrateInfo->bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK= FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); + } + + } + } + else + { + return; + } +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8188E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + } + } + else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } +} + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E; + pConfig->RfPathCount = MAX_PATH_NUM_8188E; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E; + pConfig->DoIQK = DoIQK_8188E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB, + IN u4Byte Ktimes + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //1 Tx IQK + //path-A IQK setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + if (Ktimes == 0x0) + { + //LO calibration on + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + } + else + { + //LO calibration off + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + } + + //TX IQK mode setting + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f7f ); + + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510f0 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + if (Ktimes == 0) + { + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E*2); + + } + else + { + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + } + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); + + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + + return result; + + + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117b ); + + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510f0 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160fff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); + + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160fff); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + +#if 0 + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_88E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); + regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); + regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +_PHY_PathAFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; + if(FALSE == is2T){ + pathOn = 0x0bdb25a0; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +#else + BOOLEAN is2T = 0; +#endif + + if(is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 2; +#else + const u4Byte retryCount = 2; +#endif +#endif + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + + if(t==0) + { + pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pRFCalibrateInfo->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, TRUE); +#else + _PHY_PIModeSwitch(pDM_Odm, TRUE); +#endif + } + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); +#endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + + + + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T, t + i); +#else + PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T, t + i); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK(pAdapter, is2T); +#else + PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T); +#endif + if(PathAOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } + + if(is2T){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8188E(pAdapter); +#else + PathBOK = phy_PathB_IQK_8188E(pDM_Odm); +#endif + if(PathBOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if(t!=0) + { + if(!pRFCalibrateInfo->bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch(pAdapter, FALSE); +#else + _PHY_PIModeSwitch(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if(is2T){ + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8188E( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == ODM_RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + else if(path == ODM_RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == ODM_RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pRFCalibrateInfo->bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if(path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if(path == ODM_RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pRFCalibrateInfo->bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ + +//20131031 +//V2.0 +//fine tune TXIQK/RXIQK loop gain for SMIC. +//LOK only perform 1 time. +//IQK retry count 10-->2 + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if MP_DRIVER == 1 + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + + if (pRFCalibrateInfo->bIQKInProgress) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_WIN + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#endif + return; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i=0; i<3; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)) + { + phy_IQCalibrate_8188E(pAdapter, result, i, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8188E(pAdapter, result, i, FALSE); +#else + phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE); +#endif + } + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; + pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; + pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value + pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + +} + + +VOID +PHY_LCCalibrate_8188E( + PVOID pDM_VOID + ) +{ + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if MP_DRIVER == 1 + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pRFCalibrateInfo->bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + phy_LCCalibrate_8188E(pDM_Odm, FALSE); + + pRFCalibrateInfo->bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pRFCalibrateInfo->bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8188E(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8188E(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8188E(pDM_Odm, delta, FALSE); +#endif + } +} +VOID phy_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(!pAdapter->bHWInitReady) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pAdapter->hw_init_completed == _FALSE) + #endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), + // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0); + ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table + + if(bMain) + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna + + } + else + { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna + } + + } +} +VOID PHY_SetRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#endif + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE); +#endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pRFCalibrateInfo->bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pRFCalibrateInfo->bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pRFCalibrateInfo->bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pRFCalibrateInfo->bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexbDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8188E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pRFCalibrateInfo->bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_DigitalPredistortion(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + //if(IS_92C_SERIAL( pHalData->VersionID)){ + if(IS_2T2R( pHalData->VersionID)){ + return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE); +#endif + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.h b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.h index e93f6cc20ef..74dfb113c12 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/halphyrf_8188e_win.h @@ -1,144 +1,144 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8188E_H__ -#define __HAL_PHY_RF_8188E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_88E 15 //ms -#define IQK_DELAY_TIME_8723B 10 //ms - -#define index_mapping_NUM_88E 15 -#define AVG_THERMAL_NUM_88E 4 - -#include "halphyrf_win.h" - -void ConfigureTxpowerTrack_8188E( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8188E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -void DoIQK_8188E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr88E( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8188E( - PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8188E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); - -#define PHY_DPCalibrate_8821A PHY_DPCalibrate_8812A - -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ); - - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8188E_H__ +#define __HAL_PHY_RF_8188E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_88E 15 //ms +#define IQK_DELAY_TIME_8723B 10 //ms + +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 + +#include "halphyrf_win.h" + +void ConfigureTxpowerTrack_8188E( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8188E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +void DoIQK_8188E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr88E( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188E( + PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8188E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter); + +#define PHY_DPCalibrate_8821A PHY_DPCalibrate_8812A + +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.c b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.c index 0bbd3e73983..2d020f713f3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.c @@ -1,245 +1,245 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" - -#include "../phydm_precomp.h" - -#if (RTL8188E_SUPPORT == 1) - -void -odm_ConfigRFReg_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifndef SMP_SYNC - unsigned long x; -#endif - struct rtl8192cd_priv *priv = pDM_Odm->priv; -#endif - - if(Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else if (Addr == 0xfd) - { - ODM_delay_ms(5); - } - else if (Addr == 0xfc) - { - ODM_delay_ms(1); - } - else if (Addr == 0xfb) - { - ODM_delay_us(50); - } - else if (Addr == 0xfa) - { - ODM_delay_us(5); - } - else if (Addr == 0xf9) - { - ODM_delay_us(1); - } - else - { - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - SAVE_INT_AND_CLI(x); - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - RESTORE_INT(x); -#else - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); -#endif - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } -} - - -void -odm_ConfigRF_RadioA_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe){ - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else if (Addr == 0xfd){ - ODM_delay_ms(5); - } - else if (Addr == 0xfc){ - ODM_delay_ms(1); - } - else if (Addr == 0xfb){ - ODM_delay_us(50); - } - else if (Addr == 0xfa){ - ODM_delay_us(5); - } - else if (Addr == 0xf9){ - ODM_delay_us(1); - } - else { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); - - #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); - #endif - } -} - -void -odm_ConfigBB_TXPWR_LMT_8188E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -void -odm_ConfigBB_PHY_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe){ - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else if (Addr == 0xfd){ - ODM_delay_ms(5); - } - else if (Addr == 0xfc){ - ODM_delay_ms(1); - } - else if (Addr == 0xfb){ - ODM_delay_us(50); - } - else if (Addr == 0xfa){ - ODM_delay_us(5); - } - else if (Addr == 0xf9){ - ODM_delay_us(1); - } - else { - if (Addr == 0xa24) - pDM_Odm->RFCalibrateInfo.RegA24 = Data; - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = pDM_Odm->priv; +#endif + + if(Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd) + { + ODM_delay_ms(5); + } + else if (Addr == 0xfc) + { + ODM_delay_ms(1); + } + else if (Addr == 0xfb) + { + ODM_delay_us(50); + } + else if (Addr == 0xfa) + { + ODM_delay_us(5); + } + else if (Addr == 0xf9) + { + ODM_delay_us(1); + } + else + { + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + SAVE_INT_AND_CLI(x); + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + RESTORE_INT(x); +#else + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); +#endif + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); + + #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); + #endif + } +} + +void +odm_ConfigBB_TXPWR_LMT_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else { + if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.h b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.h index 2cce339b567..999c77263f1 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_regconfig8188e.h @@ -1,96 +1,96 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8188E -#define __INC_ODM_REGCONFIG_H_8188E - -#if (RTL8188E_SUPPORT == 1) - -void -odm_ConfigRFReg_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8188E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8188E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188E +#define __INC_ODM_REGCONFIG_H_8188E + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.c b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.c index c4c2fcfe364..f5065e7dfa4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.c @@ -1,460 +1,460 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" - -#include "../phydm_precomp.h" - -#if (RTL8188E_SUPPORT == 1) - -VOID -ODM_DIG_LowerBound_88E( - IN PDM_ODM_T pDM_Odm -) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - { - pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); - } - //If only one Entry connected -} - -/*============================================================= -* AntDiv Before Link -===============================================================*/ -VOID -ODM_SwAntDivResetBeforeLink( - IN PDM_ODM_T pDM_Odm - ) -{ - - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - pDM_SWAT_Table->SWAS_NoLink_State = 0; - -} - - -//3============================================================ -//3 Dynamic Primary CCA -//3============================================================ - -VOID -ODM_PrimaryCCA_Init( - IN PDM_ODM_T pDM_Odm) -{ - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->Monitor_flag = 0; - PrimaryCCA->PriCCA_flag = 0; -} - -BOOLEAN -ODM_DynamicPrimaryCCA_DupRTS( - IN PDM_ODM_T pDM_Odm - ) -{ - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - return PrimaryCCA->DupRTS_flag; -} - -VOID -ODM_DynamicPrimaryCCA( - IN PDM_ODM_T pDM_Odm - ) -{ - -#if(DM_ODM_SUPPORT_TYPE !=ODM_CE) - - PADAPTER Adapter = pDM_Odm->Adapter; // for NIC - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PRT_WLAN_STA pEntry; -#endif - - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - BOOLEAN Is40MHz; - BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW - BOOLEAN bConnected = FALSE; // connected or not - static u1Byte Client_40MHz_pre = 0; - static u8Byte lastTxOkCnt = 0; - static u8Byte lastRxOkCnt = 0; - static u4Byte Counter = 0; - static u1Byte Delay = 1; - u8Byte curTxOkCnt; - u8Byte curRxOkCnt; - u1Byte SecCHOffset; - u1Byte i; - - if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)) - return; - - if(pDM_Odm->SupportICType != ODM_RTL8188E) - return; - - Is40MHz = *(pDM_Odm->pBandWidth); - SecCHOffset = *(pDM_Odm->pSecChOffset); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(Is40MHz==1) - SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); - //3 Check Current WLAN Traffic - curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; - curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; - lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; - lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - //3 Check Current WLAN Traffic - curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; - curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; - lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); - lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); -#endif - - //==================Debug Message==================== - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail)); - //================================================ - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode -#endif - { - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter))); - //3 To get entry's connection and BW infomation status. - for(i=0;iBandWidth; // client BW - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp)); - if(Client_tmp>Client_40MHz) - Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High - - if(pEntry->bAssociated) - { - bConnected=TRUE; // client is connected or not - break; - } - } - else - { - break; - } - } -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - //3 To get entry's connection and BW infomation status. - - PSTA_INFO_T pstat; - - for(i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pstat) ) - { - Client_tmp = pstat->tx_bw; - if(Client_tmp>Client_40MHz) - Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High - - bConnected = TRUE; - } - } -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz)); - //1 Monitor whether the interference exists or not - if(PrimaryCCA->Monitor_flag == 1) - { - if(SecCHOffset == 1) // secondary channel is below the primary channel - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500)) - { - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - { - PrimaryCCA->intf_type = 1; - PrimaryCCA->PriCCA_flag = 1; - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF - if(PrimaryCCA->DupRTS_flag == 1) - PrimaryCCA->DupRTS_flag = 0; - } - else - { - PrimaryCCA->intf_type = 2; - if(PrimaryCCA->DupRTS_flag == 0) - PrimaryCCA->DupRTS_flag = 1; - } - - } - else // interferecne disappear - { - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - } - } - else if(SecCHOffset == 2) // secondary channel is above the primary channel - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500)) - { - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - { - PrimaryCCA->intf_type = 1; - PrimaryCCA->PriCCA_flag = 1; - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF - if(PrimaryCCA->DupRTS_flag == 1) - PrimaryCCA->DupRTS_flag = 0; - } - else - { - PrimaryCCA->intf_type = 2; - if(PrimaryCCA->DupRTS_flag == 0) - PrimaryCCA->DupRTS_flag = 1; - } - - } - else // interferecne disappear - { - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - } - - - } - PrimaryCCA->Monitor_flag = 0; - } - - //1 Dynamic Primary CCA Main Function - if(PrimaryCCA->Monitor_flag == 0) - { - if(Is40MHz) // if RFBW==40M mode which require to process primary cca - { - //2 STA is NOT Connected - if(!bConnected) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n")); - - if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected - { - PrimaryCCA->PriCCA_flag = 0; - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); - } - if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected - PrimaryCCA->DupRTS_flag = 0; - - if(SecCHOffset == 1) // secondary channel is below the primary channel - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) - { - PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - } - else - { - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - } - } - else if(SecCHOffset == 2) // secondary channel is above the primary channel - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) - { - PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - } - else - { - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type)); - } - //2 STA is Connected - else - { - if(Client_40MHz == 0) //3 // client BW = 20MHz - { - if(PrimaryCCA->PriCCA_flag == 0) - { - PrimaryCCA->PriCCA_flag = 1; - if(SecCHOffset==1) - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); - else if(SecCHOffset==2) - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag)); - } - else //3 // client BW = 40MHz - { - if(PrimaryCCA->intf_flag == 1) // interference is detected!! - { - if(PrimaryCCA->intf_type == 1) - { - if(PrimaryCCA->PriCCA_flag!=1) - { - PrimaryCCA->PriCCA_flag = 1; - if(SecCHOffset==1) - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); - else if(SecCHOffset==2) - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); - } - } - else if(PrimaryCCA->intf_type == 2) - { - if(PrimaryCCA->DupRTS_flag!=1) - PrimaryCCA->DupRTS_flag = 1; - } - } - else // if intf_flag==0 - { - if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low - { - if(SecCHOffset == 1) - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) - { - PrimaryCCA->intf_flag = 1; - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - } - } - else if(SecCHOffset == 2) - { - if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) - { - PrimaryCCA->intf_flag = 1; - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - } - - } - } - else // TP Traffic is High - { - if(SecCHOffset == 1) - { - if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500)) - { - if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time - { - PrimaryCCA->intf_flag = 1; - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - Delay = 1; - } - else - Delay = 0; - } - } - else if(SecCHOffset == 2) - { - if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500)) - { - if(Delay == 0) // add delay to avoid interference occurring abruptly - { - PrimaryCCA->intf_flag = 1; - if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) - PrimaryCCA->intf_type = 1; // interference is shift - else - PrimaryCCA->intf_type = 2; // interference is in-band - Delay = 1; - } - else - Delay = 0; - } - } - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag)); - } - - }// end of connected - } - } - //1 Dynamic Primary CCA Monitor Counter - if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1)) - { - if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag - { - Client_40MHz_pre = Client_40MHz; - return; - } - Counter++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter)); - if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time - { - PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!! - if(PrimaryCCA->PriCCA_flag == 1) - { - PrimaryCCA->PriCCA_flag = 0; - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); - } - Counter = 0; - } - } - } - - Client_40MHz_pre = Client_40MHz; -#endif -} - -#endif //#if (RTL8188E_SUPPORT == 1) - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +VOID +ODM_DIG_LowerBound_88E( + IN PDM_ODM_T pDM_Odm +) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); + } + //If only one Entry connected +} + +/*============================================================= +* AntDiv Before Link +===============================================================*/ +VOID +ODM_SwAntDivResetBeforeLink( + IN PDM_ODM_T pDM_Odm + ) +{ + + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + pDM_SWAT_Table->SWAS_NoLink_State = 0; + +} + + +//3============================================================ +//3 Dynamic Primary CCA +//3============================================================ + +VOID +ODM_PrimaryCCA_Init( + IN PDM_ODM_T pDM_Odm) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->Monitor_flag = 0; + PrimaryCCA->PriCCA_flag = 0; +} + +BOOLEAN +ODM_DynamicPrimaryCCA_DupRTS( + IN PDM_ODM_T pDM_Odm + ) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + return PrimaryCCA->DupRTS_flag; +} + +VOID +ODM_DynamicPrimaryCCA( + IN PDM_ODM_T pDM_Odm + ) +{ + +#if(DM_ODM_SUPPORT_TYPE !=ODM_CE) + + PADAPTER Adapter = pDM_Odm->Adapter; // for NIC + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PRT_WLAN_STA pEntry; +#endif + + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + BOOLEAN Is40MHz; + BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW + BOOLEAN bConnected = FALSE; // connected or not + static u1Byte Client_40MHz_pre = 0; + static u8Byte lastTxOkCnt = 0; + static u8Byte lastRxOkCnt = 0; + static u4Byte Counter = 0; + static u1Byte Delay = 1; + u8Byte curTxOkCnt; + u8Byte curRxOkCnt; + u1Byte SecCHOffset; + u1Byte i; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)) + return; + + if(pDM_Odm->SupportICType != ODM_RTL8188E) + return; + + Is40MHz = *(pDM_Odm->pBandWidth); + SecCHOffset = *(pDM_Odm->pSecChOffset); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(Is40MHz==1) + SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset)); + //3 Check Current WLAN Traffic + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; + lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //3 Check Current WLAN Traffic + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); +#endif + + //==================Debug Message==================== + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail)); + //================================================ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode +#endif + { + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter))); + //3 To get entry's connection and BW infomation status. + for(i=0;iBandWidth; // client BW + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp)); + if(Client_tmp>Client_40MHz) + Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High + + if(pEntry->bAssociated) + { + bConnected=TRUE; // client is connected or not + break; + } + } + else + { + break; + } + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //3 To get entry's connection and BW infomation status. + + PSTA_INFO_T pstat; + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) + { + Client_tmp = pstat->tx_bw; + if(Client_tmp>Client_40MHz) + Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High + + bConnected = TRUE; + } + } +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz)); + //1 Monitor whether the interference exists or not + if(PrimaryCCA->Monitor_flag == 1) + { + if(SecCHOffset == 1) // secondary channel is below the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500)) + { + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + { + PrimaryCCA->intf_type = 1; + PrimaryCCA->PriCCA_flag = 1; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF + if(PrimaryCCA->DupRTS_flag == 1) + PrimaryCCA->DupRTS_flag = 0; + } + else + { + PrimaryCCA->intf_type = 2; + if(PrimaryCCA->DupRTS_flag == 0) + PrimaryCCA->DupRTS_flag = 1; + } + + } + else // interferecne disappear + { + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + else if(SecCHOffset == 2) // secondary channel is above the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500)) + { + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + { + PrimaryCCA->intf_type = 1; + PrimaryCCA->PriCCA_flag = 1; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF + if(PrimaryCCA->DupRTS_flag == 1) + PrimaryCCA->DupRTS_flag = 0; + } + else + { + PrimaryCCA->intf_type = 2; + if(PrimaryCCA->DupRTS_flag == 0) + PrimaryCCA->DupRTS_flag = 1; + } + + } + else // interferecne disappear + { + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + + + } + PrimaryCCA->Monitor_flag = 0; + } + + //1 Dynamic Primary CCA Main Function + if(PrimaryCCA->Monitor_flag == 0) + { + if(Is40MHz) // if RFBW==40M mode which require to process primary cca + { + //2 STA is NOT Connected + if(!bConnected) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n")); + + if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected + { + PrimaryCCA->PriCCA_flag = 0; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); + } + if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected + PrimaryCCA->DupRTS_flag = 0; + + if(SecCHOffset == 1) // secondary channel is below the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) + { + PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + else + { + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + else if(SecCHOffset == 2) // secondary channel is above the primary channel + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) + { + PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!! + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + else + { + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type)); + } + //2 STA is Connected + else + { + if(Client_40MHz == 0) //3 // client BW = 20MHz + { + if(PrimaryCCA->PriCCA_flag == 0) + { + PrimaryCCA->PriCCA_flag = 1; + if(SecCHOffset==1) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); + else if(SecCHOffset==2) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag)); + } + else //3 // client BW = 40MHz + { + if(PrimaryCCA->intf_flag == 1) // interference is detected!! + { + if(PrimaryCCA->intf_type == 1) + { + if(PrimaryCCA->PriCCA_flag!=1) + { + PrimaryCCA->PriCCA_flag = 1; + if(SecCHOffset==1) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); + else if(SecCHOffset==2) + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); + } + } + else if(PrimaryCCA->intf_type == 2) + { + if(PrimaryCCA->DupRTS_flag!=1) + PrimaryCCA->DupRTS_flag = 1; + } + } + else // if intf_flag==0 + { + if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low + { + if(SecCHOffset == 1) + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9)) + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + } + else if(SecCHOffset == 2) + { + if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9)) + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + } + + } + } + else // TP Traffic is High + { + if(SecCHOffset == 1) + { + if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500)) + { + if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + Delay = 1; + } + else + Delay = 0; + } + } + else if(SecCHOffset == 2) + { + if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500)) + { + if(Delay == 0) // add delay to avoid interference occurring abruptly + { + PrimaryCCA->intf_flag = 1; + if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1) + PrimaryCCA->intf_type = 1; // interference is shift + else + PrimaryCCA->intf_type = 2; // interference is in-band + Delay = 1; + } + else + Delay = 0; + } + } + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag)); + } + + }// end of connected + } + } + //1 Dynamic Primary CCA Monitor Counter + if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1)) + { + if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag + { + Client_40MHz_pre = Client_40MHz; + return; + } + Counter++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter)); + if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time + { + PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!! + if(PrimaryCCA->PriCCA_flag == 1) + { + PrimaryCCA->PriCCA_flag = 0; + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); + } + Counter = 0; + } + } + } + + Client_40MHz_pre = Client_40MHz; +#endif +} + +#endif //#if (RTL8188E_SUPPORT == 1) + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.h b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.h index 20b9e1d7c02..c92b16147c5 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/phydm_rtl8188e.h @@ -1,79 +1,79 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_RTL8188E_H__ -#define __ODM_RTL8188E_H__ - -#if (RTL8188E_SUPPORT == 1) - - - -#define MAIN_ANT_CG_TRX 1 -#define AUX_ANT_CG_TRX 0 -#define MAIN_ANT_CGCS_RX 0 -#define AUX_ANT_CGCS_RX 1 - -VOID -ODM_DIG_LowerBound_88E( - IN PDM_ODM_T pDM_Odm -); - - - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - -#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink - -VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm); - -VOID -ODM_SetTxAntByTxInfo_88E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN u1Byte macId -); -#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_SetTxAntByTxInfo_88E( - IN PDM_ODM_T pDM_Odm -); -#endif - -VOID -ODM_PrimaryCCA_Init( - IN PDM_ODM_T pDM_Odm); - -BOOLEAN -ODM_DynamicPrimaryCCA_DupRTS( - IN PDM_ODM_T pDM_Odm); - -VOID -ODM_DynamicPrimaryCCA( - IN PDM_ODM_T pDM_Odm); - -#else /* (RTL8188E_SUPPORT == 0)*/ - -#define ODM_PrimaryCCA_Init(_pDM_Odm) -#define ODM_DynamicPrimaryCCA(_pDM_Odm) - -#endif /* RTL8188E_SUPPORT */ - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8188E_H__ +#define __ODM_RTL8188E_H__ + +#if (RTL8188E_SUPPORT == 1) + + + +#define MAIN_ANT_CG_TRX 1 +#define AUX_ANT_CG_TRX 0 +#define MAIN_ANT_CGCS_RX 0 +#define AUX_ANT_CGCS_RX 1 + +VOID +ODM_DIG_LowerBound_88E( + IN PDM_ODM_T pDM_Odm +); + + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + +#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink + +VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm); + +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +); +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxAntByTxInfo_88E( + IN PDM_ODM_T pDM_Odm +); +#endif + +VOID +ODM_PrimaryCCA_Init( + IN PDM_ODM_T pDM_Odm); + +BOOLEAN +ODM_DynamicPrimaryCCA_DupRTS( + IN PDM_ODM_T pDM_Odm); + +VOID +ODM_DynamicPrimaryCCA( + IN PDM_ODM_T pDM_Odm); + +#else /* (RTL8188E_SUPPORT == 0)*/ + +#define ODM_PrimaryCCA_Init(_pDM_Odm) +#define ODM_DynamicPrimaryCCA(_pDM_Odm) + +#endif /* RTL8188E_SUPPORT */ + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188e/version_rtl8188e.h b/package/kernel/rtl8192cd/phydm/rtl8188e/version_rtl8188e.h index 70afb29fac2..859109524a9 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188e/version_rtl8188e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188e/version_rtl8188e.h @@ -1,10 +1,10 @@ -/*RTL8188E PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8188E 20151218 -#define COMMIT_BY_8188E "BB_Luke" -#define RELEASE_VERSION_8188E 69 +/*RTL8188E PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8188E 20151218 +#define COMMIT_BY_8188E "BB_Luke" +#define RELEASE_VERSION_8188E 69 diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/hal8188freg.h b/package/kernel/rtl8192cd/phydm/rtl8188f/hal8188freg.h index 19c1654940a..d447f6d3f08 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/hal8188freg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/hal8188freg.h @@ -1,863 +1,863 @@ -/***************************************************************************** - * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. - * - * Module: __INC_HAL8188FREG_H - * - * - * Note: 1. Define Mac register address and corresponding bit mask map - * - * - * Export: Constants, macro, functions(API), global variables(None). - * - * Abbrev: - * - * History: - * Data Who Remark - * - *****************************************************************************/ -#ifndef __INC_HAL8188FREG_H -#define __INC_HAL8188FREG_H - - - -//============================================================ -// -//============================================================ - -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -#define REG_SYS_ISO_CTRL_8188F 0x0000 // 2 Byte -#define REG_SYS_FUNC_EN_8188F 0x0002 // 2 Byte -#define REG_APS_FSMCO_8188F 0x0004 // 4 Byte -#define REG_SYS_CLKR_8188F 0x0008 // 2 Byte -#define REG_9346CR_8188F 0x000A // 2 Byte -#define REG_EE_VPD_8188F 0x000C // 2 Byte -#define REG_AFE_MISC_8188F 0x0010 // 1 Byte -#define REG_SPS0_CTRL_8188F 0x0011 // 7 Byte -#define REG_SPS_OCP_CFG_8188F 0x0018 // 4 Byte -#define REG_RSV_CTRL_8188F 0x001C // 3 Byte -#define REG_RF_CTRL_8188F 0x001F // 1 Byte -#define REG_LPLDO_CTRL_8188F 0x0023 // 1 Byte -#define REG_AFE_XTAL_CTRL_8188F 0x0024 // 4 Byte -#define REG_AFE_PLL_CTRL_8188F 0x0028 // 4 Byte -#define REG_MAC_PLL_CTRL_EXT_8188F 0x002c // 4 Byte -#define REG_EFUSE_CTRL_8188F 0x0030 -#define REG_EFUSE_TEST_8188F 0x0034 -#define REG_PWR_DATA_8188F 0x0038 -#define REG_CAL_TIMER_8188F 0x003C -#define REG_ACLK_MON_8188F 0x003E -#define REG_GPIO_MUXCFG_8188F 0x0040 -#define REG_GPIO_IO_SEL_8188F 0x0042 -#define REG_MAC_PINMUX_CFG_8188F 0x0043 -#define REG_GPIO_PIN_CTRL_8188F 0x0044 -#define REG_GPIO_INTM_8188F 0x0048 -#define REG_LEDCFG0_8188F 0x004C -#define REG_LEDCFG1_8188F 0x004D -#define REG_LEDCFG2_8188F 0x004E -#define REG_LEDCFG3_8188F 0x004F -#define REG_FSIMR_8188F 0x0050 -#define REG_FSISR_8188F 0x0054 -#define REG_HSIMR_8188F 0x0058 -#define REG_HSISR_8188F 0x005c -#define REG_GPIO_EXT_CTRL 0x0060 -#define REG_MULTI_FUNC_CTRL_8188F 0x0068 -#define REG_GPIO_STATUS_8188F 0x006C -#define REG_SDIO_CTRL_8188F 0x0070 -#define REG_OPT_CTRL_8188F 0x0074 -#define REG_AFE_XTAL_CTRL_EXT_8188F 0x0078 -#define REG_MCUFWDL_8188F 0x0080 -#define REG_FW_DBG_STATUS_8188F 0x0088 -#define REG_FW_DBG_CTRL_8188F 0x008F -#define REG_WLLPS_CTRL_8188F 0x0090 -#define REG_HIMR0_8188F 0x00B0 -#define REG_HISR0_8188F 0x00B4 -#define REG_HIMR1_8188F 0x00B8 -#define REG_HISR1_8188F 0x00BC -#define REG_PMC_DBG_CTRL2_8188F 0x00CC -#define REG_EFUSE_BURN_GNT_8188F 0x00CF -#define REG_HPON_FSM_8188F 0x00EC -#define REG_SYS_CFG_8188F 0x00F0 -#define REG_SYS_CFG1_8188F 0x00FC -#define REG_ROM_VERSION 0x00FD - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -#define REG_CR_8188F 0x0100 -#define REG_PBP_8188F 0x0104 -#define REG_PKT_BUFF_ACCESS_CTRL_8188F 0x0106 -#define REG_TRXDMA_CTRL_8188F 0x010C -#define REG_TRXFF_BNDY_8188F 0x0114 -#define REG_TRXFF_STATUS_8188F 0x0118 -#define REG_RXFF_PTR_8188F 0x011C -#define REG_CPWM_8188F 0x012F -#define REG_FWIMR_8188F 0x0130 -#define REG_FWISR_8188F 0x0134 -#define REG_FTIMR_8188F 0x0138 -#define REG_PKTBUF_DBG_CTRL_8188F 0x0140 -#define REG_RXPKTBUF_CTRL_8188F 0x0142 -#define REG_PKTBUF_DBG_DATA_L_8188F 0x0144 -#define REG_PKTBUF_DBG_DATA_H_8188F 0x0148 - -#define REG_TC0_CTRL_8188F 0x0150 -#define REG_TC1_CTRL_8188F 0x0154 -#define REG_TC2_CTRL_8188F 0x0158 -#define REG_TC3_CTRL_8188F 0x015C -#define REG_TC4_CTRL_8188F 0x0160 -#define REG_TCUNIT_BASE_8188F 0x0164 -#define REG_RSVD3_8188F 0x0168 -#define REG_32K_CAL_REG1_8188F 0x0198 -#define REG_C2HEVT_MSG_NORMAL_8188F 0x01A0 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE -#define REG_C2HEVT_CLEAR_8188F 0x01AF -#define REG_MCUTST_1_8188F 0x01C0 -#define REG_MCUTST_2_8188F 0x01C4 -#define REG_MCUTST_WOWLAN_8188F 0x01C7 -#define REG_FMETHR_8188F 0x01C8 -#define REG_HMETFR_8188F 0x01CC -#define REG_HMEBOX_0_8188F 0x01D0 -#define REG_HMEBOX_1_8188F 0x01D4 -#define REG_HMEBOX_2_8188F 0x01D8 -#define REG_HMEBOX_3_8188F 0x01DC -#define REG_LLT_INIT_8188F 0x01E0 -#define REG_HMEBOX_EXT0_8188F 0x01F0 -#define REG_HMEBOX_EXT1_8188F 0x01F4 -#define REG_HMEBOX_EXT2_8188F 0x01F8 -#define REG_HMEBOX_EXT3_8188F 0x01FC - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -#define REG_RQPN_8188F 0x0200 -#define REG_FIFOPAGE_8188F 0x0204 -#define REG_TDECTRL_8188F 0x0208 -#define REG_DWBCN0_CTRL_8188F REG_TDECTRL -#define REG_TXDMA_OFFSET_CHK_8188F 0x020C -#define REG_TXDMA_STATUS_8188F 0x0210 -#define REG_RQPN_NPQ_8188F 0x0214 -#define REG_AUTO_LLT_8188F 0x0224 -#define REG_TDECTRL1_8188F 0x0228 -#define REG_DWBCN1_CTRL_8188F 0x0228 - -//----------------------------------------------------- -// -// 0x0280h ~ 0x02FFh RXDMA Configuration -// -//----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH_8188F 0x0280 -#define REG_FW_UPD_RDPTR_8188F 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 -#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA. -#define REG_RXPKT_NUM_8188F 0x0287 // The number of packets in RXPKTBUF. -#define REG_RXDMA_STATUS_8188F 0x0288 -#define REG_RXDMA_PRO_8188F 0x0290 -#define REG_EARLY_MODE_CONTROL_8188F 0x02BC -#define REG_RSVD5_8188F 0x02F0 -#define REG_RSVD6_8188F 0x02F4 - - -//----------------------------------------------------- -// -// 0x0300h ~ 0x03FFh PCIe -// -//----------------------------------------------------- -#define REG_PCIE_CTRL_REG_8188F 0x0300 -#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration -#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address -#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address -#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address -#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address -#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address -#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address -#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address -#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address -#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data -#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data -#define REG_DBI_ADDR_8188F 0x0350 // DBI Address -#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag -#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY -#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY -#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control -#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register -#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM -#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM -#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control - -#define REG_MGQ_TXBD_NUM_8188F 0x0380 - -// spec version 11 -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -#define REG_VOQ_INFORMATION_8188F 0x0400 -#define REG_VIQ_INFORMATION_8188F 0x0404 -#define REG_BEQ_INFORMATION_8188F 0x0408 -#define REG_BKQ_INFORMATION_8188F 0x040C -#define REG_MGQ_INFORMATION_8188F 0x0410 -#define REG_HGQ_INFORMATION_8188F 0x0414 -#define REG_BCNQ_INFORMATION_8188F 0x0418 -#define REG_TXPKT_EMPTY_8188F 0x041A - -#define REG_FWHW_TXQ_CTRL_8188F 0x0420 -#define REG_HWSEQ_CTRL_8188F 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 -#define REG_LIFECTRL_CTRL_8188F 0x0426 -#define REG_MULTI_BCNQ_OFFSET_8188F 0x0427 -#define REG_SPEC_SIFS_8188F 0x0428 -#define REG_RL_8188F 0x042A -#define REG_TXBF_CTRL_8188F 0x042C -#define REG_DARFRC_8188F 0x0430 -#define REG_RARFRC_8188F 0x0438 -#define REG_RRSR_8188F 0x0440 -#define REG_ARFR0_8188F 0x0444 -#define REG_ARFR1_8188F 0x044C -#define REG_CCK_CHECK_8188F 0x0454 -#define REG_AMPDU_MAX_TIME_8188F 0x0456 -#define REG_TXPKTBUF_BCNQ_BDNY1_8188F 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8188F 0x0458 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D -#define REG_NDPA_OPT_CTRL_8188F 0x045F -#define REG_FAST_EDCA_CTRL_8188F 0x0460 -#define REG_RD_RESP_PKT_TH_8188F 0x0463 -#define REG_DATA_SC_8188F 0x0483 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8188F 0x04B4 -#define REG_POWER_STAGE2_8188F 0x04B8 -#define REG_AMPDU_BURST_MODE_8188F 0x04BC -#define REG_PKT_VO_VI_LIFE_TIME_8188F 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8188F 0x04C2 -#define REG_STBC_SETTING_8188F 0x04C4 -#define REG_HT_SINGLE_AMPDU_8188F 0x04C7 -#define REG_PROT_MODE_CTRL_8188F 0x04C8 -#define REG_MAX_AGGR_NUM_8188F 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8188F 0x04CB -#define REG_BAR_MODE_CTRL_8188F 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8188F 0x04CF -#define REG_MACID_PKT_DROP0_8188F 0x04D0 -#define REG_MACID_PKT_SLEEP_8188F 0x04D4 - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -#define REG_EDCA_VO_PARAM_8188F 0x0500 -#define REG_EDCA_VI_PARAM_8188F 0x0504 -#define REG_EDCA_BE_PARAM_8188F 0x0508 -#define REG_EDCA_BK_PARAM_8188F 0x050C -#define REG_BCNTCFG_8188F 0x0510 -#define REG_PIFS_8188F 0x0512 -#define REG_RDG_PIFS_8188F 0x0513 -#define REG_SIFS_CTX_8188F 0x0514 -#define REG_SIFS_TRX_8188F 0x0516 -#define REG_AGGR_BREAK_TIME_8188F 0x051A -#define REG_SLOT_8188F 0x051B -#define REG_TX_PTCL_CTRL_8188F 0x0520 -#define REG_TXPAUSE_8188F 0x0522 -#define REG_DIS_TXREQ_CLR_8188F 0x0523 -#define REG_RD_CTRL_8188F 0x0524 -// -// Format for offset 540h-542h: -// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. -// [7:4]: Reserved. -// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. -// [23:20]: Reserved -// Description: -// | -// |<--Setup--|--Hold------------>| -// --------------|---------------------- -// | -// TBTT -// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. -// Described by Designer Tim and Bruce, 2011-01-14. -// -#define REG_TBTT_PROHIBIT_8188F 0x0540 -#define REG_RD_NAV_NXT_8188F 0x0544 -#define REG_NAV_PROT_LEN_8188F 0x0546 -#define REG_BCN_CTRL_8188F 0x0550 -#define REG_BCN_CTRL_1_8188F 0x0551 -#define REG_MBID_NUM_8188F 0x0552 -#define REG_DUAL_TSF_RST_8188F 0x0553 -#define REG_BCN_INTERVAL_8188F 0x0554 -#define REG_DRVERLYINT_8188F 0x0558 -#define REG_BCNDMATIM_8188F 0x0559 -#define REG_ATIMWND_8188F 0x055A -#define REG_USTIME_TSF_8188F 0x055C -#define REG_BCN_MAX_ERR_8188F 0x055D -#define REG_RXTSF_OFFSET_CCK_8188F 0x055E -#define REG_RXTSF_OFFSET_OFDM_8188F 0x055F -#define REG_TSFTR_8188F 0x0560 -#define REG_CTWND_8188F 0x0572 -#define REG_SECONDARY_CCA_CTRL_8188F 0x0577 -#define REG_PSTIMER_8188F 0x0580 -#define REG_TIMER0_8188F 0x0584 -#define REG_TIMER1_8188F 0x0588 -#define REG_ACMHWCTRL_8188F 0x05C0 -#define REG_SCH_TXCMD_8188F 0x05F8 - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -#define REG_MAC_CR_8188F 0x0600 -#define REG_TCR_8188F 0x0604 -#define REG_RCR_8188F 0x0608 -#define REG_RX_PKT_LIMIT_8188F 0x060C -#define REG_RX_DLK_TIME_8188F 0x060D -#define REG_RX_DRVINFO_SZ_8188F 0x060F - -#define REG_MACID_8188F 0x0610 -#define REG_BSSID_8188F 0x0618 -#define REG_MAR_8188F 0x0620 -#define REG_MBIDCAMCFG_8188F 0x0628 - -#define REG_USTIME_EDCA_8188F 0x0638 -#define REG_MAC_SPEC_SIFS_8188F 0x063A -#define REG_RESP_SIFP_CCK_8188F 0x063C -#define REG_RESP_SIFS_OFDM_8188F 0x063E -#define REG_ACKTO_8188F 0x0640 -#define REG_CTS2TO_8188F 0x0641 -#define REG_EIFS_8188F 0x0642 - -#define REG_NAV_UPPER_8188F 0x0652 // unit of 128 -#define REG_TRXPTCL_CTL_8188F 0x0668 - -// Security -#define REG_CAMCMD_8188F 0x0670 -#define REG_CAMWRITE_8188F 0x0674 -#define REG_CAMREAD_8188F 0x0678 -#define REG_CAMDBG_8188F 0x067C -#define REG_SECCFG_8188F 0x0680 - -// Power -#define REG_WOW_CTRL_8188F 0x0690 -#define REG_PS_RX_INFO_8188F 0x0692 -#define REG_UAPSD_TID_8188F 0x0693 -#define REG_WKFMCAM_CMD_8188F 0x0698 -#define REG_WKFMCAM_NUM_8188F 0x0698 -#define REG_WKFMCAM_RWD_8188F 0x069C -#define REG_RXFLTMAP0_8188F 0x06A0 -#define REG_RXFLTMAP1_8188F 0x06A2 -#define REG_RXFLTMAP2_8188F 0x06A4 -#define REG_BCN_PSR_RPT_8188F 0x06A8 -#define REG_BT_COEX_TABLE_8188F 0x06C0 -#define REG_BFMER0_INFO_8188F 0x06E4 -#define REG_BFMER1_INFO_8188F 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8188F 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8188F 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8188F 0x06FC - -// Hardware Port 2 -#define REG_MACID1_8188F 0x0700 -#define REG_BSSID1_8188F 0x0708 -#define REG_BFMEE_SEL_8188F 0x0714 -#define REG_SND_PTCL_CTRL_8188F 0x0718 - -// LTE_COEX -#define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 - -//----------------------------------------------------- -// -// Redifine 8192C register definition for compatibility -// -//----------------------------------------------------- - -// TODO: use these definition when using REG_xxx naming rule. -// NOTE: DO NOT Remove these definition. Use later. -#define EFUSE_CTRL_8188F REG_EFUSE_CTRL_8188F // E-Fuse Control. -#define EFUSE_TEST_8188F REG_EFUSE_TEST_8188F // E-Fuse Test. -#define MSR_8188F (REG_CR_8188F + 2) // Media Status register -#define ISR_8188F REG_HISR0_8188F -#define TSFR_8188F REG_TSFTR_8188F // Timing Sync Function Timer Register. - -#define PBP_8188F REG_PBP_8188F - -// Redifine MACID register, to compatible prior ICs. -#define IDR0_8188F REG_MACID_8188F // MAC ID Register, Offset 0x0050-0x0053 -#define IDR4_8188F (REG_MACID_8188F + 4) // MAC ID Register, Offset 0x0054-0x0055 - - -// -// 9. Security Control Registers (Offset: ) -// -#define RWCAM_8188F REG_CAMCMD_8188F //IN 8190 Data Sheet is called CAMcmd -#define WCAMI_8188F REG_CAMWRITE_8188F // Software write CAM input content -#define RCAMO_8188F REG_CAMREAD_8188F // Software read/write CAM config -#define CAMDBG_8188F REG_CAMDBG_8188F -#define SECR_8188F REG_SECCFG_8188F //Security Configuration Register - - -//---------------------------------------------------------------------------- -// 8195 IMR/ISR bits (offset 0xB0, 8bits) -//---------------------------------------------------------------------------- -#define IMR_DISABLED_8188F 0 -// IMR DW0(0x00B0-00B3) Bit 0-31 -#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2 -#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1 -#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt -#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1 -#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1 -#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error -#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK -#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt -#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0 -#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0 -#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7 -#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End -#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear -#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK -#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK -#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK -#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK -#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK -#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK -#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable -#define IMR_ROK_8188F BIT0 // Receive DMA OK - -// IMR DW1(0x00B4-00B7) Bit 0-31 -#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7 -#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1 -#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7 -#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear. -#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear -#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow -#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow - - - - - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ -//---------------------------------------------------------------------------- -// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- -/* -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopVO BIT3 -#define StopVI BIT2 -#define StopBE BIT1 -#define StopBK BIT0 -*/ - - -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -/* -//2 SYS_ISO_CTRL -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) -#define PWC_EV12V BIT(15) - - -//2 SYS_FUNC_EN -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) - -//2 APS_FSMCO -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) - -//2 SYS_CLKR -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) - - -//2 9346CR - -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - - -//2 RF_CTRL -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - -//2 LDOV12D_CTRL -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - - -//2 EFUSE_TEST (For RTL8188 partially) -#define EF_TRPT BIT(7) -#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 -#define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) -#define EFUSE_SEL_MASK 0x300 -#define EFUSE_WIFI_SEL_0 0x0 -#define EFUSE_BT_SEL_0 0x1 -#define EFUSE_BT_SEL_1 0x2 -#define EFUSE_BT_SEL_2 0x3 - - -//2 8051FWDL -//2 MCUFWDL -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define RAM_DL_SEL BIT(7) -#define ROM_DLEN BIT(19) -#define CPRST BIT(23) - - - -//2 REG_SYS_CFG -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define TRP_B15V_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define BT_FUNC BIT(16) -#define VENDOR_ID BIT(19) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) // RTL ID -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 -#define CHIP_VER_RTL_SHIFT 12 - -*/ -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -/* - -//2 Function Enable Registers -//2 CR 0x0100-0x0103 - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) -#define CALTMR_EN BIT(10) // 32k CAL TMR enable - -// Network type -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - - -//2 PBP - Page Size Register 0x0104 -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 - - -//2 TX/RXDMA 0x010C -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) - -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - - -//2 REG_C2HEVT_CLEAR 0x01AF -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - - - -//2 LLT_INIT 0x01E0 -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 - -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - -*/ -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -/* -//2 TDECTL 0x0208 -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - - -//2 TXDMA_OFFSET_CHK 0x020C -#define DROP_DATA_EN BIT(9) -*/ -//----------------------------------------------------- -// -// 0x0280h ~ 0x028Bh RX DMA Configuration -// -//----------------------------------------------------- -/* -//2 REG_RXDMA_CONTROL, 0x0286h - -// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before -// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. -#define RXPKT_RELEASE_POLL BIT(0) -// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in -// this bit. FW can start releasing packets after RXDMA entering idle mode. -#define RXDMA_IDLE BIT(1) -// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host -// completed, and stop DMA packet to host. RXDMA will then report Default: 0; -#define RW_RELEASE_EN BIT(2) -*/ -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -/* -//2 FWHW_TXQ_CTRL 0x0420 -#define EN_AMPDU_RTY_NEW BIT(7) - - -//2 REG_LIFECTRL_CTRL 0x0426 -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 - -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. - - -//2 SPEC SIFS 0x0428 -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) - -//2 RL 0x042A -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) -*/ - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -/* -//2 EDCA setting 0x050C -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - -//2 BCN_CTRL 0x0550 -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) - -//2 TxPause 0x0522 -#define STOP_BCNQ BIT(6) -*/ - - -//2 ACMHWCTRL 0x05C0 -#define AcmHw_HwEn_8188F BIT(0) -#define AcmHw_VoqEn_8188F BIT(1) -#define AcmHw_ViqEn_8188F BIT(2) -#define AcmHw_BeqEn_8188F BIT(3) -#define AcmHw_VoqStatus_8188F BIT(5) -#define AcmHw_ViqStatus_8188F BIT(6) -#define AcmHw_BeqStatus_8188F BIT(7) - - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -/* - -//2 TCR 0x0604 -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) -*/ - -//---------------------------------------------------------------------------- -// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) -//---------------------------------------------------------------------------- -/* -#define RCR_APPFCS BIT31 // WMAC append FCS after pauload -#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. -#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. -#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF -#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. -#define RCR_RSVD_BIT26 BIT26 // Reserved -*/ -#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload - -#endif // #ifndef __INC_HAL8188FREG_H +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8188FREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8188FREG_H +#define __INC_HAL8188FREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8188F 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8188F 0x0002 // 2 Byte +#define REG_APS_FSMCO_8188F 0x0004 // 4 Byte +#define REG_SYS_CLKR_8188F 0x0008 // 2 Byte +#define REG_9346CR_8188F 0x000A // 2 Byte +#define REG_EE_VPD_8188F 0x000C // 2 Byte +#define REG_AFE_MISC_8188F 0x0010 // 1 Byte +#define REG_SPS0_CTRL_8188F 0x0011 // 7 Byte +#define REG_SPS_OCP_CFG_8188F 0x0018 // 4 Byte +#define REG_RSV_CTRL_8188F 0x001C // 3 Byte +#define REG_RF_CTRL_8188F 0x001F // 1 Byte +#define REG_LPLDO_CTRL_8188F 0x0023 // 1 Byte +#define REG_AFE_XTAL_CTRL_8188F 0x0024 // 4 Byte +#define REG_AFE_PLL_CTRL_8188F 0x0028 // 4 Byte +#define REG_MAC_PLL_CTRL_EXT_8188F 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8188F 0x0030 +#define REG_EFUSE_TEST_8188F 0x0034 +#define REG_PWR_DATA_8188F 0x0038 +#define REG_CAL_TIMER_8188F 0x003C +#define REG_ACLK_MON_8188F 0x003E +#define REG_GPIO_MUXCFG_8188F 0x0040 +#define REG_GPIO_IO_SEL_8188F 0x0042 +#define REG_MAC_PINMUX_CFG_8188F 0x0043 +#define REG_GPIO_PIN_CTRL_8188F 0x0044 +#define REG_GPIO_INTM_8188F 0x0048 +#define REG_LEDCFG0_8188F 0x004C +#define REG_LEDCFG1_8188F 0x004D +#define REG_LEDCFG2_8188F 0x004E +#define REG_LEDCFG3_8188F 0x004F +#define REG_FSIMR_8188F 0x0050 +#define REG_FSISR_8188F 0x0054 +#define REG_HSIMR_8188F 0x0058 +#define REG_HSISR_8188F 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_MULTI_FUNC_CTRL_8188F 0x0068 +#define REG_GPIO_STATUS_8188F 0x006C +#define REG_SDIO_CTRL_8188F 0x0070 +#define REG_OPT_CTRL_8188F 0x0074 +#define REG_AFE_XTAL_CTRL_EXT_8188F 0x0078 +#define REG_MCUFWDL_8188F 0x0080 +#define REG_FW_DBG_STATUS_8188F 0x0088 +#define REG_FW_DBG_CTRL_8188F 0x008F +#define REG_WLLPS_CTRL_8188F 0x0090 +#define REG_HIMR0_8188F 0x00B0 +#define REG_HISR0_8188F 0x00B4 +#define REG_HIMR1_8188F 0x00B8 +#define REG_HISR1_8188F 0x00BC +#define REG_PMC_DBG_CTRL2_8188F 0x00CC +#define REG_EFUSE_BURN_GNT_8188F 0x00CF +#define REG_HPON_FSM_8188F 0x00EC +#define REG_SYS_CFG_8188F 0x00F0 +#define REG_SYS_CFG1_8188F 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8188F 0x0100 +#define REG_PBP_8188F 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8188F 0x0106 +#define REG_TRXDMA_CTRL_8188F 0x010C +#define REG_TRXFF_BNDY_8188F 0x0114 +#define REG_TRXFF_STATUS_8188F 0x0118 +#define REG_RXFF_PTR_8188F 0x011C +#define REG_CPWM_8188F 0x012F +#define REG_FWIMR_8188F 0x0130 +#define REG_FWISR_8188F 0x0134 +#define REG_FTIMR_8188F 0x0138 +#define REG_PKTBUF_DBG_CTRL_8188F 0x0140 +#define REG_RXPKTBUF_CTRL_8188F 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8188F 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8188F 0x0148 + +#define REG_TC0_CTRL_8188F 0x0150 +#define REG_TC1_CTRL_8188F 0x0154 +#define REG_TC2_CTRL_8188F 0x0158 +#define REG_TC3_CTRL_8188F 0x015C +#define REG_TC4_CTRL_8188F 0x0160 +#define REG_TCUNIT_BASE_8188F 0x0164 +#define REG_RSVD3_8188F 0x0168 +#define REG_32K_CAL_REG1_8188F 0x0198 +#define REG_C2HEVT_MSG_NORMAL_8188F 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE +#define REG_C2HEVT_CLEAR_8188F 0x01AF +#define REG_MCUTST_1_8188F 0x01C0 +#define REG_MCUTST_2_8188F 0x01C4 +#define REG_MCUTST_WOWLAN_8188F 0x01C7 +#define REG_FMETHR_8188F 0x01C8 +#define REG_HMETFR_8188F 0x01CC +#define REG_HMEBOX_0_8188F 0x01D0 +#define REG_HMEBOX_1_8188F 0x01D4 +#define REG_HMEBOX_2_8188F 0x01D8 +#define REG_HMEBOX_3_8188F 0x01DC +#define REG_LLT_INIT_8188F 0x01E0 +#define REG_HMEBOX_EXT0_8188F 0x01F0 +#define REG_HMEBOX_EXT1_8188F 0x01F4 +#define REG_HMEBOX_EXT2_8188F 0x01F8 +#define REG_HMEBOX_EXT3_8188F 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8188F 0x0200 +#define REG_FIFOPAGE_8188F 0x0204 +#define REG_TDECTRL_8188F 0x0208 +#define REG_DWBCN0_CTRL_8188F REG_TDECTRL +#define REG_TXDMA_OFFSET_CHK_8188F 0x020C +#define REG_TXDMA_STATUS_8188F 0x0210 +#define REG_RQPN_NPQ_8188F 0x0214 +#define REG_AUTO_LLT_8188F 0x0224 +#define REG_TDECTRL1_8188F 0x0228 +#define REG_DWBCN1_CTRL_8188F 0x0228 + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8188F 0x0280 +#define REG_FW_UPD_RDPTR_8188F 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_8188F 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS_8188F 0x0288 +#define REG_RXDMA_PRO_8188F 0x0290 +#define REG_EARLY_MODE_CONTROL_8188F 0x02BC +#define REG_RSVD5_8188F 0x02F0 +#define REG_RSVD6_8188F 0x02F4 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8188F 0x0300 +#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data +#define REG_DBI_ADDR_8188F 0x0350 // DBI Address +#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control +#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control + +#define REG_MGQ_TXBD_NUM_8188F 0x0380 + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION_8188F 0x0400 +#define REG_VIQ_INFORMATION_8188F 0x0404 +#define REG_BEQ_INFORMATION_8188F 0x0408 +#define REG_BKQ_INFORMATION_8188F 0x040C +#define REG_MGQ_INFORMATION_8188F 0x0410 +#define REG_HGQ_INFORMATION_8188F 0x0414 +#define REG_BCNQ_INFORMATION_8188F 0x0418 +#define REG_TXPKT_EMPTY_8188F 0x041A + +#define REG_FWHW_TXQ_CTRL_8188F 0x0420 +#define REG_HWSEQ_CTRL_8188F 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 +#define REG_LIFECTRL_CTRL_8188F 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8188F 0x0427 +#define REG_SPEC_SIFS_8188F 0x0428 +#define REG_RL_8188F 0x042A +#define REG_TXBF_CTRL_8188F 0x042C +#define REG_DARFRC_8188F 0x0430 +#define REG_RARFRC_8188F 0x0438 +#define REG_RRSR_8188F 0x0440 +#define REG_ARFR0_8188F 0x0444 +#define REG_ARFR1_8188F 0x044C +#define REG_CCK_CHECK_8188F 0x0454 +#define REG_AMPDU_MAX_TIME_8188F 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8188F 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8188F 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D +#define REG_NDPA_OPT_CTRL_8188F 0x045F +#define REG_FAST_EDCA_CTRL_8188F 0x0460 +#define REG_RD_RESP_PKT_TH_8188F 0x0463 +#define REG_DATA_SC_8188F 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8188F 0x04B4 +#define REG_POWER_STAGE2_8188F 0x04B8 +#define REG_AMPDU_BURST_MODE_8188F 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8188F 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8188F 0x04C2 +#define REG_STBC_SETTING_8188F 0x04C4 +#define REG_HT_SINGLE_AMPDU_8188F 0x04C7 +#define REG_PROT_MODE_CTRL_8188F 0x04C8 +#define REG_MAX_AGGR_NUM_8188F 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8188F 0x04CB +#define REG_BAR_MODE_CTRL_8188F 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8188F 0x04CF +#define REG_MACID_PKT_DROP0_8188F 0x04D0 +#define REG_MACID_PKT_SLEEP_8188F 0x04D4 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM_8188F 0x0500 +#define REG_EDCA_VI_PARAM_8188F 0x0504 +#define REG_EDCA_BE_PARAM_8188F 0x0508 +#define REG_EDCA_BK_PARAM_8188F 0x050C +#define REG_BCNTCFG_8188F 0x0510 +#define REG_PIFS_8188F 0x0512 +#define REG_RDG_PIFS_8188F 0x0513 +#define REG_SIFS_CTX_8188F 0x0514 +#define REG_SIFS_TRX_8188F 0x0516 +#define REG_AGGR_BREAK_TIME_8188F 0x051A +#define REG_SLOT_8188F 0x051B +#define REG_TX_PTCL_CTRL_8188F 0x0520 +#define REG_TXPAUSE_8188F 0x0522 +#define REG_DIS_TXREQ_CLR_8188F 0x0523 +#define REG_RD_CTRL_8188F 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8188F 0x0540 +#define REG_RD_NAV_NXT_8188F 0x0544 +#define REG_NAV_PROT_LEN_8188F 0x0546 +#define REG_BCN_CTRL_8188F 0x0550 +#define REG_BCN_CTRL_1_8188F 0x0551 +#define REG_MBID_NUM_8188F 0x0552 +#define REG_DUAL_TSF_RST_8188F 0x0553 +#define REG_BCN_INTERVAL_8188F 0x0554 +#define REG_DRVERLYINT_8188F 0x0558 +#define REG_BCNDMATIM_8188F 0x0559 +#define REG_ATIMWND_8188F 0x055A +#define REG_USTIME_TSF_8188F 0x055C +#define REG_BCN_MAX_ERR_8188F 0x055D +#define REG_RXTSF_OFFSET_CCK_8188F 0x055E +#define REG_RXTSF_OFFSET_OFDM_8188F 0x055F +#define REG_TSFTR_8188F 0x0560 +#define REG_CTWND_8188F 0x0572 +#define REG_SECONDARY_CCA_CTRL_8188F 0x0577 +#define REG_PSTIMER_8188F 0x0580 +#define REG_TIMER0_8188F 0x0584 +#define REG_TIMER1_8188F 0x0588 +#define REG_ACMHWCTRL_8188F 0x05C0 +#define REG_SCH_TXCMD_8188F 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_MAC_CR_8188F 0x0600 +#define REG_TCR_8188F 0x0604 +#define REG_RCR_8188F 0x0608 +#define REG_RX_PKT_LIMIT_8188F 0x060C +#define REG_RX_DLK_TIME_8188F 0x060D +#define REG_RX_DRVINFO_SZ_8188F 0x060F + +#define REG_MACID_8188F 0x0610 +#define REG_BSSID_8188F 0x0618 +#define REG_MAR_8188F 0x0620 +#define REG_MBIDCAMCFG_8188F 0x0628 + +#define REG_USTIME_EDCA_8188F 0x0638 +#define REG_MAC_SPEC_SIFS_8188F 0x063A +#define REG_RESP_SIFP_CCK_8188F 0x063C +#define REG_RESP_SIFS_OFDM_8188F 0x063E +#define REG_ACKTO_8188F 0x0640 +#define REG_CTS2TO_8188F 0x0641 +#define REG_EIFS_8188F 0x0642 + +#define REG_NAV_UPPER_8188F 0x0652 // unit of 128 +#define REG_TRXPTCL_CTL_8188F 0x0668 + +// Security +#define REG_CAMCMD_8188F 0x0670 +#define REG_CAMWRITE_8188F 0x0674 +#define REG_CAMREAD_8188F 0x0678 +#define REG_CAMDBG_8188F 0x067C +#define REG_SECCFG_8188F 0x0680 + +// Power +#define REG_WOW_CTRL_8188F 0x0690 +#define REG_PS_RX_INFO_8188F 0x0692 +#define REG_UAPSD_TID_8188F 0x0693 +#define REG_WKFMCAM_CMD_8188F 0x0698 +#define REG_WKFMCAM_NUM_8188F 0x0698 +#define REG_WKFMCAM_RWD_8188F 0x069C +#define REG_RXFLTMAP0_8188F 0x06A0 +#define REG_RXFLTMAP1_8188F 0x06A2 +#define REG_RXFLTMAP2_8188F 0x06A4 +#define REG_BCN_PSR_RPT_8188F 0x06A8 +#define REG_BT_COEX_TABLE_8188F 0x06C0 +#define REG_BFMER0_INFO_8188F 0x06E4 +#define REG_BFMER1_INFO_8188F 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8188F 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8188F 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8188F 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8188F 0x0700 +#define REG_BSSID1_8188F 0x0708 +#define REG_BFMEE_SEL_8188F 0x0714 +#define REG_SND_PTCL_CTRL_8188F 0x0718 + +// LTE_COEX +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8188F REG_EFUSE_CTRL_8188F // E-Fuse Control. +#define EFUSE_TEST_8188F REG_EFUSE_TEST_8188F // E-Fuse Test. +#define MSR_8188F (REG_CR_8188F + 2) // Media Status register +#define ISR_8188F REG_HISR0_8188F +#define TSFR_8188F REG_TSFTR_8188F // Timing Sync Function Timer Register. + +#define PBP_8188F REG_PBP_8188F + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8188F REG_MACID_8188F // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8188F (REG_MACID_8188F + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8188F REG_CAMCMD_8188F //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8188F REG_CAMWRITE_8188F // Software write CAM input content +#define RCAMO_8188F REG_CAMREAD_8188F // Software read/write CAM config +#define CAMDBG_8188F REG_CAMDBG_8188F +#define SECR_8188F REG_SECCFG_8188F //Security Configuration Register + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8188F 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK +#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK +#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8188F BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow + + + + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8188 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8188F BIT(0) +#define AcmHw_VoqEn_8188F BIT(1) +#define AcmHw_ViqEn_8188F BIT(2) +#define AcmHw_BeqEn_8188F BIT(3) +#define AcmHw_VoqStatus_8188F BIT(5) +#define AcmHw_ViqStatus_8188F BIT(6) +#define AcmHw_BeqStatus_8188F BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload + +#endif // #ifndef __INC_HAL8188FREG_H diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.c b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.c index e3dd26e1499..af4bc53904a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.c @@ -1,590 +1,590 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8188F_AGC_TAB[] = { - 0xC78, 0xFC000001, - 0xC78, 0xFB010001, - 0xC78, 0xFA020001, - 0xC78, 0xF9030001, - 0xC78, 0xF8040001, - 0xC78, 0xF7050001, - 0xC78, 0xF6060001, - 0xC78, 0xF5070001, - 0xC78, 0xF4080001, - 0xC78, 0xF3090001, - 0xC78, 0xF20A0001, - 0xC78, 0xF10B0001, - 0xC78, 0xF00C0001, - 0xC78, 0xEF0D0001, - 0xC78, 0xEE0E0001, - 0xC78, 0xED0F0001, - 0xC78, 0xEC100001, - 0xC78, 0xEB110001, - 0xC78, 0xEA120001, - 0xC78, 0xE9130001, - 0xC78, 0xE8140001, - 0xC78, 0xE7150001, - 0xC78, 0xE6160001, - 0xC78, 0xE5170001, - 0xC78, 0xE4180001, - 0xC78, 0xE3190001, - 0xC78, 0xE21A0001, - 0xC78, 0xE11B0001, - 0xC78, 0xE01C0001, - 0xC78, 0xC21D0001, - 0xC78, 0xC11E0001, - 0xC78, 0xC01F0001, - 0xC78, 0xA5200001, - 0xC78, 0xA4210001, - 0xC78, 0xA3220001, - 0xC78, 0xA2230001, - 0xC78, 0xA1240001, - 0xC78, 0xA0250001, - 0xC78, 0x65260001, - 0xC78, 0x64270001, - 0xC78, 0x63280001, - 0xC78, 0x62290001, - 0xC78, 0x612A0001, - 0xC78, 0x442B0001, - 0xC78, 0x432C0001, - 0xC78, 0x422D0001, - 0xC78, 0x412E0001, - 0xC78, 0x402F0001, - 0xC78, 0x21300001, - 0xC78, 0x20310001, - 0xC78, 0x05320001, - 0xC78, 0x04330001, - 0xC78, 0x03340001, - 0xC78, 0x02350001, - 0xC78, 0x01360001, - 0xC78, 0x00370001, - 0xC78, 0x00380001, - 0xC78, 0x00390001, - 0xC78, 0x003A0001, - 0xC78, 0x003B0001, - 0xC78, 0x003C0001, - 0xC78, 0x003D0001, - 0xC78, 0x003E0001, - 0xC78, 0x003F0001, - 0xC50, 0x69553422, - 0xC50, 0x69553420, - -}; - -void -ODM_ReadAndConfig_MP_8188F_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188F_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188F_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8188F(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188F_AGC_TAB(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188F_PHY_REG[] = { - 0x800, 0x83045700, - 0x804, 0x00000001, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x00200385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x824, 0x00390204, - 0x828, 0x00000000, - 0x82C, 0x00000000, - 0x830, 0x00000000, - 0x834, 0x00000000, - 0x838, 0x00000000, - 0x83C, 0x00000000, - 0x840, 0x00010000, - 0x844, 0x00000000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00030000, - 0x854, 0x00000000, - 0x858, 0x569A569A, - 0x85C, 0x569A569A, - 0x860, 0x00000130, - 0x864, 0x00000000, - 0x868, 0x00000000, - 0x86C, 0x27272700, - 0x870, 0x00000000, - 0x874, 0x25004000, - 0x878, 0x00000808, - 0x87C, 0x004F0201, - 0x880, 0xB0000B1E, - 0x884, 0x00000007, - 0x888, 0x00000000, - 0x88C, 0xCCC000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121111, - 0x910, 0x00000002, - 0x914, 0x00000201, - 0x948, 0x99000000, - 0x94C, 0x00000010, - 0x950, 0x20003000, - 0x954, 0x4A880000, - 0x958, 0x4BC5D87A, - 0x95C, 0x04EB9B79, - 0x96C, 0x00000003, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0x80000400, 0x00000000, 0x40000000, 0x00000000, - 0xA08, 0x8C038300, - 0xA0000000, 0x00000000, - 0xA08, 0x8C898300, - 0xB0000000, 0x00000000, - 0xA0C, 0x2E7F120F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0xD1D80000, - 0xA24, 0x5A7DA0BD, - 0xA28, 0x0000223B, - 0xA2C, 0x00D30000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000007, - 0xA78, 0x00008900, - 0xA7C, 0x225B0606, - 0xA80, 0x218075B1, - 0xA84, 0x00120000, - 0xA88, 0x040C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x05100000, - 0xA9C, 0x3F000000, - 0xAA0, 0x00000000, - 0xB2C, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05611, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x18800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9CC4A, - 0xC34, 0x31000040, - 0xC38, 0x21688080, - 0xC3C, 0x00001714, - 0xC40, 0x1F78403F, - 0xC44, 0x00010036, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0xC50, 0x69553420, - 0xC54, 0x43BC0094, - 0xC58, 0x00013169, - 0xC5C, 0x00250492, - 0xC60, 0x00000000, - 0xC64, 0x7112848B, - 0xC68, 0x47C07BFF, - 0xC6C, 0x00000036, - 0xC70, 0x2C7F000D, - 0xC74, 0x020600DB, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0xC80, 0x390000E4, - 0x80000400, 0x00000000, 0x40000000, 0x00000000, - 0xC84, 0x21F60000, - 0xA0000000, 0x00000000, - 0xC84, 0x11F60000, - 0xB0000000, 0x00000000, - 0xC88, 0x40000100, - 0xC8C, 0x20200000, - 0xC90, 0x00091521, - 0xC94, 0x00000000, - 0xC98, 0x00121820, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00000000, - 0xCA4, 0x000300A0, - 0xCA8, 0x00000000, - 0xCAC, 0x00000000, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x00222222, - 0xCE4, 0x10000000, - 0xCE8, 0x37644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x04030740, - 0xD04, 0x40020401, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC53, - 0xD18, 0x7A8F5B6F, - 0xD2C, 0xCB979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x98000000, - 0xD3C, 0x40127353, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xD6C, 0x2A201C16, - 0xD70, 0x1812362E, - 0xD74, 0x322C2220, - 0xD78, 0x000E3C24, - 0xE00, 0x2D2D2D2D, - 0xE04, 0x2D2D2D2D, - 0xE08, 0x0390272D, - 0xE10, 0x2D2D2D2D, - 0xE14, 0x2D2D2D2D, - 0xE18, 0x2D2D2D2D, - 0xE1C, 0x2D2D2D2D, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000008, - 0xE60, 0x021400A0, - 0xE64, 0x281600A0, - 0xE6C, 0x01C00010, - 0xE70, 0x01C00010, - 0xE74, 0x02000010, - 0xE78, 0x02000010, - 0xE7C, 0x02000010, - 0xE80, 0x02000010, - 0xE84, 0x01C00010, - 0xE88, 0x02000010, - 0xE8C, 0x01C00010, - 0xED0, 0x01C00010, - 0xED4, 0x01C00010, - 0xED8, 0x01C00010, - 0xEDC, 0x00000010, - 0xEE0, 0x00000010, - 0xEEC, 0x03C00010, - 0xF14, 0x00000003, - 0xF4C, 0x00000000, - 0xF00, 0x00000300, - -}; - -void -ODM_ReadAndConfig_MP_8188F_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188F_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8188F(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188F_PHY_REG(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188F_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 -}; - -void -ODM_ReadAndConfig_MP_8188F_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188F_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8188F(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_AGC_TAB[] = { + 0xC78, 0xFC000001, + 0xC78, 0xFB010001, + 0xC78, 0xFA020001, + 0xC78, 0xF9030001, + 0xC78, 0xF8040001, + 0xC78, 0xF7050001, + 0xC78, 0xF6060001, + 0xC78, 0xF5070001, + 0xC78, 0xF4080001, + 0xC78, 0xF3090001, + 0xC78, 0xF20A0001, + 0xC78, 0xF10B0001, + 0xC78, 0xF00C0001, + 0xC78, 0xEF0D0001, + 0xC78, 0xEE0E0001, + 0xC78, 0xED0F0001, + 0xC78, 0xEC100001, + 0xC78, 0xEB110001, + 0xC78, 0xEA120001, + 0xC78, 0xE9130001, + 0xC78, 0xE8140001, + 0xC78, 0xE7150001, + 0xC78, 0xE6160001, + 0xC78, 0xE5170001, + 0xC78, 0xE4180001, + 0xC78, 0xE3190001, + 0xC78, 0xE21A0001, + 0xC78, 0xE11B0001, + 0xC78, 0xE01C0001, + 0xC78, 0xC21D0001, + 0xC78, 0xC11E0001, + 0xC78, 0xC01F0001, + 0xC78, 0xA5200001, + 0xC78, 0xA4210001, + 0xC78, 0xA3220001, + 0xC78, 0xA2230001, + 0xC78, 0xA1240001, + 0xC78, 0xA0250001, + 0xC78, 0x65260001, + 0xC78, 0x64270001, + 0xC78, 0x63280001, + 0xC78, 0x62290001, + 0xC78, 0x612A0001, + 0xC78, 0x442B0001, + 0xC78, 0x432C0001, + 0xC78, 0x422D0001, + 0xC78, 0x412E0001, + 0xC78, 0x402F0001, + 0xC78, 0x21300001, + 0xC78, 0x20310001, + 0xC78, 0x05320001, + 0xC78, 0x04330001, + 0xC78, 0x03340001, + 0xC78, 0x02350001, + 0xC78, 0x01360001, + 0xC78, 0x00370001, + 0xC78, 0x00380001, + 0xC78, 0x00390001, + 0xC78, 0x003A0001, + 0xC78, 0x003B0001, + 0xC78, 0x003C0001, + 0xC78, 0x003D0001, + 0xC78, 0x003E0001, + 0xC78, 0x003F0001, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +ODM_ReadAndConfig_MP_8188F_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8188F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_AGC_TAB(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_PHY_REG[] = { + 0x800, 0x83045700, + 0x804, 0x00000001, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x00200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00030000, + 0x854, 0x00000000, + 0x858, 0x569A569A, + 0x85C, 0x569A569A, + 0x860, 0x00000130, + 0x864, 0x00000000, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x00000000, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x004F0201, + 0x880, 0xB0000B1E, + 0x884, 0x00000007, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0x948, 0x99000000, + 0x94C, 0x00000010, + 0x950, 0x20003000, + 0x954, 0x4A880000, + 0x958, 0x4BC5D87A, + 0x95C, 0x04EB9B79, + 0x96C, 0x00000003, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0xA08, 0x8C038300, + 0xA0000000, 0x00000000, + 0xA08, 0x8C898300, + 0xB0000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xD1D80000, + 0xA24, 0x5A7DA0BD, + 0xA28, 0x0000223B, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00008900, + 0xA7C, 0x225B0606, + 0xA80, 0x218075B1, + 0xA84, 0x00120000, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x05100000, + 0xA9C, 0x3F000000, + 0xAA0, 0x00000000, + 0xB2C, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x18800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9CC4A, + 0xC34, 0x31000040, + 0xC38, 0x21688080, + 0xC3C, 0x00001714, + 0xC40, 0x1F78403F, + 0xC44, 0x00010036, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00013169, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C07BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020600DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0xC84, 0x21F60000, + 0xA0000000, 0x00000000, + 0xC84, 0x11F60000, + 0xB0000000, 0x00000000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x10000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x04030740, + 0xD04, 0x40020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC53, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCB979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x98000000, + 0xD3C, 0x40127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000008, + 0xE60, 0x021400A0, + 0xE64, 0x281600A0, + 0xE6C, 0x01C00010, + 0xE70, 0x01C00010, + 0xE74, 0x02000010, + 0xE78, 0x02000010, + 0xE7C, 0x02000010, + 0xE80, 0x02000010, + 0xE84, 0x01C00010, + 0xE88, 0x02000010, + 0xE8C, 0x01C00010, + 0xED0, 0x01C00010, + 0xED4, 0x01C00010, + 0xED8, 0x01C00010, + 0xEDC, 0x00000010, + 0xEE0, 0x00000010, + 0xEEC, 0x03C00010, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8188F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_PHY_REG(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 +}; + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8188F(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.h b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.h index 71d15e50a7f..f0a4aa01597 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188F_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8188F_H -#define __INC_MP_BB_HW_IMG_8188F_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8188F_H +#define __INC_MP_BB_HW_IMG_8188F_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.c b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.c index 49024f9784b..093f45f1543 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.c @@ -1,3987 +1,3987 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8188f/hal8188f_fw.h" -#endif - - -#if (RTL8188F_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188F_FW_AP[] = { -0xF1, 0x88, 0x20, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x11, 0x25, 0x17, 0x05, 0x90, 0x44, 0x02, 0x00, -0x2F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x87, 0x32, 0x02, 0xB8, 0x9F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_NIC, ArrayLength_MP_8188F_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8188F_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8188F_FW_WoWLAN[] = { -0xF1, 0x88, 0x30, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x11, 0x25, 0x17, 0x06, 0x7C, 0x52, 0x02, 0x00, -0x2F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x86, 0xAD, 0x02, 0xC4, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xBA, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xC4, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xC4, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xBD, 0x05, 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0xF0, 0x22, 0x74, 0x12, 0x2F, 0xF5, 0x82, -0xE4, 0x34, 0xFC, 0x22, 0x12, 0x02, 0xF6, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x90, 0x85, 0xC9, 0xE0, -0x44, 0x10, 0xF0, 0x22, 0xF9, 0xE4, 0x3A, 0xFA, 0x02, 0x02, 0xF6, 0x7D, 0x05, 0x7F, 0x01, 0x02, -0x96, 0x06, 0xE5, 0x69, 0xF0, 0xA3, 0xE5, 0x6A, 0xF0, 0x22, 0x90, 0x00, 0x02, 0x12, 0x04, 0x18, -0xFF, 0x22, 0x7D, 0x05, 0x7F, 0x04, 0x02, 0x96, 0x06, 0x90, 0x85, 0xC1, 0xE0, 0x54, 0xF7, 0xF0, -0x22, 0xFF, 0x12, 0x02, 0xF6, 0xFE, 0x54, 0x0F, 0x22, 0x00, 0xF8, 0x34, -}; -u4Byte ArrayLength_MP_8188F_FW_WoWLAN = 21148; - -#endif - -void -ODM_ReadFirmware_MP_8188F_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_WoWLAN, ArrayLength_MP_8188F_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8188F_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8188f/hal8188f_fw.h" +#endif + + +#if (RTL8188F_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188F_FW_AP[] = { +0xF1, 0x88, 0x20, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x11, 0x25, 0x17, 0x05, 0x90, 0x44, 0x02, 0x00, +0x2F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x87, 0x32, 0x02, 0xB8, 0x9F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x22, 0x90, 0x92, 0x4B, 0x12, 0x86, 0xFA, 0x02, 0x03, 0xED, 0x74, 0xBC, 0x25, 0x62, +0xF5, 0x82, 0xE4, 0x34, 0x8F, 0x22, 0x90, 0x92, 0x52, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, 0x7D, 0x05, +0x7F, 0x01, 0x02, 0xAE, 0xF6, 0xE5, 0x68, 0xF0, 0xA3, 0xE5, 0x69, 0xF0, 0x22, 0x00, 0x8B, 0x34, + +}; +u4Byte ArrayLength_MP_8188F_FW_AP = 17584; + +#endif + +void +ODM_ReadFirmware_MP_8188F_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_AP, ArrayLength_MP_8188F_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8188F_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188F_FW_NIC[] = { +0xF1, 0x88, 0x10, 0x00, 0x01, 0x00, 0x0D, 0x00, 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+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_NIC, ArrayLength_MP_8188F_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8188F_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8188F_FW_WoWLAN[] = { +0xF1, 0x88, 0x30, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x11, 0x25, 0x17, 0x06, 0x7C, 0x52, 0x02, 0x00, +0x2F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x86, 0xAD, 0x02, 0xC4, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xBA, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC4, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC4, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xBD, 0x05, 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0x85, 0xC7, 0xE0, 0x90, 0x01, 0xBB, 0x22, 0xE5, 0x65, 0x25, 0xE0, 0x24, +0xF5, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0x22, 0x74, 0x21, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, +0x83, 0xE0, 0x22, 0x12, 0x05, 0x28, 0xE0, 0xFC, 0xA3, 0xE0, 0xF5, 0x82, 0x8C, 0x83, 0x22, 0xF0, +0x74, 0xCC, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0x8F, 0xF5, 0x83, 0x22, 0x74, 0xBC, 0x25, 0x63, 0xF5, +0x82, 0xE4, 0x34, 0x8F, 0xF5, 0x83, 0x22, 0x90, 0x92, 0x5B, 0xE4, 0xF0, 0xA3, 0x22, 0x90, 0x92, +0x59, 0xE4, 0xF0, 0xA3, 0x22, 0x90, 0x00, 0x06, 0x02, 0x04, 0x18, 0x90, 0x00, 0x08, 0x02, 0x04, +0x18, 0x90, 0x92, 0x9D, 0xE0, 0x14, 0x90, 0x92, 0x9F, 0xF0, 0x22, 0xFE, 0x54, 0x03, 0xFD, 0xEE, +0x13, 0x13, 0x54, 0x07, 0x22, 0x90, 0x92, 0xA2, 0xE0, 0xFE, 0xC3, 0x13, 0x54, 0x07, 0x22, 0x90, +0x93, 0x75, 0xE0, 0xFF, 0x90, 0x93, 0x73, 0xE0, 0x22, 0x8B, 0x5B, 0x8A, 0x5C, 0x89, 0x5D, 0x22, +0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22, 0x90, 0x92, 0x9E, 0xE0, 0x90, 0x05, 0x73, +0xF0, 0x22, 0x90, 0x85, 0xCB, 0xE0, 0x90, 0x05, 0x73, 0xF0, 0x22, 0x74, 0x12, 0x2F, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0x22, 0x12, 0x02, 0xF6, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x90, 0x85, 0xC9, 0xE0, +0x44, 0x10, 0xF0, 0x22, 0xF9, 0xE4, 0x3A, 0xFA, 0x02, 0x02, 0xF6, 0x7D, 0x05, 0x7F, 0x01, 0x02, +0x96, 0x06, 0xE5, 0x69, 0xF0, 0xA3, 0xE5, 0x6A, 0xF0, 0x22, 0x90, 0x00, 0x02, 0x12, 0x04, 0x18, +0xFF, 0x22, 0x7D, 0x05, 0x7F, 0x04, 0x02, 0x96, 0x06, 0x90, 0x85, 0xC1, 0xE0, 0x54, 0xF7, 0xF0, +0x22, 0xFF, 0x12, 0x02, 0xF6, 0xFE, 0x54, 0x0F, 0x22, 0x00, 0xF8, 0x34, +}; +u4Byte ArrayLength_MP_8188F_FW_WoWLAN = 21148; + +#endif + +void +ODM_ReadFirmware_MP_8188F_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_WoWLAN, ArrayLength_MP_8188F_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8188F_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.h b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.h index 2778653e4ad..1b862acb43d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8188F_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8188F_H -#define __INC_MP_FW_HW_IMG_8188F_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188F_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188F_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8188F_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8188F_H +#define __INC_MP_FW_HW_IMG_8188F_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188F_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188F_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188F_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.c b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.c index 7ae319d5943..49963a78fd3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.c @@ -1,288 +1,288 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8188F_MAC_REG[] = { - 0x024, 0x000000DF, - 0x025, 0x00000007, - 0x02B, 0x0000001C, - 0x283, 0x00000020, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000044, - 0x461, 0x00000044, - 0x4BC, 0x000000C0, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000028, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000028, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - -}; - -void -ODM_ReadAndConfig_MP_8188F_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188F_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188F_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8188F(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188F_MAC_REG(void) -{ - return 28; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_MAC_REG[] = { + 0x024, 0x000000DF, + 0x025, 0x00000007, + 0x02B, 0x0000001C, + 0x283, 0x00000020, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000044, + 0x461, 0x00000044, + 0x4BC, 0x000000C0, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000028, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000028, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + +}; + +void +ODM_ReadAndConfig_MP_8188F_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8188F(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_MAC_REG(void) +{ + return 28; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.h b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.h index 6d61aa5d8d6..8dd1f8ea312 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188F_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8188F_H -#define __INC_MP_MAC_HW_IMG_8188F_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8188F_H +#define __INC_MP_MAC_HW_IMG_8188F_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.c b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.c index 0221806a2e5..b81f54455b3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.c @@ -1,1143 +1,1143 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8188F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8188F_RadioA[] = { - 0x000, 0x00030000, - 0x008, 0x00008400, - 0x018, 0x00000407, - 0x019, 0x00000012, - 0x80000400, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000C6C, - 0xA0000000, 0x00000000, - 0x01B, 0x00001C6C, - 0xB0000000, 0x00000000, - 0x01E, 0x00080009, - 0x01F, 0x00000880, - 0x02F, 0x0001A060, - 0x03F, 0x00028000, - 0x042, 0x000060C0, - 0x057, 0x000D0000, - 0x058, 0x000C0160, - 0x067, 0x00001552, - 0x083, 0x00000000, - 0x0B0, 0x000FF9F0, - 0x0B1, 0x00022218, - 0x0B2, 0x00034C00, - 0x0B4, 0x0004484B, - 0x0B5, 0x0000112A, - 0x0B6, 0x0000053E, - 0x0B7, 0x00010408, - 0x0B8, 0x00010200, - 0x0B9, 0x00080001, - 0x0BA, 0x00040001, - 0x0BB, 0x00000400, - 0x0BF, 0x000C0000, - 0x0C2, 0x00002400, - 0x0C3, 0x00000009, - 0x0C4, 0x00040C91, - 0x0C5, 0x00099999, - 0x0C6, 0x000000A3, - 0x0C7, 0x0008F820, - 0x0C8, 0x00076C06, - 0x0C9, 0x00000000, - 0x0CA, 0x00080000, - 0x0DF, 0x00000180, - 0x0EF, 0x000001A0, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, - 0x051, 0x000E8231, - 0xA0000000, 0x00000000, - 0x051, 0x000E8333, - 0xB0000000, 0x00000000, - 0x80000400, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x000FAC88, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x052, 0x000FAC2C, - 0xA0000000, 0x00000000, - 0x052, 0x000FAC2C, - 0xB0000000, 0x00000000, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, - 0x053, 0x00000141, - 0xA0000000, 0x00000000, - 0x053, 0x00000103, - 0xB0000000, 0x00000000, - 0x056, 0x000517F0, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000090, - 0x035, 0x00000190, - 0x035, 0x00000290, - 0x036, 0x00001064, - 0x036, 0x00009064, - 0x036, 0x00011064, - 0x036, 0x00019064, - 0xA0000000, 0x00000000, - 0x035, 0x00000099, - 0x035, 0x00000199, - 0x035, 0x00000299, - 0x036, 0x00000064, - 0x036, 0x00008064, - 0x036, 0x00010064, - 0x036, 0x00018064, - 0xB0000000, 0x00000000, - 0x018, 0x00000C07, - 0x05A, 0x00048000, - 0x019, 0x000739D0, - 0x80000400, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD2, - 0x034, 0x00009DCF, - 0x034, 0x00008CF2, - 0x034, 0x00007CEF, - 0x034, 0x00006CEC, - 0x034, 0x00005CE9, - 0x034, 0x00004CCE, - 0x034, 0x00003CCB, - 0x034, 0x00002CC8, - 0x034, 0x00001C4B, - 0x034, 0x00000C48, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD2, - 0x034, 0x00009DD0, - 0x034, 0x00008CF3, - 0x034, 0x00007CF0, - 0x034, 0x00006CED, - 0x034, 0x00005CD2, - 0x034, 0x00004CCF, - 0x034, 0x00003CCC, - 0x034, 0x00002CC9, - 0x034, 0x00001C4C, - 0x034, 0x00000C49, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADD6, - 0x034, 0x00009DD3, - 0x034, 0x00008CF4, - 0x034, 0x00007CF1, - 0x034, 0x00006CEE, - 0x034, 0x00005CEB, - 0x034, 0x00004CCE, - 0x034, 0x00003CCB, - 0x034, 0x00002CC8, - 0x034, 0x00001C4B, - 0x034, 0x00000C48, - 0xB0000000, 0x00000000, - 0x000, 0x00030159, - 0x084, 0x00048000, - 0x086, 0x0000002A, - 0x087, 0x00000025, - 0x08E, 0x00065540, - 0x08F, 0x00088000, - 0x0EF, 0x000020A0, - 0x03B, 0x000F0F00, - 0x03B, 0x000E0B00, - 0x03B, 0x000D0900, - 0x03B, 0x000C0700, - 0x03B, 0x000B0600, - 0x03B, 0x000A0400, - 0x03B, 0x00090200, - 0x03B, 0x00080000, - 0x03B, 0x0007BF00, - 0x03B, 0x00060B00, - 0x03B, 0x0005C900, - 0x03B, 0x00040700, - 0x03B, 0x00030600, - 0x03B, 0x0002D500, - 0x03B, 0x00010200, - 0x03B, 0x0000E000, - 0x0EF, 0x000000A0, - 0x0EF, 0x00000010, - 0x03B, 0x0000C0A8, - 0x03B, 0x00010400, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x030, 0x00010000, - 0x031, 0x0000000F, - 0x032, 0x00007EFE, - 0x0EF, 0x00000000, - 0x000, 0x00010159, - 0x018, 0x0000FC07, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01F, 0x00080003, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01E, 0x00000001, - 0x01F, 0x00080000, - 0x000, 0x00033D95, - -}; - -void -ODM_ReadAndConfig_MP_8188F_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8188F_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8188F_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8188F(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8188F_RadioA(void) -{ - return 28; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -#endif - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 6, 7, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; -#endif - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F[] = {0, 1, 1, 2, 3, 4, 4, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 6, 6, 7, 8, 8, 10, 10, 11, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8188F_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "30", - "FCC", "2.4G", "20M", "HT", "1T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "30", - "FCC", "2.4G", "20M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "30", - "FCC", "2.4G", "20M", "HT", "1T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "30", - "FCC", "2.4G", "20M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "30", - "FCC", "2.4G", "20M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "30", - "FCC", "2.4G", "20M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "30", - "FCC", "2.4G", "20M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "30", - "FCC", "2.4G", "20M", "HT", "1T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "30", - "FCC", "2.4G", "20M", "HT", "1T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "30", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "30", - "FCC", "2.4G", "20M", "HT", "1T", "12", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "30", - "FCC", "2.4G", "20M", "HT", "1T", "13", "16", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "30", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "26", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", - "MKK", "2.4G", "40M", "HT", "1T", "04", "26", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", - "MKK", "2.4G", "40M", "HT", "1T", "05", "26", - "FCC", "2.4G", "40M", "HT", "1T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", - "MKK", "2.4G", "40M", "HT", "1T", "06", "26", - "FCC", "2.4G", "40M", "HT", "1T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", - "MKK", "2.4G", "40M", "HT", "1T", "07", "26", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", - "MKK", "2.4G", "40M", "HT", "1T", "08", "26", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", - "MKK", "2.4G", "40M", "HT", "1T", "09", "26", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", - "MKK", "2.4G", "40M", "HT", "1T", "10", "26", - "FCC", "2.4G", "40M", "HT", "1T", "11", "10", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "26", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", - "MKK", "2.4G", "40M", "HT", "1T", "12", "26", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", - "MKK", "2.4G", "40M", "HT", "1T", "13", "26", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", - "MKK", "2.4G", "40M", "HT", "2T", "12", "26", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", - "MKK", "2.4G", "40M", "HT", "2T", "13", "26", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "30", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "28", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8188F_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8188F_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8188F_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8188F(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_RadioA[] = { + 0x000, 0x00030000, + 0x008, 0x00008400, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000C6C, + 0xA0000000, 0x00000000, + 0x01B, 0x00001C6C, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00028000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000C0160, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF9F0, + 0x0B1, 0x00022218, + 0x0B2, 0x00034C00, + 0x0B4, 0x0004484B, + 0x0B5, 0x0000112A, + 0x0B6, 0x0000053E, + 0x0B7, 0x00010408, + 0x0B8, 0x00010200, + 0x0B9, 0x00080001, + 0x0BA, 0x00040001, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x0008F820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x000E8231, + 0xA0000000, 0x00000000, + 0x051, 0x000E8333, + 0xB0000000, 0x00000000, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x000FAC88, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x000FAC2C, + 0xA0000000, 0x00000000, + 0x052, 0x000FAC2C, + 0xB0000000, 0x00000000, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x053, 0x00000141, + 0xA0000000, 0x00000000, + 0x053, 0x00000103, + 0xB0000000, 0x00000000, + 0x056, 0x000517F0, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000090, + 0x035, 0x00000190, + 0x035, 0x00000290, + 0x036, 0x00001064, + 0x036, 0x00009064, + 0x036, 0x00011064, + 0x036, 0x00019064, + 0xA0000000, 0x00000000, + 0x035, 0x00000099, + 0x035, 0x00000199, + 0x035, 0x00000299, + 0x036, 0x00000064, + 0x036, 0x00008064, + 0x036, 0x00010064, + 0x036, 0x00018064, + 0xB0000000, 0x00000000, + 0x018, 0x00000C07, + 0x05A, 0x00048000, + 0x019, 0x000739D0, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD2, + 0x034, 0x00009DCF, + 0x034, 0x00008CF2, + 0x034, 0x00007CEF, + 0x034, 0x00006CEC, + 0x034, 0x00005CE9, + 0x034, 0x00004CCE, + 0x034, 0x00003CCB, + 0x034, 0x00002CC8, + 0x034, 0x00001C4B, + 0x034, 0x00000C48, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD2, + 0x034, 0x00009DD0, + 0x034, 0x00008CF3, + 0x034, 0x00007CF0, + 0x034, 0x00006CED, + 0x034, 0x00005CD2, + 0x034, 0x00004CCF, + 0x034, 0x00003CCC, + 0x034, 0x00002CC9, + 0x034, 0x00001C4C, + 0x034, 0x00000C49, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADD6, + 0x034, 0x00009DD3, + 0x034, 0x00008CF4, + 0x034, 0x00007CF1, + 0x034, 0x00006CEE, + 0x034, 0x00005CEB, + 0x034, 0x00004CCE, + 0x034, 0x00003CCB, + 0x034, 0x00002CC8, + 0x034, 0x00001C4B, + 0x034, 0x00000C48, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00048000, + 0x086, 0x0000002A, + 0x087, 0x00000025, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x03B, 0x000F0F00, + 0x03B, 0x000E0B00, + 0x03B, 0x000D0900, + 0x03B, 0x000C0700, + 0x03B, 0x000B0600, + 0x03B, 0x000A0400, + 0x03B, 0x00090200, + 0x03B, 0x00080000, + 0x03B, 0x0007BF00, + 0x03B, 0x00060B00, + 0x03B, 0x0005C900, + 0x03B, 0x00040700, + 0x03B, 0x00030600, + 0x03B, 0x0002D500, + 0x03B, 0x00010200, + 0x03B, 0x0000E000, + 0x0EF, 0x000000A0, + 0x0EF, 0x00000010, + 0x03B, 0x0000C0A8, + 0x03B, 0x00010400, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x030, 0x00010000, + 0x031, 0x0000000F, + 0x032, 0x00007EFE, + 0x0EF, 0x00000000, + 0x000, 0x00010159, + 0x018, 0x0000FC07, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033D95, + +}; + +void +ODM_ReadAndConfig_MP_8188F_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8188F(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_RadioA(void) +{ + return 28; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 6, 7, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F[] = {0, 1, 1, 2, 3, 4, 4, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 6, 6, 7, 8, 8, 10, 10, 11, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8188F_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "16", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "10", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8188F_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188F_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8188F_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8188F(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.h b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.h index 7bf5f4883d3..417b3b8567a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/halhwimg8188f_rf.h @@ -1,79 +1,79 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8188F_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8188F_H -#define __INC_MP_RF_HW_IMG_8188F_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8188F_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8188F_TXPWR_LMT(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8188F_H +#define __INC_MP_RF_HW_IMG_8188F_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TXPWR_LMT(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8188f/version_rtl8188f.h b/package/kernel/rtl8192cd/phydm/rtl8188f/version_rtl8188f.h index fec40095e1f..7bb443cec4b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8188f/version_rtl8188f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8188f/version_rtl8188f.h @@ -1,10 +1,10 @@ -/*RTL8188F PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8188F 20160330 -#define COMMIT_BY_8188F "BB_DAVID" -#define RELEASE_VERSION_8188F 27 +/*RTL8188F PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8188F 20160330 +#define COMMIT_BY_8188F "BB_DAVID" +#define RELEASE_VERSION_8188F 27 diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/hal8192ereg.h b/package/kernel/rtl8192cd/phydm/rtl8192e/hal8192ereg.h index be35fc35498..2ef06fd5539 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/hal8192ereg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/hal8192ereg.h @@ -1,1117 +1,1117 @@ -/***************************************************************************** - * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. - * - * Module: __INC_HAL8192EREG_H - * - * - * Note: 1. Define Mac register address and corresponding bit mask map - * - * - * Export: Constants, macro, functions(API), global variables(None). - * - * Abbrev: - * - * History: - * Data Who Remark - * - *****************************************************************************/ -#ifndef __INC_HAL8192EREG_H -#define __INC_HAL8192EREG_H - - - -//============================================================ -// -//============================================================ - -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -#define REG_SYS_ISO_CTRL_8192E 0x0000 // 2 Byte -#define REG_SYS_FUNC_EN_8192E 0x0002 // 2 Byte -#define REG_SYS_PW_CTRL_8192E 0x0004 // 4 Byte -#define REG_SYS_CLKR_8192E 0x0008 // 2 Byte -#define REG_SYS_EEPROM_CTRL_8192E 0x000A // 2 Byte -#define REG_EE_VPD_8192E 0x000C // 2 Byte -#define REG_SYS_SWR_CTRL1_8192E 0x0010 // 1 Byte -#define REG_SYS_SWR_CTRL2_8192E 0x0014 // 1 Byte -#define REG_SYS_SWR_CTRL3_8192E 0x0018 // 4 Byte -#define REG_RSV_CTRL_8192E 0x001C // 3 Byte -#define REG_RF_CTRL_8192E 0x001F // 1 Byte -#define REG_AFE_CTRL1_8192E 0x0024 // 4 Byte -#define REG_AFE_CTRL2_8192E 0x0028 // 4 Byte -#define REG_AFE_CTRL3_8192E 0x002c // 4 Byte -#define REG_EFUSE_CTRL_8192E 0x0030 -#define REG_LDO_EFUSE_CTRL_8192E 0x0034 -#define REG_PWR_DATA_8192E 0x0038 -#define REG_CAL_TIMER_8192E 0x003C -#define REG_ACLK_MON_8192E 0x003E -#define REG_GPIO_MUXCFG_8192E 0x0040 -#define REG_GPIO_IO_SEL_8192E 0x0042 -#define REG_MAC_PINMUX_CFG_8192E 0x0043 // ?????? -#define REG_GPIO_PIN_CTRL_8192E 0x0044 -#define REG_GPIO_INTM_8192E 0x0048 -#define BIT_REG_LED_CFG_8192E 0x004C -#define REG_LEDCFG2_8192E 0x004E // ?????? -#define REG_FSIMR_8192E 0x0050 -#define REG_FSISR_8192E 0x0054 -#define REG_HSIMR_8192E 0x0058 -#define REG_HSISR_8192E 0x005c -#define REG_PAD_CTRL1_8192E 0x0064 -#define REG_WL_BT_PWR_CTRL_8192E 0x0068 -#define REG_SDM_DEBUG_8192E 0x006C -#define REG_SDIO_CTRL_8192E 0x0070 -#define REG_HCI_OPT_CTRL_8192E 0x0074 -#define REG_AFE_CTRL4_8192E 0x0078 -#define REG_8051FW_CTRL_8192E 0x0080 -#define REG_WLLPS_CTRL_8192E 0x0090 -#define REG_HIMR0_8192E 0x00B0 -#define REG_HISR0_8192E 0x00B4 -#define REG_HIMR1_8192E 0x00B8 -#define REG_HISR1_8192E 0x00BC -#define REG_PMC_DBG_CTRL2_8192E 0x00CC -#define REG_EFUSE_BURN_GNT_8192E 0x00CF -#define REG_SYS_CFG1_8192E 0x00F0 -#define REG_SYS_CFG2_8192E 0x00FC - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -#define REG_CR_8192E 0x0100 -#define REG_PBP_8192E 0x0104 // ?????? -#define REG_PKT_BUFF_ACCESS_CTRL_8192E 0x0106 // ?????? -#define REG_TRXDMA_CTRL_8192E 0x010C -#define REG_TRXFF_BNDY_8192E 0x0114 -#define REG_RXFF_PTR_8192E 0x011C -#define REG_CPWM_8192E 0x012C -#define REG_FWIMR_8192E 0x0130 -#define REG_FWISR_8192E 0x0134 -#define REG_FTIMR_8192E 0x0138 -#define REG_PKTBUF_DBG_CTRL_8192E 0x0140 -#define REG_RXPKTBUF_CTRL_8192E 0x0142 // ?????? -#define REG_PKTBUF_DBG_DATA_L_8192E 0x0144 -#define REG_PKTBUF_DBG_DATA_H_8192E 0x0148 - -#define REG_TC0_CTRL_8192E 0x0150 -#define REG_TC1_CTRL_8192E 0x0154 -#define REG_TC2_CTRL_8192E 0x0158 -#define REG_TC3_CTRL_8192E 0x015C -#define REG_TC4_CTRL_8192E 0x0160 -#define REG_TCUNIT_BASE_8192E 0x0164 -#define REG_RSVD3_8192E 0x0168 // ????? - -#define REG_C2HEVT_MSG_NORMAL_8192E 0x01A0 // ?????? -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ?????? -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ?????? -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ?????? -#define REG_C2HEVT_CLEAR_8192E 0x01AF // ?????? -#define REG_MCUTST_1_8192E 0x01C0 -#define REG_MCUTST_2_8192E 0x01C4 -#define REG_MCUTST_WOWLAN_8192E 0x01C7 // ?????? -#define REG_FMETHR_8192E 0x01C8 -#define REG_HMETFR_8192E 0x01CC -#define REG_HMEBOX_0_8192E 0x01D0 -#define REG_HMEBOX_1_8192E 0x01D4 -#define REG_HMEBOX_2_8192E 0x01D8 -#define REG_HMEBOX_3_8192E 0x01DC -#define REG_LLT_INIT_8192E 0x01E0 -#define REG_HMEBOX_EXT0_8192E 0x01F0 // ?????? -#define REG_HMEBOX_EXT1_8192E 0x01F4 // ?????? -#define REG_HMEBOX_EXT2_8192E 0x01F8 // ?????? -#define REG_HMEBOX_EXT3_8192E 0x01FC // ?????? - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -#define REG_RQPN_8192E 0x0200 -#define REG_FIFOPAGE_8192E 0x0204 -#define REG_DWBCN0_CTRL_8192E 0x0208 -#define REG_TXDMA_OFFSET_CHK_8192E 0x020C -#define REG_TXDMA_STATUS_8192E 0x0210 -#define REG_RQPN_NPQ_8192E 0x0214 -#define REG_AUTO_LLT_8192E 0x0224 -#define REG_DWBCN1_CTRL_8192E 0x0228 - - -//----------------------------------------------------- -// -// 0x0280h ~ 0x02FFh RXDMA Configuration -// -//----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH_8192E 0x0280 -#define REG_RXPKT_NUM_8192E 0x0284 // The number of packets in RXPKTBUF. -#define REG_RXDMA_CONTROL_8192E 0x0286 // ?????? Control the RX DMA. -#define REG_RXDMA_STATUS_8192E 0x0288 -#define REG_RXDMA_PRO_8192E 0x0290 // ?????? -#define REG_EARLY_MODE_CONTROL_8192E 0x02BC // ?????? -#define REG_RSVD5_8192E 0x02F0 // ?????? - - -//----------------------------------------------------- -// -// 0x0300h ~ 0x03FFh PCIe -// -//----------------------------------------------------- -#define REG_PCIE_CTRL_REG_8192E 0x0300 -#define REG_INT_MIG_8192E 0x0304 // Interrupt Migration -#define REG_BCNQ_TXBD_DESA_8192E 0x0308 // TX Beacon Descriptor Address -#define REG_MGQ_TXBD_DESA_8192E 0x0310 // TX Manage Queue Descriptor Address -#define REG_VOQ_TXBD_DESA_8192E 0x0318 // TX VO Queue Descriptor Address -#define REG_VIQ_TXBD_DESA_8192E 0x0320 // TX VI Queue Descriptor Address -#define REG_BEQ_TXBD_DESA_8192E 0x0328 // TX BE Queue Descriptor Address -#define REG_BKQ_TXBD_DESA_8192E 0x0330 // TX BK Queue Descriptor Address -#define REG_RXQ_RXBD_DESA_8192E 0x0338 // RX Queue Descriptor Address -#define REG_HI0Q_TXBD_DESA_8192E 0x0340 -#define REG_HI1Q_TXBD_DESA_8192E 0x0348 -#define REG_HI2Q_TXBD_DESA_8192E 0x0350 -#define REG_HI3Q_TXBD_DESA_8192E 0x0358 -#define REG_HI4Q_TXBD_DESA_8192E 0x0360 -#define REG_HI5Q_TXBD_DESA_8192E 0x0368 -#define REG_HI6Q_TXBD_DESA_8192E 0x0370 -#define REG_HI7Q_TXBD_DESA_8192E 0x0378 -#define REG_MGQ_TXBD_NUM_8192E 0x0380 -#define REG_RX_RXBD_NUM_8192E 0x0382 -#define REG_VOQ_TXBD_NUM_8192E 0x0384 -#define REG_VIQ_TXBD_NUM_8192E 0x0386 -#define REG_BEQ_TXBD_NUM_8192E 0x0388 -#define REG_BKQ_TXBD_NUM_8192E 0x038A -#define REG_HI0Q_TXBD_NUM_8192E 0x038C -#define REG_HI1Q_TXBD_NUM_8192E 0x038E -#define REG_HI2Q_TXBD_NUM_8192E 0x0390 -#define REG_HI3Q_TXBD_NUM_8192E 0x0392 -#define REG_HI4Q_TXBD_NUM_8192E 0x0394 -#define REG_HI5Q_TXBD_NUM_8192E 0x0396 -#define REG_HI6Q_TXBD_NUM_8192E 0x0398 -#define REG_HI7Q_TXBD_NUM_8192E 0x039A -#define REG_TSFTIMER_HCI_8192E 0x039C - -//Read Write Point -#define REG_VOQ_TXBD_IDX_8192E 0x03A0 -#define REG_VIQ_TXBD_IDX_8192E 0x03A4 -#define REG_BEQ_TXBD_IDX_8192E 0x03A8 -#define REG_BKQ_TXBD_IDX_8192E 0x03AC -#define REG_MGQ_TXBD_IDX_8192E 0x03B0 -#define REG_RXQ_TXBD_IDX_8192E 0x03B4 -#define REG_HI0Q_TXBD_IDX_8192E 0x03B8 -#define REG_HI1Q_TXBD_IDX_8192E 0x03BC -#define REG_HI2Q_TXBD_IDX_8192E 0x03C0 -#define REG_HI3Q_TXBD_IDX_8192E 0x03C4 -#define REG_HI4Q_TXBD_IDX_8192E 0x03C8 -#define REG_HI5Q_TXBD_IDX_8192E 0x03CC -#define REG_HI6Q_TXBD_IDX_8192E 0x03D0 -#define REG_HI7Q_TXBD_IDX_8192E 0x03D4 - -#define REG_PCIE_HCPWM_8192EE 0x03D8 // ?????? -#define REG_PCIE_HRPWM_8192EE 0x03DC //PCIe RPWM // ?????? -#define REG_DBI_WDATA_V1_8192E 0x03E8 -#define REG_DBI_RDATA_V1_8192E 0x03EC -#define REG_DBI_FLAG_V1_8192E 0x03F0 -#define REG_MDIO_V1_8192E 0x3F4 -#define REG_PCIE_MIX_CFG_8192E 0x3F8 - - - -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -#define REG_TXPKT_EMPTY_8192E 0x041A -#define REG_FWHW_TXQ_CTRL_8192E 0x0420 -#define REG_HWSEQ_CTRL_8192E 0x0423 -#define REG_BCNQ_BDNY_8192E 0x0424 -#define REG_MGQ_BDNY_8192E 0x0425 -#define REG_LIFETIME_EN_8192E 0x0426 -#define REG_FW_FREE_TAIL_8192E 0x0427 -#define REG_SPEC_SIFS_8192E 0x0428 -#define REG_RETRY_LIMIT_8192E 0x042A -#define REG_TXBF_CTRL_8192E 0x042C -#define REG_DARFRC_8192E 0x0430 -#define REG_RARFRC_8192E 0x0438 -#define REG_RRSR_8192E 0x0440 -#define REG_ARFR0_8192E 0x0444 -#define REG_ARFR1_8192E 0x044C -#define REG_CCK_CHECK_8192E 0x0454 -#define REG_AMPDU_MAX_TIME_8192E 0x0456 -#define REG_BCNQ1_BDNY_8192E 0x0457 -#define REG_AMPDU_MAX_LENGTH_8192E 0x0458 -#define REG_WMAC_LBK_BUF_HD_8192E 0x045D -#define REG_NDPA_OPT_CTRL_8192E 0x045F -#define REG_FAST_EDCA_CTRL_8192E 0x0460 -#define REG_RD_RESP_PKT_TH_8192E 0x0463 -#define REG_DATA_SC_8192E 0x0483 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8192E 0x04B4 -#define REG_SW_AMPDU_BURST_MODE_CTRL_8192E 0x04BC -#define REG_PKT_LIFE_TIME_8192E 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8192E 0x04C2 // ?????? - -#define REG_STBC_SETTING_8192E 0x04C4 -#define REG_PROT_MODE_CTRL_8192E 0x04C8 -#define REG_MAX_AGGR_NUM_8192E 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8192E 0x04CB -#define REG_BAR_MODE_CTRL_8192E 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8192E 0x04CF -#define REG_MACID_SLEEP2_8192E 0x04D0 -#define REG_MACID_SLEEP_8192E 0x04D4 -#define REG_HW_SEQ0_8192E 0x04D8 -#define REG_HW_SEQ1_8192E 0x04DA -#define REG_HW_SEQ2_8192E 0x04DC -#define REG_HW_SEQ3_8192E 0x04DE -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192E 0x045D // ?????? - - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -// gogogo -#define REG_EDCA_VO_PARAM_8192E 0x0500 -#define REG_EDCA_VI_PARAM_8192E 0x0504 -#define REG_EDCA_BE_PARAM_8192E 0x0508 -#define REG_EDCA_BK_PARAM_8192E 0x050C -#define REG_BCNTCFG_8192E 0x0510 -#define REG_PIFS_8192E 0x0512 -#define REG_RDG_PIFS_8192E 0x0513 -#define REG_SIFS_CTX_8192E 0x0514 -#define REG_SIFS_TRX_8192E 0x0516 -#define REG_AGGR_BREAK_TIME_8192E 0x051A -#define REG_SLOT_8192E 0x051B -#define REG_TX_PTCL_CTRL_8192E 0x0520 -#define REG_TXPAUSE_8192E 0x0522 -#define REG_DIS_TXREQ_CLR_8192E 0x0523 -#define REG_RD_CTRL_8192E 0x0524 -// -// Format for offset 540h-542h: -// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. -// [7:4]: Reserved. -// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. -// [23:20]: Reserved -// Description: -// | -// |<--Setup--|--Hold------------>| -// --------------|---------------------- -// | -// TBTT -// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. -// Described by Designer Tim and Bruce, 2011-01-14. -// -#define REG_TBTT_PROHIBIT_8192E 0x0540 -#define REG_RD_NAV_NXT_8192E 0x0544 -#define REG_NAV_PROT_LEN_8192E 0x0546 -#define REG_BCN_CTRL_8192E 0x0550 -#define REG_BCN_CTRL_1_8192E 0x0551 -#define REG_MBID_NUM_8192E 0x0552 -#define REG_DUAL_TSF_RST_8192E 0x0553 -#define REG_MBSSID_BCN_SPACE_8192E 0x0554 -#define REG_DRVERLYINT_8192E 0x0558 -#define REG_BCNDMATIM_8192E 0x0559 -#define REG_ATIMWND_8192E 0x055A -#define REG_USTIME_TSF_8192E 0x055C -#define REG_BCN_MAX_ERR_8192E 0x055D -#define REG_RXTSF_OFFSET_CCK_8192E 0x055E -#define REG_RXTSF_OFFSET_OFDM_8192E 0x055F -#define REG_TSFTR_8192E 0x0560 -#define REG_CTWND_8192E 0x0572 -#define REG_SECONDARY_CCA_CTRL_8192E 0x0577 // ?????? -#define REG_PSTIMER_8192E 0x0580 -#define REG_TIMER0_8192E 0x0584 -#define REG_TIMER1_8192E 0x0588 -#define REG_ACMHWCTRL_8192E 0x05C0 -#define REG_SCH_TXCMD_8192E 0x05F8 - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -// gogogo -#define REG_MAC_CR_8192E 0x0600 -#define REG_TCR_8192E 0x0604 -#define REG_RCR_8192E 0x0608 -#define REG_RX_PKT_LIMIT_8192E 0x060C -#define REG_RX_DLK_TIME_8192E 0x060D -#define REG_RX_DRVINFO_SZ_8192E 0x060F - -#define REG_MACID_8192E 0x0610 -#define REG_BSSID_8192E 0x0618 -#define REG_MAR_8192E 0x0620 -#define REG_MBIDCAMCFG_8192E 0x0628 - -#define REG_USTIME_EDCA_8192E 0x0638 -#define REG_MAC_SPEC_SIFS_8192E 0x063A -#define REG_RESP_SIFP_CCK_8192E 0x063C -#define REG_RESP_SIFS_OFDM_8192E 0x063E -#define REG_ACKTO_8192E 0x0640 -#define REG_CTS2TO_8192E 0x0641 -#define REG_EIFS_8192E 0x0642 - -#define REG_NAV_UPPER_8192E 0x0652 // ?????? -#define REG_TRXPTCL_CTL_8192E 0x0668 - -// Security -#define REG_CAMCMD_8192E 0x0670 -#define REG_CAMWRITE_8192E 0x0674 -#define REG_CAMREAD_8192E 0x0678 -#define REG_CAMDBG_8192E 0x067C -#define REG_SECCFG_8192E 0x0680 - -// Power -#define REG_WOW_CTRL_8192E 0x0690 -#define REG_PS_RX_INFO_8192E 0x0692 -#define REG_UAPSD_TID_8192E 0x0693 -#define REG_WKFMCAM_NUM_8192E 0x0698 -#define REG_RXFLTMAP0_8192E 0x06A0 -#define REG_RXFLTMAP1_8192E 0x06A2 -#define REG_RXFLTMAP2_8192E 0x06A4 -#define REG_BCN_PSR_RPT_8192E 0x06A8 -#define REG_BT_COEX_TABLE0_8192E 0x06C0 -#define REG_BT_COEX_TABLE1_8192E 0x06C4 -#define REG_BT_COEX_TABLE2_8192E 0x06C8 -#define REG_BT_COEX_TABLE3_8192E 0x06CC -#define REG_ASSOCIATED_BFMER0_INFO_8192E 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO_8192E 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC - -// Hardware Port 2 -#define REG_MACID1_8192E 0x0700 -#define REG_BSSID1_8192E 0x0708 -#define REG_ASSOCIATED_BFMEE_SEL_8192E 0x0714 -#define REG_SND_PTCL_CTRL_8192E 0x0718 - -// BT -#define REG_BT_STATISTICS_CTRL_8192E 0x076E // bit0~bit3 for REG_BT_STATISTICS_CTRL , bit4~bit15 for REG_BT_COEX_ENH_INTF_CTRL -#define REG_BT_STATISTICS_OTH_CTRL_8192E 0x0778 -#define REG_TDMA_TIME_AND_RPT_SAM_SET_8192E 0x0790 - - -//----------------------------------------------------- -// -// Redifine 8192C register definition for compatibility -// -//----------------------------------------------------- - -// TODO: use these definition when using REG_xxx naming rule. -// NOTE: DO NOT Remove these definition. Use later. -#define EFUSE_CTRL_8192E REG_EFUSE_CTRL_8192E // E-Fuse Control. -#define EFUSE_TEST_8192E REG_LDO_EFUSE_CTRL_8192E // E-Fuse Test. -#define MSR_8192E (REG_CR_8192E + 2) // Media Status register -#define ISR_8192E REG_HISR0_8192E -#define TSFR_8192E REG_TSFTR_8192E // Timing Sync Function Timer Register. - -#define PBP_8192E REG_PBP_8192E - -// Redifine MACID register, to compatible prior ICs. -#define IDR0_8192E REG_MACID_8192E // MAC ID Register, Offset 0x0050-0x0053 -#define IDR4_8192E (REG_MACID_8192E + 4) // MAC ID Register, Offset 0x0054-0x0055 - - -// -// 9. Security Control Registers (Offset: ) -// -#define RWCAM_8192E REG_CAMCMD_8192E //IN 8190 Data Sheet is called CAMcmd -#define WCAMI_8192E REG_CAMWRITE_8192E // Software write CAM input content -#define RCAMO_8192E REG_CAMREAD_8192E // Software read/write CAM config -#define CAMDBG_8192E REG_CAMDBG_8192E -#define SECR_8192E REG_SECCFG_8192E //Security Configuration Register - -/* RSSI Dump Message */ -#define rA_RSSIDump_92E 0xcb0 -#define rB_RSSIDump_92E 0xcb1 -#define rS1_RXevmDump_92E 0xcb2 -#define rS2_RXevmDump_92E 0xcb3 -#define rA_RXsnrDump_92E 0xcb4 -#define rB_RXsnrDump_92E 0xcb5 -#define rA_CfoShortDump_92E 0xcb6 -#define rB_CfoShortDump_92E 0xcb8 -#define rA_CfoLongDump_92E 0xcba -#define rB_CfoLongDump_92E 0xcbc - -//---------------------------------------------------------------------------- -// 8195 IMR/ISR bits (offset 0xB0, 8bits) -//---------------------------------------------------------------------------- -#define IMR_DISABLED_8192E 0 -// IMR DW0(0x00B0-00B3) Bit 0-31 -#define IMR_TIMER2_8192E BIT31 // Timeout interrupt 2 -#define IMR_TIMER1_8192E BIT30 // Timeout interrupt 1 -#define IMR_PSTIMEOUT_8192E BIT29 // Power Save Time Out Interrupt -#define IMR_GTINT4_8192E BIT28 // When GTIMER4 expires, this bit is set to 1 -#define IMR_GTINT3_8192E BIT27 // When GTIMER3 expires, this bit is set to 1 -#define IMR_TXBCN0ERR_8192E BIT26 // Transmit Beacon0 Error -#define IMR_TXBCN0OK_8192E BIT25 // Transmit Beacon0 OK -#define IMR_TSF_BIT32_TOGGLE_8192E BIT24 // TSF Timer BIT32 toggle indication interrupt -#define IMR_BCNDMAINT0_8192E BIT20 // Beacon DMA Interrupt 0 -#define IMR_BCNDERR0_8192E BIT16 // Beacon Queue DMA OK0 -#define IMR_HSISR_IND_ON_INT_8192E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define IMR_BCNDMAINT_E_8192E BIT14 // Beacon DMA Interrupt Extension for Win7 -#define IMR_ATIMEND_8192E BIT12 // CTWidnow End or ATIM Window End -#define IMR_C2HCMD_8192E BIT10 // CPU to Host Command INT Status, Write 1 clear -#define IMR_CPWM2_8192E BIT9 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_CPWM_8192E BIT8 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_HIGHDOK_8192E BIT7 // High Queue DMA OK -#define IMR_MGNTDOK_8192E BIT6 // Management Queue DMA OK -#define IMR_BKDOK_8192E BIT5 // AC_BK DMA OK -#define IMR_BEDOK_8192E BIT4 // AC_BE DMA OK -#define IMR_VIDOK_8192E BIT3 // AC_VI DMA OK -#define IMR_VODOK_8192E BIT2 // AC_VO DMA OK -#define IMR_RDU_8192E BIT1 // Rx Descriptor Unavailable -#define IMR_ROK_8192E BIT0 // Receive DMA OK - -// IMR DW1(0x00B4-00B7) Bit 0-31 -#define IMR_BCNDMAINT7_8192E BIT27 // Beacon DMA Interrupt 7 -#define IMR_BCNDMAINT6_8192E BIT26 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5_8192E BIT25 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4_8192E BIT24 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3_8192E BIT23 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2_8192E BIT22 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1_8192E BIT21 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK7_8192E BIT20 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6_8192E BIT19 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5_8192E BIT18 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4_8192E BIT17 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3_8192E BIT16 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2_8192E BIT15 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1_8192E BIT14 // Beacon Queue DMA OK Interrup 1 -#define IMR_ATIMEND_E_8192E BIT13 // ATIM Window End Extension for Win7 -#define IMR_TXERR_8192E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. -#define IMR_RXERR_8192E BIT10 // Rx Error Flag INT Status, Write 1 clear -#define IMR_TXFOVW_8192E BIT9 // Transmit FIFO Overflow -#define IMR_RXFOVW_8192E BIT8 // Receive FIFO Overflow - - - -#define IMR_MCUERR_8192E BIT28 // Beacon DMA Interrupt 7 - - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ -//---------------------------------------------------------------------------- -// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- -/* -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopVO BIT3 -#define StopVI BIT2 -#define StopBE BIT1 -#define StopBK BIT0 -*/ - - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- -/*#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_HRPWM 0xFE58 -#define REG_USB_HCPWM 0xFE57 - -//2 USB Information (0xFE17) -#define USB_IS_HIGH_SPEED 0 -#define USB_IS_FULL_SPEED 1 -#define USB_SPEED_MASK BIT(5) - -#define USB_NORMAL_SIE_EP_MASK 0xF -#define USB_NORMAL_SIE_EP_SHIFT 4 - -//2 Special Option -#define USB_AGG_EN BIT(3) - -*/ -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -/* -//2 SYS_ISO_CTRL -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) -#define PWC_EV12V BIT(15) - - -//2 SYS_FUNC_EN -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) - -//2 APS_FSMCO -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) - -//2 SYS_CLKR -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) - - -//2 9346CR - -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - - -//2 RF_CTRL -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - -//2 LDOV12D_CTRL -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - - -//2 EFUSE_TEST (For RTL8723 partially) -#define EF_TRPT BIT(7) -#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 -#define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) -#define EFUSE_SEL_MASK 0x300 -#define EFUSE_WIFI_SEL_0 0x0 -#define EFUSE_BT_SEL_0 0x1 -#define EFUSE_BT_SEL_1 0x2 -#define EFUSE_BT_SEL_2 0x3 - - -//2 8051FWDL -//2 MCUFWDL -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define RAM_DL_SEL BIT(7) -#define ROM_DLEN BIT(19) -#define CPRST BIT(23) - - - -//2 REG_SYS_CFG -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define TRP_B15V_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define BT_FUNC BIT(16) -#define VENDOR_ID BIT(19) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) // RTL ID -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 -#define CHIP_VER_RTL_SHIFT 12 - -*/ -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -/* - -//2 Function Enable Registers -//2 CR 0x0100-0x0103 - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) -#define CALTMR_EN BIT(10) // 32k CAL TMR enable - -// Network type -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - - -//2 PBP - Page Size Register 0x0104 -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 - - -//2 TX/RXDMA 0x010C -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) - -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - - -//2 REG_C2HEVT_CLEAR 0x01AF -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - - - -//2 LLT_INIT 0x01E0 -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 - -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - -*/ -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -/* -//2 TDECTL 0x0208 -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - - -//2 TXDMA_OFFSET_CHK 0x020C -#define DROP_DATA_EN BIT(9) -*/ -//----------------------------------------------------- -// -// 0x0280h ~ 0x028Bh RX DMA Configuration -// -//----------------------------------------------------- -/* -//2 REG_RXDMA_CONTROL, 0x0286h - -// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before -// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. -#define RXPKT_RELEASE_POLL BIT(0) -// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in -// this bit. FW can start releasing packets after RXDMA entering idle mode. -#define RXDMA_IDLE BIT(1) -// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host -// completed, and stop DMA packet to host. RXDMA will then report Default: 0; -#define RW_RELEASE_EN BIT(2) -*/ -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -/* -//2 FWHW_TXQ_CTRL 0x0420 -#define EN_AMPDU_RTY_NEW BIT(7) - - -//2 REG_LIFECTRL_CTRL 0x0426 -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 - -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. - - -//2 SPEC SIFS 0x0428 -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) - -//2 RL 0x042A -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) -*/ - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -/* -//2 EDCA setting 0x050C -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - -//2 BCN_CTRL 0x0550 -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) - -//2 TxPause 0x0522 -#define STOP_BCNQ BIT(6) -*/ - - -//2 ACMHWCTRL 0x05C0 -#define AcmHw_HwEn_8192E BIT(0) -#define AcmHw_VoqEn_8192E BIT(1) -#define AcmHw_ViqEn_8192E BIT(2) -#define AcmHw_BeqEn_8192E BIT(3) -#define AcmHw_VoqStatus_8192E BIT(5) -#define AcmHw_ViqStatus_8192E BIT(6) -#define AcmHw_BeqStatus_8192E BIT(7) - - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -/* - -//2 TCR 0x0604 -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) -*/ - -//---------------------------------------------------------------------------- -// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) -//---------------------------------------------------------------------------- -/* -#define RCR_APPFCS BIT31 // WMAC append FCS after pauload -#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. -#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. -#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF -#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. -#define RCR_RSVD_BIT26 BIT26 // Reserved -*/ -#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload -/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. -#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. -#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. -*/ -/*#define RCR_RSVD_BIT19 BIT19 // Reserved -#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. -#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable. -#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable. -*/ -/*#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 -#define RCR_AMF BIT13 // Accept management type frame -#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. -#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). -*/ -/*#define RCR_AICV BIT9 // Accept ICV error packet -#define RCR_ACRC32 BIT8 // Accept CRC32 error packet -#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) -#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) -#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet -#define RCR_APWRMGT BIT5 // Accept power management packet -#define RCR_ADD3 BIT4 // Accept address 3 match packet -#define RCR_AB BIT3 // Accept broadcast packet -#define RCR_AM BIT2 // Accept multicast packet -#define RCR_APM BIT1 // Accept physical match packet -#define RCR_AAP BIT0 // Accept all unicast packet - -#define AAP BIT(0) -#define APM BIT(1) -#define AM BIT(2) -#define AB BIT(3) -#define ADD3 BIT(4) -#define APWRMGT BIT(5) -#define CBSSID BIT(6) -#define CBSSID_DATA BIT(6) -#define CBSSID_BCN BIT(7) -#define ACRC32 BIT(8) -#define AICV BIT(9) -#define ADF BIT(11) -#define ACF BIT(12) -#define AMF BIT(13) -#define HTC_LOC_CTRL BIT(14) -#define UC_DATA_EN BIT(16) -#define BM_DATA_EN BIT(17) -#define MFBEN BIT(22) -#define LSIGEN BIT(23) -#define EnMBID BIT(24) -#define APP_BASSN BIT(27) -#define APP_PHYSTS BIT(28) -#define APP_ICV BIT(29) -#define APP_MIC BIT(30) -*/ - -//---------------------------------------------------------------------------- -// 8195 CAM Config Setting (offset 0x680, 1 byte) -//---------------------------------------------------------------------------- -/* -#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key -#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key -#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption -#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption -#define SCR_SKByA2 BIT(4) //Search kEY BY A2 -#define SCR_NoSKMC BIT(5) //No Key Search Multicast -#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key -#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key - -#define CAM_NONE 0x0 -#define CAM_WEP40 0x01 -#define CAM_TKIP 0x02 -#define CAM_AES 0x04 -#define CAM_WEP104 0x05 -#define CAM_SMS4 0x6 - -#define TOTAL_CAM_ENTRY 32 -#define HALF_CAM_ENTRY 16 - -#define CAM_CONFIG_USEDK TRUE -#define CAM_CONFIG_NO_USEDK FALSE - - -#define SCR_UseDK 0x01 -#define SCR_TxSecEnable 0x02 -#define SCR_RxSecEnable 0x04 -*/ - - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration -// -//----------------------------------------------------- -/* -//SDIO host local register space mapping. -#define SDIO_LOCAL_MSK 0x0FFF -#define WLAN_IOREG_MSK 0x7FFF -#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] - -#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID -#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] -#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] -#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] -#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] -#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] -#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] - -//SDIO Tx Free Page Index -#define HI_QUEUE_IDX 0 -#define MID_QUEUE_IDX 1 -#define LOW_QUEUE_IDX 2 -#define PUBLIC_QUEUE_IDX 3 - -#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control -#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask -#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine -#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode -#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length -#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page -#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 -#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 -#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion -#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 -#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 -#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock -#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control -#define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always -#define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always - -#define SDIO_HIMR_DISABLED 0 - -// RTL8723/RTL8188E SDIO Host Interrupt Mask Register -#define SDIO_HIMR_RX_REQUEST_MSK BIT0 -#define SDIO_HIMR_AVAL_MSK BIT1 -#define SDIO_HIMR_TXERR_MSK BIT2 -#define SDIO_HIMR_RXERR_MSK BIT3 -#define SDIO_HIMR_TXFOVW_MSK BIT4 -#define SDIO_HIMR_RXFOVW_MSK BIT5 -#define SDIO_HIMR_TXBCNOK_MSK BIT6 -#define SDIO_HIMR_TXBCNERR_MSK BIT7 -#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 -#define SDIO_HIMR_C2HCMD_MSK BIT17 -#define SDIO_HIMR_CPWM1_MSK BIT18 -#define SDIO_HIMR_CPWM2_MSK BIT19 -#define SDIO_HIMR_HSISR_IND_MSK BIT20 -#define SDIO_HIMR_GTINT3_IND_MSK BIT21 -#define SDIO_HIMR_GTINT4_IND_MSK BIT22 -#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 -#define SDIO_HIMR_OCPINT_MSK BIT24 -#define SDIO_HIMR_ATIMEND_MSK BIT25 -#define SDIO_HIMR_ATIMEND_E_MSK BIT26 -#define SDIO_HIMR_CTWEND_MSK BIT27 - -//RTL8188E SDIO Specific -#define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 - -// SDIO Host Interrupt Service Routine -#define SDIO_HISR_RX_REQUEST BIT0 -#define SDIO_HISR_AVAL BIT1 -#define SDIO_HISR_TXERR BIT2 -#define SDIO_HISR_RXERR BIT3 -#define SDIO_HISR_TXFOVW BIT4 -#define SDIO_HISR_RXFOVW BIT5 -#define SDIO_HISR_TXBCNOK BIT6 -#define SDIO_HISR_TXBCNERR BIT7 -#define SDIO_HISR_BCNERLY_INT BIT16 -#define SDIO_HISR_C2HCMD BIT17 -#define SDIO_HISR_CPWM1 BIT18 -#define SDIO_HISR_CPWM2 BIT19 -#define SDIO_HISR_HSISR_IND BIT20 -#define SDIO_HISR_GTINT3_IND BIT21 -#define SDIO_HISR_GTINT4_IND BIT22 -#define SDIO_HISR_PSTIMEOUT BIT23 -#define SDIO_HISR_OCPINT BIT24 -#define SDIO_HISR_ATIMEND BIT25 -#define SDIO_HISR_ATIMEND_E BIT26 -#define SDIO_HISR_CTWEND BIT27 - -//RTL8188E SDIO Specific -#define SDIO_HISR_MCU_ERR BIT28 -#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 - - -// SDIO HCI Suspend Control Register -#define HCI_RESUME_PWR_RDY BIT1 -#define HCI_SUS_CTRL BIT0 - - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - #define MAX_TX_AGG_PACKET_NUMBER 0x8 -#else - #define MAX_TX_AGG_PACKET_NUMBER 0xFF -#endif - -*/ -#endif // #ifndef __INC_HAL8192EREG_H +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8192EREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8192EREG_H +#define __INC_HAL8192EREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8192E 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8192E 0x0002 // 2 Byte +#define REG_SYS_PW_CTRL_8192E 0x0004 // 4 Byte +#define REG_SYS_CLKR_8192E 0x0008 // 2 Byte +#define REG_SYS_EEPROM_CTRL_8192E 0x000A // 2 Byte +#define REG_EE_VPD_8192E 0x000C // 2 Byte +#define REG_SYS_SWR_CTRL1_8192E 0x0010 // 1 Byte +#define REG_SYS_SWR_CTRL2_8192E 0x0014 // 1 Byte +#define REG_SYS_SWR_CTRL3_8192E 0x0018 // 4 Byte +#define REG_RSV_CTRL_8192E 0x001C // 3 Byte +#define REG_RF_CTRL_8192E 0x001F // 1 Byte +#define REG_AFE_CTRL1_8192E 0x0024 // 4 Byte +#define REG_AFE_CTRL2_8192E 0x0028 // 4 Byte +#define REG_AFE_CTRL3_8192E 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8192E 0x0030 +#define REG_LDO_EFUSE_CTRL_8192E 0x0034 +#define REG_PWR_DATA_8192E 0x0038 +#define REG_CAL_TIMER_8192E 0x003C +#define REG_ACLK_MON_8192E 0x003E +#define REG_GPIO_MUXCFG_8192E 0x0040 +#define REG_GPIO_IO_SEL_8192E 0x0042 +#define REG_MAC_PINMUX_CFG_8192E 0x0043 // ?????? +#define REG_GPIO_PIN_CTRL_8192E 0x0044 +#define REG_GPIO_INTM_8192E 0x0048 +#define BIT_REG_LED_CFG_8192E 0x004C +#define REG_LEDCFG2_8192E 0x004E // ?????? +#define REG_FSIMR_8192E 0x0050 +#define REG_FSISR_8192E 0x0054 +#define REG_HSIMR_8192E 0x0058 +#define REG_HSISR_8192E 0x005c +#define REG_PAD_CTRL1_8192E 0x0064 +#define REG_WL_BT_PWR_CTRL_8192E 0x0068 +#define REG_SDM_DEBUG_8192E 0x006C +#define REG_SDIO_CTRL_8192E 0x0070 +#define REG_HCI_OPT_CTRL_8192E 0x0074 +#define REG_AFE_CTRL4_8192E 0x0078 +#define REG_8051FW_CTRL_8192E 0x0080 +#define REG_WLLPS_CTRL_8192E 0x0090 +#define REG_HIMR0_8192E 0x00B0 +#define REG_HISR0_8192E 0x00B4 +#define REG_HIMR1_8192E 0x00B8 +#define REG_HISR1_8192E 0x00BC +#define REG_PMC_DBG_CTRL2_8192E 0x00CC +#define REG_EFUSE_BURN_GNT_8192E 0x00CF +#define REG_SYS_CFG1_8192E 0x00F0 +#define REG_SYS_CFG2_8192E 0x00FC + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8192E 0x0100 +#define REG_PBP_8192E 0x0104 // ?????? +#define REG_PKT_BUFF_ACCESS_CTRL_8192E 0x0106 // ?????? +#define REG_TRXDMA_CTRL_8192E 0x010C +#define REG_TRXFF_BNDY_8192E 0x0114 +#define REG_RXFF_PTR_8192E 0x011C +#define REG_CPWM_8192E 0x012C +#define REG_FWIMR_8192E 0x0130 +#define REG_FWISR_8192E 0x0134 +#define REG_FTIMR_8192E 0x0138 +#define REG_PKTBUF_DBG_CTRL_8192E 0x0140 +#define REG_RXPKTBUF_CTRL_8192E 0x0142 // ?????? +#define REG_PKTBUF_DBG_DATA_L_8192E 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8192E 0x0148 + +#define REG_TC0_CTRL_8192E 0x0150 +#define REG_TC1_CTRL_8192E 0x0154 +#define REG_TC2_CTRL_8192E 0x0158 +#define REG_TC3_CTRL_8192E 0x015C +#define REG_TC4_CTRL_8192E 0x0160 +#define REG_TCUNIT_BASE_8192E 0x0164 +#define REG_RSVD3_8192E 0x0168 // ????? + +#define REG_C2HEVT_MSG_NORMAL_8192E 0x01A0 // ?????? +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ?????? +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ?????? +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ?????? +#define REG_C2HEVT_CLEAR_8192E 0x01AF // ?????? +#define REG_MCUTST_1_8192E 0x01C0 +#define REG_MCUTST_2_8192E 0x01C4 +#define REG_MCUTST_WOWLAN_8192E 0x01C7 // ?????? +#define REG_FMETHR_8192E 0x01C8 +#define REG_HMETFR_8192E 0x01CC +#define REG_HMEBOX_0_8192E 0x01D0 +#define REG_HMEBOX_1_8192E 0x01D4 +#define REG_HMEBOX_2_8192E 0x01D8 +#define REG_HMEBOX_3_8192E 0x01DC +#define REG_LLT_INIT_8192E 0x01E0 +#define REG_HMEBOX_EXT0_8192E 0x01F0 // ?????? +#define REG_HMEBOX_EXT1_8192E 0x01F4 // ?????? +#define REG_HMEBOX_EXT2_8192E 0x01F8 // ?????? +#define REG_HMEBOX_EXT3_8192E 0x01FC // ?????? + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8192E 0x0200 +#define REG_FIFOPAGE_8192E 0x0204 +#define REG_DWBCN0_CTRL_8192E 0x0208 +#define REG_TXDMA_OFFSET_CHK_8192E 0x020C +#define REG_TXDMA_STATUS_8192E 0x0210 +#define REG_RQPN_NPQ_8192E 0x0214 +#define REG_AUTO_LLT_8192E 0x0224 +#define REG_DWBCN1_CTRL_8192E 0x0228 + + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8192E 0x0280 +#define REG_RXPKT_NUM_8192E 0x0284 // The number of packets in RXPKTBUF. +#define REG_RXDMA_CONTROL_8192E 0x0286 // ?????? Control the RX DMA. +#define REG_RXDMA_STATUS_8192E 0x0288 +#define REG_RXDMA_PRO_8192E 0x0290 // ?????? +#define REG_EARLY_MODE_CONTROL_8192E 0x02BC // ?????? +#define REG_RSVD5_8192E 0x02F0 // ?????? + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8192E 0x0300 +#define REG_INT_MIG_8192E 0x0304 // Interrupt Migration +#define REG_BCNQ_TXBD_DESA_8192E 0x0308 // TX Beacon Descriptor Address +#define REG_MGQ_TXBD_DESA_8192E 0x0310 // TX Manage Queue Descriptor Address +#define REG_VOQ_TXBD_DESA_8192E 0x0318 // TX VO Queue Descriptor Address +#define REG_VIQ_TXBD_DESA_8192E 0x0320 // TX VI Queue Descriptor Address +#define REG_BEQ_TXBD_DESA_8192E 0x0328 // TX BE Queue Descriptor Address +#define REG_BKQ_TXBD_DESA_8192E 0x0330 // TX BK Queue Descriptor Address +#define REG_RXQ_RXBD_DESA_8192E 0x0338 // RX Queue Descriptor Address +#define REG_HI0Q_TXBD_DESA_8192E 0x0340 +#define REG_HI1Q_TXBD_DESA_8192E 0x0348 +#define REG_HI2Q_TXBD_DESA_8192E 0x0350 +#define REG_HI3Q_TXBD_DESA_8192E 0x0358 +#define REG_HI4Q_TXBD_DESA_8192E 0x0360 +#define REG_HI5Q_TXBD_DESA_8192E 0x0368 +#define REG_HI6Q_TXBD_DESA_8192E 0x0370 +#define REG_HI7Q_TXBD_DESA_8192E 0x0378 +#define REG_MGQ_TXBD_NUM_8192E 0x0380 +#define REG_RX_RXBD_NUM_8192E 0x0382 +#define REG_VOQ_TXBD_NUM_8192E 0x0384 +#define REG_VIQ_TXBD_NUM_8192E 0x0386 +#define REG_BEQ_TXBD_NUM_8192E 0x0388 +#define REG_BKQ_TXBD_NUM_8192E 0x038A +#define REG_HI0Q_TXBD_NUM_8192E 0x038C +#define REG_HI1Q_TXBD_NUM_8192E 0x038E +#define REG_HI2Q_TXBD_NUM_8192E 0x0390 +#define REG_HI3Q_TXBD_NUM_8192E 0x0392 +#define REG_HI4Q_TXBD_NUM_8192E 0x0394 +#define REG_HI5Q_TXBD_NUM_8192E 0x0396 +#define REG_HI6Q_TXBD_NUM_8192E 0x0398 +#define REG_HI7Q_TXBD_NUM_8192E 0x039A +#define REG_TSFTIMER_HCI_8192E 0x039C + +//Read Write Point +#define REG_VOQ_TXBD_IDX_8192E 0x03A0 +#define REG_VIQ_TXBD_IDX_8192E 0x03A4 +#define REG_BEQ_TXBD_IDX_8192E 0x03A8 +#define REG_BKQ_TXBD_IDX_8192E 0x03AC +#define REG_MGQ_TXBD_IDX_8192E 0x03B0 +#define REG_RXQ_TXBD_IDX_8192E 0x03B4 +#define REG_HI0Q_TXBD_IDX_8192E 0x03B8 +#define REG_HI1Q_TXBD_IDX_8192E 0x03BC +#define REG_HI2Q_TXBD_IDX_8192E 0x03C0 +#define REG_HI3Q_TXBD_IDX_8192E 0x03C4 +#define REG_HI4Q_TXBD_IDX_8192E 0x03C8 +#define REG_HI5Q_TXBD_IDX_8192E 0x03CC +#define REG_HI6Q_TXBD_IDX_8192E 0x03D0 +#define REG_HI7Q_TXBD_IDX_8192E 0x03D4 + +#define REG_PCIE_HCPWM_8192EE 0x03D8 // ?????? +#define REG_PCIE_HRPWM_8192EE 0x03DC //PCIe RPWM // ?????? +#define REG_DBI_WDATA_V1_8192E 0x03E8 +#define REG_DBI_RDATA_V1_8192E 0x03EC +#define REG_DBI_FLAG_V1_8192E 0x03F0 +#define REG_MDIO_V1_8192E 0x3F4 +#define REG_PCIE_MIX_CFG_8192E 0x3F8 + + + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_TXPKT_EMPTY_8192E 0x041A +#define REG_FWHW_TXQ_CTRL_8192E 0x0420 +#define REG_HWSEQ_CTRL_8192E 0x0423 +#define REG_BCNQ_BDNY_8192E 0x0424 +#define REG_MGQ_BDNY_8192E 0x0425 +#define REG_LIFETIME_EN_8192E 0x0426 +#define REG_FW_FREE_TAIL_8192E 0x0427 +#define REG_SPEC_SIFS_8192E 0x0428 +#define REG_RETRY_LIMIT_8192E 0x042A +#define REG_TXBF_CTRL_8192E 0x042C +#define REG_DARFRC_8192E 0x0430 +#define REG_RARFRC_8192E 0x0438 +#define REG_RRSR_8192E 0x0440 +#define REG_ARFR0_8192E 0x0444 +#define REG_ARFR1_8192E 0x044C +#define REG_CCK_CHECK_8192E 0x0454 +#define REG_AMPDU_MAX_TIME_8192E 0x0456 +#define REG_BCNQ1_BDNY_8192E 0x0457 +#define REG_AMPDU_MAX_LENGTH_8192E 0x0458 +#define REG_WMAC_LBK_BUF_HD_8192E 0x045D +#define REG_NDPA_OPT_CTRL_8192E 0x045F +#define REG_FAST_EDCA_CTRL_8192E 0x0460 +#define REG_RD_RESP_PKT_TH_8192E 0x0463 +#define REG_DATA_SC_8192E 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8192E 0x04B4 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8192E 0x04BC +#define REG_PKT_LIFE_TIME_8192E 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8192E 0x04C2 // ?????? + +#define REG_STBC_SETTING_8192E 0x04C4 +#define REG_PROT_MODE_CTRL_8192E 0x04C8 +#define REG_MAX_AGGR_NUM_8192E 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8192E 0x04CB +#define REG_BAR_MODE_CTRL_8192E 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8192E 0x04CF +#define REG_MACID_SLEEP2_8192E 0x04D0 +#define REG_MACID_SLEEP_8192E 0x04D4 +#define REG_HW_SEQ0_8192E 0x04D8 +#define REG_HW_SEQ1_8192E 0x04DA +#define REG_HW_SEQ2_8192E 0x04DC +#define REG_HW_SEQ3_8192E 0x04DE +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192E 0x045D // ?????? + + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +// gogogo +#define REG_EDCA_VO_PARAM_8192E 0x0500 +#define REG_EDCA_VI_PARAM_8192E 0x0504 +#define REG_EDCA_BE_PARAM_8192E 0x0508 +#define REG_EDCA_BK_PARAM_8192E 0x050C +#define REG_BCNTCFG_8192E 0x0510 +#define REG_PIFS_8192E 0x0512 +#define REG_RDG_PIFS_8192E 0x0513 +#define REG_SIFS_CTX_8192E 0x0514 +#define REG_SIFS_TRX_8192E 0x0516 +#define REG_AGGR_BREAK_TIME_8192E 0x051A +#define REG_SLOT_8192E 0x051B +#define REG_TX_PTCL_CTRL_8192E 0x0520 +#define REG_TXPAUSE_8192E 0x0522 +#define REG_DIS_TXREQ_CLR_8192E 0x0523 +#define REG_RD_CTRL_8192E 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8192E 0x0540 +#define REG_RD_NAV_NXT_8192E 0x0544 +#define REG_NAV_PROT_LEN_8192E 0x0546 +#define REG_BCN_CTRL_8192E 0x0550 +#define REG_BCN_CTRL_1_8192E 0x0551 +#define REG_MBID_NUM_8192E 0x0552 +#define REG_DUAL_TSF_RST_8192E 0x0553 +#define REG_MBSSID_BCN_SPACE_8192E 0x0554 +#define REG_DRVERLYINT_8192E 0x0558 +#define REG_BCNDMATIM_8192E 0x0559 +#define REG_ATIMWND_8192E 0x055A +#define REG_USTIME_TSF_8192E 0x055C +#define REG_BCN_MAX_ERR_8192E 0x055D +#define REG_RXTSF_OFFSET_CCK_8192E 0x055E +#define REG_RXTSF_OFFSET_OFDM_8192E 0x055F +#define REG_TSFTR_8192E 0x0560 +#define REG_CTWND_8192E 0x0572 +#define REG_SECONDARY_CCA_CTRL_8192E 0x0577 // ?????? +#define REG_PSTIMER_8192E 0x0580 +#define REG_TIMER0_8192E 0x0584 +#define REG_TIMER1_8192E 0x0588 +#define REG_ACMHWCTRL_8192E 0x05C0 +#define REG_SCH_TXCMD_8192E 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +// gogogo +#define REG_MAC_CR_8192E 0x0600 +#define REG_TCR_8192E 0x0604 +#define REG_RCR_8192E 0x0608 +#define REG_RX_PKT_LIMIT_8192E 0x060C +#define REG_RX_DLK_TIME_8192E 0x060D +#define REG_RX_DRVINFO_SZ_8192E 0x060F + +#define REG_MACID_8192E 0x0610 +#define REG_BSSID_8192E 0x0618 +#define REG_MAR_8192E 0x0620 +#define REG_MBIDCAMCFG_8192E 0x0628 + +#define REG_USTIME_EDCA_8192E 0x0638 +#define REG_MAC_SPEC_SIFS_8192E 0x063A +#define REG_RESP_SIFP_CCK_8192E 0x063C +#define REG_RESP_SIFS_OFDM_8192E 0x063E +#define REG_ACKTO_8192E 0x0640 +#define REG_CTS2TO_8192E 0x0641 +#define REG_EIFS_8192E 0x0642 + +#define REG_NAV_UPPER_8192E 0x0652 // ?????? +#define REG_TRXPTCL_CTL_8192E 0x0668 + +// Security +#define REG_CAMCMD_8192E 0x0670 +#define REG_CAMWRITE_8192E 0x0674 +#define REG_CAMREAD_8192E 0x0678 +#define REG_CAMDBG_8192E 0x067C +#define REG_SECCFG_8192E 0x0680 + +// Power +#define REG_WOW_CTRL_8192E 0x0690 +#define REG_PS_RX_INFO_8192E 0x0692 +#define REG_UAPSD_TID_8192E 0x0693 +#define REG_WKFMCAM_NUM_8192E 0x0698 +#define REG_RXFLTMAP0_8192E 0x06A0 +#define REG_RXFLTMAP1_8192E 0x06A2 +#define REG_RXFLTMAP2_8192E 0x06A4 +#define REG_BCN_PSR_RPT_8192E 0x06A8 +#define REG_BT_COEX_TABLE0_8192E 0x06C0 +#define REG_BT_COEX_TABLE1_8192E 0x06C4 +#define REG_BT_COEX_TABLE2_8192E 0x06C8 +#define REG_BT_COEX_TABLE3_8192E 0x06CC +#define REG_ASSOCIATED_BFMER0_INFO_8192E 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO_8192E 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8192E 0x0700 +#define REG_BSSID1_8192E 0x0708 +#define REG_ASSOCIATED_BFMEE_SEL_8192E 0x0714 +#define REG_SND_PTCL_CTRL_8192E 0x0718 + +// BT +#define REG_BT_STATISTICS_CTRL_8192E 0x076E // bit0~bit3 for REG_BT_STATISTICS_CTRL , bit4~bit15 for REG_BT_COEX_ENH_INTF_CTRL +#define REG_BT_STATISTICS_OTH_CTRL_8192E 0x0778 +#define REG_TDMA_TIME_AND_RPT_SAM_SET_8192E 0x0790 + + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8192E REG_EFUSE_CTRL_8192E // E-Fuse Control. +#define EFUSE_TEST_8192E REG_LDO_EFUSE_CTRL_8192E // E-Fuse Test. +#define MSR_8192E (REG_CR_8192E + 2) // Media Status register +#define ISR_8192E REG_HISR0_8192E +#define TSFR_8192E REG_TSFTR_8192E // Timing Sync Function Timer Register. + +#define PBP_8192E REG_PBP_8192E + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8192E REG_MACID_8192E // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8192E (REG_MACID_8192E + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8192E REG_CAMCMD_8192E //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8192E REG_CAMWRITE_8192E // Software write CAM input content +#define RCAMO_8192E REG_CAMREAD_8192E // Software read/write CAM config +#define CAMDBG_8192E REG_CAMDBG_8192E +#define SECR_8192E REG_SECCFG_8192E //Security Configuration Register + +/* RSSI Dump Message */ +#define rA_RSSIDump_92E 0xcb0 +#define rB_RSSIDump_92E 0xcb1 +#define rS1_RXevmDump_92E 0xcb2 +#define rS2_RXevmDump_92E 0xcb3 +#define rA_RXsnrDump_92E 0xcb4 +#define rB_RXsnrDump_92E 0xcb5 +#define rA_CfoShortDump_92E 0xcb6 +#define rB_CfoShortDump_92E 0xcb8 +#define rA_CfoLongDump_92E 0xcba +#define rB_CfoLongDump_92E 0xcbc + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8192E 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8192E BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8192E BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8192E BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8192E BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8192E BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8192E BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8192E BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8192E BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8192E BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8192E BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8192E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8192E BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8192E BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8192E BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8192E BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8192E BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8192E BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8192E BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8192E BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8192E BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8192E BIT3 // AC_VI DMA OK +#define IMR_VODOK_8192E BIT2 // AC_VO DMA OK +#define IMR_RDU_8192E BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8192E BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8192E BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8192E BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8192E BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8192E BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8192E BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8192E BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8192E BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8192E BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8192E BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8192E BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8192E BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8192E BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8192E BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8192E BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8192E BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8192E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8192E BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8192E BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8192E BIT8 // Receive FIFO Overflow + + + +#define IMR_MCUERR_8192E BIT28 // Beacon DMA Interrupt 7 + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +/*#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +//2 USB Information (0xFE17) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +//2 Special Option +#define USB_AGG_EN BIT(3) + +*/ +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8192E BIT(0) +#define AcmHw_VoqEn_8192E BIT(1) +#define AcmHw_ViqEn_8192E BIT(2) +#define AcmHw_BeqEn_8192E BIT(3) +#define AcmHw_VoqStatus_8192E BIT(5) +#define AcmHw_ViqStatus_8192E BIT(6) +#define AcmHw_BeqStatus_8192E BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload +/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. +#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. +#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. +*/ +/*#define RCR_RSVD_BIT19 BIT19 // Reserved +#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. +#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable. +#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable. +*/ +/*#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 +#define RCR_AMF BIT13 // Accept management type frame +#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. +#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). +*/ +/*#define RCR_AICV BIT9 // Accept ICV error packet +#define RCR_ACRC32 BIT8 // Accept CRC32 error packet +#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) +#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) +#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet +#define RCR_APWRMGT BIT5 // Accept power management packet +#define RCR_ADD3 BIT4 // Accept address 3 match packet +#define RCR_AB BIT3 // Accept broadcast packet +#define RCR_AM BIT2 // Accept multicast packet +#define RCR_APM BIT1 // Accept physical match packet +#define RCR_AAP BIT0 // Accept all unicast packet + +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +*/ + +//---------------------------------------------------------------------------- +// 8195 CAM Config Setting (offset 0x680, 1 byte) +//---------------------------------------------------------------------------- +/* +#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key +#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key +#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption +#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption +#define SCR_SKByA2 BIT(4) //Search kEY BY A2 +#define SCR_NoSKMC BIT(5) //No Key Search Multicast +#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key +#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK TRUE +#define CAM_CONFIG_NO_USEDK FALSE + + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 +*/ + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration +// +//----------------------------------------------------- +/* +//SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SDIO Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control +#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask +#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine +#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode +#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control +#define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always +#define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always + +#define SDIO_HIMR_DISABLED 0 + +// RTL8723/RTL8188E SDIO Host Interrupt Mask Register +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +// SDIO Host Interrupt Service Routine +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIMEOUT BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + + +// SDIO HCI Suspend Control Register +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + #define MAX_TX_AGG_PACKET_NUMBER 0x8 +#else + #define MAX_TX_AGG_PACKET_NUMBER 0xFF +#endif + +*/ +#endif // #ifndef __INC_HAL8192EREG_H diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.c index aa02f379b44..968e4443a1d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.c @@ -1,1423 +1,1423 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8192E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_AGC_TAB[] = { - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFB010001, - 0xC78, 0xFA020001, - 0xC78, 0xF9030001, - 0xC78, 0xF8040001, - 0xC78, 0xF7050001, - 0xC78, 0xF6060001, - 0xC78, 0xF5070001, - 0xC78, 0xF4080001, - 0xC78, 0xF3090001, - 0xC78, 0xF20A0001, - 0xC78, 0xF10B0001, - 0xC78, 0xF00C0001, - 0xC78, 0xEF0D0001, - 0xC78, 0xEE0E0001, - 0xC78, 0xED0F0001, - 0xC78, 0xEC100001, - 0xC78, 0xEB110001, - 0xC78, 0xEA120001, - 0xC78, 0xE9130001, - 0xC78, 0xE8140001, - 0xC78, 0xE7150001, - 0xC78, 0xE6160001, - 0xC78, 0xE5170001, - 0xC78, 0xE4180001, - 0xC78, 0xE3190001, - 0xC78, 0xE21A0001, - 0xC78, 0xE11B0001, - 0xC78, 0x8A1C0001, - 0xC78, 0x891D0001, - 0xC78, 0x881E0001, - 0xC78, 0x871F0001, - 0xC78, 0x86200001, - 0xC78, 0x85210001, - 0xC78, 0x84220001, - 0xC78, 0x83230001, - 0xC78, 0x82240001, - 0xC78, 0x6A250001, - 0xC78, 0x69260001, - 0xC78, 0x68270001, - 0xC78, 0x67280001, - 0xC78, 0x66290001, - 0xC78, 0x652A0001, - 0xC78, 0x642B0001, - 0xC78, 0x632C0001, - 0xC78, 0x622D0001, - 0xC78, 0x612E0001, - 0xC78, 0x602F0001, - 0xC78, 0x47300001, - 0xC78, 0x46310001, - 0xC78, 0x45320001, - 0xC78, 0x44330001, - 0xC78, 0x43340001, - 0xC78, 0x42350001, - 0xC78, 0x41360001, - 0xC78, 0x40370001, - 0xC78, 0x40380001, - 0xC78, 0x40390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0xC78, 0x403F0001, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFB010001, - 0xC78, 0xFB020001, - 0xC78, 0xFB030001, - 0xC78, 0xFA040001, - 0xC78, 0xF9050001, - 0xC78, 0xF8060001, - 0xC78, 0xF7070001, - 0xC78, 0xF6080001, - 0xC78, 0xF5090001, - 0xC78, 0xF40A0001, - 0xC78, 0xF30B0001, - 0xC78, 0xF20C0001, - 0xC78, 0xF10D0001, - 0xC78, 0xF00E0001, - 0xC78, 0xEF0F0001, - 0xC78, 0xEE100001, - 0xC78, 0xED110001, - 0xC78, 0xEC120001, - 0xC78, 0xEB130001, - 0xC78, 0xEA140001, - 0xC78, 0xE9150001, - 0xC78, 0xE8160001, - 0xC78, 0xE7170001, - 0xC78, 0xE6180001, - 0xC78, 0xE5190001, - 0xC78, 0xE41A0001, - 0xC78, 0xE31B0001, - 0xC78, 0xE21C0001, - 0xC78, 0xE11D0001, - 0xC78, 0x8A1E0001, - 0xC78, 0x891F0001, - 0xC78, 0x88200001, - 0xC78, 0x87210001, - 0xC78, 0x86220001, - 0xC78, 0x85230001, - 0xC78, 0x84240001, - 0xC78, 0x83250001, - 0xC78, 0x82260001, - 0xC78, 0x6A270001, - 0xC78, 0x69280001, - 0xC78, 0x68290001, - 0xC78, 0x672A0001, - 0xC78, 0x662B0001, - 0xC78, 0x652C0001, - 0xC78, 0x642D0001, - 0xC78, 0x632E0001, - 0xC78, 0x622F0001, - 0xC78, 0x61300001, - 0xC78, 0x60310001, - 0xC78, 0x47320001, - 0xC78, 0x46330001, - 0xC78, 0x45340001, - 0xC78, 0x44350001, - 0xC78, 0x43360001, - 0xC78, 0x42370001, - 0xC78, 0x41380001, - 0xC78, 0x40390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0xC78, 0x403F0001, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFB010001, - 0xC78, 0xFB020001, - 0xC78, 0xFB030001, - 0xC78, 0xFB040001, - 0xC78, 0xFA050001, - 0xC78, 0xF9060001, - 0xC78, 0xF8070001, - 0xC78, 0xF7080001, - 0xC78, 0xF6090001, - 0xC78, 0xF50A0001, - 0xC78, 0xF40B0001, - 0xC78, 0xF30C0001, - 0xC78, 0xF20D0001, - 0xC78, 0xF10E0001, - 0xC78, 0xF00F0001, - 0xC78, 0xEF100001, - 0xC78, 0xEE110001, - 0xC78, 0xED120001, - 0xC78, 0xEC130001, - 0xC78, 0xEB140001, - 0xC78, 0xEA150001, - 0xC78, 0xE9160001, - 0xC78, 0xE8170001, - 0xC78, 0xE7180001, - 0xC78, 0xE6190001, - 0xC78, 0xE51A0001, - 0xC78, 0xE41B0001, - 0xC78, 0xE31C0001, - 0xC78, 0xE21D0001, - 0xC78, 0xE11E0001, - 0xC78, 0x8A1F0001, - 0xC78, 0x89200001, - 0xC78, 0x88210001, - 0xC78, 0x87220001, - 0xC78, 0x86230001, - 0xC78, 0x85240001, - 0xC78, 0x84250001, - 0xC78, 0x83260001, - 0xC78, 0x82270001, - 0xC78, 0x6A280001, - 0xC78, 0x69290001, - 0xC78, 0x682A0001, - 0xC78, 0x672B0001, - 0xC78, 0x662C0001, - 0xC78, 0x652D0001, - 0xC78, 0x642E0001, - 0xC78, 0x632F0001, - 0xC78, 0x62300001, - 0xC78, 0x61310001, - 0xC78, 0x60320001, - 0xC78, 0x47330001, - 0xC78, 0x46340001, - 0xC78, 0x45350001, - 0xC78, 0x44360001, - 0xC78, 0x43370001, - 0xC78, 0x42380001, - 0xC78, 0x41390001, - 0xC78, 0x403A0001, - 0xC78, 0x403B0001, - 0xC78, 0x403C0001, - 0xC78, 0x403D0001, - 0xC78, 0x403E0001, - 0xC78, 0x403F0001, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0xC78, 0xFB000001, - 0xC78, 0xFB010001, - 0xC78, 0xFB020001, - 0xC78, 0xFB030001, - 0xC78, 0xFB040001, - 0xC78, 0xFB050001, - 0xC78, 0xFA060001, - 0xC78, 0xF9070001, - 0xC78, 0xF8080001, - 0xC78, 0xF7090001, - 0xC78, 0xF60A0001, - 0xC78, 0xF50B0001, - 0xC78, 0xF40C0001, - 0xC78, 0xF30D0001, - 0xC78, 0xF20E0001, - 0xC78, 0xF10F0001, - 0xC78, 0xF0100001, - 0xC78, 0xEF110001, - 0xC78, 0xEE120001, - 0xC78, 0xED130001, - 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0xC78, 0xF74A0001, - 0xC78, 0xF64B0001, - 0xC78, 0xF54C0001, - 0xC78, 0xF44D0001, - 0xC78, 0xF34E0001, - 0xC78, 0xF24F0001, - 0xC78, 0xF1500001, - 0xC78, 0xF0510001, - 0xC78, 0xEF520001, - 0xC78, 0xEE530001, - 0xC78, 0xED540001, - 0xC78, 0xEC550001, - 0xC78, 0xEB560001, - 0xC78, 0xEA570001, - 0xC78, 0xE9580001, - 0xC78, 0xE8590001, - 0xC78, 0xE75A0001, - 0xC78, 0xE65B0001, - 0xC78, 0xE55C0001, - 0xC78, 0xE45D0001, - 0xC78, 0xE35E0001, - 0xC78, 0xE25F0001, - 0xC78, 0xE1600001, - 0xC78, 0x8A610001, - 0xC78, 0x89620001, - 0xC78, 0x88630001, - 0xC78, 0x87640001, - 0xC78, 0x86650001, - 0xC78, 0x85660001, - 0xC78, 0x84670001, - 0xC78, 0x83680001, - 0xC78, 0x82690001, - 0xC78, 0x6B6A0001, - 0xC78, 0x6A6B0001, - 0xC78, 0x696C0001, - 0xC78, 0x686D0001, - 0xC78, 0x676E0001, - 0xC78, 0x666F0001, - 0xC78, 0x65700001, - 0xC78, 0x64710001, - 0xC78, 0x63720001, - 0xC78, 0x62730001, - 0xC78, 0x61740001, - 0xC78, 0x49750001, - 0xC78, 0x48760001, - 0xC78, 0x47770001, - 0xC78, 0x46780001, - 0xC78, 0x45790001, - 0xC78, 0x447A0001, - 0xC78, 0x437B0001, - 0xC78, 0x427C0001, - 0xC78, 0x417D0001, - 0xC78, 0x407E0001, - 0xC78, 0x407F0001, - 0xC50, 0x00040020, - 0xC58, 0x00000020, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8192E_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8192E_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8192E(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8192E_AGC_TAB(void) -{ - return 58; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_PHY_REG[] = { - 0x800, 0x80040000, - 0x804, 0x00000003, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x02220385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x824, 0x00390004, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x824, 0x00390004, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x824, 0x00390004, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x824, 0x00390004, - 0xA0000000, 0x00000000, - 0x824, 0x00390204, - 0xB0000000, 0x00000000, - 0x828, 0x01000100, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x82C, 0x00390004, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x82C, 0x00390004, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x82C, 0x00390004, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x82C, 0x00390004, - 0xA0000000, 0x00000000, - 0x82C, 0x00390204, - 0xB0000000, 0x00000000, - 0x830, 0x32323232, - 0x834, 0x30303030, - 0x838, 0x30303030, - 0x83C, 0x30303030, - 0x840, 0x00010000, - 0x844, 0x00010000, - 0x848, 0x28282828, - 0x84C, 0x28282828, - 0x850, 0x00000000, - 0x854, 0x00000000, - 0x858, 0x009A009A, - 0x85C, 0x01000014, - 0x860, 0x66F60000, - 0x864, 0x061F0000, - 0x868, 0x30303030, - 0x86C, 0x30303030, - 0x870, 0x00000000, - 0x874, 0x55004200, - 0x878, 0x08080808, - 0x87C, 0x00000000, - 0x880, 0xB0000C1C, - 0x884, 0x00000001, - 0x888, 0x00000000, - 0x88C, 0xCC0000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121313, - 0x910, 0x806C0001, - 0x914, 0x00000001, - 0x918, 0x00000000, - 0x91C, 0x00010000, - 0x924, 0x00000001, - 0x928, 0x00000000, - 0x92C, 0x00000000, - 0x930, 0x00000000, - 0x934, 0x00000000, - 0x938, 0x00000000, - 0x93C, 0x00000000, - 0x940, 0x00000000, - 0x944, 0x00000000, - 0x94C, 0x00000008, - 0xA00, 0x00D047C8, - 0xA04, 0x81FF800C, - 0xA08, 0x8C838300, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0xA0C, 0x2E30120F, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xA0C, 0x2E30120F, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0xA0C, 0x2E30120F, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0xA0C, 0x2E30120F, - 0xA0000000, 0x00000000, - 0xA0C, 0x2E68120F, - 0xB0000000, 0x00000000, - 0xA10, 0x95009B78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x12130000, - 0xA24, 0x060A0D10, - 0xA28, 0x00000103, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xA20, 0x12130000, - 0xA24, 0x060A0D10, - 0xA28, 0x00000103, - 0xA0000000, 0x00000000, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0xB0000000, 0x00000000, - 0xA2C, 0x00D30000, - 0xA70, 0x101FFF80, - 0xA74, 0x00000007, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0xA80, 0x21807531, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xA80, 0x21807531, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0xA80, 0x21807531, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0xA80, 0x21807531, - 0xA0000000, 0x00000000, - 0xA80, 0x218075B1, - 0xB0000000, 0x00000000, - 0xB38, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05633, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x08800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9AC47, - 0xC34, 0x469652AF, - 0xC38, 0x49795994, - 0xC3C, 0x0A97971C, - 0xC40, 0x1F7C403F, - 0xC44, 0x000100B7, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0xA0000000, 0x00000000, - 0xC50, 0x00340020, - 0xB0000000, 0x00000000, - 0xC54, 0x0080801F, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0xA0000000, 0x00000000, - 0xC58, 0x00000020, - 0xB0000000, 0x00000000, - 0xC5C, 0x00248492, - 0xC60, 0x00000000, - 0xC64, 0x2112848B, - 0xC68, 0x47C00BFF, - 0xC6C, 0x00000036, - 0xC70, 0x00000600, - 0xC74, 0x02013269, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x2D4000B5, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x2D4000B5, - 0xA0000000, 0x00000000, - 0xC80, 0x40000100, - 0xB0000000, 0x00000000, - 0xC84, 0x21F60000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x2D4000B5, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x2D4000B5, - 0xA0000000, 0x00000000, - 0xC88, 0x40000100, - 0xB0000000, 0x00000000, - 0xC8C, 0xA0E40000, - 0xC90, 0x00121820, - 0xC94, 0x00000000, - 0xC98, 0x00121820, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00000000, - 0xCA4, 0x000300A0, - 0xCA8, 0x00000000, - 0xCAC, 0x00000000, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x00222222, - 0xCE4, 0x00040000, - 0xCE8, 0x77644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x00080740, - 0xD04, 0x00020403, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC43, - 0xD18, 0x7A8F5B6B, - 0xD1C, 0x0000007F, - 0xD2C, 0xCC979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x00000000, - 0xD3C, 0x00127353, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xD6C, 0x2A201C16, - 0xD70, 0x1812362E, - 0xD74, 0x322C2220, - 0xD78, 0x000E3C24, - 0xD80, 0x01081008, - 0xD84, 0x00000800, - 0xD88, 0xF0B50000, - 0xE00, 0x30303030, - 0xE04, 0x30303030, - 0xE08, 0x03903030, - 0xE10, 0x30303030, - 0xE14, 0x30303030, - 0xE18, 0x30303030, - 0xE1C, 0x30303030, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000048, - 0xE68, 0x0FC05656, - 0xE6C, 0x03C09696, - 0xE70, 0x03C09696, - 0xE74, 0x0C005656, - 0xE78, 0x0C005656, - 0xE7C, 0x0C005656, - 0xE80, 0x0C005656, - 0xE84, 0x03C09696, - 0xE88, 0x0C005656, - 0xE8C, 0x03C09696, - 0xED0, 0x03C09696, - 0xED4, 0x03C09696, - 0xED8, 0x03C09696, - 0xEDC, 0x0000D6D6, - 0xEE0, 0x0000D6D6, - 0xEEC, 0x0FC01616, - 0xEE4, 0xB0000C1C, - 0xEE8, 0x00000001, - 0xF14, 0x00000003, - 0xF4C, 0x00000000, - 0xF00, 0x00000300, - -}; - -void -ODM_ReadAndConfig_MP_8192E_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8192E_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8192E(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8192E_PHY_REG(void) -{ - return 58; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, - 0, 0, 1, 0x00000e08, 0x0000ff00, 0x00003200, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, - 0, 0, 1, 0x0000086c, 0xffffff00, 0x32323200, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x36364040, - 0, 0, 1, 0x00000e00, 0xffffffff, 0x34343636, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28283234, - 0, 0, 1, 0x00000e04, 0xffffffff, 0x28283032, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x38383840, - 0, 0, 1, 0x00000e10, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26283038, - 0, 0, 1, 0x00000e14, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000e18, 0xffffffff, 0x36384040, - 0, 0, 1, 0x00000e1c, 0xffffffff, 0x24262832, - 0, 1, 0, 0x00000838, 0xffffff00, 0x32323200, - 0, 1, 1, 0x00000838, 0xffffff00, 0x32323200, - 0, 1, 0, 0x0000086c, 0x000000ff, 0x00000032, - 0, 1, 1, 0x0000086c, 0x000000ff, 0x00000032, - 0, 1, 0, 0x00000830, 0xffffffff, 0x36364040, - 0, 1, 1, 0x00000830, 0xffffffff, 0x34343636, - 0, 1, 0, 0x00000834, 0xffffffff, 0x28283234, - 0, 1, 1, 0x00000834, 0xffffffff, 0x28283032, - 0, 1, 0, 0x0000083c, 0xffffffff, 0x38383840, - 0, 1, 1, 0x0000083c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000848, 0xffffffff, 0x26283038, - 0, 1, 1, 0x00000848, 0xffffffff, 0x26283032, - 0, 1, 1, 0x0000084c, 0xffffffff, 0x36384040, - 0, 1, 1, 0x00000868, 0xffffffff, 0x24262832 -}; - -void -ODM_ReadAndConfig_MP_8192E_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8192E_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8192E(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8192E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_AGC_TAB[] = { + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFA020001, + 0xC78, 0xF9030001, + 0xC78, 0xF8040001, + 0xC78, 0xF7050001, + 0xC78, 0xF6060001, + 0xC78, 0xF5070001, + 0xC78, 0xF4080001, + 0xC78, 0xF3090001, + 0xC78, 0xF20A0001, + 0xC78, 0xF10B0001, + 0xC78, 0xF00C0001, + 0xC78, 0xEF0D0001, + 0xC78, 0xEE0E0001, + 0xC78, 0xED0F0001, + 0xC78, 0xEC100001, + 0xC78, 0xEB110001, + 0xC78, 0xEA120001, + 0xC78, 0xE9130001, + 0xC78, 0xE8140001, + 0xC78, 0xE7150001, + 0xC78, 0xE6160001, + 0xC78, 0xE5170001, + 0xC78, 0xE4180001, + 0xC78, 0xE3190001, + 0xC78, 0xE21A0001, + 0xC78, 0xE11B0001, + 0xC78, 0x8A1C0001, + 0xC78, 0x891D0001, + 0xC78, 0x881E0001, + 0xC78, 0x871F0001, + 0xC78, 0x86200001, + 0xC78, 0x85210001, + 0xC78, 0x84220001, + 0xC78, 0x83230001, + 0xC78, 0x82240001, + 0xC78, 0x6A250001, + 0xC78, 0x69260001, + 0xC78, 0x68270001, + 0xC78, 0x67280001, + 0xC78, 0x66290001, + 0xC78, 0x652A0001, + 0xC78, 0x642B0001, + 0xC78, 0x632C0001, + 0xC78, 0x622D0001, + 0xC78, 0x612E0001, + 0xC78, 0x602F0001, + 0xC78, 0x47300001, + 0xC78, 0x46310001, + 0xC78, 0x45320001, + 0xC78, 0x44330001, + 0xC78, 0x43340001, + 0xC78, 0x42350001, + 0xC78, 0x41360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFA040001, + 0xC78, 0xF9050001, + 0xC78, 0xF8060001, + 0xC78, 0xF7070001, + 0xC78, 0xF6080001, + 0xC78, 0xF5090001, + 0xC78, 0xF40A0001, + 0xC78, 0xF30B0001, + 0xC78, 0xF20C0001, + 0xC78, 0xF10D0001, + 0xC78, 0xF00E0001, + 0xC78, 0xEF0F0001, + 0xC78, 0xEE100001, + 0xC78, 0xED110001, + 0xC78, 0xEC120001, + 0xC78, 0xEB130001, + 0xC78, 0xEA140001, + 0xC78, 0xE9150001, + 0xC78, 0xE8160001, + 0xC78, 0xE7170001, + 0xC78, 0xE6180001, + 0xC78, 0xE5190001, + 0xC78, 0xE41A0001, + 0xC78, 0xE31B0001, + 0xC78, 0xE21C0001, + 0xC78, 0xE11D0001, + 0xC78, 0x8A1E0001, + 0xC78, 0x891F0001, + 0xC78, 0x88200001, + 0xC78, 0x87210001, + 0xC78, 0x86220001, + 0xC78, 0x85230001, + 0xC78, 0x84240001, + 0xC78, 0x83250001, + 0xC78, 0x82260001, + 0xC78, 0x6A270001, + 0xC78, 0x69280001, + 0xC78, 0x68290001, + 0xC78, 0x672A0001, + 0xC78, 0x662B0001, + 0xC78, 0x652C0001, + 0xC78, 0x642D0001, + 0xC78, 0x632E0001, + 0xC78, 0x622F0001, + 0xC78, 0x61300001, + 0xC78, 0x60310001, + 0xC78, 0x47320001, + 0xC78, 0x46330001, + 0xC78, 0x45340001, + 0xC78, 0x44350001, + 0xC78, 0x43360001, + 0xC78, 0x42370001, + 0xC78, 0x41380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xC78, 0xFA050001, + 0xC78, 0xF9060001, + 0xC78, 0xF8070001, + 0xC78, 0xF7080001, + 0xC78, 0xF6090001, + 0xC78, 0xF50A0001, + 0xC78, 0xF40B0001, + 0xC78, 0xF30C0001, + 0xC78, 0xF20D0001, + 0xC78, 0xF10E0001, + 0xC78, 0xF00F0001, + 0xC78, 0xEF100001, + 0xC78, 0xEE110001, + 0xC78, 0xED120001, + 0xC78, 0xEC130001, + 0xC78, 0xEB140001, + 0xC78, 0xEA150001, + 0xC78, 0xE9160001, + 0xC78, 0xE8170001, + 0xC78, 0xE7180001, + 0xC78, 0xE6190001, + 0xC78, 0xE51A0001, + 0xC78, 0xE41B0001, + 0xC78, 0xE31C0001, + 0xC78, 0xE21D0001, + 0xC78, 0xE11E0001, + 0xC78, 0x8A1F0001, + 0xC78, 0x89200001, + 0xC78, 0x88210001, + 0xC78, 0x87220001, + 0xC78, 0x86230001, + 0xC78, 0x85240001, + 0xC78, 0x84250001, + 0xC78, 0x83260001, + 0xC78, 0x82270001, + 0xC78, 0x6A280001, + 0xC78, 0x69290001, + 0xC78, 0x682A0001, + 0xC78, 0x672B0001, + 0xC78, 0x662C0001, + 0xC78, 0x652D0001, + 0xC78, 0x642E0001, + 0xC78, 0x632F0001, + 0xC78, 0x62300001, + 0xC78, 0x61310001, + 0xC78, 0x60320001, + 0xC78, 0x47330001, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xE51B0001, + 0xC78, 0xE41C0001, + 0xC78, 0xE31D0001, + 0xC78, 0xE21E0001, + 0xC78, 0xE11F0001, + 0xC78, 0x8A200001, + 0xC78, 0x89210001, + 0xC78, 0x88220001, + 0xC78, 0x87230001, + 0xC78, 0x86240001, + 0xC78, 0x85250001, + 0xC78, 0x84260001, + 0xC78, 0x83270001, + 0xC78, 0x82280001, + 0xC78, 0x6A290001, + 0xC78, 0x692A0001, + 0xC78, 0x682B0001, + 0xC78, 0x672C0001, + 0xC78, 0x662D0001, + 0xC78, 0x652E0001, + 0xC78, 0x642F0001, + 0xC78, 0x63300001, + 0xC78, 0x62310001, + 0xC78, 0x61320001, + 0xC78, 0x60330001, + 0xC78, 0x47340001, + 0xC78, 0x46350001, + 0xC78, 0x45360001, + 0xC78, 0x44370001, + 0xC78, 0x43380001, + 0xC78, 0x42390001, + 0xC78, 0x413A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xC78, 0xFB050001, + 0xC78, 0xFB060001, + 0xC78, 0xFB070001, + 0xC78, 0xFA080001, + 0xC78, 0xF9090001, + 0xC78, 0xF80A0001, + 0xC78, 0xF70B0001, + 0xC78, 0xF60C0001, + 0xC78, 0xF50D0001, + 0xC78, 0xF40E0001, + 0xC78, 0xF30F0001, + 0xC78, 0xF2100001, + 0xC78, 0xF1110001, + 0xC78, 0xF0120001, + 0xC78, 0xEF130001, + 0xC78, 0xEE140001, + 0xC78, 0xED150001, + 0xC78, 0xEC160001, + 0xC78, 0xEB170001, + 0xC78, 0xEA180001, + 0xC78, 0xE9190001, + 0xC78, 0xC81A0001, + 0xC78, 0xC71B0001, + 0xC78, 0xC61C0001, + 0xC78, 0x071D0001, + 0xC78, 0x061E0001, + 0xC78, 0x051F0001, + 0xC78, 0x04200001, + 0xC78, 0x03210001, + 0xC78, 0xAA220001, + 0xC78, 0xA9230001, + 0xC78, 0xA8240001, + 0xC78, 0xA7250001, + 0xC78, 0xA6260001, + 0xC78, 0x85270001, + 0xC78, 0x84280001, + 0xC78, 0x83290001, + 0xC78, 0x252A0001, + 0xC78, 0x242B0001, + 0xC78, 0x232C0001, + 0xC78, 0x222D0001, + 0xC78, 0x672E0001, + 0xC78, 0x662F0001, + 0xC78, 0x65300001, + 0xC78, 0x64310001, + 0xC78, 0x63320001, + 0xC78, 0x62330001, + 0xC78, 0x61340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0xA0000000, 0x00000000, + 0xC78, 0xFF000001, + 0xC78, 0xFF010001, + 0xC78, 0xFE020001, + 0xC78, 0xFD030001, + 0xC78, 0xFC040001, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xC9190001, + 0xC78, 0xC81A0001, + 0xC78, 0xC71B0001, + 0xC78, 0xC61C0001, + 0xC78, 0xC51D0001, + 0xC78, 0xC41E0001, + 0xC78, 0xC31F0001, + 0xC78, 0x05200001, + 0xC78, 0x04210001, + 0xC78, 0x03220001, + 0xC78, 0x02230001, + 0xC78, 0xA8240001, + 0xC78, 0xA7250001, + 0xC78, 0xA6260001, + 0xC78, 0xA5270001, + 0xC78, 0x27280001, + 0xC78, 0x26290001, + 0xC78, 0x252A0001, + 0xC78, 0x242B0001, + 0xC78, 0x232C0001, + 0xC78, 0x222D0001, + 0xC78, 0x662E0001, + 0xC78, 0x652F0001, + 0xC78, 0x64300001, + 0xC78, 0x63310001, + 0xC78, 0x62320001, + 0xC78, 0x61330001, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFE400001, + 0xC78, 0xFD410001, + 0xC78, 0xFC420001, + 0xC78, 0xFB430001, + 0xC78, 0xFA440001, + 0xC78, 0xF9450001, + 0xC78, 0xF8460001, + 0xC78, 0xF7470001, + 0xC78, 0xF6480001, + 0xC78, 0xF5490001, + 0xC78, 0xF44A0001, + 0xC78, 0xF34B0001, + 0xC78, 0xF24C0001, + 0xC78, 0xF14D0001, + 0xC78, 0xF04E0001, + 0xC78, 0xEF4F0001, + 0xC78, 0xEE500001, + 0xC78, 0xED510001, + 0xC78, 0xEC520001, + 0xC78, 0xEB530001, + 0xC78, 0xEA540001, + 0xC78, 0xE9550001, + 0xC78, 0xE8560001, + 0xC78, 0xE7570001, + 0xC78, 0xE6580001, + 0xC78, 0xE5590001, + 0xC78, 0xE45A0001, + 0xC78, 0xE35B0001, + 0xC78, 0x885C0001, + 0xC78, 0x875D0001, + 0xC78, 0xAA5E0001, + 0xC78, 0xA95F0001, + 0xC78, 0xA8600001, + 0xC78, 0xA7610001, + 0xC78, 0xA6620001, + 0xC78, 0xA5630001, + 0xC78, 0x66640001, + 0xC78, 0x65650001, + 0xC78, 0x64660001, + 0xC78, 0x63670001, + 0xC78, 0x62680001, + 0xC78, 0x49690001, + 0xC78, 0x486A0001, + 0xC78, 0x476B0001, + 0xC78, 0x466C0001, + 0xC78, 0x456D0001, + 0xC78, 0x446E0001, + 0xC78, 0x436F0001, + 0xC78, 0x42700001, + 0xC78, 0x41710001, + 0xC78, 0x40720001, + 0xC78, 0x40730001, + 0xC78, 0x40740001, + 0xC78, 0x40750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040220, + 0xC58, 0x00000220, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xC78, 0xFE400001, + 0xC78, 0xFE410001, + 0xC78, 0xFE420001, + 0xC78, 0xFD430001, + 0xC78, 0xFC440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xE45C0001, + 0xC78, 0xE35D0001, + 0xC78, 0x885E0001, + 0xC78, 0x875F0001, + 0xC78, 0xAA600001, + 0xC78, 0xA9610001, + 0xC78, 0xA8620001, + 0xC78, 0xA7630001, + 0xC78, 0xA6640001, + 0xC78, 0xA5650001, + 0xC78, 0x66660001, + 0xC78, 0x65670001, + 0xC78, 0x64680001, + 0xC78, 0x63690001, + 0xC78, 0x626A0001, + 0xC78, 0x496B0001, + 0xC78, 0x486C0001, + 0xC78, 0x476D0001, + 0xC78, 0x466E0001, + 0xC78, 0x456F0001, + 0xC78, 0x44700001, + 0xC78, 0x43710001, + 0xC78, 0x42720001, + 0xC78, 0x41730001, + 0xC78, 0x40740001, + 0xC78, 0x40750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040220, + 0xC58, 0x00000220, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xC78, 0xFE400001, + 0xC78, 0xFE410001, + 0xC78, 0xFE420001, + 0xC78, 0xFE430001, + 0xC78, 0xFD440001, + 0xC78, 0xFC450001, + 0xC78, 0xFB460001, + 0xC78, 0xFA470001, + 0xC78, 0xF9480001, + 0xC78, 0xF8490001, + 0xC78, 0xF74A0001, + 0xC78, 0xF64B0001, + 0xC78, 0xF54C0001, + 0xC78, 0xF44D0001, + 0xC78, 0xF34E0001, + 0xC78, 0xF24F0001, + 0xC78, 0xF1500001, + 0xC78, 0xF0510001, + 0xC78, 0xEF520001, + 0xC78, 0xEE530001, + 0xC78, 0xED540001, + 0xC78, 0xEC550001, + 0xC78, 0xEB560001, + 0xC78, 0xEA570001, + 0xC78, 0xE9580001, + 0xC78, 0xE8590001, + 0xC78, 0xE75A0001, + 0xC78, 0xE65B0001, + 0xC78, 0xE55C0001, + 0xC78, 0xE45D0001, + 0xC78, 0xE35E0001, + 0xC78, 0x885F0001, + 0xC78, 0x87600001, + 0xC78, 0xAA610001, + 0xC78, 0xA9620001, + 0xC78, 0xA8630001, + 0xC78, 0xA7640001, + 0xC78, 0xA6650001, + 0xC78, 0xA5660001, + 0xC78, 0x66670001, + 0xC78, 0x65680001, + 0xC78, 0x64690001, + 0xC78, 0x636A0001, + 0xC78, 0x626B0001, + 0xC78, 0x496C0001, + 0xC78, 0x486D0001, + 0xC78, 0x476E0001, + 0xC78, 0x466F0001, + 0xC78, 0x45700001, + 0xC78, 0x44710001, + 0xC78, 0x43720001, + 0xC78, 0x42730001, + 0xC78, 0x41740001, + 0xC78, 0x40750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040220, + 0xC58, 0x00000220, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xC78, 0xFE400001, + 0xC78, 0xFE410001, + 0xC78, 0xFE420001, + 0xC78, 0xFE430001, + 0xC78, 0xFE440001, + 0xC78, 0xFD450001, + 0xC78, 0xFC460001, + 0xC78, 0xFB470001, + 0xC78, 0xFA480001, + 0xC78, 0xF9490001, + 0xC78, 0xF84A0001, + 0xC78, 0xF74B0001, + 0xC78, 0xF64C0001, + 0xC78, 0xF54D0001, + 0xC78, 0xF44E0001, + 0xC78, 0xF34F0001, + 0xC78, 0xF2500001, + 0xC78, 0xF1510001, + 0xC78, 0xF0520001, + 0xC78, 0xEF530001, + 0xC78, 0xEE540001, + 0xC78, 0xED550001, + 0xC78, 0xEC560001, + 0xC78, 0xEB570001, + 0xC78, 0xEA580001, + 0xC78, 0x09590001, + 0xC78, 0x085A0001, + 0xC78, 0x075B0001, + 0xC78, 0x065C0001, + 0xC78, 0x055D0001, + 0xC78, 0x045E0001, + 0xC78, 0x035F0001, + 0xC78, 0x29600001, + 0xC78, 0x28610001, + 0xC78, 0x27620001, + 0xC78, 0x26630001, + 0xC78, 0x25640001, + 0xC78, 0x24650001, + 0xC78, 0x23660001, + 0xC78, 0x68670001, + 0xC78, 0x67680001, + 0xC78, 0x66690001, + 0xC78, 0x656A0001, + 0xC78, 0x646B0001, + 0xC78, 0x636C0001, + 0xC78, 0x626D0001, + 0xC78, 0x496E0001, + 0xC78, 0x486F0001, + 0xC78, 0x47700001, + 0xC78, 0x46710001, + 0xC78, 0x45720001, + 0xC78, 0x44730001, + 0xC78, 0x43740001, + 0xC78, 0x42750001, + 0xC78, 0x41760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040220, + 0xC58, 0x00000220, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xE45C0001, + 0xC78, 0xE35D0001, + 0xC78, 0xE25E0001, + 0xC78, 0xE15F0001, + 0xC78, 0x8A600001, + 0xC78, 0x89610001, + 0xC78, 0x88620001, + 0xC78, 0x87630001, + 0xC78, 0x86640001, + 0xC78, 0x85650001, + 0xC78, 0x84660001, + 0xC78, 0x83670001, + 0xC78, 0x82680001, + 0xC78, 0x6B690001, + 0xC78, 0x6A6A0001, + 0xC78, 0x696B0001, + 0xC78, 0x686C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x49740001, + 0xC78, 0x48750001, + 0xC78, 0x47760001, + 0xC78, 0x46770001, + 0xC78, 0x45780001, + 0xC78, 0x44790001, + 0xC78, 0x437A0001, + 0xC78, 0x427B0001, + 0xC78, 0x417C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040020, + 0xC58, 0x00000020, + 0xA0000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFA470001, + 0xC78, 0xF9480001, + 0xC78, 0xF8490001, + 0xC78, 0xF74A0001, + 0xC78, 0xF64B0001, + 0xC78, 0xF54C0001, + 0xC78, 0xF44D0001, + 0xC78, 0xF34E0001, + 0xC78, 0xF24F0001, + 0xC78, 0xF1500001, + 0xC78, 0xF0510001, + 0xC78, 0xEF520001, + 0xC78, 0xEE530001, + 0xC78, 0xED540001, + 0xC78, 0xEC550001, + 0xC78, 0xEB560001, + 0xC78, 0xEA570001, + 0xC78, 0xE9580001, + 0xC78, 0xE8590001, + 0xC78, 0xE75A0001, + 0xC78, 0xE65B0001, + 0xC78, 0xE55C0001, + 0xC78, 0xE45D0001, + 0xC78, 0xE35E0001, + 0xC78, 0xE25F0001, + 0xC78, 0xE1600001, + 0xC78, 0x8A610001, + 0xC78, 0x89620001, + 0xC78, 0x88630001, + 0xC78, 0x87640001, + 0xC78, 0x86650001, + 0xC78, 0x85660001, + 0xC78, 0x84670001, + 0xC78, 0x83680001, + 0xC78, 0x82690001, + 0xC78, 0x6B6A0001, + 0xC78, 0x6A6B0001, + 0xC78, 0x696C0001, + 0xC78, 0x686D0001, + 0xC78, 0x676E0001, + 0xC78, 0x666F0001, + 0xC78, 0x65700001, + 0xC78, 0x64710001, + 0xC78, 0x63720001, + 0xC78, 0x62730001, + 0xC78, 0x61740001, + 0xC78, 0x49750001, + 0xC78, 0x48760001, + 0xC78, 0x47770001, + 0xC78, 0x46780001, + 0xC78, 0x45790001, + 0xC78, 0x447A0001, + 0xC78, 0x437B0001, + 0xC78, 0x427C0001, + 0xC78, 0x417D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xC50, 0x00040020, + 0xC58, 0x00000020, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8192E_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8192E_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8192E(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8192E_AGC_TAB(void) +{ + return 58; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_PHY_REG[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02220385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0xA0000000, 0x00000000, + 0x824, 0x00390204, + 0xB0000000, 0x00000000, + 0x828, 0x01000100, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x82C, 0x00390004, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x82C, 0x00390004, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x82C, 0x00390004, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x82C, 0x00390004, + 0xA0000000, 0x00000000, + 0x82C, 0x00390204, + 0xB0000000, 0x00000000, + 0x830, 0x32323232, + 0x834, 0x30303030, + 0x838, 0x30303030, + 0x83C, 0x30303030, + 0x840, 0x00010000, + 0x844, 0x00010000, + 0x848, 0x28282828, + 0x84C, 0x28282828, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x009A009A, + 0x85C, 0x01000014, + 0x860, 0x66F60000, + 0x864, 0x061F0000, + 0x868, 0x30303030, + 0x86C, 0x30303030, + 0x870, 0x00000000, + 0x874, 0x55004200, + 0x878, 0x08080808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCC0000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121313, + 0x910, 0x806C0001, + 0x914, 0x00000001, + 0x918, 0x00000000, + 0x91C, 0x00010000, + 0x924, 0x00000001, + 0x928, 0x00000000, + 0x92C, 0x00000000, + 0x930, 0x00000000, + 0x934, 0x00000000, + 0x938, 0x00000000, + 0x93C, 0x00000000, + 0x940, 0x00000000, + 0x944, 0x00000000, + 0x94C, 0x00000008, + 0xA00, 0x00D047C8, + 0xA04, 0x81FF800C, + 0xA08, 0x8C838300, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E30120F, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xA0C, 0x2E30120F, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xA0C, 0x2E30120F, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xA0C, 0x2E30120F, + 0xA0000000, 0x00000000, + 0xA0C, 0x2E68120F, + 0xB0000000, 0x00000000, + 0xA10, 0x95009B78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x12130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x12130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0xA0000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xB0000000, 0x00000000, + 0xA2C, 0x00D30000, + 0xA70, 0x101FFF80, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0xA0000000, 0x00000000, + 0xA80, 0x218075B1, + 0xB0000000, 0x00000000, + 0xB38, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05633, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC47, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0xA0000000, 0x00000000, + 0xC50, 0x00340020, + 0xB0000000, 0x00000000, + 0xC54, 0x0080801F, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0xA0000000, 0x00000000, + 0xC58, 0x00000020, + 0xB0000000, 0x00000000, + 0xC5C, 0x00248492, + 0xC60, 0x00000000, + 0xC64, 0x2112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x00000600, + 0xC74, 0x02013269, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0xA0000000, 0x00000000, + 0xC80, 0x40000100, + 0xB0000000, 0x00000000, + 0xC84, 0x21F60000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x2D4000B5, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x2D4000B5, + 0xA0000000, 0x00000000, + 0xC88, 0x40000100, + 0xB0000000, 0x00000000, + 0xC8C, 0xA0E40000, + 0xC90, 0x00121820, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00040000, + 0xCE8, 0x77644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00080740, + 0xD04, 0x00020403, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC43, + 0xD18, 0x7A8F5B6B, + 0xD1C, 0x0000007F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xD80, 0x01081008, + 0xD84, 0x00000800, + 0xD88, 0xF0B50000, + 0xE00, 0x30303030, + 0xE04, 0x30303030, + 0xE08, 0x03903030, + 0xE10, 0x30303030, + 0xE14, 0x30303030, + 0xE18, 0x30303030, + 0xE1C, 0x30303030, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000048, + 0xE68, 0x0FC05656, + 0xE6C, 0x03C09696, + 0xE70, 0x03C09696, + 0xE74, 0x0C005656, + 0xE78, 0x0C005656, + 0xE7C, 0x0C005656, + 0xE80, 0x0C005656, + 0xE84, 0x03C09696, + 0xE88, 0x0C005656, + 0xE8C, 0x03C09696, + 0xED0, 0x03C09696, + 0xED4, 0x03C09696, + 0xED8, 0x03C09696, + 0xEDC, 0x0000D6D6, + 0xEE0, 0x0000D6D6, + 0xEEC, 0x0FC01616, + 0xEE4, 0xB0000C1C, + 0xEE8, 0x00000001, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +ODM_ReadAndConfig_MP_8192E_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8192E_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8192E(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8192E_PHY_REG(void) +{ + return 58; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 1, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 1, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x36364040, + 0, 0, 1, 0x00000e00, 0xffffffff, 0x34343636, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28283234, + 0, 0, 1, 0x00000e04, 0xffffffff, 0x28283032, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x38383840, + 0, 0, 1, 0x00000e10, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26283038, + 0, 0, 1, 0x00000e14, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000e18, 0xffffffff, 0x36384040, + 0, 0, 1, 0x00000e1c, 0xffffffff, 0x24262832, + 0, 1, 0, 0x00000838, 0xffffff00, 0x32323200, + 0, 1, 1, 0x00000838, 0xffffff00, 0x32323200, + 0, 1, 0, 0x0000086c, 0x000000ff, 0x00000032, + 0, 1, 1, 0x0000086c, 0x000000ff, 0x00000032, + 0, 1, 0, 0x00000830, 0xffffffff, 0x36364040, + 0, 1, 1, 0x00000830, 0xffffffff, 0x34343636, + 0, 1, 0, 0x00000834, 0xffffffff, 0x28283234, + 0, 1, 1, 0x00000834, 0xffffffff, 0x28283032, + 0, 1, 0, 0x0000083c, 0xffffffff, 0x38383840, + 0, 1, 1, 0x0000083c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000848, 0xffffffff, 0x26283038, + 0, 1, 1, 0x00000848, 0xffffffff, 0x26283032, + 0, 1, 1, 0x0000084c, 0xffffffff, 0x36384040, + 0, 1, 1, 0x00000868, 0xffffffff, 0x24262832 +}; + +void +ODM_ReadAndConfig_MP_8192E_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8192E_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8192E(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.h index 58a343bf8ea..dccf06f621c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8192E_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8192E_H -#define __INC_MP_BB_HW_IMG_8192E_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8192E_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8192E_H +#define __INC_MP_BB_HW_IMG_8192E_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.c index dd2de0b77ed..67dfcebfbf8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.c @@ -1,7098 +1,7098 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8192e/hal8192e_fw.h" -#endif - - -#if (RTL8192E_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8192E_FW_AP[] = { -0xE1, 0x92, 0x20, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x38, 0xE2, 0x5C, 0x00, 0x00, -0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x48, 0xB1, 0x02, 0x77, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x65, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x7B, 0xB3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x77, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x78, 0x25, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x7B, 0xB2, 0x1D, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0D, 0xF0, 0x0F, -0x00, 0x00, 0x00, 0x00, 0x0D, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0D, 0xF0, 0x0F, 0x00, 0x00, -0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, -0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x10, 0xF0, 0x3F, 0x00, -0x00, 0x00, 0x00, 0x32, 0x32, 0x24, 0x32, 0x32, 0x43, 0x4B, 0x43, 0x4B, 0x43, 0x4B, 0x59, 0x32, -0x32, 0x43, 0x4B, 0x43, 0x4B, 0x59, 0x5A, 0x32, 0x32, 0x43, 0x4B, 0x43, 0x4B, 0x59, 0x5A, 0x52, -0x53, 0x54, 0x55, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x56, 0x57, 0x58, 0x59, 0x5A, -0x5B, 0x5C, 0x5D, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x00, 0x00, 0x00, 0x01, 0x00, -0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x03, 0x00, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x03, 0x00, -0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x03, 0x04, 0x05, -0x06, 0x07, 0x08, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x05, 0x06, 0x06, 0x07, 0x08, -0x0A, 0x0B, 0x0C, 0x04, 0x02, 0x04, 0x02, 0x03, 0x0C, 0x0D, 0x0C, 0x14, 0x0D, 0x15, 0x0E, 0x15, -0x0F, 0x16, 0x10, 0x17, 0x11, 0x18, 0x12, 0x18, 0x13, 0x18, 0xFF, 0x15, 0x0E, 0x16, 0x10, 0x17, -0x11, 0x18, 0x12, 0x19, 0xFF, 0x1A, 0xFF, 0x1B, 0xFF, 0x14, 0x0C, 0x14, 0x0D, 0x0E, 0x14, 0x15, -0x0F, 0x16, 0x10, 0x17, 0x11, 0x12, 0x17, 0x0C, 0xFF, 0x0E, 0x14, 0x15, 0x0F, 0x16, 0x10, 0x13, -0x17, 0x18, 0x13, 0x19, 0x18, 0x1A, 0x19, 0x19, 0x06, 0x04, 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-0x3D, 0xC8, -}; -u4Byte ArrayLength_MP_8192E_FW_AP = 23810; - -#endif - -void -ODM_ReadFirmware_MP_8192E_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_AP; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_AP, ArrayLength_MP_8192E_FW_AP); -#endif - *pFirmwareSize = ArrayLength_MP_8192E_FW_AP; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8192E_FW_AP_PCIE[] = { -0xE1, 0x92, 0x23, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x39, 0x40, 0x7B, 0x00, 0x00, -0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x48, 0xB1, 0x02, 0x67, 0xF5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 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ArrayLength_MP_8192E_FW_NIC = 30248; - - -#endif - -void -ODM_ReadFirmware_MP_8192E_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_NIC, ArrayLength_MP_8192E_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8192E_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8192E_FW_WoWLAN[] = { -0xE1, 0x92, 0x30, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x38, 0x5C, 0x64, 0x00, 0x00, -0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x4A, 0xB8, 0x02, 0x5F, 0xFB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x6F, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 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0x54, 0xFB, 0xF0, 0x22, 0xE4, 0x75, 0xF0, 0x20, -0x02, 0x08, 0xD6, 0x90, 0x8E, 0x3E, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, -0x7B, 0x01, 0x22, 0x90, 0x8E, 0xF5, 0x12, 0x48, 0xCA, 0xE0, 0x22, 0x7E, 0x00, 0x7F, 0x10, 0x02, -0x06, 0x63, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x22, 0x90, 0x8E, 0x56, 0xE0, 0xC4, 0x54, -0x0F, 0x22, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x22, 0x3C, 0x59, -}; -u4Byte ArrayLength_MP_8192E_FW_WoWLAN = 25724; - -#endif - -void -ODM_ReadFirmware_MP_8192E_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_WoWLAN, ArrayLength_MP_8192E_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8192E_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8192e/hal8192e_fw.h" +#endif + + +#if (RTL8192E_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8192E_FW_AP[] = { +0xE1, 0x92, 0x20, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x38, 0xE2, 0x5C, 0x00, 0x00, +0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0xB1, 0x02, 0x77, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+0x3D, 0xC8, +}; +u4Byte ArrayLength_MP_8192E_FW_AP = 23810; + +#endif + +void +ODM_ReadFirmware_MP_8192E_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_AP, ArrayLength_MP_8192E_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8192E_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8192E_FW_AP_PCIE[] = { +0xE1, 0x92, 0x23, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x39, 0x40, 0x7B, 0x00, 0x00, +0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0xB1, 0x02, 0x67, 0xF5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 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0x48, 0x55, +0xEF, 0x44, 0x04, 0xFF, 0x22, 0x90, 0xA4, 0x22, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0x00, 0xD2, 0x69, + +}; +u4Byte ArrayLength_MP_8192E_FW_AP_PCIE = 31584; + + +#endif + +void +ODM_ReadFirmware_MP_8192E_FW_AP_PCIE( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_AP_PCIE; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_AP_PCIE, ArrayLength_MP_8192E_FW_AP_PCIE); +#endif + *pFirmwareSize = ArrayLength_MP_8192E_FW_AP_PCIE; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8192E_FW_NIC[] = { +0xE1, 0x92, 0x10, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x37, 0x08, 0x76, 0x00, 0x00, +0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0xB2, 0x02, 0x7F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x80, 0x1C, 0x00, 0x00, 0x00, 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ArrayLength_MP_8192E_FW_NIC = 30248; + + +#endif + +void +ODM_ReadFirmware_MP_8192E_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_NIC, ArrayLength_MP_8192E_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8192E_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8192E_FW_WoWLAN[] = { +0xE1, 0x92, 0x30, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x12, 0x08, 0x17, 0x38, 0x5C, 0x64, 0x00, 0x00, +0x41, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x4A, 0xB8, 0x02, 0x5F, 0xFB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x6F, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 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0x7F, 0x01, 0x22, 0x90, 0x93, 0x63, 0xEE, +0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x51, 0x2C, 0x90, 0x94, 0x78, 0xE0, 0x64, 0x01, 0xF0, 0xE0, 0x24, +0x35, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0xA2, 0xA3, 0x12, 0x5C, 0x75, 0x02, 0x84, 0xD1, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x94, 0x7D, 0xE0, 0xFE, 0x90, 0x94, 0x7A, 0xE0, 0xC3, 0x9E, +0x40, 0x04, 0x7F, 0x00, 0x80, 0x0E, 0xEF, 0x60, 0x05, 0xD3, 0x94, 0x0E, 0x40, 0x04, 0x7F, 0x00, +0x80, 0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xED, 0x14, 0x60, 0x06, 0x04, 0x70, 0x03, +0x7F, 0x01, 0x22, 0x7F, 0x01, 0x22, 0x90, 0x93, 0x67, 0xEF, 0xF0, 0x22, 0x90, 0x93, 0x65, 0xE0, +0xFD, 0x90, 0x93, 0x64, 0xE0, 0x2D, 0xFD, 0x22, 0x90, 0x8E, 0x3C, 0xE0, 0x24, 0x01, 0xFF, 0x90, +0x8E, 0x3B, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x22, 0x90, 0x8E, 0x54, 0xE0, 0xFF, 0x13, 0x13, 0x13, +0x54, 0x1F, 0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x93, 0x8C, 0xE0, 0x04, 0xF0, 0x22, 0x7D, 0x01, +0x7B, 0x01, 0x7A, 0x8E, 0x79, 0xE7, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x4A, 0x94, 0xEF, 0x22, 0x78, +0x10, 0x12, 0x08, 0x47, 0x90, 0x95, 0x06, 0x12, 0x48, 0xBE, 0x02, 0x48, 0x1D, 0x75, 0xF0, 0x20, +0xA4, 0x24, 0x37, 0xF9, 0x74, 0x91, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0x22, 0xEE, 0x8F, 0xF0, 0x12, +0x08, 0xD6, 0x90, 0x8E, 0x3B, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xF0, 0xEE, 0x54, 0x20, 0xFE, +0xEF, 0x54, 0xDF, 0x4E, 0x22, 0x90, 0x8E, 0xBC, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22, 0xE0, +0x90, 0x01, 0xBA, 0xF0, 0x90, 0x8E, 0x5A, 0xE0, 0x90, 0x01, 0xBB, 0x22, 0xEF, 0xF0, 0x90, 0x93, +0x6B, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x93, 0x66, 0xE0, 0xFD, 0x90, 0x93, 0x65, 0xE0, 0x22, 0x24, +0x30, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x22, 0x12, 0x26, 0x4A, 0x90, 0x95, 0x06, 0x02, +0x08, 0x6D, 0x90, 0x93, 0x8C, 0xE0, 0xFF, 0xC3, 0x22, 0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, +0xFF, 0x22, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x22, 0x74, 0xFF, 0x2E, 0xF5, 0x82, +0xE4, 0x34, 0x90, 0x22, 0x90, 0x94, 0x85, 0xE0, 0x90, 0x95, 0x3D, 0xF0, 0x22, 0x7E, 0x00, 0x7F, +0x08, 0x7D, 0x00, 0x7B, 0x01, 0x22, 0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x22, 0x90, +0x94, 0x97, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x22, 0x90, 0x94, 0x99, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, +0x22, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x02, 0x87, 0xE0, 0x22, 0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, +0x01, 0x1E, 0x22, 0x90, 0x95, 0x04, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x22, 0x90, 0x93, 0x8D, 0xE0, +0xFF, 0x75, 0xF0, 0x38, 0x22, 0xE0, 0x24, 0x6C, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0x22, 0xE0, 0x24, +0x66, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0x22, 0x78, 0x6C, 0x7C, 0x93, 0x7D, 0x01, 0x7B, 0xFF, 0x22, +0x90, 0x93, 0x69, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0, +0xFD, 0x22, 0x90, 0x8E, 0x56, 0xE0, 0xFF, 0xC4, 0x54, 0x0F, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5, +0x82, 0x8E, 0x83, 0x22, 0xF0, 0x7F, 0x10, 0x7E, 0x00, 0x02, 0x3E, 0x87, 0x12, 0x4B, 0x96, 0xEF, +0x44, 0x01, 0xFD, 0x22, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0x22, 0xF5, 0x82, 0xE4, 0x34, +0x91, 0xF5, 0x83, 0x22, 0x90, 0x02, 0x86, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0xE4, 0x75, 0xF0, 0x20, +0x02, 0x08, 0xD6, 0x90, 0x8E, 0x3E, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, +0x7B, 0x01, 0x22, 0x90, 0x8E, 0xF5, 0x12, 0x48, 0xCA, 0xE0, 0x22, 0x7E, 0x00, 0x7F, 0x10, 0x02, +0x06, 0x63, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x22, 0x90, 0x8E, 0x56, 0xE0, 0xC4, 0x54, +0x0F, 0x22, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x22, 0x3C, 0x59, +}; +u4Byte ArrayLength_MP_8192E_FW_WoWLAN = 25724; + +#endif + +void +ODM_ReadFirmware_MP_8192E_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8192E_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8192E_FW_WoWLAN, ArrayLength_MP_8192E_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8192E_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.h index 9763a4675c4..00976e712b8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_fw.h @@ -1,73 +1,73 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8192E_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8192E_H -#define __INC_MP_FW_HW_IMG_8192E_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8192E_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_AP_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8192E_FW_AP_PCIE( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8192E_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8192E_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8192E_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8192E_H +#define __INC_MP_FW_HW_IMG_8192E_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8192E_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_AP_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8192E_FW_AP_PCIE( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8192E_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8192E_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.c index aeac2b07c6a..2436ab5cb2a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.c @@ -1,289 +1,289 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8192E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_MAC_REG[] = { - 0x011, 0x000000EB, - 0x012, 0x00000007, - 0x014, 0x00000075, - 0x303, 0x000000A7, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x540, 0x00000012, - 0x541, 0x00000064, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x0000002B, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - -}; - -void -ODM_ReadAndConfig_MP_8192E_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8192E_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8192E(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8192E_MAC_REG(void) -{ - return 58; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8192E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_MAC_REG[] = { + 0x011, 0x000000EB, + 0x012, 0x00000007, + 0x014, 0x00000075, + 0x303, 0x000000A7, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x540, 0x00000012, + 0x541, 0x00000064, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x0000002B, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + +}; + +void +ODM_ReadAndConfig_MP_8192E_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8192E_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8192E(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8192E_MAC_REG(void) +{ + return 58; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.h index 11a55d4ce1d..1b0a4c87bdd 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8192E_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8192E_H -#define __INC_MP_MAC_HW_IMG_8192E_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8192E_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8192E_H +#define __INC_MP_MAC_HW_IMG_8192E_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.c index 4c848396b2d..5f1b50dc41a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.c @@ -1,2240 +1,2240 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8192E_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_RadioA[] = { - 0x07F, 0x00000082, - 0x081, 0x0003FC00, - 0x000, 0x00030000, - 0x008, 0x00008400, - 0x018, 0x00000407, - 0x019, 0x00000012, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000064, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000394C, - 0xA0000000, 0x00000000, - 0x01B, 0x0000394C, - 0xB0000000, 0x00000000, - 0x01E, 0x00080009, - 0x01F, 0x00000880, - 0x02F, 0x0001A060, - 0x03F, 0x00000000, - 0x042, 0x000060C0, - 0x057, 0x000D0000, - 0x058, 0x000BE180, - 0x067, 0x00001552, - 0x083, 0x00000000, - 0x0B0, 0x000FF9F1, - 0x0B1, 0x00055418, - 0x0B2, 0x0008CC00, - 0x0B4, 0x00043083, - 0x0B5, 0x00008166, - 0x0B6, 0x0000803E, - 0x0B7, 0x0001C69F, - 0x0B8, 0x0000407F, - 0x0B9, 0x00090001, - 0x0BA, 0x00040001, - 0x0BB, 0x00000400, - 0x0BC, 0x00000078, - 0x0BD, 0x000B3333, - 0x0BE, 0x00033340, - 0x0BF, 0x00000000, - 0x0C0, 0x00005999, - 0x0C1, 0x00009999, - 0x0C2, 0x00002400, - 0x0C3, 0x00000009, - 0x0C4, 0x00040C91, - 0x0C5, 0x00099999, - 0x0C6, 0x000000A3, - 0x0C7, 0x00088820, - 0x0C8, 0x00076C06, - 0x0C9, 0x00000000, - 0x0CA, 0x00080000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0xA0000000, 0x00000000, - 0x01C, 0x00000000, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000180, - 0x0EF, 0x000001A0, - 0x051, 0x00069545, - 0x052, 0x0007E45E, - 0x053, 0x00000071, - 0x056, 0x00051FF3, - 0x035, 0x000000A8, - 0x035, 0x000001E2, - 0x035, 0x000002A8, - 0x036, 0x00001C24, - 0x036, 0x00009C24, - 0x036, 0x00011C24, - 0x036, 0x00019C24, - 0x018, 0x00000C07, - 0x05A, 0x00048000, - 0x019, 0x000739D0, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0xB0000000, 0x00000000, - 0x000, 0x00030159, - 0x084, 0x00068180, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000014E, - 0x087, 0x00049F80, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000014E, - 0x087, 0x00049F80, - 0xA0000000, 0x00000000, - 0x086, 0x0000014E, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x08E, 0x00065540, - 0x08F, 0x00088000, - 0x0EF, 0x000020A0, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F52B0, - 0xA0000000, 0x00000000, - 0x03B, 0x000F02B0, - 0xB0000000, 0x00000000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0xA0000000, 0x00000000, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0xB0000000, 0x00000000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x00078730, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x00070730, - 0xA0000000, 0x00000000, - 0x03B, 0x00078730, - 0xB0000000, 0x00000000, - 0x03B, 0x00060FB0, - 0x03B, 0x0005FFA0, - 0x03B, 0x00040620, - 0x03B, 0x00037090, - 0x03B, 0x00020080, - 0x03B, 0x0001F060, - 0x03B, 0x0000FFB0, - 0x0EF, 0x000000A0, - 0xFFE, 0x00000000, - 0x018, 0x0000FC07, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01E, 0x00000001, - 0x01F, 0x00080000, - 0x000, 0x00033E70, - -}; - -void -ODM_ReadAndConfig_MP_8192E_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8192E_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8192E(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8192E_RadioA(void) -{ - return 58; -} - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -u4Byte Array_MP_8192E_RadioB[] = { - 0x07F, 0x00000082, - 0x081, 0x0003FC00, - 0x000, 0x00030000, - 0x008, 0x00008400, - 0x018, 0x00000407, - 0x019, 0x00000012, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00000064, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x01B, 0x0000146C, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x0000394C, - 0xA0000000, 0x00000000, - 0x01B, 0x0000394C, - 0xB0000000, 0x00000000, - 0x01E, 0x00080009, - 0x01F, 0x00000880, - 0x02F, 0x0001A060, - 0x03F, 0x00000000, - 0x042, 0x000060C0, - 0x057, 0x000D0000, - 0x058, 0x000BE180, - 0x067, 0x00001552, - 0x07F, 0x00000082, - 0x081, 0x0003F000, - 0x083, 0x00000000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00001C00, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x01C, 0x00000000, - 0xA0000000, 0x00000000, - 0x01C, 0x00000000, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000180, - 0x0EF, 0x000001A0, - 0x051, 0x00069545, - 0x052, 0x0007E42E, - 0x053, 0x00000071, - 0x056, 0x00051FF3, - 0x035, 0x000000A8, - 0x035, 0x000001E0, - 0x035, 0x000002A8, - 0x036, 0x00001CA8, - 0x036, 0x00009C24, - 0x036, 0x00011C24, - 0x036, 0x00019C24, - 0x018, 0x00000C07, - 0x05A, 0x00048000, - 0x019, 0x000739D0, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A093, - 0x034, 0x0000908F, - 0x034, 0x0000808C, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000000, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005DC8, - 0x034, 0x00004DC5, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x00000014, - 0xB0000000, 0x00000000, - 0x000, 0x00030159, - 0x084, 0x00068180, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00049F80, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x086, 0x0000010E, - 0x087, 0x000F5F80, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00049F80, - 0xA0000000, 0x00000000, - 0x086, 0x000000CE, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x08E, 0x00065540, - 0x08F, 0x00088000, - 0x0EF, 0x000020A0, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F02B0, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000F0730, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000F52B0, - 0xA0000000, 0x00000000, - 0x03B, 0x000F02B0, - 0xB0000000, 0x00000000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000E0730, - 0x03B, 0x000D0020, - 0x03B, 0x000C0020, - 0x03B, 0x000B0760, - 0x03B, 0x000A0010, - 0x03B, 0x00090000, - 0x03B, 0x00080000, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0xA0000000, 0x00000000, - 0x03B, 0x000EF7B0, - 0x03B, 0x000D4FB0, - 0x03B, 0x000CF060, - 0x03B, 0x000B0090, - 0x03B, 0x000A0080, - 0x03B, 0x00090080, - 0x03B, 0x0008F780, - 0xB0000000, 0x00000000, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000003, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x00078730, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x0000000a, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000001, 0x0000000f, 0x40000000, 0x00000000, - 0x03B, 0x000787B0, - 0x90000400, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x00070730, - 0xA0000000, 0x00000000, - 0x03B, 0x00078730, - 0xB0000000, 0x00000000, - 0x03B, 0x00060FB0, - 0x03B, 0x0005FFA0, - 0x03B, 0x00040620, - 0x03B, 0x00037090, - 0x03B, 0x00020080, - 0x03B, 0x0001F060, - 0x03B, 0x0000FFB0, - 0x0EF, 0x000000A0, - 0x000, 0x00010159, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x01E, 0x00000001, - 0x01F, 0x00080000, - 0x000, 0x00033E70, - -}; - -void -ODM_ReadAndConfig_MP_8192E_RadioB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8192E_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8192E_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioB_8192E(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8192E_RadioB(void) -{ - return 58; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8192E[] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8192E[] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8192E_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "CCK", "2T", "01", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "01", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "01", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "02", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "02", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "02", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "03", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "03", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "03", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "04", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "04", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "04", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "05", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "05", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "05", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "06", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "06", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "06", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "07", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "07", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "07", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "08", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "08", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "08", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "09", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "09", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "09", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "10", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "10", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "10", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "11", "26", - "ETSI", "2.4G", "20M", "CCK", "2T", "11", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "11", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "12", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "12", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "13", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "13", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "2T", "14", "26", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "OFDM", "2T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "2T", "01", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "02", "26", - "ETSI", "2.4G", "20M", "OFDM", "2T", "02", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "02", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "03", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "03", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "03", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "04", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "04", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "05", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "05", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "06", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "06", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "07", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "07", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "2T", "08", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "08", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "2T", "09", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "09", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "2T", "10", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "10", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "2T", "11", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "11", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "12", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "12", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "13", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "28", - "MKK", "2.4G", "20M", "HT", "1T", "01", "28", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "28", - "MKK", "2.4G", "20M", "HT", "1T", "02", "28", - "FCC", "2.4G", "20M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "28", - "MKK", "2.4G", "20M", "HT", "1T", "09", "28", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "28", - "MKK", "2.4G", "20M", "HT", "1T", "10", "28", - "FCC", "2.4G", "20M", "HT", "1T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "28", - "MKK", "2.4G", "20M", "HT", "1T", "11", "28", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "28", - "MKK", "2.4G", "20M", "HT", "1T", "12", "28", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "28", - "MKK", "2.4G", "20M", "HT", "1T", "13", "28", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "26", - "MKK", "2.4G", "20M", "HT", "2T", "01", "28", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "26", - "MKK", "2.4G", "20M", "HT", "2T", "02", "28", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "26", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "26", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "26", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "26", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "26", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", - "MKK", "2.4G", "20M", "HT", "2T", "09", "28", - "FCC", "2.4G", "20M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "26", - "MKK", "2.4G", "20M", "HT", "2T", "10", "28", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "26", - "MKK", "2.4G", "20M", "HT", "2T", "11", "28", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "26", - "MKK", "2.4G", "20M", "HT", "2T", "12", "28", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "26", - "MKK", "2.4G", "20M", "HT", "2T", "13", "28", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "26", - "MKK", "2.4G", "20M", "HT", "2T", "01", "26", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "26", - "MKK", "2.4G", "20M", "HT", "2T", "02", "26", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "26", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "26", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "26", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "26", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "26", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", - "MKK", "2.4G", "20M", "HT", "2T", "09", "26", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "26", - "MKK", "2.4G", "20M", "HT", "2T", "10", "26", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "26", - "MKK", "2.4G", "20M", "HT", "2T", "11", "26", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "26", - "MKK", "2.4G", "20M", "HT", "2T", "12", "26", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "26", - "MKK", "2.4G", "20M", "HT", "2T", "13", "26", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "28", - "MKK", "2.4G", "40M", "HT", "1T", "03", "28", - "FCC", "2.4G", "40M", "HT", "1T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", - "MKK", "2.4G", "40M", "HT", "1T", "04", "28", - "FCC", "2.4G", "40M", "HT", "1T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", - "MKK", "2.4G", "40M", "HT", "1T", "05", "28", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "30", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "30", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "30", - "FCC", "2.4G", "40M", "HT", "1T", "09", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", - "MKK", "2.4G", "40M", "HT", "1T", "09", "28", - "FCC", "2.4G", "40M", "HT", "1T", "10", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", - "MKK", "2.4G", "40M", "HT", "1T", "10", "28", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "28", - "MKK", "2.4G", "40M", "HT", "1T", "11", "28", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63" -}; - -void -ODM_ReadAndConfig_MP_8192E_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8192E_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8192E_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8192E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8192E_SAR_5mm.TXT -******************************************************************************/ - -const char *Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "CCK", "2T", "01", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "01", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "01", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "02", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "02", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "02", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "03", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "03", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "03", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "04", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "04", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "04", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "05", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "05", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "05", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "06", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "06", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "06", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "07", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "07", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "07", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "08", "24", - "ETSI", "2.4G", "20M", "CCK", "2T", "08", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "08", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "09", "22", - "ETSI", "2.4G", "20M", "CCK", "2T", "09", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "09", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "10", "22", - "ETSI", "2.4G", "20M", "CCK", "2T", "10", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "10", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "11", "22", - "ETSI", "2.4G", "20M", "CCK", "2T", "11", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "11", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "12", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "12", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "13", "22", - "MKK", "2.4G", "20M", "CCK", "2T", "13", "26", - "FCC", "2.4G", "20M", "CCK", "2T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "2T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "2T", "14", "26", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "OFDM", "2T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "2T", "01", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "02", "26", - "ETSI", "2.4G", "20M", "OFDM", "2T", "02", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "02", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "03", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "03", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "03", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "04", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "04", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "04", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "05", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "05", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "05", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "06", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "06", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "06", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "07", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "07", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "07", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "08", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "08", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "08", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "09", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "09", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "09", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "10", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "10", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "2T", "11", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "11", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "12", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "12", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "13", "26", - "MKK", "2.4G", "20M", "OFDM", "2T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "2T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "2T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "28", - "MKK", "2.4G", "20M", "HT", "1T", "01", "28", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "28", - "MKK", "2.4G", "20M", "HT", "1T", "02", "28", - "FCC", "2.4G", "20M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "28", - "MKK", "2.4G", "20M", "HT", "1T", "09", "28", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "28", - "MKK", "2.4G", "20M", "HT", "1T", "10", "28", - "FCC", "2.4G", "20M", "HT", "1T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "28", - "MKK", "2.4G", "20M", "HT", "1T", "11", "28", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "28", - "MKK", "2.4G", "20M", "HT", "1T", "12", "28", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "28", - "MKK", "2.4G", "20M", "HT", "1T", "13", "28", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "26", - "MKK", "2.4G", "20M", "HT", "2T", "01", "28", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "26", - "MKK", "2.4G", "20M", "HT", "2T", "02", "28", - "FCC", "2.4G", "20M", "HT", "2T", "03", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "26", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "26", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "26", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "26", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "26", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", - "MKK", "2.4G", "20M", "HT", "2T", "09", "28", - "FCC", "2.4G", "20M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "26", - "MKK", "2.4G", "20M", "HT", "2T", "10", "28", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "26", - "MKK", "2.4G", "20M", "HT", "2T", "11", "28", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "26", - "MKK", "2.4G", "20M", "HT", "2T", "12", "28", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "26", - "MKK", "2.4G", "20M", "HT", "2T", "13", "28", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "26", - "MKK", "2.4G", "20M", "HT", "2T", "01", "26", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "26", - "MKK", "2.4G", "20M", "HT", "2T", "02", "26", - "FCC", "2.4G", "20M", "HT", "2T", "03", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "26", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "26", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "26", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "26", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "26", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", - "MKK", "2.4G", "20M", "HT", "2T", "09", "26", - "FCC", "2.4G", "20M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "26", - "MKK", "2.4G", "20M", "HT", "2T", "10", "26", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "26", - "MKK", "2.4G", "20M", "HT", "2T", "11", "26", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "26", - "MKK", "2.4G", "20M", "HT", "2T", "12", "26", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "26", - "MKK", "2.4G", "20M", "HT", "2T", "13", "26", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "28", - "MKK", "2.4G", "40M", "HT", "1T", "03", "28", - "FCC", "2.4G", "40M", "HT", "1T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", - "MKK", "2.4G", "40M", "HT", "1T", "04", "28", - "FCC", "2.4G", "40M", "HT", "1T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", - "MKK", "2.4G", "40M", "HT", "1T", "05", "28", - "FCC", "2.4G", "40M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "30", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "30", - "FCC", "2.4G", "40M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "30", - "FCC", "2.4G", "40M", "HT", "1T", "09", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", - "MKK", "2.4G", "40M", "HT", "1T", "09", "28", - "FCC", "2.4G", "40M", "HT", "1T", "10", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", - "MKK", "2.4G", "40M", "HT", "1T", "10", "28", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "28", - "MKK", "2.4G", "40M", "HT", "1T", "11", "28", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63" -}; - -void -ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8192E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8192E_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_RadioA[] = { + 0x07F, 0x00000082, + 0x081, 0x0003FC00, + 0x000, 0x00030000, + 0x008, 0x00008400, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000064, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000394C, + 0xA0000000, 0x00000000, + 0x01B, 0x0000394C, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF9F1, + 0x0B1, 0x00055418, + 0x0B2, 0x0008CC00, + 0x0B4, 0x00043083, + 0x0B5, 0x00008166, + 0x0B6, 0x0000803E, + 0x0B7, 0x0001C69F, + 0x0B8, 0x0000407F, + 0x0B9, 0x00090001, + 0x0BA, 0x00040001, + 0x0BB, 0x00000400, + 0x0BC, 0x00000078, + 0x0BD, 0x000B3333, + 0x0BE, 0x00033340, + 0x0BF, 0x00000000, + 0x0C0, 0x00005999, + 0x0C1, 0x00009999, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0xA0000000, 0x00000000, + 0x01C, 0x00000000, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x00069545, + 0x052, 0x0007E45E, + 0x053, 0x00000071, + 0x056, 0x00051FF3, + 0x035, 0x000000A8, + 0x035, 0x000001E2, + 0x035, 0x000002A8, + 0x036, 0x00001C24, + 0x036, 0x00009C24, + 0x036, 0x00011C24, + 0x036, 0x00019C24, + 0x018, 0x00000C07, + 0x05A, 0x00048000, + 0x019, 0x000739D0, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00068180, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000014E, + 0x087, 0x00049F80, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000014E, + 0x087, 0x00049F80, + 0xA0000000, 0x00000000, + 0x086, 0x0000014E, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F52B0, + 0xA0000000, 0x00000000, + 0x03B, 0x000F02B0, + 0xB0000000, 0x00000000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0xA0000000, 0x00000000, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0xB0000000, 0x00000000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00078730, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00070730, + 0xA0000000, 0x00000000, + 0x03B, 0x00078730, + 0xB0000000, 0x00000000, + 0x03B, 0x00060FB0, + 0x03B, 0x0005FFA0, + 0x03B, 0x00040620, + 0x03B, 0x00037090, + 0x03B, 0x00020080, + 0x03B, 0x0001F060, + 0x03B, 0x0000FFB0, + 0x0EF, 0x000000A0, + 0xFFE, 0x00000000, + 0x018, 0x0000FC07, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E70, + +}; + +void +ODM_ReadAndConfig_MP_8192E_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8192E_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8192E(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8192E_RadioA(void) +{ + return 58; +} + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +u4Byte Array_MP_8192E_RadioB[] = { + 0x07F, 0x00000082, + 0x081, 0x0003FC00, + 0x000, 0x00030000, + 0x008, 0x00008400, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000064, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x01B, 0x0000146C, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x0000394C, + 0xA0000000, 0x00000000, + 0x01B, 0x0000394C, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x07F, 0x00000082, + 0x081, 0x0003F000, + 0x083, 0x00000000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00001C00, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x01C, 0x00000000, + 0xA0000000, 0x00000000, + 0x01C, 0x00000000, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x00069545, + 0x052, 0x0007E42E, + 0x053, 0x00000071, + 0x056, 0x00051FF3, + 0x035, 0x000000A8, + 0x035, 0x000001E0, + 0x035, 0x000002A8, + 0x036, 0x00001CA8, + 0x036, 0x00009C24, + 0x036, 0x00011C24, + 0x036, 0x00019C24, + 0x018, 0x00000C07, + 0x05A, 0x00048000, + 0x019, 0x000739D0, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A093, + 0x034, 0x0000908F, + 0x034, 0x0000808C, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005DC8, + 0x034, 0x00004DC5, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x00000014, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00068180, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00049F80, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x086, 0x0000010E, + 0x087, 0x000F5F80, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00049F80, + 0xA0000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000F0730, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F52B0, + 0xA0000000, 0x00000000, + 0x03B, 0x000F02B0, + 0xB0000000, 0x00000000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000E0730, + 0x03B, 0x000D0020, + 0x03B, 0x000C0020, + 0x03B, 0x000B0760, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x00080000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0xA0000000, 0x00000000, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0xB0000000, 0x00000000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000003, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00078730, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x0000000a, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000001, 0x0000000f, 0x40000000, 0x00000000, + 0x03B, 0x000787B0, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00070730, + 0xA0000000, 0x00000000, + 0x03B, 0x00078730, + 0xB0000000, 0x00000000, + 0x03B, 0x00060FB0, + 0x03B, 0x0005FFA0, + 0x03B, 0x00040620, + 0x03B, 0x00037090, + 0x03B, 0x00020080, + 0x03B, 0x0001F060, + 0x03B, 0x0000FFB0, + 0x0EF, 0x000000A0, + 0x000, 0x00010159, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E70, + +}; + +void +ODM_ReadAndConfig_MP_8192E_RadioB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8192E_RadioB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8192E_RadioB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_RadioB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioB_8192E(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8192E_RadioB(void) +{ + return 58; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8192E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8192E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8192E[] = {0, 0, 0, 0, 1, 1, 1, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 7, 7, 7, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8192E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8192E[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8192E[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8192E[] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8192E[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8192E[] = {0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8192E_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "CCK", "2T", "01", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "01", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "01", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "02", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "02", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "02", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "03", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "03", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "03", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "04", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "04", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "04", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "05", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "05", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "05", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "06", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "06", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "06", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "07", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "07", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "07", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "08", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "08", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "08", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "09", "26", + "ETSI", "2.4G", "20M", "CCK", "2T", "09", "22", + "MKK", "2.4G", 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"2.4G", "20M", "HT", "2T", "07", "26", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", + "MKK", "2.4G", "20M", "HT", "2T", "09", "26", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "26", + "MKK", "2.4G", "20M", "HT", "2T", "10", "26", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "26", + "MKK", "2.4G", "20M", "HT", "2T", "11", "26", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "26", + "MKK", "2.4G", "20M", "HT", "2T", "12", "26", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "26", + "MKK", "2.4G", "20M", "HT", "2T", "13", "26", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "28", + "MKK", "2.4G", "40M", "HT", "1T", "03", "28", + "FCC", "2.4G", "40M", "HT", "1T", "04", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", + "MKK", "2.4G", "40M", "HT", "1T", "04", "28", + "FCC", "2.4G", "40M", "HT", "1T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", + "MKK", "2.4G", "40M", "HT", "1T", "05", "28", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "FCC", "2.4G", "40M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", + "MKK", "2.4G", "40M", "HT", "1T", "09", "28", + "FCC", "2.4G", "40M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", + "MKK", "2.4G", "40M", "HT", "1T", "10", "28", + "FCC", "2.4G", "40M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "28", + "MKK", "2.4G", "40M", "HT", "1T", "11", "28", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63" +}; + +void +ODM_ReadAndConfig_MP_8192E_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8192E_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8192E_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8192E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8192E_SAR_5mm.TXT +******************************************************************************/ + +const char *Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "CCK", "2T", "01", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "01", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "01", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "02", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "02", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "02", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "03", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "03", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "03", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "04", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "04", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "04", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "05", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "05", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "05", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "06", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "06", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "06", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "07", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "07", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "07", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "08", "24", + "ETSI", "2.4G", "20M", "CCK", "2T", "08", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "08", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "09", "22", + "ETSI", "2.4G", "20M", "CCK", "2T", "09", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "09", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "10", "22", + "ETSI", "2.4G", "20M", "CCK", "2T", "10", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "10", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "11", "22", + "ETSI", "2.4G", "20M", "CCK", "2T", "11", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "11", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "2T", "12", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "12", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "2T", "13", "22", + "MKK", "2.4G", "20M", "CCK", "2T", "13", "26", + "FCC", "2.4G", "20M", "CCK", "2T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "2T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "2T", "14", "26", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", 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"06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "FCC", "2.4G", "40M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", + "MKK", "2.4G", "40M", "HT", "1T", "09", "28", + "FCC", "2.4G", "40M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", + "MKK", "2.4G", "40M", "HT", "1T", "10", "28", + "FCC", "2.4G", "40M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "28", + "MKK", "2.4G", "40M", "HT", "1T", "11", "28", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63" +}; + +void +ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8192E_TXPWR_LMT_8192E_SAR_5mm; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8192E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.h index 93679aefbe2..cc0eddfa5f8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halhwimg8192e_rf.h @@ -1,109 +1,109 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8192E_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8192E_H -#define __INC_MP_RF_HW_IMG_8192E_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_RadioA(void); - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_RadioB(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT(void); - -/****************************************************************************** -* TXPWR_LMT_8192E_SAR_5mm.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8192E_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8192E_H +#define __INC_MP_RF_HW_IMG_8192E_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_RadioA(void); + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_RadioB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_RadioB(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT(void); + +/****************************************************************************** +* TXPWR_LMT_8192E_SAR_5mm.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.c index e9ba0ffa9be..c3017362299 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.c @@ -1,3315 +1,3315 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "../mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_92E 6 - -/*---------------------------Define Local Constant---------------------------*/ - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - -#if 0 -void setIqkMatrix_8192E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y -) -{ - s4Byte ele_A = 0, ele_D, ele_C = 0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; - - /*new element A = element D x X*/ - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; - - /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ - switch (RFPath) { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif - - ODM_ResetIQKResult(pDM_Odm); - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); - #else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); - #endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); - #endif - #endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8192E(pDM_Odm, FALSE); - #else - PHY_IQCalibrate_8192E(Adapter, FALSE); - #endif - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); - #else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); - #endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); - #endif - #endif -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr92E( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - if (Method == TXAGC) { - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - #if (MP_DRIVER != 1) - PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - #else - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase[RF_PATH_A]); - TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - #endif - - #endif - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - #endif - - } else if (Method == BBSWING) { - // Adjust BB swing by CCK filter coefficient - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][7]); - } - - // Adjust BB swing by OFDM IQ matrix - if (RFPath == RF_PATH_A) { - setIqkMatrix_8192E(pDM_Odm, pDM_Odm->BbSwingIdxOfdm[RF_PATH_A], RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - } else if (RFPath == RF_PATH_B) { - setIqkMatrix_8192E(pDM_Odm, pDM_Odm->BbSwingIdxOfdm[RF_PATH_B], RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - } - } else - return; -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8192E( - IN PDM_ODM_T pDM_Odm, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -) -{ - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; -} - - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE_92E; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE_92E; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; - pConfig->RfPathCount = 1; - pConfig->ThermalRegAddr = RF_T_METER_92E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; - pConfig->DoIQK = DoIQK_8192E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; -} -#endif - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C, regEA4, tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - /*8192E IQK V2.1 20150713*/ - /*1 Tx IQK*/ - //path-A IQK setting - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); - - - - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51100); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - /* PA/PAD controlled by 0x0*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); - return result; - - } - - u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); -/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000) >> 16) != 0x132) && - (((regEAC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - u4Byte regEAC, regEB4, regEBC; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - /*1 Tx IQK*/ - //path-B IQK setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); - - /*disable path-A PI, prevent path-A re-LOK*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - #if 0 - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); - #endif - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - /*enable path-A PI*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); - - return result; -} - - - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); - return result; - } - - u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ - (((regEC4 & 0x03FF0000) >> 16) != 0x132) && - (((regECC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); - - return result; - - -} - - -VOID -_PHY_PathAFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly -) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - #if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; - #endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only -) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); - - if (bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -/* MP Already declare in odm.c*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0 ; i < RegisterNum ; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); -} - - -VOID -_PHY_SaveMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); -} - -VOID -_PHY_ReloadMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - #if 1 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); - #else - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); - #endif -} - - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -) -{ - u4Byte pathOn; - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; - if (FALSE == is2T) { - pathOn = 0x0fc01616; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); - } else - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - - for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); - -} - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - //u4Byte i = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - /* - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - */ - #if 1 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); - #else - ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); - ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); - ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); - #endif - - -} - -VOID -_PHY_PathAStandBy_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); -// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetRFReg(pDM_Odm, 0x0, 0x0, bRFRegOffsetMask, 0x10000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode -) -{ - u4Byte mode; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 -) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ -/*#else*/ - BOOLEAN is2T = TRUE; -/*#endif*/ - - s4Byte tmp1 = 0, tmp2 = 0; - - if (is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i] + result[c1][i + 1] == 0) - final_candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - final_candidate[(i / 4)] = c1; - else - SimularityBitMap = SimularityBitMap | (1 << i); - } else - SimularityBitMap = SimularityBitMap | (1 << i); - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); - - if (SimularityBitMap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (final_candidate[i] != 0xFF) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[final_candidate[i]][j]; - bResult = FALSE; - } - } - return bResult; - } else { - - if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ - for (i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ - for (i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ - for (i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - - } - - if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ - for (i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - } - - return FALSE; - } - - - -} - - - -VOID -phy_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte t, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u4Byte i; - u1Byte PathAOK = 0, PathBOK = 0; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - 0xe68, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - /*since 92C & 92D have the different define in IQK_BB_REG*/ - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - 0x92c, 0x930, - 0x938, rCCK0_AFESetting - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; - #else - #if MP_DRIVER - const u4Byte retryCount = 9; - #else - const u4Byte retryCount = 2; - #endif - #endif - - /*Note: IQ calibration must be performed after loading*/ - /*PHY_REG.txt,and radio_a,radio_b.txt*/ - - //u4Byte bbvalue; - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 2; - #endif - #endif - - - if (t == 0) { - /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ - /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ - - /*Save ADDA parameters, turn Path A ADDA on*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); - #else - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); - #endif - - /* - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch_92E(pAdapter, TRUE); - #else - _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); - #endif - } - */ - //BB setting - /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); - -// -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - - if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { // external LNA / external PA = 1 /0 - //PAPE force to high - //just for high power with external LNA, without external PA - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); - } else if (pDM_Odm->ExtPA) { // external PA = 1 - //PAPE force to low - //just for high power with external PA, without external LNA - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); - } - - -// if(is2T) -// { -// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); -// } - - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #endif - - - //Page B init - //AP or IQK - /* - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } - */ - // IQ calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); - #else - PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); - #endif -// if(PathAOK == 0x03){ - if (PathAOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); - result[t][0] = 0x100; - result[t][1] = 0x0; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - -//path A RXIQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); - #else - PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - result[t][2] = 0x100; - result[t][3] = 0x0; - } - } - - if (0x00 == PathAOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - - #endif - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy_92E(pAdapter); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathAStandBy_92E(pDM_Odm); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - // IQ calibration setting - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - -//path B Tx IQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8192E(pAdapter); - #else - PathBOK = phy_PathB_IQK_8192E(pDM_Odm); - #endif -// if(PathBOK == 0x03){ - if (PathBOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Fail!!\n")); - result[t][4] = 0x100; - result[t][5] = 0x0; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -//path B RX IQK - #if 1 - - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); - #else - PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); - result[t][6] = 0x100; - result[t][7] = 0x0; - } - } - - if (0x00 == PathBOK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - /**/ - } - #endif - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { - - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - -/*Allen initial gain 0xc50*/ - /* Restore RX initial gain*/ - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); - -} - - -VOID -phy_LCCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - u1Byte tmpReg; - u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - if ((tmpReg & 0x70) != 0) { - //1. Read original RF mode - //Path-A - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); - } - - //3. Read RF reg18 - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } else /*Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 - }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 - }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB - }; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB - }; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000 - }; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000 - }; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - - #if MP_DRIVER == 1 - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if (!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. - #if MP_DRIVER != 1 - return; - #endif - //settings adjust for normal chip - for (index = 0; index < PATH_NUM; index ++) { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for (index = 0; index < APK_BB_REG_NUM; index ++) { - for (path = 0; path < pathbound; path++) { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for (index = 0; index < APK_BB_REG_NUM ; index++) { - if (index == 0) /*skip*/ - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - /*save MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - for (path = 0; path < pathbound; path++) { - - - if (path == ODM_RF_PATH_A) { - /*path A APK*/ - /*load APK setting*/ - /*path-A*/ - offset = rPdp_AntA; - for (index = 0; index < 11; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for (; index < 13; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else if (path == ODM_RF_PATH_B) { - /*path B APK*/ - /*load APK setting*/ - /*path-B*/ - offset = rPdp_AntB; - for (index = 0; index < 10; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for (; index < 13; index ++) { /*offset 0xb68, 0xb6c*/ - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); - #else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); - #endif - - //Path A AFE all on, path B AFE All off or vise versa - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if (path == 0) { - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } else { /*path B*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - else { /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta + 14) / 2); - if (delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for (index = 0; index < APK_BB_REG_NUM; index++) { - if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ - continue; - - tmpReg = APK_RF_init_value[path][index]; - #if 1 - if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if (!(tmpReg & BIT15)) /*sign bit 0*/ - BB_offset = -BB_offset; - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if (BB_offset < 0) { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } else - tmpReg = tmpReg | BIT15; - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } - #endif - - ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); - #endif - - /* PA11+PAD01111, one shot*/ - i = 0; - do { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } while (tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - /*reload MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*reload BB default value*/ - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //reload RF path default value - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); - if (path == ODM_RF_PATH_B) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if (path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - u1Byte channelToIQK = 7; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #else - prtl8192cd_priv priv = pDM_Odm->priv; - - #ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } - #endif - /* - if (priv->pshare->IQK_92E_done) - bReCovery= 1; - priv->pshare->IQK_92E_done = 1; - */ - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - #ifdef DISABLE_BB_RF - return; - #endif - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) - #else /*for ODM_WIN*/ - if (bReCovery && - (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ - #endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #endif - return; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - priv->pshare->IQK_total_cnt++; - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[3][i] = 0x100; - else - result[3][i] = 0; - } - - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); -// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); - - #else - -// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); - phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); - #endif - - - if (i == 1) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); - #else - is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); - #endif - - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); - #else - is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); - #endif - - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); - - break; - } - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); - #else - is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); - #endif - - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - /* - for(i = 0; i < 4; i++) - RegTmp &= result[3][i*2]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - */ - final_candidate = 3; - - } - } - } - - if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { - for (i = 0; i < 8; i++) { - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[final_candidate][i] = 0x100; - else - result[final_candidate][i] = 0; - } - } - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - panic_printk("Load IQK defult value"); - priv->pshare->IQK_fail_cnt++; - } - - if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #else - _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #endif - } - - if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -//Allen -// if (IS_92C_SERIAL(pHalData->VersionID)) -// { - _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); -// } - #else - _PHY_PathBFillIQKMatrix_92E(pDM_Odm, bPathBOK, result, final_candidate, (RegEC4 == 0)); - #endif - } - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); - #else - Indexforchannel = 0; - #endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - -} - - -VOID -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - - - - - #if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - - #ifdef DISABLE_BB_RF - return; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_2T2R(pHalData->VersionID)) - phy_LCCalibrate_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8192E(pAdapter, FALSE); - #else - phy_LCCalibrate_8192E(pDM_Odm, FALSE); - #endif - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - #ifdef DISABLE_BB_RF - return; - #endif - - return; - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if FOR_BRAZIL_PRETEST != 1 - if (pDM_Odm->RFCalibrateInfo.bAPKdone) - #endif - return; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - phy_APCalibrate_8192E(pAdapter, delta, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8192E(pAdapter, delta, FALSE); - #else - phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); - #endif - } -} -VOID phy_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (!pAdapter->bHWInitReady) - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (pAdapter->hw_init_completed == _FALSE) - #endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - #endif - - if (is2T) { //92C - if (bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6, 0x2); //BT - } else { //88C - - // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), - // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8 | BIT9, 0x0); - ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table - - if (bMain) { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14 | BIT13 | BIT12, 0x1); // Tx Main (HW control)(The right antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3, 0x1); // AntDivType = TRDiv, right antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna - - } else { - //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) - //4 [ Tx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14 | BIT13 | BIT12, 0x0); // Tx Aux (HW control)(The left antenna) - - //4 [ Rx ] - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3, 0x0); // AntDivType = TRDiv, left antenna - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna - } - - } -} -VOID PHY_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #endif - - #ifdef DISABLE_BB_RF - return; - #endif - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8192E(pAdapter, bMain, FALSE); - #else - phy_SetRFPathSwitch_8192E(pDM_Odm, bMain, FALSE); - #endif - } -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion_92E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T -) -{ - #if (RT_PLATFORM == PLATFORM_WINDOWS) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0 - }; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - - //save MAC default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); - #endif - - //save RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (index = 0; index < DP_RF_REG_NUM; index++) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #else - RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #endif - } - - //save AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //Path A/B AFE all on - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); - - //BB register setting - for (index = 0; index < DP_BB_REG_NUM; index++) { - if (index < 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); - else if (index == 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); - } - - //MAC register setting - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*PAGE-E IQC setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - //path_A DPK - //Path B to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - - // PA gain = 11 & PAD1 => tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for (i = rPdp_AntA; i <= 0xb3c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for (i = 0xb4c; i <= 0xb5c; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - /*DPK path B*/ - if (is2T) { - /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - /* LUTs => tx_agc*/ - /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ - /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ - /* PA gain = 01 => tx_agc 0b ~0d*/ - /* PA gain = 00 => tx_agc 0a ~00*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - /* PAGE_B for Path-A inner loopback DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - /*----send one shot signal----*/ - /* Path B*/ - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - /* PA gain = 11 => tx_agc = 1a*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); - - /* PAGE_B for Path-B DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for (i = 0xb60; i <= 0xb9c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for (i = 0xbac; i <= 0xbbc; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - - //reload RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (i = 0 ; i < DP_RF_REG_NUM ; i++) - ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off - - /*reload AFE default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); - #endif -} - -VOID -PHY_DigitalPredistortion_8192E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - #ifdef DISABLE_BB_RF - return; - #endif - - return; - - if (pDM_Odm->RFCalibrateInfo.bDPdone) - return; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_92C_SERIAL(pHalData->VersionID)) - phy_DigitalPredistortion_92E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - phy_DigitalPredistortion_92E(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - if (!pAdapter->bHWInitReady) { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if (is2T) { // - if (ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6) == 0x01) - return TRUE; - else - return FALSE; - } else { - if ((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #ifdef DISABLE_BB_RF - return TRUE; - #endif - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_2T2R(pHalData->VersionID)) - return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); - #else - return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); - #endif - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_92E 6 + +/*---------------------------Define Local Constant---------------------------*/ + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +#if 0 +void setIqkMatrix_8192E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; + + /*new element A = element D x X*/ + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; + + /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ + switch (RFPath) { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #endif + + ODM_ResetIQKResult(pDM_Odm); + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); + #else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); + #endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); + #endif + #endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8192E(pDM_Odm, FALSE); + #else + PHY_IQCalibrate_8192E(Adapter, FALSE); + #endif + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); + #else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); + #endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); + #endif + #endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr92E( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + if (Method == TXAGC) { + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + #if (MP_DRIVER != 1) + PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + #else + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr << 16) | (pwr << 8) | (pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase[RF_PATH_A]); + TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + #endif + + #endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + #endif + + } else if (Method == BBSWING) { + // Adjust BB swing by CCK filter coefficient + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_92E[pDM_Odm->BbSwingIdxCck][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_92E[pDM_Odm->BbSwingIdxCck][7]); + } + + // Adjust BB swing by OFDM IQ matrix + if (RFPath == RF_PATH_A) { + setIqkMatrix_8192E(pDM_Odm, pDM_Odm->BbSwingIdxOfdm[RF_PATH_A], RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + } else if (RFPath == RF_PATH_B) { + setIqkMatrix_8192E(pDM_Odm, pDM_Odm->BbSwingIdxOfdm[RF_PATH_B], RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + } + } else + return; +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8192E( + IN PDM_ODM_T pDM_Odm, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +) +{ + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; +} + + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE_92E; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE_92E; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; + pConfig->RfPathCount = 1; + pConfig->ThermalRegAddr = RF_T_METER_92E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; + pConfig->DoIQK = DoIQK_8192E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; +} +#endif + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + /*8192E IQK V2.1 20150713*/ + /*1 Tx IQK*/ + //path-A IQK setting + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); + + + + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51100); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + /* PA/PAD controlled by 0x0*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); + return result; + + } + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); +/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regEB4, regEBC; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + /*1 Tx IQK*/ + //path-B IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); + + /*disable path-A PI, prevent path-A re-LOK*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + #if 0 + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); + #endif + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + /*enable path-A PI*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); + + return result; +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); + return result; + } + + u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly +) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + #if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; + #endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only +) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); + + if (bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +/* MP Already declare in odm.c*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0 ; i < RegisterNum ; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +VOID +_PHY_ReloadMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + #if 1 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); + #else + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); + #endif +} + + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +) +{ + u4Byte pathOn; + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; + if (FALSE == is2T) { + pathOn = 0x0fc01616; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); + } else + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + + for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); + +} + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + //u4Byte i = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + /* + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + */ + #if 1 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); + #else + ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); + ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); + ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); + #endif + + +} + +VOID +_PHY_PathAStandBy_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); +// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetRFReg(pDM_Odm, 0x0, 0x0, bRFRegOffsetMask, 0x10000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode +) +{ + u4Byte mode; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 +) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ +/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ +/*#else*/ + BOOLEAN is2T = TRUE; +/*#endif*/ + + s4Byte tmp1 = 0, tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i] + result[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + SimularityBitMap = SimularityBitMap | (1 << i); + } else + SimularityBitMap = SimularityBitMap | (1 << i); + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); + + if (SimularityBitMap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + } else { + + if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ + for (i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ + for (i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + + } + + if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + } + + return FALSE; + } + + + +} + + + +VOID +phy_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u4Byte i; + u1Byte PathAOK = 0, PathBOK = 0; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + 0xe68, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + /*since 92C & 92D have the different define in IQK_BB_REG*/ + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + 0x92c, 0x930, + 0x938, rCCK0_AFESetting + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; + #else + #if MP_DRIVER + const u4Byte retryCount = 9; + #else + const u4Byte retryCount = 2; + #endif + #endif + + /*Note: IQ calibration must be performed after loading*/ + /*PHY_REG.txt,and radio_a,radio_b.txt*/ + + //u4Byte bbvalue; + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 2; + #endif + #endif + + + if (t == 0) { + /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ + /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ + + /*Save ADDA parameters, turn Path A ADDA on*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); + #else + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); + #endif + + /* + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch_92E(pAdapter, TRUE); + #else + _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); + #endif + } + */ + //BB setting + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); + +// +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + + if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { // external LNA / external PA = 1 /0 + //PAPE force to high + //just for high power with external LNA, without external PA + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); + } else if (pDM_Odm->ExtPA) { // external PA = 1 + //PAPE force to low + //just for high power with external PA, without external LNA + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); + } + + +// if(is2T) +// { +// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); +// } + + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #endif + + + //Page B init + //AP or IQK + /* + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + */ + // IQ calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); + #else + PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); + #endif +// if(PathAOK == 0x03){ + if (PathAOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); + result[t][0] = 0x100; + result[t][1] = 0x0; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + +//path A RXIQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); + #else + PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + result[t][2] = 0x100; + result[t][3] = 0x0; + } + } + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + + #endif + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy_92E(pAdapter); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathAStandBy_92E(pDM_Odm); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + // IQ calibration setting + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + +//path B Tx IQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8192E(pAdapter); + #else + PathBOK = phy_PathB_IQK_8192E(pDM_Odm); + #endif +// if(PathBOK == 0x03){ + if (PathBOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Fail!!\n")); + result[t][4] = 0x100; + result[t][5] = 0x0; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +//path B RX IQK + #if 1 + + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); + #else + PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); + result[t][6] = 0x100; + result[t][7] = 0x0; + } + } + + if (0x00 == PathBOK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + /**/ + } + #endif + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { + + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + +/*Allen initial gain 0xc50*/ + /* Restore RX initial gain*/ + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + if ((tmpReg & 0x70) != 0) { + //1. Read original RF mode + //Path-A + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); + } + + //3. Read RF reg18 + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } else /*Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 + }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 + }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB + }; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB + }; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000 + }; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000 + }; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + + #if MP_DRIVER == 1 + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if (!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. + #if MP_DRIVER != 1 + return; + #endif + //settings adjust for normal chip + for (index = 0; index < PATH_NUM; index ++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for (index = 0; index < APK_BB_REG_NUM; index ++) { + for (path = 0; path < pathbound; path++) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for (index = 0; index < APK_BB_REG_NUM ; index++) { + if (index == 0) /*skip*/ + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + /*save MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + for (path = 0; path < pathbound; path++) { + + + if (path == ODM_RF_PATH_A) { + /*path A APK*/ + /*load APK setting*/ + /*path-A*/ + offset = rPdp_AntA; + for (index = 0; index < 11; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for (; index < 13; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else if (path == ODM_RF_PATH_B) { + /*path B APK*/ + /*load APK setting*/ + /*path-B*/ + offset = rPdp_AntB; + for (index = 0; index < 10; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for (; index < 13; index ++) { /*offset 0xb68, 0xb6c*/ + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); + #else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); + #endif + + //Path A AFE all on, path B AFE All off or vise versa + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if (path == 0) { + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } else { /*path B*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + else { /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta + 14) / 2); + if (delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ + continue; + + tmpReg = APK_RF_init_value[path][index]; + #if 1 + if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if (!(tmpReg & BIT15)) /*sign bit 0*/ + BB_offset = -BB_offset; + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if (BB_offset < 0) { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } else + tmpReg = tmpReg | BIT15; + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } + #endif + + ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); + #endif + + /* PA11+PAD01111, one shot*/ + i = 0; + do { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } while (tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + /*reload MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*reload BB default value*/ + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //reload RF path default value + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); + if (path == ODM_RF_PATH_B) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if (path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + u1Byte channelToIQK = 7; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #else + prtl8192cd_priv priv = pDM_Odm->priv; + + #ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } + #endif + /* + if (priv->pshare->IQK_92E_done) + bReCovery= 1; + priv->pshare->IQK_92E_done = 1; + */ + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + #ifdef DISABLE_BB_RF + return; + #endif + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) + #else /*for ODM_WIN*/ + if (bReCovery && + (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ + #endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #endif + return; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + priv->pshare->IQK_total_cnt++; + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); +// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); + + #else + +// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); + phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); + #endif + + + if (i == 1) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); + #else + is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); + #endif + + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); + #else + is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); + #endif + + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); + + break; + } + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); + #else + is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); + #endif + + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + /* + for(i = 0; i < 4; i++) + RegTmp &= result[3][i*2]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + */ + final_candidate = 3; + + } + } + } + + if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { + for (i = 0; i < 8; i++) { + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[final_candidate][i] = 0x100; + else + result[final_candidate][i] = 0; + } + } + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + panic_printk("Load IQK defult value"); + priv->pshare->IQK_fail_cnt++; + } + + if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #else + _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #endif + } + + if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +//Allen +// if (IS_92C_SERIAL(pHalData->VersionID)) +// { + _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); +// } + #else + _PHY_PathBFillIQKMatrix_92E(pDM_Odm, bPathBOK, result, final_candidate, (RegEC4 == 0)); + #endif + } + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); + #else + Indexforchannel = 0; + #endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + +} + + +VOID +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + + + + + #if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + + #ifdef DISABLE_BB_RF + return; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_2T2R(pHalData->VersionID)) + phy_LCCalibrate_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8192E(pAdapter, FALSE); + #else + phy_LCCalibrate_8192E(pDM_Odm, FALSE); + #endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + #ifdef DISABLE_BB_RF + return; + #endif + + return; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if FOR_BRAZIL_PRETEST != 1 + if (pDM_Odm->RFCalibrateInfo.bAPKdone) + #endif + return; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_APCalibrate_8192E(pAdapter, delta, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8192E(pAdapter, delta, FALSE); + #else + phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); + #endif + } +} +VOID phy_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (!pAdapter->bHWInitReady) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pAdapter->hw_init_completed == _FALSE) + #endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + #endif + + if (is2T) { //92C + if (bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6, 0x2); //BT + } else { //88C + + // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), + // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW) + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8 | BIT9, 0x0); + ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table + + if (bMain) { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14 | BIT13 | BIT12, 0x1); // Tx Main (HW control)(The right antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3, 0x1); // AntDivType = TRDiv, right antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna + + } else { + //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna) + //4 [ Tx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14 | BIT13 | BIT12, 0x0); // Tx Aux (HW control)(The left antenna) + + //4 [ Rx ] + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3, 0x0); // AntDivType = TRDiv, left antenna + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna + } + + } +} +VOID PHY_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #endif + + #ifdef DISABLE_BB_RF + return; + #endif + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8192E(pAdapter, bMain, FALSE); + #else + phy_SetRFPathSwitch_8192E(pDM_Odm, bMain, FALSE); + #endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion_92E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T +) +{ + #if (RT_PLATFORM == PLATFORM_WINDOWS) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0 + }; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + + //save MAC default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); + #endif + + //save RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (index = 0; index < DP_RF_REG_NUM; index++) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #else + RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #endif + } + + //save AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //Path A/B AFE all on + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); + + //BB register setting + for (index = 0; index < DP_BB_REG_NUM; index++) { + if (index < 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); + else if (index == 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); + } + + //MAC register setting + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*PAGE-E IQC setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + //path_A DPK + //Path B to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + + // PA gain = 11 & PAD1 => tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for (i = rPdp_AntA; i <= 0xb3c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for (i = 0xb4c; i <= 0xb5c; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + /*DPK path B*/ + if (is2T) { + /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + /* LUTs => tx_agc*/ + /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ + /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ + /* PA gain = 01 => tx_agc 0b ~0d*/ + /* PA gain = 00 => tx_agc 0a ~00*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + /* PAGE_B for Path-A inner loopback DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + /*----send one shot signal----*/ + /* Path B*/ + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + /* PA gain = 11 => tx_agc = 1a*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); + + /* PAGE_B for Path-B DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for (i = 0xb60; i <= 0xb9c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for (i = 0xbac; i <= 0xbbc; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + + //reload RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (i = 0 ; i < DP_RF_REG_NUM ; i++) + ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off + + /*reload AFE default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); + #endif +} + +VOID +PHY_DigitalPredistortion_8192E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + #ifdef DISABLE_BB_RF + return; + #endif + + return; + + if (pDM_Odm->RFCalibrateInfo.bDPdone) + return; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_DigitalPredistortion_92E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + phy_DigitalPredistortion_92E(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + if (!pAdapter->bHWInitReady) { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if (is2T) { // + if (ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT6) == 0x01) + return TRUE; + else + return FALSE; + } else { + if ((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #ifdef DISABLE_BB_RF + return TRUE; + #endif + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) + return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); + #else + return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); + #endif + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.h index 008b28e54ea..14a172ba0ca 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ap.h @@ -1,146 +1,146 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8192E_H__ -#define __HAL_PHY_RF_8192E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -#define IQK_DELAY_TIME_92E 15 //ms -#else -#define IQK_DELAY_TIME_92E 10 -#endif - -#define index_mapping_NUM_92E 15 -#define AVG_THERMAL_NUM_92E 4 -#define RF_T_METER_92E 0x42 - -#include "../halphyrf_ap.h" - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -); - -VOID -GetDeltaSwingTable_8192E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -); - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -); - -VOID -ODM_TxPwrTrackSetPwr92E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -); - -//1 7. IQK - -void -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -); - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -); - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -_PHY_PathAStandBy( - IN PDM_ODM_T pDM_Odm -); -#endif - - - - -#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8192E_H__ +#define __HAL_PHY_RF_8192E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define IQK_DELAY_TIME_92E 15 //ms +#else +#define IQK_DELAY_TIME_92E 10 +#endif + +#define index_mapping_NUM_92E 15 +#define AVG_THERMAL_NUM_92E 4 +#define RF_T_METER_92E 0x42 + +#include "../halphyrf_ap.h" + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +); + +VOID +GetDeltaSwingTable_8192E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +); + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +); + +VOID +ODM_TxPwrTrackSetPwr92E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +); + +//1 7. IQK + +void +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +); + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +); + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +_PHY_PathAStandBy( + IN PDM_ODM_T pDM_Odm +); +#endif + + + + +#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.c index 6f78ac8069d..99e2d86565b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.c @@ -1,3674 +1,3674 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_92E 6 - -/*---------------------------Define Local Constant---------------------------*/ - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8192E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y -) -{ - s4Byte ele_A = 0, ele_D, ele_C = 0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; - - /*new element A = element D x X*/ - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; - - /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ - switch (RFPath) { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif - - ODM_ResetIQKResult(pDM_Odm); - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); - #else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); - #endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); - #endif - #endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8192E(pDM_Odm, FALSE); - #else - PHY_IQCalibrate_8192E(Adapter, FALSE); - #endif - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); - #else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); - #endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); - #endif - #endif -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr92E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 30; /*+0dB*/ - u1Byte PwrTrackingLimit_CCK = 28; /*-2dB*/ - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8192EA\n")); - - if (TxRate != 0xFF) { /*20130429 Mimic Modify High Rate BBSwing Limit.*/ - /*2 CCK*/ - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || TxRate == MGN_11M) - PwrTrackingLimit_CCK = 28; /*-2dB*/ - //2 OFDM - else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if (TxRate == MGN_54M) - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - - //2 HT - else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ - PwrTrackingLimit_OFDM = 38; /*+4dB*/ - else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - - else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) /*QPSK/BPSK*/ - PwrTrackingLimit_OFDM = 38; /*+4dB*/ - else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) /*16QAM*/ - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) /*64QAM*/ - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ - } - - if (Method == TXAGC) { - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*Remnant index equal to aboslute compensate value.*/ - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - - #if (MP_DRIVER == 1) - if (pDM_Odm->mp_mode == TRUE) { - if (RFPath == ODM_RF_PATH_A) { - //CCK Path A - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - //OFDM Path A - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); - TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } else if (RFPath == ODM_RF_PATH_B) { - //CCK Path B - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B]; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(B) Power = 0x%x\n", pwr)); - - //OFDM Path B - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); - TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); - } - } else - #endif - { - //PHY_SetTxPowerLevelByPath8192E(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function - //PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - if (RFPath == ODM_RF_PATH_A) { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - } else { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - } - } - - #endif - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - #endif - - } else if (Method == BBSWING) { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index <= 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE - 1; - else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) - Final_CCK_Swing_Index = 0; - - // Adjust BB swing by OFDM IQ matrix - if (RFPath == ODM_RF_PATH_A) { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - // Adjust BB swing by CCK filter coefficient - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - } else if (RFPath == ODM_RF_PATH_B) { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - } - } else if (Method == MIX_MODE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) { - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*CCK Follow Path-A and lower CCK index means higher power.*/ - - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index <= 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - - if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - /* Adjust BB swing by CCK filter coefficient*/ - - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - } else if (Final_CCK_Swing_Index <= 0) { /*Lowest CCK Index = 0*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); - - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); - } - - } - } - if (RFPath == ODM_RF_PATH_B) { - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index <= 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - } - } else - return; -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8192E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; - pConfig->RfPathCount = MAX_PATH_NUM_8192E; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; - pConfig->DoIQK = DoIQK_8192E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - /*8192E IQK V2.1 20150713*/ - /*1 Tx IQK*/ - //path-A IQK setting - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); - - - - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x511e0); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - /* PA/PAD controlled by 0x0*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); - return result; - - } - - u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); -/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000) >> 16) != 0x132) && - (((regEAC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - u4Byte regEAC, regEB4, regEBC; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - /*1 Tx IQK*/ - //path-B IQK setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); - - /*disable path-A PI, prevent path-A re-LOK*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - #if 0 - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); - #endif - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - /*enable path-A PI*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); - - return result; -} - - - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); - return result; - } - - u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ - (((regEC4 & 0x03FF0000) >> 16) != 0x132) && - (((regECC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); - - return result; - - -} - - -VOID -_PHY_PathAFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly -) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; - #endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only -) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); - - if (bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -/* MP Already declare in odm.c*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if (rtw_is_drv_stopped(padapter)|| Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s /%d/%d\n", - ?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0 ; i < RegisterNum ; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); -} - - -VOID -_PHY_SaveMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); -} - -VOID -_PHY_ReloadMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - #if 0 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); - #else - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); - #endif -} - - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -) -{ - u4Byte pathOn; - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; - if (FALSE == is2T) { - pathOn = 0x0fc01616; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); - } else - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - - for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); - -} - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - //u4Byte i = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - /* - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - */ - - //ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); - //ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); - //ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); - - ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); -// ODM_SetBBReg(pDM_Odm, 0x550, 0x0000ffff, 0x0015); - - -} - -VOID -_PHY_PathAStandBy_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); -// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PathBStandBy_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode -) -{ - u4Byte mode; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 -) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ -/*#else*/ - BOOLEAN is2T = TRUE; -/*#endif*/ - - s4Byte tmp1 = 0, tmp2 = 0; - - //if(is2T) - bound = 8; - //else - // bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i] + result[c1][i + 1] == 0) - final_candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - final_candidate[(i / 4)] = c1; - else - SimularityBitMap = SimularityBitMap | (1 << i); - } else - SimularityBitMap = SimularityBitMap | (1 << i); - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); - - if (SimularityBitMap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (final_candidate[i] != 0xFF) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[final_candidate[i]][j]; - bResult = FALSE; - } - } - return bResult; - } else { - - if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ - for (i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ - for (i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ - for (i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - - } - - if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ - for (i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - } - - return FALSE; - } - - - -} - - - -VOID -phy_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte t, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u4Byte i; - u1Byte PathAOK = 0, PathBOK = 0; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - /*since 92C & 92D have the different define in IQK_BB_REG*/ - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - 0x92c, 0x930, - 0x938, rCCK0_AFESetting - - }; - - u4Byte retryCount = 2; - - #if MP_DRIVER - if (pDM_Odm->mp_mode == TRUE) - retryCount = 9; - #endif - - /*Note: IQ calibration must be performed after loading*/ - /*PHY_REG.txt,and radio_a,radio_b.txt*/ - - //u4Byte bbvalue; - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 2; - #endif - #endif - - - if (t == 0) { - /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ - /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ - - /*Save ADDA parameters, turn Path A ADDA on*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); - #else - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); - #endif - - /* - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch_92E(pAdapter, TRUE); - #else - _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); - #endif - } - */ - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); - - if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { /* external LNA / external PA = 1 /0 */ - /*PAPE force to high*/ - /*just for high power with external LNA, without external PA*/ - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); - } else if (pDM_Odm->ExtPA) { /* external PA = 1*/ - /*PAPE force to low*/ - /*just for high power with external PA, without external LNA*/ - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); - } - - // IQ calibration setting -/*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathBStandBy_92E(pAdapter); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathBStandBy_92E(pDM_Odm); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - } - -//path A TXIQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); - #else - PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); - #endif -// if(PathAOK == 0x03){ - if (PathAOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -//path A RXIQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); - #else - PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - - if (0x00 == PathAOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - - #endif - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy_92E(pAdapter); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathAStandBy_92E(pDM_Odm); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - // IQ calibration setting - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - -//path B Tx IQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8192E(pAdapter); - #else - PathBOK = phy_PathB_IQK_8192E(pDM_Odm); - #endif -// if(PathBOK == 0x03){ - if (PathBOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - break; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -//path B RX IQK - #if 1 - - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); - #else - PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } - } - - if (0x00 == PathBOK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - /**/ - } - #endif - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { - - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - -/*Allen initial gain 0xc50*/ - /* Restore RX initial gain*/ - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); - -} - - -VOID -phy_LCCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - u1Byte tmpReg; - u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - if ((tmpReg & 0x70) != 0) { - //1. Read original RF mode - //Path-A - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); - } - - //3. Read RF reg18 - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } else /*Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 - }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 - }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB - }; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB - }; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000 - }; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000 - }; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - - #if MP_DRIVER == 1 - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if (!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -//#if MP_DRIVER != 1 - if (pDM_Odm->mp_mode == FALSE) - return; -//#endif - - //settings adjust for normal chip - for (index = 0; index < PATH_NUM; index++) { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for (index = 0; index < APK_BB_REG_NUM; index++) { - for (path = 0; path < pathbound; path++) { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for (index = 0; index < APK_BB_REG_NUM ; index++) { - if (index == 0) /*skip*/ - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - /*save MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - for (path = 0; path < pathbound; path++) { - - - if (path == ODM_RF_PATH_A) { - /*path A APK*/ - /*load APK setting*/ - /*path-A*/ - offset = rPdp_AntA; - for (index = 0; index < 11; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for (; index < 13; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else if (path == ODM_RF_PATH_B) { - /*path B APK*/ - /*load APK setting*/ - /*path-B*/ - offset = rPdp_AntB; - for (index = 0; index < 10; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - #else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - #endif - - offset = rConfig_AntA; - index = 11; - for (; index < 13; index++) { /*offset 0xb68, 0xb6c*/ - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); - #else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); - #endif - - //Path A AFE all on, path B AFE All off or vise versa - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if (path == 0) { - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } else { /*path B*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - else { /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta + 14) / 2); - if (delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for (index = 0; index < APK_BB_REG_NUM; index++) { - if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ - continue; - - tmpReg = APK_RF_init_value[path][index]; - #if 1 - if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if (!(tmpReg & BIT15)) /*sign bit 0*/ - BB_offset = -BB_offset; - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if (BB_offset < 0) { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } else - tmpReg = tmpReg | BIT15; - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } - #endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); - #endif - - /* PA11+PAD01111, one shot*/ - i = 0; - do { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } while (tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - /*reload MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*reload BB default value*/ - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //reload RF path default value - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if (path == ODM_RF_PATH_B) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if (path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta - }; - u4Byte StartTime; - s4Byte ProgressingTime; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #else - prtl8192cd_priv priv = pDM_Odm->priv; - - #ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } - #endif - - if (priv->pshare->IQK_88E_done) - bReCovery = 1; - priv->pshare->IQK_88E_done = 1; - - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if MP_DRIVER == 1 - if (pDM_Odm->mp_mode == TRUE) { - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - } - #endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - #if DISABLE_BB_RF - return; - #endif - - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) - #else /*for ODM_WIN*/ - if (bReCovery && - (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ - #endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #endif - return; - } - StartTime = ODM_GetCurrentTime(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[3][i] = 0x100; - else - result[3][i] = 0; - } - - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); -// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); - - #else - -// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); - phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); - #endif - - - if (i == 1) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); - #else - is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); - #endif - - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); - #else - is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); - #endif - - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); - - break; - } - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); - #else - is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); - #endif - - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - /* - for(i = 0; i < 4; i++) - RegTmp &= result[3][i*2]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - */ - final_candidate = 3; - - } - } - } - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - } - - if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #else - _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #endif - } - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - - #endif - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); - #else - Indexforchannel = 0; - #endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); - #endif - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); - -} - - -VOID -PHY_LCCalibrate_8192E( - PVOID pDM_VOID -) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - u4Byte StartTime; - s4Byte ProgressingTime; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - - - - - #if MP_DRIVER == 1 - if (pDM_Odm->mp_mode == TRUE) { - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - } - #endif - - - #if DISABLE_BB_RF - return; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - StartTime = ODM_GetCurrentTime(pDM_Odm); - - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_2T2R(pHalData->VersionID)) - phy_LCCalibrate_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8192E(pAdapter, FALSE); - #else - phy_LCCalibrate_8192E(pDM_Odm, FALSE); - #endif - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); -} - -VOID -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - #if DISABLE_BB_RF - return; - #endif - - return; - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if FOR_BRAZIL_PRETEST != 1 - if (pDM_Odm->RFCalibrateInfo.bAPKdone) - #endif - return; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_2T2R(pHalData->VersionID)) - phy_APCalibrate_8192E(pAdapter, delta, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8192E(pAdapter, delta, FALSE); - #else - phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); - #endif - } -} -VOID phy_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - // MAIN: WiFi - u4Byte reg = ODM_GetMACReg(pDM_Odm, 0x64, bMaskDWord); - reg &= 0xFFFFF000; - reg = (bMain) ? (reg | 0x00000100) : (reg | 0x00000004); - ODM_SetMACReg(pDM_Odm, 0x64, bMaskDWord, reg); - -} - -VOID PHY_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #endif - - #if DISABLE_BB_RF - return; - #endif - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); - #endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion_92E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T -) -{ - #if (RT_PLATFORM == PLATFORM_WINDOWS) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0 - }; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - - //save MAC default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); - #endif - - //save RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (index = 0; index < DP_RF_REG_NUM; index++) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #else - RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #endif - } - - //save AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //Path A/B AFE all on - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); - - //BB register setting - for (index = 0; index < DP_BB_REG_NUM; index++) { - if (index < 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); - else if (index == 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); - } - - //MAC register setting - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*PAGE-E IQC setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - //path_A DPK - //Path B to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - - // PA gain = 11 & PAD1 => tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for (i = rPdp_AntA; i <= 0xb3c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for (i = 0xb4c; i <= 0xb5c; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - /*DPK path B*/ - if (is2T) { - /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - /* LUTs => tx_agc*/ - /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ - /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ - /* PA gain = 01 => tx_agc 0b ~0d*/ - /* PA gain = 00 => tx_agc 0a ~00*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - /* PAGE_B for Path-A inner loopback DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - /*----send one shot signal----*/ - /* Path B*/ - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - /* PA gain = 11 => tx_agc = 1a*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); - - /* PAGE_B for Path-B DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for (i = 0xb60; i <= 0xb9c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for (i = 0xbac; i <= 0xbbc; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - - //reload RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (i = 0 ; i < DP_RF_REG_NUM ; i++) - ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off - - /*reload AFE default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); - #endif -} - -VOID -PHY_DigitalPredistortion_8192E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - #if DISABLE_BB_RF - return; - #endif - - return; - - if (pDM_Odm->RFCalibrateInfo.bDPdone) - return; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_2T2R(pHalData->VersionID)) - phy_DigitalPredistortion_92E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - phy_DigitalPredistortion_92E(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - // MAIN: WiFi - - if (ODM_GetMACReg(pDM_Odm, 0x64, 0xFFF) == 0x100) - return TRUE; - else - return FALSE; - -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if DISABLE_BB_RF - return TRUE; - #endif - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_2T2R(pHalData->VersionID)) - return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); - #else - return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); - #endif - } -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_92E 6 + +/*---------------------------Define Local Constant---------------------------*/ + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8192E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; + + /*new element A = element D x X*/ + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; + + /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ + switch (RFPath) { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #endif + + ODM_ResetIQKResult(pDM_Odm); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); + #else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); + #endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); + #endif + #endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8192E(pDM_Odm, FALSE); + #else + PHY_IQCalibrate_8192E(Adapter, FALSE); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); + #else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); + #endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); + #endif + #endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr92E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 30; /*+0dB*/ + u1Byte PwrTrackingLimit_CCK = 28; /*-2dB*/ + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8192EA\n")); + + if (TxRate != 0xFF) { /*20130429 Mimic Modify High Rate BBSwing Limit.*/ + /*2 CCK*/ + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || TxRate == MGN_11M) + PwrTrackingLimit_CCK = 28; /*-2dB*/ + //2 OFDM + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + + //2 HT + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ + PwrTrackingLimit_OFDM = 38; /*+4dB*/ + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + + else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) /*QPSK/BPSK*/ + PwrTrackingLimit_OFDM = 38; /*+4dB*/ + else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) /*16QAM*/ + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) /*64QAM*/ + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ + } + + if (Method == TXAGC) { + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*Remnant index equal to aboslute compensate value.*/ + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + #if (MP_DRIVER == 1) + if (pDM_Odm->mp_mode == TRUE) { + if (RFPath == ODM_RF_PATH_A) { + //CCK Path A + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr << 16) | (pwr << 8) | (pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + //OFDM Path A + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); + TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else if (RFPath == ODM_RF_PATH_B) { + //CCK Path B + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B]; + PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(B) Power = 0x%x\n", pwr)); + + //OFDM Path B + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); + TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); + } + } else + #endif + { + //PHY_SetTxPowerLevelByPath8192E(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function + //PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + if (RFPath == ODM_RF_PATH_A) { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + } else { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + } + } + + #endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + #endif + + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index <= 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE - 1; + else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) + Final_CCK_Swing_Index = 0; + + // Adjust BB swing by OFDM IQ matrix + if (RFPath == ODM_RF_PATH_A) { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + // Adjust BB swing by CCK filter coefficient + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + } else if (RFPath == ODM_RF_PATH_B) { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + } + } else if (Method == MIX_MODE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) { + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*CCK Follow Path-A and lower CCK index means higher power.*/ + + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index <= 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + + if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + /* Adjust BB swing by CCK filter coefficient*/ + + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + } else if (Final_CCK_Swing_Index <= 0) { /*Lowest CCK Index = 0*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); + + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); + } + + } + } + if (RFPath == ODM_RF_PATH_B) { + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index <= 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + } + } else + return; +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8192E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; + pConfig->RfPathCount = MAX_PATH_NUM_8192E; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; + pConfig->DoIQK = DoIQK_8192E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + /*8192E IQK V2.1 20150713*/ + /*1 Tx IQK*/ + //path-A IQK setting + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); + + + + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x511e0); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + /* PA/PAD controlled by 0x0*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); + return result; + + } + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); +/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regEB4, regEBC; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + /*1 Tx IQK*/ + //path-B IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); + + /*disable path-A PI, prevent path-A re-LOK*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + #if 0 + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); + #endif + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + /*enable path-A PI*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); + + return result; +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); + return result; + } + + u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly +) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; + #endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only +) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); + + if (bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +/* MP Already declare in odm.c*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if (rtw_is_drv_stopped(padapter)|| Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s /%d/%d\n", + ?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0 ; i < RegisterNum ; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +VOID +_PHY_ReloadMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + #if 0 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); + #else + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); + #endif +} + + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +) +{ + u4Byte pathOn; + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; + if (FALSE == is2T) { + pathOn = 0x0fc01616; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); + } else + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + + for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); + +} + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + //u4Byte i = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + /* + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + */ + + //ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); + //ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); + //ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); + + ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); +// ODM_SetBBReg(pDM_Odm, 0x550, 0x0000ffff, 0x0015); + + +} + +VOID +_PHY_PathAStandBy_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); +// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PathBStandBy_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode +) +{ + u4Byte mode; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 +) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ +/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ +/*#else*/ + BOOLEAN is2T = TRUE; +/*#endif*/ + + s4Byte tmp1 = 0, tmp2 = 0; + + //if(is2T) + bound = 8; + //else + // bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i] + result[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + SimularityBitMap = SimularityBitMap | (1 << i); + } else + SimularityBitMap = SimularityBitMap | (1 << i); + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); + + if (SimularityBitMap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + } else { + + if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ + for (i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ + for (i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + + } + + if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + } + + return FALSE; + } + + + +} + + + +VOID +phy_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u4Byte i; + u1Byte PathAOK = 0, PathBOK = 0; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + /*since 92C & 92D have the different define in IQK_BB_REG*/ + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + 0x92c, 0x930, + 0x938, rCCK0_AFESetting + + }; + + u4Byte retryCount = 2; + + #if MP_DRIVER + if (pDM_Odm->mp_mode == TRUE) + retryCount = 9; + #endif + + /*Note: IQ calibration must be performed after loading*/ + /*PHY_REG.txt,and radio_a,radio_b.txt*/ + + //u4Byte bbvalue; + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 2; + #endif + #endif + + + if (t == 0) { + /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ + /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ + + /*Save ADDA parameters, turn Path A ADDA on*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); + #else + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); + #endif + + /* + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch_92E(pAdapter, TRUE); + #else + _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); + #endif + } + */ + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); + + if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { /* external LNA / external PA = 1 /0 */ + /*PAPE force to high*/ + /*just for high power with external LNA, without external PA*/ + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); + } else if (pDM_Odm->ExtPA) { /* external PA = 1*/ + /*PAPE force to low*/ + /*just for high power with external PA, without external LNA*/ + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); + } + + // IQ calibration setting +/*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathBStandBy_92E(pAdapter); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathBStandBy_92E(pDM_Odm); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + } + +//path A TXIQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); + #else + PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); + #endif +// if(PathAOK == 0x03){ + if (PathAOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +//path A RXIQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); + #else + PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + + #endif + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy_92E(pAdapter); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathAStandBy_92E(pDM_Odm); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + // IQ calibration setting + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + +//path B Tx IQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8192E(pAdapter); + #else + PathBOK = phy_PathB_IQK_8192E(pDM_Odm); + #endif +// if(PathBOK == 0x03){ + if (PathBOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +//path B RX IQK + #if 1 + + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); + #else + PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + } + + if (0x00 == PathBOK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + /**/ + } + #endif + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { + + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + +/*Allen initial gain 0xc50*/ + /* Restore RX initial gain*/ + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + if ((tmpReg & 0x70) != 0) { + //1. Read original RF mode + //Path-A + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); + } + + //3. Read RF reg18 + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } else /*Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 + }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 + }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB + }; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB + }; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000 + }; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000 + }; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + + #if MP_DRIVER == 1 + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if (!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +//#if MP_DRIVER != 1 + if (pDM_Odm->mp_mode == FALSE) + return; +//#endif + + //settings adjust for normal chip + for (index = 0; index < PATH_NUM; index++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for (index = 0; index < APK_BB_REG_NUM; index++) { + for (path = 0; path < pathbound; path++) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for (index = 0; index < APK_BB_REG_NUM ; index++) { + if (index == 0) /*skip*/ + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + /*save MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + for (path = 0; path < pathbound; path++) { + + + if (path == ODM_RF_PATH_A) { + /*path A APK*/ + /*load APK setting*/ + /*path-A*/ + offset = rPdp_AntA; + for (index = 0; index < 11; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for (; index < 13; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else if (path == ODM_RF_PATH_B) { + /*path B APK*/ + /*load APK setting*/ + /*path-B*/ + offset = rPdp_AntB; + for (index = 0; index < 10; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + #else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + #endif + + offset = rConfig_AntA; + index = 11; + for (; index < 13; index++) { /*offset 0xb68, 0xb6c*/ + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); + #else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); + #endif + + //Path A AFE all on, path B AFE All off or vise versa + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if (path == 0) { + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } else { /*path B*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + else { /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta + 14) / 2); + if (delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ + continue; + + tmpReg = APK_RF_init_value[path][index]; + #if 1 + if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if (!(tmpReg & BIT15)) /*sign bit 0*/ + BB_offset = -BB_offset; + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if (BB_offset < 0) { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } else + tmpReg = tmpReg | BIT15; + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } + #endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); + #endif + + /* PA11+PAD01111, one shot*/ + i = 0; + do { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } while (tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + /*reload MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*reload BB default value*/ + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //reload RF path default value + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if (path == ODM_RF_PATH_B) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if (path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + u4Byte StartTime; + s4Byte ProgressingTime; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #else + prtl8192cd_priv priv = pDM_Odm->priv; + + #ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } + #endif + + if (priv->pshare->IQK_88E_done) + bReCovery = 1; + priv->pshare->IQK_88E_done = 1; + + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if MP_DRIVER == 1 + if (pDM_Odm->mp_mode == TRUE) { + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + } + #endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + #if DISABLE_BB_RF + return; + #endif + + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) + #else /*for ODM_WIN*/ + if (bReCovery && + (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ + #endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #endif + return; + } + StartTime = ODM_GetCurrentTime(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); +// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); + + #else + +// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); + phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); + #endif + + + if (i == 1) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); + #else + is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); + #endif + + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); + #else + is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); + #endif + + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); + + break; + } + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); + #else + is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); + #endif + + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + /* + for(i = 0; i < 4; i++) + RegTmp &= result[3][i*2]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + */ + final_candidate = 3; + + } + } + } + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + + if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #else + _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #endif + } + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + + #endif + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); + #else + Indexforchannel = 0; + #endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); + #endif + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); + +} + + +VOID +PHY_LCCalibrate_8192E( + PVOID pDM_VOID +) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + u4Byte StartTime; + s4Byte ProgressingTime; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + + + + + #if MP_DRIVER == 1 + if (pDM_Odm->mp_mode == TRUE) { + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + } + #endif + + + #if DISABLE_BB_RF + return; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + StartTime = ODM_GetCurrentTime(pDM_Odm); + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_2T2R(pHalData->VersionID)) + phy_LCCalibrate_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8192E(pAdapter, FALSE); + #else + phy_LCCalibrate_8192E(pDM_Odm, FALSE); + #endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); +} + +VOID +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + #if DISABLE_BB_RF + return; + #endif + + return; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if FOR_BRAZIL_PRETEST != 1 + if (pDM_Odm->RFCalibrateInfo.bAPKdone) + #endif + return; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) + phy_APCalibrate_8192E(pAdapter, delta, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8192E(pAdapter, delta, FALSE); + #else + phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); + #endif + } +} +VOID phy_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + // MAIN: WiFi + u4Byte reg = ODM_GetMACReg(pDM_Odm, 0x64, bMaskDWord); + reg &= 0xFFFFF000; + reg = (bMain) ? (reg | 0x00000100) : (reg | 0x00000004); + ODM_SetMACReg(pDM_Odm, 0x64, bMaskDWord, reg); + +} + +VOID PHY_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #endif + + #if DISABLE_BB_RF + return; + #endif + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); + #endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion_92E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T +) +{ + #if (RT_PLATFORM == PLATFORM_WINDOWS) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0 + }; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + + //save MAC default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); + #endif + + //save RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (index = 0; index < DP_RF_REG_NUM; index++) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #else + RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #endif + } + + //save AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //Path A/B AFE all on + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); + + //BB register setting + for (index = 0; index < DP_BB_REG_NUM; index++) { + if (index < 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); + else if (index == 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); + } + + //MAC register setting + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*PAGE-E IQC setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + //path_A DPK + //Path B to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + + // PA gain = 11 & PAD1 => tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for (i = rPdp_AntA; i <= 0xb3c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for (i = 0xb4c; i <= 0xb5c; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + /*DPK path B*/ + if (is2T) { + /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + /* LUTs => tx_agc*/ + /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ + /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ + /* PA gain = 01 => tx_agc 0b ~0d*/ + /* PA gain = 00 => tx_agc 0a ~00*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + /* PAGE_B for Path-A inner loopback DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + /*----send one shot signal----*/ + /* Path B*/ + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + /* PA gain = 11 => tx_agc = 1a*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); + + /* PAGE_B for Path-B DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for (i = 0xb60; i <= 0xb9c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for (i = 0xbac; i <= 0xbbc; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + + //reload RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (i = 0 ; i < DP_RF_REG_NUM ; i++) + ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off + + /*reload AFE default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); + #endif +} + +VOID +PHY_DigitalPredistortion_8192E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + #if DISABLE_BB_RF + return; + #endif + + return; + + if (pDM_Odm->RFCalibrateInfo.bDPdone) + return; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_2T2R(pHalData->VersionID)) + phy_DigitalPredistortion_92E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + phy_DigitalPredistortion_92E(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + // MAIN: WiFi + + if (ODM_GetMACReg(pDM_Odm, 0x64, 0xFFF) == 0x100) + return TRUE; + else + return FALSE; + +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if DISABLE_BB_RF + return TRUE; + #endif + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) + return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); + #else + return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); + #endif + } +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.h index c96bc6fd464..33f6bfb9655 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_ce.h @@ -1,146 +1,146 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8192E_H__ -#define __HAL_PHY_RF_8192E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -#define IQK_DELAY_TIME_92E 15 //ms -#else -#define IQK_DELAY_TIME_92E 10 -#endif - -#define index_mapping_NUM_92E 15 -#define AVG_THERMAL_NUM_92E 4 -#define RF_T_METER_92E 0x42 - -#include "../halphyrf_ce.h" - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -); - -VOID -GetDeltaSwingTable_8192E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -); - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -); - -VOID -ODM_TxPwrTrackSetPwr92E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -); - -//1 7. IQK - -void -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -); - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -); - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -_PHY_PathAStandBy( - IN PDM_ODM_T pDM_Odm -); -#endif - - - - -#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8192E_H__ +#define __HAL_PHY_RF_8192E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define IQK_DELAY_TIME_92E 15 //ms +#else +#define IQK_DELAY_TIME_92E 10 +#endif + +#define index_mapping_NUM_92E 15 +#define AVG_THERMAL_NUM_92E 4 +#define RF_T_METER_92E 0x42 + +#include "../halphyrf_ce.h" + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +); + +VOID +GetDeltaSwingTable_8192E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +); + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +); + +VOID +ODM_TxPwrTrackSetPwr92E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +); + +//1 7. IQK + +void +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +); + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +); + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +_PHY_PathAStandBy( + IN PDM_ODM_T pDM_Odm +); +#endif + + + + +#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.c b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.c index f3ba770ab65..cafc3054c1d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.c @@ -1,3671 +1,3671 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - -#if (RTL8192E_SUPPORT == 1) - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_92E 6 - -/*---------------------------Define Local Constant---------------------------*/ - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8192E( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y -) -{ - s4Byte ele_A = 0, ele_D, ele_C = 0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; - - /*new element A = element D x X*/ - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; - - /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ - switch (RFPath) { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - #endif - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8192E(pDM_Odm, FALSE); - #else - PHY_IQCalibrate_8192E(Adapter, FALSE); - #endif - -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr92E( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 30; //+0dB - u1Byte PwrTrackingLimit_CCK = 28; //-2dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8192EA\n")); - - if (TxRate != 0xFF) { //20130429 Mimic Modify High Rate BBSwing Limit. - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = 28; //-2dB - //2 OFDM - else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM = 36; //+3dB - else if (TxRate == MGN_54M) - PwrTrackingLimit_OFDM = 34; //+2dB - - //2 HT - else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit_OFDM = 38; //+4dB - else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit_OFDM = 36; //+3dB - else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit_OFDM = 34; //+2dB - - else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) //QPSK/BPSK - PwrTrackingLimit_OFDM = 38; //+4dB - else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) //16QAM - PwrTrackingLimit_OFDM = 36; //+3dB - else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) //64QAM - PwrTrackingLimit_OFDM = 34; //+2dB - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PwrTrackingLimit_CCK=%d PwrTrackingLimit_OFDM=%d\n", PwrTrackingLimit_CCK, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) { - - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - #if (MP_DRIVER != 1) - //PHY_SetTxPowerLevelByPath8192E(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function - //PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - if (RFPath == ODM_RF_PATH_A) { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - } else { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - } - #else - - if (RFPath == ODM_RF_PATH_A) { - //CCK Path A - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - //OFDM Path A - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); - TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } else if (RFPath == ODM_RF_PATH_B) { - //CCK Path B - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B]; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(B) Power = 0x%x\n", pwr)); - - //OFDM Path B - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); - TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); - } - #endif - - #endif - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - #endif - - } else if (Method == BBSWING) { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE - 1; - else if (pRFCalibrateInfo->BbSwingIdxCck < 0) - Final_CCK_Swing_Index = 0; - - // Adjust BB swing by OFDM IQ matrix - if (RFPath == ODM_RF_PATH_A) { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - // Adjust BB swing by CCK filter coefficient - if (!pRFCalibrateInfo->bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - } else if (RFPath == ODM_RF_PATH_B) { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - } - } else if (Method == MIX_MODE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) { - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //CCK Follow Path-A and lower CCK index means higher power. - - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { //BBSwing higher then Limit - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { //If TxAGC has changed, reset TxAGC again - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - - if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - // Adjust BB swing by CCK filter coefficient - - if (!pRFCalibrateInfo->bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - } else if (Final_CCK_Swing_Index < 0) { // Lowest CCK Index = 0 - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - if (!pRFCalibrateInfo->bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); - - if (!pRFCalibrateInfo->bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); - } - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { //If TxAGC has changed, reset TxAGC again - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); - } - - } - } - if (RFPath == ODM_RF_PATH_B) { - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { //BBSwing higher then Limit - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { //If TxAGC has changed, reset TxAGC again - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - //Set TxAGC Page C{}; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - } - } else - return; -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8192E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call GetDeltaSwingTable_8192E Power Tracking TxRate=0x%X\n", TxRate)); - - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; - pConfig->RfPathCount = MAX_PATH_NUM_8192E; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; - pConfig->DoIQK = DoIQK_8192E; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - /*8192E IQK V2.1 20150713*/ - /*1 Tx IQK*/ - //path-A IQK setting - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); - - - - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x511e0); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - /* PA/PAD controlled by 0x0*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); - return result; - - } - - u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ - - - // PA/PAD control by 0x56, and set = 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); -/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000) >> 16) != 0x132) && - (((regEAC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - u4Byte regEAC, regEB4, regEBC; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - /*1 Tx IQK*/ - //path-B IQK setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); - - /*disable path-A PI, prevent path-A re-LOK*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - - //modify TXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - #if 0 - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); - ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); - #endif - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); -// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - /*enable path-A PI*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); - - return result; -} - - - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_RxIQK_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB -) -{ - u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - // PA/PAD controlled by 0x0 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); - return result; - } - - u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ - - // PA/PAD all off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); - //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); - ODM_delay_ms(IQK_DELAY_TIME_92E); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); - - if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ - (((regEC4 & 0x03FF0000) >> 16) != 0x132) && - (((regECC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); - - return result; - - -} - - -VOID -_PHY_PathAFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly -) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - #if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; - #endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only -) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); - - if (bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -/* MP Already declare in odm.c*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0 ; i < RegisterNum ; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); -} - - -VOID -_PHY_SaveMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); -} - -VOID -_PHY_ReloadMACRegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - #if 0 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); - #else - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); - #endif -} - - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -) -{ - u4Byte pathOn; - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; - if (FALSE == is2T) { - pathOn = 0x0fc01616; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); - } else - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - - for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); - -} - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - //u4Byte i = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - /* - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - */ - - //ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); - //ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); - //ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); - - ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); -// ODM_SetBBReg(pDM_Odm, 0x550, 0x0000ffff, 0x0015); - - -} - -VOID -_PHY_PathAStandBy_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); -// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PathBStandBy_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode -) -{ - u4Byte mode; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 -) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ -/*#else*/ - BOOLEAN is2T = TRUE; -/*#endif*/ - - s4Byte tmp1 = 0, tmp2 = 0; - - if (is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i] + result[c1][i + 1] == 0) - final_candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - final_candidate[(i / 4)] = c1; - else - SimularityBitMap = SimularityBitMap | (1 << i); - } else - SimularityBitMap = SimularityBitMap | (1 << i); - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); - - if (SimularityBitMap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (final_candidate[i] != 0xFF) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[final_candidate[i]][j]; - bResult = FALSE; - } - } - return bResult; - } else { - - if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ - for (i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ - for (i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ - for (i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - - } - - if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ - for (i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - } - - return FALSE; - } - - - -} - - - -VOID -phy_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte t, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte i; - u1Byte PathAOK = 0, PathBOK = 0; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - /*since 92C & 92D have the different define in IQK_BB_REG*/ - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - 0x92c, 0x930, - 0x938, rCCK0_AFESetting - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; - #else - #if MP_DRIVER - const u4Byte retryCount = 9; - #else - const u4Byte retryCount = 2; - #endif - #endif - - /*Note: IQ calibration must be performed after loading*/ - /*PHY_REG.txt,and radio_a,radio_b.txt*/ - - //u4Byte bbvalue; - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 2; - #endif - #endif - - - if (t == 0) { - /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ - /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ - - /*Save ADDA parameters, turn Path A ADDA on*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); - #endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); - #else - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); - #endif - - /* - if(t==0) - { - pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pRFCalibrateInfo->bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch_92E(pAdapter, TRUE); - #else - _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); - #endif - } - */ - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - #endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); - - if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { /* external LNA / external PA = 1 /0 */ - /*PAPE force to high*/ - /*just for high power with external LNA, without external PA*/ - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); - } else if (pDM_Odm->ExtPA) { /* external PA = 1*/ - /*PAPE force to low*/ - /*just for high power with external PA, without external LNA*/ - ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); - ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); - } - - // IQ calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathBStandBy_92E(pAdapter); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathBStandBy_92E(pDM_Odm); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - } - -//path A TXIQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); - #else - PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); - #endif -// if(PathAOK == 0x03){ - if (PathAOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -//path A RXIQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); - #else - PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - - if(0x00 == PathAOK){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } - - #endif - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy_92E(pAdapter); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathAStandBy_92E(pDM_Odm); - - // Turn ADDA on - _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - // IQ calibration setting - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - -//path B Tx IQK - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8192E(pAdapter); - #else - PathBOK = phy_PathB_IQK_8192E(pDM_Odm); - #endif -// if(PathBOK == 0x03){ - if (PathBOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - break; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -//path B RX IQK - #if 1 - - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); - #else - PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); - #endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } - } - - if (0x00 == PathBOK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - /**/ - } - #endif - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { - - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); - #else - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); - #endif - - /*Allen initial gain 0xc50*/ - /* Restore RX initial gain*/ - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); - -} - - -VOID -phy_LCCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - u1Byte tmpReg; - u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - if ((tmpReg & 0x70) != 0) { - //1. Read original RF mode - //Path-A - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if (is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); - #endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); - } - - //3. Read RF reg18 - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); - #endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } else { /*Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 - }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 - }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB - }; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB - }; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000 - }; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000 - }; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - - #if MP_DRIVER == 1 - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if (!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. - #if MP_DRIVER != 1 - return; - #endif - //settings adjust for normal chip - for (index = 0; index < PATH_NUM; index ++) { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for (index = 0; index < APK_BB_REG_NUM; index ++) { - for (path = 0; path < pathbound; path++) { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for (index = 0; index < APK_BB_REG_NUM ; index++) { - if (index == 0) /*skip*/ - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - /*save MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - - /*save AFE default value*/ - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - for (path = 0; path < pathbound; path++) { - - - if (path == ODM_RF_PATH_A) { - /*path A APK*/ - /*load APK setting*/ - /*path-A*/ - offset = rPdp_AntA; - for (index = 0; index < 11; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for (; index < 13; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else if (path == ODM_RF_PATH_B) { - /*path B APK*/ - /*load APK setting*/ - /*path-B*/ - offset = rPdp_AntB; - for (index = 0; index < 10; index ++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - #else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - #endif - - offset = rConfig_AntA; - index = 11; - for (; index < 13; index ++) { /*offset 0xb68, 0xb6c*/ - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); - #else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); - #endif - - //Path A AFE all on, path B AFE All off or vise versa - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if (path == 0) { - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } else { /*path B*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - else { /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta + 14) / 2); - if (delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for (index = 0; index < APK_BB_REG_NUM; index++) { - if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ - continue; - - tmpReg = APK_RF_init_value[path][index]; - #if 1 - if (!pRFCalibrateInfo->bAPKThermalMeterIgnore) { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if (!(tmpReg & BIT15)) /*sign bit 0*/ - BB_offset = -BB_offset; - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if (BB_offset < 0) { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } else - tmpReg = tmpReg | BIT15; - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } - #endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); - #endif - - /* PA11+PAD01111, one shot*/ - i = 0; - do { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } while (tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - /*reload MAC default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*reload BB default value*/ - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) /*skip*/ - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //reload RF path default value - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if (path == ODM_RF_PATH_B) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if (path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pRFCalibrateInfo->bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #else - prtl8192cd_priv priv = pDM_Odm->priv; - - #ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } - #endif - - if (priv->pshare->IQK_88E_done) - bReCovery = 1; - priv->pshare->IQK_88E_done = 1; - - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if MP_DRIVER == 1 - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - #if DISABLE_BB_RF - return; - #endif - - if (pRFCalibrateInfo->bIQKInProgress) - return; - - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) - #else /*for ODM_WIN*/ - if (bReCovery && - (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ - #endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); - #endif - return; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[3][i] = 0x100; - else - result[3][i] = 0; - } - - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); -// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); - - #else - -// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); - phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); - #endif - - - if (i == 1) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); - #else - is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); - #endif - - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); - #else - is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); - #endif - - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); - - break; - } - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); - #else - is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); - #endif - - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - /* - for(i = 0; i < 4; i++) - RegTmp &= result[3][i*2]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - */ - final_candidate = 3; - - } - } - } - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; - pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; - pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value - pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value - } - - if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #else - _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #endif - } - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -//Allen -// if (IS_92C_SERIAL(pHalData->VersionID)) -// { -// if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) -// { - _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); -// } -// } - #endif - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); - #else - Indexforchannel = 0; - #endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); - #endif - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - -} - - -VOID -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - - - #if MP_DRIVER == 1 - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - - #if DISABLE_BB_RF - return; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if (bSingleTone || bCarrierSuppression) - return; - - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pRFCalibrateInfo->bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_2T2R(pHalData->VersionID)) - phy_LCCalibrate_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8192E(pAdapter, FALSE); - #else - phy_LCCalibrate_8192E(pDM_Odm, FALSE); - #endif - } - - pRFCalibrateInfo->bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - #if DISABLE_BB_RF - return; - #endif - - return; - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if FOR_BRAZIL_PRETEST != 1 - if (pRFCalibrateInfo->bAPKdone) - #endif - return; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - phy_APCalibrate_8192E(pAdapter, delta, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8192E(pAdapter, delta, FALSE); - #else - phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); - #endif - } -} -VOID phy_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - // MAIN: WiFi - u4Byte reg = PHY_QueryMacReg(pAdapter, 0x64, bMaskDWord); - reg &= 0xFFFFF000; - reg = (bMain) ? (reg | 0x00000100) : (reg | 0x00000004); - PHY_SetMacReg(pAdapter, 0x64, bMaskDWord, reg); - -} - -VOID PHY_SetRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #endif - - #if DISABLE_BB_RF - return; - #endif - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); - #endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion_92E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T -) -{ - #if (RT_PLATFORM == PLATFORM_WINDOWS) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE - }; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0 - }; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A - }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4 - }; /*path A on path B off / path A off path B on*/ - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - - //save MAC default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); - #else - _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); - #endif - - //save RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (index = 0; index < DP_RF_REG_NUM; index++) - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #else - RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); - #endif - } - - //save AFE default value - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #else - _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - #endif - - //Path A/B AFE all on - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); - - //BB register setting - for (index = 0; index < DP_BB_REG_NUM; index++) { - if (index < 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); - else if (index == 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); - } - - //MAC register setting - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - /*PAGE-E IQC setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - //path_A DPK - //Path B to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - - // PA gain = 11 & PAD1 => tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); - pRFCalibrateInfo->bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if (pRFCalibrateInfo->bDPPathAOK) { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for (i = rPdp_AntA; i <= 0xb3c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for (i = 0xb4c; i <= 0xb5c; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - /*DPK path B*/ - if (is2T) { - /*Path A to standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - /* LUTs => tx_agc*/ - /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ - /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ - /* PA gain = 01 => tx_agc 0b ~0d*/ - /* PA gain = 00 => tx_agc 0a ~00*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*do inner loopback DPK 3 times*/ - for (i = 0; i < 3; i++) { - /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); - - /* PAGE_B for Path-A inner loopback DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - /*----send one shot signal----*/ - /* Path B*/ - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - /* PA gain = 11 => tx_agc = 1a*/ - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); - - /* PAGE_B for Path-B DPK setting*/ - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while (RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pRFCalibrateInfo->bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if (pRFCalibrateInfo->bDPPathBOK) { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for (i = 0xb60; i <= 0xb9c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for (i = 0xbac; i <= 0xbbc; i += 4) - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for (index = 0; index < DP_BB_REG_NUM; index++) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - - //reload RF default value - for (path = 0; path < DP_PATH_NUM; path++) { - for (i = 0 ; i < DP_RF_REG_NUM ; i++) - ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off - - /*reload AFE default value*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); - #else - _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - /*reload MAC default value*/ - _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); - #endif - - pRFCalibrateInfo->bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); - #endif -} - -VOID -PHY_DigitalPredistortion_8192E( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - #if DISABLE_BB_RF - return; - #endif - - return; - - if (pRFCalibrateInfo->bDPdone) - return; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_92C_SERIAL(pHalData->VersionID)) - phy_DigitalPredistortion_92E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - phy_DigitalPredistortion_92E(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -) -{ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - // MAIN: WiFi - - if (ODM_GetMACReg(pDM_Odm, 0x64, 0xFFF) == 0x100) - return TRUE; - else - return FALSE; - -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if DISABLE_BB_RF - return TRUE; - #endif - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_2T2R(pHalData->VersionID)) - return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); - else - #endif - { - // For 88C 1T1R - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); - #else - return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); - #endif - } -} -#endif - -#else /* #if (RTL8192E_SUPPORT == 1)*/ - -VOID -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ){} -VOID -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID - ){} - -VOID -ODM_TxPwrTrackSetPwr92E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ){} - -#endif /* #if (RTL8192E_SUPPORT == 1)*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +#if (RTL8192E_SUPPORT == 1) + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_92E 6 + +/*---------------------------Define Local Constant---------------------------*/ + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8192E( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; + + /*new element A = element D x X*/ + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; + + /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ + switch (RFPath) { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + #endif + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8192E(pDM_Odm, FALSE); + #else + PHY_IQCalibrate_8192E(Adapter, FALSE); + #endif + +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr92E( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 30; //+0dB + u1Byte PwrTrackingLimit_CCK = 28; //-2dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8192EA\n")); + + if (TxRate != 0xFF) { //20130429 Mimic Modify High Rate BBSwing Limit. + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = 28; //-2dB + //2 OFDM + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; //+3dB + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; //+2dB + + //2 HT + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM = 38; //+4dB + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM = 36; //+3dB + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM = 34; //+2dB + + else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) //QPSK/BPSK + PwrTrackingLimit_OFDM = 38; //+4dB + else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) //16QAM + PwrTrackingLimit_OFDM = 36; //+3dB + else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) //64QAM + PwrTrackingLimit_OFDM = 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PwrTrackingLimit_CCK=%d PwrTrackingLimit_OFDM=%d\n", PwrTrackingLimit_CCK, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) { + + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr92E CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + #if (MP_DRIVER != 1) + //PHY_SetTxPowerLevelByPath8192E(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function + //PHY_SetTxPowerLevel8192E(pDM_Odm->Adapter, *pDM_Odm->pChannel); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + if (RFPath == ODM_RF_PATH_A) { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + } else { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + } + #else + + if (RFPath == ODM_RF_PATH_A) { + //CCK Path A + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr << 16) | (pwr << 8) | (pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + //OFDM Path A + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); + TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else if (RFPath == ODM_RF_PATH_B) { + //CCK Path B + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B]; + PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: CCK Tx-rf(B) Power = 0x%x\n", pwr)); + + //OFDM Path B + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); + TxAGC = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr92E: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); + } + #endif + + #endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + #endif + + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE - 1; + else if (pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + // Adjust BB swing by OFDM IQ matrix + if (RFPath == ODM_RF_PATH_A) { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + // Adjust BB swing by CCK filter coefficient + if (!pRFCalibrateInfo->bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + } else if (RFPath == ODM_RF_PATH_B) { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + } + } else if (Method == MIX_MODE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) { + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //CCK Follow Path-A and lower CCK index means higher power. + + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { //BBSwing higher then Limit + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { //If TxAGC has changed, reset TxAGC again + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + + if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + // Adjust BB swing by CCK filter coefficient + + if (!pRFCalibrateInfo->bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + } else if (Final_CCK_Swing_Index < 0) { // Lowest CCK Index = 0 + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + if (!pRFCalibrateInfo->bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]); + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + + if (!pRFCalibrateInfo->bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]); + } + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { //If TxAGC has changed, reset TxAGC again + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); + } + + } + } + if (RFPath == ODM_RF_PATH_B) { + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { //BBSwing higher then Limit + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8192E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8192E(pDM_Odm, 0, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8192E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { //If TxAGC has changed, reset TxAGC again + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + } + } else + return; +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8192E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call GetDeltaSwingTable_8192E Power Tracking TxRate=0x%X\n", TxRate)); + + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; + pConfig->RfPathCount = MAX_PATH_NUM_8192E; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr92E; + pConfig->DoIQK = DoIQK_8192E; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8192E; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8192E; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + /*8192E IQK V2.1 20150713*/ + /*1 Tx IQK*/ + //path-A IQK setting + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x68160000); + + + + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA TX IQK is not success\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //PA off, deafault:0xf117b + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x511e0); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + /* PA/PAD controlled by 0x0*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathA get TXIMR is not success\n")); + return result; + + } + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /*PA off : default:0xf7ffa*/ + + + // PA/PAD control by 0x56, and set = 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510e0); +/*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );*/ + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK is not success!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regEB4, regEBC; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + /*1 Tx IQK*/ + //path-B IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); + + /*disable path-A PI, prevent path-A re-LOK*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + + //modify TXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0x07f77); //PA off, default: 0x7f7f + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + #if 0 + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B 0xdf = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask))); + ODM_SetBBReg(pDM_Odm, 0xe28, 0xffffff00, 0x808000); + #endif + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140303); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); +// ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + /*enable path-A PI*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TX IQK is not success\n")); + + return result; +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); /*PA off, default: 0xf117b*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x511e0); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8216031f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x6816031f); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + // PA/PAD controlled by 0x0 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pathB get TXIMR is not success\n")); + return result; + } + + u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Do RXIQK!\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); /* PA off, default:0xf7ffa*/ + + // PA/PAD all off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x510e0); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask, 0x51000 ); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x821608ff); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x281608ff); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160cff); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160cff); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_92E)); + //PlatformStallExecution(IQK_DELAY_TIME_92E*1000); + ODM_delay_ms(IQK_DELAY_TIME_92E); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK is not success!!\n")); + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly +) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_92E only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + #if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; + #endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only +) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); + + if (bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +/* MP Already declare in odm.c*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0 ; i < RegisterNum ; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +VOID +_PHY_ReloadMACRegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + #if 0 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); + #else + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); + #endif +} + + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +) +{ + u4Byte pathOn; + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; + if (FALSE == is2T) { + pathOn = 0x0fc01616; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); + } else + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + + for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); + +} + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + //u4Byte i = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + /* + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + */ + + //ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); + //ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); + //ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); + + ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); +// ODM_SetBBReg(pDM_Odm, 0x550, 0x0000ffff, 0x0015); + + +} + +VOID +_PHY_PathAStandBy_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); +// ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PathBStandBy_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode +) +{ + u4Byte mode; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 +) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ +/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ +/*#else*/ + BOOLEAN is2T = TRUE; +/*#endif*/ + + s4Byte tmp1 = 0, tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i] + result[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + SimularityBitMap = SimularityBitMap | (1 << i); + } else + SimularityBitMap = SimularityBitMap | (1 << i); + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); + + if (SimularityBitMap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + } else { + + if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ + for (i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ + for (i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + + } + + if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + } + + return FALSE; + } + + + +} + + + +VOID +phy_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte i; + u1Byte PathAOK = 0, PathBOK = 0; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + /*since 92C & 92D have the different define in IQK_BB_REG*/ + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + 0x92c, 0x930, + 0x938, rCCK0_AFESetting + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; + #else + #if MP_DRIVER + const u4Byte retryCount = 9; + #else + const u4Byte retryCount = 2; + #endif + #endif + + /*Note: IQ calibration must be performed after loading*/ + /*PHY_REG.txt,and radio_a,radio_b.txt*/ + + //u4Byte bbvalue; + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 2; + #endif + #endif + + + if (t == 0) { + /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ + /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ + + /*Save ADDA parameters, turn Path A ADDA on*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); + #endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, TRUE, is2T); + #else + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, TRUE, is2T); + #endif + + /* + if(t==0) + { + pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pRFCalibrateInfo->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch_92E(pAdapter, TRUE); + #else + _PHY_PIModeSwitch_92E(pDM_Odm, TRUE); + #endif + } + */ + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + #endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x55204200); + + if ((pDM_Odm->ExtLNA) && !(pDM_Odm->ExtPA)) { /* external LNA / external PA = 1 /0 */ + /*PAPE force to high*/ + /*just for high power with external LNA, without external PA*/ + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00410041); + } else if (pDM_Odm->ExtPA) { /* external PA = 1*/ + /*PAPE force to low*/ + /*just for high power with external PA, without external LNA*/ + ODM_SetBBReg(pDM_Odm, 0x930, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x930, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0xf, 0x7); + ODM_SetBBReg(pDM_Odm, 0x938, 0x0f000000, 0x7); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x00000000); + } + + // IQ calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathBStandBy_92E(pAdapter); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathBStandBy_92E(pDM_Odm); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + } + +//path A TXIQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8192E(pAdapter, is2T); + #else + PathAOK = phy_PathA_IQK_8192E(pDM_Odm, is2T); + #endif +// if(PathAOK == 0x03){ + if (PathAOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Fail!!\n")); + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +//path A RXIQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK_92E(pAdapter, is2T); + #else + PathAOK = phy_PathA_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } + + #endif + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy_92E(pAdapter); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathAStandBy_92E(pDM_Odm); + + // Turn ADDA on + _PHY_PathADDAOn_92E(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + // IQ calibration setting + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + +//path B Tx IQK + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8192E(pAdapter); + #else + PathBOK = phy_PathB_IQK_8192E(pDM_Odm); + #endif +// if(PathBOK == 0x03){ + if (PathBOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +//path B RX IQK + #if 1 + + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK_92E(pAdapter, is2T); + #else + PathBOK = phy_PathB_RxIQK_92E(pDM_Odm, is2T); + #endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + } + + if (0x00 == PathBOK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + /**/ + } + #endif + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { + + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_92E(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); + #else + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_92E(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_92E(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); + #endif + + /*Allen initial gain 0xc50*/ + /* Restore RX initial gain*/ + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8192E() <==\n")); + +} + + +VOID +phy_LCCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + if ((tmpReg & 0x70) != 0) { + //1. Read original RF mode + //Path-A + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if (is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); + #endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode & 0x8FFFF) | 0x10000); + } + + //3. Read RF reg18 + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); + #endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if ((tmpReg & 0x70) != 0) { /*Deal with contisuous TX case*/ + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } else { /*Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 + }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 + }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /*path settings equal to path b settings*/ + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /*path settings equal to path b settings*/ + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB + }; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB + }; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000 + }; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000 + }; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + + #if MP_DRIVER == 1 + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if (!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. + #if MP_DRIVER != 1 + return; + #endif + //settings adjust for normal chip + for (index = 0; index < PATH_NUM; index ++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for (index = 0; index < APK_BB_REG_NUM; index ++) { + for (path = 0; path < pathbound; path++) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for (index = 0; index < APK_BB_REG_NUM ; index++) { + if (index == 0) /*skip*/ + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + /*save MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + + /*save AFE default value*/ + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + for (path = 0; path < pathbound; path++) { + + + if (path == ODM_RF_PATH_A) { + /*path A APK*/ + /*load APK setting*/ + /*path-A*/ + offset = rPdp_AntA; + for (index = 0; index < 11; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for (; index < 13; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else if (path == ODM_RF_PATH_B) { + /*path B APK*/ + /*load APK setting*/ + /*path-B*/ + offset = rPdp_AntB; + for (index = 0; index < 10; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + #else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + #endif + + offset = rConfig_AntA; + index = 11; + for (; index < 13; index ++) { /*offset 0xb68, 0xb6c*/ + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); + #else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); + #endif + + //Path A AFE all on, path B AFE All off or vise versa + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if (path == 0) { + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } else { /*path B*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + if (path == ODM_RF_PATH_A) /*Path B to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + else { /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta + 14) / 2); + if (delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index != 1) /*only DO PA11+PAD01001, AP RF setting*/ + continue; + + tmpReg = APK_RF_init_value[path][index]; + #if 1 + if (!pRFCalibrateInfo->bAPKThermalMeterIgnore) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if (!(tmpReg & BIT15)) /*sign bit 0*/ + BB_offset = -BB_offset; + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if (BB_offset < 0) { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } else + tmpReg = tmpReg | BIT15; + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } + #endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); + #endif + + /* PA11+PAD01111, one shot*/ + i = 0; + do { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } while (tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + /*reload MAC default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*reload BB default value*/ + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) /*skip*/ + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //reload RF path default value + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if (path == ODM_RF_PATH_B) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if (path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pRFCalibrateInfo->bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #else + prtl8192cd_priv priv = pDM_Odm->priv; + + #ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } + #endif + + if (priv->pshare->IQK_88E_done) + bReCovery = 1; + priv->pshare->IQK_88E_done = 1; + + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if MP_DRIVER == 1 + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + #if DISABLE_BB_RF + return; + #endif + + if (pRFCalibrateInfo->bIQKInProgress) + return; + + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) + #else /*for ODM_WIN*/ + if (bReCovery && + (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ + #endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_92E: Return due to bReCovery!\n")); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); + #endif + return; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_IQCalibrate_8192E(pAdapter, result, i, TRUE); +// phy_IQCalibrate_8192E(pAdapter, result, i, FALSE); + + #else + +// phy_IQCalibrate_8192E(pDM_Odm, result, i, FALSE); + phy_IQCalibrate_8192E(pDM_Odm, result, i, TRUE); + #endif + + + if (i == 1) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 1); + #else + is12simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 1); + #endif + + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8192E(pAdapter, result, 0, 2); + #else + is13simular = phy_SimularityCompare_8192E(pDM_Odm, result, 0, 2); + #endif + + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); + + break; + } + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8192E(pAdapter, result, 1, 2); + #else + is23simular = phy_SimularityCompare_8192E(pDM_Odm, result, 1, 2); + #endif + + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + /* + for(i = 0; i < 4; i++) + RegTmp &= result[3][i*2]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + */ + final_candidate = 3; + + } + } + } + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; + pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; + pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value + pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value + } + + if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix_92E(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #else + _PHY_PathAFillIQKMatrix_92E(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #endif + } + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +//Allen +// if (IS_92C_SERIAL(pHalData->VersionID)) +// { +// if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) +// { + _PHY_PathBFillIQKMatrix_92E(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); +// } +// } + #endif + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); + #else + Indexforchannel = 0; + #endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters_92E(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); + #endif + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + +} + + +VOID +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + + + #if MP_DRIVER == 1 + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + + #if DISABLE_BB_RF + return; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pRFCalibrateInfo->bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_2T2R(pHalData->VersionID)) + phy_LCCalibrate_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8192E(pAdapter, FALSE); + #else + phy_LCCalibrate_8192E(pDM_Odm, FALSE); + #endif + } + + pRFCalibrateInfo->bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + #if DISABLE_BB_RF + return; + #endif + + return; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if FOR_BRAZIL_PRETEST != 1 + if (pRFCalibrateInfo->bAPKdone) + #endif + return; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_APCalibrate_8192E(pAdapter, delta, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8192E(pAdapter, delta, FALSE); + #else + phy_APCalibrate_8192E(pDM_Odm, delta, FALSE); + #endif + } +} +VOID phy_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + // MAIN: WiFi + u4Byte reg = PHY_QueryMacReg(pAdapter, 0x64, bMaskDWord); + reg &= 0xFFFFF000; + reg = (bMain) ? (reg | 0x00000100) : (reg | 0x00000004); + PHY_SetMacReg(pAdapter, 0x64, bMaskDWord, reg); + +} + +VOID PHY_SetRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #endif + + #if DISABLE_BB_RF + return; + #endif + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_SetRFPathSwitch_8192E(pAdapter, bMain, TRUE); + #endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion_92E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T +) +{ + #if (RT_PLATFORM == PLATFORM_WINDOWS) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0 + }; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; /*path A on path B off / path A off path B on*/ + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_92E()\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_92E for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + + //save MAC default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_92E(pAdapter, BB_REG, MAC_backup); + #else + _PHY_SaveMACRegisters_92E(pDM_Odm, BB_REG, MAC_backup); + #endif + + //save RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (index = 0; index < DP_RF_REG_NUM; index++) + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #else + RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); + #endif + } + + //save AFE default value + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #else + _PHY_SaveADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + #endif + + //Path A/B AFE all on + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); + + //BB register setting + for (index = 0; index < DP_BB_REG_NUM; index++) { + if (index < 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); + else if (index == 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); + } + + //MAC register setting + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_MACSettingCalibration_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + /*PAGE-E IQC setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + //path_A DPK + //Path B to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + + // PA gain = 11 & PAD1 => tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Success\n")); + pRFCalibrateInfo->bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if (pRFCalibrateInfo->bDPPathAOK) { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for (i = rPdp_AntA; i <= 0xb3c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for (i = 0xb4c; i <= 0xb5c; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + /*DPK path B*/ + if (is2T) { + /*Path A to standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + /* LUTs => tx_agc*/ + /* PA gain = 11 & PAD1, => tx_agc 1f ~11*/ + /* PA gain = 11 & PAD2, => tx_agc 10 ~0e*/ + /* PA gain = 01 => tx_agc 0b ~0d*/ + /* PA gain = 00 => tx_agc 0a ~00*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*do inner loopback DPK 3 times*/ + for (i = 0; i < 3; i++) { + /*PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + /* PAGE_B for Path-A inner loopback DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + /*----send one shot signal----*/ + /* Path B*/ + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + /* PA gain = 11 => tx_agc = 1a*/ + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); + + /* PAGE_B for Path-B DPK setting*/ + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pRFCalibrateInfo->bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if (pRFCalibrateInfo->bDPPathBOK) { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for (i = 0xb60; i <= 0xb9c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for (i = 0xbac; i <= 0xbbc; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + + //reload RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (i = 0 ; i < DP_RF_REG_NUM ; i++) + ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off + + /*reload AFE default value*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_92E(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pAdapter, MAC_REG, MAC_backup); + #else + _PHY_ReloadADDARegisters_92E(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + /*reload MAC default value*/ + _PHY_ReloadMACRegisters_92E(pDM_Odm, MAC_REG, MAC_backup); + #endif + + pRFCalibrateInfo->bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_92E()\n")); + #endif +} + +VOID +PHY_DigitalPredistortion_8192E( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + #if DISABLE_BB_RF + return; + #endif + + return; + + if (pRFCalibrateInfo->bDPdone) + return; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_DigitalPredistortion_92E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + phy_DigitalPredistortion_92E(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + // MAIN: WiFi + + if (ODM_GetMACReg(pDM_Odm, 0x64, 0xFFF) == 0x100) + return TRUE; + else + return FALSE; + +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if DISABLE_BB_RF + return TRUE; + #endif + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) + return phy_QueryRFPathSwitch_8192E(pAdapter, TRUE); + else + #endif + { + // For 88C 1T1R + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8192E(pAdapter, FALSE); + #else + return phy_QueryRFPathSwitch_8192E(pDM_Odm, FALSE); + #endif + } +} +#endif + +#else /* #if (RTL8192E_SUPPORT == 1)*/ + +VOID +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ){} +VOID +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID + ){} + +VOID +ODM_TxPwrTrackSetPwr92E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ){} + +#endif /* #if (RTL8192E_SUPPORT == 1)*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.h b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.h index 82233866ce3..7b6b902e341 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/halphyrf_8192e_win.h @@ -1,146 +1,146 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8192E_H__ -#define __HAL_PHY_RF_8192E_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -#define IQK_DELAY_TIME_92E 15 //ms -#else -#define IQK_DELAY_TIME_92E 10 -#endif - -#define index_mapping_NUM_92E 15 -#define AVG_THERMAL_NUM_92E 4 -#define RF_T_METER_92E 0x42 - -#include "halphyrf_win.h" - -void ConfigureTxpowerTrack_8192E( - PTXPWRTRACK_CFG pConfig -); - -VOID -GetDeltaSwingTable_8192E( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -); - -void DoIQK_8192E( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -); - -VOID -ODM_TxPwrTrackSetPwr92E( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -); - -//1 7. IQK - -void -PHY_IQCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8192E( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8192E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -); - -VOID -_PHY_PathADDAOn_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T -); - -VOID -_PHY_MACSettingCalibration_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -_PHY_PathAStandBy( - IN PDM_ODM_T pDM_Odm -); -#endif - - - - -#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8192E_H__ +#define __HAL_PHY_RF_8192E_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define IQK_DELAY_TIME_92E 15 //ms +#else +#define IQK_DELAY_TIME_92E 10 +#endif + +#define index_mapping_NUM_92E 15 +#define AVG_THERMAL_NUM_92E 4 +#define RF_T_METER_92E 0x42 + +#include "halphyrf_win.h" + +void ConfigureTxpowerTrack_8192E( + PTXPWRTRACK_CFG pConfig +); + +VOID +GetDeltaSwingTable_8192E( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +); + +void DoIQK_8192E( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +); + +VOID +ODM_TxPwrTrackSetPwr92E( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +); + +//1 7. IQK + +void +PHY_IQCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192E( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +); + +VOID +_PHY_PathADDAOn_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +); + +VOID +_PHY_MACSettingCalibration_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +_PHY_PathAStandBy( + IN PDM_ODM_T pDM_Odm +); +#endif + + + + +#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.c b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.c index a76a75f5124..e0c3a43bce2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.c @@ -1,233 +1,233 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8192E_SUPPORT == 1) - -void -odm_ConfigRFReg_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if(Addr == 0xfe || Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else - { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - - //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130. - if(Addr == 0xb6) - { - u4Byte getvalue=0; - u1Byte count =0; - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - - ODM_delay_us(1); - - while((getvalue>>8)!=(Data>>8)) - { - count++; - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - ODM_delay_us(1); - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); - if(count>5) - break; - } - } - - if(Addr == 0xb2) - { - u4Byte getvalue=0; - u1Byte count =0; - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - - ODM_delay_us(1); - - while(getvalue!=Data) - { - count++; - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - ODM_delay_us(1); - //Do LCK againg - ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07); - ODM_delay_us(1); - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); - if(count>5) - break; - } - } - } -} - - -void -odm_ConfigRF_RadioA_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else - { -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - } - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8192E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8192E_SUPPORT == 1) + +void +odm_ConfigRFReg_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + + //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130. + if(Addr == 0xb6) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while((getvalue>>8)!=(Data>>8)) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + + if(Addr == 0xb2) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while(getvalue!=Data) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + //Do LCK againg + ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + } +} + + +void +odm_ConfigRF_RadioA_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + } + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8192E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.h b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.h index 4ac7829d6ea..154eb584855 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_regconfig8192e.h @@ -1,98 +1,98 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8192E -#define __INC_ODM_REGCONFIG_H_8192E - -#if (RTL8192E_SUPPORT == 1) - -void -odm_ConfigRFReg_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8192E( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8192E( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - - -#endif -#endif // end of SUPPORT - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8192E +#define __INC_ODM_REGCONFIG_H_8192E + +#if (RTL8192E_SUPPORT == 1) + +void +odm_ConfigRFReg_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8192E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8192E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + + +#endif +#endif // end of SUPPORT + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.c b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.c index 6bddccbe34f..f7a0c48ef37 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.c +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.c @@ -1,455 +1,455 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8192E_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - - -VOID -odm_Write_Dynamic_CCA( - IN PDM_ODM_T pDM_Odm, - IN u1Byte CurrentMFstate - ) -{ - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - if (PrimaryCCA->MF_state != CurrentMFstate){ - - ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate); - } - - PrimaryCCA->MF_state = CurrentMFstate; - -} - -VOID -odm_PrimaryCCA_Check_Init( - IN PDM_ODM_T pDM_Odm) -{ -#if((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) - PADAPTER pAdapter = pDM_Odm->Adapter; - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->Monitor_flag = 0; - PrimaryCCA->PriCCA_flag = 0; - PrimaryCCA->CH_offset = 0; - PrimaryCCA->MF_state = 0; -#endif -} - -VOID -odm_DynamicPrimaryCCA_Check( - IN PDM_ODM_T pDM_Odm - ) -{ - if(pDM_Odm->SupportICType != ODM_RTL8192E) - return; - - if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)) - return; - - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - odm_DynamicPrimaryCCAMP(pDM_Odm); -#endif - break; - - case ODM_CE: -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - -#endif - break; - - case ODM_AP: -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_DynamicPrimaryCCAAP(pDM_Odm); -#endif - break; - } - -} - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_DynamicPrimaryCCAMP( - IN PDM_ODM_T pDM_Odm - ) -{ - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); -#else - PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); -#endif - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - BOOLEAN Is40MHz = FALSE; - u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt; - u1Byte SecCHOffset; - u1Byte CurMFstate; - static u1Byte CountDown = Monitor_TIME; - - OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA; - OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail; - BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC; - BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM CCA=%d\n", OFDM_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM FA=%d\n", OFDM_FA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_USC=%d\n", BW_USC_Cnt)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_LSC=%d\n", BW_LSC_Cnt)); - Is40MHz = *(pDM_Odm->pBandWidth); - SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above - //DbgPrint("92E: SecCHOffset = %d\n", SecCHOffset); - if(IsAPModeExist(pAdapter)){ - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - return; - } - - if(!pDM_Odm->bLinked){ - return; - } - else{ - - if(Is40MHz){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Cont Down= %d\n", CountDown)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_Type=%d\n", PrimaryCCA->intf_type)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_flag=%d\n", PrimaryCCA->intf_flag )); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag)); - //DbgPrint("92E RTS_EN=%d\n", pHalData->RTSEN); - - if(PrimaryCCA->PriCCA_flag == 0){ - - if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition - - if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) - && (OFDM_FA>(OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 1; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - } - else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) - && (OFDM_FA < (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 2; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - PrimaryCCA->DupRTS_flag = 1; - pHalData->RTSEN = 1; - } - else{ - - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - } - - } - else if (SecCHOffset == 1){ - - if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias)) - && (OFDM_FA > (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 1; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - } - else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias)) - && (OFDM_FA < (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 2; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - PrimaryCCA->DupRTS_flag = 1; - pHalData->RTSEN = 1; - } - else{ - - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - } - - } - - } - else{ // PrimaryCCA->PriCCA_flag==1 - - CountDown--; - if(CountDown == 0){ - CountDown = Monitor_TIME; - PrimaryCCA->PriCCA_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - } - - } - - } - else{ - - return; - } - } - -} - -#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) - -VOID -odm_DynamicPrimaryCCAAP( - IN PDM_ODM_T pDM_Odm - ) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - prtl8192cd_priv priv = pDM_Odm->priv; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); -#else - PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); -#endif - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte i; - static u4Byte Count_Down = Monitor_TIME; - BOOLEAN STA_BW = FALSE, STA_BW_pre = FALSE, STA_BW_TMP = FALSE; - BOOLEAN bConnected = FALSE; - BOOLEAN Is40MHz = FALSE; - u1Byte SecCHOffset; - u1Byte CurMFstate; - PSTA_INFO_T pstat; - - Is40MHz = *(pDM_Odm->pBandWidth); - SecCHOffset = *(pDM_Odm->pSecChOffset); // AP: 1: sec is below, 2: sec is above - - - for(i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pstat)){ - - STA_BW_TMP = pstat->tx_bw; - if(STA_BW_TMP > STA_BW){ - STA_BW = STA_BW_TMP; - } - bConnected = TRUE; - } - } - - if(Is40MHz){ - - if(PrimaryCCA->PriCCA_flag == 0){ - - if(bConnected){ - - if(STA_BW == 0){ //2 STA BW=20M - - PrimaryCCA->PriCCA_flag = 1; - if(SecCHOffset==1){ - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - } - else if(SecCHOffset==2){ - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - } - } - else{ //2 STA BW=40M - if(PrimaryCCA->intf_flag == 0){ - - odm_Intf_Detection(pDM_Odm); - } - else{ // intf_flag = 1 - - if(PrimaryCCA->intf_type == 1){ - - if(PrimaryCCA->CH_offset == 1){ - - CurMFstate = MF_USC; - if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - } - } - else if(PrimaryCCA->CH_offset == 2){ - - CurMFstate = MF_LSC; - if(SecCHOffset == 2){ - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - } - } - } - else if(PrimaryCCA->intf_type==2){ - - if(PrimaryCCA->CH_offset==1){ - - //ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_USC); - pHalData->RTSEN = 1; - } - else if(PrimaryCCA->CH_offset==2){ - - //ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_LSC); - pHalData->RTSEN = 1; - } - - } - } - } - - } - else{ // disconnected interference detection - - odm_Intf_Detection(pDM_Odm); - }// end of disconnected - - - } - else{ // PrimaryCCA->PriCCA_flag == 1 - - if(STA_BW==0){ - - STA_BW_pre = STA_BW; - return; - } - - Count_Down--; - if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){ - - Count_Down = Monitor_TIME; - PrimaryCCA->PriCCA_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default - pHalData->RTSEN = 0; - - } - - } - - STA_BW_pre = STA_BW; - - } - else{ - //2 Reset - odm_PrimaryCCA_Check_Init(pDM_Odm); - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); - Count_Down = Monitor_TIME; - } - -} - - -VOID -odm_Intf_Detection( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); -#else - PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); -#endif - - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH) - &&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){ - - PrimaryCCA->intf_flag = 1; - PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC - if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){ - PrimaryCCA->intf_type = 1; - } - else{ - PrimaryCCA->intf_type = 2; - } - } - else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH) - &&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){ - - PrimaryCCA->intf_flag = 1; - PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC - if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){ - PrimaryCCA->intf_type = 1; - } - else{ - PrimaryCCA->intf_type = 2; - } - } - else{ - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->CH_offset = 0; - } - -} - -#endif - - - -#endif -#endif // RTL8192E_SUPPORT == 1 - - - - - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8192E_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + +VOID +odm_Write_Dynamic_CCA( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurrentMFstate + ) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + if (PrimaryCCA->MF_state != CurrentMFstate){ + + ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate); + } + + PrimaryCCA->MF_state = CurrentMFstate; + +} + +VOID +odm_PrimaryCCA_Check_Init( + IN PDM_ODM_T pDM_Odm) +{ +#if((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) + PADAPTER pAdapter = pDM_Odm->Adapter; + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->Monitor_flag = 0; + PrimaryCCA->PriCCA_flag = 0; + PrimaryCCA->CH_offset = 0; + PrimaryCCA->MF_state = 0; +#endif +} + +VOID +odm_DynamicPrimaryCCA_Check( + IN PDM_ODM_T pDM_Odm + ) +{ + if(pDM_Odm->SupportICType != ODM_RTL8192E) + return; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)) + return; + + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + odm_DynamicPrimaryCCAMP(pDM_Odm); +#endif + break; + + case ODM_CE: +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + +#endif + break; + + case ODM_AP: +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_DynamicPrimaryCCAAP(pDM_Odm); +#endif + break; + } + +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_DynamicPrimaryCCAMP( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); +#else + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); +#endif + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + BOOLEAN Is40MHz = FALSE; + u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt; + u1Byte SecCHOffset; + u1Byte CurMFstate; + static u1Byte CountDown = Monitor_TIME; + + OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA; + OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail; + BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC; + BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM CCA=%d\n", OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM FA=%d\n", OFDM_FA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_USC=%d\n", BW_USC_Cnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_LSC=%d\n", BW_LSC_Cnt)); + Is40MHz = *(pDM_Odm->pBandWidth); + SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above + //DbgPrint("92E: SecCHOffset = %d\n", SecCHOffset); + if(IsAPModeExist(pAdapter)){ + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + return; + } + + if(!pDM_Odm->bLinked){ + return; + } + else{ + + if(Is40MHz){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Cont Down= %d\n", CountDown)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_Type=%d\n", PrimaryCCA->intf_type)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_flag=%d\n", PrimaryCCA->intf_flag )); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag)); + //DbgPrint("92E RTS_EN=%d\n", pHalData->RTSEN); + + if(PrimaryCCA->PriCCA_flag == 0){ + + if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition + + if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) + && (OFDM_FA>(OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 1; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + } + else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) + && (OFDM_FA < (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 2; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + PrimaryCCA->DupRTS_flag = 1; + pHalData->RTSEN = 1; + } + else{ + + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + } + + } + else if (SecCHOffset == 1){ + + if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias)) + && (OFDM_FA > (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 1; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + } + else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias)) + && (OFDM_FA < (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 2; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + PrimaryCCA->DupRTS_flag = 1; + pHalData->RTSEN = 1; + } + else{ + + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + } + + } + + } + else{ // PrimaryCCA->PriCCA_flag==1 + + CountDown--; + if(CountDown == 0){ + CountDown = Monitor_TIME; + PrimaryCCA->PriCCA_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + } + + } + + } + else{ + + return; + } + } + +} + +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +odm_DynamicPrimaryCCAAP( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + prtl8192cd_priv priv = pDM_Odm->priv; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); +#else + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); +#endif + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte i; + static u4Byte Count_Down = Monitor_TIME; + BOOLEAN STA_BW = FALSE, STA_BW_pre = FALSE, STA_BW_TMP = FALSE; + BOOLEAN bConnected = FALSE; + BOOLEAN Is40MHz = FALSE; + u1Byte SecCHOffset; + u1Byte CurMFstate; + PSTA_INFO_T pstat; + + Is40MHz = *(pDM_Odm->pBandWidth); + SecCHOffset = *(pDM_Odm->pSecChOffset); // AP: 1: sec is below, 2: sec is above + + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat)){ + + STA_BW_TMP = pstat->tx_bw; + if(STA_BW_TMP > STA_BW){ + STA_BW = STA_BW_TMP; + } + bConnected = TRUE; + } + } + + if(Is40MHz){ + + if(PrimaryCCA->PriCCA_flag == 0){ + + if(bConnected){ + + if(STA_BW == 0){ //2 STA BW=20M + + PrimaryCCA->PriCCA_flag = 1; + if(SecCHOffset==1){ + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + } + else if(SecCHOffset==2){ + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + } + } + else{ //2 STA BW=40M + if(PrimaryCCA->intf_flag == 0){ + + odm_Intf_Detection(pDM_Odm); + } + else{ // intf_flag = 1 + + if(PrimaryCCA->intf_type == 1){ + + if(PrimaryCCA->CH_offset == 1){ + + CurMFstate = MF_USC; + if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + } + } + else if(PrimaryCCA->CH_offset == 2){ + + CurMFstate = MF_LSC; + if(SecCHOffset == 2){ + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + } + } + } + else if(PrimaryCCA->intf_type==2){ + + if(PrimaryCCA->CH_offset==1){ + + //ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_USC); + pHalData->RTSEN = 1; + } + else if(PrimaryCCA->CH_offset==2){ + + //ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_LSC); + pHalData->RTSEN = 1; + } + + } + } + } + + } + else{ // disconnected interference detection + + odm_Intf_Detection(pDM_Odm); + }// end of disconnected + + + } + else{ // PrimaryCCA->PriCCA_flag == 1 + + if(STA_BW==0){ + + STA_BW_pre = STA_BW; + return; + } + + Count_Down--; + if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){ + + Count_Down = Monitor_TIME; + PrimaryCCA->PriCCA_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default + pHalData->RTSEN = 0; + + } + + } + + STA_BW_pre = STA_BW; + + } + else{ + //2 Reset + odm_PrimaryCCA_Check_Init(pDM_Odm); + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); + Count_Down = Monitor_TIME; + } + +} + + +VOID +odm_Intf_Detection( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); +#else + PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); +#endif + + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH) + &&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){ + + PrimaryCCA->intf_flag = 1; + PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC + if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){ + PrimaryCCA->intf_type = 1; + } + else{ + PrimaryCCA->intf_type = 2; + } + } + else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH) + &&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){ + + PrimaryCCA->intf_flag = 1; + PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC + if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){ + PrimaryCCA->intf_type = 1; + } + else{ + PrimaryCCA->intf_type = 2; + } + } + else{ + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->CH_offset = 0; + } + +} + +#endif + + + +#endif +#endif // RTL8192E_SUPPORT == 1 + + + + + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.h b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.h index 6cb48768e5f..b810a273ebc 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/phydm_rtl8192e.h @@ -1,67 +1,67 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_RTL8192E_H__ -#define __ODM_RTL8192E_H__ - -#define OFDMCCA_TH 500 -#define BW_Ind_Bias 500 -#define MF_USC 2 -#define MF_LSC 1 -#define MF_USC_LSC 0 -#define Monitor_TIME 30 - -VOID -odm_Write_Dynamic_CCA( - IN PDM_ODM_T pDM_Odm, - IN u1Byte CurrentMFstate - ); - -VOID -odm_PrimaryCCA_Check_Init( - IN PDM_ODM_T pDM_Odm - ); - -VOID -odm_DynamicPrimaryCCA_Check( - IN PDM_ODM_T pDM_Odm - ); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_DynamicPrimaryCCAMP( - IN PDM_ODM_T pDM_Odm - ); - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - -VOID -odm_DynamicPrimaryCCAAP( - IN PDM_ODM_T pDM_Odm - ); - -VOID -odm_Intf_Detection( - IN PDM_ODM_T pDM_Odm - ); - -#endif - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8192E_H__ +#define __ODM_RTL8192E_H__ + +#define OFDMCCA_TH 500 +#define BW_Ind_Bias 500 +#define MF_USC 2 +#define MF_LSC 1 +#define MF_USC_LSC 0 +#define Monitor_TIME 30 + +VOID +odm_Write_Dynamic_CCA( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurrentMFstate + ); + +VOID +odm_PrimaryCCA_Check_Init( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicPrimaryCCA_Check( + IN PDM_ODM_T pDM_Odm + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_DynamicPrimaryCCAMP( + IN PDM_ODM_T pDM_Odm + ); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +odm_DynamicPrimaryCCAAP( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_Intf_Detection( + IN PDM_ODM_T pDM_Odm + ); + +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8192e/version_rtl8192e.h b/package/kernel/rtl8192cd/phydm/rtl8192e/version_rtl8192e.h index 1161a38e43c..3673f700e2d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8192e/version_rtl8192e.h +++ b/package/kernel/rtl8192cd/phydm/rtl8192e/version_rtl8192e.h @@ -1,10 +1,10 @@ -/*RTL8192E PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8192E 20160314 -#define COMMIT_BY_8192E "BB_DINO" -#define RELEASE_VERSION_8192E 58 +/*RTL8192E PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8192E 20160314 +#define COMMIT_BY_8192E "BB_DINO" +#define RELEASE_VERSION_8192E 58 diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/Hal8197FPhyReg.h b/package/kernel/rtl8192cd/phydm/rtl8197f/Hal8197FPhyReg.h index eaa4f64f710..ca8f51e614c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/Hal8197FPhyReg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/Hal8197FPhyReg.h @@ -1,20 +1,20 @@ -#ifndef __INC_HAL8197FPHYREG_H -#define __INC_HAL8197FPHYREG_H - - -/*--------------------------Define Parameters-------------------------------*/ - -/*BB Register Definition*/ -#define r_dma_trigger_8197F 0x9A0 -#define r_dma_addra_8197F 0x9A4 - -#define r_reset_cfo_rpt_ctrl_8197F 0xD00 - - - -/*--------------------------Define Parameters-------------------------------*/ - - -#endif /*__INC_HAL8197FPHYREG_H*/ - - +#ifndef __INC_HAL8197FPHYREG_H +#define __INC_HAL8197FPHYREG_H + + +/*--------------------------Define Parameters-------------------------------*/ + +/*BB Register Definition*/ +#define r_dma_trigger_8197F 0x9A0 +#define r_dma_addra_8197F 0x9A4 + +#define r_reset_cfo_rpt_ctrl_8197F 0xD00 + + + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif /*__INC_HAL8197FPHYREG_H*/ + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.c b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.c index 84ed598ab90..dbbaf0555cc 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.c @@ -1,5420 +1,5420 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8197F_AGC_TAB[] = { - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x0DB0001F, - 0xC78, 0x0DA0011F, - 0xC78, 0x0D90021F, - 0xC78, 0x0D80031F, - 0xC78, 0x0D70041F, - 0xC78, 0x0D60051F, - 0xC78, 0x0D50061F, - 0xC78, 0x0D40071F, - 0xC78, 0x0D30081F, - 0xC78, 0x0D20091F, - 0xC78, 0x0D100A1F, - 0xC78, 0x0D000B1F, - 0xC78, 0x0CF00C1F, - 0xC78, 0x0CE00D1F, - 0xC78, 0x0CD00E1F, - 0xC78, 0x0CC00F1F, - 0xC78, 0x0CB0101F, - 0xC78, 0x0CA0111F, - 0xC78, 0x0C90121F, - 0xC78, 0x0C80131F, - 0xC78, 0x0C70141F, - 0xC78, 0x0C60151F, - 0xC78, 0x0C50161F, - 0xC78, 0x0C40171F, - 0xC78, 0x0C30181F, - 0xC78, 0x0C20191F, - 0xC78, 0x0C101A1F, - 0xC78, 0x0A501B1F, - 0xC78, 0x0A401C1F, - 0xC78, 0x0A301D1F, - 0xC78, 0x0A201E1F, - 0xC78, 0x0A101F1F, - 0xC78, 0x0A00201F, - 0xC78, 0x0820211F, - 0xC78, 0x0810221F, - 0xC78, 0x0650231F, - 0xC78, 0x0640241F, - 0xC78, 0x0630251F, - 0xC78, 0x0450261F, - 0xC78, 0x0440271F, - 0xC78, 0x0430281F, - 0xC78, 0x0420291F, - 0xC78, 0x04102A1F, - 0xC78, 0x04002B1F, - 0xC78, 0x02402C1F, - 0xC78, 0x02302D1F, - 0xC78, 0x00602E1F, - 0xC78, 0x00502F1F, - 0xC78, 0x0040301F, - 0xC78, 0x0030311F, - 0xC78, 0x0020321F, - 0xC78, 0x0010331F, - 0xC78, 0x0000341F, - 0xC78, 0x0000351F, - 0xC78, 0x0000361F, - 0xC78, 0x0000371F, - 0xC78, 0x0000381F, - 0xC78, 0x0000391F, - 0xC78, 0x00003A1F, - 0xC78, 0x00003B1F, - 0xC78, 0x00003C1F, - 0xC78, 0x00003D1F, - 0xC78, 0x00003E1F, - 0xC78, 0x00003F1F, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x0F40001F, - 0xC78, 0x0F30011F, - 0xC78, 0x0F20021F, - 0xC78, 0x0F10031F, - 0xC78, 0x0F00041F, - 0xC78, 0x0EF0051F, - 0xC78, 0x0EE0061F, - 0xC78, 0x0ED0071F, - 0xC78, 0x0EC0081F, - 0xC78, 0x0EB0091F, - 0xC78, 0x0EA00A1F, - 0xC78, 0x0E900B1F, - 0xC78, 0x0CD00C1F, - 0xC78, 0x0CC00D1F, - 0xC78, 0x0CB00E1F, - 0xC78, 0x0CA00F1F, - 0xC78, 0x0E40101F, - 0xC78, 0x0E30111F, - 0xC78, 0x0AB0121F, - 0xC78, 0x0AA0131F, - 0xC78, 0x0A90141F, - 0xC78, 0x0A80151F, - 0xC78, 0x0A70161F, - 0xC78, 0x0A60171F, - 0xC78, 0x0A50181F, - 0xC78, 0x0A40191F, - 0xC78, 0x0A301A1F, - 0xC78, 0x0A201B1F, - 0xC78, 0x0A101C1F, - 0xC78, 0x08401D1F, - 0xC78, 0x08301E1F, - 0xC78, 0x08201F1F, - 0xC78, 0x0810201F, - 0xC78, 0x0640211F, - 0xC78, 0x0630221F, - 0xC78, 0x0620231F, - 0xC78, 0x0610241F, - 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0xC78, 0x0D30861F, - 0xC78, 0x0D20871F, - 0xC78, 0x0980881F, - 0xC78, 0x0970891F, - 0xC78, 0x09608A1F, - 0xC78, 0x09508B1F, - 0xC78, 0x09408C1F, - 0xC78, 0x07808D1F, - 0xC78, 0x07708E1F, - 0xC78, 0x07608F1F, - 0xC78, 0x0750901F, - 0xC78, 0x0740911F, - 0xC78, 0x0730921F, - 0xC78, 0x0580931F, - 0xC78, 0x0570941F, - 0xC78, 0x0560951F, - 0xC78, 0x0550961F, - 0xC78, 0x0540971F, - 0xC78, 0x0530981F, - 0xC78, 0x0520991F, - 0xC78, 0x05109A1F, - 0xC78, 0x05009B1F, - 0xC78, 0x04F09C1F, - 0xC78, 0x04E09D1F, - 0xC78, 0x04D09E1F, - 0xC78, 0x04C09F1F, - 0xC78, 0x04B0A01F, - 0xC78, 0x04A0A11F, - 0xC78, 0x0490A21F, - 0xC78, 0x0480A31F, - 0xC78, 0x0470A41F, - 0xC78, 0x0460A51F, - 0xC78, 0x0450A61F, - 0xC78, 0x0440A71F, - 0xC78, 0x0430A81F, - 0xC78, 0x0270A91F, - 0xC78, 0x0260AA1F, - 0xC78, 0x0250AB1F, - 0xC78, 0x0240AC1F, - 0xC78, 0x0230AD1F, - 0xC78, 0x0220AE1F, - 0xC78, 0x0210AF1F, - 0xC78, 0x0050B01F, - 0xC78, 0x0040B11F, - 0xC78, 0x0030B21F, - 0xC78, 0x0020B31F, - 0xC78, 0x0010B41F, - 0xC78, 0x0010B51F, - 0xC78, 0x0010B61F, - 0xC78, 0x0010B71F, - 0xC78, 0x0010B81F, - 0xC78, 0x0010B91F, - 0xC78, 0x0010BA1F, - 0xC78, 0x0010BB1F, - 0xC78, 0x0010BC1F, - 0xC78, 0x0010BD1F, - 0xC78, 0x0010BE1F, - 0xC78, 0x0010BF1F, - 0xC50, 0x00340222, - 0xC50, 0x00340220, - 0xC58, 0x00000222, - 0xC58, 0x00000220, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC78, 0x0F40801F, - 0xC78, 0x0F30811F, - 0xC78, 0x0F20821F, - 0xC78, 0x0F10831F, - 0xC78, 0x0F00841F, - 0xC78, 0x0D40851F, - 0xC78, 0x0D30861F, - 0xC78, 0x0D20871F, - 0xC78, 0x0980881F, - 0xC78, 0x0970891F, - 0xC78, 0x09608A1F, - 0xC78, 0x09508B1F, - 0xC78, 0x09408C1F, - 0xC78, 0x07808D1F, - 0xC78, 0x07708E1F, - 0xC78, 0x07608F1F, - 0xC78, 0x0750901F, - 0xC78, 0x0740911F, - 0xC78, 0x0730921F, - 0xC78, 0x0580931F, - 0xC78, 0x0570941F, - 0xC78, 0x0560951F, - 0xC78, 0x0550961F, - 0xC78, 0x0540971F, - 0xC78, 0x0530981F, - 0xC78, 0x0520991F, - 0xC78, 0x05109A1F, - 0xC78, 0x05009B1F, - 0xC78, 0x04F09C1F, - 0xC78, 0x04E09D1F, - 0xC78, 0x04D09E1F, - 0xC78, 0x04C09F1F, - 0xC78, 0x04B0A01F, - 0xC78, 0x04A0A11F, - 0xC78, 0x0490A21F, - 0xC78, 0x0480A31F, - 0xC78, 0x0470A41F, - 0xC78, 0x0460A51F, - 0xC78, 0x0450A61F, - 0xC78, 0x0440A71F, - 0xC78, 0x0430A81F, - 0xC78, 0x0270A91F, - 0xC78, 0x0260AA1F, - 0xC78, 0x0250AB1F, - 0xC78, 0x0240AC1F, - 0xC78, 0x0230AD1F, - 0xC78, 0x0220AE1F, - 0xC78, 0x0210AF1F, - 0xC78, 0x0050B01F, - 0xC78, 0x0040B11F, - 0xC78, 0x0030B21F, - 0xC78, 0x0020B31F, - 0xC78, 0x0010B41F, - 0xC78, 0x0010B51F, - 0xC78, 0x0010B61F, - 0xC78, 0x0010B71F, - 0xC78, 0x0010B81F, - 0xC78, 0x0010B91F, - 0xC78, 0x0010BA1F, - 0xC78, 0x0010BB1F, - 0xC78, 0x0010BC1F, - 0xC78, 0x0010BD1F, - 0xC78, 0x0010BE1F, - 0xC78, 0x0010BF1F, - 0xC50, 0x00340222, - 0xC50, 0x00340220, - 0xC58, 0x00000222, - 0xC58, 0x00000220, - 0xA0000000, 0x00000000, - 0xC78, 0x0FE0801F, - 0xC78, 0x0FD0811F, - 0xC78, 0x0FC0821F, - 0xC78, 0x0FB0831F, - 0xC78, 0x0FA0841F, - 0xC78, 0x0F90851F, - 0xC78, 0x0F80861F, - 0xC78, 0x0F70871F, - 0xC78, 0x0F60881F, - 0xC78, 0x0F50891F, - 0xC78, 0x0F408A1F, - 0xC78, 0x0D708B1F, - 0xC78, 0x0D608C1F, - 0xC78, 0x0D508D1F, - 0xC78, 0x0D408E1F, - 0xC78, 0x0D308F1F, - 0xC78, 0x0B70901F, - 0xC78, 0x0B60911F, - 0xC78, 0x0B50921F, - 0xC78, 0x0B40931F, - 0xC78, 0x0B30941F, - 0xC78, 0x0B20951F, - 0xC78, 0x0B10961F, - 0xC78, 0x0B00971F, - 0xC78, 0x0AF0981F, - 0xC78, 0x0AE0991F, - 0xC78, 0x0AD09A1F, - 0xC78, 0x0AC09B1F, - 0xC78, 0x0AB09C1F, - 0xC78, 0x0AA09D1F, - 0xC78, 0x0A909E1F, - 0xC78, 0x0A809F1F, - 0xC78, 0x0A70A01F, - 0xC78, 0x0A60A11F, - 0xC78, 0x0A50A21F, - 0xC78, 0x0A40A31F, - 0xC78, 0x0A30A41F, - 0xC78, 0x0860A51F, - 0xC78, 0x0850A61F, - 0xC78, 0x0840A71F, - 0xC78, 0x0670A81F, - 0xC78, 0x0660A91F, - 0xC78, 0x0650AA1F, - 0xC78, 0x0640AB1F, - 0xC78, 0x0470AC1F, - 0xC78, 0x0460AD1F, - 0xC78, 0x0450AE1F, - 0xC78, 0x0290AF1F, - 0xC78, 0x0280B01F, - 0xC78, 0x0270B11F, - 0xC78, 0x0260B21F, - 0xC78, 0x0250B31F, - 0xC78, 0x0060B41F, - 0xC78, 0x0050B51F, - 0xC78, 0x0040B61F, - 0xC78, 0x0030B71F, - 0xC78, 0x0020B81F, - 0xC78, 0x0010B91F, - 0xC78, 0x0000BA1F, - 0xC78, 0x0000BB1F, - 0xC78, 0x0000BC1F, - 0xC78, 0x0000BD1F, - 0xC78, 0x0000BE1F, - 0xC78, 0x0000BF1F, - 0xC50, 0x00340022, - 0xC50, 0x00340020, - 0xC58, 0x00000022, - 0xC58, 0x00000020, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8197F_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8197F_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8197F_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8197F(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8197F_AGC_TAB(void) -{ - return 66; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8197F_PHY_REG[] = { - 0x800, 0x83005308, - 0x804, 0x00004001, - 0x808, 0x0000FC00, - 0x80C, 0x00000000, - 0x810, 0x22000322, - 0x814, 0x020C3D10, - 0x818, 0x00000385, - 0x81C, 0x07000000, - 0x820, 0x01000100, - 0x824, 0x00390204, - 0x828, 0x01000100, - 0x82C, 0x00390204, - 0x830, 0x00000000, - 0x834, 0x00690200, - 0x838, 0x00000004, - 0x83C, 0x00690200, - 0x840, 0x00010000, - 0x844, 0x00010000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00031FE0, - 0x854, 0x00000000, - 0x858, 0x569A569A, - 0x85C, 0x00400040, - 0x860, 0x66F60000, - 0x864, 0x061F0000, - 0x868, 0x0F7F0130, - 0x86C, 0x0F7F0130, - 0x870, 0x00000300, - 0x874, 0x04003400, - 0x878, 0x08080808, - 0x87C, 0x004F0201, - 0x880, 0xD8001402, - 0x884, 0xC0000120, - 0x888, 0x00000000, - 0x88C, 0xCC0000C0, - 0x890, 0x00000000, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x8A0, 0x00000000, - 0x8A4, 0x00000000, - 0x8A8, 0x00000109, - 0x8AC, 0x00000000, - 0x8B0, 0x00000000, - 0x8B4, 0x00000000, - 0x8B8, 0x00000000, - 0x8BC, 0x00000000, - 0x8C0, 0x03910C40, - 0x8C4, 0x00000000, - 0x8C8, 0x00000000, - 0x8CC, 0x00000000, - 0x8D0, 0x00000000, - 0x8D4, 0x00000000, - 0x8D8, 0x00000000, - 0x8DC, 0x00000000, - 0x8E0, 0x02000200, - 0x8E4, 0x00000000, - 0x8E8, 0xD8080000, - 0x8EC, 0x00000000, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000F00, - 0x90C, 0x81121313, - 0x910, 0x024C0000, - 0x914, 0x00000000, - 0x918, 0x00000000, - 0x91C, 0x00000000, - 0x920, 0x00000000, - 0x924, 0x00000000, - 0x928, 0x00000000, - 0x92C, 0x00000000, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFFFFFF, - 0x934, 0xFFFFF2F5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF5F2F, - 0x940, 0xFF44FFFF, - 0x944, 0x3F3F0F00, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0x88000000, - 0x934, 0x00000245, - 0x938, 0x00024588, - 0x93C, 0x00000000, - 0x940, 0x000007FF, - 0x944, 0x3F3F0000, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0x88000000, - 0x934, 0x00000245, - 0x938, 0x00024588, - 0x93C, 0x00000000, - 0x940, 0x000007FF, - 0x944, 0x3F3F0000, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFFFFFF, - 0x934, 0xFFFFF2F5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF5F2F, - 0x940, 0xFF44FFFF, - 0x944, 0x3F3F0F00, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x930, 0xFFFF02FF, - 0x934, 0xFFFFFFF5, - 0x938, 0xFFFFFFFF, - 0x93C, 0xFFFF502F, - 0x940, 0xFF54FF0F, - 0x944, 0x3F3F0F0C, - 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0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0xE82C0001, - 0xA24, 0x64B80C1C, - 0xA28, 0x00008810, - 0xA2C, 0x00920000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000107, - 0xA78, 0x00008900, - 0xA7C, 0x225B0606, - 0xA80, 0x21807532, - 0xA84, 0x00110000, - 0xA88, 0x040C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x00000000, - 0xA9C, 0x3F000000, - 0xAA0, 0x00000000, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0xAA4, 0x00010010, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 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0xC50, 0x00340220, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340020, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340020, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00340220, - 0xA0000000, 0x00000000, - 0xC50, 0x00340020, - 0xB0000000, 0x00000000, - 0xC54, 0x04008017, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000020, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000020, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000020, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000020, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC58, 0x00000220, - 0xA0000000, 0x00000000, - 0xC58, 0x00000020, - 0xB0000000, 0x00000000, - 0xC5C, 0x00708492, - 0xC60, 0x002E0200, - 0xC64, 0x5012838B, - 0xC68, 0x47C006C7, - 0xC6C, 0x00000035, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020155A7, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020155A7, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00001007, - 0xC74, 0x020251E9, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00001007, - 0xC74, 0x020251E9, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020151A9, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020151A9, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020151A7, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00001007, - 0xC74, 0x020251A9, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00001007, - 0xC74, 0x020251A9, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC70, 0x00000007, - 0xC74, 0x020251A7, - 0xA0000000, 0x00000000, - 0xC70, 0x00001007, - 0xC74, 0x020251A9, - 0xB0000000, 0x00000000, - 0xC78, 0x0FE07F1F, - 0xC7C, 0x00B91612, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x24000090, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC80, 0x40000100, - 0xA0000000, 0x00000000, - 0xC80, 0x40000100, - 0xB0000000, 0x00000000, - 0xC84, 0x32000000, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x24000090, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0xC88, 0x40000100, - 0xA0000000, 0x00000000, - 0xC88, 0x40000100, - 0xB0000000, 0x00000000, - 0xC8C, 0xA0240000, - 0xC90, 0x40000100, - 0xC94, 0x00000000, - 0xC98, 0x40000100, - 0xC9C, 0x0000BDC8, - 0xCA0, 0x00000000, - 0xCA4, 0x098300A0, - 0xCA8, 0x00000000, - 0xCAC, 0x00F5FB1A, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28100200, - 0xCC0, 0x0010A3D0, - 0xCC4, 0x00000F7D, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x40201001, - 0xCE4, 0x00000000, - 0xCE8, 0x40E04407, - 0xCEC, 0x2E572000, - 0xCF0, 0x00000000, - 0xCF4, 0x00000000, - 0xCF8, 0x00000000, - 0xD00, 0x000B0680, - 0xD04, 0xC0020403, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0x06288888, - 0xD14, 0x8888366B, - 0xD18, 0x7D806DB3, - 0xD1C, 0x0000007F, - 0xD20, 0x167401B8, - 0xD24, 0x0000018B, - 0xD28, 0xD513FF7D, - 0xD2C, 0xCC979975, - 0xD30, 0x00008000, - 0xD34, 0x40608000, - 0xD38, 0xA8000000, - 0xD3C, 0x00026EE2, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x20500000, - 0xD58, 0x16161616, - 0xD5C, 0x70320064, - 0xD60, 0x4653DE60, - 0xD64, 0x7E718A3C, - 0xD68, 0x00000103, - 0xD6C, 0x00000000, - 0xD70, 0x00000000, - 0xD74, 0x00000000, - 0xD78, 0x00000000, - 0xD7C, 0x00000000, - 0xD80, 0x00000000, - 0xD84, 0x31310000, - 0xD88, 0xF5B50000, - 0xD8C, 0x00000000, - 0xD90, 0x00000000, - 0xD94, 0x44BBBB44, - 0xD98, 0x44BB44FF, - 0xD9C, 0x06033688, - 0xDA0, 0x00000002, - 0xDA4, 0x00000000, - 0xDA8, 0x00000000, - 0xDAC, 0x00000000, - 0xDB0, 0x00000000, - 0xDB4, 0x00000000, - 0xDB8, 0x00000000, - 0xDBC, 0x00000000, - 0xDC0, 0x00000000, - 0xDC4, 0x00210000, - 0xDC8, 0x00000200, - 0xDCC, 0x0000000F, - 0xDD0, 0x00000020, - 0xDD4, 0x00007F7F, - 0xDD8, 0xE5AF1854, - 0xDDC, 0x000040AB, - 0xDE0, 0x00000000, - 0xDE4, 0x00000000, - 0xDE8, 0x0002030B, - 0xDEC, 0x0000A987, - 0xDF0, 0x00005807, - 0xDF4, 0x00000000, - 0xDF8, 0x00000005, - 0xE00, 0x00000000, - 0xE04, 0x00000000, - 0xE08, 0x00000000, - 0xE0C, 0x000000FF, - 0xE10, 0x00000000, - 0xE14, 0x00000000, - 0xE18, 0x00000000, - 0xE1C, 0x00000000, - 0xE20, 0x00000000, - 0xE24, 0x00200000, - 0xE28, 0x00000000, - 0xE2C, 0x00000000, - 0xE30, 0x01007C00, - 0xE34, 0x01004800, - 0xE38, 0x10008C0F, - 0xE3C, 0x3C008C0F, - 0xE40, 0x01007C00, - 0xE44, 0x00000000, - 0xE48, 0x00000000, - 0xE4C, 0x00000000, - 0xE50, 0x01007C00, - 0xE54, 0x01004800, - 0xE58, 0x10008C0F, - 0xE5C, 0x3C008C0F, - 0xE60, 0x02100000, - 0xE64, 0xBBBBBBBB, - 0xE68, 0x40404040, - 0xE6C, 0x80408040, - 0xE70, 0x80408040, - 0xE74, 0x40404040, - 0xE78, 0x00400040, - 0xE7C, 0x40404040, - 0xE80, 0x00FF0000, - 0xE84, 0x80408040, - 0xE88, 0x40404040, - 0xE8C, 0x80408040, - 0xE90, 0x00000000, - 0xE94, 0x01000000, - 0xE98, 0x00000000, - 0xE9C, 0x00000000, - 0xEA0, 0x00000000, - 0xEA4, 0x01000000, - 0xEA8, 0x00000000, - 0xEAC, 0x00000000, - 0xEB0, 0x00000000, - 0xEB4, 0x01000000, - 0xEB8, 0x00000000, - 0xEBC, 0x00000000, - 0xEC0, 0x00000000, - 0xEC4, 0x01000000, - 0xEC8, 0x00000000, - 0xECC, 0x00000000, - 0xED0, 0x80408040, - 0xED4, 0x80408040, - 0xED8, 0x80408040, - 0xEDC, 0xC040C040, - 0xEE0, 0xC040C040, - 0xEE4, 0x00400040, - 0xEE8, 0xD8001402, - 0xEEC, 0xC0000120, - 0xEF0, 0x02000B09, - 0xEF4, 0x00000001, - 0xEF8, 0x00000000, - 0xF00, 0x00000300, - 0xF04, 0x00000000, - 0xF08, 0x0002030B, - 0xF0C, 0x0000A987, - 0xF10, 0x00005807, - 0xF14, 0x00000003, - 0xF18, 0x00020002, - 0xF1C, 0x8000001F, - 0xF20, 0x00000000, - 0xF24, 0x00000000, - 0xF28, 0x00000000, - 0xF2C, 0x00000000, - 0xF30, 0x00000000, - 0xF34, 0x00000000, - 0xF38, 0x00030155, - 0xF3C, 0x0000003A, - 0xF40, 0x00000000, - 0xF44, 0x00000000, - 0xF48, 0x00030000, - 0xF4C, 0x13000000, - 0xF50, 0x00000010, - 0xF54, 0x00000000, - 0xF58, 0x00000000, - 0xF5C, 0x00000000, - 0xF60, 0x00000000, - 0xF64, 0x00000000, - 0xF68, 0x00000000, - 0xF6C, 0x00000000, - 0xF70, 0x00000000, - 0xF74, 0x00000000, - 0xF78, 0x00000000, - 0xF7C, 0x00000000, - 0xF80, 0x00000000, - 0xF84, 0x00000000, - 0xF88, 0x00000000, - 0xF8C, 0x00000000, - 0xF90, 0x00000002, - 0xF94, 0x00000000, - 0xF98, 0x00000000, - 0xF9C, 0x00000000, - 0xFA0, 0x00000000, - 0xFA4, 0x0002030B, - 0xFA8, 0x0000A987, - 0xFAC, 0x00005807, - 0xFB0, 0x00000000, - 0xFB4, 0x00000000, - 0xFB8, 0x00000000, - 0xFBC, 0x00000000, - 0xFC0, 0x00C02001, - 0xFC4, 0x90063000, - 0xFC8, 0x00000018, - 0xFCC, 0x10003005, - 0xFD0, 0x0000E5AF, - 0xFD4, 0x00000000, - 0xFD8, 0x00000000, - 0xFDC, 0x00000000, - 0xFE0, 0x00000000, - 0xFE4, 0x00000000, - 0xFE8, 0x00000000, - 0xFEC, 0x00000000, - 0xFF0, 0x00000000, - 0xFF4, 0x00000000, - 0xFF8, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8197F_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8197F_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8197F_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8197F(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8197F_PHY_REG(void) -{ - return 66; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8197F_AGC_TAB[] = { + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0DB0001F, + 0xC78, 0x0DA0011F, + 0xC78, 0x0D90021F, + 0xC78, 0x0D80031F, + 0xC78, 0x0D70041F, + 0xC78, 0x0D60051F, + 0xC78, 0x0D50061F, + 0xC78, 0x0D40071F, + 0xC78, 0x0D30081F, + 0xC78, 0x0D20091F, + 0xC78, 0x0D100A1F, + 0xC78, 0x0D000B1F, + 0xC78, 0x0CF00C1F, + 0xC78, 0x0CE00D1F, + 0xC78, 0x0CD00E1F, + 0xC78, 0x0CC00F1F, + 0xC78, 0x0CB0101F, + 0xC78, 0x0CA0111F, + 0xC78, 0x0C90121F, + 0xC78, 0x0C80131F, + 0xC78, 0x0C70141F, + 0xC78, 0x0C60151F, + 0xC78, 0x0C50161F, + 0xC78, 0x0C40171F, + 0xC78, 0x0C30181F, + 0xC78, 0x0C20191F, + 0xC78, 0x0C101A1F, + 0xC78, 0x0A501B1F, + 0xC78, 0x0A401C1F, + 0xC78, 0x0A301D1F, + 0xC78, 0x0A201E1F, + 0xC78, 0x0A101F1F, + 0xC78, 0x0A00201F, + 0xC78, 0x0820211F, + 0xC78, 0x0810221F, + 0xC78, 0x0650231F, + 0xC78, 0x0640241F, + 0xC78, 0x0630251F, + 0xC78, 0x0450261F, + 0xC78, 0x0440271F, + 0xC78, 0x0430281F, + 0xC78, 0x0420291F, + 0xC78, 0x04102A1F, + 0xC78, 0x04002B1F, + 0xC78, 0x02402C1F, + 0xC78, 0x02302D1F, + 0xC78, 0x00602E1F, + 0xC78, 0x00502F1F, + 0xC78, 0x0040301F, + 0xC78, 0x0030311F, + 0xC78, 0x0020321F, + 0xC78, 0x0010331F, + 0xC78, 0x0000341F, + 0xC78, 0x0000351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F40001F, + 0xC78, 0x0F30011F, + 0xC78, 0x0F20021F, + 0xC78, 0x0F10031F, + 0xC78, 0x0F00041F, + 0xC78, 0x0EF0051F, + 0xC78, 0x0EE0061F, + 0xC78, 0x0ED0071F, + 0xC78, 0x0EC0081F, + 0xC78, 0x0EB0091F, + 0xC78, 0x0EA00A1F, + 0xC78, 0x0E900B1F, + 0xC78, 0x0CD00C1F, + 0xC78, 0x0CC00D1F, + 0xC78, 0x0CB00E1F, + 0xC78, 0x0CA00F1F, + 0xC78, 0x0E40101F, + 0xC78, 0x0E30111F, + 0xC78, 0x0AB0121F, + 0xC78, 0x0AA0131F, + 0xC78, 0x0A90141F, + 0xC78, 0x0A80151F, + 0xC78, 0x0A70161F, + 0xC78, 0x0A60171F, + 0xC78, 0x0A50181F, + 0xC78, 0x0A40191F, + 0xC78, 0x0A301A1F, + 0xC78, 0x0A201B1F, + 0xC78, 0x0A101C1F, + 0xC78, 0x08401D1F, + 0xC78, 0x08301E1F, + 0xC78, 0x08201F1F, + 0xC78, 0x0810201F, + 0xC78, 0x0640211F, + 0xC78, 0x0630221F, + 0xC78, 0x0620231F, + 0xC78, 0x0610241F, + 0xC78, 0x0450251F, + 0xC78, 0x0440261F, + 0xC78, 0x0430271F, + 0xC78, 0x0420281F, + 0xC78, 0x0410291F, + 0xC78, 0x02402A1F, + 0xC78, 0x02302B1F, + 0xC78, 0x02202C1F, + 0xC78, 0x02102D1F, + 0xC78, 0x00502E1F, + 0xC78, 0x00402F1F, + 0xC78, 0x0030301F, + 0xC78, 0x0020311F, + 0xC78, 0x0010321F, + 0xC78, 0x0000331F, + 0xC78, 0x0000341F, + 0xC78, 0x0000351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F00001F, + 0xC78, 0x0EF0011F, + 0xC78, 0x0EE0021F, + 0xC78, 0x0ED0031F, + 0xC78, 0x0EC0041F, + 0xC78, 0x0EB0051F, + 0xC78, 0x0EA0061F, + 0xC78, 0x0E90071F, + 0xC78, 0x0E80081F, + 0xC78, 0x0E70091F, + 0xC78, 0x0AF00A1F, + 0xC78, 0x0AE00B1F, + 0xC78, 0x0AD00C1F, + 0xC78, 0x0AC00D1F, + 0xC78, 0x0AB00E1F, + 0xC78, 0x0AA00F1F, + 0xC78, 0x0A90101F, + 0xC78, 0x0A80111F, + 0xC78, 0x0A70121F, + 0xC78, 0x0A60131F, + 0xC78, 0x0890141F, + 0xC78, 0x0880151F, + 0xC78, 0x0870161F, + 0xC78, 0x0860171F, + 0xC78, 0x0850181F, + 0xC78, 0x0840191F, + 0xC78, 0x08301A1F, + 0xC78, 0x08201B1F, + 0xC78, 0x08101C1F, + 0xC78, 0x06501D1F, + 0xC78, 0x06401E1F, + 0xC78, 0x06301F1F, + 0xC78, 0x0620201F, + 0xC78, 0x0610211F, + 0xC78, 0x0470221F, + 0xC78, 0x0460231F, + 0xC78, 0x0450241F, + 0xC78, 0x0440251F, + 0xC78, 0x0430261F, + 0xC78, 0x0420271F, + 0xC78, 0x0410281F, + 0xC78, 0x0240291F, + 0xC78, 0x02302A1F, + 0xC78, 0x02202B1F, + 0xC78, 0x02102C1F, + 0xC78, 0x00502D1F, + 0xC78, 0x00402E1F, + 0xC78, 0x00302F1F, + 0xC78, 0x0020301F, + 0xC78, 0x0010311F, + 0xC78, 0x0000321F, + 0xC78, 0x0000331F, + 0xC78, 0x0000341F, + 0xC78, 0x0000351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F40001F, + 0xC78, 0x0F30011F, + 0xC78, 0x0F20021F, + 0xC78, 0x0F10031F, + 0xC78, 0x0F00041F, + 0xC78, 0x0D40051F, + 0xC78, 0x0D30061F, + 0xC78, 0x0D20071F, + 0xC78, 0x0D10081F, + 0xC78, 0x0D00091F, + 0xC78, 0x0CF00A1F, + 0xC78, 0x0CE00B1F, + 0xC78, 0x0CD00C1F, + 0xC78, 0x0CC00D1F, + 0xC78, 0x0AF00E1F, + 0xC78, 0x0AE00F1F, + 0xC78, 0x0AD0101F, + 0xC78, 0x0AC0111F, + 0xC78, 0x0AB0121F, + 0xC78, 0x0AA0131F, + 0xC78, 0x0A90141F, + 0xC78, 0x0A80151F, + 0xC78, 0x0A70161F, + 0xC78, 0x0A60171F, + 0xC78, 0x0A50181F, + 0xC78, 0x0A40191F, + 0xC78, 0x0A301A1F, + 0xC78, 0x08501B1F, + 0xC78, 0x08401C1F, + 0xC78, 0x08301D1F, + 0xC78, 0x06701E1F, + 0xC78, 0x06601F1F, + 0xC78, 0x0650201F, + 0xC78, 0x0640211F, + 0xC78, 0x0630221F, + 0xC78, 0x0620231F, + 0xC78, 0x0470241F, + 0xC78, 0x0460251F, + 0xC78, 0x0450261F, + 0xC78, 0x0440271F, + 0xC78, 0x0430281F, + 0xC78, 0x0270291F, + 0xC78, 0x02602A1F, + 0xC78, 0x02502B1F, + 0xC78, 0x02402C1F, + 0xC78, 0x02302D1F, + 0xC78, 0x02202E1F, + 0xC78, 0x02102F1F, + 0xC78, 0x0050301F, + 0xC78, 0x0040311F, + 0xC78, 0x0030321F, + 0xC78, 0x0020331F, + 0xC78, 0x0010341F, + 0xC78, 0x0010351F, + 0xC78, 0x0010361F, + 0xC78, 0x0010371F, + 0xC78, 0x0010381F, + 0xC78, 0x0010391F, + 0xC78, 0x00103A1F, + 0xC78, 0x00103B1F, + 0xC78, 0x00103C1F, + 0xC78, 0x00103D1F, + 0xC78, 0x00103E1F, + 0xC78, 0x00103F1F, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0D50001F, + 0xC78, 0x0D40011F, + 0xC78, 0x0D30021F, + 0xC78, 0x0D20031F, + 0xC78, 0x0D10041F, + 0xC78, 0x0D00051F, + 0xC78, 0x0CF0061F, + 0xC78, 0x0CE0071F, + 0xC78, 0x0CD0081F, + 0xC78, 0x0CC0091F, + 0xC78, 0x0CB00A1F, + 0xC78, 0x0CA00B1F, + 0xC78, 0x0C900C1F, + 0xC78, 0x0C800D1F, + 0xC78, 0x0C700E1F, + 0xC78, 0x0C600F1F, + 0xC78, 0x0C50101F, + 0xC78, 0x0C40111F, + 0xC78, 0x0C30121F, + 0xC78, 0x0A80131F, + 0xC78, 0x0A70141F, + 0xC78, 0x0A60151F, + 0xC78, 0x0A50161F, + 0xC78, 0x0A40171F, + 0xC78, 0x0A30181F, + 0xC78, 0x0860191F, + 0xC78, 0x08501A1F, + 0xC78, 0x08401B1F, + 0xC78, 0x08301C1F, + 0xC78, 0x06701D1F, + 0xC78, 0x06601E1F, + 0xC78, 0x06501F1F, + 0xC78, 0x0640201F, + 0xC78, 0x0630211F, + 0xC78, 0x0490221F, + 0xC78, 0x0480231F, + 0xC78, 0x0470241F, + 0xC78, 0x0460251F, + 0xC78, 0x0450261F, + 0xC78, 0x0290271F, + 0xC78, 0x0280281F, + 0xC78, 0x0270291F, + 0xC78, 0x02602A1F, + 0xC78, 0x02502B1F, + 0xC78, 0x02402C1F, + 0xC78, 0x02302D1F, + 0xC78, 0x02202E1F, + 0xC78, 0x02102F1F, + 0xC78, 0x0200301F, + 0xC78, 0x0040311F, + 0xC78, 0x0030321F, + 0xC78, 0x0020331F, + 0xC78, 0x0010341F, + 0xC78, 0x0000351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F60001F, + 0xC78, 0x0F50011F, + 0xC78, 0x0F40021F, + 0xC78, 0x0F30031F, + 0xC78, 0x0F20041F, + 0xC78, 0x0F10051F, + 0xC78, 0x0F00061F, + 0xC78, 0x0EF0071F, + 0xC78, 0x0EE0081F, + 0xC78, 0x0ED0091F, + 0xC78, 0x0EC00A1F, + 0xC78, 0x0EB00B1F, + 0xC78, 0x0EA00C1F, + 0xC78, 0x0E900D1F, + 0xC78, 0x0E800E1F, + 0xC78, 0x0E700F1F, + 0xC78, 0x0E60101F, + 0xC78, 0x0E50111F, + 0xC78, 0x0E40121F, + 0xC78, 0x0E30131F, + 0xC78, 0x0C70141F, + 0xC78, 0x0C60151F, + 0xC78, 0x0C50161F, + 0xC78, 0x0C40171F, + 0xC78, 0x0C30181F, + 0xC78, 0x0C20191F, + 0xC78, 0x0C101A1F, + 0xC78, 0x0A401B1F, + 0xC78, 0x0A301C1F, + 0xC78, 0x0A201D1F, + 0xC78, 0x0A101E1F, + 0xC78, 0x06801F1F, + 0xC78, 0x0670201F, + 0xC78, 0x0660211F, + 0xC78, 0x0650221F, + 0xC78, 0x0640231F, + 0xC78, 0x0630241F, + 0xC78, 0x0620251F, + 0xC78, 0x0610261F, + 0xC78, 0x0440271F, + 0xC78, 0x0430281F, + 0xC78, 0x0420291F, + 0xC78, 0x04102A1F, + 0xC78, 0x02502B1F, + 0xC78, 0x02402C1F, + 0xC78, 0x02302D1F, + 0xC78, 0x02202E1F, + 0xC78, 0x02102F1F, + 0xC78, 0x0040301F, + 0xC78, 0x0030311F, + 0xC78, 0x0020321F, + 0xC78, 0x0010331F, + 0xC78, 0x0000341F, + 0xC78, 0x0000351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F20001F, + 0xC78, 0x0F10011F, + 0xC78, 0x0F00021F, + 0xC78, 0x0EF0031F, + 0xC78, 0x0EE0041F, + 0xC78, 0x0ED0051F, + 0xC78, 0x0EC0061F, + 0xC78, 0x0EB0071F, + 0xC78, 0x0EA0081F, + 0xC78, 0x0E90091F, + 0xC78, 0x0E800A1F, + 0xC78, 0x0E700B1F, + 0xC78, 0x0E600C1F, + 0xC78, 0x0E500D1F, + 0xC78, 0x0E400E1F, + 0xC78, 0x0C700F1F, + 0xC78, 0x0C60101F, + 0xC78, 0x0C50111F, + 0xC78, 0x0C40121F, + 0xC78, 0x0C30131F, + 0xC78, 0x0A80141F, + 0xC78, 0x0A70151F, + 0xC78, 0x0A60161F, + 0xC78, 0x0A50171F, + 0xC78, 0x0A40181F, + 0xC78, 0x0A30191F, + 0xC78, 0x08601A1F, + 0xC78, 0x08501B1F, + 0xC78, 0x08401C1F, + 0xC78, 0x08301D1F, + 0xC78, 0x06701E1F, + 0xC78, 0x06601F1F, + 0xC78, 0x0650201F, + 0xC78, 0x0640211F, + 0xC78, 0x0630221F, + 0xC78, 0x0490231F, + 0xC78, 0x0480241F, + 0xC78, 0x0470251F, + 0xC78, 0x0460261F, + 0xC78, 0x0450271F, + 0xC78, 0x0290281F, + 0xC78, 0x0280291F, + 0xC78, 0x02702A1F, + 0xC78, 0x02602B1F, + 0xC78, 0x02502C1F, + 0xC78, 0x02402D1F, + 0xC78, 0x02302E1F, + 0xC78, 0x02202F1F, + 0xC78, 0x0210301F, + 0xC78, 0x0200311F, + 0xC78, 0x0040321F, + 0xC78, 0x0030331F, + 0xC78, 0x0020341F, + 0xC78, 0x0010351F, + 0xC78, 0x0000361F, + 0xC78, 0x0000371F, + 0xC78, 0x0000381F, + 0xC78, 0x0000391F, + 0xC78, 0x00003A1F, + 0xC78, 0x00003B1F, + 0xC78, 0x00003C1F, + 0xC78, 0x00003D1F, + 0xC78, 0x00003E1F, + 0xC78, 0x00003F1F, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F30001F, + 0xC78, 0x0F30011F, + 0xC78, 0x0F20021F, + 0xC78, 0x0F10031F, + 0xC78, 0x0F00041F, + 0xC78, 0x0EF0051F, + 0xC78, 0x0EE0061F, + 0xC78, 0x0ED0071F, + 0xC78, 0x0EC0081F, + 0xC78, 0x0EB0091F, + 0xC78, 0x0EA00A1F, + 0xC78, 0x0E900B1F, + 0xC78, 0x0E800C1F, + 0xC78, 0x0E700D1F, + 0xC78, 0x0E600E1F, + 0xC78, 0x0E500F1F, + 0xC78, 0x0E30101F, + 0xC78, 0x0E20111F, + 0xC78, 0x0C60121F, + 0xC78, 0x0C50131F, + 0xC78, 0x0C40141F, + 0xC78, 0x0C30151F, + 0xC78, 0x0C20161F, + 0xC78, 0x0C10171F, + 0xC78, 0x0A40181F, + 0xC78, 0x0A30191F, + 0xC78, 0x0A201A1F, + 0xC78, 0x0A101B1F, + 0xC78, 0x08401C1F, + 0xC78, 0x08301D1F, + 0xC78, 0x06701E1F, + 0xC78, 0x06601F1F, + 0xC78, 0x0650201F, + 0xC78, 0x0640211F, + 0xC78, 0x0630221F, + 0xC78, 0x0620231F, + 0xC78, 0x0610241F, + 0xC78, 0x0450251F, + 0xC78, 0x0440261F, + 0xC78, 0x0430271F, + 0xC78, 0x0420281F, + 0xC78, 0x0260291F, + 0xC78, 0x02502A1F, + 0xC78, 0x02402B1F, + 0xC78, 0x02302C1F, + 0xC78, 0x02202D1F, + 0xC78, 0x02102E1F, + 0xC78, 0x00502F1F, + 0xC78, 0x0040301F, + 0xC78, 0x0030311F, + 0xC78, 0x0020321F, + 0xC78, 0x0010331F, + 0xC78, 0x0010341F, + 0xC78, 0x0010351F, + 0xC78, 0x0010361F, + 0xC78, 0x0010371F, + 0xC78, 0x0010381F, + 0xC78, 0x0010391F, + 0xC78, 0x00103A1F, + 0xC78, 0x00103B1F, + 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0xC78, 0x0420AF1F, + 0xC78, 0x0410B01F, + 0xC78, 0x0400B11F, + 0xC78, 0x0080B21F, + 0xC78, 0x0070B31F, + 0xC78, 0x0060B41F, + 0xC78, 0x0050B51F, + 0xC78, 0x0040B61F, + 0xC78, 0x0030B71F, + 0xC78, 0x0020B81F, + 0xC78, 0x0010B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340222, + 0xC50, 0x00340220, + 0xC58, 0x00000222, + 0xC58, 0x00000220, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0FD0801F, + 0xC78, 0x0FC0811F, + 0xC78, 0x0FB0821F, + 0xC78, 0x0FA0831F, + 0xC78, 0x0F90841F, + 0xC78, 0x0F80851F, + 0xC78, 0x0F70861F, + 0xC78, 0x0F60871F, + 0xC78, 0x0F50881F, + 0xC78, 0x0F40891F, + 0xC78, 0x0F308A1F, + 0xC78, 0x0F208B1F, + 0xC78, 0x0F108C1F, + 0xC78, 0x0F008D1F, + 0xC78, 0x0EF08E1F, + 0xC78, 0x0EE08F1F, + 0xC78, 0x0ED0901F, + 0xC78, 0x0EC0911F, + 0xC78, 0x0EB0921F, + 0xC78, 0x0EA0931F, + 0xC78, 0x0E90941F, + 0xC78, 0x0E80951F, + 0xC78, 0x0E70961F, + 0xC78, 0x0CB0971F, + 0xC78, 0x0CA0981F, + 0xC78, 0x0C90991F, + 0xC78, 0x0C809A1F, + 0xC78, 0x0C709B1F, + 0xC78, 0x0C609C1F, + 0xC78, 0x0C509D1F, + 0xC78, 0x0C409E1F, + 0xC78, 0x0C309F1F, + 0xC78, 0x0C20A01F, + 0xC78, 0x0C10A11F, + 0xC78, 0x0C00A21F, + 0xC78, 0x0A40A31F, + 0xC78, 0x0A30A41F, + 0xC78, 0x0A20A51F, + 0xC78, 0x0840A61F, + 0xC78, 0x0830A71F, + 0xC78, 0x0820A81F, + 0xC78, 0x0810A91F, + 0xC78, 0x0800AA1F, + 0xC78, 0x0640AB1F, + 0xC78, 0x0630AC1F, + 0xC78, 0x0620AD1F, + 0xC78, 0x0440AE1F, + 0xC78, 0x0430AF1F, + 0xC78, 0x0420B01F, + 0xC78, 0x0410B11F, + 0xC78, 0x0400B21F, + 0xC78, 0x0050B31F, + 0xC78, 0x0040B41F, + 0xC78, 0x0030B51F, + 0xC78, 0x0020B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0000B81F, + 0xC78, 0x0000B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340022, + 0xC50, 0x00340020, + 0xC58, 0x00000022, + 0xC58, 0x00000020, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0FD0801F, + 0xC78, 0x0FC0811F, + 0xC78, 0x0FB0821F, + 0xC78, 0x0FA0831F, + 0xC78, 0x0F90841F, + 0xC78, 0x0F80851F, + 0xC78, 0x0F70861F, + 0xC78, 0x0F60871F, + 0xC78, 0x0F50881F, + 0xC78, 0x0F40891F, + 0xC78, 0x0F308A1F, + 0xC78, 0x0B708B1F, + 0xC78, 0x0B608C1F, + 0xC78, 0x0B508D1F, + 0xC78, 0x0B408E1F, + 0xC78, 0x0B308F1F, + 0xC78, 0x0B20901F, + 0xC78, 0x0B10911F, + 0xC78, 0x0B00921F, + 0xC78, 0x0CF0931F, + 0xC78, 0x0CE0941F, + 0xC78, 0x0CD0951F, + 0xC78, 0x0CC0961F, + 0xC78, 0x0CB0971F, + 0xC78, 0x0CA0981F, + 0xC78, 0x0C90991F, + 0xC78, 0x0AD09A1F, + 0xC78, 0x0AC09B1F, + 0xC78, 0x0AB09C1F, + 0xC78, 0x0AA09D1F, + 0xC78, 0x0A909E1F, + 0xC78, 0x0A809F1F, + 0xC78, 0x0A70A01F, + 0xC78, 0x0890A11F, + 0xC78, 0x0880A21F, + 0xC78, 0x0870A31F, + 0xC78, 0x0860A41F, + 0xC78, 0x0850A51F, + 0xC78, 0x0840A61F, + 0xC78, 0x0830A71F, + 0xC78, 0x0820A81F, + 0xC78, 0x0810A91F, + 0xC78, 0x0800AA1F, + 0xC78, 0x0640AB1F, + 0xC78, 0x0630AC1F, + 0xC78, 0x0620AD1F, + 0xC78, 0x0440AE1F, + 0xC78, 0x0430AF1F, + 0xC78, 0x0420B01F, + 0xC78, 0x0410B11F, + 0xC78, 0x0400B21F, + 0xC78, 0x0050B31F, + 0xC78, 0x0040B41F, + 0xC78, 0x0030B51F, + 0xC78, 0x0020B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0000B81F, + 0xC78, 0x0000B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340022, + 0xC50, 0x00340020, + 0xC58, 0x00000022, + 0xC58, 0x00000020, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0FD0801F, + 0xC78, 0x0FC0811F, + 0xC78, 0x0FB0821F, + 0xC78, 0x0FA0831F, + 0xC78, 0x0F90841F, + 0xC78, 0x0F80851F, + 0xC78, 0x0F70861F, + 0xC78, 0x0F60871F, + 0xC78, 0x0F50881F, + 0xC78, 0x0F40891F, + 0xC78, 0x0D708A1F, + 0xC78, 0x0D608B1F, + 0xC78, 0x0D508C1F, + 0xC78, 0x0D408D1F, + 0xC78, 0x0D308E1F, + 0xC78, 0x0B708F1F, + 0xC78, 0x0B60901F, + 0xC78, 0x0B50911F, + 0xC78, 0x0B40921F, + 0xC78, 0x0B30931F, + 0xC78, 0x0B20941F, + 0xC78, 0x0B10951F, + 0xC78, 0x0B00961F, + 0xC78, 0x0AF0971F, + 0xC78, 0x0AE0981F, + 0xC78, 0x0AD0991F, + 0xC78, 0x0AC09A1F, + 0xC78, 0x0AB09B1F, + 0xC78, 0x0AA09C1F, + 0xC78, 0x0A909D1F, + 0xC78, 0x0A809E1F, + 0xC78, 0x0A709F1F, + 0xC78, 0x0A60A01F, + 0xC78, 0x0A50A11F, + 0xC78, 0x0A40A21F, + 0xC78, 0x0A30A31F, + 0xC78, 0x0A20A41F, + 0xC78, 0x0840A51F, + 0xC78, 0x0830A61F, + 0xC78, 0x0820A71F, + 0xC78, 0x0810A81F, + 0xC78, 0x0800A91F, + 0xC78, 0x0640AA1F, + 0xC78, 0x0630AB1F, + 0xC78, 0x0620AC1F, + 0xC78, 0x0450AD1F, + 0xC78, 0x0440AE1F, + 0xC78, 0x0430AF1F, + 0xC78, 0x0420B01F, + 0xC78, 0x0250B11F, + 0xC78, 0x0240B21F, + 0xC78, 0x0230B31F, + 0xC78, 0x0040B41F, + 0xC78, 0x0030B51F, + 0xC78, 0x0020B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0000B81F, + 0xC78, 0x0000B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340022, + 0xC50, 0x00340020, + 0xC58, 0x00000022, + 0xC58, 0x00000020, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0FD0801F, + 0xC78, 0x0FC0811F, + 0xC78, 0x0FB0821F, + 0xC78, 0x0FA0831F, + 0xC78, 0x0F90841F, + 0xC78, 0x0F80851F, + 0xC78, 0x0F70861F, + 0xC78, 0x0F60871F, + 0xC78, 0x0F50881F, + 0xC78, 0x0F40891F, + 0xC78, 0x0F308A1F, + 0xC78, 0x0F208B1F, + 0xC78, 0x0F108C1F, + 0xC78, 0x0F008D1F, + 0xC78, 0x0EF08E1F, + 0xC78, 0x0EE08F1F, + 0xC78, 0x0ED0901F, + 0xC78, 0x0EC0911F, + 0xC78, 0x0EB0921F, + 0xC78, 0x0EA0931F, + 0xC78, 0x0E90941F, + 0xC78, 0x0E80951F, + 0xC78, 0x0E70961F, + 0xC78, 0x0CB0971F, + 0xC78, 0x0CA0981F, + 0xC78, 0x0C90991F, + 0xC78, 0x0C809A1F, + 0xC78, 0x0C709B1F, + 0xC78, 0x0C609C1F, + 0xC78, 0x0C509D1F, + 0xC78, 0x0C409E1F, + 0xC78, 0x0C309F1F, + 0xC78, 0x0C20A01F, + 0xC78, 0x0C10A11F, + 0xC78, 0x0C00A21F, + 0xC78, 0x0A40A31F, + 0xC78, 0x0A30A41F, + 0xC78, 0x0A20A51F, + 0xC78, 0x0840A61F, + 0xC78, 0x0830A71F, + 0xC78, 0x0820A81F, + 0xC78, 0x0810A91F, + 0xC78, 0x0800AA1F, + 0xC78, 0x0640AB1F, + 0xC78, 0x0630AC1F, + 0xC78, 0x0620AD1F, + 0xC78, 0x0440AE1F, + 0xC78, 0x0430AF1F, + 0xC78, 0x0420B01F, + 0xC78, 0x0410B11F, + 0xC78, 0x0400B21F, + 0xC78, 0x0050B31F, + 0xC78, 0x0040B41F, + 0xC78, 0x0030B51F, + 0xC78, 0x0020B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0000B81F, + 0xC78, 0x0000B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340022, + 0xC50, 0x00340020, + 0xC58, 0x00000022, + 0xC58, 0x00000020, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F40801F, + 0xC78, 0x0F30811F, + 0xC78, 0x0F20821F, + 0xC78, 0x0F10831F, + 0xC78, 0x0F00841F, + 0xC78, 0x0D40851F, + 0xC78, 0x0D30861F, + 0xC78, 0x0D20871F, + 0xC78, 0x0980881F, + 0xC78, 0x0970891F, + 0xC78, 0x09608A1F, + 0xC78, 0x09508B1F, + 0xC78, 0x09408C1F, + 0xC78, 0x07808D1F, + 0xC78, 0x07708E1F, + 0xC78, 0x07608F1F, + 0xC78, 0x0750901F, + 0xC78, 0x0740911F, + 0xC78, 0x0730921F, + 0xC78, 0x0580931F, + 0xC78, 0x0570941F, + 0xC78, 0x0560951F, + 0xC78, 0x0550961F, + 0xC78, 0x0540971F, + 0xC78, 0x0530981F, + 0xC78, 0x0520991F, + 0xC78, 0x05109A1F, + 0xC78, 0x05009B1F, + 0xC78, 0x04F09C1F, + 0xC78, 0x04E09D1F, + 0xC78, 0x04D09E1F, + 0xC78, 0x04C09F1F, + 0xC78, 0x04B0A01F, + 0xC78, 0x04A0A11F, + 0xC78, 0x0490A21F, + 0xC78, 0x0480A31F, + 0xC78, 0x0470A41F, + 0xC78, 0x0460A51F, + 0xC78, 0x0450A61F, + 0xC78, 0x0440A71F, + 0xC78, 0x0430A81F, + 0xC78, 0x0270A91F, + 0xC78, 0x0260AA1F, + 0xC78, 0x0250AB1F, + 0xC78, 0x0240AC1F, + 0xC78, 0x0230AD1F, + 0xC78, 0x0220AE1F, + 0xC78, 0x0210AF1F, + 0xC78, 0x0050B01F, + 0xC78, 0x0040B11F, + 0xC78, 0x0030B21F, + 0xC78, 0x0020B31F, + 0xC78, 0x0010B41F, + 0xC78, 0x0010B51F, + 0xC78, 0x0010B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0010B81F, + 0xC78, 0x0010B91F, + 0xC78, 0x0010BA1F, + 0xC78, 0x0010BB1F, + 0xC78, 0x0010BC1F, + 0xC78, 0x0010BD1F, + 0xC78, 0x0010BE1F, + 0xC78, 0x0010BF1F, + 0xC50, 0x00340222, + 0xC50, 0x00340220, + 0xC58, 0x00000222, + 0xC58, 0x00000220, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x0F40801F, + 0xC78, 0x0F30811F, + 0xC78, 0x0F20821F, + 0xC78, 0x0F10831F, + 0xC78, 0x0F00841F, + 0xC78, 0x0D40851F, + 0xC78, 0x0D30861F, + 0xC78, 0x0D20871F, + 0xC78, 0x0980881F, + 0xC78, 0x0970891F, + 0xC78, 0x09608A1F, + 0xC78, 0x09508B1F, + 0xC78, 0x09408C1F, + 0xC78, 0x07808D1F, + 0xC78, 0x07708E1F, + 0xC78, 0x07608F1F, + 0xC78, 0x0750901F, + 0xC78, 0x0740911F, + 0xC78, 0x0730921F, + 0xC78, 0x0580931F, + 0xC78, 0x0570941F, + 0xC78, 0x0560951F, + 0xC78, 0x0550961F, + 0xC78, 0x0540971F, + 0xC78, 0x0530981F, + 0xC78, 0x0520991F, + 0xC78, 0x05109A1F, + 0xC78, 0x05009B1F, + 0xC78, 0x04F09C1F, + 0xC78, 0x04E09D1F, + 0xC78, 0x04D09E1F, + 0xC78, 0x04C09F1F, + 0xC78, 0x04B0A01F, + 0xC78, 0x04A0A11F, + 0xC78, 0x0490A21F, + 0xC78, 0x0480A31F, + 0xC78, 0x0470A41F, + 0xC78, 0x0460A51F, + 0xC78, 0x0450A61F, + 0xC78, 0x0440A71F, + 0xC78, 0x0430A81F, + 0xC78, 0x0270A91F, + 0xC78, 0x0260AA1F, + 0xC78, 0x0250AB1F, + 0xC78, 0x0240AC1F, + 0xC78, 0x0230AD1F, + 0xC78, 0x0220AE1F, + 0xC78, 0x0210AF1F, + 0xC78, 0x0050B01F, + 0xC78, 0x0040B11F, + 0xC78, 0x0030B21F, + 0xC78, 0x0020B31F, + 0xC78, 0x0010B41F, + 0xC78, 0x0010B51F, + 0xC78, 0x0010B61F, + 0xC78, 0x0010B71F, + 0xC78, 0x0010B81F, + 0xC78, 0x0010B91F, + 0xC78, 0x0010BA1F, + 0xC78, 0x0010BB1F, + 0xC78, 0x0010BC1F, + 0xC78, 0x0010BD1F, + 0xC78, 0x0010BE1F, + 0xC78, 0x0010BF1F, + 0xC50, 0x00340222, + 0xC50, 0x00340220, + 0xC58, 0x00000222, + 0xC58, 0x00000220, + 0xA0000000, 0x00000000, + 0xC78, 0x0FE0801F, + 0xC78, 0x0FD0811F, + 0xC78, 0x0FC0821F, + 0xC78, 0x0FB0831F, + 0xC78, 0x0FA0841F, + 0xC78, 0x0F90851F, + 0xC78, 0x0F80861F, + 0xC78, 0x0F70871F, + 0xC78, 0x0F60881F, + 0xC78, 0x0F50891F, + 0xC78, 0x0F408A1F, + 0xC78, 0x0D708B1F, + 0xC78, 0x0D608C1F, + 0xC78, 0x0D508D1F, + 0xC78, 0x0D408E1F, + 0xC78, 0x0D308F1F, + 0xC78, 0x0B70901F, + 0xC78, 0x0B60911F, + 0xC78, 0x0B50921F, + 0xC78, 0x0B40931F, + 0xC78, 0x0B30941F, + 0xC78, 0x0B20951F, + 0xC78, 0x0B10961F, + 0xC78, 0x0B00971F, + 0xC78, 0x0AF0981F, + 0xC78, 0x0AE0991F, + 0xC78, 0x0AD09A1F, + 0xC78, 0x0AC09B1F, + 0xC78, 0x0AB09C1F, + 0xC78, 0x0AA09D1F, + 0xC78, 0x0A909E1F, + 0xC78, 0x0A809F1F, + 0xC78, 0x0A70A01F, + 0xC78, 0x0A60A11F, + 0xC78, 0x0A50A21F, + 0xC78, 0x0A40A31F, + 0xC78, 0x0A30A41F, + 0xC78, 0x0860A51F, + 0xC78, 0x0850A61F, + 0xC78, 0x0840A71F, + 0xC78, 0x0670A81F, + 0xC78, 0x0660A91F, + 0xC78, 0x0650AA1F, + 0xC78, 0x0640AB1F, + 0xC78, 0x0470AC1F, + 0xC78, 0x0460AD1F, + 0xC78, 0x0450AE1F, + 0xC78, 0x0290AF1F, + 0xC78, 0x0280B01F, + 0xC78, 0x0270B11F, + 0xC78, 0x0260B21F, + 0xC78, 0x0250B31F, + 0xC78, 0x0060B41F, + 0xC78, 0x0050B51F, + 0xC78, 0x0040B61F, + 0xC78, 0x0030B71F, + 0xC78, 0x0020B81F, + 0xC78, 0x0010B91F, + 0xC78, 0x0000BA1F, + 0xC78, 0x0000BB1F, + 0xC78, 0x0000BC1F, + 0xC78, 0x0000BD1F, + 0xC78, 0x0000BE1F, + 0xC78, 0x0000BF1F, + 0xC50, 0x00340022, + 0xC50, 0x00340020, + 0xC58, 0x00000022, + 0xC58, 0x00000020, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8197F_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8197F_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8197F_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8197F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8197F_AGC_TAB(void) +{ + return 66; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8197F_PHY_REG[] = { + 0x800, 0x83005308, + 0x804, 0x00004001, + 0x808, 0x0000FC00, + 0x80C, 0x00000000, + 0x810, 0x22000322, + 0x814, 0x020C3D10, + 0x818, 0x00000385, + 0x81C, 0x07000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x01000100, + 0x82C, 0x00390204, + 0x830, 0x00000000, + 0x834, 0x00690200, + 0x838, 0x00000004, + 0x83C, 0x00690200, + 0x840, 0x00010000, + 0x844, 0x00010000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00031FE0, + 0x854, 0x00000000, + 0x858, 0x569A569A, + 0x85C, 0x00400040, + 0x860, 0x66F60000, + 0x864, 0x061F0000, + 0x868, 0x0F7F0130, + 0x86C, 0x0F7F0130, + 0x870, 0x00000300, + 0x874, 0x04003400, + 0x878, 0x08080808, + 0x87C, 0x004F0201, + 0x880, 0xD8001402, + 0x884, 0xC0000120, + 0x888, 0x00000000, + 0x88C, 0xCC0000C0, + 0x890, 0x00000000, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x8A0, 0x00000000, + 0x8A4, 0x00000000, + 0x8A8, 0x00000109, + 0x8AC, 0x00000000, + 0x8B0, 0x00000000, + 0x8B4, 0x00000000, + 0x8B8, 0x00000000, + 0x8BC, 0x00000000, + 0x8C0, 0x03910C40, + 0x8C4, 0x00000000, + 0x8C8, 0x00000000, + 0x8CC, 0x00000000, + 0x8D0, 0x00000000, + 0x8D4, 0x00000000, + 0x8D8, 0x00000000, + 0x8DC, 0x00000000, + 0x8E0, 0x02000200, + 0x8E4, 0x00000000, + 0x8E8, 0xD8080000, + 0x8EC, 0x00000000, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000F00, + 0x90C, 0x81121313, + 0x910, 0x024C0000, + 0x914, 0x00000000, + 0x918, 0x00000000, + 0x91C, 0x00000000, + 0x920, 0x00000000, + 0x924, 0x00000000, + 0x928, 0x00000000, + 0x92C, 0x00000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFFFFFF, + 0x934, 0xFFFFF2F5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF5F2F, + 0x940, 0xFF44FFFF, + 0x944, 0x3F3F0F00, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0x88000000, + 0x934, 0x00000245, + 0x938, 0x00024588, + 0x93C, 0x00000000, + 0x940, 0x000007FF, + 0x944, 0x3F3F0000, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0x88000000, + 0x934, 0x00000245, + 0x938, 0x00024588, + 0x93C, 0x00000000, + 0x940, 0x000007FF, + 0x944, 0x3F3F0000, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFFFFFF, + 0x934, 0xFFFFF2F5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF5F2F, + 0x940, 0xFF44FFFF, + 0x944, 0x3F3F0F00, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0x88000000, + 0x934, 0x00000245, + 0x938, 0x00024588, + 0x93C, 0x00000000, + 0x940, 0x000007FF, + 0x944, 0x3F3F0000, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0x88000000, + 0x934, 0x00000245, + 0x938, 0x00024588, + 0x93C, 0x00000000, + 0x940, 0x000007FF, + 0x944, 0x3F3F0000, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x930, 0xFFFF02FF, + 0x934, 0xFFFFFFF5, + 0x938, 0xFFFFFFFF, + 0x93C, 0xFFFF502F, + 0x940, 0xFF54FF0F, + 0x944, 0x3F3F0F0C, + 0xA0000000, 0x00000000, + 0x930, 0x88000000, + 0x934, 0x00000245, + 0x938, 0x00024588, + 0x93C, 0x00000000, + 0x940, 0x000007FF, + 0x944, 0x3F3F0000, + 0xB0000000, 0x00000000, + 0x948, 0x000001A3, + 0x94C, 0x20200008, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338397, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338897, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338797, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0x00338497, + 0xA0000000, 0x00000000, + 0x950, 0x00338797, + 0xB0000000, 0x00000000, + 0x954, 0x00000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC6D87A, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC8D87A, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC8D87A, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x958, 0x4BC5D87A, + 0xA0000000, 0x00000000, + 0x958, 0x4BC7D87A, + 0xB0000000, 0x00000000, + 0x95C, 0x06EB9B79, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000003, + 0x970, 0x00000000, + 0x974, 0x00000000, + 0x978, 0x00000000, + 0x97C, 0x10030000, + 0x980, 0x00000000, + 0x984, 0x00050050, + 0x988, 0x020A5704, + 0x98C, 0x1461C826, + 0x990, 0x0001469E, + 0x994, 0x008858D1, + 0x998, 0x70049489, + 0x99C, 0x77777777, + 0x9A0, 0x00000000, + 0x9A4, 0x00000000, + 0x9A8, 0x00000000, + 0x9AC, 0x00020000, + 0x9B0, 0x00000000, + 0x9B4, 0x00000000, + 0x9B8, 0x00000000, + 0x9BC, 0x00000000, + 0x9C0, 0x00000011, + 0x9C4, 0x00000000, + 0x9C8, 0x00000000, + 0x9CC, 0x00000000, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E0, 0x00000000, + 0x9E4, 0x00000000, + 0x9E8, 0x00000000, + 0x9EC, 0x00000000, + 0x9F0, 0x80000000, + 0x9F4, 0x00000000, + 0x9F8, 0x00000000, + 0xA00, 0x00D046C8, + 0xA04, 0x80FF800C, + 0xA08, 0x9C838300, + 0xA0C, 0x297E000F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xE82C0001, + 0xA24, 0x64B80C1C, + 0xA28, 0x00008810, + 0xA2C, 0x00920000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000107, + 0xA78, 0x00008900, + 0xA7C, 0x225B0606, + 0xA80, 0x21807532, + 0xA84, 0x00110000, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x00000000, + 0xA9C, 0x3F000000, + 0xAA0, 0x00000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xAA4, 0x00010010, + 0xA0000000, 0x00000000, + 0xAA4, 0x00010010, + 0xB0000000, 0x00000000, + 0xAA8, 0xEAEF0004, + 0xAAC, 0x01235667, + 0xAB0, 0x00000000, + 0xAB4, 0x00201402, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0D2E2EA, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0D2E2EA, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xACC0D2E0, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xACC0D2E0, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C6D8E6, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xACC0D2E0, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C6D8E6, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C8DAE2, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C8DAE2, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C8DAE2, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xC0C8DAE2, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xD0E2F0F8, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xD0E2F0F8, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xCCDCEEF8, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xCCDCEEF8, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xCCDCEEF8, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xCEE0F0F8, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xCEE0F0F8, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xACC0D2E0, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xABC, 0xACC0D2E0, + 0xA0000000, 0x00000000, + 0xABC, 0xD2E2F2FA, + 0xB0000000, 0x00000000, + 0xB00, 0x00000000, + 0xB04, 0x00000000, + 0xB08, 0x00000000, + 0xB0C, 0x00000000, + 0xB10, 0x00000000, + 0xB14, 0x00000000, + 0xB18, 0x00000000, + 0xB1C, 0x00000000, + 0xB20, 0x00000000, + 0xB24, 0x00000000, + 0xB28, 0x00000000, + 0xB2C, 0x00000000, + 0xB30, 0x20000000, + 0xB34, 0x00000000, + 0xB38, 0x00000000, + 0xB3C, 0x00000000, + 0xB40, 0x00000000, + 0xB44, 0x00000000, + 0xB48, 0x00000000, + 0xB4C, 0x00000000, + 0xB50, 0x00000000, + 0xB54, 0x00000000, + 0xB58, 0x00000000, + 0xB5C, 0x00000000, + 0xB60, 0x00000000, + 0xB64, 0x00000000, + 0xB68, 0x80000000, + 0xB6C, 0x80000000, + 0xB70, 0x00000000, + 0xB74, 0x00000000, + 0xB78, 0x00000000, + 0xB7C, 0x00000000, + 0xB80, 0x00000000, + 0xB84, 0x00000000, + 0xB88, 0x00000000, + 0xB8C, 0x00000000, + 0xB90, 0x00000000, + 0xB94, 0x00000000, + 0xB98, 0x00000000, + 0xB9C, 0x00000000, + 0xBA0, 0x00000000, + 0xBA4, 0x00000000, + 0xBA8, 0x00000000, + 0xBAC, 0x00000000, + 0xBB0, 0x00440000, + 0xBB4, 0x00000000, + 0xBB8, 0x00000000, + 0xBBC, 0x00000000, + 0xBD0, 0x00000000, + 0xBD4, 0x00000000, + 0xBDC, 0x02000000, + 0xBE0, 0x02000000, + 0xBE4, 0x02000000, + 0xBE8, 0x02000000, + 0xBEC, 0x02000000, + 0xBF0, 0x02000000, + 0xBF4, 0x02000000, + 0xBF8, 0x02000000, + 0xC00, 0x00000080, + 0xC04, 0x6F005433, + 0xC08, 0x000004E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x22000000, + 0xC14, 0x40000100, + 0xC18, 0x22000000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x40000100, + 0xC28, 0x00000000, + 0xC2C, 0x40000100, + 0xC30, 0x0401A807, + 0xC34, 0x30000020, + 0xC38, 0x23808080, + 0xC3C, 0x00002FD4, + 0xC40, 0x1CF8403F, + 0xC44, 0x000100C7, + 0xC48, 0xEC060106, + 0xC4C, 0x007F037F, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340020, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340020, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340020, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340020, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00340220, + 0xA0000000, 0x00000000, + 0xC50, 0x00340020, + 0xB0000000, 0x00000000, + 0xC54, 0x04008017, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000020, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000020, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000020, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000020, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00000220, + 0xA0000000, 0x00000000, + 0xC58, 0x00000020, + 0xB0000000, 0x00000000, + 0xC5C, 0x00708492, + 0xC60, 0x002E0200, + 0xC64, 0x5012838B, + 0xC68, 0x47C006C7, + 0xC6C, 0x00000035, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020155A7, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020155A7, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00001007, + 0xC74, 0x020251E9, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00001007, + 0xC74, 0x020251E9, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020151A9, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020151A9, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020151A7, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00001007, + 0xC74, 0x020251A9, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00001007, + 0xC74, 0x020251A9, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC70, 0x00000007, + 0xC74, 0x020251A7, + 0xA0000000, 0x00000000, + 0xC70, 0x00001007, + 0xC74, 0x020251A9, + 0xB0000000, 0x00000000, + 0xC78, 0x0FE07F1F, + 0xC7C, 0x00B91612, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x24000090, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x40000100, + 0xA0000000, 0x00000000, + 0xC80, 0x40000100, + 0xB0000000, 0x00000000, + 0xC84, 0x32000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x24000090, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0xC88, 0x40000100, + 0xA0000000, 0x00000000, + 0xC88, 0x40000100, + 0xB0000000, 0x00000000, + 0xC8C, 0xA0240000, + 0xC90, 0x40000100, + 0xC94, 0x00000000, + 0xC98, 0x40000100, + 0xC9C, 0x0000BDC8, + 0xCA0, 0x00000000, + 0xCA4, 0x098300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00F5FB1A, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28100200, + 0xCC0, 0x0010A3D0, + 0xCC4, 0x00000F7D, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x40201001, + 0xCE4, 0x00000000, + 0xCE8, 0x40E04407, + 0xCEC, 0x2E572000, + 0xCF0, 0x00000000, + 0xCF4, 0x00000000, + 0xCF8, 0x00000000, + 0xD00, 0x000B0680, + 0xD04, 0xC0020403, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0x06288888, + 0xD14, 0x8888366B, + 0xD18, 0x7D806DB3, + 0xD1C, 0x0000007F, + 0xD20, 0x167401B8, + 0xD24, 0x0000018B, + 0xD28, 0xD513FF7D, + 0xD2C, 0xCC979975, + 0xD30, 0x00008000, + 0xD34, 0x40608000, + 0xD38, 0xA8000000, + 0xD3C, 0x00026EE2, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x20500000, + 0xD58, 0x16161616, + 0xD5C, 0x70320064, + 0xD60, 0x4653DE60, + 0xD64, 0x7E718A3C, + 0xD68, 0x00000103, + 0xD6C, 0x00000000, + 0xD70, 0x00000000, + 0xD74, 0x00000000, + 0xD78, 0x00000000, + 0xD7C, 0x00000000, + 0xD80, 0x00000000, + 0xD84, 0x31310000, + 0xD88, 0xF5B50000, + 0xD8C, 0x00000000, + 0xD90, 0x00000000, + 0xD94, 0x44BBBB44, + 0xD98, 0x44BB44FF, + 0xD9C, 0x06033688, + 0xDA0, 0x00000002, + 0xDA4, 0x00000000, + 0xDA8, 0x00000000, + 0xDAC, 0x00000000, + 0xDB0, 0x00000000, + 0xDB4, 0x00000000, + 0xDB8, 0x00000000, + 0xDBC, 0x00000000, + 0xDC0, 0x00000000, + 0xDC4, 0x00210000, + 0xDC8, 0x00000200, + 0xDCC, 0x0000000F, + 0xDD0, 0x00000020, + 0xDD4, 0x00007F7F, + 0xDD8, 0xE5AF1854, + 0xDDC, 0x000040AB, + 0xDE0, 0x00000000, + 0xDE4, 0x00000000, + 0xDE8, 0x0002030B, + 0xDEC, 0x0000A987, + 0xDF0, 0x00005807, + 0xDF4, 0x00000000, + 0xDF8, 0x00000005, + 0xE00, 0x00000000, + 0xE04, 0x00000000, + 0xE08, 0x00000000, + 0xE0C, 0x000000FF, + 0xE10, 0x00000000, + 0xE14, 0x00000000, + 0xE18, 0x00000000, + 0xE1C, 0x00000000, + 0xE20, 0x00000000, + 0xE24, 0x00200000, + 0xE28, 0x00000000, + 0xE2C, 0x00000000, + 0xE30, 0x01007C00, + 0xE34, 0x01004800, + 0xE38, 0x10008C0F, + 0xE3C, 0x3C008C0F, + 0xE40, 0x01007C00, + 0xE44, 0x00000000, + 0xE48, 0x00000000, + 0xE4C, 0x00000000, + 0xE50, 0x01007C00, + 0xE54, 0x01004800, + 0xE58, 0x10008C0F, + 0xE5C, 0x3C008C0F, + 0xE60, 0x02100000, + 0xE64, 0xBBBBBBBB, + 0xE68, 0x40404040, + 0xE6C, 0x80408040, + 0xE70, 0x80408040, + 0xE74, 0x40404040, + 0xE78, 0x00400040, + 0xE7C, 0x40404040, + 0xE80, 0x00FF0000, + 0xE84, 0x80408040, + 0xE88, 0x40404040, + 0xE8C, 0x80408040, + 0xE90, 0x00000000, + 0xE94, 0x01000000, + 0xE98, 0x00000000, + 0xE9C, 0x00000000, + 0xEA0, 0x00000000, + 0xEA4, 0x01000000, + 0xEA8, 0x00000000, + 0xEAC, 0x00000000, + 0xEB0, 0x00000000, + 0xEB4, 0x01000000, + 0xEB8, 0x00000000, + 0xEBC, 0x00000000, + 0xEC0, 0x00000000, + 0xEC4, 0x01000000, + 0xEC8, 0x00000000, + 0xECC, 0x00000000, + 0xED0, 0x80408040, + 0xED4, 0x80408040, + 0xED8, 0x80408040, + 0xEDC, 0xC040C040, + 0xEE0, 0xC040C040, + 0xEE4, 0x00400040, + 0xEE8, 0xD8001402, + 0xEEC, 0xC0000120, + 0xEF0, 0x02000B09, + 0xEF4, 0x00000001, + 0xEF8, 0x00000000, + 0xF00, 0x00000300, + 0xF04, 0x00000000, + 0xF08, 0x0002030B, + 0xF0C, 0x0000A987, + 0xF10, 0x00005807, + 0xF14, 0x00000003, + 0xF18, 0x00020002, + 0xF1C, 0x8000001F, + 0xF20, 0x00000000, + 0xF24, 0x00000000, + 0xF28, 0x00000000, + 0xF2C, 0x00000000, + 0xF30, 0x00000000, + 0xF34, 0x00000000, + 0xF38, 0x00030155, + 0xF3C, 0x0000003A, + 0xF40, 0x00000000, + 0xF44, 0x00000000, + 0xF48, 0x00030000, + 0xF4C, 0x13000000, + 0xF50, 0x00000010, + 0xF54, 0x00000000, + 0xF58, 0x00000000, + 0xF5C, 0x00000000, + 0xF60, 0x00000000, + 0xF64, 0x00000000, + 0xF68, 0x00000000, + 0xF6C, 0x00000000, + 0xF70, 0x00000000, + 0xF74, 0x00000000, + 0xF78, 0x00000000, + 0xF7C, 0x00000000, + 0xF80, 0x00000000, + 0xF84, 0x00000000, + 0xF88, 0x00000000, + 0xF8C, 0x00000000, + 0xF90, 0x00000002, + 0xF94, 0x00000000, + 0xF98, 0x00000000, + 0xF9C, 0x00000000, + 0xFA0, 0x00000000, + 0xFA4, 0x0002030B, + 0xFA8, 0x0000A987, + 0xFAC, 0x00005807, + 0xFB0, 0x00000000, + 0xFB4, 0x00000000, + 0xFB8, 0x00000000, + 0xFBC, 0x00000000, + 0xFC0, 0x00C02001, + 0xFC4, 0x90063000, + 0xFC8, 0x00000018, + 0xFCC, 0x10003005, + 0xFD0, 0x0000E5AF, + 0xFD4, 0x00000000, + 0xFD8, 0x00000000, + 0xFDC, 0x00000000, + 0xFE0, 0x00000000, + 0xFE4, 0x00000000, + 0xFE8, 0x00000000, + 0xFEC, 0x00000000, + 0xFF0, 0x00000000, + 0xFF4, 0x00000000, + 0xFF8, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8197F_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8197F_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8197F_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8197F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8197F_PHY_REG(void) +{ + return 66; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.h b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.h index b25e2475a7e..88bfe2a673a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_bb.h @@ -1,44 +1,44 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8197F_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8197F_H -#define __INC_MP_BB_HW_IMG_8197F_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_PHY_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8197F_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8197F_H +#define __INC_MP_BB_HW_IMG_8197F_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_PHY_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.c b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.c index 5e98bb651ef..cf96dadc6d6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.c @@ -1,316 +1,316 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8197F_MAC_REG[] = { - 0x020, 0x000000BD, - 0x021, 0x0000001D, - 0x004, 0x00000012, - 0x007, 0x00000014, - 0x000, 0x00000092, - 0x001, 0x000000B2, - 0x80001002, 0x00000000, 0x40000000, 0x00000000, - 0x024, 0x0000005F, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x024, 0x0000005F, - 0xA0000000, 0x00000000, - 0x024, 0x0000003B, - 0xB0000000, 0x00000000, - 0x078, 0x000000FB, - 0x079, 0x00000002, - 0x07A, 0x00000000, - 0x07B, 0x00000007, - 0x420, 0x00000080, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x000000F0, - 0x446, 0x00000001, - 0x447, 0x000000FE, - 0x448, 0x00000000, - 0x449, 0x00000000, - 0x44A, 0x00000000, - 0x44B, 0x00000040, - 0x44C, 0x00000010, - 0x44D, 0x000000F0, - 0x44E, 0x0000003F, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x00000000, - 0x452, 0x00000000, - 0x453, 0x00000040, - 0x455, 0x00000070, - 0x45E, 0x00000004, - 0x49C, 0x00000010, - 0x49D, 0x000000F0, - 0x49E, 0x00000000, - 0x49F, 0x00000006, - 0x4A0, 0x000000E0, - 0x4A1, 0x00000003, - 0x4A2, 0x00000000, - 0x4A3, 0x00000040, - 0x4A4, 0x00000015, - 0x4A5, 0x000000F0, - 0x4A6, 0x00000000, - 0x4A7, 0x00000006, - 0x4A8, 0x000000E0, - 0x4A9, 0x00000000, - 0x4AA, 0x00000000, - 0x4AB, 0x00000000, - 0x7DA, 0x00000008, - 0x1448, 0x00000006, - 0x144A, 0x00000006, - 0x144C, 0x00000006, - 0x144E, 0x00000006, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CA, 0x00000010, - 0x4CB, 0x00000010, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4CF, 0x00000008, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x521, 0x0000002F, - 0x525, 0x0000004F, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x577, 0x0000000B, - 0x5BE, 0x00000064, - 0x604, 0x00000001, - 0x605, 0x00000030, - 0x607, 0x00000005, - 0x608, 0x0000000E, - 0x609, 0x00000022, - 0x60C, 0x00000018, - 0x6A0, 0x000000FF, - 0x6A1, 0x000000FF, - 0x6A2, 0x000000FF, - 0x6A3, 0x000000FF, - 0x6A4, 0x000000FF, - 0x6A5, 0x000000FF, - 0x6DE, 0x00000084, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x718, 0x00000040, - -}; - -void -ODM_ReadAndConfig_MP_8197F_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8197F_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8197F_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8197F(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8197F_MAC_REG(void) -{ - return 66; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8197F_MAC_REG[] = { + 0x020, 0x000000BD, + 0x021, 0x0000001D, + 0x004, 0x00000012, + 0x007, 0x00000014, + 0x000, 0x00000092, + 0x001, 0x000000B2, + 0x80001002, 0x00000000, 0x40000000, 0x00000000, + 0x024, 0x0000005F, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x024, 0x0000005F, + 0xA0000000, 0x00000000, + 0x024, 0x0000003B, + 0xB0000000, 0x00000000, + 0x078, 0x000000FB, + 0x079, 0x00000002, + 0x07A, 0x00000000, + 0x07B, 0x00000007, + 0x420, 0x00000080, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x000000F0, + 0x446, 0x00000001, + 0x447, 0x000000FE, + 0x448, 0x00000000, + 0x449, 0x00000000, + 0x44A, 0x00000000, + 0x44B, 0x00000040, + 0x44C, 0x00000010, + 0x44D, 0x000000F0, + 0x44E, 0x0000003F, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x00000000, + 0x452, 0x00000000, + 0x453, 0x00000040, + 0x455, 0x00000070, + 0x45E, 0x00000004, + 0x49C, 0x00000010, + 0x49D, 0x000000F0, + 0x49E, 0x00000000, + 0x49F, 0x00000006, + 0x4A0, 0x000000E0, + 0x4A1, 0x00000003, + 0x4A2, 0x00000000, + 0x4A3, 0x00000040, + 0x4A4, 0x00000015, + 0x4A5, 0x000000F0, + 0x4A6, 0x00000000, + 0x4A7, 0x00000006, + 0x4A8, 0x000000E0, + 0x4A9, 0x00000000, + 0x4AA, 0x00000000, + 0x4AB, 0x00000000, + 0x7DA, 0x00000008, + 0x1448, 0x00000006, + 0x144A, 0x00000006, + 0x144C, 0x00000006, + 0x144E, 0x00000006, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CA, 0x00000010, + 0x4CB, 0x00000010, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4CF, 0x00000008, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x521, 0x0000002F, + 0x525, 0x0000004F, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x577, 0x0000000B, + 0x5BE, 0x00000064, + 0x604, 0x00000001, + 0x605, 0x00000030, + 0x607, 0x00000005, + 0x608, 0x0000000E, + 0x609, 0x00000022, + 0x60C, 0x00000018, + 0x6A0, 0x000000FF, + 0x6A1, 0x000000FF, + 0x6A2, 0x000000FF, + 0x6A3, 0x000000FF, + 0x6A4, 0x000000FF, + 0x6A5, 0x000000FF, + 0x6DE, 0x00000084, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + +}; + +void +ODM_ReadAndConfig_MP_8197F_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8197F_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8197F_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8197F(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8197F_MAC_REG(void) +{ + return 66; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.h b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.h index 0f335af817b..ae6e41de36d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_mac.h @@ -1,34 +1,34 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8197F_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8197F_H -#define __INC_MP_MAC_HW_IMG_8197F_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8197F_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8197F_H +#define __INC_MP_MAC_HW_IMG_8197F_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.c b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.c index 454fd81f020..323f8804717 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.c @@ -1,1733 +1,1733 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8197F_RadioA[] = { - 0x000, 0x00030000, - 0x018, 0x00000C07, - 0x0CA, 0x00002000, - 0x081, 0x0000FC00, - 0x082, 0x000003C0, - 0x084, 0x00000005, - 0x086, 0x000933A5, - 0x087, 0x00000000, - 0x088, 0x0007B030, - 0x08E, 0x00064540, - 0x08F, 0x000A8000, - 0x0DF, 0x00000E00, - 0x051, 0x00000C1C, - 0x052, 0x0009A007, - 0x053, 0x00018C47, - 0x054, 0x00090034, - 0x055, 0x00082000, - 0x056, 0x0000880F, - 0x057, 0x0007F000, - 0x058, 0x000603F0, - 0x05A, 0x00050000, - 0x05B, 0x00000006, - 0x05C, 0x00000015, - 0x065, 0x00020000, - 0x06E, 0x00038319, - 0x0DF, 0x00000602, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030026, - 0x033, 0x00038026, - 0x033, 0x00070026, - 0x033, 0x00078026, - 0x033, 0x000D8022, - 0x0EF, 0x00000000, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x0C9, 0x00000600, - 0x0B0, 0x000FFBC3, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B87, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B87, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B87, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B87, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0B1, 0x00033B8F, - 0xA0000000, 0x00000000, - 0x0B1, 0x00033B87, - 0xB0000000, 0x00000000, - 0x0B2, 0x00033762, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000140F0, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000140F0, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000140F0, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000140F0, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0B4, 0x000141F0, - 0xA0000000, 0x00000000, - 0x0B4, 0x000140F0, - 0xB0000000, 0x00000000, - 0x0B5, 0x00014000, - 0x0B6, 0x00012425, - 0x0B7, 0x00010E8C, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00030FFF, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00030FFF, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00030FFF, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00030FFF, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0B8, 0x00070FFF, - 0xA0000000, 0x00000000, - 0x0B8, 0x00030FFF, - 0xB0000000, 0x00000000, - 0x0B9, 0x000C0008, - 0x0BA, 0x00040005, - 0x0C2, 0x00002C01, - 0x0C3, 0x0000000B, - 0x0C4, 0x00081E2F, - 0x0C5, 0x0005C28F, - 0x0C6, 0x000000A0, - 0x0C9, 0x00000600, - 0x0CA, 0x00002000, - 0xFFE, 0x00000000, - 0x018, 0x00008C07, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x000, 0x00035DF5, - -}; - -void -ODM_ReadAndConfig_MP_8197F_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8197F_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8197F_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8197F(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8197F_RadioA(void) -{ - return 66; -} - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -u4Byte Array_MP_8197F_RadioB[] = { - 0x000, 0x00030000, - 0x081, 0x0000FC00, - 0x082, 0x000003C0, - 0x084, 0x00000005, - 0x086, 0x000933A5, - 0x087, 0x00000000, - 0x088, 0x0007B030, - 0x08E, 0x00064540, - 0x08F, 0x000A8000, - 0x0DF, 0x00000E00, - 0x051, 0x00000C18, - 0x052, 0x0009A007, - 0x053, 0x00018C4B, - 0x054, 0x00090030, - 0x055, 0x00082000, - 0x056, 0x0000880F, - 0x057, 0x0007F000, - 0x058, 0x000603F0, - 0x05A, 0x00050000, - 0x05B, 0x00000006, - 0x05C, 0x00000015, - 0x065, 0x00020000, - 0x06E, 0x00038319, - 0x0DF, 0x00000602, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000121, - 0x033, 0x00004123, - 0x033, 0x00008126, - 0x033, 0x0000C129, - 0x033, 0x0001012C, - 0x033, 0x0001414C, - 0x033, 0x0001816C, - 0x033, 0x0001C16F, - 0x033, 0x000201AE, - 0x033, 0x000245AC, - 0x033, 0x00028DAB, - 0x0EF, 0x00000000, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x000000A5, - 0x033, 0x000040A8, - 0x033, 0x000080E8, - 0x033, 0x0000C4E6, - 0x033, 0x00010DE5, - 0x033, 0x00014DE8, - 0x033, 0x00018DEB, - 0x033, 0x0001CDEE, - 0x033, 0x00020DF1, - 0x033, 0x00024DF4, - 0x033, 0x00028DF7, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80001001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f001, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x9000f004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002006, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90001002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x9000f003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0x90001007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0x90002007, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00002000, - 0x033, 0x0006000D, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00020000, - 0x033, 0x00030021, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x000, 0x00035DF5, - -}; - -void -ODM_ReadAndConfig_MP_8197F_RadioB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8197F_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8197F_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioB_8197F(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8197F_RadioB(void) -{ - return 66; -} - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type0.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type0( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type1.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type1( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type2.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type2( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type3.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type3( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type4.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type4( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type5.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type5( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type6.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type6( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type7.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type7( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8197F_RadioA[] = { + 0x000, 0x00030000, + 0x018, 0x00000C07, + 0x0CA, 0x00002000, + 0x081, 0x0000FC00, + 0x082, 0x000003C0, + 0x084, 0x00000005, + 0x086, 0x000933A5, + 0x087, 0x00000000, + 0x088, 0x0007B030, + 0x08E, 0x00064540, + 0x08F, 0x000A8000, + 0x0DF, 0x00000E00, + 0x051, 0x00000C1C, + 0x052, 0x0009A007, + 0x053, 0x00018C47, + 0x054, 0x00090034, + 0x055, 0x00082000, + 0x056, 0x0000880F, + 0x057, 0x0007F000, + 0x058, 0x000603F0, + 0x05A, 0x00050000, + 0x05B, 0x00000006, + 0x05C, 0x00000015, + 0x065, 0x00020000, + 0x06E, 0x00038319, + 0x0DF, 0x00000602, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030026, + 0x033, 0x00038026, + 0x033, 0x00070026, + 0x033, 0x00078026, + 0x033, 0x000D8022, + 0x0EF, 0x00000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0C9, 0x00000600, + 0x0B0, 0x000FFBC3, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B87, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B87, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B87, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B87, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0B1, 0x00033B8F, + 0xA0000000, 0x00000000, + 0x0B1, 0x00033B87, + 0xB0000000, 0x00000000, + 0x0B2, 0x00033762, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000140F0, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000140F0, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000140F0, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000140F0, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0B4, 0x000141F0, + 0xA0000000, 0x00000000, + 0x0B4, 0x000140F0, + 0xB0000000, 0x00000000, + 0x0B5, 0x00014000, + 0x0B6, 0x00012425, + 0x0B7, 0x00010E8C, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00030FFF, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00030FFF, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00030FFF, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00030FFF, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00070FFF, + 0xA0000000, 0x00000000, + 0x0B8, 0x00030FFF, + 0xB0000000, 0x00000000, + 0x0B9, 0x000C0008, + 0x0BA, 0x00040005, + 0x0C2, 0x00002C01, + 0x0C3, 0x0000000B, + 0x0C4, 0x00081E2F, + 0x0C5, 0x0005C28F, + 0x0C6, 0x000000A0, + 0x0C9, 0x00000600, + 0x0CA, 0x00002000, + 0xFFE, 0x00000000, + 0x018, 0x00008C07, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x000, 0x00035DF5, + +}; + +void +ODM_ReadAndConfig_MP_8197F_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8197F_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8197F_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8197F(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8197F_RadioA(void) +{ + return 66; +} + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +u4Byte Array_MP_8197F_RadioB[] = { + 0x000, 0x00030000, + 0x081, 0x0000FC00, + 0x082, 0x000003C0, + 0x084, 0x00000005, + 0x086, 0x000933A5, + 0x087, 0x00000000, + 0x088, 0x0007B030, + 0x08E, 0x00064540, + 0x08F, 0x000A8000, + 0x0DF, 0x00000E00, + 0x051, 0x00000C18, + 0x052, 0x0009A007, + 0x053, 0x00018C4B, + 0x054, 0x00090030, + 0x055, 0x00082000, + 0x056, 0x0000880F, + 0x057, 0x0007F000, + 0x058, 0x000603F0, + 0x05A, 0x00050000, + 0x05B, 0x00000006, + 0x05C, 0x00000015, + 0x065, 0x00020000, + 0x06E, 0x00038319, + 0x0DF, 0x00000602, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000121, + 0x033, 0x00004123, + 0x033, 0x00008126, + 0x033, 0x0000C129, + 0x033, 0x0001012C, + 0x033, 0x0001414C, + 0x033, 0x0001816C, + 0x033, 0x0001C16F, + 0x033, 0x000201AE, + 0x033, 0x000245AC, + 0x033, 0x00028DAB, + 0x0EF, 0x00000000, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x000000A5, + 0x033, 0x000040A8, + 0x033, 0x000080E8, + 0x033, 0x0000C4E6, + 0x033, 0x00010DE5, + 0x033, 0x00014DE8, + 0x033, 0x00018DEB, + 0x033, 0x0001CDEE, + 0x033, 0x00020DF1, + 0x033, 0x00024DF4, + 0x033, 0x00028DF7, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x9000f004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90001002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x9000f003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0x90001007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0x90002007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x0006000D, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00020000, + 0x033, 0x00030021, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x000, 0x00035DF5, + +}; + +void +ODM_ReadAndConfig_MP_8197F_RadioB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8197F_RadioB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8197F_RadioB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8197F_RadioB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioB_8197F(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8197F_RadioB(void) +{ + return 66; +} + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type0.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type0( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type1.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type1( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type2.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type2( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type3.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type3( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type4.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type4( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type5.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8197F[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12, 13, 13}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type5( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type6.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type6( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8197F, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type7.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8197F[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8197F[] = {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8}; + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type7( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8197F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8197F, DELTA_SWINGIDX_SIZE*3); +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.h b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.h index 7184bb6242b..e1f7d8277df 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halhwimg8197f_rf.h @@ -1,134 +1,134 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8197F_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8197F_H -#define __INC_MP_RF_HW_IMG_8197F_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_RadioA(void); - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_RadioB(void); - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack(void); - -/****************************************************************************** -* TxPowerTrack_Type0.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type0(void); - -/****************************************************************************** -* TxPowerTrack_Type1.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type1(void); - -/****************************************************************************** -* TxPowerTrack_Type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type2(void); - -/****************************************************************************** -* TxPowerTrack_Type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type3(void); - -/****************************************************************************** -* TxPowerTrack_Type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type4(void); - -/****************************************************************************** -* TxPowerTrack_Type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type5(void); - -/****************************************************************************** -* TxPowerTrack_Type6.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type6(void); - -/****************************************************************************** -* TxPowerTrack_Type7.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type7(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8197F_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8197F_H +#define __INC_MP_RF_HW_IMG_8197F_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_RadioA(void); + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_RadioB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_RadioB(void); + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack(void); + +/****************************************************************************** +* TxPowerTrack_Type0.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type0(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type0(void); + +/****************************************************************************** +* TxPowerTrack_Type1.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type1(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type1(void); + +/****************************************************************************** +* TxPowerTrack_Type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type2(void); + +/****************************************************************************** +* TxPowerTrack_Type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type3(void); + +/****************************************************************************** +* TxPowerTrack_Type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type4(void); + +/****************************************************************************** +* TxPowerTrack_Type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type5(void); + +/****************************************************************************** +* TxPowerTrack_Type6.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type6(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type6(void); + +/****************************************************************************** +* TxPowerTrack_Type7.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8197F_TxPowerTrack_Type7(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8197F_TxPowerTrack_Type7(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.c b/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.c index dfe09246d61..18c1452af8a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.c @@ -1,329 +1,329 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) - -void setIqkMatrix_8197F( - PVOID pDM_VOID, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - s4Byte ele_A = 0, ele_D, ele_C = 0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; - - /*new element A = element D x X*/ - if (IqkResult_X != 0) { - if ((IqkResult_X & 0x00000200) != 0) /*consider minus*/ - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; - - /*new element C = element D x Y*/ - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; - - /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ - switch (RFPath) { - case ODM_RF_PATH_A: - /*write new elements A, C, D to regC80 and regC94, element B is always 0*/ - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - /*write new elements A, C, D to regC88 and regC9C, element B is always 0*/ - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); - -} - - -#if 0 -VOID -setCCKFilterCoefficient_8197F( - PVOID pDM_VOID, - u1Byte CCKSwingIndex -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - - unsigned char channel; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) - channel = priv->pshare->working_channel; - else -#endif - channel = (priv->pmib->dot11RFEntry.dot11channel); - - if (channel != 14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CCK Channel=%d 0xa20=0x%x 0xa24=0x%x 0xa28=0x%x\n", channel, ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord))); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CCK Channel=%d 0xa20=0x%x 0xa24=0x%x 0xa28=0x%x\n", channel, ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord))); - } -} -#endif - - - -VOID -ODM_TxPwrTrackSetPwr8197F( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - prtl8192cd_priv priv = pDM_Odm->priv; - s1Byte Final_OFDM_Swing_Index = 0; - s1Byte Final_CCK_Swing_Index = 0; - u4Byte BitMask_10_0 = (BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); - u4Byte BitMask_21_11 = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | BIT11); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->DefaultOfdmIndex=%d pRF->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->Absolute_OFDMSwingIdx=%d pRF->Remnant_OFDMSwingIdx=%d pRF->Absolute_CCKSwingIdx=%d pRF->Remnant_CCKSwingIdx=%d RFPath=%d\n", - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath]; - - /*OFDM BB-Swing Index Limit*/ - if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - else if (Final_OFDM_Swing_Index > OFDM_TABLE_SIZE_92D - 1) - Final_OFDM_Swing_Index = OFDM_TABLE_SIZE_92D - 1; - - /*CCK BB-Swing Index Limit*/ - if (Final_CCK_Swing_Index < 0) - Final_CCK_Swing_Index = 0; - else if (Final_CCK_Swing_Index > CCK_TABLE_SIZE_8723D - 1) - Final_CCK_Swing_Index = CCK_TABLE_SIZE_8723D - 1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Final_OFDM_Swing_Index=%d Final_CCK_Swing_Index=%d RFPath=%d\n", Final_OFDM_Swing_Index, Final_CCK_Swing_Index, RFPath)); - - - - if (Method == BBSWING) { - switch (RFPath) { - - case ODM_RF_PATH_A: -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[Final_OFDM_Swing_Index]); -#else - setIqkMatrix_8197F(pDM_VOID, Final_OFDM_Swing_Index, RFPath, priv->pshare->RegE94, priv->pshare->RegE9C); -#endif -/* setCCKFilterCoefficient_8197F(pDM_VOID, Final_CCK_Swing_Index);*/ - ODM_SetBBReg(pDM_Odm, 0xAb4, BitMask_10_0, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BBSwing=0x%x CCKBBSwing=0x%x RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord), - ODM_GetBBReg(pDM_Odm, 0xAb4, BitMask_10_0), RFPath)); - break; - - case ODM_RF_PATH_B: -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[Final_OFDM_Swing_Index]); -#else - setIqkMatrix_8197F(pDM_VOID, Final_OFDM_Swing_Index, RFPath, priv->pshare->RegEB4, priv->pshare->RegEBC); -#endif -/* setCCKFilterCoefficient_8197F(pDM_VOID, Final_CCK_Swing_Index);*/ - ODM_SetBBReg(pDM_Odm, 0xAb4, BitMask_21_11, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BBSwing=0x%x CCKBBSwing=0x%x RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord), - ODM_GetBBReg(pDM_Odm, 0xAb4, BitMask_21_11), RFPath)); - break; - - default: - break; - } - - - } - -} - -VOID -GetDeltaSwingTable_8197F( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte channel = *(pDM_Odm->pChannel); - - if (channel >= 1 && channel <= 14) { - *TemperatureUP_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } else { - *TemperatureUP_CCK_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_CCK_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - *TemperatureUP_CCK_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_CCK_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - } - - return; - -} - - - -void ConfigureTxpowerTrack_8197F( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->Threshold_DPK = DPK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8197F; - pConfig->RfPathCount = MAX_PATH_NUM_8197F; - pConfig->ThermalRegAddr = RF_T_METER_8197F; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8197F; - pConfig->DoIQK = DoIQK_8197F; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8197F; - pConfig->GetDeltaAllSwingTable = GetDeltaSwingTable_8197F; -} - -#if 0 - -VOID PHY_SetRFPathSwitch_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -} - -BOOLEAN -phy_QueryRFPathSwitch_8197F( - IN PADAPTER pAdapter - ) -{ - return TRUE; -} - - -BOOLEAN PHY_QueryRFPathSwitch_8197F( - IN PADAPTER pAdapter - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - - return phy_QueryRFPathSwitch_8197F(pAdapter); -} -#endif - -#endif /* (RTL8197F_SUPPORT == 0)*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) + +void setIqkMatrix_8197F( + PVOID pDM_VOID, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; + + /*new element A = element D x X*/ + if (IqkResult_X != 0) { + if ((IqkResult_X & 0x00000200) != 0) /*consider minus*/ + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; + + /*new element C = element D x Y*/ + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; + + /*if (RFPath == ODM_RF_PATH_A)// Remove this to Fix Path B PowerTracking */ + switch (RFPath) { + case ODM_RF_PATH_A: + /*write new elements A, C, D to regC80 and regC94, element B is always 0*/ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + /*write new elements A, C, D to regC88 and regC9C, element B is always 0*/ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); + +} + + +#if 0 +VOID +setCCKFilterCoefficient_8197F( + PVOID pDM_VOID, + u1Byte CCKSwingIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + + unsigned char channel; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) + channel = priv->pshare->working_channel; + else +#endif + channel = (priv->pmib->dot11RFEntry.dot11channel); + + if (channel != 14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CCK Channel=%d 0xa20=0x%x 0xa24=0x%x 0xa28=0x%x\n", channel, ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord))); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("CCK Channel=%d 0xa20=0x%x 0xa24=0x%x 0xa28=0x%x\n", channel, ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord))); + } +} +#endif + + + +VOID +ODM_TxPwrTrackSetPwr8197F( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + prtl8192cd_priv priv = pDM_Odm->priv; + s1Byte Final_OFDM_Swing_Index = 0; + s1Byte Final_CCK_Swing_Index = 0; + u4Byte BitMask_10_0 = (BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + u4Byte BitMask_21_11 = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | BIT11); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->DefaultOfdmIndex=%d pRF->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->Absolute_OFDMSwingIdx=%d pRF->Remnant_OFDMSwingIdx=%d pRF->Absolute_CCKSwingIdx=%d pRF->Remnant_CCKSwingIdx=%d RFPath=%d\n", + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath]; + + /*OFDM BB-Swing Index Limit*/ + if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + else if (Final_OFDM_Swing_Index > OFDM_TABLE_SIZE_92D - 1) + Final_OFDM_Swing_Index = OFDM_TABLE_SIZE_92D - 1; + + /*CCK BB-Swing Index Limit*/ + if (Final_CCK_Swing_Index < 0) + Final_CCK_Swing_Index = 0; + else if (Final_CCK_Swing_Index > CCK_TABLE_SIZE_8723D - 1) + Final_CCK_Swing_Index = CCK_TABLE_SIZE_8723D - 1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Final_OFDM_Swing_Index=%d Final_CCK_Swing_Index=%d RFPath=%d\n", Final_OFDM_Swing_Index, Final_CCK_Swing_Index, RFPath)); + + + + if (Method == BBSWING) { + switch (RFPath) { + + case ODM_RF_PATH_A: +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[Final_OFDM_Swing_Index]); +#else + setIqkMatrix_8197F(pDM_VOID, Final_OFDM_Swing_Index, RFPath, priv->pshare->RegE94, priv->pshare->RegE9C); +#endif +/* setCCKFilterCoefficient_8197F(pDM_VOID, Final_CCK_Swing_Index);*/ + ODM_SetBBReg(pDM_Odm, 0xAb4, BitMask_10_0, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BBSwing=0x%x CCKBBSwing=0x%x RFPath=%d\n", + ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord), + ODM_GetBBReg(pDM_Odm, 0xAb4, BitMask_10_0), RFPath)); + break; + + case ODM_RF_PATH_B: +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[Final_OFDM_Swing_Index]); +#else + setIqkMatrix_8197F(pDM_VOID, Final_OFDM_Swing_Index, RFPath, priv->pshare->RegEB4, priv->pshare->RegEBC); +#endif +/* setCCKFilterCoefficient_8197F(pDM_VOID, Final_CCK_Swing_Index);*/ + ODM_SetBBReg(pDM_Odm, 0xAb4, BitMask_21_11, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BBSwing=0x%x CCKBBSwing=0x%x RFPath=%d\n", + ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord), + ODM_GetBBReg(pDM_Odm, 0xAb4, BitMask_21_11), RFPath)); + break; + + default: + break; + } + + + } + +} + +VOID +GetDeltaSwingTable_8197F( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B, + pu1Byte *TemperatureUP_CCK_A, + pu1Byte *TemperatureDOWN_CCK_A, + pu1Byte *TemperatureUP_CCK_B, + pu1Byte *TemperatureDOWN_CCK_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte channel = *(pDM_Odm->pChannel); + + if (channel >= 1 && channel <= 14) { + *TemperatureUP_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } else { + *TemperatureUP_CCK_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_CCK_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + *TemperatureUP_CCK_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_CCK_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + } + + return; + +} + + + +void ConfigureTxpowerTrack_8197F( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->Threshold_DPK = DPK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8197F; + pConfig->RfPathCount = MAX_PATH_NUM_8197F; + pConfig->ThermalRegAddr = RF_T_METER_8197F; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8197F; + pConfig->DoIQK = DoIQK_8197F; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8197F; + pConfig->GetDeltaAllSwingTable = GetDeltaSwingTable_8197F; +} + +#if 0 + +VOID PHY_SetRFPathSwitch_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +} + +BOOLEAN +phy_QueryRFPathSwitch_8197F( + IN PADAPTER pAdapter + ) +{ + return TRUE; +} + + +BOOLEAN PHY_QueryRFPathSwitch_8197F( + IN PADAPTER pAdapter + ) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + + return phy_QueryRFPathSwitch_8197F(pAdapter); +} +#endif + +#endif /* (RTL8197F_SUPPORT == 0)*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.h b/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.h index 1e5920ecc60..080078fe881 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/halphyrf_8197f.h @@ -1,76 +1,76 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8197F_H__ -#define __HAL_PHY_RF_8197F_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -#define IQK_DELAY_TIME_97F 15 /*ms*/ -#else -#define IQK_DELAY_TIME_97F 10 -#endif - -#define AVG_THERMAL_NUM_8197F 4 -#define RF_T_METER_8197F 0x42 -#define DPK_THRESHOLD_8197F 7 - - -void -ConfigureTxpowerTrack_8197F( - PTXPWRTRACK_CFG pConfig - ); - -VOID -ODM_TxPwrTrackSetPwr8197F( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -GetDeltaSwingTable_8197F( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B - ); - - - - -VOID -PHY_SetRFPathSwitch_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - -#endif /* #ifndef __HAL_PHY_RF_8197F_H__ */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8197F_H__ +#define __HAL_PHY_RF_8197F_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define IQK_DELAY_TIME_97F 15 /*ms*/ +#else +#define IQK_DELAY_TIME_97F 10 +#endif + +#define AVG_THERMAL_NUM_8197F 4 +#define RF_T_METER_8197F 0x42 +#define DPK_THRESHOLD_8197F 7 + + +void +ConfigureTxpowerTrack_8197F( + PTXPWRTRACK_CFG pConfig + ); + +VOID +ODM_TxPwrTrackSetPwr8197F( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +GetDeltaSwingTable_8197F( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B, + pu1Byte *TemperatureUP_CCK_A, + pu1Byte *TemperatureDOWN_CCK_A, + pu1Byte *TemperatureUP_CCK_B, + pu1Byte *TemperatureDOWN_CCK_B + ); + + + + +VOID +PHY_SetRFPathSwitch_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + +#endif /* #ifndef __HAL_PHY_RF_8197F_H__ */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.c b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.c index fa2104b7778..2ed7f469157 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.c @@ -1,1181 +1,1181 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) - -/* ======================================================================== */ -/* These following functions can be used for PHY DM only*/ - -VOID -phydm_CcaParByBw_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte regc3c; - u4Byte regc3c_8_6; /*regc3c[8:6]*/ - u4Byte reg_aaa; - - regc3c = ODM_GetBBReg(pDM_Odm, 0xc3c, bMaskDWord); - regc3c_8_6 = ((regc3c & 0x1c0)>>6); - regc3c &= (~(0x000001f8)); - - reg_aaa = ODM_Read1Byte(pDM_Odm, 0xaaa) & 0x1f; - pDM_DigTable->aaa_default = reg_aaa; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s ==> RFEType=%d, PackageType=%d, CutVersion=%d, bandwidth=%d, RXAntStatus=%d\n", - __func__, - pDM_Odm->RFEType, - pDM_Odm->PackageType, - pDM_Odm->CutVersion, - bandwidth, - pDM_Odm->RXAntStatus)); - - if ((pDM_Odm->RFEType == 1) && (pDM_Odm->PackageType == 1)) { // 97FS type1 - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if ((bandwidth == ODM_BW40M) && (pDM_Odm->RXAntStatus != (ODM_RF_A|ODM_RF_B))) { - regc3c |= ((0x1) << 3); - regc3c |= ((0x0) << 6); - } else if ((bandwidth == ODM_BW40M) && (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B))){ - regc3c |= ((0x1) << 3); - regc3c |= ((0x3) << 6); - } else { - regc3c |= ((0x0) << 3); - regc3c |= ((0x0) << 6); - } - } else { - regc3c |= ((0x2) << 3); - regc3c |= ((0x6) << 6); - } - if ((bandwidth == ODM_BW20M)) { - reg_aaa = 0x10; - } else { - reg_aaa = 0x12; - } - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); - pDM_DigTable->aaa_default = reg_aaa; - } else if ((pDM_Odm->RFEType == 1) && (pDM_Odm->PackageType == 2)) { // 97FN type1 - if ((bandwidth == ODM_BW20M)) { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x3) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x3) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x10; - } else { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x12; - } - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); - pDM_DigTable->aaa_default = reg_aaa; - - } - else if ((pDM_Odm->RFEType == 2) && (pDM_Odm->PackageType == 2)) { - if ((bandwidth == ODM_BW20M)) { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x1) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0xf; - } - else { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x0) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x12; - } - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); - pDM_DigTable->aaa_default = reg_aaa; - } else if ((pDM_Odm->RFEType == 3) && (pDM_Odm->PackageType == 2)) { // 97FN type3 - if ((bandwidth == ODM_BW20M)) { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x10; - } else { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x1) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x1) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x12; - } - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); - pDM_DigTable->aaa_default = reg_aaa; - } - else { // 97FN/97FS type0 - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if ((bandwidth == ODM_BW20M) && (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B))) { - regc3c |= ((0x0) << 3); - regc3c |= ((0x0) << 6); - } else { - regc3c |= ((0x1) << 3); - regc3c |= ((0x4) << 6); - } - } else { - if ((bandwidth == ODM_BW20M)) { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0xf; - } else { - if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } else { /*ODM_BW40M*/ - regc3c |= ((0x2) << 3); - regc3c |= (regc3c_8_6 << 6); - } - reg_aaa = 0x12; - } - ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); - pDM_DigTable->aaa_default = reg_aaa; - } - - } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s ==> regc3c=0x%x, reg_aaa=0x%x\n", __func__, regc3c, reg_aaa)); - - ODM_SetBBReg(pDM_Odm, 0xc3c, bMaskDWord, regc3c); -} - -VOID -phydm_CcaParByRxPath_8197f( - IN PDM_ODM_T pDM_Odm - ) -{ - ODM_BW_E bandwidth = *pDM_Odm->pBandWidth; - - phydm_CcaParByBw_8197f(pDM_Odm, bandwidth); -} - -VOID -phydm_RxDfirParByBw_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - ODM_SetBBReg(pDM_Odm, ODM_REG_TAP_UPD_97F, (BIT21|BIT20), 0x2); - ODM_SetBBReg(pDM_Odm, ODM_REG_DOWNSAM_FACTOR_11N, (BIT29|BIT28), 0x2); - - if (bandwidth == ODM_BW40M) { - /* RX DFIR for BW40 */ - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, BIT8, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, bMaskByte0, 0x3); - } else { - /* RX DFIR for BW20, BW10 and BW5*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, BIT8, 0x1); - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, bMaskByte0, 0xa3); - } -} - -VOID -phydm_init_hw_info_by_rfe_type_8197f( - IN PDM_ODM_T pDM_Odm - ) -{ - u2Byte mask_path_a = 0x0303; - u2Byte mask_path_b = 0x0c0c; - /*u2Byte mask_path_c = 0x3030;*/ - /*u2Byte mask_path_d = 0xc0c0;*/ - - pDM_Odm->bInitHwInfoByRfe = FALSE; - - if (pDM_Odm->RFEType == 0) { - panic_printk("[97F] RFE type 0 PHY paratemters: DEFAULT\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_DEFAULT); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x0); /*GPIO setting*/ - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x0); /*GPIO setting*/ - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x0); /*GPIO setting*/ - - } else if (pDM_Odm->RFEType == 1) { - panic_printk("[97F] RFE type 1 PHY paratemters: GPA0+GLNA0\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 2) { - panic_printk("[97F] RFE type 2 PHY paratemters: 2L internal\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA_5G); /*Special setting for 2L internal*/ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x0); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x0); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x0); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - - } else if (pDM_Odm->RFEType == 3) { - panic_printk("[97F] RFE type 3 PHY paratemters: internal with TRSW\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA_5G); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 1); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - - } else if (pDM_Odm->RFEType == 4) { - panic_printk("[97F] RFE type 4 PHY paratemters: GLNA0\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_LNA); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - - } else if (pDM_Odm->RFEType == 5) { - panic_printk("[97F] RFE type 5 PHY paratemters: GPA1+GLNA1\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - - } else if (pDM_Odm->RFEType == 6) { - panic_printk("[97F] RFE type 6 PHY paratemters: GLNA1\n"); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_LNA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - - } else { - panic_printk("[97F] RFE type Unknown PHY paratemters:\n"); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); - ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); - } - - pDM_Odm->bInitHwInfoByRfe = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: RFE type (%d), Board type (0x%x), Package type (%d)\n", __func__, pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", __func__, pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", __func__, pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA)); - -} - -/* ======================================================================== */ - -/* ======================================================================== */ -/* These following functions can be used by driver*/ - -u4Byte -config_phydm_read_rf_reg_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ - u4Byte Readback_Value, Direct_Addr; - u4Byte offset_readRF[2] = {0x2800, 0x2c00}; - u4Byte power_RF[2] = {0x1c, 0x78}; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): unsupported path (%d)\n", RFPath)); - return INVALID_RF_DATA; - } - - /* Error handling. Check if RF power is enable or not */ - /* 0xffffffff means RF power is disable */ - if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): Read fail, RF is disabled\n")); - return INVALID_RF_DATA; - } - - /* Calculate offset */ - RegAddr &= 0xff; - Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); - - /* RF register only has 20bits */ - BitMask &= bRFRegOffsetMask; - - /* Read RF register directly */ - Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - RFPath, RegAddr, Readback_Value, BitMask)); - return Readback_Value; -} - -BOOLEAN -config_phydm_write_rf_reg_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ - u4Byte DataAndAddr = 0, Data_original = 0; - u4Byte offset_writeRF[2] = {0x840, 0x844}; - u4Byte power_RF[2] = {0x1c, 0x78}; - u1Byte BitShift; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): unsupported path (%d)\n", RFPath)); - return FALSE; - } - - /* Read RF register content first */ - RegAddr &= 0xff; - BitMask = BitMask & bRFRegOffsetMask; - - if (BitMask != bRFRegOffsetMask) { - Data_original = config_phydm_read_rf_reg_8197f(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); - - /* Error handling. RF is disabled */ - if (config_phydm_read_rf_check_8197f(Data_original) == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): Write fail, RF is disable\n")); - return FALSE; - } - - /* check bit mask */ - if (BitMask != 0xfffff) { - for (BitShift = 0; BitShift <= 19; BitShift++) { - if (((BitMask >> BitShift) & 0x1) == 1) - break; - } - Data = ((Data_original) & (~BitMask)) | ((Data << BitShift) & (BitMask)); - } - } - else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): Write fail, RF is disabled\n")); - return FALSE; - } - - /* Put write addr in [27:20] and write data in [19:00] */ - DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; - - /* Write Operation */ - ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - RFPath, RegAddr, Data, Data_original, BitMask)); - return TRUE; -} - -BOOLEAN -config_phydm_write_txagc_8197f( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u1Byte readBack_data; /*for 97F workaroud*/ - /* Input need to be HW rate index, not driver rate index!!!! */ - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): disable PHY API for debug!!\n")); - return TRUE; - } - - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > ODM_RATEMCS15)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): unsupported path (%d)\n", Path)); - return FALSE; - } - - if (Path == ODM_RF_PATH_A) { - switch (HwRate) { - case ODM_RATE1M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_CCK1_Mcs32, 0x00007f00, PowerIndex); - break; - case ODM_RATE2M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x00007f00, PowerIndex); - break; - case ODM_RATE5_5M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x007f0000, PowerIndex); - break; - case ODM_RATE11M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x7f000000, PowerIndex); - break; - - case ODM_RATE6M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x0000007f, PowerIndex); - break; - case ODM_RATE9M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x00007f00, PowerIndex); - break; - case ODM_RATE12M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x007f0000, PowerIndex); - break; - case ODM_RATE18M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x7f000000, PowerIndex); - break; - case ODM_RATE24M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x0000007f, PowerIndex); - break; - case ODM_RATE36M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x00007f00, PowerIndex); - break; - case ODM_RATE48M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x007f0000, PowerIndex); - break; - case ODM_RATE54M: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x7f000000, PowerIndex); - break; - - case ODM_RATEMCS0: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS1: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS2: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS3: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x7f000000, PowerIndex); - break; - case ODM_RATEMCS4: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS5: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS6: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS7: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x7f000000, PowerIndex); - break; - - case ODM_RATEMCS8: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS9: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS10: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS11: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x7f000000, PowerIndex); - break; - case ODM_RATEMCS12: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS13: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS14: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS15: - ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x7f000000, PowerIndex); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); - break; - } - } else if (Path == ODM_RF_PATH_B) { - switch (HwRate) { - case ODM_RATE1M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x00007f00, PowerIndex); - break; - case ODM_RATE2M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x007f0000, PowerIndex); - break; - case ODM_RATE5_5M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x7f000000, PowerIndex); - break; - case ODM_RATE11M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x0000007f, PowerIndex); - break; - - case ODM_RATE6M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x0000007f, PowerIndex); - break; - case ODM_RATE9M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x00007f00, PowerIndex); - break; - case ODM_RATE12M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x007f0000, PowerIndex); - break; - case ODM_RATE18M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x7f000000, PowerIndex); - break; - case ODM_RATE24M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x0000007f, PowerIndex); - break; - case ODM_RATE36M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x00007f00, PowerIndex); - break; - case ODM_RATE48M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x007f0000, PowerIndex); - break; - case ODM_RATE54M: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x7f000000, PowerIndex); - break; - - case ODM_RATEMCS0: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS1: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS2: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS3: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x7f000000, PowerIndex); - break; - case ODM_RATEMCS4: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS5: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS6: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS7: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x7f000000, PowerIndex); - break; - - case ODM_RATEMCS8: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS9: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS10: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS11: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x7f000000, PowerIndex); - break; - case ODM_RATEMCS12: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x0000007f, PowerIndex); - break; - case ODM_RATEMCS13: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x00007f00, PowerIndex); - break; - case ODM_RATEMCS14: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x007f0000, PowerIndex); - break; - case ODM_RATEMCS15: - ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x7f000000, PowerIndex); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); - break; - } - } else - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid RF path!!\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): Path-%d Rate index 0x%x = 0x%x\n", - Path, HwRate, PowerIndex)); - return TRUE; -} - -u1Byte -config_phydm_read_txagc_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u1Byte readBack_data; - - /* Input need to be HW rate index, not driver rate index!!!! */ - - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > ODM_RATEMCS15)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8197f(): unsupported path (%d)\n", Path)); - return INVALID_TXAGC_DATA; - } - - if (Path == ODM_RF_PATH_A) { - switch (HwRate) { - case ODM_RATE1M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_CCK1_Mcs32, 0x00007f00); - break; - case ODM_RATE2M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x00007f00); - break; - case ODM_RATE5_5M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x007f0000); - break; - case ODM_RATE11M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x7f000000); - break; - - case ODM_RATE6M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x0000007f); - break; - case ODM_RATE9M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x00007f00); - break; - case ODM_RATE12M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x007f0000); - break; - case ODM_RATE18M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x7f000000); - break; - case ODM_RATE24M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x0000007f); - break; - case ODM_RATE36M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x00007f00); - break; - case ODM_RATE48M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x007f0000); - break; - case ODM_RATE54M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x7f000000); - break; - - case ODM_RATEMCS0: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x0000007f); - break; - case ODM_RATEMCS1: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x00007f00); - break; - case ODM_RATEMCS2: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x007f0000); - break; - case ODM_RATEMCS3: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x7f000000); - break; - case ODM_RATEMCS4: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x0000007f); - break; - case ODM_RATEMCS5: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x00007f00); - break; - case ODM_RATEMCS6: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x007f0000); - break; - case ODM_RATEMCS7: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x7f000000); - break; - - case ODM_RATEMCS8: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x0000007f); - break; - case ODM_RATEMCS9: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x00007f00); - break; - case ODM_RATEMCS10: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x007f0000); - break; - case ODM_RATEMCS11: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x7f000000); - break; - case ODM_RATEMCS12: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x0000007f); - break; - case ODM_RATEMCS13: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x00007f00); - break; - case ODM_RATEMCS14: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x007f0000); - break; - case ODM_RATEMCS15: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x7f000000); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); - break; - } - } else if (Path == ODM_RF_PATH_B) { - switch (HwRate) { - case ODM_RATE1M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x00007f00); - break; - case ODM_RATE2M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x007f0000); - break; - case ODM_RATE5_5M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x7f000000); - break; - case ODM_RATE11M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x0000007f); - break; - - case ODM_RATE6M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x0000007f); - break; - case ODM_RATE9M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x00007f00); - break; - case ODM_RATE12M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x007f0000); - break; - case ODM_RATE18M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x7f000000); - break; - case ODM_RATE24M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x0000007f); - break; - case ODM_RATE36M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x00007f00); - break; - case ODM_RATE48M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x007f0000); - break; - case ODM_RATE54M: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x7f000000); - break; - - case ODM_RATEMCS0: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x0000007f); - break; - case ODM_RATEMCS1: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x00007f00); - break; - case ODM_RATEMCS2: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x007f0000); - break; - case ODM_RATEMCS3: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x7f000000); - break; - case ODM_RATEMCS4: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x0000007f); - break; - case ODM_RATEMCS5: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x00007f00); - break; - case ODM_RATEMCS6: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x007f0000); - break; - case ODM_RATEMCS7: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x7f000000); - break; - - case ODM_RATEMCS8: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x0000007f); - break; - case ODM_RATEMCS9: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x00007f00); - break; - case ODM_RATEMCS10: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x007f0000); - break; - case ODM_RATEMCS11: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x7f000000); - break; - case ODM_RATEMCS12: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x0000007f); - break; - case ODM_RATEMCS13: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x00007f00); - break; - case ODM_RATEMCS14: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x007f0000); - break; - case ODM_RATEMCS15: - readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x7f000000); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); - break; - } - } else - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid RF path!!\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8197f(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data)); - return readBack_data; -} - -BOOLEAN -config_phydm_switch_channel_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f()====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): disable PHY API for debug!!\n")); - return TRUE; - } - - rf_reg18 = config_phydm_read_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8197f(rf_reg18); - - /* Switch band and channel */ - if (central_ch <= 14) { - /* 2.4G */ - /*table selection*/ - pDM_DigTable->agcTableIdx = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV2_11N, BIT12|BIT11|BIT10|BIT9); - /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); - rf_reg18 = (rf_reg18|central_ch); - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Fail to switch band (ch: %d)\n", central_ch)); - return FALSE; - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_B, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); - return FALSE; - } - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Success to switch channel (ch: %d)\n", central_ch)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_bandwidth_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f()===================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): disable PHY API for debug!!\n")); - return TRUE; - } - - /* Error handling */ - if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return FALSE; - } - - rf_reg18 = config_phydm_read_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8197f(rf_reg18); - - /* Switch bandwidth */ - switch (bandwidth) { - case ODM_BW20M: - { - /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 20M */ - ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); - - /* ADC clock = 160M clock for BW20*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x4); - - /* DAC clock = 160M clock for BW20 = 3'b101*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x5); - - /* ADC buffer clock 0xca4[27:26] = 2'b10*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 | BIT11 | BIT10); - break; - } - case ODM_BW40M: - { - /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 1 for 40M */ - ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x1); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x1); - - /* ADC clock = 160M clock for BW40 no need to setting, it will be setting in PHY_REG */ - - /* DAC clock = 160M clock for BW20 = 3'b101*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x5); - - /* ADC buffer clock 0xca4[27:26] = 2'b10*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); - - /* CCK primary channel */ - if (primary_ch_idx == 1) - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT4, primary_ch_idx); - else - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT4, 0); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT11); - break; - } - case ODM_BW5M: - { - /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 5M */ - ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x1); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); - - /* ADC clock = 40M clock for BW5 = 3'b010*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x2); - - /* DAC clock = 20M clock for BW20 = 3'b110*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x6); - - /* ADC buffer clock 0xca4[27:26] = 2'b10*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - case ODM_BW10M: - { - /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 10M */ - ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x2); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); - - /* ADC clock = 80M clock for BW5 = 3'b011*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x3); - - /* DAC clock = 160M clock for BW20 = 3'b110*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x4); - - /* ADC buffer clock 0xca4[27:26] = 2'b10*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - } - - /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_B, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); - return FALSE; - } - - /* Modify RX DFIR parameters */ - phydm_RxDfirParByBw_8197f(pDM_Odm, bandwidth); - - /* Modify CCA parameters */ - phydm_CcaParByBw_8197f(pDM_Odm, bandwidth); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_channel_bw_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - u1Byte eRFPath = 0; - u4Byte RFValToWR , RFTmpVal, BitShift, BitMask; - - /* Switch band */ - /*97F no need*/ - - /* Switch channel */ - if (config_phydm_switch_channel_8197f(pDM_Odm, central_ch) == FALSE) - return FALSE; - - /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8197f(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) - return FALSE; - - return TRUE; -} - -BOOLEAN -config_phydm_trx_mode_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) -{ - BOOLEAN rf_reg_status = TRUE; - u1Byte IGI; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f()=====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): disable PHY API for debug!!\n")); - return TRUE; - } - - if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Wrong TX setting (TX: 0x%x)\n", TxPath)); - return FALSE; - } - - if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Wrong RX setting (RX: 0x%x)\n", RxPath)); - return FALSE; - } - - /* RF mode of path-A and path-B */ - /* OFDM Tx and Rx path setting */ - if (TxPath == (ODM_RF_A|ODM_RF_B)) - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x81121313); - else if (TxPath & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x81121311); - else - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x82221322); - - if (RxPath == (ODM_RF_A|ODM_RF_B)) { - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x33); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x3); - } else if (RxPath & ODM_RF_A) { - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x11); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x1); - } else { - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x22); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x2); - } - - /* CCK Tx and Rx path setting*/ - if (TxPath & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0x8); - else - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0x4); - - if (RxPath == (ODM_RF_A|ODM_RF_B)) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x4); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x1); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x1); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); - } else if (RxPath & ODM_RF_A) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); - } else { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x5); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); - } - - if(bTx2Path) { - /*OFDM tx setting*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x83321333); - /*CCK tx setting*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0xc); - - /*Paath_A*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff, 0x08000); /*Select Standby mode 0x30=0x08000*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff, 0x0005f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0x01042); /*Enable TXIQGEN in standby mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff, 0x0004f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0x71fc2); /*Enable TXIQGEN in RX mode*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +VOID +phydm_CcaParByBw_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u4Byte regc3c; + u4Byte regc3c_8_6; /*regc3c[8:6]*/ + u4Byte reg_aaa; + + regc3c = ODM_GetBBReg(pDM_Odm, 0xc3c, bMaskDWord); + regc3c_8_6 = ((regc3c & 0x1c0)>>6); + regc3c &= (~(0x000001f8)); + + reg_aaa = ODM_Read1Byte(pDM_Odm, 0xaaa) & 0x1f; + pDM_DigTable->aaa_default = reg_aaa; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s ==> RFEType=%d, PackageType=%d, CutVersion=%d, bandwidth=%d, RXAntStatus=%d\n", + __func__, + pDM_Odm->RFEType, + pDM_Odm->PackageType, + pDM_Odm->CutVersion, + bandwidth, + pDM_Odm->RXAntStatus)); + + if ((pDM_Odm->RFEType == 1) && (pDM_Odm->PackageType == 1)) { // 97FS type1 + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if ((bandwidth == ODM_BW40M) && (pDM_Odm->RXAntStatus != (ODM_RF_A|ODM_RF_B))) { + regc3c |= ((0x1) << 3); + regc3c |= ((0x0) << 6); + } else if ((bandwidth == ODM_BW40M) && (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B))){ + regc3c |= ((0x1) << 3); + regc3c |= ((0x3) << 6); + } else { + regc3c |= ((0x0) << 3); + regc3c |= ((0x0) << 6); + } + } else { + regc3c |= ((0x2) << 3); + regc3c |= ((0x6) << 6); + } + if ((bandwidth == ODM_BW20M)) { + reg_aaa = 0x10; + } else { + reg_aaa = 0x12; + } + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); + pDM_DigTable->aaa_default = reg_aaa; + } else if ((pDM_Odm->RFEType == 1) && (pDM_Odm->PackageType == 2)) { // 97FN type1 + if ((bandwidth == ODM_BW20M)) { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x3) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x3) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x10; + } else { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x12; + } + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); + pDM_DigTable->aaa_default = reg_aaa; + + } + else if ((pDM_Odm->RFEType == 2) && (pDM_Odm->PackageType == 2)) { + if ((bandwidth == ODM_BW20M)) { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x1) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0xf; + } + else { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x0) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x12; + } + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); + pDM_DigTable->aaa_default = reg_aaa; + } else if ((pDM_Odm->RFEType == 3) && (pDM_Odm->PackageType == 2)) { // 97FN type3 + if ((bandwidth == ODM_BW20M)) { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x10; + } else { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x1) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x1) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x12; + } + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); + pDM_DigTable->aaa_default = reg_aaa; + } + else { // 97FN/97FS type0 + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if ((bandwidth == ODM_BW20M) && (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B))) { + regc3c |= ((0x0) << 3); + regc3c |= ((0x0) << 6); + } else { + regc3c |= ((0x1) << 3); + regc3c |= ((0x4) << 6); + } + } else { + if ((bandwidth == ODM_BW20M)) { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0xf; + } else { + if (pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) { + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } else { /*ODM_BW40M*/ + regc3c |= ((0x2) << 3); + regc3c |= (regc3c_8_6 << 6); + } + reg_aaa = 0x12; + } + ODM_SetBBReg(pDM_Odm, 0xaa8, 0x1f0000, reg_aaa); + pDM_DigTable->aaa_default = reg_aaa; + } + + } + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s ==> regc3c=0x%x, reg_aaa=0x%x\n", __func__, regc3c, reg_aaa)); + + ODM_SetBBReg(pDM_Odm, 0xc3c, bMaskDWord, regc3c); +} + +VOID +phydm_CcaParByRxPath_8197f( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_BW_E bandwidth = *pDM_Odm->pBandWidth; + + phydm_CcaParByBw_8197f(pDM_Odm, bandwidth); +} + +VOID +phydm_RxDfirParByBw_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ + ODM_SetBBReg(pDM_Odm, ODM_REG_TAP_UPD_97F, (BIT21|BIT20), 0x2); + ODM_SetBBReg(pDM_Odm, ODM_REG_DOWNSAM_FACTOR_11N, (BIT29|BIT28), 0x2); + + if (bandwidth == ODM_BW40M) { + /* RX DFIR for BW40 */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, BIT8, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, bMaskByte0, 0x3); + } else { + /* RX DFIR for BW20, BW10 and BW5*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, BIT8, 0x1); + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DFIR_MOD_97F, bMaskByte0, 0xa3); + } +} + +VOID +phydm_init_hw_info_by_rfe_type_8197f( + IN PDM_ODM_T pDM_Odm + ) +{ + u2Byte mask_path_a = 0x0303; + u2Byte mask_path_b = 0x0c0c; + /*u2Byte mask_path_c = 0x3030;*/ + /*u2Byte mask_path_d = 0xc0c0;*/ + + pDM_Odm->bInitHwInfoByRfe = FALSE; + + if (pDM_Odm->RFEType == 0) { + panic_printk("[97F] RFE type 0 PHY paratemters: DEFAULT\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_DEFAULT); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x0); /*GPIO setting*/ + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x0); /*GPIO setting*/ + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x0); /*GPIO setting*/ + + } else if (pDM_Odm->RFEType == 1) { + panic_printk("[97F] RFE type 1 PHY paratemters: GPA0+GLNA0\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); + } else if (pDM_Odm->RFEType == 2) { + panic_printk("[97F] RFE type 2 PHY paratemters: 2L internal\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA_5G); /*Special setting for 2L internal*/ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x0); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x0); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x0); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + + } else if (pDM_Odm->RFEType == 3) { + panic_printk("[97F] RFE type 3 PHY paratemters: internal with TRSW\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA_5G); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 1); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + + } else if (pDM_Odm->RFEType == 4) { + panic_printk("[97F] RFE type 4 PHY paratemters: GLNA0\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_LNA); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + + } else if (pDM_Odm->RFEType == 5) { + panic_printk("[97F] RFE type 5 PHY paratemters: GPA1+GLNA1\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); + + } else if (pDM_Odm->RFEType == 6) { + panic_printk("[97F] RFE type 6 PHY paratemters: GLNA1\n"); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_LNA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + + } else { + panic_printk("[97F] RFE type Unknown PHY paratemters:\n"); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT24, 0x1); + ODM_SetBBReg(pDM_Odm, 0x64, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x40, 0xf000000, 0x5); + } + + pDM_Odm->bInitHwInfoByRfe = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: RFE type (%d), Board type (0x%x), Package type (%d)\n", __func__, pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType)); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", __func__, pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", __func__, pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA)); + +} + +/* ======================================================================== */ + +/* ======================================================================== */ +/* These following functions can be used by driver*/ + +u4Byte +config_phydm_read_rf_reg_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ + u4Byte Readback_Value, Direct_Addr; + u4Byte offset_readRF[2] = {0x2800, 0x2c00}; + u4Byte power_RF[2] = {0x1c, 0x78}; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_B) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): unsupported path (%d)\n", RFPath)); + return INVALID_RF_DATA; + } + + /* Error handling. Check if RF power is enable or not */ + /* 0xffffffff means RF power is disable */ + if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): Read fail, RF is disabled\n")); + return INVALID_RF_DATA; + } + + /* Calculate offset */ + RegAddr &= 0xff; + Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); + + /* RF register only has 20bits */ + BitMask &= bRFRegOffsetMask; + + /* Read RF register directly */ + Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8197f(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + RFPath, RegAddr, Readback_Value, BitMask)); + return Readback_Value; +} + +BOOLEAN +config_phydm_write_rf_reg_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ + u4Byte DataAndAddr = 0, Data_original = 0; + u4Byte offset_writeRF[2] = {0x840, 0x844}; + u4Byte power_RF[2] = {0x1c, 0x78}; + u1Byte BitShift; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_B) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): unsupported path (%d)\n", RFPath)); + return FALSE; + } + + /* Read RF register content first */ + RegAddr &= 0xff; + BitMask = BitMask & bRFRegOffsetMask; + + if (BitMask != bRFRegOffsetMask) { + Data_original = config_phydm_read_rf_reg_8197f(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); + + /* Error handling. RF is disabled */ + if (config_phydm_read_rf_check_8197f(Data_original) == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): Write fail, RF is disable\n")); + return FALSE; + } + + /* check bit mask */ + if (BitMask != 0xfffff) { + for (BitShift = 0; BitShift <= 19; BitShift++) { + if (((BitMask >> BitShift) & 0x1) == 1) + break; + } + Data = ((Data_original) & (~BitMask)) | ((Data << BitShift) & (BitMask)); + } + } + else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): Write fail, RF is disabled\n")); + return FALSE; + } + + /* Put write addr in [27:20] and write data in [19:00] */ + DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; + + /* Write Operation */ + ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8197f(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + RFPath, RegAddr, Data, Data_original, BitMask)); + return TRUE; +} + +BOOLEAN +config_phydm_write_txagc_8197f( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u1Byte readBack_data; /*for 97F workaroud*/ + /* Input need to be HW rate index, not driver rate index!!!! */ + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): disable PHY API for debug!!\n")); + return TRUE; + } + + /* Error handling */ + if ((Path > ODM_RF_PATH_B) || (HwRate > ODM_RATEMCS15)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): unsupported path (%d)\n", Path)); + return FALSE; + } + + if (Path == ODM_RF_PATH_A) { + switch (HwRate) { + case ODM_RATE1M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_CCK1_Mcs32, 0x00007f00, PowerIndex); + break; + case ODM_RATE2M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x00007f00, PowerIndex); + break; + case ODM_RATE5_5M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x007f0000, PowerIndex); + break; + case ODM_RATE11M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x7f000000, PowerIndex); + break; + + case ODM_RATE6M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x0000007f, PowerIndex); + break; + case ODM_RATE9M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x00007f00, PowerIndex); + break; + case ODM_RATE12M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x007f0000, PowerIndex); + break; + case ODM_RATE18M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x7f000000, PowerIndex); + break; + case ODM_RATE24M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x0000007f, PowerIndex); + break; + case ODM_RATE36M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x00007f00, PowerIndex); + break; + case ODM_RATE48M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x007f0000, PowerIndex); + break; + case ODM_RATE54M: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x7f000000, PowerIndex); + break; + + case ODM_RATEMCS0: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS1: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS2: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS3: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x7f000000, PowerIndex); + break; + case ODM_RATEMCS4: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS5: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS6: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS7: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x7f000000, PowerIndex); + break; + + case ODM_RATEMCS8: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS9: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS10: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS11: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x7f000000, PowerIndex); + break; + case ODM_RATEMCS12: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS13: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS14: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS15: + ODM_SetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x7f000000, PowerIndex); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); + break; + } + } else if (Path == ODM_RF_PATH_B) { + switch (HwRate) { + case ODM_RATE1M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x00007f00, PowerIndex); + break; + case ODM_RATE2M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x007f0000, PowerIndex); + break; + case ODM_RATE5_5M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x7f000000, PowerIndex); + break; + case ODM_RATE11M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x0000007f, PowerIndex); + break; + + case ODM_RATE6M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x0000007f, PowerIndex); + break; + case ODM_RATE9M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x00007f00, PowerIndex); + break; + case ODM_RATE12M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x007f0000, PowerIndex); + break; + case ODM_RATE18M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x7f000000, PowerIndex); + break; + case ODM_RATE24M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x0000007f, PowerIndex); + break; + case ODM_RATE36M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x00007f00, PowerIndex); + break; + case ODM_RATE48M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x007f0000, PowerIndex); + break; + case ODM_RATE54M: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x7f000000, PowerIndex); + break; + + case ODM_RATEMCS0: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS1: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS2: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS3: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x7f000000, PowerIndex); + break; + case ODM_RATEMCS4: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS5: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS6: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS7: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x7f000000, PowerIndex); + break; + + case ODM_RATEMCS8: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS9: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS10: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS11: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x7f000000, PowerIndex); + break; + case ODM_RATEMCS12: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x0000007f, PowerIndex); + break; + case ODM_RATEMCS13: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x00007f00, PowerIndex); + break; + case ODM_RATEMCS14: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x007f0000, PowerIndex); + break; + case ODM_RATEMCS15: + ODM_SetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x7f000000, PowerIndex); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); + break; + } + } else + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid RF path!!\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8197f(): Path-%d Rate index 0x%x = 0x%x\n", + Path, HwRate, PowerIndex)); + return TRUE; +} + +u1Byte +config_phydm_read_txagc_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u1Byte readBack_data; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + /* Error handling */ + if ((Path > ODM_RF_PATH_B) || (HwRate > ODM_RATEMCS15)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8197f(): unsupported path (%d)\n", Path)); + return INVALID_TXAGC_DATA; + } + + if (Path == ODM_RF_PATH_A) { + switch (HwRate) { + case ODM_RATE1M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_CCK1_Mcs32, 0x00007f00); + break; + case ODM_RATE2M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x00007f00); + break; + case ODM_RATE5_5M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x007f0000); + break; + case ODM_RATE11M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x7f000000); + break; + + case ODM_RATE6M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x0000007f); + break; + case ODM_RATE9M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x00007f00); + break; + case ODM_RATE12M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x007f0000); + break; + case ODM_RATE18M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate18_06, 0x7f000000); + break; + case ODM_RATE24M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x0000007f); + break; + case ODM_RATE36M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x00007f00); + break; + case ODM_RATE48M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x007f0000); + break; + case ODM_RATE54M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Rate54_24, 0x7f000000); + break; + + case ODM_RATEMCS0: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x0000007f); + break; + case ODM_RATEMCS1: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x00007f00); + break; + case ODM_RATEMCS2: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x007f0000); + break; + case ODM_RATEMCS3: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs03_Mcs00, 0x7f000000); + break; + case ODM_RATEMCS4: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x0000007f); + break; + case ODM_RATEMCS5: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x00007f00); + break; + case ODM_RATEMCS6: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x007f0000); + break; + case ODM_RATEMCS7: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs07_Mcs04, 0x7f000000); + break; + + case ODM_RATEMCS8: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x0000007f); + break; + case ODM_RATEMCS9: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x00007f00); + break; + case ODM_RATEMCS10: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x007f0000); + break; + case ODM_RATEMCS11: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs11_Mcs08, 0x7f000000); + break; + case ODM_RATEMCS12: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x0000007f); + break; + case ODM_RATEMCS13: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x00007f00); + break; + case ODM_RATEMCS14: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x007f0000); + break; + case ODM_RATEMCS15: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_A_Mcs15_Mcs12, 0x7f000000); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); + break; + } + } else if (Path == ODM_RF_PATH_B) { + switch (HwRate) { + case ODM_RATE1M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x00007f00); + break; + case ODM_RATE2M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x007f0000); + break; + case ODM_RATE5_5M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK1_55_Mcs32, 0x7f000000); + break; + case ODM_RATE11M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_CCK11_A_CCK2_11, 0x0000007f); + break; + + case ODM_RATE6M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x0000007f); + break; + case ODM_RATE9M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x00007f00); + break; + case ODM_RATE12M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x007f0000); + break; + case ODM_RATE18M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate18_06, 0x7f000000); + break; + case ODM_RATE24M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x0000007f); + break; + case ODM_RATE36M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x00007f00); + break; + case ODM_RATE48M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x007f0000); + break; + case ODM_RATE54M: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Rate54_24, 0x7f000000); + break; + + case ODM_RATEMCS0: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x0000007f); + break; + case ODM_RATEMCS1: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x00007f00); + break; + case ODM_RATEMCS2: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x007f0000); + break; + case ODM_RATEMCS3: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs03_Mcs00, 0x7f000000); + break; + case ODM_RATEMCS4: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x0000007f); + break; + case ODM_RATEMCS5: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x00007f00); + break; + case ODM_RATEMCS6: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x007f0000); + break; + case ODM_RATEMCS7: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs07_Mcs04, 0x7f000000); + break; + + case ODM_RATEMCS8: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x0000007f); + break; + case ODM_RATEMCS9: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x00007f00); + break; + case ODM_RATEMCS10: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x007f0000); + break; + case ODM_RATEMCS11: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs11_Mcs08, 0x7f000000); + break; + case ODM_RATEMCS12: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x0000007f); + break; + case ODM_RATEMCS13: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x00007f00); + break; + case ODM_RATEMCS14: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x007f0000); + break; + case ODM_RATEMCS15: + readBack_data = ODM_GetBBReg(pDM_Odm, rTxAGC_B_Mcs15_Mcs12, 0x7f000000); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid HWrate!\n")); + break; + } + } else + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("Invalid RF path!!\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8197f(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data)); + return readBack_data; +} + +BOOLEAN +config_phydm_switch_channel_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u4Byte rf_reg18; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f()====================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): disable PHY API for debug!!\n")); + return TRUE; + } + + rf_reg18 = config_phydm_read_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8197f(rf_reg18); + + /* Switch band and channel */ + if (central_ch <= 14) { + /* 2.4G */ + /*table selection*/ + pDM_DigTable->agcTableIdx = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV2_11N, BIT12|BIT11|BIT10|BIT9); + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); + rf_reg18 = (rf_reg18|central_ch); + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Fail to switch band (ch: %d)\n", central_ch)); + return FALSE; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); + if (pDM_Odm->RFType > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_B, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8197f(): Success to switch channel (ch: %d)\n", central_ch)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_bandwidth_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + u4Byte rf_reg18; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f()===================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): disable PHY API for debug!!\n")); + return TRUE; + } + + /* Error handling */ + if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return FALSE; + } + + rf_reg18 = config_phydm_read_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8197f(rf_reg18); + + /* Switch bandwidth */ + switch (bandwidth) { + case ODM_BW20M: + { + /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 20M */ + ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); + + /* ADC clock = 160M clock for BW20*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x4); + + /* DAC clock = 160M clock for BW20 = 3'b101*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x5); + + /* ADC buffer clock 0xca4[27:26] = 2'b10*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT11 | BIT10); + break; + } + case ODM_BW40M: + { + /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 1 for 40M */ + ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x1); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x1); + + /* ADC clock = 160M clock for BW40 no need to setting, it will be setting in PHY_REG */ + + /* DAC clock = 160M clock for BW20 = 3'b101*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x5); + + /* ADC buffer clock 0xca4[27:26] = 2'b10*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); + + /* CCK primary channel */ + if (primary_ch_idx == 1) + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT4, primary_ch_idx); + else + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT4, 0); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); + rf_reg18 = (rf_reg18|BIT11); + break; + } + case ODM_BW5M: + { + /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 5M */ + ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x1); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); + + /* ADC clock = 40M clock for BW5 = 3'b010*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x2); + + /* DAC clock = 20M clock for BW20 = 3'b110*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x6); + + /* ADC buffer clock 0xca4[27:26] = 2'b10*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + case ODM_BW10M: + { + /* Small BW([31:30]) = 0, rf mode(800[0], 900[0]) = 0 for 10M */ + ODM_SetBBReg(pDM_Odm, ODM_REG_SMALL_BANDWIDTH_11N, (BIT31|BIT30), 0x2); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, BIT0, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_PAGE9_11N, BIT0, 0x0); + + /* ADC clock = 80M clock for BW5 = 3'b011*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_RXCK_RFMOD, (BIT18|BIT17|BIT16), 0x3); + + /* DAC clock = 160M clock for BW20 = 3'b110*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT14|BIT13|BIT12), 0x4); + + /* ADC buffer clock 0xca4[27:26] = 2'b10*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, (BIT27|BIT26), 0x2); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + } + + /* Write RF register */ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_A, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->RFType > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8197f(pDM_Odm, ODM_RF_PATH_B, ODM_REG_CHNBW_11N, bRFRegOffsetMask, rf_reg18); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); + return FALSE; + } + + /* Modify RX DFIR parameters */ + phydm_RxDfirParByBw_8197f(pDM_Odm, bandwidth); + + /* Modify CCA parameters */ + phydm_CcaParByBw_8197f(pDM_Odm, bandwidth); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8197f(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_channel_bw_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + u1Byte eRFPath = 0; + u4Byte RFValToWR , RFTmpVal, BitShift, BitMask; + + /* Switch band */ + /*97F no need*/ + + /* Switch channel */ + if (config_phydm_switch_channel_8197f(pDM_Odm, central_ch) == FALSE) + return FALSE; + + /* Switch bandwidth */ + if (config_phydm_switch_bandwidth_8197f(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) + return FALSE; + + return TRUE; +} + +BOOLEAN +config_phydm_trx_mode_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ) +{ + BOOLEAN rf_reg_status = TRUE; + u1Byte IGI; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f()=====================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): disable PHY API for debug!!\n")); + return TRUE; + } + + if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Wrong TX setting (TX: 0x%x)\n", TxPath)); + return FALSE; + } + + if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Wrong RX setting (RX: 0x%x)\n", RxPath)); + return FALSE; + } + + /* RF mode of path-A and path-B */ + /* OFDM Tx and Rx path setting */ + if (TxPath == (ODM_RF_A|ODM_RF_B)) + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x81121313); + else if (TxPath & ODM_RF_A) + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x81121311); + else + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x82221322); + + if (RxPath == (ODM_RF_A|ODM_RF_B)) { + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x33); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x3); + } else if (RxPath & ODM_RF_A) { + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x11); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x1); + } else { + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11N, bMaskByte0, 0x22); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_ANT_11N, BIT3|BIT2|BIT1|BIT0, 0x2); + } + + /* CCK Tx and Rx path setting*/ + if (TxPath & ODM_RF_A) + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0x8); + else + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0x4); + + if (RxPath == (ODM_RF_A|ODM_RF_B)) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x4); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x1); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x1); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); + } else if (RxPath & ODM_RF_A) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); + } else { + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, BIT27|BIT26|BIT25|BIT24, 0x5); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT18, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT22, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0x0); + } + + if(bTx2Path) { + /*OFDM tx setting*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_TX_PATH_11N, BIT27|BIT26|BIT25|BIT24|bMaskL3Byte, 0x83321333); + /*CCK tx setting*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT31, 0x0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANT_SEL_11N, bMaskH4Bits, 0xc); + + /*Paath_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff, 0x08000); /*Select Standby mode 0x30=0x08000*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff, 0x0005f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0x01042); /*Enable TXIQGEN in standby mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff, 0x0004f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0x71fc2); /*Enable TXIQGEN in RX mode*/ /*Path_B*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff, 0x08000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff, 0x00050); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff, 0x01042); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff, 0x18000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff, 0x00040); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff, 0x71fc2); - } - - /* Update TXRX antenna status for PHYDM */ - pDM_Odm->TXAntStatus = (TxPath & 0x3); - pDM_Odm->RXAntStatus = (RxPath & 0x3); - - /* Modify CCA parameters */ - phydm_CcaParByRxPath_8197f(pDM_Odm); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath)); - return TRUE; -} - -BOOLEAN -config_phydm_parameter_8197f_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ) -{ - if (type == ODM_PRE_SETTING) { - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT25|BIT24), 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Pre setting: disable OFDM and CCK block\n")); - } else if (type == ODM_POST_SETTING) { - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT25|BIT24), 0x3); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Post setting: enable OFDM and CCK block\n")); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Wrong type!!\n")); - return FALSE; - } - - return TRUE; -} - -/* ======================================================================== */ -#endif /* RTL8197F_SUPPORT == 1 */ - + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff, 0x08000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff, 0x00050); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff, 0x01042); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff, 0x18000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff, 0x00040); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff, 0x71fc2); + } + + /* Update TXRX antenna status for PHYDM */ + pDM_Odm->TXAntStatus = (TxPath & 0x3); + pDM_Odm->RXAntStatus = (RxPath & 0x3); + + /* Modify CCA parameters */ + phydm_CcaParByRxPath_8197f(pDM_Odm); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8197f(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath)); + return TRUE; +} + +BOOLEAN +config_phydm_parameter_8197f_init( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ) +{ + if (type == ODM_PRE_SETTING) { + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT25|BIT24), 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Pre setting: disable OFDM and CCK block\n")); + } else if (type == ODM_POST_SETTING) { + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_CTRL_11N, (BIT25|BIT24), 0x3); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Post setting: enable OFDM and CCK block\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_8197f_init(): Wrong type!!\n")); + return FALSE; + } + + return TRUE; +} + +/* ======================================================================== */ +#endif /* RTL8197F_SUPPORT == 1 */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.h b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.h index e77b126abff..322aba7af58 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_hal_api8197f.h @@ -1,115 +1,115 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_PHYDM_API_H_8197F__ -#define __INC_PHYDM_API_H_8197F__ - -#if (RTL8197F_SUPPORT == 1) - -#define PHY_CONFIG_VERSION_8197F "R5.V4.0" /*2015.08.15, move init procedure to phydm(user guide version: R5, API version: V2.9)*/ - -#define INVALID_RF_DATA 0xffffffff -#define INVALID_TXAGC_DATA 0xff - -#define config_phydm_read_rf_check_8197f(data) (data != INVALID_RF_DATA) -#define config_phydm_read_txagc_check_8197f(data) (data != INVALID_TXAGC_DATA) - -VOID -phydm_init_hw_info_by_rfe_type_8197f( - IN PDM_ODM_T pDM_Odm - ); - -u4Byte -config_phydm_read_rf_reg_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - -BOOLEAN -config_phydm_write_rf_reg_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -BOOLEAN -config_phydm_write_txagc_8197f( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -u1Byte -config_phydm_read_txagc_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -BOOLEAN -config_phydm_switch_band_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_channel_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_bandwidth_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_switch_channel_bw_8197f( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_trx_mode_8197f( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ); - -BOOLEAN -config_phydm_parameter_8197f_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ); - - -#endif /* RTL8197F_SUPPORT == 1 */ -#endif /* __INC_PHYDM_API_H_8197F__ */ - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_PHYDM_API_H_8197F__ +#define __INC_PHYDM_API_H_8197F__ + +#if (RTL8197F_SUPPORT == 1) + +#define PHY_CONFIG_VERSION_8197F "R5.V4.0" /*2015.08.15, move init procedure to phydm(user guide version: R5, API version: V2.9)*/ + +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff + +#define config_phydm_read_rf_check_8197f(data) (data != INVALID_RF_DATA) +#define config_phydm_read_txagc_check_8197f(data) (data != INVALID_TXAGC_DATA) + +VOID +phydm_init_hw_info_by_rfe_type_8197f( + IN PDM_ODM_T pDM_Odm + ); + +u4Byte +config_phydm_read_rf_reg_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +BOOLEAN +config_phydm_write_rf_reg_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +BOOLEAN +config_phydm_write_txagc_8197f( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +u1Byte +config_phydm_read_txagc_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +BOOLEAN +config_phydm_switch_band_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_channel_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_bandwidth_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_switch_channel_bw_8197f( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_trx_mode_8197f( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ); + +BOOLEAN +config_phydm_parameter_8197f_init( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ); + + +#endif /* RTL8197F_SUPPORT == 1 */ +#endif /* __INC_PHYDM_API_H_8197F__ */ + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.c b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.c index 25311f253b4..6c6fceb8c2a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.c @@ -1,4047 +1,4047 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - -/*---------------------------Define Local Constant---------------------------*/ -#define DPK_VER_8197F 0x8 /*8197F DPK version: 0x7 20180731*/ - -/*---------------------------Define Local Constant---------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8197F( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - - PHY_IQCalibrate_8197F(pDM_Odm, FALSE); - -} -#else -/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8197F, but DoIQK_8197F and PHY_IQCalibrate_8197F have different arguments*/ -void DoIQK_8197F( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ -#if 1 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bReCovery = (BOOLEAN) DeltaThermalIndex; - - PHY_IQCalibrate_8197F(pDM_Odm, bReCovery); -#endif -} -#endif - -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 /*ms*/ - -VOID -do_dpk_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN is2T, - u1Byte k - -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u1Byte i = 0; - u4Byte tmp_rf_a_18, tmp_rf_b_18; - - if (!((pDM_Odm->RFEType == 0) || (pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 3))) - { - printk("[DPK] Skip DPK due to RFE type != 0/2/3\n"); - return; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK Start (Ver: 0x%x) !!!!\n", DPK_VER_8197F)); - - tmp_rf_a_18 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff); - tmp_rf_b_18 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff); - -#if 1 - switch (k) - { - case 0: /*channel 3*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc03); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc03); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH3!!!!\n")); - break; - - case 1: /*channel 7*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc07); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc07); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH7!!!!\n")); - break; - - case 2: /*channel 11*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc0b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc0b); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH11!!!!\n")); - break; - } -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0x18@ path_A = 0x%x, path_B = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask), ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask))); - - for (i = 0; i < 6; i++) - { - //printk("[DPK] Retry DPK i=%d\n", i); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Retry DPK i=%d\n", i)); - if (phy_dpcalibrate_8197f(pDM_Odm, TRUE, k) == 1) - break; - } - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, tmp_rf_a_18); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, tmp_rf_b_18); - - - if ((pDM_Odm->RFCalibrateInfo.bDPPathAOK == 1) && (pDM_Odm->RFCalibrateInfo.bDPPathBOK == 1) && k == 2) - phy_lut_sram_write_8197f(pDM_Odm); - else - phy_dpk_enable_disable_8197f(pDM_Odm, false); -} - - -VOID -phy_dpk_track_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - prtl8192cd_priv priv = pDM_Odm->priv; - s1Byte pwsf_a, pwsf_b; - u1Byte offset, delta_DPK, is_increase, ThermalValue = 0, ThermalValue_DPK_AVG_count = 0, i = 0, k = 0; - u4Byte ThermalValue_DPK_AVG = 0; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - if (priv->pshare->mp_tx_dpk_tracking == FALSE) - return; - } -#endif - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_DPK) - pDM_Odm->RFCalibrateInfo.ThermalValue_DPK = priv->pmib->dot11RFEntry.ther; - - /* calculate average thermal meter */ - - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_8197F, BIT17 | BIT16, 0x3); /*thermal meter trigger*/ - ODM_delay_ms(1); - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_8197F, 0xfc00); /*get thermal meter*/ - - pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index++; - - if (pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index == Thermal_DPK_AVG_num) /*Average times */ - pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index = 0; - - for (i = 0; i < Thermal_DPK_AVG_num; i++) { - if (pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[i]) { - ThermalValue_DPK_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[i]; - ThermalValue_DPK_AVG_count++; - } - } - - if (ThermalValue_DPK_AVG_count) {/*Calculate Average ThermalValue after average enough times*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[DPK_track] ThermalValue_DPK_AVG=0x%x(%d) ThermalValue_DPK_AVG_count = %d\n" - , ThermalValue_DPK_AVG, ThermalValue_DPK_AVG, ThermalValue_DPK_AVG_count)); - - ThermalValue = (u1Byte)(ThermalValue_DPK_AVG / ThermalValue_DPK_AVG_count); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[DPK_track] AVG Thermal Meter = 0x%X(%d), PG Thermal Meter = 0x%X(%d)\n", - ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); - } - - - delta_DPK = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); - - offset = delta_DPK / DPK_THRESHOLD_8197F; - - k = phy_dpk_channel_transfer_8197f(pDM_Odm); - - pwsf_a = pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k]; - pwsf_b = pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] delta_DPK = %d, offset = %d, track direction is %s\n", delta_DPK, offset, (is_increase ? "Plus" : "Minus"))); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_a before tracking is 0x%x, pwsf_b before tracking is 0x%x\n", pwsf_a, pwsf_b)); - - if ((pwsf_a>>4) != 0) - pwsf_a = (pwsf_a | 0xe0); - - if ((pwsf_b>>4) != 0) - pwsf_b = (pwsf_b | 0xe0); - - if (is_increase) { - - pwsf_a = pwsf_a + offset; - pwsf_b = pwsf_b + offset; - - } else { - - pwsf_a = pwsf_a - offset; - pwsf_b = pwsf_b - offset; - - } - - ODM_SetBBReg(pDM_Odm, 0xb68, 0x00007C00, pwsf_a); - ODM_SetBBReg(pDM_Odm, 0xb6c, 0x00007C00, pwsf_b); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_a after tracking is %d (0x%x), 0xb68 = 0x%x\n", pwsf_a, (pwsf_a & 0x1f), ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_b after tracking is %d (0x%x), 0xb6c = 0x%x\n", pwsf_b, (pwsf_b & 0x1f), ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord))); - -} - - - -VOID -phy_dpkoff_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - /*Path A*/ - ODM_Write1Byte(pDM_Odm, 0xb00, 0x18); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_delay_ms(10); - - /*Path B*/ - ODM_Write1Byte(pDM_Odm, 0xb70, 0x18); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_delay_ms(10); - -} - -VOID -phy_dpkon_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - /*Path A*/ - ODM_Write1Byte(pDM_Odm, 0xb00, 0x98); - ODM_Write1Byte(pDM_Odm, 0xb07, 0xF7); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_delay_ms(10); - - ODM_Write1Byte(pDM_Odm, 0xb07, 0x77); - ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x4c104c10); /*1.5dB*/ - - /*Path B*/ - ODM_Write1Byte(pDM_Odm, 0xb70, 0x98); - ODM_Write1Byte(pDM_Odm, 0xb77, 0xF7); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_delay_ms(10); - - ODM_Write1Byte(pDM_Odm, 0xb77, 0x77); - ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x4c104c10); /*1.5dB*/ - -} - - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathA_IQK_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN configPathB -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte regEAC, regE94, regE9C, regEA4, tmp; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path A TXIQK start!====================\n")); - - /*=============================TXIQK setting=============================*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - if (pDM_Odm->ExtPA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003ff, 0x71); - } else if (pDM_Odm->ExtPA == 0 && pDM_Odm->CutVersion != ODM_CUT_A) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003ff, 0xe8); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x56 at Path A TXIQK = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask))); - - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-A IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if (pDM_Odm->ExtPA) - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214400f); - else - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140002); - } else - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214000f); - - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28140000); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00e62911); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - /*reload 0xdf and CCK_IND off */ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, BIT14, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] path A TXIQK is not success\n")); - return result; - -} - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathA_RxIQK_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN configPathB -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, RXPGA; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RxIQK start!\n")); - - /* =============================Get TXIMR setting=============================*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path A RXIQK step1!====================\n")); - - - /*modify RXIQK mode table*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); - - if (pDM_Odm->ExtPA) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xa8000); - else - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xae000); - } - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - /*Restore RXPGA*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, RXPGA); - } - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK step1 is not success\n")); - - - return result; - - } - - u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - /* =============================RXIQK setting=============================*/ - /*modify RXIQK mode table*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]====================Path A RXIQK step2!====================\n")); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK modify RXIQK mode table 2!\n"));*/ - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - /*PA/PAD control by 0x56, and set = 0x0*/ - if (pDM_Odm->CutVersion == ODM_CUT_A) { - - RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); - - if (pDM_Odm->ExtPA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x3); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x28000); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xae000); - } - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x3); - } - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); - - if (pDM_Odm->ExtPA == 1 && pDM_Odm->CutVersion == ODM_CUT_A) - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170c00); - else - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe3c(RX_PI_Data)= 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe3c, bMaskDWord)));*/ - - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - /*PA/PAD controlled by 0x0 & Restore RXPGA*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); - if (pDM_Odm->CutVersion == ODM_CUT_A) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, RXPGA); - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000) >> 16) != 0x132) && - (((regEAC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RxIQK step2 is not success!!\n")); - return result; - - - -} - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathB_IQK_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte regEAC, regEB4, regEBC; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B TXIQK start!====================\n")); - - /* =============================TXIQK setting=============================*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*path A to SI mode to avoid RF go to shot-down mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - if (pDM_Odm->ExtPA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003ff, 0x71); - } else if (pDM_Odm->ExtPA == 0 && pDM_Odm->CutVersion != ODM_CUT_A) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003ff, 0xe8); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x56 at Path B TXIQK = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask))); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if (pDM_Odm->ExtPA) - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8214400f); - else - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140002); - } else - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8214000f); - - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28140000); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00e62911); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path B LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - /*Path A back to PI mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - /*reload 0xdf and CCK_IND off */ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, BIT14, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x0); - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B TXIQK is not success\n")); - return result; - -} - - - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathB_RxIQK_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN configPathB -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp, RXPGA; - u1Byte result = 0x00; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RxIQK start!\n")); - - /* =============================Get TXIMR setting=============================*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B RXIQK step1!====================\n")); - /*modify RXIQK mode table*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK modify RXIQK mode table!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); - - if (pDM_Odm->ExtPA) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xa8000); - else - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xae000); - } - - /*path A to SI mode to avoid RF go to shot-down mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - /*path-B IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, Path B LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - /*Restore RXPGA*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, RXPGA); - } - - /*Path A back to PI mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - - if (!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000) >> 16) != 0x142) && - (((regEBC & 0x03FF0000) >> 16) != 0x42)) - result |= 0x01; - else { /*if Tx not OK, ignore Rx*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK step1 is not success\n")); - return result; - - } - - u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - /* =============================RXIQK setting=============================*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B RXIQK step2!====================\n")); - - /*modify RXIQK mode table*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B RXIQK modify RXIQK mode table 2!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - /*PA/PAD control by 0x56, and set = 0x0*/ - if (pDM_Odm->CutVersion == ODM_CUT_A) { - - RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); - - if (pDM_Odm->ExtPA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x3); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x28000); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xae000); - } - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x3); - } - - /*path A to SI mode to avoid RF go to shot-down mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-B IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c0c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82170000); - - if (pDM_Odm->ExtPA == 1 && pDM_Odm->CutVersion == ODM_CUT_A) - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28170c00); - else - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28170000); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe5c(RX_PI_Data)= 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe5c, bMaskDWord))); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, Path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ - ODM_delay_ms(IQK_DELAY_TIME_97F); - - - /*Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); - - /*PA/PAD controlled by 0x0 & Restore RXPGA*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x0); - if (pDM_Odm->CutVersion == ODM_CUT_A) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, RXPGA); - - /*Path A back to PI mode*/ - ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); - - if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ - (((regEC4 & 0x03FF0000) >> 16) != 0x132) && - (((regECC & 0x03FF0000) >> 16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK step2 is not success!!\n")); - return result; - - -} - -VOID -_PHY_PathAFillIQKMatrix_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN bIQKOK, - s4Byte result[][8], - u1Byte final_candidate, - BOOLEAN bTxOnly -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, Oldval_0); - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - - TX0_A = (X * 0x100) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX0_A = 0x%x\n", X, TX0_A)); - - ODM_SetBBReg(pDM_Odm, 0xe30, 0x3FF00000, TX0_A); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX0_C = (Y * 0x100) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, 0xe20, 0x000003C0, ((TX0_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, 0xe20, 0x0000003F, (TX0_C & 0x3F)); -#else - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); -#endif - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] _PHY_PathAFillIQKMatrix_97F only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; - #endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -_PHY_PathBFillIQKMatrix_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN bIQKOK, - s4Byte result[][8], - u1Byte final_candidate, - BOOLEAN bTxOnly /*do Tx only*/ -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, Oldval_1); - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - - TX1_A = (X * 0x100) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - - ODM_SetBBReg(pDM_Odm, 0xe50, 0x3FF00000, TX1_A); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * 0x100) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, 0xe24, 0x000003C0, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, 0xe24, 0x0000003F, (TX1_C & 0x3F)); -#else - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); -#endif - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] _PHY_PathBFillIQKMatrix_97F only Tx OK\n")); - return; - } - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, 0xca8, 0x000000F0, reg); - } -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -#if 0 - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.*/ - if (pMgntInfo->init_adpt_in_progress == TRUE) { - ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if (Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) { - ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -#endif - return TRUE; -} -#endif - - -VOID -_PHY_SaveADDARegisters_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte ADDAReg, - pu4Byte ADDABackup, - u4Byte RegisterNum -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Save ADDA parameters.\n"));*/ - for (i = 0 ; i < RegisterNum ; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); -} - - -VOID -_PHY_SaveMACRegisters_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte MACReg, - pu4Byte MACBackup -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Save MAC parameters.\n"));*/ - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte ADDAReg, - pu4Byte ADDABackup, - u4Byte RegiesterNum -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); -} - -VOID -_PHY_ReloadMACRegisters_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte MACReg, - pu4Byte MACBackup -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Reload MAC parameters !\n")); - #if 0 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); - #else - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); - #endif -} - -VOID -_PHY_PathADDAOn_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte ADDAReg, - BOOLEAN isPathAOn, - BOOLEAN is2T -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte pathOn; - u4Byte i; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ADDA ON.\n"));*/ - - ODM_SetBBReg(pDM_Odm, 0xd94, 0x00ff0000, 0xff); - ODM_SetBBReg(pDM_Odm, 0xe70, bMaskDWord, 0x00400040); - -#if 0 - pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; - if (FALSE == is2T) { - pathOn = 0x0fc01616; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); - } else - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - - for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); -#endif -} - -VOID -_PHY_MACSettingCalibration_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - pu4Byte MACReg, - pu4Byte MACBackup -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*u4Byte i = 0;*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif -/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));*/ - -#if 0 - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT3))); - - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT5))); -#endif - - #if 1 - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); - #else - ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); - ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); - ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); - #endif - - -} - -VOID -_PHY_PathAStandBy_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); - /*ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);*/ - ODM_SetRFReg(pDM_Odm, 0x0, 0x0, bRFRegOffsetMask, 0x10000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PathBStandBy_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-B standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, 0x1, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - - -VOID -_PHY_PIModeSwitch_97F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN PIMode -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte mode; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - /*DM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));*/ - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - s4Byte result[][8], - u1Byte c1, - u1Byte c2 -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte i, j, diff, SimularityBitMap, bound = 0; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; /*for path A and path B*/ - BOOLEAN bResult = TRUE; -/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ -/*#else*/ - BOOLEAN is2T = TRUE; -/*#endif*/ - - s4Byte tmp1 = 0, tmp2 = 0; - - if (is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ===> IQK:phy_SimularityCompare_8197F c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i] + result[c1][i + 1] == 0) - final_candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - final_candidate[(i / 4)] = c1; - else - SimularityBitMap = SimularityBitMap | (1 << i); - } else - SimularityBitMap = SimularityBitMap | (1 << i); - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] phy_SimularityCompare_8197F SimularityBitMap %x !!!\n", SimularityBitMap)); - - if (SimularityBitMap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (final_candidate[i] != 0xFF) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[final_candidate[i]][j]; - bResult = FALSE; - } - } - return bResult; - - } else { - - if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ - for (i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ - for (i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - } - - if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ - for (i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - - } - - if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ - for (i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - } - - return FALSE; - } - -} - -VOID -_phy_iqk_check_97f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte txa_fail, rxa_fail, txb_fail, rxb_fail; - - - txa_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(28)); - rxa_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(27)); - txb_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(31)); - rxb_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(30)); - - if (txa_fail == 1) - panic_printk("[IQK] path A TXIQK load default value!!!\n"); - if (rxa_fail == 1) - panic_printk("[IQK] path A RXIQK load default value!!!\n"); - if (txb_fail == 1) - panic_printk("[IQK] path B TXIQK load default value!!!\n"); - if (rxb_fail == 1) - panic_printk("[IQK] path B RXIQK load default value!!!\n"); - -} - - - -VOID -phy_IQCalibrate_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - s4Byte result[][8], - u1Byte t, - BOOLEAN is2T -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - u4Byte i, DAC_gain_A, DAC_gain_B; - u1Byte PathAOK = 0, PathBOK = 0; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - 0xd94, rRx_Wait_CCA - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - /*since 92C & 92D have the different define in IQK_BB_REG*/ - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - 0x930, 0x934, - 0x93c, rCCK0_AFESetting - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) - u4Byte retryCount = 2; - #else - #if MP_DRIVER - const u4Byte retryCount = 9; - #else - const u4Byte retryCount = 2; - #endif - #endif - - /*Note: IQ calibration must be performed after loading*/ - /*PHY_REG.txt,and radio_a,radio_b.txt*/ - - /*u4Byte bbvalue;*/ - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 2; - #endif - #endif - -#if 0 - /*RF setting :RXBB leave power saving*/ - if (pDM_Odm->CutVersion != ODM_CUT_A) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00002, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00002, 0x1); - } -#endif - /*Save and set DAC gain for IQK*/ - DAC_gain_A = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask); - DAC_gain_B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Ori_0x55 at Path A = 0x%x\n", DAC_gain_A)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Ori_0x55 at Path B = 0x%x\n", DAC_gain_B)); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x000e0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, 0x000e0, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Set_0x55 at Path A = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Set_0x55 at Path B = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask))); - - if (t == 0) { - /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ - /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ - - /*Save ADDA parameters, turn Path A ADDA on*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_97F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - _PHY_SaveADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn_97F(pAdapter, ADDA_REG, TRUE, is2T); - #else - _PHY_PathADDAOn_97F(pDM_Odm, ADDA_REG, TRUE, is2T); - #endif - - - /*BB setting*/ - /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x6f005403); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000804e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x04203400); - - -#if 1 - /*FEM off when ExtPA or ExtLNA= 1*/ - if (pDM_Odm->ExtPA || pDM_Odm->ExtLNA) { - ODM_SetBBReg(pDM_Odm, 0x930, bMaskDWord, 0xFFFF77FF); - ODM_SetBBReg(pDM_Odm, 0x934, bMaskDWord, 0xFFFFFFF7); - ODM_SetBBReg(pDM_Odm, 0x93c, bMaskDWord, 0xFFFF777F); - } -#endif - - -/* if(is2T) {*/ -/* ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);*/ -/* ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);*/ -/* }*/ - - /*MAC settings*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #else - _PHY_MACSettingCalibration_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - #endif - - /* IQ calibration setting*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - -/*path A TXIQK*/ - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8197F(pAdapter, is2T); - #else - PathAOK = phy_PathA_IQK_8197F(pDM_Odm, is2T); - #endif - if (PathAOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A TXIQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A TXIQK Fail!!\n")); - result[t][0] = 0x100; - result[t][1] = 0x0; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -/*path A RXIQK*/ - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK_97F(pAdapter, is2T); - #else - PathAOK = phy_PathA_RxIQK_97F(pDM_Odm, is2T); - #endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK Success!!\n")); - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK Fail!!\n")); - result[t][2] = 0x100; - result[t][3] = 0x0; - } - } - - if (0x00 == PathAOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A IQK failed!!\n")); - - #endif - - if (is2T) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy_97F(pAdapter); - - /*Turn ADDA on*/ - _PHY_PathADDAOn_97F(pAdapter, ADDA_REG, FALSE, is2T); - #else - _PHY_PathAStandBy_97F(pDM_Odm); - - /*Turn ADDA on*/ - _PHY_PathADDAOn_97F(pDM_Odm, ADDA_REG, FALSE, is2T); - #endif - - /*IQ calibration setting*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - -/*path B Tx IQK*/ - #if 1 - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8197F(pAdapter); - #else - PathBOK = phy_PathB_IQK_8197F(pDM_Odm); - #endif - - if (PathBOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B TXIQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TXIQK Fail!!\n")); - result[t][4] = 0x100; - result[t][5] = 0x0; - } - #if 0 - else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ - RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; - } - #endif - } - #endif - -/*path B RX IQK*/ - #if 1 - - for (i = 0 ; i < retryCount ; i++) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK_97F(pAdapter, is2T); - #else - PathBOK = phy_PathB_RxIQK_97F(pDM_Odm, is2T); - #endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK Success!!\n")); - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; - break; - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); - result[t][6] = 0x100; - result[t][7] = 0x0; - } - } - - if (0x00 == PathBOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - - #endif - } - - /*Back to BB mode, load original value*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { - - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_97F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #else - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - #endif - - /*Allen initial gain 0xc50*/ - /* Restore RX initial gain*/ - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } -#if 0 - /*RF setting :RXBB enter power saving*/ - if (pDM_Odm->CutVersion != ODM_CUT_A) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00002, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00002, 0x0); - } -#endif - #if 0 - /*load 0xe30 IQC default value*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - #endif - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] phy_IQCalibrate_8197F() <==\n")); - - /*reload DAC gain for K-free*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, DAC_gain_A); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask, DAC_gain_B); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Restore_0x55 at Path A = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Restore_0x55 at Path B = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask))); -} - -VOID -phy_LCCalibrate_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN is2T -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u1Byte tmpReg; - u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal, cnt; - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - /*Check continuous TX and Packet TX*/ - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - - /*backup RF0x18*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - /*Start LCK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - - ODM_delay_ms(10); - } - - /*Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - - /*Restore original situation*/ - if ((tmpReg&0x70) != 0) { - /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - } else { - /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } - -} - - -VOID -PHY_IQCalibrate_8197F( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN bReCovery -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif/*(MP_DRIVER == 1)*/ - #endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - - s4Byte result[4][8]; /*last is final result*/ - u1Byte i, final_candidate, Indexforchannel; - u1Byte channelToIQK = 7; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, 0xca8, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta - }; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #else - prtl8192cd_priv priv = pDM_Odm->priv; - - #ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } - #endif - /* if (priv->pshare->IQK_92E_done)*/ - /* bReCovery= 1; */ - /* priv->pshare->IQK_92E_done = 1;*/ - #endif - - #if 1//(DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - - #if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ - if (bSingleTone || bCarrierSuppression) - return; - - #ifdef DISABLE_BB_RF - return; - #endif - - if (pRFCalibrateInfo->bIQKInProgress) - return; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) - #else /*for ODM_WIN*/ - if (bReCovery && - (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ - #endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK] PHY_IQCalibrate_97F: Return due to bReCovery!\n")); -#if 0 - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #endif -#endif - return; - } - -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - /*turn off DPK*/ - phy_dpkoff_8197f(pDM_Odm); -#endif - - /*check IC cut and IQK version*/ - if (pDM_Odm->CutVersion == ODM_CUT_A) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is A\n")); - else if (pDM_Odm->CutVersion == ODM_CUT_B) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is B\n")); - else if (pDM_Odm->CutVersion == ODM_CUT_C) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is C\n")); - else if (pDM_Odm->CutVersion == ODM_CUT_D) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is D\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK Version is v2.6 (20170109)\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] PHY Version is v%d \n", ODM_GetHWImgVersion(ODMPTR))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ExtPA = %d, ExtLNA = %d\n", pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK Start!!!\n")); - priv->pshare->IQK_total_cnt++; - -#if 0 - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); -#endif - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[3][i] = 0x100; - else - result[3][i] = 0; - } - - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_IQCalibrate_8197F(pAdapter, result, i, TRUE); - - - #else - - - phy_IQCalibrate_8197F(pDM_Odm, result, i, TRUE); - #endif - - - if (i == 1) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8197F(pAdapter, result, 0, 1); - #else - is12simular = phy_SimularityCompare_8197F(pDM_Odm, result, 0, 1); - #endif - - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8197F(pAdapter, result, 0, 2); - #else - is13simular = phy_SimularityCompare_8197F(pDM_Odm, result, 0, 2); - #endif - - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is13simular final_candidate is %x\n", final_candidate)); - - break; - } - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8197F(pAdapter, result, 1, 2); - #else - is23simular = phy_SimularityCompare_8197F(pDM_Odm, result, 1, 2); - #endif - - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is23simular final_candidate is %x\n", final_candidate)); - } else { -#if 0 - for (i = 0; i < 4; i++) - RegTmp &= result[3][i*2]; - - if (RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; -#endif - final_candidate = 3; - - } - } - } -#if 0 - if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { - for (i = 0; i < 8; i++) { - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[final_candidate][i] = 0x100; - else - result[final_candidate][i] = 0; - } - } -#endif - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - priv->pshare->RegEB4 = pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - priv->pshare->RegEBC = pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] FAIL use default value\n"));*/ - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _phy_iqk_check_97f(pAdapter); - #else - _phy_iqk_check_97f(pDM_Odm); - #endif - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /*X default value*/ - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /*Y default value*/ - priv->pshare->IQK_fail_cnt++; - } - -#if 0 - /*reset TXIQC for DPD*/ - ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000); - ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xe50, bMaskDWord, 0x10000000); - ODM_SetBBReg(pDM_Odm, 0xe24, bMaskDWord, 0x00000000); -#endif - - if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix_97F(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #else - _PHY_PathAFillIQKMatrix_97F(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); - #endif - } - - if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/) { - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathBFillIQKMatrix_97F(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - #else - _PHY_PathBFillIQKMatrix_97F(pDM_Odm, bPathBOK, result, final_candidate, (RegEC4 == 0)); - #endif - } - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); - #else - Indexforchannel = 0; - #endif - -/*To Fix BSOD when final_candidate is 0xff*/ -/*by sherry 20120321*/ - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - /*RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK OK Indexforchannel %d.\n", Indexforchannel)); - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); - #else - _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc80 = 0x%x, 0xc94 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe30 = 0x%x, 0xe20 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xe30, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe20, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc14 = 0x%x, 0xca0 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xca0, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc88 = 0x%x, 0xc9c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc88, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc9c, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe50 = 0x%x, 0xe24 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xe50, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe24, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc1c = 0x%x, 0xca8 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc1c, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xca8, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x58 at Path A = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x58 at Path B = 0x%x\n", - ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK finished\n")); - -#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) - /*trun on DPK*/ - phy_dpkon_8197f(pDM_Odm); -#endif - -} - - -VOID -PHY_LCCalibrate_8197F( - PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif/*(MP_DRIVER == 1)*/ - #endif - - - - - #if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif - - - #ifdef DISABLE_BB_RF - return; - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - #endif - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) */ - if (bSingleTone || bCarrierSuppression) - return; - - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_2T2R(pHalData->VersionID)) - phy_LCCalibrate_8197F(pAdapter, TRUE); - else - #endif - { - /* For 88C 1T1R*/ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8197F(pAdapter, FALSE); - #else - phy_LCCalibrate_8197F(pDM_Odm, FALSE); - #endif - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -phy_path_a_dpk_init_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - /**/ - ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, 0x0001e018); - ODM_SetBBReg(pDM_Odm, 0xb04, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, 0xb28, bMaskDWord, 0x000844aa); - ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, 0x31160200); - - ODM_SetBBReg(pDM_Odm, 0xb30, 0x000fffff, 0x0007bdef); - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); - - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x00021d5f); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x41382e21); - ODM_SetBBReg(pDM_Odm, 0xb0c, bMaskDWord, 0x5b554f48); - ODM_SetBBReg(pDM_Odm, 0xb10, bMaskDWord, 0x6f6b6661); - ODM_SetBBReg(pDM_Odm, 0xb14, bMaskDWord, 0x817d7874); - ODM_SetBBReg(pDM_Odm, 0xb18, bMaskDWord, 0x908c8884); - ODM_SetBBReg(pDM_Odm, 0xb1c, bMaskDWord, 0x9d9a9793); - ODM_SetBBReg(pDM_Odm, 0xb20, bMaskDWord, 0xaaa7a4a1); - ODM_SetBBReg(pDM_Odm, 0xb24, bMaskDWord, 0xb6b3b0ad); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); - - ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, 0x02ce03e8); - ODM_SetBBReg(pDM_Odm, 0xb04, bMaskDWord, 0x01fd024c); - ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x01a101c9); - ODM_SetBBReg(pDM_Odm, 0xb0C, bMaskDWord, 0x016a0183); - ODM_SetBBReg(pDM_Odm, 0xb10, bMaskDWord, 0x01430153); - ODM_SetBBReg(pDM_Odm, 0xb14, bMaskDWord, 0x01280134); - ODM_SetBBReg(pDM_Odm, 0xb18, bMaskDWord, 0x0112011c); - ODM_SetBBReg(pDM_Odm, 0xb1C, bMaskDWord, 0x01000107); - ODM_SetBBReg(pDM_Odm, 0xb20, bMaskDWord, 0x00f200f9); - ODM_SetBBReg(pDM_Odm, 0xb24, bMaskDWord, 0x00e500eb); - ODM_SetBBReg(pDM_Odm, 0xb28, bMaskDWord, 0x00da00e0); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00d200d6); - ODM_SetBBReg(pDM_Odm, 0xb30, bMaskDWord, 0x00c900cd); - ODM_SetBBReg(pDM_Odm, 0xb34, bMaskDWord, 0x00c200c5); - ODM_SetBBReg(pDM_Odm, 0xb38, bMaskDWord, 0x00bb00be); - ODM_SetBBReg(pDM_Odm, 0xb3c, bMaskDWord, 0x00b500b8); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10000304); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10010203); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10020102); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10030101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10040101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10050101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10060101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10070101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x1008caff); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100980a1); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100a5165); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100b3340); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100c2028); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100d1419); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100e0810); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100f0506); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01007800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01017800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01027800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01037800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01047800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01057800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01067800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01077800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01087800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01097800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01107800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01117800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01127800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01137800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01147800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01157800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01167800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01177800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01187800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01197800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01207800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01217800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01227800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01237800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01247800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01257800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01267800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01277800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01287800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01297800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01307800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01317800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01327800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01337800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01347800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01357800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01367800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01377800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01387800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01397800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013F7800); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02007800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02017800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02027800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02037800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02047800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02057800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02067800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02077800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02087800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02097800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02107800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02117800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02127800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02137800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02147800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02157800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02167800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02177800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02187800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02197800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02207800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02217800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02227800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02237800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02247800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02257800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02267800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02277800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02287800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02297800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02307800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02317800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02327800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02337800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02347800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02357800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02367800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02377800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02387800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02397800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023F7800); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - -} - -VOID -phy_path_b_dpk_init_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - /**/ - ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, 0x0001e018); - ODM_SetBBReg(pDM_Odm, 0xb74, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, 0xb98, bMaskDWord, 0x000844aa); - ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, 0x31160200); - - ODM_SetBBReg(pDM_Odm, 0xba0, 0x000fffff, 0x0007bdef); - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); - - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x00021d5f); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x41382e21); - ODM_SetBBReg(pDM_Odm, 0xb7c, bMaskDWord, 0x5b554f48); - ODM_SetBBReg(pDM_Odm, 0xb80, bMaskDWord, 0x6f6b6661); - ODM_SetBBReg(pDM_Odm, 0xb84, bMaskDWord, 0x817d7874); - ODM_SetBBReg(pDM_Odm, 0xb88, bMaskDWord, 0x908c8884); - ODM_SetBBReg(pDM_Odm, 0xb8c, bMaskDWord, 0x9d9a9793); - ODM_SetBBReg(pDM_Odm, 0xb90, bMaskDWord, 0xaaa7a4a1); - ODM_SetBBReg(pDM_Odm, 0xb94, bMaskDWord, 0xb6b3b0ad); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); - - ODM_SetBBReg(pDM_Odm, 0xb60, bMaskDWord, 0x02ce03e8); - ODM_SetBBReg(pDM_Odm, 0xb64, bMaskDWord, 0x01fd024c); - ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, 0x01a101c9); - ODM_SetBBReg(pDM_Odm, 0xb6C, bMaskDWord, 0x016a0183); - ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, 0x01430153); - ODM_SetBBReg(pDM_Odm, 0xb74, bMaskDWord, 0x01280134); - ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x0112011c); - ODM_SetBBReg(pDM_Odm, 0xb7C, bMaskDWord, 0x01000107); - ODM_SetBBReg(pDM_Odm, 0xb80, bMaskDWord, 0x00f200f9); - ODM_SetBBReg(pDM_Odm, 0xb84, bMaskDWord, 0x00e500eb); - ODM_SetBBReg(pDM_Odm, 0xb88, bMaskDWord, 0x00da00e0); - ODM_SetBBReg(pDM_Odm, 0xb8c, bMaskDWord, 0x00d200d6); - ODM_SetBBReg(pDM_Odm, 0xb90, bMaskDWord, 0x00c900cd); - ODM_SetBBReg(pDM_Odm, 0xb94, bMaskDWord, 0x00c200c5); - ODM_SetBBReg(pDM_Odm, 0xb98, bMaskDWord, 0x00bb00be); - ODM_SetBBReg(pDM_Odm, 0xb9c, bMaskDWord, 0x00b500b8); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20000304); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20010203); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20020102); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20030101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20040101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20050101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20060101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20070101); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x2008caff); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200980a1); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200a5165); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200b3340); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200c2028); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200d1419); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200e0810); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200f0506); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04007800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04017800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04027800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04037800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04047800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04057800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04067800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04077800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04087800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04097800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04107800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04117800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04127800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04137800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04147800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04157800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04167800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04177800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04187800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04197800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04207800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04217800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04227800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04237800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04247800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04257800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04267800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04277800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04287800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04297800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04307800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04317800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04327800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04337800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04347800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04357800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04367800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04377800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04387800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04397800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043F7800); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08007800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08017800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08027800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08037800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08047800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08057800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08067800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08077800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08087800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08097800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08107800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08117800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08127800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08137800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08147800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08157800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08167800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08177800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08187800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08197800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08207800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08217800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08227800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08237800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08247800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08257800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08267800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08277800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08287800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08297800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082F7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08307800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08317800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08327800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08337800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08347800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08357800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08367800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08377800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08387800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08397800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083A7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083B7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083C7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083D7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083E7800); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083F7800); - - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - -} - - -VOID -phy_set_txrate_index_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - /*Path A*/ - ODM_SetBBReg(pDM_Odm, 0xe08, 0x00007F00, 0x30); - ODM_SetBBReg(pDM_Odm, 0x86c, 0xFFFFFF00, 0x303030); - ODM_SetBBReg(pDM_Odm, 0xe00, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0xe04, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0xe10, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0xe14, bMaskDWord, 0x30303030); - - /*Path B*/ - ODM_SetBBReg(pDM_Odm, 0x838, 0xFFFFFF00, 0x303030); - ODM_SetBBReg(pDM_Odm, 0x86c, 0x000000FF, 0x30); - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0x834, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, 0x30303030); - ODM_SetBBReg(pDM_Odm, 0x848, bMaskDWord, 0x30303030); - -} - -u1Byte -phy_path_a_gainloss_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - int k; - u1Byte TX_AGC_search = 0x0, result[5] = {0x0}; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xaa000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x5801c); - ODM_Write1Byte(pDM_Odm, 0xb00, 0x18); - ODM_Write1Byte(pDM_Odm, 0xb07, 0xf7); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_SetBBReg(pDM_Odm, 0xb68, 0xffff0000, 0x159f); - ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x41382e21); - ODM_Write1Byte(pDM_Odm, 0xbad, 0x2c); /*1.5dB*/ - ODM_SetBBReg(pDM_Odm, 0xe34, bMaskDWord, 0x10000000); - - ODM_delay_ms(5); - - for (k = 0; k < 5; k++) - { - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_delay_ms(20); - - result[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbdc, 0x0000000f); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] result[%d] = 0x%x\n", k, result[k])); - - if ((k != 0) && (result[k] == result[k-1])) - break; - } - - if (k == 4) - TX_AGC_search = ((result[0] + result[1] + result[2] + result[3] + result[4]) / 5); - else - TX_AGC_search = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbdc, 0x0000000f); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] TXAGC_search_a = 0x%x\n", TX_AGC_search)); - return TX_AGC_search; - -} - -u1Byte -phy_path_b_gainloss_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - int k; - u1Byte TX_AGC_search = 0x0, result[5] = {0x0}; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xaa000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x5801c); - ODM_Write1Byte(pDM_Odm, 0xb70, 0x18); - ODM_Write1Byte(pDM_Odm, 0xb77, 0xf7); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_SetBBReg(pDM_Odm, 0xb6c, 0xffff0000, 0x159f); - ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x41382e21); - ODM_Write1Byte(pDM_Odm, 0xbad, 0x2c); /*1.5dB*/ - ODM_SetBBReg(pDM_Odm, 0xe54, bMaskDWord, 0x10000000); - - ODM_delay_ms(5); - - for (k = 0; k < 5; k++) - { - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_delay_ms(20); - - result[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbec, 0x0000000f); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] result[%d] = 0x%x\n", k, result[k])); - - if ((k != 0) && (result[k] == result[k-1])) - break; - } - - if (k == 4) - TX_AGC_search = ((result[0] + result[1] + result[2] + result[3] + result[4]) / 5); - else - TX_AGC_search = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbec, 0x0000000f); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] TXAGC_search_b = 0x%x\n", TX_AGC_search)); - return TX_AGC_search; - -} - - -u4Byte -phy_path_a_dodpk_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - u1Byte TX_AGC_search, - u1Byte k -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte REG_B68, result; - u1Byte TX_AGC = 0x0; - - - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x40); - - switch (TX_AGC_search) - { - case 0x0: - REG_B68 = 0x11160200 | (0x19<<10); - TX_AGC = 0x12; - break; - - case 0x1: - REG_B68 = 0x11160200 | (0x1a<<10); - TX_AGC = 0x13; - break; - - case 0x2: - REG_B68 = 0x11160200 | (0x1b<<10); - TX_AGC = 0x14; - break; - - case 0x3: - REG_B68 = 0x11160200 | (0x1c<<10); - TX_AGC = 0x15; - break; - - case 0x4: - REG_B68 = 0x11160200 | (0x1d<<10); - TX_AGC = 0x16; - break; - - case 0x5: - REG_B68 = 0x11160200 | (0x1e<<10); - TX_AGC = 0x17; - break; - - case 0x6: - REG_B68 = 0x11160200 | (0x1f<<10); - TX_AGC = 0x18; - break; - - case 0x7: - REG_B68 = 0x11160200 | (0x00<<10); - TX_AGC = 0x19; - break; - - case 0x8: - REG_B68 = 0x11160200 | (0x01<<10); - TX_AGC = 0x1a; - break; - - case 0x9: - REG_B68 = 0x11160200 | (0x02<<10); - TX_AGC = 0x1b; - break; - - case 0xa: - REG_B68 = 0x11160200 | (0x03<<10); - TX_AGC = 0x1c; - break; - - } - - ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, REG_B68); - /*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xaa000);*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, (0x58000 | TX_AGC)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a 0x0 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask))); - - pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xb68, 0x00007C00); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb68[%d] = 0x%x, pwsf_2g_a[%d] = 0x%x\n", - k, ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord), k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k])); - //ODM_delay_ms(5); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0xc0); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x40); - ODM_delay_ms(10); - - result = ODM_GetBBReg(pDM_Odm, 0xbd8, (BIT18)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] fail bit = %x\n", result)); - return result; - -} - -u4Byte -phy_path_b_dodpk_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - u1Byte TX_AGC_search, - u1Byte k -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte REG_B6C, result; - u1Byte TX_AGC = 0x0; - - - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x40); - - switch (TX_AGC_search) - { - case 0x0: - REG_B6C = 0x11160200 | (0x19<<10); - TX_AGC = 0x12; - break; - - case 0x1: - REG_B6C = 0x11160200 | (0x1a<<10); - TX_AGC = 0x13; - break; - - case 0x2: - REG_B6C = 0x11160200 | (0x1b<<10); - TX_AGC = 0x14; - break; - - case 0x3: - REG_B6C = 0x11160200 | (0x1c<<10); - TX_AGC = 0x15; - break; - - case 0x4: - REG_B6C = 0x11160200 | (0x1d<<10); - TX_AGC = 0x16; - break; - - case 0x5: - REG_B6C = 0x11160200 | (0x1e<<10); - TX_AGC = 0x17; - break; - - case 0x6: - REG_B6C = 0x11160200 | (0x1f<<10); - TX_AGC = 0x18; - break; - - case 0x7: - REG_B6C = 0x11160200 | (0x00<<10); - TX_AGC = 0x19; - break; - - case 0x8: - REG_B6C = 0x11160200 | (0x01<<10); - TX_AGC = 0x1a; - break; - - case 0x9: - REG_B6C = 0x11160200 | (0x02<<10); - TX_AGC = 0x1b; - break; - - case 0xa: - REG_B6C = 0x11160200 | (0x03<<10); - TX_AGC = 0x1c; - break; - - } - - ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, REG_B6C); - /*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xaa000);*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, (0x58000 | TX_AGC)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_b 0x0 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask))); - - pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xb6c, 0x00007C00); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb6c[%d] = 0x%x, pwsf_2g_b[%d] = 0x%x\n", - k, ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord), k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k])); - //ODM_delay_ms(5); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0xc0); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x40); - ODM_delay_ms(10); - - result = ODM_GetBBReg(pDM_Odm, 0xbd8, (BIT19)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] fail bit = %x\n", result)); - return result; - -} - -BOOLEAN -phy_path_a_iq_check_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - u1Byte group, - u1Byte addr, - BOOLEAN is_even -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte i_val, q_val; - - if (is_even) { - i_val = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x003FF800); - q_val = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x000007FF); - } else { - i_val = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x003FF800); - q_val = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x000007FF); - } - - if (((q_val & 0x400)>>10) == 1) - q_val = 0x800 - q_val; - - if ((addr == 0) && ((i_val*i_val + q_val*q_val) < 0x2851e)) {/* LMS (I^2 + Q^2) < -2dB happen*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x <-2dB\n", group, (i_val*i_val + q_val*q_val))); - return 1; - } else if ((i_val*i_val + q_val*q_val) > 0x47cf2) {/* LMS (I^2 + Q^2) > 0.5dB happen*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x >0.5dB\n", group, (i_val*i_val + q_val*q_val))); - return 1; - } else { - return 0; - } - -} - -BOOLEAN -phy_path_b_iq_check_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - u1Byte group, - u1Byte addr, - BOOLEAN is_even -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte i_val, q_val; - - if (is_even) { - i_val = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x003FF800); - q_val = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x000007FF); - } else { - i_val = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x003FF800); - q_val = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x000007FF); - } - - if (((q_val & 0x400)>>10) == 1) - q_val = 0x800 - q_val; - - if ((addr == 0) && ((i_val*i_val + q_val*q_val) < 0x2851e)) {/* LMS (I^2 + Q^2) < -2dB happen*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x <-2dB\n", group, (i_val*i_val + q_val*q_val))); - return 1; - } else if ((i_val*i_val + q_val*q_val) > 0x47cf2) {/* LMS (I^2 + Q^2) > 0.5dB happen*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x >0.5dB\n", group, (i_val*i_val + q_val*q_val))); - return 1; - } else { - return 0; - } - -} - - -VOID -phy_path_a_pas_read_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN is_gainloss -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - int k; - u4Byte reg_b00, reg_b68, reg_bdc, reg_be0, reg_be4, reg_be8; - - - reg_b00 = ODM_GetBBReg(pDM_Odm, 0xb00, bMaskDWord); - reg_b68 = ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord); - - if(is_gainloss) { - ODM_SetBBReg(pDM_Odm, 0xb68, BIT26, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb68 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord))); - } - - for (k = 0; k < 8; k++) - { - ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, (0x0101f038 | k)); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb00[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb00, bMaskDWord))); - reg_bdc = ODM_GetBBReg(pDM_Odm, 0xbdc, bMaskDWord); - reg_be0 = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - reg_be4 = ODM_GetBBReg(pDM_Odm, 0xbe4, bMaskDWord); - reg_be8 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_bdc)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be8)); - } - - ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, reg_b00); - ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, reg_b68); - -} - -VOID -phy_path_b_pas_read_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN is_gainloss -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - int k; - u4Byte reg_b70, reg_b6c, reg_bec, reg_bf0, reg_bf4, reg_bf8; - - reg_b70 = ODM_GetBBReg(pDM_Odm, 0xb70, bMaskDWord); - reg_b6c = ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord); - - - if(is_gainloss) { - ODM_SetBBReg(pDM_Odm, 0xb6c, BIT26, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb6c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord))); - } - - for (k = 0; k < 8; k++) - { - ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, (0x0101f038 | k)); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb70[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb70, bMaskDWord))); - reg_bec = ODM_GetBBReg(pDM_Odm, 0xbec, bMaskDWord); - reg_bf0 = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - reg_bf4 = ODM_GetBBReg(pDM_Odm, 0xbf4, bMaskDWord); - reg_bf8 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bec)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf8)); - } - - ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, reg_b70); - ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, reg_b6c); - -} - -VOID -phy_path_a_dpk_enable_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_Write1Byte(pDM_Odm, 0xb00, 0x98); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_Write1Byte(pDM_Odm, 0xb6a, 0x26); - - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); - ODM_delay_ms(10); - - ODM_Write1Byte(pDM_Odm, 0xb07, 0x77); - ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x4c104c10); /*1.5dB*/ - - /*ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000);*/ - /*ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000);*/ - -} - -VOID -phy_path_b_dpk_enable_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - ODM_Write1Byte(pDM_Odm, 0xb70, 0x98); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_Write1Byte(pDM_Odm, 0xb6e, 0x26); - - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); - ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); - ODM_delay_ms(10); - - ODM_Write1Byte(pDM_Odm, 0xb77, 0x77); - ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x4c104c10); /*1.5dB*/ - - /*ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000);*/ - /*ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000);*/ - -} - -u1Byte -phy_dpk_channel_transfer_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u1Byte channel, bandwidth, i; - - channel = *pDM_Odm->pChannel; - bandwidth = *pDM_Odm->pBandWidth; - - if (channel <= 4) - i = 0; - else if (channel >= 5 && channel <= 8) - i = 1; - else if (channel >= 9) - i = 2; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] channel = %d, bandwidth = %d, transfer idx = %d\n", - channel, bandwidth, i)); - - return i; - -} - - -u1Byte -phy_lut_sram_read_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - u1Byte k -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u1Byte addr, i; - u4Byte regb2c; - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - for(addr = 0; addr < 64; addr++) - { - regb2c = (0x00801234 | (addr << 16)); - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, regb2c); - - /*A even*/ - if (phy_path_a_iq_check_8197f(pDM_Odm, k, addr, true)) { - return 0; - } - pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x003FFFFF); - - /*A odd*/ - if (phy_path_a_iq_check_8197f(pDM_Odm, k, addr, false)) { - return 0; - } - pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x003FFFFF); - - /*B even*/ - if (phy_path_b_iq_check_8197f(pDM_Odm, k, addr, true)) { - return 0; - } - pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x003FFFFF); - - /*B odd*/ - if (phy_path_b_iq_check_8197f(pDM_Odm, k, addr, false)) { - return 0; - } - pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x003FFFFF); - - } - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - -#if (DPK_SRAM_read_DBG_8197F) - - if (k == 2) - { - for (i = 0; i < 3; i++) - { - for(addr = 0; addr < 16; addr++) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_A even 0xbc0[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[i][addr])); - - for(addr = 0; addr < 16; addr++) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_A odd 0xbc4[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[i][addr])); - - for(addr = 0; addr < 16; addr++) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_B even 0xbc8[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[i][addr])); - - for(addr = 0; addr < 16; addr++) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_B odd 0xbcc[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[i][addr])); - } - } -#endif - -#if 0 - if (k == 2) - { - printk("bDPPathAOK=%d bDPPathBOK=%d\n", pDM_Odm->RFCalibrateInfo.bDPPathAOK, pDM_Odm->RFCalibrateInfo.bDPPathBOK); - u4Byte j; - - //for (i = 0; i < 3; i++) - { - printk("sram_read pwsf_2g_a[%d]=0x%x pwsf_2g_b[%d]=0x%x\n", k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k], k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]); - } - - //for (i = 0; i < 3; i++) - { - for (j = 0; j < 64; j++) - printk("sram_read lut_2g_even_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_read lut_2g_odd_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_read lut_2g_even_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_read lut_2g_odd_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][j]); - } - } -#endif - -return 1; - -} - -VOID -phy_lut_sram_write_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID -#else - PADAPTER pAdapter -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u1Byte addr, k; - u4Byte regba8_a_even[64] = {0}, regb2c_a_even[64] = {0}; - u4Byte regba8_a_odd[64] = {0}, regb2c_a_odd[64] = {0}; - u4Byte regba8_b_even[64] = {0}, regb2c_b_even[64] = {0}; - u4Byte regba8_b_odd[64] = {0}, regb2c_b_odd[64] = {0}; - - - k = phy_dpk_channel_transfer_8197f(pDM_Odm); - -#if 0 -{ - printk("bDPPathAOK=%d bDPPathBOK=%d\n", pDM_Odm->RFCalibrateInfo.bDPPathAOK, pDM_Odm->RFCalibrateInfo.bDPPathBOK); - u4Byte j; - - //for (i = 0; i < 3; i++) - { - printk("sram_write pwsf_2g_a[%d]=0x%x pwsf_2g_b[%d]=0x%x\n", k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k], k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]); - } - - //for (i = 0; i < 3; i++) - { - for (j = 0; j < 64; j++) - printk("sram_write lut_2g_even_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_write lut_2g_odd_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_write lut_2g_even_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][j]); - - for (j = 0; j < 64; j++) - printk("sram_write lut_2g_odd_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][j]); - } -} -#endif - - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); - - for(addr = 0; addr < 64; addr++) - { - /*A even*/ - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x1); - regba8_a_even[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] & 0x003F0000)>>16; - regb2c_a_even[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] & 0x0000FFFF; - - ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_a_even[addr]); - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_a_even[addr] | (addr<<16))); - -#if (DPK_SRAM_write_DBG_8197F) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A even 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A even 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); -#endif - } - - for(addr = 0; addr < 64; addr++) - { - /*A odd*/ - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x2); - regba8_a_odd[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] & 0x003F0000)>>16; - regb2c_a_odd[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] & 0x0000FFFF; - - ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_a_odd[addr]); - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_a_odd[addr] | (addr<<16))); - -#if (DPK_SRAM_write_DBG_8197F) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A odd 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A odd 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); -#endif - } - - for(addr = 0; addr < 64; addr++) - { - /*B even*/ - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x4); - regba8_b_even[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] & 0x003F0000)>>16; - regb2c_b_even[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] & 0x0000FFFF; - - ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_b_even[addr]); - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_b_even[addr] | (addr<<16))); - -#if (DPK_SRAM_write_DBG_8197F) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B even 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B even 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); -#endif - } - - for(addr = 0; addr < 64; addr++) - { - /*B odd*/ - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x8); - regba8_b_odd[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] & 0x003F0000)>>16; - regb2c_b_odd[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] & 0x0000FFFF; - - ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_b_odd[addr]); - ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_b_odd[addr] | (addr<<16))); - -#if (DPK_SRAM_write_DBG_8197F) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B odd 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B odd 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); -#endif - } - - ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, (0x11260200 | (pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k]<<10))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] init pwsf_a[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb68, 0x00007c00))); - - ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, (0x11260200 | (pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]<<10))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] init pwsf_b[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb6c, 0x00007c00))); - - -} - -VOID -phy_dpk_enable_disable_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN enable -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - if (enable) { /*use dpk result*/ - ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x0); - ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x0); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = 1; - pDM_Odm->RFCalibrateInfo.bDPPathBOK = 1; - } else { /*bypass dpk result*/ - ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x1); - ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x1); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0; - pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0; - } -} - -u1Byte -phy_dpcalibrate_8197f( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PVOID pDM_VOID, -#else - PADAPTER pAdapter, -#endif - BOOLEAN is2T, - u1Byte k - -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - #endif - - u4Byte ADDA_REG[2] = { - 0xd94, rRx_Wait_CCA - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - u4Byte IQK_BB_REG_92C[17] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, 0x88c, 0xc5c, - 0xc14, 0xc1c, 0x800, 0x880, 0x884, - 0x930, 0x934, 0x93c, 0x92c, 0xc30, - 0xc3c, 0xc84 - }; - - u4Byte Txrate_REG[11] = { - 0xe08, 0x86c, 0xe00, 0xe04, 0xe10, 0xe14, - 0x838, 0x830, 0x834, 0x83c, 0x848 - }; - - u4Byte result_a = 0x1, result_b = 0x1, tmp_rf_a_00, tmp_rf_a_8f, tmp_rf_b_00, tmp_rf_b_8f; - u1Byte TXAGC_a_search = 0x0, TXAGC_b_search = 0x0; - - _PHY_SaveADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, 2); - _PHY_SaveMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, 17); - _PHY_SaveADDARegisters_97F(pDM_Odm, Txrate_REG, pDM_Odm->RFCalibrateInfo.Txrate, 11); - - tmp_rf_a_00 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); - tmp_rf_a_8f = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); - tmp_rf_b_00 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask); - tmp_rf_b_8f = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); - - ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); /*Tx Pause*/ - - phy_path_a_dpk_init_8197f(pDM_Odm); - phy_path_b_dpk_init_8197f(pDM_Odm); - - phy_set_txrate_index_8197f(pDM_Odm); - - ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0xccf008c0); - ODM_SetBBReg(pDM_Odm, 0xc5c, bMaskDWord, 0x80708492); - ODM_SetBBReg(pDM_Odm, 0xd94, bMaskDWord, 0x44FFBB44); - ODM_SetBBReg(pDM_Odm, 0xe70, bMaskDWord, 0x00400040); - ODM_SetBBReg(pDM_Odm, 0x87c, bMaskDWord, 0x004f0201); - ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0xc0000120); - ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0xd8001402); - ODM_SetBBReg(pDM_Odm, 0xc04, bMaskDWord, 0x6f005433); - ODM_SetBBReg(pDM_Odm, 0xc08, bMaskDWord, 0x000804e4); - ODM_SetBBReg(pDM_Odm, 0x874, bMaskDWord, 0x25204000); - ODM_SetBBReg(pDM_Odm, 0xc14, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0xc1c, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, 0x800, BIT24, 0x0); /*disable CCK block*/ - - /*TRSW PA on, LNA off*/ - ODM_SetBBReg(pDM_Odm, 0x930, bMaskDWord, 0xFFFF77FF); - ODM_SetBBReg(pDM_Odm, 0x934, bMaskDWord, 0xFFFFFFF7); - ODM_SetBBReg(pDM_Odm, 0x93c, bMaskDWord, 0xFFFF777F); - ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x0C000108); - - /*set CCA TH to highest*/ - ODM_SetBBReg(pDM_Odm, 0xc3c, 0x000007F8, 0xff); - ODM_SetBBReg(pDM_Odm, 0xc30, 0x0000000f, 0xf); - ODM_SetBBReg(pDM_Odm, 0xc84, 0xf0000000, 0xf); - -#if 1 - /*path A DPK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] ============ Path A[%d] DPK ============\n", k)); - - TXAGC_a_search = phy_path_a_gainloss_8197f(pDM_Odm); - - if (DPK_PAS_DBG_8197F) - phy_path_a_pas_read_8197f(pDM_Odm, TRUE); - - ODM_delay_ms(5); - - result_a = phy_path_a_dodpk_8197f(pDM_Odm, TXAGC_a_search, k); - - if (DPK_PAS_DBG_8197F) - phy_path_a_pas_read_8197f(pDM_Odm, FALSE); - -#endif - -#if 1 - /*path B DPK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] ============ Path B[%d] DPK ============\n", k)); - - TXAGC_b_search = phy_path_b_gainloss_8197f(pDM_Odm); - - if (DPK_PAS_DBG_8197F) - phy_path_b_pas_read_8197f(pDM_Odm, TRUE); - - ODM_delay_ms(5); - - result_b = phy_path_b_dodpk_8197f(pDM_Odm, TXAGC_b_search, k); - - if (DPK_PAS_DBG_8197F) - phy_path_b_pas_read_8197f(pDM_Odm, FALSE); - -#endif - - phy_path_a_dpk_enable_8197f(pDM_Odm); - phy_path_b_dpk_enable_8197f(pDM_Odm); - - if (result_a != 0) - { - ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x1); /*bypass path_A DPD*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Bypass Path_A[%d] DPD!!!!\n", k)); - pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; - pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK PathA need check k=%d\n", k)); - //printk("[DPK] DPK PathA need check k=%d\n", k); - } else { - pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 1; - - if (k == 2 - && pDM_Odm->RFCalibrateInfo.DPPathAResult[0] == 1 - && pDM_Odm->RFCalibrateInfo.DPPathAResult[1] == 1 - && pDM_Odm->RFCalibrateInfo.DPPathAResult[2] == 1) - pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0x1; - } - - if (result_b != 0) - { - ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x1); /*bypass path_B DPD*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Bypass Path_B DPD!!!!\n")); - pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; - pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK PathB need check k=%d\n", k)); - //printk("[DPK] DPK PathB need check k=%d\n", k); - - } else { - pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 1; - - if (k == 2 - && pDM_Odm->RFCalibrateInfo.DPPathBResult[0] == 1 - && pDM_Odm->RFCalibrateInfo.DPPathBResult[1] == 1 - && pDM_Odm->RFCalibrateInfo.DPPathBResult[2] == 1) - pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0x1; - } - - _PHY_ReloadADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, 2); - _PHY_ReloadMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, 17); - _PHY_ReloadADDARegisters_97F(pDM_Odm, Txrate_REG, pDM_Odm->RFCalibrateInfo.Txrate, 11); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, tmp_rf_a_00); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, tmp_rf_a_8f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, tmp_rf_b_00); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, tmp_rf_b_8f); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK Finish!!!!\n")); - -#if 1 - - if((result_a == 0) && (result_b == 0)) - { - if (phy_lut_sram_read_8197f(pDM_Odm, k)) - return 1; - else { - pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; - pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; - return 0; - } - } else { - pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; - pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; - return 0; - } - -#endif -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +/*---------------------------Define Local Constant---------------------------*/ +#define DPK_VER_8197F 0x8 /*8197F DPK version: 0x7 20180731*/ + +/*---------------------------Define Local Constant---------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void DoIQK_8197F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + + PHY_IQCalibrate_8197F(pDM_Odm, FALSE); + +} +#else +/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8197F, but DoIQK_8197F and PHY_IQCalibrate_8197F have different arguments*/ +void DoIQK_8197F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ +#if 1 + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bReCovery = (BOOLEAN) DeltaThermalIndex; + + PHY_IQCalibrate_8197F(pDM_Odm, bReCovery); +#endif +} +#endif + +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 /*ms*/ + +VOID +do_dpk_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN is2T, + u1Byte k + +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u1Byte i = 0; + u4Byte tmp_rf_a_18, tmp_rf_b_18; + + if (!((pDM_Odm->RFEType == 0) || (pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 3))) + { + printk("[DPK] Skip DPK due to RFE type != 0/2/3\n"); + return; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK Start (Ver: 0x%x) !!!!\n", DPK_VER_8197F)); + + tmp_rf_a_18 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff); + tmp_rf_b_18 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff); + +#if 1 + switch (k) + { + case 0: /*channel 3*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc03); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc03); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH3!!!!\n")); + break; + + case 1: /*channel 7*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc07); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc07); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH7!!!!\n")); + break; + + case 2: /*channel 11*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, 0xc0b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, 0xc0b); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] switch to 20M-CH11!!!!\n")); + break; + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0x18@ path_A = 0x%x, path_B = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask), ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask))); + + for (i = 0; i < 6; i++) + { + //printk("[DPK] Retry DPK i=%d\n", i); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Retry DPK i=%d\n", i)); + if (phy_dpcalibrate_8197f(pDM_Odm, TRUE, k) == 1) + break; + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x18, 0x00fff, tmp_rf_a_18); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x18, 0x00fff, tmp_rf_b_18); + + + if ((pDM_Odm->RFCalibrateInfo.bDPPathAOK == 1) && (pDM_Odm->RFCalibrateInfo.bDPPathBOK == 1) && k == 2) + phy_lut_sram_write_8197f(pDM_Odm); + else + phy_dpk_enable_disable_8197f(pDM_Odm, false); +} + + +VOID +phy_dpk_track_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + prtl8192cd_priv priv = pDM_Odm->priv; + s1Byte pwsf_a, pwsf_b; + u1Byte offset, delta_DPK, is_increase, ThermalValue = 0, ThermalValue_DPK_AVG_count = 0, i = 0, k = 0; + u4Byte ThermalValue_DPK_AVG = 0; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + if (priv->pshare->mp_tx_dpk_tracking == FALSE) + return; + } +#endif + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_DPK) + pDM_Odm->RFCalibrateInfo.ThermalValue_DPK = priv->pmib->dot11RFEntry.ther; + + /* calculate average thermal meter */ + + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_8197F, BIT17 | BIT16, 0x3); /*thermal meter trigger*/ + ODM_delay_ms(1); + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_8197F, 0xfc00); /*get thermal meter*/ + + pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index++; + + if (pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index == Thermal_DPK_AVG_num) /*Average times */ + pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG_index = 0; + + for (i = 0; i < Thermal_DPK_AVG_num; i++) { + if (pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[i]) { + ThermalValue_DPK_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_DPK_AVG[i]; + ThermalValue_DPK_AVG_count++; + } + } + + if (ThermalValue_DPK_AVG_count) {/*Calculate Average ThermalValue after average enough times*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK_track] ThermalValue_DPK_AVG=0x%x(%d) ThermalValue_DPK_AVG_count = %d\n" + , ThermalValue_DPK_AVG, ThermalValue_DPK_AVG, ThermalValue_DPK_AVG_count)); + + ThermalValue = (u1Byte)(ThermalValue_DPK_AVG / ThermalValue_DPK_AVG_count); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK_track] AVG Thermal Meter = 0x%X(%d), PG Thermal Meter = 0x%X(%d)\n", + ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + } + + + delta_DPK = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + offset = delta_DPK / DPK_THRESHOLD_8197F; + + k = phy_dpk_channel_transfer_8197f(pDM_Odm); + + pwsf_a = pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k]; + pwsf_b = pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] delta_DPK = %d, offset = %d, track direction is %s\n", delta_DPK, offset, (is_increase ? "Plus" : "Minus"))); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_a before tracking is 0x%x, pwsf_b before tracking is 0x%x\n", pwsf_a, pwsf_b)); + + if ((pwsf_a>>4) != 0) + pwsf_a = (pwsf_a | 0xe0); + + if ((pwsf_b>>4) != 0) + pwsf_b = (pwsf_b | 0xe0); + + if (is_increase) { + + pwsf_a = pwsf_a + offset; + pwsf_b = pwsf_b + offset; + + } else { + + pwsf_a = pwsf_a - offset; + pwsf_b = pwsf_b - offset; + + } + + ODM_SetBBReg(pDM_Odm, 0xb68, 0x00007C00, pwsf_a); + ODM_SetBBReg(pDM_Odm, 0xb6c, 0x00007C00, pwsf_b); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_a after tracking is %d (0x%x), 0xb68 = 0x%x\n", pwsf_a, (pwsf_a & 0x1f), ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK track] pwsf_b after tracking is %d (0x%x), 0xb6c = 0x%x\n", pwsf_b, (pwsf_b & 0x1f), ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord))); + +} + + + +VOID +phy_dpkoff_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + /*Path A*/ + ODM_Write1Byte(pDM_Odm, 0xb00, 0x18); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_delay_ms(10); + + /*Path B*/ + ODM_Write1Byte(pDM_Odm, 0xb70, 0x18); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_delay_ms(10); + +} + +VOID +phy_dpkon_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + /*Path A*/ + ODM_Write1Byte(pDM_Odm, 0xb00, 0x98); + ODM_Write1Byte(pDM_Odm, 0xb07, 0xF7); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_delay_ms(10); + + ODM_Write1Byte(pDM_Odm, 0xb07, 0x77); + ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x4c104c10); /*1.5dB*/ + + /*Path B*/ + ODM_Write1Byte(pDM_Odm, 0xb70, 0x98); + ODM_Write1Byte(pDM_Odm, 0xb77, 0xF7); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_delay_ms(10); + + ODM_Write1Byte(pDM_Odm, 0xb77, 0x77); + ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x4c104c10); /*1.5dB*/ + +} + + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathA_IQK_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN configPathB +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte regEAC, regE94, regE9C, regEA4, tmp; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path A TXIQK start!====================\n")); + + /*=============================TXIQK setting=============================*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + if (pDM_Odm->ExtPA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003ff, 0x71); + } else if (pDM_Odm->ExtPA == 0 && pDM_Odm->CutVersion != ODM_CUT_A) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003ff, 0xe8); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x56 at Path A TXIQK = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask))); + + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-A IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if (pDM_Odm->ExtPA) + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214400f); + else + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140002); + } else + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214000f); + + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28140000); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00e62911); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + /*reload 0xdf and CCK_IND off */ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, BIT14, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] path A TXIQK is not success\n")); + return result; + +} + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathA_RxIQK_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN configPathB +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, RXPGA; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RxIQK start!\n")); + + /* =============================Get TXIMR setting=============================*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path A RXIQK step1!====================\n")); + + + /*modify RXIQK mode table*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); + + if (pDM_Odm->ExtPA) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xa8000); + else + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xae000); + } + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + /*Restore RXPGA*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, RXPGA); + } + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK step1 is not success\n")); + + + return result; + + } + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + /* =============================RXIQK setting=============================*/ + /*modify RXIQK mode table*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]====================Path A RXIQK step2!====================\n")); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK modify RXIQK mode table 2!\n"));*/ + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + /*PA/PAD control by 0x56, and set = 0x0*/ + if (pDM_Odm->CutVersion == ODM_CUT_A) { + + RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); + + if (pDM_Odm->ExtPA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x3); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x28000); + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xae000); + } + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x003e0, 0x3); + } + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); + + if (pDM_Odm->ExtPA == 1 && pDM_Odm->CutVersion == ODM_CUT_A) + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170c00); + else + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe3c(RX_PI_Data)= 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe3c, bMaskDWord)));*/ + + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path A LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_92E));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + /*PA/PAD controlled by 0x0 & Restore RXPGA*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); + if (pDM_Odm->CutVersion == ODM_CUT_A) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, RXPGA); + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RxIQK step2 is not success!!\n")); + return result; + + + +} + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathB_IQK_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte regEAC, regEB4, regEBC; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B TXIQK start!====================\n")); + + /* =============================TXIQK setting=============================*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*path A to SI mode to avoid RF go to shot-down mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + if (pDM_Odm->ExtPA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003ff, 0x71); + } else if (pDM_Odm->ExtPA == 0 && pDM_Odm->CutVersion != ODM_CUT_A) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003ff, 0xe8); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x56 at Path B TXIQK = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, bRFRegOffsetMask))); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if (pDM_Odm->ExtPA) + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8214400f); + else + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82140002); + } else + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x8214000f); + + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28140000); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00e62911); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, path B LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + /*Path A back to PI mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + /*reload 0xdf and CCK_IND off */ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, BIT14, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x0); + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B TXIQK is not success\n")); + return result; + +} + + + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathB_RxIQK_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN configPathB +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp, RXPGA; + u1Byte result = 0x00; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RxIQK start!\n")); + + /* =============================Get TXIMR setting=============================*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B RXIQK step1!====================\n")); + /*modify RXIQK mode table*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK modify RXIQK mode table!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); + + if (pDM_Odm->ExtPA) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xa8000); + else + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xae000); + } + + /*path A to SI mode to avoid RF go to shot-down mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + /*path-B IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28160000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] One shot, Path B LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + /*Restore RXPGA*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, RXPGA); + } + + /*Path A back to PI mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else { /*if Tx not OK, ignore Rx*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK step1 is not success\n")); + return result; + + } + + u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + /* =============================RXIQK setting=============================*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ====================Path B RXIQK step2!====================\n")); + + /*modify RXIQK mode table*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B RXIQK modify RXIQK mode table 2!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + /*PA/PAD control by 0x56, and set = 0x0*/ + if (pDM_Odm->CutVersion == ODM_CUT_A) { + + RXPGA = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); + + if (pDM_Odm->ExtPA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x3); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x28000); + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xae000); + } + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x56, 0x003e0, 0x3); + } + + /*path A to SI mode to avoid RF go to shot-down mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x0); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-B IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x18008c0c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82170000); + + if (pDM_Odm->ExtPA == 1 && pDM_Odm->CutVersion == ODM_CUT_A) + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28170c00); + else + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28170000); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe5c(RX_PI_Data)= 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe5c, bMaskDWord))); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa005800); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8005800); + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, Path B LOK & IQK.\n", IQK_DELAY_TIME_97F));*/ + ODM_delay_ms(IQK_DELAY_TIME_97F); + + + /*Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); + + /*PA/PAD controlled by 0x0 & Restore RXPGA*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00800, 0x0); + if (pDM_Odm->CutVersion == ODM_CUT_A) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, RXPGA); + + /*Path A back to PI mode*/ + ODM_SetBBReg(pDM_Odm, 0x820, BIT8, 0x1); + + if (!(regEAC & BIT30) &&/*if Tx is OK, check whether Rx is OK*/ + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK step2 is not success!!\n")); + return result; + + +} + +VOID +_PHY_PathAFillIQKMatrix_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN bIQKOK, + s4Byte result[][8], + u1Byte final_candidate, + BOOLEAN bTxOnly +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, Oldval_0); + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + + TX0_A = (X * 0x100) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX0_A = 0x%x\n", X, TX0_A)); + + ODM_SetBBReg(pDM_Odm, 0xe30, 0x3FF00000, TX0_A); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX0_C = (Y * 0x100) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, 0xe20, 0x000003C0, ((TX0_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, 0xe20, 0x0000003F, (TX0_C & 0x3F)); +#else + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); +#endif + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] _PHY_PathAFillIQKMatrix_97F only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; + #endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +_PHY_PathBFillIQKMatrix_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN bIQKOK, + s4Byte result[][8], + u1Byte final_candidate, + BOOLEAN bTxOnly /*do Tx only*/ +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, Oldval_1); + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + + TX1_A = (X * 0x100) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + ODM_SetBBReg(pDM_Odm, 0xe50, 0x3FF00000, TX1_A); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * 0x100) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, 0xe24, 0x000003C0, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, 0xe24, 0x0000003F, (TX1_C & 0x3F)); +#else + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); +#endif + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] _PHY_PathBFillIQKMatrix_97F only Tx OK\n")); + return; + } + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, 0xca8, 0x000000F0, reg); + } +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +#if 0 + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.*/ + if (pMgntInfo->init_adpt_in_progress == TRUE) { + ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if (Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) { + ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +#endif + return TRUE; +} +#endif + + +VOID +_PHY_SaveADDARegisters_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte ADDAReg, + pu4Byte ADDABackup, + u4Byte RegisterNum +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #endif + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Save ADDA parameters.\n"));*/ + for (i = 0 ; i < RegisterNum ; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte MACReg, + pu4Byte MACBackup +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Save MAC parameters.\n"));*/ + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte ADDAReg, + pu4Byte ADDABackup, + u4Byte RegiesterNum +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +VOID +_PHY_ReloadMACRegisters_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte MACReg, + pu4Byte MACBackup +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Reload MAC parameters !\n")); + #if 0 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0x0); + #else + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); + #endif +} + +VOID +_PHY_PathADDAOn_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte ADDAReg, + BOOLEAN isPathAOn, + BOOLEAN is2T +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte pathOn; + u4Byte i; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ADDA ON.\n"));*/ + + ODM_SetBBReg(pDM_Odm, 0xd94, 0x00ff0000, 0xff); + ODM_SetBBReg(pDM_Odm, 0xe70, bMaskDWord, 0x00400040); + +#if 0 + pathOn = isPathAOn ? 0x0fc01616 : 0x0fc01616; + if (FALSE == is2T) { + pathOn = 0x0fc01616; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0fc01616); + } else + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + + for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); +#endif +} + +VOID +_PHY_MACSettingCalibration_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + pu4Byte MACReg, + pu4Byte MACBackup +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*u4Byte i = 0;*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif +/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));*/ + +#if 0 + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT3))); + + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT5))); +#endif + + #if 1 + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); + #else + ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f); + ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15); + ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00); + #endif + + +} + +VOID +_PHY_PathAStandBy_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); + /*ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);*/ + ODM_SetRFReg(pDM_Odm, 0x0, 0x0, bRFRegOffsetMask, 0x10000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PathBStandBy_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path-B standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, 0x1, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + + +VOID +_PHY_PIModeSwitch_97F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN PIMode +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte mode; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + /*DM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));*/ + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + s4Byte result[][8], + u1Byte c1, + u1Byte c2 +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u4Byte i, j, diff, SimularityBitMap, bound = 0; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; /*for path A and path B*/ + BOOLEAN bResult = TRUE; +/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/ +/* BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);*/ +/*#else*/ + BOOLEAN is2T = TRUE; +/*#endif*/ + + s4Byte tmp1 = 0, tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ===> IQK:phy_SimularityCompare_8197F c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i] + result[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + SimularityBitMap = SimularityBitMap | (1 << i); + } else + SimularityBitMap = SimularityBitMap | (1 << i); + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] phy_SimularityCompare_8197F SimularityBitMap %x !!!\n", SimularityBitMap)); + + if (SimularityBitMap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + + } else { + + if (!(SimularityBitMap & 0x03)) { /*path A TX OK*/ + for (i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x0c)) { /*path A RX OK*/ + for (i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x30)) { /*path B TX OK*/ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + + } + + if (!(SimularityBitMap & 0xc0)) { /*path B RX OK*/ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + } + + return FALSE; + } + +} + +VOID +_phy_iqk_check_97f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte txa_fail, rxa_fail, txb_fail, rxb_fail; + + + txa_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(28)); + rxa_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(27)); + txb_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(31)); + rxb_fail = ODM_GetBBReg(pDM_Odm, 0xeac, BIT(30)); + + if (txa_fail == 1) + panic_printk("[IQK] path A TXIQK load default value!!!\n"); + if (rxa_fail == 1) + panic_printk("[IQK] path A RXIQK load default value!!!\n"); + if (txb_fail == 1) + panic_printk("[IQK] path B TXIQK load default value!!!\n"); + if (rxb_fail == 1) + panic_printk("[IQK] path B RXIQK load default value!!!\n"); + +} + + + +VOID +phy_IQCalibrate_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + s4Byte result[][8], + u1Byte t, + BOOLEAN is2T +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + u4Byte i, DAC_gain_A, DAC_gain_B; + u1Byte PathAOK = 0, PathBOK = 0; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + 0xd94, rRx_Wait_CCA + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + /*since 92C & 92D have the different define in IQK_BB_REG*/ + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + 0x930, 0x934, + 0x93c, rCCK0_AFESetting + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u4Byte retryCount = 2; + #else + #if MP_DRIVER + const u4Byte retryCount = 9; + #else + const u4Byte retryCount = 2; + #endif + #endif + + /*Note: IQ calibration must be performed after loading*/ + /*PHY_REG.txt,and radio_a,radio_b.txt*/ + + /*u4Byte bbvalue;*/ + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 2; + #endif + #endif + +#if 0 + /*RF setting :RXBB leave power saving*/ + if (pDM_Odm->CutVersion != ODM_CUT_A) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00002, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00002, 0x1); + } +#endif + /*Save and set DAC gain for IQK*/ + DAC_gain_A = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask); + DAC_gain_B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Ori_0x55 at Path A = 0x%x\n", DAC_gain_A)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Ori_0x55 at Path B = 0x%x\n", DAC_gain_B)); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x000e0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, 0x000e0, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Set_0x55 at Path A = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Set_0x55 at Path B = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask))); + + if (t == 0) { + /*bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);*/ + /*RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));*/ + + /*Save ADDA parameters, turn Path A ADDA on*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_97F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + _PHY_SaveADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn_97F(pAdapter, ADDA_REG, TRUE, is2T); + #else + _PHY_PathADDAOn_97F(pDM_Odm, ADDA_REG, TRUE, is2T); + #endif + + + /*BB setting*/ + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x6f005403); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000804e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x04203400); + + +#if 1 + /*FEM off when ExtPA or ExtLNA= 1*/ + if (pDM_Odm->ExtPA || pDM_Odm->ExtLNA) { + ODM_SetBBReg(pDM_Odm, 0x930, bMaskDWord, 0xFFFF77FF); + ODM_SetBBReg(pDM_Odm, 0x934, bMaskDWord, 0xFFFFFFF7); + ODM_SetBBReg(pDM_Odm, 0x93c, bMaskDWord, 0xFFFF777F); + } +#endif + + +/* if(is2T) {*/ +/* ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);*/ +/* ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);*/ +/* }*/ + + /*MAC settings*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #else + _PHY_MACSettingCalibration_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + #endif + + /* IQ calibration setting*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + +/*path A TXIQK*/ + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8197F(pAdapter, is2T); + #else + PathAOK = phy_PathA_IQK_8197F(pDM_Odm, is2T); + #endif + if (PathAOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A TXIQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A TXIQK Fail!!\n")); + result[t][0] = 0x100; + result[t][1] = 0x0; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +/*path A RXIQK*/ + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK_97F(pAdapter, is2T); + #else + PathAOK = phy_PathA_RxIQK_97F(pDM_Odm, is2T); + #endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK Success!!\n")); + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A RXIQK Fail!!\n")); + result[t][2] = 0x100; + result[t][3] = 0x0; + } + } + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path A IQK failed!!\n")); + + #endif + + if (is2T) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy_97F(pAdapter); + + /*Turn ADDA on*/ + _PHY_PathADDAOn_97F(pAdapter, ADDA_REG, FALSE, is2T); + #else + _PHY_PathAStandBy_97F(pDM_Odm); + + /*Turn ADDA on*/ + _PHY_PathADDAOn_97F(pDM_Odm, ADDA_REG, FALSE, is2T); + #endif + + /*IQ calibration setting*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + +/*path B Tx IQK*/ + #if 1 + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8197F(pAdapter); + #else + PathBOK = phy_PathB_IQK_8197F(pDM_Odm); + #endif + + if (PathBOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B TXIQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B TXIQK Fail!!\n")); + result[t][4] = 0x100; + result[t][5] = 0x0; + } + #if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { /*Tx IQK OK*/ + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + } + #endif + } + #endif + +/*path B RX IQK*/ + #if 1 + + for (i = 0 ; i < retryCount ; i++) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK_97F(pAdapter, is2T); + #else + PathBOK = phy_PathB_RxIQK_97F(pDM_Odm, is2T); + #endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Path B RXIQK Success!!\n")); + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); + result[t][6] = 0x100; + result[t][7] = 0x0; + } + } + + if (0x00 == PathBOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + + #endif + } + + /*Back to BB mode, load original value*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { + + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_97F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_97F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #else + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + #endif + + /*Allen initial gain 0xc50*/ + /* Restore RX initial gain*/ + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } +#if 0 + /*RF setting :RXBB enter power saving*/ + if (pDM_Odm->CutVersion != ODM_CUT_A) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00002, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, 0x00002, 0x0); + } +#endif + #if 0 + /*load 0xe30 IQC default value*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + #endif + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] phy_IQCalibrate_8197F() <==\n")); + + /*reload DAC gain for K-free*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, DAC_gain_A); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask, DAC_gain_B); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Restore_0x55 at Path A = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Restore_0x55 at Path B = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x55, bRFRegOffsetMask))); +} + +VOID +phy_LCCalibrate_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN is2T +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal, cnt; + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + /*Check continuous TX and Packet TX*/ + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + + /*backup RF0x18*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + /*Start LCK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); + + for (cnt = 0; cnt < 100; cnt++) { + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + + ODM_delay_ms(10); + } + + /*Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + + /*Restore original situation*/ + if ((tmpReg&0x70) != 0) { + /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + } else { + /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } + +} + + +VOID +PHY_IQCalibrate_8197F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN bReCovery +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif/*(MP_DRIVER == 1)*/ + #endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + + s4Byte result[4][8]; /*last is final result*/ + u1Byte i, final_candidate, Indexforchannel; + u1Byte channelToIQK = 7; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, 0xca8, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #else + prtl8192cd_priv priv = pDM_Odm->priv; + + #ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } + #endif + /* if (priv->pshare->IQK_92E_done)*/ + /* bReCovery= 1; */ + /* priv->pshare->IQK_92E_done = 1;*/ + #endif + + #if 1//(DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + + #if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ + if (bSingleTone || bCarrierSuppression) + return; + + #ifdef DISABLE_BB_RF + return; + #endif + + if (pRFCalibrateInfo->bIQKInProgress) + return; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) + #else /*for ODM_WIN*/ + if (bReCovery && + (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ + #endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK] PHY_IQCalibrate_97F: Return due to bReCovery!\n")); +#if 0 + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #endif +#endif + return; + } + +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + /*turn off DPK*/ + phy_dpkoff_8197f(pDM_Odm); +#endif + + /*check IC cut and IQK version*/ + if (pDM_Odm->CutVersion == ODM_CUT_A) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is A\n")); + else if (pDM_Odm->CutVersion == ODM_CUT_B) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is B\n")); + else if (pDM_Odm->CutVersion == ODM_CUT_C) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is C\n")); + else if (pDM_Odm->CutVersion == ODM_CUT_D) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] Cut Version is D\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK Version is v2.6 (20170109)\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] PHY Version is v%d \n", ODM_GetHWImgVersion(ODMPTR))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] ExtPA = %d, ExtLNA = %d\n", pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK Start!!!\n")); + priv->pshare->IQK_total_cnt++; + +#if 0 + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); +#endif + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_IQCalibrate_8197F(pAdapter, result, i, TRUE); + + + #else + + + phy_IQCalibrate_8197F(pDM_Odm, result, i, TRUE); + #endif + + + if (i == 1) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8197F(pAdapter, result, 0, 1); + #else + is12simular = phy_SimularityCompare_8197F(pDM_Odm, result, 0, 1); + #endif + + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8197F(pAdapter, result, 0, 2); + #else + is13simular = phy_SimularityCompare_8197F(pDM_Odm, result, 0, 2); + #endif + + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is13simular final_candidate is %x\n", final_candidate)); + + break; + } + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8197F(pAdapter, result, 1, 2); + #else + is23simular = phy_SimularityCompare_8197F(pDM_Odm, result, 1, 2); + #endif + + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] is23simular final_candidate is %x\n", final_candidate)); + } else { +#if 0 + for (i = 0; i < 4; i++) + RegTmp &= result[3][i*2]; + + if (RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; +#endif + final_candidate = 3; + + } + } + } +#if 0 + if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { + for (i = 0; i < 8; i++) { + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[final_candidate][i] = 0x100; + else + result[final_candidate][i] = 0; + } + } +#endif + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + priv->pshare->RegEB4 = pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + priv->pshare->RegEBC = pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] FAIL use default value\n"));*/ + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _phy_iqk_check_97f(pAdapter); + #else + _phy_iqk_check_97f(pDM_Odm); + #endif + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /*X default value*/ + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /*Y default value*/ + priv->pshare->IQK_fail_cnt++; + } + +#if 0 + /*reset TXIQC for DPD*/ + ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000); + ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xe50, bMaskDWord, 0x10000000); + ODM_SetBBReg(pDM_Odm, 0xe24, bMaskDWord, 0x00000000); +#endif + + if ((RegE94 != 0)/*&&(RegEA4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix_97F(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #else + _PHY_PathAFillIQKMatrix_97F(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); + #endif + } + + if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/) { + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathBFillIQKMatrix_97F(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + #else + _PHY_PathBFillIQKMatrix_97F(pDM_Odm, bPathBOK, result, final_candidate, (RegEC4 == 0)); + #endif + } + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); + #else + Indexforchannel = 0; + #endif + +/*To Fix BSOD when final_candidate is 0xff*/ +/*by sherry 20120321*/ + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + /*RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK OK Indexforchannel %d.\n", Indexforchannel)); + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters_97F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + #else + _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); + #endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc80 = 0x%x, 0xc94 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe30 = 0x%x, 0xe20 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xe30, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe20, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc14 = 0x%x, 0xca0 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xca0, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc88 = 0x%x, 0xc9c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc88, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc9c, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xe50 = 0x%x, 0xe24 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xe50, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe24, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc1c = 0x%x, 0xca8 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc1c, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xca8, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x58 at Path A = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0x58 at Path B = 0x%x\n", + ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] IQK finished\n")); + +#if defined(CONFIG_RF_DPK_SETTING_SUPPORT) && !defined(CONFIG_SOC_EXT_LNA) && !defined(CONFIG_SOC_EXT_PA) + /*trun on DPK*/ + phy_dpkon_8197f(pDM_Odm); +#endif + +} + + +VOID +PHY_LCCalibrate_8197F( + PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif/*(MP_DRIVER == 1)*/ + #endif + + + + + #if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif + + + #ifdef DISABLE_BB_RF + return; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + #endif + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) */ + if (bSingleTone || bCarrierSuppression) + return; + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_2T2R(pHalData->VersionID)) + phy_LCCalibrate_8197F(pAdapter, TRUE); + else + #endif + { + /* For 88C 1T1R*/ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8197F(pAdapter, FALSE); + #else + phy_LCCalibrate_8197F(pDM_Odm, FALSE); + #endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +phy_path_a_dpk_init_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + /**/ + ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, 0x0001e018); + ODM_SetBBReg(pDM_Odm, 0xb04, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, 0xb28, bMaskDWord, 0x000844aa); + ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, 0x31160200); + + ODM_SetBBReg(pDM_Odm, 0xb30, 0x000fffff, 0x0007bdef); + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); + + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x00021d5f); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x41382e21); + ODM_SetBBReg(pDM_Odm, 0xb0c, bMaskDWord, 0x5b554f48); + ODM_SetBBReg(pDM_Odm, 0xb10, bMaskDWord, 0x6f6b6661); + ODM_SetBBReg(pDM_Odm, 0xb14, bMaskDWord, 0x817d7874); + ODM_SetBBReg(pDM_Odm, 0xb18, bMaskDWord, 0x908c8884); + ODM_SetBBReg(pDM_Odm, 0xb1c, bMaskDWord, 0x9d9a9793); + ODM_SetBBReg(pDM_Odm, 0xb20, bMaskDWord, 0xaaa7a4a1); + ODM_SetBBReg(pDM_Odm, 0xb24, bMaskDWord, 0xb6b3b0ad); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); + + ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, 0x02ce03e8); + ODM_SetBBReg(pDM_Odm, 0xb04, bMaskDWord, 0x01fd024c); + ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x01a101c9); + ODM_SetBBReg(pDM_Odm, 0xb0C, bMaskDWord, 0x016a0183); + ODM_SetBBReg(pDM_Odm, 0xb10, bMaskDWord, 0x01430153); + ODM_SetBBReg(pDM_Odm, 0xb14, bMaskDWord, 0x01280134); + ODM_SetBBReg(pDM_Odm, 0xb18, bMaskDWord, 0x0112011c); + ODM_SetBBReg(pDM_Odm, 0xb1C, bMaskDWord, 0x01000107); + ODM_SetBBReg(pDM_Odm, 0xb20, bMaskDWord, 0x00f200f9); + ODM_SetBBReg(pDM_Odm, 0xb24, bMaskDWord, 0x00e500eb); + ODM_SetBBReg(pDM_Odm, 0xb28, bMaskDWord, 0x00da00e0); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00d200d6); + ODM_SetBBReg(pDM_Odm, 0xb30, bMaskDWord, 0x00c900cd); + ODM_SetBBReg(pDM_Odm, 0xb34, bMaskDWord, 0x00c200c5); + ODM_SetBBReg(pDM_Odm, 0xb38, bMaskDWord, 0x00bb00be); + ODM_SetBBReg(pDM_Odm, 0xb3c, bMaskDWord, 0x00b500b8); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10000304); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10010203); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10020102); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10030101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10040101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10050101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10060101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x10070101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x1008caff); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100980a1); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100a5165); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100b3340); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100c2028); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100d1419); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100e0810); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x100f0506); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01007800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01017800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01027800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01037800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01047800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01057800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01067800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01077800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01087800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01097800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x010F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01107800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01117800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01127800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01137800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01147800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01157800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01167800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01177800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01187800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01197800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x011F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01207800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01217800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01227800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01237800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01247800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01257800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01267800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01277800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01287800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01297800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x012F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01307800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01317800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01327800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01337800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01347800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01357800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01367800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01377800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01387800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x01397800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x013F7800); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02007800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02017800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02027800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02037800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02047800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02057800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02067800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02077800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02087800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02097800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x020F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02107800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02117800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02127800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02137800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02147800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02157800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02167800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02177800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02187800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02197800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x021F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02207800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02217800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02227800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02237800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02247800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02257800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02267800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02277800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02287800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02297800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x022F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02307800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02317800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02327800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02337800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02347800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02357800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02367800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02377800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02387800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x02397800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x023F7800); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + +} + +VOID +phy_path_b_dpk_init_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + /**/ + ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, 0x0001e018); + ODM_SetBBReg(pDM_Odm, 0xb74, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, 0xb98, bMaskDWord, 0x000844aa); + ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, 0x31160200); + + ODM_SetBBReg(pDM_Odm, 0xba0, 0x000fffff, 0x0007bdef); + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); + + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x00021d5f); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x41382e21); + ODM_SetBBReg(pDM_Odm, 0xb7c, bMaskDWord, 0x5b554f48); + ODM_SetBBReg(pDM_Odm, 0xb80, bMaskDWord, 0x6f6b6661); + ODM_SetBBReg(pDM_Odm, 0xb84, bMaskDWord, 0x817d7874); + ODM_SetBBReg(pDM_Odm, 0xb88, bMaskDWord, 0x908c8884); + ODM_SetBBReg(pDM_Odm, 0xb8c, bMaskDWord, 0x9d9a9793); + ODM_SetBBReg(pDM_Odm, 0xb90, bMaskDWord, 0xaaa7a4a1); + ODM_SetBBReg(pDM_Odm, 0xb94, bMaskDWord, 0xb6b3b0ad); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x40000000); + + ODM_SetBBReg(pDM_Odm, 0xb60, bMaskDWord, 0x02ce03e8); + ODM_SetBBReg(pDM_Odm, 0xb64, bMaskDWord, 0x01fd024c); + ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, 0x01a101c9); + ODM_SetBBReg(pDM_Odm, 0xb6C, bMaskDWord, 0x016a0183); + ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, 0x01430153); + ODM_SetBBReg(pDM_Odm, 0xb74, bMaskDWord, 0x01280134); + ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x0112011c); + ODM_SetBBReg(pDM_Odm, 0xb7C, bMaskDWord, 0x01000107); + ODM_SetBBReg(pDM_Odm, 0xb80, bMaskDWord, 0x00f200f9); + ODM_SetBBReg(pDM_Odm, 0xb84, bMaskDWord, 0x00e500eb); + ODM_SetBBReg(pDM_Odm, 0xb88, bMaskDWord, 0x00da00e0); + ODM_SetBBReg(pDM_Odm, 0xb8c, bMaskDWord, 0x00d200d6); + ODM_SetBBReg(pDM_Odm, 0xb90, bMaskDWord, 0x00c900cd); + ODM_SetBBReg(pDM_Odm, 0xb94, bMaskDWord, 0x00c200c5); + ODM_SetBBReg(pDM_Odm, 0xb98, bMaskDWord, 0x00bb00be); + ODM_SetBBReg(pDM_Odm, 0xb9c, bMaskDWord, 0x00b500b8); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20000304); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20010203); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20020102); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20030101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20040101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20050101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20060101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x20070101); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x2008caff); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200980a1); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200a5165); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200b3340); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200c2028); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200d1419); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200e0810); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x200f0506); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04007800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04017800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04027800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04037800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04047800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04057800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04067800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04077800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04087800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04097800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x040F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04107800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04117800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04127800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04137800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04147800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04157800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04167800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04177800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04187800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04197800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x041F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04207800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04217800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04227800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04237800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04247800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04257800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04267800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04277800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04287800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04297800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x042F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04307800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04317800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04327800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04337800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04347800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04357800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04367800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04377800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04387800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x04397800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x043F7800); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0000000d); + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08007800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08017800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08027800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08037800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08047800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08057800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08067800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08077800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08087800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08097800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x080F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08107800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08117800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08127800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08137800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08147800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08157800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08167800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08177800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08187800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08197800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x081F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08207800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08217800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08227800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08237800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08247800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08257800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08267800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08277800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08287800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08297800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x082F7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08307800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08317800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08327800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08337800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08347800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08357800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08367800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08377800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08387800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x08397800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083A7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083B7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083C7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083D7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083E7800); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x083F7800); + + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + +} + + +VOID +phy_set_txrate_index_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + /*Path A*/ + ODM_SetBBReg(pDM_Odm, 0xe08, 0x00007F00, 0x30); + ODM_SetBBReg(pDM_Odm, 0x86c, 0xFFFFFF00, 0x303030); + ODM_SetBBReg(pDM_Odm, 0xe00, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0xe04, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0xe10, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0xe14, bMaskDWord, 0x30303030); + + /*Path B*/ + ODM_SetBBReg(pDM_Odm, 0x838, 0xFFFFFF00, 0x303030); + ODM_SetBBReg(pDM_Odm, 0x86c, 0x000000FF, 0x30); + ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0x834, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, 0x30303030); + ODM_SetBBReg(pDM_Odm, 0x848, bMaskDWord, 0x30303030); + +} + +u1Byte +phy_path_a_gainloss_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + int k; + u1Byte TX_AGC_search = 0x0, result[5] = {0x0}; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xaa000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x5801c); + ODM_Write1Byte(pDM_Odm, 0xb00, 0x18); + ODM_Write1Byte(pDM_Odm, 0xb07, 0xf7); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_SetBBReg(pDM_Odm, 0xb68, 0xffff0000, 0x159f); + ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x41382e21); + ODM_Write1Byte(pDM_Odm, 0xbad, 0x2c); /*1.5dB*/ + ODM_SetBBReg(pDM_Odm, 0xe34, bMaskDWord, 0x10000000); + + ODM_delay_ms(5); + + for (k = 0; k < 5; k++) + { + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_delay_ms(20); + + result[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbdc, 0x0000000f); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] result[%d] = 0x%x\n", k, result[k])); + + if ((k != 0) && (result[k] == result[k-1])) + break; + } + + if (k == 4) + TX_AGC_search = ((result[0] + result[1] + result[2] + result[3] + result[4]) / 5); + else + TX_AGC_search = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbdc, 0x0000000f); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] TXAGC_search_a = 0x%x\n", TX_AGC_search)); + return TX_AGC_search; + +} + +u1Byte +phy_path_b_gainloss_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + int k; + u1Byte TX_AGC_search = 0x0, result[5] = {0x0}; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xaa000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x5801c); + ODM_Write1Byte(pDM_Odm, 0xb70, 0x18); + ODM_Write1Byte(pDM_Odm, 0xb77, 0xf7); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_SetBBReg(pDM_Odm, 0xb6c, 0xffff0000, 0x159f); + ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x41382e21); + ODM_Write1Byte(pDM_Odm, 0xbad, 0x2c); /*1.5dB*/ + ODM_SetBBReg(pDM_Odm, 0xe54, bMaskDWord, 0x10000000); + + ODM_delay_ms(5); + + for (k = 0; k < 5; k++) + { + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_delay_ms(20); + + result[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbec, 0x0000000f); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] result[%d] = 0x%x\n", k, result[k])); + + if ((k != 0) && (result[k] == result[k-1])) + break; + } + + if (k == 4) + TX_AGC_search = ((result[0] + result[1] + result[2] + result[3] + result[4]) / 5); + else + TX_AGC_search = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xbec, 0x0000000f); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] TXAGC_search_b = 0x%x\n", TX_AGC_search)); + return TX_AGC_search; + +} + + +u4Byte +phy_path_a_dodpk_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + u1Byte TX_AGC_search, + u1Byte k +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte REG_B68, result; + u1Byte TX_AGC = 0x0; + + + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x40); + + switch (TX_AGC_search) + { + case 0x0: + REG_B68 = 0x11160200 | (0x19<<10); + TX_AGC = 0x12; + break; + + case 0x1: + REG_B68 = 0x11160200 | (0x1a<<10); + TX_AGC = 0x13; + break; + + case 0x2: + REG_B68 = 0x11160200 | (0x1b<<10); + TX_AGC = 0x14; + break; + + case 0x3: + REG_B68 = 0x11160200 | (0x1c<<10); + TX_AGC = 0x15; + break; + + case 0x4: + REG_B68 = 0x11160200 | (0x1d<<10); + TX_AGC = 0x16; + break; + + case 0x5: + REG_B68 = 0x11160200 | (0x1e<<10); + TX_AGC = 0x17; + break; + + case 0x6: + REG_B68 = 0x11160200 | (0x1f<<10); + TX_AGC = 0x18; + break; + + case 0x7: + REG_B68 = 0x11160200 | (0x00<<10); + TX_AGC = 0x19; + break; + + case 0x8: + REG_B68 = 0x11160200 | (0x01<<10); + TX_AGC = 0x1a; + break; + + case 0x9: + REG_B68 = 0x11160200 | (0x02<<10); + TX_AGC = 0x1b; + break; + + case 0xa: + REG_B68 = 0x11160200 | (0x03<<10); + TX_AGC = 0x1c; + break; + + } + + ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, REG_B68); + /*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0xaa000);*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, (0x58000 | TX_AGC)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a 0x0 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask))); + + pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xb68, 0x00007C00); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb68[%d] = 0x%x, pwsf_2g_a[%d] = 0x%x\n", + k, ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord), k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k])); + //ODM_delay_ms(5); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0xc0); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x40); + ODM_delay_ms(10); + + result = ODM_GetBBReg(pDM_Odm, 0xbd8, (BIT18)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] fail bit = %x\n", result)); + return result; + +} + +u4Byte +phy_path_b_dodpk_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + u1Byte TX_AGC_search, + u1Byte k +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte REG_B6C, result; + u1Byte TX_AGC = 0x0; + + + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x40); + + switch (TX_AGC_search) + { + case 0x0: + REG_B6C = 0x11160200 | (0x19<<10); + TX_AGC = 0x12; + break; + + case 0x1: + REG_B6C = 0x11160200 | (0x1a<<10); + TX_AGC = 0x13; + break; + + case 0x2: + REG_B6C = 0x11160200 | (0x1b<<10); + TX_AGC = 0x14; + break; + + case 0x3: + REG_B6C = 0x11160200 | (0x1c<<10); + TX_AGC = 0x15; + break; + + case 0x4: + REG_B6C = 0x11160200 | (0x1d<<10); + TX_AGC = 0x16; + break; + + case 0x5: + REG_B6C = 0x11160200 | (0x1e<<10); + TX_AGC = 0x17; + break; + + case 0x6: + REG_B6C = 0x11160200 | (0x1f<<10); + TX_AGC = 0x18; + break; + + case 0x7: + REG_B6C = 0x11160200 | (0x00<<10); + TX_AGC = 0x19; + break; + + case 0x8: + REG_B6C = 0x11160200 | (0x01<<10); + TX_AGC = 0x1a; + break; + + case 0x9: + REG_B6C = 0x11160200 | (0x02<<10); + TX_AGC = 0x1b; + break; + + case 0xa: + REG_B6C = 0x11160200 | (0x03<<10); + TX_AGC = 0x1c; + break; + + } + + ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, REG_B6C); + /*ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0xaa000);*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, (0x58000 | TX_AGC)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_b 0x0 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask))); + + pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k] = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xb6c, 0x00007C00); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb6c[%d] = 0x%x, pwsf_2g_b[%d] = 0x%x\n", + k, ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord), k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k])); + //ODM_delay_ms(5); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0xc0); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x40); + ODM_delay_ms(10); + + result = ODM_GetBBReg(pDM_Odm, 0xbd8, (BIT19)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] fail bit = %x\n", result)); + return result; + +} + +BOOLEAN +phy_path_a_iq_check_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + u1Byte group, + u1Byte addr, + BOOLEAN is_even +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte i_val, q_val; + + if (is_even) { + i_val = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x003FF800); + q_val = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x000007FF); + } else { + i_val = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x003FF800); + q_val = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x000007FF); + } + + if (((q_val & 0x400)>>10) == 1) + q_val = 0x800 - q_val; + + if ((addr == 0) && ((i_val*i_val + q_val*q_val) < 0x2851e)) {/* LMS (I^2 + Q^2) < -2dB happen*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x <-2dB\n", group, (i_val*i_val + q_val*q_val))); + return 1; + } else if ((i_val*i_val + q_val*q_val) > 0x47cf2) {/* LMS (I^2 + Q^2) > 0.5dB happen*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x >0.5dB\n", group, (i_val*i_val + q_val*q_val))); + return 1; + } else { + return 0; + } + +} + +BOOLEAN +phy_path_b_iq_check_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + u1Byte group, + u1Byte addr, + BOOLEAN is_even +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte i_val, q_val; + + if (is_even) { + i_val = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x003FF800); + q_val = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x000007FF); + } else { + i_val = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x003FF800); + q_val = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x000007FF); + } + + if (((q_val & 0x400)>>10) == 1) + q_val = 0x800 - q_val; + + if ((addr == 0) && ((i_val*i_val + q_val*q_val) < 0x2851e)) {/* LMS (I^2 + Q^2) < -2dB happen*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x <-2dB\n", group, (i_val*i_val + q_val*q_val))); + return 1; + } else if ((i_val*i_val + q_val*q_val) > 0x47cf2) {/* LMS (I^2 + Q^2) > 0.5dB happen*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] RF_a[%d] I^2 + Q^2 = 0x%x >0.5dB\n", group, (i_val*i_val + q_val*q_val))); + return 1; + } else { + return 0; + } + +} + + +VOID +phy_path_a_pas_read_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN is_gainloss +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + int k; + u4Byte reg_b00, reg_b68, reg_bdc, reg_be0, reg_be4, reg_be8; + + + reg_b00 = ODM_GetBBReg(pDM_Odm, 0xb00, bMaskDWord); + reg_b68 = ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord); + + if(is_gainloss) { + ODM_SetBBReg(pDM_Odm, 0xb68, BIT26, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb68 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xb68, bMaskDWord))); + } + + for (k = 0; k < 8; k++) + { + ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, (0x0101f038 | k)); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb00[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb00, bMaskDWord))); + reg_bdc = ODM_GetBBReg(pDM_Odm, 0xbdc, bMaskDWord); + reg_be0 = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + reg_be4 = ODM_GetBBReg(pDM_Odm, 0xbe4, bMaskDWord); + reg_be8 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_bdc)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_A[%d] = 0x%x\n", k, reg_be8)); + } + + ODM_SetBBReg(pDM_Odm, 0xb00, bMaskDWord, reg_b00); + ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, reg_b68); + +} + +VOID +phy_path_b_pas_read_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN is_gainloss +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + int k; + u4Byte reg_b70, reg_b6c, reg_bec, reg_bf0, reg_bf4, reg_bf8; + + reg_b70 = ODM_GetBBReg(pDM_Odm, 0xb70, bMaskDWord); + reg_b6c = ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord); + + + if(is_gainloss) { + ODM_SetBBReg(pDM_Odm, 0xb6c, BIT26, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb6c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xb6c, bMaskDWord))); + } + + for (k = 0; k < 8; k++) + { + ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, (0x0101f038 | k)); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] 0xb70[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb70, bMaskDWord))); + reg_bec = ODM_GetBBReg(pDM_Odm, 0xbec, bMaskDWord); + reg_bf0 = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + reg_bf4 = ODM_GetBBReg(pDM_Odm, 0xbf4, bMaskDWord); + reg_bf8 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bec)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] PA scan_B[%d] = 0x%x\n", k, reg_bf8)); + } + + ODM_SetBBReg(pDM_Odm, 0xb70, bMaskDWord, reg_b70); + ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, reg_b6c); + +} + +VOID +phy_path_a_dpk_enable_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_Write1Byte(pDM_Odm, 0xb00, 0x98); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_Write1Byte(pDM_Odm, 0xb6a, 0x26); + + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb2b, 0x00); + ODM_delay_ms(10); + + ODM_Write1Byte(pDM_Odm, 0xb07, 0x77); + ODM_SetBBReg(pDM_Odm, 0xb08, bMaskDWord, 0x4c104c10); /*1.5dB*/ + + /*ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000);*/ + /*ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000);*/ + +} + +VOID +phy_path_b_dpk_enable_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + ODM_Write1Byte(pDM_Odm, 0xb70, 0x98); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_Write1Byte(pDM_Odm, 0xb6e, 0x26); + + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x80); + ODM_Write1Byte(pDM_Odm, 0xb9b, 0x00); + ODM_delay_ms(10); + + ODM_Write1Byte(pDM_Odm, 0xb77, 0x77); + ODM_SetBBReg(pDM_Odm, 0xb78, bMaskDWord, 0x4c104c10); /*1.5dB*/ + + /*ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x10000000);*/ + /*ODM_SetBBReg(pDM_Odm, 0xe20, bMaskDWord, 0x00000000);*/ + +} + +u1Byte +phy_dpk_channel_transfer_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u1Byte channel, bandwidth, i; + + channel = *pDM_Odm->pChannel; + bandwidth = *pDM_Odm->pBandWidth; + + if (channel <= 4) + i = 0; + else if (channel >= 5 && channel <= 8) + i = 1; + else if (channel >= 9) + i = 2; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] channel = %d, bandwidth = %d, transfer idx = %d\n", + channel, bandwidth, i)); + + return i; + +} + + +u1Byte +phy_lut_sram_read_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + u1Byte k +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u1Byte addr, i; + u4Byte regb2c; + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + for(addr = 0; addr < 64; addr++) + { + regb2c = (0x00801234 | (addr << 16)); + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, regb2c); + + /*A even*/ + if (phy_path_a_iq_check_8197f(pDM_Odm, k, addr, true)) { + return 0; + } + pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc0, 0x003FFFFF); + + /*A odd*/ + if (phy_path_a_iq_check_8197f(pDM_Odm, k, addr, false)) { + return 0; + } + pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc4, 0x003FFFFF); + + /*B even*/ + if (phy_path_b_iq_check_8197f(pDM_Odm, k, addr, true)) { + return 0; + } + pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbc8, 0x003FFFFF); + + /*B odd*/ + if (phy_path_b_iq_check_8197f(pDM_Odm, k, addr, false)) { + return 0; + } + pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] = ODM_GetBBReg(pDM_Odm, 0xbcc, 0x003FFFFF); + + } + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + +#if (DPK_SRAM_read_DBG_8197F) + + if (k == 2) + { + for (i = 0; i < 3; i++) + { + for(addr = 0; addr < 16; addr++) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_A even 0xbc0[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[i][addr])); + + for(addr = 0; addr < 16; addr++) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_A odd 0xbc4[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[i][addr])); + + for(addr = 0; addr < 16; addr++) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_B even 0xbc8[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[i][addr])); + + for(addr = 0; addr < 16; addr++) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_read_2G_B odd 0xbcc[%d][%2d] = 0x%x\n", i, addr, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[i][addr])); + } + } +#endif + +#if 0 + if (k == 2) + { + printk("bDPPathAOK=%d bDPPathBOK=%d\n", pDM_Odm->RFCalibrateInfo.bDPPathAOK, pDM_Odm->RFCalibrateInfo.bDPPathBOK); + u4Byte j; + + //for (i = 0; i < 3; i++) + { + printk("sram_read pwsf_2g_a[%d]=0x%x pwsf_2g_b[%d]=0x%x\n", k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k], k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]); + } + + //for (i = 0; i < 3; i++) + { + for (j = 0; j < 64; j++) + printk("sram_read lut_2g_even_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_read lut_2g_odd_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_read lut_2g_even_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_read lut_2g_odd_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][j]); + } + } +#endif + +return 1; + +} + +VOID +phy_lut_sram_write_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID +#else + PADAPTER pAdapter +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u1Byte addr, k; + u4Byte regba8_a_even[64] = {0}, regb2c_a_even[64] = {0}; + u4Byte regba8_a_odd[64] = {0}, regb2c_a_odd[64] = {0}; + u4Byte regba8_b_even[64] = {0}, regb2c_b_even[64] = {0}; + u4Byte regba8_b_odd[64] = {0}, regb2c_b_odd[64] = {0}; + + + k = phy_dpk_channel_transfer_8197f(pDM_Odm); + +#if 0 +{ + printk("bDPPathAOK=%d bDPPathBOK=%d\n", pDM_Odm->RFCalibrateInfo.bDPPathAOK, pDM_Odm->RFCalibrateInfo.bDPPathBOK); + u4Byte j; + + //for (i = 0; i < 3; i++) + { + printk("sram_write pwsf_2g_a[%d]=0x%x pwsf_2g_b[%d]=0x%x\n", k, pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k], k, pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]); + } + + //for (i = 0; i < 3; i++) + { + for (j = 0; j < 64; j++) + printk("sram_write lut_2g_even_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_write lut_2g_odd_a[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_write lut_2g_even_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][j]); + + for (j = 0; j < 64; j++) + printk("sram_write lut_2g_odd_b[%2d][%2d]=0x%x\n", k, j, pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][j]); + } +} +#endif + + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xbac, bMaskDWord, 0x00000c00); + + for(addr = 0; addr < 64; addr++) + { + /*A even*/ + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x1); + regba8_a_even[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] & 0x003F0000)>>16; + regb2c_a_even[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_even_a[k][addr] & 0x0000FFFF; + + ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_a_even[addr]); + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_a_even[addr] | (addr<<16))); + +#if (DPK_SRAM_write_DBG_8197F) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A even 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A even 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); +#endif + } + + for(addr = 0; addr < 64; addr++) + { + /*A odd*/ + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x2); + regba8_a_odd[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] & 0x003F0000)>>16; + regb2c_a_odd[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_odd_a[k][addr] & 0x0000FFFF; + + ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_a_odd[addr]); + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_a_odd[addr] | (addr<<16))); + +#if (DPK_SRAM_write_DBG_8197F) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A odd 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_A odd 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); +#endif + } + + for(addr = 0; addr < 64; addr++) + { + /*B even*/ + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x4); + regba8_b_even[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] & 0x003F0000)>>16; + regb2c_b_even[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_even_b[k][addr] & 0x0000FFFF; + + ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_b_even[addr]); + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_b_even[addr] | (addr<<16))); + +#if (DPK_SRAM_write_DBG_8197F) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B even 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B even 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); +#endif + } + + for(addr = 0; addr < 64; addr++) + { + /*B odd*/ + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x0F000000, 0x8); + regba8_b_odd[addr] = (pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] & 0x003F0000)>>16; + regb2c_b_odd[addr] = pDM_Odm->RFCalibrateInfo.lut_2g_odd_b[k][addr] & 0x0000FFFF; + + ODM_SetBBReg(pDM_Odm, 0xba8, 0x0000003F, regba8_b_odd[addr]); + ODM_SetBBReg(pDM_Odm, 0xb2c, 0x003FFFFF, (regb2c_b_odd[addr] | (addr<<16))); + +#if (DPK_SRAM_write_DBG_8197F) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B odd 0xba8[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xba8, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] LUT_SRAM_write_2G_B odd 0xb2c[%2d] = 0x%x\n", addr, ODM_GetBBReg(pDM_Odm, 0xb2c, bMaskDWord))); +#endif + } + + ODM_SetBBReg(pDM_Odm, 0xb2c, bMaskDWord, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0xb68, bMaskDWord, (0x11260200 | (pDM_Odm->RFCalibrateInfo.pwsf_2g_a[k]<<10))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] init pwsf_a[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb68, 0x00007c00))); + + ODM_SetBBReg(pDM_Odm, 0xb6c, bMaskDWord, (0x11260200 | (pDM_Odm->RFCalibrateInfo.pwsf_2g_b[k]<<10))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] init pwsf_b[%d] = 0x%x\n", k, ODM_GetBBReg(pDM_Odm, 0xb6c, 0x00007c00))); + + +} + +VOID +phy_dpk_enable_disable_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN enable +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + if (enable) { /*use dpk result*/ + ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x0); + ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x0); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = 1; + pDM_Odm->RFCalibrateInfo.bDPPathBOK = 1; + } else { /*bypass dpk result*/ + ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x1); + ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x1); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0; + pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0; + } +} + +u1Byte +phy_dpcalibrate_8197f( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PVOID pDM_VOID, +#else + PADAPTER pAdapter, +#endif + BOOLEAN is2T, + u1Byte k + +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + #endif + + u4Byte ADDA_REG[2] = { + 0xd94, rRx_Wait_CCA + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte IQK_BB_REG_92C[17] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, 0x88c, 0xc5c, + 0xc14, 0xc1c, 0x800, 0x880, 0x884, + 0x930, 0x934, 0x93c, 0x92c, 0xc30, + 0xc3c, 0xc84 + }; + + u4Byte Txrate_REG[11] = { + 0xe08, 0x86c, 0xe00, 0xe04, 0xe10, 0xe14, + 0x838, 0x830, 0x834, 0x83c, 0x848 + }; + + u4Byte result_a = 0x1, result_b = 0x1, tmp_rf_a_00, tmp_rf_a_8f, tmp_rf_b_00, tmp_rf_b_8f; + u1Byte TXAGC_a_search = 0x0, TXAGC_b_search = 0x0; + + _PHY_SaveADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, 2); + _PHY_SaveMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, 17); + _PHY_SaveADDARegisters_97F(pDM_Odm, Txrate_REG, pDM_Odm->RFCalibrateInfo.Txrate, 11); + + tmp_rf_a_00 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); + tmp_rf_a_8f = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask); + tmp_rf_b_00 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask); + tmp_rf_b_8f = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask); + + ODM_SetBBReg(pDM_Odm, 0x520, bMaskByte2, 0xff); /*Tx Pause*/ + + phy_path_a_dpk_init_8197f(pDM_Odm); + phy_path_b_dpk_init_8197f(pDM_Odm); + + phy_set_txrate_index_8197f(pDM_Odm); + + ODM_SetBBReg(pDM_Odm, 0xe28, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0xccf008c0); + ODM_SetBBReg(pDM_Odm, 0xc5c, bMaskDWord, 0x80708492); + ODM_SetBBReg(pDM_Odm, 0xd94, bMaskDWord, 0x44FFBB44); + ODM_SetBBReg(pDM_Odm, 0xe70, bMaskDWord, 0x00400040); + ODM_SetBBReg(pDM_Odm, 0x87c, bMaskDWord, 0x004f0201); + ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0xc0000120); + ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0xd8001402); + ODM_SetBBReg(pDM_Odm, 0xc04, bMaskDWord, 0x6f005433); + ODM_SetBBReg(pDM_Odm, 0xc08, bMaskDWord, 0x000804e4); + ODM_SetBBReg(pDM_Odm, 0x874, bMaskDWord, 0x25204000); + ODM_SetBBReg(pDM_Odm, 0xc14, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xc1c, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0x800, BIT24, 0x0); /*disable CCK block*/ + + /*TRSW PA on, LNA off*/ + ODM_SetBBReg(pDM_Odm, 0x930, bMaskDWord, 0xFFFF77FF); + ODM_SetBBReg(pDM_Odm, 0x934, bMaskDWord, 0xFFFFFFF7); + ODM_SetBBReg(pDM_Odm, 0x93c, bMaskDWord, 0xFFFF777F); + ODM_SetBBReg(pDM_Odm, 0x92c, bMaskDWord, 0x0C000108); + + /*set CCA TH to highest*/ + ODM_SetBBReg(pDM_Odm, 0xc3c, 0x000007F8, 0xff); + ODM_SetBBReg(pDM_Odm, 0xc30, 0x0000000f, 0xf); + ODM_SetBBReg(pDM_Odm, 0xc84, 0xf0000000, 0xf); + +#if 1 + /*path A DPK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] ============ Path A[%d] DPK ============\n", k)); + + TXAGC_a_search = phy_path_a_gainloss_8197f(pDM_Odm); + + if (DPK_PAS_DBG_8197F) + phy_path_a_pas_read_8197f(pDM_Odm, TRUE); + + ODM_delay_ms(5); + + result_a = phy_path_a_dodpk_8197f(pDM_Odm, TXAGC_a_search, k); + + if (DPK_PAS_DBG_8197F) + phy_path_a_pas_read_8197f(pDM_Odm, FALSE); + +#endif + +#if 1 + /*path B DPK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] ============ Path B[%d] DPK ============\n", k)); + + TXAGC_b_search = phy_path_b_gainloss_8197f(pDM_Odm); + + if (DPK_PAS_DBG_8197F) + phy_path_b_pas_read_8197f(pDM_Odm, TRUE); + + ODM_delay_ms(5); + + result_b = phy_path_b_dodpk_8197f(pDM_Odm, TXAGC_b_search, k); + + if (DPK_PAS_DBG_8197F) + phy_path_b_pas_read_8197f(pDM_Odm, FALSE); + +#endif + + phy_path_a_dpk_enable_8197f(pDM_Odm); + phy_path_b_dpk_enable_8197f(pDM_Odm); + + if (result_a != 0) + { + ODM_SetBBReg(pDM_Odm, 0xb68, BIT29, 0x1); /*bypass path_A DPD*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Bypass Path_A[%d] DPD!!!!\n", k)); + pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; + pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK PathA need check k=%d\n", k)); + //printk("[DPK] DPK PathA need check k=%d\n", k); + } else { + pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 1; + + if (k == 2 + && pDM_Odm->RFCalibrateInfo.DPPathAResult[0] == 1 + && pDM_Odm->RFCalibrateInfo.DPPathAResult[1] == 1 + && pDM_Odm->RFCalibrateInfo.DPPathAResult[2] == 1) + pDM_Odm->RFCalibrateInfo.bDPPathAOK = 0x1; + } + + if (result_b != 0) + { + ODM_SetBBReg(pDM_Odm, 0xb6c, BIT29, 0x1); /*bypass path_B DPD*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] Bypass Path_B DPD!!!!\n")); + pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; + pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK PathB need check k=%d\n", k)); + //printk("[DPK] DPK PathB need check k=%d\n", k); + + } else { + pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 1; + + if (k == 2 + && pDM_Odm->RFCalibrateInfo.DPPathBResult[0] == 1 + && pDM_Odm->RFCalibrateInfo.DPPathBResult[1] == 1 + && pDM_Odm->RFCalibrateInfo.DPPathBResult[2] == 1) + pDM_Odm->RFCalibrateInfo.bDPPathBOK = 0x1; + } + + _PHY_ReloadADDARegisters_97F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, 2); + _PHY_ReloadMACRegisters_97F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_ReloadADDARegisters_97F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, 17); + _PHY_ReloadADDARegisters_97F(pDM_Odm, Txrate_REG, pDM_Odm->RFCalibrateInfo.Txrate, 11); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, tmp_rf_a_00); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, tmp_rf_a_8f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, tmp_rf_b_00); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, tmp_rf_b_8f); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] DPK Finish!!!!\n")); + +#if 1 + + if((result_a == 0) && (result_b == 0)) + { + if (phy_lut_sram_read_8197f(pDM_Odm, k)) + return 1; + else { + pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; + pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; + return 0; + } + } else { + pDM_Odm->RFCalibrateInfo.DPPathAResult[k] = 0; + pDM_Odm->RFCalibrateInfo.DPPathBResult[k] = 0; + return 0; + } + +#endif +} + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.h b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.h index 6d0d6312424..ea69c5cc3df 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_iqk_8197f.h @@ -1,147 +1,147 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __PHYDM_IQK_8197F_H__ -#define __PHYDM_IQK_8197F_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define MAC_REG_NUM_8197F 2 -#define BB_REG_NUM_8197F 12 -#define RF_REG_NUM_8197F 3 - - -#define LOK_delay_8197F 100 -#define IQK_delay_8197F 100 -#define WBIQK_delay_8197F 100 -#define DPK_PAS_DBG_8197F 0 -#define DPK_SRAM_read_DBG_8197F 0 -#define DPK_SRAM_write_DBG_8197F 0 - - -/*---------------------------End Define Parameters-------------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -DoIQK_8197F( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#else -VOID -DoIQK_8197F( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#endif - -VOID -do_dpk_8197f( - PVOID pDM_VOID, - BOOLEAN is2T, - u1Byte k - ); - - -VOID -phy_dpk_track_8197f( - PVOID pDM_VOID -); - - -VOID -PHY_IQCalibrate_8197F( - PVOID pDM_VOID, - BOOLEAN bReCovery - ); - - - -VOID -PHY_LCCalibrate_8197F( - PVOID pDM_VOID - ); - -void -phy_path_a_dpk_init_8197f( - PVOID pDM_VOID - ); - -void -phy_path_b_dpk_init_8197f( - PVOID pDM_VOID - ); - -u1Byte -phy_dpk_channel_transfer_8197f( - PVOID pDM_VOID - ); - - -u1Byte -phy_lut_sram_read_8197f( - PVOID pDM_VOID, - u1Byte k - ); - -VOID -phy_lut_sram_write_8197f( - PVOID pDM_VOID - ); - -VOID -phy_path_a_dpk_enable_8197f( - PVOID pDM_VOID - ); - -VOID -phy_path_b_dpk_enable_8197f( - PVOID pDM_VOID - ); - -VOID -phy_dpk_enable_disable_8197f( - PVOID pDM_VOID, - u1Byte enable - ); - -VOID -phy_path_a_pas_read_8197f( - PVOID pDM_VOID, - BOOLEAN is_gainloss - ); - -VOID -phy_path_b_pas_read_8197f( - PVOID pDM_VOID, - BOOLEAN is_gainloss - ); - -u1Byte -phy_dpcalibrate_8197f( - PVOID pDM_VOID, - BOOLEAN is2T, - u1Byte k - ); - -#endif /*#ifndef __PHYDM_IQK_8197F_H__*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDM_IQK_8197F_H__ +#define __PHYDM_IQK_8197F_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8197F 2 +#define BB_REG_NUM_8197F 12 +#define RF_REG_NUM_8197F 3 + + +#define LOK_delay_8197F 100 +#define IQK_delay_8197F 100 +#define WBIQK_delay_8197F 100 +#define DPK_PAS_DBG_8197F 0 +#define DPK_SRAM_read_DBG_8197F 0 +#define DPK_SRAM_write_DBG_8197F 0 + + +/*---------------------------End Define Parameters-------------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +DoIQK_8197F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#else +VOID +DoIQK_8197F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#endif + +VOID +do_dpk_8197f( + PVOID pDM_VOID, + BOOLEAN is2T, + u1Byte k + ); + + +VOID +phy_dpk_track_8197f( + PVOID pDM_VOID +); + + +VOID +PHY_IQCalibrate_8197F( + PVOID pDM_VOID, + BOOLEAN bReCovery + ); + + + +VOID +PHY_LCCalibrate_8197F( + PVOID pDM_VOID + ); + +void +phy_path_a_dpk_init_8197f( + PVOID pDM_VOID + ); + +void +phy_path_b_dpk_init_8197f( + PVOID pDM_VOID + ); + +u1Byte +phy_dpk_channel_transfer_8197f( + PVOID pDM_VOID + ); + + +u1Byte +phy_lut_sram_read_8197f( + PVOID pDM_VOID, + u1Byte k + ); + +VOID +phy_lut_sram_write_8197f( + PVOID pDM_VOID + ); + +VOID +phy_path_a_dpk_enable_8197f( + PVOID pDM_VOID + ); + +VOID +phy_path_b_dpk_enable_8197f( + PVOID pDM_VOID + ); + +VOID +phy_dpk_enable_disable_8197f( + PVOID pDM_VOID, + u1Byte enable + ); + +VOID +phy_path_a_pas_read_8197f( + PVOID pDM_VOID, + BOOLEAN is_gainloss + ); + +VOID +phy_path_b_pas_read_8197f( + PVOID pDM_VOID, + BOOLEAN is_gainloss + ); + +u1Byte +phy_dpcalibrate_8197f( + PVOID pDM_VOID, + BOOLEAN is2T, + u1Byte k + ); + +#endif /*#ifndef __PHYDM_IQK_8197F_H__*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.c b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.c index d24f5b0e42e..62c097c022c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.c @@ -1,220 +1,220 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) - -void -odm_ConfigRFReg_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if ((Addr == 0xfe) || (Addr == 0xffe)) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - } -} - -void -odm_ConfigRF_RadioA_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; /* RF_Content: radioa_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8197F(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; /* RF_Content: radiob_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8197F(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigMAC_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_UpdateAgcBigJumpLmt_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte rfGainIdx = (u1Byte)((Data & 0x0FF00000) >> 20); - u1Byte bbGainIdx = (u1Byte)(((Data & 0x0000ff00) >> 8)) << 1; /*97F gain idx need multiply 2*/ - u1Byte agcTableIdx = (u1Byte)((Data & 0x0000f000) >> 12); - u1Byte bigJumpLmtIdx = 0; - static BOOLEAN isLimit; - - if (agcTableIdx > 3) - bigJumpLmtIdx = 1; - else - bigJumpLmtIdx = 0; - - if (Addr != 0xc78) - return; - - if (bbGainIdx > 0x3c) { - if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { - isLimit = TRUE; - pDM_DigTable->bigJumpLmt[bigJumpLmtIdx] = bbGainIdx - 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", bigJumpLmtIdx, pDM_DigTable->bigJumpLmt[bigJumpLmtIdx])); - } - } else - isLimit = FALSE; - - pDM_DigTable->rfGainIdx = rfGainIdx; - -} - -void -odm_ConfigBB_AGC_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - odm_UpdateAgcBigJumpLmt_8197F(pDM_Odm, Addr, Data); - - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { -#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8197F( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) + +void +odm_ConfigRFReg_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if ((Addr == 0xfe) || (Addr == 0xffe)) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void +odm_ConfigRF_RadioA_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; /* RF_Content: radioa_txt */ + u4Byte maskforPhySet = (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8197F(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; /* RF_Content: radiob_txt */ + u4Byte maskforPhySet = (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8197F(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigMAC_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_UpdateAgcBigJumpLmt_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte rfGainIdx = (u1Byte)((Data & 0x0FF00000) >> 20); + u1Byte bbGainIdx = (u1Byte)(((Data & 0x0000ff00) >> 8)) << 1; /*97F gain idx need multiply 2*/ + u1Byte agcTableIdx = (u1Byte)((Data & 0x0000f000) >> 12); + u1Byte bigJumpLmtIdx = 0; + static BOOLEAN isLimit; + + if (agcTableIdx > 3) + bigJumpLmtIdx = 1; + else + bigJumpLmtIdx = 0; + + if (Addr != 0xc78) + return; + + if (bbGainIdx > 0x3c) { + if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { + isLimit = TRUE; + pDM_DigTable->bigJumpLmt[bigJumpLmtIdx] = bbGainIdx - 2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", bigJumpLmtIdx, pDM_DigTable->bigJumpLmt[bigJumpLmtIdx])); + } + } else + isLimit = FALSE; + + pDM_DigTable->rfGainIdx = rfGainIdx; + +} + +void +odm_ConfigBB_AGC_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + odm_UpdateAgcBigJumpLmt_8197F(pDM_Odm, Addr, Data); + + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { +#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8197F( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.h b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.h index 4476107bd3f..604614fb056 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_regconfig8197f.h @@ -1,103 +1,103 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8197F -#define __INC_ODM_REGCONFIG_H_8197F - -#if (RTL8197F_SUPPORT == 1) - -void -odm_ConfigRFReg_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_UpdateAgcBigJumpLmt_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -); - -void -odm_ConfigBB_AGC_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8197F( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8197F( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif /* RTL8197F_SUPPORT == 1*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8197F +#define __INC_ODM_REGCONFIG_H_8197F + +#if (RTL8197F_SUPPORT == 1) + +void +odm_ConfigRFReg_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_UpdateAgcBigJumpLmt_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +); + +void +odm_ConfigBB_AGC_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8197F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8197F( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif /* RTL8197F_SUPPORT == 1*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.c b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.c index 8b1ef60e337..b4148cf2349 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.c +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.c @@ -1,208 +1,208 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================ -// include files -============================================================*/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8197F_SUPPORT == 1) - -s1Byte -odm_CCKRSSI_8197F( - IN PDM_ODM_T pDM_Odm, - IN u1Byte LNA_idx, - IN u1Byte VGA_idx - ) -{ - s1Byte rx_pwr_all; - s1Byte diff_para; - - if ((pDM_Odm->BoardType == (ODM_BOARD_EXT_TRSW|ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_PA)) && (pDM_Odm->PackageType == 1)) - diff_para = -7; - else - diff_para = 7; - - switch (LNA_idx) { - case 7: - rx_pwr_all = -52 + diff_para - 2*(VGA_idx); - break; - - case 6: - rx_pwr_all = -42 + diff_para - 2*(VGA_idx); - break; - - case 5: - rx_pwr_all = -32 + diff_para - 2*(VGA_idx); - break; - - case 4: - rx_pwr_all = -26 + diff_para - 2*(VGA_idx); - break; - - case 3: - rx_pwr_all = -18 + diff_para - 2*(VGA_idx); - break; - - case 2: - rx_pwr_all = -12 + diff_para - 2*(VGA_idx); - break; - - case 1: - rx_pwr_all = -2 + diff_para - 2*(VGA_idx); - break; - - case 0: - rx_pwr_all = 2 + diff_para - 2*(VGA_idx); - break; - - default: - break; - - } - - return rx_pwr_all; - -} - -VOID -phydm_phypara_a_cut( - IN PDM_ODM_T pDM_Odm - ) -{ - - ODM_SetBBReg(pDM_Odm, 0x97c, 0xff000000, 0x20);/*97f A-cut workaround*/ - - ODM_SetBBReg(pDM_Odm, 0xa9c, BIT17, 0);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xa0c, bMaskByte2, 0x7e);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xa0c, bMaskByte1, 0x0);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xa84, bMaskByte2, 0x1f);/*97f A-cut workaround*/ - - ODM_SetBBReg(pDM_Odm, 0x824, BIT14, 0x1);/*pathA r_rxhp_tx*/ - ODM_SetBBReg(pDM_Odm, 0x824, BIT17, 0x1);/*pathA r_rxhp_t2r*/ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT14, 0x1);/*pathB r_rxhp_tx*/ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT17, 0x1);/*pathB r_rxhp_t2r*/ - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT2, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT5, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT8, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT11, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT14, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xce0, BIT2, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc7c, BIT24, 0x1);/*97f A-cut workaround*/ - ODM_SetBBReg(pDM_Odm, 0xc7c, BIT27, 0x1);/*97f A-cut workaround*/ - -} - - -VOID -phydm_dynamic_disable_ecs( - IN PDM_ODM_T pDM_Odm - ) -{ - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - - if ((pDM_Odm->is_disable_dym_ecs == TRUE) || (pDM_Odm->mp_mode == TRUE)) /*use mib to disable this dym function*/ - return; - - if ((pDM_Odm->RSSI_Min < 30) || (FalseAlmCnt->Cnt_all * 4 >= FalseAlmCnt->Cnt_CCA_all)) - ODM_SetBBReg(pDM_Odm, 0x9ac, BIT17, 0); - else if ((pDM_Odm->RSSI_Min >= 34) && (FalseAlmCnt->Cnt_all * 5 <= FalseAlmCnt->Cnt_CCA_all)) - ODM_SetBBReg(pDM_Odm, 0x9ac, BIT17, 1); -} - -void -phydm_dynamic_ant_weighting( - PDM_ODM_T p_dm_odm -) -{ - u8 rssi_l2h = 43, rssi_h2l = 37; - - if (p_dm_odm->is_disable_dym_ant_weighting) - return; - - /* force AGC weighting */ - ODM_SetBBReg(p_dm_odm, 0xc54, BIT0, 1); - /* MRC by AGC table */ - ODM_SetBBReg(p_dm_odm, 0xce8, BIT30, 1); - /*Enable Enable antenna_weighting_shift mechanism*/ - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT29, 1); - - if (p_dm_odm->RSSI_Min_ByPath != 0xFF) { - if (p_dm_odm->RSSI_Min_ByPath >= rssi_l2h) { - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31 | BIT30, 0); /* equal weighting */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, is larger than rssi_l2h = %d, adapt equal weighting for 2SS\n", - p_dm_odm->RSSI_Min_ByPath, - rssi_l2h)); - } - else if (p_dm_odm->RSSI_Min_ByPath <= rssi_h2l) { - /*fix sec_min_wgt = 1/2*/ - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31, 0); - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT30, 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, is smaller than rssi_h2l = %d, adapt AGC weighting\n", - p_dm_odm->RSSI_Min_ByPath, - rssi_h2l)); - } - } else { - /*fix sec_min_wgt = 1/2*/ - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31, 0); - ODM_SetBBReg(p_dm_odm, 0xd5c, BIT30, 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, adapt AGC weighting\n", - p_dm_odm->RSSI_Min_ByPath)); - } -} - - -phydm_hwsetting_8197f( - IN PDM_ODM_T pDM_Odm - ) -{ - phydm_dynamic_disable_ecs(pDM_Odm); - phydm_dynamic_ant_weighting(pDM_Odm); -} - -/*DSC(double side band) = 0 or 3*/ -/*LSC(left side band) = 1*/ -/*USC(right side band) = 2*/ -phydm_api_primary_cca( - IN PDM_ODM_T pDM_Odm, - IN u8 DSC_LSC_USC - ) -{ - u32 dsc_lsc_usc; - - if(pDM_Odm->is_disable_primary_cca == TRUE) - return; - - dsc_lsc_usc = ODM_GetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7); - - if ((dsc_lsc_usc == 0) | (dsc_lsc_usc == 3)) - pDM_Odm->original_pd_threshold = ODM_GetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28); - - ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, DSC_LSC_USC); - - if((DSC_LSC_USC == 0) | (DSC_LSC_USC == 3)) - ODM_SetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28, pDM_Odm->original_pd_threshold); - else - ODM_SetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28, 0); -} -#endif /* RTL8197F_SUPPORT == 1 */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ +// include files +============================================================*/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8197F_SUPPORT == 1) + +s1Byte +odm_CCKRSSI_8197F( + IN PDM_ODM_T pDM_Odm, + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all; + s1Byte diff_para; + + if ((pDM_Odm->BoardType == (ODM_BOARD_EXT_TRSW|ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_PA)) && (pDM_Odm->PackageType == 1)) + diff_para = -7; + else + diff_para = 7; + + switch (LNA_idx) { + case 7: + rx_pwr_all = -52 + diff_para - 2*(VGA_idx); + break; + + case 6: + rx_pwr_all = -42 + diff_para - 2*(VGA_idx); + break; + + case 5: + rx_pwr_all = -32 + diff_para - 2*(VGA_idx); + break; + + case 4: + rx_pwr_all = -26 + diff_para - 2*(VGA_idx); + break; + + case 3: + rx_pwr_all = -18 + diff_para - 2*(VGA_idx); + break; + + case 2: + rx_pwr_all = -12 + diff_para - 2*(VGA_idx); + break; + + case 1: + rx_pwr_all = -2 + diff_para - 2*(VGA_idx); + break; + + case 0: + rx_pwr_all = 2 + diff_para - 2*(VGA_idx); + break; + + default: + break; + + } + + return rx_pwr_all; + +} + +VOID +phydm_phypara_a_cut( + IN PDM_ODM_T pDM_Odm + ) +{ + + ODM_SetBBReg(pDM_Odm, 0x97c, 0xff000000, 0x20);/*97f A-cut workaround*/ + + ODM_SetBBReg(pDM_Odm, 0xa9c, BIT17, 0);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xa0c, bMaskByte2, 0x7e);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xa0c, bMaskByte1, 0x0);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xa84, bMaskByte2, 0x1f);/*97f A-cut workaround*/ + + ODM_SetBBReg(pDM_Odm, 0x824, BIT14, 0x1);/*pathA r_rxhp_tx*/ + ODM_SetBBReg(pDM_Odm, 0x824, BIT17, 0x1);/*pathA r_rxhp_t2r*/ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT14, 0x1);/*pathB r_rxhp_tx*/ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT17, 0x1);/*pathB r_rxhp_t2r*/ + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT2, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT5, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT8, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT11, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT14, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xce0, BIT2, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc7c, BIT24, 0x1);/*97f A-cut workaround*/ + ODM_SetBBReg(pDM_Odm, 0xc7c, BIT27, 0x1);/*97f A-cut workaround*/ + +} + + +VOID +phydm_dynamic_disable_ecs( + IN PDM_ODM_T pDM_Odm + ) +{ + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + + if ((pDM_Odm->is_disable_dym_ecs == TRUE) || (pDM_Odm->mp_mode == TRUE)) /*use mib to disable this dym function*/ + return; + + if ((pDM_Odm->RSSI_Min < 30) || (FalseAlmCnt->Cnt_all * 4 >= FalseAlmCnt->Cnt_CCA_all)) + ODM_SetBBReg(pDM_Odm, 0x9ac, BIT17, 0); + else if ((pDM_Odm->RSSI_Min >= 34) && (FalseAlmCnt->Cnt_all * 5 <= FalseAlmCnt->Cnt_CCA_all)) + ODM_SetBBReg(pDM_Odm, 0x9ac, BIT17, 1); +} + +void +phydm_dynamic_ant_weighting( + PDM_ODM_T p_dm_odm +) +{ + u8 rssi_l2h = 43, rssi_h2l = 37; + + if (p_dm_odm->is_disable_dym_ant_weighting) + return; + + /* force AGC weighting */ + ODM_SetBBReg(p_dm_odm, 0xc54, BIT0, 1); + /* MRC by AGC table */ + ODM_SetBBReg(p_dm_odm, 0xce8, BIT30, 1); + /*Enable Enable antenna_weighting_shift mechanism*/ + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT29, 1); + + if (p_dm_odm->RSSI_Min_ByPath != 0xFF) { + if (p_dm_odm->RSSI_Min_ByPath >= rssi_l2h) { + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31 | BIT30, 0); /* equal weighting */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, is larger than rssi_l2h = %d, adapt equal weighting for 2SS\n", + p_dm_odm->RSSI_Min_ByPath, + rssi_l2h)); + } + else if (p_dm_odm->RSSI_Min_ByPath <= rssi_h2l) { + /*fix sec_min_wgt = 1/2*/ + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31, 0); + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT30, 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, is smaller than rssi_h2l = %d, adapt AGC weighting\n", + p_dm_odm->RSSI_Min_ByPath, + rssi_h2l)); + } + } else { + /*fix sec_min_wgt = 1/2*/ + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT31, 0); + ODM_SetBBReg(p_dm_odm, 0xd5c, BIT30, 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_ANT_WEIGHTING, ODM_DBG_LOUD, ("RSSI_Min_ByPath = %d, adapt AGC weighting\n", + p_dm_odm->RSSI_Min_ByPath)); + } +} + + +phydm_hwsetting_8197f( + IN PDM_ODM_T pDM_Odm + ) +{ + phydm_dynamic_disable_ecs(pDM_Odm); + phydm_dynamic_ant_weighting(pDM_Odm); +} + +/*DSC(double side band) = 0 or 3*/ +/*LSC(left side band) = 1*/ +/*USC(right side band) = 2*/ +phydm_api_primary_cca( + IN PDM_ODM_T pDM_Odm, + IN u8 DSC_LSC_USC + ) +{ + u32 dsc_lsc_usc; + + if(pDM_Odm->is_disable_primary_cca == TRUE) + return; + + dsc_lsc_usc = ODM_GetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7); + + if ((dsc_lsc_usc == 0) | (dsc_lsc_usc == 3)) + pDM_Odm->original_pd_threshold = ODM_GetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28); + + ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, DSC_LSC_USC); + + if((DSC_LSC_USC == 0) | (DSC_LSC_USC == 3)) + ODM_SetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28, pDM_Odm->original_pd_threshold); + else + ODM_SetBBReg(pDM_Odm, 0xc84, BIT31|BIT30|BIT29|BIT28, 0); +} +#endif /* RTL8197F_SUPPORT == 1 */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.h b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.h index f0979b8f7f7..3255c413e58 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.h +++ b/package/kernel/rtl8192cd/phydm/rtl8197f/phydm_rtl8197f.h @@ -1,50 +1,50 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#if (RTL8197F_SUPPORT == 1) -#ifndef __ODM_RTL8197F_H__ -#define __ODM_RTL8197F_H__ - -s1Byte -odm_CCKRSSI_8197F( - IN PDM_ODM_T pDM_Odm, - IN u1Byte LNA_idx, - IN u1Byte VGA_idx - ); - -VOID -phydm_phypara_a_cut( - IN PDM_ODM_T pDM_Odm - ); - -VOID -phydm_hwsetting_8197f( - IN PDM_ODM_T pDM_Odm - ); - -void -phydm_api_primary_cca( - IN PDM_ODM_T pDM_Odm, - IN u8 DSC_LSC_USC - ); - - -#endif /* #define __ODM_RTL8197F_H__ */ -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#if (RTL8197F_SUPPORT == 1) +#ifndef __ODM_RTL8197F_H__ +#define __ODM_RTL8197F_H__ + +s1Byte +odm_CCKRSSI_8197F( + IN PDM_ODM_T pDM_Odm, + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ); + +VOID +phydm_phypara_a_cut( + IN PDM_ODM_T pDM_Odm + ); + +VOID +phydm_hwsetting_8197f( + IN PDM_ODM_T pDM_Odm + ); + +void +phydm_api_primary_cca( + IN PDM_ODM_T pDM_Odm, + IN u8 DSC_LSC_USC + ); + + +#endif /* #define __ODM_RTL8197F_H__ */ +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.c b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.c index 88e26d61268..04c6dd04140 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.c @@ -1,833 +1,833 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8703B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8703B_AGC_TAB[] = { - 0xC78, 0xFC000101, - 0xC78, 0xFB010101, - 0xC78, 0xFA020101, - 0xC78, 0xF9030101, - 0xC78, 0xF8040101, - 0xC78, 0xF7050101, - 0xC78, 0xF6060101, - 0xC78, 0xF5070101, - 0xC78, 0xF4080101, - 0xC78, 0xF3090101, - 0xC78, 0xF20A0101, - 0xC78, 0xF10B0101, - 0xC78, 0xF00C0101, - 0xC78, 0xEF0D0101, - 0xC78, 0xEE0E0101, - 0xC78, 0xED0F0101, - 0xC78, 0xEC100101, - 0xC78, 0xEB110101, - 0xC78, 0xEA120101, - 0xC78, 0xE9130101, - 0xC78, 0xE8140101, - 0xC78, 0xE7150101, - 0xC78, 0xE6160101, - 0xC78, 0xE5170101, - 0xC78, 0xE4180101, - 0xC78, 0xE3190101, - 0xC78, 0x661A0101, - 0xC78, 0x651B0101, - 0xC78, 0x641C0101, - 0xC78, 0x631D0101, - 0xC78, 0x071E0101, - 0xC78, 0x061F0101, - 0xC78, 0x05200101, - 0xC78, 0x04210101, - 0xC78, 0x03220101, - 0xC78, 0xE8230001, - 0xC78, 0xE7240001, - 0xC78, 0xE6250001, - 0xC78, 0xE5260001, - 0xC78, 0xE4270001, - 0xC78, 0x89280001, - 0xC78, 0x88290001, - 0xC78, 0x872A0001, - 0xC78, 0x862B0001, - 0xC78, 0x852C0001, - 0xC78, 0x482D0001, - 0xC78, 0x472E0001, - 0xC78, 0x462F0001, - 0xC78, 0x45300001, - 0xC78, 0x44310001, - 0xC78, 0x07320001, - 0xC78, 0x06330001, - 0xC78, 0x05340001, - 0xC78, 0x04350001, - 0xC78, 0x03360001, - 0xC78, 0x02370001, - 0xC78, 0x01380001, - 0xC78, 0x00390001, - 0xC78, 0x003A0001, - 0xC78, 0x003B0001, - 0xC78, 0x003C0001, - 0xC78, 0x003D0001, - 0xC78, 0x003E0001, - 0xC78, 0x003F0001, - 0xC78, 0x7F002001, - 0xC78, 0x7F012001, - 0xC78, 0x7F022001, - 0xC78, 0x7F032001, - 0xC78, 0x7F042001, - 0xC78, 0x7F052001, - 0xC78, 0x7F062001, - 0xC78, 0x7F072001, - 0xC78, 0x7F082001, - 0xC78, 0x7F092001, - 0xC78, 0x7F0A2001, - 0xC78, 0x7F0B2001, - 0xC78, 0x7F0C2001, - 0xC78, 0x7F0D2001, - 0xC78, 0x7F0E2001, - 0xC78, 0x7F0F2001, - 0xC78, 0x7F102001, - 0xC78, 0x7F112001, - 0xC78, 0x7E122001, - 0xC78, 0x7D132001, - 0xC78, 0x7C142001, - 0xC78, 0x7B152001, - 0xC78, 0x7A162001, - 0xC78, 0x79172001, - 0xC78, 0x78182001, - 0xC78, 0x77192001, - 0xC78, 0x761A2001, - 0xC78, 0x751B2001, - 0xC78, 0x741C2001, - 0xC78, 0x731D2001, - 0xC78, 0x721E2001, - 0xC78, 0x711F2001, - 0xC78, 0x70202001, - 0xC78, 0x6F212001, - 0xC78, 0x6E222001, - 0xC78, 0x6D232001, - 0xC78, 0x6C242001, - 0xC78, 0x6B252001, - 0xC78, 0x6A262001, - 0xC78, 0x69272001, - 0xC78, 0x68282001, - 0xC78, 0x67292001, - 0xC78, 0x662A2001, - 0xC78, 0x652B2001, - 0xC78, 0x642C2001, - 0xC78, 0x632D2001, - 0xC78, 0x622E2001, - 0xC78, 0x612F2001, - 0xC78, 0x60302001, - 0xC78, 0x42312001, - 0xC78, 0x41322001, - 0xC78, 0x40332001, - 0xC78, 0x23342001, - 0xC78, 0x22352001, - 0xC78, 0x21362001, - 0xC78, 0x20372001, - 0xC78, 0x00382001, - 0xC78, 0x02392001, - 0xC78, 0x013A2001, - 0xC78, 0x003B2001, - 0xC78, 0x003C2001, - 0xC78, 0x003D2001, - 0xC78, 0x003E2001, - 0xC78, 0x003F2001, - 0xC78, 0x7F003101, - 0xC78, 0x7F013101, - 0xC78, 0x7F023101, - 0xC78, 0x7F033101, - 0xC78, 0x7F043101, - 0xC78, 0x7F053101, - 0xC78, 0x7F063101, - 0xC78, 0x7E073101, - 0xC78, 0x7D083101, - 0xC78, 0x7C093101, - 0xC78, 0x7B0A3101, - 0xC78, 0x7A0B3101, - 0xC78, 0x790C3101, - 0xC78, 0x780D3101, - 0xC78, 0x770E3101, - 0xC78, 0x760F3101, - 0xC78, 0x75103101, - 0xC78, 0x74113101, - 0xC78, 0x73123101, - 0xC78, 0x72133101, - 0xC78, 0x71143101, - 0xC78, 0x70153101, - 0xC78, 0x6F163101, - 0xC78, 0x69173101, - 0xC78, 0x68183101, - 0xC78, 0x67193101, - 0xC78, 0x661A3101, - 0xC78, 0x651B3101, - 0xC78, 0x641C3101, - 0xC78, 0x631D3101, - 0xC78, 0x621E3101, - 0xC78, 0x611F3101, - 0xC78, 0x60203101, - 0xC78, 0x42213101, - 0xC78, 0x41223101, - 0xC78, 0x40233101, - 0xC78, 0x22243101, - 0xC78, 0x21253101, - 0xC78, 0x20263101, - 0xC78, 0x00273101, - 0xC78, 0x00283101, - 0xC78, 0x00293101, - 0xC78, 0x002A3101, - 0xC78, 0x002B3101, - 0xC78, 0x002C3101, - 0xC78, 0x002D3101, - 0xC78, 0x002E3101, - 0xC78, 0x002F3101, - 0xC78, 0x00303101, - 0xC78, 0x00313101, - 0xC78, 0x00323101, - 0xC78, 0x00333101, - 0xC78, 0x00343101, - 0xC78, 0x00353101, - 0xC78, 0x00363101, - 0xC78, 0x00373101, - 0xC78, 0x00383101, - 0xC78, 0x00393101, - 0xC78, 0x003A3101, - 0xC78, 0x003B3101, - 0xC78, 0x003C3101, - 0xC78, 0x003D3101, - 0xC78, 0x003E3101, - 0xC78, 0x003F3101, - 0xC78, 0xFA403101, - 0xC78, 0xF9413101, - 0xC78, 0xF8423101, - 0xC78, 0xF7433101, - 0xC78, 0xF6443101, - 0xC78, 0xF5453101, - 0xC78, 0xF4463101, - 0xC78, 0xF3473101, - 0xC78, 0xF2483101, - 0xC78, 0xE1493101, - 0xC78, 0xE04A3101, - 0xC78, 0xEF4B3101, - 0xC78, 0xEE4C3101, - 0xC78, 0xED4D3101, - 0xC78, 0xEC4E3101, - 0xC78, 0xEB4F3101, - 0xC78, 0xEA503101, - 0xC78, 0xE9513101, - 0xC78, 0xE8523101, - 0xC78, 0xE7533101, - 0xC78, 0xE6543101, - 0xC78, 0xE5553101, - 0xC78, 0xE4563101, - 0xC78, 0xE3573101, - 0xC78, 0xE2583101, - 0xC78, 0xE1593101, - 0xC78, 0xE05A3101, - 0xC78, 0xC25B3101, - 0xC78, 0xC15C3101, - 0xC78, 0xC05D3101, - 0xC78, 0x825E3101, - 0xC78, 0x815F3101, - 0xC78, 0x80603101, - 0xC78, 0x80613101, - 0xC78, 0x80623101, - 0xC78, 0x80633101, - 0xC78, 0x80643101, - 0xC78, 0x80653101, - 0xC78, 0x80663101, - 0xC78, 0x80673101, - 0xC78, 0x80683101, - 0xC78, 0x80693101, - 0xC78, 0x806A3101, - 0xC78, 0x806B3101, - 0xC78, 0x806C3101, - 0xC78, 0x806D3101, - 0xC78, 0x806E3101, - 0xC78, 0x806F3101, - 0xC78, 0x80703101, - 0xC78, 0x80713101, - 0xC78, 0x80723101, - 0xC78, 0x80733101, - 0xC78, 0x80743101, - 0xC78, 0x80753101, - 0xC78, 0x80763101, - 0xC78, 0x80773101, - 0xC78, 0x80783101, - 0xC78, 0x80793101, - 0xC78, 0x807A3101, - 0xC78, 0x807B3101, - 0xC78, 0x807C3101, - 0xC78, 0x807D3101, - 0xC78, 0x807E3101, - 0xC78, 0x807F3101, - 0xC78, 0xFF402001, - 0xC78, 0xFF412001, - 0xC78, 0xFF422001, - 0xC78, 0xFF432001, - 0xC78, 0xFF442001, - 0xC78, 0xFF452001, - 0xC78, 0xFF462001, - 0xC78, 0xFF472001, - 0xC78, 0xFF482001, - 0xC78, 0xFF492001, - 0xC78, 0xFF4A2001, - 0xC78, 0xFF4B2001, - 0xC78, 0xFF4C2001, - 0xC78, 0xFE4D2001, - 0xC78, 0xFD4E2001, - 0xC78, 0xFC4F2001, - 0xC78, 0xFB502001, - 0xC78, 0xFA512001, - 0xC78, 0xF9522001, - 0xC78, 0xF8532001, - 0xC78, 0xF7542001, - 0xC78, 0xF6552001, - 0xC78, 0xF5562001, - 0xC78, 0xF4572001, - 0xC78, 0xF3582001, - 0xC78, 0xF2592001, - 0xC78, 0xF15A2001, - 0xC78, 0xF05B2001, - 0xC78, 0xEF5C2001, - 0xC78, 0xEE5D2001, - 0xC78, 0xED5E2001, - 0xC78, 0xEC5F2001, - 0xC78, 0xEB602001, - 0xC78, 0xEA612001, - 0xC78, 0xE9622001, - 0xC78, 0xE8632001, - 0xC78, 0xE7642001, - 0xC78, 0xE6652001, - 0xC78, 0xE5662001, - 0xC78, 0xE4672001, - 0xC78, 0xE3682001, - 0xC78, 0xC5692001, - 0xC78, 0xC46A2001, - 0xC78, 0xC36B2001, - 0xC78, 0xA46C2001, - 0xC78, 0x846D2001, - 0xC78, 0x836E2001, - 0xC78, 0x826F2001, - 0xC78, 0x81702001, - 0xC78, 0x80712001, - 0xC78, 0x80722001, - 0xC78, 0x80732001, - 0xC78, 0x80742001, - 0xC78, 0x80752001, - 0xC78, 0x80762001, - 0xC78, 0x80772001, - 0xC78, 0x80782001, - 0xC78, 0x80792001, - 0xC78, 0x807A2001, - 0xC78, 0x807B2001, - 0xC78, 0x807C2001, - 0xC78, 0x807D2001, - 0xC78, 0x807E2001, - 0xC78, 0x807F2001, - 0xC50, 0x69553422, - 0xC50, 0x69553420, - -}; - -void -ODM_ReadAndConfig_MP_8703B_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8703B_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8703B_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8703B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8703B_AGC_TAB(void) -{ - return 17; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8703B_PHY_REG[] = { - 0x800, 0x83045700, - 0x804, 0x00000003, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x02200385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x824, 0x00390204, - 0x828, 0x00000000, - 0x82C, 0x00000000, - 0x830, 0x00000000, - 0x834, 0x00000000, - 0x838, 0x00000000, - 0x83C, 0x00000000, - 0x840, 0x00010000, - 0x844, 0x00000000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00000000, - 0x854, 0x00000000, - 0x858, 0x569A11A9, - 0x85C, 0x01000014, - 0x860, 0x66F60110, - 0x864, 0x061F0649, - 0x868, 0x00000000, - 0x86C, 0x27272700, - 0x870, 0x07000760, - 0x874, 0x25004000, - 0x878, 0x00000808, - 0x87C, 0x004F0201, - 0x880, 0xB0000B1E, - 0x884, 0x00000001, - 0x888, 0x00000000, - 0x88C, 0xCCC000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121111, - 0x910, 0x00000002, - 0x914, 0x00000201, - 0x948, 0x99000000, - 0x94C, 0x00000010, - 0x950, 0x20003800, - 0x954, 0x4A880000, - 0x958, 0x4BC5D87A, - 0x95C, 0x04EB9B79, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0xA08, 0x8C838300, - 0xA0C, 0x2E7F120F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0xD1D80000, - 0xA24, 0x5A7DA0BD, - 0xA28, 0x0000223B, - 0xA2C, 0x00D30000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000007, - 0xA78, 0x00008900, - 0xA7C, 0x225B0606, - 0xA80, 0x2180FA74, - 0xA84, 0x00120000, - 0xA88, 0x040C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x05100000, - 0xA9C, 0x3F000000, - 0xAA0, 0x00000000, - 0xB2C, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05611, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x18800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9AC4B, - 0xC34, 0x31000040, - 0xC38, 0x21688080, - 0xC3C, 0x000016CC, - 0xC40, 0x1F78403F, - 0xC44, 0x00010036, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0xC50, 0x69553420, - 0xC54, 0x43BC0094, - 0xC58, 0x00015967, - 0xC5C, 0x18250492, - 0xC60, 0x00000000, - 0xC64, 0x7112848B, - 0xC68, 0x47C07BFF, - 0xC6C, 0x00000036, - 0xC70, 0x2C7F000D, - 0xC74, 0x020600DB, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0xC80, 0x390000E4, - 0xC84, 0x19F60000, - 0xC88, 0x40000100, - 0xC8C, 0x20200000, - 0xC90, 0x00091521, - 0xC94, 0x00000000, - 0xC98, 0x00121820, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00000000, - 0xCA4, 0x000300A0, - 0xCA8, 0x00000000, - 0xCAC, 0x00000000, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x00222222, - 0xCE4, 0x10000000, - 0xCE8, 0x37644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x00030740, - 0xD04, 0x40020401, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC53, - 0xD18, 0x7A8F5B6F, - 0xD2C, 0xCB979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x98000000, - 0xD3C, 0x40127353, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xE00, 0x2D2D2D2D, - 0xE04, 0x2D2D2D2D, - 0xE08, 0x0390272D, - 0xE10, 0x2D2D2D2D, - 0xE14, 0x2D2D2D2D, - 0xE18, 0x2D2D2D2D, - 0xE1C, 0x2D2D2D2D, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000048, - 0xE68, 0x001B25A4, - 0xE6C, 0x01C00014, - 0xE70, 0x01C00014, - 0xE74, 0x02000014, - 0xE78, 0x02000014, - 0xE7C, 0x02000014, - 0xE80, 0x02000014, - 0xE84, 0x01C00014, - 0xE88, 0x02000014, - 0xE8C, 0x01C00014, - 0xED0, 0x01C00014, - 0xED4, 0x01C00014, - 0xED8, 0x01C00014, - 0xEDC, 0x00000014, - 0xEE0, 0x00000014, - 0xEE8, 0x21555448, - 0xEEC, 0x03C00014, - 0xF14, 0x00000003, - 0xF4C, 0x00000000, - 0xF00, 0x00000300, - -}; - -void -ODM_ReadAndConfig_MP_8703B_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8703B_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8703B_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8703B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8703B_PHY_REG(void) -{ - return 17; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8703B_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 -}; - -void -ODM_ReadAndConfig_MP_8703B_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8703B_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8703B_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8703B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8703B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8703B_AGC_TAB[] = { + 0xC78, 0xFC000101, + 0xC78, 0xFB010101, + 0xC78, 0xFA020101, + 0xC78, 0xF9030101, + 0xC78, 0xF8040101, + 0xC78, 0xF7050101, + 0xC78, 0xF6060101, + 0xC78, 0xF5070101, + 0xC78, 0xF4080101, + 0xC78, 0xF3090101, + 0xC78, 0xF20A0101, + 0xC78, 0xF10B0101, + 0xC78, 0xF00C0101, + 0xC78, 0xEF0D0101, + 0xC78, 0xEE0E0101, + 0xC78, 0xED0F0101, + 0xC78, 0xEC100101, + 0xC78, 0xEB110101, + 0xC78, 0xEA120101, + 0xC78, 0xE9130101, + 0xC78, 0xE8140101, + 0xC78, 0xE7150101, + 0xC78, 0xE6160101, + 0xC78, 0xE5170101, + 0xC78, 0xE4180101, + 0xC78, 0xE3190101, + 0xC78, 0x661A0101, + 0xC78, 0x651B0101, + 0xC78, 0x641C0101, + 0xC78, 0x631D0101, + 0xC78, 0x071E0101, + 0xC78, 0x061F0101, + 0xC78, 0x05200101, + 0xC78, 0x04210101, + 0xC78, 0x03220101, + 0xC78, 0xE8230001, + 0xC78, 0xE7240001, + 0xC78, 0xE6250001, + 0xC78, 0xE5260001, + 0xC78, 0xE4270001, + 0xC78, 0x89280001, + 0xC78, 0x88290001, + 0xC78, 0x872A0001, + 0xC78, 0x862B0001, + 0xC78, 0x852C0001, + 0xC78, 0x482D0001, + 0xC78, 0x472E0001, + 0xC78, 0x462F0001, + 0xC78, 0x45300001, + 0xC78, 0x44310001, + 0xC78, 0x07320001, + 0xC78, 0x06330001, + 0xC78, 0x05340001, + 0xC78, 0x04350001, + 0xC78, 0x03360001, + 0xC78, 0x02370001, + 0xC78, 0x01380001, + 0xC78, 0x00390001, + 0xC78, 0x003A0001, + 0xC78, 0x003B0001, + 0xC78, 0x003C0001, + 0xC78, 0x003D0001, + 0xC78, 0x003E0001, + 0xC78, 0x003F0001, + 0xC78, 0x7F002001, + 0xC78, 0x7F012001, + 0xC78, 0x7F022001, + 0xC78, 0x7F032001, + 0xC78, 0x7F042001, + 0xC78, 0x7F052001, + 0xC78, 0x7F062001, + 0xC78, 0x7F072001, + 0xC78, 0x7F082001, + 0xC78, 0x7F092001, + 0xC78, 0x7F0A2001, + 0xC78, 0x7F0B2001, + 0xC78, 0x7F0C2001, + 0xC78, 0x7F0D2001, + 0xC78, 0x7F0E2001, + 0xC78, 0x7F0F2001, + 0xC78, 0x7F102001, + 0xC78, 0x7F112001, + 0xC78, 0x7E122001, + 0xC78, 0x7D132001, + 0xC78, 0x7C142001, + 0xC78, 0x7B152001, + 0xC78, 0x7A162001, + 0xC78, 0x79172001, + 0xC78, 0x78182001, + 0xC78, 0x77192001, + 0xC78, 0x761A2001, + 0xC78, 0x751B2001, + 0xC78, 0x741C2001, + 0xC78, 0x731D2001, + 0xC78, 0x721E2001, + 0xC78, 0x711F2001, + 0xC78, 0x70202001, + 0xC78, 0x6F212001, + 0xC78, 0x6E222001, + 0xC78, 0x6D232001, + 0xC78, 0x6C242001, + 0xC78, 0x6B252001, + 0xC78, 0x6A262001, + 0xC78, 0x69272001, + 0xC78, 0x68282001, + 0xC78, 0x67292001, + 0xC78, 0x662A2001, + 0xC78, 0x652B2001, + 0xC78, 0x642C2001, + 0xC78, 0x632D2001, + 0xC78, 0x622E2001, + 0xC78, 0x612F2001, + 0xC78, 0x60302001, + 0xC78, 0x42312001, + 0xC78, 0x41322001, + 0xC78, 0x40332001, + 0xC78, 0x23342001, + 0xC78, 0x22352001, + 0xC78, 0x21362001, + 0xC78, 0x20372001, + 0xC78, 0x00382001, + 0xC78, 0x02392001, + 0xC78, 0x013A2001, + 0xC78, 0x003B2001, + 0xC78, 0x003C2001, + 0xC78, 0x003D2001, + 0xC78, 0x003E2001, + 0xC78, 0x003F2001, + 0xC78, 0x7F003101, + 0xC78, 0x7F013101, + 0xC78, 0x7F023101, + 0xC78, 0x7F033101, + 0xC78, 0x7F043101, + 0xC78, 0x7F053101, + 0xC78, 0x7F063101, + 0xC78, 0x7E073101, + 0xC78, 0x7D083101, + 0xC78, 0x7C093101, + 0xC78, 0x7B0A3101, + 0xC78, 0x7A0B3101, + 0xC78, 0x790C3101, + 0xC78, 0x780D3101, + 0xC78, 0x770E3101, + 0xC78, 0x760F3101, + 0xC78, 0x75103101, + 0xC78, 0x74113101, + 0xC78, 0x73123101, + 0xC78, 0x72133101, + 0xC78, 0x71143101, + 0xC78, 0x70153101, + 0xC78, 0x6F163101, + 0xC78, 0x69173101, + 0xC78, 0x68183101, + 0xC78, 0x67193101, + 0xC78, 0x661A3101, + 0xC78, 0x651B3101, + 0xC78, 0x641C3101, + 0xC78, 0x631D3101, + 0xC78, 0x621E3101, + 0xC78, 0x611F3101, + 0xC78, 0x60203101, + 0xC78, 0x42213101, + 0xC78, 0x41223101, + 0xC78, 0x40233101, + 0xC78, 0x22243101, + 0xC78, 0x21253101, + 0xC78, 0x20263101, + 0xC78, 0x00273101, + 0xC78, 0x00283101, + 0xC78, 0x00293101, + 0xC78, 0x002A3101, + 0xC78, 0x002B3101, + 0xC78, 0x002C3101, + 0xC78, 0x002D3101, + 0xC78, 0x002E3101, + 0xC78, 0x002F3101, + 0xC78, 0x00303101, + 0xC78, 0x00313101, + 0xC78, 0x00323101, + 0xC78, 0x00333101, + 0xC78, 0x00343101, + 0xC78, 0x00353101, + 0xC78, 0x00363101, + 0xC78, 0x00373101, + 0xC78, 0x00383101, + 0xC78, 0x00393101, + 0xC78, 0x003A3101, + 0xC78, 0x003B3101, + 0xC78, 0x003C3101, + 0xC78, 0x003D3101, + 0xC78, 0x003E3101, + 0xC78, 0x003F3101, + 0xC78, 0xFA403101, + 0xC78, 0xF9413101, + 0xC78, 0xF8423101, + 0xC78, 0xF7433101, + 0xC78, 0xF6443101, + 0xC78, 0xF5453101, + 0xC78, 0xF4463101, + 0xC78, 0xF3473101, + 0xC78, 0xF2483101, + 0xC78, 0xE1493101, + 0xC78, 0xE04A3101, + 0xC78, 0xEF4B3101, + 0xC78, 0xEE4C3101, + 0xC78, 0xED4D3101, + 0xC78, 0xEC4E3101, + 0xC78, 0xEB4F3101, + 0xC78, 0xEA503101, + 0xC78, 0xE9513101, + 0xC78, 0xE8523101, + 0xC78, 0xE7533101, + 0xC78, 0xE6543101, + 0xC78, 0xE5553101, + 0xC78, 0xE4563101, + 0xC78, 0xE3573101, + 0xC78, 0xE2583101, + 0xC78, 0xE1593101, + 0xC78, 0xE05A3101, + 0xC78, 0xC25B3101, + 0xC78, 0xC15C3101, + 0xC78, 0xC05D3101, + 0xC78, 0x825E3101, + 0xC78, 0x815F3101, + 0xC78, 0x80603101, + 0xC78, 0x80613101, + 0xC78, 0x80623101, + 0xC78, 0x80633101, + 0xC78, 0x80643101, + 0xC78, 0x80653101, + 0xC78, 0x80663101, + 0xC78, 0x80673101, + 0xC78, 0x80683101, + 0xC78, 0x80693101, + 0xC78, 0x806A3101, + 0xC78, 0x806B3101, + 0xC78, 0x806C3101, + 0xC78, 0x806D3101, + 0xC78, 0x806E3101, + 0xC78, 0x806F3101, + 0xC78, 0x80703101, + 0xC78, 0x80713101, + 0xC78, 0x80723101, + 0xC78, 0x80733101, + 0xC78, 0x80743101, + 0xC78, 0x80753101, + 0xC78, 0x80763101, + 0xC78, 0x80773101, + 0xC78, 0x80783101, + 0xC78, 0x80793101, + 0xC78, 0x807A3101, + 0xC78, 0x807B3101, + 0xC78, 0x807C3101, + 0xC78, 0x807D3101, + 0xC78, 0x807E3101, + 0xC78, 0x807F3101, + 0xC78, 0xFF402001, + 0xC78, 0xFF412001, + 0xC78, 0xFF422001, + 0xC78, 0xFF432001, + 0xC78, 0xFF442001, + 0xC78, 0xFF452001, + 0xC78, 0xFF462001, + 0xC78, 0xFF472001, + 0xC78, 0xFF482001, + 0xC78, 0xFF492001, + 0xC78, 0xFF4A2001, + 0xC78, 0xFF4B2001, + 0xC78, 0xFF4C2001, + 0xC78, 0xFE4D2001, + 0xC78, 0xFD4E2001, + 0xC78, 0xFC4F2001, + 0xC78, 0xFB502001, + 0xC78, 0xFA512001, + 0xC78, 0xF9522001, + 0xC78, 0xF8532001, + 0xC78, 0xF7542001, + 0xC78, 0xF6552001, + 0xC78, 0xF5562001, + 0xC78, 0xF4572001, + 0xC78, 0xF3582001, + 0xC78, 0xF2592001, + 0xC78, 0xF15A2001, + 0xC78, 0xF05B2001, + 0xC78, 0xEF5C2001, + 0xC78, 0xEE5D2001, + 0xC78, 0xED5E2001, + 0xC78, 0xEC5F2001, + 0xC78, 0xEB602001, + 0xC78, 0xEA612001, + 0xC78, 0xE9622001, + 0xC78, 0xE8632001, + 0xC78, 0xE7642001, + 0xC78, 0xE6652001, + 0xC78, 0xE5662001, + 0xC78, 0xE4672001, + 0xC78, 0xE3682001, + 0xC78, 0xC5692001, + 0xC78, 0xC46A2001, + 0xC78, 0xC36B2001, + 0xC78, 0xA46C2001, + 0xC78, 0x846D2001, + 0xC78, 0x836E2001, + 0xC78, 0x826F2001, + 0xC78, 0x81702001, + 0xC78, 0x80712001, + 0xC78, 0x80722001, + 0xC78, 0x80732001, + 0xC78, 0x80742001, + 0xC78, 0x80752001, + 0xC78, 0x80762001, + 0xC78, 0x80772001, + 0xC78, 0x80782001, + 0xC78, 0x80792001, + 0xC78, 0x807A2001, + 0xC78, 0x807B2001, + 0xC78, 0x807C2001, + 0xC78, 0x807D2001, + 0xC78, 0x807E2001, + 0xC78, 0x807F2001, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +ODM_ReadAndConfig_MP_8703B_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8703B_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8703B_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8703B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8703B_AGC_TAB(void) +{ + return 17; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8703B_PHY_REG[] = { + 0x800, 0x83045700, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x07000760, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x004F0201, + 0x880, 0xB0000B1E, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0x948, 0x99000000, + 0x94C, 0x00000010, + 0x950, 0x20003800, + 0x954, 0x4A880000, + 0x958, 0x4BC5D87A, + 0x95C, 0x04EB9B79, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xD1D80000, + 0xA24, 0x5A7DA0BD, + 0xA28, 0x0000223B, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00008900, + 0xA7C, 0x225B0606, + 0xA80, 0x2180FA74, + 0xA84, 0x00120000, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x05100000, + 0xA9C, 0x3F000000, + 0xAA0, 0x00000000, + 0xB2C, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x18800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC4B, + 0xC34, 0x31000040, + 0xC38, 0x21688080, + 0xC3C, 0x000016CC, + 0xC40, 0x1F78403F, + 0xC44, 0x00010036, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00015967, + 0xC5C, 0x18250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C07BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020600DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0xC84, 0x19F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x10000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00030740, + 0xD04, 0x40020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC53, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCB979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x98000000, + 0xD3C, 0x40127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000048, + 0xE68, 0x001B25A4, + 0xE6C, 0x01C00014, + 0xE70, 0x01C00014, + 0xE74, 0x02000014, + 0xE78, 0x02000014, + 0xE7C, 0x02000014, + 0xE80, 0x02000014, + 0xE84, 0x01C00014, + 0xE88, 0x02000014, + 0xE8C, 0x01C00014, + 0xED0, 0x01C00014, + 0xED4, 0x01C00014, + 0xED8, 0x01C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0xEE8, 0x21555448, + 0xEEC, 0x03C00014, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +ODM_ReadAndConfig_MP_8703B_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8703B_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8703B_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8703B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8703B_PHY_REG(void) +{ + return 17; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8703B_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 +}; + +void +ODM_ReadAndConfig_MP_8703B_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8703B_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8703B_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8703B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.h b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.h index 8fd05a1720c..1e616b62d6b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8703B_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8703B_H -#define __INC_MP_BB_HW_IMG_8703B_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8703B_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8703B_H +#define __INC_MP_BB_HW_IMG_8703B_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.c b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.c index 269a9353141..b46aff08d4e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.c @@ -1,3989 +1,3989 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8703b/hal8703b_fw.h" -#endif - - -#if (RTL8703B_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8703B_FW_AP[] = { -0xB2, 0x03, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0xF4, 0x49, 0x02, 0x00, -0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x86, 0xAD, 0x02, 0xB8, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xAE, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xB8, 0xCA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xB8, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xAC, 0xC7, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xB8, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x87, 0xB8, 0x02, 0x88, 0xFC, 0x02, 0x80, 0x86, 0x02, 0x80, 0x89, 0x02, 0x80, 0x8C, 0x02, -0xA2, 0x2A, 0x02, 0xAB, 0xC9, 0x02, 0x80, 0x95, 0x02, 0x80, 0x98, 0x02, 0x80, 0x9B, 0x02, 0x80, -0x9E, 0x02, 0x80, 0xA1, 0x02, 0x80, 0xA4, 0x02, 0x80, 0xA7, 0x02, 0x80, 0xAA, 0x02, 0x80, 0xAD, -0x02, 0x80, 0xB0, 0x02, 0x8C, 0x7C, 0x02, 0x80, 0xB6, 0x02, 0x80, 0xB9, 0x02, 0x80, 0xBC, 0x02, -0x80, 0xBF, 0x02, 0x80, 0xC2, 0x02, 0x80, 0xC5, 0x02, 0x80, 0xC8, 0x02, 0x80, 0xCB, 0x02, 0x80, -0xCE, 0x02, 0x80, 0xD1, 0x02, 0xC8, 0x25, 0x02, 0x80, 0xD7, 0x02, 0x80, 0xDA, 0x02, 0x80, 0xDD, -0x02, 0x80, 0xE0, 0x02, 0x80, 0xE3, 0x02, 0x80, 0xE6, 0x02, 0x80, 0xE9, 0x02, 0x80, 0xEC, 0x00, -0x00, 0x00, 0x02, 0x80, 0xF2, 0x00, 0x00, 0x00, 0x02, 0x80, 0xF8, 0x02, 0x80, 0xFB, 0x02, 0x80, -0xFE, 0x02, 0x81, 0x01, 0x02, 0x81, 0x04, 0x02, 0x81, 0x07, 0x02, 0x81, 0x0A, 0x02, 0x81, 0x0D, -0x02, 0x81, 0x10, 0x02, 0x81, 0x13, 0x02, 0x81, 0x16, 0x02, 0x81, 0x19, 0x02, 0x81, 0x1C, 0x02, -0xC8, 0x1F, 0x02, 0x81, 0x22, 0x02, 0x81, 0x25, 0x02, 0x81, 0x28, 0x02, 0x81, 0x2B, 0x02, 0x81, -0x2E, 0x02, 0x81, 0x31, 0x02, 0x96, 0x70, 0x02, 0x94, 0x77, 0x02, 0x95, 0x0A, 0x02, 0x91, 0x89, -0x02, 0xBF, 0x75, 0x02, 0xA3, 0x88, 0x02, 0xC8, 0x79, 0x02, 0x81, 0x49, 0x02, 0x81, 0x4C, 0x02, -0x81, 0x4F, 0x02, 0x81, 0x52, 0x02, 0x81, 0x55, 0x02, 0x81, 0x58, 0x02, 0x81, 0x5B, 0x02, 0x91, -0x94, 0x02, 0x81, 0x61, 0x02, 0x81, 0x64, 0x02, 0xC6, 0x93, 0x02, 0x81, 0x6A, 0x02, 0x81, 0x6D, -0x02, 0x81, 0x70, 0x02, 0x95, 0x68, 0x02, 0x93, 0x2E, 0x02, 0xBC, 0x29, 0x00, 0x00, 0x00, 0x00, -0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0, -0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F, -0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00, -0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, -0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03, 0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00, -0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D, 0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07, -0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00, 0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B, -0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C, 0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 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ArrayLength_MP_8703B_FW_AP); -#endif - *pFirmwareSize = ArrayLength_MP_8703B_FW_AP; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8703B_FW_NIC[] = { -0xB2, 0x03, 0x10, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0xB0, 0x51, 0x02, 0x00, -0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x86, 0xAD, 0x02, 0xC5, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xB5, 0xB5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xC6, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0xC5, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xBC, 0x4E, 0x00, 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0xF0, 0x22, 0xE5, 0x6B, 0xF0, 0xA3, 0xE5, 0x6C, 0xF0, 0x22, 0x90, -0x00, 0x02, 0x12, 0x03, 0x3E, 0xFF, 0x22, 0x7D, 0x05, 0x7F, 0x04, 0x02, 0x9E, 0xE4, 0x7D, 0x20, -0xE4, 0xFF, 0x02, 0x7B, 0x2A, 0xFF, 0x12, 0x02, 0x06, 0xFE, 0x54, 0x0F, 0x22, 0x00, 0x87, 0x16, - -}; -u4Byte ArrayLength_MP_8703B_FW_NIC = 20944; - - -#endif - -void -ODM_ReadFirmware_MP_8703B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8703B_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8703B_FW_NIC, ArrayLength_MP_8703B_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8703B_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8703B_FW_WoWLAN[] = { -0xB2, 0x03, 0x30, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0x24, 0x56, 0x02, 0x00, -0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x88, 0xC2, 0x02, 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0xDA, 0x02, 0x04, -0x31, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x8A, 0x7F, 0x22, 0x90, 0x8F, 0xD4, 0xE0, 0x90, 0x8F, -0xD6, 0x22, 0x12, 0x02, 0x4C, 0x90, 0x8F, 0xBF, 0xE0, 0x22, 0x90, 0x93, 0x64, 0xE0, 0xC3, 0x94, -0x0A, 0x22, 0xF0, 0xE4, 0x90, 0x92, 0xE8, 0xF0, 0xA3, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFD, 0xED, -0xFF, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x22, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0xEB, -0xF0, 0x22, 0x12, 0x02, 0x06, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x12, 0x04, 0xB2, 0xEF, 0x44, 0x80, -0xFF, 0x22, 0x90, 0x8A, 0x7E, 0xE0, 0x54, 0xF7, 0xF0, 0x22, 0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, -0xA3, 0x22, 0xCF, 0x41, -}; -u4Byte ArrayLength_MP_8703B_FW_WoWLAN = 22084; - -#endif - -void -ODM_ReadFirmware_MP_8703B_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8703B_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8703B_FW_WoWLAN, ArrayLength_MP_8703B_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8703B_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8703b/hal8703b_fw.h" +#endif + + +#if (RTL8703B_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8703B_FW_AP[] = { +0xB2, 0x03, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0xF4, 0x49, 0x02, 0x00, +0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x86, 0xAD, 0x02, 0xB8, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x01, 0xB8, 0xE5, 0x63, 0xF0, 0x7F, +0x00, 0x22, 0x90, 0x8F, 0xA8, 0xE0, 0x30, 0xE0, 0x34, 0xC4, 0x13, 0x54, 0x07, 0x20, 0xE0, 0x2D, +0x90, 0x91, 0x1D, 0xE0, 0x04, 0xF0, 0xE0, 0xD3, 0x94, 0xC8, 0x40, 0x21, 0x90, 0x8F, 0xA8, 0xE0, +0x44, 0x20, 0xF0, 0xE4, 0x90, 0x91, 0x1D, 0xF0, 0x90, 0x8F, 0xA8, 0xE0, 0x13, 0x30, 0xE0, 0x0D, +0x90, 0x8A, 0x7E, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x8A, 0x8E, 0x74, 0xD0, 0xF0, 0x22, 0x74, 0x43, +0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0x22, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, +0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0x22, 0x74, 0x23, 0x25, 0x64, 0xF5, 0x82, 0xE4, 0x34, +0x8D, 0x22, 0x12, 0xB0, +}; +u4Byte ArrayLength_MP_8703B_FW_AP = 18964; + +#endif + +void +ODM_ReadFirmware_MP_8703B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8703B_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8703B_FW_AP, ArrayLength_MP_8703B_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8703B_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8703B_FW_NIC[] = { +0xB2, 0x03, 0x10, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0xB0, 0x51, 0x02, 0x00, +0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x86, 0xAD, 0x02, 0xC5, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xB5, 0xB5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC6, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC5, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xBC, 0x4E, 0x00, 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0xF0, 0x22, 0xE5, 0x6B, 0xF0, 0xA3, 0xE5, 0x6C, 0xF0, 0x22, 0x90, +0x00, 0x02, 0x12, 0x03, 0x3E, 0xFF, 0x22, 0x7D, 0x05, 0x7F, 0x04, 0x02, 0x9E, 0xE4, 0x7D, 0x20, +0xE4, 0xFF, 0x02, 0x7B, 0x2A, 0xFF, 0x12, 0x02, 0x06, 0xFE, 0x54, 0x0F, 0x22, 0x00, 0x87, 0x16, + +}; +u4Byte ArrayLength_MP_8703B_FW_NIC = 20944; + + +#endif + +void +ODM_ReadFirmware_MP_8703B_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8703B_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8703B_FW_NIC, ArrayLength_MP_8703B_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8703B_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8703B_FW_WoWLAN[] = { +0xB2, 0x03, 0x30, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x26, 0x17, 0x21, 0x24, 0x56, 0x02, 0x00, +0x4F, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x88, 0xC2, 0x02, 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0x8D, 0x90, 0x8F, 0xCC, 0xE0, 0xFC, 0xA3, 0xE0, +0x22, 0x90, 0x8F, 0xAA, 0x12, 0x86, 0xE9, 0xE4, 0x90, 0x8F, 0xAD, 0xF0, 0x22, 0x7B, 0x01, 0x7A, +0x91, 0x79, 0xB3, 0x90, 0x8F, 0xF5, 0xE0, 0xFD, 0x22, 0x74, 0x21, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0xFC, 0xF5, 0x83, 0xE0, 0x22, 0x90, 0x92, 0xDD, 0xE4, 0x75, 0xF0, 0x02, 0x02, 0x02, 0xE7, 0xF5, +0x83, 0xEF, 0xF0, 0x90, 0x92, 0xBB, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x8F, 0xC9, 0xE0, 0xC3, 0x13, +0x90, 0xFD, 0x10, 0xF0, 0x22, 0x74, 0x12, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22, +0xFD, 0x12, 0x7A, 0xDD, 0x90, 0x92, 0xD8, 0xEF, 0xF0, 0x22, 0x75, 0x1C, 0x91, 0x75, 0x1D, 0x20, +0x75, 0x1E, 0x02, 0x22, 0xF0, 0x7B, 0x18, 0x7D, 0x01, 0x02, 0xB7, 0x13, 0x54, 0x40, 0xFD, 0xEF, +0x54, 0xBF, 0x4D, 0xFF, 0x22, 0x90, 0x93, 0x65, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x92, +0xDA, 0xE0, 0xFF, 0xC3, 0x94, 0x10, 0x22, 0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x22, +0x90, 0x92, 0xCA, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x22, 0xFF, 0xEC, 0x90, 0x8F, 0xDA, 0x02, 0x04, +0x31, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x8A, 0x7F, 0x22, 0x90, 0x8F, 0xD4, 0xE0, 0x90, 0x8F, +0xD6, 0x22, 0x12, 0x02, 0x4C, 0x90, 0x8F, 0xBF, 0xE0, 0x22, 0x90, 0x93, 0x64, 0xE0, 0xC3, 0x94, +0x0A, 0x22, 0xF0, 0xE4, 0x90, 0x92, 0xE8, 0xF0, 0xA3, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFD, 0xED, +0xFF, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x22, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0xEB, +0xF0, 0x22, 0x12, 0x02, 0x06, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x12, 0x04, 0xB2, 0xEF, 0x44, 0x80, +0xFF, 0x22, 0x90, 0x8A, 0x7E, 0xE0, 0x54, 0xF7, 0xF0, 0x22, 0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, +0xA3, 0x22, 0xCF, 0x41, +}; +u4Byte ArrayLength_MP_8703B_FW_WoWLAN = 22084; + +#endif + +void +ODM_ReadFirmware_MP_8703B_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8703B_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8703B_FW_WoWLAN, ArrayLength_MP_8703B_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8703B_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.h b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.h index 443a2513e3f..8c666884e1f 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8703B_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8703B_H -#define __INC_MP_FW_HW_IMG_8703B_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8703B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8703B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8703B_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8703B_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8703B_H +#define __INC_MP_FW_HW_IMG_8703B_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8703B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8703B_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8703B_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.c b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.c index 3046d906b9a..27b867971c1 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.c @@ -1,290 +1,290 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8703B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8703B_MAC_REG[] = { - 0x02F, 0x00000030, - 0x035, 0x00000000, - 0x067, 0x00000002, - 0x092, 0x00000080, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000028, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000028, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000C, - 0x63F, 0x0000000C, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66A, 0x000000B0, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x765, 0x00000018, - 0x76E, 0x00000004, - -}; - -void -ODM_ReadAndConfig_MP_8703B_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8703B_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8703B_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8703B(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8703B_MAC_REG(void) -{ - return 17; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8703B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8703B_MAC_REG[] = { + 0x02F, 0x00000030, + 0x035, 0x00000000, + 0x067, 0x00000002, + 0x092, 0x00000080, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000028, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000028, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000C, + 0x63F, 0x0000000C, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66A, 0x000000B0, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x765, 0x00000018, + 0x76E, 0x00000004, + +}; + +void +ODM_ReadAndConfig_MP_8703B_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8703B_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8703B_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8703B(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8703B_MAC_REG(void) +{ + return 17; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.h b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.h index d9aae210a49..c8d14ce76f9 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8703B_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8703B_H -#define __INC_MP_MAC_HW_IMG_8703B_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8703B_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8703B_H +#define __INC_MP_MAC_HW_IMG_8703B_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.c b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.c index c60101b38c7..5da814bc3e5 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.c @@ -1,997 +1,997 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8703B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8703B_RadioA[] = { - 0x018, 0x00008C01, - 0x0B5, 0x0008C050, - 0x0B1, 0x00054258, - 0x0B2, 0x00054C00, - 0x030, 0x00018000, - 0x031, 0x00000027, - 0x032, 0x000A7F07, - 0x030, 0x00020000, - 0x031, 0x00000027, - 0x032, 0x000E7D87, - 0x01C, 0x000F8635, - 0x0EF, 0x00080000, - 0x030, 0x00008000, - 0x031, 0x00000004, - 0x032, 0x00006105, - 0x0EF, 0x00000000, - 0x0EF, 0x00000400, - 0x041, 0x0000BD54, - 0x041, 0x00003DD4, - 0x041, 0x0000FDD4, - 0x0EF, 0x00000000, - 0x0DF, 0x00000600, - 0x050, 0x0000C6DB, - 0x051, 0x00004505, - 0x052, 0x0000E31D, - 0x053, 0x00040579, - 0x054, 0x00000000, - 0x055, 0x0008206E, - 0x056, 0x00040000, - 0x0EF, 0x00000100, - 0x034, 0x0000ADD7, - 0x034, 0x00009DD4, - 0x034, 0x00008DD1, - 0x034, 0x00007DCE, - 0x034, 0x00006DCB, - 0x034, 0x00005CCE, - 0x034, 0x000048CD, - 0x034, 0x000034CC, - 0x034, 0x0000244F, - 0x034, 0x0000144C, - 0x034, 0x0000004E, - 0x0EF, 0x00000000, - 0x0EF, 0x00002000, - 0x03B, 0x0003801F, - 0x03B, 0x00030002, - 0x03B, 0x00028001, - 0x03B, 0x00020000, - 0x03B, 0x00018003, - 0x03B, 0x00010002, - 0x03B, 0x00008001, - 0x03B, 0x00000000, - 0x0EF, 0x00000000, - 0x082, 0x000C0000, - 0x083, 0x000AF025, - 0x01E, 0x00000C08, - -}; - -void -ODM_ReadAndConfig_MP_8703B_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8703B_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8703B_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8703B(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8703B_RadioA(void) -{ - return 17; -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; -#endif - -void -ODM_ReadAndConfig_MP_8703B_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; -#endif - -void -ODM_ReadAndConfig_MP_8703B_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8703B_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", - "MKK", "2.4G", "20M", "HT", "1T", "01", "28", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", - "MKK", "2.4G", "20M", "HT", "1T", "13", "28", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "26", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", - "MKK", "2.4G", "40M", "HT", "1T", "04", "26", - "FCC", "2.4G", "40M", "HT", "1T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", - "MKK", "2.4G", "40M", "HT", "1T", "05", "26", - "FCC", "2.4G", "40M", "HT", "1T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "28", - "MKK", "2.4G", "40M", "HT", "1T", "06", "26", - "FCC", "2.4G", "40M", "HT", "1T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "28", - "MKK", "2.4G", "40M", "HT", "1T", "07", "26", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "28", - "MKK", "2.4G", "40M", "HT", "1T", "08", "26", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", - "MKK", "2.4G", "40M", "HT", "1T", "09", "26", - "FCC", "2.4G", "40M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", - "MKK", "2.4G", "40M", "HT", "1T", "10", "26", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "26", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", - "MKK", "2.4G", "40M", "HT", "1T", "12", "26", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", - "MKK", "2.4G", "40M", "HT", "1T", "13", "26", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", - "MKK", "2.4G", "40M", "HT", "2T", "12", "26", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", - "MKK", "2.4G", "40M", "HT", "2T", "13", "26", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "30", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "28", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8703B_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8703B_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8703B_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8703B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TxXtalTrack.TXT -******************************************************************************/ - -s1Byte gDeltaSwingTableXtal_MP_N_TxXtalTrack_8703B[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -s1Byte gDeltaSwingTableXtal_MP_P_TxXtalTrack_8703B[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -void -ODM_ReadAndConfig_MP_8703B_TxXtalTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_P, gDeltaSwingTableXtal_MP_P_TxXtalTrack_8703B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_N, gDeltaSwingTableXtal_MP_N_TxXtalTrack_8703B, DELTA_SWINGIDX_SIZE); -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8703B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8703B_RadioA[] = { + 0x018, 0x00008C01, + 0x0B5, 0x0008C050, + 0x0B1, 0x00054258, + 0x0B2, 0x00054C00, + 0x030, 0x00018000, + 0x031, 0x00000027, + 0x032, 0x000A7F07, + 0x030, 0x00020000, + 0x031, 0x00000027, + 0x032, 0x000E7D87, + 0x01C, 0x000F8635, + 0x0EF, 0x00080000, + 0x030, 0x00008000, + 0x031, 0x00000004, + 0x032, 0x00006105, + 0x0EF, 0x00000000, + 0x0EF, 0x00000400, + 0x041, 0x0000BD54, + 0x041, 0x00003DD4, + 0x041, 0x0000FDD4, + 0x0EF, 0x00000000, + 0x0DF, 0x00000600, + 0x050, 0x0000C6DB, + 0x051, 0x00004505, + 0x052, 0x0000E31D, + 0x053, 0x00040579, + 0x054, 0x00000000, + 0x055, 0x0008206E, + 0x056, 0x00040000, + 0x0EF, 0x00000100, + 0x034, 0x0000ADD7, + 0x034, 0x00009DD4, + 0x034, 0x00008DD1, + 0x034, 0x00007DCE, + 0x034, 0x00006DCB, + 0x034, 0x00005CCE, + 0x034, 0x000048CD, + 0x034, 0x000034CC, + 0x034, 0x0000244F, + 0x034, 0x0000144C, + 0x034, 0x0000004E, + 0x0EF, 0x00000000, + 0x0EF, 0x00002000, + 0x03B, 0x0003801F, + 0x03B, 0x00030002, + 0x03B, 0x00028001, + 0x03B, 0x00020000, + 0x03B, 0x00018003, + 0x03B, 0x00010002, + 0x03B, 0x00008001, + 0x03B, 0x00000000, + 0x0EF, 0x00000000, + 0x082, 0x000C0000, + 0x083, 0x000AF025, + 0x01E, 0x00000C08, + +}; + +void +ODM_ReadAndConfig_MP_8703B_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8703B_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8703B_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8703B(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8703B_RadioA(void) +{ + return 17; +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; +#endif + +void +ODM_ReadAndConfig_MP_8703B_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8703B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8703B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8703B[] = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8703B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8703B[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13}; +#endif + +void +ODM_ReadAndConfig_MP_8703B_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8703B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8703B_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", + "MKK", "2.4G", "20M", "HT", "1T", "01", "28", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", + "MKK", "2.4G", "20M", "HT", "1T", "13", "28", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "28", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "28", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "28", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8703B_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8703B_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8703B_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8703B_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8703B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TxXtalTrack.TXT +******************************************************************************/ + +s1Byte gDeltaSwingTableXtal_MP_N_TxXtalTrack_8703B[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +s1Byte gDeltaSwingTableXtal_MP_P_TxXtalTrack_8703B[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +void +ODM_ReadAndConfig_MP_8703B_TxXtalTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8703B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_P, gDeltaSwingTableXtal_MP_P_TxXtalTrack_8703B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_N, gDeltaSwingTableXtal_MP_N_TxXtalTrack_8703B, DELTA_SWINGIDX_SIZE); +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.h b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.h index 2db4563e1de..b83da56a07d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halhwimg8703b_rf.h @@ -1,79 +1,79 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8703B_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8703B_H -#define __INC_MP_RF_HW_IMG_8703B_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_TXPWR_LMT(void); - -/****************************************************************************** -* TxXtalTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8703B_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8703B_TxXtalTrack(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8703B_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8703B_H +#define __INC_MP_RF_HW_IMG_8703B_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_TXPWR_LMT(void); + +/****************************************************************************** +* TxXtalTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8703B_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8703B_TxXtalTrack(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.c b/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.c index 084c728a0c2..cf94c6602a8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.c @@ -1,2353 +1,2353 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -//IQK -#define IQK_DELAY_TIME_8703B 10 -#define LCK_DELAY_TIME_8703B 100 - -/* LTE_COEX */ -#define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 -#define REG_LTECOEX_READ_DATA 0x07C8 -#define REG_LTECOEX_PATH_CONTROL 0x70 - - - -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8703B 6 - -#define IDX_0xC94 0 -#define IDX_0xC80 1 -#define IDX_0xC4C 2 - -#define IDX_0xC14 0 -#define IDX_0xCA0 1 - -#define KEY 0 -#define VAL 1 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8703B( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y -) -{ - s4Byte ele_A = 0, ele_D = 0, ele_C = 0, value32, tmp; - s4Byte ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0; - - RFPath = ODM_RF_PATH_A; - - - if (OFDM_index >= OFDM_TABLE_SIZE) - OFDM_index = OFDM_TABLE_SIZE-1; - else if (OFDM_index < 0) - OFDM_index = 0; - - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - - /* new element D */ - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - ele_D_ext = (((IqkResult_X * ele_D)>>7)&0x01); - - /* new element A */ - if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - ele_A_ext = ((IqkResult_X * ele_D)>>7) & 0x1; - /* new element C */ - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - ele_C_ext = ((IqkResult_Y * ele_D)>>7) & 0x1; - - switch (RFPath) { - case ODM_RF_PATH_A: - /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */ - /* write 0xc80 */ - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - /* write 0xc94 */ - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - /* write 0xc4c */ - value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29); - value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28))) | value32; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - case ODM_RF_PATH_B: - /* write new elements A, C, D to regC88, regC9C, regC4C, and element B is always 0 */ - /* write 0xc88 */ - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - /* write 0xc9c */ - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - /* write 0xc4c */ - value32 = (ele_D_ext << 24) | (ele_A_ext << 27) | (ele_C_ext << 25); - value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT24|BIT27|BIT25))) | value32; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28)); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT24|BIT27|BIT25)); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)ele_A_ext, (u4Byte)ele_C_ext, (u4Byte)ele_D_ext)); -} - -VOID -setCCKFilterCoefficient_8703B( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -) -{ - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][7]); - ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][8]); - ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][9]); - ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][10]); - ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][11]); - ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][12]); - ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][13]); - ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][14]); - ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][15]); -} - -void DoIQK_8703B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_ResetIQKResult(pDM_Odm); - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8703B(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8703B(Adapter, FALSE); -#endif - - -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr_8703B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 34; /* +0dB */ - u1Byte PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F - 1; /* -2dB */ - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -#if (MP_DRIVER == 1) /*win MP */ - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#else /*win normal*/ - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - if (!pMgntInfo->ForcedDataRate) { /*auto rate*/ - if (pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } else { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } -#endif -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (pDM_Odm->mp_mode == TRUE) { /*CE MP*/ - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - } else { /*CE normal*/ - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (pDM_Odm->TxRate != 0xFF) -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } -#endif - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8703B\n")); - - if (TxRate != 0xFF) { - /*2 CCK*/ - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F - 1; - /*2 OFDM*/ - else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if (TxRate == MGN_54M) - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - /*2 HT*/ - else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ - PwrTrackingLimit_OFDM = 38; /*+4dB*/ - else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) { - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8703B CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) -#if (MP_DRIVER != 1) - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); -#else - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[RFPath]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); -#endif -#endif - } else if (Method == BBSWING) { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, pRFCalibrateInfo->Remnant_CCKSwingIdx=%d RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - /* Adjust BB swing by OFDM IQ matrix */ - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck < 0) - Final_CCK_Swing_Index = 0; - - setIqkMatrix_8703B(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - setCCKFilterCoefficient_8703B(pDM_Odm, Final_CCK_Swing_Index); - - } else if (Method == MIX_MODE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, pDM_Odm->Remnant_CCKSwingIdx=%d RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" Final_OFDM_Swing_Index=%d, Final_CCK_Swing_Index=%d RFPath=%d\n", - Final_OFDM_Swing_Index, Final_CCK_Swing_Index, RFPath)); - - - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8703B(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", - PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8703B(pDM_Odm, 0, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8703B(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" Final_CCK_Swing_Index(%d) > PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); - - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - setCCKFilterCoefficient_8703B(pDM_Odm, PwrTrackingLimit_CCK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - - } else if (Final_CCK_Swing_Index < 0) { /* Lowest CCK Index = 0 */ - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" Final_CCK_Swing_Index(%d) < 0 PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); - - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - setCCKFilterCoefficient_8703B(pDM_Odm, 0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - - } else { - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" else Final_CCK_Swing_Index=%d PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); - - setCCKFilterCoefficient_8703B(pDM_Odm, Final_CCK_Swing_Index); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - } - - - - } - - } else { - return; // This method is not supported. - } -} - -VOID -GetDeltaSwingTable_8703B( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - - -VOID -GetDeltaSwingXtalTable_8703B( - PVOID pDM_VOID, - ps1Byte *TemperatureUP_Xtal, - ps1Byte *TemperatureDOWN_Xtal -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - *TemperatureUP_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_P; - *TemperatureDOWN_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_N; -} - - - -VOID -ODM_TxXtalTrackSetXtal_8703B( - PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - s1Byte CrystalCap; - - - CrystalCap = pHalData->CrystalCap & 0x3F; - CrystalCap = CrystalCap + pRFCalibrateInfo->XtalOffset; - - if (CrystalCap < 0) - CrystalCap = 0; - else if (CrystalCap > 63) - CrystalCap = 63; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("CrystalCap(%d)= pHalData->CrystalCap(%d) + pRFCalibrateInfo->XtalOffset(%d)\n", CrystalCap, pHalData->CrystalCap, pRFCalibrateInfo->XtalOffset)); - - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("CrystalCap(0x2c) 0x%X\n", ODM_GetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000))); - - -} - - - -void ConfigureTxpowerTrack_8703B( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8703B; - pConfig->RfPathCount = MAX_PATH_NUM_8703B; - pConfig->ThermalRegAddr = RF_T_METER_8703B; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8703B; - pConfig->DoIQK = DoIQK_8703B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8703B; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8703B; - pConfig->GetDeltaSwingXtalTable = GetDeltaSwingXtalTable_8703B; - pConfig->ODM_TxXtalTrackSetXtal = ODM_TxXtalTrackSetXtal_8703B; -} - - - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - u4Byte regEAC, regE94, regE9C, tmp/*, regEA4*/; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]TX IQK!\n")); - - /*8703b IQK v2.0 20150713*/ - /*1 Tx IQK*/ - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); -/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214030f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*PA, PAD setting*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x7f, bRFRegOffsetMask, 0x0d400); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*path setting*/ - /*Save Original Path Owner, Original GNT*/ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - - /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ -#endif - - /*One shot, path A LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /* delay x ms */ - ODM_delay_ms(IQK_DELAY_TIME_8703B); - Ktime = 0; - while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { - ODM_delay_ms(5); - Ktime++; - } - -#if 1 - /*path setting*/ - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); - - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - -#endif - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /* PA/PAD controlled by 0x0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - - return result; - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif -) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK:Get TXIMR setting\n")); - //1 Get TX_XY - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216000f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //modify RXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x00007); - /*IQK PA off*/ -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x57db7); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*path setting*/ - /*Save Original Path Owner, Original GNT*/ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - - /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ -#endif - - //One shot, path A LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8703B); - Ktime = 0; - while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { - ODM_delay_ms(5); - Ktime++; - } - -#if 1 - /*path setting*/ - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); - - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - - -#endif - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - //Allen 20131125 - tmp = (regE9C & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK\n")); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); -/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - - //modify RXIQK mode table - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x00007); - /*PA off*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); - - /*PA, PAD setting*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x5); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*path setting*/ - /*Save Original Path Owner, Original GNT*/ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - - /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ -#endif - - //One shot, path A LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8703B); - Ktime = 0; - while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { - ODM_delay_ms(5); - Ktime++; - } - -#if 1 - /*path setting*/ - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); - - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - - -#endif - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - // PA/PAD controlled by 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - //Allen 20131125 - tmp = (regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36) && - (((regEA4 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - else //if Tx not OK, ignore Rx - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; -} - - -VOID -_PHY_PathAFillIQKMatrix8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly -) -{ - u4Byte Oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if (bIQKOK) { - - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00) | (TX0_A & 0x3ff); - tmp0xc4c = (((X* Oldval_0>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - //2 Tx IQC - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - - tmp0xc94 = (((TX0_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); - - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][VAL] = tmp0xc94; - - tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F)<<16; - - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL] = tmp0xc80; - - tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_0>>7) & 0x1)<<29); - - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL] = tmp0xc4c; - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathAFillIQKMatrix8703B only Tx OK\n")); - - // <20130226, Kordan> Saving RxIQC, otherwise not initialized. - pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] = 0x40000100; - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; -#endif - - //2 Rx IQC - tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; - - reg = result[final_candidate][3] & 0x3F; - tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); - - pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] = tmp0xc14; - - reg = (result[final_candidate][3] >> 6) & 0xF; - tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); - - pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL] = tmp0xca0; - } -} - -#if 0 -VOID -_PHY_PathBFillIQKMatrix8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - - tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00) | (TX1_A & 0x3ff); - tmp0xc4c = (((X* Oldval_1>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - - /*2 Tx IQC*/ - - tmp0xc94 = (((TX1_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); - - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC94][VAL] = tmp0xc94; - - tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C&0x3F)<<16; - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC80][VAL] = tmp0xc80; - - tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_1>>7) & 0x1)<<29); - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC4C][VAL] = tmp0xc4c; - - if(bTxOnly) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathBFillIQKMatrix8703B only Tx OK\n")); - - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - return; - } - - //2 Rx IQC - reg = result[final_candidate][6]; - tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; - - reg = result[final_candidate][7] & 0x3F; - tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); - - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][VAL] = tmp0xc14; - - reg = (result[final_candidate][7] >> 6) & 0xF; - tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); - - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][VAL] = tmp0xca0; - } -} -#endif - -BOOLEAN -ODM_SetIQCbyRFpath_8703B( - IN PDM_ODM_T pDM_Odm -) -{ - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - - if ((pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] != 0x0)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload RF IQC!!!\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc14 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC14][VAL])); - - /* TX IQC */ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][VAL]>>28)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL]>>31)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL] & BIT29)>>29)); - - /* RX IQC */ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL]); - return TRUE; - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQC value invalid!!!\n")); - return FALSE; - } -} - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -#if 0 - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.*/ - if (pMgntInfo->init_adpt_in_progress == TRUE) { - ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - - /* 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK.*/ - - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if (Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) { - ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -#endif - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum -) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0; i < RegisterNum; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); -} - - -VOID -_PHY_SaveMACRegisters8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum -) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - -} - -VOID -_PHY_ReloadMACRegisters8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn -) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = 0x03c00014; - - - for (i = 0; i < IQK_ADDA_REG_NUM; i++) - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - -} - -VOID -_PHY_MACSettingCalibration8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup -) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -BOOLEAN -phy_SimularityCompare_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 -) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif - -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -//#else - BOOLEAN is2T = TRUE; -//#endif - - s4Byte tmp1 = 0,tmp2 = 0; - - if(is2T) - bound = 8; - else - bound = 4; - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if((result[c1][i]& 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if((result[c2][i]& 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - u4Byte i; - u1Byte PathAOK, PathBOK; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN - }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG - }; - - /*since 92C & 92D have the different define in IQK_BB_REG*/ - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 1; -#else - const u4Byte retryCount = 2; -#endif -#endif - - /* Note: IQ calibration must be performed after loading*/ - /*PHY_REG.txt , and radio_a, radio_b.txt*/ - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if (t == 0) { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t)); - - /* Save ADDA parameters, turn Path A ADDA on*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8703B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters8703B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn8703B(pAdapter, ADDA_REG, TRUE); -#else - _PHY_PathADDAOn8703B(pDM_Odm, ADDA_REG, TRUE); -#endif - - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - //BB setting - /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x25204000); - -//path A TX IQK -#if 1 - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8703B(pAdapter); -#else - PathAOK = phy_PathA_IQK_8703B(pDM_Odm); -#endif - - if (PathAOK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - - } -#endif - -//path A RXIQK -#if 1 - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK8703B(pAdapter); -#else - PathAOK = phy_PathA_RxIQK8703B(pDM_Odm); -#endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Fail!!\n")); - } - } - - if (0x00 == PathAOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK failed!!\n")); - -#endif - - -//path B TX IQK -#if 0 - -#if MP_DRIVER != 1 - if ((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) - || (pDM_Odm->SupportInterface == ODM_ITRF_USB)) -#endif - { - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8703B(pAdapter); -#else - PathBOK = phy_PathB_IQK_8703B(pDM_Odm); -#endif -// if(PathBOK == 0x03){ - if (PathBOK == 0x01) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - - } -#endif - -//path B RX IQK -#if 0 - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK8703B(pAdapter); -#else - PathBOK = phy_PathB_RxIQK8703B(pDM_Odm); -#endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Fail!!\n")); - - } - - - - if (0x00 == PathBOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 IQK failed!!\n")); - - } -#endif - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters8703B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - /* Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters8703B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - //Allen initial gain 0xc50 - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]phy_IQCalibrate_8703B() <==\n")); - -} - - -VOID -phy_LCCalibrate_8703B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T -) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal, cnt; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - - /*Check continuous TX and Packet TX*/ - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - - /*backup RF0x18*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - /*Start LCK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - - ODM_delay_ms(10); - } - - /*Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - - /*Restore original situation*/ - if ((tmpReg&0x70) != 0) { - /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - } else { - /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } - -} - -/* IQK version:V0.4*/ -/* 1. add coex. related setting*/ - -VOID -PHY_IQCalibrate_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery -) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else /* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif/*(MP_DRIVER == 1)*/ - - u1Byte u1bTmp; - u2Byte count=0; -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta - }; - BOOLEAN bReloadIQK = FALSE; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - -#endif - - - if (pDM_Odm->mp_mode == TRUE) { -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* Add to determine IQK ON/OFF in certain case, Suggested by Cheng.*/ - if (!pHalData->IQK_MP_Switch) - return; -#endif - - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ - if (bSingleTone || bCarrierSuppression) - return; -#endif - } - -#if DISABLE_BB_RF - return; -#endif - - - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(bReCovery) -#else//for ODM_WIN - if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]PHY_IQCalibrate_8703B: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - return; - } - - - if (pDM_Odm->mp_mode == FALSE) { -#if MP_DRIVER != 1 -//check if IQK had been done before!! - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc80 = 0x%x\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL])); - if (ODM_SetIQCbyRFpath_8703B(pDM_Odm)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK value is reloaded!!!\n")); - bReloadIQK = TRUE; - } - - if(bReloadIQK) - return; -#endif - } - /*Check & wait if BT is doing IQK*/ - - if (pDM_Odm->mp_mode == FALSE) { -#if MP_DRIVER != 1 - // Set H2C cmd to inform FW (enable). - SetFwWiFiCalibrationCmd(pAdapter, 1); - // Check 0x1e6 - count=0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while (u1bTmp != 0x1 && count < 1000) { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - - if (count >= 1000) - RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - - - // Wait BT IQK finished. - // polling 0x1e7[0]=1 or 300ms timeout - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - while ((!(u1bTmp&BIT0)) && count < 6000) { - PlatformStallExecution(50); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - count++; - } -#endif - } - - //IQK start!!!!!!!!!! - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Start!!!\n")); - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8703B(pAdapter, result, i); -#else - phy_IQCalibrate_8703B(pDM_Odm, result, i); -#endif - - - if (i == 1) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8703B(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8703B(pDM_Odm, result, 0, 1); -#endif - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8703B(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8703B(pDM_Odm, result, 0, 2); -#endif - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8703B(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8703B(pDM_Odm, result, 1, 2); -#endif - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -/* RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));*/ - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: FAIL use default value\n")); - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - } - - // fill IQK matrix - if (RegE94 != 0) - _PHY_PathAFillIQKMatrix8703B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -// if (RegEB4 != 0) -// _PHY_PathBFillIQKMatrix8703B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if (final_candidate < 4) { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - -//fill IQK register - ODM_SetIQCbyRFpath_8703B(pDM_Odm); - - if (pDM_Odm->mp_mode == FALSE) { -#if MP_DRIVER != 1 - // Set H2C cmd to inform FW (disable). - SetFwWiFiCalibrationCmd(pAdapter, 0); - - // Check 0x1e6 - count = 0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while (u1bTmp != 0 && count < 1000) { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - - if (count >= 1000) - RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - -#endif - } - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK finished\n")); -} - - -VOID -PHY_LCCalibrate_8703B( - PVOID pDM_VOID -) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif/*(MP_DRIVER == 1)*/ -#endif - - - - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // Add to Disable Default LCK when Cont Tx, For Lab Test Usage. - if (!pHalData->IQK_MP_Switch) - return; -#endif - - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#if DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - - phy_LCCalibrate_8703B(pDM_Odm, FALSE); - - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID phy_SetRFPathSwitch_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (bMain) { /*Set WIFI S1*/ - ODM_SetBBReg(pDM_Odm, 0x7C4, bMaskLWord, 0x7703); - ODM_SetBBReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); - } else { /*Set BT S0*/ - ODM_SetBBReg(pDM_Odm, 0x7C4, bMaskLWord, 0xCC03); - ODM_SetBBReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); - } -} - -VOID PHY_SetRFPathSwitch_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8703B(pAdapter, bMain, TRUE); -#endif - -} - - -/*return value TRUE => WIFI(S1); FALSE => BT(S0)*/ -BOOLEAN phy_QueryRFPathSwitch_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - if (ODM_GetBBReg(pDM_Odm, 0x7C4, bMaskLWord) == 0x7703) - return TRUE; - else - return FALSE; - -} - - - -/*return value TRUE => WIFI(S1); FALSE => BT(S0)*/ -BOOLEAN PHY_QueryRFPathSwitch_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8703B(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8703B(pDM_Odm, FALSE); -#endif - -} - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +//IQK +#define IQK_DELAY_TIME_8703B 10 +#define LCK_DELAY_TIME_8703B 100 + +/* LTE_COEX */ +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 + + + +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8703B 6 + +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 + +#define IDX_0xC14 0 +#define IDX_0xCA0 1 + +#define KEY 0 +#define VAL 1 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8703B( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + s4Byte ele_A = 0, ele_D = 0, ele_C = 0, value32, tmp; + s4Byte ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0; + + RFPath = ODM_RF_PATH_A; + + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE-1; + else if (OFDM_index < 0) + OFDM_index = 0; + + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + + /* new element D */ + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + ele_D_ext = (((IqkResult_X * ele_D)>>7)&0x01); + + /* new element A */ + if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + ele_A_ext = ((IqkResult_X * ele_D)>>7) & 0x1; + /* new element C */ + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + ele_C_ext = ((IqkResult_Y * ele_D)>>7) & 0x1; + + switch (RFPath) { + case ODM_RF_PATH_A: + /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */ + /* write 0xc80 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + /* write 0xc94 */ + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + /* write 0xc4c */ + value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29); + value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28))) | value32; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + case ODM_RF_PATH_B: + /* write new elements A, C, D to regC88, regC9C, regC4C, and element B is always 0 */ + /* write 0xc88 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + /* write 0xc9c */ + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + /* write 0xc4c */ + value32 = (ele_D_ext << 24) | (ele_A_ext << 27) | (ele_C_ext << 25); + value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT24|BIT27|BIT25))) | value32; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28)); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT24|BIT27|BIT25)); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)ele_A_ext, (u4Byte)ele_C_ext, (u4Byte)ele_D_ext)); +} + +VOID +setCCKFilterCoefficient_8703B( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +) +{ + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][7]); + ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][8]); + ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][9]); + ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][10]); + ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][11]); + ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][12]); + ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][13]); + ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][14]); + ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[CCKSwingIndex][15]); +} + +void DoIQK_8703B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_ResetIQKResult(pDM_Odm); + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8703B(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8703B(Adapter, FALSE); +#endif + + +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8703B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 34; /* +0dB */ + u1Byte PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F - 1; /* -2dB */ + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#if (MP_DRIVER == 1) /*win MP */ + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#else /*win normal*/ + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + if (!pMgntInfo->ForcedDataRate) { /*auto rate*/ + if (pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } else { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } +#endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (pDM_Odm->mp_mode == TRUE) { /*CE MP*/ + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + } else { /*CE normal*/ + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (pDM_Odm->TxRate != 0xFF) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } +#endif + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8703B\n")); + + if (TxRate != 0xFF) { + /*2 CCK*/ + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F - 1; + /*2 OFDM*/ + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + /*2 HT*/ + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ + PwrTrackingLimit_OFDM = 38; /*+4dB*/ + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) { + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8703B CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) +#if (MP_DRIVER != 1) + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); +#else + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[RFPath]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); +#endif +#endif + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, pRFCalibrateInfo->Remnant_CCKSwingIdx=%d RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); + + /* Adjust BB swing by OFDM IQ matrix */ + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + setIqkMatrix_8703B(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + setCCKFilterCoefficient_8703B(pDM_Odm, Final_CCK_Swing_Index); + + } else if (Method == MIX_MODE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, pDM_Odm->Remnant_CCKSwingIdx=%d RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" Final_OFDM_Swing_Index=%d, Final_CCK_Swing_Index=%d RFPath=%d\n", + Final_OFDM_Swing_Index, Final_CCK_Swing_Index, RFPath)); + + + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /*BBSwing higher then Limit*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8703B(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", + PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8703B(pDM_Odm, 0, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8703B(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" Final_CCK_Swing_Index(%d) > PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); + + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + setCCKFilterCoefficient_8703B(pDM_Odm, PwrTrackingLimit_CCK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + + } else if (Final_CCK_Swing_Index < 0) { /* Lowest CCK Index = 0 */ + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" Final_CCK_Swing_Index(%d) < 0 PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); + + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + setCCKFilterCoefficient_8703B(pDM_Odm, 0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + + } else { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" else Final_CCK_Swing_Index=%d PwrTrackingLimit_CCK(%d)\n", Final_CCK_Swing_Index, PwrTrackingLimit_CCK)); + + setCCKFilterCoefficient_8703B(pDM_Odm, Final_CCK_Swing_Index); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + } + + + + } + + } else { + return; // This method is not supported. + } +} + +VOID +GetDeltaSwingTable_8703B( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + + +VOID +GetDeltaSwingXtalTable_8703B( + PVOID pDM_VOID, + ps1Byte *TemperatureUP_Xtal, + ps1Byte *TemperatureDOWN_Xtal +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + *TemperatureUP_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_P; + *TemperatureDOWN_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_N; +} + + + +VOID +ODM_TxXtalTrackSetXtal_8703B( + PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + s1Byte CrystalCap; + + + CrystalCap = pHalData->CrystalCap & 0x3F; + CrystalCap = CrystalCap + pRFCalibrateInfo->XtalOffset; + + if (CrystalCap < 0) + CrystalCap = 0; + else if (CrystalCap > 63) + CrystalCap = 63; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("CrystalCap(%d)= pHalData->CrystalCap(%d) + pRFCalibrateInfo->XtalOffset(%d)\n", CrystalCap, pHalData->CrystalCap, pRFCalibrateInfo->XtalOffset)); + + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("CrystalCap(0x2c) 0x%X\n", ODM_GetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000))); + + +} + + + +void ConfigureTxpowerTrack_8703B( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8703B; + pConfig->RfPathCount = MAX_PATH_NUM_8703B; + pConfig->ThermalRegAddr = RF_T_METER_8703B; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8703B; + pConfig->DoIQK = DoIQK_8703B; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8703B; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8703B; + pConfig->GetDeltaSwingXtalTable = GetDeltaSwingXtalTable_8703B; + pConfig->ODM_TxXtalTrackSetXtal = ODM_TxXtalTrackSetXtal_8703B; +} + + + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regE94, regE9C, tmp/*, regEA4*/; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]TX IQK!\n")); + + /*8703b IQK v2.0 20150713*/ + /*1 Tx IQK*/ + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); +/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214030f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*PA, PAD setting*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x7f, bRFRegOffsetMask, 0x0d400); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*path setting*/ + /*Save Original Path Owner, Original GNT*/ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + + /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ +#endif + + /*One shot, path A LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + ODM_delay_ms(IQK_DELAY_TIME_8703B); + Ktime = 0; + while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { + ODM_delay_ms(5); + Ktime++; + } + +#if 1 + /*path setting*/ + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); + + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + +#endif + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /* PA/PAD controlled by 0x0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + + return result; + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK:Get TXIMR setting\n")); + //1 Get TX_XY + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8216000f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //modify RXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x00007); + /*IQK PA off*/ +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x57db7); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*path setting*/ + /*Save Original Path Owner, Original GNT*/ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + + /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ +#endif + + //One shot, path A LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8703B); + Ktime = 0; + while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { + ODM_delay_ms(5); + Ktime++; + } + +#if 1 + /*path setting*/ + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); + + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + + +#endif + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + //Allen 20131125 + tmp = (regE9C & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK\n")); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); +/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + + //modify RXIQK mode table + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x00007); + /*PA off*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); + + /*PA, PAD setting*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x5); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*path setting*/ + /*Save Original Path Owner, Original GNT*/ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + + /*set GNT_WL=1/GNT_BT=0 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x00007700); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); /*0x70[26] =1 --> Path Owner to WiFi*/ +#endif + + //One shot, path A LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8703B); + Ktime = 0; + while ((ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord) == 0) && Ktime < 10) { + ODM_delay_ms(5); + Ktime++; + } + +#if 1 + /*path setting*/ + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); + + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + + +#endif + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + // PA/PAD controlled by 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + //Allen 20131125 + tmp = (regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36) && + (((regEA4 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + else //if Tx not OK, ignore Rx + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; +} + + +VOID +_PHY_PathAFillIQKMatrix8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly +) +{ + u4Byte Oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if (bIQKOK) { + + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00) | (TX0_A & 0x3ff); + tmp0xc4c = (((X* Oldval_0>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //2 Tx IQC + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + + tmp0xc94 = (((TX0_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); + + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][VAL] = tmp0xc94; + + tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F)<<16; + + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL] = tmp0xc80; + + tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_0>>7) & 0x1)<<29); + + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL] = tmp0xc4c; + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathAFillIQKMatrix8703B only Tx OK\n")); + + // <20130226, Kordan> Saving RxIQC, otherwise not initialized. + pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] = 0x40000100; + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; +#endif + + //2 Rx IQC + tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; + + reg = result[final_candidate][3] & 0x3F; + tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); + + pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] = tmp0xc14; + + reg = (result[final_candidate][3] >> 6) & 0xF; + tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); + + pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL] = tmp0xca0; + } +} + +#if 0 +VOID +_PHY_PathBFillIQKMatrix8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00) | (TX1_A & 0x3ff); + tmp0xc4c = (((X* Oldval_1>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + + /*2 Tx IQC*/ + + tmp0xc94 = (((TX1_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); + + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC94][VAL] = tmp0xc94; + + tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C&0x3F)<<16; + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC80][VAL] = tmp0xc80; + + tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_1>>7) & 0x1)<<29); + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8703B[PATH_S0][IDX_0xC4C][VAL] = tmp0xc4c; + + if(bTxOnly) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathBFillIQKMatrix8703B only Tx OK\n")); + + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + return; + } + + //2 Rx IQC + reg = result[final_candidate][6]; + tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; + + reg = result[final_candidate][7] & 0x3F; + tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); + + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xC14][VAL] = tmp0xc14; + + reg = (result[final_candidate][7] >> 6) & 0xF; + tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); + + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8703B[PATH_S0][IDX_0xCA0][VAL] = tmp0xca0; + } +} +#endif + +BOOLEAN +ODM_SetIQCbyRFpath_8703B( + IN PDM_ODM_T pDM_Odm +) +{ + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + + if ((pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL] != 0x0)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload RF IQC!!!\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc14 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC14][VAL])); + + /* TX IQC */ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8703B[IDX_0xC94][VAL]>>28)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL]>>31)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8703B[IDX_0xC4C][VAL] & BIT29)>>29)); + + /* RX IQC */ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8703B[IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8703B[IDX_0xCA0][VAL]); + return TRUE; + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQC value invalid!!!\n")); + return FALSE; + } +} + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +#if 0 + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.*/ + if (pMgntInfo->init_adpt_in_progress == TRUE) { + ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + + /* 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK.*/ + + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if (Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) { + ODM_RT_TRACE(pDM_Odm, COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +#endif + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0; i < RegisterNum; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + +} + +VOID +_PHY_ReloadMACRegisters8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn +) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = 0x03c00014; + + + for (i = 0; i < IQK_ADDA_REG_NUM; i++) + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + +} + +VOID +_PHY_MACSettingCalibration8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +BOOLEAN +phy_SimularityCompare_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 +) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +//#else + BOOLEAN is2T = TRUE; +//#endif + + s4Byte tmp1 = 0,tmp2 = 0; + + if(is2T) + bound = 8; + else + bound = 4; + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if((result[c1][i]& 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if((result[c2][i]& 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + /*since 92C & 92D have the different define in IQK_BB_REG*/ + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 1; +#else + const u4Byte retryCount = 2; +#endif +#endif + + /* Note: IQ calibration must be performed after loading*/ + /*PHY_REG.txt , and radio_a, radio_b.txt*/ + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if (t == 0) { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t)); + + /* Save ADDA parameters, turn Path A ADDA on*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8703B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters8703B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn8703B(pAdapter, ADDA_REG, TRUE); +#else + _PHY_PathADDAOn8703B(pDM_Odm, ADDA_REG, TRUE); +#endif + + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + //BB setting + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x25204000); + +//path A TX IQK +#if 1 + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8703B(pAdapter); +#else + PathAOK = phy_PathA_IQK_8703B(pDM_Odm); +#endif + + if (PathAOK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + + } +#endif + +//path A RXIQK +#if 1 + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK8703B(pAdapter); +#else + PathAOK = phy_PathA_RxIQK8703B(pDM_Odm); +#endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Fail!!\n")); + } + } + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK failed!!\n")); + +#endif + + +//path B TX IQK +#if 0 + +#if MP_DRIVER != 1 + if ((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) + || (pDM_Odm->SupportInterface == ODM_ITRF_USB)) +#endif + { + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8703B(pAdapter); +#else + PathBOK = phy_PathB_IQK_8703B(pDM_Odm); +#endif +// if(PathBOK == 0x03){ + if (PathBOK == 0x01) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + + } +#endif + +//path B RX IQK +#if 0 + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK8703B(pAdapter); +#else + PathBOK = phy_PathB_RxIQK8703B(pDM_Odm); +#endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Fail!!\n")); + + } + + + + if (0x00 == PathBOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 IQK failed!!\n")); + + } +#endif + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters8703B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters8703B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + /* Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters8703B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters8703B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + //Allen initial gain 0xc50 + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]phy_IQCalibrate_8703B() <==\n")); + +} + + +VOID +phy_LCCalibrate_8703B( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T +) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal, cnt; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + + /*Check continuous TX and Packet TX*/ + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + + /*backup RF0x18*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + /*Start LCK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); + + for (cnt = 0; cnt < 100; cnt++) { + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + + ODM_delay_ms(10); + } + + /*Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + + /*Restore original situation*/ + if ((tmpReg&0x70) != 0) { + /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + } else { + /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } + +} + +/* IQK version:V0.4*/ +/* 1. add coex. related setting*/ + +VOID +PHY_IQCalibrate_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else /* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif/*(MP_DRIVER == 1)*/ + + u1Byte u1bTmp; + u2Byte count=0; +#endif + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + BOOLEAN bReloadIQK = FALSE; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + +#endif + + + if (pDM_Odm->mp_mode == TRUE) { +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* Add to determine IQK ON/OFF in certain case, Suggested by Cheng.*/ + if (!pHalData->IQK_MP_Switch) + return; +#endif + + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ + if (bSingleTone || bCarrierSuppression) + return; +#endif + } + +#if DISABLE_BB_RF + return; +#endif + + + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_WIN + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]PHY_IQCalibrate_8703B: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + + + if (pDM_Odm->mp_mode == FALSE) { +#if MP_DRIVER != 1 +//check if IQK had been done before!! + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc80 = 0x%x\n", pRFCalibrateInfo->TxIQC_8703B[IDX_0xC80][VAL])); + if (ODM_SetIQCbyRFpath_8703B(pDM_Odm)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK value is reloaded!!!\n")); + bReloadIQK = TRUE; + } + + if(bReloadIQK) + return; +#endif + } + /*Check & wait if BT is doing IQK*/ + + if (pDM_Odm->mp_mode == FALSE) { +#if MP_DRIVER != 1 + // Set H2C cmd to inform FW (enable). + SetFwWiFiCalibrationCmd(pAdapter, 1); + // Check 0x1e6 + count=0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while (u1bTmp != 0x1 && count < 1000) { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + + if (count >= 1000) + RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + + + // Wait BT IQK finished. + // polling 0x1e7[0]=1 or 300ms timeout + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + while ((!(u1bTmp&BIT0)) && count < 6000) { + PlatformStallExecution(50); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + count++; + } +#endif + } + + //IQK start!!!!!!!!!! + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Start!!!\n")); + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8703B(pAdapter, result, i); +#else + phy_IQCalibrate_8703B(pDM_Odm, result, i); +#endif + + + if (i == 1) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8703B(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8703B(pDM_Odm, result, 0, 1); +#endif + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8703B(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8703B(pDM_Odm, result, 0, 2); +#endif + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8703B(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8703B(pDM_Odm, result, 1, 2); +#endif + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +/* RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));*/ + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: FAIL use default value\n")); + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + + // fill IQK matrix + if (RegE94 != 0) + _PHY_PathAFillIQKMatrix8703B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +// if (RegEB4 != 0) +// _PHY_PathBFillIQKMatrix8703B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if (final_candidate < 4) { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8703B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters8703B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + +//fill IQK register + ODM_SetIQCbyRFpath_8703B(pDM_Odm); + + if (pDM_Odm->mp_mode == FALSE) { +#if MP_DRIVER != 1 + // Set H2C cmd to inform FW (disable). + SetFwWiFiCalibrationCmd(pAdapter, 0); + + // Check 0x1e6 + count = 0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while (u1bTmp != 0 && count < 1000) { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + + if (count >= 1000) + RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + +#endif + } + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK finished\n")); +} + + +VOID +PHY_LCCalibrate_8703B( + PVOID pDM_VOID +) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif/*(MP_DRIVER == 1)*/ +#endif + + + + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // Add to Disable Default LCK when Cont Tx, For Lab Test Usage. + if (!pHalData->IQK_MP_Switch) + return; +#endif + + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + + phy_LCCalibrate_8703B(pDM_Odm, FALSE); + + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID phy_SetRFPathSwitch_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (bMain) { /*Set WIFI S1*/ + ODM_SetBBReg(pDM_Odm, 0x7C4, bMaskLWord, 0x7703); + ODM_SetBBReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); + } else { /*Set BT S0*/ + ODM_SetBBReg(pDM_Odm, 0x7C4, bMaskLWord, 0xCC03); + ODM_SetBBReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); + } +} + +VOID PHY_SetRFPathSwitch_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8703B(pAdapter, bMain, TRUE); +#endif + +} + + +/*return value TRUE => WIFI(S1); FALSE => BT(S0)*/ +BOOLEAN phy_QueryRFPathSwitch_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + if (ODM_GetBBReg(pDM_Odm, 0x7C4, bMaskLWord) == 0x7703) + return TRUE; + else + return FALSE; + +} + + + +/*return value TRUE => WIFI(S1); FALSE => BT(S0)*/ +BOOLEAN PHY_QueryRFPathSwitch_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8703B(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8703B(pDM_Odm, FALSE); +#endif + +} + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.h b/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.h index ea20502b24a..7c13a1c738c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/halphyrf_8703b.h @@ -1,135 +1,135 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8703B_H__ -#define __HAL_PHY_RF_8703B_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define index_mapping_NUM_8703B 15 -#define AVG_THERMAL_NUM_8703B 4 -#define RF_T_METER_8703B 0x42 - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -#include "../halphyrf_win.h" -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#include "../halphyrf_ce.h" -#endif - -void ConfigureTxpowerTrack_8703B( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8703B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr_8703B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -ODM_TxXtalTrackSetXtal_8703B( - PVOID pDM_VOID -); - - -//1 7. IQK - -void -PHY_IQCalibrate_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - -BOOLEAN -ODM_SetIQCbyRFpath_8703B( - IN PDM_ODM_T pDM_Odm - ); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8703B( - PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8703B( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration_8703B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8703B_H__ +#define __HAL_PHY_RF_8703B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define index_mapping_NUM_8703B 15 +#define AVG_THERMAL_NUM_8703B 4 +#define RF_T_METER_8703B 0x42 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#include "../halphyrf_win.h" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#include "../halphyrf_ce.h" +#endif + +void ConfigureTxpowerTrack_8703B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8703B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8703B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +ODM_TxXtalTrackSetXtal_8703B( + PVOID pDM_VOID +); + + +//1 7. IQK + +void +PHY_IQCalibrate_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + +BOOLEAN +ODM_SetIQCbyRFpath_8703B( + IN PDM_ODM_T pDM_Odm + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8703B( + PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8703B( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8703B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.c b/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.c index e6455753096..c13bd5abfc4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.c @@ -1,219 +1,219 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8703B_SUPPORT == 1) - -void -odm_ConfigRFReg_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if(Addr == 0xfe || Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else - { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } -} - - -void -odm_ConfigRF_RadioA_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigRF_RadioC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_C, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigRF_RadioD_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_D, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else - { -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - } - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8703B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8703B_SUPPORT == 1) + +void +odm_ConfigRFReg_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigRF_RadioC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_C, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigRF_RadioD_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8703B(pDM_Odm, Addr, Data, ODM_RF_PATH_D, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + } + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8703B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.h b/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.h index 8086bca3032..7fde2e77980 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/phydm_regconfig8703b.h @@ -1,109 +1,109 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8703B -#define __INC_ODM_REGCONFIG_H_8703B - -#if (RTL8703B_SUPPORT == 1) - -void -odm_ConfigRFReg_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioD_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8703B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8703B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8703B +#define __INC_ODM_REGCONFIG_H_8703B + +#if (RTL8703B_SUPPORT == 1) + +void +odm_ConfigRFReg_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioD_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8703B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8703B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8703b/version_rtl8703b.h b/package/kernel/rtl8192cd/phydm/rtl8703b/version_rtl8703b.h index 14bcb6f0593..6331b552744 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8703b/version_rtl8703b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8703b/version_rtl8703b.h @@ -1,10 +1,10 @@ -/*RTL8703B PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8703B 20150915 -#define COMMIT_BY_8703B "BB_Luke" -#define RELEASE_VERSION_8703B 17 +/*RTL8703B PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8703B 20150915 +#define COMMIT_BY_8703B "BB_Luke" +#define RELEASE_VERSION_8703B 17 diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/hal8723breg.h b/package/kernel/rtl8192cd/phydm/rtl8723b/hal8723breg.h index 2d088c5e2e8..987032342b5 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/hal8723breg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/hal8723breg.h @@ -1,862 +1,862 @@ -/***************************************************************************** - * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. - * - * Module: __INC_HAL8723BREG_H - * - * - * Note: 1. Define Mac register address and corresponding bit mask map - * - * - * Export: Constants, macro, functions(API), global variables(None). - * - * Abbrev: - * - * History: - * Data Who Remark - * - *****************************************************************************/ -#ifndef __INC_HAL8723BREG_H -#define __INC_HAL8723BREG_H - - - -//============================================================ -// -//============================================================ - -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -#define REG_SYS_ISO_CTRL_8723B 0x0000 // 2 Byte -#define REG_SYS_FUNC_EN_8723B 0x0002 // 2 Byte -#define REG_APS_FSMCO_8723B 0x0004 // 4 Byte -#define REG_SYS_CLKR_8723B 0x0008 // 2 Byte -#define REG_9346CR_8723B 0x000A // 2 Byte -#define REG_EE_VPD_8723B 0x000C // 2 Byte -#define REG_AFE_MISC_8723B 0x0010 // 1 Byte -#define REG_SPS0_CTRL_8723B 0x0011 // 7 Byte -#define REG_SPS_OCP_CFG_8723B 0x0018 // 4 Byte -#define REG_RSV_CTRL_8723B 0x001C // 3 Byte -#define REG_RF_CTRL_8723B 0x001F // 1 Byte -#define REG_LPLDO_CTRL_8723B 0x0023 // 1 Byte -#define REG_AFE_XTAL_CTRL_8723B 0x0024 // 4 Byte -#define REG_AFE_PLL_CTRL_8723B 0x0028 // 4 Byte -#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c // 4 Byte -#define REG_EFUSE_CTRL_8723B 0x0030 -#define REG_EFUSE_TEST_8723B 0x0034 -#define REG_PWR_DATA_8723B 0x0038 -#define REG_CAL_TIMER_8723B 0x003C -#define REG_ACLK_MON_8723B 0x003E -#define REG_GPIO_MUXCFG_8723B 0x0040 -#define REG_GPIO_IO_SEL_8723B 0x0042 -#define REG_MAC_PINMUX_CFG_8723B 0x0043 -#define REG_GPIO_PIN_CTRL_8723B 0x0044 -#define REG_GPIO_INTM_8723B 0x0048 -#define REG_LEDCFG0_8723B 0x004C -#define REG_LEDCFG1_8723B 0x004D -#define REG_LEDCFG2_8723B 0x004E -#define REG_LEDCFG3_8723B 0x004F -#define REG_FSIMR_8723B 0x0050 -#define REG_FSISR_8723B 0x0054 -#define REG_HSIMR_8723B 0x0058 -#define REG_HSISR_8723B 0x005c -#define REG_GPIO_EXT_CTRL 0x0060 -#define REG_MULTI_FUNC_CTRL_8723B 0x0068 -#define REG_GPIO_STATUS_8723B 0x006C -#define REG_SDIO_CTRL_8723B 0x0070 -#define REG_OPT_CTRL_8723B 0x0074 -#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 -#define REG_MCUFWDL_8723B 0x0080 -#define REG_FW_DBG_STATUS_8723B 0x0088 -#define REG_FW_DBG_CTRL_8723B 0x008F -#define REG_SYSON_FSM_MON_8723B 0x00A0 -#define REG_HIMR0_8723B 0x00B0 -#define REG_HISR0_8723B 0x00B4 -#define REG_HIMR1_8723B 0x00B8 -#define REG_HISR1_8723B 0x00BC -#define REG_PMC_DBG_CTRL2_8723B 0x00CC -#define REG_EFUSE_BURN_GNT_8723B 0x00CF -#define REG_HPON_FSM_8723B 0x00EC -#define REG_SYS_CFG_8723B 0x00F0 -#define REG_SYS_CFG1_8723B 0x00FC -#define REG_ROM_VERSION 0x00FD - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -#define REG_CR_8723B 0x0100 -#define REG_PBP_8723B 0x0104 -#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 -#define REG_TRXDMA_CTRL_8723B 0x010C -#define REG_TRXFF_BNDY_8723B 0x0114 -#define REG_TRXFF_STATUS_8723B 0x0118 -#define REG_RXFF_PTR_8723B 0x011C -#define REG_CPWM_8723B 0x012F -#define REG_FWIMR_8723B 0x0130 -#define REG_FWISR_8723B 0x0134 -#define REG_FTIMR_8723B 0x0138 -#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 -#define REG_RXPKTBUF_CTRL_8723B 0x0142 -#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 -#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 - -#define REG_TC0_CTRL_8723B 0x0150 -#define REG_TC1_CTRL_8723B 0x0154 -#define REG_TC2_CTRL_8723B 0x0158 -#define REG_TC3_CTRL_8723B 0x015C -#define REG_TC4_CTRL_8723B 0x0160 -#define REG_TCUNIT_BASE_8723B 0x0164 -#define REG_RSVD3_8723B 0x0168 -#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE -#define REG_C2HEVT_CLEAR_8723B 0x01AF -#define REG_MCUTST_1_8723B 0x01C0 -#define REG_MCUTST_2_8723B 0x01C4 -#define REG_MCUTST_WOWLAN_8723B 0x01C7 -#define REG_FMETHR_8723B 0x01C8 -#define REG_HMETFR_8723B 0x01CC -#define REG_HMEBOX_0_8723B 0x01D0 -#define REG_HMEBOX_1_8723B 0x01D4 -#define REG_HMEBOX_2_8723B 0x01D8 -#define REG_HMEBOX_3_8723B 0x01DC -#define REG_LLT_INIT_8723B 0x01E0 -#define REG_HMEBOX_EXT0_8723B 0x01F0 -#define REG_HMEBOX_EXT1_8723B 0x01F4 -#define REG_HMEBOX_EXT2_8723B 0x01F8 -#define REG_HMEBOX_EXT3_8723B 0x01FC - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -#define REG_RQPN_8723B 0x0200 -#define REG_FIFOPAGE_8723B 0x0204 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define REG_DWBCN0_CTRL_8723B REG_TDECTRL -#else -#define REG_TDECTRL_8723B 0x0208 -#endif -#define REG_TXDMA_OFFSET_CHK_8723B 0x020C -#define REG_TXDMA_STATUS_8723B 0x0210 -#define REG_RQPN_NPQ_8723B 0x0214 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define REG_DWBCN1_CTRL_8723B 0x0228 -#else -#define REG_TDECTRL1_8723B 0x0228 -#endif - -//----------------------------------------------------- -// -// 0x0280h ~ 0x02FFh RXDMA Configuration -// -//----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH_8723B 0x0280 -#define REG_FW_UPD_RDPTR_8723B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 -#define REG_RXDMA_CONTROL_8723B 0x0286 // Control the RX DMA. -#define REG_RXPKT_NUM_8723B 0x0287 // The number of packets in RXPKTBUF. -#define REG_RXDMA_STATUS_8723B 0x0288 -#define REG_RXDMA_PRO_8723B 0x0290 -#define REG_EARLY_MODE_CONTROL_8723B 0x02BC -#define REG_RSVD5_8723B 0x02F0 -#define REG_RSVD6_8723B 0x02F4 - - -//----------------------------------------------------- -// -// 0x0300h ~ 0x03FFh PCIe -// -//----------------------------------------------------- -#define REG_PCIE_CTRL_REG_8723B 0x0300 -#define REG_INT_MIG_8723B 0x0304 // Interrupt Migration -#define REG_BCNQ_DESA_8723B 0x0308 // TX Beacon Descriptor Address -#define REG_HQ_DESA_8723B 0x0310 // TX High Queue Descriptor Address -#define REG_MGQ_DESA_8723B 0x0318 // TX Manage Queue Descriptor Address -#define REG_VOQ_DESA_8723B 0x0320 // TX VO Queue Descriptor Address -#define REG_VIQ_DESA_8723B 0x0328 // TX VI Queue Descriptor Address -#define REG_BEQ_DESA_8723B 0x0330 // TX BE Queue Descriptor Address -#define REG_BKQ_DESA_8723B 0x0338 // TX BK Queue Descriptor Address -#define REG_RX_DESA_8723B 0x0340 // RX Queue Descriptor Address -#define REG_DBI_WDATA_8723B 0x0348 // DBI Write Data -#define REG_DBI_RDATA_8723B 0x034C // DBI Read Data -#define REG_DBI_ADDR_8723B 0x0350 // DBI Address -#define REG_DBI_FLAG_8723B 0x0352 // DBI Read/Write Flag -#define REG_MDIO_WDATA_8723B 0x0354 // MDIO for Write PCIE PHY -#define REG_MDIO_RDATA_8723B 0x0356 // MDIO for Reads PCIE PHY -#define REG_MDIO_CTL_8723B 0x0358 // MDIO for Control -#define REG_DBG_SEL_8723B 0x0360 // Debug Selection Register -#define REG_PCIE_HRPWM_8723B 0x0361 //PCIe RPWM -#define REG_PCIE_HCPWM_8723B 0x0363 //PCIe CPWM -#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A //PCIE Multi-Fethc Control - -// spec version 11 -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -#define REG_VOQ_INFORMATION_8723B 0x0400 -#define REG_VIQ_INFORMATION_8723B 0x0404 -#define REG_BEQ_INFORMATION_8723B 0x0408 -#define REG_BKQ_INFORMATION_8723B 0x040C -#define REG_MGQ_INFORMATION_8723B 0x0410 -#define REG_HGQ_INFORMATION_8723B 0x0414 -#define REG_BCNQ_INFORMATION_8723B 0x0418 -#define REG_TXPKT_EMPTY_8723B 0x041A - -#define REG_FWHW_TXQ_CTRL_8723B 0x0420 -#define REG_HWSEQ_CTRL_8723B 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 -#define REG_LIFECTRL_CTRL_8723B 0x0426 -#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 -#define REG_SPEC_SIFS_8723B 0x0428 -#define REG_RL_8723B 0x042A -#define REG_TXBF_CTRL_8723B 0x042C -#define REG_DARFRC_8723B 0x0430 -#define REG_RARFRC_8723B 0x0438 -#define REG_RRSR_8723B 0x0440 -#define REG_ARFR0_8723B 0x0444 -#define REG_ARFR1_8723B 0x044C -#define REG_CCK_CHECK_8723B 0x0454 -#define REG_AMPDU_MAX_TIME_8723B 0x0456 -#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8723B 0x0458 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D -#define REG_NDPA_OPT_CTRL_8723B 0x045F -#define REG_FAST_EDCA_CTRL_8723B 0x0460 -#define REG_RD_RESP_PKT_TH_8723B 0x0463 -#define REG_DATA_SC_8723B 0x0483 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8723B 0x04B4 -#define REG_POWER_STAGE2_8723B 0x04B8 -#define REG_AMPDU_BURST_MODE_8723B 0x04BC -#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 -#define REG_STBC_SETTING_8723B 0x04C4 -#define REG_HT_SINGLE_AMPDU_8723B 0x04C7 -#define REG_PROT_MODE_CTRL_8723B 0x04C8 -#define REG_MAX_AGGR_NUM_8723B 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB -#define REG_BAR_MODE_CTRL_8723B 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF -#define REG_MACID_PKT_DROP0_8723B 0x04D0 -#define REG_MACID_PKT_SLEEP_8723B 0x04D4 - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -#define REG_EDCA_VO_PARAM_8723B 0x0500 -#define REG_EDCA_VI_PARAM_8723B 0x0504 -#define REG_EDCA_BE_PARAM_8723B 0x0508 -#define REG_EDCA_BK_PARAM_8723B 0x050C -#define REG_BCNTCFG_8723B 0x0510 -#define REG_PIFS_8723B 0x0512 -#define REG_RDG_PIFS_8723B 0x0513 -#define REG_SIFS_CTX_8723B 0x0514 -#define REG_SIFS_TRX_8723B 0x0516 -#define REG_AGGR_BREAK_TIME_8723B 0x051A -#define REG_SLOT_8723B 0x051B -#define REG_TX_PTCL_CTRL_8723B 0x0520 -#define REG_TXPAUSE_8723B 0x0522 -#define REG_DIS_TXREQ_CLR_8723B 0x0523 -#define REG_RD_CTRL_8723B 0x0524 -// -// Format for offset 540h-542h: -// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. -// [7:4]: Reserved. -// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. -// [23:20]: Reserved -// Description: -// | -// |<--Setup--|--Hold------------>| -// --------------|---------------------- -// | -// TBTT -// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. -// Described by Designer Tim and Bruce, 2011-01-14. -// -#define REG_TBTT_PROHIBIT_8723B 0x0540 -#define REG_RD_NAV_NXT_8723B 0x0544 -#define REG_NAV_PROT_LEN_8723B 0x0546 -#define REG_BCN_CTRL_8723B 0x0550 -#define REG_BCN_CTRL_1_8723B 0x0551 -#define REG_MBID_NUM_8723B 0x0552 -#define REG_DUAL_TSF_RST_8723B 0x0553 -#define REG_BCN_INTERVAL_8723B 0x0554 -#define REG_DRVERLYINT_8723B 0x0558 -#define REG_BCNDMATIM_8723B 0x0559 -#define REG_ATIMWND_8723B 0x055A -#define REG_USTIME_TSF_8723B 0x055C -#define REG_BCN_MAX_ERR_8723B 0x055D -#define REG_RXTSF_OFFSET_CCK_8723B 0x055E -#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F -#define REG_TSFTR_8723B 0x0560 -#define REG_CTWND_8723B 0x0572 -#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 -#define REG_PSTIMER_8723B 0x0580 -#define REG_TIMER0_8723B 0x0584 -#define REG_TIMER1_8723B 0x0588 -#define REG_ACMHWCTRL_8723B 0x05C0 -#define REG_SCH_TXCMD_8723B 0x05F8 - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -#define REG_MAC_CR_8723B 0x0600 -#define REG_TCR_8723B 0x0604 -#define REG_RCR_8723B 0x0608 -#define REG_RX_PKT_LIMIT_8723B 0x060C -#define REG_RX_DLK_TIME_8723B 0x060D -#define REG_RX_DRVINFO_SZ_8723B 0x060F - -#define REG_MACID_8723B 0x0610 -#define REG_BSSID_8723B 0x0618 -#define REG_MAR_8723B 0x0620 -#define REG_MBIDCAMCFG_8723B 0x0628 - -#define REG_USTIME_EDCA_8723B 0x0638 -#define REG_MAC_SPEC_SIFS_8723B 0x063A -#define REG_RESP_SIFP_CCK_8723B 0x063C -#define REG_RESP_SIFS_OFDM_8723B 0x063E -#define REG_ACKTO_8723B 0x0640 -#define REG_CTS2TO_8723B 0x0641 -#define REG_EIFS_8723B 0x0642 - -#define REG_NAV_UPPER_8723B 0x0652 // unit of 128 -#define REG_TRXPTCL_CTL_8723B 0x0668 - -// Security -#define REG_CAMCMD_8723B 0x0670 -#define REG_CAMWRITE_8723B 0x0674 -#define REG_CAMREAD_8723B 0x0678 -#define REG_CAMDBG_8723B 0x067C -#define REG_SECCFG_8723B 0x0680 - -// Power -#define REG_WOW_CTRL_8723B 0x0690 -#define REG_PS_RX_INFO_8723B 0x0692 -#define REG_UAPSD_TID_8723B 0x0693 -#define REG_WKFMCAM_CMD_8723B 0x0698 -#define REG_WKFMCAM_NUM_8723B 0x0698 -#define REG_WKFMCAM_RWD_8723B 0x069C -#define REG_RXFLTMAP0_8723B 0x06A0 -#define REG_RXFLTMAP1_8723B 0x06A2 -#define REG_RXFLTMAP2_8723B 0x06A4 -#define REG_BCN_PSR_RPT_8723B 0x06A8 -#define REG_BT_COEX_TABLE_8723B 0x06C0 -#define REG_BFMER0_INFO_8723B 0x06E4 -#define REG_BFMER1_INFO_8723B 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC - -// Hardware Port 2 -#define REG_MACID1_8723B 0x0700 -#define REG_BSSID1_8723B 0x0708 -#define REG_BFMEE_SEL_8723B 0x0714 -#define REG_SND_PTCL_CTRL_8723B 0x0718 - - -//----------------------------------------------------- -// -// Redifine 8192C register definition for compatibility -// -//----------------------------------------------------- - -// TODO: use these definition when using REG_xxx naming rule. -// NOTE: DO NOT Remove these definition. Use later. -#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B // E-Fuse Control. -#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B // E-Fuse Test. -#define MSR_8723B (REG_CR_8723B + 2) // Media Status register -#define ISR_8723B REG_HISR0_8723B -#define TSFR_8723B REG_TSFTR_8723B // Timing Sync Function Timer Register. - -#define PBP_8723B REG_PBP_8723B - -// Redifine MACID register, to compatible prior ICs. -#define IDR0_8723B REG_MACID_8723B // MAC ID Register, Offset 0x0050-0x0053 -#define IDR4_8723B (REG_MACID_8723B + 4) // MAC ID Register, Offset 0x0054-0x0055 - - -// -// 9. Security Control Registers (Offset: ) -// -#define RWCAM_8723B REG_CAMCMD_8723B //IN 8190 Data Sheet is called CAMcmd -#define WCAMI_8723B REG_CAMWRITE_8723B // Software write CAM input content -#define RCAMO_8723B REG_CAMREAD_8723B // Software read/write CAM config -#define CAMDBG_8723B REG_CAMDBG_8723B -#define SECR_8723B REG_SECCFG_8723B //Security Configuration Register - - -//---------------------------------------------------------------------------- -// 8195 IMR/ISR bits (offset 0xB0, 8bits) -//---------------------------------------------------------------------------- -#define IMR_DISABLED_8723B 0 -// IMR DW0(0x00B0-00B3) Bit 0-31 -#define IMR_TIMER2_8723B BIT31 // Timeout interrupt 2 -#define IMR_TIMER1_8723B BIT30 // Timeout interrupt 1 -#define IMR_PSTIMEOUT_8723B BIT29 // Power Save Time Out Interrupt -#define IMR_GTINT4_8723B BIT28 // When GTIMER4 expires, this bit is set to 1 -#define IMR_GTINT3_8723B BIT27 // When GTIMER3 expires, this bit is set to 1 -#define IMR_TXBCN0ERR_8723B BIT26 // Transmit Beacon0 Error -#define IMR_TXBCN0OK_8723B BIT25 // Transmit Beacon0 OK -#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 // TSF Timer BIT32 toggle indication interrupt -#define IMR_BCNDMAINT0_8723B BIT20 // Beacon DMA Interrupt 0 -#define IMR_BCNDERR0_8723B BIT16 // Beacon Queue DMA OK0 -#define IMR_HSISR_IND_ON_INT_8723B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define IMR_BCNDMAINT_E_8723B BIT14 // Beacon DMA Interrupt Extension for Win7 -#define IMR_ATIMEND_8723B BIT12 // CTWidnow End or ATIM Window End -#define IMR_C2HCMD_8723B BIT10 // CPU to Host Command INT Status, Write 1 clear -#define IMR_CPWM2_8723B BIT9 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_HIGHDOK_8723B BIT7 // High Queue DMA OK -#define IMR_MGNTDOK_8723B BIT6 // Management Queue DMA OK -#define IMR_BKDOK_8723B BIT5 // AC_BK DMA OK -#define IMR_BEDOK_8723B BIT4 // AC_BE DMA OK -#define IMR_VIDOK_8723B BIT3 // AC_VI DMA OK -#define IMR_VODOK_8723B BIT2 // AC_VO DMA OK -#define IMR_RDU_8723B BIT1 // Rx Descriptor Unavailable -#define IMR_ROK_8723B BIT0 // Receive DMA OK - -// IMR DW1(0x00B4-00B7) Bit 0-31 -#define IMR_BCNDMAINT7_8723B BIT27 // Beacon DMA Interrupt 7 -#define IMR_BCNDMAINT6_8723B BIT26 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5_8723B BIT25 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4_8723B BIT24 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3_8723B BIT23 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2_8723B BIT22 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1_8723B BIT21 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK7_8723B BIT20 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6_8723B BIT19 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5_8723B BIT18 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4_8723B BIT17 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3_8723B BIT16 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2_8723B BIT15 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1_8723B BIT14 // Beacon Queue DMA OK Interrup 1 -#define IMR_ATIMEND_E_8723B BIT13 // ATIM Window End Extension for Win7 -#define IMR_TXERR_8723B BIT11 // Tx Error Flag Interrupt Status, write 1 clear. -#define IMR_RXERR_8723B BIT10 // Rx Error Flag INT Status, Write 1 clear -#define IMR_TXFOVW_8723B BIT9 // Transmit FIFO Overflow -#define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow - - - - - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ -//---------------------------------------------------------------------------- -// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- -/* -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopVO BIT3 -#define StopVI BIT2 -#define StopBE BIT1 -#define StopBK BIT0 -*/ - - -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -/* -//2 SYS_ISO_CTRL -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) -#define PWC_EV12V BIT(15) - - -//2 SYS_FUNC_EN -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) - -//2 APS_FSMCO -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) - -//2 SYS_CLKR -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) - - -//2 9346CR - -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - - -//2 RF_CTRL -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - -//2 LDOV12D_CTRL -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - - -//2 EFUSE_TEST (For RTL8723 partially) -#define EF_TRPT BIT(7) -#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 -#define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) -#define EFUSE_SEL_MASK 0x300 -#define EFUSE_WIFI_SEL_0 0x0 -#define EFUSE_BT_SEL_0 0x1 -#define EFUSE_BT_SEL_1 0x2 -#define EFUSE_BT_SEL_2 0x3 - - -//2 8051FWDL -//2 MCUFWDL -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define RAM_DL_SEL BIT(7) -#define ROM_DLEN BIT(19) -#define CPRST BIT(23) - - - -//2 REG_SYS_CFG -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define TRP_B15V_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define BT_FUNC BIT(16) -#define VENDOR_ID BIT(19) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) // RTL ID -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 -#define CHIP_VER_RTL_SHIFT 12 - -*/ -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -/* - -//2 Function Enable Registers -//2 CR 0x0100-0x0103 - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) -#define CALTMR_EN BIT(10) // 32k CAL TMR enable - -// Network type -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - - -//2 PBP - Page Size Register 0x0104 -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 - - -//2 TX/RXDMA 0x010C -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) - -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - - -//2 REG_C2HEVT_CLEAR 0x01AF -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - - - -//2 LLT_INIT 0x01E0 -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 - -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - -*/ -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -/* -//2 TDECTL 0x0208 -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - - -//2 TXDMA_OFFSET_CHK 0x020C -#define DROP_DATA_EN BIT(9) -*/ -//----------------------------------------------------- -// -// 0x0280h ~ 0x028Bh RX DMA Configuration -// -//----------------------------------------------------- -/* -//2 REG_RXDMA_CONTROL, 0x0286h - -// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before -// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. -#define RXPKT_RELEASE_POLL BIT(0) -// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in -// this bit. FW can start releasing packets after RXDMA entering idle mode. -#define RXDMA_IDLE BIT(1) -// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host -// completed, and stop DMA packet to host. RXDMA will then report Default: 0; -#define RW_RELEASE_EN BIT(2) -*/ -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -/* -//2 FWHW_TXQ_CTRL 0x0420 -#define EN_AMPDU_RTY_NEW BIT(7) - - -//2 REG_LIFECTRL_CTRL 0x0426 -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 - -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. - - -//2 SPEC SIFS 0x0428 -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) - -//2 RL 0x042A -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) -*/ - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -/* -//2 EDCA setting 0x050C -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - -//2 BCN_CTRL 0x0550 -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) - -//2 TxPause 0x0522 -#define STOP_BCNQ BIT(6) -*/ - - -//2 ACMHWCTRL 0x05C0 -#define AcmHw_HwEn_8723B BIT(0) -#define AcmHw_VoqEn_8723B BIT(1) -#define AcmHw_ViqEn_8723B BIT(2) -#define AcmHw_BeqEn_8723B BIT(3) -#define AcmHw_VoqStatus_8723B BIT(5) -#define AcmHw_ViqStatus_8723B BIT(6) -#define AcmHw_BeqStatus_8723B BIT(7) - - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -/* - -//2 TCR 0x0604 -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) -*/ - -//---------------------------------------------------------------------------- -// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) -//---------------------------------------------------------------------------- -/* -#define RCR_APPFCS BIT31 // WMAC append FCS after pauload -#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. -#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. -#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF -#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. -#define RCR_RSVD_BIT26 BIT26 // Reserved -*/ -#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload - -#endif // #ifndef __INC_HAL8723BREG_H +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8723BREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8723BREG_H +#define __INC_HAL8723BREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8723B 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8723B 0x0002 // 2 Byte +#define REG_APS_FSMCO_8723B 0x0004 // 4 Byte +#define REG_SYS_CLKR_8723B 0x0008 // 2 Byte +#define REG_9346CR_8723B 0x000A // 2 Byte +#define REG_EE_VPD_8723B 0x000C // 2 Byte +#define REG_AFE_MISC_8723B 0x0010 // 1 Byte +#define REG_SPS0_CTRL_8723B 0x0011 // 7 Byte +#define REG_SPS_OCP_CFG_8723B 0x0018 // 4 Byte +#define REG_RSV_CTRL_8723B 0x001C // 3 Byte +#define REG_RF_CTRL_8723B 0x001F // 1 Byte +#define REG_LPLDO_CTRL_8723B 0x0023 // 1 Byte +#define REG_AFE_XTAL_CTRL_8723B 0x0024 // 4 Byte +#define REG_AFE_PLL_CTRL_8723B 0x0028 // 4 Byte +#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8723B 0x0030 +#define REG_EFUSE_TEST_8723B 0x0034 +#define REG_PWR_DATA_8723B 0x0038 +#define REG_CAL_TIMER_8723B 0x003C +#define REG_ACLK_MON_8723B 0x003E +#define REG_GPIO_MUXCFG_8723B 0x0040 +#define REG_GPIO_IO_SEL_8723B 0x0042 +#define REG_MAC_PINMUX_CFG_8723B 0x0043 +#define REG_GPIO_PIN_CTRL_8723B 0x0044 +#define REG_GPIO_INTM_8723B 0x0048 +#define REG_LEDCFG0_8723B 0x004C +#define REG_LEDCFG1_8723B 0x004D +#define REG_LEDCFG2_8723B 0x004E +#define REG_LEDCFG3_8723B 0x004F +#define REG_FSIMR_8723B 0x0050 +#define REG_FSISR_8723B 0x0054 +#define REG_HSIMR_8723B 0x0058 +#define REG_HSISR_8723B 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_MULTI_FUNC_CTRL_8723B 0x0068 +#define REG_GPIO_STATUS_8723B 0x006C +#define REG_SDIO_CTRL_8723B 0x0070 +#define REG_OPT_CTRL_8723B 0x0074 +#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 +#define REG_MCUFWDL_8723B 0x0080 +#define REG_FW_DBG_STATUS_8723B 0x0088 +#define REG_FW_DBG_CTRL_8723B 0x008F +#define REG_SYSON_FSM_MON_8723B 0x00A0 +#define REG_HIMR0_8723B 0x00B0 +#define REG_HISR0_8723B 0x00B4 +#define REG_HIMR1_8723B 0x00B8 +#define REG_HISR1_8723B 0x00BC +#define REG_PMC_DBG_CTRL2_8723B 0x00CC +#define REG_EFUSE_BURN_GNT_8723B 0x00CF +#define REG_HPON_FSM_8723B 0x00EC +#define REG_SYS_CFG_8723B 0x00F0 +#define REG_SYS_CFG1_8723B 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8723B 0x0100 +#define REG_PBP_8723B 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 +#define REG_TRXDMA_CTRL_8723B 0x010C +#define REG_TRXFF_BNDY_8723B 0x0114 +#define REG_TRXFF_STATUS_8723B 0x0118 +#define REG_RXFF_PTR_8723B 0x011C +#define REG_CPWM_8723B 0x012F +#define REG_FWIMR_8723B 0x0130 +#define REG_FWISR_8723B 0x0134 +#define REG_FTIMR_8723B 0x0138 +#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 +#define REG_RXPKTBUF_CTRL_8723B 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 + +#define REG_TC0_CTRL_8723B 0x0150 +#define REG_TC1_CTRL_8723B 0x0154 +#define REG_TC2_CTRL_8723B 0x0158 +#define REG_TC3_CTRL_8723B 0x015C +#define REG_TC4_CTRL_8723B 0x0160 +#define REG_TCUNIT_BASE_8723B 0x0164 +#define REG_RSVD3_8723B 0x0168 +#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE +#define REG_C2HEVT_CLEAR_8723B 0x01AF +#define REG_MCUTST_1_8723B 0x01C0 +#define REG_MCUTST_2_8723B 0x01C4 +#define REG_MCUTST_WOWLAN_8723B 0x01C7 +#define REG_FMETHR_8723B 0x01C8 +#define REG_HMETFR_8723B 0x01CC +#define REG_HMEBOX_0_8723B 0x01D0 +#define REG_HMEBOX_1_8723B 0x01D4 +#define REG_HMEBOX_2_8723B 0x01D8 +#define REG_HMEBOX_3_8723B 0x01DC +#define REG_LLT_INIT_8723B 0x01E0 +#define REG_HMEBOX_EXT0_8723B 0x01F0 +#define REG_HMEBOX_EXT1_8723B 0x01F4 +#define REG_HMEBOX_EXT2_8723B 0x01F8 +#define REG_HMEBOX_EXT3_8723B 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8723B 0x0200 +#define REG_FIFOPAGE_8723B 0x0204 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define REG_DWBCN0_CTRL_8723B REG_TDECTRL +#else +#define REG_TDECTRL_8723B 0x0208 +#endif +#define REG_TXDMA_OFFSET_CHK_8723B 0x020C +#define REG_TXDMA_STATUS_8723B 0x0210 +#define REG_RQPN_NPQ_8723B 0x0214 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define REG_DWBCN1_CTRL_8723B 0x0228 +#else +#define REG_TDECTRL1_8723B 0x0228 +#endif + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8723B 0x0280 +#define REG_FW_UPD_RDPTR_8723B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL_8723B 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_8723B 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS_8723B 0x0288 +#define REG_RXDMA_PRO_8723B 0x0290 +#define REG_EARLY_MODE_CONTROL_8723B 0x02BC +#define REG_RSVD5_8723B 0x02F0 +#define REG_RSVD6_8723B 0x02F4 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8723B 0x0300 +#define REG_INT_MIG_8723B 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8723B 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8723B 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8723B 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8723B 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8723B 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8723B 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8723B 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8723B 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8723B 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8723B 0x034C // DBI Read Data +#define REG_DBI_ADDR_8723B 0x0350 // DBI Address +#define REG_DBI_FLAG_8723B 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8723B 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8723B 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8723B 0x0358 // MDIO for Control +#define REG_DBG_SEL_8723B 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8723B 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8723B 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A //PCIE Multi-Fethc Control + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION_8723B 0x0400 +#define REG_VIQ_INFORMATION_8723B 0x0404 +#define REG_BEQ_INFORMATION_8723B 0x0408 +#define REG_BKQ_INFORMATION_8723B 0x040C +#define REG_MGQ_INFORMATION_8723B 0x0410 +#define REG_HGQ_INFORMATION_8723B 0x0414 +#define REG_BCNQ_INFORMATION_8723B 0x0418 +#define REG_TXPKT_EMPTY_8723B 0x041A + +#define REG_FWHW_TXQ_CTRL_8723B 0x0420 +#define REG_HWSEQ_CTRL_8723B 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 +#define REG_LIFECTRL_CTRL_8723B 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 +#define REG_SPEC_SIFS_8723B 0x0428 +#define REG_RL_8723B 0x042A +#define REG_TXBF_CTRL_8723B 0x042C +#define REG_DARFRC_8723B 0x0430 +#define REG_RARFRC_8723B 0x0438 +#define REG_RRSR_8723B 0x0440 +#define REG_ARFR0_8723B 0x0444 +#define REG_ARFR1_8723B 0x044C +#define REG_CCK_CHECK_8723B 0x0454 +#define REG_AMPDU_MAX_TIME_8723B 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8723B 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D +#define REG_NDPA_OPT_CTRL_8723B 0x045F +#define REG_FAST_EDCA_CTRL_8723B 0x0460 +#define REG_RD_RESP_PKT_TH_8723B 0x0463 +#define REG_DATA_SC_8723B 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8723B 0x04B4 +#define REG_POWER_STAGE2_8723B 0x04B8 +#define REG_AMPDU_BURST_MODE_8723B 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 +#define REG_STBC_SETTING_8723B 0x04C4 +#define REG_HT_SINGLE_AMPDU_8723B 0x04C7 +#define REG_PROT_MODE_CTRL_8723B 0x04C8 +#define REG_MAX_AGGR_NUM_8723B 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB +#define REG_BAR_MODE_CTRL_8723B 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF +#define REG_MACID_PKT_DROP0_8723B 0x04D0 +#define REG_MACID_PKT_SLEEP_8723B 0x04D4 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM_8723B 0x0500 +#define REG_EDCA_VI_PARAM_8723B 0x0504 +#define REG_EDCA_BE_PARAM_8723B 0x0508 +#define REG_EDCA_BK_PARAM_8723B 0x050C +#define REG_BCNTCFG_8723B 0x0510 +#define REG_PIFS_8723B 0x0512 +#define REG_RDG_PIFS_8723B 0x0513 +#define REG_SIFS_CTX_8723B 0x0514 +#define REG_SIFS_TRX_8723B 0x0516 +#define REG_AGGR_BREAK_TIME_8723B 0x051A +#define REG_SLOT_8723B 0x051B +#define REG_TX_PTCL_CTRL_8723B 0x0520 +#define REG_TXPAUSE_8723B 0x0522 +#define REG_DIS_TXREQ_CLR_8723B 0x0523 +#define REG_RD_CTRL_8723B 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8723B 0x0540 +#define REG_RD_NAV_NXT_8723B 0x0544 +#define REG_NAV_PROT_LEN_8723B 0x0546 +#define REG_BCN_CTRL_8723B 0x0550 +#define REG_BCN_CTRL_1_8723B 0x0551 +#define REG_MBID_NUM_8723B 0x0552 +#define REG_DUAL_TSF_RST_8723B 0x0553 +#define REG_BCN_INTERVAL_8723B 0x0554 +#define REG_DRVERLYINT_8723B 0x0558 +#define REG_BCNDMATIM_8723B 0x0559 +#define REG_ATIMWND_8723B 0x055A +#define REG_USTIME_TSF_8723B 0x055C +#define REG_BCN_MAX_ERR_8723B 0x055D +#define REG_RXTSF_OFFSET_CCK_8723B 0x055E +#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F +#define REG_TSFTR_8723B 0x0560 +#define REG_CTWND_8723B 0x0572 +#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 +#define REG_PSTIMER_8723B 0x0580 +#define REG_TIMER0_8723B 0x0584 +#define REG_TIMER1_8723B 0x0588 +#define REG_ACMHWCTRL_8723B 0x05C0 +#define REG_SCH_TXCMD_8723B 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_MAC_CR_8723B 0x0600 +#define REG_TCR_8723B 0x0604 +#define REG_RCR_8723B 0x0608 +#define REG_RX_PKT_LIMIT_8723B 0x060C +#define REG_RX_DLK_TIME_8723B 0x060D +#define REG_RX_DRVINFO_SZ_8723B 0x060F + +#define REG_MACID_8723B 0x0610 +#define REG_BSSID_8723B 0x0618 +#define REG_MAR_8723B 0x0620 +#define REG_MBIDCAMCFG_8723B 0x0628 + +#define REG_USTIME_EDCA_8723B 0x0638 +#define REG_MAC_SPEC_SIFS_8723B 0x063A +#define REG_RESP_SIFP_CCK_8723B 0x063C +#define REG_RESP_SIFS_OFDM_8723B 0x063E +#define REG_ACKTO_8723B 0x0640 +#define REG_CTS2TO_8723B 0x0641 +#define REG_EIFS_8723B 0x0642 + +#define REG_NAV_UPPER_8723B 0x0652 // unit of 128 +#define REG_TRXPTCL_CTL_8723B 0x0668 + +// Security +#define REG_CAMCMD_8723B 0x0670 +#define REG_CAMWRITE_8723B 0x0674 +#define REG_CAMREAD_8723B 0x0678 +#define REG_CAMDBG_8723B 0x067C +#define REG_SECCFG_8723B 0x0680 + +// Power +#define REG_WOW_CTRL_8723B 0x0690 +#define REG_PS_RX_INFO_8723B 0x0692 +#define REG_UAPSD_TID_8723B 0x0693 +#define REG_WKFMCAM_CMD_8723B 0x0698 +#define REG_WKFMCAM_NUM_8723B 0x0698 +#define REG_WKFMCAM_RWD_8723B 0x069C +#define REG_RXFLTMAP0_8723B 0x06A0 +#define REG_RXFLTMAP1_8723B 0x06A2 +#define REG_RXFLTMAP2_8723B 0x06A4 +#define REG_BCN_PSR_RPT_8723B 0x06A8 +#define REG_BT_COEX_TABLE_8723B 0x06C0 +#define REG_BFMER0_INFO_8723B 0x06E4 +#define REG_BFMER1_INFO_8723B 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8723B 0x0700 +#define REG_BSSID1_8723B 0x0708 +#define REG_BFMEE_SEL_8723B 0x0714 +#define REG_SND_PTCL_CTRL_8723B 0x0718 + + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B // E-Fuse Control. +#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B // E-Fuse Test. +#define MSR_8723B (REG_CR_8723B + 2) // Media Status register +#define ISR_8723B REG_HISR0_8723B +#define TSFR_8723B REG_TSFTR_8723B // Timing Sync Function Timer Register. + +#define PBP_8723B REG_PBP_8723B + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8723B REG_MACID_8723B // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8723B (REG_MACID_8723B + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8723B REG_CAMCMD_8723B //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8723B REG_CAMWRITE_8723B // Software write CAM input content +#define RCAMO_8723B REG_CAMREAD_8723B // Software read/write CAM config +#define CAMDBG_8723B REG_CAMDBG_8723B +#define SECR_8723B REG_SECCFG_8723B //Security Configuration Register + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8723B 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8723B BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8723B BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8723B BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8723B BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8723B BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8723B BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8723B BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8723B BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8723B BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8723B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8723B BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8723B BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8723B BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8723B BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8723B BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8723B BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8723B BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8723B BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8723B BIT3 // AC_VI DMA OK +#define IMR_VODOK_8723B BIT2 // AC_VO DMA OK +#define IMR_RDU_8723B BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8723B BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8723B BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8723B BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8723B BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8723B BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8723B BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8723B BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8723B BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8723B BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8723B BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8723B BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8723B BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8723B BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8723B BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8723B BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8723B BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8723B BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8723B BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8723B BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow + + + + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8723B BIT(0) +#define AcmHw_VoqEn_8723B BIT(1) +#define AcmHw_ViqEn_8723B BIT(2) +#define AcmHw_BeqEn_8723B BIT(3) +#define AcmHw_VoqStatus_8723B BIT(5) +#define AcmHw_ViqStatus_8723B BIT(6) +#define AcmHw_BeqStatus_8723B BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload + +#endif // #ifndef __INC_HAL8723BREG_H diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.c index a21b44dbde0..9e50492d07d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.c @@ -1,633 +1,633 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8723B_AGC_TAB[] = { - 0xC78, 0xFD000001, - 0xC78, 0xFC010001, - 0xC78, 0xFB020001, - 0xC78, 0xFA030001, - 0xC78, 0xF9040001, - 0xC78, 0xF8050001, - 0xC78, 0xF7060001, - 0xC78, 0xF6070001, - 0xC78, 0xF5080001, - 0xC78, 0xF4090001, - 0xC78, 0xF30A0001, - 0xC78, 0xF20B0001, - 0xC78, 0xF10C0001, - 0xC78, 0xF00D0001, - 0xC78, 0xEF0E0001, - 0xC78, 0xEE0F0001, - 0xC78, 0xED100001, - 0xC78, 0xEC110001, - 0xC78, 0xEB120001, - 0xC78, 0xEA130001, - 0xC78, 0xE9140001, - 0xC78, 0xE8150001, - 0xC78, 0xE7160001, - 0xC78, 0xE6170001, - 0xC78, 0xE5180001, - 0xC78, 0xE4190001, - 0xC78, 0xE31A0001, - 0xC78, 0xA51B0001, - 0xC78, 0xA41C0001, - 0xC78, 0xA31D0001, - 0xC78, 0x671E0001, - 0xC78, 0x661F0001, - 0xC78, 0x65200001, - 0xC78, 0x64210001, - 0xC78, 0x63220001, - 0xC78, 0x4A230001, - 0xC78, 0x49240001, - 0xC78, 0x48250001, - 0xC78, 0x47260001, - 0xC78, 0x46270001, - 0xC78, 0x45280001, - 0xC78, 0x44290001, - 0xC78, 0x432A0001, - 0xC78, 0x422B0001, - 0xC78, 0x292C0001, - 0xC78, 0x282D0001, - 0xC78, 0x272E0001, - 0xC78, 0x262F0001, - 0xC78, 0x0A300001, - 0xC78, 0x09310001, - 0xC78, 0x08320001, - 0xC78, 0x07330001, - 0xC78, 0x06340001, - 0xC78, 0x05350001, - 0xC78, 0x04360001, - 0xC78, 0x03370001, - 0xC78, 0x02380001, - 0xC78, 0x01390001, - 0xC78, 0x013A0001, - 0xC78, 0x013B0001, - 0xC78, 0x013C0001, - 0xC78, 0x013D0001, - 0xC78, 0x013E0001, - 0xC78, 0x013F0001, - 0xC78, 0xFC400001, - 0xC78, 0xFB410001, - 0xC78, 0xFA420001, - 0xC78, 0xF9430001, - 0xC78, 0xF8440001, - 0xC78, 0xF7450001, - 0xC78, 0xF6460001, - 0xC78, 0xF5470001, - 0xC78, 0xF4480001, - 0xC78, 0xF3490001, - 0xC78, 0xF24A0001, - 0xC78, 0xF14B0001, - 0xC78, 0xF04C0001, - 0xC78, 0xEF4D0001, - 0xC78, 0xEE4E0001, - 0xC78, 0xED4F0001, - 0xC78, 0xEC500001, - 0xC78, 0xEB510001, - 0xC78, 0xEA520001, - 0xC78, 0xE9530001, - 0xC78, 0xE8540001, - 0xC78, 0xE7550001, - 0xC78, 0xE6560001, - 0xC78, 0xE5570001, - 0xC78, 0xE4580001, - 0xC78, 0xE3590001, - 0xC78, 0xA65A0001, - 0xC78, 0xA55B0001, - 0xC78, 0xA45C0001, - 0xC78, 0xA35D0001, - 0xC78, 0x675E0001, - 0xC78, 0x665F0001, - 0xC78, 0x65600001, - 0xC78, 0x64610001, - 0xC78, 0x63620001, - 0xC78, 0x62630001, - 0xC78, 0x61640001, - 0xC78, 0x48650001, - 0xC78, 0x47660001, - 0xC78, 0x46670001, - 0xC78, 0x45680001, - 0xC78, 0x44690001, - 0xC78, 0x436A0001, - 0xC78, 0x426B0001, - 0xC78, 0x286C0001, - 0xC78, 0x276D0001, - 0xC78, 0x266E0001, - 0xC78, 0x256F0001, - 0xC78, 0x24700001, - 0xC78, 0x09710001, - 0xC78, 0x08720001, - 0xC78, 0x07730001, - 0xC78, 0x06740001, - 0xC78, 0x05750001, - 0xC78, 0x04760001, - 0xC78, 0x03770001, - 0xC78, 0x02780001, - 0xC78, 0x01790001, - 0xC78, 0x017A0001, - 0xC78, 0x017B0001, - 0xC78, 0x017C0001, - 0xC78, 0x017D0001, - 0xC78, 0x017E0001, - 0xC78, 0x017F0001, - 0xC50, 0x69553422, - 0xC50, 0x69553420, - 0x824, 0x00390204, - -}; - -void -ODM_ReadAndConfig_MP_8723B_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723B_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723B_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8723B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723B_AGC_TAB(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723B_PHY_REG[] = { - 0x800, 0x80040000, - 0x804, 0x00000003, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x02200385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x824, 0x00190204, - 0x828, 0x00000000, - 0x82C, 0x00000000, - 0x830, 0x00000000, - 0x834, 0x00000000, - 0x838, 0x00000000, - 0x83C, 0x00000000, - 0x840, 0x00010000, - 0x844, 0x00000000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00000000, - 0x854, 0x00000000, - 0x858, 0x569A11A9, - 0x85C, 0x01000014, - 0x860, 0x66F60110, - 0x864, 0x061F0649, - 0x868, 0x00000000, - 0x86C, 0x27272700, - 0x870, 0x07000760, - 0x874, 0x25004000, - 0x878, 0x00000808, - 0x87C, 0x00000000, - 0x880, 0xB0000C1C, - 0x884, 0x00000001, - 0x888, 0x00000000, - 0x88C, 0xCCC000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121111, - 0x910, 0x00000002, - 0x914, 0x00000201, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0xA08, 0x8C838300, - 0xA0C, 0x2E7F120F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0xA2C, 0x00D30000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000007, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0xA80, 0x21806490, - 0xB2C, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05611, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x08800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9AC44, - 0xC34, 0x469652AF, - 0xC38, 0x49795994, - 0xC3C, 0x0A97971C, - 0xC40, 0x1F7C403F, - 0xC44, 0x000100B7, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0xC50, 0x69553420, - 0xC54, 0x43BC0094, - 0xC58, 0x00013147, - 0xC5C, 0x00250492, - 0xC60, 0x00000000, - 0xC64, 0x5112848B, - 0xC68, 0x47C00BFF, - 0xC6C, 0x00000036, - 0xC70, 0x2C7F000D, - 0xC74, 0x020610DB, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0xC80, 0x390000E4, - 0xC84, 0x21F60000, - 0xC88, 0x40000100, - 0xC8C, 0x20200000, - 0xC90, 0x00020E1A, - 0xC94, 0x00000000, - 0xC98, 0x00020E1A, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00000000, - 0xCA4, 0x000300A0, - 0xCA8, 0x00000000, - 0xCAC, 0x00000000, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x64B22427, - 0xCDC, 0x00766932, - 0xCE0, 0x00222222, - 0xCE4, 0x00000000, - 0xCE8, 0x37644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x00000740, - 0xD04, 0x40020401, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC53, - 0xD18, 0x7A8F5B6F, - 0xD2C, 0xCC979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x00000000, - 0xD3C, 0x00127353, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x6437140A, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xD6C, 0x2A201C16, - 0xD70, 0x1812362E, - 0xD74, 0x322C2220, - 0xD78, 0x000E3C24, - 0xE00, 0x2D2D2D2D, - 0xE04, 0x2D2D2D2D, - 0xE08, 0x0390272D, - 0xE10, 0x2D2D2D2D, - 0xE14, 0x2D2D2D2D, - 0xE18, 0x2D2D2D2D, - 0xE1C, 0x2D2D2D2D, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000048, - 0xE68, 0x001B2556, - 0xE6C, 0x00C00096, - 0xE70, 0x00C00096, - 0xE74, 0x01000056, - 0xE78, 0x01000014, - 0xE7C, 0x01000056, - 0xE80, 0x01000014, - 0xE84, 0x00C00096, - 0xE88, 0x01000056, - 0xE8C, 0x00C00096, - 0xED0, 0x00C00096, - 0xED4, 0x00C00096, - 0xED8, 0x00C00096, - 0xEDC, 0x000000D6, - 0xEE0, 0x000000D6, - 0xEEC, 0x01C00016, - 0xF14, 0x00000003, - 0xF4C, 0x00000000, - 0xF00, 0x00000300, - 0x820, 0x01000100, - 0x800, 0x83040000, - -}; - -void -ODM_ReadAndConfig_MP_8723B_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723B_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723B_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8723B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723B_PHY_REG(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723B_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x40424444, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 -}; - -void -ODM_ReadAndConfig_MP_8723B_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8723B_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723B_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8723B_AGC_TAB[] = { + 0xC78, 0xFD000001, + 0xC78, 0xFC010001, + 0xC78, 0xFB020001, + 0xC78, 0xFA030001, + 0xC78, 0xF9040001, + 0xC78, 0xF8050001, + 0xC78, 0xF7060001, + 0xC78, 0xF6070001, + 0xC78, 0xF5080001, + 0xC78, 0xF4090001, + 0xC78, 0xF30A0001, + 0xC78, 0xF20B0001, + 0xC78, 0xF10C0001, + 0xC78, 0xF00D0001, + 0xC78, 0xEF0E0001, + 0xC78, 0xEE0F0001, + 0xC78, 0xED100001, + 0xC78, 0xEC110001, + 0xC78, 0xEB120001, + 0xC78, 0xEA130001, + 0xC78, 0xE9140001, + 0xC78, 0xE8150001, + 0xC78, 0xE7160001, + 0xC78, 0xE6170001, + 0xC78, 0xE5180001, + 0xC78, 0xE4190001, + 0xC78, 0xE31A0001, + 0xC78, 0xA51B0001, + 0xC78, 0xA41C0001, + 0xC78, 0xA31D0001, + 0xC78, 0x671E0001, + 0xC78, 0x661F0001, + 0xC78, 0x65200001, + 0xC78, 0x64210001, + 0xC78, 0x63220001, + 0xC78, 0x4A230001, + 0xC78, 0x49240001, + 0xC78, 0x48250001, + 0xC78, 0x47260001, + 0xC78, 0x46270001, + 0xC78, 0x45280001, + 0xC78, 0x44290001, + 0xC78, 0x432A0001, + 0xC78, 0x422B0001, + 0xC78, 0x292C0001, + 0xC78, 0x282D0001, + 0xC78, 0x272E0001, + 0xC78, 0x262F0001, + 0xC78, 0x0A300001, + 0xC78, 0x09310001, + 0xC78, 0x08320001, + 0xC78, 0x07330001, + 0xC78, 0x06340001, + 0xC78, 0x05350001, + 0xC78, 0x04360001, + 0xC78, 0x03370001, + 0xC78, 0x02380001, + 0xC78, 0x01390001, + 0xC78, 0x013A0001, + 0xC78, 0x013B0001, + 0xC78, 0x013C0001, + 0xC78, 0x013D0001, + 0xC78, 0x013E0001, + 0xC78, 0x013F0001, + 0xC78, 0xFC400001, + 0xC78, 0xFB410001, + 0xC78, 0xFA420001, + 0xC78, 0xF9430001, + 0xC78, 0xF8440001, + 0xC78, 0xF7450001, + 0xC78, 0xF6460001, + 0xC78, 0xF5470001, + 0xC78, 0xF4480001, + 0xC78, 0xF3490001, + 0xC78, 0xF24A0001, + 0xC78, 0xF14B0001, + 0xC78, 0xF04C0001, + 0xC78, 0xEF4D0001, + 0xC78, 0xEE4E0001, + 0xC78, 0xED4F0001, + 0xC78, 0xEC500001, + 0xC78, 0xEB510001, + 0xC78, 0xEA520001, + 0xC78, 0xE9530001, + 0xC78, 0xE8540001, + 0xC78, 0xE7550001, + 0xC78, 0xE6560001, + 0xC78, 0xE5570001, + 0xC78, 0xE4580001, + 0xC78, 0xE3590001, + 0xC78, 0xA65A0001, + 0xC78, 0xA55B0001, + 0xC78, 0xA45C0001, + 0xC78, 0xA35D0001, + 0xC78, 0x675E0001, + 0xC78, 0x665F0001, + 0xC78, 0x65600001, + 0xC78, 0x64610001, + 0xC78, 0x63620001, + 0xC78, 0x62630001, + 0xC78, 0x61640001, + 0xC78, 0x48650001, + 0xC78, 0x47660001, + 0xC78, 0x46670001, + 0xC78, 0x45680001, + 0xC78, 0x44690001, + 0xC78, 0x436A0001, + 0xC78, 0x426B0001, + 0xC78, 0x286C0001, + 0xC78, 0x276D0001, + 0xC78, 0x266E0001, + 0xC78, 0x256F0001, + 0xC78, 0x24700001, + 0xC78, 0x09710001, + 0xC78, 0x08720001, + 0xC78, 0x07730001, + 0xC78, 0x06740001, + 0xC78, 0x05750001, + 0xC78, 0x04760001, + 0xC78, 0x03770001, + 0xC78, 0x02780001, + 0xC78, 0x01790001, + 0xC78, 0x017A0001, + 0xC78, 0x017B0001, + 0xC78, 0x017C0001, + 0xC78, 0x017D0001, + 0xC78, 0x017E0001, + 0xC78, 0x017F0001, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + 0x824, 0x00390204, + +}; + +void +ODM_ReadAndConfig_MP_8723B_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723B_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723B_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8723B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723B_AGC_TAB(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723B_PHY_REG[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00190204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x07000760, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x21806490, + 0xB2C, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC44, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00013147, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x5112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020610DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0xC84, 0x21F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00020E1A, + 0xC94, 0x00000000, + 0xC98, 0x00020E1A, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00000740, + 0xD04, 0x40020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC53, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000048, + 0xE68, 0x001B2556, + 0xE6C, 0x00C00096, + 0xE70, 0x00C00096, + 0xE74, 0x01000056, + 0xE78, 0x01000014, + 0xE7C, 0x01000056, + 0xE80, 0x01000014, + 0xE84, 0x00C00096, + 0xE88, 0x01000056, + 0xE8C, 0x00C00096, + 0xED0, 0x00C00096, + 0xED4, 0x00C00096, + 0xED8, 0x00C00096, + 0xEDC, 0x000000D6, + 0xEE0, 0x000000D6, + 0xEEC, 0x01C00016, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + 0x820, 0x01000100, + 0x800, 0x83040000, + +}; + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723B_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723B_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8723B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723B_PHY_REG(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723B_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x40424444, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 +}; + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8723B_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723B_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.h index 2adb8acb4fc..c2bf12998d3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8723B_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8723B_H -#define __INC_MP_BB_HW_IMG_8723B_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8723B_H +#define __INC_MP_BB_HW_IMG_8723B_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.c index c47bc64ba9c..6169c771a32 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.c @@ -1,5269 +1,5269 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8723b/hal8723b_fw.h" -#endif - - -#if (RTL8723B_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8723B_FW_AP[] = { -0x01, 0x53, 0x20, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x9A, 0x58, 0x00, 0x00, -0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x45, 0xDB, 0x02, 0x79, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x97, 0xE0, 0x22, -0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22, 0x90, 0xA1, 0x64, 0xE0, 0xC4, 0x54, 0x0F, 0x22, -0x90, 0xA1, 0x6C, 0xE0, 0x90, 0x05, 0x73, 0x22, 0x90, 0xA1, 0x6A, 0xE0, 0x44, 0x10, 0xF0, 0x22, -0x74, 0x01, 0x7E, 0x00, 0xA8, 0x53, 0x08, 0x22, 0x90, 0xA2, 0x03, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, -0x4F, 0xFF, 0xF0, 0x12, 0x06, 0x89, 0xFE, 0x22, 0xC1, 0x51, -}; -u4Byte ArrayLength_MP_8723B_FW_AP = 22714; - -#endif - -void -ODM_ReadFirmware_MP_8723B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_AP; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_AP, ArrayLength_MP_8723B_FW_AP); -#endif - *pFirmwareSize = ArrayLength_MP_8723B_FW_AP; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8723B_FW_NIC[] = { -0x01, 0x53, 0x10, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x0A, 0x7E, 0x00, 0x00, -0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x46, 0x2A, 0x02, 0x7F, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x81, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x80, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x8F, 0xEC, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x97, 0xDD, 0x1F, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, -0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, 0x00, 0x00, -0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x10, 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-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_NIC, ArrayLength_MP_8723B_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8723B_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8723B_FW_WoWLAN[] = { -0x01, 0x53, 0x30, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x32, 0x6B, 0x00, 0x00, -0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x48, 0xA2, 0x02, 0x77, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x78, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x78, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x78, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7F, 0xEA, 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- OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_WoWLAN, ArrayLength_MP_8723B_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8723B_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8723b/hal8723b_fw.h" +#endif + + +#if (RTL8723B_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723B_FW_AP[] = { +0x01, 0x53, 0x20, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x9A, 0x58, 0x00, 0x00, +0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x45, 0xDB, 0x02, 0x79, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x97, 0xE0, 0x22, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22, 0x90, 0xA1, 0x64, 0xE0, 0xC4, 0x54, 0x0F, 0x22, +0x90, 0xA1, 0x6C, 0xE0, 0x90, 0x05, 0x73, 0x22, 0x90, 0xA1, 0x6A, 0xE0, 0x44, 0x10, 0xF0, 0x22, +0x74, 0x01, 0x7E, 0x00, 0xA8, 0x53, 0x08, 0x22, 0x90, 0xA2, 0x03, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, +0x4F, 0xFF, 0xF0, 0x12, 0x06, 0x89, 0xFE, 0x22, 0xC1, 0x51, +}; +u4Byte ArrayLength_MP_8723B_FW_AP = 22714; + +#endif + +void +ODM_ReadFirmware_MP_8723B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_AP, ArrayLength_MP_8723B_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8723B_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723B_FW_NIC[] = { +0x01, 0x53, 0x10, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x0A, 0x7E, 0x00, 0x00, +0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x46, 0x2A, 0x02, 0x7F, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x81, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x80, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x8F, 0xEC, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x97, 0xDD, 0x1F, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, +0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, 0x00, 0x00, +0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x10, 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+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_NIC, ArrayLength_MP_8723B_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8723B_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723B_FW_WoWLAN[] = { +0x01, 0x53, 0x30, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x28, 0x16, 0x13, 0x32, 0x6B, 0x00, 0x00, +0xB3, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0xA2, 0x02, 0x77, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x78, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x78, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x78, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7F, 0xEA, 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0x75, 0x43, 0x02, 0x22, 0xE4, 0x75, 0xF0, 0x20, 0x02, +0x08, 0xD6, 0x90, 0x94, 0xC7, 0xE0, 0x90, 0x95, 0x88, 0x22, 0x7F, 0x01, 0x7E, 0x00, 0x02, 0x3D, +0xC2, 0xF0, 0x90, 0x06, 0x08, 0xE0, 0x54, 0x7F, 0x22, 0x90, 0x94, 0x41, 0xE0, 0xC3, 0x94, 0x0A, +0x22, 0x74, 0x10, 0xF0, 0x7A, 0x8F, 0x79, 0x50, 0x22, 0x12, 0x44, 0x20, 0x7A, 0x93, 0x79, 0xA1, +0x22, 0x90, 0x93, 0x96, 0xEE, 0xF0, 0xA3, 0xEF, 0x22, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, +0x22, 0x90, 0x8E, 0x14, 0xE0, 0x54, 0xFE, 0xF0, 0x22, 0x90, 0x8E, 0x15, 0xE0, 0xC4, 0x54, 0x0F, +0x22, 0x90, 0x8E, 0x1D, 0xE0, 0x90, 0x05, 0x73, 0x22, 0x90, 0x8E, 0x1B, 0xE0, 0x44, 0x10, 0xF0, +0x22, 0x90, 0x94, 0xD9, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x94, 0xD9, 0xE0, 0xFC, 0xA3, 0xE0, +0x22, 0x90, 0x94, 0xDB, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, 0x7E, 0x00, 0x7F, 0x10, 0x02, 0x06, 0x63, +0x2C, 0xA6, +}; +u4Byte ArrayLength_MP_8723B_FW_WoWLAN = 27474; + +#endif + +void +ODM_ReadFirmware_MP_8723B_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_WoWLAN, ArrayLength_MP_8723B_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8723B_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.h index e087a7c6ef7..0fd2d1d2f2b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8723B_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8723B_H -#define __INC_MP_FW_HW_IMG_8723B_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723B_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8723B_H +#define __INC_MP_FW_HW_IMG_8723B_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723B_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.c index 287b063f4ea..3d7098b2ed4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.c @@ -1,290 +1,290 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723B_MAC_REG[] = { - 0x02F, 0x00000030, - 0x035, 0x00000000, - 0x039, 0x00000008, - 0x064, 0x00000000, - 0x067, 0x00000020, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x765, 0x00000018, - 0x76E, 0x00000004, - -}; - -void -ODM_ReadAndConfig_MP_8723B_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723B_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723B_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8723B(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723B_MAC_REG(void) -{ - return 28; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723B_MAC_REG[] = { + 0x02F, 0x00000030, + 0x035, 0x00000000, + 0x039, 0x00000008, + 0x064, 0x00000000, + 0x067, 0x00000020, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x765, 0x00000018, + 0x76E, 0x00000004, + +}; + +void +ODM_ReadAndConfig_MP_8723B_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723B_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723B_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8723B(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723B_MAC_REG(void) +{ + return 28; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.h index 6501616836e..5768a7e74cf 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8723B_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8723B_H -#define __INC_MP_MAC_HW_IMG_8723B_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8723B_H +#define __INC_MP_MAC_HW_IMG_8723B_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.c index e1a9bd52d82..c689dd9c1db 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.c @@ -1,2694 +1,2694 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT==1) - -#ifdef CONFIG_MP_INCLUDED - -//#define SIZE_OF_BT_MP_PATCH 20564 -u8 Rtl8723BFwBTImgArray[Rtl8723BFwBTImgArrayLength] = { -0xfc, 0x63, 0x07, 0x62, 0x06, 0xd1, 0x05, 0xd0, 0x00, 0x69, 0x4f, 0xb2, 0x20, 0xda, 0x4f, 0xb2, 0x40, 0x9a, 0x4f, 0xb3, 0x4f, 0xb0, 0x42, 0x34, 0x82, 0x34, 0x80, 0xcb, 0x4e, 0xb3, 0x40, 0xcb, -0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x01, 0x6b, 0x4e, 0xb2, 0x60, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xca, 0x4e, 0xb3, 0x4e, 0xb2, 0x60, 0xda, -0x4e, 0xb3, 0x4f, 0xb2, 0x60, 0xda, 0x4f, 0xb3, 0x4f, 0xb2, 0x60, 0xda, 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(SIZE_PTR)Array_MP_8723B_FW_MP; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_MP, ArrayLength_MP_8723B_FW_MP); -#endif - *pFirmwareSize = ArrayLength_MP_8723B_FW_MP; -} - - -const u32 Rtl8723B_PHYREG_Array_MP[Rtl8723B_PHYREG_Array_MPLength] = { -0xc30,0x69e9ac4a, -0xc3c,0x0a979718, -}; - -#endif //CONFIG_MP_INCLUDED - -#endif +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT==1) + +#ifdef CONFIG_MP_INCLUDED + +//#define SIZE_OF_BT_MP_PATCH 20564 +u8 Rtl8723BFwBTImgArray[Rtl8723BFwBTImgArrayLength] = { +0xfc, 0x63, 0x07, 0x62, 0x06, 0xd1, 0x05, 0xd0, 0x00, 0x69, 0x4f, 0xb2, 0x20, 0xda, 0x4f, 0xb2, 0x40, 0x9a, 0x4f, 0xb3, 0x4f, 0xb0, 0x42, 0x34, 0x82, 0x34, 0x80, 0xcb, 0x4e, 0xb3, 0x40, 0xcb, +0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x01, 0x6b, 0x4e, 0xb2, 0x60, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xc2, 0x4e, 0xb2, 0x20, 0xca, 0x4e, 0xb3, 0x4e, 0xb2, 0x60, 0xda, +0x4e, 0xb3, 0x4f, 0xb2, 0x60, 0xda, 0x4f, 0xb3, 0x4f, 0xb2, 0x60, 0xda, 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0x90, 0xA1, 0xBB, 0xE0, 0xC3, +0x13, 0x54, 0x7F, 0x90, 0xA3, 0xAF, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x12, 0x48, +0x29, 0x90, 0xA1, 0x16, 0xE0, 0x44, 0x08, 0xF0, 0x22, 0x90, 0xA1, 0xCD, 0xE0, 0x30, 0xE0, 0x17, +0x90, 0xA1, 0xDF, 0xE0, 0x70, 0x60, 0x90, 0xA1, 0x1C, 0xE0, 0xD3, 0x94, 0x00, 0x50, 0x57, 0x90, +0xA1, 0xBF, 0xE0, 0x60, 0x4E, 0x80, 0x4F, 0x12, 0x73, 0xF1, 0xEF, 0x64, 0x01, 0x70, 0x47, 0x90, +0xA1, 0x1E, 0xE0, 0xFF, 0x54, 0x03, 0x70, 0x3E, 0x90, 0xA1, 0x1C, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, +0x40, 0x34, 0xEF, 0x20, 0xE2, 0x30, 0x90, 0xA1, 0x1E, 0xE0, 0x20, 0xE4, 0x29, 0x90, 0xA1, 0x17, +0xE0, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x1E, 0x90, 0xA1, 0xBF, 0xE0, 0x70, 0x18, 0x90, 0x06, +0x62, 0xE0, 0x20, 0xE1, 0x11, 0x90, 0x06, 0x62, 0xE0, 0x30, 0xE0, 0x07, 0xE0, 0x54, 0xFC, 0x64, +0x80, 0x60, 0x03, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0xEF, 0x60, 0x3B, 0x90, 0xA0, 0x90, 0xE0, +0x64, 0x01, 0x70, 0x33, 0x90, 0xA1, 0x17, 0xE0, 0x54, 0xFE, 0xF0, 0x7D, 0x2B, 0x7F, 0x0F, 0x12, +0x49, 0x5E, 0x90, 0x06, 0x04, 0xE0, 0x54, 0xBF, 0xF0, 0x7D, 0x08, 0xE4, 0xFF, 0x12, 0x49, 0x74, +0xBF, 0x01, 0x14, 0x90, 0xA1, 0x16, 0xE0, 0x44, 0x40, 0xF0, 0x7D, 0x06, 0x7F, 0x01, 0x12, 0x55, +0x87, 0x90, 0xA1, 0x15, 0x74, 0x06, 0xF0, 0x22, 0x90, 0xA0, 0x90, 0xE0, 0x64, 0x01, 0x70, 0x28, +0x90, 0xA1, 0x17, 0xE0, 0x54, 0xFD, 0xF0, 0x7D, 0x2C, 0x7F, 0x6F, 0x12, 0x49, 0x5E, 0x12, 0x49, +0x69, 0xBF, 0x01, 0x14, 0x90, 0xA1, 0x16, 0xE0, 0x44, 0x80, 0xF0, 0x7D, 0x0E, 0x7F, 0x01, 0x12, +0x55, 0x87, 0x90, 0xA1, 0x15, 0x74, 0x0E, 0xF0, 0x22, 0x7D, 0x2D, 0x12, 0x4C, 0x04, 0x90, 0x01, +0x37, 0x74, 0x02, 0xF0, 0xFD, 0x7F, 0x03, 0x12, 0x5A, 0x91, 0x12, 0x46, 0xFD, 0xE4, 0xFD, 0x7F, +0x01, 0x12, 0x55, 0x87, 0xE4, 0x90, 0xA1, 0x15, 0xF0, 0x22, 0x7D, 0x2E, 0x7F, 0x6F, 0x12, 0x49, +0x5E, 0x7D, 0x02, 0x7F, 0x01, 0x12, 0x55, 0x87, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, +0xA1, 0x15, 0x74, 0x02, 0xF0, 0x22, 0xE4, 0xFD, 0xFF, 0x12, 0x49, 0x5E, 0x7D, 0x04, 0x7F, 0x01, +0x12, 0x55, 0x87, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0xA1, 0x15, 0x74, 0x04, 0xF0, +0x22, 0x7E, 0x00, 0x7F, 0x04, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0xA1, 0x79, 0xC0, 0x02, 0x08, 0xAA, +0x90, 0xA3, 0xBD, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x81, 0x00, 0xE0, 0x54, 0x0F, 0xFD, 0xAC, +0x07, 0x74, 0x0D, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, 0xF0, 0x74, +0x0D, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, 0x07, 0x74, +0x12, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, 0x11, 0x2C, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, 0x06, 0x2C, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0E, 0xF0, 0x90, 0x04, 0xA7, 0xE4, 0xF0, +0x90, 0x04, 0xA6, 0xF0, 0x90, 0x04, 0xA5, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0xA4, 0x74, 0xFD, 0xF0, +0x74, 0x14, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, 0xFD, 0x74, +0x14, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0x90, 0xA3, 0xBB, 0xE0, +0xFF, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0xA4, 0x0C, 0xEF, 0xF0, 0x90, 0x9F, 0x9F, +0xE0, 0xFF, 0x90, 0x04, 0x1C, 0xE0, 0x6F, 0x70, 0x49, 0x90, 0xA1, 0x1D, 0xE0, 0x64, 0x0E, 0x70, +0x15, 0x90, 0xA4, 0x0C, 0xE0, 0x70, 0x3B, 0x90, 0xA1, 0x16, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x06, +0x04, 0x12, 0x55, 0x7F, 0x80, 0x26, 0x90, 0xA1, 0x1D, 0xE0, 0x64, 0x06, 0x70, 0x24, 0x90, 0xA4, +0x0C, 0xE0, 0x60, 0x1E, 0x90, 0xA1, 0x16, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x06, 0x04, 0xE0, 0x44, +0x40, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0xA1, 0x1D, 0x74, 0x04, 0xF0, 0xE4, 0xFD, 0xFF, 0x12, +0x49, 0x5E, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xFE, 0xEF, 0xC3, 0x13, 0xFD, 0xEF, 0x30, 0xE0, +0x02, 0x7E, 0x80, 0x90, 0xFD, 0x10, 0xED, 0xF0, 0xAF, 0x06, 0x22, 0x00, 0x14, 0xF9, +}; + +void +ODM_ReadFirmware_MP_8723B_FW_MP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723B_FW_MP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723B_FW_MP, ArrayLength_MP_8723B_FW_MP); +#endif + *pFirmwareSize = ArrayLength_MP_8723B_FW_MP; +} + + +const u32 Rtl8723B_PHYREG_Array_MP[Rtl8723B_PHYREG_Array_MPLength] = { +0xc30,0x69e9ac4a, +0xc3c,0x0a979718, +}; + +#endif //CONFIG_MP_INCLUDED + +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.h index 7c411f46406..be51ee4c5ec 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_mp.h @@ -1,45 +1,45 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -#if (RTL8723B_SUPPORT==1) -#ifndef __INC_MP_HW_IMG_8723B_H - -#define __INC_MP_HW_IMG_8723B_H - -#ifdef CONFIG_MP_INCLUDED - -#define Rtl8723BFwBTImgArrayLength 20564 - -#define Rtl8723B_PHYREG_Array_MPLength 4 - -extern u8 Rtl8723BFwBTImgArray[Rtl8723BFwBTImgArrayLength]; -extern const u32 Rtl8723B_PHYREG_Array_MP[Rtl8723B_PHYREG_Array_MPLength]; - -void -ODM_ReadFirmware_MP_8723B_FW_MP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - - -#endif //CONFIG_MP_INCLUDED -#endif -#endif +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#if (RTL8723B_SUPPORT==1) +#ifndef __INC_MP_HW_IMG_8723B_H + +#define __INC_MP_HW_IMG_8723B_H + +#ifdef CONFIG_MP_INCLUDED + +#define Rtl8723BFwBTImgArrayLength 20564 + +#define Rtl8723B_PHYREG_Array_MPLength 4 + +extern u8 Rtl8723BFwBTImgArray[Rtl8723BFwBTImgArrayLength]; +extern const u32 Rtl8723B_PHYREG_Array_MP[Rtl8723B_PHYREG_Array_MPLength]; + +void +ODM_ReadFirmware_MP_8723B_FW_MP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + + +#endif //CONFIG_MP_INCLUDED +#endif +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.c index 7f7b7b2f7c3..d64f967ca27 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.c @@ -1,865 +1,865 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8723B_RadioA[] = { - 0x000, 0x00010000, - 0x0B0, 0x000DFFE0, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x0B1, 0x00000018, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x0B2, 0x00084C00, - 0x0B5, 0x0000D2CC, - 0x0B6, 0x000925AA, - 0x0B7, 0x00000010, - 0x0B8, 0x0000907F, - 0x05C, 0x00000002, - 0x07C, 0x00000002, - 0x07E, 0x00000005, - 0x08B, 0x0006FC00, - 0x0B0, 0x000FF9F0, - 0x01C, 0x000739D2, - 0x01E, 0x00000000, - 0x0DF, 0x00000780, - 0x050, 0x00067435, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x051, 0x0006F10E, - 0x052, 0x000007D3, - 0x90003000, 0x00000000, 0x40000000, 0x00000000, - 0x051, 0x0006F10E, - 0x052, 0x000007D3, - 0x90004000, 0x00000000, 0x40000000, 0x00000000, - 0x051, 0x0006F10E, - 0x052, 0x000007D3, - 0xA0000000, 0x00000000, - 0x051, 0x0006B04E, - 0x052, 0x000007D2, - 0xB0000000, 0x00000000, - 0x053, 0x00000000, - 0x054, 0x00050400, - 0x055, 0x0004026E, - 0x0DD, 0x0000004C, - 0x070, 0x00067435, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x071, 0x0006F10E, - 0x072, 0x000007D3, - 0x90003000, 0x00000000, 0x40000000, 0x00000000, - 0x071, 0x0006F10E, - 0x072, 0x000007D3, - 0x90004000, 0x00000000, 0x40000000, 0x00000000, - 0x071, 0x0006F10E, - 0x072, 0x000007D3, - 0xA0000000, 0x00000000, - 0x071, 0x0006B04E, - 0x072, 0x000007D2, - 0xB0000000, 0x00000000, - 0x073, 0x00000000, - 0x074, 0x00050400, - 0x075, 0x0004026E, - 0x0EF, 0x00000100, - 0x034, 0x0000ADD7, - 0x035, 0x00005C00, - 0x034, 0x00009DD4, - 0x035, 0x00005000, - 0x034, 0x00008DD1, - 0x035, 0x00004400, - 0x034, 0x00007DCE, - 0x035, 0x00003800, - 0x034, 0x00006CD1, - 0x035, 0x00004400, - 0x034, 0x00005CCE, - 0x035, 0x00003800, - 0x034, 0x000048CE, - 0x035, 0x00004400, - 0x034, 0x000034CE, - 0x035, 0x00003800, - 0x034, 0x00002451, - 0x035, 0x00004400, - 0x034, 0x0000144E, - 0x035, 0x00003800, - 0x034, 0x00000051, - 0x035, 0x00004400, - 0x0EF, 0x00000000, - 0x0EF, 0x00000100, - 0x0ED, 0x00000010, - 0x044, 0x0000ADD7, - 0x044, 0x00009DD4, - 0x044, 0x00008DD1, - 0x044, 0x00007DCE, - 0x044, 0x00006CC1, - 0x044, 0x00005CCE, - 0x044, 0x000044D1, - 0x044, 0x000034CE, - 0x044, 0x00002451, - 0x044, 0x0000144E, - 0x044, 0x00000051, - 0x0EF, 0x00000000, - 0x0ED, 0x00000000, - 0x07F, 0x00020080, - 0x0EF, 0x00002000, - 0x03B, 0x000389EF, - 0x03B, 0x000302FE, - 0x03B, 0x00028CE6, - 0x03B, 0x000200BC, - 0x03B, 0x000188A5, - 0x03B, 0x00010FBC, - 0x03B, 0x00008F71, - 0x03B, 0x00000900, - 0x0EF, 0x00000000, - 0x0ED, 0x00000001, - 0x040, 0x000380EF, - 0x040, 0x000302FE, - 0x040, 0x00028CE6, - 0x040, 0x000200BC, - 0x040, 0x000188A5, - 0x040, 0x00010FBC, - 0x040, 0x00008F71, - 0x040, 0x00000900, - 0x0ED, 0x00000000, - 0x082, 0x00080000, - 0x083, 0x00008000, - 0x084, 0x00049F80, - 0x085, 0x00068000, - 0x0A2, 0x00080000, - 0x0A3, 0x00008000, - 0x0A4, 0x00048D80, - 0x0A5, 0x00068000, - 0x0ED, 0x00000002, - 0x0EF, 0x00000002, - 0x056, 0x00000032, - 0x076, 0x00000032, - 0x001, 0x00000780, - -}; - -void -ODM_ReadAndConfig_MP_8723B_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723B_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723B_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8723B(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723B_RadioA(void) -{ - return 28; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; -#endif - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8723B_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", - "MKK", "2.4G", "20M", "HT", "1T", "01", "28", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", - "MKK", "2.4G", "20M", "HT", "1T", "13", "28", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "26", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", - "MKK", "2.4G", "40M", "HT", "1T", "04", "26", - "FCC", "2.4G", "40M", "HT", "1T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", - "MKK", "2.4G", "40M", "HT", "1T", "05", "26", - "FCC", "2.4G", "40M", "HT", "1T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "28", - "MKK", "2.4G", "40M", "HT", "1T", "06", "26", - "FCC", "2.4G", "40M", "HT", "1T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "28", - "MKK", "2.4G", "40M", "HT", "1T", "07", "26", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "28", - "MKK", "2.4G", "40M", "HT", "1T", "08", "26", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", - "MKK", "2.4G", "40M", "HT", "1T", "09", "26", - "FCC", "2.4G", "40M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", - "MKK", "2.4G", "40M", "HT", "1T", "10", "26", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "26", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", - "MKK", "2.4G", "40M", "HT", "1T", "12", "26", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", - "MKK", "2.4G", "40M", "HT", "1T", "13", "26", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63" -}; - -void -ODM_ReadAndConfig_MP_8723B_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8723B_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8723B_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8723B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8723B_RadioA[] = { + 0x000, 0x00010000, + 0x0B0, 0x000DFFE0, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x0B1, 0x00000018, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x0B2, 0x00084C00, + 0x0B5, 0x0000D2CC, + 0x0B6, 0x000925AA, + 0x0B7, 0x00000010, + 0x0B8, 0x0000907F, + 0x05C, 0x00000002, + 0x07C, 0x00000002, + 0x07E, 0x00000005, + 0x08B, 0x0006FC00, + 0x0B0, 0x000FF9F0, + 0x01C, 0x000739D2, + 0x01E, 0x00000000, + 0x0DF, 0x00000780, + 0x050, 0x00067435, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x0006F10E, + 0x052, 0x000007D3, + 0x90003000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x0006F10E, + 0x052, 0x000007D3, + 0x90004000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x0006F10E, + 0x052, 0x000007D3, + 0xA0000000, 0x00000000, + 0x051, 0x0006B04E, + 0x052, 0x000007D2, + 0xB0000000, 0x00000000, + 0x053, 0x00000000, + 0x054, 0x00050400, + 0x055, 0x0004026E, + 0x0DD, 0x0000004C, + 0x070, 0x00067435, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x071, 0x0006F10E, + 0x072, 0x000007D3, + 0x90003000, 0x00000000, 0x40000000, 0x00000000, + 0x071, 0x0006F10E, + 0x072, 0x000007D3, + 0x90004000, 0x00000000, 0x40000000, 0x00000000, + 0x071, 0x0006F10E, + 0x072, 0x000007D3, + 0xA0000000, 0x00000000, + 0x071, 0x0006B04E, + 0x072, 0x000007D2, + 0xB0000000, 0x00000000, + 0x073, 0x00000000, + 0x074, 0x00050400, + 0x075, 0x0004026E, + 0x0EF, 0x00000100, + 0x034, 0x0000ADD7, + 0x035, 0x00005C00, + 0x034, 0x00009DD4, + 0x035, 0x00005000, + 0x034, 0x00008DD1, + 0x035, 0x00004400, + 0x034, 0x00007DCE, + 0x035, 0x00003800, + 0x034, 0x00006CD1, + 0x035, 0x00004400, + 0x034, 0x00005CCE, + 0x035, 0x00003800, + 0x034, 0x000048CE, + 0x035, 0x00004400, + 0x034, 0x000034CE, + 0x035, 0x00003800, + 0x034, 0x00002451, + 0x035, 0x00004400, + 0x034, 0x0000144E, + 0x035, 0x00003800, + 0x034, 0x00000051, + 0x035, 0x00004400, + 0x0EF, 0x00000000, + 0x0EF, 0x00000100, + 0x0ED, 0x00000010, + 0x044, 0x0000ADD7, + 0x044, 0x00009DD4, + 0x044, 0x00008DD1, + 0x044, 0x00007DCE, + 0x044, 0x00006CC1, + 0x044, 0x00005CCE, + 0x044, 0x000044D1, + 0x044, 0x000034CE, + 0x044, 0x00002451, + 0x044, 0x0000144E, + 0x044, 0x00000051, + 0x0EF, 0x00000000, + 0x0ED, 0x00000000, + 0x07F, 0x00020080, + 0x0EF, 0x00002000, + 0x03B, 0x000389EF, + 0x03B, 0x000302FE, + 0x03B, 0x00028CE6, + 0x03B, 0x000200BC, + 0x03B, 0x000188A5, + 0x03B, 0x00010FBC, + 0x03B, 0x00008F71, + 0x03B, 0x00000900, + 0x0EF, 0x00000000, + 0x0ED, 0x00000001, + 0x040, 0x000380EF, + 0x040, 0x000302FE, + 0x040, 0x00028CE6, + 0x040, 0x000200BC, + 0x040, 0x000188A5, + 0x040, 0x00010FBC, + 0x040, 0x00008F71, + 0x040, 0x00000900, + 0x0ED, 0x00000000, + 0x082, 0x00080000, + 0x083, 0x00008000, + 0x084, 0x00049F80, + 0x085, 0x00068000, + 0x0A2, 0x00080000, + 0x0A3, 0x00008000, + 0x0A4, 0x00048D80, + 0x0A5, 0x00068000, + 0x0ED, 0x00000002, + 0x0EF, 0x00000002, + 0x056, 0x00000032, + 0x076, 0x00000032, + 0x001, 0x00000780, + +}; + +void +ODM_ReadAndConfig_MP_8723B_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723B_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723B_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8723B(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723B_RadioA(void) +{ + return 28; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8723B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723B[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723B[] = {0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723B, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8723B_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", + "MKK", "2.4G", "20M", "HT", "1T", "01", "28", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", + "MKK", "2.4G", "20M", "HT", "1T", "13", "28", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "28", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "28", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "28", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "28", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "28", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "28", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "28", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63" +}; + +void +ODM_ReadAndConfig_MP_8723B_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8723B_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8723B_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723B_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8723B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.h index 45a626a087b..32bf0329621 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halhwimg8723b_rf.h @@ -1,89 +1,89 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8723B_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8723B_H -#define __INC_MP_RF_HW_IMG_8723B_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723B_TXPWR_LMT(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8723B_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8723B_H +#define __INC_MP_RF_HW_IMG_8723B_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723B_TXPWR_LMT(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.c index 98ccb68968a..07668c6d69c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.c @@ -1,2681 +1,2681 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -/* 2010/04/25 MH Define the max tx power tracking tx agc power.*/ -#define ODM_TXPWRTRACK_MAX_IDX8723B 6 - -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0]*/ -#define PATH_S0 1 /* RF_PATH_B*/ -#define IDX_0xC94 0 -#define IDX_0xC80 1 -#define IDX_0xC4C 2 -#define IDX_0xC14 0 -#define IDX_0xCA0 1 -#define KEY 0 -#define VAL 1 - -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1]*/ -#define PATH_S1 0 /* RF_PATH_A*/ -#define IDX_0xC9C 0 -#define IDX_0xC88 1 -#define IDX_0xC4C 2 -#define IDX_0xC1C 0 -#define IDX_0xC78 1 - - -/*---------------------------Define Local Constant---------------------------*/ - - -/*============================================================*/ -/* Tx Power Tracking*/ -/*============================================================*/ - - -void setIqkMatrix_8723B( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A = 0, ele_D, ele_C = 0, value32; - - if (OFDM_index >= OFDM_TABLE_SIZE) - OFDM_index = OFDM_TABLE_SIZE-1; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - /*new element A = element D x X*/ - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - if ((IqkResult_X & 0x00000200) != 0) /*consider minus*/ - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8) & 0x000003FF; - - /*new element C = element D x Y*/ - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8) & 0x000003FF; - - /*if (RFPath == ODM_RF_PATH_A)*/ - switch (RFPath) { - case ODM_RF_PATH_A: - /*wirte new elements A, C, D to regC80 and regC94, element B is always 0*/ - value32 = (ele_D<<22) | ((ele_C&0x3F)<<16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - /*wirte new elements A, C, D to regC88 and regC9C, element B is always 0*/ - value32 = (ele_D<<22) | ((ele_C & 0x3F)<<16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - - -VOID -setCCKFilterCoefficient( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -) -{ - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); - } else { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); - } -} - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ -#if 0 /* mark by Lucas@SD4 20140128, suggested by Allen@SD3*/ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE); -#else - PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE); -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -#endif /* #if 0 */ -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte PwrTrackingLimit_OFDM = 34; /*+0dB*/ - u1Byte PwrTrackingLimit_CCK = 28; /*-2dB*/ - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - #endif - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { - /*auto rate*/ - if (pDM_Odm->TxRate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else /*force rate*/ - TxRate = (u1Byte)rate; - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8723B\n")); - - if (TxRate != 0xFF) { - -#if (DM_ODM_SUPPORT_TYPE == (ODM_WIN|ODM_CE)) - /*2 CCK*/ - if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M)) - PwrTrackingLimit_CCK = 28; /*-2dB*/ - /*2 OFDM*/ - else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if (TxRate == MGN_54M) - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - - /*2 HT*/ - else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ - PwrTrackingLimit_OFDM = 38; /*+4dB*/ - else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ - PwrTrackingLimit_OFDM = 36; /*+3dB*/ - else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ - PwrTrackingLimit_OFDM = 34; /*+2dB*/ - - else -#endif - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) { - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (pDM_Odm->mp_mode == TRUE) { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } else { - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - } -#endif - } else if (Method == BBSWING) { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - /* Adjust BB swing by OFDM IQ matrix*/ - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index <= 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) - Final_CCK_Swing_Index = 0; - - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - } else if (Method == MIX_MODE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { - /*BBSwing higher then Limit*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", - PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index <= 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8723B(pDM_Odm, 0, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { - /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - - if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } else if (Final_CCK_Swing_Index <= 0) { - /* Lowest CCK Index = 0*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - setCCKFilterCoefficient(pDM_Odm, 0); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } else { - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { - /*If TxAGC has changed, reset TxAGC again*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); - } - } - } else { - return; /* This method is not supported.*/ - } -} - -VOID -GetDeltaSwingTable_8723B( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - u1Byte channel = priv->pmib->dot11RFEntry.dot11channel; -#else - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte channel = pHalData->CurrentChannel; -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(rate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } - /*else if ( 36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if ( 100 <= channel && channel <= 140) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if ( 149 <= channel && channel <= 173) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - }*/else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - -} - - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; - pConfig->RfPathCount = MAX_PATH_NUM_8723B; - pConfig->ThermalRegAddr = RF_T_METER_8723B; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; - pConfig->DoIQK = DoIQK_8723B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; -} - -/*1 7. IQK*/ -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathA_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB, - IN u1Byte RF_Path - ) -{ - u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; - u1Byte result = 0x00; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - /* Save RF Path */ - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* enable path A PA in TXIQK mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); - /* disable path B PA in TXIQK mode*/ -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 );*/ - - /*1 Tx IQK*/ - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); -/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*Ant switch*/ - if (configPathB || (RF_Path == 0)) - /* wifi switch to S1*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - /* wifi switch to S0*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path A LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - - return result; - -} - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathA_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB, - IN u1Byte RF_Path - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - /* Save RF Path */ - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n")); - /*1 Get TXIMR setting*/ - /*modify RXIQK mode table*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - /*LNA2 off, PA on for Dcut*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*Ant switch*/ - if (configPathB || (RF_Path == 0)) - /* wifi switch to S1*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - /* wifi switch to S0*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path A LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else /*if Tx not OK, ignore Rx*/ - return result; - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - /*1 RX IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n")); - - /*modify RXIQK mode table*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - /*LAN2 on, PA off for Dcut*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ - - /*PA, PAD setting*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); - - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*Ant switch*/ - if (configPathB || (RF_Path == 0)) - /* wifi switch to S1*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - /* wifi switch to S0*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path A LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - /* PA/PAD controlled by 0x0*/ - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); - - /* Allen 20141201 */ - tmp = (regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - /*if Tx is OK, check whether Rx is OK*/ - if (!(regEAC & BIT27) && - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36) && - (((regEA4 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - else /*if Tx not OK, ignore Rx*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - - return result; - - -} - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathB_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - /* Save RF Path*/ - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* in TXIQK mode*/ -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );*/ - /* enable path B PA in TXIQK mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); - - - - /*1 Tx IQK*/ - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114);*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*switch to path B*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path B LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - - return result; - -} - - - -u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ -phy_PathB_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - /* Save RF Path*/ - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /*switch to path B*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*1 Get TXIMR setting*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n")); - /*modify RXIQK mode table*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - /*open PA S1 & SMIXER*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd); - - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - - /*path-B IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f );*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*switch to path B*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path B TXIQK @ RXIQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000) >> 16) != 0x142) && - (((regE9C & 0x03FF0000) >> 16) != 0x42)) - - result |= 0x01; - else /*if Tx not OK, ignore Rx*/ - return result; - - - - u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - /*1 RX IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ - - /*open PA S1 & close SMIXER*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); - - /*PA, PAD setting*/ -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);*/ -/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ - - - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-B IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - /*switch to path B*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - /*GNT_BT = 0*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - /*One shot, path B LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - /*restore Ant Path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - /*GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - /* Allen 20141201 */ - tmp = (regEAC & 0x03FF0000) >> 16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000) >> 16) != 0x132) && - (((regEAC & 0x03FF0000) >> 16) != 0x36) && - (((regEA4 & 0x03FF0000) >> 16) < 0x11a) && - (((regEA4 & 0x03FF0000) >> 16) > 0xe6) && - (tmp < 0x1a)) - - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - - -} - - -VOID -_PHY_PathAFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); - - if (final_candidate == 0xFF) - return; - else if (bIQKOK) { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - /*2 Tx IQC*/ - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0) >> 6)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); - - /* <20130226, Kordan> Saving RxIQC, otherwise not initialized.*/ - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);*/ - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (RTL_ABS(reg, 0x100) >= 16) - reg = 0x100; -#endif - - /*2 Rx IQC*/ - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - - } -} - -VOID -_PHY_PathBFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); - - if (final_candidate == 0xFF) - return; - else if (bIQKOK) { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - - /*2 Tx IQC*/ - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE;*/ -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);*/ - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - return; - } - - /*2 Rx IQC*/ - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); - - reg = (result[final_candidate][7] >> 6) & 0xF; -/* ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28) | (ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord) & 0x0fffffff); - } -} - -VOID -ODM_SetIQCbyRFpath( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RFpath - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && - (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && - (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && - (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) { - - if (RFpath) { - - /*S1: RFpath = 0, S0:RFpath = 1*/ - /*S0 TX IQC*/ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); - /*S0 RX IQC*/ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); - } else { - /*S1 TX IQC*/ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); - /*S1 RX IQC*/ - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); - } - } -} - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for (i = 0; i < RegisterNum; i++) - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - -} - - -VOID -_PHY_SaveMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - -} - -VOID -_PHY_ReloadMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; - if (FALSE == is2T) { - pathOn = 0x01c00014; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); - } else { - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - } - - for (i = 1; i < IQK_ADDA_REG_NUM; i++) - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); -} - -VOID -_PHY_MACSettingCalibration8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); -} - -VOID -_PHY_PIModeSwitch8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; - BOOLEAN bResult = TRUE; - BOOLEAN is2T = TRUE; - - s4Byte tmp1 = 0, tmp2 = 0; - - if (is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte i; - u1Byte PathAOK, PathBOK; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN}; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - - u4Byte Path_SEL_BB; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 1; -#else - const u4Byte retryCount = 2; -#endif -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if ((pAdapter->registrypriv.mp_mode == 1) && (pAdapter->mppriv.mode == 3)) { - return; - } -#endif - /* Note: IQ calibration must be performed after loading - PHY_REG.txt , and radio_a, radio_b.txt */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) -#ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if (t == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - - /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); */ - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - /*RX IQ calibration setting for 8723B D cut large current issue when leaving IPS*/ - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); - -/*path A TX IQK*/ -#if 1 - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path); -#else - PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path); -#endif - if (PathAOK == 0x01) { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - } -#endif - -/*path A RXIQK*/ -#if 1 - - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path); -#else - PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path); -#endif - if (PathAOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ -/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - - } - - if (0x00 == PathAOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); -#endif - -/*path B IQK*/ -#if 1 - - if (is2T) { -/*path B TX IQK*/ -#if 1 - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8723B(pAdapter); -#else - PathBOK = phy_PathB_IQK_8723B(pDM_Odm); -#endif - if (PathBOK == 0x01) { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - } -#endif - -/*path B RX IQK*/ -#if 1 - -for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T); -#else - PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T); -#endif - if (PathBOK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); -/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ -/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); - } - -#endif - - - if (0x00 == PathBOK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } -#endif - - /*Back to BB mode, load original value*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); - - if (t != 0) { - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - /*Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /*Reload MAC parameters*/ - _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - /*Reload ADDA power saving parameters*/ - _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /*Reload MAC parameters*/ - _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - /*Allen initial gain 0xc50, Restore RX initial gain*/ - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - /*load 0xe30 IQC default value*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n")); - -} - - -VOID -phy_LCCalibrate_8723B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - - if (pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3) { - return; - } -#endif - /*Check continuous TX and Packet TX*/ - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg&0x70) != 0) /*Deal with contisuous TX case*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); /*disable all continuous TX*/ - else /* Deal with Packet TX case*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ - - if ((tmpReg&0x70) != 0) { - /*1. Read original RF mode*/ - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - - if (is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - - if (is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#endif - - /*2. Set RF mode = standby mode*/ - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - /*3. Read RF reg18*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - /*4. Set LC calibration begin bit15*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF*/ - - /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ - if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); - - - /*Restore original situation*/ - if ((tmpReg&0x70) != 0) { /*Deal with contisuous TX case */ - /*Path-A*/ - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - /*Path-B*/ - if (is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } else - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - -} - - -/*IQK version:V2.5 20140123*/ -/*IQK is controlled by Is2ant, RF path*/ -VOID -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery, - IN BOOLEAN bRestore, - IN BOOLEAN Is2ant, /*false:1ant, true:2-ant*/ - IN u1Byte RF_Path /*0:S1, 1:S0*/ - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif -#endif - - s4Byte result[4][8]; - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - - u4Byte GNT_BT_default; - u4Byte StartTime; - s4Byte ProgressingTime; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - #if !(RTL8723B_SUPPORT == 1) - if (priv->pshare->IQK_88E_done) - bReCovery = 1; - priv->pshare->IQK_88E_done = 1; - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - -#endif - -#if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ - if (bSingleTone || bCarrierSuppression) - return; - -#ifdef DISABLE_BB_RF - return; -#endif - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - if (bRestore) { - u4Byte offset, data; - u1Byte path, bResult = SUCCESS; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B); - - /*Restore TX IQK*/ - for (i = 0; i < 3; ++i) { - offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; - data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; - if ((offset == 0) || (i == 1 && data == 0)) { /* 0xc80, 0xc88 ==> index=1 */ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - bResult = FAIL; - break; - } - /*RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));*/ - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); - } - - /* Restore RX IQK*/ - for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; - data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; - if ((offset == 0) || (i == 0 && data == 0)) { /* 0xc14, 0xc1c ==> index=0 */ - #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - bResult = FAIL; - break; - } - /*RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));*/ - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); - } - - if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { - bResult = FAIL; - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); - } - - if (bResult == SUCCESS) - goto out; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) -#else - if (bReCovery && (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - goto out; - } - StartTime = ODM_GetCurrentTime(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - priv->pshare->IQK_total_cnt++; - - /*save default GNT_BT*/ - GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i = 0; i < 3; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path); -#else - phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path); -#endif - - if (i == 1) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); -#endif - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); - break; - } - } - - if (i == 2) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); -#endif - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); -#endif - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); - } else { - for (i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if (RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } - - if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { - for (i = 0; i < 8; i++) { - if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) - result[final_candidate][i] = 0x100; - else - result[final_candidate][i] = 0; - } - } - - for (i = 0; i < 4; i++) { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if (final_candidate != 0xff) { - priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; - panic_printk("Load IQK default value"); - priv->pshare->IQK_fail_cnt++; - } - -#if MP_DRIVER == 1 - if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) -#endif - { - if (RegE94 != 0) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#else - _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#endif - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if MP_DRIVER == 1 - if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) -#endif - { - if (RegEB4 != 0) - _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -/*To Fix BSOD when final_candidate is 0xff -by sherry 20120321 */ - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - /*restore GNT_BT*/ - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default); - - /*Resotr RX mode table parameter*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); - - /*set GNT_BT= HW control*/ -/* ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); - ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0); */ - - if (Is2ant) { - if (RF_Path == 0x0) - ODM_SetIQCbyRFpath(pDM_Odm, 0); - else - ODM_SetIQCbyRFpath(pDM_Odm, 1); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); - -out: - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); -} - -VOID -PHY_LCCalibrate_8723B( - PVOID pDM_VOID - ) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - u4Byte StartTime; - s4Byte ProgressingTime; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif -#endif - - - - -#if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#ifdef DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - -#endif - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ - if (bSingleTone || bCarrierSuppression) - return; - - StartTime = ODM_GetCurrentTime(pDM_Odm); - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - - phy_LCCalibrate_8723B(pDM_Odm, FALSE); - - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); -} - -/*Analog Pre-distortion calibration*/ -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ - -} - -VOID -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - return; - -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if (pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_2T2R(pHalData->VersionID)) { - phy_APCalibrate_8723B(pAdapter, delta, TRUE); - } else -#endif - { - /* For 88C 1T1R */ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8723B(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); -#endif - } -} -VOID phy_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (bMain) { /* Left antenna */ - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); - } else { - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); - } -} -VOID PHY_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -#ifdef DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); -#endif - -} - - -/*return value TRUE => Main; FALSE => Aux */ - -BOOLEAN phy_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - if (ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) - return TRUE; - else - return FALSE; - -} - - - -/*return value TRUE => Main; FALSE => Aux*/ -BOOLEAN PHY_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#endif -#ifdef DISABLE_BB_RF - return TRUE; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); -#endif - -} +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +/* 2010/04/25 MH Define the max tx power tracking tx agc power.*/ +#define ODM_TXPWRTRACK_MAX_IDX8723B 6 + +/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0]*/ +#define PATH_S0 1 /* RF_PATH_B*/ +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 +#define IDX_0xC14 0 +#define IDX_0xCA0 1 +#define KEY 0 +#define VAL 1 + +/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1]*/ +#define PATH_S1 0 /* RF_PATH_A*/ +#define IDX_0xC9C 0 +#define IDX_0xC88 1 +#define IDX_0xC4C 2 +#define IDX_0xC1C 0 +#define IDX_0xC78 1 + + +/*---------------------------Define Local Constant---------------------------*/ + + +/*============================================================*/ +/* Tx Power Tracking*/ +/*============================================================*/ + + +void setIqkMatrix_8723B( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE-1; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + /*new element A = element D x X*/ + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + if ((IqkResult_X & 0x00000200) != 0) /*consider minus*/ + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8) & 0x000003FF; + + /*new element C = element D x Y*/ + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8) & 0x000003FF; + + /*if (RFPath == ODM_RF_PATH_A)*/ + switch (RFPath) { + case ODM_RF_PATH_A: + /*wirte new elements A, C, D to regC80 and regC94, element B is always 0*/ + value32 = (ele_D<<22) | ((ele_C&0x3F)<<16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + /*wirte new elements A, C, D to regC88 and regC9C, element B is always 0*/ + value32 = (ele_D<<22) | ((ele_C & 0x3F)<<16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + + +VOID +setCCKFilterCoefficient( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +) +{ + if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); + } else { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); + } +} + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ +#if 0 /* mark by Lucas@SD4 20140128, suggested by Allen@SD3*/ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE); +#else + PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE); +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +#endif /* #if 0 */ +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte PwrTrackingLimit_OFDM = 34; /*+0dB*/ + u1Byte PwrTrackingLimit_CCK = 28; /*-2dB*/ + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + #endif + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { + /*auto rate*/ + if (pDM_Odm->TxRate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else /*force rate*/ + TxRate = (u1Byte)rate; + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8723B\n")); + + if (TxRate != 0xFF) { + +#if (DM_ODM_SUPPORT_TYPE == (ODM_WIN|ODM_CE)) + /*2 CCK*/ + if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M)) + PwrTrackingLimit_CCK = 28; /*-2dB*/ + /*2 OFDM*/ + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + + /*2 HT*/ + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /*QPSK/BPSK*/ + PwrTrackingLimit_OFDM = 38; /*+4dB*/ + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /*16QAM*/ + PwrTrackingLimit_OFDM = 36; /*+3dB*/ + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /*64QAM*/ + PwrTrackingLimit_OFDM = 34; /*+2dB*/ + + else +#endif + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) { + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (pDM_Odm->mp_mode == TRUE) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else { + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + } +#endif + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + /* Adjust BB swing by OFDM IQ matrix*/ + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index <= 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) + Final_CCK_Swing_Index = 0; + + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + } else if (Method == MIX_MODE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { + /*BBSwing higher then Limit*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", + PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index <= 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8723B(pDM_Odm, 0, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { + /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + + if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } else if (Final_CCK_Swing_Index <= 0) { + /* Lowest CCK Index = 0*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + setCCKFilterCoefficient(pDM_Odm, 0); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } else { + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) { + /*If TxAGC has changed, reset TxAGC again*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); + } + } + } else { + return; /* This method is not supported.*/ + } +} + +VOID +GetDeltaSwingTable_8723B( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + u1Byte channel = priv->pmib->dot11RFEntry.dot11channel; +#else + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte channel = pHalData->CurrentChannel; +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(rate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } + /*else if ( 36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if ( 100 <= channel && channel <= 140) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if ( 149 <= channel && channel <= 173) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + }*/else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + +} + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; + pConfig->RfPathCount = MAX_PATH_NUM_8723B; + pConfig->ThermalRegAddr = RF_T_METER_8723B; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; + pConfig->DoIQK = DoIQK_8723B; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; +} + +/*1 7. IQK*/ +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathA_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB, + IN u1Byte RF_Path + ) +{ + u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; + u1Byte result = 0x00; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + /* Save RF Path */ + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* enable path A PA in TXIQK mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); + /* disable path B PA in TXIQK mode*/ +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 );*/ + + /*1 Tx IQK*/ + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); +/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*Ant switch*/ + if (configPathB || (RF_Path == 0)) + /* wifi switch to S1*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + /* wifi switch to S0*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path A LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + + return result; + +} + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathA_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB, + IN u1Byte RF_Path + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + /* Save RF Path */ + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n")); + /*1 Get TXIMR setting*/ + /*modify RXIQK mode table*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + /*LNA2 off, PA on for Dcut*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*Ant switch*/ + if (configPathB || (RF_Path == 0)) + /* wifi switch to S1*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + /* wifi switch to S0*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path A LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else /*if Tx not OK, ignore Rx*/ + return result; + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + /*1 RX IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n")); + + /*modify RXIQK mode table*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + /*LAN2 on, PA off for Dcut*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ + + /*PA, PAD setting*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); + + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*Ant switch*/ + if (configPathB || (RF_Path == 0)) + /* wifi switch to S1*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + /* wifi switch to S0*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path A LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + /* PA/PAD controlled by 0x0*/ + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); + + /* Allen 20141201 */ + tmp = (regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + /*if Tx is OK, check whether Rx is OK*/ + if (!(regEAC & BIT27) && + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36) && + (((regEA4 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + else /*if Tx not OK, ignore Rx*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + + return result; + + +} + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathB_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + /* Save RF Path*/ + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* in TXIQK mode*/ +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );*/ + /* enable path B PA in TXIQK mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); + + + + /*1 Tx IQK*/ + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114);*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*switch to path B*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path B LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + + return result; + +} + + + +u1Byte /*bit0 = 1 => Tx OK, bit1 = 1 => Rx OK*/ +phy_PathB_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + /* Save RF Path*/ + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /*switch to path B*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*1 Get TXIMR setting*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n")); + /*modify RXIQK mode table*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + /*open PA S1 & SMIXER*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd); + + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + + /*path-B IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +/* ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f );*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*switch to path B*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path B TXIQK @ RXIQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + + result |= 0x01; + else /*if Tx not OK, ignore Rx*/ + return result; + + + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + /*1 RX IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ + + /*open PA S1 & close SMIXER*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); + + /*PA, PAD setting*/ +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);*/ +/* ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ + + + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-B IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +/* ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + /*switch to path B*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + /*GNT_BT = 0*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + /*One shot, path B LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + /*restore Ant Path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + /*GNT_BT = 1*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + /* Allen 20141201 */ + tmp = (regEAC & 0x03FF0000) >> 16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36) && + (((regEA4 & 0x03FF0000) >> 16) < 0x11a) && + (((regEA4 & 0x03FF0000) >> 16) > 0xe6) && + (tmp < 0x1a)) + + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); + + if (final_candidate == 0xFF) + return; + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + /*2 Tx IQC*/ + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0) >> 6)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); + + /* <20130226, Kordan> Saving RxIQC, otherwise not initialized.*/ + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; +/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);*/ + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (RTL_ABS(reg, 0x100) >= 16) + reg = 0x100; +#endif + + /*2 Rx IQC*/ + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + + } +} + +VOID +_PHY_PathBFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); + + if (final_candidate == 0xFF) + return; + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + + /*2 Tx IQC*/ + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); +/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE;*/ +/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);*/ + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; +/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); */ + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + return; + } + + /*2 Rx IQC*/ + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][7] >> 6) & 0xF; +/* ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); */ + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28) | (ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord) & 0x0fffffff); + } +} + +VOID +ODM_SetIQCbyRFpath( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RFpath + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && + (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && + (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && + (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) { + + if (RFpath) { + + /*S1: RFpath = 0, S0:RFpath = 1*/ + /*S0 TX IQC*/ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); + /*S0 RX IQC*/ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); + } else { + /*S1 TX IQC*/ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); + /*S1 RX IQC*/ + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); + } + } +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0; i < RegisterNum; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + +} + + +VOID +_PHY_SaveMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + +} + +VOID +_PHY_ReloadMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; + if (FALSE == is2T) { + pathOn = 0x01c00014; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); + } else { + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + } + + for (i = 1; i < IQK_ADDA_REG_NUM; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); +} + +VOID +_PHY_MACSettingCalibration8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); +} + +VOID +_PHY_PIModeSwitch8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; + BOOLEAN bResult = TRUE; + BOOLEAN is2T = TRUE; + + s4Byte tmp1 = 0, tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN}; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + + u4Byte Path_SEL_BB; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 1; +#else + const u4Byte retryCount = 2; +#endif +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if ((pAdapter->registrypriv.mp_mode == 1) && (pAdapter->mppriv.mode == 3)) { + return; + } +#endif + /* Note: IQ calibration must be performed after loading + PHY_REG.txt , and radio_a, radio_b.txt */ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if (t == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); */ + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + /*RX IQ calibration setting for 8723B D cut large current issue when leaving IPS*/ + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); + +/*path A TX IQK*/ +#if 1 + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path); +#else + PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path); +#endif + if (PathAOK == 0x01) { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + } +#endif + +/*path A RXIQK*/ +#if 1 + + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path); +#else + PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path); +#endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ +/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + + } + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); +#endif + +/*path B IQK*/ +#if 1 + + if (is2T) { +/*path B TX IQK*/ +#if 1 + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8723B(pAdapter); +#else + PathBOK = phy_PathB_IQK_8723B(pDM_Odm); +#endif + if (PathBOK == 0x01) { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + } +#endif + +/*path B RX IQK*/ +#if 1 + +for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T); +#else + PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T); +#endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ +/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); + } + +#endif + + + if (0x00 == PathBOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } +#endif + + /*Back to BB mode, load original value*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + + if (t != 0) { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /*Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /*Reload MAC parameters*/ + _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + /*Reload ADDA power saving parameters*/ + _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /*Reload MAC parameters*/ + _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + /*Allen initial gain 0xc50, Restore RX initial gain*/ + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + /*load 0xe30 IQC default value*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n")); + +} + + +VOID +phy_LCCalibrate_8723B( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + + if (pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3) { + return; + } +#endif + /*Check continuous TX and Packet TX*/ + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg&0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + if ((tmpReg&0x70) != 0) { + /*1. Read original RF mode*/ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + + if (is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + + if (is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#endif + + /*2. Set RF mode = standby mode*/ + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + /*3. Read RF reg18*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + /*4. Set LC calibration begin bit15*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF*/ + + /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ + if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); + + + /*Restore original situation*/ + if ((tmpReg&0x70) != 0) { /*Deal with contisuous TX case */ + /*Path-A*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + /*Path-B*/ + if (is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } else + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + +} + + +/*IQK version:V2.5 20140123*/ +/*IQK is controlled by Is2ant, RF path*/ +VOID +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore, + IN BOOLEAN Is2ant, /*false:1ant, true:2-ant*/ + IN u1Byte RF_Path /*0:S1, 1:S0*/ + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif +#endif + + s4Byte result[4][8]; + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + + u4Byte GNT_BT_default; + u4Byte StartTime; + s4Byte ProgressingTime; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + #if !(RTL8723B_SUPPORT == 1) + if (priv->pshare->IQK_88E_done) + bReCovery = 1; + priv->pshare->IQK_88E_done = 1; + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + +#endif + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ + if (bSingleTone || bCarrierSuppression) + return; + +#ifdef DISABLE_BB_RF + return; +#endif + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + if (bRestore) { + u4Byte offset, data; + u1Byte path, bResult = SUCCESS; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B); + + /*Restore TX IQK*/ + for (i = 0; i < 3; ++i) { + offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; + if ((offset == 0) || (i == 1 && data == 0)) { /* 0xc80, 0xc88 ==> index=1 */ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + #endif + bResult = FAIL; + break; + } + /*RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));*/ + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); + } + + /* Restore RX IQK*/ + for (i = 0; i < 2; ++i) { + offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; + if ((offset == 0) || (i == 0 && data == 0)) { /* 0xc14, 0xc1c ==> index=0 */ + #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + #endif + bResult = FAIL; + break; + } + /*RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));*/ + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); + } + + if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { + bResult = FAIL; + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); + } + + if (bResult == SUCCESS) + goto out; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) +#else + if (bReCovery && (!pAdapter->bInHctTest)) /*YJ,add for PowerTest,120405*/ +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + goto out; + } + StartTime = ODM_GetCurrentTime(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + priv->pshare->IQK_total_cnt++; + + /*save default GNT_BT*/ + GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path); +#else + phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path); +#endif + + if (i == 1) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); +#endif + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); +#endif + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); +#endif + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + for (i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if (RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } + + if ((result[final_candidate][0] | result[final_candidate][2] | result[final_candidate][4] | result[final_candidate][6]) == 0) { + for (i = 0; i < 8; i++) { + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[final_candidate][i] = 0x100; + else + result[final_candidate][i] = 0; + } + } + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + priv->pshare->RegE94 = pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + priv->pshare->RegE9C = pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; + panic_printk("Load IQK default value"); + priv->pshare->IQK_fail_cnt++; + } + +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) +#endif + { + if (RegE94 != 0) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) +#endif + { + if (RegEB4 != 0) + _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +/*To Fix BSOD when final_candidate is 0xff +by sherry 20120321 */ + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + /*restore GNT_BT*/ + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default); + + /*Resotr RX mode table parameter*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); + + /*set GNT_BT= HW control*/ +/* ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); + ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0); */ + + if (Is2ant) { + if (RF_Path == 0x0) + ODM_SetIQCbyRFpath(pDM_Odm, 0); + else + ODM_SetIQCbyRFpath(pDM_Odm, 1); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); + +out: + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); +} + +VOID +PHY_LCCalibrate_8723B( + PVOID pDM_VOID + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + u4Byte StartTime; + s4Byte ProgressingTime; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif +#endif + + + + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#ifdef DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + +#endif + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ + if (bSingleTone || bCarrierSuppression) + return; + + StartTime = ODM_GetCurrentTime(pDM_Odm); + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + + phy_LCCalibrate_8723B(pDM_Odm, FALSE); + + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); +} + +/*Analog Pre-distortion calibration*/ +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ + +} + +VOID +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; + +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if (pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) { + phy_APCalibrate_8723B(pAdapter, delta, TRUE); + } else +#endif + { + /* For 88C 1T1R */ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8723B(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); +#endif + } +} +VOID phy_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (bMain) { /* Left antenna */ + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); + } else { + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); + } +} +VOID PHY_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +#ifdef DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); +#endif + +} + + +/*return value TRUE => Main; FALSE => Aux */ + +BOOLEAN phy_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + if (ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) + return TRUE; + else + return FALSE; + +} + + + +/*return value TRUE => Main; FALSE => Aux*/ +BOOLEAN PHY_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#endif +#ifdef DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); +#endif + +} diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.h index 629ea5e0ed4..0e98f834646 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ap.h @@ -1,126 +1,126 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8723B_H__ -#define __HAL_PHY_RF_8723B_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8723B 20 -#define IQK_DEFERRED_TIME_8723B 4 -#define index_mapping_NUM_8723B 15 -#define AVG_THERMAL_NUM_8723B 4 -#define RF_T_METER_8723B 0x42 - - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -/*1 7. IQK */ - -void -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery, - IN BOOLEAN bRestore, - IN BOOLEAN Is2ant, - IN u1Byte RF_Path); - -VOID -ODM_SetIQCbyRFpath( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RFpath - ); - - -void -PHY_LCCalibrate_8723B( - IN PVOID pDM_VOID -); - - -void -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8723B( - IN PADAPTER pAdapter); - -VOID -_PHY_SaveADDARegisters_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - -#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723B_H__ +#define __HAL_PHY_RF_8723B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8723B 20 +#define IQK_DEFERRED_TIME_8723B 4 +#define index_mapping_NUM_8723B 15 +#define AVG_THERMAL_NUM_8723B 4 +#define RF_T_METER_8723B 0x42 + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +/*1 7. IQK */ + +void +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore, + IN BOOLEAN Is2ant, + IN u1Byte RF_Path); + +VOID +ODM_SetIQCbyRFpath( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RFpath + ); + + +void +PHY_LCCalibrate_8723B( + IN PVOID pDM_VOID +); + + +void +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723B( + IN PADAPTER pAdapter); + +VOID +_PHY_SaveADDARegisters_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.c index d2469b02adf..fdb1480b540 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.c @@ -1,3959 +1,3959 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8723B 6 - -// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] -#define PATH_S0 1 // RF_PATH_B -#define IDX_0xC94 0 -#define IDX_0xC80 1 -#define IDX_0xC4C 2 -#define IDX_0xC14 0 -#define IDX_0xCA0 1 -#define KEY 0 -#define VAL 1 - -// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] -#define PATH_S1 0 // RF_PATH_A -#define IDX_0xC9C 0 -#define IDX_0xC88 1 -#define IDX_0xC4C 2 -#define IDX_0xC1C 0 -#define IDX_0xC78 1 - - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8723B( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A=0, ele_D, ele_C=0, value32; - - if (OFDM_index >= OFDM_TABLE_SIZE) - OFDM_index = OFDM_TABLE_SIZE-1; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - //new element A = element D x X - if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - - //if (RFPath == ODM_RF_PATH_A) - switch (RFPath) - { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); - - break; - default: - break; - } - } - else - { - switch (RFPath) - { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - - -VOID -setCCKFilterCoefficient( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -) -{ - if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); - } -} - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ -#if 0 // mark by Lucas@SD4 20140128, suggested by Allen@SD3 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE); -#else - PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE); -#endif - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -#endif // #if 0 -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 34; //+0dB - u1Byte PwrTrackingLimit_CCK= 28; //-2dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = 28; //-2dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM= 36; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit_OFDM= 34; //+2dB - - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit_OFDM= 38; //+4dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit_OFDM= 36; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit_OFDM= 34; //+2dB - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) - { - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - if (pDM_Odm->mp_mode == TRUE) - { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } - else - { - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); - } -#endif - } - else if (Method == BBSWING) - { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - // Adjust BB swing by OFDM IQ matrix - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index <= 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) - Final_CCK_Swing_Index = 0; - - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", - PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index <= 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - setIqkMatrix_8723B(pDM_Odm, 0, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - - if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } - else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0 - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - setCCKFilterCoefficient(pDM_Odm, 0); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } - else - { - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); - } - } - } - else - { - return; // This method is not supported. - } -} - -VOID -GetDeltaSwingTable_8723B( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; - pConfig->RfPathCount = MAX_PATH_NUM_8723B; - pConfig->ThermalRegAddr = RF_T_METER_8723B; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; - pConfig->DoIQK = DoIQK_8723B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB, - IN u1Byte RF_Path - ) -{ - u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; - u1Byte result = 0x00; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - // Save RF Path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // enable path A PA in TXIQK mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); - // disable path B PA in TXIQK mode -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 ); - - //1 Tx IQK - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - //path-A IQK setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //Ant switch - if (configPathB || (RF_Path == 0)) - // wifi switch to S1 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - // wifi switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); - //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - - return result; - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - } - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB, - IN u1Byte RF_Path - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp, Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - // Save RF Path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n")); - //1 Get TXIMR setting - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - //LNA2 off, PA on for Dcut - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //Ant switch - if (configPathB || (RF_Path == 0)) - // wifi switch to S1 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - // wifi switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); - //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n")); - - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); - //LAN2 on, PA off for Dcut - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); - - //PA, PAD setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f ); - - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //Ant switch - if (configPathB || (RF_Path == 0)) - // wifi switch to S1 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else - // wifi switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path A LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 ); - - /* Allen 20141201 */ - tmp=(regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)&& - (((regEA4 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - else //if Tx not OK, ignore Rx - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - // Save RF Path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // in TXIQK mode -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); - // enable path B PA in TXIQK mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); - - - - //1 Tx IQK - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - //path-A IQK setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //switch to path B - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - - return result; - -#if 0 - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - -#endif -} - - - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); - - // Save RF Path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - //switch to path B - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n")); - //modify RXIQK mode table -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 ); - //open PA S1 & SMIXER - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd ); - - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f ); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //switch to path B - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path B TXIQK @ RXIQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n")); - - //modify RXIQK mode table - //<20121009, Kordan> RF Mode = 3 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); - - //open PA S1 & close SMIXER - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); - - //PA, PAD setting -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); - - - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); - - //switch to path B - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); - - //GNT_BT = 0 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); - - //One shot, path B LOK & IQK -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //restore Ant Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); - //GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - // PA/PAD controlled by 0x0 - //leave IQK mode -// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x00000000); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 ); - - - -#if 0 - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - - /* Allen 20141201 */ - tmp=(regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36) && - (((regEA4 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - - -} - - -VOID -_PHY_PathAFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - //2 Tx IQC - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); - - // <20130226, Kordan> Saving RxIQC, otherwise not initialized. - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; -// pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - - //2 Rx IQC - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - - } -} - -VOID -_PHY_PathBFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - - //2 Tx IQC - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); -// pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; -// pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - - if(bTxOnly) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; -// pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - return; - } - - //2 Rx IQC - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); - - reg = (result[final_candidate][7] >> 6) & 0xF; -// ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(ODM_GetBBReg(pDM_Odm,rOFDM0_RxIQExtAnta, bMaskDWord)& 0x0fffffff); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c - -VOID -ODM_SetIQCbyRFpath( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RFpath - ) -{ - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)&& - (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) - { - if(RFpath) //S1: RFpath = 0, S0:RFpath = 1 - { - //S0 TX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); - //S0 RX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); - } - else - { - //S1 TX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); - //S1 RX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); - } - } -} - -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s/%d/%d\n", - rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; - if(FALSE == is2T){ - pathOn = 0x01c00014; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); -//Allen - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); -// - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); -} - -VOID -_PHY_PIModeSwitch8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -//#else - BOOLEAN is2T = TRUE; -//#endif - - s4Byte tmp1 = 0,tmp2 = 0; - - if(is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - - if((i==1) || (i==3) || (i==5) || (i==7)) - { - if((result[c1][i]& 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if((result[c2][i]& 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } - else - { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte i; - u1Byte PathAOK, PathBOK; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - - u4Byte Path_SEL_BB; -// u4Byte Path_SEL_BB, Path_SEL_RF; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 1; -#else - const u4Byte retryCount = 2; -#endif -#endif - -if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 ) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n", __func__)); - return; -} - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if(t==0) - { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - - // Save ADDA parameters, turn Path A ADDA on -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - -//no serial mode -#if 0 - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch8723B(pAdapter, TRUE); -#else - _PHY_PIModeSwitch8723B(pDM_Odm, TRUE); -#endif - } -#endif - - //save RF path for 8723B -// Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); -// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - -//for 8723B -#if 0 - if(is2T) - { - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } -#endif - - -//no APK -#if 0 - //Page B init - //AP or IQK - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } -#endif - -//RX IQ calibration setting for 8723B D cut large current issue when leaving IPS - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); -/* -//LOK RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); -*/ - - -//path A TX IQK -#if 1 - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path); -#else - PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path); -#endif -// if(PathAOK == 0x03){ - if(PathAOK == 0x01){ - // Path A Tx IQK Success - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } -#if 0 - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } -#endif - -//path A RXIQK -#if 1 - - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path); -#else - PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path); -#endif - if(PathAOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); - } - } - - if(0x00 == PathAOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); - } -#endif - -//path B IQK -#if 1 - - if(is2T){ - -/* -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// _PHY_PathAStandBy8723B(pAdapter); - - // Turn Path B ADDA on - _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T); -#else -// _PHY_PathAStandBy8723B(pDM_Odm); - - // Turn Path B ADDA on - _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif -*/ - -//path B TX IQK -#if 1 - for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8723B(pAdapter); -#else - PathBOK = phy_PathB_IQK_8723B(pDM_Odm); -#endif -// if(PathBOK == 0x03){ - if(PathBOK == 0x01){ - // Path B Tx IQK Success - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } -#if 0 - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } -#endif - -//path B RX IQK -#if 1 - -for(i = 0 ; i < retryCount ; i++){ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T); -#else - PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T); -#endif - if(PathBOK == 0x03){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); - } - } - -#endif - -////////Allen end ///////// - if(0x00 == PathBOK){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); - } - } -#endif //pathB IQK - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); - - if(t!=0) - { - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// _PHY_PIModeSwitch8723B(pAdapter, FALSE); -#else -// _PHY_PIModeSwitch8723B(pDM_Odm, FALSE); -#endif - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - //Reload RF path -// ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); - - //Allen initial gain 0xc50 - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if(is2T){ - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n")); - -} - - -VOID -phy_LCCalibrate_8723B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 ) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n", __func__)); - return; - } - - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF - - // Channel 10 LC calibration issue for 8723bs with 26M xtal - if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); - } - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == ODM_RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - } - else if(path == ODM_RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#endif - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == ODM_RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - if(path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if(path == ODM_RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - -//IQK version:V2.5 20140123 -//IQK is controlled by Is2ant, RF path -VOID -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery, - IN BOOLEAN bRestore, - IN BOOLEAN Is2ant, //false:1ant, true:2-ant - IN u1Byte RF_Path //0:S1, 1:S0 - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; -// u4Byte Path_SEL_BB = 0; - u4Byte GNT_BT_default; - u4Byte StartTime; - s4Byte ProgressingTime; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; - -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - -#if DISABLE_BB_RF - return; -#endif - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - if (bRestore) { - u4Byte offset, data; - u1Byte path, bResult = SUCCESS; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - //#define PATH_S0 1 // RF_PATH_B - //#define PATH_S1 0 // RF_PATH_A - - path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B); - - // Restore TX IQK - for (i = 0; i < 3; ++i) { - offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; - data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; - if ((offset == 0) || (i == 1 && data == 0)) { /* 0xc80, 0xc88 ==> index=1 */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s =>path:%s Restore TX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B")); - bResult = FAIL; - break; - } - //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); - ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data); - } - - // Restore RX IQK - for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; - data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; - if ((offset == 0) || (i == 0 && data == 0)) { /* 0xc14, 0xc1c ==> index=0 */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s =>path:%s Restore RX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B")); - bResult = FAIL; - break; - } - //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); - ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data); - } - - if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] ==0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s => Restore Path-A TxLOK result failed\n", __func__)); - bResult = FAIL; - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); - } - - if (bResult == SUCCESS) - goto out; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(bReCovery) -#else//for ODM_WIN - if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - goto out; - } - StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - - //save default GNT_BT - GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); - // Save RF Path -// Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); -// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); - - //set GNT_BT=0, pause BT traffic -// ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); -// ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x1); - - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i=0; i<3; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path); -#else - phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path); -#endif - - if(i == 1) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); -#endif - if(is12simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if(i == 2) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); -#endif - if(is13simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); -#endif - if(is23simular) - { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); - } - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value - } - -#if MP_DRIVER == 1 - if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) -#endif - { - if (RegE94 != 0) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#else - _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); -#endif - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if MP_DRIVER == 1 - if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) -#endif - { - if (RegEB4 != 0) - { - _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - } - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if(final_candidate < 4) - { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - //restore GNT_BT - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default); - // Restore RF Path -// ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); - - //Resotr RX mode table parameter - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd ); - - //set GNT_BT= HW control -// ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); -// ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0); - - if (Is2ant) { - if (RF_Path == 0x0) //S1 - ODM_SetIQCbyRFpath(pDM_Odm, 0); - else //S0 - ODM_SetIQCbyRFpath(pDM_Odm, 1); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); - -out: - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); -} - - -VOID -PHY_LCCalibrate_8723B( - PVOID pDM_VOID - ) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - u4Byte StartTime; - s4Byte ProgressingTime; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - - - - -#if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#if DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - StartTime = ODM_GetCurrentTime( pDM_Odm); - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - - phy_LCCalibrate_8723B(pDM_Odm, FALSE); - - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); -} - -VOID -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_2T2R( pHalData->VersionID)){ - phy_APCalibrate_8723B(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8723B(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); -#endif - } -} -VOID phy_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if(bMain) // Left antenna - { - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); - } - else - { - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); - } -} -VOID PHY_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); -#endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion8723B( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8723B( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; - - if(pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_2T2R( pHalData->VersionID)){ - phy_DigitalPredistortion8723B(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion8723B(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) - return TRUE; - else - return FALSE; - -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); -#endif - -} -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8723B 6 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] +#define PATH_S0 1 // RF_PATH_B +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 +#define IDX_0xC14 0 +#define IDX_0xCA0 1 +#define KEY 0 +#define VAL 1 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] +#define PATH_S1 0 // RF_PATH_A +#define IDX_0xC9C 0 +#define IDX_0xC88 1 +#define IDX_0xC4C 2 +#define IDX_0xC1C 0 +#define IDX_0xC78 1 + + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8723B( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A=0, ele_D, ele_C=0, value32; + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE-1; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + //new element A = element D x X + if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + + //if (RFPath == ODM_RF_PATH_A) + switch (RFPath) + { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } + else + { + switch (RFPath) + { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + + +VOID +setCCKFilterCoefficient( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +) +{ + if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); + } +} + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ +#if 0 // mark by Lucas@SD4 20140128, suggested by Allen@SD3 + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE); +#else + PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE); +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +#endif // #if 0 +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 34; //+0dB + u1Byte PwrTrackingLimit_CCK= 28; //-2dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = 28; //-2dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM= 36; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit_OFDM= 34; //+2dB + + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM= 38; //+4dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM= 36; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM= 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/ + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) + { + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + if (pDM_Odm->mp_mode == TRUE) + { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } + else + { + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); + } +#endif + } + else if (Method == BBSWING) + { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + // Adjust BB swing by OFDM IQ matrix + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index <= 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck <= 0) + Final_CCK_Swing_Index = 0; + + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", + PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index <= 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + setIqkMatrix_8723B(pDM_Odm, 0, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + + if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } + else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0 + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + setCCKFilterCoefficient(pDM_Odm, 0); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } + else + { + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n")); + } + } + } + else + { + return; // This method is not supported. + } +} + +VOID +GetDeltaSwingTable_8723B( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; + pConfig->RfPathCount = MAX_PATH_NUM_8723B; + pConfig->ThermalRegAddr = RF_T_METER_8723B; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; + pConfig->DoIQK = DoIQK_8723B; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB, + IN u1Byte RF_Path + ) +{ + u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; + u1Byte result = 0x00; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + // Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // enable path A PA in TXIQK mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); + // disable path B PA in TXIQK mode +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 ); + + //1 Tx IQK + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + //path-A IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //Ant switch + if (configPathB || (RF_Path == 0)) + // wifi switch to S1 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + // wifi switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); + //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB, + IN u1Byte RF_Path + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp, Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + // Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n")); + //1 Get TXIMR setting + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + //LNA2 off, PA on for Dcut + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //Ant switch + if (configPathB || (RF_Path == 0)) + // wifi switch to S1 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + // wifi switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); + //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n")); + + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); + //LAN2 on, PA off for Dcut + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); + + //PA, PAD setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f ); + + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //Ant switch + if (configPathB || (RF_Path == 0)) + // wifi switch to S1 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else + // wifi switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 ); + + /* Allen 20141201 */ + tmp=(regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)&& + (((regEA4 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + else //if Tx not OK, ignore Rx + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + // Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // in TXIQK mode +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); + // enable path B PA in TXIQK mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); + + + + //1 Tx IQK + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + //path-A IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //switch to path B + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + + return result; + +#if 0 + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + +#endif +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); + + // Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //switch to path B + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n")); + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 ); + //open PA S1 & SMIXER + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd ); + + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f ); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //switch to path B + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path B TXIQK @ RXIQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n")); + + //modify RXIQK mode table + //<20121009, Kordan> RF Mode = 3 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); + + //open PA S1 & close SMIXER + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); + + //PA, PAD setting +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); + + + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //switch to path B + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); + + //GNT_BT = 0 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); + //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //restore Ant Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB); + //GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x00000000); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 ); + + + +#if 0 + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + + /* Allen 20141201 */ + tmp=(regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36) && + (((regEA4 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //2 Tx IQC + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); + + // <20130226, Kordan> Saving RxIQC, otherwise not initialized. + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; +// pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + + //2 Rx IQC + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + + } +} + +VOID +_PHY_PathBFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + + //2 Tx IQC + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); +// pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; +// pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if(bTxOnly) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; +// pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + return; + } + + //2 Rx IQC + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][7] >> 6) & 0xF; +// ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(ODM_GetBBReg(pDM_Odm,rOFDM0_RxIQExtAnta, bMaskDWord)& 0x0fffffff); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c + +VOID +ODM_SetIQCbyRFpath( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RFpath + ) +{ + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)&& + (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) + { + if(RFpath) //S1: RFpath = 0, S0:RFpath = 1 + { + //S0 TX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); + //S0 RX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); + } + else + { + //S1 TX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); + //S1 RX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); + } + } +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s/%d/%d\n", + rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; + if(FALSE == is2T){ + pathOn = 0x01c00014; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0); +//Allen + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); +// + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); +} + +VOID +_PHY_PIModeSwitch8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +//#else + BOOLEAN is2T = TRUE; +//#endif + + s4Byte tmp1 = 0,tmp2 = 0; + + if(is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + + if((i==1) || (i==3) || (i==5) || (i==7)) + { + if((result[c1][i]& 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if((result[c2][i]& 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } + else + { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + + u4Byte Path_SEL_BB; +// u4Byte Path_SEL_BB, Path_SEL_RF; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 1; +#else + const u4Byte retryCount = 2; +#endif +#endif + +if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n", __func__)); + return; +} + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + +//no serial mode +#if 0 + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch8723B(pAdapter, TRUE); +#else + _PHY_PIModeSwitch8723B(pDM_Odm, TRUE); +#endif + } +#endif + + //save RF path for 8723B +// Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); +// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + +//for 8723B +#if 0 + if(is2T) + { + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } +#endif + + +//no APK +#if 0 + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } +#endif + +//RX IQ calibration setting for 8723B D cut large current issue when leaving IPS + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); +/* +//LOK RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); +*/ + + +//path A TX IQK +#if 1 + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path); +#else + PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01){ + // Path A Tx IQK Success + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } +#endif + +//path A RXIQK +#if 1 + + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path); +#else + PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path); +#endif + if(PathAOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + } +#endif + +//path B IQK +#if 1 + + if(is2T){ + +/* +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// _PHY_PathAStandBy8723B(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T); +#else +// _PHY_PathAStandBy8723B(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif +*/ + +//path B TX IQK +#if 1 + for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8723B(pAdapter); +#else + PathBOK = phy_PathB_IQK_8723B(pDM_Odm); +#endif +// if(PathBOK == 0x03){ + if(PathBOK == 0x01){ + // Path B Tx IQK Success + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } +#if 0 + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } +#endif + +//path B RX IQK +#if 1 + +for(i = 0 ; i < retryCount ; i++){ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T); +#else + PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T); +#endif + if(PathBOK == 0x03){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); + } + } + +#endif + +////////Allen end ///////// + if(0x00 == PathBOK){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + } +#endif //pathB IQK + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + + if(t!=0) + { + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// _PHY_PIModeSwitch8723B(pAdapter, FALSE); +#else +// _PHY_PIModeSwitch8723B(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + //Reload RF path +// ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); + + //Allen initial gain 0xc50 + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if(is2T){ + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n")); + +} + + +VOID +phy_LCCalibrate_8723B( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n", __func__)); + return; + } + + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF + + // Channel 10 LC calibration issue for 8723bs with 26M xtal + if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); + } + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == ODM_RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } + else if(path == ODM_RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == ODM_RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + if(path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if(path == ODM_RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + +//IQK version:V2.5 20140123 +//IQK is controlled by Is2ant, RF path +VOID +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore, + IN BOOLEAN Is2ant, //false:1ant, true:2-ant + IN u1Byte RF_Path //0:S1, 1:S0 + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; +// u4Byte Path_SEL_BB = 0; + u4Byte GNT_BT_default; + u4Byte StartTime; + s4Byte ProgressingTime; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + if (bRestore) { + u4Byte offset, data; + u1Byte path, bResult = SUCCESS; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + //#define PATH_S0 1 // RF_PATH_B + //#define PATH_S1 0 // RF_PATH_A + + path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B); + + // Restore TX IQK + for (i = 0; i < 3; ++i) { + offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; + if ((offset == 0) || (i == 1 && data == 0)) { /* 0xc80, 0xc88 ==> index=1 */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s =>path:%s Restore TX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B")); + bResult = FAIL; + break; + } + //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); + ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data); + } + + // Restore RX IQK + for (i = 0; i < 2; ++i) { + offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; + if ((offset == 0) || (i == 0 && data == 0)) { /* 0xc14, 0xc1c ==> index=0 */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s =>path:%s Restore RX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B")); + bResult = FAIL; + break; + } + //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); + ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data); + } + + if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] ==0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("%s => Restore Path-A TxLOK result failed\n", __func__)); + bResult = FAIL; + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); + } + + if (bResult == SUCCESS) + goto out; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_WIN + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + goto out; + } + StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + + //save default GNT_BT + GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); + // Save RF Path +// Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); +// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); + + //set GNT_BT=0, pause BT traffic +// ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); +// ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x1); + + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i=0; i<3; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path); +#else + phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path); +#endif + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) +#endif + { + if (RegE94 != 0) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE)) +#endif + { + if (RegEB4 != 0) + { + _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + //restore GNT_BT + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default); + // Restore RF Path +// ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); + + //Resotr RX mode table parameter + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd ); + + //set GNT_BT= HW control +// ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0); +// ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0); + + if (Is2ant) { + if (RF_Path == 0x0) //S1 + ODM_SetIQCbyRFpath(pDM_Odm, 0); + else //S0 + ODM_SetIQCbyRFpath(pDM_Odm, 1); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); + +out: + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); +} + + +VOID +PHY_LCCalibrate_8723B( + PVOID pDM_VOID + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + u4Byte StartTime; + s4Byte ProgressingTime; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + + + + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + StartTime = ODM_GetCurrentTime( pDM_Odm); + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + + phy_LCCalibrate_8723B(pDM_Odm, FALSE); + + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); +} + +VOID +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_2T2R( pHalData->VersionID)){ + phy_APCalibrate_8723B(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8723B(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); +#endif + } +} +VOID phy_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if(bMain) // Left antenna + { + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); + } + else + { + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); + } +} +VOID PHY_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion8723B( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8723B( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_2T2R( pHalData->VersionID)){ + phy_DigitalPredistortion8723B(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion8723B(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) + return TRUE; + else + return FALSE; + +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); +#endif + +} +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.h index 2f48325b313..feb77d869eb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_ce.h @@ -1,134 +1,134 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8723B_H__ -#define __HAL_PHY_RF_8723B_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8723B 20 //ms -#define IQK_DEFERRED_TIME_8723B 4 -#define index_mapping_NUM_8723B 15 -#define AVG_THERMAL_NUM_8723B 4 -#define RF_T_METER_8723B 0x42 // - - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery, - IN BOOLEAN bRestore, - IN BOOLEAN Is2ant, - IN u1Byte RF_Path); - -VOID -ODM_SetIQCbyRFpath( -//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -//#else - //IN PADAPTER pAdapter, -//#endif - IN u4Byte RFpath - ); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8723B( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723B_H__ +#define __HAL_PHY_RF_8723B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8723B 20 //ms +#define IQK_DEFERRED_TIME_8723B 4 +#define index_mapping_NUM_8723B 15 +#define AVG_THERMAL_NUM_8723B 4 +#define RF_T_METER_8723B 0x42 // + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore, + IN BOOLEAN Is2ant, + IN u1Byte RF_Path); + +VOID +ODM_SetIQCbyRFpath( +//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +//#else + //IN PADAPTER pAdapter, +//#endif + IN u4Byte RFpath + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8723B( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.c b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.c index 8e5b1abb970..c10d96072f6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.c @@ -1,3975 +1,3975 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8723B 6 - -// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] -#define PATH_S0 1 // RF_PATH_B -#define IDX_0xC94 0 -#define IDX_0xC80 1 -#define IDX_0xC4C 2 -#define IDX_0xC14 0 -#define IDX_0xCA0 1 -#define KEY 0 -#define VAL 1 - -// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] -#define PATH_S1 0 // RF_PATH_A -#define IDX_0xC9C 0 -#define IDX_0xC88 1 -#define IDX_0xC4C 2 -#define IDX_0xC1C 0 -#define IDX_0xC78 1 - - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void setIqkMatrix_8723B( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - s4Byte IqkResultS1_X, - s4Byte IqkResultS1_Y, - s4Byte IqkResultS0_X, - s4Byte IqkResultS0_Y - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - s4Byte ele_A=0, ele_D, ele_C=0, value32; - s4Byte ele_A_ext = 0, ele_C_ext = 0; - u1Byte RFPath = ODM_RF_PATH_A; - - if(pDM_Odm->mp_mode) - { - // MP driver => Check which antenna is using now - value32 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskLWord); - if(value32 == 0x280 || value32 == 0x80) - RFPath = ODM_RF_PATH_B; - } - else - { - // If Dual Antenna && Antenna diversity change antenna to S0 (path B) => Change RFPath to pathB - // If USB interface or efuse 0xc3 = 51(1-ant , path B) ==> swith to pathB - if(((*pDM_Odm->pIs1Antenna == TRUE)&&(*pDM_Odm->pRFDefaultPath == 1))||(pDM_Odm->SupportInterface == ODM_ITRF_USB) - ||((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && (pDM_FatTable->RxIdleAnt == AUX_ANT))) - RFPath = ODM_RF_PATH_B; - } - - - if (OFDM_index >= OFDM_TABLE_SIZE) - OFDM_index = OFDM_TABLE_SIZE-1; - else if (OFDM_index < 0) - OFDM_index = 0; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - // S1------------------------------------- - if ((IqkResultS1_X & 0x00000200) != 0) //consider minus - IqkResultS1_X = IqkResultS1_X | 0xFFFFFC00; - ele_A = ((IqkResultS1_X * ele_D)>>8)&0x000003FF; - ele_A_ext = ((IqkResultS1_X * ele_D)>>7) & 0x1; - - if ((IqkResultS1_Y & 0x00000200) != 0) - IqkResultS1_Y = IqkResultS1_Y | 0xFFFFFC00; - ele_C = ((IqkResultS1_Y * ele_D)>>8)&0x000003FF; - ele_C_ext = ((IqkResultS1_Y * ele_D)>>7) & 0x1; - - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = value32; - - value32 = ((ele_C&0x000003C0)>>6)<<28; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = - (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] & (~(bMaskH4Bits))) | value32; - - value32 = ((((IqkResultS1_X * ele_D)>>7)&0x01)<<28) | (ele_A_ext << 31) | (ele_C_ext << 29) ; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = - (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & (~(BIT31|BIT29|BIT28))) | value32; - - - // S0------------------------------------- - if(pDM_Odm->mp_mode || (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) || ((*pDM_Odm->pIs1Antenna == TRUE)&&(*pDM_Odm->pRFDefaultPath == 1)) - || (pDM_Odm->SupportInterface == ODM_ITRF_USB) || (*pDM_Odm->pIs1Antenna == FALSE)) - { - ele_A=0; - ele_C=0; - - if ((IqkResultS0_X & 0x00000200) != 0) //consider minus - IqkResultS0_X = IqkResultS0_X | 0xFFFFFC00; - ele_A = ((IqkResultS0_X * ele_D)>>8)&0x000003FF; - ele_A_ext = ((IqkResultS0_X * ele_D)>>7) & 0x1; - - if ((IqkResultS0_Y & 0x00000200) != 0) - IqkResultS0_Y = IqkResultS0_Y | 0xFFFFFC00; - ele_C = ((IqkResultS0_Y * ele_D)>>8)&0x000003FF; - ele_C_ext = ((IqkResultS0_Y * ele_D)>>7) & 0x1; - - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = value32; - - value32 = ((ele_C&0x000003C0)>>6)<<28; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = - (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] & (~(bMaskH4Bits))) | value32; - - value32 = ((((IqkResultS0_X * ele_D)>>7)&0x01)<<28) | (ele_A_ext << 31) | (ele_C_ext << 29) ; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = - (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & (~(BIT31|BIT29|BIT28))) | value32; - } - - //Set register by path------------------------------ - if((((IqkResultS1_X != 0) && (RFPath == ODM_RF_PATH_A)) || - ((IqkResultS0_X != 0) && (RFPath == ODM_RF_PATH_B))) && - (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - switch (RFPath) - { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - // for 8723B S1 - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL])>>28)); - - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - value32 = (value32 & (~(BIT31|BIT29|BIT28))) | (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & (BIT31|BIT29|BIT28)); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - case ODM_RF_PATH_B: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - // for 8723B S0 - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL])>>28)); - - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - value32 = (value32 & (~(BIT31|BIT29|BIT28))) | (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & (BIT31|BIT29|BIT28)); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - default: - break; - } - } - else - { - // default IQK value (if current Antenna has default IQK value) - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); - value32 = (value32 & (~(BIT31|BIT29|BIT28))); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - } -} - - -VOID -setCCKFilterCoefficient( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - if(!pRFCalibrateInfo->bCCKinCH14) - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); - } - else - { - ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); - ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); - ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); - ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); - ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); - ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); - ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); - ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); - } -} - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_ResetIQKResult(pDM_Odm); - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8723B(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8723B(Adapter, FALSE); -#endif - - -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - u1Byte PwrTrackingLimit_OFDM = 34; //+0dB - u1Byte PwrTrackingLimit_CCK= 28; //-2dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit_CCK = 28; //-2dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM= 36; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit_OFDM= 34; //+2dB - - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit_OFDM= 38; //+4dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit_OFDM= 36; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit_OFDM= 34; //+2dB - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); - - if (Method == TXAGC) - { - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) -#if (MP_DRIVER != 1) - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); -#else - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[RFPath]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); -#endif -#endif - } - else if (Method == BBSWING) - { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - // Adjust BB swing by OFDM IQ matrix - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) - Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; - else if (pRFCalibrateInfo->BbSwingIdxCck < 0) - Final_CCK_Swing_Index = 0; - - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", - PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index < 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8723B(pDM_Odm, 0, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - - if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } - else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0 - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - setCCKFilterCoefficient(pDM_Odm, 0); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - } - else - { - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK= FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); - } - } - } - else - { - return; // This method is not supported. - } -} - -VOID -GetDeltaSwingTable_8723B( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; - pConfig->RfPathCount = MAX_PATH_NUM_8723B; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; - pConfig->DoIQK = DoIQK_8723B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regE94, regE9C, Path_SEL_BB/*, regEA4*/; - u1Byte result = 0x00; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 TX IQK!\n")); - //save RF path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - //1 Tx IQK - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // enable path A PA in TXIQK mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - //RF switch to S1 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x764 when IQK= 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord))); - - //One shot, path A LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x764 after IQK= 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord))); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - - return result; - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - } - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp,Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - //save RF path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 RX IQK:Get TXIMR setting\n")); - //1 Get TXIMR setting - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //modify RXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - //S1 IQK PA off -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7df7); - //S0 IQK PA off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fed); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60efd); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); - - //One shot, path A LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - //Allen 20141201 - tmp=(regE9C & 0x03FF0000)>>16; - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) && - (((regE94 & 0x03FF0000)>>16) <0x11a) && - (((regE94 & 0x03FF0000)>>16) >0xe6) && - (tmp <0x1a)) - - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 RX IQK\n")); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816081f); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - - //modify RXIQK mode table - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); - //S1 PA off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); - - //S1 PA, PAD setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x40207 ); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //switch to S1 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); - - //One shot, path A LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - // PA/PAD controlled by 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 ); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - //Allen 20131125 - tmp=(regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)&& - (((regEA4 & 0x03FF0000)>>16) < 0x110) && - (((regEA4 & 0x03FF0000)>>16) > 0xf0) && - (tmp <0xf)) - result |= 0x02; - else //if Tx not OK, ignore Rx - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regE94, regE9C, Path_SEL_BB/*, regEC4, regECC*/; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 TX IQK!\n")); - - //save RF path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - //1 Tx IQK - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // enable path B PA in TXIQK mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //RF switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); - - //One shot, path B LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - - return result; - -#if 0 - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - -#endif -} - - - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_RxIQK8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - //save RF path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - - //1 Get TXIMR setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 RX IQK:Get TXIMR setting!\n")); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - -// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f ); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //modify RXIQK mode table - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); - //S1 IQK PA off -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7df7); - //S0 IQK PA off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fed ); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60efd); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //RF switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); - - - //One shot, path B TXIQK @ RXIQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - //Allen 20131125 - tmp=(regE9C & 0x03FF0000)>>16; - - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) && - (((regE94 & 0x03FF0000)>>16) <0x11a) && - (((regE94 & 0x03FF0000)>>16) >0xe6) && - (tmp <0x1a)) - result |= 0x01; - else //if Tx not OK, ignore Rx - { - return result; - } - - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - //1 RX IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 RX IQK\n")); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-B IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816081f); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); - - //LO calibration setting - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - //modify RXIQK mode table - //<20121009, Kordan> RF Mode = 3 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - //S1 PA off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); - //S0 PA off - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); - - //PA, PAD setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdd, bRFRegOffsetMask, 0x5c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x75, bRFRegOffsetMask, 0xe1007); - - //enter IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - //switch to S0 - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - //set GNT_BT=0, pause BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); - - //One shot, path B LOK & IQK - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_delay_ms(IQK_DELAY_TIME_8723B); - - //set GNT_BT=1, enable BT traffic - ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); - - //reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - //leave IQK mode - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - // PA/PAD controlled by 0x0 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdd, bRFRegOffsetMask, 0x4c ); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - //monitor image power before & after IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - -#if 0 - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - - //Allen 20131125 - tmp=(regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200)> 0) - tmp = 0x400 - tmp; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36) && - (((regEA4 & 0x03FF0000)>>16) <0x110) && - (((regEA4 & 0x03FF0000)>>16) >0xf0) && - (tmp <0xf)) - - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK fail!!\n")); - - return result; -} - - -VOID -_PHY_PathAFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00)| (TX0_A & 0x3ff); - tmp0xc4c = (((X* Oldval_0>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - //2 Tx IQC - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - - tmp0xc94 = (((TX0_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); - - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = tmp0xc94; - - tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F)<<16; - - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = tmp0xc80; - - tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_0>>7) & 0x1)<<29); - - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = tmp0xc4c; - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); - - // <20130226, Kordan> Saving RxIQC, otherwise not initialized. - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - - //2 Rx IQC - tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; - - reg = result[final_candidate][3] & 0x3F; - tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = tmp0xc14; - - reg = (result[final_candidate][3] >> 6) & 0xF; - tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = tmp0xca0; - } -} - -VOID -_PHY_PathBFillIQKMatrix8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - - tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00)| (TX1_A & 0x3ff); - tmp0xc4c = (((X* Oldval_1>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - - //2 Tx IQC - - tmp0xc94 = (((TX1_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); - - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = tmp0xc94; - - tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C&0x3F)<<16; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = tmp0xc80; - - tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_1>>7) & 0x1)<<29); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = tmp0xc4c; - - if(bTxOnly) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); - return; - } - - //2 Rx IQC - reg = result[final_candidate][6]; - tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; - - reg = result[final_candidate][7] & 0x3F; - tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = tmp0xc14; - - reg = (result[final_candidate][7] >> 6) & 0xF; - tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); - - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = tmp0xca0; - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c - -BOOLEAN -ODM_SetIQCbyRFpath( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RFpath - ) -{ - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if(RFpath) //S1: RFpath = 0, S0:RFpath = 1 - { - if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)) - { - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RF S0 IQC!!!\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL])); - - //S0 TX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]>>28)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]>>31)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & BIT29)>>29)); - - //S0 RX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); - return TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQC S0 vaule invalid!!!\n")); - return FALSE; - } - } - else - { - if((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RF S1 IQC!!!\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL])); - - //S1 TX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]>>28)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]>>31)); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & BIT29)>>29)); - - - //S1 RX IQC - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); - ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); - return TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQC S1 vaule invalid!!!\n")); - return FALSE; - } - } -} - -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; - if( TRUE == *pDM_Odm->pIs1Antenna){ - pathOn = 0x01c00014; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID -_PHY_PathAStandBy8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); -//Allen - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); -// - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PIModeSwitch8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -//#else - BOOLEAN is2T = TRUE; -//#endif - - s4Byte tmp1 = 0,tmp2 = 0; - - if(is2T) - bound = 8; - else - bound = 4; - -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - - if((i==1) || (i==3) || (i==5) || (i==7)) - { - if((result[c1][i]& 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if((result[c2][i]& 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } - else - { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) - { -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte i; - u1Byte PathAOK, PathBOK; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - - u4Byte Path_SEL_BB, tmp0x764; -// u4Byte Path_SEL_BB, Path_SEL_RF; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 1; -#else - const u4Byte retryCount = 2; -#endif -#endif - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - //u4Byte bbvalue; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#ifdef MP_TEST - if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if(t==0) - { -// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); -// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s for %d times\n", (*pDM_Odm->pIs1Antenna ? "1ant" : "2ant"), t)); - if(*pDM_Odm->pIs1Antenna) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s\n", (*pDM_Odm->pRFDefaultPath ? "S0" : "S1"))); - - // Save ADDA parameters, turn Path A ADDA on -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s for %d times\n", (*pDM_Odm->pIs1Antenna ? "1ant" : "2ant"), t)); - if(*pDM_Odm->pIs1Antenna) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s\n", (*pDM_Odm->pRFDefaultPath ? "S0" : "S1"))); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE); -#else - _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE); -#endif - -//no serial mode -#if 0 - if(t==0) - { - pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pRFCalibrateInfo->bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch8723B(pAdapter, TRUE); -#else - _PHY_PIModeSwitch8723B(pDM_Odm, TRUE); -#endif - } -#endif - - //save RF path for 8723B - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - //save 0x764 GNT_BT - tmp0x764 = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); - -// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); -#else - _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); -#endif - - //BB setting - //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - - -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); -// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - - -//for 8723B -#if 0 - if(is2T) - { - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } -#endif - - -//no APK -#if 0 - //Page B init - //AP or IQK - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - - if(is2T) - { - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); - } -#endif - -//RX IQ calibration setting for 8723B D cut large current issue when leaving IPS - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); -/* -//LOK RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); -*/ - - -//path A TX IQK -#if 1 - -#if MP_DRIVER != 1 - if((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE)&& (pDM_Odm->SupportInterface != ODM_ITRF_USB) - && (*pDM_Odm->pRFDefaultPath == 0)) ) -#endif - { - - for(i = 0 ; i < retryCount ; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_IQK_8723B(pAdapter); -#else - PathAOK = phy_PathA_IQK_8723B(pDM_Odm); -#endif -// if(PathAOK == 0x03){ - if(PathAOK == 0x01) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - - } -#endif - -//path A RXIQK -#if 1 - - for(i = 0 ; i < retryCount ; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathAOK = phy_PathA_RxIQK8723B(pAdapter); -#else - PathAOK = phy_PathA_RxIQK8723B(pDM_Odm); -#endif - if(PathAOK == 0x03) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1Rx IQK Fail!!\n")); - } - } - - if(0x00 == PathAOK) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 IQK failed!!\n")); - } - } -#endif - -//path B TX IQK - -/* -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// _PHY_PathAStandBy8723B(pAdapter); - - // Turn Path B ADDA on - _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T); -#else -// _PHY_PathAStandBy8723B(pDM_Odm); - - // Turn Path B ADDA on - _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif -*/ - -//path B TX IQK -#if 1 - -#if MP_DRIVER != 1 - if((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) - || (pDM_Odm->SupportInterface == ODM_ITRF_USB)) -#endif - { - - for(i = 0 ; i < retryCount ; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_IQK_8723B(pAdapter); -#else - PathBOK = phy_PathB_IQK_8723B(pDM_Odm); -#endif -// if(PathBOK == 0x03){ - if(PathBOK == 0x01) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } - - } -#endif - -//path B RX IQK -#if 1 - - for(i = 0 ; i < retryCount ; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathBOK = phy_PathB_RxIQK8723B(pAdapter); -#else - PathBOK = phy_PathB_RxIQK8723B(pDM_Odm); -#endif - if(PathBOK == 0x03) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Success!!\n")); -// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; -// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Fail!!\n")); - } - } - -#endif - - if(0x00 == PathBOK) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if(t!=0) - { - if(!pRFCalibrateInfo->bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// _PHY_PIModeSwitch8723B(pAdapter, FALSE); -#else -// _PHY_PIModeSwitch8723B(pDM_Odm, FALSE); -#endif - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#else - // Reload ADDA power saving parameters - _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); - - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - //Reload RF path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - //reload 0x764 GNT_BT - ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, tmp0x764); - -// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); - - //Allen initial gain 0xc50 - // Restore RX initial gain - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if(*pDM_Odm->pIs1Antenna == FALSE){ - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - //load 0xe30 IQC default value - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]phy_IQCalibrate_8723B() <==\n")); - -} - - -VOID -phy_LCCalibrate_8723B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF - - // Channel 10 LC calibration issue for 8723bs with 26M xtal - if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); - } - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == ODM_RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - else if(path == ODM_RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#endif - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == ODM_RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pRFCalibrateInfo->bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if(path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if(path == ODM_RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pRFCalibrateInfo->bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - -// IQK version:V2.9 20141201 -// 1. modify the boundary of IQK result for 8723B F-cut - -VOID -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - - u1Byte u1bTmp; - u2Byte count=0; -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - u4Byte Path_SEL_BB = 0; - BOOLEAN bReloadIQK = FALSE; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if(priv->pshare->rf_ft_var.mp_specific) - { - if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if(priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - - -#if MP_DRIVER == 1 - // Add to determine IQK ON/OFF in certain case, Suggested by Cheng. - if (!pHalData->IQK_MP_Switch) - return; - - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; -#endif - - -#if DISABLE_BB_RF - return; -#endif - - - if (pRFCalibrateInfo->bIQKInProgress) - return; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(bReCovery) -#else//for ODM_WIN - if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#endif - return; - } - - - -#if MP_DRIVER != 1 -//check if IQK had been done before!! - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 0xc80 = 0x%x, S0 0xc80 = 0x%x\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL], pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL])); - - if((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 0)) // 1-ant, S1 - { - if(ODM_SetIQCbyRFpath(pDM_Odm, 0)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]1-ant S1 IQK value is reloaded!!!\n")); - bReloadIQK = TRUE; - } - } - else if((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) // 1-ant, S0 - { - if(ODM_SetIQCbyRFpath(pDM_Odm, 1)) // S0 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]1-ant S0 IQK value is reloaded!!!\n")); - bReloadIQK = TRUE; - } - } - else // 2-ant - { - if((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK has been done before.!!!\n")); - - if((Path_SEL_BB == 0x0) || (Path_SEL_BB == 0x200)) //S1 - { - if(ODM_SetIQCbyRFpath(pDM_Odm, 0)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]2-ant S1 IQK value is reloaded!!!\n")); - bReloadIQK = TRUE; - } - } - else // S0 - { - if(ODM_SetIQCbyRFpath(pDM_Odm, 1)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]2-ant S0 IQK value is reloaded!!!\n")); - bReloadIQK = TRUE; - } - } - } - } - - if(bReloadIQK) - return; -#endif - - //Check & wait if BT is doing IQK -#if MP_DRIVER != 1 - // Set H2C cmd to inform FW (enable). - SetFwWiFiCalibrationCmd_8723B(pAdapter, 1); - - // Check 0x1e6 - count=0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while(u1bTmp != 0x1 && count<1000) - { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - - if(count >= 1000) - { - RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - } - - // Wait BT IQK finished. - // polling 0x1e7[0]=1 or 300ms timeout - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - while((!(u1bTmp&BIT0)) && count<6000) - { - PlatformStallExecution(50); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - count++; - } -#endif - - -// Save RF Path - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948 = 0x%x\n", Path_SEL_BB)); - - - //IQK start!!!!!!!!!! - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Start!!!\n")); - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - - for (i=0; i<3; i++) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_IQCalibrate_8723B(pAdapter, result, i); -#else - phy_IQCalibrate_8723B(pDM_Odm, result, i); -#endif - - - if(i == 1) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); -#endif - if(is12simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if(i == 2) - { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); -#endif - if(is13simular) - { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); -#endif - if(is23simular) - { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is23simular final_candidate is %x\n",final_candidate)); - } - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; - pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; - pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: final_candidate is %x\n",final_candidate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: FAIL use default value\n")); - pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value - pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value - } - - // fill IQK matrix - if (RegE94 != 0) - _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - if (RegEB4 != 0) - _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 - if(final_candidate < 4) - { - for(i = 0; i < IQK_Matrix_REG_NUM; i++) - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]\nIQK OK Indexforchannel %d.\n", Indexforchannel)); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - // Restore RF Path - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]is1ant = %d, supprotinterface = %d, RFdefaultpath=%d.\n",*pDM_Odm->pIs1Antenna, pDM_Odm->SupportInterface, *pDM_Odm->pRFDefaultPath )); - -//fill IQK register -#if MP_DRIVER == 1 - if((Path_SEL_BB == 0x0) || (Path_SEL_BB == 0x200)) //S1 - ODM_SetIQCbyRFpath( pDM_Odm, 0); - else - ODM_SetIQCbyRFpath( pDM_Odm, 1); -#else - if(*pDM_Odm->pRFDefaultPath == 0x0 ) //S1 - ODM_SetIQCbyRFpath( pDM_Odm, 0); - else - ODM_SetIQCbyRFpath( pDM_Odm, 1); -#endif - - -#if MP_DRIVER != 1 - // Set H2C cmd to inform FW (disable). - SetFwWiFiCalibrationCmd_8723B(pAdapter, 0); - - // Check 0x1e6 - count = 0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while(u1bTmp != 0 && count<1000) - { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - - if(count >= 1000) - { - RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - } -#endif - - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK finished\n")); -} - - -VOID -PHY_LCCalibrate_8723B( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - - -#if MP_DRIVER == 1 - // Add to Disable Default LCK when Cont Tx, For Lab Test Usage. - if (!pHalData->IQK_MP_Switch) - return; - - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#if DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pRFCalibrateInfo->bLCKInProgress = TRUE; - - - phy_LCCalibrate_8723B(pDM_Odm, FALSE); - - - pRFCalibrateInfo->bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pRFCalibrateInfo->bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8723B(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8723B(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); -#endif - } -} -VOID phy_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - if(bMain) // Left antenna - { - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); - } - else - { - ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); - } -} -VOID PHY_SetRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); -#endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID -phy_DigitalPredistortion8723B( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pRFCalibrateInfo->bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pRFCalibrateInfo->bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pRFCalibrateInfo->bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pRFCalibrateInfo->bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexbDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8723B( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if DISABLE_BB_RF - return; -#endif - - return; - - if(pRFCalibrateInfo->bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_DigitalPredistortion8723B(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion8723B(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - -BOOLEAN phy_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) - return TRUE; - else - return FALSE; - -} - - - -//return value TRUE => Main; FALSE => Aux -BOOLEAN PHY_QueryRFPathSwitch_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); -#endif - -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8723B 6 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] +#define PATH_S0 1 // RF_PATH_B +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 +#define IDX_0xC14 0 +#define IDX_0xCA0 1 +#define KEY 0 +#define VAL 1 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] +#define PATH_S1 0 // RF_PATH_A +#define IDX_0xC9C 0 +#define IDX_0xC88 1 +#define IDX_0xC4C 2 +#define IDX_0xC1C 0 +#define IDX_0xC78 1 + + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8723B( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + s4Byte IqkResultS1_X, + s4Byte IqkResultS1_Y, + s4Byte IqkResultS0_X, + s4Byte IqkResultS0_Y + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + s4Byte ele_A=0, ele_D, ele_C=0, value32; + s4Byte ele_A_ext = 0, ele_C_ext = 0; + u1Byte RFPath = ODM_RF_PATH_A; + + if(pDM_Odm->mp_mode) + { + // MP driver => Check which antenna is using now + value32 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskLWord); + if(value32 == 0x280 || value32 == 0x80) + RFPath = ODM_RF_PATH_B; + } + else + { + // If Dual Antenna && Antenna diversity change antenna to S0 (path B) => Change RFPath to pathB + // If USB interface or efuse 0xc3 = 51(1-ant , path B) ==> swith to pathB + if(((*pDM_Odm->pIs1Antenna == TRUE)&&(*pDM_Odm->pRFDefaultPath == 1))||(pDM_Odm->SupportInterface == ODM_ITRF_USB) + ||((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && (pDM_FatTable->RxIdleAnt == AUX_ANT))) + RFPath = ODM_RF_PATH_B; + } + + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE-1; + else if (OFDM_index < 0) + OFDM_index = 0; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + // S1------------------------------------- + if ((IqkResultS1_X & 0x00000200) != 0) //consider minus + IqkResultS1_X = IqkResultS1_X | 0xFFFFFC00; + ele_A = ((IqkResultS1_X * ele_D)>>8)&0x000003FF; + ele_A_ext = ((IqkResultS1_X * ele_D)>>7) & 0x1; + + if ((IqkResultS1_Y & 0x00000200) != 0) + IqkResultS1_Y = IqkResultS1_Y | 0xFFFFFC00; + ele_C = ((IqkResultS1_Y * ele_D)>>8)&0x000003FF; + ele_C_ext = ((IqkResultS1_Y * ele_D)>>7) & 0x1; + + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = value32; + + value32 = ((ele_C&0x000003C0)>>6)<<28; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = + (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] & (~(bMaskH4Bits))) | value32; + + value32 = ((((IqkResultS1_X * ele_D)>>7)&0x01)<<28) | (ele_A_ext << 31) | (ele_C_ext << 29) ; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = + (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & (~(BIT31|BIT29|BIT28))) | value32; + + + // S0------------------------------------- + if(pDM_Odm->mp_mode || (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) || ((*pDM_Odm->pIs1Antenna == TRUE)&&(*pDM_Odm->pRFDefaultPath == 1)) + || (pDM_Odm->SupportInterface == ODM_ITRF_USB) || (*pDM_Odm->pIs1Antenna == FALSE)) + { + ele_A=0; + ele_C=0; + + if ((IqkResultS0_X & 0x00000200) != 0) //consider minus + IqkResultS0_X = IqkResultS0_X | 0xFFFFFC00; + ele_A = ((IqkResultS0_X * ele_D)>>8)&0x000003FF; + ele_A_ext = ((IqkResultS0_X * ele_D)>>7) & 0x1; + + if ((IqkResultS0_Y & 0x00000200) != 0) + IqkResultS0_Y = IqkResultS0_Y | 0xFFFFFC00; + ele_C = ((IqkResultS0_Y * ele_D)>>8)&0x000003FF; + ele_C_ext = ((IqkResultS0_Y * ele_D)>>7) & 0x1; + + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = value32; + + value32 = ((ele_C&0x000003C0)>>6)<<28; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = + (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] & (~(bMaskH4Bits))) | value32; + + value32 = ((((IqkResultS0_X * ele_D)>>7)&0x01)<<28) | (ele_A_ext << 31) | (ele_C_ext << 29) ; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = + (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & (~(BIT31|BIT29|BIT28))) | value32; + } + + //Set register by path------------------------------ + if((((IqkResultS1_X != 0) && (RFPath == ODM_RF_PATH_A)) || + ((IqkResultS0_X != 0) && (RFPath == ODM_RF_PATH_B))) && + (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + switch (RFPath) + { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + // for 8723B S1 + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL])>>28)); + + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + value32 = (value32 & (~(BIT31|BIT29|BIT28))) | (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & (BIT31|BIT29|BIT28)); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + // for 8723B S0 + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL])>>28)); + + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + value32 = (value32 & (~(BIT31|BIT29|BIT28))) | (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & (BIT31|BIT29|BIT28)); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + default: + break; + } + } + else + { + // default IQK value (if current Antenna has default IQK value) + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + value32 = (value32 & (~(BIT31|BIT29|BIT28))); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + } +} + + +VOID +setCCKFilterCoefficient( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + if(!pRFCalibrateInfo->bCCKinCH14) + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); + } + else + { + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); + } +} + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_ResetIQKResult(pDM_Odm); + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8723B(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8723B(Adapter, FALSE); +#endif + + +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 34; //+0dB + u1Byte PwrTrackingLimit_CCK= 28; //-2dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit_CCK = 28; //-2dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM= 36; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit_OFDM= 34; //+2dB + + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM= 38; //+4dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM= 36; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM= 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + if (Method == TXAGC) + { + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) +#if (MP_DRIVER != 1) + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); +#else + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[RFPath]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); +#endif +#endif + } + else if (Method == BBSWING) + { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + // Adjust BB swing by OFDM IQ matrix + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) + Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; + else if (pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", + PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8723B(pDM_Odm, 0, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + + if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } + else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0 + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + setCCKFilterCoefficient(pDM_Odm, 0); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + } + else + { + setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK ); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK= FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); + } + } + } + else + { + return; // This method is not supported. + } +} + +VOID +GetDeltaSwingTable_8723B( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_92E; + pConfig->RfPathCount = MAX_PATH_NUM_8723B; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; + pConfig->DoIQK = DoIQK_8723B; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regE94, regE9C, Path_SEL_BB/*, regEA4*/; + u1Byte result = 0x00; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 TX IQK!\n")); + //save RF path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + //1 Tx IQK + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // enable path A PA in TXIQK mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + //RF switch to S1 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x764 when IQK= 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord))); + + //One shot, path A LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x764 after IQK= 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord))); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + } + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp,Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + //save RF path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 RX IQK:Get TXIMR setting\n")); + //1 Get TXIMR setting + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //modify RXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + //S1 IQK PA off +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7df7); + //S0 IQK PA off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fed); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60efd); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); + + //One shot, path A LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + //Allen 20141201 + tmp=(regE9C & 0x03FF0000)>>16; + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) && + (((regE94 & 0x03FF0000)>>16) <0x11a) && + (((regE94 & 0x03FF0000)>>16) >0xe6) && + (tmp <0x1a)) + + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 RX IQK\n")); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816081f); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + + //modify RXIQK mode table + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); + //S1 PA off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 ); + + //S1 PA, PAD setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x40207 ); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //switch to S1 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); + + //One shot, path A LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + // PA/PAD controlled by 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 ); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + //Allen 20131125 + tmp=(regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)&& + (((regEA4 & 0x03FF0000)>>16) < 0x110) && + (((regEA4 & 0x03FF0000)>>16) > 0xf0) && + (tmp <0xf)) + result |= 0x02; + else //if Tx not OK, ignore Rx + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regE94, regE9C, Path_SEL_BB/*, regEC4, regECC*/; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 TX IQK!\n")); + + //save RF path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + //1 Tx IQK + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // enable path B PA in TXIQK mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //RF switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); + + //One shot, path B LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + + return result; + +#if 0 + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + +#endif +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + //save RF path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 RX IQK:Get TXIMR setting!\n")); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + +// ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f ); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //modify RXIQK mode table + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f ); + //S1 IQK PA off +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7df7); + //S0 IQK PA off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fed ); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60efd); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //RF switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); + + + //One shot, path B TXIQK @ RXIQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + //Allen 20131125 + tmp=(regE9C & 0x03FF0000)>>16; + + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) && + (((regE94 & 0x03FF0000)>>16) <0x11a) && + (((regE94 & 0x03FF0000)>>16) >0xe6) && + (tmp <0x1a)) + result |= 0x01; + else //if Tx not OK, ignore Rx + { + return result; + } + + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + //1 RX IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 RX IQK\n")); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +// ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816081f); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + + //LO calibration setting + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + //modify RXIQK mode table + //<20121009, Kordan> RF Mode = 3 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + //S1 PA off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); + //S0 PA off + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd); + + //PA, PAD setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdd, bRFRegOffsetMask, 0x5c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x75, bRFRegOffsetMask, 0xe1007); + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + //switch to S0 + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + //set GNT_BT=0, pause BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x1); + + //One shot, path B LOK & IQK + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_delay_ms(IQK_DELAY_TIME_8723B); + + //set GNT_BT=1, enable BT traffic + ODM_SetBBReg(pDM_Odm, 0x764, BIT12|BIT11, 0x3); + + //reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + //leave IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + // PA/PAD controlled by 0x0 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdd, bRFRegOffsetMask, 0x4c ); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + +#if 0 + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + + //Allen 20131125 + tmp=(regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200)> 0) + tmp = 0x400 - tmp; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36) && + (((regEA4 & 0x03FF0000)>>16) <0x110) && + (((regEA4 & 0x03FF0000)>>16) >0xf0) && + (tmp <0xf)) + + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK fail!!\n")); + + return result; +} + + +VOID +_PHY_PathAFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00)| (TX0_A & 0x3ff); + tmp0xc4c = (((X* Oldval_0>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //2 Tx IQC + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + + tmp0xc94 = (((TX0_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); + + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = tmp0xc94; + + tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F)<<16; + + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = tmp0xc80; + + tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_0>>7) & 0x1)<<29); + + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = tmp0xc4c; + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); + + // <20130226, Kordan> Saving RxIQC, otherwise not initialized. + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + + //2 Rx IQC + tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; + + reg = result[final_candidate][3] & 0x3F; + tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = tmp0xc14; + + reg = (result[final_candidate][3] >> 6) & 0xF; + tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = tmp0xca0; + } +} + +VOID +_PHY_PathBFillIQKMatrix8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + tmp0xc80 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) & 0xfffffc00)| (TX1_A & 0x3ff); + tmp0xc4c = (((X* Oldval_1>>7) & 0x1) << 31 ) | (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord) & 0x7fffffff); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + + //2 Tx IQC + + tmp0xc94 = (((TX1_C&0x3C0)>>6) << 28) | (ODM_GetBBReg(pDM_Odm,rOFDM0_XCTxAFE, bMaskDWord) & 0x0fffffff); + + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = tmp0xc94; + + tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C&0x3F)<<16; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = tmp0xc80; + + tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y* Oldval_1>>7) & 0x1)<<29); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = tmp0xc4c; + + if(bTxOnly) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + return; + } + + //2 Rx IQC + reg = result[final_candidate][6]; + tmp0xc14 = (0x40000100 & 0xfffffc00) | reg; + + reg = result[final_candidate][7] & 0x3F; + tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = tmp0xc14; + + reg = (result[final_candidate][7] >> 6) & 0xF; + tmp0xca0 = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0x0fffffff) | (reg << 28); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = tmp0xca0; + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c + +BOOLEAN +ODM_SetIQCbyRFpath( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RFpath + ) +{ + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if(RFpath) //S1: RFpath = 0, S0:RFpath = 1 + { + if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)) + { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RF S0 IQC!!!\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL])); + + //S0 TX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]>>28)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]>>31)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] & BIT29)>>29)); + + //S0 RX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); + return TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQC S0 vaule invalid!!!\n")); + return FALSE; + } + } + else + { + if((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RF S1 IQC!!!\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL])); + + //S1 TX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskH4Bits, (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]>>28)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], BIT31, (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]>>31)); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], BIT29, ((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] & BIT29)>>29)); + + + //S1 RX IQC + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); + ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); + return TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQC S1 vaule invalid!!!\n")); + return FALSE; + } + } +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; + if( TRUE == *pDM_Odm->pIs1Antenna){ + pathOn = 0x01c00014; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID +_PHY_PathAStandBy8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); +//Allen + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); +// + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PIModeSwitch8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +//#else + BOOLEAN is2T = TRUE; +//#endif + + s4Byte tmp1 = 0,tmp2 = 0; + + if(is2T) + bound = 8; + else + bound = 4; + +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + + if((i==1) || (i==3) || (i==5) || (i==7)) + { + if((result[c1][i]& 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if((result[c2][i]& 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } + else + { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) + { +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte i; + u1Byte PathAOK, PathBOK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + + u4Byte Path_SEL_BB, tmp0x764; +// u4Byte Path_SEL_BB, Path_SEL_RF; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 1; +#else + const u4Byte retryCount = 2; +#endif +#endif + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if(t==0) + { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s for %d times\n", (*pDM_Odm->pIs1Antenna ? "1ant" : "2ant"), t)); + if(*pDM_Odm->pIs1Antenna) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s\n", (*pDM_Odm->pRFDefaultPath ? "S0" : "S1"))); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s for %d times\n", (*pDM_Odm->pIs1Antenna ? "1ant" : "2ant"), t)); + if(*pDM_Odm->pIs1Antenna) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %s\n", (*pDM_Odm->pRFDefaultPath ? "S0" : "S1"))); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE); +#else + _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE); +#endif + +//no serial mode +#if 0 + if(t==0) + { + pRFCalibrateInfo->bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pRFCalibrateInfo->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch8723B(pAdapter, TRUE); +#else + _PHY_PIModeSwitch8723B(pDM_Odm, TRUE); +#endif + } +#endif + + //save RF path for 8723B + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + //save 0x764 GNT_BT + tmp0x764 = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord); + +// Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); +#else + _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); +#endif + + //BB setting + //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + +//for 8723B +#if 0 + if(is2T) + { + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } +#endif + + +//no APK +#if 0 + //Page B init + //AP or IQK + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if(is2T) + { + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } +#endif + +//RX IQ calibration setting for 8723B D cut large current issue when leaving IPS + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); +/* +//LOK RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032); +*/ + + +//path A TX IQK +#if 1 + +#if MP_DRIVER != 1 + if((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE)&& (pDM_Odm->SupportInterface != ODM_ITRF_USB) + && (*pDM_Odm->pRFDefaultPath == 0)) ) +#endif + { + + for(i = 0 ; i < retryCount ; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8723B(pAdapter); +#else + PathAOK = phy_PathA_IQK_8723B(pDM_Odm); +#endif +// if(PathAOK == 0x03){ + if(PathAOK == 0x01) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + + } +#endif + +//path A RXIQK +#if 1 + + for(i = 0 ; i < retryCount ; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK8723B(pAdapter); +#else + PathAOK = phy_PathA_RxIQK8723B(pDM_Odm); +#endif + if(PathAOK == 0x03) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1Rx IQK Fail!!\n")); + } + } + + if(0x00 == PathAOK) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 IQK failed!!\n")); + } + } +#endif + +//path B TX IQK + +/* +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// _PHY_PathAStandBy8723B(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T); +#else +// _PHY_PathAStandBy8723B(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif +*/ + +//path B TX IQK +#if 1 + +#if MP_DRIVER != 1 + if((*pDM_Odm->pIs1Antenna == FALSE) || ((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) + || (pDM_Odm->SupportInterface == ODM_ITRF_USB)) +#endif + { + + for(i = 0 ; i < retryCount ; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8723B(pAdapter); +#else + PathBOK = phy_PathB_IQK_8723B(pDM_Odm); +#endif +// if(PathBOK == 0x03){ + if(PathBOK == 0x01) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } + + } +#endif + +//path B RX IQK +#if 1 + + for(i = 0 ; i < retryCount ; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK8723B(pAdapter); +#else + PathBOK = phy_PathB_RxIQK8723B(pDM_Odm); +#endif + if(PathBOK == 0x03) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Fail!!\n")); + } + } + +#endif + + if(0x00 == PathBOK) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if(t!=0) + { + if(!pRFCalibrateInfo->bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// _PHY_PIModeSwitch8723B(pAdapter, FALSE); +#else +// _PHY_PIModeSwitch8723B(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pRFCalibrateInfo->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pRFCalibrateInfo->IQK_MAC_backup); + + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + //Reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + //reload 0x764 GNT_BT + ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, tmp0x764); + +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); + + //Allen initial gain 0xc50 + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if(*pDM_Odm->pIs1Antenna == FALSE){ + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]phy_IQCalibrate_8723B() <==\n")); + +} + + +VOID +phy_LCCalibrate_8723B( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF + + // Channel 10 LC calibration issue for 8723bs with 26M xtal + if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); + } + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == ODM_RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + else if(path == ODM_RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == ODM_RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pRFCalibrateInfo->bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if(path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if(path == ODM_RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pRFCalibrateInfo->bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + +// IQK version:V2.9 20141201 +// 1. modify the boundary of IQK result for 8723B F-cut + +VOID +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + + u1Byte u1bTmp; + u2Byte count=0; +#endif + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + u4Byte Path_SEL_BB = 0; + BOOLEAN bReloadIQK = FALSE; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if(priv->pshare->rf_ft_var.mp_specific) + { + if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if(priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + + +#if MP_DRIVER == 1 + // Add to determine IQK ON/OFF in certain case, Suggested by Cheng. + if (!pHalData->IQK_MP_Switch) + return; + + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; +#endif + + +#if DISABLE_BB_RF + return; +#endif + + + if (pRFCalibrateInfo->bIQKInProgress) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(bReCovery) +#else//for ODM_WIN + if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#endif + return; + } + + + +#if MP_DRIVER != 1 +//check if IQK had been done before!! + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S1 0xc80 = 0x%x, S0 0xc80 = 0x%x\n", pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL], pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL])); + + if((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 0)) // 1-ant, S1 + { + if(ODM_SetIQCbyRFpath(pDM_Odm, 0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]1-ant S1 IQK value is reloaded!!!\n")); + bReloadIQK = TRUE; + } + } + else if((*pDM_Odm->pIs1Antenna == TRUE) && (*pDM_Odm->pRFDefaultPath == 1)) // 1-ant, S0 + { + if(ODM_SetIQCbyRFpath(pDM_Odm, 1)) // S0 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]1-ant S0 IQK value is reloaded!!!\n")); + bReloadIQK = TRUE; + } + } + else // 2-ant + { + if((pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK has been done before.!!!\n")); + + if((Path_SEL_BB == 0x0) || (Path_SEL_BB == 0x200)) //S1 + { + if(ODM_SetIQCbyRFpath(pDM_Odm, 0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]2-ant S1 IQK value is reloaded!!!\n")); + bReloadIQK = TRUE; + } + } + else // S0 + { + if(ODM_SetIQCbyRFpath(pDM_Odm, 1)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]2-ant S0 IQK value is reloaded!!!\n")); + bReloadIQK = TRUE; + } + } + } + } + + if(bReloadIQK) + return; +#endif + + //Check & wait if BT is doing IQK +#if MP_DRIVER != 1 + // Set H2C cmd to inform FW (enable). + SetFwWiFiCalibrationCmd_8723B(pAdapter, 1); + + // Check 0x1e6 + count=0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while(u1bTmp != 0x1 && count<1000) + { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + + if(count >= 1000) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + } + + // Wait BT IQK finished. + // polling 0x1e7[0]=1 or 300ms timeout + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + while((!(u1bTmp&BIT0)) && count<6000) + { + PlatformStallExecution(50); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + count++; + } +#endif + + +// Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948 = 0x%x\n", Path_SEL_BB)); + + + //IQK start!!!!!!!!!! + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Start!!!\n")); + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i=0; i<3; i++) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_IQCalibrate_8723B(pAdapter, result, i); +#else + phy_IQCalibrate_8723B(pDM_Odm, result, i); +#endif + + + if(i == 1) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1); +#endif + if(is12simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if(i == 2) + { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2); +#endif + if(is13simular) + { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2); +#endif + if(is23simular) + { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is23simular final_candidate is %x\n",final_candidate)); + } + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pRFCalibrateInfo->RegE94 = RegE94 = result[final_candidate][0]; + pRFCalibrateInfo->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pRFCalibrateInfo->RegEB4 = RegEB4 = result[final_candidate][4]; + pRFCalibrateInfo->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: final_candidate is %x\n",final_candidate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: FAIL use default value\n")); + pRFCalibrateInfo->RegE94 = pRFCalibrateInfo->RegEB4 = 0x100; //X default value + pRFCalibrateInfo->RegE9C = pRFCalibrateInfo->RegEBC = 0x0; //Y default value + } + + // fill IQK matrix + if (RegE94 != 0) + _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + if (RegEB4 != 0) + _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if(final_candidate < 4) + { + for(i = 0; i < IQK_Matrix_REG_NUM; i++) + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pRFCalibrateInfo->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pRFCalibrateInfo->IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + // Restore RF Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]is1ant = %d, supprotinterface = %d, RFdefaultpath=%d.\n",*pDM_Odm->pIs1Antenna, pDM_Odm->SupportInterface, *pDM_Odm->pRFDefaultPath )); + +//fill IQK register +#if MP_DRIVER == 1 + if((Path_SEL_BB == 0x0) || (Path_SEL_BB == 0x200)) //S1 + ODM_SetIQCbyRFpath( pDM_Odm, 0); + else + ODM_SetIQCbyRFpath( pDM_Odm, 1); +#else + if(*pDM_Odm->pRFDefaultPath == 0x0 ) //S1 + ODM_SetIQCbyRFpath( pDM_Odm, 0); + else + ODM_SetIQCbyRFpath( pDM_Odm, 1); +#endif + + +#if MP_DRIVER != 1 + // Set H2C cmd to inform FW (disable). + SetFwWiFiCalibrationCmd_8723B(pAdapter, 0); + + // Check 0x1e6 + count = 0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while(u1bTmp != 0 && count<1000) + { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + + if(count >= 1000) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + } +#endif + + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK finished\n")); +} + + +VOID +PHY_LCCalibrate_8723B( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + + +#if MP_DRIVER == 1 + // Add to Disable Default LCK when Cont Tx, For Lab Test Usage. + if (!pHalData->IQK_MP_Switch) + return; + + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pRFCalibrateInfo->bLCKInProgress = TRUE; + + + phy_LCCalibrate_8723B(pDM_Odm, FALSE); + + + pRFCalibrateInfo->bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pRFCalibrateInfo->bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8723B(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8723B(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8723B(pDM_Odm, delta, FALSE); +#endif + } +} +VOID phy_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + if(bMain) // Left antenna + { + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); + } + else + { + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); + } +} +VOID PHY_SetRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE); +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion8723B( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pRFCalibrateInfo->bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pRFCalibrateInfo->bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pRFCalibrateInfo->bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pRFCalibrateInfo->bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pRFCalibrateInfo->bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexbDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8723B( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pRFCalibrateInfo->bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_DigitalPredistortion8723B(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion8723B(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) + return TRUE; + else + return FALSE; + +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE); +#endif + +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.h b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.h index 7bd1d406b7c..baf2dc08003 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/halphyrf_8723b_win.h @@ -1,129 +1,129 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8723B_H__ -#define __HAL_PHY_RF_8723B_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define index_mapping_NUM_8723B 15 -#define AVG_THERMAL_NUM_8723B 4 - -#include "halphyrf_win.h" - -void ConfigureTxpowerTrack_8723B( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8723B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr_8723B( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - -BOOLEAN -ODM_SetIQCbyRFpath( -//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -//#else - //IN PADAPTER pAdapter, -//#endif - IN u4Byte RFpath - ); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8723B( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration_8723B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723B_H__ +#define __HAL_PHY_RF_8723B_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define index_mapping_NUM_8723B 15 +#define AVG_THERMAL_NUM_8723B 4 + +#include "halphyrf_win.h" + +void ConfigureTxpowerTrack_8723B( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8723B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723B( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + +BOOLEAN +ODM_SetIQCbyRFpath( +//#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +//#else + //IN PADAPTER pAdapter, +//#endif + IN u4Byte RFpath + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8723B( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723B( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.c b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.c index e10eb8067bd..2f18788c484 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.c @@ -1,232 +1,232 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT == 1) - -void -odm_ConfigRFReg_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if(Addr == 0xfe || Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else - { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. - if(Addr == 0xb6) - { - u4Byte getvalue=0; - u1Byte count =0; - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - - ODM_delay_us(1); - - while((getvalue>>8)!=(Data>>8)) - { - count++; - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - ODM_delay_us(1); - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); - if(count>5) - break; - } - } - - if(Addr == 0xb2) - { - u4Byte getvalue=0; - u1Byte count =0; - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - - ODM_delay_us(1); - - while(getvalue!=Data) - { - count++; - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - ODM_delay_us(1); - //Do LCK againg - ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07); - ODM_delay_us(1); - getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); - if(count>5) - break; - } - } - } -} - - -void -odm_ConfigRF_RadioA_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else - { -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - } - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8723B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT == 1) + +void +odm_ConfigRFReg_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. + if(Addr == 0xb6) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while((getvalue>>8)!=(Data>>8)) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + + if(Addr == 0xb2) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while(getvalue!=Data) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + //Do LCK againg + ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + } +} + + +void +odm_ConfigRF_RadioA_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8723B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + } + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8723B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.h b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.h index de6531e6e08..4f2d3884e31 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_regconfig8723b.h @@ -1,96 +1,96 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8723B -#define __INC_ODM_REGCONFIG_H_8723B - -#if (RTL8723B_SUPPORT == 1) - -void -odm_ConfigRFReg_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8723B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8723B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8723B +#define __INC_ODM_REGCONFIG_H_8723B + +#if (RTL8723B_SUPPORT == 1) + +void +odm_ConfigRFReg_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8723B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8723B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.c b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.c index f450addb1f7..1e0f2c4a501 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.c @@ -1,70 +1,70 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723B_SUPPORT == 1) - - s1Byte -odm_CCKRSSI_8723B( - IN u1Byte LNA_idx, - IN u1Byte VGA_idx - ) -{ - s1Byte rx_pwr_all=0x00; - switch (LNA_idx) { - //46 53 73 95 201301231630 - // 46 53 77 99 201301241630 - - case 6: - rx_pwr_all = -40 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = -20 - (2 * VGA_idx); - break; - case 1: - rx_pwr_all = 0 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = 10 - (2 * VGA_idx); - break; - default: - /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ - /*DbgPrint("wrong LNA index\n");*/ - break; - - } - return rx_pwr_all; -} - -#endif // end if RTL8723B - - - - - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723B_SUPPORT == 1) + + s1Byte +odm_CCKRSSI_8723B( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all=0x00; + switch (LNA_idx) { + //46 53 73 95 201301231630 + // 46 53 77 99 201301241630 + + case 6: + rx_pwr_all = -40 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = -20 - (2 * VGA_idx); + break; + case 1: + rx_pwr_all = 0 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = 10 - (2 * VGA_idx); + break; + default: + /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ + /*DbgPrint("wrong LNA index\n");*/ + break; + + } + return rx_pwr_all; +} + +#endif // end if RTL8723B + + + + + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.h b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.h index c41a6965c23..a7739ef175e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/phydm_rtl8723b.h @@ -1,29 +1,29 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_RTL8723B_H__ -#define __ODM_RTL8723B_H__ - -s1Byte -odm_CCKRSSI_8723B( - IN u1Byte LNA_idx, - IN u1Byte VGA_idx - ); - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8723B_H__ +#define __ODM_RTL8723B_H__ + +s1Byte +odm_CCKRSSI_8723B( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ); + +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8723b/version_rtl8723b.h b/package/kernel/rtl8192cd/phydm/rtl8723b/version_rtl8723b.h index 2533f8cde34..c7b61c45b8d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723b/version_rtl8723b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723b/version_rtl8723b.h @@ -1,9 +1,9 @@ -/*RTL8723B PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8723B 20151208 -#define COMMIT_BY_8723B "BB_STANLEY" -#define RELEASE_VERSION_8723B 28 +/*RTL8723B PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8723B 20151208 +#define COMMIT_BY_8723B "BB_STANLEY" +#define RELEASE_VERSION_8723B 28 diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/hal8723dreg.h b/package/kernel/rtl8192cd/phydm/rtl8723d/hal8723dreg.h index 97dacb3c1c4..43c781fb984 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/hal8723dreg.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/hal8723dreg.h @@ -1,927 +1,927 @@ -/***************************************************************************** - * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. - * - * Module: __INC_HAL8723DREG_H - * - * - * Note: 1. Define Mac register address and corresponding bit mask map - * - * - * Export: Constants, macro, functions(API), global variables(None). - * - * Abbrev: - * - * History: - * Data Who Remark - * - *****************************************************************************/ -#ifndef __INC_HAL8723DREG_H -#define __INC_HAL8723DREG_H - - - -//============================================================ -// -//============================================================ - -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -#define REG_SYS_ISO_CTRL_8723D 0x0000 // 2 Byte -#define REG_SYS_FUNC_EN_8723D 0x0002 // 2 Byte -#define REG_SYS_PW_CTRL_8723D 0x0004 // 4 Byte -#define REG_SYS_CLKR_8723D 0x0008 // 2 Byte -#define REG_SYS_EEPROM_CTRL_8723D 0x000A // 2 Byte -#define REG_EE_VPD_8723D 0x000C // 2 Byte -#define REG_SYS_SWR_CTRL1_8723D 0x0010 // 1 Byte -#define REG_SYS_SWR_CTRL2_8723D 0x0014 // 1 Byte -#define REG_SYS_SWR_CTRL3_8723D 0x0018 // 4 Byte -#define REG_RSV_CTRL_8723D 0x001C // 3 Byte -#define REG_RF_CTRL_8723D 0x001F // 1 Byte -#define REG_AFE_CTRL1_8723D 0x0024 // 4 Byte -#define REG_AFE_CTRL2_8723D 0x0028 // 4 Byte -#define REG_AFE_CTRL3_8723D 0x002c // 4 Byte -#define REG_EFUSE_CTRL_8723D 0x0030 -#define REG_LDO_EFUSE_CTRL_8723D 0x0034 -#define REG_PWR_DATA_8723D 0x0038 -#define REG_CAL_TIMER_8723D 0x003C -#define REG_ACLK_MON_8723D 0x003E -#define REG_GPIO_MUXCFG_8723D 0x0040 -#define REG_GPIO_IO_SEL_8723D 0x0042 -#define REG_MAC_PINMUX_CFG_8723D 0x0043 // ?????? -#define REG_GPIO_PIN_CTRL_8723D 0x0044 -#define REG_GPIO_INTM_8723D 0x0048 -#define BIT_REG_LED_CFG_8723D 0x004C -#define REG_LEDCFG2_8723D 0x004E // ?????? -#define REG_FSIMR_8723D 0x0050 -#define REG_FSISR_8723D 0x0054 -#define REG_HSIMR_8723D 0x0058 -#define REG_HSISR_8723D 0x005c -#define REG_GPIO_EXT_CTRL_8723D 0x0060 -#define REG_MULTI_FUNC_CTRL_8723D 0x0068 -#define REG_GPIO_STATUS_8723D 0x006C -#define REG_SDIO_CTRL_8723D 0x0070 -#define REG_HCI_OPT_CTRL_8723D 0x0074 -#define REG_AFE_CTRL4_8723D 0x0078 -#define REG_LDO_SWR_CTRL_8723D 0x007C -#define REG_8051FW_CTRL_8723D 0x0080 -#define REG_FW_DBG_STATUS_8723D 0x0088 -#define REG_FW_DBG_CTRL_8723D 0x008F -#define REG_WLLPS_CTRL_8723D 0x0090 -#define REG_HIMR0_8723D 0x00B0 -#define REG_HISR0_8723D 0x00B4 -#define REG_HIMR1_8723D 0x00B8 -#define REG_HISR1_8723D 0x00BC -#define REG_PMC_DBG_CTRL2_8723D 0x00CC -#define REG_EFUSE_BURN_GNT_8723D 0x00CF -#define REG_XTAL_AAC_8723D 0x00EC -#define REG_SYS_CFG1_8723D 0x00F0 -#define REG_SYS_CFG2_8723D 0x00FC -#define REG_ROM_VERSION 0x00FD - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -#define REG_CR_8723D 0x0100 -#define REG_PBP_8723D 0x0104 // ?????? -#define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 // ?????? -#define REG_TRXDMA_CTRL_8723D 0x010C -#define REG_TRXFF_BNDY_8723D 0x0114 -#define REG_RXFF_PTR_8723D 0x011C -#define REG_CPWM_8723D 0x012C -#define REG_FWIMR_8723D 0x0130 -#define REG_FWISR_8723D 0x0134 -#define REG_FTIMR_8723D 0x0138 -#define REG_PKTBUF_DBG_CTRL_8723D 0x0140 -#define REG_RXPKTBUF_CTRL_8723D 0x0142 // ?????? -#define REG_PKTBUF_DBG_DATA_L_8723D 0x0144 -#define REG_PKTBUF_DBG_DATA_H_8723D 0x0148 - -#define REG_TC0_CTRL_8723D 0x0150 -#define REG_TC1_CTRL_8723D 0x0154 -#define REG_TC2_CTRL_8723D 0x0158 -#define REG_TC3_CTRL_8723D 0x015C -#define REG_TC4_CTRL_8723D 0x0160 -#define REG_TCUNIT_BASE_8723D 0x0164 -#define REG_RSVD3_8723D 0x0168 // ????? - -#define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 // ?????? -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ?????? -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ?????? -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ?????? -#define REG_C2HEVT_CLEAR_8723D 0x01AF // ?????? -#define REG_MCUTST_1_8723D 0x01C0 -#define REG_MCUTST_2_8723D 0x01C4 -#define REG_MCUTST_WOWLAN_8723D 0x01C7 // ?????? -#define REG_FMETHR_8723D 0x01C8 -#define REG_HMETFR_8723D 0x01CC -#define REG_HMEBOX_0_8723D 0x01D0 -#define REG_HMEBOX_1_8723D 0x01D4 -#define REG_HMEBOX_2_8723D 0x01D8 -#define REG_HMEBOX_3_8723D 0x01DC -#define REG_LLT_INIT_8723D 0x01E0 -#define REG_HMEBOX_EXT0_8723D 0x01F0 // ?????? -#define REG_HMEBOX_EXT1_8723D 0x01F4 // ?????? -#define REG_HMEBOX_EXT2_8723D 0x01F8 // ?????? -#define REG_HMEBOX_EXT3_8723D 0x01FC // ?????? - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -#define REG_RQPN_8723D 0x0200 -#define REG_FIFOPAGE_8723D 0x0204 -#define REG_TDECTRL_8723D 0x0208 -#define REG_TXDMA_OFFSET_CHK_8723D 0x020C -#define REG_TXDMA_STATUS_8723D 0x0210 -#define REG_RQPN_NPQ_8723D 0x0214 -#define REG_AUTO_LLT_8723D 0x0224 -#define REG_DWBCN1_CTRL_8723D 0x0228 - - -//----------------------------------------------------- -// -// 0x0280h ~ 0x02FFh RXDMA Configuration -// -//----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH_8723D 0x0280 -#define REG_RXPKT_NUM_8723D 0x0284 // The number of packets in RXPKTBUF. -#define REG_RXDMA_CONTROL_8723D 0x0286 // ?????? Control the RX DMA. -#define REG_RXDMA_STATUS_8723D 0x0288 -#define REG_RXDMA_PRO_8723D 0x0290 // ?????? -#define REG_EARLY_MODE_CONTROL_8723D 0x02BC // ?????? -#define REG_RSVD5_8723D 0x02F0 // ?????? - - -//----------------------------------------------------- -// -// 0x0300h ~ 0x03FFh PCIe -// -//----------------------------------------------------- -#define REG_PCIE_CTRL_REG_8723D 0x0300 -#define REG_INT_MIG_8723D 0x0304 // Interrupt Migration -#define REG_BCNQ_TXBD_DESA_8723D 0x0308 // TX Beacon Descriptor Address -#define REG_MGQ_TXBD_DESA_8723D 0x0310 // TX Manage Queue Descriptor Address -#define REG_VOQ_TXBD_DESA_8723D 0x0318 // TX VO Queue Descriptor Address -#define REG_VIQ_TXBD_DESA_8723D 0x0320 // TX VI Queue Descriptor Address -#define REG_BEQ_TXBD_DESA_8723D 0x0328 // TX BE Queue Descriptor Address -#define REG_BKQ_TXBD_DESA_8723D 0x0330 // TX BK Queue Descriptor Address -#define REG_RXQ_RXBD_DESA_8723D 0x0338 // RX Queue Descriptor Address -#define REG_HI0Q_TXBD_DESA_8723D 0x0340 -#define REG_HI1Q_TXBD_DESA_8723D 0x0348 -#define REG_HI2Q_TXBD_DESA_8723D 0x0350 -#define REG_HI3Q_TXBD_DESA_8723D 0x0358 -#define REG_HI4Q_TXBD_DESA_8723D 0x0360 -#define REG_HI5Q_TXBD_DESA_8723D 0x0368 -#define REG_HI6Q_TXBD_DESA_8723D 0x0370 -#define REG_HI7Q_TXBD_DESA_8723D 0x0378 -#define REG_MGQ_TXBD_NUM_8723D 0x0380 -#define REG_RX_RXBD_NUM_8723D 0x0382 -#define REG_VOQ_TXBD_NUM_8723D 0x0384 -#define REG_VIQ_TXBD_NUM_8723D 0x0386 -#define REG_BEQ_TXBD_NUM_8723D 0x0388 -#define REG_BKQ_TXBD_NUM_8723D 0x038A -#define REG_HI0Q_TXBD_NUM_8723D 0x038C -#define REG_HI1Q_TXBD_NUM_8723D 0x038E -#define REG_HI2Q_TXBD_NUM_8723D 0x0390 -#define REG_HI3Q_TXBD_NUM_8723D 0x0392 -#define REG_HI4Q_TXBD_NUM_8723D 0x0394 -#define REG_HI5Q_TXBD_NUM_8723D 0x0396 -#define REG_HI6Q_TXBD_NUM_8723D 0x0398 -#define REG_HI7Q_TXBD_NUM_8723D 0x039A -#define REG_TSFTIMER_HCI_8723D 0x039C - -//Read Write Point -#define REG_VOQ_TXBD_IDX_8723D 0x03A0 -#define REG_VIQ_TXBD_IDX_8723D 0x03A4 -#define REG_BEQ_TXBD_IDX_8723D 0x03A8 -#define REG_BKQ_TXBD_IDX_8723D 0x03AC -#define REG_MGQ_TXBD_IDX_8723D 0x03B0 -#define REG_RXQ_TXBD_IDX_8723D 0x03B4 -#define REG_HI0Q_TXBD_IDX_8723D 0x03B8 -#define REG_HI1Q_TXBD_IDX_8723D 0x03BC -#define REG_HI2Q_TXBD_IDX_8723D 0x03C0 -#define REG_HI3Q_TXBD_IDX_8723D 0x03C4 -#define REG_HI4Q_TXBD_IDX_8723D 0x03C8 -#define REG_HI5Q_TXBD_IDX_8723D 0x03CC -#define REG_HI6Q_TXBD_IDX_8723D 0x03D0 -#define REG_HI7Q_TXBD_IDX_8723D 0x03D4 - -#define REG_PCIE_HCPWM_8723DE 0x03D8 // ?????? -#define REG_PCIE_HRPWM_8723DE 0x03DC //PCIe RPWM // ?????? -#define REG_DBI_WDATA_V1_8723D 0x03E8 -#define REG_DBI_RDATA_V1_8723D 0x03EC -#define REG_DBI_FLAG_V1_8723D 0x03F0 -#define REG_MDIO_V1_8723D 0x03F4 -#define REG_PCIE_MIX_CFG_8723D 0x03F8 -#define REG_HCI_MIX_CFG_8723D 0x03FC - -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -#define REG_TXPKT_EMPTY_8723D 0x041A -#define REG_PTCL_POLL_MGN_8723D 0x041F -#define REG_FWHW_TXQ_CTRL_8723D 0x0420 -#define REG_HWSEQ_CTRL_8723D 0x0423 -#define REG_BCNQ_BDNY_8723D 0x0424 -#define REG_MGQ_BDNY_8723D 0x0425 -#define REG_LIFETIME_EN_8723D 0x0426 -#define REG_FW_FREE_TAIL_8723D 0x0427 -#define REG_SPEC_SIFS_8723D 0x0428 -#define REG_RETRY_LIMIT_8723D 0x042A -#define REG_TXBF_CTRL_8723D 0x042C -#define REG_DARFRC_8723D 0x0430 -#define REG_RARFRC_8723D 0x0438 -#define REG_RRSR_8723D 0x0440 -#define REG_ARFR0_8723D 0x0444 -#define REG_ARFR1_8723D 0x044C -#define REG_CCK_CHECK_8723D 0x0454 -#define REG_BCNQ2_BDNY_8723D 0x0455 -#define REG_AMPDU_MAX_TIME_8723D 0x0456 -#define REG_BCNQ1_BDNY_8723D 0x0457 -#define REG_AMPDU_MAX_LENGTH_8723D 0x0458 -#define REG_WMAC_LBK_BUF_HD_8723D 0x045D -#define REG_NDPA_OPT_CTRL_8723D 0x045F -#define REG_FAST_EDCA_CTRL_8723D 0x0460 -#define REG_RD_RESP_PKT_TH_8723D 0x0463 -#define REG_DATA_SC_8723D 0x0483 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8723D 0x04B4 -#define REG_PTCL_SDF_STATUS_8723D 0x04BB -#define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC -#define REG_EVTQ_BNDY_8723D 0x04BF -#define REG_PKT_LIFE_TIME_8723D 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 // ?????? - -#define REG_STBC_SETTING_8723D 0x04C4 -#define REG_HT_SINGLE_AMPDU_8723D 0x04C7 -#define REG_PROT_MODE_CTRL_8723D 0x04C8 -#define REG_MAX_AGGR_NUM_8723D 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB -#define REG_BAR_MODE_CTRL_8723D 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF -#define REG_MACID_SLEEP2_8723D 0x04D0 -#define REG_PTCL_HWSSN0_8723D 0x04D8 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D // ?????? - - -/************* 0x1480~0x14A7 is for NAN ***************/ -//Own Master Rank, 8Bytes -#define REG_NAN_INTERFACE_ADDR_8723D 0x2480 // 6 bytes -#define REG_NAN_RANDOM_FACTOR_8723D 0x2486 // 1 byte -#define REG_NAN_MASTER_PREF_8723D 0x2487 // 1 byte - -//0x5dc[25:24] NAN role - -//Current Anchor Master Record -#define REG_NAN_CAMR_L_8723D 0x2488 // 4 bytes -#define REG_NAN_CAMR_H_8723D 0x248C // 4 byte -//#define REG_HOP_CNT_8723D 0x05DC -#define REG_NAN_CAMR_AMBTT_8723D 0x2490 // 4 bytes - -//Last Anchor Master Record -#define REG_NAN_LAMR_L_8723D 0x2494 // 4 bytes -#define REG_NAN_LAMR_H_8723D 0x2498 // 4 byte -#define REG_NAN_LAMR_AMBTT_8723D 0x249C // 4 bytes - -//TSF Synced:bit 0 -//Anchor Master: bit 7 -#define REG_NAN_STATUS_8723D 0x24A0 //BIT0 -/***************************************************/ - - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -// gogogo -#define REG_EDCA_VO_PARAM_8723D 0x0500 -#define REG_EDCA_VI_PARAM_8723D 0x0504 -#define REG_EDCA_BE_PARAM_8723D 0x0508 -#define REG_EDCA_BK_PARAM_8723D 0x050C -#define REG_BCNTCFG_8723D 0x0510 -#define REG_PIFS_8723D 0x0512 -#define REG_RDG_PIFS_8723D 0x0513 -#define REG_SIFS_CTX_8723D 0x0514 -#define REG_SIFS_TRX_8723D 0x0516 -#define REG_AGGR_BREAK_TIME_8723D 0x051A -#define REG_SLOT_8723D 0x051B -#define REG_TX_PTCL_CTRL_8723D 0x0520 -#define REG_TXPAUSE_8723D 0x0522 -#define REG_DIS_TXREQ_CLR_8723D 0x0523 -#define REG_RD_CTRL_8723D 0x0524 -// -// Format for offset 540h-542h: -// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. -// [7:4]: Reserved. -// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. -// [23:20]: Reserved -// Description: -// | -// |<--Setup--|--Hold------------>| -// --------------|---------------------- -// | -// TBTT -// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. -// Described by Designer Tim and Bruce, 2011-01-14. -// -#define REG_TBTT_PROHIBIT_8723D 0x0540 -#define REG_RD_NAV_NXT_8723D 0x0544 -#define REG_NAV_PROT_LEN_8723D 0x0546 -#define REG_BCN_CTRL_8723D 0x0550 -#define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551 -#define REG_MBID_NUM_8723D 0x0552 -#define REG_DUAL_TSF_RST_8723D 0x0553 -#define REG_BCN_INTERVAL_8723D 0x0554 -#define REG_DRVERLYINT_8723D 0x0558 -#define REG_BCNDMATIM_8723D 0x0559 -#define REG_ATIMWND_8723D 0x055A -#define REG_USTIME_TSF_8723D 0x055C -#define REG_BCN_MAX_ERR_8723D 0x055D -#define REG_RXTSF_OFFSET_CCK_8723D 0x055E -#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F -#define REG_TSFTR_8723D 0x0560 -#define REG_CTWND_8723D 0x0572 -#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 // ?????? -#define REG_TSFTR2_8723D 0x0578 -#define REG_PSTIMER_8723D 0x0580 -#define REG_TIMER0_8723D 0x0584 -#define REG_TIMER1_8723D 0x0588 -#define REG_SCH_MULTI_BCN_8723D 0x05B2 -#define REG_SCH_CURRENT_BCN_8723D 0x05B3 -#define REG_ACMHWCTRL_8723D 0x05C0 -#define REG_SCH_SDFX_EARLY_8723D 0x05CF -#define REG_SCH_PORT2_EARLY_8723D 0x05D0 -#define REG_SCH_TSFT_DIFF_8723D 0x05D2 -#define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4 -#define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4 -#define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8 -#define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA -#define REG_HOP_CNT_8723D 0x05DC -#define REG_SCH_M_DW_8723D 0x05DD -#define REG_SCH_M_SLOT_8723D 0x05DE -#define REG_SCH_EARLY_DWEND_8723D 0x05DF -#define REG_SCH_TXCMD_8723D 0x05F8 - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -// gogogo -#define REG_MAC_CR_8723D 0x0600 -#define REG_TCR_8723D 0x0604 -#define REG_RCR_8723D 0x0608 -#define REG_RX_PKT_LIMIT_8723D 0x060C -#define REG_RX_DLK_TIME_8723D 0x060D -#define REG_RX_DRVINFO_SZ_8723D 0x060F - -#define REG_MACID_8723D 0x0610 -#define REG_BSSID_8723D 0x0618 -#define REG_MAR_8723D 0x0620 -#define REG_MBIDCAMCFG_8723D 0x0628 - -#define REG_USTIME_EDCA_8723D 0x0638 -#define REG_MAC_SPEC_SIFS_8723D 0x063A -#define REG_RESP_SIFP_CCK_8723D 0x063C -#define REG_RESP_SIFS_OFDM_8723D 0x063E -#define REG_ACKTO_8723D 0x0640 -#define REG_CTS2TO_8723D 0x0641 -#define REG_EIFS_8723D 0x0642 - -#define REG_NAV_UPPER_8723D 0x0652 // ?????? -#define REG_TRXPTCL_CTL_8723D 0x0668 - -// Security -#define REG_CAMCMD_8723D 0x0670 -#define REG_CAMWRITE_8723D 0x0674 -#define REG_CAMREAD_8723D 0x0678 -#define REG_CAMDBG_8723D 0x067C -#define REG_SECCFG_8723D 0x0680 - -// Power -#define REG_WOW_CTRL_8723D 0x0690 -#define REG_PS_RX_INFO_8723D 0x0692 -#define REG_UAPSD_TID_8723D 0x0693 -#define REG_WKFMCAM_NUM_8723D 0x0698 -#define REG_RXFLTMAP0_8723D 0x06A0 -#define REG_RXFLTMAP1_8723D 0x06A2 -#define REG_RXFLTMAP2_8723D 0x06A4 -#define REG_BCN_PSR_RPT_8723D 0x06A8 -#define REG_BT_COEX_TABLE_8723D 0x06C0 -#define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC - -// Hardware Port 2 -#define REG_MACID1_8723D 0x0700 -#define REG_BSSID1_8723D 0x0708 -#define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714 -#define REG_SND_PTCL_CTRL_8723D 0x0718 - -//----------------------------------------------------- -// -// Redifine 8192C register definition for compatibility -// -//----------------------------------------------------- - -// TODO: use these definition when using REG_xxx naming rule. -// NOTE: DO NOT Remove these definition. Use later. -#define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D // E-Fuse Control. -#define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D // E-Fuse Test. -#define MSR_8723D (REG_CR_8723D + 2) // Media Status register -#define ISR_8723D REG_HISR0_8723D -#define TSFR_8723D REG_TSFTR_8723D // Timing Sync Function Timer Register. - -// Redifine MACID register, to compatible prior ICs. -#define IDR0_8723D REG_MACID_8723D // MAC ID Register, Offset 0x0050-0x0053 -#define IDR4_8723D (REG_MACID_8723D + 4) // MAC ID Register, Offset 0x0054-0x0055 - - -// -// 9. Security Control Registers (Offset: ) -// -#define RWCAM_8723D REG_CAMCMD_8723D //IN 8190 Data Sheet is called CAMcmd -#define WCAMI_8723D REG_CAMWRITE_8723D // Software write CAM input content -#define RCAMO_8723D REG_CAMREAD_8723D // Software read/write CAM config -#define CAMDBG_8723D REG_CAMDBG_8723D -#define SECR_8723D REG_SECCFG_8723D //Security Configuration Register - - -//---------------------------------------------------------------------------- -// 8195 IMR/ISR bits (offset 0xB0, 8bits) -//---------------------------------------------------------------------------- -#define IMR_DISABLED_8723D 0 -// IMR DW0(0x00B0-00B3) Bit 0-31 -#define IMR_TIMER2_8723D BIT31 // Timeout interrupt 2 -#define IMR_TIMER1_8723D BIT30 // Timeout interrupt 1 -#define IMR_PSTIMEOUT_8723D BIT29 // Power Save Time Out Interrupt -#define IMR_GTINT4_8723D BIT28 // When GTIMER4 expires, this bit is set to 1 -#define IMR_GTINT3_8723D BIT27 // When GTIMER3 expires, this bit is set to 1 -#define IMR_TXBCN0ERR_8723D BIT26 // Transmit Beacon0 Error -#define IMR_TXBCN0OK_8723D BIT25 // Transmit Beacon0 OK -#define IMR_TSF_BIT32_TOGGLE_8723D BIT24 // TSF Timer BIT32 toggle indication interrupt -#define IMR_BCNDMAINT0_8723D BIT20 // Beacon DMA Interrupt 0 -#define IMR_BCNDERR0_8723D BIT16 // Beacon Queue DMA OK0 -#define IMR_HSISR_IND_ON_INT_8723D BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define IMR_BCNDMAINT_E_8723D BIT14 // Beacon DMA Interrupt Extension for Win7 -#define IMR_ATIMEND_8723D BIT12 // CTWidnow End or ATIM Window End -#define IMR_C2HCMD_8723D BIT10 // CPU to Host Command INT Status, Write 1 clear -#define IMR_CPWM2_8723D BIT9 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_CPWM_8723D BIT8 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_HIGHDOK_8723D BIT7 // High Queue DMA OK -#define IMR_MGNTDOK_8723D BIT6 // Management Queue DMA OK -#define IMR_BKDOK_8723D BIT5 // AC_BK DMA OK -#define IMR_BEDOK_8723D BIT4 // AC_BE DMA OK -#define IMR_VIDOK_8723D BIT3 // AC_VI DMA OK -#define IMR_VODOK_8723D BIT2 // AC_VO DMA OK -#define IMR_RDU_8723D BIT1 // Rx Descriptor Unavailable -#define IMR_ROK_8723D BIT0 // Receive DMA OK - -// IMR DW1(0x00B4-00B7) Bit 0-31 -#define IMR_BCNDMAINT7_8723D BIT27 // Beacon DMA Interrupt 7 -#define IMR_BCNDMAINT6_8723D BIT26 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5_8723D BIT25 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4_8723D BIT24 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3_8723D BIT23 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2_8723D BIT22 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1_8723D BIT21 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK7_8723D BIT20 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6_8723D BIT19 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5_8723D BIT18 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4_8723D BIT17 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3_8723D BIT16 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2_8723D BIT15 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1_8723D BIT14 // Beacon Queue DMA OK Interrup 1 -#define IMR_ATIMEND_E_8723D BIT13 // ATIM Window End Extension for Win7 -#define IMR_TXERR_8723D BIT11 // Tx Error Flag Interrupt Status, write 1 clear. -#define IMR_RXERR_8723D BIT10 // Rx Error Flag INT Status, Write 1 clear -#define IMR_TXFOVW_8723D BIT9 // Transmit FIFO Overflow -#define IMR_RXFOVW_8723D BIT8 // Receive FIFO Overflow - - - -#define IMR_MCUERR_8723D BIT28 // Beacon DMA Interrupt 7 - - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ -//---------------------------------------------------------------------------- -// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- -/* -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopVO BIT3 -#define StopVI BIT2 -#define StopBE BIT1 -#define StopBK BIT0 -*/ - - - -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -/* -//2 SYS_ISO_CTRL -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) -#define PWC_EV12V BIT(15) - - -//2 SYS_FUNC_EN -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) - -//2 APS_FSMCO -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) - -//2 SYS_CLKR -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) - - -//2 9346CR - -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - - -//2 RF_CTRL -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - -//2 LDOV12D_CTRL -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - - -//2 EFUSE_TEST (For RTL8723 partially) -#define EF_TRPT BIT(7) -#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 -#define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) -#define EFUSE_SEL_MASK 0x300 -#define EFUSE_WIFI_SEL_0 0x0 -#define EFUSE_BT_SEL_0 0x1 -#define EFUSE_BT_SEL_1 0x2 -#define EFUSE_BT_SEL_2 0x3 - - -//2 8051FWDL -//2 MCUFWDL -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define RAM_DL_SEL BIT(7) -#define ROM_DLEN BIT(19) -#define CPRST BIT(23) - - - -//2 REG_SYS_CFG -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define TRP_B15V_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define BT_FUNC BIT(16) -#define VENDOR_ID BIT(19) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) // RTL ID -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 -#define CHIP_VER_RTL_SHIFT 12 - -*/ -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -/* - -//2 Function Enable Registers -//2 CR 0x0100-0x0103 - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) -#define CALTMR_EN BIT(10) // 32k CAL TMR enable - -// Network type -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - - -//2 PBP - Page Size Register 0x0104 -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 - - -//2 TX/RXDMA 0x010C -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) - -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - - -//2 REG_C2HEVT_CLEAR 0x01AF -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - - - -//2 LLT_INIT 0x01E0 -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 - -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - -*/ -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -/* -//2 TDECTL 0x0208 -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - - -//2 TXDMA_OFFSET_CHK 0x020C -#define DROP_DATA_EN BIT(9) -*/ -//----------------------------------------------------- -// -// 0x0280h ~ 0x028Bh RX DMA Configuration -// -//----------------------------------------------------- -/* -//2 REG_RXDMA_CONTROL, 0x0286h - -// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before -// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. -#define RXPKT_RELEASE_POLL BIT(0) -// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in -// this bit. FW can start releasing packets after RXDMA entering idle mode. -#define RXDMA_IDLE BIT(1) -// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host -// completed, and stop DMA packet to host. RXDMA will then report Default: 0; -#define RW_RELEASE_EN BIT(2) -*/ -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -/* -//2 FWHW_TXQ_CTRL 0x0420 -#define EN_AMPDU_RTY_NEW BIT(7) - - -//2 REG_LIFECTRL_CTRL 0x0426 -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 - -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. - - -//2 SPEC SIFS 0x0428 -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) - -//2 RL 0x042A -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) -*/ - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -/* -//2 EDCA setting 0x050C -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - -//2 BCN_CTRL 0x0550 -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) - -//2 TxPause 0x0522 -#define STOP_BCNQ BIT(6) -*/ - - -//2 ACMHWCTRL 0x05C0 -#define AcmHw_HwEn_8723D BIT(0) -#define AcmHw_VoqEn_8723D BIT(1) -#define AcmHw_ViqEn_8723D BIT(2) -#define AcmHw_BeqEn_8723D BIT(3) -#define AcmHw_VoqStatus_8723D BIT(5) -#define AcmHw_ViqStatus_8723D BIT(6) -#define AcmHw_BeqStatus_8723D BIT(7) - - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -/* - -//2 TCR 0x0604 -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) -*/ - -//---------------------------------------------------------------------------- -// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) -//---------------------------------------------------------------------------- -/* -#define RCR_APPFCS BIT31 // WMAC append FCS after pauload -#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. -#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. -#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF -#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. -#define RCR_RSVD_BIT26 BIT26 // Reserved -*/ -#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload -/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. -#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. -#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. -*/ - - -#endif // #ifndef __INC_HAL8723DREG_H +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8723DREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8723DREG_H +#define __INC_HAL8723DREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8723D 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8723D 0x0002 // 2 Byte +#define REG_SYS_PW_CTRL_8723D 0x0004 // 4 Byte +#define REG_SYS_CLKR_8723D 0x0008 // 2 Byte +#define REG_SYS_EEPROM_CTRL_8723D 0x000A // 2 Byte +#define REG_EE_VPD_8723D 0x000C // 2 Byte +#define REG_SYS_SWR_CTRL1_8723D 0x0010 // 1 Byte +#define REG_SYS_SWR_CTRL2_8723D 0x0014 // 1 Byte +#define REG_SYS_SWR_CTRL3_8723D 0x0018 // 4 Byte +#define REG_RSV_CTRL_8723D 0x001C // 3 Byte +#define REG_RF_CTRL_8723D 0x001F // 1 Byte +#define REG_AFE_CTRL1_8723D 0x0024 // 4 Byte +#define REG_AFE_CTRL2_8723D 0x0028 // 4 Byte +#define REG_AFE_CTRL3_8723D 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8723D 0x0030 +#define REG_LDO_EFUSE_CTRL_8723D 0x0034 +#define REG_PWR_DATA_8723D 0x0038 +#define REG_CAL_TIMER_8723D 0x003C +#define REG_ACLK_MON_8723D 0x003E +#define REG_GPIO_MUXCFG_8723D 0x0040 +#define REG_GPIO_IO_SEL_8723D 0x0042 +#define REG_MAC_PINMUX_CFG_8723D 0x0043 // ?????? +#define REG_GPIO_PIN_CTRL_8723D 0x0044 +#define REG_GPIO_INTM_8723D 0x0048 +#define BIT_REG_LED_CFG_8723D 0x004C +#define REG_LEDCFG2_8723D 0x004E // ?????? +#define REG_FSIMR_8723D 0x0050 +#define REG_FSISR_8723D 0x0054 +#define REG_HSIMR_8723D 0x0058 +#define REG_HSISR_8723D 0x005c +#define REG_GPIO_EXT_CTRL_8723D 0x0060 +#define REG_MULTI_FUNC_CTRL_8723D 0x0068 +#define REG_GPIO_STATUS_8723D 0x006C +#define REG_SDIO_CTRL_8723D 0x0070 +#define REG_HCI_OPT_CTRL_8723D 0x0074 +#define REG_AFE_CTRL4_8723D 0x0078 +#define REG_LDO_SWR_CTRL_8723D 0x007C +#define REG_8051FW_CTRL_8723D 0x0080 +#define REG_FW_DBG_STATUS_8723D 0x0088 +#define REG_FW_DBG_CTRL_8723D 0x008F +#define REG_WLLPS_CTRL_8723D 0x0090 +#define REG_HIMR0_8723D 0x00B0 +#define REG_HISR0_8723D 0x00B4 +#define REG_HIMR1_8723D 0x00B8 +#define REG_HISR1_8723D 0x00BC +#define REG_PMC_DBG_CTRL2_8723D 0x00CC +#define REG_EFUSE_BURN_GNT_8723D 0x00CF +#define REG_XTAL_AAC_8723D 0x00EC +#define REG_SYS_CFG1_8723D 0x00F0 +#define REG_SYS_CFG2_8723D 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8723D 0x0100 +#define REG_PBP_8723D 0x0104 // ?????? +#define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 // ?????? +#define REG_TRXDMA_CTRL_8723D 0x010C +#define REG_TRXFF_BNDY_8723D 0x0114 +#define REG_RXFF_PTR_8723D 0x011C +#define REG_CPWM_8723D 0x012C +#define REG_FWIMR_8723D 0x0130 +#define REG_FWISR_8723D 0x0134 +#define REG_FTIMR_8723D 0x0138 +#define REG_PKTBUF_DBG_CTRL_8723D 0x0140 +#define REG_RXPKTBUF_CTRL_8723D 0x0142 // ?????? +#define REG_PKTBUF_DBG_DATA_L_8723D 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8723D 0x0148 + +#define REG_TC0_CTRL_8723D 0x0150 +#define REG_TC1_CTRL_8723D 0x0154 +#define REG_TC2_CTRL_8723D 0x0158 +#define REG_TC3_CTRL_8723D 0x015C +#define REG_TC4_CTRL_8723D 0x0160 +#define REG_TCUNIT_BASE_8723D 0x0164 +#define REG_RSVD3_8723D 0x0168 // ????? + +#define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 // ?????? +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ?????? +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ?????? +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ?????? +#define REG_C2HEVT_CLEAR_8723D 0x01AF // ?????? +#define REG_MCUTST_1_8723D 0x01C0 +#define REG_MCUTST_2_8723D 0x01C4 +#define REG_MCUTST_WOWLAN_8723D 0x01C7 // ?????? +#define REG_FMETHR_8723D 0x01C8 +#define REG_HMETFR_8723D 0x01CC +#define REG_HMEBOX_0_8723D 0x01D0 +#define REG_HMEBOX_1_8723D 0x01D4 +#define REG_HMEBOX_2_8723D 0x01D8 +#define REG_HMEBOX_3_8723D 0x01DC +#define REG_LLT_INIT_8723D 0x01E0 +#define REG_HMEBOX_EXT0_8723D 0x01F0 // ?????? +#define REG_HMEBOX_EXT1_8723D 0x01F4 // ?????? +#define REG_HMEBOX_EXT2_8723D 0x01F8 // ?????? +#define REG_HMEBOX_EXT3_8723D 0x01FC // ?????? + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8723D 0x0200 +#define REG_FIFOPAGE_8723D 0x0204 +#define REG_TDECTRL_8723D 0x0208 +#define REG_TXDMA_OFFSET_CHK_8723D 0x020C +#define REG_TXDMA_STATUS_8723D 0x0210 +#define REG_RQPN_NPQ_8723D 0x0214 +#define REG_AUTO_LLT_8723D 0x0224 +#define REG_DWBCN1_CTRL_8723D 0x0228 + + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8723D 0x0280 +#define REG_RXPKT_NUM_8723D 0x0284 // The number of packets in RXPKTBUF. +#define REG_RXDMA_CONTROL_8723D 0x0286 // ?????? Control the RX DMA. +#define REG_RXDMA_STATUS_8723D 0x0288 +#define REG_RXDMA_PRO_8723D 0x0290 // ?????? +#define REG_EARLY_MODE_CONTROL_8723D 0x02BC // ?????? +#define REG_RSVD5_8723D 0x02F0 // ?????? + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8723D 0x0300 +#define REG_INT_MIG_8723D 0x0304 // Interrupt Migration +#define REG_BCNQ_TXBD_DESA_8723D 0x0308 // TX Beacon Descriptor Address +#define REG_MGQ_TXBD_DESA_8723D 0x0310 // TX Manage Queue Descriptor Address +#define REG_VOQ_TXBD_DESA_8723D 0x0318 // TX VO Queue Descriptor Address +#define REG_VIQ_TXBD_DESA_8723D 0x0320 // TX VI Queue Descriptor Address +#define REG_BEQ_TXBD_DESA_8723D 0x0328 // TX BE Queue Descriptor Address +#define REG_BKQ_TXBD_DESA_8723D 0x0330 // TX BK Queue Descriptor Address +#define REG_RXQ_RXBD_DESA_8723D 0x0338 // RX Queue Descriptor Address +#define REG_HI0Q_TXBD_DESA_8723D 0x0340 +#define REG_HI1Q_TXBD_DESA_8723D 0x0348 +#define REG_HI2Q_TXBD_DESA_8723D 0x0350 +#define REG_HI3Q_TXBD_DESA_8723D 0x0358 +#define REG_HI4Q_TXBD_DESA_8723D 0x0360 +#define REG_HI5Q_TXBD_DESA_8723D 0x0368 +#define REG_HI6Q_TXBD_DESA_8723D 0x0370 +#define REG_HI7Q_TXBD_DESA_8723D 0x0378 +#define REG_MGQ_TXBD_NUM_8723D 0x0380 +#define REG_RX_RXBD_NUM_8723D 0x0382 +#define REG_VOQ_TXBD_NUM_8723D 0x0384 +#define REG_VIQ_TXBD_NUM_8723D 0x0386 +#define REG_BEQ_TXBD_NUM_8723D 0x0388 +#define REG_BKQ_TXBD_NUM_8723D 0x038A +#define REG_HI0Q_TXBD_NUM_8723D 0x038C +#define REG_HI1Q_TXBD_NUM_8723D 0x038E +#define REG_HI2Q_TXBD_NUM_8723D 0x0390 +#define REG_HI3Q_TXBD_NUM_8723D 0x0392 +#define REG_HI4Q_TXBD_NUM_8723D 0x0394 +#define REG_HI5Q_TXBD_NUM_8723D 0x0396 +#define REG_HI6Q_TXBD_NUM_8723D 0x0398 +#define REG_HI7Q_TXBD_NUM_8723D 0x039A +#define REG_TSFTIMER_HCI_8723D 0x039C + +//Read Write Point +#define REG_VOQ_TXBD_IDX_8723D 0x03A0 +#define REG_VIQ_TXBD_IDX_8723D 0x03A4 +#define REG_BEQ_TXBD_IDX_8723D 0x03A8 +#define REG_BKQ_TXBD_IDX_8723D 0x03AC +#define REG_MGQ_TXBD_IDX_8723D 0x03B0 +#define REG_RXQ_TXBD_IDX_8723D 0x03B4 +#define REG_HI0Q_TXBD_IDX_8723D 0x03B8 +#define REG_HI1Q_TXBD_IDX_8723D 0x03BC +#define REG_HI2Q_TXBD_IDX_8723D 0x03C0 +#define REG_HI3Q_TXBD_IDX_8723D 0x03C4 +#define REG_HI4Q_TXBD_IDX_8723D 0x03C8 +#define REG_HI5Q_TXBD_IDX_8723D 0x03CC +#define REG_HI6Q_TXBD_IDX_8723D 0x03D0 +#define REG_HI7Q_TXBD_IDX_8723D 0x03D4 + +#define REG_PCIE_HCPWM_8723DE 0x03D8 // ?????? +#define REG_PCIE_HRPWM_8723DE 0x03DC //PCIe RPWM // ?????? +#define REG_DBI_WDATA_V1_8723D 0x03E8 +#define REG_DBI_RDATA_V1_8723D 0x03EC +#define REG_DBI_FLAG_V1_8723D 0x03F0 +#define REG_MDIO_V1_8723D 0x03F4 +#define REG_PCIE_MIX_CFG_8723D 0x03F8 +#define REG_HCI_MIX_CFG_8723D 0x03FC + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_TXPKT_EMPTY_8723D 0x041A +#define REG_PTCL_POLL_MGN_8723D 0x041F +#define REG_FWHW_TXQ_CTRL_8723D 0x0420 +#define REG_HWSEQ_CTRL_8723D 0x0423 +#define REG_BCNQ_BDNY_8723D 0x0424 +#define REG_MGQ_BDNY_8723D 0x0425 +#define REG_LIFETIME_EN_8723D 0x0426 +#define REG_FW_FREE_TAIL_8723D 0x0427 +#define REG_SPEC_SIFS_8723D 0x0428 +#define REG_RETRY_LIMIT_8723D 0x042A +#define REG_TXBF_CTRL_8723D 0x042C +#define REG_DARFRC_8723D 0x0430 +#define REG_RARFRC_8723D 0x0438 +#define REG_RRSR_8723D 0x0440 +#define REG_ARFR0_8723D 0x0444 +#define REG_ARFR1_8723D 0x044C +#define REG_CCK_CHECK_8723D 0x0454 +#define REG_BCNQ2_BDNY_8723D 0x0455 +#define REG_AMPDU_MAX_TIME_8723D 0x0456 +#define REG_BCNQ1_BDNY_8723D 0x0457 +#define REG_AMPDU_MAX_LENGTH_8723D 0x0458 +#define REG_WMAC_LBK_BUF_HD_8723D 0x045D +#define REG_NDPA_OPT_CTRL_8723D 0x045F +#define REG_FAST_EDCA_CTRL_8723D 0x0460 +#define REG_RD_RESP_PKT_TH_8723D 0x0463 +#define REG_DATA_SC_8723D 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8723D 0x04B4 +#define REG_PTCL_SDF_STATUS_8723D 0x04BB +#define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC +#define REG_EVTQ_BNDY_8723D 0x04BF +#define REG_PKT_LIFE_TIME_8723D 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 // ?????? + +#define REG_STBC_SETTING_8723D 0x04C4 +#define REG_HT_SINGLE_AMPDU_8723D 0x04C7 +#define REG_PROT_MODE_CTRL_8723D 0x04C8 +#define REG_MAX_AGGR_NUM_8723D 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB +#define REG_BAR_MODE_CTRL_8723D 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF +#define REG_MACID_SLEEP2_8723D 0x04D0 +#define REG_PTCL_HWSSN0_8723D 0x04D8 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D // ?????? + + +/************* 0x1480~0x14A7 is for NAN ***************/ +//Own Master Rank, 8Bytes +#define REG_NAN_INTERFACE_ADDR_8723D 0x2480 // 6 bytes +#define REG_NAN_RANDOM_FACTOR_8723D 0x2486 // 1 byte +#define REG_NAN_MASTER_PREF_8723D 0x2487 // 1 byte + +//0x5dc[25:24] NAN role + +//Current Anchor Master Record +#define REG_NAN_CAMR_L_8723D 0x2488 // 4 bytes +#define REG_NAN_CAMR_H_8723D 0x248C // 4 byte +//#define REG_HOP_CNT_8723D 0x05DC +#define REG_NAN_CAMR_AMBTT_8723D 0x2490 // 4 bytes + +//Last Anchor Master Record +#define REG_NAN_LAMR_L_8723D 0x2494 // 4 bytes +#define REG_NAN_LAMR_H_8723D 0x2498 // 4 byte +#define REG_NAN_LAMR_AMBTT_8723D 0x249C // 4 bytes + +//TSF Synced:bit 0 +//Anchor Master: bit 7 +#define REG_NAN_STATUS_8723D 0x24A0 //BIT0 +/***************************************************/ + + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +// gogogo +#define REG_EDCA_VO_PARAM_8723D 0x0500 +#define REG_EDCA_VI_PARAM_8723D 0x0504 +#define REG_EDCA_BE_PARAM_8723D 0x0508 +#define REG_EDCA_BK_PARAM_8723D 0x050C +#define REG_BCNTCFG_8723D 0x0510 +#define REG_PIFS_8723D 0x0512 +#define REG_RDG_PIFS_8723D 0x0513 +#define REG_SIFS_CTX_8723D 0x0514 +#define REG_SIFS_TRX_8723D 0x0516 +#define REG_AGGR_BREAK_TIME_8723D 0x051A +#define REG_SLOT_8723D 0x051B +#define REG_TX_PTCL_CTRL_8723D 0x0520 +#define REG_TXPAUSE_8723D 0x0522 +#define REG_DIS_TXREQ_CLR_8723D 0x0523 +#define REG_RD_CTRL_8723D 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8723D 0x0540 +#define REG_RD_NAV_NXT_8723D 0x0544 +#define REG_NAV_PROT_LEN_8723D 0x0546 +#define REG_BCN_CTRL_8723D 0x0550 +#define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551 +#define REG_MBID_NUM_8723D 0x0552 +#define REG_DUAL_TSF_RST_8723D 0x0553 +#define REG_BCN_INTERVAL_8723D 0x0554 +#define REG_DRVERLYINT_8723D 0x0558 +#define REG_BCNDMATIM_8723D 0x0559 +#define REG_ATIMWND_8723D 0x055A +#define REG_USTIME_TSF_8723D 0x055C +#define REG_BCN_MAX_ERR_8723D 0x055D +#define REG_RXTSF_OFFSET_CCK_8723D 0x055E +#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F +#define REG_TSFTR_8723D 0x0560 +#define REG_CTWND_8723D 0x0572 +#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 // ?????? +#define REG_TSFTR2_8723D 0x0578 +#define REG_PSTIMER_8723D 0x0580 +#define REG_TIMER0_8723D 0x0584 +#define REG_TIMER1_8723D 0x0588 +#define REG_SCH_MULTI_BCN_8723D 0x05B2 +#define REG_SCH_CURRENT_BCN_8723D 0x05B3 +#define REG_ACMHWCTRL_8723D 0x05C0 +#define REG_SCH_SDFX_EARLY_8723D 0x05CF +#define REG_SCH_PORT2_EARLY_8723D 0x05D0 +#define REG_SCH_TSFT_DIFF_8723D 0x05D2 +#define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4 +#define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4 +#define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8 +#define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA +#define REG_HOP_CNT_8723D 0x05DC +#define REG_SCH_M_DW_8723D 0x05DD +#define REG_SCH_M_SLOT_8723D 0x05DE +#define REG_SCH_EARLY_DWEND_8723D 0x05DF +#define REG_SCH_TXCMD_8723D 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +// gogogo +#define REG_MAC_CR_8723D 0x0600 +#define REG_TCR_8723D 0x0604 +#define REG_RCR_8723D 0x0608 +#define REG_RX_PKT_LIMIT_8723D 0x060C +#define REG_RX_DLK_TIME_8723D 0x060D +#define REG_RX_DRVINFO_SZ_8723D 0x060F + +#define REG_MACID_8723D 0x0610 +#define REG_BSSID_8723D 0x0618 +#define REG_MAR_8723D 0x0620 +#define REG_MBIDCAMCFG_8723D 0x0628 + +#define REG_USTIME_EDCA_8723D 0x0638 +#define REG_MAC_SPEC_SIFS_8723D 0x063A +#define REG_RESP_SIFP_CCK_8723D 0x063C +#define REG_RESP_SIFS_OFDM_8723D 0x063E +#define REG_ACKTO_8723D 0x0640 +#define REG_CTS2TO_8723D 0x0641 +#define REG_EIFS_8723D 0x0642 + +#define REG_NAV_UPPER_8723D 0x0652 // ?????? +#define REG_TRXPTCL_CTL_8723D 0x0668 + +// Security +#define REG_CAMCMD_8723D 0x0670 +#define REG_CAMWRITE_8723D 0x0674 +#define REG_CAMREAD_8723D 0x0678 +#define REG_CAMDBG_8723D 0x067C +#define REG_SECCFG_8723D 0x0680 + +// Power +#define REG_WOW_CTRL_8723D 0x0690 +#define REG_PS_RX_INFO_8723D 0x0692 +#define REG_UAPSD_TID_8723D 0x0693 +#define REG_WKFMCAM_NUM_8723D 0x0698 +#define REG_RXFLTMAP0_8723D 0x06A0 +#define REG_RXFLTMAP1_8723D 0x06A2 +#define REG_RXFLTMAP2_8723D 0x06A4 +#define REG_BCN_PSR_RPT_8723D 0x06A8 +#define REG_BT_COEX_TABLE_8723D 0x06C0 +#define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8723D 0x0700 +#define REG_BSSID1_8723D 0x0708 +#define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714 +#define REG_SND_PTCL_CTRL_8723D 0x0718 + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D // E-Fuse Control. +#define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D // E-Fuse Test. +#define MSR_8723D (REG_CR_8723D + 2) // Media Status register +#define ISR_8723D REG_HISR0_8723D +#define TSFR_8723D REG_TSFTR_8723D // Timing Sync Function Timer Register. + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8723D REG_MACID_8723D // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8723D (REG_MACID_8723D + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8723D REG_CAMCMD_8723D //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8723D REG_CAMWRITE_8723D // Software write CAM input content +#define RCAMO_8723D REG_CAMREAD_8723D // Software read/write CAM config +#define CAMDBG_8723D REG_CAMDBG_8723D +#define SECR_8723D REG_SECCFG_8723D //Security Configuration Register + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8723D 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8723D BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8723D BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8723D BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8723D BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8723D BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8723D BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8723D BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8723D BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8723D BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8723D BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8723D BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8723D BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8723D BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8723D BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8723D BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8723D BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8723D BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8723D BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8723D BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8723D BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8723D BIT3 // AC_VI DMA OK +#define IMR_VODOK_8723D BIT2 // AC_VO DMA OK +#define IMR_RDU_8723D BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8723D BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8723D BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8723D BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8723D BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8723D BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8723D BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8723D BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8723D BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8723D BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8723D BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8723D BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8723D BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8723D BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8723D BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8723D BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8723D BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8723D BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8723D BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8723D BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8723D BIT8 // Receive FIFO Overflow + + + +#define IMR_MCUERR_8723D BIT28 // Beacon DMA Interrupt 7 + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8723D BIT(0) +#define AcmHw_VoqEn_8723D BIT(1) +#define AcmHw_ViqEn_8723D BIT(2) +#define AcmHw_BeqEn_8723D BIT(3) +#define AcmHw_VoqStatus_8723D BIT(5) +#define AcmHw_ViqStatus_8723D BIT(6) +#define AcmHw_BeqStatus_8723D BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload +/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. +#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. +#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. +*/ + + +#endif // #ifndef __INC_HAL8723DREG_H diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.c b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.c index 3b1d9e73797..6a0c2de2174 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.c @@ -1,917 +1,917 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723D_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8723D_AGC_TAB[] = { - 0xC78, 0xFE000101, - 0xC78, 0xFD010101, - 0xC78, 0xFC020101, - 0xC78, 0xFB030101, - 0xC78, 0xFA040101, - 0xC78, 0xF9050101, - 0xC78, 0xF8060101, - 0xC78, 0xF7070101, - 0xC78, 0xF6080101, - 0xC78, 0xF5090101, - 0xC78, 0xF40A0101, - 0xC78, 0xF30B0101, - 0xC78, 0xF20C0101, - 0xC78, 0xF10D0101, - 0xC78, 0xF00E0101, - 0xC78, 0xEF0F0101, - 0xC78, 0xEE100101, - 0xC78, 0xED110101, - 0xC78, 0xEC120101, - 0xC78, 0xEB130101, - 0xC78, 0xEA140101, - 0xC78, 0xE9150101, - 0xC78, 0xE8160101, - 0xC78, 0xE7170101, - 0xC78, 0xE6180101, - 0xC78, 0xE5190101, - 0xC78, 0xE41A0101, - 0xC78, 0xE31B0101, - 0xC78, 0xE21C0101, - 0xC78, 0xE11D0101, - 0xC78, 0xE01E0101, - 0xC78, 0x861F0101, - 0xC78, 0x85200101, - 0xC78, 0x84210101, - 0xC78, 0x83220101, - 0xC78, 0x82230101, - 0xC78, 0x81240101, - 0xC78, 0x80250101, - 0xC78, 0x44260101, - 0xC78, 0x43270101, - 0xC78, 0x42280101, - 0xC78, 0x41290101, - 0xC78, 0x402A0101, - 0xC78, 0x022B0101, - 0xC78, 0x012C0101, - 0xC78, 0x002D0101, - 0xC78, 0xC52E0001, - 0xC78, 0xC42F0001, - 0xC78, 0xC3300001, - 0xC78, 0xC2310001, - 0xC78, 0xC1320001, - 0xC78, 0xC0330001, - 0xC78, 0x04340001, - 0xC78, 0x03350001, - 0xC78, 0x02360001, - 0xC78, 0x01370001, - 0xC78, 0x00380001, - 0xC78, 0x00390001, - 0xC78, 0x003A0001, - 0xC78, 0x003B0001, - 0xC78, 0x003C0001, - 0xC78, 0x003D0001, - 0xC78, 0x003E0001, - 0xC78, 0x003F0001, - 0xC78, 0x6F002001, - 0xC78, 0x6F012001, - 0xC78, 0x6F022001, - 0xC78, 0x6F032001, - 0xC78, 0x6F042001, - 0xC78, 0x6F052001, - 0xC78, 0x6F062001, - 0xC78, 0x6F072001, - 0xC78, 0x6F082001, - 0xC78, 0x6F092001, - 0xC78, 0x6F0A2001, - 0xC78, 0x6F0B2001, - 0xC78, 0x6F0C2001, - 0xC78, 0x6F0D2001, - 0xC78, 0x6F0E2001, - 0xC78, 0x6F0F2001, - 0xC78, 0x6F102001, - 0xC78, 0x6F112001, - 0xC78, 0x6F122001, - 0xC78, 0x6F132001, - 0xC78, 0x6F142001, - 0xC78, 0x6F152001, - 0xC78, 0x6F162001, - 0xC78, 0x6F172001, - 0xC78, 0x6F182001, - 0xC78, 0x6F192001, - 0xC78, 0x6F1A2001, - 0xC78, 0x6F1B2001, - 0xC78, 0x6F1C2001, - 0xC78, 0x6F1D2001, - 0xC78, 0x6F1E2001, - 0xC78, 0x6F1F2001, - 0xC78, 0x6F202001, - 0xC78, 0x6F212001, - 0xC78, 0x6F222001, - 0xC78, 0x6F232001, - 0xC78, 0x6E242001, - 0xC78, 0x6D252001, - 0xC78, 0x6C262001, - 0xC78, 0x6B272001, - 0xC78, 0x6A282001, - 0xC78, 0x69292001, - 0xC78, 0x4B2A2001, - 0xC78, 0x4A2B2001, - 0xC78, 0x492C2001, - 0xC78, 0x482D2001, - 0xC78, 0x472E2001, - 0xC78, 0x462F2001, - 0xC78, 0x45302001, - 0xC78, 0x44312001, - 0xC78, 0x43322001, - 0xC78, 0x42332001, - 0xC78, 0x41342001, - 0xC78, 0x40352001, - 0xC78, 0x02362001, - 0xC78, 0x01372001, - 0xC78, 0x00382001, - 0xC78, 0x00392001, - 0xC78, 0x003A2001, - 0xC78, 0x003B2001, - 0xC78, 0x003C2001, - 0xC78, 0x003D2001, - 0xC78, 0x003E2001, - 0xC78, 0x003F2001, - 0xC78, 0x7F003101, - 0xC78, 0x7F013101, - 0xC78, 0x7F023101, - 0xC78, 0x7F033101, - 0xC78, 0x7F043101, - 0xC78, 0x7F053101, - 0xC78, 0x7F063101, - 0xC78, 0x7F073101, - 0xC78, 0x7E083101, - 0xC78, 0x7D093101, - 0xC78, 0x7C0A3101, - 0xC78, 0x7B0B3101, - 0xC78, 0x7A0C3101, - 0xC78, 0x790D3101, - 0xC78, 0x780E3101, - 0xC78, 0x770F3101, - 0xC78, 0x76103101, - 0xC78, 0x75113101, - 0xC78, 0x74123101, - 0xC78, 0x73133101, - 0xC78, 0x72143101, - 0xC78, 0x71153101, - 0xC78, 0x70163101, - 0xC78, 0x6F173101, - 0xC78, 0x6E183101, - 0xC78, 0x6D193101, - 0xC78, 0x6C1A3101, - 0xC78, 0x6B1B3101, - 0xC78, 0x6A1C3101, - 0xC78, 0x691D3101, - 0xC78, 0x681E3101, - 0xC78, 0x4B1F3101, - 0xC78, 0x4A203101, - 0xC78, 0x49213101, - 0xC78, 0x48223101, - 0xC78, 0x47233101, - 0xC78, 0x46243101, - 0xC78, 0x45253101, - 0xC78, 0x44263101, - 0xC78, 0x43273101, - 0xC78, 0x42283101, - 0xC78, 0x41293101, - 0xC78, 0x402A3101, - 0xC78, 0x022B3101, - 0xC78, 0x012C3101, - 0xC78, 0x002D3101, - 0xC78, 0x002E3101, - 0xC78, 0x002F3101, - 0xC78, 0x00303101, - 0xC78, 0x00313101, - 0xC78, 0x00323101, - 0xC78, 0x00333101, - 0xC78, 0x00343101, - 0xC78, 0x00353101, - 0xC78, 0x00363101, - 0xC78, 0x00373101, - 0xC78, 0x00383101, - 0xC78, 0x00393101, - 0xC78, 0x003A3101, - 0xC78, 0x003B3101, - 0xC78, 0x003C3101, - 0xC78, 0x003D3101, - 0xC78, 0x003E3101, - 0xC78, 0x003F3101, - 0xC78, 0xFE403101, - 0xC78, 0xFD413101, - 0xC78, 0xFC423101, - 0xC78, 0xFB433101, - 0xC78, 0xFA443101, - 0xC78, 0xF9453101, - 0xC78, 0xF8463101, - 0xC78, 0xF7473101, - 0xC78, 0xF6483101, - 0xC78, 0xF5493101, - 0xC78, 0xF44A3101, - 0xC78, 0xF34B3101, - 0xC78, 0xF24C3101, - 0xC78, 0xF14D3101, - 0xC78, 0xF04E3101, - 0xC78, 0xEF4F3101, - 0xC78, 0xEE503101, - 0xC78, 0xED513101, - 0xC78, 0xEC523101, - 0xC78, 0xEB533101, - 0xC78, 0xEA543101, - 0xC78, 0xE9553101, - 0xC78, 0xE8563101, - 0xC78, 0xE7573101, - 0xC78, 0xE6583101, - 0xC78, 0xE5593101, - 0xC78, 0xE45A3101, - 0xC78, 0xE35B3101, - 0xC78, 0xE25C3101, - 0xC78, 0xE15D3101, - 0xC78, 0xE05E3101, - 0xC78, 0x865F3101, - 0xC78, 0x85603101, - 0xC78, 0x84613101, - 0xC78, 0x83623101, - 0xC78, 0x82633101, - 0xC78, 0x81643101, - 0xC78, 0x80653101, - 0xC78, 0x80663101, - 0xC78, 0x80673101, - 0xC78, 0x80683101, - 0xC78, 0x80693101, - 0xC78, 0x806A3101, - 0xC78, 0x806B3101, - 0xC78, 0x806C3101, - 0xC78, 0x806D3101, - 0xC78, 0x806E3101, - 0xC78, 0x806F3101, - 0xC78, 0x80703101, - 0xC78, 0x80713101, - 0xC78, 0x80723101, - 0xC78, 0x80733101, - 0xC78, 0x80743101, - 0xC78, 0x80753101, - 0xC78, 0x80763101, - 0xC78, 0x80773101, - 0xC78, 0x80783101, - 0xC78, 0x80793101, - 0xC78, 0x807A3101, - 0xC78, 0x807B3101, - 0xC78, 0x807C3101, - 0xC78, 0x807D3101, - 0xC78, 0x807E3101, - 0xC78, 0x807F3101, - 0xC78, 0xEF402001, - 0xC78, 0xEF412001, - 0xC78, 0xEF422001, - 0xC78, 0xEF432001, - 0xC78, 0xEF442001, - 0xC78, 0xEF452001, - 0xC78, 0xEF462001, - 0xC78, 0xEF472001, - 0xC78, 0xEF482001, - 0xC78, 0xEF492001, - 0xC78, 0xEF4A2001, - 0xC78, 0xEF4B2001, - 0xC78, 0xEF4C2001, - 0xC78, 0xEF4D2001, - 0xC78, 0xEF4E2001, - 0xC78, 0xEF4F2001, - 0xC78, 0xEF502001, - 0xC78, 0xEF512001, - 0xC78, 0xEF522001, - 0xC78, 0xEF532001, - 0xC78, 0xEF542001, - 0xC78, 0xEF552001, - 0xC78, 0xEF562001, - 0xC78, 0xEF572001, - 0xC78, 0xEF582001, - 0xC78, 0xEF592001, - 0xC78, 0xEF5A2001, - 0xC78, 0xEF5B2001, - 0xC78, 0xEF5C2001, - 0xC78, 0xEF5D2001, - 0xC78, 0xEF5E2001, - 0xC78, 0xEF5F2001, - 0xC78, 0xEF602001, - 0xC78, 0xEE612001, - 0xC78, 0xED622001, - 0xC78, 0xEC632001, - 0xC78, 0xEB642001, - 0xC78, 0xEA652001, - 0xC78, 0xE9662001, - 0xC78, 0xE8672001, - 0xC78, 0xCB682001, - 0xC78, 0xCA692001, - 0xC78, 0xC96A2001, - 0xC78, 0xC86B2001, - 0xC78, 0xC76C2001, - 0xC78, 0xC66D2001, - 0xC78, 0xC56E2001, - 0xC78, 0xC46F2001, - 0xC78, 0xC3702001, - 0xC78, 0xC2712001, - 0xC78, 0xC1722001, - 0xC78, 0xC0732001, - 0xC78, 0x82742001, - 0xC78, 0x81752001, - 0xC78, 0x80762001, - 0xC78, 0x80772001, - 0xC78, 0x80782001, - 0xC78, 0x80792001, - 0xC78, 0x807A2001, - 0xC78, 0x807B2001, - 0xC78, 0x807C2001, - 0xC78, 0x807D2001, - 0xC78, 0x807E2001, - 0xC78, 0x807F2001, - 0xC78, 0xFA001101, - 0xC78, 0xF9011101, - 0xC78, 0xF8021101, - 0xC78, 0xF7031101, - 0xC78, 0xF6041101, - 0xC78, 0xF5051101, - 0xC78, 0xF4061101, - 0xC78, 0xD7071101, - 0xC78, 0xD6081101, - 0xC78, 0xD5091101, - 0xC78, 0xD40A1101, - 0xC78, 0x970B1101, - 0xC78, 0x960C1101, - 0xC78, 0x950D1101, - 0xC78, 0x940E1101, - 0xC78, 0x930F1101, - 0xC78, 0x92101101, - 0xC78, 0x91111101, - 0xC78, 0x90121101, - 0xC78, 0x8F131101, - 0xC78, 0x8E141101, - 0xC78, 0x8D151101, - 0xC78, 0x8C161101, - 0xC78, 0x8B171101, - 0xC78, 0x8A181101, - 0xC78, 0x89191101, - 0xC78, 0x881A1101, - 0xC78, 0x871B1101, - 0xC78, 0x861C1101, - 0xC78, 0x851D1101, - 0xC78, 0x841E1101, - 0xC78, 0x831F1101, - 0xC78, 0x82201101, - 0xC78, 0x81211101, - 0xC78, 0x80221101, - 0xC78, 0x43231101, - 0xC78, 0x42241101, - 0xC78, 0x41251101, - 0xC78, 0x04261101, - 0xC78, 0x03271101, - 0xC78, 0x02281101, - 0xC78, 0x01291101, - 0xC78, 0x002A1101, - 0xC78, 0xC42B1001, - 0xC78, 0xC32C1001, - 0xC78, 0xC22D1001, - 0xC78, 0xC12E1001, - 0xC78, 0xC02F1001, - 0xC78, 0x85301001, - 0xC78, 0x84311001, - 0xC78, 0x83321001, - 0xC78, 0x82331001, - 0xC78, 0x81341001, - 0xC78, 0x80351001, - 0xC78, 0x05361001, - 0xC78, 0x04371001, - 0xC78, 0x03381001, - 0xC78, 0x02391001, - 0xC78, 0x013A1001, - 0xC78, 0x003B1001, - 0xC78, 0x003C1001, - 0xC78, 0x003D1001, - 0xC78, 0x003E1001, - 0xC78, 0x003F1001, - 0xC50, 0x69553422, - 0xC50, 0x69553420, - -}; - -void -ODM_ReadAndConfig_MP_8723D_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723D_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723D_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8723D(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723D_AGC_TAB(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723D_PHY_REG[] = { - 0x800, 0x80046C00, - 0x804, 0x00000003, - 0x808, 0x0000FC00, - 0x80C, 0x0000000A, - 0x810, 0x10001331, - 0x814, 0x020C3D10, - 0x818, 0x00200385, - 0x81C, 0x00000000, - 0x820, 0x01000100, - 0x824, 0x00390204, - 0x828, 0x00000000, - 0x82C, 0x00000000, - 0x830, 0x00000000, - 0x834, 0x00000000, - 0x838, 0x00000000, - 0x83C, 0x00000000, - 0x840, 0x00010000, - 0x844, 0x00000000, - 0x848, 0x00000000, - 0x84C, 0x00000000, - 0x850, 0x00000000, - 0x854, 0x00000000, - 0x858, 0x569A11A9, - 0x85C, 0x01000014, - 0x860, 0x66F60110, - 0x864, 0x461F0641, - 0x868, 0x00000000, - 0x86C, 0x27272700, - 0x870, 0x07000460, - 0x874, 0x25004000, - 0x878, 0x00000808, - 0x87C, 0x004F0201, - 0x880, 0xB2002E12, - 0x884, 0x00000007, - 0x888, 0x00000000, - 0x88C, 0xCCC000C0, - 0x890, 0x00000800, - 0x894, 0xFFFFFFFE, - 0x898, 0x40302010, - 0x89C, 0x00706050, - 0x900, 0x00000000, - 0x904, 0x00000023, - 0x908, 0x00000000, - 0x90C, 0x81121111, - 0x910, 0x00000402, - 0x914, 0x00000300, - 0x920, 0x18C6318C, - 0x924, 0x0000018C, - 0x948, 0x99000000, - 0x94C, 0x00000010, - 0x950, 0x00003800, - 0x954, 0x5A380000, - 0x958, 0x4BC6D87A, - 0x95C, 0x04EB9B79, - 0x96C, 0x00000003, - 0x970, 0x00000000, - 0x974, 0x00000000, - 0x978, 0x00000000, - 0x97C, 0x13000000, - 0x980, 0x00000000, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0xA08, 0x8C838300, - 0xA0C, 0x2E20100F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0xE82C0001, - 0xA24, 0x64B80C1C, - 0xA28, 0x00008810, - 0xA2C, 0x00D30000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000007, - 0xA78, 0x00008900, - 0xA7C, 0x225B0606, - 0xA80, 0x2180FA74, - 0xA84, 0x00200000, - 0xA88, 0x040C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x00000000, - 0xA9C, 0x00020000, - 0xAA0, 0x00000000, - 0xAA8, 0xCA100008, - 0xAAC, 0x01235667, - 0xAB0, 0x00000000, - 0xAB4, 0x20201402, - 0xB2C, 0x00000000, - 0xC00, 0x48071D40, - 0xC04, 0x03A05611, - 0xC08, 0x000000E4, - 0xC0C, 0x6C6C6C6C, - 0xC10, 0x28800000, - 0xC14, 0x40000100, - 0xC18, 0x08800000, - 0xC1C, 0x40000100, - 0xC20, 0x00000000, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x69E9AC48, - 0xC34, 0x31000040, - 0xC38, 0x21688080, - 0xC3C, 0x000016D4, - 0xC40, 0x1F78403F, - 0xC44, 0x00010036, - 0xC48, 0xEC020107, - 0xC4C, 0x007F037F, - 0xC50, 0x69553420, - 0xC54, 0x43BC0094, - 0xC58, 0x00015969, - 0xC5C, 0x00310492, - 0xC60, 0x00280A00, - 0xC64, 0x7112848B, - 0xC68, 0x47C074FF, - 0xC6C, 0x00000036, - 0xC70, 0x2C7F000D, - 0xC74, 0x020600DB, - 0xC78, 0x0000001F, - 0xC7C, 0x00B91612, - 0xC80, 0x390000E4, - 0xC84, 0x11F60000, - 0xC88, 0x40000100, - 0xC8C, 0x20200000, - 0xC90, 0x00091521, - 0xC94, 0x00000000, - 0xC98, 0x00121820, - 0xC9C, 0x00007F7F, - 0xCA0, 0x00012000, - 0xCA4, 0xA00000A0, - 0xCA8, 0x85E7C606, - 0xCAC, 0x00000060, - 0xCB0, 0x00000000, - 0xCB4, 0x00000000, - 0xCB8, 0x00000000, - 0xCBC, 0x28000000, - 0xCC0, 0x0010A3D0, - 0xCC4, 0x00000F7D, - 0xCC8, 0x000442D6, - 0xCCC, 0x00000000, - 0xCD0, 0x000001C8, - 0xCD4, 0x001C8000, - 0xCD8, 0x00000100, - 0xCDC, 0x40100000, - 0xCE0, 0x00222222, - 0xCE4, 0x20000000, - 0xCE8, 0x37644302, - 0xCEC, 0x2F97D40C, - 0xD00, 0x00030740, - 0xD04, 0x40020401, - 0xD08, 0x0000907F, - 0xD0C, 0x20010201, - 0xD10, 0xA0633333, - 0xD14, 0x3333BC53, - 0xD18, 0x7A8F5B6F, - 0xD2C, 0xCB979975, - 0xD30, 0x00000000, - 0xD34, 0x80608000, - 0xD38, 0x88000000, - 0xD3C, 0xC0127343, - 0xD40, 0x00000000, - 0xD44, 0x00000000, - 0xD48, 0x00000000, - 0xD4C, 0x00000000, - 0xD50, 0x00000038, - 0xD54, 0x00000000, - 0xD58, 0x00000282, - 0xD5C, 0x30032064, - 0xD60, 0x4653DE68, - 0xD64, 0x04518A3C, - 0xD68, 0x00002101, - 0xE00, 0x2D2D2D2D, - 0xE04, 0x2D2D2D2D, - 0xE08, 0x0390272D, - 0xE10, 0x2D2D2D2D, - 0xE14, 0x2D2D2D2D, - 0xE18, 0x2D2D2D2D, - 0xE1C, 0x2D2D2D2D, - 0xE28, 0x00000000, - 0xE30, 0x1000DC1F, - 0xE34, 0x10008C1F, - 0xE38, 0x02140102, - 0xE3C, 0x681604C2, - 0xE40, 0x01007C00, - 0xE44, 0x01004800, - 0xE48, 0xFB000000, - 0xE4C, 0x000028D1, - 0xE50, 0x1000DC1F, - 0xE54, 0x10008C1F, - 0xE58, 0x02140102, - 0xE5C, 0x28160D05, - 0xE60, 0x00000008, - 0xE68, 0x001B25A4, - 0xE6C, 0x01C00014, - 0xE70, 0x01C00016, - 0xE74, 0x02000014, - 0xE78, 0x02000014, - 0xE7C, 0x02000014, - 0xE80, 0x02000014, - 0xE84, 0x01C00014, - 0xE88, 0x02000014, - 0xE8C, 0x01C00014, - 0xED0, 0x01C00014, - 0xED4, 0x01C00014, - 0xED8, 0x01C00014, - 0xEDC, 0x00000014, - 0xEE0, 0x00000014, - 0xEE8, 0x21555448, - 0xEEC, 0x03C00014, - 0xF14, 0x00000003, - 0xF00, 0x00100300, - 0xF08, 0x0000800B, - 0xF0C, 0x0000F007, - 0xF10, 0x0000A487, - 0xF1C, 0x80000064, - 0xF38, 0x00030155, - 0xF3C, 0x0000003A, - 0xF4C, 0x13000000, - 0xF50, 0x00000000, - 0xF18, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8723D_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723D_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8723D(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723D_PHY_REG(void) -{ - return 28; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723D_PHY_REG_PG[] = { - 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, - 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, - 0, 0, 0, 0x00000e00, 0xffffffff, 0x32343434, - 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303032, - 0, 0, 0, 0x00000e10, 0xffffffff, 0x30323234, - 0, 0, 0, 0x00000e14, 0xffffffff, 0x26282830 -}; - -void -ODM_ReadAndConfig_MP_8723D_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723D_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8723D(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723D_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8723D_AGC_TAB[] = { + 0xC78, 0xFE000101, + 0xC78, 0xFD010101, + 0xC78, 0xFC020101, + 0xC78, 0xFB030101, + 0xC78, 0xFA040101, + 0xC78, 0xF9050101, + 0xC78, 0xF8060101, + 0xC78, 0xF7070101, + 0xC78, 0xF6080101, + 0xC78, 0xF5090101, + 0xC78, 0xF40A0101, + 0xC78, 0xF30B0101, + 0xC78, 0xF20C0101, + 0xC78, 0xF10D0101, + 0xC78, 0xF00E0101, + 0xC78, 0xEF0F0101, + 0xC78, 0xEE100101, + 0xC78, 0xED110101, + 0xC78, 0xEC120101, + 0xC78, 0xEB130101, + 0xC78, 0xEA140101, + 0xC78, 0xE9150101, + 0xC78, 0xE8160101, + 0xC78, 0xE7170101, + 0xC78, 0xE6180101, + 0xC78, 0xE5190101, + 0xC78, 0xE41A0101, + 0xC78, 0xE31B0101, + 0xC78, 0xE21C0101, + 0xC78, 0xE11D0101, + 0xC78, 0xE01E0101, + 0xC78, 0x861F0101, + 0xC78, 0x85200101, + 0xC78, 0x84210101, + 0xC78, 0x83220101, + 0xC78, 0x82230101, + 0xC78, 0x81240101, + 0xC78, 0x80250101, + 0xC78, 0x44260101, + 0xC78, 0x43270101, + 0xC78, 0x42280101, + 0xC78, 0x41290101, + 0xC78, 0x402A0101, + 0xC78, 0x022B0101, + 0xC78, 0x012C0101, + 0xC78, 0x002D0101, + 0xC78, 0xC52E0001, + 0xC78, 0xC42F0001, + 0xC78, 0xC3300001, + 0xC78, 0xC2310001, + 0xC78, 0xC1320001, + 0xC78, 0xC0330001, + 0xC78, 0x04340001, + 0xC78, 0x03350001, + 0xC78, 0x02360001, + 0xC78, 0x01370001, + 0xC78, 0x00380001, + 0xC78, 0x00390001, + 0xC78, 0x003A0001, + 0xC78, 0x003B0001, + 0xC78, 0x003C0001, + 0xC78, 0x003D0001, + 0xC78, 0x003E0001, + 0xC78, 0x003F0001, + 0xC78, 0x6F002001, + 0xC78, 0x6F012001, + 0xC78, 0x6F022001, + 0xC78, 0x6F032001, + 0xC78, 0x6F042001, + 0xC78, 0x6F052001, + 0xC78, 0x6F062001, + 0xC78, 0x6F072001, + 0xC78, 0x6F082001, + 0xC78, 0x6F092001, + 0xC78, 0x6F0A2001, + 0xC78, 0x6F0B2001, + 0xC78, 0x6F0C2001, + 0xC78, 0x6F0D2001, + 0xC78, 0x6F0E2001, + 0xC78, 0x6F0F2001, + 0xC78, 0x6F102001, + 0xC78, 0x6F112001, + 0xC78, 0x6F122001, + 0xC78, 0x6F132001, + 0xC78, 0x6F142001, + 0xC78, 0x6F152001, + 0xC78, 0x6F162001, + 0xC78, 0x6F172001, + 0xC78, 0x6F182001, + 0xC78, 0x6F192001, + 0xC78, 0x6F1A2001, + 0xC78, 0x6F1B2001, + 0xC78, 0x6F1C2001, + 0xC78, 0x6F1D2001, + 0xC78, 0x6F1E2001, + 0xC78, 0x6F1F2001, + 0xC78, 0x6F202001, + 0xC78, 0x6F212001, + 0xC78, 0x6F222001, + 0xC78, 0x6F232001, + 0xC78, 0x6E242001, + 0xC78, 0x6D252001, + 0xC78, 0x6C262001, + 0xC78, 0x6B272001, + 0xC78, 0x6A282001, + 0xC78, 0x69292001, + 0xC78, 0x4B2A2001, + 0xC78, 0x4A2B2001, + 0xC78, 0x492C2001, + 0xC78, 0x482D2001, + 0xC78, 0x472E2001, + 0xC78, 0x462F2001, + 0xC78, 0x45302001, + 0xC78, 0x44312001, + 0xC78, 0x43322001, + 0xC78, 0x42332001, + 0xC78, 0x41342001, + 0xC78, 0x40352001, + 0xC78, 0x02362001, + 0xC78, 0x01372001, + 0xC78, 0x00382001, + 0xC78, 0x00392001, + 0xC78, 0x003A2001, + 0xC78, 0x003B2001, + 0xC78, 0x003C2001, + 0xC78, 0x003D2001, + 0xC78, 0x003E2001, + 0xC78, 0x003F2001, + 0xC78, 0x7F003101, + 0xC78, 0x7F013101, + 0xC78, 0x7F023101, + 0xC78, 0x7F033101, + 0xC78, 0x7F043101, + 0xC78, 0x7F053101, + 0xC78, 0x7F063101, + 0xC78, 0x7F073101, + 0xC78, 0x7E083101, + 0xC78, 0x7D093101, + 0xC78, 0x7C0A3101, + 0xC78, 0x7B0B3101, + 0xC78, 0x7A0C3101, + 0xC78, 0x790D3101, + 0xC78, 0x780E3101, + 0xC78, 0x770F3101, + 0xC78, 0x76103101, + 0xC78, 0x75113101, + 0xC78, 0x74123101, + 0xC78, 0x73133101, + 0xC78, 0x72143101, + 0xC78, 0x71153101, + 0xC78, 0x70163101, + 0xC78, 0x6F173101, + 0xC78, 0x6E183101, + 0xC78, 0x6D193101, + 0xC78, 0x6C1A3101, + 0xC78, 0x6B1B3101, + 0xC78, 0x6A1C3101, + 0xC78, 0x691D3101, + 0xC78, 0x681E3101, + 0xC78, 0x4B1F3101, + 0xC78, 0x4A203101, + 0xC78, 0x49213101, + 0xC78, 0x48223101, + 0xC78, 0x47233101, + 0xC78, 0x46243101, + 0xC78, 0x45253101, + 0xC78, 0x44263101, + 0xC78, 0x43273101, + 0xC78, 0x42283101, + 0xC78, 0x41293101, + 0xC78, 0x402A3101, + 0xC78, 0x022B3101, + 0xC78, 0x012C3101, + 0xC78, 0x002D3101, + 0xC78, 0x002E3101, + 0xC78, 0x002F3101, + 0xC78, 0x00303101, + 0xC78, 0x00313101, + 0xC78, 0x00323101, + 0xC78, 0x00333101, + 0xC78, 0x00343101, + 0xC78, 0x00353101, + 0xC78, 0x00363101, + 0xC78, 0x00373101, + 0xC78, 0x00383101, + 0xC78, 0x00393101, + 0xC78, 0x003A3101, + 0xC78, 0x003B3101, + 0xC78, 0x003C3101, + 0xC78, 0x003D3101, + 0xC78, 0x003E3101, + 0xC78, 0x003F3101, + 0xC78, 0xFE403101, + 0xC78, 0xFD413101, + 0xC78, 0xFC423101, + 0xC78, 0xFB433101, + 0xC78, 0xFA443101, + 0xC78, 0xF9453101, + 0xC78, 0xF8463101, + 0xC78, 0xF7473101, + 0xC78, 0xF6483101, + 0xC78, 0xF5493101, + 0xC78, 0xF44A3101, + 0xC78, 0xF34B3101, + 0xC78, 0xF24C3101, + 0xC78, 0xF14D3101, + 0xC78, 0xF04E3101, + 0xC78, 0xEF4F3101, + 0xC78, 0xEE503101, + 0xC78, 0xED513101, + 0xC78, 0xEC523101, + 0xC78, 0xEB533101, + 0xC78, 0xEA543101, + 0xC78, 0xE9553101, + 0xC78, 0xE8563101, + 0xC78, 0xE7573101, + 0xC78, 0xE6583101, + 0xC78, 0xE5593101, + 0xC78, 0xE45A3101, + 0xC78, 0xE35B3101, + 0xC78, 0xE25C3101, + 0xC78, 0xE15D3101, + 0xC78, 0xE05E3101, + 0xC78, 0x865F3101, + 0xC78, 0x85603101, + 0xC78, 0x84613101, + 0xC78, 0x83623101, + 0xC78, 0x82633101, + 0xC78, 0x81643101, + 0xC78, 0x80653101, + 0xC78, 0x80663101, + 0xC78, 0x80673101, + 0xC78, 0x80683101, + 0xC78, 0x80693101, + 0xC78, 0x806A3101, + 0xC78, 0x806B3101, + 0xC78, 0x806C3101, + 0xC78, 0x806D3101, + 0xC78, 0x806E3101, + 0xC78, 0x806F3101, + 0xC78, 0x80703101, + 0xC78, 0x80713101, + 0xC78, 0x80723101, + 0xC78, 0x80733101, + 0xC78, 0x80743101, + 0xC78, 0x80753101, + 0xC78, 0x80763101, + 0xC78, 0x80773101, + 0xC78, 0x80783101, + 0xC78, 0x80793101, + 0xC78, 0x807A3101, + 0xC78, 0x807B3101, + 0xC78, 0x807C3101, + 0xC78, 0x807D3101, + 0xC78, 0x807E3101, + 0xC78, 0x807F3101, + 0xC78, 0xEF402001, + 0xC78, 0xEF412001, + 0xC78, 0xEF422001, + 0xC78, 0xEF432001, + 0xC78, 0xEF442001, + 0xC78, 0xEF452001, + 0xC78, 0xEF462001, + 0xC78, 0xEF472001, + 0xC78, 0xEF482001, + 0xC78, 0xEF492001, + 0xC78, 0xEF4A2001, + 0xC78, 0xEF4B2001, + 0xC78, 0xEF4C2001, + 0xC78, 0xEF4D2001, + 0xC78, 0xEF4E2001, + 0xC78, 0xEF4F2001, + 0xC78, 0xEF502001, + 0xC78, 0xEF512001, + 0xC78, 0xEF522001, + 0xC78, 0xEF532001, + 0xC78, 0xEF542001, + 0xC78, 0xEF552001, + 0xC78, 0xEF562001, + 0xC78, 0xEF572001, + 0xC78, 0xEF582001, + 0xC78, 0xEF592001, + 0xC78, 0xEF5A2001, + 0xC78, 0xEF5B2001, + 0xC78, 0xEF5C2001, + 0xC78, 0xEF5D2001, + 0xC78, 0xEF5E2001, + 0xC78, 0xEF5F2001, + 0xC78, 0xEF602001, + 0xC78, 0xEE612001, + 0xC78, 0xED622001, + 0xC78, 0xEC632001, + 0xC78, 0xEB642001, + 0xC78, 0xEA652001, + 0xC78, 0xE9662001, + 0xC78, 0xE8672001, + 0xC78, 0xCB682001, + 0xC78, 0xCA692001, + 0xC78, 0xC96A2001, + 0xC78, 0xC86B2001, + 0xC78, 0xC76C2001, + 0xC78, 0xC66D2001, + 0xC78, 0xC56E2001, + 0xC78, 0xC46F2001, + 0xC78, 0xC3702001, + 0xC78, 0xC2712001, + 0xC78, 0xC1722001, + 0xC78, 0xC0732001, + 0xC78, 0x82742001, + 0xC78, 0x81752001, + 0xC78, 0x80762001, + 0xC78, 0x80772001, + 0xC78, 0x80782001, + 0xC78, 0x80792001, + 0xC78, 0x807A2001, + 0xC78, 0x807B2001, + 0xC78, 0x807C2001, + 0xC78, 0x807D2001, + 0xC78, 0x807E2001, + 0xC78, 0x807F2001, + 0xC78, 0xFA001101, + 0xC78, 0xF9011101, + 0xC78, 0xF8021101, + 0xC78, 0xF7031101, + 0xC78, 0xF6041101, + 0xC78, 0xF5051101, + 0xC78, 0xF4061101, + 0xC78, 0xD7071101, + 0xC78, 0xD6081101, + 0xC78, 0xD5091101, + 0xC78, 0xD40A1101, + 0xC78, 0x970B1101, + 0xC78, 0x960C1101, + 0xC78, 0x950D1101, + 0xC78, 0x940E1101, + 0xC78, 0x930F1101, + 0xC78, 0x92101101, + 0xC78, 0x91111101, + 0xC78, 0x90121101, + 0xC78, 0x8F131101, + 0xC78, 0x8E141101, + 0xC78, 0x8D151101, + 0xC78, 0x8C161101, + 0xC78, 0x8B171101, + 0xC78, 0x8A181101, + 0xC78, 0x89191101, + 0xC78, 0x881A1101, + 0xC78, 0x871B1101, + 0xC78, 0x861C1101, + 0xC78, 0x851D1101, + 0xC78, 0x841E1101, + 0xC78, 0x831F1101, + 0xC78, 0x82201101, + 0xC78, 0x81211101, + 0xC78, 0x80221101, + 0xC78, 0x43231101, + 0xC78, 0x42241101, + 0xC78, 0x41251101, + 0xC78, 0x04261101, + 0xC78, 0x03271101, + 0xC78, 0x02281101, + 0xC78, 0x01291101, + 0xC78, 0x002A1101, + 0xC78, 0xC42B1001, + 0xC78, 0xC32C1001, + 0xC78, 0xC22D1001, + 0xC78, 0xC12E1001, + 0xC78, 0xC02F1001, + 0xC78, 0x85301001, + 0xC78, 0x84311001, + 0xC78, 0x83321001, + 0xC78, 0x82331001, + 0xC78, 0x81341001, + 0xC78, 0x80351001, + 0xC78, 0x05361001, + 0xC78, 0x04371001, + 0xC78, 0x03381001, + 0xC78, 0x02391001, + 0xC78, 0x013A1001, + 0xC78, 0x003B1001, + 0xC78, 0x003C1001, + 0xC78, 0x003D1001, + 0xC78, 0x003E1001, + 0xC78, 0x003F1001, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +ODM_ReadAndConfig_MP_8723D_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723D_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723D_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8723D(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723D_AGC_TAB(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723D_PHY_REG[] = { + 0x800, 0x80046C00, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x00200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x461F0641, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x07000460, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x004F0201, + 0x880, 0xB2002E12, + 0x884, 0x00000007, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000402, + 0x914, 0x00000300, + 0x920, 0x18C6318C, + 0x924, 0x0000018C, + 0x948, 0x99000000, + 0x94C, 0x00000010, + 0x950, 0x00003800, + 0x954, 0x5A380000, + 0x958, 0x4BC6D87A, + 0x95C, 0x04EB9B79, + 0x96C, 0x00000003, + 0x970, 0x00000000, + 0x974, 0x00000000, + 0x978, 0x00000000, + 0x97C, 0x13000000, + 0x980, 0x00000000, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E20100F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xE82C0001, + 0xA24, 0x64B80C1C, + 0xA28, 0x00008810, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00008900, + 0xA7C, 0x225B0606, + 0xA80, 0x2180FA74, + 0xA84, 0x00200000, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x00000000, + 0xA9C, 0x00020000, + 0xAA0, 0x00000000, + 0xAA8, 0xCA100008, + 0xAAC, 0x01235667, + 0xAB0, 0x00000000, + 0xAB4, 0x20201402, + 0xB2C, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x28800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC48, + 0xC34, 0x31000040, + 0xC38, 0x21688080, + 0xC3C, 0x000016D4, + 0xC40, 0x1F78403F, + 0xC44, 0x00010036, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00015969, + 0xC5C, 0x00310492, + 0xC60, 0x00280A00, + 0xC64, 0x7112848B, + 0xC68, 0x47C074FF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020600DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0xC84, 0x11F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00012000, + 0xCA4, 0xA00000A0, + 0xCA8, 0x85E7C606, + 0xCAC, 0x00000060, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x0010A3D0, + 0xCC4, 0x00000F7D, + 0xCC8, 0x000442D6, + 0xCCC, 0x00000000, + 0xCD0, 0x000001C8, + 0xCD4, 0x001C8000, + 0xCD8, 0x00000100, + 0xCDC, 0x40100000, + 0xCE0, 0x00222222, + 0xCE4, 0x20000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00030740, + 0xD04, 0x40020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC53, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCB979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x88000000, + 0xD3C, 0xC0127343, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x00000038, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000008, + 0xE68, 0x001B25A4, + 0xE6C, 0x01C00014, + 0xE70, 0x01C00016, + 0xE74, 0x02000014, + 0xE78, 0x02000014, + 0xE7C, 0x02000014, + 0xE80, 0x02000014, + 0xE84, 0x01C00014, + 0xE88, 0x02000014, + 0xE8C, 0x01C00014, + 0xED0, 0x01C00014, + 0xED4, 0x01C00014, + 0xED8, 0x01C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0xEE8, 0x21555448, + 0xEEC, 0x03C00014, + 0xF14, 0x00000003, + 0xF00, 0x00100300, + 0xF08, 0x0000800B, + 0xF0C, 0x0000F007, + 0xF10, 0x0000A487, + 0xF1C, 0x80000064, + 0xF38, 0x00030155, + 0xF3C, 0x0000003A, + 0xF4C, 0x13000000, + 0xF50, 0x00000000, + 0xF18, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8723D_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723D_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8723D(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723D_PHY_REG(void) +{ + return 28; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723D_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x32343434, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303032, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x30323234, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26282830 +}; + +void +ODM_ReadAndConfig_MP_8723D_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723D_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8723D(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.h b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.h index 6d890babd1c..a39afb80896 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#if (RTL8723D_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8723D_H -#define __INC_MP_BB_HW_IMG_8723D_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8723D_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8723D_H +#define __INC_MP_BB_HW_IMG_8723D_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.c b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.c index 92e3698d545..375c981aea2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.c @@ -1,4840 +1,4840 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8723d/hal8723d_fw.h" -#endif - - -#if (RTL8723D_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8723D_FW_AP[] = { -0xD1, 0x23, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x05, 0x16, 0x18, 0x17, 0xA0, 0x52, 0x02, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x02, 0x85, 0xAD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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-0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0x22, 0x90, 0x88, 0x34, 0xE0, 0xC4, 0x54, 0x0F, 0x22, -0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, 0xA3, 0x22, 0x2C, 0xC0, -}; -u4Byte ArrayLength_MP_8723D_FW_WoWLAN = 28778; - -#endif - -void -ODM_ReadFirmware_MP_8723D_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723D_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723D_FW_WoWLAN, ArrayLength_MP_8723D_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8723D_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8723d/hal8723d_fw.h" +#endif + + +#if (RTL8723D_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723D_FW_AP[] = { +0xD1, 0x23, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x05, 0x16, 0x18, 0x17, 0xA0, 0x52, 0x02, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x02, 0x85, 0xAD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+0xE0, 0x90, 0x05, 0x73, 0x22, 0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, 0xA3, 0x22, 0x00, 0x82, 0xDC, + +}; +u4Byte ArrayLength_MP_8723D_FW_AP = 21184; + +#endif + +void +ODM_ReadFirmware_MP_8723D_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723D_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723D_FW_AP, ArrayLength_MP_8723D_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8723D_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723D_FW_NIC[] = { +0xD1, 0x23, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x05, 0x16, 0x18, 0x16, 0x12, 0x64, 0x02, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x02, 0x86, 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0xF6, 0x7E, 0x01, +0x02, 0x5F, 0xA6, 0x7F, 0xF5, 0x7E, 0x01, 0x02, 0x5F, 0xA6, 0x7F, 0xF4, 0x7E, 0x01, 0x02, 0x5F, +0xA6, 0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, 0xA3, 0x22, 0x7D, 0x03, 0x7F, 0x02, 0x02, 0x7C, 0x05, +0xFC, 0x2A, +}; +u4Byte ArrayLength_MP_8723D_FW_NIC = 25650; + + +#endif + +void +ODM_ReadFirmware_MP_8723D_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723D_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723D_FW_NIC, ArrayLength_MP_8723D_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8723D_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8723D_FW_WoWLAN[] = { +0xD1, 0x23, 0x30, 0x00, 0x10, 0x00, 0x00, 0x00, 0x05, 0x16, 0x18, 0x17, 0x4A, 0x70, 0x02, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x02, 0x87, 0xD0, 0x00, 0x00, 0x00, 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0x39, 0xE0, 0xB4, 0x0C, 0x09, 0x12, 0x97, 0xD5, 0x30, 0xE0, 0x03, 0x12, 0x79, 0xD4, 0x90, +0x88, 0x39, 0xD1, 0x59, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE0, 0x90, 0x01, 0xBA, 0xF0, 0x90, 0x88, +0x38, 0xE0, 0x90, 0x01, 0xBB, 0xF0, 0x22, 0x90, 0x88, 0x8D, 0x74, 0x18, 0xF0, 0xA3, 0xF0, 0xA3, +0xE4, 0xF0, 0xA3, 0x74, 0x64, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xF0, 0x22, 0xD1, 0xC2, 0x40, +0x40, 0x90, 0x88, 0x50, 0xE0, 0x04, 0xF0, 0x90, 0x88, 0x92, 0xE0, 0xFF, 0x90, 0x88, 0x50, 0xE0, +0xD3, 0x9F, 0x50, 0x2D, 0x90, 0x88, 0x48, 0xE0, 0x04, 0xF0, 0x90, 0x88, 0x3F, 0x12, 0x9F, 0x5F, +0x33, 0x33, 0x33, 0x54, 0xF8, 0xFF, 0x90, 0x88, 0x3E, 0xE0, 0x2F, 0x90, 0x88, 0x4F, 0xF0, 0xFB, +0x90, 0x88, 0x48, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x90, 0x92, 0x98, 0x74, 0x03, 0xF0, 0x12, 0x6E, +0x2F, 0x22, 0x90, 0x88, 0x93, 0xE0, 0xFF, 0x90, 0x88, 0x3F, 0xE0, 0xD3, 0x9F, 0x22, 0xE4, 0xFE, +0x12, 0xA3, 0x99, 0xE4, 0xF0, 0x74, 0x8B, 0x2E, 0x12, 0xA3, 0x91, 0x74, 0xFF, 0xF0, 0x0E, 0xEE, +0xB4, 0xA0, 0xED, 0xE4, 0x90, 0x88, 0x4D, 0xF0, 0x90, 0x88, 0x4C, 0xF0, 0x90, 0x88, 0x50, 0xF0, +0xEF, 0xB4, 0x01, 0x07, 0xA3, 0x74, 0xA0, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0x90, 0x93, 0x08, 0xE0, +0x30, 0xE0, 0x0A, 0x90, 0x01, 0x3B, 0xE0, 0x30, 0xE4, 0x03, 0x12, 0xA7, 0xED, 0x22, 0xF9, 0xE4, +0x3A, 0x8B, 0x45, 0xF5, 0x46, 0x89, 0x47, 0x75, 0x48, 0x04, 0x7B, 0x01, 0x7A, 0x98, 0x79, 0x76, +0x12, 0x69, 0xF5, 0x90, 0x98, 0x70, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x22, 0x90, 0x05, 0x63, 0xE0, +0x90, 0x88, 0x89, 0xF0, 0x90, 0x05, 0x62, 0xE0, 0x90, 0x88, 0x8A, 0xF0, 0x90, 0x05, 0x61, 0xE0, +0x90, 0x88, 0x8B, 0xF0, 0x90, 0x05, 0x60, 0xE0, 0x90, 0x88, 0x8C, 0xF0, 0x90, 0x88, 0x32, 0xE0, +0x44, 0x80, 0xF0, 0x22, 0xFF, 0x90, 0x98, 0x75, 0xF0, 0x7B, 0x01, 0x7A, 0x98, 0x79, 0x76, 0x12, +0x8F, 0x21, 0x90, 0x98, 0x72, 0x12, 0x85, 0xEE, 0xE9, 0x22, 0xE0, 0xFF, 0x24, 0x10, 0xF5, 0x82, +0xE4, 0x34, 0x93, 0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB2, 0xF0, 0x74, 0x15, 0x2F, 0xF5, 0x82, 0xE4, +0x34, 0x93, 0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB3, 0xF0, 0xE0, 0x22, 0xF0, 0xA3, 0xEF, 0xF0, 0x74, +0x02, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0F, 0x33, 0x33, 0x33, 0x54, +0xF8, 0xFF, 0x90, 0x95, 0xEA, 0xE0, 0x22, 0x90, 0x8A, 0x77, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xF5, +0x82, 0x8E, 0x83, 0x02, 0x04, 0x7E, 0x90, 0x88, 0x28, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x88, 0x27, +0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x22, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x22, 0x54, +0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x22, 0x90, 0x88, 0x38, 0xE0, 0x90, 0x98, 0xA0, 0xF0, +0x90, 0x8A, 0x89, 0x22, 0x7D, 0x01, 0x7E, 0x00, 0x7F, 0x10, 0x12, 0x87, 0xAC, 0xEF, 0x22, 0x7F, +0x84, 0x7E, 0x08, 0x12, 0xB7, 0x14, 0x90, 0x99, 0x92, 0x22, 0x90, 0x97, 0x32, 0x12, 0x85, 0xF7, +0x02, 0x02, 0x06, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x22, 0xF0, 0xEE, 0x54, 0x80, +0xFE, 0xEF, 0x54, 0x7F, 0x22, 0x90, 0x97, 0xCA, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x22, 0x90, 0x97, +0xCA, 0xE0, 0xFF, 0xC3, 0x94, 0x06, 0x22, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x87, 0xAC, 0xEF, 0x22, +0x54, 0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0x22, 0x90, 0x88, 0x34, 0xE0, 0xC4, 0x54, 0x0F, 0x22, +0x90, 0x05, 0x00, 0x74, 0x1C, 0xF0, 0xA3, 0x22, 0x2C, 0xC0, +}; +u4Byte ArrayLength_MP_8723D_FW_WoWLAN = 28778; + +#endif + +void +ODM_ReadFirmware_MP_8723D_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8723D_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8723D_FW_WoWLAN, ArrayLength_MP_8723D_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8723D_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.h b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.h index 5fef7fbdbe2..7aff7555139 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8723D_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8723D_H -#define __INC_MP_FW_HW_IMG_8723D_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723D_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723D_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8723D_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8723D_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8723D_H +#define __INC_MP_FW_HW_IMG_8723D_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723D_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723D_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8723D_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.c b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.c index d9ab2c6abaf..877169707be 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.c @@ -1,296 +1,296 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723D_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8723D_MAC_REG[] = { - 0x020, 0x00000013, - 0x02F, 0x00000010, - 0x077, 0x00000007, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000028, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000028, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000C, - 0x63F, 0x0000000C, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66A, 0x000000B0, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x765, 0x00000018, - 0x76E, 0x00000004, - 0x7C0, 0x00000038, - 0x7C2, 0x0000000F, - 0x7C3, 0x000000C0, - 0x073, 0x00000004, - 0x7C4, 0x00000077, - 0x07C, 0x00000003, - 0x016, 0x000000B3, - -}; - -void -ODM_ReadAndConfig_MP_8723D_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723D_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723D_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8723D(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723D_MAC_REG(void) -{ - return 28; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723D_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8723D_MAC_REG[] = { + 0x020, 0x00000013, + 0x02F, 0x00000010, + 0x077, 0x00000007, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000028, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000028, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000C, + 0x63F, 0x0000000C, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66A, 0x000000B0, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x765, 0x00000018, + 0x76E, 0x00000004, + 0x7C0, 0x00000038, + 0x7C2, 0x0000000F, + 0x7C3, 0x000000C0, + 0x073, 0x00000004, + 0x7C4, 0x00000077, + 0x07C, 0x00000003, + 0x016, 0x000000B3, + +}; + +void +ODM_ReadAndConfig_MP_8723D_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723D_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723D_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8723D(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723D_MAC_REG(void) +{ + return 28; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.h b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.h index 07a1dd0aacf..8451deb4eb0 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#if (RTL8723D_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8723D_H -#define __INC_MP_MAC_HW_IMG_8723D_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8723D_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8723D_H +#define __INC_MP_MAC_HW_IMG_8723D_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.c b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.c index 0a1b09de427..08b3071c1d4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.c @@ -1,1194 +1,1194 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8723D_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8723D_RadioA[] = { - 0x050, 0x00019000, - 0x000, 0x00010000, - 0x0B1, 0x00054573, - 0x0B4, 0x000508AB, - 0x0B7, 0x00014787, - 0x0B8, 0x000064CB, - 0x01B, 0x00073A40, - 0x051, 0x00038CAF, - 0x052, 0x000FCCA3, - 0x053, 0x00090F38, - 0x054, 0x00011083, - 0x057, 0x000D0000, - 0x08D, 0x00000A1A, - 0x082, 0x00082AAC, - 0x08E, 0x00076940, - 0x08F, 0x00088400, - 0x061, 0x00038CAF, - 0x062, 0x000FCCA3, - 0x063, 0x00090F38, - 0x064, 0x00011083, - 0x067, 0x000D0000, - 0x092, 0x00082AAC, - 0x0EF, 0x00000400, - 0x030, 0x000008CA, - 0x030, 0x000018CF, - 0x030, 0x000028CA, - 0x030, 0x000038CA, - 0x0EF, 0x00000000, - 0x0EE, 0x00000400, - 0x030, 0x000008CA, - 0x030, 0x000018CF, - 0x030, 0x000028CA, - 0x030, 0x000038CA, - 0x0EE, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000000, - 0x03F, 0x0000CCA3, - 0x033, 0x00000001, - 0x03F, 0x0000CCA3, - 0x033, 0x00000002, - 0x03F, 0x0000CCA3, - 0x033, 0x00000003, - 0x03F, 0x0000CCA3, - 0x033, 0x00000004, - 0x03F, 0x0000CCA3, - 0x033, 0x00000005, - 0x03F, 0x0000CCA3, - 0x033, 0x00000006, - 0x03F, 0x0000CCA3, - 0x033, 0x00000007, - 0x03F, 0x0000CCA3, - 0x0EF, 0x00000000, - 0x0EE, 0x00000100, - 0x033, 0x00000000, - 0x03F, 0x0000CCA3, - 0x033, 0x00000001, - 0x03F, 0x0000CCA3, - 0x033, 0x00000002, - 0x03F, 0x0000CCA3, - 0x033, 0x00000003, - 0x03F, 0x0000CCA3, - 0x033, 0x00000004, - 0x03F, 0x0000CCA3, - 0x033, 0x00000005, - 0x03F, 0x0000CCA3, - 0x033, 0x00000006, - 0x03F, 0x0000CCA3, - 0x033, 0x00000007, - 0x03F, 0x0000CCA3, - 0x0EE, 0x00000000, - 0x0EF, 0x00000800, - 0x030, 0x0000002D, - 0x030, 0x0000122C, - 0x030, 0x0000222F, - 0x030, 0x0000326C, - 0x030, 0x0000466B, - 0x030, 0x0000566E, - 0x030, 0x000066EB, - 0x030, 0x000077EC, - 0x030, 0x000087EF, - 0x030, 0x000097F2, - 0x030, 0x0000A7F5, - 0x0EF, 0x00000000, - 0x0EE, 0x00000800, - 0x030, 0x00000001, - 0x030, 0x00001011, - 0x030, 0x00002011, - 0x030, 0x00003013, - 0x030, 0x00004033, - 0x030, 0x00005033, - 0x030, 0x00006037, - 0x030, 0x0000703F, - 0x030, 0x0000803F, - 0x030, 0x0000903F, - 0x030, 0x0000A03F, - 0x0EE, 0x00000000, - 0x082, 0x00083B8C, - 0x0ED, 0x00000008, - 0x030, 0x000030F6, - 0x030, 0x00002004, - 0x030, 0x000010F6, - 0x030, 0x000000F6, - 0x0ED, 0x00000000, - 0x092, 0x00083B8C, - 0x0EC, 0x00000008, - 0x030, 0x000030F6, - 0x030, 0x00002004, - 0x030, 0x000010F6, - 0x030, 0x000000F6, - 0x0EC, 0x00000000, - 0x0EF, 0x00010000, - 0x030, 0x0001C11C, - 0x030, 0x000181F4, - 0x030, 0x00014108, - 0x030, 0x000101E4, - 0x030, 0x0000C11C, - 0x030, 0x000081F4, - 0x030, 0x00004108, - 0x030, 0x000001E4, - 0x0EF, 0x00000000, - 0x0EE, 0x00010000, - 0x030, 0x0001C11C, - 0x030, 0x000181F4, - 0x030, 0x00014108, - 0x030, 0x000101E4, - 0x030, 0x0000C11C, - 0x030, 0x000081F4, - 0x030, 0x00004108, - 0x030, 0x000001E4, - 0x0EE, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000007, - 0x03E, 0x0000005F, - 0x03F, 0x000B3FDB, - 0x033, 0x00000004, - 0x03E, 0x0000005D, - 0x03F, 0x000BFFE0, - 0x033, 0x00000005, - 0x03E, 0x0000005D, - 0x03F, 0x000FBFCE, - 0x033, 0x00000006, - 0x03E, 0x0000005F, - 0x03F, 0x000A7FFB, - 0x0EF, 0x00000000, - 0x0EE, 0x00000002, - 0x030, 0x00000001, - 0x030, 0x00002001, - 0x030, 0x00004001, - 0x030, 0x00007001, - 0x030, 0x00006001, - 0x030, 0x00020001, - 0x030, 0x00022001, - 0x030, 0x00024001, - 0x030, 0x00027001, - 0x030, 0x00026001, - 0x030, 0x00034001, - 0x030, 0x00037001, - 0x030, 0x00036001, - 0x030, 0x00008000, - 0x030, 0x0000A000, - 0x030, 0x0000C000, - 0x030, 0x0000E000, - 0x030, 0x0001C000, - 0x030, 0x0001E000, - 0x0EE, 0x00000000, - 0x0EE, 0x00020000, - 0x0EF, 0x00020000, - 0x030, 0x00000F75, - 0x030, 0x00002F55, - 0x030, 0x00003F75, - 0x0EE, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x00008401, - 0xFFE, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8723D_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8723D_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8723D_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8723D(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8723D_RadioA(void) -{ - return 28; -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -#endif - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -#endif - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -#endif - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8723D_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "30", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "17", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "29", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "29", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "29", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "31", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "31", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "31", - "MKK", "2.4G", "20M", "HT", "1T", "01", "31", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "31", - "MKK", "2.4G", "20M", "HT", "1T", "02", "31", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "31", - "MKK", "2.4G", "20M", "HT", "1T", "03", "31", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "31", - "MKK", "2.4G", "20M", "HT", "1T", "04", "31", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "31", - "MKK", "2.4G", "20M", "HT", "1T", "05", "31", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "31", - "MKK", "2.4G", "20M", "HT", "1T", "06", "31", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "31", - "MKK", "2.4G", "20M", "HT", "1T", "07", "31", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "31", - "MKK", "2.4G", "20M", "HT", "1T", "08", "31", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "31", - "MKK", "2.4G", "20M", "HT", "1T", "09", "31", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "31", - "MKK", "2.4G", "20M", "HT", "1T", "10", "31", - "FCC", "2.4G", "20M", "HT", "1T", "11", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "31", - "MKK", "2.4G", "20M", "HT", "1T", "11", "31", - "FCC", "2.4G", "20M", "HT", "1T", "12", "23", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "31", - "MKK", "2.4G", "20M", "HT", "1T", "12", "31", - "FCC", "2.4G", "20M", "HT", "1T", "13", "13", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "31", - "MKK", "2.4G", "20M", "HT", "1T", "13", "31", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "30", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "30", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "30", - "FCC", "2.4G", "40M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "30", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "30", - "FCC", "2.4G", "40M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "30", - "FCC", "2.4G", "40M", "HT", "1T", "09", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "30", - "FCC", "2.4G", "40M", "HT", "1T", "10", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "30", - "FCC", "2.4G", "40M", "HT", "1T", "11", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "30", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "30", - "MKK", "2.4G", "40M", "HT", "1T", "12", "30", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "30", - "MKK", "2.4G", "40M", "HT", "1T", "13", "30", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", - "MKK", "2.4G", "40M", "HT", "2T", "03", "26", - "FCC", "2.4G", "40M", "HT", "2T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", - "MKK", "2.4G", "40M", "HT", "2T", "04", "26", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", - "MKK", "2.4G", "40M", "HT", "2T", "05", "26", - "FCC", "2.4G", "40M", "HT", "2T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", - "MKK", "2.4G", "40M", "HT", "2T", "06", "26", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", - "MKK", "2.4G", "40M", "HT", "2T", "07", "26", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", - "MKK", "2.4G", "40M", "HT", "2T", "08", "26", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", - "MKK", "2.4G", "40M", "HT", "2T", "09", "26", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", - "MKK", "2.4G", "40M", "HT", "2T", "10", "26", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", - "MKK", "2.4G", "40M", "HT", "2T", "11", "26", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", - "MKK", "2.4G", "40M", "HT", "2T", "12", "26", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", - "MKK", "2.4G", "40M", "HT", "2T", "13", "26", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "30", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "28", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8723D_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8723D_TXPWR_LMT)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8723D_TXPWR_LMT; -#else - u4Byte ArrayLen = sizeof(Array_MP_8723D_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8723D_TXPWR_LMT; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8723D(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TxXtalTrack.TXT -******************************************************************************/ - -s1Byte gDeltaSwingTableXtal_MP_N_TxXtalTrack_8723D[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -s1Byte gDeltaSwingTableXtal_MP_P_TxXtalTrack_8723D[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16}; - -void -ODM_ReadAndConfig_MP_8723D_TxXtalTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_P, gDeltaSwingTableXtal_MP_P_TxXtalTrack_8723D, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_N, gDeltaSwingTableXtal_MP_N_TxXtalTrack_8723D, DELTA_SWINGIDX_SIZE); -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8723D_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8723D_RadioA[] = { + 0x050, 0x00019000, + 0x000, 0x00010000, + 0x0B1, 0x00054573, + 0x0B4, 0x000508AB, + 0x0B7, 0x00014787, + 0x0B8, 0x000064CB, + 0x01B, 0x00073A40, + 0x051, 0x00038CAF, + 0x052, 0x000FCCA3, + 0x053, 0x00090F38, + 0x054, 0x00011083, + 0x057, 0x000D0000, + 0x08D, 0x00000A1A, + 0x082, 0x00082AAC, + 0x08E, 0x00076940, + 0x08F, 0x00088400, + 0x061, 0x00038CAF, + 0x062, 0x000FCCA3, + 0x063, 0x00090F38, + 0x064, 0x00011083, + 0x067, 0x000D0000, + 0x092, 0x00082AAC, + 0x0EF, 0x00000400, + 0x030, 0x000008CA, + 0x030, 0x000018CF, + 0x030, 0x000028CA, + 0x030, 0x000038CA, + 0x0EF, 0x00000000, + 0x0EE, 0x00000400, + 0x030, 0x000008CA, + 0x030, 0x000018CF, + 0x030, 0x000028CA, + 0x030, 0x000038CA, + 0x0EE, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x0000CCA3, + 0x033, 0x00000001, + 0x03F, 0x0000CCA3, + 0x033, 0x00000002, + 0x03F, 0x0000CCA3, + 0x033, 0x00000003, + 0x03F, 0x0000CCA3, + 0x033, 0x00000004, + 0x03F, 0x0000CCA3, + 0x033, 0x00000005, + 0x03F, 0x0000CCA3, + 0x033, 0x00000006, + 0x03F, 0x0000CCA3, + 0x033, 0x00000007, + 0x03F, 0x0000CCA3, + 0x0EF, 0x00000000, + 0x0EE, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x0000CCA3, + 0x033, 0x00000001, + 0x03F, 0x0000CCA3, + 0x033, 0x00000002, + 0x03F, 0x0000CCA3, + 0x033, 0x00000003, + 0x03F, 0x0000CCA3, + 0x033, 0x00000004, + 0x03F, 0x0000CCA3, + 0x033, 0x00000005, + 0x03F, 0x0000CCA3, + 0x033, 0x00000006, + 0x03F, 0x0000CCA3, + 0x033, 0x00000007, + 0x03F, 0x0000CCA3, + 0x0EE, 0x00000000, + 0x0EF, 0x00000800, + 0x030, 0x0000002D, + 0x030, 0x0000122C, + 0x030, 0x0000222F, + 0x030, 0x0000326C, + 0x030, 0x0000466B, + 0x030, 0x0000566E, + 0x030, 0x000066EB, + 0x030, 0x000077EC, + 0x030, 0x000087EF, + 0x030, 0x000097F2, + 0x030, 0x0000A7F5, + 0x0EF, 0x00000000, + 0x0EE, 0x00000800, + 0x030, 0x00000001, + 0x030, 0x00001011, + 0x030, 0x00002011, + 0x030, 0x00003013, + 0x030, 0x00004033, + 0x030, 0x00005033, + 0x030, 0x00006037, + 0x030, 0x0000703F, + 0x030, 0x0000803F, + 0x030, 0x0000903F, + 0x030, 0x0000A03F, + 0x0EE, 0x00000000, + 0x082, 0x00083B8C, + 0x0ED, 0x00000008, + 0x030, 0x000030F6, + 0x030, 0x00002004, + 0x030, 0x000010F6, + 0x030, 0x000000F6, + 0x0ED, 0x00000000, + 0x092, 0x00083B8C, + 0x0EC, 0x00000008, + 0x030, 0x000030F6, + 0x030, 0x00002004, + 0x030, 0x000010F6, + 0x030, 0x000000F6, + 0x0EC, 0x00000000, + 0x0EF, 0x00010000, + 0x030, 0x0001C11C, + 0x030, 0x000181F4, + 0x030, 0x00014108, + 0x030, 0x000101E4, + 0x030, 0x0000C11C, + 0x030, 0x000081F4, + 0x030, 0x00004108, + 0x030, 0x000001E4, + 0x0EF, 0x00000000, + 0x0EE, 0x00010000, + 0x030, 0x0001C11C, + 0x030, 0x000181F4, + 0x030, 0x00014108, + 0x030, 0x000101E4, + 0x030, 0x0000C11C, + 0x030, 0x000081F4, + 0x030, 0x00004108, + 0x030, 0x000001E4, + 0x0EE, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000007, + 0x03E, 0x0000005F, + 0x03F, 0x000B3FDB, + 0x033, 0x00000004, + 0x03E, 0x0000005D, + 0x03F, 0x000BFFE0, + 0x033, 0x00000005, + 0x03E, 0x0000005D, + 0x03F, 0x000FBFCE, + 0x033, 0x00000006, + 0x03E, 0x0000005F, + 0x03F, 0x000A7FFB, + 0x0EF, 0x00000000, + 0x0EE, 0x00000002, + 0x030, 0x00000001, + 0x030, 0x00002001, + 0x030, 0x00004001, + 0x030, 0x00007001, + 0x030, 0x00006001, + 0x030, 0x00020001, + 0x030, 0x00022001, + 0x030, 0x00024001, + 0x030, 0x00027001, + 0x030, 0x00026001, + 0x030, 0x00034001, + 0x030, 0x00037001, + 0x030, 0x00036001, + 0x030, 0x00008000, + 0x030, 0x0000A000, + 0x030, 0x0000C000, + 0x030, 0x0000E000, + 0x030, 0x0001C000, + 0x030, 0x0001E000, + 0x0EE, 0x00000000, + 0x0EE, 0x00020000, + 0x0EF, 0x00020000, + 0x030, 0x00000F75, + 0x030, 0x00002F55, + 0x030, 0x00003F75, + 0x0EE, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x00008401, + 0xFFE, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8723D_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8723D_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8723D_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8723D(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8723D_RadioA(void) +{ + return 28; +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +#endif + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8723D, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +#endif + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723D, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723D[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723D[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723D[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +#endif + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8723D, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8723D_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "17", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "29", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "29", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "29", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "31", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "31", + "MKK", "2.4G", "20M", "HT", "1T", "01", "31", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "31", + "MKK", "2.4G", "20M", "HT", "1T", "02", "31", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "31", + "MKK", "2.4G", "20M", "HT", "1T", "03", "31", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "31", + "MKK", "2.4G", "20M", "HT", "1T", "04", "31", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "31", + "MKK", "2.4G", "20M", "HT", "1T", "05", "31", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "31", + "MKK", "2.4G", "20M", "HT", "1T", "06", "31", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "31", + "MKK", "2.4G", "20M", "HT", "1T", "07", "31", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "31", + "MKK", "2.4G", "20M", "HT", "1T", "08", "31", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "31", + "MKK", "2.4G", "20M", "HT", "1T", "09", "31", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "31", + "MKK", "2.4G", "20M", "HT", "1T", "10", "31", + "FCC", "2.4G", "20M", "HT", "1T", "11", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "31", + "MKK", "2.4G", "20M", "HT", "1T", "11", "31", + "FCC", "2.4G", "20M", "HT", "1T", "12", "23", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "31", + "MKK", "2.4G", "20M", "HT", "1T", "12", "31", + "FCC", "2.4G", "20M", "HT", "1T", "13", "13", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "31", + "MKK", "2.4G", "20M", "HT", "1T", "13", "31", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "30", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "30", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "30", + "FCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "FCC", "2.4G", "40M", "HT", "1T", "09", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "30", + "FCC", "2.4G", "40M", "HT", "1T", "10", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "30", + "FCC", "2.4G", "40M", "HT", "1T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "30", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "30", + "MKK", "2.4G", "40M", "HT", "1T", "12", "30", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "30", + "MKK", "2.4G", "40M", "HT", "1T", "13", "30", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8723D_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8723D_TXPWR_LMT)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8723D_TXPWR_LMT; +#else + u4Byte ArrayLen = sizeof(Array_MP_8723D_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8723D_TXPWR_LMT; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8723D(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TxXtalTrack.TXT +******************************************************************************/ + +s1Byte gDeltaSwingTableXtal_MP_N_TxXtalTrack_8723D[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +s1Byte gDeltaSwingTableXtal_MP_P_TxXtalTrack_8723D[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16}; + +void +ODM_ReadAndConfig_MP_8723D_TxXtalTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8723D\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_P, gDeltaSwingTableXtal_MP_P_TxXtalTrack_8723D, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableXtal_N, gDeltaSwingTableXtal_MP_N_TxXtalTrack_8723D, DELTA_SWINGIDX_SIZE); +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.h b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.h index 0f9362d4272..1492bb3bc7f 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halhwimg8723d_rf.h @@ -1,89 +1,89 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.23*/ -#if (RTL8723D_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8723D_H -#define __INC_MP_RF_HW_IMG_8723D_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_TXPWR_LMT(void); - -/****************************************************************************** -* TxXtalTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8723D_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8723D_TxXtalTrack(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8723D_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8723D_H +#define __INC_MP_RF_HW_IMG_8723D_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_TXPWR_LMT(void); + +/****************************************************************************** +* TxXtalTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8723D_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8723D_TxXtalTrack(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.c b/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.c index 98deb4dc661..dd743806046 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.c +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.c @@ -1,4085 +1,4085 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//#include "Mp_Precomp.h" -#include "../phydm_precomp.h" - - -#if (RTL8723D_SUPPORT == 1) - -/*---------------------------Define Local Constant---------------------------*/ -/*IQK*/ -#define IQK_DELAY_TIME_8723D 10 - -/* 2010/04/25 MH Define the max tx power tracking tx agc power.*/ -#define ODM_TXPWRTRACK_MAX_IDX_8723D 6 - -#define PATH_S1 0 -#define IDX_0xC94 0 -#define IDX_0xC80 1 -#define IDX_0xC4C 2 - -#define IDX_0xC14 0 -#define IDX_0xCA0 1 - - -#define PATH_S0 1 -#define IDX_0xCD0 0 -#define IDX_0xCD4 1 - -#define IDX_0xCD8 0 -#define IDX_0xCDC 1 - -#define KEY 0 -#define VAL 1 - - - -/*---------------------------Define Local Constant---------------------------*/ - - -/* Tx Power Tracking*/ - - -void setIqkMatrix_8723D( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) - { - s4Byte ele_A = 0, ele_D = 0, ele_C = 0, value32, tmp; - s4Byte ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0; - - if (OFDM_index >= OFDM_TABLE_SIZE) - OFDM_index = OFDM_TABLE_SIZE-1; - else if (OFDM_index < 0) - OFDM_index = 0; - - if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - - /* new element D */ - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - ele_D_ext = (((IqkResult_X * ele_D)>>7)&0x01); - /* new element A */ - if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - ele_A_ext = ((IqkResult_X * ele_D)>>7) & 0x1; - /* new element C */ - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - ele_C_ext = ((IqkResult_Y * ele_D)>>7) & 0x1; - - switch (RFPath) { - case ODM_RF_PATH_A: - /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */ - /* write 0xc80 */ - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - /* write 0xc94 */ - value32 = (ele_C & 0x000003C0) >> 6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - /* write 0xc4c */ - value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29); - value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28))) | value32; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - - case ODM_RF_PATH_B: - /*wirte new elements A, C, D to regCd0 and regCd4, element B is always 0*/ - value32 = ele_D; - ODM_SetBBReg(pDM_Odm, 0xCd4, 0x007FE000, value32); - - value32 = ele_C; - ODM_SetBBReg(pDM_Odm, 0xCd4, 0x000007FE, value32); - - value32 = ele_A; - ODM_SetBBReg(pDM_Odm, 0xCd0, 0x000007FE, value32); - - ODM_SetBBReg(pDM_Odm, 0xCd4, BIT12, ele_D_ext); - ODM_SetBBReg(pDM_Odm, 0xCd0, BIT0, ele_A_ext); - ODM_SetBBReg(pDM_Odm, 0xCd4, BIT0, ele_C_ext); - break; - default: - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28)); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); - break; - - case ODM_RF_PATH_B: - /*image S1:c80 to S0:Cd0 and Cd4*/ - ODM_SetBBReg(pDM_Odm, 0xcd0, 0x000007FE, OFDMSwingTable_New[OFDM_index]&0x000003FF); - ODM_SetBBReg(pDM_Odm, 0xcd0, 0x0007E000, (OFDMSwingTable_New[OFDM_index]&0x0000FC00)>>10); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x0000007E, (OFDMSwingTable_New[OFDM_index]&0x003F0000)>>16); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x007FE000, (OFDMSwingTable_New[OFDM_index]&0xFFC00000)>>22); - - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x00000780, 0x00); - - ODM_SetBBReg(pDM_Odm, 0xcd4, BIT12, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, BIT0, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd0, BIT0, 0x0); - break; - default: - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n", - (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)ele_A_ext, (u4Byte)ele_C_ext, (u4Byte)ele_D_ext)); - } - -VOID -setCCKFilterCoefficient_8723D( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[CCKSwingIndex]); -} - -void DoIQK_8723D( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - u4Byte bIsBtEnable; - - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - -#if (MP_DRIVER != 1) - - bIsBtEnable = ODM_GetMACReg(pDM_Odm, 0xa8, bMaskDWord) & BIT17; - - if (bIsBtEnable) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Skip IQK because BT is enable\n")); - return; - } - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Do IQK because BT is disable\n")); -#endif - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate_8723D(pDM_Odm, FALSE); -#else - PHY_IQCalibrate_8723D(Adapter, FALSE); -#endif - -} - -/*----------------------------------------------------------------------------- - * Function: ODM_TxPwrTrackSetPwr_8723D() - * - * Overview: 8723D change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID, -#else - IN PDM_ODM_T pDM_VOID, -#endif - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte PwrTrackingLimit_OFDM = 30; - u1Byte PwrTrackingLimit_CCK = 40; - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#else - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - if (!pMgntInfo->ForcedDataRate) { - if (pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } else { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } -#endif -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (pDM_Odm->mp_mode == TRUE) { /*CE MP*/ - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - } else { /*CE normal*/ - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (pDM_Odm->TxRate != 0xFF) -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723DA\n")); - - if (TxRate != 0xFF) { - /*CCK*/ - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || TxRate == MGN_11M) - PwrTrackingLimit_CCK = 40; - /*OFDM*/ - else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) - PwrTrackingLimit_OFDM = 36; - else if (TxRate == MGN_54M) - PwrTrackingLimit_OFDM = 34; - - /* HT*/ - else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) - PwrTrackingLimit_OFDM = 38; - else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) - PwrTrackingLimit_OFDM = 36; - else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) - PwrTrackingLimit_OFDM = 34; - - else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) - PwrTrackingLimit_OFDM = 38; - else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) - PwrTrackingLimit_OFDM = 36; - else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) - PwrTrackingLimit_OFDM = 34; - - else - PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30 */ - } - - if (Method == TXAGC) { - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr_8723D CH=%d\n", *(pDM_Odm->pChannel))); - - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - -#if (MP_DRIVER != 1) - /*PHY_SetTxPowerLevelByPath8723D(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function - //PHY_SetTxPowerLevel8723D(pDM_Odm->Adapter, *pDM_Odm->pChannel);*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - if (RFPath == ODM_RF_PATH_A) { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15 ); - } else { - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15 ); - } -#else - - if (RFPath == ODM_RF_PATH_A) { - /*CCK Path S1*/ - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - /*OFDM Path S1*/ - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); - TxAGC = ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - } else if (RFPath == ODM_RF_PATH_B) { - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B]; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: CCK Tx-rf(B) Power = 0x%x\n", pwr)); - - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); - TxAGC = ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); - RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); - } -#endif - -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - /*PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));*/ -#endif - - } else if (Method == BBSWING) { - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, pRFCalibrateInfo->Remnant_CCKSwingIdx=%d RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - /* Adjust BB swing by OFDM IQ matrix */ - if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) - Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; - else if (Final_OFDM_Swing_Index < 0) - Final_OFDM_Swing_Index = 0; - - if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE_8723D) - Final_CCK_Swing_Index = CCK_TABLE_SIZE_8723D-1; - else if (pRFCalibrateInfo->BbSwingIdxCck < 0) - Final_CCK_Swing_Index = 0; - - setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - - setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - setCCKFilterCoefficient_8723D(pDM_Odm, Final_CCK_Swing_Index); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_CCK_Swing_Index=%d\n", Final_CCK_Swing_Index)); - - } else if (Method == MIX_MODE) { - #if (MP_DRIVER == 1) - u4Byte TxAGC = 0; /*add by Mingzhi.Guo 2015-04-10*/ - s4Byte pwr = 0; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) { - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*CCK Follow Path-A and lower CCK index means higher power.*/ - - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM);*/ - /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - /*Set TxAGC Page C{};*/ - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM);*/ - /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); - setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - /*Set TxAGC Page C{};*/ - /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15 );*/ - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } -#if (MP_DRIVER == 1) - if ((pDM_Odm->mp_mode) == 1) { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM); - - if (pwr > 0x3F) - pwr = 0x3F; - else if (pwr < 0) - pwr = 0; - - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - - } else -#endif - { - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] ; - - if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - /* Adjust BB swing by CCK filter coefficient*/ - ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[PwrTrackingLimit_CCK]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - /*Set TxAGC Page C{};*/ - /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK);*/ - - } else if (Final_CCK_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); - - ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; - - - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK);*/ - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); - - ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); - - /* if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) {*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - - - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK );*/ - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); - } -#if (MP_DRIVER == 1) - if ((pDM_Odm->mp_mode) == 1) { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1); - pwr += pRFCalibrateInfo->Remnant_CCKSwingIdx-pRFCalibrateInfo->Modify_TxAGC_Value_CCK; - - if (pwr > 0x3F) - pwr = 0x3F; - else if (pwr < 0) - pwr = 0; - - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723D: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - } else -#endif - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); - - pRFCalibrateInfo->Modify_TxAGC_Value_CCK = pRFCalibrateInfo->Remnant_CCKSwingIdx; - } -#if 0 - if (RFPath == ODM_RF_PATH_B) { - if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; - - setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else if (Final_OFDM_Swing_Index < 0) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; - - setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } else { - setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], - pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } -#if (MP_DRIVER == 1) - if ((pDM_Odm->mp_mode) == 1) { - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_B] - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM); - - if (pwr > 0x3F) - pwr = 0x3F; - else if (pwr < 0) - pwr = 0; - - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723D: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); - - } else -#endif - { - - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_B] ; - } -#endif -} else { - return; - } -} - -VOID -GetDeltaSwingTable_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID, -#else - IN PDM_ODM_T pDM_Odm, -#endif - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -VOID -GetDeltaSwingXtalTable_8723D( - PVOID pDM_VOID, - ps1Byte *TemperatureUP_Xtal, - ps1Byte *TemperatureDOWN_Xtal -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - *TemperatureUP_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_P; - *TemperatureDOWN_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_N; -} - - - -VOID -ODM_TxXtalTrackSetXtal_8723D( - PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - s1Byte CrystalCap; - - - CrystalCap = pHalData->CrystalCap & 0x3F; - CrystalCap = CrystalCap + pRFCalibrateInfo->XtalOffset; - - if (CrystalCap < 0) - CrystalCap = 0; - else if (CrystalCap > 63) - CrystalCap = 63; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("CrystalCap(%d)= pHalData->CrystalCap(%d) + pRFCalibrateInfo->XtalOffset(%d)\n", CrystalCap, pHalData->CrystalCap, pRFCalibrateInfo->XtalOffset)); - - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("CrystalCap(0x2c) 0x%X\n", ODM_GetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000))); - -} - -void ConfigureTxpowerTrack_8723D( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE_8723D; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723D; - pConfig->RfPathCount = MAX_PATH_NUM_8723D; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723D; - pConfig->DoIQK = DoIQK_8723D; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723D; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723D; - pConfig->GetDeltaSwingXtalTable = GetDeltaSwingXtalTable_8723D; - pConfig->ODM_TxXtalTrackSetXtal = ODM_TxXtalTrackSetXtal_8723D; -} - - -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 - -u1Byte -phy_PathS1_IQK_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathS0 - ) -{ - u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEA4*/; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 TXIQK!!\n")); - /*save RF path*/ - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 TXIQK = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000000); - - /*IQK setting*/ - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /* --- \A7\EF\BCgTXIQK mode table ---//*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00004); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xBFFE0); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x08008c0c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214019f); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160200); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /*PA, PAD setting*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x600, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x1E0, 0x3); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8d, 0x1F, 0xf); - - /*LOK setting added for 8723D*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x10, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x54, 0x1, 0x1); -#if 1 - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe0d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x60d); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - /*One shot, Path S1 LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /* delay x ms */ - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /*PA/PAD controlled by 0x0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - - /* Check failed*/ - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 TXIQK FAIL\n")); - - - return result; - - } - -u1Byte -phy_PathS1_RxIQK_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathS0 - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 RXIQK Step1!!\n")); - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000000); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 RXIQK1 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6))); */ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - /*IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - /*modify RXIQK mode table*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00006); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xa7ffb); - - /*---------PA/PAD=0----------*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x600, 0x0); -#if 1 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe0d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x60d); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - /*One shot, Path S1 LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /*delay x ms*/ - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - - - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - tmp = (regE9C & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 RXIQK STEP1 FAIL\n")); -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - return result; - } - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 RXIQK STEP2!!\n")); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 RXIQK2 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6))); */ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); - - - /*modify RXIQK mode table*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00007); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xb3fdb); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /* PA/PAD controlled by 0x0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - - tmp = (regEAC & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36) && - (((regEA4 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 RXIQK STEP2 FAIL\n")); - - - return result; -} - - -u1Byte -phy_PathS0_IQK_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEA4, regEAC, regE94, regE9C, regE94_S0, regE9C_S0, regEA4_S0, regEAC_S0, tmp, Path_SEL_BB; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 TXIQK!\n")); - - - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000280); /*10 od 0x948 0x1 [7] ; WL:S1 to S0;BT:S0 to S1;*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 TXIQK = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /*modify TXIQK mode table*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00004); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xBFFE0); - - /*path-A IQK setting*/ - ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x08008c0c); - ODM_SetBBReg(pDM_Odm, 0xe34, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, 0xe38, bMaskDWord, 0x8214018a); - ODM_SetBBReg(pDM_Odm, 0xe3c, bMaskDWord, 0x28160200); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - /*LO calibration setting*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - /*PA, PAD setting*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x600, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x1E0, 0x3); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8d, 0x1F, 0xf); - - /*LOK setting added for 8723D*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, 0x10, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x1, 0x1); - -#if 1 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe6d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x66d); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - - - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - /*One shot, Path S1 LOK & IQK*/ - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - /*delay x ms*/ - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - /*PA/PAD controlled by 0x0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - - /* Check failed*/ - regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n", regE94_S0, regE9C_S0)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - if (!(regEAC_S0 & BIT28) && - (((regE94_S0 & 0x03FF0000)>>16) != 0x142) && - (((regE9C_S0 & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 TXIQK FAIL\n")); - - return result; -} - - - -u1Byte -phy_PathS0_RxIQK_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathS0 - ) -{ - u4Byte regE94, regE9C, regEA4, regEAC, regE94_S0, regE9C_S0, regEA4_S0, regEAC_S0, tmp, u4tmp, Path_SEL_BB; - u1Byte result = 0x00, Ktime; - u4Byte originalPath, originalGNT; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 RxIQK Step1!!\n")); - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000280); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 RXIQK1 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00006); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xa7ffb); - - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x600, 0x0); - -#if 1 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe6d); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x66d); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - - regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regE94_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - regE9C_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n", regE94_S0, regE9C_S0)); - /*monitor image power before & after IQK*/ - ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); - - - tmp = (regE9C_S0 & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC_S0 & BIT28) && - (((regE94_S0 & 0x03FF0000)>>16) != 0x142) && - (((regE9C_S0 & 0x03FF0000)>>16) != 0x42)) - - result |= 0x01; - else { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 RXIQK STEP1 FAIL\n")); -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - return result; - } - - u4tmp = 0x80007C00 | (regE94_S0&0x3FF0000) | ((regE9C_S0&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40_s0 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S0 RXIQK STEP2!!\n\n")); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 RXIQK2 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); - - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00007); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xb3fdb); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); - /*enter IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); - ODM_delay_ms(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); - - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - - /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ - Ktime = 0; - while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { - ODM_delay_ms(1); - Ktime++; - } - -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - /*reload RF path*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); - - /*leave IQK mode*/ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); - - regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - regEA4_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4_s0 = 0x%x, 0xeac_s0 = 0x%x\n", regEA4_S0, regEAC_S0)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0_s0(before IQK)= 0x%x, 0xea8_s0(afer IQK) = 0x%x\n", - ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); - - - tmp = (regEAC_S0 & 0x03FF0000)>>16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(regEAC_S0 & BIT27) && /*if Tx is OK, check whether Rx is OK*/ - (((regEA4_S0 & 0x03FF0000)>>16) != 0x132) && - (((regEAC_S0 & 0x03FF0000)>>16) != 0x36) && - (((regEA4_S0 & 0x03FF0000)>>16) < 0x11a) && - (((regEA4_S0 & 0x03FF0000)>>16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 RXIQK STEP2 FAIL\n")); - - - return result; -} - - -VOID -_PHY_PathS1FillIQKMatrix_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) - { - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x, Oldval_1 0x%x\n", X, TX1_A, Oldval_1)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_1 >> 7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_1 >> 7) & 0x1)); - - if (bTxOnly) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathS1FillIQKMatrix_8723D only Tx OK\n")); - return; - } - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (RTL_ABS(reg , 0x100) >= 16) - reg = 0x100; -#endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); -/* -10 os 7201 10 -10 id ea4 [25:16] p -10 os 7202 10 -10 od c14 VarFromTmp [9:0] p - -10 os 7201 11 -10 id eac [25:22] p -10 os 7202 11 -10 od ca0 VarFromTmp [31:28] p - -10 os 7201 12 -10 id eac [21:16] p -10 os 7202 12 -10 od c14 VarFromTmp [15:10] p -*/ - } - } - -VOID -_PHY_PathS0FillIQKMatrix_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); - - if (final_candidate == 0xFF) - return; - - else if (bIQKOK) { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord) >> 13) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, 0xcd0, 0x7FE, TX0_A); - - ODM_SetBBReg(pDM_Odm, 0xcd0, BIT(0), ((X * Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x7FE, (TX0_C & 0x3FF)); - - ODM_SetBBReg(pDM_Odm, 0xcd4, BIT(0), ((Y * Oldval_0>>7) & 0x1)); - - if (bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, 0xcd8, 0x3FF, reg); - - reg = result[final_candidate][7]; - ODM_SetBBReg(pDM_Odm, 0xcd8, 0x003FF000, reg); -/* -10 os 7201 10 -10 id ea4 [25:16] p -10 os 7202 10 -10 od cd8 VarFromTmp [9:0] p - -10 os 7201 11 -10 id eac [25:16] p -10 os 7202 11 -10 od cd8 VarFromTmp [21:12] p - RegE94_S1 = result[i][0]; - RegE9C_S1 = result[i][1]; - RegEA4_S1 = result[i][2]; - RegEAC_S1 = result[i][3]; - RegE94_S0 = result[i][4]; - RegE9C_S0 = result[i][5]; - RegEA4_S0 = result[i][6]; - RegEAC_S0 = result[i][7]; -*/ - } -} -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ -/* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } -*/ - return TRUE; -} -#endif - -VOID -_PHY_SaveADDARegisters_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - - for (i = 0 ; i < RegisterNum ; i++) { - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID -_PHY_SaveMACRegisters_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID -_PHY_ReloadADDARegisters_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for (i = 0 ; i < RegiesterNum; i++) { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID -_PHY_ReloadMACRegisters_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID -_PHY_PathADDAOn_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - pathOn = isPathAOn ? 0x03c00016 : 0x03c00016; - - if (FALSE == is2T) { - pathOn = 0x03c00016; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x03c00016); - } else { - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); - } - - for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) { - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID -_PHY_MACSettingCalibration_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - -/* - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); -*/ - - /*ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f);*/ - /*ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15);*/ - /*ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00);*/ - - ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); - - - -} - -VOID -_PHY_PathAStandBy_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-S1 standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); -/* ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID -_PHY_PathBStandBy_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-S0 standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - - -VOID -_PHY_PIModeSwitch_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN -phy_SimularityCompare_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; - BOOLEAN bResult = TRUE; -/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -//#else*/ - BOOLEAN is2T = TRUE; -/*#endif*/ - - s4Byte tmp1 = 0,tmp2 = 0; - - if (is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8723D c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for (i = 0; i < bound; i++) { - - if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { - if ((result[c1][i] & 0x00000200) != 0) - tmp1 = result[c1][i] | 0xFFFFFC00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i] & 0x00000200) != 0) - tmp2 = result[c2][i] | 0xFFFFFC00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); - - if ((i == 2 || i == 6) && !SimularityBitMap) { - if (result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1<odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte i; - u1Byte PathS1_OK, PathS0_OK; - u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); - u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting - }; - u4Byte cnt_IQKFail = 0; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) - u4Byte retryCount = 2; -#else -#if MP_DRIVER - const u4Byte retryCount = 9; -#else - const u4Byte retryCount = 2; -#endif -#endif - - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) -#ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - retryCount = 9; -#endif -#endif - - - if (t == 0) { - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_8723D(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - _PHY_SaveADDARegisters_8723D(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - _PHY_SaveADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for 1T1R_S0/S1 for %d times\n", t)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, TRUE, is2T); -#else - _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, TRUE, is2T); -#endif - - -/* - if(t==0) - { - pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PIModeSwitch_8723D(pAdapter, TRUE); -#else - _PHY_PIModeSwitch_8723D(pDM_Odm, TRUE); -#endif - } -*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#else - _PHY_MACSettingCalibration_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); -#endif - - /*BB setting*/ - /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05611); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x25204200); - - /*IQ calibration setting*/ - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); */ - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - -if (is2T) { - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathBStandBy_8723D(pAdapter); - - - _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, FALSE, is2T); -#else - _PHY_PathBStandBy_8723D(pDM_Odm); - - - _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif - } - - -#if 1 - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathS1_OK = phy_PathS1_IQK_8723D(pAdapter, is2T); -#else - PathS1_OK = phy_PathS1_IQK_8723D(pDM_Odm, is2T); -#endif - - if (PathS1_OK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Tx IQK Success!!\n")); - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Tx IQK Fail!!\n")); - result[t][0] = 0x100; - result[t][1] = 0x0; - cnt_IQKFail++; - } -#if 0 - else if (i == (retryCount-1) && PathS1_OK == 0x01) - { - RT_DISP(FINIT, INIT_IQK, ("Path S1 IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } -#endif - - -#if 1 - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathS1_OK = phy_PathS1_RxIQK_8723D(pAdapter, is2T); -#else - PathS1_OK = phy_PathS1_RxIQK_8723D(pDM_Odm, is2T); -#endif - if (PathS1_OK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Rx IQK Success!!\n")); - result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Rx IQK Fail!!\n")); - result[t][2] = 0x100; - result[t][3] = 0x0; - cnt_IQKFail++; - } - } - - if (0x00 == PathS1_OK) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 IQK failed!!\n")); - } - -#endif - - if (is2T) { - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_PathAStandBy_8723D(pAdapter); - - - _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, FALSE, is2T); -#else - _PHY_PathAStandBy_8723D(pDM_Odm); - - - _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, FALSE, is2T); -#endif - - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - -#if 1 - for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathS0_OK = phy_PathS0_IQK_8723D(pAdapter); -#else - PathS0_OK = phy_PathS0_IQK_8723D(pDM_Odm); -#endif - - if (PathS0_OK == 0x01) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Tx IQK Success!!\n")); - result[t][4] = (ODM_GetBBReg(pDM_Odm, 0xe94, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (ODM_GetBBReg(pDM_Odm, 0xe9c, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Tx IQK Fail!!\n")); - result[t][4] = 0x100; - result[t][5] = 0x0; - cnt_IQKFail++; - } -#if 0 - else if (i == (retryCount-1) && PathS1_OK == 0x01) - { - RT_DISP(FINIT, INIT_IQK, ("Path S0 IQK Only Tx Success!!\n")); - - result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } -#endif - } -#endif - - -#if 1 - -for (i = 0 ; i < retryCount ; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PathS0_OK = phy_PathS0_RxIQK_8723D(pAdapter, is2T); -#else - PathS0_OK = phy_PathS0_RxIQK_8723D(pDM_Odm, is2T); -#endif - if (PathS0_OK == 0x03) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Rx IQK Success!!\n")); -/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ -/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ - result[t][6] = (ODM_GetBBReg(pDM_Odm, 0xea4, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (ODM_GetBBReg(pDM_Odm, 0xeac, bMaskDWord)&0x3FF0000)>>16; - break; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Rx IQK Fail!!\n")); - result[t][6] = 0x100; - result[t][7] = 0x0; - cnt_IQKFail++; - } - } - - - - if (0x00 == PathS0_OK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 IQK failed!!\n")); - -#endif - } - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (t != 0) { - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - - _PHY_ReloadADDARegisters_8723D(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#else - - _PHY_ReloadADDARegisters_8723D(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - - /* Reload MAC parameters*/ - _PHY_ReloadMACRegisters_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - - _PHY_ReloadADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); -#endif - - - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); - if (is2T) { - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); - ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); - } - - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - - } - - pDM_Odm->nIQK_Cnt++; - - if (cnt_IQKFail == 0) - pDM_Odm->nIQK_OK_Cnt++; - else - pDM_Odm->nIQK_Fail_Cnt = pDM_Odm->nIQK_Fail_Cnt + cnt_IQKFail; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723D() <==\n")); - -} - - -VOID -phy_LCCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal, cnt; -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; -#endif - - - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if ((tmpReg & 0x70) != 0) - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); - else - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); - - /*backup RF0x18*/ - - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - - /*Start LCK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - ODM_delay_ms(10); - } - - /* Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - /*Restore original situation*/ - if ((tmpReg & 0x70) != 0) - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - else - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); -} - - -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; -/* u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];*/ - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8723D() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if (!is2T) - pathbound = 1; - - - -/* Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.*/ -#if MP_DRIVER != 1 - return; -#endif - - for (index = 0; index < PATH_NUM; index++) { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for (index = 0; index < APK_BB_REG_NUM; index++) { - for (path = 0; path < pathbound; path++) { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - - for (index = 0; index < APK_BB_REG_NUM ; index++) { - if (index == 0) - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); - - - _PHY_SaveADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); - - - _PHY_SaveADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for (path = 0; path < pathbound; path++) { - - - if (path == ODM_RF_PATH_A) { - - offset = rPdp_AntA; - for (index = 0; index < 11; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for (; index < 13; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - - offset = rPdp_AntA; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else if (path == ODM_RF_PATH_B) { - - offset = rPdp_AntB; - for (index = 0; index < 10; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#else - PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); -#endif - - offset = rConfig_AntA; - index = 11; - for (; index < 13; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - - offset = 0xb60; - for (index = 0; index < 16; index++) { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - - if (path == 0) { - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } else { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_8723D(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration_8723D(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if (path == ODM_RF_PATH_A) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if (delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - - for (index = 0; index < APK_BB_REG_NUM; index++) { - if (index != 1) - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if (!(tmpReg & BIT15)) { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if (BB_offset < 0) { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } else { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - if (path == ODM_RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); -#endif - - - for (index = 0; index < APK_BB_REG_NUM ; index++) { - - if (index == 0) - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - - for (path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); - if (path == ODM_RF_PATH_B) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for (path = 0; path < pathbound; path++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if (path == ODM_RF_PATH_A) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (!IS_HARDWARE_TYPE_8723A(pAdapter)) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8723D()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - - -VOID -PHY_IQCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif -#endif - - - u1Byte u1bTmp; - u2Byte count = 0; - s4Byte result[4][8]; - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathS1_OK, bPathS0_OK; - s4Byte RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0, RegTmp = 0; - s4Byte RegC80, RegC94, RegC14, RegCA0, RegCd0, RegCd4, RegCd8; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE, bContinousTx = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - u4Byte Path_SEL_BB_phyIQK; - u4Byte originalPath, originalGNT; -#if 1 -ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("================ IQK Start ===================\n")); - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#else - prtl8192cd_priv priv = pDM_Odm->priv; - -#ifdef MP_TEST - if (priv->pshare->rf_ft_var.mp_specific) { - if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) - return; - } -#endif - - if (priv->pshare->IQK_88E_done) - bReCovery= 1; - priv->pshare->IQK_88E_done = 1; - -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { - return; - } -#endif - - -#if MP_DRIVER == 1 - -/*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - /* Add to determine IQK ON/OFF in certain case, Suggested by Cheng.*/ - /* if (!pHalData->IQK_MP_Switch) - return;*/ -/*#endif*/ - - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - bContinousTx = pMptCtx->bStartContTx; -#endif - - /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ - if (bSingleTone || bCarrierSuppression || bContinousTx) - return; - - - -#if DISABLE_BB_RF - return; -#endif - - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("=====>PHY_IQCalibrate_8723D\n")); - - - Path_SEL_BB_phyIQK = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if (bReCovery) -#else - if (bReCovery && (!pAdapter->bInHctTest)) -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723D: Return due to bReCovery!\n")); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_ReloadADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#endif - return; - } - - /*Check & wait if BT is doing IQK*/ - - if (pDM_Odm->mp_mode == FALSE) { -#if MP_DRIVER != 1 - SetFwWiFiCalibrationCmd_8723D(pAdapter, 1); - - - count = 0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while (u1bTmp != 0x1 && count < 1000) { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - if (count >= 1000) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - } - - - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - while ((!(u1bTmp&BIT0)) && count < 6000) { - PlatformStallExecution(50); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); - count++; - } -#endif - } - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - for (i = 0; i < 8; i++) { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - - final_candidate = 0xff; - bPathS1_OK = FALSE; - bPathS0_OK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - -#if 1 - /*backup Path & GNT value */ - originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); - ODM_delay_ms(1); - originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); - - /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); -#endif - - for (i = 0; i < 3; i++) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_IQCalibrate_8723D(pAdapter, result, i, TRUE); -#else - phy_IQCalibrate_8723D(pDM_Odm, result, i, TRUE); -#endif - -#if 1 - /*Restore GNT_WL/GNT_BT and Path owner*/ - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); - ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); - ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); -#endif - - if (i == 1) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is12simular = phy_SimularityCompare_8723D(pAdapter, result, 0, 1); -#else - is12simular = phy_SimularityCompare_8723D(pDM_Odm, result, 0, 1); -#endif - - if (is12simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); - break; - } - } - - if (i == 2) { -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is13simular = phy_SimularityCompare_8723D(pAdapter, result, 0, 2); -#else - is13simular = phy_SimularityCompare_8723D(pDM_Odm, result, 0, 2); -#endif - - if (is13simular) { - final_candidate = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); - - break; - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - is23simular = phy_SimularityCompare_8723D(pAdapter, result, 1, 2); -#else - is23simular = phy_SimularityCompare_8723D(pDM_Odm, result, 1, 2); -#endif - - if (is23simular) { - final_candidate = 1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); - } else { - for (i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if (RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - - } - } - } - - - - for (i = 0; i < 4; i++) { - RegE94_S1 = result[i][0]; - RegE9C_S1 = result[i][1]; - RegEA4_S1 = result[i][2]; - RegEAC_S1 = result[i][3]; - RegE94_S0 = result[i][4]; - RegE9C_S0 = result[i][5]; - RegEA4_S0 = result[i][6]; - RegEAC_S0 = result[i][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] RegE94_S1=%x RegE9C_S1=%x RegEA4_S1=%x RegEAC_S1=%x RegE94_S0=%x RegE9C_S0=%x RegEA4_S0=%x RegEAC_S0=%x\n ", RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0)); - } - - if (final_candidate != 0xff) { - pDM_Odm->RFCalibrateInfo.RegE94 = RegE94_S1 = result[final_candidate][0]; - pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C_S1 = result[final_candidate][1]; - RegEA4_S1 = result[final_candidate][2]; - RegEAC_S1 = result[final_candidate][3]; - pDM_Odm->RFCalibrateInfo.RegEB4 = RegE94_S0 = result[final_candidate][4]; - pDM_Odm->RFCalibrateInfo.RegEBC = RegE9C_S0 = result[final_candidate][5]; - RegEA4_S0 = result[final_candidate][6]; - RegEAC_S0 = result[final_candidate][7]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] final_candidate is %x\n", final_candidate)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x\n ", RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0)); - bPathS1_OK = bPathS0_OK = TRUE; - } else { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] FAIL use default value\n")); - - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; - } - - - if (RegE94_S1 != 0) - _PHY_PathS1FillIQKMatrix_8723D(pAdapter, bPathS1_OK, result, final_candidate, (RegEA4_S1 == 0)); - if (RegE94_S0 != 0) - _PHY_PathS0FillIQKMatrix_8723D(pAdapter, bPathS0_OK, result, final_candidate, (RegEA4_S0 == 0)); - - - RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); - RegC94 = ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord); - RegC14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); - RegCA0 = ODM_GetBBReg(pDM_Odm, 0xca0, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", RegC80, RegC94, RegC14, RegCA0)); - - - RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); - RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); - RegCd8 = ODM_GetBBReg(pDM_Odm, 0xcd8, bMaskDWord); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", RegCd0, RegCd4, RegCd8)); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -#else - Indexforchannel = 0; -#endif - - - if (final_candidate < 4) { - for (i = 0; i < IQK_Matrix_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; - pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - _PHY_SaveADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); -#else - _PHY_SaveADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); -#endif - - if (pDM_Odm->mp_mode == FALSE) { -#if MP_DRIVER != 1 - SetFwWiFiCalibrationCmd_8723D(pAdapter, 0); - - - count = 0; - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - while (u1bTmp != 0 && count < 1000) { - PlatformStallExecution(10); - u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); - count++; - } - - if (count >= 1000) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); - } -#endif - } - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB_phyIQK); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); -#endif - -} - - -VOID -PHY_LCCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ - BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif -#endif - -#if MP_DRIVER == 1 - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#if DISABLE_BB_RF - return; -#endif - - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { - return; - } -#endif - - if (bSingleTone || bCarrierSuppression) - return; - - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - phy_LCCalibrate_8723D(pDM_Odm, FALSE); - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); - -} - -VOID -PHY_APCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { - return; - } -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if (pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8723D(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8723D(pDM_Odm, delta, FALSE); -#endif - } -VOID phy_SetRFPathSwitch_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (bMain) { - ODM_SetMACReg(pDM_Odm, 0x7C4, bMaskLWord, 0x7700); - } else { - ODM_SetMACReg(pDM_Odm, 0x7C4, bMaskLWord, 0xDD00); - } - - ODM_SetMACReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); - ODM_SetMACReg(pDM_Odm, 0x70, BIT26, 1); - ODM_SetMACReg(pDM_Odm, 0x64, BIT31, 1); -} - -VOID PHY_SetRFPathSwitch_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8723D(pAdapter, bMain, TRUE); -#endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -phy_DigitalPredistortion_8723D( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8723D()\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8723D for %s\n", (is2T ? "2T2R" : "1T1R"))); - - - for (index = 0; index < DP_BB_REG_NUM; index++) - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_8723D(pAdapter, BB_REG, MAC_backup); -#else - _PHY_SaveMACRegisters_8723D(pDM_Odm, BB_REG, MAC_backup); -#endif - - - for (path = 0; path < DP_PATH_NUM; path++) { - for (index = 0; index < DP_RF_REG_NUM; index++) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); -#else - RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); -#endif - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - - for (index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); - - - for (index = 0; index < DP_BB_REG_NUM; index++) { - if (index < 4) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); - else if (index == 4) - ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); - } - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_8723D(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration_8723D(pDM_Odm, MAC_REG, MAC_backup); -#endif - - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - for (i = 0; i < 3; i++) { - - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - - for (index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm, 0xe08+index*4, bMaskDWord, 0x03903434); - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, 0x34343434); - - - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - - if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { - - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for (i = rPdp_AntA; i <= 0xb3c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 ofsset = 0x%x\n", i)); - } - - - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for (i = 0xb4c; i <= 0xb5c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - - if (is2T) { - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - - for (i = 0; i < 3; i++) { - - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - - for (index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for (index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - - if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { - - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for (i = 0xb60; i <= 0xb9c; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for (i = 0xbac; i <= 0xbbc; i += 4) { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); - - } else { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - - for (index = 0; index < DP_BB_REG_NUM; index++) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - - - for (path = 0; path < DP_PATH_NUM; path++) { - for (i = 0 ; i < DP_RF_REG_NUM ; i++) { - ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); - } - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - - _PHY_ReloadMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - - _PHY_ReloadMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); -#endif - - pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8723D()\n")); -#endif -} - -VOID -PHY_DigitalPredistortion_8723D( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; - - if (pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (IS_92C_SERIAL(pHalData->VersionID)) { - phy_DigitalPredistortion_8723D(pAdapter, TRUE); - } - else -#endif - { - - phy_DigitalPredistortion_8723D(pAdapter, FALSE); - } -} - - - - - -BOOLEAN phy_QueryRFPathSwitch_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - - if (ODM_GetBBReg(pDM_Odm, 0x7C4, bMaskLWord) == 0x7700) - return TRUE; - else - return FALSE; - -} - - - - -BOOLEAN PHY_QueryRFPathSwitch_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8723D(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8723D(pDM_Odm, FALSE); -#endif - -} -#endif - - - -#else - -VOID -PHY_IQCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bReCovery - ){} -VOID -PHY_LCCalibrate_8723D( - IN PDM_ODM_T pDM_Odm - ){} - -VOID -ODM_TxPwrTrackSetPwr_8723D( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ){} -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//#include "Mp_Precomp.h" +#include "../phydm_precomp.h" + + +#if (RTL8723D_SUPPORT == 1) + +/*---------------------------Define Local Constant---------------------------*/ +/*IQK*/ +#define IQK_DELAY_TIME_8723D 10 + +/* 2010/04/25 MH Define the max tx power tracking tx agc power.*/ +#define ODM_TXPWRTRACK_MAX_IDX_8723D 6 + +#define PATH_S1 0 +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 + +#define IDX_0xC14 0 +#define IDX_0xCA0 1 + + +#define PATH_S0 1 +#define IDX_0xCD0 0 +#define IDX_0xCD4 1 + +#define IDX_0xCD8 0 +#define IDX_0xCDC 1 + +#define KEY 0 +#define VAL 1 + + + +/*---------------------------Define Local Constant---------------------------*/ + + +/* Tx Power Tracking*/ + + +void setIqkMatrix_8723D( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) + { + s4Byte ele_A = 0, ele_D = 0, ele_C = 0, value32, tmp; + s4Byte ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0; + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE-1; + else if (OFDM_index < 0) + OFDM_index = 0; + + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + + /* new element D */ + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + ele_D_ext = (((IqkResult_X * ele_D)>>7)&0x01); + /* new element A */ + if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + ele_A_ext = ((IqkResult_X * ele_D)>>7) & 0x1; + /* new element C */ + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + ele_C_ext = ((IqkResult_Y * ele_D)>>7) & 0x1; + + switch (RFPath) { + case ODM_RF_PATH_A: + /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */ + /* write 0xc80 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + /* write 0xc94 */ + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + /* write 0xc4c */ + value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29); + value32 = (ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28))) | value32; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + + case ODM_RF_PATH_B: + /*wirte new elements A, C, D to regCd0 and regCd4, element B is always 0*/ + value32 = ele_D; + ODM_SetBBReg(pDM_Odm, 0xCd4, 0x007FE000, value32); + + value32 = ele_C; + ODM_SetBBReg(pDM_Odm, 0xCd4, 0x000007FE, value32); + + value32 = ele_A; + ODM_SetBBReg(pDM_Odm, 0xCd0, 0x000007FE, value32); + + ODM_SetBBReg(pDM_Odm, 0xCd4, BIT12, ele_D_ext); + ODM_SetBBReg(pDM_Odm, 0xCd0, BIT0, ele_A_ext); + ODM_SetBBReg(pDM_Odm, 0xCd4, BIT0, ele_C_ext); + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + value32 = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord)&(~(BIT31|BIT29|BIT28)); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord, value32); + break; + + case ODM_RF_PATH_B: + /*image S1:c80 to S0:Cd0 and Cd4*/ + ODM_SetBBReg(pDM_Odm, 0xcd0, 0x000007FE, OFDMSwingTable_New[OFDM_index]&0x000003FF); + ODM_SetBBReg(pDM_Odm, 0xcd0, 0x0007E000, (OFDMSwingTable_New[OFDM_index]&0x0000FC00)>>10); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x0000007E, (OFDMSwingTable_New[OFDM_index]&0x003F0000)>>16); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x007FE000, (OFDMSwingTable_New[OFDM_index]&0xFFC00000)>>22); + + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x00000780, 0x00); + + ODM_SetBBReg(pDM_Odm, 0xcd4, BIT12, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, BIT0, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd0, BIT0, 0x0); + break; + default: + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n", + (RFPath == ODM_RF_PATH_A ? 'A' : 'B'), (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)ele_A_ext, (u4Byte)ele_C_ext, (u4Byte)ele_D_ext)); + } + +VOID +setCCKFilterCoefficient_8723D( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[CCKSwingIndex]); +} + +void DoIQK_8723D( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + u4Byte bIsBtEnable; + + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + +#if (MP_DRIVER != 1) + + bIsBtEnable = ODM_GetMACReg(pDM_Odm, 0xa8, bMaskDWord) & BIT17; + + if (bIsBtEnable) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Skip IQK because BT is enable\n")); + return; + } + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Do IQK because BT is disable\n")); +#endif + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8723D(pDM_Odm, FALSE); +#else + PHY_IQCalibrate_8723D(Adapter, FALSE); +#endif + +} + +/*----------------------------------------------------------------------------- + * Function: ODM_TxPwrTrackSetPwr_8723D() + * + * Overview: 8723D change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID, +#else + IN PDM_ODM_T pDM_VOID, +#endif + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte PwrTrackingLimit_OFDM = 30; + u1Byte PwrTrackingLimit_CCK = 40; + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#else + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + if (!pMgntInfo->ForcedDataRate) { + if (pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } else { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } +#endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (pDM_Odm->mp_mode == TRUE) { /*CE MP*/ + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + } else { /*CE normal*/ + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (pDM_Odm->TxRate != 0xFF) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723DA\n")); + + if (TxRate != 0xFF) { + /*CCK*/ + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || TxRate == MGN_11M) + PwrTrackingLimit_CCK = 40; + /*OFDM*/ + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; + + /* HT*/ + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) + PwrTrackingLimit_OFDM = 38; + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) + PwrTrackingLimit_OFDM = 36; + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) + PwrTrackingLimit_OFDM = 34; + + else if ((TxRate >= MGN_MCS8) && (TxRate <= MGN_MCS10)) + PwrTrackingLimit_OFDM = 38; + else if ((TxRate >= MGN_MCS11) && (TxRate <= MGN_MCS12)) + PwrTrackingLimit_OFDM = 36; + else if ((TxRate >= MGN_MCS13) && (TxRate <= MGN_MCS15)) + PwrTrackingLimit_OFDM = 34; + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30 */ + } + + if (Method == TXAGC) { + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr_8723D CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value. + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + +#if (MP_DRIVER != 1) + /*PHY_SetTxPowerLevelByPath8723D(Adapter, pHalData->CurrentChannel, RFPath); //Using new set power function + //PHY_SetTxPowerLevel8723D(pDM_Odm->Adapter, *pDM_Odm->pChannel);*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + if (RFPath == ODM_RF_PATH_A) { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15 ); + } else { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS8_MCS15 ); + } +#else + + if (RFPath == ODM_RF_PATH_A) { + /*CCK Path S1*/ + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0x00ffffff, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + /*OFDM Path S1*/ + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); + TxAGC = ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else if (RFPath == ODM_RF_PATH_B) { + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B]; + PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xff000000, pwr); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: CCK Tx-rf(B) Power = 0x%x\n", pwr)); + + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_B] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_B]); + TxAGC = ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr_8723D: OFDM Tx-rf(B) Power = 0x%x\n", TxAGC)); + } +#endif + +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + /*PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));*/ +#endif + + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, pRFCalibrateInfo->Remnant_CCKSwingIdx=%d RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); + + /* Adjust BB swing by OFDM IQ matrix */ + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index < 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE_8723D) + Final_CCK_Swing_Index = CCK_TABLE_SIZE_8723D-1; + else if (pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + setCCKFilterCoefficient_8723D(pDM_Odm, Final_CCK_Swing_Index); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_CCK_Swing_Index=%d\n", Final_CCK_Swing_Index)); + + } else if (Method == MIX_MODE) { + #if (MP_DRIVER == 1) + u4Byte TxAGC = 0; /*add by Mingzhi.Guo 2015-04-10*/ + s4Byte pwr = 0; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) { + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*CCK Follow Path-A and lower CCK index means higher power.*/ + + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM);*/ + /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + /*Set TxAGC Page C{};*/ + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM);*/ + /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + /*Set TxAGC Page C{};*/ + /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS8_MCS15 );*/ + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } +#if (MP_DRIVER == 1) + if ((pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM); + + if (pwr > 0x3F) + pwr = 0x3F; + else if (pwr < 0) + pwr = 0; + + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + + } else +#endif + { + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] ; + + if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + /* Adjust BB swing by CCK filter coefficient*/ + ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[PwrTrackingLimit_CCK]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + /*Set TxAGC Page C{};*/ + /* PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK);*/ + + } else if (Final_CCK_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + + ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK);*/ + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + + ODM_SetBBReg(pDM_Odm, 0xab4, 0x000007FF, CCKSwingTable_Ch1_Ch14_8723D[Final_CCK_Swing_Index]); + + /* if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) {*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + + + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, CCK );*/ + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n")); + } +#if (MP_DRIVER == 1) + if ((pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1); + pwr += pRFCalibrateInfo->Remnant_CCKSwingIdx-pRFCalibrateInfo->Modify_TxAGC_Value_CCK; + + if (pwr > 0x3F) + pwr = 0x3F; + else if (pwr < 0) + pwr = 0; + + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723D: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else +#endif + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + + pRFCalibrateInfo->Modify_TxAGC_Value_CCK = pRFCalibrateInfo->Remnant_CCKSwingIdx; + } +#if 0 + if (RFPath == ODM_RF_PATH_B) { + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8723D(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < 0) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + + setIqkMatrix_8723D(pDM_Odm, 0, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else { + setIqkMatrix_8723D(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_B, + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][4], + pRFCalibrateInfo->IQKMatrixRegSetting[ChannelMappedIndex].Value[0][5]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + /*PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7);*/ + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } +#if (MP_DRIVER == 1) + if ((pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_B] - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM); + + if (pwr > 0x3F) + pwr = 0x3F; + else if (pwr < 0) + pwr = 0; + + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723D: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + + } else +#endif + { + + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_B, pHalData->CurrentChannel, HT_MCS0_MCS7); + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_B] ; + } +#endif +} else { + return; + } +} + +VOID +GetDeltaSwingTable_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID, +#else + IN PDM_ODM_T pDM_Odm, +#endif + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +VOID +GetDeltaSwingXtalTable_8723D( + PVOID pDM_VOID, + ps1Byte *TemperatureUP_Xtal, + ps1Byte *TemperatureDOWN_Xtal +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + *TemperatureUP_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_P; + *TemperatureDOWN_Xtal = pRFCalibrateInfo->DeltaSwingTableXtal_N; +} + + + +VOID +ODM_TxXtalTrackSetXtal_8723D( + PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + s1Byte CrystalCap; + + + CrystalCap = pHalData->CrystalCap & 0x3F; + CrystalCap = CrystalCap + pRFCalibrateInfo->XtalOffset; + + if (CrystalCap < 0) + CrystalCap = 0; + else if (CrystalCap > 63) + CrystalCap = 63; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("CrystalCap(%d)= pHalData->CrystalCap(%d) + pRFCalibrateInfo->XtalOffset(%d)\n", CrystalCap, pHalData->CrystalCap, pRFCalibrateInfo->XtalOffset)); + + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("CrystalCap(0x2c) 0x%X\n", ODM_GetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000))); + +} + +void ConfigureTxpowerTrack_8723D( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE_8723D; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723D; + pConfig->RfPathCount = MAX_PATH_NUM_8723D; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723D; + pConfig->DoIQK = DoIQK_8723D; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723D; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723D; + pConfig->GetDeltaSwingXtalTable = GetDeltaSwingXtalTable_8723D; + pConfig->ODM_TxXtalTrackSetXtal = ODM_TxXtalTrackSetXtal_8723D; +} + + +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 + +u1Byte +phy_PathS1_IQK_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathS0 + ) +{ + u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEA4*/; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 TXIQK!!\n")); + /*save RF path*/ + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 TXIQK = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000000); + + /*IQK setting*/ + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /* --- \A7\EF\BCgTXIQK mode table ---//*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00004); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xBFFE0); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x08008c0c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214019f); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160200); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /*PA, PAD setting*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x600, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x1E0, 0x3); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8d, 0x1F, 0xf); + + /*LOK setting added for 8723D*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x10, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x54, 0x1, 0x1); +#if 1 + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe0d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x60d); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + /*One shot, Path S1 LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xfa000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /*PA/PAD controlled by 0x0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + + /* Check failed*/ + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 TXIQK FAIL\n")); + + + return result; + + } + +u1Byte +phy_PathS1_RxIQK_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathS0 + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 RXIQK Step1!!\n")); + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000000); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 RXIQK1 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6))); */ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + /*IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /*modify RXIQK mode table*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00006); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xa7ffb); + + /*---------PA/PAD=0----------*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, 0x600, 0x0); +#if 1 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe0d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x60d); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + /*One shot, Path S1 LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /*delay x ms*/ + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + + + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + tmp = (regE9C & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 RXIQK STEP1 FAIL\n")); +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + return result; + } + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S1 RXIQK STEP2!!\n")); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S1 RXIQK2 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6))); */ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + + + /*modify RXIQK mode table*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00007); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xb3fdb); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S1 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S1 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S1 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S1 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /* PA/PAD controlled by 0x0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + + tmp = (regEAC & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36) && + (((regEA4 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S1 RXIQK STEP2 FAIL\n")); + + + return result; +} + + +u1Byte +phy_PathS0_IQK_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEA4, regEAC, regE94, regE9C, regE94_S0, regE9C_S0, regEA4_S0, regEAC_S0, tmp, Path_SEL_BB; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 TXIQK!\n")); + + + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000280); /*10 od 0x948 0x1 [7] ; WL:S1 to S0;BT:S0 to S1;*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 TXIQK = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /*modify TXIQK mode table*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00004); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xBFFE0); + + /*path-A IQK setting*/ + ODM_SetBBReg(pDM_Odm, 0xe30, bMaskDWord, 0x08008c0c); + ODM_SetBBReg(pDM_Odm, 0xe34, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, 0xe38, bMaskDWord, 0x8214018a); + ODM_SetBBReg(pDM_Odm, 0xe3c, bMaskDWord, 0x28160200); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + /*LO calibration setting*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /*PA, PAD setting*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x600, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x1E0, 0x3); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8d, 0x1F, 0xf); + + /*LOK setting added for 8723D*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, 0x10, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x1, 0x1); + +#if 1 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe6d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x66d); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 TXIQK = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + + + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 TXIQK = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + /*One shot, Path S1 LOK & IQK*/ + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /*delay x ms*/ + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /*PA/PAD controlled by 0x0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + + /* Check failed*/ + regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n", regE94_S0, regE9C_S0)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC_S0 & BIT28) && + (((regE94_S0 & 0x03FF0000)>>16) != 0x142) && + (((regE9C_S0 & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 TXIQK FAIL\n")); + + return result; +} + + + +u1Byte +phy_PathS0_RxIQK_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathS0 + ) +{ + u4Byte regE94, regE9C, regEA4, regEAC, regE94_S0, regE9C_S0, regEA4_S0, regEAC_S0, tmp, u4tmp, Path_SEL_BB; + u1Byte result = 0x00, Ktime; + u4Byte originalPath, originalGNT; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 RxIQK Step1!!\n")); + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x99000280); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 RXIQK1 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00006); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xa7ffb); + + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x66, 0x600, 0x0); + +#if 1 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, 0xe6d); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask, 0x66d); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 RXIQK1 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 RXIQK1 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + + regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C_S0 = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n", regE94_S0, regE9C_S0)); + /*monitor image power before & after IQK*/ + ODM_RT_TRACE(pDM_Odm , ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + tmp = (regE9C_S0 & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC_S0 & BIT28) && + (((regE94_S0 & 0x03FF0000)>>16) != 0x142) && + (((regE9C_S0 & 0x03FF0000)>>16) != 0x42)) + + result |= 0x01; + else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 RXIQK STEP1 FAIL\n")); +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + return result; + } + + u4tmp = 0x80007C00 | (regE94_S0&0x3FF0000) | ((regE9C_S0&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40_s0 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Path S0 RXIQK STEP2!!\n\n")); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]0x1e6@S0 RXIQK2 = 0x%x\n", PlatformEFIORead1Byte(pAdapter, 0x1e6)));*/ + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82170000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28170000); + + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a891); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xee, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00007); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x0005f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0xb3fdb); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x1@ Path S0 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF0x2@ Path S0 RXIQK2 = 0x%x\n", ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, bRFRegOffsetMask))); + /*enter IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0054); + ODM_delay_ms(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]GNT_BT@S0 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0x948@S0 RXIQK2 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + + /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/ + Ktime = 0; + while ((!ODM_GetBBReg(pDM_Odm, 0xeac, BIT26)) && Ktime < 10) { + ODM_delay_ms(1); + Ktime++; + } + +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + /*reload RF path*/ + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + + /*leave IQK mode*/ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xde, 0x800, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2, BIT0, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, BIT0, 0x0); + + regEAC_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4_S0 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac_s0 = 0x%x\n", regEAC_S0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4_s0 = 0x%x, 0xeac_s0 = 0x%x\n", regEA4_S0, regEAC_S0)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0_s0(before IQK)= 0x%x, 0xea8_s0(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + + tmp = (regEAC_S0 & 0x03FF0000)>>16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(regEAC_S0 & BIT27) && /*if Tx is OK, check whether Rx is OK*/ + (((regEA4_S0 & 0x03FF0000)>>16) != 0x132) && + (((regEAC_S0 & 0x03FF0000)>>16) != 0x36) && + (((regEA4_S0 & 0x03FF0000)>>16) < 0x11a) && + (((regEA4_S0 & 0x03FF0000)>>16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S0 RXIQK STEP2 FAIL\n")); + + + return result; +} + + +VOID +_PHY_PathS1FillIQKMatrix_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) + { + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x, Oldval_1 0x%x\n", X, TX1_A, Oldval_1)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_1 >> 7) & 0x1)); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathS1FillIQKMatrix_8723D only Tx OK\n")); + return; + } + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (RTL_ABS(reg , 0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); +/* +10 os 7201 10 +10 id ea4 [25:16] p +10 os 7202 10 +10 od c14 VarFromTmp [9:0] p + +10 os 7201 11 +10 id eac [25:22] p +10 os 7202 11 +10 od ca0 VarFromTmp [31:28] p + +10 os 7201 12 +10 id eac [21:16] p +10 os 7202 12 +10 od c14 VarFromTmp [15:10] p +*/ + } + } + +VOID +_PHY_PathS0FillIQKMatrix_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord) >> 13) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, 0xcd0, 0x7FE, TX0_A); + + ODM_SetBBReg(pDM_Odm, 0xcd0, BIT(0), ((X * Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x7FE, (TX0_C & 0x3FF)); + + ODM_SetBBReg(pDM_Odm, 0xcd4, BIT(0), ((Y * Oldval_0>>7) & 0x1)); + + if (bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, 0xcd8, 0x3FF, reg); + + reg = result[final_candidate][7]; + ODM_SetBBReg(pDM_Odm, 0xcd8, 0x003FF000, reg); +/* +10 os 7201 10 +10 id ea4 [25:16] p +10 os 7202 10 +10 od cd8 VarFromTmp [9:0] p + +10 os 7201 11 +10 id eac [25:16] p +10 os 7202 11 +10 od cd8 VarFromTmp [21:12] p + RegE94_S1 = result[i][0]; + RegE9C_S1 = result[i][1]; + RegEA4_S1 = result[i][2]; + RegEAC_S1 = result[i][3]; + RegE94_S0 = result[i][4]; + RegE9C_S0 = result[i][5]; + RegEA4_S0 = result[i][6]; + RegEAC_S0 = result[i][7]; +*/ + } +} +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ +/* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } +*/ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + + for (i = 0 ; i < RegisterNum ; i++) { + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID +_PHY_SaveMACRegisters_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0 ; i < RegiesterNum; i++) { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID +_PHY_ReloadMACRegisters_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + pathOn = isPathAOn ? 0x03c00016 : 0x03c00016; + + if (FALSE == is2T) { + pathOn = 0x03c00016; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x03c00016); + } else { + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + } + + for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) { + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID +_PHY_MACSettingCalibration_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + +/* + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); +*/ + + /*ODM_SetBBReg(pDM_Odm, 0x522, bMaskByte0, 0x7f);*/ + /*ODM_SetBBReg(pDM_Odm, 0x550, bMaskByte0, 0x15);*/ + /*ODM_SetBBReg(pDM_Odm, 0x551, bMaskByte0, 0x00);*/ + + ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); + + + +} + +VOID +_PHY_PathAStandBy_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-S1 standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); +/* ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID +_PHY_PathBStandBy_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-S0 standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + + +VOID +_PHY_PIModeSwitch_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; + BOOLEAN bResult = TRUE; +/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +//#else*/ + BOOLEAN is2T = TRUE; +/*#endif*/ + + s4Byte tmp1 = 0,tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8723D c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1<odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte i; + u1Byte PathS1_OK, PathS0_OK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting + }; + u4Byte cnt_IQKFail = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 9; +#else + const u4Byte retryCount = 2; +#endif +#endif + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if (t == 0) { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_8723D(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters_8723D(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for 1T1R_S0/S1 for %d times\n", t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + +/* + if(t==0) + { + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch_8723D(pAdapter, TRUE); +#else + _PHY_PIModeSwitch_8723D(pDM_Odm, TRUE); +#endif + } +*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + /*BB setting*/ + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05611); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x25204200); + + /*IQ calibration setting*/ + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); */ + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + +if (is2T) { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathBStandBy_8723D(pAdapter); + + + _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathBStandBy_8723D(pDM_Odm); + + + _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + } + + +#if 1 + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathS1_OK = phy_PathS1_IQK_8723D(pAdapter, is2T); +#else + PathS1_OK = phy_PathS1_IQK_8723D(pDM_Odm, is2T); +#endif + + if (PathS1_OK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Tx IQK Fail!!\n")); + result[t][0] = 0x100; + result[t][1] = 0x0; + cnt_IQKFail++; + } +#if 0 + else if (i == (retryCount-1) && PathS1_OK == 0x01) + { + RT_DISP(FINIT, INIT_IQK, ("Path S1 IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } +#endif + + +#if 1 + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathS1_OK = phy_PathS1_RxIQK_8723D(pAdapter, is2T); +#else + PathS1_OK = phy_PathS1_RxIQK_8723D(pDM_Odm, is2T); +#endif + if (PathS1_OK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Rx IQK Success!!\n")); + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 Rx IQK Fail!!\n")); + result[t][2] = 0x100; + result[t][3] = 0x0; + cnt_IQKFail++; + } + } + + if (0x00 == PathS1_OK) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 IQK failed!!\n")); + } + +#endif + + if (is2T) { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy_8723D(pAdapter); + + + _PHY_PathADDAOn_8723D(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy_8723D(pDM_Odm); + + + _PHY_PathADDAOn_8723D(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif + + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + +#if 1 + for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathS0_OK = phy_PathS0_IQK_8723D(pAdapter); +#else + PathS0_OK = phy_PathS0_IQK_8723D(pDM_Odm); +#endif + + if (PathS0_OK == 0x01) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, 0xe94, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, 0xe9c, bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Tx IQK Fail!!\n")); + result[t][4] = 0x100; + result[t][5] = 0x0; + cnt_IQKFail++; + } +#if 0 + else if (i == (retryCount-1) && PathS1_OK == 0x01) + { + RT_DISP(FINIT, INIT_IQK, ("Path S0 IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } +#endif + } +#endif + + +#if 1 + +for (i = 0 ; i < retryCount ; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathS0_OK = phy_PathS0_RxIQK_8723D(pAdapter, is2T); +#else + PathS0_OK = phy_PathS0_RxIQK_8723D(pDM_Odm, is2T); +#endif + if (PathS0_OK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Rx IQK Success!!\n")); +/* result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ +/* result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;*/ + result[t][6] = (ODM_GetBBReg(pDM_Odm, 0xea4, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, 0xeac, bMaskDWord)&0x3FF0000)>>16; + break; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 Rx IQK Fail!!\n")); + result[t][6] = 0x100; + result[t][7] = 0x0; + cnt_IQKFail++; + } + } + + + + if (0x00 == PathS0_OK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S0 IQK failed!!\n")); + +#endif + } + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (t != 0) { + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + + _PHY_ReloadADDARegisters_8723D(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_8723D(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + + _PHY_ReloadADDARegisters_8723D(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters*/ + _PHY_ReloadMACRegisters_8723D(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + + } + + pDM_Odm->nIQK_Cnt++; + + if (cnt_IQKFail == 0) + pDM_Odm->nIQK_OK_Cnt++; + else + pDM_Odm->nIQK_Fail_Cnt = pDM_Odm->nIQK_Fail_Cnt + cnt_IQKFail; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723D() <==\n")); + +} + + +VOID +phy_LCCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal, cnt; +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + + + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); + else + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); + + /*backup RF0x18*/ + + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + + /*Start LCK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); + + for (cnt = 0; cnt < 100; cnt++) { + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + + /* Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + /*Restore original situation*/ + if ((tmpReg & 0x70) != 0) + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + else + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); +} + + +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; +/* u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];*/ + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8723D() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if (!is2T) + pathbound = 1; + + + +/* Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.*/ +#if MP_DRIVER != 1 + return; +#endif + + for (index = 0; index < PATH_NUM; index++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for (index = 0; index < APK_BB_REG_NUM; index++) { + for (path = 0; path < pathbound; path++) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + + for (index = 0; index < APK_BB_REG_NUM ; index++) { + if (index == 0) + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); + + + _PHY_SaveADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); + + + _PHY_SaveADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for (path = 0; path < pathbound; path++) { + + + if (path == ODM_RF_PATH_A) { + + offset = rPdp_AntA; + for (index = 0; index < 11; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for (; index < 13; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + + offset = rPdp_AntA; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else if (path == ODM_RF_PATH_B) { + + offset = rPdp_AntB; + for (index = 0; index < 10; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for (; index < 13; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + + offset = 0xb60; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + + if (path == 0) { + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } else { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_8723D(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration_8723D(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if (path == ODM_RF_PATH_A) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if (delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index != 1) + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if (!(tmpReg & BIT15)) { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if (BB_offset < 0) { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } else { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + if (path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8723D() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); +#endif + + + for (index = 0; index < APK_BB_REG_NUM ; index++) { + + if (index == 0) + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + + for (path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if (path == ODM_RF_PATH_B) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if (path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (!IS_HARDWARE_TYPE_8723A(pAdapter)) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8723D()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + + +VOID +PHY_IQCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif +#endif + + + u1Byte u1bTmp; + u2Byte count = 0; + s4Byte result[4][8]; + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathS1_OK, bPathS0_OK; + s4Byte RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0, RegTmp = 0; + s4Byte RegC80, RegC94, RegC14, RegCA0, RegCd0, RegCd4, RegCd8; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE, bContinousTx = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + u4Byte Path_SEL_BB_phyIQK; + u4Byte originalPath, originalGNT; +#if 1 +ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("================ IQK Start ===================\n")); + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if (priv->pshare->IQK_88E_done) + bReCovery= 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { + return; + } +#endif + + +#if MP_DRIVER == 1 + +/*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + /* Add to determine IQK ON/OFF in certain case, Suggested by Cheng.*/ + /* if (!pHalData->IQK_MP_Switch) + return;*/ +/*#endif*/ + + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + bContinousTx = pMptCtx->bStartContTx; +#endif + + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu)*/ + if (bSingleTone || bCarrierSuppression || bContinousTx) + return; + + + +#if DISABLE_BB_RF + return; +#endif + + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("=====>PHY_IQCalibrate_8723D\n")); + + + Path_SEL_BB_phyIQK = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) +#else + if (bReCovery && (!pAdapter->bInHctTest)) +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723D: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + + /*Check & wait if BT is doing IQK*/ + + if (pDM_Odm->mp_mode == FALSE) { +#if MP_DRIVER != 1 + SetFwWiFiCalibrationCmd_8723D(pAdapter, 1); + + + count = 0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while (u1bTmp != 0x1 && count < 1000) { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + if (count >= 1000) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + } + + + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + while ((!(u1bTmp&BIT0)) && count < 6000) { + PlatformStallExecution(50); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e7); + count++; + } +#endif + } + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + + final_candidate = 0xff; + bPathS1_OK = FALSE; + bPathS0_OK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + +#if 1 + /*backup Path & GNT value */ + originalPath = ODM_GetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, bMaskDWord); /*save 0x70*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0x800f0038); + ODM_delay_ms(1); + originalGNT = ODM_GetBBReg(pDM_Odm, REG_LTECOEX_READ_DATA, bMaskDWord); /*save 0x38*/ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]OriginalGNT = 0x%x\n", originalGNT)); + + /*set GNT_WL=1/GNT_BT=1 and Path owner to WiFi for pause BT traffic*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc0020038); /*0x38[15:8] = 0x77*/ + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, BIT26, 0x1); +#endif + + for (i = 0; i < 3; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_IQCalibrate_8723D(pAdapter, result, i, TRUE); +#else + phy_IQCalibrate_8723D(pDM_Odm, result, i, TRUE); +#endif + +#if 1 + /*Restore GNT_WL/GNT_BT and Path owner*/ + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_WRITE_DATA, bMaskDWord, originalGNT); + ODM_SetBBReg(pDM_Odm, REG_LTECOEX_CTRL, bMaskDWord, 0xc00f0038); + ODM_SetMACReg(pDM_Odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, originalPath); +#endif + + if (i == 1) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8723D(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8723D(pDM_Odm, result, 0, 1); +#endif + + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate)); + break; + } + } + + if (i == 2) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8723D(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8723D(pDM_Odm, result, 0, 2); +#endif + + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8723D(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8723D(pDM_Odm, result, 1, 2); +#endif + + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate)); + } else { + for (i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if (RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + + } + } + } + + + + for (i = 0; i < 4; i++) { + RegE94_S1 = result[i][0]; + RegE9C_S1 = result[i][1]; + RegEA4_S1 = result[i][2]; + RegEAC_S1 = result[i][3]; + RegE94_S0 = result[i][4]; + RegE9C_S0 = result[i][5]; + RegEA4_S0 = result[i][6]; + RegEAC_S0 = result[i][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] RegE94_S1=%x RegE9C_S1=%x RegEA4_S1=%x RegEAC_S1=%x RegE94_S0=%x RegE9C_S0=%x RegEA4_S0=%x RegEAC_S0=%x\n ", RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0)); + } + + if (final_candidate != 0xff) { + pDM_Odm->RFCalibrateInfo.RegE94 = RegE94_S1 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C_S1 = result[final_candidate][1]; + RegEA4_S1 = result[final_candidate][2]; + RegEAC_S1 = result[final_candidate][3]; + pDM_Odm->RFCalibrateInfo.RegEB4 = RegE94_S0 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = RegE9C_S0 = result[final_candidate][5]; + RegEA4_S0 = result[final_candidate][6]; + RegEAC_S0 = result[final_candidate][7]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x\n ", RegE94_S1, RegE9C_S1, RegEA4_S1, RegEAC_S1, RegE94_S0, RegE9C_S0, RegEA4_S0, RegEAC_S0)); + bPathS1_OK = bPathS0_OK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; + } + + + if (RegE94_S1 != 0) + _PHY_PathS1FillIQKMatrix_8723D(pAdapter, bPathS1_OK, result, final_candidate, (RegEA4_S1 == 0)); + if (RegE94_S0 != 0) + _PHY_PathS0FillIQKMatrix_8723D(pAdapter, bPathS0_OK, result, final_candidate, (RegEA4_S0 == 0)); + + + RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); + RegC94 = ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord); + RegC14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); + RegCA0 = ODM_GetBBReg(pDM_Odm, 0xca0, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", RegC80, RegC94, RegC14, RegCA0)); + + + RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); + RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); + RegCd8 = ODM_GetBBReg(pDM_Odm, 0xcd8, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", RegCd0, RegCd4, RegCd8)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + + + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters_8723D(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters_8723D(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + if (pDM_Odm->mp_mode == FALSE) { +#if MP_DRIVER != 1 + SetFwWiFiCalibrationCmd_8723D(pAdapter, 0); + + + count = 0; + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + while (u1bTmp != 0 && count < 1000) { + PlatformStallExecution(10); + u1bTmp = PlatformEFIORead1Byte(pAdapter, 0x1e6); + count++; + } + + if (count >= 1000) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count)); + } +#endif + } + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB_phyIQK); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); +#endif + +} + + +VOID +PHY_LCCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif +#endif + +#if MP_DRIVER == 1 + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { + return; + } +#endif + + if (bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + phy_LCCalibrate_8723D(pDM_Odm, FALSE); + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) { + return; + } +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if (pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8723D(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8723D(pDM_Odm, delta, FALSE); +#endif + } +VOID phy_SetRFPathSwitch_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (bMain) { + ODM_SetMACReg(pDM_Odm, 0x7C4, bMaskLWord, 0x7700); + } else { + ODM_SetMACReg(pDM_Odm, 0x7C4, bMaskLWord, 0xDD00); + } + + ODM_SetMACReg(pDM_Odm, 0x7C0, bMaskDWord, 0xC00F0038); + ODM_SetMACReg(pDM_Odm, 0x70, BIT26, 1); + ODM_SetMACReg(pDM_Odm, 0x64, BIT31, 1); +} + +VOID PHY_SetRFPathSwitch_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8723D(pAdapter, bMain, TRUE); +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +phy_DigitalPredistortion_8723D( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8723D()\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8723D for %s\n", (is2T ? "2T2R" : "1T1R"))); + + + for (index = 0; index < DP_BB_REG_NUM; index++) + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_8723D(pAdapter, BB_REG, MAC_backup); +#else + _PHY_SaveMACRegisters_8723D(pDM_Odm, BB_REG, MAC_backup); +#endif + + + for (path = 0; path < DP_PATH_NUM; path++) { + for (index = 0; index < DP_RF_REG_NUM; index++) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); +#else + RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); +#endif + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + + for (index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); + + + for (index = 0; index < DP_BB_REG_NUM; index++) { + if (index < 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); + else if (index == 4) + ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); + } + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_8723D(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration_8723D(pDM_Odm, MAC_REG, MAC_backup); +#endif + + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + for (i = 0; i < 3; i++) { + + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + + for (index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm, 0xe08+index*4, bMaskDWord, 0x03903434); + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, 0x34343434); + + + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + + if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for (i = rPdp_AntA; i <= 0xb3c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 ofsset = 0x%x\n", i)); + } + + + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for (i = 0xb4c; i <= 0xb5c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + + if (is2T) { + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + + for (i = 0; i < 3; i++) { + + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + + for (index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + + if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for (i = 0xb60; i <= 0xb9c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for (i = 0xbac; i <= 0xbbc; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + + for (index = 0; index < DP_BB_REG_NUM; index++) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + + + for (path = 0; path < DP_PATH_NUM; path++) { + for (i = 0 ; i < DP_RF_REG_NUM ; i++) { + ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + } + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + + _PHY_ReloadMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + + _PHY_ReloadMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup); +#endif + + pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8723D()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8723D( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if (pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_92C_SERIAL(pHalData->VersionID)) { + phy_DigitalPredistortion_8723D(pAdapter, TRUE); + } + else +#endif + { + + phy_DigitalPredistortion_8723D(pAdapter, FALSE); + } +} + + + + + +BOOLEAN phy_QueryRFPathSwitch_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + + if (ODM_GetBBReg(pDM_Odm, 0x7C4, bMaskLWord) == 0x7700) + return TRUE; + else + return FALSE; + +} + + + + +BOOLEAN PHY_QueryRFPathSwitch_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8723D(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8723D(pDM_Odm, FALSE); +#endif + +} +#endif + + + +#else + +VOID +PHY_IQCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery + ){} +VOID +PHY_LCCalibrate_8723D( + IN PDM_ODM_T pDM_Odm + ){} + +VOID +ODM_TxPwrTrackSetPwr_8723D( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ){} +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.h b/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.h index 7138254ea34..737b77bbc29 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/halphyrf_8723d.h @@ -1,153 +1,153 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8723D_H__ -#define __HAL_PHY_RF_8723D_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8723D 10 //ms -#define index_mapping_NUM_8723D 15 -#define AVG_THERMAL_NUM_8723D 4 -#define RF_T_METER_8723D 0x42 - -void ConfigureTxpowerTrack_8723D( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID, -#else - IN PDM_ODM_T pDM_Odm, -#endif - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -VOID -setCCKFilterCoefficient_8723D( - PDM_ODM_T pDM_Odm, - u1Byte CCKSwingIndex -); - -void DoIQK_8723D( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID, -#else - IN PDM_ODM_T pDM_Odm, -#endif - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -ODM_TxXtalTrackSetXtal_8723D( - PVOID pDM_VOID -); - -//1 7. IQK - -void -PHY_IQCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER Adapter, -#endif - IN BOOLEAN bReCovery); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - PVOID pDM_VOID -#else - IN PDM_ODM_T pDM_Odm -#endif -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8723D( IN PADAPTER pAdapter); - - -VOID -_PHY_SaveADDARegisters_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration_8723D( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - -#endif // #ifndef __HAL_PHY_RF_8723D_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8723D_H__ +#define __HAL_PHY_RF_8723D_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8723D 10 //ms +#define index_mapping_NUM_8723D 15 +#define AVG_THERMAL_NUM_8723D 4 +#define RF_T_METER_8723D 0x42 + +void ConfigureTxpowerTrack_8723D( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID, +#else + IN PDM_ODM_T pDM_Odm, +#endif + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +VOID +setCCKFilterCoefficient_8723D( + PDM_ODM_T pDM_Odm, + u1Byte CCKSwingIndex +); + +void DoIQK_8723D( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID, +#else + IN PDM_ODM_T pDM_Odm, +#endif + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +ODM_TxXtalTrackSetXtal_8723D( + PVOID pDM_VOID +); + +//1 7. IQK + +void +PHY_IQCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + PVOID pDM_VOID +#else + IN PDM_ODM_T pDM_Odm +#endif +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8723D( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8723D( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +#endif // #ifndef __HAL_PHY_RF_8723D_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8723d/version_rtl8723d.h b/package/kernel/rtl8192cd/phydm/rtl8723d/version_rtl8723d.h index c804051f571..f2314045ce2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8723d/version_rtl8723d.h +++ b/package/kernel/rtl8192cd/phydm/rtl8723d/version_rtl8723d.h @@ -1,5 +1,5 @@ -/*RTL8723D PHY Parameters*/ -#define SVN_COMMIT_VERSION_8723D 16656 -#define RELEASE_DATE_8723D 20160516 -#define COMMIT_BY_8723D "BB_Jessica" -#define RELEASE_VERSION_8723D 28 +/*RTL8723D PHY Parameters*/ +#define SVN_COMMIT_VERSION_8723D 16656 +#define RELEASE_DATE_8723D 20160516 +#define COMMIT_BY_8723D "BB_Jessica" +#define RELEASE_VERSION_8723D 28 diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.c index ee380a8fde0..5d4c21fcdf6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.c @@ -1,1483 +1,1483 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8812A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_AGC_TAB[] = { - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000001, - 0x81C, 0xFB020001, - 0x81C, 0xFA040001, - 0x81C, 0xF9060001, - 0x81C, 0xF8080001, - 0x81C, 0xF70A0001, - 0x81C, 0xF60C0001, - 0x81C, 0xF50E0001, - 0x81C, 0xF4100001, - 0x81C, 0xF3120001, - 0x81C, 0xF2140001, - 0x81C, 0xF1160001, - 0x81C, 0xF0180001, - 0x81C, 0xEF1A0001, - 0x81C, 0xEE1C0001, - 0x81C, 0xED1E0001, - 0x81C, 0xEC200001, - 0x81C, 0xEB220001, - 0x81C, 0xEA240001, - 0x81C, 0xCD260001, - 0x81C, 0xCC280001, - 0x81C, 0xCB2A0001, - 0x81C, 0xCA2C0001, - 0x81C, 0xC92E0001, - 0x81C, 0xC8300001, - 0x81C, 0xA6320001, - 0x81C, 0xA5340001, - 0x81C, 0xA4360001, - 0x81C, 0xA3380001, - 0x81C, 0xA23A0001, - 0x81C, 0x883C0001, - 0x81C, 0x873E0001, - 0x81C, 0x86400001, - 0x81C, 0x85420001, - 0x81C, 0x84440001, - 0x81C, 0x83460001, - 0x81C, 0x82480001, - 0x81C, 0x814A0001, - 0x81C, 0x484C0001, - 0x81C, 0x474E0001, - 0x81C, 0x46500001, - 0x81C, 0x45520001, - 0x81C, 0x44540001, - 0x81C, 0x43560001, - 0x81C, 0x42580001, - 0x81C, 0x415A0001, - 0x81C, 0x255C0001, - 0x81C, 0x245E0001, - 0x81C, 0x23600001, - 0x81C, 0x22620001, - 0x81C, 0x21640001, - 0x81C, 0x21660001, - 0x81C, 0x21680001, - 0x81C, 0x216A0001, - 0x81C, 0x216C0001, - 0x81C, 0x216E0001, - 0x81C, 0x21700001, - 0x81C, 0x21720001, - 0x81C, 0x21740001, - 0x81C, 0x21760001, - 0x81C, 0x21780001, - 0x81C, 0x217A0001, - 0x81C, 0x217C0001, - 0x81C, 0x217E0001, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x81C, 0xF9000001, - 0x81C, 0xF8020001, - 0x81C, 0xF7040001, - 0x81C, 0xF6060001, - 0x81C, 0xF5080001, - 0x81C, 0xF40A0001, - 0x81C, 0xF30C0001, - 0x81C, 0xF20E0001, - 0x81C, 0xF1100001, - 0x81C, 0xF0120001, - 0x81C, 0xEF140001, - 0x81C, 0xEE160001, - 0x81C, 0xED180001, - 0x81C, 0xEC1A0001, - 0x81C, 0xEB1C0001, - 0x81C, 0xEA1E0001, - 0x81C, 0xCD200001, - 0x81C, 0xCC220001, - 0x81C, 0xCB240001, - 0x81C, 0xCA260001, - 0x81C, 0xC9280001, - 0x81C, 0xC82A0001, - 0x81C, 0xC72C0001, - 0x81C, 0xC62E0001, - 0x81C, 0xA5300001, - 0x81C, 0xA4320001, - 0x81C, 0xA3340001, - 0x81C, 0xA2360001, - 0x81C, 0x88380001, - 0x81C, 0x873A0001, - 0x81C, 0x863C0001, - 0x81C, 0x853E0001, - 0x81C, 0x84400001, - 0x81C, 0x83420001, - 0x81C, 0x82440001, - 0x81C, 0x81460001, - 0x81C, 0x48480001, - 0x81C, 0x474A0001, - 0x81C, 0x464C0001, - 0x81C, 0x454E0001, - 0x81C, 0x44500001, - 0x81C, 0x43520001, - 0x81C, 0x42540001, - 0x81C, 0x41560001, - 0x81C, 0x25580001, - 0x81C, 0x245A0001, - 0x81C, 0x235C0001, - 0x81C, 0x225E0001, - 0x81C, 0x21600001, - 0x81C, 0x21620001, - 0x81C, 0x21640001, - 0x81C, 0x21660001, - 0x81C, 0x21680001, - 0x81C, 0x216A0001, - 0x81C, 0x236C0001, - 0x81C, 0x226E0001, - 0x81C, 0x21700001, - 0x81C, 0x21720001, - 0x81C, 0x21740001, - 0x81C, 0x21760001, - 0x81C, 0x21780001, - 0x81C, 0x217A0001, - 0x81C, 0x217C0001, - 0x81C, 0x217E0001, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000001, - 0x81C, 0xFF020001, - 0x81C, 0xFF040001, - 0x81C, 0xFF060001, - 0x81C, 0xFF080001, - 0x81C, 0xFE0A0001, - 0x81C, 0xFD0C0001, - 0x81C, 0xFC0E0001, - 0x81C, 0xFB100001, - 0x81C, 0xFA120001, - 0x81C, 0xF9140001, - 0x81C, 0xF8160001, - 0x81C, 0xF7180001, - 0x81C, 0xF61A0001, - 0x81C, 0xF51C0001, - 0x81C, 0xF41E0001, - 0x81C, 0xF3200001, - 0x81C, 0xF2220001, - 0x81C, 0xF1240001, - 0x81C, 0xF0260001, - 0x81C, 0xEF280001, - 0x81C, 0xEE2A0001, - 0x81C, 0xED2C0001, - 0x81C, 0xEC2E0001, - 0x81C, 0xEB300001, - 0x81C, 0xEA320001, - 0x81C, 0xE9340001, - 0x81C, 0xE8360001, - 0x81C, 0xE7380001, - 0x81C, 0xE63A0001, - 0x81C, 0xE53C0001, - 0x81C, 0xC73E0001, - 0x81C, 0xC6400001, - 0x81C, 0xC5420001, - 0x81C, 0xC4440001, - 0x81C, 0xC3460001, - 0x81C, 0xC2480001, - 0x81C, 0xC14A0001, - 0x81C, 0xA74C0001, - 0x81C, 0xA64E0001, - 0x81C, 0xA5500001, - 0x81C, 0xA4520001, - 0x81C, 0xA3540001, - 0x81C, 0xA2560001, - 0x81C, 0xA1580001, - 0x81C, 0x675A0001, - 0x81C, 0x665C0001, - 0x81C, 0x655E0001, - 0x81C, 0x64600001, - 0x81C, 0x63620001, - 0x81C, 0x48640001, - 0x81C, 0x47660001, - 0x81C, 0x46680001, - 0x81C, 0x456A0001, - 0x81C, 0x446C0001, - 0x81C, 0x436E0001, - 0x81C, 0x42700001, - 0x81C, 0x41720001, - 0x81C, 0x41740001, - 0x81C, 0x41760001, - 0x81C, 0x41780001, - 0x81C, 0x417A0001, - 0x81C, 0x417C0001, - 0x81C, 0x417E0001, - 0xB0000000, 0x00000000, - 0x80000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC800001, - 0x81C, 0xFB820001, - 0x81C, 0xFA840001, - 0x81C, 0xF9860001, - 0x81C, 0xF8880001, - 0x81C, 0xF78A0001, - 0x81C, 0xF68C0001, - 0x81C, 0xF58E0001, - 0x81C, 0xF4900001, - 0x81C, 0xF3920001, - 0x81C, 0xF2940001, - 0x81C, 0xF1960001, - 0x81C, 0xF0980001, - 0x81C, 0xEF9A0001, - 0x81C, 0xEE9C0001, - 0x81C, 0xED9E0001, - 0x81C, 0xECA00001, - 0x81C, 0xEBA20001, - 0x81C, 0xEAA40001, - 0x81C, 0xE9A60001, - 0x81C, 0xE8A80001, - 0x81C, 0xE7AA0001, - 0x81C, 0xE6AC0001, - 0x81C, 0xE5AE0001, - 0x81C, 0xE4B00001, - 0x81C, 0xE3B20001, - 0x81C, 0xA8B40001, - 0x81C, 0xA7B60001, - 0x81C, 0xA6B80001, - 0x81C, 0xA5BA0001, - 0x81C, 0xA4BC0001, - 0x81C, 0xA3BE0001, - 0x81C, 0xA2C00001, - 0x81C, 0xA1C20001, - 0x81C, 0x68C40001, - 0x81C, 0x67C60001, - 0x81C, 0x66C80001, - 0x81C, 0x65CA0001, - 0x81C, 0x64CC0001, - 0x81C, 0x47CE0001, - 0x81C, 0x46D00001, - 0x81C, 0x45D20001, - 0x81C, 0x44D40001, - 0x81C, 0x43D60001, - 0x81C, 0x42D80001, - 0x81C, 0x08DA0001, - 0x81C, 0x07DC0001, - 0x81C, 0x06DE0001, - 0x81C, 0x05E00001, - 0x81C, 0x04E20001, - 0x81C, 0x03E40001, - 0x81C, 0x02E60001, - 0x81C, 0x01E80001, - 0x81C, 0x01EA0001, - 0x81C, 0x01EC0001, - 0x81C, 0x01EE0001, - 0x81C, 0x01F00001, - 0x81C, 0x01F20001, - 0x81C, 0x01F40001, - 0x81C, 0x01F60001, - 0x81C, 0x01F80001, - 0x81C, 0x01FA0001, - 0x81C, 0x01FC0001, - 0x81C, 0x01FE0001, - 0xA0000000, 0x00000000, - 0x81C, 0xFF800001, - 0x81C, 0xFF820001, - 0x81C, 0xFF840001, - 0x81C, 0xFE860001, - 0x81C, 0xFD880001, - 0x81C, 0xFC8A0001, - 0x81C, 0xFB8C0001, - 0x81C, 0xFA8E0001, - 0x81C, 0xF9900001, - 0x81C, 0xF8920001, - 0x81C, 0xF7940001, - 0x81C, 0xF6960001, - 0x81C, 0xF5980001, - 0x81C, 0xF49A0001, - 0x81C, 0xF39C0001, - 0x81C, 0xF29E0001, - 0x81C, 0xF1A00001, - 0x81C, 0xF0A20001, - 0x81C, 0xEFA40001, - 0x81C, 0xEEA60001, - 0x81C, 0xEDA80001, - 0x81C, 0xECAA0001, - 0x81C, 0xEBAC0001, - 0x81C, 0xEAAE0001, - 0x81C, 0xE9B00001, - 0x81C, 0xE8B20001, - 0x81C, 0xE7B40001, - 0x81C, 0xE6B60001, - 0x81C, 0xE5B80001, - 0x81C, 0xE4BA0001, - 0x81C, 0xE3BC0001, - 0x81C, 0xA8BE0001, - 0x81C, 0xA7C00001, - 0x81C, 0xA6C20001, - 0x81C, 0xA5C40001, - 0x81C, 0xA4C60001, - 0x81C, 0xA3C80001, - 0x81C, 0xA2CA0001, - 0x81C, 0xA1CC0001, - 0x81C, 0x68CE0001, - 0x81C, 0x67D00001, - 0x81C, 0x66D20001, - 0x81C, 0x65D40001, - 0x81C, 0x64D60001, - 0x81C, 0x47D80001, - 0x81C, 0x46DA0001, - 0x81C, 0x45DC0001, - 0x81C, 0x44DE0001, - 0x81C, 0x43E00001, - 0x81C, 0x42E20001, - 0x81C, 0x08E40001, - 0x81C, 0x07E60001, - 0x81C, 0x06E80001, - 0x81C, 0x05EA0001, - 0x81C, 0x04EC0001, - 0x81C, 0x03EE0001, - 0x81C, 0x02F00001, - 0x81C, 0x01F20001, - 0x81C, 0x01F40001, - 0x81C, 0x01F60001, - 0x81C, 0x01F80001, - 0x81C, 0x01FA0001, - 0x81C, 0x01FC0001, - 0x81C, 0x01FE0001, - 0xB0000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - -}; - -void -ODM_ReadAndConfig_MP_8812A_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8812A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_AGC_TAB(void) -{ - return 57; -} - -/****************************************************************************** -* AGC_TAB_DIFF.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_AGC_TAB_DIFF_LB[] = { - 0x80000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0x47CE0001, - 0x81C, 0x46D00001, - 0x81C, 0x45D20001, - 0x81C, 0x44D40001, - 0x81C, 0x43D60001, - 0x81C, 0x42D80001, - 0x81C, 0x08DA0001, - 0x81C, 0x07DC0001, - 0x81C, 0x06DE0001, - 0x81C, 0x05E00001, - 0x81C, 0x04E20001, - 0x81C, 0x03E40001, - 0x81C, 0x02E60001, - 0xA0000000, 0x00000000, - 0x81C, 0x47D80001, - 0x81C, 0x46DA0001, - 0x81C, 0x45DC0001, - 0x81C, 0x44DE0001, - 0x81C, 0x43E00001, - 0x81C, 0x42E20001, - 0x81C, 0x08E40001, - 0x81C, 0x07E60001, - 0x81C, 0x06E80001, - 0x81C, 0x05EA0001, - 0x81C, 0x04EC0001, - 0x81C, 0x03EE0001, - 0x81C, 0x02F00001, - 0xB0000000, 0x00000000, -}; - -u4Byte Array_MP_8812A_AGC_TAB_DIFF_HB[] = { - 0x80000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0x45CE0001, - 0x81C, 0x44D00001, - 0x81C, 0x43D20001, - 0x81C, 0x42D40001, - 0x81C, 0x08D60001, - 0x81C, 0x07D80001, - 0x81C, 0x06DA0001, - 0x81C, 0x05DC0001, - 0x81C, 0x04DE0001, - 0x81C, 0x03E00001, - 0x81C, 0x02E20001, - 0x81C, 0x01E40001, - 0x81C, 0x01E60001, - 0xA0000000, 0x00000000, - 0x81C, 0x45D80001, - 0x81C, 0x44DA0001, - 0x81C, 0x43DC0001, - 0x81C, 0x42DE0001, - 0x81C, 0x08E00001, - 0x81C, 0x07E20001, - 0x81C, 0x06E40001, - 0x81C, 0x05E60001, - 0x81C, 0x04E80001, - 0x81C, 0x03EA0001, - 0x81C, 0x02EC0001, - 0x81C, 0x01EE0001, - 0x81C, 0x01F00001, - 0xB0000000, 0x00000000, -}; - -void -ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Array[], - IN u4Byte ArrayLen -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8812A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_AGC_TAB_DIFF(void) -{ - return 57; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG[] = { - 0x800, 0x8020D010, - 0x804, 0x080112E0, - 0x808, 0x0E028233, - 0x80C, 0x12131113, - 0x810, 0x20101263, - 0x814, 0x020C3D10, - 0x818, 0x03A00385, - 0x820, 0x00000000, - 0x824, 0x00030FE0, - 0x828, 0x00000000, - 0x82C, 0x002083DD, - 0x830, 0x2EAAEEB8, - 0x834, 0x0037A706, - 0x838, 0x06C89B44, - 0x83C, 0x0000095B, - 0x840, 0xC0000001, - 0x844, 0x40003CDE, - 0x848, 0x6210FF8B, - 0x84C, 0x6CFDFFB8, - 0x850, 0x28874706, - 0x854, 0x0001520C, - 0x858, 0x8060E000, - 0x85C, 0x74210168, - 0x860, 0x6929C321, - 0x864, 0x79727432, - 0x868, 0x8CA7A314, - 0x86C, 0x338C2878, - 0x870, 0x03333333, - 0x874, 0x31602C2E, - 0x878, 0x00003152, - 0x87C, 0x000FC000, - 0x8A0, 0x00000013, - 0x8A4, 0x7F7F7F7F, - 0x8A8, 0xA202033E, - 0x8AC, 0x0FF0FA0A, - 0x8B0, 0x00000600, - 0x8B4, 0x000FC080, - 0x8B8, 0x6C0057FF, - 0x8BC, 0x4CA520A3, - 0x8C0, 0x27F00020, - 0x8C4, 0x00000000, - 0x8C8, 0x00012D69, - 0x8CC, 0x08248492, - 0x8D0, 0x0000B800, - 0x8DC, 0x00000000, - 0x8D4, 0x940008A0, - 0x8D8, 0x290B5612, - 0x8F8, 0x400002C0, - 0x8FC, 0x00000000, - 0x900, 0x00000701, - 0x90C, 0x00000000, - 0x910, 0x0000FC00, - 0x914, 0x00000404, - 0x918, 0x1C1028C0, - 0x91C, 0x64B11A1C, - 0x920, 0xE0767233, - 0x924, 0x055AA500, - 0x928, 0x00000004, - 0x92C, 0xFFFE0000, - 0x930, 0xFFFFFFFE, - 0x934, 0x001FFFFF, - 0x960, 0x00000000, - 0x964, 0x00000000, - 0x968, 0x00000000, - 0x96C, 0x00000000, - 0x970, 0x801FFFFF, - 0x978, 0x00000000, - 0x97C, 0x00000000, - 0x980, 0x00000000, - 0x984, 0x00000000, - 0x988, 0x00000000, - 0x990, 0x27100000, - 0x994, 0xFFFF0100, - 0x998, 0xFFFFFF5C, - 0x99C, 0xFFFFFFFF, - 0x9A0, 0x000000FF, - 0x9A4, 0x00080080, - 0x9A8, 0x00000000, - 0x9AC, 0x00000000, - 0x9B0, 0x81081008, - 0x9B4, 0x00000000, - 0x9B8, 0x01081008, - 0x9BC, 0x01081008, - 0x9D0, 0x00000000, - 0x9D4, 0x00000000, - 0x9D8, 0x00000000, - 0x9DC, 0x00000000, - 0x9E4, 0x00000003, - 0x9E8, 0x000002D5, - 0xA00, 0x00D047C8, - 0xA04, 0x01FF000C, - 0xA08, 0x8C838300, - 0xA0C, 0x2E7F000F, - 0xA10, 0x9500BB78, - 0xA14, 0x11144028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1217, - 0xA28, 0x00000305, - 0xA2C, 0x00900000, - 0xA70, 0x101FFF00, - 0xA74, 0x00000008, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0xA80, 0x218075B2, - 0xA84, 0x001F8C80, - 0xB00, 0x03100000, - 0xB04, 0x0000B000, - 0xB08, 0xAE0201EB, - 0xB0C, 0x01003207, - 0xB10, 0x00009807, - 0xB14, 0x01000000, - 0xB18, 0x00000002, - 0xB1C, 0x00000002, - 0xB20, 0x0000001F, - 0xB24, 0x03020100, - 0xB28, 0x07060504, - 0xB2C, 0x0B0A0908, - 0xB30, 0x0F0E0D0C, - 0xB34, 0x13121110, - 0xB38, 0x17161514, - 0xB3C, 0x0000003A, - 0xB40, 0x00000000, - 0xB44, 0x00000000, - 0xB48, 0x13000032, - 0xB4C, 0x48080000, - 0xB50, 0x00000000, - 0xB54, 0x00000000, - 0xB58, 0x00000000, - 0xB5C, 0x00000000, - 0xC00, 0x00000007, - 0xC04, 0x00042020, - 0xC08, 0x80410231, - 0xC0C, 0x00000000, - 0xC10, 0x00000100, - 0xC14, 0x01000000, - 0xC1C, 0x40000003, - 0xC20, 0x12121212, - 0xC24, 0x12121212, - 0xC28, 0x12121212, - 0xC2C, 0x12121212, - 0xC30, 0x12121212, - 0xC34, 0x12121212, - 0xC38, 0x12121212, - 0xC3C, 0x12121212, - 0xC40, 0x12121212, - 0xC44, 0x12121212, - 0xC48, 0x12121212, - 0xC4C, 0x12121212, - 0xC50, 0x00000020, - 0xC54, 0x0008121C, - 0xC58, 0x30000C1C, - 0xC5C, 0x00000058, - 0xC60, 0x34344443, - 0xC64, 0x07003333, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0xC68, 0x59791979, - 0xA0000000, 0x00000000, - 0xC68, 0x59799979, - 0xB0000000, 0x00000000, - 0xC6C, 0x59795979, - 0xC70, 0x19795979, - 0xC74, 0x19795979, - 0xC78, 0x19791979, - 0xC7C, 0x19791979, - 0xC80, 0x19791979, - 0xC84, 0x19791979, - 0xC94, 0x0100005C, - 0xC98, 0x00000000, - 0xC9C, 0x00000000, - 0xCA0, 0x00000029, - 0xCA4, 0x08040201, - 0xCA8, 0x80402010, - 0xCB0, 0x77547777, - 0xCB4, 0x00000077, - 0xCB8, 0x00508242, - 0xE00, 0x00000007, - 0xE04, 0x00042020, - 0xE08, 0x80410231, - 0xE0C, 0x00000000, - 0xE10, 0x00000100, - 0xE14, 0x01000000, - 0xE1C, 0x40000003, - 0xE20, 0x12121212, - 0xE24, 0x12121212, - 0xE28, 0x12121212, - 0xE2C, 0x12121212, - 0xE30, 0x12121212, - 0xE34, 0x12121212, - 0xE38, 0x12121212, - 0xE3C, 0x12121212, - 0xE40, 0x12121212, - 0xE44, 0x12121212, - 0xE48, 0x12121212, - 0xE4C, 0x12121212, - 0xE50, 0x00000020, - 0xE54, 0x0008121C, - 0xE58, 0x30000C1C, - 0xE5C, 0x00000058, - 0xE60, 0x34344443, - 0xE64, 0x07003333, - 0xE68, 0x59791979, - 0xE6C, 0x59795979, - 0xE70, 0x19795979, - 0xE74, 0x19795979, - 0xE78, 0x19791979, - 0xE7C, 0x19791979, - 0xE80, 0x19791979, - 0xE84, 0x19791979, - 0xE94, 0x0100005C, - 0xE98, 0x00000000, - 0xE9C, 0x00000000, - 0xEA0, 0x00000029, - 0xEA4, 0x08040201, - 0xEA8, 0x80402010, - 0xEB0, 0x77547777, - 0xEB4, 0x00000077, - 0xEB8, 0x00508242, - -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8812A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_PHY_REG(void) -{ - return 57; -} - -/****************************************************************************** -* PHY_REG_MP.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_MP[] = { - 0x800, 0x8020D410, - 0x830, 0x2EAA8EB8, - -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_MP( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_MP)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_MP; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_MP\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8812A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_PHY_REG_MP(void) -{ - return 57; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_ASUS.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_PG_ASUS[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303232, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303232, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x32323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303232, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303232, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x32323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322222, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303232, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322222, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303232, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22222426 -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_ASUS)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_PG_ASUS; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_DNI.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_PG_DNI[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x33333333, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x28282828, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x28282828, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x28282828, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x33333333, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28282828, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x28282828, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28282828, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x28282828, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x28282828, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x28282828, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24242424, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x24242424, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24242424, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x24242424, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x24242424, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24242424, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x24242424, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24242424, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x24242424, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x24242424, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x24242424 -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_DNI)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_PG_DNI; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_NEC.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_PG_NEC[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x32343434, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x32343434, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x34342022, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x32343434, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32343434, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x32343434, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x34342022, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x32343434, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x28282828, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262828, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x28282022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28282828, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x32343434, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343434, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x28282828, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262828, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343434, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x28282022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28282828, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_NEC)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_PG_NEC; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_TPLINK.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_PHY_REG_PG_TPLINK[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x36363840, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x38404040, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x36383840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363638, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x36363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x36382426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323434, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x36363840, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x38404040, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x36383840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363638, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x36363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x36382426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323434, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x38404040, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x36383840, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x34363638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363840, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323434, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x38404040, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x36383840, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x34363638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x36363840, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323434, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 -}; - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_TPLINK)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_PHY_REG_PG_TPLINK; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8812A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_AGC_TAB[] = { + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000001, + 0x81C, 0xFB020001, + 0x81C, 0xFA040001, + 0x81C, 0xF9060001, + 0x81C, 0xF8080001, + 0x81C, 0xF70A0001, + 0x81C, 0xF60C0001, + 0x81C, 0xF50E0001, + 0x81C, 0xF4100001, + 0x81C, 0xF3120001, + 0x81C, 0xF2140001, + 0x81C, 0xF1160001, + 0x81C, 0xF0180001, + 0x81C, 0xEF1A0001, + 0x81C, 0xEE1C0001, + 0x81C, 0xED1E0001, + 0x81C, 0xEC200001, + 0x81C, 0xEB220001, + 0x81C, 0xEA240001, + 0x81C, 0xCD260001, + 0x81C, 0xCC280001, + 0x81C, 0xCB2A0001, + 0x81C, 0xCA2C0001, + 0x81C, 0xC92E0001, + 0x81C, 0xC8300001, + 0x81C, 0xA6320001, + 0x81C, 0xA5340001, + 0x81C, 0xA4360001, + 0x81C, 0xA3380001, + 0x81C, 0xA23A0001, + 0x81C, 0x883C0001, + 0x81C, 0x873E0001, + 0x81C, 0x86400001, + 0x81C, 0x85420001, + 0x81C, 0x84440001, + 0x81C, 0x83460001, + 0x81C, 0x82480001, + 0x81C, 0x814A0001, + 0x81C, 0x484C0001, + 0x81C, 0x474E0001, + 0x81C, 0x46500001, + 0x81C, 0x45520001, + 0x81C, 0x44540001, + 0x81C, 0x43560001, + 0x81C, 0x42580001, + 0x81C, 0x415A0001, + 0x81C, 0x255C0001, + 0x81C, 0x245E0001, + 0x81C, 0x23600001, + 0x81C, 0x22620001, + 0x81C, 0x21640001, + 0x81C, 0x21660001, + 0x81C, 0x21680001, + 0x81C, 0x216A0001, + 0x81C, 0x216C0001, + 0x81C, 0x216E0001, + 0x81C, 0x21700001, + 0x81C, 0x21720001, + 0x81C, 0x21740001, + 0x81C, 0x21760001, + 0x81C, 0x21780001, + 0x81C, 0x217A0001, + 0x81C, 0x217C0001, + 0x81C, 0x217E0001, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x81C, 0xF9000001, + 0x81C, 0xF8020001, + 0x81C, 0xF7040001, + 0x81C, 0xF6060001, + 0x81C, 0xF5080001, + 0x81C, 0xF40A0001, + 0x81C, 0xF30C0001, + 0x81C, 0xF20E0001, + 0x81C, 0xF1100001, + 0x81C, 0xF0120001, + 0x81C, 0xEF140001, + 0x81C, 0xEE160001, + 0x81C, 0xED180001, + 0x81C, 0xEC1A0001, + 0x81C, 0xEB1C0001, + 0x81C, 0xEA1E0001, + 0x81C, 0xCD200001, + 0x81C, 0xCC220001, + 0x81C, 0xCB240001, + 0x81C, 0xCA260001, + 0x81C, 0xC9280001, + 0x81C, 0xC82A0001, + 0x81C, 0xC72C0001, + 0x81C, 0xC62E0001, + 0x81C, 0xA5300001, + 0x81C, 0xA4320001, + 0x81C, 0xA3340001, + 0x81C, 0xA2360001, + 0x81C, 0x88380001, + 0x81C, 0x873A0001, + 0x81C, 0x863C0001, + 0x81C, 0x853E0001, + 0x81C, 0x84400001, + 0x81C, 0x83420001, + 0x81C, 0x82440001, + 0x81C, 0x81460001, + 0x81C, 0x48480001, + 0x81C, 0x474A0001, + 0x81C, 0x464C0001, + 0x81C, 0x454E0001, + 0x81C, 0x44500001, + 0x81C, 0x43520001, + 0x81C, 0x42540001, + 0x81C, 0x41560001, + 0x81C, 0x25580001, + 0x81C, 0x245A0001, + 0x81C, 0x235C0001, + 0x81C, 0x225E0001, + 0x81C, 0x21600001, + 0x81C, 0x21620001, + 0x81C, 0x21640001, + 0x81C, 0x21660001, + 0x81C, 0x21680001, + 0x81C, 0x216A0001, + 0x81C, 0x236C0001, + 0x81C, 0x226E0001, + 0x81C, 0x21700001, + 0x81C, 0x21720001, + 0x81C, 0x21740001, + 0x81C, 0x21760001, + 0x81C, 0x21780001, + 0x81C, 0x217A0001, + 0x81C, 0x217C0001, + 0x81C, 0x217E0001, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000001, + 0x81C, 0xFF020001, + 0x81C, 0xFF040001, + 0x81C, 0xFF060001, + 0x81C, 0xFF080001, + 0x81C, 0xFE0A0001, + 0x81C, 0xFD0C0001, + 0x81C, 0xFC0E0001, + 0x81C, 0xFB100001, + 0x81C, 0xFA120001, + 0x81C, 0xF9140001, + 0x81C, 0xF8160001, + 0x81C, 0xF7180001, + 0x81C, 0xF61A0001, + 0x81C, 0xF51C0001, + 0x81C, 0xF41E0001, + 0x81C, 0xF3200001, + 0x81C, 0xF2220001, + 0x81C, 0xF1240001, + 0x81C, 0xF0260001, + 0x81C, 0xEF280001, + 0x81C, 0xEE2A0001, + 0x81C, 0xED2C0001, + 0x81C, 0xEC2E0001, + 0x81C, 0xEB300001, + 0x81C, 0xEA320001, + 0x81C, 0xE9340001, + 0x81C, 0xE8360001, + 0x81C, 0xE7380001, + 0x81C, 0xE63A0001, + 0x81C, 0xE53C0001, + 0x81C, 0xC73E0001, + 0x81C, 0xC6400001, + 0x81C, 0xC5420001, + 0x81C, 0xC4440001, + 0x81C, 0xC3460001, + 0x81C, 0xC2480001, + 0x81C, 0xC14A0001, + 0x81C, 0xA74C0001, + 0x81C, 0xA64E0001, + 0x81C, 0xA5500001, + 0x81C, 0xA4520001, + 0x81C, 0xA3540001, + 0x81C, 0xA2560001, + 0x81C, 0xA1580001, + 0x81C, 0x675A0001, + 0x81C, 0x665C0001, + 0x81C, 0x655E0001, + 0x81C, 0x64600001, + 0x81C, 0x63620001, + 0x81C, 0x48640001, + 0x81C, 0x47660001, + 0x81C, 0x46680001, + 0x81C, 0x456A0001, + 0x81C, 0x446C0001, + 0x81C, 0x436E0001, + 0x81C, 0x42700001, + 0x81C, 0x41720001, + 0x81C, 0x41740001, + 0x81C, 0x41760001, + 0x81C, 0x41780001, + 0x81C, 0x417A0001, + 0x81C, 0x417C0001, + 0x81C, 0x417E0001, + 0xB0000000, 0x00000000, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC800001, + 0x81C, 0xFB820001, + 0x81C, 0xFA840001, + 0x81C, 0xF9860001, + 0x81C, 0xF8880001, + 0x81C, 0xF78A0001, + 0x81C, 0xF68C0001, + 0x81C, 0xF58E0001, + 0x81C, 0xF4900001, + 0x81C, 0xF3920001, + 0x81C, 0xF2940001, + 0x81C, 0xF1960001, + 0x81C, 0xF0980001, + 0x81C, 0xEF9A0001, + 0x81C, 0xEE9C0001, + 0x81C, 0xED9E0001, + 0x81C, 0xECA00001, + 0x81C, 0xEBA20001, + 0x81C, 0xEAA40001, + 0x81C, 0xE9A60001, + 0x81C, 0xE8A80001, + 0x81C, 0xE7AA0001, + 0x81C, 0xE6AC0001, + 0x81C, 0xE5AE0001, + 0x81C, 0xE4B00001, + 0x81C, 0xE3B20001, + 0x81C, 0xA8B40001, + 0x81C, 0xA7B60001, + 0x81C, 0xA6B80001, + 0x81C, 0xA5BA0001, + 0x81C, 0xA4BC0001, + 0x81C, 0xA3BE0001, + 0x81C, 0xA2C00001, + 0x81C, 0xA1C20001, + 0x81C, 0x68C40001, + 0x81C, 0x67C60001, + 0x81C, 0x66C80001, + 0x81C, 0x65CA0001, + 0x81C, 0x64CC0001, + 0x81C, 0x47CE0001, + 0x81C, 0x46D00001, + 0x81C, 0x45D20001, + 0x81C, 0x44D40001, + 0x81C, 0x43D60001, + 0x81C, 0x42D80001, + 0x81C, 0x08DA0001, + 0x81C, 0x07DC0001, + 0x81C, 0x06DE0001, + 0x81C, 0x05E00001, + 0x81C, 0x04E20001, + 0x81C, 0x03E40001, + 0x81C, 0x02E60001, + 0x81C, 0x01E80001, + 0x81C, 0x01EA0001, + 0x81C, 0x01EC0001, + 0x81C, 0x01EE0001, + 0x81C, 0x01F00001, + 0x81C, 0x01F20001, + 0x81C, 0x01F40001, + 0x81C, 0x01F60001, + 0x81C, 0x01F80001, + 0x81C, 0x01FA0001, + 0x81C, 0x01FC0001, + 0x81C, 0x01FE0001, + 0xA0000000, 0x00000000, + 0x81C, 0xFF800001, + 0x81C, 0xFF820001, + 0x81C, 0xFF840001, + 0x81C, 0xFE860001, + 0x81C, 0xFD880001, + 0x81C, 0xFC8A0001, + 0x81C, 0xFB8C0001, + 0x81C, 0xFA8E0001, + 0x81C, 0xF9900001, + 0x81C, 0xF8920001, + 0x81C, 0xF7940001, + 0x81C, 0xF6960001, + 0x81C, 0xF5980001, + 0x81C, 0xF49A0001, + 0x81C, 0xF39C0001, + 0x81C, 0xF29E0001, + 0x81C, 0xF1A00001, + 0x81C, 0xF0A20001, + 0x81C, 0xEFA40001, + 0x81C, 0xEEA60001, + 0x81C, 0xEDA80001, + 0x81C, 0xECAA0001, + 0x81C, 0xEBAC0001, + 0x81C, 0xEAAE0001, + 0x81C, 0xE9B00001, + 0x81C, 0xE8B20001, + 0x81C, 0xE7B40001, + 0x81C, 0xE6B60001, + 0x81C, 0xE5B80001, + 0x81C, 0xE4BA0001, + 0x81C, 0xE3BC0001, + 0x81C, 0xA8BE0001, + 0x81C, 0xA7C00001, + 0x81C, 0xA6C20001, + 0x81C, 0xA5C40001, + 0x81C, 0xA4C60001, + 0x81C, 0xA3C80001, + 0x81C, 0xA2CA0001, + 0x81C, 0xA1CC0001, + 0x81C, 0x68CE0001, + 0x81C, 0x67D00001, + 0x81C, 0x66D20001, + 0x81C, 0x65D40001, + 0x81C, 0x64D60001, + 0x81C, 0x47D80001, + 0x81C, 0x46DA0001, + 0x81C, 0x45DC0001, + 0x81C, 0x44DE0001, + 0x81C, 0x43E00001, + 0x81C, 0x42E20001, + 0x81C, 0x08E40001, + 0x81C, 0x07E60001, + 0x81C, 0x06E80001, + 0x81C, 0x05EA0001, + 0x81C, 0x04EC0001, + 0x81C, 0x03EE0001, + 0x81C, 0x02F00001, + 0x81C, 0x01F20001, + 0x81C, 0x01F40001, + 0x81C, 0x01F60001, + 0x81C, 0x01F80001, + 0x81C, 0x01FA0001, + 0x81C, 0x01FC0001, + 0x81C, 0x01FE0001, + 0xB0000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + +}; + +void +ODM_ReadAndConfig_MP_8812A_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8812A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_AGC_TAB(void) +{ + return 57; +} + +/****************************************************************************** +* AGC_TAB_DIFF.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_AGC_TAB_DIFF_LB[] = { + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0x47CE0001, + 0x81C, 0x46D00001, + 0x81C, 0x45D20001, + 0x81C, 0x44D40001, + 0x81C, 0x43D60001, + 0x81C, 0x42D80001, + 0x81C, 0x08DA0001, + 0x81C, 0x07DC0001, + 0x81C, 0x06DE0001, + 0x81C, 0x05E00001, + 0x81C, 0x04E20001, + 0x81C, 0x03E40001, + 0x81C, 0x02E60001, + 0xA0000000, 0x00000000, + 0x81C, 0x47D80001, + 0x81C, 0x46DA0001, + 0x81C, 0x45DC0001, + 0x81C, 0x44DE0001, + 0x81C, 0x43E00001, + 0x81C, 0x42E20001, + 0x81C, 0x08E40001, + 0x81C, 0x07E60001, + 0x81C, 0x06E80001, + 0x81C, 0x05EA0001, + 0x81C, 0x04EC0001, + 0x81C, 0x03EE0001, + 0x81C, 0x02F00001, + 0xB0000000, 0x00000000, +}; + +u4Byte Array_MP_8812A_AGC_TAB_DIFF_HB[] = { + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0x45CE0001, + 0x81C, 0x44D00001, + 0x81C, 0x43D20001, + 0x81C, 0x42D40001, + 0x81C, 0x08D60001, + 0x81C, 0x07D80001, + 0x81C, 0x06DA0001, + 0x81C, 0x05DC0001, + 0x81C, 0x04DE0001, + 0x81C, 0x03E00001, + 0x81C, 0x02E20001, + 0x81C, 0x01E40001, + 0x81C, 0x01E60001, + 0xA0000000, 0x00000000, + 0x81C, 0x45D80001, + 0x81C, 0x44DA0001, + 0x81C, 0x43DC0001, + 0x81C, 0x42DE0001, + 0x81C, 0x08E00001, + 0x81C, 0x07E20001, + 0x81C, 0x06E40001, + 0x81C, 0x05E60001, + 0x81C, 0x04E80001, + 0x81C, 0x03EA0001, + 0x81C, 0x02EC0001, + 0x81C, 0x01EE0001, + 0x81C, 0x01F00001, + 0xB0000000, 0x00000000, +}; + +void +ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Array[], + IN u4Byte ArrayLen +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8812A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_AGC_TAB_DIFF(void) +{ + return 57; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG[] = { + 0x800, 0x8020D010, + 0x804, 0x080112E0, + 0x808, 0x0E028233, + 0x80C, 0x12131113, + 0x810, 0x20101263, + 0x814, 0x020C3D10, + 0x818, 0x03A00385, + 0x820, 0x00000000, + 0x824, 0x00030FE0, + 0x828, 0x00000000, + 0x82C, 0x002083DD, + 0x830, 0x2EAAEEB8, + 0x834, 0x0037A706, + 0x838, 0x06C89B44, + 0x83C, 0x0000095B, + 0x840, 0xC0000001, + 0x844, 0x40003CDE, + 0x848, 0x6210FF8B, + 0x84C, 0x6CFDFFB8, + 0x850, 0x28874706, + 0x854, 0x0001520C, + 0x858, 0x8060E000, + 0x85C, 0x74210168, + 0x860, 0x6929C321, + 0x864, 0x79727432, + 0x868, 0x8CA7A314, + 0x86C, 0x338C2878, + 0x870, 0x03333333, + 0x874, 0x31602C2E, + 0x878, 0x00003152, + 0x87C, 0x000FC000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0xA202033E, + 0x8AC, 0x0FF0FA0A, + 0x8B0, 0x00000600, + 0x8B4, 0x000FC080, + 0x8B8, 0x6C0057FF, + 0x8BC, 0x4CA520A3, + 0x8C0, 0x27F00020, + 0x8C4, 0x00000000, + 0x8C8, 0x00012D69, + 0x8CC, 0x08248492, + 0x8D0, 0x0000B800, + 0x8DC, 0x00000000, + 0x8D4, 0x940008A0, + 0x8D8, 0x290B5612, + 0x8F8, 0x400002C0, + 0x8FC, 0x00000000, + 0x900, 0x00000701, + 0x90C, 0x00000000, + 0x910, 0x0000FC00, + 0x914, 0x00000404, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x055AA500, + 0x928, 0x00000004, + 0x92C, 0xFFFE0000, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x801FFFFF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x00080080, + 0x9A8, 0x00000000, + 0x9AC, 0x00000000, + 0x9B0, 0x81081008, + 0x9B4, 0x00000000, + 0x9B8, 0x01081008, + 0x9BC, 0x01081008, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E4, 0x00000003, + 0x9E8, 0x000002D5, + 0xA00, 0x00D047C8, + 0xA04, 0x01FF000C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E7F000F, + 0xA10, 0x9500BB78, + 0xA14, 0x11144028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1217, + 0xA28, 0x00000305, + 0xA2C, 0x00900000, + 0xA70, 0x101FFF00, + 0xA74, 0x00000008, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x218075B2, + 0xA84, 0x001F8C80, + 0xB00, 0x03100000, + 0xB04, 0x0000B000, + 0xB08, 0xAE0201EB, + 0xB0C, 0x01003207, + 0xB10, 0x00009807, + 0xB14, 0x01000000, + 0xB18, 0x00000002, + 0xB1C, 0x00000002, + 0xB20, 0x0000001F, + 0xB24, 0x03020100, + 0xB28, 0x07060504, + 0xB2C, 0x0B0A0908, + 0xB30, 0x0F0E0D0C, + 0xB34, 0x13121110, + 0xB38, 0x17161514, + 0xB3C, 0x0000003A, + 0xB40, 0x00000000, + 0xB44, 0x00000000, + 0xB48, 0x13000032, + 0xB4C, 0x48080000, + 0xB50, 0x00000000, + 0xB54, 0x00000000, + 0xB58, 0x00000000, + 0xB5C, 0x00000000, + 0xC00, 0x00000007, + 0xC04, 0x00042020, + 0xC08, 0x80410231, + 0xC0C, 0x00000000, + 0xC10, 0x00000100, + 0xC14, 0x01000000, + 0xC1C, 0x40000003, + 0xC20, 0x12121212, + 0xC24, 0x12121212, + 0xC28, 0x12121212, + 0xC2C, 0x12121212, + 0xC30, 0x12121212, + 0xC34, 0x12121212, + 0xC38, 0x12121212, + 0xC3C, 0x12121212, + 0xC40, 0x12121212, + 0xC44, 0x12121212, + 0xC48, 0x12121212, + 0xC4C, 0x12121212, + 0xC50, 0x00000020, + 0xC54, 0x0008121C, + 0xC58, 0x30000C1C, + 0xC5C, 0x00000058, + 0xC60, 0x34344443, + 0xC64, 0x07003333, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0xC68, 0x59791979, + 0xA0000000, 0x00000000, + 0xC68, 0x59799979, + 0xB0000000, 0x00000000, + 0xC6C, 0x59795979, + 0xC70, 0x19795979, + 0xC74, 0x19795979, + 0xC78, 0x19791979, + 0xC7C, 0x19791979, + 0xC80, 0x19791979, + 0xC84, 0x19791979, + 0xC94, 0x0100005C, + 0xC98, 0x00000000, + 0xC9C, 0x00000000, + 0xCA0, 0x00000029, + 0xCA4, 0x08040201, + 0xCA8, 0x80402010, + 0xCB0, 0x77547777, + 0xCB4, 0x00000077, + 0xCB8, 0x00508242, + 0xE00, 0x00000007, + 0xE04, 0x00042020, + 0xE08, 0x80410231, + 0xE0C, 0x00000000, + 0xE10, 0x00000100, + 0xE14, 0x01000000, + 0xE1C, 0x40000003, + 0xE20, 0x12121212, + 0xE24, 0x12121212, + 0xE28, 0x12121212, + 0xE2C, 0x12121212, + 0xE30, 0x12121212, + 0xE34, 0x12121212, + 0xE38, 0x12121212, + 0xE3C, 0x12121212, + 0xE40, 0x12121212, + 0xE44, 0x12121212, + 0xE48, 0x12121212, + 0xE4C, 0x12121212, + 0xE50, 0x00000020, + 0xE54, 0x0008121C, + 0xE58, 0x30000C1C, + 0xE5C, 0x00000058, + 0xE60, 0x34344443, + 0xE64, 0x07003333, + 0xE68, 0x59791979, + 0xE6C, 0x59795979, + 0xE70, 0x19795979, + 0xE74, 0x19795979, + 0xE78, 0x19791979, + 0xE7C, 0x19791979, + 0xE80, 0x19791979, + 0xE84, 0x19791979, + 0xE94, 0x0100005C, + 0xE98, 0x00000000, + 0xE9C, 0x00000000, + 0xEA0, 0x00000029, + 0xEA4, 0x08040201, + 0xEA8, 0x80402010, + 0xEB0, 0x77547777, + 0xEB4, 0x00000077, + 0xEB8, 0x00508242, + +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8812A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_PHY_REG(void) +{ + return 57; +} + +/****************************************************************************** +* PHY_REG_MP.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_MP[] = { + 0x800, 0x8020D410, + 0x830, 0x2EAA8EB8, + +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_MP( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_MP)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_MP; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_MP\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8812A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_PHY_REG_MP(void) +{ + return 57; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_PG[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_ASUS.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_PG_ASUS[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303232, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303232, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x32323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303232, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303232, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x32323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322222, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303232, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322222, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303232, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22222426 +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_ASUS)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_PG_ASUS; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_DNI.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_PG_DNI[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x33333333, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x28282828, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x28282828, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x28282828, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x33333333, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28282828, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x28282828, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28282828, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x28282828, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x28282828, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x28282828, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24242424, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x24242424, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24242424, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x24242424, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x24242424, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24242424, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x24242424, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24242424, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x24242424, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x24242424, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x24242424 +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_DNI)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_PG_DNI; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_NEC.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_PG_NEC[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x32343434, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x32343434, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x34342022, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x32343434, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32343434, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x32343434, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x34342022, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x28282828, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262828, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x28282022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28282828, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32343434, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343434, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x28282828, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262828, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343434, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x28282022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28282828, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_NEC)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_PG_NEC; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_TPLINK.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_PHY_REG_PG_TPLINK[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x36363840, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x38404040, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x36383840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363638, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x36363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x36382426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323434, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x36363840, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x38404040, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x36383840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363638, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x36363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x36382426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323434, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x38404040, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x36383840, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x34363638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363840, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323434, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x38404040, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323638, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x36383840, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x34363638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x36363840, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323434, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 +}; + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_PHY_REG_PG_TPLINK)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_PHY_REG_PG_TPLINK; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8812A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.h index 0e5b31aa45d..8a7d68ed59c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_bb.h @@ -1,123 +1,123 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8812A_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8812A_H -#define __INC_MP_BB_HW_IMG_8812A_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_AGC_TAB(void); - -/****************************************************************************** -* AGC_TAB_DIFF.TXT -******************************************************************************/ - -extern u4Byte Array_MP_8812A_AGC_TAB_DIFF_LB[60]; -extern u4Byte Array_MP_8812A_AGC_TAB_DIFF_HB[60]; -void -ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Array[], - IN u4Byte ArrayLen -); -u4Byte ODM_GetVersion_MP_8812A_AGC_TAB_DIFF(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_MP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_MP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_MP(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG(void); - -/****************************************************************************** -* PHY_REG_PG_ASUS.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_ASUS(void); - -/****************************************************************************** -* PHY_REG_PG_DNI.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_DNI(void); - -/****************************************************************************** -* PHY_REG_PG_NEC.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_NEC(void); - -/****************************************************************************** -* PHY_REG_PG_TPLINK.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_TPLINK(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8812A_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8812A_H +#define __INC_MP_BB_HW_IMG_8812A_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_AGC_TAB(void); + +/****************************************************************************** +* AGC_TAB_DIFF.TXT +******************************************************************************/ + +extern u4Byte Array_MP_8812A_AGC_TAB_DIFF_LB[60]; +extern u4Byte Array_MP_8812A_AGC_TAB_DIFF_HB[60]; +void +ODM_ReadAndConfig_MP_8812A_AGC_TAB_DIFF( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Array[], + IN u4Byte ArrayLen +); +u4Byte ODM_GetVersion_MP_8812A_AGC_TAB_DIFF(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_MP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_MP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_MP(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG(void); + +/****************************************************************************** +* PHY_REG_PG_ASUS.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_ASUS(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_ASUS(void); + +/****************************************************************************** +* PHY_REG_PG_DNI.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_DNI(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_DNI(void); + +/****************************************************************************** +* PHY_REG_PG_NEC.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_NEC(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_NEC(void); + +/****************************************************************************** +* PHY_REG_PG_TPLINK.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_PHY_REG_PG_TPLINK(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_PHY_REG_PG_TPLINK(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.c index 4a4f48026d0..8f3808d6f63 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.c @@ -1,7369 +1,7369 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8812a/hal8812a_fw.h" -#endif - - -#if (RTL8812A_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8812A_FW_AP[] = { -0x01, 0x95, 0x20, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0x84, 0x5C, 0x00, 0x00, -0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x4A, 0xB8, 0x02, 0x8F, 0x5F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x2F, 0x22, 0xB4, 0xA4, -}; -u4Byte ArrayLength_MP_8812A_FW_NIC = 32654; - - -#endif - -void -ODM_ReadFirmware_MP_8812A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8812A_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_NIC, ArrayLength_MP_8812A_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8812A_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8812A_FW_NIC_BT[] = { -0x01, 0x95, 0x13, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0xB6, 0x72, 0x00, 0x00, -0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x4A, 0x9A, 0x02, 0x88, 0x5D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x89, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x97, 0xE8, 0x00, 0x00, 0x00, 0x00, 0x00, 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(SIZE_PTR)Array_MP_8812A_FW_NIC_BT; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_NIC_BT, ArrayLength_MP_8812A_FW_NIC_BT); -#endif - *pFirmwareSize = ArrayLength_MP_8812A_FW_NIC_BT; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8812A_FW_WoWLAN[] = { -0x01, 0x95, 0x30, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0xE4, 0x74, 0x00, 0x00, -0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x4D, 0x2A, 0x02, 0x80, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x81, 0x3A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x8F, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x80, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x87, 0xEC, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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*pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8812A_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_WoWLAN, ArrayLength_MP_8812A_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8812A_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8812a/hal8812a_fw.h" +#endif + + +#if (RTL8812A_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8812A_FW_AP[] = { +0x01, 0x95, 0x20, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0x84, 0x5C, 0x00, 0x00, +0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x4A, 0xB8, 0x02, 0x8F, 0x5F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x01, 0x7F, 0x02, 0x02, 0x6F, +0x01, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, 0x22, 0x90, 0x89, 0x07, 0x12, 0x4A, 0x48, 0xE0, +0x22, 0x90, 0xA7, 0x99, 0xE0, 0xD3, 0x94, 0x80, 0x22, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x6E, 0x08, +0x22, 0xFE, 0x33, 0x33, 0x33, 0x54, 0xF8, 0x4F, 0x22, 0x54, 0x03, 0x4F, 0xFF, 0x75, 0xF0, 0x10, +0x22, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x22, 0x08, 0x22, 0x90, 0x05, 0x21, 0xE0, 0x54, 0x7F, 0xF0, +0x22, 0x00, 0xB3, 0xD2, +}; +u4Byte ArrayLength_MP_8812A_FW_AP = 23716; + +#endif + +void +ODM_ReadFirmware_MP_8812A_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8812A_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_AP, ArrayLength_MP_8812A_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8812A_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8812A_FW_NIC[] = { +0x01, 0x95, 0x10, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0x6E, 0x7F, 0x00, 0x00, +0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x4B, 0xBE, 0x02, 0x8F, 0xCB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x90, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xA7, 0xD2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x90, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x9F, 0xB5, 0x00, 0x00, +0x0A, 0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03, 0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, +0x00, 0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D, 0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, +0x07, 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0x2F, 0x22, 0xB4, 0xA4, +}; +u4Byte ArrayLength_MP_8812A_FW_NIC = 32654; + + +#endif + +void +ODM_ReadFirmware_MP_8812A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8812A_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_NIC, ArrayLength_MP_8812A_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8812A_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8812A_FW_NIC_BT[] = { +0x01, 0x95, 0x13, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0xB6, 0x72, 0x00, 0x00, +0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x4A, 0x9A, 0x02, 0x88, 0x5D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x89, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x97, 0xE8, 0x00, 0x00, 0x00, 0x00, 0x00, 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(SIZE_PTR)Array_MP_8812A_FW_NIC_BT; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_NIC_BT, ArrayLength_MP_8812A_FW_NIC_BT); +#endif + *pFirmwareSize = ArrayLength_MP_8812A_FW_NIC_BT; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8812A_FW_WoWLAN[] = { +0x01, 0x95, 0x30, 0x00, 0x31, 0x00, 0x00, 0x00, 0x03, 0x09, 0x21, 0x01, 0xE4, 0x74, 0x00, 0x00, +0xC9, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x4D, 0x2A, 0x02, 0x80, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x81, 0x3A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x8F, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x80, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x87, 0xEC, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x93, 0xC8, 0xE0, 0xFF, 0x24, 0x9B, 0xF5, 0x82, 0xE4, 0x34, +0x8F, 0xF5, 0x83, 0xE0, 0x22, 0x75, 0xF0, 0x20, 0xA4, 0x24, 0x5C, 0xF9, 0x74, 0x91, 0x35, 0xF0, +0xFA, 0x7B, 0x01, 0x22, 0xE4, 0x90, 0x95, 0x8E, 0xF0, 0xA3, 0x74, 0x0A, 0xF0, 0xE4, 0xFB, 0xFD, +0x7F, 0x60, 0x22, 0x90, 0x8E, 0x7F, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22, 0x7F, 0x00, 0x7E, +0x0C, 0x12, 0x37, 0x5D, 0x7F, 0x00, 0x7E, 0x0E, 0x22, 0x90, 0x93, 0xA4, 0xE0, 0xFD, 0x90, 0x93, +0xA3, 0xE0, 0x2D, 0x22, 0x90, 0x93, 0xCB, 0xE4, 0x75, 0xF0, 0x02, 0x02, 0x46, 0xD6, 0x7F, 0xB0, +0x7E, 0x0C, 0x12, 0x36, 0xCE, 0x90, 0x8E, 0x25, 0x22, 0x90, 0x94, 0xA4, 0xEE, 0xF0, 0xA3, 0xEF, +0xF0, 0x22, 0x90, 0x8E, 0x7D, 0xE0, 0x90, 0x05, 0x73, 0xF0, 0x22, 0x90, 0x8E, 0x15, 0xE0, 0xFF, +0xC4, 0x54, 0x0F, 0x22, 0x7E, 0x00, 0x7F, 0x08, 0x7D, 0x00, 0x7B, 0x01, 0x22, 0xF0, 0xEE, 0x54, +0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x22, 0x90, 0x93, 0x8D, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x90, +0x93, 0x8D, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x22, 0x90, 0x93, 0x8F, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, +0x22, 0x7E, 0x0E, 0x12, 0x37, 0x5D, 0x90, 0x00, 0xFF, 0x22, 0x7F, 0xB4, 0x7E, 0x08, 0x12, 0x36, +0xCE, 0xEF, 0x22, 0xE4, 0x75, 0xF0, 0x04, 0x02, 0x46, 0xD6, 0x90, 0x8D, 0xFA, 0xF0, 0xA3, 0xEF, +0xF0, 0x22, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0x22, 0xE4, 0x75, 0xF0, 0x20, 0x02, 0x46, +0xD6, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22, 0xF0, 0x90, 0x93, 0xC8, 0xE0, 0x04, 0xF0, +0x22, 0x90, 0x8E, 0x7D, 0xE0, 0x90, 0x01, 0x3F, 0x22, 0x90, 0x8E, 0x13, 0xE0, 0x44, 0x04, 0xF0, +0x22, 0x90, 0x8E, 0x1D, 0xE0, 0xFF, 0xA3, 0xE0, 0x22, 0x90, 0x8E, 0x15, 0xE0, 0xC4, 0x54, 0x0F, +0x22, 0x90, 0x8D, 0xFD, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0x90, 0x00, 0x01, 0x12, 0x26, 0x37, 0xFD, +0x22, 0x12, 0x37, 0x5D, 0x90, 0x00, 0x02, 0xE0, 0x22, 0x90, 0x01, 0xC2, 0xE0, 0x44, 0x01, 0xF0, +0x22, 0x00, 0x59, 0xEF, +}; +u4Byte ArrayLength_MP_8812A_FW_WoWLAN = 29956; + +#endif + +void +ODM_ReadFirmware_MP_8812A_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8812A_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8812A_FW_WoWLAN, ArrayLength_MP_8812A_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8812A_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.h index 6bab5a8054d..9eb383004fb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_fw.h @@ -1,73 +1,73 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8812A_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8812A_H -#define __INC_MP_FW_HW_IMG_8812A_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8812A_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8812A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC_BT.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8812A_FW_NIC_BT( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8812A_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8812A_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8812A_H +#define __INC_MP_FW_HW_IMG_8812A_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8812A_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8812A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC_BT.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8812A_FW_NIC_BT( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8812A_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.c index d71ca549b6a..278189e0bf2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.c @@ -1,294 +1,294 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8812A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_MAC_REG[] = { - 0x010, 0x0000000C, - 0x80000200, 0x00000000, 0x40000000, 0x00000000, - 0x011, 0x00000066, - 0xA0000000, 0x00000000, - 0x011, 0x0000005A, - 0xB0000000, 0x00000000, - 0x025, 0x0000000F, - 0x072, 0x00000000, - 0x420, 0x00000080, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x45B, 0x00000080, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x604, 0x00000009, - 0x605, 0x00000030, - 0x607, 0x00000003, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000080, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x718, 0x00000040, - -}; - -void -ODM_ReadAndConfig_MP_8812A_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8812A(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_MAC_REG(void) -{ - return 57; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8812A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_MAC_REG[] = { + 0x010, 0x0000000C, + 0x80000200, 0x00000000, 0x40000000, 0x00000000, + 0x011, 0x00000066, + 0xA0000000, 0x00000000, + 0x011, 0x0000005A, + 0xB0000000, 0x00000000, + 0x025, 0x0000000F, + 0x072, 0x00000000, + 0x420, 0x00000080, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x45B, 0x00000080, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x604, 0x00000009, + 0x605, 0x00000030, + 0x607, 0x00000003, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000080, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + +}; + +void +ODM_ReadAndConfig_MP_8812A_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8812A(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_MAC_REG(void) +{ + return 57; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.h index 0b0101dfa3b..32ee35c7d44 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8812A_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8812A_H -#define __INC_MP_MAC_HW_IMG_8812A_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8812A_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8812A_H +#define __INC_MP_MAC_HW_IMG_8812A_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.c index a2c01861097..80aa914fa50 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.c @@ -1,3809 +1,3809 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8812A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_RadioA[] = { - 0x000, 0x00010000, - 0x018, 0x0001712A, - 0x056, 0x00051CF2, - 0x066, 0x00040000, - 0x01E, 0x00080000, - 0x089, 0x00000080, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x00014B3A, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x00014B3A, - 0xA0000000, 0x00000000, - 0x086, 0x00014B38, - 0xB0000000, 0x00000000, - 0x80000004, 0x00000000, 0x40000000, 0x00000000, - 0x08B, 0x00080180, - 0xA0000000, 0x00000000, - 0x08B, 0x00087180, - 0xB0000000, 0x00000000, - 0x0B1, 0x0001FC1A, - 0x0B3, 0x000F0810, - 0x0B4, 0x0001A78D, - 0x0BA, 0x00086180, - 0x018, 0x00000006, - 0x0EF, 0x00002000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F218, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x0003F218, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xA0000000, 0x00000000, - 0x03B, 0x00038A58, - 0x03B, 0x00037A58, - 0x03B, 0x0002A590, - 0x03B, 0x00027A50, - 0x03B, 0x00018248, - 0x03B, 0x00010240, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A4EE, - 0x034, 0x00009076, - 0x034, 0x00008073, - 0x034, 0x00007070, - 0x034, 0x0000606D, - 0x034, 0x0000506A, - 0x034, 0x00004049, - 0x034, 0x00003046, - 0x034, 0x00002028, - 0x034, 0x00001025, - 0x034, 0x00000022, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF4, - 0x034, 0x00009DF1, - 0x034, 0x00008DEE, - 0x034, 0x00007DEB, - 0x034, 0x00006DE8, - 0x034, 0x00005DE5, - 0x034, 0x00004DE2, - 0x034, 0x00003CE6, - 0x034, 0x000024E7, - 0x034, 0x000014E4, - 0x034, 0x000004E1, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x0EF, 0x00000002, - 0x008, 0x00008400, - 0x018, 0x0001712A, - 0x0EF, 0x00001000, - 0x03A, 0x00000080, - 0x03B, 0x0003A02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x0003202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x0002B064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x00023070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0001B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00012085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0000A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00002080, - 0x03C, 0x00010000, - 0x03A, 0x00000080, - 0x03B, 0x0007A02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x0007202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x0006B064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x00063070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0005B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00052085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0004A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00042080, - 0x03C, 0x00010000, - 0x03A, 0x00000080, - 0x03B, 0x000BA02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x000B202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x000AB064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x000A3070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0009B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00092085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0008A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00082080, - 0x03C, 0x00010000, - 0x0EF, 0x00001100, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0B2, - 0x034, 0x000490AF, - 0x034, 0x00048070, - 0x034, 0x0004706D, - 0x034, 0x00046050, - 0x034, 0x0004504D, - 0x034, 0x0004404A, - 0x034, 0x00043047, - 0x034, 0x0004200A, - 0x034, 0x00041007, - 0x034, 0x00040004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0B2, - 0x034, 0x000490AF, - 0x034, 0x00048070, - 0x034, 0x0004706D, - 0x034, 0x0004604D, - 0x034, 0x0004504A, - 0x034, 0x00044047, - 0x034, 0x00043044, - 0x034, 0x00042007, - 0x034, 0x00041004, - 0x034, 0x00040001, - 0xA0000000, 0x00000000, - 0x034, 0x0004ADF5, - 0x034, 0x00049DF2, - 0x034, 0x00048DEF, - 0x034, 0x00047DEC, - 0x034, 0x00046DE9, - 0x034, 0x00045DE6, - 0x034, 0x00044DE3, - 0x034, 0x000438C8, - 0x034, 0x000428C5, - 0x034, 0x000418C2, - 0x034, 0x000408C0, - 0xB0000000, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0B2, - 0x034, 0x000290AF, - 0x034, 0x00028070, - 0x034, 0x0002706D, - 0x034, 0x00026050, - 0x034, 0x0002504D, - 0x034, 0x0002404A, - 0x034, 0x00023047, - 0x034, 0x0002200A, - 0x034, 0x00021007, - 0x034, 0x00020004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0B4, - 0x034, 0x000290B1, - 0x034, 0x00028072, - 0x034, 0x0002706F, - 0x034, 0x0002604F, - 0x034, 0x0002504C, - 0x034, 0x00024049, - 0x034, 0x00023046, - 0x034, 0x00022009, - 0x034, 0x00021006, - 0x034, 0x00020003, - 0xA0000000, 0x00000000, - 0x034, 0x0002ADF5, - 0x034, 0x00029DF2, - 0x034, 0x00028DEF, - 0x034, 0x00027DEC, - 0x034, 0x00026DE9, - 0x034, 0x00025DE6, - 0x034, 0x00024DE3, - 0x034, 0x000238C8, - 0x034, 0x000228C5, - 0x034, 0x000218C2, - 0x034, 0x000208C0, - 0xB0000000, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0B2, - 0x034, 0x000090AF, - 0x034, 0x00008070, - 0x034, 0x0000706D, - 0x034, 0x00006050, - 0x034, 0x0000504D, - 0x034, 0x0000404A, - 0x034, 0x00003047, - 0x034, 0x0000200A, - 0x034, 0x00001007, - 0x034, 0x00000004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0B2, - 0x034, 0x000090AF, - 0x034, 0x00008070, - 0x034, 0x0000706D, - 0x034, 0x0000604D, - 0x034, 0x0000504A, - 0x034, 0x00004047, - 0x034, 0x00003044, - 0x034, 0x00002007, - 0x034, 0x00001004, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000AFF7, - 0x034, 0x00009DF7, - 0x034, 0x00008DF4, - 0x034, 0x00007DF1, - 0x034, 0x00006DEE, - 0x034, 0x00005DEB, - 0x034, 0x00004DE8, - 0x034, 0x000038CC, - 0x034, 0x000028C9, - 0x034, 0x000018C6, - 0x034, 0x000008C3, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x000001D4, - 0x035, 0x000081D4, - 0x035, 0x000101D4, - 0x035, 0x000201B4, - 0x035, 0x000281B4, - 0x035, 0x000301B4, - 0x035, 0x000401B4, - 0x035, 0x000481B4, - 0x035, 0x000501B4, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x000001D4, - 0x035, 0x000081D4, - 0x035, 0x000101D4, - 0x035, 0x000201B4, - 0x035, 0x000281B4, - 0x035, 0x000301B4, - 0x035, 0x000401B4, - 0x035, 0x000481B4, - 0x035, 0x000501B4, - 0xA0000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x00000188, - 0x035, 0x00008147, - 0x035, 0x00010147, - 0x035, 0x000201D7, - 0x035, 0x000281D7, - 0x035, 0x000301D7, - 0x035, 0x000401D8, - 0x035, 0x000481D8, - 0x035, 0x000501D8, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00004BFB, - 0x036, 0x0000CBFB, - 0x036, 0x00014BFB, - 0x036, 0x0001CBFB, - 0x036, 0x00024F4B, - 0x036, 0x0002CF4B, - 0x036, 0x00034F4B, - 0x036, 0x0003CF4B, - 0x036, 0x00044F4B, - 0x036, 0x0004CF4B, - 0x036, 0x00054F4B, - 0x036, 0x0005CF4B, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00004BFB, - 0x036, 0x0000CBFB, - 0x036, 0x00014BFB, - 0x036, 0x0001CBFB, - 0x036, 0x00024F4B, - 0x036, 0x0002CF4B, - 0x036, 0x00034F4B, - 0x036, 0x0003CF4B, - 0x036, 0x00044F4B, - 0x036, 0x0004CF4B, - 0x036, 0x00054F4B, - 0x036, 0x0005CF4B, - 0xA0000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00084EB4, - 0x036, 0x0008CC35, - 0x036, 0x00094C35, - 0x036, 0x0009CC35, - 0x036, 0x000A4C35, - 0x036, 0x000ACC35, - 0x036, 0x000B4C35, - 0x036, 0x000BCC35, - 0x036, 0x000C4C34, - 0x036, 0x000CCC35, - 0x036, 0x000D4C35, - 0x036, 0x000DCC35, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x00000008, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000002CC, - 0x03C, 0x00000522, - 0x03C, 0x00000902, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x03C, 0x000002CC, - 0x03C, 0x00000522, - 0x03C, 0x00000902, - 0xA0000000, 0x00000000, - 0x03C, 0x000002A8, - 0x03C, 0x000005A2, - 0x03C, 0x00000880, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000002, - 0x0DF, 0x00000080, - 0x01F, 0x00000064, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000FDD43, - 0x062, 0x00038F4B, - 0x063, 0x00032117, - 0x064, 0x000194AC, - 0x065, 0x000931D1, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x061, 0x000FDD43, - 0x062, 0x00038F4B, - 0x063, 0x00032117, - 0x064, 0x000194AC, - 0x065, 0x000931D2, - 0xA0000000, 0x00000000, - 0x061, 0x000E5D53, - 0x062, 0x00038FCD, - 0x063, 0x000114EB, - 0x064, 0x000196AC, - 0x065, 0x000911D7, - 0xB0000000, 0x00000000, - 0x008, 0x00008400, - 0x01C, 0x000739D2, - 0x0B4, 0x0001E78D, - 0x018, 0x0001F12A, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x0B4, 0x0001A78D, - 0x018, 0x0001712A, - -}; - -void -ODM_ReadAndConfig_MP_8812A_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8812A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_RadioA(void) -{ - return 57; -} - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -u4Byte Array_MP_8812A_RadioB[] = { - 0x056, 0x00051CF2, - 0x066, 0x00040000, - 0x089, 0x00000080, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x00014B3A, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x086, 0x00014B3A, - 0xA0000000, 0x00000000, - 0x086, 0x00014B38, - 0xB0000000, 0x00000000, - 0x80000004, 0x00000000, 0x40000000, 0x00000000, - 0x08B, 0x00080180, - 0xA0000000, 0x00000000, - 0x08B, 0x00087180, - 0xB0000000, 0x00000000, - 0x018, 0x00000006, - 0x0EF, 0x00002000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F218, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0x90000001, 0x00000005, 0x40000000, 0x00000000, - 0x03B, 0x0003F218, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xA0000000, 0x00000000, - 0x03B, 0x00038A58, - 0x03B, 0x00037A58, - 0x03B, 0x0002A590, - 0x03B, 0x00027A50, - 0x03B, 0x00018248, - 0x03B, 0x00010240, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A4EE, - 0x034, 0x00009076, - 0x034, 0x00008073, - 0x034, 0x00007070, - 0x034, 0x0000606D, - 0x034, 0x0000506A, - 0x034, 0x00004049, - 0x034, 0x00003046, - 0x034, 0x00002028, - 0x034, 0x00001025, - 0x034, 0x00000022, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF4, - 0x034, 0x00009DF1, - 0x034, 0x00008DEE, - 0x034, 0x00007DEB, - 0x034, 0x00006DE8, - 0x034, 0x00005DE5, - 0x034, 0x00004DE2, - 0x034, 0x00003CE6, - 0x034, 0x000024E7, - 0x034, 0x000014E4, - 0x034, 0x000004E1, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x0EF, 0x00000002, - 0x008, 0x00008400, - 0x018, 0x0001712A, - 0x0EF, 0x00001000, - 0x03A, 0x00000080, - 0x03B, 0x0003A02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x0003202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x0002B064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x00023070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0001B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00012085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0000A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00002080, - 0x03C, 0x00010000, - 0x03A, 0x00000080, - 0x03B, 0x0007A02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x0007202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x0006B064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x00063070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0005B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00052085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0004A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00042080, - 0x03C, 0x00010000, - 0x03A, 0x00000080, - 0x03B, 0x000BA02C, - 0x03C, 0x00004000, - 0x03A, 0x00000400, - 0x03B, 0x000B202C, - 0x03C, 0x00010000, - 0x03A, 0x000000A0, - 0x03B, 0x000AB064, - 0x03C, 0x00004000, - 0x03A, 0x000000D8, - 0x03B, 0x000A3070, - 0x03C, 0x00004000, - 0x03A, 0x00000468, - 0x03B, 0x0009B870, - 0x03C, 0x00010000, - 0x03A, 0x00000098, - 0x03B, 0x00092085, - 0x03C, 0x000E4000, - 0x03A, 0x00000418, - 0x03B, 0x0008A080, - 0x03C, 0x000F0000, - 0x03A, 0x00000418, - 0x03B, 0x00082080, - 0x03C, 0x00010000, - 0x0EF, 0x00001100, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0B2, - 0x034, 0x000490AF, - 0x034, 0x00048070, - 0x034, 0x0004706D, - 0x034, 0x00046050, - 0x034, 0x0004504D, - 0x034, 0x0004404A, - 0x034, 0x00043047, - 0x034, 0x0004200A, - 0x034, 0x00041007, - 0x034, 0x00040004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0B1, - 0x034, 0x000490AE, - 0x034, 0x0004806F, - 0x034, 0x0004706C, - 0x034, 0x0004604C, - 0x034, 0x00045049, - 0x034, 0x00044046, - 0x034, 0x00043043, - 0x034, 0x00042006, - 0x034, 0x00041003, - 0x034, 0x00040000, - 0xA0000000, 0x00000000, - 0x034, 0x0004ADF5, - 0x034, 0x00049DF2, - 0x034, 0x00048DEF, - 0x034, 0x00047DEC, - 0x034, 0x00046DE9, - 0x034, 0x00045DE6, - 0x034, 0x00044DE3, - 0x034, 0x000438C8, - 0x034, 0x000428C5, - 0x034, 0x000418C2, - 0x034, 0x000408C0, - 0xB0000000, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0B2, - 0x034, 0x000290AF, - 0x034, 0x00028070, - 0x034, 0x0002706D, - 0x034, 0x00026050, - 0x034, 0x0002504D, - 0x034, 0x0002404A, - 0x034, 0x00023047, - 0x034, 0x0002200A, - 0x034, 0x00021007, - 0x034, 0x00020004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0B3, - 0x034, 0x000290B0, - 0x034, 0x00028071, - 0x034, 0x0002706E, - 0x034, 0x0002604E, - 0x034, 0x0002504B, - 0x034, 0x00024048, - 0x034, 0x00023045, - 0x034, 0x00022008, - 0x034, 0x00021005, - 0x034, 0x00020002, - 0xA0000000, 0x00000000, - 0x034, 0x0002ADF5, - 0x034, 0x00029DF2, - 0x034, 0x00028DEF, - 0x034, 0x00027DEC, - 0x034, 0x00026DE9, - 0x034, 0x00025DE6, - 0x034, 0x00024DE3, - 0x034, 0x000238C8, - 0x034, 0x000228C5, - 0x034, 0x000218C2, - 0x034, 0x000208C0, - 0xB0000000, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0B2, - 0x034, 0x000090AF, - 0x034, 0x00008070, - 0x034, 0x0000706D, - 0x034, 0x00006050, - 0x034, 0x0000504D, - 0x034, 0x0000404A, - 0x034, 0x00003047, - 0x034, 0x0000200A, - 0x034, 0x00001007, - 0x034, 0x00000004, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0B3, - 0x034, 0x000090B0, - 0x034, 0x00008070, - 0x034, 0x0000706D, - 0x034, 0x0000604D, - 0x034, 0x0000504A, - 0x034, 0x00004047, - 0x034, 0x00003044, - 0x034, 0x00002007, - 0x034, 0x00001004, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000AFF7, - 0x034, 0x00009DF7, - 0x034, 0x00008DF4, - 0x034, 0x00007DF1, - 0x034, 0x00006DEE, - 0x034, 0x00005DEB, - 0x034, 0x00004DE8, - 0x034, 0x000038CC, - 0x034, 0x000028C9, - 0x034, 0x000018C6, - 0x034, 0x000008C3, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x000001C5, - 0x035, 0x000081C5, - 0x035, 0x000101C5, - 0x035, 0x00020174, - 0x035, 0x00028174, - 0x035, 0x00030174, - 0x035, 0x00040185, - 0x035, 0x00048185, - 0x035, 0x00050185, - 0x0EF, 0x00000000, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x000001C5, - 0x035, 0x000081C5, - 0x035, 0x000101C5, - 0x035, 0x00020174, - 0x035, 0x00028174, - 0x035, 0x00030174, - 0x035, 0x00040185, - 0x035, 0x00048185, - 0x035, 0x00050185, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x035, 0x00000188, - 0x035, 0x00008147, - 0x035, 0x00010147, - 0x035, 0x000201D7, - 0x035, 0x000281D7, - 0x035, 0x000301D7, - 0x035, 0x000401D8, - 0x035, 0x000481D8, - 0x035, 0x000501D8, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00005B8B, - 0x036, 0x0000DB8B, - 0x036, 0x00015B8B, - 0x036, 0x0001DB8B, - 0x036, 0x000262DB, - 0x036, 0x0002E2DB, - 0x036, 0x000362DB, - 0x036, 0x0003E2DB, - 0x036, 0x0004553B, - 0x036, 0x0004D53B, - 0x036, 0x0005553B, - 0x036, 0x0005D53B, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00005B8B, - 0x036, 0x0000DB8B, - 0x036, 0x00015B8B, - 0x036, 0x0001DB8B, - 0x036, 0x000262DB, - 0x036, 0x0002E2DB, - 0x036, 0x000362DB, - 0x036, 0x0003E2DB, - 0x036, 0x0004553B, - 0x036, 0x0004D53B, - 0x036, 0x0005553B, - 0x036, 0x0005D53B, - 0xA0000000, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x036, 0x00084EB4, - 0x036, 0x0008CC35, - 0x036, 0x00094C35, - 0x036, 0x0009CC35, - 0x036, 0x000A4C35, - 0x036, 0x000ACC35, - 0x036, 0x000B4C35, - 0x036, 0x000BCC35, - 0x036, 0x000C4C34, - 0x036, 0x000CCC35, - 0x036, 0x000D4C35, - 0x036, 0x000DCC35, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x00000008, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000002DC, - 0x03C, 0x00000524, - 0x03C, 0x00000902, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x03C, 0x000002DC, - 0x03C, 0x00000524, - 0x03C, 0x00000902, - 0xA0000000, 0x00000000, - 0x03C, 0x000002A8, - 0x03C, 0x000005A2, - 0x03C, 0x00000880, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000002, - 0x0DF, 0x00000080, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000EAC43, - 0x062, 0x00038F47, - 0x063, 0x00031157, - 0x064, 0x0001C4AC, - 0x065, 0x000931D1, - 0x90000008, 0x05000000, 0x40000000, 0x00000000, - 0x061, 0x000EAC43, - 0x062, 0x00038F47, - 0x063, 0x00031157, - 0x064, 0x0001C4AC, - 0x065, 0x000931D2, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000EAC43, - 0x062, 0x00038F47, - 0x063, 0x00031157, - 0x064, 0x0001C4AC, - 0x065, 0x000931D1, - 0xA0000000, 0x00000000, - 0x061, 0x000E5D53, - 0x062, 0x00038FCD, - 0x063, 0x000114EB, - 0x064, 0x000196AC, - 0x065, 0x000911D7, - 0xB0000000, 0x00000000, - 0x008, 0x00008400, - -}; - -void -ODM_ReadAndConfig_MP_8812A_RadioB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8812A_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8812A_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioB_8812A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8812A_RadioB(void) -{ - return 57; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 18, 19, 19, 19}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -#endif - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13}, - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13}, - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -#endif - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_RFE3.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 18, 18}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 14, 13, 13, 14, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 16, 16, 17, 17}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE3_8812A[] = {0, 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE3_8812A[] = {0, 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE3( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_RFE4.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13}, - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13}, - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE4( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 4, 4, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; -#endif - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8812A_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "30", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "36", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "36", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "36", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "36", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "36", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "36", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_HM812A03.TXT -******************************************************************************/ - -const char *Array_MP_8812A_TXPWR_LMT_HM812A03[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "36", - "FCC", "2.4G", "20M", "HT", "1T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "36", - "FCC", "2.4G", "20M", "HT", "1T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "36", - "FCC", "2.4G", "20M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "36", - "FCC", "2.4G", "20M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "36", - "FCC", "2.4G", "20M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "36", - "FCC", "2.4G", "20M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "36", - "FCC", "2.4G", "20M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "36", - "FCC", "2.4G", "20M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "36", - "FCC", "2.4G", "20M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "36", - "FCC", "2.4G", "20M", "HT", "1T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "36", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "36", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "36", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "24", - "MKK", "2.4G", "20M", "HT", "2T", "01", "34", - "FCC", "2.4G", "20M", "HT", "2T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "24", - "MKK", "2.4G", "20M", "HT", "2T", "02", "34", - "FCC", "2.4G", "20M", "HT", "2T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "24", - "MKK", "2.4G", "20M", "HT", "2T", "03", "34", - "FCC", "2.4G", "20M", "HT", "2T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "24", - "MKK", "2.4G", "20M", "HT", "2T", "04", "34", - "FCC", "2.4G", "20M", "HT", "2T", "05", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "24", - "MKK", "2.4G", "20M", "HT", "2T", "05", "34", - "FCC", "2.4G", "20M", "HT", "2T", "06", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "24", - "MKK", "2.4G", "20M", "HT", "2T", "06", "34", - "FCC", "2.4G", "20M", "HT", "2T", "07", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "24", - "MKK", "2.4G", "20M", "HT", "2T", "07", "34", - "FCC", "2.4G", "20M", "HT", "2T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "24", - "MKK", "2.4G", "20M", "HT", "2T", "08", "34", - "FCC", "2.4G", "20M", "HT", "2T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "24", - "MKK", "2.4G", "20M", "HT", "2T", "09", "34", - "FCC", "2.4G", "20M", "HT", "2T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "24", - "MKK", "2.4G", "20M", "HT", "2T", "10", "34", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "24", - "MKK", "2.4G", "20M", "HT", "2T", "11", "34", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "24", - "MKK", "2.4G", "20M", "HT", "2T", "12", "34", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "24", - "MKK", "2.4G", "20M", "HT", "2T", "13", "34", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "24", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "24", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "24", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "24", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "24", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "24", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "24", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "24", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "24", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "36", - "FCC", "5G", "20M", "OFDM", "1T", "104", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "36", - "FCC", "5G", "20M", "OFDM", "1T", "108", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "36", - "FCC", "5G", "20M", "OFDM", "1T", "112", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "36", - "FCC", "5G", "20M", "OFDM", "1T", "116", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "36", - "FCC", "5G", "20M", "OFDM", "1T", "120", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "36", - "FCC", "5G", "20M", "OFDM", "1T", "124", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "36", - "FCC", "5G", "20M", "OFDM", "1T", "128", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "36", - "FCC", "5G", "20M", "OFDM", "1T", "132", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "36", - "FCC", "5G", "20M", "OFDM", "1T", "136", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "36", - "FCC", "5G", "20M", "OFDM", "1T", "140", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "36", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "36", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "30", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "36", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "36", - "FCC", "5G", "20M", "HT", "1T", "104", "36", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "36", - "FCC", "5G", "20M", "HT", "1T", "108", "36", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "36", - "FCC", "5G", "20M", "HT", "1T", "112", "36", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "36", - "FCC", "5G", "20M", "HT", "1T", "116", "36", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "36", - "FCC", "5G", "20M", "HT", "1T", "120", "63", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "36", - "FCC", "5G", "20M", "HT", "1T", "124", "63", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "36", - "FCC", "5G", "20M", "HT", "1T", "128", "63", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "36", - "FCC", "5G", "20M", "HT", "1T", "132", "36", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "36", - "FCC", "5G", "20M", "HT", "1T", "136", "36", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "36", - "FCC", "5G", "20M", "HT", "1T", "140", "30", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "36", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "36", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "36", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "36", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "36", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "22", - "ETSI", "5G", "20M", "HT", "2T", "36", "26", - "MKK", "5G", "20M", "HT", "2T", "36", "26", - "FCC", "5G", "20M", "HT", "2T", "40", "22", - "ETSI", "5G", "20M", "HT", "2T", "40", "26", - "MKK", "5G", "20M", "HT", "2T", "40", "26", - "FCC", "5G", "20M", "HT", "2T", "44", "22", - "ETSI", "5G", "20M", "HT", "2T", "44", "26", - "MKK", "5G", "20M", "HT", "2T", "44", "26", - "FCC", "5G", "20M", "HT", "2T", "48", "22", - "ETSI", "5G", "20M", "HT", "2T", "48", "26", - "MKK", "5G", "20M", "HT", "2T", "48", "26", - "FCC", "5G", "20M", "HT", "2T", "52", "36", - "ETSI", "5G", "20M", "HT", "2T", "52", "26", - "MKK", "5G", "20M", "HT", "2T", "52", "26", - "FCC", "5G", "20M", "HT", "2T", "56", "36", - "ETSI", "5G", "20M", "HT", "2T", "56", "26", - "MKK", "5G", "20M", "HT", "2T", "56", "26", - "FCC", "5G", "20M", "HT", "2T", "60", "36", - "ETSI", "5G", "20M", "HT", "2T", "60", "26", - "MKK", "5G", "20M", "HT", "2T", "60", "26", - "FCC", "5G", "20M", "HT", "2T", "64", "30", - "ETSI", "5G", "20M", "HT", "2T", "64", "26", - "MKK", "5G", "20M", "HT", "2T", "64", "26", - "FCC", "5G", "20M", "HT", "2T", "100", "32", - "ETSI", "5G", "20M", "HT", "2T", "100", "26", - "MKK", "5G", "20M", "HT", "2T", "100", "34", - "FCC", "5G", "20M", "HT", "2T", "104", "36", - "ETSI", "5G", "20M", "HT", "2T", "104", "26", - "MKK", "5G", "20M", "HT", "2T", "104", "34", - "FCC", "5G", "20M", "HT", "2T", "108", "36", - "ETSI", "5G", "20M", "HT", "2T", "108", "26", - "MKK", "5G", "20M", "HT", "2T", "108", "34", - "FCC", "5G", "20M", "HT", "2T", "112", "36", - "ETSI", "5G", "20M", "HT", "2T", "112", "26", - "MKK", "5G", "20M", "HT", "2T", "112", "34", - "FCC", "5G", "20M", "HT", "2T", "116", "36", - "ETSI", "5G", "20M", "HT", "2T", "116", "26", - "MKK", "5G", "20M", "HT", "2T", "116", "34", - "FCC", "5G", "20M", "HT", "2T", "120", "63", - "ETSI", "5G", "20M", "HT", "2T", "120", "26", - "MKK", "5G", "20M", "HT", "2T", "120", "34", - "FCC", "5G", "20M", "HT", "2T", "124", "63", - "ETSI", "5G", "20M", "HT", "2T", "124", "26", - "MKK", "5G", "20M", "HT", "2T", "124", "34", - "FCC", "5G", "20M", "HT", "2T", "128", "63", - "ETSI", "5G", "20M", "HT", "2T", "128", "26", - "MKK", "5G", "20M", "HT", "2T", "128", "34", - "FCC", "5G", "20M", "HT", "2T", "132", "36", - "ETSI", "5G", "20M", "HT", "2T", "132", "26", - "MKK", "5G", "20M", "HT", "2T", "132", "34", - "FCC", "5G", "20M", "HT", "2T", "136", "36", - "ETSI", "5G", "20M", "HT", "2T", "136", "26", - "MKK", "5G", "20M", "HT", "2T", "136", "34", - "FCC", "5G", "20M", "HT", "2T", "140", "30", - "ETSI", "5G", "20M", "HT", "2T", "140", "26", - "MKK", "5G", "20M", "HT", "2T", "140", "34", - "FCC", "5G", "20M", "HT", "2T", "149", "36", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "36", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "36", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "36", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "36", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "20", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "34", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "34", - "FCC", "5G", "40M", "HT", "1T", "54", "34", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "34", - "FCC", "5G", "40M", "HT", "1T", "62", "20", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "34", - "FCC", "5G", "40M", "HT", "1T", "102", "22", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "36", - "FCC", "5G", "40M", "HT", "1T", "110", "36", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "34", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "34", - "FCC", "5G", "40M", "HT", "1T", "126", "63", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "34", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "34", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "26", - "MKK", "5G", "40M", "HT", "2T", "38", "26", - "FCC", "5G", "40M", "HT", "2T", "46", "22", - "ETSI", "5G", "40M", "HT", "2T", "46", "26", - "MKK", "5G", "40M", "HT", "2T", "46", "26", - "FCC", "5G", "40M", "HT", "2T", "54", "34", - "ETSI", "5G", "40M", "HT", "2T", "54", "26", - "MKK", "5G", "40M", "HT", "2T", "54", "26", - "FCC", "5G", "40M", "HT", "2T", "62", "20", - "ETSI", "5G", "40M", "HT", "2T", "62", "26", - "MKK", "5G", "40M", "HT", "2T", "62", "26", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "26", - "MKK", "5G", "40M", "HT", "2T", "102", "36", - "FCC", "5G", "40M", "HT", "2T", "110", "36", - "ETSI", "5G", "40M", "HT", "2T", "110", "26", - "MKK", "5G", "40M", "HT", "2T", "110", "34", - "FCC", "5G", "40M", "HT", "2T", "118", "36", - "ETSI", "5G", "40M", "HT", "2T", "118", "26", - "MKK", "5G", "40M", "HT", "2T", "118", "34", - "FCC", "5G", "40M", "HT", "2T", "126", "63", - "ETSI", "5G", "40M", "HT", "2T", "126", "26", - "MKK", "5G", "40M", "HT", "2T", "126", "34", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "26", - "MKK", "5G", "40M", "HT", "2T", "134", "34", - "FCC", "5G", "40M", "HT", "2T", "151", "36", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "36", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "16", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "22", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "63", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "26", - "MKK", "5G", "80M", "VHT", "2T", "42", "28", - "FCC", "5G", "80M", "VHT", "2T", "58", "16", - "ETSI", "5G", "80M", "VHT", "2T", "58", "26", - "MKK", "5G", "80M", "VHT", "2T", "58", "28", - "FCC", "5G", "80M", "VHT", "2T", "106", "22", - "ETSI", "5G", "80M", "VHT", "2T", "106", "26", - "MKK", "5G", "80M", "VHT", "2T", "106", "32", - "FCC", "5G", "80M", "VHT", "2T", "122", "63", - "ETSI", "5G", "80M", "VHT", "2T", "122", "26", - "MKK", "5G", "80M", "VHT", "2T", "122", "32", - "FCC", "5G", "80M", "VHT", "2T", "155", "36", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_HM812A03)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_HM812A03; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_NFA812A00.TXT -******************************************************************************/ - -const char *Array_MP_8812A_TXPWR_LMT_NFA812A00[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "36", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "36", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "24", - "MKK", "2.4G", "20M", "HT", "2T", "01", "34", - "FCC", "2.4G", "20M", "HT", "2T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "24", - "MKK", "2.4G", "20M", "HT", "2T", "02", "34", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "24", - "MKK", "2.4G", "20M", "HT", "2T", "03", "34", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "24", - "MKK", "2.4G", "20M", "HT", "2T", "04", "34", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "24", - "MKK", "2.4G", "20M", "HT", "2T", "05", "34", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "24", - "MKK", "2.4G", "20M", "HT", "2T", "06", "34", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "24", - "MKK", "2.4G", "20M", "HT", "2T", "07", "34", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "24", - "MKK", "2.4G", "20M", "HT", "2T", "08", "34", - "FCC", "2.4G", "20M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "24", - "MKK", "2.4G", "20M", "HT", "2T", "09", "34", - "FCC", "2.4G", "20M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "24", - "MKK", "2.4G", "20M", "HT", "2T", "10", "34", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "24", - "MKK", "2.4G", "20M", "HT", "2T", "11", "34", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "24", - "MKK", "2.4G", "20M", "HT", "2T", "12", "34", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "24", - "MKK", "2.4G", "20M", "HT", "2T", "13", "34", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "24", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "24", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "24", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "24", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "24", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "24", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "24", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "24", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "24", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "34", - "FCC", "5G", "20M", "OFDM", "1T", "40", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "34", - "FCC", "5G", "20M", "OFDM", "1T", "44", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "34", - "FCC", "5G", "20M", "OFDM", "1T", "114", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", - "MKK", "5G", "20M", "OFDM", "1T", "114", "34", - "FCC", "5G", "20M", "OFDM", "1T", "108", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "34", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "34", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "34", - "FCC", "5G", "20M", "OFDM", "1T", "120", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "34", - "FCC", "5G", "20M", "OFDM", "1T", "124", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "34", - "FCC", "5G", "20M", "OFDM", "1T", "128", "63", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "34", - "FCC", "5G", "20M", "OFDM", "1T", "132", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "34", - "FCC", "5G", "20M", "OFDM", "1T", "136", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "34", - "FCC", "5G", "20M", "OFDM", "1T", "140", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "34", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "34", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "34", - "FCC", "5G", "20M", "HT", "1T", "40", "34", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "34", - "FCC", "5G", "20M", "HT", "1T", "44", "34", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "34", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "34", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "34", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "34", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "34", - "FCC", "5G", "20M", "HT", "1T", "114", "34", - "ETSI", "5G", "20M", "HT", "1T", "114", "32", - "MKK", "5G", "20M", "HT", "1T", "114", "34", - "FCC", "5G", "20M", "HT", "1T", "108", "34", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "34", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "34", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "34", - "FCC", "5G", "20M", "HT", "1T", "120", "63", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "34", - "FCC", "5G", "20M", "HT", "1T", "124", "63", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "34", - "FCC", "5G", "20M", "HT", "1T", "128", "63", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "34", - "FCC", "5G", "20M", "HT", "1T", "132", "34", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "34", - "FCC", "5G", "20M", "HT", "1T", "136", "34", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "34", - "FCC", "5G", "20M", "HT", "1T", "140", "34", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "34", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "34", - "ETSI", "5G", "20M", "HT", "2T", "36", "26", - "MKK", "5G", "20M", "HT", "2T", "36", "28", - "FCC", "5G", "20M", "HT", "2T", "40", "34", - "ETSI", "5G", "20M", "HT", "2T", "40", "26", - "MKK", "5G", "20M", "HT", "2T", "40", "28", - "FCC", "5G", "20M", "HT", "2T", "44", "34", - "ETSI", "5G", "20M", "HT", "2T", "44", "26", - "MKK", "5G", "20M", "HT", "2T", "44", "28", - "FCC", "5G", "20M", "HT", "2T", "48", "34", - "ETSI", "5G", "20M", "HT", "2T", "48", "26", - "MKK", "5G", "20M", "HT", "2T", "48", "28", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "26", - "MKK", "5G", "20M", "HT", "2T", "52", "28", - "FCC", "5G", "20M", "HT", "2T", "56", "34", - "ETSI", "5G", "20M", "HT", "2T", "56", "26", - "MKK", "5G", "20M", "HT", "2T", "56", "28", - "FCC", "5G", "20M", "HT", "2T", "60", "34", - "ETSI", "5G", "20M", "HT", "2T", "60", "26", - "MKK", "5G", "20M", "HT", "2T", "60", "28", - "FCC", "5G", "20M", "HT", "2T", "64", "34", - "ETSI", "5G", "20M", "HT", "2T", "64", "26", - "MKK", "5G", "20M", "HT", "2T", "64", "28", - "FCC", "5G", "20M", "HT", "2T", "100", "34", - "ETSI", "5G", "20M", "HT", "2T", "100", "26", - "MKK", "5G", "20M", "HT", "2T", "100", "34", - "FCC", "5G", "20M", "HT", "2T", "114", "34", - "ETSI", "5G", "20M", "HT", "2T", "114", "26", - "MKK", "5G", "20M", "HT", "2T", "114", "34", - "FCC", "5G", "20M", "HT", "2T", "108", "34", - "ETSI", "5G", "20M", "HT", "2T", "108", "26", - "MKK", "5G", "20M", "HT", "2T", "108", "34", - "FCC", "5G", "20M", "HT", "2T", "112", "34", - "ETSI", "5G", "20M", "HT", "2T", "112", "26", - "MKK", "5G", "20M", "HT", "2T", "112", "34", - "FCC", "5G", "20M", "HT", "2T", "116", "34", - "ETSI", "5G", "20M", "HT", "2T", "116", "26", - "MKK", "5G", "20M", "HT", "2T", "116", "34", - "FCC", "5G", "20M", "HT", "2T", "120", "63", - "ETSI", "5G", "20M", "HT", "2T", "120", "26", - "MKK", "5G", "20M", "HT", "2T", "120", "34", - "FCC", "5G", "20M", "HT", "2T", "124", "63", - "ETSI", "5G", "20M", "HT", "2T", "124", "26", - "MKK", "5G", "20M", "HT", "2T", "124", "34", - "FCC", "5G", "20M", "HT", "2T", "128", "63", - "ETSI", "5G", "20M", "HT", "2T", "128", "26", - "MKK", "5G", "20M", "HT", "2T", "128", "34", - "FCC", "5G", "20M", "HT", "2T", "132", "34", - "ETSI", "5G", "20M", "HT", "2T", "132", "26", - "MKK", "5G", "20M", "HT", "2T", "132", "34", - "FCC", "5G", "20M", "HT", "2T", "136", "34", - "ETSI", "5G", "20M", "HT", "2T", "136", "26", - "MKK", "5G", "20M", "HT", "2T", "136", "34", - "FCC", "5G", "20M", "HT", "2T", "140", "34", - "ETSI", "5G", "20M", "HT", "2T", "140", "26", - "MKK", "5G", "20M", "HT", "2T", "140", "34", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "28", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "34", - "FCC", "5G", "40M", "HT", "1T", "46", "34", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "34", - "FCC", "5G", "40M", "HT", "1T", "54", "34", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "34", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "34", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "34", - "FCC", "5G", "40M", "HT", "1T", "110", "34", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "34", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "34", - "FCC", "5G", "40M", "HT", "1T", "126", "63", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "34", - "FCC", "5G", "40M", "HT", "1T", "134", "34", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "34", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "26", - "MKK", "5G", "40M", "HT", "2T", "38", "28", - "FCC", "5G", "40M", "HT", "2T", "46", "34", - "ETSI", "5G", "40M", "HT", "2T", "46", "26", - "MKK", "5G", "40M", "HT", "2T", "46", "28", - "FCC", "5G", "40M", "HT", "2T", "54", "34", - "ETSI", "5G", "40M", "HT", "2T", "54", "26", - "MKK", "5G", "40M", "HT", "2T", "54", "28", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "26", - "MKK", "5G", "40M", "HT", "2T", "62", "28", - "FCC", "5G", "40M", "HT", "2T", "102", "28", - "ETSI", "5G", "40M", "HT", "2T", "102", "26", - "MKK", "5G", "40M", "HT", "2T", "102", "34", - "FCC", "5G", "40M", "HT", "2T", "110", "34", - "ETSI", "5G", "40M", "HT", "2T", "110", "26", - "MKK", "5G", "40M", "HT", "2T", "110", "34", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "26", - "MKK", "5G", "40M", "HT", "2T", "118", "34", - "FCC", "5G", "40M", "HT", "2T", "126", "63", - "ETSI", "5G", "40M", "HT", "2T", "126", "26", - "MKK", "5G", "40M", "HT", "2T", "126", "34", - "FCC", "5G", "40M", "HT", "2T", "134", "34", - "ETSI", "5G", "40M", "HT", "2T", "134", "26", - "MKK", "5G", "40M", "HT", "2T", "134", "34", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "24", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "32", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "26", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "34", - "FCC", "5G", "80M", "VHT", "1T", "122", "63", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "34", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "24", - "ETSI", "5G", "80M", "VHT", "2T", "42", "26", - "MKK", "5G", "80M", "VHT", "2T", "42", "24", - "FCC", "5G", "80M", "VHT", "2T", "58", "30", - "ETSI", "5G", "80M", "VHT", "2T", "58", "26", - "MKK", "5G", "80M", "VHT", "2T", "58", "26", - "FCC", "5G", "80M", "VHT", "2T", "106", "26", - "ETSI", "5G", "80M", "VHT", "2T", "106", "26", - "MKK", "5G", "80M", "VHT", "2T", "106", "34", - "FCC", "5G", "80M", "VHT", "2T", "122", "63", - "ETSI", "5G", "80M", "VHT", "2T", "122", "26", - "MKK", "5G", "80M", "VHT", "2T", "122", "34", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_NFA812A00)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_NFA812A00; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_TPLINK.TXT -******************************************************************************/ - -const char *Array_MP_8812A_TXPWR_LMT_TPLINK[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "35", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "31", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "35", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "34", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "34", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "34", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "34", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "34", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "34", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "34", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "34", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "34", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "34", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "34", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "33", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "34", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "34", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "34", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "34", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "34", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "34", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "34", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "34", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "34", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "34", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "33", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "34", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "34", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "34", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "33", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "32", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "32", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "32", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "32", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "32", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "32", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "32", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "33", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "32", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "31", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "32", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "36", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "36", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "29", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "36", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "36", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "36", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "36", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "36", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "36", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "36", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "114", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "114", "36", - "MKK", "5G", "20M", "OFDM", "1T", "114", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "36", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "36", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "36", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "36", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "36", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "36", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "36", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "36", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "36", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "35", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "36", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "36", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "29", - "ETSI", "5G", "20M", "HT", "1T", "44", "36", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "36", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "33", - "ETSI", "5G", "20M", "HT", "1T", "52", "36", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "33", - "ETSI", "5G", "20M", "HT", "1T", "56", "36", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "33", - "ETSI", "5G", "20M", "HT", "1T", "60", "36", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "33", - "ETSI", "5G", "20M", "HT", "1T", "64", "36", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "33", - "ETSI", "5G", "20M", "HT", "1T", "100", "36", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "114", "33", - "ETSI", "5G", "20M", "HT", "1T", "114", "36", - "MKK", "5G", "20M", "HT", "1T", "114", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "33", - "ETSI", "5G", "20M", "HT", "1T", "108", "36", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "33", - "ETSI", "5G", "20M", "HT", "1T", "112", "36", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "33", - "ETSI", "5G", "20M", "HT", "1T", "116", "36", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "33", - "ETSI", "5G", "20M", "HT", "1T", "120", "36", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "33", - "ETSI", "5G", "20M", "HT", "1T", "124", "36", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "33", - "ETSI", "5G", "20M", "HT", "1T", "128", "36", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "33", - "ETSI", "5G", "20M", "HT", "1T", "132", "36", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "33", - "ETSI", "5G", "20M", "HT", "1T", "136", "36", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "33", - "ETSI", "5G", "20M", "HT", "1T", "140", "36", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "24", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "24", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "24", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "24", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "33", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "33", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "33", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "33", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "33", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "114", "33", - "ETSI", "5G", "20M", "HT", "2T", "114", "30", - "MKK", "5G", "20M", "HT", "2T", "114", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "33", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "33", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "33", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "33", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "33", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "33", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "33", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "33", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "33", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "33", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "33", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "33", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "33", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "33", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "33", - "ETSI", "5G", "40M", "HT", "1T", "38", "33", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "33", - "ETSI", "5G", "40M", "HT", "1T", "46", "33", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "33", - "ETSI", "5G", "40M", "HT", "1T", "54", "33", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "33", - "ETSI", "5G", "40M", "HT", "1T", "62", "33", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "33", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "33", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "33", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "33", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "33", - "ETSI", "5G", "40M", "HT", "1T", "134", "36", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "24", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "24", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "33", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "33", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "33", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "33", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "33", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "33", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "33", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "33", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "33", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "33", - "ETSI", "5G", "80M", "VHT", "1T", "42", "33", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "33", - "ETSI", "5G", "80M", "VHT", "1T", "58", "36", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "33", - "ETSI", "5G", "80M", "VHT", "1T", "106", "31", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "33", - "ETSI", "5G", "80M", "VHT", "1T", "122", "36", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "33", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "33", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "33", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "33", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "33", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "33", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_TPLINK)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_TPLINK; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8812A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_RadioA[] = { + 0x000, 0x00010000, + 0x018, 0x0001712A, + 0x056, 0x00051CF2, + 0x066, 0x00040000, + 0x01E, 0x00080000, + 0x089, 0x00000080, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x00014B3A, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x00014B3A, + 0xA0000000, 0x00000000, + 0x086, 0x00014B38, + 0xB0000000, 0x00000000, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x08B, 0x00080180, + 0xA0000000, 0x00000000, + 0x08B, 0x00087180, + 0xB0000000, 0x00000000, + 0x0B1, 0x0001FC1A, + 0x0B3, 0x000F0810, + 0x0B4, 0x0001A78D, + 0x0BA, 0x00086180, + 0x018, 0x00000006, + 0x0EF, 0x00002000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F218, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x0003F218, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xA0000000, 0x00000000, + 0x03B, 0x00038A58, + 0x03B, 0x00037A58, + 0x03B, 0x0002A590, + 0x03B, 0x00027A50, + 0x03B, 0x00018248, + 0x03B, 0x00010240, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A4EE, + 0x034, 0x00009076, + 0x034, 0x00008073, + 0x034, 0x00007070, + 0x034, 0x0000606D, + 0x034, 0x0000506A, + 0x034, 0x00004049, + 0x034, 0x00003046, + 0x034, 0x00002028, + 0x034, 0x00001025, + 0x034, 0x00000022, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF4, + 0x034, 0x00009DF1, + 0x034, 0x00008DEE, + 0x034, 0x00007DEB, + 0x034, 0x00006DE8, + 0x034, 0x00005DE5, + 0x034, 0x00004DE2, + 0x034, 0x00003CE6, + 0x034, 0x000024E7, + 0x034, 0x000014E4, + 0x034, 0x000004E1, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x0EF, 0x00000002, + 0x008, 0x00008400, + 0x018, 0x0001712A, + 0x0EF, 0x00001000, + 0x03A, 0x00000080, + 0x03B, 0x0003A02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x0003202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x0002B064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x00023070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0001B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00012085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0000A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00002080, + 0x03C, 0x00010000, + 0x03A, 0x00000080, + 0x03B, 0x0007A02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x0007202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x0006B064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x00063070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0005B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00052085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0004A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00042080, + 0x03C, 0x00010000, + 0x03A, 0x00000080, + 0x03B, 0x000BA02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x000B202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x000AB064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x000A3070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0009B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00092085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0008A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00082080, + 0x03C, 0x00010000, + 0x0EF, 0x00001100, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0B2, + 0x034, 0x000490AF, + 0x034, 0x00048070, + 0x034, 0x0004706D, + 0x034, 0x00046050, + 0x034, 0x0004504D, + 0x034, 0x0004404A, + 0x034, 0x00043047, + 0x034, 0x0004200A, + 0x034, 0x00041007, + 0x034, 0x00040004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0B2, + 0x034, 0x000490AF, + 0x034, 0x00048070, + 0x034, 0x0004706D, + 0x034, 0x0004604D, + 0x034, 0x0004504A, + 0x034, 0x00044047, + 0x034, 0x00043044, + 0x034, 0x00042007, + 0x034, 0x00041004, + 0x034, 0x00040001, + 0xA0000000, 0x00000000, + 0x034, 0x0004ADF5, + 0x034, 0x00049DF2, + 0x034, 0x00048DEF, + 0x034, 0x00047DEC, + 0x034, 0x00046DE9, + 0x034, 0x00045DE6, + 0x034, 0x00044DE3, + 0x034, 0x000438C8, + 0x034, 0x000428C5, + 0x034, 0x000418C2, + 0x034, 0x000408C0, + 0xB0000000, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0B2, + 0x034, 0x000290AF, + 0x034, 0x00028070, + 0x034, 0x0002706D, + 0x034, 0x00026050, + 0x034, 0x0002504D, + 0x034, 0x0002404A, + 0x034, 0x00023047, + 0x034, 0x0002200A, + 0x034, 0x00021007, + 0x034, 0x00020004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0B4, + 0x034, 0x000290B1, + 0x034, 0x00028072, + 0x034, 0x0002706F, + 0x034, 0x0002604F, + 0x034, 0x0002504C, + 0x034, 0x00024049, + 0x034, 0x00023046, + 0x034, 0x00022009, + 0x034, 0x00021006, + 0x034, 0x00020003, + 0xA0000000, 0x00000000, + 0x034, 0x0002ADF5, + 0x034, 0x00029DF2, + 0x034, 0x00028DEF, + 0x034, 0x00027DEC, + 0x034, 0x00026DE9, + 0x034, 0x00025DE6, + 0x034, 0x00024DE3, + 0x034, 0x000238C8, + 0x034, 0x000228C5, + 0x034, 0x000218C2, + 0x034, 0x000208C0, + 0xB0000000, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0B2, + 0x034, 0x000090AF, + 0x034, 0x00008070, + 0x034, 0x0000706D, + 0x034, 0x00006050, + 0x034, 0x0000504D, + 0x034, 0x0000404A, + 0x034, 0x00003047, + 0x034, 0x0000200A, + 0x034, 0x00001007, + 0x034, 0x00000004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0B2, + 0x034, 0x000090AF, + 0x034, 0x00008070, + 0x034, 0x0000706D, + 0x034, 0x0000604D, + 0x034, 0x0000504A, + 0x034, 0x00004047, + 0x034, 0x00003044, + 0x034, 0x00002007, + 0x034, 0x00001004, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000AFF7, + 0x034, 0x00009DF7, + 0x034, 0x00008DF4, + 0x034, 0x00007DF1, + 0x034, 0x00006DEE, + 0x034, 0x00005DEB, + 0x034, 0x00004DE8, + 0x034, 0x000038CC, + 0x034, 0x000028C9, + 0x034, 0x000018C6, + 0x034, 0x000008C3, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x000001D4, + 0x035, 0x000081D4, + 0x035, 0x000101D4, + 0x035, 0x000201B4, + 0x035, 0x000281B4, + 0x035, 0x000301B4, + 0x035, 0x000401B4, + 0x035, 0x000481B4, + 0x035, 0x000501B4, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x000001D4, + 0x035, 0x000081D4, + 0x035, 0x000101D4, + 0x035, 0x000201B4, + 0x035, 0x000281B4, + 0x035, 0x000301B4, + 0x035, 0x000401B4, + 0x035, 0x000481B4, + 0x035, 0x000501B4, + 0xA0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x00000188, + 0x035, 0x00008147, + 0x035, 0x00010147, + 0x035, 0x000201D7, + 0x035, 0x000281D7, + 0x035, 0x000301D7, + 0x035, 0x000401D8, + 0x035, 0x000481D8, + 0x035, 0x000501D8, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00004BFB, + 0x036, 0x0000CBFB, + 0x036, 0x00014BFB, + 0x036, 0x0001CBFB, + 0x036, 0x00024F4B, + 0x036, 0x0002CF4B, + 0x036, 0x00034F4B, + 0x036, 0x0003CF4B, + 0x036, 0x00044F4B, + 0x036, 0x0004CF4B, + 0x036, 0x00054F4B, + 0x036, 0x0005CF4B, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00004BFB, + 0x036, 0x0000CBFB, + 0x036, 0x00014BFB, + 0x036, 0x0001CBFB, + 0x036, 0x00024F4B, + 0x036, 0x0002CF4B, + 0x036, 0x00034F4B, + 0x036, 0x0003CF4B, + 0x036, 0x00044F4B, + 0x036, 0x0004CF4B, + 0x036, 0x00054F4B, + 0x036, 0x0005CF4B, + 0xA0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00084EB4, + 0x036, 0x0008CC35, + 0x036, 0x00094C35, + 0x036, 0x0009CC35, + 0x036, 0x000A4C35, + 0x036, 0x000ACC35, + 0x036, 0x000B4C35, + 0x036, 0x000BCC35, + 0x036, 0x000C4C34, + 0x036, 0x000CCC35, + 0x036, 0x000D4C35, + 0x036, 0x000DCC35, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000008, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000002CC, + 0x03C, 0x00000522, + 0x03C, 0x00000902, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x03C, 0x000002CC, + 0x03C, 0x00000522, + 0x03C, 0x00000902, + 0xA0000000, 0x00000000, + 0x03C, 0x000002A8, + 0x03C, 0x000005A2, + 0x03C, 0x00000880, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000002, + 0x0DF, 0x00000080, + 0x01F, 0x00000064, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000FDD43, + 0x062, 0x00038F4B, + 0x063, 0x00032117, + 0x064, 0x000194AC, + 0x065, 0x000931D1, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x061, 0x000FDD43, + 0x062, 0x00038F4B, + 0x063, 0x00032117, + 0x064, 0x000194AC, + 0x065, 0x000931D2, + 0xA0000000, 0x00000000, + 0x061, 0x000E5D53, + 0x062, 0x00038FCD, + 0x063, 0x000114EB, + 0x064, 0x000196AC, + 0x065, 0x000911D7, + 0xB0000000, 0x00000000, + 0x008, 0x00008400, + 0x01C, 0x000739D2, + 0x0B4, 0x0001E78D, + 0x018, 0x0001F12A, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x0B4, 0x0001A78D, + 0x018, 0x0001712A, + +}; + +void +ODM_ReadAndConfig_MP_8812A_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8812A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_RadioA(void) +{ + return 57; +} + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +u4Byte Array_MP_8812A_RadioB[] = { + 0x056, 0x00051CF2, + 0x066, 0x00040000, + 0x089, 0x00000080, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x00014B3A, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x086, 0x00014B3A, + 0xA0000000, 0x00000000, + 0x086, 0x00014B38, + 0xB0000000, 0x00000000, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x08B, 0x00080180, + 0xA0000000, 0x00000000, + 0x08B, 0x00087180, + 0xB0000000, 0x00000000, + 0x018, 0x00000006, + 0x0EF, 0x00002000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F218, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0x90000001, 0x00000005, 0x40000000, 0x00000000, + 0x03B, 0x0003F218, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xA0000000, 0x00000000, + 0x03B, 0x00038A58, + 0x03B, 0x00037A58, + 0x03B, 0x0002A590, + 0x03B, 0x00027A50, + 0x03B, 0x00018248, + 0x03B, 0x00010240, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A4EE, + 0x034, 0x00009076, + 0x034, 0x00008073, + 0x034, 0x00007070, + 0x034, 0x0000606D, + 0x034, 0x0000506A, + 0x034, 0x00004049, + 0x034, 0x00003046, + 0x034, 0x00002028, + 0x034, 0x00001025, + 0x034, 0x00000022, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF4, + 0x034, 0x00009DF1, + 0x034, 0x00008DEE, + 0x034, 0x00007DEB, + 0x034, 0x00006DE8, + 0x034, 0x00005DE5, + 0x034, 0x00004DE2, + 0x034, 0x00003CE6, + 0x034, 0x000024E7, + 0x034, 0x000014E4, + 0x034, 0x000004E1, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x0EF, 0x00000002, + 0x008, 0x00008400, + 0x018, 0x0001712A, + 0x0EF, 0x00001000, + 0x03A, 0x00000080, + 0x03B, 0x0003A02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x0003202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x0002B064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x00023070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0001B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00012085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0000A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00002080, + 0x03C, 0x00010000, + 0x03A, 0x00000080, + 0x03B, 0x0007A02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x0007202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x0006B064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x00063070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0005B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00052085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0004A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00042080, + 0x03C, 0x00010000, + 0x03A, 0x00000080, + 0x03B, 0x000BA02C, + 0x03C, 0x00004000, + 0x03A, 0x00000400, + 0x03B, 0x000B202C, + 0x03C, 0x00010000, + 0x03A, 0x000000A0, + 0x03B, 0x000AB064, + 0x03C, 0x00004000, + 0x03A, 0x000000D8, + 0x03B, 0x000A3070, + 0x03C, 0x00004000, + 0x03A, 0x00000468, + 0x03B, 0x0009B870, + 0x03C, 0x00010000, + 0x03A, 0x00000098, + 0x03B, 0x00092085, + 0x03C, 0x000E4000, + 0x03A, 0x00000418, + 0x03B, 0x0008A080, + 0x03C, 0x000F0000, + 0x03A, 0x00000418, + 0x03B, 0x00082080, + 0x03C, 0x00010000, + 0x0EF, 0x00001100, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0B2, + 0x034, 0x000490AF, + 0x034, 0x00048070, + 0x034, 0x0004706D, + 0x034, 0x00046050, + 0x034, 0x0004504D, + 0x034, 0x0004404A, + 0x034, 0x00043047, + 0x034, 0x0004200A, + 0x034, 0x00041007, + 0x034, 0x00040004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0B1, + 0x034, 0x000490AE, + 0x034, 0x0004806F, + 0x034, 0x0004706C, + 0x034, 0x0004604C, + 0x034, 0x00045049, + 0x034, 0x00044046, + 0x034, 0x00043043, + 0x034, 0x00042006, + 0x034, 0x00041003, + 0x034, 0x00040000, + 0xA0000000, 0x00000000, + 0x034, 0x0004ADF5, + 0x034, 0x00049DF2, + 0x034, 0x00048DEF, + 0x034, 0x00047DEC, + 0x034, 0x00046DE9, + 0x034, 0x00045DE6, + 0x034, 0x00044DE3, + 0x034, 0x000438C8, + 0x034, 0x000428C5, + 0x034, 0x000418C2, + 0x034, 0x000408C0, + 0xB0000000, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0B2, + 0x034, 0x000290AF, + 0x034, 0x00028070, + 0x034, 0x0002706D, + 0x034, 0x00026050, + 0x034, 0x0002504D, + 0x034, 0x0002404A, + 0x034, 0x00023047, + 0x034, 0x0002200A, + 0x034, 0x00021007, + 0x034, 0x00020004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0B3, + 0x034, 0x000290B0, + 0x034, 0x00028071, + 0x034, 0x0002706E, + 0x034, 0x0002604E, + 0x034, 0x0002504B, + 0x034, 0x00024048, + 0x034, 0x00023045, + 0x034, 0x00022008, + 0x034, 0x00021005, + 0x034, 0x00020002, + 0xA0000000, 0x00000000, + 0x034, 0x0002ADF5, + 0x034, 0x00029DF2, + 0x034, 0x00028DEF, + 0x034, 0x00027DEC, + 0x034, 0x00026DE9, + 0x034, 0x00025DE6, + 0x034, 0x00024DE3, + 0x034, 0x000238C8, + 0x034, 0x000228C5, + 0x034, 0x000218C2, + 0x034, 0x000208C0, + 0xB0000000, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0B2, + 0x034, 0x000090AF, + 0x034, 0x00008070, + 0x034, 0x0000706D, + 0x034, 0x00006050, + 0x034, 0x0000504D, + 0x034, 0x0000404A, + 0x034, 0x00003047, + 0x034, 0x0000200A, + 0x034, 0x00001007, + 0x034, 0x00000004, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0B3, + 0x034, 0x000090B0, + 0x034, 0x00008070, + 0x034, 0x0000706D, + 0x034, 0x0000604D, + 0x034, 0x0000504A, + 0x034, 0x00004047, + 0x034, 0x00003044, + 0x034, 0x00002007, + 0x034, 0x00001004, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000AFF7, + 0x034, 0x00009DF7, + 0x034, 0x00008DF4, + 0x034, 0x00007DF1, + 0x034, 0x00006DEE, + 0x034, 0x00005DEB, + 0x034, 0x00004DE8, + 0x034, 0x000038CC, + 0x034, 0x000028C9, + 0x034, 0x000018C6, + 0x034, 0x000008C3, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x000001C5, + 0x035, 0x000081C5, + 0x035, 0x000101C5, + 0x035, 0x00020174, + 0x035, 0x00028174, + 0x035, 0x00030174, + 0x035, 0x00040185, + 0x035, 0x00048185, + 0x035, 0x00050185, + 0x0EF, 0x00000000, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x000001C5, + 0x035, 0x000081C5, + 0x035, 0x000101C5, + 0x035, 0x00020174, + 0x035, 0x00028174, + 0x035, 0x00030174, + 0x035, 0x00040185, + 0x035, 0x00048185, + 0x035, 0x00050185, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x035, 0x00000188, + 0x035, 0x00008147, + 0x035, 0x00010147, + 0x035, 0x000201D7, + 0x035, 0x000281D7, + 0x035, 0x000301D7, + 0x035, 0x000401D8, + 0x035, 0x000481D8, + 0x035, 0x000501D8, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00005B8B, + 0x036, 0x0000DB8B, + 0x036, 0x00015B8B, + 0x036, 0x0001DB8B, + 0x036, 0x000262DB, + 0x036, 0x0002E2DB, + 0x036, 0x000362DB, + 0x036, 0x0003E2DB, + 0x036, 0x0004553B, + 0x036, 0x0004D53B, + 0x036, 0x0005553B, + 0x036, 0x0005D53B, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00005B8B, + 0x036, 0x0000DB8B, + 0x036, 0x00015B8B, + 0x036, 0x0001DB8B, + 0x036, 0x000262DB, + 0x036, 0x0002E2DB, + 0x036, 0x000362DB, + 0x036, 0x0003E2DB, + 0x036, 0x0004553B, + 0x036, 0x0004D53B, + 0x036, 0x0005553B, + 0x036, 0x0005D53B, + 0xA0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x036, 0x00084EB4, + 0x036, 0x0008CC35, + 0x036, 0x00094C35, + 0x036, 0x0009CC35, + 0x036, 0x000A4C35, + 0x036, 0x000ACC35, + 0x036, 0x000B4C35, + 0x036, 0x000BCC35, + 0x036, 0x000C4C34, + 0x036, 0x000CCC35, + 0x036, 0x000D4C35, + 0x036, 0x000DCC35, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000008, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000002DC, + 0x03C, 0x00000524, + 0x03C, 0x00000902, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x03C, 0x000002DC, + 0x03C, 0x00000524, + 0x03C, 0x00000902, + 0xA0000000, 0x00000000, + 0x03C, 0x000002A8, + 0x03C, 0x000005A2, + 0x03C, 0x00000880, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000002, + 0x0DF, 0x00000080, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000EAC43, + 0x062, 0x00038F47, + 0x063, 0x00031157, + 0x064, 0x0001C4AC, + 0x065, 0x000931D1, + 0x90000008, 0x05000000, 0x40000000, 0x00000000, + 0x061, 0x000EAC43, + 0x062, 0x00038F47, + 0x063, 0x00031157, + 0x064, 0x0001C4AC, + 0x065, 0x000931D2, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000EAC43, + 0x062, 0x00038F47, + 0x063, 0x00031157, + 0x064, 0x0001C4AC, + 0x065, 0x000931D1, + 0xA0000000, 0x00000000, + 0x061, 0x000E5D53, + 0x062, 0x00038FCD, + 0x063, 0x000114EB, + 0x064, 0x000196AC, + 0x065, 0x000911D7, + 0xB0000000, 0x00000000, + 0x008, 0x00008400, + +}; + +void +ODM_ReadAndConfig_MP_8812A_RadioB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8812A_RadioB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8812A_RadioB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_RadioB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioB_8812A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8812A_RadioB(void) +{ + return 57; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 18, 19, 19, 19}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8812A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13}, + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13}, + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8812A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_RFE3.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 18, 18}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 14, 13, 13, 14, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 16, 16, 17, 17}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE3_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE3_8812A[] = {0, 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE3_8812A[] = {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE3_8812A[] = {0, 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11}; + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE3( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE3_8812A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_RFE4.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13}, + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13}, + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE4_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE4_8812A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE4_8812A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE4( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_RFE4_8812A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 4, 4, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8812A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8812A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}; +#endif + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8812A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8812A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8812A_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", + "MKK", "2.4G", "40M", "HT", "1T", "12", "32", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", + "MKK", "2.4G", "40M", "HT", "1T", "13", "32", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "30", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "36", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "36", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "36", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "36", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "36", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "36", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_HM812A03.TXT +******************************************************************************/ + +const char *Array_MP_8812A_TXPWR_LMT_HM812A03[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", + "ETSI", "2.4G", "20M", "OFDM", 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"OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "36", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "36", + "FCC", "2.4G", "20M", "HT", "1T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "36", + "FCC", "2.4G", "20M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "36", + "FCC", "2.4G", "20M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "36", + "FCC", "2.4G", "20M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "36", + "FCC", "2.4G", "20M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "36", + "FCC", "2.4G", "20M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "36", + "FCC", "2.4G", "20M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "36", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "36", + "FCC", "2.4G", "20M", "HT", "1T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "36", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "36", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "36", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "24", + "MKK", "2.4G", "20M", "HT", "2T", "01", "34", + "FCC", "2.4G", "20M", "HT", "2T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "24", + "MKK", "2.4G", "20M", "HT", "2T", "02", "34", + "FCC", "2.4G", "20M", "HT", "2T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "24", + "MKK", "2.4G", "20M", "HT", "2T", "03", "34", + "FCC", "2.4G", "20M", "HT", "2T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "24", + "MKK", "2.4G", "20M", "HT", "2T", "04", "34", + "FCC", "2.4G", "20M", "HT", "2T", "05", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "24", + "MKK", "2.4G", "20M", "HT", "2T", "05", "34", + "FCC", "2.4G", "20M", "HT", "2T", "06", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "24", + "MKK", "2.4G", "20M", "HT", "2T", "06", "34", + "FCC", "2.4G", "20M", "HT", "2T", "07", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "24", + "MKK", "2.4G", "20M", "HT", "2T", "07", "34", + "FCC", "2.4G", "20M", "HT", "2T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "24", + "MKK", "2.4G", "20M", "HT", "2T", "08", "34", + "FCC", "2.4G", "20M", "HT", "2T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "24", + "MKK", "2.4G", "20M", "HT", "2T", "09", "34", + "FCC", "2.4G", "20M", "HT", "2T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "24", + "MKK", "2.4G", "20M", "HT", "2T", "10", "34", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "24", + "MKK", "2.4G", "20M", "HT", "2T", "11", "34", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "24", + "MKK", "2.4G", "20M", "HT", "2T", "12", "34", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "24", + "MKK", "2.4G", "20M", "HT", "2T", "13", "34", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "24", + "MKK", "2.4G", "40M", "HT", "2T", "03", "34", + "FCC", "2.4G", "40M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "24", + "MKK", "2.4G", "40M", "HT", "2T", "04", "34", + "FCC", "2.4G", "40M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "24", + "MKK", "2.4G", "40M", "HT", "2T", "05", "34", + "FCC", "2.4G", "40M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "24", + "MKK", "2.4G", "40M", "HT", "2T", "06", "34", + "FCC", "2.4G", "40M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "24", + "MKK", "2.4G", "40M", "HT", "2T", "07", "34", + "FCC", "2.4G", "40M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "24", + "MKK", "2.4G", "40M", "HT", "2T", "08", "34", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "24", + "MKK", "2.4G", "40M", "HT", "2T", "09", "34", + "FCC", "2.4G", "40M", "HT", "2T", "10", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "24", + "MKK", "2.4G", "40M", "HT", "2T", "10", "34", + "FCC", "2.4G", "40M", "HT", "2T", "11", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "24", + "MKK", "2.4G", "40M", "HT", "2T", "11", "34", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "36", + "FCC", "5G", "20M", "OFDM", "1T", "104", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "36", + "FCC", "5G", "20M", "OFDM", "1T", "108", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "36", + "FCC", "5G", "20M", "OFDM", "1T", "112", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "36", + "FCC", "5G", "20M", "OFDM", "1T", "116", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "36", + "FCC", "5G", "20M", "OFDM", "1T", "120", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "36", + "FCC", "5G", "20M", "OFDM", "1T", "124", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "36", + "FCC", "5G", "20M", "OFDM", "1T", "128", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "36", + "FCC", "5G", "20M", "OFDM", "1T", "132", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "36", + "FCC", "5G", "20M", "OFDM", "1T", "136", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "36", + "FCC", "5G", "20M", "OFDM", "1T", "140", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "36", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "36", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "30", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "36", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "36", + "FCC", "5G", "20M", "HT", "1T", "104", "36", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "36", + "FCC", "5G", "20M", "HT", "1T", "108", "36", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "36", + "FCC", "5G", "20M", "HT", "1T", "112", "36", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "36", + "FCC", "5G", "20M", "HT", "1T", "116", "36", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "36", + "FCC", "5G", "20M", "HT", "1T", "120", "63", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "36", + "FCC", "5G", "20M", "HT", "1T", "124", "63", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "36", + "FCC", "5G", "20M", "HT", "1T", "128", "63", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "36", + "FCC", "5G", "20M", "HT", "1T", "132", "36", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "36", + "FCC", "5G", "20M", "HT", "1T", "136", "36", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "36", + "FCC", "5G", "20M", "HT", "1T", "140", "30", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "36", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "36", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "36", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "36", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "36", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "22", + "ETSI", "5G", "20M", "HT", "2T", "36", "26", + "MKK", "5G", "20M", "HT", "2T", "36", "26", + "FCC", "5G", "20M", "HT", "2T", "40", "22", + "ETSI", "5G", "20M", "HT", "2T", "40", "26", + "MKK", "5G", "20M", "HT", "2T", "40", "26", + "FCC", "5G", "20M", "HT", "2T", "44", "22", + "ETSI", "5G", "20M", "HT", "2T", "44", "26", + "MKK", "5G", "20M", "HT", "2T", "44", "26", + "FCC", "5G", "20M", "HT", "2T", "48", "22", + "ETSI", "5G", "20M", "HT", "2T", "48", "26", + "MKK", "5G", "20M", "HT", "2T", "48", "26", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "26", + "MKK", "5G", "20M", "HT", "2T", "52", "26", + "FCC", "5G", "20M", "HT", "2T", "56", "36", + "ETSI", "5G", "20M", "HT", "2T", "56", "26", + "MKK", "5G", "20M", "HT", "2T", "56", "26", + "FCC", "5G", "20M", "HT", "2T", "60", "36", + "ETSI", "5G", "20M", "HT", "2T", "60", "26", + "MKK", "5G", "20M", "HT", "2T", "60", "26", + "FCC", "5G", "20M", "HT", "2T", "64", "30", + "ETSI", "5G", "20M", "HT", "2T", "64", "26", + "MKK", "5G", "20M", "HT", "2T", "64", "26", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "26", + "MKK", "5G", "20M", "HT", "2T", "100", "34", + "FCC", "5G", "20M", "HT", "2T", "104", "36", + "ETSI", "5G", "20M", "HT", "2T", "104", "26", + "MKK", "5G", "20M", "HT", "2T", "104", "34", + "FCC", "5G", "20M", "HT", "2T", "108", "36", + "ETSI", "5G", "20M", "HT", "2T", "108", "26", + "MKK", "5G", "20M", "HT", "2T", "108", "34", + "FCC", "5G", "20M", "HT", "2T", "112", "36", + "ETSI", "5G", "20M", "HT", "2T", "112", "26", + "MKK", "5G", "20M", "HT", "2T", "112", "34", + "FCC", "5G", "20M", "HT", "2T", "116", "36", + "ETSI", "5G", "20M", "HT", "2T", "116", "26", + "MKK", "5G", "20M", "HT", "2T", "116", "34", + "FCC", "5G", "20M", "HT", "2T", "120", "63", + "ETSI", "5G", "20M", "HT", "2T", "120", "26", + "MKK", "5G", "20M", "HT", "2T", "120", "34", + "FCC", "5G", "20M", "HT", "2T", "124", "63", + "ETSI", "5G", "20M", "HT", "2T", "124", "26", + "MKK", "5G", "20M", "HT", "2T", "124", "34", + "FCC", "5G", "20M", "HT", "2T", "128", "63", + "ETSI", "5G", "20M", "HT", "2T", "128", "26", + "MKK", "5G", "20M", "HT", "2T", "128", "34", + "FCC", "5G", "20M", "HT", "2T", "132", "36", + "ETSI", "5G", "20M", "HT", "2T", "132", "26", + "MKK", "5G", "20M", "HT", "2T", "132", "34", + "FCC", "5G", "20M", "HT", "2T", "136", "36", + "ETSI", "5G", "20M", "HT", "2T", "136", "26", + "MKK", "5G", "20M", "HT", "2T", "136", "34", + "FCC", "5G", "20M", "HT", "2T", "140", "30", + "ETSI", "5G", "20M", "HT", "2T", "140", "26", + "MKK", "5G", "20M", "HT", "2T", "140", "34", + "FCC", "5G", "20M", "HT", "2T", "149", "36", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "36", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "36", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "36", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "36", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "20", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "34", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "34", + "FCC", "5G", "40M", "HT", "1T", "54", "34", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "34", + "FCC", "5G", "40M", "HT", "1T", "62", "20", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "34", + "FCC", "5G", "40M", "HT", "1T", "102", "22", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "36", + "FCC", "5G", "40M", "HT", "1T", "110", "36", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "34", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "34", + "FCC", "5G", "40M", "HT", "1T", "126", "63", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "34", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "34", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "26", + "MKK", "5G", "40M", "HT", "2T", "38", "26", + "FCC", "5G", "40M", "HT", "2T", "46", "22", + "ETSI", "5G", "40M", "HT", "2T", "46", "26", + "MKK", "5G", "40M", "HT", "2T", "46", "26", + "FCC", "5G", "40M", "HT", "2T", "54", "34", + "ETSI", "5G", "40M", "HT", "2T", "54", "26", + "MKK", "5G", "40M", "HT", "2T", "54", "26", + "FCC", "5G", "40M", "HT", "2T", "62", "20", + "ETSI", "5G", "40M", "HT", "2T", "62", "26", + "MKK", "5G", "40M", "HT", "2T", "62", "26", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "26", + "MKK", "5G", "40M", "HT", "2T", "102", "36", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "26", + "MKK", "5G", "40M", "HT", "2T", "110", "34", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "26", + "MKK", "5G", "40M", "HT", "2T", "118", "34", + "FCC", "5G", "40M", "HT", "2T", "126", "63", + "ETSI", "5G", "40M", "HT", "2T", "126", "26", + "MKK", "5G", "40M", "HT", "2T", "126", "34", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "26", + "MKK", "5G", "40M", "HT", "2T", "134", "34", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "36", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "16", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "22", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "63", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "26", + "MKK", "5G", "80M", "VHT", "2T", "42", "28", + "FCC", "5G", "80M", "VHT", "2T", "58", "16", + "ETSI", "5G", "80M", "VHT", "2T", "58", "26", + "MKK", "5G", "80M", "VHT", "2T", "58", "28", + "FCC", "5G", "80M", "VHT", "2T", "106", "22", + "ETSI", "5G", "80M", "VHT", "2T", "106", "26", + "MKK", "5G", "80M", "VHT", "2T", "106", "32", + "FCC", "5G", "80M", "VHT", "2T", "122", "63", + "ETSI", "5G", "80M", "VHT", "2T", "122", "26", + "MKK", "5G", "80M", "VHT", "2T", "122", "32", + "FCC", "5G", "80M", "VHT", "2T", "155", "36", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_HM812A03)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_HM812A03; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_NFA812A00.TXT +******************************************************************************/ + +const char *Array_MP_8812A_TXPWR_LMT_NFA812A00[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "36", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "36", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "24", + "MKK", "2.4G", "20M", "HT", "2T", "01", "34", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "24", + "MKK", "2.4G", "20M", "HT", "2T", "02", "34", + "FCC", "2.4G", "20M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "24", + "MKK", "2.4G", "20M", "HT", "2T", "03", "34", + "FCC", "2.4G", "20M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "24", + "MKK", "2.4G", "20M", "HT", "2T", "04", "34", + "FCC", "2.4G", "20M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "24", + "MKK", "2.4G", "20M", "HT", "2T", "05", "34", + "FCC", "2.4G", "20M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "24", + "MKK", "2.4G", "20M", "HT", "2T", "06", "34", + "FCC", "2.4G", "20M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "24", + "MKK", "2.4G", "20M", "HT", "2T", "07", "34", + "FCC", "2.4G", "20M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "24", + "MKK", "2.4G", "20M", "HT", "2T", "08", "34", + "FCC", "2.4G", "20M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "24", + "MKK", "2.4G", "20M", "HT", "2T", "09", "34", + "FCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "24", + "MKK", "2.4G", "20M", "HT", "2T", "10", "34", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "24", + "MKK", "2.4G", "20M", "HT", "2T", "11", "34", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "24", + "MKK", "2.4G", "20M", "HT", "2T", "12", "34", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "24", + "MKK", "2.4G", "20M", "HT", "2T", "13", "34", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "24", + "MKK", "2.4G", "40M", "HT", "2T", "03", "34", + "FCC", "2.4G", "40M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "24", + "MKK", "2.4G", "40M", "HT", "2T", "04", "34", + "FCC", "2.4G", "40M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "24", + "MKK", "2.4G", "40M", "HT", "2T", "05", "34", + "FCC", "2.4G", "40M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "24", + "MKK", "2.4G", "40M", "HT", "2T", "06", "34", + "FCC", "2.4G", "40M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "24", + "MKK", "2.4G", "40M", "HT", "2T", "07", "34", + "FCC", "2.4G", "40M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "24", + "MKK", "2.4G", "40M", "HT", "2T", "08", "34", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "24", + "MKK", "2.4G", "40M", "HT", "2T", "09", "34", + "FCC", "2.4G", "40M", "HT", "2T", "10", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "24", + "MKK", "2.4G", "40M", "HT", "2T", "10", "34", + "FCC", "2.4G", "40M", "HT", "2T", "11", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "24", + "MKK", "2.4G", "40M", "HT", "2T", "11", "34", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "34", + "FCC", "5G", "20M", "OFDM", "1T", "40", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "34", + "FCC", "5G", "20M", "OFDM", "1T", "44", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "34", + "FCC", "5G", "20M", "OFDM", "1T", "114", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "34", + "FCC", "5G", "20M", "OFDM", "1T", "108", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "34", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "34", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "34", + "FCC", "5G", "20M", "OFDM", "1T", "120", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "34", + "FCC", "5G", "20M", "OFDM", "1T", "124", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "34", + "FCC", "5G", "20M", "OFDM", "1T", "128", "63", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "34", + "FCC", "5G", "20M", "OFDM", "1T", "132", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "34", + "FCC", "5G", "20M", "OFDM", "1T", "136", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "34", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "34", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "34", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "34", + "FCC", "5G", "20M", "HT", "1T", "40", "34", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "34", + "FCC", "5G", "20M", "HT", "1T", "44", "34", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "34", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "34", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "34", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "34", + "FCC", "5G", "20M", "HT", "1T", "114", "34", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "34", + "FCC", "5G", "20M", "HT", "1T", "108", "34", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "34", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "34", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "34", + "FCC", "5G", "20M", "HT", "1T", "120", "63", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "34", + "FCC", "5G", "20M", "HT", "1T", "124", "63", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "34", + "FCC", "5G", "20M", "HT", "1T", "128", "63", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "34", + "FCC", "5G", "20M", "HT", "1T", "132", "34", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "34", + "FCC", "5G", "20M", "HT", "1T", "136", "34", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "34", + "FCC", "5G", "20M", "HT", "1T", "140", "34", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "34", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "26", + "MKK", "5G", "20M", "HT", "2T", "36", "28", + "FCC", "5G", "20M", "HT", "2T", "40", "34", + "ETSI", "5G", "20M", "HT", "2T", "40", "26", + "MKK", "5G", "20M", "HT", "2T", "40", "28", + "FCC", "5G", "20M", "HT", "2T", "44", "34", + "ETSI", "5G", "20M", "HT", "2T", "44", "26", + "MKK", "5G", "20M", "HT", "2T", "44", "28", + "FCC", "5G", "20M", "HT", "2T", "48", "34", + "ETSI", "5G", "20M", "HT", "2T", "48", "26", + "MKK", "5G", "20M", "HT", "2T", "48", "28", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "26", + "MKK", "5G", "20M", "HT", "2T", "52", "28", + "FCC", "5G", "20M", "HT", "2T", "56", "34", + "ETSI", "5G", "20M", "HT", "2T", "56", "26", + "MKK", "5G", "20M", "HT", "2T", "56", "28", + "FCC", "5G", "20M", "HT", "2T", "60", "34", + "ETSI", "5G", "20M", "HT", "2T", "60", "26", + "MKK", "5G", "20M", "HT", "2T", "60", "28", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "26", + "MKK", "5G", "20M", "HT", "2T", "64", "28", + "FCC", "5G", "20M", "HT", "2T", "100", "34", + "ETSI", "5G", "20M", "HT", "2T", "100", "26", + "MKK", "5G", "20M", "HT", "2T", "100", "34", + "FCC", "5G", "20M", "HT", "2T", "114", "34", + "ETSI", "5G", "20M", "HT", "2T", "114", "26", + "MKK", "5G", "20M", "HT", "2T", "114", "34", + "FCC", "5G", "20M", "HT", "2T", "108", "34", + "ETSI", "5G", "20M", "HT", "2T", "108", "26", + "MKK", "5G", "20M", "HT", "2T", "108", "34", + "FCC", "5G", "20M", "HT", "2T", "112", "34", + "ETSI", "5G", "20M", "HT", "2T", "112", "26", + "MKK", "5G", "20M", "HT", "2T", "112", "34", + "FCC", "5G", "20M", "HT", "2T", "116", "34", + "ETSI", "5G", "20M", "HT", "2T", "116", "26", + "MKK", "5G", "20M", "HT", "2T", "116", "34", + "FCC", "5G", "20M", "HT", "2T", "120", "63", + "ETSI", "5G", "20M", "HT", "2T", "120", "26", + "MKK", "5G", "20M", "HT", "2T", "120", "34", + "FCC", "5G", "20M", "HT", "2T", "124", "63", + "ETSI", "5G", "20M", "HT", "2T", "124", "26", + "MKK", "5G", "20M", "HT", "2T", "124", "34", + "FCC", "5G", "20M", "HT", "2T", "128", "63", + "ETSI", "5G", "20M", "HT", "2T", "128", "26", + "MKK", "5G", "20M", "HT", "2T", "128", "34", + "FCC", "5G", "20M", "HT", "2T", "132", "34", + "ETSI", "5G", "20M", "HT", "2T", "132", "26", + "MKK", "5G", "20M", "HT", "2T", "132", "34", + "FCC", "5G", "20M", "HT", "2T", "136", "34", + "ETSI", "5G", "20M", "HT", "2T", "136", "26", + "MKK", "5G", "20M", "HT", "2T", "136", "34", + "FCC", "5G", "20M", "HT", "2T", "140", "34", + "ETSI", "5G", "20M", "HT", "2T", "140", "26", + "MKK", "5G", "20M", "HT", "2T", "140", "34", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "34", + "FCC", "5G", "40M", "HT", "1T", "46", "34", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "34", + "FCC", "5G", "40M", "HT", "1T", "54", "34", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "34", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "34", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "34", + "FCC", "5G", "40M", "HT", "1T", "110", "34", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "34", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "34", + "FCC", "5G", "40M", "HT", "1T", "126", "63", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "34", + "FCC", "5G", "40M", "HT", "1T", "134", "34", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "34", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "26", + "MKK", "5G", "40M", "HT", "2T", "38", "28", + "FCC", "5G", "40M", "HT", "2T", "46", "34", + "ETSI", "5G", "40M", "HT", "2T", "46", "26", + "MKK", "5G", "40M", "HT", "2T", "46", "28", + "FCC", "5G", "40M", "HT", "2T", "54", "34", + "ETSI", "5G", "40M", "HT", "2T", "54", "26", + "MKK", "5G", "40M", "HT", "2T", "54", "28", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "26", + "MKK", "5G", "40M", "HT", "2T", "62", "28", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "26", + "MKK", "5G", "40M", "HT", "2T", "102", "34", + "FCC", "5G", "40M", "HT", "2T", "110", "34", + "ETSI", "5G", "40M", "HT", "2T", "110", "26", + "MKK", "5G", "40M", "HT", "2T", "110", "34", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "26", + "MKK", "5G", "40M", "HT", "2T", "118", "34", + "FCC", "5G", "40M", "HT", "2T", "126", "63", + "ETSI", "5G", "40M", "HT", "2T", "126", "26", + "MKK", "5G", "40M", "HT", "2T", "126", "34", + "FCC", "5G", "40M", "HT", "2T", "134", "34", + "ETSI", "5G", "40M", "HT", "2T", "134", "26", + "MKK", "5G", "40M", "HT", "2T", "134", "34", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "24", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "32", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "26", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "34", + "FCC", "5G", "80M", "VHT", "1T", "122", "63", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "34", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "26", + "MKK", "5G", "80M", "VHT", "2T", "42", "24", + "FCC", "5G", "80M", "VHT", "2T", "58", "30", + "ETSI", "5G", "80M", "VHT", "2T", "58", "26", + "MKK", "5G", "80M", "VHT", "2T", "58", "26", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "26", + "MKK", "5G", "80M", "VHT", "2T", "106", "34", + "FCC", "5G", "80M", "VHT", "2T", "122", "63", + "ETSI", "5G", "80M", "VHT", "2T", "122", "26", + "MKK", "5G", "80M", "VHT", "2T", "122", "34", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_NFA812A00)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_NFA812A00; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_TPLINK.TXT +******************************************************************************/ + +const char *Array_MP_8812A_TXPWR_LMT_TPLINK[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "35", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "31", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "35", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "34", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "34", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "34", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "34", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "34", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "34", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "34", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "34", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "34", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "34", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "34", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "33", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "34", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "34", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "34", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "34", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "34", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "34", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "34", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "34", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "34", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "34", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "33", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "34", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "34", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "34", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "33", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", + "MKK", "2.4G", "40M", "HT", "1T", "12", "32", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", + "MKK", "2.4G", "40M", "HT", "1T", "13", "32", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "32", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "32", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "32", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "32", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "32", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "32", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "32", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "33", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "32", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "31", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "32", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "36", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "36", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "29", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "36", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "36", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "36", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "36", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "36", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "36", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "36", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "36", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "36", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "36", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "36", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "36", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "36", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "36", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "36", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "36", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "36", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "35", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "36", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "36", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "29", + "ETSI", "5G", "20M", "HT", "1T", "44", "36", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "36", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "33", + "ETSI", "5G", "20M", "HT", "1T", "52", "36", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "33", + "ETSI", "5G", "20M", "HT", "1T", "56", "36", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "33", + "ETSI", "5G", "20M", "HT", "1T", "60", "36", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "33", + "ETSI", "5G", "20M", "HT", "1T", "64", "36", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "33", + "ETSI", "5G", "20M", "HT", "1T", "100", "36", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "33", + "ETSI", "5G", "20M", "HT", "1T", "114", "36", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "33", + "ETSI", "5G", "20M", "HT", "1T", "108", "36", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "33", + "ETSI", "5G", "20M", "HT", "1T", "112", "36", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "33", + "ETSI", "5G", "20M", "HT", "1T", "116", "36", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "33", + "ETSI", "5G", "20M", "HT", "1T", "120", "36", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "33", + "ETSI", "5G", "20M", "HT", "1T", "124", "36", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "33", + "ETSI", "5G", "20M", "HT", "1T", "128", "36", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "33", + "ETSI", "5G", "20M", "HT", "1T", "132", "36", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "33", + "ETSI", "5G", "20M", "HT", "1T", "136", "36", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "33", + "ETSI", "5G", "20M", "HT", "1T", "140", "36", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "24", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "24", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "24", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "24", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "33", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "33", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "33", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "33", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "33", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "33", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "33", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "33", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "33", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "33", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "33", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "33", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "33", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "33", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "33", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "33", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "33", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "33", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "33", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "33", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "33", + "ETSI", "5G", "40M", "HT", "1T", "38", "33", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "33", + "ETSI", "5G", "40M", "HT", "1T", "46", "33", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "33", + "ETSI", "5G", "40M", "HT", "1T", "54", "33", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "33", + "ETSI", "5G", "40M", "HT", "1T", "62", "33", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "33", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "33", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "33", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "33", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "33", + "ETSI", "5G", "40M", "HT", "1T", "134", "36", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "24", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "24", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "33", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "33", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "33", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "33", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "33", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "33", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "33", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "33", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "33", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "33", + "ETSI", "5G", "80M", "VHT", "1T", "42", "33", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "33", + "ETSI", "5G", "80M", "VHT", "1T", "58", "36", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "33", + "ETSI", "5G", "80M", "VHT", "1T", "106", "31", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "33", + "ETSI", "5G", "80M", "VHT", "1T", "122", "36", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "33", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "33", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "33", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "33", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "33", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "33", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8812A_TXPWR_LMT_TPLINK)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8812A_TXPWR_LMT_TPLINK; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8812A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.h index 3fb3706f6bd..a726fa641a6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halhwimg8812a_rf.h @@ -1,139 +1,139 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8812A_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8812A_H -#define __INC_MP_RF_HW_IMG_8812A_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_RadioA(void); - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_RadioB(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_RFE3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_RFE3(void); - -/****************************************************************************** -* TxPowerTrack_RFE4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_RFE4(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT(void); - -/****************************************************************************** -* TXPWR_LMT_HM812A03.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_HM812A03(void); - -/****************************************************************************** -* TXPWR_LMT_NFA812A00.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_NFA812A00(void); - -/****************************************************************************** -* TXPWR_LMT_TPLINK.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_TPLINK(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8812A_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8812A_H +#define __INC_MP_RF_HW_IMG_8812A_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_RadioA(void); + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_RadioB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_RadioB(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_RFE3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_RFE3(void); + +/****************************************************************************** +* TxPowerTrack_RFE4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_RFE4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_RFE4(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT(void); + +/****************************************************************************** +* TXPWR_LMT_HM812A03.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_HM812A03(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_HM812A03(void); + +/****************************************************************************** +* TXPWR_LMT_NFA812A00.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_NFA812A00(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_NFA812A00(void); + +/****************************************************************************** +* TXPWR_LMT_TPLINK.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8812A_TXPWR_LMT_TPLINK(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8812A_TXPWR_LMT_TPLINK(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.c index c88546fc6cd..0ebe15fa3fc 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.c @@ -1,3710 +1,3710 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "../mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8812A 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - -#if 0 - - - - //new element A = element D x X - - //new element C = element D x Y - - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#else - PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformAcquireMutex(&pHalData->mxChnlBwControl); -#endif -#endif - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8812A(Adapter, FALSE); - - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#if USE_WORKITEM - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#else - PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); -#endif -#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - PlatformReleaseMutex(&pHalData->mxChnlBwControl); -#endif -#endif -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr8812A( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - if (Method == TXAGC) - { - u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT]; - u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; - u1Byte rf = 0; - u4Byte pwr = 0, TxAGC = 0; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); - TxAGC = (pwr<<16)|(pwr<<8)|(pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); - RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); - - pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); - pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase); - TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); - PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); -#endif - - } - else if (Method == BBSWING) - { - // Adjust BB swing by OFDM IQ matrix - if (RFPath == RF_PATH_A) - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, bMaskDWord, pDM_Odm->BbSwingIdxOfdm[RF_PATH_A]); - else if (RFPath == RF_PATH_B) - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, bMaskDWord, pDM_Odm->BbSwingIdxOfdm[RF_PATH_B]); - } - else - { - return; - } -} // odm_TxPwrTrackSetPwr88E - -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; - pConfig->RfPathCount = 2; - pConfig->ThermalRegAddr = RF_T_METER_8812A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; - pConfig->DoIQK = DoIQK_8812A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; -} - -#endif - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK - phy_PathA_IQK_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - - //1 Tx IQK - //path-A IQK setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); - //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); - ODM_delay_ms(IQK_DELAY_TIME_8812A); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - -#if 0 - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); -#endif - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK - phy_PathA_RxIQK_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN configPathB - ) -{ - u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - - //1 Get TXIMR setting - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); - //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); - ODM_delay_ms(IQK_DELAY_TIME_8812A); - - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - - - //1 RX IQK - //modify RXIQK mode table - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - - //IQK setting - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - - //path-A IQK setting - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); - - //LO calibration setting - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - - //One shot, path A LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); - //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); - ODM_delay_ms(IQK_DELAY_TIME_8812A); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - -#if 0 - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; -#endif - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK - phy_PathB_IQK_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_8812A)); - //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); - ODM_delay_ms(IQK_DELAY_TIME_8812A); - - // Check failed - regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); - regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); - regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); - regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID - _PHY_PathAFillIQKMatrix_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - - TX0_C = (Y * Oldval_0) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", (u4Byte)Y, (u4Byte)TX0_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_8812A only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; -#if (DM_ODM_SUPPORT_TYPE==ODM_AP) - if( RTL_ABS(reg ,0x100) >= 16) - reg = 0x100; -#endif - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID - _PHY_PathBFillIQKMatrix_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - TX1_C = (Y * Oldval_1) >> 8; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", (u4Byte)Y, (u4Byte)TX1_C)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if 0 //!(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -VOID - _PHY_SaveADDARegisters_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID - _PHY_SaveMACRegisters_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID - _PHY_ReloadADDARegisters_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID - _PHY_ReloadMACRegisters_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - -VOID - _PHY_PathADDAOn_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ) -{ - u4Byte pathOn; - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); - - pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; - if(FALSE == is2T){ - pathOn = 0x0bdb25a0; - ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); - } - else{ - ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); - } - - for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ - ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); - } - -} - -VOID - _PHY_MACSettingCalibration_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -VOID - _PHY_PathAStandBy_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -VOID - _PHY_PIModeSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN PIMode - ) -{ - u4Byte mode; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); - - mode = PIMode ? 0x01000100 : 0x01000000; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); -} - -BOOLEAN - phy_SimularityCompare_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); -#else - BOOLEAN is2T = 0; -#endif - - if(is2T) - bound = 8; - else - bound = 4; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8812A c1 %d c2 %d!!!\n", c1, c2)); - - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8812A differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, (u4Byte)result[c1][i], (u4Byte)result[c2][i])); - - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1< Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xe90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} -void _IQK_BackupRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - RFB_backup[i] = ODM_GetRFReg(pDM_Odm, RF_PATH_B, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} -void _IQK_BackupAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} -void _IQK_RestoreMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} -void _IQK_RestoreRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - case ODM_RF_PATH_B: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); - } - break; - default: - break; - } -} -void _IQK_RestoreAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - - -void _IQK_ConfigureMAC_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_SetBBReg(pDM_Odm, 0x808, BIT(28), 0x0); // CCK Off - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off -} - -#define cal_num 3 - -void _IQK_Tx_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte chnlIdx - ) -{ - u4Byte TX_fail,RX_fail, delay_count, IQK_ready, cal_retry, cal = 0, temp_reg65; - int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0; - int TX_X0[cal_num], TX_Y0[cal_num], RX_X0[cal_num], RX_Y0[cal_num]; - BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; - int TX_X1[cal_num], TX_Y1[cal_num], RX_X1[cal_num], RX_Y1[cal_num]; - BOOLEAN TX1IQKOK = FALSE, RX1IQKOK = FALSE, VDF_enable = FALSE; - int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], Rx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - prtl8192cd_priv priv = pDM_Odm->priv; - - pDM_Odm->priv->pshare->IQK_total_cnt++; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d ExtPA = %d pBand = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA, *pDM_Odm->pBandType)); - if (*pDM_Odm->pBandWidth == 2){ - VDF_enable = TRUE; - } - temp_reg65 = ODM_GetRFReg(pDM_Odm, Path, 0x65, bMaskDWord); - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - // Port 1 DAC/ADC off - ODM_Write4Byte(pDM_Odm, 0xe60, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x00000000); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - - // IQK Setting - //====== TX IQK ====== - // 1. DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT(30), 0x1); - //ODM_SetBBReg(pDM_Odm, 0xcb0, 0x000000f0, 0x7); - ODM_SetBBReg(pDM_Odm, 0xcb0, 0x00ff0000, 0x77); - ODM_SetBBReg(pDM_Odm, 0xcb4, 0x03000000, 0x0); - } - break; - case ODM_RF_PATH_B: - {ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // Port 0 DAC/ADC off - ODM_Write4Byte(pDM_Odm, 0xc60, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x00000000); - - // Port 1 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off - - // DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT(30), 0x1); - //ODM_SetBBReg(pDM_Odm, 0xeb0, 0x000000f0, 0x7); - ODM_SetBBReg(pDM_Odm, 0xeb0, 0x00ff0000, 0x77); - ODM_SetBBReg(pDM_Odm, 0xeb4, 0x03000000, 0x0); - } - break; - default: - break; - } - while (cal < cal_num){ - switch (Path) { - case ODM_RF_PATH_A: - { - //====== TX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - - if (VDF_enable == 1){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXVDF Start\n")); - for (k = 0;k <= 2; k++){ - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 1: - { - ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Tx_dt = %d\n", Tx_dt[cal])); - Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); - Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); - } - break; - default: - break; - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((IQK_ready) || (delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_VDF_cal_retry = %d\n", cal_retry)); - TX_X0[cal] = VDF_X[k-1] ; - TX_Y0[cal] = VDF_Y[k-1]; - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - cal_retry = 0; - while(1){ - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 25ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((IQK_ready) || (delay_count>20)) { - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - /* - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - break; - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal_retry)); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (TX0IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - - if (VDF_enable == 1){ - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); // TX VDF Disable - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXVDF Start\n")); - - //====== RX mode TXK (RXK Step 1) ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161420); - - for (k = 0;k <= 2; k++){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (VDF_X[k])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (VDF_Y[k])>>21&0x000007ff); - - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(30), 0x0); - } - break; - case 1: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x28008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x08008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Rx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Rx_dt = %d\n", Rx_dt[cal])); - Rx_dt[cal] = ((16*Rx_dt[cal])*10000/13823); - Rx_dt[cal] = (Rx_dt[cal] >> 1 )+(Rx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, 0x00003fff, Rx_dt[cal] & 0x00003fff); - } - break; - default: - break; - } - - - if (k==2){ - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(30), 0x1); //RX VDF Enable - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_VDF_cal_retry = %d\n", cal_retry)); - RX_X0[cal] = VDF_X[k-1] ; - RX_Y0[cal] = VDF_Y[k-1]; - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); // TX VDF Enable - } - else{ - //====== RX mode TXK (RXK Step 1) ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // 1. TX RF Setting - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161cc0); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; -/* - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); -*/ - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal_retry)); - } - if (TX0IQKOK) - TX_Average++; - if (RX0IQKOK) - RX_Average++; - } - break; - case ODM_RF_PATH_B: - { - //Path-B TX/RX IQK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); - ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - - - if (pDM_Odm->ExtPA) - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); - else - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); - - if (VDF_enable == 1){ - for (k = 0;k <= 2; k++){ - switch (k){ - case 0: - { - // one shot - ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910); - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); - } - break; - case 1: - { - ODM_SetBBReg(pDM_Odm, 0xe80, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe84, BIT(28), 0x0); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910); - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Tx_dt = %d\n", Tx_dt[cal])); - Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); - Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xee8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); - } - break; - default: - break; - } - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK_ready) || (delay_count>20)) { - break; - } - else { - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - TX1IQKOK = TRUE; - break; - } - else{ - TX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - else{ - TX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_VDF_cal_retry = %d\n", cal_retry)); - TX_X1[cal] = VDF_X[k-1] ; - TX_Y1[cal] = VDF_Y[k-1]; - } - else{ - ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 25ms - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - TX_X1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - TX_Y1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - TX1IQKOK = TRUE; - /* - int reg1 = 0, reg2 = 0, Image_Power = 0; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - break; - } - else{ - TX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - else { - TX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal_retry)); - } - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (TX1IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - - - if (VDF_enable == 1){ - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); // TX VDF Disable - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXVDF Start\n")); - - //====== RX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xe88, 0x02140119); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161420); - - for (k = 0;k <= 2; k++){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (VDF_X[k])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (VDF_Y[k])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x0); - } - break; - case 1: - { - ODM_Write4Byte(pDM_Odm, 0xe80, 0x28008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x08008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x0); - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Rx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Rx_dt = %d\n", Rx_dt[cal])); - Rx_dt[cal] = ((16*Rx_dt[cal])*10000/13823); - Rx_dt[cal] = (Rx_dt[cal] >> 1 )+(Rx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xee8, 0x00003fff, Rx_dt[cal] & 0x00003fff); - } - break; - default: - break; - } - - - if (k==2){ - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x1); //RX VDF Enable - } - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); - if (RX_fail == 0){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - RX1IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0x0>>1); - RX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_VDF_cal_retry = %d\n", cal_retry)); - RX_X1[cal] = VDF_X[k-1] ; - RX_Y1[cal] = VDF_Y[k-1]; - ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x1); // TX VDF Enable - } - else{ - //====== RX mode TXK (RXK Step 1) ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X1[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y1[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c15);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c15);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xe88, 0x02140119); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161cc0); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ???SI/PI 使用æ¬?????iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); - if (RX_fail == 0){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - RX_X1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - RX_Y1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - RX1IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0x0>>1); - RX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - else{ - RX1IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal_retry)); - } - - - if (RX1IQKOK) - RX_Average++; - - - if (TX1IQKOK) - TX_Average++; - - } - break; - default: - break; - } - cal++; - } - // FillIQK Result - switch (Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - if (TX_Average == 0){ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - break; - } - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X0[ii]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); - if (dy < 4 && dy > -4){ - TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; - TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; - if (*pDM_Odm->pBandWidth == 2){ - Tx_dt[0] = (Tx_dt[i] + Tx_dt[ii])/2; - } - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[0] & 0x00003fff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - if (TX_finish == 1){ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - } - if (RX_Average == 0){ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - break; - } - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, (RX_X0[i])>>21&0x000007ff, i, (RX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[i]>>21) - (RX_Y0[ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X0[i]>>21) + (RX_X0[ii]>>21))/2; - RX_Y = ((RX_Y0[i]>>21) + (RX_Y0[ii]>>21))/2; - if (*pDM_Odm->pBandWidth == 2){ - Rx_dt[0] = (Rx_dt[i] + Rx_dt[ii])/2; - } - RX_finish = 1; - break; - } - } - } - if (RX_finish == 1) - break; - } - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xce8, 0x00003fff, Rx_dt[0] & 0x00003fff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - if (RX_finish == 1){ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - } - if (TX_finish && RX_finish){ - pRFCalibrateInfo->bNeedIQK = FALSE; - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0] = ((TX_X & 0x000007ff) << 16) + (TX_Y & 0x000007ff); //Path A TX - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1] = ((RX_X & 0x000007ff) << 16) + (RX_Y & 0x000007ff); //Path A RX - - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4] = ODM_Read4Byte( pDM_Odm, 0xce8); //Path B VDF - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - } - - } - break; - case ODM_RF_PATH_B: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); - if (TX_Average == 0){ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - break; - } - - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", i, (TX_X1[i])>>21&0x000007ff, i, (TX_Y1[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X1[ii]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_Y1[i]>>21) - (TX_Y1[ii]>>21); - if (dy < 4 && dy > -4){ - TX_X = ((TX_X1[i]>>21) + (TX_X1[ii]>>21))/2; - TX_Y = ((TX_Y1[i]>>21) + (TX_Y1[ii]>>21))/2; - if (*pDM_Odm->pBandWidth == 2){ - Tx_dt[0] = (Tx_dt[i] + Tx_dt[ii])/2; - } - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xee8, 0x3fff0000, Tx_dt[0] & 0x00003fff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - if (TX_finish == 1){ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - } - if (RX_Average == 0){ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - break; - } - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", i, (RX_X1[i])>>21&0x000007ff, i, (RX_Y1[i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X1[ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y1[i]>>21) - (RX_Y1[ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X1[i]>>21) + (RX_X1[ii]>>21))/2; - RX_Y = ((RX_Y1[i]>>21) + (RX_Y1[ii]>>21))/2; - if (*pDM_Odm->pBandWidth == 2){ - Rx_dt[0] = (Rx_dt[i] + Rx_dt[ii])/2; - } - RX_finish = 1; - break; - } - } - } - if (RX_finish == 1) - break; - } - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xee8, 0x00003fff, Rx_dt[0] & 0x00003fff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - if (RX_finish == 1){ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); - } - if (TX_finish && RX_finish){ - pRFCalibrateInfo->bNeedIQK = FALSE; - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2] = ((TX_X & 0x000007ff) << 16) + (TX_Y & 0x000007ff); //Path B TX - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3] = ((RX_X & 0x000007ff) << 16) + (RX_Y & 0x000007ff); //Path B RX - - if (*pDM_Odm->pBandWidth == 2){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C - pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5] = ODM_Read4Byte( pDM_Odm, 0xee8); //Path B VDF - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - } - } - - } - break; - default: - break; - } - - if (!TX_finish && !RX_finish) - priv->pshare->IQK_fail_cnt++; -} - -#define MACBB_REG_NUM 10 -#define AFE_REG_NUM 14 -#define RF_REG_NUM 3 -/* -IQK v1.0 update TXIQK high power parameter -*/ -VOID -phy_IQCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0x838, 0x90c, 0xb00, 0xc00, 0xe00, 0x8c4, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb8, 0xcb0, 0xcb4, - 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb8, 0xeb0, 0xeb4}; - u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; - u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); - - _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); - - _IQK_ConfigureMAC_8812A(pDM_Odm); - _IQK_Tx_8812A(pDM_Odm, ODM_RF_PATH_A, chnlIdx); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); - - _IQK_Tx_8812A(pDM_Odm, ODM_RF_PATH_B, chnlIdx); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); - - _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - - //_IQK_Exit_8812A(pDM_Odm); - //_IQK_TX_CheckResult_8812A - -} - - -VOID - phy_LCCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - //Check continuous TX and Packet TX - tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); -#else - RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); -#endif - - //2. Set RF mode = standby mode - //Path-A - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); -#else - LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits); -#endif - - //4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - ODM_delay_ms(100); - - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID - phy_APCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a - // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if defined(MP_DRIVER) && (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8812A() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - - // Temporarily do not allow normal driver to do the following settings because these offset - // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal - // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the - // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if !defined(MP_DRIVER) || (MP_DRIVER != 1) - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_8812A(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters_8812A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters_8812A(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters_8812A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - else if(path == RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_8812A(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration_8812A(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, (int)delta_V, (int)delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - if(path == RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_8812A(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters_8812A(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_8812A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters_8812A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); - if(path == RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == RF_PATH_A) - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8812A()\n")); -} - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - -#if 0 //FOR_8812_IQK -VOID -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#endif -#if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif -#endif//(MP_DRIVER == 1) - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - -#if MP_DRIVER == 1 - if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) -#endif - phy_IQCalibrate_8812A(pDM_Odm); - - -} -#endif - -VOID -PHY_LCCalibrate_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ -#if 0 - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte timeout = 2000, timecount = 0; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif//(MP_DRIVER == 1) -#endif - - - - -#if MP_DRIVER == 1 - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif - - -#ifdef DISABLE_BB_RF - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) - if(bSingleTone || bCarrierSuppression) - return; - - while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) - { - ODM_delay_ms(50); - timecount += 50; - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_2T2R(pHalData->VersionID)) - { - phy_LCCalibrate_8812A(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_LCCalibrate_8812A(pAdapter, FALSE); -#else - phy_LCCalibrate_8812A(pDM_Odm, FALSE); -#endif - } - - pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); -#endif -} - -VOID - PHY_APCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if defined(FOR_BRAZIL_PRETEST) && (FOR_BRAZIL_PRETEST != 1) - if(pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8812A(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8812A(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8812A(pDM_Odm, delta, FALSE); -#endif - } -} - VOID phy_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(!pAdapter->bHWInitReady) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pAdapter->hw_init_completed == _FALSE) -#endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - -#endif - - if(is2T) //92C - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else //88C - { - - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux - } -} - VOID PHY_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#ifdef DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8812A(pAdapter, bMain, FALSE); -#else - phy_SetRFPathSwitch_8812A(pDM_Odm, bMain, FALSE); -#endif - } -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID - phy_DigitalPredistortion_8812A( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8812A()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8812A for %s %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8812A()\n")); -#endif -} - -VOID - phy_DigitalPredistortion_8812A_8812A( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - - return; - - if(pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_DigitalPredistortion_8812A(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion_8812A(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - - BOOLEAN phy_QueryRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - if(!pAdapter->bHWInitReady) - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) // - { - if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return TRUE; - else - return FALSE; - } - else - { - if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x0) || - (ODM_GetBBReg(pDM_Odm, rConfig_ram64x16, BIT31) == 0x0)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux - BOOLEAN PHY_QueryRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#ifdef DISABLE_BB_RF - return TRUE; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - //if(IS_92C_SERIAL( pHalData->VersionID)){ - if(IS_2T2R( pHalData->VersionID)){ - return phy_QueryRFPathSwitch_8812A(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8812A(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8812A(pDM_Odm, FALSE); -#endif - } -} -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8812A 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +#if 0 + + + + //new element A = element D x X + + //new element C = element D x Y + + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8812A(Adapter, FALSE); + + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr8812A( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + if (Method == TXAGC) + { + u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT]; + u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; + u1Byte rf = 0; + u4Byte pwr = 0, TxAGC = 0; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE )) + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pDM_Odm->BbSwingIdxOfdm[RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase); + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + RTPRINT(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + + } + else if (Method == BBSWING) + { + // Adjust BB swing by OFDM IQ matrix + if (RFPath == RF_PATH_A) + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, bMaskDWord, pDM_Odm->BbSwingIdxOfdm[RF_PATH_A]); + else if (RFPath == RF_PATH_B) + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, bMaskDWord, pDM_Odm->BbSwingIdxOfdm[RF_PATH_B]); + } + else + { + return; + } +} // odm_TxPwrTrackSetPwr88E + +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; + pConfig->RfPathCount = 2; + pConfig->ThermalRegAddr = RF_T_METER_8812A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; + pConfig->DoIQK = DoIQK_8812A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; +} + +#endif + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK + phy_PathA_IQK_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + //1 Tx IQK + //path-A IQK setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); + //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); + ODM_delay_ms(IQK_DELAY_TIME_8812A); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + +#if 0 + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); +#endif + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK + phy_PathA_RxIQK_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB + ) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); + //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); + ODM_delay_ms(IQK_DELAY_TIME_8812A); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8812A)); + //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); + ODM_delay_ms(IQK_DELAY_TIME_8812A); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); + regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); + regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + +#if 0 + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK + phy_PathB_IQK_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_8812A)); + //PlatformStallExecution(IQK_DELAY_TIME_8812A*1000); + ODM_delay_ms(IQK_DELAY_TIME_8812A); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC)); + regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4)); + regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID + _PHY_PathAFillIQKMatrix_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", (u4Byte)Y, (u4Byte)TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix_8812A only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if( RTL_ABS(reg ,0x100) >= 16) + reg = 0x100; +#endif + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID + _PHY_PathBFillIQKMatrix_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", (u4Byte)Y, (u4Byte)TX1_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if 0 //!(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID + _PHY_SaveADDARegisters_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID + _PHY_SaveMACRegisters_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID + _PHY_ReloadADDARegisters_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID + _PHY_ReloadMACRegisters_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID + _PHY_PathADDAOn_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; + if(FALSE == is2T){ + pathOn = 0x0bdb25a0; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + } + else{ + ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn); + } + + for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ + ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn); + } + +} + +VOID + _PHY_MACSettingCalibration_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +VOID + _PHY_PathAStandBy_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x0); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +VOID + _PHY_PIModeSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode + ) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN + phy_SimularityCompare_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +#else + BOOLEAN is2T = 0; +#endif + + if(is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8812A c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8812A differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, (u4Byte)result[c1][i], (u4Byte)result[c2][i])); + + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1< Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xe90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} +void _IQK_BackupRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + RFB_backup[i] = ODM_GetRFReg(pDM_Odm, RF_PATH_B, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} +void _IQK_BackupAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} +void _IQK_RestoreMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} +void _IQK_RestoreRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + case ODM_RF_PATH_B: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); + } + break; + default: + break; + } +} +void _IQK_RestoreAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + + +void _IQK_ConfigureMAC_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_SetBBReg(pDM_Odm, 0x808, BIT(28), 0x0); // CCK Off + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off +} + +#define cal_num 3 + +void _IQK_Tx_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte chnlIdx + ) +{ + u4Byte TX_fail,RX_fail, delay_count, IQK_ready, cal_retry, cal = 0, temp_reg65; + int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0; + int TX_X0[cal_num], TX_Y0[cal_num], RX_X0[cal_num], RX_Y0[cal_num]; + BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; + int TX_X1[cal_num], TX_Y1[cal_num], RX_X1[cal_num], RX_Y1[cal_num]; + BOOLEAN TX1IQKOK = FALSE, RX1IQKOK = FALSE, VDF_enable = FALSE; + int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], Rx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + prtl8192cd_priv priv = pDM_Odm->priv; + + pDM_Odm->priv->pshare->IQK_total_cnt++; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d ExtPA = %d pBand = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA, *pDM_Odm->pBandType)); + if (*pDM_Odm->pBandWidth == 2){ + VDF_enable = TRUE; + } + temp_reg65 = ODM_GetRFReg(pDM_Odm, Path, 0x65, bMaskDWord); + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + // Port 1 DAC/ADC off + ODM_Write4Byte(pDM_Odm, 0xe60, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x00000000); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + + // IQK Setting + //====== TX IQK ====== + // 1. DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT(30), 0x1); + //ODM_SetBBReg(pDM_Odm, 0xcb0, 0x000000f0, 0x7); + ODM_SetBBReg(pDM_Odm, 0xcb0, 0x00ff0000, 0x77); + ODM_SetBBReg(pDM_Odm, 0xcb4, 0x03000000, 0x0); + } + break; + case ODM_RF_PATH_B: + {ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // Port 0 DAC/ADC off + ODM_Write4Byte(pDM_Odm, 0xc60, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x00000000); + + // Port 1 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off + + // DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT(30), 0x1); + //ODM_SetBBReg(pDM_Odm, 0xeb0, 0x000000f0, 0x7); + ODM_SetBBReg(pDM_Odm, 0xeb0, 0x00ff0000, 0x77); + ODM_SetBBReg(pDM_Odm, 0xeb4, 0x03000000, 0x0); + } + break; + default: + break; + } + while (cal < cal_num){ + switch (Path) { + case ODM_RF_PATH_A: + { + //====== TX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + + if (VDF_enable == 1){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXVDF Start\n")); + for (k = 0;k <= 2; k++){ + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 1: + { + ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Tx_dt = %d\n", Tx_dt[cal])); + Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); + Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); + } + break; + default: + break; + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((IQK_ready) || (delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_VDF_cal_retry = %d\n", cal_retry)); + TX_X0[cal] = VDF_X[k-1] ; + TX_Y0[cal] = VDF_Y[k-1]; + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + cal_retry = 0; + while(1){ + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 25ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((IQK_ready) || (delay_count>20)) { + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + /* + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + break; + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal_retry)); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (TX0IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + + if (VDF_enable == 1){ + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); // TX VDF Disable + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXVDF Start\n")); + + //====== RX mode TXK (RXK Step 1) ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161420); + + for (k = 0;k <= 2; k++){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (VDF_X[k])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (VDF_Y[k])>>21&0x000007ff); + + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(30), 0x0); + } + break; + case 1: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x28008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x08008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Rx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Rx_dt = %d\n", Rx_dt[cal])); + Rx_dt[cal] = ((16*Rx_dt[cal])*10000/13823); + Rx_dt[cal] = (Rx_dt[cal] >> 1 )+(Rx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, 0x00003fff, Rx_dt[cal] & 0x00003fff); + } + break; + default: + break; + } + + + if (k==2){ + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(30), 0x1); //RX VDF Enable + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_VDF_cal_retry = %d\n", cal_retry)); + RX_X0[cal] = VDF_X[k-1] ; + RX_Y0[cal] = VDF_Y[k-1]; + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); // TX VDF Enable + } + else{ + //====== RX mode TXK (RXK Step 1) ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // 1. TX RF Setting + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161cc0); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; +/* + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); +*/ + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal_retry)); + } + if (TX0IQKOK) + TX_Average++; + if (RX0IQKOK) + RX_Average++; + } + break; + case ODM_RF_PATH_B: + { + //Path-B TX/RX IQK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); + ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + + + if (pDM_Odm->ExtPA) + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); + else + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); + + if (VDF_enable == 1){ + for (k = 0;k <= 2; k++){ + switch (k){ + case 0: + { + // one shot + ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910); + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); + } + break; + case 1: + { + ODM_SetBBReg(pDM_Odm, 0xe80, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe84, BIT(28), 0x0); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910); + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Tx_dt = %d\n", Tx_dt[cal])); + Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); + Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xee8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); + } + break; + default: + break; + } + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK_ready) || (delay_count>20)) { + break; + } + else { + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + TX1IQKOK = TRUE; + break; + } + else{ + TX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + else{ + TX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_VDF_cal_retry = %d\n", cal_retry)); + TX_X1[cal] = VDF_X[k-1] ; + TX_Y1[cal] = VDF_Y[k-1]; + } + else{ + ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 25ms + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + TX_X1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + TX_Y1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + TX1IQKOK = TRUE; + /* + int reg1 = 0, reg2 = 0, Image_Power = 0; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + break; + } + else{ + TX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + else { + TX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal_retry)); + } + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (TX1IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + + + if (VDF_enable == 1){ + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x0); // TX VDF Disable + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXVDF Start\n")); + + //====== RX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xe88, 0x02140119); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161420); + + for (k = 0;k <= 2; k++){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (VDF_X[k])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (VDF_Y[k])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x0); + } + break; + case 1: + { + ODM_Write4Byte(pDM_Odm, 0xe80, 0x28008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x08008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x0); + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Rx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Rx_dt = %d\n", Rx_dt[cal])); + Rx_dt[cal] = ((16*Rx_dt[cal])*10000/13823); + Rx_dt[cal] = (Rx_dt[cal] >> 1 )+(Rx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xee8, 0x00003fff, Rx_dt[cal] & 0x00003fff); + } + break; + default: + break; + } + + + if (k==2){ + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(30), 0x1); //RX VDF Enable + } + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨?Â¥??v¤?µ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); + if (RX_fail == 0){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + RX1IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0x0>>1); + RX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_VDF_cal_retry = %d\n", cal_retry)); + RX_X1[cal] = VDF_X[k-1] ; + RX_Y1[cal] = VDF_Y[k-1]; + ODM_SetBBReg(pDM_Odm, 0xee8, BIT(31), 0x1); // TX VDF Enable + } + else{ + //====== RX mode TXK (RXK Step 1) ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d0); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X1[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y1[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c15);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c15);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xe88, 0x02140119); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161cc0); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ???SI/PI 使用æ¬?????iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); + if (RX_fail == 0){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + RX_X1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + RX_Y1[cal] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + RX1IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0x0>>1); + RX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + else{ + RX1IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal_retry)); + } + + + if (RX1IQKOK) + RX_Average++; + + + if (TX1IQKOK) + TX_Average++; + + } + break; + default: + break; + } + cal++; + } + // FillIQK Result + switch (Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + if (TX_Average == 0){ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + break; + } + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X0[ii]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); + if (dy < 4 && dy > -4){ + TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; + TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; + if (*pDM_Odm->pBandWidth == 2){ + Tx_dt[0] = (Tx_dt[i] + Tx_dt[ii])/2; + } + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[0] & 0x00003fff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + if (TX_finish == 1){ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + } + if (RX_Average == 0){ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + break; + } + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, (RX_X0[i])>>21&0x000007ff, i, (RX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[i]>>21) - (RX_Y0[ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X0[i]>>21) + (RX_X0[ii]>>21))/2; + RX_Y = ((RX_Y0[i]>>21) + (RX_Y0[ii]>>21))/2; + if (*pDM_Odm->pBandWidth == 2){ + Rx_dt[0] = (Rx_dt[i] + Rx_dt[ii])/2; + } + RX_finish = 1; + break; + } + } + } + if (RX_finish == 1) + break; + } + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xce8, 0x00003fff, Rx_dt[0] & 0x00003fff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + if (RX_finish == 1){ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + } + if (TX_finish && RX_finish){ + pRFCalibrateInfo->bNeedIQK = FALSE; + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0] = ((TX_X & 0x000007ff) << 16) + (TX_Y & 0x000007ff); //Path A TX + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1] = ((RX_X & 0x000007ff) << 16) + (RX_Y & 0x000007ff); //Path A RX + + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4] = ODM_Read4Byte( pDM_Odm, 0xce8); //Path B VDF + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + } + + } + break; + case ODM_RF_PATH_B: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); + if (TX_Average == 0){ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + break; + } + + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", i, (TX_X1[i])>>21&0x000007ff, i, (TX_Y1[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X1[ii]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_Y1[i]>>21) - (TX_Y1[ii]>>21); + if (dy < 4 && dy > -4){ + TX_X = ((TX_X1[i]>>21) + (TX_X1[ii]>>21))/2; + TX_Y = ((TX_Y1[i]>>21) + (TX_Y1[ii]>>21))/2; + if (*pDM_Odm->pBandWidth == 2){ + Tx_dt[0] = (Tx_dt[i] + Tx_dt[ii])/2; + } + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xee8, 0x3fff0000, Tx_dt[0] & 0x00003fff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + if (TX_finish == 1){ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + } + if (RX_Average == 0){ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + break; + } + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", i, (RX_X1[i])>>21&0x000007ff, i, (RX_Y1[i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X1[ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y1[i]>>21) - (RX_Y1[ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X1[i]>>21) + (RX_X1[ii]>>21))/2; + RX_Y = ((RX_Y1[i]>>21) + (RX_Y1[ii]>>21))/2; + if (*pDM_Odm->pBandWidth == 2){ + Rx_dt[0] = (Rx_dt[i] + Rx_dt[ii])/2; + } + RX_finish = 1; + break; + } + } + } + if (RX_finish == 1) + break; + } + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xee8, 0x00003fff, Rx_dt[0] & 0x00003fff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + if (RX_finish == 1){ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, Path, 0x200, 0x0); + } + if (TX_finish && RX_finish){ + pRFCalibrateInfo->bNeedIQK = FALSE; + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2] = ((TX_X & 0x000007ff) << 16) + (TX_Y & 0x000007ff); //Path B TX + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3] = ((RX_X & 0x000007ff) << 16) + (RX_Y & 0x000007ff); //Path B RX + + if (*pDM_Odm->pBandWidth == 2){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 0 --> Page C + pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5] = ODM_Read4Byte( pDM_Odm, 0xee8); //Path B VDF + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + } + } + + } + break; + default: + break; + } + + if (!TX_finish && !RX_finish) + priv->pshare->IQK_fail_cnt++; +} + +#define MACBB_REG_NUM 10 +#define AFE_REG_NUM 14 +#define RF_REG_NUM 3 +/* +IQK v1.0 update TXIQK high power parameter +*/ +VOID +phy_IQCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0x838, 0x90c, 0xb00, 0xc00, 0xe00, 0x8c4, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb8, 0xcb0, 0xcb4, + 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb8, 0xeb0, 0xeb4}; + u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; + u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); + + _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); + + _IQK_ConfigureMAC_8812A(pDM_Odm); + _IQK_Tx_8812A(pDM_Odm, ODM_RF_PATH_A, chnlIdx); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); + + _IQK_Tx_8812A(pDM_Odm, ODM_RF_PATH_B, chnlIdx); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); + + _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + + //_IQK_Exit_8812A(pDM_Odm); + //_IQK_TX_CheckResult_8812A + +} + + +VOID + phy_LCCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + //Check continuous TX and Packet TX + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); +#else + RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits); +#endif + + //2. Set RF mode = standby mode + //Path-A + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); +#else + LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits); +#endif + + //4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + ODM_delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID + phy_APCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a + // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if defined(MP_DRIVER) && (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8812A() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + + // Temporarily do not allow normal driver to do the following settings because these offset + // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal + // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the + // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if !defined(MP_DRIVER) || (MP_DRIVER != 1) + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_8812A(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters_8812A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters_8812A(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters_8812A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_8812A(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration_8812A(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, (int)delta_V, (int)delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + if(path == RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8812A() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_8812A(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters_8812A(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_8812A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters_8812A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); + if(path == RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8812A()\n")); +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + +#if 0 //FOR_8812_IQK +VOID +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#endif +#if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif +#endif//(MP_DRIVER == 1) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + +#if MP_DRIVER == 1 + if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) +#endif + phy_IQCalibrate_8812A(pDM_Odm); + + +} +#endif + +VOID +PHY_LCCalibrate_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ +#if 0 + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif//(MP_DRIVER == 1) +#endif + + + + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#ifdef DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if(bSingleTone || bCarrierSuppression) + return; + + while(*(pDM_Odm->pbScanInProcess) && timecount < timeout) + { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_2T2R(pHalData->VersionID)) + { + phy_LCCalibrate_8812A(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_LCCalibrate_8812A(pAdapter, FALSE); +#else + phy_LCCalibrate_8812A(pDM_Odm, FALSE); +#endif + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); +#endif +} + +VOID + PHY_APCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if defined(FOR_BRAZIL_PRETEST) && (FOR_BRAZIL_PRETEST != 1) + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8812A(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8812A(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8812A(pDM_Odm, delta, FALSE); +#endif + } +} + VOID phy_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(!pAdapter->bHWInitReady) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pAdapter->hw_init_completed == _FALSE) +#endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux + } +} + VOID PHY_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#ifdef DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8812A(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8812A(pDM_Odm, bMain, FALSE); +#endif + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID + phy_DigitalPredistortion_8812A( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8812A()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8812A for %s %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8812A()\n")); +#endif +} + +VOID + phy_DigitalPredistortion_8812A_8812A( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_DigitalPredistortion_8812A(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion_8812A(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + + BOOLEAN phy_QueryRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x0) || + (ODM_GetBBReg(pDM_Odm, rConfig_ram64x16, BIT31) == 0x0)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux + BOOLEAN PHY_QueryRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#ifdef DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + //if(IS_92C_SERIAL( pHalData->VersionID)){ + if(IS_2T2R( pHalData->VersionID)){ + return phy_QueryRFPathSwitch_8812A(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8812A(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8812A(pDM_Odm, FALSE); +#endif + } +} +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.h index dcbc9274a88..b25021d8fa8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ap.h @@ -1,153 +1,153 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8812A_H__ -#define __HAL_PHY_RF_8812A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8812A 10 //ms -#define index_mapping_NUM_8812A 15 -#define AVG_THERMAL_NUM_8812A 4 -#define RF_T_METER_8812A 0x42 - - -#if 0 -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ); - - - - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr8812A( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -#endif - - -//1 7. IQK - -#if 0 - -void -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery -); - -#else - - -VOID -phy_IQCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel -); - -#endif - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8812A( - IN PDM_ODM_T pDM_Odm -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); - - -#if 0 //FOR_8812_IQK -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ); - -#endif - - -#endif // #ifndef __HAL_PHY_RF_8812A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8812A_H__ +#define __HAL_PHY_RF_8812A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8812A 10 //ms +#define index_mapping_NUM_8812A 15 +#define AVG_THERMAL_NUM_8812A 4 +#define RF_T_METER_8812A 0x42 + + +#if 0 +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ); + + + + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr8812A( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +#endif + + +//1 7. IQK + +#if 0 + +void +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery +); + +#else + + +VOID +phy_IQCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel +); + +#endif + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8812A( + IN PDM_ODM_T pDM_Odm +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); + + +#if 0 //FOR_8812_IQK +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + +#endif + + +#endif // #ifndef __HAL_PHY_RF_8812A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.c index 1555b69dd7a..a4ce09c9bfc 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.c @@ -1,2200 +1,2200 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8812A 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8812A(Adapter, FALSE); -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr8812A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - u4Byte finalBbSwingIdx[2]; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte PwrTrackingLimit = 26; //+1.0dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); - - if(TxRate != 0xFF) //20130429 Mimic Modify High Rate BBSwing Limit. - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit = 32; //+4dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit = 30; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit = 28; //+2dB - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit = 28; //+2dB - - else if((TxRate >= MGN_MCS8)&&(TxRate <= MGN_MCS10)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS11)&&(TxRate <= MGN_MCS12)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS13)&&(TxRate <= MGN_MCS15)) //64QAM - PwrTrackingLimit = 28; //+2dB - - //2 VHT - else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT1SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT1SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT1SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else if((TxRate >= MGN_VHT2SS_MCS0)&&(TxRate <= MGN_VHT2SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT2SS_MCS3)&&(TxRate <= MGN_VHT2SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT2SS_MCS5)&&(TxRate <= MGN_VHT2SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT2SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT2SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT2SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else - PwrTrackingLimit = 24; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); - - - if (Method == BBSWING) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); - - if (RFPath == ODM_RF_PATH_A) - { - finalBbSwingIdx[ODM_RF_PATH_A] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", - pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); - } - else - { - finalBbSwingIdx[ODM_RF_PATH_B] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n", - pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B], finalBbSwingIdx[ODM_RF_PATH_B])); - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_B]]); - } - } - - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) - { - if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit; /*CCK Follow the same compensate value as Path A*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index <= 0) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; /*CCK Follow the same compensate value as Path A*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - } - - if (RFPath == ODM_RF_PATH_B) - { - if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index <= 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - } - - } - else - { - return; - } -} - -VOID -GetDeltaSwingTable_8812A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; - pConfig->RfPathCount = MAX_PATH_NUM_8812A; - pConfig->ThermalRegAddr = RF_T_METER_8812A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; - pConfig->DoIQK = DoIQK_8812A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8812A; -} - - -#define BW_20M 0 -#define BW_40M 1 -#define BW_80M 2 - -void _IQK_RX_FillIQC_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - } - else{ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); - } - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} -void _IQK_BackupRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - RFB_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} -void _IQK_BackupAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} -void _IQK_RestoreMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} -void _IQK_RestoreRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - case ODM_RF_PATH_B: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); - } - break; - default: - break; - } -} -void _IQK_RestoreAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); - //ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); - //ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - - -void _IQK_ConfigureMAC_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -#define cal_num 10 - -void _IQK_Tx_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte chnlIdx - ) -{ - u1Byte delay_count, cal = 0; - u1Byte cal0_retry, cal1_retry, TX0_Average = 0, TX1_Average = 0, RX0_Average = 0, RX1_Average = 0; - int TX_IQC_temp[10][4], TX_IQC[4]={}; //TX_IQC = [TX0_X, TX0_Y,TX1_X,TX1_Y]; for 3 times - int RX_IQC_temp[10][4], RX_IQC[4]={}; //RX_IQC = [RX0_X, RX0_Y,RX1_X,RX1_Y]; for 3 times - BOOLEAN TX0_fail = TRUE, RX0_fail = TRUE, IQK0_ready = FALSE, TX0_finish = FALSE, RX0_finish = FALSE; - BOOLEAN TX1_fail = TRUE, RX1_fail = TRUE, IQK1_ready = FALSE, TX1_finish = FALSE, RX1_finish = FALSE, VDF_enable = FALSE; - int i, ii, dx = 0, dy = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA5G = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA5G, pDM_Odm->ExtPA)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, RFE_Type = %d\n", pDM_Odm->SupportInterface, pDM_Odm->RFEType)); - if (*pDM_Odm->pBandWidth == 2){ - VDF_enable = TRUE; - } - VDF_enable = FALSE; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - // Port 1 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off - - // DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - //====== Path A TX IQK RF Setting ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); - //====== Path B TX IQK RF Setting ====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G){ - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f7); - } - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); - } - if (*pDM_Odm->pBandType){ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); - if (pDM_Odm->RFEType == 3){ - if (pDM_Odm->ExtPA) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - } - } - - if (VDF_enable){} - else{ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); - - cal0_retry = 0; - cal1_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - if (!TX0_finish) - IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if (!TX1_finish) - IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK0_ready && IQK1_ready) || (delay_count>20)) - break; - else{ - ODM_delay_ms(1); - delay_count++; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX delay_count = %d\n", delay_count)); - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - TX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); - if (!(TX0_fail || TX0_finish)){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_IQC_temp[TX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_IQC_temp[TX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", TX0_Average, (TX_IQC_temp[TX0_Average][0])>>21&0x000007ff, TX0_Average, (TX_IQC_temp[TX0_Average][1])>>21&0x000007ff)); - /* - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - TX0_Average++; - } - else{ - cal0_retry++; - if (cal0_retry == 10) - break; - } - if (!(TX1_fail || TX1_finish)){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - TX_IQC_temp[TX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - TX_IQC_temp[TX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", TX1_Average, (TX_IQC_temp[TX1_Average][2])>>21&0x000007ff, TX1_Average, (TX_IQC_temp[TX1_Average][3])>>21&0x000007ff)); - /* - int reg1 = 0, reg2 = 0, Image_Power = 0; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - TX1_Average++; - } - else{ - cal1_retry++; - if (cal1_retry == 10) - break; - } - } - else{ - cal0_retry++; - cal1_retry++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms TX IQK Not Ready!!!!!\n")); - if (cal0_retry == 10) - break; - } - if (TX0_Average >= 2){ - for (i = 0; i < TX0_Average; i++){ - for (ii = i+1; ii >21) - (TX_IQC_temp[ii][0]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_IQC_temp[i][1]>>21) - (TX_IQC_temp[ii][1]>>21); - if (dy < 4 && dy > -4){ - TX_IQC[0] = ((TX_IQC_temp[i][0]>>21) + (TX_IQC_temp[ii][0]>>21))/2; - TX_IQC[1] = ((TX_IQC_temp[i][1]>>21) + (TX_IQC_temp[ii][1]>>21))/2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_X = %x;;TXA_Y = %x\n", TX_IQC[0]&0x000007ff, TX_IQC[1]&0x000007ff)); - TX0_finish = TRUE; - } - } - } - } - } - if (TX1_Average >= 2){ - for (i = 0; i < TX1_Average; i++){ - for (ii = i+1; ii >21) - (TX_IQC_temp[ii][2]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_IQC_temp[i][3]>>21) - (TX_IQC_temp[ii][3]>>21); - if (dy < 4 && dy > -4){ - TX_IQC[2] = ((TX_IQC_temp[i][2]>>21) + (TX_IQC_temp[ii][2]>>21))/2; - TX_IQC[3] = ((TX_IQC_temp[i][3]>>21) + (TX_IQC_temp[ii][3]>>21))/2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_X = %x;;TXB_Y = %x\n", TX_IQC[2]&0x000007ff, TX_IQC[3]&0x000007ff)); - TX1_finish = TRUE; - } - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_Average = %d, TX1_Average = %d\n", TX0_Average, TX1_Average)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_finish = %d, TX1_finish = %d\n", TX0_finish, TX1_finish)); - if (TX0_finish && TX1_finish) - break; - if ((cal0_retry + TX0_Average) >= 10 || (cal1_retry + TX1_Average) >= 10 ) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal0_retry)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal1_retry)); - - } - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, 0xffc00)); // Load LOK - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, 0xffc00)); // Load LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (VDF_enable == 1){} - else{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (TX0_finish){ - //====== Path A RX IQK RF Setting====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - } - if (TX1_finish){ - //====== Path B RX IQK RF Setting====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x00000); - } - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - else - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); - //ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00000077); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00000077); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x02000077); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x02000077); - } - - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (TX0_finish){ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x82140119); - } - if (TX1_finish){ - ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xe88, 0x82140119); - } - cal0_retry = 0; - cal1_retry = 0; - while(1){ - // one shot - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (TX0_finish){ - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[0])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[1])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161500); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160cc0); - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000); - ODM_delay_ms(5); //Delay 5ms - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - } - if (TX1_finish){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[2])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[3])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161500); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28160ca0); - } - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_delay_ms(5); //Delay 5ms - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - } - delay_count = 0; - while (1){ - if (!RX0_finish && TX0_finish) - IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if (!RX1_finish && TX1_finish) - IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK0_ready && IQK1_ready)||(delay_count>20)) - break; - else{ - ODM_delay_ms(1); - delay_count++; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX delay_count = %d\n", delay_count)); - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - RX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); - if (!(RX0_fail || RX0_finish) && TX0_finish){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_IQC_temp[RX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_IQC_temp[RX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", RX0_Average, (RX_IQC_temp[RX0_Average][0])>>21&0x000007ff, RX0_Average, (RX_IQC_temp[RX0_Average][1])>>21&0x000007ff)); -/* - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); -*/ - RX0_Average++; - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("1. RXA_cal_retry = %d\n", cal0_retry)); - cal0_retry++; - if (cal0_retry == 10) - break; - } - if (!(RX1_fail || RX1_finish) && TX1_finish){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - RX_IQC_temp[RX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - RX_IQC_temp[RX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", RX1_Average, (RX_IQC_temp[RX1_Average][2])>>21&0x000007ff, RX1_Average, (RX_IQC_temp[RX1_Average][3])>>21&0x000007ff)); -/* - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); -*/ - RX1_Average++; - } - else{ - cal1_retry++; - if (cal1_retry == 10) - break; - } - - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("2. RXA_cal_retry = %d\n", cal0_retry)); - cal0_retry++; - cal1_retry++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms RX IQK Not Ready!!!!!\n")); - if (cal0_retry == 10) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("3. RXA_cal_retry = %d\n", cal0_retry)); - if (RX0_Average >= 2){ - for (i = 0; i < RX0_Average; i++){ - for (ii = i+1; ii >21) - (RX_IQC_temp[ii][0]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_IQC_temp[i][1]>>21) - (RX_IQC_temp[ii][1]>>21); - if (dy < 4 && dy > -4){ - RX_IQC[0]= ((RX_IQC_temp[i][0]>>21) + (RX_IQC_temp[ii][0]>>21))/2; - RX_IQC[1] = ((RX_IQC_temp[i][1]>>21) + (RX_IQC_temp[ii][1]>>21))/2; - RX0_finish = TRUE; - break; - } - } - } - } - } - if (RX1_Average >= 2){ - for (i = 0; i < RX1_Average; i++){ - for (ii = i+1; ii >21) - (RX_IQC_temp[ii][2]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_IQC_temp[i][3]>>21) - (RX_IQC_temp[ii][3]>>21); - if (dy < 4 && dy > -4){ - RX_IQC[2] = ((RX_IQC_temp[i][2]>>21) + (RX_IQC_temp[ii][2]>>21))/2; - RX_IQC[3] = ((RX_IQC_temp[i][3]>>21) + (RX_IQC_temp[ii][3]>>21))/2; - RX1_finish = TRUE; - break; - } - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_Average = %d, RX1_Average = %d\n", RX0_Average, RX1_Average)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_finish = %d, RX1_finish = %d\n", RX0_finish, RX1_finish)); - if ((RX0_finish|| !TX0_finish) && (RX1_finish || !TX1_finish) ) - break; - if ((cal0_retry + RX0_Average) >= 10 || (cal1_retry + RX1_Average) >= 10 || RX0_Average == 3 || RX1_Average == 3) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal0_retry)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal1_retry)); - } - - // FillIQK Result - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - - if (TX0_finish){ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, TX_IQC[0], TX_IQC[1]); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); - } - - - - if (RX0_finish){ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, RX_IQC[0], RX_IQC[1]); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); - - if (TX1_finish){ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, TX_IQC[2], TX_IQC[3]); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); - } - - - - if (RX1_finish){ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, RX_IQC[2], RX_IQC[3]); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); - } - - - -} - -#define MACBB_REG_NUM 9 -#define AFE_REG_NUM 12 -#define RF_REG_NUM 3 - -// Maintained by BB James. -VOID -phy_IQCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM] = {0}, RFA_backup[RF_REG_NUM] = {0}, RFB_backup[RF_REG_NUM] = {0}; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0xe00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb0, 0xcb4, - 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb0, 0xeb4}; - u4Byte Reg_C1B8, Reg_E1B8; - u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; - u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); - - _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - Reg_C1B8 = ODM_Read4Byte(pDM_Odm, 0xcb8); - Reg_E1B8 = ODM_Read4Byte(pDM_Odm, 0xeb8); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); - - _IQK_ConfigureMAC_8812A(pDM_Odm); - _IQK_Tx_8812A(pDM_Odm, chnlIdx); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); - - _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_Write4Byte(pDM_Odm, 0xcb8, Reg_C1B8); - ODM_Write4Byte(pDM_Odm, 0xeb8, Reg_E1B8); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - - -} - -VOID -phy_LCCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; - - //Check continuous TX and Packet TX - u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; - - // Backup RF reg18. - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - if((reg0x914 & 0x70000) != 0) //If contTx, disable all continuous TX. 0x914[18:16] - // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx - // until another packet comes in. To avoid ContTx being turned off, we skip this step. - ;//ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914 & (~0x70000)); - else // If packet Tx-ing, pause Tx. - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); - - -/* - //3 1. Read original RF mode - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask); - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask); - - - //3 2. Set RF mode = standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, (RF_Amode&0x8FFFF)|0x10000); - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, (RF_Bmode&0x8FFFF)|0x10000); -*/ - - // Enter LCK mode - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp | BIT14); - - //3 3. Read RF reg18 - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - //3 4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); - - ODM_delay_ms(150); // suggest by RFSI Binson - - // Leave LCK mode - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp & ~BIT14); - - - - //3 Restore original situation - if((reg0x914 & 70000) != 0) //Deal with contisuous TX case, 0x914[18:16] - { - // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx - // until another packet comes in. To avoid ContTx being turned off, we skip this step. - //ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - } - - // Recover channel number - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - /* - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, RF_Amode); - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, RF_Bmode); - */ - -} - - - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - -VOID -phy_ReloadIQKSetting_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff0000)>>16); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff0000)>>16); - - if (*pDM_Odm->pBandWidth != 2){ - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xce8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4]); - ODM_Write4Byte(pDM_Odm, 0xee8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff0000)>>17); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff)>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff0000)>>17); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff)>>1); - - -} - -VOID -PHY_ResetIQKResult_8812A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); -} - -VOID -phy_IQCalibrate_By_FW_8812A( - IN PADAPTER pAdapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - u1Byte IQKcmd[3] = {pHalData->CurrentChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(pHalData->CurrentBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) - Buf2 = 0x1; - else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) - Buf2 = 0x1<<1; - else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pHalData->ExternalPA_5G | pHalData->ExternalLNA_5G<<1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== IQK Start ==\n")); - - FillH2CCmd_8812(pAdapter, 0x45, 3, IQKcmd); - - rtl8812_iqk_wait(pAdapter, 500); -} - -VOID -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - u4Byte counter = 0; - u4Byte StartTime; - s4Byte ProgressingTime; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - -#if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif -#endif//(MP_DRIVER == 1) - -//#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - //if (ODM_CheckPowerStatus(pAdapter) == FALSE) - //return; -//#endif - pDM_Odm->IQKFWOffload = 0; - StartTime = ODM_GetCurrentTime( pDM_Odm); - -#if MP_DRIVER == 1 - if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) -#endif - { - - if(pDM_Odm->IQKFWOffload) - { - phy_IQCalibrate_By_FW_8812A(pAdapter); - } - else - { - phy_IQCalibrate_8812A(pDM_Odm, pHalData->CurrentChannel); - } - } - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); -} - - -VOID -PHY_LCCalibrate_8812A( - IN PVOID pDM_VOID - ) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte StartTime; - s4Byte ProgressingTime; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; - #endif//(MP_DRIVER == 1) -#endif - - StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8812A\n")); - - phy_LCCalibrate_8812A(pDM_Odm, TRUE); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8812A\n")); - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); - -} - -VOID phy_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - -#endif - - if (IS_HARDWARE_TYPE_8821(pAdapter)) - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x1); //Main - else - ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x2); //Aux - } - else if (IS_HARDWARE_TYPE_8812(pAdapter)) - { - if (pHalData->RFEType == 5) - { - if(bMain) { - //WiFi - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } else { - // BT - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } - } - } - -} - -VOID PHY_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); - -#endif -} - - -VOID -_DPK_ThermalCompensation( - IN PDM_ODM_T pDM_Odm - ) -{ -} - -VOID -_DPK_parareload( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - - - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } -} - - -VOID -_DPK_parabackup( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - - - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } -} - -VOID -_DPK_Globalparaset( - IN PDM_ODM_T pDM_Odm - ) -{ - - //***************************************// - //set MAC register - //***************************************// - - //TX pause - ODM_Write4Byte(pDM_Odm, 0x520, 0x007f3F0F); - - //***************************************// - //set BB register - //***************************************// - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); - - // test pin in/out control - ODM_Write4Byte(pDM_Odm, 0x970, 0x00000000); - - // path A regcb8[3:0] = h'd, TRSW to TX - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0050824d); - - // path B regeb8[3:0] = h'd, TRSW to TX - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0050824d); - - // reg838[3:0] = h'c, CCA off - ODM_Write4Byte(pDM_Odm, 0x838, 0x06c8d24c); - - // path A 3-wire off - ODM_Write4Byte(pDM_Odm, 0xc00, 0x00000004); - - // path B 3-wire off - ODM_Write4Byte(pDM_Odm, 0xe00, 0x00000004); - - // reg90c[15] = b'1, DAC fifo reset by CSWU - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - - // reset DPK circuit - ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); - - // path A regc94[0] = b'1 (r_gothrough_iqkdpk), ±N DPK ¤Á¶i normal path - ODM_Write4Byte(pDM_Odm, 0xc94, 0x01000001); - - // path B rege94[0] = b'1 (r_gothrough_iqkdpk), ±N DPK ¤Á¶i normal path - ODM_Write4Byte(pDM_Odm, 0xe94, 0x01000001); - - //***************************************// - //set AFE register - //***************************************// - - //path A - //regc68 ¨ì regc84À³¸Ó¬O­n¸ò¥¿±` Tx mode ®Éªº³]©w¤@­P - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc6c, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc70, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc74, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc78, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc7c, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x19791979); - - // force DAC/ADC power on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - //path B - //rege68 ¨ì rege84À³¸Ó¬O­n¸ò¥¿±` Tx mode ®Éªº³]©w¤@­P - - ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe6c, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe70, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe74, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe78, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe7c, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe84, 0x19791979); - - // force DAC/ADC power on - ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); - -} - - -VOID -_DPK_GetGainLoss( - IN PDM_ODM_T pDM_Odm, - IN u1Byte path - ) -{ - u4Byte GL_I=0,GL_Q=0; - u4Byte GL_I_tmp=0,GL_Q_tmp=0; - - u4Byte Power_GL; - u2Byte Scaler[]={0x4000, 0x41db, 0x43c7, 0x45c3, 0x47cf, 0x49ec, 0x4c19, 0x4e46, 0x5093,0x52f2, //10 - 0x5560, 0x57cf, 0x5a7f, 0x5d0e, 0x5fbe - }; - u1Byte sindex=0; - u4Byte pagesel = 0,regsel = 0; - - if(path == 0) //pathA - { - pagesel = 0; - regsel = 0; - } - else //pathB - { - pagesel = 0x200; - regsel = 0x40; - } - - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0601f0bf); - ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x0c000000); - - - - GL_I_tmp = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0xffff0000); - GL_Q_tmp = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0x0000ffff); - - if(GL_I_tmp >= 0x8000) - GL_I = (GL_I_tmp-0x8000+0x1); - else - GL_I = GL_I_tmp; - - - if(GL_Q_tmp >= 0x8000) - GL_Q = (GL_Q_tmp-0x8000+0x1); - else - GL_Q = GL_Q_tmp; - - Power_GL = ((GL_I*GL_I)+(GL_Q*GL_Q))/4; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Power_GL = 0x%x", Power_GL)); - - if (Power_GL > 63676){ - sindex = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0 dB\n")); - } - else if (63676 >= Power_GL && Power_GL > 60114){ - sindex = 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.25 dB\n")); - } - else if (60114 >= Power_GL && Power_GL> 56751){ - sindex = 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.5 dB\n")); - } - else if (56751 >= Power_GL && Power_GL> 53577){ - sindex = 3; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.75 dB\n")); - } - else if (53577 >= Power_GL && Power_GL> 49145){ - sindex = 4; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1 dB\n")); - } - else if (49145 >= Power_GL && Power_GL> 47750){ - sindex = 5; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.25 dB\n")); - } - else if (47750 >= Power_GL && Power_GL> 45079){ - sindex = 6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.5 dB\n")); - } - else if (45079 >= Power_GL && Power_GL> 42557){ - sindex = 7; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.75 dB\n")); - } - else if (42557 >= Power_GL && Power_GL> 40177){ - sindex = 8; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2 dB\n")); - } - else if (40177 >= Power_GL && Power_GL> 37929){ - sindex = 9; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.25 dB\n")); - } - else if (37929 >= Power_GL && Power_GL> 35807){ - sindex = 10; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.5 dB\n")); - } - else if (35807 >= Power_GL && Power_GL> 33804){ - sindex = 11; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.75 dB\n")); - } - else if (33804 >= Power_GL && Power_GL> 31913){ - sindex = 12; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3 dB\n")); - } - else if (31913 >= Power_GL && Power_GL> 30128){ - sindex = 13; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3.25 dB\n")); - } - else if (30128 >= Power_GL){ - sindex = 14; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3.5 dB\n")); - } - - - ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, (Scaler[sindex] << 16) | Scaler[sindex]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Set Gainloss reg 0xc98(0xe98)= 0x%x\n",ODM_Read4Byte(pDM_Odm, 0xc98+pagesel))); - -} - - -VOID -_DPK_EnableDP( - IN PDM_ODM_T pDM_Odm, - IN u1Byte path, - IN u4Byte TXindex - ) -{ - - //***************************************// - //Enable DP - //***************************************// - - //PWSF[6] = 0x40 = 0dB, set the address represented TXindex as 0dB - u1Byte PWSF[] = { 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40, //6~0dB - 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, 0x0d, //-1~-7dB - 0x0a, 0x08, 0x06, 0x05, 0x04, 0x03, 0x03, //-8~-14dB - 0x02, 0x02, 0x01, 0x01, - }; - u1Byte zeropoint; - u1Byte pwsf1,pwsf2; - u1Byte i; - u4Byte pagesel = 0,regsel = 0; - - if(path == 0) - { - pagesel = 0; - regsel = 0; - } - else - { - pagesel = 0x200; - regsel = 0x40; - } - - - //=========// - // DPK setting // - //=========// - // reg82c[31] = b'1, ¤Á´«¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); - - - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0000f098); - ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0x776c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x08840000); - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); - - - // ¼gPWSF table in 1st SRAM for PA = 11 use - ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x00000800); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Write PWSF table\n")); - - - if(TXindex == 0x1f) - zeropoint = 0; - else if(TXindex == 0x1e) - zeropoint = 1; - else if(TXindex == 0x1d) - zeropoint = 2; - else if(TXindex == 0x1c) - zeropoint = 3; - else if(TXindex == 0x1b) - zeropoint = 4; - else if(TXindex == 0x1a) - zeropoint = 5; - else if(TXindex == 0x19) - zeropoint = 6; - else - zeropoint = 6; - - - - for(i=0;i<16;i++) - { - pwsf1 = (6-zeropoint)+i*2; - if(pwsf1 > 24) - pwsf1 = 24; - - pwsf2 = (6-zeropoint-1)+i*2; - if(pwsf2 > 24) - pwsf2 = 24; - - ODM_Write4Byte(pDM_Odm, 0xce4+pagesel, 0x00000001 | i<<1 | (PWSF[pwsf1]<<8) | (PWSF[pwsf2]<<16)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x%x\n", ODM_Read4Byte(pDM_Odm, 0xce4+pagesel))); - ODM_SetBBReg(pDM_Odm, 0xce4+pagesel, 0xff, 0x0); - } - - ODM_Write4Byte(pDM_Odm, 0xce4+pagesel, 0x00000000); - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); - -} - - -VOID -_DPK_pathABDPK( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte TXindex = 0; - u1Byte path = 0; - u4Byte pagesel = 0,regsel = 0; - u4Byte i=0,j=0; - - for(path=0;path<2;path ++) //path A = 0; path B = 1; - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK start!!!\n", (path==0)?"A":"B")); - - if(path == 0) - { - pagesel = 0; - regsel = 0; - } - else - { - pagesel = 0x200; - regsel = 0x40; - } - - //***************************************// - //find compress-2.5dB TX index - //***************************************// - - - // reg82c[31] = b'1, ¤Á´«¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); - - // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. - // dB_sel = b'000 ' 1.0 dB PA gain loss - // dB_sel = b'001 ' 1.5 dB PA gain loss - // dB_sel = b'010 ' 2.0 dB PA gain loss - // dB_sel = b'011 ' 2.5 dB PA gain loss - // dB_sel = b'100 ' 3.0 dB PA gain loss - // dB_sel = b'101 ' 3.5 dB PA gain loss - // dB_sel = b'110 ' 4.0 dB PA gain loss - ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x00006000); - - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0401e038); - ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x148b0000); - ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); - - // tx_amp ' ¨M©w Ramp ¤¤¦U©¶ªiªº®¶´T¤j¤p - ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, 0x41382e21); - ODM_Write4Byte(pDM_Odm, 0xc9c+pagesel, 0x5b554f48); - ODM_Write4Byte(pDM_Odm, 0xca0+pagesel, 0x6f6b6661); - ODM_Write4Byte(pDM_Odm, 0xca4+pagesel, 0x817d7874); - ODM_Write4Byte(pDM_Odm, 0xca8+pagesel, 0x908c8884); - ODM_Write4Byte(pDM_Odm, 0xcac+pagesel, 0x9d9a9793); - ODM_Write4Byte(pDM_Odm, 0xcb0+pagesel, 0xaaa7a4a1); - ODM_Write4Byte(pDM_Odm, 0xcb4+pagesel, 0xb6b3b0ad); - - // tx_inverse ' Ramp ¤¤¦U©¶ªipower ªº­Ë¼Æ, ¥H­pºâ¥X PA ªº gain report?? - ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x02ce03e9); - ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x01fd0249); - ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x01a101c9); - ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x016a0181); - ODM_Write4Byte(pDM_Odm, 0xc50+pagesel, 0x01430155); - ODM_Write4Byte(pDM_Odm, 0xc54+pagesel, 0x01270135); - ODM_Write4Byte(pDM_Odm, 0xc58+pagesel, 0x0112011c); - ODM_Write4Byte(pDM_Odm, 0xc5c+pagesel, 0x01000108); - ODM_Write4Byte(pDM_Odm, 0xc60+pagesel, 0x00f100f8); - ODM_Write4Byte(pDM_Odm, 0xc64+pagesel, 0x00e500eb); - ODM_Write4Byte(pDM_Odm, 0xc68+pagesel, 0x00db00e0); - ODM_Write4Byte(pDM_Odm, 0xc6c+pagesel, 0x00d100d5); - ODM_Write4Byte(pDM_Odm, 0xc70+pagesel, 0x00c900cd); - ODM_Write4Byte(pDM_Odm, 0xc74+pagesel, 0x00c200c5); - ODM_Write4Byte(pDM_Odm, 0xc78+pagesel, 0x00bb00be); - ODM_Write4Byte(pDM_Odm, 0xc7c+pagesel, 0x00b500b8); - - //============// - // RF setting for DPK // - //============// - - //pathA,pathB standby mode - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); - - // 00[4:0] = Tx AGC, 00[9:5] = Rx AGC (BB), 00[12:10] = Rx AGC (LNA) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x0, bRFRegOffsetMask, 0x50bff); - - - // 64[14:12] = loop back attenuation - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x64, bRFRegOffsetMask, 0x19aac); - - // 8f[14:13] = PGA2 gain - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x8f, bRFRegOffsetMask, 0x8e001); - - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x000c5599); - - - // delay 100 ms - ODM_delay_ms(100); - - - // read back - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0109f018); - ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x09000000); - // ¥i¥H¦b d00[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w - // Ū¦^d00[3:0] = h'1 ' Tx AGC = 15 - // Ū¦^d00[3:0] = h'2 ' Tx AGC = 16 - // Ū¦^d00[3:0] = h'3 ' Tx AGC = 17 - // Ū¦^d00[3:0] = h'4 ' Tx AGC = 18 - // Ū¦^d00[3:0] = h'5 ' Tx AGC = 19 - // Ū¦^d00[3:0] = h'6 ' Tx AGC = 1a - // Ū¦^d00[3:0] = h'7 ' Tx AGC = 1b - // Ū¦^d00[3:0] = h'8 ' Tx AGC = 1c - // Ū¦^d00[3:0] = h'9 ' Tx AGC = 1d - // Ū¦^d00[3:0] = h'a ' Tx AGC = 1e - // Ū¦^d00[3:0] = h'b ' Tx AGC = 1f - - TXindex = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0x0000000f); - - - //***************************************// - //get LUT - //***************************************// - - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0001e038); - ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x400c5599); - ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x11930080); //0xcc4[9:4]= DPk fail threshold - ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); - - - // tx_amp ' ¨M©w Ramp ¤¤¦U©¶ªiªº®¶´T¤j¤p - - ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, 0x41382e21); - ODM_Write4Byte(pDM_Odm, 0xc9c+pagesel, 0x5b554f48); - ODM_Write4Byte(pDM_Odm, 0xca0+pagesel, 0x6f6b6661); - ODM_Write4Byte(pDM_Odm, 0xca4+pagesel, 0x817d7874); - ODM_Write4Byte(pDM_Odm, 0xca8+pagesel, 0x908c8884); - ODM_Write4Byte(pDM_Odm, 0xcac+pagesel, 0x9d9a9793); - ODM_Write4Byte(pDM_Odm, 0xcb0+pagesel, 0xaaa7a4a1); - ODM_Write4Byte(pDM_Odm, 0xcb4+pagesel, 0xb6b3b0ad); - - // tx_inverse ' Ramp ¤¤¦U©¶ªipower ªº­Ë¼Æ, ¥H­pºâ¥X PA ªº gain - ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x02ce03e9); - ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x01fd0249); - ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x01a101c9); - ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x016a0181); - ODM_Write4Byte(pDM_Odm, 0xc50+pagesel, 0x01430155); - ODM_Write4Byte(pDM_Odm, 0xc54+pagesel, 0x01270135); - ODM_Write4Byte(pDM_Odm, 0xc58+pagesel, 0x0112011c); - ODM_Write4Byte(pDM_Odm, 0xc5c+pagesel, 0x01000108); - ODM_Write4Byte(pDM_Odm, 0xc60+pagesel, 0x00f100f8); - ODM_Write4Byte(pDM_Odm, 0xc64+pagesel, 0x00e500eb); - ODM_Write4Byte(pDM_Odm, 0xc68+pagesel, 0x00db00e0); - ODM_Write4Byte(pDM_Odm, 0xc6c+pagesel, 0x00d100d5); - ODM_Write4Byte(pDM_Odm, 0xc70+pagesel, 0x00c900cd); - ODM_Write4Byte(pDM_Odm, 0xc74+pagesel, 0x00c200c5); - ODM_Write4Byte(pDM_Odm, 0xc78+pagesel, 0x00bb00be); - ODM_Write4Byte(pDM_Odm, 0xc7c+pagesel, 0x00b500b8); - - //fill BB TX index for the DPK reference - // reg82c[31] =1b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); - - ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc24+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc28+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc2c+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc30+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc34+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc38+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc3c+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x3c3c3c3c); - - // reg82c[31] =1b'1, ¤Á´«¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); - - - - // r_agc_boudary - // PA gain = 11 ¹ïÀ³ tx_agc ±q1f ¨ì11 boundary = b'11111 ' PageC1 ªº bc0[4:0] = 11111 - // PA gain = 10 ¹ïÀ³ tx_agc ±q11 ¨ì11 ? boundary = b'10011 ' PageC1 ªº bc0[9:5] = 10001 - // PA gain = 01 ¹ïÀ³ tx_agc ±q10 ¨ì0e ? boundary = b'10000 ' PageC1 ªº bc0[14:10] = 10000 - // PA gain = 00 ¹ïÀ³ tx_agc ±q0d ¨ì00 ? boundary = b'01101 ' PageC1 ªº bc0[19:15] = 01101 - ODM_Write4Byte(pDM_Odm, 0xcbc+pagesel, 0x0006c23f); - - // r_bnd, ¥t¥~4¶ô PWSF (power scaling factor) ªº boundary, ¦]¬°¥Ø«e¥u¦³¦b PA gain = 11 ®É¤~°µ¸ÉÀv, ©Ò¥H³]¦¨ h'fffff §Y¥i. - ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x000fffff); - - //============// - // RF setting for DPK // - //============// - // 00[4:0] = Tx AGC, 00[9:5] = Rx AGC (BB), 00[12:10] = Rx AGC (LNA) - // ¦¹³B reg00[4:0] = h'1d, ¬O¥Ñ«e­± gain loss function ±o¨ìªºµ²ªG. - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x0, bRFRegOffsetMask, 0x517e0 | TXindex); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF 0x0 = 0x%x\n", 0x517e0 | TXindex)); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0xc00c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x400c5599); - - // delay 100 ms - ODM_delay_ms(100); - - // read back dp_fail report - ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x00000000); - - //if d00[6] = 1, DPK fail - if(ODM_GetBBReg(pDM_Odm, 0xd00+regsel, BIT6)) - { - //bypass DPK - ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x28848000); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK fail!!!!!!!!!!!!!!!!!!!!!\n", (path==0)?"A":"B")); - - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK ok!!!!!!!!!!!!!!!!!!!!!\n", (path==0)?"A":"B")); - - - - //read LMS table -->debug message only - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("read LMS\n")); - - for(i=0;i<8;i++){ - ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0601f0b8+i); - for(j=0;j<4;j++){ - ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x09000000+(j<<24)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x%x", ODM_Read4Byte(pDM_Odm, 0xd00+regsel))); - } - } - - - //***************************************// - //get gain loss - //***************************************// - - _DPK_GetGainLoss(pDM_Odm,path); - - - //***************************************// - //Enable DP - //***************************************// - - _DPK_EnableDP(pDM_Odm, path, TXindex); - - -} - - -} - - - -VOID -phy_DPCalibrate_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte backupRegAddrs[] = { - 0x970, 0xcb8, 0x838, 0xc00, 0x90c, 0xb00, 0xc94, 0x82c, 0x520, 0xc60, // 10 - 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc50, // 20 - 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, // 30 - 0xc48, 0xc4c, 0xe50, 0xe20, 0xe24, 0xe28, 0xe2c, 0xe30, 0xe34, 0xe38, // 40 - 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xeb8, 0xe00, 0xe94, 0xe60, 0xe64, //50 - 0xe68, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84 - }; - - u4Byte backupRegData[sizeof(backupRegAddrs)/sizeof(u4Byte)]; - - - //backup BB&MAC default value - - _DPK_parabackup(pDM_Odm, backupRegData, backupRegAddrs, sizeof(backupRegAddrs)/sizeof(u4Byte)); - - //set global parameters - _DPK_Globalparaset(pDM_Odm); - - //DPK - _DPK_pathABDPK(pDM_Odm); - - // TH_DPK=thermalmeter - - - //reload BB&MAC defaul value; - _DPK_parareload(pDM_Odm, backupRegData, backupRegAddrs, sizeof(backupRegAddrs)/sizeof(u4Byte)); - -} - -VOID -PHY_DPCalibrate_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - pDM_Odm->DPK_Done = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_DPCalibrate_8812A\n")); - phy_DPCalibrate_8812A(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_DPCalibrate_8812A\n")); -} - - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8812A 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8812A(Adapter, FALSE); +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr8812A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + u4Byte finalBbSwingIdx[2]; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte PwrTrackingLimit = 26; //+1.0dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); + + if(TxRate != 0xFF) //20130429 Mimic Modify High Rate BBSwing Limit. + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit = 32; //+4dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit = 30; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit = 28; //+2dB + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit = 28; //+2dB + + else if((TxRate >= MGN_MCS8)&&(TxRate <= MGN_MCS10)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS11)&&(TxRate <= MGN_MCS12)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS13)&&(TxRate <= MGN_MCS15)) //64QAM + PwrTrackingLimit = 28; //+2dB + + //2 VHT + else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT1SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT1SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT1SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else if((TxRate >= MGN_VHT2SS_MCS0)&&(TxRate <= MGN_VHT2SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT2SS_MCS3)&&(TxRate <= MGN_VHT2SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT2SS_MCS5)&&(TxRate <= MGN_VHT2SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT2SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT2SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT2SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else + PwrTrackingLimit = 24; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); + + + if (Method == BBSWING) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); + + if (RFPath == ODM_RF_PATH_A) + { + finalBbSwingIdx[ODM_RF_PATH_A] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); + } + else + { + finalBbSwingIdx[ODM_RF_PATH_B] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B], finalBbSwingIdx[ODM_RF_PATH_B])); + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_B]]); + } + } + + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) + { + if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit; /*CCK Follow the same compensate value as Path A*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index <= 0) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; /*CCK Follow the same compensate value as Path A*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + } + + if (RFPath == ODM_RF_PATH_B) + { + if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index <= 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + } + + } + else + { + return; + } +} + +VOID +GetDeltaSwingTable_8812A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; + pConfig->RfPathCount = MAX_PATH_NUM_8812A; + pConfig->ThermalRegAddr = RF_T_METER_8812A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; + pConfig->DoIQK = DoIQK_8812A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8812A; +} + + +#define BW_20M 0 +#define BW_40M 1 +#define BW_80M 2 + +void _IQK_RX_FillIQC_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + } + else{ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); + } + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} +void _IQK_BackupRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + RFB_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} +void _IQK_BackupAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} +void _IQK_RestoreMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} +void _IQK_RestoreRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + case ODM_RF_PATH_B: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); + } + break; + default: + break; + } +} +void _IQK_RestoreAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); + //ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); + //ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + + +void _IQK_ConfigureMAC_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +#define cal_num 10 + +void _IQK_Tx_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte chnlIdx + ) +{ + u1Byte delay_count, cal = 0; + u1Byte cal0_retry, cal1_retry, TX0_Average = 0, TX1_Average = 0, RX0_Average = 0, RX1_Average = 0; + int TX_IQC_temp[10][4], TX_IQC[4]={}; //TX_IQC = [TX0_X, TX0_Y,TX1_X,TX1_Y]; for 3 times + int RX_IQC_temp[10][4], RX_IQC[4]={}; //RX_IQC = [RX0_X, RX0_Y,RX1_X,RX1_Y]; for 3 times + BOOLEAN TX0_fail = TRUE, RX0_fail = TRUE, IQK0_ready = FALSE, TX0_finish = FALSE, RX0_finish = FALSE; + BOOLEAN TX1_fail = TRUE, RX1_fail = TRUE, IQK1_ready = FALSE, TX1_finish = FALSE, RX1_finish = FALSE, VDF_enable = FALSE; + int i, ii, dx = 0, dy = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA5G = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA5G, pDM_Odm->ExtPA)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, RFE_Type = %d\n", pDM_Odm->SupportInterface, pDM_Odm->RFEType)); + if (*pDM_Odm->pBandWidth == 2){ + VDF_enable = TRUE; + } + VDF_enable = FALSE; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + // Port 1 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off + + // DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + //====== Path A TX IQK RF Setting ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); + //====== Path B TX IQK RF Setting ====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G){ + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f7); + } + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); + } + if (*pDM_Odm->pBandType){ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); + if (pDM_Odm->RFEType == 3){ + if (pDM_Odm->ExtPA) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + } + } + + if (VDF_enable){} + else{ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); + + cal0_retry = 0; + cal1_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + if (!TX0_finish) + IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if (!TX1_finish) + IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK0_ready && IQK1_ready) || (delay_count>20)) + break; + else{ + ODM_delay_ms(1); + delay_count++; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX delay_count = %d\n", delay_count)); + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + TX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); + if (!(TX0_fail || TX0_finish)){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_IQC_temp[TX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_IQC_temp[TX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", TX0_Average, (TX_IQC_temp[TX0_Average][0])>>21&0x000007ff, TX0_Average, (TX_IQC_temp[TX0_Average][1])>>21&0x000007ff)); + /* + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + TX0_Average++; + } + else{ + cal0_retry++; + if (cal0_retry == 10) + break; + } + if (!(TX1_fail || TX1_finish)){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + TX_IQC_temp[TX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + TX_IQC_temp[TX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", TX1_Average, (TX_IQC_temp[TX1_Average][2])>>21&0x000007ff, TX1_Average, (TX_IQC_temp[TX1_Average][3])>>21&0x000007ff)); + /* + int reg1 = 0, reg2 = 0, Image_Power = 0; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + TX1_Average++; + } + else{ + cal1_retry++; + if (cal1_retry == 10) + break; + } + } + else{ + cal0_retry++; + cal1_retry++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms TX IQK Not Ready!!!!!\n")); + if (cal0_retry == 10) + break; + } + if (TX0_Average >= 2){ + for (i = 0; i < TX0_Average; i++){ + for (ii = i+1; ii >21) - (TX_IQC_temp[ii][0]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_IQC_temp[i][1]>>21) - (TX_IQC_temp[ii][1]>>21); + if (dy < 4 && dy > -4){ + TX_IQC[0] = ((TX_IQC_temp[i][0]>>21) + (TX_IQC_temp[ii][0]>>21))/2; + TX_IQC[1] = ((TX_IQC_temp[i][1]>>21) + (TX_IQC_temp[ii][1]>>21))/2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_X = %x;;TXA_Y = %x\n", TX_IQC[0]&0x000007ff, TX_IQC[1]&0x000007ff)); + TX0_finish = TRUE; + } + } + } + } + } + if (TX1_Average >= 2){ + for (i = 0; i < TX1_Average; i++){ + for (ii = i+1; ii >21) - (TX_IQC_temp[ii][2]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_IQC_temp[i][3]>>21) - (TX_IQC_temp[ii][3]>>21); + if (dy < 4 && dy > -4){ + TX_IQC[2] = ((TX_IQC_temp[i][2]>>21) + (TX_IQC_temp[ii][2]>>21))/2; + TX_IQC[3] = ((TX_IQC_temp[i][3]>>21) + (TX_IQC_temp[ii][3]>>21))/2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_X = %x;;TXB_Y = %x\n", TX_IQC[2]&0x000007ff, TX_IQC[3]&0x000007ff)); + TX1_finish = TRUE; + } + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_Average = %d, TX1_Average = %d\n", TX0_Average, TX1_Average)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_finish = %d, TX1_finish = %d\n", TX0_finish, TX1_finish)); + if (TX0_finish && TX1_finish) + break; + if ((cal0_retry + TX0_Average) >= 10 || (cal1_retry + TX1_Average) >= 10 ) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal0_retry)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal1_retry)); + + } + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, 0xffc00)); // Load LOK + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, 0xffc00)); // Load LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (VDF_enable == 1){} + else{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (TX0_finish){ + //====== Path A RX IQK RF Setting====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); + } + if (TX1_finish){ + //====== Path B RX IQK RF Setting====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x00000); + } + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + else + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); + //ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00000077); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00000077); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0x02000077); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0x02000077); + } + + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (TX0_finish){ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x82140119); + } + if (TX1_finish){ + ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xe88, 0x82140119); + } + cal0_retry = 0; + cal1_retry = 0; + while(1){ + // one shot + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (TX0_finish){ + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[0])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[1])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161500); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160cc0); + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000); + ODM_delay_ms(5); //Delay 5ms + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + } + if (TX1_finish){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[2])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[3])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161500); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28160ca0); + } + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_delay_ms(5); //Delay 5ms + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + } + delay_count = 0; + while (1){ + if (!RX0_finish && TX0_finish) + IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if (!RX1_finish && TX1_finish) + IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK0_ready && IQK1_ready)||(delay_count>20)) + break; + else{ + ODM_delay_ms(1); + delay_count++; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX delay_count = %d\n", delay_count)); + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + RX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); + if (!(RX0_fail || RX0_finish) && TX0_finish){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_IQC_temp[RX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_IQC_temp[RX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", RX0_Average, (RX_IQC_temp[RX0_Average][0])>>21&0x000007ff, RX0_Average, (RX_IQC_temp[RX0_Average][1])>>21&0x000007ff)); +/* + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); +*/ + RX0_Average++; + } + else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("1. RXA_cal_retry = %d\n", cal0_retry)); + cal0_retry++; + if (cal0_retry == 10) + break; + } + if (!(RX1_fail || RX1_finish) && TX1_finish){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + RX_IQC_temp[RX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + RX_IQC_temp[RX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", RX1_Average, (RX_IQC_temp[RX1_Average][2])>>21&0x000007ff, RX1_Average, (RX_IQC_temp[RX1_Average][3])>>21&0x000007ff)); +/* + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); +*/ + RX1_Average++; + } + else{ + cal1_retry++; + if (cal1_retry == 10) + break; + } + + } + else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("2. RXA_cal_retry = %d\n", cal0_retry)); + cal0_retry++; + cal1_retry++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms RX IQK Not Ready!!!!!\n")); + if (cal0_retry == 10) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("3. RXA_cal_retry = %d\n", cal0_retry)); + if (RX0_Average >= 2){ + for (i = 0; i < RX0_Average; i++){ + for (ii = i+1; ii >21) - (RX_IQC_temp[ii][0]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_IQC_temp[i][1]>>21) - (RX_IQC_temp[ii][1]>>21); + if (dy < 4 && dy > -4){ + RX_IQC[0]= ((RX_IQC_temp[i][0]>>21) + (RX_IQC_temp[ii][0]>>21))/2; + RX_IQC[1] = ((RX_IQC_temp[i][1]>>21) + (RX_IQC_temp[ii][1]>>21))/2; + RX0_finish = TRUE; + break; + } + } + } + } + } + if (RX1_Average >= 2){ + for (i = 0; i < RX1_Average; i++){ + for (ii = i+1; ii >21) - (RX_IQC_temp[ii][2]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_IQC_temp[i][3]>>21) - (RX_IQC_temp[ii][3]>>21); + if (dy < 4 && dy > -4){ + RX_IQC[2] = ((RX_IQC_temp[i][2]>>21) + (RX_IQC_temp[ii][2]>>21))/2; + RX_IQC[3] = ((RX_IQC_temp[i][3]>>21) + (RX_IQC_temp[ii][3]>>21))/2; + RX1_finish = TRUE; + break; + } + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_Average = %d, RX1_Average = %d\n", RX0_Average, RX1_Average)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_finish = %d, RX1_finish = %d\n", RX0_finish, RX1_finish)); + if ((RX0_finish|| !TX0_finish) && (RX1_finish || !TX1_finish) ) + break; + if ((cal0_retry + RX0_Average) >= 10 || (cal1_retry + RX1_Average) >= 10 || RX0_Average == 3 || RX1_Average == 3) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal0_retry)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal1_retry)); + } + + // FillIQK Result + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + + if (TX0_finish){ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, TX_IQC[0], TX_IQC[1]); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); + } + + + + if (RX0_finish){ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, RX_IQC[0], RX_IQC[1]); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); + + if (TX1_finish){ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, TX_IQC[2], TX_IQC[3]); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); + } + + + + if (RX1_finish){ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, RX_IQC[2], RX_IQC[3]); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); + } + + + +} + +#define MACBB_REG_NUM 9 +#define AFE_REG_NUM 12 +#define RF_REG_NUM 3 + +// Maintained by BB James. +VOID +phy_IQCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM] = {0}, RFA_backup[RF_REG_NUM] = {0}, RFB_backup[RF_REG_NUM] = {0}; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0xe00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb0, 0xcb4, + 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb0, 0xeb4}; + u4Byte Reg_C1B8, Reg_E1B8; + u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; + u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); + + _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + Reg_C1B8 = ODM_Read4Byte(pDM_Odm, 0xcb8); + Reg_E1B8 = ODM_Read4Byte(pDM_Odm, 0xeb8); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); + + _IQK_ConfigureMAC_8812A(pDM_Odm); + _IQK_Tx_8812A(pDM_Odm, chnlIdx); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); + + _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_Write4Byte(pDM_Odm, 0xcb8, Reg_C1B8); + ODM_Write4Byte(pDM_Odm, 0xeb8, Reg_E1B8); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + + +} + +VOID +phy_LCCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; + + //Check continuous TX and Packet TX + u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; + + // Backup RF reg18. + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + if((reg0x914 & 0x70000) != 0) //If contTx, disable all continuous TX. 0x914[18:16] + // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx + // until another packet comes in. To avoid ContTx being turned off, we skip this step. + ;//ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914 & (~0x70000)); + else // If packet Tx-ing, pause Tx. + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); + + +/* + //3 1. Read original RF mode + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask); + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask); + + + //3 2. Set RF mode = standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, (RF_Amode&0x8FFFF)|0x10000); + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, (RF_Bmode&0x8FFFF)|0x10000); +*/ + + // Enter LCK mode + tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp | BIT14); + + //3 3. Read RF reg18 + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + //3 4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); + + ODM_delay_ms(150); // suggest by RFSI Binson + + // Leave LCK mode + tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp & ~BIT14); + + + + //3 Restore original situation + if((reg0x914 & 70000) != 0) //Deal with contisuous TX case, 0x914[18:16] + { + // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx + // until another packet comes in. To avoid ContTx being turned off, we skip this step. + //ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } + + // Recover channel number + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + /* + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, RF_Amode); + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, RF_Bmode); + */ + +} + + + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + +VOID +phy_ReloadIQKSetting_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff0000)>>16); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff0000)>>16); + + if (*pDM_Odm->pBandWidth != 2){ + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xce8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4]); + ODM_Write4Byte(pDM_Odm, 0xee8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff0000)>>17); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff)>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff0000)>>17); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff)>>1); + + +} + +VOID +PHY_ResetIQKResult_8812A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); +} + +VOID +phy_IQCalibrate_By_FW_8812A( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + u1Byte IQKcmd[3] = {pHalData->CurrentChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(pHalData->CurrentBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) + Buf2 = 0x1; + else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) + Buf2 = 0x1<<1; + else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pHalData->ExternalPA_5G | pHalData->ExternalLNA_5G<<1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== IQK Start ==\n")); + + FillH2CCmd_8812(pAdapter, 0x45, 3, IQKcmd); + + rtl8812_iqk_wait(pAdapter, 500); +} + +VOID +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + u4Byte counter = 0; + u4Byte StartTime; + s4Byte ProgressingTime; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + +#if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif +#endif//(MP_DRIVER == 1) + +//#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + //if (ODM_CheckPowerStatus(pAdapter) == FALSE) + //return; +//#endif + pDM_Odm->IQKFWOffload = 0; + StartTime = ODM_GetCurrentTime( pDM_Odm); + +#if MP_DRIVER == 1 + if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) +#endif + { + + if(pDM_Odm->IQKFWOffload) + { + phy_IQCalibrate_By_FW_8812A(pAdapter); + } + else + { + phy_IQCalibrate_8812A(pDM_Odm, pHalData->CurrentChannel); + } + } + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); +} + + +VOID +PHY_LCCalibrate_8812A( + IN PVOID pDM_VOID + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte StartTime; + s4Byte ProgressingTime; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; + #endif//(MP_DRIVER == 1) +#endif + + StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8812A\n")); + + phy_LCCalibrate_8812A(pDM_Odm, TRUE); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8812A\n")); + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); + +} + +VOID phy_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + +#endif + + if (IS_HARDWARE_TYPE_8821(pAdapter)) + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x1); //Main + else + ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x2); //Aux + } + else if (IS_HARDWARE_TYPE_8812(pAdapter)) + { + if (pHalData->RFEType == 5) + { + if(bMain) { + //WiFi + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } else { + // BT + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } + } + } + +} + +VOID PHY_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); + +#endif +} + + +VOID +_DPK_ThermalCompensation( + IN PDM_ODM_T pDM_Odm + ) +{ +} + +VOID +_DPK_parareload( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + + + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } +} + + +VOID +_DPK_parabackup( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + + + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } +} + +VOID +_DPK_Globalparaset( + IN PDM_ODM_T pDM_Odm + ) +{ + + //***************************************// + //set MAC register + //***************************************// + + //TX pause + ODM_Write4Byte(pDM_Odm, 0x520, 0x007f3F0F); + + //***************************************// + //set BB register + //***************************************// + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); + + // test pin in/out control + ODM_Write4Byte(pDM_Odm, 0x970, 0x00000000); + + // path A regcb8[3:0] = h'd, TRSW to TX + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0050824d); + + // path B regeb8[3:0] = h'd, TRSW to TX + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0050824d); + + // reg838[3:0] = h'c, CCA off + ODM_Write4Byte(pDM_Odm, 0x838, 0x06c8d24c); + + // path A 3-wire off + ODM_Write4Byte(pDM_Odm, 0xc00, 0x00000004); + + // path B 3-wire off + ODM_Write4Byte(pDM_Odm, 0xe00, 0x00000004); + + // reg90c[15] = b'1, DAC fifo reset by CSWU + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + + // reset DPK circuit + ODM_Write4Byte(pDM_Odm, 0xb00, 0x03000100); + + // path A regc94[0] = b'1 (r_gothrough_iqkdpk), ±N DPK ¤Á¶i normal path + ODM_Write4Byte(pDM_Odm, 0xc94, 0x01000001); + + // path B rege94[0] = b'1 (r_gothrough_iqkdpk), ±N DPK ¤Á¶i normal path + ODM_Write4Byte(pDM_Odm, 0xe94, 0x01000001); + + //***************************************// + //set AFE register + //***************************************// + + //path A + //regc68 ¨ì regc84À³¸Ó¬O­n¸ò¥¿±` Tx mode ®Éªº³]©w¤@­P + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc6c, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc70, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc74, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc78, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc7c, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x19791979); + + // force DAC/ADC power on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + //path B + //rege68 ¨ì rege84À³¸Ó¬O­n¸ò¥¿±` Tx mode ®Éªº³]©w¤@­P + + ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe6c, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe70, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe74, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe78, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe7c, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe84, 0x19791979); + + // force DAC/ADC power on + ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); + +} + + +VOID +_DPK_GetGainLoss( + IN PDM_ODM_T pDM_Odm, + IN u1Byte path + ) +{ + u4Byte GL_I=0,GL_Q=0; + u4Byte GL_I_tmp=0,GL_Q_tmp=0; + + u4Byte Power_GL; + u2Byte Scaler[]={0x4000, 0x41db, 0x43c7, 0x45c3, 0x47cf, 0x49ec, 0x4c19, 0x4e46, 0x5093,0x52f2, //10 + 0x5560, 0x57cf, 0x5a7f, 0x5d0e, 0x5fbe + }; + u1Byte sindex=0; + u4Byte pagesel = 0,regsel = 0; + + if(path == 0) //pathA + { + pagesel = 0; + regsel = 0; + } + else //pathB + { + pagesel = 0x200; + regsel = 0x40; + } + + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0601f0bf); + ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x0c000000); + + + + GL_I_tmp = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0xffff0000); + GL_Q_tmp = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0x0000ffff); + + if(GL_I_tmp >= 0x8000) + GL_I = (GL_I_tmp-0x8000+0x1); + else + GL_I = GL_I_tmp; + + + if(GL_Q_tmp >= 0x8000) + GL_Q = (GL_Q_tmp-0x8000+0x1); + else + GL_Q = GL_Q_tmp; + + Power_GL = ((GL_I*GL_I)+(GL_Q*GL_Q))/4; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Power_GL = 0x%x", Power_GL)); + + if (Power_GL > 63676){ + sindex = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0 dB\n")); + } + else if (63676 >= Power_GL && Power_GL > 60114){ + sindex = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.25 dB\n")); + } + else if (60114 >= Power_GL && Power_GL> 56751){ + sindex = 2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.5 dB\n")); + } + else if (56751 >= Power_GL && Power_GL> 53577){ + sindex = 3; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 0.75 dB\n")); + } + else if (53577 >= Power_GL && Power_GL> 49145){ + sindex = 4; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1 dB\n")); + } + else if (49145 >= Power_GL && Power_GL> 47750){ + sindex = 5; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.25 dB\n")); + } + else if (47750 >= Power_GL && Power_GL> 45079){ + sindex = 6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.5 dB\n")); + } + else if (45079 >= Power_GL && Power_GL> 42557){ + sindex = 7; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 1.75 dB\n")); + } + else if (42557 >= Power_GL && Power_GL> 40177){ + sindex = 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2 dB\n")); + } + else if (40177 >= Power_GL && Power_GL> 37929){ + sindex = 9; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.25 dB\n")); + } + else if (37929 >= Power_GL && Power_GL> 35807){ + sindex = 10; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.5 dB\n")); + } + else if (35807 >= Power_GL && Power_GL> 33804){ + sindex = 11; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 2.75 dB\n")); + } + else if (33804 >= Power_GL && Power_GL> 31913){ + sindex = 12; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3 dB\n")); + } + else if (31913 >= Power_GL && Power_GL> 30128){ + sindex = 13; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3.25 dB\n")); + } + else if (30128 >= Power_GL){ + sindex = 14; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Gainloss = 3.5 dB\n")); + } + + + ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, (Scaler[sindex] << 16) | Scaler[sindex]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Set Gainloss reg 0xc98(0xe98)= 0x%x\n",ODM_Read4Byte(pDM_Odm, 0xc98+pagesel))); + +} + + +VOID +_DPK_EnableDP( + IN PDM_ODM_T pDM_Odm, + IN u1Byte path, + IN u4Byte TXindex + ) +{ + + //***************************************// + //Enable DP + //***************************************// + + //PWSF[6] = 0x40 = 0dB, set the address represented TXindex as 0dB + u1Byte PWSF[] = { 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40, //6~0dB + 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, 0x0d, //-1~-7dB + 0x0a, 0x08, 0x06, 0x05, 0x04, 0x03, 0x03, //-8~-14dB + 0x02, 0x02, 0x01, 0x01, + }; + u1Byte zeropoint; + u1Byte pwsf1,pwsf2; + u1Byte i; + u4Byte pagesel = 0,regsel = 0; + + if(path == 0) + { + pagesel = 0; + regsel = 0; + } + else + { + pagesel = 0x200; + regsel = 0x40; + } + + + //=========// + // DPK setting // + //=========// + // reg82c[31] = b'1, ¤Á´«¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); + + + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0000f098); + ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0x776c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x08840000); + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); + + + // ¼gPWSF table in 1st SRAM for PA = 11 use + ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x00000800); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Write PWSF table\n")); + + + if(TXindex == 0x1f) + zeropoint = 0; + else if(TXindex == 0x1e) + zeropoint = 1; + else if(TXindex == 0x1d) + zeropoint = 2; + else if(TXindex == 0x1c) + zeropoint = 3; + else if(TXindex == 0x1b) + zeropoint = 4; + else if(TXindex == 0x1a) + zeropoint = 5; + else if(TXindex == 0x19) + zeropoint = 6; + else + zeropoint = 6; + + + + for(i=0;i<16;i++) + { + pwsf1 = (6-zeropoint)+i*2; + if(pwsf1 > 24) + pwsf1 = 24; + + pwsf2 = (6-zeropoint-1)+i*2; + if(pwsf2 > 24) + pwsf2 = 24; + + ODM_Write4Byte(pDM_Odm, 0xce4+pagesel, 0x00000001 | i<<1 | (PWSF[pwsf1]<<8) | (PWSF[pwsf2]<<16)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x%x\n", ODM_Read4Byte(pDM_Odm, 0xce4+pagesel))); + ODM_SetBBReg(pDM_Odm, 0xce4+pagesel, 0xff, 0x0); + } + + ODM_Write4Byte(pDM_Odm, 0xce4+pagesel, 0x00000000); + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); + +} + + +VOID +_DPK_pathABDPK( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte TXindex = 0; + u1Byte path = 0; + u4Byte pagesel = 0,regsel = 0; + u4Byte i=0,j=0; + + for(path=0;path<2;path ++) //path A = 0; path B = 1; + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK start!!!\n", (path==0)?"A":"B")); + + if(path == 0) + { + pagesel = 0; + regsel = 0; + } + else + { + pagesel = 0x200; + regsel = 0x40; + } + + //***************************************// + //find compress-2.5dB TX index + //***************************************// + + + // reg82c[31] = b'1, ¤Á´«¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); + + // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. + // dB_sel = b'000 ' 1.0 dB PA gain loss + // dB_sel = b'001 ' 1.5 dB PA gain loss + // dB_sel = b'010 ' 2.0 dB PA gain loss + // dB_sel = b'011 ' 2.5 dB PA gain loss + // dB_sel = b'100 ' 3.0 dB PA gain loss + // dB_sel = b'101 ' 3.5 dB PA gain loss + // dB_sel = b'110 ' 4.0 dB PA gain loss + ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x00006000); + + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0401e038); + ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x148b0000); + ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); + + // tx_amp ' ¨M©w Ramp ¤¤¦U©¶ªiªº®¶´T¤j¤p + ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, 0x41382e21); + ODM_Write4Byte(pDM_Odm, 0xc9c+pagesel, 0x5b554f48); + ODM_Write4Byte(pDM_Odm, 0xca0+pagesel, 0x6f6b6661); + ODM_Write4Byte(pDM_Odm, 0xca4+pagesel, 0x817d7874); + ODM_Write4Byte(pDM_Odm, 0xca8+pagesel, 0x908c8884); + ODM_Write4Byte(pDM_Odm, 0xcac+pagesel, 0x9d9a9793); + ODM_Write4Byte(pDM_Odm, 0xcb0+pagesel, 0xaaa7a4a1); + ODM_Write4Byte(pDM_Odm, 0xcb4+pagesel, 0xb6b3b0ad); + + // tx_inverse ' Ramp ¤¤¦U©¶ªipower ªº­Ë¼Æ, ¥H­pºâ¥X PA ªº gain report?? + ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x02ce03e9); + ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x01fd0249); + ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x01a101c9); + ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x016a0181); + ODM_Write4Byte(pDM_Odm, 0xc50+pagesel, 0x01430155); + ODM_Write4Byte(pDM_Odm, 0xc54+pagesel, 0x01270135); + ODM_Write4Byte(pDM_Odm, 0xc58+pagesel, 0x0112011c); + ODM_Write4Byte(pDM_Odm, 0xc5c+pagesel, 0x01000108); + ODM_Write4Byte(pDM_Odm, 0xc60+pagesel, 0x00f100f8); + ODM_Write4Byte(pDM_Odm, 0xc64+pagesel, 0x00e500eb); + ODM_Write4Byte(pDM_Odm, 0xc68+pagesel, 0x00db00e0); + ODM_Write4Byte(pDM_Odm, 0xc6c+pagesel, 0x00d100d5); + ODM_Write4Byte(pDM_Odm, 0xc70+pagesel, 0x00c900cd); + ODM_Write4Byte(pDM_Odm, 0xc74+pagesel, 0x00c200c5); + ODM_Write4Byte(pDM_Odm, 0xc78+pagesel, 0x00bb00be); + ODM_Write4Byte(pDM_Odm, 0xc7c+pagesel, 0x00b500b8); + + //============// + // RF setting for DPK // + //============// + + //pathA,pathB standby mode + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x0, 0x0, bRFRegOffsetMask, 0x10000); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)0x1, 0x0, bRFRegOffsetMask, 0x10000); + + // 00[4:0] = Tx AGC, 00[9:5] = Rx AGC (BB), 00[12:10] = Rx AGC (LNA) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x0, bRFRegOffsetMask, 0x50bff); + + + // 64[14:12] = loop back attenuation + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x64, bRFRegOffsetMask, 0x19aac); + + // 8f[14:13] = PGA2 gain + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x8f, bRFRegOffsetMask, 0x8e001); + + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x000c5599); + + + // delay 100 ms + ODM_delay_ms(100); + + + // read back + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0109f018); + ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x09000000); + // ¥i¥H¦b d00[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w + // Ū¦^d00[3:0] = h'1 ' Tx AGC = 15 + // Ū¦^d00[3:0] = h'2 ' Tx AGC = 16 + // Ū¦^d00[3:0] = h'3 ' Tx AGC = 17 + // Ū¦^d00[3:0] = h'4 ' Tx AGC = 18 + // Ū¦^d00[3:0] = h'5 ' Tx AGC = 19 + // Ū¦^d00[3:0] = h'6 ' Tx AGC = 1a + // Ū¦^d00[3:0] = h'7 ' Tx AGC = 1b + // Ū¦^d00[3:0] = h'8 ' Tx AGC = 1c + // Ū¦^d00[3:0] = h'9 ' Tx AGC = 1d + // Ū¦^d00[3:0] = h'a ' Tx AGC = 1e + // Ū¦^d00[3:0] = h'b ' Tx AGC = 1f + + TXindex = ODM_GetBBReg(pDM_Odm, 0xd00+regsel, 0x0000000f); + + + //***************************************// + //get LUT + //***************************************// + + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0001e038); + ODM_Write4Byte(pDM_Odm, 0xc94+pagesel, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x400c5599); + ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x11930080); //0xcc4[9:4]= DPk fail threshold + ODM_Write4Byte(pDM_Odm, 0xc8c+pagesel, 0x3c000000); + + + // tx_amp ' ¨M©w Ramp ¤¤¦U©¶ªiªº®¶´T¤j¤p + + ODM_Write4Byte(pDM_Odm, 0xc98+pagesel, 0x41382e21); + ODM_Write4Byte(pDM_Odm, 0xc9c+pagesel, 0x5b554f48); + ODM_Write4Byte(pDM_Odm, 0xca0+pagesel, 0x6f6b6661); + ODM_Write4Byte(pDM_Odm, 0xca4+pagesel, 0x817d7874); + ODM_Write4Byte(pDM_Odm, 0xca8+pagesel, 0x908c8884); + ODM_Write4Byte(pDM_Odm, 0xcac+pagesel, 0x9d9a9793); + ODM_Write4Byte(pDM_Odm, 0xcb0+pagesel, 0xaaa7a4a1); + ODM_Write4Byte(pDM_Odm, 0xcb4+pagesel, 0xb6b3b0ad); + + // tx_inverse ' Ramp ¤¤¦U©¶ªipower ªº­Ë¼Æ, ¥H­pºâ¥X PA ªº gain + ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x02ce03e9); + ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x01fd0249); + ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x01a101c9); + ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x016a0181); + ODM_Write4Byte(pDM_Odm, 0xc50+pagesel, 0x01430155); + ODM_Write4Byte(pDM_Odm, 0xc54+pagesel, 0x01270135); + ODM_Write4Byte(pDM_Odm, 0xc58+pagesel, 0x0112011c); + ODM_Write4Byte(pDM_Odm, 0xc5c+pagesel, 0x01000108); + ODM_Write4Byte(pDM_Odm, 0xc60+pagesel, 0x00f100f8); + ODM_Write4Byte(pDM_Odm, 0xc64+pagesel, 0x00e500eb); + ODM_Write4Byte(pDM_Odm, 0xc68+pagesel, 0x00db00e0); + ODM_Write4Byte(pDM_Odm, 0xc6c+pagesel, 0x00d100d5); + ODM_Write4Byte(pDM_Odm, 0xc70+pagesel, 0x00c900cd); + ODM_Write4Byte(pDM_Odm, 0xc74+pagesel, 0x00c200c5); + ODM_Write4Byte(pDM_Odm, 0xc78+pagesel, 0x00bb00be); + ODM_Write4Byte(pDM_Odm, 0xc7c+pagesel, 0x00b500b8); + + //fill BB TX index for the DPK reference + // reg82c[31] =1b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083d5); + + ODM_Write4Byte(pDM_Odm, 0xc20+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc24+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc28+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc2c+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc30+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc34+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc38+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc3c+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc40+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc44+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc48+pagesel, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc4c+pagesel, 0x3c3c3c3c); + + // reg82c[31] =1b'1, ¤Á´«¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083d5); + + + + // r_agc_boudary + // PA gain = 11 ¹ïÀ³ tx_agc ±q1f ¨ì11 boundary = b'11111 ' PageC1 ªº bc0[4:0] = 11111 + // PA gain = 10 ¹ïÀ³ tx_agc ±q11 ¨ì11 ? boundary = b'10011 ' PageC1 ªº bc0[9:5] = 10001 + // PA gain = 01 ¹ïÀ³ tx_agc ±q10 ¨ì0e ? boundary = b'10000 ' PageC1 ªº bc0[14:10] = 10000 + // PA gain = 00 ¹ïÀ³ tx_agc ±q0d ¨ì00 ? boundary = b'01101 ' PageC1 ªº bc0[19:15] = 01101 + ODM_Write4Byte(pDM_Odm, 0xcbc+pagesel, 0x0006c23f); + + // r_bnd, ¥t¥~4¶ô PWSF (power scaling factor) ªº boundary, ¦]¬°¥Ø«e¥u¦³¦b PA gain = 11 ®É¤~°µ¸ÉÀv, ©Ò¥H³]¦¨ h'fffff §Y¥i. + ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x000fffff); + + //============// + // RF setting for DPK // + //============// + // 00[4:0] = Tx AGC, 00[9:5] = Rx AGC (BB), 00[12:10] = Rx AGC (LNA) + // ¦¹³B reg00[4:0] = h'1d, ¬O¥Ñ«e­± gain loss function ±o¨ìªºµ²ªG. + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)(0x0+path), 0x0, bRFRegOffsetMask, 0x517e0 | TXindex); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RF 0x0 = 0x%x\n", 0x517e0 | TXindex)); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0xc00c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8+pagesel, 0x400c5599); + + // delay 100 ms + ODM_delay_ms(100); + + // read back dp_fail report + ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x00000000); + + //if d00[6] = 1, DPK fail + if(ODM_GetBBReg(pDM_Odm, 0xd00+regsel, BIT6)) + { + //bypass DPK + ODM_Write4Byte(pDM_Odm, 0xcc4+pagesel, 0x28848000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK fail!!!!!!!!!!!!!!!!!!!!!\n", (path==0)?"A":"B")); + + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path %s DPK ok!!!!!!!!!!!!!!!!!!!!!\n", (path==0)?"A":"B")); + + + + //read LMS table -->debug message only + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("read LMS\n")); + + for(i=0;i<8;i++){ + ODM_Write4Byte(pDM_Odm, 0xc90+pagesel, 0x0601f0b8+i); + for(j=0;j<4;j++){ + ODM_Write4Byte(pDM_Odm, 0xcb8+pagesel, 0x09000000+(j<<24)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x%x", ODM_Read4Byte(pDM_Odm, 0xd00+regsel))); + } + } + + + //***************************************// + //get gain loss + //***************************************// + + _DPK_GetGainLoss(pDM_Odm,path); + + + //***************************************// + //Enable DP + //***************************************// + + _DPK_EnableDP(pDM_Odm, path, TXindex); + + +} + + +} + + + +VOID +phy_DPCalibrate_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte backupRegAddrs[] = { + 0x970, 0xcb8, 0x838, 0xc00, 0x90c, 0xb00, 0xc94, 0x82c, 0x520, 0xc60, // 10 + 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc50, // 20 + 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, // 30 + 0xc48, 0xc4c, 0xe50, 0xe20, 0xe24, 0xe28, 0xe2c, 0xe30, 0xe34, 0xe38, // 40 + 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xeb8, 0xe00, 0xe94, 0xe60, 0xe64, //50 + 0xe68, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84 + }; + + u4Byte backupRegData[sizeof(backupRegAddrs)/sizeof(u4Byte)]; + + + //backup BB&MAC default value + + _DPK_parabackup(pDM_Odm, backupRegData, backupRegAddrs, sizeof(backupRegAddrs)/sizeof(u4Byte)); + + //set global parameters + _DPK_Globalparaset(pDM_Odm); + + //DPK + _DPK_pathABDPK(pDM_Odm); + + // TH_DPK=thermalmeter + + + //reload BB&MAC defaul value; + _DPK_parareload(pDM_Odm, backupRegData, backupRegAddrs, sizeof(backupRegAddrs)/sizeof(u4Byte)); + +} + +VOID +PHY_DPCalibrate_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + pDM_Odm->DPK_Done = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_DPCalibrate_8812A\n")); + phy_DPCalibrate_8812A(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_DPCalibrate_8812A\n")); +} + + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.h index 7d1909c7873..8cd464aac34 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_ce.h @@ -1,106 +1,106 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8812A_H__ -#define __HAL_PHY_RF_8812A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8812A 10 //ms -#define IQK_DEFERRED_TIME_8812A 4 //sec -#define index_mapping_NUM_8812A 15 -#define AVG_THERMAL_NUM_8812A 4 -#define RF_T_METER_8812A 0x42 - - -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8812A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr8812A( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery -); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8812A( - PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); - -VOID -PHY_DPCalibrate_8812A( - IN PDM_ODM_T pDM_Odm -); -VOID PHY_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - - -#endif // #ifndef __HAL_PHY_RF_8812A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8812A_H__ +#define __HAL_PHY_RF_8812A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8812A 10 //ms +#define IQK_DEFERRED_TIME_8812A 4 //sec +#define index_mapping_NUM_8812A 15 +#define AVG_THERMAL_NUM_8812A 4 +#define RF_T_METER_8812A 0x42 + + +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8812A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr8812A( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery +); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8812A( + PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); + +VOID +PHY_DPCalibrate_8812A( + IN PDM_ODM_T pDM_Odm +); +VOID PHY_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + + +#endif // #ifndef __HAL_PHY_RF_8812A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.c b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.c index 5dd25fb899a..20de6110fa2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.c @@ -1,2979 +1,2979 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8812A 6 - -/*---------------------------Define Local Constant---------------------------*/ - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_ResetIQKResult(pDM_Odm); - - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8812A(Adapter, FALSE); -} - -/*----------------------------------------------------------------------------- - * Function: odm_TxPwrTrackSetPwr88E() - * - * Overview: 88E change all channel tx power accordign to flag. - * OFDM & CCK are all different. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 04/23/2012 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -VOID -ODM_TxPwrTrackSetPwr8812A( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - u4Byte finalBbSwingIdx[2]; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte PwrTrackingLimit = 26; //+1.0dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); - - if(TxRate != 0xFF) //20130429 Mimic Modify High Rate BBSwing Limit. - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit = 32; /*+4dB*/ - /*2 OFDM*/ - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit = 30; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit = 28; //+2dB - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit = 28; //+2dB - - else if((TxRate >= MGN_MCS8)&&(TxRate <= MGN_MCS10)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS11)&&(TxRate <= MGN_MCS12)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS13)&&(TxRate <= MGN_MCS15)) //64QAM - PwrTrackingLimit = 28; //+2dB - - //2 VHT - else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT1SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT1SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT1SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else if((TxRate >= MGN_VHT2SS_MCS0)&&(TxRate <= MGN_VHT2SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT2SS_MCS3)&&(TxRate <= MGN_VHT2SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT2SS_MCS5)&&(TxRate <= MGN_VHT2SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT2SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT2SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT2SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else - PwrTrackingLimit = 24; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); - - - if (Method == BBSWING) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); - - if (RFPath == ODM_RF_PATH_A) - { - finalBbSwingIdx[ODM_RF_PATH_A] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", - pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); - } - else - { - finalBbSwingIdx[ODM_RF_PATH_B] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n", - pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B], finalBbSwingIdx[ODM_RF_PATH_B])); - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_B]]); - } - } - - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) - { - - if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index - PwrTrackingLimit; // CCK Follow the same compensate value as Path A - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index < 0) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index; // CCK Follow the same compensate value as Path A - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= 0; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - } - - if (RFPath == ODM_RF_PATH_B) - { - if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB= TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index < 0) - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - } - - } - else - { - return; - } -} - -VOID -GetDeltaSwingTable_8812A( - PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - - return; -} - -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->Threshold_DPK = DPK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; - pConfig->RfPathCount = MAX_PATH_NUM_8812A; - pConfig->ThermalRegAddr = RF_T_METER_8812A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; - pConfig->DoIQK = DoIQK_8812A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8812A; -} - - -#define BW_20M 0 -#define BW_40M 1 -#define BW_80M 2 - -void _IQK_RX_FillIQC_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - } - else{ - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); - } - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - case ODM_RF_PATH_B: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} -void _IQK_BackupRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - RFB_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} -void _IQK_BackupAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} -void _IQK_RestoreMacBB_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} -void _IQK_RestoreRF_8812A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - case ODM_RF_PATH_B: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); - } - break; - default: - break; - } -} -void _IQK_RestoreAFE_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); - //ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); - if (!pDM_Odm->DPK_Done) - ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); - //ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - - -void _IQK_ConfigureMAC_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -#define cal_num 10 - -void _IQK_Tx_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte chnlIdx - ) -{ - u1Byte delay_count; - u1Byte cal0_retry, cal1_retry, TX0_Average = 0, TX1_Average = 0, RX0_Average = 0, RX1_Average = 0; - int TX_IQC_temp[10][4], TX_IQC[4]; //TX_IQC = [TX0_X, TX0_Y,TX1_X,TX1_Y]; for 3 times - int RX_IQC_temp[10][4], RX_IQC[4]; //RX_IQC = [RX0_X, RX0_Y,RX1_X,RX1_Y]; for 3 times - BOOLEAN TX0_fail = TRUE, RX0_fail = TRUE, IQK0_ready = FALSE, TX0_finish = FALSE, RX0_finish = FALSE; - BOOLEAN TX1_fail = TRUE, RX1_fail = TRUE, IQK1_ready = FALSE, TX1_finish = FALSE, RX1_finish = FALSE; - int i, ii, dx = 0, dy = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA5G = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA5G, pDM_Odm->ExtPA)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, RFE_Type = %d\n", pDM_Odm->SupportInterface, pDM_Odm->RFEType)); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - // Port 1 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off - - // DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - //====== Path A TX IQK RF Setting ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); - //====== Path B TX IQK RF Setting ====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3fffd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe83f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G){ - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f7); - } - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); - ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); - } - if (*pDM_Odm->pBandType){ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); - if (pDM_Odm->RFEType == 3){ - if (pDM_Odm->ExtPA) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - } - } - - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); - - cal0_retry = 0; - cal1_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - delay_count = 0; - while (1){ - if (!TX0_finish) - IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if (!TX1_finish) - IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK0_ready && IQK1_ready) || (delay_count>20)) - break; - else{ - ODM_delay_ms(1); - delay_count++; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX delay_count = %d\n", delay_count)); - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - TX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); - if (!(TX0_fail || TX0_finish)){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_IQC_temp[TX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_IQC_temp[TX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", TX0_Average, (TX_IQC_temp[TX0_Average][0])>>21&0x000007ff, TX0_Average, (TX_IQC_temp[TX0_Average][1])>>21&0x000007ff)); - /* - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - TX0_Average++; - } - else{ - cal0_retry++; - if (cal0_retry == 10) - break; - } - if (!(TX1_fail || TX1_finish)){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - TX_IQC_temp[TX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - TX_IQC_temp[TX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", TX1_Average, (TX_IQC_temp[TX1_Average][2])>>21&0x000007ff, TX1_Average, (TX_IQC_temp[TX1_Average][3])>>21&0x000007ff)); - /* - int reg1 = 0, reg2 = 0, Image_Power = 0; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - TX1_Average++; - } - else{ - cal1_retry++; - if (cal1_retry == 10) - break; - } - } - else{ - cal0_retry++; - cal1_retry++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms TX IQK Not Ready!!!!!\n")); - if (cal0_retry == 10) - break; - } - if (TX0_Average >= 2){ - for (i = 0; i < TX0_Average; i++){ - for (ii = i+1; ii >21) - (TX_IQC_temp[ii][0]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_IQC_temp[i][1]>>21) - (TX_IQC_temp[ii][1]>>21); - if (dy < 4 && dy > -4){ - TX_IQC[0] = ((TX_IQC_temp[i][0]>>21) + (TX_IQC_temp[ii][0]>>21))/2; - TX_IQC[1] = ((TX_IQC_temp[i][1]>>21) + (TX_IQC_temp[ii][1]>>21))/2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_X = %x;;TXA_Y = %x\n", TX_IQC[0]&0x000007ff, TX_IQC[1]&0x000007ff)); - TX0_finish = TRUE; - } - } - } - } - } - if (TX1_Average >= 2){ - for (i = 0; i < TX1_Average; i++){ - for (ii = i+1; ii >21) - (TX_IQC_temp[ii][2]>>21); - if (dx < 4 && dx > -4){ - dy = (TX_IQC_temp[i][3]>>21) - (TX_IQC_temp[ii][3]>>21); - if (dy < 4 && dy > -4){ - TX_IQC[2] = ((TX_IQC_temp[i][2]>>21) + (TX_IQC_temp[ii][2]>>21))/2; - TX_IQC[3] = ((TX_IQC_temp[i][3]>>21) + (TX_IQC_temp[ii][3]>>21))/2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_X = %x;;TXB_Y = %x\n", TX_IQC[2]&0x000007ff, TX_IQC[3]&0x000007ff)); - TX1_finish = TRUE; - } - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_Average = %d, TX1_Average = %d\n", TX0_Average, TX1_Average)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_finish = %d, TX1_finish = %d\n", TX0_finish, TX1_finish)); - if (TX0_finish && TX1_finish) - break; - if ((cal0_retry + TX0_Average) >= 10 || (cal1_retry + TX1_Average) >= 10 ) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal0_retry)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal1_retry)); - - - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, 0xffc00)); // Load LOK - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, 0xffc00)); // Load LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (TX0_finish){ - //====== Path A RX IQK RF Setting====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - } - if (TX1_finish){ - //====== Path B RX IQK RF Setting====== - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe7bf); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x00000); - } - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - else - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); - //ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00000077); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00000077); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x02000077); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x02000077); - } - - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (TX0_finish){ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x82140119); - } - if (TX1_finish){ - ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xe88, 0x82140119); - } - cal0_retry = 0; - cal1_retry = 0; - while(1){ - // one shot - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - if (TX0_finish){ - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[0])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[1])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161500); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160cc0); - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000); - ODM_delay_ms(5); //Delay 5ms - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - } - if (TX1_finish){ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[2])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[3])&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - if (pDM_Odm->RFEType == 1){ - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161500); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28160ca0); - } - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_delay_ms(5); //Delay 5ms - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - } - delay_count = 0; - while (1){ - if (!RX0_finish && TX0_finish) - IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if (!RX1_finish && TX1_finish) - IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); - if ((IQK0_ready && IQK1_ready)||(delay_count>20)) - break; - else{ - ODM_delay_ms(1); - delay_count++; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX delay_count = %d\n", delay_count)); - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - RX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); - if (!(RX0_fail || RX0_finish) && TX0_finish){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_IQC_temp[RX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_IQC_temp[RX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", RX0_Average, (RX_IQC_temp[RX0_Average][0])>>21&0x000007ff, RX0_Average, (RX_IQC_temp[RX0_Average][1])>>21&0x000007ff)); -/* - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); -*/ - RX0_Average++; - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("1. RXA_cal_retry = %d\n", cal0_retry)); - cal0_retry++; - if (cal0_retry == 10) - break; - } - if (!(RX1_fail || RX1_finish) && TX1_finish){ - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - RX_IQC_temp[RX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - RX_IQC_temp[RX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", RX1_Average, (RX_IQC_temp[RX1_Average][2])>>21&0x000007ff, RX1_Average, (RX_IQC_temp[RX1_Average][3])>>21&0x000007ff)); -/* - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); -*/ - RX1_Average++; - } - else{ - cal1_retry++; - if (cal1_retry == 10) - break; - } - - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("2. RXA_cal_retry = %d\n", cal0_retry)); - cal0_retry++; - cal1_retry++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms RX IQK Not Ready!!!!!\n")); - if (cal0_retry == 10) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("3. RXA_cal_retry = %d\n", cal0_retry)); - if (RX0_Average >= 2){ - for (i = 0; i < RX0_Average; i++){ - for (ii = i+1; ii >21) - (RX_IQC_temp[ii][0]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_IQC_temp[i][1]>>21) - (RX_IQC_temp[ii][1]>>21); - if (dy < 4 && dy > -4){ - RX_IQC[0]= ((RX_IQC_temp[i][0]>>21) + (RX_IQC_temp[ii][0]>>21))/2; - RX_IQC[1] = ((RX_IQC_temp[i][1]>>21) + (RX_IQC_temp[ii][1]>>21))/2; - RX0_finish = TRUE; - break; - } - } - } - } - } - if (RX1_Average >= 2){ - for (i = 0; i < RX1_Average; i++){ - for (ii = i+1; ii >21) - (RX_IQC_temp[ii][2]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_IQC_temp[i][3]>>21) - (RX_IQC_temp[ii][3]>>21); - if (dy < 4 && dy > -4){ - RX_IQC[2] = ((RX_IQC_temp[i][2]>>21) + (RX_IQC_temp[ii][2]>>21))/2; - RX_IQC[3] = ((RX_IQC_temp[i][3]>>21) + (RX_IQC_temp[ii][3]>>21))/2; - RX1_finish = TRUE; - break; - } - } - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_Average = %d, RX1_Average = %d\n", RX0_Average, RX1_Average)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_finish = %d, RX1_finish = %d\n", RX0_finish, RX1_finish)); - if ((RX0_finish|| !TX0_finish) && (RX1_finish || !TX1_finish) ) - break; - if ((cal0_retry + RX0_Average) >= 10 || (cal1_retry + RX1_Average) >= 10 || RX0_Average == 3 || RX1_Average == 3) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal0_retry)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal1_retry)); - - - // FillIQK Result - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - - if (TX0_finish){ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, TX_IQC[0], TX_IQC[1]); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); - } - - - - if (RX0_finish){ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, RX_IQC[0], RX_IQC[1]); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); - - if (TX1_finish){ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, TX_IQC[2], TX_IQC[3]); - } - else{ - _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); - } - - - - if (RX1_finish){ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, RX_IQC[2], RX_IQC[3]); - } - else{ - _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); - } - - - -} - -#define MACBB_REG_NUM 9 -#define AFE_REG_NUM 12 -#define RF_REG_NUM 3 - -// Maintained by BB James. -VOID -phy_IQCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0xe00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb0, 0xcb4, - 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb0, 0xeb4}; - u4Byte Reg_C1B8, Reg_E1B8; - u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; - u1Byte chnlIdx = GetRightChnlPlaceforIQK(Channel); - - _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - Reg_C1B8 = ODM_Read4Byte(pDM_Odm, 0xcb8); - Reg_E1B8 = ODM_Read4Byte(pDM_Odm, 0xeb8); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); - - _IQK_ConfigureMAC_8812A(pDM_Odm); - _IQK_Tx_8812A(pDM_Odm, chnlIdx); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); - _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); - - _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_Write4Byte(pDM_Odm, 0xcb8, Reg_C1B8); - ODM_Write4Byte(pDM_Odm, 0xeb8, Reg_E1B8); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - - -} - -VOID -phy_LCCalibrate_8812A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; - - //Check continuous TX and Packet TX - u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; - - // Backup RF reg18. - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - if((reg0x914 & 0x70000) != 0) //If contTx, disable all continuous TX. 0x914[18:16] - // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx - // until another packet comes in. To avoid ContTx being turned off, we skip this step. - ;//ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914 & (~0x70000)); - else // If packet Tx-ing, pause Tx. - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); - - -/* - //3 1. Read original RF mode - RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask); - if(is2T) - RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask); - - - //3 2. Set RF mode = standby mode - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, (RF_Amode&0x8FFFF)|0x10000); - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, (RF_Bmode&0x8FFFF)|0x10000); -*/ - - // Enter LCK mode - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp | BIT14); - - //3 3. Read RF reg18 - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - //3 4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); - - ODM_delay_ms(150); // suggest by RFSI Binson - - // Leave LCK mode - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp & ~BIT14); - - //3 Restore original situation - if((reg0x914 & 70000) != 0) //Deal with contisuous TX case, 0x914[18:16] - { - // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx - // until another packet comes in. To avoid ContTx being turned off, we skip this step. - //ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914); - } - else // Deal with Packet TX case - { - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00); - } - - // Recover channel number - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - /* - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, RF_Amode); - if(is2T) - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, RF_Bmode); - */ - -} - - - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - -VOID -phy_ReloadIQKSetting_8812A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte chnlIdx = GetRightChnlPlaceforIQK(Channel); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff0000)>>16); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff0000)>>16); - - if (*pDM_Odm->pBandWidth != 2){ - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); - } - else{ - ODM_Write4Byte(pDM_Odm, 0xce8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4]); - ODM_Write4Byte(pDM_Odm, 0xee8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff0000)>>17); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff)>>1); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff0000)>>17); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff)>>1); - - -} - -VOID -PHY_ResetIQKResult_8812A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); -} - -VOID -phy_IQCalibrate_By_FW_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - - u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(*pDM_Odm->pBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(*pDM_Odm->pBandWidth == ODM_BW20M) - Buf2 = 0x1; - else if(*pDM_Odm->pBandWidth == ODM_BW40M) - Buf2 = 0x1<<1; - else if(*pDM_Odm->pBandWidth == ODM_BW80M) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtPA<<1 | pDM_Odm->SupportInterface<<2 | pDM_Odm->RFEType<<5; - - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Start ==\n")); - pRFCalibrateInfo->IQK_StartTime = 0; - pRFCalibrateInfo->IQK_StartTime = ODM_GetCurrentTime(pDM_Odm); - RT_TRACE(COMP_MP, DBG_LOUD, ("== StartTime: %u\n", pRFCalibrateInfo->IQK_StartTime)); - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); - - -} - -VOID -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - u4Byte counter = 0; - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif -#endif//(MP_DRIVER == 1) - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - //pMgntInfo->RegIQKFWOffload = (u1Byte)ODM_GetBBReg( pDM_Odm, 0x444, BIT8); -#if MP_DRIVER == 1 - - // Add to determine IQK ON/OFF in certain case, Suggested by Cheng. - if (!pHalData->IQK_MP_Switch) - return; - - - if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) -#endif - { - - //3 == FW IQK == - if(pMgntInfo->RegIQKFWOffload) - { - if ( ! pRFCalibrateInfo->bIQKInProgress) - { - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - - phy_IQCalibrate_By_FW_8812A(pDM_Odm); - } - else - { - for(counter = 0; counter < 10; counter++){ - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); - delay_ms(50); - if ( ! pRFCalibrateInfo->bIQKInProgress) - { - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); - break; - } - } - - if (pRFCalibrateInfo->bIQKInProgress) - { - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - } - else - { - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - phy_IQCalibrate_By_FW_8812A(pDM_Odm); - } - - - } - } - //3 == Driver IQK == - else - { - if ( ! pRFCalibrateInfo->bIQKInProgress) - { - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - - //RT_TRACE(COMP_P2P, DBG_LOUD, ("1 %s: KeGetCurrentIrql(): %d\n", __FUNCTION__, KeGetCurrentIrql())); - phy_IQCalibrate_8812A(pDM_Odm, pHalData->CurrentChannel); - //RT_TRACE(COMP_P2P, DBG_LOUD, ("3 %s: KeGetCurrentIrql(): %d\n", __FUNCTION__, KeGetCurrentIrql())); - - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - } - } - - - } - -} - - -VOID -PHY_LCCalibrate_8812A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8812A\n")); - -#if (MP_DRIVER == 1) - phy_LCCalibrate_8812A(pDM_Odm, TRUE); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8812A\n")); - -} - -VOID phy_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - -#endif - - if (IS_HARDWARE_TYPE_8821(pAdapter)) - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x1); //Main - else - ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x2); //Aux - } - else if (pDM_Odm->SupportICType & ODM_RTL8812) - { - if (pHalData->RFEType == 5) - { - if(bMain) { - // WiFi - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } else { - // BT - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } - } - else if (pHalData->RFEType == 1) - { // <131224, VincentL> When RFEType == 1 also Set 0x900, suggested by RF Binson. - if(bMain) { - // WiFi - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } else { - // BT - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); - ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); - } - } - - } - -} -VOID PHY_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - -#if DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); - -#endif -} - -s4Byte -_Sign( - IN u4Byte Number - ) -{ - if ((Number & BIT10) == BIT10) {// Negative - Number &= (~0xFFFFFC00); // [9:0] - Number = ~Number; - Number &= (~0xFFFFFC00); // [9:0] - Number += 1; - Number &= (~0xFFFFF800); // [10:0] - return -1 * Number; - } else { // Positive - return (s4Byte)Number; - } -} - - -VOID -_DPK_MacBBBackup_PathA( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN OUT pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - BackupRegData[i] = ODM_Read4Byte(pDM_Odm, BackupRegAddr[i]); -} -VOID -_DPK_MacBBRestore_PathA( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - ODM_Write4Byte(pDM_Odm, BackupRegAddr[i], BackupRegData[i]); -} - - -VOID -_DPK_RFBackup_PathA( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN ODM_RF_RADIO_PATH_E RFPath, - IN OUT pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - BackupRegData[i] = ODM_GetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask); -} - -VOID -_DPK_RFRestore_PathA( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN ODM_RF_RADIO_PATH_E RFPath, - IN pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - ODM_SetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask, BackupRegData[i]); -} - - - -s4Byte -_ComputeLoopBackGain_PathA( - IN PDM_ODM_T pDM_Odm -) -{ - // compute loopback gain - // ­pºâtmpLBGain ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.10 - // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, - // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, - // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, - // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, - // Á|¨Ò5, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, - u4Byte reg0xD00_26_16 = ODM_GetBBReg(pDM_Odm, 0xD00, 0x7FF0000); - u4Byte reg0xD00_10_0 = ODM_GetBBReg(pDM_Odm, 0xD00, 0x7FF); - - s4Byte tmpLBGain = _Sign(reg0xD00_26_16)*_Sign(reg0xD00_26_16) + _Sign(reg0xD00_10_0)*_Sign(reg0xD00_10_0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _ComputeLoopBackGain_PathA, tmpLBGain = 0x%X\n", tmpLBGain)); - - return tmpLBGain; -} - - -BOOLEAN -_FineTuneLoopBackGain_PathA( - IN PDM_ODM_T pDM_Odm, - IN u4Byte DpkTxAGC - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - u4Byte rf0x64_orig = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7); - u4Byte rf0x64_new = rf0x64_orig; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _FineTuneLoopBackGain\n")); - - do { - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, DpkTxAGC); - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); - - tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); - - if ((rf0x64_new == (BIT2|BIT1|BIT0)) || (rf0x64_new == 0)) { - //printf('DPK Phase 1 failed'); - pRFCalibrateInfo->bDPKFail = TRUE; - break; - //Go to DPK Phase 5 - } else { - if (tmpLBGain < 263390) {// fine tune loopback path gain: newReg64[2:0] = reg64[2:0] - 3b'001 - rf0x64_new -= 1; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7, rf0x64_new); - - } else if (tmpLBGain > 661607) {// fine tune loopback path gain: newReg64 [2:0] = reg64[2:0] + 3b'001 - rf0x64_new += 1; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7, rf0x64_new); - - } else { - pRFCalibrateInfo->bDPKFail = FALSE; - } - } - - } while (tmpLBGain < 263390 || 661607 < tmpLBGain); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _FineTuneLoopBackGain\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - - -VOID -_DPK_Init_PathA( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_Init\n")); - - //TX pause - ODM_Write1Byte(pDM_Odm, 0x522, 0x7f); - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - // AFE setting - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - // external TRSW ¤Á¨ì T - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x01000077); - - // hardware 3-wire off - ODM_Write4Byte(pDM_Odm, 0xc00, 0x00000004); - - // CCA off - ODM_Write4Byte(pDM_Odm, 0x838, 0x16C89B4c); - - //90c[15]: dac fifo reset by CSWU - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - - // r_gothrough_iqkdpk - ODM_Write4Byte(pDM_Odm, 0xc94, 0x0100005D); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // IQK Amp off - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - - // tx_amp - ODM_Write4Byte(pDM_Odm, 0xc98, 0x41382e21); - ODM_Write4Byte(pDM_Odm, 0xc9c, 0x5b554f48); - ODM_Write4Byte(pDM_Odm, 0xca0, 0x6f6b6661); - ODM_Write4Byte(pDM_Odm, 0xca4, 0x817d7874); - ODM_Write4Byte(pDM_Odm, 0xca8, 0x908c8884); - ODM_Write4Byte(pDM_Odm, 0xcac, 0x9d9a9793); - ODM_Write4Byte(pDM_Odm, 0xcb0, 0xaaa7a4a1); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0xb6b3b0ad); - - // tx_inverse - ODM_Write4Byte(pDM_Odm, 0xc40, 0x02ce03e9); - ODM_Write4Byte(pDM_Odm, 0xc44, 0x01fd0249); - ODM_Write4Byte(pDM_Odm, 0xc48, 0x01a101c9); - ODM_Write4Byte(pDM_Odm, 0xc4c, 0x016a0181); - ODM_Write4Byte(pDM_Odm, 0xc50, 0x01430155); - ODM_Write4Byte(pDM_Odm, 0xc54, 0x01270135); - ODM_Write4Byte(pDM_Odm, 0xc58, 0x0112011c); - ODM_Write4Byte(pDM_Odm, 0xc5c, 0x01000108); - ODM_Write4Byte(pDM_Odm, 0xc60, 0x00f100f8); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x00e500eb); - ODM_Write4Byte(pDM_Odm, 0xc68, 0x00db00e0); - ODM_Write4Byte(pDM_Odm, 0xc6c, 0x00d100d5); - ODM_Write4Byte(pDM_Odm, 0xc70, 0x00c900cd); - ODM_Write4Byte(pDM_Odm, 0xc74, 0x00c200c5); - ODM_Write4Byte(pDM_Odm, 0xc78, 0x00bb00be); - ODM_Write4Byte(pDM_Odm, 0xc7c, 0x00b500b8); - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - pRFCalibrateInfo->bDPKFail = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_Init\n")); - -} - - -BOOLEAN -_DPK_AdjustRFGain_PathA( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGain\n")); - - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x50bfc); - // Attn: A mode @ reg64[2:0], G mode @ reg56 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, bRFRegOffsetMask, 0x19aac); - // PGA gain: RF reg8f[14:13] - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11838000); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0xFFF000, 0x100); // ±Ncd4[23:12] §ï¦¨ h'100, ¨ä¥¦¦ì¤¸½Ð«O¯d­ì­È¤£­n¼g¨ì - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // read back Loopback Gain - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x09000000); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); - - tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); - - // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 - if (tmpLBGain < 263390) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8e001); - _FineTuneLoopBackGain_PathA(pDM_Odm, 0x50bfc); - - } - else if (tmpLBGain > 661607) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); - _FineTuneLoopBackGain_PathA(pDM_Odm, 0x50bfc); - } - else - pRFCalibrateInfo->bDPKFail = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGain\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - - -VOID -_DPK_GainLossToFindTxAGC_PathA( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte Reg0xD00 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_GainLossToFindTxAGC\n")); - - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x50bfc); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. - // dB_sel = b'000 ' 1.0 dB PA gain loss - // dB_sel = b'001 ' 1.5 dB PA gain loss - // dB_sel = b'010 ' 2.0 dB PA gain loss - // dB_sel = b'011 ' 2.5 dB PA gain loss - // dB_sel = b'100 ' 3.0 dB PA gain loss - // dB_sel = b'101 ' 3.5 dB PA gain loss - // dB_sel = b'110 ' 4.0 dB PA gain loss - ODM_Write4Byte(pDM_Odm, 0xc20, 0x00002000); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x148b8000); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0401f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // read back Loopback Gain - // ¥i¥H¦b d00[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w - // Ū¦^d00[3:0] = h'1 ' Tx AGC = h'13 - // Ū¦^d00[3:0] = h'2 ' Tx AGC = h'14 - // Ū¦^d00[3:0] = h'3 ' Tx AGC = h'15 - // Ū¦^d00[3:0] = h'4 ' Tx AGC = h'16 - // Ū¦^d00[3:0] = h'5 ' Tx AGC = h'17 - // Ū¦^d00[3:0] = h'6 ' Tx AGC = h'18 - // Ū¦^d00[3:0] = h'7 ' Tx AGC = h'19 - // Ū¦^d00[3:0] = h'8 ' Tx AGC = h'1a - // Ū¦^d00[3:0] = h'9 ' Tx AGC = h'1b - // Ū¦^d00[3:0] = h'a ' Tx AGC = h'1c - // - Reg0xD00 = ODM_Read4Byte(pDM_Odm, 0xd00); - switch (ODM_Read4Byte(pDM_Odm, 0xd00) & (BIT3|BIT2|BIT1|BIT0)) - { - case 0x0: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x2; break; - case 0x1: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x3; break; - case 0x2: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x4; break; - case 0x3: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x5; break; - case 0x4: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x6; break; - case 0x5: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x7; break; - case 0x6: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x8; break; - case 0x7: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x9; break; - case 0x8: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xa; break; - case 0x9: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xb; break; - case 0xa: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xc; break; - } - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_GainLossToFindTxAGC\n")); -} - - -BOOLEAN -_DPK_AdjustRFGainByFoundTxAGC_PathA -( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGainByFoundTxAGC\n")); - - // RF setting, ­«·s³]©wRF reg00, Á|¨Ò¥ÎDPK Phase 2±o¨ìªº d00[3:0] = 0x6 ' TX AGC= 0x18 ' RF reg00[4:0] = 0x18 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); - // Attn: A mode @ reg64[2:0], G mode @ reg56 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, bRFRegOffsetMask, 0x19aac); - // PGA gain: RF reg8f[14:13] - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11838000); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); - - - tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); - - if (tmpLBGain < 263390) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8e001); - _FineTuneLoopBackGain_PathA(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); - } - else if (tmpLBGain > 661607) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); - _FineTuneLoopBackGain_PathA(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); - } - else - pRFCalibrateInfo->bDPKFail = FALSE;//Go to DPK Phase 4 - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGainByFoundTxAGC\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - -VOID -_DPK_DoAutoDPK_PathA( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte tmpLBGain = 0, reg0xD00 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_DoAutoDPK\n")); - - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - // RF setting, ¦¹³BRF reg00, »P DPK Phase 3 ¤@­P - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); - // Baseband Data Rate setting - ODM_Write4Byte(pDM_Odm, 0xc20, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc24, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc28, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc2c, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc30, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc34, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc38, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc3c, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc40, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc44, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc48, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xc4c, 0x3c3c3c3c); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76C9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x400C5599); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11938080); //0xcc4[9:4]= DPk fail threshold - - if ( 36 <= *(pDM_Odm->pChannel) && *(pDM_Odm->pChannel) <= 53)//Channelchannel at low band) - // r_agc - ODM_Write4Byte(pDM_Odm, 0xcbc, 0x00022a1f); - else - // r_agc - ODM_Write4Byte(pDM_Odm, 0xcbc, 0x00009dbf); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); // TODO: 0xC90(rA_LSSIWrite_Jaguar) can not be overwritten. - - // one shot - ODM_Write4Byte(pDM_Odm, 0xcc8, 0xc00c5599); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x400c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - // T-meter RFReg42[17] = 1 to enable read T-meter, [15:10] ' T-meter value - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, BIT17, 1); - pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, 0xFC00); // Ū¥X42[15:10] ­È¨Ã¦s¨ìÅܼÆTMeter - DbgPrint("pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] = 0x%X\n", pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33D8D); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - // read back dp_fail report - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - //dp_fail³o­Óbit¦bd00[6], ·í d00[6] = 1, ªí¥Ücalibration¥¢±Ñ. - reg0xD00 = ODM_Read4Byte(pDM_Odm, 0xd00); - - if ((reg0xD00 & BIT6) == BIT6) { - //printf('DPK fail') - pRFCalibrateInfo->bDPKFail = TRUE; - //Go to DPK Phase 5 - } else { - //printf('DPK success') - } - - - // read back - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0201f01f); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0c000000); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - // ­pºâtmpGainLoss ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.9 - // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, - // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, - // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, - // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, - // Á|¨Ò4, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, - tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); - - - // Gain Scaling - if (227007 < tmpLBGain) - pRFCalibrateInfo->DpkGain = 0x43ca43ca; - else if (214309 < tmpLBGain && tmpLBGain <= 227007) - pRFCalibrateInfo->DpkGain = 0x45c545c5; - else if (202321 < tmpLBGain && tmpLBGain <= 214309) - pRFCalibrateInfo->DpkGain = 0x47cf47cf; - else if (191003 < tmpLBGain && tmpLBGain <= 202321) - pRFCalibrateInfo->DpkGain = 0x49e749e7; - else if (180318 < tmpLBGain && tmpLBGain <= 191003) - pRFCalibrateInfo->DpkGain = 0x4c104c10; - else if (170231 < tmpLBGain && tmpLBGain <= 180318) - pRFCalibrateInfo->DpkGain = 0x4e494e49; - else if (160709 < tmpLBGain && tmpLBGain <= 170231) - pRFCalibrateInfo->DpkGain = 0x50925092; - else if (151719 < tmpLBGain && tmpLBGain <= 160709) - pRFCalibrateInfo->DpkGain = 0x52ec52ec; - else if (151719 <= tmpLBGain) - pRFCalibrateInfo->DpkGain = 0x55585558; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_DoAutoDPK\n")); -} - - -VOID -_DPK_EnableDP_PathA( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_EnableDP\n")); - - // [31] = 1 --> switch to page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // enable IQC matrix --> ¦]¬° BB «H¸¹·|¥ý¸g¹L predistortion module, ¤~¸g¹L IQC matrix ¨ì DAC ¥´¥X¥h - // ©Ò¥H­n¥ý enable predistortion module {c90[7] = 1 (enable_predis) cc4[18] = 1 (½T©wÅý IQK/DPK module ¦³clock), cc8[29] = 1 (¤@­ÓIQK/DPK module ¸Ìªºmux, ½T»{ data path ¨«IQK/DPK)} - ODM_Write4Byte(pDM_Odm, 0xc90, 0x0000f098); - ODM_Write4Byte(pDM_Odm, 0xc94, 0x776d9f84); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - // r_bnd - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x000fffff); - - if (pRFCalibrateInfo->bDPKFail) - { - // cc4[29] = 1 (bypass DP LUT) - ODM_Write4Byte(pDM_Odm, 0xc98, 0x40004000); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x28840000); - } - else - { - ODM_Write4Byte(pDM_Odm, 0xc98, pRFCalibrateInfo->DpkGain); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x08840000); - - // PWSF - // ¼gPWSF table in 1st SRAM for PA = 11 use - ODM_Write4Byte(pDM_Odm, 0xc20, 0x00000800); - - //******************************************************* - //0xce4[0]¬Owrite enable¡A0xce4[7:1]¬Oaddress¡A0xce4[15:8]©M0xce4[23:16]¹ïÀ³¨ìTX index¡A - //­Y¦ì¸m¬°0(0xce4[7:1] = 0x0)¦¹®É0xce4[15:8]¹ïÀ³¨ìªºTX RF index ¬O0x1f,¡A - //0xce4[23:16]¹ïÀ³¨ìªº¬O0x1e¡A­Y¦ì¸m¬°1(0xce4[7:1] = 0x1)¡A¦¹®É0xce4 [15:8]¹ïÀ³¨ì0x1d¡A - //0xce4[23:16]¹ïÀ³0x1c¡A¨ä¥L¨Ì¦¹Ãþ±À¡A¨C­ÓdataÄæ¦ì³£¬O¬Û®t1dB¡C­Ygainloss§ä¨ìªºRF TX index=0x18¡A - //«h¦b0xce4 address¹ïÀ³¨ì0x18ªº¦a¤è­n¶ñ0x40(¤]´N¬O0dB)¡A¨ä¥L«h·Ó¤U­±tableªº¶¶§Ç¨C®æ1dB¨Ì§Ç±Æ¦C - //±N©Ò¦³ªº0xce4cªºdataÄæ¦ì³£¶ñ¤J¬Û¹ïÀ³ªº­È¡C - //*************************************************************// - - { - const s4Byte LEN = 25; - u4Byte baseIdx = 6; // 0 dB: 0x40 - u4Byte TablePWSF[] = { - 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40/* 0 dB */, - 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, - 0x0d, 0x0a, 0x08, 0x06, 0x05, 0x04, - 0x03, 0x03, 0x02, 0x02, 0x01, 0x01 - }; - - u4Byte centerTxIdx = pRFCalibrateInfo->DpkTxAGC & 0x1F; - u4Byte centerAddr = (0x1F-centerTxIdx) / 2; - s4Byte i = 0, j = 0, value = 0, startIdx = 0; - - // Upper - startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+1 : baseIdx); - - for (i = startIdx, j = 0; (centerAddr-j+1) >= 1; i -= 2, j++) { - if (i-1 < 0) - value = (TablePWSF[0] << 16) | (TablePWSF[0] << 8) | ((centerAddr-j) << 1) | 0x1; - else - value = (TablePWSF[i] << 16) | (TablePWSF[i-1] << 8) | ((centerAddr-j) << 1) | 0x1; - - ODM_Write4Byte(pDM_Odm, 0xce4, value); - ODM_Write1Byte(pDM_Odm, 0xce4, 0x0); //write disable - } - - // Lower - startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+2 : baseIdx+1); - centerAddr++; // Skip centerTxIdx - for (i = startIdx, j = 0; (centerAddr+j) < 16; i += 2, j++) { // Total: 16*2 = 32 values (Upper+Lower) - if (i+1 >= LEN) - value = (TablePWSF[LEN-1] << 16) | (TablePWSF[LEN-1] << 8) | ((centerAddr+j) << 1) | 0x1; - else - value = (TablePWSF[i+1] << 16) | (TablePWSF[i] << 8) | ((centerAddr+j) << 1) | 0x1; - ODM_Write4Byte(pDM_Odm, 0xce4, value); - ODM_Write1Byte(pDM_Odm, 0xce4, 0x0); //write disable - } - } - } - // [31] = 0 --> switch to page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_EnableDP\n")); - -} - - - - - -VOID -phy_DPCalibrate_PathA_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte backupMacBBRegAddrs[] = { - 0xC60, 0xC64, 0xC68, 0x82C, 0x838, 0x90C, 0x522, 0xC00, 0xC20, 0xC24, // 10 - 0xC28, 0xC2C, 0xC30, 0xC34, 0xC38, 0xC3C, 0xC40, 0xC44, 0xC48, 0xC4C, // 20 - 0xC94, 0xCB0, 0xCB4 - }; - u4Byte backupRFRegAddrs[] = {0x00, 0x64, 0x8F}; - - u4Byte backupMacBBRegData[sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)]; - u4Byte backupRFRegData_A[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; - //u4Byte backupRFRegData_B[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; - - - _DPK_MacBBBackup_PathA(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); - _DPK_RFBackup_PathA(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_A, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); - - _DPK_Init_PathA(pDM_Odm); - - if (_DPK_AdjustRFGain_PathA(pDM_Odm)) { // Phase 1 - _DPK_GainLossToFindTxAGC_PathA(pDM_Odm); // Phase 2 - if (_DPK_AdjustRFGainByFoundTxAGC_PathA(pDM_Odm)) // Phase 3 - _DPK_DoAutoDPK_PathA(pDM_Odm); // Phase 4 - } - _DPK_EnableDP_PathA(pDM_Odm); // Phase 5 - - _DPK_MacBBRestore_PathA(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); - _DPK_RFRestore_PathA(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_A, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); -} - - -VOID -_DPK_MacBBBackup_PathB( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN OUT pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - BackupRegData[i] = ODM_Read4Byte(pDM_Odm, BackupRegAddr[i]); -} - -VOID -_DPK_MacBBRestore_PathB( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - ODM_Write4Byte(pDM_Odm, BackupRegAddr[i], BackupRegData[i]); -} - - -VOID -_DPK_RFBackup_PathB( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN ODM_RF_RADIO_PATH_E RFPath, - IN OUT pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - BackupRegData[i] = ODM_GetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask); -} - -VOID -_DPK_RFRestore_PathB( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte BackupRegAddr, - IN ODM_RF_RADIO_PATH_E RFPath, - IN pu4Byte BackupRegData, - IN u4Byte Number - ) -{ - u4Byte i; - - for (i = 0; i < Number; i++) - ODM_SetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask, BackupRegData[i]); -} - - - -s4Byte -_ComputeLoopBackGain_PathB( - IN PDM_ODM_T pDM_Odm -) -{ - // compute loopback gain - // ­pºâtmpLBGain ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.10 - // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, - // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, - // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, - // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, - // Á|¨Ò5, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, - u4Byte reg0xD40_26_16 = ODM_GetBBReg(pDM_Odm, 0xD40, 0x7FF0000); - u4Byte reg0xD40_10_0 = ODM_GetBBReg(pDM_Odm, 0xD40, 0x7FF); - - s4Byte tmpLBGain = _Sign(reg0xD40_26_16)*_Sign(reg0xD40_26_16) + _Sign(reg0xD40_10_0)*_Sign(reg0xD40_10_0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _ComputeLoopBackGain_PathB, tmpLBGain = 0x%X\n", tmpLBGain)); - - return tmpLBGain; -} - - -BOOLEAN -_FineTuneLoopBackGain_PathB( - IN PDM_ODM_T pDM_Odm, - IN u4Byte DpkTxAGC - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - u4Byte rf0x64_orig = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7); - u4Byte rf0x64_new = rf0x64_orig; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _FineTuneLoopBackGain_PathB\n")); - - do { - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, DpkTxAGC); - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); - - tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); - - if ((rf0x64_new == (BIT2|BIT1|BIT0)) || (rf0x64_new == 0)) { - //printf('DPK Phase 1 failed'); - pRFCalibrateInfo->bDPKFail = TRUE; - break; - //Go to DPK Phase 5 - } else { - if (tmpLBGain < 263390) {// fine tune loopback path gain: newReg64[2:0] = reg64[2:0] - 3b'001 - rf0x64_new -= 1; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7, rf0x64_new); - - } else if (tmpLBGain > 661607) {// fine tune loopback path gain: newReg64 [2:0] = reg64[2:0] + 3b'001 - rf0x64_new += 1; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7, rf0x64_new); - - } else { - pRFCalibrateInfo->bDPKFail = FALSE; - } - } - - } while (tmpLBGain < 263390 || 661607 < tmpLBGain); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _FineTuneLoopBackGain_PathB\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - - -VOID -_DPK_Init_PathB( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_Init\n")); - - //TX pause - ODM_Write1Byte(pDM_Odm, 0x522, 0x7f); - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - // AFE setting - ODM_Write4Byte(pDM_Odm, 0xc68, 0x59791979); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); - - // external TRSW ¤Á¨ì T - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x01000077); - - // hardware 3-wire off - ODM_Write4Byte(pDM_Odm, 0xe00, 0x00000004); - - // CCA off - ODM_Write4Byte(pDM_Odm, 0x838, 0x16C89B4c); - - //90c[15]: dac fifo reset by CSWU - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - - // r_gothrough_iqkdpk - ODM_Write4Byte(pDM_Odm, 0xe94, 0x0100005D); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // IQK Amp off - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - - // tx_amp - ODM_Write4Byte(pDM_Odm, 0xe98, 0x41382e21); - ODM_Write4Byte(pDM_Odm, 0xe9c, 0x5b554f48); - ODM_Write4Byte(pDM_Odm, 0xea0, 0x6f6b6661); - ODM_Write4Byte(pDM_Odm, 0xea4, 0x817d7874); - ODM_Write4Byte(pDM_Odm, 0xea8, 0x908c8884); - ODM_Write4Byte(pDM_Odm, 0xeac, 0x9d9a9793); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0xaaa7a4a1); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0xb6b3b0ad); - - // tx_inverse - ODM_Write4Byte(pDM_Odm, 0xe40, 0x02ce03e9); - ODM_Write4Byte(pDM_Odm, 0xe44, 0x01fd0249); - ODM_Write4Byte(pDM_Odm, 0xe48, 0x01a101c9); - ODM_Write4Byte(pDM_Odm, 0xe4c, 0x016a0181); - ODM_Write4Byte(pDM_Odm, 0xe50, 0x01430155); - ODM_Write4Byte(pDM_Odm, 0xe54, 0x01270135); - ODM_Write4Byte(pDM_Odm, 0xe58, 0x0112011c); - ODM_Write4Byte(pDM_Odm, 0xe5c, 0x01000108); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x00f100f8); - ODM_Write4Byte(pDM_Odm, 0xe64, 0x00e500eb); - ODM_Write4Byte(pDM_Odm, 0xe68, 0x00db00e0); - ODM_Write4Byte(pDM_Odm, 0xe6c, 0x00d100d5); - ODM_Write4Byte(pDM_Odm, 0xe70, 0x00c900cd); - ODM_Write4Byte(pDM_Odm, 0xe74, 0x00c200c5); - ODM_Write4Byte(pDM_Odm, 0xe78, 0x00bb00be); - ODM_Write4Byte(pDM_Odm, 0xe7c, 0x00b500b8); - - // reg82c[31] = b'0, ¤Á´«¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - pRFCalibrateInfo->bDPKFail = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_Init\n")); - -} - - -BOOLEAN -_DPK_AdjustRFGain_PathB( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGain\n")); - - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x50bfc); - // Attn: A mode @ reg64[2:0], G mode @ reg56 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, bRFRegOffsetMask, 0x19aac); - // PGA gain: RF reg8f[14:13] - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x11838000); - ODM_SetBBReg(pDM_Odm, 0xed4, 0xFFF000, 0x100); // ±Ncd4[23:12] §ï¦¨ h'100, ¨ä¥¦¦ì¤¸½Ð«O¯d­ì­È¤£­n¼g¨ì - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // read back Loopback Gain - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x09000000); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); - - tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); - - // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 - if (tmpLBGain < 263390) - { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8e001); - _FineTuneLoopBackGain_PathB(pDM_Odm, 0x50bfc); - - } - else if (tmpLBGain > 661607) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); - _FineTuneLoopBackGain_PathB(pDM_Odm, 0x50bfc); - } - else - pRFCalibrateInfo->bDPKFail = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGain\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - - -VOID -_DPK_GainLossToFindTxAGC_PathB( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte Reg0xD40 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_GainLossToFindTxAGC\n")); - - // RF setting - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x50bfc); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. - // dB_sel = b'000 ' 1.0 dB PA gain loss - // dB_sel = b'001 ' 1.5 dB PA gain loss - // dB_sel = b'010 ' 2.0 dB PA gain loss - // dB_sel = b'011 ' 2.5 dB PA gain loss - // dB_sel = b'100 ' 3.0 dB PA gain loss - // dB_sel = b'101 ' 3.5 dB PA gain loss - // dB_sel = b'110 ' 4.0 dB PA gain loss - ODM_Write4Byte(pDM_Odm, 0xe20, 0x00002000); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x148b8000); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0401f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // read back Loopback Gain - // ¥i¥H¦b d40[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w - // Ū¦^d00[3:0] = h'1 ' Tx AGC = h'13 - // Ū¦^d00[3:0] = h'2 ' Tx AGC = h'14 - // Ū¦^d00[3:0] = h'3 ' Tx AGC = h'15 - // Ū¦^d00[3:0] = h'4 ' Tx AGC = h'16 - // Ū¦^d00[3:0] = h'5 ' Tx AGC = h'17 - // Ū¦^d00[3:0] = h'6 ' Tx AGC = h'18 - // Ū¦^d00[3:0] = h'7 ' Tx AGC = h'19 - // Ū¦^d00[3:0] = h'8 ' Tx AGC = h'1a - // Ū¦^d00[3:0] = h'9 ' Tx AGC = h'1b - // Ū¦^d00[3:0] = h'a ' Tx AGC = h'1c - // - Reg0xD40 = ODM_Read4Byte(pDM_Odm, 0xd40); - switch (ODM_Read4Byte(pDM_Odm, 0xd40) & (BIT3|BIT2|BIT1|BIT0)) - { - case 0x0: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x2; break; - case 0x1: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x3; break; - case 0x2: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x4; break; - case 0x3: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x5; break; - case 0x4: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x6; break; - case 0x5: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x7; break; - case 0x6: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x8; break; - case 0x7: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x9; break; - case 0x8: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xa; break; - case 0x9: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xb; break; - case 0xa: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xc; break; - } - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_GainLossToFindTxAGC\n")); -} - - -BOOLEAN -_DPK_AdjustRFGainByFoundTxAGC_PathB -( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - s4Byte tmpLBGain = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGainByFoundTxAGC\n")); - - // RF setting, ­«·s³]©wRF reg00, Á|¨Ò¥ÎDPK Phase 2±o¨ìªº d40[3:0] = 0x6 ' TX AGC= 0x18 ' RF reg00[4:0] = 0x18 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); - // Attn: A mode @ reg64[2:0], G mode @ reg56 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, bRFRegOffsetMask, 0x19aac); - // PGA gain: RF reg8f[14:13] - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x11838000); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); - - // one shot - ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); - - - tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); - - if (tmpLBGain < 263390) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8e001); - _FineTuneLoopBackGain_PathB(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); - } - else if (tmpLBGain > 661607) - { - // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); - _FineTuneLoopBackGain_PathB(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); - } - else - pRFCalibrateInfo->bDPKFail = FALSE;//Go to DPK Phase 4 - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGainByFoundTxAGC\n")); - - return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; - -} - - -VOID -_DPK_DoAutoDPK_PathB( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u4Byte tmpLBGain = 0, reg0xD40 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_DoAutoDPK\n")); - - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - // RF setting, ¦¹³BRF reg00, »P DPK Phase 3 ¤@­P - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); - // Baseband Data Rate setting - ODM_Write4Byte(pDM_Odm, 0xe20, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe24, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe28, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe2c, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe30, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe34, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe38, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe3c, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe40, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe44, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe48, 0x3c3c3c3c); - ODM_Write4Byte(pDM_Odm, 0xe4c, 0x3c3c3c3c); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // DPK setting - ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76C9f84); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x400C5599); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x11938080); //0xec4[9:4]= DPk fail threshold - - if ( 36 <= *(pDM_Odm->pChannel) && *(pDM_Odm->pChannel) <= 53)//Channelchannel at low band) - // r_agc - ODM_Write4Byte(pDM_Odm, 0xebc, 0x00022a1f); - else - // r_agc - ODM_Write4Byte(pDM_Odm, 0xebc, 0x00009dbf); - - // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); // TODO: 0xe90(rA_LSSIWrite_Jaguar) can not be overwritten. - - // one shot - ODM_Write4Byte(pDM_Odm, 0xec8, 0xc00c5599); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x400c5599); - // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ - delay_ms(50); - - // reg82c[31] = 0 --> ¤Á¨ì page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - // T-meter RFReg42[17] = 1 to enable read T-meter, [15:10] ' T-meter value - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, BIT17, 1); - pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, 0xFC00); // Ū¥X42[15:10] ­È¨Ã¦s¨ìÅܼÆTMeter - DbgPrint("pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] = 0x%X\n", pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33D8D); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - // read back dp_fail report - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); - //dp_fail³o­Óbit¦bd40[6], ·í d40[6] = 1, ªí¥Ücalibration¥¢±Ñ. - reg0xD40 = ODM_Read4Byte(pDM_Odm, 0xd40); - - if ((reg0xD40 & BIT6) == BIT6) { - //printf('DPK fail') - pRFCalibrateInfo->bDPKFail = TRUE; - //Go to DPK Phase 5 - } else { - //printf('DPK success') - } - - - // read back - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0201f01f); - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0c000000); - - // reg82c[31] = 1 --> ¤Á¨ì page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - // ­pºâtmpGainLoss ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.9 - // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, - // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, - // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, - // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, - // Á|¨Ò4, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, - tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); - - - // Gain Scaling - if (227007 < tmpLBGain) - pRFCalibrateInfo->DpkGain = 0x43ca43ca; - else if (214309 < tmpLBGain && tmpLBGain <= 227007) - pRFCalibrateInfo->DpkGain = 0x45c545c5; - else if (202321 < tmpLBGain && tmpLBGain <= 214309) - pRFCalibrateInfo->DpkGain = 0x47cf47cf; - else if (191003 < tmpLBGain && tmpLBGain <= 202321) - pRFCalibrateInfo->DpkGain = 0x49e749e7; - else if (180318 < tmpLBGain && tmpLBGain <= 191003) - pRFCalibrateInfo->DpkGain = 0x4c104c10; - else if (170231 < tmpLBGain && tmpLBGain <= 180318) - pRFCalibrateInfo->DpkGain = 0x4e494e49; - else if (160709 < tmpLBGain && tmpLBGain <= 170231) - pRFCalibrateInfo->DpkGain = 0x50925092; - else if (151719 < tmpLBGain && tmpLBGain <= 160709) - pRFCalibrateInfo->DpkGain = 0x52ec52ec; - else if (151719 <= tmpLBGain) - pRFCalibrateInfo->DpkGain = 0x55585558; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_DoAutoDPK\n")); -} - - -VOID -_DPK_EnableDP_PathB( - IN PDM_ODM_T pDM_Odm - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_EnableDP\n")); - - // [31] = 1 --> switch to page C1 - ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); - - // enable IQC matrix --> ¦]¬° BB «H¸¹·|¥ý¸g¹L predistortion module, ¤~¸g¹L IQC matrix ¨ì DAC ¥´¥X¥h - // ©Ò¥H­n¥ý enable predistortion module {c90[7] = 1 (enable_predis) cc4[18] = 1 (½T©wÅý IQK/DPK module ¦³clock), cc8[29] = 1 (¤@­ÓIQK/DPK module ¸Ìªºmux, ½T»{ data path ¨«IQK/DPK)} - ODM_Write4Byte(pDM_Odm, 0xe90, 0x0000f098); - ODM_Write4Byte(pDM_Odm, 0xe94, 0x776d9f84); - ODM_Write4Byte(pDM_Odm, 0xec8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); - // r_bnd - ODM_Write4Byte(pDM_Odm, 0xeb8, 0x000fffff); - - if (pRFCalibrateInfo->bDPKFail) - { - // cc4[29] = 1 (bypass DP LUT) - ODM_Write4Byte(pDM_Odm, 0xe98, 0x40004000); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x28840000); - } - else - { - ODM_Write4Byte(pDM_Odm, 0xe98, pRFCalibrateInfo->DpkGain); - ODM_Write4Byte(pDM_Odm, 0xec4, 0x08840000); - - // PWSF - // ¼gPWSF table in 1st SRAM for PA = 11 use - ODM_Write4Byte(pDM_Odm, 0xe20, 0x00000800); - - //******************************************************* - //0xee4[0]¬Owrite enable¡A0xee4[7:1]¬Oaddress¡A0xee4[15:8]©M0xee4[23:16]¹ïÀ³¨ìTX index¡A - //­Y¦ì¸m¬°0(0xee4[7:1] = 0x0)¦¹®É0xee4[15:8]¹ïÀ³¨ìªºTX RF index ¬O0x1f,¡A - //0xee4[23:16]¹ïÀ³¨ìªº¬O0x1e¡A­Y¦ì¸m¬°1(0xee4[7:1] = 0x1)¡A¦¹®É0xee4 [15:8]¹ïÀ³¨ì0x1d¡A - //0xee4[23:16]¹ïÀ³0x1c¡A¨ä¥L¨Ì¦¹Ãþ±À¡A¨C­ÓdataÄæ¦ì³£¬O¬Û®t1dB¡C­Ygainloss§ä¨ìªºRF TX index=0x18¡A - //«h¦b0xee4 address¹ïÀ³¨ì0x18ªº¦a¤è­n¶ñ0x40(¤]´N¬O0dB)¡A¨ä¥L«h·Ó¤U­±tableªº¶¶§Ç¨C®æ1dB¨Ì§Ç±Æ¦C - //±N©Ò¦³ªº0xee4cªºdataÄæ¦ì³£¶ñ¤J¬Û¹ïÀ³ªº­È¡C - //*************************************************************// - - { - const s4Byte LEN = 25; - u4Byte baseIdx = 6; // 0 dB: 0x40 - u4Byte TablePWSF[] = { - 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40/* 0 dB */, - 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, - 0x0d, 0x0a, 0x08, 0x06, 0x05, 0x04, - 0x03, 0x03, 0x02, 0x02, 0x01, 0x01 - }; - - u4Byte centerTxIdx = pRFCalibrateInfo->DpkTxAGC & 0x1F; - u4Byte centerAddr = (0x1F-centerTxIdx) / 2; - s4Byte i = 0, j = 0, value = 0, startIdx = 0; - - // Upper - startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+1 : baseIdx); - - for (i = startIdx, j = 0; (centerAddr-j+1) >= 1; i -= 2, j++) { - if (i-1 < 0) - value = (TablePWSF[0] << 16) | (TablePWSF[0] << 8) | ((centerAddr-j) << 1) | 0x1; - else - value = (TablePWSF[i] << 16) | (TablePWSF[i-1] << 8) | ((centerAddr-j) << 1) | 0x1; - - ODM_Write4Byte(pDM_Odm, 0xee4, value); - ODM_Write1Byte(pDM_Odm, 0xee4, 0x0); //write disable - } - - // Lower - startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+2 : baseIdx+1); - centerAddr++; // Skip centerTxIdx - for (i = startIdx, j = 0; (centerAddr+j) < 16; i += 2, j++) { // Total: 16*2 = 32 values (Upper+Lower) - if (i+1 >= LEN) - value = (TablePWSF[LEN-1] << 16) | (TablePWSF[LEN-1] << 8) | ((centerAddr+j) << 1) | 0x1; - else - value = (TablePWSF[i+1] << 16) | (TablePWSF[i] << 8) | ((centerAddr+j) << 1) | 0x1; - ODM_Write4Byte(pDM_Odm, 0xee4, value); - ODM_Write1Byte(pDM_Odm, 0xee4, 0x0); //write disable - } - } - } - // [31] = 0 --> switch to page C - ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_EnableDP\n")); - -} - - - - - -VOID -phy_DPCalibrate_PathB_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte backupMacBBRegAddrs[] = { - 0xE60, 0xE64, 0xC68, 0x82C, 0x838, 0x90C, 0x522, 0xE00, 0xE20, 0xE24, // 10 - 0xE28, 0xE2C, 0xE30, 0xE34, 0xE38, 0xE3C, 0xE40, 0xE44, 0xE48, 0xE4C, // 20 - 0xE94, 0xEB0, 0xEB4 - }; - u4Byte backupRFRegAddrs[] = {0x00, 0x64, 0x8F}; - - u4Byte backupMacBBRegData[sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)]; - u4Byte backupRFRegData_A[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; - //u4Byte backupRFRegData_B[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; - - - _DPK_MacBBBackup_PathB(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); - _DPK_RFBackup_PathB(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_B, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); - - _DPK_Init_PathB(pDM_Odm); - - if (_DPK_AdjustRFGain_PathB(pDM_Odm)) { // Phase 1 - _DPK_GainLossToFindTxAGC_PathB(pDM_Odm); // Phase 2 - if (_DPK_AdjustRFGainByFoundTxAGC_PathB(pDM_Odm)) // Phase 3 - _DPK_DoAutoDPK_PathB(pDM_Odm); // Phase 4 - } - _DPK_EnableDP_PathB(pDM_Odm); // Phase 5 - - _DPK_MacBBRestore_PathB(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); - _DPK_RFRestore_PathB(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_B, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); -} -VOID -PHY_DPCalibrate_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - pDM_Odm->DPK_Done = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_DPCalibrate_8812A\n")); - phy_DPCalibrate_PathA_8812A(pDM_Odm); - phy_DPCalibrate_PathB_8812A(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_DPCalibrate_8812A\n")); -} - - - - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8812A 6 + +/*---------------------------Define Local Constant---------------------------*/ + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_ResetIQKResult(pDM_Odm); + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8812A(Adapter, FALSE); +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr8812A( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + u4Byte finalBbSwingIdx[2]; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte PwrTrackingLimit = 26; //+1.0dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); + + if(TxRate != 0xFF) //20130429 Mimic Modify High Rate BBSwing Limit. + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit = 32; /*+4dB*/ + /*2 OFDM*/ + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit = 30; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit = 28; //+2dB + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit = 28; //+2dB + + else if((TxRate >= MGN_MCS8)&&(TxRate <= MGN_MCS10)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS11)&&(TxRate <= MGN_MCS12)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS13)&&(TxRate <= MGN_MCS15)) //64QAM + PwrTrackingLimit = 28; //+2dB + + //2 VHT + else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT1SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT1SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT1SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else if((TxRate >= MGN_VHT2SS_MCS0)&&(TxRate <= MGN_VHT2SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT2SS_MCS3)&&(TxRate <= MGN_VHT2SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT2SS_MCS5)&&(TxRate <= MGN_VHT2SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT2SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT2SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT2SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else + PwrTrackingLimit = 24; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); + + + if (Method == BBSWING) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8812A\n")); + + if (RFPath == ODM_RF_PATH_A) + { + finalBbSwingIdx[ODM_RF_PATH_A] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", + pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); + } + else + { + finalBbSwingIdx[ODM_RF_PATH_B] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n", + pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_B], finalBbSwingIdx[ODM_RF_PATH_B])); + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_B]]); + } + } + + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) + { + + if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index - PwrTrackingLimit; // CCK Follow the same compensate value as Path A + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index; // CCK Follow the same compensate value as Path A + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= 0; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + } + + if (RFPath == ODM_RF_PATH_B) + { + if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB= TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathB) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_B); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + } + + } + else + { + return; + } +} + +VOID +GetDeltaSwingTable_8812A( + PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + + return; +} + +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->Threshold_DPK = DPK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; + pConfig->RfPathCount = MAX_PATH_NUM_8812A; + pConfig->ThermalRegAddr = RF_T_METER_8812A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8812A; + pConfig->DoIQK = DoIQK_8812A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8812A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8812A; +} + + +#define BW_20M 0 +#define BW_40M 1 +#define BW_80M 2 + +void _IQK_RX_FillIQC_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (RX_X>>1 >=0x112 || (RX_Y>>1 >= 0x12 && RX_Y>>1 <= 0x3ee)){ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + } + else{ + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ", RX_X>>1&0x000003ff, RX_Y>>1&0x000003ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe10 = %x====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xe10))); + } + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + case ODM_RF_PATH_B: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X&0x000007ff, TX_Y&0x000007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xed4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xecc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} +void _IQK_BackupRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + RFB_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} +void _IQK_BackupAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} +void _IQK_RestoreMacBB_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} +void _IQK_RestoreRF_8812A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x0); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + case ODM_RF_PATH_B: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path B Success!!!!\n")); + } + break; + default: + break; + } +} +void _IQK_RestoreAFE_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_SetBBReg(pDM_Odm, 0xc90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc8, BIT(29), 0x1); + //ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + ODM_SetBBReg(pDM_Odm, 0xe90, BIT(7), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(18), 0x1); + if (!pDM_Odm->DPK_Done) + ODM_SetBBReg(pDM_Odm, 0xec4, BIT(29), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec8, BIT(29), 0x1); + //ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + + +void _IQK_ConfigureMAC_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +#define cal_num 10 + +void _IQK_Tx_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte chnlIdx + ) +{ + u1Byte delay_count; + u1Byte cal0_retry, cal1_retry, TX0_Average = 0, TX1_Average = 0, RX0_Average = 0, RX1_Average = 0; + int TX_IQC_temp[10][4], TX_IQC[4]; //TX_IQC = [TX0_X, TX0_Y,TX1_X,TX1_Y]; for 3 times + int RX_IQC_temp[10][4], RX_IQC[4]; //RX_IQC = [RX0_X, RX0_Y,RX1_X,RX1_Y]; for 3 times + BOOLEAN TX0_fail = TRUE, RX0_fail = TRUE, IQK0_ready = FALSE, TX0_finish = FALSE, RX0_finish = FALSE; + BOOLEAN TX1_fail = TRUE, RX1_fail = TRUE, IQK1_ready = FALSE, TX1_finish = FALSE, RX1_finish = FALSE; + int i, ii, dx = 0, dy = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA5G = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA5G, pDM_Odm->ExtPA)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, RFE_Type = %d\n", pDM_Odm->SupportInterface, pDM_Odm->RFEType)); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + // Port 1 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xe68, 0x19791979); + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + ODM_SetBBReg(pDM_Odm, 0xe00, 0xf, 0x4);// hardware 3-wire off + + // DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + ODM_SetBBReg(pDM_Odm, 0xe5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + //====== Path A TX IQK RF Setting ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); + //====== Path B TX IQK RF Setting ====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3fffd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe83f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_SetBBReg(pDM_Odm, 0xe94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G){ + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403e3); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f7); + } + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f1); + ODM_Write4Byte(pDM_Odm, 0xe88, 0x821403f1); + } + if (*pDM_Odm->pBandType){ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x68163e96); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28163e96); + if (pDM_Odm->RFEType == 3){ + if (pDM_Odm->ExtPA) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + } + } + + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xce8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xe80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xee8, 0x00000000); + + cal0_retry = 0; + cal1_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + delay_count = 0; + while (1){ + if (!TX0_finish) + IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if (!TX1_finish) + IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK0_ready && IQK1_ready) || (delay_count>20)) + break; + else{ + ODM_delay_ms(1); + delay_count++; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX delay_count = %d\n", delay_count)); + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + TX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(12)); + if (!(TX0_fail || TX0_finish)){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_IQC_temp[TX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_IQC_temp[TX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", TX0_Average, (TX_IQC_temp[TX0_Average][0])>>21&0x000007ff, TX0_Average, (TX_IQC_temp[TX0_Average][1])>>21&0x000007ff)); + /* + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + TX0_Average++; + } + else{ + cal0_retry++; + if (cal0_retry == 10) + break; + } + if (!(TX1_fail || TX1_finish)){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + TX_IQC_temp[TX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + TX_IQC_temp[TX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n", TX1_Average, (TX_IQC_temp[TX1_Average][2])>>21&0x000007ff, TX1_Average, (TX_IQC_temp[TX1_Average][3])>>21&0x000007ff)); + /* + int reg1 = 0, reg2 = 0, Image_Power = 0; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x01000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x02000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x03000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x04000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + TX1_Average++; + } + else{ + cal1_retry++; + if (cal1_retry == 10) + break; + } + } + else{ + cal0_retry++; + cal1_retry++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms TX IQK Not Ready!!!!!\n")); + if (cal0_retry == 10) + break; + } + if (TX0_Average >= 2){ + for (i = 0; i < TX0_Average; i++){ + for (ii = i+1; ii >21) - (TX_IQC_temp[ii][0]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_IQC_temp[i][1]>>21) - (TX_IQC_temp[ii][1]>>21); + if (dy < 4 && dy > -4){ + TX_IQC[0] = ((TX_IQC_temp[i][0]>>21) + (TX_IQC_temp[ii][0]>>21))/2; + TX_IQC[1] = ((TX_IQC_temp[i][1]>>21) + (TX_IQC_temp[ii][1]>>21))/2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_X = %x;;TXA_Y = %x\n", TX_IQC[0]&0x000007ff, TX_IQC[1]&0x000007ff)); + TX0_finish = TRUE; + } + } + } + } + } + if (TX1_Average >= 2){ + for (i = 0; i < TX1_Average; i++){ + for (ii = i+1; ii >21) - (TX_IQC_temp[ii][2]>>21); + if (dx < 4 && dx > -4){ + dy = (TX_IQC_temp[i][3]>>21) - (TX_IQC_temp[ii][3]>>21); + if (dy < 4 && dy > -4){ + TX_IQC[2] = ((TX_IQC_temp[i][2]>>21) + (TX_IQC_temp[ii][2]>>21))/2; + TX_IQC[3] = ((TX_IQC_temp[i][3]>>21) + (TX_IQC_temp[ii][3]>>21))/2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_X = %x;;TXB_Y = %x\n", TX_IQC[2]&0x000007ff, TX_IQC[3]&0x000007ff)); + TX1_finish = TRUE; + } + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_Average = %d, TX1_Average = %d\n", TX0_Average, TX1_Average)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX0_finish = %d, TX1_finish = %d\n", TX0_finish, TX1_finish)); + if (TX0_finish && TX1_finish) + break; + if ((cal0_retry + TX0_Average) >= 10 || (cal1_retry + TX1_Average) >= 10 ) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXA_cal_retry = %d\n", cal0_retry)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TXB_cal_retry = %d\n", cal1_retry)); + + + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, 0xffc00)); // Load LOK + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, 0xffc00)); // Load LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (TX0_finish){ + //====== Path A RX IQK RF Setting====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x931d1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); + } + if (TX1_finish){ + //====== Path B RX IQK RF Setting====== + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, bRFRegOffsetMask, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, bRFRegOffsetMask, 0xfe7bf); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x931d1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x00000); + } + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + else + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); + //ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a890); + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00000077); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00000077); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0x02000077); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777717); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0x02000077); + } + + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (TX0_finish){ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x82140119); + } + if (TX1_finish){ + ODM_Write4Byte(pDM_Odm, 0xe80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xe84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xe88, 0x82140119); + } + cal0_retry = 0; + cal1_retry = 0; + while(1){ + // one shot + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + if (TX0_finish){ + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[0])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[1])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161500); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160cc0); + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000); + ODM_delay_ms(5); //Delay 5ms + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + } + if (TX1_finish){ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_IQC[2])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_IQC[3])&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + if (pDM_Odm->RFEType == 1){ + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28161500); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x28160ca0); + } + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00300000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_delay_ms(5); //Delay 5ms + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + } + delay_count = 0; + while (1){ + if (!RX0_finish && TX0_finish) + IQK0_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if (!RX1_finish && TX1_finish) + IQK1_ready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(10)); + if ((IQK0_ready && IQK1_ready)||(delay_count>20)) + break; + else{ + ODM_delay_ms(1); + delay_count++; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX delay_count = %d\n", delay_count)); + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX0_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + RX1_fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xd40, BIT(11)); + if (!(RX0_fail || RX0_finish) && TX0_finish){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_IQC_temp[RX0_Average][0] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_IQC_temp[RX0_Average][1] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", RX0_Average, (RX_IQC_temp[RX0_Average][0])>>21&0x000007ff, RX0_Average, (RX_IQC_temp[RX0_Average][1])>>21&0x000007ff)); +/* + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); +*/ + RX0_Average++; + } + else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("1. RXA_cal_retry = %d\n", cal0_retry)); + cal0_retry++; + if (cal0_retry == 10) + break; + } + if (!(RX1_fail || RX1_finish) && TX1_finish){ + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + RX_IQC_temp[RX1_Average][2] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + RX_IQC_temp[RX1_Average][3] = ODM_GetBBReg(pDM_Odm, 0xd40, 0x07ff0000)<<21; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n", RX1_Average, (RX_IQC_temp[RX1_Average][2])>>21&0x000007ff, RX1_Average, (RX_IQC_temp[RX1_Average][3])>>21&0x000007ff)); +/* + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd40, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd40, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); +*/ + RX1_Average++; + } + else{ + cal1_retry++; + if (cal1_retry == 10) + break; + } + + } + else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("2. RXA_cal_retry = %d\n", cal0_retry)); + cal0_retry++; + cal1_retry++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay 20ms RX IQK Not Ready!!!!!\n")); + if (cal0_retry == 10) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("3. RXA_cal_retry = %d\n", cal0_retry)); + if (RX0_Average >= 2){ + for (i = 0; i < RX0_Average; i++){ + for (ii = i+1; ii >21) - (RX_IQC_temp[ii][0]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_IQC_temp[i][1]>>21) - (RX_IQC_temp[ii][1]>>21); + if (dy < 4 && dy > -4){ + RX_IQC[0]= ((RX_IQC_temp[i][0]>>21) + (RX_IQC_temp[ii][0]>>21))/2; + RX_IQC[1] = ((RX_IQC_temp[i][1]>>21) + (RX_IQC_temp[ii][1]>>21))/2; + RX0_finish = TRUE; + break; + } + } + } + } + } + if (RX1_Average >= 2){ + for (i = 0; i < RX1_Average; i++){ + for (ii = i+1; ii >21) - (RX_IQC_temp[ii][2]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_IQC_temp[i][3]>>21) - (RX_IQC_temp[ii][3]>>21); + if (dy < 4 && dy > -4){ + RX_IQC[2] = ((RX_IQC_temp[i][2]>>21) + (RX_IQC_temp[ii][2]>>21))/2; + RX_IQC[3] = ((RX_IQC_temp[i][3]>>21) + (RX_IQC_temp[ii][3]>>21))/2; + RX1_finish = TRUE; + break; + } + } + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_Average = %d, RX1_Average = %d\n", RX0_Average, RX1_Average)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX0_finish = %d, RX1_finish = %d\n", RX0_finish, RX1_finish)); + if ((RX0_finish|| !TX0_finish) && (RX1_finish || !TX1_finish) ) + break; + if ((cal0_retry + RX0_Average) >= 10 || (cal1_retry + RX1_Average) >= 10 || RX0_Average == 3 || RX1_Average == 3) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXA_cal_retry = %d\n", cal0_retry)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RXB_cal_retry = %d\n", cal1_retry)); + + + // FillIQK Result + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + + if (TX0_finish){ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, TX_IQC[0], TX_IQC[1]); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); + } + + + + if (RX0_finish){ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, RX_IQC[0], RX_IQC[1]); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_A, 0x200, 0x0); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_B =======\n")); + + if (TX1_finish){ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, TX_IQC[2], TX_IQC[3]); + } + else{ + _IQK_TX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); + } + + + + if (RX1_finish){ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, RX_IQC[2], RX_IQC[3]); + } + else{ + _IQK_RX_FillIQC_8812A(pDM_Odm, ODM_RF_PATH_B, 0x200, 0x0); + } + + + +} + +#define MACBB_REG_NUM 9 +#define AFE_REG_NUM 12 +#define RF_REG_NUM 3 + +// Maintained by BB James. +VOID +phy_IQCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0xe00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xcb0, 0xcb4, + 0xe5c, 0xe60, 0xe64, 0xe68, 0xeb0, 0xeb4}; + u4Byte Reg_C1B8, Reg_E1B8; + u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; + u1Byte chnlIdx = GetRightChnlPlaceforIQK(Channel); + + _IQK_BackupMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + Reg_C1B8 = ODM_Read4Byte(pDM_Odm, 0xcb8); + Reg_E1B8 = ODM_Read4Byte(pDM_Odm, 0xeb8); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + _IQK_BackupAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_BackupRF_8812A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); + + _IQK_ConfigureMAC_8812A(pDM_Odm); + _IQK_Tx_8812A(pDM_Odm, chnlIdx); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); + _IQK_RestoreRF_8812A(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG, RFB_backup, RF_REG_NUM); + + _IQK_RestoreAFE_8812A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_Write4Byte(pDM_Odm, 0xcb8, Reg_C1B8); + ODM_Write4Byte(pDM_Odm, 0xeb8, Reg_E1B8); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + _IQK_RestoreMacBB_8812A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + + +} + +VOID +phy_LCCalibrate_8812A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; + + //Check continuous TX and Packet TX + u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; + + // Backup RF reg18. + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + if((reg0x914 & 0x70000) != 0) //If contTx, disable all continuous TX. 0x914[18:16] + // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx + // until another packet comes in. To avoid ContTx being turned off, we skip this step. + ;//ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914 & (~0x70000)); + else // If packet Tx-ing, pause Tx. + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); + + +/* + //3 1. Read original RF mode + RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask); + if(is2T) + RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask); + + + //3 2. Set RF mode = standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, (RF_Amode&0x8FFFF)|0x10000); + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, (RF_Bmode&0x8FFFF)|0x10000); +*/ + + // Enter LCK mode + tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp | BIT14); + + //3 3. Read RF reg18 + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + //3 4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); + + ODM_delay_ms(150); // suggest by RFSI Binson + + // Leave LCK mode + tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_LCK, bRFRegOffsetMask, tmp & ~BIT14); + + //3 Restore original situation + if((reg0x914 & 70000) != 0) //Deal with contisuous TX case, 0x914[18:16] + { + // <20121121, Kordan> A workaround: If we set 0x914[18:16] as zero, BB turns off ContTx + // until another packet comes in. To avoid ContTx being turned off, we skip this step. + //ODM_Write4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar, reg0x914); + } + else // Deal with Packet TX case + { + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00); + } + + // Recover channel number + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + /* + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, RF_Amode); + if(is2T) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bRFRegOffsetMask, RF_Bmode); + */ + +} + + + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + +VOID +phy_ReloadIQKSetting_8812A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte chnlIdx = GetRightChnlPlaceforIQK(Channel); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][0]&0x7ff0000)>>16); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][2]&0x7ff0000)>>16); + + if (*pDM_Odm->pBandWidth != 2){ + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); + } + else{ + ODM_Write4Byte(pDM_Odm, 0xce8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][4]); + ODM_Write4Byte(pDM_Odm, 0xee8, pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][5]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff0000)>>17); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][1]&0x7ff)>>1); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff0000)>>17); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x03ff0000, (pRFCalibrateInfo->IQKMatrixRegSetting[chnlIdx].Value[*pDM_Odm->pBandWidth][3]&0x7ff)>>1); + + +} + +VOID +PHY_ResetIQKResult_8812A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_SetBBReg(pDM_Odm, 0xecc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xed4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_Write4Byte(pDM_Odm, 0xee8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xe10, 0x000003ff, 0x100); +} + +VOID +phy_IQCalibrate_By_FW_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + + u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(*pDM_Odm->pBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(*pDM_Odm->pBandWidth == ODM_BW20M) + Buf2 = 0x1; + else if(*pDM_Odm->pBandWidth == ODM_BW40M) + Buf2 = 0x1<<1; + else if(*pDM_Odm->pBandWidth == ODM_BW80M) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtPA<<1 | pDM_Odm->SupportInterface<<2 | pDM_Odm->RFEType<<5; + + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Start ==\n")); + pRFCalibrateInfo->IQK_StartTime = 0; + pRFCalibrateInfo->IQK_StartTime = ODM_GetCurrentTime(pDM_Odm); + RT_TRACE(COMP_MP, DBG_LOUD, ("== StartTime: %u\n", pRFCalibrateInfo->IQK_StartTime)); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); + + +} + +VOID +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + u4Byte counter = 0; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif +#endif//(MP_DRIVER == 1) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + //pMgntInfo->RegIQKFWOffload = (u1Byte)ODM_GetBBReg( pDM_Odm, 0x444, BIT8); +#if MP_DRIVER == 1 + + // Add to determine IQK ON/OFF in certain case, Suggested by Cheng. + if (!pHalData->IQK_MP_Switch) + return; + + + if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) +#endif + { + + //3 == FW IQK == + if(pMgntInfo->RegIQKFWOffload) + { + if ( ! pRFCalibrateInfo->bIQKInProgress) + { + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + + phy_IQCalibrate_By_FW_8812A(pDM_Odm); + } + else + { + for(counter = 0; counter < 10; counter++){ + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); + delay_ms(50); + if ( ! pRFCalibrateInfo->bIQKInProgress) + { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); + break; + } + } + + if (pRFCalibrateInfo->bIQKInProgress) + { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + } + else + { + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + phy_IQCalibrate_By_FW_8812A(pDM_Odm); + } + + + } + } + //3 == Driver IQK == + else + { + if ( ! pRFCalibrateInfo->bIQKInProgress) + { + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + + //RT_TRACE(COMP_P2P, DBG_LOUD, ("1 %s: KeGetCurrentIrql(): %d\n", __FUNCTION__, KeGetCurrentIrql())); + phy_IQCalibrate_8812A(pDM_Odm, pHalData->CurrentChannel); + //RT_TRACE(COMP_P2P, DBG_LOUD, ("3 %s: KeGetCurrentIrql(): %d\n", __FUNCTION__, KeGetCurrentIrql())); + + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + } + } + + + } + +} + + +VOID +PHY_LCCalibrate_8812A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8812A\n")); + +#if (MP_DRIVER == 1) + phy_LCCalibrate_8812A(pDM_Odm, TRUE); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8812A\n")); + +} + +VOID phy_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + +#endif + + if (IS_HARDWARE_TYPE_8821(pAdapter)) + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x1); //Main + else + ODM_SetBBReg(pDM_Odm, rA_RFE_Pinmux_Jaguar+4, BIT29|BIT28, 0x2); //Aux + } + else if (pDM_Odm->SupportICType & ODM_RTL8812) + { + if (pHalData->RFEType == 5) + { + if(bMain) { + // WiFi + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } else { + // BT + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } + } + else if (pHalData->RFEType == 1) + { // <131224, VincentL> When RFEType == 1 also Set 0x900, suggested by RF Binson. + if(bMain) { + // WiFi + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x2); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } else { + // BT + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); + ODM_SetBBReg(pDM_Odm, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); + } + } + + } + +} +VOID PHY_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + phy_SetRFPathSwitch_8812A(pAdapter, bMain, TRUE); + +#endif +} + +s4Byte +_Sign( + IN u4Byte Number + ) +{ + if ((Number & BIT10) == BIT10) {// Negative + Number &= (~0xFFFFFC00); // [9:0] + Number = ~Number; + Number &= (~0xFFFFFC00); // [9:0] + Number += 1; + Number &= (~0xFFFFF800); // [10:0] + return -1 * Number; + } else { // Positive + return (s4Byte)Number; + } +} + + +VOID +_DPK_MacBBBackup_PathA( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN OUT pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + BackupRegData[i] = ODM_Read4Byte(pDM_Odm, BackupRegAddr[i]); +} +VOID +_DPK_MacBBRestore_PathA( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + ODM_Write4Byte(pDM_Odm, BackupRegAddr[i], BackupRegData[i]); +} + + +VOID +_DPK_RFBackup_PathA( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN ODM_RF_RADIO_PATH_E RFPath, + IN OUT pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + BackupRegData[i] = ODM_GetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask); +} + +VOID +_DPK_RFRestore_PathA( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN ODM_RF_RADIO_PATH_E RFPath, + IN pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + ODM_SetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask, BackupRegData[i]); +} + + + +s4Byte +_ComputeLoopBackGain_PathA( + IN PDM_ODM_T pDM_Odm +) +{ + // compute loopback gain + // ­pºâtmpLBGain ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.10 + // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, + // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, + // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, + // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, + // Á|¨Ò5, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, + u4Byte reg0xD00_26_16 = ODM_GetBBReg(pDM_Odm, 0xD00, 0x7FF0000); + u4Byte reg0xD00_10_0 = ODM_GetBBReg(pDM_Odm, 0xD00, 0x7FF); + + s4Byte tmpLBGain = _Sign(reg0xD00_26_16)*_Sign(reg0xD00_26_16) + _Sign(reg0xD00_10_0)*_Sign(reg0xD00_10_0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _ComputeLoopBackGain_PathA, tmpLBGain = 0x%X\n", tmpLBGain)); + + return tmpLBGain; +} + + +BOOLEAN +_FineTuneLoopBackGain_PathA( + IN PDM_ODM_T pDM_Odm, + IN u4Byte DpkTxAGC + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + u4Byte rf0x64_orig = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7); + u4Byte rf0x64_new = rf0x64_orig; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _FineTuneLoopBackGain\n")); + + do { + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, DpkTxAGC); + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); + + tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); + + if ((rf0x64_new == (BIT2|BIT1|BIT0)) || (rf0x64_new == 0)) { + //printf('DPK Phase 1 failed'); + pRFCalibrateInfo->bDPKFail = TRUE; + break; + //Go to DPK Phase 5 + } else { + if (tmpLBGain < 263390) {// fine tune loopback path gain: newReg64[2:0] = reg64[2:0] - 3b'001 + rf0x64_new -= 1; + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7, rf0x64_new); + + } else if (tmpLBGain > 661607) {// fine tune loopback path gain: newReg64 [2:0] = reg64[2:0] + 3b'001 + rf0x64_new += 1; + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, 0x7, rf0x64_new); + + } else { + pRFCalibrateInfo->bDPKFail = FALSE; + } + } + + } while (tmpLBGain < 263390 || 661607 < tmpLBGain); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _FineTuneLoopBackGain\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + + +VOID +_DPK_Init_PathA( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_Init\n")); + + //TX pause + ODM_Write1Byte(pDM_Odm, 0x522, 0x7f); + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + // AFE setting + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + // external TRSW ¤Á¨ì T + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0x01000077); + + // hardware 3-wire off + ODM_Write4Byte(pDM_Odm, 0xc00, 0x00000004); + + // CCA off + ODM_Write4Byte(pDM_Odm, 0x838, 0x16C89B4c); + + //90c[15]: dac fifo reset by CSWU + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + + // r_gothrough_iqkdpk + ODM_Write4Byte(pDM_Odm, 0xc94, 0x0100005D); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // IQK Amp off + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + + // tx_amp + ODM_Write4Byte(pDM_Odm, 0xc98, 0x41382e21); + ODM_Write4Byte(pDM_Odm, 0xc9c, 0x5b554f48); + ODM_Write4Byte(pDM_Odm, 0xca0, 0x6f6b6661); + ODM_Write4Byte(pDM_Odm, 0xca4, 0x817d7874); + ODM_Write4Byte(pDM_Odm, 0xca8, 0x908c8884); + ODM_Write4Byte(pDM_Odm, 0xcac, 0x9d9a9793); + ODM_Write4Byte(pDM_Odm, 0xcb0, 0xaaa7a4a1); + ODM_Write4Byte(pDM_Odm, 0xcb4, 0xb6b3b0ad); + + // tx_inverse + ODM_Write4Byte(pDM_Odm, 0xc40, 0x02ce03e9); + ODM_Write4Byte(pDM_Odm, 0xc44, 0x01fd0249); + ODM_Write4Byte(pDM_Odm, 0xc48, 0x01a101c9); + ODM_Write4Byte(pDM_Odm, 0xc4c, 0x016a0181); + ODM_Write4Byte(pDM_Odm, 0xc50, 0x01430155); + ODM_Write4Byte(pDM_Odm, 0xc54, 0x01270135); + ODM_Write4Byte(pDM_Odm, 0xc58, 0x0112011c); + ODM_Write4Byte(pDM_Odm, 0xc5c, 0x01000108); + ODM_Write4Byte(pDM_Odm, 0xc60, 0x00f100f8); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x00e500eb); + ODM_Write4Byte(pDM_Odm, 0xc68, 0x00db00e0); + ODM_Write4Byte(pDM_Odm, 0xc6c, 0x00d100d5); + ODM_Write4Byte(pDM_Odm, 0xc70, 0x00c900cd); + ODM_Write4Byte(pDM_Odm, 0xc74, 0x00c200c5); + ODM_Write4Byte(pDM_Odm, 0xc78, 0x00bb00be); + ODM_Write4Byte(pDM_Odm, 0xc7c, 0x00b500b8); + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + pRFCalibrateInfo->bDPKFail = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_Init\n")); + +} + + +BOOLEAN +_DPK_AdjustRFGain_PathA( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGain\n")); + + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x50bfc); + // Attn: A mode @ reg64[2:0], G mode @ reg56 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, bRFRegOffsetMask, 0x19aac); + // PGA gain: RF reg8f[14:13] + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11838000); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0xFFF000, 0x100); // ±Ncd4[23:12] §ï¦¨ h'100, ¨ä¥¦¦ì¤¸½Ð«O¯d­ì­È¤£­n¼g¨ì + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // read back Loopback Gain + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x09000000); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); + + tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); + + // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 + if (tmpLBGain < 263390) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8e001); + _FineTuneLoopBackGain_PathA(pDM_Odm, 0x50bfc); + + } + else if (tmpLBGain > 661607) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); + _FineTuneLoopBackGain_PathA(pDM_Odm, 0x50bfc); + } + else + pRFCalibrateInfo->bDPKFail = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGain\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + + +VOID +_DPK_GainLossToFindTxAGC_PathA( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte Reg0xD00 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_GainLossToFindTxAGC\n")); + + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x50bfc); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. + // dB_sel = b'000 ' 1.0 dB PA gain loss + // dB_sel = b'001 ' 1.5 dB PA gain loss + // dB_sel = b'010 ' 2.0 dB PA gain loss + // dB_sel = b'011 ' 2.5 dB PA gain loss + // dB_sel = b'100 ' 3.0 dB PA gain loss + // dB_sel = b'101 ' 3.5 dB PA gain loss + // dB_sel = b'110 ' 4.0 dB PA gain loss + ODM_Write4Byte(pDM_Odm, 0xc20, 0x00002000); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x148b8000); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0401f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // read back Loopback Gain + // ¥i¥H¦b d00[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w + // Ū¦^d00[3:0] = h'1 ' Tx AGC = h'13 + // Ū¦^d00[3:0] = h'2 ' Tx AGC = h'14 + // Ū¦^d00[3:0] = h'3 ' Tx AGC = h'15 + // Ū¦^d00[3:0] = h'4 ' Tx AGC = h'16 + // Ū¦^d00[3:0] = h'5 ' Tx AGC = h'17 + // Ū¦^d00[3:0] = h'6 ' Tx AGC = h'18 + // Ū¦^d00[3:0] = h'7 ' Tx AGC = h'19 + // Ū¦^d00[3:0] = h'8 ' Tx AGC = h'1a + // Ū¦^d00[3:0] = h'9 ' Tx AGC = h'1b + // Ū¦^d00[3:0] = h'a ' Tx AGC = h'1c + // + Reg0xD00 = ODM_Read4Byte(pDM_Odm, 0xd00); + switch (ODM_Read4Byte(pDM_Odm, 0xd00) & (BIT3|BIT2|BIT1|BIT0)) + { + case 0x0: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x2; break; + case 0x1: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x3; break; + case 0x2: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x4; break; + case 0x3: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x5; break; + case 0x4: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x6; break; + case 0x5: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x7; break; + case 0x6: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x8; break; + case 0x7: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x9; break; + case 0x8: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xa; break; + case 0x9: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xb; break; + case 0xa: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xc; break; + } + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_GainLossToFindTxAGC\n")); +} + + +BOOLEAN +_DPK_AdjustRFGainByFoundTxAGC_PathA +( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGainByFoundTxAGC\n")); + + // RF setting, ­«·s³]©wRF reg00, Á|¨Ò¥ÎDPK Phase 2±o¨ìªº d00[3:0] = 0x6 ' TX AGC= 0x18 ' RF reg00[4:0] = 0x18 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); + // Attn: A mode @ reg64[2:0], G mode @ reg56 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x64, bRFRegOffsetMask, 0x19aac); + // PGA gain: RF reg8f[14:13] + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8a001); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11838000); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33d8d); + + + tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); + + if (tmpLBGain < 263390) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x8e001); + _FineTuneLoopBackGain_PathA(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); + } + else if (tmpLBGain > 661607) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); + _FineTuneLoopBackGain_PathA(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); + } + else + pRFCalibrateInfo->bDPKFail = FALSE;//Go to DPK Phase 4 + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGainByFoundTxAGC\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + +VOID +_DPK_DoAutoDPK_PathA( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte tmpLBGain = 0, reg0xD00 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_DoAutoDPK\n")); + + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + // RF setting, ¦¹³BRF reg00, »P DPK Phase 3 ¤@­P + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); + // Baseband Data Rate setting + ODM_Write4Byte(pDM_Odm, 0xc20, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc24, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc28, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc2c, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc30, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc34, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc38, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc3c, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc40, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc44, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc48, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xc4c, 0x3c3c3c3c); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xc94, 0xf76C9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x400C5599); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x11938080); //0xcc4[9:4]= DPk fail threshold + + if ( 36 <= *(pDM_Odm->pChannel) && *(pDM_Odm->pChannel) <= 53)//Channelchannel at low band) + // r_agc + ODM_Write4Byte(pDM_Odm, 0xcbc, 0x00022a1f); + else + // r_agc + ODM_Write4Byte(pDM_Odm, 0xcbc, 0x00009dbf); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0101f018); // TODO: 0xC90(rA_LSSIWrite_Jaguar) can not be overwritten. + + // one shot + ODM_Write4Byte(pDM_Odm, 0xcc8, 0xc00c5599); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x400c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + // T-meter RFReg42[17] = 1 to enable read T-meter, [15:10] ' T-meter value + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, BIT17, 1); + pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, 0xFC00); // Ū¥X42[15:10] ­È¨Ã¦s¨ìÅܼÆTMeter + DbgPrint("pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] = 0x%X\n", pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask, 0x33D8D); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + // read back dp_fail report + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + //dp_fail³o­Óbit¦bd00[6], ·í d00[6] = 1, ªí¥Ücalibration¥¢±Ñ. + reg0xD00 = ODM_Read4Byte(pDM_Odm, 0xd00); + + if ((reg0xD00 & BIT6) == BIT6) { + //printf('DPK fail') + pRFCalibrateInfo->bDPKFail = TRUE; + //Go to DPK Phase 5 + } else { + //printf('DPK success') + } + + + // read back + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0201f01f); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0c000000); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + // ­pºâtmpGainLoss ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.9 + // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, + // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, + // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, + // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, + // Á|¨Ò4, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, + tmpLBGain = _ComputeLoopBackGain_PathA(pDM_Odm); + + + // Gain Scaling + if (227007 < tmpLBGain) + pRFCalibrateInfo->DpkGain = 0x43ca43ca; + else if (214309 < tmpLBGain && tmpLBGain <= 227007) + pRFCalibrateInfo->DpkGain = 0x45c545c5; + else if (202321 < tmpLBGain && tmpLBGain <= 214309) + pRFCalibrateInfo->DpkGain = 0x47cf47cf; + else if (191003 < tmpLBGain && tmpLBGain <= 202321) + pRFCalibrateInfo->DpkGain = 0x49e749e7; + else if (180318 < tmpLBGain && tmpLBGain <= 191003) + pRFCalibrateInfo->DpkGain = 0x4c104c10; + else if (170231 < tmpLBGain && tmpLBGain <= 180318) + pRFCalibrateInfo->DpkGain = 0x4e494e49; + else if (160709 < tmpLBGain && tmpLBGain <= 170231) + pRFCalibrateInfo->DpkGain = 0x50925092; + else if (151719 < tmpLBGain && tmpLBGain <= 160709) + pRFCalibrateInfo->DpkGain = 0x52ec52ec; + else if (151719 <= tmpLBGain) + pRFCalibrateInfo->DpkGain = 0x55585558; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_DoAutoDPK\n")); +} + + +VOID +_DPK_EnableDP_PathA( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_EnableDP\n")); + + // [31] = 1 --> switch to page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // enable IQC matrix --> ¦]¬° BB «H¸¹·|¥ý¸g¹L predistortion module, ¤~¸g¹L IQC matrix ¨ì DAC ¥´¥X¥h + // ©Ò¥H­n¥ý enable predistortion module {c90[7] = 1 (enable_predis) cc4[18] = 1 (½T©wÅý IQK/DPK module ¦³clock), cc8[29] = 1 (¤@­ÓIQK/DPK module ¸Ìªºmux, ½T»{ data path ¨«IQK/DPK)} + ODM_Write4Byte(pDM_Odm, 0xc90, 0x0000f098); + ODM_Write4Byte(pDM_Odm, 0xc94, 0x776d9f84); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + // r_bnd + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x000fffff); + + if (pRFCalibrateInfo->bDPKFail) + { + // cc4[29] = 1 (bypass DP LUT) + ODM_Write4Byte(pDM_Odm, 0xc98, 0x40004000); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x28840000); + } + else + { + ODM_Write4Byte(pDM_Odm, 0xc98, pRFCalibrateInfo->DpkGain); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x08840000); + + // PWSF + // ¼gPWSF table in 1st SRAM for PA = 11 use + ODM_Write4Byte(pDM_Odm, 0xc20, 0x00000800); + + //******************************************************* + //0xce4[0]¬Owrite enable¡A0xce4[7:1]¬Oaddress¡A0xce4[15:8]©M0xce4[23:16]¹ïÀ³¨ìTX index¡A + //­Y¦ì¸m¬°0(0xce4[7:1] = 0x0)¦¹®É0xce4[15:8]¹ïÀ³¨ìªºTX RF index ¬O0x1f,¡A + //0xce4[23:16]¹ïÀ³¨ìªº¬O0x1e¡A­Y¦ì¸m¬°1(0xce4[7:1] = 0x1)¡A¦¹®É0xce4 [15:8]¹ïÀ³¨ì0x1d¡A + //0xce4[23:16]¹ïÀ³0x1c¡A¨ä¥L¨Ì¦¹Ãþ±À¡A¨C­ÓdataÄæ¦ì³£¬O¬Û®t1dB¡C­Ygainloss§ä¨ìªºRF TX index=0x18¡A + //«h¦b0xce4 address¹ïÀ³¨ì0x18ªº¦a¤è­n¶ñ0x40(¤]´N¬O0dB)¡A¨ä¥L«h·Ó¤U­±tableªº¶¶§Ç¨C®æ1dB¨Ì§Ç±Æ¦C + //±N©Ò¦³ªº0xce4cªºdataÄæ¦ì³£¶ñ¤J¬Û¹ïÀ³ªº­È¡C + //*************************************************************// + + { + const s4Byte LEN = 25; + u4Byte baseIdx = 6; // 0 dB: 0x40 + u4Byte TablePWSF[] = { + 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40/* 0 dB */, + 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, + 0x0d, 0x0a, 0x08, 0x06, 0x05, 0x04, + 0x03, 0x03, 0x02, 0x02, 0x01, 0x01 + }; + + u4Byte centerTxIdx = pRFCalibrateInfo->DpkTxAGC & 0x1F; + u4Byte centerAddr = (0x1F-centerTxIdx) / 2; + s4Byte i = 0, j = 0, value = 0, startIdx = 0; + + // Upper + startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+1 : baseIdx); + + for (i = startIdx, j = 0; (centerAddr-j+1) >= 1; i -= 2, j++) { + if (i-1 < 0) + value = (TablePWSF[0] << 16) | (TablePWSF[0] << 8) | ((centerAddr-j) << 1) | 0x1; + else + value = (TablePWSF[i] << 16) | (TablePWSF[i-1] << 8) | ((centerAddr-j) << 1) | 0x1; + + ODM_Write4Byte(pDM_Odm, 0xce4, value); + ODM_Write1Byte(pDM_Odm, 0xce4, 0x0); //write disable + } + + // Lower + startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+2 : baseIdx+1); + centerAddr++; // Skip centerTxIdx + for (i = startIdx, j = 0; (centerAddr+j) < 16; i += 2, j++) { // Total: 16*2 = 32 values (Upper+Lower) + if (i+1 >= LEN) + value = (TablePWSF[LEN-1] << 16) | (TablePWSF[LEN-1] << 8) | ((centerAddr+j) << 1) | 0x1; + else + value = (TablePWSF[i+1] << 16) | (TablePWSF[i] << 8) | ((centerAddr+j) << 1) | 0x1; + ODM_Write4Byte(pDM_Odm, 0xce4, value); + ODM_Write1Byte(pDM_Odm, 0xce4, 0x0); //write disable + } + } + } + // [31] = 0 --> switch to page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_EnableDP\n")); + +} + + + + + +VOID +phy_DPCalibrate_PathA_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte backupMacBBRegAddrs[] = { + 0xC60, 0xC64, 0xC68, 0x82C, 0x838, 0x90C, 0x522, 0xC00, 0xC20, 0xC24, // 10 + 0xC28, 0xC2C, 0xC30, 0xC34, 0xC38, 0xC3C, 0xC40, 0xC44, 0xC48, 0xC4C, // 20 + 0xC94, 0xCB0, 0xCB4 + }; + u4Byte backupRFRegAddrs[] = {0x00, 0x64, 0x8F}; + + u4Byte backupMacBBRegData[sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)]; + u4Byte backupRFRegData_A[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; + //u4Byte backupRFRegData_B[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; + + + _DPK_MacBBBackup_PathA(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); + _DPK_RFBackup_PathA(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_A, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); + + _DPK_Init_PathA(pDM_Odm); + + if (_DPK_AdjustRFGain_PathA(pDM_Odm)) { // Phase 1 + _DPK_GainLossToFindTxAGC_PathA(pDM_Odm); // Phase 2 + if (_DPK_AdjustRFGainByFoundTxAGC_PathA(pDM_Odm)) // Phase 3 + _DPK_DoAutoDPK_PathA(pDM_Odm); // Phase 4 + } + _DPK_EnableDP_PathA(pDM_Odm); // Phase 5 + + _DPK_MacBBRestore_PathA(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); + _DPK_RFRestore_PathA(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_A, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); +} + + +VOID +_DPK_MacBBBackup_PathB( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN OUT pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + BackupRegData[i] = ODM_Read4Byte(pDM_Odm, BackupRegAddr[i]); +} + +VOID +_DPK_MacBBRestore_PathB( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + ODM_Write4Byte(pDM_Odm, BackupRegAddr[i], BackupRegData[i]); +} + + +VOID +_DPK_RFBackup_PathB( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN ODM_RF_RADIO_PATH_E RFPath, + IN OUT pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + BackupRegData[i] = ODM_GetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask); +} + +VOID +_DPK_RFRestore_PathB( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte BackupRegAddr, + IN ODM_RF_RADIO_PATH_E RFPath, + IN pu4Byte BackupRegData, + IN u4Byte Number + ) +{ + u4Byte i; + + for (i = 0; i < Number; i++) + ODM_SetRFReg(pDM_Odm, RFPath, BackupRegAddr[i], bRFRegOffsetMask, BackupRegData[i]); +} + + + +s4Byte +_ComputeLoopBackGain_PathB( + IN PDM_ODM_T pDM_Odm +) +{ + // compute loopback gain + // ­pºâtmpLBGain ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.10 + // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, + // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, + // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, + // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, + // Á|¨Ò5, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, + u4Byte reg0xD40_26_16 = ODM_GetBBReg(pDM_Odm, 0xD40, 0x7FF0000); + u4Byte reg0xD40_10_0 = ODM_GetBBReg(pDM_Odm, 0xD40, 0x7FF); + + s4Byte tmpLBGain = _Sign(reg0xD40_26_16)*_Sign(reg0xD40_26_16) + _Sign(reg0xD40_10_0)*_Sign(reg0xD40_10_0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _ComputeLoopBackGain_PathB, tmpLBGain = 0x%X\n", tmpLBGain)); + + return tmpLBGain; +} + + +BOOLEAN +_FineTuneLoopBackGain_PathB( + IN PDM_ODM_T pDM_Odm, + IN u4Byte DpkTxAGC + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + u4Byte rf0x64_orig = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7); + u4Byte rf0x64_new = rf0x64_orig; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _FineTuneLoopBackGain_PathB\n")); + + do { + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, DpkTxAGC); + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); + + tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); + + if ((rf0x64_new == (BIT2|BIT1|BIT0)) || (rf0x64_new == 0)) { + //printf('DPK Phase 1 failed'); + pRFCalibrateInfo->bDPKFail = TRUE; + break; + //Go to DPK Phase 5 + } else { + if (tmpLBGain < 263390) {// fine tune loopback path gain: newReg64[2:0] = reg64[2:0] - 3b'001 + rf0x64_new -= 1; + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7, rf0x64_new); + + } else if (tmpLBGain > 661607) {// fine tune loopback path gain: newReg64 [2:0] = reg64[2:0] + 3b'001 + rf0x64_new += 1; + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, 0x7, rf0x64_new); + + } else { + pRFCalibrateInfo->bDPKFail = FALSE; + } + } + + } while (tmpLBGain < 263390 || 661607 < tmpLBGain); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _FineTuneLoopBackGain_PathB\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + + +VOID +_DPK_Init_PathB( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_Init\n")); + + //TX pause + ODM_Write1Byte(pDM_Odm, 0x522, 0x7f); + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + // AFE setting + ODM_Write4Byte(pDM_Odm, 0xc68, 0x59791979); + ODM_Write4Byte(pDM_Odm, 0xe60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x77777777); + + // external TRSW ¤Á¨ì T + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0x01000077); + + // hardware 3-wire off + ODM_Write4Byte(pDM_Odm, 0xe00, 0x00000004); + + // CCA off + ODM_Write4Byte(pDM_Odm, 0x838, 0x16C89B4c); + + //90c[15]: dac fifo reset by CSWU + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + + // r_gothrough_iqkdpk + ODM_Write4Byte(pDM_Odm, 0xe94, 0x0100005D); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // IQK Amp off + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + + // tx_amp + ODM_Write4Byte(pDM_Odm, 0xe98, 0x41382e21); + ODM_Write4Byte(pDM_Odm, 0xe9c, 0x5b554f48); + ODM_Write4Byte(pDM_Odm, 0xea0, 0x6f6b6661); + ODM_Write4Byte(pDM_Odm, 0xea4, 0x817d7874); + ODM_Write4Byte(pDM_Odm, 0xea8, 0x908c8884); + ODM_Write4Byte(pDM_Odm, 0xeac, 0x9d9a9793); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0xaaa7a4a1); + ODM_Write4Byte(pDM_Odm, 0xeb4, 0xb6b3b0ad); + + // tx_inverse + ODM_Write4Byte(pDM_Odm, 0xe40, 0x02ce03e9); + ODM_Write4Byte(pDM_Odm, 0xe44, 0x01fd0249); + ODM_Write4Byte(pDM_Odm, 0xe48, 0x01a101c9); + ODM_Write4Byte(pDM_Odm, 0xe4c, 0x016a0181); + ODM_Write4Byte(pDM_Odm, 0xe50, 0x01430155); + ODM_Write4Byte(pDM_Odm, 0xe54, 0x01270135); + ODM_Write4Byte(pDM_Odm, 0xe58, 0x0112011c); + ODM_Write4Byte(pDM_Odm, 0xe5c, 0x01000108); + ODM_Write4Byte(pDM_Odm, 0xe60, 0x00f100f8); + ODM_Write4Byte(pDM_Odm, 0xe64, 0x00e500eb); + ODM_Write4Byte(pDM_Odm, 0xe68, 0x00db00e0); + ODM_Write4Byte(pDM_Odm, 0xe6c, 0x00d100d5); + ODM_Write4Byte(pDM_Odm, 0xe70, 0x00c900cd); + ODM_Write4Byte(pDM_Odm, 0xe74, 0x00c200c5); + ODM_Write4Byte(pDM_Odm, 0xe78, 0x00bb00be); + ODM_Write4Byte(pDM_Odm, 0xe7c, 0x00b500b8); + + // reg82c[31] = b'0, ¤Á´«¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + pRFCalibrateInfo->bDPKFail = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_Init\n")); + +} + + +BOOLEAN +_DPK_AdjustRFGain_PathB( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGain\n")); + + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x50bfc); + // Attn: A mode @ reg64[2:0], G mode @ reg56 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, bRFRegOffsetMask, 0x19aac); + // PGA gain: RF reg8f[14:13] + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x11838000); + ODM_SetBBReg(pDM_Odm, 0xed4, 0xFFF000, 0x100); // ±Ncd4[23:12] §ï¦¨ h'100, ¨ä¥¦¦ì¤¸½Ð«O¯d­ì­È¤£­n¼g¨ì + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // read back Loopback Gain + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x09000000); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); + + tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); + + // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 + if (tmpLBGain < 263390) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8e001); + _FineTuneLoopBackGain_PathB(pDM_Odm, 0x50bfc); + + } + else if (tmpLBGain > 661607) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); + _FineTuneLoopBackGain_PathB(pDM_Odm, 0x50bfc); + } + else + pRFCalibrateInfo->bDPKFail = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGain\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + + +VOID +_DPK_GainLossToFindTxAGC_PathB( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte Reg0xD40 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_GainLossToFindTxAGC\n")); + + // RF setting + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x50bfc); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // regc20[15:13] = dB sel, §i¶D Gain Loss function ¥h´M§ä dB_sel ©Ò³]©wªºPA gain loss¥Ø¼Ð©Ò¹ïÀ³ªº Tx AGC ¬°¦ó. + // dB_sel = b'000 ' 1.0 dB PA gain loss + // dB_sel = b'001 ' 1.5 dB PA gain loss + // dB_sel = b'010 ' 2.0 dB PA gain loss + // dB_sel = b'011 ' 2.5 dB PA gain loss + // dB_sel = b'100 ' 3.0 dB PA gain loss + // dB_sel = b'101 ' 3.5 dB PA gain loss + // dB_sel = b'110 ' 4.0 dB PA gain loss + ODM_Write4Byte(pDM_Odm, 0xe20, 0x00002000); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x148b8000); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0401f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // read back Loopback Gain + // ¥i¥H¦b d40[3:0] ¤¤Åª¦^, dB_sel ¤¤©Ò³]©wªº gain loss ·|¸¨¦b­þ¤@­Ó Tx AGC ³]©w + // Ū¦^d00[3:0] = h'1 ' Tx AGC = h'13 + // Ū¦^d00[3:0] = h'2 ' Tx AGC = h'14 + // Ū¦^d00[3:0] = h'3 ' Tx AGC = h'15 + // Ū¦^d00[3:0] = h'4 ' Tx AGC = h'16 + // Ū¦^d00[3:0] = h'5 ' Tx AGC = h'17 + // Ū¦^d00[3:0] = h'6 ' Tx AGC = h'18 + // Ū¦^d00[3:0] = h'7 ' Tx AGC = h'19 + // Ū¦^d00[3:0] = h'8 ' Tx AGC = h'1a + // Ū¦^d00[3:0] = h'9 ' Tx AGC = h'1b + // Ū¦^d00[3:0] = h'a ' Tx AGC = h'1c + // + Reg0xD40 = ODM_Read4Byte(pDM_Odm, 0xd40); + switch (ODM_Read4Byte(pDM_Odm, 0xd40) & (BIT3|BIT2|BIT1|BIT0)) + { + case 0x0: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x2; break; + case 0x1: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x3; break; + case 0x2: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x4; break; + case 0x3: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x5; break; + case 0x4: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x6; break; + case 0x5: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x7; break; + case 0x6: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x8; break; + case 0x7: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0x9; break; + case 0x8: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xa; break; + case 0x9: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xb; break; + case 0xa: pRFCalibrateInfo->DpkTxAGC = 0x50bf0 | 0xc; break; + } + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_GainLossToFindTxAGC\n")); +} + + +BOOLEAN +_DPK_AdjustRFGainByFoundTxAGC_PathB +( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + s4Byte tmpLBGain = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_AdjustRFGainByFoundTxAGC\n")); + + // RF setting, ­«·s³]©wRF reg00, Á|¨Ò¥ÎDPK Phase 2±o¨ìªº d40[3:0] = 0x6 ' TX AGC= 0x18 ' RF reg00[4:0] = 0x18 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); + // Attn: A mode @ reg64[2:0], G mode @ reg56 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x64, bRFRegOffsetMask, 0x19aac); + // PGA gain: RF reg8f[14:13] + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8a001); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76c9f84); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x11838000); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); + + // one shot + ODM_Write4Byte(pDM_Odm, 0xec8, 0x800c5599); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x000c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33d8d); + + + tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); + + if (tmpLBGain < 263390) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'11 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x8e001); + _FineTuneLoopBackGain_PathB(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); + } + else if (tmpLBGain > 661607) + { + // coarse tune loopback gain by RF reg8f[14:13] = 2b'00 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); + _FineTuneLoopBackGain_PathB(pDM_Odm, pRFCalibrateInfo->DpkTxAGC); + } + else + pRFCalibrateInfo->bDPKFail = FALSE;//Go to DPK Phase 4 + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_AdjustRFGainByFoundTxAGC\n")); + + return pRFCalibrateInfo->bDPKFail ? FALSE : TRUE; + +} + + +VOID +_DPK_DoAutoDPK_PathB( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u4Byte tmpLBGain = 0, reg0xD40 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_DoAutoDPK\n")); + + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + // RF setting, ¦¹³BRF reg00, »P DPK Phase 3 ¤@­P + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, pRFCalibrateInfo->DpkTxAGC); + // Baseband Data Rate setting + ODM_Write4Byte(pDM_Odm, 0xe20, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe24, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe28, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe2c, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe30, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe34, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe38, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe3c, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe40, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe44, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe48, 0x3c3c3c3c); + ODM_Write4Byte(pDM_Odm, 0xe4c, 0x3c3c3c3c); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // DPK setting + ODM_Write4Byte(pDM_Odm, 0xe94, 0xf76C9f84); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x400C5599); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x11938080); //0xec4[9:4]= DPk fail threshold + + if ( 36 <= *(pDM_Odm->pChannel) && *(pDM_Odm->pChannel) <= 53)//Channelchannel at low band) + // r_agc + ODM_Write4Byte(pDM_Odm, 0xebc, 0x00022a1f); + else + // r_agc + ODM_Write4Byte(pDM_Odm, 0xebc, 0x00009dbf); + + // ª`·Npage c1ªºc90¦bDPK¹Lµ{¤¤¤d¸U¤£¯à³Q¨ä¥Lthread or process§ï¼g¦¨page cªºc90­È + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0101f018); // TODO: 0xe90(rA_LSSIWrite_Jaguar) can not be overwritten. + + // one shot + ODM_Write4Byte(pDM_Odm, 0xec8, 0xc00c5599); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x400c5599); + // delay 50 ms,Åý delay ®É¶¡ªø¤@ÂI, ½T©w PA Scan function ¦³°µ§¹ + delay_ms(50); + + // reg82c[31] = 0 --> ¤Á¨ì page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + // T-meter RFReg42[17] = 1 to enable read T-meter, [15:10] ' T-meter value + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, BIT17, 1); + pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x42, 0xFC00); // Ū¥X42[15:10] ­È¨Ã¦s¨ìÅܼÆTMeter + DbgPrint("pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] = 0x%X\n", pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x00, bRFRegOffsetMask, 0x33D8D); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + // read back dp_fail report + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x00000000); + //dp_fail³o­Óbit¦bd40[6], ·í d40[6] = 1, ªí¥Ücalibration¥¢±Ñ. + reg0xD40 = ODM_Read4Byte(pDM_Odm, 0xd40); + + if ((reg0xD40 & BIT6) == BIT6) { + //printf('DPK fail') + pRFCalibrateInfo->bDPKFail = TRUE; + //Go to DPK Phase 5 + } else { + //printf('DPK success') + } + + + // read back + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0201f01f); + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x0c000000); + + // reg82c[31] = 1 --> ¤Á¨ì page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + // ­pºâtmpGainLoss ¥Î¨ìªºfunction hex2dec() ¬O±N twos complementªº¤Q¤»¶i¦ìÂন¤Q¶i¦ì, ¤Q¤»¶i¦ìªº®æ¦¡¬°s11.9 + // Á|¨Ò1, d00[10:0] = h'3ff, ¸g¹L hex2dec(h'3ff) = 1023, + // Á|¨Ò2, d00[10:0] = h'400, ¸g¹L hex2dec(h'400) = -1024, + // Á|¨Ò3, d00[10:0] = h'0A9, ¸g¹L hex2dec(h'0A9) = 169, + // Á|¨Ò4, d00[10:0] = h'54c, ¸g¹L hex2dec(h'54c) = -692, + // Á|¨Ò4, d00[10:0] = h'7ff, ¸g¹L hex2dec(h'7ff) = -1, + tmpLBGain = _ComputeLoopBackGain_PathB(pDM_Odm); + + + // Gain Scaling + if (227007 < tmpLBGain) + pRFCalibrateInfo->DpkGain = 0x43ca43ca; + else if (214309 < tmpLBGain && tmpLBGain <= 227007) + pRFCalibrateInfo->DpkGain = 0x45c545c5; + else if (202321 < tmpLBGain && tmpLBGain <= 214309) + pRFCalibrateInfo->DpkGain = 0x47cf47cf; + else if (191003 < tmpLBGain && tmpLBGain <= 202321) + pRFCalibrateInfo->DpkGain = 0x49e749e7; + else if (180318 < tmpLBGain && tmpLBGain <= 191003) + pRFCalibrateInfo->DpkGain = 0x4c104c10; + else if (170231 < tmpLBGain && tmpLBGain <= 180318) + pRFCalibrateInfo->DpkGain = 0x4e494e49; + else if (160709 < tmpLBGain && tmpLBGain <= 170231) + pRFCalibrateInfo->DpkGain = 0x50925092; + else if (151719 < tmpLBGain && tmpLBGain <= 160709) + pRFCalibrateInfo->DpkGain = 0x52ec52ec; + else if (151719 <= tmpLBGain) + pRFCalibrateInfo->DpkGain = 0x55585558; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_DoAutoDPK\n")); +} + + +VOID +_DPK_EnableDP_PathB( + IN PDM_ODM_T pDM_Odm + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> _DPK_EnableDP\n")); + + // [31] = 1 --> switch to page C1 + ODM_Write4Byte(pDM_Odm, 0x82c, 0x802083dd); + + // enable IQC matrix --> ¦]¬° BB «H¸¹·|¥ý¸g¹L predistortion module, ¤~¸g¹L IQC matrix ¨ì DAC ¥´¥X¥h + // ©Ò¥H­n¥ý enable predistortion module {c90[7] = 1 (enable_predis) cc4[18] = 1 (½T©wÅý IQK/DPK module ¦³clock), cc8[29] = 1 (¤@­ÓIQK/DPK module ¸Ìªºmux, ½T»{ data path ¨«IQK/DPK)} + ODM_Write4Byte(pDM_Odm, 0xe90, 0x0000f098); + ODM_Write4Byte(pDM_Odm, 0xe94, 0x776d9f84); + ODM_Write4Byte(pDM_Odm, 0xec8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xe8c, 0x3c000000); + // r_bnd + ODM_Write4Byte(pDM_Odm, 0xeb8, 0x000fffff); + + if (pRFCalibrateInfo->bDPKFail) + { + // cc4[29] = 1 (bypass DP LUT) + ODM_Write4Byte(pDM_Odm, 0xe98, 0x40004000); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x28840000); + } + else + { + ODM_Write4Byte(pDM_Odm, 0xe98, pRFCalibrateInfo->DpkGain); + ODM_Write4Byte(pDM_Odm, 0xec4, 0x08840000); + + // PWSF + // ¼gPWSF table in 1st SRAM for PA = 11 use + ODM_Write4Byte(pDM_Odm, 0xe20, 0x00000800); + + //******************************************************* + //0xee4[0]¬Owrite enable¡A0xee4[7:1]¬Oaddress¡A0xee4[15:8]©M0xee4[23:16]¹ïÀ³¨ìTX index¡A + //­Y¦ì¸m¬°0(0xee4[7:1] = 0x0)¦¹®É0xee4[15:8]¹ïÀ³¨ìªºTX RF index ¬O0x1f,¡A + //0xee4[23:16]¹ïÀ³¨ìªº¬O0x1e¡A­Y¦ì¸m¬°1(0xee4[7:1] = 0x1)¡A¦¹®É0xee4 [15:8]¹ïÀ³¨ì0x1d¡A + //0xee4[23:16]¹ïÀ³0x1c¡A¨ä¥L¨Ì¦¹Ãþ±À¡A¨C­ÓdataÄæ¦ì³£¬O¬Û®t1dB¡C­Ygainloss§ä¨ìªºRF TX index=0x18¡A + //«h¦b0xee4 address¹ïÀ³¨ì0x18ªº¦a¤è­n¶ñ0x40(¤]´N¬O0dB)¡A¨ä¥L«h·Ó¤U­±tableªº¶¶§Ç¨C®æ1dB¨Ì§Ç±Æ¦C + //±N©Ò¦³ªº0xee4cªºdataÄæ¦ì³£¶ñ¤J¬Û¹ïÀ³ªº­È¡C + //*************************************************************// + + { + const s4Byte LEN = 25; + u4Byte baseIdx = 6; // 0 dB: 0x40 + u4Byte TablePWSF[] = { + 0xff, 0xca, 0xa1, 0x80, 0x65, 0x51, 0x40/* 0 dB */, + 0x33, 0x28, 0x20, 0x19, 0x14, 0x10, + 0x0d, 0x0a, 0x08, 0x06, 0x05, 0x04, + 0x03, 0x03, 0x02, 0x02, 0x01, 0x01 + }; + + u4Byte centerTxIdx = pRFCalibrateInfo->DpkTxAGC & 0x1F; + u4Byte centerAddr = (0x1F-centerTxIdx) / 2; + s4Byte i = 0, j = 0, value = 0, startIdx = 0; + + // Upper + startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+1 : baseIdx); + + for (i = startIdx, j = 0; (centerAddr-j+1) >= 1; i -= 2, j++) { + if (i-1 < 0) + value = (TablePWSF[0] << 16) | (TablePWSF[0] << 8) | ((centerAddr-j) << 1) | 0x1; + else + value = (TablePWSF[i] << 16) | (TablePWSF[i-1] << 8) | ((centerAddr-j) << 1) | 0x1; + + ODM_Write4Byte(pDM_Odm, 0xee4, value); + ODM_Write1Byte(pDM_Odm, 0xee4, 0x0); //write disable + } + + // Lower + startIdx = (((0x1F-centerTxIdx)%2 == 0) ? baseIdx+2 : baseIdx+1); + centerAddr++; // Skip centerTxIdx + for (i = startIdx, j = 0; (centerAddr+j) < 16; i += 2, j++) { // Total: 16*2 = 32 values (Upper+Lower) + if (i+1 >= LEN) + value = (TablePWSF[LEN-1] << 16) | (TablePWSF[LEN-1] << 8) | ((centerAddr+j) << 1) | 0x1; + else + value = (TablePWSF[i+1] << 16) | (TablePWSF[i] << 8) | ((centerAddr+j) << 1) | 0x1; + ODM_Write4Byte(pDM_Odm, 0xee4, value); + ODM_Write1Byte(pDM_Odm, 0xee4, 0x0); //write disable + } + } + } + // [31] = 0 --> switch to page C + ODM_Write4Byte(pDM_Odm, 0x82c, 0x002083dd); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== _DPK_EnableDP\n")); + +} + + + + + +VOID +phy_DPCalibrate_PathB_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte backupMacBBRegAddrs[] = { + 0xE60, 0xE64, 0xC68, 0x82C, 0x838, 0x90C, 0x522, 0xE00, 0xE20, 0xE24, // 10 + 0xE28, 0xE2C, 0xE30, 0xE34, 0xE38, 0xE3C, 0xE40, 0xE44, 0xE48, 0xE4C, // 20 + 0xE94, 0xEB0, 0xEB4 + }; + u4Byte backupRFRegAddrs[] = {0x00, 0x64, 0x8F}; + + u4Byte backupMacBBRegData[sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)]; + u4Byte backupRFRegData_A[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; + //u4Byte backupRFRegData_B[sizeof(backupRFRegAddrs)/sizeof(u4Byte)]; + + + _DPK_MacBBBackup_PathB(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); + _DPK_RFBackup_PathB(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_B, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); + + _DPK_Init_PathB(pDM_Odm); + + if (_DPK_AdjustRFGain_PathB(pDM_Odm)) { // Phase 1 + _DPK_GainLossToFindTxAGC_PathB(pDM_Odm); // Phase 2 + if (_DPK_AdjustRFGainByFoundTxAGC_PathB(pDM_Odm)) // Phase 3 + _DPK_DoAutoDPK_PathB(pDM_Odm); // Phase 4 + } + _DPK_EnableDP_PathB(pDM_Odm); // Phase 5 + + _DPK_MacBBRestore_PathB(pDM_Odm, backupMacBBRegAddrs, backupMacBBRegData, sizeof(backupMacBBRegAddrs)/sizeof(u4Byte)); + _DPK_RFRestore_PathB(pDM_Odm, backupRFRegAddrs, ODM_RF_PATH_B, backupRFRegData_A, sizeof(backupRFRegAddrs)/sizeof(u4Byte)); +} +VOID +PHY_DPCalibrate_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + pDM_Odm->DPK_Done = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_DPCalibrate_8812A\n")); + phy_DPCalibrate_PathA_8812A(pDM_Odm); + phy_DPCalibrate_PathB_8812A(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_DPCalibrate_8812A\n")); +} + + + + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.h b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.h index ec218b93fbd..d2762496463 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/halphyrf_8812a_win.h @@ -1,106 +1,106 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8812A_H__ -#define __HAL_PHY_RF_8812A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8812A 10 //ms -#define IQK_DEFERRED_TIME_8812A 4 //sec -#define index_mapping_NUM_8812A 15 -#define AVG_THERMAL_NUM_8812A 4 -#define RF_T_METER_8812A 0x42 - - -void ConfigureTxpowerTrack_8812A( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8812A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -void DoIQK_8812A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr8812A( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8812A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery -); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8812A( - IN PVOID pDM_VOID -); - -// -// AP calibrate -// -void -PHY_APCalibrate_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); - -VOID -PHY_DPCalibrate_8812A( - IN PDM_ODM_T pDM_Odm -); -VOID PHY_SetRFPathSwitch_8812A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - - -#endif // #ifndef __HAL_PHY_RF_8812A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8812A_H__ +#define __HAL_PHY_RF_8812A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8812A 10 //ms +#define IQK_DEFERRED_TIME_8812A 4 //sec +#define index_mapping_NUM_8812A 15 +#define AVG_THERMAL_NUM_8812A 4 +#define RF_T_METER_8812A 0x42 + + +void ConfigureTxpowerTrack_8812A( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8812A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +void DoIQK_8812A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr8812A( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8812A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery +); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8812A( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8812A( IN PADAPTER pAdapter); + +VOID +PHY_DPCalibrate_8812A( + IN PDM_ODM_T pDM_Odm +); +VOID PHY_SetRFPathSwitch_8812A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + + +#endif // #ifndef __HAL_PHY_RF_8812A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.c b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.c index 5e74ffad1e3..18e4671de26 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.c @@ -1,195 +1,195 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8812A_SUPPORT == 1) - -void -odm_ConfigRFReg_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if (Addr == 0xfe || Addr == 0xffe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } -} - - -void -odm_ConfigRF_RadioA_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else { -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#else /* #if (RTL8812A_SUPPORT == 1) */ -void -odm_ConfigRFReg_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ){} - -#endif /* #if (RTL8812A_SUPPORT == 1) */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8812A_SUPPORT == 1) + +void +odm_ConfigRFReg_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if (Addr == 0xfe || Addr == 0xffe) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#else /* #if (RTL8812A_SUPPORT == 1) */ +void +odm_ConfigRFReg_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ){} + +#endif /* #if (RTL8812A_SUPPORT == 1) */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.h b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.h index 7db8233e542..0269e5b6e39 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_regconfig8812a.h @@ -1,96 +1,96 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8812A -#define __INC_ODM_REGCONFIG_H_8812A - -#if (RTL8812A_SUPPORT == 1) - -void -odm_ConfigRFReg_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8812A +#define __INC_ODM_REGCONFIG_H_8812A + +#if (RTL8812A_SUPPORT == 1) + +void +odm_ConfigRFReg_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.c b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.c index 28d3c91f263..205a1c2053b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.c @@ -1,161 +1,161 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" - -#include "../phydm_precomp.h" - -#if (RTL8812A_SUPPORT == 1) - -#if(defined(CONFIG_PATH_DIVERSITY)) -VOID -odm_UpdateTxPath_8812A(IN PDM_ODM_T pDM_Odm, IN u1Byte Path) -{ - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - if(pDM_PathDiv->RespTxPath != Path) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Need to Update Tx Path\n")); - - if(Path == ODM_RF_PATH_A) - { - ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg - ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo - } - else - { - ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x222); //Tx by Reg - ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 2); //Resp Tx by Txinfo - } - } - pDM_PathDiv->RespTxPath = Path; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Path=%s\n",(Path==ODM_RF_PATH_A)?"ODM_RF_PATH_A":"ODM_RF_PATH_B")); -} - - -VOID -ODM_PathDiversityInit_8812A( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - ODM_SetBBReg(pDM_Odm, 0x80c , BIT29, 1); //Tx path from Reg - ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg - ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo - odm_UpdateTxPath_8812A(pDM_Odm, ODM_RF_PATH_A); - - for (i=0; iPathSel[i] = 1; // TxInfo default at path-A - } -} - - - -VOID -ODM_PathDiversity_8812A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte i, RssiAvgA=0, RssiAvgB=0, LocalMinRSSI, MinRSSI=0xFF; - u1Byte TxRespPath=0, TargetPath; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - PSTA_INFO_T pEntry; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Odm_PathDiversity_8812A() =>\n")); - - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - //2 Caculate RSSI per Path - RssiAvgA = (pDM_PathDiv->PathA_Cnt[i]!=0)?(pDM_PathDiv->PathA_Sum[i]/pDM_PathDiv->PathA_Cnt[i]):0; - RssiAvgB = (pDM_PathDiv->PathB_Cnt[i]!=0)?(pDM_PathDiv->PathB_Sum[i]/pDM_PathDiv->PathB_Cnt[i]):0; - TargetPath = (RssiAvgA==RssiAvgB)?pDM_PathDiv->RespTxPath:((RssiAvgA>=RssiAvgB)?ODM_RF_PATH_A:ODM_RF_PATH_B); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, PathA_Sum=%d, PathA_Cnt=%d\n", i, pDM_PathDiv->PathA_Sum[i], pDM_PathDiv->PathA_Cnt[i])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, PathB_Sum=%d, PathB_Cnt=%d\n",i, pDM_PathDiv->PathB_Sum[i], pDM_PathDiv->PathB_Cnt[i])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, RssiAvgA= %d, RssiAvgB= %d\n", i, RssiAvgA, RssiAvgB)); - - //2 Select Resp Tx Path - LocalMinRSSI = (RssiAvgA>RssiAvgB)?RssiAvgB:RssiAvgA; - if(LocalMinRSSI < MinRSSI) - { - MinRSSI = LocalMinRSSI; - TxRespPath = TargetPath; - } - - //2 Select Tx DESC - if(TargetPath == ODM_RF_PATH_A) - pDM_PathDiv->PathSel[i] = 1; - else - pDM_PathDiv->PathSel[i] = 2; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetPath=%s\n", - (TargetPath==ODM_RF_PATH_A)?"ODM_RF_PATH_A":"ODM_RF_PATH_B")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_PathDiv->PathSel[%d] = %d\n", i, pDM_PathDiv->PathSel[i])); - - } - pDM_PathDiv->PathA_Cnt[i] = 0; - pDM_PathDiv->PathA_Sum[i] = 0; - pDM_PathDiv->PathB_Cnt[i] = 0; - pDM_PathDiv->PathB_Sum[i] = 0; - } - - //2 Update Tx Path - odm_UpdateTxPath_8812A(pDM_Odm, TxRespPath); - -} - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -ODM_SetTxPathByTxInfo_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN u1Byte macId -) -{ - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - if((pDM_Odm->SupportICType != ODM_RTL8812)||(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))) - return; - - SET_TX_DESC_TX_ANT_8812(pDesc, pDM_PathDiv->PathSel[macId]); -} -#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_SetTxPathByTxInfo_8812A( - IN PDM_ODM_T pDM_Odm -) -{ - -} -#endif - -#endif // CONFIG_PATH_DIVERSITY +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8812A_SUPPORT == 1) + +#if(defined(CONFIG_PATH_DIVERSITY)) +VOID +odm_UpdateTxPath_8812A(IN PDM_ODM_T pDM_Odm, IN u1Byte Path) +{ + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + if(pDM_PathDiv->RespTxPath != Path) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Need to Update Tx Path\n")); + + if(Path == ODM_RF_PATH_A) + { + ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg + ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo + } + else + { + ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x222); //Tx by Reg + ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 2); //Resp Tx by Txinfo + } + } + pDM_PathDiv->RespTxPath = Path; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Path=%s\n",(Path==ODM_RF_PATH_A)?"ODM_RF_PATH_A":"ODM_RF_PATH_B")); +} + + +VOID +ODM_PathDiversityInit_8812A( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + ODM_SetBBReg(pDM_Odm, 0x80c , BIT29, 1); //Tx path from Reg + ODM_SetBBReg(pDM_Odm, 0x80c , 0xFFF0, 0x111); //Tx by Reg + ODM_SetBBReg(pDM_Odm, 0x6d8 , BIT7|BIT6, 1); //Resp Tx by Txinfo + odm_UpdateTxPath_8812A(pDM_Odm, ODM_RF_PATH_A); + + for (i=0; iPathSel[i] = 1; // TxInfo default at path-A + } +} + + + +VOID +ODM_PathDiversity_8812A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i, RssiAvgA=0, RssiAvgB=0, LocalMinRSSI, MinRSSI=0xFF; + u1Byte TxRespPath=0, TargetPath; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + PSTA_INFO_T pEntry; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Odm_PathDiversity_8812A() =>\n")); + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Path + RssiAvgA = (pDM_PathDiv->PathA_Cnt[i]!=0)?(pDM_PathDiv->PathA_Sum[i]/pDM_PathDiv->PathA_Cnt[i]):0; + RssiAvgB = (pDM_PathDiv->PathB_Cnt[i]!=0)?(pDM_PathDiv->PathB_Sum[i]/pDM_PathDiv->PathB_Cnt[i]):0; + TargetPath = (RssiAvgA==RssiAvgB)?pDM_PathDiv->RespTxPath:((RssiAvgA>=RssiAvgB)?ODM_RF_PATH_A:ODM_RF_PATH_B); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, PathA_Sum=%d, PathA_Cnt=%d\n", i, pDM_PathDiv->PathA_Sum[i], pDM_PathDiv->PathA_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, PathB_Sum=%d, PathB_Cnt=%d\n",i, pDM_PathDiv->PathB_Sum[i], pDM_PathDiv->PathB_Cnt[i])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("MacID=%d, RssiAvgA= %d, RssiAvgB= %d\n", i, RssiAvgA, RssiAvgB)); + + //2 Select Resp Tx Path + LocalMinRSSI = (RssiAvgA>RssiAvgB)?RssiAvgB:RssiAvgA; + if(LocalMinRSSI < MinRSSI) + { + MinRSSI = LocalMinRSSI; + TxRespPath = TargetPath; + } + + //2 Select Tx DESC + if(TargetPath == ODM_RF_PATH_A) + pDM_PathDiv->PathSel[i] = 1; + else + pDM_PathDiv->PathSel[i] = 2; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetPath=%s\n", + (TargetPath==ODM_RF_PATH_A)?"ODM_RF_PATH_A":"ODM_RF_PATH_B")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_PathDiv->PathSel[%d] = %d\n", i, pDM_PathDiv->PathSel[i])); + + } + pDM_PathDiv->PathA_Cnt[i] = 0; + pDM_PathDiv->PathA_Sum[i] = 0; + pDM_PathDiv->PathB_Cnt[i] = 0; + pDM_PathDiv->PathB_Sum[i] = 0; + } + + //2 Update Tx Path + odm_UpdateTxPath_8812A(pDM_Odm, TxRespPath); + +} + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxPathByTxInfo_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +) +{ + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + if((pDM_Odm->SupportICType != ODM_RTL8812)||(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))) + return; + + SET_TX_DESC_TX_ANT_8812(pDesc, pDM_PathDiv->PathSel[macId]); +} +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxPathByTxInfo_8812A( + IN PDM_ODM_T pDM_Odm +) +{ + +} +#endif + +#endif // CONFIG_PATH_DIVERSITY #endif //#if (RTL8812A_SUPPORT == 1) \ No newline at end of file diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.h b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.h index 2c3f15a173d..6ffc248b083 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/phydm_rtl8812a.h @@ -1,46 +1,46 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __ODM_RTL8812A_H__ -#define __ODM_RTL8812A_H__ -#if(defined(CONFIG_PATH_DIVERSITY)) - -VOID -ODM_PathStatistics_8812A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte MacId, - IN u4Byte RSSI_A, - IN u4Byte RSSI_B -); - -VOID -ODM_PathDiversityInit_8812A( IN PDM_ODM_T pDM_Odm); - -VOID -ODM_PathDiversity_8812A( IN PDM_ODM_T pDM_Odm); - -VOID -ODM_SetTxPathByTxInfo_8812A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN u1Byte macId -); - #endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_RTL8812A_H__ +#define __ODM_RTL8812A_H__ +#if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +ODM_PathStatistics_8812A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte MacId, + IN u4Byte RSSI_A, + IN u4Byte RSSI_B +); + +VOID +ODM_PathDiversityInit_8812A( IN PDM_ODM_T pDM_Odm); + +VOID +ODM_PathDiversity_8812A( IN PDM_ODM_T pDM_Odm); + +VOID +ODM_SetTxPathByTxInfo_8812A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +); + #endif #endif \ No newline at end of file diff --git a/package/kernel/rtl8192cd/phydm/rtl8812a/version_rtl8812a.h b/package/kernel/rtl8192cd/phydm/rtl8812a/version_rtl8812a.h index 2a7954cdd87..f2062c299d2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8812a/version_rtl8812a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8812a/version_rtl8812a.h @@ -1,10 +1,10 @@ -/*RTL8812A PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8812A 20150920 -#define COMMIT_BY_8812A "BB_LUKE" -#define RELEASE_VERSION_8812A 57 +/*RTL8812A PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8812A 20150920 +#define COMMIT_BY_8812A "BB_LUKE" +#define RELEASE_VERSION_8812A 57 diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/hal8814areg_odm.h b/package/kernel/rtl8192cd/phydm/rtl8814a/hal8814areg_odm.h index d7352cbfc1e..1cd40304ae0 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/hal8814areg_odm.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/hal8814areg_odm.h @@ -1,47 +1,47 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -//============================================================ -/* File Name: hal8814areg_odm.h */ -// -// Description: -// -// This file is for RTL8814A register definition. -// -// -//============================================================ -#ifndef __HAL_8814A_REG_H__ -#define __HAL_8814A_REG_H__ - -// -// Register Definition -// -#define TRX_ANTDIV_PATH 0x860 -#define RX_ANTDIV_PATH 0xb2c -#define ODM_R_A_AGC_CORE1_8814A 0xc50 - - -// -// Bitmap Definition -// -#define BIT_FA_RESET_8814A BIT0 - - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +/* File Name: hal8814areg_odm.h */ +// +// Description: +// +// This file is for RTL8814A register definition. +// +// +//============================================================ +#ifndef __HAL_8814A_REG_H__ +#define __HAL_8814A_REG_H__ + +// +// Register Definition +// +#define TRX_ANTDIV_PATH 0x860 +#define RX_ANTDIV_PATH 0xb2c +#define ODM_R_A_AGC_CORE1_8814A 0xc50 + + +// +// Bitmap Definition +// +#define BIT_FA_RESET_8814A BIT0 + + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.c index 46dcb0bf2ce..d005000220c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.c @@ -1,6947 +1,6947 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_AGC_TAB[] = { - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000003, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xCF240003, - 0x81C, 0xCE260003, - 0x81C, 0xCD280003, - 0x81C, 0xCC2A0003, - 0x81C, 0xCB2C0003, - 0x81C, 0xCA2E0003, - 0x81C, 0xC9300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xC43A0003, - 0x81C, 0xA63C0003, - 0x81C, 0xA53E0003, - 0x81C, 0xA4400003, - 0x81C, 0xA3420003, - 0x81C, 0xA2440003, - 0x81C, 0xA1460003, - 0x81C, 0x86480003, - 0x81C, 0x854A0003, - 0x81C, 0x844C0003, - 0x81C, 0x834E0003, - 0x81C, 0x66500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x435C0003, - 0x81C, 0x425E0003, - 0x81C, 0x41600003, - 0x81C, 0x27620003, - 0x81C, 0x26640003, - 0x81C, 0x25660003, - 0x81C, 0x24680003, - 0x81C, 0x236A0003, - 0x81C, 0x226C0003, - 0x81C, 0x216E0003, - 0x81C, 0x21700003, - 0x81C, 0x21720003, - 0x81C, 0x21740003, - 0x81C, 0x21760003, - 0x81C, 0x21780003, - 0x81C, 0x217A0003, - 0x81C, 0x217C0003, - 0x81C, 0x217E0003, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFE020003, - 0x81C, 0xFD040003, - 0x81C, 0xFC060003, - 0x81C, 0xFB080003, - 0x81C, 0xFA0A0003, - 0x81C, 0xF90C0003, - 0x81C, 0xF80E0003, - 0x81C, 0xF7100003, - 0x81C, 0xF6120003, - 0x81C, 0xF5140003, - 0x81C, 0xF4160003, - 0x81C, 0xF3180003, - 0x81C, 0xF21A0003, - 0x81C, 0xF11C0003, - 0x81C, 0xF01E0003, - 0x81C, 0xEF200003, - 0x81C, 0xEE220003, - 0x81C, 0xED240003, - 0x81C, 0xEC260003, - 0x81C, 0xEB280003, - 0x81C, 0xEA2A0003, - 0x81C, 0xE92C0003, - 0x81C, 0xE82E0003, - 0x81C, 0xE7300003, - 0x81C, 0xE6320003, - 0x81C, 0xE5340003, - 0x81C, 0xE4360003, - 0x81C, 0xE3380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xA8440003, - 0x81C, 0xA7460003, - 0x81C, 0xA6480003, - 0x81C, 0xA54A0003, - 0x81C, 0xA44C0003, - 0x81C, 0xA34E0003, - 0x81C, 0xA2500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x475C0003, - 0x81C, 0x465E0003, - 0x81C, 0x45600003, - 0x81C, 0x44620003, - 0x81C, 0x43640003, - 0x81C, 0x42660003, - 0x81C, 0x41680003, - 0x81C, 0x416A0003, - 0x81C, 0x416C0003, - 0x81C, 0x416E0003, - 0x81C, 0x41700003, - 0x81C, 0x41720003, - 0x81C, 0x41740003, - 0x81C, 0x41760003, - 0x81C, 0x41780003, - 0x81C, 0x417A0003, - 0x81C, 0x417C0003, - 0x81C, 0x417E0003, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xEC240003, - 0x81C, 0xEB260003, - 0x81C, 0xEA280003, - 0x81C, 0xE92A0003, - 0x81C, 0xE82C0003, - 0x81C, 0xE72E0003, - 0x81C, 0xE6300003, - 0x81C, 0xE5320003, - 0x81C, 0xE4340003, - 0x81C, 0xE3360003, - 0x81C, 0xC6380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xA9420003, - 0x81C, 0xA8440003, - 0x81C, 0xA7460003, - 0x81C, 0xA6480003, - 0x81C, 0xA54A0003, - 0x81C, 0xA44C0003, - 0x81C, 0xA34E0003, - 0x81C, 0x66500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x49580003, - 0x81C, 0x485A0003, - 0x81C, 0x475C0003, - 0x81C, 0x465E0003, - 0x81C, 0x45600003, - 0x81C, 0x44620003, - 0x81C, 0x43640003, - 0x81C, 0x42660003, - 0x81C, 0x41680003, - 0x81C, 0x416A0003, - 0x81C, 0x416C0003, - 0x81C, 0x416E0003, - 0x81C, 0x41700003, - 0x81C, 0x41720003, - 0x81C, 0x41740003, - 0x81C, 0x41760003, - 0x81C, 0x41780003, - 0x81C, 0x417A0003, - 0x81C, 0x417C0003, - 0x81C, 0x417E0003, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFE020003, - 0x81C, 0xFD040003, - 0x81C, 0xFC060003, - 0x81C, 0xFB080003, - 0x81C, 0xFA0A0003, - 0x81C, 0xF90C0003, - 0x81C, 0xF80E0003, - 0x81C, 0xF7100003, - 0x81C, 0xF6120003, - 0x81C, 0xF5140003, - 0x81C, 0xF4160003, - 0x81C, 0xF3180003, - 0x81C, 0xF21A0003, - 0x81C, 0xF11C0003, - 0x81C, 0xF01E0003, - 0x81C, 0xEF200003, - 0x81C, 0xEE220003, - 0x81C, 0xED240003, - 0x81C, 0xEC260003, - 0x81C, 0xEB280003, - 0x81C, 0xEA2A0003, - 0x81C, 0xE92C0003, - 0x81C, 0xE82E0003, - 0x81C, 0xE7300003, - 0x81C, 0xE6320003, - 0x81C, 0xE5340003, - 0x81C, 0xE4360003, - 0x81C, 0xE3380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xA8440003, - 0x81C, 0xA7460003, - 0x81C, 0xA6480003, - 0x81C, 0xA54A0003, - 0x81C, 0xA44C0003, - 0x81C, 0xA34E0003, - 0x81C, 0xA2500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x475C0003, - 0x81C, 0x465E0003, - 0x81C, 0x45600003, - 0x81C, 0x44620003, - 0x81C, 0x43640003, - 0x81C, 0x42660003, - 0x81C, 0x41680003, - 0x81C, 0x416A0003, - 0x81C, 0x416C0003, - 0x81C, 0x416E0003, - 0x81C, 0x41700003, - 0x81C, 0x41720003, - 0x81C, 0x41740003, - 0x81C, 0x41760003, - 0x81C, 0x41780003, - 0x81C, 0x417A0003, - 0x81C, 0x417C0003, - 0x81C, 0x417E0003, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xEC240003, - 0x81C, 0xEB260003, - 0x81C, 0xEA280003, - 0x81C, 0xE92A0003, - 0x81C, 0xE82C0003, - 0x81C, 0xE72E0003, - 0x81C, 0xE6300003, - 0x81C, 0xE5320003, - 0x81C, 0xE4340003, - 0x81C, 0xE3360003, - 0x81C, 0xC6380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xA9420003, - 0x81C, 0xA8440003, - 0x81C, 0xA7460003, - 0x81C, 0xA6480003, - 0x81C, 0xA54A0003, - 0x81C, 0xA44C0003, - 0x81C, 0xA34E0003, - 0x81C, 0x66500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x49580003, - 0x81C, 0x485A0003, - 0x81C, 0x475C0003, - 0x81C, 0x465E0003, - 0x81C, 0x45600003, - 0x81C, 0x44620003, - 0x81C, 0x43640003, - 0x81C, 0x42660003, - 0x81C, 0x41680003, - 0x81C, 0x416A0003, - 0x81C, 0x416C0003, - 0x81C, 0x416E0003, - 0x81C, 0x41700003, - 0x81C, 0x41720003, - 0x81C, 0x41740003, - 0x81C, 0x41760003, - 0x81C, 0x41780003, - 0x81C, 0x417A0003, - 0x81C, 0x417C0003, - 0x81C, 0x417E0003, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xDF000003, - 0x81C, 0xDF020003, - 0x81C, 0xDF040003, - 0x81C, 0xDE060003, - 0x81C, 0xDD080003, - 0x81C, 0xDC0A0003, - 0x81C, 0xDB0C0003, - 0x81C, 0xDA0E0003, - 0x81C, 0xD9100003, - 0x81C, 0xD8120003, - 0x81C, 0xD7140003, - 0x81C, 0xD6160003, - 0x81C, 0xD5180003, - 0x81C, 0xD41A0003, - 0x81C, 0xD31C0003, - 0x81C, 0xD21E0003, - 0x81C, 0xD1200003, - 0x81C, 0xD0220003, - 0x81C, 0xCF240003, - 0x81C, 0xCE260003, - 0x81C, 0xCD280003, - 0x81C, 0xCC2A0003, - 0x81C, 0xCB2C0003, - 0x81C, 0xCA2E0003, - 0x81C, 0xC9300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xA73A0003, - 0x81C, 0xA63C0003, - 0x81C, 0xA53E0003, - 0x81C, 0xA4400003, - 0x81C, 0xA3420003, - 0x81C, 0xA2440003, - 0x81C, 0x87460003, - 0x81C, 0x86480003, - 0x81C, 0x854A0003, - 0x81C, 0x844C0003, - 0x81C, 0x834E0003, - 0x81C, 0x82500003, - 0x81C, 0x81520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x445C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x27640003, - 0x81C, 0x26660003, - 0x81C, 0x25680003, - 0x81C, 0x246A0003, - 0x81C, 0x236C0003, - 0x81C, 0x226E0003, - 0x81C, 0x21700003, - 0x81C, 0x21720003, - 0x81C, 0x21740003, - 0x81C, 0x21760003, - 0x81C, 0x21780003, - 0x81C, 0x217A0003, - 0x81C, 0x217C0003, - 0x81C, 0x217E0003, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFE020003, - 0x81C, 0xFD040003, - 0x81C, 0xFC060003, - 0x81C, 0xFB080003, - 0x81C, 0xFA0A0003, - 0x81C, 0xF90C0003, - 0x81C, 0xF80E0003, - 0x81C, 0xF7100003, - 0x81C, 0xF6120003, - 0x81C, 0xF5140003, - 0x81C, 0xF4160003, - 0x81C, 0xF3180003, - 0x81C, 0xF21A0003, - 0x81C, 0xF11C0003, - 0x81C, 0xF01E0003, - 0x81C, 0xEF200003, - 0x81C, 0xEE220003, - 0x81C, 0xED240003, - 0x81C, 0xEC260003, - 0x81C, 0xEB280003, - 0x81C, 0xEA2A0003, - 0x81C, 0xE92C0003, - 0x81C, 0xE82E0003, - 0x81C, 0xE7300003, - 0x81C, 0xE6320003, - 0x81C, 0xE5340003, - 0x81C, 0xE4360003, - 0x81C, 0xE3380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xA8440003, - 0x81C, 0xA7460003, - 0x81C, 0xA6480003, - 0x81C, 0xA54A0003, - 0x81C, 0xA44C0003, - 0x81C, 0xA34E0003, - 0x81C, 0xA2500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x475C0003, - 0x81C, 0x465E0003, - 0x81C, 0x45600003, - 0x81C, 0x44620003, - 0x81C, 0x43640003, - 0x81C, 0x42660003, - 0x81C, 0x41680003, - 0x81C, 0x416A0003, - 0x81C, 0x416C0003, - 0x81C, 0x416E0003, - 0x81C, 0x41700003, - 0x81C, 0x41720003, - 0x81C, 0x41740003, - 0x81C, 0x41760003, - 0x81C, 0x41780003, - 0x81C, 0x417A0003, - 0x81C, 0x417C0003, - 0x81C, 0x417E0003, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xDF000003, - 0x81C, 0xDF020003, - 0x81C, 0xDF040003, - 0x81C, 0xDE060003, - 0x81C, 0xDD080003, - 0x81C, 0xDC0A0003, - 0x81C, 0xDB0C0003, - 0x81C, 0xDA0E0003, - 0x81C, 0xD9100003, - 0x81C, 0xD8120003, - 0x81C, 0xD7140003, - 0x81C, 0xD6160003, - 0x81C, 0xD5180003, - 0x81C, 0xD41A0003, - 0x81C, 0xD31C0003, - 0x81C, 0xD21E0003, - 0x81C, 0xD1200003, - 0x81C, 0xD0220003, - 0x81C, 0xCF240003, - 0x81C, 0xCE260003, - 0x81C, 0xCD280003, - 0x81C, 0xCC2A0003, - 0x81C, 0xCB2C0003, - 0x81C, 0xCA2E0003, - 0x81C, 0xC9300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xA73A0003, - 0x81C, 0xA63C0003, - 0x81C, 0xA53E0003, - 0x81C, 0xA4400003, - 0x81C, 0xA3420003, - 0x81C, 0xA2440003, - 0x81C, 0x87460003, - 0x81C, 0x86480003, - 0x81C, 0x854A0003, - 0x81C, 0x844C0003, - 0x81C, 0x834E0003, - 0x81C, 0x82500003, - 0x81C, 0x81520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x445C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x27640003, - 0x81C, 0x26660003, - 0x81C, 0x25680003, - 0x81C, 0x246A0003, - 0x81C, 0x236C0003, - 0x81C, 0x226E0003, - 0x81C, 0x21700003, - 0x81C, 0x21720003, - 0x81C, 0x21740003, - 0x81C, 0x21760003, - 0x81C, 0x21780003, - 0x81C, 0x217A0003, - 0x81C, 0x217C0003, - 0x81C, 0x217E0003, - 0xA0000000, 0x00000000, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xCF240003, - 0x81C, 0xCE260003, - 0x81C, 0xCD280003, - 0x81C, 0xCC2A0003, - 0x81C, 0xCB2C0003, - 0x81C, 0xCA2E0003, - 0x81C, 0xC9300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xC43A0003, - 0x81C, 0xA63C0003, - 0x81C, 0xA53E0003, - 0x81C, 0xA4400003, - 0x81C, 0xA3420003, - 0x81C, 0xA2440003, - 0x81C, 0xA1460003, - 0x81C, 0x86480003, - 0x81C, 0x854A0003, - 0x81C, 0x844C0003, - 0x81C, 0x834E0003, - 0x81C, 0x66500003, - 0x81C, 0x65520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x615A0003, - 0x81C, 0x435C0003, - 0x81C, 0x425E0003, - 0x81C, 0x41600003, - 0x81C, 0x27620003, - 0x81C, 0x26640003, - 0x81C, 0x25660003, - 0x81C, 0x24680003, - 0x81C, 0x236A0003, - 0x81C, 0x226C0003, - 0x81C, 0x216E0003, - 0x81C, 0x21700003, - 0x81C, 0x21720003, - 0x81C, 0x21740003, - 0x81C, 0x21760003, - 0x81C, 0x21780003, - 0x81C, 0x217A0003, - 0x81C, 0x217C0003, - 0x81C, 0x217E0003, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000103, - 0x81C, 0xF8020103, - 0x81C, 0xF7040103, - 0x81C, 0xF6060103, - 0x81C, 0xF5080103, - 0x81C, 0xF40A0103, - 0x81C, 0xF30C0103, - 0x81C, 0xF20E0103, - 0x81C, 0xF1100103, - 0x81C, 0xF0120103, - 0x81C, 0xEF140103, - 0x81C, 0xEE160103, - 0x81C, 0xED180103, - 0x81C, 0xEC1A0103, - 0x81C, 0xEB1C0103, - 0x81C, 0xEA1E0103, - 0x81C, 0xE9200103, - 0x81C, 0xE8220103, - 0x81C, 0xE7240103, - 0x81C, 0xE6260103, - 0x81C, 0xE5280103, - 0x81C, 0xE42A0103, - 0x81C, 0xE32C0103, - 0x81C, 0xC32E0103, - 0x81C, 0xC2300103, - 0x81C, 0xC1320103, - 0x81C, 0xA5340103, - 0x81C, 0xA4360103, - 0x81C, 0xA3380103, - 0x81C, 0xA23A0103, - 0x81C, 0xA13C0103, - 0x81C, 0x843E0103, - 0x81C, 0x83400103, - 0x81C, 0x82420103, - 0x81C, 0x81440103, - 0x81C, 0x64460103, - 0x81C, 0x63480103, - 0x81C, 0x624A0103, - 0x81C, 0x614C0103, - 0x81C, 0x444E0103, - 0x81C, 0x43500103, - 0x81C, 0x42520103, - 0x81C, 0x41540103, - 0x81C, 0x25560103, - 0x81C, 0x24580103, - 0x81C, 0x235A0103, - 0x81C, 0x065C0103, - 0x81C, 0x055E0103, - 0x81C, 0x04600103, - 0x81C, 0x03620103, - 0x81C, 0x02640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xE22C0103, - 0x81C, 0xE12E0103, - 0x81C, 0xA5300103, - 0x81C, 0xA4320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0x843A0103, - 0x81C, 0x833C0103, - 0x81C, 0x823E0103, - 0x81C, 0x81400103, - 0x81C, 0x64420103, - 0x81C, 0x63440103, - 0x81C, 0x62460103, - 0x81C, 0x61480103, - 0x81C, 0x454A0103, - 0x81C, 0x444C0103, - 0x81C, 0x434E0103, - 0x81C, 0x42500103, - 0x81C, 0x25520103, - 0x81C, 0x24540103, - 0x81C, 0x23560103, - 0x81C, 0x06580103, - 0x81C, 0x055A0103, - 0x81C, 0x045C0103, - 0x81C, 0x035E0103, - 0x81C, 0x02600103, - 0x81C, 0x01620103, - 0x81C, 0x01640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000103, - 0x81C, 0xFB020103, - 0x81C, 0xFA040103, - 0x81C, 0xF9060103, - 0x81C, 0xF8080103, - 0x81C, 0xF70A0103, - 0x81C, 0xF60C0103, - 0x81C, 0xF50E0103, - 0x81C, 0xF4100103, - 0x81C, 0xF3120103, - 0x81C, 0xF2140103, - 0x81C, 0xF1160103, - 0x81C, 0xF0180103, - 0x81C, 0xEF1A0103, - 0x81C, 0xEE1C0103, - 0x81C, 0xED1E0103, - 0x81C, 0xEC200103, - 0x81C, 0xEB220103, - 0x81C, 0xEA240103, - 0x81C, 0xE9260103, - 0x81C, 0xE8280103, - 0x81C, 0xE72A0103, - 0x81C, 0xE62C0103, - 0x81C, 0xE52E0103, - 0x81C, 0xE4300103, - 0x81C, 0xE3320103, - 0x81C, 0xE2340103, - 0x81C, 0xE1360103, - 0x81C, 0x87380103, - 0x81C, 0x863A0103, - 0x81C, 0x853C0103, - 0x81C, 0x843E0103, - 0x81C, 0x83400103, - 0x81C, 0x82420103, - 0x81C, 0x81440103, - 0x81C, 0x64460103, - 0x81C, 0x63480103, - 0x81C, 0x624A0103, - 0x81C, 0x464C0103, - 0x81C, 0x454E0103, - 0x81C, 0x44500103, - 0x81C, 0x43520103, - 0x81C, 0x26540103, - 0x81C, 0x25560103, - 0x81C, 0x24580103, - 0x81C, 0x075A0103, - 0x81C, 0x065C0103, - 0x81C, 0x055E0103, - 0x81C, 0x04600103, - 0x81C, 0x03620103, - 0x81C, 0x02640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000103, - 0x81C, 0xF8020103, - 0x81C, 0xF7040103, - 0x81C, 0xF6060103, - 0x81C, 0xF5080103, - 0x81C, 0xF40A0103, - 0x81C, 0xF30C0103, - 0x81C, 0xF20E0103, - 0x81C, 0xF1100103, - 0x81C, 0xF0120103, - 0x81C, 0xEF140103, - 0x81C, 0xEE160103, - 0x81C, 0xED180103, - 0x81C, 0xEC1A0103, - 0x81C, 0xEB1C0103, - 0x81C, 0xEA1E0103, - 0x81C, 0xE9200103, - 0x81C, 0xE8220103, - 0x81C, 0xE7240103, - 0x81C, 0xE6260103, - 0x81C, 0xE5280103, - 0x81C, 0xE42A0103, - 0x81C, 0xE32C0103, - 0x81C, 0xE22E0103, - 0x81C, 0xA6300103, - 0x81C, 0xA5320103, - 0x81C, 0xA4340103, - 0x81C, 0xA3360103, - 0x81C, 0xA2380103, - 0x81C, 0xA13A0103, - 0x81C, 0x843C0103, - 0x81C, 0x833E0103, - 0x81C, 0x82400103, - 0x81C, 0x81420103, - 0x81C, 0x64440103, - 0x81C, 0x63460103, - 0x81C, 0x62480103, - 0x81C, 0x614A0103, - 0x81C, 0x444C0103, - 0x81C, 0x434E0103, - 0x81C, 0x42500103, - 0x81C, 0x41520103, - 0x81C, 0x25540103, - 0x81C, 0x24560103, - 0x81C, 0x23580103, - 0x81C, 0x225A0103, - 0x81C, 0x055C0103, - 0x81C, 0x045E0103, - 0x81C, 0x03600103, - 0x81C, 0x02620103, - 0x81C, 0x01640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFD000103, - 0x81C, 0xFC020103, - 0x81C, 0xFB040103, - 0x81C, 0xFA060103, - 0x81C, 0xF9080103, - 0x81C, 0xF80A0103, - 0x81C, 0xF70C0103, - 0x81C, 0xF60E0103, - 0x81C, 0xF5100103, - 0x81C, 0xF4120103, - 0x81C, 0xF3140103, - 0x81C, 0xF2160103, - 0x81C, 0xF1180103, - 0x81C, 0xF01A0103, - 0x81C, 0xEF1C0103, - 0x81C, 0xEE1E0103, - 0x81C, 0xED200103, - 0x81C, 0xEC220103, - 0x81C, 0xEB240103, - 0x81C, 0xEA260103, - 0x81C, 0xE9280103, - 0x81C, 0xE82A0103, - 0x81C, 0xE72C0103, - 0x81C, 0xE62E0103, - 0x81C, 0xE5300103, - 0x81C, 0xE4320103, - 0x81C, 0xE3340103, - 0x81C, 0xE2360103, - 0x81C, 0xE1380103, - 0x81C, 0xA33A0103, - 0x81C, 0xA23C0103, - 0x81C, 0xA13E0103, - 0x81C, 0x84400103, - 0x81C, 0x83420103, - 0x81C, 0x82440103, - 0x81C, 0x81460103, - 0x81C, 0x64480103, - 0x81C, 0x634A0103, - 0x81C, 0x624C0103, - 0x81C, 0x614E0103, - 0x81C, 0x45500103, - 0x81C, 0x44520103, - 0x81C, 0x43540103, - 0x81C, 0x42560103, - 0x81C, 0x25580103, - 0x81C, 0x245A0103, - 0x81C, 0x235C0103, - 0x81C, 0x065E0103, - 0x81C, 0x05600103, - 0x81C, 0x04620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFA000103, - 0x81C, 0xF9020103, - 0x81C, 0xF8040103, - 0x81C, 0xF7060103, - 0x81C, 0xF6080103, - 0x81C, 0xF50A0103, - 0x81C, 0xF40C0103, - 0x81C, 0xF30E0103, - 0x81C, 0xF2100103, - 0x81C, 0xF1120103, - 0x81C, 0xF0140103, - 0x81C, 0xEF160103, - 0x81C, 0xEE180103, - 0x81C, 0xED1A0103, - 0x81C, 0xEC1C0103, - 0x81C, 0xEB1E0103, - 0x81C, 0xEA200103, - 0x81C, 0xE9220103, - 0x81C, 0xE8240103, - 0x81C, 0xE7260103, - 0x81C, 0xE6280103, - 0x81C, 0xE52A0103, - 0x81C, 0xE42C0103, - 0x81C, 0xE32E0103, - 0x81C, 0xE2300103, - 0x81C, 0xE1320103, - 0x81C, 0xA5340103, - 0x81C, 0xA4360103, - 0x81C, 0xA3380103, - 0x81C, 0xA23A0103, - 0x81C, 0xA13C0103, - 0x81C, 0x843E0103, - 0x81C, 0x83400103, - 0x81C, 0x82420103, - 0x81C, 0x81440103, - 0x81C, 0x64460103, - 0x81C, 0x63480103, - 0x81C, 0x624A0103, - 0x81C, 0x614C0103, - 0x81C, 0x454E0103, - 0x81C, 0x44500103, - 0x81C, 0x43520103, - 0x81C, 0x42540103, - 0x81C, 0x41560103, - 0x81C, 0x24580103, - 0x81C, 0x235A0103, - 0x81C, 0x225C0103, - 0x81C, 0x055E0103, - 0x81C, 0x04600103, - 0x81C, 0x03620103, - 0x81C, 0x02640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000103, - 0x81C, 0xFF020103, - 0x81C, 0xFE040103, - 0x81C, 0xFD060103, - 0x81C, 0xFC080103, - 0x81C, 0xFB0A0103, - 0x81C, 0xFA0C0103, - 0x81C, 0xF90E0103, - 0x81C, 0xF8100103, - 0x81C, 0xF7120103, - 0x81C, 0xF6140103, - 0x81C, 0xF5160103, - 0x81C, 0xF4180103, - 0x81C, 0xF31A0103, - 0x81C, 0xF21C0103, - 0x81C, 0xF11E0103, - 0x81C, 0xF0200103, - 0x81C, 0xEF220103, - 0x81C, 0xEE240103, - 0x81C, 0xED260103, - 0x81C, 0xEC280103, - 0x81C, 0xEB2A0103, - 0x81C, 0xEA2C0103, - 0x81C, 0xE92E0103, - 0x81C, 0xE8300103, - 0x81C, 0xE7320103, - 0x81C, 0xE6340103, - 0x81C, 0xE5360103, - 0x81C, 0xE4380103, - 0x81C, 0xE33A0103, - 0x81C, 0xA53C0103, - 0x81C, 0xA43E0103, - 0x81C, 0xA3400103, - 0x81C, 0xA2420103, - 0x81C, 0xA1440103, - 0x81C, 0x85460103, - 0x81C, 0x84480103, - 0x81C, 0x834A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x64500103, - 0x81C, 0x63520103, - 0x81C, 0x62540103, - 0x81C, 0x44560103, - 0x81C, 0x43580103, - 0x81C, 0x425A0103, - 0x81C, 0x265C0103, - 0x81C, 0x255E0103, - 0x81C, 0x24600103, - 0x81C, 0x07620103, - 0x81C, 0x06640103, - 0x81C, 0x05660103, - 0x81C, 0x04680103, - 0x81C, 0x036A0103, - 0x81C, 0x026C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xE22C0103, - 0x81C, 0xE12E0103, - 0x81C, 0xA4300103, - 0x81C, 0xA3320103, - 0x81C, 0xA2340103, - 0x81C, 0xA1360103, - 0x81C, 0x85380103, - 0x81C, 0x843A0103, - 0x81C, 0x833C0103, - 0x81C, 0x823E0103, - 0x81C, 0x65400103, - 0x81C, 0x64420103, - 0x81C, 0x63440103, - 0x81C, 0x62460103, - 0x81C, 0x45480103, - 0x81C, 0x444A0103, - 0x81C, 0x434C0103, - 0x81C, 0x264E0103, - 0x81C, 0x25500103, - 0x81C, 0x24520103, - 0x81C, 0x08540103, - 0x81C, 0x07560103, - 0x81C, 0x06580103, - 0x81C, 0x055A0103, - 0x81C, 0x045C0103, - 0x81C, 0x035E0103, - 0x81C, 0x02600103, - 0x81C, 0x01620103, - 0x81C, 0x01640103, - 0x81C, 0x01660103, - 0x81C, 0x01680103, - 0x81C, 0x016A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000103, - 0x81C, 0xFF020103, - 0x81C, 0xFE040103, - 0x81C, 0xFD060103, - 0x81C, 0xFC080103, - 0x81C, 0xFB0A0103, - 0x81C, 0xFA0C0103, - 0x81C, 0xF90E0103, - 0x81C, 0xF8100103, - 0x81C, 0xF7120103, - 0x81C, 0xF6140103, - 0x81C, 0xF5160103, - 0x81C, 0xF4180103, - 0x81C, 0xF31A0103, - 0x81C, 0xF21C0103, - 0x81C, 0xF11E0103, - 0x81C, 0xF0200103, - 0x81C, 0xEF220103, - 0x81C, 0xEE240103, - 0x81C, 0xED260103, - 0x81C, 0xEC280103, - 0x81C, 0xEB2A0103, - 0x81C, 0xEA2C0103, - 0x81C, 0xE92E0103, - 0x81C, 0xE8300103, - 0x81C, 0xE7320103, - 0x81C, 0xE6340103, - 0x81C, 0xE5360103, - 0x81C, 0xE4380103, - 0x81C, 0xE33A0103, - 0x81C, 0xA53C0103, - 0x81C, 0xA43E0103, - 0x81C, 0xA3400103, - 0x81C, 0xA2420103, - 0x81C, 0xA1440103, - 0x81C, 0x85460103, - 0x81C, 0x84480103, - 0x81C, 0x834A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x64500103, - 0x81C, 0x63520103, - 0x81C, 0x62540103, - 0x81C, 0x44560103, - 0x81C, 0x43580103, - 0x81C, 0x425A0103, - 0x81C, 0x265C0103, - 0x81C, 0x255E0103, - 0x81C, 0x24600103, - 0x81C, 0x07620103, - 0x81C, 0x06640103, - 0x81C, 0x05660103, - 0x81C, 0x04680103, - 0x81C, 0x036A0103, - 0x81C, 0x026C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000103, - 0x81C, 0xFE020103, - 0x81C, 0xFD040103, - 0x81C, 0xFC060103, - 0x81C, 0xFB080103, - 0x81C, 0xFA0A0103, - 0x81C, 0xF90C0103, - 0x81C, 0xF80E0103, - 0x81C, 0xF7100103, - 0x81C, 0xF6120103, - 0x81C, 0xF5140103, - 0x81C, 0xF4160103, - 0x81C, 0xF3180103, - 0x81C, 0xF21A0103, - 0x81C, 0xF11C0103, - 0x81C, 0xF01E0103, - 0x81C, 0xEF200103, - 0x81C, 0xEE220103, - 0x81C, 0xED240103, - 0x81C, 0xEC260103, - 0x81C, 0xEB280103, - 0x81C, 0xEA2A0103, - 0x81C, 0xE92C0103, - 0x81C, 0xE82E0103, - 0x81C, 0xE7300103, - 0x81C, 0xE6320103, - 0x81C, 0xE5340103, - 0x81C, 0xE4360103, - 0x81C, 0xE3380103, - 0x81C, 0xE23A0103, - 0x81C, 0xE13C0103, - 0x81C, 0xA43E0103, - 0x81C, 0xA3400103, - 0x81C, 0xA2420103, - 0x81C, 0xA1440103, - 0x81C, 0x86460103, - 0x81C, 0x85480103, - 0x81C, 0x844A0103, - 0x81C, 0x834C0103, - 0x81C, 0x824E0103, - 0x81C, 0x81500103, - 0x81C, 0x64520103, - 0x81C, 0x63540103, - 0x81C, 0x62560103, - 0x81C, 0x61580103, - 0x81C, 0x435A0103, - 0x81C, 0x425C0103, - 0x81C, 0x415E0103, - 0x81C, 0x25600103, - 0x81C, 0x24620103, - 0x81C, 0x06640103, - 0x81C, 0x05660103, - 0x81C, 0x04680103, - 0x81C, 0x036A0103, - 0x81C, 0x026C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFA000203, - 0x81C, 0xF9020203, - 0x81C, 0xF8040203, - 0x81C, 0xF7060203, - 0x81C, 0xF6080203, - 0x81C, 0xF50A0203, - 0x81C, 0xF40C0203, - 0x81C, 0xF30E0203, - 0x81C, 0xF2100203, - 0x81C, 0xF1120203, - 0x81C, 0xF0140203, - 0x81C, 0xEF160203, - 0x81C, 0xEE180203, - 0x81C, 0xED1A0203, - 0x81C, 0xEC1C0203, - 0x81C, 0xEB1E0203, - 0x81C, 0xEA200203, - 0x81C, 0xE9220203, - 0x81C, 0xE8240203, - 0x81C, 0xE7260203, - 0x81C, 0xE6280203, - 0x81C, 0xE52A0203, - 0x81C, 0xE42C0203, - 0x81C, 0xE32E0203, - 0x81C, 0xE2300203, - 0x81C, 0xE1320203, - 0x81C, 0xA5340203, - 0x81C, 0xA4360203, - 0x81C, 0xA3380203, - 0x81C, 0xA23A0203, - 0x81C, 0xA13C0203, - 0x81C, 0x843E0203, - 0x81C, 0x83400203, - 0x81C, 0x82420203, - 0x81C, 0x81440203, - 0x81C, 0x63460203, - 0x81C, 0x62480203, - 0x81C, 0x614A0203, - 0x81C, 0x464C0203, - 0x81C, 0x454E0203, - 0x81C, 0x44500203, - 0x81C, 0x43520203, - 0x81C, 0x42540203, - 0x81C, 0x41560203, - 0x81C, 0x24580203, - 0x81C, 0x235A0203, - 0x81C, 0x065C0203, - 0x81C, 0x055E0203, - 0x81C, 0x04600203, - 0x81C, 0x03620203, - 0x81C, 0x02640203, - 0x81C, 0x01660203, - 0x81C, 0x01680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000203, - 0x81C, 0xF7020203, - 0x81C, 0xF6040203, - 0x81C, 0xF5060203, - 0x81C, 0xF4080203, - 0x81C, 0xF30A0203, - 0x81C, 0xF20C0203, - 0x81C, 0xF10E0203, - 0x81C, 0xF0100203, - 0x81C, 0xEF120203, - 0x81C, 0xEE140203, - 0x81C, 0xED160203, - 0x81C, 0xEC180203, - 0x81C, 0xEB1A0203, - 0x81C, 0xEA1C0203, - 0x81C, 0xE91E0203, - 0x81C, 0xE8200203, - 0x81C, 0xE7220203, - 0x81C, 0xE6240203, - 0x81C, 0xE5260203, - 0x81C, 0xE4280203, - 0x81C, 0xE32A0203, - 0x81C, 0xE22C0203, - 0x81C, 0xE12E0203, - 0x81C, 0xA6300203, - 0x81C, 0xA5320203, - 0x81C, 0xA4340203, - 0x81C, 0xA3360203, - 0x81C, 0xA2380203, - 0x81C, 0x853A0203, - 0x81C, 0x843C0203, - 0x81C, 0x833E0203, - 0x81C, 0x82400203, - 0x81C, 0x81420203, - 0x81C, 0x64440203, - 0x81C, 0x63460203, - 0x81C, 0x62480203, - 0x81C, 0x614A0203, - 0x81C, 0x444C0203, - 0x81C, 0x434E0203, - 0x81C, 0x42500203, - 0x81C, 0x25520203, - 0x81C, 0x24540203, - 0x81C, 0x23560203, - 0x81C, 0x06580203, - 0x81C, 0x055A0203, - 0x81C, 0x045C0203, - 0x81C, 0x035E0203, - 0x81C, 0x02600203, - 0x81C, 0x01620203, - 0x81C, 0x01640203, - 0x81C, 0x01660203, - 0x81C, 0x01680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xE1360203, - 0x81C, 0x87380203, - 0x81C, 0x863A0203, - 0x81C, 0x853C0203, - 0x81C, 0x843E0203, - 0x81C, 0x83400203, - 0x81C, 0x82420203, - 0x81C, 0x81440203, - 0x81C, 0x64460203, - 0x81C, 0x63480203, - 0x81C, 0x624A0203, - 0x81C, 0x474C0203, - 0x81C, 0x464E0203, - 0x81C, 0x45500203, - 0x81C, 0x44520203, - 0x81C, 0x43540203, - 0x81C, 0x42560203, - 0x81C, 0x24580203, - 0x81C, 0x235A0203, - 0x81C, 0x075C0203, - 0x81C, 0x065E0203, - 0x81C, 0x05600203, - 0x81C, 0x04620203, - 0x81C, 0x03640203, - 0x81C, 0x02660203, - 0x81C, 0x01680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000203, - 0x81C, 0xF7020203, - 0x81C, 0xF6040203, - 0x81C, 0xF5060203, - 0x81C, 0xF4080203, - 0x81C, 0xF30A0203, - 0x81C, 0xF20C0203, - 0x81C, 0xF10E0203, - 0x81C, 0xF0100203, - 0x81C, 0xEF120203, - 0x81C, 0xEE140203, - 0x81C, 0xED160203, - 0x81C, 0xEC180203, - 0x81C, 0xEB1A0203, - 0x81C, 0xEA1C0203, - 0x81C, 0xE91E0203, - 0x81C, 0xE8200203, - 0x81C, 0xE7220203, - 0x81C, 0xE6240203, - 0x81C, 0xE5260203, - 0x81C, 0xE4280203, - 0x81C, 0xE32A0203, - 0x81C, 0xE22C0203, - 0x81C, 0xE12E0203, - 0x81C, 0xA6300203, - 0x81C, 0xA5320203, - 0x81C, 0xA4340203, - 0x81C, 0xA3360203, - 0x81C, 0xA2380203, - 0x81C, 0xA13A0203, - 0x81C, 0x843C0203, - 0x81C, 0x833E0203, - 0x81C, 0x82400203, - 0x81C, 0x81420203, - 0x81C, 0x64440203, - 0x81C, 0x63460203, - 0x81C, 0x62480203, - 0x81C, 0x614A0203, - 0x81C, 0x444C0203, - 0x81C, 0x434E0203, - 0x81C, 0x42500203, - 0x81C, 0x41520203, - 0x81C, 0x25540203, - 0x81C, 0x24560203, - 0x81C, 0x23580203, - 0x81C, 0x065A0203, - 0x81C, 0x055C0203, - 0x81C, 0x045E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x01660203, - 0x81C, 0x01680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000203, - 0x81C, 0xFA020203, - 0x81C, 0xF9040203, - 0x81C, 0xF8060203, - 0x81C, 0xF7080203, - 0x81C, 0xF60A0203, - 0x81C, 0xF50C0203, - 0x81C, 0xF40E0203, - 0x81C, 0xF3100203, - 0x81C, 0xF2120203, - 0x81C, 0xF1140203, - 0x81C, 0xF0160203, - 0x81C, 0xEF180203, - 0x81C, 0xEE1A0203, - 0x81C, 0xED1C0203, - 0x81C, 0xEC1E0203, - 0x81C, 0xEB200203, - 0x81C, 0xEA220203, - 0x81C, 0xE9240203, - 0x81C, 0xE8260203, - 0x81C, 0xE7280203, - 0x81C, 0xE62A0203, - 0x81C, 0xE52C0203, - 0x81C, 0xE42E0203, - 0x81C, 0xE3300203, - 0x81C, 0xE2320203, - 0x81C, 0xE1340203, - 0x81C, 0xA5360203, - 0x81C, 0xA4380203, - 0x81C, 0xA33A0203, - 0x81C, 0xA23C0203, - 0x81C, 0x843E0203, - 0x81C, 0x83400203, - 0x81C, 0x82420203, - 0x81C, 0x81440203, - 0x81C, 0x64460203, - 0x81C, 0x63480203, - 0x81C, 0x624A0203, - 0x81C, 0x614C0203, - 0x81C, 0x474E0203, - 0x81C, 0x46500203, - 0x81C, 0x45520203, - 0x81C, 0x44540203, - 0x81C, 0x43560203, - 0x81C, 0x25580203, - 0x81C, 0x245A0203, - 0x81C, 0x235C0203, - 0x81C, 0x075E0203, - 0x81C, 0x06600203, - 0x81C, 0x05620203, - 0x81C, 0x04640203, - 0x81C, 0x03660203, - 0x81C, 0x02680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xE1360203, - 0x81C, 0xA5380203, - 0x81C, 0xA43A0203, - 0x81C, 0xA33C0203, - 0x81C, 0x853E0203, - 0x81C, 0x84400203, - 0x81C, 0x83420203, - 0x81C, 0x82440203, - 0x81C, 0x81460203, - 0x81C, 0x64480203, - 0x81C, 0x634A0203, - 0x81C, 0x624C0203, - 0x81C, 0x614E0203, - 0x81C, 0x46500203, - 0x81C, 0x45520203, - 0x81C, 0x44540203, - 0x81C, 0x43560203, - 0x81C, 0x25580203, - 0x81C, 0x245A0203, - 0x81C, 0x235C0203, - 0x81C, 0x075E0203, - 0x81C, 0x06600203, - 0x81C, 0x05620203, - 0x81C, 0x04640203, - 0x81C, 0x03660203, - 0x81C, 0x02680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000203, - 0x81C, 0xFF020203, - 0x81C, 0xFE040203, - 0x81C, 0xFD060203, - 0x81C, 0xFC080203, - 0x81C, 0xFB0A0203, - 0x81C, 0xFA0C0203, - 0x81C, 0xF90E0203, - 0x81C, 0xF8100203, - 0x81C, 0xF7120203, - 0x81C, 0xF6140203, - 0x81C, 0xF5160203, - 0x81C, 0xF4180203, - 0x81C, 0xF31A0203, - 0x81C, 0xF21C0203, - 0x81C, 0xF11E0203, - 0x81C, 0xF0200203, - 0x81C, 0xEF220203, - 0x81C, 0xEE240203, - 0x81C, 0xED260203, - 0x81C, 0xEC280203, - 0x81C, 0xEB2A0203, - 0x81C, 0xEA2C0203, - 0x81C, 0xE92E0203, - 0x81C, 0xE8300203, - 0x81C, 0xE7320203, - 0x81C, 0xE6340203, - 0x81C, 0xE5360203, - 0x81C, 0xE4380203, - 0x81C, 0xE33A0203, - 0x81C, 0xE23C0203, - 0x81C, 0xE13E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x84480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x45580203, - 0x81C, 0x445A0203, - 0x81C, 0x435C0203, - 0x81C, 0x425E0203, - 0x81C, 0x24600203, - 0x81C, 0x23620203, - 0x81C, 0x07640203, - 0x81C, 0x06660203, - 0x81C, 0x05680203, - 0x81C, 0x046A0203, - 0x81C, 0x036C0203, - 0x81C, 0x026E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xE22A0203, - 0x81C, 0xA62C0203, - 0x81C, 0xA52E0203, - 0x81C, 0xA4300203, - 0x81C, 0xA3320203, - 0x81C, 0xA2340203, - 0x81C, 0xA1360203, - 0x81C, 0x86380203, - 0x81C, 0x853A0203, - 0x81C, 0x843C0203, - 0x81C, 0x833E0203, - 0x81C, 0x65400203, - 0x81C, 0x64420203, - 0x81C, 0x63440203, - 0x81C, 0x46460203, - 0x81C, 0x45480203, - 0x81C, 0x444A0203, - 0x81C, 0x434C0203, - 0x81C, 0x264E0203, - 0x81C, 0x25500203, - 0x81C, 0x24520203, - 0x81C, 0x08540203, - 0x81C, 0x07560203, - 0x81C, 0x06580203, - 0x81C, 0x055A0203, - 0x81C, 0x045C0203, - 0x81C, 0x035E0203, - 0x81C, 0x02600203, - 0x81C, 0x01620203, - 0x81C, 0x01640203, - 0x81C, 0x01660203, - 0x81C, 0x01680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000203, - 0x81C, 0xFF020203, - 0x81C, 0xFE040203, - 0x81C, 0xFD060203, - 0x81C, 0xFC080203, - 0x81C, 0xFB0A0203, - 0x81C, 0xFA0C0203, - 0x81C, 0xF90E0203, - 0x81C, 0xF8100203, - 0x81C, 0xF7120203, - 0x81C, 0xF6140203, - 0x81C, 0xF5160203, - 0x81C, 0xF4180203, - 0x81C, 0xF31A0203, - 0x81C, 0xF21C0203, - 0x81C, 0xF11E0203, - 0x81C, 0xF0200203, - 0x81C, 0xEF220203, - 0x81C, 0xEE240203, - 0x81C, 0xED260203, - 0x81C, 0xEC280203, - 0x81C, 0xEB2A0203, - 0x81C, 0xEA2C0203, - 0x81C, 0xE92E0203, - 0x81C, 0xE8300203, - 0x81C, 0xE7320203, - 0x81C, 0xE6340203, - 0x81C, 0xE5360203, - 0x81C, 0xE4380203, - 0x81C, 0xE33A0203, - 0x81C, 0xE23C0203, - 0x81C, 0xE13E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x84480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x45580203, - 0x81C, 0x445A0203, - 0x81C, 0x435C0203, - 0x81C, 0x425E0203, - 0x81C, 0x24600203, - 0x81C, 0x23620203, - 0x81C, 0x07640203, - 0x81C, 0x06660203, - 0x81C, 0x05680203, - 0x81C, 0x046A0203, - 0x81C, 0x036C0203, - 0x81C, 0x026E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000203, - 0x81C, 0xFF020203, - 0x81C, 0xFE040203, - 0x81C, 0xFD060203, - 0x81C, 0xFC080203, - 0x81C, 0xFB0A0203, - 0x81C, 0xFA0C0203, - 0x81C, 0xF90E0203, - 0x81C, 0xF8100203, - 0x81C, 0xF7120203, - 0x81C, 0xF6140203, - 0x81C, 0xF5160203, - 0x81C, 0xF4180203, - 0x81C, 0xF31A0203, - 0x81C, 0xF21C0203, - 0x81C, 0xF11E0203, - 0x81C, 0xF0200203, - 0x81C, 0xEF220203, - 0x81C, 0xEE240203, - 0x81C, 0xED260203, - 0x81C, 0xEC280203, - 0x81C, 0xEB2A0203, - 0x81C, 0xEA2C0203, - 0x81C, 0xE92E0203, - 0x81C, 0xE8300203, - 0x81C, 0xE7320203, - 0x81C, 0xE6340203, - 0x81C, 0xE5360203, - 0x81C, 0xE4380203, - 0x81C, 0xE33A0203, - 0x81C, 0xE23C0203, - 0x81C, 0xE13E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x85480203, - 0x81C, 0x844A0203, - 0x81C, 0x834C0203, - 0x81C, 0x824E0203, - 0x81C, 0x81500203, - 0x81C, 0x64520203, - 0x81C, 0x63540203, - 0x81C, 0x62560203, - 0x81C, 0x61580203, - 0x81C, 0x445A0203, - 0x81C, 0x435C0203, - 0x81C, 0x425E0203, - 0x81C, 0x25600203, - 0x81C, 0x24620203, - 0x81C, 0x06640203, - 0x81C, 0x05660203, - 0x81C, 0x04680203, - 0x81C, 0x036A0203, - 0x81C, 0x026C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000303, - 0x81C, 0xF7020303, - 0x81C, 0xF6040303, - 0x81C, 0xF5060303, - 0x81C, 0xF4080303, - 0x81C, 0xF30A0303, - 0x81C, 0xF20C0303, - 0x81C, 0xF10E0303, - 0x81C, 0xF0100303, - 0x81C, 0xEF120303, - 0x81C, 0xEE140303, - 0x81C, 0xED160303, - 0x81C, 0xEC180303, - 0x81C, 0xEB1A0303, - 0x81C, 0xEA1C0303, - 0x81C, 0xE91E0303, - 0x81C, 0xE8200303, - 0x81C, 0xE7220303, - 0x81C, 0xE6240303, - 0x81C, 0xE5260303, - 0x81C, 0xE4280303, - 0x81C, 0xE32A0303, - 0x81C, 0xE22C0303, - 0x81C, 0xE12E0303, - 0x81C, 0xA6300303, - 0x81C, 0xA5320303, - 0x81C, 0xA4340303, - 0x81C, 0xA3360303, - 0x81C, 0xA2380303, - 0x81C, 0xA13A0303, - 0x81C, 0x843C0303, - 0x81C, 0x833E0303, - 0x81C, 0x82400303, - 0x81C, 0x81420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x454C0303, - 0x81C, 0x444E0303, - 0x81C, 0x43500303, - 0x81C, 0x42520303, - 0x81C, 0x41540303, - 0x81C, 0x24560303, - 0x81C, 0x23580303, - 0x81C, 0x065A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xE81E0303, - 0x81C, 0xE7200303, - 0x81C, 0xE6220303, - 0x81C, 0xE5240303, - 0x81C, 0xE4260303, - 0x81C, 0xE3280303, - 0x81C, 0xC32A0303, - 0x81C, 0xC22C0303, - 0x81C, 0xC12E0303, - 0x81C, 0xA5300303, - 0x81C, 0xA4320303, - 0x81C, 0xA3340303, - 0x81C, 0xA2360303, - 0x81C, 0xA1380303, - 0x81C, 0x853A0303, - 0x81C, 0x843C0303, - 0x81C, 0x833E0303, - 0x81C, 0x82400303, - 0x81C, 0x81420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x454C0303, - 0x81C, 0x444E0303, - 0x81C, 0x43500303, - 0x81C, 0x25520303, - 0x81C, 0x24540303, - 0x81C, 0x23560303, - 0x81C, 0x06580303, - 0x81C, 0x055A0303, - 0x81C, 0x045C0303, - 0x81C, 0x035E0303, - 0x81C, 0x02600303, - 0x81C, 0x01620303, - 0x81C, 0x01640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000303, - 0x81C, 0xF8020303, - 0x81C, 0xF7040303, - 0x81C, 0xF6060303, - 0x81C, 0xF5080303, - 0x81C, 0xF40A0303, - 0x81C, 0xF30C0303, - 0x81C, 0xF20E0303, - 0x81C, 0xF1100303, - 0x81C, 0xF0120303, - 0x81C, 0xEF140303, - 0x81C, 0xEE160303, - 0x81C, 0xED180303, - 0x81C, 0xEC1A0303, - 0x81C, 0xEB1C0303, - 0x81C, 0xEA1E0303, - 0x81C, 0xE9200303, - 0x81C, 0xE8220303, - 0x81C, 0xE7240303, - 0x81C, 0xE6260303, - 0x81C, 0xE5280303, - 0x81C, 0xE42A0303, - 0x81C, 0xE32C0303, - 0x81C, 0xE22E0303, - 0x81C, 0xE1300303, - 0x81C, 0xA4320303, - 0x81C, 0xA3340303, - 0x81C, 0xA2360303, - 0x81C, 0xA1380303, - 0x81C, 0x853A0303, - 0x81C, 0x843C0303, - 0x81C, 0x833E0303, - 0x81C, 0x82400303, - 0x81C, 0x81420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x444C0303, - 0x81C, 0x434E0303, - 0x81C, 0x42500303, - 0x81C, 0x25520303, - 0x81C, 0x24540303, - 0x81C, 0x23560303, - 0x81C, 0x07580303, - 0x81C, 0x065A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xE81E0303, - 0x81C, 0xE7200303, - 0x81C, 0xE6220303, - 0x81C, 0xE5240303, - 0x81C, 0xE4260303, - 0x81C, 0xE3280303, - 0x81C, 0xE22A0303, - 0x81C, 0xE12C0303, - 0x81C, 0xA72E0303, - 0x81C, 0xA6300303, - 0x81C, 0xA5320303, - 0x81C, 0xA4340303, - 0x81C, 0xA3360303, - 0x81C, 0xA2380303, - 0x81C, 0xA13A0303, - 0x81C, 0x843C0303, - 0x81C, 0x833E0303, - 0x81C, 0x82400303, - 0x81C, 0x81420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x454C0303, - 0x81C, 0x444E0303, - 0x81C, 0x43500303, - 0x81C, 0x42520303, - 0x81C, 0x41540303, - 0x81C, 0x24560303, - 0x81C, 0x23580303, - 0x81C, 0x065A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000303, - 0x81C, 0xFA020303, - 0x81C, 0xF9040303, - 0x81C, 0xF8060303, - 0x81C, 0xF7080303, - 0x81C, 0xF60A0303, - 0x81C, 0xF50C0303, - 0x81C, 0xF40E0303, - 0x81C, 0xF3100303, - 0x81C, 0xF2120303, - 0x81C, 0xF1140303, - 0x81C, 0xF0160303, - 0x81C, 0xEF180303, - 0x81C, 0xEE1A0303, - 0x81C, 0xED1C0303, - 0x81C, 0xEC1E0303, - 0x81C, 0xEB200303, - 0x81C, 0xEA220303, - 0x81C, 0xE9240303, - 0x81C, 0xE8260303, - 0x81C, 0xE7280303, - 0x81C, 0xE62A0303, - 0x81C, 0xE52C0303, - 0x81C, 0xE42E0303, - 0x81C, 0xE3300303, - 0x81C, 0xE2320303, - 0x81C, 0xE1340303, - 0x81C, 0xC2360303, - 0x81C, 0xC1380303, - 0x81C, 0xA33A0303, - 0x81C, 0xA23C0303, - 0x81C, 0x853E0303, - 0x81C, 0x84400303, - 0x81C, 0x83420303, - 0x81C, 0x66440303, - 0x81C, 0x65460303, - 0x81C, 0x64480303, - 0x81C, 0x634A0303, - 0x81C, 0x624C0303, - 0x81C, 0x614E0303, - 0x81C, 0x45500303, - 0x81C, 0x44520303, - 0x81C, 0x43540303, - 0x81C, 0x42560303, - 0x81C, 0x25580303, - 0x81C, 0x245A0303, - 0x81C, 0x235C0303, - 0x81C, 0x065E0303, - 0x81C, 0x05600303, - 0x81C, 0x04620303, - 0x81C, 0x03640303, - 0x81C, 0x02660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000303, - 0x81C, 0xF8020303, - 0x81C, 0xF7040303, - 0x81C, 0xF6060303, - 0x81C, 0xF5080303, - 0x81C, 0xF40A0303, - 0x81C, 0xF30C0303, - 0x81C, 0xF20E0303, - 0x81C, 0xF1100303, - 0x81C, 0xF0120303, - 0x81C, 0xEF140303, - 0x81C, 0xEE160303, - 0x81C, 0xED180303, - 0x81C, 0xEC1A0303, - 0x81C, 0xEB1C0303, - 0x81C, 0xEA1E0303, - 0x81C, 0xE9200303, - 0x81C, 0xE8220303, - 0x81C, 0xE7240303, - 0x81C, 0xE6260303, - 0x81C, 0xE5280303, - 0x81C, 0xE42A0303, - 0x81C, 0xE32C0303, - 0x81C, 0xE22E0303, - 0x81C, 0xE1300303, - 0x81C, 0xA6320303, - 0x81C, 0xA5340303, - 0x81C, 0xA4360303, - 0x81C, 0xA3380303, - 0x81C, 0xA23A0303, - 0x81C, 0xA13C0303, - 0x81C, 0x853E0303, - 0x81C, 0x84400303, - 0x81C, 0x83420303, - 0x81C, 0x82440303, - 0x81C, 0x81460303, - 0x81C, 0x64480303, - 0x81C, 0x634A0303, - 0x81C, 0x624C0303, - 0x81C, 0x614E0303, - 0x81C, 0x44500303, - 0x81C, 0x43520303, - 0x81C, 0x42540303, - 0x81C, 0x41560303, - 0x81C, 0x25580303, - 0x81C, 0x245A0303, - 0x81C, 0x235C0303, - 0x81C, 0x055E0303, - 0x81C, 0x04600303, - 0x81C, 0x03620303, - 0x81C, 0x02640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000303, - 0x81C, 0xFD020303, - 0x81C, 0xFC040303, - 0x81C, 0xFB060303, - 0x81C, 0xFA080303, - 0x81C, 0xF90A0303, - 0x81C, 0xF80C0303, - 0x81C, 0xF70E0303, - 0x81C, 0xF6100303, - 0x81C, 0xF5120303, - 0x81C, 0xF4140303, - 0x81C, 0xF3160303, - 0x81C, 0xF2180303, - 0x81C, 0xF11A0303, - 0x81C, 0xF01C0303, - 0x81C, 0xEF1E0303, - 0x81C, 0xEE200303, - 0x81C, 0xED220303, - 0x81C, 0xEC240303, - 0x81C, 0xEB260303, - 0x81C, 0xEA280303, - 0x81C, 0xE92A0303, - 0x81C, 0xE82C0303, - 0x81C, 0xE72E0303, - 0x81C, 0xE6300303, - 0x81C, 0xE5320303, - 0x81C, 0xE4340303, - 0x81C, 0xE3360303, - 0x81C, 0xC3380303, - 0x81C, 0xC23A0303, - 0x81C, 0xC13C0303, - 0x81C, 0xA43E0303, - 0x81C, 0xA3400303, - 0x81C, 0xA2420303, - 0x81C, 0xA1440303, - 0x81C, 0x85460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x64500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x44580303, - 0x81C, 0x435A0303, - 0x81C, 0x425C0303, - 0x81C, 0x265E0303, - 0x81C, 0x25600303, - 0x81C, 0x24620303, - 0x81C, 0x06640303, - 0x81C, 0x05660303, - 0x81C, 0x04680303, - 0x81C, 0x036A0303, - 0x81C, 0x026C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xE81E0303, - 0x81C, 0xE7200303, - 0x81C, 0xE6220303, - 0x81C, 0xE5240303, - 0x81C, 0xE4260303, - 0x81C, 0xE3280303, - 0x81C, 0xE22A0303, - 0x81C, 0xA62C0303, - 0x81C, 0xA52E0303, - 0x81C, 0xA4300303, - 0x81C, 0xA3320303, - 0x81C, 0xA2340303, - 0x81C, 0x87360303, - 0x81C, 0x86380303, - 0x81C, 0x853A0303, - 0x81C, 0x843C0303, - 0x81C, 0x833E0303, - 0x81C, 0x66400303, - 0x81C, 0x65420303, - 0x81C, 0x64440303, - 0x81C, 0x45460303, - 0x81C, 0x44480303, - 0x81C, 0x434A0303, - 0x81C, 0x274C0303, - 0x81C, 0x264E0303, - 0x81C, 0x25500303, - 0x81C, 0x24520303, - 0x81C, 0x23540303, - 0x81C, 0x08560303, - 0x81C, 0x07580303, - 0x81C, 0x065A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x01660303, - 0x81C, 0x01680303, - 0x81C, 0x016A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000303, - 0x81C, 0xFD020303, - 0x81C, 0xFC040303, - 0x81C, 0xFB060303, - 0x81C, 0xFA080303, - 0x81C, 0xF90A0303, - 0x81C, 0xF80C0303, - 0x81C, 0xF70E0303, - 0x81C, 0xF6100303, - 0x81C, 0xF5120303, - 0x81C, 0xF4140303, - 0x81C, 0xF3160303, - 0x81C, 0xF2180303, - 0x81C, 0xF11A0303, - 0x81C, 0xF01C0303, - 0x81C, 0xEF1E0303, - 0x81C, 0xEE200303, - 0x81C, 0xED220303, - 0x81C, 0xEC240303, - 0x81C, 0xEB260303, - 0x81C, 0xEA280303, - 0x81C, 0xE92A0303, - 0x81C, 0xE82C0303, - 0x81C, 0xE72E0303, - 0x81C, 0xE6300303, - 0x81C, 0xE5320303, - 0x81C, 0xE4340303, - 0x81C, 0xE3360303, - 0x81C, 0xC3380303, - 0x81C, 0xC23A0303, - 0x81C, 0xC13C0303, - 0x81C, 0xA43E0303, - 0x81C, 0xA3400303, - 0x81C, 0xA2420303, - 0x81C, 0xA1440303, - 0x81C, 0x85460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x64500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x44580303, - 0x81C, 0x435A0303, - 0x81C, 0x425C0303, - 0x81C, 0x265E0303, - 0x81C, 0x25600303, - 0x81C, 0x24620303, - 0x81C, 0x06640303, - 0x81C, 0x05660303, - 0x81C, 0x04680303, - 0x81C, 0x036A0303, - 0x81C, 0x026C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0xA0000000, 0x00000000, - 0x81C, 0xFD000303, - 0x81C, 0xFC020303, - 0x81C, 0xFB040303, - 0x81C, 0xFA060303, - 0x81C, 0xF9080303, - 0x81C, 0xF80A0303, - 0x81C, 0xF70C0303, - 0x81C, 0xF60E0303, - 0x81C, 0xF5100303, - 0x81C, 0xF4120303, - 0x81C, 0xF3140303, - 0x81C, 0xF2160303, - 0x81C, 0xF1180303, - 0x81C, 0xF01A0303, - 0x81C, 0xEF1C0303, - 0x81C, 0xEE1E0303, - 0x81C, 0xED200303, - 0x81C, 0xEC220303, - 0x81C, 0xEB240303, - 0x81C, 0xEA260303, - 0x81C, 0xE9280303, - 0x81C, 0xE82A0303, - 0x81C, 0xE72C0303, - 0x81C, 0xE62E0303, - 0x81C, 0xE5300303, - 0x81C, 0xE4320303, - 0x81C, 0xE3340303, - 0x81C, 0xE2360303, - 0x81C, 0xE1380303, - 0x81C, 0xA53A0303, - 0x81C, 0xA43C0303, - 0x81C, 0xA33E0303, - 0x81C, 0xA2400303, - 0x81C, 0xA1420303, - 0x81C, 0x87440303, - 0x81C, 0x86460303, - 0x81C, 0x85480303, - 0x81C, 0x844A0303, - 0x81C, 0x834C0303, - 0x81C, 0x824E0303, - 0x81C, 0x81500303, - 0x81C, 0x64520303, - 0x81C, 0x63540303, - 0x81C, 0x62560303, - 0x81C, 0x61580303, - 0x81C, 0x435A0303, - 0x81C, 0x425C0303, - 0x81C, 0x415E0303, - 0x81C, 0x07600303, - 0x81C, 0x06620303, - 0x81C, 0x05640303, - 0x81C, 0x04660303, - 0x81C, 0x03680303, - 0x81C, 0x026A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0xB0000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0x1850, 0x00000022, - 0x1850, 0x00000020, - 0x1A50, 0x00000022, - 0x1A50, 0x00000020, - -}; - -void -ODM_ReadAndConfig_MP_8814A_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8814A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_AGC_TAB(void) -{ - return 107; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG[] = { - 0x800, 0x9020D010, - 0x804, 0x08011280, - 0x808, 0x0E0282FF, - 0x80C, 0x1000002F, - 0x80000003, 0x00000000, 0x40000000, 0x00000000, - 0x810, 0x33303265, - 0xA0000000, 0x00000000, - 0x810, 0x33303265, - 0xB0000000, 0x00000000, - 0x814, 0x020C3D10, - 0x818, 0x04A10385, - 0x820, 0x00000000, - 0x824, 0x00033E40, - 0x828, 0x00000000, - 0x82C, 0x73985170, - 0x830, 0x79A0EA08, - 0x834, 0x042E708A, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x838, 0x86667640, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x838, 0x86667641, - 0xA0000000, 0x00000000, - 0x838, 0x86667640, - 0xB0000000, 0x00000000, - 0x83C, 0x9798B9B9, - 0x840, 0x17578F60, - 0x844, 0x4BBDFCDE, - 0x848, 0x5CD07F8B, - 0x84C, 0x6CFBF7B5, - 0x850, 0x28834706, - 0x854, 0x0001520C, - 0x858, 0x4060C000, - 0x85C, 0x74210368, - 0x860, 0x6929C321, - 0x864, 0x79727432, - 0x868, 0x8CA7A314, - 0x86C, 0x438C2878, - 0x870, 0x44444444, - 0x874, 0x21612C2E, - 0x878, 0x00003152, - 0x87C, 0x000FC000, - 0x8A0, 0x00000013, - 0x8A4, 0x7F7F7F7F, - 0x8A8, 0xA202033E, - 0x8AC, 0xF40F550A, - 0x8B0, 0x00000600, - 0x8B4, 0x000FC080, - 0x8B8, 0xEC0057FF, - 0x8BC, 0x8CA520C3, - 0x8C0, 0x3FF00020, - 0x8C4, 0x44C00000, - 0x80000009, 0x00000000, 0x40000000, 0x00000000, - 0x8C8, 0x80025969, - 0xA0000000, 0x00000000, - 0x8C8, 0x80025167, - 0xB0000000, 0x00000000, - 0x8CC, 0x08250492, - 0x8D0, 0x0000B800, - 0x8D4, 0x940008A0, - 0x8D8, 0x290B5612, - 0x8DC, 0x00000000, - 0x8E0, 0x32316407, - 0x8E4, 0x4A092925, - 0x8E8, 0xFFFFC42C, - 0x8EC, 0x99999999, - 0x8F0, 0x00009999, - 0x8F4, 0x00F80FA1, - 0x8F8, 0x400082C0, - 0x8FC, 0x00000000, - 0x900, 0x00400700, - 0x90C, 0x09004000, - 0x910, 0x0000FC00, - 0x914, 0xD6400404, - 0x918, 0x1C1028C0, - 0x91C, 0x64B11A1C, - 0x920, 0xE0767233, - 0x924, 0x055AA500, - 0x928, 0x4AB0E4E4, - 0x92C, 0xFFFE0000, - 0x930, 0xFFFFFFFE, - 0x934, 0x001FFFFF, - 0x938, 0x00008400, - 0x93C, 0x932C0642, - 0x940, 0x093E9360, - 0x944, 0x08000000, - 0x948, 0x04000000, - 0x950, 0x02010080, - 0x954, 0x86510080, - 0x960, 0x00000000, - 0x964, 0x00000000, - 0x968, 0x00000000, - 0x96C, 0x00000000, - 0x970, 0x801FFFFF, - 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0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B28, 0xC0060324, - 0xA0000000, 0x00000000, - 0x1B28, 0xC0060348, - 0xB0000000, 0x00000000, - 0x1B2C, 0x20000003, - 0x1B30, 0x20000000, - 0x1B38, 0x20000000, - 0x1B3C, 0x20000000, - 0x1BD4, 0x00000001, - 0x1B94, 0x80000000, - 0x1B34, 0x00000000, - 0x1B34, 0x00000002, - 0x1B34, 0x00000000, - 0x1B00, 0xF8000000, - 0x1B80, 0x00000007, - 0x1B80, 0x09060005, - 0x1B80, 0x09060007, - 0x1B80, 0x0FFE0015, - 0x1B80, 0x0FFE0017, - 0x1B80, 0x00240025, - 0x1B80, 0x00240027, - 0x1B80, 0x00040035, - 0x1B80, 0x00040037, - 0x1B80, 0x05C00045, - 0x1B80, 0x05C00047, - 0x1B80, 0x00070055, - 0x1B80, 0x00070057, - 0x1B80, 0x64000065, - 0x1B80, 0x64000067, - 0x1B80, 0x00020075, - 0x1B80, 0x00020077, - 0x1B80, 0x00080085, - 0x1B80, 0x00080087, - 0x1B80, 0x80000095, - 0x1B80, 0x80000097, - 0x1B80, 0x090100A5, - 0x1B80, 0x090100A7, - 0x1B80, 0x0F0200B5, - 0x1B80, 0x0F0200B7, - 0x1B80, 0x002400C5, - 0x1B80, 0x002400C7, - 0x1B80, 0x000400D5, - 0x1B80, 0x000400D7, - 0x1B80, 0x05C000E5, - 0x1B80, 0x05C000E7, - 0x1B80, 0x000700F5, - 0x1B80, 0x000700F7, - 0x1B80, 0x64020105, - 0x1B80, 0x64020107, - 0x1B80, 0x00020115, - 0x1B80, 0x00020117, - 0x1B80, 0x00040125, - 0x1B80, 0x00040127, - 0x1B80, 0x4A000135, - 0x1B80, 0x4A000137, - 0x1B80, 0x4B040145, - 0x1B80, 0x4B040147, - 0x1B80, 0x85030155, - 0x1B80, 0x85030157, - 0x1B80, 0x40010165, - 0x1B80, 0x40010167, - 0x1B80, 0xE0290175, - 0x1B80, 0xE0290177, - 0x1B80, 0x00040185, - 0x1B80, 0x00040187, - 0x1B80, 0x4B050195, - 0x1B80, 0x4B050197, - 0x1B80, 0x860301A5, - 0x1B80, 0x860301A7, - 0x1B80, 0x400301B5, - 0x1B80, 0x400301B7, - 0x1B80, 0xE02901C5, - 0x1B80, 0xE02901C7, - 0x1B80, 0x000401D5, - 0x1B80, 0x000401D7, - 0x1B80, 0x4B0601E5, - 0x1B80, 0x4B0601E7, - 0x1B80, 0x870301F5, - 0x1B80, 0x870301F7, - 0x1B80, 0x40050205, - 0x1B80, 0x40050207, - 0x1B80, 0xE0290215, - 0x1B80, 0xE0290217, - 0x1B80, 0x00040225, - 0x1B80, 0x00040227, - 0x1B80, 0x4B070235, - 0x1B80, 0x4B070237, - 0x1B80, 0x88030245, - 0x1B80, 0x88030247, - 0x1B80, 0x40070255, - 0x1B80, 0x40070257, - 0x1B80, 0xE0290265, - 0x1B80, 0xE0290267, - 0x1B80, 0x4B000275, - 0x1B80, 0x4B000277, - 0x1B80, 0x30000285, - 0x1B80, 0x30000287, - 0x1B80, 0xFE100295, - 0x1B80, 0xFE100297, - 0x1B80, 0xFF1002A5, - 0x1B80, 0xFF1002A7, - 0x1B80, 0xE18602B5, - 0x1B80, 0xE18602B7, - 0x1B80, 0xF00A02C5, - 0x1B80, 0xF00A02C7, - 0x1B80, 0xF10A02D5, - 0x1B80, 0xF10A02D7, - 0x1B80, 0xF20A02E5, - 0x1B80, 0xF20A02E7, - 0x1B80, 0xF30802F5, - 0x1B80, 0xF30802F7, - 0x1B80, 0xF4070305, - 0x1B80, 0xF4070307, - 0x1B80, 0xF5060315, - 0x1B80, 0xF5060317, - 0x1B80, 0xF7060325, - 0x1B80, 0xF7060327, - 0x1B80, 0xF8050335, - 0x1B80, 0xF8050337, - 0x1B80, 0xF9040345, - 0x1B80, 0xF9040347, - 0x1B80, 0x00010355, - 0x1B80, 0x00010357, - 0x1B80, 0x303B0365, - 0x1B80, 0x303B0367, - 0x1B80, 0x30500375, - 0x1B80, 0x30500377, - 0x1B80, 0x305C0385, - 0x1B80, 0x305C0387, - 0x1B80, 0x31D50395, - 0x1B80, 0x31D50397, - 0x1B80, 0x31C503A5, - 0x1B80, 0x31C503A7, - 0x1B80, 0x4D0403B5, - 0x1B80, 0x4D0403B7, - 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0x1B80, 0x54801675, - 0x1B80, 0x54801677, - 0x1B80, 0xE1721685, - 0x1B80, 0xE1721687, - 0x1B80, 0xBF031695, - 0x1B80, 0xBF031697, - 0x1B80, 0x000216A5, - 0x1B80, 0x000216A7, - 0x1B80, 0x302816B5, - 0x1B80, 0x302816B7, - 0x1B80, 0x54BF16C5, - 0x1B80, 0x54BF16C7, - 0x1B80, 0x54C516D5, - 0x1B80, 0x54C516D7, - 0x1B80, 0x050A16E5, - 0x1B80, 0x050A16E7, - 0x1B80, 0x071416F5, - 0x1B80, 0x071416F7, - 0x1B80, 0x54DF1705, - 0x1B80, 0x54DF1707, - 0x1B80, 0x00011715, - 0x1B80, 0x00011717, - 0x1B80, 0x54BF1725, - 0x1B80, 0x54BF1727, - 0x1B80, 0x54C01735, - 0x1B80, 0x54C01737, - 0x1B80, 0x54A31745, - 0x1B80, 0x54A31747, - 0x1B80, 0x54C11755, - 0x1B80, 0x54C11757, - 0x1B80, 0x54A41765, - 0x1B80, 0x54A41767, - 0x1B80, 0x4C831775, - 0x1B80, 0x4C831777, - 0x1B80, 0x4C031785, - 0x1B80, 0x4C031787, - 0x1B80, 0xBF0B1795, - 0x1B80, 0xBF0B1797, - 0x1B80, 0x54C217A5, - 0x1B80, 0x54C217A7, - 0x1B80, 0x54A417B5, - 0x1B80, 0x54A417B7, - 0x1B80, 0x4C8517C5, - 0x1B80, 0x4C8517C7, - 0x1B80, 0x4C0517D5, - 0x1B80, 0x4C0517D7, - 0x1B80, 0xBF0617E5, - 0x1B80, 0xBF0617E7, - 0x1B80, 0x54C117F5, - 0x1B80, 0x54C117F7, - 0x1B80, 0x54A31805, - 0x1B80, 0x54A31807, - 0x1B80, 0x4C861815, - 0x1B80, 0x4C861817, - 0x1B80, 0x4C061825, - 0x1B80, 0x4C061827, - 0x1B80, 0xBF011835, - 0x1B80, 0xBF011837, - 0x1B80, 0x54DF1845, - 0x1B80, 0x54DF1847, - 0x1B80, 0x00011855, - 0x1B80, 0x00011857, - 0x1B80, 0x00071865, - 0x1B80, 0x00071867, - 0x1B80, 0x54011875, - 0x1B80, 0x54011877, - 0x1B80, 0x00041885, - 0x1B80, 0x00041887, - 0x1B80, 0x56001895, - 0x1B80, 0x56001897, - 0x1B80, 0x5CF218A5, - 0x1B80, 0x5CF218A7, - 0x1B80, 0x630718B5, - 0x1B80, 0x630718B7, - 0x1B80, 0x620418C5, - 0x1B80, 0x620418C7, - 0x1B80, 0x610018D5, - 0x1B80, 0x610018D7, - 0x1B80, 0x670718E5, - 0x1B80, 0x670718E7, - 0x1B80, 0x660618F5, - 0x1B80, 0x660618F7, - 0x1B80, 0x6F201905, - 0x1B80, 0x6F201907, - 0x1B80, 0x6E001915, - 0x1B80, 0x6E001917, - 0x1B80, 0x6D001925, - 0x1B80, 0x6D001927, - 0x1B80, 0x6C031935, - 0x1B80, 0x6C031937, - 0x1B80, 0x73201945, - 0x1B80, 0x73201947, - 0x1B80, 0x72001955, - 0x1B80, 0x72001957, - 0x1B80, 0x71001965, - 0x1B80, 0x71001967, - 0x1B80, 0x7B201975, - 0x1B80, 0x7B201977, - 0x1B80, 0x7A001985, - 0x1B80, 0x7A001987, - 0x1B80, 0x79001995, - 0x1B80, 0x79001997, - 0x1B80, 0x7F2019A5, - 0x1B80, 0x7F2019A7, - 0x1B80, 0x7E0019B5, - 0x1B80, 0x7E0019B7, - 0x1B80, 0x7D0019C5, - 0x1B80, 0x7D0019C7, - 0x1B80, 0x090119D5, - 0x1B80, 0x090119D7, - 0x1B80, 0x0AC619E5, - 0x1B80, 0x0AC619E7, - 0x1B80, 0x0BA619F5, - 0x1B80, 0x0BA619F7, - 0x1B80, 0x0C011A05, - 0x1B80, 0x0C011A07, - 0x1B80, 0x0D021A15, - 0x1B80, 0x0D021A17, - 0x1B80, 0x0E041A25, - 0x1B80, 0x0E041A27, - 0x1B80, 0x0FFF1A35, - 0x1B80, 0x0FFF1A37, - 0x1B80, 0x4D041A45, - 0x1B80, 0x4D041A47, - 0x1B80, 0x28F81A55, - 0x1B80, 0x28F81A57, - 0x1B80, 0xE0001A65, - 0x1B80, 0xE0001A67, - 0x1B80, 0x4D001A75, - 0x1B80, 0x4D001A77, - 0x1B80, 0x00011A85, - 0x1B80, 0x00011A87, - 0x1B80, 0x4D041A95, - 0x1B80, 0x4D041A97, - 0x1B80, 0x2EF81AA5, - 0x1B80, 0x2EF81AA7, - 0x1B80, 0x00021AB5, - 0x1B80, 0x00021AB7, - 0x1B80, 0x23031AC5, - 0x1B80, 0x23031AC7, - 0x1B80, 0x00001AD5, - 0x1B80, 0x00001AD7, - 0x1B80, 0x23131AE5, - 0x1B80, 0x23131AE7, - 0x1B80, 0xE77F1AF5, - 0x1B80, 0xE77F1AF7, - 0x1B80, 0x232F1B05, - 0x1B80, 0x232F1B07, - 0x1B80, 0xEFBF1B15, - 0x1B80, 0xEFBF1B17, - 0x1B80, 0x2EF01B25, - 0x1B80, 0x2EF01B27, - 0x1B80, 0x00021B35, - 0x1B80, 0x00021B37, - 0x1B80, 0x4D001B45, - 0x1B80, 0x4D001B47, - 0x1B80, 0x00011B55, - 0x1B80, 0x00011B57, - 0x1B80, 0x4D041B65, - 0x1B80, 0x4D041B67, - 0x1B80, 0x2EF81B75, - 0x1B80, 0x2EF81B77, - 0x1B80, 0x00021B85, - 0x1B80, 0x00021B87, - 0x1B80, 0x23031B95, - 0x1B80, 0x23031B97, - 0x1B80, 0x00001BA5, - 0x1B80, 0x00001BA7, - 0x1B80, 0x23131BB5, - 0x1B80, 0x23131BB7, - 0x1B80, 0xE77F1BC5, - 0x1B80, 0xE77F1BC7, - 0x1B80, 0x232F1BD5, - 0x1B80, 0x232F1BD7, - 0x1B80, 0xE79F1BE5, - 0x1B80, 0xE79F1BE7, - 0x1B80, 0x2EF01BF5, - 0x1B80, 0x2EF01BF7, - 0x1B80, 0x00021C05, - 0x1B80, 0x00021C07, - 0x1B80, 0x28F81C15, - 0x1B80, 0x28F81C17, - 0x1B80, 0x80001C25, - 0x1B80, 0x80001C27, - 0x1B80, 0x4D001C35, - 0x1B80, 0x4D001C37, - 0x1B80, 0x00011C45, - 0x1B80, 0x00011C47, - 0x1B80, 0x00041C55, - 0x1B80, 0x00041C57, - 0x1B80, 0x6BC01C65, - 0x1B80, 0x6BC01C67, - 0x1B80, 0x4D041C75, - 0x1B80, 0x4D041C77, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241C85, - 0x1B80, 0x68241C87, - 0xA0000000, 0x00000000, - 0x1B80, 0x68481C85, - 0x1B80, 0x68481C87, - 0xB0000000, 0x00000000, - 0x1B80, 0x66061C95, - 0x1B80, 0x66061C97, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x650C1CA5, - 0x1B80, 0x650C1CA7, - 0xA0000000, 0x00000000, - 0x1B80, 0x65041CA5, - 0x1B80, 0x65041CA7, - 0xB0000000, 0x00000000, - 0x1B80, 0x64471CB5, - 0x1B80, 0x64471CB7, - 0x1B80, 0x23411CC5, - 0x1B80, 0x23411CC7, - 0x1B80, 0x100E1CD5, - 0x1B80, 0x100E1CD7, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60101CE5, - 0x1B80, 0x60101CE7, - 0xA0000000, 0x00000000, - 0x1B80, 0x60011CE5, - 0x1B80, 0x60011CE7, - 0xB0000000, 0x00000000, - 0x1B80, 0x23411CF5, - 0x1B80, 0x23411CF7, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60811D05, - 0x1B80, 0x60811D07, - 0xA0000000, 0x00000000, - 0x1B80, 0x60611D05, - 0x1B80, 0x60611D07, - 0xB0000000, 0x00000000, - 0x1B80, 0x23411D15, - 0x1B80, 0x23411D17, - 0x1B80, 0x70E11D25, - 0x1B80, 0x70E11D27, - 0x1B80, 0x4D001D35, - 0x1B80, 0x4D001D37, - 0x1B80, 0x00011D45, - 0x1B80, 0x00011D47, - 0x1B80, 0x00041D55, - 0x1B80, 0x00041D57, - 0x1B80, 0x6B401D65, - 0x1B80, 0x6B401D67, - 0x1B80, 0x4D041D75, - 0x1B80, 0x4D041D77, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241D85, - 0x1B80, 0x68241D87, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241D85, - 0x1B80, 0x68241D87, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241D85, - 0x1B80, 0x68241D87, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x68241D85, - 0x1B80, 0x68241D87, - 0xA0000000, 0x00000000, - 0x1B80, 0x68481D85, - 0x1B80, 0x68481D87, - 0xB0000000, 0x00000000, - 0x1B80, 0x66061D95, - 0x1B80, 0x66061D97, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65081DA5, - 0x1B80, 0x65081DA7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65181DA5, - 0x1B80, 0x65181DA7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65181DA5, - 0x1B80, 0x65181DA7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65181DA5, - 0x1B80, 0x65181DA7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65181DA5, - 0x1B80, 0x65181DA7, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x65081DA5, - 0x1B80, 0x65081DA7, - 0xA0000000, 0x00000000, - 0x1B80, 0x65081DA5, - 0x1B80, 0x65081DA7, - 0xB0000000, 0x00000000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x64481DB5, - 0x1B80, 0x64481DB7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x64481DB5, - 0x1B80, 0x64481DB7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x64481DB5, - 0x1B80, 0x64481DB7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x64481DB5, - 0x1B80, 0x64481DB7, - 0xA0000000, 0x00000000, - 0x1B80, 0x64471DB5, - 0x1B80, 0x64471DB7, - 0xB0000000, 0x00000000, - 0x1B80, 0x23411DC5, - 0x1B80, 0x23411DC7, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E41DD5, - 0x1B80, 0x11E41DD7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E81DD5, - 0x1B80, 0x11E81DD7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E81DD5, - 0x1B80, 0x11E81DD7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E81DD5, - 0x1B80, 0x11E81DD7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E81DD5, - 0x1B80, 0x11E81DD7, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x11E41DD5, - 0x1B80, 0x11E41DD7, - 0xA0000000, 0x00000000, - 0x1B80, 0x11E41DD5, - 0x1B80, 0x11E41DD7, - 0xB0000000, 0x00000000, - 0x1B80, 0x60011DE5, - 0x1B80, 0x60011DE7, - 0x1B80, 0x23411DF5, - 0x1B80, 0x23411DF7, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60E11E05, - 0x1B80, 0x60E11E07, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x61E11E05, - 0x1B80, 0x61E11E07, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x61E11E05, - 0x1B80, 0x61E11E07, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x61E11E05, - 0x1B80, 0x61E11E07, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x61E11E05, - 0x1B80, 0x61E11E07, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x1B80, 0x60E11E05, - 0x1B80, 0x60E11E07, - 0xA0000000, 0x00000000, - 0x1B80, 0x60E11E05, - 0x1B80, 0x60E11E07, - 0xB0000000, 0x00000000, - 0x1B80, 0x23411E15, - 0x1B80, 0x23411E17, - 0x1B80, 0x70611E25, - 0x1B80, 0x70611E27, - 0x1B80, 0x4D001E35, - 0x1B80, 0x4D001E37, - 0x1B80, 0x00011E45, - 0x1B80, 0x00011E47, - 0x1B80, 0x00001E55, - 0x1B80, 0x00001E57, - 0x1B80, 0x00001E65, - 0x1B80, 0x00001E67, - 0x1B80, 0x00001E75, - 0x1B80, 0x00001E77, - 0x1B80, 0x00001E85, - 0x1B80, 0x00001E87, - 0x1B80, 0x00001E95, - 0x1B80, 0x00001E97, - 0x1B80, 0x00001EA5, - 0x1B80, 0x00001EA7, - 0x1B80, 0x00001EB5, - 0x1B80, 0x00001EB7, - 0x1B80, 0x00001EC5, - 0x1B80, 0x00001EC7, - 0x1B80, 0x00001ED5, - 0x1B80, 0x00001ED7, - 0x1B80, 0x00001EE5, - 0x1B80, 0x00001EE7, - 0x1B80, 0x00001EF5, - 0x1B80, 0x00001EF7, - 0x1B80, 0x00001F05, - 0x1B80, 0x00001F07, - 0x1B80, 0x00001F15, - 0x1B80, 0x00001F17, - 0x1B80, 0x00001F25, - 0x1B80, 0x00001F27, - 0x1B80, 0x00001F35, - 0x1B80, 0x00001F37, - 0x1B80, 0x00001F45, - 0x1B80, 0x00001F47, - 0x1B80, 0x00001F55, - 0x1B80, 0x00001F57, - 0x1B80, 0x00001F65, - 0x1B80, 0x00001F67, - 0x1B80, 0x00001F75, - 0x1B80, 0x00001F77, - 0x1B80, 0x00001F85, - 0x1B80, 0x00001F87, - 0x1B80, 0x00001F95, - 0x1B80, 0x00001F97, - 0x1B80, 0x00001FA5, - 0x1B80, 0x00001FA7, - 0x1B80, 0x00001FB5, - 0x1B80, 0x00001FB7, - 0x1B80, 0x00001FC5, - 0x1B80, 0x00001FC7, - 0x1B80, 0x00001FD5, - 0x1B80, 0x00001FD7, - 0x1B80, 0x00001FE5, - 0x1B80, 0x00001FE7, - 0x1B80, 0x00001FF5, - 0x1B80, 0x00001FF7, - 0x1B80, 0x00000006, - 0x1B80, 0x00000002, - -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8814A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_PHY_REG(void) -{ - return 107; -} - -/****************************************************************************** -* PHY_REG_MP.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_MP[] = { - 0x8FC, 0x00000000, - 0x838, 0x86667641, - -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_MP( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_MP)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_MP; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_MP\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8814A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_PHY_REG_MP(void) -{ - return 107; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type0.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type0[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, - 0, 2, 0, 0x00001820, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001824, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001828, 0xffffffff, 0x28303232, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001830, 0xffffffff, 0x26283032, - 0, 2, 1, 0x00001834, 0xffffffff, 0x30303030, - 0, 2, 1, 0x00001838, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001840, 0xffffffff, 0x26283032, - 0, 2, 0, 0x00001844, 0xffffffff, 0x30302224, - 0, 2, 1, 0x00001848, 0xffffffff, 0x28303030, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, - 1, 2, 0, 0x00001824, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001828, 0xffffffff, 0x28303232, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001830, 0xffffffff, 0x26283032, - 1, 2, 1, 0x00001834, 0xffffffff, 0x30303030, - 1, 2, 1, 0x00001838, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001840, 0xffffffff, 0x26283032, - 1, 2, 0, 0x00001844, 0xffffffff, 0x30302224, - 1, 2, 1, 0x00001848, 0xffffffff, 0x28303030, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type0)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type0; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type1.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type1[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type1)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type1; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type2.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type2[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, - 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type2)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type2; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type3.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type3[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x42444646, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x42444646, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x46463840, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x46464646, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x38404244, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x42444646, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x38383840, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x48484848, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x42444646, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x42444646, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x46463840, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x46464646, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x38404244, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x42444646, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x38383840, - 0, 2, 0, 0x00001820, 0xffffffff, 0x48484848, - 0, 2, 0, 0x00001824, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001828, 0xffffffff, 0x44464646, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001830, 0xffffffff, 0x42444646, - 0, 2, 1, 0x00001834, 0xffffffff, 0x46464646, - 0, 2, 1, 0x00001838, 0xffffffff, 0x42444646, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x42444646, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001840, 0xffffffff, 0x42444646, - 0, 2, 0, 0x00001844, 0xffffffff, 0x46463840, - 0, 2, 1, 0x00001848, 0xffffffff, 0x46464646, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x38404244, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x42444646, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x38383840, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x48484848, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x42444646, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x42444646, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x46463840, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x46464646, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x38404244, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x42444646, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x38383840, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x42444646, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x42444646, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x46463840, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x46464646, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x38404244, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x42444646, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x38383840, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x42444646, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x42444646, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x46463840, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x46464646, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x38404244, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x42444646, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x38383840, - 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001828, 0xffffffff, 0x44464646, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001830, 0xffffffff, 0x42444646, - 1, 2, 1, 0x00001834, 0xffffffff, 0x46464646, - 1, 2, 1, 0x00001838, 0xffffffff, 0x42444646, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x42444646, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001840, 0xffffffff, 0x42444646, - 1, 2, 0, 0x00001844, 0xffffffff, 0x46463840, - 1, 2, 1, 0x00001848, 0xffffffff, 0x46464646, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x38404244, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x42444646, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x38383840, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x42444646, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x42444646, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x46463840, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x46464646, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x38404244, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x42444646, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x38383840 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type3)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type3; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type4.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type4[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x42424242, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424242, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x42424242, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x42424242, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x34363840, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x42424242, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x42423032, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x38404242, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x30323436, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x34363840, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x30303032, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x42424242, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424242, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x42424242, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x42424242, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x34363840, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x42424242, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x42423032, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x38404242, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x30323436, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x34363840, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x30303032, - 0, 2, 0, 0x00001820, 0xffffffff, 0x42424242, - 0, 2, 0, 0x00001824, 0xffffffff, 0x42424242, - 0, 2, 0, 0x00001828, 0xffffffff, 0x36384042, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x42424242, - 0, 2, 0, 0x00001830, 0xffffffff, 0x34363840, - 0, 2, 1, 0x00001834, 0xffffffff, 0x42424242, - 0, 2, 1, 0x00001838, 0xffffffff, 0x34363840, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x42424242, - 0, 2, 0, 0x00001840, 0xffffffff, 0x34363840, - 0, 2, 0, 0x00001844, 0xffffffff, 0x42423032, - 0, 2, 1, 0x00001848, 0xffffffff, 0x38404242, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x30323436, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x34363840, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x30303032, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x42424242, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x42424242, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x36384042, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x42424242, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x34363840, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x42424242, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x34363840, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x42424242, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x34363840, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x42423032, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x38404242, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x30323436, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x34363840, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x30303032, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424242, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x36384042, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x42424242, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x34363840, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x42424242, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x34363840, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x42424242, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x42423032, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x38404242, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x30323436, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x34363840, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x30303032, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424242, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x36384042, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x42424242, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x34363840, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x42424242, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x34363840, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x42424242, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x42423032, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x38404242, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x30323436, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x34363840, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x30303032, - 1, 2, 0, 0x00001824, 0xffffffff, 0x42424242, - 1, 2, 0, 0x00001828, 0xffffffff, 0x36384042, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x42424242, - 1, 2, 0, 0x00001830, 0xffffffff, 0x34363840, - 1, 2, 1, 0x00001834, 0xffffffff, 0x42424242, - 1, 2, 1, 0x00001838, 0xffffffff, 0x34363840, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x42424242, - 1, 2, 0, 0x00001840, 0xffffffff, 0x34363840, - 1, 2, 0, 0x00001844, 0xffffffff, 0x42423032, - 1, 2, 1, 0x00001848, 0xffffffff, 0x38404242, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x30323436, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x34363840, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x30303032, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x42424242, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x36384042, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x42424242, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x34363840, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x42424242, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x34363840, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x42424242, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x34363840, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x42423032, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x38404242, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x30323436, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x34363840, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x30303032 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type4)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type4; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type5.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type5[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x40424444, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x38404242, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x44444040, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x44444444, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x38384042, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x38404242, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20203636, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x48484848, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x44444444, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x40424444, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x38404242, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x44444040, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x44444444, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x38384042, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x38404242, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20203636, - 0, 2, 0, 0x00001820, 0xffffffff, 0x48484848, - 0, 2, 0, 0x00001824, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001828, 0xffffffff, 0x44464646, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001830, 0xffffffff, 0x42444646, - 0, 2, 1, 0x00001834, 0xffffffff, 0x44444444, - 0, 2, 1, 0x00001838, 0xffffffff, 0x40424444, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x38404242, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, - 0, 2, 0, 0x00001840, 0xffffffff, 0x42444646, - 0, 2, 0, 0x00001844, 0xffffffff, 0x44444040, - 0, 2, 1, 0x00001848, 0xffffffff, 0x44444444, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x38384042, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x38404242, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20203636, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x48484848, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x44444444, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x40424444, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x38404242, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x44444040, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x44444444, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x38384042, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x38404242, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20203636, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x40424444, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x38404242, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x44443840, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x44444444, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x36384042, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x38404242, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20203436, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x44444444, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x40424444, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x38404242, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x44443840, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x44444444, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x36384042, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x38404242, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20203436, - 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001828, 0xffffffff, 0x44464646, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001830, 0xffffffff, 0x42444646, - 1, 2, 1, 0x00001834, 0xffffffff, 0x44444444, - 1, 2, 1, 0x00001838, 0xffffffff, 0x40424444, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x38404242, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001840, 0xffffffff, 0x42444646, - 1, 2, 0, 0x00001844, 0xffffffff, 0x44443840, - 1, 2, 1, 0x00001848, 0xffffffff, 0x44444444, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x36384042, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x38404242, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20203436, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x44444444, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x40424444, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x38404242, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x44443840, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x44444444, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x36384042, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x38404242, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20203436 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type5)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type5; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type6.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type6[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, - 0, 2, 0, 0x00001820, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001824, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001828, 0xffffffff, 0x28303232, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001830, 0xffffffff, 0x26283032, - 0, 2, 1, 0x00001834, 0xffffffff, 0x30303030, - 0, 2, 1, 0x00001838, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, - 0, 2, 0, 0x00001840, 0xffffffff, 0x26283032, - 0, 2, 0, 0x00001844, 0xffffffff, 0x30302224, - 0, 2, 1, 0x00001848, 0xffffffff, 0x28303030, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, - 1, 2, 0, 0x00001824, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001828, 0xffffffff, 0x28303232, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001830, 0xffffffff, 0x26283032, - 1, 2, 1, 0x00001834, 0xffffffff, 0x30303030, - 1, 2, 1, 0x00001838, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, - 1, 2, 0, 0x00001840, 0xffffffff, 0x26283032, - 1, 2, 0, 0x00001844, 0xffffffff, 0x30302224, - 1, 2, 1, 0x00001848, 0xffffffff, 0x28303030, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type6)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type6; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type7.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type7[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34343434, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x34342426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x32343434, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x28303234, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x24263434, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34343434, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x34342426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x32343434, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x28303234, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x24263434, - 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 0, 2, 1, 0x00001834, 0xffffffff, 0x34343434, - 0, 2, 1, 0x00001838, 0xffffffff, 0x28303234, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x34342426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x32343434, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x28303234, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x24263434, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x34343434, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x34342426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x32343434, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x28303234, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x24263434, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x34343434, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x34342426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x32343434, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x28303234, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x24263434, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x34343434, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x34342426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x32343434, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x28303234, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x24263434, - 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, - 1, 2, 1, 0x00001834, 0xffffffff, 0x34343434, - 1, 2, 1, 0x00001838, 0xffffffff, 0x28303234, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 1, 2, 0, 0x00001844, 0xffffffff, 0x34342426, - 1, 2, 1, 0x00001848, 0xffffffff, 0x32343434, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x24262830, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x28303234, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x24263434, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x34343434, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x34342426, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x32343434, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x24262830, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x28303234, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x24263434 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type7)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type7; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type8.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type8[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x43434343, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x43434343, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x35373941, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x43434343, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x33353739, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x43434343, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x31333537, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x43434343, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x29313335, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x43434343, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x43434343, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x35373941, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x41434343, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x33353739, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x39414141, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x31333537, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x37393939, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x29313335, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 0, 2, 0, 0x00001820, 0xffffffff, 0x43434343, - 0, 2, 0, 0x00001824, 0xffffffff, 0x43434343, - 0, 2, 0, 0x00001828, 0xffffffff, 0x35373941, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x41434343, - 0, 2, 0, 0x00001830, 0xffffffff, 0x33353739, - 0, 2, 1, 0x00001834, 0xffffffff, 0x39414141, - 0, 2, 1, 0x00001838, 0xffffffff, 0x31333537, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x37393939, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x29313335, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x43434343, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x43434343, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x35373941, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x41434343, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x33353739, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x39414141, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x31333537, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x37393939, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x29313335, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x39414345, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x38404244, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x36384042, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x46463738, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x42444646, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x35373840, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x37394143, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x33333335, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x39414345, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x38404244, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x36384042, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x46463738, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x42444646, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x35373840, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x37394143, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x33333335, - 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001828, 0xffffffff, 0x39414345, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001830, 0xffffffff, 0x38404244, - 1, 2, 1, 0x00001834, 0xffffffff, 0x46464646, - 1, 2, 1, 0x00001838, 0xffffffff, 0x36384042, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, - 1, 2, 0, 0x00001840, 0xffffffff, 0x38404244, - 1, 2, 0, 0x00001844, 0xffffffff, 0x46463738, - 1, 2, 1, 0x00001848, 0xffffffff, 0x42444646, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x35373840, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x37394143, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x33333335, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x39414345, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x38404244, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x36384042, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x38404244, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x46463738, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x42444646, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x35373840, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x37394143, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x33333335 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type8)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type8; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_Type9.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_PHY_REG_PG_Type9[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x44444444, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x44444444, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x44444444, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x32343638, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x44444444, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x44444444, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x44444444, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40444444, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x32343638, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404040, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, - 0, 1, 2, 0x00000ed8, 0xffffffff, 0x36383838, - 0, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, - 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, - 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, - 0, 2, 0, 0x00001820, 0xffffffff, 0x44444444, - 0, 2, 0, 0x00001824, 0xffffffff, 0x44444444, - 0, 2, 0, 0x00001828, 0xffffffff, 0x34363840, - 0, 2, 0, 0x0000182c, 0xffffffff, 0x40444444, - 0, 2, 0, 0x00001830, 0xffffffff, 0x32343638, - 0, 2, 1, 0x00001834, 0xffffffff, 0x38404040, - 0, 2, 1, 0x00001838, 0xffffffff, 0x30323436, - 0, 2, 2, 0x000018d8, 0xffffffff, 0x36383838, - 0, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, - 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, - 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, - 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, - 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, - 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, - 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, - 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, - 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, - 0, 3, 0, 0x00001a20, 0xffffffff, 0x44444444, - 0, 3, 0, 0x00001a24, 0xffffffff, 0x44444444, - 0, 3, 0, 0x00001a28, 0xffffffff, 0x34363840, - 0, 3, 0, 0x00001a2c, 0xffffffff, 0x40444444, - 0, 3, 0, 0x00001a30, 0xffffffff, 0x32343638, - 0, 3, 1, 0x00001a34, 0xffffffff, 0x38404040, - 0, 3, 1, 0x00001a38, 0xffffffff, 0x30323436, - 0, 3, 2, 0x00001ad8, 0xffffffff, 0x36383838, - 0, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, - 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, - 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, - 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, - 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, - 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, - 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, - 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x36363636, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x36363636, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x29313335, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x35353535, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x27293133, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363636, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x29313335, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x35352426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x32343535, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x23252830, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x27293133, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x22222224, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x36363636, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x36363636, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x29313335, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x35353535, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, - 1, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, - 1, 1, 2, 0x00000edc, 0xffffffff, 0x27293133, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x36363636, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x29313335, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x35352426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x32343535, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x23252830, - 1, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, - 1, 1, 2, 0x00000ee4, 0xffffffff, 0x27293133, - 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x22222224, - 1, 2, 0, 0x00001824, 0xffffffff, 0x36363636, - 1, 2, 0, 0x00001828, 0xffffffff, 0x30323436, - 1, 2, 0, 0x0000182c, 0xffffffff, 0x36363636, - 1, 2, 0, 0x00001830, 0xffffffff, 0x29313335, - 1, 2, 1, 0x00001834, 0xffffffff, 0x35353535, - 1, 2, 1, 0x00001838, 0xffffffff, 0x28303234, - 1, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, - 1, 2, 2, 0x000018dc, 0xffffffff, 0x27293133, - 1, 2, 0, 0x0000183c, 0xffffffff, 0x36363636, - 1, 2, 0, 0x00001840, 0xffffffff, 0x29313335, - 1, 2, 0, 0x00001844, 0xffffffff, 0x35352426, - 1, 2, 1, 0x00001848, 0xffffffff, 0x32343535, - 1, 2, 1, 0x0000184c, 0xffffffff, 0x23252830, - 1, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, - 1, 2, 2, 0x000018e4, 0xffffffff, 0x27293133, - 1, 2, 2, 0x000018e8, 0x0000ffff, 0x22222224, - 1, 3, 0, 0x00001a24, 0xffffffff, 0x36363636, - 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323436, - 1, 3, 0, 0x00001a2c, 0xffffffff, 0x36363636, - 1, 3, 0, 0x00001a30, 0xffffffff, 0x29313335, - 1, 3, 1, 0x00001a34, 0xffffffff, 0x35353535, - 1, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, - 1, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, - 1, 3, 2, 0x00001adc, 0xffffffff, 0x27293133, - 1, 3, 0, 0x00001a3c, 0xffffffff, 0x36363636, - 1, 3, 0, 0x00001a40, 0xffffffff, 0x29313335, - 1, 3, 0, 0x00001a44, 0xffffffff, 0x35352426, - 1, 3, 1, 0x00001a48, 0xffffffff, 0x32343535, - 1, 3, 1, 0x00001a4c, 0xffffffff, 0x23252830, - 1, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, - 1, 3, 2, 0x00001ae4, 0xffffffff, 0x27293133, - 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x22222224 -}; - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type9)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type9; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_AGC_TAB[] = { + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000003, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xCF240003, + 0x81C, 0xCE260003, + 0x81C, 0xCD280003, + 0x81C, 0xCC2A0003, + 0x81C, 0xCB2C0003, + 0x81C, 0xCA2E0003, + 0x81C, 0xC9300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xA63C0003, + 0x81C, 0xA53E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0xA1460003, + 0x81C, 0x86480003, + 0x81C, 0x854A0003, + 0x81C, 0x844C0003, + 0x81C, 0x834E0003, + 0x81C, 0x66500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x27620003, + 0x81C, 0x26640003, + 0x81C, 0x25660003, + 0x81C, 0x24680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x216E0003, + 0x81C, 0x21700003, + 0x81C, 0x21720003, + 0x81C, 0x21740003, + 0x81C, 0x21760003, + 0x81C, 0x21780003, + 0x81C, 0x217A0003, + 0x81C, 0x217C0003, + 0x81C, 0x217E0003, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE020003, + 0x81C, 0xFD040003, + 0x81C, 0xFC060003, + 0x81C, 0xFB080003, + 0x81C, 0xFA0A0003, + 0x81C, 0xF90C0003, + 0x81C, 0xF80E0003, + 0x81C, 0xF7100003, + 0x81C, 0xF6120003, + 0x81C, 0xF5140003, + 0x81C, 0xF4160003, + 0x81C, 0xF3180003, + 0x81C, 0xF21A0003, + 0x81C, 0xF11C0003, + 0x81C, 0xF01E0003, + 0x81C, 0xEF200003, + 0x81C, 0xEE220003, + 0x81C, 0xED240003, + 0x81C, 0xEC260003, + 0x81C, 0xEB280003, + 0x81C, 0xEA2A0003, + 0x81C, 0xE92C0003, + 0x81C, 0xE82E0003, + 0x81C, 0xE7300003, + 0x81C, 0xE6320003, + 0x81C, 0xE5340003, + 0x81C, 0xE4360003, + 0x81C, 0xE3380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xA8440003, + 0x81C, 0xA7460003, + 0x81C, 0xA6480003, + 0x81C, 0xA54A0003, + 0x81C, 0xA44C0003, + 0x81C, 0xA34E0003, + 0x81C, 0xA2500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x475C0003, + 0x81C, 0x465E0003, + 0x81C, 0x45600003, + 0x81C, 0x44620003, + 0x81C, 0x43640003, + 0x81C, 0x42660003, + 0x81C, 0x41680003, + 0x81C, 0x416A0003, + 0x81C, 0x416C0003, + 0x81C, 0x416E0003, + 0x81C, 0x41700003, + 0x81C, 0x41720003, + 0x81C, 0x41740003, + 0x81C, 0x41760003, + 0x81C, 0x41780003, + 0x81C, 0x417A0003, + 0x81C, 0x417C0003, + 0x81C, 0x417E0003, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xE4340003, + 0x81C, 0xE3360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xA9420003, + 0x81C, 0xA8440003, + 0x81C, 0xA7460003, + 0x81C, 0xA6480003, + 0x81C, 0xA54A0003, + 0x81C, 0xA44C0003, + 0x81C, 0xA34E0003, + 0x81C, 0x66500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x49580003, + 0x81C, 0x485A0003, + 0x81C, 0x475C0003, + 0x81C, 0x465E0003, + 0x81C, 0x45600003, + 0x81C, 0x44620003, + 0x81C, 0x43640003, + 0x81C, 0x42660003, + 0x81C, 0x41680003, + 0x81C, 0x416A0003, + 0x81C, 0x416C0003, + 0x81C, 0x416E0003, + 0x81C, 0x41700003, + 0x81C, 0x41720003, + 0x81C, 0x41740003, + 0x81C, 0x41760003, + 0x81C, 0x41780003, + 0x81C, 0x417A0003, + 0x81C, 0x417C0003, + 0x81C, 0x417E0003, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE020003, + 0x81C, 0xFD040003, + 0x81C, 0xFC060003, + 0x81C, 0xFB080003, + 0x81C, 0xFA0A0003, + 0x81C, 0xF90C0003, + 0x81C, 0xF80E0003, + 0x81C, 0xF7100003, + 0x81C, 0xF6120003, + 0x81C, 0xF5140003, + 0x81C, 0xF4160003, + 0x81C, 0xF3180003, + 0x81C, 0xF21A0003, + 0x81C, 0xF11C0003, + 0x81C, 0xF01E0003, + 0x81C, 0xEF200003, + 0x81C, 0xEE220003, + 0x81C, 0xED240003, + 0x81C, 0xEC260003, + 0x81C, 0xEB280003, + 0x81C, 0xEA2A0003, + 0x81C, 0xE92C0003, + 0x81C, 0xE82E0003, + 0x81C, 0xE7300003, + 0x81C, 0xE6320003, + 0x81C, 0xE5340003, + 0x81C, 0xE4360003, + 0x81C, 0xE3380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xA8440003, + 0x81C, 0xA7460003, + 0x81C, 0xA6480003, + 0x81C, 0xA54A0003, + 0x81C, 0xA44C0003, + 0x81C, 0xA34E0003, + 0x81C, 0xA2500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x475C0003, + 0x81C, 0x465E0003, + 0x81C, 0x45600003, + 0x81C, 0x44620003, + 0x81C, 0x43640003, + 0x81C, 0x42660003, + 0x81C, 0x41680003, + 0x81C, 0x416A0003, + 0x81C, 0x416C0003, + 0x81C, 0x416E0003, + 0x81C, 0x41700003, + 0x81C, 0x41720003, + 0x81C, 0x41740003, + 0x81C, 0x41760003, + 0x81C, 0x41780003, + 0x81C, 0x417A0003, + 0x81C, 0x417C0003, + 0x81C, 0x417E0003, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xE4340003, + 0x81C, 0xE3360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xA9420003, + 0x81C, 0xA8440003, + 0x81C, 0xA7460003, + 0x81C, 0xA6480003, + 0x81C, 0xA54A0003, + 0x81C, 0xA44C0003, + 0x81C, 0xA34E0003, + 0x81C, 0x66500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x49580003, + 0x81C, 0x485A0003, + 0x81C, 0x475C0003, + 0x81C, 0x465E0003, + 0x81C, 0x45600003, + 0x81C, 0x44620003, + 0x81C, 0x43640003, + 0x81C, 0x42660003, + 0x81C, 0x41680003, + 0x81C, 0x416A0003, + 0x81C, 0x416C0003, + 0x81C, 0x416E0003, + 0x81C, 0x41700003, + 0x81C, 0x41720003, + 0x81C, 0x41740003, + 0x81C, 0x41760003, + 0x81C, 0x41780003, + 0x81C, 0x417A0003, + 0x81C, 0x417C0003, + 0x81C, 0x417E0003, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xDF000003, + 0x81C, 0xDF020003, + 0x81C, 0xDF040003, + 0x81C, 0xDE060003, + 0x81C, 0xDD080003, + 0x81C, 0xDC0A0003, + 0x81C, 0xDB0C0003, + 0x81C, 0xDA0E0003, + 0x81C, 0xD9100003, + 0x81C, 0xD8120003, + 0x81C, 0xD7140003, + 0x81C, 0xD6160003, + 0x81C, 0xD5180003, + 0x81C, 0xD41A0003, + 0x81C, 0xD31C0003, + 0x81C, 0xD21E0003, + 0x81C, 0xD1200003, + 0x81C, 0xD0220003, + 0x81C, 0xCF240003, + 0x81C, 0xCE260003, + 0x81C, 0xCD280003, + 0x81C, 0xCC2A0003, + 0x81C, 0xCB2C0003, + 0x81C, 0xCA2E0003, + 0x81C, 0xC9300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xA73A0003, + 0x81C, 0xA63C0003, + 0x81C, 0xA53E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0x87460003, + 0x81C, 0x86480003, + 0x81C, 0x854A0003, + 0x81C, 0x844C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x445C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x27640003, + 0x81C, 0x26660003, + 0x81C, 0x25680003, + 0x81C, 0x246A0003, + 0x81C, 0x236C0003, + 0x81C, 0x226E0003, + 0x81C, 0x21700003, + 0x81C, 0x21720003, + 0x81C, 0x21740003, + 0x81C, 0x21760003, + 0x81C, 0x21780003, + 0x81C, 0x217A0003, + 0x81C, 0x217C0003, + 0x81C, 0x217E0003, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE020003, + 0x81C, 0xFD040003, + 0x81C, 0xFC060003, + 0x81C, 0xFB080003, + 0x81C, 0xFA0A0003, + 0x81C, 0xF90C0003, + 0x81C, 0xF80E0003, + 0x81C, 0xF7100003, + 0x81C, 0xF6120003, + 0x81C, 0xF5140003, + 0x81C, 0xF4160003, + 0x81C, 0xF3180003, + 0x81C, 0xF21A0003, + 0x81C, 0xF11C0003, + 0x81C, 0xF01E0003, + 0x81C, 0xEF200003, + 0x81C, 0xEE220003, + 0x81C, 0xED240003, + 0x81C, 0xEC260003, + 0x81C, 0xEB280003, + 0x81C, 0xEA2A0003, + 0x81C, 0xE92C0003, + 0x81C, 0xE82E0003, + 0x81C, 0xE7300003, + 0x81C, 0xE6320003, + 0x81C, 0xE5340003, + 0x81C, 0xE4360003, + 0x81C, 0xE3380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xA8440003, + 0x81C, 0xA7460003, + 0x81C, 0xA6480003, + 0x81C, 0xA54A0003, + 0x81C, 0xA44C0003, + 0x81C, 0xA34E0003, + 0x81C, 0xA2500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x475C0003, + 0x81C, 0x465E0003, + 0x81C, 0x45600003, + 0x81C, 0x44620003, + 0x81C, 0x43640003, + 0x81C, 0x42660003, + 0x81C, 0x41680003, + 0x81C, 0x416A0003, + 0x81C, 0x416C0003, + 0x81C, 0x416E0003, + 0x81C, 0x41700003, + 0x81C, 0x41720003, + 0x81C, 0x41740003, + 0x81C, 0x41760003, + 0x81C, 0x41780003, + 0x81C, 0x417A0003, + 0x81C, 0x417C0003, + 0x81C, 0x417E0003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xDF000003, + 0x81C, 0xDF020003, + 0x81C, 0xDF040003, + 0x81C, 0xDE060003, + 0x81C, 0xDD080003, + 0x81C, 0xDC0A0003, + 0x81C, 0xDB0C0003, + 0x81C, 0xDA0E0003, + 0x81C, 0xD9100003, + 0x81C, 0xD8120003, + 0x81C, 0xD7140003, + 0x81C, 0xD6160003, + 0x81C, 0xD5180003, + 0x81C, 0xD41A0003, + 0x81C, 0xD31C0003, + 0x81C, 0xD21E0003, + 0x81C, 0xD1200003, + 0x81C, 0xD0220003, + 0x81C, 0xCF240003, + 0x81C, 0xCE260003, + 0x81C, 0xCD280003, + 0x81C, 0xCC2A0003, + 0x81C, 0xCB2C0003, + 0x81C, 0xCA2E0003, + 0x81C, 0xC9300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xA73A0003, + 0x81C, 0xA63C0003, + 0x81C, 0xA53E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0x87460003, + 0x81C, 0x86480003, + 0x81C, 0x854A0003, + 0x81C, 0x844C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x445C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x27640003, + 0x81C, 0x26660003, + 0x81C, 0x25680003, + 0x81C, 0x246A0003, + 0x81C, 0x236C0003, + 0x81C, 0x226E0003, + 0x81C, 0x21700003, + 0x81C, 0x21720003, + 0x81C, 0x21740003, + 0x81C, 0x21760003, + 0x81C, 0x21780003, + 0x81C, 0x217A0003, + 0x81C, 0x217C0003, + 0x81C, 0x217E0003, + 0xA0000000, 0x00000000, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xCF240003, + 0x81C, 0xCE260003, + 0x81C, 0xCD280003, + 0x81C, 0xCC2A0003, + 0x81C, 0xCB2C0003, + 0x81C, 0xCA2E0003, + 0x81C, 0xC9300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xA63C0003, + 0x81C, 0xA53E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0xA1460003, + 0x81C, 0x86480003, + 0x81C, 0x854A0003, + 0x81C, 0x844C0003, + 0x81C, 0x834E0003, + 0x81C, 0x66500003, + 0x81C, 0x65520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x615A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x27620003, + 0x81C, 0x26640003, + 0x81C, 0x25660003, + 0x81C, 0x24680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x216E0003, + 0x81C, 0x21700003, + 0x81C, 0x21720003, + 0x81C, 0x21740003, + 0x81C, 0x21760003, + 0x81C, 0x21780003, + 0x81C, 0x217A0003, + 0x81C, 0x217C0003, + 0x81C, 0x217E0003, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000103, + 0x81C, 0xF8020103, + 0x81C, 0xF7040103, + 0x81C, 0xF6060103, + 0x81C, 0xF5080103, + 0x81C, 0xF40A0103, + 0x81C, 0xF30C0103, + 0x81C, 0xF20E0103, + 0x81C, 0xF1100103, + 0x81C, 0xF0120103, + 0x81C, 0xEF140103, + 0x81C, 0xEE160103, + 0x81C, 0xED180103, + 0x81C, 0xEC1A0103, + 0x81C, 0xEB1C0103, + 0x81C, 0xEA1E0103, + 0x81C, 0xE9200103, + 0x81C, 0xE8220103, + 0x81C, 0xE7240103, + 0x81C, 0xE6260103, + 0x81C, 0xE5280103, + 0x81C, 0xE42A0103, + 0x81C, 0xE32C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA5340103, + 0x81C, 0xA4360103, + 0x81C, 0xA3380103, + 0x81C, 0xA23A0103, + 0x81C, 0xA13C0103, + 0x81C, 0x843E0103, + 0x81C, 0x83400103, + 0x81C, 0x82420103, + 0x81C, 0x81440103, + 0x81C, 0x64460103, + 0x81C, 0x63480103, + 0x81C, 0x624A0103, + 0x81C, 0x614C0103, + 0x81C, 0x444E0103, + 0x81C, 0x43500103, + 0x81C, 0x42520103, + 0x81C, 0x41540103, + 0x81C, 0x25560103, + 0x81C, 0x24580103, + 0x81C, 0x235A0103, + 0x81C, 0x065C0103, + 0x81C, 0x055E0103, + 0x81C, 0x04600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xE12E0103, + 0x81C, 0xA5300103, + 0x81C, 0xA4320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0x843A0103, + 0x81C, 0x833C0103, + 0x81C, 0x823E0103, + 0x81C, 0x81400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x454A0103, + 0x81C, 0x444C0103, + 0x81C, 0x434E0103, + 0x81C, 0x42500103, + 0x81C, 0x25520103, + 0x81C, 0x24540103, + 0x81C, 0x23560103, + 0x81C, 0x06580103, + 0x81C, 0x055A0103, + 0x81C, 0x045C0103, + 0x81C, 0x035E0103, + 0x81C, 0x02600103, + 0x81C, 0x01620103, + 0x81C, 0x01640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000103, + 0x81C, 0xFB020103, + 0x81C, 0xFA040103, + 0x81C, 0xF9060103, + 0x81C, 0xF8080103, + 0x81C, 0xF70A0103, + 0x81C, 0xF60C0103, + 0x81C, 0xF50E0103, + 0x81C, 0xF4100103, + 0x81C, 0xF3120103, + 0x81C, 0xF2140103, + 0x81C, 0xF1160103, + 0x81C, 0xF0180103, + 0x81C, 0xEF1A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xE1360103, + 0x81C, 0x87380103, + 0x81C, 0x863A0103, + 0x81C, 0x853C0103, + 0x81C, 0x843E0103, + 0x81C, 0x83400103, + 0x81C, 0x82420103, + 0x81C, 0x81440103, + 0x81C, 0x64460103, + 0x81C, 0x63480103, + 0x81C, 0x624A0103, + 0x81C, 0x464C0103, + 0x81C, 0x454E0103, + 0x81C, 0x44500103, + 0x81C, 0x43520103, + 0x81C, 0x26540103, + 0x81C, 0x25560103, + 0x81C, 0x24580103, + 0x81C, 0x075A0103, + 0x81C, 0x065C0103, + 0x81C, 0x055E0103, + 0x81C, 0x04600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000103, + 0x81C, 0xF8020103, + 0x81C, 0xF7040103, + 0x81C, 0xF6060103, + 0x81C, 0xF5080103, + 0x81C, 0xF40A0103, + 0x81C, 0xF30C0103, + 0x81C, 0xF20E0103, + 0x81C, 0xF1100103, + 0x81C, 0xF0120103, + 0x81C, 0xEF140103, + 0x81C, 0xEE160103, + 0x81C, 0xED180103, + 0x81C, 0xEC1A0103, + 0x81C, 0xEB1C0103, + 0x81C, 0xEA1E0103, + 0x81C, 0xE9200103, + 0x81C, 0xE8220103, + 0x81C, 0xE7240103, + 0x81C, 0xE6260103, + 0x81C, 0xE5280103, + 0x81C, 0xE42A0103, + 0x81C, 0xE32C0103, + 0x81C, 0xE22E0103, + 0x81C, 0xA6300103, + 0x81C, 0xA5320103, + 0x81C, 0xA4340103, + 0x81C, 0xA3360103, + 0x81C, 0xA2380103, + 0x81C, 0xA13A0103, + 0x81C, 0x843C0103, + 0x81C, 0x833E0103, + 0x81C, 0x82400103, + 0x81C, 0x81420103, + 0x81C, 0x64440103, + 0x81C, 0x63460103, + 0x81C, 0x62480103, + 0x81C, 0x614A0103, + 0x81C, 0x444C0103, + 0x81C, 0x434E0103, + 0x81C, 0x42500103, + 0x81C, 0x41520103, + 0x81C, 0x25540103, + 0x81C, 0x24560103, + 0x81C, 0x23580103, + 0x81C, 0x225A0103, + 0x81C, 0x055C0103, + 0x81C, 0x045E0103, + 0x81C, 0x03600103, + 0x81C, 0x02620103, + 0x81C, 0x01640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xE2360103, + 0x81C, 0xE1380103, + 0x81C, 0xA33A0103, + 0x81C, 0xA23C0103, + 0x81C, 0xA13E0103, + 0x81C, 0x84400103, + 0x81C, 0x83420103, + 0x81C, 0x82440103, + 0x81C, 0x81460103, + 0x81C, 0x64480103, + 0x81C, 0x634A0103, + 0x81C, 0x624C0103, + 0x81C, 0x614E0103, + 0x81C, 0x45500103, + 0x81C, 0x44520103, + 0x81C, 0x43540103, + 0x81C, 0x42560103, + 0x81C, 0x25580103, + 0x81C, 0x245A0103, + 0x81C, 0x235C0103, + 0x81C, 0x065E0103, + 0x81C, 0x05600103, + 0x81C, 0x04620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFA000103, + 0x81C, 0xF9020103, + 0x81C, 0xF8040103, + 0x81C, 0xF7060103, + 0x81C, 0xF6080103, + 0x81C, 0xF50A0103, + 0x81C, 0xF40C0103, + 0x81C, 0xF30E0103, + 0x81C, 0xF2100103, + 0x81C, 0xF1120103, + 0x81C, 0xF0140103, + 0x81C, 0xEF160103, + 0x81C, 0xEE180103, + 0x81C, 0xED1A0103, + 0x81C, 0xEC1C0103, + 0x81C, 0xEB1E0103, + 0x81C, 0xEA200103, + 0x81C, 0xE9220103, + 0x81C, 0xE8240103, + 0x81C, 0xE7260103, + 0x81C, 0xE6280103, + 0x81C, 0xE52A0103, + 0x81C, 0xE42C0103, + 0x81C, 0xE32E0103, + 0x81C, 0xE2300103, + 0x81C, 0xE1320103, + 0x81C, 0xA5340103, + 0x81C, 0xA4360103, + 0x81C, 0xA3380103, + 0x81C, 0xA23A0103, + 0x81C, 0xA13C0103, + 0x81C, 0x843E0103, + 0x81C, 0x83400103, + 0x81C, 0x82420103, + 0x81C, 0x81440103, + 0x81C, 0x64460103, + 0x81C, 0x63480103, + 0x81C, 0x624A0103, + 0x81C, 0x614C0103, + 0x81C, 0x454E0103, + 0x81C, 0x44500103, + 0x81C, 0x43520103, + 0x81C, 0x42540103, + 0x81C, 0x41560103, + 0x81C, 0x24580103, + 0x81C, 0x235A0103, + 0x81C, 0x225C0103, + 0x81C, 0x055E0103, + 0x81C, 0x04600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000103, + 0x81C, 0xFF020103, + 0x81C, 0xFE040103, + 0x81C, 0xFD060103, + 0x81C, 0xFC080103, + 0x81C, 0xFB0A0103, + 0x81C, 0xFA0C0103, + 0x81C, 0xF90E0103, + 0x81C, 0xF8100103, + 0x81C, 0xF7120103, + 0x81C, 0xF6140103, + 0x81C, 0xF5160103, + 0x81C, 0xF4180103, + 0x81C, 0xF31A0103, + 0x81C, 0xF21C0103, + 0x81C, 0xF11E0103, + 0x81C, 0xF0200103, + 0x81C, 0xEF220103, + 0x81C, 0xEE240103, + 0x81C, 0xED260103, + 0x81C, 0xEC280103, + 0x81C, 0xEB2A0103, + 0x81C, 0xEA2C0103, + 0x81C, 0xE92E0103, + 0x81C, 0xE8300103, + 0x81C, 0xE7320103, + 0x81C, 0xE6340103, + 0x81C, 0xE5360103, + 0x81C, 0xE4380103, + 0x81C, 0xE33A0103, + 0x81C, 0xA53C0103, + 0x81C, 0xA43E0103, + 0x81C, 0xA3400103, + 0x81C, 0xA2420103, + 0x81C, 0xA1440103, + 0x81C, 0x85460103, + 0x81C, 0x84480103, + 0x81C, 0x834A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x64500103, + 0x81C, 0x63520103, + 0x81C, 0x62540103, + 0x81C, 0x44560103, + 0x81C, 0x43580103, + 0x81C, 0x425A0103, + 0x81C, 0x265C0103, + 0x81C, 0x255E0103, + 0x81C, 0x24600103, + 0x81C, 0x07620103, + 0x81C, 0x06640103, + 0x81C, 0x05660103, + 0x81C, 0x04680103, + 0x81C, 0x036A0103, + 0x81C, 0x026C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xE12E0103, + 0x81C, 0xA4300103, + 0x81C, 0xA3320103, + 0x81C, 0xA2340103, + 0x81C, 0xA1360103, + 0x81C, 0x85380103, + 0x81C, 0x843A0103, + 0x81C, 0x833C0103, + 0x81C, 0x823E0103, + 0x81C, 0x65400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x45480103, + 0x81C, 0x444A0103, + 0x81C, 0x434C0103, + 0x81C, 0x264E0103, + 0x81C, 0x25500103, + 0x81C, 0x24520103, + 0x81C, 0x08540103, + 0x81C, 0x07560103, + 0x81C, 0x06580103, + 0x81C, 0x055A0103, + 0x81C, 0x045C0103, + 0x81C, 0x035E0103, + 0x81C, 0x02600103, + 0x81C, 0x01620103, + 0x81C, 0x01640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000103, + 0x81C, 0xFF020103, + 0x81C, 0xFE040103, + 0x81C, 0xFD060103, + 0x81C, 0xFC080103, + 0x81C, 0xFB0A0103, + 0x81C, 0xFA0C0103, + 0x81C, 0xF90E0103, + 0x81C, 0xF8100103, + 0x81C, 0xF7120103, + 0x81C, 0xF6140103, + 0x81C, 0xF5160103, + 0x81C, 0xF4180103, + 0x81C, 0xF31A0103, + 0x81C, 0xF21C0103, + 0x81C, 0xF11E0103, + 0x81C, 0xF0200103, + 0x81C, 0xEF220103, + 0x81C, 0xEE240103, + 0x81C, 0xED260103, + 0x81C, 0xEC280103, + 0x81C, 0xEB2A0103, + 0x81C, 0xEA2C0103, + 0x81C, 0xE92E0103, + 0x81C, 0xE8300103, + 0x81C, 0xE7320103, + 0x81C, 0xE6340103, + 0x81C, 0xE5360103, + 0x81C, 0xE4380103, + 0x81C, 0xE33A0103, + 0x81C, 0xA53C0103, + 0x81C, 0xA43E0103, + 0x81C, 0xA3400103, + 0x81C, 0xA2420103, + 0x81C, 0xA1440103, + 0x81C, 0x85460103, + 0x81C, 0x84480103, + 0x81C, 0x834A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x64500103, + 0x81C, 0x63520103, + 0x81C, 0x62540103, + 0x81C, 0x44560103, + 0x81C, 0x43580103, + 0x81C, 0x425A0103, + 0x81C, 0x265C0103, + 0x81C, 0x255E0103, + 0x81C, 0x24600103, + 0x81C, 0x07620103, + 0x81C, 0x06640103, + 0x81C, 0x05660103, + 0x81C, 0x04680103, + 0x81C, 0x036A0103, + 0x81C, 0x026C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000103, + 0x81C, 0xFE020103, + 0x81C, 0xFD040103, + 0x81C, 0xFC060103, + 0x81C, 0xFB080103, + 0x81C, 0xFA0A0103, + 0x81C, 0xF90C0103, + 0x81C, 0xF80E0103, + 0x81C, 0xF7100103, + 0x81C, 0xF6120103, + 0x81C, 0xF5140103, + 0x81C, 0xF4160103, + 0x81C, 0xF3180103, + 0x81C, 0xF21A0103, + 0x81C, 0xF11C0103, + 0x81C, 0xF01E0103, + 0x81C, 0xEF200103, + 0x81C, 0xEE220103, + 0x81C, 0xED240103, + 0x81C, 0xEC260103, + 0x81C, 0xEB280103, + 0x81C, 0xEA2A0103, + 0x81C, 0xE92C0103, + 0x81C, 0xE82E0103, + 0x81C, 0xE7300103, + 0x81C, 0xE6320103, + 0x81C, 0xE5340103, + 0x81C, 0xE4360103, + 0x81C, 0xE3380103, + 0x81C, 0xE23A0103, + 0x81C, 0xE13C0103, + 0x81C, 0xA43E0103, + 0x81C, 0xA3400103, + 0x81C, 0xA2420103, + 0x81C, 0xA1440103, + 0x81C, 0x86460103, + 0x81C, 0x85480103, + 0x81C, 0x844A0103, + 0x81C, 0x834C0103, + 0x81C, 0x824E0103, + 0x81C, 0x81500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x435A0103, + 0x81C, 0x425C0103, + 0x81C, 0x415E0103, + 0x81C, 0x25600103, + 0x81C, 0x24620103, + 0x81C, 0x06640103, + 0x81C, 0x05660103, + 0x81C, 0x04680103, + 0x81C, 0x036A0103, + 0x81C, 0x026C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFA000203, + 0x81C, 0xF9020203, + 0x81C, 0xF8040203, + 0x81C, 0xF7060203, + 0x81C, 0xF6080203, + 0x81C, 0xF50A0203, + 0x81C, 0xF40C0203, + 0x81C, 0xF30E0203, + 0x81C, 0xF2100203, + 0x81C, 0xF1120203, + 0x81C, 0xF0140203, + 0x81C, 0xEF160203, + 0x81C, 0xEE180203, + 0x81C, 0xED1A0203, + 0x81C, 0xEC1C0203, + 0x81C, 0xEB1E0203, + 0x81C, 0xEA200203, + 0x81C, 0xE9220203, + 0x81C, 0xE8240203, + 0x81C, 0xE7260203, + 0x81C, 0xE6280203, + 0x81C, 0xE52A0203, + 0x81C, 0xE42C0203, + 0x81C, 0xE32E0203, + 0x81C, 0xE2300203, + 0x81C, 0xE1320203, + 0x81C, 0xA5340203, + 0x81C, 0xA4360203, + 0x81C, 0xA3380203, + 0x81C, 0xA23A0203, + 0x81C, 0xA13C0203, + 0x81C, 0x843E0203, + 0x81C, 0x83400203, + 0x81C, 0x82420203, + 0x81C, 0x81440203, + 0x81C, 0x63460203, + 0x81C, 0x62480203, + 0x81C, 0x614A0203, + 0x81C, 0x464C0203, + 0x81C, 0x454E0203, + 0x81C, 0x44500203, + 0x81C, 0x43520203, + 0x81C, 0x42540203, + 0x81C, 0x41560203, + 0x81C, 0x24580203, + 0x81C, 0x235A0203, + 0x81C, 0x065C0203, + 0x81C, 0x055E0203, + 0x81C, 0x04600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000203, + 0x81C, 0xF7020203, + 0x81C, 0xF6040203, + 0x81C, 0xF5060203, + 0x81C, 0xF4080203, + 0x81C, 0xF30A0203, + 0x81C, 0xF20C0203, + 0x81C, 0xF10E0203, + 0x81C, 0xF0100203, + 0x81C, 0xEF120203, + 0x81C, 0xEE140203, + 0x81C, 0xED160203, + 0x81C, 0xEC180203, + 0x81C, 0xEB1A0203, + 0x81C, 0xEA1C0203, + 0x81C, 0xE91E0203, + 0x81C, 0xE8200203, + 0x81C, 0xE7220203, + 0x81C, 0xE6240203, + 0x81C, 0xE5260203, + 0x81C, 0xE4280203, + 0x81C, 0xE32A0203, + 0x81C, 0xE22C0203, + 0x81C, 0xE12E0203, + 0x81C, 0xA6300203, + 0x81C, 0xA5320203, + 0x81C, 0xA4340203, + 0x81C, 0xA3360203, + 0x81C, 0xA2380203, + 0x81C, 0x853A0203, + 0x81C, 0x843C0203, + 0x81C, 0x833E0203, + 0x81C, 0x82400203, + 0x81C, 0x81420203, + 0x81C, 0x64440203, + 0x81C, 0x63460203, + 0x81C, 0x62480203, + 0x81C, 0x614A0203, + 0x81C, 0x444C0203, + 0x81C, 0x434E0203, + 0x81C, 0x42500203, + 0x81C, 0x25520203, + 0x81C, 0x24540203, + 0x81C, 0x23560203, + 0x81C, 0x06580203, + 0x81C, 0x055A0203, + 0x81C, 0x045C0203, + 0x81C, 0x035E0203, + 0x81C, 0x02600203, + 0x81C, 0x01620203, + 0x81C, 0x01640203, + 0x81C, 0x01660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xE1360203, + 0x81C, 0x87380203, + 0x81C, 0x863A0203, + 0x81C, 0x853C0203, + 0x81C, 0x843E0203, + 0x81C, 0x83400203, + 0x81C, 0x82420203, + 0x81C, 0x81440203, + 0x81C, 0x64460203, + 0x81C, 0x63480203, + 0x81C, 0x624A0203, + 0x81C, 0x474C0203, + 0x81C, 0x464E0203, + 0x81C, 0x45500203, + 0x81C, 0x44520203, + 0x81C, 0x43540203, + 0x81C, 0x42560203, + 0x81C, 0x24580203, + 0x81C, 0x235A0203, + 0x81C, 0x075C0203, + 0x81C, 0x065E0203, + 0x81C, 0x05600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000203, + 0x81C, 0xF7020203, + 0x81C, 0xF6040203, + 0x81C, 0xF5060203, + 0x81C, 0xF4080203, + 0x81C, 0xF30A0203, + 0x81C, 0xF20C0203, + 0x81C, 0xF10E0203, + 0x81C, 0xF0100203, + 0x81C, 0xEF120203, + 0x81C, 0xEE140203, + 0x81C, 0xED160203, + 0x81C, 0xEC180203, + 0x81C, 0xEB1A0203, + 0x81C, 0xEA1C0203, + 0x81C, 0xE91E0203, + 0x81C, 0xE8200203, + 0x81C, 0xE7220203, + 0x81C, 0xE6240203, + 0x81C, 0xE5260203, + 0x81C, 0xE4280203, + 0x81C, 0xE32A0203, + 0x81C, 0xE22C0203, + 0x81C, 0xE12E0203, + 0x81C, 0xA6300203, + 0x81C, 0xA5320203, + 0x81C, 0xA4340203, + 0x81C, 0xA3360203, + 0x81C, 0xA2380203, + 0x81C, 0xA13A0203, + 0x81C, 0x843C0203, + 0x81C, 0x833E0203, + 0x81C, 0x82400203, + 0x81C, 0x81420203, + 0x81C, 0x64440203, + 0x81C, 0x63460203, + 0x81C, 0x62480203, + 0x81C, 0x614A0203, + 0x81C, 0x444C0203, + 0x81C, 0x434E0203, + 0x81C, 0x42500203, + 0x81C, 0x41520203, + 0x81C, 0x25540203, + 0x81C, 0x24560203, + 0x81C, 0x23580203, + 0x81C, 0x065A0203, + 0x81C, 0x055C0203, + 0x81C, 0x045E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x01660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000203, + 0x81C, 0xFA020203, + 0x81C, 0xF9040203, + 0x81C, 0xF8060203, + 0x81C, 0xF7080203, + 0x81C, 0xF60A0203, + 0x81C, 0xF50C0203, + 0x81C, 0xF40E0203, + 0x81C, 0xF3100203, + 0x81C, 0xF2120203, + 0x81C, 0xF1140203, + 0x81C, 0xF0160203, + 0x81C, 0xEF180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xE1340203, + 0x81C, 0xA5360203, + 0x81C, 0xA4380203, + 0x81C, 0xA33A0203, + 0x81C, 0xA23C0203, + 0x81C, 0x843E0203, + 0x81C, 0x83400203, + 0x81C, 0x82420203, + 0x81C, 0x81440203, + 0x81C, 0x64460203, + 0x81C, 0x63480203, + 0x81C, 0x624A0203, + 0x81C, 0x614C0203, + 0x81C, 0x474E0203, + 0x81C, 0x46500203, + 0x81C, 0x45520203, + 0x81C, 0x44540203, + 0x81C, 0x43560203, + 0x81C, 0x25580203, + 0x81C, 0x245A0203, + 0x81C, 0x235C0203, + 0x81C, 0x075E0203, + 0x81C, 0x06600203, + 0x81C, 0x05620203, + 0x81C, 0x04640203, + 0x81C, 0x03660203, + 0x81C, 0x02680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xE1360203, + 0x81C, 0xA5380203, + 0x81C, 0xA43A0203, + 0x81C, 0xA33C0203, + 0x81C, 0x853E0203, + 0x81C, 0x84400203, + 0x81C, 0x83420203, + 0x81C, 0x82440203, + 0x81C, 0x81460203, + 0x81C, 0x64480203, + 0x81C, 0x634A0203, + 0x81C, 0x624C0203, + 0x81C, 0x614E0203, + 0x81C, 0x46500203, + 0x81C, 0x45520203, + 0x81C, 0x44540203, + 0x81C, 0x43560203, + 0x81C, 0x25580203, + 0x81C, 0x245A0203, + 0x81C, 0x235C0203, + 0x81C, 0x075E0203, + 0x81C, 0x06600203, + 0x81C, 0x05620203, + 0x81C, 0x04640203, + 0x81C, 0x03660203, + 0x81C, 0x02680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000203, + 0x81C, 0xFF020203, + 0x81C, 0xFE040203, + 0x81C, 0xFD060203, + 0x81C, 0xFC080203, + 0x81C, 0xFB0A0203, + 0x81C, 0xFA0C0203, + 0x81C, 0xF90E0203, + 0x81C, 0xF8100203, + 0x81C, 0xF7120203, + 0x81C, 0xF6140203, + 0x81C, 0xF5160203, + 0x81C, 0xF4180203, + 0x81C, 0xF31A0203, + 0x81C, 0xF21C0203, + 0x81C, 0xF11E0203, + 0x81C, 0xF0200203, + 0x81C, 0xEF220203, + 0x81C, 0xEE240203, + 0x81C, 0xED260203, + 0x81C, 0xEC280203, + 0x81C, 0xEB2A0203, + 0x81C, 0xEA2C0203, + 0x81C, 0xE92E0203, + 0x81C, 0xE8300203, + 0x81C, 0xE7320203, + 0x81C, 0xE6340203, + 0x81C, 0xE5360203, + 0x81C, 0xE4380203, + 0x81C, 0xE33A0203, + 0x81C, 0xE23C0203, + 0x81C, 0xE13E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x84480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x45580203, + 0x81C, 0x445A0203, + 0x81C, 0x435C0203, + 0x81C, 0x425E0203, + 0x81C, 0x24600203, + 0x81C, 0x23620203, + 0x81C, 0x07640203, + 0x81C, 0x06660203, + 0x81C, 0x05680203, + 0x81C, 0x046A0203, + 0x81C, 0x036C0203, + 0x81C, 0x026E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000203, + 0x81C, 0xF6020203, + 0x81C, 0xF5040203, + 0x81C, 0xF4060203, + 0x81C, 0xF3080203, + 0x81C, 0xF20A0203, + 0x81C, 0xF10C0203, + 0x81C, 0xF00E0203, + 0x81C, 0xEF100203, + 0x81C, 0xEE120203, + 0x81C, 0xED140203, + 0x81C, 0xEC160203, + 0x81C, 0xEB180203, + 0x81C, 0xEA1A0203, + 0x81C, 0xE91C0203, + 0x81C, 0xE81E0203, + 0x81C, 0xE7200203, + 0x81C, 0xE6220203, + 0x81C, 0xE5240203, + 0x81C, 0xE4260203, + 0x81C, 0xE3280203, + 0x81C, 0xE22A0203, + 0x81C, 0xA62C0203, + 0x81C, 0xA52E0203, + 0x81C, 0xA4300203, + 0x81C, 0xA3320203, + 0x81C, 0xA2340203, + 0x81C, 0xA1360203, + 0x81C, 0x86380203, + 0x81C, 0x853A0203, + 0x81C, 0x843C0203, + 0x81C, 0x833E0203, + 0x81C, 0x65400203, + 0x81C, 0x64420203, + 0x81C, 0x63440203, + 0x81C, 0x46460203, + 0x81C, 0x45480203, + 0x81C, 0x444A0203, + 0x81C, 0x434C0203, + 0x81C, 0x264E0203, + 0x81C, 0x25500203, + 0x81C, 0x24520203, + 0x81C, 0x08540203, + 0x81C, 0x07560203, + 0x81C, 0x06580203, + 0x81C, 0x055A0203, + 0x81C, 0x045C0203, + 0x81C, 0x035E0203, + 0x81C, 0x02600203, + 0x81C, 0x01620203, + 0x81C, 0x01640203, + 0x81C, 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0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x84480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x45580203, + 0x81C, 0x445A0203, + 0x81C, 0x435C0203, + 0x81C, 0x425E0203, + 0x81C, 0x24600203, + 0x81C, 0x23620203, + 0x81C, 0x07640203, + 0x81C, 0x06660203, + 0x81C, 0x05680203, + 0x81C, 0x046A0203, + 0x81C, 0x036C0203, + 0x81C, 0x026E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000203, + 0x81C, 0xFF020203, + 0x81C, 0xFE040203, + 0x81C, 0xFD060203, + 0x81C, 0xFC080203, + 0x81C, 0xFB0A0203, + 0x81C, 0xFA0C0203, + 0x81C, 0xF90E0203, + 0x81C, 0xF8100203, + 0x81C, 0xF7120203, + 0x81C, 0xF6140203, + 0x81C, 0xF5160203, + 0x81C, 0xF4180203, + 0x81C, 0xF31A0203, + 0x81C, 0xF21C0203, + 0x81C, 0xF11E0203, + 0x81C, 0xF0200203, + 0x81C, 0xEF220203, + 0x81C, 0xEE240203, + 0x81C, 0xED260203, + 0x81C, 0xEC280203, + 0x81C, 0xEB2A0203, + 0x81C, 0xEA2C0203, + 0x81C, 0xE92E0203, + 0x81C, 0xE8300203, + 0x81C, 0xE7320203, + 0x81C, 0xE6340203, + 0x81C, 0xE5360203, + 0x81C, 0xE4380203, + 0x81C, 0xE33A0203, + 0x81C, 0xE23C0203, + 0x81C, 0xE13E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x85480203, + 0x81C, 0x844A0203, + 0x81C, 0x834C0203, + 0x81C, 0x824E0203, + 0x81C, 0x81500203, + 0x81C, 0x64520203, + 0x81C, 0x63540203, + 0x81C, 0x62560203, + 0x81C, 0x61580203, + 0x81C, 0x445A0203, + 0x81C, 0x435C0203, + 0x81C, 0x425E0203, + 0x81C, 0x25600203, + 0x81C, 0x24620203, + 0x81C, 0x06640203, + 0x81C, 0x05660203, + 0x81C, 0x04680203, + 0x81C, 0x036A0203, + 0x81C, 0x026C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000303, + 0x81C, 0xF7020303, + 0x81C, 0xF6040303, + 0x81C, 0xF5060303, + 0x81C, 0xF4080303, + 0x81C, 0xF30A0303, + 0x81C, 0xF20C0303, + 0x81C, 0xF10E0303, + 0x81C, 0xF0100303, + 0x81C, 0xEF120303, + 0x81C, 0xEE140303, + 0x81C, 0xED160303, + 0x81C, 0xEC180303, + 0x81C, 0xEB1A0303, + 0x81C, 0xEA1C0303, + 0x81C, 0xE91E0303, + 0x81C, 0xE8200303, + 0x81C, 0xE7220303, + 0x81C, 0xE6240303, + 0x81C, 0xE5260303, + 0x81C, 0xE4280303, + 0x81C, 0xE32A0303, + 0x81C, 0xE22C0303, + 0x81C, 0xE12E0303, + 0x81C, 0xA6300303, + 0x81C, 0xA5320303, + 0x81C, 0xA4340303, + 0x81C, 0xA3360303, + 0x81C, 0xA2380303, + 0x81C, 0xA13A0303, + 0x81C, 0x843C0303, + 0x81C, 0x833E0303, + 0x81C, 0x82400303, + 0x81C, 0x81420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x454C0303, + 0x81C, 0x444E0303, + 0x81C, 0x43500303, + 0x81C, 0x42520303, + 0x81C, 0x41540303, + 0x81C, 0x24560303, + 0x81C, 0x23580303, + 0x81C, 0x065A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xE81E0303, + 0x81C, 0xE7200303, + 0x81C, 0xE6220303, + 0x81C, 0xE5240303, + 0x81C, 0xE4260303, + 0x81C, 0xE3280303, + 0x81C, 0xC32A0303, + 0x81C, 0xC22C0303, + 0x81C, 0xC12E0303, + 0x81C, 0xA5300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0x853A0303, + 0x81C, 0x843C0303, + 0x81C, 0x833E0303, + 0x81C, 0x82400303, + 0x81C, 0x81420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x454C0303, + 0x81C, 0x444E0303, + 0x81C, 0x43500303, + 0x81C, 0x25520303, + 0x81C, 0x24540303, + 0x81C, 0x23560303, + 0x81C, 0x06580303, + 0x81C, 0x055A0303, + 0x81C, 0x045C0303, + 0x81C, 0x035E0303, + 0x81C, 0x02600303, + 0x81C, 0x01620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000303, + 0x81C, 0xF8020303, + 0x81C, 0xF7040303, + 0x81C, 0xF6060303, + 0x81C, 0xF5080303, + 0x81C, 0xF40A0303, + 0x81C, 0xF30C0303, + 0x81C, 0xF20E0303, + 0x81C, 0xF1100303, + 0x81C, 0xF0120303, + 0x81C, 0xEF140303, + 0x81C, 0xEE160303, + 0x81C, 0xED180303, + 0x81C, 0xEC1A0303, + 0x81C, 0xEB1C0303, + 0x81C, 0xEA1E0303, + 0x81C, 0xE9200303, + 0x81C, 0xE8220303, + 0x81C, 0xE7240303, + 0x81C, 0xE6260303, + 0x81C, 0xE5280303, + 0x81C, 0xE42A0303, + 0x81C, 0xE32C0303, + 0x81C, 0xE22E0303, + 0x81C, 0xE1300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0x853A0303, + 0x81C, 0x843C0303, + 0x81C, 0x833E0303, + 0x81C, 0x82400303, + 0x81C, 0x81420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x444C0303, + 0x81C, 0x434E0303, + 0x81C, 0x42500303, + 0x81C, 0x25520303, + 0x81C, 0x24540303, + 0x81C, 0x23560303, + 0x81C, 0x07580303, + 0x81C, 0x065A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xE81E0303, + 0x81C, 0xE7200303, + 0x81C, 0xE6220303, + 0x81C, 0xE5240303, + 0x81C, 0xE4260303, + 0x81C, 0xE3280303, + 0x81C, 0xE22A0303, + 0x81C, 0xE12C0303, + 0x81C, 0xA72E0303, + 0x81C, 0xA6300303, + 0x81C, 0xA5320303, + 0x81C, 0xA4340303, + 0x81C, 0xA3360303, + 0x81C, 0xA2380303, + 0x81C, 0xA13A0303, + 0x81C, 0x843C0303, + 0x81C, 0x833E0303, + 0x81C, 0x82400303, + 0x81C, 0x81420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x454C0303, + 0x81C, 0x444E0303, + 0x81C, 0x43500303, + 0x81C, 0x42520303, + 0x81C, 0x41540303, + 0x81C, 0x24560303, + 0x81C, 0x23580303, + 0x81C, 0x065A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xC2360303, + 0x81C, 0xC1380303, + 0x81C, 0xA33A0303, + 0x81C, 0xA23C0303, + 0x81C, 0x853E0303, + 0x81C, 0x84400303, + 0x81C, 0x83420303, + 0x81C, 0x66440303, + 0x81C, 0x65460303, + 0x81C, 0x64480303, + 0x81C, 0x634A0303, + 0x81C, 0x624C0303, + 0x81C, 0x614E0303, + 0x81C, 0x45500303, + 0x81C, 0x44520303, + 0x81C, 0x43540303, + 0x81C, 0x42560303, + 0x81C, 0x25580303, + 0x81C, 0x245A0303, + 0x81C, 0x235C0303, + 0x81C, 0x065E0303, + 0x81C, 0x05600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000303, + 0x81C, 0xF8020303, + 0x81C, 0xF7040303, + 0x81C, 0xF6060303, + 0x81C, 0xF5080303, + 0x81C, 0xF40A0303, + 0x81C, 0xF30C0303, + 0x81C, 0xF20E0303, + 0x81C, 0xF1100303, + 0x81C, 0xF0120303, + 0x81C, 0xEF140303, + 0x81C, 0xEE160303, + 0x81C, 0xED180303, + 0x81C, 0xEC1A0303, + 0x81C, 0xEB1C0303, + 0x81C, 0xEA1E0303, + 0x81C, 0xE9200303, + 0x81C, 0xE8220303, + 0x81C, 0xE7240303, + 0x81C, 0xE6260303, + 0x81C, 0xE5280303, + 0x81C, 0xE42A0303, + 0x81C, 0xE32C0303, + 0x81C, 0xE22E0303, + 0x81C, 0xE1300303, + 0x81C, 0xA6320303, + 0x81C, 0xA5340303, + 0x81C, 0xA4360303, + 0x81C, 0xA3380303, + 0x81C, 0xA23A0303, + 0x81C, 0xA13C0303, + 0x81C, 0x853E0303, + 0x81C, 0x84400303, + 0x81C, 0x83420303, + 0x81C, 0x82440303, + 0x81C, 0x81460303, + 0x81C, 0x64480303, + 0x81C, 0x634A0303, + 0x81C, 0x624C0303, + 0x81C, 0x614E0303, + 0x81C, 0x44500303, + 0x81C, 0x43520303, + 0x81C, 0x42540303, + 0x81C, 0x41560303, + 0x81C, 0x25580303, + 0x81C, 0x245A0303, + 0x81C, 0x235C0303, + 0x81C, 0x055E0303, + 0x81C, 0x04600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000303, + 0x81C, 0xFD020303, + 0x81C, 0xFC040303, + 0x81C, 0xFB060303, + 0x81C, 0xFA080303, + 0x81C, 0xF90A0303, + 0x81C, 0xF80C0303, + 0x81C, 0xF70E0303, + 0x81C, 0xF6100303, + 0x81C, 0xF5120303, + 0x81C, 0xF4140303, + 0x81C, 0xF3160303, + 0x81C, 0xF2180303, + 0x81C, 0xF11A0303, + 0x81C, 0xF01C0303, + 0x81C, 0xEF1E0303, + 0x81C, 0xEE200303, + 0x81C, 0xED220303, + 0x81C, 0xEC240303, + 0x81C, 0xEB260303, + 0x81C, 0xEA280303, + 0x81C, 0xE92A0303, + 0x81C, 0xE82C0303, + 0x81C, 0xE72E0303, + 0x81C, 0xE6300303, + 0x81C, 0xE5320303, + 0x81C, 0xE4340303, + 0x81C, 0xE3360303, + 0x81C, 0xC3380303, + 0x81C, 0xC23A0303, + 0x81C, 0xC13C0303, + 0x81C, 0xA43E0303, + 0x81C, 0xA3400303, + 0x81C, 0xA2420303, + 0x81C, 0xA1440303, + 0x81C, 0x85460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x64500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x44580303, + 0x81C, 0x435A0303, + 0x81C, 0x425C0303, + 0x81C, 0x265E0303, + 0x81C, 0x25600303, + 0x81C, 0x24620303, + 0x81C, 0x06640303, + 0x81C, 0x05660303, + 0x81C, 0x04680303, + 0x81C, 0x036A0303, + 0x81C, 0x026C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xE81E0303, + 0x81C, 0xE7200303, + 0x81C, 0xE6220303, + 0x81C, 0xE5240303, + 0x81C, 0xE4260303, + 0x81C, 0xE3280303, + 0x81C, 0xE22A0303, + 0x81C, 0xA62C0303, + 0x81C, 0xA52E0303, + 0x81C, 0xA4300303, + 0x81C, 0xA3320303, + 0x81C, 0xA2340303, + 0x81C, 0x87360303, + 0x81C, 0x86380303, + 0x81C, 0x853A0303, + 0x81C, 0x843C0303, + 0x81C, 0x833E0303, + 0x81C, 0x66400303, + 0x81C, 0x65420303, + 0x81C, 0x64440303, + 0x81C, 0x45460303, + 0x81C, 0x44480303, + 0x81C, 0x434A0303, + 0x81C, 0x274C0303, + 0x81C, 0x264E0303, + 0x81C, 0x25500303, + 0x81C, 0x24520303, + 0x81C, 0x23540303, + 0x81C, 0x08560303, + 0x81C, 0x07580303, + 0x81C, 0x065A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000303, + 0x81C, 0xFD020303, + 0x81C, 0xFC040303, + 0x81C, 0xFB060303, + 0x81C, 0xFA080303, + 0x81C, 0xF90A0303, + 0x81C, 0xF80C0303, + 0x81C, 0xF70E0303, + 0x81C, 0xF6100303, + 0x81C, 0xF5120303, + 0x81C, 0xF4140303, + 0x81C, 0xF3160303, + 0x81C, 0xF2180303, + 0x81C, 0xF11A0303, + 0x81C, 0xF01C0303, + 0x81C, 0xEF1E0303, + 0x81C, 0xEE200303, + 0x81C, 0xED220303, + 0x81C, 0xEC240303, + 0x81C, 0xEB260303, + 0x81C, 0xEA280303, + 0x81C, 0xE92A0303, + 0x81C, 0xE82C0303, + 0x81C, 0xE72E0303, + 0x81C, 0xE6300303, + 0x81C, 0xE5320303, + 0x81C, 0xE4340303, + 0x81C, 0xE3360303, + 0x81C, 0xC3380303, + 0x81C, 0xC23A0303, + 0x81C, 0xC13C0303, + 0x81C, 0xA43E0303, + 0x81C, 0xA3400303, + 0x81C, 0xA2420303, + 0x81C, 0xA1440303, + 0x81C, 0x85460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x64500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x44580303, + 0x81C, 0x435A0303, + 0x81C, 0x425C0303, + 0x81C, 0x265E0303, + 0x81C, 0x25600303, + 0x81C, 0x24620303, + 0x81C, 0x06640303, + 0x81C, 0x05660303, + 0x81C, 0x04680303, + 0x81C, 0x036A0303, + 0x81C, 0x026C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000303, + 0x81C, 0xFC020303, + 0x81C, 0xFB040303, + 0x81C, 0xFA060303, + 0x81C, 0xF9080303, + 0x81C, 0xF80A0303, + 0x81C, 0xF70C0303, + 0x81C, 0xF60E0303, + 0x81C, 0xF5100303, + 0x81C, 0xF4120303, + 0x81C, 0xF3140303, + 0x81C, 0xF2160303, + 0x81C, 0xF1180303, + 0x81C, 0xF01A0303, + 0x81C, 0xEF1C0303, + 0x81C, 0xEE1E0303, + 0x81C, 0xED200303, + 0x81C, 0xEC220303, + 0x81C, 0xEB240303, + 0x81C, 0xEA260303, + 0x81C, 0xE9280303, + 0x81C, 0xE82A0303, + 0x81C, 0xE72C0303, + 0x81C, 0xE62E0303, + 0x81C, 0xE5300303, + 0x81C, 0xE4320303, + 0x81C, 0xE3340303, + 0x81C, 0xE2360303, + 0x81C, 0xE1380303, + 0x81C, 0xA53A0303, + 0x81C, 0xA43C0303, + 0x81C, 0xA33E0303, + 0x81C, 0xA2400303, + 0x81C, 0xA1420303, + 0x81C, 0x87440303, + 0x81C, 0x86460303, + 0x81C, 0x85480303, + 0x81C, 0x844A0303, + 0x81C, 0x834C0303, + 0x81C, 0x824E0303, + 0x81C, 0x81500303, + 0x81C, 0x64520303, + 0x81C, 0x63540303, + 0x81C, 0x62560303, + 0x81C, 0x61580303, + 0x81C, 0x435A0303, + 0x81C, 0x425C0303, + 0x81C, 0x415E0303, + 0x81C, 0x07600303, + 0x81C, 0x06620303, + 0x81C, 0x05640303, + 0x81C, 0x04660303, + 0x81C, 0x03680303, + 0x81C, 0x026A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0xB0000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x1850, 0x00000022, + 0x1850, 0x00000020, + 0x1A50, 0x00000022, + 0x1A50, 0x00000020, + +}; + +void +ODM_ReadAndConfig_MP_8814A_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8814A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_AGC_TAB(void) +{ + return 107; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG[] = { + 0x800, 0x9020D010, + 0x804, 0x08011280, + 0x808, 0x0E0282FF, + 0x80C, 0x1000002F, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x810, 0x33303265, + 0xA0000000, 0x00000000, + 0x810, 0x33303265, + 0xB0000000, 0x00000000, + 0x814, 0x020C3D10, + 0x818, 0x04A10385, + 0x820, 0x00000000, + 0x824, 0x00033E40, + 0x828, 0x00000000, + 0x82C, 0x73985170, + 0x830, 0x79A0EA08, + 0x834, 0x042E708A, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x838, 0x86667640, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x838, 0x86667641, + 0xA0000000, 0x00000000, + 0x838, 0x86667640, + 0xB0000000, 0x00000000, + 0x83C, 0x9798B9B9, + 0x840, 0x17578F60, + 0x844, 0x4BBDFCDE, + 0x848, 0x5CD07F8B, + 0x84C, 0x6CFBF7B5, + 0x850, 0x28834706, + 0x854, 0x0001520C, + 0x858, 0x4060C000, + 0x85C, 0x74210368, + 0x860, 0x6929C321, + 0x864, 0x79727432, + 0x868, 0x8CA7A314, + 0x86C, 0x438C2878, + 0x870, 0x44444444, + 0x874, 0x21612C2E, + 0x878, 0x00003152, + 0x87C, 0x000FC000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0xA202033E, + 0x8AC, 0xF40F550A, + 0x8B0, 0x00000600, + 0x8B4, 0x000FC080, + 0x8B8, 0xEC0057FF, + 0x8BC, 0x8CA520C3, + 0x8C0, 0x3FF00020, + 0x8C4, 0x44C00000, + 0x80000009, 0x00000000, 0x40000000, 0x00000000, + 0x8C8, 0x80025969, + 0xA0000000, 0x00000000, + 0x8C8, 0x80025167, + 0xB0000000, 0x00000000, + 0x8CC, 0x08250492, + 0x8D0, 0x0000B800, + 0x8D4, 0x940008A0, + 0x8D8, 0x290B5612, + 0x8DC, 0x00000000, + 0x8E0, 0x32316407, + 0x8E4, 0x4A092925, + 0x8E8, 0xFFFFC42C, + 0x8EC, 0x99999999, + 0x8F0, 0x00009999, + 0x8F4, 0x00F80FA1, + 0x8F8, 0x400082C0, + 0x8FC, 0x00000000, + 0x900, 0x00400700, + 0x90C, 0x09004000, + 0x910, 0x0000FC00, + 0x914, 0xD6400404, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x055AA500, + 0x928, 0x4AB0E4E4, + 0x92C, 0xFFFE0000, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x938, 0x00008400, + 0x93C, 0x932C0642, + 0x940, 0x093E9360, + 0x944, 0x08000000, + 0x948, 0x04000000, + 0x950, 0x02010080, + 0x954, 0x86510080, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x801FFFFF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x98C, 0x03440000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x00080080, + 0x9A8, 0x0C2F0000, + 0x9AC, 0x00560000, + 0x9B0, 0x81081008, + 0x9B4, 0x00000000, + 0x9B8, 0x01081008, + 0x9BC, 0x01081008, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E4, 0x00000002, + 0x9E8, 0x000022D5, + 0x9FC, 0xEFFFF7FF, + 0xB00, 0xE3100000, + 0xB04, 0x0000B000, + 0xB0C, 0x31EAA006, + 0xB5C, 0x41CFFFFF, + 0xC00, 0x00000007, + 0xC04, 0x00042020, + 0xC08, 0x80410231, + 0xC0C, 0x00000000, + 0xC10, 0x00000100, + 0xC14, 0x01000000, + 0xC1C, 0x40000053, + 0xC50, 0x00000020, + 0xC54, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x3C0A0C14, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x3C0A0C14, + 0xA0000000, 0x00000000, + 0xC58, 0x3C020C14, + 0xB0000000, 0x00000000, + 0xC5C, 0x0D000058, + 0xC60, 0x1B800000, + 0xC60, 0x0B800001, + 0xC60, 0x05800002, + 0xC60, 0x07800003, + 0xC60, 0x1A800004, + 0xC60, 0x0B800005, + 0xC60, 0x05800006, + 0xC60, 0x0E800007, + 0xC60, 0x1A800008, + 0xC60, 0x0B800009, + 0xC60, 0x1580000A, + 0xC60, 0x0880000B, + 0xC60, 0x1A80000C, + 0xC60, 0x0B80000D, + 0xC60, 0x0580000E, + 0xC60, 0x0E80000F, + 0xC60, 0x1A800010, + 0xC60, 0x0B800011, + 0xC60, 0x15800012, + 0xC60, 0x08800013, + 0xC60, 0x1A800014, + 0xC60, 0x0B800015, + 0xC60, 0x05800016, + 0xC60, 0x07800017, + 0xC60, 0x1A800018, + 0xC60, 0x0B800019, + 0xC60, 0x1580001A, + 0xC60, 0x0880001B, + 0xC60, 0x1B80001C, + 0xC60, 0x0B80001D, + 0xC60, 0x0580001E, + 0xC60, 0x0780001F, + 0xC60, 0x1B800020, + 0xC60, 0x0B800021, + 0xC60, 0x05800022, + 0xC60, 0x07800023, + 0xC60, 0x1B800024, + 0xC60, 0x0B800025, + 0xC60, 0x05800026, + 0xC60, 0x07800027, + 0xC60, 0x1B800028, + 0xC60, 0x0B800029, + 0xC60, 0x0580002A, + 0xC60, 0x0780002B, + 0xC60, 0x1B800030, + 0xC60, 0x0B800031, + 0xC60, 0x05800032, + 0xC60, 0x00800033, + 0xC60, 0x1B800034, + 0xC60, 0x0B800035, + 0xC60, 0x05800036, + 0xC60, 0x00800037, + 0xC60, 0x1B800038, + 0xC60, 0x0B800039, + 0xC60, 0x0580003A, + 0xC60, 0x0E80803B, + 0xC94, 0x01000401, + 0xC98, 0x00188000, + 0xCA0, 0x00002929, + 0xCA4, 0x08040201, + 0xCA8, 0x80402010, + 0xCAC, 0x77777000, + 0xCB0, 0x54775477, + 0xCB4, 0x54775477, + 0xCB8, 0x00500000, + 0xCBC, 0x77700000, + 0xCC0, 0x00000010, + 0xCC8, 0x00000010, + 0xE00, 0x00000007, + 0xE04, 0x00042020, + 0xE08, 0x80410231, + 0xE0C, 0x00000000, + 0xE10, 0x00000100, + 0xE14, 0x01000000, + 0xE1C, 0x40000053, + 0xE50, 0x00000020, + 0xE54, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0xE58, 0x3C0A0C14, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0xE58, 0x3C0A0C14, + 0xA0000000, 0x00000000, + 0xE58, 0x3C020C14, + 0xB0000000, 0x00000000, + 0xE5C, 0x0D000058, + 0xE60, 0x1B800000, + 0xE60, 0x0B800001, + 0xE60, 0x05800002, + 0xE60, 0x07800003, + 0xE60, 0x1A800004, + 0xE60, 0x0B800005, + 0xE60, 0x05800006, + 0xE60, 0x0E800007, + 0xE60, 0x1A800008, + 0xE60, 0x0B800009, + 0xE60, 0x1580000A, + 0xE60, 0x0880000B, + 0xE60, 0x1A80000C, + 0xE60, 0x0B80000D, + 0xE60, 0x0580000E, + 0xE60, 0x0E80000F, + 0xE60, 0x1A800010, + 0xE60, 0x0B800011, + 0xE60, 0x15800012, + 0xE60, 0x08800013, + 0xE60, 0x1A800014, + 0xE60, 0x0B800015, + 0xE60, 0x05800016, + 0xE60, 0x07800017, + 0xE60, 0x1A800018, + 0xE60, 0x0B800019, + 0xE60, 0x1580001A, + 0xE60, 0x0880001B, + 0xE60, 0x1B80001C, + 0xE60, 0x0B80001D, + 0xE60, 0x0580001E, + 0xE60, 0x0780001F, + 0xE60, 0x1B800020, + 0xE60, 0x0B800021, + 0xE60, 0x05800022, + 0xE60, 0x07800023, + 0xE60, 0x1B800024, + 0xE60, 0x0B800025, + 0xE60, 0x05800026, + 0xE60, 0x07800027, + 0xE60, 0x1B800028, + 0xE60, 0x0B800029, + 0xE60, 0x0580002A, + 0xE60, 0x0780002B, + 0xE60, 0x1B800030, + 0xE60, 0x0B800031, + 0xE60, 0x05800032, + 0xE60, 0x00800033, + 0xE60, 0x1B800034, + 0xE60, 0x0B800035, + 0xE60, 0x05800036, + 0xE60, 0x00800037, + 0xE60, 0x1B800038, + 0xE60, 0x0B800039, + 0xE60, 0x0580003A, + 0xE60, 0x0E80803B, + 0xE94, 0x01000401, + 0xE98, 0x00188000, + 0xEA0, 0x00002929, + 0xEA4, 0x08040201, + 0xEA8, 0x80402010, + 0xEAC, 0x77777000, + 0xEB0, 0x54775477, + 0xEB4, 0x54775477, + 0xEB8, 0x00500000, + 0xEBC, 0x77700000, + 0x1800, 0x00000007, + 0x1804, 0x00042020, + 0x1808, 0x80410231, + 0x180C, 0x00000000, + 0x1810, 0x00000100, + 0x1814, 0x01000000, + 0x181C, 0x40000053, + 0x1850, 0x00000020, + 0x1854, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x1858, 0x3C0A0C14, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1858, 0x3C0A0C14, + 0xA0000000, 0x00000000, + 0x1858, 0x3C020C14, + 0xB0000000, 0x00000000, + 0x185C, 0x0D000058, + 0x1860, 0x1B800000, + 0x1860, 0x0B800001, + 0x1860, 0x05800002, + 0x1860, 0x07800003, + 0x1860, 0x1A800004, + 0x1860, 0x0B800005, + 0x1860, 0x05800006, + 0x1860, 0x0E800007, + 0x1860, 0x1A800008, + 0x1860, 0x0B800009, + 0x1860, 0x1580000A, + 0x1860, 0x0880000B, + 0x1860, 0x1A80000C, + 0x1860, 0x0B80000D, + 0x1860, 0x0580000E, + 0x1860, 0x0E80000F, + 0x1860, 0x1A800010, + 0x1860, 0x0B800011, + 0x1860, 0x15800012, + 0x1860, 0x08800013, + 0x1860, 0x1A800014, + 0x1860, 0x0B800015, + 0x1860, 0x05800016, + 0x1860, 0x07800017, + 0x1860, 0x1A800018, + 0x1860, 0x0B800019, + 0x1860, 0x1580001A, + 0x1860, 0x0880001B, + 0x1860, 0x1B80001C, + 0x1860, 0x0B80001D, + 0x1860, 0x0580001E, + 0x1860, 0x0780001F, + 0x1860, 0x1B800020, + 0x1860, 0x0B800021, + 0x1860, 0x05800022, + 0x1860, 0x07800023, + 0x1860, 0x1B800024, + 0x1860, 0x0B800025, + 0x1860, 0x05800026, + 0x1860, 0x07800027, + 0x1860, 0x1B800028, + 0x1860, 0x0B800029, + 0x1860, 0x0580002A, + 0x1860, 0x0780002B, + 0x1860, 0x1B800030, + 0x1860, 0x0B800031, + 0x1860, 0x05800032, + 0x1860, 0x00800033, + 0x1860, 0x1B800034, + 0x1860, 0x0B800035, + 0x1860, 0x05800036, + 0x1860, 0x00800037, + 0x1860, 0x1B800038, + 0x1860, 0x0B800039, + 0x1860, 0x0580003A, + 0x1860, 0x0E80803B, + 0x1894, 0x01000401, + 0x1898, 0x00188000, + 0x18A0, 0x00002929, + 0x18A4, 0x08040201, + 0x18A8, 0x80402010, + 0x18AC, 0x77777000, + 0x18B0, 0x54775477, + 0x18B4, 0x54775477, + 0x18B8, 0x00500000, + 0x18BC, 0x77700000, + 0x1A00, 0x00000007, + 0x1A04, 0x00042020, + 0x1A08, 0x80410231, + 0x1A0C, 0x00000000, + 0x1A10, 0x00000100, + 0x1A14, 0x01000000, + 0x1A1C, 0x40000053, + 0x1A50, 0x00000020, + 0x1A54, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x1A58, 0x3C0A0C14, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1A58, 0x3C0A0C14, + 0xA0000000, 0x00000000, + 0x1A58, 0x3C020C14, + 0xB0000000, 0x00000000, + 0x1A5C, 0x0D000058, + 0x1A60, 0x1B800000, + 0x1A60, 0x0B800001, + 0x1A60, 0x05800002, + 0x1A60, 0x07800003, + 0x1A60, 0x1A800004, + 0x1A60, 0x0B800005, + 0x1A60, 0x05800006, + 0x1A60, 0x0E800007, + 0x1A60, 0x1A800008, + 0x1A60, 0x0B800009, + 0x1A60, 0x1580000A, + 0x1A60, 0x0880000B, + 0x1A60, 0x1A80000C, + 0x1A60, 0x0B80000D, + 0x1A60, 0x0580000E, + 0x1A60, 0x0E80000F, + 0x1A60, 0x1A800010, + 0x1A60, 0x0B800011, + 0x1A60, 0x15800012, + 0x1A60, 0x08800013, + 0x1A60, 0x1A800014, + 0x1A60, 0x0B800015, + 0x1A60, 0x05800016, + 0x1A60, 0x07800017, + 0x1A60, 0x1A800018, + 0x1A60, 0x0B800019, + 0x1A60, 0x1580001A, + 0x1A60, 0x0880001B, + 0x1A60, 0x1B80001C, + 0x1A60, 0x0B80001D, + 0x1A60, 0x0580001E, + 0x1A60, 0x0780001F, + 0x1A60, 0x1B800020, + 0x1A60, 0x0B800021, + 0x1A60, 0x05800022, + 0x1A60, 0x07800023, + 0x1A60, 0x1B800024, + 0x1A60, 0x0B800025, + 0x1A60, 0x05800026, + 0x1A60, 0x07800027, + 0x1A60, 0x1B800028, + 0x1A60, 0x0B800029, + 0x1A60, 0x0580002A, + 0x1A60, 0x0780002B, + 0x1A60, 0x1B800030, + 0x1A60, 0x0B800031, + 0x1A60, 0x05800032, + 0x1A60, 0x00800033, + 0x1A60, 0x1B800034, + 0x1A60, 0x0B800035, + 0x1A60, 0x05800036, + 0x1A60, 0x00800037, + 0x1A60, 0x1B800038, + 0x1A60, 0x0B800039, + 0x1A60, 0x0580003A, + 0x1A60, 0x0E80803B, + 0x1A94, 0x01000401, + 0x1A98, 0x00188000, + 0x1AA0, 0x00002929, + 0x1AA4, 0x08040201, + 0x1AA8, 0x80402010, + 0x1AAC, 0x77777000, + 0x1AB0, 0x54775477, + 0x1AB4, 0x54775477, + 0x1AB8, 0x00500000, + 0x1ABC, 0x77700000, + 0x1904, 0x00030000, + 0x1914, 0x00030000, + 0x1984, 0x03000000, + 0x1988, 0x00000087, + 0x198C, 0x00000007, + 0x1990, 0xFFAA5500, + 0x1994, 0x00000077, + 0x1998, 0x12801000, + 0x1998, 0x12801000, + 0x1998, 0x12801001, + 0x1998, 0x12801002, + 0x1998, 0x12801003, + 0x1998, 0x12801004, + 0x1998, 0x12801005, + 0x1998, 0x12801006, + 0x1998, 0x12801007, + 0x1998, 0x12801008, + 0x1998, 0x12801009, + 0x1998, 0x1280100A, + 0x1998, 0x1280100B, + 0x1998, 0x1280100C, + 0x1998, 0x1280100D, + 0x1998, 0x1280100E, + 0x1998, 0x1280100F, + 0x1998, 0x12801010, + 0x1998, 0x12801011, + 0x1998, 0x12801012, + 0x1998, 0x12801013, + 0x1998, 0x12801014, + 0x1998, 0x12801015, + 0x1998, 0x12801016, + 0x1998, 0x12801017, + 0x1998, 0x12801018, + 0x1998, 0x12801019, + 0x1998, 0x1280101A, + 0x1998, 0x1280101B, + 0x1998, 0x1280101C, + 0x1998, 0x1280101D, + 0x1998, 0x1280101E, + 0x1998, 0x1280101F, + 0x1998, 0x12801020, + 0x1998, 0x12801021, + 0x1998, 0x12801022, + 0x1998, 0x12801023, + 0x1998, 0x1280102C, + 0x1998, 0x1280102D, + 0x1998, 0x1280102E, + 0x1998, 0x1280102F, + 0x1998, 0x12801030, + 0x1998, 0x12801031, + 0x1998, 0x12801032, + 0x1998, 0x12801033, + 0x1998, 0x12801034, + 0x1998, 0x12801035, + 0x1998, 0x12801036, + 0x1998, 0x12801037, + 0x1998, 0x12801038, + 0x1998, 0x12801039, + 0x1998, 0x1280103A, + 0x1998, 0x1280103B, + 0x1998, 0x1280103C, + 0x1998, 0x1280103D, + 0x1998, 0x1280103E, + 0x1998, 0x1280103F, + 0x1998, 0x12801040, + 0x1998, 0x12801041, + 0x1998, 0x12801042, + 0x1998, 0x12801043, + 0x1998, 0x12801044, + 0x1998, 0x12801045, + 0x1998, 0x12801046, + 0x1998, 0x12801047, + 0x1998, 0x12801048, + 0x1998, 0x12801049, + 0x1998, 0x12801100, + 0x1998, 0x12801101, + 0x1998, 0x12801102, + 0x1998, 0x12801103, + 0x1998, 0x12801104, + 0x1998, 0x12801105, + 0x1998, 0x12801106, + 0x1998, 0x12801107, + 0x1998, 0x12801108, + 0x1998, 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0x4D001D35, + 0x1B80, 0x4D001D37, + 0x1B80, 0x00011D45, + 0x1B80, 0x00011D47, + 0x1B80, 0x00041D55, + 0x1B80, 0x00041D57, + 0x1B80, 0x6B401D65, + 0x1B80, 0x6B401D67, + 0x1B80, 0x4D041D75, + 0x1B80, 0x4D041D77, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x68241D85, + 0x1B80, 0x68241D87, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x68241D85, + 0x1B80, 0x68241D87, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x68241D85, + 0x1B80, 0x68241D87, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x68241D85, + 0x1B80, 0x68241D87, + 0xA0000000, 0x00000000, + 0x1B80, 0x68481D85, + 0x1B80, 0x68481D87, + 0xB0000000, 0x00000000, + 0x1B80, 0x66061D95, + 0x1B80, 0x66061D97, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65081DA5, + 0x1B80, 0x65081DA7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65181DA5, + 0x1B80, 0x65181DA7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65181DA5, + 0x1B80, 0x65181DA7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65181DA5, + 0x1B80, 0x65181DA7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65181DA5, + 0x1B80, 0x65181DA7, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x65081DA5, + 0x1B80, 0x65081DA7, + 0xA0000000, 0x00000000, + 0x1B80, 0x65081DA5, + 0x1B80, 0x65081DA7, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x64481DB5, + 0x1B80, 0x64481DB7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x64481DB5, + 0x1B80, 0x64481DB7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x64481DB5, + 0x1B80, 0x64481DB7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x64481DB5, + 0x1B80, 0x64481DB7, + 0xA0000000, 0x00000000, + 0x1B80, 0x64471DB5, + 0x1B80, 0x64471DB7, + 0xB0000000, 0x00000000, + 0x1B80, 0x23411DC5, + 0x1B80, 0x23411DC7, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E41DD5, + 0x1B80, 0x11E41DD7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E81DD5, + 0x1B80, 0x11E81DD7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E81DD5, + 0x1B80, 0x11E81DD7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E81DD5, + 0x1B80, 0x11E81DD7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E81DD5, + 0x1B80, 0x11E81DD7, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x11E41DD5, + 0x1B80, 0x11E41DD7, + 0xA0000000, 0x00000000, + 0x1B80, 0x11E41DD5, + 0x1B80, 0x11E41DD7, + 0xB0000000, 0x00000000, + 0x1B80, 0x60011DE5, + 0x1B80, 0x60011DE7, + 0x1B80, 0x23411DF5, + 0x1B80, 0x23411DF7, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x60E11E05, + 0x1B80, 0x60E11E07, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x61E11E05, + 0x1B80, 0x61E11E07, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x61E11E05, + 0x1B80, 0x61E11E07, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x61E11E05, + 0x1B80, 0x61E11E07, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x61E11E05, + 0x1B80, 0x61E11E07, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x1B80, 0x60E11E05, + 0x1B80, 0x60E11E07, + 0xA0000000, 0x00000000, + 0x1B80, 0x60E11E05, + 0x1B80, 0x60E11E07, + 0xB0000000, 0x00000000, + 0x1B80, 0x23411E15, + 0x1B80, 0x23411E17, + 0x1B80, 0x70611E25, + 0x1B80, 0x70611E27, + 0x1B80, 0x4D001E35, + 0x1B80, 0x4D001E37, + 0x1B80, 0x00011E45, + 0x1B80, 0x00011E47, + 0x1B80, 0x00001E55, + 0x1B80, 0x00001E57, + 0x1B80, 0x00001E65, + 0x1B80, 0x00001E67, + 0x1B80, 0x00001E75, + 0x1B80, 0x00001E77, + 0x1B80, 0x00001E85, + 0x1B80, 0x00001E87, + 0x1B80, 0x00001E95, + 0x1B80, 0x00001E97, + 0x1B80, 0x00001EA5, + 0x1B80, 0x00001EA7, + 0x1B80, 0x00001EB5, + 0x1B80, 0x00001EB7, + 0x1B80, 0x00001EC5, + 0x1B80, 0x00001EC7, + 0x1B80, 0x00001ED5, + 0x1B80, 0x00001ED7, + 0x1B80, 0x00001EE5, + 0x1B80, 0x00001EE7, + 0x1B80, 0x00001EF5, + 0x1B80, 0x00001EF7, + 0x1B80, 0x00001F05, + 0x1B80, 0x00001F07, + 0x1B80, 0x00001F15, + 0x1B80, 0x00001F17, + 0x1B80, 0x00001F25, + 0x1B80, 0x00001F27, + 0x1B80, 0x00001F35, + 0x1B80, 0x00001F37, + 0x1B80, 0x00001F45, + 0x1B80, 0x00001F47, + 0x1B80, 0x00001F55, + 0x1B80, 0x00001F57, + 0x1B80, 0x00001F65, + 0x1B80, 0x00001F67, + 0x1B80, 0x00001F75, + 0x1B80, 0x00001F77, + 0x1B80, 0x00001F85, + 0x1B80, 0x00001F87, + 0x1B80, 0x00001F95, + 0x1B80, 0x00001F97, + 0x1B80, 0x00001FA5, + 0x1B80, 0x00001FA7, + 0x1B80, 0x00001FB5, + 0x1B80, 0x00001FB7, + 0x1B80, 0x00001FC5, + 0x1B80, 0x00001FC7, + 0x1B80, 0x00001FD5, + 0x1B80, 0x00001FD7, + 0x1B80, 0x00001FE5, + 0x1B80, 0x00001FE7, + 0x1B80, 0x00001FF5, + 0x1B80, 0x00001FF7, + 0x1B80, 0x00000006, + 0x1B80, 0x00000002, + +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8814A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_PHY_REG(void) +{ + return 107; +} + +/****************************************************************************** +* PHY_REG_MP.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_MP[] = { + 0x8FC, 0x00000000, + 0x838, 0x86667641, + +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_MP( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_MP)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_MP; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_MP\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8814A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_PHY_REG_MP(void) +{ + return 107; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type0.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type0[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, + 0, 2, 0, 0x00001820, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001824, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001828, 0xffffffff, 0x28303232, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001830, 0xffffffff, 0x26283032, + 0, 2, 1, 0x00001834, 0xffffffff, 0x30303030, + 0, 2, 1, 0x00001838, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001840, 0xffffffff, 0x26283032, + 0, 2, 0, 0x00001844, 0xffffffff, 0x30302224, + 0, 2, 1, 0x00001848, 0xffffffff, 0x28303030, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, + 1, 2, 0, 0x00001824, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001828, 0xffffffff, 0x28303232, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001830, 0xffffffff, 0x26283032, + 1, 2, 1, 0x00001834, 0xffffffff, 0x30303030, + 1, 2, 1, 0x00001838, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001840, 0xffffffff, 0x26283032, + 1, 2, 0, 0x00001844, 0xffffffff, 0x30302224, + 1, 2, 1, 0x00001848, 0xffffffff, 0x28303030, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type0)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type0; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type1.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type1[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type1)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type1; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type2.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type2[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 0, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 0, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32323232, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32323232, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 1, 2, 1, 0x00001834, 0xffffffff, 0x32323232, + 1, 2, 1, 0x00001838, 0xffffffff, 0x26283032, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x24262830, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 1, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 1, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x32323232, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x26283032, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x24262830, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type2)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type2; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type3.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type3[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x42444646, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x42444646, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x46463840, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x46464646, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x38404244, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x42444646, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x38383840, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x48484848, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x42444646, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x42444646, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x46463840, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x46464646, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x38404244, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x42444646, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x38383840, + 0, 2, 0, 0x00001820, 0xffffffff, 0x48484848, + 0, 2, 0, 0x00001824, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001828, 0xffffffff, 0x44464646, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001830, 0xffffffff, 0x42444646, + 0, 2, 1, 0x00001834, 0xffffffff, 0x46464646, + 0, 2, 1, 0x00001838, 0xffffffff, 0x42444646, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x42444646, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001840, 0xffffffff, 0x42444646, + 0, 2, 0, 0x00001844, 0xffffffff, 0x46463840, + 0, 2, 1, 0x00001848, 0xffffffff, 0x46464646, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x38404244, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x42444646, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x38383840, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x48484848, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x42444646, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x42444646, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x46463840, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x46464646, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x38404244, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x42444646, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x38383840, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x42444646, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x42444646, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x46463840, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x46464646, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x38404244, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x42444646, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x38383840, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x42444646, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x42444646, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x46463840, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x46464646, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x38404244, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x42444646, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x38383840, + 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001828, 0xffffffff, 0x44464646, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001830, 0xffffffff, 0x42444646, + 1, 2, 1, 0x00001834, 0xffffffff, 0x46464646, + 1, 2, 1, 0x00001838, 0xffffffff, 0x42444646, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x42444646, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001840, 0xffffffff, 0x42444646, + 1, 2, 0, 0x00001844, 0xffffffff, 0x46463840, + 1, 2, 1, 0x00001848, 0xffffffff, 0x46464646, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x38404244, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x42444646, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x38383840, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x42444646, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x42444646, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x46463840, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x46464646, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x38404244, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x42444646, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x38383840 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type3)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type3; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type4.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type4[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x42424242, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424242, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x42424242, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x42424242, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x34363840, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x42424242, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x42423032, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x38404242, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x30323436, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x34363840, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x30303032, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x42424242, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424242, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x42424242, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x42424242, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x34363840, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x42424242, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x42423032, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x38404242, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x30323436, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x34363840, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x30303032, + 0, 2, 0, 0x00001820, 0xffffffff, 0x42424242, + 0, 2, 0, 0x00001824, 0xffffffff, 0x42424242, + 0, 2, 0, 0x00001828, 0xffffffff, 0x36384042, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x42424242, + 0, 2, 0, 0x00001830, 0xffffffff, 0x34363840, + 0, 2, 1, 0x00001834, 0xffffffff, 0x42424242, + 0, 2, 1, 0x00001838, 0xffffffff, 0x34363840, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x42424242, + 0, 2, 0, 0x00001840, 0xffffffff, 0x34363840, + 0, 2, 0, 0x00001844, 0xffffffff, 0x42423032, + 0, 2, 1, 0x00001848, 0xffffffff, 0x38404242, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x30323436, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x34363840, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x30303032, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x42424242, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x42424242, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x36384042, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x42424242, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x34363840, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x42424242, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x34363840, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x42424242, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x34363840, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x42423032, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x38404242, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x30323436, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x34363840, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x30303032, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424242, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x36384042, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x42424242, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x42424242, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x34363840, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x42424242, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42423032, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x38404242, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x30323436, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x34363840, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x30303032, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424242, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x36384042, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x42424242, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x42424242, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x34363840, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x42424242, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42423032, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x38404242, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x30323436, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x34363840, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x30303032, + 1, 2, 0, 0x00001824, 0xffffffff, 0x42424242, + 1, 2, 0, 0x00001828, 0xffffffff, 0x36384042, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x42424242, + 1, 2, 0, 0x00001830, 0xffffffff, 0x34363840, + 1, 2, 1, 0x00001834, 0xffffffff, 0x42424242, + 1, 2, 1, 0x00001838, 0xffffffff, 0x34363840, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x42424242, + 1, 2, 0, 0x00001840, 0xffffffff, 0x34363840, + 1, 2, 0, 0x00001844, 0xffffffff, 0x42423032, + 1, 2, 1, 0x00001848, 0xffffffff, 0x38404242, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x30323436, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x34363840, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x30303032, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x42424242, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x36384042, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x42424242, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x34363840, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x42424242, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x34363840, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x42424242, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x34363840, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x42423032, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x38404242, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x30323436, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x34363840, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x30303032 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type4)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type4; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type5.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type5[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x40424444, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x38404242, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x44444040, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x44444444, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x38384042, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x38404242, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20203636, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x48484848, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x44444444, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x40424444, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x38404242, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x44444040, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x44444444, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x38384042, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x38404242, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20203636, + 0, 2, 0, 0x00001820, 0xffffffff, 0x48484848, + 0, 2, 0, 0x00001824, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001828, 0xffffffff, 0x44464646, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001830, 0xffffffff, 0x42444646, + 0, 2, 1, 0x00001834, 0xffffffff, 0x44444444, + 0, 2, 1, 0x00001838, 0xffffffff, 0x40424444, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x38404242, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, + 0, 2, 0, 0x00001840, 0xffffffff, 0x42444646, + 0, 2, 0, 0x00001844, 0xffffffff, 0x44444040, + 0, 2, 1, 0x00001848, 0xffffffff, 0x44444444, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x38384042, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x38404242, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20203636, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x48484848, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x44444444, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x40424444, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x38404242, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x44444040, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x44444444, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x38384042, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x38404242, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20203636, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x44464646, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x42444646, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x40424444, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x42424242, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x38404242, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x42444646, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x44443840, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x44444444, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x36384042, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x42424242, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x38404242, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20203436, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x44464646, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x42444646, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x44444444, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x40424444, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x42424242, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x38404242, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x42444646, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x44443840, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x44444444, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x36384042, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x42424242, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x38404242, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x20203436, + 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001828, 0xffffffff, 0x44464646, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001830, 0xffffffff, 0x42444646, + 1, 2, 1, 0x00001834, 0xffffffff, 0x44444444, + 1, 2, 1, 0x00001838, 0xffffffff, 0x40424444, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x42424242, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x38404242, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001840, 0xffffffff, 0x42444646, + 1, 2, 0, 0x00001844, 0xffffffff, 0x44443840, + 1, 2, 1, 0x00001848, 0xffffffff, 0x44444444, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x36384042, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x42424242, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x38404242, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x20203436, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x44464646, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x42444646, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x44444444, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x40424444, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x42424242, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x38404242, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x42444646, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x44443840, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x44444444, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x36384042, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x42424242, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x38404242, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x20203436 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type5)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type5; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type6.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type6[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, + 0, 2, 0, 0x00001820, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001824, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001828, 0xffffffff, 0x28303232, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001830, 0xffffffff, 0x26283032, + 0, 2, 1, 0x00001834, 0xffffffff, 0x30303030, + 0, 2, 1, 0x00001838, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, + 0, 2, 0, 0x00001840, 0xffffffff, 0x26283032, + 0, 2, 0, 0x00001844, 0xffffffff, 0x30302224, + 0, 2, 1, 0x00001848, 0xffffffff, 0x28303030, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x28303232, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x30303030, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x28282828, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32323232, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x30302224, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303030, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x28282828, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x18202020, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x28303232, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x30303030, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x28282828, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32323232, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x30302224, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303030, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x28282828, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x22242628, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x18202020, + 1, 2, 0, 0x00001824, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001828, 0xffffffff, 0x28303232, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001830, 0xffffffff, 0x26283032, + 1, 2, 1, 0x00001834, 0xffffffff, 0x30303030, + 1, 2, 1, 0x00001838, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x28282828, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x22242628, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x32323232, + 1, 2, 0, 0x00001840, 0xffffffff, 0x26283032, + 1, 2, 0, 0x00001844, 0xffffffff, 0x30302224, + 1, 2, 1, 0x00001848, 0xffffffff, 0x28303030, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x20222426, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x28282828, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x22242628, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x18202020, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x28303232, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x26283032, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x30303030, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x28282828, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x22242628, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x32323232, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x26283032, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x30302224, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x28303030, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x20222426, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x28282828, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x22242628, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x18202020 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type6)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type6; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type7.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type7[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34343434, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x34342426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x32343434, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x28303234, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x24263434, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34343434, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x34342426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x32343434, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x28303234, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x24263434, + 0, 2, 0, 0x00001820, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 0, 2, 1, 0x00001834, 0xffffffff, 0x34343434, + 0, 2, 1, 0x00001838, 0xffffffff, 0x28303234, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x34342426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x32343434, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x28303234, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x24263434, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x34343434, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x34342426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x32343434, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x28303234, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x24263434, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323434, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x34343434, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x34342426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x32343434, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x24262830, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x28303234, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x24263434, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323434, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x34343434, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x34342426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x32343434, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x24262830, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x28303234, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x24263434, + 1, 2, 0, 0x00001824, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001828, 0xffffffff, 0x30323434, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001830, 0xffffffff, 0x28303234, + 1, 2, 1, 0x00001834, 0xffffffff, 0x34343434, + 1, 2, 1, 0x00001838, 0xffffffff, 0x28303234, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 1, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 1, 2, 0, 0x00001844, 0xffffffff, 0x34342426, + 1, 2, 1, 0x00001848, 0xffffffff, 0x32343434, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x24262830, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x28303234, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x24263434, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323434, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x28303234, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x34343434, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x34342426, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x32343434, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x24262830, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x28303234, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x24263434 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type7)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type7; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type8.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type8[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x43434343, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x43434343, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x35373941, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x43434343, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x33353739, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x43434343, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x31333537, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x43434343, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x29313335, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x43434343, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x43434343, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x35373941, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x41434343, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x33353739, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x39414141, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x31333537, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x37393939, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x29313335, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 0, 2, 0, 0x00001820, 0xffffffff, 0x43434343, + 0, 2, 0, 0x00001824, 0xffffffff, 0x43434343, + 0, 2, 0, 0x00001828, 0xffffffff, 0x35373941, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x41434343, + 0, 2, 0, 0x00001830, 0xffffffff, 0x33353739, + 0, 2, 1, 0x00001834, 0xffffffff, 0x39414141, + 0, 2, 1, 0x00001838, 0xffffffff, 0x31333537, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x37393939, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x29313335, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x43434343, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x43434343, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x35373941, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x41434343, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x33353739, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x39414141, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x31333537, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x37393939, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x29313335, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x39414345, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x38404244, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x46464646, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x36384042, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x46464646, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x46464646, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x46463738, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x42444646, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x35373840, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x46464646, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x37394143, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x33333335, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x39414345, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x38404244, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x46464646, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x36384042, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x46464646, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x46464646, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x46463738, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x42444646, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x35373840, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x46464646, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x37394143, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x33333335, + 1, 2, 0, 0x00001824, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001828, 0xffffffff, 0x39414345, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001830, 0xffffffff, 0x38404244, + 1, 2, 1, 0x00001834, 0xffffffff, 0x46464646, + 1, 2, 1, 0x00001838, 0xffffffff, 0x36384042, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x46464646, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x34363840, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x46464646, + 1, 2, 0, 0x00001840, 0xffffffff, 0x38404244, + 1, 2, 0, 0x00001844, 0xffffffff, 0x46463738, + 1, 2, 1, 0x00001848, 0xffffffff, 0x42444646, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x35373840, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x46464646, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x37394143, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x33333335, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x39414345, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x38404244, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x46464646, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x36384042, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x46464646, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x34363840, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x46464646, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x38404244, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x46463738, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x42444646, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x35373840, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x46464646, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x37394143, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x33333335 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type8)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type8; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_Type9.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_PHY_REG_PG_Type9[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x44444444, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x44444444, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x44444444, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x32343638, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x44444444, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x44444444, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34343434, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x32322426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323232, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x30303030, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262830, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20222222, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x44444444, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x44444444, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40444444, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x32343638, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404040, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 0, 1, 2, 0x00000ed8, 0xffffffff, 0x36383838, + 0, 1, 2, 0x00000edc, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34343434, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x32322426, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323232, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 0, 1, 2, 0x00000ee0, 0xffffffff, 0x30303030, + 0, 1, 2, 0x00000ee4, 0xffffffff, 0x24262830, + 0, 1, 2, 0x00000ee8, 0x0000ffff, 0x20222222, + 0, 2, 0, 0x00001820, 0xffffffff, 0x44444444, + 0, 2, 0, 0x00001824, 0xffffffff, 0x44444444, + 0, 2, 0, 0x00001828, 0xffffffff, 0x34363840, + 0, 2, 0, 0x0000182c, 0xffffffff, 0x40444444, + 0, 2, 0, 0x00001830, 0xffffffff, 0x32343638, + 0, 2, 1, 0x00001834, 0xffffffff, 0x38404040, + 0, 2, 1, 0x00001838, 0xffffffff, 0x30323436, + 0, 2, 2, 0x000018d8, 0xffffffff, 0x36383838, + 0, 2, 2, 0x000018dc, 0xffffffff, 0x28303234, + 0, 2, 0, 0x0000183c, 0xffffffff, 0x34343434, + 0, 2, 0, 0x00001840, 0xffffffff, 0x28303234, + 0, 2, 0, 0x00001844, 0xffffffff, 0x32322426, + 0, 2, 1, 0x00001848, 0xffffffff, 0x30323232, + 0, 2, 1, 0x0000184c, 0xffffffff, 0x22242628, + 0, 2, 2, 0x000018e0, 0xffffffff, 0x30303030, + 0, 2, 2, 0x000018e4, 0xffffffff, 0x24262830, + 0, 2, 2, 0x000018e8, 0x0000ffff, 0x20222222, + 0, 3, 0, 0x00001a20, 0xffffffff, 0x44444444, + 0, 3, 0, 0x00001a24, 0xffffffff, 0x44444444, + 0, 3, 0, 0x00001a28, 0xffffffff, 0x34363840, + 0, 3, 0, 0x00001a2c, 0xffffffff, 0x40444444, + 0, 3, 0, 0x00001a30, 0xffffffff, 0x32343638, + 0, 3, 1, 0x00001a34, 0xffffffff, 0x38404040, + 0, 3, 1, 0x00001a38, 0xffffffff, 0x30323436, + 0, 3, 2, 0x00001ad8, 0xffffffff, 0x36383838, + 0, 3, 2, 0x00001adc, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a3c, 0xffffffff, 0x34343434, + 0, 3, 0, 0x00001a40, 0xffffffff, 0x28303234, + 0, 3, 0, 0x00001a44, 0xffffffff, 0x32322426, + 0, 3, 1, 0x00001a48, 0xffffffff, 0x30323232, + 0, 3, 1, 0x00001a4c, 0xffffffff, 0x22242628, + 0, 3, 2, 0x00001ae0, 0xffffffff, 0x30303030, + 0, 3, 2, 0x00001ae4, 0xffffffff, 0x24262830, + 0, 3, 2, 0x00001ae8, 0x0000ffff, 0x20222222, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x36363636, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x36363636, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x29313335, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x35353535, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x28303234, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x34343434, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x27293133, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363636, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x29313335, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x35352426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x32343535, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x23252830, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x34343434, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x27293133, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x22222224, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x36363636, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x36363636, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x29313335, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x35353535, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x28303234, + 1, 1, 2, 0x00000ed8, 0xffffffff, 0x34343434, + 1, 1, 2, 0x00000edc, 0xffffffff, 0x27293133, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x36363636, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x29313335, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x35352426, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x32343535, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x23252830, + 1, 1, 2, 0x00000ee0, 0xffffffff, 0x34343434, + 1, 1, 2, 0x00000ee4, 0xffffffff, 0x27293133, + 1, 1, 2, 0x00000ee8, 0x0000ffff, 0x22222224, + 1, 2, 0, 0x00001824, 0xffffffff, 0x36363636, + 1, 2, 0, 0x00001828, 0xffffffff, 0x30323436, + 1, 2, 0, 0x0000182c, 0xffffffff, 0x36363636, + 1, 2, 0, 0x00001830, 0xffffffff, 0x29313335, + 1, 2, 1, 0x00001834, 0xffffffff, 0x35353535, + 1, 2, 1, 0x00001838, 0xffffffff, 0x28303234, + 1, 2, 2, 0x000018d8, 0xffffffff, 0x34343434, + 1, 2, 2, 0x000018dc, 0xffffffff, 0x27293133, + 1, 2, 0, 0x0000183c, 0xffffffff, 0x36363636, + 1, 2, 0, 0x00001840, 0xffffffff, 0x29313335, + 1, 2, 0, 0x00001844, 0xffffffff, 0x35352426, + 1, 2, 1, 0x00001848, 0xffffffff, 0x32343535, + 1, 2, 1, 0x0000184c, 0xffffffff, 0x23252830, + 1, 2, 2, 0x000018e0, 0xffffffff, 0x34343434, + 1, 2, 2, 0x000018e4, 0xffffffff, 0x27293133, + 1, 2, 2, 0x000018e8, 0x0000ffff, 0x22222224, + 1, 3, 0, 0x00001a24, 0xffffffff, 0x36363636, + 1, 3, 0, 0x00001a28, 0xffffffff, 0x30323436, + 1, 3, 0, 0x00001a2c, 0xffffffff, 0x36363636, + 1, 3, 0, 0x00001a30, 0xffffffff, 0x29313335, + 1, 3, 1, 0x00001a34, 0xffffffff, 0x35353535, + 1, 3, 1, 0x00001a38, 0xffffffff, 0x28303234, + 1, 3, 2, 0x00001ad8, 0xffffffff, 0x34343434, + 1, 3, 2, 0x00001adc, 0xffffffff, 0x27293133, + 1, 3, 0, 0x00001a3c, 0xffffffff, 0x36363636, + 1, 3, 0, 0x00001a40, 0xffffffff, 0x29313335, + 1, 3, 0, 0x00001a44, 0xffffffff, 0x35352426, + 1, 3, 1, 0x00001a48, 0xffffffff, 0x32343535, + 1, 3, 1, 0x00001a4c, 0xffffffff, 0x23252830, + 1, 3, 2, 0x00001ae0, 0xffffffff, 0x34343434, + 1, 3, 2, 0x00001ae4, 0xffffffff, 0x27293133, + 1, 3, 2, 0x00001ae8, 0x0000ffff, 0x22222224 +}; + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8814A_PHY_REG_PG_Type9)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_PHY_REG_PG_Type9; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8814A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.h index 87734253c35..a8a85afe8ea 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_bb.h @@ -1,164 +1,164 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8814A_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8814A_H -#define __INC_MP_BB_HW_IMG_8814A_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_MP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_MP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_MP(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG(void); - -/****************************************************************************** -* PHY_REG_PG_Type0.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type0(void); - -/****************************************************************************** -* PHY_REG_PG_Type1.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type1(void); - -/****************************************************************************** -* PHY_REG_PG_Type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type2(void); - -/****************************************************************************** -* PHY_REG_PG_Type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type3(void); - -/****************************************************************************** -* PHY_REG_PG_Type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type4(void); - -/****************************************************************************** -* PHY_REG_PG_Type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type5(void); - -/****************************************************************************** -* PHY_REG_PG_Type6.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type6(void); - -/****************************************************************************** -* PHY_REG_PG_Type7.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type7(void); - -/****************************************************************************** -* PHY_REG_PG_Type8.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type8(void); - -/****************************************************************************** -* PHY_REG_PG_Type9.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type9(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8814A_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8814A_H +#define __INC_MP_BB_HW_IMG_8814A_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_MP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_MP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_MP(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG(void); + +/****************************************************************************** +* PHY_REG_PG_Type0.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type0(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type0(void); + +/****************************************************************************** +* PHY_REG_PG_Type1.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type1(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type1(void); + +/****************************************************************************** +* PHY_REG_PG_Type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type2(void); + +/****************************************************************************** +* PHY_REG_PG_Type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type3(void); + +/****************************************************************************** +* PHY_REG_PG_Type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type4(void); + +/****************************************************************************** +* PHY_REG_PG_Type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type5(void); + +/****************************************************************************** +* PHY_REG_PG_Type6.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type6(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type6(void); + +/****************************************************************************** +* PHY_REG_PG_Type7.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type7(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type7(void); + +/****************************************************************************** +* PHY_REG_PG_Type8.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type8(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type8(void); + +/****************************************************************************** +* PHY_REG_PG_Type9.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_PHY_REG_PG_Type9(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type9(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.c index 98a31ac521f..95436d08765 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.c @@ -1,7785 +1,7785 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8814a/hal8814a_fw.h" -#endif - - -#if (RTL8814A_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8814A_FW_AP[] = { -0x14, 0x88, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x42, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x0A, 0x1C, 0x13, 0x30, 0xDF, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0xE8, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE4, 0x23, 0xF7, 0x70, 0xC2, -0xDD, 0x67, 0x96, 0xA6, 0x5D, 0x67, 0x76, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x0C, 0x4B, -0x68, 0x33, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE3, 0x60, 0x9A, 0xDD, 0x67, 0xB4, 0xA6, 0xDD, 0x67, -0x53, 0xA6, 0x49, 0xE5, 0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x0C, 0x4C, 0x88, 0x34, -0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE4, 0x60, 0xDA, 0x05, 0x10, 0x00, 0x65, 0x03, 0x10, 0x00, 0x65, -0x01, 0x10, 0x00, 0x65, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x01, 0x14, 0x00, 0x00, -0xEC, 0x8C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -u4Byte ArrayLength_MP_8814A_FW_NIC = 66904; - - -#endif - -void -ODM_ReadFirmware_MP_8814A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8814A_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8814A_FW_NIC, ArrayLength_MP_8814A_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8814A_FW_NIC; -} - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8814a/hal8814a_fw.h" +#endif + + +#if (RTL8814A_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8814A_FW_AP[] = { +0x14, 0x88, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x42, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x0A, 0x1C, 0x13, 0x30, 0xDF, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0xE8, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x16, 0x4B, 0x68, 0x33, 0x02, 0xF4, +0x08, 0x4A, 0x49, 0xE3, 0x60, 0x9A, 0xDD, 0x67, 0xB4, 0xA6, 0xDD, 0x67, 0x53, 0xA6, 0x49, 0xE5, +0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x16, 0x4C, 0x88, 0x34, 0x02, 0xF4, 0x08, 0x4A, +0x49, 0xE4, 0x60, 0xDA, 0x05, 0x10, 0x00, 0x65, 0x03, 0x10, 0x00, 0x65, 0x01, 0x10, 0x00, 0x65, +0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + +}; +u4Byte ArrayLength_MP_8814A_FW_AP = 56224; + +#endif + +void +ODM_ReadFirmware_MP_8814A_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8814A_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8814A_FW_AP, ArrayLength_MP_8814A_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8814A_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8814A_FW_NIC[] = { +0x14, 0x88, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x42, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x0A, 0x1C, 0x13, 0x30, 0xDF, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0xF8, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x10, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE9, 0x02, 0x00, 0x80, 0xF9, 0x02, 0x00, 0x80, +0x09, 0x03, 0x00, 0x80, 0x19, 0x03, 0x00, 0x80, 0x29, 0x03, 0x00, 0x80, 0x39, 0x03, 0x00, 0x80, +0x49, 0x03, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, +0x35, 0x04, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, 0x35, 0x04, 0x00, 0x80, +0x35, 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x06, 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0x01, 0x6A, 0x7D, 0x67, 0x50, 0xC3, 0x03, 0x10, 0x02, 0x6A, 0x9D, 0x67, 0x50, 0xC4, +0xBD, 0x67, 0x20, 0xF0, 0x40, 0xA5, 0x4C, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA1, 0xF4, +0x40, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, +0x43, 0x32, 0x00, 0x52, 0x58, 0x67, 0x7A, 0x22, 0x7D, 0x67, 0x56, 0xA3, 0x30, 0xF0, 0x20, 0x6B, +0x4C, 0x32, 0x48, 0x34, 0x89, 0xE2, 0x02, 0xF5, 0x18, 0x4B, 0x69, 0xE2, 0x60, 0xF5, 0x57, 0xA2, +0x5A, 0x32, 0x62, 0x67, 0x01, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA, 0x67, 0x22, 0x9D, 0x67, +0x55, 0xA4, 0x37, 0x2A, 0xBD, 0x67, 0x56, 0xA5, 0x30, 0xF0, 0x20, 0x6B, 0x02, 0xF5, 0x18, 0x4B, +0x6D, 0xE2, 0xA5, 0xF1, 0x70, 0xA3, 0x81, 0x43, 0xFF, 0x6B, 0x8C, 0xEB, 0x30, 0xF0, 0x20, 0x6C, +0x02, 0xF5, 0x18, 0x4C, 0x89, 0xE2, 0xA5, 0xF1, 0x70, 0xC2, 0xDD, 0x67, 0x76, 0xA6, 0x30, 0xF0, +0x20, 0x6A, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE3, 0xA5, 0xF1, 0x70, 0xA2, 0x9D, 0x67, 0x56, 0xA4, +0x30, 0xF0, 0x20, 0x6C, 0x4C, 0x32, 0x48, 0x35, 0xA9, 0xE2, 0x02, 0xF5, 0x18, 0x4C, 0x89, 0xE2, +0x60, 0xF5, 0x5B, 0xA2, 0x6E, 0xEA, 0xC0, 0xF0, 0x02, 0x2A, 0xBD, 0x67, 0x56, 0xA5, 0x82, 0x67, +0x01, 0x6D, 0x00, 0x18, 0xEB, 0x30, 0xDD, 0x67, 0x56, 0xA6, 0x82, 0x67, 0x00, 0x18, 0x77, 0x3B, +0xB9, 0x10, 0x7D, 0x67, 0x56, 0xA3, 0x30, 0xF0, 0x20, 0x6B, 0x02, 0xF5, 0x18, 0x4B, 0x6D, 0xE2, +0x25, 0xF2, 0x70, 0xA3, 0x81, 0x43, 0xFF, 0x6B, 0x8C, 0xEB, 0x30, 0xF0, 0x20, 0x6C, 0x02, 0xF5, +0x18, 0x4C, 0x89, 0xE2, 0x25, 0xF2, 0x70, 0xC2, 0x9D, 0x67, 0x76, 0xA4, 0x30, 0xF0, 0x20, 0x6A, +0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE3, 0x25, 0xF2, 0x50, 0xA2, 0xBD, 0x67, 0x70, 0xA5, 0x6E, 0xEA, +0x80, 0xF0, 0x17, 0x2A, 0xDD, 0x67, 0x56, 0xA6, 0x82, 0x67, 0x00, 0x6D, 0x00, 0x18, 0xEB, 0x30, +0x7D, 0x67, 0x56, 0xA3, 0x82, 0x67, 0x00, 0x18, 0x77, 0x3B, 0x8C, 0x10, 0x9D, 0x67, 0x55, 0xA4, +0xFF, 0x6B, 0x4C, 0xEB, 0x05, 0x5B, 0x78, 0x67, 0x01, 0x2B, 0x04, 0x6A, 0x7D, 0x67, 0x55, 0xC3, +0x9D, 0x67, 0x20, 0xF0, 0x40, 0xA4, 0x4C, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA1, 0xF4, +0x40, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB, 0x3F, 0x6A, 0x6C, 0xEA, 0xBD, 0x67, +0x54, 0xC5, 0xDD, 0x67, 0x20, 0xF0, 0x40, 0xA6, 0x4C, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, +0xA1, 0xF4, 0x44, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB, 0x3F, 0x6A, 0x6C, 0xEA, +0x7D, 0x67, 0x53, 0xC3, 0x9D, 0x67, 0x76, 0xA4, 0xBD, 0x67, 0xD5, 0xA5, 0x5D, 0x67, 0x96, 0xA2, +0xBD, 0x67, 0xF5, 0xA5, 0x30, 0xF0, 0x20, 0x6D, 0x44, 0x67, 0x48, 0x32, 0x89, 0xE2, 0xE9, 0xE2, +0xE0, 0xF7, 0x0C, 0x4A, 0x48, 0x34, 0x45, 0x67, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE4, 0x80, 0x9A, +0xBD, 0x67, 0x54, 0xA5, 0x51, 0xE4, 0x30, 0xF0, 0x20, 0x6D, 0x43, 0x67, 0x48, 0x32, 0x69, 0xE2, +0xC9, 0xE2, 0xE0, 0xF7, 0x0C, 0x4A, 0x48, 0x33, 0x45, 0x67, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE3, +0x80, 0xDA, 0xDD, 0x67, 0x96, 0xA6, 0x5D, 0x67, 0x76, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0x02, 0xF5, +0x18, 0x4A, 0x49, 0xE3, 0x23, 0xF7, 0x70, 0xA2, 0xBD, 0x67, 0x53, 0xA5, 0x4D, 0xE3, 0xFF, 0x6A, +0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE4, 0x23, 0xF7, 0x70, 0xC2, +0xDD, 0x67, 0x96, 0xA6, 0x5D, 0x67, 0x76, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x0C, 0x4B, +0x68, 0x33, 0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE3, 0x60, 0x9A, 0xDD, 0x67, 0xB4, 0xA6, 0xDD, 0x67, +0x53, 0xA6, 0x49, 0xE5, 0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x0C, 0x4C, 0x88, 0x34, +0x02, 0xF5, 0x18, 0x4A, 0x49, 0xE4, 0x60, 0xDA, 0x05, 0x10, 0x00, 0x65, 0x03, 0x10, 0x00, 0x65, +0x01, 0x10, 0x00, 0x65, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x01, 0x14, 0x00, 0x00, +0xEC, 0x8C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +u4Byte ArrayLength_MP_8814A_FW_NIC = 66904; + + +#endif + +void +ODM_ReadFirmware_MP_8814A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8814A_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8814A_FW_NIC, ArrayLength_MP_8814A_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8814A_FW_NIC; +} + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.h index baf33022cd7..585a8def321 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_fw.h @@ -1,51 +1,51 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8814A_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8814A_H -#define __INC_MP_FW_HW_IMG_8814A_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8814A_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8814A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8814A_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8814A_H +#define __INC_MP_FW_HW_IMG_8814A_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8814A_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8814A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.c index d62c88a52d8..acf52f5b0a6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.c @@ -1,309 +1,309 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_MAC_REG[] = { - 0x010, 0x0000007C, - 0x014, 0x000000DB, - 0x016, 0x00000002, - 0x073, 0x00000010, - 0x420, 0x00000080, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x000000F0, - 0x446, 0x00000001, - 0x447, 0x000000FE, - 0x448, 0x00000000, - 0x449, 0x00000000, - 0x44A, 0x00000000, - 0x44B, 0x00000040, - 0x44C, 0x00000010, - 0x44D, 0x000000F0, - 0x44E, 0x0000003F, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x00000000, - 0x452, 0x00000000, - 0x453, 0x00000040, - 0x45E, 0x00000004, - 0x49C, 0x00000010, - 0x49D, 0x000000F0, - 0x49E, 0x00000000, - 0x49F, 0x00000006, - 0x4A0, 0x000000E0, - 0x4A1, 0x00000003, - 0x4A2, 0x00000000, - 0x4A3, 0x00000040, - 0x4A4, 0x00000015, - 0x4A5, 0x000000F0, - 0x4A6, 0x00000000, - 0x4A7, 0x00000006, - 0x4A8, 0x000000E0, - 0x4A9, 0x00000000, - 0x4AA, 0x00000000, - 0x4AB, 0x00000000, - 0x7DA, 0x00000008, - 0x1448, 0x00000006, - 0x144A, 0x00000006, - 0x144C, 0x00000006, - 0x144E, 0x00000006, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CA, 0x0000003C, - 0x4CB, 0x0000003C, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4CF, 0x00000008, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x521, 0x0000002F, - 0x525, 0x00000047, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000064, - 0x55D, 0x000000FF, - 0x577, 0x00000003, - 0x5BE, 0x00000064, - 0x604, 0x00000001, - 0x605, 0x00000030, - 0x607, 0x00000001, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x60A, 0x00000000, - 0x60C, 0x00000018, - 0x60D, 0x00000050, - 0x6A0, 0x000000FF, - 0x6A1, 0x000000FF, - 0x6A2, 0x000000FF, - 0x6A3, 0x000000FF, - 0x6A4, 0x000000FF, - 0x6A5, 0x000000FF, - 0x6DE, 0x00000084, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000064, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x718, 0x00000040, - 0x7D5, 0x000000BC, - 0x7D8, 0x00000028, - 0x7D9, 0x00000000, - 0x7DA, 0x0000000B, - -}; - -void -ODM_ReadAndConfig_MP_8814A_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8814A(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_MAC_REG(void) -{ - return 107; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_MAC_REG[] = { + 0x010, 0x0000007C, + 0x014, 0x000000DB, + 0x016, 0x00000002, + 0x073, 0x00000010, + 0x420, 0x00000080, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x000000F0, + 0x446, 0x00000001, + 0x447, 0x000000FE, + 0x448, 0x00000000, + 0x449, 0x00000000, + 0x44A, 0x00000000, + 0x44B, 0x00000040, + 0x44C, 0x00000010, + 0x44D, 0x000000F0, + 0x44E, 0x0000003F, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x00000000, + 0x452, 0x00000000, + 0x453, 0x00000040, + 0x45E, 0x00000004, + 0x49C, 0x00000010, + 0x49D, 0x000000F0, + 0x49E, 0x00000000, + 0x49F, 0x00000006, + 0x4A0, 0x000000E0, + 0x4A1, 0x00000003, + 0x4A2, 0x00000000, + 0x4A3, 0x00000040, + 0x4A4, 0x00000015, + 0x4A5, 0x000000F0, + 0x4A6, 0x00000000, + 0x4A7, 0x00000006, + 0x4A8, 0x000000E0, + 0x4A9, 0x00000000, + 0x4AA, 0x00000000, + 0x4AB, 0x00000000, + 0x7DA, 0x00000008, + 0x1448, 0x00000006, + 0x144A, 0x00000006, + 0x144C, 0x00000006, + 0x144E, 0x00000006, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CA, 0x0000003C, + 0x4CB, 0x0000003C, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4CF, 0x00000008, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x521, 0x0000002F, + 0x525, 0x00000047, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000064, + 0x55D, 0x000000FF, + 0x577, 0x00000003, + 0x5BE, 0x00000064, + 0x604, 0x00000001, + 0x605, 0x00000030, + 0x607, 0x00000001, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x60A, 0x00000000, + 0x60C, 0x00000018, + 0x60D, 0x00000050, + 0x6A0, 0x000000FF, + 0x6A1, 0x000000FF, + 0x6A2, 0x000000FF, + 0x6A3, 0x000000FF, + 0x6A4, 0x000000FF, + 0x6A5, 0x000000FF, + 0x6DE, 0x00000084, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000064, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + 0x7D5, 0x000000BC, + 0x7D8, 0x00000028, + 0x7D9, 0x00000000, + 0x7DA, 0x0000000B, + +}; + +void +ODM_ReadAndConfig_MP_8814A_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8814A(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_MAC_REG(void) +{ + return 107; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.h index 8849722a1db..bc23da9eaed 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_mac.h @@ -1,34 +1,34 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8814A_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8814A_H -#define __INC_MP_MAC_HW_IMG_8814A_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8814A_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8814A_H +#define __INC_MP_MAC_HW_IMG_8814A_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.c index f46f013531b..26bb94e806d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.c @@ -1,19404 +1,19404 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_RadioA[] = { - 0x018, 0x00013124, - 0x040, 0x00000C00, - 0x058, 0x00000F98, - 0x07F, 0x00068004, - 0x0B0, 0x000FFFFE, - 0x0B1, 0x0003FF48, - 0x0B2, 0x0006AA3F, - 0x0B3, 0x000FFC9A, - 0x0B4, 0x0000A78F, - 0x0B5, 0x00000A3F, - 0x0B6, 0x0000C09C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x0B7, 0x00030008, - 0xA0000000, 0x00000000, - 0x0B7, 0x0003000C, - 0xB0000000, 0x00000000, - 0x0B8, 0x0007400E, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0xA0000000, 0x00000000, - 0x0B9, 0x000FBF50, - 0xB0000000, 0x00000000, - 0x0BA, 0x00050780, - 0x0BB, 0x00000000, - 0x0BC, 0x00040009, - 0x0BD, 0x00000000, - 0x0BE, 0x00000000, - 0x0BF, 0x00000000, - 0x0EF, 0x00020000, - 0x03E, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0xA0000000, 0x00000000, - 0x03F, 0x00030000, - 0xB0000000, 0x00000000, - 0x03E, 0x00020000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00040000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00040000, - 0xA0000000, 0x00000000, - 0x03F, 0x00040000, - 0xB0000000, 0x00000000, - 0x03E, 0x00040000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0xA0000000, 0x00000000, - 0x03F, 0x00030000, - 0xB0000000, 0x00000000, - 0x03E, 0x00060000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00030000, - 0xA0000000, 0x00000000, - 0x03F, 0x00030000, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x00010000, - 0x03E, 0x00000000, - 0x03F, 0x00006800, - 0x03E, 0x00000080, - 0x03F, 0x00006000, - 0x03E, 0x00000100, - 0x03F, 0x00004800, - 0x03E, 0x00000180, - 0x03F, 0x00004000, - 0x03E, 0x00000200, - 0x03F, 0x00004000, - 0x03E, 0x00000280, - 0x03F, 0x00002800, - 0x03E, 0x00000300, - 0x03F, 0x00002800, - 0x03E, 0x00000380, - 0x03F, 0x00002000, - 0x0EF, 0x00000000, - 0x0EF, 0x00040000, - 0x03E, 0x00000000, - 0x03F, 0x000000BC, - 0x03E, 0x00000040, - 0x03F, 0x00000053, - 0x03E, 0x00000050, - 0x03F, 0x00000050, - 0x03E, 0x00000060, - 0x03F, 0x00000050, - 0x0EF, 0x00000000, - 0x0EF, 0x00000400, - 0x03E, 0x00000006, - 0x041, 0x000EE080, - 0x03E, 0x00000008, - 0x041, 0x000EE0C0, - 0x03E, 0x0000000A, - 0x041, 0x000EE100, - 0x03E, 0x0000000C, - 0x041, 0x000EE100, - 0x0EF, 0x00000000, - 0x018, 0x00000006, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0xA0000000, 0x00000000, - 0x086, 0x000E4B58, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000008, - 0x0EF, 0x00002000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x000179C3, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x000179C3, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x000179C3, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x000179C3, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x000179C3, - 0xA0000000, 0x00000000, - 0x03B, 0x0003F258, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF6, - 0x034, 0x00009DF3, - 0x034, 0x00008DF0, - 0x034, 0x00007DED, - 0x034, 0x00006DEA, - 0x034, 0x00005CED, - 0x034, 0x00004CEA, - 0x034, 0x000034EA, - 0x034, 0x000024E7, - 0x034, 0x0000146A, - 0x034, 0x0000006B, - 0xB0000000, 0x00000000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0008ADF6, - 0x034, 0x00089DF3, - 0x034, 0x00088DF0, - 0x034, 0x00087DED, - 0x034, 0x00086DEA, - 0x034, 0x00085CED, - 0x034, 0x00084CEA, - 0x034, 0x000834EA, - 0x034, 0x000824E7, - 0x034, 0x0008146A, - 0x034, 0x0008006B, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x018, 0x0001012A, - 0x081, 0x0007FC00, - 0x089, 0x00050110, - 0x08A, 0x00043E50, - 0x08B, 0x0002E180, - 0x08C, 0x00093C3C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0xA0000000, 0x00000000, - 0x085, 0x000F8000, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xA0000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xB0000000, 0x00000000, - 0x0EF, 0x00001000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0xA0000000, 0x00000000, - 0x03C, 0x00028000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00030023, - 0x03C, 0x00048000, - 0x03A, 0x0000013C, - 0x03B, 0x00028623, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00021633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x0001C633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00010293, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00009593, - 0x03C, 0x00000000, - 0x03A, 0x00000148, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0000118B, - 0xA0000000, 0x00000000, - 0x03B, 0x0000078B, - 0xB0000000, 0x00000000, - 0x03C, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xA0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000AC000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00024000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00040000, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0xA0000000, 0x00000000, - 0x03C, 0x0004C000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00070023, - 0x03C, 0x00048000, - 0x03A, 0x0000013C, - 0x03B, 0x00068623, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00061633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x0005C633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00050293, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00049593, - 0x03C, 0x00000000, - 0x03A, 0x00000148, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0004138B, - 0xA0000000, 0x00000000, - 0x03B, 0x0004078B, - 0xB0000000, 0x00000000, - 0x03C, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0xA0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0008C000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00020000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00060000, - 0xA0000000, 0x00000000, - 0x03C, 0x00004000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B0023, - 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0x03C, 0x0000127D, - 0x03C, 0x0000154A, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x0000254A, - 0x03C, 0x00002821, - 0xA0000000, 0x00000000, - 0x03C, 0x0000037E, - 0x03C, 0x00000575, - 0x03C, 0x00000971, - 0x03C, 0x0000127E, - 0x03C, 0x00001575, - 0x03C, 0x00001871, - 0x03C, 0x0000217E, - 0x03C, 0x00002575, - 0x03C, 0x00002871, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x061, 0x000C0D47, - 0x062, 0x0000133C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0xA0000000, 0x00000000, - 0x063, 0x0007D0E7, - 0xB0000000, 0x00000000, - 0x064, 0x00014FEC, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 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0x01C, 0x000739D2, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x01F, 0x0002255C, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x01F, 0x0002255C, - 0xA0000000, 0x00000000, - 0x01F, 0x0002255C, - 0xB0000000, 0x00000000, - 0x0B1, 0x0007FF48, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x0C4, 0x00081700, - 0xA0000000, 0x00000000, - 0x0C4, 0x00083F00, - 0xB0000000, 0x00000000, - 0x018, 0x0001B126, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x018, 0x00013126, - 0x018, 0x00013124, - -}; - -void -ODM_ReadAndConfig_MP_8814A_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8814A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_RadioA(void) -{ - return 107; -} - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_RadioB[] = { - 0x018, 0x00013124, - 0x040, 0x00000C00, - 0x058, 0x00000F98, - 0x07F, 0x00068004, - 0x018, 0x00000006, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0xA0000000, 0x00000000, - 0x086, 0x000E4B58, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000008, - 0x0EF, 0x00002000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017BC3, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F39B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017BC3, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017BC3, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F39B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017BC3, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017BC3, - 0xA0000000, 0x00000000, - 0x03B, 0x0003F258, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF6, - 0x034, 0x00009DF3, - 0x034, 0x00008DF0, - 0x034, 0x00007DED, - 0x034, 0x00006DEA, - 0x034, 0x00005CED, - 0x034, 0x00004CEA, - 0x034, 0x000034EA, - 0x034, 0x000024E7, - 0x034, 0x0000146A, - 0x034, 0x0000006B, - 0xB0000000, 0x00000000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0008ADF6, - 0x034, 0x00089DF3, - 0x034, 0x00088DF0, - 0x034, 0x00087DED, - 0x034, 0x00086DEA, - 0x034, 0x00085CED, - 0x034, 0x00084CEA, - 0x034, 0x000834EA, - 0x034, 0x000824E7, - 0x034, 0x0008146A, - 0x034, 0x0008006B, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x018, 0x0001012A, - 0x081, 0x0007FC00, - 0x089, 0x00050110, - 0x08A, 0x00043E50, - 0x08B, 0x0002E180, - 0x08C, 0x00093C3C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0xA0000000, 0x00000000, - 0x085, 0x000F8000, - 0xB0000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x0EF, 0x00001000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0xA0000000, 0x00000000, - 0x03C, 0x00040000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00030023, - 0x03C, 0x00048000, - 0x03A, 0x0000013C, - 0x03B, 0x00028623, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00021633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x0001C633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00010293, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00009593, - 0x03C, 0x00000000, - 0x03A, 0x00000148, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x00000F8B, - 0xA0000000, 0x00000000, - 0x03B, 0x0000078B, - 0xB0000000, 0x00000000, - 0x03C, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xA0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00020000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00060000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00048000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00048000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00020000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0xA0000000, 0x00000000, - 0x03C, 0x00020000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00070023, - 0x03C, 0x00048000, - 0x03A, 0x0000013C, - 0x03B, 0x00068623, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00061633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x0005C633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00050293, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00049593, - 0x03C, 0x00000000, - 0x03A, 0x00000148, - 0x03B, 0x0004078B, - 0x03C, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x000B8023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 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0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027E, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127E, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227E, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027E, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127E, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227E, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027E, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127E, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227E, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0xA0000000, 0x00000000, - 0x03C, 0x0000037E, - 0x03C, 0x00000575, - 0x03C, 0x00000971, - 0x03C, 0x0000127E, - 0x03C, 0x00001575, - 0x03C, 0x00001871, - 0x03C, 0x0000217E, - 0x03C, 0x00002575, - 0x03C, 0x00002871, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x061, 0x000C0D47, - 0x062, 0x0000133C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0xA0000000, 0x00000000, - 0x063, 0x0007D0E7, - 0xB0000000, 0x00000000, - 0x064, 0x00014FEC, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0xA0000000, 0x00000000, - 0x065, 0x000923FF, - 0xB0000000, 0x00000000, - 0x066, 0x00000040, - 0x057, 0x00050000, - 0x056, 0x00051DF0, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0xA0000000, 0x00000000, - 0x055, 0x00082060, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8814A_RadioB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioB_8814A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_RadioB(void) -{ - return 107; -} - -/****************************************************************************** -* RadioC.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_RadioC[] = { - 0x018, 0x00013124, - 0x040, 0x00000C00, - 0x058, 0x00000F98, - 0x07F, 0x00068004, - 0x018, 0x00000006, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0xA0000000, 0x00000000, - 0x086, 0x000E4B58, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000008, - 0x0EF, 0x00002000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017823, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017823, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017823, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017823, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017823, - 0xA0000000, 0x00000000, - 0x03B, 0x0003F258, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF6, - 0x034, 0x00009DF3, - 0x034, 0x00008DF0, - 0x034, 0x00007DED, - 0x034, 0x00006DEA, - 0x034, 0x00005CED, - 0x034, 0x00004CEA, - 0x034, 0x000034EA, - 0x034, 0x000024E7, - 0x034, 0x0000146A, - 0x034, 0x0000006B, - 0xB0000000, 0x00000000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0008ADF6, - 0x034, 0x00089DF3, - 0x034, 0x00088DF0, - 0x034, 0x00087DED, - 0x034, 0x00086DEA, - 0x034, 0x00085CED, - 0x034, 0x00084CEA, - 0x034, 0x000834EA, - 0x034, 0x000824E7, - 0x034, 0x0008146A, - 0x034, 0x0008006B, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x018, 0x0001012A, - 0x081, 0x0007FC00, - 0x089, 0x00050110, - 0x08A, 0x00043E50, - 0x08B, 0x0002E180, - 0x08C, 0x00093C3C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0xA0000000, 0x00000000, - 0x085, 0x000F8000, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xA0000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xB0000000, 0x00000000, - 0x0EF, 0x00001000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0006C000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000D4000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00080000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00088000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0006C000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0008C000, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00004000, - 0xA0000000, 0x00000000, - 0x03C, 0x000A0000, - 0xB0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00030023, - 0x03C, 0x00048000, - 0x03A, 0x0000013C, - 0x03B, 0x00028623, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00021633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x0001C633, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00010293, - 0x03C, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00009593, - 0x03C, 0x00000000, - 0x03A, 0x00000148, - 0x80000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0000118B, - 0xA0000000, 0x00000000, - 0x03B, 0x0000078B, - 0xB0000000, 0x00000000, - 0x03C, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xA0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00078023, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0004C000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00084000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00080000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0004C000, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000D0000, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 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0x03C, 0x00001541, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002541, - 0x03C, 0x00002821, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027D, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127D, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027D, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127D, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027D, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127D, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027D, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127D, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027D, - 0x03C, 0x00000546, - 0x03C, 0x00000821, - 0x03C, 0x0000127D, - 0x03C, 0x00001546, - 0x03C, 0x00001821, - 0x03C, 0x0000227D, - 0x03C, 0x00002546, - 0x03C, 0x00002821, - 0xA0000000, 0x00000000, - 0x03C, 0x0000037E, - 0x03C, 0x00000575, - 0x03C, 0x00000971, - 0x03C, 0x0000127E, - 0x03C, 0x00001575, - 0x03C, 0x00001871, - 0x03C, 0x0000217E, - 0x03C, 0x00002575, - 0x03C, 0x00002871, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x061, 0x000C0D47, - 0x062, 0x0000133C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0xA0000000, 0x00000000, - 0x063, 0x0007D0E7, - 0xB0000000, 0x00000000, - 0x064, 0x00014FEC, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0xA0000000, 0x00000000, - 0x065, 0x000923FF, - 0xB0000000, 0x00000000, - 0x066, 0x00000040, - 0x057, 0x00050000, - 0x056, 0x00051DF0, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0xA0000000, 0x00000000, - 0x055, 0x00082060, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8814A_RadioC( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioC)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_RadioC; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioC\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioC_8814A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_RadioC(void) -{ - return 107; -} - -/****************************************************************************** -* RadioD.TXT -******************************************************************************/ - -u4Byte Array_MP_8814A_RadioD[] = { - 0x018, 0x00013124, - 0x040, 0x00000C00, - 0x058, 0x00000F98, - 0x07F, 0x00068004, - 0x018, 0x00000006, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x000E335A, - 0x087, 0x00079F80, - 0xA0000000, 0x00000000, - 0x086, 0x000E4B58, - 0x087, 0x00049F80, - 0xB0000000, 0x00000000, - 0x0DF, 0x00000008, - 0x0EF, 0x00002000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017803, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F09B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017803, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017803, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F09B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017803, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03B, 0x0003F19B, - 0x03B, 0x00037A5B, - 0x03B, 0x0002A433, - 0x03B, 0x00027BD3, - 0x03B, 0x0001F80B, - 0x03B, 0x00017803, - 0xA0000000, 0x00000000, - 0x03B, 0x0003F258, - 0x03B, 0x00030A58, - 0x03B, 0x0002FA58, - 0x03B, 0x00022590, - 0x03B, 0x0001FA50, - 0x03B, 0x00010248, - 0x03B, 0x00008240, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF6, - 0x034, 0x00009DF3, - 0x034, 0x00008DF0, - 0x034, 0x00007DED, - 0x034, 0x00006DEA, - 0x034, 0x00005CED, - 0x034, 0x00004CEA, - 0x034, 0x000034EA, - 0x034, 0x000024E7, - 0x034, 0x0000146A, - 0x034, 0x0000006B, - 0xB0000000, 0x00000000, - 0x80000002, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D0, - 0x034, 0x000090CD, - 0x034, 0x000080CA, - 0x034, 0x0000704D, - 0x034, 0x0000604A, - 0x034, 0x00005047, - 0x034, 0x0000400A, - 0x034, 0x00003007, - 0x034, 0x00002004, - 0x034, 0x00001001, - 0x034, 0x00000001, - 0xA0000000, 0x00000000, - 0x034, 0x0008ADF6, - 0x034, 0x00089DF3, - 0x034, 0x00088DF0, - 0x034, 0x00087DED, - 0x034, 0x00086DEA, - 0x034, 0x00085CED, - 0x034, 0x00084CEA, - 0x034, 0x000834EA, - 0x034, 0x000824E7, - 0x034, 0x0008146A, - 0x034, 0x0008006B, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000192, - 0x035, 0x00008192, - 0x035, 0x00010192, - 0x036, 0x00000024, - 0x036, 0x00008024, - 0x036, 0x00010024, - 0x036, 0x00018024, - 0x0EF, 0x00000000, - 0x051, 0x00000C21, - 0x052, 0x000006D9, - 0x053, 0x000FC649, - 0x054, 0x0000017E, - 0x018, 0x0001012A, - 0x081, 0x0007FC00, - 0x089, 0x00050110, - 0x08A, 0x00043E50, - 0x08B, 0x0002E180, - 0x08C, 0x00093C3C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x085, 0x000F8000, - 0xA0000000, 0x00000000, - 0x085, 0x000F8000, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xA0000000, 0x00000000, - 0x08D, 0x000FFFF0, - 0xB0000000, 0x00000000, - 0x0EF, 0x00001000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0xA0000000, 0x00000000, - 0x03A, 0x0000013C, - 0x03B, 0x00038023, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00044000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00048000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000000, - 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0x036, 0x00030475, - 0x036, 0x00040475, - 0x036, 0x00048475, - 0x036, 0x00050475, - 0x036, 0x00080475, - 0x036, 0x00088475, - 0x036, 0x00090475, - 0x036, 0x000A0475, - 0x036, 0x000A8475, - 0x036, 0x000B0475, - 0x036, 0x000C0475, - 0x036, 0x000C8475, - 0x036, 0x000D0475, - 0xA0000000, 0x00000000, - 0x036, 0x00000474, - 0x036, 0x00008474, - 0x036, 0x00010474, - 0x036, 0x00020474, - 0x036, 0x00028474, - 0x036, 0x00030474, - 0x036, 0x00040474, - 0x036, 0x00048474, - 0x036, 0x00050474, - 0x036, 0x00080474, - 0x036, 0x00088474, - 0x036, 0x00090474, - 0x036, 0x000A0474, - 0x036, 0x000A8474, - 0x036, 0x000B0474, - 0x036, 0x000C0474, - 0x036, 0x000C8474, - 0x036, 0x000D0474, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 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0x037, 0x00098000, - 0x038, 0x00005ECE, - 0x037, 0x0009C000, - 0x038, 0x00005ECE, - 0x037, 0x000A0000, - 0x038, 0x00005ECE, - 0x037, 0x000A4000, - 0x038, 0x00005ECE, - 0x037, 0x000A8000, - 0x038, 0x00005ECE, - 0x037, 0x000AC000, - 0x038, 0x00005ECE, - 0x037, 0x000B0000, - 0x038, 0x00005ECE, - 0x037, 0x000B4000, - 0x038, 0x00005ECE, - 0x037, 0x000B8000, - 0x038, 0x00005ECE, - 0x037, 0x000BC000, - 0x038, 0x00005ECE, - 0x037, 0x000C0000, - 0x038, 0x00005ECE, - 0x037, 0x000C4000, - 0x038, 0x00005ECE, - 0x037, 0x000C8000, - 0x038, 0x00005ECE, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000008, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0xA0000000, 0x00000000, - 0x03C, 0x0000007D, - 0x03C, 0x0000047D, - 0x03C, 0x0000087D, - 0x03C, 0x0000107D, - 0x03C, 0x0000147D, - 0x03C, 0x0000187D, - 0xB0000000, 0x00000000, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000275, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x00001275, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x00002275, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027F, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x0000127F, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x0000227F, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027F, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x0000127F, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x0000227F, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027F, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x0000127F, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x0000227F, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027F, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x0000127F, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x0000227F, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000027F, - 0x03C, 0x00000542, - 0x03C, 0x00000821, - 0x03C, 0x0000127F, - 0x03C, 0x00001542, - 0x03C, 0x00001821, - 0x03C, 0x0000227F, - 0x03C, 0x00002542, - 0x03C, 0x00002821, - 0xA0000000, 0x00000000, - 0x03C, 0x0000037E, - 0x03C, 0x00000575, - 0x03C, 0x00000971, - 0x03C, 0x0000127E, - 0x03C, 0x00001575, - 0x03C, 0x00001871, - 0x03C, 0x0000217E, - 0x03C, 0x00002575, - 0x03C, 0x00002871, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x061, 0x000C0D47, - 0x062, 0x0000133C, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000750E7, - 0xA0000000, 0x00000000, - 0x063, 0x0007D0E7, - 0xB0000000, 0x00000000, - 0x064, 0x00014FEC, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x000920D0, - 0xA0000000, 0x00000000, - 0x065, 0x000923FF, - 0xB0000000, 0x00000000, - 0x066, 0x00000040, - 0x057, 0x00050000, - 0x056, 0x00051DF0, - 0x80000001, 0x00000000, 0x40000000, 0x00000000, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0xA0000000, 0x00000000, - 0x055, 0x00082060, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8814A_RadioD( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioD)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8814A_RadioD; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioD\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioD_8814A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8814A_RadioD(void) -{ - return 107; -} - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19}, - {0, 1, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 16, 16, 17, 18}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 24, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 17}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 23, 24}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type0.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type0( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type1.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19}, - {0, 1, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 16, 16, 17, 18}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 24, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 17}, - {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 23, 24}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type1( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type2.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, - {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type2( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type3.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, - {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type3( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type4.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, - {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type4( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type5.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 3, 3, 3, 4, 6, 6, 7, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 4, 5, 6, 7, 7, 8, 7, 8, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 0, 0, 1, 1, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 0, 1, 1, 2, 2, 3, 5, 7, 8, 9, 10, 11, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 4, 6, 7, 7, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 3, 3, 7, 7, 8, 8, 9, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 0, 1, 2, 3, 4, 5, 7, 8, 8, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 9, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13}, - {0, 0, 1, 2, 3, 3, 5, 5, 6, 8, 8, 9, 10, 11, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 4, 4, 5, 7, 8, 9, 9, 10, 11, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 3, 3, 7, 7, 8, 8, 9, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 0, 1, 2, 3, 4, 5, 7, 8, 8, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 1, 2, 2, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 0, 2, 3, 4, 5, 6, 8, 8, 9, 9, 11, 12, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 11, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 0, 1, 2, 3, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12}, - {0, 2, 3, 4, 5, 7, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 4, 6, 7, 8, 8, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 3, 3, 3, 5, 5, 6, 6, 8, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 8, 9, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 0, 1, 3, 3, 4, 5, 5, 6, 7, 7, 8, 10, 10, 11, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 8, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 111, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 10, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type5_8814A[] = {0, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type5_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8814A[] = {0, 2, 3, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 2, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type5( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type6.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type6( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type7.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type7( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type8.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 4, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 4, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 0, 1, 2, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 3, 4, 4, 5, 6, 7, 7, 8, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, - {0, 0, 1, 2, 4, 5, 5, 6, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 10, 11, 11, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 10, 10, 11, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, - {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, - {0, 0, 1, 2, 3, 3, 4, 4, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type8_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type8( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type9.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, - {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type9( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTSSI.TXT -******************************************************************************/ - -u1Byte gDeltaTSSITableIdx_MP_5GD_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 8, 8, 10, 13, 15, 20, 22, 25, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 7, 9, 11, 11, 13, 15, 17, 23, 23, 31, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 7, 9, 10, 15, 15, 17, 20, 22, 25, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; -u1Byte gDeltaTSSITableIdx_MP_5GC_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 4, 6, 7, 9, 11, 13, 15, 18, 19, 22, 24, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 8, 10, 11, 13, 15, 18, 20, 23, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 4, 5, 7, 9, 11, 13, 14, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; -u1Byte gDeltaTSSITableIdx_MP_5GB_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 4, 5, 6, 7, 9, 11, 13, 15, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 6, 7, 9, 11, 13, 15, 17, 19, 22, 24, 27, 29, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; -u1Byte gDeltaTSSITableIdx_MP_5GA_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19, 22, 24, 26, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 21, 23, 26, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 5, 6, 7, 8, 9, 9, 10, 12, 13, 14, 15, 17, 20, 22, 24, 25, 29, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; -u1Byte gDeltaTSSITableIdx_MP_2GD_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GC_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GB_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GA_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GCCKD_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GCCKC_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GCCKB_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -u1Byte gDeltaTSSITableIdx_MP_2GCCKA_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTSSI( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GA, gDeltaTSSITableIdx_MP_2GA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GB, gDeltaTSSITableIdx_MP_2GB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GC, gDeltaTSSITableIdx_MP_2GC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GD, gDeltaTSSITableIdx_MP_2GD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA, gDeltaTSSITableIdx_MP_2GCCKA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB, gDeltaTSSITableIdx_MP_2GCCKB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC, gDeltaTSSITableIdx_MP_2GCCKC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD, gDeltaTSSITableIdx_MP_2GCCKD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GA, gDeltaTSSITableIdx_MP_5GA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GB, gDeltaTSSITableIdx_MP_5GB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GC, gDeltaTSSITableIdx_MP_5GC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GD, gDeltaTSSITableIdx_MP_5GD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "30", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "36", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "36", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "36", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "36", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "36", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "36", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "26", - "ETSI", "5G", "20M", "HT", "3T", "36", "28", - "MKK", "5G", "20M", "HT", "3T", "36", "28", - "FCC", "5G", "20M", "HT", "3T", "40", "26", - "ETSI", "5G", "20M", "HT", "3T", "40", "28", - "MKK", "5G", "20M", "HT", "3T", "40", "28", - "FCC", "5G", "20M", "HT", "3T", "44", "26", - "ETSI", "5G", "20M", "HT", "3T", "44", "28", - "MKK", "5G", "20M", "HT", "3T", "44", "28", - "FCC", "5G", "20M", "HT", "3T", "48", "26", - "ETSI", "5G", "20M", "HT", "3T", "48", "28", - "MKK", "5G", "20M", "HT", "3T", "48", "28", - "FCC", "5G", "20M", "HT", "3T", "52", "32", - "ETSI", "5G", "20M", "HT", "3T", "52", "28", - "MKK", "5G", "20M", "HT", "3T", "52", "28", - "FCC", "5G", "20M", "HT", "3T", "56", "30", - "ETSI", "5G", "20M", "HT", "3T", "56", "28", - "MKK", "5G", "20M", "HT", "3T", "56", "28", - "FCC", "5G", "20M", "HT", "3T", "60", "28", - "ETSI", "5G", "20M", "HT", "3T", "60", "28", - "MKK", "5G", "20M", "HT", "3T", "60", "28", - "FCC", "5G", "20M", "HT", "3T", "64", "24", - "ETSI", "5G", "20M", "HT", "3T", "64", "28", - "MKK", "5G", "20M", "HT", "3T", "64", "28", - "FCC", "5G", "20M", "HT", "3T", "100", "26", - "ETSI", "5G", "20M", "HT", "3T", "100", "28", - "MKK", "5G", "20M", "HT", "3T", "100", "28", - "FCC", "5G", "20M", "HT", "3T", "104", "26", - "ETSI", "5G", "20M", "HT", "3T", "104", "28", - "MKK", "5G", "20M", "HT", "3T", "104", "28", - "FCC", "5G", "20M", "HT", "3T", "108", "28", - "ETSI", "5G", "20M", "HT", "3T", "108", "28", - "MKK", "5G", "20M", "HT", "3T", "108", "28", - "FCC", "5G", "20M", "HT", "3T", "112", "30", - "ETSI", "5G", "20M", "HT", "3T", "112", "28", - "MKK", "5G", "20M", "HT", "3T", "112", "28", - "FCC", "5G", "20M", "HT", "3T", "116", "30", - "ETSI", "5G", "20M", "HT", "3T", "116", "28", - "MKK", "5G", "20M", "HT", "3T", "116", "28", - "FCC", "5G", "20M", "HT", "3T", "120", "32", - "ETSI", "5G", "20M", "HT", "3T", "120", "28", - "MKK", "5G", "20M", "HT", "3T", "120", "28", - "FCC", "5G", "20M", "HT", "3T", "124", "30", - "ETSI", "5G", "20M", "HT", "3T", "124", "28", - "MKK", "5G", "20M", "HT", "3T", "124", "28", - "FCC", "5G", "20M", "HT", "3T", "128", "28", - "ETSI", "5G", "20M", "HT", "3T", "128", "28", - "MKK", "5G", "20M", "HT", "3T", "128", "28", - "FCC", "5G", "20M", "HT", "3T", "132", "26", - "ETSI", "5G", "20M", "HT", "3T", "132", "28", - "MKK", "5G", "20M", "HT", "3T", "132", "28", - "FCC", "5G", "20M", "HT", "3T", "136", "26", - "ETSI", "5G", "20M", "HT", "3T", "136", "28", - "MKK", "5G", "20M", "HT", "3T", "136", "28", - "FCC", "5G", "20M", "HT", "3T", "140", "24", - "ETSI", "5G", "20M", "HT", "3T", "140", "28", - "MKK", "5G", "20M", "HT", "3T", "140", "28", - "FCC", "5G", "20M", "HT", "3T", "149", "32", - "ETSI", "5G", "20M", "HT", "3T", "149", "28", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "32", - "ETSI", "5G", "20M", "HT", "3T", "153", "28", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "32", - "ETSI", "5G", "20M", "HT", "3T", "157", "28", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "32", - "ETSI", "5G", "20M", "HT", "3T", "161", "28", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "32", - "ETSI", "5G", "20M", "HT", "3T", "165", "28", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "24", - "ETSI", "5G", "20M", "HT", "4T", "36", "26", - "MKK", "5G", "20M", "HT", "4T", "36", "26", - "FCC", "5G", "20M", "HT", "4T", "40", "24", - "ETSI", "5G", "20M", "HT", "4T", "40", "26", - "MKK", "5G", "20M", "HT", "4T", "40", "26", - "FCC", "5G", "20M", "HT", "4T", "44", "24", - "ETSI", "5G", "20M", "HT", "4T", "44", "26", - "MKK", "5G", "20M", "HT", "4T", "44", "26", - "FCC", "5G", "20M", "HT", "4T", "48", "24", - "ETSI", "5G", "20M", "HT", "4T", "48", "26", - "MKK", "5G", "20M", "HT", "4T", "48", "26", - "FCC", "5G", "20M", "HT", "4T", "52", "30", - "ETSI", "5G", "20M", "HT", "4T", "52", "26", - "MKK", "5G", "20M", "HT", "4T", "52", "26", - "FCC", "5G", "20M", "HT", "4T", "56", "28", - "ETSI", "5G", "20M", "HT", "4T", "56", "26", - "MKK", "5G", "20M", "HT", "4T", "56", "26", - "FCC", "5G", "20M", "HT", "4T", "60", "26", - "ETSI", "5G", "20M", "HT", "4T", "60", "26", - "MKK", "5G", "20M", "HT", "4T", "60", "26", - "FCC", "5G", "20M", "HT", "4T", "64", "22", - "ETSI", "5G", "20M", "HT", "4T", "64", "26", - "MKK", "5G", "20M", "HT", "4T", "64", "26", - "FCC", "5G", "20M", "HT", "4T", "100", "24", - "ETSI", "5G", "20M", "HT", "4T", "100", "26", - "MKK", "5G", "20M", "HT", "4T", "100", "26", - "FCC", "5G", "20M", "HT", "4T", "104", "24", - "ETSI", "5G", "20M", "HT", "4T", "104", "26", - "MKK", "5G", "20M", "HT", "4T", "104", "26", - "FCC", "5G", "20M", "HT", "4T", "108", "26", - "ETSI", "5G", "20M", "HT", "4T", "108", "26", - "MKK", "5G", "20M", "HT", "4T", "108", "26", - "FCC", "5G", "20M", "HT", "4T", "112", "28", - "ETSI", "5G", "20M", "HT", "4T", "112", "26", - "MKK", "5G", "20M", "HT", "4T", "112", "26", - "FCC", "5G", "20M", "HT", "4T", "116", "28", - "ETSI", "5G", "20M", "HT", "4T", "116", "26", - "MKK", "5G", "20M", "HT", "4T", "116", "26", - "FCC", "5G", "20M", "HT", "4T", "120", "30", - "ETSI", "5G", "20M", "HT", "4T", "120", "26", - "MKK", "5G", "20M", "HT", "4T", "120", "26", - "FCC", "5G", "20M", "HT", "4T", "124", "28", - "ETSI", "5G", "20M", "HT", "4T", "124", "26", - "MKK", "5G", "20M", "HT", "4T", "124", "26", - "FCC", "5G", "20M", "HT", "4T", "128", "26", - "ETSI", "5G", "20M", "HT", "4T", "128", "26", - "MKK", "5G", "20M", "HT", "4T", "128", "26", - "FCC", "5G", "20M", "HT", "4T", "132", "24", - "ETSI", "5G", "20M", "HT", "4T", "132", "26", - "MKK", "5G", "20M", "HT", "4T", "132", "26", - "FCC", "5G", "20M", "HT", "4T", "136", "24", - "ETSI", "5G", "20M", "HT", "4T", "136", "26", - "MKK", "5G", "20M", "HT", "4T", "136", "26", - "FCC", "5G", "20M", "HT", "4T", "140", "22", - "ETSI", "5G", "20M", "HT", "4T", "140", "26", - "MKK", "5G", "20M", "HT", "4T", "140", "26", - "FCC", "5G", "20M", "HT", "4T", "149", "30", - "ETSI", "5G", "20M", "HT", "4T", "149", "26", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "30", - "ETSI", "5G", "20M", "HT", "4T", "153", "26", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "30", - "ETSI", "5G", "20M", "HT", "4T", "157", "26", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "30", - "ETSI", "5G", "20M", "HT", "4T", "161", "26", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "30", - "ETSI", "5G", "20M", "HT", "4T", "165", "26", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "26", - "ETSI", "5G", "40M", "HT", "3T", "38", "28", - "MKK", "5G", "40M", "HT", "3T", "38", "28", - "FCC", "5G", "40M", "HT", "3T", "46", "26", - "ETSI", "5G", "40M", "HT", "3T", "46", "28", - "MKK", "5G", "40M", "HT", "3T", "46", "28", - "FCC", "5G", "40M", "HT", "3T", "54", "28", - "ETSI", "5G", "40M", "HT", "3T", "54", "28", - "MKK", "5G", "40M", "HT", "3T", "54", "28", - "FCC", "5G", "40M", "HT", "3T", "62", "28", - "ETSI", "5G", "40M", "HT", "3T", "62", "28", - "MKK", "5G", "40M", "HT", "3T", "62", "28", - "FCC", "5G", "40M", "HT", "3T", "102", "24", - "ETSI", "5G", "40M", "HT", "3T", "102", "28", - "MKK", "5G", "40M", "HT", "3T", "102", "28", - "FCC", "5G", "40M", "HT", "3T", "110", "28", - "ETSI", "5G", "40M", "HT", "3T", "110", "28", - "MKK", "5G", "40M", "HT", "3T", "110", "28", - "FCC", "5G", "40M", "HT", "3T", "118", "32", - "ETSI", "5G", "40M", "HT", "3T", "118", "28", - "MKK", "5G", "40M", "HT", "3T", "118", "28", - "FCC", "5G", "40M", "HT", "3T", "126", "30", - "ETSI", "5G", "40M", "HT", "3T", "126", "28", - "MKK", "5G", "40M", "HT", "3T", "126", "28", - "FCC", "5G", "40M", "HT", "3T", "134", "28", - "ETSI", "5G", "40M", "HT", "3T", "134", "28", - "MKK", "5G", "40M", "HT", "3T", "134", "28", - "FCC", "5G", "40M", "HT", "3T", "151", "32", - "ETSI", "5G", "40M", "HT", "3T", "151", "28", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "32", - "ETSI", "5G", "40M", "HT", "3T", "159", "28", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "24", - "ETSI", "5G", "40M", "HT", "4T", "38", "26", - "MKK", "5G", "40M", "HT", "4T", "38", "26", - "FCC", "5G", "40M", "HT", "4T", "46", "24", - "ETSI", "5G", "40M", "HT", "4T", "46", "26", - "MKK", "5G", "40M", "HT", "4T", "46", "26", - "FCC", "5G", "40M", "HT", "4T", "54", "26", - "ETSI", "5G", "40M", "HT", "4T", "54", "26", - "MKK", "5G", "40M", "HT", "4T", "54", "26", - "FCC", "5G", "40M", "HT", "4T", "62", "26", - "ETSI", "5G", "40M", "HT", "4T", "62", "26", - "MKK", "5G", "40M", "HT", "4T", "62", "26", - "FCC", "5G", "40M", "HT", "4T", "102", "22", - "ETSI", "5G", "40M", "HT", "4T", "102", "26", - "MKK", "5G", "40M", "HT", "4T", "102", "26", - "FCC", "5G", "40M", "HT", "4T", "110", "26", - "ETSI", "5G", "40M", "HT", "4T", "110", "26", - "MKK", "5G", "40M", "HT", "4T", "110", "26", - "FCC", "5G", "40M", "HT", "4T", "118", "30", - "ETSI", "5G", "40M", "HT", "4T", "118", "26", - "MKK", "5G", "40M", "HT", "4T", "118", "26", - "FCC", "5G", "40M", "HT", "4T", "126", "28", - "ETSI", "5G", "40M", "HT", "4T", "126", "26", - "MKK", "5G", "40M", "HT", "4T", "126", "26", - "FCC", "5G", "40M", "HT", "4T", "134", "26", - "ETSI", "5G", "40M", "HT", "4T", "134", "26", - "MKK", "5G", "40M", "HT", "4T", "134", "26", - "FCC", "5G", "40M", "HT", "4T", "151", "30", - "ETSI", "5G", "40M", "HT", "4T", "151", "26", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "30", - "ETSI", "5G", "40M", "HT", "4T", "159", "26", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "26", - "ETSI", "5G", "80M", "VHT", "3T", "42", "28", - "MKK", "5G", "80M", "VHT", "3T", "42", "28", - "FCC", "5G", "80M", "VHT", "3T", "58", "24", - "ETSI", "5G", "80M", "VHT", "3T", "58", "28", - "MKK", "5G", "80M", "VHT", "3T", "58", "28", - "FCC", "5G", "80M", "VHT", "3T", "106", "26", - "ETSI", "5G", "80M", "VHT", "3T", "106", "28", - "MKK", "5G", "80M", "VHT", "3T", "106", "28", - "FCC", "5G", "80M", "VHT", "3T", "122", "30", - "ETSI", "5G", "80M", "VHT", "3T", "122", "28", - "MKK", "5G", "80M", "VHT", "3T", "122", "28", - "FCC", "5G", "80M", "VHT", "3T", "155", "32", - "ETSI", "5G", "80M", "VHT", "3T", "155", "28", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "24", - "ETSI", "5G", "80M", "VHT", "4T", "42", "26", - "MKK", "5G", "80M", "VHT", "4T", "42", "26", - "FCC", "5G", "80M", "VHT", "4T", "58", "22", - "ETSI", "5G", "80M", "VHT", "4T", "58", "26", - "MKK", "5G", "80M", "VHT", "4T", "58", "26", - "FCC", "5G", "80M", "VHT", "4T", "106", "24", - "ETSI", "5G", "80M", "VHT", "4T", "106", "26", - "MKK", "5G", "80M", "VHT", "4T", "106", "26", - "FCC", "5G", "80M", "VHT", "4T", "122", "28", - "ETSI", "5G", "80M", "VHT", "4T", "122", "26", - "MKK", "5G", "80M", "VHT", "4T", "122", "26", - "FCC", "5G", "80M", "VHT", "4T", "155", "30", - "ETSI", "5G", "80M", "VHT", "4T", "155", "26", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type0.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type0[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "18", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "8", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "6", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "24", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "24", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "22", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "22", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "20", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "20", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "10", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "22", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "20", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "20", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "26", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "26", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "26", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "24", - "ETSI", "5G", "20M", "HT", "2T", "36", "28", - "MKK", "5G", "20M", "HT", "2T", "36", "28", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "28", - "MKK", "5G", "20M", "HT", "2T", "40", "28", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "28", - "MKK", "5G", "20M", "HT", "2T", "44", "28", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "28", - "MKK", "5G", "20M", "HT", "2T", "48", "28", - "FCC", "5G", "20M", "HT", "2T", "52", "28", - "ETSI", "5G", "20M", "HT", "2T", "52", "28", - "MKK", "5G", "20M", "HT", "2T", "52", "28", - "FCC", "5G", "20M", "HT", "2T", "56", "28", - "ETSI", "5G", "20M", "HT", "2T", "56", "28", - "MKK", "5G", "20M", "HT", "2T", "56", "28", - "FCC", "5G", "20M", "HT", "2T", "60", "28", - "ETSI", "5G", "20M", "HT", "2T", "60", "28", - "MKK", "5G", "20M", "HT", "2T", "60", "28", - "FCC", "5G", "20M", "HT", "2T", "64", "24", - "ETSI", "5G", "20M", "HT", "2T", "64", "28", - "MKK", "5G", "20M", "HT", "2T", "64", "28", - "FCC", "5G", "20M", "HT", "2T", "100", "24", - "ETSI", "5G", "20M", "HT", "2T", "100", "28", - "MKK", "5G", "20M", "HT", "2T", "100", "28", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "28", - "MKK", "5G", "20M", "HT", "2T", "104", "28", - "FCC", "5G", "20M", "HT", "2T", "108", "28", - "ETSI", "5G", "20M", "HT", "2T", "108", "28", - "MKK", "5G", "20M", "HT", "2T", "108", "28", - "FCC", "5G", "20M", "HT", "2T", "112", "28", - "ETSI", "5G", "20M", "HT", "2T", "112", "28", - "MKK", "5G", "20M", "HT", "2T", "112", "28", - "FCC", "5G", "20M", "HT", "2T", "116", "28", - "ETSI", "5G", "20M", "HT", "2T", "116", "28", - "MKK", "5G", "20M", "HT", "2T", "116", "28", - "FCC", "5G", "20M", "HT", "2T", "120", "28", - "ETSI", "5G", "20M", "HT", "2T", "120", "28", - "MKK", "5G", "20M", "HT", "2T", "120", "28", - "FCC", "5G", "20M", "HT", "2T", "124", "28", - "ETSI", "5G", "20M", "HT", "2T", "124", "28", - "MKK", "5G", "20M", "HT", "2T", "124", "28", - "FCC", "5G", "20M", "HT", "2T", "128", "28", - "ETSI", "5G", "20M", "HT", "2T", "128", "28", - "MKK", "5G", "20M", "HT", "2T", "128", "28", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "28", - "MKK", "5G", "20M", "HT", "2T", "132", "28", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "28", - "MKK", "5G", "20M", "HT", "2T", "136", "28", - "FCC", "5G", "20M", "HT", "2T", "140", "24", - "ETSI", "5G", "20M", "HT", "2T", "140", "28", - "MKK", "5G", "20M", "HT", "2T", "140", "28", - "FCC", "5G", "20M", "HT", "2T", "149", "24", - "ETSI", "5G", "20M", "HT", "2T", "149", "28", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "28", - "ETSI", "5G", "20M", "HT", "2T", "153", "28", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "28", - "ETSI", "5G", "20M", "HT", "2T", "157", "28", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "28", - "ETSI", "5G", "20M", "HT", "2T", "161", "28", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "28", - "ETSI", "5G", "20M", "HT", "2T", "165", "28", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "22", - "ETSI", "5G", "20M", "HT", "3T", "36", "26", - "MKK", "5G", "20M", "HT", "3T", "36", "26", - "FCC", "5G", "20M", "HT", "3T", "40", "26", - "ETSI", "5G", "20M", "HT", "3T", "40", "26", - "MKK", "5G", "20M", "HT", "3T", "40", "26", - "FCC", "5G", "20M", "HT", "3T", "44", "26", - "ETSI", "5G", "20M", "HT", "3T", "44", "26", - "MKK", "5G", "20M", "HT", "3T", "44", "26", - "FCC", "5G", "20M", "HT", "3T", "48", "26", - "ETSI", "5G", "20M", "HT", "3T", "48", "26", - "MKK", "5G", "20M", "HT", "3T", "48", "26", - "FCC", "5G", "20M", "HT", "3T", "52", "26", - "ETSI", "5G", "20M", "HT", "3T", "52", "26", - "MKK", "5G", "20M", "HT", "3T", "52", "26", - "FCC", "5G", "20M", "HT", "3T", "56", "26", - "ETSI", "5G", "20M", "HT", "3T", "56", "26", - "MKK", "5G", "20M", "HT", "3T", "56", "26", - "FCC", "5G", "20M", "HT", "3T", "60", "26", - "ETSI", "5G", "20M", "HT", "3T", "60", "26", - "MKK", "5G", "20M", "HT", "3T", "60", "26", - "FCC", "5G", "20M", "HT", "3T", "64", "22", - "ETSI", "5G", "20M", "HT", "3T", "64", "26", - "MKK", "5G", "20M", "HT", "3T", "64", "26", - "FCC", "5G", "20M", "HT", "3T", "100", "22", - "ETSI", "5G", "20M", "HT", "3T", "100", "26", - "MKK", "5G", "20M", "HT", "3T", "100", "26", - "FCC", "5G", "20M", "HT", "3T", "104", "26", - "ETSI", "5G", "20M", "HT", "3T", "104", "26", - "MKK", "5G", "20M", "HT", "3T", "104", "26", - "FCC", "5G", "20M", "HT", "3T", "108", "26", - "ETSI", "5G", "20M", "HT", "3T", "108", "26", - "MKK", "5G", "20M", "HT", "3T", "108", "26", - "FCC", "5G", "20M", "HT", "3T", "112", "26", - "ETSI", "5G", "20M", "HT", "3T", "112", "26", - "MKK", "5G", "20M", "HT", "3T", "112", "26", - "FCC", "5G", "20M", "HT", "3T", "116", "26", - "ETSI", "5G", "20M", "HT", "3T", "116", "26", - "MKK", "5G", "20M", "HT", "3T", "116", "26", - "FCC", "5G", "20M", "HT", "3T", "120", "26", - "ETSI", "5G", "20M", "HT", "3T", "120", "26", - "MKK", "5G", "20M", "HT", "3T", "120", "26", - "FCC", "5G", "20M", "HT", "3T", "124", "26", - "ETSI", "5G", "20M", "HT", "3T", "124", "26", - "MKK", "5G", "20M", "HT", "3T", "124", "26", - "FCC", "5G", "20M", "HT", "3T", "128", "26", - "ETSI", "5G", "20M", "HT", "3T", "128", "26", - "MKK", "5G", "20M", "HT", "3T", "128", "26", - "FCC", "5G", "20M", "HT", "3T", "132", "26", - "ETSI", "5G", "20M", "HT", "3T", "132", "26", - "MKK", "5G", "20M", "HT", "3T", "132", "26", - "FCC", "5G", "20M", "HT", "3T", "136", "26", - "ETSI", "5G", "20M", "HT", "3T", "136", "26", - "MKK", "5G", "20M", "HT", "3T", "136", "26", - "FCC", "5G", "20M", "HT", "3T", "140", "22", - "ETSI", "5G", "20M", "HT", "3T", "140", "26", - "MKK", "5G", "20M", "HT", "3T", "140", "26", - "FCC", "5G", "20M", "HT", "3T", "149", "22", - "ETSI", "5G", "20M", "HT", "3T", "149", "26", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "26", - "ETSI", "5G", "20M", "HT", "3T", "153", "26", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "26", - "ETSI", "5G", "20M", "HT", "3T", "157", "26", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "26", - "ETSI", "5G", "20M", "HT", "3T", "161", "26", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "26", - "ETSI", "5G", "20M", "HT", "3T", "165", "26", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "20", - "ETSI", "5G", "20M", "HT", "4T", "36", "24", - "MKK", "5G", "20M", "HT", "4T", "36", "24", - "FCC", "5G", "20M", "HT", "4T", "40", "24", - "ETSI", "5G", "20M", "HT", "4T", "40", "24", - "MKK", "5G", "20M", "HT", "4T", "40", "24", - "FCC", "5G", "20M", "HT", "4T", "44", "24", - "ETSI", "5G", "20M", "HT", "4T", "44", "24", - "MKK", "5G", "20M", "HT", "4T", "44", "24", - "FCC", "5G", "20M", "HT", "4T", "48", "24", - "ETSI", "5G", "20M", "HT", "4T", "48", "24", - "MKK", "5G", "20M", "HT", "4T", "48", "24", - "FCC", "5G", "20M", "HT", "4T", "52", "24", - "ETSI", "5G", "20M", "HT", "4T", "52", "24", - "MKK", "5G", "20M", "HT", "4T", "52", "24", - "FCC", "5G", "20M", "HT", "4T", "56", "24", - "ETSI", "5G", "20M", "HT", "4T", "56", "24", - "MKK", "5G", "20M", "HT", "4T", "56", "24", - "FCC", "5G", "20M", "HT", "4T", "60", "24", - "ETSI", "5G", "20M", "HT", "4T", "60", "24", - "MKK", "5G", "20M", "HT", "4T", "60", "24", - "FCC", "5G", "20M", "HT", "4T", "64", "20", - "ETSI", "5G", "20M", "HT", "4T", "64", "24", - "MKK", "5G", "20M", "HT", "4T", "64", "24", - "FCC", "5G", "20M", "HT", "4T", "100", "20", - "ETSI", "5G", "20M", "HT", "4T", "100", "24", - "MKK", "5G", "20M", "HT", "4T", "100", "24", - "FCC", "5G", "20M", "HT", "4T", "104", "24", - "ETSI", "5G", "20M", "HT", "4T", "104", "24", - "MKK", "5G", "20M", "HT", "4T", "104", "24", - "FCC", "5G", "20M", "HT", "4T", "108", "24", - "ETSI", "5G", "20M", "HT", "4T", "108", "24", - "MKK", "5G", "20M", "HT", "4T", "108", "24", - "FCC", "5G", "20M", "HT", "4T", "112", "24", - "ETSI", "5G", "20M", "HT", "4T", "112", "24", - "MKK", "5G", "20M", "HT", "4T", "112", "24", - "FCC", "5G", "20M", "HT", "4T", "116", "24", - "ETSI", "5G", "20M", "HT", "4T", "116", "24", - "MKK", "5G", "20M", "HT", "4T", "116", "24", - "FCC", "5G", "20M", "HT", "4T", "120", "24", - "ETSI", "5G", "20M", "HT", "4T", "120", "24", - "MKK", "5G", "20M", "HT", "4T", "120", "24", - "FCC", "5G", "20M", "HT", "4T", "124", "24", - "ETSI", "5G", "20M", "HT", "4T", "124", "24", - "MKK", "5G", "20M", "HT", "4T", "124", "24", - "FCC", "5G", "20M", "HT", "4T", "128", "24", - "ETSI", "5G", "20M", "HT", "4T", "128", "24", - "MKK", "5G", "20M", "HT", "4T", "128", "24", - "FCC", "5G", "20M", "HT", "4T", "132", "24", - "ETSI", "5G", "20M", "HT", "4T", "132", "24", - "MKK", "5G", "20M", "HT", "4T", "132", "24", - "FCC", "5G", "20M", "HT", "4T", "136", "24", - "ETSI", "5G", "20M", "HT", "4T", "136", "24", - "MKK", "5G", "20M", "HT", "4T", "136", "24", - "FCC", "5G", "20M", "HT", "4T", "140", "20", - "ETSI", "5G", "20M", "HT", "4T", "140", "24", - "MKK", "5G", "20M", "HT", "4T", "140", "24", - "FCC", "5G", "20M", "HT", "4T", "149", "20", - "ETSI", "5G", "20M", "HT", "4T", "149", "24", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "24", - "ETSI", "5G", "20M", "HT", "4T", "153", "24", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "24", - "ETSI", "5G", "20M", "HT", "4T", "157", "24", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "24", - "ETSI", "5G", "20M", "HT", "4T", "161", "24", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "24", - "ETSI", "5G", "20M", "HT", "4T", "165", "24", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "26", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "26", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "26", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "24", - "ETSI", "5G", "40M", "HT", "2T", "38", "28", - "MKK", "5G", "40M", "HT", "2T", "38", "28", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "28", - "MKK", "5G", "40M", "HT", "2T", "46", "28", - "FCC", "5G", "40M", "HT", "2T", "54", "28", - "ETSI", "5G", "40M", "HT", "2T", "54", "28", - "MKK", "5G", "40M", "HT", "2T", "54", "28", - "FCC", "5G", "40M", "HT", "2T", "62", "24", - "ETSI", "5G", "40M", "HT", "2T", "62", "28", - "MKK", "5G", "40M", "HT", "2T", "62", "28", - "FCC", "5G", "40M", "HT", "2T", "102", "24", - "ETSI", "5G", "40M", "HT", "2T", "102", "28", - "MKK", "5G", "40M", "HT", "2T", "102", "28", - "FCC", "5G", "40M", "HT", "2T", "110", "28", - "ETSI", "5G", "40M", "HT", "2T", "110", "28", - "MKK", "5G", "40M", "HT", "2T", "110", "28", - "FCC", "5G", "40M", "HT", "2T", "118", "28", - "ETSI", "5G", "40M", "HT", "2T", "118", "28", - "MKK", "5G", "40M", "HT", "2T", "118", "28", - "FCC", "5G", "40M", "HT", "2T", "126", "28", - "ETSI", "5G", "40M", "HT", "2T", "126", "28", - "MKK", "5G", "40M", "HT", "2T", "126", "28", - "FCC", "5G", "40M", "HT", "2T", "134", "28", - "ETSI", "5G", "40M", "HT", "2T", "134", "28", - "MKK", "5G", "40M", "HT", "2T", "134", "28", - "FCC", "5G", "40M", "HT", "2T", "151", "24", - "ETSI", "5G", "40M", "HT", "2T", "151", "28", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "28", - "ETSI", "5G", "40M", "HT", "2T", "159", "28", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "20", - "ETSI", "5G", "40M", "HT", "3T", "38", "26", - "MKK", "5G", "40M", "HT", "3T", "38", "26", - "FCC", "5G", "40M", "HT", "3T", "46", "26", - "ETSI", "5G", "40M", "HT", "3T", "46", "26", - "MKK", "5G", "40M", "HT", "3T", "46", "26", - "FCC", "5G", "40M", "HT", "3T", "54", "26", - "ETSI", "5G", "40M", "HT", "3T", "54", "26", - "MKK", "5G", "40M", "HT", "3T", "54", "26", - "FCC", "5G", "40M", "HT", "3T", "62", "20", - "ETSI", "5G", "40M", "HT", "3T", "62", "26", - "MKK", "5G", "40M", "HT", "3T", "62", "26", - "FCC", "5G", "40M", "HT", "3T", "102", "20", - "ETSI", "5G", "40M", "HT", "3T", "102", "26", - "MKK", "5G", "40M", "HT", "3T", "102", "26", - "FCC", "5G", "40M", "HT", "3T", "110", "26", - "ETSI", "5G", "40M", "HT", "3T", "110", "26", - "MKK", "5G", "40M", "HT", "3T", "110", "26", - "FCC", "5G", "40M", "HT", "3T", "118", "26", - "ETSI", "5G", "40M", "HT", "3T", "118", "26", - "MKK", "5G", "40M", "HT", "3T", "118", "26", - "FCC", "5G", "40M", "HT", "3T", "126", "26", - "ETSI", "5G", "40M", "HT", "3T", "126", "26", - "MKK", "5G", "40M", "HT", "3T", "126", "26", - "FCC", "5G", "40M", "HT", "3T", "134", "26", - "ETSI", "5G", "40M", "HT", "3T", "134", "26", - "MKK", "5G", "40M", "HT", "3T", "134", "26", - "FCC", "5G", "40M", "HT", "3T", "151", "20", - "ETSI", "5G", "40M", "HT", "3T", "151", "26", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "26", - "ETSI", "5G", "40M", "HT", "3T", "159", "26", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "18", - "ETSI", "5G", "40M", "HT", "4T", "38", "24", - "MKK", "5G", "40M", "HT", "4T", "38", "24", - "FCC", "5G", "40M", "HT", "4T", "46", "24", - "ETSI", "5G", "40M", "HT", "4T", "46", "24", - "MKK", "5G", "40M", "HT", "4T", "46", "24", - "FCC", "5G", "40M", "HT", "4T", "54", "24", - "ETSI", "5G", "40M", "HT", "4T", "54", "24", - "MKK", "5G", "40M", "HT", "4T", "54", "24", - "FCC", "5G", "40M", "HT", "4T", "62", "18", - "ETSI", "5G", "40M", "HT", "4T", "62", "24", - "MKK", "5G", "40M", "HT", "4T", "62", "24", - "FCC", "5G", "40M", "HT", "4T", "102", "18", - "ETSI", "5G", "40M", "HT", "4T", "102", "24", - "MKK", "5G", "40M", "HT", "4T", "102", "24", - "FCC", "5G", "40M", "HT", "4T", "110", "24", - "ETSI", "5G", "40M", "HT", "4T", "110", "24", - "MKK", "5G", "40M", "HT", "4T", "110", "24", - "FCC", "5G", "40M", "HT", "4T", "118", "24", - "ETSI", "5G", "40M", "HT", "4T", "118", "24", - "MKK", "5G", "40M", "HT", "4T", "118", "24", - "FCC", "5G", "40M", "HT", "4T", "126", "24", - "ETSI", "5G", "40M", "HT", "4T", "126", "24", - "MKK", "5G", "40M", "HT", "4T", "126", "24", - "FCC", "5G", "40M", "HT", "4T", "134", "24", - "ETSI", "5G", "40M", "HT", "4T", "134", "24", - "MKK", "5G", "40M", "HT", "4T", "134", "24", - "FCC", "5G", "40M", "HT", "4T", "151", "18", - "ETSI", "5G", "40M", "HT", "4T", "151", "24", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "24", - "ETSI", "5G", "40M", "HT", "4T", "159", "24", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "22", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "22", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "22", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "20", - "ETSI", "5G", "80M", "VHT", "2T", "42", "28", - "MKK", "5G", "80M", "VHT", "2T", "42", "28", - "FCC", "5G", "80M", "VHT", "2T", "58", "20", - "ETSI", "5G", "80M", "VHT", "2T", "58", "28", - "MKK", "5G", "80M", "VHT", "2T", "58", "28", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "28", - "MKK", "5G", "80M", "VHT", "2T", "106", "28", - "FCC", "5G", "80M", "VHT", "2T", "122", "28", - "ETSI", "5G", "80M", "VHT", "2T", "122", "28", - "MKK", "5G", "80M", "VHT", "2T", "122", "28", - "FCC", "5G", "80M", "VHT", "2T", "155", "20", - "ETSI", "5G", "80M", "VHT", "2T", "155", "28", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "18", - "ETSI", "5G", "80M", "VHT", "3T", "42", "26", - "MKK", "5G", "80M", "VHT", "3T", "42", "26", - "FCC", "5G", "80M", "VHT", "3T", "58", "18", - "ETSI", "5G", "80M", "VHT", "3T", "58", "26", - "MKK", "5G", "80M", "VHT", "3T", "58", "26", - "FCC", "5G", "80M", "VHT", "3T", "106", "18", - "ETSI", "5G", "80M", "VHT", "3T", "106", "26", - "MKK", "5G", "80M", "VHT", "3T", "106", "26", - "FCC", "5G", "80M", "VHT", "3T", "122", "26", - "ETSI", "5G", "80M", "VHT", "3T", "122", "26", - "MKK", "5G", "80M", "VHT", "3T", "122", "26", - "FCC", "5G", "80M", "VHT", "3T", "155", "18", - "ETSI", "5G", "80M", "VHT", "3T", "155", "26", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "16", - "ETSI", "5G", "80M", "VHT", "4T", "42", "24", - "MKK", "5G", "80M", "VHT", "4T", "42", "24", - "FCC", "5G", "80M", "VHT", "4T", "58", "16", - "ETSI", "5G", "80M", "VHT", "4T", "58", "24", - "MKK", "5G", "80M", "VHT", "4T", "58", "24", - "FCC", "5G", "80M", "VHT", "4T", "106", "16", - "ETSI", "5G", "80M", "VHT", "4T", "106", "24", - "MKK", "5G", "80M", "VHT", "4T", "106", "24", - "FCC", "5G", "80M", "VHT", "4T", "122", "24", - "ETSI", "5G", "80M", "VHT", "4T", "122", "24", - "MKK", "5G", "80M", "VHT", "4T", "122", "24", - "FCC", "5G", "80M", "VHT", "4T", "155", "16", - "ETSI", "5G", "80M", "VHT", "4T", "155", "24", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type0)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type0; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type0)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type0; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type1.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type1[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "18", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "8", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "6", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "24", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "24", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "22", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "22", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "10", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "24", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "22", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "28", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "30", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "28", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "28", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "26", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "30", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "30", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "30", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "30", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "30", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "26", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "30", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "30", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "30", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "30", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "24", - "ETSI", "5G", "20M", "HT", "3T", "36", "28", - "MKK", "5G", "20M", "HT", "3T", "36", "28", - "FCC", "5G", "20M", "HT", "3T", "40", "28", - "ETSI", "5G", "20M", "HT", "3T", "40", "28", - "MKK", "5G", "20M", "HT", "3T", "40", "28", - "FCC", "5G", "20M", "HT", "3T", "44", "28", - "ETSI", "5G", "20M", "HT", "3T", "44", "28", - "MKK", "5G", "20M", "HT", "3T", "44", "28", - "FCC", "5G", "20M", "HT", "3T", "48", "28", - "ETSI", "5G", "20M", "HT", "3T", "48", "28", - "MKK", "5G", "20M", "HT", "3T", "48", "28", - "FCC", "5G", "20M", "HT", "3T", "52", "28", - "ETSI", "5G", "20M", "HT", "3T", "52", "28", - "MKK", "5G", "20M", "HT", "3T", "52", "28", - "FCC", "5G", "20M", "HT", "3T", "56", "28", - "ETSI", "5G", "20M", "HT", "3T", "56", "28", - "MKK", "5G", "20M", "HT", "3T", "56", "28", - "FCC", "5G", "20M", "HT", "3T", "60", "28", - "ETSI", "5G", "20M", "HT", "3T", "60", "28", - "MKK", "5G", "20M", "HT", "3T", "60", "28", - "FCC", "5G", "20M", "HT", "3T", "64", "26", - "ETSI", "5G", "20M", "HT", "3T", "64", "28", - "MKK", "5G", "20M", "HT", "3T", "64", "28", - "FCC", "5G", "20M", "HT", "3T", "100", "24", - "ETSI", "5G", "20M", "HT", "3T", "100", "28", - "MKK", "5G", "20M", "HT", "3T", "100", "28", - "FCC", "5G", "20M", "HT", "3T", "104", "28", - "ETSI", "5G", "20M", "HT", "3T", "104", "28", - "MKK", "5G", "20M", "HT", "3T", "104", "28", - "FCC", "5G", "20M", "HT", "3T", "108", "28", - "ETSI", "5G", "20M", "HT", "3T", "108", "28", - "MKK", "5G", "20M", "HT", "3T", "108", "28", - "FCC", "5G", "20M", "HT", "3T", "112", "28", - "ETSI", "5G", "20M", "HT", "3T", "112", "28", - "MKK", "5G", "20M", "HT", "3T", "112", "28", - "FCC", "5G", "20M", "HT", "3T", "116", "28", - "ETSI", "5G", "20M", "HT", "3T", "116", "28", - "MKK", "5G", "20M", "HT", "3T", "116", "28", - "FCC", "5G", "20M", "HT", "3T", "120", "28", - "ETSI", "5G", "20M", "HT", "3T", "120", "28", - "MKK", "5G", "20M", "HT", "3T", "120", "28", - "FCC", "5G", "20M", "HT", "3T", "124", "28", - "ETSI", "5G", "20M", "HT", "3T", "124", "28", - "MKK", "5G", "20M", "HT", "3T", "124", "28", - "FCC", "5G", "20M", "HT", "3T", "128", "28", - "ETSI", "5G", "20M", "HT", "3T", "128", "28", - "MKK", "5G", "20M", "HT", "3T", "128", "28", - "FCC", "5G", "20M", "HT", "3T", "132", "28", - "ETSI", "5G", "20M", "HT", "3T", "132", "28", - "MKK", "5G", "20M", "HT", "3T", "132", "28", - "FCC", "5G", "20M", "HT", "3T", "136", "28", - "ETSI", "5G", "20M", "HT", "3T", "136", "28", - "MKK", "5G", "20M", "HT", "3T", "136", "28", - "FCC", "5G", "20M", "HT", "3T", "140", "24", - "ETSI", "5G", "20M", "HT", "3T", "140", "28", - "MKK", "5G", "20M", "HT", "3T", "140", "28", - "FCC", "5G", "20M", "HT", "3T", "149", "24", - "ETSI", "5G", "20M", "HT", "3T", "149", "28", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "28", - "ETSI", "5G", "20M", "HT", "3T", "153", "28", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "28", - "ETSI", "5G", "20M", "HT", "3T", "157", "28", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "28", - "ETSI", "5G", "20M", "HT", "3T", "161", "28", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "28", - "ETSI", "5G", "20M", "HT", "3T", "165", "28", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "22", - "ETSI", "5G", "20M", "HT", "4T", "36", "26", - "MKK", "5G", "20M", "HT", "4T", "36", "26", - "FCC", "5G", "20M", "HT", "4T", "40", "26", - "ETSI", "5G", "20M", "HT", "4T", "40", "26", - "MKK", "5G", "20M", "HT", "4T", "40", "26", - "FCC", "5G", "20M", "HT", "4T", "44", "26", - "ETSI", "5G", "20M", "HT", "4T", "44", "26", - "MKK", "5G", "20M", "HT", "4T", "44", "26", - "FCC", "5G", "20M", "HT", "4T", "48", "26", - "ETSI", "5G", "20M", "HT", "4T", "48", "26", - "MKK", "5G", "20M", "HT", "4T", "48", "26", - "FCC", "5G", "20M", "HT", "4T", "52", "26", - "ETSI", "5G", "20M", "HT", "4T", "52", "26", - "MKK", "5G", "20M", "HT", "4T", "52", "26", - "FCC", "5G", "20M", "HT", "4T", "56", "26", - "ETSI", "5G", "20M", "HT", "4T", "56", "26", - "MKK", "5G", "20M", "HT", "4T", "56", "26", - "FCC", "5G", "20M", "HT", "4T", "60", "26", - "ETSI", "5G", "20M", "HT", "4T", "60", "26", - "MKK", "5G", "20M", "HT", "4T", "60", "26", - "FCC", "5G", "20M", "HT", "4T", "64", "24", - "ETSI", "5G", "20M", "HT", "4T", "64", "26", - "MKK", "5G", "20M", "HT", "4T", "64", "26", - "FCC", "5G", "20M", "HT", "4T", "100", "22", - "ETSI", "5G", "20M", "HT", "4T", "100", "26", - "MKK", "5G", "20M", "HT", "4T", "100", "26", - "FCC", "5G", "20M", "HT", "4T", "104", "26", - "ETSI", "5G", "20M", "HT", "4T", "104", "26", - "MKK", "5G", "20M", "HT", "4T", "104", "26", - "FCC", "5G", "20M", "HT", "4T", "108", "26", - "ETSI", "5G", "20M", "HT", "4T", "108", "26", - "MKK", "5G", "20M", "HT", "4T", "108", "26", - "FCC", "5G", "20M", "HT", "4T", "112", "26", - "ETSI", "5G", "20M", "HT", "4T", "112", "26", - "MKK", "5G", "20M", "HT", "4T", "112", "26", - "FCC", "5G", "20M", "HT", "4T", "116", "26", - "ETSI", "5G", "20M", "HT", "4T", "116", "26", - "MKK", "5G", "20M", "HT", "4T", "116", "26", - "FCC", "5G", "20M", "HT", "4T", "120", "26", - "ETSI", "5G", "20M", "HT", "4T", "120", "26", - "MKK", "5G", "20M", "HT", "4T", "120", "26", - "FCC", "5G", "20M", "HT", "4T", "124", "26", - "ETSI", "5G", "20M", "HT", "4T", "124", "26", - "MKK", "5G", "20M", "HT", "4T", "124", "26", - "FCC", "5G", "20M", "HT", "4T", "128", "26", - "ETSI", "5G", "20M", "HT", "4T", "128", "26", - "MKK", "5G", "20M", "HT", "4T", "128", "26", - "FCC", "5G", "20M", "HT", "4T", "132", "26", - "ETSI", "5G", "20M", "HT", "4T", "132", "26", - "MKK", "5G", "20M", "HT", "4T", "132", "26", - "FCC", "5G", "20M", "HT", "4T", "136", "26", - "ETSI", "5G", "20M", "HT", "4T", "136", "26", - "MKK", "5G", "20M", "HT", "4T", "136", "26", - "FCC", "5G", "20M", "HT", "4T", "140", "22", - "ETSI", "5G", "20M", "HT", "4T", "140", "26", - "MKK", "5G", "20M", "HT", "4T", "140", "26", - "FCC", "5G", "20M", "HT", "4T", "149", "22", - "ETSI", "5G", "20M", "HT", "4T", "149", "26", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "26", - "ETSI", "5G", "20M", "HT", "4T", "153", "26", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "26", - "ETSI", "5G", "20M", "HT", "4T", "157", "26", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "26", - "ETSI", "5G", "20M", "HT", "4T", "161", "26", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "26", - "ETSI", "5G", "20M", "HT", "4T", "165", "26", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "28", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "28", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "28", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "26", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "26", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "28", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "26", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "20", - "ETSI", "5G", "40M", "HT", "3T", "38", "28", - "MKK", "5G", "40M", "HT", "3T", "38", "28", - "FCC", "5G", "40M", "HT", "3T", "46", "28", - "ETSI", "5G", "40M", "HT", "3T", "46", "28", - "MKK", "5G", "40M", "HT", "3T", "46", "28", - "FCC", "5G", "40M", "HT", "3T", "54", "28", - "ETSI", "5G", "40M", "HT", "3T", "54", "28", - "MKK", "5G", "40M", "HT", "3T", "54", "28", - "FCC", "5G", "40M", "HT", "3T", "62", "20", - "ETSI", "5G", "40M", "HT", "3T", "62", "28", - "MKK", "5G", "40M", "HT", "3T", "62", "28", - "FCC", "5G", "40M", "HT", "3T", "102", "22", - "ETSI", "5G", "40M", "HT", "3T", "102", "28", - "MKK", "5G", "40M", "HT", "3T", "102", "28", - "FCC", "5G", "40M", "HT", "3T", "110", "28", - "ETSI", "5G", "40M", "HT", "3T", "110", "28", - "MKK", "5G", "40M", "HT", "3T", "110", "28", - "FCC", "5G", "40M", "HT", "3T", "118", "28", - "ETSI", "5G", "40M", "HT", "3T", "118", "28", - "MKK", "5G", "40M", "HT", "3T", "118", "28", - "FCC", "5G", "40M", "HT", "3T", "126", "28", - "ETSI", "5G", "40M", "HT", "3T", "126", "28", - "MKK", "5G", "40M", "HT", "3T", "126", "28", - "FCC", "5G", "40M", "HT", "3T", "134", "26", - "ETSI", "5G", "40M", "HT", "3T", "134", "28", - "MKK", "5G", "40M", "HT", "3T", "134", "28", - "FCC", "5G", "40M", "HT", "3T", "151", "22", - "ETSI", "5G", "40M", "HT", "3T", "151", "28", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "28", - "ETSI", "5G", "40M", "HT", "3T", "159", "28", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "18", - "ETSI", "5G", "40M", "HT", "4T", "38", "26", - "MKK", "5G", "40M", "HT", "4T", "38", "26", - "FCC", "5G", "40M", "HT", "4T", "46", "26", - "ETSI", "5G", "40M", "HT", "4T", "46", "26", - "MKK", "5G", "40M", "HT", "4T", "46", "26", - "FCC", "5G", "40M", "HT", "4T", "54", "26", - "ETSI", "5G", "40M", "HT", "4T", "54", "26", - "MKK", "5G", "40M", "HT", "4T", "54", "26", - "FCC", "5G", "40M", "HT", "4T", "62", "18", - "ETSI", "5G", "40M", "HT", "4T", "62", "26", - "MKK", "5G", "40M", "HT", "4T", "62", "26", - "FCC", "5G", "40M", "HT", "4T", "102", "20", - "ETSI", "5G", "40M", "HT", "4T", "102", "26", - "MKK", "5G", "40M", "HT", "4T", "102", "26", - "FCC", "5G", "40M", "HT", "4T", "110", "26", - "ETSI", "5G", "40M", "HT", "4T", "110", "26", - "MKK", "5G", "40M", "HT", "4T", "110", "26", - "FCC", "5G", "40M", "HT", "4T", "118", "26", - "ETSI", "5G", "40M", "HT", "4T", "118", "26", - "MKK", "5G", "40M", "HT", "4T", "118", "26", - "FCC", "5G", "40M", "HT", "4T", "126", "26", - "ETSI", "5G", "40M", "HT", "4T", "126", "26", - "MKK", "5G", "40M", "HT", "4T", "126", "26", - "FCC", "5G", "40M", "HT", "4T", "134", "24", - "ETSI", "5G", "40M", "HT", "4T", "134", "26", - "MKK", "5G", "40M", "HT", "4T", "134", "26", - "FCC", "5G", "40M", "HT", "4T", "151", "20", - "ETSI", "5G", "40M", "HT", "4T", "151", "26", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "26", - "ETSI", "5G", "40M", "HT", "4T", "159", "26", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "24", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "24", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "24", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "32", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "26", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "22", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "22", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "22", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "24", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "20", - "ETSI", "5G", "80M", "VHT", "3T", "42", "28", - "MKK", "5G", "80M", "VHT", "3T", "42", "28", - "FCC", "5G", "80M", "VHT", "3T", "58", "20", - "ETSI", "5G", "80M", "VHT", "3T", "58", "28", - "MKK", "5G", "80M", "VHT", "3T", "58", "28", - "FCC", "5G", "80M", "VHT", "3T", "106", "20", - "ETSI", "5G", "80M", "VHT", "3T", "106", "28", - "MKK", "5G", "80M", "VHT", "3T", "106", "28", - "FCC", "5G", "80M", "VHT", "3T", "122", "28", - "ETSI", "5G", "80M", "VHT", "3T", "122", "28", - "MKK", "5G", "80M", "VHT", "3T", "122", "28", - "FCC", "5G", "80M", "VHT", "3T", "155", "20", - "ETSI", "5G", "80M", "VHT", "3T", "155", "28", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "18", - "ETSI", "5G", "80M", "VHT", "4T", "42", "26", - "MKK", "5G", "80M", "VHT", "4T", "42", "26", - "FCC", "5G", "80M", "VHT", "4T", "58", "18", - "ETSI", "5G", "80M", "VHT", "4T", "58", "26", - "MKK", "5G", "80M", "VHT", "4T", "58", "26", - "FCC", "5G", "80M", "VHT", "4T", "106", "18", - "ETSI", "5G", "80M", "VHT", "4T", "106", "26", - "MKK", "5G", "80M", "VHT", "4T", "106", "26", - "FCC", "5G", "80M", "VHT", "4T", "122", "26", - "ETSI", "5G", "80M", "VHT", "4T", "122", "26", - "MKK", "5G", "80M", "VHT", "4T", "122", "26", - "FCC", "5G", "80M", "VHT", "4T", "155", "18", - "ETSI", "5G", "80M", "VHT", "4T", "155", "26", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type1)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type1; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type1)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type1; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type2.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type2[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "42", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "42", - "MKK", "2.4G", "20M", "HT", "1T", "01", "42", - "FCC", "2.4G", "20M", "HT", "1T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "42", - "MKK", "2.4G", "20M", "HT", "1T", "02", "42", - "FCC", "2.4G", "20M", "HT", "1T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "42", - "MKK", "2.4G", "20M", "HT", "1T", "03", "42", - "FCC", "2.4G", "20M", "HT", "1T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "42", - "MKK", "2.4G", "20M", "HT", "1T", "04", "42", - "FCC", "2.4G", "20M", "HT", "1T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "42", - "MKK", "2.4G", "20M", "HT", "1T", "05", "42", - "FCC", "2.4G", "20M", "HT", "1T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "42", - "MKK", "2.4G", "20M", "HT", "1T", "06", "42", - "FCC", "2.4G", "20M", "HT", "1T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "42", - "MKK", "2.4G", "20M", "HT", "1T", "07", "42", - "FCC", "2.4G", "20M", "HT", "1T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "42", - "MKK", "2.4G", "20M", "HT", "1T", "08", "42", - "FCC", "2.4G", "20M", "HT", "1T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "42", - "MKK", "2.4G", "20M", "HT", "1T", "09", "42", - "FCC", "2.4G", "20M", "HT", "1T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "42", - "MKK", "2.4G", "20M", "HT", "1T", "10", "42", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "42", - "MKK", "2.4G", "20M", "HT", "1T", "11", "42", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "42", - "MKK", "2.4G", "20M", "HT", "1T", "12", "42", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "42", - "MKK", "2.4G", "20M", "HT", "1T", "13", "42", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", - "MKK", "2.4G", "20M", "HT", "2T", "01", "40", - "FCC", "2.4G", "20M", "HT", "2T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", - "MKK", "2.4G", "20M", "HT", "2T", "02", "40", - "FCC", "2.4G", "20M", "HT", "2T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", - "MKK", "2.4G", "20M", "HT", "2T", "03", "40", - "FCC", "2.4G", "20M", "HT", "2T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", - "MKK", "2.4G", "20M", "HT", "2T", "04", "40", - "FCC", "2.4G", "20M", "HT", "2T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", - "MKK", "2.4G", "20M", "HT", "2T", "05", "40", - "FCC", "2.4G", "20M", "HT", "2T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", - "MKK", "2.4G", "20M", "HT", "2T", "06", "40", - "FCC", "2.4G", "20M", "HT", "2T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", - "MKK", "2.4G", "20M", "HT", "2T", "07", "40", - "FCC", "2.4G", "20M", "HT", "2T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", - "MKK", "2.4G", "20M", "HT", "2T", "08", "40", - "FCC", "2.4G", "20M", "HT", "2T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", - "MKK", "2.4G", "20M", "HT", "2T", "09", "40", - "FCC", "2.4G", "20M", "HT", "2T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", - "MKK", "2.4G", "20M", "HT", "2T", "10", "40", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", - "MKK", "2.4G", "20M", "HT", "2T", "11", "40", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", - "MKK", "2.4G", "20M", "HT", "2T", "12", "40", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", - "MKK", "2.4G", "20M", "HT", "2T", "13", "40", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", - "MKK", "2.4G", "20M", "HT", "3T", "01", "40", - "FCC", "2.4G", "20M", "HT", "3T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", - "MKK", "2.4G", "20M", "HT", "3T", "02", "40", - "FCC", "2.4G", "20M", "HT", "3T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", - "MKK", "2.4G", "20M", "HT", "3T", "03", "40", - "FCC", "2.4G", "20M", "HT", "3T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", - "MKK", "2.4G", "20M", "HT", "3T", "04", "40", - "FCC", "2.4G", "20M", "HT", "3T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", - "MKK", "2.4G", "20M", "HT", "3T", "05", "40", - "FCC", "2.4G", "20M", "HT", "3T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", - "MKK", "2.4G", "20M", "HT", "3T", "06", "40", - "FCC", "2.4G", "20M", "HT", "3T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", - "MKK", "2.4G", "20M", "HT", "3T", "07", "40", - "FCC", "2.4G", "20M", "HT", "3T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", - "MKK", "2.4G", "20M", "HT", "3T", "08", "40", - "FCC", "2.4G", "20M", "HT", "3T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", - "MKK", "2.4G", "20M", "HT", "3T", "09", "40", - "FCC", "2.4G", "20M", "HT", "3T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", - "MKK", "2.4G", "20M", "HT", "3T", "10", "40", - "FCC", "2.4G", "20M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", - "MKK", "2.4G", "20M", "HT", "3T", "11", "40", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", - "MKK", "2.4G", "20M", "HT", "3T", "12", "40", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", - "MKK", "2.4G", "20M", "HT", "3T", "13", "40", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", - "MKK", "2.4G", "20M", "HT", "4T", "01", "40", - "FCC", "2.4G", "20M", "HT", "4T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", - "MKK", "2.4G", "20M", "HT", "4T", "02", "40", - "FCC", "2.4G", "20M", "HT", "4T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", - "MKK", "2.4G", "20M", "HT", "4T", "03", "40", - "FCC", "2.4G", "20M", "HT", "4T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", - "MKK", "2.4G", "20M", "HT", "4T", "04", "40", - "FCC", "2.4G", "20M", "HT", "4T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", - "MKK", "2.4G", "20M", "HT", "4T", "05", "40", - "FCC", "2.4G", "20M", "HT", "4T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", - "MKK", "2.4G", "20M", "HT", "4T", "06", "40", - "FCC", "2.4G", "20M", "HT", "4T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", - "MKK", "2.4G", "20M", "HT", "4T", "07", "40", - "FCC", "2.4G", "20M", "HT", "4T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", - "MKK", "2.4G", "20M", "HT", "4T", "08", "40", - "FCC", "2.4G", "20M", "HT", "4T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", - "MKK", "2.4G", "20M", "HT", "4T", "09", "40", - "FCC", "2.4G", "20M", "HT", "4T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", - "MKK", "2.4G", "20M", "HT", "4T", "10", "40", - "FCC", "2.4G", "20M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", - "MKK", "2.4G", "20M", "HT", "4T", "11", "40", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", - "MKK", "2.4G", "20M", "HT", "4T", "12", "40", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", - "MKK", "2.4G", "20M", "HT", "4T", "13", "40", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", - "MKK", "2.4G", "40M", "HT", "1T", "12", "34", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", - "MKK", "2.4G", "40M", "HT", "1T", "13", "34", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "34", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "34", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "34", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "34", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", - "MKK", "2.4G", "40M", "HT", "2T", "12", "34", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", - "MKK", "2.4G", "40M", "HT", "2T", "13", "34", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", - "MKK", "2.4G", "40M", "HT", "3T", "03", "34", - "FCC", "2.4G", "40M", "HT", "3T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", - "MKK", "2.4G", "40M", "HT", "3T", "04", "34", - "FCC", "2.4G", "40M", "HT", "3T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", - "MKK", "2.4G", "40M", "HT", "3T", "05", "34", - "FCC", "2.4G", "40M", "HT", "3T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", - "MKK", "2.4G", "40M", "HT", "3T", "06", "34", - "FCC", "2.4G", "40M", "HT", "3T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", - "MKK", "2.4G", "40M", "HT", "3T", "07", "34", - "FCC", "2.4G", "40M", "HT", "3T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", - "MKK", "2.4G", "40M", "HT", "3T", "08", "34", - "FCC", "2.4G", "40M", "HT", "3T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", - "MKK", "2.4G", "40M", "HT", "3T", "09", "34", - "FCC", "2.4G", "40M", "HT", "3T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", - "MKK", "2.4G", "40M", "HT", "3T", "10", "34", - "FCC", "2.4G", "40M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", - "MKK", "2.4G", "40M", "HT", "3T", "11", "34", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", - "MKK", "2.4G", "40M", "HT", "3T", "12", "34", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", - "MKK", "2.4G", "40M", "HT", "3T", "13", "34", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", - "MKK", "2.4G", "40M", "HT", "4T", "03", "34", - "FCC", "2.4G", "40M", "HT", "4T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", - "MKK", "2.4G", "40M", "HT", "4T", "04", "34", - "FCC", "2.4G", "40M", "HT", "4T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", - "MKK", "2.4G", "40M", "HT", "4T", "05", "34", - "FCC", "2.4G", "40M", "HT", "4T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", - "MKK", "2.4G", "40M", "HT", "4T", "06", "34", - "FCC", "2.4G", "40M", "HT", "4T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", - "MKK", "2.4G", "40M", "HT", "4T", "07", "34", - "FCC", "2.4G", "40M", "HT", "4T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", - "MKK", "2.4G", "40M", "HT", "4T", "08", "34", - "FCC", "2.4G", "40M", "HT", "4T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", - "MKK", "2.4G", "40M", "HT", "4T", "09", "34", - "FCC", "2.4G", "40M", "HT", "4T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", - "MKK", "2.4G", "40M", "HT", "4T", "10", "34", - "FCC", "2.4G", "40M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", - "MKK", "2.4G", "40M", "HT", "4T", "11", "34", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", - "MKK", "2.4G", "40M", "HT", "4T", "12", "34", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", - "MKK", "2.4G", "40M", "HT", "4T", "13", "34", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "42", - "MKK", "5G", "20M", "OFDM", "1T", "36", "42", - "FCC", "5G", "20M", "OFDM", "1T", "40", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "42", - "MKK", "5G", "20M", "OFDM", "1T", "40", "42", - "FCC", "5G", "20M", "OFDM", "1T", "44", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "42", - "MKK", "5G", "20M", "OFDM", "1T", "44", "42", - "FCC", "5G", "20M", "OFDM", "1T", "48", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "42", - "MKK", "5G", "20M", "OFDM", "1T", "48", "42", - "FCC", "5G", "20M", "OFDM", "1T", "52", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "42", - "MKK", "5G", "20M", "OFDM", "1T", "52", "42", - "FCC", "5G", "20M", "OFDM", "1T", "56", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "42", - "MKK", "5G", "20M", "OFDM", "1T", "56", "42", - "FCC", "5G", "20M", "OFDM", "1T", "60", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "42", - "MKK", "5G", "20M", "OFDM", "1T", "60", "42", - "FCC", "5G", "20M", "OFDM", "1T", "64", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "42", - "MKK", "5G", "20M", "OFDM", "1T", "64", "42", - "FCC", "5G", "20M", "OFDM", "1T", "100", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "42", - "MKK", "5G", "20M", "OFDM", "1T", "100", "42", - "FCC", "5G", "20M", "OFDM", "1T", "104", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "42", - "MKK", "5G", "20M", "OFDM", "1T", "104", "42", - "FCC", "5G", "20M", "OFDM", "1T", "108", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "42", - "MKK", "5G", "20M", "OFDM", "1T", "108", "42", - "FCC", "5G", "20M", "OFDM", "1T", "112", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "42", - "MKK", "5G", "20M", "OFDM", "1T", "112", "42", - "FCC", "5G", "20M", "OFDM", "1T", "116", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "42", - "MKK", "5G", "20M", "OFDM", "1T", "116", "42", - "FCC", "5G", "20M", "OFDM", "1T", "120", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "42", - "MKK", "5G", "20M", "OFDM", "1T", "120", "42", - "FCC", "5G", "20M", "OFDM", "1T", "124", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "42", - "MKK", "5G", "20M", "OFDM", "1T", "124", "42", - "FCC", "5G", "20M", "OFDM", "1T", "128", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "42", - "MKK", "5G", "20M", "OFDM", "1T", "128", "42", - "FCC", "5G", "20M", "OFDM", "1T", "132", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "42", - "MKK", "5G", "20M", "OFDM", "1T", "132", "42", - "FCC", "5G", "20M", "OFDM", "1T", "136", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "42", - "MKK", "5G", "20M", "OFDM", "1T", "136", "42", - "FCC", "5G", "20M", "OFDM", "1T", "140", "40", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", - "MKK", "5G", "20M", "OFDM", "1T", "140", "40", - "FCC", "5G", "20M", "OFDM", "1T", "149", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "44", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "44", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "36", - "ETSI", "5G", "20M", "HT", "1T", "48", "36", - "MKK", "5G", "20M", "HT", "1T", "48", "36", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "36", - "MKK", "5G", "20M", "HT", "1T", "52", "36", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "32", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "32", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "30", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "40", - "ETSI", "5G", "20M", "HT", "1T", "149", "40", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "40", - "ETSI", "5G", "20M", "HT", "1T", "153", "40", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "40", - "ETSI", "5G", "20M", "HT", "1T", "157", "40", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "40", - "ETSI", "5G", "20M", "HT", "1T", "161", "40", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "42", - "ETSI", "5G", "20M", "HT", "1T", "165", "42", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "32", - "ETSI", "5G", "20M", "HT", "2T", "36", "32", - "MKK", "5G", "20M", "HT", "2T", "36", "32", - "FCC", "5G", "20M", "HT", "2T", "40", "32", - "ETSI", "5G", "20M", "HT", "2T", "40", "32", - "MKK", "5G", "20M", "HT", "2T", "40", "32", - "FCC", "5G", "20M", "HT", "2T", "44", "32", - "ETSI", "5G", "20M", "HT", "2T", "44", "32", - "MKK", "5G", "20M", "HT", "2T", "44", "32", - "FCC", "5G", "20M", "HT", "2T", "48", "36", - "ETSI", "5G", "20M", "HT", "2T", "48", "36", - "MKK", "5G", "20M", "HT", "2T", "48", "36", - "FCC", "5G", "20M", "HT", "2T", "52", "36", - "ETSI", "5G", "20M", "HT", "2T", "52", "36", - "MKK", "5G", "20M", "HT", "2T", "52", "36", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "32", - "MKK", "5G", "20M", "HT", "2T", "56", "32", - "FCC", "5G", "20M", "HT", "2T", "60", "32", - "ETSI", "5G", "20M", "HT", "2T", "60", "32", - "MKK", "5G", "20M", "HT", "2T", "60", "32", - "FCC", "5G", "20M", "HT", "2T", "64", "32", - "ETSI", "5G", "20M", "HT", "2T", "64", "32", - "MKK", "5G", "20M", "HT", "2T", "64", "32", - "FCC", "5G", "20M", "HT", "2T", "100", "32", - "ETSI", "5G", "20M", "HT", "2T", "100", "32", - "MKK", "5G", "20M", "HT", "2T", "100", "32", - "FCC", "5G", "20M", "HT", "2T", "104", "32", - "ETSI", "5G", "20M", "HT", "2T", "104", "32", - "MKK", "5G", "20M", "HT", "2T", "104", "32", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "32", - "MKK", "5G", "20M", "HT", "2T", "108", "32", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "32", - "MKK", "5G", "20M", "HT", "2T", "112", "32", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "32", - "MKK", "5G", "20M", "HT", "2T", "116", "32", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "32", - "MKK", "5G", "20M", "HT", "2T", "120", "32", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "32", - "MKK", "5G", "20M", "HT", "2T", "124", "32", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "32", - "MKK", "5G", "20M", "HT", "2T", "128", "32", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "32", - "MKK", "5G", "20M", "HT", "2T", "132", "32", - "FCC", "5G", "20M", "HT", "2T", "136", "32", - "ETSI", "5G", "20M", "HT", "2T", "136", "32", - "MKK", "5G", "20M", "HT", "2T", "136", "32", - "FCC", "5G", "20M", "HT", "2T", "140", "30", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "40", - "ETSI", "5G", "20M", "HT", "2T", "149", "40", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "40", - "ETSI", "5G", "20M", "HT", "2T", "153", "40", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "40", - "ETSI", "5G", "20M", "HT", "2T", "157", "40", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "40", - "ETSI", "5G", "20M", "HT", "2T", "161", "40", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "42", - "ETSI", "5G", "20M", "HT", "2T", "165", "42", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "32", - "ETSI", "5G", "20M", "HT", "3T", "36", "32", - "MKK", "5G", "20M", "HT", "3T", "36", "32", - "FCC", "5G", "20M", "HT", "3T", "40", "32", - "ETSI", "5G", "20M", "HT", "3T", "40", "32", - "MKK", "5G", "20M", "HT", "3T", "40", "32", - "FCC", "5G", "20M", "HT", "3T", "44", "32", - "ETSI", "5G", "20M", "HT", "3T", "44", "32", - "MKK", "5G", "20M", "HT", "3T", "44", "32", - "FCC", "5G", "20M", "HT", "3T", "48", "36", - "ETSI", "5G", "20M", "HT", "3T", "48", "36", - "MKK", "5G", "20M", "HT", "3T", "48", "36", - "FCC", "5G", "20M", "HT", "3T", "52", "36", - "ETSI", "5G", "20M", "HT", "3T", "52", "36", - "MKK", "5G", "20M", "HT", "3T", "52", "36", - "FCC", "5G", "20M", "HT", "3T", "56", "32", - "ETSI", "5G", "20M", "HT", "3T", "56", "32", - "MKK", "5G", "20M", "HT", "3T", "56", "32", - "FCC", "5G", "20M", "HT", "3T", "60", "32", - "ETSI", "5G", "20M", "HT", "3T", "60", "32", - "MKK", "5G", "20M", "HT", "3T", "60", "32", - "FCC", "5G", "20M", "HT", "3T", "64", "32", - "ETSI", "5G", "20M", "HT", "3T", "64", "32", - "MKK", "5G", "20M", "HT", "3T", "64", "32", - "FCC", "5G", "20M", "HT", "3T", "100", "32", - "ETSI", "5G", "20M", "HT", "3T", "100", "32", - "MKK", "5G", "20M", "HT", "3T", "100", "32", - "FCC", "5G", "20M", "HT", "3T", "104", "32", - "ETSI", "5G", "20M", "HT", "3T", "104", "32", - "MKK", "5G", "20M", "HT", "3T", "104", "32", - "FCC", "5G", "20M", "HT", "3T", "108", "32", - "ETSI", "5G", "20M", "HT", "3T", "108", "32", - "MKK", "5G", "20M", "HT", "3T", "108", "32", - "FCC", "5G", "20M", "HT", "3T", "112", "32", - "ETSI", "5G", "20M", "HT", "3T", "112", "32", - "MKK", "5G", "20M", "HT", "3T", "112", "32", - "FCC", "5G", "20M", "HT", "3T", "116", "32", - "ETSI", "5G", "20M", "HT", "3T", "116", "32", - "MKK", "5G", "20M", "HT", "3T", "116", "32", - "FCC", "5G", "20M", "HT", "3T", "120", "32", - "ETSI", "5G", "20M", "HT", "3T", "120", "32", - "MKK", "5G", "20M", "HT", "3T", "120", "32", - "FCC", "5G", "20M", "HT", "3T", "124", "32", - "ETSI", "5G", "20M", "HT", "3T", "124", "32", - "MKK", "5G", "20M", "HT", "3T", "124", "32", - "FCC", "5G", "20M", "HT", "3T", "128", "32", - "ETSI", "5G", "20M", "HT", "3T", "128", "32", - "MKK", "5G", "20M", "HT", "3T", "128", "32", - "FCC", "5G", "20M", "HT", "3T", "132", "32", - "ETSI", "5G", "20M", "HT", "3T", "132", "32", - "MKK", "5G", "20M", "HT", "3T", "132", "32", - "FCC", "5G", "20M", "HT", "3T", "136", "32", - "ETSI", "5G", "20M", "HT", "3T", "136", "32", - "MKK", "5G", "20M", "HT", "3T", "136", "32", - "FCC", "5G", "20M", "HT", "3T", "140", "30", - "ETSI", "5G", "20M", "HT", "3T", "140", "30", - "MKK", "5G", "20M", "HT", "3T", "140", "30", - "FCC", "5G", "20M", "HT", "3T", "149", "40", - "ETSI", "5G", "20M", "HT", "3T", "149", "40", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "40", - "ETSI", "5G", "20M", "HT", "3T", "153", "40", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "40", - "ETSI", "5G", "20M", "HT", "3T", "157", "40", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "40", - "ETSI", "5G", "20M", "HT", "3T", "161", "40", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "42", - "ETSI", "5G", "20M", "HT", "3T", "165", "42", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "32", - "ETSI", "5G", "20M", "HT", "4T", "36", "32", - "MKK", "5G", "20M", "HT", "4T", "36", "32", - "FCC", "5G", "20M", "HT", "4T", "40", "32", - "ETSI", "5G", "20M", "HT", "4T", "40", "32", - "MKK", "5G", "20M", "HT", "4T", "40", "32", - "FCC", "5G", "20M", "HT", "4T", "44", "32", - "ETSI", "5G", "20M", "HT", "4T", "44", "32", - "MKK", "5G", "20M", "HT", "4T", "44", "32", - "FCC", "5G", "20M", "HT", "4T", "48", "36", - "ETSI", "5G", "20M", "HT", "4T", "48", "36", - "MKK", "5G", "20M", "HT", "4T", "48", "36", - "FCC", "5G", "20M", "HT", "4T", "52", "36", - "ETSI", "5G", "20M", "HT", "4T", "52", "36", - "MKK", "5G", "20M", "HT", "4T", "52", "36", - "FCC", "5G", "20M", "HT", "4T", "56", "32", - "ETSI", "5G", "20M", "HT", "4T", "56", "32", - "MKK", "5G", "20M", "HT", "4T", "56", "32", - "FCC", "5G", "20M", "HT", "4T", "60", "32", - "ETSI", "5G", "20M", "HT", "4T", "60", "32", - "MKK", "5G", "20M", "HT", "4T", "60", "32", - "FCC", "5G", "20M", "HT", "4T", "64", "32", - "ETSI", "5G", "20M", "HT", "4T", "64", "32", - "MKK", "5G", "20M", "HT", "4T", "64", "32", - "FCC", "5G", "20M", "HT", "4T", "100", "32", - "ETSI", "5G", "20M", "HT", "4T", "100", "32", - "MKK", "5G", "20M", "HT", "4T", "100", "32", - "FCC", "5G", "20M", "HT", "4T", "104", "32", - "ETSI", "5G", "20M", "HT", "4T", "104", "32", - "MKK", "5G", "20M", "HT", "4T", "104", "32", - "FCC", "5G", "20M", "HT", "4T", "108", "32", - "ETSI", "5G", "20M", "HT", "4T", "108", "32", - "MKK", "5G", "20M", "HT", "4T", "108", "32", - "FCC", "5G", "20M", "HT", "4T", "112", "32", - "ETSI", "5G", "20M", "HT", "4T", "112", "32", - "MKK", "5G", "20M", "HT", "4T", "112", "32", - "FCC", "5G", "20M", "HT", "4T", "116", "32", - "ETSI", "5G", "20M", "HT", "4T", "116", "32", - "MKK", "5G", "20M", "HT", "4T", "116", "32", - "FCC", "5G", "20M", "HT", "4T", "120", "32", - "ETSI", "5G", "20M", "HT", "4T", "120", "32", - "MKK", "5G", "20M", "HT", "4T", "120", "32", - "FCC", "5G", "20M", "HT", "4T", "124", "32", - "ETSI", "5G", "20M", "HT", "4T", "124", "32", - "MKK", "5G", "20M", "HT", "4T", "124", "32", - "FCC", "5G", "20M", "HT", "4T", "128", "32", - "ETSI", "5G", "20M", "HT", "4T", "128", "32", - "MKK", "5G", "20M", "HT", "4T", "128", "32", - "FCC", "5G", "20M", "HT", "4T", "132", "32", - "ETSI", "5G", "20M", "HT", "4T", "132", "32", - "MKK", "5G", "20M", "HT", "4T", "132", "32", - "FCC", "5G", "20M", "HT", "4T", "136", "32", - "ETSI", "5G", "20M", "HT", "4T", "136", "32", - "MKK", "5G", "20M", "HT", "4T", "136", "32", - "FCC", "5G", "20M", "HT", "4T", "140", "30", - "ETSI", "5G", "20M", "HT", "4T", "140", "30", - "MKK", "5G", "20M", "HT", "4T", "140", "30", - "FCC", "5G", "20M", "HT", "4T", "149", "40", - "ETSI", "5G", "20M", "HT", "4T", "149", "40", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "40", - "ETSI", "5G", "20M", "HT", "4T", "153", "40", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "40", - "ETSI", "5G", "20M", "HT", "4T", "157", "40", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "40", - "ETSI", "5G", "20M", "HT", "4T", "161", "40", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "42", - "ETSI", "5G", "20M", "HT", "4T", "165", "42", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "32", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "36", - "ETSI", "5G", "40M", "HT", "1T", "46", "36", - "MKK", "5G", "40M", "HT", "1T", "46", "36", - "FCC", "5G", "40M", "HT", "1T", "54", "36", - "ETSI", "5G", "40M", "HT", "1T", "54", "36", - "MKK", "5G", "40M", "HT", "1T", "54", "36", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "30", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "36", - "ETSI", "5G", "40M", "HT", "1T", "134", "36", - "MKK", "5G", "40M", "HT", "1T", "134", "36", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "36", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "40", - "ETSI", "5G", "40M", "HT", "1T", "159", "40", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "32", - "ETSI", "5G", "40M", "HT", "2T", "38", "32", - "MKK", "5G", "40M", "HT", "2T", "38", "32", - "FCC", "5G", "40M", "HT", "2T", "46", "36", - "ETSI", "5G", "40M", "HT", "2T", "46", "36", - "MKK", "5G", "40M", "HT", "2T", "46", "36", - "FCC", "5G", "40M", "HT", "2T", "54", "36", - "ETSI", "5G", "40M", "HT", "2T", "54", "36", - "MKK", "5G", "40M", "HT", "2T", "54", "36", - "FCC", "5G", "40M", "HT", "2T", "62", "32", - "ETSI", "5G", "40M", "HT", "2T", "62", "32", - "MKK", "5G", "40M", "HT", "2T", "62", "32", - "FCC", "5G", "40M", "HT", "2T", "102", "30", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "32", - "ETSI", "5G", "40M", "HT", "2T", "110", "32", - "MKK", "5G", "40M", "HT", "2T", "110", "32", - "FCC", "5G", "40M", "HT", "2T", "118", "32", - "ETSI", "5G", "40M", "HT", "2T", "118", "32", - "MKK", "5G", "40M", "HT", "2T", "118", "32", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "32", - "MKK", "5G", "40M", "HT", "2T", "126", "32", - "FCC", "5G", "40M", "HT", "2T", "134", "36", - "ETSI", "5G", "40M", "HT", "2T", "134", "36", - "MKK", "5G", "40M", "HT", "2T", "134", "36", - "FCC", "5G", "40M", "HT", "2T", "151", "36", - "ETSI", "5G", "40M", "HT", "2T", "151", "36", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "40", - "ETSI", "5G", "40M", "HT", "2T", "159", "40", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "32", - "ETSI", "5G", "40M", "HT", "3T", "38", "32", - "MKK", "5G", "40M", "HT", "3T", "38", "32", - "FCC", "5G", "40M", "HT", "3T", "46", "36", - "ETSI", "5G", "40M", "HT", "3T", "46", "36", - "MKK", "5G", "40M", "HT", "3T", "46", "36", - "FCC", "5G", "40M", "HT", "3T", "54", "36", - "ETSI", "5G", "40M", "HT", "3T", "54", "36", - "MKK", "5G", "40M", "HT", "3T", "54", "36", - "FCC", "5G", "40M", "HT", "3T", "62", "32", - "ETSI", "5G", "40M", "HT", "3T", "62", "32", - "MKK", "5G", "40M", "HT", "3T", "62", "32", - "FCC", "5G", "40M", "HT", "3T", "102", "30", - "ETSI", "5G", "40M", "HT", "3T", "102", "30", - "MKK", "5G", "40M", "HT", "3T", "102", "30", - "FCC", "5G", "40M", "HT", "3T", "110", "32", - "ETSI", "5G", "40M", "HT", "3T", "110", "32", - "MKK", "5G", "40M", "HT", "3T", "110", "32", - "FCC", "5G", "40M", "HT", "3T", "118", "32", - "ETSI", "5G", "40M", "HT", "3T", "118", "32", - "MKK", "5G", "40M", "HT", "3T", "118", "32", - "FCC", "5G", "40M", "HT", "3T", "126", "32", - "ETSI", "5G", "40M", "HT", "3T", "126", "32", - "MKK", "5G", "40M", "HT", "3T", "126", "32", - "FCC", "5G", "40M", "HT", "3T", "134", "36", - "ETSI", "5G", "40M", "HT", "3T", "134", "36", - "MKK", "5G", "40M", "HT", "3T", "134", "36", - "FCC", "5G", "40M", "HT", "3T", "151", "36", - "ETSI", "5G", "40M", "HT", "3T", "151", "36", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "40", - "ETSI", "5G", "40M", "HT", "3T", "159", "40", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "32", - "ETSI", "5G", "40M", "HT", "4T", "38", "32", - "MKK", "5G", "40M", "HT", "4T", "38", "32", - "FCC", "5G", "40M", "HT", "4T", "46", "36", - "ETSI", "5G", "40M", "HT", "4T", "46", "36", - "MKK", "5G", "40M", "HT", "4T", "46", "36", - "FCC", "5G", "40M", "HT", "4T", "54", "36", - "ETSI", "5G", "40M", "HT", "4T", "54", "36", - "MKK", "5G", "40M", "HT", "4T", "54", "36", - "FCC", "5G", "40M", "HT", "4T", "62", "32", - "ETSI", "5G", "40M", "HT", "4T", "62", "32", - "MKK", "5G", "40M", "HT", "4T", "62", "32", - "FCC", "5G", "40M", "HT", "4T", "102", "30", - "ETSI", "5G", "40M", "HT", "4T", "102", "30", - "MKK", "5G", "40M", "HT", "4T", "102", "30", - "FCC", "5G", "40M", "HT", "4T", "110", "32", - "ETSI", "5G", "40M", "HT", "4T", "110", "32", - "MKK", "5G", "40M", "HT", "4T", "110", "32", - "FCC", "5G", "40M", "HT", "4T", "118", "32", - "ETSI", "5G", "40M", "HT", "4T", "118", "32", - "MKK", "5G", "40M", "HT", "4T", "118", "32", - "FCC", "5G", "40M", "HT", "4T", "126", "32", - "ETSI", "5G", "40M", "HT", "4T", "126", "32", - "MKK", "5G", "40M", "HT", "4T", "126", "32", - "FCC", "5G", "40M", "HT", "4T", "134", "36", - "ETSI", "5G", "40M", "HT", "4T", "134", "36", - "MKK", "5G", "40M", "HT", "4T", "134", "36", - "FCC", "5G", "40M", "HT", "4T", "151", "36", - "ETSI", "5G", "40M", "HT", "4T", "151", "36", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "40", - "ETSI", "5G", "40M", "HT", "4T", "159", "40", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "34", - "ETSI", "5G", "80M", "VHT", "1T", "42", "34", - "MKK", "5G", "80M", "VHT", "1T", "42", "34", - "FCC", "5G", "80M", "VHT", "1T", "58", "34", - "ETSI", "5G", "80M", "VHT", "1T", "58", "34", - "MKK", "5G", "80M", "VHT", "1T", "58", "34", - "FCC", "5G", "80M", "VHT", "1T", "106", "32", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "34", - "MKK", "5G", "80M", "VHT", "1T", "122", "34", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "34", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "34", - "ETSI", "5G", "80M", "VHT", "2T", "42", "34", - "MKK", "5G", "80M", "VHT", "2T", "42", "34", - "FCC", "5G", "80M", "VHT", "2T", "58", "34", - "ETSI", "5G", "80M", "VHT", "2T", "58", "34", - "MKK", "5G", "80M", "VHT", "2T", "58", "34", - "FCC", "5G", "80M", "VHT", "2T", "106", "32", - "ETSI", "5G", "80M", "VHT", "2T", "106", "32", - "MKK", "5G", "80M", "VHT", "2T", "106", "32", - "FCC", "5G", "80M", "VHT", "2T", "122", "34", - "ETSI", "5G", "80M", "VHT", "2T", "122", "34", - "MKK", "5G", "80M", "VHT", "2T", "122", "34", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "34", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "34", - "ETSI", "5G", "80M", "VHT", "3T", "42", "34", - "MKK", "5G", "80M", "VHT", "3T", "42", "34", - "FCC", "5G", "80M", "VHT", "3T", "58", "34", - "ETSI", "5G", "80M", "VHT", "3T", "58", "34", - "MKK", "5G", "80M", "VHT", "3T", "58", "34", - "FCC", "5G", "80M", "VHT", "3T", "106", "32", - "ETSI", "5G", "80M", "VHT", "3T", "106", "32", - "MKK", "5G", "80M", "VHT", "3T", "106", "32", - "FCC", "5G", "80M", "VHT", "3T", "122", "34", - "ETSI", "5G", "80M", "VHT", "3T", "122", "34", - "MKK", "5G", "80M", "VHT", "3T", "122", "34", - "FCC", "5G", "80M", "VHT", "3T", "155", "34", - "ETSI", "5G", "80M", "VHT", "3T", "155", "34", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "34", - "ETSI", "5G", "80M", "VHT", "4T", "42", "34", - "MKK", "5G", "80M", "VHT", "4T", "42", "34", - "FCC", "5G", "80M", "VHT", "4T", "58", "34", - "ETSI", "5G", "80M", "VHT", "4T", "58", "34", - "MKK", "5G", "80M", "VHT", "4T", "58", "34", - "FCC", "5G", "80M", "VHT", "4T", "106", "32", - "ETSI", "5G", "80M", "VHT", "4T", "106", "32", - "MKK", "5G", "80M", "VHT", "4T", "106", "32", - "FCC", "5G", "80M", "VHT", "4T", "122", "34", - "ETSI", "5G", "80M", "VHT", "4T", "122", "34", - "MKK", "5G", "80M", "VHT", "4T", "122", "34", - "FCC", "5G", "80M", "VHT", "4T", "155", "34", - "ETSI", "5G", "80M", "VHT", "4T", "155", "34", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type2)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type2; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type2)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type2; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type3.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type3[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", - "MKK", "2.4G", "20M", "HT", "1T", "01", "40", - "FCC", "2.4G", "20M", "HT", "1T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", - "MKK", "2.4G", "20M", "HT", "1T", "02", "40", - "FCC", "2.4G", "20M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", - "MKK", "2.4G", "20M", "HT", "1T", "03", "40", - "FCC", "2.4G", "20M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", - "MKK", "2.4G", "20M", "HT", "1T", "04", "40", - "FCC", "2.4G", "20M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "40", - "MKK", "2.4G", "20M", "HT", "1T", "05", "40", - "FCC", "2.4G", "20M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "40", - "MKK", "2.4G", "20M", "HT", "1T", "06", "40", - "FCC", "2.4G", "20M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "40", - "MKK", "2.4G", "20M", "HT", "1T", "07", "40", - "FCC", "2.4G", "20M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "40", - "MKK", "2.4G", "20M", "HT", "1T", "08", "40", - "FCC", "2.4G", "20M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "40", - "MKK", "2.4G", "20M", "HT", "1T", "09", "40", - "FCC", "2.4G", "20M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "40", - "MKK", "2.4G", "20M", "HT", "1T", "10", "40", - "FCC", "2.4G", "20M", "HT", "1T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "40", - "MKK", "2.4G", "20M", "HT", "1T", "11", "40", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "40", - "MKK", "2.4G", "20M", "HT", "1T", "12", "40", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "40", - "MKK", "2.4G", "20M", "HT", "1T", "13", "40", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", - "MKK", "2.4G", "20M", "HT", "2T", "01", "40", - "FCC", "2.4G", "20M", "HT", "2T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", - "MKK", "2.4G", "20M", "HT", "2T", "02", "40", - "FCC", "2.4G", "20M", "HT", "2T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", - "MKK", "2.4G", "20M", "HT", "2T", "03", "40", - "FCC", "2.4G", "20M", "HT", "2T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", - "MKK", "2.4G", "20M", "HT", "2T", "04", "40", - "FCC", "2.4G", "20M", "HT", "2T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", - "MKK", "2.4G", "20M", "HT", "2T", "05", "40", - "FCC", "2.4G", "20M", "HT", "2T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", - "MKK", "2.4G", "20M", "HT", "2T", "06", "40", - "FCC", "2.4G", "20M", "HT", "2T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", - "MKK", "2.4G", "20M", "HT", "2T", "07", "40", - "FCC", "2.4G", "20M", "HT", "2T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", - "MKK", "2.4G", "20M", "HT", "2T", "08", "40", - "FCC", "2.4G", "20M", "HT", "2T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", - "MKK", "2.4G", "20M", "HT", "2T", "09", "40", - "FCC", "2.4G", "20M", "HT", "2T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", - "MKK", "2.4G", "20M", "HT", "2T", "10", "40", - "FCC", "2.4G", "20M", "HT", "2T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", - "MKK", "2.4G", "20M", "HT", "2T", "11", "40", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", - "MKK", "2.4G", "20M", "HT", "2T", "12", "40", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", - "MKK", "2.4G", "20M", "HT", "2T", "13", "40", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", - "MKK", "2.4G", "20M", "HT", "3T", "01", "40", - "FCC", "2.4G", "20M", "HT", "3T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", - "MKK", "2.4G", "20M", "HT", "3T", "02", "40", - "FCC", "2.4G", "20M", "HT", "3T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", - "MKK", "2.4G", "20M", "HT", "3T", "03", "40", - "FCC", "2.4G", "20M", "HT", "3T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", - "MKK", "2.4G", "20M", "HT", "3T", "04", "40", - "FCC", "2.4G", "20M", "HT", "3T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", - "MKK", "2.4G", "20M", "HT", "3T", "05", "40", - "FCC", "2.4G", "20M", "HT", "3T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", - "MKK", "2.4G", "20M", "HT", "3T", "06", "40", - "FCC", "2.4G", "20M", "HT", "3T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", - "MKK", "2.4G", "20M", "HT", "3T", "07", "40", - "FCC", "2.4G", "20M", "HT", "3T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", - "MKK", "2.4G", "20M", "HT", "3T", "08", "40", - "FCC", "2.4G", "20M", "HT", "3T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", - "MKK", "2.4G", "20M", "HT", "3T", "09", "40", - "FCC", "2.4G", "20M", "HT", "3T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", - "MKK", "2.4G", "20M", "HT", "3T", "10", "40", - "FCC", "2.4G", "20M", "HT", "3T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", - "MKK", "2.4G", "20M", "HT", "3T", "11", "40", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", - "MKK", "2.4G", "20M", "HT", "3T", "12", "40", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", - "MKK", "2.4G", "20M", "HT", "3T", "13", "40", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", - "MKK", "2.4G", "20M", "HT", "4T", "01", "40", - "FCC", "2.4G", "20M", "HT", "4T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", - "MKK", "2.4G", "20M", "HT", "4T", "02", "40", - "FCC", "2.4G", "20M", "HT", "4T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", - "MKK", "2.4G", "20M", "HT", "4T", "03", "40", - "FCC", "2.4G", "20M", "HT", "4T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", - "MKK", "2.4G", "20M", "HT", "4T", "04", "40", - "FCC", "2.4G", "20M", "HT", "4T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", - "MKK", "2.4G", "20M", "HT", "4T", "05", "40", - "FCC", "2.4G", "20M", "HT", "4T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", - "MKK", "2.4G", "20M", "HT", "4T", "06", "40", - "FCC", "2.4G", "20M", "HT", "4T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", - "MKK", "2.4G", "20M", "HT", "4T", "07", "40", - "FCC", "2.4G", "20M", "HT", "4T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", - "MKK", "2.4G", "20M", "HT", "4T", "08", "40", - "FCC", "2.4G", "20M", "HT", "4T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", - "MKK", "2.4G", "20M", "HT", "4T", "09", "40", - "FCC", "2.4G", "20M", "HT", "4T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", - "MKK", "2.4G", "20M", "HT", "4T", "10", "40", - "FCC", "2.4G", "20M", "HT", "4T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", - "MKK", "2.4G", "20M", "HT", "4T", "11", "40", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", - "MKK", "2.4G", "20M", "HT", "4T", "12", "40", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", - "MKK", "2.4G", "20M", "HT", "4T", "13", "40", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "40", - "MKK", "2.4G", "40M", "HT", "1T", "03", "40", - "FCC", "2.4G", "40M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "40", - "MKK", "2.4G", "40M", "HT", "1T", "04", "40", - "FCC", "2.4G", "40M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "40", - "MKK", "2.4G", "40M", "HT", "1T", "05", "40", - "FCC", "2.4G", "40M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "40", - "MKK", "2.4G", "40M", "HT", "1T", "06", "40", - "FCC", "2.4G", "40M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "40", - "MKK", "2.4G", "40M", "HT", "1T", "07", "40", - "FCC", "2.4G", "40M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "40", - "MKK", "2.4G", "40M", "HT", "1T", "08", "40", - "FCC", "2.4G", "40M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "40", - "MKK", "2.4G", "40M", "HT", "1T", "09", "40", - "FCC", "2.4G", "40M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "40", - "MKK", "2.4G", "40M", "HT", "1T", "10", "40", - "FCC", "2.4G", "40M", "HT", "1T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "40", - "MKK", "2.4G", "40M", "HT", "1T", "11", "40", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "40", - "MKK", "2.4G", "40M", "HT", "1T", "12", "40", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "40", - "MKK", "2.4G", "40M", "HT", "1T", "13", "40", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "40", - "MKK", "2.4G", "40M", "HT", "2T", "03", "40", - "FCC", "2.4G", "40M", "HT", "2T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "40", - "MKK", "2.4G", "40M", "HT", "2T", "04", "40", - "FCC", "2.4G", "40M", "HT", "2T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "40", - "MKK", "2.4G", "40M", "HT", "2T", "05", "40", - "FCC", "2.4G", "40M", "HT", "2T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "40", - "MKK", "2.4G", "40M", "HT", "2T", "06", "40", - "FCC", "2.4G", "40M", "HT", "2T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "40", - "MKK", "2.4G", "40M", "HT", "2T", "07", "40", - "FCC", "2.4G", "40M", "HT", "2T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "40", - "MKK", "2.4G", "40M", "HT", "2T", "08", "40", - "FCC", "2.4G", "40M", "HT", "2T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "40", - "MKK", "2.4G", "40M", "HT", "2T", "09", "40", - "FCC", "2.4G", "40M", "HT", "2T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "40", - "MKK", "2.4G", "40M", "HT", "2T", "10", "40", - "FCC", "2.4G", "40M", "HT", "2T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "40", - "MKK", "2.4G", "40M", "HT", "2T", "11", "40", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "40", - "MKK", "2.4G", "40M", "HT", "2T", "12", "40", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "40", - "MKK", "2.4G", "40M", "HT", "2T", "13", "40", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "40", - "MKK", "2.4G", "40M", "HT", "3T", "03", "40", - "FCC", "2.4G", "40M", "HT", "3T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "40", - "MKK", "2.4G", "40M", "HT", "3T", "04", "40", - "FCC", "2.4G", "40M", "HT", "3T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "40", - "MKK", "2.4G", "40M", "HT", "3T", "05", "40", - "FCC", "2.4G", "40M", "HT", "3T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "40", - "MKK", "2.4G", "40M", "HT", "3T", "06", "40", - "FCC", "2.4G", "40M", "HT", "3T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "40", - "MKK", "2.4G", "40M", "HT", "3T", "07", "40", - "FCC", "2.4G", "40M", "HT", "3T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "40", - "MKK", "2.4G", "40M", "HT", "3T", "08", "40", - "FCC", "2.4G", "40M", "HT", "3T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "40", - "MKK", "2.4G", "40M", "HT", "3T", "09", "40", - "FCC", "2.4G", "40M", "HT", "3T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "40", - "MKK", "2.4G", "40M", "HT", "3T", "10", "40", - "FCC", "2.4G", "40M", "HT", "3T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "40", - "MKK", "2.4G", "40M", "HT", "3T", "11", "40", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "40", - "MKK", "2.4G", "40M", "HT", "3T", "12", "40", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "40", - "MKK", "2.4G", "40M", "HT", "3T", "13", "40", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "40", - "MKK", "2.4G", "40M", "HT", "4T", "03", "40", - "FCC", "2.4G", "40M", "HT", "4T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "40", - "MKK", "2.4G", "40M", "HT", "4T", "04", "40", - "FCC", "2.4G", "40M", "HT", "4T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "40", - "MKK", "2.4G", "40M", "HT", "4T", "05", "40", - "FCC", "2.4G", "40M", "HT", "4T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "40", - "MKK", "2.4G", "40M", "HT", "4T", "06", "40", - "FCC", "2.4G", "40M", "HT", "4T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "40", - "MKK", "2.4G", "40M", "HT", "4T", "07", "40", - "FCC", "2.4G", "40M", "HT", "4T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "40", - "MKK", "2.4G", "40M", "HT", "4T", "08", "40", - "FCC", "2.4G", "40M", "HT", "4T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "40", - "MKK", "2.4G", "40M", "HT", "4T", "09", "40", - "FCC", "2.4G", "40M", "HT", "4T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "40", - "MKK", "2.4G", "40M", "HT", "4T", "10", "40", - "FCC", "2.4G", "40M", "HT", "4T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "40", - "MKK", "2.4G", "40M", "HT", "4T", "11", "40", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "40", - "MKK", "2.4G", "40M", "HT", "4T", "12", "40", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "40", - "MKK", "2.4G", "40M", "HT", "4T", "13", "40", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "40", - "MKK", "5G", "20M", "OFDM", "1T", "36", "40", - "FCC", "5G", "20M", "OFDM", "1T", "40", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "40", - "MKK", "5G", "20M", "OFDM", "1T", "40", "40", - "FCC", "5G", "20M", "OFDM", "1T", "44", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "40", - "MKK", "5G", "20M", "OFDM", "1T", "44", "40", - "FCC", "5G", "20M", "OFDM", "1T", "48", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "40", - "MKK", "5G", "20M", "OFDM", "1T", "48", "40", - "FCC", "5G", "20M", "OFDM", "1T", "52", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "40", - "MKK", "5G", "20M", "OFDM", "1T", "52", "40", - "FCC", "5G", "20M", "OFDM", "1T", "56", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "40", - "MKK", "5G", "20M", "OFDM", "1T", "56", "40", - "FCC", "5G", "20M", "OFDM", "1T", "60", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "40", - "MKK", "5G", "20M", "OFDM", "1T", "60", "40", - "FCC", "5G", "20M", "OFDM", "1T", "64", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", - "MKK", "5G", "20M", "OFDM", "1T", "64", "40", - "FCC", "5G", "20M", "OFDM", "1T", "100", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", - "MKK", "5G", "20M", "OFDM", "1T", "100", "40", - "FCC", "5G", "20M", "OFDM", "1T", "104", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "40", - "MKK", "5G", "20M", "OFDM", "1T", "104", "40", - "FCC", "5G", "20M", "OFDM", "1T", "108", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "40", - "MKK", "5G", "20M", "OFDM", "1T", "108", "40", - "FCC", "5G", "20M", "OFDM", "1T", "112", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "40", - "MKK", "5G", "20M", "OFDM", "1T", "112", "40", - "FCC", "5G", "20M", "OFDM", "1T", "116", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "40", - "MKK", "5G", "20M", "OFDM", "1T", "116", "40", - "FCC", "5G", "20M", "OFDM", "1T", "120", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "40", - "MKK", "5G", "20M", "OFDM", "1T", "120", "40", - "FCC", "5G", "20M", "OFDM", "1T", "124", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "40", - "MKK", "5G", "20M", "OFDM", "1T", "124", "40", - "FCC", "5G", "20M", "OFDM", "1T", "128", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "40", - "MKK", "5G", "20M", "OFDM", "1T", "128", "40", - "FCC", "5G", "20M", "OFDM", "1T", "132", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "40", - "MKK", "5G", "20M", "OFDM", "1T", "132", "40", - "FCC", "5G", "20M", "OFDM", "1T", "136", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "40", - "MKK", "5G", "20M", "OFDM", "1T", "136", "40", - "FCC", "5G", "20M", "OFDM", "1T", "140", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", - "MKK", "5G", "20M", "OFDM", "1T", "140", "40", - "FCC", "5G", "20M", "OFDM", "1T", "149", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "40", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "40", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "40", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "40", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "40", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "46", - "ETSI", "5G", "20M", "HT", "1T", "36", "40", - "MKK", "5G", "20M", "HT", "1T", "36", "40", - "FCC", "5G", "20M", "HT", "1T", "40", "46", - "ETSI", "5G", "20M", "HT", "1T", "40", "40", - "MKK", "5G", "20M", "HT", "1T", "40", "40", - "FCC", "5G", "20M", "HT", "1T", "44", "46", - "ETSI", "5G", "20M", "HT", "1T", "44", "40", - "MKK", "5G", "20M", "HT", "1T", "44", "40", - "FCC", "5G", "20M", "HT", "1T", "48", "46", - "ETSI", "5G", "20M", "HT", "1T", "48", "40", - "MKK", "5G", "20M", "HT", "1T", "48", "40", - "FCC", "5G", "20M", "HT", "1T", "52", "46", - "ETSI", "5G", "20M", "HT", "1T", "52", "40", - "MKK", "5G", "20M", "HT", "1T", "52", "40", - "FCC", "5G", "20M", "HT", "1T", "56", "46", - "ETSI", "5G", "20M", "HT", "1T", "56", "40", - "MKK", "5G", "20M", "HT", "1T", "56", "40", - "FCC", "5G", "20M", "HT", "1T", "60", "46", - "ETSI", "5G", "20M", "HT", "1T", "60", "40", - "MKK", "5G", "20M", "HT", "1T", "60", "40", - "FCC", "5G", "20M", "HT", "1T", "64", "46", - "ETSI", "5G", "20M", "HT", "1T", "64", "40", - "MKK", "5G", "20M", "HT", "1T", "64", "40", - "FCC", "5G", "20M", "HT", "1T", "100", "46", - "ETSI", "5G", "20M", "HT", "1T", "100", "40", - "MKK", "5G", "20M", "HT", "1T", "100", "40", - "FCC", "5G", "20M", "HT", "1T", "104", "46", - "ETSI", "5G", "20M", "HT", "1T", "104", "40", - "MKK", "5G", "20M", "HT", "1T", "104", "40", - "FCC", "5G", "20M", "HT", "1T", "108", "46", - "ETSI", "5G", "20M", "HT", "1T", "108", "40", - "MKK", "5G", "20M", "HT", "1T", "108", "40", - "FCC", "5G", "20M", "HT", "1T", "112", "46", - "ETSI", "5G", "20M", "HT", "1T", "112", "40", - "MKK", "5G", "20M", "HT", "1T", "112", "40", - "FCC", "5G", "20M", "HT", "1T", "116", "46", - "ETSI", "5G", "20M", "HT", "1T", "116", "40", - "MKK", "5G", "20M", "HT", "1T", "116", "40", - "FCC", "5G", "20M", "HT", "1T", "120", "46", - "ETSI", "5G", "20M", "HT", "1T", "120", "40", - "MKK", "5G", "20M", "HT", "1T", "120", "40", - "FCC", "5G", "20M", "HT", "1T", "124", "46", - "ETSI", "5G", "20M", "HT", "1T", "124", "40", - "MKK", "5G", "20M", "HT", "1T", "124", "40", - "FCC", "5G", "20M", "HT", "1T", "128", "46", - "ETSI", "5G", "20M", "HT", "1T", "128", "40", - "MKK", "5G", "20M", "HT", "1T", "128", "40", - "FCC", "5G", "20M", "HT", "1T", "132", "46", - "ETSI", "5G", "20M", "HT", "1T", "132", "40", - "MKK", "5G", "20M", "HT", "1T", "132", "40", - "FCC", "5G", "20M", "HT", "1T", "136", "46", - "ETSI", "5G", "20M", "HT", "1T", "136", "40", - "MKK", "5G", "20M", "HT", "1T", "136", "40", - "FCC", "5G", "20M", "HT", "1T", "140", "46", - "ETSI", "5G", "20M", "HT", "1T", "140", "40", - "MKK", "5G", "20M", "HT", "1T", "140", "40", - "FCC", "5G", "20M", "HT", "1T", "149", "46", - "ETSI", "5G", "20M", "HT", "1T", "149", "40", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "46", - "ETSI", "5G", "20M", "HT", "1T", "153", "40", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "46", - "ETSI", "5G", "20M", "HT", "1T", "157", "40", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "46", - "ETSI", "5G", "20M", "HT", "1T", "161", "40", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "46", - "ETSI", "5G", "20M", "HT", "1T", "165", "40", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "46", - "ETSI", "5G", "20M", "HT", "2T", "36", "40", - "MKK", "5G", "20M", "HT", "2T", "36", "40", - "FCC", "5G", "20M", "HT", "2T", "40", "46", - "ETSI", "5G", "20M", "HT", "2T", "40", "40", - "MKK", "5G", "20M", "HT", "2T", "40", "40", - "FCC", "5G", "20M", "HT", "2T", "44", "46", - "ETSI", "5G", "20M", "HT", "2T", "44", "40", - "MKK", "5G", "20M", "HT", "2T", "44", "40", - "FCC", "5G", "20M", "HT", "2T", "48", "46", - "ETSI", "5G", "20M", "HT", "2T", "48", "40", - "MKK", "5G", "20M", "HT", "2T", "48", "40", - "FCC", "5G", "20M", "HT", "2T", "52", "46", - "ETSI", "5G", "20M", "HT", "2T", "52", "40", - "MKK", "5G", "20M", "HT", "2T", "52", "40", - "FCC", "5G", "20M", "HT", "2T", "56", "46", - "ETSI", "5G", "20M", "HT", "2T", "56", "40", - "MKK", "5G", "20M", "HT", "2T", "56", "40", - "FCC", "5G", "20M", "HT", "2T", "60", "46", - "ETSI", "5G", "20M", "HT", "2T", "60", "40", - "MKK", "5G", "20M", "HT", "2T", "60", "40", - "FCC", "5G", "20M", "HT", "2T", "64", "46", - "ETSI", "5G", "20M", "HT", "2T", "64", "40", - "MKK", "5G", "20M", "HT", "2T", "64", "40", - "FCC", "5G", "20M", "HT", "2T", "100", "46", - "ETSI", "5G", "20M", "HT", "2T", "100", "40", - "MKK", "5G", "20M", "HT", "2T", "100", "40", - "FCC", "5G", "20M", "HT", "2T", "104", "46", - "ETSI", "5G", "20M", "HT", "2T", "104", "40", - "MKK", "5G", "20M", "HT", "2T", "104", "40", - "FCC", "5G", "20M", "HT", "2T", "108", "46", - "ETSI", "5G", "20M", "HT", "2T", "108", "40", - "MKK", "5G", "20M", "HT", "2T", "108", "40", - "FCC", "5G", "20M", "HT", "2T", "112", "46", - "ETSI", "5G", "20M", "HT", "2T", "112", "40", - "MKK", "5G", "20M", "HT", "2T", "112", "40", - "FCC", "5G", "20M", "HT", "2T", "116", "46", - "ETSI", "5G", "20M", "HT", "2T", "116", "40", - "MKK", "5G", "20M", "HT", "2T", "116", "40", - "FCC", "5G", "20M", "HT", "2T", "120", "46", - "ETSI", "5G", "20M", "HT", "2T", "120", "40", - "MKK", "5G", "20M", "HT", "2T", "120", "40", - "FCC", "5G", "20M", "HT", "2T", "124", "46", - "ETSI", "5G", "20M", "HT", "2T", "124", "40", - "MKK", "5G", "20M", "HT", "2T", "124", "40", - "FCC", "5G", "20M", "HT", "2T", "128", "46", - "ETSI", "5G", "20M", "HT", "2T", "128", "40", - "MKK", "5G", "20M", "HT", "2T", "128", "40", - "FCC", "5G", "20M", "HT", "2T", "132", "46", - "ETSI", "5G", "20M", "HT", "2T", "132", "40", - "MKK", "5G", "20M", "HT", "2T", "132", "40", - "FCC", "5G", "20M", "HT", "2T", "136", "46", - "ETSI", "5G", "20M", "HT", "2T", "136", "40", - "MKK", "5G", "20M", "HT", "2T", "136", "40", - "FCC", "5G", "20M", "HT", "2T", "140", "46", - "ETSI", "5G", "20M", "HT", "2T", "140", "40", - "MKK", "5G", "20M", "HT", "2T", "140", "40", - "FCC", "5G", "20M", "HT", "2T", "149", "46", - "ETSI", "5G", "20M", "HT", "2T", "149", "40", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "46", - "ETSI", "5G", "20M", "HT", "2T", "153", "40", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "46", - "ETSI", "5G", "20M", "HT", "2T", "157", "40", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "46", - "ETSI", "5G", "20M", "HT", "2T", "161", "40", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "46", - "ETSI", "5G", "20M", "HT", "2T", "165", "40", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "46", - "ETSI", "5G", "20M", "HT", "3T", "36", "40", - "MKK", "5G", "20M", "HT", "3T", "36", "40", - "FCC", "5G", "20M", "HT", "3T", "40", "46", - "ETSI", "5G", "20M", "HT", "3T", "40", "40", - "MKK", "5G", "20M", "HT", "3T", "40", "40", - "FCC", "5G", "20M", "HT", "3T", "44", "46", - "ETSI", "5G", "20M", "HT", "3T", "44", "40", - "MKK", "5G", "20M", "HT", "3T", "44", "40", - "FCC", "5G", "20M", "HT", "3T", "48", "46", - "ETSI", "5G", "20M", "HT", "3T", "48", "40", - "MKK", "5G", "20M", "HT", "3T", "48", "40", - "FCC", "5G", "20M", "HT", "3T", "52", "46", - "ETSI", "5G", "20M", "HT", "3T", "52", "40", - "MKK", "5G", "20M", "HT", "3T", "52", "40", - "FCC", "5G", "20M", "HT", "3T", "56", "46", - "ETSI", "5G", "20M", "HT", "3T", "56", "40", - "MKK", "5G", "20M", "HT", "3T", "56", "40", - "FCC", "5G", "20M", "HT", "3T", "60", "46", - "ETSI", "5G", "20M", "HT", "3T", "60", "40", - "MKK", "5G", "20M", "HT", "3T", "60", "40", - "FCC", "5G", "20M", "HT", "3T", "64", "46", - "ETSI", "5G", "20M", "HT", "3T", "64", "40", - "MKK", "5G", "20M", "HT", "3T", "64", "40", - "FCC", "5G", "20M", "HT", "3T", "100", "46", - "ETSI", "5G", "20M", "HT", "3T", "100", "40", - "MKK", "5G", "20M", "HT", "3T", "100", "40", - "FCC", "5G", "20M", "HT", "3T", "104", "46", - "ETSI", "5G", "20M", "HT", "3T", "104", "40", - "MKK", "5G", "20M", "HT", "3T", "104", "40", - "FCC", "5G", "20M", "HT", "3T", "108", "46", - "ETSI", "5G", "20M", "HT", "3T", "108", "40", - "MKK", "5G", "20M", "HT", "3T", "108", "40", - "FCC", "5G", "20M", "HT", "3T", "112", "46", - "ETSI", "5G", "20M", "HT", "3T", "112", "40", - "MKK", "5G", "20M", "HT", "3T", "112", "40", - "FCC", "5G", "20M", "HT", "3T", "116", "46", - "ETSI", "5G", "20M", "HT", "3T", "116", "40", - "MKK", "5G", "20M", "HT", "3T", "116", "40", - "FCC", "5G", "20M", "HT", "3T", "120", "46", - "ETSI", "5G", "20M", "HT", "3T", "120", "40", - "MKK", "5G", "20M", "HT", "3T", "120", "40", - "FCC", "5G", "20M", "HT", "3T", "124", "46", - "ETSI", "5G", "20M", "HT", "3T", "124", "40", - "MKK", "5G", "20M", "HT", "3T", "124", "40", - "FCC", "5G", "20M", "HT", "3T", "128", "46", - "ETSI", "5G", "20M", "HT", "3T", "128", "40", - "MKK", "5G", "20M", "HT", "3T", "128", "40", - "FCC", "5G", "20M", "HT", "3T", "132", "46", - "ETSI", "5G", "20M", "HT", "3T", "132", "40", - "MKK", "5G", "20M", "HT", "3T", "132", "40", - "FCC", "5G", "20M", "HT", "3T", "136", "46", - "ETSI", "5G", "20M", "HT", "3T", "136", "40", - "MKK", "5G", "20M", "HT", "3T", "136", "40", - "FCC", "5G", "20M", "HT", "3T", "140", "46", - "ETSI", "5G", "20M", "HT", "3T", "140", "40", - "MKK", "5G", "20M", "HT", "3T", "140", "40", - "FCC", "5G", "20M", "HT", "3T", "149", "46", - "ETSI", "5G", "20M", "HT", "3T", "149", "40", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "46", - "ETSI", "5G", "20M", "HT", "3T", "153", "40", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "46", - "ETSI", "5G", "20M", "HT", "3T", "157", "40", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "46", - "ETSI", "5G", "20M", "HT", "3T", "161", "40", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "46", - "ETSI", "5G", "20M", "HT", "3T", "165", "40", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "46", - "ETSI", "5G", "20M", "HT", "4T", "36", "40", - "MKK", "5G", "20M", "HT", "4T", "36", "40", - "FCC", "5G", "20M", "HT", "4T", "40", "46", - "ETSI", "5G", "20M", "HT", "4T", "40", "40", - "MKK", "5G", "20M", "HT", "4T", "40", "40", - "FCC", "5G", "20M", "HT", "4T", "44", "46", - "ETSI", "5G", "20M", "HT", "4T", "44", "40", - "MKK", "5G", "20M", "HT", "4T", "44", "40", - "FCC", "5G", "20M", "HT", "4T", "48", "46", - "ETSI", "5G", "20M", "HT", "4T", "48", "40", - "MKK", "5G", "20M", "HT", "4T", "48", "40", - "FCC", "5G", "20M", "HT", "4T", "52", "46", - "ETSI", "5G", "20M", "HT", "4T", "52", "40", - "MKK", "5G", "20M", "HT", "4T", "52", "40", - "FCC", "5G", "20M", "HT", "4T", "56", "46", - "ETSI", "5G", "20M", "HT", "4T", "56", "40", - "MKK", "5G", "20M", "HT", "4T", "56", "40", - "FCC", "5G", "20M", "HT", "4T", "60", "46", - "ETSI", "5G", "20M", "HT", "4T", "60", "40", - "MKK", "5G", "20M", "HT", "4T", "60", "40", - "FCC", "5G", "20M", "HT", "4T", "64", "46", - "ETSI", "5G", "20M", "HT", "4T", "64", "40", - "MKK", "5G", "20M", "HT", "4T", "64", "40", - "FCC", "5G", "20M", "HT", "4T", "100", "46", - "ETSI", "5G", "20M", "HT", "4T", "100", "40", - "MKK", "5G", "20M", "HT", "4T", "100", "40", - "FCC", "5G", "20M", "HT", "4T", "104", "46", - "ETSI", "5G", "20M", "HT", "4T", "104", "40", - "MKK", "5G", "20M", "HT", "4T", "104", "40", - "FCC", "5G", "20M", "HT", "4T", "108", "46", - "ETSI", "5G", "20M", "HT", "4T", "108", "40", - "MKK", "5G", "20M", "HT", "4T", "108", "40", - "FCC", "5G", "20M", "HT", "4T", "112", "46", - "ETSI", "5G", "20M", "HT", "4T", "112", "40", - "MKK", "5G", "20M", "HT", "4T", "112", "40", - "FCC", "5G", "20M", "HT", "4T", "116", "46", - "ETSI", "5G", "20M", "HT", "4T", "116", "40", - "MKK", "5G", "20M", "HT", "4T", "116", "40", - "FCC", "5G", "20M", "HT", "4T", "120", "46", - "ETSI", "5G", "20M", "HT", "4T", "120", "40", - "MKK", "5G", "20M", "HT", "4T", "120", "40", - "FCC", "5G", "20M", "HT", "4T", "124", "46", - "ETSI", "5G", "20M", "HT", "4T", "124", "40", - "MKK", "5G", "20M", "HT", "4T", "124", "40", - "FCC", "5G", "20M", "HT", "4T", "128", "46", - "ETSI", "5G", "20M", "HT", "4T", "128", "40", - "MKK", "5G", "20M", "HT", "4T", "128", "40", - "FCC", "5G", "20M", "HT", "4T", "132", "46", - "ETSI", "5G", "20M", "HT", "4T", "132", "40", - "MKK", "5G", "20M", "HT", "4T", "132", "40", - "FCC", "5G", "20M", "HT", "4T", "136", "46", - "ETSI", "5G", "20M", "HT", "4T", "136", "40", - "MKK", "5G", "20M", "HT", "4T", "136", "40", - "FCC", "5G", "20M", "HT", "4T", "140", "46", - "ETSI", "5G", "20M", "HT", "4T", "140", "40", - "MKK", "5G", "20M", "HT", "4T", "140", "40", - "FCC", "5G", "20M", "HT", "4T", "149", "46", - "ETSI", "5G", "20M", "HT", "4T", "149", "40", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "46", - "ETSI", "5G", "20M", "HT", "4T", "153", "40", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "46", - "ETSI", "5G", "20M", "HT", "4T", "157", "40", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "46", - "ETSI", "5G", "20M", "HT", "4T", "161", "40", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "46", - "ETSI", "5G", "20M", "HT", "4T", "165", "40", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "46", - "ETSI", "5G", "40M", "HT", "1T", "38", "40", - "MKK", "5G", "40M", "HT", "1T", "38", "40", - "FCC", "5G", "40M", "HT", "1T", "46", "46", - "ETSI", "5G", "40M", "HT", "1T", "46", "40", - "MKK", "5G", "40M", "HT", "1T", "46", "40", - "FCC", "5G", "40M", "HT", "1T", "54", "46", - "ETSI", "5G", "40M", "HT", "1T", "54", "40", - "MKK", "5G", "40M", "HT", "1T", "54", "40", - "FCC", "5G", "40M", "HT", "1T", "62", "46", - "ETSI", "5G", "40M", "HT", "1T", "62", "40", - "MKK", "5G", "40M", "HT", "1T", "62", "40", - "FCC", "5G", "40M", "HT", "1T", "102", "46", - "ETSI", "5G", "40M", "HT", "1T", "102", "40", - "MKK", "5G", "40M", "HT", "1T", "102", "40", - "FCC", "5G", "40M", "HT", "1T", "110", "46", - "ETSI", "5G", "40M", "HT", "1T", "110", "40", - "MKK", "5G", "40M", "HT", "1T", "110", "40", - "FCC", "5G", "40M", "HT", "1T", "118", "46", - "ETSI", "5G", "40M", "HT", "1T", "118", "40", - "MKK", "5G", "40M", "HT", "1T", "118", "40", - "FCC", "5G", "40M", "HT", "1T", "126", "46", - "ETSI", "5G", "40M", "HT", "1T", "126", "40", - "MKK", "5G", "40M", "HT", "1T", "126", "40", - "FCC", "5G", "40M", "HT", "1T", "134", "46", - "ETSI", "5G", "40M", "HT", "1T", "134", "40", - "MKK", "5G", "40M", "HT", "1T", "134", "40", - "FCC", "5G", "40M", "HT", "1T", "151", "46", - "ETSI", "5G", "40M", "HT", "1T", "151", "40", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "46", - "ETSI", "5G", "40M", "HT", "1T", "159", "40", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "46", - "ETSI", "5G", "40M", "HT", "2T", "38", "40", - "MKK", "5G", "40M", "HT", "2T", "38", "40", - "FCC", "5G", "40M", "HT", "2T", "46", "46", - "ETSI", "5G", "40M", "HT", "2T", "46", "40", - "MKK", "5G", "40M", "HT", "2T", "46", "40", - "FCC", "5G", "40M", "HT", "2T", "54", "46", - "ETSI", "5G", "40M", "HT", "2T", "54", "40", - "MKK", "5G", "40M", "HT", "2T", "54", "40", - "FCC", "5G", "40M", "HT", "2T", "62", "46", - "ETSI", "5G", "40M", "HT", "2T", "62", "40", - "MKK", "5G", "40M", "HT", "2T", "62", "40", - "FCC", "5G", "40M", "HT", "2T", "102", "46", - "ETSI", "5G", "40M", "HT", "2T", "102", "40", - "MKK", "5G", "40M", "HT", "2T", "102", "40", - "FCC", "5G", "40M", "HT", "2T", "110", "46", - "ETSI", "5G", "40M", "HT", "2T", "110", "40", - "MKK", "5G", "40M", "HT", "2T", "110", "40", - "FCC", "5G", "40M", "HT", "2T", "118", "46", - "ETSI", "5G", "40M", "HT", "2T", "118", "40", - "MKK", "5G", "40M", "HT", "2T", "118", "40", - "FCC", "5G", "40M", "HT", "2T", "126", "46", - "ETSI", "5G", "40M", "HT", "2T", "126", "40", - "MKK", "5G", "40M", "HT", "2T", "126", "40", - "FCC", "5G", "40M", "HT", "2T", "134", "46", - "ETSI", "5G", "40M", "HT", "2T", "134", "40", - "MKK", "5G", "40M", "HT", "2T", "134", "40", - "FCC", "5G", "40M", "HT", "2T", "151", "46", - "ETSI", "5G", "40M", "HT", "2T", "151", "40", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "46", - "ETSI", "5G", "40M", "HT", "2T", "159", "40", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "46", - "ETSI", "5G", "40M", "HT", "3T", "38", "40", - "MKK", "5G", "40M", "HT", "3T", "38", "40", - "FCC", "5G", "40M", "HT", "3T", "46", "46", - "ETSI", "5G", "40M", "HT", "3T", "46", "40", - "MKK", "5G", "40M", "HT", "3T", "46", "40", - "FCC", "5G", "40M", "HT", "3T", "54", "46", - "ETSI", "5G", "40M", "HT", "3T", "54", "40", - "MKK", "5G", "40M", "HT", "3T", "54", "40", - "FCC", "5G", "40M", "HT", "3T", "62", "46", - "ETSI", "5G", "40M", "HT", "3T", "62", "40", - "MKK", "5G", "40M", "HT", "3T", "62", "40", - "FCC", "5G", "40M", "HT", "3T", "102", "46", - "ETSI", "5G", "40M", "HT", "3T", "102", "40", - "MKK", "5G", "40M", "HT", "3T", "102", "40", - "FCC", "5G", "40M", "HT", "3T", "110", "46", - "ETSI", "5G", "40M", "HT", "3T", "110", "40", - "MKK", "5G", "40M", "HT", "3T", "110", "40", - "FCC", "5G", "40M", "HT", "3T", "118", "46", - "ETSI", "5G", "40M", "HT", "3T", "118", "40", - "MKK", "5G", "40M", "HT", "3T", "118", "40", - "FCC", "5G", "40M", "HT", "3T", "126", "46", - "ETSI", "5G", "40M", "HT", "3T", "126", "40", - "MKK", "5G", "40M", "HT", "3T", "126", "40", - "FCC", "5G", "40M", "HT", "3T", "134", "46", - "ETSI", "5G", "40M", "HT", "3T", "134", "40", - "MKK", "5G", "40M", "HT", "3T", "134", "40", - "FCC", "5G", "40M", "HT", "3T", "151", "46", - "ETSI", "5G", "40M", "HT", "3T", "151", "40", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "46", - "ETSI", "5G", "40M", "HT", "3T", "159", "40", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "46", - "ETSI", "5G", "40M", "HT", "4T", "38", "40", - "MKK", "5G", "40M", "HT", "4T", "38", "40", - "FCC", "5G", "40M", "HT", "4T", "46", "46", - "ETSI", "5G", "40M", "HT", "4T", "46", "40", - "MKK", "5G", "40M", "HT", "4T", "46", "40", - "FCC", "5G", "40M", "HT", "4T", "54", "46", - "ETSI", "5G", "40M", "HT", "4T", "54", "40", - "MKK", "5G", "40M", "HT", "4T", "54", "40", - "FCC", "5G", "40M", "HT", "4T", "62", "46", - "ETSI", "5G", "40M", "HT", "4T", "62", "40", - "MKK", "5G", "40M", "HT", "4T", "62", "40", - "FCC", "5G", "40M", "HT", "4T", "102", "46", - "ETSI", "5G", "40M", "HT", "4T", "102", "40", - "MKK", "5G", "40M", "HT", "4T", "102", "40", - "FCC", "5G", "40M", "HT", "4T", "110", "46", - "ETSI", "5G", "40M", "HT", "4T", "110", "40", - "MKK", "5G", "40M", "HT", "4T", "110", "40", - "FCC", "5G", "40M", "HT", "4T", "118", "46", - "ETSI", "5G", "40M", "HT", "4T", "118", "40", - "MKK", "5G", "40M", "HT", "4T", "118", "40", - "FCC", "5G", "40M", "HT", "4T", "126", "46", - "ETSI", "5G", "40M", "HT", "4T", "126", "40", - "MKK", "5G", "40M", "HT", "4T", "126", "40", - "FCC", "5G", "40M", "HT", "4T", "134", "46", - "ETSI", "5G", "40M", "HT", "4T", "134", "40", - "MKK", "5G", "40M", "HT", "4T", "134", "40", - "FCC", "5G", "40M", "HT", "4T", "151", "46", - "ETSI", "5G", "40M", "HT", "4T", "151", "40", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "46", - "ETSI", "5G", "40M", "HT", "4T", "159", "40", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "46", - "ETSI", "5G", "80M", "VHT", "1T", "42", "40", - "MKK", "5G", "80M", "VHT", "1T", "42", "40", - "FCC", "5G", "80M", "VHT", "1T", "58", "46", - "ETSI", "5G", "80M", "VHT", "1T", "58", "40", - "MKK", "5G", "80M", "VHT", "1T", "58", "40", - "FCC", "5G", "80M", "VHT", "1T", "106", "46", - "ETSI", "5G", "80M", "VHT", "1T", "106", "40", - "MKK", "5G", "80M", "VHT", "1T", "106", "40", - "FCC", "5G", "80M", "VHT", "1T", "122", "46", - "ETSI", "5G", "80M", "VHT", "1T", "122", "40", - "MKK", "5G", "80M", "VHT", "1T", "122", "40", - "FCC", "5G", "80M", "VHT", "1T", "155", "46", - "ETSI", "5G", "80M", "VHT", "1T", "155", "40", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "46", - "ETSI", "5G", "80M", "VHT", "2T", "42", "40", - "MKK", "5G", "80M", "VHT", "2T", "42", "40", - "FCC", "5G", "80M", "VHT", "2T", "58", "46", - "ETSI", "5G", "80M", "VHT", "2T", "58", "40", - "MKK", "5G", "80M", "VHT", "2T", "58", "40", - "FCC", "5G", "80M", "VHT", "2T", "106", "46", - "ETSI", "5G", "80M", "VHT", "2T", "106", "40", - "MKK", "5G", "80M", "VHT", "2T", "106", "40", - "FCC", "5G", "80M", "VHT", "2T", "122", "46", - "ETSI", "5G", "80M", "VHT", "2T", "122", "40", - "MKK", "5G", "80M", "VHT", "2T", "122", "40", - "FCC", "5G", "80M", "VHT", "2T", "155", "46", - "ETSI", "5G", "80M", "VHT", "2T", "155", "40", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "46", - "ETSI", "5G", "80M", "VHT", "3T", "42", "40", - "MKK", "5G", "80M", "VHT", "3T", "42", "40", - "FCC", "5G", "80M", "VHT", "3T", "58", "46", - "ETSI", "5G", "80M", "VHT", "3T", "58", "40", - "MKK", "5G", "80M", "VHT", "3T", "58", "40", - "FCC", "5G", "80M", "VHT", "3T", "106", "46", - "ETSI", "5G", "80M", "VHT", "3T", "106", "40", - "MKK", "5G", "80M", "VHT", "3T", "106", "40", - "FCC", "5G", "80M", "VHT", "3T", "122", "46", - "ETSI", "5G", "80M", "VHT", "3T", "122", "40", - "MKK", "5G", "80M", "VHT", "3T", "122", "40", - "FCC", "5G", "80M", "VHT", "3T", "155", "46", - "ETSI", "5G", "80M", "VHT", "3T", "155", "40", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "46", - "ETSI", "5G", "80M", "VHT", "4T", "42", "40", - "MKK", "5G", "80M", "VHT", "4T", "42", "40", - "FCC", "5G", "80M", "VHT", "4T", "58", "46", - "ETSI", "5G", "80M", "VHT", "4T", "58", "40", - "MKK", "5G", "80M", "VHT", "4T", "58", "40", - "FCC", "5G", "80M", "VHT", "4T", "106", "46", - "ETSI", "5G", "80M", "VHT", "4T", "106", "40", - "MKK", "5G", "80M", "VHT", "4T", "106", "40", - "FCC", "5G", "80M", "VHT", "4T", "122", "46", - "ETSI", "5G", "80M", "VHT", "4T", "122", "40", - "MKK", "5G", "80M", "VHT", "4T", "122", "40", - "FCC", "5G", "80M", "VHT", "4T", "155", "46", - "ETSI", "5G", "80M", "VHT", "4T", "155", "40", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type3)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type3; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type3)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type3; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type4.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type4[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "42", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "50", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "42", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "42", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "42", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "42", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "42", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "42", - "MKK", "2.4G", "20M", "HT", "1T", "01", "42", - "FCC", "2.4G", "20M", "HT", "1T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "42", - "MKK", "2.4G", "20M", "HT", "1T", "02", "42", - "FCC", "2.4G", "20M", "HT", "1T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "42", - "MKK", "2.4G", "20M", "HT", "1T", "03", "42", - "FCC", "2.4G", "20M", "HT", "1T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "42", - "MKK", "2.4G", "20M", "HT", "1T", "04", "42", - "FCC", "2.4G", "20M", "HT", "1T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "42", - "MKK", "2.4G", "20M", "HT", "1T", "05", "42", - "FCC", "2.4G", "20M", "HT", "1T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "42", - "MKK", "2.4G", "20M", "HT", "1T", "06", "42", - "FCC", "2.4G", "20M", "HT", "1T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "42", - "MKK", "2.4G", "20M", "HT", "1T", "07", "42", - "FCC", "2.4G", "20M", "HT", "1T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "42", - "MKK", "2.4G", "20M", "HT", "1T", "08", "42", - "FCC", "2.4G", "20M", "HT", "1T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "42", - "MKK", "2.4G", "20M", "HT", "1T", "09", "42", - "FCC", "2.4G", "20M", "HT", "1T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "42", - "MKK", "2.4G", "20M", "HT", "1T", "10", "42", - "FCC", "2.4G", "20M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "42", - "MKK", "2.4G", "20M", "HT", "1T", "11", "42", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "42", - "MKK", "2.4G", "20M", "HT", "1T", "12", "42", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "42", - "MKK", "2.4G", "20M", "HT", "1T", "13", "42", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", - "MKK", "2.4G", "20M", "HT", "2T", "01", "40", - "FCC", "2.4G", "20M", "HT", "2T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", - "MKK", "2.4G", "20M", "HT", "2T", "02", "40", - "FCC", "2.4G", "20M", "HT", "2T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", - "MKK", "2.4G", "20M", "HT", "2T", "03", "40", - "FCC", "2.4G", "20M", "HT", "2T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", - "MKK", "2.4G", "20M", "HT", "2T", "04", "40", - "FCC", "2.4G", "20M", "HT", "2T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", - "MKK", "2.4G", "20M", "HT", "2T", "05", "40", - "FCC", "2.4G", "20M", "HT", "2T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", - "MKK", "2.4G", "20M", "HT", "2T", "06", "40", - "FCC", "2.4G", "20M", "HT", "2T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", - "MKK", "2.4G", "20M", "HT", "2T", "07", "40", - "FCC", "2.4G", "20M", "HT", "2T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", - "MKK", "2.4G", "20M", "HT", "2T", "08", "40", - "FCC", "2.4G", "20M", "HT", "2T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", - "MKK", "2.4G", "20M", "HT", "2T", "09", "40", - "FCC", "2.4G", "20M", "HT", "2T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", - "MKK", "2.4G", "20M", "HT", "2T", "10", "40", - "FCC", "2.4G", "20M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", - "MKK", "2.4G", "20M", "HT", "2T", "11", "40", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", - "MKK", "2.4G", "20M", "HT", "2T", "12", "40", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", - "MKK", "2.4G", "20M", "HT", "2T", "13", "40", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", - "MKK", "2.4G", "20M", "HT", "3T", "01", "40", - "FCC", "2.4G", "20M", "HT", "3T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", - "MKK", "2.4G", "20M", "HT", "3T", "02", "40", - "FCC", "2.4G", "20M", "HT", "3T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", - "MKK", "2.4G", "20M", "HT", "3T", "03", "40", - "FCC", "2.4G", "20M", "HT", "3T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", - "MKK", "2.4G", "20M", "HT", "3T", "04", "40", - "FCC", "2.4G", "20M", "HT", "3T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", - "MKK", "2.4G", "20M", "HT", "3T", "05", "40", - "FCC", "2.4G", "20M", "HT", "3T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", - "MKK", "2.4G", "20M", "HT", "3T", "06", "40", - "FCC", "2.4G", "20M", "HT", "3T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", - "MKK", "2.4G", "20M", "HT", "3T", "07", "40", - "FCC", "2.4G", "20M", "HT", "3T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", - "MKK", "2.4G", "20M", "HT", "3T", "08", "40", - "FCC", "2.4G", "20M", "HT", "3T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", - "MKK", "2.4G", "20M", "HT", "3T", "09", "40", - "FCC", "2.4G", "20M", "HT", "3T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", - "MKK", "2.4G", "20M", "HT", "3T", "10", "40", - "FCC", "2.4G", "20M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", - "MKK", "2.4G", "20M", "HT", "3T", "11", "40", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", - "MKK", "2.4G", "20M", "HT", "3T", "12", "40", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", - "MKK", "2.4G", "20M", "HT", "3T", "13", "40", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", - "MKK", "2.4G", "20M", "HT", "4T", "01", "40", - "FCC", "2.4G", "20M", "HT", "4T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", - "MKK", "2.4G", "20M", "HT", "4T", "02", "40", - "FCC", "2.4G", "20M", "HT", "4T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", - "MKK", "2.4G", "20M", "HT", "4T", "03", "40", - "FCC", "2.4G", "20M", "HT", "4T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", - "MKK", "2.4G", "20M", "HT", "4T", "04", "40", - "FCC", "2.4G", "20M", "HT", "4T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", - "MKK", "2.4G", "20M", "HT", "4T", "05", "40", - "FCC", "2.4G", "20M", "HT", "4T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", - "MKK", "2.4G", "20M", "HT", "4T", "06", "40", - "FCC", "2.4G", "20M", "HT", "4T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", - "MKK", "2.4G", "20M", "HT", "4T", "07", "40", - "FCC", "2.4G", "20M", "HT", "4T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", - "MKK", "2.4G", "20M", "HT", "4T", "08", "40", - "FCC", "2.4G", "20M", "HT", "4T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", - "MKK", "2.4G", "20M", "HT", "4T", "09", "40", - "FCC", "2.4G", "20M", "HT", "4T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", - "MKK", "2.4G", "20M", "HT", "4T", "10", "40", - "FCC", "2.4G", "20M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", - "MKK", "2.4G", "20M", "HT", "4T", "11", "40", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", - "MKK", "2.4G", "20M", "HT", "4T", "12", "40", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", - "MKK", "2.4G", "20M", "HT", "4T", "13", "40", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", - "MKK", "2.4G", "40M", "HT", "1T", "12", "34", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", - "MKK", "2.4G", "40M", "HT", "1T", "13", "34", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "34", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "34", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "34", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "34", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", - "MKK", "2.4G", "40M", "HT", "2T", "12", "34", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", - "MKK", "2.4G", "40M", "HT", "2T", "13", "34", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", - "MKK", "2.4G", "40M", "HT", "3T", "03", "34", - "FCC", "2.4G", "40M", "HT", "3T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", - "MKK", "2.4G", "40M", "HT", "3T", "04", "34", - "FCC", "2.4G", "40M", "HT", "3T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", - "MKK", "2.4G", "40M", "HT", "3T", "05", "34", - "FCC", "2.4G", "40M", "HT", "3T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", - "MKK", "2.4G", "40M", "HT", "3T", "06", "34", - "FCC", "2.4G", "40M", "HT", "3T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", - "MKK", "2.4G", "40M", "HT", "3T", "07", "34", - "FCC", "2.4G", "40M", "HT", "3T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", - "MKK", "2.4G", "40M", "HT", "3T", "08", "34", - "FCC", "2.4G", "40M", "HT", "3T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", - "MKK", "2.4G", "40M", "HT", "3T", "09", "34", - "FCC", "2.4G", "40M", "HT", "3T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", - "MKK", "2.4G", "40M", "HT", "3T", "10", "34", - "FCC", "2.4G", "40M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", - "MKK", "2.4G", "40M", "HT", "3T", "11", "34", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", - "MKK", "2.4G", "40M", "HT", "3T", "12", "34", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", - "MKK", "2.4G", "40M", "HT", "3T", "13", "34", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", - "MKK", "2.4G", "40M", "HT", "4T", "03", "34", - "FCC", "2.4G", "40M", "HT", "4T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", - "MKK", "2.4G", "40M", "HT", "4T", "04", "34", - "FCC", "2.4G", "40M", "HT", "4T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", - "MKK", "2.4G", "40M", "HT", "4T", "05", "34", - "FCC", "2.4G", "40M", "HT", "4T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", - "MKK", "2.4G", "40M", "HT", "4T", "06", "34", - "FCC", "2.4G", "40M", "HT", "4T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", - "MKK", "2.4G", "40M", "HT", "4T", "07", "34", - "FCC", "2.4G", "40M", "HT", "4T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", - "MKK", "2.4G", "40M", "HT", "4T", "08", "34", - "FCC", "2.4G", "40M", "HT", "4T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", - "MKK", "2.4G", "40M", "HT", "4T", "09", "34", - "FCC", "2.4G", "40M", "HT", "4T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", - "MKK", "2.4G", "40M", "HT", "4T", "10", "34", - "FCC", "2.4G", "40M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", - "MKK", "2.4G", "40M", "HT", "4T", "11", "34", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", - "MKK", "2.4G", "40M", "HT", "4T", "12", "34", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", - "MKK", "2.4G", "40M", "HT", "4T", "13", "34", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "42", - "MKK", "5G", "20M", "OFDM", "1T", "36", "42", - "FCC", "5G", "20M", "OFDM", "1T", "40", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "42", - "MKK", "5G", "20M", "OFDM", "1T", "40", "42", - "FCC", "5G", "20M", "OFDM", "1T", "44", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "42", - "MKK", "5G", "20M", "OFDM", "1T", "44", "42", - "FCC", "5G", "20M", "OFDM", "1T", "48", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "42", - "MKK", "5G", "20M", "OFDM", "1T", "48", "42", - "FCC", "5G", "20M", "OFDM", "1T", "52", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "42", - "MKK", "5G", "20M", "OFDM", "1T", "52", "42", - "FCC", "5G", "20M", "OFDM", "1T", "56", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "42", - "MKK", "5G", "20M", "OFDM", "1T", "56", "42", - "FCC", "5G", "20M", "OFDM", "1T", "60", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "42", - "MKK", "5G", "20M", "OFDM", "1T", "60", "42", - "FCC", "5G", "20M", "OFDM", "1T", "64", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "42", - "MKK", "5G", "20M", "OFDM", "1T", "64", "42", - "FCC", "5G", "20M", "OFDM", "1T", "100", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "42", - "MKK", "5G", "20M", "OFDM", "1T", "100", "42", - "FCC", "5G", "20M", "OFDM", "1T", "104", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "42", - "MKK", "5G", "20M", "OFDM", "1T", "104", "42", - "FCC", "5G", "20M", "OFDM", "1T", "108", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "42", - "MKK", "5G", "20M", "OFDM", "1T", "108", "42", - "FCC", "5G", "20M", "OFDM", "1T", "112", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "42", - "MKK", "5G", "20M", "OFDM", "1T", "112", "42", - "FCC", "5G", "20M", "OFDM", "1T", "116", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "42", - "MKK", "5G", "20M", "OFDM", "1T", "116", "42", - "FCC", "5G", "20M", "OFDM", "1T", "120", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "42", - "MKK", "5G", "20M", "OFDM", "1T", "120", "42", - "FCC", "5G", "20M", "OFDM", "1T", "124", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "42", - "MKK", "5G", "20M", "OFDM", "1T", "124", "42", - "FCC", "5G", "20M", "OFDM", "1T", "128", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "42", - "MKK", "5G", "20M", "OFDM", "1T", "128", "42", - "FCC", "5G", "20M", "OFDM", "1T", "132", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "42", - "MKK", "5G", "20M", "OFDM", "1T", "132", "42", - "FCC", "5G", "20M", "OFDM", "1T", "136", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "42", - "MKK", "5G", "20M", "OFDM", "1T", "136", "42", - "FCC", "5G", "20M", "OFDM", "1T", "140", "40", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", - "MKK", "5G", "20M", "OFDM", "1T", "140", "40", - "FCC", "5G", "20M", "OFDM", "1T", "149", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "44", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "44", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "36", - "ETSI", "5G", "20M", "HT", "1T", "48", "36", - "MKK", "5G", "20M", "HT", "1T", "48", "36", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "36", - "MKK", "5G", "20M", "HT", "1T", "52", "36", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "32", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "32", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "30", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "40", - "ETSI", "5G", "20M", "HT", "1T", "149", "40", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "40", - "ETSI", "5G", "20M", "HT", "1T", "153", "40", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "40", - "ETSI", "5G", "20M", "HT", "1T", "157", "40", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "40", - "ETSI", "5G", "20M", "HT", "1T", "161", "40", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "42", - "ETSI", "5G", "20M", "HT", "1T", "165", "42", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "32", - "ETSI", "5G", "20M", "HT", "2T", "36", "32", - "MKK", "5G", "20M", "HT", "2T", "36", "32", - "FCC", "5G", "20M", "HT", "2T", "40", "32", - "ETSI", "5G", "20M", "HT", "2T", "40", "32", - "MKK", "5G", "20M", "HT", "2T", "40", "32", - "FCC", "5G", "20M", "HT", "2T", "44", "32", - "ETSI", "5G", "20M", "HT", "2T", "44", "32", - "MKK", "5G", "20M", "HT", "2T", "44", "32", - "FCC", "5G", "20M", "HT", "2T", "48", "36", - "ETSI", "5G", "20M", "HT", "2T", "48", "36", - "MKK", "5G", "20M", "HT", "2T", "48", "36", - "FCC", "5G", "20M", "HT", "2T", "52", "36", - "ETSI", "5G", "20M", "HT", "2T", "52", "36", - "MKK", "5G", "20M", "HT", "2T", "52", "36", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "32", - "MKK", "5G", "20M", "HT", "2T", "56", "32", - "FCC", "5G", "20M", "HT", "2T", "60", "32", - "ETSI", "5G", "20M", "HT", "2T", "60", "32", - "MKK", "5G", "20M", "HT", "2T", "60", "32", - "FCC", "5G", "20M", "HT", "2T", "64", "32", - "ETSI", "5G", "20M", "HT", "2T", "64", "32", - "MKK", "5G", "20M", "HT", "2T", "64", "32", - "FCC", "5G", "20M", "HT", "2T", "100", "32", - "ETSI", "5G", "20M", "HT", "2T", "100", "32", - "MKK", "5G", "20M", "HT", "2T", "100", "32", - "FCC", "5G", "20M", "HT", "2T", "104", "32", - "ETSI", "5G", "20M", "HT", "2T", "104", "32", - "MKK", "5G", "20M", "HT", "2T", "104", "32", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "32", - "MKK", "5G", "20M", "HT", "2T", "108", "32", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "32", - "MKK", "5G", "20M", "HT", "2T", "112", "32", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "32", - "MKK", "5G", "20M", "HT", "2T", "116", "32", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "32", - "MKK", "5G", "20M", "HT", "2T", "120", "32", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "32", - "MKK", "5G", "20M", "HT", "2T", "124", "32", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "32", - "MKK", "5G", "20M", "HT", "2T", "128", "32", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "32", - "MKK", "5G", "20M", "HT", "2T", "132", "32", - "FCC", "5G", "20M", "HT", "2T", "136", "32", - "ETSI", "5G", "20M", "HT", "2T", "136", "32", - "MKK", "5G", "20M", "HT", "2T", "136", "32", - "FCC", "5G", "20M", "HT", "2T", "140", "30", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "40", - "ETSI", "5G", "20M", "HT", "2T", "149", "40", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "40", - "ETSI", "5G", "20M", "HT", "2T", "153", "40", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "40", - "ETSI", "5G", "20M", "HT", "2T", "157", "40", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "40", - "ETSI", "5G", "20M", "HT", "2T", "161", "40", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "42", - "ETSI", "5G", "20M", "HT", "2T", "165", "42", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "32", - "ETSI", "5G", "20M", "HT", "3T", "36", "32", - "MKK", "5G", "20M", "HT", "3T", "36", "32", - "FCC", "5G", "20M", "HT", "3T", "40", "32", - "ETSI", "5G", "20M", "HT", "3T", "40", "32", - "MKK", "5G", "20M", "HT", "3T", "40", "32", - "FCC", "5G", "20M", "HT", "3T", "44", "32", - "ETSI", "5G", "20M", "HT", "3T", "44", "32", - "MKK", "5G", "20M", "HT", "3T", "44", "32", - "FCC", "5G", "20M", "HT", "3T", "48", "36", - "ETSI", "5G", "20M", "HT", "3T", "48", "36", - "MKK", "5G", "20M", "HT", "3T", "48", "36", - "FCC", "5G", "20M", "HT", "3T", "52", "36", - "ETSI", "5G", "20M", "HT", "3T", "52", "36", - "MKK", "5G", "20M", "HT", "3T", "52", "36", - "FCC", "5G", "20M", "HT", "3T", "56", "32", - "ETSI", "5G", "20M", "HT", "3T", "56", "32", - "MKK", "5G", "20M", "HT", "3T", "56", "32", - "FCC", "5G", "20M", "HT", "3T", "60", "32", - "ETSI", "5G", "20M", "HT", "3T", "60", "32", - "MKK", "5G", "20M", "HT", "3T", "60", "32", - "FCC", "5G", "20M", "HT", "3T", "64", "32", - "ETSI", "5G", "20M", "HT", "3T", "64", "32", - "MKK", "5G", "20M", "HT", "3T", "64", "32", - "FCC", "5G", "20M", "HT", "3T", "100", "32", - "ETSI", "5G", "20M", "HT", "3T", "100", "32", - "MKK", "5G", "20M", "HT", "3T", "100", "32", - "FCC", "5G", "20M", "HT", "3T", "104", "32", - "ETSI", "5G", "20M", "HT", "3T", "104", "32", - "MKK", "5G", "20M", "HT", "3T", "104", "32", - "FCC", "5G", "20M", "HT", "3T", "108", "32", - "ETSI", "5G", "20M", "HT", "3T", "108", "32", - "MKK", "5G", "20M", "HT", "3T", "108", "32", - "FCC", "5G", "20M", "HT", "3T", "112", "32", - "ETSI", "5G", "20M", "HT", "3T", "112", "32", - "MKK", "5G", "20M", "HT", "3T", "112", "32", - "FCC", "5G", "20M", "HT", "3T", "116", "32", - "ETSI", "5G", "20M", "HT", "3T", "116", "32", - "MKK", "5G", "20M", "HT", "3T", "116", "32", - "FCC", "5G", "20M", "HT", "3T", "120", "32", - "ETSI", "5G", "20M", "HT", "3T", "120", "32", - "MKK", "5G", "20M", "HT", "3T", "120", "32", - "FCC", "5G", "20M", "HT", "3T", "124", "32", - "ETSI", "5G", "20M", "HT", "3T", "124", "32", - "MKK", "5G", "20M", "HT", "3T", "124", "32", - "FCC", "5G", "20M", "HT", "3T", "128", "32", - "ETSI", "5G", "20M", "HT", "3T", "128", "32", - "MKK", "5G", "20M", "HT", "3T", "128", "32", - "FCC", "5G", "20M", "HT", "3T", "132", "32", - "ETSI", "5G", "20M", "HT", "3T", "132", "32", - "MKK", "5G", "20M", "HT", "3T", "132", "32", - "FCC", "5G", "20M", "HT", "3T", "136", "32", - "ETSI", "5G", "20M", "HT", "3T", "136", "32", - "MKK", "5G", "20M", "HT", "3T", "136", "32", - "FCC", "5G", "20M", "HT", "3T", "140", "30", - "ETSI", "5G", "20M", "HT", "3T", "140", "30", - "MKK", "5G", "20M", "HT", "3T", "140", "30", - "FCC", "5G", "20M", "HT", "3T", "149", "40", - "ETSI", "5G", "20M", "HT", "3T", "149", "40", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "40", - "ETSI", "5G", "20M", "HT", "3T", "153", "40", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "40", - "ETSI", "5G", "20M", "HT", "3T", "157", "40", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "40", - "ETSI", "5G", "20M", "HT", "3T", "161", "40", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "42", - "ETSI", "5G", "20M", "HT", "3T", "165", "42", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "32", - "ETSI", "5G", "20M", "HT", "4T", "36", "32", - "MKK", "5G", "20M", "HT", "4T", "36", "32", - "FCC", "5G", "20M", "HT", "4T", "40", "32", - "ETSI", "5G", "20M", "HT", "4T", "40", "32", - "MKK", "5G", "20M", "HT", "4T", "40", "32", - "FCC", "5G", "20M", "HT", "4T", "44", "32", - "ETSI", "5G", "20M", "HT", "4T", "44", "32", - "MKK", "5G", "20M", "HT", "4T", "44", "32", - "FCC", "5G", "20M", "HT", "4T", "48", "36", - "ETSI", "5G", "20M", "HT", "4T", "48", "36", - "MKK", "5G", "20M", "HT", "4T", "48", "36", - "FCC", "5G", "20M", "HT", "4T", "52", "36", - "ETSI", "5G", "20M", "HT", "4T", "52", "36", - "MKK", "5G", "20M", "HT", "4T", "52", "36", - "FCC", "5G", "20M", "HT", "4T", "56", "32", - "ETSI", "5G", "20M", "HT", "4T", "56", "32", - "MKK", "5G", "20M", "HT", "4T", "56", "32", - "FCC", "5G", "20M", "HT", "4T", "60", "32", - "ETSI", "5G", "20M", "HT", "4T", "60", "32", - "MKK", "5G", "20M", "HT", "4T", "60", "32", - "FCC", "5G", "20M", "HT", "4T", "64", "32", - "ETSI", "5G", "20M", "HT", "4T", "64", "32", - "MKK", "5G", "20M", "HT", "4T", "64", "32", - "FCC", "5G", "20M", "HT", "4T", "100", "32", - "ETSI", "5G", "20M", "HT", "4T", "100", "32", - "MKK", "5G", "20M", "HT", "4T", "100", "32", - "FCC", "5G", "20M", "HT", "4T", "104", "32", - "ETSI", "5G", "20M", "HT", "4T", "104", "32", - "MKK", "5G", "20M", "HT", "4T", "104", "32", - "FCC", "5G", "20M", "HT", "4T", "108", "32", - "ETSI", "5G", "20M", "HT", "4T", "108", "32", - "MKK", "5G", "20M", "HT", "4T", "108", "32", - "FCC", "5G", "20M", "HT", "4T", "112", "32", - "ETSI", "5G", "20M", "HT", "4T", "112", "32", - "MKK", "5G", "20M", "HT", "4T", "112", "32", - "FCC", "5G", "20M", "HT", "4T", "116", "32", - "ETSI", "5G", "20M", "HT", "4T", "116", "32", - "MKK", "5G", "20M", "HT", "4T", "116", "32", - "FCC", "5G", "20M", "HT", "4T", "120", "32", - "ETSI", "5G", "20M", "HT", "4T", "120", "32", - "MKK", "5G", "20M", "HT", "4T", "120", "32", - "FCC", "5G", "20M", "HT", "4T", "124", "32", - "ETSI", "5G", "20M", "HT", "4T", "124", "32", - "MKK", "5G", "20M", "HT", "4T", "124", "32", - "FCC", "5G", "20M", "HT", "4T", "128", "32", - "ETSI", "5G", "20M", "HT", "4T", "128", "32", - "MKK", "5G", "20M", "HT", "4T", "128", "32", - "FCC", "5G", "20M", "HT", "4T", "132", "32", - "ETSI", "5G", "20M", "HT", "4T", "132", "32", - "MKK", "5G", "20M", "HT", "4T", "132", "32", - "FCC", "5G", "20M", "HT", "4T", "136", "32", - "ETSI", "5G", "20M", "HT", "4T", "136", "32", - "MKK", "5G", "20M", "HT", "4T", "136", "32", - "FCC", "5G", "20M", "HT", "4T", "140", "30", - "ETSI", "5G", "20M", "HT", "4T", "140", "30", - "MKK", "5G", "20M", "HT", "4T", "140", "30", - "FCC", "5G", "20M", "HT", "4T", "149", "40", - "ETSI", "5G", "20M", "HT", "4T", "149", "40", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "40", - "ETSI", "5G", "20M", "HT", "4T", "153", "40", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "40", - "ETSI", "5G", "20M", "HT", "4T", "157", "40", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "40", - "ETSI", "5G", "20M", "HT", "4T", "161", "40", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "42", - "ETSI", "5G", "20M", "HT", "4T", "165", "42", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "32", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "36", - "ETSI", "5G", "40M", "HT", "1T", "46", "36", - "MKK", "5G", "40M", "HT", "1T", "46", "36", - "FCC", "5G", "40M", "HT", "1T", "54", "36", - "ETSI", "5G", "40M", "HT", "1T", "54", "36", - "MKK", "5G", "40M", "HT", "1T", "54", "36", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "30", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "36", - "ETSI", "5G", "40M", "HT", "1T", "134", "36", - "MKK", "5G", "40M", "HT", "1T", "134", "36", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "36", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "40", - "ETSI", "5G", "40M", "HT", "1T", "159", "40", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "32", - "ETSI", "5G", "40M", "HT", "2T", "38", "32", - "MKK", "5G", "40M", "HT", "2T", "38", "32", - "FCC", "5G", "40M", "HT", "2T", "46", "36", - "ETSI", "5G", "40M", "HT", "2T", "46", "36", - "MKK", "5G", "40M", "HT", "2T", "46", "36", - "FCC", "5G", "40M", "HT", "2T", "54", "36", - "ETSI", "5G", "40M", "HT", "2T", "54", "36", - "MKK", "5G", "40M", "HT", "2T", "54", "36", - "FCC", "5G", "40M", "HT", "2T", "62", "32", - "ETSI", "5G", "40M", "HT", "2T", "62", "32", - "MKK", "5G", "40M", "HT", "2T", "62", "32", - "FCC", "5G", "40M", "HT", "2T", "102", "30", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "32", - "ETSI", "5G", "40M", "HT", "2T", "110", "32", - "MKK", "5G", "40M", "HT", "2T", "110", "32", - "FCC", "5G", "40M", "HT", "2T", "118", "32", - "ETSI", "5G", "40M", "HT", "2T", "118", "32", - "MKK", "5G", "40M", "HT", "2T", "118", "32", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "32", - "MKK", "5G", "40M", "HT", "2T", "126", "32", - "FCC", "5G", "40M", "HT", "2T", "134", "36", - "ETSI", "5G", "40M", "HT", "2T", "134", "36", - "MKK", "5G", "40M", "HT", "2T", "134", "36", - "FCC", "5G", "40M", "HT", "2T", "151", "36", - "ETSI", "5G", "40M", "HT", "2T", "151", "36", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "40", - "ETSI", "5G", "40M", "HT", "2T", "159", "40", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "32", - "ETSI", "5G", "40M", "HT", "3T", "38", "32", - "MKK", "5G", "40M", "HT", "3T", "38", "32", - "FCC", "5G", "40M", "HT", "3T", "46", "36", - "ETSI", "5G", "40M", "HT", "3T", "46", "36", - "MKK", "5G", "40M", "HT", "3T", "46", "36", - "FCC", "5G", "40M", "HT", "3T", "54", "36", - "ETSI", "5G", "40M", "HT", "3T", "54", "36", - "MKK", "5G", "40M", "HT", "3T", "54", "36", - "FCC", "5G", "40M", "HT", "3T", "62", "32", - "ETSI", "5G", "40M", "HT", "3T", "62", "32", - "MKK", "5G", "40M", "HT", "3T", "62", "32", - "FCC", "5G", "40M", "HT", "3T", "102", "30", - "ETSI", "5G", "40M", "HT", "3T", "102", "30", - "MKK", "5G", "40M", "HT", "3T", "102", "30", - "FCC", "5G", "40M", "HT", "3T", "110", "32", - "ETSI", "5G", "40M", "HT", "3T", "110", "32", - "MKK", "5G", "40M", "HT", "3T", "110", "32", - "FCC", "5G", "40M", "HT", "3T", "118", "32", - "ETSI", "5G", "40M", "HT", "3T", "118", "32", - "MKK", "5G", "40M", "HT", "3T", "118", "32", - "FCC", "5G", "40M", "HT", "3T", "126", "32", - "ETSI", "5G", "40M", "HT", "3T", "126", "32", - "MKK", "5G", "40M", "HT", "3T", "126", "32", - "FCC", "5G", "40M", "HT", "3T", "134", "36", - "ETSI", "5G", "40M", "HT", "3T", "134", "36", - "MKK", "5G", "40M", "HT", "3T", "134", "36", - "FCC", "5G", "40M", "HT", "3T", "151", "36", - "ETSI", "5G", "40M", "HT", "3T", "151", "36", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "40", - "ETSI", "5G", "40M", "HT", "3T", "159", "40", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "32", - "ETSI", "5G", "40M", "HT", "4T", "38", "32", - "MKK", "5G", "40M", "HT", "4T", "38", "32", - "FCC", "5G", "40M", "HT", "4T", "46", "36", - "ETSI", "5G", "40M", "HT", "4T", "46", "36", - "MKK", "5G", "40M", "HT", "4T", "46", "36", - "FCC", "5G", "40M", "HT", "4T", "54", "36", - "ETSI", "5G", "40M", "HT", "4T", "54", "36", - "MKK", "5G", "40M", "HT", "4T", "54", "36", - "FCC", "5G", "40M", "HT", "4T", "62", "32", - "ETSI", "5G", "40M", "HT", "4T", "62", "32", - "MKK", "5G", "40M", "HT", "4T", "62", "32", - "FCC", "5G", "40M", "HT", "4T", "102", "30", - "ETSI", "5G", "40M", "HT", "4T", "102", "30", - "MKK", "5G", "40M", "HT", "4T", "102", "30", - "FCC", "5G", "40M", "HT", "4T", "110", "32", - "ETSI", "5G", "40M", "HT", "4T", "110", "32", - "MKK", "5G", "40M", "HT", "4T", "110", "32", - "FCC", "5G", "40M", "HT", "4T", "118", "32", - "ETSI", "5G", "40M", "HT", "4T", "118", "32", - "MKK", "5G", "40M", "HT", "4T", "118", "32", - "FCC", "5G", "40M", "HT", "4T", "126", "32", - "ETSI", "5G", "40M", "HT", "4T", "126", "32", - "MKK", "5G", "40M", "HT", "4T", "126", "32", - "FCC", "5G", "40M", "HT", "4T", "134", "36", - "ETSI", "5G", "40M", "HT", "4T", "134", "36", - "MKK", "5G", "40M", "HT", "4T", "134", "36", - "FCC", "5G", "40M", "HT", "4T", "151", "36", - "ETSI", "5G", "40M", "HT", "4T", "151", "36", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "40", - "ETSI", "5G", "40M", "HT", "4T", "159", "40", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "34", - "ETSI", "5G", "80M", "VHT", "1T", "42", "34", - "MKK", "5G", "80M", "VHT", "1T", "42", "34", - "FCC", "5G", "80M", "VHT", "1T", "58", "34", - "ETSI", "5G", "80M", "VHT", "1T", "58", "34", - "MKK", "5G", "80M", "VHT", "1T", "58", "34", - "FCC", "5G", "80M", "VHT", "1T", "106", "32", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "34", - "MKK", "5G", "80M", "VHT", "1T", "122", "34", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "34", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "34", - "ETSI", "5G", "80M", "VHT", "2T", "42", "34", - "MKK", "5G", "80M", "VHT", "2T", "42", "34", - "FCC", "5G", "80M", "VHT", "2T", "58", "34", - "ETSI", "5G", "80M", "VHT", "2T", "58", "34", - "MKK", "5G", "80M", "VHT", "2T", "58", "34", - "FCC", "5G", "80M", "VHT", "2T", "106", "32", - "ETSI", "5G", "80M", "VHT", "2T", "106", "32", - "MKK", "5G", "80M", "VHT", "2T", "106", "32", - "FCC", "5G", "80M", "VHT", "2T", "122", "34", - "ETSI", "5G", "80M", "VHT", "2T", "122", "34", - "MKK", "5G", "80M", "VHT", "2T", "122", "34", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "34", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "34", - "ETSI", "5G", "80M", "VHT", "3T", "42", "34", - "MKK", "5G", "80M", "VHT", "3T", "42", "34", - "FCC", "5G", "80M", "VHT", "3T", "58", "34", - "ETSI", "5G", "80M", "VHT", "3T", "58", "34", - "MKK", "5G", "80M", "VHT", "3T", "58", "34", - "FCC", "5G", "80M", "VHT", "3T", "106", "32", - "ETSI", "5G", "80M", "VHT", "3T", "106", "32", - "MKK", "5G", "80M", "VHT", "3T", "106", "32", - "FCC", "5G", "80M", "VHT", "3T", "122", "34", - "ETSI", "5G", "80M", "VHT", "3T", "122", "34", - "MKK", "5G", "80M", "VHT", "3T", "122", "34", - "FCC", "5G", "80M", "VHT", "3T", "155", "34", - "ETSI", "5G", "80M", "VHT", "3T", "155", "34", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "34", - "ETSI", "5G", "80M", "VHT", "4T", "42", "34", - "MKK", "5G", "80M", "VHT", "4T", "42", "34", - "FCC", "5G", "80M", "VHT", "4T", "58", "34", - "ETSI", "5G", "80M", "VHT", "4T", "58", "34", - "MKK", "5G", "80M", "VHT", "4T", "58", "34", - "FCC", "5G", "80M", "VHT", "4T", "106", "32", - "ETSI", "5G", "80M", "VHT", "4T", "106", "32", - "MKK", "5G", "80M", "VHT", "4T", "106", "32", - "FCC", "5G", "80M", "VHT", "4T", "122", "34", - "ETSI", "5G", "80M", "VHT", "4T", "122", "34", - "MKK", "5G", "80M", "VHT", "4T", "122", "34", - "FCC", "5G", "80M", "VHT", "4T", "155", "34", - "ETSI", "5G", "80M", "VHT", "4T", "155", "34", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type4)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type4; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type4)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type4; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type5.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type5[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", - "MKK", "2.4G", "20M", "HT", "1T", "01", "40", - "FCC", "2.4G", "20M", "HT", "1T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", - "MKK", "2.4G", "20M", "HT", "1T", "02", "40", - "FCC", "2.4G", "20M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", - "MKK", "2.4G", "20M", "HT", "1T", "03", "40", - "FCC", "2.4G", "20M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", - "MKK", "2.4G", "20M", "HT", "1T", "04", "40", - "FCC", "2.4G", "20M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "40", - "MKK", "2.4G", "20M", "HT", "1T", "05", "40", - "FCC", "2.4G", "20M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "40", - "MKK", "2.4G", "20M", "HT", "1T", "06", "40", - "FCC", "2.4G", "20M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "40", - "MKK", "2.4G", "20M", "HT", "1T", "07", "40", - "FCC", "2.4G", "20M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "40", - "MKK", "2.4G", "20M", "HT", "1T", "08", "40", - "FCC", "2.4G", "20M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "40", - "MKK", "2.4G", "20M", "HT", "1T", "09", "40", - "FCC", "2.4G", "20M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "40", - "MKK", "2.4G", "20M", "HT", "1T", "10", "40", - "FCC", "2.4G", "20M", "HT", "1T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "40", - "MKK", "2.4G", "20M", "HT", "1T", "11", "40", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "40", - "MKK", "2.4G", "20M", "HT", "1T", "12", "40", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "40", - "MKK", "2.4G", "20M", "HT", "1T", "13", "40", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", - "MKK", "2.4G", "20M", "HT", "2T", "01", "40", - "FCC", "2.4G", "20M", "HT", "2T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", - "MKK", "2.4G", "20M", "HT", "2T", "02", "40", - "FCC", "2.4G", "20M", "HT", "2T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", - "MKK", "2.4G", "20M", "HT", "2T", "03", "40", - "FCC", "2.4G", "20M", "HT", "2T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", - "MKK", "2.4G", "20M", "HT", "2T", "04", "40", - "FCC", "2.4G", "20M", "HT", "2T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", - "MKK", "2.4G", "20M", "HT", "2T", "05", "40", - "FCC", "2.4G", "20M", "HT", "2T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", - "MKK", "2.4G", "20M", "HT", "2T", "06", "40", - "FCC", "2.4G", "20M", "HT", "2T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", - "MKK", "2.4G", "20M", "HT", "2T", "07", "40", - "FCC", "2.4G", "20M", "HT", "2T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", - "MKK", "2.4G", "20M", "HT", "2T", "08", "40", - "FCC", "2.4G", "20M", "HT", "2T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", - "MKK", "2.4G", "20M", "HT", "2T", "09", "40", - "FCC", "2.4G", "20M", "HT", "2T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", - "MKK", "2.4G", "20M", "HT", "2T", "10", "40", - "FCC", "2.4G", "20M", "HT", "2T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", - "MKK", "2.4G", "20M", "HT", "2T", "11", "40", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", - "MKK", "2.4G", "20M", "HT", "2T", "12", "40", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", - "MKK", "2.4G", "20M", "HT", "2T", "13", "40", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", - "MKK", "2.4G", "20M", "HT", "3T", "01", "40", - "FCC", "2.4G", "20M", "HT", "3T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", - "MKK", "2.4G", "20M", "HT", "3T", "02", "40", - "FCC", "2.4G", "20M", "HT", "3T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", - "MKK", "2.4G", "20M", "HT", "3T", "03", "40", - "FCC", "2.4G", "20M", "HT", "3T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", - "MKK", "2.4G", "20M", "HT", "3T", "04", "40", - "FCC", "2.4G", "20M", "HT", "3T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", - "MKK", "2.4G", "20M", "HT", "3T", "05", "40", - "FCC", "2.4G", "20M", "HT", "3T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", - "MKK", "2.4G", "20M", "HT", "3T", "06", "40", - "FCC", "2.4G", "20M", "HT", "3T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", - "MKK", "2.4G", "20M", "HT", "3T", "07", "40", - "FCC", "2.4G", "20M", "HT", "3T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", - "MKK", "2.4G", "20M", "HT", "3T", "08", "40", - "FCC", "2.4G", "20M", "HT", "3T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", - "MKK", "2.4G", "20M", "HT", "3T", "09", "40", - "FCC", "2.4G", "20M", "HT", "3T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", - "MKK", "2.4G", "20M", "HT", "3T", "10", "40", - "FCC", "2.4G", "20M", "HT", "3T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", - "MKK", "2.4G", "20M", "HT", "3T", "11", "40", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", - "MKK", "2.4G", "20M", "HT", "3T", "12", "40", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", - "MKK", "2.4G", "20M", "HT", "3T", "13", "40", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", - "MKK", "2.4G", "20M", "HT", "4T", "01", "40", - "FCC", "2.4G", "20M", "HT", "4T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", - "MKK", "2.4G", "20M", "HT", "4T", "02", "40", - "FCC", "2.4G", "20M", "HT", "4T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", - "MKK", "2.4G", "20M", "HT", "4T", "03", "40", - "FCC", "2.4G", "20M", "HT", "4T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", - "MKK", "2.4G", "20M", "HT", "4T", "04", "40", - "FCC", "2.4G", "20M", "HT", "4T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", - "MKK", "2.4G", "20M", "HT", "4T", "05", "40", - "FCC", "2.4G", "20M", "HT", "4T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", - "MKK", "2.4G", "20M", "HT", "4T", "06", "40", - "FCC", "2.4G", "20M", "HT", "4T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", - "MKK", "2.4G", "20M", "HT", "4T", "07", "40", - "FCC", "2.4G", "20M", "HT", "4T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", - "MKK", "2.4G", "20M", "HT", "4T", "08", "40", - "FCC", "2.4G", "20M", "HT", "4T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", - "MKK", "2.4G", "20M", "HT", "4T", "09", "40", - "FCC", "2.4G", "20M", "HT", "4T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", - "MKK", "2.4G", "20M", "HT", "4T", "10", "40", - "FCC", "2.4G", "20M", "HT", "4T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", - "MKK", "2.4G", "20M", "HT", "4T", "11", "40", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", - "MKK", "2.4G", "20M", "HT", "4T", "12", "40", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", - "MKK", "2.4G", "20M", "HT", "4T", "13", "40", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "40", - "MKK", "2.4G", "40M", "HT", "1T", "03", "40", - "FCC", "2.4G", "40M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "40", - "MKK", "2.4G", "40M", "HT", "1T", "04", "40", - "FCC", "2.4G", "40M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "40", - "MKK", "2.4G", "40M", "HT", "1T", "05", "40", - "FCC", "2.4G", "40M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "40", - "MKK", "2.4G", "40M", "HT", "1T", "06", "40", - "FCC", "2.4G", "40M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "40", - "MKK", "2.4G", "40M", "HT", "1T", "07", "40", - "FCC", "2.4G", "40M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "40", - "MKK", "2.4G", "40M", "HT", "1T", "08", "40", - "FCC", "2.4G", "40M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "40", - "MKK", "2.4G", "40M", "HT", "1T", "09", "40", - "FCC", "2.4G", "40M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "40", - "MKK", "2.4G", "40M", "HT", "1T", "10", "40", - "FCC", "2.4G", "40M", "HT", "1T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "40", - "MKK", "2.4G", "40M", "HT", "1T", "11", "40", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "40", - "MKK", "2.4G", "40M", "HT", "1T", "12", "40", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "40", - "MKK", "2.4G", "40M", "HT", "1T", "13", "40", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "40", - "MKK", "2.4G", "40M", "HT", "2T", "03", "40", - "FCC", "2.4G", "40M", "HT", "2T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "40", - "MKK", "2.4G", "40M", "HT", "2T", "04", "40", - "FCC", "2.4G", "40M", "HT", "2T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "40", - "MKK", "2.4G", "40M", "HT", "2T", "05", "40", - "FCC", "2.4G", "40M", "HT", "2T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "40", - "MKK", "2.4G", "40M", "HT", "2T", "06", "40", - "FCC", "2.4G", "40M", "HT", "2T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "40", - "MKK", "2.4G", "40M", "HT", "2T", "07", "40", - "FCC", "2.4G", "40M", "HT", "2T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "40", - "MKK", "2.4G", "40M", "HT", "2T", "08", "40", - "FCC", "2.4G", "40M", "HT", "2T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "40", - "MKK", "2.4G", "40M", "HT", "2T", "09", "40", - "FCC", "2.4G", "40M", "HT", "2T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "40", - "MKK", "2.4G", "40M", "HT", "2T", "10", "40", - "FCC", "2.4G", "40M", "HT", "2T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "40", - "MKK", "2.4G", "40M", "HT", "2T", "11", "40", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "40", - "MKK", "2.4G", "40M", "HT", "2T", "12", "40", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "40", - "MKK", "2.4G", "40M", "HT", "2T", "13", "40", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "40", - "MKK", "2.4G", "40M", "HT", "3T", "03", "40", - "FCC", "2.4G", "40M", "HT", "3T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "40", - "MKK", "2.4G", "40M", "HT", "3T", "04", "40", - "FCC", "2.4G", "40M", "HT", "3T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "40", - "MKK", "2.4G", "40M", "HT", "3T", "05", "40", - "FCC", "2.4G", "40M", "HT", "3T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "40", - "MKK", "2.4G", "40M", "HT", "3T", "06", "40", - "FCC", "2.4G", "40M", "HT", "3T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "40", - "MKK", "2.4G", "40M", "HT", "3T", "07", "40", - "FCC", "2.4G", "40M", "HT", "3T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "40", - "MKK", "2.4G", "40M", "HT", "3T", "08", "40", - "FCC", "2.4G", "40M", "HT", "3T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "40", - "MKK", "2.4G", "40M", "HT", "3T", "09", "40", - "FCC", "2.4G", "40M", "HT", "3T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "40", - "MKK", "2.4G", "40M", "HT", "3T", "10", "40", - "FCC", "2.4G", "40M", "HT", "3T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "40", - "MKK", "2.4G", "40M", "HT", "3T", "11", "40", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "40", - "MKK", "2.4G", "40M", "HT", "3T", "12", "40", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "40", - "MKK", "2.4G", "40M", "HT", "3T", "13", "40", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "40", - "MKK", "2.4G", "40M", "HT", "4T", "03", "40", - "FCC", "2.4G", "40M", "HT", "4T", "04", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "40", - "MKK", "2.4G", "40M", "HT", "4T", "04", "40", - "FCC", "2.4G", "40M", "HT", "4T", "05", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "40", - "MKK", "2.4G", "40M", "HT", "4T", "05", "40", - "FCC", "2.4G", "40M", "HT", "4T", "06", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "40", - "MKK", "2.4G", "40M", "HT", "4T", "06", "40", - "FCC", "2.4G", "40M", "HT", "4T", "07", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "40", - "MKK", "2.4G", "40M", "HT", "4T", "07", "40", - "FCC", "2.4G", "40M", "HT", "4T", "08", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "40", - "MKK", "2.4G", "40M", "HT", "4T", "08", "40", - "FCC", "2.4G", "40M", "HT", "4T", "09", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "40", - "MKK", "2.4G", "40M", "HT", "4T", "09", "40", - "FCC", "2.4G", "40M", "HT", "4T", "10", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "40", - "MKK", "2.4G", "40M", "HT", "4T", "10", "40", - "FCC", "2.4G", "40M", "HT", "4T", "11", "46", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "40", - "MKK", "2.4G", "40M", "HT", "4T", "11", "40", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "40", - "MKK", "2.4G", "40M", "HT", "4T", "12", "40", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "40", - "MKK", "2.4G", "40M", "HT", "4T", "13", "40", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "40", - "MKK", "5G", "20M", "OFDM", "1T", "36", "40", - "FCC", "5G", "20M", "OFDM", "1T", "40", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "40", - "MKK", "5G", "20M", "OFDM", "1T", "40", "40", - "FCC", "5G", "20M", "OFDM", "1T", "44", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "40", - "MKK", "5G", "20M", "OFDM", "1T", "44", "40", - "FCC", "5G", "20M", "OFDM", "1T", "48", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "40", - "MKK", "5G", "20M", "OFDM", "1T", "48", "40", - "FCC", "5G", "20M", "OFDM", "1T", "52", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "40", - "MKK", "5G", "20M", "OFDM", "1T", "52", "40", - "FCC", "5G", "20M", "OFDM", "1T", "56", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "40", - "MKK", "5G", "20M", "OFDM", "1T", "56", "40", - "FCC", "5G", "20M", "OFDM", "1T", "60", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "40", - "MKK", "5G", "20M", "OFDM", "1T", "60", "40", - "FCC", "5G", "20M", "OFDM", "1T", "64", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", - "MKK", "5G", "20M", "OFDM", "1T", "64", "40", - "FCC", "5G", "20M", "OFDM", "1T", "100", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", - "MKK", "5G", "20M", "OFDM", "1T", "100", "40", - "FCC", "5G", "20M", "OFDM", "1T", "104", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "40", - "MKK", "5G", "20M", "OFDM", "1T", "104", "40", - "FCC", "5G", "20M", "OFDM", "1T", "108", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "40", - "MKK", "5G", "20M", "OFDM", "1T", "108", "40", - "FCC", "5G", "20M", "OFDM", "1T", "112", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "40", - "MKK", "5G", "20M", "OFDM", "1T", "112", "40", - "FCC", "5G", "20M", "OFDM", "1T", "116", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "40", - "MKK", "5G", "20M", "OFDM", "1T", "116", "40", - "FCC", "5G", "20M", "OFDM", "1T", "120", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "40", - "MKK", "5G", "20M", "OFDM", "1T", "120", "40", - "FCC", "5G", "20M", "OFDM", "1T", "124", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "40", - "MKK", "5G", "20M", "OFDM", "1T", "124", "40", - "FCC", "5G", "20M", "OFDM", "1T", "128", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "40", - "MKK", "5G", "20M", "OFDM", "1T", "128", "40", - "FCC", "5G", "20M", "OFDM", "1T", "132", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "40", - "MKK", "5G", "20M", "OFDM", "1T", "132", "40", - "FCC", "5G", "20M", "OFDM", "1T", "136", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "40", - "MKK", "5G", "20M", "OFDM", "1T", "136", "40", - "FCC", "5G", "20M", "OFDM", "1T", "140", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", - "MKK", "5G", "20M", "OFDM", "1T", "140", "40", - "FCC", "5G", "20M", "OFDM", "1T", "149", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "40", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "40", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "40", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "40", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "40", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "46", - "ETSI", "5G", "20M", "HT", "1T", "36", "40", - "MKK", "5G", "20M", "HT", "1T", "36", "40", - "FCC", "5G", "20M", "HT", "1T", "40", "46", - "ETSI", "5G", "20M", "HT", "1T", "40", "40", - "MKK", "5G", "20M", "HT", "1T", "40", "40", - "FCC", "5G", "20M", "HT", "1T", "44", "46", - "ETSI", "5G", "20M", "HT", "1T", "44", "40", - "MKK", "5G", "20M", "HT", "1T", "44", "40", - "FCC", "5G", "20M", "HT", "1T", "48", "46", - "ETSI", "5G", "20M", "HT", "1T", "48", "40", - "MKK", "5G", "20M", "HT", "1T", "48", "40", - "FCC", "5G", "20M", "HT", "1T", "52", "46", - "ETSI", "5G", "20M", "HT", "1T", "52", "40", - "MKK", "5G", "20M", "HT", "1T", "52", "40", - "FCC", "5G", "20M", "HT", "1T", "56", "46", - "ETSI", "5G", "20M", "HT", "1T", "56", "40", - "MKK", "5G", "20M", "HT", "1T", "56", "40", - "FCC", "5G", "20M", "HT", "1T", "60", "46", - "ETSI", "5G", "20M", "HT", "1T", "60", "40", - "MKK", "5G", "20M", "HT", "1T", "60", "40", - "FCC", "5G", "20M", "HT", "1T", "64", "46", - "ETSI", "5G", "20M", "HT", "1T", "64", "40", - "MKK", "5G", "20M", "HT", "1T", "64", "40", - "FCC", "5G", "20M", "HT", "1T", "100", "46", - "ETSI", "5G", "20M", "HT", "1T", "100", "40", - "MKK", "5G", "20M", "HT", "1T", "100", "40", - "FCC", "5G", "20M", "HT", "1T", "104", "46", - "ETSI", "5G", "20M", "HT", "1T", "104", "40", - "MKK", "5G", "20M", "HT", "1T", "104", "40", - "FCC", "5G", "20M", "HT", "1T", "108", "46", - "ETSI", "5G", "20M", "HT", "1T", "108", "40", - "MKK", "5G", "20M", "HT", "1T", "108", "40", - "FCC", "5G", "20M", "HT", "1T", "112", "46", - "ETSI", "5G", "20M", "HT", "1T", "112", "40", - "MKK", "5G", "20M", "HT", "1T", "112", "40", - "FCC", "5G", "20M", "HT", "1T", "116", "46", - "ETSI", "5G", "20M", "HT", "1T", "116", "40", - "MKK", "5G", "20M", "HT", "1T", "116", "40", - "FCC", "5G", "20M", "HT", "1T", "120", "46", - "ETSI", "5G", "20M", "HT", "1T", "120", "40", - "MKK", "5G", "20M", "HT", "1T", "120", "40", - "FCC", "5G", "20M", "HT", "1T", "124", "46", - "ETSI", "5G", "20M", "HT", "1T", "124", "40", - "MKK", "5G", "20M", "HT", "1T", "124", "40", - "FCC", "5G", "20M", "HT", "1T", "128", "46", - "ETSI", "5G", "20M", "HT", "1T", "128", "40", - "MKK", "5G", "20M", "HT", "1T", "128", "40", - "FCC", "5G", "20M", "HT", "1T", "132", "46", - "ETSI", "5G", "20M", "HT", "1T", "132", "40", - "MKK", "5G", "20M", "HT", "1T", "132", "40", - "FCC", "5G", "20M", "HT", "1T", "136", "46", - "ETSI", "5G", "20M", "HT", "1T", "136", "40", - "MKK", "5G", "20M", "HT", "1T", "136", "40", - "FCC", "5G", "20M", "HT", "1T", "140", "46", - "ETSI", "5G", "20M", "HT", "1T", "140", "40", - "MKK", "5G", "20M", "HT", "1T", "140", "40", - "FCC", "5G", "20M", "HT", "1T", "149", "46", - "ETSI", "5G", "20M", "HT", "1T", "149", "40", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "46", - "ETSI", "5G", "20M", "HT", "1T", "153", "40", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "46", - "ETSI", "5G", "20M", "HT", "1T", "157", "40", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "46", - "ETSI", "5G", "20M", "HT", "1T", "161", "40", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "46", - "ETSI", "5G", "20M", "HT", "1T", "165", "40", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "46", - "ETSI", "5G", "20M", "HT", "2T", "36", "40", - "MKK", "5G", "20M", "HT", "2T", "36", "40", - "FCC", "5G", "20M", "HT", "2T", "40", "46", - "ETSI", "5G", "20M", "HT", "2T", "40", "40", - "MKK", "5G", "20M", "HT", "2T", "40", "40", - "FCC", "5G", "20M", "HT", "2T", "44", "46", - "ETSI", "5G", "20M", "HT", "2T", "44", "40", - "MKK", "5G", "20M", "HT", "2T", "44", "40", - "FCC", "5G", "20M", "HT", "2T", "48", "46", - "ETSI", "5G", "20M", "HT", "2T", "48", "40", - "MKK", "5G", "20M", "HT", "2T", "48", "40", - "FCC", "5G", "20M", "HT", "2T", "52", "46", - "ETSI", "5G", "20M", "HT", "2T", "52", "40", - "MKK", "5G", "20M", "HT", "2T", "52", "40", - "FCC", "5G", "20M", "HT", "2T", "56", "46", - "ETSI", "5G", "20M", "HT", "2T", "56", "40", - "MKK", "5G", "20M", "HT", "2T", "56", "40", - "FCC", "5G", "20M", "HT", "2T", "60", "46", - "ETSI", "5G", "20M", "HT", "2T", "60", "40", - "MKK", "5G", "20M", "HT", "2T", "60", "40", - "FCC", "5G", "20M", "HT", "2T", "64", "46", - "ETSI", "5G", "20M", "HT", "2T", "64", "40", - "MKK", "5G", "20M", "HT", "2T", "64", "40", - "FCC", "5G", "20M", "HT", "2T", "100", "46", - "ETSI", "5G", "20M", "HT", "2T", "100", "40", - "MKK", "5G", "20M", "HT", "2T", "100", "40", - "FCC", "5G", "20M", "HT", "2T", "104", "46", - "ETSI", "5G", "20M", "HT", "2T", "104", "40", - "MKK", "5G", "20M", "HT", "2T", "104", "40", - "FCC", "5G", "20M", "HT", "2T", "108", "46", - "ETSI", "5G", "20M", "HT", "2T", "108", "40", - "MKK", "5G", "20M", "HT", "2T", "108", "40", - "FCC", "5G", "20M", "HT", "2T", "112", "46", - "ETSI", "5G", "20M", "HT", "2T", "112", "40", - "MKK", "5G", "20M", "HT", "2T", "112", "40", - "FCC", "5G", "20M", "HT", "2T", "116", "46", - "ETSI", "5G", "20M", "HT", "2T", "116", "40", - "MKK", "5G", "20M", "HT", "2T", "116", "40", - "FCC", "5G", "20M", "HT", "2T", "120", "46", - "ETSI", "5G", "20M", "HT", "2T", "120", "40", - "MKK", "5G", "20M", "HT", "2T", "120", "40", - "FCC", "5G", "20M", "HT", "2T", "124", "46", - "ETSI", "5G", "20M", "HT", "2T", "124", "40", - "MKK", "5G", "20M", "HT", "2T", "124", "40", - "FCC", "5G", "20M", "HT", "2T", "128", "46", - "ETSI", "5G", "20M", "HT", "2T", "128", "40", - "MKK", "5G", "20M", "HT", "2T", "128", "40", - "FCC", "5G", "20M", "HT", "2T", "132", "46", - "ETSI", "5G", "20M", "HT", "2T", "132", "40", - "MKK", "5G", "20M", "HT", "2T", "132", "40", - "FCC", "5G", "20M", "HT", "2T", "136", "46", - "ETSI", "5G", "20M", "HT", "2T", "136", "40", - "MKK", "5G", "20M", "HT", "2T", "136", "40", - "FCC", "5G", "20M", "HT", "2T", "140", "46", - "ETSI", "5G", "20M", "HT", "2T", "140", "40", - "MKK", "5G", "20M", "HT", "2T", "140", "40", - "FCC", "5G", "20M", "HT", "2T", "149", "46", - "ETSI", "5G", "20M", "HT", "2T", "149", "40", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "46", - "ETSI", "5G", "20M", "HT", "2T", "153", "40", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "46", - "ETSI", "5G", "20M", "HT", "2T", "157", "40", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "46", - "ETSI", "5G", "20M", "HT", "2T", "161", "40", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "46", - "ETSI", "5G", "20M", "HT", "2T", "165", "40", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "46", - "ETSI", "5G", "20M", "HT", "3T", "36", "40", - "MKK", "5G", "20M", "HT", "3T", "36", "40", - "FCC", "5G", "20M", "HT", "3T", "40", "46", - "ETSI", "5G", "20M", "HT", "3T", "40", "40", - "MKK", "5G", "20M", "HT", "3T", "40", "40", - "FCC", "5G", "20M", "HT", "3T", "44", "46", - "ETSI", "5G", "20M", "HT", "3T", "44", "40", - "MKK", "5G", "20M", "HT", "3T", "44", "40", - "FCC", "5G", "20M", "HT", "3T", "48", "46", - "ETSI", "5G", "20M", "HT", "3T", "48", "40", - "MKK", "5G", "20M", "HT", "3T", "48", "40", - "FCC", "5G", "20M", "HT", "3T", "52", "46", - "ETSI", "5G", "20M", "HT", "3T", "52", "40", - "MKK", "5G", "20M", "HT", "3T", "52", "40", - "FCC", "5G", "20M", "HT", "3T", "56", "46", - "ETSI", "5G", "20M", "HT", "3T", "56", "40", - "MKK", "5G", "20M", "HT", "3T", "56", "40", - "FCC", "5G", "20M", "HT", "3T", "60", "46", - "ETSI", "5G", "20M", "HT", "3T", "60", "40", - "MKK", "5G", "20M", "HT", "3T", "60", "40", - "FCC", "5G", "20M", "HT", "3T", "64", "46", - "ETSI", "5G", "20M", "HT", "3T", "64", "40", - "MKK", "5G", "20M", "HT", "3T", "64", "40", - "FCC", "5G", "20M", "HT", "3T", "100", "46", - "ETSI", "5G", "20M", "HT", "3T", "100", "40", - "MKK", "5G", "20M", "HT", "3T", "100", "40", - "FCC", "5G", "20M", "HT", "3T", "104", "46", - "ETSI", "5G", "20M", "HT", "3T", "104", "40", - "MKK", "5G", "20M", "HT", "3T", "104", "40", - "FCC", "5G", "20M", "HT", "3T", "108", "46", - "ETSI", "5G", "20M", "HT", "3T", "108", "40", - "MKK", "5G", "20M", "HT", "3T", "108", "40", - "FCC", "5G", "20M", "HT", "3T", "112", "46", - "ETSI", "5G", "20M", "HT", "3T", "112", "40", - "MKK", "5G", "20M", "HT", "3T", "112", "40", - "FCC", "5G", "20M", "HT", "3T", "116", "46", - "ETSI", "5G", "20M", "HT", "3T", "116", "40", - "MKK", "5G", "20M", "HT", "3T", "116", "40", - "FCC", "5G", "20M", "HT", "3T", "120", "46", - "ETSI", "5G", "20M", "HT", "3T", "120", "40", - "MKK", "5G", "20M", "HT", "3T", "120", "40", - "FCC", "5G", "20M", "HT", "3T", "124", "46", - "ETSI", "5G", "20M", "HT", "3T", "124", "40", - "MKK", "5G", "20M", "HT", "3T", "124", "40", - "FCC", "5G", "20M", "HT", "3T", "128", "46", - "ETSI", "5G", "20M", "HT", "3T", "128", "40", - "MKK", "5G", "20M", "HT", "3T", "128", "40", - "FCC", "5G", "20M", "HT", "3T", "132", "46", - "ETSI", "5G", "20M", "HT", "3T", "132", "40", - "MKK", "5G", "20M", "HT", "3T", "132", "40", - "FCC", "5G", "20M", "HT", "3T", "136", "46", - "ETSI", "5G", "20M", "HT", "3T", "136", "40", - "MKK", "5G", "20M", "HT", "3T", "136", "40", - "FCC", "5G", "20M", "HT", "3T", "140", "46", - "ETSI", "5G", "20M", "HT", "3T", "140", "40", - "MKK", "5G", "20M", "HT", "3T", "140", "40", - "FCC", "5G", "20M", "HT", "3T", "149", "46", - "ETSI", "5G", "20M", "HT", "3T", "149", "40", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "46", - "ETSI", "5G", "20M", "HT", "3T", "153", "40", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "46", - "ETSI", "5G", "20M", "HT", "3T", "157", "40", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "46", - "ETSI", "5G", "20M", "HT", "3T", "161", "40", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "46", - "ETSI", "5G", "20M", "HT", "3T", "165", "40", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "46", - "ETSI", "5G", "20M", "HT", "4T", "36", "40", - "MKK", "5G", "20M", "HT", "4T", "36", "40", - "FCC", "5G", "20M", "HT", "4T", "40", "46", - "ETSI", "5G", "20M", "HT", "4T", "40", "40", - "MKK", "5G", "20M", "HT", "4T", "40", "40", - "FCC", "5G", "20M", "HT", "4T", "44", "46", - "ETSI", "5G", "20M", "HT", "4T", "44", "40", - "MKK", "5G", "20M", "HT", "4T", "44", "40", - "FCC", "5G", "20M", "HT", "4T", "48", "46", - "ETSI", "5G", "20M", "HT", "4T", "48", "40", - "MKK", "5G", "20M", "HT", "4T", "48", "40", - "FCC", "5G", "20M", "HT", "4T", "52", "46", - "ETSI", "5G", "20M", "HT", "4T", "52", "40", - "MKK", "5G", "20M", "HT", "4T", "52", "40", - "FCC", "5G", "20M", "HT", "4T", "56", "46", - "ETSI", "5G", "20M", "HT", "4T", "56", "40", - "MKK", "5G", "20M", "HT", "4T", "56", "40", - "FCC", "5G", "20M", "HT", "4T", "60", "46", - "ETSI", "5G", "20M", "HT", "4T", "60", "40", - "MKK", "5G", "20M", "HT", "4T", "60", "40", - "FCC", "5G", "20M", "HT", "4T", "64", "46", - "ETSI", "5G", "20M", "HT", "4T", "64", "40", - "MKK", "5G", "20M", "HT", "4T", "64", "40", - "FCC", "5G", "20M", "HT", "4T", "100", "46", - "ETSI", "5G", "20M", "HT", "4T", "100", "40", - "MKK", "5G", "20M", "HT", "4T", "100", "40", - "FCC", "5G", "20M", "HT", "4T", "104", "46", - "ETSI", "5G", "20M", "HT", "4T", "104", "40", - "MKK", "5G", "20M", "HT", "4T", "104", "40", - "FCC", "5G", "20M", "HT", "4T", "108", "46", - "ETSI", "5G", "20M", "HT", "4T", "108", "40", - "MKK", "5G", "20M", "HT", "4T", "108", "40", - "FCC", "5G", "20M", "HT", "4T", "112", "46", - "ETSI", "5G", "20M", "HT", "4T", "112", "40", - "MKK", "5G", "20M", "HT", "4T", "112", "40", - "FCC", "5G", "20M", "HT", "4T", "116", "46", - "ETSI", "5G", "20M", "HT", "4T", "116", "40", - "MKK", "5G", "20M", "HT", "4T", "116", "40", - "FCC", "5G", "20M", "HT", "4T", "120", "46", - "ETSI", "5G", "20M", "HT", "4T", "120", "40", - "MKK", "5G", "20M", "HT", "4T", "120", "40", - "FCC", "5G", "20M", "HT", "4T", "124", "46", - "ETSI", "5G", "20M", "HT", "4T", "124", "40", - "MKK", "5G", "20M", "HT", "4T", "124", "40", - "FCC", "5G", "20M", "HT", "4T", "128", "46", - "ETSI", "5G", "20M", "HT", "4T", "128", "40", - "MKK", "5G", "20M", "HT", "4T", "128", "40", - "FCC", "5G", "20M", "HT", "4T", "132", "46", - "ETSI", "5G", "20M", "HT", "4T", "132", "40", - "MKK", "5G", "20M", "HT", "4T", "132", "40", - "FCC", "5G", "20M", "HT", "4T", "136", "46", - "ETSI", "5G", "20M", "HT", "4T", "136", "40", - "MKK", "5G", "20M", "HT", "4T", "136", "40", - "FCC", "5G", "20M", "HT", "4T", "140", "46", - "ETSI", "5G", "20M", "HT", "4T", "140", "40", - "MKK", "5G", "20M", "HT", "4T", "140", "40", - "FCC", "5G", "20M", "HT", "4T", "149", "46", - "ETSI", "5G", "20M", "HT", "4T", "149", "40", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "46", - "ETSI", "5G", "20M", "HT", "4T", "153", "40", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "46", - "ETSI", "5G", "20M", "HT", "4T", "157", "40", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "46", - "ETSI", "5G", "20M", "HT", "4T", "161", "40", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "46", - "ETSI", "5G", "20M", "HT", "4T", "165", "40", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "46", - "ETSI", "5G", "40M", "HT", "1T", "38", "40", - "MKK", "5G", "40M", "HT", "1T", "38", "40", - "FCC", "5G", "40M", "HT", "1T", "46", "46", - "ETSI", "5G", "40M", "HT", "1T", "46", "40", - "MKK", "5G", "40M", "HT", "1T", "46", "40", - "FCC", "5G", "40M", "HT", "1T", "54", "46", - "ETSI", "5G", "40M", "HT", "1T", "54", "40", - "MKK", "5G", "40M", "HT", "1T", "54", "40", - "FCC", "5G", "40M", "HT", "1T", "62", "46", - "ETSI", "5G", "40M", "HT", "1T", "62", "40", - "MKK", "5G", "40M", "HT", "1T", "62", "40", - "FCC", "5G", "40M", "HT", "1T", "102", "46", - "ETSI", "5G", "40M", "HT", "1T", "102", "40", - "MKK", "5G", "40M", "HT", "1T", "102", "40", - "FCC", "5G", "40M", "HT", "1T", "110", "46", - "ETSI", "5G", "40M", "HT", "1T", "110", "40", - "MKK", "5G", "40M", "HT", "1T", "110", "40", - "FCC", "5G", "40M", "HT", "1T", "118", "46", - "ETSI", "5G", "40M", "HT", "1T", "118", "40", - "MKK", "5G", "40M", "HT", "1T", "118", "40", - "FCC", "5G", "40M", "HT", "1T", "126", "46", - "ETSI", "5G", "40M", "HT", "1T", "126", "40", - "MKK", "5G", "40M", "HT", "1T", "126", "40", - "FCC", "5G", "40M", "HT", "1T", "134", "46", - "ETSI", "5G", "40M", "HT", "1T", "134", "40", - "MKK", "5G", "40M", "HT", "1T", "134", "40", - "FCC", "5G", "40M", "HT", "1T", "151", "46", - "ETSI", "5G", "40M", "HT", "1T", "151", "40", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "46", - "ETSI", "5G", "40M", "HT", "1T", "159", "40", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "46", - "ETSI", "5G", "40M", "HT", "2T", "38", "40", - "MKK", "5G", "40M", "HT", "2T", "38", "40", - "FCC", "5G", "40M", "HT", "2T", "46", "46", - "ETSI", "5G", "40M", "HT", "2T", "46", "40", - "MKK", "5G", "40M", "HT", "2T", "46", "40", - "FCC", "5G", "40M", "HT", "2T", "54", "46", - "ETSI", "5G", "40M", "HT", "2T", "54", "40", - "MKK", "5G", "40M", "HT", "2T", "54", "40", - "FCC", "5G", "40M", "HT", "2T", "62", "46", - "ETSI", "5G", "40M", "HT", "2T", "62", "40", - "MKK", "5G", "40M", "HT", "2T", "62", "40", - "FCC", "5G", "40M", "HT", "2T", "102", "46", - "ETSI", "5G", "40M", "HT", "2T", "102", "40", - "MKK", "5G", "40M", "HT", "2T", "102", "40", - "FCC", "5G", "40M", "HT", "2T", "110", "46", - "ETSI", "5G", "40M", "HT", "2T", "110", "40", - "MKK", "5G", "40M", "HT", "2T", "110", "40", - "FCC", "5G", "40M", "HT", "2T", "118", "46", - "ETSI", "5G", "40M", "HT", "2T", "118", "40", - "MKK", "5G", "40M", "HT", "2T", "118", "40", - "FCC", "5G", "40M", "HT", "2T", "126", "46", - "ETSI", "5G", "40M", "HT", "2T", "126", "40", - "MKK", "5G", "40M", "HT", "2T", "126", "40", - "FCC", "5G", "40M", "HT", "2T", "134", "46", - "ETSI", "5G", "40M", "HT", "2T", "134", "40", - "MKK", "5G", "40M", "HT", "2T", "134", "40", - "FCC", "5G", "40M", "HT", "2T", "151", "46", - "ETSI", "5G", "40M", "HT", "2T", "151", "40", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "46", - "ETSI", "5G", "40M", "HT", "2T", "159", "40", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "46", - "ETSI", "5G", "40M", "HT", "3T", "38", "40", - "MKK", "5G", "40M", "HT", "3T", "38", "40", - "FCC", "5G", "40M", "HT", "3T", "46", "46", - "ETSI", "5G", "40M", "HT", "3T", "46", "40", - "MKK", "5G", "40M", "HT", "3T", "46", "40", - "FCC", "5G", "40M", "HT", "3T", "54", "46", - "ETSI", "5G", "40M", "HT", "3T", "54", "40", - "MKK", "5G", "40M", "HT", "3T", "54", "40", - "FCC", "5G", "40M", "HT", "3T", "62", "46", - "ETSI", "5G", "40M", "HT", "3T", "62", "40", - "MKK", "5G", "40M", "HT", "3T", "62", "40", - "FCC", "5G", "40M", "HT", "3T", "102", "46", - "ETSI", "5G", "40M", "HT", "3T", "102", "40", - "MKK", "5G", "40M", "HT", "3T", "102", "40", - "FCC", "5G", "40M", "HT", "3T", "110", "46", - "ETSI", "5G", "40M", "HT", "3T", "110", "40", - "MKK", "5G", "40M", "HT", "3T", "110", "40", - "FCC", "5G", "40M", "HT", "3T", "118", "46", - "ETSI", "5G", "40M", "HT", "3T", "118", "40", - "MKK", "5G", "40M", "HT", "3T", "118", "40", - "FCC", "5G", "40M", "HT", "3T", "126", "46", - "ETSI", "5G", "40M", "HT", "3T", "126", "40", - "MKK", "5G", "40M", "HT", "3T", "126", "40", - "FCC", "5G", "40M", "HT", "3T", "134", "46", - "ETSI", "5G", "40M", "HT", "3T", "134", "40", - "MKK", "5G", "40M", "HT", "3T", "134", "40", - "FCC", "5G", "40M", "HT", "3T", "151", "46", - "ETSI", "5G", "40M", "HT", "3T", "151", "40", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "46", - "ETSI", "5G", "40M", "HT", "3T", "159", "40", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "46", - "ETSI", "5G", "40M", "HT", "4T", "38", "40", - "MKK", "5G", "40M", "HT", "4T", "38", "40", - "FCC", "5G", "40M", "HT", "4T", "46", "46", - "ETSI", "5G", "40M", "HT", "4T", "46", "40", - "MKK", "5G", "40M", "HT", "4T", "46", "40", - "FCC", "5G", "40M", "HT", "4T", "54", "46", - "ETSI", "5G", "40M", "HT", "4T", "54", "40", - "MKK", "5G", "40M", "HT", "4T", "54", "40", - "FCC", "5G", "40M", "HT", "4T", "62", "46", - "ETSI", "5G", "40M", "HT", "4T", "62", "40", - "MKK", "5G", "40M", "HT", "4T", "62", "40", - "FCC", "5G", "40M", "HT", "4T", "102", "46", - "ETSI", "5G", "40M", "HT", "4T", "102", "40", - "MKK", "5G", "40M", "HT", "4T", "102", "40", - "FCC", "5G", "40M", "HT", "4T", "110", "46", - "ETSI", "5G", "40M", "HT", "4T", "110", "40", - "MKK", "5G", "40M", "HT", "4T", "110", "40", - "FCC", "5G", "40M", "HT", "4T", "118", "46", - "ETSI", "5G", "40M", "HT", "4T", "118", "40", - "MKK", "5G", "40M", "HT", "4T", "118", "40", - "FCC", "5G", "40M", "HT", "4T", "126", "46", - "ETSI", "5G", "40M", "HT", "4T", "126", "40", - "MKK", "5G", "40M", "HT", "4T", "126", "40", - "FCC", "5G", "40M", "HT", "4T", "134", "46", - "ETSI", "5G", "40M", "HT", "4T", "134", "40", - "MKK", "5G", "40M", "HT", "4T", "134", "40", - "FCC", "5G", "40M", "HT", "4T", "151", "46", - "ETSI", "5G", "40M", "HT", "4T", "151", "40", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "46", - "ETSI", "5G", "40M", "HT", "4T", "159", "40", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "46", - "ETSI", "5G", "80M", "VHT", "1T", "42", "40", - "MKK", "5G", "80M", "VHT", "1T", "42", "40", - "FCC", "5G", "80M", "VHT", "1T", "58", "46", - "ETSI", "5G", "80M", "VHT", "1T", "58", "40", - "MKK", "5G", "80M", "VHT", "1T", "58", "40", - "FCC", "5G", "80M", "VHT", "1T", "106", "46", - "ETSI", "5G", "80M", "VHT", "1T", "106", "40", - "MKK", "5G", "80M", "VHT", "1T", "106", "40", - "FCC", "5G", "80M", "VHT", "1T", "122", "46", - "ETSI", "5G", "80M", "VHT", "1T", "122", "40", - "MKK", "5G", "80M", "VHT", "1T", "122", "40", - "FCC", "5G", "80M", "VHT", "1T", "155", "46", - "ETSI", "5G", "80M", "VHT", "1T", "155", "40", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "46", - "ETSI", "5G", "80M", "VHT", "2T", "42", "40", - "MKK", "5G", "80M", "VHT", "2T", "42", "40", - "FCC", "5G", "80M", "VHT", "2T", "58", "46", - "ETSI", "5G", "80M", "VHT", "2T", "58", "40", - "MKK", "5G", "80M", "VHT", "2T", "58", "40", - "FCC", "5G", "80M", "VHT", "2T", "106", "46", - "ETSI", "5G", "80M", "VHT", "2T", "106", "40", - "MKK", "5G", "80M", "VHT", "2T", "106", "40", - "FCC", "5G", "80M", "VHT", "2T", "122", "46", - "ETSI", "5G", "80M", "VHT", "2T", "122", "40", - "MKK", "5G", "80M", "VHT", "2T", "122", "40", - "FCC", "5G", "80M", "VHT", "2T", "155", "46", - "ETSI", "5G", "80M", "VHT", "2T", "155", "40", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "46", - "ETSI", "5G", "80M", "VHT", "3T", "42", "40", - "MKK", "5G", "80M", "VHT", "3T", "42", "40", - "FCC", "5G", "80M", "VHT", "3T", "58", "46", - "ETSI", "5G", "80M", "VHT", "3T", "58", "40", - "MKK", "5G", "80M", "VHT", "3T", "58", "40", - "FCC", "5G", "80M", "VHT", "3T", "106", "46", - "ETSI", "5G", "80M", "VHT", "3T", "106", "40", - "MKK", "5G", "80M", "VHT", "3T", "106", "40", - "FCC", "5G", "80M", "VHT", "3T", "122", "46", - "ETSI", "5G", "80M", "VHT", "3T", "122", "40", - "MKK", "5G", "80M", "VHT", "3T", "122", "40", - "FCC", "5G", "80M", "VHT", "3T", "155", "46", - "ETSI", "5G", "80M", "VHT", "3T", "155", "40", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "46", - "ETSI", "5G", "80M", "VHT", "4T", "42", "40", - "MKK", "5G", "80M", "VHT", "4T", "42", "40", - "FCC", "5G", "80M", "VHT", "4T", "58", "46", - "ETSI", "5G", "80M", "VHT", "4T", "58", "40", - "MKK", "5G", "80M", "VHT", "4T", "58", "40", - "FCC", "5G", "80M", "VHT", "4T", "106", "46", - "ETSI", "5G", "80M", "VHT", "4T", "106", "40", - "MKK", "5G", "80M", "VHT", "4T", "106", "40", - "FCC", "5G", "80M", "VHT", "4T", "122", "46", - "ETSI", "5G", "80M", "VHT", "4T", "122", "40", - "MKK", "5G", "80M", "VHT", "4T", "122", "40", - "FCC", "5G", "80M", "VHT", "4T", "155", "46", - "ETSI", "5G", "80M", "VHT", "4T", "155", "40", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type5)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type5; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type5)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type5; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type6.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type6[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "18", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "8", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "6", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "24", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "24", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "22", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "22", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "20", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "20", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "4", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "10", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "22", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "20", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "20", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "14", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "8", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "26", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "26", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "26", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "24", - "ETSI", "5G", "20M", "HT", "2T", "36", "28", - "MKK", "5G", "20M", "HT", "2T", "36", "28", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "28", - "MKK", "5G", "20M", "HT", "2T", "40", "28", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "28", - "MKK", "5G", "20M", "HT", "2T", "44", "28", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "28", - "MKK", "5G", "20M", "HT", "2T", "48", "28", - "FCC", "5G", "20M", "HT", "2T", "52", "28", - "ETSI", "5G", "20M", "HT", "2T", "52", "28", - "MKK", "5G", "20M", "HT", "2T", "52", "28", - "FCC", "5G", "20M", "HT", "2T", "56", "28", - "ETSI", "5G", "20M", "HT", "2T", "56", "28", - "MKK", "5G", "20M", "HT", "2T", "56", "28", - "FCC", "5G", "20M", "HT", "2T", "60", "28", - "ETSI", "5G", "20M", "HT", "2T", "60", "28", - "MKK", "5G", "20M", "HT", "2T", "60", "28", - "FCC", "5G", "20M", "HT", "2T", "64", "24", - "ETSI", "5G", "20M", "HT", "2T", "64", "28", - "MKK", "5G", "20M", "HT", "2T", "64", "28", - "FCC", "5G", "20M", "HT", "2T", "100", "24", - "ETSI", "5G", "20M", "HT", "2T", "100", "28", - "MKK", "5G", "20M", "HT", "2T", "100", "28", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "28", - "MKK", "5G", "20M", "HT", "2T", "104", "28", - "FCC", "5G", "20M", "HT", "2T", "108", "28", - "ETSI", "5G", "20M", "HT", "2T", "108", "28", - "MKK", "5G", "20M", "HT", "2T", "108", "28", - "FCC", "5G", "20M", "HT", "2T", "112", "28", - "ETSI", "5G", "20M", "HT", "2T", "112", "28", - "MKK", "5G", "20M", "HT", "2T", "112", "28", - "FCC", "5G", "20M", "HT", "2T", "116", "28", - "ETSI", "5G", "20M", "HT", "2T", "116", "28", - "MKK", "5G", "20M", "HT", "2T", "116", "28", - "FCC", "5G", "20M", "HT", "2T", "120", "28", - "ETSI", "5G", "20M", "HT", "2T", "120", "28", - "MKK", "5G", "20M", "HT", "2T", "120", "28", - "FCC", "5G", "20M", "HT", "2T", "124", "28", - "ETSI", "5G", "20M", "HT", "2T", "124", "28", - "MKK", "5G", "20M", "HT", "2T", "124", "28", - "FCC", "5G", "20M", "HT", "2T", "128", "28", - "ETSI", "5G", "20M", "HT", "2T", "128", "28", - "MKK", "5G", "20M", "HT", "2T", "128", "28", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "28", - "MKK", "5G", "20M", "HT", "2T", "132", "28", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "28", - "MKK", "5G", "20M", "HT", "2T", "136", "28", - "FCC", "5G", "20M", "HT", "2T", "140", "24", - "ETSI", "5G", "20M", "HT", "2T", "140", "28", - "MKK", "5G", "20M", "HT", "2T", "140", "28", - "FCC", "5G", "20M", "HT", "2T", "149", "24", - "ETSI", "5G", "20M", "HT", "2T", "149", "28", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "28", - "ETSI", "5G", "20M", "HT", "2T", "153", "28", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "28", - "ETSI", "5G", "20M", "HT", "2T", "157", "28", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "28", - "ETSI", "5G", "20M", "HT", "2T", "161", "28", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "28", - "ETSI", "5G", "20M", "HT", "2T", "165", "28", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "22", - "ETSI", "5G", "20M", "HT", "3T", "36", "26", - "MKK", "5G", "20M", "HT", "3T", "36", "26", - "FCC", "5G", "20M", "HT", "3T", "40", "26", - "ETSI", "5G", "20M", "HT", "3T", "40", "26", - "MKK", "5G", "20M", "HT", "3T", "40", "26", - "FCC", "5G", "20M", "HT", "3T", "44", "26", - "ETSI", "5G", "20M", "HT", "3T", "44", "26", - "MKK", "5G", "20M", "HT", "3T", "44", "26", - "FCC", "5G", "20M", "HT", "3T", "48", "26", - "ETSI", "5G", "20M", "HT", "3T", "48", "26", - "MKK", "5G", "20M", "HT", "3T", "48", "26", - "FCC", "5G", "20M", "HT", "3T", "52", "26", - "ETSI", "5G", "20M", "HT", "3T", "52", "26", - "MKK", "5G", "20M", "HT", "3T", "52", "26", - "FCC", "5G", "20M", "HT", "3T", "56", "26", - "ETSI", "5G", "20M", "HT", "3T", "56", "26", - "MKK", "5G", "20M", "HT", "3T", "56", "26", - "FCC", "5G", "20M", "HT", "3T", "60", "26", - "ETSI", "5G", "20M", "HT", "3T", "60", "26", - "MKK", "5G", "20M", "HT", "3T", "60", "26", - "FCC", "5G", "20M", "HT", "3T", "64", "22", - "ETSI", "5G", "20M", "HT", "3T", "64", "26", - "MKK", "5G", "20M", "HT", "3T", "64", "26", - "FCC", "5G", "20M", "HT", "3T", "100", "22", - "ETSI", "5G", "20M", "HT", "3T", "100", "26", - "MKK", "5G", "20M", "HT", "3T", "100", "26", - "FCC", "5G", "20M", "HT", "3T", "104", "26", - "ETSI", "5G", "20M", "HT", "3T", "104", "26", - "MKK", "5G", "20M", "HT", "3T", "104", "26", - "FCC", "5G", "20M", "HT", "3T", "108", "26", - "ETSI", "5G", "20M", "HT", "3T", "108", "26", - "MKK", "5G", "20M", "HT", "3T", "108", "26", - "FCC", "5G", "20M", "HT", "3T", "112", "26", - "ETSI", "5G", "20M", "HT", "3T", "112", "26", - "MKK", "5G", "20M", "HT", "3T", "112", "26", - "FCC", "5G", "20M", "HT", "3T", "116", "26", - "ETSI", "5G", "20M", "HT", "3T", "116", "26", - "MKK", "5G", "20M", "HT", "3T", "116", "26", - "FCC", "5G", "20M", "HT", "3T", "120", "26", - "ETSI", "5G", "20M", "HT", "3T", "120", "26", - "MKK", "5G", "20M", "HT", "3T", "120", "26", - "FCC", "5G", "20M", "HT", "3T", "124", "26", - "ETSI", "5G", "20M", "HT", "3T", "124", "26", - "MKK", "5G", "20M", "HT", "3T", "124", "26", - "FCC", "5G", "20M", "HT", "3T", "128", "26", - "ETSI", "5G", "20M", "HT", "3T", "128", "26", - "MKK", "5G", "20M", "HT", "3T", "128", "26", - "FCC", "5G", "20M", "HT", "3T", "132", "26", - "ETSI", "5G", "20M", "HT", "3T", "132", "26", - "MKK", "5G", "20M", "HT", "3T", "132", "26", - "FCC", "5G", "20M", "HT", "3T", "136", "26", - "ETSI", "5G", "20M", "HT", "3T", "136", "26", - "MKK", "5G", "20M", "HT", "3T", "136", "26", - "FCC", "5G", "20M", "HT", "3T", "140", "22", - "ETSI", "5G", "20M", "HT", "3T", "140", "26", - "MKK", "5G", "20M", "HT", "3T", "140", "26", - "FCC", "5G", "20M", "HT", "3T", "149", "22", - "ETSI", "5G", "20M", "HT", "3T", "149", "26", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "26", - "ETSI", "5G", "20M", "HT", "3T", "153", "26", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "26", - "ETSI", "5G", "20M", "HT", "3T", "157", "26", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "26", - "ETSI", "5G", "20M", "HT", "3T", "161", "26", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "26", - "ETSI", "5G", "20M", "HT", "3T", "165", "26", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "20", - "ETSI", "5G", "20M", "HT", "4T", "36", "24", - "MKK", "5G", "20M", "HT", "4T", "36", "24", - "FCC", "5G", "20M", "HT", "4T", "40", "24", - "ETSI", "5G", "20M", "HT", "4T", "40", "24", - "MKK", "5G", "20M", "HT", "4T", "40", "24", - "FCC", "5G", "20M", "HT", "4T", "44", "24", - "ETSI", "5G", "20M", "HT", "4T", "44", "24", - "MKK", "5G", "20M", "HT", "4T", "44", "24", - "FCC", "5G", "20M", "HT", "4T", "48", "24", - "ETSI", "5G", "20M", "HT", "4T", "48", "24", - "MKK", "5G", "20M", "HT", "4T", "48", "24", - "FCC", "5G", "20M", "HT", "4T", "52", "24", - "ETSI", "5G", "20M", "HT", "4T", "52", "24", - "MKK", "5G", "20M", "HT", "4T", "52", "24", - "FCC", "5G", "20M", "HT", "4T", "56", "24", - "ETSI", "5G", "20M", "HT", "4T", "56", "24", - "MKK", "5G", "20M", "HT", "4T", "56", "24", - "FCC", "5G", "20M", "HT", "4T", "60", "24", - "ETSI", "5G", "20M", "HT", "4T", "60", "24", - "MKK", "5G", "20M", "HT", "4T", "60", "24", - "FCC", "5G", "20M", "HT", "4T", "64", "20", - "ETSI", "5G", "20M", "HT", "4T", "64", "24", - "MKK", "5G", "20M", "HT", "4T", "64", "24", - "FCC", "5G", "20M", "HT", "4T", "100", "20", - "ETSI", "5G", "20M", "HT", "4T", "100", "24", - "MKK", "5G", "20M", "HT", "4T", "100", "24", - "FCC", "5G", "20M", "HT", "4T", "104", "24", - "ETSI", "5G", "20M", "HT", "4T", "104", "24", - "MKK", "5G", "20M", "HT", "4T", "104", "24", - "FCC", "5G", "20M", "HT", "4T", "108", "24", - "ETSI", "5G", "20M", "HT", "4T", "108", "24", - "MKK", "5G", "20M", "HT", "4T", "108", "24", - "FCC", "5G", "20M", "HT", "4T", "112", "24", - "ETSI", "5G", "20M", "HT", "4T", "112", "24", - "MKK", "5G", "20M", "HT", "4T", "112", "24", - "FCC", "5G", "20M", "HT", "4T", "116", "24", - "ETSI", "5G", "20M", "HT", "4T", "116", "24", - "MKK", "5G", "20M", "HT", "4T", "116", "24", - "FCC", "5G", "20M", "HT", "4T", "120", "24", - "ETSI", "5G", "20M", "HT", "4T", "120", "24", - "MKK", "5G", "20M", "HT", "4T", "120", "24", - "FCC", "5G", "20M", "HT", "4T", "124", "24", - "ETSI", "5G", "20M", "HT", "4T", "124", "24", - "MKK", "5G", "20M", "HT", "4T", "124", "24", - "FCC", "5G", "20M", "HT", "4T", "128", "24", - "ETSI", "5G", "20M", "HT", "4T", "128", "24", - "MKK", "5G", "20M", "HT", "4T", "128", "24", - "FCC", "5G", "20M", "HT", "4T", "132", "24", - "ETSI", "5G", "20M", "HT", "4T", "132", "24", - "MKK", "5G", "20M", "HT", "4T", "132", "24", - "FCC", "5G", "20M", "HT", "4T", "136", "24", - "ETSI", "5G", "20M", "HT", "4T", "136", "24", - "MKK", "5G", "20M", "HT", "4T", "136", "24", - "FCC", "5G", "20M", "HT", "4T", "140", "20", - "ETSI", "5G", "20M", "HT", "4T", "140", "24", - "MKK", "5G", "20M", "HT", "4T", "140", "24", - "FCC", "5G", "20M", "HT", "4T", "149", "20", - "ETSI", "5G", "20M", "HT", "4T", "149", "24", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "24", - "ETSI", "5G", "20M", "HT", "4T", "153", "24", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "24", - "ETSI", "5G", "20M", "HT", "4T", "157", "24", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "24", - "ETSI", "5G", "20M", "HT", "4T", "161", "24", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "24", - "ETSI", "5G", "20M", "HT", "4T", "165", "24", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "26", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "26", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "26", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "24", - "ETSI", "5G", "40M", "HT", "2T", "38", "28", - "MKK", "5G", "40M", "HT", "2T", "38", "28", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "28", - "MKK", "5G", "40M", "HT", "2T", "46", "28", - "FCC", "5G", "40M", "HT", "2T", "54", "28", - "ETSI", "5G", "40M", "HT", "2T", "54", "28", - "MKK", "5G", "40M", "HT", "2T", "54", "28", - "FCC", "5G", "40M", "HT", "2T", "62", "24", - "ETSI", "5G", "40M", "HT", "2T", "62", "28", - "MKK", "5G", "40M", "HT", "2T", "62", "28", - "FCC", "5G", "40M", "HT", "2T", "102", "24", - "ETSI", "5G", "40M", "HT", "2T", "102", "28", - "MKK", "5G", "40M", "HT", "2T", "102", "28", - "FCC", "5G", "40M", "HT", "2T", "110", "28", - "ETSI", "5G", "40M", "HT", "2T", "110", "28", - "MKK", "5G", "40M", "HT", "2T", "110", "28", - "FCC", "5G", "40M", "HT", "2T", "118", "28", - "ETSI", "5G", "40M", "HT", "2T", "118", "28", - "MKK", "5G", "40M", "HT", "2T", "118", "28", - "FCC", "5G", "40M", "HT", "2T", "126", "28", - "ETSI", "5G", "40M", "HT", "2T", "126", "28", - "MKK", "5G", "40M", "HT", "2T", "126", "28", - "FCC", "5G", "40M", "HT", "2T", "134", "28", - "ETSI", "5G", "40M", "HT", "2T", "134", "28", - "MKK", "5G", "40M", "HT", "2T", "134", "28", - "FCC", "5G", "40M", "HT", "2T", "151", "24", - "ETSI", "5G", "40M", "HT", "2T", "151", "28", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "28", - "ETSI", "5G", "40M", "HT", "2T", "159", "28", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "20", - "ETSI", "5G", "40M", "HT", "3T", "38", "26", - "MKK", "5G", "40M", "HT", "3T", "38", "26", - "FCC", "5G", "40M", "HT", "3T", "46", "26", - "ETSI", "5G", "40M", "HT", "3T", "46", "26", - "MKK", "5G", "40M", "HT", "3T", "46", "26", - "FCC", "5G", "40M", "HT", "3T", "54", "26", - "ETSI", "5G", "40M", "HT", "3T", "54", "26", - "MKK", "5G", "40M", "HT", "3T", "54", "26", - "FCC", "5G", "40M", "HT", "3T", "62", "20", - "ETSI", "5G", "40M", "HT", "3T", "62", "26", - "MKK", "5G", "40M", "HT", "3T", "62", "26", - "FCC", "5G", "40M", "HT", "3T", "102", "20", - "ETSI", "5G", "40M", "HT", "3T", "102", "26", - "MKK", "5G", "40M", "HT", "3T", "102", "26", - "FCC", "5G", "40M", "HT", "3T", "110", "26", - "ETSI", "5G", "40M", "HT", "3T", "110", "26", - "MKK", "5G", "40M", "HT", "3T", "110", "26", - "FCC", "5G", "40M", "HT", "3T", "118", "26", - "ETSI", "5G", "40M", "HT", "3T", "118", "26", - "MKK", "5G", "40M", "HT", "3T", "118", "26", - "FCC", "5G", "40M", "HT", "3T", "126", "26", - "ETSI", "5G", "40M", "HT", "3T", "126", "26", - "MKK", "5G", "40M", "HT", "3T", "126", "26", - "FCC", "5G", "40M", "HT", "3T", "134", "26", - "ETSI", "5G", "40M", "HT", "3T", "134", "26", - "MKK", "5G", "40M", "HT", "3T", "134", "26", - "FCC", "5G", "40M", "HT", "3T", "151", "20", - "ETSI", "5G", "40M", "HT", "3T", "151", "26", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "26", - "ETSI", "5G", "40M", "HT", "3T", "159", "26", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "18", - "ETSI", "5G", "40M", "HT", "4T", "38", "24", - "MKK", "5G", "40M", "HT", "4T", "38", "24", - "FCC", "5G", "40M", "HT", "4T", "46", "24", - "ETSI", "5G", "40M", "HT", "4T", "46", "24", - "MKK", "5G", "40M", "HT", "4T", "46", "24", - "FCC", "5G", "40M", "HT", "4T", "54", "24", - "ETSI", "5G", "40M", "HT", "4T", "54", "24", - "MKK", "5G", "40M", "HT", "4T", "54", "24", - "FCC", "5G", "40M", "HT", "4T", "62", "18", - "ETSI", "5G", "40M", "HT", "4T", "62", "24", - "MKK", "5G", "40M", "HT", "4T", "62", "24", - "FCC", "5G", "40M", "HT", "4T", "102", "18", - "ETSI", "5G", "40M", "HT", "4T", "102", "24", - "MKK", "5G", "40M", "HT", "4T", "102", "24", - "FCC", "5G", "40M", "HT", "4T", "110", "24", - "ETSI", "5G", "40M", "HT", "4T", "110", "24", - "MKK", "5G", "40M", "HT", "4T", "110", "24", - "FCC", "5G", "40M", "HT", "4T", "118", "24", - "ETSI", "5G", "40M", "HT", "4T", "118", "24", - "MKK", "5G", "40M", "HT", "4T", "118", "24", - "FCC", "5G", "40M", "HT", "4T", "126", "24", - "ETSI", "5G", "40M", "HT", "4T", "126", "24", - "MKK", "5G", "40M", "HT", "4T", "126", "24", - "FCC", "5G", "40M", "HT", "4T", "134", "24", - "ETSI", "5G", "40M", "HT", "4T", "134", "24", - "MKK", "5G", "40M", "HT", "4T", "134", "24", - "FCC", "5G", "40M", "HT", "4T", "151", "18", - "ETSI", "5G", "40M", "HT", "4T", "151", "24", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "24", - "ETSI", "5G", "40M", "HT", "4T", "159", "24", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "22", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "22", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "22", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "20", - "ETSI", "5G", "80M", "VHT", "2T", "42", "28", - "MKK", "5G", "80M", "VHT", "2T", "42", "28", - "FCC", "5G", "80M", "VHT", "2T", "58", "20", - "ETSI", "5G", "80M", "VHT", "2T", "58", "28", - "MKK", "5G", "80M", "VHT", "2T", "58", "28", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "28", - "MKK", "5G", "80M", "VHT", "2T", "106", "28", - "FCC", "5G", "80M", "VHT", "2T", "122", "28", - "ETSI", "5G", "80M", "VHT", "2T", "122", "28", - "MKK", "5G", "80M", "VHT", "2T", "122", "28", - "FCC", "5G", "80M", "VHT", "2T", "155", "20", - "ETSI", "5G", "80M", "VHT", "2T", "155", "28", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "18", - "ETSI", "5G", "80M", "VHT", "3T", "42", "26", - "MKK", "5G", "80M", "VHT", "3T", "42", "26", - "FCC", "5G", "80M", "VHT", "3T", "58", "18", - "ETSI", "5G", "80M", "VHT", "3T", "58", "26", - "MKK", "5G", "80M", "VHT", "3T", "58", "26", - "FCC", "5G", "80M", "VHT", "3T", "106", "18", - "ETSI", "5G", "80M", "VHT", "3T", "106", "26", - "MKK", "5G", "80M", "VHT", "3T", "106", "26", - "FCC", "5G", "80M", "VHT", "3T", "122", "26", - "ETSI", "5G", "80M", "VHT", "3T", "122", "26", - "MKK", "5G", "80M", "VHT", "3T", "122", "26", - "FCC", "5G", "80M", "VHT", "3T", "155", "18", - "ETSI", "5G", "80M", "VHT", "3T", "155", "26", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "16", - "ETSI", "5G", "80M", "VHT", "4T", "42", "24", - "MKK", "5G", "80M", "VHT", "4T", "42", "24", - "FCC", "5G", "80M", "VHT", "4T", "58", "16", - "ETSI", "5G", "80M", "VHT", "4T", "58", "24", - "MKK", "5G", "80M", "VHT", "4T", "58", "24", - "FCC", "5G", "80M", "VHT", "4T", "106", "16", - "ETSI", "5G", "80M", "VHT", "4T", "106", "24", - "MKK", "5G", "80M", "VHT", "4T", "106", "24", - "FCC", "5G", "80M", "VHT", "4T", "122", "24", - "ETSI", "5G", "80M", "VHT", "4T", "122", "24", - "MKK", "5G", "80M", "VHT", "4T", "122", "24", - "FCC", "5G", "80M", "VHT", "4T", "155", "16", - "ETSI", "5G", "80M", "VHT", "4T", "155", "24", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type6)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type6; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type6)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type6; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type7.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type7[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "44", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "52", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "38", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "38", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "44", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "42", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "40", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "38", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "36", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "36", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "36", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "36", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "36", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "36", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "36", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "36", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "36", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "36", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "36", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "36", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "36", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "36", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "36", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "36", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "36", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "36", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "36", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "34", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "38", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "38", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "38", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "38", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "34", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "34", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "34", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "34", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "34", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "34", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "34", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "34", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "34", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "34", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "34", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "34", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "34", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "34", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "34", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "34", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "32", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "30", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "36", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "36", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "36", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "36", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "32", - "ETSI", "5G", "20M", "HT", "3T", "36", "28", - "MKK", "5G", "20M", "HT", "3T", "36", "28", - "FCC", "5G", "20M", "HT", "3T", "40", "32", - "ETSI", "5G", "20M", "HT", "3T", "40", "28", - "MKK", "5G", "20M", "HT", "3T", "40", "28", - "FCC", "5G", "20M", "HT", "3T", "44", "32", - "ETSI", "5G", "20M", "HT", "3T", "44", "28", - "MKK", "5G", "20M", "HT", "3T", "44", "28", - "FCC", "5G", "20M", "HT", "3T", "48", "32", - "ETSI", "5G", "20M", "HT", "3T", "48", "28", - "MKK", "5G", "20M", "HT", "3T", "48", "28", - "FCC", "5G", "20M", "HT", "3T", "52", "32", - "ETSI", "5G", "20M", "HT", "3T", "52", "28", - "MKK", "5G", "20M", "HT", "3T", "52", "28", - "FCC", "5G", "20M", "HT", "3T", "56", "32", - "ETSI", "5G", "20M", "HT", "3T", "56", "28", - "MKK", "5G", "20M", "HT", "3T", "56", "28", - "FCC", "5G", "20M", "HT", "3T", "60", "32", - "ETSI", "5G", "20M", "HT", "3T", "60", "28", - "MKK", "5G", "20M", "HT", "3T", "60", "28", - "FCC", "5G", "20M", "HT", "3T", "64", "32", - "ETSI", "5G", "20M", "HT", "3T", "64", "28", - "MKK", "5G", "20M", "HT", "3T", "64", "28", - "FCC", "5G", "20M", "HT", "3T", "100", "32", - "ETSI", "5G", "20M", "HT", "3T", "100", "28", - "MKK", "5G", "20M", "HT", "3T", "100", "28", - "FCC", "5G", "20M", "HT", "3T", "104", "32", - "ETSI", "5G", "20M", "HT", "3T", "104", "28", - "MKK", "5G", "20M", "HT", "3T", "104", "28", - "FCC", "5G", "20M", "HT", "3T", "108", "32", - "ETSI", "5G", "20M", "HT", "3T", "108", "28", - "MKK", "5G", "20M", "HT", "3T", "108", "28", - "FCC", "5G", "20M", "HT", "3T", "112", "32", - "ETSI", "5G", "20M", "HT", "3T", "112", "28", - "MKK", "5G", "20M", "HT", "3T", "112", "28", - "FCC", "5G", "20M", "HT", "3T", "116", "32", - "ETSI", "5G", "20M", "HT", "3T", "116", "28", - "MKK", "5G", "20M", "HT", "3T", "116", "28", - "FCC", "5G", "20M", "HT", "3T", "120", "32", - "ETSI", "5G", "20M", "HT", "3T", "120", "28", - "MKK", "5G", "20M", "HT", "3T", "120", "28", - "FCC", "5G", "20M", "HT", "3T", "124", "32", - "ETSI", "5G", "20M", "HT", "3T", "124", "28", - "MKK", "5G", "20M", "HT", "3T", "124", "28", - "FCC", "5G", "20M", "HT", "3T", "128", "32", - "ETSI", "5G", "20M", "HT", "3T", "128", "28", - "MKK", "5G", "20M", "HT", "3T", "128", "28", - "FCC", "5G", "20M", "HT", "3T", "132", "32", - "ETSI", "5G", "20M", "HT", "3T", "132", "28", - "MKK", "5G", "20M", "HT", "3T", "132", "28", - "FCC", "5G", "20M", "HT", "3T", "136", "32", - "ETSI", "5G", "20M", "HT", "3T", "136", "28", - "MKK", "5G", "20M", "HT", "3T", "136", "28", - "FCC", "5G", "20M", "HT", "3T", "140", "30", - "ETSI", "5G", "20M", "HT", "3T", "140", "28", - "MKK", "5G", "20M", "HT", "3T", "140", "28", - "FCC", "5G", "20M", "HT", "3T", "149", "28", - "ETSI", "5G", "20M", "HT", "3T", "149", "28", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "34", - "ETSI", "5G", "20M", "HT", "3T", "153", "28", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "34", - "ETSI", "5G", "20M", "HT", "3T", "157", "28", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "34", - "ETSI", "5G", "20M", "HT", "3T", "161", "28", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "34", - "ETSI", "5G", "20M", "HT", "3T", "165", "28", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "30", - "ETSI", "5G", "20M", "HT", "4T", "36", "26", - "MKK", "5G", "20M", "HT", "4T", "36", "26", - "FCC", "5G", "20M", "HT", "4T", "40", "30", - "ETSI", "5G", "20M", "HT", "4T", "40", "26", - "MKK", "5G", "20M", "HT", "4T", "40", "26", - "FCC", "5G", "20M", "HT", "4T", "44", "30", - "ETSI", "5G", "20M", "HT", "4T", "44", "26", - "MKK", "5G", "20M", "HT", "4T", "44", "26", - "FCC", "5G", "20M", "HT", "4T", "48", "30", - "ETSI", "5G", "20M", "HT", "4T", "48", "26", - "MKK", "5G", "20M", "HT", "4T", "48", "26", - "FCC", "5G", "20M", "HT", "4T", "52", "30", - "ETSI", "5G", "20M", "HT", "4T", "52", "26", - "MKK", "5G", "20M", "HT", "4T", "52", "26", - "FCC", "5G", "20M", "HT", "4T", "56", "30", - "ETSI", "5G", "20M", "HT", "4T", "56", "26", - "MKK", "5G", "20M", "HT", "4T", "56", "26", - "FCC", "5G", "20M", "HT", "4T", "60", "30", - "ETSI", "5G", "20M", "HT", "4T", "60", "26", - "MKK", "5G", "20M", "HT", "4T", "60", "26", - "FCC", "5G", "20M", "HT", "4T", "64", "30", - "ETSI", "5G", "20M", "HT", "4T", "64", "26", - "MKK", "5G", "20M", "HT", "4T", "64", "26", - "FCC", "5G", "20M", "HT", "4T", "100", "30", - "ETSI", "5G", "20M", "HT", "4T", "100", "26", - "MKK", "5G", "20M", "HT", "4T", "100", "26", - "FCC", "5G", "20M", "HT", "4T", "104", "30", - "ETSI", "5G", "20M", "HT", "4T", "104", "26", - "MKK", "5G", "20M", "HT", "4T", "104", "26", - "FCC", "5G", "20M", "HT", "4T", "108", "30", - "ETSI", "5G", "20M", "HT", "4T", "108", "26", - "MKK", "5G", "20M", "HT", "4T", "108", "26", - "FCC", "5G", "20M", "HT", "4T", "112", "30", - "ETSI", "5G", "20M", "HT", "4T", "112", "26", - "MKK", "5G", "20M", "HT", "4T", "112", "26", - "FCC", "5G", "20M", "HT", "4T", "116", "30", - "ETSI", "5G", "20M", "HT", "4T", "116", "26", - "MKK", "5G", "20M", "HT", "4T", "116", "26", - "FCC", "5G", "20M", "HT", "4T", "120", "30", - "ETSI", "5G", "20M", "HT", "4T", "120", "26", - "MKK", "5G", "20M", "HT", "4T", "120", "26", - "FCC", "5G", "20M", "HT", "4T", "124", "30", - "ETSI", "5G", "20M", "HT", "4T", "124", "26", - "MKK", "5G", "20M", "HT", "4T", "124", "26", - "FCC", "5G", "20M", "HT", "4T", "128", "30", - "ETSI", "5G", "20M", "HT", "4T", "128", "26", - "MKK", "5G", "20M", "HT", "4T", "128", "26", - "FCC", "5G", "20M", "HT", "4T", "132", "30", - "ETSI", "5G", "20M", "HT", "4T", "132", "26", - "MKK", "5G", "20M", "HT", "4T", "132", "26", - "FCC", "5G", "20M", "HT", "4T", "136", "30", - "ETSI", "5G", "20M", "HT", "4T", "136", "26", - "MKK", "5G", "20M", "HT", "4T", "136", "26", - "FCC", "5G", "20M", "HT", "4T", "140", "28", - "ETSI", "5G", "20M", "HT", "4T", "140", "26", - "MKK", "5G", "20M", "HT", "4T", "140", "26", - "FCC", "5G", "20M", "HT", "4T", "149", "26", - "ETSI", "5G", "20M", "HT", "4T", "149", "26", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "32", - "ETSI", "5G", "20M", "HT", "4T", "153", "26", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "32", - "ETSI", "5G", "20M", "HT", "4T", "157", "26", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "32", - "ETSI", "5G", "20M", "HT", "4T", "161", "26", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "32", - "ETSI", "5G", "20M", "HT", "4T", "165", "26", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "32", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "30", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "30", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "38", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "38", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "38", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "38", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "32", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "30", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "28", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "28", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "36", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "36", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "36", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "36", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "28", - "ETSI", "5G", "40M", "HT", "3T", "38", "28", - "MKK", "5G", "40M", "HT", "3T", "38", "28", - "FCC", "5G", "40M", "HT", "3T", "46", "28", - "ETSI", "5G", "40M", "HT", "3T", "46", "28", - "MKK", "5G", "40M", "HT", "3T", "46", "28", - "FCC", "5G", "40M", "HT", "3T", "54", "28", - "ETSI", "5G", "40M", "HT", "3T", "54", "28", - "MKK", "5G", "40M", "HT", "3T", "54", "28", - "FCC", "5G", "40M", "HT", "3T", "62", "26", - "ETSI", "5G", "40M", "HT", "3T", "62", "28", - "MKK", "5G", "40M", "HT", "3T", "62", "28", - "FCC", "5G", "40M", "HT", "3T", "102", "26", - "ETSI", "5G", "40M", "HT", "3T", "102", "28", - "MKK", "5G", "40M", "HT", "3T", "102", "28", - "FCC", "5G", "40M", "HT", "3T", "110", "34", - "ETSI", "5G", "40M", "HT", "3T", "110", "28", - "MKK", "5G", "40M", "HT", "3T", "110", "28", - "FCC", "5G", "40M", "HT", "3T", "118", "34", - "ETSI", "5G", "40M", "HT", "3T", "118", "28", - "MKK", "5G", "40M", "HT", "3T", "118", "28", - "FCC", "5G", "40M", "HT", "3T", "126", "34", - "ETSI", "5G", "40M", "HT", "3T", "126", "28", - "MKK", "5G", "40M", "HT", "3T", "126", "28", - "FCC", "5G", "40M", "HT", "3T", "134", "34", - "ETSI", "5G", "40M", "HT", "3T", "134", "28", - "MKK", "5G", "40M", "HT", "3T", "134", "28", - "FCC", "5G", "40M", "HT", "3T", "151", "28", - "ETSI", "5G", "40M", "HT", "3T", "151", "28", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "28", - "ETSI", "5G", "40M", "HT", "3T", "159", "28", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "26", - "ETSI", "5G", "40M", "HT", "4T", "38", "26", - "MKK", "5G", "40M", "HT", "4T", "38", "26", - "FCC", "5G", "40M", "HT", "4T", "46", "26", - "ETSI", "5G", "40M", "HT", "4T", "46", "26", - "MKK", "5G", "40M", "HT", "4T", "46", "26", - "FCC", "5G", "40M", "HT", "4T", "54", "26", - "ETSI", "5G", "40M", "HT", "4T", "54", "26", - "MKK", "5G", "40M", "HT", "4T", "54", "26", - "FCC", "5G", "40M", "HT", "4T", "62", "24", - "ETSI", "5G", "40M", "HT", "4T", "62", "26", - "MKK", "5G", "40M", "HT", "4T", "62", "26", - "FCC", "5G", "40M", "HT", "4T", "102", "24", - "ETSI", "5G", "40M", "HT", "4T", "102", "26", - "MKK", "5G", "40M", "HT", "4T", "102", "26", - "FCC", "5G", "40M", "HT", "4T", "110", "32", - "ETSI", "5G", "40M", "HT", "4T", "110", "26", - "MKK", "5G", "40M", "HT", "4T", "110", "26", - "FCC", "5G", "40M", "HT", "4T", "118", "32", - "ETSI", "5G", "40M", "HT", "4T", "118", "26", - "MKK", "5G", "40M", "HT", "4T", "118", "26", - "FCC", "5G", "40M", "HT", "4T", "126", "32", - "ETSI", "5G", "40M", "HT", "4T", "126", "26", - "MKK", "5G", "40M", "HT", "4T", "126", "26", - "FCC", "5G", "40M", "HT", "4T", "134", "32", - "ETSI", "5G", "40M", "HT", "4T", "134", "26", - "MKK", "5G", "40M", "HT", "4T", "134", "26", - "FCC", "5G", "40M", "HT", "4T", "151", "26", - "ETSI", "5G", "40M", "HT", "4T", "151", "26", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "26", - "ETSI", "5G", "40M", "HT", "4T", "159", "26", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "26", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "26", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "28", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "28", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "28", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "24", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "24", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "26", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "26", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "26", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "22", - "ETSI", "5G", "80M", "VHT", "3T", "42", "28", - "MKK", "5G", "80M", "VHT", "3T", "42", "28", - "FCC", "5G", "80M", "VHT", "3T", "58", "22", - "ETSI", "5G", "80M", "VHT", "3T", "58", "28", - "MKK", "5G", "80M", "VHT", "3T", "58", "28", - "FCC", "5G", "80M", "VHT", "3T", "106", "24", - "ETSI", "5G", "80M", "VHT", "3T", "106", "28", - "MKK", "5G", "80M", "VHT", "3T", "106", "28", - "FCC", "5G", "80M", "VHT", "3T", "122", "24", - "ETSI", "5G", "80M", "VHT", "3T", "122", "28", - "MKK", "5G", "80M", "VHT", "3T", "122", "28", - "FCC", "5G", "80M", "VHT", "3T", "155", "24", - "ETSI", "5G", "80M", "VHT", "3T", "155", "28", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "20", - "ETSI", "5G", "80M", "VHT", "4T", "42", "26", - "MKK", "5G", "80M", "VHT", "4T", "42", "26", - "FCC", "5G", "80M", "VHT", "4T", "58", "20", - "ETSI", "5G", "80M", "VHT", "4T", "58", "26", - "MKK", "5G", "80M", "VHT", "4T", "58", "26", - "FCC", "5G", "80M", "VHT", "4T", "106", "22", - "ETSI", "5G", "80M", "VHT", "4T", "106", "26", - "MKK", "5G", "80M", "VHT", "4T", "106", "26", - "FCC", "5G", "80M", "VHT", "4T", "122", "22", - "ETSI", "5G", "80M", "VHT", "4T", "122", "26", - "MKK", "5G", "80M", "VHT", "4T", "122", "26", - "FCC", "5G", "80M", "VHT", "4T", "155", "22", - "ETSI", "5G", "80M", "VHT", "4T", "155", "26", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type7)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type7; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type7)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type7; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type8.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type8[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "46", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "46", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "46", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "46", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "46", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "46", - "FCC", "2.4G", "20M", "HT", "1T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "46", - "MKK", "2.4G", "20M", "HT", "1T", "01", "46", - "FCC", "2.4G", "20M", "HT", "1T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "46", - "MKK", "2.4G", "20M", "HT", "1T", "02", "46", - "FCC", "2.4G", "20M", "HT", "1T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "46", - "MKK", "2.4G", "20M", "HT", "1T", "03", "46", - "FCC", "2.4G", "20M", "HT", "1T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "46", - "MKK", "2.4G", "20M", "HT", "1T", "04", "46", - "FCC", "2.4G", "20M", "HT", "1T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "46", - "MKK", "2.4G", "20M", "HT", "1T", "05", "46", - "FCC", "2.4G", "20M", "HT", "1T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "46", - "MKK", "2.4G", "20M", "HT", "1T", "06", "46", - "FCC", "2.4G", "20M", "HT", "1T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "46", - "MKK", "2.4G", "20M", "HT", "1T", "07", "46", - "FCC", "2.4G", "20M", "HT", "1T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "46", - "MKK", "2.4G", "20M", "HT", "1T", "08", "46", - "FCC", "2.4G", "20M", "HT", "1T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "46", - "MKK", "2.4G", "20M", "HT", "1T", "09", "46", - "FCC", "2.4G", "20M", "HT", "1T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "46", - "MKK", "2.4G", "20M", "HT", "1T", "10", "46", - "FCC", "2.4G", "20M", "HT", "1T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "46", - "MKK", "2.4G", "20M", "HT", "1T", "11", "46", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "46", - "MKK", "2.4G", "20M", "HT", "1T", "12", "46", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "46", - "MKK", "2.4G", "20M", "HT", "1T", "13", "46", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "46", - "FCC", "2.4G", "20M", "HT", "2T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "46", - "MKK", "2.4G", "20M", "HT", "2T", "01", "46", - "FCC", "2.4G", "20M", "HT", "2T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "46", - "MKK", "2.4G", "20M", "HT", "2T", "02", "46", - "FCC", "2.4G", "20M", "HT", "2T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "46", - "MKK", "2.4G", "20M", "HT", "2T", "03", "46", - "FCC", "2.4G", "20M", "HT", "2T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "46", - "MKK", "2.4G", "20M", "HT", "2T", "04", "46", - "FCC", "2.4G", "20M", "HT", "2T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "46", - "MKK", "2.4G", "20M", "HT", "2T", "05", "46", - "FCC", "2.4G", "20M", "HT", "2T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "46", - "MKK", "2.4G", "20M", "HT", "2T", "06", "46", - "FCC", "2.4G", "20M", "HT", "2T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "46", - "MKK", "2.4G", "20M", "HT", "2T", "07", "46", - "FCC", "2.4G", "20M", "HT", "2T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "46", - "MKK", "2.4G", "20M", "HT", "2T", "08", "46", - "FCC", "2.4G", "20M", "HT", "2T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "46", - "MKK", "2.4G", "20M", "HT", "2T", "09", "46", - "FCC", "2.4G", "20M", "HT", "2T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "46", - "MKK", "2.4G", "20M", "HT", "2T", "10", "46", - "FCC", "2.4G", "20M", "HT", "2T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "46", - "MKK", "2.4G", "20M", "HT", "2T", "11", "46", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "46", - "MKK", "2.4G", "20M", "HT", "2T", "12", "46", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "46", - "MKK", "2.4G", "20M", "HT", "2T", "13", "46", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "46", - "FCC", "2.4G", "20M", "HT", "3T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "46", - "MKK", "2.4G", "20M", "HT", "3T", "01", "46", - "FCC", "2.4G", "20M", "HT", "3T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "46", - "MKK", "2.4G", "20M", "HT", "3T", "02", "46", - "FCC", "2.4G", "20M", "HT", "3T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "46", - "MKK", "2.4G", "20M", "HT", "3T", "03", "46", - "FCC", "2.4G", "20M", "HT", "3T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "46", - "MKK", "2.4G", "20M", "HT", "3T", "04", "46", - "FCC", "2.4G", "20M", "HT", "3T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "46", - "MKK", "2.4G", "20M", "HT", "3T", "05", "46", - "FCC", "2.4G", "20M", "HT", "3T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "46", - "MKK", "2.4G", "20M", "HT", "3T", "06", "46", - "FCC", "2.4G", "20M", "HT", "3T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "46", - "MKK", "2.4G", "20M", "HT", "3T", "07", "46", - "FCC", "2.4G", "20M", "HT", "3T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "46", - "MKK", "2.4G", "20M", "HT", "3T", "08", "46", - "FCC", "2.4G", "20M", "HT", "3T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "46", - "MKK", "2.4G", "20M", "HT", "3T", "09", "46", - "FCC", "2.4G", "20M", "HT", "3T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "46", - "MKK", "2.4G", "20M", "HT", "3T", "10", "46", - "FCC", "2.4G", "20M", "HT", "3T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "46", - "MKK", "2.4G", "20M", "HT", "3T", "11", "46", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "46", - "MKK", "2.4G", "20M", "HT", "3T", "12", "46", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "46", - "MKK", "2.4G", "20M", "HT", "3T", "13", "46", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "46", - "FCC", "2.4G", "20M", "HT", "4T", "01", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "46", - "MKK", "2.4G", "20M", "HT", "4T", "01", "46", - "FCC", "2.4G", "20M", "HT", "4T", "02", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "46", - "MKK", "2.4G", "20M", "HT", "4T", "02", "46", - "FCC", "2.4G", "20M", "HT", "4T", "03", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "46", - "MKK", "2.4G", "20M", "HT", "4T", "03", "46", - "FCC", "2.4G", "20M", "HT", "4T", "04", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "46", - "MKK", "2.4G", "20M", "HT", "4T", "04", "46", - "FCC", "2.4G", "20M", "HT", "4T", "05", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "46", - "MKK", "2.4G", "20M", "HT", "4T", "05", "46", - "FCC", "2.4G", "20M", "HT", "4T", "06", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "46", - "MKK", "2.4G", "20M", "HT", "4T", "06", "46", - "FCC", "2.4G", "20M", "HT", "4T", "07", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "46", - "MKK", "2.4G", "20M", "HT", "4T", "07", "46", - "FCC", "2.4G", "20M", "HT", "4T", "08", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "46", - "MKK", "2.4G", "20M", "HT", "4T", "08", "46", - "FCC", "2.4G", "20M", "HT", "4T", "09", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "46", - "MKK", "2.4G", "20M", "HT", "4T", "09", "46", - "FCC", "2.4G", "20M", "HT", "4T", "10", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "46", - "MKK", "2.4G", "20M", "HT", "4T", "10", "46", - "FCC", "2.4G", "20M", "HT", "4T", "11", "46", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "46", - "MKK", "2.4G", "20M", "HT", "4T", "11", "46", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "46", - "MKK", "2.4G", "20M", "HT", "4T", "12", "46", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "46", - "MKK", "2.4G", "20M", "HT", "4T", "13", "46", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "46", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", - "MKK", "2.4G", "40M", "HT", "1T", "12", "34", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", - "MKK", "2.4G", "40M", "HT", "1T", "13", "34", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "34", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "34", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "34", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "34", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", - "MKK", "2.4G", "40M", "HT", "2T", "12", "34", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", - "MKK", "2.4G", "40M", "HT", "2T", "13", "34", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", - "MKK", "2.4G", "40M", "HT", "3T", "03", "34", - "FCC", "2.4G", "40M", "HT", "3T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", - "MKK", "2.4G", "40M", "HT", "3T", "04", "34", - "FCC", "2.4G", "40M", "HT", "3T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", - "MKK", "2.4G", "40M", "HT", "3T", "05", "34", - "FCC", "2.4G", "40M", "HT", "3T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", - "MKK", "2.4G", "40M", "HT", "3T", "06", "34", - "FCC", "2.4G", "40M", "HT", "3T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", - "MKK", "2.4G", "40M", "HT", "3T", "07", "34", - "FCC", "2.4G", "40M", "HT", "3T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", - "MKK", "2.4G", "40M", "HT", "3T", "08", "34", - "FCC", "2.4G", "40M", "HT", "3T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", - "MKK", "2.4G", "40M", "HT", "3T", "09", "34", - "FCC", "2.4G", "40M", "HT", "3T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", - "MKK", "2.4G", "40M", "HT", "3T", "10", "34", - "FCC", "2.4G", "40M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", - "MKK", "2.4G", "40M", "HT", "3T", "11", "34", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", - "MKK", "2.4G", "40M", "HT", "3T", "12", "34", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", - "MKK", "2.4G", "40M", "HT", "3T", "13", "34", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", - "MKK", "2.4G", "40M", "HT", "4T", "03", "34", - "FCC", "2.4G", "40M", "HT", "4T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", - "MKK", "2.4G", "40M", "HT", "4T", "04", "34", - "FCC", "2.4G", "40M", "HT", "4T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", - "MKK", "2.4G", "40M", "HT", "4T", "05", "34", - "FCC", "2.4G", "40M", "HT", "4T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", - "MKK", "2.4G", "40M", "HT", "4T", "06", "34", - "FCC", "2.4G", "40M", "HT", "4T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", - "MKK", "2.4G", "40M", "HT", "4T", "07", "34", - "FCC", "2.4G", "40M", "HT", "4T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", - "MKK", "2.4G", "40M", "HT", "4T", "08", "34", - "FCC", "2.4G", "40M", "HT", "4T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", - "MKK", "2.4G", "40M", "HT", "4T", "09", "34", - "FCC", "2.4G", "40M", "HT", "4T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", - "MKK", "2.4G", "40M", "HT", "4T", "10", "34", - "FCC", "2.4G", "40M", "HT", "4T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", - "MKK", "2.4G", "40M", "HT", "4T", "11", "34", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", - "MKK", "2.4G", "40M", "HT", "4T", "12", "34", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", - "MKK", "2.4G", "40M", "HT", "4T", "13", "34", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "46", - "MKK", "5G", "20M", "OFDM", "1T", "36", "46", - "FCC", "5G", "20M", "OFDM", "1T", "40", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "46", - "MKK", "5G", "20M", "OFDM", "1T", "40", "46", - "FCC", "5G", "20M", "OFDM", "1T", "44", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "46", - "MKK", "5G", "20M", "OFDM", "1T", "44", "46", - "FCC", "5G", "20M", "OFDM", "1T", "48", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "46", - "MKK", "5G", "20M", "OFDM", "1T", "48", "46", - "FCC", "5G", "20M", "OFDM", "1T", "52", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "46", - "MKK", "5G", "20M", "OFDM", "1T", "52", "46", - "FCC", "5G", "20M", "OFDM", "1T", "56", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "46", - "MKK", "5G", "20M", "OFDM", "1T", "56", "46", - "FCC", "5G", "20M", "OFDM", "1T", "60", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "46", - "MKK", "5G", "20M", "OFDM", "1T", "60", "46", - "FCC", "5G", "20M", "OFDM", "1T", "64", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "46", - "MKK", "5G", "20M", "OFDM", "1T", "64", "46", - "FCC", "5G", "20M", "OFDM", "1T", "100", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "46", - "MKK", "5G", "20M", "OFDM", "1T", "100", "46", - "FCC", "5G", "20M", "OFDM", "1T", "104", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "46", - "MKK", "5G", "20M", "OFDM", "1T", "104", "46", - "FCC", "5G", "20M", "OFDM", "1T", "108", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "46", - "MKK", "5G", "20M", "OFDM", "1T", "108", "46", - "FCC", "5G", "20M", "OFDM", "1T", "112", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "46", - "MKK", "5G", "20M", "OFDM", "1T", "112", "46", - "FCC", "5G", "20M", "OFDM", "1T", "116", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "46", - "MKK", "5G", "20M", "OFDM", "1T", "116", "46", - "FCC", "5G", "20M", "OFDM", "1T", "120", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "46", - "MKK", "5G", "20M", "OFDM", "1T", "120", "46", - "FCC", "5G", "20M", "OFDM", "1T", "124", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "46", - "MKK", "5G", "20M", "OFDM", "1T", "124", "46", - "FCC", "5G", "20M", "OFDM", "1T", "128", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "46", - "MKK", "5G", "20M", "OFDM", "1T", "128", "46", - "FCC", "5G", "20M", "OFDM", "1T", "132", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "46", - "MKK", "5G", "20M", "OFDM", "1T", "132", "46", - "FCC", "5G", "20M", "OFDM", "1T", "136", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "46", - "MKK", "5G", "20M", "OFDM", "1T", "136", "46", - "FCC", "5G", "20M", "OFDM", "1T", "140", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "46", - "MKK", "5G", "20M", "OFDM", "1T", "140", "46", - "FCC", "5G", "20M", "OFDM", "1T", "149", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "46", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "46", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "46", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "46", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "46", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "46", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "46", - "ETSI", "5G", "20M", "HT", "1T", "36", "46", - "MKK", "5G", "20M", "HT", "1T", "36", "46", - "FCC", "5G", "20M", "HT", "1T", "40", "46", - "ETSI", "5G", "20M", "HT", "1T", "40", "46", - "MKK", "5G", "20M", "HT", "1T", "40", "46", - "FCC", "5G", "20M", "HT", "1T", "44", "46", - "ETSI", "5G", "20M", "HT", "1T", "44", "46", - "MKK", "5G", "20M", "HT", "1T", "44", "46", - "FCC", "5G", "20M", "HT", "1T", "48", "46", - "ETSI", "5G", "20M", "HT", "1T", "48", "46", - "MKK", "5G", "20M", "HT", "1T", "48", "46", - "FCC", "5G", "20M", "HT", "1T", "52", "46", - "ETSI", "5G", "20M", "HT", "1T", "52", "46", - "MKK", "5G", "20M", "HT", "1T", "52", "46", - "FCC", "5G", "20M", "HT", "1T", "56", "46", - "ETSI", "5G", "20M", "HT", "1T", "56", "46", - "MKK", "5G", "20M", "HT", "1T", "56", "46", - "FCC", "5G", "20M", "HT", "1T", "60", "46", - "ETSI", "5G", "20M", "HT", "1T", "60", "46", - "MKK", "5G", "20M", "HT", "1T", "60", "46", - "FCC", "5G", "20M", "HT", "1T", "64", "46", - "ETSI", "5G", "20M", "HT", "1T", "64", "46", - "MKK", "5G", "20M", "HT", "1T", "64", "46", - "FCC", "5G", "20M", "HT", "1T", "100", "46", - "ETSI", "5G", "20M", "HT", "1T", "100", "46", - "MKK", "5G", "20M", "HT", "1T", "100", "46", - "FCC", "5G", "20M", "HT", "1T", "104", "46", - "ETSI", "5G", "20M", "HT", "1T", "104", "46", - "MKK", "5G", "20M", "HT", "1T", "104", "46", - "FCC", "5G", "20M", "HT", "1T", "108", "46", - "ETSI", "5G", "20M", "HT", "1T", "108", "46", - "MKK", "5G", "20M", "HT", "1T", "108", "46", - "FCC", "5G", "20M", "HT", "1T", "112", "46", - "ETSI", "5G", "20M", "HT", "1T", "112", "46", - "MKK", "5G", "20M", "HT", "1T", "112", "46", - "FCC", "5G", "20M", "HT", "1T", "116", "46", - "ETSI", "5G", "20M", "HT", "1T", "116", "46", - "MKK", "5G", "20M", "HT", "1T", "116", "46", - "FCC", "5G", "20M", "HT", "1T", "120", "46", - "ETSI", "5G", "20M", "HT", "1T", "120", "46", - "MKK", "5G", "20M", "HT", "1T", "120", "46", - "FCC", "5G", "20M", "HT", "1T", "124", "46", - "ETSI", "5G", "20M", "HT", "1T", "124", "46", - "MKK", "5G", "20M", "HT", "1T", "124", "46", - "FCC", "5G", "20M", "HT", "1T", "128", "46", - "ETSI", "5G", "20M", "HT", "1T", "128", "46", - "MKK", "5G", "20M", "HT", "1T", "128", "46", - "FCC", "5G", "20M", "HT", "1T", "132", "46", - "ETSI", "5G", "20M", "HT", "1T", "132", "46", - "MKK", "5G", "20M", "HT", "1T", "132", "46", - "FCC", "5G", "20M", "HT", "1T", "136", "46", - "ETSI", "5G", "20M", "HT", "1T", "136", "46", - "MKK", "5G", "20M", "HT", "1T", "136", "46", - "FCC", "5G", "20M", "HT", "1T", "140", "46", - "ETSI", "5G", "20M", "HT", "1T", "140", "46", - "MKK", "5G", "20M", "HT", "1T", "140", "46", - "FCC", "5G", "20M", "HT", "1T", "149", "46", - "ETSI", "5G", "20M", "HT", "1T", "149", "46", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "46", - "ETSI", "5G", "20M", "HT", "1T", "153", "46", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "46", - "ETSI", "5G", "20M", "HT", "1T", "157", "46", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "46", - "ETSI", "5G", "20M", "HT", "1T", "161", "46", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "46", - "ETSI", "5G", "20M", "HT", "1T", "165", "46", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "46", - "ETSI", "5G", "20M", "HT", "2T", "36", "46", - "MKK", "5G", "20M", "HT", "2T", "36", "46", - "FCC", "5G", "20M", "HT", "2T", "40", "46", - "ETSI", "5G", "20M", "HT", "2T", "40", "46", - "MKK", "5G", "20M", "HT", "2T", "40", "46", - "FCC", "5G", "20M", "HT", "2T", "44", "46", - "ETSI", "5G", "20M", "HT", "2T", "44", "46", - "MKK", "5G", "20M", "HT", "2T", "44", "46", - "FCC", "5G", "20M", "HT", "2T", "48", "46", - "ETSI", "5G", "20M", "HT", "2T", "48", "46", - "MKK", "5G", "20M", "HT", "2T", "48", "46", - "FCC", "5G", "20M", "HT", "2T", "52", "46", - "ETSI", "5G", "20M", "HT", "2T", "52", "46", - "MKK", "5G", "20M", "HT", "2T", "52", "46", - "FCC", "5G", "20M", "HT", "2T", "56", "46", - "ETSI", "5G", "20M", "HT", "2T", "56", "46", - "MKK", "5G", "20M", "HT", "2T", "56", "46", - "FCC", "5G", "20M", "HT", "2T", "60", "46", - "ETSI", "5G", "20M", "HT", "2T", "60", "46", - "MKK", "5G", "20M", "HT", "2T", "60", "46", - "FCC", "5G", "20M", "HT", "2T", "64", "46", - "ETSI", "5G", "20M", "HT", "2T", "64", "46", - "MKK", "5G", "20M", "HT", "2T", "64", "46", - "FCC", "5G", "20M", "HT", "2T", "100", "46", - "ETSI", "5G", "20M", "HT", "2T", "100", "46", - "MKK", "5G", "20M", "HT", "2T", "100", "46", - "FCC", "5G", "20M", "HT", "2T", "104", "46", - "ETSI", "5G", "20M", "HT", "2T", "104", "46", - "MKK", "5G", "20M", "HT", "2T", "104", "46", - "FCC", "5G", "20M", "HT", "2T", "108", "46", - "ETSI", "5G", "20M", "HT", "2T", "108", "46", - "MKK", "5G", "20M", "HT", "2T", "108", "46", - "FCC", "5G", "20M", "HT", "2T", "112", "46", - "ETSI", "5G", "20M", "HT", "2T", "112", "46", - "MKK", "5G", "20M", "HT", "2T", "112", "46", - "FCC", "5G", "20M", "HT", "2T", "116", "46", - "ETSI", "5G", "20M", "HT", "2T", "116", "46", - "MKK", "5G", "20M", "HT", "2T", "116", "46", - "FCC", "5G", "20M", "HT", "2T", "120", "46", - "ETSI", "5G", "20M", "HT", "2T", "120", "46", - "MKK", "5G", "20M", "HT", "2T", "120", "46", - "FCC", "5G", "20M", "HT", "2T", "124", "46", - "ETSI", "5G", "20M", "HT", "2T", "124", "46", - "MKK", "5G", "20M", "HT", "2T", "124", "46", - "FCC", "5G", "20M", "HT", "2T", "128", "46", - "ETSI", "5G", "20M", "HT", "2T", "128", "46", - "MKK", "5G", "20M", "HT", "2T", "128", "46", - "FCC", "5G", "20M", "HT", "2T", "132", "46", - "ETSI", "5G", "20M", "HT", "2T", "132", "46", - "MKK", "5G", "20M", "HT", "2T", "132", "46", - "FCC", "5G", "20M", "HT", "2T", "136", "46", - "ETSI", "5G", "20M", "HT", "2T", "136", "46", - "MKK", "5G", "20M", "HT", "2T", "136", "46", - "FCC", "5G", "20M", "HT", "2T", "140", "46", - "ETSI", "5G", "20M", "HT", "2T", "140", "46", - "MKK", "5G", "20M", "HT", "2T", "140", "46", - "FCC", "5G", "20M", "HT", "2T", "149", "46", - "ETSI", "5G", "20M", "HT", "2T", "149", "46", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "46", - "ETSI", "5G", "20M", "HT", "2T", "153", "46", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "46", - "ETSI", "5G", "20M", "HT", "2T", "157", "46", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "46", - "ETSI", "5G", "20M", "HT", "2T", "161", "46", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "46", - "ETSI", "5G", "20M", "HT", "2T", "165", "46", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "46", - "ETSI", "5G", "20M", "HT", "3T", "36", "46", - "MKK", "5G", "20M", "HT", "3T", "36", "46", - "FCC", "5G", "20M", "HT", "3T", "40", "46", - "ETSI", "5G", "20M", "HT", "3T", "40", "46", - "MKK", "5G", "20M", "HT", "3T", "40", "46", - "FCC", "5G", "20M", "HT", "3T", "44", "46", - "ETSI", "5G", "20M", "HT", "3T", "44", "46", - "MKK", "5G", "20M", "HT", "3T", "44", "46", - "FCC", "5G", "20M", "HT", "3T", "48", "46", - "ETSI", "5G", "20M", "HT", "3T", "48", "46", - "MKK", "5G", "20M", "HT", "3T", "48", "46", - "FCC", "5G", "20M", "HT", "3T", "52", "46", - "ETSI", "5G", "20M", "HT", "3T", "52", "46", - "MKK", "5G", "20M", "HT", "3T", "52", "46", - "FCC", "5G", "20M", "HT", "3T", "56", "46", - "ETSI", "5G", "20M", "HT", "3T", "56", "46", - "MKK", "5G", "20M", "HT", "3T", "56", "46", - "FCC", "5G", "20M", "HT", "3T", "60", "46", - "ETSI", "5G", "20M", "HT", "3T", "60", "46", - "MKK", "5G", "20M", "HT", "3T", "60", "46", - "FCC", "5G", "20M", "HT", "3T", "64", "46", - "ETSI", "5G", "20M", "HT", "3T", "64", "46", - "MKK", "5G", "20M", "HT", "3T", "64", "46", - "FCC", "5G", "20M", "HT", "3T", "100", "46", - "ETSI", "5G", "20M", "HT", "3T", "100", "46", - "MKK", "5G", "20M", "HT", "3T", "100", "46", - "FCC", "5G", "20M", "HT", "3T", "104", "46", - "ETSI", "5G", "20M", "HT", "3T", "104", "46", - "MKK", "5G", "20M", "HT", "3T", "104", "46", - "FCC", "5G", "20M", "HT", "3T", "108", "46", - "ETSI", "5G", "20M", "HT", "3T", "108", "46", - "MKK", "5G", "20M", "HT", "3T", "108", "46", - "FCC", "5G", "20M", "HT", "3T", "112", "46", - "ETSI", "5G", "20M", "HT", "3T", "112", "46", - "MKK", "5G", "20M", "HT", "3T", "112", "46", - "FCC", "5G", "20M", "HT", "3T", "116", "46", - "ETSI", "5G", "20M", "HT", "3T", "116", "46", - "MKK", "5G", "20M", "HT", "3T", "116", "46", - "FCC", "5G", "20M", "HT", "3T", "120", "46", - "ETSI", "5G", "20M", "HT", "3T", "120", "46", - "MKK", "5G", "20M", "HT", "3T", "120", "46", - "FCC", "5G", "20M", "HT", "3T", "124", "46", - "ETSI", "5G", "20M", "HT", "3T", "124", "46", - "MKK", "5G", "20M", "HT", "3T", "124", "46", - "FCC", "5G", "20M", "HT", "3T", "128", "46", - "ETSI", "5G", "20M", "HT", "3T", "128", "46", - "MKK", "5G", "20M", "HT", "3T", "128", "46", - "FCC", "5G", "20M", "HT", "3T", "132", "46", - "ETSI", "5G", "20M", "HT", "3T", "132", "46", - "MKK", "5G", "20M", "HT", "3T", "132", "46", - "FCC", "5G", "20M", "HT", "3T", "136", "46", - "ETSI", "5G", "20M", "HT", "3T", "136", "46", - "MKK", "5G", "20M", "HT", "3T", "136", "46", - "FCC", "5G", "20M", "HT", "3T", "140", "46", - "ETSI", "5G", "20M", "HT", "3T", "140", "46", - "MKK", "5G", "20M", "HT", "3T", "140", "46", - "FCC", "5G", "20M", "HT", "3T", "149", "46", - "ETSI", "5G", "20M", "HT", "3T", "149", "46", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "46", - "ETSI", "5G", "20M", "HT", "3T", "153", "46", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "46", - "ETSI", "5G", "20M", "HT", "3T", "157", "46", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "46", - "ETSI", "5G", "20M", "HT", "3T", "161", "46", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "46", - "ETSI", "5G", "20M", "HT", "3T", "165", "46", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "46", - "ETSI", "5G", "20M", "HT", "4T", "36", "46", - "MKK", "5G", "20M", "HT", "4T", "36", "46", - "FCC", "5G", "20M", "HT", "4T", "40", "46", - "ETSI", "5G", "20M", "HT", "4T", "40", "46", - "MKK", "5G", "20M", "HT", "4T", "40", "46", - "FCC", "5G", "20M", "HT", "4T", "44", "46", - "ETSI", "5G", "20M", "HT", "4T", "44", "46", - "MKK", "5G", "20M", "HT", "4T", "44", "46", - "FCC", "5G", "20M", "HT", "4T", "48", "46", - "ETSI", "5G", "20M", "HT", "4T", "48", "46", - "MKK", "5G", "20M", "HT", "4T", "48", "46", - "FCC", "5G", "20M", "HT", "4T", "52", "46", - "ETSI", "5G", "20M", "HT", "4T", "52", "46", - "MKK", "5G", "20M", "HT", "4T", "52", "46", - "FCC", "5G", "20M", "HT", "4T", "56", "46", - "ETSI", "5G", "20M", "HT", "4T", "56", "46", - "MKK", "5G", "20M", "HT", "4T", "56", "46", - "FCC", "5G", "20M", "HT", "4T", "60", "46", - "ETSI", "5G", "20M", "HT", "4T", "60", "46", - "MKK", "5G", "20M", "HT", "4T", "60", "46", - "FCC", "5G", "20M", "HT", "4T", "64", "46", - "ETSI", "5G", "20M", "HT", "4T", "64", "46", - "MKK", "5G", "20M", "HT", "4T", "64", "46", - "FCC", "5G", "20M", "HT", "4T", "100", "46", - "ETSI", "5G", "20M", "HT", "4T", "100", "46", - "MKK", "5G", "20M", "HT", "4T", "100", "46", - "FCC", "5G", "20M", "HT", "4T", "104", "46", - "ETSI", "5G", "20M", "HT", "4T", "104", "46", - "MKK", "5G", "20M", "HT", "4T", "104", "46", - "FCC", "5G", "20M", "HT", "4T", "108", "46", - "ETSI", "5G", "20M", "HT", "4T", "108", "46", - "MKK", "5G", "20M", "HT", "4T", "108", "46", - "FCC", "5G", "20M", "HT", "4T", "112", "46", - "ETSI", "5G", "20M", "HT", "4T", "112", "46", - "MKK", "5G", "20M", "HT", "4T", "112", "46", - "FCC", "5G", "20M", "HT", "4T", "116", "46", - "ETSI", "5G", "20M", "HT", "4T", "116", "46", - "MKK", "5G", "20M", "HT", "4T", "116", "46", - "FCC", "5G", "20M", "HT", "4T", "120", "46", - "ETSI", "5G", "20M", "HT", "4T", "120", "46", - "MKK", "5G", "20M", "HT", "4T", "120", "46", - "FCC", "5G", "20M", "HT", "4T", "124", "46", - "ETSI", "5G", "20M", "HT", "4T", "124", "46", - "MKK", "5G", "20M", "HT", "4T", "124", "46", - "FCC", "5G", "20M", "HT", "4T", "128", "46", - "ETSI", "5G", "20M", "HT", "4T", "128", "46", - "MKK", "5G", "20M", "HT", "4T", "128", "46", - "FCC", "5G", "20M", "HT", "4T", "132", "46", - "ETSI", "5G", "20M", "HT", "4T", "132", "46", - "MKK", "5G", "20M", "HT", "4T", "132", "46", - "FCC", "5G", "20M", "HT", "4T", "136", "46", - "ETSI", "5G", "20M", "HT", "4T", "136", "46", - "MKK", "5G", "20M", "HT", "4T", "136", "46", - "FCC", "5G", "20M", "HT", "4T", "140", "46", - "ETSI", "5G", "20M", "HT", "4T", "140", "46", - "MKK", "5G", "20M", "HT", "4T", "140", "46", - "FCC", "5G", "20M", "HT", "4T", "149", "46", - "ETSI", "5G", "20M", "HT", "4T", "149", "46", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "46", - "ETSI", "5G", "20M", "HT", "4T", "153", "46", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "46", - "ETSI", "5G", "20M", "HT", "4T", "157", "46", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "46", - "ETSI", "5G", "20M", "HT", "4T", "161", "46", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "46", - "ETSI", "5G", "20M", "HT", "4T", "165", "46", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "46", - "ETSI", "5G", "40M", "HT", "1T", "38", "46", - "MKK", "5G", "40M", "HT", "1T", "38", "46", - "FCC", "5G", "40M", "HT", "1T", "46", "46", - "ETSI", "5G", "40M", "HT", "1T", "46", "46", - "MKK", "5G", "40M", "HT", "1T", "46", "46", - "FCC", "5G", "40M", "HT", "1T", "54", "46", - "ETSI", "5G", "40M", "HT", "1T", "54", "46", - "MKK", "5G", "40M", "HT", "1T", "54", "46", - "FCC", "5G", "40M", "HT", "1T", "62", "46", - "ETSI", "5G", "40M", "HT", "1T", "62", "46", - "MKK", "5G", "40M", "HT", "1T", "62", "46", - "FCC", "5G", "40M", "HT", "1T", "102", "46", - "ETSI", "5G", "40M", "HT", "1T", "102", "46", - "MKK", "5G", "40M", "HT", "1T", "102", "46", - "FCC", "5G", "40M", "HT", "1T", "110", "46", - "ETSI", "5G", "40M", "HT", "1T", "110", "46", - "MKK", "5G", "40M", "HT", "1T", "110", "46", - "FCC", "5G", "40M", "HT", "1T", "118", "46", - "ETSI", "5G", "40M", "HT", "1T", "118", "46", - "MKK", "5G", "40M", "HT", "1T", "118", "46", - "FCC", "5G", "40M", "HT", "1T", "126", "46", - "ETSI", "5G", "40M", "HT", "1T", "126", "46", - "MKK", "5G", "40M", "HT", "1T", "126", "46", - "FCC", "5G", "40M", "HT", "1T", "134", "46", - "ETSI", "5G", "40M", "HT", "1T", "134", "46", - "MKK", "5G", "40M", "HT", "1T", "134", "46", - "FCC", "5G", "40M", "HT", "1T", "151", "46", - "ETSI", "5G", "40M", "HT", "1T", "151", "46", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "46", - "ETSI", "5G", "40M", "HT", "1T", "159", "46", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "46", - "ETSI", "5G", "40M", "HT", "2T", "38", "46", - "MKK", "5G", "40M", "HT", "2T", "38", "46", - "FCC", "5G", "40M", "HT", "2T", "46", "46", - "ETSI", "5G", "40M", "HT", "2T", "46", "46", - "MKK", "5G", "40M", "HT", "2T", "46", "46", - "FCC", "5G", "40M", "HT", "2T", "54", "46", - "ETSI", "5G", "40M", "HT", "2T", "54", "46", - "MKK", "5G", "40M", "HT", "2T", "54", "46", - "FCC", "5G", "40M", "HT", "2T", "62", "46", - "ETSI", "5G", "40M", "HT", "2T", "62", "46", - "MKK", "5G", "40M", "HT", "2T", "62", "46", - "FCC", "5G", "40M", "HT", "2T", "102", "46", - "ETSI", "5G", "40M", "HT", "2T", "102", "46", - "MKK", "5G", "40M", "HT", "2T", "102", "46", - "FCC", "5G", "40M", "HT", "2T", "110", "46", - "ETSI", "5G", "40M", "HT", "2T", "110", "46", - "MKK", "5G", "40M", "HT", "2T", "110", "46", - "FCC", "5G", "40M", "HT", "2T", "118", "46", - "ETSI", "5G", "40M", "HT", "2T", "118", "46", - "MKK", "5G", "40M", "HT", "2T", "118", "46", - "FCC", "5G", "40M", "HT", "2T", "126", "46", - "ETSI", "5G", "40M", "HT", "2T", "126", "46", - "MKK", "5G", "40M", "HT", "2T", "126", "46", - "FCC", "5G", "40M", "HT", "2T", "134", "46", - "ETSI", "5G", "40M", "HT", "2T", "134", "46", - "MKK", "5G", "40M", "HT", "2T", "134", "46", - "FCC", "5G", "40M", "HT", "2T", "151", "46", - "ETSI", "5G", "40M", "HT", "2T", "151", "46", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "46", - "ETSI", "5G", "40M", "HT", "2T", "159", "46", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "46", - "ETSI", "5G", "40M", "HT", "3T", "38", "46", - "MKK", "5G", "40M", "HT", "3T", "38", "46", - "FCC", "5G", "40M", "HT", "3T", "46", "46", - "ETSI", "5G", "40M", "HT", "3T", "46", "46", - "MKK", "5G", "40M", "HT", "3T", "46", "46", - "FCC", "5G", "40M", "HT", "3T", "54", "46", - "ETSI", "5G", "40M", "HT", "3T", "54", "46", - "MKK", "5G", "40M", "HT", "3T", "54", "46", - "FCC", "5G", "40M", "HT", "3T", "62", "46", - "ETSI", "5G", "40M", "HT", "3T", "62", "46", - "MKK", "5G", "40M", "HT", "3T", "62", "46", - "FCC", "5G", "40M", "HT", "3T", "102", "46", - "ETSI", "5G", "40M", "HT", "3T", "102", "46", - "MKK", "5G", "40M", "HT", "3T", "102", "46", - "FCC", "5G", "40M", "HT", "3T", "110", "46", - "ETSI", "5G", "40M", "HT", "3T", "110", "46", - "MKK", "5G", "40M", "HT", "3T", "110", "46", - "FCC", "5G", "40M", "HT", "3T", "118", "46", - "ETSI", "5G", "40M", "HT", "3T", "118", "46", - "MKK", "5G", "40M", "HT", "3T", "118", "46", - "FCC", "5G", "40M", "HT", "3T", "126", "46", - "ETSI", "5G", "40M", "HT", "3T", "126", "46", - "MKK", "5G", "40M", "HT", "3T", "126", "46", - "FCC", "5G", "40M", "HT", "3T", "134", "46", - "ETSI", "5G", "40M", "HT", "3T", "134", "46", - "MKK", "5G", "40M", "HT", "3T", "134", "46", - "FCC", "5G", "40M", "HT", "3T", "151", "46", - "ETSI", "5G", "40M", "HT", "3T", "151", "46", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "46", - "ETSI", "5G", "40M", "HT", "3T", "159", "46", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "46", - "ETSI", "5G", "40M", "HT", "4T", "38", "46", - "MKK", "5G", "40M", "HT", "4T", "38", "46", - "FCC", "5G", "40M", "HT", "4T", "46", "46", - "ETSI", "5G", "40M", "HT", "4T", "46", "46", - "MKK", "5G", "40M", "HT", "4T", "46", "46", - "FCC", "5G", "40M", "HT", "4T", "54", "46", - "ETSI", "5G", "40M", "HT", "4T", "54", "46", - "MKK", "5G", "40M", "HT", "4T", "54", "46", - "FCC", "5G", "40M", "HT", "4T", "62", "46", - "ETSI", "5G", "40M", "HT", "4T", "62", "46", - "MKK", "5G", "40M", "HT", "4T", "62", "46", - "FCC", "5G", "40M", "HT", "4T", "102", "46", - "ETSI", "5G", "40M", "HT", "4T", "102", "46", - "MKK", "5G", "40M", "HT", "4T", "102", "46", - "FCC", "5G", "40M", "HT", "4T", "110", "46", - "ETSI", "5G", "40M", "HT", "4T", "110", "46", - "MKK", "5G", "40M", "HT", "4T", "110", "46", - "FCC", "5G", "40M", "HT", "4T", "118", "46", - "ETSI", "5G", "40M", "HT", "4T", "118", "46", - "MKK", "5G", "40M", "HT", "4T", "118", "46", - "FCC", "5G", "40M", "HT", "4T", "126", "46", - "ETSI", "5G", "40M", "HT", "4T", "126", "46", - "MKK", "5G", "40M", "HT", "4T", "126", "46", - "FCC", "5G", "40M", "HT", "4T", "134", "46", - "ETSI", "5G", "40M", "HT", "4T", "134", "46", - "MKK", "5G", "40M", "HT", "4T", "134", "46", - "FCC", "5G", "40M", "HT", "4T", "151", "46", - "ETSI", "5G", "40M", "HT", "4T", "151", "46", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "46", - "ETSI", "5G", "40M", "HT", "4T", "159", "46", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "46", - "ETSI", "5G", "80M", "VHT", "1T", "42", "46", - "MKK", "5G", "80M", "VHT", "1T", "42", "46", - "FCC", "5G", "80M", "VHT", "1T", "58", "46", - "ETSI", "5G", "80M", "VHT", "1T", "58", "46", - "MKK", "5G", "80M", "VHT", "1T", "58", "46", - "FCC", "5G", "80M", "VHT", "1T", "106", "46", - "ETSI", "5G", "80M", "VHT", "1T", "106", "46", - "MKK", "5G", "80M", "VHT", "1T", "106", "46", - "FCC", "5G", "80M", "VHT", "1T", "122", "46", - "ETSI", "5G", "80M", "VHT", "1T", "122", "46", - "MKK", "5G", "80M", "VHT", "1T", "122", "46", - "FCC", "5G", "80M", "VHT", "1T", "155", "46", - "ETSI", "5G", "80M", "VHT", "1T", "155", "46", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "46", - "ETSI", "5G", "80M", "VHT", "2T", "42", "46", - "MKK", "5G", "80M", "VHT", "2T", "42", "46", - "FCC", "5G", "80M", "VHT", "2T", "58", "46", - "ETSI", "5G", "80M", "VHT", "2T", "58", "46", - "MKK", "5G", "80M", "VHT", "2T", "58", "46", - "FCC", "5G", "80M", "VHT", "2T", "106", "46", - "ETSI", "5G", "80M", "VHT", "2T", "106", "46", - "MKK", "5G", "80M", "VHT", "2T", "106", "46", - "FCC", "5G", "80M", "VHT", "2T", "122", "46", - "ETSI", "5G", "80M", "VHT", "2T", "122", "46", - "MKK", "5G", "80M", "VHT", "2T", "122", "46", - "FCC", "5G", "80M", "VHT", "2T", "155", "46", - "ETSI", "5G", "80M", "VHT", "2T", "155", "46", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "46", - "ETSI", "5G", "80M", "VHT", "3T", "42", "46", - "MKK", "5G", "80M", "VHT", "3T", "42", "46", - "FCC", "5G", "80M", "VHT", "3T", "58", "46", - "ETSI", "5G", "80M", "VHT", "3T", "58", "46", - "MKK", "5G", "80M", "VHT", "3T", "58", "46", - "FCC", "5G", "80M", "VHT", "3T", "106", "46", - "ETSI", "5G", "80M", "VHT", "3T", "106", "46", - "MKK", "5G", "80M", "VHT", "3T", "106", "46", - "FCC", "5G", "80M", "VHT", "3T", "122", "46", - "ETSI", "5G", "80M", "VHT", "3T", "122", "46", - "MKK", "5G", "80M", "VHT", "3T", "122", "46", - "FCC", "5G", "80M", "VHT", "3T", "155", "46", - "ETSI", "5G", "80M", "VHT", "3T", "155", "46", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "46", - "ETSI", "5G", "80M", "VHT", "4T", "42", "46", - "MKK", "5G", "80M", "VHT", "4T", "42", "46", - "FCC", "5G", "80M", "VHT", "4T", "58", "46", - "ETSI", "5G", "80M", "VHT", "4T", "58", "46", - "MKK", "5G", "80M", "VHT", "4T", "58", "46", - "FCC", "5G", "80M", "VHT", "4T", "106", "46", - "ETSI", "5G", "80M", "VHT", "4T", "106", "46", - "MKK", "5G", "80M", "VHT", "4T", "106", "46", - "FCC", "5G", "80M", "VHT", "4T", "122", "46", - "ETSI", "5G", "80M", "VHT", "4T", "122", "46", - "MKK", "5G", "80M", "VHT", "4T", "122", "46", - "FCC", "5G", "80M", "VHT", "4T", "155", "46", - "ETSI", "5G", "80M", "VHT", "4T", "155", "46", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type8)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type8; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type8)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type8; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_Type9.TXT -******************************************************************************/ - -const char *Array_MP_8814A_TXPWR_LMT_Type9[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "40", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "40", - "FCC", "2.4G", "20M", "HT", "1T", "01", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", - "MKK", "2.4G", "20M", "HT", "1T", "01", "40", - "FCC", "2.4G", "20M", "HT", "1T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", - "MKK", "2.4G", "20M", "HT", "1T", "02", "40", - "FCC", "2.4G", "20M", "HT", "1T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", - "MKK", "2.4G", "20M", "HT", "1T", "03", "40", - "FCC", "2.4G", "20M", "HT", "1T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", - "MKK", "2.4G", "20M", "HT", "1T", "04", "40", - "FCC", "2.4G", "20M", "HT", "1T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "40", - "MKK", "2.4G", "20M", "HT", "1T", "05", "40", - "FCC", "2.4G", "20M", "HT", "1T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "40", - "MKK", "2.4G", "20M", "HT", "1T", "06", "40", - "FCC", "2.4G", "20M", "HT", "1T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "40", - "MKK", "2.4G", "20M", "HT", "1T", "07", "40", - "FCC", "2.4G", "20M", "HT", "1T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "40", - "MKK", "2.4G", "20M", "HT", "1T", "08", "40", - "FCC", "2.4G", "20M", "HT", "1T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "40", - "MKK", "2.4G", "20M", "HT", "1T", "09", "40", - "FCC", "2.4G", "20M", "HT", "1T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "40", - "MKK", "2.4G", "20M", "HT", "1T", "10", "40", - "FCC", "2.4G", "20M", "HT", "1T", "11", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "40", - "MKK", "2.4G", "20M", "HT", "1T", "11", "40", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "40", - "MKK", "2.4G", "20M", "HT", "1T", "12", "40", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "40", - "MKK", "2.4G", "20M", "HT", "1T", "13", "40", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "40", - "FCC", "2.4G", "20M", "HT", "2T", "01", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", - "MKK", "2.4G", "20M", "HT", "2T", "01", "40", - "FCC", "2.4G", "20M", "HT", "2T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", - "MKK", "2.4G", "20M", "HT", "2T", "02", "40", - "FCC", "2.4G", "20M", "HT", "2T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", - "MKK", "2.4G", "20M", "HT", "2T", "03", "40", - "FCC", "2.4G", "20M", "HT", "2T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", - "MKK", "2.4G", "20M", "HT", "2T", "04", "40", - "FCC", "2.4G", "20M", "HT", "2T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", - "MKK", "2.4G", "20M", "HT", "2T", "05", "40", - "FCC", "2.4G", "20M", "HT", "2T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", - "MKK", "2.4G", "20M", "HT", "2T", "06", "40", - "FCC", "2.4G", "20M", "HT", "2T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", - "MKK", "2.4G", "20M", "HT", "2T", "07", "40", - "FCC", "2.4G", "20M", "HT", "2T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", - "MKK", "2.4G", "20M", "HT", "2T", "08", "40", - "FCC", "2.4G", "20M", "HT", "2T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", - "MKK", "2.4G", "20M", "HT", "2T", "09", "40", - "FCC", "2.4G", "20M", "HT", "2T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", - "MKK", "2.4G", "20M", "HT", "2T", "10", "40", - "FCC", "2.4G", "20M", "HT", "2T", "11", "40", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", - "MKK", "2.4G", "20M", "HT", "2T", "11", "40", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", - "MKK", "2.4G", "20M", "HT", "2T", "12", "40", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", - "MKK", "2.4G", "20M", "HT", "2T", "13", "40", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "40", - "FCC", "2.4G", "20M", "HT", "3T", "01", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", - "MKK", "2.4G", "20M", "HT", "3T", "01", "40", - "FCC", "2.4G", "20M", "HT", "3T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", - "MKK", "2.4G", "20M", "HT", "3T", "02", "40", - "FCC", "2.4G", "20M", "HT", "3T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", - "MKK", "2.4G", "20M", "HT", "3T", "03", "40", - "FCC", "2.4G", "20M", "HT", "3T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", - "MKK", "2.4G", "20M", "HT", "3T", "04", "40", - "FCC", "2.4G", "20M", "HT", "3T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", - "MKK", "2.4G", "20M", "HT", "3T", "05", "40", - "FCC", "2.4G", "20M", "HT", "3T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", - "MKK", "2.4G", "20M", "HT", "3T", "06", "40", - "FCC", "2.4G", "20M", "HT", "3T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", - "MKK", "2.4G", "20M", "HT", "3T", "07", "40", - "FCC", "2.4G", "20M", "HT", "3T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", - "MKK", "2.4G", "20M", "HT", "3T", "08", "40", - "FCC", "2.4G", "20M", "HT", "3T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", - "MKK", "2.4G", "20M", "HT", "3T", "09", "40", - "FCC", "2.4G", "20M", "HT", "3T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", - "MKK", "2.4G", "20M", "HT", "3T", "10", "40", - "FCC", "2.4G", "20M", "HT", "3T", "11", "40", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", - "MKK", "2.4G", "20M", "HT", "3T", "11", "40", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", - "MKK", "2.4G", "20M", "HT", "3T", "12", "40", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", - "MKK", "2.4G", "20M", "HT", "3T", "13", "40", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "40", - "FCC", "2.4G", "20M", "HT", "4T", "01", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", - "MKK", "2.4G", "20M", "HT", "4T", "01", "40", - "FCC", "2.4G", "20M", "HT", "4T", "02", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", - "MKK", "2.4G", "20M", "HT", "4T", "02", "40", - "FCC", "2.4G", "20M", "HT", "4T", "03", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", - "MKK", "2.4G", "20M", "HT", "4T", "03", "40", - "FCC", "2.4G", "20M", "HT", "4T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", - "MKK", "2.4G", "20M", "HT", "4T", "04", "40", - "FCC", "2.4G", "20M", "HT", "4T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", - "MKK", "2.4G", "20M", "HT", "4T", "05", "40", - "FCC", "2.4G", "20M", "HT", "4T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", - "MKK", "2.4G", "20M", "HT", "4T", "06", "40", - "FCC", "2.4G", "20M", "HT", "4T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", - "MKK", "2.4G", "20M", "HT", "4T", "07", "40", - "FCC", "2.4G", "20M", "HT", "4T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", - "MKK", "2.4G", "20M", "HT", "4T", "08", "40", - "FCC", "2.4G", "20M", "HT", "4T", "09", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", - "MKK", "2.4G", "20M", "HT", "4T", "09", "40", - "FCC", "2.4G", "20M", "HT", "4T", "10", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", - "MKK", "2.4G", "20M", "HT", "4T", "10", "40", - "FCC", "2.4G", "20M", "HT", "4T", "11", "40", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", - "MKK", "2.4G", "20M", "HT", "4T", "11", "40", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", - "MKK", "2.4G", "20M", "HT", "4T", "12", "40", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", - "MKK", "2.4G", "20M", "HT", "4T", "13", "40", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "40", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", - "MKK", "2.4G", "40M", "HT", "1T", "12", "34", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", - "MKK", "2.4G", "40M", "HT", "1T", "13", "34", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "34", - "MKK", "2.4G", "40M", "HT", "2T", "03", "34", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "34", - "MKK", "2.4G", "40M", "HT", "2T", "04", "34", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "34", - "MKK", "2.4G", "40M", "HT", "2T", "05", "34", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "34", - "MKK", "2.4G", "40M", "HT", "2T", "06", "34", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", - "MKK", "2.4G", "40M", "HT", "2T", "07", "34", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", - "MKK", "2.4G", "40M", "HT", "2T", "08", "34", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", - "MKK", "2.4G", "40M", "HT", "2T", "09", "34", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", - "MKK", "2.4G", "40M", "HT", "2T", "10", "34", - "FCC", "2.4G", "40M", "HT", "2T", "11", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", - "MKK", "2.4G", "40M", "HT", "2T", "11", "34", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", - "MKK", "2.4G", "40M", "HT", "2T", "12", "34", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", - "MKK", "2.4G", "40M", "HT", "2T", "13", "34", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", - "MKK", "2.4G", "40M", "HT", "3T", "03", "34", - "FCC", "2.4G", "40M", "HT", "3T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", - "MKK", "2.4G", "40M", "HT", "3T", "04", "34", - "FCC", "2.4G", "40M", "HT", "3T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", - "MKK", "2.4G", "40M", "HT", "3T", "05", "34", - "FCC", "2.4G", "40M", "HT", "3T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", - "MKK", "2.4G", "40M", "HT", "3T", "06", "34", - "FCC", "2.4G", "40M", "HT", "3T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", - "MKK", "2.4G", "40M", "HT", "3T", "07", "34", - "FCC", "2.4G", "40M", "HT", "3T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", - "MKK", "2.4G", "40M", "HT", "3T", "08", "34", - "FCC", "2.4G", "40M", "HT", "3T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", - "MKK", "2.4G", "40M", "HT", "3T", "09", "34", - "FCC", "2.4G", "40M", "HT", "3T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", - "MKK", "2.4G", "40M", "HT", "3T", "10", "34", - "FCC", "2.4G", "40M", "HT", "3T", "11", "34", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", - "MKK", "2.4G", "40M", "HT", "3T", "11", "34", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", - "MKK", "2.4G", "40M", "HT", "3T", "12", "34", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", - "MKK", "2.4G", "40M", "HT", "3T", "13", "34", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", - "MKK", "2.4G", "40M", "HT", "4T", "03", "34", - "FCC", "2.4G", "40M", "HT", "4T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", - "MKK", "2.4G", "40M", "HT", "4T", "04", "34", - "FCC", "2.4G", "40M", "HT", "4T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", - "MKK", "2.4G", "40M", "HT", "4T", "05", "34", - "FCC", "2.4G", "40M", "HT", "4T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", - "MKK", "2.4G", "40M", "HT", "4T", "06", "34", - "FCC", "2.4G", "40M", "HT", "4T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", - "MKK", "2.4G", "40M", "HT", "4T", "07", "34", - "FCC", "2.4G", "40M", "HT", "4T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", - "MKK", "2.4G", "40M", "HT", "4T", "08", "34", - "FCC", "2.4G", "40M", "HT", "4T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", - "MKK", "2.4G", "40M", "HT", "4T", "09", "34", - "FCC", "2.4G", "40M", "HT", "4T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", - "MKK", "2.4G", "40M", "HT", "4T", "10", "34", - "FCC", "2.4G", "40M", "HT", "4T", "11", "34", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", - "MKK", "2.4G", "40M", "HT", "4T", "11", "34", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", - "MKK", "2.4G", "40M", "HT", "4T", "12", "34", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", - "MKK", "2.4G", "40M", "HT", "4T", "13", "34", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "44", - "MKK", "5G", "20M", "OFDM", "1T", "36", "44", - "FCC", "5G", "20M", "OFDM", "1T", "40", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "44", - "MKK", "5G", "20M", "OFDM", "1T", "40", "44", - "FCC", "5G", "20M", "OFDM", "1T", "44", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "44", - "MKK", "5G", "20M", "OFDM", "1T", "44", "44", - "FCC", "5G", "20M", "OFDM", "1T", "48", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "44", - "MKK", "5G", "20M", "OFDM", "1T", "48", "44", - "FCC", "5G", "20M", "OFDM", "1T", "52", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "44", - "MKK", "5G", "20M", "OFDM", "1T", "52", "44", - "FCC", "5G", "20M", "OFDM", "1T", "56", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "44", - "MKK", "5G", "20M", "OFDM", "1T", "56", "44", - "FCC", "5G", "20M", "OFDM", "1T", "60", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "44", - "MKK", "5G", "20M", "OFDM", "1T", "60", "44", - "FCC", "5G", "20M", "OFDM", "1T", "64", "40", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", - "MKK", "5G", "20M", "OFDM", "1T", "64", "40", - "FCC", "5G", "20M", "OFDM", "1T", "100", "40", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", - "MKK", "5G", "20M", "OFDM", "1T", "100", "40", - "FCC", "5G", "20M", "OFDM", "1T", "104", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "44", - "MKK", "5G", "20M", "OFDM", "1T", "104", "44", - "FCC", "5G", "20M", "OFDM", "1T", "108", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "44", - "MKK", "5G", "20M", "OFDM", "1T", "108", "44", - "FCC", "5G", "20M", "OFDM", "1T", "112", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "44", - "MKK", "5G", "20M", "OFDM", "1T", "112", "44", - "FCC", "5G", "20M", "OFDM", "1T", "116", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "44", - "MKK", "5G", "20M", "OFDM", "1T", "116", "44", - "FCC", "5G", "20M", "OFDM", "1T", "120", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "44", - "MKK", "5G", "20M", "OFDM", "1T", "120", "44", - "FCC", "5G", "20M", "OFDM", "1T", "124", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "44", - "MKK", "5G", "20M", "OFDM", "1T", "124", "44", - "FCC", "5G", "20M", "OFDM", "1T", "128", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "44", - "MKK", "5G", "20M", "OFDM", "1T", "128", "44", - "FCC", "5G", "20M", "OFDM", "1T", "132", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "44", - "MKK", "5G", "20M", "OFDM", "1T", "132", "44", - "FCC", "5G", "20M", "OFDM", "1T", "136", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "44", - "MKK", "5G", "20M", "OFDM", "1T", "136", "44", - "FCC", "5G", "20M", "OFDM", "1T", "140", "40", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", - "MKK", "5G", "20M", "OFDM", "1T", "140", "40", - "FCC", "5G", "20M", "OFDM", "1T", "149", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "42", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "44", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "42", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "42", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "40", - "ETSI", "5G", "20M", "HT", "1T", "36", "40", - "MKK", "5G", "20M", "HT", "1T", "36", "40", - "FCC", "5G", "20M", "HT", "1T", "40", "44", - "ETSI", "5G", "20M", "HT", "1T", "40", "44", - "MKK", "5G", "20M", "HT", "1T", "40", "44", - "FCC", "5G", "20M", "HT", "1T", "44", "44", - "ETSI", "5G", "20M", "HT", "1T", "44", "44", - "MKK", "5G", "20M", "HT", "1T", "44", "44", - "FCC", "5G", "20M", "HT", "1T", "48", "44", - "ETSI", "5G", "20M", "HT", "1T", "48", "44", - "MKK", "5G", "20M", "HT", "1T", "48", "44", - "FCC", "5G", "20M", "HT", "1T", "52", "44", - "ETSI", "5G", "20M", "HT", "1T", "52", "44", - "MKK", "5G", "20M", "HT", "1T", "52", "44", - "FCC", "5G", "20M", "HT", "1T", "56", "44", - "ETSI", "5G", "20M", "HT", "1T", "56", "44", - "MKK", "5G", "20M", "HT", "1T", "56", "44", - "FCC", "5G", "20M", "HT", "1T", "60", "44", - "ETSI", "5G", "20M", "HT", "1T", "60", "44", - "MKK", "5G", "20M", "HT", "1T", "60", "44", - "FCC", "5G", "20M", "HT", "1T", "64", "42", - "ETSI", "5G", "20M", "HT", "1T", "64", "42", - "MKK", "5G", "20M", "HT", "1T", "64", "42", - "FCC", "5G", "20M", "HT", "1T", "100", "40", - "ETSI", "5G", "20M", "HT", "1T", "100", "40", - "MKK", "5G", "20M", "HT", "1T", "100", "40", - "FCC", "5G", "20M", "HT", "1T", "104", "44", - "ETSI", "5G", "20M", "HT", "1T", "104", "44", - "MKK", "5G", "20M", "HT", "1T", "104", "44", - "FCC", "5G", "20M", "HT", "1T", "108", "44", - "ETSI", "5G", "20M", "HT", "1T", "108", "44", - "MKK", "5G", "20M", "HT", "1T", "108", "44", - "FCC", "5G", "20M", "HT", "1T", "112", "44", - "ETSI", "5G", "20M", "HT", "1T", "112", "44", - "MKK", "5G", "20M", "HT", "1T", "112", "44", - "FCC", "5G", "20M", "HT", "1T", "116", "44", - "ETSI", "5G", "20M", "HT", "1T", "116", "44", - "MKK", "5G", "20M", "HT", "1T", "116", "44", - "FCC", "5G", "20M", "HT", "1T", "120", "44", - "ETSI", "5G", "20M", "HT", "1T", "120", "44", - "MKK", "5G", "20M", "HT", "1T", "120", "44", - "FCC", "5G", "20M", "HT", "1T", "124", "44", - "ETSI", "5G", "20M", "HT", "1T", "124", "44", - "MKK", "5G", "20M", "HT", "1T", "124", "44", - "FCC", "5G", "20M", "HT", "1T", "128", "44", - "ETSI", "5G", "20M", "HT", "1T", "128", "44", - "MKK", "5G", "20M", "HT", "1T", "128", "44", - "FCC", "5G", "20M", "HT", "1T", "132", "44", - "ETSI", "5G", "20M", "HT", "1T", "132", "44", - "MKK", "5G", "20M", "HT", "1T", "132", "44", - "FCC", "5G", "20M", "HT", "1T", "136", "44", - "ETSI", "5G", "20M", "HT", "1T", "136", "44", - "MKK", "5G", "20M", "HT", "1T", "136", "44", - "FCC", "5G", "20M", "HT", "1T", "140", "40", - "ETSI", "5G", "20M", "HT", "1T", "140", "40", - "MKK", "5G", "20M", "HT", "1T", "140", "40", - "FCC", "5G", "20M", "HT", "1T", "149", "44", - "ETSI", "5G", "20M", "HT", "1T", "149", "44", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "44", - "ETSI", "5G", "20M", "HT", "1T", "153", "44", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "44", - "ETSI", "5G", "20M", "HT", "1T", "157", "44", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "44", - "ETSI", "5G", "20M", "HT", "1T", "161", "44", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "42", - "ETSI", "5G", "20M", "HT", "1T", "165", "42", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "40", - "ETSI", "5G", "20M", "HT", "2T", "36", "40", - "MKK", "5G", "20M", "HT", "2T", "36", "40", - "FCC", "5G", "20M", "HT", "2T", "40", "44", - "ETSI", "5G", "20M", "HT", "2T", "40", "44", - "MKK", "5G", "20M", "HT", "2T", "40", "44", - "FCC", "5G", "20M", "HT", "2T", "44", "44", - "ETSI", "5G", "20M", "HT", "2T", "44", "44", - "MKK", "5G", "20M", "HT", "2T", "44", "44", - "FCC", "5G", "20M", "HT", "2T", "48", "44", - "ETSI", "5G", "20M", "HT", "2T", "48", "44", - "MKK", "5G", "20M", "HT", "2T", "48", "44", - "FCC", "5G", "20M", "HT", "2T", "52", "44", - "ETSI", "5G", "20M", "HT", "2T", "52", "44", - "MKK", "5G", "20M", "HT", "2T", "52", "44", - "FCC", "5G", "20M", "HT", "2T", "56", "44", - "ETSI", "5G", "20M", "HT", "2T", "56", "44", - "MKK", "5G", "20M", "HT", "2T", "56", "44", - "FCC", "5G", "20M", "HT", "2T", "60", "44", - "ETSI", "5G", "20M", "HT", "2T", "60", "44", - "MKK", "5G", "20M", "HT", "2T", "60", "44", - "FCC", "5G", "20M", "HT", "2T", "64", "42", - "ETSI", "5G", "20M", "HT", "2T", "64", "42", - "MKK", "5G", "20M", "HT", "2T", "64", "42", - "FCC", "5G", "20M", "HT", "2T", "100", "40", - "ETSI", "5G", "20M", "HT", "2T", "100", "40", - "MKK", "5G", "20M", "HT", "2T", "100", "40", - "FCC", "5G", "20M", "HT", "2T", "104", "44", - "ETSI", "5G", "20M", "HT", "2T", "104", "44", - "MKK", "5G", "20M", "HT", "2T", "104", "44", - "FCC", "5G", "20M", "HT", "2T", "108", "44", - "ETSI", "5G", "20M", "HT", "2T", "108", "44", - "MKK", "5G", "20M", "HT", "2T", "108", "44", - "FCC", "5G", "20M", "HT", "2T", "112", "44", - "ETSI", "5G", "20M", "HT", "2T", "112", "44", - "MKK", "5G", "20M", "HT", "2T", "112", "44", - "FCC", "5G", "20M", "HT", "2T", "116", "44", - "ETSI", "5G", "20M", "HT", "2T", "116", "44", - "MKK", "5G", "20M", "HT", "2T", "116", "44", - "FCC", "5G", "20M", "HT", "2T", "120", "44", - "ETSI", "5G", "20M", "HT", "2T", "120", "44", - "MKK", "5G", "20M", "HT", "2T", "120", "44", - "FCC", "5G", "20M", "HT", "2T", "124", "44", - "ETSI", "5G", "20M", "HT", "2T", "124", "44", - "MKK", "5G", "20M", "HT", "2T", "124", "44", - "FCC", "5G", "20M", "HT", "2T", "128", "44", - "ETSI", "5G", "20M", "HT", "2T", "128", "44", - "MKK", "5G", "20M", "HT", "2T", "128", "44", - "FCC", "5G", "20M", "HT", "2T", "132", "44", - "ETSI", "5G", "20M", "HT", "2T", "132", "44", - "MKK", "5G", "20M", "HT", "2T", "132", "44", - "FCC", "5G", "20M", "HT", "2T", "136", "44", - "ETSI", "5G", "20M", "HT", "2T", "136", "44", - "MKK", "5G", "20M", "HT", "2T", "136", "44", - "FCC", "5G", "20M", "HT", "2T", "140", "40", - "ETSI", "5G", "20M", "HT", "2T", "140", "40", - "MKK", "5G", "20M", "HT", "2T", "140", "40", - "FCC", "5G", "20M", "HT", "2T", "149", "44", - "ETSI", "5G", "20M", "HT", "2T", "149", "44", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "44", - "ETSI", "5G", "20M", "HT", "2T", "153", "44", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "44", - "ETSI", "5G", "20M", "HT", "2T", "157", "44", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "44", - "ETSI", "5G", "20M", "HT", "2T", "161", "44", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "42", - "ETSI", "5G", "20M", "HT", "2T", "165", "42", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "40", - "ETSI", "5G", "20M", "HT", "3T", "36", "40", - "MKK", "5G", "20M", "HT", "3T", "36", "40", - "FCC", "5G", "20M", "HT", "3T", "40", "44", - "ETSI", "5G", "20M", "HT", "3T", "40", "44", - "MKK", "5G", "20M", "HT", "3T", "40", "44", - "FCC", "5G", "20M", "HT", "3T", "44", "44", - "ETSI", "5G", "20M", "HT", "3T", "44", "44", - "MKK", "5G", "20M", "HT", "3T", "44", "44", - "FCC", "5G", "20M", "HT", "3T", "48", "44", - "ETSI", "5G", "20M", "HT", "3T", "48", "44", - "MKK", "5G", "20M", "HT", "3T", "48", "44", - "FCC", "5G", "20M", "HT", "3T", "52", "44", - "ETSI", "5G", "20M", "HT", "3T", "52", "44", - "MKK", "5G", "20M", "HT", "3T", "52", "44", - "FCC", "5G", "20M", "HT", "3T", "56", "44", - "ETSI", "5G", "20M", "HT", "3T", "56", "44", - "MKK", "5G", "20M", "HT", "3T", "56", "44", - "FCC", "5G", "20M", "HT", "3T", "60", "44", - "ETSI", "5G", "20M", "HT", "3T", "60", "44", - "MKK", "5G", "20M", "HT", "3T", "60", "44", - "FCC", "5G", "20M", "HT", "3T", "64", "42", - "ETSI", "5G", "20M", "HT", "3T", "64", "42", - "MKK", "5G", "20M", "HT", "3T", "64", "42", - "FCC", "5G", "20M", "HT", "3T", "100", "40", - "ETSI", "5G", "20M", "HT", "3T", "100", "40", - "MKK", "5G", "20M", "HT", "3T", "100", "40", - "FCC", "5G", "20M", "HT", "3T", "104", "44", - "ETSI", "5G", "20M", "HT", "3T", "104", "44", - "MKK", "5G", "20M", "HT", "3T", "104", "44", - "FCC", "5G", "20M", "HT", "3T", "108", "44", - "ETSI", "5G", "20M", "HT", "3T", "108", "44", - "MKK", "5G", "20M", "HT", "3T", "108", "44", - "FCC", "5G", "20M", "HT", "3T", "112", "44", - "ETSI", "5G", "20M", "HT", "3T", "112", "44", - "MKK", "5G", "20M", "HT", "3T", "112", "44", - "FCC", "5G", "20M", "HT", "3T", "116", "44", - "ETSI", "5G", "20M", "HT", "3T", "116", "44", - "MKK", "5G", "20M", "HT", "3T", "116", "44", - "FCC", "5G", "20M", "HT", "3T", "120", "44", - "ETSI", "5G", "20M", "HT", "3T", "120", "44", - "MKK", "5G", "20M", "HT", "3T", "120", "44", - "FCC", "5G", "20M", "HT", "3T", "124", "44", - "ETSI", "5G", "20M", "HT", "3T", "124", "44", - "MKK", "5G", "20M", "HT", "3T", "124", "44", - "FCC", "5G", "20M", "HT", "3T", "128", "44", - "ETSI", "5G", "20M", "HT", "3T", "128", "44", - "MKK", "5G", "20M", "HT", "3T", "128", "44", - "FCC", "5G", "20M", "HT", "3T", "132", "44", - "ETSI", "5G", "20M", "HT", "3T", "132", "44", - "MKK", "5G", "20M", "HT", "3T", "132", "44", - "FCC", "5G", "20M", "HT", "3T", "136", "44", - "ETSI", "5G", "20M", "HT", "3T", "136", "44", - "MKK", "5G", "20M", "HT", "3T", "136", "44", - "FCC", "5G", "20M", "HT", "3T", "140", "40", - "ETSI", "5G", "20M", "HT", "3T", "140", "40", - "MKK", "5G", "20M", "HT", "3T", "140", "40", - "FCC", "5G", "20M", "HT", "3T", "149", "44", - "ETSI", "5G", "20M", "HT", "3T", "149", "44", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "44", - "ETSI", "5G", "20M", "HT", "3T", "153", "44", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "44", - "ETSI", "5G", "20M", "HT", "3T", "157", "44", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "44", - "ETSI", "5G", "20M", "HT", "3T", "161", "44", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "42", - "ETSI", "5G", "20M", "HT", "3T", "165", "42", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "40", - "ETSI", "5G", "20M", "HT", "4T", "36", "40", - "MKK", "5G", "20M", "HT", "4T", "36", "40", - "FCC", "5G", "20M", "HT", "4T", "40", "44", - "ETSI", "5G", "20M", "HT", "4T", "40", "44", - "MKK", "5G", "20M", "HT", "4T", "40", "44", - "FCC", "5G", "20M", "HT", "4T", "44", "44", - "ETSI", "5G", "20M", "HT", "4T", "44", "44", - "MKK", "5G", "20M", "HT", "4T", "44", "44", - "FCC", "5G", "20M", "HT", "4T", "48", "44", - "ETSI", "5G", "20M", "HT", "4T", "48", "44", - "MKK", "5G", "20M", "HT", "4T", "48", "44", - "FCC", "5G", "20M", "HT", "4T", "52", "44", - "ETSI", "5G", "20M", "HT", "4T", "52", "44", - "MKK", "5G", "20M", "HT", "4T", "52", "44", - "FCC", "5G", "20M", "HT", "4T", "56", "44", - "ETSI", "5G", "20M", "HT", "4T", "56", "44", - "MKK", "5G", "20M", "HT", "4T", "56", "44", - "FCC", "5G", "20M", "HT", "4T", "60", "44", - "ETSI", "5G", "20M", "HT", "4T", "60", "44", - "MKK", "5G", "20M", "HT", "4T", "60", "44", - "FCC", "5G", "20M", "HT", "4T", "64", "42", - "ETSI", "5G", "20M", "HT", "4T", "64", "42", - "MKK", "5G", "20M", "HT", "4T", "64", "42", - "FCC", "5G", "20M", "HT", "4T", "100", "40", - "ETSI", "5G", "20M", "HT", "4T", "100", "40", - "MKK", "5G", "20M", "HT", "4T", "100", "40", - "FCC", "5G", "20M", "HT", "4T", "104", "44", - "ETSI", "5G", "20M", "HT", "4T", "104", "44", - "MKK", "5G", "20M", "HT", "4T", "104", "44", - "FCC", "5G", "20M", "HT", "4T", "108", "44", - "ETSI", "5G", "20M", "HT", "4T", "108", "44", - "MKK", "5G", "20M", "HT", "4T", "108", "44", - "FCC", "5G", "20M", "HT", "4T", "112", "44", - "ETSI", "5G", "20M", "HT", "4T", "112", "44", - "MKK", "5G", "20M", "HT", "4T", "112", "44", - "FCC", "5G", "20M", "HT", "4T", "116", "44", - "ETSI", "5G", "20M", "HT", "4T", "116", "44", - "MKK", "5G", "20M", "HT", "4T", "116", "44", - "FCC", "5G", "20M", "HT", "4T", "120", "44", - "ETSI", "5G", "20M", "HT", "4T", "120", "44", - "MKK", "5G", "20M", "HT", "4T", "120", "44", - "FCC", "5G", "20M", "HT", "4T", "124", "44", - "ETSI", "5G", "20M", "HT", "4T", "124", "44", - "MKK", "5G", "20M", "HT", "4T", "124", "44", - "FCC", "5G", "20M", "HT", "4T", "128", "44", - "ETSI", "5G", "20M", "HT", "4T", "128", "44", - "MKK", "5G", "20M", "HT", "4T", "128", "44", - "FCC", "5G", "20M", "HT", "4T", "132", "44", - "ETSI", "5G", "20M", "HT", "4T", "132", "44", - "MKK", "5G", "20M", "HT", "4T", "132", "44", - "FCC", "5G", "20M", "HT", "4T", "136", "44", - "ETSI", "5G", "20M", "HT", "4T", "136", "44", - "MKK", "5G", "20M", "HT", "4T", "136", "44", - "FCC", "5G", "20M", "HT", "4T", "140", "40", - "ETSI", "5G", "20M", "HT", "4T", "140", "40", - "MKK", "5G", "20M", "HT", "4T", "140", "40", - "FCC", "5G", "20M", "HT", "4T", "149", "44", - "ETSI", "5G", "20M", "HT", "4T", "149", "44", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "44", - "ETSI", "5G", "20M", "HT", "4T", "153", "44", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "44", - "ETSI", "5G", "20M", "HT", "4T", "157", "44", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "44", - "ETSI", "5G", "20M", "HT", "4T", "161", "44", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "42", - "ETSI", "5G", "20M", "HT", "4T", "165", "42", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "34", - "ETSI", "5G", "40M", "HT", "1T", "38", "34", - "MKK", "5G", "40M", "HT", "1T", "38", "34", - "FCC", "5G", "40M", "HT", "1T", "46", "44", - "ETSI", "5G", "40M", "HT", "1T", "46", "44", - "MKK", "5G", "40M", "HT", "1T", "46", "44", - "FCC", "5G", "40M", "HT", "1T", "54", "44", - "ETSI", "5G", "40M", "HT", "1T", "54", "44", - "MKK", "5G", "40M", "HT", "1T", "54", "44", - "FCC", "5G", "40M", "HT", "1T", "62", "34", - "ETSI", "5G", "40M", "HT", "1T", "62", "34", - "MKK", "5G", "40M", "HT", "1T", "62", "34", - "FCC", "5G", "40M", "HT", "1T", "102", "34", - "ETSI", "5G", "40M", "HT", "1T", "102", "34", - "MKK", "5G", "40M", "HT", "1T", "102", "34", - "FCC", "5G", "40M", "HT", "1T", "110", "44", - "ETSI", "5G", "40M", "HT", "1T", "110", "44", - "MKK", "5G", "40M", "HT", "1T", "110", "44", - "FCC", "5G", "40M", "HT", "1T", "118", "44", - "ETSI", "5G", "40M", "HT", "1T", "118", "44", - "MKK", "5G", "40M", "HT", "1T", "118", "44", - "FCC", "5G", "40M", "HT", "1T", "126", "44", - "ETSI", "5G", "40M", "HT", "1T", "126", "44", - "MKK", "5G", "40M", "HT", "1T", "126", "44", - "FCC", "5G", "40M", "HT", "1T", "134", "42", - "ETSI", "5G", "40M", "HT", "1T", "134", "42", - "MKK", "5G", "40M", "HT", "1T", "134", "42", - "FCC", "5G", "40M", "HT", "1T", "151", "42", - "ETSI", "5G", "40M", "HT", "1T", "151", "42", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "42", - "ETSI", "5G", "40M", "HT", "1T", "159", "42", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "34", - "ETSI", "5G", "40M", "HT", "2T", "38", "34", - "MKK", "5G", "40M", "HT", "2T", "38", "34", - "FCC", "5G", "40M", "HT", "2T", "46", "44", - "ETSI", "5G", "40M", "HT", "2T", "46", "44", - "MKK", "5G", "40M", "HT", "2T", "46", "44", - "FCC", "5G", "40M", "HT", "2T", "54", "44", - "ETSI", "5G", "40M", "HT", "2T", "54", "44", - "MKK", "5G", "40M", "HT", "2T", "54", "44", - "FCC", "5G", "40M", "HT", "2T", "62", "34", - "ETSI", "5G", "40M", "HT", "2T", "62", "34", - "MKK", "5G", "40M", "HT", "2T", "62", "34", - "FCC", "5G", "40M", "HT", "2T", "102", "34", - "ETSI", "5G", "40M", "HT", "2T", "102", "34", - "MKK", "5G", "40M", "HT", "2T", "102", "34", - "FCC", "5G", "40M", "HT", "2T", "110", "44", - "ETSI", "5G", "40M", "HT", "2T", "110", "44", - "MKK", "5G", "40M", "HT", "2T", "110", "44", - "FCC", "5G", "40M", "HT", "2T", "118", "44", - "ETSI", "5G", "40M", "HT", "2T", "118", "44", - "MKK", "5G", "40M", "HT", "2T", "118", "44", - "FCC", "5G", "40M", "HT", "2T", "126", "44", - "ETSI", "5G", "40M", "HT", "2T", "126", "44", - "MKK", "5G", "40M", "HT", "2T", "126", "44", - "FCC", "5G", "40M", "HT", "2T", "134", "42", - "ETSI", "5G", "40M", "HT", "2T", "134", "42", - "MKK", "5G", "40M", "HT", "2T", "134", "42", - "FCC", "5G", "40M", "HT", "2T", "151", "42", - "ETSI", "5G", "40M", "HT", "2T", "151", "42", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "42", - "ETSI", "5G", "40M", "HT", "2T", "159", "42", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "34", - "ETSI", "5G", "40M", "HT", "3T", "38", "34", - "MKK", "5G", "40M", "HT", "3T", "38", "34", - "FCC", "5G", "40M", "HT", "3T", "46", "44", - "ETSI", "5G", "40M", "HT", "3T", "46", "44", - "MKK", "5G", "40M", "HT", "3T", "46", "44", - "FCC", "5G", "40M", "HT", "3T", "54", "44", - "ETSI", "5G", "40M", "HT", "3T", "54", "44", - "MKK", "5G", "40M", "HT", "3T", "54", "44", - "FCC", "5G", "40M", "HT", "3T", "62", "34", - "ETSI", "5G", "40M", "HT", "3T", "62", "34", - "MKK", "5G", "40M", "HT", "3T", "62", "34", - "FCC", "5G", "40M", "HT", "3T", "102", "34", - "ETSI", "5G", "40M", "HT", "3T", "102", "34", - "MKK", "5G", "40M", "HT", "3T", "102", "34", - "FCC", "5G", "40M", "HT", "3T", "110", "44", - "ETSI", "5G", "40M", "HT", "3T", "110", "44", - "MKK", "5G", "40M", "HT", "3T", "110", "44", - "FCC", "5G", "40M", "HT", "3T", "118", "44", - "ETSI", "5G", "40M", "HT", "3T", "118", "44", - "MKK", "5G", "40M", "HT", "3T", "118", "44", - "FCC", "5G", "40M", "HT", "3T", "126", "44", - "ETSI", "5G", "40M", "HT", "3T", "126", "44", - "MKK", "5G", "40M", "HT", "3T", "126", "44", - "FCC", "5G", "40M", "HT", "3T", "134", "42", - "ETSI", "5G", "40M", "HT", "3T", "134", "42", - "MKK", "5G", "40M", "HT", "3T", "134", "42", - "FCC", "5G", "40M", "HT", "3T", "151", "42", - "ETSI", "5G", "40M", "HT", "3T", "151", "42", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "42", - "ETSI", "5G", "40M", "HT", "3T", "159", "42", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "34", - "ETSI", "5G", "40M", "HT", "4T", "38", "34", - "MKK", "5G", "40M", "HT", "4T", "38", "34", - "FCC", "5G", "40M", "HT", "4T", "46", "44", - "ETSI", "5G", "40M", "HT", "4T", "46", "44", - "MKK", "5G", "40M", "HT", "4T", "46", "44", - "FCC", "5G", "40M", "HT", "4T", "54", "44", - "ETSI", "5G", "40M", "HT", "4T", "54", "44", - "MKK", "5G", "40M", "HT", "4T", "54", "44", - "FCC", "5G", "40M", "HT", "4T", "62", "34", - "ETSI", "5G", "40M", "HT", "4T", "62", "34", - "MKK", "5G", "40M", "HT", "4T", "62", "34", - "FCC", "5G", "40M", "HT", "4T", "102", "34", - "ETSI", "5G", "40M", "HT", "4T", "102", "34", - "MKK", "5G", "40M", "HT", "4T", "102", "34", - "FCC", "5G", "40M", "HT", "4T", "110", "44", - "ETSI", "5G", "40M", "HT", "4T", "110", "44", - "MKK", "5G", "40M", "HT", "4T", "110", "44", - "FCC", "5G", "40M", "HT", "4T", "118", "44", - "ETSI", "5G", "40M", "HT", "4T", "118", "44", - "MKK", "5G", "40M", "HT", "4T", "118", "44", - "FCC", "5G", "40M", "HT", "4T", "126", "44", - "ETSI", "5G", "40M", "HT", "4T", "126", "44", - "MKK", "5G", "40M", "HT", "4T", "126", "44", - "FCC", "5G", "40M", "HT", "4T", "134", "42", - "ETSI", "5G", "40M", "HT", "4T", "134", "42", - "MKK", "5G", "40M", "HT", "4T", "134", "42", - "FCC", "5G", "40M", "HT", "4T", "151", "42", - "ETSI", "5G", "40M", "HT", "4T", "151", "42", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "42", - "ETSI", "5G", "40M", "HT", "4T", "159", "42", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "28", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "44", - "ETSI", "5G", "80M", "VHT", "1T", "122", "44", - "MKK", "5G", "80M", "VHT", "1T", "122", "44", - "FCC", "5G", "80M", "VHT", "1T", "155", "40", - "ETSI", "5G", "80M", "VHT", "1T", "155", "40", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "30", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "28", - "ETSI", "5G", "80M", "VHT", "2T", "58", "28", - "MKK", "5G", "80M", "VHT", "2T", "58", "28", - "FCC", "5G", "80M", "VHT", "2T", "106", "30", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "44", - "ETSI", "5G", "80M", "VHT", "2T", "122", "44", - "MKK", "5G", "80M", "VHT", "2T", "122", "44", - "FCC", "5G", "80M", "VHT", "2T", "155", "40", - "ETSI", "5G", "80M", "VHT", "2T", "155", "40", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "30", - "ETSI", "5G", "80M", "VHT", "3T", "42", "30", - "MKK", "5G", "80M", "VHT", "3T", "42", "30", - "FCC", "5G", "80M", "VHT", "3T", "58", "28", - "ETSI", "5G", "80M", "VHT", "3T", "58", "28", - "MKK", "5G", "80M", "VHT", "3T", "58", "28", - "FCC", "5G", "80M", "VHT", "3T", "106", "30", - "ETSI", "5G", "80M", "VHT", "3T", "106", "30", - "MKK", "5G", "80M", "VHT", "3T", "106", "30", - "FCC", "5G", "80M", "VHT", "3T", "122", "44", - "ETSI", "5G", "80M", "VHT", "3T", "122", "44", - "MKK", "5G", "80M", "VHT", "3T", "122", "44", - "FCC", "5G", "80M", "VHT", "3T", "155", "40", - "ETSI", "5G", "80M", "VHT", "3T", "155", "40", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "30", - "ETSI", "5G", "80M", "VHT", "4T", "42", "30", - "MKK", "5G", "80M", "VHT", "4T", "42", "30", - "FCC", "5G", "80M", "VHT", "4T", "58", "28", - "ETSI", "5G", "80M", "VHT", "4T", "58", "28", - "MKK", "5G", "80M", "VHT", "4T", "58", "28", - "FCC", "5G", "80M", "VHT", "4T", "106", "30", - "ETSI", "5G", "80M", "VHT", "4T", "106", "30", - "MKK", "5G", "80M", "VHT", "4T", "106", "30", - "FCC", "5G", "80M", "VHT", "4T", "122", "44", - "ETSI", "5G", "80M", "VHT", "4T", "122", "44", - "MKK", "5G", "80M", "VHT", "4T", "122", "44", - "FCC", "5G", "80M", "VHT", "4T", "155", "40", - "ETSI", "5G", "80M", "VHT", "4T", "155", "40", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type9)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type9; -#else - u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type9)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type9; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_RadioA[] = { + 0x018, 0x00013124, + 0x040, 0x00000C00, + 0x058, 0x00000F98, + 0x07F, 0x00068004, + 0x0B0, 0x000FFFFE, + 0x0B1, 0x0003FF48, + 0x0B2, 0x0006AA3F, + 0x0B3, 0x000FFC9A, + 0x0B4, 0x0000A78F, + 0x0B5, 0x00000A3F, + 0x0B6, 0x0000C09C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0B7, 0x00030008, + 0xA0000000, 0x00000000, + 0x0B7, 0x0003000C, + 0xB0000000, 0x00000000, + 0x0B8, 0x0007400E, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0xA0000000, 0x00000000, + 0x0B9, 0x000FBF50, + 0xB0000000, 0x00000000, + 0x0BA, 0x00050780, + 0x0BB, 0x00000000, + 0x0BC, 0x00040009, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0EF, 0x00020000, + 0x03E, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0xA0000000, 0x00000000, + 0x03F, 0x00030000, + 0xB0000000, 0x00000000, + 0x03E, 0x00020000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00040000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00040000, + 0xA0000000, 0x00000000, + 0x03F, 0x00040000, + 0xB0000000, 0x00000000, + 0x03E, 0x00040000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0xA0000000, 0x00000000, + 0x03F, 0x00030000, + 0xB0000000, 0x00000000, + 0x03E, 0x00060000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00030000, + 0xA0000000, 0x00000000, + 0x03F, 0x00030000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00010000, + 0x03E, 0x00000000, + 0x03F, 0x00006800, + 0x03E, 0x00000080, + 0x03F, 0x00006000, + 0x03E, 0x00000100, + 0x03F, 0x00004800, + 0x03E, 0x00000180, + 0x03F, 0x00004000, + 0x03E, 0x00000200, + 0x03F, 0x00004000, + 0x03E, 0x00000280, + 0x03F, 0x00002800, + 0x03E, 0x00000300, + 0x03F, 0x00002800, + 0x03E, 0x00000380, + 0x03F, 0x00002000, + 0x0EF, 0x00000000, + 0x0EF, 0x00040000, + 0x03E, 0x00000000, + 0x03F, 0x000000BC, + 0x03E, 0x00000040, + 0x03F, 0x00000053, + 0x03E, 0x00000050, + 0x03F, 0x00000050, + 0x03E, 0x00000060, + 0x03F, 0x00000050, + 0x0EF, 0x00000000, + 0x0EF, 0x00000400, + 0x03E, 0x00000006, + 0x041, 0x000EE080, + 0x03E, 0x00000008, + 0x041, 0x000EE0C0, + 0x03E, 0x0000000A, + 0x041, 0x000EE100, + 0x03E, 0x0000000C, + 0x041, 0x000EE100, + 0x0EF, 0x00000000, + 0x018, 0x00000006, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0xA0000000, 0x00000000, + 0x086, 0x000E4B58, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000008, + 0x0EF, 0x00002000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x000179C3, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x000179C3, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x000179C3, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x000179C3, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x000179C3, + 0xA0000000, 0x00000000, + 0x03B, 0x0003F258, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF6, + 0x034, 0x00009DF3, + 0x034, 0x00008DF0, + 0x034, 0x00007DED, + 0x034, 0x00006DEA, + 0x034, 0x00005CED, + 0x034, 0x00004CEA, + 0x034, 0x000034EA, + 0x034, 0x000024E7, + 0x034, 0x0000146A, + 0x034, 0x0000006B, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0008ADF6, + 0x034, 0x00089DF3, + 0x034, 0x00088DF0, + 0x034, 0x00087DED, + 0x034, 0x00086DEA, + 0x034, 0x00085CED, + 0x034, 0x00084CEA, + 0x034, 0x000834EA, + 0x034, 0x000824E7, + 0x034, 0x0008146A, + 0x034, 0x0008006B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x018, 0x0001012A, + 0x081, 0x0007FC00, + 0x089, 0x00050110, + 0x08A, 0x00043E50, + 0x08B, 0x0002E180, + 0x08C, 0x00093C3C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0xA0000000, 0x00000000, + 0x085, 0x000F8000, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xA0000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xB0000000, 0x00000000, + 0x0EF, 0x00001000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x00028000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00030023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00028623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00021633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0001C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00010293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00009593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0000118B, + 0xA0000000, 0x00000000, + 0x03B, 0x0000078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000AC000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00040000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x0004C000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00070023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00068623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00061633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0005C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00050293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00049593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0004138B, + 0xA0000000, 0x00000000, + 0x03B, 0x0004078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0008C000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0xA0000000, 0x00000000, + 0x03C, 0x00004000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B0023, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A8623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A1633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0009C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00090293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00089593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0008118B, + 0xA0000000, 0x00000000, + 0x03B, 0x0008078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000800, 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0x0008302C, + 0x034, 0x00082029, + 0x034, 0x0008100C, + 0x034, 0x00080009, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 0x000893AC, + 0x034, 0x0008838A, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 0x000893AC, + 0x034, 0x0008838A, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 0x000893AC, + 0x034, 0x0008838A, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 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0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0xA0000000, 0x00000000, + 0x035, 0x00000747, + 0x035, 0x00008747, + 0x035, 0x00010747, + 0x035, 0x00020747, + 0x035, 0x00028747, + 0x035, 0x00030747, + 0x035, 0x00040747, + 0x035, 0x00048747, + 0x035, 0x00050747, + 0x035, 0x000805FB, + 0x035, 0x000885FB, + 0x035, 0x000905FB, + 0x035, 0x000A05FB, + 0x035, 0x000A85FB, + 0x035, 0x000B05FB, + 0x035, 0x000C05FB, + 0x035, 0x000C85FB, + 0x035, 0x000D05FB, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0DF, 0x00000001, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000473, + 0x036, 0x00008473, + 0x036, 0x00010473, + 0x036, 0x00020473, + 0x036, 0x00028473, + 0x036, 0x00030473, + 0x036, 0x00040473, + 0x036, 0x00048473, + 0x036, 0x00050473, + 0x036, 0x00080473, + 0x036, 0x00088473, + 0x036, 0x00090473, + 0x036, 0x000A0473, + 0x036, 0x000A8473, + 0x036, 0x000B0473, + 0x036, 0x000C0473, + 0x036, 0x000C8473, + 0x036, 0x000D0473, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0xA0000000, 0x00000000, + 0x036, 0x00000473, + 0x036, 0x00008473, + 0x036, 0x00010473, + 0x036, 0x00020473, + 0x036, 0x00028473, + 0x036, 0x00030473, + 0x036, 0x00040473, + 0x036, 0x00048473, + 0x036, 0x00050473, + 0x036, 0x00080473, + 0x036, 0x00088473, + 0x036, 0x00090473, + 0x036, 0x000A0473, + 0x036, 0x000A8473, + 0x036, 0x000B0473, + 0x036, 0x000C0473, + 0x036, 0x000C8473, + 0x036, 0x000D0473, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000004, + 0x037, 0x00000000, + 0x038, 0x00005146, + 0x037, 0x00004000, + 0x038, 0x00005146, + 0x037, 0x00008000, + 0x038, 0x00005146, + 0x037, 0x00010000, + 0x038, 0x00005146, + 0x037, 0x00014000, + 0x038, 0x00005146, + 0x037, 0x00018000, + 0x038, 0x00004D4E, + 0x037, 0x0001C000, + 0x038, 0x00004D4E, + 0x037, 0x00020000, + 0x038, 0x00004D4E, + 0x037, 0x00024000, + 0x038, 0x000071C6, + 0x037, 0x00028000, + 0x038, 0x000071C6, + 0x037, 0x0002C000, + 0x038, 0x000071C6, + 0x037, 0x00030000, + 0x038, 0x000071CE, + 0x037, 0x00034000, + 0x038, 0x000071CE, + 0x037, 0x00038000, + 0x038, 0x00005126, + 0x037, 0x0003C000, + 0x038, 0x00005126, + 0x037, 0x00040000, + 0x038, 0x00005126, + 0x037, 0x00044000, + 0x038, 0x00005126, + 0x037, 0x00048000, + 0x038, 0x00005126, + 0x037, 0x00080000, + 0x038, 0x00005ECE, + 0x037, 0x00084000, + 0x038, 0x00005ECE, + 0x037, 0x00088000, + 0x038, 0x00005ECE, + 0x037, 0x00090000, + 0x038, 0x00005ECE, + 0x037, 0x00094000, + 0x038, 0x00005ECE, + 0x037, 0x00098000, + 0x038, 0x00005ECE, + 0x037, 0x0009C000, + 0x038, 0x00005ECE, + 0x037, 0x000A0000, + 0x038, 0x00005ECE, + 0x037, 0x000A4000, + 0x038, 0x00005ECE, + 0x037, 0x000A8000, + 0x038, 0x00005ECE, + 0x037, 0x000AC000, + 0x038, 0x00005ECE, + 0x037, 0x000B0000, + 0x038, 0x00005ECE, + 0x037, 0x000B4000, + 0x038, 0x00005ECE, + 0x037, 0x000B8000, + 0x038, 0x00005ECE, + 0x037, 0x000BC000, + 0x038, 0x00005ECE, + 0x037, 0x000C0000, + 0x038, 0x00005ECE, + 0x037, 0x000C4000, + 0x038, 0x00005ECE, + 0x037, 0x000C8000, + 0x038, 0x00005ECE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000008, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x0000007D, + 0x03C, 0x0000047D, + 0x03C, 0x0000087D, + 0x03C, 0x0000107D, + 0x03C, 0x0000147D, + 0x03C, 0x0000187D, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x0000054A, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x0000154A, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x0000254A, + 0x03C, 0x00002821, + 0xA0000000, 0x00000000, + 0x03C, 0x0000037E, + 0x03C, 0x00000575, + 0x03C, 0x00000971, + 0x03C, 0x0000127E, + 0x03C, 0x00001575, + 0x03C, 0x00001871, + 0x03C, 0x0000217E, + 0x03C, 0x00002575, + 0x03C, 0x00002871, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x061, 0x000C0D47, + 0x062, 0x0000133C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0xA0000000, 0x00000000, + 0x063, 0x0007D0E7, + 0xB0000000, 0x00000000, + 0x064, 0x00014FEC, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0xA0000000, 0x00000000, + 0x065, 0x000933FF, + 0xB0000000, 0x00000000, + 0x066, 0x00000040, + 0x057, 0x00050000, + 0x056, 0x00051DF0, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x055, 0x00082061, + 0xA0000000, 0x00000000, + 0x055, 0x00082060, + 0xB0000000, 0x00000000, + 0x01C, 0x000739D2, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x01F, 0x0002255C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x01F, 0x0002255C, + 0xA0000000, 0x00000000, + 0x01F, 0x0002255C, + 0xB0000000, 0x00000000, + 0x0B1, 0x0007FF48, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0C4, 0x00081700, + 0xA0000000, 0x00000000, + 0x0C4, 0x00083F00, + 0xB0000000, 0x00000000, + 0x018, 0x0001B126, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x018, 0x00013126, + 0x018, 0x00013124, + +}; + +void +ODM_ReadAndConfig_MP_8814A_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8814A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_RadioA(void) +{ + return 107; +} + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_RadioB[] = { + 0x018, 0x00013124, + 0x040, 0x00000C00, + 0x058, 0x00000F98, + 0x07F, 0x00068004, + 0x018, 0x00000006, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0xA0000000, 0x00000000, + 0x086, 0x000E4B58, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000008, + 0x0EF, 0x00002000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017BC3, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F39B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017BC3, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017BC3, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F39B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017BC3, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017BC3, + 0xA0000000, 0x00000000, + 0x03B, 0x0003F258, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF6, + 0x034, 0x00009DF3, + 0x034, 0x00008DF0, + 0x034, 0x00007DED, + 0x034, 0x00006DEA, + 0x034, 0x00005CED, + 0x034, 0x00004CEA, + 0x034, 0x000034EA, + 0x034, 0x000024E7, + 0x034, 0x0000146A, + 0x034, 0x0000006B, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0008ADF6, + 0x034, 0x00089DF3, + 0x034, 0x00088DF0, + 0x034, 0x00087DED, + 0x034, 0x00086DEA, + 0x034, 0x00085CED, + 0x034, 0x00084CEA, + 0x034, 0x000834EA, + 0x034, 0x000824E7, + 0x034, 0x0008146A, + 0x034, 0x0008006B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x018, 0x0001012A, + 0x081, 0x0007FC00, + 0x089, 0x00050110, + 0x08A, 0x00043E50, + 0x08B, 0x0002E180, + 0x08C, 0x00093C3C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0xA0000000, 0x00000000, + 0x085, 0x000F8000, + 0xB0000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x0EF, 0x00001000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0xA0000000, 0x00000000, + 0x03C, 0x00040000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00030023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00028623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00021633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0001C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00010293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00009593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00000F8B, + 0xA0000000, 0x00000000, + 0x03B, 0x0000078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00048000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00048000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00070023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00068623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00061633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0005C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00050293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00049593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x03B, 0x0004078B, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00048000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0004C000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00044000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0004C000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00048000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00004000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B0023, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A8623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A1633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0009C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00090293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00089593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0008138B, + 0xA0000000, 0x00000000, + 0x03B, 0x0008078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000800, + 0x03B, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0xA0000000, 0x00000000, + 0x03A, 0x00000803, + 0xB0000000, 0x00000000, + 0x03B, 0x00040000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000800, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000800, + 0xA0000000, 0x00000000, + 0x03A, 0x00001000, + 0xB0000000, 0x00000000, + 0x03B, 0x00080000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001802, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001802, + 0xA0000000, 0x00000000, + 0x03A, 0x00001002, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x00013124, + 0x0EF, 0x00000100, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38C, + 0x034, 0x000491AD, + 0x034, 0x000481AA, + 0x034, 0x000471A7, + 0x034, 0x000460AA, + 0x034, 0x000450A7, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x0004200C, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38C, + 0x034, 0x00049389, + 0x034, 0x0004816D, + 0x034, 0x0004716A, + 0x034, 0x0004606D, + 0x034, 0x0004506A, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x00042026, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38B, + 0x034, 0x00049388, + 0x034, 0x0004818B, + 0x034, 0x00047188, + 0x034, 0x0004606D, + 0x034, 0x0004506A, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x00042026, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38C, + 0x034, 0x00049389, + 0x034, 0x0004816D, + 0x034, 0x0004716A, + 0x034, 0x0004606D, + 0x034, 0x0004506A, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x00042026, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38B, + 0x034, 0x00049388, + 0x034, 0x0004818B, + 0x034, 0x00047188, + 0x034, 0x0004606D, + 0x034, 0x0004506A, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x00042026, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A3F5, + 0x034, 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0x000893AD, + 0x034, 0x0008838A, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3F4, + 0x034, 0x000893F0, + 0x034, 0x000883AE, + 0x034, 0x00087350, + 0x034, 0x0008634D, + 0x034, 0x0008534A, + 0x034, 0x00084347, + 0x034, 0x0008312D, + 0x034, 0x0008212A, + 0x034, 0x00081127, + 0x034, 0x0008002A, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008AFF7, + 0x034, 0x00089FF4, + 0x034, 0x00088FF1, + 0x034, 0x00087FEE, + 0x034, 0x00086FEB, + 0x034, 0x00085FE8, + 0x034, 0x00084DEB, + 0x034, 0x00083DE8, + 0x034, 0x00082DE5, + 0x034, 0x00081C8B, + 0x034, 0x00080C88, + 0xA0000000, 0x00000000, + 0x034, 0x0008A794, + 0x034, 0x00089791, + 0x034, 0x0008878E, + 0x034, 0x0008778B, + 0x034, 0x0008658D, + 0x034, 0x0008558A, + 0x034, 0x0008448D, + 0x034, 0x0008348A, + 0x034, 0x0008244C, + 0x034, 0x00081449, + 0x034, 0x0008042B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0xA0000000, 0x00000000, + 0x035, 0x00000484, + 0x035, 0x00008484, + 0x035, 0x00010484, + 0x035, 0x00020584, + 0x035, 0x00028584, + 0x035, 0x00030584, + 0x035, 0x00040584, + 0x035, 0x00048584, + 0x035, 0x00050584, + 0x035, 0x000805FB, + 0x035, 0x000885FB, + 0x035, 0x000905FB, + 0x035, 0x000A05FB, + 0x035, 0x000A85FB, + 0x035, 0x000B05FB, + 0x035, 0x000C05FB, + 0x035, 0x000C85FB, + 0x035, 0x000D05FB, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000473, + 0x036, 0x00008473, + 0x036, 0x00010473, + 0x036, 0x00020473, + 0x036, 0x00028473, + 0x036, 0x00030473, + 0x036, 0x00040473, + 0x036, 0x00048473, + 0x036, 0x00050473, + 0x036, 0x00080473, + 0x036, 0x00088473, + 0x036, 0x00090473, + 0x036, 0x000A0473, + 0x036, 0x000A8473, + 0x036, 0x000B0473, + 0x036, 0x000C0473, + 0x036, 0x000C8473, + 0x036, 0x000D0473, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0xA0000000, 0x00000000, + 0x036, 0x00000474, + 0x036, 0x00008474, + 0x036, 0x00010474, + 0x036, 0x00020474, + 0x036, 0x00028474, + 0x036, 0x00030474, + 0x036, 0x00040474, + 0x036, 0x00048474, + 0x036, 0x00050474, + 0x036, 0x00080474, + 0x036, 0x00088474, + 0x036, 0x00090474, + 0x036, 0x000A0474, + 0x036, 0x000A8474, + 0x036, 0x000B0474, + 0x036, 0x000C0474, + 0x036, 0x000C8474, + 0x036, 0x000D0474, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000004, + 0x037, 0x00000000, + 0x038, 0x0000514E, + 0x037, 0x00004000, + 0x038, 0x0000514E, + 0x037, 0x00008000, + 0x038, 0x0000514E, + 0x037, 0x00010000, + 0x038, 0x0000514E, + 0x037, 0x00014000, + 0x038, 0x0000514E, + 0x037, 0x00018000, + 0x038, 0x0000514E, + 0x037, 0x0001C000, + 0x038, 0x0000514E, + 0x037, 0x00020000, + 0x038, 0x0000514E, + 0x037, 0x00024000, + 0x038, 0x0000514E, + 0x037, 0x00028000, + 0x038, 0x0000514E, + 0x037, 0x0002C000, + 0x038, 0x0000714E, + 0x037, 0x00030000, + 0x038, 0x0000514E, + 0x037, 0x00034000, + 0x038, 0x0000514E, + 0x037, 0x00038000, + 0x038, 0x0000514E, + 0x037, 0x0003C000, + 0x038, 0x0000514E, + 0x037, 0x00040000, + 0x038, 0x0000514E, + 0x037, 0x00044000, + 0x038, 0x0000514E, + 0x037, 0x00048000, + 0x038, 0x0000514E, + 0x037, 0x00080000, + 0x038, 0x00005ECE, + 0x037, 0x00084000, + 0x038, 0x00005ECE, + 0x037, 0x00088000, + 0x038, 0x00005ECE, + 0x037, 0x00090000, + 0x038, 0x00005ECE, + 0x037, 0x00094000, + 0x038, 0x00005ECE, + 0x037, 0x00098000, + 0x038, 0x00005ECE, + 0x037, 0x0009C000, + 0x038, 0x00005ECE, + 0x037, 0x000A0000, + 0x038, 0x00005ECE, + 0x037, 0x000A4000, + 0x038, 0x00005ECE, + 0x037, 0x000A8000, + 0x038, 0x00005ECE, + 0x037, 0x000AC000, + 0x038, 0x00005ECE, + 0x037, 0x000B0000, + 0x038, 0x00005ECE, + 0x037, 0x000B4000, + 0x038, 0x00005ECE, + 0x037, 0x000B8000, + 0x038, 0x00005ECE, + 0x037, 0x000BC000, + 0x038, 0x00005ECE, + 0x037, 0x000C0000, + 0x038, 0x00005ECE, + 0x037, 0x000C4000, + 0x038, 0x00005ECE, + 0x037, 0x000C8000, + 0x038, 0x00005ECE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000008, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x0000007D, + 0x03C, 0x0000047D, + 0x03C, 0x0000087D, + 0x03C, 0x0000107D, + 0x03C, 0x0000147D, + 0x03C, 0x0000187D, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027E, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127E, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227E, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0xA0000000, 0x00000000, + 0x03C, 0x0000037E, + 0x03C, 0x00000575, + 0x03C, 0x00000971, + 0x03C, 0x0000127E, + 0x03C, 0x00001575, + 0x03C, 0x00001871, + 0x03C, 0x0000217E, + 0x03C, 0x00002575, + 0x03C, 0x00002871, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x061, 0x000C0D47, + 0x062, 0x0000133C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0xA0000000, 0x00000000, + 0x063, 0x0007D0E7, + 0xB0000000, 0x00000000, + 0x064, 0x00014FEC, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0xA0000000, 0x00000000, + 0x065, 0x000923FF, + 0xB0000000, 0x00000000, + 0x066, 0x00000040, + 0x057, 0x00050000, + 0x056, 0x00051DF0, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x055, 0x00082060, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8814A_RadioB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_RadioB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioB_8814A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_RadioB(void) +{ + return 107; +} + +/****************************************************************************** +* RadioC.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_RadioC[] = { + 0x018, 0x00013124, + 0x040, 0x00000C00, + 0x058, 0x00000F98, + 0x07F, 0x00068004, + 0x018, 0x00000006, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0xA0000000, 0x00000000, + 0x086, 0x000E4B58, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000008, + 0x0EF, 0x00002000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017823, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017823, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017823, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017823, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017823, + 0xA0000000, 0x00000000, + 0x03B, 0x0003F258, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF6, + 0x034, 0x00009DF3, + 0x034, 0x00008DF0, + 0x034, 0x00007DED, + 0x034, 0x00006DEA, + 0x034, 0x00005CED, + 0x034, 0x00004CEA, + 0x034, 0x000034EA, + 0x034, 0x000024E7, + 0x034, 0x0000146A, + 0x034, 0x0000006B, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0008ADF6, + 0x034, 0x00089DF3, + 0x034, 0x00088DF0, + 0x034, 0x00087DED, + 0x034, 0x00086DEA, + 0x034, 0x00085CED, + 0x034, 0x00084CEA, + 0x034, 0x000834EA, + 0x034, 0x000824E7, + 0x034, 0x0008146A, + 0x034, 0x0008006B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x018, 0x0001012A, + 0x081, 0x0007FC00, + 0x089, 0x00050110, + 0x08A, 0x00043E50, + 0x08B, 0x0002E180, + 0x08C, 0x00093C3C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0xA0000000, 0x00000000, + 0x085, 0x000F8000, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xA0000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xB0000000, 0x00000000, + 0x0EF, 0x00001000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0006C000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000D4000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00080000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0006C000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0008C000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00004000, + 0xA0000000, 0x00000000, + 0x03C, 0x000A0000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00030023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00028623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00021633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0001C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00010293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00009593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0000118B, + 0xA0000000, 0x00000000, + 0x03B, 0x0000078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0004C000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00084000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00080000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0004C000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000D0000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x00028000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00070023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00068623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00061633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0005C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00050293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00049593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x03B, 0x0004078B, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00080000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B0023, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A8623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A1633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0009C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00090293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00089593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0008128B, + 0xA0000000, 0x00000000, + 0x03B, 0x0008078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000800, + 0x03B, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001803, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001803, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001003, + 0xA0000000, 0x00000000, + 0x03A, 0x00000803, + 0xB0000000, 0x00000000, + 0x03B, 0x00040000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000800, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0xA0000000, 0x00000000, + 0x03A, 0x00001000, + 0xB0000000, 0x00000000, + 0x03B, 0x00080000, + 0x80000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001802, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00001802, + 0xA0000000, 0x00000000, + 0x03A, 0x00001002, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00013124, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00013124, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00013124, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00013124, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00013124, + 0xA0000000, 0x00000000, + 0x018, 0x00013124, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A38C, + 0x034, 0x000491AD, + 0x034, 0x000481AA, + 0x034, 0x000471A7, + 0x034, 0x000460AA, + 0x034, 0x000450A7, + 0x034, 0x0004402C, + 0x034, 0x00043029, + 0x034, 0x0004200C, + 0x034, 0x00041009, + 0x034, 0x00040006, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A3EF, + 0x034, 0x000493AD, + 0x034, 0x0004838A, + 0x034, 0x0004718C, + 0x034, 0x00046189, + 0x034, 0x0004506D, + 0x034, 0x0004404C, + 0x034, 0x0004302C, + 0x034, 0x00042029, + 0x034, 0x00041026, + 0x034, 0x00040023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A3EF, + 0x034, 0x000493AD, + 0x034, 0x0004838A, + 0x034, 0x0004718C, + 0x034, 0x00046189, + 0x034, 0x0004506D, + 0x034, 0x0004404C, + 0x034, 0x0004302C, + 0x034, 0x00042029, + 0x034, 0x00041026, + 0x034, 0x00040023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A3EF, + 0x034, 0x000493AD, + 0x034, 0x0004838A, + 0x034, 0x0004718C, + 0x034, 0x00046189, + 0x034, 0x0004506D, + 0x034, 0x0004404C, + 0x034, 0x0004302C, + 0x034, 0x00042029, + 0x034, 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0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 0x000893AB, + 0x034, 0x00088389, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3EE, + 0x034, 0x000893AB, + 0x034, 0x00088389, + 0x034, 0x0008718C, + 0x034, 0x00086189, + 0x034, 0x0008506D, + 0x034, 0x0008406A, + 0x034, 0x0008302C, + 0x034, 0x00082029, + 0x034, 0x00081026, + 0x034, 0x00080023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008A3F5, + 0x034, 0x000893F1, + 0x034, 0x000883B0, + 0x034, 0x00087370, + 0x034, 0x0008636D, + 0x034, 0x0008536A, + 0x034, 0x00084367, + 0x034, 0x0008308E, + 0x034, 0x0008208B, + 0x034, 0x00081088, + 0x034, 0x00080085, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0008AFF7, + 0x034, 0x00089FF5, + 0x034, 0x00088FF2, + 0x034, 0x00087FEF, + 0x034, 0x00086FEC, + 0x034, 0x00085FE9, + 0x034, 0x00084EAA, + 0x034, 0x00083EA7, + 0x034, 0x00082C70, + 0x034, 0x00081C6D, + 0x034, 0x00080C6A, + 0xA0000000, 0x00000000, + 0x034, 0x0008A794, + 0x034, 0x00089791, + 0x034, 0x0008878E, + 0x034, 0x0008778B, + 0x034, 0x0008658D, + 0x034, 0x0008558A, + 0x034, 0x0008448D, + 0x034, 0x0008348A, + 0x034, 0x0008244C, + 0x034, 0x00081449, + 0x034, 0x0008042B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0xA0000000, 0x00000000, + 0x035, 0x00000484, + 0x035, 0x00008484, + 0x035, 0x00010484, + 0x035, 0x00020584, + 0x035, 0x00028584, + 0x035, 0x00030584, + 0x035, 0x00040584, + 0x035, 0x00048584, + 0x035, 0x00050584, + 0x035, 0x000805FB, + 0x035, 0x000885FB, + 0x035, 0x000905FB, + 0x035, 0x000A05FB, + 0x035, 0x000A85FB, + 0x035, 0x000B05FB, + 0x035, 0x000C05FB, + 0x035, 0x000C85FB, + 0x035, 0x000D05FB, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000473, + 0x036, 0x00008473, + 0x036, 0x00010473, + 0x036, 0x00020473, + 0x036, 0x00028473, + 0x036, 0x00030473, + 0x036, 0x00040473, + 0x036, 0x00048473, + 0x036, 0x00050473, + 0x036, 0x00080473, + 0x036, 0x00088473, + 0x036, 0x00090473, + 0x036, 0x000A0473, + 0x036, 0x000A8473, + 0x036, 0x000B0473, + 0x036, 0x000C0473, + 0x036, 0x000C8473, + 0x036, 0x000D0473, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0xA0000000, 0x00000000, + 0x036, 0x00000474, + 0x036, 0x00008474, + 0x036, 0x00010474, + 0x036, 0x00020474, + 0x036, 0x00028474, + 0x036, 0x00030474, + 0x036, 0x00040474, + 0x036, 0x00048474, + 0x036, 0x00050474, + 0x036, 0x00080474, + 0x036, 0x00088474, + 0x036, 0x00090474, + 0x036, 0x000A0474, + 0x036, 0x000A8474, + 0x036, 0x000B0474, + 0x036, 0x000C0474, + 0x036, 0x000C8474, + 0x036, 0x000D0474, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000004, + 0x037, 0x00000000, + 0x038, 0x0000514E, + 0x037, 0x00004000, + 0x038, 0x0000514E, + 0x037, 0x00008000, + 0x038, 0x0000514E, + 0x037, 0x00010000, + 0x038, 0x0000514E, + 0x037, 0x00014000, + 0x038, 0x0000514E, + 0x037, 0x00018000, + 0x038, 0x0000514E, + 0x037, 0x0001C000, + 0x038, 0x0000514E, + 0x037, 0x00020000, + 0x038, 0x0000514E, + 0x037, 0x00024000, + 0x038, 0x0000514E, + 0x037, 0x00028000, + 0x038, 0x0000514E, + 0x037, 0x0002C000, + 0x038, 0x0000714E, + 0x037, 0x00030000, + 0x038, 0x0000514E, + 0x037, 0x00034000, + 0x038, 0x0000514E, + 0x037, 0x00038000, + 0x038, 0x0000514E, + 0x037, 0x0003C000, + 0x038, 0x0000514E, + 0x037, 0x00040000, + 0x038, 0x0000514E, + 0x037, 0x00044000, + 0x038, 0x0000514E, + 0x037, 0x00048000, + 0x038, 0x0000514E, + 0x037, 0x00080000, + 0x038, 0x00005ECE, + 0x037, 0x00084000, + 0x038, 0x00005ECE, + 0x037, 0x00088000, + 0x038, 0x00005ECE, + 0x037, 0x00090000, + 0x038, 0x00005ECE, + 0x037, 0x00094000, + 0x038, 0x00005ECE, + 0x037, 0x00098000, + 0x038, 0x00005ECE, + 0x037, 0x0009C000, + 0x038, 0x00005ECE, + 0x037, 0x000A0000, + 0x038, 0x00005ECE, + 0x037, 0x000A4000, + 0x038, 0x00005ECE, + 0x037, 0x000A8000, + 0x038, 0x00005ECE, + 0x037, 0x000AC000, + 0x038, 0x00005ECE, + 0x037, 0x000B0000, + 0x038, 0x00005ECE, + 0x037, 0x000B4000, + 0x038, 0x00005ECE, + 0x037, 0x000B8000, + 0x038, 0x00005ECE, + 0x037, 0x000BC000, + 0x038, 0x00005ECE, + 0x037, 0x000C0000, + 0x038, 0x00005ECE, + 0x037, 0x000C4000, + 0x038, 0x00005ECE, + 0x037, 0x000C8000, + 0x038, 0x00005ECE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000008, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x0000007D, + 0x03C, 0x0000047D, + 0x03C, 0x0000087D, + 0x03C, 0x0000107D, + 0x03C, 0x0000147D, + 0x03C, 0x0000187D, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000541, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001541, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002541, + 0x03C, 0x00002821, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027D, + 0x03C, 0x00000546, + 0x03C, 0x00000821, + 0x03C, 0x0000127D, + 0x03C, 0x00001546, + 0x03C, 0x00001821, + 0x03C, 0x0000227D, + 0x03C, 0x00002546, + 0x03C, 0x00002821, + 0xA0000000, 0x00000000, + 0x03C, 0x0000037E, + 0x03C, 0x00000575, + 0x03C, 0x00000971, + 0x03C, 0x0000127E, + 0x03C, 0x00001575, + 0x03C, 0x00001871, + 0x03C, 0x0000217E, + 0x03C, 0x00002575, + 0x03C, 0x00002871, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x061, 0x000C0D47, + 0x062, 0x0000133C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0xA0000000, 0x00000000, + 0x063, 0x0007D0E7, + 0xB0000000, 0x00000000, + 0x064, 0x00014FEC, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0xA0000000, 0x00000000, + 0x065, 0x000923FF, + 0xB0000000, 0x00000000, + 0x066, 0x00000040, + 0x057, 0x00050000, + 0x056, 0x00051DF0, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x055, 0x00082060, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8814A_RadioC( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioC)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_RadioC; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioC\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioC_8814A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_RadioC(void) +{ + return 107; +} + +/****************************************************************************** +* RadioD.TXT +******************************************************************************/ + +u4Byte Array_MP_8814A_RadioD[] = { + 0x018, 0x00013124, + 0x040, 0x00000C00, + 0x058, 0x00000F98, + 0x07F, 0x00068004, + 0x018, 0x00000006, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000E335A, + 0x087, 0x00079F80, + 0xA0000000, 0x00000000, + 0x086, 0x000E4B58, + 0x087, 0x00049F80, + 0xB0000000, 0x00000000, + 0x0DF, 0x00000008, + 0x0EF, 0x00002000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017803, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F09B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017803, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017803, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F09B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017803, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0003F19B, + 0x03B, 0x00037A5B, + 0x03B, 0x0002A433, + 0x03B, 0x00027BD3, + 0x03B, 0x0001F80B, + 0x03B, 0x00017803, + 0xA0000000, 0x00000000, + 0x03B, 0x0003F258, + 0x03B, 0x00030A58, + 0x03B, 0x0002FA58, + 0x03B, 0x00022590, + 0x03B, 0x0001FA50, + 0x03B, 0x00010248, + 0x03B, 0x00008240, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF6, + 0x034, 0x00009DF3, + 0x034, 0x00008DF0, + 0x034, 0x00007DED, + 0x034, 0x00006DEA, + 0x034, 0x00005CED, + 0x034, 0x00004CEA, + 0x034, 0x000034EA, + 0x034, 0x000024E7, + 0x034, 0x0000146A, + 0x034, 0x0000006B, + 0xB0000000, 0x00000000, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A0D0, + 0x034, 0x000090CD, + 0x034, 0x000080CA, + 0x034, 0x0000704D, + 0x034, 0x0000604A, + 0x034, 0x00005047, + 0x034, 0x0000400A, + 0x034, 0x00003007, + 0x034, 0x00002004, + 0x034, 0x00001001, + 0x034, 0x00000001, + 0xA0000000, 0x00000000, + 0x034, 0x0008ADF6, + 0x034, 0x00089DF3, + 0x034, 0x00088DF0, + 0x034, 0x00087DED, + 0x034, 0x00086DEA, + 0x034, 0x00085CED, + 0x034, 0x00084CEA, + 0x034, 0x000834EA, + 0x034, 0x000824E7, + 0x034, 0x0008146A, + 0x034, 0x0008006B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000192, + 0x035, 0x00008192, + 0x035, 0x00010192, + 0x036, 0x00000024, + 0x036, 0x00008024, + 0x036, 0x00010024, + 0x036, 0x00018024, + 0x0EF, 0x00000000, + 0x051, 0x00000C21, + 0x052, 0x000006D9, + 0x053, 0x000FC649, + 0x054, 0x0000017E, + 0x018, 0x0001012A, + 0x081, 0x0007FC00, + 0x089, 0x00050110, + 0x08A, 0x00043E50, + 0x08B, 0x0002E180, + 0x08C, 0x00093C3C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x085, 0x000F8000, + 0xA0000000, 0x00000000, + 0x085, 0x000F8000, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xA0000000, 0x00000000, + 0x08D, 0x000FFFF0, + 0xB0000000, 0x00000000, + 0x0EF, 0x00001000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00038023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00044000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00048000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00044000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00088000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00040000, + 0xA0000000, 0x00000000, + 0x03C, 0x00048000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00030023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00028623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00021633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0001C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00010293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00009593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00000F8B, + 0xA0000000, 0x00000000, + 0x03B, 0x0000078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00078023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00044000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x00024000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00070023, + 0x03C, 0x00048000, + 0x03A, 0x0000013C, + 0x03B, 0x00068623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00061633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0005C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00050293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00049593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x00040F8B, + 0xA0000000, 0x00000000, + 0x03B, 0x0004078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xA0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B8023, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00004000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00024000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00004000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00060000, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0xA0000000, 0x00000000, + 0x03C, 0x00004000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000B0023, + 0x80000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00020000, + 0xA0000000, 0x00000000, + 0x03C, 0x00020000, + 0xB0000000, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A8623, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x000A1633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x0009C633, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00090293, + 0x03C, 0x00000000, + 0x03A, 0x0000013C, + 0x03B, 0x00089593, + 0x03C, 0x00000000, + 0x03A, 0x00000148, + 0x80000008, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x0008138B, + 0xA0000000, 0x00000000, + 0x03B, 0x0008078B, + 0xB0000000, 0x00000000, + 0x03C, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000800, + 0x03B, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03A, 0x00000803, + 0x90000005, 0x00000000, 0x40000000, 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0x00088FF3, + 0x034, 0x00087FF0, + 0x034, 0x00086FED, + 0x034, 0x00085FEA, + 0x034, 0x00084FE7, + 0x034, 0x00083EC7, + 0x034, 0x00082EC4, + 0x034, 0x00081D4B, + 0x034, 0x00080D48, + 0xA0000000, 0x00000000, + 0x034, 0x0008A794, + 0x034, 0x00089791, + 0x034, 0x0008878E, + 0x034, 0x0008778B, + 0x034, 0x0008658D, + 0x034, 0x0008558A, + 0x034, 0x0008448D, + 0x034, 0x0008348A, + 0x034, 0x0008244C, + 0x034, 0x00081449, + 0x034, 0x0008042B, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x000006CC, + 0x035, 0x000086CC, + 0x035, 0x000106CC, + 0x035, 0x000206CC, + 0x035, 0x000286CC, + 0x035, 0x000306CC, + 0x035, 0x000406CC, + 0x035, 0x000486CC, + 0x035, 0x000506CC, + 0x035, 0x000806CC, + 0x035, 0x000886CC, + 0x035, 0x000906CC, + 0x035, 0x000A06CC, + 0x035, 0x000A86CC, + 0x035, 0x000B06CC, + 0x035, 0x000C06CC, + 0x035, 0x000C86CC, + 0x035, 0x000D06CC, + 0xA0000000, 0x00000000, + 0x035, 0x00000484, + 0x035, 0x00008484, + 0x035, 0x00010484, + 0x035, 0x00020584, + 0x035, 0x00028584, + 0x035, 0x00030584, + 0x035, 0x00040584, + 0x035, 0x00048584, + 0x035, 0x00050584, + 0x035, 0x000805FB, + 0x035, 0x000885FB, + 0x035, 0x000905FB, + 0x035, 0x000A05FB, + 0x035, 0x000A85FB, + 0x035, 0x000B05FB, + 0x035, 0x000C05FB, + 0x035, 0x000C85FB, + 0x035, 0x000D05FB, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x0DF, 0x00000001, + 0xA0000000, 0x00000000, + 0x0DF, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000473, + 0x036, 0x00008473, + 0x036, 0x00010473, + 0x036, 0x00020473, + 0x036, 0x00028473, + 0x036, 0x00030473, + 0x036, 0x00040473, + 0x036, 0x00048473, + 0x036, 0x00050473, + 0x036, 0x00080473, + 0x036, 0x00088473, + 0x036, 0x00090473, + 0x036, 0x000A0473, + 0x036, 0x000A8473, + 0x036, 0x000B0473, + 0x036, 0x000C0473, + 0x036, 0x000C8473, + 0x036, 0x000D0473, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00000475, + 0x036, 0x00008475, + 0x036, 0x00010475, + 0x036, 0x00020475, + 0x036, 0x00028475, + 0x036, 0x00030475, + 0x036, 0x00040475, + 0x036, 0x00048475, + 0x036, 0x00050475, + 0x036, 0x00080475, + 0x036, 0x00088475, + 0x036, 0x00090475, + 0x036, 0x000A0475, + 0x036, 0x000A8475, + 0x036, 0x000B0475, + 0x036, 0x000C0475, + 0x036, 0x000C8475, + 0x036, 0x000D0475, + 0xA0000000, 0x00000000, + 0x036, 0x00000474, + 0x036, 0x00008474, + 0x036, 0x00010474, + 0x036, 0x00020474, + 0x036, 0x00028474, + 0x036, 0x00030474, + 0x036, 0x00040474, + 0x036, 0x00048474, + 0x036, 0x00050474, + 0x036, 0x00080474, + 0x036, 0x00088474, + 0x036, 0x00090474, + 0x036, 0x000A0474, + 0x036, 0x000A8474, + 0x036, 0x000B0474, + 0x036, 0x000C0474, + 0x036, 0x000C8474, + 0x036, 0x000D0474, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000004, + 0x037, 0x00000000, + 0x038, 0x0000514E, + 0x037, 0x00004000, + 0x038, 0x0000514E, + 0x037, 0x00008000, + 0x038, 0x0000514E, + 0x037, 0x00010000, + 0x038, 0x0000514E, + 0x037, 0x00014000, + 0x038, 0x0000514E, + 0x037, 0x00018000, + 0x038, 0x0000514E, + 0x037, 0x0001C000, + 0x038, 0x0000514E, + 0x037, 0x00020000, + 0x038, 0x0000514E, + 0x037, 0x00024000, + 0x038, 0x0000514E, + 0x037, 0x00028000, + 0x038, 0x0000514E, + 0x037, 0x0002C000, + 0x038, 0x0000714E, + 0x037, 0x00030000, + 0x038, 0x0000514E, + 0x037, 0x00034000, + 0x038, 0x0000514E, + 0x037, 0x00038000, + 0x038, 0x0000514E, + 0x037, 0x0003C000, + 0x038, 0x0000514E, + 0x037, 0x00040000, + 0x038, 0x0000514E, + 0x037, 0x00044000, + 0x038, 0x0000514E, + 0x037, 0x00048000, + 0x038, 0x0000514E, + 0x037, 0x00080000, + 0x038, 0x00005ECE, + 0x037, 0x00084000, + 0x038, 0x00005ECE, + 0x037, 0x00088000, + 0x038, 0x00005ECE, + 0x037, 0x00090000, + 0x038, 0x00005ECE, + 0x037, 0x00094000, + 0x038, 0x00005ECE, + 0x037, 0x00098000, + 0x038, 0x00005ECE, + 0x037, 0x0009C000, + 0x038, 0x00005ECE, + 0x037, 0x000A0000, + 0x038, 0x00005ECE, + 0x037, 0x000A4000, + 0x038, 0x00005ECE, + 0x037, 0x000A8000, + 0x038, 0x00005ECE, + 0x037, 0x000AC000, + 0x038, 0x00005ECE, + 0x037, 0x000B0000, + 0x038, 0x00005ECE, + 0x037, 0x000B4000, + 0x038, 0x00005ECE, + 0x037, 0x000B8000, + 0x038, 0x00005ECE, + 0x037, 0x000BC000, + 0x038, 0x00005ECE, + 0x037, 0x000C0000, + 0x038, 0x00005ECE, + 0x037, 0x000C4000, + 0x038, 0x00005ECE, + 0x037, 0x000C8000, + 0x038, 0x00005ECE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000008, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x03C, 0x0000007D, + 0x03C, 0x0000047D, + 0x03C, 0x0000087D, + 0x03C, 0x0000107D, + 0x03C, 0x0000147D, + 0x03C, 0x0000187D, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000275, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x00001275, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x00002275, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027F, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x0000127F, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x0000227F, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027F, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x0000127F, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x0000227F, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027F, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x0000127F, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x0000227F, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027F, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x0000127F, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x0000227F, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000027F, + 0x03C, 0x00000542, + 0x03C, 0x00000821, + 0x03C, 0x0000127F, + 0x03C, 0x00001542, + 0x03C, 0x00001821, + 0x03C, 0x0000227F, + 0x03C, 0x00002542, + 0x03C, 0x00002821, + 0xA0000000, 0x00000000, + 0x03C, 0x0000037E, + 0x03C, 0x00000575, + 0x03C, 0x00000971, + 0x03C, 0x0000127E, + 0x03C, 0x00001575, + 0x03C, 0x00001871, + 0x03C, 0x0000217E, + 0x03C, 0x00002575, + 0x03C, 0x00002871, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x061, 0x000C0D47, + 0x062, 0x0000133C, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000750E7, + 0xA0000000, 0x00000000, + 0x063, 0x0007D0E7, + 0xB0000000, 0x00000000, + 0x064, 0x00014FEC, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x000920D0, + 0xA0000000, 0x00000000, + 0x065, 0x000923FF, + 0xB0000000, 0x00000000, + 0x066, 0x00000040, + 0x057, 0x00050000, + 0x056, 0x00051DF0, + 0x80000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0x055, 0x00082060, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8814A_RadioD( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioD)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8814A_RadioD; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_RadioD\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioD_8814A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8814A_RadioD(void) +{ + return 107; +} + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19}, + {0, 1, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 16, 16, 17, 18}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 24, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 17}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 23, 24}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type0.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type0( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type0_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type1.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19}, + {0, 1, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 17, 17, 18}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 16, 16, 17, 18}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 24, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17, 17}, + {0, 1, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 19, 19, 20}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 16, 17, 18, 18, 19, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 23, 24}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type1( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type1_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type2.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, + {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type2( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type2_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type3.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, + {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type3( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type3_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type4.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 10, 10, 11, 11, 12, 12, 13, 14, 15, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 22, 22, 22, 22, 22}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 23, 23, 23, 23, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 10, 11, 12, 13, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21, 21}, + {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 21, 21, 21, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 20, 20, 20, 20, 20, 20}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type4( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type4_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type5.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 3, 3, 3, 4, 6, 6, 7, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 4, 5, 6, 7, 7, 8, 7, 8, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 9, 10, 10, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 0, 0, 1, 1, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 0, 1, 1, 2, 2, 3, 5, 7, 8, 9, 10, 11, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 4, 6, 7, 7, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 3, 7, 7, 8, 8, 9, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 0, 1, 2, 3, 4, 5, 7, 8, 8, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 1, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 9, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13}, + {0, 0, 1, 2, 3, 3, 5, 5, 6, 8, 8, 9, 10, 11, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 4, 4, 5, 7, 8, 9, 9, 10, 11, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 3, 7, 7, 8, 8, 9, 11, 12, 12, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 0, 1, 2, 3, 4, 5, 7, 8, 8, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 1, 2, 2, 4, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 0, 2, 3, 4, 5, 6, 8, 8, 9, 9, 11, 12, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 0, 1, 2, 3, 3, 4, 6, 7, 8, 9, 10, 11, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 0, 1, 2, 3, 3, 3, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12}, + {0, 2, 3, 4, 5, 7, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 4, 6, 7, 8, 8, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 3, 3, 5, 5, 6, 6, 8, 8, 9, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 8, 9, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 0, 1, 3, 3, 4, 5, 5, 6, 7, 7, 8, 10, 10, 11, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 8, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 111, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 10, 10, 10, 10, 10, 11, 11, 10, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type5_8814A[] = {0, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type5_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8814A[] = {0, 2, 3, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8814A[] = {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8814A[] = {0, 1, 1, 2, 2, 2, 3, 4, 4, 5, 6, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type5( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type5_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type6.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type6( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type6_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type7.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type7( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type7_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type8.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 4, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 4, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 0, 1, 2, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 3, 4, 4, 5, 6, 7, 7, 8, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 0, 1, 2, 4, 5, 5, 6, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 10, 11, 11, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 10, 10, 11, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 10, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, + {0, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type8_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, + {0, 0, 1, 2, 3, 3, 4, 4, 6, 7, 7, 9, 10, 11, 12, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 11, 11, 11, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 10, 11, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 10, 11, 12, 12, 13, 14, 14, 14, 14, 14, 14, 14}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type8_8814A[] = {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type8_8814A[] = {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type8_8814A[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type8( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type8_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type9.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, + {0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type9_8814A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type9_8814A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type9( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P, gDeltaSwingTableIdx_MP_2GC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N, gDeltaSwingTableIdx_MP_2GC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P, gDeltaSwingTableIdx_MP_2GD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N, gDeltaSwingTableIdx_MP_2GD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P, gDeltaSwingTableIdx_MP_2GCCKC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N, gDeltaSwingTableIdx_MP_2GCCKC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P, gDeltaSwingTableIdx_MP_2GCCKD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N, gDeltaSwingTableIdx_MP_2GCCKD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P, gDeltaSwingTableIdx_MP_5GC_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N, gDeltaSwingTableIdx_MP_5GC_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P, gDeltaSwingTableIdx_MP_5GD_P_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N, gDeltaSwingTableIdx_MP_5GD_N_TxPowerTrack_Type9_8814A, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTSSI.TXT +******************************************************************************/ + +u1Byte gDeltaTSSITableIdx_MP_5GD_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 8, 8, 10, 13, 15, 20, 22, 25, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 7, 9, 11, 11, 13, 15, 17, 23, 23, 31, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 7, 9, 10, 15, 15, 17, 20, 22, 25, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; +u1Byte gDeltaTSSITableIdx_MP_5GC_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 4, 6, 7, 9, 11, 13, 15, 18, 19, 22, 24, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 5, 6, 8, 10, 11, 13, 15, 18, 20, 23, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 4, 5, 7, 9, 11, 13, 14, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; +u1Byte gDeltaTSSITableIdx_MP_5GB_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 4, 5, 6, 7, 9, 11, 13, 15, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 5, 6, 7, 9, 11, 13, 15, 17, 19, 22, 25, 27, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 6, 7, 9, 11, 13, 15, 17, 19, 22, 24, 27, 29, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; +u1Byte gDeltaTSSITableIdx_MP_5GA_TxPowerTSSI_8814A[][DELTA_SWINTSSI_SIZE] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19, 22, 24, 26, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 21, 23, 26, 28, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 5, 6, 7, 8, 9, 9, 10, 12, 13, 14, 15, 17, 20, 22, 24, 25, 29, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; +u1Byte gDeltaTSSITableIdx_MP_2GD_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GC_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GB_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GA_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GCCKD_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GCCKC_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GCCKB_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +u1Byte gDeltaTSSITableIdx_MP_2GCCKA_TxPowerTSSI_8814A[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTSSI( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8814A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GA, gDeltaTSSITableIdx_MP_2GA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GB, gDeltaTSSITableIdx_MP_2GB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GC, gDeltaTSSITableIdx_MP_2GC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GD, gDeltaTSSITableIdx_MP_2GD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA, gDeltaTSSITableIdx_MP_2GCCKA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB, gDeltaTSSITableIdx_MP_2GCCKB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC, gDeltaTSSITableIdx_MP_2GCCKC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD, gDeltaTSSITableIdx_MP_2GCCKD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GA, gDeltaTSSITableIdx_MP_5GA_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GB, gDeltaTSSITableIdx_MP_5GB_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GC, gDeltaTSSITableIdx_MP_5GC_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTSSITable_5GD, gDeltaTSSITableIdx_MP_5GD_TxPowerTSSI_8814A, DELTA_SWINTSSI_SIZE*3); +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", 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"28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "30", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "36", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "36", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "36", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "36", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "36", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "36", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "26", + "ETSI", "5G", "20M", "HT", "3T", "36", "28", + "MKK", "5G", "20M", "HT", "3T", "36", "28", + "FCC", "5G", "20M", "HT", "3T", "40", "26", + "ETSI", "5G", "20M", "HT", "3T", "40", "28", + "MKK", "5G", "20M", "HT", "3T", "40", "28", + "FCC", "5G", "20M", "HT", "3T", "44", "26", + "ETSI", "5G", "20M", "HT", "3T", "44", "28", + "MKK", "5G", "20M", "HT", "3T", "44", "28", + "FCC", "5G", "20M", "HT", "3T", "48", "26", + "ETSI", "5G", "20M", "HT", "3T", "48", "28", + "MKK", "5G", "20M", "HT", "3T", "48", "28", + "FCC", "5G", "20M", "HT", "3T", "52", "32", + "ETSI", "5G", "20M", "HT", "3T", "52", "28", + "MKK", "5G", "20M", "HT", "3T", "52", "28", + "FCC", "5G", "20M", "HT", "3T", "56", "30", + "ETSI", "5G", "20M", "HT", "3T", "56", "28", + "MKK", "5G", "20M", "HT", "3T", "56", "28", + "FCC", "5G", "20M", "HT", "3T", "60", "28", + "ETSI", "5G", "20M", "HT", "3T", "60", "28", + "MKK", "5G", "20M", "HT", "3T", "60", "28", + "FCC", "5G", "20M", "HT", "3T", "64", "24", + "ETSI", "5G", "20M", "HT", "3T", "64", "28", + "MKK", "5G", "20M", "HT", "3T", "64", "28", + "FCC", "5G", "20M", "HT", "3T", "100", "26", + "ETSI", "5G", "20M", "HT", "3T", "100", "28", + "MKK", "5G", "20M", "HT", "3T", "100", "28", + "FCC", "5G", "20M", "HT", "3T", "104", "26", + "ETSI", "5G", "20M", "HT", "3T", "104", "28", + "MKK", "5G", "20M", "HT", "3T", "104", "28", + "FCC", "5G", "20M", "HT", "3T", "108", "28", + "ETSI", "5G", "20M", "HT", "3T", "108", "28", + "MKK", "5G", "20M", "HT", "3T", "108", "28", + "FCC", "5G", "20M", "HT", "3T", "112", "30", + "ETSI", "5G", "20M", "HT", "3T", "112", "28", + "MKK", "5G", "20M", "HT", "3T", "112", "28", + "FCC", "5G", "20M", "HT", "3T", "116", "30", + "ETSI", "5G", "20M", "HT", "3T", "116", "28", + "MKK", "5G", "20M", "HT", "3T", "116", "28", + "FCC", "5G", "20M", "HT", "3T", "120", "32", + "ETSI", "5G", "20M", "HT", "3T", "120", "28", + "MKK", "5G", "20M", "HT", "3T", "120", "28", + "FCC", "5G", "20M", "HT", "3T", "124", "30", + "ETSI", "5G", "20M", "HT", "3T", "124", "28", + "MKK", "5G", "20M", "HT", "3T", "124", "28", + "FCC", "5G", "20M", "HT", "3T", "128", "28", + "ETSI", "5G", "20M", "HT", "3T", "128", "28", + "MKK", "5G", "20M", "HT", "3T", "128", "28", + "FCC", "5G", "20M", "HT", "3T", "132", "26", + "ETSI", "5G", "20M", "HT", "3T", "132", "28", + "MKK", "5G", "20M", "HT", "3T", "132", "28", + "FCC", "5G", "20M", "HT", "3T", "136", "26", + "ETSI", "5G", "20M", "HT", "3T", "136", "28", + "MKK", "5G", "20M", "HT", "3T", "136", "28", + "FCC", "5G", "20M", "HT", "3T", "140", "24", + "ETSI", "5G", "20M", "HT", "3T", "140", "28", + "MKK", "5G", "20M", "HT", "3T", "140", "28", + "FCC", "5G", "20M", "HT", "3T", "149", "32", + "ETSI", "5G", "20M", "HT", "3T", "149", "28", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "32", + "ETSI", "5G", "20M", "HT", "3T", "153", "28", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "32", + "ETSI", "5G", "20M", "HT", "3T", "157", "28", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "32", + "ETSI", "5G", "20M", "HT", "3T", "161", "28", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "32", + "ETSI", "5G", "20M", "HT", "3T", "165", "28", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "24", + "ETSI", "5G", "20M", "HT", "4T", "36", "26", + "MKK", "5G", "20M", "HT", "4T", "36", "26", + "FCC", "5G", "20M", "HT", "4T", "40", "24", + "ETSI", "5G", "20M", "HT", "4T", "40", "26", + "MKK", "5G", "20M", "HT", "4T", "40", "26", + "FCC", "5G", "20M", "HT", "4T", "44", "24", + "ETSI", "5G", "20M", "HT", "4T", "44", "26", + "MKK", "5G", "20M", "HT", "4T", "44", "26", + "FCC", "5G", "20M", "HT", "4T", "48", "24", + "ETSI", "5G", "20M", "HT", "4T", "48", "26", + "MKK", "5G", "20M", "HT", "4T", "48", "26", + "FCC", "5G", "20M", "HT", "4T", "52", "30", + "ETSI", "5G", "20M", "HT", "4T", "52", "26", + "MKK", "5G", "20M", "HT", "4T", "52", "26", + "FCC", "5G", "20M", "HT", "4T", "56", "28", + "ETSI", "5G", "20M", "HT", "4T", "56", "26", + "MKK", "5G", "20M", "HT", "4T", "56", "26", + "FCC", "5G", "20M", "HT", "4T", "60", "26", + "ETSI", "5G", "20M", "HT", "4T", "60", "26", + "MKK", "5G", "20M", "HT", "4T", "60", "26", + "FCC", "5G", "20M", "HT", "4T", "64", "22", + "ETSI", "5G", "20M", "HT", "4T", "64", "26", + "MKK", "5G", "20M", "HT", "4T", "64", "26", + "FCC", "5G", "20M", "HT", "4T", "100", "24", + "ETSI", "5G", "20M", "HT", "4T", "100", "26", + "MKK", "5G", "20M", "HT", "4T", "100", "26", + "FCC", "5G", "20M", "HT", "4T", "104", "24", + "ETSI", "5G", "20M", "HT", "4T", "104", "26", + "MKK", "5G", "20M", "HT", "4T", "104", "26", + "FCC", "5G", "20M", "HT", "4T", "108", "26", + "ETSI", "5G", "20M", "HT", "4T", "108", "26", + "MKK", "5G", "20M", "HT", "4T", "108", "26", + "FCC", "5G", "20M", "HT", "4T", "112", "28", + "ETSI", "5G", "20M", "HT", "4T", "112", "26", + "MKK", "5G", "20M", "HT", "4T", "112", "26", + "FCC", "5G", "20M", "HT", "4T", "116", "28", + "ETSI", "5G", "20M", "HT", "4T", "116", "26", + "MKK", "5G", "20M", "HT", "4T", "116", "26", + "FCC", "5G", "20M", "HT", "4T", "120", "30", + "ETSI", "5G", "20M", "HT", "4T", "120", "26", + "MKK", "5G", "20M", "HT", "4T", "120", "26", + "FCC", "5G", "20M", "HT", "4T", "124", "28", + "ETSI", "5G", "20M", "HT", "4T", "124", "26", + "MKK", "5G", "20M", "HT", "4T", "124", "26", + "FCC", "5G", "20M", "HT", "4T", "128", "26", + "ETSI", "5G", "20M", "HT", "4T", "128", "26", + "MKK", "5G", "20M", "HT", "4T", "128", "26", + "FCC", "5G", "20M", "HT", "4T", "132", "24", + "ETSI", "5G", "20M", "HT", "4T", "132", "26", + "MKK", "5G", "20M", "HT", "4T", "132", "26", + "FCC", "5G", "20M", "HT", "4T", "136", "24", + "ETSI", "5G", "20M", "HT", "4T", "136", "26", + "MKK", "5G", "20M", "HT", "4T", "136", "26", + "FCC", "5G", "20M", "HT", "4T", "140", "22", + "ETSI", "5G", "20M", "HT", "4T", "140", "26", + "MKK", "5G", "20M", "HT", "4T", "140", "26", + "FCC", "5G", "20M", "HT", "4T", "149", "30", + "ETSI", "5G", "20M", "HT", "4T", "149", "26", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "30", + "ETSI", "5G", "20M", "HT", "4T", "153", "26", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "30", + "ETSI", "5G", "20M", "HT", "4T", "157", "26", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "30", + "ETSI", "5G", "20M", "HT", "4T", "161", "26", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "30", + "ETSI", "5G", "20M", "HT", "4T", "165", "26", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "26", + "ETSI", "5G", "40M", "HT", "3T", "38", "28", + "MKK", "5G", "40M", "HT", "3T", "38", "28", + "FCC", "5G", "40M", "HT", "3T", "46", "26", + "ETSI", "5G", "40M", "HT", "3T", "46", "28", + "MKK", "5G", "40M", "HT", "3T", "46", "28", + "FCC", "5G", "40M", "HT", "3T", "54", "28", + "ETSI", "5G", "40M", "HT", "3T", "54", "28", + "MKK", "5G", "40M", "HT", "3T", "54", "28", + "FCC", "5G", "40M", "HT", "3T", "62", "28", + "ETSI", "5G", "40M", "HT", "3T", "62", "28", + "MKK", "5G", "40M", "HT", "3T", "62", "28", + "FCC", "5G", "40M", "HT", "3T", "102", "24", + "ETSI", "5G", "40M", "HT", "3T", "102", "28", + "MKK", "5G", "40M", "HT", "3T", "102", "28", + "FCC", "5G", "40M", "HT", "3T", "110", "28", + "ETSI", "5G", "40M", "HT", "3T", "110", "28", + "MKK", "5G", "40M", "HT", "3T", "110", "28", + "FCC", "5G", "40M", "HT", "3T", "118", "32", + "ETSI", "5G", "40M", "HT", "3T", "118", "28", + "MKK", "5G", "40M", "HT", "3T", "118", "28", + "FCC", "5G", "40M", "HT", "3T", "126", "30", + "ETSI", "5G", "40M", "HT", "3T", "126", "28", + "MKK", "5G", "40M", "HT", "3T", "126", "28", + "FCC", "5G", "40M", "HT", "3T", "134", "28", + "ETSI", "5G", "40M", "HT", "3T", "134", "28", + "MKK", "5G", "40M", "HT", "3T", "134", "28", + "FCC", "5G", "40M", "HT", "3T", "151", "32", + "ETSI", "5G", "40M", "HT", "3T", "151", "28", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "32", + "ETSI", "5G", "40M", "HT", "3T", "159", "28", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "24", + "ETSI", "5G", "40M", "HT", "4T", "38", "26", + "MKK", "5G", "40M", "HT", "4T", "38", "26", + "FCC", "5G", "40M", "HT", "4T", "46", "24", + "ETSI", "5G", "40M", "HT", "4T", "46", "26", + "MKK", "5G", "40M", "HT", "4T", "46", "26", + "FCC", "5G", "40M", "HT", "4T", "54", "26", + "ETSI", "5G", "40M", "HT", "4T", "54", "26", + "MKK", "5G", "40M", "HT", "4T", "54", "26", + "FCC", "5G", "40M", "HT", "4T", "62", "26", + "ETSI", "5G", "40M", "HT", "4T", "62", "26", + "MKK", "5G", "40M", "HT", "4T", "62", "26", + "FCC", "5G", "40M", "HT", "4T", "102", "22", + "ETSI", "5G", "40M", "HT", "4T", "102", "26", + "MKK", "5G", "40M", "HT", "4T", "102", "26", + "FCC", "5G", "40M", "HT", "4T", "110", "26", + "ETSI", "5G", "40M", "HT", "4T", "110", "26", + "MKK", "5G", "40M", "HT", "4T", "110", "26", + "FCC", "5G", "40M", "HT", "4T", "118", "30", + "ETSI", "5G", "40M", "HT", "4T", "118", "26", + "MKK", "5G", "40M", "HT", "4T", "118", "26", + "FCC", "5G", "40M", "HT", "4T", "126", "28", + "ETSI", "5G", "40M", "HT", "4T", "126", "26", + "MKK", "5G", "40M", "HT", "4T", "126", "26", + "FCC", "5G", "40M", "HT", "4T", "134", "26", + "ETSI", "5G", "40M", "HT", "4T", "134", "26", + "MKK", "5G", "40M", "HT", "4T", "134", "26", + "FCC", "5G", "40M", "HT", "4T", "151", "30", + "ETSI", "5G", "40M", "HT", "4T", "151", "26", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "30", + "ETSI", "5G", "40M", "HT", "4T", "159", "26", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "26", + "ETSI", "5G", "80M", "VHT", "3T", "42", "28", + "MKK", "5G", "80M", "VHT", "3T", "42", "28", + "FCC", "5G", "80M", "VHT", "3T", "58", "24", + "ETSI", "5G", "80M", "VHT", "3T", "58", "28", + "MKK", "5G", "80M", "VHT", "3T", "58", "28", + "FCC", "5G", "80M", "VHT", "3T", "106", "26", + "ETSI", "5G", "80M", "VHT", "3T", "106", "28", + "MKK", "5G", "80M", "VHT", "3T", "106", "28", + "FCC", "5G", "80M", "VHT", "3T", "122", "30", + "ETSI", "5G", "80M", "VHT", "3T", "122", "28", + "MKK", "5G", "80M", "VHT", "3T", "122", "28", + "FCC", "5G", "80M", "VHT", "3T", "155", "32", + "ETSI", "5G", "80M", "VHT", "3T", "155", "28", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "24", + "ETSI", "5G", "80M", "VHT", "4T", "42", "26", + "MKK", "5G", "80M", "VHT", "4T", "42", "26", + "FCC", "5G", "80M", "VHT", "4T", "58", "22", + "ETSI", "5G", "80M", "VHT", "4T", "58", "26", + "MKK", "5G", "80M", "VHT", "4T", "58", "26", + "FCC", "5G", "80M", "VHT", "4T", "106", "24", + "ETSI", "5G", "80M", "VHT", "4T", "106", "26", + "MKK", "5G", "80M", "VHT", "4T", "106", "26", + "FCC", "5G", "80M", "VHT", "4T", "122", "28", + "ETSI", "5G", "80M", "VHT", "4T", "122", "26", + "MKK", "5G", "80M", "VHT", "4T", "122", "26", + "FCC", "5G", "80M", "VHT", "4T", "155", "30", + "ETSI", "5G", "80M", "VHT", "4T", "155", "26", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type0.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type0[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "18", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "8", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "16", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "6", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "24", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "24", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "4", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "20M", "HT", "3T", "01", "22", + "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", + "MKK", "2.4G", "20M", "HT", "3T", "01", "28", + "FCC", "2.4G", "20M", "HT", "3T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", + "MKK", "2.4G", "20M", "HT", "3T", "02", "28", + "FCC", "2.4G", "20M", "HT", "3T", "03", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", + "MKK", "2.4G", "20M", "HT", "3T", "03", "28", + "FCC", "2.4G", "20M", "HT", "3T", "04", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", + "MKK", "2.4G", "20M", "HT", "3T", "04", "28", + "FCC", "2.4G", "20M", "HT", "3T", "05", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", + "MKK", "2.4G", "20M", "HT", "3T", "05", "28", + "FCC", "2.4G", "20M", "HT", "3T", "06", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", + "MKK", "2.4G", "20M", "HT", "3T", "06", "28", + "FCC", "2.4G", "20M", "HT", "3T", "07", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", + "MKK", "2.4G", "20M", "HT", "3T", "07", "28", + "FCC", "2.4G", "20M", "HT", "3T", "08", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", + "MKK", "2.4G", "20M", "HT", "3T", "08", "28", + "FCC", "2.4G", "20M", "HT", "3T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", + "MKK", "2.4G", "20M", "HT", "3T", "09", "28", + "FCC", "2.4G", "20M", "HT", "3T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", + "MKK", "2.4G", "20M", "HT", "3T", "10", "28", + "FCC", "2.4G", "20M", "HT", "3T", "11", "22", + "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", + "MKK", "2.4G", "20M", "HT", "3T", "11", "28", + "FCC", "2.4G", "20M", "HT", "3T", "12", "14", + "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", + "MKK", "2.4G", "20M", "HT", "3T", "12", "28", + "FCC", "2.4G", "20M", "HT", "3T", "13", "4", + "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", + "MKK", "2.4G", "20M", "HT", "3T", "13", "28", + "FCC", "2.4G", "20M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", + "MKK", "2.4G", "20M", "HT", "3T", "14", "63", + "FCC", "2.4G", "20M", "HT", "4T", "01", "20", + "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", + "MKK", "2.4G", "20M", "HT", "4T", "01", "26", + "FCC", "2.4G", "20M", "HT", "4T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", + "MKK", "2.4G", "20M", "HT", "4T", "02", "26", + "FCC", "2.4G", "20M", "HT", "4T", "03", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", + "MKK", "2.4G", "20M", "HT", "4T", "03", "26", + "FCC", "2.4G", "20M", "HT", "4T", "04", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", + "MKK", "2.4G", "20M", "HT", "4T", "04", "26", + "FCC", "2.4G", "20M", "HT", "4T", "05", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", + "MKK", "2.4G", "20M", "HT", "4T", "05", "26", + "FCC", "2.4G", "20M", "HT", "4T", "06", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", + "MKK", "2.4G", "20M", "HT", "4T", "06", "26", + "FCC", "2.4G", "20M", "HT", "4T", "07", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", + "MKK", "2.4G", "20M", "HT", "4T", "07", "26", + "FCC", "2.4G", "20M", "HT", "4T", "08", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", + "MKK", "2.4G", "20M", "HT", "4T", "08", "26", + "FCC", "2.4G", "20M", "HT", "4T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", + "MKK", "2.4G", "20M", "HT", "4T", "09", "26", + "FCC", "2.4G", "20M", "HT", "4T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", + "MKK", "2.4G", "20M", "HT", "4T", "10", "26", + "FCC", "2.4G", "20M", "HT", "4T", "11", "20", + "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", + "MKK", "2.4G", "20M", "HT", "4T", "11", "26", + "FCC", "2.4G", "20M", "HT", "4T", "12", "14", + "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", + "MKK", "2.4G", "20M", "HT", "4T", "12", "26", + "FCC", "2.4G", "20M", "HT", "4T", "13", "4", + "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", + "MKK", "2.4G", "20M", "HT", "4T", "13", "26", + "FCC", "2.4G", "20M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", + "MKK", "2.4G", "20M", "HT", "4T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "16", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", + "MKK", "2.4G", "40M", "HT", "1T", "12", "32", + "FCC", "2.4G", "40M", "HT", "1T", "13", "10", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", + "MKK", "2.4G", "40M", "HT", "1T", "13", "32", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", + "MKK", "2.4G", "40M", "HT", "2T", "12", "30", + "FCC", "2.4G", "40M", "HT", "2T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", + "MKK", "2.4G", "40M", "HT", "2T", "13", "30", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "22", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", + "MKK", "2.4G", "40M", "HT", "3T", "03", "28", + "FCC", "2.4G", "40M", "HT", "3T", "04", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", + "MKK", "2.4G", "40M", "HT", "3T", "04", "28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "20", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "26", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "26", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "26", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "24", + "ETSI", "5G", "20M", "HT", "2T", "36", "28", + "MKK", "5G", "20M", "HT", "2T", "36", "28", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "28", + "MKK", "5G", "20M", "HT", "2T", "40", "28", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "28", + "MKK", "5G", "20M", "HT", "2T", "44", "28", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "28", + "MKK", "5G", "20M", "HT", "2T", "48", "28", + "FCC", "5G", "20M", "HT", "2T", "52", "28", + "ETSI", "5G", "20M", "HT", "2T", "52", "28", + "MKK", "5G", "20M", "HT", "2T", "52", "28", + "FCC", "5G", "20M", "HT", "2T", "56", "28", + "ETSI", "5G", "20M", "HT", "2T", "56", "28", + "MKK", "5G", "20M", "HT", "2T", "56", "28", + "FCC", "5G", "20M", "HT", "2T", "60", "28", + "ETSI", "5G", "20M", "HT", "2T", "60", "28", + "MKK", "5G", "20M", "HT", "2T", "60", "28", + "FCC", "5G", "20M", "HT", "2T", "64", "24", + "ETSI", "5G", "20M", "HT", "2T", "64", "28", + "MKK", "5G", "20M", "HT", "2T", "64", "28", + "FCC", "5G", "20M", "HT", "2T", "100", "24", + "ETSI", "5G", "20M", "HT", "2T", "100", "28", + "MKK", "5G", "20M", "HT", "2T", "100", "28", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "28", + "MKK", "5G", "20M", "HT", "2T", "104", "28", + "FCC", "5G", "20M", "HT", "2T", "108", "28", + "ETSI", "5G", "20M", "HT", "2T", "108", "28", + "MKK", "5G", "20M", "HT", "2T", "108", "28", + "FCC", "5G", "20M", "HT", "2T", "112", "28", + "ETSI", "5G", "20M", "HT", "2T", "112", "28", + "MKK", "5G", "20M", "HT", "2T", "112", "28", + "FCC", "5G", "20M", "HT", "2T", "116", "28", + "ETSI", "5G", "20M", "HT", "2T", "116", "28", + "MKK", "5G", "20M", "HT", "2T", "116", "28", + "FCC", "5G", "20M", "HT", "2T", "120", "28", + "ETSI", "5G", "20M", "HT", "2T", "120", "28", + "MKK", "5G", "20M", "HT", "2T", "120", "28", + "FCC", "5G", "20M", "HT", "2T", "124", "28", + "ETSI", "5G", "20M", "HT", "2T", "124", "28", + "MKK", "5G", "20M", "HT", "2T", "124", "28", + "FCC", "5G", "20M", "HT", "2T", "128", "28", + "ETSI", "5G", "20M", "HT", "2T", "128", "28", + "MKK", "5G", "20M", "HT", "2T", "128", "28", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "28", + "MKK", "5G", "20M", "HT", "2T", "132", "28", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "28", + "MKK", "5G", "20M", "HT", "2T", "136", "28", + "FCC", "5G", "20M", "HT", "2T", "140", "24", + "ETSI", "5G", "20M", "HT", "2T", "140", "28", + "MKK", "5G", "20M", "HT", "2T", "140", "28", + "FCC", "5G", "20M", "HT", "2T", "149", "24", + "ETSI", "5G", "20M", "HT", "2T", "149", "28", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "28", + "ETSI", "5G", "20M", "HT", "2T", "153", "28", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "28", + "ETSI", "5G", "20M", "HT", "2T", "157", "28", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "28", + "ETSI", "5G", "20M", "HT", "2T", "161", "28", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "28", + "ETSI", "5G", "20M", "HT", "2T", "165", "28", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "22", + "ETSI", "5G", "20M", "HT", "3T", "36", "26", + "MKK", "5G", "20M", "HT", "3T", "36", "26", + "FCC", "5G", "20M", "HT", "3T", "40", "26", + "ETSI", "5G", "20M", "HT", "3T", "40", "26", + "MKK", "5G", "20M", "HT", "3T", "40", "26", + "FCC", "5G", "20M", "HT", "3T", "44", "26", + "ETSI", "5G", "20M", "HT", "3T", "44", "26", + "MKK", "5G", "20M", "HT", "3T", "44", "26", + "FCC", "5G", "20M", "HT", "3T", "48", "26", + "ETSI", "5G", "20M", "HT", "3T", "48", "26", + "MKK", "5G", "20M", "HT", "3T", "48", "26", + "FCC", "5G", "20M", "HT", "3T", "52", "26", + "ETSI", "5G", "20M", "HT", "3T", "52", "26", + "MKK", "5G", "20M", "HT", "3T", "52", "26", + "FCC", "5G", "20M", "HT", "3T", "56", "26", + "ETSI", "5G", "20M", "HT", "3T", "56", "26", + "MKK", "5G", "20M", "HT", "3T", "56", "26", + "FCC", "5G", "20M", "HT", "3T", "60", "26", + "ETSI", "5G", "20M", "HT", "3T", "60", "26", + "MKK", "5G", "20M", "HT", "3T", "60", "26", + "FCC", "5G", "20M", "HT", "3T", "64", "22", + "ETSI", "5G", "20M", "HT", "3T", "64", "26", + "MKK", "5G", "20M", "HT", "3T", "64", "26", + "FCC", "5G", "20M", "HT", "3T", "100", "22", + "ETSI", "5G", "20M", "HT", "3T", "100", "26", + "MKK", "5G", "20M", "HT", "3T", "100", "26", + "FCC", "5G", "20M", "HT", "3T", "104", "26", + "ETSI", "5G", "20M", "HT", "3T", "104", "26", + "MKK", "5G", "20M", "HT", "3T", "104", "26", + "FCC", "5G", "20M", "HT", "3T", "108", "26", + "ETSI", "5G", "20M", "HT", "3T", "108", "26", + "MKK", "5G", "20M", "HT", "3T", "108", "26", + "FCC", "5G", "20M", "HT", "3T", "112", "26", + "ETSI", "5G", "20M", "HT", "3T", "112", "26", + "MKK", "5G", "20M", "HT", "3T", "112", "26", + "FCC", "5G", "20M", "HT", "3T", "116", "26", + "ETSI", "5G", "20M", "HT", "3T", "116", "26", + "MKK", "5G", "20M", "HT", "3T", "116", "26", + "FCC", "5G", "20M", "HT", "3T", "120", "26", + "ETSI", "5G", "20M", "HT", "3T", "120", "26", + "MKK", "5G", "20M", "HT", "3T", "120", "26", + "FCC", "5G", "20M", "HT", "3T", "124", "26", + "ETSI", "5G", "20M", "HT", "3T", "124", "26", + "MKK", "5G", "20M", "HT", "3T", "124", "26", + "FCC", "5G", "20M", "HT", "3T", "128", "26", + "ETSI", "5G", "20M", "HT", "3T", "128", "26", + "MKK", "5G", "20M", "HT", "3T", "128", "26", + "FCC", "5G", "20M", "HT", "3T", "132", "26", + "ETSI", "5G", "20M", "HT", "3T", "132", "26", + "MKK", "5G", "20M", "HT", "3T", "132", "26", + "FCC", "5G", "20M", "HT", "3T", "136", "26", + "ETSI", "5G", "20M", "HT", "3T", "136", "26", + "MKK", "5G", "20M", "HT", "3T", "136", "26", + "FCC", "5G", "20M", "HT", "3T", "140", "22", + "ETSI", "5G", "20M", "HT", "3T", "140", "26", + "MKK", "5G", "20M", "HT", "3T", "140", "26", + "FCC", "5G", "20M", "HT", "3T", "149", "22", + "ETSI", "5G", "20M", "HT", "3T", "149", "26", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "26", + "ETSI", "5G", "20M", "HT", "3T", "153", "26", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "26", + "ETSI", "5G", "20M", "HT", "3T", "157", "26", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "26", + "ETSI", "5G", "20M", "HT", "3T", "161", "26", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "26", + "ETSI", "5G", "20M", "HT", "3T", "165", "26", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "20", + "ETSI", "5G", "20M", "HT", "4T", "36", "24", + "MKK", "5G", "20M", "HT", "4T", "36", "24", + "FCC", "5G", "20M", "HT", "4T", "40", "24", + "ETSI", "5G", "20M", "HT", "4T", "40", "24", + "MKK", "5G", "20M", "HT", "4T", "40", "24", + "FCC", "5G", "20M", "HT", "4T", "44", "24", + "ETSI", "5G", "20M", "HT", "4T", "44", "24", + "MKK", "5G", "20M", "HT", "4T", "44", "24", + "FCC", "5G", "20M", "HT", "4T", "48", "24", + "ETSI", "5G", "20M", "HT", "4T", "48", "24", + "MKK", "5G", "20M", "HT", "4T", "48", "24", + "FCC", "5G", "20M", "HT", "4T", "52", "24", + "ETSI", "5G", "20M", "HT", "4T", "52", "24", + "MKK", "5G", "20M", "HT", "4T", "52", "24", + "FCC", "5G", "20M", "HT", "4T", "56", "24", + "ETSI", "5G", "20M", "HT", "4T", "56", "24", + "MKK", "5G", "20M", "HT", "4T", "56", "24", + "FCC", "5G", "20M", "HT", "4T", "60", "24", + "ETSI", "5G", "20M", "HT", "4T", "60", "24", + "MKK", "5G", "20M", "HT", "4T", "60", "24", + "FCC", "5G", "20M", "HT", "4T", "64", "20", + "ETSI", "5G", "20M", "HT", "4T", "64", "24", + "MKK", "5G", "20M", "HT", "4T", "64", "24", + "FCC", "5G", "20M", "HT", "4T", "100", "20", + "ETSI", "5G", "20M", "HT", "4T", "100", "24", + "MKK", "5G", "20M", "HT", "4T", "100", "24", + "FCC", "5G", "20M", "HT", "4T", "104", "24", + "ETSI", "5G", "20M", "HT", "4T", "104", "24", + "MKK", "5G", "20M", "HT", "4T", "104", "24", + "FCC", "5G", "20M", "HT", "4T", "108", "24", + "ETSI", "5G", "20M", "HT", "4T", "108", "24", + "MKK", "5G", "20M", "HT", "4T", "108", "24", + "FCC", "5G", "20M", "HT", "4T", "112", "24", + "ETSI", "5G", "20M", "HT", "4T", "112", "24", + "MKK", "5G", "20M", "HT", "4T", "112", "24", + "FCC", "5G", "20M", "HT", "4T", "116", "24", + "ETSI", "5G", "20M", "HT", "4T", "116", "24", + "MKK", "5G", "20M", "HT", "4T", "116", "24", + "FCC", "5G", "20M", "HT", "4T", "120", "24", + "ETSI", "5G", "20M", "HT", "4T", "120", "24", + "MKK", "5G", "20M", "HT", "4T", "120", "24", + "FCC", "5G", "20M", "HT", "4T", "124", "24", + "ETSI", "5G", "20M", "HT", "4T", "124", "24", + "MKK", "5G", "20M", "HT", "4T", "124", "24", + "FCC", "5G", "20M", "HT", "4T", "128", "24", + "ETSI", "5G", "20M", "HT", "4T", "128", "24", + "MKK", "5G", "20M", "HT", "4T", "128", "24", + "FCC", "5G", "20M", "HT", "4T", "132", "24", + "ETSI", "5G", "20M", "HT", "4T", "132", "24", + "MKK", "5G", "20M", "HT", "4T", "132", "24", + "FCC", "5G", "20M", "HT", "4T", "136", "24", + "ETSI", "5G", "20M", "HT", "4T", "136", "24", + "MKK", "5G", "20M", "HT", "4T", "136", "24", + "FCC", "5G", "20M", "HT", "4T", "140", "20", + "ETSI", "5G", "20M", "HT", "4T", "140", "24", + "MKK", "5G", "20M", "HT", "4T", "140", "24", + "FCC", "5G", "20M", "HT", "4T", "149", "20", + "ETSI", "5G", "20M", "HT", "4T", "149", "24", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "24", + "ETSI", "5G", "20M", "HT", "4T", "153", "24", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "24", + "ETSI", "5G", "20M", "HT", "4T", "157", "24", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "24", + "ETSI", "5G", "20M", "HT", "4T", "161", "24", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "24", + "ETSI", "5G", "20M", "HT", "4T", "165", "24", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "26", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "26", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "26", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "24", + "ETSI", "5G", "40M", "HT", "2T", "38", "28", + "MKK", "5G", "40M", "HT", "2T", "38", "28", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "28", + "MKK", "5G", "40M", "HT", "2T", "46", "28", + "FCC", "5G", "40M", "HT", "2T", "54", "28", + "ETSI", "5G", "40M", "HT", "2T", "54", "28", + "MKK", "5G", "40M", "HT", "2T", "54", "28", + "FCC", "5G", "40M", "HT", "2T", "62", "24", + "ETSI", "5G", "40M", "HT", "2T", "62", "28", + "MKK", "5G", "40M", "HT", "2T", "62", "28", + "FCC", "5G", "40M", "HT", "2T", "102", "24", + "ETSI", "5G", "40M", "HT", "2T", "102", "28", + "MKK", "5G", "40M", "HT", "2T", "102", "28", + "FCC", "5G", "40M", "HT", "2T", "110", "28", + "ETSI", "5G", "40M", "HT", "2T", "110", "28", + "MKK", "5G", "40M", "HT", "2T", "110", "28", + "FCC", "5G", "40M", "HT", "2T", "118", "28", + "ETSI", "5G", "40M", "HT", "2T", "118", "28", + "MKK", "5G", "40M", "HT", "2T", "118", "28", + "FCC", "5G", "40M", "HT", "2T", "126", "28", + "ETSI", "5G", "40M", "HT", "2T", "126", "28", + "MKK", "5G", "40M", "HT", "2T", "126", "28", + "FCC", "5G", "40M", "HT", "2T", "134", "28", + "ETSI", "5G", "40M", "HT", "2T", "134", "28", + "MKK", "5G", "40M", "HT", "2T", "134", "28", + "FCC", "5G", "40M", "HT", "2T", "151", "24", + "ETSI", "5G", "40M", "HT", "2T", "151", "28", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "28", + "ETSI", "5G", "40M", "HT", "2T", "159", "28", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "20", + "ETSI", "5G", "40M", "HT", "3T", "38", "26", + "MKK", "5G", "40M", "HT", "3T", "38", "26", + "FCC", "5G", "40M", "HT", "3T", "46", "26", + "ETSI", "5G", "40M", "HT", "3T", "46", "26", + "MKK", "5G", "40M", "HT", "3T", "46", "26", + "FCC", "5G", "40M", "HT", "3T", "54", "26", + "ETSI", "5G", "40M", "HT", "3T", "54", "26", + "MKK", "5G", "40M", "HT", "3T", "54", "26", + "FCC", "5G", "40M", "HT", "3T", "62", "20", + "ETSI", "5G", "40M", "HT", "3T", "62", "26", + "MKK", "5G", "40M", "HT", "3T", "62", "26", + "FCC", "5G", "40M", "HT", "3T", "102", "20", + "ETSI", "5G", "40M", "HT", "3T", "102", "26", + "MKK", "5G", "40M", "HT", "3T", "102", "26", + "FCC", "5G", "40M", "HT", "3T", "110", "26", + "ETSI", "5G", "40M", "HT", "3T", "110", "26", + "MKK", "5G", "40M", "HT", "3T", "110", "26", + "FCC", "5G", "40M", "HT", "3T", "118", "26", + "ETSI", "5G", "40M", "HT", "3T", "118", "26", + "MKK", "5G", "40M", "HT", "3T", "118", "26", + "FCC", "5G", "40M", "HT", "3T", "126", "26", + "ETSI", "5G", "40M", "HT", "3T", "126", "26", + "MKK", "5G", "40M", "HT", "3T", "126", "26", + "FCC", "5G", "40M", "HT", "3T", "134", "26", + "ETSI", "5G", "40M", "HT", "3T", "134", "26", + "MKK", "5G", "40M", "HT", "3T", "134", "26", + "FCC", "5G", "40M", "HT", "3T", "151", "20", + "ETSI", "5G", "40M", "HT", "3T", "151", "26", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "26", + "ETSI", "5G", "40M", "HT", "3T", "159", "26", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "18", + "ETSI", "5G", "40M", "HT", "4T", "38", "24", + "MKK", "5G", "40M", "HT", "4T", "38", "24", + "FCC", "5G", "40M", "HT", "4T", "46", "24", + "ETSI", "5G", "40M", "HT", "4T", "46", "24", + "MKK", "5G", "40M", "HT", "4T", "46", "24", + "FCC", "5G", "40M", "HT", "4T", "54", "24", + "ETSI", "5G", "40M", "HT", "4T", "54", "24", + "MKK", "5G", "40M", "HT", "4T", "54", "24", + "FCC", "5G", "40M", "HT", "4T", "62", "18", + "ETSI", "5G", "40M", "HT", "4T", "62", "24", + "MKK", "5G", "40M", "HT", "4T", "62", "24", + "FCC", "5G", "40M", "HT", "4T", "102", "18", + "ETSI", "5G", "40M", "HT", "4T", "102", "24", + "MKK", "5G", "40M", "HT", "4T", "102", "24", + "FCC", "5G", "40M", "HT", "4T", "110", "24", + "ETSI", "5G", "40M", "HT", "4T", "110", "24", + "MKK", "5G", "40M", "HT", "4T", "110", "24", + "FCC", "5G", "40M", "HT", "4T", "118", "24", + "ETSI", "5G", "40M", "HT", "4T", "118", "24", + "MKK", "5G", "40M", "HT", "4T", "118", "24", + "FCC", "5G", "40M", "HT", "4T", "126", "24", + "ETSI", "5G", "40M", "HT", "4T", "126", "24", + "MKK", "5G", "40M", "HT", "4T", "126", "24", + "FCC", "5G", "40M", "HT", "4T", "134", "24", + "ETSI", "5G", "40M", "HT", "4T", "134", "24", + "MKK", "5G", "40M", "HT", "4T", "134", "24", + "FCC", "5G", "40M", "HT", "4T", "151", "18", + "ETSI", "5G", "40M", "HT", "4T", "151", "24", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "24", + "ETSI", "5G", "40M", "HT", "4T", "159", "24", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "22", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "22", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "22", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "20", + "ETSI", "5G", "80M", "VHT", "2T", "42", "28", + "MKK", "5G", "80M", "VHT", "2T", "42", "28", + "FCC", "5G", "80M", "VHT", "2T", "58", "20", + "ETSI", "5G", "80M", "VHT", "2T", "58", "28", + "MKK", "5G", "80M", "VHT", "2T", "58", "28", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "28", + "MKK", "5G", "80M", "VHT", "2T", "106", "28", + "FCC", "5G", "80M", "VHT", "2T", "122", "28", + "ETSI", "5G", "80M", "VHT", "2T", "122", "28", + "MKK", "5G", "80M", "VHT", "2T", "122", "28", + "FCC", "5G", "80M", "VHT", "2T", "155", "20", + "ETSI", "5G", "80M", "VHT", "2T", "155", "28", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "18", + "ETSI", "5G", "80M", "VHT", "3T", "42", "26", + "MKK", "5G", "80M", "VHT", "3T", "42", "26", + "FCC", "5G", "80M", "VHT", "3T", "58", "18", + "ETSI", "5G", "80M", "VHT", "3T", "58", "26", + "MKK", "5G", "80M", "VHT", "3T", "58", "26", + "FCC", "5G", "80M", "VHT", "3T", "106", "18", + "ETSI", "5G", "80M", "VHT", "3T", "106", "26", + "MKK", "5G", "80M", "VHT", "3T", "106", "26", + "FCC", "5G", "80M", "VHT", "3T", "122", "26", + "ETSI", "5G", "80M", "VHT", "3T", "122", "26", + "MKK", "5G", "80M", "VHT", "3T", "122", "26", + "FCC", "5G", "80M", "VHT", "3T", "155", "18", + "ETSI", "5G", "80M", "VHT", "3T", "155", "26", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "16", + "ETSI", "5G", "80M", "VHT", "4T", "42", "24", + "MKK", "5G", "80M", "VHT", "4T", "42", "24", + "FCC", "5G", "80M", "VHT", "4T", "58", "16", + "ETSI", "5G", "80M", "VHT", "4T", "58", "24", + "MKK", "5G", "80M", "VHT", "4T", "58", "24", + "FCC", "5G", "80M", "VHT", "4T", "106", "16", + "ETSI", "5G", "80M", "VHT", "4T", "106", "24", + "MKK", "5G", "80M", "VHT", "4T", "106", "24", + "FCC", "5G", "80M", "VHT", "4T", "122", "24", + "ETSI", "5G", "80M", "VHT", "4T", "122", "24", + "MKK", "5G", "80M", "VHT", "4T", "122", "24", + "FCC", "5G", "80M", "VHT", "4T", "155", "16", + "ETSI", "5G", "80M", "VHT", "4T", "155", "24", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type0)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type0; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type0)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type0; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type1.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type1[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "18", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "8", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "16", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "6", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", 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"30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "4", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "20M", "HT", "3T", "01", "24", + "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", + "MKK", "2.4G", "20M", "HT", "3T", "01", "28", + "FCC", "2.4G", "20M", "HT", "3T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", + "MKK", "2.4G", "20M", "HT", "3T", "02", "28", + "FCC", "2.4G", "20M", "HT", "3T", "03", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", + "MKK", "2.4G", "20M", "HT", "3T", "03", "28", + "FCC", "2.4G", "20M", "HT", "3T", "04", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", + "MKK", "2.4G", "20M", "HT", "3T", "04", "28", + "FCC", "2.4G", "20M", "HT", "3T", "05", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", + "MKK", "2.4G", "20M", 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"HT", "4T", "12", "26", + "MKK", "2.4G", "20M", "HT", "4T", "12", "26", + "FCC", "2.4G", "20M", "HT", "4T", "13", "4", + "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", + "MKK", "2.4G", "20M", "HT", "4T", "13", "26", + "FCC", "2.4G", "20M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", + "MKK", "2.4G", "20M", "HT", "4T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "32", + "ETSI", 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"2.4G", "40M", "HT", "2T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", + "MKK", "2.4G", "40M", "HT", "2T", "12", "30", + "FCC", "2.4G", "40M", "HT", "2T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", + "MKK", "2.4G", "40M", "HT", "2T", "13", "30", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", + "MKK", "2.4G", "40M", "HT", "3T", "03", "28", + "FCC", "2.4G", "40M", "HT", "3T", "04", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", + "MKK", "2.4G", "40M", "HT", "3T", "04", "28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "24", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "22", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "28", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "30", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "28", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "28", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "26", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "30", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "30", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "30", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "30", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "30", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "26", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "30", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "30", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "30", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "30", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "24", + "ETSI", "5G", "20M", "HT", "3T", "36", "28", + "MKK", "5G", "20M", "HT", "3T", "36", "28", + "FCC", "5G", "20M", "HT", "3T", "40", "28", + "ETSI", "5G", "20M", "HT", "3T", "40", "28", + "MKK", "5G", "20M", "HT", "3T", "40", "28", + "FCC", "5G", "20M", "HT", "3T", "44", "28", + "ETSI", "5G", "20M", "HT", "3T", "44", "28", + "MKK", "5G", "20M", "HT", "3T", "44", "28", + "FCC", "5G", "20M", "HT", "3T", "48", "28", + "ETSI", "5G", "20M", "HT", "3T", "48", "28", + "MKK", "5G", "20M", "HT", "3T", "48", "28", + "FCC", "5G", "20M", "HT", "3T", "52", "28", + "ETSI", "5G", "20M", "HT", "3T", "52", "28", + "MKK", "5G", "20M", "HT", "3T", "52", "28", + "FCC", "5G", "20M", "HT", "3T", "56", "28", + "ETSI", "5G", "20M", "HT", "3T", "56", "28", + "MKK", "5G", "20M", "HT", "3T", "56", "28", + "FCC", "5G", "20M", "HT", "3T", "60", "28", + "ETSI", "5G", "20M", "HT", "3T", "60", "28", + "MKK", "5G", "20M", "HT", "3T", "60", "28", + "FCC", "5G", "20M", "HT", "3T", "64", "26", + "ETSI", "5G", "20M", "HT", "3T", "64", "28", + "MKK", "5G", "20M", "HT", "3T", "64", "28", + "FCC", "5G", "20M", "HT", "3T", "100", "24", + "ETSI", "5G", "20M", "HT", "3T", "100", "28", + "MKK", "5G", "20M", "HT", "3T", "100", "28", + "FCC", "5G", "20M", "HT", "3T", "104", "28", + "ETSI", "5G", "20M", "HT", "3T", "104", "28", + "MKK", "5G", "20M", "HT", "3T", "104", "28", + "FCC", "5G", "20M", "HT", "3T", "108", "28", + "ETSI", "5G", "20M", "HT", "3T", "108", "28", + "MKK", "5G", "20M", "HT", "3T", "108", "28", + "FCC", "5G", "20M", "HT", "3T", "112", "28", + "ETSI", "5G", "20M", "HT", "3T", "112", "28", + "MKK", "5G", "20M", "HT", "3T", "112", "28", + "FCC", "5G", "20M", "HT", "3T", "116", "28", + "ETSI", "5G", "20M", "HT", "3T", "116", "28", + "MKK", "5G", "20M", "HT", "3T", "116", "28", + "FCC", "5G", "20M", "HT", "3T", "120", "28", + "ETSI", "5G", "20M", "HT", "3T", "120", "28", + "MKK", "5G", "20M", "HT", "3T", "120", "28", + "FCC", "5G", "20M", "HT", "3T", "124", "28", + "ETSI", "5G", "20M", "HT", "3T", "124", "28", + "MKK", "5G", "20M", "HT", "3T", "124", "28", + "FCC", "5G", "20M", "HT", "3T", "128", "28", + "ETSI", "5G", "20M", "HT", "3T", "128", "28", + "MKK", "5G", "20M", "HT", "3T", "128", "28", + "FCC", "5G", "20M", "HT", "3T", "132", "28", + "ETSI", "5G", "20M", "HT", "3T", "132", "28", + "MKK", "5G", "20M", "HT", "3T", "132", "28", + "FCC", "5G", "20M", "HT", "3T", "136", "28", + "ETSI", "5G", "20M", "HT", "3T", "136", "28", + "MKK", "5G", "20M", "HT", "3T", "136", "28", + "FCC", "5G", "20M", "HT", "3T", "140", "24", + "ETSI", "5G", "20M", "HT", "3T", "140", "28", + "MKK", "5G", "20M", "HT", "3T", "140", "28", + "FCC", "5G", "20M", "HT", "3T", "149", "24", + "ETSI", "5G", "20M", "HT", "3T", "149", "28", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "28", + "ETSI", "5G", "20M", "HT", "3T", "153", "28", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "28", + "ETSI", "5G", "20M", "HT", "3T", "157", "28", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "28", + "ETSI", "5G", "20M", "HT", "3T", "161", "28", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "28", + "ETSI", "5G", "20M", "HT", "3T", "165", "28", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "22", + "ETSI", "5G", "20M", "HT", "4T", "36", "26", + "MKK", "5G", "20M", "HT", "4T", "36", "26", + "FCC", "5G", "20M", "HT", "4T", "40", "26", + "ETSI", "5G", "20M", "HT", "4T", "40", "26", + "MKK", "5G", "20M", "HT", "4T", "40", "26", + "FCC", "5G", "20M", "HT", "4T", "44", "26", + "ETSI", "5G", "20M", "HT", "4T", "44", "26", + "MKK", "5G", "20M", "HT", "4T", "44", "26", + "FCC", "5G", "20M", "HT", "4T", "48", "26", + "ETSI", "5G", "20M", "HT", "4T", "48", "26", + "MKK", "5G", "20M", "HT", "4T", "48", "26", + "FCC", "5G", "20M", "HT", "4T", "52", "26", + "ETSI", "5G", "20M", "HT", "4T", "52", "26", + "MKK", "5G", "20M", "HT", "4T", "52", "26", + "FCC", "5G", "20M", "HT", "4T", "56", "26", + "ETSI", "5G", "20M", "HT", "4T", "56", "26", + "MKK", "5G", "20M", "HT", "4T", "56", "26", + "FCC", "5G", "20M", "HT", "4T", "60", "26", + "ETSI", "5G", "20M", "HT", "4T", "60", "26", + "MKK", "5G", "20M", "HT", "4T", "60", "26", + "FCC", "5G", "20M", "HT", "4T", "64", "24", + "ETSI", "5G", "20M", "HT", "4T", "64", "26", + "MKK", "5G", "20M", "HT", "4T", "64", "26", + "FCC", "5G", "20M", "HT", "4T", "100", "22", + "ETSI", "5G", "20M", "HT", "4T", "100", "26", + "MKK", "5G", "20M", "HT", "4T", "100", "26", + "FCC", "5G", "20M", "HT", "4T", "104", "26", + "ETSI", "5G", "20M", "HT", "4T", "104", "26", + "MKK", "5G", "20M", "HT", "4T", "104", "26", + "FCC", "5G", "20M", "HT", "4T", "108", "26", + "ETSI", "5G", "20M", "HT", "4T", "108", "26", + "MKK", "5G", "20M", "HT", "4T", "108", "26", + "FCC", "5G", "20M", "HT", "4T", "112", "26", + "ETSI", "5G", "20M", "HT", "4T", "112", "26", + "MKK", "5G", "20M", "HT", "4T", "112", "26", + "FCC", "5G", "20M", "HT", "4T", "116", "26", + "ETSI", "5G", "20M", "HT", "4T", "116", "26", + "MKK", "5G", "20M", "HT", "4T", "116", "26", + "FCC", "5G", "20M", "HT", "4T", "120", "26", + "ETSI", "5G", "20M", "HT", "4T", "120", "26", + "MKK", "5G", "20M", "HT", "4T", "120", "26", + "FCC", "5G", "20M", "HT", "4T", "124", "26", + "ETSI", "5G", "20M", "HT", "4T", "124", "26", + "MKK", "5G", "20M", "HT", "4T", "124", "26", + "FCC", "5G", "20M", "HT", "4T", "128", "26", + "ETSI", "5G", "20M", "HT", "4T", "128", "26", + "MKK", "5G", "20M", "HT", "4T", "128", "26", + "FCC", "5G", "20M", "HT", "4T", "132", "26", + "ETSI", "5G", "20M", "HT", "4T", "132", "26", + "MKK", "5G", "20M", "HT", "4T", "132", "26", + "FCC", "5G", "20M", "HT", "4T", "136", "26", + "ETSI", "5G", "20M", "HT", "4T", "136", "26", + "MKK", "5G", "20M", "HT", "4T", "136", "26", + "FCC", "5G", "20M", "HT", "4T", "140", "22", + "ETSI", "5G", "20M", "HT", "4T", "140", "26", + "MKK", "5G", "20M", "HT", "4T", "140", "26", + "FCC", "5G", "20M", "HT", "4T", "149", "22", + "ETSI", "5G", "20M", "HT", "4T", "149", "26", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "26", + "ETSI", "5G", "20M", "HT", "4T", "153", "26", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "26", + "ETSI", "5G", "20M", "HT", "4T", "157", "26", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "26", + "ETSI", "5G", "20M", "HT", "4T", "161", "26", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "26", + "ETSI", "5G", "20M", "HT", "4T", "165", "26", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "28", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "28", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "26", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "28", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "26", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "20", + "ETSI", "5G", "40M", "HT", "3T", "38", "28", + "MKK", "5G", "40M", "HT", "3T", "38", "28", + "FCC", "5G", "40M", "HT", "3T", "46", "28", + "ETSI", "5G", "40M", "HT", "3T", "46", "28", + "MKK", "5G", "40M", "HT", "3T", "46", "28", + "FCC", "5G", "40M", "HT", "3T", "54", "28", + "ETSI", "5G", "40M", "HT", "3T", "54", "28", + "MKK", "5G", "40M", "HT", "3T", "54", "28", + "FCC", "5G", "40M", "HT", "3T", "62", "20", + "ETSI", "5G", "40M", "HT", "3T", "62", "28", + "MKK", "5G", "40M", "HT", "3T", "62", "28", + "FCC", "5G", "40M", "HT", "3T", "102", "22", + "ETSI", "5G", "40M", "HT", "3T", "102", "28", + "MKK", "5G", "40M", "HT", "3T", "102", "28", + "FCC", "5G", "40M", "HT", "3T", "110", "28", + "ETSI", "5G", "40M", "HT", "3T", "110", "28", + "MKK", "5G", "40M", "HT", "3T", "110", "28", + "FCC", "5G", "40M", "HT", "3T", "118", "28", + "ETSI", "5G", "40M", "HT", "3T", "118", "28", + "MKK", "5G", "40M", "HT", "3T", "118", "28", + "FCC", "5G", "40M", "HT", "3T", "126", "28", + "ETSI", "5G", "40M", "HT", "3T", "126", "28", + "MKK", "5G", "40M", "HT", "3T", "126", "28", + "FCC", "5G", "40M", "HT", "3T", "134", "26", + "ETSI", "5G", "40M", "HT", "3T", "134", "28", + "MKK", "5G", "40M", "HT", "3T", "134", "28", + "FCC", "5G", "40M", "HT", "3T", "151", "22", + "ETSI", "5G", "40M", "HT", "3T", "151", "28", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "28", + "ETSI", "5G", "40M", "HT", "3T", "159", "28", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "18", + "ETSI", "5G", "40M", "HT", "4T", "38", "26", + "MKK", "5G", "40M", "HT", "4T", "38", "26", + "FCC", "5G", "40M", "HT", "4T", "46", "26", + "ETSI", "5G", "40M", "HT", "4T", "46", "26", + "MKK", "5G", "40M", "HT", "4T", "46", "26", + "FCC", "5G", "40M", "HT", "4T", "54", "26", + "ETSI", "5G", "40M", "HT", "4T", "54", "26", + "MKK", "5G", "40M", "HT", "4T", "54", "26", + "FCC", "5G", "40M", "HT", "4T", "62", "18", + "ETSI", "5G", "40M", "HT", "4T", "62", "26", + "MKK", "5G", "40M", "HT", "4T", "62", "26", + "FCC", "5G", "40M", "HT", "4T", "102", "20", + "ETSI", "5G", "40M", "HT", "4T", "102", "26", + "MKK", "5G", "40M", "HT", "4T", "102", "26", + "FCC", "5G", "40M", "HT", "4T", "110", "26", + "ETSI", "5G", "40M", "HT", "4T", "110", "26", + "MKK", "5G", "40M", "HT", "4T", "110", "26", + "FCC", "5G", "40M", "HT", "4T", "118", "26", + "ETSI", "5G", "40M", "HT", "4T", "118", "26", + "MKK", "5G", "40M", "HT", "4T", "118", "26", + "FCC", "5G", "40M", "HT", "4T", "126", "26", + "ETSI", "5G", "40M", "HT", "4T", "126", "26", + "MKK", "5G", "40M", "HT", "4T", "126", "26", + "FCC", "5G", "40M", "HT", "4T", "134", "24", + "ETSI", "5G", "40M", "HT", "4T", "134", "26", + "MKK", "5G", "40M", "HT", "4T", "134", "26", + "FCC", "5G", "40M", "HT", "4T", "151", "20", + "ETSI", "5G", "40M", "HT", "4T", "151", "26", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "26", + "ETSI", "5G", "40M", "HT", "4T", "159", "26", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "24", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "24", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "24", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "32", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "26", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "22", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "22", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "22", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "24", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "20", + "ETSI", "5G", "80M", "VHT", "3T", "42", "28", + "MKK", "5G", "80M", "VHT", "3T", "42", "28", + "FCC", "5G", "80M", "VHT", "3T", "58", "20", + "ETSI", "5G", "80M", "VHT", "3T", "58", "28", + "MKK", "5G", "80M", "VHT", "3T", "58", "28", + "FCC", "5G", "80M", "VHT", "3T", "106", "20", + "ETSI", "5G", "80M", "VHT", "3T", "106", "28", + "MKK", "5G", "80M", "VHT", "3T", "106", "28", + "FCC", "5G", "80M", "VHT", "3T", "122", "28", + "ETSI", "5G", "80M", "VHT", "3T", "122", "28", + "MKK", "5G", "80M", "VHT", "3T", "122", "28", + "FCC", "5G", "80M", "VHT", "3T", "155", "20", + "ETSI", "5G", "80M", "VHT", "3T", "155", "28", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "18", + "ETSI", "5G", "80M", "VHT", "4T", "42", "26", + "MKK", "5G", "80M", "VHT", "4T", "42", "26", + "FCC", "5G", "80M", "VHT", "4T", "58", "18", + "ETSI", "5G", "80M", "VHT", "4T", "58", "26", + "MKK", "5G", "80M", "VHT", "4T", "58", "26", + "FCC", "5G", "80M", "VHT", "4T", "106", "18", + "ETSI", "5G", "80M", "VHT", "4T", "106", "26", + "MKK", "5G", "80M", "VHT", "4T", "106", "26", + "FCC", "5G", "80M", "VHT", "4T", "122", "26", + "ETSI", "5G", "80M", "VHT", "4T", "122", "26", + "MKK", "5G", "80M", "VHT", "4T", "122", "26", + "FCC", "5G", "80M", "VHT", "4T", "155", "18", + "ETSI", "5G", "80M", "VHT", "4T", "155", "26", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type1)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type1; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type1)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type1; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type2.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type2[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "42", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "42", + "MKK", "2.4G", "20M", "HT", "1T", "01", "42", + "FCC", "2.4G", "20M", "HT", "1T", "02", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "42", + "MKK", "2.4G", "20M", "HT", "1T", "02", "42", + "FCC", "2.4G", "20M", "HT", "1T", "03", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "42", + "MKK", "2.4G", "20M", "HT", "1T", "03", "42", + "FCC", "2.4G", "20M", "HT", "1T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "42", + "MKK", "2.4G", "20M", "HT", "1T", "04", "42", + "FCC", "2.4G", "20M", "HT", "1T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "42", + "MKK", "2.4G", "20M", "HT", "1T", "05", "42", + "FCC", "2.4G", "20M", "HT", "1T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "42", + "MKK", "2.4G", "20M", "HT", "1T", "06", "42", + "FCC", "2.4G", "20M", "HT", "1T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "42", + "MKK", "2.4G", "20M", "HT", "1T", "07", "42", + "FCC", "2.4G", "20M", "HT", "1T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "42", + "MKK", "2.4G", "20M", "HT", "1T", "08", "42", + "FCC", "2.4G", "20M", "HT", "1T", "09", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "42", + "MKK", "2.4G", "20M", "HT", "1T", "09", "42", + "FCC", "2.4G", "20M", "HT", "1T", "10", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "42", + "MKK", "2.4G", "20M", "HT", "1T", "10", "42", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "42", + "MKK", "2.4G", "20M", "HT", "1T", "11", "42", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "42", + "MKK", "2.4G", "20M", "HT", "1T", "12", "42", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "42", + "MKK", "2.4G", "20M", "HT", "1T", "13", "42", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", + "MKK", "2.4G", "20M", "HT", "2T", "01", "40", + "FCC", "2.4G", "20M", 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"HT", "2T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", + "MKK", "2.4G", "40M", "HT", "2T", "08", "34", + "FCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", + "MKK", "2.4G", "40M", "HT", "2T", "09", "34", + "FCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", + "MKK", "2.4G", "40M", "HT", "2T", "10", "34", + "FCC", "2.4G", "40M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", + "MKK", "2.4G", "40M", "HT", "2T", "11", "34", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", + "MKK", "2.4G", "40M", "HT", "2T", "12", "34", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", + "MKK", "2.4G", "40M", "HT", "2T", "13", "34", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", + "MKK", "2.4G", "40M", "HT", "3T", "03", "34", + "FCC", "2.4G", "40M", "HT", "3T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", + "MKK", "2.4G", "40M", "HT", "3T", "04", "34", + "FCC", "2.4G", "40M", "HT", "3T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", + "MKK", "2.4G", "40M", "HT", "3T", "05", "34", + "FCC", "2.4G", "40M", "HT", "3T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", + "MKK", "2.4G", "40M", "HT", "3T", "06", "34", + "FCC", "2.4G", "40M", "HT", "3T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", + "MKK", "2.4G", "40M", "HT", "3T", "07", "34", + "FCC", "2.4G", "40M", "HT", "3T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", + "MKK", "2.4G", "40M", "HT", "3T", "08", "34", + "FCC", "2.4G", "40M", "HT", "3T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", + "MKK", "2.4G", "40M", "HT", "3T", "09", "34", + "FCC", "2.4G", "40M", "HT", "3T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", + "MKK", "2.4G", "40M", "HT", "3T", "10", "34", + "FCC", "2.4G", "40M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", + "MKK", "2.4G", "40M", "HT", "3T", "11", "34", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", + "MKK", "2.4G", "40M", "HT", "3T", "12", "34", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", + "MKK", "2.4G", "40M", "HT", "3T", "13", "34", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", + "MKK", "2.4G", "40M", "HT", "4T", "03", "34", + "FCC", "2.4G", "40M", "HT", "4T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", + "MKK", "2.4G", "40M", "HT", "4T", "04", "34", + "FCC", "2.4G", "40M", "HT", "4T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", + "MKK", "2.4G", "40M", "HT", "4T", "05", "34", + "FCC", "2.4G", "40M", "HT", "4T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", + "MKK", "2.4G", "40M", "HT", "4T", "06", "34", + "FCC", "2.4G", "40M", "HT", "4T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", + "MKK", "2.4G", "40M", "HT", "4T", "07", "34", + "FCC", "2.4G", "40M", "HT", "4T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", + "MKK", "2.4G", "40M", "HT", "4T", "08", "34", + "FCC", "2.4G", "40M", "HT", "4T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", + "MKK", "2.4G", "40M", "HT", "4T", "09", "34", + "FCC", "2.4G", "40M", "HT", "4T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", + "MKK", "2.4G", "40M", "HT", "4T", "10", "34", + "FCC", "2.4G", "40M", "HT", "4T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", + "MKK", "2.4G", "40M", "HT", "4T", "11", "34", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", + "MKK", "2.4G", "40M", "HT", "4T", "12", "34", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", + "MKK", "2.4G", "40M", "HT", "4T", "13", "34", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "42", + "MKK", "5G", "20M", "OFDM", "1T", "36", "42", + "FCC", "5G", "20M", "OFDM", "1T", "40", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "42", + "MKK", "5G", "20M", "OFDM", "1T", "40", "42", + "FCC", "5G", "20M", "OFDM", "1T", "44", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "42", + "MKK", "5G", "20M", "OFDM", "1T", "44", "42", + "FCC", "5G", "20M", "OFDM", "1T", "48", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "42", + "MKK", "5G", "20M", "OFDM", "1T", "48", "42", + "FCC", "5G", "20M", "OFDM", "1T", "52", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "42", + "MKK", "5G", "20M", "OFDM", "1T", "52", "42", + "FCC", "5G", "20M", "OFDM", "1T", "56", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "42", + "MKK", "5G", "20M", "OFDM", "1T", "56", "42", + "FCC", "5G", "20M", "OFDM", "1T", "60", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "42", + "MKK", "5G", "20M", "OFDM", "1T", "60", "42", + "FCC", "5G", "20M", "OFDM", "1T", "64", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "42", + "MKK", "5G", "20M", "OFDM", "1T", "64", "42", + "FCC", "5G", "20M", "OFDM", "1T", "100", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "42", + "MKK", "5G", "20M", "OFDM", "1T", "100", "42", + "FCC", "5G", "20M", "OFDM", "1T", "104", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "42", + "MKK", "5G", "20M", "OFDM", "1T", "104", "42", + "FCC", "5G", "20M", "OFDM", "1T", "108", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "42", + "MKK", "5G", "20M", "OFDM", "1T", "108", "42", + "FCC", "5G", "20M", "OFDM", "1T", "112", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "42", + "MKK", "5G", "20M", "OFDM", "1T", "112", "42", + "FCC", "5G", "20M", "OFDM", "1T", "116", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "42", + "MKK", "5G", "20M", "OFDM", "1T", "116", "42", + "FCC", "5G", "20M", "OFDM", "1T", "120", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "42", + "MKK", "5G", "20M", "OFDM", "1T", "120", "42", + "FCC", "5G", "20M", "OFDM", "1T", "124", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "42", + "MKK", "5G", "20M", "OFDM", "1T", "124", "42", + "FCC", "5G", "20M", "OFDM", "1T", "128", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "42", + "MKK", "5G", "20M", "OFDM", "1T", "128", "42", + "FCC", "5G", "20M", "OFDM", "1T", "132", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "42", + "MKK", "5G", "20M", "OFDM", "1T", "132", "42", + "FCC", "5G", "20M", "OFDM", "1T", "136", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "42", + "MKK", "5G", "20M", "OFDM", "1T", "136", "42", + "FCC", "5G", "20M", "OFDM", "1T", "140", "40", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", + "MKK", "5G", "20M", "OFDM", "1T", "140", "40", + "FCC", "5G", "20M", "OFDM", "1T", "149", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "44", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "44", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "36", + "ETSI", "5G", "20M", "HT", "1T", "48", "36", + "MKK", "5G", "20M", "HT", "1T", "48", "36", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "36", + "MKK", "5G", "20M", "HT", "1T", "52", "36", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "32", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "30", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "40", + "ETSI", "5G", "20M", "HT", "1T", "149", "40", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "40", + "ETSI", "5G", "20M", "HT", "1T", "153", "40", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "40", + "ETSI", "5G", "20M", "HT", "1T", "157", "40", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "40", + "ETSI", "5G", "20M", "HT", "1T", "161", "40", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "42", + "ETSI", "5G", "20M", "HT", "1T", "165", "42", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "32", + "ETSI", "5G", "20M", "HT", "2T", "36", "32", + "MKK", "5G", "20M", "HT", "2T", "36", "32", + "FCC", "5G", "20M", "HT", "2T", "40", "32", + "ETSI", "5G", "20M", "HT", "2T", "40", "32", + "MKK", "5G", "20M", "HT", "2T", "40", "32", + "FCC", "5G", "20M", "HT", "2T", "44", "32", + "ETSI", "5G", "20M", "HT", "2T", "44", "32", + "MKK", "5G", "20M", "HT", "2T", "44", "32", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "36", + "MKK", "5G", "20M", "HT", "2T", "48", "36", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "36", + "MKK", "5G", "20M", "HT", "2T", "52", "36", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "32", + "MKK", "5G", "20M", "HT", "2T", "56", "32", + "FCC", "5G", "20M", "HT", "2T", "60", "32", + "ETSI", "5G", "20M", "HT", "2T", "60", "32", + "MKK", "5G", "20M", "HT", "2T", "60", "32", + "FCC", "5G", "20M", "HT", "2T", "64", "32", + "ETSI", "5G", "20M", "HT", "2T", "64", "32", + "MKK", "5G", "20M", "HT", "2T", "64", "32", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "32", + "MKK", "5G", "20M", "HT", "2T", "100", "32", + "FCC", "5G", "20M", "HT", "2T", "104", "32", + "ETSI", "5G", "20M", "HT", "2T", "104", "32", + "MKK", "5G", "20M", "HT", "2T", "104", "32", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "32", + "MKK", "5G", "20M", "HT", "2T", "108", "32", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "32", + "MKK", "5G", "20M", "HT", "2T", "112", "32", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "32", + "MKK", "5G", "20M", "HT", "2T", "116", "32", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "32", + "MKK", "5G", "20M", "HT", "2T", "120", "32", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "32", + "MKK", "5G", "20M", "HT", "2T", "124", "32", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "32", + "MKK", "5G", "20M", "HT", "2T", "128", "32", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "32", + "MKK", "5G", "20M", "HT", "2T", "132", "32", + "FCC", "5G", "20M", "HT", "2T", "136", "32", + "ETSI", "5G", "20M", "HT", "2T", "136", "32", + "MKK", "5G", "20M", "HT", "2T", "136", "32", + "FCC", "5G", "20M", "HT", "2T", "140", "30", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "40", + "ETSI", "5G", "20M", "HT", "2T", "149", "40", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "40", + "ETSI", "5G", "20M", "HT", "2T", "153", "40", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "40", + "ETSI", "5G", "20M", "HT", "2T", "157", "40", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "40", + "ETSI", "5G", "20M", "HT", "2T", "161", "40", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "42", + "ETSI", "5G", "20M", "HT", "2T", "165", "42", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "32", + "ETSI", "5G", "20M", "HT", "3T", "36", "32", + "MKK", "5G", "20M", "HT", "3T", "36", "32", + "FCC", "5G", "20M", "HT", "3T", "40", "32", + "ETSI", "5G", "20M", "HT", "3T", "40", "32", + "MKK", "5G", "20M", "HT", "3T", "40", "32", + "FCC", "5G", "20M", "HT", "3T", "44", "32", + "ETSI", "5G", "20M", "HT", "3T", "44", "32", + "MKK", "5G", "20M", "HT", "3T", "44", "32", + "FCC", "5G", "20M", "HT", "3T", "48", "36", + "ETSI", "5G", "20M", "HT", "3T", "48", "36", + "MKK", "5G", "20M", "HT", "3T", "48", "36", + "FCC", "5G", "20M", "HT", "3T", "52", "36", + "ETSI", "5G", "20M", "HT", "3T", "52", "36", + "MKK", "5G", "20M", "HT", "3T", "52", "36", + "FCC", "5G", "20M", "HT", "3T", "56", "32", + "ETSI", "5G", "20M", "HT", "3T", "56", "32", + "MKK", "5G", "20M", "HT", "3T", "56", "32", + "FCC", "5G", "20M", "HT", "3T", "60", "32", + "ETSI", "5G", "20M", "HT", "3T", "60", "32", + "MKK", "5G", "20M", "HT", "3T", "60", "32", + "FCC", "5G", "20M", "HT", "3T", "64", "32", + "ETSI", "5G", "20M", "HT", "3T", "64", "32", + "MKK", "5G", "20M", "HT", "3T", "64", "32", + "FCC", "5G", "20M", "HT", "3T", "100", "32", + "ETSI", "5G", "20M", "HT", "3T", "100", "32", + "MKK", "5G", "20M", "HT", "3T", "100", "32", + "FCC", "5G", "20M", "HT", "3T", "104", "32", + "ETSI", "5G", "20M", "HT", "3T", "104", "32", + "MKK", "5G", "20M", "HT", "3T", "104", "32", + "FCC", "5G", "20M", "HT", "3T", "108", "32", + "ETSI", "5G", "20M", "HT", "3T", "108", "32", + "MKK", "5G", "20M", "HT", "3T", "108", "32", + "FCC", "5G", "20M", "HT", "3T", "112", "32", + "ETSI", "5G", "20M", "HT", "3T", "112", "32", + "MKK", "5G", "20M", "HT", "3T", "112", "32", + "FCC", "5G", "20M", "HT", "3T", "116", "32", + "ETSI", "5G", "20M", "HT", "3T", "116", "32", + "MKK", "5G", "20M", "HT", "3T", "116", "32", + "FCC", "5G", "20M", "HT", "3T", "120", "32", + "ETSI", "5G", "20M", "HT", "3T", "120", "32", + "MKK", "5G", "20M", "HT", "3T", "120", "32", + "FCC", "5G", "20M", "HT", "3T", "124", "32", + "ETSI", "5G", "20M", "HT", "3T", "124", "32", + "MKK", "5G", "20M", "HT", "3T", "124", "32", + "FCC", "5G", "20M", "HT", "3T", "128", "32", + "ETSI", "5G", "20M", "HT", "3T", "128", "32", + "MKK", "5G", "20M", "HT", "3T", "128", "32", + "FCC", "5G", "20M", "HT", "3T", "132", "32", + "ETSI", "5G", "20M", "HT", "3T", "132", "32", + "MKK", "5G", "20M", "HT", "3T", "132", "32", + "FCC", "5G", "20M", "HT", "3T", "136", "32", + "ETSI", "5G", "20M", "HT", "3T", "136", "32", + "MKK", "5G", "20M", "HT", "3T", "136", "32", + "FCC", "5G", "20M", "HT", "3T", "140", "30", + "ETSI", "5G", "20M", "HT", "3T", "140", "30", + "MKK", "5G", "20M", "HT", "3T", "140", "30", + "FCC", "5G", "20M", "HT", "3T", "149", "40", + "ETSI", "5G", "20M", "HT", "3T", "149", "40", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "40", + "ETSI", "5G", "20M", "HT", "3T", "153", "40", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "40", + "ETSI", "5G", "20M", "HT", "3T", "157", "40", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "40", + "ETSI", "5G", "20M", "HT", "3T", "161", "40", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "42", + "ETSI", "5G", "20M", "HT", "3T", "165", "42", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "32", + "ETSI", "5G", "20M", "HT", "4T", "36", "32", + "MKK", "5G", "20M", "HT", "4T", "36", "32", + "FCC", "5G", "20M", "HT", "4T", "40", "32", + "ETSI", "5G", "20M", "HT", "4T", "40", "32", + "MKK", "5G", "20M", "HT", "4T", "40", "32", + "FCC", "5G", "20M", "HT", "4T", "44", "32", + "ETSI", "5G", "20M", "HT", "4T", "44", "32", + "MKK", "5G", "20M", "HT", "4T", "44", "32", + "FCC", "5G", "20M", "HT", "4T", "48", "36", + "ETSI", "5G", "20M", "HT", "4T", "48", "36", + "MKK", "5G", "20M", "HT", "4T", "48", "36", + "FCC", "5G", "20M", "HT", "4T", "52", "36", + "ETSI", "5G", "20M", "HT", "4T", "52", "36", + "MKK", "5G", "20M", "HT", "4T", "52", "36", + "FCC", "5G", "20M", "HT", "4T", "56", "32", + "ETSI", "5G", "20M", "HT", "4T", "56", "32", + "MKK", "5G", "20M", "HT", "4T", "56", "32", + "FCC", "5G", "20M", "HT", "4T", "60", "32", + "ETSI", "5G", "20M", "HT", "4T", "60", "32", + "MKK", "5G", "20M", "HT", "4T", "60", "32", + "FCC", "5G", "20M", "HT", "4T", "64", "32", + "ETSI", "5G", "20M", "HT", "4T", "64", "32", + "MKK", "5G", "20M", "HT", "4T", "64", "32", + "FCC", "5G", "20M", "HT", "4T", "100", "32", + "ETSI", "5G", "20M", "HT", "4T", "100", "32", + "MKK", "5G", "20M", "HT", "4T", "100", "32", + "FCC", "5G", "20M", "HT", "4T", "104", "32", + "ETSI", "5G", "20M", "HT", "4T", "104", "32", + "MKK", "5G", "20M", "HT", "4T", "104", "32", + "FCC", "5G", "20M", "HT", "4T", "108", "32", + "ETSI", "5G", "20M", "HT", "4T", "108", "32", + "MKK", "5G", "20M", "HT", "4T", "108", "32", + "FCC", "5G", "20M", "HT", "4T", "112", "32", + "ETSI", "5G", "20M", "HT", "4T", "112", "32", + "MKK", "5G", "20M", "HT", "4T", "112", "32", + "FCC", "5G", "20M", "HT", "4T", "116", "32", + "ETSI", "5G", "20M", "HT", "4T", "116", "32", + "MKK", "5G", "20M", "HT", "4T", "116", "32", + "FCC", "5G", "20M", "HT", "4T", "120", "32", + "ETSI", "5G", "20M", "HT", "4T", "120", "32", + "MKK", "5G", "20M", "HT", "4T", "120", "32", + "FCC", "5G", "20M", "HT", "4T", "124", "32", + "ETSI", "5G", "20M", "HT", "4T", "124", "32", + "MKK", "5G", "20M", "HT", "4T", "124", "32", + "FCC", "5G", "20M", "HT", "4T", "128", "32", + "ETSI", "5G", "20M", "HT", "4T", "128", "32", + "MKK", "5G", "20M", "HT", "4T", "128", "32", + "FCC", "5G", "20M", "HT", "4T", "132", "32", + "ETSI", "5G", "20M", "HT", "4T", "132", "32", + "MKK", "5G", "20M", "HT", "4T", "132", "32", + "FCC", "5G", "20M", "HT", "4T", "136", "32", + "ETSI", "5G", "20M", "HT", "4T", "136", "32", + "MKK", "5G", "20M", "HT", "4T", "136", "32", + "FCC", "5G", "20M", "HT", "4T", "140", "30", + "ETSI", "5G", "20M", "HT", "4T", "140", "30", + "MKK", "5G", "20M", "HT", "4T", "140", "30", + "FCC", "5G", "20M", "HT", "4T", "149", "40", + "ETSI", "5G", "20M", "HT", "4T", "149", "40", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "40", + "ETSI", "5G", "20M", "HT", "4T", "153", "40", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "40", + "ETSI", "5G", "20M", "HT", "4T", "157", "40", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "40", + "ETSI", "5G", "20M", "HT", "4T", "161", "40", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "42", + "ETSI", "5G", "20M", "HT", "4T", "165", "42", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "32", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "36", + "MKK", "5G", "40M", "HT", "1T", "46", "36", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "36", + "MKK", "5G", "40M", "HT", "1T", "54", "36", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "36", + "MKK", "5G", "40M", "HT", "1T", "134", "36", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "36", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "40", + "ETSI", "5G", "40M", "HT", "1T", "159", "40", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "32", + "ETSI", "5G", "40M", "HT", "2T", "38", "32", + "MKK", "5G", "40M", "HT", "2T", "38", "32", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "36", + "MKK", "5G", "40M", "HT", "2T", "46", "36", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "36", + "MKK", "5G", "40M", "HT", "2T", "54", "36", + "FCC", "5G", "40M", "HT", "2T", "62", "32", + "ETSI", "5G", "40M", "HT", "2T", "62", "32", + "MKK", "5G", "40M", "HT", "2T", "62", "32", + "FCC", "5G", "40M", "HT", "2T", "102", "30", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "32", + "ETSI", "5G", "40M", "HT", "2T", "110", "32", + "MKK", "5G", "40M", "HT", "2T", "110", "32", + "FCC", "5G", "40M", "HT", "2T", "118", "32", + "ETSI", "5G", "40M", "HT", "2T", "118", "32", + "MKK", "5G", "40M", "HT", "2T", "118", "32", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "32", + "MKK", "5G", "40M", "HT", "2T", "126", "32", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "36", + "MKK", "5G", "40M", "HT", "2T", "134", "36", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "36", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "40", + "ETSI", "5G", "40M", "HT", "2T", "159", "40", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "32", + "ETSI", "5G", "40M", "HT", "3T", "38", "32", + "MKK", "5G", "40M", "HT", "3T", "38", "32", + "FCC", "5G", "40M", "HT", "3T", "46", "36", + "ETSI", "5G", "40M", "HT", "3T", "46", "36", + "MKK", "5G", "40M", "HT", "3T", "46", "36", + "FCC", "5G", "40M", "HT", "3T", "54", "36", + "ETSI", "5G", "40M", "HT", "3T", "54", "36", + "MKK", "5G", "40M", "HT", "3T", "54", "36", + "FCC", "5G", "40M", "HT", "3T", "62", "32", + "ETSI", "5G", "40M", "HT", "3T", "62", "32", + "MKK", "5G", "40M", "HT", "3T", "62", "32", + "FCC", "5G", "40M", "HT", "3T", "102", "30", + "ETSI", "5G", "40M", "HT", "3T", "102", "30", + "MKK", "5G", "40M", "HT", "3T", "102", "30", + "FCC", "5G", "40M", "HT", "3T", "110", "32", + "ETSI", "5G", "40M", "HT", "3T", "110", "32", + "MKK", "5G", "40M", "HT", "3T", "110", "32", + "FCC", "5G", "40M", "HT", "3T", "118", "32", + "ETSI", "5G", "40M", "HT", "3T", "118", "32", + "MKK", "5G", "40M", "HT", "3T", "118", "32", + "FCC", "5G", "40M", "HT", "3T", "126", "32", + "ETSI", "5G", "40M", "HT", "3T", "126", "32", + "MKK", "5G", "40M", "HT", "3T", "126", "32", + "FCC", "5G", "40M", "HT", "3T", "134", "36", + "ETSI", "5G", "40M", "HT", "3T", "134", "36", + "MKK", "5G", "40M", "HT", "3T", "134", "36", + "FCC", "5G", "40M", "HT", "3T", "151", "36", + "ETSI", "5G", "40M", "HT", "3T", "151", "36", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "40", + "ETSI", "5G", "40M", "HT", "3T", "159", "40", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "32", + "ETSI", "5G", "40M", "HT", "4T", "38", "32", + "MKK", "5G", "40M", "HT", "4T", "38", "32", + "FCC", "5G", "40M", "HT", "4T", "46", "36", + "ETSI", "5G", "40M", "HT", "4T", "46", "36", + "MKK", "5G", "40M", "HT", "4T", "46", "36", + "FCC", "5G", "40M", "HT", "4T", "54", "36", + "ETSI", "5G", "40M", "HT", "4T", "54", "36", + "MKK", "5G", "40M", "HT", "4T", "54", "36", + "FCC", "5G", "40M", "HT", "4T", "62", "32", + "ETSI", "5G", "40M", "HT", "4T", "62", "32", + "MKK", "5G", "40M", "HT", "4T", "62", "32", + "FCC", "5G", "40M", "HT", "4T", "102", "30", + "ETSI", "5G", "40M", "HT", "4T", "102", "30", + "MKK", "5G", "40M", "HT", "4T", "102", "30", + "FCC", "5G", "40M", "HT", "4T", "110", "32", + "ETSI", "5G", "40M", "HT", "4T", "110", "32", + "MKK", "5G", "40M", "HT", "4T", "110", "32", + "FCC", "5G", "40M", "HT", "4T", "118", "32", + "ETSI", "5G", "40M", "HT", "4T", "118", "32", + "MKK", "5G", "40M", "HT", "4T", "118", "32", + "FCC", "5G", "40M", "HT", "4T", "126", "32", + "ETSI", "5G", "40M", "HT", "4T", "126", "32", + "MKK", "5G", "40M", "HT", "4T", "126", "32", + "FCC", "5G", "40M", "HT", "4T", "134", "36", + "ETSI", "5G", "40M", "HT", "4T", "134", "36", + "MKK", "5G", "40M", "HT", "4T", "134", "36", + "FCC", "5G", "40M", "HT", "4T", "151", "36", + "ETSI", "5G", "40M", "HT", "4T", "151", "36", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "40", + "ETSI", "5G", "40M", "HT", "4T", "159", "40", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "34", + "ETSI", "5G", "80M", "VHT", "1T", "42", "34", + "MKK", "5G", "80M", "VHT", "1T", "42", "34", + "FCC", "5G", "80M", "VHT", "1T", "58", "34", + "ETSI", "5G", "80M", "VHT", "1T", "58", "34", + "MKK", "5G", "80M", "VHT", "1T", "58", "34", + "FCC", "5G", "80M", "VHT", "1T", "106", "32", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "34", + "MKK", "5G", "80M", "VHT", "1T", "122", "34", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "34", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "34", + "ETSI", "5G", "80M", "VHT", "2T", "42", "34", + "MKK", "5G", "80M", "VHT", "2T", "42", "34", + "FCC", "5G", "80M", "VHT", "2T", "58", "34", + "ETSI", "5G", "80M", "VHT", "2T", "58", "34", + "MKK", "5G", "80M", "VHT", "2T", "58", "34", + "FCC", "5G", "80M", "VHT", "2T", "106", "32", + "ETSI", "5G", "80M", "VHT", "2T", "106", "32", + "MKK", "5G", "80M", "VHT", "2T", "106", "32", + "FCC", "5G", "80M", "VHT", "2T", "122", "34", + "ETSI", "5G", "80M", "VHT", "2T", "122", "34", + "MKK", "5G", "80M", "VHT", "2T", "122", "34", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "34", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "34", + "ETSI", "5G", "80M", "VHT", "3T", "42", "34", + "MKK", "5G", "80M", "VHT", "3T", "42", "34", + "FCC", "5G", "80M", "VHT", "3T", "58", "34", + "ETSI", "5G", "80M", "VHT", "3T", "58", "34", + "MKK", "5G", "80M", "VHT", "3T", "58", "34", + "FCC", "5G", "80M", "VHT", "3T", "106", "32", + "ETSI", "5G", "80M", "VHT", "3T", "106", "32", + "MKK", "5G", "80M", "VHT", "3T", "106", "32", + "FCC", "5G", "80M", "VHT", "3T", "122", "34", + "ETSI", "5G", "80M", "VHT", "3T", "122", "34", + "MKK", "5G", "80M", "VHT", "3T", "122", "34", + "FCC", "5G", "80M", "VHT", "3T", "155", "34", + "ETSI", "5G", "80M", "VHT", "3T", "155", "34", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "34", + "ETSI", "5G", "80M", "VHT", "4T", "42", "34", + "MKK", "5G", "80M", "VHT", "4T", "42", "34", + "FCC", "5G", "80M", "VHT", "4T", "58", "34", + "ETSI", "5G", "80M", "VHT", "4T", "58", "34", + "MKK", "5G", "80M", "VHT", "4T", "58", "34", + "FCC", "5G", "80M", "VHT", "4T", "106", "32", + "ETSI", "5G", "80M", "VHT", "4T", "106", "32", + "MKK", "5G", "80M", "VHT", "4T", "106", "32", + "FCC", "5G", "80M", "VHT", "4T", "122", "34", + "ETSI", "5G", "80M", "VHT", "4T", "122", "34", + "MKK", "5G", "80M", "VHT", "4T", "122", "34", + "FCC", "5G", "80M", "VHT", "4T", "155", "34", + "ETSI", "5G", "80M", "VHT", "4T", "155", "34", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type2)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type2; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type2)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type2; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type3.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type3[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", + "MKK", "2.4G", "20M", "HT", "1T", "01", "40", + "FCC", "2.4G", "20M", "HT", "1T", "02", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", + "MKK", "2.4G", "20M", "HT", "1T", "02", "40", + "FCC", "2.4G", "20M", "HT", "1T", "03", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", + "MKK", "2.4G", "20M", "HT", "1T", "03", "40", + "FCC", "2.4G", "20M", "HT", "1T", "04", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", + "MKK", "2.4G", "20M", "HT", "1T", "04", "40", + "FCC", "2.4G", "20M", "HT", "1T", "05", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "05", 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"46", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "40", + "MKK", "2.4G", "40M", "HT", "3T", "04", "40", + "FCC", "2.4G", "40M", "HT", "3T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "40", + "MKK", "2.4G", "40M", "HT", "3T", "05", "40", + "FCC", "2.4G", "40M", "HT", "3T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "40", + "MKK", "2.4G", "40M", "HT", "3T", "06", "40", + "FCC", "2.4G", "40M", "HT", "3T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "40", + "MKK", "2.4G", "40M", "HT", "3T", "07", "40", + "FCC", "2.4G", "40M", "HT", "3T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "40", + "MKK", "2.4G", "40M", "HT", "3T", "08", "40", + "FCC", "2.4G", "40M", "HT", "3T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "40", + "MKK", "2.4G", "40M", "HT", "3T", "09", "40", + "FCC", "2.4G", "40M", "HT", "3T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "40", + "MKK", "2.4G", "40M", "HT", "3T", "10", "40", + "FCC", "2.4G", "40M", "HT", "3T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "40", + "MKK", "2.4G", "40M", "HT", "3T", "11", "40", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "40", + "MKK", "2.4G", "40M", "HT", "3T", "12", "40", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "40", + "MKK", "2.4G", "40M", "HT", "3T", "13", "40", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "40", + "MKK", "2.4G", "40M", "HT", "4T", "03", "40", + "FCC", "2.4G", "40M", "HT", "4T", "04", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "40", + "MKK", "2.4G", "40M", "HT", "4T", "04", "40", + "FCC", "2.4G", "40M", "HT", "4T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "40", + "MKK", "2.4G", "40M", "HT", "4T", "05", "40", + "FCC", "2.4G", "40M", "HT", "4T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "40", + "MKK", "2.4G", "40M", "HT", "4T", "06", "40", + "FCC", "2.4G", "40M", "HT", "4T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "40", + "MKK", "2.4G", "40M", "HT", "4T", "07", "40", + "FCC", "2.4G", "40M", "HT", "4T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "40", + "MKK", "2.4G", "40M", "HT", "4T", "08", "40", + "FCC", "2.4G", "40M", "HT", "4T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "40", + "MKK", "2.4G", "40M", "HT", "4T", "09", "40", + "FCC", "2.4G", "40M", "HT", "4T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "40", + "MKK", "2.4G", "40M", "HT", "4T", "10", "40", + "FCC", "2.4G", "40M", "HT", "4T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "40", + "MKK", "2.4G", "40M", "HT", "4T", "11", "40", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "40", + "MKK", "2.4G", "40M", "HT", "4T", "12", "40", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "40", + "MKK", "2.4G", "40M", "HT", "4T", "13", "40", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "40", + "MKK", "5G", "20M", "OFDM", "1T", "36", "40", + "FCC", "5G", "20M", "OFDM", "1T", "40", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "40", + "MKK", "5G", "20M", "OFDM", "1T", "40", "40", + "FCC", "5G", "20M", "OFDM", "1T", "44", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "40", + "MKK", "5G", "20M", "OFDM", "1T", "44", "40", + "FCC", "5G", "20M", "OFDM", "1T", "48", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "40", + "MKK", "5G", "20M", "OFDM", "1T", "48", "40", + "FCC", "5G", "20M", "OFDM", "1T", "52", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "40", + "MKK", "5G", "20M", "OFDM", "1T", "52", "40", + "FCC", "5G", "20M", "OFDM", "1T", "56", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "40", + "MKK", "5G", "20M", "OFDM", "1T", "56", "40", + "FCC", "5G", "20M", "OFDM", "1T", "60", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "40", + "MKK", "5G", "20M", "OFDM", "1T", "60", "40", + "FCC", "5G", "20M", "OFDM", "1T", "64", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", + "MKK", "5G", "20M", "OFDM", "1T", "64", "40", + "FCC", "5G", "20M", "OFDM", "1T", "100", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", + "MKK", "5G", "20M", "OFDM", "1T", "100", "40", + "FCC", "5G", "20M", "OFDM", "1T", "104", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "40", + "MKK", "5G", "20M", "OFDM", "1T", "104", "40", + "FCC", "5G", "20M", "OFDM", "1T", "108", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "40", + "MKK", "5G", "20M", "OFDM", "1T", "108", "40", + "FCC", "5G", "20M", "OFDM", "1T", "112", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "40", + "MKK", "5G", "20M", "OFDM", "1T", "112", "40", + "FCC", "5G", "20M", "OFDM", "1T", "116", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "40", + "MKK", "5G", "20M", "OFDM", "1T", "116", "40", + "FCC", "5G", "20M", "OFDM", "1T", "120", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "40", + "MKK", "5G", "20M", "OFDM", "1T", "120", "40", + "FCC", "5G", "20M", "OFDM", "1T", "124", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "40", + "MKK", "5G", "20M", "OFDM", "1T", "124", "40", + "FCC", "5G", "20M", "OFDM", "1T", "128", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "40", + "MKK", "5G", "20M", "OFDM", "1T", "128", "40", + "FCC", "5G", "20M", "OFDM", "1T", "132", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "40", + "MKK", "5G", "20M", "OFDM", "1T", "132", "40", + "FCC", "5G", "20M", "OFDM", "1T", "136", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "40", + "MKK", "5G", "20M", "OFDM", "1T", "136", "40", + "FCC", "5G", "20M", "OFDM", "1T", "140", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", + "MKK", "5G", "20M", "OFDM", "1T", "140", "40", + "FCC", "5G", "20M", "OFDM", "1T", "149", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "40", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "40", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "40", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "40", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "40", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "46", + "ETSI", "5G", "20M", "HT", "1T", "36", "40", + "MKK", "5G", "20M", "HT", "1T", "36", "40", + "FCC", "5G", "20M", "HT", "1T", "40", "46", + "ETSI", "5G", "20M", "HT", "1T", "40", "40", + "MKK", "5G", "20M", "HT", "1T", "40", "40", + "FCC", "5G", "20M", "HT", "1T", "44", "46", + "ETSI", "5G", "20M", "HT", "1T", "44", "40", + "MKK", "5G", "20M", "HT", "1T", "44", "40", + "FCC", "5G", "20M", "HT", "1T", "48", "46", + "ETSI", "5G", "20M", "HT", "1T", "48", "40", + "MKK", "5G", "20M", "HT", "1T", "48", "40", + "FCC", "5G", "20M", "HT", "1T", "52", "46", + "ETSI", "5G", "20M", "HT", "1T", "52", "40", + "MKK", "5G", "20M", "HT", "1T", "52", "40", + "FCC", "5G", "20M", "HT", "1T", "56", "46", + "ETSI", "5G", "20M", "HT", "1T", "56", "40", + "MKK", "5G", "20M", "HT", "1T", "56", "40", + "FCC", "5G", "20M", "HT", "1T", "60", "46", + "ETSI", "5G", "20M", "HT", "1T", "60", "40", + "MKK", "5G", "20M", "HT", "1T", "60", "40", + "FCC", "5G", "20M", "HT", "1T", "64", "46", + "ETSI", "5G", "20M", "HT", "1T", "64", "40", + "MKK", "5G", "20M", "HT", "1T", "64", "40", + "FCC", "5G", "20M", "HT", "1T", "100", "46", + "ETSI", "5G", "20M", "HT", "1T", "100", "40", + "MKK", "5G", "20M", "HT", "1T", "100", "40", + "FCC", "5G", "20M", "HT", "1T", "104", "46", + "ETSI", "5G", "20M", "HT", "1T", "104", "40", + "MKK", "5G", "20M", "HT", "1T", "104", "40", + "FCC", "5G", "20M", "HT", "1T", "108", "46", + "ETSI", "5G", "20M", "HT", "1T", "108", "40", + "MKK", "5G", "20M", "HT", "1T", "108", "40", + "FCC", "5G", "20M", "HT", "1T", "112", "46", + "ETSI", "5G", "20M", "HT", "1T", "112", "40", + "MKK", "5G", "20M", "HT", "1T", "112", "40", + "FCC", "5G", "20M", "HT", "1T", "116", "46", + "ETSI", "5G", "20M", "HT", "1T", "116", "40", + "MKK", "5G", "20M", "HT", "1T", "116", "40", + "FCC", "5G", "20M", "HT", "1T", "120", "46", + "ETSI", "5G", "20M", "HT", "1T", "120", "40", + "MKK", "5G", "20M", "HT", "1T", "120", "40", + "FCC", "5G", "20M", "HT", "1T", "124", "46", + "ETSI", "5G", "20M", "HT", "1T", "124", "40", + "MKK", "5G", "20M", "HT", "1T", "124", "40", + "FCC", "5G", "20M", "HT", "1T", "128", "46", + "ETSI", "5G", "20M", "HT", "1T", "128", "40", + "MKK", "5G", "20M", "HT", "1T", "128", "40", + "FCC", "5G", "20M", "HT", "1T", "132", "46", + "ETSI", "5G", "20M", "HT", "1T", "132", "40", + "MKK", "5G", "20M", "HT", "1T", "132", "40", + "FCC", "5G", "20M", "HT", "1T", "136", "46", + "ETSI", "5G", "20M", "HT", "1T", "136", "40", + "MKK", "5G", "20M", "HT", "1T", "136", "40", + "FCC", "5G", "20M", "HT", "1T", "140", "46", + "ETSI", "5G", "20M", "HT", "1T", "140", "40", + "MKK", "5G", "20M", "HT", "1T", "140", "40", + "FCC", "5G", "20M", "HT", "1T", "149", "46", + "ETSI", "5G", "20M", "HT", "1T", "149", "40", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "46", + "ETSI", "5G", "20M", "HT", "1T", "153", "40", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "46", + "ETSI", "5G", "20M", "HT", "1T", "157", "40", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "46", + "ETSI", "5G", "20M", "HT", "1T", "161", "40", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "46", + "ETSI", "5G", "20M", "HT", "1T", "165", "40", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "46", + "ETSI", "5G", "20M", "HT", "2T", "36", "40", + "MKK", "5G", "20M", "HT", "2T", "36", "40", + "FCC", "5G", "20M", "HT", "2T", "40", "46", + "ETSI", "5G", "20M", "HT", "2T", "40", "40", + "MKK", "5G", "20M", "HT", "2T", "40", "40", + "FCC", "5G", "20M", "HT", "2T", "44", "46", + "ETSI", "5G", "20M", "HT", "2T", "44", "40", + "MKK", "5G", "20M", "HT", "2T", "44", "40", + "FCC", "5G", "20M", "HT", "2T", "48", "46", + "ETSI", "5G", "20M", "HT", "2T", "48", "40", + "MKK", "5G", "20M", "HT", "2T", "48", "40", + "FCC", "5G", "20M", "HT", "2T", "52", "46", + "ETSI", "5G", "20M", "HT", "2T", "52", "40", + "MKK", "5G", "20M", "HT", "2T", "52", "40", + "FCC", "5G", "20M", "HT", "2T", "56", "46", + "ETSI", "5G", "20M", "HT", "2T", "56", "40", + "MKK", "5G", "20M", "HT", "2T", "56", "40", + "FCC", "5G", "20M", "HT", "2T", "60", "46", + "ETSI", "5G", "20M", "HT", "2T", "60", "40", + "MKK", "5G", "20M", "HT", "2T", "60", "40", + "FCC", "5G", "20M", "HT", "2T", "64", "46", + "ETSI", "5G", "20M", "HT", "2T", "64", "40", + "MKK", "5G", "20M", "HT", "2T", "64", "40", + "FCC", "5G", "20M", "HT", "2T", "100", "46", + "ETSI", "5G", "20M", "HT", "2T", "100", "40", + "MKK", "5G", "20M", "HT", "2T", "100", "40", + "FCC", "5G", "20M", "HT", "2T", "104", "46", + "ETSI", "5G", "20M", "HT", "2T", "104", "40", + "MKK", "5G", "20M", "HT", "2T", "104", "40", + "FCC", "5G", "20M", "HT", "2T", "108", "46", + "ETSI", "5G", "20M", "HT", "2T", "108", "40", + "MKK", "5G", "20M", "HT", "2T", "108", "40", + "FCC", "5G", "20M", "HT", "2T", "112", "46", + "ETSI", "5G", "20M", "HT", "2T", "112", "40", + "MKK", "5G", "20M", "HT", "2T", "112", "40", + "FCC", "5G", "20M", "HT", "2T", "116", "46", + "ETSI", "5G", "20M", "HT", "2T", "116", "40", + "MKK", "5G", "20M", "HT", "2T", "116", "40", + "FCC", "5G", "20M", "HT", "2T", "120", "46", + "ETSI", "5G", "20M", "HT", "2T", "120", "40", + "MKK", "5G", "20M", "HT", "2T", "120", "40", + "FCC", "5G", "20M", "HT", "2T", "124", "46", + "ETSI", "5G", "20M", "HT", "2T", "124", "40", + "MKK", "5G", "20M", "HT", "2T", "124", "40", + "FCC", "5G", "20M", "HT", "2T", "128", "46", + "ETSI", "5G", "20M", "HT", "2T", "128", "40", + "MKK", "5G", "20M", "HT", "2T", "128", "40", + "FCC", "5G", "20M", "HT", "2T", "132", "46", + "ETSI", "5G", "20M", "HT", "2T", "132", "40", + "MKK", "5G", "20M", "HT", "2T", "132", "40", + "FCC", "5G", "20M", "HT", "2T", "136", "46", + "ETSI", "5G", "20M", "HT", "2T", "136", "40", + "MKK", "5G", "20M", "HT", "2T", "136", "40", + "FCC", "5G", "20M", "HT", "2T", "140", "46", + "ETSI", "5G", "20M", "HT", "2T", "140", "40", + "MKK", "5G", "20M", "HT", "2T", "140", "40", + "FCC", "5G", "20M", "HT", "2T", "149", "46", + "ETSI", "5G", "20M", "HT", "2T", "149", "40", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "46", + "ETSI", "5G", "20M", "HT", "2T", "153", "40", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "46", + "ETSI", "5G", "20M", "HT", "2T", "157", "40", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "46", + "ETSI", "5G", "20M", "HT", "2T", "161", "40", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "46", + "ETSI", "5G", "20M", "HT", "2T", "165", "40", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "46", + "ETSI", "5G", "20M", "HT", "3T", "36", "40", + "MKK", "5G", "20M", "HT", "3T", "36", "40", + "FCC", "5G", "20M", "HT", "3T", "40", "46", + "ETSI", "5G", "20M", "HT", "3T", "40", "40", + "MKK", "5G", "20M", "HT", "3T", "40", "40", + "FCC", "5G", "20M", "HT", "3T", "44", "46", + "ETSI", "5G", "20M", "HT", "3T", "44", "40", + "MKK", "5G", "20M", "HT", "3T", "44", "40", + "FCC", "5G", "20M", "HT", "3T", "48", "46", + "ETSI", "5G", "20M", "HT", "3T", "48", "40", + "MKK", "5G", "20M", "HT", "3T", "48", "40", + "FCC", "5G", "20M", "HT", "3T", "52", "46", + "ETSI", "5G", "20M", "HT", "3T", "52", "40", + "MKK", "5G", "20M", "HT", "3T", "52", "40", + "FCC", "5G", "20M", "HT", "3T", "56", "46", + "ETSI", "5G", "20M", "HT", "3T", "56", "40", + "MKK", "5G", "20M", "HT", "3T", "56", "40", + "FCC", "5G", "20M", "HT", "3T", "60", "46", + "ETSI", "5G", "20M", "HT", "3T", "60", "40", + "MKK", "5G", "20M", "HT", "3T", "60", "40", + "FCC", "5G", "20M", "HT", "3T", "64", "46", + "ETSI", "5G", "20M", "HT", "3T", "64", "40", + "MKK", "5G", "20M", "HT", "3T", "64", "40", + "FCC", "5G", "20M", "HT", "3T", "100", "46", + "ETSI", "5G", "20M", "HT", "3T", "100", "40", + "MKK", "5G", "20M", "HT", "3T", "100", "40", + "FCC", "5G", "20M", "HT", "3T", "104", "46", + "ETSI", "5G", "20M", "HT", "3T", "104", "40", + "MKK", "5G", "20M", "HT", "3T", "104", "40", + "FCC", "5G", "20M", "HT", "3T", "108", "46", + "ETSI", "5G", "20M", "HT", "3T", "108", "40", + "MKK", "5G", "20M", "HT", "3T", "108", "40", + "FCC", "5G", "20M", "HT", "3T", "112", "46", + "ETSI", "5G", "20M", "HT", "3T", "112", "40", + "MKK", "5G", "20M", "HT", "3T", "112", "40", + "FCC", "5G", "20M", "HT", "3T", "116", "46", + "ETSI", "5G", "20M", "HT", "3T", "116", "40", + "MKK", "5G", "20M", "HT", "3T", "116", "40", + "FCC", "5G", "20M", "HT", "3T", "120", "46", + "ETSI", "5G", "20M", "HT", "3T", "120", "40", + "MKK", "5G", "20M", "HT", "3T", "120", "40", + "FCC", "5G", "20M", "HT", "3T", "124", "46", + "ETSI", "5G", "20M", "HT", "3T", "124", "40", + "MKK", "5G", "20M", "HT", "3T", "124", "40", + "FCC", "5G", "20M", "HT", "3T", "128", "46", + "ETSI", "5G", "20M", "HT", "3T", "128", "40", + "MKK", "5G", "20M", "HT", "3T", "128", "40", + "FCC", "5G", "20M", "HT", "3T", "132", "46", + "ETSI", "5G", "20M", "HT", "3T", "132", "40", + "MKK", "5G", "20M", "HT", "3T", "132", "40", + "FCC", "5G", "20M", "HT", "3T", "136", "46", + "ETSI", "5G", "20M", "HT", "3T", "136", "40", + "MKK", "5G", "20M", "HT", "3T", "136", "40", + "FCC", "5G", "20M", "HT", "3T", "140", "46", + "ETSI", "5G", "20M", "HT", "3T", "140", "40", + "MKK", "5G", "20M", "HT", "3T", "140", "40", + "FCC", "5G", "20M", "HT", "3T", "149", "46", + "ETSI", "5G", "20M", "HT", "3T", "149", "40", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "46", + "ETSI", "5G", "20M", "HT", "3T", "153", "40", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "46", + "ETSI", "5G", "20M", "HT", "3T", "157", "40", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "46", + "ETSI", "5G", "20M", "HT", "3T", "161", "40", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "46", + "ETSI", "5G", "20M", "HT", "3T", "165", "40", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "46", + "ETSI", "5G", "20M", "HT", "4T", "36", "40", + "MKK", "5G", "20M", "HT", "4T", "36", "40", + "FCC", "5G", "20M", "HT", "4T", "40", "46", + "ETSI", "5G", "20M", "HT", "4T", "40", "40", + "MKK", "5G", "20M", "HT", "4T", "40", "40", + "FCC", "5G", "20M", "HT", "4T", "44", "46", + "ETSI", "5G", "20M", "HT", "4T", "44", "40", + "MKK", "5G", "20M", "HT", "4T", "44", "40", + "FCC", "5G", "20M", "HT", "4T", "48", "46", + "ETSI", "5G", "20M", "HT", "4T", "48", "40", + "MKK", "5G", "20M", "HT", "4T", "48", "40", + "FCC", "5G", "20M", "HT", "4T", "52", "46", + "ETSI", "5G", "20M", "HT", "4T", "52", "40", + "MKK", "5G", "20M", "HT", "4T", "52", "40", + "FCC", "5G", "20M", "HT", "4T", "56", "46", + "ETSI", "5G", "20M", "HT", "4T", "56", "40", + "MKK", "5G", "20M", "HT", "4T", "56", "40", + "FCC", "5G", "20M", "HT", "4T", "60", "46", + "ETSI", "5G", "20M", "HT", "4T", "60", "40", + "MKK", "5G", "20M", "HT", "4T", "60", "40", + "FCC", "5G", "20M", "HT", "4T", "64", "46", + "ETSI", "5G", "20M", "HT", "4T", "64", "40", + "MKK", "5G", "20M", "HT", "4T", "64", "40", + "FCC", "5G", "20M", "HT", "4T", "100", "46", + "ETSI", "5G", "20M", "HT", "4T", "100", "40", + "MKK", "5G", "20M", "HT", "4T", "100", "40", + "FCC", "5G", "20M", "HT", "4T", "104", "46", + "ETSI", "5G", "20M", "HT", "4T", "104", "40", + "MKK", "5G", "20M", "HT", "4T", "104", "40", + "FCC", "5G", "20M", "HT", "4T", "108", "46", + "ETSI", "5G", "20M", "HT", "4T", "108", "40", + "MKK", "5G", "20M", "HT", "4T", "108", "40", + "FCC", "5G", "20M", "HT", "4T", "112", "46", + "ETSI", "5G", "20M", "HT", "4T", "112", "40", + "MKK", "5G", "20M", "HT", "4T", "112", "40", + "FCC", "5G", "20M", "HT", "4T", "116", "46", + "ETSI", "5G", "20M", "HT", "4T", "116", "40", + "MKK", "5G", "20M", "HT", "4T", "116", "40", + "FCC", "5G", "20M", "HT", "4T", "120", "46", + "ETSI", "5G", "20M", "HT", "4T", "120", "40", + "MKK", "5G", "20M", "HT", "4T", "120", "40", + "FCC", "5G", "20M", "HT", "4T", "124", "46", + "ETSI", "5G", "20M", "HT", "4T", "124", "40", + "MKK", "5G", "20M", "HT", "4T", "124", "40", + "FCC", "5G", "20M", "HT", "4T", "128", "46", + "ETSI", "5G", "20M", "HT", "4T", "128", "40", + "MKK", "5G", "20M", "HT", "4T", "128", "40", + "FCC", "5G", "20M", "HT", "4T", "132", "46", + "ETSI", "5G", "20M", "HT", "4T", "132", "40", + "MKK", "5G", "20M", "HT", "4T", "132", "40", + "FCC", "5G", "20M", "HT", "4T", "136", "46", + "ETSI", "5G", "20M", "HT", "4T", "136", "40", + "MKK", "5G", "20M", "HT", "4T", "136", "40", + "FCC", "5G", "20M", "HT", "4T", "140", "46", + "ETSI", "5G", "20M", "HT", "4T", "140", "40", + "MKK", "5G", "20M", "HT", "4T", "140", "40", + "FCC", "5G", "20M", "HT", "4T", "149", "46", + "ETSI", "5G", "20M", "HT", "4T", "149", "40", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "46", + "ETSI", "5G", "20M", "HT", "4T", "153", "40", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "46", + "ETSI", "5G", "20M", "HT", "4T", "157", "40", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "46", + "ETSI", "5G", "20M", "HT", "4T", "161", "40", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "46", + "ETSI", "5G", "20M", "HT", "4T", "165", "40", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "46", + "ETSI", "5G", "40M", "HT", "1T", "38", "40", + "MKK", "5G", "40M", "HT", "1T", "38", "40", + "FCC", "5G", "40M", "HT", "1T", "46", "46", + "ETSI", "5G", "40M", "HT", "1T", "46", "40", + "MKK", "5G", "40M", "HT", "1T", "46", "40", + "FCC", "5G", "40M", "HT", "1T", "54", "46", + "ETSI", "5G", "40M", "HT", "1T", "54", "40", + "MKK", "5G", "40M", "HT", "1T", "54", "40", + "FCC", "5G", "40M", "HT", "1T", "62", "46", + "ETSI", "5G", "40M", "HT", "1T", "62", "40", + "MKK", "5G", "40M", "HT", "1T", "62", "40", + "FCC", "5G", "40M", "HT", "1T", "102", "46", + "ETSI", "5G", "40M", "HT", "1T", "102", "40", + "MKK", "5G", "40M", "HT", "1T", "102", "40", + "FCC", "5G", "40M", "HT", "1T", "110", "46", + "ETSI", "5G", "40M", "HT", "1T", "110", "40", + "MKK", "5G", "40M", "HT", "1T", "110", "40", + "FCC", "5G", "40M", "HT", "1T", "118", "46", + "ETSI", "5G", "40M", "HT", "1T", "118", "40", + "MKK", "5G", "40M", "HT", "1T", "118", "40", + "FCC", "5G", "40M", "HT", "1T", "126", "46", + "ETSI", "5G", "40M", "HT", "1T", "126", "40", + "MKK", "5G", "40M", "HT", "1T", "126", "40", + "FCC", "5G", "40M", "HT", "1T", "134", "46", + "ETSI", "5G", "40M", "HT", "1T", "134", "40", + "MKK", "5G", "40M", "HT", "1T", "134", "40", + "FCC", "5G", "40M", "HT", "1T", "151", "46", + "ETSI", "5G", "40M", "HT", "1T", "151", "40", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "46", + "ETSI", "5G", "40M", "HT", "1T", "159", "40", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "46", + "ETSI", "5G", "40M", "HT", "2T", "38", "40", + "MKK", "5G", "40M", "HT", "2T", "38", "40", + "FCC", "5G", "40M", "HT", "2T", "46", "46", + "ETSI", "5G", "40M", "HT", "2T", "46", "40", + "MKK", "5G", "40M", "HT", "2T", "46", "40", + "FCC", "5G", "40M", "HT", "2T", "54", "46", + "ETSI", "5G", "40M", "HT", "2T", "54", "40", + "MKK", "5G", "40M", "HT", "2T", "54", "40", + "FCC", "5G", "40M", "HT", "2T", "62", "46", + "ETSI", "5G", "40M", "HT", "2T", "62", "40", + "MKK", "5G", "40M", "HT", "2T", "62", "40", + "FCC", "5G", "40M", "HT", "2T", "102", "46", + "ETSI", "5G", "40M", "HT", "2T", "102", "40", + "MKK", "5G", "40M", "HT", "2T", "102", "40", + "FCC", "5G", "40M", "HT", "2T", "110", "46", + "ETSI", "5G", "40M", "HT", "2T", "110", "40", + "MKK", "5G", "40M", "HT", "2T", "110", "40", + "FCC", "5G", "40M", "HT", "2T", "118", "46", + "ETSI", "5G", "40M", "HT", "2T", "118", "40", + "MKK", "5G", "40M", "HT", "2T", "118", "40", + "FCC", "5G", "40M", "HT", "2T", "126", "46", + "ETSI", "5G", "40M", "HT", "2T", "126", "40", + "MKK", "5G", "40M", "HT", "2T", "126", "40", + "FCC", "5G", "40M", "HT", "2T", "134", "46", + "ETSI", "5G", "40M", "HT", "2T", "134", "40", + "MKK", "5G", "40M", "HT", "2T", "134", "40", + "FCC", "5G", "40M", "HT", "2T", "151", "46", + "ETSI", "5G", "40M", "HT", "2T", "151", "40", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "46", + "ETSI", "5G", "40M", "HT", "2T", "159", "40", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "46", + "ETSI", "5G", "40M", "HT", "3T", "38", "40", + "MKK", "5G", "40M", "HT", "3T", "38", "40", + "FCC", "5G", "40M", "HT", "3T", "46", "46", + "ETSI", "5G", "40M", "HT", "3T", "46", "40", + "MKK", "5G", "40M", "HT", "3T", "46", "40", + "FCC", "5G", "40M", "HT", "3T", "54", "46", + "ETSI", "5G", "40M", "HT", "3T", "54", "40", + "MKK", "5G", "40M", "HT", "3T", "54", "40", + "FCC", "5G", "40M", "HT", "3T", "62", "46", + "ETSI", "5G", "40M", "HT", "3T", "62", "40", + "MKK", "5G", "40M", "HT", "3T", "62", "40", + "FCC", "5G", "40M", "HT", "3T", "102", "46", + "ETSI", "5G", "40M", "HT", "3T", "102", "40", + "MKK", "5G", "40M", "HT", "3T", "102", "40", + "FCC", "5G", "40M", "HT", "3T", "110", "46", + "ETSI", "5G", "40M", "HT", "3T", "110", "40", + "MKK", "5G", "40M", "HT", "3T", "110", "40", + "FCC", "5G", "40M", "HT", "3T", "118", "46", + "ETSI", "5G", "40M", "HT", "3T", "118", "40", + "MKK", "5G", "40M", "HT", "3T", "118", "40", + "FCC", "5G", "40M", "HT", "3T", "126", "46", + "ETSI", "5G", "40M", "HT", "3T", "126", "40", + "MKK", "5G", "40M", "HT", "3T", "126", "40", + "FCC", "5G", "40M", "HT", "3T", "134", "46", + "ETSI", "5G", "40M", "HT", "3T", "134", "40", + "MKK", "5G", "40M", "HT", "3T", "134", "40", + "FCC", "5G", "40M", "HT", "3T", "151", "46", + "ETSI", "5G", "40M", "HT", "3T", "151", "40", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "46", + "ETSI", "5G", "40M", "HT", "3T", "159", "40", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "46", + "ETSI", "5G", "40M", "HT", "4T", "38", "40", + "MKK", "5G", "40M", "HT", "4T", "38", "40", + "FCC", "5G", "40M", "HT", "4T", "46", "46", + "ETSI", "5G", "40M", "HT", "4T", "46", "40", + "MKK", "5G", "40M", "HT", "4T", "46", "40", + "FCC", "5G", "40M", "HT", "4T", "54", "46", + "ETSI", "5G", "40M", "HT", "4T", "54", "40", + "MKK", "5G", "40M", "HT", "4T", "54", "40", + "FCC", "5G", "40M", "HT", "4T", "62", "46", + "ETSI", "5G", "40M", "HT", "4T", "62", "40", + "MKK", "5G", "40M", "HT", "4T", "62", "40", + "FCC", "5G", "40M", "HT", "4T", "102", "46", + "ETSI", "5G", "40M", "HT", "4T", "102", "40", + "MKK", "5G", "40M", "HT", "4T", "102", "40", + "FCC", "5G", "40M", "HT", "4T", "110", "46", + "ETSI", "5G", "40M", "HT", "4T", "110", "40", + "MKK", "5G", "40M", "HT", "4T", "110", "40", + "FCC", "5G", "40M", "HT", "4T", "118", "46", + "ETSI", "5G", "40M", "HT", "4T", "118", "40", + "MKK", "5G", "40M", "HT", "4T", "118", "40", + "FCC", "5G", "40M", "HT", "4T", "126", "46", + "ETSI", "5G", "40M", "HT", "4T", "126", "40", + "MKK", "5G", "40M", "HT", "4T", "126", "40", + "FCC", "5G", "40M", "HT", "4T", "134", "46", + "ETSI", "5G", "40M", "HT", "4T", "134", "40", + "MKK", "5G", "40M", "HT", "4T", "134", "40", + "FCC", "5G", "40M", "HT", "4T", "151", "46", + "ETSI", "5G", "40M", "HT", "4T", "151", "40", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "46", + "ETSI", "5G", "40M", "HT", "4T", "159", "40", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "46", + "ETSI", "5G", "80M", "VHT", "1T", "42", "40", + "MKK", "5G", "80M", "VHT", "1T", "42", "40", + "FCC", "5G", "80M", "VHT", "1T", "58", "46", + "ETSI", "5G", "80M", "VHT", "1T", "58", "40", + "MKK", "5G", "80M", "VHT", "1T", "58", "40", + "FCC", "5G", "80M", "VHT", "1T", "106", "46", + "ETSI", "5G", "80M", "VHT", "1T", "106", "40", + "MKK", "5G", "80M", "VHT", "1T", "106", "40", + "FCC", "5G", "80M", "VHT", "1T", "122", "46", + "ETSI", "5G", "80M", "VHT", "1T", "122", "40", + "MKK", "5G", "80M", "VHT", "1T", "122", "40", + "FCC", "5G", "80M", "VHT", "1T", "155", "46", + "ETSI", "5G", "80M", "VHT", "1T", "155", "40", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "46", + "ETSI", "5G", "80M", "VHT", "2T", "42", "40", + "MKK", "5G", "80M", "VHT", "2T", "42", "40", + "FCC", "5G", "80M", "VHT", "2T", "58", "46", + "ETSI", "5G", "80M", "VHT", "2T", "58", "40", + "MKK", "5G", "80M", "VHT", "2T", "58", "40", + "FCC", "5G", "80M", "VHT", "2T", "106", "46", + "ETSI", "5G", "80M", "VHT", "2T", "106", "40", + "MKK", "5G", "80M", "VHT", "2T", "106", "40", + "FCC", "5G", "80M", "VHT", "2T", "122", "46", + "ETSI", "5G", "80M", "VHT", "2T", "122", "40", + "MKK", "5G", "80M", "VHT", "2T", "122", "40", + "FCC", "5G", "80M", "VHT", "2T", "155", "46", + "ETSI", "5G", "80M", "VHT", "2T", "155", "40", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "46", + "ETSI", "5G", "80M", "VHT", "3T", "42", "40", + "MKK", "5G", "80M", "VHT", "3T", "42", "40", + "FCC", "5G", "80M", "VHT", "3T", "58", "46", + "ETSI", "5G", "80M", "VHT", "3T", "58", "40", + "MKK", "5G", "80M", "VHT", "3T", "58", "40", + "FCC", "5G", "80M", "VHT", "3T", "106", "46", + "ETSI", "5G", "80M", "VHT", "3T", "106", "40", + "MKK", "5G", "80M", "VHT", "3T", "106", "40", + "FCC", "5G", "80M", "VHT", "3T", "122", "46", + "ETSI", "5G", "80M", "VHT", "3T", "122", "40", + "MKK", "5G", "80M", "VHT", "3T", "122", "40", + "FCC", "5G", "80M", "VHT", "3T", "155", "46", + "ETSI", "5G", "80M", "VHT", "3T", "155", "40", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "46", + "ETSI", "5G", "80M", "VHT", "4T", "42", "40", + "MKK", "5G", "80M", "VHT", "4T", "42", "40", + "FCC", "5G", "80M", "VHT", "4T", "58", "46", + "ETSI", "5G", "80M", "VHT", "4T", "58", "40", + "MKK", "5G", "80M", "VHT", "4T", "58", "40", + "FCC", "5G", "80M", "VHT", "4T", "106", "46", + "ETSI", "5G", "80M", "VHT", "4T", "106", "40", + "MKK", "5G", "80M", "VHT", "4T", "106", "40", + "FCC", "5G", "80M", "VHT", "4T", "122", "46", + "ETSI", "5G", "80M", "VHT", "4T", "122", "40", + "MKK", "5G", "80M", "VHT", "4T", "122", "40", + "FCC", "5G", "80M", "VHT", "4T", "155", "46", + "ETSI", "5G", "80M", "VHT", "4T", "155", "40", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type3)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type3; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type3)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type3; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type4.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type4[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "42", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "50", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "42", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "42", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "42", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "42", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "42", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "42", + "MKK", "2.4G", "20M", "HT", "1T", "01", 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"63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", + "MKK", "2.4G", "40M", "HT", "3T", "03", "34", + "FCC", "2.4G", "40M", "HT", "3T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", + "MKK", "2.4G", "40M", "HT", "3T", "04", "34", + "FCC", "2.4G", "40M", "HT", "3T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", + "MKK", "2.4G", "40M", "HT", "3T", "05", "34", + "FCC", "2.4G", "40M", "HT", "3T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", + "MKK", "2.4G", "40M", "HT", "3T", "06", "34", + "FCC", "2.4G", "40M", "HT", "3T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", + "MKK", "2.4G", "40M", "HT", "3T", "07", "34", + "FCC", "2.4G", "40M", "HT", "3T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", + "MKK", "2.4G", "40M", "HT", "3T", "08", "34", + "FCC", "2.4G", "40M", "HT", "3T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", + "MKK", "2.4G", "40M", "HT", "3T", "09", "34", + "FCC", "2.4G", "40M", "HT", "3T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", + "MKK", "2.4G", "40M", "HT", "3T", "10", "34", + "FCC", "2.4G", "40M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", + "MKK", "2.4G", "40M", "HT", "3T", "11", "34", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", + "MKK", "2.4G", "40M", "HT", "3T", "12", "34", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", + "MKK", "2.4G", "40M", "HT", "3T", "13", "34", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", + "MKK", "2.4G", "40M", "HT", "4T", "03", "34", + "FCC", "2.4G", "40M", "HT", "4T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", + "MKK", "2.4G", "40M", "HT", "4T", "04", "34", + "FCC", "2.4G", "40M", "HT", "4T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", + "MKK", "2.4G", "40M", "HT", "4T", "05", "34", + "FCC", "2.4G", "40M", "HT", "4T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", + "MKK", "2.4G", "40M", "HT", "4T", "06", "34", + "FCC", "2.4G", "40M", "HT", "4T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", + "MKK", "2.4G", "40M", "HT", "4T", "07", "34", + "FCC", "2.4G", "40M", "HT", "4T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", + "MKK", "2.4G", "40M", "HT", "4T", "08", "34", + "FCC", "2.4G", "40M", "HT", "4T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", + "MKK", "2.4G", "40M", "HT", "4T", "09", "34", + "FCC", "2.4G", "40M", "HT", "4T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", + "MKK", "2.4G", "40M", "HT", "4T", "10", "34", + "FCC", "2.4G", "40M", "HT", "4T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", + "MKK", "2.4G", "40M", "HT", "4T", "11", "34", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", + "MKK", "2.4G", "40M", "HT", "4T", "12", "34", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", + "MKK", "2.4G", "40M", "HT", "4T", "13", "34", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "42", + "MKK", "5G", "20M", "OFDM", "1T", "36", "42", + "FCC", "5G", "20M", "OFDM", "1T", "40", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "42", + "MKK", "5G", "20M", "OFDM", "1T", "40", "42", + "FCC", "5G", "20M", "OFDM", "1T", "44", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "42", + "MKK", "5G", "20M", "OFDM", "1T", "44", "42", + "FCC", "5G", "20M", "OFDM", "1T", "48", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "42", + "MKK", "5G", "20M", "OFDM", "1T", "48", "42", + "FCC", "5G", "20M", "OFDM", "1T", "52", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "42", + "MKK", "5G", "20M", "OFDM", "1T", "52", "42", + "FCC", "5G", "20M", "OFDM", "1T", "56", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "42", + "MKK", "5G", "20M", "OFDM", "1T", "56", "42", + "FCC", "5G", "20M", "OFDM", "1T", "60", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "42", + "MKK", "5G", "20M", "OFDM", "1T", "60", "42", + "FCC", "5G", "20M", "OFDM", "1T", "64", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "42", + "MKK", "5G", "20M", "OFDM", "1T", "64", "42", + "FCC", "5G", "20M", "OFDM", "1T", "100", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "42", + "MKK", "5G", "20M", "OFDM", "1T", "100", "42", + "FCC", "5G", "20M", "OFDM", "1T", "104", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "42", + "MKK", "5G", "20M", "OFDM", "1T", "104", "42", + "FCC", "5G", "20M", "OFDM", "1T", "108", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "42", + "MKK", "5G", "20M", "OFDM", "1T", "108", "42", + "FCC", "5G", "20M", "OFDM", "1T", "112", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "42", + "MKK", "5G", "20M", "OFDM", "1T", "112", "42", + "FCC", "5G", "20M", "OFDM", "1T", "116", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "42", + "MKK", "5G", "20M", "OFDM", "1T", "116", "42", + "FCC", "5G", "20M", "OFDM", "1T", "120", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "42", + "MKK", "5G", "20M", "OFDM", "1T", "120", "42", + "FCC", "5G", "20M", "OFDM", "1T", "124", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "42", + "MKK", "5G", "20M", "OFDM", "1T", "124", "42", + "FCC", "5G", "20M", "OFDM", "1T", "128", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "42", + "MKK", "5G", "20M", "OFDM", "1T", "128", "42", + "FCC", "5G", "20M", "OFDM", "1T", "132", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "42", + "MKK", "5G", "20M", "OFDM", "1T", "132", "42", + "FCC", "5G", "20M", "OFDM", "1T", "136", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "42", + "MKK", "5G", "20M", "OFDM", "1T", "136", "42", + "FCC", "5G", "20M", "OFDM", "1T", "140", "40", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", + "MKK", "5G", "20M", "OFDM", "1T", "140", "40", + "FCC", "5G", "20M", "OFDM", "1T", "149", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "44", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "44", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "36", + "ETSI", "5G", "20M", "HT", "1T", "48", "36", + "MKK", "5G", "20M", "HT", "1T", "48", "36", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "36", + "MKK", "5G", "20M", "HT", "1T", "52", "36", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "32", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "30", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "40", + "ETSI", "5G", "20M", "HT", "1T", "149", "40", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "40", + "ETSI", "5G", "20M", "HT", "1T", "153", "40", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "40", + "ETSI", "5G", "20M", "HT", "1T", "157", "40", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "40", + "ETSI", "5G", "20M", "HT", "1T", "161", "40", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "42", + "ETSI", "5G", "20M", "HT", "1T", "165", "42", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "32", + "ETSI", "5G", "20M", "HT", "2T", "36", "32", + "MKK", "5G", "20M", "HT", "2T", "36", "32", + "FCC", "5G", "20M", "HT", "2T", "40", "32", + "ETSI", "5G", "20M", "HT", "2T", "40", "32", + "MKK", "5G", "20M", "HT", "2T", "40", "32", + "FCC", "5G", "20M", "HT", "2T", "44", "32", + "ETSI", "5G", "20M", "HT", "2T", "44", "32", + "MKK", "5G", "20M", "HT", "2T", "44", "32", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "36", + "MKK", "5G", "20M", "HT", "2T", "48", "36", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "36", + "MKK", "5G", "20M", "HT", "2T", "52", "36", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "32", + "MKK", "5G", "20M", "HT", "2T", "56", "32", + "FCC", "5G", "20M", "HT", "2T", "60", "32", + "ETSI", "5G", "20M", "HT", "2T", "60", "32", + "MKK", "5G", "20M", "HT", "2T", "60", "32", + "FCC", "5G", "20M", "HT", "2T", "64", "32", + "ETSI", "5G", "20M", "HT", "2T", "64", "32", + "MKK", "5G", "20M", "HT", "2T", "64", "32", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "32", + "MKK", "5G", "20M", "HT", "2T", "100", "32", + "FCC", "5G", "20M", "HT", "2T", "104", "32", + "ETSI", "5G", "20M", "HT", "2T", "104", "32", + "MKK", "5G", "20M", "HT", "2T", "104", "32", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "32", + "MKK", "5G", "20M", "HT", "2T", "108", "32", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "32", + "MKK", "5G", "20M", "HT", "2T", "112", "32", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "32", + "MKK", "5G", "20M", "HT", "2T", "116", "32", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "32", + "MKK", "5G", "20M", "HT", "2T", "120", "32", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "32", + "MKK", "5G", "20M", "HT", "2T", "124", "32", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "32", + "MKK", "5G", "20M", "HT", "2T", "128", "32", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "32", + "MKK", "5G", "20M", "HT", "2T", "132", "32", + "FCC", "5G", "20M", "HT", "2T", "136", "32", + "ETSI", "5G", "20M", "HT", "2T", "136", "32", + "MKK", "5G", "20M", "HT", "2T", "136", "32", + "FCC", "5G", "20M", "HT", "2T", "140", "30", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "40", + "ETSI", "5G", "20M", "HT", "2T", "149", "40", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "40", + "ETSI", "5G", "20M", "HT", "2T", "153", "40", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "40", + "ETSI", "5G", "20M", "HT", "2T", "157", "40", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "40", + "ETSI", "5G", "20M", "HT", "2T", "161", "40", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "42", + "ETSI", "5G", "20M", "HT", "2T", "165", "42", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "32", + "ETSI", "5G", "20M", "HT", "3T", "36", "32", + "MKK", "5G", "20M", "HT", "3T", "36", "32", + "FCC", "5G", "20M", "HT", "3T", "40", "32", + "ETSI", "5G", "20M", "HT", "3T", "40", "32", + "MKK", "5G", "20M", "HT", "3T", "40", "32", + "FCC", "5G", "20M", "HT", "3T", "44", "32", + "ETSI", "5G", "20M", "HT", "3T", "44", "32", + "MKK", "5G", "20M", "HT", "3T", "44", "32", + "FCC", "5G", "20M", "HT", "3T", "48", "36", + "ETSI", "5G", "20M", "HT", "3T", "48", "36", + "MKK", "5G", "20M", "HT", "3T", "48", "36", + "FCC", "5G", "20M", "HT", "3T", "52", "36", + "ETSI", "5G", "20M", "HT", "3T", "52", "36", + "MKK", "5G", "20M", "HT", "3T", "52", "36", + "FCC", "5G", "20M", "HT", "3T", "56", "32", + "ETSI", "5G", "20M", "HT", "3T", "56", "32", + "MKK", "5G", "20M", "HT", "3T", "56", "32", + "FCC", "5G", "20M", "HT", "3T", "60", "32", + "ETSI", "5G", "20M", "HT", "3T", "60", "32", + "MKK", "5G", "20M", "HT", "3T", "60", "32", + "FCC", "5G", "20M", "HT", "3T", "64", "32", + "ETSI", "5G", "20M", "HT", "3T", "64", "32", + "MKK", "5G", "20M", "HT", "3T", "64", "32", + "FCC", "5G", "20M", "HT", "3T", "100", "32", + "ETSI", "5G", "20M", "HT", "3T", "100", "32", + "MKK", "5G", "20M", "HT", "3T", "100", "32", + "FCC", "5G", "20M", "HT", "3T", "104", "32", + "ETSI", "5G", "20M", "HT", "3T", "104", "32", + "MKK", "5G", "20M", "HT", "3T", "104", "32", + "FCC", "5G", "20M", "HT", "3T", "108", "32", + "ETSI", "5G", "20M", "HT", "3T", "108", "32", + "MKK", "5G", "20M", "HT", "3T", "108", "32", + "FCC", "5G", "20M", "HT", "3T", "112", "32", + "ETSI", "5G", "20M", "HT", "3T", "112", "32", + "MKK", "5G", "20M", "HT", "3T", "112", "32", + "FCC", "5G", "20M", "HT", "3T", "116", "32", + "ETSI", "5G", "20M", "HT", "3T", "116", "32", + "MKK", "5G", "20M", "HT", "3T", "116", "32", + "FCC", "5G", "20M", "HT", "3T", "120", "32", + "ETSI", "5G", "20M", "HT", "3T", "120", "32", + "MKK", "5G", "20M", "HT", "3T", "120", "32", + "FCC", "5G", "20M", "HT", "3T", "124", "32", + "ETSI", "5G", "20M", "HT", "3T", "124", "32", + "MKK", "5G", "20M", "HT", "3T", "124", "32", + "FCC", "5G", "20M", "HT", "3T", "128", "32", + "ETSI", "5G", "20M", "HT", "3T", "128", "32", + "MKK", "5G", "20M", "HT", "3T", "128", "32", + "FCC", "5G", "20M", "HT", "3T", "132", "32", + "ETSI", "5G", "20M", "HT", "3T", "132", "32", + "MKK", "5G", "20M", "HT", "3T", "132", "32", + "FCC", "5G", "20M", "HT", "3T", "136", "32", + "ETSI", "5G", "20M", "HT", "3T", "136", "32", + "MKK", "5G", "20M", "HT", "3T", "136", "32", + "FCC", "5G", "20M", "HT", "3T", "140", "30", + "ETSI", "5G", "20M", "HT", "3T", "140", "30", + "MKK", "5G", "20M", "HT", "3T", "140", "30", + "FCC", "5G", "20M", "HT", "3T", "149", "40", + "ETSI", "5G", "20M", "HT", "3T", "149", "40", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "40", + "ETSI", "5G", "20M", "HT", "3T", "153", "40", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "40", + "ETSI", "5G", "20M", "HT", "3T", "157", "40", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "40", + "ETSI", "5G", "20M", "HT", "3T", "161", "40", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "42", + "ETSI", "5G", "20M", "HT", "3T", "165", "42", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "32", + "ETSI", "5G", "20M", "HT", "4T", "36", "32", + "MKK", "5G", "20M", "HT", "4T", "36", "32", + "FCC", "5G", "20M", "HT", "4T", "40", "32", + "ETSI", "5G", "20M", "HT", "4T", "40", "32", + "MKK", "5G", "20M", "HT", "4T", "40", "32", + "FCC", "5G", "20M", "HT", "4T", "44", "32", + "ETSI", "5G", "20M", "HT", "4T", "44", "32", + "MKK", "5G", "20M", "HT", "4T", "44", "32", + "FCC", "5G", "20M", "HT", "4T", "48", "36", + "ETSI", "5G", "20M", "HT", "4T", "48", "36", + "MKK", "5G", "20M", "HT", "4T", "48", "36", + "FCC", "5G", "20M", "HT", "4T", "52", "36", + "ETSI", "5G", "20M", "HT", "4T", "52", "36", + "MKK", "5G", "20M", "HT", "4T", "52", "36", + "FCC", "5G", "20M", "HT", "4T", "56", "32", + "ETSI", "5G", "20M", "HT", "4T", "56", "32", + "MKK", "5G", "20M", "HT", "4T", "56", "32", + "FCC", "5G", "20M", "HT", "4T", "60", "32", + "ETSI", "5G", "20M", "HT", "4T", "60", "32", + "MKK", "5G", "20M", "HT", "4T", "60", "32", + "FCC", "5G", "20M", "HT", "4T", "64", "32", + "ETSI", "5G", "20M", "HT", "4T", "64", "32", + "MKK", "5G", "20M", "HT", "4T", "64", "32", + "FCC", "5G", "20M", "HT", "4T", "100", "32", + "ETSI", "5G", "20M", "HT", "4T", "100", "32", + "MKK", "5G", "20M", "HT", "4T", "100", "32", + "FCC", "5G", "20M", "HT", "4T", "104", "32", + "ETSI", "5G", "20M", "HT", "4T", "104", "32", + "MKK", "5G", "20M", "HT", "4T", "104", "32", + "FCC", "5G", "20M", "HT", "4T", "108", "32", + "ETSI", "5G", "20M", "HT", "4T", "108", "32", + "MKK", "5G", "20M", "HT", "4T", "108", "32", + "FCC", "5G", "20M", "HT", "4T", "112", "32", + "ETSI", "5G", "20M", "HT", "4T", "112", "32", + "MKK", "5G", "20M", "HT", "4T", "112", "32", + "FCC", "5G", "20M", "HT", "4T", "116", "32", + "ETSI", "5G", "20M", "HT", "4T", "116", "32", + "MKK", "5G", "20M", "HT", "4T", "116", "32", + "FCC", "5G", "20M", "HT", "4T", "120", "32", + "ETSI", "5G", "20M", "HT", "4T", "120", "32", + "MKK", "5G", "20M", "HT", "4T", "120", "32", + "FCC", "5G", "20M", "HT", "4T", "124", "32", + "ETSI", "5G", "20M", "HT", "4T", "124", "32", + "MKK", "5G", "20M", "HT", "4T", "124", "32", + "FCC", "5G", "20M", "HT", "4T", "128", "32", + "ETSI", "5G", "20M", "HT", "4T", "128", "32", + "MKK", "5G", "20M", "HT", "4T", "128", "32", + "FCC", "5G", "20M", "HT", "4T", "132", "32", + "ETSI", "5G", "20M", "HT", "4T", "132", "32", + "MKK", "5G", "20M", "HT", "4T", "132", "32", + "FCC", "5G", "20M", "HT", "4T", "136", "32", + "ETSI", "5G", "20M", "HT", "4T", "136", "32", + "MKK", "5G", "20M", "HT", "4T", "136", "32", + "FCC", "5G", "20M", "HT", "4T", "140", "30", + "ETSI", "5G", "20M", "HT", "4T", "140", "30", + "MKK", "5G", "20M", "HT", "4T", "140", "30", + "FCC", "5G", "20M", "HT", "4T", "149", "40", + "ETSI", "5G", "20M", "HT", "4T", "149", "40", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "40", + "ETSI", "5G", "20M", "HT", "4T", "153", "40", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "40", + "ETSI", "5G", "20M", "HT", "4T", "157", "40", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "40", + "ETSI", "5G", "20M", "HT", "4T", "161", "40", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "42", + "ETSI", "5G", "20M", "HT", "4T", "165", "42", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "32", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "36", + "MKK", "5G", "40M", "HT", "1T", "46", "36", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "36", + "MKK", "5G", "40M", "HT", "1T", "54", "36", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "36", + "MKK", "5G", "40M", "HT", "1T", "134", "36", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "36", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "40", + "ETSI", "5G", "40M", "HT", "1T", "159", "40", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "32", + "ETSI", "5G", "40M", "HT", "2T", "38", "32", + "MKK", "5G", "40M", "HT", "2T", "38", "32", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "36", + "MKK", "5G", "40M", "HT", "2T", "46", "36", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "36", + "MKK", "5G", "40M", "HT", "2T", "54", "36", + "FCC", "5G", "40M", "HT", "2T", "62", "32", + "ETSI", "5G", "40M", "HT", "2T", "62", "32", + "MKK", "5G", "40M", "HT", "2T", "62", "32", + "FCC", "5G", "40M", "HT", "2T", "102", "30", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "32", + "ETSI", "5G", "40M", "HT", "2T", "110", "32", + "MKK", "5G", "40M", "HT", "2T", "110", "32", + "FCC", "5G", "40M", "HT", "2T", "118", "32", + "ETSI", "5G", "40M", "HT", "2T", "118", "32", + "MKK", "5G", "40M", "HT", "2T", "118", "32", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "32", + "MKK", "5G", "40M", "HT", "2T", "126", "32", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "36", + "MKK", "5G", "40M", "HT", "2T", "134", "36", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "36", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "40", + "ETSI", "5G", "40M", "HT", "2T", "159", "40", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "32", + "ETSI", "5G", "40M", "HT", "3T", "38", "32", + "MKK", "5G", "40M", "HT", "3T", "38", "32", + "FCC", "5G", "40M", "HT", "3T", "46", "36", + "ETSI", "5G", "40M", "HT", "3T", "46", "36", + "MKK", "5G", "40M", "HT", "3T", "46", "36", + "FCC", "5G", "40M", "HT", "3T", "54", "36", + "ETSI", "5G", "40M", "HT", "3T", "54", "36", + "MKK", "5G", "40M", "HT", "3T", "54", "36", + "FCC", "5G", "40M", "HT", "3T", "62", "32", + "ETSI", "5G", "40M", "HT", "3T", "62", "32", + "MKK", "5G", "40M", "HT", "3T", "62", "32", + "FCC", "5G", "40M", "HT", "3T", "102", "30", + "ETSI", "5G", "40M", "HT", "3T", "102", "30", + "MKK", "5G", "40M", "HT", "3T", "102", "30", + "FCC", "5G", "40M", "HT", "3T", "110", "32", + "ETSI", "5G", "40M", "HT", "3T", "110", "32", + "MKK", "5G", "40M", "HT", "3T", "110", "32", + "FCC", "5G", "40M", "HT", "3T", "118", "32", + "ETSI", "5G", "40M", "HT", "3T", "118", "32", + "MKK", "5G", "40M", "HT", "3T", "118", "32", + "FCC", "5G", "40M", "HT", "3T", "126", "32", + "ETSI", "5G", "40M", "HT", "3T", "126", "32", + "MKK", "5G", "40M", "HT", "3T", "126", "32", + "FCC", "5G", "40M", "HT", "3T", "134", "36", + "ETSI", "5G", "40M", "HT", "3T", "134", "36", + "MKK", "5G", "40M", "HT", "3T", "134", "36", + "FCC", "5G", "40M", "HT", "3T", "151", "36", + "ETSI", "5G", "40M", "HT", "3T", "151", "36", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "40", + "ETSI", "5G", "40M", "HT", "3T", "159", "40", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "32", + "ETSI", "5G", "40M", "HT", "4T", "38", "32", + "MKK", "5G", "40M", "HT", "4T", "38", "32", + "FCC", "5G", "40M", "HT", "4T", "46", "36", + "ETSI", "5G", "40M", "HT", "4T", "46", "36", + "MKK", "5G", "40M", "HT", "4T", "46", "36", + "FCC", "5G", "40M", "HT", "4T", "54", "36", + "ETSI", "5G", "40M", "HT", "4T", "54", "36", + "MKK", "5G", "40M", "HT", "4T", "54", "36", + "FCC", "5G", "40M", "HT", "4T", "62", "32", + "ETSI", "5G", "40M", "HT", "4T", "62", "32", + "MKK", "5G", "40M", "HT", "4T", "62", "32", + "FCC", "5G", "40M", "HT", "4T", "102", "30", + "ETSI", "5G", "40M", "HT", "4T", "102", "30", + "MKK", "5G", "40M", "HT", "4T", "102", "30", + "FCC", "5G", "40M", "HT", "4T", "110", "32", + "ETSI", "5G", "40M", "HT", "4T", "110", "32", + "MKK", "5G", "40M", "HT", "4T", "110", "32", + "FCC", "5G", "40M", "HT", "4T", "118", "32", + "ETSI", "5G", "40M", "HT", "4T", "118", "32", + "MKK", "5G", "40M", "HT", "4T", "118", "32", + "FCC", "5G", "40M", "HT", "4T", "126", "32", + "ETSI", "5G", "40M", "HT", "4T", "126", "32", + "MKK", "5G", "40M", "HT", "4T", "126", "32", + "FCC", "5G", "40M", "HT", "4T", "134", "36", + "ETSI", "5G", "40M", "HT", "4T", "134", "36", + "MKK", "5G", "40M", "HT", "4T", "134", "36", + "FCC", "5G", "40M", "HT", "4T", "151", "36", + "ETSI", "5G", "40M", "HT", "4T", "151", "36", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "40", + "ETSI", "5G", "40M", "HT", "4T", "159", "40", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "34", + "ETSI", "5G", "80M", "VHT", "1T", "42", "34", + "MKK", "5G", "80M", "VHT", "1T", "42", "34", + "FCC", "5G", "80M", "VHT", "1T", "58", "34", + "ETSI", "5G", "80M", "VHT", "1T", "58", "34", + "MKK", "5G", "80M", "VHT", "1T", "58", "34", + "FCC", "5G", "80M", "VHT", "1T", "106", "32", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "34", + "MKK", "5G", "80M", "VHT", "1T", "122", "34", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "34", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "34", + "ETSI", "5G", "80M", "VHT", "2T", "42", "34", + "MKK", "5G", "80M", "VHT", "2T", "42", "34", + "FCC", "5G", "80M", "VHT", "2T", "58", "34", + "ETSI", "5G", "80M", "VHT", "2T", "58", "34", + "MKK", "5G", "80M", "VHT", "2T", "58", "34", + "FCC", "5G", "80M", "VHT", "2T", "106", "32", + "ETSI", "5G", "80M", "VHT", "2T", "106", "32", + "MKK", "5G", "80M", "VHT", "2T", "106", "32", + "FCC", "5G", "80M", "VHT", "2T", "122", "34", + "ETSI", "5G", "80M", "VHT", "2T", "122", "34", + "MKK", "5G", "80M", "VHT", "2T", "122", "34", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "34", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "34", + "ETSI", "5G", "80M", "VHT", "3T", "42", "34", + "MKK", "5G", "80M", "VHT", "3T", "42", "34", + "FCC", "5G", "80M", "VHT", "3T", "58", "34", + "ETSI", "5G", "80M", "VHT", "3T", "58", "34", + "MKK", "5G", "80M", "VHT", "3T", "58", "34", + "FCC", "5G", "80M", "VHT", "3T", "106", "32", + "ETSI", "5G", "80M", "VHT", "3T", "106", "32", + "MKK", "5G", "80M", "VHT", "3T", "106", "32", + "FCC", "5G", "80M", "VHT", "3T", "122", "34", + "ETSI", "5G", "80M", "VHT", "3T", "122", "34", + "MKK", "5G", "80M", "VHT", "3T", "122", "34", + "FCC", "5G", "80M", "VHT", "3T", "155", "34", + "ETSI", "5G", "80M", "VHT", "3T", "155", "34", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "34", + "ETSI", "5G", "80M", "VHT", "4T", "42", "34", + "MKK", "5G", "80M", "VHT", "4T", "42", "34", + "FCC", "5G", "80M", "VHT", "4T", "58", "34", + "ETSI", "5G", "80M", "VHT", "4T", "58", "34", + "MKK", "5G", "80M", "VHT", "4T", "58", "34", + "FCC", "5G", "80M", "VHT", "4T", "106", "32", + "ETSI", "5G", "80M", "VHT", "4T", "106", "32", + "MKK", "5G", "80M", "VHT", "4T", "106", "32", + "FCC", "5G", "80M", "VHT", "4T", "122", "34", + "ETSI", "5G", "80M", "VHT", "4T", "122", "34", + "MKK", "5G", "80M", "VHT", "4T", "122", "34", + "FCC", "5G", "80M", "VHT", "4T", "155", "34", + "ETSI", "5G", "80M", "VHT", "4T", "155", "34", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type4)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type4; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type4)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type4; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type5.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type5[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", + "MKK", "2.4G", "20M", "HT", "1T", "01", "40", + "FCC", "2.4G", "20M", "HT", "1T", "02", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", + "MKK", "2.4G", "20M", "HT", "1T", "02", "40", + "FCC", "2.4G", "20M", "HT", "1T", "03", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", + "MKK", "2.4G", "20M", "HT", "1T", "03", "40", + "FCC", "2.4G", "20M", "HT", "1T", "04", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", + "MKK", "2.4G", "20M", "HT", "1T", "04", "40", + "FCC", "2.4G", "20M", "HT", "1T", "05", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "40", + "MKK", "2.4G", "20M", "HT", "1T", "05", "40", + "FCC", "2.4G", "20M", "HT", "1T", "06", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "40", + "MKK", "2.4G", "20M", "HT", "1T", "06", "40", + "FCC", "2.4G", "20M", "HT", "1T", "07", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "40", + "MKK", "2.4G", "20M", "HT", "1T", "07", "40", + "FCC", "2.4G", "20M", "HT", "1T", "08", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "40", + "MKK", "2.4G", "20M", "HT", "1T", "08", "40", + "FCC", "2.4G", "20M", "HT", "1T", "09", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "40", + "MKK", "2.4G", "20M", "HT", "1T", "09", "40", + "FCC", "2.4G", "20M", "HT", "1T", "10", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "40", + "MKK", "2.4G", "20M", "HT", "1T", "10", "40", + "FCC", "2.4G", "20M", "HT", "1T", "11", "46", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "40", + "MKK", "2.4G", "20M", "HT", "1T", "11", "40", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "40", + "MKK", "2.4G", "20M", "HT", "1T", "12", "40", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "40", + "MKK", "2.4G", "20M", "HT", "1T", "13", "40", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", + "MKK", "2.4G", "20M", "HT", "2T", "01", "40", + "FCC", "2.4G", "20M", "HT", "2T", "02", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", + "MKK", "2.4G", "20M", "HT", "2T", "02", "40", + "FCC", "2.4G", "20M", "HT", "2T", "03", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", + "MKK", "2.4G", "20M", "HT", "2T", "03", "40", + "FCC", "2.4G", "20M", "HT", "2T", "04", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", + "MKK", "2.4G", "20M", "HT", "2T", "04", "40", + "FCC", "2.4G", "20M", "HT", "2T", "05", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", + "MKK", "2.4G", "20M", "HT", "2T", "05", "40", + "FCC", "2.4G", "20M", "HT", "2T", "06", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", + "MKK", "2.4G", "20M", "HT", "2T", "06", "40", + "FCC", "2.4G", "20M", "HT", "2T", "07", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", + "MKK", "2.4G", "20M", "HT", "2T", "07", "40", + "FCC", "2.4G", "20M", "HT", "2T", "08", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", + "MKK", "2.4G", "20M", "HT", "2T", "08", "40", + "FCC", "2.4G", "20M", "HT", "2T", "09", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", + "MKK", "2.4G", "20M", "HT", "2T", "09", "40", + "FCC", "2.4G", "20M", "HT", "2T", "10", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", + "MKK", "2.4G", "20M", "HT", "2T", "10", "40", + "FCC", "2.4G", "20M", "HT", "2T", "11", "46", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", + "MKK", "2.4G", "20M", "HT", "2T", "11", "40", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", + "MKK", "2.4G", "20M", "HT", "2T", "12", "40", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", + "MKK", "2.4G", "20M", "HT", "2T", "13", "40", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "20M", "HT", "3T", "01", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", + "MKK", "2.4G", "20M", "HT", "3T", "01", "40", + "FCC", "2.4G", "20M", "HT", "3T", "02", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", + "MKK", "2.4G", "20M", "HT", "3T", "02", "40", + "FCC", "2.4G", "20M", "HT", "3T", "03", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", + "MKK", "2.4G", "20M", "HT", "3T", "03", "40", + "FCC", "2.4G", "20M", "HT", "3T", "04", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", + "MKK", "2.4G", "20M", "HT", "3T", "04", "40", + "FCC", "2.4G", "20M", "HT", "3T", "05", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", + "MKK", "2.4G", "20M", "HT", "3T", "05", "40", + "FCC", "2.4G", "20M", "HT", "3T", "06", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", + "MKK", "2.4G", "20M", "HT", "3T", "06", "40", + "FCC", "2.4G", "20M", "HT", "3T", "07", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", + "MKK", "2.4G", "20M", "HT", "3T", "07", "40", + "FCC", "2.4G", "20M", "HT", "3T", "08", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", + "MKK", "2.4G", "20M", "HT", "3T", "08", "40", + "FCC", "2.4G", "20M", "HT", "3T", "09", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", + "MKK", "2.4G", "20M", "HT", "3T", "09", "40", + "FCC", "2.4G", "20M", "HT", "3T", "10", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", + "MKK", "2.4G", "20M", "HT", "3T", "10", "40", + "FCC", "2.4G", "20M", "HT", "3T", "11", "46", + "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", + "MKK", "2.4G", "20M", "HT", "3T", "11", "40", + "FCC", "2.4G", "20M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", + "MKK", "2.4G", "20M", "HT", "3T", "12", "40", + "FCC", "2.4G", "20M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", + "MKK", "2.4G", "20M", "HT", "3T", "13", "40", + "FCC", "2.4G", "20M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", + "MKK", "2.4G", "20M", "HT", "3T", "14", "63", + "FCC", "2.4G", "20M", "HT", "4T", "01", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", + "MKK", "2.4G", "20M", "HT", "4T", "01", "40", + "FCC", "2.4G", "20M", "HT", "4T", "02", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", + "MKK", "2.4G", "20M", "HT", "4T", "02", "40", + "FCC", "2.4G", "20M", "HT", "4T", "03", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", + "MKK", "2.4G", "20M", "HT", "4T", "03", "40", + "FCC", "2.4G", "20M", "HT", "4T", "04", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", + "MKK", "2.4G", "20M", "HT", "4T", "04", "40", + "FCC", "2.4G", "20M", "HT", "4T", "05", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", + "MKK", "2.4G", "20M", "HT", "4T", "05", "40", + "FCC", "2.4G", "20M", "HT", "4T", "06", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", + "MKK", "2.4G", "20M", "HT", "4T", "06", "40", + "FCC", "2.4G", "20M", "HT", "4T", "07", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", + "MKK", "2.4G", "20M", "HT", "4T", "07", "40", + "FCC", "2.4G", "20M", "HT", "4T", "08", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", + "MKK", "2.4G", "20M", "HT", "4T", "08", "40", + "FCC", "2.4G", "20M", "HT", "4T", "09", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", + "MKK", "2.4G", "20M", "HT", "4T", "09", "40", + "FCC", "2.4G", "20M", "HT", "4T", "10", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", + "MKK", "2.4G", "20M", "HT", "4T", "10", "40", + "FCC", "2.4G", "20M", "HT", "4T", "11", "46", + "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", + "MKK", "2.4G", "20M", "HT", "4T", "11", "40", + "FCC", "2.4G", "20M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", + "MKK", "2.4G", "20M", "HT", "4T", "12", "40", + "FCC", "2.4G", "20M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", + "MKK", "2.4G", "20M", "HT", "4T", "13", "40", + "FCC", "2.4G", "20M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", + "MKK", "2.4G", "20M", "HT", "4T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "40", + "MKK", "2.4G", "40M", "HT", "1T", "03", "40", + "FCC", "2.4G", "40M", "HT", "1T", "04", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "40", + "MKK", "2.4G", "40M", "HT", "1T", "04", "40", + "FCC", "2.4G", "40M", "HT", "1T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "40", + "MKK", "2.4G", "40M", "HT", "1T", "05", "40", + "FCC", "2.4G", "40M", "HT", "1T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "40", + "MKK", "2.4G", "40M", "HT", "1T", "06", "40", + "FCC", "2.4G", "40M", "HT", "1T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "40", + "MKK", "2.4G", "40M", "HT", "1T", "07", "40", + "FCC", "2.4G", "40M", "HT", "1T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "40", + "MKK", "2.4G", "40M", "HT", "1T", "08", "40", + "FCC", "2.4G", "40M", "HT", "1T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "40", + "MKK", "2.4G", "40M", "HT", "1T", "09", "40", + "FCC", "2.4G", "40M", "HT", "1T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "40", + "MKK", "2.4G", "40M", "HT", "1T", "10", "40", + "FCC", "2.4G", "40M", "HT", "1T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "40", + "MKK", "2.4G", "40M", "HT", "1T", "11", "40", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "40", + "MKK", "2.4G", "40M", "HT", "1T", "12", "40", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "40", + "MKK", "2.4G", "40M", "HT", "1T", "13", "40", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "40", + "MKK", "2.4G", "40M", "HT", "2T", "03", "40", + "FCC", "2.4G", "40M", "HT", "2T", "04", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "40", + "MKK", "2.4G", "40M", "HT", "2T", "04", "40", + "FCC", "2.4G", "40M", "HT", "2T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "40", + "MKK", "2.4G", "40M", "HT", "2T", "05", "40", + "FCC", "2.4G", "40M", "HT", "2T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "40", + "MKK", "2.4G", "40M", "HT", "2T", "06", "40", + "FCC", "2.4G", "40M", "HT", "2T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "40", + "MKK", "2.4G", "40M", "HT", "2T", "07", "40", + "FCC", "2.4G", "40M", "HT", "2T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "40", + "MKK", "2.4G", "40M", "HT", "2T", "08", "40", + "FCC", "2.4G", "40M", "HT", "2T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "40", + "MKK", "2.4G", "40M", "HT", "2T", "09", "40", + "FCC", "2.4G", "40M", "HT", "2T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "40", + "MKK", "2.4G", "40M", "HT", "2T", "10", "40", + "FCC", "2.4G", "40M", "HT", "2T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "40", + "MKK", "2.4G", "40M", "HT", "2T", "11", "40", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "40", + "MKK", "2.4G", "40M", "HT", "2T", "12", "40", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "40", + "MKK", "2.4G", "40M", "HT", "2T", "13", "40", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "40", + "MKK", "2.4G", "40M", "HT", "3T", "03", "40", + "FCC", "2.4G", "40M", "HT", "3T", "04", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "40", + "MKK", "2.4G", "40M", "HT", "3T", "04", "40", + "FCC", "2.4G", "40M", "HT", "3T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "40", + "MKK", "2.4G", "40M", "HT", "3T", "05", "40", + "FCC", "2.4G", "40M", "HT", "3T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "40", + "MKK", "2.4G", "40M", "HT", "3T", "06", "40", + "FCC", "2.4G", "40M", "HT", "3T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "40", + "MKK", "2.4G", "40M", "HT", "3T", "07", "40", + "FCC", "2.4G", "40M", "HT", "3T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "40", + "MKK", "2.4G", "40M", "HT", "3T", "08", "40", + "FCC", "2.4G", "40M", "HT", "3T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "40", + "MKK", "2.4G", "40M", "HT", "3T", "09", "40", + "FCC", "2.4G", "40M", "HT", "3T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "40", + "MKK", "2.4G", "40M", "HT", "3T", "10", "40", + "FCC", "2.4G", "40M", "HT", "3T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "40", + "MKK", "2.4G", "40M", "HT", "3T", "11", "40", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "40", + "MKK", "2.4G", "40M", "HT", "3T", "12", "40", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "40", + "MKK", "2.4G", "40M", "HT", "3T", "13", "40", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "40", + "MKK", "2.4G", "40M", "HT", "4T", "03", "40", + "FCC", "2.4G", "40M", "HT", "4T", "04", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "40", + "MKK", "2.4G", "40M", "HT", "4T", "04", "40", + "FCC", "2.4G", "40M", "HT", "4T", "05", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "40", + "MKK", "2.4G", "40M", "HT", "4T", "05", "40", + "FCC", "2.4G", "40M", "HT", "4T", "06", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "40", + "MKK", "2.4G", "40M", "HT", "4T", "06", "40", + "FCC", "2.4G", "40M", "HT", "4T", "07", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "40", + "MKK", "2.4G", "40M", "HT", "4T", "07", "40", + "FCC", "2.4G", "40M", "HT", "4T", "08", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "40", + "MKK", "2.4G", "40M", "HT", "4T", "08", "40", + "FCC", "2.4G", "40M", "HT", "4T", "09", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "40", + "MKK", "2.4G", "40M", "HT", "4T", "09", "40", + "FCC", "2.4G", "40M", "HT", "4T", "10", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "40", + "MKK", "2.4G", "40M", "HT", "4T", "10", "40", + "FCC", "2.4G", "40M", "HT", "4T", "11", "46", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "40", + "MKK", "2.4G", "40M", "HT", "4T", "11", "40", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "40", + "MKK", "2.4G", "40M", "HT", "4T", "12", "40", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "40", + "MKK", "2.4G", "40M", "HT", "4T", "13", "40", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "40", + "MKK", "5G", "20M", "OFDM", "1T", "36", "40", + "FCC", "5G", "20M", "OFDM", "1T", "40", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "40", + "MKK", "5G", "20M", "OFDM", "1T", "40", "40", + "FCC", "5G", "20M", "OFDM", "1T", "44", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "40", + "MKK", "5G", "20M", "OFDM", "1T", "44", "40", + "FCC", "5G", "20M", "OFDM", "1T", "48", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "40", + "MKK", "5G", "20M", "OFDM", "1T", "48", "40", + "FCC", "5G", "20M", "OFDM", "1T", "52", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "40", + "MKK", "5G", "20M", "OFDM", "1T", "52", "40", + "FCC", "5G", "20M", "OFDM", "1T", "56", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "40", + "MKK", "5G", "20M", "OFDM", "1T", "56", "40", + "FCC", "5G", "20M", "OFDM", "1T", "60", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "40", + "MKK", "5G", "20M", "OFDM", "1T", "60", "40", + "FCC", "5G", "20M", "OFDM", "1T", "64", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", + "MKK", "5G", "20M", "OFDM", "1T", "64", "40", + "FCC", "5G", "20M", "OFDM", "1T", "100", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", + "MKK", "5G", "20M", "OFDM", "1T", "100", "40", + "FCC", "5G", "20M", "OFDM", "1T", "104", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "40", + "MKK", "5G", "20M", "OFDM", "1T", "104", "40", + "FCC", "5G", "20M", "OFDM", "1T", "108", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "40", + "MKK", "5G", "20M", "OFDM", "1T", "108", "40", + "FCC", "5G", "20M", "OFDM", "1T", "112", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "40", + "MKK", "5G", "20M", "OFDM", "1T", "112", "40", + "FCC", "5G", "20M", "OFDM", "1T", "116", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "40", + "MKK", "5G", "20M", "OFDM", "1T", "116", "40", + "FCC", "5G", "20M", "OFDM", "1T", "120", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "40", + "MKK", "5G", "20M", "OFDM", "1T", "120", "40", + "FCC", "5G", "20M", "OFDM", "1T", "124", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "40", + "MKK", "5G", "20M", "OFDM", "1T", "124", "40", + "FCC", "5G", "20M", "OFDM", "1T", "128", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "40", + "MKK", "5G", "20M", "OFDM", "1T", "128", "40", + "FCC", "5G", "20M", "OFDM", "1T", "132", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "40", + "MKK", "5G", "20M", "OFDM", "1T", "132", "40", + "FCC", "5G", "20M", "OFDM", "1T", "136", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "40", + "MKK", "5G", "20M", "OFDM", "1T", "136", "40", + "FCC", "5G", "20M", "OFDM", "1T", "140", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", + "MKK", "5G", "20M", "OFDM", "1T", "140", "40", + "FCC", "5G", "20M", "OFDM", "1T", "149", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "40", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "40", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "40", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "40", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "40", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "46", + "ETSI", "5G", "20M", "HT", "1T", "36", "40", + "MKK", "5G", "20M", "HT", "1T", "36", "40", + "FCC", "5G", "20M", "HT", "1T", "40", "46", + "ETSI", "5G", "20M", "HT", "1T", "40", "40", + "MKK", "5G", "20M", "HT", "1T", "40", "40", + "FCC", "5G", "20M", "HT", "1T", "44", "46", + "ETSI", "5G", "20M", "HT", "1T", "44", "40", + "MKK", "5G", "20M", "HT", "1T", "44", "40", + "FCC", "5G", "20M", "HT", "1T", "48", "46", + "ETSI", "5G", "20M", "HT", "1T", "48", "40", + "MKK", "5G", "20M", "HT", "1T", "48", "40", + "FCC", "5G", "20M", "HT", "1T", "52", "46", + "ETSI", "5G", "20M", "HT", "1T", "52", "40", + "MKK", "5G", "20M", "HT", "1T", "52", "40", + "FCC", "5G", "20M", "HT", "1T", "56", "46", + "ETSI", "5G", "20M", "HT", "1T", "56", "40", + "MKK", "5G", "20M", "HT", "1T", "56", "40", + "FCC", "5G", "20M", "HT", "1T", "60", "46", + "ETSI", "5G", "20M", "HT", "1T", "60", "40", + "MKK", "5G", "20M", "HT", "1T", "60", "40", + "FCC", "5G", "20M", "HT", "1T", "64", "46", + "ETSI", "5G", "20M", "HT", "1T", "64", "40", + "MKK", "5G", "20M", "HT", "1T", "64", "40", + "FCC", "5G", "20M", "HT", "1T", "100", "46", + "ETSI", "5G", "20M", "HT", "1T", "100", "40", + "MKK", "5G", "20M", "HT", "1T", "100", "40", + "FCC", "5G", "20M", "HT", "1T", "104", "46", + "ETSI", "5G", "20M", "HT", "1T", "104", "40", + "MKK", "5G", "20M", "HT", "1T", "104", "40", + "FCC", "5G", "20M", "HT", "1T", "108", "46", + "ETSI", "5G", "20M", "HT", "1T", "108", "40", + "MKK", "5G", "20M", "HT", "1T", "108", "40", + "FCC", "5G", "20M", "HT", "1T", "112", "46", + "ETSI", "5G", "20M", "HT", "1T", "112", "40", + "MKK", "5G", "20M", "HT", "1T", "112", "40", + "FCC", "5G", "20M", "HT", "1T", "116", "46", + "ETSI", "5G", "20M", "HT", "1T", "116", "40", + "MKK", "5G", "20M", "HT", "1T", "116", "40", + "FCC", "5G", "20M", "HT", "1T", "120", "46", + "ETSI", "5G", "20M", "HT", "1T", "120", "40", + "MKK", "5G", "20M", "HT", "1T", "120", "40", + "FCC", "5G", "20M", "HT", "1T", "124", "46", + "ETSI", "5G", "20M", "HT", "1T", "124", "40", + "MKK", "5G", "20M", "HT", "1T", "124", "40", + "FCC", "5G", "20M", "HT", "1T", "128", "46", + "ETSI", "5G", "20M", "HT", "1T", "128", "40", + "MKK", "5G", "20M", "HT", "1T", "128", "40", + "FCC", "5G", "20M", "HT", "1T", "132", "46", + "ETSI", "5G", "20M", "HT", "1T", "132", "40", + "MKK", "5G", "20M", "HT", "1T", "132", "40", + "FCC", "5G", "20M", "HT", "1T", "136", "46", + "ETSI", "5G", "20M", "HT", "1T", "136", "40", + "MKK", "5G", "20M", "HT", "1T", "136", "40", + "FCC", "5G", "20M", "HT", "1T", "140", "46", + "ETSI", "5G", "20M", "HT", "1T", "140", "40", + "MKK", "5G", "20M", "HT", "1T", "140", "40", + "FCC", "5G", "20M", "HT", "1T", "149", "46", + "ETSI", "5G", "20M", "HT", "1T", "149", "40", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "46", + "ETSI", "5G", "20M", "HT", "1T", "153", "40", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "46", + "ETSI", "5G", "20M", "HT", "1T", "157", "40", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "46", + "ETSI", "5G", "20M", "HT", "1T", "161", "40", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "46", + "ETSI", "5G", "20M", "HT", "1T", "165", "40", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "46", + "ETSI", "5G", "20M", "HT", "2T", "36", "40", + "MKK", "5G", "20M", "HT", "2T", "36", "40", + "FCC", "5G", "20M", "HT", "2T", "40", "46", + "ETSI", "5G", "20M", "HT", "2T", "40", "40", + "MKK", "5G", "20M", "HT", "2T", "40", "40", + "FCC", "5G", "20M", "HT", "2T", "44", "46", + "ETSI", "5G", "20M", "HT", "2T", "44", "40", + "MKK", "5G", "20M", "HT", "2T", "44", "40", + "FCC", "5G", "20M", "HT", "2T", "48", "46", + "ETSI", "5G", "20M", "HT", "2T", "48", "40", + "MKK", "5G", "20M", "HT", "2T", "48", "40", + "FCC", "5G", "20M", "HT", "2T", "52", "46", + "ETSI", "5G", "20M", "HT", "2T", "52", "40", + "MKK", "5G", "20M", "HT", "2T", "52", "40", + "FCC", "5G", "20M", "HT", "2T", "56", "46", + "ETSI", "5G", "20M", "HT", "2T", "56", "40", + "MKK", "5G", "20M", "HT", "2T", "56", "40", + "FCC", "5G", "20M", "HT", "2T", "60", "46", + "ETSI", "5G", "20M", "HT", "2T", "60", "40", + "MKK", "5G", "20M", "HT", "2T", "60", "40", + "FCC", "5G", "20M", "HT", "2T", "64", "46", + "ETSI", "5G", "20M", "HT", "2T", "64", "40", + "MKK", "5G", "20M", "HT", "2T", "64", "40", + "FCC", "5G", "20M", "HT", "2T", "100", "46", + "ETSI", "5G", "20M", "HT", "2T", "100", "40", + "MKK", "5G", "20M", "HT", "2T", "100", "40", + "FCC", "5G", "20M", "HT", "2T", "104", "46", + "ETSI", "5G", "20M", "HT", "2T", "104", "40", + "MKK", "5G", "20M", "HT", "2T", "104", "40", + "FCC", "5G", "20M", "HT", "2T", "108", "46", + "ETSI", "5G", "20M", "HT", "2T", "108", "40", + "MKK", "5G", "20M", "HT", "2T", "108", "40", + "FCC", "5G", "20M", "HT", "2T", "112", "46", + "ETSI", "5G", "20M", "HT", "2T", "112", "40", + "MKK", "5G", "20M", "HT", "2T", "112", "40", + "FCC", "5G", "20M", "HT", "2T", "116", "46", + "ETSI", "5G", "20M", "HT", "2T", "116", "40", + "MKK", "5G", "20M", "HT", "2T", "116", "40", + "FCC", "5G", "20M", "HT", "2T", "120", "46", + "ETSI", "5G", "20M", "HT", "2T", "120", "40", + "MKK", "5G", "20M", "HT", "2T", "120", "40", + "FCC", "5G", "20M", "HT", "2T", "124", "46", + "ETSI", "5G", "20M", "HT", "2T", "124", "40", + "MKK", "5G", "20M", "HT", "2T", "124", "40", + "FCC", "5G", "20M", "HT", "2T", "128", "46", + "ETSI", "5G", "20M", "HT", "2T", "128", "40", + "MKK", "5G", "20M", "HT", "2T", "128", "40", + "FCC", "5G", "20M", "HT", "2T", "132", "46", + "ETSI", "5G", "20M", "HT", "2T", "132", "40", + "MKK", "5G", "20M", "HT", "2T", "132", "40", + "FCC", "5G", "20M", "HT", "2T", "136", "46", + "ETSI", "5G", "20M", "HT", "2T", "136", "40", + "MKK", "5G", "20M", "HT", "2T", "136", "40", + "FCC", "5G", "20M", "HT", "2T", "140", "46", + "ETSI", "5G", "20M", "HT", "2T", "140", "40", + "MKK", "5G", "20M", "HT", "2T", "140", "40", + "FCC", "5G", "20M", "HT", "2T", "149", "46", + "ETSI", "5G", "20M", "HT", "2T", "149", "40", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "46", + "ETSI", "5G", "20M", "HT", "2T", "153", "40", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "46", + "ETSI", "5G", "20M", "HT", "2T", "157", "40", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "46", + "ETSI", "5G", "20M", "HT", "2T", "161", "40", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "46", + "ETSI", "5G", "20M", "HT", "2T", "165", "40", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "46", + "ETSI", "5G", "20M", "HT", "3T", "36", "40", + "MKK", "5G", "20M", "HT", "3T", "36", "40", + "FCC", "5G", "20M", "HT", "3T", "40", "46", + "ETSI", "5G", "20M", "HT", "3T", "40", "40", + "MKK", "5G", "20M", "HT", "3T", "40", "40", + "FCC", "5G", "20M", "HT", "3T", "44", "46", + "ETSI", "5G", "20M", "HT", "3T", "44", "40", + "MKK", "5G", "20M", "HT", "3T", "44", "40", + "FCC", "5G", "20M", "HT", "3T", "48", "46", + "ETSI", "5G", "20M", "HT", "3T", "48", "40", + "MKK", "5G", "20M", "HT", "3T", "48", "40", + "FCC", "5G", "20M", "HT", "3T", "52", "46", + "ETSI", "5G", "20M", "HT", "3T", "52", "40", + "MKK", "5G", "20M", "HT", "3T", "52", "40", + "FCC", "5G", "20M", "HT", "3T", "56", "46", + "ETSI", "5G", "20M", "HT", "3T", "56", "40", + "MKK", "5G", "20M", "HT", "3T", "56", "40", + "FCC", "5G", "20M", "HT", "3T", "60", "46", + "ETSI", "5G", "20M", "HT", "3T", "60", "40", + "MKK", "5G", "20M", "HT", "3T", "60", "40", + "FCC", "5G", "20M", "HT", "3T", "64", "46", + "ETSI", "5G", "20M", "HT", "3T", "64", "40", + "MKK", "5G", "20M", "HT", "3T", "64", "40", + "FCC", "5G", "20M", "HT", "3T", "100", "46", + "ETSI", "5G", "20M", "HT", "3T", "100", "40", + "MKK", "5G", "20M", "HT", "3T", "100", "40", + "FCC", "5G", "20M", "HT", "3T", "104", "46", + "ETSI", "5G", "20M", "HT", "3T", "104", "40", + "MKK", "5G", "20M", "HT", "3T", "104", "40", + "FCC", "5G", "20M", "HT", "3T", "108", "46", + "ETSI", "5G", "20M", "HT", "3T", "108", "40", + "MKK", "5G", "20M", "HT", "3T", "108", "40", + "FCC", "5G", "20M", "HT", "3T", "112", "46", + "ETSI", "5G", "20M", "HT", "3T", "112", "40", + "MKK", "5G", "20M", "HT", "3T", "112", "40", + "FCC", "5G", "20M", "HT", "3T", "116", "46", + "ETSI", "5G", "20M", "HT", "3T", "116", "40", + "MKK", "5G", "20M", "HT", "3T", "116", "40", + "FCC", "5G", "20M", "HT", "3T", "120", "46", + "ETSI", "5G", "20M", "HT", "3T", "120", "40", + "MKK", "5G", "20M", "HT", "3T", "120", "40", + "FCC", "5G", "20M", "HT", "3T", "124", "46", + "ETSI", "5G", "20M", "HT", "3T", "124", "40", + "MKK", "5G", "20M", "HT", "3T", "124", "40", + "FCC", "5G", "20M", "HT", "3T", "128", "46", + "ETSI", "5G", "20M", "HT", "3T", "128", "40", + "MKK", "5G", "20M", "HT", "3T", "128", "40", + "FCC", "5G", "20M", "HT", "3T", "132", "46", + "ETSI", "5G", "20M", "HT", "3T", "132", "40", + "MKK", "5G", "20M", "HT", "3T", "132", "40", + "FCC", "5G", "20M", "HT", "3T", "136", "46", + "ETSI", "5G", "20M", "HT", "3T", "136", "40", + "MKK", "5G", "20M", "HT", "3T", "136", "40", + "FCC", "5G", "20M", "HT", "3T", "140", "46", + "ETSI", "5G", "20M", "HT", "3T", "140", "40", + "MKK", "5G", "20M", "HT", "3T", "140", "40", + "FCC", "5G", "20M", "HT", "3T", "149", "46", + "ETSI", "5G", "20M", "HT", "3T", "149", "40", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "46", + "ETSI", "5G", "20M", "HT", "3T", "153", "40", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "46", + "ETSI", "5G", "20M", "HT", "3T", "157", "40", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "46", + "ETSI", "5G", "20M", "HT", "3T", "161", "40", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "46", + "ETSI", "5G", "20M", "HT", "3T", "165", "40", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "46", + "ETSI", "5G", "20M", "HT", "4T", "36", "40", + "MKK", "5G", "20M", "HT", "4T", "36", "40", + "FCC", "5G", "20M", "HT", "4T", "40", "46", + "ETSI", "5G", "20M", "HT", "4T", "40", "40", + "MKK", "5G", "20M", "HT", "4T", "40", "40", + "FCC", "5G", "20M", "HT", "4T", "44", "46", + "ETSI", "5G", "20M", "HT", "4T", "44", "40", + "MKK", "5G", "20M", "HT", "4T", "44", "40", + "FCC", "5G", "20M", "HT", "4T", "48", "46", + "ETSI", "5G", "20M", "HT", "4T", "48", "40", + "MKK", "5G", "20M", "HT", "4T", "48", "40", + "FCC", "5G", "20M", "HT", "4T", "52", "46", + "ETSI", "5G", "20M", "HT", "4T", "52", "40", + "MKK", "5G", "20M", "HT", "4T", "52", "40", + "FCC", "5G", "20M", "HT", "4T", "56", "46", + "ETSI", "5G", "20M", "HT", "4T", "56", "40", + "MKK", "5G", "20M", "HT", "4T", "56", "40", + "FCC", "5G", "20M", "HT", "4T", "60", "46", + "ETSI", "5G", "20M", "HT", "4T", "60", "40", + "MKK", "5G", "20M", "HT", "4T", "60", "40", + "FCC", "5G", "20M", "HT", "4T", "64", "46", + "ETSI", "5G", "20M", "HT", "4T", "64", "40", + "MKK", "5G", "20M", "HT", "4T", "64", "40", + "FCC", "5G", "20M", "HT", "4T", "100", "46", + "ETSI", "5G", "20M", "HT", "4T", "100", "40", + "MKK", "5G", "20M", "HT", "4T", "100", "40", + "FCC", "5G", "20M", "HT", "4T", "104", "46", + "ETSI", "5G", "20M", "HT", "4T", "104", "40", + "MKK", "5G", "20M", "HT", "4T", "104", "40", + "FCC", "5G", "20M", "HT", "4T", "108", "46", + "ETSI", "5G", "20M", "HT", "4T", "108", "40", + "MKK", "5G", "20M", "HT", "4T", "108", "40", + "FCC", "5G", "20M", "HT", "4T", "112", "46", + "ETSI", "5G", "20M", "HT", "4T", "112", "40", + "MKK", "5G", "20M", "HT", "4T", "112", "40", + "FCC", "5G", "20M", "HT", "4T", "116", "46", + "ETSI", "5G", "20M", "HT", "4T", "116", "40", + "MKK", "5G", "20M", "HT", "4T", "116", "40", + "FCC", "5G", "20M", "HT", "4T", "120", "46", + "ETSI", "5G", "20M", "HT", "4T", "120", "40", + "MKK", "5G", "20M", "HT", "4T", "120", "40", + "FCC", "5G", "20M", "HT", "4T", "124", "46", + "ETSI", "5G", "20M", "HT", "4T", "124", "40", + "MKK", "5G", "20M", "HT", "4T", "124", "40", + "FCC", "5G", "20M", "HT", "4T", "128", "46", + "ETSI", "5G", "20M", "HT", "4T", "128", "40", + "MKK", "5G", "20M", "HT", "4T", "128", "40", + "FCC", "5G", "20M", "HT", "4T", "132", "46", + "ETSI", "5G", "20M", "HT", "4T", "132", "40", + "MKK", "5G", "20M", "HT", "4T", "132", "40", + "FCC", "5G", "20M", "HT", "4T", "136", "46", + "ETSI", "5G", "20M", "HT", "4T", "136", "40", + "MKK", "5G", "20M", "HT", "4T", "136", "40", + "FCC", "5G", "20M", "HT", "4T", "140", "46", + "ETSI", "5G", "20M", "HT", "4T", "140", "40", + "MKK", "5G", "20M", "HT", "4T", "140", "40", + "FCC", "5G", "20M", "HT", "4T", "149", "46", + "ETSI", "5G", "20M", "HT", "4T", "149", "40", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "46", + "ETSI", "5G", "20M", "HT", "4T", "153", "40", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "46", + "ETSI", "5G", "20M", "HT", "4T", "157", "40", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "46", + "ETSI", "5G", "20M", "HT", "4T", "161", "40", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "46", + "ETSI", "5G", "20M", "HT", "4T", "165", "40", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "46", + "ETSI", "5G", "40M", "HT", "1T", "38", "40", + "MKK", "5G", "40M", "HT", "1T", "38", "40", + "FCC", "5G", "40M", "HT", "1T", "46", "46", + "ETSI", "5G", "40M", "HT", "1T", "46", "40", + "MKK", "5G", "40M", "HT", "1T", "46", "40", + "FCC", "5G", "40M", "HT", "1T", "54", "46", + "ETSI", "5G", "40M", "HT", "1T", "54", "40", + "MKK", "5G", "40M", "HT", "1T", "54", "40", + "FCC", "5G", "40M", "HT", "1T", "62", "46", + "ETSI", "5G", "40M", "HT", "1T", "62", "40", + "MKK", "5G", "40M", "HT", "1T", "62", "40", + "FCC", "5G", "40M", "HT", "1T", "102", "46", + "ETSI", "5G", "40M", "HT", "1T", "102", "40", + "MKK", "5G", "40M", "HT", "1T", "102", "40", + "FCC", "5G", "40M", "HT", "1T", "110", "46", + "ETSI", "5G", "40M", "HT", "1T", "110", "40", + "MKK", "5G", "40M", "HT", "1T", "110", "40", + "FCC", "5G", "40M", "HT", "1T", "118", "46", + "ETSI", "5G", "40M", "HT", "1T", "118", "40", + "MKK", "5G", "40M", "HT", "1T", "118", "40", + "FCC", "5G", "40M", "HT", "1T", "126", "46", + "ETSI", "5G", "40M", "HT", "1T", "126", "40", + "MKK", "5G", "40M", "HT", "1T", "126", "40", + "FCC", "5G", "40M", "HT", "1T", "134", "46", + "ETSI", "5G", "40M", "HT", "1T", "134", "40", + "MKK", "5G", "40M", "HT", "1T", "134", "40", + "FCC", "5G", "40M", "HT", "1T", "151", "46", + "ETSI", "5G", "40M", "HT", "1T", "151", "40", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "46", + "ETSI", "5G", "40M", "HT", "1T", "159", "40", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "46", + "ETSI", "5G", "40M", "HT", "2T", "38", "40", + "MKK", "5G", "40M", "HT", "2T", "38", "40", + "FCC", "5G", "40M", "HT", "2T", "46", "46", + "ETSI", "5G", "40M", "HT", "2T", "46", "40", + "MKK", "5G", "40M", "HT", "2T", "46", "40", + "FCC", "5G", "40M", "HT", "2T", "54", "46", + "ETSI", "5G", "40M", "HT", "2T", "54", "40", + "MKK", "5G", "40M", "HT", "2T", "54", "40", + "FCC", "5G", "40M", "HT", "2T", "62", "46", + "ETSI", "5G", "40M", "HT", "2T", "62", "40", + "MKK", "5G", "40M", "HT", "2T", "62", "40", + "FCC", "5G", "40M", "HT", "2T", "102", "46", + "ETSI", "5G", "40M", "HT", "2T", "102", "40", + "MKK", "5G", "40M", "HT", "2T", "102", "40", + "FCC", "5G", "40M", "HT", "2T", "110", "46", + "ETSI", "5G", "40M", "HT", "2T", "110", "40", + "MKK", "5G", "40M", "HT", "2T", "110", "40", + "FCC", "5G", "40M", "HT", "2T", "118", "46", + "ETSI", "5G", "40M", "HT", "2T", "118", "40", + "MKK", "5G", "40M", "HT", "2T", "118", "40", + "FCC", "5G", "40M", "HT", "2T", "126", "46", + "ETSI", "5G", "40M", "HT", "2T", "126", "40", + "MKK", "5G", "40M", "HT", "2T", "126", "40", + "FCC", "5G", "40M", "HT", "2T", "134", "46", + "ETSI", "5G", "40M", "HT", "2T", "134", "40", + "MKK", "5G", "40M", "HT", "2T", "134", "40", + "FCC", "5G", "40M", "HT", "2T", "151", "46", + "ETSI", "5G", "40M", "HT", "2T", "151", "40", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "46", + "ETSI", "5G", "40M", "HT", "2T", "159", "40", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "46", + "ETSI", "5G", "40M", "HT", "3T", "38", "40", + "MKK", "5G", "40M", "HT", "3T", "38", "40", + "FCC", "5G", "40M", "HT", "3T", "46", "46", + "ETSI", "5G", "40M", "HT", "3T", "46", "40", + "MKK", "5G", "40M", "HT", "3T", "46", "40", + "FCC", "5G", "40M", "HT", "3T", "54", "46", + "ETSI", "5G", "40M", "HT", "3T", "54", "40", + "MKK", "5G", "40M", "HT", "3T", "54", "40", + "FCC", "5G", "40M", "HT", "3T", "62", "46", + "ETSI", "5G", "40M", "HT", "3T", "62", "40", + "MKK", "5G", "40M", "HT", "3T", "62", "40", + "FCC", "5G", "40M", "HT", "3T", "102", "46", + "ETSI", "5G", "40M", "HT", "3T", "102", "40", + "MKK", "5G", "40M", "HT", "3T", "102", "40", + "FCC", "5G", "40M", "HT", "3T", "110", "46", + "ETSI", "5G", "40M", "HT", "3T", "110", "40", + "MKK", "5G", "40M", "HT", "3T", "110", "40", + "FCC", "5G", "40M", "HT", "3T", "118", "46", + "ETSI", "5G", "40M", "HT", "3T", "118", "40", + "MKK", "5G", "40M", "HT", "3T", "118", "40", + "FCC", "5G", "40M", "HT", "3T", "126", "46", + "ETSI", "5G", "40M", "HT", "3T", "126", "40", + "MKK", "5G", "40M", "HT", "3T", "126", "40", + "FCC", "5G", "40M", "HT", "3T", "134", "46", + "ETSI", "5G", "40M", "HT", "3T", "134", "40", + "MKK", "5G", "40M", "HT", "3T", "134", "40", + "FCC", "5G", "40M", "HT", "3T", "151", "46", + "ETSI", "5G", "40M", "HT", "3T", "151", "40", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "46", + "ETSI", "5G", "40M", "HT", "3T", "159", "40", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "46", + "ETSI", "5G", "40M", "HT", "4T", "38", "40", + "MKK", "5G", "40M", "HT", "4T", "38", "40", + "FCC", "5G", "40M", "HT", "4T", "46", "46", + "ETSI", "5G", "40M", "HT", "4T", "46", "40", + "MKK", "5G", "40M", "HT", "4T", "46", "40", + "FCC", "5G", "40M", "HT", "4T", "54", "46", + "ETSI", "5G", "40M", "HT", "4T", "54", "40", + "MKK", "5G", "40M", "HT", "4T", "54", "40", + "FCC", "5G", "40M", "HT", "4T", "62", "46", + "ETSI", "5G", "40M", "HT", "4T", "62", "40", + "MKK", "5G", "40M", "HT", "4T", "62", "40", + "FCC", "5G", "40M", "HT", "4T", "102", "46", + "ETSI", "5G", "40M", "HT", "4T", "102", "40", + "MKK", "5G", "40M", "HT", "4T", "102", "40", + "FCC", "5G", "40M", "HT", "4T", "110", "46", + "ETSI", "5G", "40M", "HT", "4T", "110", "40", + "MKK", "5G", "40M", "HT", "4T", "110", "40", + "FCC", "5G", "40M", "HT", "4T", "118", "46", + "ETSI", "5G", "40M", "HT", "4T", "118", "40", + "MKK", "5G", "40M", "HT", "4T", "118", "40", + "FCC", "5G", "40M", "HT", "4T", "126", "46", + "ETSI", "5G", "40M", "HT", "4T", "126", "40", + "MKK", "5G", "40M", "HT", "4T", "126", "40", + "FCC", "5G", "40M", "HT", "4T", "134", "46", + "ETSI", "5G", "40M", "HT", "4T", "134", "40", + "MKK", "5G", "40M", "HT", "4T", "134", "40", + "FCC", "5G", "40M", "HT", "4T", "151", "46", + "ETSI", "5G", "40M", "HT", "4T", "151", "40", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "46", + "ETSI", "5G", "40M", "HT", "4T", "159", "40", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "46", + "ETSI", "5G", "80M", "VHT", "1T", "42", "40", + "MKK", "5G", "80M", "VHT", "1T", "42", "40", + "FCC", "5G", "80M", "VHT", "1T", "58", "46", + "ETSI", "5G", "80M", "VHT", "1T", "58", "40", + "MKK", "5G", "80M", "VHT", "1T", "58", "40", + "FCC", "5G", "80M", "VHT", "1T", "106", "46", + "ETSI", "5G", "80M", "VHT", "1T", "106", "40", + "MKK", "5G", "80M", "VHT", "1T", "106", "40", + "FCC", "5G", "80M", "VHT", "1T", "122", "46", + "ETSI", "5G", "80M", "VHT", "1T", "122", "40", + "MKK", "5G", "80M", "VHT", "1T", "122", "40", + "FCC", "5G", "80M", "VHT", "1T", "155", "46", + "ETSI", "5G", "80M", "VHT", "1T", "155", "40", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "46", + "ETSI", "5G", "80M", "VHT", "2T", "42", "40", + "MKK", "5G", "80M", "VHT", "2T", "42", "40", + "FCC", "5G", "80M", "VHT", "2T", "58", "46", + "ETSI", "5G", "80M", "VHT", "2T", "58", "40", + "MKK", "5G", "80M", "VHT", "2T", "58", "40", + "FCC", "5G", "80M", "VHT", "2T", "106", "46", + "ETSI", "5G", "80M", "VHT", "2T", "106", "40", + "MKK", "5G", "80M", "VHT", "2T", "106", "40", + "FCC", "5G", "80M", "VHT", "2T", "122", "46", + "ETSI", "5G", "80M", "VHT", "2T", "122", "40", + "MKK", "5G", "80M", "VHT", "2T", "122", "40", + "FCC", "5G", "80M", "VHT", "2T", "155", "46", + "ETSI", "5G", "80M", "VHT", "2T", "155", "40", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "46", + "ETSI", "5G", "80M", "VHT", "3T", "42", "40", + "MKK", "5G", "80M", "VHT", "3T", "42", "40", + "FCC", "5G", "80M", "VHT", "3T", "58", "46", + "ETSI", "5G", "80M", "VHT", "3T", "58", "40", + "MKK", "5G", "80M", "VHT", "3T", "58", "40", + "FCC", "5G", "80M", "VHT", "3T", "106", "46", + "ETSI", "5G", "80M", "VHT", "3T", "106", "40", + "MKK", "5G", "80M", "VHT", "3T", "106", "40", + "FCC", "5G", "80M", "VHT", "3T", "122", "46", + "ETSI", "5G", "80M", "VHT", "3T", "122", "40", + "MKK", "5G", "80M", "VHT", "3T", "122", "40", + "FCC", "5G", "80M", "VHT", "3T", "155", "46", + "ETSI", "5G", "80M", "VHT", "3T", "155", "40", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "46", + "ETSI", "5G", "80M", "VHT", "4T", "42", "40", + "MKK", "5G", "80M", "VHT", "4T", "42", "40", + "FCC", "5G", "80M", "VHT", "4T", "58", "46", + "ETSI", "5G", "80M", "VHT", "4T", "58", "40", + "MKK", "5G", "80M", "VHT", "4T", "58", "40", + "FCC", "5G", "80M", "VHT", "4T", "106", "46", + "ETSI", "5G", "80M", "VHT", "4T", "106", "40", + "MKK", "5G", "80M", "VHT", "4T", "106", "40", + "FCC", "5G", "80M", "VHT", "4T", "122", "46", + "ETSI", "5G", "80M", "VHT", "4T", "122", "40", + "MKK", "5G", "80M", "VHT", "4T", "122", "40", + "FCC", "5G", "80M", "VHT", "4T", "155", "46", + "ETSI", "5G", "80M", "VHT", "4T", "155", "40", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type5)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type5; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type5)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type5; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type6.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type6[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", 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"30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", + "MKK", "2.4G", "40M", "HT", "2T", "12", "30", + "FCC", "2.4G", "40M", "HT", "2T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", + "MKK", "2.4G", "40M", "HT", "2T", "13", "30", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "22", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", + "MKK", "2.4G", "40M", "HT", "3T", "03", "28", + "FCC", "2.4G", "40M", "HT", "3T", "04", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", + "MKK", "2.4G", "40M", "HT", "3T", "04", "28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "20", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "14", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "8", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "26", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "26", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "26", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "24", + "ETSI", "5G", "20M", "HT", "2T", "36", "28", + "MKK", "5G", "20M", "HT", "2T", "36", "28", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "28", + "MKK", "5G", "20M", "HT", "2T", "40", "28", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "28", + "MKK", "5G", "20M", "HT", "2T", "44", "28", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "28", + "MKK", "5G", "20M", "HT", "2T", "48", "28", + "FCC", "5G", "20M", "HT", "2T", "52", "28", + "ETSI", "5G", "20M", "HT", "2T", "52", "28", + "MKK", "5G", "20M", "HT", "2T", "52", "28", + "FCC", "5G", "20M", "HT", "2T", "56", "28", + "ETSI", "5G", "20M", "HT", "2T", "56", "28", + "MKK", "5G", "20M", "HT", "2T", "56", "28", + "FCC", "5G", "20M", "HT", "2T", "60", "28", + "ETSI", "5G", "20M", "HT", "2T", "60", "28", + "MKK", "5G", "20M", "HT", "2T", "60", "28", + "FCC", "5G", "20M", "HT", "2T", "64", "24", + "ETSI", "5G", "20M", "HT", "2T", "64", "28", + "MKK", "5G", "20M", "HT", "2T", "64", "28", + "FCC", "5G", "20M", "HT", "2T", "100", "24", + "ETSI", "5G", "20M", "HT", "2T", "100", "28", + "MKK", "5G", "20M", "HT", "2T", "100", "28", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "28", + "MKK", "5G", "20M", "HT", "2T", "104", "28", + "FCC", "5G", "20M", "HT", "2T", "108", "28", + "ETSI", "5G", "20M", "HT", "2T", "108", "28", + "MKK", "5G", "20M", "HT", "2T", "108", "28", + "FCC", "5G", "20M", "HT", "2T", "112", "28", + "ETSI", "5G", "20M", "HT", "2T", "112", "28", + "MKK", "5G", "20M", "HT", "2T", "112", "28", + "FCC", "5G", "20M", "HT", "2T", "116", "28", + "ETSI", "5G", "20M", "HT", "2T", "116", "28", + "MKK", "5G", "20M", "HT", "2T", "116", "28", + "FCC", "5G", "20M", "HT", "2T", "120", "28", + "ETSI", "5G", "20M", "HT", "2T", "120", "28", + "MKK", "5G", "20M", "HT", "2T", "120", "28", + "FCC", "5G", "20M", "HT", "2T", "124", "28", + "ETSI", "5G", "20M", "HT", "2T", "124", "28", + "MKK", "5G", "20M", "HT", "2T", "124", "28", + "FCC", "5G", "20M", "HT", "2T", "128", "28", + "ETSI", "5G", "20M", "HT", "2T", "128", "28", + "MKK", "5G", "20M", "HT", "2T", "128", "28", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "28", + "MKK", "5G", "20M", "HT", "2T", "132", "28", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "28", + "MKK", "5G", "20M", "HT", "2T", "136", "28", + "FCC", "5G", "20M", "HT", "2T", "140", "24", + "ETSI", "5G", "20M", "HT", "2T", "140", "28", + "MKK", "5G", "20M", "HT", "2T", "140", "28", + "FCC", "5G", "20M", "HT", "2T", "149", "24", + "ETSI", "5G", "20M", "HT", "2T", "149", "28", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "28", + "ETSI", "5G", "20M", "HT", "2T", "153", "28", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "28", + "ETSI", "5G", "20M", "HT", "2T", "157", "28", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "28", + "ETSI", "5G", "20M", "HT", "2T", "161", "28", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "28", + "ETSI", "5G", "20M", "HT", "2T", "165", "28", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "22", + "ETSI", "5G", "20M", "HT", "3T", "36", "26", + "MKK", "5G", "20M", "HT", "3T", "36", "26", + "FCC", "5G", "20M", "HT", "3T", "40", "26", + "ETSI", "5G", "20M", "HT", "3T", "40", "26", + "MKK", "5G", "20M", "HT", "3T", "40", "26", + "FCC", "5G", "20M", "HT", "3T", "44", "26", + "ETSI", "5G", "20M", "HT", "3T", "44", "26", + "MKK", "5G", "20M", "HT", "3T", "44", "26", + "FCC", "5G", "20M", "HT", "3T", "48", "26", + "ETSI", "5G", "20M", "HT", "3T", "48", "26", + "MKK", "5G", "20M", "HT", "3T", "48", "26", + "FCC", "5G", "20M", "HT", "3T", "52", "26", + "ETSI", "5G", "20M", "HT", "3T", "52", "26", + "MKK", "5G", "20M", "HT", "3T", "52", "26", + "FCC", "5G", "20M", "HT", "3T", "56", "26", + "ETSI", "5G", "20M", "HT", "3T", "56", "26", + "MKK", "5G", "20M", "HT", "3T", "56", "26", + "FCC", "5G", "20M", "HT", "3T", "60", "26", + "ETSI", "5G", "20M", "HT", "3T", "60", "26", + "MKK", "5G", "20M", "HT", "3T", "60", "26", + "FCC", "5G", "20M", "HT", "3T", "64", "22", + "ETSI", "5G", "20M", "HT", "3T", "64", "26", + "MKK", "5G", "20M", "HT", "3T", "64", "26", + "FCC", "5G", "20M", "HT", "3T", "100", "22", + "ETSI", "5G", "20M", "HT", "3T", "100", "26", + "MKK", "5G", "20M", "HT", "3T", "100", "26", + "FCC", "5G", "20M", "HT", "3T", "104", "26", + "ETSI", "5G", "20M", "HT", "3T", "104", "26", + "MKK", "5G", "20M", "HT", "3T", "104", "26", + "FCC", "5G", "20M", "HT", "3T", "108", "26", + "ETSI", "5G", "20M", "HT", "3T", "108", "26", + "MKK", "5G", "20M", "HT", "3T", "108", "26", + "FCC", "5G", "20M", "HT", "3T", "112", "26", + "ETSI", "5G", "20M", "HT", "3T", "112", "26", + "MKK", "5G", "20M", "HT", "3T", "112", "26", + "FCC", "5G", "20M", "HT", "3T", "116", "26", + "ETSI", "5G", "20M", "HT", "3T", "116", "26", + "MKK", "5G", "20M", "HT", "3T", "116", "26", + "FCC", "5G", "20M", "HT", "3T", "120", "26", + "ETSI", "5G", "20M", "HT", "3T", "120", "26", + "MKK", "5G", "20M", "HT", "3T", "120", "26", + "FCC", "5G", "20M", "HT", "3T", "124", "26", + "ETSI", "5G", "20M", "HT", "3T", "124", "26", + "MKK", "5G", "20M", "HT", "3T", "124", "26", + "FCC", "5G", "20M", "HT", "3T", "128", "26", + "ETSI", "5G", "20M", "HT", "3T", "128", "26", + "MKK", "5G", "20M", "HT", "3T", "128", "26", + "FCC", "5G", "20M", "HT", "3T", "132", "26", + "ETSI", "5G", "20M", "HT", "3T", "132", "26", + "MKK", "5G", "20M", "HT", "3T", "132", "26", + "FCC", "5G", "20M", "HT", "3T", "136", "26", + "ETSI", "5G", "20M", "HT", "3T", "136", "26", + "MKK", "5G", "20M", "HT", "3T", "136", "26", + "FCC", "5G", "20M", "HT", "3T", "140", "22", + "ETSI", "5G", "20M", "HT", "3T", "140", "26", + "MKK", "5G", "20M", "HT", "3T", "140", "26", + "FCC", "5G", "20M", "HT", "3T", "149", "22", + "ETSI", "5G", "20M", "HT", "3T", "149", "26", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "26", + "ETSI", "5G", "20M", "HT", "3T", "153", "26", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "26", + "ETSI", "5G", "20M", "HT", "3T", "157", "26", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "26", + "ETSI", "5G", "20M", "HT", "3T", "161", "26", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "26", + "ETSI", "5G", "20M", "HT", "3T", "165", "26", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "20", + "ETSI", "5G", "20M", "HT", "4T", "36", "24", + "MKK", "5G", "20M", "HT", "4T", "36", "24", + "FCC", "5G", "20M", "HT", "4T", "40", "24", + "ETSI", "5G", "20M", "HT", "4T", "40", "24", + "MKK", "5G", "20M", "HT", "4T", "40", "24", + "FCC", "5G", "20M", "HT", "4T", "44", "24", + "ETSI", "5G", "20M", "HT", "4T", "44", "24", + "MKK", "5G", "20M", "HT", "4T", "44", "24", + "FCC", "5G", "20M", "HT", "4T", "48", "24", + "ETSI", "5G", "20M", "HT", "4T", "48", "24", + "MKK", "5G", "20M", "HT", "4T", "48", "24", + "FCC", "5G", "20M", "HT", "4T", "52", "24", + "ETSI", "5G", "20M", "HT", "4T", "52", "24", + "MKK", "5G", "20M", "HT", "4T", "52", "24", + "FCC", "5G", "20M", "HT", "4T", "56", "24", + "ETSI", "5G", "20M", "HT", "4T", "56", "24", + "MKK", "5G", "20M", "HT", "4T", "56", "24", + "FCC", "5G", "20M", "HT", "4T", "60", "24", + "ETSI", "5G", "20M", "HT", "4T", "60", "24", + "MKK", "5G", "20M", "HT", "4T", "60", "24", + "FCC", "5G", "20M", "HT", "4T", "64", "20", + "ETSI", "5G", "20M", "HT", "4T", "64", "24", + "MKK", "5G", "20M", "HT", "4T", "64", "24", + "FCC", "5G", "20M", "HT", "4T", "100", "20", + "ETSI", "5G", "20M", "HT", "4T", "100", "24", + "MKK", "5G", "20M", "HT", "4T", "100", "24", + "FCC", "5G", "20M", "HT", "4T", "104", "24", + "ETSI", "5G", "20M", "HT", "4T", "104", "24", + "MKK", "5G", "20M", "HT", "4T", "104", "24", + "FCC", "5G", "20M", "HT", "4T", "108", "24", + "ETSI", "5G", "20M", "HT", "4T", "108", "24", + "MKK", "5G", "20M", "HT", "4T", "108", "24", + "FCC", "5G", "20M", "HT", "4T", "112", "24", + "ETSI", "5G", "20M", "HT", "4T", "112", "24", + "MKK", "5G", "20M", "HT", "4T", "112", "24", + "FCC", "5G", "20M", "HT", "4T", "116", "24", + "ETSI", "5G", "20M", "HT", "4T", "116", "24", + "MKK", "5G", "20M", "HT", "4T", "116", "24", + "FCC", "5G", "20M", "HT", "4T", "120", "24", + "ETSI", "5G", "20M", "HT", "4T", "120", "24", + "MKK", "5G", "20M", "HT", "4T", "120", "24", + "FCC", "5G", "20M", "HT", "4T", "124", "24", + "ETSI", "5G", "20M", "HT", "4T", "124", "24", + "MKK", "5G", "20M", "HT", "4T", "124", "24", + "FCC", "5G", "20M", "HT", "4T", "128", "24", + "ETSI", "5G", "20M", "HT", "4T", "128", "24", + "MKK", "5G", "20M", "HT", "4T", "128", "24", + "FCC", "5G", "20M", "HT", "4T", "132", "24", + "ETSI", "5G", "20M", "HT", "4T", "132", "24", + "MKK", "5G", "20M", "HT", "4T", "132", "24", + "FCC", "5G", "20M", "HT", "4T", "136", "24", + "ETSI", "5G", "20M", "HT", "4T", "136", "24", + "MKK", "5G", "20M", "HT", "4T", "136", "24", + "FCC", "5G", "20M", "HT", "4T", "140", "20", + "ETSI", "5G", "20M", "HT", "4T", "140", "24", + "MKK", "5G", "20M", "HT", "4T", "140", "24", + "FCC", "5G", "20M", "HT", "4T", "149", "20", + "ETSI", "5G", "20M", "HT", "4T", "149", "24", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "24", + "ETSI", "5G", "20M", "HT", "4T", "153", "24", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "24", + "ETSI", "5G", "20M", "HT", "4T", "157", "24", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "24", + "ETSI", "5G", "20M", "HT", "4T", "161", "24", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "24", + "ETSI", "5G", "20M", "HT", "4T", "165", "24", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "26", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "26", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "26", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "24", + "ETSI", "5G", "40M", "HT", "2T", "38", "28", + "MKK", "5G", "40M", "HT", "2T", "38", "28", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "28", + "MKK", "5G", "40M", "HT", "2T", "46", "28", + "FCC", "5G", "40M", "HT", "2T", "54", "28", + "ETSI", "5G", "40M", "HT", "2T", "54", "28", + "MKK", "5G", "40M", "HT", "2T", "54", "28", + "FCC", "5G", "40M", "HT", "2T", "62", "24", + "ETSI", "5G", "40M", "HT", "2T", "62", "28", + "MKK", "5G", "40M", "HT", "2T", "62", "28", + "FCC", "5G", "40M", "HT", "2T", "102", "24", + "ETSI", "5G", "40M", "HT", "2T", "102", "28", + "MKK", "5G", "40M", "HT", "2T", "102", "28", + "FCC", "5G", "40M", "HT", "2T", "110", "28", + "ETSI", "5G", "40M", "HT", "2T", "110", "28", + "MKK", "5G", "40M", "HT", "2T", "110", "28", + "FCC", "5G", "40M", "HT", "2T", "118", "28", + "ETSI", "5G", "40M", "HT", "2T", "118", "28", + "MKK", "5G", "40M", "HT", "2T", "118", "28", + "FCC", "5G", "40M", "HT", "2T", "126", "28", + "ETSI", "5G", "40M", "HT", "2T", "126", "28", + "MKK", "5G", "40M", "HT", "2T", "126", "28", + "FCC", "5G", "40M", "HT", "2T", "134", "28", + "ETSI", "5G", "40M", "HT", "2T", "134", "28", + "MKK", "5G", "40M", "HT", "2T", "134", "28", + "FCC", "5G", "40M", "HT", "2T", "151", "24", + "ETSI", "5G", "40M", "HT", "2T", "151", "28", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "28", + "ETSI", "5G", "40M", "HT", "2T", "159", "28", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "20", + "ETSI", "5G", "40M", "HT", "3T", "38", "26", + "MKK", "5G", "40M", "HT", "3T", "38", "26", + "FCC", "5G", "40M", "HT", "3T", "46", "26", + "ETSI", "5G", "40M", "HT", "3T", "46", "26", + "MKK", "5G", "40M", "HT", "3T", "46", "26", + "FCC", "5G", "40M", "HT", "3T", "54", "26", + "ETSI", "5G", "40M", "HT", "3T", "54", "26", + "MKK", "5G", "40M", "HT", "3T", "54", "26", + "FCC", "5G", "40M", "HT", "3T", "62", "20", + "ETSI", "5G", "40M", "HT", "3T", "62", "26", + "MKK", "5G", "40M", "HT", "3T", "62", "26", + "FCC", "5G", "40M", "HT", "3T", "102", "20", + "ETSI", "5G", "40M", "HT", "3T", "102", "26", + "MKK", "5G", "40M", "HT", "3T", "102", "26", + "FCC", "5G", "40M", "HT", "3T", "110", "26", + "ETSI", "5G", "40M", "HT", "3T", "110", "26", + "MKK", "5G", "40M", "HT", "3T", "110", "26", + "FCC", "5G", "40M", "HT", "3T", "118", "26", + "ETSI", "5G", "40M", "HT", "3T", "118", "26", + "MKK", "5G", "40M", "HT", "3T", "118", "26", + "FCC", "5G", "40M", "HT", "3T", "126", "26", + "ETSI", "5G", "40M", "HT", "3T", "126", "26", + "MKK", "5G", "40M", "HT", "3T", "126", "26", + "FCC", "5G", "40M", "HT", "3T", "134", "26", + "ETSI", "5G", "40M", "HT", "3T", "134", "26", + "MKK", "5G", "40M", "HT", "3T", "134", "26", + "FCC", "5G", "40M", "HT", "3T", "151", "20", + "ETSI", "5G", "40M", "HT", "3T", "151", "26", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "26", + "ETSI", "5G", "40M", "HT", "3T", "159", "26", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "18", + "ETSI", "5G", "40M", "HT", "4T", "38", "24", + "MKK", "5G", "40M", "HT", "4T", "38", "24", + "FCC", "5G", "40M", "HT", "4T", "46", "24", + "ETSI", "5G", "40M", "HT", "4T", "46", "24", + "MKK", "5G", "40M", "HT", "4T", "46", "24", + "FCC", "5G", "40M", "HT", "4T", "54", "24", + "ETSI", "5G", "40M", "HT", "4T", "54", "24", + "MKK", "5G", "40M", "HT", "4T", "54", "24", + "FCC", "5G", "40M", "HT", "4T", "62", "18", + "ETSI", "5G", "40M", "HT", "4T", "62", "24", + "MKK", "5G", "40M", "HT", "4T", "62", "24", + "FCC", "5G", "40M", "HT", "4T", "102", "18", + "ETSI", "5G", "40M", "HT", "4T", "102", "24", + "MKK", "5G", "40M", "HT", "4T", "102", "24", + "FCC", "5G", "40M", "HT", "4T", "110", "24", + "ETSI", "5G", "40M", "HT", "4T", "110", "24", + "MKK", "5G", "40M", "HT", "4T", "110", "24", + "FCC", "5G", "40M", "HT", "4T", "118", "24", + "ETSI", "5G", "40M", "HT", "4T", "118", "24", + "MKK", "5G", "40M", "HT", "4T", "118", "24", + "FCC", "5G", "40M", "HT", "4T", "126", "24", + "ETSI", "5G", "40M", "HT", "4T", "126", "24", + "MKK", "5G", "40M", "HT", "4T", "126", "24", + "FCC", "5G", "40M", "HT", "4T", "134", "24", + "ETSI", "5G", "40M", "HT", "4T", "134", "24", + "MKK", "5G", "40M", "HT", "4T", "134", "24", + "FCC", "5G", "40M", "HT", "4T", "151", "18", + "ETSI", "5G", "40M", "HT", "4T", "151", "24", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "24", + "ETSI", "5G", "40M", "HT", "4T", "159", "24", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "22", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "22", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "22", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "20", + "ETSI", "5G", "80M", "VHT", "2T", "42", "28", + "MKK", "5G", "80M", "VHT", "2T", "42", "28", + "FCC", "5G", "80M", "VHT", "2T", "58", "20", + "ETSI", "5G", "80M", "VHT", "2T", "58", "28", + "MKK", "5G", "80M", "VHT", "2T", "58", "28", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "28", + "MKK", "5G", "80M", "VHT", "2T", "106", "28", + "FCC", "5G", "80M", "VHT", "2T", "122", "28", + "ETSI", "5G", "80M", "VHT", "2T", "122", "28", + "MKK", "5G", "80M", "VHT", "2T", "122", "28", + "FCC", "5G", "80M", "VHT", "2T", "155", "20", + "ETSI", "5G", "80M", "VHT", "2T", "155", "28", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "18", + "ETSI", "5G", "80M", "VHT", "3T", "42", "26", + "MKK", "5G", "80M", "VHT", "3T", "42", "26", + "FCC", "5G", "80M", "VHT", "3T", "58", "18", + "ETSI", "5G", "80M", "VHT", "3T", "58", "26", + "MKK", "5G", "80M", "VHT", "3T", "58", "26", + "FCC", "5G", "80M", "VHT", "3T", "106", "18", + "ETSI", "5G", "80M", "VHT", "3T", "106", "26", + "MKK", "5G", "80M", "VHT", "3T", "106", "26", + "FCC", "5G", "80M", "VHT", "3T", "122", "26", + "ETSI", "5G", "80M", "VHT", "3T", "122", "26", + "MKK", "5G", "80M", "VHT", "3T", "122", "26", + "FCC", "5G", "80M", "VHT", "3T", "155", "18", + "ETSI", "5G", "80M", "VHT", "3T", "155", "26", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "16", + "ETSI", "5G", "80M", "VHT", "4T", "42", "24", + "MKK", "5G", "80M", "VHT", "4T", "42", "24", + "FCC", "5G", "80M", "VHT", "4T", "58", "16", + "ETSI", "5G", "80M", "VHT", "4T", "58", "24", + "MKK", "5G", "80M", "VHT", "4T", "58", "24", + "FCC", "5G", "80M", "VHT", "4T", "106", "16", + "ETSI", "5G", "80M", "VHT", "4T", "106", "24", + "MKK", "5G", "80M", "VHT", "4T", "106", "24", + "FCC", "5G", "80M", "VHT", "4T", "122", "24", + "ETSI", "5G", "80M", "VHT", "4T", "122", "24", + "MKK", "5G", "80M", "VHT", "4T", "122", "24", + "FCC", "5G", "80M", "VHT", "4T", "155", "16", + "ETSI", "5G", "80M", "VHT", "4T", "155", "24", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type6)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type6; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type6)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type6; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type7.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type7[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "44", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "52", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "44", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "38", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", 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"MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "40", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", + "MKK", "2.4G", "40M", "HT", "1T", "12", "32", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", + "MKK", "2.4G", "40M", "HT", "1T", "13", "32", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "38", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", + "MKK", "2.4G", "40M", "HT", "2T", "12", "30", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", + "MKK", "2.4G", "40M", "HT", "2T", "13", "30", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", + "MKK", "2.4G", "40M", "HT", "3T", "03", "28", + "FCC", "2.4G", "40M", "HT", "3T", "04", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", + "MKK", "2.4G", "40M", "HT", "3T", "04", "28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "36", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "32", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "36", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "36", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "36", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "36", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "36", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "36", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "36", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "36", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "36", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "36", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "36", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "36", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "36", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "36", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "36", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "36", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "36", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "36", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "34", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "38", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "38", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "38", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "38", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "34", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "34", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "34", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "34", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "34", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "34", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "34", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "34", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "34", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "34", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "34", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "34", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "34", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "34", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "32", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "30", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "36", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "36", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "36", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "36", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "32", + "ETSI", "5G", "20M", "HT", "3T", "36", "28", + "MKK", "5G", "20M", "HT", "3T", "36", "28", + "FCC", "5G", "20M", "HT", "3T", "40", "32", + "ETSI", "5G", "20M", "HT", "3T", "40", "28", + "MKK", "5G", "20M", "HT", "3T", "40", "28", + "FCC", "5G", "20M", "HT", "3T", "44", "32", + "ETSI", "5G", "20M", "HT", "3T", "44", "28", + "MKK", "5G", "20M", "HT", "3T", "44", "28", + "FCC", "5G", "20M", "HT", "3T", "48", "32", + "ETSI", "5G", "20M", "HT", "3T", "48", "28", + "MKK", "5G", "20M", "HT", "3T", "48", "28", + "FCC", "5G", "20M", "HT", "3T", "52", "32", + "ETSI", "5G", "20M", "HT", "3T", "52", "28", + "MKK", "5G", "20M", "HT", "3T", "52", "28", + "FCC", "5G", "20M", "HT", "3T", "56", "32", + "ETSI", "5G", "20M", "HT", "3T", "56", "28", + "MKK", "5G", "20M", "HT", "3T", "56", "28", + "FCC", "5G", "20M", "HT", "3T", "60", "32", + "ETSI", "5G", "20M", "HT", "3T", "60", "28", + "MKK", "5G", "20M", "HT", "3T", "60", "28", + "FCC", "5G", "20M", "HT", "3T", "64", "32", + "ETSI", "5G", "20M", "HT", "3T", "64", "28", + "MKK", "5G", "20M", "HT", "3T", "64", "28", + "FCC", "5G", "20M", "HT", "3T", "100", "32", + "ETSI", "5G", "20M", "HT", "3T", "100", "28", + "MKK", "5G", "20M", "HT", "3T", "100", "28", + "FCC", "5G", "20M", "HT", "3T", "104", "32", + "ETSI", "5G", "20M", "HT", "3T", "104", "28", + "MKK", "5G", "20M", "HT", "3T", "104", "28", + "FCC", "5G", "20M", "HT", "3T", "108", "32", + "ETSI", "5G", "20M", "HT", "3T", "108", "28", + "MKK", "5G", "20M", "HT", "3T", "108", "28", + "FCC", "5G", "20M", "HT", "3T", "112", "32", + "ETSI", "5G", "20M", "HT", "3T", "112", "28", + "MKK", "5G", "20M", "HT", "3T", "112", "28", + "FCC", "5G", "20M", "HT", "3T", "116", "32", + "ETSI", "5G", "20M", "HT", "3T", "116", "28", + "MKK", "5G", "20M", "HT", "3T", "116", "28", + "FCC", "5G", "20M", "HT", "3T", "120", "32", + "ETSI", "5G", "20M", "HT", "3T", "120", "28", + "MKK", "5G", "20M", "HT", "3T", "120", "28", + "FCC", "5G", "20M", "HT", "3T", "124", "32", + "ETSI", "5G", "20M", "HT", "3T", "124", "28", + "MKK", "5G", "20M", "HT", "3T", "124", "28", + "FCC", "5G", "20M", "HT", "3T", "128", "32", + "ETSI", "5G", "20M", "HT", "3T", "128", "28", + "MKK", "5G", "20M", "HT", "3T", "128", "28", + "FCC", "5G", "20M", "HT", "3T", "132", "32", + "ETSI", "5G", "20M", "HT", "3T", "132", "28", + "MKK", "5G", "20M", "HT", "3T", "132", "28", + "FCC", "5G", "20M", "HT", "3T", "136", "32", + "ETSI", "5G", "20M", "HT", "3T", "136", "28", + "MKK", "5G", "20M", "HT", "3T", "136", "28", + "FCC", "5G", "20M", "HT", "3T", "140", "30", + "ETSI", "5G", "20M", "HT", "3T", "140", "28", + "MKK", "5G", "20M", "HT", "3T", "140", "28", + "FCC", "5G", "20M", "HT", "3T", "149", "28", + "ETSI", "5G", "20M", "HT", "3T", "149", "28", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "34", + "ETSI", "5G", "20M", "HT", "3T", "153", "28", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "34", + "ETSI", "5G", "20M", "HT", "3T", "157", "28", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "34", + "ETSI", "5G", "20M", "HT", "3T", "161", "28", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "34", + "ETSI", "5G", "20M", "HT", "3T", "165", "28", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "30", + "ETSI", "5G", "20M", "HT", "4T", "36", "26", + "MKK", "5G", "20M", "HT", "4T", "36", "26", + "FCC", "5G", "20M", "HT", "4T", "40", "30", + "ETSI", "5G", "20M", "HT", "4T", "40", "26", + "MKK", "5G", "20M", "HT", "4T", "40", "26", + "FCC", "5G", "20M", "HT", "4T", "44", "30", + "ETSI", "5G", "20M", "HT", "4T", "44", "26", + "MKK", "5G", "20M", "HT", "4T", "44", "26", + "FCC", "5G", "20M", "HT", "4T", "48", "30", + "ETSI", "5G", "20M", "HT", "4T", "48", "26", + "MKK", "5G", "20M", "HT", "4T", "48", "26", + "FCC", "5G", "20M", "HT", "4T", "52", "30", + "ETSI", "5G", "20M", "HT", "4T", "52", "26", + "MKK", "5G", "20M", "HT", "4T", "52", "26", + "FCC", "5G", "20M", "HT", "4T", "56", "30", + "ETSI", "5G", "20M", "HT", "4T", "56", "26", + "MKK", "5G", "20M", "HT", "4T", "56", "26", + "FCC", "5G", "20M", "HT", "4T", "60", "30", + "ETSI", "5G", "20M", "HT", "4T", "60", "26", + "MKK", "5G", "20M", "HT", "4T", "60", "26", + "FCC", "5G", "20M", "HT", "4T", "64", "30", + "ETSI", "5G", "20M", "HT", "4T", "64", "26", + "MKK", "5G", "20M", "HT", "4T", "64", "26", + "FCC", "5G", "20M", "HT", "4T", "100", "30", + "ETSI", "5G", "20M", "HT", "4T", "100", "26", + "MKK", "5G", "20M", "HT", "4T", "100", "26", + "FCC", "5G", "20M", "HT", "4T", "104", "30", + "ETSI", "5G", "20M", "HT", "4T", "104", "26", + "MKK", "5G", "20M", "HT", "4T", "104", "26", + "FCC", "5G", "20M", "HT", "4T", "108", "30", + "ETSI", "5G", "20M", "HT", "4T", "108", "26", + "MKK", "5G", "20M", "HT", "4T", "108", "26", + "FCC", "5G", "20M", "HT", "4T", "112", "30", + "ETSI", "5G", "20M", "HT", "4T", "112", "26", + "MKK", "5G", "20M", "HT", "4T", "112", "26", + "FCC", "5G", "20M", "HT", "4T", "116", "30", + "ETSI", "5G", "20M", "HT", "4T", "116", "26", + "MKK", "5G", "20M", "HT", "4T", "116", "26", + "FCC", "5G", "20M", "HT", "4T", "120", "30", + "ETSI", "5G", "20M", "HT", "4T", "120", "26", + "MKK", "5G", "20M", "HT", "4T", "120", "26", + "FCC", "5G", "20M", "HT", "4T", "124", "30", + "ETSI", "5G", "20M", "HT", "4T", "124", "26", + "MKK", "5G", "20M", "HT", "4T", "124", "26", + "FCC", "5G", "20M", "HT", "4T", "128", "30", + "ETSI", "5G", "20M", "HT", "4T", "128", "26", + "MKK", "5G", "20M", "HT", "4T", "128", "26", + "FCC", "5G", "20M", "HT", "4T", "132", "30", + "ETSI", "5G", "20M", "HT", "4T", "132", "26", + "MKK", "5G", "20M", "HT", "4T", "132", "26", + "FCC", "5G", "20M", "HT", "4T", "136", "30", + "ETSI", "5G", "20M", "HT", "4T", "136", "26", + "MKK", "5G", "20M", "HT", "4T", "136", "26", + "FCC", "5G", "20M", "HT", "4T", "140", "28", + "ETSI", "5G", "20M", "HT", "4T", "140", "26", + "MKK", "5G", "20M", "HT", "4T", "140", "26", + "FCC", "5G", "20M", "HT", "4T", "149", "26", + "ETSI", "5G", "20M", "HT", "4T", "149", "26", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "32", + "ETSI", "5G", "20M", "HT", "4T", "153", "26", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "32", + "ETSI", "5G", "20M", "HT", "4T", "157", "26", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "32", + "ETSI", "5G", "20M", "HT", "4T", "161", "26", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "32", + "ETSI", "5G", "20M", "HT", "4T", "165", "26", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "32", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "30", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "38", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "38", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "38", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "38", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "32", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "30", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "28", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "36", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "28", + "ETSI", "5G", "40M", "HT", "3T", "38", "28", + "MKK", "5G", "40M", "HT", "3T", "38", "28", + "FCC", "5G", "40M", "HT", "3T", "46", "28", + "ETSI", "5G", "40M", "HT", "3T", "46", "28", + "MKK", "5G", "40M", "HT", "3T", "46", "28", + "FCC", "5G", "40M", "HT", "3T", "54", "28", + "ETSI", "5G", "40M", "HT", "3T", "54", "28", + "MKK", "5G", "40M", "HT", "3T", "54", "28", + "FCC", "5G", "40M", "HT", "3T", "62", "26", + "ETSI", "5G", "40M", "HT", "3T", "62", "28", + "MKK", "5G", "40M", "HT", "3T", "62", "28", + "FCC", "5G", "40M", "HT", "3T", "102", "26", + "ETSI", "5G", "40M", "HT", "3T", "102", "28", + "MKK", "5G", "40M", "HT", "3T", "102", "28", + "FCC", "5G", "40M", "HT", "3T", "110", "34", + "ETSI", "5G", "40M", "HT", "3T", "110", "28", + "MKK", "5G", "40M", "HT", "3T", "110", "28", + "FCC", "5G", "40M", "HT", "3T", "118", "34", + "ETSI", "5G", "40M", "HT", "3T", "118", "28", + "MKK", "5G", "40M", "HT", "3T", "118", "28", + "FCC", "5G", "40M", "HT", "3T", "126", "34", + "ETSI", "5G", "40M", "HT", "3T", "126", "28", + "MKK", "5G", "40M", "HT", "3T", "126", "28", + "FCC", "5G", "40M", "HT", "3T", "134", "34", + "ETSI", "5G", "40M", "HT", "3T", "134", "28", + "MKK", "5G", "40M", "HT", "3T", "134", "28", + "FCC", "5G", "40M", "HT", "3T", "151", "28", + "ETSI", "5G", "40M", "HT", "3T", "151", "28", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "28", + "ETSI", "5G", "40M", "HT", "3T", "159", "28", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "26", + "ETSI", "5G", "40M", "HT", "4T", "38", "26", + "MKK", "5G", "40M", "HT", "4T", "38", "26", + "FCC", "5G", "40M", "HT", "4T", "46", "26", + "ETSI", "5G", "40M", "HT", "4T", "46", "26", + "MKK", "5G", "40M", "HT", "4T", "46", "26", + "FCC", "5G", "40M", "HT", "4T", "54", "26", + "ETSI", "5G", "40M", "HT", "4T", "54", "26", + "MKK", "5G", "40M", "HT", "4T", "54", "26", + "FCC", "5G", "40M", "HT", "4T", "62", "24", + "ETSI", "5G", "40M", "HT", "4T", "62", "26", + "MKK", "5G", "40M", "HT", "4T", "62", "26", + "FCC", "5G", "40M", "HT", "4T", "102", "24", + "ETSI", "5G", "40M", "HT", "4T", "102", "26", + "MKK", "5G", "40M", "HT", "4T", "102", "26", + "FCC", "5G", "40M", "HT", "4T", "110", "32", + "ETSI", "5G", "40M", "HT", "4T", "110", "26", + "MKK", "5G", "40M", "HT", "4T", "110", "26", + "FCC", "5G", "40M", "HT", "4T", "118", "32", + "ETSI", "5G", "40M", "HT", "4T", "118", "26", + "MKK", "5G", "40M", "HT", "4T", "118", "26", + "FCC", "5G", "40M", "HT", "4T", "126", "32", + "ETSI", "5G", "40M", "HT", "4T", "126", "26", + "MKK", "5G", "40M", "HT", "4T", "126", "26", + "FCC", "5G", "40M", "HT", "4T", "134", "32", + "ETSI", "5G", "40M", "HT", "4T", "134", "26", + "MKK", "5G", "40M", "HT", "4T", "134", "26", + "FCC", "5G", "40M", "HT", "4T", "151", "26", + "ETSI", "5G", "40M", "HT", "4T", "151", "26", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "26", + "ETSI", "5G", "40M", "HT", "4T", "159", "26", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "26", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "28", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "28", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "28", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "24", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "26", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "26", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "22", + "ETSI", "5G", "80M", "VHT", "3T", "42", "28", + "MKK", "5G", "80M", "VHT", "3T", "42", "28", + "FCC", "5G", "80M", "VHT", "3T", "58", "22", + "ETSI", "5G", "80M", "VHT", "3T", "58", "28", + "MKK", "5G", "80M", "VHT", "3T", "58", "28", + "FCC", "5G", "80M", "VHT", "3T", "106", "24", + "ETSI", "5G", "80M", "VHT", "3T", "106", "28", + "MKK", "5G", "80M", "VHT", "3T", "106", "28", + "FCC", "5G", "80M", "VHT", "3T", "122", "24", + "ETSI", "5G", "80M", "VHT", "3T", "122", "28", + "MKK", "5G", "80M", "VHT", "3T", "122", "28", + "FCC", "5G", "80M", "VHT", "3T", "155", "24", + "ETSI", "5G", "80M", "VHT", "3T", "155", "28", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "20", + "ETSI", "5G", "80M", "VHT", "4T", "42", "26", + "MKK", "5G", "80M", "VHT", "4T", "42", "26", + "FCC", "5G", "80M", "VHT", "4T", "58", "20", + "ETSI", "5G", "80M", "VHT", "4T", "58", "26", + "MKK", "5G", "80M", "VHT", "4T", "58", "26", + "FCC", "5G", "80M", "VHT", "4T", "106", "22", + "ETSI", "5G", "80M", "VHT", "4T", "106", "26", + "MKK", "5G", "80M", "VHT", "4T", "106", "26", + "FCC", "5G", "80M", "VHT", "4T", "122", "22", + "ETSI", "5G", "80M", "VHT", "4T", "122", "26", + "MKK", "5G", "80M", "VHT", "4T", "122", "26", + "FCC", "5G", "80M", "VHT", "4T", "155", "22", + "ETSI", "5G", "80M", "VHT", "4T", "155", "26", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type7)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type7; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type7)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type7; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type8.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type8[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "46", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "46", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "46", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "46", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "46", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "46", + "FCC", "2.4G", "20M", "OFDM", "1T", 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"34", + "MKK", "2.4G", "40M", "HT", "2T", "06", "34", + "FCC", "2.4G", "40M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", + "MKK", "2.4G", "40M", "HT", "2T", "07", "34", + "FCC", "2.4G", "40M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", + "MKK", "2.4G", "40M", "HT", "2T", "08", "34", + "FCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", + "MKK", "2.4G", "40M", "HT", "2T", "09", "34", + "FCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", + "MKK", "2.4G", "40M", "HT", "2T", "10", "34", + "FCC", "2.4G", "40M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", + "MKK", "2.4G", "40M", "HT", "2T", "11", "34", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", + "MKK", "2.4G", "40M", "HT", "2T", "12", "34", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", + "MKK", "2.4G", "40M", "HT", "2T", "13", "34", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", + "MKK", "2.4G", "40M", "HT", "3T", "03", "34", + "FCC", "2.4G", "40M", "HT", "3T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", + "MKK", "2.4G", "40M", "HT", "3T", "04", "34", + "FCC", "2.4G", "40M", "HT", "3T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", + "MKK", "2.4G", "40M", "HT", "3T", "05", "34", + "FCC", "2.4G", "40M", "HT", "3T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", + "MKK", "2.4G", "40M", "HT", "3T", "06", "34", + "FCC", "2.4G", "40M", "HT", "3T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", + "MKK", "2.4G", "40M", "HT", "3T", "07", "34", + "FCC", "2.4G", "40M", "HT", "3T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", + "MKK", "2.4G", "40M", "HT", "3T", "08", "34", + "FCC", "2.4G", "40M", "HT", "3T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", + "MKK", "2.4G", "40M", "HT", "3T", "09", "34", + "FCC", "2.4G", "40M", "HT", "3T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", + "MKK", "2.4G", "40M", "HT", "3T", "10", "34", + "FCC", "2.4G", "40M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", + "MKK", "2.4G", "40M", "HT", "3T", "11", "34", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", + "MKK", "2.4G", "40M", "HT", "3T", "12", "34", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", + "MKK", "2.4G", "40M", "HT", "3T", "13", "34", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", + "MKK", "2.4G", "40M", "HT", "4T", "03", "34", + "FCC", "2.4G", "40M", "HT", "4T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", + "MKK", "2.4G", "40M", "HT", "4T", "04", "34", + "FCC", "2.4G", "40M", "HT", "4T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", + "MKK", "2.4G", "40M", "HT", "4T", "05", "34", + "FCC", "2.4G", "40M", "HT", "4T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", + "MKK", "2.4G", "40M", "HT", "4T", "06", "34", + "FCC", "2.4G", "40M", "HT", "4T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", + "MKK", "2.4G", "40M", "HT", "4T", "07", "34", + "FCC", "2.4G", "40M", "HT", "4T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", + "MKK", "2.4G", "40M", "HT", "4T", "08", "34", + "FCC", "2.4G", "40M", "HT", "4T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", + "MKK", "2.4G", "40M", "HT", "4T", "09", "34", + "FCC", "2.4G", "40M", "HT", "4T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", + "MKK", "2.4G", "40M", "HT", "4T", "10", "34", + "FCC", "2.4G", "40M", "HT", "4T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", + "MKK", "2.4G", "40M", "HT", "4T", "11", "34", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", + "MKK", "2.4G", "40M", "HT", "4T", "12", "34", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", + "MKK", "2.4G", "40M", "HT", "4T", "13", "34", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "46", + "MKK", "5G", "20M", "OFDM", "1T", "36", "46", + "FCC", "5G", "20M", "OFDM", "1T", "40", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "46", + "MKK", "5G", "20M", "OFDM", "1T", "40", "46", + "FCC", "5G", "20M", "OFDM", "1T", "44", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "46", + "MKK", "5G", "20M", "OFDM", "1T", "44", "46", + "FCC", "5G", "20M", "OFDM", "1T", "48", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "46", + "MKK", "5G", "20M", "OFDM", "1T", "48", "46", + "FCC", "5G", "20M", "OFDM", "1T", "52", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "46", + "MKK", "5G", "20M", "OFDM", "1T", "52", "46", + "FCC", "5G", "20M", "OFDM", "1T", "56", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "46", + "MKK", "5G", "20M", "OFDM", "1T", "56", "46", + "FCC", "5G", "20M", "OFDM", "1T", "60", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "46", + "MKK", "5G", "20M", "OFDM", "1T", "60", "46", + "FCC", "5G", "20M", "OFDM", "1T", "64", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "46", + "MKK", "5G", "20M", "OFDM", "1T", "64", "46", + "FCC", "5G", "20M", "OFDM", "1T", "100", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "46", + "MKK", "5G", "20M", "OFDM", "1T", "100", "46", + "FCC", "5G", "20M", "OFDM", "1T", "104", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "46", + "MKK", "5G", "20M", "OFDM", "1T", "104", "46", + "FCC", "5G", "20M", "OFDM", "1T", "108", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "46", + "MKK", "5G", "20M", "OFDM", "1T", "108", "46", + "FCC", "5G", "20M", "OFDM", "1T", "112", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "46", + "MKK", "5G", "20M", "OFDM", "1T", "112", "46", + "FCC", "5G", "20M", "OFDM", "1T", "116", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "46", + "MKK", "5G", "20M", "OFDM", "1T", "116", "46", + "FCC", "5G", "20M", "OFDM", "1T", "120", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "46", + "MKK", "5G", "20M", "OFDM", "1T", "120", "46", + "FCC", "5G", "20M", "OFDM", "1T", "124", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "46", + "MKK", "5G", "20M", "OFDM", "1T", "124", "46", + "FCC", "5G", "20M", "OFDM", "1T", "128", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "46", + "MKK", "5G", "20M", "OFDM", "1T", "128", "46", + "FCC", "5G", "20M", "OFDM", "1T", "132", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "46", + "MKK", "5G", "20M", "OFDM", "1T", "132", "46", + "FCC", "5G", "20M", "OFDM", "1T", "136", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "46", + "MKK", "5G", "20M", "OFDM", "1T", "136", "46", + "FCC", "5G", "20M", "OFDM", "1T", "140", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "46", + "MKK", "5G", "20M", "OFDM", "1T", "140", "46", + "FCC", "5G", "20M", "OFDM", "1T", "149", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "46", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "46", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "46", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "46", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "46", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "46", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "46", + "ETSI", "5G", "20M", "HT", "1T", "36", "46", + "MKK", "5G", "20M", "HT", "1T", "36", "46", + "FCC", "5G", "20M", "HT", "1T", "40", "46", + "ETSI", "5G", "20M", "HT", "1T", "40", "46", + "MKK", "5G", "20M", "HT", "1T", "40", "46", + "FCC", "5G", "20M", "HT", "1T", "44", "46", + "ETSI", "5G", "20M", "HT", "1T", "44", "46", + "MKK", "5G", "20M", "HT", "1T", "44", "46", + "FCC", "5G", "20M", "HT", "1T", "48", "46", + "ETSI", "5G", "20M", "HT", "1T", "48", "46", + "MKK", "5G", "20M", "HT", "1T", "48", "46", + "FCC", "5G", "20M", "HT", "1T", "52", "46", + "ETSI", "5G", "20M", "HT", "1T", "52", "46", + "MKK", "5G", "20M", "HT", "1T", "52", "46", + "FCC", "5G", "20M", "HT", "1T", "56", "46", + "ETSI", "5G", "20M", "HT", "1T", "56", "46", + "MKK", "5G", "20M", "HT", "1T", "56", "46", + "FCC", "5G", "20M", "HT", "1T", "60", "46", + "ETSI", "5G", "20M", "HT", "1T", "60", "46", + "MKK", "5G", "20M", "HT", "1T", "60", "46", + "FCC", "5G", "20M", "HT", "1T", "64", "46", + "ETSI", "5G", "20M", "HT", "1T", "64", "46", + "MKK", "5G", "20M", "HT", "1T", "64", "46", + "FCC", "5G", "20M", "HT", "1T", "100", "46", + "ETSI", "5G", "20M", "HT", "1T", "100", "46", + "MKK", "5G", "20M", "HT", "1T", "100", "46", + "FCC", "5G", "20M", "HT", "1T", "104", "46", + "ETSI", "5G", "20M", "HT", "1T", "104", "46", + "MKK", "5G", "20M", "HT", "1T", "104", "46", + "FCC", "5G", "20M", "HT", "1T", "108", "46", + "ETSI", "5G", "20M", "HT", "1T", "108", "46", + "MKK", "5G", "20M", "HT", "1T", "108", "46", + "FCC", "5G", "20M", "HT", "1T", "112", "46", + "ETSI", "5G", "20M", "HT", "1T", "112", "46", + "MKK", "5G", "20M", "HT", "1T", "112", "46", + "FCC", "5G", "20M", "HT", "1T", "116", "46", + "ETSI", "5G", "20M", "HT", "1T", "116", "46", + "MKK", "5G", "20M", "HT", "1T", "116", "46", + "FCC", "5G", "20M", "HT", "1T", "120", "46", + "ETSI", "5G", "20M", "HT", "1T", "120", "46", + "MKK", "5G", "20M", "HT", "1T", "120", "46", + "FCC", "5G", "20M", "HT", "1T", "124", "46", + "ETSI", "5G", "20M", "HT", "1T", "124", "46", + "MKK", "5G", "20M", "HT", "1T", "124", "46", + "FCC", "5G", "20M", "HT", "1T", "128", "46", + "ETSI", "5G", "20M", "HT", "1T", "128", "46", + "MKK", "5G", "20M", "HT", "1T", "128", "46", + "FCC", "5G", "20M", "HT", "1T", "132", "46", + "ETSI", "5G", "20M", "HT", "1T", "132", "46", + "MKK", "5G", "20M", "HT", "1T", "132", "46", + "FCC", "5G", "20M", "HT", "1T", "136", "46", + "ETSI", "5G", "20M", "HT", "1T", "136", "46", + "MKK", "5G", "20M", "HT", "1T", "136", "46", + "FCC", "5G", "20M", "HT", "1T", "140", "46", + "ETSI", "5G", "20M", "HT", "1T", "140", "46", + "MKK", "5G", "20M", "HT", "1T", "140", "46", + "FCC", "5G", "20M", "HT", "1T", "149", "46", + "ETSI", "5G", "20M", "HT", "1T", "149", "46", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "46", + "ETSI", "5G", "20M", "HT", "1T", "153", "46", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "46", + "ETSI", "5G", "20M", "HT", "1T", "157", "46", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "46", + "ETSI", "5G", "20M", "HT", "1T", "161", "46", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "46", + "ETSI", "5G", "20M", "HT", "1T", "165", "46", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "46", + "ETSI", "5G", "20M", "HT", "2T", "36", "46", + "MKK", "5G", "20M", "HT", "2T", "36", "46", + "FCC", "5G", "20M", "HT", "2T", "40", "46", + "ETSI", "5G", "20M", "HT", "2T", "40", "46", + "MKK", "5G", "20M", "HT", "2T", "40", "46", + "FCC", "5G", "20M", "HT", "2T", "44", "46", + "ETSI", "5G", "20M", "HT", "2T", "44", "46", + "MKK", "5G", "20M", "HT", "2T", "44", "46", + "FCC", "5G", "20M", "HT", "2T", "48", "46", + "ETSI", "5G", "20M", "HT", "2T", "48", "46", + "MKK", "5G", "20M", "HT", "2T", "48", "46", + "FCC", "5G", "20M", "HT", "2T", "52", "46", + "ETSI", "5G", "20M", "HT", "2T", "52", "46", + "MKK", "5G", "20M", "HT", "2T", "52", "46", + "FCC", "5G", "20M", "HT", "2T", "56", "46", + "ETSI", "5G", "20M", "HT", "2T", "56", "46", + "MKK", "5G", "20M", "HT", "2T", "56", "46", + "FCC", "5G", "20M", "HT", "2T", "60", "46", + "ETSI", "5G", "20M", "HT", "2T", "60", "46", + "MKK", "5G", "20M", "HT", "2T", "60", "46", + "FCC", "5G", "20M", "HT", "2T", "64", "46", + "ETSI", "5G", "20M", "HT", "2T", "64", "46", + "MKK", "5G", "20M", "HT", "2T", "64", "46", + "FCC", "5G", "20M", "HT", "2T", "100", "46", + "ETSI", "5G", "20M", "HT", "2T", "100", "46", + "MKK", "5G", "20M", "HT", "2T", "100", "46", + "FCC", "5G", "20M", "HT", "2T", "104", "46", + "ETSI", "5G", "20M", "HT", "2T", "104", "46", + "MKK", "5G", "20M", "HT", "2T", "104", "46", + "FCC", "5G", "20M", "HT", "2T", "108", "46", + "ETSI", "5G", "20M", "HT", "2T", "108", "46", + "MKK", "5G", "20M", "HT", "2T", "108", "46", + "FCC", "5G", "20M", "HT", "2T", "112", "46", + "ETSI", "5G", "20M", "HT", "2T", "112", "46", + "MKK", "5G", "20M", "HT", "2T", "112", "46", + "FCC", "5G", "20M", "HT", "2T", "116", "46", + "ETSI", "5G", "20M", "HT", "2T", "116", "46", + "MKK", "5G", "20M", "HT", "2T", "116", "46", + "FCC", "5G", "20M", "HT", "2T", "120", "46", + "ETSI", "5G", "20M", "HT", "2T", "120", "46", + "MKK", "5G", "20M", "HT", "2T", "120", "46", + "FCC", "5G", "20M", "HT", "2T", "124", "46", + "ETSI", "5G", "20M", "HT", "2T", "124", "46", + "MKK", "5G", "20M", "HT", "2T", "124", "46", + "FCC", "5G", "20M", "HT", "2T", "128", "46", + "ETSI", "5G", "20M", "HT", "2T", "128", "46", + "MKK", "5G", "20M", "HT", "2T", "128", "46", + "FCC", "5G", "20M", "HT", "2T", "132", "46", + "ETSI", "5G", "20M", "HT", "2T", "132", "46", + "MKK", "5G", "20M", "HT", "2T", "132", "46", + "FCC", "5G", "20M", "HT", "2T", "136", "46", + "ETSI", "5G", "20M", "HT", "2T", "136", "46", + "MKK", "5G", "20M", "HT", "2T", "136", "46", + "FCC", "5G", "20M", "HT", "2T", "140", "46", + "ETSI", "5G", "20M", "HT", "2T", "140", "46", + "MKK", "5G", "20M", "HT", "2T", "140", "46", + "FCC", "5G", "20M", "HT", "2T", "149", "46", + "ETSI", "5G", "20M", "HT", "2T", "149", "46", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "46", + "ETSI", "5G", "20M", "HT", "2T", "153", "46", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "46", + "ETSI", "5G", "20M", "HT", "2T", "157", "46", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "46", + "ETSI", "5G", "20M", "HT", "2T", "161", "46", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "46", + "ETSI", "5G", "20M", "HT", "2T", "165", "46", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "46", + "ETSI", "5G", "20M", "HT", "3T", "36", "46", + "MKK", "5G", "20M", "HT", "3T", "36", "46", + "FCC", "5G", "20M", "HT", "3T", "40", "46", + "ETSI", "5G", "20M", "HT", "3T", "40", "46", + "MKK", "5G", "20M", "HT", "3T", "40", "46", + "FCC", "5G", "20M", "HT", "3T", "44", "46", + "ETSI", "5G", "20M", "HT", "3T", "44", "46", + "MKK", "5G", "20M", "HT", "3T", "44", "46", + "FCC", "5G", "20M", "HT", "3T", "48", "46", + "ETSI", "5G", "20M", "HT", "3T", "48", "46", + "MKK", "5G", "20M", "HT", "3T", "48", "46", + "FCC", "5G", "20M", "HT", "3T", "52", "46", + "ETSI", "5G", "20M", "HT", "3T", "52", "46", + "MKK", "5G", "20M", "HT", "3T", "52", "46", + "FCC", "5G", "20M", "HT", "3T", "56", "46", + "ETSI", "5G", "20M", "HT", "3T", "56", "46", + "MKK", "5G", "20M", "HT", "3T", "56", "46", + "FCC", "5G", "20M", "HT", "3T", "60", "46", + "ETSI", "5G", "20M", "HT", "3T", "60", "46", + "MKK", "5G", "20M", "HT", "3T", "60", "46", + "FCC", "5G", "20M", "HT", "3T", "64", "46", + "ETSI", "5G", "20M", "HT", "3T", "64", "46", + "MKK", "5G", "20M", "HT", "3T", "64", "46", + "FCC", "5G", "20M", "HT", "3T", "100", "46", + "ETSI", "5G", "20M", "HT", "3T", "100", "46", + "MKK", "5G", "20M", "HT", "3T", "100", "46", + "FCC", "5G", "20M", "HT", "3T", "104", "46", + "ETSI", "5G", "20M", "HT", "3T", "104", "46", + "MKK", "5G", "20M", "HT", "3T", "104", "46", + "FCC", "5G", "20M", "HT", "3T", "108", "46", + "ETSI", "5G", "20M", "HT", "3T", "108", "46", + "MKK", "5G", "20M", "HT", "3T", "108", "46", + "FCC", "5G", "20M", "HT", "3T", "112", "46", + "ETSI", "5G", "20M", "HT", "3T", "112", "46", + "MKK", "5G", "20M", "HT", "3T", "112", "46", + "FCC", "5G", "20M", "HT", "3T", "116", "46", + "ETSI", "5G", "20M", "HT", "3T", "116", "46", + "MKK", "5G", "20M", "HT", "3T", "116", "46", + "FCC", "5G", "20M", "HT", "3T", "120", "46", + "ETSI", "5G", "20M", "HT", "3T", "120", "46", + "MKK", "5G", "20M", "HT", "3T", "120", "46", + "FCC", "5G", "20M", "HT", "3T", "124", "46", + "ETSI", "5G", "20M", "HT", "3T", "124", "46", + "MKK", "5G", "20M", "HT", "3T", "124", "46", + "FCC", "5G", "20M", "HT", "3T", "128", "46", + "ETSI", "5G", "20M", "HT", "3T", "128", "46", + "MKK", "5G", "20M", "HT", "3T", "128", "46", + "FCC", "5G", "20M", "HT", "3T", "132", "46", + "ETSI", "5G", "20M", "HT", "3T", "132", "46", + "MKK", "5G", "20M", "HT", "3T", "132", "46", + "FCC", "5G", "20M", "HT", "3T", "136", "46", + "ETSI", "5G", "20M", "HT", "3T", "136", "46", + "MKK", "5G", "20M", "HT", "3T", "136", "46", + "FCC", "5G", "20M", "HT", "3T", "140", "46", + "ETSI", "5G", "20M", "HT", "3T", "140", "46", + "MKK", "5G", "20M", "HT", "3T", "140", "46", + "FCC", "5G", "20M", "HT", "3T", "149", "46", + "ETSI", "5G", "20M", "HT", "3T", "149", "46", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "46", + "ETSI", "5G", "20M", "HT", "3T", "153", "46", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "46", + "ETSI", "5G", "20M", "HT", "3T", "157", "46", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "46", + "ETSI", "5G", "20M", "HT", "3T", "161", "46", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "46", + "ETSI", "5G", "20M", "HT", "3T", "165", "46", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "46", + "ETSI", "5G", "20M", "HT", "4T", "36", "46", + "MKK", "5G", "20M", "HT", "4T", "36", "46", + "FCC", "5G", "20M", "HT", "4T", "40", "46", + "ETSI", "5G", "20M", "HT", "4T", "40", "46", + "MKK", "5G", "20M", "HT", "4T", "40", "46", + "FCC", "5G", "20M", "HT", "4T", "44", "46", + "ETSI", "5G", "20M", "HT", "4T", "44", "46", + "MKK", "5G", "20M", "HT", "4T", "44", "46", + "FCC", "5G", "20M", "HT", "4T", "48", "46", + "ETSI", "5G", "20M", "HT", "4T", "48", "46", + "MKK", "5G", "20M", "HT", "4T", "48", "46", + "FCC", "5G", "20M", "HT", "4T", "52", "46", + "ETSI", "5G", "20M", "HT", "4T", "52", "46", + "MKK", "5G", "20M", "HT", "4T", "52", "46", + "FCC", "5G", "20M", "HT", "4T", "56", "46", + "ETSI", "5G", "20M", "HT", "4T", "56", "46", + "MKK", "5G", "20M", "HT", "4T", "56", "46", + "FCC", "5G", "20M", "HT", "4T", "60", "46", + "ETSI", "5G", "20M", "HT", "4T", "60", "46", + "MKK", "5G", "20M", "HT", "4T", "60", "46", + "FCC", "5G", "20M", "HT", "4T", "64", "46", + "ETSI", "5G", "20M", "HT", "4T", "64", "46", + "MKK", "5G", "20M", "HT", "4T", "64", "46", + "FCC", "5G", "20M", "HT", "4T", "100", "46", + "ETSI", "5G", "20M", "HT", "4T", "100", "46", + "MKK", "5G", "20M", "HT", "4T", "100", "46", + "FCC", "5G", "20M", "HT", "4T", "104", "46", + "ETSI", "5G", "20M", "HT", "4T", "104", "46", + "MKK", "5G", "20M", "HT", "4T", "104", "46", + "FCC", "5G", "20M", "HT", "4T", "108", "46", + "ETSI", "5G", "20M", "HT", "4T", "108", "46", + "MKK", "5G", "20M", "HT", "4T", "108", "46", + "FCC", "5G", "20M", "HT", "4T", "112", "46", + "ETSI", "5G", "20M", "HT", "4T", "112", "46", + "MKK", "5G", "20M", "HT", "4T", "112", "46", + "FCC", "5G", "20M", "HT", "4T", "116", "46", + "ETSI", "5G", "20M", "HT", "4T", "116", "46", + "MKK", "5G", "20M", "HT", "4T", "116", "46", + "FCC", "5G", "20M", "HT", "4T", "120", "46", + "ETSI", "5G", "20M", "HT", "4T", "120", "46", + "MKK", "5G", "20M", "HT", "4T", "120", "46", + "FCC", "5G", "20M", "HT", "4T", "124", "46", + "ETSI", "5G", "20M", "HT", "4T", "124", "46", + "MKK", "5G", "20M", "HT", "4T", "124", "46", + "FCC", "5G", "20M", "HT", "4T", "128", "46", + "ETSI", "5G", "20M", "HT", "4T", "128", "46", + "MKK", "5G", "20M", "HT", "4T", "128", "46", + "FCC", "5G", "20M", "HT", "4T", "132", "46", + "ETSI", "5G", "20M", "HT", "4T", "132", "46", + "MKK", "5G", "20M", "HT", "4T", "132", "46", + "FCC", "5G", "20M", "HT", "4T", "136", "46", + "ETSI", "5G", "20M", "HT", "4T", "136", "46", + "MKK", "5G", "20M", "HT", "4T", "136", "46", + "FCC", "5G", "20M", "HT", "4T", "140", "46", + "ETSI", "5G", "20M", "HT", "4T", "140", "46", + "MKK", "5G", "20M", "HT", "4T", "140", "46", + "FCC", "5G", "20M", "HT", "4T", "149", "46", + "ETSI", "5G", "20M", "HT", "4T", "149", "46", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "46", + "ETSI", "5G", "20M", "HT", "4T", "153", "46", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "46", + "ETSI", "5G", "20M", "HT", "4T", "157", "46", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "46", + "ETSI", "5G", "20M", "HT", "4T", "161", "46", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "46", + "ETSI", "5G", "20M", "HT", "4T", "165", "46", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "46", + "ETSI", "5G", "40M", "HT", "1T", "38", "46", + "MKK", "5G", "40M", "HT", "1T", "38", "46", + "FCC", "5G", "40M", "HT", "1T", "46", "46", + "ETSI", "5G", "40M", "HT", "1T", "46", "46", + "MKK", "5G", "40M", "HT", "1T", "46", "46", + "FCC", "5G", "40M", "HT", "1T", "54", "46", + "ETSI", "5G", "40M", "HT", "1T", "54", "46", + "MKK", "5G", "40M", "HT", "1T", "54", "46", + "FCC", "5G", "40M", "HT", "1T", "62", "46", + "ETSI", "5G", "40M", "HT", "1T", "62", "46", + "MKK", "5G", "40M", "HT", "1T", "62", "46", + "FCC", "5G", "40M", "HT", "1T", "102", "46", + "ETSI", "5G", "40M", "HT", "1T", "102", "46", + "MKK", "5G", "40M", "HT", "1T", "102", "46", + "FCC", "5G", "40M", "HT", "1T", "110", "46", + "ETSI", "5G", "40M", "HT", "1T", "110", "46", + "MKK", "5G", "40M", "HT", "1T", "110", "46", + "FCC", "5G", "40M", "HT", "1T", "118", "46", + "ETSI", "5G", "40M", "HT", "1T", "118", "46", + "MKK", "5G", "40M", "HT", "1T", "118", "46", + "FCC", "5G", "40M", "HT", "1T", "126", "46", + "ETSI", "5G", "40M", "HT", "1T", "126", "46", + "MKK", "5G", "40M", "HT", "1T", "126", "46", + "FCC", "5G", "40M", "HT", "1T", "134", "46", + "ETSI", "5G", "40M", "HT", "1T", "134", "46", + "MKK", "5G", "40M", "HT", "1T", "134", "46", + "FCC", "5G", "40M", "HT", "1T", "151", "46", + "ETSI", "5G", "40M", "HT", "1T", "151", "46", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "46", + "ETSI", "5G", "40M", "HT", "1T", "159", "46", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "46", + "ETSI", "5G", "40M", "HT", "2T", "38", "46", + "MKK", "5G", "40M", "HT", "2T", "38", "46", + "FCC", "5G", "40M", "HT", "2T", "46", "46", + "ETSI", "5G", "40M", "HT", "2T", "46", "46", + "MKK", "5G", "40M", "HT", "2T", "46", "46", + "FCC", "5G", "40M", "HT", "2T", "54", "46", + "ETSI", "5G", "40M", "HT", "2T", "54", "46", + "MKK", "5G", "40M", "HT", "2T", "54", "46", + "FCC", "5G", "40M", "HT", "2T", "62", "46", + "ETSI", "5G", "40M", "HT", "2T", "62", "46", + "MKK", "5G", "40M", "HT", "2T", "62", "46", + "FCC", "5G", "40M", "HT", "2T", "102", "46", + "ETSI", "5G", "40M", "HT", "2T", "102", "46", + "MKK", "5G", "40M", "HT", "2T", "102", "46", + "FCC", "5G", "40M", "HT", "2T", "110", "46", + "ETSI", "5G", "40M", "HT", "2T", "110", "46", + "MKK", "5G", "40M", "HT", "2T", "110", "46", + "FCC", "5G", "40M", "HT", "2T", "118", "46", + "ETSI", "5G", "40M", "HT", "2T", "118", "46", + "MKK", "5G", "40M", "HT", "2T", "118", "46", + "FCC", "5G", "40M", "HT", "2T", "126", "46", + "ETSI", "5G", "40M", "HT", "2T", "126", "46", + "MKK", "5G", "40M", "HT", "2T", "126", "46", + "FCC", "5G", "40M", "HT", "2T", "134", "46", + "ETSI", "5G", "40M", "HT", "2T", "134", "46", + "MKK", "5G", "40M", "HT", "2T", "134", "46", + "FCC", "5G", "40M", "HT", "2T", "151", "46", + "ETSI", "5G", "40M", "HT", "2T", "151", "46", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "46", + "ETSI", "5G", "40M", "HT", "2T", "159", "46", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "46", + "ETSI", "5G", "40M", "HT", "3T", "38", "46", + "MKK", "5G", "40M", "HT", "3T", "38", "46", + "FCC", "5G", "40M", "HT", "3T", "46", "46", + "ETSI", "5G", "40M", "HT", "3T", "46", "46", + "MKK", "5G", "40M", "HT", "3T", "46", "46", + "FCC", "5G", "40M", "HT", "3T", "54", "46", + "ETSI", "5G", "40M", "HT", "3T", "54", "46", + "MKK", "5G", "40M", "HT", "3T", "54", "46", + "FCC", "5G", "40M", "HT", "3T", "62", "46", + "ETSI", "5G", "40M", "HT", "3T", "62", "46", + "MKK", "5G", "40M", "HT", "3T", "62", "46", + "FCC", "5G", "40M", "HT", "3T", "102", "46", + "ETSI", "5G", "40M", "HT", "3T", "102", "46", + "MKK", "5G", "40M", "HT", "3T", "102", "46", + "FCC", "5G", "40M", "HT", "3T", "110", "46", + "ETSI", "5G", "40M", "HT", "3T", "110", "46", + "MKK", "5G", "40M", "HT", "3T", "110", "46", + "FCC", "5G", "40M", "HT", "3T", "118", "46", + "ETSI", "5G", "40M", "HT", "3T", "118", "46", + "MKK", "5G", "40M", "HT", "3T", "118", "46", + "FCC", "5G", "40M", "HT", "3T", "126", "46", + "ETSI", "5G", "40M", "HT", "3T", "126", "46", + "MKK", "5G", "40M", "HT", "3T", "126", "46", + "FCC", "5G", "40M", "HT", "3T", "134", "46", + "ETSI", "5G", "40M", "HT", "3T", "134", "46", + "MKK", "5G", "40M", "HT", "3T", "134", "46", + "FCC", "5G", "40M", "HT", "3T", "151", "46", + "ETSI", "5G", "40M", "HT", "3T", "151", "46", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "46", + "ETSI", "5G", "40M", "HT", "3T", "159", "46", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "46", + "ETSI", "5G", "40M", "HT", "4T", "38", "46", + "MKK", "5G", "40M", "HT", "4T", "38", "46", + "FCC", "5G", "40M", "HT", "4T", "46", "46", + "ETSI", "5G", "40M", "HT", "4T", "46", "46", + "MKK", "5G", "40M", "HT", "4T", "46", "46", + "FCC", "5G", "40M", "HT", "4T", "54", "46", + "ETSI", "5G", "40M", "HT", "4T", "54", "46", + "MKK", "5G", "40M", "HT", "4T", "54", "46", + "FCC", "5G", "40M", "HT", "4T", "62", "46", + "ETSI", "5G", "40M", "HT", "4T", "62", "46", + "MKK", "5G", "40M", "HT", "4T", "62", "46", + "FCC", "5G", "40M", "HT", "4T", "102", "46", + "ETSI", "5G", "40M", "HT", "4T", "102", "46", + "MKK", "5G", "40M", "HT", "4T", "102", "46", + "FCC", "5G", "40M", "HT", "4T", "110", "46", + "ETSI", "5G", "40M", "HT", "4T", "110", "46", + "MKK", "5G", "40M", "HT", "4T", "110", "46", + "FCC", "5G", "40M", "HT", "4T", "118", "46", + "ETSI", "5G", "40M", "HT", "4T", "118", "46", + "MKK", "5G", "40M", "HT", "4T", "118", "46", + "FCC", "5G", "40M", "HT", "4T", "126", "46", + "ETSI", "5G", "40M", "HT", "4T", "126", "46", + "MKK", "5G", "40M", "HT", "4T", "126", "46", + "FCC", "5G", "40M", "HT", "4T", "134", "46", + "ETSI", "5G", "40M", "HT", "4T", "134", "46", + "MKK", "5G", "40M", "HT", "4T", "134", "46", + "FCC", "5G", "40M", "HT", "4T", "151", "46", + "ETSI", "5G", "40M", "HT", "4T", "151", "46", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "46", + "ETSI", "5G", "40M", "HT", "4T", "159", "46", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "46", + "ETSI", "5G", "80M", "VHT", "1T", "42", "46", + "MKK", "5G", "80M", "VHT", "1T", "42", "46", + "FCC", "5G", "80M", "VHT", "1T", "58", "46", + "ETSI", "5G", "80M", "VHT", "1T", "58", "46", + "MKK", "5G", "80M", "VHT", "1T", "58", "46", + "FCC", "5G", "80M", "VHT", "1T", "106", "46", + "ETSI", "5G", "80M", "VHT", "1T", "106", "46", + "MKK", "5G", "80M", "VHT", "1T", "106", "46", + "FCC", "5G", "80M", "VHT", "1T", "122", "46", + "ETSI", "5G", "80M", "VHT", "1T", "122", "46", + "MKK", "5G", "80M", "VHT", "1T", "122", "46", + "FCC", "5G", "80M", "VHT", "1T", "155", "46", + "ETSI", "5G", "80M", "VHT", "1T", "155", "46", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "46", + "ETSI", "5G", "80M", "VHT", "2T", "42", "46", + "MKK", "5G", "80M", "VHT", "2T", "42", "46", + "FCC", "5G", "80M", "VHT", "2T", "58", "46", + "ETSI", "5G", "80M", "VHT", "2T", "58", "46", + "MKK", "5G", "80M", "VHT", "2T", "58", "46", + "FCC", "5G", "80M", "VHT", "2T", "106", "46", + "ETSI", "5G", "80M", "VHT", "2T", "106", "46", + "MKK", "5G", "80M", "VHT", "2T", "106", "46", + "FCC", "5G", "80M", "VHT", "2T", "122", "46", + "ETSI", "5G", "80M", "VHT", "2T", "122", "46", + "MKK", "5G", "80M", "VHT", "2T", "122", "46", + "FCC", "5G", "80M", "VHT", "2T", "155", "46", + "ETSI", "5G", "80M", "VHT", "2T", "155", "46", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "46", + "ETSI", "5G", "80M", "VHT", "3T", "42", "46", + "MKK", "5G", "80M", "VHT", "3T", "42", "46", + "FCC", "5G", "80M", "VHT", "3T", "58", "46", + "ETSI", "5G", "80M", "VHT", "3T", "58", "46", + "MKK", "5G", "80M", "VHT", "3T", "58", "46", + "FCC", "5G", "80M", "VHT", "3T", "106", "46", + "ETSI", "5G", "80M", "VHT", "3T", "106", "46", + "MKK", "5G", "80M", "VHT", "3T", "106", "46", + "FCC", "5G", "80M", "VHT", "3T", "122", "46", + "ETSI", "5G", "80M", "VHT", "3T", "122", "46", + "MKK", "5G", "80M", "VHT", "3T", "122", "46", + "FCC", "5G", "80M", "VHT", "3T", "155", "46", + "ETSI", "5G", "80M", "VHT", "3T", "155", "46", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "46", + "ETSI", "5G", "80M", "VHT", "4T", "42", "46", + "MKK", "5G", "80M", "VHT", "4T", "42", "46", + "FCC", "5G", "80M", "VHT", "4T", "58", "46", + "ETSI", "5G", "80M", "VHT", "4T", "58", "46", + "MKK", "5G", "80M", "VHT", "4T", "58", "46", + "FCC", "5G", "80M", "VHT", "4T", "106", "46", + "ETSI", "5G", "80M", "VHT", "4T", "106", "46", + "MKK", "5G", "80M", "VHT", "4T", "106", "46", + "FCC", "5G", "80M", "VHT", "4T", "122", "46", + "ETSI", "5G", "80M", "VHT", "4T", "122", "46", + "MKK", "5G", "80M", "VHT", "4T", "122", "46", + "FCC", "5G", "80M", "VHT", "4T", "155", "46", + "ETSI", "5G", "80M", "VHT", "4T", "155", "46", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type8)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type8; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type8)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type8; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_Type9.TXT +******************************************************************************/ + +const char *Array_MP_8814A_TXPWR_LMT_Type9[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "40", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "40", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "40", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "40", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "40", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "40", + "FCC", "2.4G", "20M", "HT", "1T", "01", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "40", + "MKK", "2.4G", "20M", "HT", "1T", "01", "40", + "FCC", "2.4G", "20M", "HT", "1T", "02", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "40", + "MKK", "2.4G", "20M", "HT", "1T", "02", "40", + "FCC", "2.4G", "20M", "HT", "1T", "03", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "40", + "MKK", "2.4G", "20M", "HT", "1T", "03", "40", + "FCC", "2.4G", "20M", "HT", "1T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "40", + "MKK", "2.4G", "20M", "HT", "1T", "04", "40", + "FCC", "2.4G", "20M", "HT", "1T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "40", + "MKK", "2.4G", "20M", "HT", "1T", "05", "40", + "FCC", "2.4G", "20M", "HT", "1T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "40", + "MKK", "2.4G", "20M", "HT", "1T", "06", "40", + "FCC", "2.4G", "20M", "HT", "1T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "40", + "MKK", "2.4G", "20M", "HT", "1T", "07", "40", + "FCC", "2.4G", "20M", "HT", "1T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "40", + "MKK", "2.4G", "20M", "HT", "1T", "08", "40", + "FCC", "2.4G", "20M", "HT", "1T", "09", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "40", + "MKK", "2.4G", "20M", "HT", "1T", "09", "40", + "FCC", "2.4G", "20M", "HT", "1T", "10", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "40", + "MKK", "2.4G", "20M", "HT", "1T", "10", "40", + "FCC", "2.4G", "20M", "HT", "1T", "11", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "40", + "MKK", "2.4G", "20M", "HT", "1T", "11", "40", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "40", + "MKK", "2.4G", "20M", "HT", "1T", "12", "40", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "40", + "MKK", "2.4G", "20M", "HT", "1T", "13", "40", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "40", + "FCC", "2.4G", "20M", "HT", "2T", "01", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "40", + "MKK", "2.4G", "20M", "HT", "2T", "01", "40", + "FCC", "2.4G", "20M", "HT", "2T", "02", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "40", + "MKK", "2.4G", "20M", "HT", "2T", "02", "40", + "FCC", "2.4G", "20M", "HT", "2T", "03", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "40", + "MKK", "2.4G", "20M", "HT", "2T", "03", "40", + "FCC", "2.4G", "20M", "HT", "2T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "40", + "MKK", "2.4G", "20M", "HT", "2T", "04", "40", + "FCC", "2.4G", "20M", "HT", "2T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "40", + "MKK", "2.4G", "20M", "HT", "2T", "05", "40", + "FCC", "2.4G", "20M", "HT", "2T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "40", + "MKK", "2.4G", "20M", "HT", "2T", "06", "40", + "FCC", "2.4G", "20M", "HT", "2T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "40", + "MKK", "2.4G", "20M", "HT", "2T", "07", "40", + "FCC", "2.4G", "20M", "HT", "2T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "40", + "MKK", "2.4G", "20M", "HT", "2T", "08", "40", + "FCC", "2.4G", "20M", "HT", "2T", "09", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "40", + "MKK", "2.4G", "20M", "HT", "2T", "09", "40", + "FCC", "2.4G", "20M", "HT", "2T", "10", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "40", + "MKK", "2.4G", "20M", "HT", "2T", "10", "40", + "FCC", "2.4G", "20M", "HT", "2T", "11", "40", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "40", + "MKK", "2.4G", "20M", "HT", "2T", "11", "40", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "40", + "MKK", "2.4G", "20M", "HT", "2T", "12", "40", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "40", + "MKK", "2.4G", "20M", "HT", "2T", "13", "40", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "40", + "FCC", "2.4G", "20M", "HT", "3T", "01", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "01", "40", + "MKK", "2.4G", "20M", "HT", "3T", "01", "40", + "FCC", "2.4G", "20M", "HT", "3T", "02", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "02", "40", + "MKK", "2.4G", "20M", "HT", "3T", "02", "40", + "FCC", "2.4G", "20M", "HT", "3T", "03", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "03", "40", + "MKK", "2.4G", "20M", "HT", "3T", "03", "40", + "FCC", "2.4G", "20M", "HT", "3T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "04", "40", + "MKK", "2.4G", "20M", "HT", "3T", "04", "40", + "FCC", "2.4G", "20M", "HT", "3T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "05", "40", + "MKK", "2.4G", "20M", "HT", "3T", "05", "40", + "FCC", "2.4G", "20M", "HT", "3T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "06", "40", + "MKK", "2.4G", "20M", "HT", "3T", "06", "40", + "FCC", "2.4G", "20M", "HT", "3T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "07", "40", + "MKK", "2.4G", "20M", "HT", "3T", "07", "40", + "FCC", "2.4G", "20M", "HT", "3T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "08", "40", + "MKK", "2.4G", "20M", "HT", "3T", "08", "40", + "FCC", "2.4G", "20M", "HT", "3T", "09", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "09", "40", + "MKK", "2.4G", "20M", "HT", "3T", "09", "40", + "FCC", "2.4G", "20M", "HT", "3T", "10", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "10", "40", + "MKK", "2.4G", "20M", "HT", "3T", "10", "40", + "FCC", "2.4G", "20M", "HT", "3T", "11", "40", + "ETSI", "2.4G", "20M", "HT", "3T", "11", "40", + "MKK", "2.4G", "20M", "HT", "3T", "11", "40", + "FCC", "2.4G", "20M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "12", "40", + "MKK", "2.4G", "20M", "HT", "3T", "12", "40", + "FCC", "2.4G", "20M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "13", "40", + "MKK", "2.4G", "20M", "HT", "3T", "13", "40", + "FCC", "2.4G", "20M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", + "MKK", "2.4G", "20M", "HT", "3T", "14", "40", + "FCC", "2.4G", "20M", "HT", "4T", "01", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "01", "40", + "MKK", "2.4G", "20M", "HT", "4T", "01", "40", + "FCC", "2.4G", "20M", "HT", "4T", "02", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "02", "40", + "MKK", "2.4G", "20M", "HT", "4T", "02", "40", + "FCC", "2.4G", "20M", "HT", "4T", "03", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "03", "40", + "MKK", "2.4G", "20M", "HT", "4T", "03", "40", + "FCC", "2.4G", "20M", "HT", "4T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "04", "40", + "MKK", "2.4G", "20M", "HT", "4T", "04", "40", + "FCC", "2.4G", "20M", "HT", "4T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "05", "40", + "MKK", "2.4G", "20M", "HT", "4T", "05", "40", + "FCC", "2.4G", "20M", "HT", "4T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "06", "40", + "MKK", "2.4G", "20M", "HT", "4T", "06", "40", + "FCC", "2.4G", "20M", "HT", "4T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "07", "40", + "MKK", "2.4G", "20M", "HT", "4T", "07", "40", + "FCC", "2.4G", "20M", "HT", "4T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "08", "40", + "MKK", "2.4G", "20M", "HT", "4T", "08", "40", + "FCC", "2.4G", "20M", "HT", "4T", "09", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "09", "40", + "MKK", "2.4G", "20M", "HT", "4T", "09", "40", + "FCC", "2.4G", "20M", "HT", "4T", "10", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "10", "40", + "MKK", "2.4G", "20M", "HT", "4T", "10", "40", + "FCC", "2.4G", "20M", "HT", "4T", "11", "40", + "ETSI", "2.4G", "20M", "HT", "4T", "11", "40", + "MKK", "2.4G", "20M", "HT", "4T", "11", "40", + "FCC", "2.4G", "20M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "12", "40", + "MKK", "2.4G", "20M", "HT", "4T", "12", "40", + "FCC", "2.4G", "20M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "13", "40", + "MKK", "2.4G", "20M", "HT", "4T", "13", "40", + "FCC", "2.4G", "20M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", + "MKK", "2.4G", "20M", "HT", "4T", "14", "40", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "34", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "34", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "34", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "34", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "34", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "34", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "34", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "34", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "34", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "34", + "MKK", "2.4G", "40M", "HT", "1T", "12", "34", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "34", + "MKK", "2.4G", "40M", "HT", "1T", "13", "34", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "34", + "MKK", "2.4G", "40M", "HT", "2T", "03", "34", + "FCC", "2.4G", "40M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "34", + "MKK", "2.4G", "40M", "HT", "2T", "04", "34", + "FCC", "2.4G", "40M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "34", + "MKK", "2.4G", "40M", "HT", "2T", "05", "34", + "FCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "34", + "MKK", "2.4G", "40M", "HT", "2T", "06", "34", + "FCC", "2.4G", "40M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "34", + "MKK", "2.4G", "40M", "HT", "2T", "07", "34", + "FCC", "2.4G", "40M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "34", + "MKK", "2.4G", "40M", "HT", "2T", "08", "34", + "FCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "34", + "MKK", "2.4G", "40M", "HT", "2T", "09", "34", + "FCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "34", + "MKK", "2.4G", "40M", "HT", "2T", "10", "34", + "FCC", "2.4G", "40M", "HT", "2T", "11", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "34", + "MKK", "2.4G", "40M", "HT", "2T", "11", "34", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "34", + "MKK", "2.4G", "40M", "HT", "2T", "12", "34", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "34", + "MKK", "2.4G", "40M", "HT", "2T", "13", "34", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "34", + "MKK", "2.4G", "40M", "HT", "3T", "03", "34", + "FCC", "2.4G", "40M", "HT", "3T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "34", + "MKK", "2.4G", "40M", "HT", "3T", "04", "34", + "FCC", "2.4G", "40M", "HT", "3T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "34", + "MKK", "2.4G", "40M", "HT", "3T", "05", "34", + "FCC", "2.4G", "40M", "HT", "3T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "34", + "MKK", "2.4G", "40M", "HT", "3T", "06", "34", + "FCC", "2.4G", "40M", "HT", "3T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "34", + "MKK", "2.4G", "40M", "HT", "3T", "07", "34", + "FCC", "2.4G", "40M", "HT", "3T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "34", + "MKK", "2.4G", "40M", "HT", "3T", "08", "34", + "FCC", "2.4G", "40M", "HT", "3T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "34", + "MKK", "2.4G", "40M", "HT", "3T", "09", "34", + "FCC", "2.4G", "40M", "HT", "3T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "34", + "MKK", "2.4G", "40M", "HT", "3T", "10", "34", + "FCC", "2.4G", "40M", "HT", "3T", "11", "34", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "34", + "MKK", "2.4G", "40M", "HT", "3T", "11", "34", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "34", + "MKK", "2.4G", "40M", "HT", "3T", "12", "34", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "34", + "MKK", "2.4G", "40M", "HT", "3T", "13", "34", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "34", + "MKK", "2.4G", "40M", "HT", "4T", "03", "34", + "FCC", "2.4G", "40M", "HT", "4T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "34", + "MKK", "2.4G", "40M", "HT", "4T", "04", "34", + "FCC", "2.4G", "40M", "HT", "4T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "34", + "MKK", "2.4G", "40M", "HT", "4T", "05", "34", + "FCC", "2.4G", "40M", "HT", "4T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "34", + "MKK", "2.4G", "40M", "HT", "4T", "06", "34", + "FCC", "2.4G", "40M", "HT", "4T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "34", + "MKK", "2.4G", "40M", "HT", "4T", "07", "34", + "FCC", "2.4G", "40M", "HT", "4T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "34", + "MKK", "2.4G", "40M", "HT", "4T", "08", "34", + "FCC", "2.4G", "40M", "HT", "4T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "34", + "MKK", "2.4G", "40M", "HT", "4T", "09", "34", + "FCC", "2.4G", "40M", "HT", "4T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "34", + "MKK", "2.4G", "40M", "HT", "4T", "10", "34", + "FCC", "2.4G", "40M", "HT", "4T", "11", "34", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "34", + "MKK", "2.4G", "40M", "HT", "4T", "11", "34", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "34", + "MKK", "2.4G", "40M", "HT", "4T", "12", "34", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "34", + "MKK", "2.4G", "40M", "HT", "4T", "13", "34", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "44", + "MKK", "5G", "20M", "OFDM", "1T", "36", "44", + "FCC", "5G", "20M", "OFDM", "1T", "40", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "44", + "MKK", "5G", "20M", "OFDM", "1T", "40", "44", + "FCC", "5G", "20M", "OFDM", "1T", "44", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "44", + "MKK", "5G", "20M", "OFDM", "1T", "44", "44", + "FCC", "5G", "20M", "OFDM", "1T", "48", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "44", + "MKK", "5G", "20M", "OFDM", "1T", "48", "44", + "FCC", "5G", "20M", "OFDM", "1T", "52", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "44", + "MKK", "5G", "20M", "OFDM", "1T", "52", "44", + "FCC", "5G", "20M", "OFDM", "1T", "56", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "44", + "MKK", "5G", "20M", "OFDM", "1T", "56", "44", + "FCC", "5G", "20M", "OFDM", "1T", "60", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "44", + "MKK", "5G", "20M", "OFDM", "1T", "60", "44", + "FCC", "5G", "20M", "OFDM", "1T", "64", "40", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "40", + "MKK", "5G", "20M", "OFDM", "1T", "64", "40", + "FCC", "5G", "20M", "OFDM", "1T", "100", "40", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "40", + "MKK", "5G", "20M", "OFDM", "1T", "100", "40", + "FCC", "5G", "20M", "OFDM", "1T", "104", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "44", + "MKK", "5G", "20M", "OFDM", "1T", "104", "44", + "FCC", "5G", "20M", "OFDM", "1T", "108", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "44", + "MKK", "5G", "20M", "OFDM", "1T", "108", "44", + "FCC", "5G", "20M", "OFDM", "1T", "112", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "44", + "MKK", "5G", "20M", "OFDM", "1T", "112", "44", + "FCC", "5G", "20M", "OFDM", "1T", "116", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "44", + "MKK", "5G", "20M", "OFDM", "1T", "116", "44", + "FCC", "5G", "20M", "OFDM", "1T", "120", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "44", + "MKK", "5G", "20M", "OFDM", "1T", "120", "44", + "FCC", "5G", "20M", "OFDM", "1T", "124", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "44", + "MKK", "5G", "20M", "OFDM", "1T", "124", "44", + "FCC", "5G", "20M", "OFDM", "1T", "128", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "44", + "MKK", "5G", "20M", "OFDM", "1T", "128", "44", + "FCC", "5G", "20M", "OFDM", "1T", "132", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "44", + "MKK", "5G", "20M", "OFDM", "1T", "132", "44", + "FCC", "5G", "20M", "OFDM", "1T", "136", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "44", + "MKK", "5G", "20M", "OFDM", "1T", "136", "44", + "FCC", "5G", "20M", "OFDM", "1T", "140", "40", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "40", + "MKK", "5G", "20M", "OFDM", "1T", "140", "40", + "FCC", "5G", "20M", "OFDM", "1T", "149", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "42", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "44", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "44", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "44", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "44", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "42", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "42", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "40", + "ETSI", "5G", "20M", "HT", "1T", "36", "40", + "MKK", "5G", "20M", "HT", "1T", "36", "40", + "FCC", "5G", "20M", "HT", "1T", "40", "44", + "ETSI", "5G", "20M", "HT", "1T", "40", "44", + "MKK", "5G", "20M", "HT", "1T", "40", "44", + "FCC", "5G", "20M", "HT", "1T", "44", "44", + "ETSI", "5G", "20M", "HT", "1T", "44", "44", + "MKK", "5G", "20M", "HT", "1T", "44", "44", + "FCC", "5G", "20M", "HT", "1T", "48", "44", + "ETSI", "5G", "20M", "HT", "1T", "48", "44", + "MKK", "5G", "20M", "HT", "1T", "48", "44", + "FCC", "5G", "20M", "HT", "1T", "52", "44", + "ETSI", "5G", "20M", "HT", "1T", "52", "44", + "MKK", "5G", "20M", "HT", "1T", "52", "44", + "FCC", "5G", "20M", "HT", "1T", "56", "44", + "ETSI", "5G", "20M", "HT", "1T", "56", "44", + "MKK", "5G", "20M", "HT", "1T", "56", "44", + "FCC", "5G", "20M", "HT", "1T", "60", "44", + "ETSI", "5G", "20M", "HT", "1T", "60", "44", + "MKK", "5G", "20M", "HT", "1T", "60", "44", + "FCC", "5G", "20M", "HT", "1T", "64", "42", + "ETSI", "5G", "20M", "HT", "1T", "64", "42", + "MKK", "5G", "20M", "HT", "1T", "64", "42", + "FCC", "5G", "20M", "HT", "1T", "100", "40", + "ETSI", "5G", "20M", "HT", "1T", "100", "40", + "MKK", "5G", "20M", "HT", "1T", "100", "40", + "FCC", "5G", "20M", "HT", "1T", "104", "44", + "ETSI", "5G", "20M", "HT", "1T", "104", "44", + "MKK", "5G", "20M", "HT", "1T", "104", "44", + "FCC", "5G", "20M", "HT", "1T", "108", "44", + "ETSI", "5G", "20M", "HT", "1T", "108", "44", + "MKK", "5G", "20M", "HT", "1T", "108", "44", + "FCC", "5G", "20M", "HT", "1T", "112", "44", + "ETSI", "5G", "20M", "HT", "1T", "112", "44", + "MKK", "5G", "20M", "HT", "1T", "112", "44", + "FCC", "5G", "20M", "HT", "1T", "116", "44", + "ETSI", "5G", "20M", "HT", "1T", "116", "44", + "MKK", "5G", "20M", "HT", "1T", "116", "44", + "FCC", "5G", "20M", "HT", "1T", "120", "44", + "ETSI", "5G", "20M", "HT", "1T", "120", "44", + "MKK", "5G", "20M", "HT", "1T", "120", "44", + "FCC", "5G", "20M", "HT", "1T", "124", "44", + "ETSI", "5G", "20M", "HT", "1T", "124", "44", + "MKK", "5G", "20M", "HT", "1T", "124", "44", + "FCC", "5G", "20M", "HT", "1T", "128", "44", + "ETSI", "5G", "20M", "HT", "1T", "128", "44", + "MKK", "5G", "20M", "HT", "1T", "128", "44", + "FCC", "5G", "20M", "HT", "1T", "132", "44", + "ETSI", "5G", "20M", "HT", "1T", "132", "44", + "MKK", "5G", "20M", "HT", "1T", "132", "44", + "FCC", "5G", "20M", "HT", "1T", "136", "44", + "ETSI", "5G", "20M", "HT", "1T", "136", "44", + "MKK", "5G", "20M", "HT", "1T", "136", "44", + "FCC", "5G", "20M", "HT", "1T", "140", "40", + "ETSI", "5G", "20M", "HT", "1T", "140", "40", + "MKK", "5G", "20M", "HT", "1T", "140", "40", + "FCC", "5G", "20M", "HT", "1T", "149", "44", + "ETSI", "5G", "20M", "HT", "1T", "149", "44", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "44", + "ETSI", "5G", "20M", "HT", "1T", "153", "44", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "44", + "ETSI", "5G", "20M", "HT", "1T", "157", "44", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "44", + "ETSI", "5G", "20M", "HT", "1T", "161", "44", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "42", + "ETSI", "5G", "20M", "HT", "1T", "165", "42", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "40", + "ETSI", "5G", "20M", "HT", "2T", "36", "40", + "MKK", "5G", "20M", "HT", "2T", "36", "40", + "FCC", "5G", "20M", "HT", "2T", "40", "44", + "ETSI", "5G", "20M", "HT", "2T", "40", "44", + "MKK", "5G", "20M", "HT", "2T", "40", "44", + "FCC", "5G", "20M", "HT", "2T", "44", "44", + "ETSI", "5G", "20M", "HT", "2T", "44", "44", + "MKK", "5G", "20M", "HT", "2T", "44", "44", + "FCC", "5G", "20M", "HT", "2T", "48", "44", + "ETSI", "5G", "20M", "HT", "2T", "48", "44", + "MKK", "5G", "20M", "HT", "2T", "48", "44", + "FCC", "5G", "20M", "HT", "2T", "52", "44", + "ETSI", "5G", "20M", "HT", "2T", "52", "44", + "MKK", "5G", "20M", "HT", "2T", "52", "44", + "FCC", "5G", "20M", "HT", "2T", "56", "44", + "ETSI", "5G", "20M", "HT", "2T", "56", "44", + "MKK", "5G", "20M", "HT", "2T", "56", "44", + "FCC", "5G", "20M", "HT", "2T", "60", "44", + "ETSI", "5G", "20M", "HT", "2T", "60", "44", + "MKK", "5G", "20M", "HT", "2T", "60", "44", + "FCC", "5G", "20M", "HT", "2T", "64", "42", + "ETSI", "5G", "20M", "HT", "2T", "64", "42", + "MKK", "5G", "20M", "HT", "2T", "64", "42", + "FCC", "5G", "20M", "HT", "2T", "100", "40", + "ETSI", "5G", "20M", "HT", "2T", "100", "40", + "MKK", "5G", "20M", "HT", "2T", "100", "40", + "FCC", "5G", "20M", "HT", "2T", "104", "44", + "ETSI", "5G", "20M", "HT", "2T", "104", "44", + "MKK", "5G", "20M", "HT", "2T", "104", "44", + "FCC", "5G", "20M", "HT", "2T", "108", "44", + "ETSI", "5G", "20M", "HT", "2T", "108", "44", + "MKK", "5G", "20M", "HT", "2T", "108", "44", + "FCC", "5G", "20M", "HT", "2T", "112", "44", + "ETSI", "5G", "20M", "HT", "2T", "112", "44", + "MKK", "5G", "20M", "HT", "2T", "112", "44", + "FCC", "5G", "20M", "HT", "2T", "116", "44", + "ETSI", "5G", "20M", "HT", "2T", "116", "44", + "MKK", "5G", "20M", "HT", "2T", "116", "44", + "FCC", "5G", "20M", "HT", "2T", "120", "44", + "ETSI", "5G", "20M", "HT", "2T", "120", "44", + "MKK", "5G", "20M", "HT", "2T", "120", "44", + "FCC", "5G", "20M", "HT", "2T", "124", "44", + "ETSI", "5G", "20M", "HT", "2T", "124", "44", + "MKK", "5G", "20M", "HT", "2T", "124", "44", + "FCC", "5G", "20M", "HT", "2T", "128", "44", + "ETSI", "5G", "20M", "HT", "2T", "128", "44", + "MKK", "5G", "20M", "HT", "2T", "128", "44", + "FCC", "5G", "20M", "HT", "2T", "132", "44", + "ETSI", "5G", "20M", "HT", "2T", "132", "44", + "MKK", "5G", "20M", "HT", "2T", "132", "44", + "FCC", "5G", "20M", "HT", "2T", "136", "44", + "ETSI", "5G", "20M", "HT", "2T", "136", "44", + "MKK", "5G", "20M", "HT", "2T", "136", "44", + "FCC", "5G", "20M", "HT", "2T", "140", "40", + "ETSI", "5G", "20M", "HT", "2T", "140", "40", + "MKK", "5G", "20M", "HT", "2T", "140", "40", + "FCC", "5G", "20M", "HT", "2T", "149", "44", + "ETSI", "5G", "20M", "HT", "2T", "149", "44", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "44", + "ETSI", "5G", "20M", "HT", "2T", "153", "44", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "44", + "ETSI", "5G", "20M", "HT", "2T", "157", "44", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "44", + "ETSI", "5G", "20M", "HT", "2T", "161", "44", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "42", + "ETSI", "5G", "20M", "HT", "2T", "165", "42", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "40", + "ETSI", "5G", "20M", "HT", "3T", "36", "40", + "MKK", "5G", "20M", "HT", "3T", "36", "40", + "FCC", "5G", "20M", "HT", "3T", "40", "44", + "ETSI", "5G", "20M", "HT", "3T", "40", "44", + "MKK", "5G", "20M", "HT", "3T", "40", "44", + "FCC", "5G", "20M", "HT", "3T", "44", "44", + "ETSI", "5G", "20M", "HT", "3T", "44", "44", + "MKK", "5G", "20M", "HT", "3T", "44", "44", + "FCC", "5G", "20M", "HT", "3T", "48", "44", + "ETSI", "5G", "20M", "HT", "3T", "48", "44", + "MKK", "5G", "20M", "HT", "3T", "48", "44", + "FCC", "5G", "20M", "HT", "3T", "52", "44", + "ETSI", "5G", "20M", "HT", "3T", "52", "44", + "MKK", "5G", "20M", "HT", "3T", "52", "44", + "FCC", "5G", "20M", "HT", "3T", "56", "44", + "ETSI", "5G", "20M", "HT", "3T", "56", "44", + "MKK", "5G", "20M", "HT", "3T", "56", "44", + "FCC", "5G", "20M", "HT", "3T", "60", "44", + "ETSI", "5G", "20M", "HT", "3T", "60", "44", + "MKK", "5G", "20M", "HT", "3T", "60", "44", + "FCC", "5G", "20M", "HT", "3T", "64", "42", + "ETSI", "5G", "20M", "HT", "3T", "64", "42", + "MKK", "5G", "20M", "HT", "3T", "64", "42", + "FCC", "5G", "20M", "HT", "3T", "100", "40", + "ETSI", "5G", "20M", "HT", "3T", "100", "40", + "MKK", "5G", "20M", "HT", "3T", "100", "40", + "FCC", "5G", "20M", "HT", "3T", "104", "44", + "ETSI", "5G", "20M", "HT", "3T", "104", "44", + "MKK", "5G", "20M", "HT", "3T", "104", "44", + "FCC", "5G", "20M", "HT", "3T", "108", "44", + "ETSI", "5G", "20M", "HT", "3T", "108", "44", + "MKK", "5G", "20M", "HT", "3T", "108", "44", + "FCC", "5G", "20M", "HT", "3T", "112", "44", + "ETSI", "5G", "20M", "HT", "3T", "112", "44", + "MKK", "5G", "20M", "HT", "3T", "112", "44", + "FCC", "5G", "20M", "HT", "3T", "116", "44", + "ETSI", "5G", "20M", "HT", "3T", "116", "44", + "MKK", "5G", "20M", "HT", "3T", "116", "44", + "FCC", "5G", "20M", "HT", "3T", "120", "44", + "ETSI", "5G", "20M", "HT", "3T", "120", "44", + "MKK", "5G", "20M", "HT", "3T", "120", "44", + "FCC", "5G", "20M", "HT", "3T", "124", "44", + "ETSI", "5G", "20M", "HT", "3T", "124", "44", + "MKK", "5G", "20M", "HT", "3T", "124", "44", + "FCC", "5G", "20M", "HT", "3T", "128", "44", + "ETSI", "5G", "20M", "HT", "3T", "128", "44", + "MKK", "5G", "20M", "HT", "3T", "128", "44", + "FCC", "5G", "20M", "HT", "3T", "132", "44", + "ETSI", "5G", "20M", "HT", "3T", "132", "44", + "MKK", "5G", "20M", "HT", "3T", "132", "44", + "FCC", "5G", "20M", "HT", "3T", "136", "44", + "ETSI", "5G", "20M", "HT", "3T", "136", "44", + "MKK", "5G", "20M", "HT", "3T", "136", "44", + "FCC", "5G", "20M", "HT", "3T", "140", "40", + "ETSI", "5G", "20M", "HT", "3T", "140", "40", + "MKK", "5G", "20M", "HT", "3T", "140", "40", + "FCC", "5G", "20M", "HT", "3T", "149", "44", + "ETSI", "5G", "20M", "HT", "3T", "149", "44", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "44", + "ETSI", "5G", "20M", "HT", "3T", "153", "44", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "44", + "ETSI", "5G", "20M", "HT", "3T", "157", "44", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "44", + "ETSI", "5G", "20M", "HT", "3T", "161", "44", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "42", + "ETSI", "5G", "20M", "HT", "3T", "165", "42", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "40", + "ETSI", "5G", "20M", "HT", "4T", "36", "40", + "MKK", "5G", "20M", "HT", "4T", "36", "40", + "FCC", "5G", "20M", "HT", "4T", "40", "44", + "ETSI", "5G", "20M", "HT", "4T", "40", "44", + "MKK", "5G", "20M", "HT", "4T", "40", "44", + "FCC", "5G", "20M", "HT", "4T", "44", "44", + "ETSI", "5G", "20M", "HT", "4T", "44", "44", + "MKK", "5G", "20M", "HT", "4T", "44", "44", + "FCC", "5G", "20M", "HT", "4T", "48", "44", + "ETSI", "5G", "20M", "HT", "4T", "48", "44", + "MKK", "5G", "20M", "HT", "4T", "48", "44", + "FCC", "5G", "20M", "HT", "4T", "52", "44", + "ETSI", "5G", "20M", "HT", "4T", "52", "44", + "MKK", "5G", "20M", "HT", "4T", "52", "44", + "FCC", "5G", "20M", "HT", "4T", "56", "44", + "ETSI", "5G", "20M", "HT", "4T", "56", "44", + "MKK", "5G", "20M", "HT", "4T", "56", "44", + "FCC", "5G", "20M", "HT", "4T", "60", "44", + "ETSI", "5G", "20M", "HT", "4T", "60", "44", + "MKK", "5G", "20M", "HT", "4T", "60", "44", + "FCC", "5G", "20M", "HT", "4T", "64", "42", + "ETSI", "5G", "20M", "HT", "4T", "64", "42", + "MKK", "5G", "20M", "HT", "4T", "64", "42", + "FCC", "5G", "20M", "HT", "4T", "100", "40", + "ETSI", "5G", "20M", "HT", "4T", "100", "40", + "MKK", "5G", "20M", "HT", "4T", "100", "40", + "FCC", "5G", "20M", "HT", "4T", "104", "44", + "ETSI", "5G", "20M", "HT", "4T", "104", "44", + "MKK", "5G", "20M", "HT", "4T", "104", "44", + "FCC", "5G", "20M", "HT", "4T", "108", "44", + "ETSI", "5G", "20M", "HT", "4T", "108", "44", + "MKK", "5G", "20M", "HT", "4T", "108", "44", + "FCC", "5G", "20M", "HT", "4T", "112", "44", + "ETSI", "5G", "20M", "HT", "4T", "112", "44", + "MKK", "5G", "20M", "HT", "4T", "112", "44", + "FCC", "5G", "20M", "HT", "4T", "116", "44", + "ETSI", "5G", "20M", "HT", "4T", "116", "44", + "MKK", "5G", "20M", "HT", "4T", "116", "44", + "FCC", "5G", "20M", "HT", "4T", "120", "44", + "ETSI", "5G", "20M", "HT", "4T", "120", "44", + "MKK", "5G", "20M", "HT", "4T", "120", "44", + "FCC", "5G", "20M", "HT", "4T", "124", "44", + "ETSI", "5G", "20M", "HT", "4T", "124", "44", + "MKK", "5G", "20M", "HT", "4T", "124", "44", + "FCC", "5G", "20M", "HT", "4T", "128", "44", + "ETSI", "5G", "20M", "HT", "4T", "128", "44", + "MKK", "5G", "20M", "HT", "4T", "128", "44", + "FCC", "5G", "20M", "HT", "4T", "132", "44", + "ETSI", "5G", "20M", "HT", "4T", "132", "44", + "MKK", "5G", "20M", "HT", "4T", "132", "44", + "FCC", "5G", "20M", "HT", "4T", "136", "44", + "ETSI", "5G", "20M", "HT", "4T", "136", "44", + "MKK", "5G", "20M", "HT", "4T", "136", "44", + "FCC", "5G", "20M", "HT", "4T", "140", "40", + "ETSI", "5G", "20M", "HT", "4T", "140", "40", + "MKK", "5G", "20M", "HT", "4T", "140", "40", + "FCC", "5G", "20M", "HT", "4T", "149", "44", + "ETSI", "5G", "20M", "HT", "4T", "149", "44", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "44", + "ETSI", "5G", "20M", "HT", "4T", "153", "44", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "44", + "ETSI", "5G", "20M", "HT", "4T", "157", "44", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "44", + "ETSI", "5G", "20M", "HT", "4T", "161", "44", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "42", + "ETSI", "5G", "20M", "HT", "4T", "165", "42", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "34", + "ETSI", "5G", "40M", "HT", "1T", "38", "34", + "MKK", "5G", "40M", "HT", "1T", "38", "34", + "FCC", "5G", "40M", "HT", "1T", "46", "44", + "ETSI", "5G", "40M", "HT", "1T", "46", "44", + "MKK", "5G", "40M", "HT", "1T", "46", "44", + "FCC", "5G", "40M", "HT", "1T", "54", "44", + "ETSI", "5G", "40M", "HT", "1T", "54", "44", + "MKK", "5G", "40M", "HT", "1T", "54", "44", + "FCC", "5G", "40M", "HT", "1T", "62", "34", + "ETSI", "5G", "40M", "HT", "1T", "62", "34", + "MKK", "5G", "40M", "HT", "1T", "62", "34", + "FCC", "5G", "40M", "HT", "1T", "102", "34", + "ETSI", "5G", "40M", "HT", "1T", "102", "34", + "MKK", "5G", "40M", "HT", "1T", "102", "34", + "FCC", "5G", "40M", "HT", "1T", "110", "44", + "ETSI", "5G", "40M", "HT", "1T", "110", "44", + "MKK", "5G", "40M", "HT", "1T", "110", "44", + "FCC", "5G", "40M", "HT", "1T", "118", "44", + "ETSI", "5G", "40M", "HT", "1T", "118", "44", + "MKK", "5G", "40M", "HT", "1T", "118", "44", + "FCC", "5G", "40M", "HT", "1T", "126", "44", + "ETSI", "5G", "40M", "HT", "1T", "126", "44", + "MKK", "5G", "40M", "HT", "1T", "126", "44", + "FCC", "5G", "40M", "HT", "1T", "134", "42", + "ETSI", "5G", "40M", "HT", "1T", "134", "42", + "MKK", "5G", "40M", "HT", "1T", "134", "42", + "FCC", "5G", "40M", "HT", "1T", "151", "42", + "ETSI", "5G", "40M", "HT", "1T", "151", "42", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "42", + "ETSI", "5G", "40M", "HT", "1T", "159", "42", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "34", + "ETSI", "5G", "40M", "HT", "2T", "38", "34", + "MKK", "5G", "40M", "HT", "2T", "38", "34", + "FCC", "5G", "40M", "HT", "2T", "46", "44", + "ETSI", "5G", "40M", "HT", "2T", "46", "44", + "MKK", "5G", "40M", "HT", "2T", "46", "44", + "FCC", "5G", "40M", "HT", "2T", "54", "44", + "ETSI", "5G", "40M", "HT", "2T", "54", "44", + "MKK", "5G", "40M", "HT", "2T", "54", "44", + "FCC", "5G", "40M", "HT", "2T", "62", "34", + "ETSI", "5G", "40M", "HT", "2T", "62", "34", + "MKK", "5G", "40M", "HT", "2T", "62", "34", + "FCC", "5G", "40M", "HT", "2T", "102", "34", + "ETSI", "5G", "40M", "HT", "2T", "102", "34", + "MKK", "5G", "40M", "HT", "2T", "102", "34", + "FCC", "5G", "40M", "HT", "2T", "110", "44", + "ETSI", "5G", "40M", "HT", "2T", "110", "44", + "MKK", "5G", "40M", "HT", "2T", "110", "44", + "FCC", "5G", "40M", "HT", "2T", "118", "44", + "ETSI", "5G", "40M", "HT", "2T", "118", "44", + "MKK", "5G", "40M", "HT", "2T", "118", "44", + "FCC", "5G", "40M", "HT", "2T", "126", "44", + "ETSI", "5G", "40M", "HT", "2T", "126", "44", + "MKK", "5G", "40M", "HT", "2T", "126", "44", + "FCC", "5G", "40M", "HT", "2T", "134", "42", + "ETSI", "5G", "40M", "HT", "2T", "134", "42", + "MKK", "5G", "40M", "HT", "2T", "134", "42", + "FCC", "5G", "40M", "HT", "2T", "151", "42", + "ETSI", "5G", "40M", "HT", "2T", "151", "42", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "42", + "ETSI", "5G", "40M", "HT", "2T", "159", "42", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "34", + "ETSI", "5G", "40M", "HT", "3T", "38", "34", + "MKK", "5G", "40M", "HT", "3T", "38", "34", + "FCC", "5G", "40M", "HT", "3T", "46", "44", + "ETSI", "5G", "40M", "HT", "3T", "46", "44", + "MKK", "5G", "40M", "HT", "3T", "46", "44", + "FCC", "5G", "40M", "HT", "3T", "54", "44", + "ETSI", "5G", "40M", "HT", "3T", "54", "44", + "MKK", "5G", "40M", "HT", "3T", "54", "44", + "FCC", "5G", "40M", "HT", "3T", "62", "34", + "ETSI", "5G", "40M", "HT", "3T", "62", "34", + "MKK", "5G", "40M", "HT", "3T", "62", "34", + "FCC", "5G", "40M", "HT", "3T", "102", "34", + "ETSI", "5G", "40M", "HT", "3T", "102", "34", + "MKK", "5G", "40M", "HT", "3T", "102", "34", + "FCC", "5G", "40M", "HT", "3T", "110", "44", + "ETSI", "5G", "40M", "HT", "3T", "110", "44", + "MKK", "5G", "40M", "HT", "3T", "110", "44", + "FCC", "5G", "40M", "HT", "3T", "118", "44", + "ETSI", "5G", "40M", "HT", "3T", "118", "44", + "MKK", "5G", "40M", "HT", "3T", "118", "44", + "FCC", "5G", "40M", "HT", "3T", "126", "44", + "ETSI", "5G", "40M", "HT", "3T", "126", "44", + "MKK", "5G", "40M", "HT", "3T", "126", "44", + "FCC", "5G", "40M", "HT", "3T", "134", "42", + "ETSI", "5G", "40M", "HT", "3T", "134", "42", + "MKK", "5G", "40M", "HT", "3T", "134", "42", + "FCC", "5G", "40M", "HT", "3T", "151", "42", + "ETSI", "5G", "40M", "HT", "3T", "151", "42", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "42", + "ETSI", "5G", "40M", "HT", "3T", "159", "42", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "34", + "ETSI", "5G", "40M", "HT", "4T", "38", "34", + "MKK", "5G", "40M", "HT", "4T", "38", "34", + "FCC", "5G", "40M", "HT", "4T", "46", "44", + "ETSI", "5G", "40M", "HT", "4T", "46", "44", + "MKK", "5G", "40M", "HT", "4T", "46", "44", + "FCC", "5G", "40M", "HT", "4T", "54", "44", + "ETSI", "5G", "40M", "HT", "4T", "54", "44", + "MKK", "5G", "40M", "HT", "4T", "54", "44", + "FCC", "5G", "40M", "HT", "4T", "62", "34", + "ETSI", "5G", "40M", "HT", "4T", "62", "34", + "MKK", "5G", "40M", "HT", "4T", "62", "34", + "FCC", "5G", "40M", "HT", "4T", "102", "34", + "ETSI", "5G", "40M", "HT", "4T", "102", "34", + "MKK", "5G", "40M", "HT", "4T", "102", "34", + "FCC", "5G", "40M", "HT", "4T", "110", "44", + "ETSI", "5G", "40M", "HT", "4T", "110", "44", + "MKK", "5G", "40M", "HT", "4T", "110", "44", + "FCC", "5G", "40M", "HT", "4T", "118", "44", + "ETSI", "5G", "40M", "HT", "4T", "118", "44", + "MKK", "5G", "40M", "HT", "4T", "118", "44", + "FCC", "5G", "40M", "HT", "4T", "126", "44", + "ETSI", "5G", "40M", "HT", "4T", "126", "44", + "MKK", "5G", "40M", "HT", "4T", "126", "44", + "FCC", "5G", "40M", "HT", "4T", "134", "42", + "ETSI", "5G", "40M", "HT", "4T", "134", "42", + "MKK", "5G", "40M", "HT", "4T", "134", "42", + "FCC", "5G", "40M", "HT", "4T", "151", "42", + "ETSI", "5G", "40M", "HT", "4T", "151", "42", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "42", + "ETSI", "5G", "40M", "HT", "4T", "159", "42", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "28", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "44", + "ETSI", "5G", "80M", "VHT", "1T", "122", "44", + "MKK", "5G", "80M", "VHT", "1T", "122", "44", + "FCC", "5G", "80M", "VHT", "1T", "155", "40", + "ETSI", "5G", "80M", "VHT", "1T", "155", "40", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "30", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "28", + "ETSI", "5G", "80M", "VHT", "2T", "58", "28", + "MKK", "5G", "80M", "VHT", "2T", "58", "28", + "FCC", "5G", "80M", "VHT", "2T", "106", "30", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "44", + "ETSI", "5G", "80M", "VHT", "2T", "122", "44", + "MKK", "5G", "80M", "VHT", "2T", "122", "44", + "FCC", "5G", "80M", "VHT", "2T", "155", "40", + "ETSI", "5G", "80M", "VHT", "2T", "155", "40", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "30", + "ETSI", "5G", "80M", "VHT", "3T", "42", "30", + "MKK", "5G", "80M", "VHT", "3T", "42", "30", + "FCC", "5G", "80M", "VHT", "3T", "58", "28", + "ETSI", "5G", "80M", "VHT", "3T", "58", "28", + "MKK", "5G", "80M", "VHT", "3T", "58", "28", + "FCC", "5G", "80M", "VHT", "3T", "106", "30", + "ETSI", "5G", "80M", "VHT", "3T", "106", "30", + "MKK", "5G", "80M", "VHT", "3T", "106", "30", + "FCC", "5G", "80M", "VHT", "3T", "122", "44", + "ETSI", "5G", "80M", "VHT", "3T", "122", "44", + "MKK", "5G", "80M", "VHT", "3T", "122", "44", + "FCC", "5G", "80M", "VHT", "3T", "155", "40", + "ETSI", "5G", "80M", "VHT", "3T", "155", "40", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "30", + "ETSI", "5G", "80M", "VHT", "4T", "42", "30", + "MKK", "5G", "80M", "VHT", "4T", "42", "30", + "FCC", "5G", "80M", "VHT", "4T", "58", "28", + "ETSI", "5G", "80M", "VHT", "4T", "58", "28", + "MKK", "5G", "80M", "VHT", "4T", "58", "28", + "FCC", "5G", "80M", "VHT", "4T", "106", "30", + "ETSI", "5G", "80M", "VHT", "4T", "106", "30", + "MKK", "5G", "80M", "VHT", "4T", "106", "30", + "FCC", "5G", "80M", "VHT", "4T", "122", "44", + "ETSI", "5G", "80M", "VHT", "4T", "122", "44", + "MKK", "5G", "80M", "VHT", "4T", "122", "44", + "FCC", "5G", "80M", "VHT", "4T", "155", "40", + "ETSI", "5G", "80M", "VHT", "4T", "155", "40", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type9)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8814A_TXPWR_LMT_Type9; +#else + u4Byte ArrayLen = sizeof(Array_MP_8814A_TXPWR_LMT_Type9)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8814A_TXPWR_LMT_Type9; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.h index d967404c7af..265feb7e134 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halhwimg8814a_rf.h @@ -1,294 +1,294 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8814A_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8814A_H -#define __INC_MP_RF_HW_IMG_8814A_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_RadioA(void); - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_RadioB(void); - -/****************************************************************************** -* RadioC.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_RadioC(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_RadioC(void); - -/****************************************************************************** -* RadioD.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_RadioD(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_RadioD(void); - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack(void); - -/****************************************************************************** -* TxPowerTrack_Type0.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type0(void); - -/****************************************************************************** -* TxPowerTrack_Type1.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type1(void); - -/****************************************************************************** -* TxPowerTrack_Type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type2(void); - -/****************************************************************************** -* TxPowerTrack_Type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type3(void); - -/****************************************************************************** -* TxPowerTrack_Type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type4(void); - -/****************************************************************************** -* TxPowerTrack_Type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type5(void); - -/****************************************************************************** -* TxPowerTrack_Type6.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type6(void); - -/****************************************************************************** -* TxPowerTrack_Type7.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type7(void); - -/****************************************************************************** -* TxPowerTrack_Type8.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type8(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type8(void); - -/****************************************************************************** -* TxPowerTrack_Type9.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type9(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type9(void); - -/****************************************************************************** -* TxPowerTSSI.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TxPowerTSSI(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TxPowerTSSI(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT(void); - -/****************************************************************************** -* TXPWR_LMT_Type0.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type0(void); - -/****************************************************************************** -* TXPWR_LMT_Type1.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type1(void); - -/****************************************************************************** -* TXPWR_LMT_Type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type2(void); - -/****************************************************************************** -* TXPWR_LMT_Type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type3(void); - -/****************************************************************************** -* TXPWR_LMT_Type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type4(void); - -/****************************************************************************** -* TXPWR_LMT_Type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type5(void); - -/****************************************************************************** -* TXPWR_LMT_Type6.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type6(void); - -/****************************************************************************** -* TXPWR_LMT_Type7.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type7(void); - -/****************************************************************************** -* TXPWR_LMT_Type8.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type8(void); - -/****************************************************************************** -* TXPWR_LMT_Type9.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type9(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8814A_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8814A_H +#define __INC_MP_RF_HW_IMG_8814A_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_RadioA(void); + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_RadioB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_RadioB(void); + +/****************************************************************************** +* RadioC.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_RadioC(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_RadioC(void); + +/****************************************************************************** +* RadioD.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_RadioD(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_RadioD(void); + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack(void); + +/****************************************************************************** +* TxPowerTrack_Type0.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type0(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type0(void); + +/****************************************************************************** +* TxPowerTrack_Type1.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type1(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type1(void); + +/****************************************************************************** +* TxPowerTrack_Type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type2(void); + +/****************************************************************************** +* TxPowerTrack_Type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type3(void); + +/****************************************************************************** +* TxPowerTrack_Type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type4(void); + +/****************************************************************************** +* TxPowerTrack_Type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type5(void); + +/****************************************************************************** +* TxPowerTrack_Type6.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type6(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type6(void); + +/****************************************************************************** +* TxPowerTrack_Type7.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type7(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type7(void); + +/****************************************************************************** +* TxPowerTrack_Type8.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type8(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type8(void); + +/****************************************************************************** +* TxPowerTrack_Type9.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTrack_Type9(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type9(void); + +/****************************************************************************** +* TxPowerTSSI.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TxPowerTSSI(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TxPowerTSSI(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT(void); + +/****************************************************************************** +* TXPWR_LMT_Type0.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type0(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type0(void); + +/****************************************************************************** +* TXPWR_LMT_Type1.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type1(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type1(void); + +/****************************************************************************** +* TXPWR_LMT_Type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type2(void); + +/****************************************************************************** +* TXPWR_LMT_Type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type3(void); + +/****************************************************************************** +* TXPWR_LMT_Type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type4(void); + +/****************************************************************************** +* TXPWR_LMT_Type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type5(void); + +/****************************************************************************** +* TXPWR_LMT_Type6.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type6(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type6(void); + +/****************************************************************************** +* TXPWR_LMT_Type7.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type7(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type7(void); + +/****************************************************************************** +* TXPWR_LMT_Type8.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type8(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type8(void); + +/****************************************************************************** +* TXPWR_LMT_Type9.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8814A_TXPWR_LMT_Type9(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type9(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.c index 9c01784da96..49b33f27bef 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.c @@ -1,1754 +1,1754 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#if !defined(__ECOS) && !defined(CONFIG_COMPAT_WIRELESS) -#include "mp_precomp.h" -#else -#include "../mp_precomp.h" -#endif -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8814A 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - -u1Byte -CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ) -{ - s1Byte UpperBound = 10, LowerBound = -5; // 4'b1010 = 10 - s1Byte Final_RF_Index = 0; - BOOLEAN bPositive = FALSE; - u4Byte bitMask = 0; - u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4;// upper bound +2dB, lower bound -9dB - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if(Method == MIX_MODE) //normal Tx power tracking - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("is 8814 MP chip\n")); - bitMask = BIT19; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; - - if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not - bPositive = TRUE; - else - bPositive = FALSE; - - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, bPositive); - - bitMask = BIT18|BIT17|BIT16|BIT15; - Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ - - } - - if(Final_RF_Index > UpperBound) //Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB - { - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, UpperBound); //set RF Reg0x55 per path - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); - - if(Final_OFDM_Swing_Index > TxScalingUpperBound) // bb swing upper bound = +2dB - Final_OFDM_Swing_Index = TxScalingUpperBound; - - return Final_OFDM_Swing_Index; - } - else if(Final_RF_Index < LowerBound) // lower bound = -5dB - { - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*(LowerBound)); //set RF Reg0x55 per path - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound<<1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - - if(Final_OFDM_Swing_Index < TxScalingLowerBound) // bb swing lower bound = -10dB - Final_OFDM_Swing_Index = TxScalingLowerBound; - return Final_OFDM_Swing_Index; - } - else // normal case - { - - if(bPositive == TRUE) - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); //set RF Reg0x55 per path - else - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); //set RF Reg0x55 per path - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2; - return Final_OFDM_Swing_Index; - } - - return FALSE; -} - - -VOID -ODM_TxPwrTrackSetPwr8814A( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); -#endif - u1Byte Final_OFDM_Swing_Index = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_OFDM_Swing_Index = CheckRFGainOffset(pDM_Odm, MIX_MODE, RFPath); - } - else if(Method == TSSI_MODE) - { - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0); - } - else if(Method == BBSWING) // use for mp driver clean power tracking status - { - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - - ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0); - } - - if((Method == MIX_MODE) || (Method == BBSWING)) - { - switch(RFPath) - { - case ODM_RF_PATH_A: - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - break; - - case ODM_RF_PATH_B: - - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - break; - - case ODM_RF_PATH_C: - - ODM_SetBBReg(pDM_Odm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - break; - - case ODM_RF_PATH_D: - - ODM_SetBBReg(pDM_Odm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - break; - - default: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!! \n")); - - break; - } - } - return; -} // ODM_TxPwrTrackSetPwr8814A - -VOID -GetDeltaSwingTable_8814A( - IN PDM_ODM_T pDM_Odm, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u2Byte rate = *(pDM_Odm->pForcedDataRate); - u1Byte channel = *(pDM_Odm->pChannel); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(rate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - } - - return; -} - - -VOID -GetDeltaSwingTable_8814A_PathCD( - IN PDM_ODM_T pDM_Odm, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D - ) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u2Byte rate = *(pDM_Odm->pForcedDataRate); - u1Byte channel = *(pDM_Odm->pChannel); - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(rate)) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; - } else { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; - } else { - *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; - *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; - } - - return; -} - - -void ConfigureTxpowerTrack_8814A( - IN PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = ODM_CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = ODM_OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; - pConfig->RfPathCount = MAX_PATH_NUM_8814A; - pConfig->ThermalRegAddr = RF_T_METER_8814A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; - pConfig->DoIQK = DoIQK_8814A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; - pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; -} - - - -//1 7. IQK - - - -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c -#if 0 //!(DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) -{ - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; - } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; - } - */ - return TRUE; -} -#endif - -VOID - _PHY_SaveADDARegisters_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); - for( i = 0 ; i < RegisterNum ; i++){ - ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); - } -} - - -VOID - _PHY_SaveMACRegisters_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); - for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); - } - MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); - -} - - -VOID - _PHY_ReloadADDARegisters_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegiesterNum - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); - for(i = 0 ; i < RegiesterNum; i++) - { - ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); - } -} - -VOID - _PHY_ReloadMACRegisters_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); - for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); - } - ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); -} - - - -VOID - _PHY_MACSettingCalibration_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ) -{ - u4Byte i = 0; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); - - ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); - - for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); - } - ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); - -} - -#if 0 -#define BW_20M 0 -#define BW_40M 1 -#define BW_80M 2 -#endif - -VOID - phy_LCCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ - u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; - u4Byte cnt; - - //Check continuous TX and Packet TX - u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; - - // Backup RF reg18. - - if((reg0x914 & 0x70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812, 0xFF); - - //3 3. Read RF reg18 - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - //3 4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000, 0x1); - - ODM_delay_ms(100); - - for (cnt = 0; cnt < 100; cnt++) { - if(ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - ODM_delay_ms(10); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); - - - //3 Restore original situation - if((reg0x914 & 70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812, 0x00); - - // Recover channel number - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); -} - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID - phy_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, apkbound; - u1Byte path, i, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a - // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if defined(MP_DRIVER) && (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#endif - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; - -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8814A() delta %d\n", delta)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - - // Temporarily do not allow normal driver to do the following settings because these offset - // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal - // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the - // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if !defined(MP_DRIVER) || (MP_DRIVER != 1) - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); - } - - //save MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_SaveMACRegisters_8814A(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters_8814A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_SaveMACRegisters_8814A(pDM_Odm, MAC_REG, MAC_backup); - - //save AFE default value - _PHY_SaveADDARegisters_8814A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - for(path = 0; path < pathbound; path++) - { - - - if(path == RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - } - else if(path == RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); - - offset += 0x04; - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); - } - - //save RF default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); -#else - regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); -#endif - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); - } - - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - - //MAC settings -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_MACSettingCalibration_8814A(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_MACSettingCalibration_8814A(pDM_Odm, MAC_REG, MAC_backup); -#endif - - if(path == RF_PATH_A) //Path B to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); - } - else //Path A to standby mode - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, (int)delta_V, (int)delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - - ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); -#else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); - ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); -#endif - - // PA11+PAD01111, one shot - i = 0; - do - { - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); - { - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - ODM_delay_ms(3); - ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); - - ODM_delay_ms(20); - } - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - - if(path == RF_PATH_A) - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); - else - tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadMACRegisters_8814A(pAdapter, MAC_REG, MAC_backup); -#else - _PHY_ReloadMACRegisters_8814A(pDM_Odm, MAC_REG, MAC_backup); -#endif - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - _PHY_ReloadADDARegisters_8814A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#else - _PHY_ReloadADDARegisters_8814A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); -#endif - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); - if(path == RF_PATH_B) - { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == RF_PATH_A) - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, - ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); -#endif - } - - pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8814A()\n")); -} - - - - - - -VOID -PHY_LCCalibrate_8814A( - IN PDM_ODM_T pDM_Odm - ) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); - phy_LCCalibrate_8814A(pDM_Odm, TRUE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); -} - -VOID - PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -#ifdef DISABLE_BB_RF - return; -#endif - - return; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) - { - return; - } -#endif - -#if defined(FOR_BRAZIL_PRETEST) && (FOR_BRAZIL_PRETEST != 1) - if(pDM_Odm->RFCalibrateInfo.bAPKdone) -#endif - return; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8814A(pAdapter, delta, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_APCalibrate_8814A(pAdapter, delta, FALSE); -#else - phy_APCalibrate_8814A(pDM_Odm, delta, FALSE); -#endif - } -} - VOID phy_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if(!pAdapter->bHWInitReady) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pAdapter->hw_init_completed == _FALSE) -#endif - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - -#endif - - if(is2T) //92C - { - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else //88C - { - - if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main - else - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux - } -} - VOID PHY_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#ifdef DISABLE_BB_RF - return; -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (IS_92C_SERIAL(pHalData->VersionID)) - { - phy_SetRFPathSwitch_8814A(pAdapter, bMain, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_SetRFPathSwitch_8814A(pAdapter, bMain, FALSE); -#else - phy_SetRFPathSwitch_8814A(pDM_Odm, bMain, FALSE); -#endif - } -} - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//digital predistortion -VOID - phy_DigitalPredistortion_8814A( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter, -#else - IN PDM_ODM_T pDM_Odm, -#endif - IN BOOLEAN is2T - ) -{ -#if (RT_PLATFORM == PLATFORM_WINDOWS) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - - u4Byte tmpReg, tmpReg2, index, i; - u1Byte path, pathbound = PATH_NUM; - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte BB_backup[DP_BB_REG_NUM]; - u4Byte BB_REG[DP_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rFPGA0_RFMOD, - rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE}; - u4Byte BB_settings[DP_BB_REG_NUM] = { - 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, - 0x0, 0x0, 0x0}; - - u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; - u4Byte RF_REG[DP_RF_REG_NUM] = { - RF_TXBIAS_A}; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { - {0x1e1e1e1e, 0x03901e1e}, - {0x18181818, 0x03901818}, - {0x0e0e0e0e, 0x03900e0e} - }; - - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u1Byte RetryCount = 0; - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8814A()\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8814A for %s %s\n", (is2T ? "2T2R" : "1T1R"))); - - //save BB default value - for(index=0; index tx_agc 1f ~11 - // PA gain = 11 & PAD2 => tx_agc 10~0e - // PA gain = 01 => tx_agc 0b~0d - // PA gain = 00 => tx_agc 0a~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - //PA gain = 11 => tx_agc = 1a - for(index = 0; index < 3; index++) - ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); - ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); - - //==================================== - // PAGE_B for Path-A DPK setting - //==================================== - // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 - ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); - - //rf_lpbk_setup - //1.rf 00:5205a, rf 0d:0e52c - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); - - //----send one shot signal----// - // Path A - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); - ODM_delay_ms(10); - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); - ODM_delay_ms(10); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); - pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; - break; - } - } - RetryCount = 0; - - //DPP path A - if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) - { - // DP settings - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - - for(i=rPdp_AntA; i<=0xb3c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); - } - - //pwsf - ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); - ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); - - for(i=0xb4c; i<=0xb5c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - //TX_AGC boundary - ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); - } - - //DPK path B - if(is2T) - { - //Path A to standby mode - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); - - // LUTs => tx_agc - // PA gain = 11 & PAD1, => tx_agc 1f ~11 - // PA gain = 11 & PAD2, => tx_agc 10 ~0e - // PA gain = 01 => tx_agc 0b ~0d - // PA gain = 00 => tx_agc 0a ~00 - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - - //do inner loopback DPK 3 times - for(i = 0; i < 3; i++) - { - //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); - - // PAGE_B for Path-A inner loopback DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - //----send one shot signal----// - // Path B - ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); - ODM_delay_ms(50); - } - - // PA gain = 11 => tx_agc = 1a - for(index = 0; index < 4; index++) - ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); - for(index = 0; index < 2; index++) - ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); - - // PAGE_B for Path-B DPK setting - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - // RF lpbk switches on - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); - - //Path-B RF lpbk - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); - ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); - - //----send one shot signal----// - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - - while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - //----read back measurement results----// - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); - tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); - tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); - - tmpReg = (tmpReg & bMaskHWord) >> 16; - tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; - - if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); - ODM_delay_ms(1); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); - ODM_delay_ms(50); - RetryCount++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); - pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; - break; - } - } - - //DPP path B - if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) - { - // DP setting - // LUT by SRAM - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); - ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); - ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); - - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - for(i=0xb60; i<=0xb9c; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); - } - - // PWSF - ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); - ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); - ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); - - for(i=0xbac; i<=0xbbc; i+=4) - { - ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); - } - - // tx_agc boundary - ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - - } - else - { - ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); - ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); - } - } - - //reload BB default value - for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8814A()\n")); -#endif -} - -VOID - phy_DigitalPredistortion_8814A_8814A( -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PADAPTER pAdapter -#else - IN PDM_ODM_T pDM_Odm -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif -#if DISABLE_BB_RF - return; -#endif - - return; - - if(pDM_Odm->RFCalibrateInfo.bDPdone) - return; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_DigitalPredistortion_8814A(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R - phy_DigitalPredistortion_8814A(pAdapter, FALSE); - } -} - - - -//return value TRUE => Main; FALSE => Aux - - BOOLEAN phy_QueryRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#endif -#endif - if(!pAdapter->bHWInitReady) - { - u1Byte u1bTmp; - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; - ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); - ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) // - { - if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return TRUE; - else - return FALSE; - } - else - { - if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x0) || - (ODM_GetBBReg(pDM_Odm, rConfig_ram64x16, BIT31) == 0x0)) - return TRUE; - else - return FALSE; - } -} - - - -//return value TRUE => Main; FALSE => Aux - BOOLEAN PHY_QueryRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return TRUE; -#endif -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - //if(IS_92C_SERIAL( pHalData->VersionID)){ - if(IS_2T2R( pHalData->VersionID)){ - return phy_QueryRFPathSwitch_8814A(pAdapter, TRUE); - } - else -#endif - { - // For 88C 1T1R -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8814A(pAdapter, FALSE); -#else - return phy_QueryRFPathSwitch_8814A(pDM_Odm, FALSE); -#endif - } -} -#endif - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#if !defined(__ECOS) && !defined(CONFIG_COMPAT_WIRELESS) +#include "mp_precomp.h" +#else +#include "../mp_precomp.h" +#endif +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8814A 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +u1Byte +CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ) +{ + s1Byte UpperBound = 10, LowerBound = -5; // 4'b1010 = 10 + s1Byte Final_RF_Index = 0; + BOOLEAN bPositive = FALSE; + u4Byte bitMask = 0; + u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4;// upper bound +2dB, lower bound -9dB + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if(Method == MIX_MODE) //normal Tx power tracking + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("is 8814 MP chip\n")); + bitMask = BIT19; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; + + if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not + bPositive = TRUE; + else + bPositive = FALSE; + + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, bPositive); + + bitMask = BIT18|BIT17|BIT16|BIT15; + Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ + + } + + if(Final_RF_Index > UpperBound) //Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB + { + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, UpperBound); //set RF Reg0x55 per path + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); + + if(Final_OFDM_Swing_Index > TxScalingUpperBound) // bb swing upper bound = +2dB + Final_OFDM_Swing_Index = TxScalingUpperBound; + + return Final_OFDM_Swing_Index; + } + else if(Final_RF_Index < LowerBound) // lower bound = -5dB + { + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*(LowerBound)); //set RF Reg0x55 per path + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound<<1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + + if(Final_OFDM_Swing_Index < TxScalingLowerBound) // bb swing lower bound = -10dB + Final_OFDM_Swing_Index = TxScalingLowerBound; + return Final_OFDM_Swing_Index; + } + else // normal case + { + + if(bPositive == TRUE) + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); //set RF Reg0x55 per path + else + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); //set RF Reg0x55 per path + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2; + return Final_OFDM_Swing_Index; + } + + return FALSE; +} + + +VOID +ODM_TxPwrTrackSetPwr8814A( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); +#endif + u1Byte Final_OFDM_Swing_Index = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_OFDM_Swing_Index = CheckRFGainOffset(pDM_Odm, MIX_MODE, RFPath); + } + else if(Method == TSSI_MODE) + { + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0); + } + else if(Method == BBSWING) // use for mp driver clean power tracking status + { + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + + ODM_SetRFReg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0); + } + + if((Method == MIX_MODE) || (Method == BBSWING)) + { + switch(RFPath) + { + case ODM_RF_PATH_A: + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + break; + + case ODM_RF_PATH_B: + + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + break; + + case ODM_RF_PATH_C: + + ODM_SetBBReg(pDM_Odm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + break; + + case ODM_RF_PATH_D: + + ODM_SetBBReg(pDM_Odm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + break; + + default: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!! \n")); + + break; + } + } + return; +} // ODM_TxPwrTrackSetPwr8814A + +VOID +GetDeltaSwingTable_8814A( + IN PDM_ODM_T pDM_Odm, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u2Byte rate = *(pDM_Odm->pForcedDataRate); + u1Byte channel = *(pDM_Odm->pChannel); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(rate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + } + + return; +} + + +VOID +GetDeltaSwingTable_8814A_PathCD( + IN PDM_ODM_T pDM_Odm, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D + ) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u2Byte rate = *(pDM_Odm->pForcedDataRate); + u1Byte channel = *(pDM_Odm->pChannel); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(rate)) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; + } else { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; + } else { + *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_DEFAULT; + *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_DEFAULT; + } + + return; +} + + +void ConfigureTxpowerTrack_8814A( + IN PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = ODM_CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = ODM_OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; + pConfig->RfPathCount = MAX_PATH_NUM_8814A; + pConfig->ThermalRegAddr = RF_T_METER_8814A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; + pConfig->DoIQK = DoIQK_8814A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; + pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; +} + + + +//1 7. IQK + + + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if 0 //!(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID + _PHY_SaveADDARegisters_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for( i = 0 ; i < RegisterNum ; i++){ + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); + } +} + + +VOID + _PHY_SaveMACRegisters_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + } + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID + _PHY_ReloadADDARegisters_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for(i = 0 ; i < RegiesterNum; i++) + { + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); + } +} + +VOID + _PHY_ReloadMACRegisters_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + } + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + + +VOID + _PHY_MACSettingCalibration_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3))); + } + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5))); + +} + +#if 0 +#define BW_20M 0 +#define BW_40M 1 +#define BW_80M 2 +#endif + +VOID + phy_LCCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ + u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0; + u4Byte cnt; + + //Check continuous TX and Packet TX + u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; + + // Backup RF reg18. + + if((reg0x914 & 0x70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812, 0xFF); + + //3 3. Read RF reg18 + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + //3 4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000, 0x1); + + ODM_delay_ms(100); + + for (cnt = 0; cnt < 100; cnt++) { + if(ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); + + + //3 Restore original situation + if((reg0x914 & 70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812, 0x00); + + // Recover channel number + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID + phy_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a + // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if defined(MP_DRIVER) && (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8814A() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + + // Temporarily do not allow normal driver to do the following settings because these offset + // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal + // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the + // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if !defined(MP_DRIVER) || (MP_DRIVER != 1) + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters_8814A(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters_8814A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters_8814A(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters_8814A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration_8814A(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration_8814A(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if(path == RF_PATH_A) //Path B to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + else //Path A to standby mode + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, (int)delta_V, (int)delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do + { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + if(path == RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8814A() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters_8814A(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters_8814A(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters_8814A(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters_8814A(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); + if(path == RF_PATH_B) + { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8814A()\n")); +} + + + + + + +VOID +PHY_LCCalibrate_8814A( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); + phy_LCCalibrate_8814A(pDM_Odm, TRUE); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); +} + +VOID + PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#ifdef DISABLE_BB_RF + return; +#endif + + return; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + { + return; + } +#endif + +#if defined(FOR_BRAZIL_PRETEST) && (FOR_BRAZIL_PRETEST != 1) + if(pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8814A(pAdapter, delta, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8814A(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8814A(pDM_Odm, delta, FALSE); +#endif + } +} + VOID phy_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if(!pAdapter->bHWInitReady) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pAdapter->hw_init_completed == _FALSE) +#endif + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + +#endif + + if(is2T) //92C + { + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + } + else //88C + { + + if(bMain) + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main + else + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux + } +} + VOID PHY_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#ifdef DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_92C_SERIAL(pHalData->VersionID)) + { + phy_SetRFPathSwitch_8814A(pAdapter, bMain, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8814A(pAdapter, bMain, FALSE); +#else + phy_SetRFPathSwitch_8814A(pDM_Odm, bMain, FALSE); +#endif + } +} + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID + phy_DigitalPredistortion_8814A( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T + ) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE}; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0}; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A}; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + {0x1e1e1e1e, 0x03901e1e}, + {0x18181818, 0x03901818}, + {0x0e0e0e0e, 0x03900e0e} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8814A()\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8814A for %s %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for(index=0; index tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for(index = 0; index < 3; index++) + ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434); + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a ); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if(pDM_Odm->RFCalibrateInfo.bDPPathAOK) + { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + + for(i=rPdp_AntA; i<=0xb3c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for(i=0xb4c; i<=0xb5c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if(is2T) + { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + //do inner loopback DPK 3 times + for(i = 0; i < 3; i++) + { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for(index = 0; index < 4; index++) + ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434); + for(index = 0; index < 2; index++) + ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if(pDM_Odm->RFCalibrateInfo.bDPPathBOK) + { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); + for(i=0xb60; i<=0xb9c; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for(i=0xbac; i<=0xbbc; i+=4) + { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + } + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); + + } + else + { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for(index=0; indexRFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8814A()\n")); +#endif +} + +VOID + phy_DigitalPredistortion_8814A_8814A( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if(pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_DigitalPredistortion_8814A(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion_8814A(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + + BOOLEAN phy_QueryRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + if(!pAdapter->bHWInitReady) + { + u1Byte u1bTmp; + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; + ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); + //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); + } + + if(is2T) // + { + if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) + return TRUE; + else + return FALSE; + } + else + { + if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x0) || + (ODM_GetBBReg(pDM_Odm, rConfig_ram64x16, BIT31) == 0x0)) + return TRUE; + else + return FALSE; + } +} + + + +//return value TRUE => Main; FALSE => Aux + BOOLEAN PHY_QueryRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + //if(IS_92C_SERIAL( pHalData->VersionID)){ + if(IS_2T2R( pHalData->VersionID)){ + return phy_QueryRFPathSwitch_8814A(pAdapter, TRUE); + } + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8814A(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8814A(pDM_Odm, FALSE); +#endif + } +} +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.h index 1422aadd184..46eaa801e14 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ap.h @@ -1,164 +1,164 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8814A_H__ -#define __HAL_PHY_RF_8814A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8814A 10 //ms -#define index_mapping_NUM_8814A 15 -#define AVG_THERMAL_NUM_8814A 4 -#define RF_T_METER_8814A 0x42 -#define MAX_PATH_NUM_8814A 4 - -#include "../halphyrf_ap.h" - - -void ConfigureTxpowerTrack_8814A( - PTXPWRTRACK_CFG pConfig - ); - -VOID -GetDeltaSwingTable_8814A( - IN PDM_ODM_T pDM_Odm, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ); - -VOID -GetDeltaSwingTable_8814A_PathCD( - IN PDM_ODM_T pDM_Odm, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D - ); - -VOID -ConfigureTxpowerTrack_8814A( - IN PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_TxPwrTrackSetPwr8814A( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u1Byte ChannelMappedIndex - ); - - -u1Byte -CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8814A( - IN PDM_ODM_T pDM_Odm -); - -void -phy_LCCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN is2T -); - - -// -// AP calibrate -// -void -PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta); -void -PHY_DigitalPredistortion_8814A( IN PADAPTER pAdapter); - - -#if 0 //FOR_8814_IQK -VOID -_PHY_SaveADDARegisters( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN pu4Byte ADDABackup, - IN u4Byte RegisterNum - ); - -VOID -_PHY_PathADDAOn( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte ADDAReg, - IN BOOLEAN isPathAOn, - IN BOOLEAN is2T - ); - -VOID -_PHY_MACSettingCalibration( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN pu4Byte MACReg, - IN pu4Byte MACBackup - ); - - - -VOID -_PHY_PathAStandBy( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER pAdapter -#endif - ); - -#endif - - -#endif // #ifndef __HAL_PHY_RF_8814A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8814A_H__ +#define __HAL_PHY_RF_8814A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8814A 10 //ms +#define index_mapping_NUM_8814A 15 +#define AVG_THERMAL_NUM_8814A 4 +#define RF_T_METER_8814A 0x42 +#define MAX_PATH_NUM_8814A 4 + +#include "../halphyrf_ap.h" + + +void ConfigureTxpowerTrack_8814A( + PTXPWRTRACK_CFG pConfig + ); + +VOID +GetDeltaSwingTable_8814A( + IN PDM_ODM_T pDM_Odm, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ); + +VOID +GetDeltaSwingTable_8814A_PathCD( + IN PDM_ODM_T pDM_Odm, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D + ); + +VOID +ConfigureTxpowerTrack_8814A( + IN PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_TxPwrTrackSetPwr8814A( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u1Byte ChannelMappedIndex + ); + + +u1Byte +CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8814A( + IN PDM_ODM_T pDM_Odm +); + +void +phy_LCCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +); + + +// +// AP calibrate +// +void +PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8814A( IN PADAPTER pAdapter); + + +#if 0 //FOR_8814_IQK +VOID +_PHY_SaveADDARegisters( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + +#endif + + +#endif // #ifndef __HAL_PHY_RF_8814A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.c index acec6a70285..7ece1558666 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.c @@ -1,1680 +1,1680 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_8814A 6 - -/*---------------------------Define Local Constant---------------------------*/ - -/*3============================================================*/ -//3 Tx Power Tracking -/*3============================================================*/ -#define rA_TXAGC 0xC94 -#define rB_TXAGC 0xE94 -#define rC_TXAGC 0x1894 -#define rD_TXAGC 0x1A94 -#define TXAGC_BITMASK (BIT29 | BIT28 | BIT27 | BIT26 | BIT25) -#define rA_BBSWING 0xC1C -#define rB_BBSWING 0xE1C -#define rC_BBSWING 0x181C -#define rD_BBSWING 0x1A1C -#define BBSWING_BITMASK 0xFFE00000 - - -#if 0 - -u1Byte CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - s1Byte UpperBound = 10, LowerBound = -5; /*4'b1010 = 10*/ - s1Byte Final_RF_Index = 0; - BOOLEAN bPositive = FALSE; - u4Byte bitMask = 0; - u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4; /*upper bound +2dB, lower bound -10dB*/ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (Method == MIX_MODE) { /*normal Tx power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("is 8814 MP chip\n")); - bitMask = BIT19; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) /*check if RF_Index is positive or not*/ - bPositive = TRUE; - else - bPositive = FALSE; - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, bPositive); - - bitMask = BIT18 | BIT17 | BIT16 | BIT15; - Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ - - } - - if (Final_RF_Index > UpperBound) { /*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, UpperBound); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); - - if (Final_OFDM_Swing_Index > TxScalingUpperBound) /*bb swing upper bound = +2dB*/ - Final_OFDM_Swing_Index = TxScalingUpperBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path-%d Compensate with TXBB = %d\n", RFPath, UpperBound)); - - return Final_OFDM_Swing_Index; - } else if (Final_RF_Index < LowerBound) { /*lower bound = -5dB*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1) * (LowerBound)); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound << 1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - - if (Final_OFDM_Swing_Index < TxScalingLowerBound) /*bb swing lower bound = -10dB*/ - Final_OFDM_Swing_Index = TxScalingLowerBound; - - return Final_OFDM_Swing_Index; - - } else { /*normal case*/ - - if (bPositive == TRUE) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); /*set RF Reg0x55 per path*/ - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) % 2; - return Final_OFDM_Swing_Index; - } - - return FALSE; -} - -#endif - -u1Byte GetTSSIVALUE( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - s1Byte PowerByRateValue = 0; - u1Byte Tx_num, TSSIValue = 0; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxRate = 0xFF; - u1Byte TxLimit = 0; - u1Byte RegPwrTblSel = 0; - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - RegPwrTblSel = pMgntInfo->RegPwrTblSel; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - RegPwrTblSel = Adapter->registrypriv.RegPwrTblSel; -#endif -#endif - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - Tx_num = MgntQuery_NssTxRate(TxRate); - - - if (Channel >= 1 && Channel <= 14) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_2_4G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_2_4G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - if (IS_CCK_RATE(TxRate)) { - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA[PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB[PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC[PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD[PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!\n", __func__)); - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GA[PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GB[PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GC[PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GD[PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } - } else if (Channel >= 36 && Channel <= 64) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[0][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } else if (Channel >= 100 && Channel <= 144) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[1][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } else if (Channel >= 149 && Channel <= 173) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[2][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s Index=%d TSSIValue=%d\n", __func__, PowerByRateValue, TSSIValue)); - -#endif /*CONFIG_PHYDM_POWERTRACK_BY_TSSI*/ - - return TSSIValue; -} - -BOOLEAN GetTSSIModeTxAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u4Byte OffsetVaule, - IN u1Byte TxPowerIndexOffest -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - u1Byte TX_AGC_Index = (u1Byte) pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - u1Byte TX_BBSwing_Index = (u1Byte) pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]; - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (TX_AGC_Index == 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - OffsetVaule = OffsetVaule & 0X1F; - - if (OffsetVaule > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule > 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } else { - TX_AGC_Index = (u1Byte) OffsetVaule; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule <= 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - - } else if (TX_AGC_Index > 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - if (OffsetVaule > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else - TX_AGC_Index = (u1Byte) OffsetVaule; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index > 0 TX_BBSwing_Index(18) +++ OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index > 0 TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - - - } else if (TX_AGC_Index > 0 && TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - - if (TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { - TX_AGC_Index = TxPowerIndexOffest - (pRFCalibrateInfo->DefaultOfdmIndex - TX_BBSwing_Index); - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index>0 TX_BBSwing_Index>18 --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d OffsetVaule=%d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index, OffsetVaule - TxPowerIndexOffest)); - - } else if (TX_AGC_Index == 0 && TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 1) { - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - } else { - OffsetVaule = (OffsetVaule & 0x1F); - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule; - - if (TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { - TX_AGC_Index = TX_BBSwing_Index - pRFCalibrateInfo->DefaultOfdmIndex; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - if (TX_AGC_Index > TxPowerIndexOffest) { - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (u1Byte) (TX_AGC_Index) - TxPowerIndexOffest; - TX_AGC_Index = TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } - } - } - - if (TX_BBSwing_Index <= BBSwingLowerBound) { - TX_BBSwing_Index = BBSwingLowerBound; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s Path_%d BBSwing Lower Bound\n", __func__, RFPath)); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index < 18 OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - - } - - if ((TX_AGC_Index == pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) && (TX_BBSwing_Index == pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])) - return FALSE; - - else { - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - return TRUE; - } - -} - - -VOID SetTxAGCBBSWingOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - u1Byte TxRate = 0xFF; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u4Byte TxPath = pHalData->AntennaTxPath; - - u1Byte TSSIValue = 0; - u1Byte TxPowerIndex = 0; - u1Byte TxPowerIndexOffest = 0; - u4Byte OffsetVaule = 0; - u4Byte TSSIFunction = 0; - u4Byte TXBBSwing = 0; - u1Byte TX_BBSwing_Index = 0; - u4Byte TX_AGC_Index = 0; - u4Byte WaitTXAGCOffsetTimer = 0; - u1Byte i = 0; - BOOLEAN rtn = FALSE; - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (Method == TSSI_MODE) { - switch (RFPath) { - case ODM_RF_PATH_A: - /*Disable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); - /*Enable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0xC8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); - /*Enable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30) != 1) && ((TxPath & 8) == 8)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XD2C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); - /*Disable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathA TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XD2C)=0X%X TXAGC(rA_TXAGC)=0X%X 0XC1C(PathC BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - case ODM_RF_PATH_B: - /*Disable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); - /*Enable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0xE8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); - /*Enable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30) != 1) && ((TxPath & 4) == 4)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XD6C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); - /*Disable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathB TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XD6C)=0X%X TXAGC(rB_TXAGC)=0X%X 0XE1C(PathB BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - case ODM_RF_PATH_C: - /*Disable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); - /*Enable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0x188C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0x188C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); - /*Enable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30) != 1) && ((TxPath & 2) == 2)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XDAC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); - /*Disable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathC TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XDAC)=0X%X TXAGC(rC_TXAGC)=0X%X 0X181C(PathC BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - - case ODM_RF_PATH_D: - /*Disable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); - /*Enable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0x1A8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); - /*Enable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 1); - - /* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30) != 1) && ((TxPath & 1) == 1)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XDEC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); - /*Disable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathD TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XDEC)=0X%X TXAGC(rD_TXAGC)=0X%X 0X1A1C(PathD BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - - break; - } - } - -} - -BOOLEAN GetMixModeTXAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u1Byte TxPowerIndexOffest -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - - s1Byte TX_AGC_Index = 0; - u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { - TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else { - TX_AGC_Index = 0; - - if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index < BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); - - return TRUE; -} - -VOID PowerTrackingByMixMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte TxRate = 0xFF; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxPowerIndexOffest = 0; - u1Byte TxPowerIndex = 0; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking MIX MODE**********\n", RFPath)); - - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - TxPowerIndexOffest = 63 - TxPowerIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d TxPowerIndex=%d\n", RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndex)); - - switch (RFPath) { - case ODM_RF_PATH_A: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_B: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_C: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_D: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - break; - } - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Power Index is the same, EEPROMThermalMeter = 0XFF or TxPowerTrackControl is Disable !!!!\n")); -} - -VOID PowerTrackingByTSSIMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking TSSI_MODE**********\n", RFPath)); - - SetTxAGCBBSWingOffset(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d End POWER Tracking TSSI_MODE**********\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n")); -} - - - -VOID ODM_TxPwrTrackSetPwr8814A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Channel = pHalData->CurrentChannel; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - -/*K-Free*/ -#if 0 - s1Byte TXBBIndex = 0; - s1Byte TXBBUpperBound = 10, TXBBLowerBound = -5; - - TXBBIndex = pRFCalibrateInfo->KfreeOffset[RFPath] / 2; - - if (TXBBIndex > TXBBUpperBound) - TXBBIndex = TXBBUpperBound; - else if (TXBBIndex < TXBBLowerBound) - TXBBIndex = TXBBLowerBound; - - if (TXBBIndex >= 0) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 1); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), TXBBIndex); /*set RF Reg0x55 per path*/ - } else { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 0); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), (-1)*TXBBIndex); - } - -#endif - - if (Method == TXAGC) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking No TXAGC MODE**********\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])); - } else if (Method == TSSI_MODE) { - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == BBSWING) { /*use for mp driver clean power tracking status*/ - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_C: - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_D: - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("RFPath=%d Clear 8814 Power tracking TXAGC=%d BBSwing=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - } else if (Method == MIX_MODE) { - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == MIX_2G_TSSI_5G_MODE) { - if (Channel <= 14) - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - else - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == MIX_5G_TSSI_2G_MODE) { - if (Channel <= 14) - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - else - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } -} /*ODM_TxPwrTrackSetPwr8814A*/ - - -VOID GetDeltaSwingTable_8814A( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - -VOID GetDeltaSwingTable_8814A_PathCD( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; - } else { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; - } else { - *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -void ConfigureTxpowerTrack_8814A( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; - pConfig->RfPathCount = MAX_PATH_NUM_8814A; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; - pConfig->DoIQK = DoIQK_8814A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; - pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; -} - -VOID -phy_LCCalibrate_8814A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T - ) -{ - u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0, cnt; - - //Check continuous TX and Packet TX - u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; - - // Backup RF reg18. - - if((reg0x914 & 0x70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); - - //3 3. Read RF reg18 - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - //3 4. Set LC calibration begin bit15 - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x1b126); - - ODM_delay_ms(100); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - ODM_delay_ms(10); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); - - ODM_SetRFReg( pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13126); - ODM_SetRFReg( pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13124); - //3 Restore original situation - if((reg0x914 & 70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); - - // Recover channel number - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - DbgPrint("Call %s\n", __FUNCTION__); -} - - -VOID -phy_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ -} - - -VOID -PHY_LCCalibrate_8814A( - IN PVOID pDM_VOID - ) -{ - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); - -//#if (MP_DRIVER == 1) - phy_LCCalibrate_8814A(pDM_Odm, TRUE); -//#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); - -} - -VOID -PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ) -{ - -} - - -VOID -PHY_DPCalibrate_8814A( - IN PDM_ODM_T pDM_Odm - ) -{ -} - - -BOOLEAN -phy_QueryRFPathSwitch_8814A( - IN PADAPTER pAdapter - ) -{ - return TRUE; -} - - -BOOLEAN PHY_QueryRFPathSwitch_8814A( - IN PADAPTER pAdapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return TRUE; -#endif - - return phy_QueryRFPathSwitch_8814A(pAdapter); -} - - -VOID phy_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ -} -VOID PHY_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -} - - - - -#endif /* (RTL8814A_SUPPORT == 0)*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_8814A 6 + +/*---------------------------Define Local Constant---------------------------*/ + +/*3============================================================*/ +//3 Tx Power Tracking +/*3============================================================*/ +#define rA_TXAGC 0xC94 +#define rB_TXAGC 0xE94 +#define rC_TXAGC 0x1894 +#define rD_TXAGC 0x1A94 +#define TXAGC_BITMASK (BIT29 | BIT28 | BIT27 | BIT26 | BIT25) +#define rA_BBSWING 0xC1C +#define rB_BBSWING 0xE1C +#define rC_BBSWING 0x181C +#define rD_BBSWING 0x1A1C +#define BBSWING_BITMASK 0xFFE00000 + + +#if 0 + +u1Byte CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + s1Byte UpperBound = 10, LowerBound = -5; /*4'b1010 = 10*/ + s1Byte Final_RF_Index = 0; + BOOLEAN bPositive = FALSE; + u4Byte bitMask = 0; + u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4; /*upper bound +2dB, lower bound -10dB*/ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (Method == MIX_MODE) { /*normal Tx power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("is 8814 MP chip\n")); + bitMask = BIT19; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; + + if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) /*check if RF_Index is positive or not*/ + bPositive = TRUE; + else + bPositive = FALSE; + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, bPositive); + + bitMask = BIT18 | BIT17 | BIT16 | BIT15; + Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ + + } + + if (Final_RF_Index > UpperBound) { /*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, UpperBound); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); + + if (Final_OFDM_Swing_Index > TxScalingUpperBound) /*bb swing upper bound = +2dB*/ + Final_OFDM_Swing_Index = TxScalingUpperBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path-%d Compensate with TXBB = %d\n", RFPath, UpperBound)); + + return Final_OFDM_Swing_Index; + } else if (Final_RF_Index < LowerBound) { /*lower bound = -5dB*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1) * (LowerBound)); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound << 1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + + if (Final_OFDM_Swing_Index < TxScalingLowerBound) /*bb swing lower bound = -10dB*/ + Final_OFDM_Swing_Index = TxScalingLowerBound; + + return Final_OFDM_Swing_Index; + + } else { /*normal case*/ + + if (bPositive == TRUE) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); /*set RF Reg0x55 per path*/ + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) % 2; + return Final_OFDM_Swing_Index; + } + + return FALSE; +} + +#endif + +u1Byte GetTSSIVALUE( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + s1Byte PowerByRateValue = 0; + u1Byte Tx_num, TSSIValue = 0; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u1Byte TxRate = 0xFF; + u1Byte TxLimit = 0; + u1Byte RegPwrTblSel = 0; + +#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + RegPwrTblSel = pMgntInfo->RegPwrTblSel; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + RegPwrTblSel = Adapter->registrypriv.RegPwrTblSel; +#endif +#endif + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + Tx_num = MgntQuery_NssTxRate(TxRate); + + + if (Channel >= 1 && Channel <= 14) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_2_4G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_2_4G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + if (IS_CCK_RATE(TxRate)) { + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA[PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB[PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC[PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD[PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!\n", __func__)); + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GA[PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GB[PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GC[PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GD[PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } + } else if (Channel >= 36 && Channel <= 64) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[0][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } else if (Channel >= 100 && Channel <= 144) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[1][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } else if (Channel >= 149 && Channel <= 173) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[2][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s Index=%d TSSIValue=%d\n", __func__, PowerByRateValue, TSSIValue)); + +#endif /*CONFIG_PHYDM_POWERTRACK_BY_TSSI*/ + + return TSSIValue; +} + +BOOLEAN GetTSSIModeTxAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u4Byte OffsetVaule, + IN u1Byte TxPowerIndexOffest +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; + u1Byte BBSwingLowerBound = 0; + u1Byte TX_AGC_Index = (u1Byte) pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + u1Byte TX_BBSwing_Index = (u1Byte) pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]; + + if (TxPowerIndexOffest > 0XF) + TxPowerIndexOffest = 0XF; + + if (TX_AGC_Index == 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + OffsetVaule = OffsetVaule & 0X1F; + + if (OffsetVaule > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule > 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } else { + TX_AGC_Index = (u1Byte) OffsetVaule; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule <= 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + + } else if (TX_AGC_Index > 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + if (OffsetVaule > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } else + TX_AGC_Index = (u1Byte) OffsetVaule; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index > 0 TX_BBSwing_Index(18) +++ OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index > 0 TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + + + } else if (TX_AGC_Index > 0 && TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + + if (TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { + TX_AGC_Index = TxPowerIndexOffest - (pRFCalibrateInfo->DefaultOfdmIndex - TX_BBSwing_Index); + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + } + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index>0 TX_BBSwing_Index>18 --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d OffsetVaule=%d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index, OffsetVaule - TxPowerIndexOffest)); + + } else if (TX_AGC_Index == 0 && TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 1) { + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + } else { + OffsetVaule = (OffsetVaule & 0x1F); + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule; + + if (TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { + TX_AGC_Index = TX_BBSwing_Index - pRFCalibrateInfo->DefaultOfdmIndex; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + if (TX_AGC_Index > TxPowerIndexOffest) { + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (u1Byte) (TX_AGC_Index) - TxPowerIndexOffest; + TX_AGC_Index = TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } + } + } + + if (TX_BBSwing_Index <= BBSwingLowerBound) { + TX_BBSwing_Index = BBSwingLowerBound; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s Path_%d BBSwing Lower Bound\n", __func__, RFPath)); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index < 18 OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + + } + + if ((TX_AGC_Index == pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) && (TX_BBSwing_Index == pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])) + return FALSE; + + else { + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; + return TRUE; + } + +} + + +VOID SetTxAGCBBSWingOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + u1Byte TxRate = 0xFF; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u4Byte TxPath = pHalData->AntennaTxPath; + + u1Byte TSSIValue = 0; + u1Byte TxPowerIndex = 0; + u1Byte TxPowerIndexOffest = 0; + u4Byte OffsetVaule = 0; + u4Byte TSSIFunction = 0; + u4Byte TXBBSwing = 0; + u1Byte TX_BBSwing_Index = 0; + u4Byte TX_AGC_Index = 0; + u4Byte WaitTXAGCOffsetTimer = 0; + u1Byte i = 0; + BOOLEAN rtn = FALSE; + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (Method == TSSI_MODE) { + switch (RFPath) { + case ODM_RF_PATH_A: + /*Disable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); + /*Enable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0xC8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); + /*Enable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30) != 1) && ((TxPath & 8) == 8)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XD2C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); + /*Disable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathA TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XD2C)=0X%X TXAGC(rA_TXAGC)=0X%X 0XC1C(PathC BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + case ODM_RF_PATH_B: + /*Disable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); + /*Enable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0xE8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); + /*Enable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30) != 1) && ((TxPath & 4) == 4)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XD6C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); + /*Disable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathB TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XD6C)=0X%X TXAGC(rB_TXAGC)=0X%X 0XE1C(PathB BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + case ODM_RF_PATH_C: + /*Disable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); + /*Enable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0x188C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0x188C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); + /*Enable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30) != 1) && ((TxPath & 2) == 2)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XDAC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); + /*Disable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathC TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XDAC)=0X%X TXAGC(rC_TXAGC)=0X%X 0X181C(PathC BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + + case ODM_RF_PATH_D: + /*Disable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); + /*Enable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0x1A8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); + /*Enable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 1); + + /* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30) != 1) && ((TxPath & 1) == 1)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XDEC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); + /*Disable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathD TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XDEC)=0X%X TXAGC(rD_TXAGC)=0X%X 0X1A1C(PathD BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + + break; + } + } + +} + +BOOLEAN GetMixModeTXAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u1Byte TxPowerIndexOffest +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; + u1Byte BBSwingLowerBound = 0; + + s1Byte TX_AGC_Index = 0; + u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); + + if (TxPowerIndexOffest > 0XF) + TxPowerIndexOffest = 0XF; + + if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { + TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } else { + TX_AGC_Index = 0; + + if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index < BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); + + return TRUE; +} + +VOID PowerTrackingByMixMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte TxRate = 0xFF; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u1Byte TxPowerIndexOffest = 0; + u1Byte TxPowerIndex = 0; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking MIX MODE**********\n", RFPath)); + + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + TxPowerIndexOffest = 63 - TxPowerIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d TxPowerIndex=%d\n", RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndex)); + + switch (RFPath) { + case ODM_RF_PATH_A: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_B: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_C: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_D: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + break; + } + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Power Index is the same, EEPROMThermalMeter = 0XFF or TxPowerTrackControl is Disable !!!!\n")); +} + +VOID PowerTrackingByTSSIMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking TSSI_MODE**********\n", RFPath)); + + SetTxAGCBBSWingOffset(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d End POWER Tracking TSSI_MODE**********\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n")); +} + + + +VOID ODM_TxPwrTrackSetPwr8814A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Channel = pHalData->CurrentChannel; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + +/*K-Free*/ +#if 0 + s1Byte TXBBIndex = 0; + s1Byte TXBBUpperBound = 10, TXBBLowerBound = -5; + + TXBBIndex = pRFCalibrateInfo->KfreeOffset[RFPath] / 2; + + if (TXBBIndex > TXBBUpperBound) + TXBBIndex = TXBBUpperBound; + else if (TXBBIndex < TXBBLowerBound) + TXBBIndex = TXBBLowerBound; + + if (TXBBIndex >= 0) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 1); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), TXBBIndex); /*set RF Reg0x55 per path*/ + } else { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 0); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), (-1)*TXBBIndex); + } + +#endif + + if (Method == TXAGC) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking No TXAGC MODE**********\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])); + } else if (Method == TSSI_MODE) { + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == BBSWING) { /*use for mp driver clean power tracking status*/ + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_C: + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_D: + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("RFPath=%d Clear 8814 Power tracking TXAGC=%d BBSwing=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + } else if (Method == MIX_MODE) { + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == MIX_2G_TSSI_5G_MODE) { + if (Channel <= 14) + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + else + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == MIX_5G_TSSI_2G_MODE) { + if (Channel <= 14) + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + else + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } +} /*ODM_TxPwrTrackSetPwr8814A*/ + + +VOID GetDeltaSwingTable_8814A( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + +VOID GetDeltaSwingTable_8814A_PathCD( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; + } else { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; + } else { + *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +void ConfigureTxpowerTrack_8814A( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; + pConfig->RfPathCount = MAX_PATH_NUM_8814A; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; + pConfig->DoIQK = DoIQK_8814A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; + pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; +} + +VOID +phy_LCCalibrate_8814A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T + ) +{ + u4Byte /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0, cnt; + + //Check continuous TX and Packet TX + u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; + + // Backup RF reg18. + + if((reg0x914 & 0x70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); + + //3 3. Read RF reg18 + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + //3 4. Set LC calibration begin bit15 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x1b126); + + ODM_delay_ms(100); + + for (cnt = 0; cnt < 100; cnt++) { + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); + + ODM_SetRFReg( pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13126); + ODM_SetRFReg( pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13124); + //3 Restore original situation + if((reg0x914 & 70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + + // Recover channel number + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + DbgPrint("Call %s\n", __FUNCTION__); +} + + +VOID +phy_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ +} + + +VOID +PHY_LCCalibrate_8814A( + IN PVOID pDM_VOID + ) +{ + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); + +//#if (MP_DRIVER == 1) + phy_LCCalibrate_8814A(pDM_Odm, TRUE); +//#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); + +} + +VOID +PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ) +{ + +} + + +VOID +PHY_DPCalibrate_8814A( + IN PDM_ODM_T pDM_Odm + ) +{ +} + + +BOOLEAN +phy_QueryRFPathSwitch_8814A( + IN PADAPTER pAdapter + ) +{ + return TRUE; +} + + +BOOLEAN PHY_QueryRFPathSwitch_8814A( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif + + return phy_QueryRFPathSwitch_8814A(pAdapter); +} + + +VOID phy_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T + ) +{ +} +VOID PHY_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +} + + + + +#endif /* (RTL8814A_SUPPORT == 0)*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.h index a362a3cc1bc..8b8cb7d8b23 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_ce.h @@ -1,152 +1,152 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8814A_H__ -#define __HAL_PHY_RF_8814A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define AVG_THERMAL_NUM_8814A 4 -#define RF_T_METER_8814A 0x42 - -#include "../halphyrf_ce.h" - -void ConfigureTxpowerTrack_8814A( - PTXPWRTRACK_CFG pConfig - ); - -VOID GetDeltaSwingTable_8814A( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B - ); - - -VOID -GetDeltaSwingTable_8814A_PathCD( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D - ); - -VOID -ODM_TxPwrTrackSetPwr8814A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -#if 0 -u1Byte -CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); -#endif - -u1Byte -GetTSSIVALUE( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath - ); - -BOOLEAN -GetTSSIModeTxAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u4Byte OffsetVaule, - IN u1Byte TxPowerIndexOffest - ); - -BOOLEAN -GetMixModeTXAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u1Byte TxPowerIndexOffest - ); - -VOID -PowerTrackingByMixMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); - -VOID -PowerTrackingByTSSIMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); - -VOID -PHY_IQCalibrate_8814A( - IN PVOID pDM_VOID, - IN BOOLEAN bReCovery - ); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8814A( - IN PVOID pDM_VOID - ); - -// -// AP calibrate -// -void -PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ); - - -VOID -PHY_DPCalibrate_8814A( - IN PDM_ODM_T pDM_Odm - ); - - -VOID PHY_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8814A_H__ +#define __HAL_PHY_RF_8814A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define AVG_THERMAL_NUM_8814A 4 +#define RF_T_METER_8814A 0x42 + +#include "../halphyrf_ce.h" + +void ConfigureTxpowerTrack_8814A( + PTXPWRTRACK_CFG pConfig + ); + +VOID GetDeltaSwingTable_8814A( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B + ); + + +VOID +GetDeltaSwingTable_8814A_PathCD( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D + ); + +VOID +ODM_TxPwrTrackSetPwr8814A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +#if 0 +u1Byte +CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); +#endif + +u1Byte +GetTSSIVALUE( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath + ); + +BOOLEAN +GetTSSIModeTxAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u4Byte OffsetVaule, + IN u1Byte TxPowerIndexOffest + ); + +BOOLEAN +GetMixModeTXAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u1Byte TxPowerIndexOffest + ); + +VOID +PowerTrackingByMixMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); + +VOID +PowerTrackingByTSSIMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); + +VOID +PHY_IQCalibrate_8814A( + IN PVOID pDM_VOID, + IN BOOLEAN bReCovery + ); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8814A( + IN PVOID pDM_VOID + ); + +// +// AP calibrate +// +void +PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ); + + +VOID +PHY_DPCalibrate_8814A( + IN PDM_ODM_T pDM_Odm + ); + + +VOID PHY_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.c b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.c index 75302909c28..7ccab6acc3e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.c @@ -1,1670 +1,1670 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX_8814A 6 - -/*---------------------------Define Local Constant---------------------------*/ - -/*3============================================================*/ -//3 Tx Power Tracking -/*3============================================================*/ -#define rA_TXAGC 0xC94 -#define rB_TXAGC 0xE94 -#define rC_TXAGC 0x1894 -#define rD_TXAGC 0x1A94 -#define TXAGC_BITMASK (BIT29 | BIT28 | BIT27 | BIT26 | BIT25) -#define rA_BBSWING 0xC1C -#define rB_BBSWING 0xE1C -#define rC_BBSWING 0x181C -#define rD_BBSWING 0x1A1C -#define BBSWING_BITMASK 0xFFE00000 - - -#if 0 - -u1Byte CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - s1Byte UpperBound = 10, LowerBound = -5; /*4'b1010 = 10*/ - s1Byte Final_RF_Index = 0; - BOOLEAN bPositive = FALSE; - u4Byte bitMask = 0; - u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4; /*upper bound +2dB, lower bound -10dB*/ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (Method == MIX_MODE) { /*normal Tx power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("is 8814 MP chip\n")); - bitMask = BIT19; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) /*check if RF_Index is positive or not*/ - bPositive = TRUE; - else - bPositive = FALSE; - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, bPositive); - - bitMask = BIT18 | BIT17 | BIT16 | BIT15; - Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ - - } - - if (Final_RF_Index > UpperBound) { /*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, UpperBound); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); - - if (Final_OFDM_Swing_Index > TxScalingUpperBound) /*bb swing upper bound = +2dB*/ - Final_OFDM_Swing_Index = TxScalingUpperBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Path-%d Compensate with TXBB = %d\n", RFPath, UpperBound)); - - return Final_OFDM_Swing_Index; - } else if (Final_RF_Index < LowerBound) { /*lower bound = -5dB*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1) * (LowerBound)); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound << 1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - - if (Final_OFDM_Swing_Index < TxScalingLowerBound) /*bb swing lower bound = -10dB*/ - Final_OFDM_Swing_Index = TxScalingLowerBound; - - return Final_OFDM_Swing_Index; - - } else { /*normal case*/ - - if (bPositive == TRUE) - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); /*set RF Reg0x55 per path*/ - else - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); /*set RF Reg0x55 per path*/ - - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) % 2; - return Final_OFDM_Swing_Index; - } - - return FALSE; -} - -#endif - -u1Byte GetTSSIVALUE( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - s1Byte PowerByRateValue = 0; - u1Byte Tx_num, TSSIValue = 0; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxRate = 0xFF; - u1Byte TxLimit = 0; - u1Byte RegPwrTblSel = 0; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - RegPwrTblSel = pMgntInfo->RegPwrTblSel; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - RegPwrTblSel = Adapter->registrypriv.RegPwrTblSel; -#endif -#endif - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - Tx_num = MgntQuery_NssTxRate(TxRate); - - - if (Channel >= 1 && Channel <= 14) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_2_4G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_2_4G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - if (IS_CCK_RATE(TxRate)) { - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA[PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB[PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC[PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD[PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!\n", __func__)); - break; - } - } else { - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GA[PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GB[PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GC[PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GD[PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } - } else if (Channel >= 36 && Channel <= 64) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[0][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[0][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } else if (Channel >= 100 && Channel <= 144) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[1][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[1][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } else if (Channel >= 149 && Channel <= 173) { - PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); - - TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); - - PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; - - switch (RFPath) { - case ODM_RF_PATH_A: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_B: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_C: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[2][PowerByRateValue]; - break; - - case ODM_RF_PATH_D: - TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[2][PowerByRateValue]; - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call:%s Wrong Path name!!!!\n", __func__)); - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s Index=%d TSSIValue=%d\n", __func__, PowerByRateValue, TSSIValue)); - - return TSSIValue; -} - -BOOLEAN GetTSSIModeTxAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u4Byte OffsetVaule, - IN u1Byte TxPowerIndexOffest -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - u1Byte TX_AGC_Index = (u1Byte) pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - u1Byte TX_BBSwing_Index = (u1Byte) pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]; - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (TX_AGC_Index == 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - OffsetVaule = OffsetVaule & 0X1F; - - if (OffsetVaule > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule > 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } else { - TX_AGC_Index = (u1Byte) OffsetVaule; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule <= 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - - } else if (TX_AGC_Index > 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - if (OffsetVaule > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else - TX_AGC_Index = (u1Byte) OffsetVaule; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index > 0 TX_BBSwing_Index(18) +++ OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index > 0 TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - } - - - } else if (TX_AGC_Index > 0 && TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 0) { - TX_AGC_Index = TxPowerIndexOffest; - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - - if (TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { - TX_AGC_Index = TxPowerIndexOffest - (pRFCalibrateInfo->DefaultOfdmIndex - TX_BBSwing_Index); - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } - } else { - TX_AGC_Index = 0; - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index <= BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index>0 TX_BBSwing_Index>18 --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d OffsetVaule=%d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index, OffsetVaule - TxPowerIndexOffest)); - - } else if (TX_AGC_Index == 0 && TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { - if ((OffsetVaule & 0X20) >> 5 == 1) { - OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; - - if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) - TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; - else - TX_BBSwing_Index = BBSwingLowerBound; - } else { - OffsetVaule = (OffsetVaule & 0x1F); - TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule; - - if (TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { - TX_AGC_Index = TX_BBSwing_Index - pRFCalibrateInfo->DefaultOfdmIndex; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - if (TX_AGC_Index > TxPowerIndexOffest) { - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (u1Byte) (TX_AGC_Index) - TxPowerIndexOffest; - TX_AGC_Index = TxPowerIndexOffest; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } - } - } - - if (TX_BBSwing_Index <= BBSwingLowerBound) { - TX_BBSwing_Index = BBSwingLowerBound; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s Path_%d BBSwing Lower Bound\n", __func__, RFPath)); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TX_AGC_Index(0) TX_BBSwing_Index < 18 OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); - - } - - if ((TX_AGC_Index == pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) && (TX_BBSwing_Index == pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])) - return FALSE; - - else { - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - return TRUE; - } - -} - - -VOID SetTxAGCBBSWingOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - u1Byte TxRate = 0xFF; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u4Byte TxPath = pHalData->AntennaTxPath; - - u1Byte TSSIValue = 0; - u1Byte TxPowerIndex = 0; - u1Byte TxPowerIndexOffest = 0; - u4Byte OffsetVaule = 0; - u4Byte TSSIFunction = 0; - u4Byte TXBBSwing = 0; - u1Byte TX_BBSwing_Index = 0; - u4Byte TX_AGC_Index = 0; - u4Byte WaitTXAGCOffsetTimer = 0; - u1Byte i = 0; - BOOLEAN rtn = FALSE; - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (Method == TSSI_MODE) { - switch (RFPath) { - case ODM_RF_PATH_A: - /*Disable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); - /*Enable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0xC8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); - /*Enable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30) != 1) && ((TxPath & 8) == 8)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XD2C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); - /*Disable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathA TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XD2C)=0X%X TXAGC(rA_TXAGC)=0X%X 0XC1C(PathC BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - case ODM_RF_PATH_B: - /*Disable Path A TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); - /*Enable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0xE8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); - /*Enable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30) != 1) && ((TxPath & 4) == 4)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XD6C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); - /*Disable Path B TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathB TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XD6C)=0X%X TXAGC(rB_TXAGC)=0X%X 0XE1C(PathB BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - case ODM_RF_PATH_C: - /*Disable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); - /*Enable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0x188C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0x188C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); - /*Enable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 1); - -/* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30) != 1) && ((TxPath & 2) == 2)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XDAC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); - /*Disable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathC TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XDAC)=0X%X TXAGC(rC_TXAGC)=0X%X 0X181C(PathC BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - - case ODM_RF_PATH_D: - /*Disable Path C TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); - /*Enable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); - - /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ - TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); - - /*Write BB 0x1A8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); - - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); - - /*Write BB TXAGC Initial Power Index for EEPROM*/ - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", - __func__, - ODM_GetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), - RFPath, TxRate, BandWidth, Channel, - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) - )); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); - /*Enable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); - /*Enable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 1); - - /* delay_us(500);*/ - WaitTXAGCOffsetTimer = 0; - - while ((ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30) != 1) && ((TxPath & 1) == 1)) { - WaitTXAGCOffsetTimer++; - - if (WaitTXAGCOffsetTimer >= 1000) - break; - } - - /*Read the offset value at BB Reg.*/ - OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); - - TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Call %s 0XDEC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); - - /*Disable BB TSSI Power Tracking*/ - ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); - /*Disable Path D TSSI Circuit*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); - - if (TSSIFunction == 1) { - TXBBSwing = ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK); - - for (i = 0; i <= 36; i++) { - if (TXBBSwing == TxScalingTable_Jaguar[i]) { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" PathD TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); - break; - - } else { - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; - } - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - TxPowerIndexOffest = 63 - TxPowerIndex; - - rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); - - if (rtn == TRUE) { - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" OffsetValue(0XDEC)=0X%X TXAGC(rD_TXAGC)=0X%X 0X1A1C(PathD BBSwing)(%d)=0X%X\n", - ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), - ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], - ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" 0X55[13:9]=0X%X 0X56=0X%X\n", - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), - ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) - )); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" ========================================================\n")); - - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - (" TSSI does not Calculate Finish\n")); - - break; - - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - - break; - } - } - -} - -BOOLEAN GetMixModeTXAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u1Byte TxPowerIndexOffest -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - - s1Byte TX_AGC_Index = 0; - u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { - TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else { - TX_AGC_Index = 0; - - if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index < BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); - - return TRUE; -} - -VOID PowerTrackingByMixMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte TxRate = 0xFF; - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxPowerIndexOffest = 0; - u1Byte TxPowerIndex = 0; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking MIX MODE**********\n", RFPath)); - - TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH)BandWidth, Channel); - TxPowerIndexOffest = 63 - TxPowerIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d TxPowerIndex=%d\n", RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndex)); - - switch (RFPath) { - case ODM_RF_PATH_A: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_B: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_C: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_D: - GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - break; - } - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Power Index is the same, EEPROMThermalMeter = 0XFF or TxPowerTrackControl is Disable !!!!\n")); -} - -VOID PowerTrackingByTSSIMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath -) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking TSSI_MODE**********\n", RFPath)); - - SetTxAGCBBSWingOffset(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d End POWER Tracking TSSI_MODE**********\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n")); -} - - - -VOID ODM_TxPwrTrackSetPwr8814A( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Channel = pHalData->CurrentChannel; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - -/*K-Free*/ -#if 0 - s1Byte TXBBIndex = 0; - s1Byte TXBBUpperBound = 10, TXBBLowerBound = -5; - - TXBBIndex = pRFCalibrateInfo->KfreeOffset[RFPath] / 2; - - if (TXBBIndex > TXBBUpperBound) - TXBBIndex = TXBBUpperBound; - else if (TXBBIndex < TXBBLowerBound) - TXBBIndex = TXBBLowerBound; - - if (TXBBIndex >= 0) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 1); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), TXBBIndex); /*set RF Reg0x55 per path*/ - } else { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 0); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), (-1)*TXBBIndex); - } - -#endif - - if (Method == TXAGC) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("****************Path_%d POWER Tracking No TXAGC MODE**********\n", RFPath)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])); - } else if (Method == TSSI_MODE) { - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == BBSWING) { /*use for mp driver clean power tracking status*/ - switch (RFPath) { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_B: - ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_C: - ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - case ODM_RF_PATH_D: - ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Wrong Path name!!!!\n")); - - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("RFPath=%d Clear 8814 Power tracking TXAGC=%d BBSwing=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); - - } else if (Method == MIX_MODE) { - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == MIX_2G_TSSI_5G_MODE) { - if (Channel <= 14) - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - else - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } else if (Method == MIX_5G_TSSI_2G_MODE) { - if (Channel <= 14) - PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - else - PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); - } -} /*ODM_TxPwrTrackSetPwr8814A*/ - - -VOID GetDeltaSwingTable_8814A( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - - -VOID GetDeltaSwingTable_8814A_PathCD( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); -#endif -#endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); -#endif - } - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - if (1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; - } else { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; - *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; - *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; - *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; - } else { - *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -void ConfigureTxpowerTrack_8814A( - PTXPWRTRACK_CFG pConfig -) -{ - pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; - pConfig->Threshold_IQK = 8; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; - pConfig->RfPathCount = MAX_PATH_NUM_8814A; - pConfig->ThermalRegAddr = RF_T_METER_88E; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; - pConfig->DoIQK = DoIQK_8814A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; - pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; -} - -VOID phy_LCCalibrate_8814A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN is2T -) -{ - u4Byte LC_Cal = 0, cnt; - - /*Check continuous TX and Packet TX*/ - u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; - - /*Backup RF reg18.*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - if ((reg0x914 & 0x70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); - - /*3 3. Read RF reg18*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - /*3 4. Set LC calibration begin bit15*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); - - ODM_delay_ms(100); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - - ODM_delay_ms(10); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); - - - - /*3 Restore original situation*/ - if ((reg0x914 & 70000) == 0) - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00); - - /*Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - - DbgPrint("Call %s\n", __func__); -} - - -VOID phy_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta, - IN BOOLEAN is2T -) -{ -} - - -VOID PHY_LCCalibrate_8814A( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif -#endif -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); - -/*#if (MP_DRIVER == 1)*/ - phy_LCCalibrate_8814A(pDM_Odm, TRUE); -/*#endif*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); - -} - -VOID PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta -) -{ - -} - - -VOID PHY_DPCalibrate_8814A( - IN PDM_ODM_T pDM_Odm -) -{ -} - - -BOOLEAN phy_QueryRFPathSwitch_8814A( - IN PADAPTER pAdapter -) -{ - return TRUE; -} - - -BOOLEAN PHY_QueryRFPathSwitch_8814A( - IN PADAPTER pAdapter -) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - - return phy_QueryRFPathSwitch_8814A(pAdapter); -} - - -VOID phy_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain, - IN BOOLEAN is2T -) -{ -} -VOID PHY_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain -) -{ -} - - - - -#else /*(RTL8814A_SUPPORT == 0)*/ -VOID PHY_LCCalibrate_8814A( - IN PDM_ODM_T pDM_Odm -) {} - -VOID PHY_IQCalibrate_8814A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery -) {} -#endif /* (RTL8814A_SUPPORT == 0)*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX_8814A 6 + +/*---------------------------Define Local Constant---------------------------*/ + +/*3============================================================*/ +//3 Tx Power Tracking +/*3============================================================*/ +#define rA_TXAGC 0xC94 +#define rB_TXAGC 0xE94 +#define rC_TXAGC 0x1894 +#define rD_TXAGC 0x1A94 +#define TXAGC_BITMASK (BIT29 | BIT28 | BIT27 | BIT26 | BIT25) +#define rA_BBSWING 0xC1C +#define rB_BBSWING 0xE1C +#define rC_BBSWING 0x181C +#define rD_BBSWING 0x1A1C +#define BBSWING_BITMASK 0xFFE00000 + + +#if 0 + +u1Byte CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + s1Byte UpperBound = 10, LowerBound = -5; /*4'b1010 = 10*/ + s1Byte Final_RF_Index = 0; + BOOLEAN bPositive = FALSE; + u4Byte bitMask = 0; + u1Byte Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4; /*upper bound +2dB, lower bound -10dB*/ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (Method == MIX_MODE) { /*normal Tx power tracking*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("is 8814 MP chip\n")); + bitMask = BIT19; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] + pRFCalibrateInfo->KfreeOffset[RFPath]; + + if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) /*check if RF_Index is positive or not*/ + bPositive = TRUE; + else + bPositive = FALSE; + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, bPositive); + + bitMask = BIT18 | BIT17 | BIT16 | BIT15; + Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/ + + } + + if (Final_RF_Index > UpperBound) { /*Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, UpperBound); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1)); + + if (Final_OFDM_Swing_Index > TxScalingUpperBound) /*bb swing upper bound = +2dB*/ + Final_OFDM_Swing_Index = TxScalingUpperBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path-%d Compensate with TXBB = %d\n", RFPath, UpperBound)); + + return Final_OFDM_Swing_Index; + } else if (Final_RF_Index < LowerBound) { /*lower bound = -5dB*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1) * (LowerBound)); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex - ((LowerBound << 1) - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + + if (Final_OFDM_Swing_Index < TxScalingLowerBound) /*bb swing lower bound = -10dB*/ + Final_OFDM_Swing_Index = TxScalingLowerBound; + + return Final_OFDM_Swing_Index; + + } else { /*normal case*/ + + if (bPositive == TRUE) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); /*set RF Reg0x55 per path*/ + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); /*set RF Reg0x55 per path*/ + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) % 2; + return Final_OFDM_Swing_Index; + } + + return FALSE; +} + +#endif + +u1Byte GetTSSIVALUE( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + s1Byte PowerByRateValue = 0; + u1Byte Tx_num, TSSIValue = 0; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u1Byte TxRate = 0xFF; + u1Byte TxLimit = 0; + u1Byte RegPwrTblSel = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + RegPwrTblSel = pMgntInfo->RegPwrTblSel; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + RegPwrTblSel = Adapter->registrypriv.RegPwrTblSel; +#endif +#endif + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + Tx_num = MgntQuery_NssTxRate(TxRate); + + + if (Channel >= 1 && Channel <= 14) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_2_4G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_2_4G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + if (IS_CCK_RATE(TxRate)) { + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKA[PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKB[PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKC[PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GCCKD[PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!\n", __func__)); + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GA[PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GB[PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GC[PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_2GD[PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } + } else if (Channel >= 36 && Channel <= 64) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[0][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[0][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } else if (Channel >= 100 && Channel <= 144) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[1][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[1][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } else if (Channel >= 149 && Channel <= 173) { + PowerByRateValue = PHY_GetTxPowerByRateOriginal(Adapter, BAND_ON_5G, (ODM_RF_RADIO_PATH_E) RFPath, Tx_num, TxRate); + + TxLimit = PHY_GetTxPowerLimitOriginal(Adapter, RegPwrTblSel, BAND_ON_5G, (CHANNEL_WIDTH) BandWidth, ODM_RF_PATH_A, TxRate, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s PowerByRateValue=%d TxRate=0x%X RFPath=%d Tx_num=%d\n", __func__, PowerByRateValue, TxRate, RFPath, Tx_num)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxLimit=%d RegPwrTblSel=0x%X BandWidth=%d Channel=%d\n", __func__, TxLimit, RegPwrTblSel, BandWidth, Channel)); + + PowerByRateValue = PowerByRateValue > TxLimit ? TxLimit : PowerByRateValue; + + switch (RFPath) { + case ODM_RF_PATH_A: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GA[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_B: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GB[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_C: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GC[2][PowerByRateValue]; + break; + + case ODM_RF_PATH_D: + TSSIValue = pRFCalibrateInfo->DeltaSwingTSSITable_5GD[2][PowerByRateValue]; + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call:%s Wrong Path name!!!!\n", __func__)); + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s Index=%d TSSIValue=%d\n", __func__, PowerByRateValue, TSSIValue)); + + return TSSIValue; +} + +BOOLEAN GetTSSIModeTxAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u4Byte OffsetVaule, + IN u1Byte TxPowerIndexOffest +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; + u1Byte BBSwingLowerBound = 0; + u1Byte TX_AGC_Index = (u1Byte) pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + u1Byte TX_BBSwing_Index = (u1Byte) pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]; + + if (TxPowerIndexOffest > 0XF) + TxPowerIndexOffest = 0XF; + + if (TX_AGC_Index == 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + OffsetVaule = OffsetVaule & 0X1F; + + if (OffsetVaule > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule > 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } else { + TX_AGC_Index = (u1Byte) OffsetVaule; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) +++ ( OffsetVaule <= 0XF) OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + + } else if (TX_AGC_Index > 0 && TX_BBSwing_Index == pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + if (OffsetVaule > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } else + TX_AGC_Index = (u1Byte) OffsetVaule; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index > 0 TX_BBSwing_Index(18) +++ OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index > 0 TX_BBSwing_Index(18) --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + } + + + } else if (TX_AGC_Index > 0 && TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 0) { + TX_AGC_Index = TxPowerIndexOffest; + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule - TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + + if (TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { + TX_AGC_Index = TxPowerIndexOffest - (pRFCalibrateInfo->DefaultOfdmIndex - TX_BBSwing_Index); + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + } + } else { + TX_AGC_Index = 0; + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index <= BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index>0 TX_BBSwing_Index>18 --- OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d OffsetVaule=%d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index, OffsetVaule - TxPowerIndexOffest)); + + } else if (TX_AGC_Index == 0 && TX_BBSwing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { + if ((OffsetVaule & 0X20) >> 5 == 1) { + OffsetVaule = ((~OffsetVaule) + 1) & 0X1F; + + if (TX_BBSwing_Index >= (u1Byte) OffsetVaule) + TX_BBSwing_Index = TX_BBSwing_Index - (u1Byte) OffsetVaule; + else + TX_BBSwing_Index = BBSwingLowerBound; + } else { + OffsetVaule = (OffsetVaule & 0x1F); + TX_BBSwing_Index = TX_BBSwing_Index + (u1Byte) OffsetVaule; + + if (TX_BBSwing_Index > pRFCalibrateInfo->DefaultOfdmIndex) { + TX_AGC_Index = TX_BBSwing_Index - pRFCalibrateInfo->DefaultOfdmIndex; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + if (TX_AGC_Index > TxPowerIndexOffest) { + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (u1Byte) (TX_AGC_Index) - TxPowerIndexOffest; + TX_AGC_Index = TxPowerIndexOffest; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } + } + } + + if (TX_BBSwing_Index <= BBSwingLowerBound) { + TX_BBSwing_Index = BBSwingLowerBound; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s Path_%d BBSwing Lower Bound\n", __func__, RFPath)); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TX_AGC_Index(0) TX_BBSwing_Index < 18 OffsetVaule = 0X%X TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", OffsetVaule, TX_AGC_Index, TX_BBSwing_Index)); + + } + + if ((TX_AGC_Index == pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]) && (TX_BBSwing_Index == pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])) + return FALSE; + + else { + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; + return TRUE; + } + +} + + +VOID SetTxAGCBBSWingOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + u1Byte TxRate = 0xFF; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u4Byte TxPath = pHalData->AntennaTxPath; + + u1Byte TSSIValue = 0; + u1Byte TxPowerIndex = 0; + u1Byte TxPowerIndexOffest = 0; + u4Byte OffsetVaule = 0; + u4Byte TSSIFunction = 0; + u4Byte TXBBSwing = 0; + u1Byte TX_BBSwing_Index = 0; + u4Byte TX_AGC_Index = 0; + u4Byte WaitTXAGCOffsetTimer = 0; + u1Byte i = 0; + BOOLEAN rtn = FALSE; + + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (Method == TSSI_MODE) { + switch (RFPath) { + case ODM_RF_PATH_A: + /*Disable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); + /*Enable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0xC8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0xC8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); + /*Enable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30) != 1) && ((TxPath & 8) == 8)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD2C, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XD2C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xC8C, BIT7, 0); + /*Disable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathA TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XD2C)=0X%X TXAGC(rA_TXAGC)=0X%X 0XC1C(PathC BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xD2C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + case ODM_RF_PATH_B: + /*Disable Path A TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, BIT10, 0); + /*Enable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0xE8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0xE8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); + /*Enable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30) != 1) && ((TxPath & 4) == 4)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xD6C, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XD6C TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0xE8C, BIT7, 0); + /*Disable Path B TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathB TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XD6C)=0X%X TXAGC(rB_TXAGC)=0X%X 0XE1C(PathB BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xD6C, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + case ODM_RF_PATH_C: + /*Disable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); + /*Enable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0x188C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0x188C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0x188C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); + /*Enable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 1); + +/* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30) != 1) && ((TxPath & 2) == 2)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDAC, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XDAC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x188C, BIT7, 0); + /*Disable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathC TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XDAC)=0X%X TXAGC(rC_TXAGC)=0X%X 0X181C(PathC BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xDAC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + + case ODM_RF_PATH_D: + /*Disable Path C TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x65, BIT10, 0); + /*Enable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); + + /*Read power by rate table to set TSSI value by power and set rf reg 0x65[19:15]*/ + TSSIValue = GetTSSIVALUE(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15, TSSIValue); + + /*Write BB 0x1A8C for Setting Max. packet (30) of tracking power and the initial Value of TXAGC*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT18 | BIT17 | BIT16 | BIT15 | BIT14, 30); + + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8, 0); + + /*Write BB TXAGC Initial Power Index for EEPROM*/ + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH) BandWidth, Channel); + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0, TxPowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s TxPowerIndex=%d RFPath=%d TxRate=%d BandWidth=%d Channel=%d 0x65[19:15]=0X%X 0x65[11:10]=0X%X\n", + __func__, + ODM_GetBBReg(pDM_Odm, 0x1A8C, BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + RFPath, TxRate, BandWidth, Channel, + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT19 | BIT18 | BIT17 | BIT16 | BIT15), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0x65, BIT11 | BIT10) + )); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); + /*Enable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 1); + /*Enable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 1); + + /* delay_us(500);*/ + WaitTXAGCOffsetTimer = 0; + + while ((ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30) != 1) && ((TxPath & 1) == 1)) { + WaitTXAGCOffsetTimer++; + + if (WaitTXAGCOffsetTimer >= 1000) + break; + } + + /*Read the offset value at BB Reg.*/ + OffsetVaule = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + + TSSIFunction = ODM_GetBBReg(pDM_Odm, 0xDEC, BIT30); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Call %s 0XDEC TSSIFunction[30]=0X%X OffsetVaule[29:24]=0X%X RFPath=%d\n", __func__, TSSIFunction, OffsetVaule, RFPath)); + + /*Disable BB TSSI Power Tracking*/ + ODM_SetBBReg(pDM_Odm, 0x1A8C, BIT7, 0); + /*Disable Path D TSSI Circuit*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x65, BIT10, 0); + + if (TSSIFunction == 1) { + TXBBSwing = ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK); + + for (i = 0; i <= 36; i++) { + if (TXBBSwing == TxScalingTable_Jaguar[i]) { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = i; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" PathD TXBBSwing = %d TXBBSwing=0X%X\n", TX_BBSwing_Index, TXBBSwing)); + break; + + } else { + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = pRFCalibrateInfo->DefaultOfdmIndex; + } + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = (u1Byte) ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGCIndex = 0X%X TX_BBSwing_Index = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + TxPowerIndexOffest = 63 - TxPowerIndex; + + rtn = GetTSSIModeTxAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, OffsetVaule, TxPowerIndexOffest); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TX_AGC_Index = %d TX_BBSwing_Index = %d rtn=%d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], rtn)); + + if (rtn == TRUE) { + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC And BB Swing are the same Path=%d\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" OffsetValue(0XDEC)=0X%X TXAGC(rD_TXAGC)=0X%X 0X1A1C(PathD BBSwing)(%d)=0X%X\n", + ODM_GetBBReg(pDM_Odm, 0xDEC, BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24), + ODM_GetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], + ODM_GetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" 0X55[13:9]=0X%X 0X56=0X%X\n", + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X55, BIT13 | BIT12 | BIT11 | BIT10 | BIT9), + ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, 0X56, 0XFFFFFFFF) + )); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" ========================================================\n")); + + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + (" TSSI does not Calculate Finish\n")); + + break; + + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + + break; + } + } + +} + +BOOLEAN GetMixModeTXAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u1Byte TxPowerIndexOffest +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; + u1Byte BBSwingLowerBound = 0; + + s1Byte TX_AGC_Index = 0; + u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); + + if (TxPowerIndexOffest > 0XF) + TxPowerIndexOffest = 0XF; + + if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { + TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } else { + TX_AGC_Index = 0; + + if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index < BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); + + return TRUE; +} + +VOID PowerTrackingByMixMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte TxRate = 0xFF; + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u1Byte TxPowerIndexOffest = 0; + u1Byte TxPowerIndex = 0; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking MIX MODE**********\n", RFPath)); + + TxPowerIndex = PHY_GetTxPowerIndex_8814A(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, (CHANNEL_WIDTH)BandWidth, Channel); + TxPowerIndexOffest = 63 - TxPowerIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d TxPowerIndex=%d\n", RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndex)); + + switch (RFPath) { + case ODM_RF_PATH_A: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_B: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_C: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_D: + GetMixModeTXAGCBBSWingOffset(pDM_Odm, Method, (ODM_RF_RADIO_PATH_E) RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + break; + } + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Power Index is the same, EEPROMThermalMeter = 0XFF or TxPowerTrackControl is Disable !!!!\n")); +} + +VOID PowerTrackingByTSSIMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath +) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking TSSI_MODE**********\n", RFPath)); + + SetTxAGCBBSWingOffset(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d End POWER Tracking TSSI_MODE**********\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n")); +} + + + +VOID ODM_TxPwrTrackSetPwr8814A( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Channel = pHalData->CurrentChannel; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + +/*K-Free*/ +#if 0 + s1Byte TXBBIndex = 0; + s1Byte TXBBUpperBound = 10, TXBBLowerBound = -5; + + TXBBIndex = pRFCalibrateInfo->KfreeOffset[RFPath] / 2; + + if (TXBBIndex > TXBBUpperBound) + TXBBIndex = TXBBUpperBound; + else if (TXBBIndex < TXBBLowerBound) + TXBBIndex = TXBBLowerBound; + + if (TXBBIndex >= 0) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 1); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), TXBBIndex); /*set RF Reg0x55 per path*/ + } else { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, BIT19, 0); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E) RFPath, rRF_TxGainOffset, (BIT18 | BIT17 | BIT16 | BIT15), (-1)*TXBBIndex); + } + +#endif + + if (Method == TXAGC) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("****************Path_%d POWER Tracking No TXAGC MODE**********\n", RFPath)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->Absolute_OFDMSwingIdx[%d] =%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])); + } else if (Method == TSSI_MODE) { + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == BBSWING) { /*use for mp driver clean power tracking status*/ + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rA_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rB_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_C: + ODM_SetBBReg(pDM_Odm, rC_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rC_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + case ODM_RF_PATH_D: + ODM_SetBBReg(pDM_Odm, rD_TXAGC, TXAGC_BITMASK, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rD_BBSWING, BBSWING_BITMASK, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); /*set BBswing*/ + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Wrong Path name!!!!\n")); + + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("RFPath=%d Clear 8814 Power tracking TXAGC=%d BBSwing=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath])); + + } else if (Method == MIX_MODE) { + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == MIX_2G_TSSI_5G_MODE) { + if (Channel <= 14) + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + else + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } else if (Method == MIX_5G_TSSI_2G_MODE) { + if (Channel <= 14) + PowerTrackingByTSSIMode(pDM_Odm, TSSI_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + else + PowerTrackingByMixMode(pDM_Odm, MIX_MODE, (ODM_RF_RADIO_PATH_E) RFPath); + } +} /*ODM_TxPwrTrackSetPwr8814A*/ + + +VOID GetDeltaSwingTable_8814A( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + +VOID GetDeltaSwingTable_8814A_PathCD( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#endif +#endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); +#endif + } + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + if (1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N; + } else { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2]; + *TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2]; + *TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2]; + *TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2]; + } else { + *TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +void ConfigureTxpowerTrack_8814A( + PTXPWRTRACK_CFG pConfig +) +{ + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = 8; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A; + pConfig->RfPathCount = MAX_PATH_NUM_8814A; + pConfig->ThermalRegAddr = RF_T_METER_88E; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A; + pConfig->DoIQK = DoIQK_8814A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A; + pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD; +} + +VOID phy_LCCalibrate_8814A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T +) +{ + u4Byte LC_Cal = 0, cnt; + + /*Check continuous TX and Packet TX*/ + u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);; + + /*Backup RF reg18.*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + if ((reg0x914 & 0x70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); + + /*3 3. Read RF reg18*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + /*3 4. Set LC calibration begin bit15*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); + + ODM_delay_ms(100); + + for (cnt = 0; cnt < 100; cnt++) { + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + + ODM_delay_ms(10); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt)); + + + + /*3 Restore original situation*/ + if ((reg0x914 & 70000) == 0) + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00); + + /*Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + DbgPrint("Call %s\n", __func__); +} + + +VOID phy_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T +) +{ +} + + +VOID PHY_LCCalibrate_8814A( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n")); + +/*#if (MP_DRIVER == 1)*/ + phy_LCCalibrate_8814A(pDM_Odm, TRUE); +/*#endif*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n")); + +} + +VOID PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta +) +{ + +} + + +VOID PHY_DPCalibrate_8814A( + IN PDM_ODM_T pDM_Odm +) +{ +} + + +BOOLEAN phy_QueryRFPathSwitch_8814A( + IN PADAPTER pAdapter +) +{ + return TRUE; +} + + +BOOLEAN PHY_QueryRFPathSwitch_8814A( + IN PADAPTER pAdapter +) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + + return phy_QueryRFPathSwitch_8814A(pAdapter); +} + + +VOID phy_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T +) +{ +} +VOID PHY_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain +) +{ +} + + + + +#else /*(RTL8814A_SUPPORT == 0)*/ +VOID PHY_LCCalibrate_8814A( + IN PDM_ODM_T pDM_Odm +) {} + +VOID PHY_IQCalibrate_8814A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery +) {} +#endif /* (RTL8814A_SUPPORT == 0)*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.h b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.h index cf4fb794b30..051b67e6a36 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/halphyrf_8814a_win.h @@ -1,149 +1,149 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8814A_H__ -#define __HAL_PHY_RF_8814A_H__ - -#if (RTL8814A_SUPPORT == 1) - - -/*--------------------------Define Parameters-------------------------------*/ -#define AVG_THERMAL_NUM_8814A 4 - -#include "halphyrf_win.h" - -void ConfigureTxpowerTrack_8814A( - PTXPWRTRACK_CFG pConfig - ); - -VOID GetDeltaSwingTable_8814A( - PVOID pDM_VOID, - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B - ); - - -VOID -GetDeltaSwingTable_8814A_PathCD( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_C, - OUT pu1Byte *TemperatureDOWN_C, - OUT pu1Byte *TemperatureUP_D, - OUT pu1Byte *TemperatureDOWN_D - ); - - -VOID -ODM_TxPwrTrackSetPwr8814A( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -#if 0 -u1Byte -CheckRFGainOffset( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); -#endif - -u1Byte -GetTSSIVALUE( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath - ); - -BOOLEAN -GetTSSIModeTxAGCBBSWingOffset( - IN PDM_ODM_T pDM_Odm, - IN PWRTRACK_METHOD Method, - IN u1Byte RFPath, - IN u4Byte OffsetVaule, - IN u1Byte TxPowerIndexOffest - ); - - -VOID -PowerTrackingByMixMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); - -VOID -PowerTrackingByTSSIMode( - PDM_ODM_T pDM_Odm, - PWRTRACK_METHOD Method, - u1Byte RFPath - ); - - -// -// LC calibrate -// -void -PHY_LCCalibrate_8814A( - IN PVOID pDM_VOID - ); - -// -// AP calibrate -// -void -PHY_APCalibrate_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN s1Byte delta - ); - - -VOID -PHY_DPCalibrate_8814A( - IN PDM_ODM_T pDM_Odm - ); - - -VOID PHY_SetRFPathSwitch_8814A( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - - -#else /* (RTL8814A_SUPPORT == 0)*/ - -#define PHY_LCCalibrate_8814A(_pDM_Odm) FALSE - -#endif /* RTL8814A_SUPPORT */ - -#endif // #ifndef __HAL_PHY_RF_8188E_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8814A_H__ +#define __HAL_PHY_RF_8814A_H__ + +#if (RTL8814A_SUPPORT == 1) + + +/*--------------------------Define Parameters-------------------------------*/ +#define AVG_THERMAL_NUM_8814A 4 + +#include "halphyrf_win.h" + +void ConfigureTxpowerTrack_8814A( + PTXPWRTRACK_CFG pConfig + ); + +VOID GetDeltaSwingTable_8814A( + PVOID pDM_VOID, + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B + ); + + +VOID +GetDeltaSwingTable_8814A_PathCD( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_C, + OUT pu1Byte *TemperatureDOWN_C, + OUT pu1Byte *TemperatureUP_D, + OUT pu1Byte *TemperatureDOWN_D + ); + + +VOID +ODM_TxPwrTrackSetPwr8814A( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +#if 0 +u1Byte +CheckRFGainOffset( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); +#endif + +u1Byte +GetTSSIVALUE( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath + ); + +BOOLEAN +GetTSSIModeTxAGCBBSWingOffset( + IN PDM_ODM_T pDM_Odm, + IN PWRTRACK_METHOD Method, + IN u1Byte RFPath, + IN u4Byte OffsetVaule, + IN u1Byte TxPowerIndexOffest + ); + + +VOID +PowerTrackingByMixMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); + +VOID +PowerTrackingByTSSIMode( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath + ); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8814A( + IN PVOID pDM_VOID + ); + +// +// AP calibrate +// +void +PHY_APCalibrate_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta + ); + + +VOID +PHY_DPCalibrate_8814A( + IN PDM_ODM_T pDM_Odm + ); + + +VOID PHY_SetRFPathSwitch_8814A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + + +#else /* (RTL8814A_SUPPORT == 0)*/ + +#define PHY_LCCalibrate_8814A(_pDM_Odm) FALSE + +#endif /* RTL8814A_SUPPORT */ + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.c b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.c index 655fc5087e5..a3b8c4640f5 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.c @@ -1,580 +1,580 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - -#if (RTL8814A_SUPPORT == 1) - - -/*---------------------------Define Local Constant---------------------------*/ - - -/*---------------------------Define Local Constant---------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8814A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - - PHY_IQCalibrate_8814A(pDM_Odm, FALSE); - -} -#else -/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8814A, but DoIQK_8814A and PHY_IQCalibrate_8814A have different arguments*/ -void DoIQK_8814A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bReCovery = (BOOLEAN) DeltaThermalIndex; - - PHY_IQCalibrate_8814A(pDM_Odm, bReCovery); -} -#endif -//1 7. IQK - -VOID -_IQK_BackupMacBB_8814A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MAC_backup, - IN pu4Byte BB_backup, - IN pu4Byte Backup_MAC_REG, - IN pu4Byte Backup_BB_REG - ) -{ - u4Byte i; - //save MACBB default value - for (i = 0; i < MAC_REG_NUM_8814; i++){ - MAC_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MAC_REG[i]); - } - for (i = 0; i < BB_REG_NUM_8814; i++){ - BB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_BB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} - - -VOID -_IQK_BackupRF_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RF_backup[][4], - IN pu4Byte Backup_RF_REG - ) -{ - u4Byte i; - //Save RF Parameters - for (i = 0; i < RF_REG_NUM_8814; i++){ - RF_backup[i][ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask); - RF_backup[i][ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask); - RF_backup[i][ODM_RF_PATH_C] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask); - RF_backup[i][ODM_RF_PATH_D] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} - - -VOID -_IQK_AFESetting_8814A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN Do_IQK - ) -{ - if(Do_IQK) - { - // IQK AFE Setting RX_WAIT_CCA mode - ODM_Write4Byte(pDM_Odm, 0xc60, 0x0e808003); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x0e808003); - ODM_Write4Byte(pDM_Odm, 0x1860, 0x0e808003); - ODM_Write4Byte(pDM_Odm, 0x1a60, 0x0e808003); - ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); - - ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); - ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); - - ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); - ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE IQK mode Success!!!!\n")); - } - else - { - ODM_Write4Byte(pDM_Odm, 0xc60, 0x07808003); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x07808003); - ODM_Write4Byte(pDM_Odm, 0x1860, 0x07808003); - ODM_Write4Byte(pDM_Odm, 0x1a60, 0x07808003); - ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); - - ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); - ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); - - ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); - ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE Normal mode Success!!!!\n")); - } - -} - - -VOID -_IQK_RestoreMacBB_8814A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MAC_backup, - IN pu4Byte BB_backup, - IN pu4Byte Backup_MAC_REG, - IN pu4Byte Backup_BB_REG - ) -{ - u4Byte i; - //Reload MacBB Parameters - for (i = 0; i < MAC_REG_NUM_8814; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MAC_REG[i], MAC_backup[i]); - } - for (i = 0; i < BB_REG_NUM_8814; i++){ - ODM_Write4Byte(pDM_Odm, Backup_BB_REG[i], BB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} - -VOID -_IQK_RestoreRF_8814A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_backup[][4] - ) -{ - u4Byte i; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0xef, bRFRegOffsetMask, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0xef, bRFRegOffsetMask, 0x0); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x8f, bRFRegOffsetMask, 0x88001); - - for (i = 0; i < RF_REG_NUM_8814; i++) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_A]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_B]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_C]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_D]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Success!!!!\n")); - -} - -VOID -PHY_ResetIQKResult_8814A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); - ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000002); - ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000004); - ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000006); - ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xc10, 0x100); - ODM_Write4Byte(pDM_Odm, 0xe10, 0x100); - ODM_Write4Byte(pDM_Odm, 0x1810, 0x100); - ODM_Write4Byte(pDM_Odm, 0x1a10, 0x100); -} - -VOID -_IQK_ResetNCTL_8814A( - IN PDM_ODM_T - pDM_Odm -) -{ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); - ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000006); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); - ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000002); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ResetNCTL Success!!!!\n")); -} - -VOID -_IQK_ConfigureMAC_8814A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xe); // CCA off - ODM_SetBBReg(pDM_Odm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0x18b4, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777); - ODM_SetBBReg(pDM_Odm, 0x1abc, 0x0ff00000, 0x77); - ODM_SetBBReg(pDM_Odm, 0x910, BIT(23)|BIT(22), 0x0); - /*by YN*/ - ODM_SetBBReg(pDM_Odm, 0xcbc, 0xf, 0x0); -} - -VOID -_LOK_One_Shot( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte Path = 0, delay_count = 0, ii; - BOOLEAN LOK_notready = FALSE; - u4Byte LOK_temp1 = 0, LOK_temp2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n")); - for(Path =0; Path <=3; Path++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("==========S%d LOK ==========\n", Path)); - - ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source - ODM_Write4Byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} - ODM_delay_ms(LOK_delay); - delay_count = 0; - LOK_notready = TRUE; - - while(LOK_notready){ - LOK_notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); - ODM_delay_ms(1); - delay_count++; - if(delay_count >= 10){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("S%d LOK timeout!!!\n", Path)); - - _IQK_ResetNCTL_8814A(pDM_Odm); - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("S%d ==> delay_count = 0x%d\n", Path, delay_count)); - - if(!LOK_notready){ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); - ODM_Write4Byte(pDM_Odm, 0x1bd4, 0x003f0001); - LOK_temp2 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f; - LOK_temp1 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f; - - for(ii = 1; ii<5; ii++){ - LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2)); - LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2)); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4)); - - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0x07c00, LOK_temp1>>4); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0xf8000, LOK_temp2>>4); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("==>S%d fill LOK\n", Path)); - - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("==>S%d LOK Fail!!!\n", Path)); - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, bRFRegOffsetMask, 0x08400); - } - pIQK_info->LOK_fail[Path] = LOK_notready; - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("LOK0_notready = %d, LOK1_notready = %d, LOK2_notready = %d, LOK3_notready = %d\n", - pIQK_info->LOK_fail[0], pIQK_info->LOK_fail[1], pIQK_info->LOK_fail[2], pIQK_info->LOK_fail[3])); -} - -VOID -_IQK_One_Shot( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte Path = 0, delay_count = 0, cal_retry = 0, idx; - BOOLEAN notready = TRUE, fail = TRUE; - u4Byte IQK_CMD = 0x0; - u2Byte IQK_Apply[4] = {0xc94, 0xe94, 0x1894, 0x1a94}; - - for(idx = 0; idx <= 1; idx++){ // ii = 0:TXK , 1: RXK - - if(idx == TX_IQK){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("============ WBTXIQK ============\n")); - } - else if(idx == RX_IQK){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("============ WBRXIQK ============\n")); - } - - for (Path = 0; Path <= 3; Path++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==========S%d IQK ==========\n", Path)); - cal_retry = 0; - fail = TRUE; - while (fail) { - ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); - if (idx == TX_IQK) { - IQK_CMD = (0xf8000001|(*pDM_Odm->pBandWidth+3)<<8|(1<<(4+Path))); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("TXK_Trigger = 0x%x\n", IQK_CMD)); - /*{0xf8000311, 0xf8000321, 0xf8000341, 0xf8000381} ==> 20 WBTXK (CMD = 3)*/ - /*{0xf8000411, 0xf8000421, 0xf8000441, 0xf8000481} ==> 40 WBTXK (CMD = 4)*/ - /*{0xf8000511, 0xf8000521, 0xf8000541, 0xf8000581} ==> 80 WBTXK (CMD = 5)*/ - } else if (idx == RX_IQK) { - if (*pDM_Odm->pBandType == ODM_BAND_2_4G) { - ODM_SetRFReg(pDM_Odm, Path, 0xdf, BIT(11), 0x1); - ODM_SetRFReg(pDM_Odm, Path, 0x56, 0xfffff, 0x51ce1); - switch (Path) { - case 0: - case 1: - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x54775477); - break; - case 2: - ODM_Write4Byte(pDM_Odm, 0x18b4, 0x54775477); - break; - case 3: - ODM_Write4Byte(pDM_Odm, 0x1abc, 0x75400000); - ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777); - break; - } - } - IQK_CMD = (0xf8000001|(9-*pDM_Odm->pBandWidth)<<8|(1<<(4+Path))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("TXK_Trigger = 0x%x\n", IQK_CMD)); - /*{0xf8000911, 0xf8000921, 0xf8000941, 0xf8000981} ==> 20 WBRXK (CMD = 9)*/ - /*{0xf8000811, 0xf8000821, 0xf8000841, 0xf8000881} ==> 40 WBRXK (CMD = 8)*/ - /*{0xf8000711, 0xf8000721, 0xf8000741, 0xf8000781} ==> 80 WBRXK (CMD = 7)*/ - } - - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD); - ODM_delay_ms(WBIQK_delay); - - delay_count = 0; - notready = TRUE; - while (notready) { - notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); - if (!notready) { - fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b08, BIT(26)); - break; - } - ODM_delay_ms(1); - delay_count++; - if (delay_count >= 20) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S%d IQK timeout!!!\n", Path)); - _IQK_ResetNCTL_8814A(pDM_Odm); - break; - } - } - if (fail) - cal_retry++; - if (cal_retry > 3) - break; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("S%d ==> 0x1b00 = 0x%x\n", Path, ODM_Read4Byte(pDM_Odm, 0x1b00))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("S%d ==> 0x1b08 = 0x%x\n", Path, ODM_Read4Byte(pDM_Odm, 0x1b08))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("S%d ==> delay_count = 0x%d, cal_retry = %x\n", Path, delay_count, cal_retry)); - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); - if(!fail){ - if(idx == TX_IQK){ - pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b38); - } - else if(idx == RX_IQK){ - ODM_Write4Byte(pDM_Odm, 0x1b3c, 0x20000000); - pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b3c); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("S%d_IQC = 0x%x\n", Path, pIQK_info->IQC_Matrix[idx][Path])); - - } - - if(idx == RX_IQK){ - if(pIQK_info->IQK_fail[TX_IQK][Path] == FALSE) // TXIQK success in RXIQK - ODM_Write4Byte( pDM_Odm, 0x1b38, pIQK_info->IQC_Matrix[TX_IQK][Path]); - else - ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], BIT0, 0x0); - - if (Path == 0) - ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0); - - if (fail) - ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0); - - if (*pDM_Odm->pBandType == ODM_BAND_2_4G) - ODM_SetRFReg(pDM_Odm, Path, 0xdf, BIT(11), 0x0); - } - - pIQK_info->IQK_fail[idx][Path] = fail; - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("IQK0_fail = %d, IQK1_fail = %d, IQK2_fail = %d, IQK3_fail = %d\n", - pIQK_info->IQK_fail[idx][0], pIQK_info->IQK_fail[idx][1], pIQK_info->IQK_fail[idx][2], pIQK_info->IQK_fail[idx][3])); - } -} - -VOID -_IQK_Tx_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte chnlIdx - ) -{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, pBandType = %d\n", pDM_Odm->SupportInterface, *pDM_Odm->pBandType)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("CutVersion = %x\n", pDM_Odm->CutVersion)); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, BIT(19), 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, BIT(19), 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x58, BIT(19), 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x58, BIT(19), 0x1); - - ODM_SetBBReg(pDM_Odm, 0xc94, (BIT11|BIT10|BIT0), 0x401); - ODM_SetBBReg(pDM_Odm, 0xe94, (BIT11|BIT10|BIT0), 0x401); - ODM_SetBBReg(pDM_Odm, 0x1894, (BIT11|BIT10|BIT0), 0x401); - ODM_SetBBReg(pDM_Odm, 0x1a94, (BIT11|BIT10|BIT0), 0x401); - - if(*pDM_Odm->pBandType == ODM_BAND_5G) - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000ff1); - else - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000ef1); - - ODM_delay_ms(1); - - ODM_Write4Byte(pDM_Odm, 0x810, 0x20101063); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x0B00C000); - - _LOK_One_Shot(pDM_Odm); - _IQK_One_Shot(pDM_Odm); - -} - -VOID -phy_IQCalibrate_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Channel - ) -{ - - u4Byte MAC_backup[MAC_REG_NUM_8814], BB_backup[BB_REG_NUM_8814], RF_backup[RF_REG_NUM_8814][4]; - u4Byte Backup_MAC_REG[MAC_REG_NUM_8814] = {0x520, 0x550}; - u4Byte Backup_BB_REG[BB_REG_NUM_8814] = {0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0, - 0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910}; - u4Byte Backup_RF_REG[RF_REG_NUM_8814] = {0x0}; - u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); - - _IQK_BackupMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); - _IQK_AFESetting_8814A(pDM_Odm,TRUE); - _IQK_BackupRF_8814A(pDM_Odm, RF_backup, Backup_RF_REG); - _IQK_ConfigureMAC_8814A(pDM_Odm); - _IQK_Tx_8814A(pDM_Odm, chnlIdx); - _IQK_ResetNCTL_8814A(pDM_Odm); //for 3-wire to BB use - _IQK_AFESetting_8814A(pDM_Odm,FALSE); - _IQK_RestoreMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); - _IQK_RestoreRF_8814A(pDM_Odm, Backup_RF_REG, RF_backup); -} - -/*IQK version:v1.3*/ -/*fix RF0x8f read fail issue*/ - - -VOID -PHY_IQCalibrate_8814A( - IN PVOID pDM_VOID, - IN BOOLEAN bReCovery - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif//(MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - - #if MP_DRIVER == 1 - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression ) - return; - #endif - -#endif - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - phy_IQCalibrate_8814A(pDM_Odm, pHalData->CurrentChannel); - #else - phy_IQCalibrate_8814A(pDM_Odm, *pDM_Odm->pChannel); - #endif -} - -VOID -PHY_IQCalibrate_8814A_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte ii, jj; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("=====>PHY_IQCalibrate_8814A_Init\n")); - for(jj = 0; jj < 2; jj++){ - for(ii = 0; ii < NUM; ii++){ - pIQK_info->LOK_fail[ii] = TRUE; - pIQK_info->IQK_fail[jj][ii] = TRUE; - pIQK_info->IQC_Matrix[jj][ii] = 0x20000000; - } - } -} - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +#if (RTL8814A_SUPPORT == 1) + + +/*---------------------------Define Local Constant---------------------------*/ + + +/*---------------------------Define Local Constant---------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void DoIQK_8814A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + + PHY_IQCalibrate_8814A(pDM_Odm, FALSE); + +} +#else +/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8814A, but DoIQK_8814A and PHY_IQCalibrate_8814A have different arguments*/ +void DoIQK_8814A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bReCovery = (BOOLEAN) DeltaThermalIndex; + + PHY_IQCalibrate_8814A(pDM_Odm, bReCovery); +} +#endif +//1 7. IQK + +VOID +_IQK_BackupMacBB_8814A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MAC_backup, + IN pu4Byte BB_backup, + IN pu4Byte Backup_MAC_REG, + IN pu4Byte Backup_BB_REG + ) +{ + u4Byte i; + //save MACBB default value + for (i = 0; i < MAC_REG_NUM_8814; i++){ + MAC_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MAC_REG[i]); + } + for (i = 0; i < BB_REG_NUM_8814; i++){ + BB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_BB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} + + +VOID +_IQK_BackupRF_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RF_backup[][4], + IN pu4Byte Backup_RF_REG + ) +{ + u4Byte i; + //Save RF Parameters + for (i = 0; i < RF_REG_NUM_8814; i++){ + RF_backup[i][ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask); + RF_backup[i][ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask); + RF_backup[i][ODM_RF_PATH_C] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask); + RF_backup[i][ODM_RF_PATH_D] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} + + +VOID +_IQK_AFESetting_8814A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN Do_IQK + ) +{ + if(Do_IQK) + { + // IQK AFE Setting RX_WAIT_CCA mode + ODM_Write4Byte(pDM_Odm, 0xc60, 0x0e808003); + ODM_Write4Byte(pDM_Odm, 0xe60, 0x0e808003); + ODM_Write4Byte(pDM_Odm, 0x1860, 0x0e808003); + ODM_Write4Byte(pDM_Odm, 0x1a60, 0x0e808003); + ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); + + ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); + ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); + + ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); + ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE IQK mode Success!!!!\n")); + } + else + { + ODM_Write4Byte(pDM_Odm, 0xc60, 0x07808003); + ODM_Write4Byte(pDM_Odm, 0xe60, 0x07808003); + ODM_Write4Byte(pDM_Odm, 0x1860, 0x07808003); + ODM_Write4Byte(pDM_Odm, 0x1a60, 0x07808003); + ODM_SetBBReg(pDM_Odm, 0x90c, BIT(13), 0x1); + + ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3); + ODM_SetBBReg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0); + + ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x1); + ODM_SetBBReg(pDM_Odm, 0x804, BIT(2), 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE Normal mode Success!!!!\n")); + } + +} + + +VOID +_IQK_RestoreMacBB_8814A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MAC_backup, + IN pu4Byte BB_backup, + IN pu4Byte Backup_MAC_REG, + IN pu4Byte Backup_BB_REG + ) +{ + u4Byte i; + //Reload MacBB Parameters + for (i = 0; i < MAC_REG_NUM_8814; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MAC_REG[i], MAC_backup[i]); + } + for (i = 0; i < BB_REG_NUM_8814; i++){ + ODM_Write4Byte(pDM_Odm, Backup_BB_REG[i], BB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} + +VOID +_IQK_RestoreRF_8814A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_backup[][4] + ) +{ + u4Byte i; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0xef, bRFRegOffsetMask, 0x0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0xef, bRFRegOffsetMask, 0x0); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x8f, bRFRegOffsetMask, 0x88001); + + for (i = 0; i < RF_REG_NUM_8814; i++) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_A]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_B]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_C]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_D]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Success!!!!\n")); + +} + +VOID +PHY_ResetIQKResult_8814A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); + ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000002); + ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000004); + ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000006); + ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xc10, 0x100); + ODM_Write4Byte(pDM_Odm, 0xe10, 0x100); + ODM_Write4Byte(pDM_Odm, 0x1810, 0x100); + ODM_Write4Byte(pDM_Odm, 0x1a10, 0x100); +} + +VOID +_IQK_ResetNCTL_8814A( + IN PDM_ODM_T + pDM_Odm +) +{ + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); + ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000006); + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000); + ODM_Write4Byte(pDM_Odm, 0x1b80, 0x00000002); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ResetNCTL Success!!!!\n")); +} + +VOID +_IQK_ConfigureMAC_8814A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xe); // CCA off + ODM_SetBBReg(pDM_Odm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off + ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0x18b4, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777); + ODM_SetBBReg(pDM_Odm, 0x1abc, 0x0ff00000, 0x77); + ODM_SetBBReg(pDM_Odm, 0x910, BIT(23)|BIT(22), 0x0); + /*by YN*/ + ODM_SetBBReg(pDM_Odm, 0xcbc, 0xf, 0x0); +} + +VOID +_LOK_One_Shot( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; + u1Byte Path = 0, delay_count = 0, ii; + BOOLEAN LOK_notready = FALSE; + u4Byte LOK_temp1 = 0, LOK_temp2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n")); + for(Path =0; Path <=3; Path++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("==========S%d LOK ==========\n", Path)); + + ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source + ODM_Write4Byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} + ODM_delay_ms(LOK_delay); + delay_count = 0; + LOK_notready = TRUE; + + while(LOK_notready){ + LOK_notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); + ODM_delay_ms(1); + delay_count++; + if(delay_count >= 10){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("S%d LOK timeout!!!\n", Path)); + + _IQK_ResetNCTL_8814A(pDM_Odm); + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("S%d ==> delay_count = 0x%d\n", Path, delay_count)); + + if(!LOK_notready){ + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); + ODM_Write4Byte(pDM_Odm, 0x1bd4, 0x003f0001); + LOK_temp2 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f; + LOK_temp1 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f; + + for(ii = 1; ii<5; ii++){ + LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2)); + LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2)); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4)); + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0x07c00, LOK_temp1>>4); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0xf8000, LOK_temp2>>4); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("==>S%d fill LOK\n", Path)); + + } + else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("==>S%d LOK Fail!!!\n", Path)); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, bRFRegOffsetMask, 0x08400); + } + pIQK_info->LOK_fail[Path] = LOK_notready; + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("LOK0_notready = %d, LOK1_notready = %d, LOK2_notready = %d, LOK3_notready = %d\n", + pIQK_info->LOK_fail[0], pIQK_info->LOK_fail[1], pIQK_info->LOK_fail[2], pIQK_info->LOK_fail[3])); +} + +VOID +_IQK_One_Shot( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; + u1Byte Path = 0, delay_count = 0, cal_retry = 0, idx; + BOOLEAN notready = TRUE, fail = TRUE; + u4Byte IQK_CMD = 0x0; + u2Byte IQK_Apply[4] = {0xc94, 0xe94, 0x1894, 0x1a94}; + + for(idx = 0; idx <= 1; idx++){ // ii = 0:TXK , 1: RXK + + if(idx == TX_IQK){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("============ WBTXIQK ============\n")); + } + else if(idx == RX_IQK){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("============ WBRXIQK ============\n")); + } + + for (Path = 0; Path <= 3; Path++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==========S%d IQK ==========\n", Path)); + cal_retry = 0; + fail = TRUE; + while (fail) { + ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); + if (idx == TX_IQK) { + IQK_CMD = (0xf8000001|(*pDM_Odm->pBandWidth+3)<<8|(1<<(4+Path))); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("TXK_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000311, 0xf8000321, 0xf8000341, 0xf8000381} ==> 20 WBTXK (CMD = 3)*/ + /*{0xf8000411, 0xf8000421, 0xf8000441, 0xf8000481} ==> 40 WBTXK (CMD = 4)*/ + /*{0xf8000511, 0xf8000521, 0xf8000541, 0xf8000581} ==> 80 WBTXK (CMD = 5)*/ + } else if (idx == RX_IQK) { + if (*pDM_Odm->pBandType == ODM_BAND_2_4G) { + ODM_SetRFReg(pDM_Odm, Path, 0xdf, BIT(11), 0x1); + ODM_SetRFReg(pDM_Odm, Path, 0x56, 0xfffff, 0x51ce1); + switch (Path) { + case 0: + case 1: + ODM_Write4Byte(pDM_Odm, 0xeb0, 0x54775477); + break; + case 2: + ODM_Write4Byte(pDM_Odm, 0x18b4, 0x54775477); + break; + case 3: + ODM_Write4Byte(pDM_Odm, 0x1abc, 0x75400000); + ODM_Write4Byte(pDM_Odm, 0x1ab4, 0x77777777); + break; + } + } + IQK_CMD = (0xf8000001|(9-*pDM_Odm->pBandWidth)<<8|(1<<(4+Path))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("TXK_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000911, 0xf8000921, 0xf8000941, 0xf8000981} ==> 20 WBRXK (CMD = 9)*/ + /*{0xf8000811, 0xf8000821, 0xf8000841, 0xf8000881} ==> 40 WBRXK (CMD = 8)*/ + /*{0xf8000711, 0xf8000721, 0xf8000741, 0xf8000781} ==> 80 WBRXK (CMD = 7)*/ + } + + ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD); + ODM_delay_ms(WBIQK_delay); + + delay_count = 0; + notready = TRUE; + while (notready) { + notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); + if (!notready) { + fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b08, BIT(26)); + break; + } + ODM_delay_ms(1); + delay_count++; + if (delay_count >= 20) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S%d IQK timeout!!!\n", Path)); + _IQK_ResetNCTL_8814A(pDM_Odm); + break; + } + } + if (fail) + cal_retry++; + if (cal_retry > 3) + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("S%d ==> 0x1b00 = 0x%x\n", Path, ODM_Read4Byte(pDM_Odm, 0x1b00))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("S%d ==> 0x1b08 = 0x%x\n", Path, ODM_Read4Byte(pDM_Odm, 0x1b08))); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("S%d ==> delay_count = 0x%d, cal_retry = %x\n", Path, delay_count, cal_retry)); + + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); + if(!fail){ + if(idx == TX_IQK){ + pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b38); + } + else if(idx == RX_IQK){ + ODM_Write4Byte(pDM_Odm, 0x1b3c, 0x20000000); + pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b3c); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("S%d_IQC = 0x%x\n", Path, pIQK_info->IQC_Matrix[idx][Path])); + + } + + if(idx == RX_IQK){ + if(pIQK_info->IQK_fail[TX_IQK][Path] == FALSE) // TXIQK success in RXIQK + ODM_Write4Byte( pDM_Odm, 0x1b38, pIQK_info->IQC_Matrix[TX_IQK][Path]); + else + ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], BIT0, 0x0); + + if (Path == 0) + ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0); + + if (fail) + ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0); + + if (*pDM_Odm->pBandType == ODM_BAND_2_4G) + ODM_SetRFReg(pDM_Odm, Path, 0xdf, BIT(11), 0x0); + } + + pIQK_info->IQK_fail[idx][Path] = fail; + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("IQK0_fail = %d, IQK1_fail = %d, IQK2_fail = %d, IQK3_fail = %d\n", + pIQK_info->IQK_fail[idx][0], pIQK_info->IQK_fail[idx][1], pIQK_info->IQK_fail[idx][2], pIQK_info->IQK_fail[idx][3])); + } +} + +VOID +_IQK_Tx_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte chnlIdx + ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA2G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, pBandType = %d\n", pDM_Odm->SupportInterface, *pDM_Odm->pBandType)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("CutVersion = %x\n", pDM_Odm->CutVersion)); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x58, BIT(19), 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x58, BIT(19), 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_C, 0x58, BIT(19), 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_D, 0x58, BIT(19), 0x1); + + ODM_SetBBReg(pDM_Odm, 0xc94, (BIT11|BIT10|BIT0), 0x401); + ODM_SetBBReg(pDM_Odm, 0xe94, (BIT11|BIT10|BIT0), 0x401); + ODM_SetBBReg(pDM_Odm, 0x1894, (BIT11|BIT10|BIT0), 0x401); + ODM_SetBBReg(pDM_Odm, 0x1a94, (BIT11|BIT10|BIT0), 0x401); + + if(*pDM_Odm->pBandType == ODM_BAND_5G) + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000ff1); + else + ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000ef1); + + ODM_delay_ms(1); + + ODM_Write4Byte(pDM_Odm, 0x810, 0x20101063); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x0B00C000); + + _LOK_One_Shot(pDM_Odm); + _IQK_One_Shot(pDM_Odm); + +} + +VOID +phy_IQCalibrate_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Channel + ) +{ + + u4Byte MAC_backup[MAC_REG_NUM_8814], BB_backup[BB_REG_NUM_8814], RF_backup[RF_REG_NUM_8814][4]; + u4Byte Backup_MAC_REG[MAC_REG_NUM_8814] = {0x520, 0x550}; + u4Byte Backup_BB_REG[BB_REG_NUM_8814] = {0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0, + 0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910}; + u4Byte Backup_RF_REG[RF_REG_NUM_8814] = {0x0}; + u1Byte chnlIdx = ODM_GetRightChnlPlaceforIQK(Channel); + + _IQK_BackupMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); + _IQK_AFESetting_8814A(pDM_Odm,TRUE); + _IQK_BackupRF_8814A(pDM_Odm, RF_backup, Backup_RF_REG); + _IQK_ConfigureMAC_8814A(pDM_Odm); + _IQK_Tx_8814A(pDM_Odm, chnlIdx); + _IQK_ResetNCTL_8814A(pDM_Odm); //for 3-wire to BB use + _IQK_AFESetting_8814A(pDM_Odm,FALSE); + _IQK_RestoreMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); + _IQK_RestoreRF_8814A(pDM_Odm, Backup_RF_REG, RF_backup); +} + +/*IQK version:v1.3*/ +/*fix RF0x8f read fail issue*/ + + +VOID +PHY_IQCalibrate_8814A( + IN PVOID pDM_VOID, + IN BOOLEAN bReCovery + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif + #endif//(MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + #endif + + #if MP_DRIVER == 1 + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression ) + return; + #endif + +#endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + phy_IQCalibrate_8814A(pDM_Odm, pHalData->CurrentChannel); + #else + phy_IQCalibrate_8814A(pDM_Odm, *pDM_Odm->pChannel); + #endif +} + +VOID +PHY_IQCalibrate_8814A_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; + u1Byte ii, jj; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("=====>PHY_IQCalibrate_8814A_Init\n")); + for(jj = 0; jj < 2; jj++){ + for(ii = 0; ii < NUM; ii++){ + pIQK_info->LOK_fail[ii] = TRUE; + pIQK_info->IQK_fail[jj][ii] = TRUE; + pIQK_info->IQC_Matrix[jj][ii] = 0x20000000; + } + } +} + +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.h b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.h index bc495b86d99..fc39a69440d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_iqk_8814a.h @@ -1,70 +1,70 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __PHYDM_IQK_8814A_H__ -#define __PHYDM_IQK_8814A_H__ - -#if (RTL8814A_SUPPORT == 1) - - -/*--------------------------Define Parameters-------------------------------*/ -#define MAC_REG_NUM_8814 2 -#define BB_REG_NUM_8814 14 -#define RF_REG_NUM_8814 1 -/*---------------------------End Define Parameters-------------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -DoIQK_8814A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#else -VOID -DoIQK_8814A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#endif - -VOID -PHY_IQCalibrate_8814A( - IN PVOID pDM_VOID, - IN BOOLEAN bReCovery - ); - -VOID -PHY_IQCalibrate_8814A_Init( - IN PVOID pDM_VOID - ); - -#else /* (RTL8814A_SUPPORT == 0)*/ - -#define PHY_IQCalibrate_8814A(_pDM_VOID, _bReCovery) 0 -#define PHY_IQCalibrate_8814A_Init(_pDM_VOID) - -#endif /* RTL8814A_SUPPORT */ - - -#endif /* #ifndef __PHYDM_IQK_8814A_H__*/ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDM_IQK_8814A_H__ +#define __PHYDM_IQK_8814A_H__ + +#if (RTL8814A_SUPPORT == 1) + + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8814 2 +#define BB_REG_NUM_8814 14 +#define RF_REG_NUM_8814 1 +/*---------------------------End Define Parameters-------------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +DoIQK_8814A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#else +VOID +DoIQK_8814A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#endif + +VOID +PHY_IQCalibrate_8814A( + IN PVOID pDM_VOID, + IN BOOLEAN bReCovery + ); + +VOID +PHY_IQCalibrate_8814A_Init( + IN PVOID pDM_VOID + ); + +#else /* (RTL8814A_SUPPORT == 0)*/ + +#define PHY_IQCalibrate_8814A(_pDM_VOID, _bReCovery) 0 +#define PHY_IQCalibrate_8814A_Init(_pDM_VOID) + +#endif /* RTL8814A_SUPPORT */ + + +#endif /* #ifndef __PHYDM_IQK_8814A_H__*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.c b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.c index 58165e1d857..c3339d47bc2 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.c @@ -1,219 +1,219 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) - -void -odm_ConfigRFReg_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if(Addr == 0xfe || Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else - { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } -} - - -void -odm_ConfigRF_RadioA_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigRF_RadioC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_C, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigRF_RadioD_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_D, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data)); - -} - -void -odm_ConfigMAC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else - { -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - { - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - } - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8814A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) + +void +odm_ConfigRFReg_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigRF_RadioC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_C, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigRF_RadioD_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, ODM_RF_PATH_D, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + } + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8814A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.h b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.h index df32a1c810c..ba4ac8cc033 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_regconfig8814a.h @@ -1,109 +1,109 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8814A -#define __INC_ODM_REGCONFIG_H_8814A - -#if (RTL8814A_SUPPORT == 1) - -void -odm_ConfigRFReg_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioD_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8814A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8814A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8814A +#define __INC_ODM_REGCONFIG_H_8814A + +#if (RTL8814A_SUPPORT == 1) + +void +odm_ConfigRFReg_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioD_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8814A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8814A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.c b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.c index 85f74d5ec26..413e0ff6a5e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.c @@ -1,290 +1,290 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8814A_SUPPORT == 1) - -VOID -odm_Write_Dynamic_CCA_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte CurrentMFstate - ) -{ - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - - if (PrimaryCCA->MF_state != CurrentMFstate){ - - ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate); - } - - PrimaryCCA->MF_state = CurrentMFstate; - -} - -VOID -odm_PrimaryCCA_Check_Init_8814A( - IN PDM_ODM_T pDM_Odm) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->Monitor_flag = 0; - PrimaryCCA->PriCCA_flag = 0; - PrimaryCCA->CH_offset = 0; - PrimaryCCA->MF_state = 0; -#endif /*((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) */ -} - -VOID -odm_DynamicPrimaryCCA_Check_8814A( - IN PDM_ODM_T pDM_Odm - ) -{ - if(pDM_Odm->SupportICType != ODM_RTL8814A) - return; - - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - odm_DynamicPrimaryCCAMP_8814A(pDM_Odm); -#endif - break; - - case ODM_CE: -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - -#endif - break; - - case ODM_AP: -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#endif - break; - } - -} - - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - -VOID -odm_DynamicPrimaryCCAMP_8814A( - IN PDM_ODM_T pDM_Odm - ) -{ - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); - BOOLEAN Is40MHz = FALSE; - u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt; - u1Byte SecCHOffset; - u1Byte CurMFstate; - static u1Byte CountDown = Monitor_TIME; - - OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA; - OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail; - BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC; - BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM CCA=%d\n", OFDM_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM FA=%d\n", OFDM_FA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_USC=%d\n", BW_USC_Cnt)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_LSC=%d\n", BW_LSC_Cnt)); - Is40MHz = *(pDM_Odm->pBandWidth); - SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above - //DbgPrint("8814A: SecCHOffset = %d\n", SecCHOffset); - if(!pDM_Odm->bLinked){ - return; - } - else{ - - if(Is40MHz){ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Cont Down= %d\n", CountDown)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_Type=%d\n", PrimaryCCA->intf_type)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_flag=%d\n", PrimaryCCA->intf_flag )); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag)); - //DbgPrint("8814A RTS_EN=%d\n", pHalData->RTSEN); - - if(PrimaryCCA->PriCCA_flag == 0){ - - if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition - - if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) - && (OFDM_FA>(OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 1; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - } - else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) - && (OFDM_FA < (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 2; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_USC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - PrimaryCCA->DupRTS_flag = 1; - pHalData->RTSEN = 1; - } - else{ - - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - } - - } - else if (SecCHOffset == 1){ - - if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias)) - && (OFDM_FA > (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 1; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_LSC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - } - else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias)) - && (OFDM_FA < (OFDM_CCA>>1))){ - - PrimaryCCA->intf_type = 2; - PrimaryCCA->intf_flag = 1; - CurMFstate = MF_LSC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - PrimaryCCA->PriCCA_flag = 1; - PrimaryCCA->DupRTS_flag = 1; - pHalData->RTSEN = 1; - } - else{ - - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - } - - } - - } - else{ // PrimaryCCA->PriCCA_flag==1 - - CountDown--; - if(CountDown == 0){ - CountDown = Monitor_TIME; - PrimaryCCA->PriCCA_flag = 0; - CurMFstate = MF_USC_LSC; - odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); /* default*/ - pHalData->RTSEN = 0; - PrimaryCCA->DupRTS_flag = 0; - PrimaryCCA->intf_type = 0; - PrimaryCCA->intf_flag = 0; - } - - } - - } - else{ - - return; - } - } - -} -#endif - -u1Byte -phydm_spur_nbi_setting_8814a( - IN PDM_ODM_T pDM_Odm - ) -{ - u1Byte set_result = 0; - - /*pDM_Odm->pChannel means central frequency, so we can use 20M as input*/ - if (pDM_Odm->RFEType == 0 || pDM_Odm->RFEType == 1 || pDM_Odm->RFEType == 6 || pDM_Odm->RFEType == 7) { - /*channel asked by RF Jeff*/ - if (*pDM_Odm->pChannel == 14) - set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel >= 4 || *pDM_Odm->pChannel <= 8) - set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); - else - set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *pDM_Odm->pChannel)); - pDM_Odm->nbi_set_result = set_result; - return set_result; - -} - -VOID -phydm_dynamic_nbi_switch_8814a( - IN PDM_ODM_T pDM_Odm - ) -{ - /*if rssi < 15%, disable nbi notch filter, if rssi > 20%, enable nbi notch filter*/ - /*add by YuChen 20160218*/ - if (pDM_Odm->RFEType == 0 || pDM_Odm->RFEType == 1 || pDM_Odm->RFEType == 6 || pDM_Odm->RFEType == 7) { - if (pDM_Odm->nbi_set_result == SET_SUCCESS) { - if (pDM_Odm->RSSI_Min <= 15) - ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, 0x0); - else if (pDM_Odm->RSSI_Min >= 20) - ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, 0x1); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s\n", __func__)); - } - -} - - -VOID -phydm_hwsetting_8814a( - IN PDM_ODM_T pDM_Odm - ) -{ - phydm_dynamic_nbi_switch_8814a(pDM_Odm); -} - -#endif // RTL8814A_SUPPORT == 1 - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8814A_SUPPORT == 1) + +VOID +odm_Write_Dynamic_CCA_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurrentMFstate + ) +{ + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + + if (PrimaryCCA->MF_state != CurrentMFstate){ + + ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate); + } + + PrimaryCCA->MF_state = CurrentMFstate; + +} + +VOID +odm_PrimaryCCA_Check_Init_8814A( + IN PDM_ODM_T pDM_Odm) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->Monitor_flag = 0; + PrimaryCCA->PriCCA_flag = 0; + PrimaryCCA->CH_offset = 0; + PrimaryCCA->MF_state = 0; +#endif /*((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) */ +} + +VOID +odm_DynamicPrimaryCCA_Check_8814A( + IN PDM_ODM_T pDM_Odm + ) +{ + if(pDM_Odm->SupportICType != ODM_RTL8814A) + return; + + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + odm_DynamicPrimaryCCAMP_8814A(pDM_Odm); +#endif + break; + + case ODM_CE: +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + +#endif + break; + + case ODM_AP: +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#endif + break; + } + +} + + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + +VOID +odm_DynamicPrimaryCCAMP_8814A( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); + BOOLEAN Is40MHz = FALSE; + u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt; + u1Byte SecCHOffset; + u1Byte CurMFstate; + static u1Byte CountDown = Monitor_TIME; + + OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA; + OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail; + BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC; + BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM CCA=%d\n", OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM FA=%d\n", OFDM_FA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_USC=%d\n", BW_USC_Cnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_LSC=%d\n", BW_LSC_Cnt)); + Is40MHz = *(pDM_Odm->pBandWidth); + SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above + //DbgPrint("8814A: SecCHOffset = %d\n", SecCHOffset); + if(!pDM_Odm->bLinked){ + return; + } + else{ + + if(Is40MHz){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Cont Down= %d\n", CountDown)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_Type=%d\n", PrimaryCCA->intf_type)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_flag=%d\n", PrimaryCCA->intf_flag )); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag)); + //DbgPrint("8814A RTS_EN=%d\n", pHalData->RTSEN); + + if(PrimaryCCA->PriCCA_flag == 0){ + + if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition + + if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) + && (OFDM_FA>(OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 1; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + } + else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias)) + && (OFDM_FA < (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 2; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_USC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + PrimaryCCA->DupRTS_flag = 1; + pHalData->RTSEN = 1; + } + else{ + + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + } + + } + else if (SecCHOffset == 1){ + + if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias)) + && (OFDM_FA > (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 1; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_LSC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + } + else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias)) + && (OFDM_FA < (OFDM_CCA>>1))){ + + PrimaryCCA->intf_type = 2; + PrimaryCCA->intf_flag = 1; + CurMFstate = MF_LSC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + PrimaryCCA->PriCCA_flag = 1; + PrimaryCCA->DupRTS_flag = 1; + pHalData->RTSEN = 1; + } + else{ + + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + } + + } + + } + else{ // PrimaryCCA->PriCCA_flag==1 + + CountDown--; + if(CountDown == 0){ + CountDown = Monitor_TIME; + PrimaryCCA->PriCCA_flag = 0; + CurMFstate = MF_USC_LSC; + odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); /* default*/ + pHalData->RTSEN = 0; + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->intf_flag = 0; + } + + } + + } + else{ + + return; + } + } + +} +#endif + +u1Byte +phydm_spur_nbi_setting_8814a( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte set_result = 0; + + /*pDM_Odm->pChannel means central frequency, so we can use 20M as input*/ + if (pDM_Odm->RFEType == 0 || pDM_Odm->RFEType == 1 || pDM_Odm->RFEType == 6 || pDM_Odm->RFEType == 7) { + /*channel asked by RF Jeff*/ + if (*pDM_Odm->pChannel == 14) + set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel >= 4 || *pDM_Odm->pChannel <= 8) + set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); + else + set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *pDM_Odm->pChannel)); + pDM_Odm->nbi_set_result = set_result; + return set_result; + +} + +VOID +phydm_dynamic_nbi_switch_8814a( + IN PDM_ODM_T pDM_Odm + ) +{ + /*if rssi < 15%, disable nbi notch filter, if rssi > 20%, enable nbi notch filter*/ + /*add by YuChen 20160218*/ + if (pDM_Odm->RFEType == 0 || pDM_Odm->RFEType == 1 || pDM_Odm->RFEType == 6 || pDM_Odm->RFEType == 7) { + if (pDM_Odm->nbi_set_result == SET_SUCCESS) { + if (pDM_Odm->RSSI_Min <= 15) + ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, 0x0); + else if (pDM_Odm->RSSI_Min >= 20) + ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, 0x1); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s\n", __func__)); + } + +} + + +VOID +phydm_hwsetting_8814a( + IN PDM_ODM_T pDM_Odm + ) +{ + phydm_dynamic_nbi_switch_8814a(pDM_Odm); +} + +#endif // RTL8814A_SUPPORT == 1 + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.h b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.h index c2c359c1db9..f5ca8c1f31e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8814a/phydm_rtl8814a.h @@ -1,65 +1,65 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_RTL8814A_H__ -#define __ODM_RTL8814A_H__ - -#define OFDMCCA_TH 500 -#define BW_Ind_Bias 500 -#define MF_USC 2 -#define MF_LSC 1 -#define MF_USC_LSC 0 -#define Monitor_TIME 30 - -VOID -odm_Write_Dynamic_CCA_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte CurrentMFstate - ); - -VOID -odm_PrimaryCCA_Check_Init_8814A( - IN PDM_ODM_T pDM_Odm - ); - -VOID -odm_DynamicPrimaryCCA_Check_8814A( - IN PDM_ODM_T pDM_Odm - ); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_DynamicPrimaryCCAMP_8814A( - IN PDM_ODM_T pDM_Odm - ); - -#endif - -u1Byte -phydm_spur_nbi_setting_8814a( - IN PDM_ODM_T pDM_Odm -); - -VOID -phydm_hwsetting_8814a( - IN PDM_ODM_T pDM_Odm -); - -#endif +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8814A_H__ +#define __ODM_RTL8814A_H__ + +#define OFDMCCA_TH 500 +#define BW_Ind_Bias 500 +#define MF_USC 2 +#define MF_LSC 1 +#define MF_USC_LSC 0 +#define Monitor_TIME 30 + +VOID +odm_Write_Dynamic_CCA_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte CurrentMFstate + ); + +VOID +odm_PrimaryCCA_Check_Init_8814A( + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_DynamicPrimaryCCA_Check_8814A( + IN PDM_ODM_T pDM_Odm + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_DynamicPrimaryCCAMP_8814A( + IN PDM_ODM_T pDM_Odm + ); + +#endif + +u1Byte +phydm_spur_nbi_setting_8814a( + IN PDM_ODM_T pDM_Odm +); + +VOID +phydm_hwsetting_8814a( + IN PDM_ODM_T pDM_Odm +); + +#endif diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.c index 718a407d55f..2612bb6e122 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.c @@ -1,929 +1,929 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_AGC_TAB[] = { - 0x81C, 0xBF000001, - 0x81C, 0xBF020001, - 0x81C, 0xBF040001, - 0x81C, 0xBF060001, - 0x81C, 0xBE080001, - 0x81C, 0xBD0A0001, - 0x81C, 0xBC0C0001, - 0x81C, 0xBA0E0001, - 0x81C, 0xB9100001, - 0x81C, 0xB8120001, - 0x81C, 0xB7140001, - 0x81C, 0xB6160001, - 0x81C, 0xB5180001, - 0x81C, 0xB41A0001, - 0x81C, 0xB31C0001, - 0x81C, 0xB21E0001, - 0x81C, 0xB1200001, - 0x81C, 0xB0220001, - 0x81C, 0xAF240001, - 0x81C, 0xAE260001, - 0x81C, 0xAD280001, - 0x81C, 0xAC2A0001, - 0x81C, 0xAB2C0001, - 0x81C, 0xAA2E0001, - 0x81C, 0xA9300001, - 0x81C, 0xA8320001, - 0x81C, 0xA7340001, - 0x81C, 0xA6360001, - 0x81C, 0xA5380001, - 0x81C, 0xA43A0001, - 0x81C, 0x683C0001, - 0x81C, 0x673E0001, - 0x81C, 0x66400001, - 0x81C, 0x65420001, - 0x81C, 0x64440001, - 0x81C, 0x63460001, - 0x81C, 0x62480001, - 0x81C, 0x614A0001, - 0x81C, 0x474C0001, - 0x81C, 0x464E0001, - 0x81C, 0x45500001, - 0x81C, 0x44520001, - 0x81C, 0x43540001, - 0x81C, 0x42560001, - 0x81C, 0x41580001, - 0x81C, 0x285A0001, - 0x81C, 0x275C0001, - 0x81C, 0x265E0001, - 0x81C, 0x25600001, - 0x81C, 0x24620001, - 0x81C, 0x0A640001, - 0x81C, 0x09660001, - 0x81C, 0x08680001, - 0x81C, 0x076A0001, - 0x81C, 0x066C0001, - 0x81C, 0x056E0001, - 0x81C, 0x04700001, - 0x81C, 0x03720001, - 0x81C, 0x02740001, - 0x81C, 0x01760001, - 0x81C, 0x01780001, - 0x81C, 0x017A0001, - 0x81C, 0x017C0001, - 0x81C, 0x017E0001, - 0x8000020c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000101, - 0x81C, 0xFA020101, - 0x81C, 0xF9040101, - 0x81C, 0xF8060101, - 0x81C, 0xF7080101, - 0x81C, 0xF60A0101, - 0x81C, 0xF50C0101, - 0x81C, 0xF40E0101, - 0x81C, 0xF3100101, - 0x81C, 0xF2120101, - 0x81C, 0xF1140101, - 0x81C, 0xF0160101, - 0x81C, 0xEF180101, - 0x81C, 0xEE1A0101, - 0x81C, 0xED1C0101, - 0x81C, 0xEC1E0101, - 0x81C, 0xEB200101, - 0x81C, 0xEA220101, - 0x81C, 0xE9240101, - 0x81C, 0xE8260101, - 0x81C, 0xE7280101, - 0x81C, 0xE62A0101, - 0x81C, 0xE52C0101, - 0x81C, 0xE42E0101, - 0x81C, 0xE3300101, - 0x81C, 0xA5320101, - 0x81C, 0xA4340101, - 0x81C, 0xA3360101, - 0x81C, 0x87380101, - 0x81C, 0x863A0101, - 0x81C, 0x853C0101, - 0x81C, 0x843E0101, - 0x81C, 0x69400101, - 0x81C, 0x68420101, - 0x81C, 0x67440101, - 0x81C, 0x66460101, - 0x81C, 0x49480101, - 0x81C, 0x484A0101, - 0x81C, 0x474C0101, - 0x81C, 0x2A4E0101, - 0x81C, 0x29500101, - 0x81C, 0x28520101, - 0x81C, 0x27540101, - 0x81C, 0x26560101, - 0x81C, 0x25580101, - 0x81C, 0x245A0101, - 0x81C, 0x235C0101, - 0x81C, 0x055E0101, - 0x81C, 0x04600101, - 0x81C, 0x03620101, - 0x81C, 0x02640101, - 0x81C, 0x01660101, - 0x81C, 0x01680101, - 0x81C, 0x016A0101, - 0x81C, 0x016C0101, - 0x81C, 0x016E0101, - 0x81C, 0x01700101, - 0x81C, 0x01720101, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000101, - 0x81C, 0xFA020101, - 0x81C, 0xF9040101, - 0x81C, 0xF8060101, - 0x81C, 0xF7080101, - 0x81C, 0xF60A0101, - 0x81C, 0xF50C0101, - 0x81C, 0xF40E0101, - 0x81C, 0xF3100101, - 0x81C, 0xF2120101, - 0x81C, 0xF1140101, - 0x81C, 0xF0160101, - 0x81C, 0xEF180101, - 0x81C, 0xEE1A0101, - 0x81C, 0xED1C0101, - 0x81C, 0xEC1E0101, - 0x81C, 0xEB200101, - 0x81C, 0xEA220101, - 0x81C, 0xE9240101, - 0x81C, 0xE8260101, - 0x81C, 0xE7280101, - 0x81C, 0xE62A0101, - 0x81C, 0xE52C0101, - 0x81C, 0xE42E0101, - 0x81C, 0xE3300101, - 0x81C, 0xA5320101, - 0x81C, 0xA4340101, - 0x81C, 0xA3360101, - 0x81C, 0x87380101, - 0x81C, 0x863A0101, - 0x81C, 0x853C0101, - 0x81C, 0x843E0101, - 0x81C, 0x69400101, - 0x81C, 0x68420101, - 0x81C, 0x67440101, - 0x81C, 0x66460101, - 0x81C, 0x49480101, - 0x81C, 0x484A0101, - 0x81C, 0x474C0101, - 0x81C, 0x2A4E0101, - 0x81C, 0x29500101, - 0x81C, 0x28520101, - 0x81C, 0x27540101, - 0x81C, 0x26560101, - 0x81C, 0x25580101, - 0x81C, 0x245A0101, - 0x81C, 0x235C0101, - 0x81C, 0x055E0101, - 0x81C, 0x04600101, - 0x81C, 0x03620101, - 0x81C, 0x02640101, - 0x81C, 0x01660101, - 0x81C, 0x01680101, - 0x81C, 0x016A0101, - 0x81C, 0x016C0101, - 0x81C, 0x016E0101, - 0x81C, 0x01700101, - 0x81C, 0x01720101, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000101, - 0x81C, 0xFF020101, - 0x81C, 0xFE040101, - 0x81C, 0xFD060101, - 0x81C, 0xFC080101, - 0x81C, 0xFD0A0101, - 0x81C, 0xFC0C0101, - 0x81C, 0xFB0E0101, - 0x81C, 0xFA100101, - 0x81C, 0xF9120101, - 0x81C, 0xF8140101, - 0x81C, 0xF7160101, - 0x81C, 0xF6180101, - 0x81C, 0xF51A0101, - 0x81C, 0xF41C0101, - 0x81C, 0xF31E0101, - 0x81C, 0xF2200101, - 0x81C, 0xF1220101, - 0x81C, 0xF0240101, - 0x81C, 0xEF260101, - 0x81C, 0xEE280101, - 0x81C, 0xED2A0101, - 0x81C, 0xEC2C0101, - 0x81C, 0xEB2E0101, - 0x81C, 0xEA300101, - 0x81C, 0xE9320101, - 0x81C, 0xE8340101, - 0x81C, 0xE7360101, - 0x81C, 0xE6380101, - 0x81C, 0xE53A0101, - 0x81C, 0xE43C0101, - 0x81C, 0xE33E0101, - 0x81C, 0xA5400101, - 0x81C, 0xA4420101, - 0x81C, 0xA3440101, - 0x81C, 0x87460101, - 0x81C, 0x86480101, - 0x81C, 0x854A0101, - 0x81C, 0x844C0101, - 0x81C, 0x694E0101, - 0x81C, 0x68500101, - 0x81C, 0x67520101, - 0x81C, 0x66540101, - 0x81C, 0x49560101, - 0x81C, 0x48580101, - 0x81C, 0x475A0101, - 0x81C, 0x2A5C0101, - 0x81C, 0x295E0101, - 0x81C, 0x28600101, - 0x81C, 0x27620101, - 0x81C, 0x26640101, - 0x81C, 0x25660101, - 0x81C, 0x24680101, - 0x81C, 0x236A0101, - 0x81C, 0x056C0101, - 0x81C, 0x046E0101, - 0x81C, 0x03700101, - 0x81C, 0x02720101, - 0xB0000000, 0x00000000, - 0x81C, 0x01740101, - 0x81C, 0x01760101, - 0x81C, 0x01780101, - 0x81C, 0x017A0101, - 0x81C, 0x017C0101, - 0x81C, 0x017E0101, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - -}; - -void -ODM_ReadAndConfig_MP_8821A_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8821A_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8821A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8821A_AGC_TAB(void) -{ - return 59; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_PHY_REG[] = { - 0x800, 0x0020D090, - 0x804, 0x080112E0, - 0x808, 0x0E028211, - 0x80C, 0x92131111, - 0x810, 0x20101261, - 0x814, 0x020C3D10, - 0x818, 0x03A00385, - 0x820, 0x00000000, - 0x824, 0x00030FE0, - 0x828, 0x00000000, - 0x82C, 0x002081DD, - 0x830, 0x2AAAEEC8, - 0x834, 0x0037A706, - 0x838, 0x06489B44, - 0x83C, 0x0000095B, - 0x840, 0xC0000001, - 0x844, 0x40003CDE, - 0x848, 0x62103F8B, - 0x84C, 0x6CFDFFB8, - 0x850, 0x28874706, - 0x854, 0x0001520C, - 0x858, 0x8060E000, - 0x85C, 0x74210168, - 0x860, 0x6929C321, - 0x864, 0x79727432, - 0x868, 0x8CA7A314, - 0x86C, 0x888C2878, - 0x870, 0x08888888, - 0x874, 0x31612C2E, - 0x878, 0x00000152, - 0x87C, 0x000FD000, - 0x8A0, 0x00000013, - 0x8A4, 0x7F7F7F7F, - 0x8A8, 0xA2000338, - 0x8AC, 0x0FF0FA0A, - 0x8B4, 0x000FC080, - 0x8B8, 0x6C10D7FF, - 0x8BC, 0x0CA52090, - 0x8C0, 0x1BF00020, - 0x8C4, 0x00000000, - 0x8C8, 0x00013169, - 0x8CC, 0x08248492, - 0x8D4, 0x940008A0, - 0x8D8, 0x290B5612, - 0x8F8, 0x400002C0, - 0x8FC, 0x00000000, - 0x900, 0x00000700, - 0x90C, 0x00000000, - 0x910, 0x0000FC00, - 0x914, 0x00000404, - 0x918, 0x1C1028C0, - 0x91C, 0x64B11A1C, - 0x920, 0xE0767233, - 0x924, 0x055AA500, - 0x928, 0x00000004, - 0x92C, 0xFFFE0000, - 0x930, 0xFFFFFFFE, - 0x934, 0x001FFFFF, - 0x960, 0x00000000, - 0x964, 0x00000000, - 0x968, 0x00000000, - 0x96C, 0x00000000, - 0x970, 0x801FFFFF, - 0x974, 0x000003FF, - 0x978, 0x00000000, - 0x97C, 0x00000000, - 0x980, 0x00000000, - 0x984, 0x00000000, - 0x988, 0x00000000, - 0x990, 0x27100000, - 0x994, 0xFFFF0100, - 0x998, 0xFFFFFF5C, - 0x99C, 0xFFFFFFFF, - 0x9A0, 0x000000FF, - 0x9A4, 0x00480080, - 0x9A8, 0x00000000, - 0x9AC, 0x00000000, - 0x9B0, 0x81081008, - 0x9B4, 0x01081008, - 0x9B8, 0x01081008, - 0x9BC, 0x01081008, - 0x9D0, 0x00000000, - 0x9D4, 0x00000000, - 0x9D8, 0x00000000, - 0x9DC, 0x00000000, - 0x9E0, 0x00005D00, - 0x9E4, 0x00000003, - 0x9E8, 0x00000001, - 0xA00, 0x00D047C8, - 0xA04, 0x01FF800C, - 0xA08, 0x8C8A8300, - 0xA0C, 0x2E68000F, - 0xA10, 0x9500BB78, - 0xA14, 0x11144028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0x1A1B0000, - 0xA24, 0x090E1317, - 0xA28, 0x00000204, - 0xA2C, 0x00900000, - 0xA70, 0x101FFF00, - 0xA74, 0x00000008, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0xA80, 0x21805490, - 0xA84, 0x001F0000, - 0xB00, 0x03100040, - 0xB04, 0x0000B000, - 0xB08, 0xAE0201EB, - 0xB0C, 0x01003207, - 0xB10, 0x00009807, - 0xB14, 0x01000000, - 0xB18, 0x00000002, - 0xB1C, 0x00000002, - 0xB20, 0x0000001F, - 0xB24, 0x03020100, - 0xB28, 0x07060504, - 0xB2C, 0x0B0A0908, - 0xB30, 0x0F0E0D0C, - 0xB34, 0x13121110, - 0xB38, 0x17161514, - 0xB3C, 0x0000003A, - 0xB40, 0x00000000, - 0xB44, 0x00000000, - 0xB48, 0x13000032, - 0xB4C, 0x48080000, - 0xB50, 0x00000000, - 0xB54, 0x00000000, - 0xB58, 0x00000000, - 0xB5C, 0x00000000, - 0xC00, 0x00000007, - 0xC04, 0x00042020, - 0xC08, 0x80410231, - 0xC0C, 0x00000000, - 0xC10, 0x00000100, - 0xC14, 0x01000000, - 0xC1C, 0x40000003, - 0xC20, 0x2C2C2C2C, - 0xC24, 0x30303030, - 0xC28, 0x30303030, - 0xC2C, 0x2C2C2C2C, - 0xC30, 0x2C2C2C2C, - 0xC34, 0x2C2C2C2C, - 0xC38, 0x2C2C2C2C, - 0xC3C, 0x2A2A2A2A, - 0xC40, 0x2A2A2A2A, - 0xC44, 0x2A2A2A2A, - 0xC48, 0x2A2A2A2A, - 0xC4C, 0x2A2A2A2A, - 0xC50, 0x00000020, - 0xC54, 0x001C1208, - 0xC58, 0x30000C1C, - 0xC5C, 0x00000058, - 0xC60, 0x34344443, - 0xC64, 0x07003333, - 0xC68, 0x19791979, - 0xC6C, 0x19791979, - 0xC70, 0x19791979, - 0xC74, 0x19791979, - 0xC78, 0x19791979, - 0xC7C, 0x19791979, - 0xC80, 0x19791979, - 0xC84, 0x19791979, - 0xC94, 0x0100005C, - 0xC98, 0x00000000, - 0xC9C, 0x00000000, - 0xCA0, 0x00000029, - 0xCA4, 0x08040201, - 0xCA8, 0x80402010, - 0xCB0, 0x77775747, - 0xCB4, 0x10000077, - 0xCB8, 0x00508240, - -}; - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8821A(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8821A_PHY_REG(void) -{ - return 59; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022 -}; - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_DNI_JP.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_PHY_REG_PG_DNI_JP[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x23232323, - 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020 -}; - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_DNI_JP)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_PHY_REG_PG_DNI_JP; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_DNI_US.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_PHY_REG_PG_DNI_US[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020 -}; - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_DNI_US)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_PHY_REG_PG_DNI_US; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_E202SA.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_PHY_REG_PG_E202SA[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x22222222, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x22222222, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x20202020, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x20202020, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x16161616, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x16161616, - 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00001616 -}; - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_E202SA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_PHY_REG_PG_E202SA; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_AGC_TAB[] = { + 0x81C, 0xBF000001, + 0x81C, 0xBF020001, + 0x81C, 0xBF040001, + 0x81C, 0xBF060001, + 0x81C, 0xBE080001, + 0x81C, 0xBD0A0001, + 0x81C, 0xBC0C0001, + 0x81C, 0xBA0E0001, + 0x81C, 0xB9100001, + 0x81C, 0xB8120001, + 0x81C, 0xB7140001, + 0x81C, 0xB6160001, + 0x81C, 0xB5180001, + 0x81C, 0xB41A0001, + 0x81C, 0xB31C0001, + 0x81C, 0xB21E0001, + 0x81C, 0xB1200001, + 0x81C, 0xB0220001, + 0x81C, 0xAF240001, + 0x81C, 0xAE260001, + 0x81C, 0xAD280001, + 0x81C, 0xAC2A0001, + 0x81C, 0xAB2C0001, + 0x81C, 0xAA2E0001, + 0x81C, 0xA9300001, + 0x81C, 0xA8320001, + 0x81C, 0xA7340001, + 0x81C, 0xA6360001, + 0x81C, 0xA5380001, + 0x81C, 0xA43A0001, + 0x81C, 0x683C0001, + 0x81C, 0x673E0001, + 0x81C, 0x66400001, + 0x81C, 0x65420001, + 0x81C, 0x64440001, + 0x81C, 0x63460001, + 0x81C, 0x62480001, + 0x81C, 0x614A0001, + 0x81C, 0x474C0001, + 0x81C, 0x464E0001, + 0x81C, 0x45500001, + 0x81C, 0x44520001, + 0x81C, 0x43540001, + 0x81C, 0x42560001, + 0x81C, 0x41580001, + 0x81C, 0x285A0001, + 0x81C, 0x275C0001, + 0x81C, 0x265E0001, + 0x81C, 0x25600001, + 0x81C, 0x24620001, + 0x81C, 0x0A640001, + 0x81C, 0x09660001, + 0x81C, 0x08680001, + 0x81C, 0x076A0001, + 0x81C, 0x066C0001, + 0x81C, 0x056E0001, + 0x81C, 0x04700001, + 0x81C, 0x03720001, + 0x81C, 0x02740001, + 0x81C, 0x01760001, + 0x81C, 0x01780001, + 0x81C, 0x017A0001, + 0x81C, 0x017C0001, + 0x81C, 0x017E0001, + 0x8000020c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000101, + 0x81C, 0xFA020101, + 0x81C, 0xF9040101, + 0x81C, 0xF8060101, + 0x81C, 0xF7080101, + 0x81C, 0xF60A0101, + 0x81C, 0xF50C0101, + 0x81C, 0xF40E0101, + 0x81C, 0xF3100101, + 0x81C, 0xF2120101, + 0x81C, 0xF1140101, + 0x81C, 0xF0160101, + 0x81C, 0xEF180101, + 0x81C, 0xEE1A0101, + 0x81C, 0xED1C0101, + 0x81C, 0xEC1E0101, + 0x81C, 0xEB200101, + 0x81C, 0xEA220101, + 0x81C, 0xE9240101, + 0x81C, 0xE8260101, + 0x81C, 0xE7280101, + 0x81C, 0xE62A0101, + 0x81C, 0xE52C0101, + 0x81C, 0xE42E0101, + 0x81C, 0xE3300101, + 0x81C, 0xA5320101, + 0x81C, 0xA4340101, + 0x81C, 0xA3360101, + 0x81C, 0x87380101, + 0x81C, 0x863A0101, + 0x81C, 0x853C0101, + 0x81C, 0x843E0101, + 0x81C, 0x69400101, + 0x81C, 0x68420101, + 0x81C, 0x67440101, + 0x81C, 0x66460101, + 0x81C, 0x49480101, + 0x81C, 0x484A0101, + 0x81C, 0x474C0101, + 0x81C, 0x2A4E0101, + 0x81C, 0x29500101, + 0x81C, 0x28520101, + 0x81C, 0x27540101, + 0x81C, 0x26560101, + 0x81C, 0x25580101, + 0x81C, 0x245A0101, + 0x81C, 0x235C0101, + 0x81C, 0x055E0101, + 0x81C, 0x04600101, + 0x81C, 0x03620101, + 0x81C, 0x02640101, + 0x81C, 0x01660101, + 0x81C, 0x01680101, + 0x81C, 0x016A0101, + 0x81C, 0x016C0101, + 0x81C, 0x016E0101, + 0x81C, 0x01700101, + 0x81C, 0x01720101, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000101, + 0x81C, 0xFA020101, + 0x81C, 0xF9040101, + 0x81C, 0xF8060101, + 0x81C, 0xF7080101, + 0x81C, 0xF60A0101, + 0x81C, 0xF50C0101, + 0x81C, 0xF40E0101, + 0x81C, 0xF3100101, + 0x81C, 0xF2120101, + 0x81C, 0xF1140101, + 0x81C, 0xF0160101, + 0x81C, 0xEF180101, + 0x81C, 0xEE1A0101, + 0x81C, 0xED1C0101, + 0x81C, 0xEC1E0101, + 0x81C, 0xEB200101, + 0x81C, 0xEA220101, + 0x81C, 0xE9240101, + 0x81C, 0xE8260101, + 0x81C, 0xE7280101, + 0x81C, 0xE62A0101, + 0x81C, 0xE52C0101, + 0x81C, 0xE42E0101, + 0x81C, 0xE3300101, + 0x81C, 0xA5320101, + 0x81C, 0xA4340101, + 0x81C, 0xA3360101, + 0x81C, 0x87380101, + 0x81C, 0x863A0101, + 0x81C, 0x853C0101, + 0x81C, 0x843E0101, + 0x81C, 0x69400101, + 0x81C, 0x68420101, + 0x81C, 0x67440101, + 0x81C, 0x66460101, + 0x81C, 0x49480101, + 0x81C, 0x484A0101, + 0x81C, 0x474C0101, + 0x81C, 0x2A4E0101, + 0x81C, 0x29500101, + 0x81C, 0x28520101, + 0x81C, 0x27540101, + 0x81C, 0x26560101, + 0x81C, 0x25580101, + 0x81C, 0x245A0101, + 0x81C, 0x235C0101, + 0x81C, 0x055E0101, + 0x81C, 0x04600101, + 0x81C, 0x03620101, + 0x81C, 0x02640101, + 0x81C, 0x01660101, + 0x81C, 0x01680101, + 0x81C, 0x016A0101, + 0x81C, 0x016C0101, + 0x81C, 0x016E0101, + 0x81C, 0x01700101, + 0x81C, 0x01720101, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000101, + 0x81C, 0xFF020101, + 0x81C, 0xFE040101, + 0x81C, 0xFD060101, + 0x81C, 0xFC080101, + 0x81C, 0xFD0A0101, + 0x81C, 0xFC0C0101, + 0x81C, 0xFB0E0101, + 0x81C, 0xFA100101, + 0x81C, 0xF9120101, + 0x81C, 0xF8140101, + 0x81C, 0xF7160101, + 0x81C, 0xF6180101, + 0x81C, 0xF51A0101, + 0x81C, 0xF41C0101, + 0x81C, 0xF31E0101, + 0x81C, 0xF2200101, + 0x81C, 0xF1220101, + 0x81C, 0xF0240101, + 0x81C, 0xEF260101, + 0x81C, 0xEE280101, + 0x81C, 0xED2A0101, + 0x81C, 0xEC2C0101, + 0x81C, 0xEB2E0101, + 0x81C, 0xEA300101, + 0x81C, 0xE9320101, + 0x81C, 0xE8340101, + 0x81C, 0xE7360101, + 0x81C, 0xE6380101, + 0x81C, 0xE53A0101, + 0x81C, 0xE43C0101, + 0x81C, 0xE33E0101, + 0x81C, 0xA5400101, + 0x81C, 0xA4420101, + 0x81C, 0xA3440101, + 0x81C, 0x87460101, + 0x81C, 0x86480101, + 0x81C, 0x854A0101, + 0x81C, 0x844C0101, + 0x81C, 0x694E0101, + 0x81C, 0x68500101, + 0x81C, 0x67520101, + 0x81C, 0x66540101, + 0x81C, 0x49560101, + 0x81C, 0x48580101, + 0x81C, 0x475A0101, + 0x81C, 0x2A5C0101, + 0x81C, 0x295E0101, + 0x81C, 0x28600101, + 0x81C, 0x27620101, + 0x81C, 0x26640101, + 0x81C, 0x25660101, + 0x81C, 0x24680101, + 0x81C, 0x236A0101, + 0x81C, 0x056C0101, + 0x81C, 0x046E0101, + 0x81C, 0x03700101, + 0x81C, 0x02720101, + 0xB0000000, 0x00000000, + 0x81C, 0x01740101, + 0x81C, 0x01760101, + 0x81C, 0x01780101, + 0x81C, 0x017A0101, + 0x81C, 0x017C0101, + 0x81C, 0x017E0101, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + +}; + +void +ODM_ReadAndConfig_MP_8821A_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8821A_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8821A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8821A_AGC_TAB(void) +{ + return 59; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_PHY_REG[] = { + 0x800, 0x0020D090, + 0x804, 0x080112E0, + 0x808, 0x0E028211, + 0x80C, 0x92131111, + 0x810, 0x20101261, + 0x814, 0x020C3D10, + 0x818, 0x03A00385, + 0x820, 0x00000000, + 0x824, 0x00030FE0, + 0x828, 0x00000000, + 0x82C, 0x002081DD, + 0x830, 0x2AAAEEC8, + 0x834, 0x0037A706, + 0x838, 0x06489B44, + 0x83C, 0x0000095B, + 0x840, 0xC0000001, + 0x844, 0x40003CDE, + 0x848, 0x62103F8B, + 0x84C, 0x6CFDFFB8, + 0x850, 0x28874706, + 0x854, 0x0001520C, + 0x858, 0x8060E000, + 0x85C, 0x74210168, + 0x860, 0x6929C321, + 0x864, 0x79727432, + 0x868, 0x8CA7A314, + 0x86C, 0x888C2878, + 0x870, 0x08888888, + 0x874, 0x31612C2E, + 0x878, 0x00000152, + 0x87C, 0x000FD000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0xA2000338, + 0x8AC, 0x0FF0FA0A, + 0x8B4, 0x000FC080, + 0x8B8, 0x6C10D7FF, + 0x8BC, 0x0CA52090, + 0x8C0, 0x1BF00020, + 0x8C4, 0x00000000, + 0x8C8, 0x00013169, + 0x8CC, 0x08248492, + 0x8D4, 0x940008A0, + 0x8D8, 0x290B5612, + 0x8F8, 0x400002C0, + 0x8FC, 0x00000000, + 0x900, 0x00000700, + 0x90C, 0x00000000, + 0x910, 0x0000FC00, + 0x914, 0x00000404, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x055AA500, + 0x928, 0x00000004, + 0x92C, 0xFFFE0000, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x801FFFFF, + 0x974, 0x000003FF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x00480080, + 0x9A8, 0x00000000, + 0x9AC, 0x00000000, + 0x9B0, 0x81081008, + 0x9B4, 0x01081008, + 0x9B8, 0x01081008, + 0x9BC, 0x01081008, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E0, 0x00005D00, + 0x9E4, 0x00000003, + 0x9E8, 0x00000001, + 0xA00, 0x00D047C8, + 0xA04, 0x01FF800C, + 0xA08, 0x8C8A8300, + 0xA0C, 0x2E68000F, + 0xA10, 0x9500BB78, + 0xA14, 0x11144028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA2C, 0x00900000, + 0xA70, 0x101FFF00, + 0xA74, 0x00000008, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x21805490, + 0xA84, 0x001F0000, + 0xB00, 0x03100040, + 0xB04, 0x0000B000, + 0xB08, 0xAE0201EB, + 0xB0C, 0x01003207, + 0xB10, 0x00009807, + 0xB14, 0x01000000, + 0xB18, 0x00000002, + 0xB1C, 0x00000002, + 0xB20, 0x0000001F, + 0xB24, 0x03020100, + 0xB28, 0x07060504, + 0xB2C, 0x0B0A0908, + 0xB30, 0x0F0E0D0C, + 0xB34, 0x13121110, + 0xB38, 0x17161514, + 0xB3C, 0x0000003A, + 0xB40, 0x00000000, + 0xB44, 0x00000000, + 0xB48, 0x13000032, + 0xB4C, 0x48080000, + 0xB50, 0x00000000, + 0xB54, 0x00000000, + 0xB58, 0x00000000, + 0xB5C, 0x00000000, + 0xC00, 0x00000007, + 0xC04, 0x00042020, + 0xC08, 0x80410231, + 0xC0C, 0x00000000, + 0xC10, 0x00000100, + 0xC14, 0x01000000, + 0xC1C, 0x40000003, + 0xC20, 0x2C2C2C2C, + 0xC24, 0x30303030, + 0xC28, 0x30303030, + 0xC2C, 0x2C2C2C2C, + 0xC30, 0x2C2C2C2C, + 0xC34, 0x2C2C2C2C, + 0xC38, 0x2C2C2C2C, + 0xC3C, 0x2A2A2A2A, + 0xC40, 0x2A2A2A2A, + 0xC44, 0x2A2A2A2A, + 0xC48, 0x2A2A2A2A, + 0xC4C, 0x2A2A2A2A, + 0xC50, 0x00000020, + 0xC54, 0x001C1208, + 0xC58, 0x30000C1C, + 0xC5C, 0x00000058, + 0xC60, 0x34344443, + 0xC64, 0x07003333, + 0xC68, 0x19791979, + 0xC6C, 0x19791979, + 0xC70, 0x19791979, + 0xC74, 0x19791979, + 0xC78, 0x19791979, + 0xC7C, 0x19791979, + 0xC80, 0x19791979, + 0xC84, 0x19791979, + 0xC94, 0x0100005C, + 0xC98, 0x00000000, + 0xC9C, 0x00000000, + 0xCA0, 0x00000029, + 0xCA4, 0x08040201, + 0xCA8, 0x80402010, + 0xCB0, 0x77775747, + 0xCB4, 0x10000077, + 0xCB8, 0x00508240, + +}; + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8821A(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8821A_PHY_REG(void) +{ + return 59; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_PHY_REG_PG[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022 +}; + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_DNI_JP.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_PHY_REG_PG_DNI_JP[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x23232323, + 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020 +}; + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_DNI_JP)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_PHY_REG_PG_DNI_JP; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_DNI_US.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_PHY_REG_PG_DNI_US[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020 +}; + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_DNI_US)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_PHY_REG_PG_DNI_US; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_E202SA.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_PHY_REG_PG_E202SA[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x22222222, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x22222222, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x20202020, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x20202020, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x16161616, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x16161616, + 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00001616 +}; + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_PHY_REG_PG_E202SA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_PHY_REG_PG_E202SA; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8821A(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.h index f162dfff988..3a17afc199c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_bb.h @@ -1,89 +1,89 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8821A_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8821A_H -#define __INC_MP_BB_HW_IMG_8821A_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG(void); - -/****************************************************************************** -* PHY_REG_PG_DNI_JP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_DNI_JP(void); - -/****************************************************************************** -* PHY_REG_PG_DNI_US.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_DNI_US(void); - -/****************************************************************************** -* PHY_REG_PG_E202SA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_E202SA(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8821A_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8821A_H +#define __INC_MP_BB_HW_IMG_8821A_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG(void); + +/****************************************************************************** +* PHY_REG_PG_DNI_JP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_JP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_DNI_JP(void); + +/****************************************************************************** +* PHY_REG_PG_DNI_US.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_DNI_US(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_DNI_US(void); + +/****************************************************************************** +* PHY_REG_PG_E202SA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_PHY_REG_PG_E202SA(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.c index 870283b445c..025c69d7c73 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.c @@ -1,7007 +1,7007 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#include "../../rtl8812a/hal8821a_fw.h" -#else -#include "../../rtl8821a/hal8821a_fw.h" -#endif -#endif - - -#if (RTL8821A_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8821A_FW_AP[] = { -0x01, 0x21, 0x20, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x06, 0xE2, 0x42, 0x00, 0x00, -0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 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*)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_AP; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_AP, ArrayLength_MP_8821A_FW_AP); -#endif - *pFirmwareSize = ArrayLength_MP_8821A_FW_AP; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8821A_FW_NIC[] = { -0x01, 0x21, 0x10, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x05, 0x94, 0x7C, 0x00, 0x00, -0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x49, 0x62, 0x02, 0x67, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x68, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x78, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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-ODM_ReadFirmware_MP_8821A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_NIC, ArrayLength_MP_8821A_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8821A_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8821A_FW_NIC_BT[] = { -0x01, 0x21, 0x13, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x06, 0x2E, 0x7E, 0x00, 0x00, -0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x48, 0x7E, 0x02, 0x77, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x78, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x02, 0x8B, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x4F, 0x7A, 0x93, 0x79, 0x90, 0x22, 0x90, 0x93, 0xA9, 0xE4, 0x75, 0xF0, 0x02, -0x22, 0x90, 0x93, 0x88, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x8E, 0x15, 0xE0, 0xC4, 0x54, 0x0F, -0x22, 0x90, 0x8D, 0xFD, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01, -0x22, 0x12, 0x4A, 0xCD, 0x90, 0x95, 0xB4, 0xE0, 0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, -0x22, 0x90, 0x95, 0xA9, 0xE0, 0xFF, 0x7D, 0x48, 0x22, 0x00, 0x62, 0x7A, -}; -u4Byte ArrayLength_MP_8821A_FW_WoWLAN = 28460; - -#endif - -void -ODM_ReadFirmware_MP_8821A_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_WoWLAN, ArrayLength_MP_8821A_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8821A_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#include "../../rtl8812a/hal8821a_fw.h" +#else +#include "../../rtl8821a/hal8821a_fw.h" +#endif +#endif + + +#if (RTL8821A_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8821A_FW_AP[] = { +0x01, 0x21, 0x20, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x06, 0xE2, 0x42, 0x00, 0x00, +0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 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*)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_AP, ArrayLength_MP_8821A_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8821A_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8821A_FW_NIC[] = { +0x01, 0x21, 0x10, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x05, 0x94, 0x7C, 0x00, 0x00, +0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x49, 0x62, 0x02, 0x67, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x68, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x78, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+ODM_ReadFirmware_MP_8821A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_NIC, ArrayLength_MP_8821A_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8821A_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8821A_FW_NIC_BT[] = { +0x01, 0x21, 0x13, 0x00, 0x27, 0x00, 0x01, 0x00, 0x02, 0x25, 0x17, 0x06, 0x2E, 0x7E, 0x00, 0x00, +0x92, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x48, 0x7E, 0x02, 0x77, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x78, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0x8B, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x7E, 0x08, 0x02, 0x38, 0x07, 0x7F, 0x00, +0x7E, 0x0E, 0x02, 0x38, 0x07, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x6F, 0xFF, 0x22, 0x90, 0x9F, 0xDC, +0xE0, 0x90, 0x05, 0x73, 0x22, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x51, 0x08, 0x22, 0x93, 0xFD, 0x7C, +0x00, 0x02, 0x07, 0x03, 0x7D, 0x00, 0x25, 0xE0, 0x25, 0xE0, 0xFC, 0x22, 0x90, 0x05, 0x00, 0x74, +0x1C, 0xF0, 0xA3, 0x22, 0x4D, 0xFF, 0x90, 0xA0, 0x38, 0xF0, 0xEE, 0x22, 0x90, 0xBB, +}; +u4Byte ArrayLength_MP_8821A_FW_NIC_BT = 32334; + +#endif + +void +ODM_ReadFirmware_MP_8821A_FW_NIC_BT( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_NIC_BT; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_NIC_BT, ArrayLength_MP_8821A_FW_NIC_BT); +#endif + *pFirmwareSize = ArrayLength_MP_8821A_FW_NIC_BT; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8821A_FW_WoWLAN[] = { +0x01, 0x21, 0x30, 0x00, 0x27, 0x00, 0x01, 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0xFA, 0x7B, 0x01, 0x22, 0x78, 0x10, 0x12, +0x08, 0x47, 0x90, 0x95, 0x35, 0x12, 0x48, 0x2E, 0x02, 0x47, 0x8D, 0x75, 0xF0, 0x20, 0xA4, 0x24, +0x58, 0xF9, 0x74, 0x91, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0x22, 0xFD, 0xE4, 0x33, 0x90, 0x95, 0x39, +0xF0, 0xA3, 0x22, 0x7F, 0x00, 0x7E, 0x0C, 0x12, 0x38, 0x07, 0x7F, 0x00, 0x7E, 0x0E, 0x22, 0x90, +0x93, 0x89, 0xA3, 0xE0, 0x24, 0x01, 0x22, 0x90, 0x02, 0x86, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0xF0, +0x90, 0x93, 0xA6, 0xE0, 0x04, 0xF0, 0x22, 0x74, 0x21, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, +0x83, 0xE0, 0x22, 0x24, 0x30, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x22, 0x24, 0x42, 0xF9, +0xE4, 0x34, 0xFC, 0x22, 0x12, 0x24, 0xE6, 0x90, 0x95, 0x35, 0x02, 0x08, 0x6D, 0x75, 0x41, 0x8F, +0x75, 0x42, 0x93, 0x75, 0x43, 0x02, 0x22, 0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x4E, +0x22, 0x90, 0x95, 0x2F, 0xA3, 0xE0, 0xFF, 0x22, 0x74, 0x20, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x91, +0x22, 0x90, 0x94, 0xB6, 0xE0, 0x90, 0x95, 0x90, 0xF0, 0x22, 0xE0, 0x24, 0x90, 0xF5, 0x82, 0xE4, +0x34, 0x93, 0x22, 0x90, 0x93, 0xA6, 0xE0, 0xFF, 0xC3, 0x94, 0x10, 0x22, 0x90, 0x94, 0xC8, 0xE0, +0xFC, 0xA3, 0xE0, 0xFD, 0x22, 0x90, 0x94, 0xCA, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x90, 0x95, +0x33, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x22, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x4A, 0x04, 0xEF, 0x22, +0x7F, 0xB4, 0x7E, 0x08, 0x12, 0x37, 0xBC, 0xEF, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, +0x83, 0x22, 0xF0, 0x7F, 0x10, 0x7E, 0x00, 0x02, 0x3D, 0x7A, 0x7F, 0x00, 0x7E, 0x0E, 0x02, 0x38, +0x07, 0xFE, 0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x22, 0xFE, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, +0x22, 0x90, 0x8D, 0xFA, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x8E, 0x7B, 0xE0, 0xC4, 0x54, 0x0F, +0x22, 0xF5, 0x82, 0xE4, 0x34, 0x91, 0xF5, 0x83, 0x22, 0xE4, 0x90, 0x93, 0x9C, 0xF0, 0x7F, 0x04, +0x22, 0x90, 0x94, 0x46, 0xEE, 0xF0, 0xA3, 0xEF, 0x22, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x54, 0x03, +0x22, 0x90, 0x94, 0x30, 0xE0, 0xC3, 0x94, 0x0A, 0x22, 0x74, 0x10, 0xF0, 0x7A, 0x8F, 0x79, 0x4C, +0x22, 0x12, 0x48, 0x4F, 0x7A, 0x93, 0x79, 0x90, 0x22, 0x90, 0x93, 0xA9, 0xE4, 0x75, 0xF0, 0x02, +0x22, 0x90, 0x93, 0x88, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x8E, 0x15, 0xE0, 0xC4, 0x54, 0x0F, +0x22, 0x90, 0x8D, 0xFD, 0xE0, 0xFF, 0xC3, 0x13, 0x22, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01, +0x22, 0x12, 0x4A, 0xCD, 0x90, 0x95, 0xB4, 0xE0, 0x22, 0x2F, 0xF8, 0xE6, 0xFE, 0xED, 0xF4, 0x5E, +0x22, 0x90, 0x95, 0xA9, 0xE0, 0xFF, 0x7D, 0x48, 0x22, 0x00, 0x62, 0x7A, +}; +u4Byte ArrayLength_MP_8821A_FW_WoWLAN = 28460; + +#endif + +void +ODM_ReadFirmware_MP_8821A_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8821A_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8821A_FW_WoWLAN, ArrayLength_MP_8821A_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8821A_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.h index 324781b578f..c2d37f08970 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_fw.h @@ -1,73 +1,73 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8821A_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8821A_H -#define __INC_MP_FW_HW_IMG_8821A_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8821A_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8821A_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC_BT.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8821A_FW_NIC_BT( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8821A_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8821A_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8821A_H +#define __INC_MP_FW_HW_IMG_8821A_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8821A_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8821A_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC_BT.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8821A_FW_NIC_BT( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8821A_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.c index b9e8be81fb9..59485fe06a8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.c @@ -1,285 +1,285 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_MAC_REG[] = { - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x00000000, - 0x446, 0x00000000, - 0x447, 0x00000000, - 0x448, 0x00000000, - 0x449, 0x000000F0, - 0x44A, 0x0000000F, - 0x44B, 0x0000003E, - 0x44C, 0x00000010, - 0x44D, 0x00000000, - 0x44E, 0x00000000, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x000000F0, - 0x452, 0x0000000F, - 0x453, 0x00000000, - 0x456, 0x0000005E, - 0x460, 0x00000066, - 0x461, 0x00000066, - 0x4C8, 0x0000003F, - 0x4C9, 0x000000FF, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x525, 0x0000004F, - 0x550, 0x00000010, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x605, 0x00000030, - 0x607, 0x00000007, - 0x608, 0x0000000E, - 0x609, 0x0000002A, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x718, 0x00000040, - -}; - -void -ODM_ReadAndConfig_MP_8821A_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8821A_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8821A(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8821A_MAC_REG(void) -{ - return 59; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_MAC_REG[] = { + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x4C8, 0x0000003F, + 0x4C9, 0x000000FF, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x607, 0x00000007, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + +}; + +void +ODM_ReadAndConfig_MP_8821A_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8821A_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8821A(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8821A_MAC_REG(void) +{ + return 59; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.h index 4a16a1d1331..48f7222654f 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8821A_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8821A_H -#define __INC_MP_MAC_HW_IMG_8821A_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8821A_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8821A_H +#define __INC_MP_MAC_HW_IMG_8821A_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.c index dcf269e6b63..1c91887b72d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.c @@ -1,5463 +1,5463 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821A_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8821A_RadioA[] = { - 0x018, 0x0001712A, - 0x056, 0x00051CF2, - 0x066, 0x00040000, - 0x000, 0x00010000, - 0x01E, 0x00080000, - 0x082, 0x00000830, - 0x083, 0x00021800, - 0x084, 0x00028000, - 0x085, 0x00048000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x086, 0x0009483A, - 0xA0000000, 0x00000000, - 0x086, 0x00094838, - 0xB0000000, 0x00000000, - 0x087, 0x00044980, - 0x088, 0x00048000, - 0x089, 0x0000D480, - 0x08A, 0x00042240, - 0x08B, 0x000F0380, - 0x08C, 0x00090000, - 0x08D, 0x00022852, - 0x08E, 0x00065540, - 0x08F, 0x00088001, - 0x0EF, 0x00020000, - 0x03E, 0x00000380, - 0x03F, 0x00090018, - 0x03E, 0x00020380, - 0x03F, 0x000A0018, - 0x03E, 0x00040308, - 0x03F, 0x000A0018, - 0x03E, 0x00060018, - 0x03F, 0x000A0018, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x089, 0x00000080, - 0x08B, 0x00080180, - 0x0EF, 0x00001000, - 0x03A, 0x00000244, - 0x03B, 0x00038027, - 0x03C, 0x00082000, - 0x03A, 0x00000244, - 0x03B, 0x00030113, - 0x03C, 0x00082000, - 0x03A, 0x0000014C, - 0x03B, 0x00028027, - 0x03C, 0x00082000, - 0x03A, 0x000000CC, - 0x03B, 0x00027027, - 0x03C, 0x00042000, - 0x03A, 0x0000014C, - 0x03B, 0x0001F913, - 0x03C, 0x00042000, - 0x03A, 0x0000010C, - 0x03B, 0x00017F10, - 0x03C, 0x00012000, - 0x03A, 0x000000D0, - 0x03B, 0x00008027, - 0x03C, 0x000CA000, - 0x03A, 0x00000244, - 0x03B, 0x00078027, - 0x03C, 0x00082000, - 0x03A, 0x00000244, - 0x03B, 0x00070113, - 0x03C, 0x00082000, - 0x03A, 0x0000014C, - 0x03B, 0x00068027, - 0x03C, 0x00082000, - 0x03A, 0x000000CC, - 0x03B, 0x00067027, - 0x03C, 0x00042000, - 0x03A, 0x0000014C, - 0x03B, 0x0005F913, - 0x03C, 0x00042000, - 0x03A, 0x0000010C, - 0x03B, 0x00057F10, - 0x03C, 0x00012000, - 0x03A, 0x000000D0, - 0x03B, 0x00048027, - 0x03C, 0x000CA000, - 0x03A, 0x00000244, - 0x03B, 0x000B8027, - 0x03C, 0x00082000, - 0x03A, 0x00000244, - 0x03B, 0x000B0113, - 0x03C, 0x00082000, - 0x03A, 0x0000014C, - 0x03B, 0x000A8027, - 0x03C, 0x00082000, - 0x03A, 0x000000CC, - 0x03B, 0x000A7027, - 0x03C, 0x00042000, - 0x03A, 0x0000014C, - 0x03B, 0x0009F913, - 0x03C, 0x00042000, - 0x03A, 0x0000010C, - 0x03B, 0x00097F10, - 0x03C, 0x00012000, - 0x03A, 0x000000D0, - 0x03B, 0x00088027, - 0x03C, 0x000CA000, - 0x0EF, 0x00000000, - 0x0EF, 0x00001100, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004ADF3, - 0x034, 0x00049DF0, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004ADF3, - 0x034, 0x00049DF0, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004ADF5, - 0x034, 0x00049DF2, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0F3, - 0x034, 0x000490B1, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004A0F3, - 0x034, 0x000490B1, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004ADF5, - 0x034, 0x00049DF2, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0004ADF3, - 0x034, 0x00049DF0, - 0xA0000000, 0x00000000, - 0x034, 0x0004ADF7, - 0x034, 0x00049DF3, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00048DED, - 0x034, 0x00047DEA, - 0x034, 0x00046DE7, - 0x034, 0x00045CE9, - 0x034, 0x00044CE6, - 0x034, 0x000438C6, - 0x034, 0x00042886, - 0x034, 0x00041486, - 0x034, 0x00040447, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00048DED, - 0x034, 0x00047DEA, - 0x034, 0x00046DE7, - 0x034, 0x00045CE9, - 0x034, 0x00044CE6, - 0x034, 0x000438C6, - 0x034, 0x00042886, - 0x034, 0x00041486, - 0x034, 0x00040447, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000480AE, - 0x034, 0x000470AB, - 0x034, 0x0004608B, - 0x034, 0x00045069, - 0x034, 0x00044048, - 0x034, 0x00043045, - 0x034, 0x00042026, - 0x034, 0x00041023, - 0x034, 0x00040002, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000480AE, - 0x034, 0x000470AB, - 0x034, 0x0004608B, - 0x034, 0x00045069, - 0x034, 0x00044048, - 0x034, 0x00043045, - 0x034, 0x00042026, - 0x034, 0x00041023, - 0x034, 0x00040002, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00048DED, - 0x034, 0x00047DEA, - 0x034, 0x00046DE7, - 0x034, 0x00045CE9, - 0x034, 0x00044CE6, - 0x034, 0x000438C6, - 0x034, 0x00042886, - 0x034, 0x00041486, - 0x034, 0x00040447, - 0xA0000000, 0x00000000, - 0x034, 0x00048DEF, - 0x034, 0x00047DEC, - 0x034, 0x00046DE9, - 0x034, 0x00045CCB, - 0x034, 0x0004488D, - 0x034, 0x0004348D, - 0x034, 0x0004248A, - 0x034, 0x0004108D, - 0x034, 0x0004008A, - 0xB0000000, 0x00000000, - 0x80000210, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002ADF4, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0F3, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002A0F3, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0002ADF4, - 0xA0000000, 0x00000000, - 0x034, 0x0002ADF7, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00029DF4, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00029DF4, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00029DF1, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000290F0, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000290F0, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00029DF1, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00029DF4, - 0xA0000000, 0x00000000, - 0x034, 0x00029DF2, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00028DF1, - 0x034, 0x00027DEE, - 0x034, 0x00026DEB, - 0x034, 0x00025CEC, - 0x034, 0x00024CE9, - 0x034, 0x000238CA, - 0x034, 0x00022889, - 0x034, 0x00021489, - 0x034, 0x0002044A, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00028DF1, - 0x034, 0x00027DEE, - 0x034, 0x00026DEB, - 0x034, 0x00025CEC, - 0x034, 0x00024CE9, - 0x034, 0x000238CA, - 0x034, 0x00022889, - 0x034, 0x00021489, - 0x034, 0x0002044A, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000280AF, - 0x034, 0x000270AC, - 0x034, 0x0002608B, - 0x034, 0x00025069, - 0x034, 0x00024048, - 0x034, 0x00023045, - 0x034, 0x00022026, - 0x034, 0x00021023, - 0x034, 0x00020002, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x000280AF, - 0x034, 0x000270AC, - 0x034, 0x0002608B, - 0x034, 0x00025069, - 0x034, 0x00024048, - 0x034, 0x00023045, - 0x034, 0x00022026, - 0x034, 0x00021023, - 0x034, 0x00020002, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00028DF1, - 0x034, 0x00027DEE, - 0x034, 0x00026DEB, - 0x034, 0x00025CEC, - 0x034, 0x00024CE9, - 0x034, 0x000238CA, - 0x034, 0x00022889, - 0x034, 0x00021489, - 0x034, 0x0002044A, - 0xA0000000, 0x00000000, - 0x034, 0x00028DEE, - 0x034, 0x00027DEB, - 0x034, 0x00026CCD, - 0x034, 0x00025CCA, - 0x034, 0x0002488C, - 0x034, 0x0002384C, - 0x034, 0x00022849, - 0x034, 0x00021449, - 0x034, 0x0002004D, - 0xB0000000, 0x00000000, - 0x8000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D7, - 0x034, 0x000090D3, - 0x034, 0x000080B1, - 0x034, 0x000070AE, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000A0D7, - 0x034, 0x000090D3, - 0x034, 0x000080B1, - 0x034, 0x000070AE, - 0xA0000000, 0x00000000, - 0x034, 0x0000ADF7, - 0x034, 0x00009DF4, - 0x034, 0x00008DF1, - 0x034, 0x00007DEE, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00006DEB, - 0x034, 0x00005CEC, - 0x034, 0x00004CE9, - 0x034, 0x000038CA, - 0x034, 0x00002889, - 0x034, 0x00001489, - 0x034, 0x0000044A, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00006DEB, - 0x034, 0x00005CEC, - 0x034, 0x00004CE9, - 0x034, 0x000038CA, - 0x034, 0x00002889, - 0x034, 0x00001489, - 0x034, 0x0000044A, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000608D, - 0x034, 0x0000506B, - 0x034, 0x0000404A, - 0x034, 0x00003047, - 0x034, 0x00002044, - 0x034, 0x00001025, - 0x034, 0x00000004, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x0000608D, - 0x034, 0x0000506B, - 0x034, 0x0000404A, - 0x034, 0x00003047, - 0x034, 0x00002044, - 0x034, 0x00001025, - 0x034, 0x00000004, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x034, 0x00006DEB, - 0x034, 0x00005CEC, - 0x034, 0x00004CE9, - 0x034, 0x000038CA, - 0x034, 0x00002889, - 0x034, 0x00001489, - 0x034, 0x0000044A, - 0xA0000000, 0x00000000, - 0x034, 0x00006DCD, - 0x034, 0x00005CCD, - 0x034, 0x00004CCA, - 0x034, 0x0000388C, - 0x034, 0x00002888, - 0x034, 0x00001488, - 0x034, 0x00000486, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000040, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000187, - 0x035, 0x00008187, - 0x035, 0x00010187, - 0x035, 0x00020188, - 0x035, 0x00028188, - 0x035, 0x00030188, - 0x035, 0x00040188, - 0x035, 0x00048188, - 0x035, 0x00050188, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000187, - 0x035, 0x00008187, - 0x035, 0x00010187, - 0x035, 0x00020188, - 0x035, 0x00028188, - 0x035, 0x00030188, - 0x035, 0x00040188, - 0x035, 0x00048188, - 0x035, 0x00050188, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000128, - 0x035, 0x00008128, - 0x035, 0x00010128, - 0x035, 0x000201C8, - 0x035, 0x000281C8, - 0x035, 0x000301C8, - 0x035, 0x000401C8, - 0x035, 0x000481C8, - 0x035, 0x000501C8, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000145, - 0x035, 0x00008145, - 0x035, 0x00010145, - 0x035, 0x00020196, - 0x035, 0x00028196, - 0x035, 0x00030196, - 0x035, 0x000401C7, - 0x035, 0x000481C7, - 0x035, 0x000501C7, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000128, - 0x035, 0x00008128, - 0x035, 0x00010128, - 0x035, 0x000201C8, - 0x035, 0x000281C8, - 0x035, 0x000301C8, - 0x035, 0x000401C8, - 0x035, 0x000481C8, - 0x035, 0x000501C8, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x035, 0x00000187, - 0x035, 0x00008187, - 0x035, 0x00010187, - 0x035, 0x00020188, - 0x035, 0x00028188, - 0x035, 0x00030188, - 0x035, 0x00040188, - 0x035, 0x00048188, - 0x035, 0x00050188, - 0xA0000000, 0x00000000, - 0x035, 0x00000145, - 0x035, 0x00008145, - 0x035, 0x00010145, - 0x035, 0x00020196, - 0x035, 0x00028196, - 0x035, 0x00030196, - 0x035, 0x000401C7, - 0x035, 0x000481C7, - 0x035, 0x000501C7, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000010, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x00085733, - 0x036, 0x0008D733, - 0x036, 0x00095733, - 0x036, 0x0009D733, - 0x036, 0x000A64B4, - 0x036, 0x000AE4B4, - 0x036, 0x000B64B4, - 0x036, 0x000BE4B4, - 0x036, 0x000C64B4, - 0x036, 0x000CE4B4, - 0x036, 0x000D64B4, - 0x036, 0x000DE4B4, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x00085733, - 0x036, 0x0008D733, - 0x036, 0x00095733, - 0x036, 0x0009D733, - 0x036, 0x000A64B4, - 0x036, 0x000AE4B4, - 0x036, 0x000B64B4, - 0x036, 0x000BE4B4, - 0x036, 0x000C64B4, - 0x036, 0x000CE4B4, - 0x036, 0x000D64B4, - 0x036, 0x000DE4B4, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x000063B5, - 0x036, 0x0000E3B5, - 0x036, 0x000163B5, - 0x036, 0x0001E3B5, - 0x036, 0x000263B5, - 0x036, 0x0002E3B5, - 0x036, 0x000363B5, - 0x036, 0x0003E3B5, - 0x036, 0x000463B5, - 0x036, 0x0004E3B5, - 0x036, 0x000563B5, - 0x036, 0x0005E3B5, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x000056B3, - 0x036, 0x0000D6B3, - 0x036, 0x000156B3, - 0x036, 0x0001D6B3, - 0x036, 0x00026634, - 0x036, 0x0002E634, - 0x036, 0x00036634, - 0x036, 0x0003E634, - 0x036, 0x000467B4, - 0x036, 0x0004E7B4, - 0x036, 0x000567B4, - 0x036, 0x0005E7B4, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x000063B5, - 0x036, 0x0000E3B5, - 0x036, 0x000163B5, - 0x036, 0x0001E3B5, - 0x036, 0x000263B5, - 0x036, 0x0002E3B5, - 0x036, 0x000363B5, - 0x036, 0x0003E3B5, - 0x036, 0x000463B5, - 0x036, 0x0004E3B5, - 0x036, 0x000563B5, - 0x036, 0x0005E3B5, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x036, 0x00085733, - 0x036, 0x0008D733, - 0x036, 0x00095733, - 0x036, 0x0009D733, - 0x036, 0x000A64B4, - 0x036, 0x000AE4B4, - 0x036, 0x000B64B4, - 0x036, 0x000BE4B4, - 0x036, 0x000C64B4, - 0x036, 0x000CE4B4, - 0x036, 0x000D64B4, - 0x036, 0x000DE4B4, - 0xA0000000, 0x00000000, - 0x036, 0x000056B3, - 0x036, 0x0000D6B3, - 0x036, 0x000156B3, - 0x036, 0x0001D6B3, - 0x036, 0x00026634, - 0x036, 0x0002E634, - 0x036, 0x00036634, - 0x036, 0x0003E634, - 0x036, 0x000467B4, - 0x036, 0x0004E7B4, - 0x036, 0x000567B4, - 0x036, 0x0005E7B4, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x00000008, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000001C8, - 0x03C, 0x00000492, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000001C8, - 0x03C, 0x00000492, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000001B6, - 0x03C, 0x00000492, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x0000022A, - 0x03C, 0x00000594, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000001B6, - 0x03C, 0x00000492, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x000001C8, - 0x03C, 0x00000492, - 0xA0000000, 0x00000000, - 0x03C, 0x0000022A, - 0x03C, 0x00000594, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000800, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000800, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000800, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000820, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000820, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000800, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x03C, 0x00000800, - 0xA0000000, 0x00000000, - 0x03C, 0x00000900, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x018, 0x0001712A, - 0x0EF, 0x00000002, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x0004E400, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x0004E400, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x00002000, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x00002000, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x00002000, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x00002000, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x008, 0x0004E400, - 0xA0000000, 0x00000000, - 0x008, 0x00002000, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0DF, 0x000000C0, - 0x01F, 0x00000064, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x000A7284, - 0x059, 0x000600EC, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x000A7284, - 0x059, 0x000600EC, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x00081184, - 0x059, 0x0006016C, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x00081184, - 0x059, 0x0006016C, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x00081184, - 0x059, 0x0006016C, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x058, 0x000A7284, - 0x059, 0x000600EC, - 0xA0000000, 0x00000000, - 0x058, 0x00081184, - 0x059, 0x0006016C, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000E8D73, - 0x062, 0x00093FC5, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000E8D73, - 0x062, 0x00093FC5, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000EFD83, - 0x062, 0x00093FCC, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000EAD53, - 0x062, 0x00093BC4, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000EFD83, - 0x062, 0x00093FCC, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x000E8D73, - 0x062, 0x00093FC5, - 0xA0000000, 0x00000000, - 0x061, 0x000EAD53, - 0x062, 0x00093BC4, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110E9, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110E9, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110EB, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110E9, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110E9, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110EB, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x063, 0x000110E9, - 0xA0000000, 0x00000000, - 0x063, 0x000714E9, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C27C, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C27C, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C27C, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C67C, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C27C, - 0x90000410, 0x00000000, 0x40000000, 0x00000000, - 0x064, 0x0001C27C, - 0xA0000000, 0x00000000, - 0x064, 0x0001C67C, - 0xB0000000, 0x00000000, - 0x80000111, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00091016, - 0x90000110, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00091016, - 0x90000210, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00093016, - 0x9000020c, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00093015, - 0x9000040c, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00093015, - 0x90000200, 0x00000000, 0x40000000, 0x00000000, - 0x065, 0x00093016, - 0xA0000000, 0x00000000, - 0x065, 0x00091016, - 0xB0000000, 0x00000000, - 0x018, 0x00000006, - 0x0EF, 0x00002000, - 0x03B, 0x0003824B, - 0x03B, 0x0003024B, - 0x03B, 0x0002844B, - 0x03B, 0x00020F4B, - 0x03B, 0x00018F4B, - 0x03B, 0x000104B2, - 0x03B, 0x00008049, - 0x03B, 0x00000148, - 0x03B, 0x0007824B, - 0x03B, 0x0007024B, - 0x03B, 0x0006824B, - 0x03B, 0x00060F4B, - 0x03B, 0x00058F4B, - 0x03B, 0x000504B2, - 0x03B, 0x00048049, - 0x03B, 0x00040148, - 0x0EF, 0x00000000, - 0x0EF, 0x00000100, - 0x034, 0x0000ADF3, - 0x034, 0x00009DF0, - 0x034, 0x00008D70, - 0x034, 0x00007D6D, - 0x034, 0x00006CEE, - 0x034, 0x00005CCC, - 0x034, 0x000044EC, - 0x034, 0x000034AC, - 0x034, 0x0000246D, - 0x034, 0x0000106F, - 0x034, 0x0000006C, - 0x0EF, 0x00000000, - 0x0ED, 0x00000010, - 0x044, 0x0000ADF2, - 0x044, 0x00009DEF, - 0x044, 0x00008DEC, - 0x044, 0x00007DE9, - 0x044, 0x00006CEC, - 0x044, 0x00005CE9, - 0x044, 0x000044EC, - 0x044, 0x000034E9, - 0x044, 0x0000246C, - 0x044, 0x00001469, - 0x044, 0x0000006C, - 0x0ED, 0x00000000, - 0x0ED, 0x00000001, - 0x040, 0x00038DA7, - 0x040, 0x000300C2, - 0x040, 0x000288E2, - 0x040, 0x000200B8, - 0x040, 0x000188A5, - 0x040, 0x00010FBC, - 0x040, 0x00008F71, - 0x040, 0x00000240, - 0x0ED, 0x00000000, - 0x0EF, 0x000020A2, - 0x0DF, 0x00000080, - 0x035, 0x00000120, - 0x035, 0x00008120, - 0x035, 0x00010120, - 0x036, 0x00000085, - 0x036, 0x00008085, - 0x036, 0x00010085, - 0x036, 0x00018085, - 0x0EF, 0x00000000, - 0x051, 0x00000C31, - 0x052, 0x00000622, - 0x053, 0x000FC70B, - 0x054, 0x0000017E, - 0x056, 0x00051DF3, - 0x051, 0x00000C01, - 0x052, 0x000006D6, - 0x053, 0x000FC649, - 0x070, 0x00049661, - 0x071, 0x0007843E, - 0x072, 0x00000382, - 0x074, 0x00051400, - 0x035, 0x00000160, - 0x035, 0x00008160, - 0x035, 0x00010160, - 0x036, 0x00000124, - 0x036, 0x00008124, - 0x036, 0x00010124, - 0x036, 0x00018124, - 0x0ED, 0x0000000C, - 0x045, 0x00000140, - 0x045, 0x00008140, - 0x045, 0x00010140, - 0x046, 0x00000124, - 0x046, 0x00008124, - 0x046, 0x00010124, - 0x046, 0x00018124, - 0x0DF, 0x00000088, - 0x0B3, 0x000F0E18, - 0x0B4, 0x0001214C, - 0x0B7, 0x0003000C, - 0x01C, 0x000539D2, - 0x0C4, 0x000AFE00, - 0x018, 0x0001F12A, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x018, 0x0001712A, - -}; - -void -ODM_ReadAndConfig_MP_8821A_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8821A_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8821A_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8821A(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8821A_RadioA(void) -{ - return 59; -} - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 18, 19, 19, 19}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; -#endif - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_AP( - IN PDM_ODM_T pDM_Odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -#endif - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_PCIE( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -#endif - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_SDIO( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; -#endif - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_USB( - IN PDM_ODM_T pDM_Odm -) -{ -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); -#endif -} - -/****************************************************************************** -* TXPWR_LMT_8811AU_FEM.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8811AU_FEM[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "34", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "34", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "34", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "34", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "34", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "34", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "34", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "34", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "34", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "34", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "32", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "34", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "34", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "34", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "34", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "34", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "32", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "34", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "34", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "34", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "34", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "34", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "34", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "34", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "34", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "32", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "34", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "34", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "34", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8811AU_FEM)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8811AU_FEM; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8811AU_IPA.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8811AU_IPA[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", - "MKK", "5G", "20M", "OFDM", "1T", "52", "30", - "FCC", "5G", "20M", "OFDM", "1T", "56", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", - "MKK", "5G", "20M", "OFDM", "1T", "56", "30", - "FCC", "5G", "20M", "OFDM", "1T", "60", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", - "MKK", "5G", "20M", "OFDM", "1T", "60", "30", - "FCC", "5G", "20M", "OFDM", "1T", "64", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", - "MKK", "5G", "20M", "OFDM", "1T", "64", "30", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", - "MKK", "5G", "20M", "OFDM", "1T", "100", "30", - "FCC", "5G", "20M", "OFDM", "1T", "104", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", - "MKK", "5G", "20M", "OFDM", "1T", "104", "30", - "FCC", "5G", "20M", "OFDM", "1T", "108", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", - "MKK", "5G", "20M", "OFDM", "1T", "108", "30", - "FCC", "5G", "20M", "OFDM", "1T", "112", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", - "MKK", "5G", "20M", "OFDM", "1T", "112", "30", - "FCC", "5G", "20M", "OFDM", "1T", "116", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", - "MKK", "5G", "20M", "OFDM", "1T", "116", "30", - "FCC", "5G", "20M", "OFDM", "1T", "120", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", - "MKK", "5G", "20M", "OFDM", "1T", "120", "30", - "FCC", "5G", "20M", "OFDM", "1T", "124", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", - "MKK", "5G", "20M", "OFDM", "1T", "124", "30", - "FCC", "5G", "20M", "OFDM", "1T", "128", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", - "MKK", "5G", "20M", "OFDM", "1T", "128", "30", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", - "MKK", "5G", "20M", "OFDM", "1T", "132", "30", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", - "MKK", "5G", "20M", "OFDM", "1T", "136", "30", - "FCC", "5G", "20M", "OFDM", "1T", "140", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", - "MKK", "5G", "20M", "OFDM", "1T", "140", "30", - "FCC", "5G", "20M", "OFDM", "1T", "149", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "30", - "MKK", "5G", "20M", "HT", "1T", "36", "30", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "30", - "MKK", "5G", "20M", "HT", "1T", "40", "30", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "30", - "MKK", "5G", "20M", "HT", "1T", "44", "30", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "30", - "MKK", "5G", "20M", "HT", "1T", "48", "30", - "FCC", "5G", "20M", "HT", "1T", "52", "30", - "ETSI", "5G", "20M", "HT", "1T", "52", "30", - "MKK", "5G", "20M", "HT", "1T", "52", "30", - "FCC", "5G", "20M", "HT", "1T", "56", "30", - "ETSI", "5G", "20M", "HT", "1T", "56", "30", - "MKK", "5G", "20M", "HT", "1T", "56", "30", - "FCC", "5G", "20M", "HT", "1T", "60", "30", - "ETSI", "5G", "20M", "HT", "1T", "60", "30", - "MKK", "5G", "20M", "HT", "1T", "60", "30", - "FCC", "5G", "20M", "HT", "1T", "64", "30", - "ETSI", "5G", "20M", "HT", "1T", "64", "30", - "MKK", "5G", "20M", "HT", "1T", "64", "30", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "30", - "MKK", "5G", "20M", "HT", "1T", "100", "30", - "FCC", "5G", "20M", "HT", "1T", "104", "30", - "ETSI", "5G", "20M", "HT", "1T", "104", "30", - "MKK", "5G", "20M", "HT", "1T", "104", "30", - "FCC", "5G", "20M", "HT", "1T", "108", "30", - "ETSI", "5G", "20M", "HT", "1T", "108", "30", - "MKK", "5G", "20M", "HT", "1T", "108", "30", - "FCC", "5G", "20M", "HT", "1T", "112", "30", - "ETSI", "5G", "20M", "HT", "1T", "112", "30", - "MKK", "5G", "20M", "HT", "1T", "112", "30", - "FCC", "5G", "20M", "HT", "1T", "116", "30", - "ETSI", "5G", "20M", "HT", "1T", "116", "30", - "MKK", "5G", "20M", "HT", "1T", "116", "30", - "FCC", "5G", "20M", "HT", "1T", "120", "30", - "ETSI", "5G", "20M", "HT", "1T", "120", "30", - "MKK", "5G", "20M", "HT", "1T", "120", "30", - "FCC", "5G", "20M", "HT", "1T", "124", "30", - "ETSI", "5G", "20M", "HT", "1T", "124", "30", - "MKK", "5G", "20M", "HT", "1T", "124", "30", - "FCC", "5G", "20M", "HT", "1T", "128", "30", - "ETSI", "5G", "20M", "HT", "1T", "128", "30", - "MKK", "5G", "20M", "HT", "1T", "128", "30", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "30", - "MKK", "5G", "20M", "HT", "1T", "132", "30", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "30", - "MKK", "5G", "20M", "HT", "1T", "136", "30", - "FCC", "5G", "20M", "HT", "1T", "140", "30", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "30", - "ETSI", "5G", "20M", "HT", "1T", "149", "30", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "30", - "ETSI", "5G", "20M", "HT", "1T", "153", "30", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "30", - "ETSI", "5G", "20M", "HT", "1T", "157", "30", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "30", - "ETSI", "5G", "20M", "HT", "1T", "161", "30", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "30", - "ETSI", "5G", "20M", "HT", "1T", "165", "30", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "28", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "28", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "28", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "28", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "28", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "28", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "28", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "28", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "30", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "30", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "28", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "26", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8811AU_IPA)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8811AU_IPA; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8821A.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8821A[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", - "MKK", "5G", "20M", "OFDM", "1T", "52", "30", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", - "MKK", "5G", "20M", "OFDM", "1T", "56", "30", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", - "MKK", "5G", "20M", "OFDM", "1T", "60", "30", - "FCC", "5G", "20M", "OFDM", "1T", "64", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", - "MKK", "5G", "20M", "OFDM", "1T", "64", "30", - "FCC", "5G", "20M", "OFDM", "1T", "100", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", - "MKK", "5G", "20M", "OFDM", "1T", "100", "30", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", - "MKK", "5G", "20M", "OFDM", "1T", "104", "30", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", - "MKK", "5G", "20M", "OFDM", "1T", "108", "30", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", - "MKK", "5G", "20M", "OFDM", "1T", "112", "30", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", - "MKK", "5G", "20M", "OFDM", "1T", "116", "30", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", - "MKK", "5G", "20M", "OFDM", "1T", "120", "30", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", - "MKK", "5G", "20M", "OFDM", "1T", "124", "30", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", - "MKK", "5G", "20M", "OFDM", "1T", "128", "30", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", - "MKK", "5G", "20M", "OFDM", "1T", "132", "30", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", - "MKK", "5G", "20M", "OFDM", "1T", "136", "30", - "FCC", "5G", "20M", "OFDM", "1T", "140", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", - "MKK", "5G", "20M", "OFDM", "1T", "140", "30", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "30", - "MKK", "5G", "20M", "HT", "1T", "36", "30", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "30", - "MKK", "5G", "20M", "HT", "1T", "40", "30", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "30", - "MKK", "5G", "20M", "HT", "1T", "44", "30", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "30", - "MKK", "5G", "20M", "HT", "1T", "48", "30", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "30", - "MKK", "5G", "20M", "HT", "1T", "52", "30", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "30", - "MKK", "5G", "20M", "HT", "1T", "56", "30", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "30", - "MKK", "5G", "20M", "HT", "1T", "60", "30", - "FCC", "5G", "20M", "HT", "1T", "64", "32", - "ETSI", "5G", "20M", "HT", "1T", "64", "30", - "MKK", "5G", "20M", "HT", "1T", "64", "30", - "FCC", "5G", "20M", "HT", "1T", "100", "32", - "ETSI", "5G", "20M", "HT", "1T", "100", "30", - "MKK", "5G", "20M", "HT", "1T", "100", "30", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "30", - "MKK", "5G", "20M", "HT", "1T", "104", "30", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "30", - "MKK", "5G", "20M", "HT", "1T", "108", "30", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "30", - "MKK", "5G", "20M", "HT", "1T", "112", "30", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "30", - "MKK", "5G", "20M", "HT", "1T", "116", "30", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "30", - "MKK", "5G", "20M", "HT", "1T", "120", "30", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "30", - "MKK", "5G", "20M", "HT", "1T", "124", "30", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "30", - "MKK", "5G", "20M", "HT", "1T", "128", "30", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "30", - "MKK", "5G", "20M", "HT", "1T", "132", "30", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "30", - "MKK", "5G", "20M", "HT", "1T", "136", "30", - "FCC", "5G", "20M", "HT", "1T", "140", "32", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "30", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "30", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "30", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "30", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "30", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "32", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "32", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "30", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "30", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "20", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "28", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8821A_E202SA.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8821A_E202SA[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "27", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "27", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "27", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "27", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "20", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "20", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "20", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "16", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", - "MKK", "2.4G", "20M", "HT", "1T", "01", "26", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "26", - "MKK", "2.4G", "20M", "HT", "1T", "02", "26", - "FCC", "2.4G", "20M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "26", - "MKK", "2.4G", "20M", "HT", "1T", "03", "26", - "FCC", "2.4G", "20M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "26", - "MKK", "2.4G", "20M", "HT", "1T", "04", "26", - "FCC", "2.4G", "20M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "26", - "MKK", "2.4G", "20M", "HT", "1T", "05", "26", - "FCC", "2.4G", "20M", "HT", "1T", "06", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "26", - "MKK", "2.4G", "20M", "HT", "1T", "06", "26", - "FCC", "2.4G", "20M", "HT", "1T", "07", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "26", - "MKK", "2.4G", "20M", "HT", "1T", "07", "26", - "FCC", "2.4G", "20M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "26", - "MKK", "2.4G", "20M", "HT", "1T", "08", "26", - "FCC", "2.4G", "20M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "26", - "MKK", "2.4G", "20M", "HT", "1T", "09", "26", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "26", - "MKK", "2.4G", "20M", "HT", "1T", "10", "26", - "FCC", "2.4G", "20M", "HT", "1T", "11", "15", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "26", - "MKK", "2.4G", "20M", "HT", "1T", "11", "26", - "FCC", "2.4G", "20M", "HT", "1T", "12", "15", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "26", - "MKK", "2.4G", "20M", "HT", "1T", "12", "26", - "FCC", "2.4G", "20M", "HT", "1T", "13", "15", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", - "MKK", "2.4G", "20M", "HT", "1T", "13", "26", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "22", - "MKK", "2.4G", "40M", "HT", "1T", "03", "22", - "FCC", "2.4G", "40M", "HT", "1T", "04", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "22", - "MKK", "2.4G", "40M", "HT", "1T", "04", "22", - "FCC", "2.4G", "40M", "HT", "1T", "05", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "22", - "MKK", "2.4G", "40M", "HT", "1T", "05", "22", - "FCC", "2.4G", "40M", "HT", "1T", "06", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "22", - "MKK", "2.4G", "40M", "HT", "1T", "06", "22", - "FCC", "2.4G", "40M", "HT", "1T", "07", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "22", - "MKK", "2.4G", "40M", "HT", "1T", "07", "22", - "FCC", "2.4G", "40M", "HT", "1T", "08", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "22", - "MKK", "2.4G", "40M", "HT", "1T", "08", "22", - "FCC", "2.4G", "40M", "HT", "1T", "09", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "22", - "MKK", "2.4G", "40M", "HT", "1T", "09", "22", - "FCC", "2.4G", "40M", "HT", "1T", "10", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "22", - "MKK", "2.4G", "40M", "HT", "1T", "10", "22", - "FCC", "2.4G", "40M", "HT", "1T", "11", "16", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "22", - "MKK", "2.4G", "40M", "HT", "1T", "11", "22", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "26", - "MKK", "5G", "20M", "OFDM", "1T", "36", "26", - "FCC", "5G", "20M", "OFDM", "1T", "40", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "26", - "MKK", "5G", "20M", "OFDM", "1T", "40", "26", - "FCC", "5G", "20M", "OFDM", "1T", "44", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "26", - "MKK", "5G", "20M", "OFDM", "1T", "44", "26", - "FCC", "5G", "20M", "OFDM", "1T", "48", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "26", - "MKK", "5G", "20M", "OFDM", "1T", "48", "26", - "FCC", "5G", "20M", "OFDM", "1T", "52", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "26", - "MKK", "5G", "20M", "OFDM", "1T", "52", "26", - "FCC", "5G", "20M", "OFDM", "1T", "56", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "26", - "MKK", "5G", "20M", "OFDM", "1T", "56", "26", - "FCC", "5G", "20M", "OFDM", "1T", "60", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "26", - "MKK", "5G", "20M", "OFDM", "1T", "60", "26", - "FCC", "5G", "20M", "OFDM", "1T", "64", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "26", - "MKK", "5G", "20M", "OFDM", "1T", "64", "26", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "26", - "MKK", "5G", "20M", "OFDM", "1T", "100", "26", - "FCC", "5G", "20M", "OFDM", "1T", "104", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "26", - "MKK", "5G", "20M", "OFDM", "1T", "104", "26", - "FCC", "5G", "20M", "OFDM", "1T", "108", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "26", - "MKK", "5G", "20M", "OFDM", "1T", "108", "26", - "FCC", "5G", "20M", "OFDM", "1T", "112", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "26", - "MKK", "5G", "20M", "OFDM", "1T", "112", "26", - "FCC", "5G", "20M", "OFDM", "1T", "116", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "26", - "MKK", "5G", "20M", "OFDM", "1T", "116", "26", - "FCC", "5G", "20M", "OFDM", "1T", "120", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "26", - "MKK", "5G", "20M", "OFDM", "1T", "120", "26", - "FCC", "5G", "20M", "OFDM", "1T", "124", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "26", - "MKK", "5G", "20M", "OFDM", "1T", "124", "26", - "FCC", "5G", "20M", "OFDM", "1T", "128", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "26", - "MKK", "5G", "20M", "OFDM", "1T", "128", "26", - "FCC", "5G", "20M", "OFDM", "1T", "132", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "26", - "MKK", "5G", "20M", "OFDM", "1T", "132", "26", - "FCC", "5G", "20M", "OFDM", "1T", "136", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "26", - "MKK", "5G", "20M", "OFDM", "1T", "136", "26", - "FCC", "5G", "20M", "OFDM", "1T", "140", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "26", - "MKK", "5G", "20M", "OFDM", "1T", "140", "26", - "FCC", "5G", "20M", "OFDM", "1T", "149", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "26", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "26", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "26", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "26", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "26", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "24", - "ETSI", "5G", "20M", "HT", "1T", "36", "24", - "MKK", "5G", "20M", "HT", "1T", "36", "24", - "FCC", "5G", "20M", "HT", "1T", "40", "24", - "ETSI", "5G", "20M", "HT", "1T", "40", "24", - "MKK", "5G", "20M", "HT", "1T", "40", "24", - "FCC", "5G", "20M", "HT", "1T", "44", "24", - "ETSI", "5G", "20M", "HT", "1T", "44", "24", - "MKK", "5G", "20M", "HT", "1T", "44", "24", - "FCC", "5G", "20M", "HT", "1T", "48", "24", - "ETSI", "5G", "20M", "HT", "1T", "48", "24", - "MKK", "5G", "20M", "HT", "1T", "48", "24", - "FCC", "5G", "20M", "HT", "1T", "52", "24", - "ETSI", "5G", "20M", "HT", "1T", "52", "24", - "MKK", "5G", "20M", "HT", "1T", "52", "24", - "FCC", "5G", "20M", "HT", "1T", "56", "24", - "ETSI", "5G", "20M", "HT", "1T", "56", "24", - "MKK", "5G", "20M", "HT", "1T", "56", "24", - "FCC", "5G", "20M", "HT", "1T", "60", "24", - "ETSI", "5G", "20M", "HT", "1T", "60", "24", - "MKK", "5G", "20M", "HT", "1T", "60", "24", - "FCC", "5G", "20M", "HT", "1T", "64", "24", - "ETSI", "5G", "20M", "HT", "1T", "64", "24", - "MKK", "5G", "20M", "HT", "1T", "64", "24", - "FCC", "5G", "20M", "HT", "1T", "100", "24", - "ETSI", "5G", "20M", "HT", "1T", "100", "24", - "MKK", "5G", "20M", "HT", "1T", "100", "24", - "FCC", "5G", "20M", "HT", "1T", "104", "24", - "ETSI", "5G", "20M", "HT", "1T", "104", "24", - "MKK", "5G", "20M", "HT", "1T", "104", "24", - "FCC", "5G", "20M", "HT", "1T", "108", "24", - "ETSI", "5G", "20M", "HT", "1T", "108", "24", - "MKK", "5G", "20M", "HT", "1T", "108", "24", - "FCC", "5G", "20M", "HT", "1T", "112", "24", - "ETSI", "5G", "20M", "HT", "1T", "112", "24", - "MKK", "5G", "20M", "HT", "1T", "112", "24", - "FCC", "5G", "20M", "HT", "1T", "116", "24", - "ETSI", "5G", "20M", "HT", "1T", "116", "24", - "MKK", "5G", "20M", "HT", "1T", "116", "24", - "FCC", "5G", "20M", "HT", "1T", "120", "24", - "ETSI", "5G", "20M", "HT", "1T", "120", "24", - "MKK", "5G", "20M", "HT", "1T", "120", "24", - "FCC", "5G", "20M", "HT", "1T", "124", "24", - "ETSI", "5G", "20M", "HT", "1T", "124", "24", - "MKK", "5G", "20M", "HT", "1T", "124", "24", - "FCC", "5G", "20M", "HT", "1T", "128", "24", - "ETSI", "5G", "20M", "HT", "1T", "128", "24", - "MKK", "5G", "20M", "HT", "1T", "128", "24", - "FCC", "5G", "20M", "HT", "1T", "132", "24", - "ETSI", "5G", "20M", "HT", "1T", "132", "24", - "MKK", "5G", "20M", "HT", "1T", "132", "24", - "FCC", "5G", "20M", "HT", "1T", "136", "24", - "ETSI", "5G", "20M", "HT", "1T", "136", "24", - "MKK", "5G", "20M", "HT", "1T", "136", "24", - "FCC", "5G", "20M", "HT", "1T", "140", "24", - "ETSI", "5G", "20M", "HT", "1T", "140", "24", - "MKK", "5G", "20M", "HT", "1T", "140", "24", - "FCC", "5G", "20M", "HT", "1T", "149", "24", - "ETSI", "5G", "20M", "HT", "1T", "149", "24", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "24", - "ETSI", "5G", "20M", "HT", "1T", "153", "24", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "24", - "ETSI", "5G", "20M", "HT", "1T", "157", "24", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "24", - "ETSI", "5G", "20M", "HT", "1T", "161", "24", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "24", - "ETSI", "5G", "20M", "HT", "1T", "165", "24", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "20", - "ETSI", "5G", "40M", "HT", "1T", "38", "20", - "MKK", "5G", "40M", "HT", "1T", "38", "20", - "FCC", "5G", "40M", "HT", "1T", "46", "20", - "ETSI", "5G", "40M", "HT", "1T", "46", "20", - "MKK", "5G", "40M", "HT", "1T", "46", "20", - "FCC", "5G", "40M", "HT", "1T", "54", "20", - "ETSI", "5G", "40M", "HT", "1T", "54", "20", - "MKK", "5G", "40M", "HT", "1T", "54", "20", - "FCC", "5G", "40M", "HT", "1T", "62", "20", - "ETSI", "5G", "40M", "HT", "1T", "62", "20", - "MKK", "5G", "40M", "HT", "1T", "62", "20", - "FCC", "5G", "40M", "HT", "1T", "102", "20", - "ETSI", "5G", "40M", "HT", "1T", "102", "20", - "MKK", "5G", "40M", "HT", "1T", "102", "20", - "FCC", "5G", "40M", "HT", "1T", "110", "20", - "ETSI", "5G", "40M", "HT", "1T", "110", "20", - "MKK", "5G", "40M", "HT", "1T", "110", "20", - "FCC", "5G", "40M", "HT", "1T", "118", "20", - "ETSI", "5G", "40M", "HT", "1T", "118", "20", - "MKK", "5G", "40M", "HT", "1T", "118", "20", - "FCC", "5G", "40M", "HT", "1T", "126", "20", - "ETSI", "5G", "40M", "HT", "1T", "126", "20", - "MKK", "5G", "40M", "HT", "1T", "126", "20", - "FCC", "5G", "40M", "HT", "1T", "134", "20", - "ETSI", "5G", "40M", "HT", "1T", "134", "20", - "MKK", "5G", "40M", "HT", "1T", "134", "20", - "FCC", "5G", "40M", "HT", "1T", "151", "20", - "ETSI", "5G", "40M", "HT", "1T", "151", "20", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "20", - "ETSI", "5G", "40M", "HT", "1T", "159", "20", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "16", - "ETSI", "5G", "80M", "VHT", "1T", "42", "16", - "MKK", "5G", "80M", "VHT", "1T", "42", "16", - "FCC", "5G", "80M", "VHT", "1T", "58", "16", - "ETSI", "5G", "80M", "VHT", "1T", "58", "16", - "MKK", "5G", "80M", "VHT", "1T", "58", "16", - "FCC", "5G", "80M", "VHT", "1T", "106", "16", - "ETSI", "5G", "80M", "VHT", "1T", "106", "16", - "MKK", "5G", "80M", "VHT", "1T", "106", "16", - "FCC", "5G", "80M", "VHT", "1T", "122", "16", - "ETSI", "5G", "80M", "VHT", "1T", "122", "16", - "MKK", "5G", "80M", "VHT", "1T", "122", "16", - "FCC", "5G", "80M", "VHT", "1T", "155", "16", - "ETSI", "5G", "80M", "VHT", "1T", "155", "16", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_E202SA)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_E202SA; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_13dBm.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "26", - "MKK", "5G", "20M", "OFDM", "1T", "36", "26", - "FCC", "5G", "20M", "OFDM", "1T", "40", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "26", - "MKK", "5G", "20M", "OFDM", "1T", "40", "26", - "FCC", "5G", "20M", "OFDM", "1T", "44", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "26", - "MKK", "5G", "20M", "OFDM", "1T", "44", "26", - "FCC", "5G", "20M", "OFDM", "1T", "48", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "26", - "MKK", "5G", "20M", "OFDM", "1T", "48", "26", - "FCC", "5G", "20M", "OFDM", "1T", "52", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "26", - "MKK", "5G", "20M", "OFDM", "1T", "52", "26", - "FCC", "5G", "20M", "OFDM", "1T", "56", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "26", - "MKK", "5G", "20M", "OFDM", "1T", "56", "26", - "FCC", "5G", "20M", "OFDM", "1T", "60", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "26", - "MKK", "5G", "20M", "OFDM", "1T", "60", "26", - "FCC", "5G", "20M", "OFDM", "1T", "64", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "26", - "MKK", "5G", "20M", "OFDM", "1T", "64", "26", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "26", - "MKK", "5G", "20M", "OFDM", "1T", "100", "26", - "FCC", "5G", "20M", "OFDM", "1T", "104", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "26", - "MKK", "5G", "20M", "OFDM", "1T", "104", "26", - "FCC", "5G", "20M", "OFDM", "1T", "108", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "26", - "MKK", "5G", "20M", "OFDM", "1T", "108", "26", - "FCC", "5G", "20M", "OFDM", "1T", "112", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "26", - "MKK", "5G", "20M", "OFDM", "1T", "112", "26", - "FCC", "5G", "20M", "OFDM", "1T", "116", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "26", - "MKK", "5G", "20M", "OFDM", "1T", "116", "26", - "FCC", "5G", "20M", "OFDM", "1T", "120", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "26", - "MKK", "5G", "20M", "OFDM", "1T", "120", "26", - "FCC", "5G", "20M", "OFDM", "1T", "124", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "26", - "MKK", "5G", "20M", "OFDM", "1T", "124", "26", - "FCC", "5G", "20M", "OFDM", "1T", "128", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "26", - "MKK", "5G", "20M", "OFDM", "1T", "128", "26", - "FCC", "5G", "20M", "OFDM", "1T", "132", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "26", - "MKK", "5G", "20M", "OFDM", "1T", "132", "26", - "FCC", "5G", "20M", "OFDM", "1T", "136", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "26", - "MKK", "5G", "20M", "OFDM", "1T", "136", "26", - "FCC", "5G", "20M", "OFDM", "1T", "140", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "26", - "MKK", "5G", "20M", "OFDM", "1T", "140", "26", - "FCC", "5G", "20M", "OFDM", "1T", "149", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "26", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "26", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "26", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "26", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "26", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "26", - "ETSI", "5G", "20M", "HT", "1T", "36", "26", - "MKK", "5G", "20M", "HT", "1T", "36", "26", - "FCC", "5G", "20M", "HT", "1T", "40", "26", - "ETSI", "5G", "20M", "HT", "1T", "40", "26", - "MKK", "5G", "20M", "HT", "1T", "40", "26", - "FCC", "5G", "20M", "HT", "1T", "44", "26", - "ETSI", "5G", "20M", "HT", "1T", "44", "26", - "MKK", "5G", "20M", "HT", "1T", "44", "26", - "FCC", "5G", "20M", "HT", "1T", "48", "26", - "ETSI", "5G", "20M", "HT", "1T", "48", "26", - "MKK", "5G", "20M", "HT", "1T", "48", "26", - "FCC", "5G", "20M", "HT", "1T", "52", "26", - "ETSI", "5G", "20M", "HT", "1T", "52", "26", - "MKK", "5G", "20M", "HT", "1T", "52", "26", - "FCC", "5G", "20M", "HT", "1T", "56", "26", - "ETSI", "5G", "20M", "HT", "1T", "56", "26", - "MKK", "5G", "20M", "HT", "1T", "56", "26", - "FCC", "5G", "20M", "HT", "1T", "60", "26", - "ETSI", "5G", "20M", "HT", "1T", "60", "26", - "MKK", "5G", "20M", "HT", "1T", "60", "26", - "FCC", "5G", "20M", "HT", "1T", "64", "26", - "ETSI", "5G", "20M", "HT", "1T", "64", "26", - "MKK", "5G", "20M", "HT", "1T", "64", "26", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "26", - "MKK", "5G", "20M", "HT", "1T", "100", "26", - "FCC", "5G", "20M", "HT", "1T", "104", "26", - "ETSI", "5G", "20M", "HT", "1T", "104", "26", - "MKK", "5G", "20M", "HT", "1T", "104", "26", - "FCC", "5G", "20M", "HT", "1T", "108", "26", - "ETSI", "5G", "20M", "HT", "1T", "108", "26", - "MKK", "5G", "20M", "HT", "1T", "108", "26", - "FCC", "5G", "20M", "HT", "1T", "112", "26", - "ETSI", "5G", "20M", "HT", "1T", "112", "26", - "MKK", "5G", "20M", "HT", "1T", "112", "26", - "FCC", "5G", "20M", "HT", "1T", "116", "26", - "ETSI", "5G", "20M", "HT", "1T", "116", "26", - "MKK", "5G", "20M", "HT", "1T", "116", "26", - "FCC", "5G", "20M", "HT", "1T", "120", "26", - "ETSI", "5G", "20M", "HT", "1T", "120", "26", - "MKK", "5G", "20M", "HT", "1T", "120", "26", - "FCC", "5G", "20M", "HT", "1T", "124", "26", - "ETSI", "5G", "20M", "HT", "1T", "124", "26", - "MKK", "5G", "20M", "HT", "1T", "124", "26", - "FCC", "5G", "20M", "HT", "1T", "128", "26", - "ETSI", "5G", "20M", "HT", "1T", "128", "26", - "MKK", "5G", "20M", "HT", "1T", "128", "26", - "FCC", "5G", "20M", "HT", "1T", "132", "26", - "ETSI", "5G", "20M", "HT", "1T", "132", "26", - "MKK", "5G", "20M", "HT", "1T", "132", "26", - "FCC", "5G", "20M", "HT", "1T", "136", "26", - "ETSI", "5G", "20M", "HT", "1T", "136", "26", - "MKK", "5G", "20M", "HT", "1T", "136", "26", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "26", - "MKK", "5G", "20M", "HT", "1T", "140", "26", - "FCC", "5G", "20M", "HT", "1T", "149", "26", - "ETSI", "5G", "20M", "HT", "1T", "149", "26", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "26", - "ETSI", "5G", "20M", "HT", "1T", "153", "26", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "26", - "ETSI", "5G", "20M", "HT", "1T", "157", "26", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "26", - "ETSI", "5G", "20M", "HT", "1T", "161", "26", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "26", - "ETSI", "5G", "20M", "HT", "1T", "165", "26", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "26", - "ETSI", "5G", "20M", "HT", "2T", "36", "26", - "MKK", "5G", "20M", "HT", "2T", "36", "26", - "FCC", "5G", "20M", "HT", "2T", "40", "26", - "ETSI", "5G", "20M", "HT", "2T", "40", "26", - "MKK", "5G", "20M", "HT", "2T", "40", "26", - "FCC", "5G", "20M", "HT", "2T", "44", "26", - "ETSI", "5G", "20M", "HT", "2T", "44", "26", - "MKK", "5G", "20M", "HT", "2T", "44", "26", - "FCC", "5G", "20M", "HT", "2T", "48", "26", - "ETSI", "5G", "20M", "HT", "2T", "48", "26", - "MKK", "5G", "20M", "HT", "2T", "48", "26", - "FCC", "5G", "20M", "HT", "2T", "52", "26", - "ETSI", "5G", "20M", "HT", "2T", "52", "26", - "MKK", "5G", "20M", "HT", "2T", "52", "26", - "FCC", "5G", "20M", "HT", "2T", "56", "26", - "ETSI", "5G", "20M", "HT", "2T", "56", "26", - "MKK", "5G", "20M", "HT", "2T", "56", "26", - "FCC", "5G", "20M", "HT", "2T", "60", "26", - "ETSI", "5G", "20M", "HT", "2T", "60", "26", - "MKK", "5G", "20M", "HT", "2T", "60", "26", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "26", - "MKK", "5G", "20M", "HT", "2T", "64", "26", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "26", - "MKK", "5G", "20M", "HT", "2T", "100", "26", - "FCC", "5G", "20M", "HT", "2T", "104", "26", - "ETSI", "5G", "20M", "HT", "2T", "104", "26", - "MKK", "5G", "20M", "HT", "2T", "104", "26", - "FCC", "5G", "20M", "HT", "2T", "108", "26", - "ETSI", "5G", "20M", "HT", "2T", "108", "26", - "MKK", "5G", "20M", "HT", "2T", "108", "26", - "FCC", "5G", "20M", "HT", "2T", "112", "26", - "ETSI", "5G", "20M", "HT", "2T", "112", "26", - "MKK", "5G", "20M", "HT", "2T", "112", "26", - "FCC", "5G", "20M", "HT", "2T", "116", "26", - "ETSI", "5G", "20M", "HT", "2T", "116", "26", - "MKK", "5G", "20M", "HT", "2T", "116", "26", - "FCC", "5G", "20M", "HT", "2T", "120", "26", - "ETSI", "5G", "20M", "HT", "2T", "120", "26", - "MKK", "5G", "20M", "HT", "2T", "120", "26", - "FCC", "5G", "20M", "HT", "2T", "124", "26", - "ETSI", "5G", "20M", "HT", "2T", "124", "26", - "MKK", "5G", "20M", "HT", "2T", "124", "26", - "FCC", "5G", "20M", "HT", "2T", "128", "26", - "ETSI", "5G", "20M", "HT", "2T", "128", "26", - "MKK", "5G", "20M", "HT", "2T", "128", "26", - "FCC", "5G", "20M", "HT", "2T", "132", "26", - "ETSI", "5G", "20M", "HT", "2T", "132", "26", - "MKK", "5G", "20M", "HT", "2T", "132", "26", - "FCC", "5G", "20M", "HT", "2T", "136", "26", - "ETSI", "5G", "20M", "HT", "2T", "136", "26", - "MKK", "5G", "20M", "HT", "2T", "136", "26", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "26", - "MKK", "5G", "20M", "HT", "2T", "140", "26", - "FCC", "5G", "20M", "HT", "2T", "149", "26", - "ETSI", "5G", "20M", "HT", "2T", "149", "26", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "26", - "ETSI", "5G", "20M", "HT", "2T", "153", "26", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "26", - "ETSI", "5G", "20M", "HT", "2T", "157", "26", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "26", - "ETSI", "5G", "20M", "HT", "2T", "161", "26", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "26", - "ETSI", "5G", "20M", "HT", "2T", "165", "26", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "26", - "MKK", "5G", "40M", "HT", "1T", "38", "26", - "FCC", "5G", "40M", "HT", "1T", "46", "26", - "ETSI", "5G", "40M", "HT", "1T", "46", "26", - "MKK", "5G", "40M", "HT", "1T", "46", "26", - "FCC", "5G", "40M", "HT", "1T", "54", "26", - "ETSI", "5G", "40M", "HT", "1T", "54", "26", - "MKK", "5G", "40M", "HT", "1T", "54", "26", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "26", - "MKK", "5G", "40M", "HT", "1T", "62", "26", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "26", - "MKK", "5G", "40M", "HT", "1T", "102", "26", - "FCC", "5G", "40M", "HT", "1T", "110", "26", - "ETSI", "5G", "40M", "HT", "1T", "110", "26", - "MKK", "5G", "40M", "HT", "1T", "110", "26", - "FCC", "5G", "40M", "HT", "1T", "118", "26", - "ETSI", "5G", "40M", "HT", "1T", "118", "26", - "MKK", "5G", "40M", "HT", "1T", "118", "26", - "FCC", "5G", "40M", "HT", "1T", "126", "26", - "ETSI", "5G", "40M", "HT", "1T", "126", "26", - "MKK", "5G", "40M", "HT", "1T", "126", "26", - "FCC", "5G", "40M", "HT", "1T", "134", "26", - "ETSI", "5G", "40M", "HT", "1T", "134", "26", - "MKK", "5G", "40M", "HT", "1T", "134", "26", - "FCC", "5G", "40M", "HT", "1T", "151", "26", - "ETSI", "5G", "40M", "HT", "1T", "151", "26", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "26", - "ETSI", "5G", "40M", "HT", "1T", "159", "26", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "26", - "ETSI", "5G", "40M", "HT", "2T", "38", "26", - "MKK", "5G", "40M", "HT", "2T", "38", "26", - "FCC", "5G", "40M", "HT", "2T", "46", "26", - "ETSI", "5G", "40M", "HT", "2T", "46", "26", - "MKK", "5G", "40M", "HT", "2T", "46", "26", - "FCC", "5G", "40M", "HT", "2T", "54", "26", - "ETSI", "5G", "40M", "HT", "2T", "54", "26", - "MKK", "5G", "40M", "HT", "2T", "54", "26", - "FCC", "5G", "40M", "HT", "2T", "62", "26", - "ETSI", "5G", "40M", "HT", "2T", "62", "26", - "MKK", "5G", "40M", "HT", "2T", "62", "26", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "26", - "MKK", "5G", "40M", "HT", "2T", "102", "26", - "FCC", "5G", "40M", "HT", "2T", "110", "26", - "ETSI", "5G", "40M", "HT", "2T", "110", "26", - "MKK", "5G", "40M", "HT", "2T", "110", "26", - "FCC", "5G", "40M", "HT", "2T", "118", "26", - "ETSI", "5G", "40M", "HT", "2T", "118", "26", - "MKK", "5G", "40M", "HT", "2T", "118", "26", - "FCC", "5G", "40M", "HT", "2T", "126", "26", - "ETSI", "5G", "40M", "HT", "2T", "126", "26", - "MKK", "5G", "40M", "HT", "2T", "126", "26", - "FCC", "5G", "40M", "HT", "2T", "134", "26", - "ETSI", "5G", "40M", "HT", "2T", "134", "26", - "MKK", "5G", "40M", "HT", "2T", "134", "26", - "FCC", "5G", "40M", "HT", "2T", "151", "26", - "ETSI", "5G", "40M", "HT", "2T", "151", "26", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "26", - "ETSI", "5G", "40M", "HT", "2T", "159", "26", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "26", - "MKK", "5G", "80M", "VHT", "1T", "42", "26", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "26", - "MKK", "5G", "80M", "VHT", "1T", "58", "26", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "26", - "MKK", "5G", "80M", "VHT", "1T", "106", "26", - "FCC", "5G", "80M", "VHT", "1T", "122", "20", - "ETSI", "5G", "80M", "VHT", "1T", "122", "26", - "MKK", "5G", "80M", "VHT", "1T", "122", "26", - "FCC", "5G", "80M", "VHT", "1T", "155", "26", - "ETSI", "5G", "80M", "VHT", "1T", "155", "26", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "26", - "ETSI", "5G", "80M", "VHT", "2T", "42", "26", - "MKK", "5G", "80M", "VHT", "2T", "42", "26", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "26", - "MKK", "5G", "80M", "VHT", "2T", "58", "26", - "FCC", "5G", "80M", "VHT", "2T", "106", "26", - "ETSI", "5G", "80M", "VHT", "2T", "106", "26", - "MKK", "5G", "80M", "VHT", "2T", "106", "26", - "FCC", "5G", "80M", "VHT", "2T", "122", "26", - "ETSI", "5G", "80M", "VHT", "2T", "122", "26", - "MKK", "5G", "80M", "VHT", "2T", "122", "26", - "FCC", "5G", "80M", "VHT", "2T", "155", "26", - "ETSI", "5G", "80M", "VHT", "2T", "155", "26", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_5mm.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", - "MKK", "5G", "20M", "OFDM", "1T", "52", "30", - "FCC", "5G", "20M", "OFDM", "1T", "56", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", - "MKK", "5G", "20M", "OFDM", "1T", "56", "30", - "FCC", "5G", "20M", "OFDM", "1T", "60", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", - "MKK", "5G", "20M", "OFDM", "1T", "60", "30", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", - "MKK", "5G", "20M", "OFDM", "1T", "64", "30", - "FCC", "5G", "20M", "OFDM", "1T", "100", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", - "MKK", "5G", "20M", "OFDM", "1T", "100", "30", - "FCC", "5G", "20M", "OFDM", "1T", "104", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", - "MKK", "5G", "20M", "OFDM", "1T", "104", "30", - "FCC", "5G", "20M", "OFDM", "1T", "108", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", - "MKK", "5G", "20M", "OFDM", "1T", "108", "30", - "FCC", "5G", "20M", "OFDM", "1T", "112", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", - "MKK", "5G", "20M", "OFDM", "1T", "112", "30", - "FCC", "5G", "20M", "OFDM", "1T", "116", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", - "MKK", "5G", "20M", "OFDM", "1T", "116", "30", - "FCC", "5G", "20M", "OFDM", "1T", "120", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", - "MKK", "5G", "20M", "OFDM", "1T", "120", "30", - "FCC", "5G", "20M", "OFDM", "1T", "124", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", - "MKK", "5G", "20M", "OFDM", "1T", "124", "30", - "FCC", "5G", "20M", "OFDM", "1T", "128", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", - "MKK", "5G", "20M", "OFDM", "1T", "128", "30", - "FCC", "5G", "20M", "OFDM", "1T", "132", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", - "MKK", "5G", "20M", "OFDM", "1T", "132", "30", - "FCC", "5G", "20M", "OFDM", "1T", "136", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", - "MKK", "5G", "20M", "OFDM", "1T", "136", "30", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", - "MKK", "5G", "20M", "OFDM", "1T", "140", "30", - "FCC", "5G", "20M", "OFDM", "1T", "149", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "30", - "MKK", "5G", "20M", "HT", "1T", "36", "30", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "30", - "MKK", "5G", "20M", "HT", "1T", "40", "30", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "30", - "MKK", "5G", "20M", "HT", "1T", "44", "30", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "30", - "MKK", "5G", "20M", "HT", "1T", "48", "30", - "FCC", "5G", "20M", "HT", "1T", "52", "28", - "ETSI", "5G", "20M", "HT", "1T", "52", "30", - "MKK", "5G", "20M", "HT", "1T", "52", "30", - "FCC", "5G", "20M", "HT", "1T", "56", "28", - "ETSI", "5G", "20M", "HT", "1T", "56", "30", - "MKK", "5G", "20M", "HT", "1T", "56", "30", - "FCC", "5G", "20M", "HT", "1T", "60", "28", - "ETSI", "5G", "20M", "HT", "1T", "60", "30", - "MKK", "5G", "20M", "HT", "1T", "60", "30", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "30", - "MKK", "5G", "20M", "HT", "1T", "64", "30", - "FCC", "5G", "20M", "HT", "1T", "100", "28", - "ETSI", "5G", "20M", "HT", "1T", "100", "30", - "MKK", "5G", "20M", "HT", "1T", "100", "30", - "FCC", "5G", "20M", "HT", "1T", "104", "28", - "ETSI", "5G", "20M", "HT", "1T", "104", "30", - "MKK", "5G", "20M", "HT", "1T", "104", "30", - "FCC", "5G", "20M", "HT", "1T", "108", "28", - "ETSI", "5G", "20M", "HT", "1T", "108", "30", - "MKK", "5G", "20M", "HT", "1T", "108", "30", - "FCC", "5G", "20M", "HT", "1T", "112", "28", - "ETSI", "5G", "20M", "HT", "1T", "112", "30", - "MKK", "5G", "20M", "HT", "1T", "112", "30", - "FCC", "5G", "20M", "HT", "1T", "116", "28", - "ETSI", "5G", "20M", "HT", "1T", "116", "30", - "MKK", "5G", "20M", "HT", "1T", "116", "30", - "FCC", "5G", "20M", "HT", "1T", "120", "28", - "ETSI", "5G", "20M", "HT", "1T", "120", "30", - "MKK", "5G", "20M", "HT", "1T", "120", "30", - "FCC", "5G", "20M", "HT", "1T", "124", "28", - "ETSI", "5G", "20M", "HT", "1T", "124", "30", - "MKK", "5G", "20M", "HT", "1T", "124", "30", - "FCC", "5G", "20M", "HT", "1T", "128", "28", - "ETSI", "5G", "20M", "HT", "1T", "128", "30", - "MKK", "5G", "20M", "HT", "1T", "128", "30", - "FCC", "5G", "20M", "HT", "1T", "132", "28", - "ETSI", "5G", "20M", "HT", "1T", "132", "30", - "MKK", "5G", "20M", "HT", "1T", "132", "30", - "FCC", "5G", "20M", "HT", "1T", "136", "28", - "ETSI", "5G", "20M", "HT", "1T", "136", "30", - "MKK", "5G", "20M", "HT", "1T", "136", "30", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "28", - "ETSI", "5G", "20M", "HT", "1T", "149", "30", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "28", - "ETSI", "5G", "20M", "HT", "1T", "153", "30", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "28", - "ETSI", "5G", "20M", "HT", "1T", "157", "30", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "28", - "ETSI", "5G", "20M", "HT", "1T", "161", "30", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "28", - "ETSI", "5G", "20M", "HT", "1T", "165", "30", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "28", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "28", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "28", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "28", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "28", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "151", "28", - "ETSI", "5G", "40M", "HT", "1T", "151", "30", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "28", - "ETSI", "5G", "40M", "HT", "1T", "159", "30", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "20", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "26", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_8mm.TXT -******************************************************************************/ - -const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "24", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", - "MKK", "2.4G", "20M", "HT", "2T", "01", "32", - "FCC", "2.4G", "20M", "HT", "2T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", - "MKK", "2.4G", "20M", "HT", "2T", "02", "32", - "FCC", "2.4G", "20M", "HT", "2T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", - "MKK", "2.4G", "20M", "HT", "2T", "03", "32", - "FCC", "2.4G", "20M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", - "MKK", "2.4G", "20M", "HT", "2T", "04", "32", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", - "MKK", "2.4G", "20M", "HT", "2T", "05", "32", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", - "MKK", "2.4G", "20M", "HT", "2T", "06", "32", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", - "MKK", "2.4G", "20M", "HT", "2T", "07", "32", - "FCC", "2.4G", "20M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", - "MKK", "2.4G", "20M", "HT", "2T", "08", "32", - "FCC", "2.4G", "20M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", - "MKK", "2.4G", "20M", "HT", "2T", "09", "32", - "FCC", "2.4G", "20M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", - "MKK", "2.4G", "20M", "HT", "2T", "10", "32", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", - "MKK", "2.4G", "20M", "HT", "2T", "11", "32", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", - "MKK", "2.4G", "20M", "HT", "2T", "12", "32", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", - "MKK", "2.4G", "20M", "HT", "2T", "13", "32", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "24", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "22", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", - "MKK", "2.4G", "40M", "HT", "2T", "12", "32", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", - "MKK", "2.4G", "40M", "HT", "2T", "13", "32", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", - "MKK", "5G", "20M", "OFDM", "1T", "52", "30", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", - "MKK", "5G", "20M", "OFDM", "1T", "56", "30", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", - "MKK", "5G", "20M", "OFDM", "1T", "60", "30", - "FCC", "5G", "20M", "OFDM", "1T", "64", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", - "MKK", "5G", "20M", "OFDM", "1T", "64", "30", - "FCC", "5G", "20M", "OFDM", "1T", "100", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", - "MKK", "5G", "20M", "OFDM", "1T", "100", "30", - "FCC", "5G", "20M", "OFDM", "1T", "104", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", - "MKK", "5G", "20M", "OFDM", "1T", "104", "30", - "FCC", "5G", "20M", "OFDM", "1T", "108", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", - "MKK", "5G", "20M", "OFDM", "1T", "108", "30", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", - "MKK", "5G", "20M", "OFDM", "1T", "112", "30", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", - "MKK", "5G", "20M", "OFDM", "1T", "116", "30", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", - "MKK", "5G", "20M", "OFDM", "1T", "120", "30", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", - "MKK", "5G", "20M", "OFDM", "1T", "124", "30", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", - "MKK", "5G", "20M", "OFDM", "1T", "128", "30", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", - "MKK", "5G", "20M", "OFDM", "1T", "132", "30", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", - "MKK", "5G", "20M", "OFDM", "1T", "136", "30", - "FCC", "5G", "20M", "OFDM", "1T", "140", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", - "MKK", "5G", "20M", "OFDM", "1T", "140", "30", - "FCC", "5G", "20M", "OFDM", "1T", "149", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "32", - "ETSI", "5G", "20M", "HT", "1T", "36", "30", - "MKK", "5G", "20M", "HT", "1T", "36", "30", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "30", - "MKK", "5G", "20M", "HT", "1T", "40", "30", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "30", - "MKK", "5G", "20M", "HT", "1T", "44", "30", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "30", - "MKK", "5G", "20M", "HT", "1T", "48", "30", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "30", - "MKK", "5G", "20M", "HT", "1T", "52", "30", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "30", - "MKK", "5G", "20M", "HT", "1T", "56", "30", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "30", - "MKK", "5G", "20M", "HT", "1T", "60", "30", - "FCC", "5G", "20M", "HT", "1T", "64", "32", - "ETSI", "5G", "20M", "HT", "1T", "64", "30", - "MKK", "5G", "20M", "HT", "1T", "64", "30", - "FCC", "5G", "20M", "HT", "1T", "100", "28", - "ETSI", "5G", "20M", "HT", "1T", "100", "30", - "MKK", "5G", "20M", "HT", "1T", "100", "30", - "FCC", "5G", "20M", "HT", "1T", "104", "28", - "ETSI", "5G", "20M", "HT", "1T", "104", "30", - "MKK", "5G", "20M", "HT", "1T", "104", "30", - "FCC", "5G", "20M", "HT", "1T", "108", "28", - "ETSI", "5G", "20M", "HT", "1T", "108", "30", - "MKK", "5G", "20M", "HT", "1T", "108", "30", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "30", - "MKK", "5G", "20M", "HT", "1T", "112", "30", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "30", - "MKK", "5G", "20M", "HT", "1T", "116", "30", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "30", - "MKK", "5G", "20M", "HT", "1T", "120", "30", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "30", - "MKK", "5G", "20M", "HT", "1T", "124", "30", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "30", - "MKK", "5G", "20M", "HT", "1T", "128", "30", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "30", - "MKK", "5G", "20M", "HT", "1T", "132", "30", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "30", - "MKK", "5G", "20M", "HT", "1T", "136", "30", - "FCC", "5G", "20M", "HT", "1T", "140", "32", - "ETSI", "5G", "20M", "HT", "1T", "140", "30", - "MKK", "5G", "20M", "HT", "1T", "140", "30", - "FCC", "5G", "20M", "HT", "1T", "149", "28", - "ETSI", "5G", "20M", "HT", "1T", "149", "30", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "28", - "ETSI", "5G", "20M", "HT", "1T", "153", "30", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "30", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "30", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "30", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "26", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "32", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "28", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "28", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "28", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "151", "28", - "ETSI", "5G", "40M", "HT", "1T", "151", "30", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", - "ETSI", "5G", "40M", "HT", "1T", "159", "30", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "22", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "30", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "30", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "20", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "155", "28", - "ETSI", "5G", "80M", "VHT", "1T", "155", "30", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821A_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8821A_RadioA[] = { + 0x018, 0x0001712A, + 0x056, 0x00051CF2, + 0x066, 0x00040000, + 0x000, 0x00010000, + 0x01E, 0x00080000, + 0x082, 0x00000830, + 0x083, 0x00021800, + 0x084, 0x00028000, + 0x085, 0x00048000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0009483A, + 0xA0000000, 0x00000000, + 0x086, 0x00094838, + 0xB0000000, 0x00000000, + 0x087, 0x00044980, + 0x088, 0x00048000, + 0x089, 0x0000D480, + 0x08A, 0x00042240, + 0x08B, 0x000F0380, + 0x08C, 0x00090000, + 0x08D, 0x00022852, + 0x08E, 0x00065540, + 0x08F, 0x00088001, + 0x0EF, 0x00020000, + 0x03E, 0x00000380, + 0x03F, 0x00090018, + 0x03E, 0x00020380, + 0x03F, 0x000A0018, + 0x03E, 0x00040308, + 0x03F, 0x000A0018, + 0x03E, 0x00060018, + 0x03F, 0x000A0018, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x089, 0x00000080, + 0x08B, 0x00080180, + 0x0EF, 0x00001000, + 0x03A, 0x00000244, + 0x03B, 0x00038027, + 0x03C, 0x00082000, + 0x03A, 0x00000244, + 0x03B, 0x00030113, + 0x03C, 0x00082000, + 0x03A, 0x0000014C, + 0x03B, 0x00028027, + 0x03C, 0x00082000, + 0x03A, 0x000000CC, + 0x03B, 0x00027027, + 0x03C, 0x00042000, + 0x03A, 0x0000014C, + 0x03B, 0x0001F913, + 0x03C, 0x00042000, + 0x03A, 0x0000010C, + 0x03B, 0x00017F10, + 0x03C, 0x00012000, + 0x03A, 0x000000D0, + 0x03B, 0x00008027, + 0x03C, 0x000CA000, + 0x03A, 0x00000244, + 0x03B, 0x00078027, + 0x03C, 0x00082000, + 0x03A, 0x00000244, + 0x03B, 0x00070113, + 0x03C, 0x00082000, + 0x03A, 0x0000014C, + 0x03B, 0x00068027, + 0x03C, 0x00082000, + 0x03A, 0x000000CC, + 0x03B, 0x00067027, + 0x03C, 0x00042000, + 0x03A, 0x0000014C, + 0x03B, 0x0005F913, + 0x03C, 0x00042000, + 0x03A, 0x0000010C, + 0x03B, 0x00057F10, + 0x03C, 0x00012000, + 0x03A, 0x000000D0, + 0x03B, 0x00048027, + 0x03C, 0x000CA000, + 0x03A, 0x00000244, + 0x03B, 0x000B8027, + 0x03C, 0x00082000, + 0x03A, 0x00000244, + 0x03B, 0x000B0113, + 0x03C, 0x00082000, + 0x03A, 0x0000014C, + 0x03B, 0x000A8027, + 0x03C, 0x00082000, + 0x03A, 0x000000CC, + 0x03B, 0x000A7027, + 0x03C, 0x00042000, + 0x03A, 0x0000014C, + 0x03B, 0x0009F913, + 0x03C, 0x00042000, + 0x03A, 0x0000010C, + 0x03B, 0x00097F10, + 0x03C, 0x00012000, + 0x03A, 0x000000D0, + 0x03B, 0x00088027, + 0x03C, 0x000CA000, + 0x0EF, 0x00000000, + 0x0EF, 0x00001100, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004ADF3, + 0x034, 0x00049DF0, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004ADF3, + 0x034, 0x00049DF0, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004ADF5, + 0x034, 0x00049DF2, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0F3, + 0x034, 0x000490B1, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004A0F3, + 0x034, 0x000490B1, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004ADF5, + 0x034, 0x00049DF2, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0004ADF3, + 0x034, 0x00049DF0, + 0xA0000000, 0x00000000, + 0x034, 0x0004ADF7, + 0x034, 0x00049DF3, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00048DED, + 0x034, 0x00047DEA, + 0x034, 0x00046DE7, + 0x034, 0x00045CE9, + 0x034, 0x00044CE6, + 0x034, 0x000438C6, + 0x034, 0x00042886, + 0x034, 0x00041486, + 0x034, 0x00040447, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00048DED, + 0x034, 0x00047DEA, + 0x034, 0x00046DE7, + 0x034, 0x00045CE9, + 0x034, 0x00044CE6, + 0x034, 0x000438C6, + 0x034, 0x00042886, + 0x034, 0x00041486, + 0x034, 0x00040447, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000480AE, + 0x034, 0x000470AB, + 0x034, 0x0004608B, + 0x034, 0x00045069, + 0x034, 0x00044048, + 0x034, 0x00043045, + 0x034, 0x00042026, + 0x034, 0x00041023, + 0x034, 0x00040002, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000480AE, + 0x034, 0x000470AB, + 0x034, 0x0004608B, + 0x034, 0x00045069, + 0x034, 0x00044048, + 0x034, 0x00043045, + 0x034, 0x00042026, + 0x034, 0x00041023, + 0x034, 0x00040002, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00048DED, + 0x034, 0x00047DEA, + 0x034, 0x00046DE7, + 0x034, 0x00045CE9, + 0x034, 0x00044CE6, + 0x034, 0x000438C6, + 0x034, 0x00042886, + 0x034, 0x00041486, + 0x034, 0x00040447, + 0xA0000000, 0x00000000, + 0x034, 0x00048DEF, + 0x034, 0x00047DEC, + 0x034, 0x00046DE9, + 0x034, 0x00045CCB, + 0x034, 0x0004488D, + 0x034, 0x0004348D, + 0x034, 0x0004248A, + 0x034, 0x0004108D, + 0x034, 0x0004008A, + 0xB0000000, 0x00000000, + 0x80000210, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002ADF4, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0F3, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002A0F3, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0002ADF4, + 0xA0000000, 0x00000000, + 0x034, 0x0002ADF7, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00029DF4, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00029DF4, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00029DF1, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000290F0, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000290F0, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00029DF1, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00029DF4, + 0xA0000000, 0x00000000, + 0x034, 0x00029DF2, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00028DF1, + 0x034, 0x00027DEE, + 0x034, 0x00026DEB, + 0x034, 0x00025CEC, + 0x034, 0x00024CE9, + 0x034, 0x000238CA, + 0x034, 0x00022889, + 0x034, 0x00021489, + 0x034, 0x0002044A, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00028DF1, + 0x034, 0x00027DEE, + 0x034, 0x00026DEB, + 0x034, 0x00025CEC, + 0x034, 0x00024CE9, + 0x034, 0x000238CA, + 0x034, 0x00022889, + 0x034, 0x00021489, + 0x034, 0x0002044A, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000280AF, + 0x034, 0x000270AC, + 0x034, 0x0002608B, + 0x034, 0x00025069, + 0x034, 0x00024048, + 0x034, 0x00023045, + 0x034, 0x00022026, + 0x034, 0x00021023, + 0x034, 0x00020002, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x000280AF, + 0x034, 0x000270AC, + 0x034, 0x0002608B, + 0x034, 0x00025069, + 0x034, 0x00024048, + 0x034, 0x00023045, + 0x034, 0x00022026, + 0x034, 0x00021023, + 0x034, 0x00020002, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00028DF1, 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0x0000044A, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00006DEB, + 0x034, 0x00005CEC, + 0x034, 0x00004CE9, + 0x034, 0x000038CA, + 0x034, 0x00002889, + 0x034, 0x00001489, + 0x034, 0x0000044A, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000608D, + 0x034, 0x0000506B, + 0x034, 0x0000404A, + 0x034, 0x00003047, + 0x034, 0x00002044, + 0x034, 0x00001025, + 0x034, 0x00000004, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000608D, + 0x034, 0x0000506B, + 0x034, 0x0000404A, + 0x034, 0x00003047, + 0x034, 0x00002044, + 0x034, 0x00001025, + 0x034, 0x00000004, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x00006DEB, + 0x034, 0x00005CEC, + 0x034, 0x00004CE9, + 0x034, 0x000038CA, + 0x034, 0x00002889, + 0x034, 0x00001489, + 0x034, 0x0000044A, + 0xA0000000, 0x00000000, + 0x034, 0x00006DCD, + 0x034, 0x00005CCD, + 0x034, 0x00004CCA, + 0x034, 0x0000388C, + 0x034, 0x00002888, + 0x034, 0x00001488, + 0x034, 0x00000486, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000040, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000187, + 0x035, 0x00008187, + 0x035, 0x00010187, + 0x035, 0x00020188, + 0x035, 0x00028188, + 0x035, 0x00030188, + 0x035, 0x00040188, + 0x035, 0x00048188, + 0x035, 0x00050188, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000187, + 0x035, 0x00008187, + 0x035, 0x00010187, + 0x035, 0x00020188, + 0x035, 0x00028188, + 0x035, 0x00030188, + 0x035, 0x00040188, + 0x035, 0x00048188, + 0x035, 0x00050188, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000128, + 0x035, 0x00008128, + 0x035, 0x00010128, + 0x035, 0x000201C8, + 0x035, 0x000281C8, + 0x035, 0x000301C8, + 0x035, 0x000401C8, + 0x035, 0x000481C8, + 0x035, 0x000501C8, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000145, + 0x035, 0x00008145, + 0x035, 0x00010145, + 0x035, 0x00020196, + 0x035, 0x00028196, + 0x035, 0x00030196, + 0x035, 0x000401C7, + 0x035, 0x000481C7, + 0x035, 0x000501C7, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000128, + 0x035, 0x00008128, + 0x035, 0x00010128, + 0x035, 0x000201C8, + 0x035, 0x000281C8, + 0x035, 0x000301C8, + 0x035, 0x000401C8, + 0x035, 0x000481C8, + 0x035, 0x000501C8, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000187, + 0x035, 0x00008187, + 0x035, 0x00010187, + 0x035, 0x00020188, + 0x035, 0x00028188, + 0x035, 0x00030188, + 0x035, 0x00040188, + 0x035, 0x00048188, + 0x035, 0x00050188, + 0xA0000000, 0x00000000, + 0x035, 0x00000145, + 0x035, 0x00008145, + 0x035, 0x00010145, + 0x035, 0x00020196, + 0x035, 0x00028196, + 0x035, 0x00030196, + 0x035, 0x000401C7, + 0x035, 0x000481C7, + 0x035, 0x000501C7, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000010, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00085733, + 0x036, 0x0008D733, + 0x036, 0x00095733, + 0x036, 0x0009D733, + 0x036, 0x000A64B4, + 0x036, 0x000AE4B4, + 0x036, 0x000B64B4, + 0x036, 0x000BE4B4, + 0x036, 0x000C64B4, + 0x036, 0x000CE4B4, + 0x036, 0x000D64B4, + 0x036, 0x000DE4B4, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00085733, + 0x036, 0x0008D733, + 0x036, 0x00095733, + 0x036, 0x0009D733, + 0x036, 0x000A64B4, + 0x036, 0x000AE4B4, + 0x036, 0x000B64B4, + 0x036, 0x000BE4B4, + 0x036, 0x000C64B4, + 0x036, 0x000CE4B4, + 0x036, 0x000D64B4, + 0x036, 0x000DE4B4, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x000063B5, + 0x036, 0x0000E3B5, + 0x036, 0x000163B5, + 0x036, 0x0001E3B5, + 0x036, 0x000263B5, + 0x036, 0x0002E3B5, + 0x036, 0x000363B5, + 0x036, 0x0003E3B5, + 0x036, 0x000463B5, + 0x036, 0x0004E3B5, + 0x036, 0x000563B5, + 0x036, 0x0005E3B5, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x000056B3, + 0x036, 0x0000D6B3, + 0x036, 0x000156B3, + 0x036, 0x0001D6B3, + 0x036, 0x00026634, + 0x036, 0x0002E634, + 0x036, 0x00036634, + 0x036, 0x0003E634, + 0x036, 0x000467B4, + 0x036, 0x0004E7B4, + 0x036, 0x000567B4, + 0x036, 0x0005E7B4, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x000063B5, + 0x036, 0x0000E3B5, + 0x036, 0x000163B5, + 0x036, 0x0001E3B5, + 0x036, 0x000263B5, + 0x036, 0x0002E3B5, + 0x036, 0x000363B5, + 0x036, 0x0003E3B5, + 0x036, 0x000463B5, + 0x036, 0x0004E3B5, + 0x036, 0x000563B5, + 0x036, 0x0005E3B5, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x036, 0x00085733, + 0x036, 0x0008D733, + 0x036, 0x00095733, + 0x036, 0x0009D733, + 0x036, 0x000A64B4, + 0x036, 0x000AE4B4, + 0x036, 0x000B64B4, + 0x036, 0x000BE4B4, + 0x036, 0x000C64B4, + 0x036, 0x000CE4B4, + 0x036, 0x000D64B4, + 0x036, 0x000DE4B4, + 0xA0000000, 0x00000000, + 0x036, 0x000056B3, + 0x036, 0x0000D6B3, + 0x036, 0x000156B3, + 0x036, 0x0001D6B3, + 0x036, 0x00026634, + 0x036, 0x0002E634, + 0x036, 0x00036634, + 0x036, 0x0003E634, + 0x036, 0x000467B4, + 0x036, 0x0004E7B4, + 0x036, 0x000567B4, + 0x036, 0x0005E7B4, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000008, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000001C8, + 0x03C, 0x00000492, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000001C8, + 0x03C, 0x00000492, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000001B6, + 0x03C, 0x00000492, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x0000022A, + 0x03C, 0x00000594, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000001B6, + 0x03C, 0x00000492, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x000001C8, + 0x03C, 0x00000492, + 0xA0000000, 0x00000000, + 0x03C, 0x0000022A, + 0x03C, 0x00000594, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000800, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000800, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000800, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000820, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000820, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000800, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x03C, 0x00000800, + 0xA0000000, 0x00000000, + 0x03C, 0x00000900, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x018, 0x0001712A, + 0x0EF, 0x00000002, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x0004E400, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x0004E400, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x00002000, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x00002000, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x00002000, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x00002000, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x008, 0x0004E400, + 0xA0000000, 0x00000000, + 0x008, 0x00002000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0DF, 0x000000C0, + 0x01F, 0x00000064, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x000A7284, + 0x059, 0x000600EC, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x000A7284, + 0x059, 0x000600EC, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x00081184, + 0x059, 0x0006016C, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x00081184, + 0x059, 0x0006016C, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x00081184, + 0x059, 0x0006016C, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x058, 0x000A7284, + 0x059, 0x000600EC, + 0xA0000000, 0x00000000, + 0x058, 0x00081184, + 0x059, 0x0006016C, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000E8D73, + 0x062, 0x00093FC5, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000E8D73, + 0x062, 0x00093FC5, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000EFD83, + 0x062, 0x00093FCC, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000EAD53, + 0x062, 0x00093BC4, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000EFD83, + 0x062, 0x00093FCC, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x000E8D73, + 0x062, 0x00093FC5, + 0xA0000000, 0x00000000, + 0x061, 0x000EAD53, + 0x062, 0x00093BC4, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110E9, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110E9, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110EB, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110E9, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110E9, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110EB, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x063, 0x000110E9, + 0xA0000000, 0x00000000, + 0x063, 0x000714E9, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C27C, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C27C, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C27C, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C67C, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C27C, + 0x90000410, 0x00000000, 0x40000000, 0x00000000, + 0x064, 0x0001C27C, + 0xA0000000, 0x00000000, + 0x064, 0x0001C67C, + 0xB0000000, 0x00000000, + 0x80000111, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00091016, + 0x90000110, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00091016, + 0x90000210, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00093016, + 0x9000020c, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00093015, + 0x9000040c, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00093015, + 0x90000200, 0x00000000, 0x40000000, 0x00000000, + 0x065, 0x00093016, + 0xA0000000, 0x00000000, + 0x065, 0x00091016, + 0xB0000000, 0x00000000, + 0x018, 0x00000006, + 0x0EF, 0x00002000, + 0x03B, 0x0003824B, + 0x03B, 0x0003024B, + 0x03B, 0x0002844B, + 0x03B, 0x00020F4B, + 0x03B, 0x00018F4B, + 0x03B, 0x000104B2, + 0x03B, 0x00008049, + 0x03B, 0x00000148, + 0x03B, 0x0007824B, + 0x03B, 0x0007024B, + 0x03B, 0x0006824B, + 0x03B, 0x00060F4B, + 0x03B, 0x00058F4B, + 0x03B, 0x000504B2, + 0x03B, 0x00048049, + 0x03B, 0x00040148, + 0x0EF, 0x00000000, + 0x0EF, 0x00000100, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008D70, + 0x034, 0x00007D6D, + 0x034, 0x00006CEE, + 0x034, 0x00005CCC, + 0x034, 0x000044EC, + 0x034, 0x000034AC, + 0x034, 0x0000246D, + 0x034, 0x0000106F, + 0x034, 0x0000006C, + 0x0EF, 0x00000000, + 0x0ED, 0x00000010, + 0x044, 0x0000ADF2, + 0x044, 0x00009DEF, + 0x044, 0x00008DEC, + 0x044, 0x00007DE9, + 0x044, 0x00006CEC, + 0x044, 0x00005CE9, + 0x044, 0x000044EC, + 0x044, 0x000034E9, + 0x044, 0x0000246C, + 0x044, 0x00001469, + 0x044, 0x0000006C, + 0x0ED, 0x00000000, + 0x0ED, 0x00000001, + 0x040, 0x00038DA7, + 0x040, 0x000300C2, + 0x040, 0x000288E2, + 0x040, 0x000200B8, + 0x040, 0x000188A5, + 0x040, 0x00010FBC, + 0x040, 0x00008F71, + 0x040, 0x00000240, + 0x0ED, 0x00000000, + 0x0EF, 0x000020A2, + 0x0DF, 0x00000080, + 0x035, 0x00000120, + 0x035, 0x00008120, + 0x035, 0x00010120, + 0x036, 0x00000085, + 0x036, 0x00008085, + 0x036, 0x00010085, + 0x036, 0x00018085, + 0x0EF, 0x00000000, + 0x051, 0x00000C31, + 0x052, 0x00000622, + 0x053, 0x000FC70B, + 0x054, 0x0000017E, + 0x056, 0x00051DF3, + 0x051, 0x00000C01, + 0x052, 0x000006D6, + 0x053, 0x000FC649, + 0x070, 0x00049661, + 0x071, 0x0007843E, + 0x072, 0x00000382, + 0x074, 0x00051400, + 0x035, 0x00000160, + 0x035, 0x00008160, + 0x035, 0x00010160, + 0x036, 0x00000124, + 0x036, 0x00008124, + 0x036, 0x00010124, + 0x036, 0x00018124, + 0x0ED, 0x0000000C, + 0x045, 0x00000140, + 0x045, 0x00008140, + 0x045, 0x00010140, + 0x046, 0x00000124, + 0x046, 0x00008124, + 0x046, 0x00010124, + 0x046, 0x00018124, + 0x0DF, 0x00000088, + 0x0B3, 0x000F0E18, + 0x0B4, 0x0001214C, + 0x0B7, 0x0003000C, + 0x01C, 0x000539D2, + 0x0C4, 0x000AFE00, + 0x018, 0x0001F12A, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x018, 0x0001712A, + +}; + +void +ODM_ReadAndConfig_MP_8821A_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8821A_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8821A_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8821A(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8821A_RadioA(void) +{ + return 59; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 18, 19, 19, 19}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8821A[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8821A[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8821A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +#endif + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_PCIE( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_PCIE_8821A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +#endif + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8821A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8821A[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, + {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8821A[] = {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8821A[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}; +#endif + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8821A\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8821A, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT_8811AU_FEM.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8811AU_FEM[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", 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"5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "34", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "34", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "34", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "34", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "34", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "34", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "34", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "32", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "34", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "34", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "34", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "34", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "34", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "32", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "34", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "34", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8811AU_FEM)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8811AU_FEM; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8811AU_IPA.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8811AU_IPA[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", + "MKK", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", + "MKK", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", + "MKK", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", + "MKK", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", + "MKK", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", + "MKK", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", + "MKK", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", + "MKK", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", + "MKK", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", + "MKK", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", + "MKK", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", + "MKK", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", + "MKK", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", + "MKK", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", + "MKK", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "30", + "MKK", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "30", + "MKK", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "30", + "MKK", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "30", + "MKK", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "30", + "ETSI", "5G", "20M", "HT", "1T", "52", "30", + "MKK", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "30", + "ETSI", "5G", "20M", "HT", "1T", "56", "30", + "MKK", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "30", + "ETSI", "5G", "20M", "HT", "1T", "60", "30", + "MKK", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "30", + "ETSI", "5G", "20M", "HT", "1T", "64", "30", + "MKK", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "30", + "MKK", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "30", + "ETSI", "5G", "20M", "HT", "1T", "104", "30", + "MKK", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "30", + "ETSI", "5G", "20M", "HT", "1T", "108", "30", + "MKK", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "30", + "ETSI", "5G", "20M", "HT", "1T", "112", "30", + "MKK", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "30", + "ETSI", "5G", "20M", "HT", "1T", "116", "30", + "MKK", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "30", + "ETSI", "5G", "20M", "HT", "1T", "120", "30", + "MKK", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "30", + "ETSI", "5G", "20M", "HT", "1T", "124", "30", + "MKK", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "30", + "ETSI", "5G", "20M", "HT", "1T", "128", "30", + "MKK", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "30", + "MKK", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "30", + "MKK", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "30", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "30", + "ETSI", "5G", "20M", "HT", "1T", "149", "30", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "30", + "ETSI", "5G", "20M", "HT", "1T", "153", "30", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "30", + "ETSI", "5G", "20M", "HT", "1T", "157", "30", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "30", + "ETSI", "5G", "20M", "HT", "1T", "161", "30", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "30", + "ETSI", "5G", "20M", "HT", "1T", "165", "30", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "28", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "28", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "28", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "28", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "28", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "28", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "28", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "30", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "30", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "28", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8811AU_IPA)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8811AU_IPA; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8821A.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8821A[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", + "MKK", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", + "MKK", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", + "MKK", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", + "MKK", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", + "MKK", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", + "MKK", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", + "MKK", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", + "MKK", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", + "MKK", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", + "MKK", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", + "MKK", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", + "MKK", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", + "MKK", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", + "MKK", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", + "MKK", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "30", + "MKK", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "30", + "MKK", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "30", + "MKK", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "30", + "MKK", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "30", + "MKK", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "30", + "MKK", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "30", + "MKK", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "32", + "ETSI", "5G", "20M", "HT", "1T", "64", "30", + "MKK", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "30", + "MKK", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "30", + "MKK", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "30", + "MKK", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "30", + "MKK", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "30", + "MKK", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "30", + "MKK", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "30", + "MKK", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "30", + "MKK", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "30", + "MKK", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "30", + "MKK", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "30", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "30", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "30", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "30", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "30", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "30", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "30", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "20", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "28", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8821A_E202SA.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8821A_E202SA[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "27", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "27", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "27", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "27", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "16", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "26", + "MKK", "2.4G", "20M", "HT", "1T", "01", "26", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "26", + "MKK", "2.4G", "20M", "HT", "1T", "02", "26", + "FCC", "2.4G", "20M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "26", + "MKK", "2.4G", "20M", "HT", "1T", "03", "26", + "FCC", "2.4G", "20M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "26", + "MKK", "2.4G", "20M", "HT", "1T", "04", "26", + "FCC", "2.4G", "20M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "26", + "MKK", "2.4G", "20M", "HT", "1T", "05", "26", + "FCC", "2.4G", "20M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "26", + "MKK", "2.4G", "20M", "HT", "1T", "06", "26", + "FCC", "2.4G", "20M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "26", + "MKK", "2.4G", "20M", "HT", "1T", "07", "26", + "FCC", "2.4G", "20M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "26", + "MKK", "2.4G", "20M", "HT", "1T", "08", "26", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "26", + "MKK", "2.4G", "20M", "HT", "1T", "09", "26", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "26", + "MKK", "2.4G", "20M", "HT", "1T", "10", "26", + "FCC", "2.4G", "20M", "HT", "1T", "11", "15", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "26", + "MKK", "2.4G", "20M", "HT", "1T", "11", "26", + "FCC", "2.4G", "20M", "HT", "1T", "12", "15", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "26", + "MKK", "2.4G", "20M", "HT", "1T", "12", "26", + "FCC", "2.4G", "20M", "HT", "1T", "13", "15", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "26", + "MKK", "2.4G", "20M", "HT", "1T", "13", "26", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "16", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "22", + "MKK", "2.4G", "40M", "HT", "1T", "03", "22", + "FCC", "2.4G", "40M", "HT", "1T", "04", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "22", + "MKK", "2.4G", "40M", "HT", "1T", "04", "22", + "FCC", "2.4G", "40M", "HT", "1T", "05", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "22", + "MKK", "2.4G", "40M", "HT", "1T", "05", "22", + "FCC", "2.4G", "40M", "HT", "1T", "06", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "22", + "MKK", "2.4G", "40M", "HT", "1T", "06", "22", + "FCC", "2.4G", "40M", "HT", "1T", "07", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "22", + "MKK", "2.4G", "40M", "HT", "1T", "07", "22", + "FCC", "2.4G", "40M", "HT", "1T", "08", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "22", + "MKK", "2.4G", "40M", "HT", "1T", "08", "22", + "FCC", "2.4G", "40M", "HT", "1T", "09", "16", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "22", + "MKK", "2.4G", "40M", "HT", "1T", "09", "22", + "FCC", "2.4G", "40M", "HT", "1T", "10", "16", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "22", + "MKK", "2.4G", "40M", "HT", "1T", "10", "22", + "FCC", "2.4G", "40M", "HT", "1T", "11", "16", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "22", + "MKK", "2.4G", "40M", "HT", "1T", "11", "22", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "26", + "MKK", "5G", "20M", "OFDM", "1T", "36", "26", + "FCC", "5G", "20M", "OFDM", "1T", "40", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "26", + "MKK", "5G", "20M", "OFDM", "1T", "40", "26", + "FCC", "5G", "20M", "OFDM", "1T", "44", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "26", + "MKK", "5G", "20M", "OFDM", "1T", "44", "26", + "FCC", "5G", "20M", "OFDM", "1T", "48", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "26", + "MKK", "5G", "20M", "OFDM", "1T", "48", "26", + "FCC", "5G", "20M", "OFDM", "1T", "52", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "26", + "MKK", "5G", "20M", "OFDM", "1T", "52", "26", + "FCC", "5G", "20M", "OFDM", "1T", "56", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "26", + "MKK", "5G", "20M", "OFDM", "1T", "56", "26", + "FCC", "5G", "20M", "OFDM", "1T", "60", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "26", + "MKK", "5G", "20M", "OFDM", "1T", "60", "26", + "FCC", "5G", "20M", "OFDM", "1T", "64", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "26", + "MKK", "5G", "20M", "OFDM", "1T", "64", "26", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "26", + "MKK", "5G", "20M", "OFDM", "1T", "100", "26", + "FCC", "5G", "20M", "OFDM", "1T", "104", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "26", + "MKK", "5G", "20M", "OFDM", "1T", "104", "26", + "FCC", "5G", "20M", "OFDM", "1T", "108", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "26", + "MKK", "5G", "20M", "OFDM", "1T", "108", "26", + "FCC", "5G", "20M", "OFDM", "1T", "112", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "26", + "MKK", "5G", "20M", "OFDM", "1T", "112", "26", + "FCC", "5G", "20M", "OFDM", "1T", "116", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "26", + "MKK", "5G", "20M", "OFDM", "1T", "116", "26", + "FCC", "5G", "20M", "OFDM", "1T", "120", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "26", + "MKK", "5G", "20M", "OFDM", "1T", "120", "26", + "FCC", "5G", "20M", "OFDM", "1T", "124", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "26", + "MKK", "5G", "20M", "OFDM", "1T", "124", "26", + "FCC", "5G", "20M", "OFDM", "1T", "128", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "26", + "MKK", "5G", "20M", "OFDM", "1T", "128", "26", + "FCC", "5G", "20M", "OFDM", "1T", "132", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "26", + "MKK", "5G", "20M", "OFDM", "1T", "132", "26", + "FCC", "5G", "20M", "OFDM", "1T", "136", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "26", + "MKK", "5G", "20M", "OFDM", "1T", "136", "26", + "FCC", "5G", "20M", "OFDM", "1T", "140", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "26", + "MKK", "5G", "20M", "OFDM", "1T", "140", "26", + "FCC", "5G", "20M", "OFDM", "1T", "149", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "26", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "26", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "26", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "26", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "26", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "24", + "ETSI", "5G", "20M", "HT", "1T", "36", "24", + "MKK", "5G", "20M", "HT", "1T", "36", "24", + "FCC", "5G", "20M", "HT", "1T", "40", "24", + "ETSI", "5G", "20M", "HT", "1T", "40", "24", + "MKK", "5G", "20M", "HT", "1T", "40", "24", + "FCC", "5G", "20M", "HT", "1T", "44", "24", + "ETSI", "5G", "20M", "HT", "1T", "44", "24", + "MKK", "5G", "20M", "HT", "1T", "44", "24", + "FCC", "5G", "20M", "HT", "1T", "48", "24", + "ETSI", "5G", "20M", "HT", "1T", "48", "24", + "MKK", "5G", "20M", "HT", "1T", "48", "24", + "FCC", "5G", "20M", "HT", "1T", "52", "24", + "ETSI", "5G", "20M", "HT", "1T", "52", "24", + "MKK", "5G", "20M", "HT", "1T", "52", "24", + "FCC", "5G", "20M", "HT", "1T", "56", "24", + "ETSI", "5G", "20M", "HT", "1T", "56", "24", + "MKK", "5G", "20M", "HT", "1T", "56", "24", + "FCC", "5G", "20M", "HT", "1T", "60", "24", + "ETSI", "5G", "20M", "HT", "1T", "60", "24", + "MKK", "5G", "20M", "HT", "1T", "60", "24", + "FCC", "5G", "20M", "HT", "1T", "64", "24", + "ETSI", "5G", "20M", "HT", "1T", "64", "24", + "MKK", "5G", "20M", "HT", "1T", "64", "24", + "FCC", "5G", "20M", "HT", "1T", "100", "24", + "ETSI", "5G", "20M", "HT", "1T", "100", "24", + "MKK", "5G", "20M", "HT", "1T", "100", "24", + "FCC", "5G", "20M", "HT", "1T", "104", "24", + "ETSI", "5G", "20M", "HT", "1T", "104", "24", + "MKK", "5G", "20M", "HT", "1T", "104", "24", + "FCC", "5G", "20M", "HT", "1T", "108", "24", + "ETSI", "5G", "20M", "HT", "1T", "108", "24", + "MKK", "5G", "20M", "HT", "1T", "108", "24", + "FCC", "5G", "20M", "HT", "1T", "112", "24", + "ETSI", "5G", "20M", "HT", "1T", "112", "24", + "MKK", "5G", "20M", "HT", "1T", "112", "24", + "FCC", "5G", "20M", "HT", "1T", "116", "24", + "ETSI", "5G", "20M", "HT", "1T", "116", "24", + "MKK", "5G", "20M", "HT", "1T", "116", "24", + "FCC", "5G", "20M", "HT", "1T", "120", "24", + "ETSI", "5G", "20M", "HT", "1T", "120", "24", + "MKK", "5G", "20M", "HT", "1T", "120", "24", + "FCC", "5G", "20M", "HT", "1T", "124", "24", + "ETSI", "5G", "20M", "HT", "1T", "124", "24", + "MKK", "5G", "20M", "HT", "1T", "124", "24", + "FCC", "5G", "20M", "HT", "1T", "128", "24", + "ETSI", "5G", "20M", "HT", "1T", "128", "24", + "MKK", "5G", "20M", "HT", "1T", "128", "24", + "FCC", "5G", "20M", "HT", "1T", "132", "24", + "ETSI", "5G", "20M", "HT", "1T", "132", "24", + "MKK", "5G", "20M", "HT", "1T", "132", "24", + "FCC", "5G", "20M", "HT", "1T", "136", "24", + "ETSI", "5G", "20M", "HT", "1T", "136", "24", + "MKK", "5G", "20M", "HT", "1T", "136", "24", + "FCC", "5G", "20M", "HT", "1T", "140", "24", + "ETSI", "5G", "20M", "HT", "1T", "140", "24", + "MKK", "5G", "20M", "HT", "1T", "140", "24", + "FCC", "5G", "20M", "HT", "1T", "149", "24", + "ETSI", "5G", "20M", "HT", "1T", "149", "24", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "24", + "ETSI", "5G", "20M", "HT", "1T", "153", "24", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "24", + "ETSI", "5G", "20M", "HT", "1T", "157", "24", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "24", + "ETSI", "5G", "20M", "HT", "1T", "161", "24", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "24", + "ETSI", "5G", "20M", "HT", "1T", "165", "24", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "20", + "ETSI", "5G", "40M", "HT", "1T", "38", "20", + "MKK", "5G", "40M", "HT", "1T", "38", "20", + "FCC", "5G", "40M", "HT", "1T", "46", "20", + "ETSI", "5G", "40M", "HT", "1T", "46", "20", + "MKK", "5G", "40M", "HT", "1T", "46", "20", + "FCC", "5G", "40M", "HT", "1T", "54", "20", + "ETSI", "5G", "40M", "HT", "1T", "54", "20", + "MKK", "5G", "40M", "HT", "1T", "54", "20", + "FCC", "5G", "40M", "HT", "1T", "62", "20", + "ETSI", "5G", "40M", "HT", "1T", "62", "20", + "MKK", "5G", "40M", "HT", "1T", "62", "20", + "FCC", "5G", "40M", "HT", "1T", "102", "20", + "ETSI", "5G", "40M", "HT", "1T", "102", "20", + "MKK", "5G", "40M", "HT", "1T", "102", "20", + "FCC", "5G", "40M", "HT", "1T", "110", "20", + "ETSI", "5G", "40M", "HT", "1T", "110", "20", + "MKK", "5G", "40M", "HT", "1T", "110", "20", + "FCC", "5G", "40M", "HT", "1T", "118", "20", + "ETSI", "5G", "40M", "HT", "1T", "118", "20", + "MKK", "5G", "40M", "HT", "1T", "118", "20", + "FCC", "5G", "40M", "HT", "1T", "126", "20", + "ETSI", "5G", "40M", "HT", "1T", "126", "20", + "MKK", "5G", "40M", "HT", "1T", "126", "20", + "FCC", "5G", "40M", "HT", "1T", "134", "20", + "ETSI", "5G", "40M", "HT", "1T", "134", "20", + "MKK", "5G", "40M", "HT", "1T", "134", "20", + "FCC", "5G", "40M", "HT", "1T", "151", "20", + "ETSI", "5G", "40M", "HT", "1T", "151", "20", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "20", + "ETSI", "5G", "40M", "HT", "1T", "159", "20", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "16", + "ETSI", "5G", "80M", "VHT", "1T", "42", "16", + "MKK", "5G", "80M", "VHT", "1T", "42", "16", + "FCC", "5G", "80M", "VHT", "1T", "58", "16", + "ETSI", "5G", "80M", "VHT", "1T", "58", "16", + "MKK", "5G", "80M", "VHT", "1T", "58", "16", + "FCC", "5G", "80M", "VHT", "1T", "106", "16", + "ETSI", "5G", "80M", "VHT", "1T", "106", "16", + "MKK", "5G", "80M", "VHT", "1T", "106", "16", + "FCC", "5G", "80M", "VHT", "1T", "122", "16", + "ETSI", "5G", "80M", "VHT", "1T", "122", "16", + "MKK", "5G", "80M", "VHT", "1T", "122", "16", + "FCC", "5G", "80M", "VHT", "1T", "155", "16", + "ETSI", "5G", "80M", "VHT", "1T", "155", "16", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_E202SA)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_E202SA; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_13dBm.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "26", + "MKK", "5G", "20M", "OFDM", "1T", "36", "26", + "FCC", "5G", "20M", "OFDM", "1T", "40", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "26", + "MKK", "5G", "20M", "OFDM", "1T", "40", "26", + "FCC", "5G", "20M", "OFDM", "1T", "44", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "26", + "MKK", "5G", "20M", "OFDM", "1T", "44", "26", + "FCC", "5G", "20M", "OFDM", "1T", "48", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "26", + "MKK", "5G", "20M", "OFDM", "1T", "48", "26", + "FCC", "5G", "20M", "OFDM", "1T", "52", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "26", + "MKK", "5G", "20M", "OFDM", "1T", "52", "26", + "FCC", "5G", "20M", "OFDM", "1T", "56", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "26", + "MKK", "5G", "20M", "OFDM", "1T", "56", "26", + "FCC", "5G", "20M", "OFDM", "1T", "60", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "26", + "MKK", "5G", "20M", "OFDM", "1T", "60", "26", + "FCC", "5G", "20M", "OFDM", "1T", "64", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "26", + "MKK", "5G", "20M", "OFDM", "1T", "64", "26", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "26", + "MKK", "5G", "20M", "OFDM", "1T", "100", "26", + "FCC", "5G", "20M", "OFDM", "1T", "104", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "26", + "MKK", "5G", "20M", "OFDM", "1T", "104", "26", + "FCC", "5G", "20M", "OFDM", "1T", "108", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "26", + "MKK", "5G", "20M", "OFDM", "1T", "108", "26", + "FCC", "5G", "20M", "OFDM", "1T", "112", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "26", + "MKK", "5G", "20M", "OFDM", "1T", "112", "26", + "FCC", "5G", "20M", "OFDM", "1T", "116", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "26", + "MKK", "5G", "20M", "OFDM", "1T", "116", "26", + "FCC", "5G", "20M", "OFDM", "1T", "120", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "26", + "MKK", "5G", "20M", "OFDM", "1T", "120", "26", + "FCC", "5G", "20M", "OFDM", "1T", "124", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "26", + "MKK", "5G", "20M", "OFDM", "1T", "124", "26", + "FCC", "5G", "20M", "OFDM", "1T", "128", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "26", + "MKK", "5G", "20M", "OFDM", "1T", "128", "26", + "FCC", "5G", "20M", "OFDM", "1T", "132", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "26", + "MKK", "5G", "20M", "OFDM", "1T", "132", "26", + "FCC", "5G", "20M", "OFDM", "1T", "136", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "26", + "MKK", "5G", "20M", "OFDM", "1T", "136", "26", + "FCC", "5G", "20M", "OFDM", "1T", "140", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "26", + "MKK", "5G", "20M", "OFDM", "1T", "140", "26", + "FCC", "5G", "20M", "OFDM", "1T", "149", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "26", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "26", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "26", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "26", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "26", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "26", + "ETSI", "5G", "20M", "HT", "1T", "36", "26", + "MKK", "5G", "20M", "HT", "1T", "36", "26", + "FCC", "5G", "20M", "HT", "1T", "40", "26", + "ETSI", "5G", "20M", "HT", "1T", "40", "26", + "MKK", "5G", "20M", "HT", "1T", "40", "26", + "FCC", "5G", "20M", "HT", "1T", "44", "26", + "ETSI", "5G", "20M", "HT", "1T", "44", "26", + "MKK", "5G", "20M", "HT", "1T", "44", "26", + "FCC", "5G", "20M", "HT", "1T", "48", "26", + "ETSI", "5G", "20M", "HT", "1T", "48", "26", + "MKK", "5G", "20M", "HT", "1T", "48", "26", + "FCC", "5G", "20M", "HT", "1T", "52", "26", + "ETSI", "5G", "20M", "HT", "1T", "52", "26", + "MKK", "5G", "20M", "HT", "1T", "52", "26", + "FCC", "5G", "20M", "HT", "1T", "56", "26", + "ETSI", "5G", "20M", "HT", "1T", "56", "26", + "MKK", "5G", "20M", "HT", "1T", "56", "26", + "FCC", "5G", "20M", "HT", "1T", "60", "26", + "ETSI", "5G", "20M", "HT", "1T", "60", "26", + "MKK", "5G", "20M", "HT", "1T", "60", "26", + "FCC", "5G", "20M", "HT", "1T", "64", "26", + "ETSI", "5G", "20M", "HT", "1T", "64", "26", + "MKK", "5G", "20M", "HT", "1T", "64", "26", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "26", + "MKK", "5G", "20M", "HT", "1T", "100", "26", + "FCC", "5G", "20M", "HT", "1T", "104", "26", + "ETSI", "5G", "20M", "HT", "1T", "104", "26", + "MKK", "5G", "20M", "HT", "1T", "104", "26", + "FCC", "5G", "20M", "HT", "1T", "108", "26", + "ETSI", "5G", "20M", "HT", "1T", "108", "26", + "MKK", "5G", "20M", "HT", "1T", "108", "26", + "FCC", "5G", "20M", "HT", "1T", "112", "26", + "ETSI", "5G", "20M", "HT", "1T", "112", "26", + "MKK", "5G", "20M", "HT", "1T", "112", "26", + "FCC", "5G", "20M", "HT", "1T", "116", "26", + "ETSI", "5G", "20M", "HT", "1T", "116", "26", + "MKK", "5G", "20M", "HT", "1T", "116", "26", + "FCC", "5G", "20M", "HT", "1T", "120", "26", + "ETSI", "5G", "20M", "HT", "1T", "120", "26", + "MKK", "5G", "20M", "HT", "1T", "120", "26", + "FCC", "5G", "20M", "HT", "1T", "124", "26", + "ETSI", "5G", "20M", "HT", "1T", "124", "26", + "MKK", "5G", "20M", "HT", "1T", "124", "26", + "FCC", "5G", "20M", "HT", "1T", "128", "26", + "ETSI", "5G", "20M", "HT", "1T", "128", "26", + "MKK", "5G", "20M", "HT", "1T", "128", "26", + "FCC", "5G", "20M", "HT", "1T", "132", "26", + "ETSI", "5G", "20M", "HT", "1T", "132", "26", + "MKK", "5G", "20M", "HT", "1T", "132", "26", + "FCC", "5G", "20M", "HT", "1T", "136", "26", + "ETSI", "5G", "20M", "HT", "1T", "136", "26", + "MKK", "5G", "20M", "HT", "1T", "136", "26", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "26", + "MKK", "5G", "20M", "HT", "1T", "140", "26", + "FCC", "5G", "20M", "HT", "1T", "149", "26", + "ETSI", "5G", "20M", "HT", "1T", "149", "26", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "26", + "ETSI", "5G", "20M", "HT", "1T", "153", "26", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "26", + "ETSI", "5G", "20M", "HT", "1T", "157", "26", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "26", + "ETSI", "5G", "20M", "HT", "1T", "161", "26", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "26", + "ETSI", "5G", "20M", "HT", "1T", "165", "26", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "26", + "ETSI", "5G", "20M", "HT", "2T", "36", "26", + "MKK", "5G", "20M", "HT", "2T", "36", "26", + "FCC", "5G", "20M", "HT", "2T", "40", "26", + "ETSI", "5G", "20M", "HT", "2T", "40", "26", + "MKK", "5G", "20M", "HT", "2T", "40", "26", + "FCC", "5G", "20M", "HT", "2T", "44", "26", + "ETSI", "5G", "20M", "HT", "2T", "44", "26", + "MKK", "5G", "20M", "HT", "2T", "44", "26", + "FCC", "5G", "20M", "HT", "2T", "48", "26", + "ETSI", "5G", "20M", "HT", "2T", "48", "26", + "MKK", "5G", "20M", "HT", "2T", "48", "26", + "FCC", "5G", "20M", "HT", "2T", "52", "26", + "ETSI", "5G", "20M", "HT", "2T", "52", "26", + "MKK", "5G", "20M", "HT", "2T", "52", "26", + "FCC", "5G", "20M", "HT", "2T", "56", "26", + "ETSI", "5G", "20M", "HT", "2T", "56", "26", + "MKK", "5G", "20M", "HT", "2T", "56", "26", + "FCC", "5G", "20M", "HT", "2T", "60", "26", + "ETSI", "5G", "20M", "HT", "2T", "60", "26", + "MKK", "5G", "20M", "HT", "2T", "60", "26", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "26", + "MKK", "5G", "20M", "HT", "2T", "64", "26", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "26", + "MKK", "5G", "20M", "HT", "2T", "100", "26", + "FCC", "5G", "20M", "HT", "2T", "104", "26", + "ETSI", "5G", "20M", "HT", "2T", "104", "26", + "MKK", "5G", "20M", "HT", "2T", "104", "26", + "FCC", "5G", "20M", "HT", "2T", "108", "26", + "ETSI", "5G", "20M", "HT", "2T", "108", "26", + "MKK", "5G", "20M", "HT", "2T", "108", "26", + "FCC", "5G", "20M", "HT", "2T", "112", "26", + "ETSI", "5G", "20M", "HT", "2T", "112", "26", + "MKK", "5G", "20M", "HT", "2T", "112", "26", + "FCC", "5G", "20M", "HT", "2T", "116", "26", + "ETSI", "5G", "20M", "HT", "2T", "116", "26", + "MKK", "5G", "20M", "HT", "2T", "116", "26", + "FCC", "5G", "20M", "HT", "2T", "120", "26", + "ETSI", "5G", "20M", "HT", "2T", "120", "26", + "MKK", "5G", "20M", "HT", "2T", "120", "26", + "FCC", "5G", "20M", "HT", "2T", "124", "26", + "ETSI", "5G", "20M", "HT", "2T", "124", "26", + "MKK", "5G", "20M", "HT", "2T", "124", "26", + "FCC", "5G", "20M", "HT", "2T", "128", "26", + "ETSI", "5G", "20M", "HT", "2T", "128", "26", + "MKK", "5G", "20M", "HT", "2T", "128", "26", + "FCC", "5G", "20M", "HT", "2T", "132", "26", + "ETSI", "5G", "20M", "HT", "2T", "132", "26", + "MKK", "5G", "20M", "HT", "2T", "132", "26", + "FCC", "5G", "20M", "HT", "2T", "136", "26", + "ETSI", "5G", "20M", "HT", "2T", "136", "26", + "MKK", "5G", "20M", "HT", "2T", "136", "26", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "26", + "MKK", "5G", "20M", "HT", "2T", "140", "26", + "FCC", "5G", "20M", "HT", "2T", "149", "26", + "ETSI", "5G", "20M", "HT", "2T", "149", "26", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "26", + "ETSI", "5G", "20M", "HT", "2T", "153", "26", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "26", + "ETSI", "5G", "20M", "HT", "2T", "157", "26", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "26", + "ETSI", "5G", "20M", "HT", "2T", "161", "26", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "26", + "ETSI", "5G", "20M", "HT", "2T", "165", "26", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "26", + "MKK", "5G", "40M", "HT", "1T", "38", "26", + "FCC", "5G", "40M", "HT", "1T", "46", "26", + "ETSI", "5G", "40M", "HT", "1T", "46", "26", + "MKK", "5G", "40M", "HT", "1T", "46", "26", + "FCC", "5G", "40M", "HT", "1T", "54", "26", + "ETSI", "5G", "40M", "HT", "1T", "54", "26", + "MKK", "5G", "40M", "HT", "1T", "54", "26", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "26", + "MKK", "5G", "40M", "HT", "1T", "62", "26", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "26", + "MKK", "5G", "40M", "HT", "1T", "102", "26", + "FCC", "5G", "40M", "HT", "1T", "110", "26", + "ETSI", "5G", "40M", "HT", "1T", "110", "26", + "MKK", "5G", "40M", "HT", "1T", "110", "26", + "FCC", "5G", "40M", "HT", "1T", "118", "26", + "ETSI", "5G", "40M", "HT", "1T", "118", "26", + "MKK", "5G", "40M", "HT", "1T", "118", "26", + "FCC", "5G", "40M", "HT", "1T", "126", "26", + "ETSI", "5G", "40M", "HT", "1T", "126", "26", + "MKK", "5G", "40M", "HT", "1T", "126", "26", + "FCC", "5G", "40M", "HT", "1T", "134", "26", + "ETSI", "5G", "40M", "HT", "1T", "134", "26", + "MKK", "5G", "40M", "HT", "1T", "134", "26", + "FCC", "5G", "40M", "HT", "1T", "151", "26", + "ETSI", "5G", "40M", "HT", "1T", "151", "26", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "26", + "ETSI", "5G", "40M", "HT", "1T", "159", "26", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "26", + "MKK", "5G", "40M", "HT", "2T", "38", "26", + "FCC", "5G", "40M", "HT", "2T", "46", "26", + "ETSI", "5G", "40M", "HT", "2T", "46", "26", + "MKK", "5G", "40M", "HT", "2T", "46", "26", + "FCC", "5G", "40M", "HT", "2T", "54", "26", + "ETSI", "5G", "40M", "HT", "2T", "54", "26", + "MKK", "5G", "40M", "HT", "2T", "54", "26", + "FCC", "5G", "40M", "HT", "2T", "62", "26", + "ETSI", "5G", "40M", "HT", "2T", "62", "26", + "MKK", "5G", "40M", "HT", "2T", "62", "26", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "26", + "MKK", "5G", "40M", "HT", "2T", "102", "26", + "FCC", "5G", "40M", "HT", "2T", "110", "26", + "ETSI", "5G", "40M", "HT", "2T", "110", "26", + "MKK", "5G", "40M", "HT", "2T", "110", "26", + "FCC", "5G", "40M", "HT", "2T", "118", "26", + "ETSI", "5G", "40M", "HT", "2T", "118", "26", + "MKK", "5G", "40M", "HT", "2T", "118", "26", + "FCC", "5G", "40M", "HT", "2T", "126", "26", + "ETSI", "5G", "40M", "HT", "2T", "126", "26", + "MKK", "5G", "40M", "HT", "2T", "126", "26", + "FCC", "5G", "40M", "HT", "2T", "134", "26", + "ETSI", "5G", "40M", "HT", "2T", "134", "26", + "MKK", "5G", "40M", "HT", "2T", "134", "26", + "FCC", "5G", "40M", "HT", "2T", "151", "26", + "ETSI", "5G", "40M", "HT", "2T", "151", "26", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "26", + "ETSI", "5G", "40M", "HT", "2T", "159", "26", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "26", + "MKK", "5G", "80M", "VHT", "1T", "42", "26", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "26", + "MKK", "5G", "80M", "VHT", "1T", "58", "26", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "26", + "MKK", "5G", "80M", "VHT", "1T", "106", "26", + "FCC", "5G", "80M", "VHT", "1T", "122", "20", + "ETSI", "5G", "80M", "VHT", "1T", "122", "26", + "MKK", "5G", "80M", "VHT", "1T", "122", "26", + "FCC", "5G", "80M", "VHT", "1T", "155", "26", + "ETSI", "5G", "80M", "VHT", "1T", "155", "26", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "26", + "ETSI", "5G", "80M", "VHT", "2T", "42", "26", + "MKK", "5G", "80M", "VHT", "2T", "42", "26", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "26", + "MKK", "5G", "80M", "VHT", "2T", "58", "26", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "26", + "MKK", "5G", "80M", "VHT", "2T", "106", "26", + "FCC", "5G", "80M", "VHT", "2T", "122", "26", + "ETSI", "5G", "80M", "VHT", "2T", "122", "26", + "MKK", "5G", "80M", "VHT", "2T", "122", "26", + "FCC", "5G", "80M", "VHT", "2T", "155", "26", + "ETSI", "5G", "80M", "VHT", "2T", "155", "26", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_5mm.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", + "MKK", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", + "MKK", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", + "MKK", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", + "MKK", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", + "MKK", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", + "MKK", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", + "MKK", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", + "MKK", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", + "MKK", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", + "MKK", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", + "MKK", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", + "MKK", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", + "MKK", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", + "MKK", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", + "MKK", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "30", + "MKK", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "30", + "MKK", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "30", + "MKK", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "30", + "MKK", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "28", + "ETSI", "5G", "20M", "HT", "1T", "52", "30", + "MKK", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "28", + "ETSI", "5G", "20M", "HT", "1T", "56", "30", + "MKK", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "28", + "ETSI", "5G", "20M", "HT", "1T", "60", "30", + "MKK", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "30", + "MKK", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "28", + "ETSI", "5G", "20M", "HT", "1T", "100", "30", + "MKK", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "28", + "ETSI", "5G", "20M", "HT", "1T", "104", "30", + "MKK", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "28", + "ETSI", "5G", "20M", "HT", "1T", "108", "30", + "MKK", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "28", + "ETSI", "5G", "20M", "HT", "1T", "112", "30", + "MKK", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "28", + "ETSI", "5G", "20M", "HT", "1T", "116", "30", + "MKK", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "28", + "ETSI", "5G", "20M", "HT", "1T", "120", "30", + "MKK", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "28", + "ETSI", "5G", "20M", "HT", "1T", "124", "30", + "MKK", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "28", + "ETSI", "5G", "20M", "HT", "1T", "128", "30", + "MKK", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "28", + "ETSI", "5G", "20M", "HT", "1T", "132", "30", + "MKK", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "28", + "ETSI", "5G", "20M", "HT", "1T", "136", "30", + "MKK", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "28", + "ETSI", "5G", "20M", "HT", "1T", "149", "30", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "28", + "ETSI", "5G", "20M", "HT", "1T", "153", "30", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "28", + "ETSI", "5G", "20M", "HT", "1T", "157", "30", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "28", + "ETSI", "5G", "20M", "HT", "1T", "161", "30", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "28", + "ETSI", "5G", "20M", "HT", "1T", "165", "30", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "28", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "28", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "28", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "28", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "28", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "28", + "ETSI", "5G", "40M", "HT", "1T", "151", "30", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "28", + "ETSI", "5G", "40M", "HT", "1T", "159", "30", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "20", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "26", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_5mm; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_8mm.TXT +******************************************************************************/ + +const char *Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "28", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "32", + "MKK", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "32", + "MKK", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "32", + "MKK", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "32", + "MKK", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "32", + "MKK", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "32", + "MKK", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "32", + "MKK", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "32", + "MKK", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "32", + "MKK", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "32", + "MKK", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "32", + "MKK", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "32", + "MKK", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "32", + "MKK", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "22", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "32", + "MKK", "2.4G", "40M", "HT", "2T", "12", "32", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "32", + "MKK", "2.4G", "40M", "HT", "2T", "13", "32", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "30", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "30", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "30", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "30", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "30", + "MKK", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "30", + "MKK", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "30", + "MKK", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "30", + "MKK", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "30", + "MKK", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "30", + "MKK", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "30", + "MKK", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "30", + "MKK", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "30", + "MKK", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "30", + "MKK", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "30", + "MKK", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "30", + "MKK", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "30", + "MKK", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "30", + "MKK", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "30", + "MKK", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "30", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "30", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "30", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "30", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "30", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "32", + "ETSI", "5G", "20M", "HT", "1T", "36", "30", + "MKK", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "30", + "MKK", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "30", + "MKK", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "30", + "MKK", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "30", + "MKK", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "30", + "MKK", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "30", + "MKK", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "32", + "ETSI", "5G", "20M", "HT", "1T", "64", "30", + "MKK", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "28", + "ETSI", "5G", "20M", "HT", "1T", "100", "30", + "MKK", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "28", + "ETSI", "5G", "20M", "HT", "1T", "104", "30", + "MKK", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "28", + "ETSI", "5G", "20M", "HT", "1T", "108", "30", + "MKK", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "30", + "MKK", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "30", + "MKK", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "30", + "MKK", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "30", + "MKK", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "30", + "MKK", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "30", + "MKK", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "30", + "MKK", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "30", + "MKK", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "28", + "ETSI", "5G", "20M", "HT", "1T", "149", "30", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "28", + "ETSI", "5G", "20M", "HT", "1T", "153", "30", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "30", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "30", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "30", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "26", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "28", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "28", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "28", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "28", + "ETSI", "5G", "40M", "HT", "1T", "151", "30", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "30", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "22", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "30", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "30", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "20", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "28", + "ETSI", "5G", "80M", "VHT", "1T", "155", "30", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8821A_TXPWR_LMT_8821A_SAR_8mm; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.h index a23eb1f3753..40a7f5247af 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halhwimg8821a_rf.h @@ -1,149 +1,149 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.18*/ -#if (RTL8821A_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8821A_H -#define __INC_MP_RF_HW_IMG_8821A_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_RadioA(void); - -/****************************************************************************** -* TxPowerTrack_AP.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_AP(void); - -/****************************************************************************** -* TxPowerTrack_PCIE.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_PCIE(void); - -/****************************************************************************** -* TxPowerTrack_SDIO.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_SDIO(void); - -/****************************************************************************** -* TxPowerTrack_USB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_USB(void); - -/****************************************************************************** -* TXPWR_LMT_8811AU_FEM.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8811AU_FEM(void); - -/****************************************************************************** -* TXPWR_LMT_8811AU_IPA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8811AU_IPA(void); - -/****************************************************************************** -* TXPWR_LMT_8821A.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A(void); - -/****************************************************************************** -* TXPWR_LMT_8821A_E202SA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_E202SA(void); - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_13dBm.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm(void); - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_5mm.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_5mm(void); - -/****************************************************************************** -* TXPWR_LMT_8821A_SAR_8mm.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_8mm(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8821A_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8821A_H +#define __INC_MP_RF_HW_IMG_8821A_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_PCIE.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_PCIE(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT_8811AU_FEM.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_FEM(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8811AU_FEM(void); + +/****************************************************************************** +* TXPWR_LMT_8811AU_IPA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8811AU_IPA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8811AU_IPA(void); + +/****************************************************************************** +* TXPWR_LMT_8821A.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A(void); + +/****************************************************************************** +* TXPWR_LMT_8821A_E202SA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_E202SA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_E202SA(void); + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_13dBm.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_13dBm(void); + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_5mm.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_5mm(void); + +/****************************************************************************** +* TXPWR_LMT_8821A_SAR_8mm.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8821A_TXPWR_LMT_8821A_SAR_8mm(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8821A_TXPWR_LMT_8821A_SAR_8mm(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.c index 2c98fd98287..e87caf1c27d 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.c @@ -1,327 +1,327 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8821A 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3 ============================================================ -//3 Tx Power Tracking -//3 ============================================================ - -VOID -ODM_TxPwrTrackSetPwr8821A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte PwrTrackingLimit = 26; //+1.0dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u1Byte i = 0; - u4Byte finalBbSwingIdx[1]; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8821A\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit = 32; //+4dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit = 30; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit = 28; //+2dB - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit = 28; //+2dB - - //2 VHT - else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT1SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT1SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT1SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else - PwrTrackingLimit = 24; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); - - if (Method == BBSWING) - { - if (RFPath == ODM_RF_PATH_A) - { - finalBbSwingIdx[ODM_RF_PATH_A] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", - pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); - } - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) - { - if (Final_OFDM_Swing_Index > PwrTrackingLimit) /*BBSwing higher then Limit*/ - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index <= 0) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); - - if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ - { - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); - } - } - } - } - else - { - return; - } -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8821A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -void ConfigureTxpowerTrack_8821A( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; - pConfig->RfPathCount = MAX_PATH_NUM_8821A; - pConfig->ThermalRegAddr = RF_T_METER_8812A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8821A; - pConfig->DoIQK = DoIQK_8821A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8821A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8821A; -} - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - -VOID -PHY_LCCalibrate_8821A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u8Byte StartTime; - u8Byte ProgressingTime; - - StartTime = ODM_GetCurrentTime( pDM_Odm); - PHY_LCCalibrate_8812A(pDM_Odm); - ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %lld\n", ProgressingTime)); -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8821A 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3 ============================================================ +//3 Tx Power Tracking +//3 ============================================================ + +VOID +ODM_TxPwrTrackSetPwr8821A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte PwrTrackingLimit = 26; //+1.0dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u1Byte i = 0; + u4Byte finalBbSwingIdx[1]; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8821A\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit = 32; //+4dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit = 30; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit = 28; //+2dB + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit = 28; //+2dB + + //2 VHT + else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT1SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT1SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT1SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else + PwrTrackingLimit = 24; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); + + if (Method == BBSWING) + { + if (RFPath == ODM_RF_PATH_A) + { + finalBbSwingIdx[ODM_RF_PATH_A] = (pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); + } + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath)); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) + { + if (Final_OFDM_Swing_Index > PwrTrackingLimit) /*BBSwing higher then Limit*/ + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index <= 0) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/ + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n")); + } + } + } + } + else + { + return; + } +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8821A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +void ConfigureTxpowerTrack_8821A( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; + pConfig->RfPathCount = MAX_PATH_NUM_8821A; + pConfig->ThermalRegAddr = RF_T_METER_8812A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8821A; + pConfig->DoIQK = DoIQK_8821A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8821A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8821A; +} + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + +VOID +PHY_LCCalibrate_8821A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8Byte StartTime; + u8Byte ProgressingTime; + + StartTime = ODM_GetCurrentTime( pDM_Odm); + PHY_LCCalibrate_8812A(pDM_Odm); + ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %lld\n", ProgressingTime)); +} + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.h index 688a95e01c4..a804af1edac 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_ce.h @@ -1,52 +1,52 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8821A_H__ -#define __HAL_PHY_RF_8821A_H__ - -/*--------------------------Define Parameters-------------------------------*/ - -void ConfigureTxpowerTrack_8821A( - PTXPWRTRACK_CFG pConfig - ); - -VOID -ODM_TxPwrTrackSetPwr8821A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -PHY_LCCalibrate_8821A( - IN PVOID pDM_VOID -); - -VOID -GetDeltaSwingTable_8821A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -); -#endif // #ifndef __HAL_PHY_RF_8821A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8821A_H__ +#define __HAL_PHY_RF_8821A_H__ + +/*--------------------------Define Parameters-------------------------------*/ + +void ConfigureTxpowerTrack_8821A( + PTXPWRTRACK_CFG pConfig + ); + +VOID +ODM_TxPwrTrackSetPwr8821A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +PHY_LCCalibrate_8821A( + IN PVOID pDM_VOID +); + +VOID +GetDeltaSwingTable_8821A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +); +#endif // #ifndef __HAL_PHY_RF_8821A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.c b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.c index 006cc0dd6d4..efc1585ca76 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.c @@ -1,1151 +1,1151 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. -#define ODM_TXPWRTRACK_MAX_IDX8821A 6 - -/*---------------------------Define Local Constant---------------------------*/ - - -//3 ============================================================ -//3 Tx Power Tracking -//3 ============================================================ - - -void setIqkMatrix_8821A( - PDM_ODM_T pDM_Odm, - u1Byte OFDM_index, - u1Byte RFPath, - s4Byte IqkResult_X, - s4Byte IqkResult_Y - ) -{ - s4Byte ele_A=0, ele_D, ele_C=0, value32; - - ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; - - //new element A = element D x X - if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) - { - if ((IqkResult_X & 0x00000200) != 0) //consider minus - IqkResult_X = IqkResult_X | 0xFFFFFC00; - ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - - //new element C = element D x Y - if ((IqkResult_Y & 0x00000200) != 0) - IqkResult_Y = IqkResult_Y | 0xFFFFFC00; - ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; - - if (RFPath == ODM_RF_PATH_A) - switch (RFPath) - { - case ODM_RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((IqkResult_X * ele_D)>>7)&0x01; - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); - break; - default: - break; - } - } - else - { - switch (RFPath) - { - case ODM_RF_PATH_A: - ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); - ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); - break; - - default: - break; - } - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", - (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); -} - -void DoIQK_8821A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8821A(Adapter, FALSE); -} - - -VOID -ODM_TxPwrTrackSetPwr8821A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u1Byte PwrTrackingLimit = 26; //+1.0dB - u1Byte TxRate = 0xFF; - u1Byte Final_OFDM_Swing_Index = 0; - u1Byte Final_CCK_Swing_Index = 0; - u4Byte finalBbSwingIdx[1]; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8821A\n")); - - if(TxRate != 0xFF) - { - //2 CCK - if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) - PwrTrackingLimit = 32; //+4dB - //2 OFDM - else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) - PwrTrackingLimit = 30; //+3dB - else if(TxRate == MGN_54M) - PwrTrackingLimit = 28; //+2dB - //2 HT - else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM - PwrTrackingLimit = 28; //+2dB - - //2 VHT - else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK - PwrTrackingLimit = 34; //+5dB - else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM - PwrTrackingLimit = 30; //+3dB - else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM - PwrTrackingLimit = 28; //+2dB - else if(TxRate == MGN_VHT1SS_MCS7) //64QAM - PwrTrackingLimit = 26; //+1dB - else if(TxRate == MGN_VHT1SS_MCS8) //256QAM - PwrTrackingLimit = 24; //+0dB - else if(TxRate == MGN_VHT1SS_MCS9) //256QAM - PwrTrackingLimit = 22; //-1dB - - else - PwrTrackingLimit = 24; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); - - if (Method == BBSWING) - { - if (RFPath == ODM_RF_PATH_A) - { - finalBbSwingIdx[ODM_RF_PATH_A] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", - pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); - } - } - else if (Method == MIX_MODE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", - pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); - - Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - - if (RFPath == ODM_RF_PATH_A) - { - if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index - PwrTrackingLimit; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else if (Final_OFDM_Swing_Index < 0) - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; - - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); - } - else - { - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); - - if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again - { - pRFCalibrateInfo->Remnant_CCKSwingIdx= 0; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; - - PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); - } - } - } - } - else - { - return; - } -} // odm_TxPwrTrackSetPwr88E - -VOID -GetDeltaSwingTable_8821A( - IN IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte TxRate = 0xFF; - u1Byte channel = pHalData->CurrentChannel; - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - if (rate != 0xFF) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } - } else { /*force rate*/ - TxRate = (u1Byte)rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); - - - if ( 1 <= channel && channel <= 14) { - if (IS_CCK_RATE(TxRate)) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; - } else { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - } - } else if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } else { - *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; - *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; - } - - return; -} - -void ConfigureTxpowerTrack_8821A( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; - pConfig->RfPathCount = MAX_PATH_NUM_8821A; - pConfig->ThermalRegAddr = RF_T_METER_8812A; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8821A; - pConfig->DoIQK = DoIQK_8821A; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8821A; - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8821A; -} - -//1 7. IQK -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - -void _IQK_RX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} -void _IQK_BackupRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} -void _IQK_BackupAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} -void _IQK_RestoreMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} -void _IQK_RestoreRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - default: - break; - } -} -void _IQK_RestoreAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - - -void _IQK_ConfigureMAC_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -#define cal_num 3 - -void _IQK_Tx_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path - ) -{ - u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; - int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; - int TX_X0[cal_num], TX_Y0[cal_num], RX_X0[2][cal_num], RX_Y0[2][cal_num]; - BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; - int i, ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); - - while (cal < cal_num){ - switch (Path) { - case ODM_RF_PATH_A: - { - //Path-A LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - - // LOK Setting - //====== LOK ====== - // 1. DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - // 2. LoK RF Setting (at BW = 20M) - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - switch (*pDM_Odm->pBandWidth) - { - case 1: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); - } - break; - case 2: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); - } - break; - default: - break; - - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - // 3. TX RF Setting - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)) { - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - - - if (TX0IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - //====== RX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // 1. RX RF Setting - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - - if (pDM_Odm->SupportInterface == 1){ - RXIQK_Loop = 2; // for 2% fail; - } - else{ - RXIQK_Loop = 1; - } - for(i = 0; i < RXIQK_Loop; i++){ - if (pDM_Odm->SupportInterface == 1) - if(i == 0) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready)||(delay_count>20)){ - break; - } - else{ - delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - /* - DbgPrint("====== RXIQK (%d) ======", i); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK) - TX_Average++; - if (RX0IQKOK) - RX_Average++; - } - break; - default: - break; - } - cal++; - } - // FillIQK Result - switch (Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - if (TX_Average == 0) - break; - - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X0[ii]>>21); - if (dx < 3 && dx > -3){ - dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); - if (dy < 3 && dy > -3){ - TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; - TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - - if (TX_finish == 1){ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - - if (RX_Average == 0) - break; - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); - if (RXIQK_Loop == 2) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; - RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; - RX_finish1 = 1; - break; - } - } - } - if (RX_finish1 == 1){ - RX_X = RX_X_temp; - RX_Y = RX_Y_temp; - break; - } - } - if(RXIQK_Loop == 2){ - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; - RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; - RX_finish2 = 1; - break; - } - } - } - if (RX_finish2 == 1) - break; - } - if(RX_finish1 && RX_finish2){ - RX_X = (RX_X+RX_X_temp)/2; - RX_Y = (RX_Y+RX_Y_temp)/2; - } - } - if (RX_finish1 || RX_finish1){ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - } - break; - default: - break; - } -} - -#define MACBB_REG_NUM 8 -#define AFE_REG_NUM 4 -#define RF_REG_NUM 3 - -VOID -phy_IQCalibrate_By_FW_8821A( - IN PADAPTER pAdapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte IQKcmd[3] = {pHalData->CurrentChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(pHalData->CurrentBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) - Buf2 = 0x1; - else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) - Buf2 = 0x1<<1; - else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pHalData->ExternalPA_5G | pHalData->ExternalLNA_5G<<1; - - - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Start ==\n")); - pHalData->IQK_StartTimer = 0; - pHalData->IQK_StartTimer = PlatformGetCurrentTime(); - RT_TRACE(COMP_MP, DBG_LOUD, ("== StartTime: %u\n", pHalData->IQK_StartTimer)); - -#if(H2C_USE_IO_THREAD == 1) - FW8821A_FillH2cCommand(pAdapter, 0x45, 3, IQKcmd); -#else - FillH2CCommand8821A(pAdapter, 0x45, 3, IQKcmd); -#endif - -} - -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68}; - u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; - - _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); - - _IQK_ConfigureMAC_8821A(pDM_Odm); - _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); - _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); - - _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); - _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); - - //_IQK_Exit_8821A(pDM_Odm); - //_IQK_TX_CheckResult_8821A - -} - - - - -#define DP_BB_REG_NUM 7 -#define DP_RF_REG_NUM 1 -#define DP_RETRY_LIMIT 10 -#define DP_PATH_NUM 2 -#define DP_DPK_NUM 3 -#define DP_DPK_VALUE_NUM 2 - - -VOID -PHY_ResetIQKResult_8821A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); -} - - -VOID -PHY_IQCalibrate_8821A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - u4Byte counter = 0; - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif -#endif//(MP_DRIVER == 1) - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - -#if MP_DRIVER == 1 - if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) -#endif - { - //3 == FW IQK == - if(pMgntInfo->RegIQKFWOffload) - { - if ( ! pRFCalibrateInfo->bIQKInProgress) - { - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - - phy_IQCalibrate_By_FW_8821A(pAdapter); - } - else - { - for(counter = 0; counter < 10; counter++){ - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); - delay_ms(50); - if ( ! pRFCalibrateInfo->bIQKInProgress) - { - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); - break; - } - } - - if (pRFCalibrateInfo->bIQKInProgress) - { - RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - } - else - { - PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); - phy_IQCalibrate_By_FW_8821A(pAdapter); - } - - - } - } - //3 == Driver IQK == - else { - if ( ! pRFCalibrateInfo->bIQKInProgress) { - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - phy_IQCalibrate_8821A(pDM_Odm); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pRFCalibrateInfo->bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } - } - } -} - - -VOID -PHY_LCCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - PHY_LCCalibrate_8812A(pDM_Odm); -} - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8821A 6 + +/*---------------------------Define Local Constant---------------------------*/ + + +//3 ============================================================ +//3 Tx Power Tracking +//3 ============================================================ + + +void setIqkMatrix_8821A( + PDM_ODM_T pDM_Odm, + u1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y + ) +{ + s4Byte ele_A=0, ele_D, ele_C=0, value32; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; + + //new element A = element D x X + if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) + { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; + + if (RFPath == ODM_RF_PATH_A) + switch (RFPath) + { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D)>>7)&0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + default: + break; + } + } + else + { + switch (RFPath) + { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8821A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + + ODM_ResetIQKResult(pDM_Odm); + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8821A(Adapter, FALSE); +} + + +VOID +ODM_TxPwrTrackSetPwr8821A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u1Byte PwrTrackingLimit = 26; //+1.0dB + u1Byte TxRate = 0xFF; + u1Byte Final_OFDM_Swing_Index = 0; + u1Byte Final_CCK_Swing_Index = 0; + u4Byte finalBbSwingIdx[1]; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8821A\n")); + + if(TxRate != 0xFF) + { + //2 CCK + if (((TxRate >= MGN_1M) && (TxRate <= MGN_5_5M)) || (TxRate == MGN_11M)) + PwrTrackingLimit = 32; //+4dB + //2 OFDM + else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M)) + PwrTrackingLimit = 30; //+3dB + else if(TxRate == MGN_54M) + PwrTrackingLimit = 28; //+2dB + //2 HT + else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit = 28; //+2dB + + //2 VHT + else if((TxRate >= MGN_VHT1SS_MCS0)&&(TxRate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK + PwrTrackingLimit = 34; //+5dB + else if((TxRate >= MGN_VHT1SS_MCS3)&&(TxRate <= MGN_VHT1SS_MCS4)) //16QAM + PwrTrackingLimit = 30; //+3dB + else if((TxRate >= MGN_VHT1SS_MCS5)&&(TxRate <= MGN_VHT1SS_MCS6)) //64QAM + PwrTrackingLimit = 28; //+2dB + else if(TxRate == MGN_VHT1SS_MCS7) //64QAM + PwrTrackingLimit = 26; //+1dB + else if(TxRate == MGN_VHT1SS_MCS8) //256QAM + PwrTrackingLimit = 24; //+0dB + else if(TxRate == MGN_VHT1SS_MCS9) //256QAM + PwrTrackingLimit = 22; //-1dB + + else + PwrTrackingLimit = 24; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit)); + + if (Method == BBSWING) + { + if (RFPath == ODM_RF_PATH_A) + { + finalBbSwingIdx[ODM_RF_PATH_A] = (pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A] > PwrTrackingLimit) ? PwrTrackingLimit : pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A]=%d, pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n", + pRFCalibrateInfo->OFDM_index[ODM_RF_PATH_A], finalBbSwingIdx[ODM_RF_PATH_A])); + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[finalBbSwingIdx[ODM_RF_PATH_A]]); + } + } + else if (Method == MIX_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); + + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + if (RFPath == ODM_RF_PATH_A) + { + if(Final_OFDM_Swing_Index > PwrTrackingLimit) //BBSwing higher then Limit + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index - PwrTrackingLimit; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[PwrTrackingLimit]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= Final_CCK_Swing_Index; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; + + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[0]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= TRUE; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + else + { + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index)); + + if(pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again + { + pRFCalibrateInfo->Remnant_CCKSwingIdx= 0; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + + PHY_SetTxPowerLevelByPath(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n")); + } + } + } + } + else + { + return; + } +} // odm_TxPwrTrackSetPwr88E + +VOID +GetDeltaSwingTable_8821A( + IN IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + +void ConfigureTxpowerTrack_8821A( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8812A; + pConfig->RfPathCount = MAX_PATH_NUM_8821A; + pConfig->ThermalRegAddr = RF_T_METER_8812A; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8821A; + pConfig->DoIQK = DoIQK_8821A; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8821A; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8821A; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +void _IQK_RX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, RX_Y>>1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} +void _IQK_BackupRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} +void _IQK_BackupAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} +void _IQK_RestoreMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} +void _IQK_RestoreRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + default: + break; + } +} +void _IQK_RestoreAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + + +void _IQK_ConfigureMAC_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +#define cal_num 3 + +void _IQK_Tx_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path + ) +{ + u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; + int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; + int TX_X0[cal_num], TX_Y0[cal_num], RX_X0[2][cal_num], RX_Y0[2][cal_num]; + BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; + int i, ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); + + while (cal < cal_num){ + switch (Path) { + case ODM_RF_PATH_A: + { + //Path-A LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + + // LOK Setting + //====== LOK ====== + // 1. DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + // 2. LoK RF Setting (at BW = 20M) + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + switch (*pDM_Odm->pBandWidth) + { + case 1: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); + } + break; + case 2: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); + } + break; + default: + break; + + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + // 3. TX RF Setting + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)) { + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + + + if (TX0IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + //====== RX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // 1. RX RF Setting + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + + if (pDM_Odm->SupportInterface == 1){ + RXIQK_Loop = 2; // for 2% fail; + } + else{ + RXIQK_Loop = 1; + } + for(i = 0; i < RXIQK_Loop; i++){ + if (pDM_Odm->SupportInterface == 1) + if(i == 0) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready)||(delay_count>20)){ + break; + } + else{ + delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + /* + DbgPrint("====== RXIQK (%d) ======", i); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK) + TX_Average++; + if (RX0IQKOK) + RX_Average++; + } + break; + default: + break; + } + cal++; + } + // FillIQK Result + switch (Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + if (TX_Average == 0) + break; + + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X0[ii]>>21); + if (dx < 3 && dx > -3){ + dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); + if (dy < 3 && dy > -3){ + TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; + TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + + if (TX_finish == 1){ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + + if (RX_Average == 0) + break; + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); + if (RXIQK_Loop == 2) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; + RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; + RX_finish1 = 1; + break; + } + } + } + if (RX_finish1 == 1){ + RX_X = RX_X_temp; + RX_Y = RX_Y_temp; + break; + } + } + if(RXIQK_Loop == 2){ + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; + RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; + RX_finish2 = 1; + break; + } + } + } + if (RX_finish2 == 1) + break; + } + if(RX_finish1 && RX_finish2){ + RX_X = (RX_X+RX_X_temp)/2; + RX_Y = (RX_Y+RX_Y_temp)/2; + } + } + if (RX_finish1 || RX_finish1){ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + } + break; + default: + break; + } +} + +#define MACBB_REG_NUM 8 +#define AFE_REG_NUM 4 +#define RF_REG_NUM 3 + +VOID +phy_IQCalibrate_By_FW_8821A( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte IQKcmd[3] = {pHalData->CurrentChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(pHalData->CurrentBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) + Buf2 = 0x1; + else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) + Buf2 = 0x1<<1; + else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pHalData->ExternalPA_5G | pHalData->ExternalLNA_5G<<1; + + + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Start ==\n")); + pHalData->IQK_StartTimer = 0; + pHalData->IQK_StartTimer = PlatformGetCurrentTime(); + RT_TRACE(COMP_MP, DBG_LOUD, ("== StartTime: %u\n", pHalData->IQK_StartTimer)); + +#if(H2C_USE_IO_THREAD == 1) + FW8821A_FillH2cCommand(pAdapter, 0x45, 3, IQKcmd); +#else + FillH2CCommand8821A(pAdapter, 0x45, 3, IQKcmd); +#endif + +} + +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM], AFE_backup[AFE_REG_NUM], RFA_backup[RF_REG_NUM], RFB_backup[RF_REG_NUM]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68}; + u4Byte Backup_RF_REG[RF_REG_NUM] = {0x65, 0x8f, 0x0}; + + _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM); + + _IQK_ConfigureMAC_8821A(pDM_Odm); + _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); + _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM); + + _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM); + _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM); + + //_IQK_Exit_8821A(pDM_Odm); + //_IQK_TX_CheckResult_8821A + +} + + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + +VOID +PHY_ResetIQKResult_8821A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); +} + + +VOID +PHY_IQCalibrate_8821A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + u4Byte counter = 0; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if (MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + #endif +#endif//(MP_DRIVER == 1) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + +#if MP_DRIVER == 1 + if( ! (pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) ) +#endif + { + //3 == FW IQK == + if(pMgntInfo->RegIQKFWOffload) + { + if ( ! pRFCalibrateInfo->bIQKInProgress) + { + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + + phy_IQCalibrate_By_FW_8821A(pAdapter); + } + else + { + for(counter = 0; counter < 10; counter++){ + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); + delay_ms(50); + if ( ! pRFCalibrateInfo->bIQKInProgress) + { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); + break; + } + } + + if (pRFCalibrateInfo->bIQKInProgress) + { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + } + else + { + PlatformAcquireSpinLock(pAdapter, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + PlatformReleaseSpinLock(pAdapter, RT_IQK_SPINLOCK); + phy_IQCalibrate_By_FW_8821A(pAdapter); + } + + + } + } + //3 == Driver IQK == + else { + if ( ! pRFCalibrateInfo->bIQKInProgress) { + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + phy_IQCalibrate_8821A(pDM_Odm); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pRFCalibrateInfo->bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + } + } + } +} + + +VOID +PHY_LCCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + PHY_LCCalibrate_8812A(pDM_Odm); +} + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.h b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.h index 40bd2db0633..da6c4c94ee6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/halphyrf_8821a_win.h @@ -1,72 +1,72 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8821A_H__ -#define __HAL_PHY_RF_8821A_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_8821A 10 //ms -#define index_mapping_NUM_8821A 15 -#define AVG_THERMAL_NUM_8821A 4 -#define RF_T_METER_8821A 0x42 - - -void ConfigureTxpowerTrack_8821A( - PTXPWRTRACK_CFG pConfig - ); - -void DoIQK_8821A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); - -VOID -ODM_TxPwrTrackSetPwr8821A( - IN PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -//1 7. IQK - -void -PHY_IQCalibrate_8821A( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery -); - -VOID -PHY_LCCalibrate_8821A( - IN IN PVOID pDM_VOID -); - -VOID -GetDeltaSwingTable_8821A( - IN PVOID pDM_VOID, - OUT pu1Byte *TemperatureUP_A, - OUT pu1Byte *TemperatureDOWN_A, - OUT pu1Byte *TemperatureUP_B, - OUT pu1Byte *TemperatureDOWN_B -); -#endif // #ifndef __HAL_PHY_RF_8821A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8821A_H__ +#define __HAL_PHY_RF_8821A_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8821A 10 //ms +#define index_mapping_NUM_8821A 15 +#define AVG_THERMAL_NUM_8821A 4 +#define RF_T_METER_8821A 0x42 + + +void ConfigureTxpowerTrack_8821A( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8821A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr8821A( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8821A( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery +); + +VOID +PHY_LCCalibrate_8821A( + IN IN PVOID pDM_VOID +); + +VOID +GetDeltaSwingTable_8821A( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +); +#endif // #ifndef __HAL_PHY_RF_8821A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.c b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.c index d585340179d..1c16e6b6801 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.c @@ -1,894 +1,894 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -#define cal_num_8821A 3 -#define MACBB_REG_NUM_8821A 8 -#define AFE_REG_NUM_8821A 4 -#define RF_REG_NUM_8821A 3 -/*---------------------------Define Local Constant---------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8821A( - PDM_ODM_T pDM_Odm, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); -} -#endif -void _IQK_RX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} - -void _IQK_BackupRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} - -void _IQK_BackupAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} - -void _IQK_RestoreMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} - -void _IQK_RestoreRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - default: - break; - } -} - -void _IQK_RestoreAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - -void _IQK_ConfigureMAC_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -void _IQK_Tx_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path - ) -{ - u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; - int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; - int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; - BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; - BOOLEAN VDF_enable = FALSE; - int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); - if (*pDM_Odm->pBandWidth == 2){ - VDF_enable = TRUE; - } - - while (cal < cal_num_8821A){ - switch (Path) { - case ODM_RF_PATH_A: - { - //Path-A LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - - // LOK Setting - //====== LOK ====== - // 1. DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - // 2. LoK RF Setting (at BW = 20M) - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - switch (*pDM_Odm->pBandWidth) - { - case 1: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); - } - break; - case 2: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); - } - break; - default: - break; - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - // 3. TX RF Setting - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); - - if (VDF_enable == 1){ - for (k = 0;k <= 2; k++){ - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 1: - { - ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); - Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); - } - break; - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - } - if (k == 3){ - TX_X0[cal] = VDF_X[k-1] ; - TX_Y0[cal] = VDF_Y[k-1]; - } - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)) { - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - //====== RX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // 1. RX RF Setting - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) { - ODM_SetRFReg(pDM_Odm, Path, 0xdf, 0x00800, 0x1); - ODM_SetRFReg(pDM_Odm, Path, 0x56, 0x003e0, 0x1); - } - - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x978 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x978, bMaskDWord))); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - - if (pDM_Odm->SupportInterface == 1){ - RXIQK_Loop = 2; // for 2% fail; - } - else{ - RXIQK_Loop = 1; - } - for(i = 0; i < RXIQK_Loop; i++){ - if (pDM_Odm->SupportInterface == 1) - if(i == 0){ - if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161800); //Good - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc8c (i=0) = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc8c, bMaskDWord))); - } - else { - if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160c00); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc8c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc8c, bMaskDWord))); - } - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready)||(delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - /* - DbgPrint("====== RXIQK (%d) ======", i); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK) - TX_Average++; - if (RX0IQKOK) - RX_Average++; - } - break; - default: - break; - } - cal++; - } - // FillIQK Result - switch (Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - if (TX_Average == 0) - break; - - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X0[ii]>>21); - if (dx < 3 && dx > -3){ - dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); - if (dy < 3 && dy > -3){ - TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; - TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - - if (TX_finish == 1){ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - - if (RX_Average == 0) - break; - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); - if (RXIQK_Loop == 2) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; - RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; - RX_finish1 = 1; - break; - } - } - } - if (RX_finish1 == 1){ - RX_X = RX_X_temp; - RX_Y = RX_Y_temp; - break; - } - } - if(RXIQK_Loop == 2){ - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; - RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; - RX_finish2 = 1; - break; - } - } - } - if (RX_finish2 == 1) - break; - } - if(RX_finish1 && RX_finish2){ - RX_X = (RX_X+RX_X_temp)/2; - RX_Y = (RX_Y+RX_Y_temp)/2; - } - } - if (RX_finish1 || RX_finish2){ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - } - break; - default: - break; - } -} - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -phy_IQCalibrate_By_FW_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - - u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); - - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(*pDM_Odm->pBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(*pDM_Odm->pBandWidth == ODM_BW20M) - Buf2 = 0x1; - else if(*pDM_Odm->pBandWidth == ODM_BW40M) - Buf2 = 0x1<<1; - else if(*pDM_Odm->pBandWidth == ODM_BW80M) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); - pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); - - -} -#endif - -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; - u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; - - _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); - _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); - - _IQK_ConfigureMAC_8821A(pDM_Odm); - _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); - - _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); - _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); -} - -VOID -PHY_ResetIQKResult_8821A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0); -} - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u4Byte counter = 0; - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - #endif - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - #endif - - } - - - //3 == FW IQK == - if(pDM_Odm->IQKFWOffload) - { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - phy_IQCalibrate_By_FW_8821A(pDM_Odm); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for(counter = 0; counter < 10; counter++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); - ODM_delay_ms(50); - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); - break; - } - } - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtl8812_iqk_wait(pAdapter, 500); - #endif - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - //3 == Driver IQK == - else { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - phy_IQCalibrate_8821A(pDM_Odm); - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +#define cal_num_8821A 3 +#define MACBB_REG_NUM_8821A 8 +#define AFE_REG_NUM_8821A 4 +#define RF_REG_NUM_8821A 3 +/*---------------------------Define Local Constant---------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void DoIQK_8821A( + PDM_ODM_T pDM_Odm, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); +} +#endif +void _IQK_RX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} + +void _IQK_BackupRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} + +void _IQK_BackupAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} + +void _IQK_RestoreMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} + +void _IQK_RestoreRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + default: + break; + } +} + +void _IQK_RestoreAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + +void _IQK_ConfigureMAC_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +void _IQK_Tx_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path + ) +{ + u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; + int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; + int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; + BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; + BOOLEAN VDF_enable = FALSE; + int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); + if (*pDM_Odm->pBandWidth == 2){ + VDF_enable = TRUE; + } + + while (cal < cal_num_8821A){ + switch (Path) { + case ODM_RF_PATH_A: + { + //Path-A LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + + // LOK Setting + //====== LOK ====== + // 1. DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + // 2. LoK RF Setting (at BW = 20M) + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + switch (*pDM_Odm->pBandWidth) + { + case 1: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); + } + break; + case 2: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); + } + break; + default: + break; + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + // 3. TX RF Setting + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); + + if (VDF_enable == 1){ + for (k = 0;k <= 2; k++){ + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 1: + { + ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); + Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); + } + break; + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + } + if (k == 3){ + TX_X0[cal] = VDF_X[k-1] ; + TX_Y0[cal] = VDF_Y[k-1]; + } + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)) { + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + //====== RX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // 1. RX RF Setting + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) { + ODM_SetRFReg(pDM_Odm, Path, 0xdf, 0x00800, 0x1); + ODM_SetRFReg(pDM_Odm, Path, 0x56, 0x003e0, 0x1); + } + + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x978 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x978, bMaskDWord))); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + + if (pDM_Odm->SupportInterface == 1){ + RXIQK_Loop = 2; // for 2% fail; + } + else{ + RXIQK_Loop = 1; + } + for(i = 0; i < RXIQK_Loop; i++){ + if (pDM_Odm->SupportInterface == 1) + if(i == 0){ + if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161800); //Good + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc8c (i=0) = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc8c, bMaskDWord))); + } + else { + if ((get_bonding_type_8881A() == BOND_8881AM) && (pDM_Odm->ExtPA5G) && (pDM_Odm->ExtLNA5G)) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160c00); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc8c = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc8c, bMaskDWord))); + } + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready)||(delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, 0x00800, 0x0); + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + /* + DbgPrint("====== RXIQK (%d) ======", i); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK) + TX_Average++; + if (RX0IQKOK) + RX_Average++; + } + break; + default: + break; + } + cal++; + } + // FillIQK Result + switch (Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + if (TX_Average == 0) + break; + + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X0[ii]>>21); + if (dx < 3 && dx > -3){ + dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); + if (dy < 3 && dy > -3){ + TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; + TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + + if (TX_finish == 1){ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + + if (RX_Average == 0) + break; + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); + if (RXIQK_Loop == 2) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; + RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; + RX_finish1 = 1; + break; + } + } + } + if (RX_finish1 == 1){ + RX_X = RX_X_temp; + RX_Y = RX_Y_temp; + break; + } + } + if(RXIQK_Loop == 2){ + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; + RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; + RX_finish2 = 1; + break; + } + } + } + if (RX_finish2 == 1) + break; + } + if(RX_finish1 && RX_finish2){ + RX_X = (RX_X+RX_X_temp)/2; + RX_Y = (RX_Y+RX_Y_temp)/2; + } + } + if (RX_finish1 || RX_finish2){ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + } + break; + default: + break; + } +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +phy_IQCalibrate_By_FW_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + + u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); + + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(*pDM_Odm->pBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(*pDM_Odm->pBandWidth == ODM_BW20M) + Buf2 = 0x1; + else if(*pDM_Odm->pBandWidth == ODM_BW40M) + Buf2 = 0x1<<1; + else if(*pDM_Odm->pBandWidth == ODM_BW80M) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); + pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); + + +} +#endif + +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; + u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; + + _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); + _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); + + _IQK_ConfigureMAC_8821A(pDM_Odm); + _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); + + _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); + _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); +} + +VOID +PHY_ResetIQKResult_8821A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0); +} + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u4Byte counter = 0; + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + #endif + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + #endif + + } + + + //3 == FW IQK == + if(pDM_Odm->IQKFWOffload) + { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + phy_IQCalibrate_By_FW_8821A(pDM_Odm); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + for(counter = 0; counter < 10; counter++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); + ODM_delay_ms(50); + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); + break; + } + } + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtl8812_iqk_wait(pAdapter, 500); + #endif + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + //3 == Driver IQK == + else { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + phy_IQCalibrate_8821A(pDM_Odm); + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.h b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.h index 8c74fece7ce..074d08587cb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ap.h @@ -1,48 +1,48 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDM_IQK_8821A_H__ -#define __PHYDM_IQK_8821A_H__ - -/*--------------------------Define Parameters-------------------------------*/ - - -/*---------------------------End Define Parameters-------------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void -DoIQK_8821A( - PDM_ODM_T pDM_Odm, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -void -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery -); -#else -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ); -#endif -#endif // #ifndef __PHYDM_IQK_8821A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_IQK_8821A_H__ +#define __PHYDM_IQK_8821A_H__ + +/*--------------------------Define Parameters-------------------------------*/ + + +/*---------------------------End Define Parameters-------------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void +DoIQK_8821A( + PDM_ODM_T pDM_Odm, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +void +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery +); +#else +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ); +#endif +#endif // #ifndef __PHYDM_IQK_8821A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.c b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.c index aefe72aa552..c334f3248fd 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.c @@ -1,887 +1,887 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -#define cal_num_8821A 3 -#define MACBB_REG_NUM_8821A 8 -#define AFE_REG_NUM_8821A 4 -#define RF_REG_NUM_8821A 3 -/*---------------------------Define Local Constant---------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8821A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); -} -#endif -void _IQK_RX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} - -void _IQK_BackupRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} - -void _IQK_BackupAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} - -void _IQK_RestoreMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} - -void _IQK_RestoreRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - default: - break; - } -} - -void _IQK_RestoreAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - -void _IQK_ConfigureMAC_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -void _IQK_Tx_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path - ) -{ - u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; - int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; - int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; - BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; - BOOLEAN VDF_enable = FALSE; - int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); - if (*pDM_Odm->pBandWidth == 2){ - VDF_enable = TRUE; - } - - while (cal < cal_num_8821A){ - switch (Path) { - case ODM_RF_PATH_A: - { - //Path-A LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - - // LOK Setting - //====== LOK ====== - // 1. DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - // 2. LoK RF Setting (at BW = 20M) - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - - if (pDM_Odm->RFCalibrateInfo.bIQKPAoff == 1) - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3ec3); - else - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - switch (*pDM_Odm->pBandWidth) - { - case 1: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); - } - break; - case 2: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); - } - break; - default: - break; - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - // 3. TX RF Setting - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - - if (pDM_Odm->RFCalibrateInfo.bIQKPAoff == 1) - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3ec3); - else - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); - - if (VDF_enable == 1){ - for (k = 0;k <= 2; k++){ - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 1: - { - ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); - Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); - } - break; - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - } - if (k == 3){ - TX_X0[cal] = VDF_X[k-1] ; - TX_Y0[cal] = VDF_Y[k-1]; - } - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)) { - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - //====== RX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // 1. RX RF Setting - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - - if (pDM_Odm->SupportInterface == 1){ - RXIQK_Loop = 2; // for 2% fail; - } - else{ - RXIQK_Loop = 1; - } - for(i = 0; i < RXIQK_Loop; i++){ - if (pDM_Odm->SupportInterface == 1) - if(i == 0) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready)||(delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - /* - DbgPrint("====== RXIQK (%d) ======", i); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK) - TX_Average++; - if (RX0IQKOK) - RX_Average++; - } - break; - default: - break; - } - cal++; - } - // FillIQK Result - switch (Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - if (TX_Average == 0) - break; - - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X0[ii]>>21); - if (dx < 3 && dx > -3){ - dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); - if (dy < 3 && dy > -3){ - TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; - TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - - if (TX_finish == 1){ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - - if (RX_Average == 0) - break; - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); - if (RXIQK_Loop == 2) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; - RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; - RX_finish1 = 1; - break; - } - } - } - if (RX_finish1 == 1){ - RX_X = RX_X_temp; - RX_Y = RX_Y_temp; - break; - } - } - if(RXIQK_Loop == 2){ - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; - RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; - RX_finish2 = 1; - break; - } - } - } - if (RX_finish2 == 1) - break; - } - if(RX_finish1 && RX_finish2){ - RX_X = (RX_X+RX_X_temp)/2; - RX_Y = (RX_Y+RX_Y_temp)/2; - } - } - if (RX_finish1 || RX_finish2){ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - } - break; - default: - break; - } -} - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -phy_IQCalibrate_By_FW_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - - u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); - - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(*pDM_Odm->pBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(*pDM_Odm->pBandWidth == ODM_BW20M) - Buf2 = 0x1; - else if(*pDM_Odm->pBandWidth == ODM_BW40M) - Buf2 = 0x1<<1; - else if(*pDM_Odm->pBandWidth == ODM_BW80M) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); - pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); - - -} -#endif - -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; - u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; - - _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); - _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); - - _IQK_ConfigureMAC_8821A(pDM_Odm); - _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); - - _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); - _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); -} - -VOID -PHY_ResetIQKResult_8821A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); -} - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u4Byte counter = 0; - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - #endif - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - pDM_Odm->IQKFWOffload = 0; /*MP mode NO FW IQK*/ - #endif - - } - /*pDM_Odm->IQKFWOffload = 0; //request by SD4 Yi Wei Sun*/ - - //3 == FW IQK == - if(pDM_Odm->IQKFWOffload) - { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - phy_IQCalibrate_By_FW_8821A(pDM_Odm); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for(counter = 0; counter < 10; counter++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); - ODM_delay_ms(50); - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); - break; - } - } - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtl8812_iqk_wait(pAdapter, 500); - #endif - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - //3 == Driver IQK == - else { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - phy_IQCalibrate_8821A(pDM_Odm); - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +#define cal_num_8821A 3 +#define MACBB_REG_NUM_8821A 8 +#define AFE_REG_NUM_8821A 4 +#define RF_REG_NUM_8821A 3 +/*---------------------------Define Local Constant---------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void DoIQK_8821A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); +} +#endif +void _IQK_RX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} + +void _IQK_BackupRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} + +void _IQK_BackupAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} + +void _IQK_RestoreMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} + +void _IQK_RestoreRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + default: + break; + } +} + +void _IQK_RestoreAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + +void _IQK_ConfigureMAC_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +void _IQK_Tx_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path + ) +{ + u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; + int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; + int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; + BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; + BOOLEAN VDF_enable = FALSE; + int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); + if (*pDM_Odm->pBandWidth == 2){ + VDF_enable = TRUE; + } + + while (cal < cal_num_8821A){ + switch (Path) { + case ODM_RF_PATH_A: + { + //Path-A LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + + // LOK Setting + //====== LOK ====== + // 1. DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + // 2. LoK RF Setting (at BW = 20M) + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + + if (pDM_Odm->RFCalibrateInfo.bIQKPAoff == 1) + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3ec3); + else + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + switch (*pDM_Odm->pBandWidth) + { + case 1: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); + } + break; + case 2: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); + } + break; + default: + break; + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + // 3. TX RF Setting + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + + if (pDM_Odm->RFCalibrateInfo.bIQKPAoff == 1) + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3ec3); + else + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); + + if (VDF_enable == 1){ + for (k = 0;k <= 2; k++){ + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 1: + { + ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); + Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); + } + break; + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + } + if (k == 3){ + TX_X0[cal] = VDF_X[k-1] ; + TX_Y0[cal] = VDF_Y[k-1]; + } + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)) { + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + //====== RX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // 1. RX RF Setting + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + + if (pDM_Odm->SupportInterface == 1){ + RXIQK_Loop = 2; // for 2% fail; + } + else{ + RXIQK_Loop = 1; + } + for(i = 0; i < RXIQK_Loop; i++){ + if (pDM_Odm->SupportInterface == 1) + if(i == 0) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready)||(delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + /* + DbgPrint("====== RXIQK (%d) ======", i); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK) + TX_Average++; + if (RX0IQKOK) + RX_Average++; + } + break; + default: + break; + } + cal++; + } + // FillIQK Result + switch (Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + if (TX_Average == 0) + break; + + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X0[ii]>>21); + if (dx < 3 && dx > -3){ + dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); + if (dy < 3 && dy > -3){ + TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; + TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + + if (TX_finish == 1){ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + + if (RX_Average == 0) + break; + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); + if (RXIQK_Loop == 2) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; + RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; + RX_finish1 = 1; + break; + } + } + } + if (RX_finish1 == 1){ + RX_X = RX_X_temp; + RX_Y = RX_Y_temp; + break; + } + } + if(RXIQK_Loop == 2){ + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; + RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; + RX_finish2 = 1; + break; + } + } + } + if (RX_finish2 == 1) + break; + } + if(RX_finish1 && RX_finish2){ + RX_X = (RX_X+RX_X_temp)/2; + RX_Y = (RX_Y+RX_Y_temp)/2; + } + } + if (RX_finish1 || RX_finish2){ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + } + break; + default: + break; + } +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +phy_IQCalibrate_By_FW_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + + u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); + + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(*pDM_Odm->pBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(*pDM_Odm->pBandWidth == ODM_BW20M) + Buf2 = 0x1; + else if(*pDM_Odm->pBandWidth == ODM_BW40M) + Buf2 = 0x1<<1; + else if(*pDM_Odm->pBandWidth == ODM_BW80M) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); + pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); + + +} +#endif + +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; + u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; + + _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); + _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); + + _IQK_ConfigureMAC_8821A(pDM_Odm); + _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); + + _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); + _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); +} + +VOID +PHY_ResetIQKResult_8821A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); +} + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u4Byte counter = 0; + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + #endif + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + pDM_Odm->IQKFWOffload = 0; /*MP mode NO FW IQK*/ + #endif + + } + /*pDM_Odm->IQKFWOffload = 0; //request by SD4 Yi Wei Sun*/ + + //3 == FW IQK == + if(pDM_Odm->IQKFWOffload) + { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + phy_IQCalibrate_By_FW_8821A(pDM_Odm); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + for(counter = 0; counter < 10; counter++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); + ODM_delay_ms(50); + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); + break; + } + } + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtl8812_iqk_wait(pAdapter, 500); + #endif + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + //3 == Driver IQK == + else { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + phy_IQCalibrate_8821A(pDM_Odm); + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.h b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.h index f44f445c877..da0d811dd10 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_ce.h @@ -1,48 +1,48 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDM_IQK_8821A_H__ -#define __PHYDM_IQK_8821A_H__ - -/*--------------------------Define Parameters-------------------------------*/ - - -/*---------------------------End Define Parameters-------------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void -DoIQK_8821A( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -void -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery -); -#else -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ); -#endif -#endif // #ifndef __PHYDM_IQK_8821A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_IQK_8821A_H__ +#define __PHYDM_IQK_8821A_H__ + +/*--------------------------Define Parameters-------------------------------*/ + + +/*---------------------------End Define Parameters-------------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void +DoIQK_8821A( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +void +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery +); +#else +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ); +#endif +#endif // #ifndef __PHYDM_IQK_8821A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.c b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.c index aeb4979671a..39898dcc0c0 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.c @@ -1,875 +1,875 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - - - -/*---------------------------Define Local Constant---------------------------*/ -#define cal_num_8821A 3 -#define MACBB_REG_NUM_8821A 8 -#define AFE_REG_NUM_8821A 4 -#define RF_REG_NUM_8821A 3 -/*---------------------------Define Local Constant---------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8821A( - PDM_ODM_T pDM_Odm, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); -} -#endif -void _IQK_RX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int RX_X, - IN unsigned int RX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); - } - break; - default: - break; - }; -} - -void _IQK_TX_FillIQC_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN unsigned int TX_X, - IN unsigned int TX_Y - ) -{ - switch (Path) { - case ODM_RF_PATH_A: - { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); - } - break; - default: - break; - }; -} - -void _IQK_BackupMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //save MACBB default value - for (i = 0; i < MACBB_NUM; i++){ - MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); -} - -void _IQK_BackupRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte RFA_backup, - IN pu4Byte RFB_backup, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_NUM - ) -{ - - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save RF Parameters - for (i = 0; i < RF_NUM; i++){ - RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); -} - -void _IQK_BackupAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Save AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); -} - -void _IQK_RestoreMacBB_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MACBB_backup, - IN pu4Byte Backup_MACBB_REG, - IN u4Byte MACBB_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload MacBB Parameters - for (i = 0; i < MACBB_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); -} - -void _IQK_RestoreRF_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN pu4Byte Backup_RF_REG, - IN pu4Byte RF_backup, - IN u4Byte RF_REG_NUM - ) -{ - u4Byte i; - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - for (i = 0; i < RF_REG_NUM; i++) - ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); - - switch(Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); - } - break; - default: - break; - } -} - -void _IQK_RestoreAFE_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte AFE_backup, - IN pu4Byte Backup_AFE_REG, - IN u4Byte AFE_NUM - ) -{ - u4Byte i; - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - //Reload AFE Parameters - for (i = 0; i < AFE_NUM; i++){ - ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); - ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); - ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); - ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); -} - -void _IQK_ConfigureMAC_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - // ========MAC register setting======== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); - ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off - ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off - ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off -} - -void _IQK_Tx_8821A( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path - ) -{ - u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; - int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; - int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; - BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; - BOOLEAN VDF_enable = FALSE; - int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); - if (*pDM_Odm->pBandWidth == 2){ - VDF_enable = TRUE; - } - - while (cal < cal_num_8821A){ - switch (Path) { - case ODM_RF_PATH_A: - { - //Path-A LOK - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // ========Path-A AFE all on======== - // Port 0 DAC/ADC on - ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); - - ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off - - // LOK Setting - //====== LOK ====== - // 1. DAC/ADC sampling rate (160 MHz) - ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); - - // 2. LoK RF Setting (at BW = 20M) - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); - - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK - switch (*pDM_Odm->pBandWidth) - { - case 1: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); - } - break; - case 2: - { - ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); - } - break; - default: - break; - } - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - // 3. TX RF Setting - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); - ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - - if (pDM_Odm->ExtPA5G) - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); - else - ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); - - if (*pDM_Odm->pBandType) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); - - if (VDF_enable == 1){ - for (k = 0;k <= 2; k++){ - switch (k){ - case 0: - { - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 1: - { - ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); - } - break; - case 2: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); - Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); - Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); - Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); - } - break; - } - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10){ - break; - } - } - } - } - if (k == 3){ - TX_X0[cal] = VDF_X[k-1] ; - TX_Y0[cal] = VDF_Y[k-1]; - } - } - else{ - ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready) || (delay_count>20)) { - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============TXIQK Check============== - TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); - - if (~TX_fail){ - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); - TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); - TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - TX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) { - break; - } - } - } - else{ - TX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK == FALSE) - break; // TXK fail, Don't do RXK - - //====== RX IQK ====== - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - // 1. RX RF Setting - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); - ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); - ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); - ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); - ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); - ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); - - ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); - ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); - ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); - ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 - ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] - ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); - - if (pDM_Odm->SupportInterface == 1){ - RXIQK_Loop = 2; // for 2% fail; - } - else{ - RXIQK_Loop = 1; - } - for(i = 0; i < RXIQK_Loop; i++){ - if (pDM_Odm->SupportInterface == 1) - if(i == 0) - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - else - ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module - - cal_retry = 0; - while(1){ - // one shot - ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); - ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); - - ODM_delay_ms(10); //Delay 10ms - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); - delay_count = 0; - while (1){ - IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); - if ((~IQK_ready)||(delay_count>20)){ - break; - } - else{ - ODM_delay_ms(1); - delay_count++; - } - } - - if (delay_count < 20){ // If 20ms No Result, then cal_retry++ - // ============RXIQK Check============== - RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); - if (RX_fail == 0){ - /* - DbgPrint("====== RXIQK (%d) ======", i); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); - Image_Power = (reg2<<32)+reg1; - DbgPrint("Before PW = %d\n", Image_Power); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); - reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); - Image_Power = (reg2<<32)+reg1; - DbgPrint("After PW = %d\n", Image_Power); - */ - - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); - RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); - RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; - RX0IQKOK = TRUE; - break; - } - else{ - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); - ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - - } - } - else{ - RX0IQKOK = FALSE; - cal_retry++; - if (cal_retry == 10) - break; - } - } - } - - if (TX0IQKOK) - TX_Average++; - if (RX0IQKOK) - RX_Average++; - } - break; - default: - break; - } - cal++; - } - // FillIQK Result - switch (Path){ - case ODM_RF_PATH_A: - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); - if (TX_Average == 0) - break; - - for (i = 0; i < TX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); - } - for (i = 0; i < TX_Average; i++){ - for (ii = i+1; ii >21) - (TX_X0[ii]>>21); - if (dx < 3 && dx > -3){ - dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); - if (dy < 3 && dy > -3){ - TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; - TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; - TX_finish = 1; - break; - } - } - } - if (TX_finish == 1) - break; - } - - if (TX_finish == 1){ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); - } - else{ - _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - - if (RX_Average == 0) - break; - - for (i = 0; i < RX_Average; i++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); - if (RXIQK_Loop == 2) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); - } - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; - RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; - RX_finish1 = 1; - break; - } - } - } - if (RX_finish1 == 1){ - RX_X = RX_X_temp; - RX_Y = RX_Y_temp; - break; - } - } - if(RXIQK_Loop == 2){ - for (i = 0; i < RX_Average; i++){ - for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); - if (dx < 4 && dx > -4){ - dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); - if (dy < 4 && dy > -4){ - RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; - RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; - RX_finish2 = 1; - break; - } - } - } - if (RX_finish2 == 1) - break; - } - if(RX_finish1 && RX_finish2){ - RX_X = (RX_X+RX_X_temp)/2; - RX_Y = (RX_Y+RX_Y_temp)/2; - } - } - if (RX_finish1 || RX_finish2){ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); - } - else{ - _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); - } - } - break; - default: - break; - } -} - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -phy_IQCalibrate_By_FW_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - - u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; - u1Byte Buf1 = 0x0; - u1Byte Buf2 = 0x0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); - - -//Byte 2, Bit 4 ~ Bit 5 : BandType - if(*pDM_Odm->pBandType) - Buf1 = 0x2<<4; - else - Buf1 = 0x1<<4; - -//Byte 2, Bit 0 ~ Bit 3 : Bandwidth - if(*pDM_Odm->pBandWidth == ODM_BW20M) - Buf2 = 0x1; - else if(*pDM_Odm->pBandWidth == ODM_BW40M) - Buf2 = 0x1<<1; - else if(*pDM_Odm->pBandWidth == ODM_BW80M) - Buf2 = 0x1<<2; - else - Buf2 = 0x1<<3; - - IQKcmd[1] = Buf1 | Buf2; - IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); - pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); - - -} -#endif - -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; - u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; - u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; - u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; - - _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); - _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); - - _IQK_ConfigureMAC_8821A(pDM_Odm); - _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); - - _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); - _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); - _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); -} - -VOID -PHY_ResetIQKResult_8821A( - IN PDM_ODM_T pDM_Odm -) -{ - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 - ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); - ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); - ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C - ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); -} - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u4Byte counter = 0; - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; -#endif - - if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - #endif - #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) - return; - #endif - - } - pDM_Odm->IQKFWOffload = 0; - - //3 == FW IQK == - if(pDM_Odm->IQKFWOffload) - { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - phy_IQCalibrate_By_FW_8821A(pDM_Odm); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for(counter = 0; counter < 10; counter++){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); - ODM_delay_ms(50); - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); - break; - } - } - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtl8812_iqk_wait(pAdapter, 500); - #endif - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); - ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - //3 == Driver IQK == - else { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); - phy_IQCalibrate_8821A(pDM_Odm); - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - } - } - -} -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + + +/*---------------------------Define Local Constant---------------------------*/ +#define cal_num_8821A 3 +#define MACBB_REG_NUM_8821A 8 +#define AFE_REG_NUM_8821A 4 +#define RF_REG_NUM_8821A 3 +/*---------------------------Define Local Constant---------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void DoIQK_8821A( + PDM_ODM_T pDM_Odm, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ) +{ + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); +} +#endif +void _IQK_RX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int RX_X, + IN unsigned int RX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, RX_X>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", ODM_Read4Byte(pDM_Odm, 0xc10))); + } + break; + default: + break; + }; +} + +void _IQK_TX_FillIQC_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN unsigned int TX_X, + IN unsigned int TX_Y + ) +{ + switch (Path) { + case ODM_RF_PATH_A: + { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, TX_Y); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, TX_X); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", ODM_GetBBReg(pDM_Odm, 0xcd4, 0x000007ff), ODM_GetBBReg(pDM_Odm, 0xccc, 0x000007ff))); + } + break; + default: + break; + }; +} + +void _IQK_BackupMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //save MACBB default value + for (i = 0; i < MACBB_NUM; i++){ + MACBB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MACBB_REG[i]); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n")); +} + +void _IQK_BackupRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte RFA_backup, + IN pu4Byte RFB_backup, + IN pu4Byte Backup_RF_REG, + IN u4Byte RF_NUM + ) +{ + + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save RF Parameters + for (i = 0; i < RF_NUM; i++){ + RFA_backup[i] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n")); +} + +void _IQK_BackupAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Save AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + AFE_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_AFE_REG[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n")); +} + +void _IQK_RestoreMacBB_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte MACBB_backup, + IN pu4Byte Backup_MACBB_REG, + IN u4Byte MACBB_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload MacBB Parameters + for (i = 0; i < MACBB_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_MACBB_REG[i], MACBB_backup[i]); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n")); +} + +void _IQK_RestoreRF_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN pu4Byte Backup_RF_REG, + IN pu4Byte RF_backup, + IN u4Byte RF_REG_NUM + ) +{ + u4Byte i; + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + for (i = 0; i < RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]); + + switch(Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n")); + } + break; + default: + break; + } +} + +void _IQK_RestoreAFE_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu4Byte AFE_backup, + IN pu4Byte Backup_AFE_REG, + IN u4Byte AFE_NUM + ) +{ + u4Byte i; + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + //Reload AFE Parameters + for (i = 0; i < AFE_NUM; i++){ + ODM_Write4Byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]); + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc84, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc88, 0x0); + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x3c000000); + ODM_Write4Byte(pDM_Odm, 0xc90, 0x00000080); + ODM_Write4Byte(pDM_Odm, 0xc94, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0xcc4, 0x20040000); + ODM_Write4Byte(pDM_Odm, 0xcc8, 0x20000000); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n")); +} + +void _IQK_ConfigureMAC_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + // ========MAC register setting======== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_Write1Byte(pDM_Odm, 0x522, 0x3f); + ODM_SetBBReg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0); + ODM_Write1Byte(pDM_Odm, 0x808, 0x00); // RX ante off + ODM_SetBBReg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off + ODM_Write1Byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off +} + +void _IQK_Tx_8821A( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path + ) +{ + u4Byte TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0; + int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0; + int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A]; + BOOLEAN TX0IQKOK = FALSE, RX0IQKOK = FALSE; + BOOLEAN VDF_enable = FALSE; + int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ExtPA5G = %d\n", *pDM_Odm->pBandWidth, pDM_Odm->SupportInterface, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); + if (*pDM_Odm->pBandWidth == 2){ + VDF_enable = TRUE; + } + + while (cal < cal_num_8821A){ + switch (Path) { + case ODM_RF_PATH_A: + { + //Path-A LOK + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // ========Path-A AFE all on======== + // Port 0 DAC/ADC on + ODM_Write4Byte(pDM_Odm, 0xc60, 0x77777777); + ODM_Write4Byte(pDM_Odm, 0xc64, 0x77777777); + + ODM_Write4Byte(pDM_Odm, 0xc68, 0x19791979); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off + + // LOK Setting + //====== LOK ====== + // 1. DAC/ADC sampling rate (160 MHz) + ODM_SetBBReg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7); + + // 2. LoK RF Setting (at BW = 20M) + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002); + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f4); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28163e96); + + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0x58, 0x7fe00, ODM_GetRFReg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK + switch (*pDM_Odm->pBandWidth) + { + case 1: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x1); + } + break; + case 2: + { + ODM_SetRFReg(pDM_Odm, Path, 0x18, 0x00c00, 0x0); + } + break; + default: + break; + } + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + // 3. TX RF Setting + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_SetBBReg(pDM_Odm, 0xc94, BIT(0), 0x1); + ODM_Write4Byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y) + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + + if (pDM_Odm->ExtPA5G) + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403f7); + else + ODM_Write4Byte(pDM_Odm, 0xc88, 0x821403e3); + + if (*pDM_Odm->pBandType) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x40163e96); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x00163e96); + + if (VDF_enable == 1){ + for (k = 0;k <= 2; k++){ + switch (k){ + case 0: + { + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 1: + { + ODM_SetBBReg(pDM_Odm, 0xc80, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xc84, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x0); + } + break; + case 2: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff)); + Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20); + Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708); + Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0)); + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_SetBBReg(pDM_Odm, 0xce8, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff); + } + break; + } + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + VDF_X[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + VDF_Y[k] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10){ + break; + } + } + } + } + if (k == 3){ + TX_X0[cal] = VDF_X[k-1] ; + TX_Y0[cal] = VDF_Y[k-1]; + } + } + else{ + ODM_Write4Byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready) || (delay_count>20)) { + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============TXIQK Check============== + TX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(12)); + + if (~TX_fail){ + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x02000000); + TX_X0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x04000000); + TX_Y0[cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + TX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) { + break; + } + } + } + else{ + TX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK == FALSE) + break; // TXK fail, Don't do RXK + + //====== RX IQK ====== + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + // 1. RX RF Setting + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000); + ODM_SetRFReg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f); + ODM_SetRFReg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb); + ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001); + ODM_SetRFReg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8); + ODM_SetRFReg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000); + + ODM_SetBBReg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff); + ODM_SetBBReg(pDM_Odm, 0x978, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0x97c, BIT(31), 0x0); + ODM_Write4Byte(pDM_Odm, 0x90c, 0x00008000); + ODM_Write4Byte(pDM_Odm, 0x984, 0x0046a911); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_Write4Byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 + ODM_Write4Byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29] + ODM_Write4Byte(pDM_Odm, 0xc88, 0x02140119); + + if (pDM_Odm->SupportInterface == 1){ + RXIQK_Loop = 2; // for 2% fail; + } + else{ + RXIQK_Loop = 1; + } + for(i = 0; i < RXIQK_Loop; i++){ + if (pDM_Odm->SupportInterface == 1) + if(i == 0) + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28161100); //Good + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + else + ODM_Write4Byte(pDM_Odm, 0xc8c, 0x28160d00); + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module + + cal_retry = 0; + while(1){ + // one shot + ODM_Write4Byte(pDM_Odm, 0x980, 0xfa000000); + ODM_Write4Byte(pDM_Odm, 0x980, 0xf8000000); + + ODM_delay_ms(10); //Delay 10ms + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x00000000); + delay_count = 0; + while (1){ + IQK_ready = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(10)); + if ((~IQK_ready)||(delay_count>20)){ + break; + } + else{ + ODM_delay_ms(1); + delay_count++; + } + } + + if (delay_count < 20){ // If 20ms No Result, then cal_retry++ + // ============RXIQK Check============== + RX_fail = ODM_GetBBReg(pDM_Odm, 0xd00, BIT(11)); + if (RX_fail == 0){ + /* + DbgPrint("====== RXIQK (%d) ======", i); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2); + Image_Power = (reg2<<32)+reg1; + DbgPrint("Before PW = %d\n", Image_Power); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000); + reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff); + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f); + Image_Power = (reg2<<32)+reg1; + DbgPrint("After PW = %d\n", Image_Power); + */ + + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000); + RX_X0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000); + RX_Y0[i][cal] = ODM_GetBBReg(pDM_Odm, 0xd00, 0x07ff0000)<<21; + RX0IQKOK = TRUE; + break; + } + else{ + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1); + ODM_SetBBReg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1); + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + + } + } + else{ + RX0IQKOK = FALSE; + cal_retry++; + if (cal_retry == 10) + break; + } + } + } + + if (TX0IQKOK) + TX_Average++; + if (RX0IQKOK) + RX_Average++; + } + break; + default: + break; + } + cal++; + } + // FillIQK Result + switch (Path){ + case ODM_RF_PATH_A: + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n")); + if (TX_Average == 0) + break; + + for (i = 0; i < TX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff)); + } + for (i = 0; i < TX_Average; i++){ + for (ii = i+1; ii >21) - (TX_X0[ii]>>21); + if (dx < 3 && dx > -3){ + dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21); + if (dy < 3 && dy > -3){ + TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2; + TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2; + TX_finish = 1; + break; + } + } + } + if (TX_finish == 1) + break; + } + + if (TX_finish == 1){ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y); + } + else{ + _IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + + if (RX_Average == 0) + break; + + for (i = 0; i < RX_Average; i++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff)); + if (RXIQK_Loop == 2) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff)); + } + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[0][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2; + RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2; + RX_finish1 = 1; + break; + } + } + } + if (RX_finish1 == 1){ + RX_X = RX_X_temp; + RX_Y = RX_Y_temp; + break; + } + } + if(RXIQK_Loop == 2){ + for (i = 0; i < RX_Average; i++){ + for (ii = i+1; ii >21) - (RX_X0[1][ii]>>21); + if (dx < 4 && dx > -4){ + dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21); + if (dy < 4 && dy > -4){ + RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2; + RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2; + RX_finish2 = 1; + break; + } + } + } + if (RX_finish2 == 1) + break; + } + if(RX_finish1 && RX_finish2){ + RX_X = (RX_X+RX_X_temp)/2; + RX_Y = (RX_Y+RX_Y_temp)/2; + } + } + if (RX_finish1 || RX_finish2){ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y); + } + else{ + _IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0); + } + } + break; + default: + break; + } +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +phy_IQCalibrate_By_FW_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + + u1Byte IQKcmd[3] = {*pDM_Odm->pChannel, 0x0, 0x0}; + u1Byte Buf1 = 0x0; + u1Byte Buf2 = 0x0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->pChannel)); + + +//Byte 2, Bit 4 ~ Bit 5 : BandType + if(*pDM_Odm->pBandType) + Buf1 = 0x2<<4; + else + Buf1 = 0x1<<4; + +//Byte 2, Bit 0 ~ Bit 3 : Bandwidth + if(*pDM_Odm->pBandWidth == ODM_BW20M) + Buf2 = 0x1; + else if(*pDM_Odm->pBandWidth == ODM_BW40M) + Buf2 = 0x1<<1; + else if(*pDM_Odm->pBandWidth == ODM_BW80M) + Buf2 = 0x1<<2; + else + Buf2 = 0x1<<3; + + IQKcmd[1] = Buf1 | Buf2; + IQKcmd[2] = pDM_Odm->ExtPA5G | pDM_Odm->ExtLNA5G<<1; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n")); + pDM_Odm->RFCalibrateInfo.IQK_StartTime = 0; + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->RFCalibrateInfo.IQK_StartTime)); + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd); + + +} +#endif + +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A]; + u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c}; + u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68}; + u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0}; + + _IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); + _IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A); + + _IQK_ConfigureMAC_8821A(pDM_Odm); + _IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A); + + _IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A); + _IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A); + _IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A); +} + +VOID +PHY_ResetIQKResult_8821A( + IN PDM_ODM_T pDM_Odm +) +{ + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1 + ODM_SetBBReg(pDM_Odm, 0xccc, 0x000007ff, 0x0); + ODM_SetBBReg(pDM_Odm, 0xcd4, 0x000007ff, 0x200); + ODM_Write4Byte(pDM_Odm, 0xce8, 0x0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C + ODM_SetBBReg(pDM_Odm, 0xc10, 0x000003ff, 0x100); +} + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u4Byte counter = 0; + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + if (pDM_Odm->mp_mode){ //(MP_DRIVER == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + #endif + #else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression) + return; + #endif + + } + pDM_Odm->IQKFWOffload = 0; + + //3 == FW IQK == + if(pDM_Odm->IQKFWOffload) + { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + phy_IQCalibrate_By_FW_8821A(pDM_Odm); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + for(counter = 0; counter < 10; counter++){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter)); + ODM_delay_ms(50); + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n")); + break; + } + } + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtl8812_iqk_wait(pAdapter, 500); + #endif + if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n")); + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + //3 == Driver IQK == + else { + if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + + pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime( pDM_Odm); + phy_IQCalibrate_8821A(pDM_Odm); + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime( pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); + + ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } + } + +} +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.h b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.h index 8c74fece7ce..074d08587cb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_iqk_8821a_win.h @@ -1,48 +1,48 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDM_IQK_8821A_H__ -#define __PHYDM_IQK_8821A_H__ - -/*--------------------------Define Parameters-------------------------------*/ - - -/*---------------------------End Define Parameters-------------------------------*/ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void -DoIQK_8821A( - PDM_ODM_T pDM_Odm, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -void -PHY_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN bReCovery -); -#else -VOID -phy_IQCalibrate_8821A( - IN PDM_ODM_T pDM_Odm - ); -#endif -#endif // #ifndef __PHYDM_IQK_8821A_H__ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_IQK_8821A_H__ +#define __PHYDM_IQK_8821A_H__ + +/*--------------------------Define Parameters-------------------------------*/ + + +/*---------------------------End Define Parameters-------------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void +DoIQK_8821A( + PDM_ODM_T pDM_Odm, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +void +PHY_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bReCovery +); +#else +VOID +phy_IQCalibrate_8821A( + IN PDM_ODM_T pDM_Odm + ); +#endif +#endif // #ifndef __PHYDM_IQK_8821A_H__ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.c b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.c index c09db08bf56..d37d2b872fb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.c @@ -1,220 +1,220 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821A_SUPPORT == 1) - -void -odm_ConfigRFReg_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if(Addr == 0xfe || Addr == 0xffe) - { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } - else if (Addr == 0xfd) - { - ODM_delay_ms(5); - } - else if (Addr == 0xfc) - { - ODM_delay_ms(1); - } - else if (Addr == 0xfb) - { - ODM_delay_us(50); - } - else if (Addr == 0xfa) - { - ODM_delay_us(5); - } - else if (Addr == 0xf9) - { - ODM_delay_us(1); - } - else - { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - } -} - - -void -odm_ConfigRF_RadioA_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; // RF_Content: radioa_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8821A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -// 8821 no RF B -/* -void -odm_ConfigRF_RadioB_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; // RF_Content: radiob_txt - u4Byte maskforPhySet= (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); - -} -*/ - -void -odm_ConfigMAC_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_AGC_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); - -#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - -} - -void -odm_ConfigBB_PHY_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else if (Addr == 0xa24) - pDM_Odm->RFCalibrateInfo.RegA24 = Data; - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - // Add 1us delay between BB/RF register setting. - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif /* #if (RTL8821A_SUPPORT == 1)*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821A_SUPPORT == 1) + +void +odm_ConfigRFReg_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd) + { + ODM_delay_ms(5); + } + else if (Addr == 0xfc) + { + ODM_delay_ms(1); + } + else if (Addr == 0xfb) + { + ODM_delay_us(50); + } + else if (Addr == 0xfa) + { + ODM_delay_us(5); + } + else if (Addr == 0xf9) + { + ODM_delay_us(1); + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8821A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +// 8821 no RF B +/* +void +odm_ConfigRF_RadioB_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} +*/ + +void +odm_ConfigMAC_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); + +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + +} + +void +odm_ConfigBB_PHY_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif /* #if (RTL8821A_SUPPORT == 1)*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.h b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.h index a07fd74016e..14b9e997051 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_regconfig8821a.h @@ -1,96 +1,96 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8821A -#define __INC_ODM_REGCONFIG_H_8821A - -#if (RTL8821A_SUPPORT == 1) - -void -odm_ConfigRFReg_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_ConfigBB_AGC_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8821A( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8821A( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif // end of SUPPORT - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8821A +#define __INC_ODM_REGCONFIG_H_8821A + +#if (RTL8821A_SUPPORT == 1) + +void +odm_ConfigRFReg_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8821A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8821A( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.c b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.c index cd0247421b1..b4b2f8261d4 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.c @@ -1,97 +1,97 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ - -#include "mp_precomp.h" - -#include "../phydm_precomp.h" - -#if (RTL8821A_SUPPORT == 1) - -VOID -phydm_set_ext_band_switch_8821A( - IN PVOID pDM_VOID, - IN u4Byte band - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*Output Pin Settings*/ - ODM_SetMACReg(pDM_Odm, 0x4C, BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ - ODM_SetMACReg(pDM_Odm, 0x4C, BIT24, 1); /*by WLAN control*/ - - ODM_SetBBReg(pDM_Odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ - ODM_SetBBReg(pDM_Odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ - - if (band == ODM_BAND_2_4G) { - ODM_SetBBReg(pDM_Odm, 0xCB4, (BIT29|BIT28), 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A set band switch = 2b'01\n")); - } else { - ODM_SetBBReg(pDM_Odm, 0xCB4, BIT29|BIT28, 2); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A set band switch = 2b'10\n")); - } -} - - -VOID -odm_DynamicTryStateAgg_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - if((pDM_Odm->SupportICType & ODM_RTL8821) && (pDM_Odm->SupportInterface == ODM_ITRF_USB)) { - if(pDM_Odm->RSSI_Min > 25) - ODM_Write1Byte(pDM_Odm, 0x4CF, 0x02); - else if(pDM_Odm->RSSI_Min < 20) - ODM_Write1Byte(pDM_Odm, 0x4CF, 0x00); - } -} - -VOID -odm_DynamicPacketdetectionTH_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - if (pDM_Odm->SupportICType & ODM_RTL8821) { - if (pDM_Odm->RSSI_Min <= 25) { - /*ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaf1a8);*/ - ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, 0x1ff0, 0x11a); - ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 1); - } else if (pDM_Odm->RSSI_Min >= 30) { - /*ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaeec8);*/ - ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, 0x1ff0, 0xec); - ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 0); - } - } -} - -VOID -odm_HWSetting_8821A( - IN PDM_ODM_T pDM_Odm - ) -{ - odm_DynamicTryStateAgg_8821A(pDM_Odm); - odm_DynamicPacketdetectionTH_8821A(pDM_Odm); -} - -#endif //#if (RTL8821A_SUPPORT == 1) - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8821A_SUPPORT == 1) + +VOID +phydm_set_ext_band_switch_8821A( + IN PVOID pDM_VOID, + IN u4Byte band + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*Output Pin Settings*/ + ODM_SetMACReg(pDM_Odm, 0x4C, BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ + ODM_SetMACReg(pDM_Odm, 0x4C, BIT24, 1); /*by WLAN control*/ + + ODM_SetBBReg(pDM_Odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ + ODM_SetBBReg(pDM_Odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ + + if (band == ODM_BAND_2_4G) { + ODM_SetBBReg(pDM_Odm, 0xCB4, (BIT29|BIT28), 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A set band switch = 2b'01\n")); + } else { + ODM_SetBBReg(pDM_Odm, 0xCB4, BIT29|BIT28, 2); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A set band switch = 2b'10\n")); + } +} + + +VOID +odm_DynamicTryStateAgg_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + if((pDM_Odm->SupportICType & ODM_RTL8821) && (pDM_Odm->SupportInterface == ODM_ITRF_USB)) { + if(pDM_Odm->RSSI_Min > 25) + ODM_Write1Byte(pDM_Odm, 0x4CF, 0x02); + else if(pDM_Odm->RSSI_Min < 20) + ODM_Write1Byte(pDM_Odm, 0x4CF, 0x00); + } +} + +VOID +odm_DynamicPacketdetectionTH_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + if (pDM_Odm->SupportICType & ODM_RTL8821) { + if (pDM_Odm->RSSI_Min <= 25) { + /*ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaf1a8);*/ + ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, 0x1ff0, 0x11a); + ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 1); + } else if (pDM_Odm->RSSI_Min >= 30) { + /*ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaeec8);*/ + ODM_SetBBReg(pDM_Odm, rPwed_TH_Jaguar, 0x1ff0, 0xec); + ODM_SetBBReg(pDM_Odm, rBWIndication_Jaguar, BIT26, 0); + } + } +} + +VOID +odm_HWSetting_8821A( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_DynamicTryStateAgg_8821A(pDM_Odm); + odm_DynamicPacketdetectionTH_8821A(pDM_Odm); +} + +#endif //#if (RTL8821A_SUPPORT == 1) + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.h b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.h index e56720bd483..0bb129a3ba5 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/phydm_rtl8821a.h @@ -1,35 +1,35 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __ODM_RTL8821A_H__ -#define __ODM_RTL8821A_H__ - -VOID -phydm_set_ext_band_switch_8821A( - IN PVOID pDM_VOID, - IN u4Byte band -); - -VOID -odm_HWSetting_8821A( - IN PDM_ODM_T pDM_Odm -); - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8821A_H__ +#define __ODM_RTL8821A_H__ + +VOID +phydm_set_ext_band_switch_8821A( + IN PVOID pDM_VOID, + IN u4Byte band +); + +VOID +odm_HWSetting_8821A( + IN PDM_ODM_T pDM_Odm +); + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821a/version_rtl8821a.h b/package/kernel/rtl8192cd/phydm/rtl8821a/version_rtl8821a.h index 7a142048a44..c36f31ae71e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821a/version_rtl8821a.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821a/version_rtl8821a.h @@ -1,10 +1,10 @@ -/*RTL8821A PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. - You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8821A 20150920 -#define COMMIT_BY_8821A "BB_LUKE" -#define RELEASE_VERSION_8821A 59 +/*RTL8821A PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8821A 20150920 +#define COMMIT_BY_8821A "BB_LUKE" +#define RELEASE_VERSION_8821A 59 diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.c b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.c index f68254164d4..e33cc150bb1 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.c @@ -1,1926 +1,1926 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821C_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_TC_8821C_AGC_TAB[] = { - 0x81C, 0xFB000003, - 0x81C, 0xFA020003, - 0x81C, 0xF9040003, - 0x81C, 0xF8060003, - 0x81C, 0xF7080003, - 0x81C, 0xF60A0003, - 0x81C, 0xF50C0003, - 0x81C, 0xF40E0003, - 0x81C, 0xF3100003, - 0x81C, 0xF2120003, - 0x81C, 0xF1140003, - 0x81C, 0xF0160003, - 0x81C, 0xEF180003, - 0x81C, 0xEE1A0003, - 0x81C, 0xED1C0003, - 0x81C, 0xEC1E0003, - 0x81C, 0xEB200003, - 0x81C, 0xEA220003, - 0x81C, 0xE9240003, - 0x81C, 0xE8260003, - 0x81C, 0xE7280003, - 0x81C, 0xE62A0003, - 0x81C, 0xCA2C0003, - 0x81C, 0xC92E0003, - 0x81C, 0xC8300003, - 0x81C, 0xC7320003, - 0x81C, 0xC6340003, - 0x81C, 0xC5360003, - 0x81C, 0xC4380003, - 0x81C, 0xC33A0003, - 0x81C, 0xC23C0003, - 0x81C, 0xC13E0003, - 0x81C, 0x88400003, - 0x81C, 0x87420003, - 0x81C, 0x86440003, - 0x81C, 0x85460003, - 0x81C, 0x84480003, - 0x81C, 0x834A0003, - 0x81C, 0x674C0003, - 0x81C, 0x664E0003, - 0x81C, 0x65500003, - 0x81C, 0x64520003, - 0x81C, 0x63540003, - 0x81C, 0x62560003, - 0x81C, 0x61580003, - 0x81C, 0x455A0003, - 0x81C, 0x445C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x25640003, - 0x81C, 0x24660003, - 0x81C, 0x23680003, - 0x81C, 0x226A0003, - 0x81C, 0x216C0003, - 0x81C, 0x016E0003, - 0x81C, 0x01700003, - 0x81C, 0x01720003, - 0x81C, 0x01740003, - 0x81C, 0x01760003, - 0x81C, 0x01780003, - 0x81C, 0x017A0003, - 0x81C, 0x017C0003, - 0x81C, 0x017E0003, - 0x81C, 0xFF000103, - 0x81C, 0xFF020103, - 0x81C, 0xFF040103, - 0x81C, 0xFE060103, - 0x81C, 0xFD080103, - 0x81C, 0xFC0A0103, - 0x81C, 0xFB0C0103, - 0x81C, 0xFA0E0103, - 0x81C, 0xF9100103, - 0x81C, 0xF8120103, - 0x81C, 0xF7140103, - 0x81C, 0xF6160103, - 0x81C, 0xF5180103, - 0x81C, 0xF41A0103, - 0x81C, 0xF31C0103, - 0x81C, 0xF21E0103, - 0x81C, 0xF1200103, - 0x81C, 0xF0220103, - 0x81C, 0xEF240103, - 0x81C, 0xEE260103, - 0x81C, 0xED280103, - 0x81C, 0xEC2A0103, - 0x81C, 0xEB2C0103, - 0x81C, 0xEA2E0103, - 0x81C, 0xE9300103, - 0x81C, 0xE8320103, - 0x81C, 0xE7340103, - 0x81C, 0xE6360103, - 0x81C, 0xE5380103, - 0x81C, 0xE43A0103, - 0x81C, 0xC63C0103, - 0x81C, 0xC53E0103, - 0x81C, 0xC4400103, - 0x81C, 0xC3420103, - 0x81C, 0xC2440103, - 0x81C, 0xC1460103, - 0x81C, 0xA3480103, - 0x81C, 0xA24A0103, - 0x81C, 0xA14C0103, - 0x81C, 0x834E0103, - 0x81C, 0x82500103, - 0x81C, 0x81520103, - 0x81C, 0x64540103, - 0x81C, 0x63560103, - 0x81C, 0x62580103, - 0x81C, 0x615A0103, - 0x81C, 0x425C0103, - 0x81C, 0x415E0103, - 0x81C, 0x24600103, - 0x81C, 0x23620103, - 0x81C, 0x22640103, - 0x81C, 0x21660103, - 0x81C, 0x03680103, - 0x81C, 0x026A0103, - 0x81C, 0x016C0103, - 0x81C, 0x016E0103, - 0x81C, 0x01700103, - 0x81C, 0x01720103, - 0x81C, 0x01740103, - 0x81C, 0x01760103, - 0x81C, 0x01780103, - 0x81C, 0x017A0103, - 0x81C, 0x017C0103, - 0x81C, 0x017E0103, - 0x81C, 0xFF000203, - 0x81C, 0xFF020203, - 0x81C, 0xFE040203, - 0x81C, 0xFD060203, - 0x81C, 0xFC080203, - 0x81C, 0xFB0A0203, - 0x81C, 0xFA0C0203, - 0x81C, 0xF90E0203, - 0x81C, 0xF8100203, - 0x81C, 0xF7120203, - 0x81C, 0xF6140203, - 0x81C, 0xF5160203, - 0x81C, 0xF4180203, - 0x81C, 0xF31A0203, - 0x81C, 0xF21C0203, - 0x81C, 0xF11E0203, - 0x81C, 0xF0200203, - 0x81C, 0xEF220203, - 0x81C, 0xEE240203, - 0x81C, 0xED260203, - 0x81C, 0xEC280203, - 0x81C, 0xEB2A0203, - 0x81C, 0xEA2C0203, - 0x81C, 0xE92E0203, - 0x81C, 0xE8300203, - 0x81C, 0xE7320203, - 0x81C, 0xE6340203, - 0x81C, 0xE5360203, - 0x81C, 0xE4380203, - 0x81C, 0xE33A0203, - 0x81C, 0xE23C0203, - 0x81C, 0xE13E0203, - 0x81C, 0xC4400203, - 0x81C, 0xC3420203, - 0x81C, 0xC2440203, - 0x81C, 0xC1460203, - 0x81C, 0xA3480203, - 0x81C, 0xA24A0203, - 0x81C, 0xA14C0203, - 0x81C, 0x834E0203, - 0x81C, 0x82500203, - 0x81C, 0x81520203, - 0x81C, 0x64540203, - 0x81C, 0x63560203, - 0x81C, 0x62580203, - 0x81C, 0x615A0203, - 0x81C, 0x425C0203, - 0x81C, 0x415E0203, - 0x81C, 0x22600203, - 0x81C, 0x21620203, - 0x81C, 0x04640203, - 0x81C, 0x03660203, - 0x81C, 0x02680203, - 0x81C, 0x016A0203, - 0x81C, 0x016C0203, - 0x81C, 0x016E0203, - 0x81C, 0x01700203, - 0x81C, 0x01720203, - 0x81C, 0x01740203, - 0x81C, 0x01760203, - 0x81C, 0x01780203, - 0x81C, 0x017A0203, - 0x81C, 0x017C0203, - 0x81C, 0x017E0203, - 0x81C, 0xFF000303, - 0x81C, 0xFF020303, - 0x81C, 0xFE040303, - 0x81C, 0xFD060303, - 0x81C, 0xFC080303, - 0x81C, 0xFB0A0303, - 0x81C, 0xFA0C0303, - 0x81C, 0xF90E0303, - 0x81C, 0xF8100303, - 0x81C, 0xF7120303, - 0x81C, 0xF6140303, - 0x81C, 0xF5160303, - 0x81C, 0xF4180303, - 0x81C, 0xF31A0303, - 0x81C, 0xF21C0303, - 0x81C, 0xF11E0303, - 0x81C, 0xF0200303, - 0x81C, 0xEF220303, - 0x81C, 0xEE240303, - 0x81C, 0xED260303, - 0x81C, 0xEC280303, - 0x81C, 0xEB2A0303, - 0x81C, 0xEA2C0303, - 0x81C, 0xE92E0303, - 0x81C, 0xE8300303, - 0x81C, 0xE7320303, - 0x81C, 0xE6340303, - 0x81C, 0xE5360303, - 0x81C, 0xE4380303, - 0x81C, 0xE33A0303, - 0x81C, 0xE23C0303, - 0x81C, 0xE13E0303, - 0x81C, 0xC4400303, - 0x81C, 0xC3420303, - 0x81C, 0xC2440303, - 0x81C, 0xC1460303, - 0x81C, 0xA4480303, - 0x81C, 0xA34A0303, - 0x81C, 0xA24C0303, - 0x81C, 0xA14E0303, - 0x81C, 0x83500303, - 0x81C, 0x82520303, - 0x81C, 0x81540303, - 0x81C, 0x64560303, - 0x81C, 0x63580303, - 0x81C, 0x625A0303, - 0x81C, 0x615C0303, - 0x81C, 0x425E0303, - 0x81C, 0x41600303, - 0x81C, 0x23620303, - 0x81C, 0x22640303, - 0x81C, 0x21660303, - 0x81C, 0x03680303, - 0x81C, 0x026A0303, - 0x81C, 0x016C0303, - 0x81C, 0x016E0303, - 0x81C, 0x01700303, - 0x81C, 0x01720303, - 0x81C, 0x01740303, - 0x81C, 0x01760303, - 0x81C, 0x01780303, - 0x81C, 0x017A0303, - 0x81C, 0x017C0303, - 0x81C, 0x017E0303, - 0x81C, 0xFB000403, - 0x81C, 0xFA020403, - 0x81C, 0xF9040403, - 0x81C, 0xF8060403, - 0x81C, 0xF7080403, - 0x81C, 0xF60A0403, - 0x81C, 0xF50C0403, - 0x81C, 0xF40E0403, - 0x81C, 0xF3100403, - 0x81C, 0xF2120403, - 0x81C, 0xF1140403, - 0x81C, 0xF0160403, - 0x81C, 0xEF180403, - 0x81C, 0xEE1A0403, - 0x81C, 0xED1C0403, - 0x81C, 0xB61E0403, - 0x81C, 0xB5200403, - 0x81C, 0xB4220403, - 0x81C, 0xB3240403, - 0x81C, 0xB2260403, - 0x81C, 0xB1280403, - 0x81C, 0xAF2A0403, - 0x81C, 0xAE2C0403, - 0x81C, 0xAD2E0403, - 0x81C, 0xAC300403, - 0x81C, 0xAB320403, - 0x81C, 0xAA340403, - 0x81C, 0xA9360403, - 0x81C, 0xA8380403, - 0x81C, 0xA73A0403, - 0x81C, 0xA63C0403, - 0x81C, 0xA53E0403, - 0x81C, 0x88400403, - 0x81C, 0x87420403, - 0x81C, 0x86440403, - 0x81C, 0x85460403, - 0x81C, 0x84480403, - 0x81C, 0x834A0403, - 0x81C, 0x674C0403, - 0x81C, 0x664E0403, - 0x81C, 0x65500403, - 0x81C, 0x64520403, - 0x81C, 0x63540403, - 0x81C, 0x62560403, - 0x81C, 0x61580403, - 0x81C, 0x455A0403, - 0x81C, 0x445C0403, - 0x81C, 0x435E0403, - 0x81C, 0x42600403, - 0x81C, 0x41620403, - 0x81C, 0x25640403, - 0x81C, 0x24660403, - 0x81C, 0x23680403, - 0x81C, 0x226A0403, - 0x81C, 0x216C0403, - 0x81C, 0x016E0403, - 0x81C, 0x01700403, - 0x81C, 0x01720403, - 0x81C, 0x01740403, - 0x81C, 0x01760403, - 0x81C, 0x01780403, - 0x81C, 0x017A0403, - 0x81C, 0x017C0403, - 0x81C, 0x017E0403, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - -}; - -void -ODM_ReadAndConfig_TC_8821C_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_TC_8821C_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_TC_8821C_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8821C(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_TC_8821C_AGC_TAB(void) -{ - return 9; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_TC_8821C_PHY_REG[] = { - 0x800, 0x9020D010, - 0x804, 0x80018180, - 0x808, 0x04028211, - 0x80C, 0x13D10011, - 0x810, 0x21101263, - 0x814, 0x020C3D10, - 0x818, 0x84A10385, - 0x81C, 0x1E1E081F, - 0x820, 0x0001AAAA, - 0x824, 0x00030FE0, - 0x828, 0x0000CCCC, - 0x82C, 0x75CB7010, - 0x830, 0x79A0EA2A, - 0x834, 0x072E6986, - 0x838, 0x87766461, - 0x83C, 0x9194B2B6, - 0x840, 0x171740E0, - 0x844, 0x4D3D7CDB, - 0x848, 0x4AD0408B, - 0x84C, 0x6AFBF7A5, - 0x850, 0x28A74706, - 0x854, 0x0001520C, - 0x858, 0x4060C000, - 0x85C, 0x74010360, - 0x860, 0x68A7C321, - 0x864, 0x79F27432, - 0x868, 0x8CA7A314, - 0x86C, 0x778C2878, - 0x870, 0x77777777, - 0x874, 0x27612C2E, - 0x878, 0xC0003152, - 0x87C, 0x5C8FC000, - 0x880, 0x00000000, - 0x884, 0x00000000, - 0x888, 0x00000000, - 0x88C, 0x00000000, - 0x890, 0x00000000, - 0x894, 0x00000000, - 0x898, 0x00000000, - 0x89C, 0x00000000, - 0x8A0, 0x00000013, - 0x8A4, 0x7F7F7F7F, - 0x8A8, 0x2202033E, - 0x8AC, 0xF00F000A, - 0x8B0, 0x00000600, - 0x8B4, 0x000FC080, - 0x8B8, 0xEC0057FF, - 0x8BC, 0xACB520A3, - 0x8C0, 0xFFE04020, - 0x8C4, 0x47C00000, - 0x8C8, 0x000251A5, - 0x8CC, 0x08108492, - 0x8D0, 0x0000B800, - 0x8D4, 0x860308A0, - 0x8D8, 0x290B5612, - 0x8DC, 0x00000000, - 0x8E0, 0x32D16777, - 0x8E4, 0x49092925, - 0x8E8, 0xFFFFC42C, - 0x8EC, 0x99999999, - 0x8F0, 0x00009999, - 0x8F4, 0x00D80FA1, - 0x8F8, 0x400000C0, - 0x8FC, 0x00000130, - 0x900, 0x00C00000, - 0x904, 0x0FFF0FFF, - 0x908, 0x00000000, - 0x90C, 0x13000000, - 0x910, 0x0000FC00, - 0x914, 0xC6380000, - 0x918, 0x1C1028C0, - 0x91C, 0x64B11A1C, - 0x920, 0xE0767233, - 0x924, 0x055A2500, - 0x928, 0x4AB0E4E4, - 0x92C, 0xFFFEB200, - 0x930, 0xFFFFFFFE, - 0x934, 0x001FFFFF, - 0x938, 0x00008480, - 0x93C, 0xE41C0642, - 0x940, 0x0E470430, - 0x944, 0x00000000, - 0x948, 0xAC000000, - 0x94C, 0x10000083, - 0x950, 0xF2010080, - 0x954, 0x86510080, - 0x958, 0x00000001, - 0x95C, 0x04248000, - 0x960, 0x00000000, - 0x964, 0x00000000, - 0x968, 0x00000000, - 0x96C, 0x00000000, - 0x970, 0x00001FFF, - 0x974, 0x04000FFF, - 0x978, 0x00000000, - 0x97C, 0x00000000, - 0x980, 0x00000000, - 0x984, 0x00000000, - 0x988, 0x00000000, - 0x98C, 0x23440000, - 0x990, 0x27100000, - 0x994, 0xFFFF0100, - 0x998, 0xFFFFFF5C, - 0x99C, 0xFFFFFFFF, - 0x9A0, 0x000000FF, - 0x9A4, 0x80000088, - 0x9A8, 0x0C2F0000, - 0x9AC, 0x01560000, - 0x9B0, 0x70000000, - 0x9B4, 0x00000000, - 0x9B8, 0x00000000, - 0x9BC, 0x00000000, - 0x9C0, 0x00000000, - 0x9C4, 0x00000000, - 0x9C8, 0x00000000, - 0x9CC, 0x00000000, - 0x9D0, 0x00000000, - 0x9D4, 0x00000000, - 0x9D8, 0x00000000, - 0x9DC, 0x00000000, - 0x9E0, 0x00000000, - 0x9E4, 0x02000402, - 0x9E8, 0x000022D4, - 0x9EC, 0x00000000, - 0x9F0, 0x00000000, - 0x9F4, 0x00000000, - 0x9F8, 0x00000000, - 0x9FC, 0xEFFFF7FF, - 0xA00, 0x00D047C8, - 0xA04, 0x80FF800C, - 0xA08, 0x9C838300, - 0xA0C, 0x2E20200F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0xE82C0000, - 0xA24, 0x64B80C1C, - 0xA28, 0x00008810, - 0xA2C, 0x00D20000, - 0xA70, 0x101FBF00, - 0xA74, 0x00000107, - 0xA78, 0x00008900, - 0xA7C, 0x225B0606, - 0xA80, 0x21807532, - 0xA84, 0x80200000, - 0xA88, 0x048C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x00000000, - 0xA9C, 0x00060000, - 0xAA0, 0x00000000, - 0xAA4, 0x00040000, - 0xAA8, 0xEACF0004, - 0xAAC, 0x01235667, - 0xAB0, 0x00000000, - 0xB00, 0xE1000440, - 0xB04, 0x00800000, - 0xB08, 0xFF02030B, - 0xB0C, 0x01EAA406, - 0xB10, 0x00030690, - 0xB14, 0x006000FA, - 0xB18, 0x00000002, - 0xB1C, 0x00000002, - 0xB20, 0x4B00001F, - 0xB24, 0x4E8E3E40, - 0xB28, 0x03020100, - 0xB2C, 0x07060504, - 0xB30, 0x0B0A0908, - 0xB34, 0x0F0E0D0C, - 0xB38, 0x13121110, - 0xB3C, 0x0000003A, - 0xB40, 0x00000000, - 0xB44, 0x80000000, - 0xB48, 0x3F0000FA, - 0xB4C, 0x88C80020, - 0xB50, 0x00000000, - 0xB54, 0x00004241, - 0xB58, 0xE0008208, - 0xB5C, 0x41EFFFF9, - 0xB60, 0x00000000, - 0xB64, 0x00200063, - 0xB68, 0x0000003A, - 0xB6C, 0x00000102, - 0xB70, 0x4E6D1870, - 0xB74, 0x03020100, - 0xB78, 0x07060504, - 0xB7C, 0x0B0A0908, - 0xB80, 0x0F0E0D0C, - 0xB84, 0x13121110, - 0xB88, 0x00000000, - 0xB8C, 0x00000000, - 0xC00, 0x00000007, - 0xC04, 0x03000020, - 0xC08, 0x60403231, - 0xC0C, 0x00012345, - 0xC10, 0x00000100, - 0xC14, 0x01000000, - 0xC18, 0x00000000, - 0xC1C, 0x40040053, - 0xC20, 0x000503A3, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x00000000, - 0xC34, 0x00000000, - 0xC38, 0x00000000, - 0xC3C, 0x00000000, - 0xC40, 0x00000000, - 0xC44, 0x00000000, - 0xC48, 0x00000000, - 0xC4C, 0x00000000, - 0xC50, 0x00000020, - 0xC54, 0x00000000, - 0xC58, 0xD8020402, - 0xC5C, 0xDE000120, - 0xC68, 0x00000179, - 0xC6C, 0x0000122A, - 0xC70, 0x00000000, - 0xC74, 0x00000000, - 0xC78, 0x00000000, - 0xC7C, 0x00000000, - 0xC80, 0x00000000, - 0xC84, 0x00000000, - 0xC88, 0x00000000, - 0xC8C, 0x07000000, - 0xC94, 0x01000100, - 0xC98, 0x201C8000, - 0xC9C, 0x00000000, - 0xCA0, 0x0000A555, - 0xCA4, 0x08040201, - 0xCA8, 0x80402010, - 0xCAC, 0x00000000, - 0xCB0, 0x98543210, - 0xCB4, 0x10000077, - 0xCB8, 0x00000000, - 0xCBC, 0x00000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x00000000, - 0xCDC, 0x00000000, - 0xCE0, 0x00000000, - 0xCE4, 0x00000000, - 0xCE8, 0x00000000, - 0xCEC, 0x00000000, - 0xE00, 0x00000007, - 0xE04, 0x00000020, - 0xE08, 0x60403231, - 0xE0C, 0x00012345, - 0xE10, 0x00000100, - 0xE14, 0x01000000, - 0xE18, 0x00000000, - 0xE1C, 0x40040053, - 0xE20, 0x00020103, - 0xE24, 0x00000000, - 0xE28, 0x00000000, - 0xE2C, 0x00000000, - 0xE30, 0x00000000, - 0xE34, 0x00000000, - 0xE38, 0x00000000, - 0xE3C, 0x00000000, - 0xE40, 0x00000000, - 0xE44, 0x00000000, - 0xE48, 0x00000000, - 0xE4C, 0x00000000, - 0xE50, 0x00000020, - 0xE54, 0x00000000, - 0xE58, 0xD8020402, - 0xE5C, 0xDE000120, - 0xE68, 0x59799979, - 0xE6C, 0x0000122A, - 0xE70, 0x99795979, - 0xE74, 0x99795979, - 0xE78, 0x99799979, - 0xE7C, 0x99791979, - 0xE80, 0x19791979, - 0xE84, 0x19791979, - 0xE88, 0x00000000, - 0xE8C, 0x07000000, - 0xE94, 0x01000100, - 0xE98, 0x201C8000, - 0xE9C, 0x00000000, - 0xEA0, 0x0000A555, - 0xEA4, 0x08040201, - 0xEA8, 0x80402010, - 0xEAC, 0x00000000, - 0xEB0, 0x98543210, - 0xEB4, 0x000000BA, - 0xEB8, 0x00000000, - 0xEBC, 0x00000000, - 0xEC0, 0x00000000, - 0xEC4, 0x00000000, - 0xEC8, 0x00000000, - 0xECC, 0x00000000, - 0xED0, 0x00000000, - 0xED4, 0x00000000, - 0xED8, 0x00000000, - 0xEDC, 0x00000000, - 0xEE0, 0x00000000, - 0xEE4, 0x00000000, - 0xEE8, 0x00000000, - 0xEEC, 0x00000000, - 0x1900, 0x00000000, - 0x1904, 0x00238000, - 0x1908, 0x00000000, - 0x190C, 0x00000000, - 0x1910, 0x00000000, - 0x1914, 0x00000000, - 0x1918, 0x00000000, - 0x191C, 0x00000000, - 0x1920, 0x00000000, - 0x1924, 0x00000000, - 0x1928, 0x00000000, - 0x192C, 0x00000000, - 0x1930, 0x00000000, - 0x1934, 0x00000000, - 0x1938, 0x00000000, - 0x193C, 0x00000000, - 0x1940, 0x00000000, - 0x1944, 0x00000000, - 0x1948, 0x00000000, - 0x194C, 0x00000000, - 0x1950, 0x00000000, - 0x1954, 0x00000000, - 0x1958, 0x00000000, - 0x195C, 0x00000000, - 0x1960, 0x00000000, - 0x1964, 0x00000000, - 0x1968, 0x00000000, - 0x196C, 0x00000000, - 0x1970, 0x00000000, - 0x1974, 0x00000000, - 0x1978, 0x00000000, - 0x197C, 0x00000000, - 0x1980, 0x00000000, - 0x1984, 0x03000000, - 0x1988, 0x21401E88, - 0x198C, 0x00004000, - 0x1990, 0x00000000, - 0x1994, 0x00000000, - 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0x1B80, 0x63030D47, - 0x1B80, 0xE1060D55, - 0x1B80, 0xE1060D57, - 0x1B80, 0x67000D65, - 0x1B80, 0x67000D67, - 0x1B80, 0xE1340D75, - 0x1B80, 0xE1340D77, - 0x1B80, 0xE15F0D85, - 0x1B80, 0xE15F0D87, - 0x1B80, 0x67030D95, - 0x1B80, 0x67030D97, - 0x1B80, 0xE1340DA5, - 0x1B80, 0xE1340DA7, - 0x1B80, 0xE15F0DB5, - 0x1B80, 0xE15F0DB7, - 0x1B80, 0xF6C90DC5, - 0x1B80, 0xF6C90DC7, - 0x1B80, 0x67070DD5, - 0x1B80, 0x67070DD7, - 0x1B80, 0xE1340DE5, - 0x1B80, 0xE1340DE7, - 0x1B80, 0xE15F0DF5, - 0x1B80, 0xE15F0DF7, - 0x1B80, 0xF7D00E05, - 0x1B80, 0xF7D00E07, - 0x1B80, 0x5C320E15, - 0x1B80, 0x5C320E17, - 0x1B80, 0x630B0E25, - 0x1B80, 0x630B0E27, - 0x1B80, 0xE1060E35, - 0x1B80, 0xE1060E37, - 0x1B80, 0x670B0E45, - 0x1B80, 0x670B0E47, - 0x1B80, 0xE1340E55, - 0x1B80, 0xE1340E57, - 0x1B80, 0xE15F0E65, - 0x1B80, 0xE15F0E67, - 0x1B80, 0x670E0E75, - 0x1B80, 0x670E0E77, - 0x1B80, 0xE1340E85, - 0x1B80, 0xE1340E87, - 0x1B80, 0xE15F0E95, - 0x1B80, 0xE15F0E97, - 0x1B80, 0x4D100EA5, - 0x1B80, 0x4D100EA7, - 0x1B80, 0x308C0EB5, - 0x1B80, 0x308C0EB7, - 0x1B80, 0x00010EC5, - 0x1B80, 0x00010EC7, - 0x1B80, 0x62850ED5, - 0x1B80, 0x62850ED7, - 0x1B80, 0xE1060EE5, - 0x1B80, 0xE1060EE7, - 0x1B80, 0x00010EF5, - 0x1B80, 0x00010EF7, - 0x1B80, 0xE1340F05, - 0x1B80, 0xE1340F07, - 0x1B80, 0x00010F15, - 0x1B80, 0x00010F17, - 0x1B80, 0x7B240F25, - 0x1B80, 0x7B240F27, - 0x1B80, 0x7A400F35, - 0x1B80, 0x7A400F37, - 0x1B80, 0x79000F45, - 0x1B80, 0x79000F47, - 0x1B80, 0x55030F55, - 0x1B80, 0x55030F57, - 0x1B80, 0x30FE0F65, - 0x1B80, 0x30FE0F67, - 0x1B80, 0x7B1C0F75, - 0x1B80, 0x7B1C0F77, - 0x1B80, 0x7A400F85, - 0x1B80, 0x7A400F87, - 0x1B80, 0x550B0F95, - 0x1B80, 0x550B0F97, - 0x1B80, 0x30FE0FA5, - 0x1B80, 0x30FE0FA7, - 0x1B80, 0x7B200FB5, - 0x1B80, 0x7B200FB7, - 0x1B80, 0x7A000FC5, - 0x1B80, 0x7A000FC7, - 0x1B80, 0x55130FD5, - 0x1B80, 0x55130FD7, - 0x1B80, 0x74010FE5, - 0x1B80, 0x74010FE7, - 0x1B80, 0x74000FF5, - 0x1B80, 0x74000FF7, - 0x1B80, 0x8E001005, - 0x1B80, 0x8E001007, - 0x1B80, 0x00011015, - 0x1B80, 0x00011017, - 0x1B80, 0x57021025, - 0x1B80, 0x57021027, - 0x1B80, 0x57001035, - 0x1B80, 0x57001037, - 0x1B80, 0x97001045, - 0x1B80, 0x97001047, - 0x1B80, 0x00011055, - 0x1B80, 0x00011057, - 0x1B80, 0x4F781065, - 0x1B80, 0x4F781067, - 0x1B80, 0x53881075, - 0x1B80, 0x53881077, - 0x1B80, 0xE1141085, - 0x1B80, 0xE1141087, - 0x1B80, 0x54801095, - 0x1B80, 0x54801097, - 0x1B80, 0x540010A5, - 0x1B80, 0x540010A7, - 0x1B80, 0xE11410B5, - 0x1B80, 0xE11410B7, - 0x1B80, 0x548110C5, - 0x1B80, 0x548110C7, - 0x1B80, 0x540010D5, - 0x1B80, 0x540010D7, - 0x1B80, 0xE11410E5, - 0x1B80, 0xE11410E7, - 0x1B80, 0x548210F5, - 0x1B80, 0x548210F7, - 0x1B80, 0x54001105, - 0x1B80, 0x54001107, - 0x1B80, 0xE11F1115, - 0x1B80, 0xE11F1117, - 0x1B80, 0xBF1D1125, - 0x1B80, 0xBF1D1127, - 0x1B80, 0x301D1135, - 0x1B80, 0x301D1137, - 0x1B80, 0xE0F21145, - 0x1B80, 0xE0F21147, - 0x1B80, 0xE0F71155, - 0x1B80, 0xE0F71157, - 0x1B80, 0xE0FB1165, - 0x1B80, 0xE0FB1167, - 0x1B80, 0xE1021175, - 0x1B80, 0xE1021177, - 0x1B80, 0xE1561185, - 0x1B80, 0xE1561187, - 0x1B80, 0x55131195, - 0x1B80, 0x55131197, - 0x1B80, 0xE0FE11A5, - 0x1B80, 0xE0FE11A7, - 0x1B80, 0x551511B5, - 0x1B80, 0x551511B7, - 0x1B80, 0xE10211C5, - 0x1B80, 0xE10211C7, - 0x1B80, 0xE15611D5, - 0x1B80, 0xE15611D7, - 0x1B80, 0x000111E5, - 0x1B80, 0x000111E7, - 0x1B80, 0x54BF11F5, - 0x1B80, 0x54BF11F7, - 0x1B80, 0x54C01205, - 0x1B80, 0x54C01207, - 0x1B80, 0x54A31215, - 0x1B80, 0x54A31217, - 0x1B80, 0x54C11225, - 0x1B80, 0x54C11227, - 0x1B80, 0x54A41235, - 0x1B80, 0x54A41237, - 0x1B80, 0x4C181245, - 0x1B80, 0x4C181247, - 0x1B80, 0xBF071255, - 0x1B80, 0xBF071257, - 0x1B80, 0x54C21265, - 0x1B80, 0x54C21267, - 0x1B80, 0x54A41275, - 0x1B80, 0x54A41277, - 0x1B80, 0xBF041285, - 0x1B80, 0xBF041287, - 0x1B80, 0x54C11295, - 0x1B80, 0x54C11297, - 0x1B80, 0x54A312A5, - 0x1B80, 0x54A312A7, - 0x1B80, 0xBF0112B5, - 0x1B80, 0xBF0112B7, - 0x1B80, 0xE16412C5, - 0x1B80, 0xE16412C7, - 0x1B80, 0x54DF12D5, - 0x1B80, 0x54DF12D7, - 0x1B80, 0x000112E5, - 0x1B80, 0x000112E7, - 0x1B80, 0x54BF12F5, - 0x1B80, 0x54BF12F7, - 0x1B80, 0x54E51305, - 0x1B80, 0x54E51307, - 0x1B80, 0x050A1315, - 0x1B80, 0x050A1317, - 0x1B80, 0x54DF1325, - 0x1B80, 0x54DF1327, - 0x1B80, 0x00011335, - 0x1B80, 0x00011337, - 0x1B80, 0x7F201345, - 0x1B80, 0x7F201347, - 0x1B80, 0x7E001355, - 0x1B80, 0x7E001357, - 0x1B80, 0x7D001365, - 0x1B80, 0x7D001367, - 0x1B80, 0x55011375, - 0x1B80, 0x55011377, - 0x1B80, 0x5C311385, - 0x1B80, 0x5C311387, - 0x1B80, 0xE0FE1395, - 0x1B80, 0xE0FE1397, - 0x1B80, 0xE10213A5, - 0x1B80, 0xE10213A7, - 0x1B80, 0x548013B5, - 0x1B80, 0x548013B7, - 0x1B80, 0x540013C5, - 0x1B80, 0x540013C7, - 0x1B80, 0xE0FE13D5, - 0x1B80, 0xE0FE13D7, - 0x1B80, 0xE10213E5, - 0x1B80, 0xE10213E7, - 0x1B80, 0x548113F5, - 0x1B80, 0x548113F7, - 0x1B80, 0x54001405, - 0x1B80, 0x54001407, - 0x1B80, 0xE0FE1415, - 0x1B80, 0xE0FE1417, - 0x1B80, 0xE1021425, - 0x1B80, 0xE1021427, - 0x1B80, 0x54821435, - 0x1B80, 0x54821437, - 0x1B80, 0x54001445, - 0x1B80, 0x54001447, - 0x1B80, 0xE11F1455, - 0x1B80, 0xE11F1457, - 0x1B80, 0xBFE91465, - 0x1B80, 0xBFE91467, - 0x1B80, 0x301D1475, - 0x1B80, 0x301D1477, - 0x1B80, 0x00231485, - 0x1B80, 0x00231487, - 0x1B80, 0x7B201495, - 0x1B80, 0x7B201497, - 0x1B80, 0x7A0014A5, - 0x1B80, 0x7A0014A7, - 0x1B80, 0x790014B5, - 0x1B80, 0x790014B7, - 0x1B80, 0xE15A14C5, - 0x1B80, 0xE15A14C7, - 0x1B80, 0x000214D5, - 0x1B80, 0x000214D7, - 0x1B80, 0x000114E5, - 0x1B80, 0x000114E7, - 0x1B80, 0x002214F5, - 0x1B80, 0x002214F7, - 0x1B80, 0x7B201505, - 0x1B80, 0x7B201507, - 0x1B80, 0x7A001515, - 0x1B80, 0x7A001517, - 0x1B80, 0x79001525, - 0x1B80, 0x79001527, - 0x1B80, 0xE15A1535, - 0x1B80, 0xE15A1537, - 0x1B80, 0x00021545, - 0x1B80, 0x00021547, - 0x1B80, 0x00011555, - 0x1B80, 0x00011557, - 0x1B80, 0x549F1565, - 0x1B80, 0x549F1567, - 0x1B80, 0x54FF1575, - 0x1B80, 0x54FF1577, - 0x1B80, 0x54001585, - 0x1B80, 0x54001587, - 0x1B80, 0x00011595, - 0x1B80, 0x00011597, - 0x1B80, 0x5C3115A5, - 0x1B80, 0x5C3115A7, - 0x1B80, 0x071415B5, - 0x1B80, 0x071415B7, - 0x1B80, 0x540015C5, - 0x1B80, 0x540015C7, - 0x1B80, 0x5C3215D5, - 0x1B80, 0x5C3215D7, - 0x1B80, 0x000115E5, - 0x1B80, 0x000115E7, - 0x1B80, 0x5C3215F5, - 0x1B80, 0x5C3215F7, - 0x1B80, 0x07141605, - 0x1B80, 0x07141607, - 0x1B80, 0x54001615, - 0x1B80, 0x54001617, - 0x1B80, 0x5C311625, - 0x1B80, 0x5C311627, - 0x1B80, 0x00011635, - 0x1B80, 0x00011637, - 0x1B80, 0x4C981645, - 0x1B80, 0x4C981647, - 0x1B80, 0x4C181655, - 0x1B80, 0x4C181657, - 0x1B80, 0x00011665, - 0x1B80, 0x00011667, - 0x1B80, 0x5C321675, - 0x1B80, 0x5C321677, - 0x1B80, 0x62841685, - 0x1B80, 0x62841687, - 0x1B80, 0x66861695, - 0x1B80, 0x66861697, - 0x1B80, 0x6C0316A5, - 0x1B80, 0x6C0316A7, - 0x1B80, 0x7B2016B5, - 0x1B80, 0x7B2016B7, - 0x1B80, 0x7A0016C5, - 0x1B80, 0x7A0016C7, - 0x1B80, 0x790016D5, - 0x1B80, 0x790016D7, - 0x1B80, 0x7F2016E5, - 0x1B80, 0x7F2016E7, - 0x1B80, 0x7E0016F5, - 0x1B80, 0x7E0016F7, - 0x1B80, 0x7D001705, - 0x1B80, 0x7D001707, - 0x1B80, 0x09011715, - 0x1B80, 0x09011717, - 0x1B80, 0x0C011725, - 0x1B80, 0x0C011727, - 0x1B80, 0x0BA61735, - 0x1B80, 0x0BA61737, - 0x1B80, 0x00011745, - 0x1B80, 0x00011747, - 0x1B80, 0x00000006, - 0x1B80, 0x00000002, - -}; - -void -ODM_ReadAndConfig_TC_8821C_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_TC_8821C_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_TC_8821C_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8821C(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_TC_8821C_PHY_REG(void) -{ - return 9; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_TC_8821C_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 0, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040, - 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040, - 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832, - 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, - 1, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040, - 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040, - 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832, - 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022 -}; - -void -ODM_ReadAndConfig_TC_8821C_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_TC_8821C_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_TC_8821C_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8821C(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821C_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_TC_8821C_AGC_TAB[] = { + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xCA2C0003, + 0x81C, 0xC92E0003, + 0x81C, 0xC8300003, + 0x81C, 0xC7320003, + 0x81C, 0xC6340003, + 0x81C, 0xC5360003, + 0x81C, 0xC4380003, + 0x81C, 0xC33A0003, + 0x81C, 0xC23C0003, + 0x81C, 0xC13E0003, + 0x81C, 0x88400003, + 0x81C, 0x87420003, + 0x81C, 0x86440003, + 0x81C, 0x85460003, + 0x81C, 0x84480003, + 0x81C, 0x834A0003, + 0x81C, 0x674C0003, + 0x81C, 0x664E0003, + 0x81C, 0x65500003, + 0x81C, 0x64520003, + 0x81C, 0x63540003, + 0x81C, 0x62560003, + 0x81C, 0x61580003, + 0x81C, 0x455A0003, + 0x81C, 0x445C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x25640003, + 0x81C, 0x24660003, + 0x81C, 0x23680003, + 0x81C, 0x226A0003, + 0x81C, 0x216C0003, + 0x81C, 0x016E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000103, + 0x81C, 0xFF020103, + 0x81C, 0xFF040103, + 0x81C, 0xFE060103, + 0x81C, 0xFD080103, + 0x81C, 0xFC0A0103, + 0x81C, 0xFB0C0103, + 0x81C, 0xFA0E0103, + 0x81C, 0xF9100103, + 0x81C, 0xF8120103, + 0x81C, 0xF7140103, + 0x81C, 0xF6160103, + 0x81C, 0xF5180103, + 0x81C, 0xF41A0103, + 0x81C, 0xF31C0103, + 0x81C, 0xF21E0103, + 0x81C, 0xF1200103, + 0x81C, 0xF0220103, + 0x81C, 0xEF240103, + 0x81C, 0xEE260103, + 0x81C, 0xED280103, + 0x81C, 0xEC2A0103, + 0x81C, 0xEB2C0103, + 0x81C, 0xEA2E0103, + 0x81C, 0xE9300103, + 0x81C, 0xE8320103, + 0x81C, 0xE7340103, + 0x81C, 0xE6360103, + 0x81C, 0xE5380103, + 0x81C, 0xE43A0103, + 0x81C, 0xC63C0103, + 0x81C, 0xC53E0103, + 0x81C, 0xC4400103, + 0x81C, 0xC3420103, + 0x81C, 0xC2440103, + 0x81C, 0xC1460103, + 0x81C, 0xA3480103, + 0x81C, 0xA24A0103, + 0x81C, 0xA14C0103, + 0x81C, 0x834E0103, + 0x81C, 0x82500103, + 0x81C, 0x81520103, + 0x81C, 0x64540103, + 0x81C, 0x63560103, + 0x81C, 0x62580103, + 0x81C, 0x615A0103, + 0x81C, 0x425C0103, + 0x81C, 0x415E0103, + 0x81C, 0x24600103, + 0x81C, 0x23620103, + 0x81C, 0x22640103, + 0x81C, 0x21660103, + 0x81C, 0x03680103, + 0x81C, 0x026A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0x81C, 0xFF000203, + 0x81C, 0xFF020203, + 0x81C, 0xFE040203, + 0x81C, 0xFD060203, + 0x81C, 0xFC080203, + 0x81C, 0xFB0A0203, + 0x81C, 0xFA0C0203, + 0x81C, 0xF90E0203, + 0x81C, 0xF8100203, + 0x81C, 0xF7120203, + 0x81C, 0xF6140203, + 0x81C, 0xF5160203, + 0x81C, 0xF4180203, + 0x81C, 0xF31A0203, + 0x81C, 0xF21C0203, + 0x81C, 0xF11E0203, + 0x81C, 0xF0200203, + 0x81C, 0xEF220203, + 0x81C, 0xEE240203, + 0x81C, 0xED260203, + 0x81C, 0xEC280203, + 0x81C, 0xEB2A0203, + 0x81C, 0xEA2C0203, + 0x81C, 0xE92E0203, + 0x81C, 0xE8300203, + 0x81C, 0xE7320203, + 0x81C, 0xE6340203, + 0x81C, 0xE5360203, + 0x81C, 0xE4380203, + 0x81C, 0xE33A0203, + 0x81C, 0xE23C0203, + 0x81C, 0xE13E0203, + 0x81C, 0xC4400203, + 0x81C, 0xC3420203, + 0x81C, 0xC2440203, + 0x81C, 0xC1460203, + 0x81C, 0xA3480203, + 0x81C, 0xA24A0203, + 0x81C, 0xA14C0203, + 0x81C, 0x834E0203, + 0x81C, 0x82500203, + 0x81C, 0x81520203, + 0x81C, 0x64540203, + 0x81C, 0x63560203, + 0x81C, 0x62580203, + 0x81C, 0x615A0203, + 0x81C, 0x425C0203, + 0x81C, 0x415E0203, + 0x81C, 0x22600203, + 0x81C, 0x21620203, + 0x81C, 0x04640203, + 0x81C, 0x03660203, + 0x81C, 0x02680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0x81C, 0xFF000303, + 0x81C, 0xFF020303, + 0x81C, 0xFE040303, + 0x81C, 0xFD060303, + 0x81C, 0xFC080303, + 0x81C, 0xFB0A0303, + 0x81C, 0xFA0C0303, + 0x81C, 0xF90E0303, + 0x81C, 0xF8100303, + 0x81C, 0xF7120303, + 0x81C, 0xF6140303, + 0x81C, 0xF5160303, + 0x81C, 0xF4180303, + 0x81C, 0xF31A0303, + 0x81C, 0xF21C0303, + 0x81C, 0xF11E0303, + 0x81C, 0xF0200303, + 0x81C, 0xEF220303, + 0x81C, 0xEE240303, + 0x81C, 0xED260303, + 0x81C, 0xEC280303, + 0x81C, 0xEB2A0303, + 0x81C, 0xEA2C0303, + 0x81C, 0xE92E0303, + 0x81C, 0xE8300303, + 0x81C, 0xE7320303, + 0x81C, 0xE6340303, + 0x81C, 0xE5360303, + 0x81C, 0xE4380303, + 0x81C, 0xE33A0303, + 0x81C, 0xE23C0303, + 0x81C, 0xE13E0303, + 0x81C, 0xC4400303, + 0x81C, 0xC3420303, + 0x81C, 0xC2440303, + 0x81C, 0xC1460303, + 0x81C, 0xA4480303, + 0x81C, 0xA34A0303, + 0x81C, 0xA24C0303, + 0x81C, 0xA14E0303, + 0x81C, 0x83500303, + 0x81C, 0x82520303, + 0x81C, 0x81540303, + 0x81C, 0x64560303, + 0x81C, 0x63580303, + 0x81C, 0x625A0303, + 0x81C, 0x615C0303, + 0x81C, 0x425E0303, + 0x81C, 0x41600303, + 0x81C, 0x23620303, + 0x81C, 0x22640303, + 0x81C, 0x21660303, + 0x81C, 0x03680303, + 0x81C, 0x026A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0x81C, 0xFB000403, + 0x81C, 0xFA020403, + 0x81C, 0xF9040403, + 0x81C, 0xF8060403, + 0x81C, 0xF7080403, + 0x81C, 0xF60A0403, + 0x81C, 0xF50C0403, + 0x81C, 0xF40E0403, + 0x81C, 0xF3100403, + 0x81C, 0xF2120403, + 0x81C, 0xF1140403, + 0x81C, 0xF0160403, + 0x81C, 0xEF180403, + 0x81C, 0xEE1A0403, + 0x81C, 0xED1C0403, + 0x81C, 0xB61E0403, + 0x81C, 0xB5200403, + 0x81C, 0xB4220403, + 0x81C, 0xB3240403, + 0x81C, 0xB2260403, + 0x81C, 0xB1280403, + 0x81C, 0xAF2A0403, + 0x81C, 0xAE2C0403, + 0x81C, 0xAD2E0403, + 0x81C, 0xAC300403, + 0x81C, 0xAB320403, + 0x81C, 0xAA340403, + 0x81C, 0xA9360403, + 0x81C, 0xA8380403, + 0x81C, 0xA73A0403, + 0x81C, 0xA63C0403, + 0x81C, 0xA53E0403, + 0x81C, 0x88400403, + 0x81C, 0x87420403, + 0x81C, 0x86440403, + 0x81C, 0x85460403, + 0x81C, 0x84480403, + 0x81C, 0x834A0403, + 0x81C, 0x674C0403, + 0x81C, 0x664E0403, + 0x81C, 0x65500403, + 0x81C, 0x64520403, + 0x81C, 0x63540403, + 0x81C, 0x62560403, + 0x81C, 0x61580403, + 0x81C, 0x455A0403, + 0x81C, 0x445C0403, + 0x81C, 0x435E0403, + 0x81C, 0x42600403, + 0x81C, 0x41620403, + 0x81C, 0x25640403, + 0x81C, 0x24660403, + 0x81C, 0x23680403, + 0x81C, 0x226A0403, + 0x81C, 0x216C0403, + 0x81C, 0x016E0403, + 0x81C, 0x01700403, + 0x81C, 0x01720403, + 0x81C, 0x01740403, + 0x81C, 0x01760403, + 0x81C, 0x01780403, + 0x81C, 0x017A0403, + 0x81C, 0x017C0403, + 0x81C, 0x017E0403, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + +}; + +void +ODM_ReadAndConfig_TC_8821C_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_TC_8821C_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_TC_8821C_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8821C(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_TC_8821C_AGC_TAB(void) +{ + return 9; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_TC_8821C_PHY_REG[] = { + 0x800, 0x9020D010, + 0x804, 0x80018180, + 0x808, 0x04028211, + 0x80C, 0x13D10011, + 0x810, 0x21101263, + 0x814, 0x020C3D10, + 0x818, 0x84A10385, + 0x81C, 0x1E1E081F, + 0x820, 0x0001AAAA, + 0x824, 0x00030FE0, + 0x828, 0x0000CCCC, + 0x82C, 0x75CB7010, + 0x830, 0x79A0EA2A, + 0x834, 0x072E6986, + 0x838, 0x87766461, + 0x83C, 0x9194B2B6, + 0x840, 0x171740E0, + 0x844, 0x4D3D7CDB, + 0x848, 0x4AD0408B, + 0x84C, 0x6AFBF7A5, + 0x850, 0x28A74706, + 0x854, 0x0001520C, + 0x858, 0x4060C000, + 0x85C, 0x74010360, + 0x860, 0x68A7C321, + 0x864, 0x79F27432, + 0x868, 0x8CA7A314, + 0x86C, 0x778C2878, + 0x870, 0x77777777, + 0x874, 0x27612C2E, + 0x878, 0xC0003152, + 0x87C, 0x5C8FC000, + 0x880, 0x00000000, + 0x884, 0x00000000, + 0x888, 0x00000000, + 0x88C, 0x00000000, + 0x890, 0x00000000, + 0x894, 0x00000000, + 0x898, 0x00000000, + 0x89C, 0x00000000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0x2202033E, + 0x8AC, 0xF00F000A, + 0x8B0, 0x00000600, + 0x8B4, 0x000FC080, + 0x8B8, 0xEC0057FF, + 0x8BC, 0xACB520A3, + 0x8C0, 0xFFE04020, + 0x8C4, 0x47C00000, + 0x8C8, 0x000251A5, + 0x8CC, 0x08108492, + 0x8D0, 0x0000B800, + 0x8D4, 0x860308A0, + 0x8D8, 0x290B5612, + 0x8DC, 0x00000000, + 0x8E0, 0x32D16777, + 0x8E4, 0x49092925, + 0x8E8, 0xFFFFC42C, + 0x8EC, 0x99999999, + 0x8F0, 0x00009999, + 0x8F4, 0x00D80FA1, + 0x8F8, 0x400000C0, + 0x8FC, 0x00000130, + 0x900, 0x00C00000, + 0x904, 0x0FFF0FFF, + 0x908, 0x00000000, + 0x90C, 0x13000000, + 0x910, 0x0000FC00, + 0x914, 0xC6380000, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x055A2500, + 0x928, 0x4AB0E4E4, + 0x92C, 0xFFFEB200, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x938, 0x00008480, + 0x93C, 0xE41C0642, + 0x940, 0x0E470430, + 0x944, 0x00000000, + 0x948, 0xAC000000, + 0x94C, 0x10000083, + 0x950, 0xF2010080, + 0x954, 0x86510080, + 0x958, 0x00000001, + 0x95C, 0x04248000, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x00001FFF, + 0x974, 0x04000FFF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x98C, 0x23440000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x80000088, + 0x9A8, 0x0C2F0000, + 0x9AC, 0x01560000, + 0x9B0, 0x70000000, + 0x9B4, 0x00000000, + 0x9B8, 0x00000000, + 0x9BC, 0x00000000, + 0x9C0, 0x00000000, + 0x9C4, 0x00000000, + 0x9C8, 0x00000000, + 0x9CC, 0x00000000, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E0, 0x00000000, + 0x9E4, 0x02000402, + 0x9E8, 0x000022D4, + 0x9EC, 0x00000000, + 0x9F0, 0x00000000, + 0x9F4, 0x00000000, + 0x9F8, 0x00000000, + 0x9FC, 0xEFFFF7FF, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x9C838300, + 0xA0C, 0x2E20200F, + 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0x00011335, + 0x1B80, 0x00011337, + 0x1B80, 0x7F201345, + 0x1B80, 0x7F201347, + 0x1B80, 0x7E001355, + 0x1B80, 0x7E001357, + 0x1B80, 0x7D001365, + 0x1B80, 0x7D001367, + 0x1B80, 0x55011375, + 0x1B80, 0x55011377, + 0x1B80, 0x5C311385, + 0x1B80, 0x5C311387, + 0x1B80, 0xE0FE1395, + 0x1B80, 0xE0FE1397, + 0x1B80, 0xE10213A5, + 0x1B80, 0xE10213A7, + 0x1B80, 0x548013B5, + 0x1B80, 0x548013B7, + 0x1B80, 0x540013C5, + 0x1B80, 0x540013C7, + 0x1B80, 0xE0FE13D5, + 0x1B80, 0xE0FE13D7, + 0x1B80, 0xE10213E5, + 0x1B80, 0xE10213E7, + 0x1B80, 0x548113F5, + 0x1B80, 0x548113F7, + 0x1B80, 0x54001405, + 0x1B80, 0x54001407, + 0x1B80, 0xE0FE1415, + 0x1B80, 0xE0FE1417, + 0x1B80, 0xE1021425, + 0x1B80, 0xE1021427, + 0x1B80, 0x54821435, + 0x1B80, 0x54821437, + 0x1B80, 0x54001445, + 0x1B80, 0x54001447, + 0x1B80, 0xE11F1455, + 0x1B80, 0xE11F1457, + 0x1B80, 0xBFE91465, + 0x1B80, 0xBFE91467, + 0x1B80, 0x301D1475, + 0x1B80, 0x301D1477, + 0x1B80, 0x00231485, + 0x1B80, 0x00231487, + 0x1B80, 0x7B201495, + 0x1B80, 0x7B201497, + 0x1B80, 0x7A0014A5, + 0x1B80, 0x7A0014A7, + 0x1B80, 0x790014B5, + 0x1B80, 0x790014B7, + 0x1B80, 0xE15A14C5, + 0x1B80, 0xE15A14C7, + 0x1B80, 0x000214D5, + 0x1B80, 0x000214D7, + 0x1B80, 0x000114E5, + 0x1B80, 0x000114E7, + 0x1B80, 0x002214F5, + 0x1B80, 0x002214F7, + 0x1B80, 0x7B201505, + 0x1B80, 0x7B201507, + 0x1B80, 0x7A001515, + 0x1B80, 0x7A001517, + 0x1B80, 0x79001525, + 0x1B80, 0x79001527, + 0x1B80, 0xE15A1535, + 0x1B80, 0xE15A1537, + 0x1B80, 0x00021545, + 0x1B80, 0x00021547, + 0x1B80, 0x00011555, + 0x1B80, 0x00011557, + 0x1B80, 0x549F1565, + 0x1B80, 0x549F1567, + 0x1B80, 0x54FF1575, + 0x1B80, 0x54FF1577, + 0x1B80, 0x54001585, + 0x1B80, 0x54001587, + 0x1B80, 0x00011595, + 0x1B80, 0x00011597, + 0x1B80, 0x5C3115A5, + 0x1B80, 0x5C3115A7, + 0x1B80, 0x071415B5, + 0x1B80, 0x071415B7, + 0x1B80, 0x540015C5, + 0x1B80, 0x540015C7, + 0x1B80, 0x5C3215D5, + 0x1B80, 0x5C3215D7, + 0x1B80, 0x000115E5, + 0x1B80, 0x000115E7, + 0x1B80, 0x5C3215F5, + 0x1B80, 0x5C3215F7, + 0x1B80, 0x07141605, + 0x1B80, 0x07141607, + 0x1B80, 0x54001615, + 0x1B80, 0x54001617, + 0x1B80, 0x5C311625, + 0x1B80, 0x5C311627, + 0x1B80, 0x00011635, + 0x1B80, 0x00011637, + 0x1B80, 0x4C981645, + 0x1B80, 0x4C981647, + 0x1B80, 0x4C181655, + 0x1B80, 0x4C181657, + 0x1B80, 0x00011665, + 0x1B80, 0x00011667, + 0x1B80, 0x5C321675, + 0x1B80, 0x5C321677, + 0x1B80, 0x62841685, + 0x1B80, 0x62841687, + 0x1B80, 0x66861695, + 0x1B80, 0x66861697, + 0x1B80, 0x6C0316A5, + 0x1B80, 0x6C0316A7, + 0x1B80, 0x7B2016B5, + 0x1B80, 0x7B2016B7, + 0x1B80, 0x7A0016C5, + 0x1B80, 0x7A0016C7, + 0x1B80, 0x790016D5, + 0x1B80, 0x790016D7, + 0x1B80, 0x7F2016E5, + 0x1B80, 0x7F2016E7, + 0x1B80, 0x7E0016F5, + 0x1B80, 0x7E0016F7, + 0x1B80, 0x7D001705, + 0x1B80, 0x7D001707, + 0x1B80, 0x09011715, + 0x1B80, 0x09011717, + 0x1B80, 0x0C011725, + 0x1B80, 0x0C011727, + 0x1B80, 0x0BA61735, + 0x1B80, 0x0BA61737, + 0x1B80, 0x00011745, + 0x1B80, 0x00011747, + 0x1B80, 0x00000006, + 0x1B80, 0x00000002, + +}; + +void +ODM_ReadAndConfig_TC_8821C_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_TC_8821C_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_TC_8821C_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8821C(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_TC_8821C_PHY_REG(void) +{ + return 9; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_TC_8821C_PHY_REG_PG[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 0, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040, + 0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040, + 0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832, + 0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034, + 1, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040, + 1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040, + 1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832, + 1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022 +}; + +void +ODM_ReadAndConfig_TC_8821C_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_TC_8821C_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_TC_8821C_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8821C(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.h b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.h index ef2226a5004..1107fd22c47 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_bb.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#if (RTL8821C_SUPPORT == 1) -#ifndef __INC_TC_BB_HW_IMG_8821C_H -#define __INC_TC_BB_HW_IMG_8821C_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_PHY_REG_PG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#if (RTL8821C_SUPPORT == 1) +#ifndef __INC_TC_BB_HW_IMG_8821C_H +#define __INC_TC_BB_HW_IMG_8821C_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.c b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.c index aa58a1bafec..7dd0f1bf82e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.c @@ -1,16139 +1,16139 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8821c/hal8821c_testchip_fw.h" -#endif - - -#if (RTL8821C_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_TC_8821C_FW_AP[] = { -0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x91, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x01, 0x19, 0x10, 0x3B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0x60, 0x19, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, -0x88, 0xBA, 0x00, 0x00, 0x80, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x4A, 0x03, 0x80, 0x15, 0x04, 0x03, 0x80, -0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE, -0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0x75, 0x5D, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, -0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 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(DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_TC_8821C_FW_WoWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_TC_8821C_FW_WoWLAN, ArrayLength_TC_8821C_FW_WoWLAN); -#endif - *pFirmwareSize = ArrayLength_TC_8821C_FW_WoWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8821c/hal8821c_testchip_fw.h" +#endif + + +#if (RTL8821C_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_TC_8821C_FW_AP[] = { +0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x91, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x19, 0x10, 0x3B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x60, 0x19, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 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+0x0D, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0x67, 0xA2, 0xF2, 0x14, 0x4B, 0x30, 0xF0, 0x20, 0x6A, +0xC2, 0xF2, 0x08, 0x4A, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xC9, 0x01, 0x00, 0x6A, 0x01, 0x10, +0x01, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x36, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + +}; +u4Byte ArrayLength_TC_8821C_FW_AP = 86720; + +#endif + +void +ODM_ReadFirmware_TC_8821C_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_TC_8821C_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_TC_8821C_FW_AP, ArrayLength_TC_8821C_FW_AP); +#endif + *pFirmwareSize = ArrayLength_TC_8821C_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_TC_8821C_FW_NIC[] = { +0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 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0xDA, 0x1C, 0x10, 0x06, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, +0x6C, 0xEA, 0x12, 0x22, 0x06, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x0D, 0x2A, 0x30, 0xF0, +0x20, 0x6A, 0x62, 0x67, 0x42, 0xF3, 0x10, 0x4B, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF3, 0x04, 0x4A, +0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xCB, 0x01, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A, 0x05, 0x97, +0x03, 0x63, 0x00, 0xEF, 0x81, 0x1A, 0x00, 0x00, 0xF1, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + +}; +u4Byte ArrayLength_TC_8821C_FW_NIC = 100240; + + +#endif + +void +ODM_ReadFirmware_TC_8821C_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_TC_8821C_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_TC_8821C_FW_NIC, ArrayLength_TC_8821C_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_TC_8821C_FW_NIC; +} + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_TC_8821C_FW_WoWLAN[] = { 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0x07, 0x92, 0x01, 0x6B, 0x6E, 0xEA, 0x33, 0x2A, 0x01, 0xF0, 0x08, 0x6B, +0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF3, 0x44, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18, +0x08, 0xF4, 0x21, 0xF0, 0x0C, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, +0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA1, 0xF3, 0x78, 0xDA, 0x21, 0xF0, 0x18, 0x6B, +0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0, +0x20, 0x6A, 0xA1, 0xF3, 0x7C, 0xDA, 0x21, 0xF0, 0x10, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, +0xA2, 0x67, 0x00, 0x18, 0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x60, 0xDA, +0x02, 0x10, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, +0x0D, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +u4Byte ArrayLength_TC_8821C_FW_WoWLAN = 69432; + +#endif + +void +ODM_ReadFirmware_TC_8821C_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_TC_8821C_FW_WoWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_TC_8821C_FW_WoWLAN, ArrayLength_TC_8821C_FW_WoWLAN); +#endif + *pFirmwareSize = ArrayLength_TC_8821C_FW_WoWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.h b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.h index 1ec1a9cfff2..6ba3a5c7c21 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8821C_SUPPORT == 1) -#ifndef __INC_TC_FW_HW_IMG_8821C_H -#define __INC_TC_FW_HW_IMG_8821C_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_TC_8821C_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_TC_8821C_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WoWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_TC_8821C_FW_WoWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8821C_SUPPORT == 1) +#ifndef __INC_TC_FW_HW_IMG_8821C_H +#define __INC_TC_FW_HW_IMG_8821C_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_TC_8821C_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_TC_8821C_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_TC_8821C_FW_WoWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.c b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.c index e39ee215303..0a284ff6a7a 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.c @@ -1,325 +1,325 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821C_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_TC_8821C_MAC_REG[] = { - 0x010, 0x00000043, - 0x025, 0x0000001D, - 0x026, 0x000000CE, - 0x04F, 0x00000001, - 0x420, 0x00000080, - 0x421, 0x0000000F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x000000F0, - 0x446, 0x00000001, - 0x447, 0x000000FE, - 0x448, 0x00000000, - 0x449, 0x00000000, - 0x44A, 0x00000000, - 0x44B, 0x00000040, - 0x44C, 0x00000010, - 0x44D, 0x000000F0, - 0x44E, 0x0000003F, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x00000000, - 0x452, 0x00000000, - 0x453, 0x00000040, - 0x455, 0x00000070, - 0x45E, 0x00000004, - 0x49C, 0x00000010, - 0x49D, 0x000000F0, - 0x49E, 0x00000000, - 0x49F, 0x00000006, - 0x4A0, 0x000000E0, - 0x4A1, 0x00000003, - 0x4A2, 0x00000000, - 0x4A3, 0x00000040, - 0x4A4, 0x00000015, - 0x4A5, 0x000000F0, - 0x4A6, 0x00000000, - 0x4A7, 0x00000006, - 0x4A8, 0x000000E0, - 0x4A9, 0x00000000, - 0x4AA, 0x00000000, - 0x4AB, 0x00000000, - 0x7DA, 0x00000008, - 0x1448, 0x00000006, - 0x144A, 0x00000006, - 0x144C, 0x00000006, - 0x144E, 0x00000006, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CA, 0x0000002B, - 0x4CB, 0x0000002B, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4CF, 0x00000008, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x521, 0x0000002F, - 0x525, 0x0000004F, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x577, 0x0000000B, - 0x5BE, 0x00000064, - 0x604, 0x00000001, - 0x605, 0x00000030, - 0x607, 0x00000001, - 0x608, 0x0000000E, - 0x609, 0x00000022, - 0x60C, 0x00000018, - 0x6A0, 0x000000FF, - 0x6A1, 0x000000FF, - 0x6A2, 0x000000FF, - 0x6A3, 0x000000FF, - 0x6A4, 0x000000FF, - 0x6A5, 0x000000FF, - 0x6DE, 0x00000084, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, - 0x718, 0x00000040, - 0x7D4, 0x00000010, - -}; - -void -ODM_ReadAndConfig_TC_8821C_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_TC_8821C_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_TC_8821C_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8821C(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_TC_8821C_MAC_REG(void) -{ - return 9; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821C_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_TC_8821C_MAC_REG[] = { + 0x010, 0x00000043, + 0x025, 0x0000001D, + 0x026, 0x000000CE, + 0x04F, 0x00000001, + 0x420, 0x00000080, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x000000F0, + 0x446, 0x00000001, + 0x447, 0x000000FE, + 0x448, 0x00000000, + 0x449, 0x00000000, + 0x44A, 0x00000000, + 0x44B, 0x00000040, + 0x44C, 0x00000010, + 0x44D, 0x000000F0, + 0x44E, 0x0000003F, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x00000000, + 0x452, 0x00000000, + 0x453, 0x00000040, + 0x455, 0x00000070, + 0x45E, 0x00000004, + 0x49C, 0x00000010, + 0x49D, 0x000000F0, + 0x49E, 0x00000000, + 0x49F, 0x00000006, + 0x4A0, 0x000000E0, + 0x4A1, 0x00000003, + 0x4A2, 0x00000000, + 0x4A3, 0x00000040, + 0x4A4, 0x00000015, + 0x4A5, 0x000000F0, + 0x4A6, 0x00000000, + 0x4A7, 0x00000006, + 0x4A8, 0x000000E0, + 0x4A9, 0x00000000, + 0x4AA, 0x00000000, + 0x4AB, 0x00000000, + 0x7DA, 0x00000008, + 0x1448, 0x00000006, + 0x144A, 0x00000006, + 0x144C, 0x00000006, + 0x144E, 0x00000006, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CA, 0x0000002B, + 0x4CB, 0x0000002B, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4CF, 0x00000008, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x521, 0x0000002F, + 0x525, 0x0000004F, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x577, 0x0000000B, + 0x5BE, 0x00000064, + 0x604, 0x00000001, + 0x605, 0x00000030, + 0x607, 0x00000001, + 0x608, 0x0000000E, + 0x609, 0x00000022, + 0x60C, 0x00000018, + 0x6A0, 0x000000FF, + 0x6A1, 0x000000FF, + 0x6A2, 0x000000FF, + 0x6A3, 0x000000FF, + 0x6A4, 0x000000FF, + 0x6A5, 0x000000FF, + 0x6DE, 0x00000084, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + 0x7D4, 0x00000010, + +}; + +void +ODM_ReadAndConfig_TC_8821C_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_TC_8821C_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_TC_8821C_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8821C(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_TC_8821C_MAC_REG(void) +{ + return 9; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.h b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.h index 6f91c11e377..098acf74647 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_mac.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#if (RTL8821C_SUPPORT == 1) -#ifndef __INC_TC_MAC_HW_IMG_8821C_H -#define __INC_TC_MAC_HW_IMG_8821C_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#if (RTL8821C_SUPPORT == 1) +#ifndef __INC_TC_MAC_HW_IMG_8821C_H +#define __INC_TC_MAC_HW_IMG_8821C_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.c b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.c index 51e795feecf..c7495ca3c50 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.c @@ -1,2305 +1,2305 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821C_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_TC_8821C_RadioA[] = { - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x000, 0x00030000, - 0x018, 0x00010D24, - 0xA0000000, 0x00000000, - 0x000, 0x00030000, - 0x018, 0x00010D24, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000002, - 0x03E, 0x0000003F, - 0x03F, 0x000C0F4E, - 0x033, 0x00000001, - 0x03E, 0x00000034, - 0x03F, 0x0004080E, - 0xA0000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000002, - 0x03E, 0x0000003F, - 0x03F, 0x000C0F4E, - 0x033, 0x00000001, - 0x03E, 0x00000034, - 0x03F, 0x0004080E, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000024, - 0x03E, 0x0000003F, - 0x03F, 0x000E0FDE, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000024, - 0x03E, 0x0000003F, - 0x03F, 0x000E0FDE, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000025, - 0x03E, 0x00000037, - 0x03F, 0x0007EFCE, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000025, - 0x03E, 0x00000037, - 0x03F, 0x0007EFCE, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000026, - 0x03E, 0x00000037, - 0x03F, 0x0005EFCE, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000026, - 0x03E, 0x00000037, - 0x03F, 0x0005EFCE, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x0B1, 0x0007DBE4, - 0x0B2, 0x000225D1, - 0x0B3, 0x000FC760, - 0x0B4, 0x00099DD0, - 0x0B5, 0x000400FC, - 0x0B6, 0x000187F0, - 0x0B7, 0x00030018, - 0x0B8, 0x00080800, - 0x0B9, 0x00000000, - 0x0BA, 0x00008000, - 0x0BB, 0x00000000, - 0x0BC, 0x00040000, - 0x0BD, 0x00000000, - 0x0BE, 0x00000000, - 0x0BF, 0x00000000, - 0x0C0, 0x00000000, - 0x0C1, 0x00000000, - 0x0C2, 0x00000000, - 0x0C3, 0x00000000, - 0x0C4, 0x00002402, - 0x0C5, 0x00000009, - 0x0C6, 0x00040299, - 0x0C7, 0x00055555, - 0x0C8, 0x0000C16C, - 0x0C9, 0x0001C140, - 0x0CA, 0x00000000, - 0x0CB, 0x00000000, - 0x0CC, 0x00000000, - 0x0CD, 0x00000000, - 0x0CE, 0x00090C00, - 0x0CF, 0x0006D200, - 0x0DF, 0x00000009, - 0xA0000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x0B1, 0x0007DBE4, - 0x0B2, 0x000225D1, - 0x0B3, 0x000FC760, - 0x0B4, 0x00099DD0, - 0x0B5, 0x000400FC, - 0x0B6, 0x000187F0, - 0x0B7, 0x00030018, - 0x0B8, 0x00080800, - 0x0B9, 0x00000000, - 0x0BA, 0x00008000, - 0x0BB, 0x00000000, - 0x0BC, 0x00040000, - 0x0BD, 0x00000000, - 0x0BE, 0x00000000, - 0x0BF, 0x00000000, - 0x0C0, 0x00000000, - 0x0C1, 0x00000000, - 0x0C2, 0x00000000, - 0x0C3, 0x00000000, - 0x0C4, 0x00002402, - 0x0C5, 0x00000009, - 0x0C6, 0x00040299, - 0x0C7, 0x00055555, - 0x0C8, 0x0000C16C, - 0x0C9, 0x0001C140, - 0x0CA, 0x00000000, - 0x0CB, 0x00000000, - 0x0CC, 0x00000000, - 0x0CD, 0x00000000, - 0x0CE, 0x00090C00, - 0x0CF, 0x0006D200, - 0x0DF, 0x00000009, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x018, 0x00010524, - 0x089, 0x00000207, - 0x08A, 0x000F5186, - 0x08B, 0x00061830, - 0x08C, 0x000112C7, - 0x08D, 0x00060000, - 0x08E, 0x00064540, - 0xA0000000, 0x00000000, - 0x018, 0x00010524, - 0x089, 0x00000207, - 0x08A, 0x000F5186, - 0x08B, 0x00061830, - 0x08C, 0x000112C7, - 0x08D, 0x00060000, - 0x08E, 0x00064540, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00020000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00020000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x033, 0x00000007, - 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0x033, 0x000000A5, - 0x03F, 0x00000E6C, - 0x033, 0x000000A6, - 0x03F, 0x00000EE9, - 0x033, 0x000000A7, - 0x03F, 0x00000EEC, - 0x033, 0x000000A8, - 0x03F, 0x00000EEF, - 0x033, 0x000000A9, - 0x03F, 0x00000EF2, - 0x033, 0x000000AA, - 0x03F, 0x00000EF5, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x033, 0x000000A0, - 0x03F, 0x00000E09, - 0x033, 0x000000A1, - 0x03F, 0x00000E0C, - 0x033, 0x000000A2, - 0x03F, 0x00000E0F, - 0x033, 0x000000A3, - 0x03F, 0x00000E2C, - 0x033, 0x000000A4, - 0x03F, 0x00000E2F, - 0x033, 0x000000A5, - 0x03F, 0x00000E6C, - 0x033, 0x000000A6, - 0x03F, 0x00000EE9, - 0x033, 0x000000A7, - 0x03F, 0x00000EEC, - 0x033, 0x000000A8, - 0x03F, 0x00000EEF, - 0x033, 0x000000A9, - 0x03F, 0x00000EF2, - 0x033, 0x000000AA, - 0x03F, 0x00000EF5, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, - 0x033, 0x00000000, - 0x03F, 0x0000267C, - 0x033, 0x00000001, - 0x03F, 0x0000267C, - 0x033, 0x00000002, - 0x03F, 0x0000267C, - 0x033, 0x00000003, - 0x03F, 0x0000267C, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000400, - 0x033, 0x00000000, - 0x03F, 0x0000267C, - 0x033, 0x00000001, - 0x03F, 0x0000267C, - 0x033, 0x00000002, - 0x03F, 0x0000267C, - 0x033, 0x00000003, - 0x03F, 0x0000267C, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000000, - 0x03F, 0x00000ED0, - 0x033, 0x00000001, - 0x03F, 0x00000ED0, - 0x033, 0x00000002, - 0x03F, 0x00000ED0, - 0x033, 0x00000003, - 0x03F, 0x00000ED0, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000100, - 0x033, 0x00000000, - 0x03F, 0x00000ED0, - 0x033, 0x00000001, - 0x03F, 0x00000ED0, - 0x033, 0x00000002, - 0x03F, 0x00000ED0, - 0x033, 0x00000003, - 0x03F, 0x00000ED0, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x051, 0x00000818, - 0x052, 0x0009E063, - 0x053, 0x00000DA1, - 0x054, 0x00070022, - 0x055, 0x00082000, - 0x056, 0x00051CCC, - 0x057, 0x0000CE16, - 0x058, 0x00072C10, - 0x059, 0x000A0000, - 0xA0000000, 0x00000000, - 0x051, 0x00000818, - 0x052, 0x0009E063, - 0x053, 0x00000DA1, - 0x054, 0x00070022, - 0x055, 0x00082000, - 0x056, 0x00051CCC, - 0x057, 0x0000CE16, - 0x058, 0x00072C10, - 0x059, 0x000A0000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x0DE, 0x00020200, - 0x05C, 0x00007FE0, - 0x033, 0x00000000, - 0x03F, 0x00051427, - 0x033, 0x00000001, - 0x03F, 0x00051446, - 0x033, 0x00000002, - 0x03F, 0x00051449, - 0x033, 0x00000003, - 0x03F, 0x0005144C, - 0x033, 0x00000004, - 0x03F, 0x00051C69, - 0x033, 0x00000005, - 0x03F, 0x00051C6C, - 0x033, 0x00000006, - 0x03F, 0x00051C8D, - 0x033, 0x00000007, - 0x03F, 0x00051CEB, - 0x033, 0x00000008, - 0x03F, 0x00051CEE, - 0x033, 0x00000009, - 0x03F, 0x00051CF1, - 0x033, 0x0000000A, - 0x03F, 0x00051CF4, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000800, - 0x0DE, 0x00020200, - 0x05C, 0x00007FE0, - 0x033, 0x00000000, - 0x03F, 0x00051427, - 0x033, 0x00000001, - 0x03F, 0x00051446, - 0x033, 0x00000002, - 0x03F, 0x00051449, - 0x033, 0x00000003, - 0x03F, 0x0005144C, - 0x033, 0x00000004, - 0x03F, 0x00051C69, - 0x033, 0x00000005, - 0x03F, 0x00051C6C, - 0x033, 0x00000006, - 0x03F, 0x00051C8D, - 0x033, 0x00000007, - 0x03F, 0x00051CEB, - 0x033, 0x00000008, - 0x03F, 0x00051CEE, - 0x033, 0x00000009, - 0x03F, 0x00051CF1, - 0x033, 0x0000000A, - 0x03F, 0x00051CF4, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EE, 0x00004000, - 0x033, 0x00000000, - 0x03F, 0x0000209D, - 0x033, 0x00000001, - 0x03F, 0x0000209D, - 0x033, 0x00000002, - 0x03F, 0x0000209D, - 0x033, 0x00000003, - 0x03F, 0x0000209D, - 0x0EE, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EE, 0x00004000, - 0x033, 0x00000000, - 0x03F, 0x0000209D, - 0x033, 0x00000001, - 0x03F, 0x0000209D, - 0x033, 0x00000002, - 0x03F, 0x0000209D, - 0x033, 0x00000003, - 0x03F, 0x0000209D, - 0x0EE, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EE, 0x00002000, - 0x033, 0x00000000, - 0x03F, 0x00000840, - 0x033, 0x00000001, - 0x03F, 0x00000840, - 0x033, 0x00000002, - 0x03F, 0x00000840, - 0x033, 0x00000003, - 0x03F, 0x00000840, - 0x0EE, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EE, 0x00002000, - 0x033, 0x00000000, - 0x03F, 0x00000840, - 0x033, 0x00000001, - 0x03F, 0x00000840, - 0x033, 0x00000002, - 0x03F, 0x00000840, - 0x033, 0x00000003, - 0x03F, 0x00000840, - 0x0EE, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x070, 0x00008000, - 0x075, 0x00002645, - 0x076, 0x0000E984, - 0x077, 0x00004408, - 0x078, 0x0003F000, - 0x07D, 0x00007600, - 0x07F, 0x00000000, - 0x06A, 0x000FCC00, - 0xA0000000, 0x00000000, - 0x070, 0x00008000, - 0x075, 0x00002645, - 0x076, 0x0000E984, - 0x077, 0x00004408, - 0x078, 0x0003F000, - 0x07D, 0x00007600, - 0x07F, 0x00000000, - 0x06A, 0x000FCC00, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EE, 0x00008000, - 0x033, 0x00000000, - 0x03F, 0x00051427, - 0x033, 0x00000001, - 0x03F, 0x00051446, - 0x033, 0x00000002, - 0x03F, 0x00051449, - 0x033, 0x00000003, - 0x03F, 0x0005144C, - 0x033, 0x00000004, - 0x03F, 0x00051C69, - 0x033, 0x00000005, - 0x03F, 0x00051C6C, - 0x033, 0x00000006, - 0x03F, 0x00051C8D, - 0x033, 0x00000007, - 0x03F, 0x00051CEB, - 0x033, 0x00000008, - 0x03F, 0x00051CEE, - 0x033, 0x00000009, - 0x03F, 0x00051CF1, - 0x033, 0x0000000A, - 0x03F, 0x00051CF4, - 0x0EE, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EE, 0x00008000, - 0x033, 0x00000000, - 0x03F, 0x00051427, - 0x033, 0x00000001, - 0x03F, 0x00051446, - 0x033, 0x00000002, - 0x03F, 0x00051449, - 0x033, 0x00000003, - 0x03F, 0x0005144C, - 0x033, 0x00000004, - 0x03F, 0x00051C69, - 0x033, 0x00000005, - 0x03F, 0x00051C6C, - 0x033, 0x00000006, - 0x03F, 0x00051C8D, - 0x033, 0x00000007, - 0x03F, 0x00051CEB, - 0x033, 0x00000008, - 0x03F, 0x00051CEE, - 0x033, 0x00000009, - 0x03F, 0x00051CF1, - 0x033, 0x0000000A, - 0x03F, 0x00051CF4, - 0x0EE, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000010, - 0x033, 0x00000000, - 0x008, 0x0009C060, - 0x033, 0x00000001, - 0x008, 0x0009C060, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000010, - 0x033, 0x00000000, - 0x008, 0x0009C060, - 0x033, 0x00000001, - 0x008, 0x0009C060, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x033, 0x000000A2, - 0x0EF, 0x00080000, - 0x03E, 0x0000593F, - 0x03F, 0x000C0F4F, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x033, 0x000000A2, - 0x0EF, 0x00080000, - 0x03E, 0x0000593F, - 0x03F, 0x000C0F4F, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x80002000, 0x00000000, 0x40000000, 0x00000000, - 0x033, 0x000000A3, - 0x0EF, 0x00080000, - 0x03E, 0x00005934, - 0x03F, 0x0005AFCF, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x033, 0x000000A3, - 0x0EF, 0x00080000, - 0x03E, 0x00005934, - 0x03F, 0x0005AFCF, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_TC_8821C_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_TC_8821C_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_TC_8821C_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8821C(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_TC_8821C_RadioA(void) -{ - return 9; -} - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_TC_5GA_N_TxPowerTrack_8821C[][DELTA_SWINGIDX_SIZE] = { - {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, - {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, - {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, -}; -u1Byte gDeltaSwingTableIdx_TC_5GA_P_TxPowerTrack_8821C[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, -}; -u1Byte gDeltaSwingTableIdx_TC_2GA_N_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; -u1Byte gDeltaSwingTableIdx_TC_2GA_P_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; -u1Byte gDeltaSwingTableIdx_TC_2GCCKA_N_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; -u1Byte gDeltaSwingTableIdx_TC_2GCCKA_P_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; - -void -ODM_ReadAndConfig_TC_8821C_TxPowerTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_TC_8821C\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_TC_2GA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_TC_2GA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_TC_2GCCKA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_TC_2GCCKA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_TC_5GA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_TC_5GA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_TC_8821C_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", - "MKK", "2.4G", "20M", "HT", "1T", "01", "32", - "FCC", "2.4G", "20M", "HT", "1T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", - "MKK", "2.4G", "20M", "HT", "1T", "02", "32", - "FCC", "2.4G", "20M", "HT", "1T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", - "MKK", "2.4G", "20M", "HT", "1T", "03", "32", - "FCC", "2.4G", "20M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", - "MKK", "2.4G", "20M", "HT", "1T", "04", "32", - "FCC", "2.4G", "20M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", - "MKK", "2.4G", "20M", "HT", "1T", "05", "32", - "FCC", "2.4G", "20M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", - "MKK", "2.4G", "20M", "HT", "1T", "06", "32", - "FCC", "2.4G", "20M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", - "MKK", "2.4G", "20M", "HT", "1T", "07", "32", - "FCC", "2.4G", "20M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", - "MKK", "2.4G", "20M", "HT", "1T", "08", "32", - "FCC", "2.4G", "20M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", - "MKK", "2.4G", "20M", "HT", "1T", "09", "32", - "FCC", "2.4G", "20M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", - "MKK", "2.4G", "20M", "HT", "1T", "10", "32", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", - "MKK", "2.4G", "20M", "HT", "1T", "11", "32", - "FCC", "2.4G", "20M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", - "MKK", "2.4G", "20M", "HT", "1T", "12", "32", - "FCC", "2.4G", "20M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", - "MKK", "2.4G", "20M", "HT", "1T", "13", "32", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "20M", "HT", "3T", "01", "30", - "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", - "MKK", "2.4G", "20M", "HT", "3T", "01", "28", - "FCC", "2.4G", "20M", "HT", "3T", "02", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", - "MKK", "2.4G", "20M", "HT", "3T", "02", "28", - "FCC", "2.4G", "20M", "HT", "3T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", - "MKK", "2.4G", "20M", "HT", "3T", "03", "28", - "FCC", "2.4G", "20M", "HT", "3T", "04", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", - "MKK", "2.4G", "20M", "HT", "3T", "04", "28", - "FCC", "2.4G", "20M", "HT", "3T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", - "MKK", "2.4G", "20M", "HT", "3T", "05", "28", - "FCC", "2.4G", "20M", "HT", "3T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", - "MKK", "2.4G", "20M", "HT", "3T", "06", "28", - "FCC", "2.4G", "20M", "HT", "3T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", - "MKK", "2.4G", "20M", "HT", "3T", "07", "28", - "FCC", "2.4G", "20M", "HT", "3T", "08", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", - "MKK", "2.4G", "20M", "HT", "3T", "08", "28", - "FCC", "2.4G", "20M", "HT", "3T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", - "MKK", "2.4G", "20M", "HT", "3T", "09", "28", - "FCC", "2.4G", "20M", "HT", "3T", "10", "32", - "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", - "MKK", "2.4G", "20M", "HT", "3T", "10", "28", - "FCC", "2.4G", "20M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", - "MKK", "2.4G", "20M", "HT", "3T", "11", "28", - "FCC", "2.4G", "20M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", - "MKK", "2.4G", "20M", "HT", "3T", "12", "28", - "FCC", "2.4G", "20M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", - "MKK", "2.4G", "20M", "HT", "3T", "13", "28", - "FCC", "2.4G", "20M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", - "MKK", "2.4G", "20M", "HT", "3T", "14", "63", - "FCC", "2.4G", "20M", "HT", "4T", "01", "28", - "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", - "MKK", "2.4G", "20M", "HT", "4T", "01", "26", - "FCC", "2.4G", "20M", "HT", "4T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", - "MKK", "2.4G", "20M", "HT", "4T", "02", "26", - "FCC", "2.4G", "20M", "HT", "4T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", - "MKK", "2.4G", "20M", "HT", "4T", "03", "26", - "FCC", "2.4G", "20M", "HT", "4T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", - "MKK", "2.4G", "20M", "HT", "4T", "04", "26", - "FCC", "2.4G", "20M", "HT", "4T", "05", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", - "MKK", "2.4G", "20M", "HT", "4T", "05", "26", - "FCC", "2.4G", "20M", "HT", "4T", "06", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", - "MKK", "2.4G", "20M", "HT", "4T", "06", "26", - "FCC", "2.4G", "20M", "HT", "4T", "07", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", - "MKK", "2.4G", "20M", "HT", "4T", "07", "26", - "FCC", "2.4G", "20M", "HT", "4T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", - "MKK", "2.4G", "20M", "HT", "4T", "08", "26", - "FCC", "2.4G", "20M", "HT", "4T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", - "MKK", "2.4G", "20M", "HT", "4T", "09", "26", - "FCC", "2.4G", "20M", "HT", "4T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", - "MKK", "2.4G", "20M", "HT", "4T", "10", "26", - "FCC", "2.4G", "20M", "HT", "4T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", - "MKK", "2.4G", "20M", "HT", "4T", "11", "26", - "FCC", "2.4G", "20M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", - "MKK", "2.4G", "20M", "HT", "4T", "12", "26", - "FCC", "2.4G", "20M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", - "MKK", "2.4G", "20M", "HT", "4T", "13", "26", - "FCC", "2.4G", "20M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", - "MKK", "2.4G", "20M", "HT", "4T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", - "MKK", "2.4G", "40M", "HT", "1T", "03", "32", - "FCC", "2.4G", "40M", "HT", "1T", "04", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", - "MKK", "2.4G", "40M", "HT", "1T", "04", "32", - "FCC", "2.4G", "40M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", - "MKK", "2.4G", "40M", "HT", "1T", "05", "32", - "FCC", "2.4G", "40M", "HT", "1T", "06", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", - "MKK", "2.4G", "40M", "HT", "1T", "06", "32", - "FCC", "2.4G", "40M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", - "MKK", "2.4G", "40M", "HT", "1T", "07", "32", - "FCC", "2.4G", "40M", "HT", "1T", "08", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", - "MKK", "2.4G", "40M", "HT", "1T", "08", "32", - "FCC", "2.4G", "40M", "HT", "1T", "09", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", - "MKK", "2.4G", "40M", "HT", "1T", "09", "32", - "FCC", "2.4G", "40M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", - "MKK", "2.4G", "40M", "HT", "1T", "10", "32", - "FCC", "2.4G", "40M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", - "MKK", "2.4G", "40M", "HT", "1T", "11", "32", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", - "MKK", "2.4G", "40M", "HT", "1T", "12", "32", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", - "MKK", "2.4G", "40M", "HT", "1T", "13", "32", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", - "MKK", "2.4G", "40M", "HT", "2T", "12", "30", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", - "MKK", "2.4G", "40M", "HT", "2T", "13", "30", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "3T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", - "MKK", "2.4G", "40M", "HT", "3T", "01", "63", - "FCC", "2.4G", "40M", "HT", "3T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", - "MKK", "2.4G", "40M", "HT", "3T", "02", "63", - "FCC", "2.4G", "40M", "HT", "3T", "03", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", - "MKK", "2.4G", "40M", "HT", "3T", "03", "28", - "FCC", "2.4G", "40M", "HT", "3T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", - "MKK", "2.4G", "40M", "HT", "3T", "04", "28", - "FCC", "2.4G", "40M", "HT", "3T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", - "MKK", "2.4G", "40M", "HT", "3T", "05", "28", - "FCC", "2.4G", "40M", "HT", "3T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", - "MKK", "2.4G", "40M", "HT", "3T", "06", "28", - "FCC", "2.4G", "40M", "HT", "3T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", - "MKK", "2.4G", "40M", "HT", "3T", "07", "28", - "FCC", "2.4G", "40M", "HT", "3T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", - "MKK", "2.4G", "40M", "HT", "3T", "08", "28", - "FCC", "2.4G", "40M", "HT", "3T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", - "MKK", "2.4G", "40M", "HT", "3T", "09", "28", - "FCC", "2.4G", "40M", "HT", "3T", "10", "32", - "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", - "MKK", "2.4G", "40M", "HT", "3T", "10", "28", - "FCC", "2.4G", "40M", "HT", "3T", "11", "28", - "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", - "MKK", "2.4G", "40M", "HT", "3T", "11", "28", - "FCC", "2.4G", "40M", "HT", "3T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", - "MKK", "2.4G", "40M", "HT", "3T", "12", "28", - "FCC", "2.4G", "40M", "HT", "3T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", - "MKK", "2.4G", "40M", "HT", "3T", "13", "28", - "FCC", "2.4G", "40M", "HT", "3T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", - "MKK", "2.4G", "40M", "HT", "3T", "14", "63", - "FCC", "2.4G", "40M", "HT", "4T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", - "MKK", "2.4G", "40M", "HT", "4T", "01", "63", - "FCC", "2.4G", "40M", "HT", "4T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", - "MKK", "2.4G", "40M", "HT", "4T", "02", "63", - "FCC", "2.4G", "40M", "HT", "4T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", - "MKK", "2.4G", "40M", "HT", "4T", "03", "26", - "FCC", "2.4G", "40M", "HT", "4T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", - "MKK", "2.4G", "40M", "HT", "4T", "04", "26", - "FCC", "2.4G", "40M", "HT", "4T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", - "MKK", "2.4G", "40M", "HT", "4T", "05", "26", - "FCC", "2.4G", "40M", "HT", "4T", "06", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", - "MKK", "2.4G", "40M", "HT", "4T", "06", "26", - "FCC", "2.4G", "40M", "HT", "4T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", - "MKK", "2.4G", "40M", "HT", "4T", "07", "26", - "FCC", "2.4G", "40M", "HT", "4T", "08", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", - "MKK", "2.4G", "40M", "HT", "4T", "08", "26", - "FCC", "2.4G", "40M", "HT", "4T", "09", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", - "MKK", "2.4G", "40M", "HT", "4T", "09", "26", - "FCC", "2.4G", "40M", "HT", "4T", "10", "30", - "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", - "MKK", "2.4G", "40M", "HT", "4T", "10", "26", - "FCC", "2.4G", "40M", "HT", "4T", "11", "26", - "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", - "MKK", "2.4G", "40M", "HT", "4T", "11", "26", - "FCC", "2.4G", "40M", "HT", "4T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", - "MKK", "2.4G", "40M", "HT", "4T", "12", "26", - "FCC", "2.4G", "40M", "HT", "4T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", - "MKK", "2.4G", "40M", "HT", "4T", "13", "26", - "FCC", "2.4G", "40M", "HT", "4T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", - "MKK", "2.4G", "40M", "HT", "4T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "32", - "FCC", "5G", "20M", "OFDM", "1T", "40", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "32", - "FCC", "5G", "20M", "OFDM", "1T", "44", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "32", - "FCC", "5G", "20M", "OFDM", "1T", "48", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "32", - "FCC", "5G", "20M", "OFDM", "1T", "52", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "32", - "FCC", "5G", "20M", "OFDM", "1T", "56", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "32", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "32", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "32", - "FCC", "5G", "20M", "OFDM", "1T", "100", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "149", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "32", - "FCC", "5G", "20M", "HT", "1T", "40", "30", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "32", - "FCC", "5G", "20M", "HT", "1T", "44", "30", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "32", - "FCC", "5G", "20M", "HT", "1T", "48", "30", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "32", - "FCC", "5G", "20M", "HT", "1T", "52", "36", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "32", - "FCC", "5G", "20M", "HT", "1T", "56", "34", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "32", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "32", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "32", - "FCC", "5G", "20M", "HT", "1T", "100", "30", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "30", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "34", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "34", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "36", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "34", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "30", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "30", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "28", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "149", "36", - "ETSI", "5G", "20M", "HT", "1T", "149", "32", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "36", - "ETSI", "5G", "20M", "HT", "1T", "153", "32", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "36", - "ETSI", "5G", "20M", "HT", "1T", "157", "32", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "36", - "ETSI", "5G", "20M", "HT", "1T", "161", "32", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "36", - "ETSI", "5G", "20M", "HT", "1T", "165", "32", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "30", - "MKK", "5G", "20M", "HT", "2T", "36", "30", - "FCC", "5G", "20M", "HT", "2T", "40", "28", - "ETSI", "5G", "20M", "HT", "2T", "40", "30", - "MKK", "5G", "20M", "HT", "2T", "40", "30", - "FCC", "5G", "20M", "HT", "2T", "44", "28", - "ETSI", "5G", "20M", "HT", "2T", "44", "30", - "MKK", "5G", "20M", "HT", "2T", "44", "30", - "FCC", "5G", "20M", "HT", "2T", "48", "28", - "ETSI", "5G", "20M", "HT", "2T", "48", "30", - "MKK", "5G", "20M", "HT", "2T", "48", "30", - "FCC", "5G", "20M", "HT", "2T", "52", "34", - "ETSI", "5G", "20M", "HT", "2T", "52", "30", - "MKK", "5G", "20M", "HT", "2T", "52", "30", - "FCC", "5G", "20M", "HT", "2T", "56", "32", - "ETSI", "5G", "20M", "HT", "2T", "56", "30", - "MKK", "5G", "20M", "HT", "2T", "56", "30", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "30", - "MKK", "5G", "20M", "HT", "2T", "60", "30", - "FCC", "5G", "20M", "HT", "2T", "64", "26", - "ETSI", "5G", "20M", "HT", "2T", "64", "30", - "MKK", "5G", "20M", "HT", "2T", "64", "30", - "FCC", "5G", "20M", "HT", "2T", "100", "28", - "ETSI", "5G", "20M", "HT", "2T", "100", "30", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "28", - "ETSI", "5G", "20M", "HT", "2T", "104", "30", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "30", - "ETSI", "5G", "20M", "HT", "2T", "108", "30", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "30", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "30", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "34", - "ETSI", "5G", "20M", "HT", "2T", "120", "30", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "30", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "30", - "ETSI", "5G", "20M", "HT", "2T", "128", "30", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "28", - "ETSI", "5G", "20M", "HT", "2T", "132", "30", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "28", - "ETSI", "5G", "20M", "HT", "2T", "136", "30", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "30", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "149", "34", - "ETSI", "5G", "20M", "HT", "2T", "149", "30", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "34", - "ETSI", "5G", "20M", "HT", "2T", "153", "30", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "34", - "ETSI", "5G", "20M", "HT", "2T", "157", "30", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "34", - "ETSI", "5G", "20M", "HT", "2T", "161", "30", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "34", - "ETSI", "5G", "20M", "HT", "2T", "165", "30", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "20M", "HT", "3T", "36", "26", - "ETSI", "5G", "20M", "HT", "3T", "36", "28", - "MKK", "5G", "20M", "HT", "3T", "36", "28", - "FCC", "5G", "20M", "HT", "3T", "40", "26", - "ETSI", "5G", "20M", "HT", "3T", "40", "28", - "MKK", "5G", "20M", "HT", "3T", "40", "28", - "FCC", "5G", "20M", "HT", "3T", "44", "26", - "ETSI", "5G", "20M", "HT", "3T", "44", "28", - "MKK", "5G", "20M", "HT", "3T", "44", "28", - "FCC", "5G", "20M", "HT", "3T", "48", "26", - "ETSI", "5G", "20M", "HT", "3T", "48", "28", - "MKK", "5G", "20M", "HT", "3T", "48", "28", - "FCC", "5G", "20M", "HT", "3T", "52", "32", - "ETSI", "5G", "20M", "HT", "3T", "52", "28", - "MKK", "5G", "20M", "HT", "3T", "52", "28", - "FCC", "5G", "20M", "HT", "3T", "56", "30", - "ETSI", "5G", "20M", "HT", "3T", "56", "28", - "MKK", "5G", "20M", "HT", "3T", "56", "28", - "FCC", "5G", "20M", "HT", "3T", "60", "28", - "ETSI", "5G", "20M", "HT", "3T", "60", "28", - "MKK", "5G", "20M", "HT", "3T", "60", "28", - "FCC", "5G", "20M", "HT", "3T", "64", "24", - "ETSI", "5G", "20M", "HT", "3T", "64", "28", - "MKK", "5G", "20M", "HT", "3T", "64", "28", - "FCC", "5G", "20M", "HT", "3T", "100", "26", - "ETSI", "5G", "20M", "HT", "3T", "100", "28", - "MKK", "5G", "20M", "HT", "3T", "100", "28", - "FCC", "5G", "20M", "HT", "3T", "104", "26", - "ETSI", "5G", "20M", "HT", "3T", "104", "28", - "MKK", "5G", "20M", "HT", "3T", "104", "28", - "FCC", "5G", "20M", "HT", "3T", "108", "28", - "ETSI", "5G", "20M", "HT", "3T", "108", "28", - "MKK", "5G", "20M", "HT", "3T", "108", "28", - "FCC", "5G", "20M", "HT", "3T", "112", "30", - "ETSI", "5G", "20M", "HT", "3T", "112", "28", - "MKK", "5G", "20M", "HT", "3T", "112", "28", - "FCC", "5G", "20M", "HT", "3T", "116", "30", - "ETSI", "5G", "20M", "HT", "3T", "116", "28", - "MKK", "5G", "20M", "HT", "3T", "116", "28", - "FCC", "5G", "20M", "HT", "3T", "120", "32", - "ETSI", "5G", "20M", "HT", "3T", "120", "28", - "MKK", "5G", "20M", "HT", "3T", "120", "28", - "FCC", "5G", "20M", "HT", "3T", "124", "30", - "ETSI", "5G", "20M", "HT", "3T", "124", "28", - "MKK", "5G", "20M", "HT", "3T", "124", "28", - "FCC", "5G", "20M", "HT", "3T", "128", "28", - "ETSI", "5G", "20M", "HT", "3T", "128", "28", - "MKK", "5G", "20M", "HT", "3T", "128", "28", - "FCC", "5G", "20M", "HT", "3T", "132", "26", - "ETSI", "5G", "20M", "HT", "3T", "132", "28", - "MKK", "5G", "20M", "HT", "3T", "132", "28", - "FCC", "5G", "20M", "HT", "3T", "136", "26", - "ETSI", "5G", "20M", "HT", "3T", "136", "28", - "MKK", "5G", "20M", "HT", "3T", "136", "28", - "FCC", "5G", "20M", "HT", "3T", "140", "24", - "ETSI", "5G", "20M", "HT", "3T", "140", "28", - "MKK", "5G", "20M", "HT", "3T", "140", "28", - "FCC", "5G", "20M", "HT", "3T", "149", "32", - "ETSI", "5G", "20M", "HT", "3T", "149", "28", - "MKK", "5G", "20M", "HT", "3T", "149", "63", - "FCC", "5G", "20M", "HT", "3T", "153", "32", - "ETSI", "5G", "20M", "HT", "3T", "153", "28", - "MKK", "5G", "20M", "HT", "3T", "153", "63", - "FCC", "5G", "20M", "HT", "3T", "157", "32", - "ETSI", "5G", "20M", "HT", "3T", "157", "28", - "MKK", "5G", "20M", "HT", "3T", "157", "63", - "FCC", "5G", "20M", "HT", "3T", "161", "32", - "ETSI", "5G", "20M", "HT", "3T", "161", "28", - "MKK", "5G", "20M", "HT", "3T", "161", "63", - "FCC", "5G", "20M", "HT", "3T", "165", "32", - "ETSI", "5G", "20M", "HT", "3T", "165", "28", - "MKK", "5G", "20M", "HT", "3T", "165", "63", - "FCC", "5G", "20M", "HT", "4T", "36", "24", - "ETSI", "5G", "20M", "HT", "4T", "36", "26", - "MKK", "5G", "20M", "HT", "4T", "36", "26", - "FCC", "5G", "20M", "HT", "4T", "40", "24", - "ETSI", "5G", "20M", "HT", "4T", "40", "26", - "MKK", "5G", "20M", "HT", "4T", "40", "26", - "FCC", "5G", "20M", "HT", "4T", "44", "24", - "ETSI", "5G", "20M", "HT", "4T", "44", "26", - "MKK", "5G", "20M", "HT", "4T", "44", "26", - "FCC", "5G", "20M", "HT", "4T", "48", "24", - "ETSI", "5G", "20M", "HT", "4T", "48", "26", - "MKK", "5G", "20M", "HT", "4T", "48", "26", - "FCC", "5G", "20M", "HT", "4T", "52", "30", - "ETSI", "5G", "20M", "HT", "4T", "52", "26", - "MKK", "5G", "20M", "HT", "4T", "52", "26", - "FCC", "5G", "20M", "HT", "4T", "56", "28", - "ETSI", "5G", "20M", "HT", "4T", "56", "26", - "MKK", "5G", "20M", "HT", "4T", "56", "26", - "FCC", "5G", "20M", "HT", "4T", "60", "26", - "ETSI", "5G", "20M", "HT", "4T", "60", "26", - "MKK", "5G", "20M", "HT", "4T", "60", "26", - "FCC", "5G", "20M", "HT", "4T", "64", "22", - "ETSI", "5G", "20M", "HT", "4T", "64", "26", - "MKK", "5G", "20M", "HT", "4T", "64", "26", - "FCC", "5G", "20M", "HT", "4T", "100", "24", - "ETSI", "5G", "20M", "HT", "4T", "100", "26", - "MKK", "5G", "20M", "HT", "4T", "100", "26", - "FCC", "5G", "20M", "HT", "4T", "104", "24", - "ETSI", "5G", "20M", "HT", "4T", "104", "26", - "MKK", "5G", "20M", "HT", "4T", "104", "26", - "FCC", "5G", "20M", "HT", "4T", "108", "26", - "ETSI", "5G", "20M", "HT", "4T", "108", "26", - "MKK", "5G", "20M", "HT", "4T", "108", "26", - "FCC", "5G", "20M", "HT", "4T", "112", "28", - "ETSI", "5G", "20M", "HT", "4T", "112", "26", - "MKK", "5G", "20M", "HT", "4T", "112", "26", - "FCC", "5G", "20M", "HT", "4T", "116", "28", - "ETSI", "5G", "20M", "HT", "4T", "116", "26", - "MKK", "5G", "20M", "HT", "4T", "116", "26", - "FCC", "5G", "20M", "HT", "4T", "120", "30", - "ETSI", "5G", "20M", "HT", "4T", "120", "26", - "MKK", "5G", "20M", "HT", "4T", "120", "26", - "FCC", "5G", "20M", "HT", "4T", "124", "28", - "ETSI", "5G", "20M", "HT", "4T", "124", "26", - "MKK", "5G", "20M", "HT", "4T", "124", "26", - "FCC", "5G", "20M", "HT", "4T", "128", "26", - "ETSI", "5G", "20M", "HT", "4T", "128", "26", - "MKK", "5G", "20M", "HT", "4T", "128", "26", - "FCC", "5G", "20M", "HT", "4T", "132", "24", - "ETSI", "5G", "20M", "HT", "4T", "132", "26", - "MKK", "5G", "20M", "HT", "4T", "132", "26", - "FCC", "5G", "20M", "HT", "4T", "136", "24", - "ETSI", "5G", "20M", "HT", "4T", "136", "26", - "MKK", "5G", "20M", "HT", "4T", "136", "26", - "FCC", "5G", "20M", "HT", "4T", "140", "22", - "ETSI", "5G", "20M", "HT", "4T", "140", "26", - "MKK", "5G", "20M", "HT", "4T", "140", "26", - "FCC", "5G", "20M", "HT", "4T", "149", "30", - "ETSI", "5G", "20M", "HT", "4T", "149", "26", - "MKK", "5G", "20M", "HT", "4T", "149", "63", - "FCC", "5G", "20M", "HT", "4T", "153", "30", - "ETSI", "5G", "20M", "HT", "4T", "153", "26", - "MKK", "5G", "20M", "HT", "4T", "153", "63", - "FCC", "5G", "20M", "HT", "4T", "157", "30", - "ETSI", "5G", "20M", "HT", "4T", "157", "26", - "MKK", "5G", "20M", "HT", "4T", "157", "63", - "FCC", "5G", "20M", "HT", "4T", "161", "30", - "ETSI", "5G", "20M", "HT", "4T", "161", "26", - "MKK", "5G", "20M", "HT", "4T", "161", "63", - "FCC", "5G", "20M", "HT", "4T", "165", "30", - "ETSI", "5G", "20M", "HT", "4T", "165", "26", - "MKK", "5G", "20M", "HT", "4T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "30", - "ETSI", "5G", "40M", "HT", "1T", "38", "32", - "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "32", - "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", - "ETSI", "5G", "40M", "HT", "1T", "54", "32", - "MKK", "5G", "40M", "HT", "1T", "54", "32", - "FCC", "5G", "40M", "HT", "1T", "62", "32", - "ETSI", "5G", "40M", "HT", "1T", "62", "32", - "MKK", "5G", "40M", "HT", "1T", "62", "32", - "FCC", "5G", "40M", "HT", "1T", "102", "28", - "ETSI", "5G", "40M", "HT", "1T", "102", "32", - "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", - "ETSI", "5G", "40M", "HT", "1T", "110", "32", - "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "32", - "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "34", - "ETSI", "5G", "40M", "HT", "1T", "126", "32", - "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", - "ETSI", "5G", "40M", "HT", "1T", "134", "32", - "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "32", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "32", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "28", - "ETSI", "5G", "40M", "HT", "2T", "38", "30", - "MKK", "5G", "40M", "HT", "2T", "38", "30", - "FCC", "5G", "40M", "HT", "2T", "46", "28", - "ETSI", "5G", "40M", "HT", "2T", "46", "30", - "MKK", "5G", "40M", "HT", "2T", "46", "30", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "30", - "MKK", "5G", "40M", "HT", "2T", "54", "30", - "FCC", "5G", "40M", "HT", "2T", "62", "30", - "ETSI", "5G", "40M", "HT", "2T", "62", "30", - "MKK", "5G", "40M", "HT", "2T", "62", "30", - "FCC", "5G", "40M", "HT", "2T", "102", "26", - "ETSI", "5G", "40M", "HT", "2T", "102", "30", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "30", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "34", - "ETSI", "5G", "40M", "HT", "2T", "118", "30", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "32", - "ETSI", "5G", "40M", "HT", "2T", "126", "30", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "30", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "151", "34", - "ETSI", "5G", "40M", "HT", "2T", "151", "30", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "34", - "ETSI", "5G", "40M", "HT", "2T", "159", "30", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "40M", "HT", "3T", "38", "26", - "ETSI", "5G", "40M", "HT", "3T", "38", "28", - "MKK", "5G", "40M", "HT", "3T", "38", "28", - "FCC", "5G", "40M", "HT", "3T", "46", "26", - "ETSI", "5G", "40M", "HT", "3T", "46", "28", - "MKK", "5G", "40M", "HT", "3T", "46", "28", - "FCC", "5G", "40M", "HT", "3T", "54", "28", - "ETSI", "5G", "40M", "HT", "3T", "54", "28", - "MKK", "5G", "40M", "HT", "3T", "54", "28", - "FCC", "5G", "40M", "HT", "3T", "62", "28", - "ETSI", "5G", "40M", "HT", "3T", "62", "28", - "MKK", "5G", "40M", "HT", "3T", "62", "28", - "FCC", "5G", "40M", "HT", "3T", "102", "24", - "ETSI", "5G", "40M", "HT", "3T", "102", "28", - "MKK", "5G", "40M", "HT", "3T", "102", "28", - "FCC", "5G", "40M", "HT", "3T", "110", "28", - "ETSI", "5G", "40M", "HT", "3T", "110", "28", - "MKK", "5G", "40M", "HT", "3T", "110", "28", - "FCC", "5G", "40M", "HT", "3T", "118", "32", - "ETSI", "5G", "40M", "HT", "3T", "118", "28", - "MKK", "5G", "40M", "HT", "3T", "118", "28", - "FCC", "5G", "40M", "HT", "3T", "126", "30", - "ETSI", "5G", "40M", "HT", "3T", "126", "28", - "MKK", "5G", "40M", "HT", "3T", "126", "28", - "FCC", "5G", "40M", "HT", "3T", "134", "28", - "ETSI", "5G", "40M", "HT", "3T", "134", "28", - "MKK", "5G", "40M", "HT", "3T", "134", "28", - "FCC", "5G", "40M", "HT", "3T", "151", "32", - "ETSI", "5G", "40M", "HT", "3T", "151", "28", - "MKK", "5G", "40M", "HT", "3T", "151", "63", - "FCC", "5G", "40M", "HT", "3T", "159", "32", - "ETSI", "5G", "40M", "HT", "3T", "159", "28", - "MKK", "5G", "40M", "HT", "3T", "159", "63", - "FCC", "5G", "40M", "HT", "4T", "38", "24", - "ETSI", "5G", "40M", "HT", "4T", "38", "26", - "MKK", "5G", "40M", "HT", "4T", "38", "26", - "FCC", "5G", "40M", "HT", "4T", "46", "24", - "ETSI", "5G", "40M", "HT", "4T", "46", "26", - "MKK", "5G", "40M", "HT", "4T", "46", "26", - "FCC", "5G", "40M", "HT", "4T", "54", "26", - "ETSI", "5G", "40M", "HT", "4T", "54", "26", - "MKK", "5G", "40M", "HT", "4T", "54", "26", - "FCC", "5G", "40M", "HT", "4T", "62", "26", - "ETSI", "5G", "40M", "HT", "4T", "62", "26", - "MKK", "5G", "40M", "HT", "4T", "62", "26", - "FCC", "5G", "40M", "HT", "4T", "102", "22", - "ETSI", "5G", "40M", "HT", "4T", "102", "26", - "MKK", "5G", "40M", "HT", "4T", "102", "26", - "FCC", "5G", "40M", "HT", "4T", "110", "26", - "ETSI", "5G", "40M", "HT", "4T", "110", "26", - "MKK", "5G", "40M", "HT", "4T", "110", "26", - "FCC", "5G", "40M", "HT", "4T", "118", "30", - "ETSI", "5G", "40M", "HT", "4T", "118", "26", - "MKK", "5G", "40M", "HT", "4T", "118", "26", - "FCC", "5G", "40M", "HT", "4T", "126", "28", - "ETSI", "5G", "40M", "HT", "4T", "126", "26", - "MKK", "5G", "40M", "HT", "4T", "126", "26", - "FCC", "5G", "40M", "HT", "4T", "134", "26", - "ETSI", "5G", "40M", "HT", "4T", "134", "26", - "MKK", "5G", "40M", "HT", "4T", "134", "26", - "FCC", "5G", "40M", "HT", "4T", "151", "30", - "ETSI", "5G", "40M", "HT", "4T", "151", "26", - "MKK", "5G", "40M", "HT", "4T", "151", "63", - "FCC", "5G", "40M", "HT", "4T", "159", "30", - "ETSI", "5G", "40M", "HT", "4T", "159", "26", - "MKK", "5G", "40M", "HT", "4T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "30", - "ETSI", "5G", "80M", "VHT", "1T", "42", "32", - "MKK", "5G", "80M", "VHT", "1T", "42", "32", - "FCC", "5G", "80M", "VHT", "1T", "58", "28", - "ETSI", "5G", "80M", "VHT", "1T", "58", "32", - "MKK", "5G", "80M", "VHT", "1T", "58", "32", - "FCC", "5G", "80M", "VHT", "1T", "106", "30", - "ETSI", "5G", "80M", "VHT", "1T", "106", "32", - "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "34", - "ETSI", "5G", "80M", "VHT", "1T", "122", "32", - "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "32", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "28", - "ETSI", "5G", "80M", "VHT", "2T", "42", "30", - "MKK", "5G", "80M", "VHT", "2T", "42", "30", - "FCC", "5G", "80M", "VHT", "2T", "58", "26", - "ETSI", "5G", "80M", "VHT", "2T", "58", "30", - "MKK", "5G", "80M", "VHT", "2T", "58", "30", - "FCC", "5G", "80M", "VHT", "2T", "106", "28", - "ETSI", "5G", "80M", "VHT", "2T", "106", "30", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "32", - "ETSI", "5G", "80M", "VHT", "2T", "122", "30", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "155", "34", - "ETSI", "5G", "80M", "VHT", "2T", "155", "30", - "MKK", "5G", "80M", "VHT", "2T", "155", "63", - "FCC", "5G", "80M", "VHT", "3T", "42", "26", - "ETSI", "5G", "80M", "VHT", "3T", "42", "28", - "MKK", "5G", "80M", "VHT", "3T", "42", "28", - "FCC", "5G", "80M", "VHT", "3T", "58", "24", - "ETSI", "5G", "80M", "VHT", "3T", "58", "28", - "MKK", "5G", "80M", "VHT", "3T", "58", "28", - "FCC", "5G", "80M", "VHT", "3T", "106", "26", - "ETSI", "5G", "80M", "VHT", "3T", "106", "28", - "MKK", "5G", "80M", "VHT", "3T", "106", "28", - "FCC", "5G", "80M", "VHT", "3T", "122", "30", - "ETSI", "5G", "80M", "VHT", "3T", "122", "28", - "MKK", "5G", "80M", "VHT", "3T", "122", "28", - "FCC", "5G", "80M", "VHT", "3T", "155", "32", - "ETSI", "5G", "80M", "VHT", "3T", "155", "28", - "MKK", "5G", "80M", "VHT", "3T", "155", "63", - "FCC", "5G", "80M", "VHT", "4T", "42", "24", - "ETSI", "5G", "80M", "VHT", "4T", "42", "26", - "MKK", "5G", "80M", "VHT", "4T", "42", "26", - "FCC", "5G", "80M", "VHT", "4T", "58", "22", - "ETSI", "5G", "80M", "VHT", "4T", "58", "26", - "MKK", "5G", "80M", "VHT", "4T", "58", "26", - "FCC", "5G", "80M", "VHT", "4T", "106", "24", - "ETSI", "5G", "80M", "VHT", "4T", "106", "26", - "MKK", "5G", "80M", "VHT", "4T", "106", "26", - "FCC", "5G", "80M", "VHT", "4T", "122", "28", - "ETSI", "5G", "80M", "VHT", "4T", "122", "26", - "MKK", "5G", "80M", "VHT", "4T", "122", "26", - "FCC", "5G", "80M", "VHT", "4T", "155", "30", - "ETSI", "5G", "80M", "VHT", "4T", "155", "26", - "MKK", "5G", "80M", "VHT", "4T", "155", "63" -}; - -void -ODM_ReadAndConfig_TC_8821C_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_TC_8821C_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_TC_8821C_TXPWR_LMT; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; - - odm_ConfigBB_TXPWR_LMT_8821C(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821C_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_TC_8821C_RadioA[] = { + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x000, 0x00030000, + 0x018, 0x00010D24, + 0xA0000000, 0x00000000, + 0x000, 0x00030000, + 0x018, 0x00010D24, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x000E0FDE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x000E0FDE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000000, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0xA0000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000000, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010524, + 0x089, 0x00000207, + 0x08A, 0x000F5186, + 0x08B, 0x00061830, + 0x08C, 0x000112C7, + 0x08D, 0x00060000, + 0x08E, 0x00064540, + 0xA0000000, 0x00000000, + 0x018, 0x00010524, + 0x089, 0x00000207, + 0x08A, 0x000F5186, + 0x08B, 0x00061830, + 0x08C, 0x000112C7, + 0x08D, 0x00060000, + 0x08E, 0x00064540, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00020000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000007, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x00000006, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x00000003, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x033, 0x00000007, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x00000006, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x00000003, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000017, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000011, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000010, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x033, 0x00000017, + 0x03E, 0x0003C000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x03E, 0x0003C080, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x03E, 0x0003C0C8, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x03E, 0x0003C190, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x03E, 0x0003C998, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x03E, 0x0003D840, + 0x03F, 0x000C3186, + 0x033, 0x00000011, + 0x03E, 0x0003D8C4, + 0x03F, 0x000C3186, + 0x033, 0x00000010, + 0x03E, 0x0003D930, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00000005, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00000005, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00040020, + 0x0DF, 0x00008009, + 0xA0000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00040020, + 0x0DF, 0x00008009, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x03F, 0x00000006, + 0x033, 0x0000000E, + 0x03F, 0x00000006, + 0x033, 0x0000000C, + 0x03F, 0x00000006, + 0x033, 0x0000000A, + 0x03F, 0x00000006, + 0x033, 0x00000008, + 0x03F, 0x00000006, + 0x033, 0x00000036, + 0x03F, 0x00000006, + 0x033, 0x00000037, + 0x03F, 0x00000006, + 0x033, 0x00000034, + 0x03F, 0x00000006, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, + 0x033, 0x00000006, + 0x03F, 0x00000006, + 0x033, 0x00000007, + 0x03F, 0x00000006, + 0x033, 0x00000004, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000006, + 0x033, 0x00000000, + 0x03F, 0x00000006, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x03F, 0x00000006, + 0x033, 0x0000000E, + 0x03F, 0x00000006, + 0x033, 0x0000000C, + 0x03F, 0x00000006, + 0x033, 0x0000000A, + 0x03F, 0x00000006, + 0x033, 0x00000008, + 0x03F, 0x00000006, + 0x033, 0x00000036, + 0x03F, 0x00000006, + 0x033, 0x00000037, + 0x03F, 0x00000006, + 0x033, 0x00000034, + 0x03F, 0x00000006, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, + 0x033, 0x00000006, + 0x03F, 0x00000006, + 0x033, 0x00000007, + 0x03F, 0x00000006, + 0x033, 0x00000004, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000006, + 0x033, 0x00000000, + 0x03F, 0x00000006, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9DBD, + 0x0AF, 0x00070000, + 0xA0000000, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9DBD, + 0x0AF, 0x00070000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, + 0x0B0, 0x000FF0F8, + 0xA0000000, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, + 0x0B0, 0x000FF0F8, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00018D24, + 0xA0000000, 0x00000000, + 0x018, 0x00018D24, + 0xB0000000, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010D24, + 0xA0000000, 0x00000000, + 0x018, 0x00010D24, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00003A40, + 0xA0000000, 0x00000000, + 0x01B, 0x00003A40, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0xA0000000, 0x00000000, + 0x061, 0x0004D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000004F1, + 0x030, 0x000014F1, + 0x030, 0x000024F1, + 0x030, 0x000034F1, + 0x030, 0x000044F1, + 0x030, 0x000054F1, + 0x030, 0x000064F1, + 0x030, 0x000074F1, + 0x030, 0x000084F1, + 0x030, 0x000094F1, + 0x030, 0x0000A4F1, + 0x030, 0x0000B4F1, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000491, + 0x030, 0x00001491, + 0x030, 0x00002491, + 0x030, 0x00003491, + 0x030, 0x00004492, + 0x030, 0x00005492, + 0x030, 0x00006492, + 0x030, 0x00007492, + 0x030, 0x00008592, + 0x030, 0x00009592, + 0x030, 0x0000A592, + 0x030, 0x0000B592, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000301, + 0x030, 0x00001301, + 0x030, 0x00002301, + 0x030, 0x00003301, + 0x030, 0x00004301, + 0x030, 0x00005301, + 0x030, 0x00006301, + 0x030, 0x00007301, + 0x030, 0x00008301, + 0x030, 0x00009301, + 0x030, 0x0000A301, + 0x030, 0x0000B301, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000401, + 0x030, 0x00001401, + 0x030, 0x00002401, + 0x030, 0x00003401, + 0x030, 0x00004403, + 0x030, 0x00005403, + 0x030, 0x00006403, + 0x030, 0x00007403, + 0x030, 0x00008402, + 0x030, 0x00009402, + 0x030, 0x0000A402, + 0x030, 0x0000B402, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000770, + 0x030, 0x00001670, + 0x030, 0x00002120, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000773, + 0x030, 0x00001543, + 0x030, 0x00002330, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, + 0x0DE, 0x00020200, + 0x05C, 0x00007FE0, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000800, + 0x0DE, 0x00020200, + 0x05C, 0x00007FE0, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000E08, + 0x033, 0x00000021, + 0x03F, 0x00000E0B, + 0x033, 0x00000022, + 0x03F, 0x00000E0E, + 0x033, 0x00000023, + 0x03F, 0x00000E2B, + 0x033, 0x00000024, + 0x03F, 0x00000E2E, + 0x033, 0x00000025, + 0x03F, 0x00000E6B, + 0x033, 0x00000026, + 0x03F, 0x00000EE9, + 0x033, 0x00000027, + 0x03F, 0x00000EEC, + 0x033, 0x00000028, + 0x03F, 0x00000EEF, + 0x033, 0x00000029, + 0x03F, 0x00000EF2, + 0x033, 0x0000002A, + 0x03F, 0x00000EF5, + 0xA0000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000E08, + 0x033, 0x00000021, + 0x03F, 0x00000E0B, + 0x033, 0x00000022, + 0x03F, 0x00000E0E, + 0x033, 0x00000023, + 0x03F, 0x00000E2B, + 0x033, 0x00000024, + 0x03F, 0x00000E2E, + 0x033, 0x00000025, + 0x03F, 0x00000E6B, + 0x033, 0x00000026, + 0x03F, 0x00000EE8, + 0x033, 0x00000027, + 0x03F, 0x00000EEB, + 0x033, 0x00000028, + 0x03F, 0x00000EEE, + 0x033, 0x00000029, + 0x03F, 0x00000EF1, + 0x033, 0x0000002A, + 0x03F, 0x00000EF4, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000E09, + 0x033, 0x00000061, + 0x03F, 0x00000E0C, + 0x033, 0x00000062, + 0x03F, 0x00000E0F, + 0x033, 0x00000063, + 0x03F, 0x00000E2C, + 0x033, 0x00000064, + 0x03F, 0x00000E2F, + 0x033, 0x00000065, + 0x03F, 0x00000E6B, + 0x033, 0x00000066, + 0x03F, 0x00000EE6, + 0x033, 0x00000067, + 0x03F, 0x00000EE9, + 0x033, 0x00000068, + 0x03F, 0x00000EEC, + 0x033, 0x00000069, + 0x03F, 0x00000EF0, + 0x033, 0x0000006A, + 0x03F, 0x00000EF3, + 0xA0000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000E08, + 0x033, 0x00000061, + 0x03F, 0x00000E0B, + 0x033, 0x00000062, + 0x03F, 0x00000E0E, + 0x033, 0x00000063, + 0x03F, 0x00000E2B, + 0x033, 0x00000064, + 0x03F, 0x00000E2E, + 0x033, 0x00000065, + 0x03F, 0x00000E6B, + 0x033, 0x00000066, + 0x03F, 0x00000EE7, + 0x033, 0x00000067, + 0x03F, 0x00000EEA, + 0x033, 0x00000068, + 0x03F, 0x00000EED, + 0x033, 0x00000069, + 0x03F, 0x00000EF0, + 0x033, 0x0000006A, + 0x03F, 0x00000EF3, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000E09, + 0x033, 0x000000A1, + 0x03F, 0x00000E0C, + 0x033, 0x000000A2, + 0x03F, 0x00000E0F, + 0x033, 0x000000A3, + 0x03F, 0x00000E2C, + 0x033, 0x000000A4, + 0x03F, 0x00000E2F, + 0x033, 0x000000A5, + 0x03F, 0x00000E6C, + 0x033, 0x000000A6, + 0x03F, 0x00000EE9, + 0x033, 0x000000A7, + 0x03F, 0x00000EEC, + 0x033, 0x000000A8, + 0x03F, 0x00000EEF, + 0x033, 0x000000A9, + 0x03F, 0x00000EF2, + 0x033, 0x000000AA, + 0x03F, 0x00000EF5, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000E09, + 0x033, 0x000000A1, + 0x03F, 0x00000E0C, + 0x033, 0x000000A2, + 0x03F, 0x00000E0F, + 0x033, 0x000000A3, + 0x03F, 0x00000E2C, + 0x033, 0x000000A4, + 0x03F, 0x00000E2F, + 0x033, 0x000000A5, + 0x03F, 0x00000E6C, + 0x033, 0x000000A6, + 0x03F, 0x00000EE9, + 0x033, 0x000000A7, + 0x03F, 0x00000EEC, + 0x033, 0x000000A8, + 0x03F, 0x00000EEF, + 0x033, 0x000000A9, + 0x03F, 0x00000EF2, + 0x033, 0x000000AA, + 0x03F, 0x00000EF5, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x0000267C, + 0x033, 0x00000001, + 0x03F, 0x0000267C, + 0x033, 0x00000002, + 0x03F, 0x0000267C, + 0x033, 0x00000003, + 0x03F, 0x0000267C, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x0000267C, + 0x033, 0x00000001, + 0x03F, 0x0000267C, + 0x033, 0x00000002, + 0x03F, 0x0000267C, + 0x033, 0x00000003, + 0x03F, 0x0000267C, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000ED0, + 0x033, 0x00000001, + 0x03F, 0x00000ED0, + 0x033, 0x00000002, + 0x03F, 0x00000ED0, + 0x033, 0x00000003, + 0x03F, 0x00000ED0, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000ED0, + 0x033, 0x00000001, + 0x03F, 0x00000ED0, + 0x033, 0x00000002, + 0x03F, 0x00000ED0, + 0x033, 0x00000003, + 0x03F, 0x00000ED0, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x00000818, + 0x052, 0x0009E063, + 0x053, 0x00000DA1, + 0x054, 0x00070022, + 0x055, 0x00082000, + 0x056, 0x00051CCC, + 0x057, 0x0000CE16, + 0x058, 0x00072C10, + 0x059, 0x000A0000, + 0xA0000000, 0x00000000, + 0x051, 0x00000818, + 0x052, 0x0009E063, + 0x053, 0x00000DA1, + 0x054, 0x00070022, + 0x055, 0x00082000, + 0x056, 0x00051CCC, + 0x057, 0x0000CE16, + 0x058, 0x00072C10, + 0x059, 0x000A0000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, + 0x0DE, 0x00020200, + 0x05C, 0x00007FE0, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000800, + 0x0DE, 0x00020200, + 0x05C, 0x00007FE0, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000209D, + 0x033, 0x00000001, + 0x03F, 0x0000209D, + 0x033, 0x00000002, + 0x03F, 0x0000209D, + 0x033, 0x00000003, + 0x03F, 0x0000209D, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000209D, + 0x033, 0x00000001, + 0x03F, 0x0000209D, + 0x033, 0x00000002, + 0x03F, 0x0000209D, + 0x033, 0x00000003, + 0x03F, 0x0000209D, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000840, + 0x033, 0x00000001, + 0x03F, 0x00000840, + 0x033, 0x00000002, + 0x03F, 0x00000840, + 0x033, 0x00000003, + 0x03F, 0x00000840, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000840, + 0x033, 0x00000001, + 0x03F, 0x00000840, + 0x033, 0x00000002, + 0x03F, 0x00000840, + 0x033, 0x00000003, + 0x03F, 0x00000840, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x00002645, + 0x076, 0x0000E984, + 0x077, 0x00004408, + 0x078, 0x0003F000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000FCC00, + 0xA0000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x00002645, + 0x076, 0x0000E984, + 0x077, 0x00004408, + 0x078, 0x0003F000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000FCC00, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A2, + 0x0EF, 0x00080000, + 0x03E, 0x0000593F, + 0x03F, 0x000C0F4F, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x033, 0x000000A2, + 0x0EF, 0x00080000, + 0x03E, 0x0000593F, + 0x03F, 0x000C0F4F, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80002000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A3, + 0x0EF, 0x00080000, + 0x03E, 0x00005934, + 0x03F, 0x0005AFCF, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x033, 0x000000A3, + 0x0EF, 0x00080000, + 0x03E, 0x00005934, + 0x03F, 0x0005AFCF, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_TC_8821C_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_TC_8821C_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_TC_8821C_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8821C(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_TC_8821C_RadioA(void) +{ + return 9; +} + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_TC_5GA_N_TxPowerTrack_8821C[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14}, + {0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21}, + {0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19}, +}; +u1Byte gDeltaSwingTableIdx_TC_5GA_P_TxPowerTrack_8821C[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25}, +}; +u1Byte gDeltaSwingTableIdx_TC_2GA_N_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13}; +u1Byte gDeltaSwingTableIdx_TC_2GA_P_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14}; +u1Byte gDeltaSwingTableIdx_TC_2GCCKA_N_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12}; +u1Byte gDeltaSwingTableIdx_TC_2GCCKA_P_TxPowerTrack_8821C[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14}; + +void +ODM_ReadAndConfig_TC_8821C_TxPowerTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_TC_8821C\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_TC_2GA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_TC_2GA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_TC_2GCCKA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_TC_2GCCKA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_TC_5GA_P_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_TC_5GA_N_TxPowerTrack_8821C, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_TC_8821C_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "36", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "32", + "MKK", "2.4G", "20M", "HT", "1T", "01", "32", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "32", + "MKK", "2.4G", "20M", "HT", "1T", "02", "32", + "FCC", "2.4G", "20M", "HT", "1T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "32", + "MKK", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "32", + "MKK", "2.4G", "20M", "HT", "1T", "04", "32", + "FCC", "2.4G", "20M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "32", + "MKK", "2.4G", "20M", "HT", "1T", "05", "32", + "FCC", "2.4G", "20M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "32", + "MKK", "2.4G", "20M", "HT", "1T", "06", "32", + "FCC", "2.4G", "20M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "32", + "MKK", "2.4G", "20M", "HT", "1T", "07", "32", + "FCC", "2.4G", "20M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "32", + "MKK", "2.4G", "20M", "HT", "1T", "08", "32", + "FCC", "2.4G", "20M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "32", + "MKK", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "32", + "MKK", "2.4G", "20M", "HT", "1T", "10", "32", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "32", + "MKK", "2.4G", "20M", "HT", "1T", "11", "32", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "32", + "MKK", "2.4G", "20M", "HT", "1T", "12", "32", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "32", + "MKK", "2.4G", "20M", "HT", "1T", "13", "32", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "20M", "HT", "3T", "01", "30", + "ETSI", "2.4G", "20M", "HT", "3T", "01", "28", + "MKK", "2.4G", "20M", "HT", "3T", "01", "28", + "FCC", "2.4G", "20M", "HT", "3T", "02", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "02", "28", + "MKK", "2.4G", "20M", "HT", "3T", "02", "28", + "FCC", "2.4G", "20M", "HT", "3T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "03", "28", + "MKK", "2.4G", "20M", "HT", "3T", "03", "28", + "FCC", "2.4G", "20M", "HT", "3T", "04", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "04", "28", + "MKK", "2.4G", "20M", "HT", "3T", "04", "28", + "FCC", "2.4G", "20M", "HT", "3T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "05", "28", + "MKK", "2.4G", "20M", "HT", "3T", "05", "28", + "FCC", "2.4G", "20M", "HT", "3T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "06", "28", + "MKK", "2.4G", "20M", "HT", "3T", "06", "28", + "FCC", "2.4G", "20M", "HT", "3T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "07", "28", + "MKK", "2.4G", "20M", "HT", "3T", "07", "28", + "FCC", "2.4G", "20M", "HT", "3T", "08", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "08", "28", + "MKK", "2.4G", "20M", "HT", "3T", "08", "28", + "FCC", "2.4G", "20M", "HT", "3T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "09", "28", + "MKK", "2.4G", "20M", "HT", "3T", "09", "28", + "FCC", "2.4G", "20M", "HT", "3T", "10", "32", + "ETSI", "2.4G", "20M", "HT", "3T", "10", "28", + "MKK", "2.4G", "20M", "HT", "3T", "10", "28", + "FCC", "2.4G", "20M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "3T", "11", "28", + "MKK", "2.4G", "20M", "HT", "3T", "11", "28", + "FCC", "2.4G", "20M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "12", "28", + "MKK", "2.4G", "20M", "HT", "3T", "12", "28", + "FCC", "2.4G", "20M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "13", "28", + "MKK", "2.4G", "20M", "HT", "3T", "13", "28", + "FCC", "2.4G", "20M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "3T", "14", "63", + "MKK", "2.4G", "20M", "HT", "3T", "14", "63", + "FCC", "2.4G", "20M", "HT", "4T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "4T", "01", "26", + "MKK", "2.4G", "20M", "HT", "4T", "01", "26", + "FCC", "2.4G", "20M", "HT", "4T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "02", "26", + "MKK", "2.4G", "20M", "HT", "4T", "02", "26", + "FCC", "2.4G", "20M", "HT", "4T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "03", "26", + "MKK", "2.4G", "20M", "HT", "4T", "03", "26", + "FCC", "2.4G", "20M", "HT", "4T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "04", "26", + "MKK", "2.4G", "20M", "HT", "4T", "04", "26", + "FCC", "2.4G", "20M", "HT", "4T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "05", "26", + "MKK", "2.4G", "20M", "HT", "4T", "05", "26", + "FCC", "2.4G", "20M", "HT", "4T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "06", "26", + "MKK", "2.4G", "20M", "HT", "4T", "06", "26", + "FCC", "2.4G", "20M", "HT", "4T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "07", "26", + "MKK", "2.4G", "20M", "HT", "4T", "07", "26", + "FCC", "2.4G", "20M", "HT", "4T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "08", "26", + "MKK", "2.4G", "20M", "HT", "4T", "08", "26", + "FCC", "2.4G", "20M", "HT", "4T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "09", "26", + "MKK", "2.4G", "20M", "HT", "4T", "09", "26", + "FCC", "2.4G", "20M", "HT", "4T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "4T", "10", "26", + "MKK", "2.4G", "20M", "HT", "4T", "10", "26", + "FCC", "2.4G", "20M", "HT", "4T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "4T", "11", "26", + "MKK", "2.4G", "20M", "HT", "4T", "11", "26", + "FCC", "2.4G", "20M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "12", "26", + "MKK", "2.4G", "20M", "HT", "4T", "12", "26", + "FCC", "2.4G", "20M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "13", "26", + "MKK", "2.4G", "20M", "HT", "4T", "13", "26", + "FCC", "2.4G", "20M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "4T", "14", "63", + "MKK", "2.4G", "20M", "HT", "4T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "32", + "MKK", "2.4G", "40M", "HT", "1T", "03", "32", + "FCC", "2.4G", "40M", "HT", "1T", "04", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "32", + "MKK", "2.4G", "40M", "HT", "1T", "04", "32", + "FCC", "2.4G", "40M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "32", + "MKK", "2.4G", "40M", "HT", "1T", "05", "32", + "FCC", "2.4G", "40M", "HT", "1T", "06", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "32", + "MKK", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "32", + "MKK", "2.4G", "40M", "HT", "1T", "07", "32", + "FCC", "2.4G", "40M", "HT", "1T", "08", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "32", + "MKK", "2.4G", "40M", "HT", "1T", "08", "32", + "FCC", "2.4G", "40M", "HT", "1T", "09", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "32", + "MKK", "2.4G", "40M", "HT", "1T", "09", "32", + "FCC", "2.4G", "40M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "32", + "MKK", "2.4G", "40M", "HT", "1T", "10", "32", + "FCC", "2.4G", "40M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "32", + "MKK", "2.4G", "40M", "HT", "1T", "11", "32", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "32", + "MKK", "2.4G", "40M", "HT", "1T", "12", "32", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "32", + "MKK", "2.4G", "40M", "HT", "1T", "13", "32", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "30", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "30", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "30", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "30", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "30", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "30", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "30", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "30", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "30", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "30", + "MKK", "2.4G", "40M", "HT", "2T", "12", "30", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "30", + "MKK", "2.4G", "40M", "HT", "2T", "13", "30", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "3T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "01", "63", + "MKK", "2.4G", "40M", "HT", "3T", "01", "63", + "FCC", "2.4G", "40M", "HT", "3T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "02", "63", + "MKK", "2.4G", "40M", "HT", "3T", "02", "63", + "FCC", "2.4G", "40M", "HT", "3T", "03", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "03", "28", + "MKK", "2.4G", "40M", "HT", "3T", "03", "28", + "FCC", "2.4G", "40M", "HT", "3T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "04", "28", + "MKK", "2.4G", "40M", "HT", "3T", "04", "28", + "FCC", "2.4G", "40M", "HT", "3T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "05", "28", + "MKK", "2.4G", "40M", "HT", "3T", "05", "28", + "FCC", "2.4G", "40M", "HT", "3T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "06", "28", + "MKK", "2.4G", "40M", "HT", "3T", "06", "28", + "FCC", "2.4G", "40M", "HT", "3T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "07", "28", + "MKK", "2.4G", "40M", "HT", "3T", "07", "28", + "FCC", "2.4G", "40M", "HT", "3T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "08", "28", + "MKK", "2.4G", "40M", "HT", "3T", "08", "28", + "FCC", "2.4G", "40M", "HT", "3T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "09", "28", + "MKK", "2.4G", "40M", "HT", "3T", "09", "28", + "FCC", "2.4G", "40M", "HT", "3T", "10", "32", + "ETSI", "2.4G", "40M", "HT", "3T", "10", "28", + "MKK", "2.4G", "40M", "HT", "3T", "10", "28", + "FCC", "2.4G", "40M", "HT", "3T", "11", "28", + "ETSI", "2.4G", "40M", "HT", "3T", "11", "28", + "MKK", "2.4G", "40M", "HT", "3T", "11", "28", + "FCC", "2.4G", "40M", "HT", "3T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "12", "28", + "MKK", "2.4G", "40M", "HT", "3T", "12", "28", + "FCC", "2.4G", "40M", "HT", "3T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "13", "28", + "MKK", "2.4G", "40M", "HT", "3T", "13", "28", + "FCC", "2.4G", "40M", "HT", "3T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "3T", "14", "63", + "MKK", "2.4G", "40M", "HT", "3T", "14", "63", + "FCC", "2.4G", "40M", "HT", "4T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "01", "63", + "MKK", "2.4G", "40M", "HT", "4T", "01", "63", + "FCC", "2.4G", "40M", "HT", "4T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "02", "63", + "MKK", "2.4G", "40M", "HT", "4T", "02", "63", + "FCC", "2.4G", "40M", "HT", "4T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "03", "26", + "MKK", "2.4G", "40M", "HT", "4T", "03", "26", + "FCC", "2.4G", "40M", "HT", "4T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "04", "26", + "MKK", "2.4G", "40M", "HT", "4T", "04", "26", + "FCC", "2.4G", "40M", "HT", "4T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "05", "26", + "MKK", "2.4G", "40M", "HT", "4T", "05", "26", + "FCC", "2.4G", "40M", "HT", "4T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "06", "26", + "MKK", "2.4G", "40M", "HT", "4T", "06", "26", + "FCC", "2.4G", "40M", "HT", "4T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "07", "26", + "MKK", "2.4G", "40M", "HT", "4T", "07", "26", + "FCC", "2.4G", "40M", "HT", "4T", "08", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "08", "26", + "MKK", "2.4G", "40M", "HT", "4T", "08", "26", + "FCC", "2.4G", "40M", "HT", "4T", "09", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "09", "26", + "MKK", "2.4G", "40M", "HT", "4T", "09", "26", + "FCC", "2.4G", "40M", "HT", "4T", "10", "30", + "ETSI", "2.4G", "40M", "HT", "4T", "10", "26", + "MKK", "2.4G", "40M", "HT", "4T", "10", "26", + "FCC", "2.4G", "40M", "HT", "4T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "4T", "11", "26", + "MKK", "2.4G", "40M", "HT", "4T", "11", "26", + "FCC", "2.4G", "40M", "HT", "4T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "12", "26", + "MKK", "2.4G", "40M", "HT", "4T", "12", "26", + "FCC", "2.4G", "40M", "HT", "4T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "13", "26", + "MKK", "2.4G", "40M", "HT", "4T", "13", "26", + "FCC", "2.4G", "40M", "HT", "4T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "4T", "14", "63", + "MKK", "2.4G", "40M", "HT", "4T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "36", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "30", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "36", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "36", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "36", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "36", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "36", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "36", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "30", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "20M", "HT", "3T", "36", "26", + "ETSI", "5G", "20M", "HT", "3T", "36", "28", + "MKK", "5G", "20M", "HT", "3T", "36", "28", + "FCC", "5G", "20M", "HT", "3T", "40", "26", + "ETSI", "5G", "20M", "HT", "3T", "40", "28", + "MKK", "5G", "20M", "HT", "3T", "40", "28", + "FCC", "5G", "20M", "HT", "3T", "44", "26", + "ETSI", "5G", "20M", "HT", "3T", "44", "28", + "MKK", "5G", "20M", "HT", "3T", "44", "28", + "FCC", "5G", "20M", "HT", "3T", "48", "26", + "ETSI", "5G", "20M", "HT", "3T", "48", "28", + "MKK", "5G", "20M", "HT", "3T", "48", "28", + "FCC", "5G", "20M", "HT", "3T", "52", "32", + "ETSI", "5G", "20M", "HT", "3T", "52", "28", + "MKK", "5G", "20M", "HT", "3T", "52", "28", + "FCC", "5G", "20M", "HT", "3T", "56", "30", + "ETSI", "5G", "20M", "HT", "3T", "56", "28", + "MKK", "5G", "20M", "HT", "3T", "56", "28", + "FCC", "5G", "20M", "HT", "3T", "60", "28", + "ETSI", "5G", "20M", "HT", "3T", "60", "28", + "MKK", "5G", "20M", "HT", "3T", "60", "28", + "FCC", "5G", "20M", "HT", "3T", "64", "24", + "ETSI", "5G", "20M", "HT", "3T", "64", "28", + "MKK", "5G", "20M", "HT", "3T", "64", "28", + "FCC", "5G", "20M", "HT", "3T", "100", "26", + "ETSI", "5G", "20M", "HT", "3T", "100", "28", + "MKK", "5G", "20M", "HT", "3T", "100", "28", + "FCC", "5G", "20M", "HT", "3T", "104", "26", + "ETSI", "5G", "20M", "HT", "3T", "104", "28", + "MKK", "5G", "20M", "HT", "3T", "104", "28", + "FCC", "5G", "20M", "HT", "3T", "108", "28", + "ETSI", "5G", "20M", "HT", "3T", "108", "28", + "MKK", "5G", "20M", "HT", "3T", "108", "28", + "FCC", "5G", "20M", "HT", "3T", "112", "30", + "ETSI", "5G", "20M", "HT", "3T", "112", "28", + "MKK", "5G", "20M", "HT", "3T", "112", "28", + "FCC", "5G", "20M", "HT", "3T", "116", "30", + "ETSI", "5G", "20M", "HT", "3T", "116", "28", + "MKK", "5G", "20M", "HT", "3T", "116", "28", + "FCC", "5G", "20M", "HT", "3T", "120", "32", + "ETSI", "5G", "20M", "HT", "3T", "120", "28", + "MKK", "5G", "20M", "HT", "3T", "120", "28", + "FCC", "5G", "20M", "HT", "3T", "124", "30", + "ETSI", "5G", "20M", "HT", "3T", "124", "28", + "MKK", "5G", "20M", "HT", "3T", "124", "28", + "FCC", "5G", "20M", "HT", "3T", "128", "28", + "ETSI", "5G", "20M", "HT", "3T", "128", "28", + "MKK", "5G", "20M", "HT", "3T", "128", "28", + "FCC", "5G", "20M", "HT", "3T", "132", "26", + "ETSI", "5G", "20M", "HT", "3T", "132", "28", + "MKK", "5G", "20M", "HT", "3T", "132", "28", + "FCC", "5G", "20M", "HT", "3T", "136", "26", + "ETSI", "5G", "20M", "HT", "3T", "136", "28", + "MKK", "5G", "20M", "HT", "3T", "136", "28", + "FCC", "5G", "20M", "HT", "3T", "140", "24", + "ETSI", "5G", "20M", "HT", "3T", "140", "28", + "MKK", "5G", "20M", "HT", "3T", "140", "28", + "FCC", "5G", "20M", "HT", "3T", "149", "32", + "ETSI", "5G", "20M", "HT", "3T", "149", "28", + "MKK", "5G", "20M", "HT", "3T", "149", "63", + "FCC", "5G", "20M", "HT", "3T", "153", "32", + "ETSI", "5G", "20M", "HT", "3T", "153", "28", + "MKK", "5G", "20M", "HT", "3T", "153", "63", + "FCC", "5G", "20M", "HT", "3T", "157", "32", + "ETSI", "5G", "20M", "HT", "3T", "157", "28", + "MKK", "5G", "20M", "HT", "3T", "157", "63", + "FCC", "5G", "20M", "HT", "3T", "161", "32", + "ETSI", "5G", "20M", "HT", "3T", "161", "28", + "MKK", "5G", "20M", "HT", "3T", "161", "63", + "FCC", "5G", "20M", "HT", "3T", "165", "32", + "ETSI", "5G", "20M", "HT", "3T", "165", "28", + "MKK", "5G", "20M", "HT", "3T", "165", "63", + "FCC", "5G", "20M", "HT", "4T", "36", "24", + "ETSI", "5G", "20M", "HT", "4T", "36", "26", + "MKK", "5G", "20M", "HT", "4T", "36", "26", + "FCC", "5G", "20M", "HT", "4T", "40", "24", + "ETSI", "5G", "20M", "HT", "4T", "40", "26", + "MKK", "5G", "20M", "HT", "4T", "40", "26", + "FCC", "5G", "20M", "HT", "4T", "44", "24", + "ETSI", "5G", "20M", "HT", "4T", "44", "26", + "MKK", "5G", "20M", "HT", "4T", "44", "26", + "FCC", "5G", "20M", "HT", "4T", "48", "24", + "ETSI", "5G", "20M", "HT", "4T", "48", "26", + "MKK", "5G", "20M", "HT", "4T", "48", "26", + "FCC", "5G", "20M", "HT", "4T", "52", "30", + "ETSI", "5G", "20M", "HT", "4T", "52", "26", + "MKK", "5G", "20M", "HT", "4T", "52", "26", + "FCC", "5G", "20M", "HT", "4T", "56", "28", + "ETSI", "5G", "20M", "HT", "4T", "56", "26", + "MKK", "5G", "20M", "HT", "4T", "56", "26", + "FCC", "5G", "20M", "HT", "4T", "60", "26", + "ETSI", "5G", "20M", "HT", "4T", "60", "26", + "MKK", "5G", "20M", "HT", "4T", "60", "26", + "FCC", "5G", "20M", "HT", "4T", "64", "22", + "ETSI", "5G", "20M", "HT", "4T", "64", "26", + "MKK", "5G", "20M", "HT", "4T", "64", "26", + "FCC", "5G", "20M", "HT", "4T", "100", "24", + "ETSI", "5G", "20M", "HT", "4T", "100", "26", + "MKK", "5G", "20M", "HT", "4T", "100", "26", + "FCC", "5G", "20M", "HT", "4T", "104", "24", + "ETSI", "5G", "20M", "HT", "4T", "104", "26", + "MKK", "5G", "20M", "HT", "4T", "104", "26", + "FCC", "5G", "20M", "HT", "4T", "108", "26", + "ETSI", "5G", "20M", "HT", "4T", "108", "26", + "MKK", "5G", "20M", "HT", "4T", "108", "26", + "FCC", "5G", "20M", "HT", "4T", "112", "28", + "ETSI", "5G", "20M", "HT", "4T", "112", "26", + "MKK", "5G", "20M", "HT", "4T", "112", "26", + "FCC", "5G", "20M", "HT", "4T", "116", "28", + "ETSI", "5G", "20M", "HT", "4T", "116", "26", + "MKK", "5G", "20M", "HT", "4T", "116", "26", + "FCC", "5G", "20M", "HT", "4T", "120", "30", + "ETSI", "5G", "20M", "HT", "4T", "120", "26", + "MKK", "5G", "20M", "HT", "4T", "120", "26", + "FCC", "5G", "20M", "HT", "4T", "124", "28", + "ETSI", "5G", "20M", "HT", "4T", "124", "26", + "MKK", "5G", "20M", "HT", "4T", "124", "26", + "FCC", "5G", "20M", "HT", "4T", "128", "26", + "ETSI", "5G", "20M", "HT", "4T", "128", "26", + "MKK", "5G", "20M", "HT", "4T", "128", "26", + "FCC", "5G", "20M", "HT", "4T", "132", "24", + "ETSI", "5G", "20M", "HT", "4T", "132", "26", + "MKK", "5G", "20M", "HT", "4T", "132", "26", + "FCC", "5G", "20M", "HT", "4T", "136", "24", + "ETSI", "5G", "20M", "HT", "4T", "136", "26", + "MKK", "5G", "20M", "HT", "4T", "136", "26", + "FCC", "5G", "20M", "HT", "4T", "140", "22", + "ETSI", "5G", "20M", "HT", "4T", "140", "26", + "MKK", "5G", "20M", "HT", "4T", "140", "26", + "FCC", "5G", "20M", "HT", "4T", "149", "30", + "ETSI", "5G", "20M", "HT", "4T", "149", "26", + "MKK", "5G", "20M", "HT", "4T", "149", "63", + "FCC", "5G", "20M", "HT", "4T", "153", "30", + "ETSI", "5G", "20M", "HT", "4T", "153", "26", + "MKK", "5G", "20M", "HT", "4T", "153", "63", + "FCC", "5G", "20M", "HT", "4T", "157", "30", + "ETSI", "5G", "20M", "HT", "4T", "157", "26", + "MKK", "5G", "20M", "HT", "4T", "157", "63", + "FCC", "5G", "20M", "HT", "4T", "161", "30", + "ETSI", "5G", "20M", "HT", "4T", "161", "26", + "MKK", "5G", "20M", "HT", "4T", "161", "63", + "FCC", "5G", "20M", "HT", "4T", "165", "30", + "ETSI", "5G", "20M", "HT", "4T", "165", "26", + "MKK", "5G", "20M", "HT", "4T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "40M", "HT", "3T", "38", "26", + "ETSI", "5G", "40M", "HT", "3T", "38", "28", + "MKK", "5G", "40M", "HT", "3T", "38", "28", + "FCC", "5G", "40M", "HT", "3T", "46", "26", + "ETSI", "5G", "40M", "HT", "3T", "46", "28", + "MKK", "5G", "40M", "HT", "3T", "46", "28", + "FCC", "5G", "40M", "HT", "3T", "54", "28", + "ETSI", "5G", "40M", "HT", "3T", "54", "28", + "MKK", "5G", "40M", "HT", "3T", "54", "28", + "FCC", "5G", "40M", "HT", "3T", "62", "28", + "ETSI", "5G", "40M", "HT", "3T", "62", "28", + "MKK", "5G", "40M", "HT", "3T", "62", "28", + "FCC", "5G", "40M", "HT", "3T", "102", "24", + "ETSI", "5G", "40M", "HT", "3T", "102", "28", + "MKK", "5G", "40M", "HT", "3T", "102", "28", + "FCC", "5G", "40M", "HT", "3T", "110", "28", + "ETSI", "5G", "40M", "HT", "3T", "110", "28", + "MKK", "5G", "40M", "HT", "3T", "110", "28", + "FCC", "5G", "40M", "HT", "3T", "118", "32", + "ETSI", "5G", "40M", "HT", "3T", "118", "28", + "MKK", "5G", "40M", "HT", "3T", "118", "28", + "FCC", "5G", "40M", "HT", "3T", "126", "30", + "ETSI", "5G", "40M", "HT", "3T", "126", "28", + "MKK", "5G", "40M", "HT", "3T", "126", "28", + "FCC", "5G", "40M", "HT", "3T", "134", "28", + "ETSI", "5G", "40M", "HT", "3T", "134", "28", + "MKK", "5G", "40M", "HT", "3T", "134", "28", + "FCC", "5G", "40M", "HT", "3T", "151", "32", + "ETSI", "5G", "40M", "HT", "3T", "151", "28", + "MKK", "5G", "40M", "HT", "3T", "151", "63", + "FCC", "5G", "40M", "HT", "3T", "159", "32", + "ETSI", "5G", "40M", "HT", "3T", "159", "28", + "MKK", "5G", "40M", "HT", "3T", "159", "63", + "FCC", "5G", "40M", "HT", "4T", "38", "24", + "ETSI", "5G", "40M", "HT", "4T", "38", "26", + "MKK", "5G", "40M", "HT", "4T", "38", "26", + "FCC", "5G", "40M", "HT", "4T", "46", "24", + "ETSI", "5G", "40M", "HT", "4T", "46", "26", + "MKK", "5G", "40M", "HT", "4T", "46", "26", + "FCC", "5G", "40M", "HT", "4T", "54", "26", + "ETSI", "5G", "40M", "HT", "4T", "54", "26", + "MKK", "5G", "40M", "HT", "4T", "54", "26", + "FCC", "5G", "40M", "HT", "4T", "62", "26", + "ETSI", "5G", "40M", "HT", "4T", "62", "26", + "MKK", "5G", "40M", "HT", "4T", "62", "26", + "FCC", "5G", "40M", "HT", "4T", "102", "22", + "ETSI", "5G", "40M", "HT", "4T", "102", "26", + "MKK", "5G", "40M", "HT", "4T", "102", "26", + "FCC", "5G", "40M", "HT", "4T", "110", "26", + "ETSI", "5G", "40M", "HT", "4T", "110", "26", + "MKK", "5G", "40M", "HT", "4T", "110", "26", + "FCC", "5G", "40M", "HT", "4T", "118", "30", + "ETSI", "5G", "40M", "HT", "4T", "118", "26", + "MKK", "5G", "40M", "HT", "4T", "118", "26", + "FCC", "5G", "40M", "HT", "4T", "126", "28", + "ETSI", "5G", "40M", "HT", "4T", "126", "26", + "MKK", "5G", "40M", "HT", "4T", "126", "26", + "FCC", "5G", "40M", "HT", "4T", "134", "26", + "ETSI", "5G", "40M", "HT", "4T", "134", "26", + "MKK", "5G", "40M", "HT", "4T", "134", "26", + "FCC", "5G", "40M", "HT", "4T", "151", "30", + "ETSI", "5G", "40M", "HT", "4T", "151", "26", + "MKK", "5G", "40M", "HT", "4T", "151", "63", + "FCC", "5G", "40M", "HT", "4T", "159", "30", + "ETSI", "5G", "40M", "HT", "4T", "159", "26", + "MKK", "5G", "40M", "HT", "4T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "FCC", "5G", "80M", "VHT", "3T", "42", "26", + "ETSI", "5G", "80M", "VHT", "3T", "42", "28", + "MKK", "5G", "80M", "VHT", "3T", "42", "28", + "FCC", "5G", "80M", "VHT", "3T", "58", "24", + "ETSI", "5G", "80M", "VHT", "3T", "58", "28", + "MKK", "5G", "80M", "VHT", "3T", "58", "28", + "FCC", "5G", "80M", "VHT", "3T", "106", "26", + "ETSI", "5G", "80M", "VHT", "3T", "106", "28", + "MKK", "5G", "80M", "VHT", "3T", "106", "28", + "FCC", "5G", "80M", "VHT", "3T", "122", "30", + "ETSI", "5G", "80M", "VHT", "3T", "122", "28", + "MKK", "5G", "80M", "VHT", "3T", "122", "28", + "FCC", "5G", "80M", "VHT", "3T", "155", "32", + "ETSI", "5G", "80M", "VHT", "3T", "155", "28", + "MKK", "5G", "80M", "VHT", "3T", "155", "63", + "FCC", "5G", "80M", "VHT", "4T", "42", "24", + "ETSI", "5G", "80M", "VHT", "4T", "42", "26", + "MKK", "5G", "80M", "VHT", "4T", "42", "26", + "FCC", "5G", "80M", "VHT", "4T", "58", "22", + "ETSI", "5G", "80M", "VHT", "4T", "58", "26", + "MKK", "5G", "80M", "VHT", "4T", "58", "26", + "FCC", "5G", "80M", "VHT", "4T", "106", "24", + "ETSI", "5G", "80M", "VHT", "4T", "106", "26", + "MKK", "5G", "80M", "VHT", "4T", "106", "26", + "FCC", "5G", "80M", "VHT", "4T", "122", "28", + "ETSI", "5G", "80M", "VHT", "4T", "122", "26", + "MKK", "5G", "80M", "VHT", "4T", "122", "26", + "FCC", "5G", "80M", "VHT", "4T", "155", "30", + "ETSI", "5G", "80M", "VHT", "4T", "155", "26", + "MKK", "5G", "80M", "VHT", "4T", "155", "63" +}; + +void +ODM_ReadAndConfig_TC_8821C_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_TC_8821C_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_TC_8821C_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_TC_8821C_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8821C(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.h b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.h index dc3dd392e4c..f43e6efe85c 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/halhwimg8821c_testchip_rf.h @@ -1,59 +1,59 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ -#if (RTL8821C_SUPPORT == 1) -#ifndef __INC_TC_RF_HW_IMG_8821C_H -#define __INC_TC_RF_HW_IMG_8821C_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_RadioA(void); - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_TxPowerTrack(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_TC_8821C_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_TC_8821C_TXPWR_LMT(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.22*/ +#if (RTL8821C_SUPPORT == 1) +#ifndef __INC_TC_RF_HW_IMG_8821C_H +#define __INC_TC_RF_HW_IMG_8821C_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_RadioA(void); + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_TxPowerTrack(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_TC_8821C_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_TC_8821C_TXPWR_LMT(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.c b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.c index 29591f03a87..8427d03f7a1 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.c @@ -1,958 +1,958 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821C_SUPPORT == 1) - -/* ======================================================================== */ -/* These following functions can be used for PHY DM only*/ - -u4Byte reg82c_8821c; -u4Byte reg838_8821c; -u4Byte reg830_8821c; -ODM_BW_E bw_8821c; -u1Byte central_ch_8821c; - - -BOOLEAN -phydm_rfe_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte channel - ) -{ -#if 0 - /* Efuse is not wrote now */ - /* Need to check RFE type finally */ - /*if (pDM_Odm->RFEType == 1) {*/ - if (channel <= 14) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); - } else if (channel > 35) { - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); - } else - return FALSE; - - /* chip top mux */ - ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0); - ODM_SetBBReg(pDM_Odm, 0x40, BIT2, 0x1); - - /* from s0 or s1 */ - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30); - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3); - - /* input or output */ - ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f); - ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3); - - /* delay 400ns for PAPE */ - ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); - - /* antenna switch table */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555); - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); - /*}*/ -#endif - return TRUE; -} - -VOID -phydm_ccapar_8821c( - IN PDM_ODM_T pDM_Odm - ) -{ -#if 0 - u4Byte cca_ifem[9][4] = { - /*20M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/ - /*40M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/ - {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/ - /*80M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x87746641, 0x00000000, 0x87746641} }; /*Reg838*/ - - u4Byte cca_efem[9][4] = { - /*20M*/ - {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ - /*40M*/ - {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ - /*80M*/ - {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431} }; /*Reg838*/ - - u1Byte row, col; - u4Byte reg82c, reg830, reg838; - - if (pDM_Odm->CutVersion != ODM_CUT_B) - return; - - if (bw_8821c == ODM_BW20M) - row = 0; - else if (bw_8821c == ODM_BW40M) - row = 3; - else - row = 6; - - if (central_ch_8821c <= 14) { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 0; - else - col = 1; - } else { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 2; - else - col = 3; - } - - if (pDM_Odm->RFEType == 0) {/*iFEM*/ - reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8821c; - reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8821c; - reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8821c; - } else {/*eFEM*/ - reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8821c; - reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8821c; - reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8821c; - } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); - ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Bcut (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", - __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, row, col)); -#endif -} - -VOID -phydm_ccapar_by_bw_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ -#if 0 - u4Byte reg82c; - - - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; - - /* A-cut */ - reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); - - if (bandwidth == ODM_BW20M) { - /* 82c[15:12] = 4 */ - /* 82c[27:24] = 6 */ - - reg82c &= (~(0x0f00f000)); - reg82c |= ((0x4) << 12); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW40M) { - /* 82c[19:16] = 9 */ - /* 82c[27:24] = 6 */ - - reg82c &= (~(0x0f0f0000)); - reg82c |= ((0x9) << 16); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW80M) { - /* 82c[15:12] 7 */ - /* 82c[19:16] b */ - /* 82c[23:20] d */ - /* 82c[27:24] 3 */ - - reg82c &= (~(0x0ffff000)); - reg82c |= ((0xdb7) << 12); - reg82c |= ((0x3) << 24); - } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); -#endif -} - -VOID -phydm_ccapar_by_rxpath_8821c( - IN PDM_ODM_T pDM_Odm - ) -{ -#if 0 - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; - - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) { - /* 838[7:4] = 8 */ - /* 838[11:8] = 7 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 7 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678); - } else { - /* 838[7:4] = 3 */ - /* 838[11:8] = 3 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 6 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633); - } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); -#endif -} - -VOID -phydm_rxdfirpar_by_bw_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - if (bandwidth == ODM_BW40M) { - /* RX DFIR for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x0); - } else if (bandwidth == ODM_BW80M) { - /* RX DFIR for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x1); - } else { - /* RX DFIR for BW20, BW10 and BW5*/ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1); - ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x0); - } -} - -BOOLEAN -phydm_write_txagc_1byte_8821c( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc), i; - u1Byte rate_offset = (HwRate & 0x3); - u4Byte rate_mask = (0xff << (rate_offset << 3)); - u4Byte txagc_content = 0x0; - - /* For debug command only!!!! */ - - /* Error handling */ - if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); - return FALSE; - } - -#if 1 - /* For HW limitation, We can't write TXAGC once a byte. */ - for (i = 0; i < 4; i++) { - if (i != rate_offset) - txagc_content = txagc_content|(config_phydm_read_txagc_8821c(pDM_Odm, Path, rate_idx + i) << (i << 3)); - else - txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3)); - } - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content); -#else - ODM_Write1Byte(pDM_Odm, (offset_txagc[Path] + HwRate), (PowerIndex & 0x3f)); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - __func__, Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; -} - -/* ======================================================================== */ - -/* ======================================================================== */ -/* These following functions can be used by driver*/ - -u4Byte -config_phydm_read_rf_reg_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ - u4Byte Readback_Value, Direct_Addr; - u4Byte offset_readRF[2] = {0x2800, 0x2c00}; - u4Byte power_RF[2] = {0x1c, 0xec}; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_A) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, RFPath)); - return INVALID_RF_DATA; - } - - /* Error handling. Check if RF power is enable or not */ - /* 0xffffffff means RF power is disable */ - if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Read fail, RF is disabled\n", __func__)); - return INVALID_RF_DATA; - } - - /* Calculate offset */ - RegAddr &= 0xff; - Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); - - /* RF register only has 20bits */ - BitMask &= bRFRegOffsetMask; - - /* Read RF register directly */ - Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - __func__, RFPath, RegAddr, Readback_Value, BitMask)); - return Readback_Value; -} - -BOOLEAN -config_phydm_write_rf_reg_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ - u4Byte DataAndAddr = 0, Data_original = 0; - u4Byte offset_writeRF[2] = {0xc90, 0xe90}; - u4Byte power_RF[2] = {0x1c, 0xec}; - u1Byte BitShift; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_A) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, RFPath)); - return FALSE; - } - - /* Read RF register content first */ - RegAddr &= 0xff; - BitMask = BitMask & bRFRegOffsetMask; - - if (BitMask != bRFRegOffsetMask) { - Data_original = config_phydm_read_rf_reg_8821c(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); - - /* Error handling. RF is disabled */ - if (config_phydm_read_rf_check_8821c(Data_original) == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disable\n", __func__)); - return FALSE; - } - - /* check bit mask */ - if (BitMask != 0xfffff) { - for (BitShift = 0; BitShift <= 19; BitShift++) { - if (((BitMask >> BitShift) & 0x1) == 1) - break; - } - Data = ((Data_original) & (~BitMask)) | (Data << BitShift); - } - } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disabled\n", __func__)); - return FALSE; - } - - /* Put write addr in [27:20] and write data in [19:00] */ - DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; - - /* Write Operation */ - ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - __func__, RFPath, RegAddr, Data, Data_original, BitMask)); - return TRUE; -} - -BOOLEAN -config_phydm_write_txagc_8821c( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc), i; - u4Byte txagc_content = 0x0; - - /* Input need to be HW rate index, not driver rate index!!!! */ - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); - return TRUE; - } - - /* Error handling */ - if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); - return FALSE; - } - - /* driver need to construct a 4-byte power index */ - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - __func__, Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; -} - -u1Byte -config_phydm_read_txagc_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u1Byte readBack_data; - - /* Input need to be HW rate index, not driver rate index!!!! */ - - /* Error handling */ - if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); - return INVALID_TXAGC_DATA; - } - - /* Disable TX AGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */ - - /* Set data rate index (bit0~6) and path index (bit7) */ - ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7))); - - /* Enable TXAGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1); - - /* Read TX AGC report */ - readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000); - - /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d rate index 0x%x = 0x%x\n", __func__, Path, HwRate, readBack_data)); - return readBack_data; -} - -BOOLEAN -config_phydm_switch_band_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) -{ - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]======================>\n", __func__)); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); - return TRUE; - } - - rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); - - if (central_ch <= 14) { - /* 2.4G */ - - /* Enable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1); - - /* Disable MAC CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0); - - /* Disable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0); - - /*CCA Mask*/ - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ - - /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); - } else if (central_ch > 35) { - /* 5G */ - - /* Enable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1); - - /* Enable CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1); - - /* Disable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0); - - /*CCA Mask*/ - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ - - /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); - rf_reg18 = (rf_reg18|BIT8|BIT16); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); - return FALSE; - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (phydm_rfe_8821c(pDM_Odm, central_ch) == FALSE) - return FALSE; - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n", __func__, central_ch)); - return FALSE; - } - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch band (ch: %d)\n", __func__, central_ch)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_channel_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte rf_reg18, rf_regB8 = 0; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]====================>\n", __func__)); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); - return TRUE; - } - - central_ch_8821c = central_ch; - rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - rf_regB8 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_regB8); - } - - /* Switch band and channel */ - if (central_ch <= 14) { - /* 2.4G */ - - /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); - rf_reg18 = (rf_reg18|central_ch); - - /* 2. AGC table selection */ - ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x0); - pDM_DigTable->agcTableIdx = 0x0; - - /* 3. Set central frequency for clock offset tracking */ - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a); - - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_regB8 = rf_regB8 | BIT19; - - } else if (central_ch > 35) { - /* 5G */ - - /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); - rf_reg18 = (rf_reg18 | central_ch); - - if (central_ch >= 36 && central_ch <= 64) - ; - else if ((central_ch >= 100) && (central_ch <= 140)) - rf_reg18 = (rf_reg18 | BIT17); - else if (central_ch > 140) - rf_reg18 = (rf_reg18 | BIT18); - else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (RF18) (ch: %d)\n", __func__, central_ch)); - return FALSE; - } - - /* 2. AGC table selection */ - if ((central_ch >= 36) && (central_ch <= 64)) { - ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x1); - pDM_DigTable->agcTableIdx = 0x1; - } else if ((central_ch >= 100) && (central_ch <= 144)) { - ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x2); - pDM_DigTable->agcTableIdx = 0x2; - } else if (central_ch >= 149) { - ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x3); - pDM_DigTable->agcTableIdx = 0x3; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (AGC) (ch: %d)\n", __func__, central_ch)); - return FALSE; - } - - /* 3. Set central frequency for clock offset tracking */ - if ((central_ch >= 36) && (central_ch <= 48)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494); - else if ((central_ch >= 52) && (central_ch <= 64)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453); - else if ((central_ch >= 100) && (central_ch <= 116)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452); - else if ((central_ch >= 118) && (central_ch <= 177)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412); - else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (fc_area) (ch: %d)\n", __func__, central_ch)); - return FALSE; - } - - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if ((central_ch >= 57) && (central_ch <= 75)) - rf_regB8 = rf_regB8 & (~BIT19); - else - rf_regB8 = rf_regB8 | BIT19; - } - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); - return FALSE; - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n", __func__, central_ch)); - return FALSE; - } - - phydm_ccapar_8821c(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch channel (ch: %d)\n", __func__, central_ch)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_bandwidth_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]===================>\n", __func__)); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); - return TRUE; - } - - /* Error handling */ - if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); - return FALSE; - } - - bw_8821c = bandwidth; - rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); - - /* Switch bandwidth */ - switch (bandwidth) { - case ODM_BW20M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M); - - /* ADC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 | BIT11 | BIT10); - - break; - } - case ODM_BW40M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M)); - - /* CCK primary channel */ - if (primary_ch_idx == 1) - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx); - else - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0); - - /* ADC clock = 160M clock for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT11); - - break; - } - case ODM_BW80M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M)); - - /* ADC clock = 160M clock for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT10); - - break; - } - case ODM_BW5M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M)); - - /* ADC clock = 40M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - case ODM_BW10M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M)); - - /* ADC clock = 80M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); - } - - /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", __func__, bandwidth, primary_ch_idx)); - return FALSE; - } - - /* Modify RX DFIR parameters */ - phydm_rxdfirpar_by_bw_8821c(pDM_Odm, bandwidth); - - /* Modify CCA parameters */ - phydm_ccapar_by_bw_8821c(pDM_Odm, bandwidth); - phydm_ccapar_8821c(pDM_Odm); - - /* Toggle RX path to avoid RX dead zone issue */ - /*ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0);*/ - /*ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x11);*/ - - - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_channel_bw_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - u1Byte eRFPath = 0; - u4Byte RFValToWR , RFTmpVal, BitShift, BitMask; - - /* Switch band */ - if (config_phydm_switch_band_8821c(pDM_Odm, central_ch) == FALSE) - return FALSE; - - /* Switch channel */ - if (config_phydm_switch_channel_8821c(pDM_Odm, central_ch) == FALSE) - return FALSE; - - /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8821c(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) - return FALSE; - - return TRUE; -} - -BOOLEAN -config_phydm_trx_mode_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) -{ - return TRUE; -} - -BOOLEAN -config_phydm_parameter_init_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ) -{ - if (type == ODM_PRE_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Pre setting: disable OFDM and CCK block\n", __func__)); - } else if (type == ODM_POST_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Post setting: enable OFDM and CCK block\n", __func__)); - reg82c_8821c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); - reg838_8821c = ODM_GetBBReg(pDM_Odm, 0x838, bMaskDWord); - reg830_8821c = ODM_GetBBReg(pDM_Odm, 0x830, bMaskDWord); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Wrong type!!\n", __func__)); - return FALSE; - } - - return TRUE; -} - -u4Byte -query_phydm_trx_capability_8821c( - IN PDM_ODM_T pDM_Odm -){ - u4Byte value32 = 0x00000000; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: trx_capability = 0x%x\n", __func__, value32)); - return value32; -} - -u4Byte -query_phydm_stbc_capability_8821c( - IN PDM_ODM_T pDM_Odm -){ - u4Byte value32 = 0x00010001; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: stbc_capability = 0x%x\n", __func__, value32)); - return value32; -} - -u4Byte -query_phydm_ldpc_capability_8821c( - IN PDM_ODM_T pDM_Odm -){ - u4Byte value32 = 0x01000100; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: ldpc_capability = 0x%x\n", __func__, value32)); - return value32; -} - -u4Byte -query_phydm_txbf_parameters_8821c( - IN PDM_ODM_T pDM_Odm -){ - u4Byte value32 = 0x00030003; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_parameters = 0x%x\n", __func__, value32)); - return value32; -} - -u4Byte -query_phydm_txbf_capability_8821c( - IN PDM_ODM_T pDM_Odm -){ - u4Byte value32 = 0x01010001; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_capability = 0x%x\n", __func__, value32)); - return value32; -} - -/* ======================================================================== */ -#endif /* RTL8821C_SUPPORT == 1 */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821C_SUPPORT == 1) + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +u4Byte reg82c_8821c; +u4Byte reg838_8821c; +u4Byte reg830_8821c; +ODM_BW_E bw_8821c; +u1Byte central_ch_8821c; + + +BOOLEAN +phydm_rfe_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte channel + ) +{ +#if 0 + /* Efuse is not wrote now */ + /* Need to check RFE type finally */ + /*if (pDM_Odm->RFEType == 1) {*/ + if (channel <= 14) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + } else if (channel > 35) { + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + } else + return FALSE; + + /* chip top mux */ + ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0); + ODM_SetBBReg(pDM_Odm, 0x40, BIT2, 0x1); + + /* from s0 or s1 */ + ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30); + ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3); + + /* input or output */ + ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f); + ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3); + + /* delay 400ns for PAPE */ + ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); + + /* antenna switch table */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555); + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + /*}*/ +#endif + return TRUE; +} + +VOID +phydm_ccapar_8821c( + IN PDM_ODM_T pDM_Odm + ) +{ +#if 0 + u4Byte cca_ifem[9][4] = { + /*20M*/ + {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/ + /*40M*/ + {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ + {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/ + {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/ + /*80M*/ + {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ + {0x00000000, 0x87746641, 0x00000000, 0x87746641} }; /*Reg838*/ + + u4Byte cca_efem[9][4] = { + /*20M*/ + {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ + {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ + /*40M*/ + {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ + {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ + /*80M*/ + {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/ + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ + {0x87766431, 0x87766431, 0x87766431, 0x87766431} }; /*Reg838*/ + + u1Byte row, col; + u4Byte reg82c, reg830, reg838; + + if (pDM_Odm->CutVersion != ODM_CUT_B) + return; + + if (bw_8821c == ODM_BW20M) + row = 0; + else if (bw_8821c == ODM_BW40M) + row = 3; + else + row = 6; + + if (central_ch_8821c <= 14) { + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) + col = 0; + else + col = 1; + } else { + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) + col = 2; + else + col = 3; + } + + if (pDM_Odm->RFEType == 0) {/*iFEM*/ + reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8821c; + reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8821c; + reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8821c; + } else {/*eFEM*/ + reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8821c; + reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8821c; + reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8821c; + } + + ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); + ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); + ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Bcut (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", + __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, row, col)); +#endif +} + +VOID +phydm_ccapar_by_bw_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ +#if 0 + u4Byte reg82c; + + + if (pDM_Odm->CutVersion != ODM_CUT_A) + return; + + /* A-cut */ + reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); + + if (bandwidth == ODM_BW20M) { + /* 82c[15:12] = 4 */ + /* 82c[27:24] = 6 */ + + reg82c &= (~(0x0f00f000)); + reg82c |= ((0x4) << 12); + reg82c |= ((0x6) << 24); + } else if (bandwidth == ODM_BW40M) { + /* 82c[19:16] = 9 */ + /* 82c[27:24] = 6 */ + + reg82c &= (~(0x0f0f0000)); + reg82c |= ((0x9) << 16); + reg82c |= ((0x6) << 24); + } else if (bandwidth == ODM_BW80M) { + /* 82c[15:12] 7 */ + /* 82c[19:16] b */ + /* 82c[23:20] d */ + /* 82c[27:24] 3 */ + + reg82c &= (~(0x0ffff000)); + reg82c |= ((0xdb7) << 12); + reg82c |= ((0x3) << 24); + } + + ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); +#endif +} + +VOID +phydm_ccapar_by_rxpath_8821c( + IN PDM_ODM_T pDM_Odm + ) +{ +#if 0 + if (pDM_Odm->CutVersion != ODM_CUT_A) + return; + + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) { + /* 838[7:4] = 8 */ + /* 838[11:8] = 7 */ + /* 838[15:12] = 6 */ + /* 838[19:16] = 7 */ + /* 838[23:20] = 7 */ + /* 838[27:24] = 7 */ + ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678); + } else { + /* 838[7:4] = 3 */ + /* 838[11:8] = 3 */ + /* 838[15:12] = 6 */ + /* 838[19:16] = 6 */ + /* 838[23:20] = 7 */ + /* 838[27:24] = 7 */ + ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633); + } + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); +#endif +} + +VOID +phydm_rxdfirpar_by_bw_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ + if (bandwidth == ODM_BW40M) { + /* RX DFIR for BW40 */ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x0); + } else if (bandwidth == ODM_BW80M) { + /* RX DFIR for BW80 */ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x1); + } else { + /* RX DFIR for BW20, BW10 and BW5*/ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1); + ODM_SetBBReg(pDM_Odm, 0x8f0, BIT31, 0x0); + } +} + +BOOLEAN +phydm_write_txagc_1byte_8821c( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; + u1Byte rate_idx = (HwRate & 0xfc), i; + u1Byte rate_offset = (HwRate & 0x3); + u4Byte rate_mask = (0xff << (rate_offset << 3)); + u4Byte txagc_content = 0x0; + + /* For debug command only!!!! */ + + /* Error handling */ + if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); + return FALSE; + } + +#if 1 + /* For HW limitation, We can't write TXAGC once a byte. */ + for (i = 0; i < 4; i++) { + if (i != rate_offset) + txagc_content = txagc_content|(config_phydm_read_txagc_8821c(pDM_Odm, Path, rate_idx + i) << (i << 3)); + else + txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3)); + } + ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content); +#else + ODM_Write1Byte(pDM_Odm, (offset_txagc[Path] + HwRate), (PowerIndex & 0x3f)); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d Rate index 0x%x (0x%x) = 0x%x\n", + __func__, Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); + return TRUE; +} + +/* ======================================================================== */ + +/* ======================================================================== */ +/* These following functions can be used by driver*/ + +u4Byte +config_phydm_read_rf_reg_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ + u4Byte Readback_Value, Direct_Addr; + u4Byte offset_readRF[2] = {0x2800, 0x2c00}; + u4Byte power_RF[2] = {0x1c, 0xec}; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_A) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, RFPath)); + return INVALID_RF_DATA; + } + + /* Error handling. Check if RF power is enable or not */ + /* 0xffffffff means RF power is disable */ + if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Read fail, RF is disabled\n", __func__)); + return INVALID_RF_DATA; + } + + /* Calculate offset */ + RegAddr &= 0xff; + Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); + + /* RF register only has 20bits */ + BitMask &= bRFRegOffsetMask; + + /* Read RF register directly */ + Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + __func__, RFPath, RegAddr, Readback_Value, BitMask)); + return Readback_Value; +} + +BOOLEAN +config_phydm_write_rf_reg_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ + u4Byte DataAndAddr = 0, Data_original = 0; + u4Byte offset_writeRF[2] = {0xc90, 0xe90}; + u4Byte power_RF[2] = {0x1c, 0xec}; + u1Byte BitShift; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_A) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, RFPath)); + return FALSE; + } + + /* Read RF register content first */ + RegAddr &= 0xff; + BitMask = BitMask & bRFRegOffsetMask; + + if (BitMask != bRFRegOffsetMask) { + Data_original = config_phydm_read_rf_reg_8821c(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); + + /* Error handling. RF is disabled */ + if (config_phydm_read_rf_check_8821c(Data_original) == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disable\n", __func__)); + return FALSE; + } + + /* check bit mask */ + if (BitMask != 0xfffff) { + for (BitShift = 0; BitShift <= 19; BitShift++) { + if (((BitMask >> BitShift) & 0x1) == 1) + break; + } + Data = ((Data_original) & (~BitMask)) | (Data << BitShift); + } + } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disabled\n", __func__)); + return FALSE; + } + + /* Put write addr in [27:20] and write data in [19:00] */ + DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; + + /* Write Operation */ + ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + __func__, RFPath, RegAddr, Data, Data_original, BitMask)); + return TRUE; +} + +BOOLEAN +config_phydm_write_txagc_8821c( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; + u1Byte rate_idx = (HwRate & 0xfc), i; + u4Byte txagc_content = 0x0; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return TRUE; + } + + /* Error handling */ + if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); + return FALSE; + } + + /* driver need to construct a 4-byte power index */ + ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d Rate index 0x%x (0x%x) = 0x%x\n", + __func__, Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); + return TRUE; +} + +u1Byte +config_phydm_read_txagc_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u1Byte readBack_data; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + /* Error handling */ + if ((Path > ODM_RF_PATH_A) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, Path)); + return INVALID_TXAGC_DATA; + } + + /* Disable TX AGC report */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */ + + /* Set data rate index (bit0~6) and path index (bit7) */ + ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7))); + + /* Enable TXAGC report */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1); + + /* Read TX AGC report */ + readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000); + + /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Path-%d rate index 0x%x = 0x%x\n", __func__, Path, HwRate, readBack_data)); + return readBack_data; +} + +BOOLEAN +config_phydm_switch_band_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ) +{ + u4Byte rf_reg18; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]======================>\n", __func__)); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return TRUE; + } + + rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + if (central_ch <= 14) { + /* 2.4G */ + + /* Enable CCK block */ + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1); + + /* Disable MAC CCK check */ + ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0); + + /* Disable BB CCK check */ + ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0); + + /*CCA Mask*/ + ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); + } else if (central_ch > 35) { + /* 5G */ + + /* Enable BB CCK check */ + ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1); + + /* Enable CCK check */ + ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1); + + /* Disable CCK block */ + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0); + + /*CCA Mask*/ + ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); + rf_reg18 = (rf_reg18|BIT8|BIT16); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + return FALSE; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (phydm_rfe_8821c(pDM_Odm, central_ch) == FALSE) + return FALSE; + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch band (ch: %d)\n", __func__, central_ch)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_channel_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u4Byte rf_reg18, rf_regB8 = 0; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]====================>\n", __func__)); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return TRUE; + } + + central_ch_8821c = central_ch; + rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + rf_regB8 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_regB8); + } + + /* Switch band and channel */ + if (central_ch <= 14) { + /* 2.4G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); + rf_reg18 = (rf_reg18|central_ch); + + /* 2. AGC table selection */ + ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x0); + pDM_DigTable->agcTableIdx = 0x0; + + /* 3. Set central frequency for clock offset tracking */ + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a); + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (pDM_Odm->CutVersion == ODM_CUT_A) + rf_regB8 = rf_regB8 | BIT19; + + } else if (central_ch > 35) { + /* 5G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); + rf_reg18 = (rf_reg18 | central_ch); + + if (central_ch >= 36 && central_ch <= 64) + ; + else if ((central_ch >= 100) && (central_ch <= 140)) + rf_reg18 = (rf_reg18 | BIT17); + else if (central_ch > 140) + rf_reg18 = (rf_reg18 | BIT18); + else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (RF18) (ch: %d)\n", __func__, central_ch)); + return FALSE; + } + + /* 2. AGC table selection */ + if ((central_ch >= 36) && (central_ch <= 64)) { + ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x1); + pDM_DigTable->agcTableIdx = 0x1; + } else if ((central_ch >= 100) && (central_ch <= 144)) { + ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x2); + pDM_DigTable->agcTableIdx = 0x2; + } else if (central_ch >= 149) { + ODM_SetBBReg(pDM_Odm, 0xc1c, 0x00000F00, 0x3); + pDM_DigTable->agcTableIdx = 0x3; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (AGC) (ch: %d)\n", __func__, central_ch)); + return FALSE; + } + + /* 3. Set central frequency for clock offset tracking */ + if ((central_ch >= 36) && (central_ch <= 48)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494); + else if ((central_ch >= 52) && (central_ch <= 64)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453); + else if ((central_ch >= 100) && (central_ch <= 116)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452); + else if ((central_ch >= 118) && (central_ch <= 177)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412); + else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (fc_area) (ch: %d)\n", __func__, central_ch)); + return FALSE; + } + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if ((central_ch >= 57) && (central_ch <= 75)) + rf_regB8 = rf_regB8 & (~BIT19); + else + rf_regB8 = rf_regB8 | BIT19; + } + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + return FALSE; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->CutVersion == ODM_CUT_A) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + return FALSE; + } + + phydm_ccapar_8821c(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch channel (ch: %d)\n", __func__, central_ch)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_bandwidth_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + u4Byte rf_reg18; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]===================>\n", __func__)); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return TRUE; + } + + /* Error handling */ + if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + return FALSE; + } + + bw_8821c = bandwidth; + rf_reg18 = config_phydm_read_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + /* Switch bandwidth */ + switch (bandwidth) { + case ODM_BW20M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M); + + /* ADC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT11 | BIT10); + + break; + } + case ODM_BW40M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M)); + + /* CCK primary channel */ + if (primary_ch_idx == 1) + ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx); + else + ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0); + + /* ADC clock = 160M clock for BW40 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); + rf_reg18 = (rf_reg18|BIT11); + + break; + } + case ODM_BW80M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M)); + + /* ADC clock = 160M clock for BW80 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); + rf_reg18 = (rf_reg18|BIT10); + + break; + } + case ODM_BW5M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M)); + + /* ADC clock = 40M clock */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + case ODM_BW10M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M)); + + /* ADC clock = 80M clock */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + } + + /* Write RF register */ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", __func__, bandwidth, primary_ch_idx)); + return FALSE; + } + + /* Modify RX DFIR parameters */ + phydm_rxdfirpar_by_bw_8821c(pDM_Odm, bandwidth); + + /* Modify CCA parameters */ + phydm_ccapar_by_bw_8821c(pDM_Odm, bandwidth); + phydm_ccapar_8821c(pDM_Odm); + + /* Toggle RX path to avoid RX dead zone issue */ + /*ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0);*/ + /*ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x11);*/ + + + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_channel_bw_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + u1Byte eRFPath = 0; + u4Byte RFValToWR , RFTmpVal, BitShift, BitMask; + + /* Switch band */ + if (config_phydm_switch_band_8821c(pDM_Odm, central_ch) == FALSE) + return FALSE; + + /* Switch channel */ + if (config_phydm_switch_channel_8821c(pDM_Odm, central_ch) == FALSE) + return FALSE; + + /* Switch bandwidth */ + if (config_phydm_switch_bandwidth_8821c(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) + return FALSE; + + return TRUE; +} + +BOOLEAN +config_phydm_trx_mode_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ) +{ + return TRUE; +} + +BOOLEAN +config_phydm_parameter_init_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ) +{ + if (type == ODM_PRE_SETTING) { + ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Pre setting: disable OFDM and CCK block\n", __func__)); + } else if (type == ODM_POST_SETTING) { + ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Post setting: enable OFDM and CCK block\n", __func__)); + reg82c_8821c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); + reg838_8821c = ODM_GetBBReg(pDM_Odm, 0x838, bMaskDWord); + reg830_8821c = ODM_GetBBReg(pDM_Odm, 0x830, bMaskDWord); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Wrong type!!\n", __func__)); + return FALSE; + } + + return TRUE; +} + +u4Byte +query_phydm_trx_capability_8821c( + IN PDM_ODM_T pDM_Odm +){ + u4Byte value32 = 0x00000000; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: trx_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u4Byte +query_phydm_stbc_capability_8821c( + IN PDM_ODM_T pDM_Odm +){ + u4Byte value32 = 0x00010001; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: stbc_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u4Byte +query_phydm_ldpc_capability_8821c( + IN PDM_ODM_T pDM_Odm +){ + u4Byte value32 = 0x01000100; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: ldpc_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u4Byte +query_phydm_txbf_parameters_8821c( + IN PDM_ODM_T pDM_Odm +){ + u4Byte value32 = 0x00030003; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_parameters = 0x%x\n", __func__, value32)); + return value32; +} + +u4Byte +query_phydm_txbf_capability_8821c( + IN PDM_ODM_T pDM_Odm +){ + u4Byte value32 = 0x01010001; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_capability = 0x%x\n", __func__, value32)); + return value32; +} + +/* ======================================================================== */ +#endif /* RTL8821C_SUPPORT == 1 */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.h b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.h index 3c45a2086ce..e4a8bc71dbb 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_hal_api8821c.h @@ -1,148 +1,148 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_PHYDM_API_H_8821C__ -#define __INC_PHYDM_API_H_8821C__ - -#if (RTL8821C_SUPPORT == 1) - -#define PHY_CONFIG_VERSION_8821C "2.1.5" /*2016.04.12 (HW user guide version: R02, SW user guide version: R01, Modification: R06)*/ - -#define INVALID_RF_DATA 0xffffffff -#define INVALID_TXAGC_DATA 0xff - -#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA) -#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA) - -u4Byte -config_phydm_read_rf_reg_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - -BOOLEAN -config_phydm_write_rf_reg_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -BOOLEAN -config_phydm_write_txagc_8821c( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -u1Byte -config_phydm_read_txagc_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -BOOLEAN -config_phydm_switch_band_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_channel_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_bandwidth_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_switch_channel_bw_8821c( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_trx_mode_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ); - -BOOLEAN -config_phydm_parameter_init_8821c( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ); - - -/* ======================================================================== */ -/* These following functions can be used for PHY DM only*/ - -BOOLEAN -phydm_write_txagc_1byte_8821c( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -/* ======================================================================== */ - -u4Byte -query_phydm_trx_capability_8821c( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_stbc_capability_8821c( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_ldpc_capability_8821c( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_txbf_parameters_8821c( - IN PDM_ODM_T pDM_Odm -); - -u4Byte -query_phydm_txbf_capability_8821c( - IN PDM_ODM_T pDM_Odm -); - -#endif /* RTL8821C_SUPPORT == 1 */ -#endif /* __INC_PHYDM_API_H_8821C__ */ - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_PHYDM_API_H_8821C__ +#define __INC_PHYDM_API_H_8821C__ + +#if (RTL8821C_SUPPORT == 1) + +#define PHY_CONFIG_VERSION_8821C "2.1.5" /*2016.04.12 (HW user guide version: R02, SW user guide version: R01, Modification: R06)*/ + +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff + +#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA) +#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA) + +u4Byte +config_phydm_read_rf_reg_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +BOOLEAN +config_phydm_write_rf_reg_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +BOOLEAN +config_phydm_write_txagc_8821c( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +u1Byte +config_phydm_read_txagc_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +BOOLEAN +config_phydm_switch_band_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_channel_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_bandwidth_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_switch_channel_bw_8821c( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_trx_mode_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ); + +BOOLEAN +config_phydm_parameter_init_8821c( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ); + + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +BOOLEAN +phydm_write_txagc_1byte_8821c( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +/* ======================================================================== */ + +u4Byte +query_phydm_trx_capability_8821c( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_stbc_capability_8821c( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_ldpc_capability_8821c( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_txbf_parameters_8821c( + IN PDM_ODM_T pDM_Odm +); + +u4Byte +query_phydm_txbf_capability_8821c( + IN PDM_ODM_T pDM_Odm +); + +#endif /* RTL8821C_SUPPORT == 1 */ +#endif /* __INC_PHYDM_API_H_8821C__ */ + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_iqk_8821c.h b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_iqk_8821c.h index 381b762382b..1bc4593740e 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_iqk_8821c.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_iqk_8821c.h @@ -1,54 +1,54 @@ -#ifndef __PHYDM_IQK_8821C_H__ -#define __PHYDM_IQK_8821C_H__ - -#if (RTL8821C_SUPPORT == 1) - - -/*--------------------------Define Parameters-------------------------------*/ -#define MAC_REG_NUM_8821C 2 -#define BB_REG_NUM_8821C 9 -#define RF_REG_NUM_8821C 5 -#define NUM_8821C 1 - -#define LOK_delay_8821C 1 -#define IQK_delay_8821C 1 -#define WBIQK_delay_8821C 1 - -#define TXIQK 0 -#define RXIQK 1 - -/*---------------------------End Define Parameters-------------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -DoIQK_8821C( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#else -VOID -DoIQK_8821C( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#endif - -VOID -PHY_IQCalibrate_8821C( - IN PVOID pDM_VOID, - IN BOOLEAN reset - ); - -#else /* (RTL8821C_SUPPORT == 0)*/ - -#define PHY_IQCalibrate_8821C(_pDM_VOID, _reset) - -#endif /* RTL8821C_SUPPORT */ - - #endif /* #ifndef __PHYDM_IQK_8821C_H__*/ - +#ifndef __PHYDM_IQK_8821C_H__ +#define __PHYDM_IQK_8821C_H__ + +#if (RTL8821C_SUPPORT == 1) + + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8821C 2 +#define BB_REG_NUM_8821C 9 +#define RF_REG_NUM_8821C 5 +#define NUM_8821C 1 + +#define LOK_delay_8821C 1 +#define IQK_delay_8821C 1 +#define WBIQK_delay_8821C 1 + +#define TXIQK 0 +#define RXIQK 1 + +/*---------------------------End Define Parameters-------------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +DoIQK_8821C( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#else +VOID +DoIQK_8821C( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#endif + +VOID +PHY_IQCalibrate_8821C( + IN PVOID pDM_VOID, + IN BOOLEAN reset + ); + +#else /* (RTL8821C_SUPPORT == 0)*/ + +#define PHY_IQCalibrate_8821C(_pDM_VOID, _reset) + +#endif /* RTL8821C_SUPPORT */ + + #endif /* #ifndef __PHYDM_IQK_8821C_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.c b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.c index dfff1ad26af..6acca406481 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.c +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.c @@ -1,185 +1,185 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8821C_SUPPORT == 1) - -void -odm_ConfigRFReg_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if (Addr == 0xffe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - } -} - -void -odm_ConfigRF_RadioA_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; /* RF_Content: radioa_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8821C(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigMAC_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_UpdateAgcBigJumpLmt_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte rfGainIdx = (u1Byte)((Data & 0xFF000000) >> 24); - u1Byte bbGainIdx = (u1Byte)((Data & 0x00ff0000) >> 16); - u1Byte agcTableIdx = (u1Byte)((Data & 0x00000f00) >> 8); - static BOOLEAN isLimit; - - if (Addr != 0x81c) - return; - - /*DbgPrint("Data = 0x%x, rfGainIdx = 0x%x, bbGainIdx = 0x%x, agcTableIdx = 0x%d\n", Data, rfGainIdx, bbGainIdx, agcTableIdx);*/ - /*DbgPrint("rfGainIdx = 0x%x, pDM_DigTable->rfGainIdx = 0x%x\n", rfGainIdx, pDM_DigTable->rfGainIdx);*/ - - if (bbGainIdx > 0x3c) { - if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { - isLimit = TRUE; - pDM_DigTable->bigJumpLmt[agcTableIdx] = bbGainIdx - 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", agcTableIdx, pDM_DigTable->bigJumpLmt[agcTableIdx])); - } - } else - isLimit = FALSE; - - pDM_DigTable->rfGainIdx = rfGainIdx; - -} - -void -odm_ConfigBB_AGC_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - odm_UpdateAgcBigJumpLmt_8821C(pDM_Odm, Addr, Data); - - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - -#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xffe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8821C( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8821C_SUPPORT == 1) + +void +odm_ConfigRFReg_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if (Addr == 0xffe) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void +odm_ConfigRF_RadioA_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; /* RF_Content: radioa_txt */ + u4Byte maskforPhySet = (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8821C(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigMAC_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_UpdateAgcBigJumpLmt_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte rfGainIdx = (u1Byte)((Data & 0xFF000000) >> 24); + u1Byte bbGainIdx = (u1Byte)((Data & 0x00ff0000) >> 16); + u1Byte agcTableIdx = (u1Byte)((Data & 0x00000f00) >> 8); + static BOOLEAN isLimit; + + if (Addr != 0x81c) + return; + + /*DbgPrint("Data = 0x%x, rfGainIdx = 0x%x, bbGainIdx = 0x%x, agcTableIdx = 0x%d\n", Data, rfGainIdx, bbGainIdx, agcTableIdx);*/ + /*DbgPrint("rfGainIdx = 0x%x, pDM_DigTable->rfGainIdx = 0x%x\n", rfGainIdx, pDM_DigTable->rfGainIdx);*/ + + if (bbGainIdx > 0x3c) { + if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { + isLimit = TRUE; + pDM_DigTable->bigJumpLmt[agcTableIdx] = bbGainIdx - 2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", agcTableIdx, pDM_DigTable->bigJumpLmt[agcTableIdx])); + } + } else + isLimit = FALSE; + + pDM_DigTable->rfGainIdx = rfGainIdx; + +} + +void +odm_ConfigBB_AGC_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + odm_UpdateAgcBigJumpLmt_8821C(pDM_Odm, Addr, Data); + + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + +#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8821C( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.h b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.h index a3901cfb47a..b3ef99f80d8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/phydm_regconfig8821c.h @@ -1,103 +1,103 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8821C -#define __INC_ODM_REGCONFIG_H_8821C - -#if (RTL8821C_SUPPORT == 1) - -void -odm_ConfigRFReg_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_UpdateAgcBigJumpLmt_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -); - -void -odm_ConfigBB_AGC_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8821C( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8821C( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif /* RTL8822B_SUPPORT == 1*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8821C +#define __INC_ODM_REGCONFIG_H_8821C + +#if (RTL8821C_SUPPORT == 1) + +void +odm_ConfigRFReg_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_UpdateAgcBigJumpLmt_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +); + +void +odm_ConfigBB_AGC_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8821C( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8821C( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif /* RTL8822B_SUPPORT == 1*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8821c/version_rtl8821c.h b/package/kernel/rtl8192cd/phydm/rtl8821c/version_rtl8821c.h index 9e7e4804036..b21e0d1af84 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8821c/version_rtl8821c.h +++ b/package/kernel/rtl8192cd/phydm/rtl8821c/version_rtl8821c.h @@ -1,9 +1,9 @@ -/*RTL8822B PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8821C 20160420 -#define COMMIT_BY_8821C "Colin" -#define RELEASE_VERSION_8821C 9 +/*RTL8822B PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8821C 20160420 +#define COMMIT_BY_8821C "Colin" +#define RELEASE_VERSION_8821C 9 diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.c b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.c index be98a512e73..cdf0258d814 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.c @@ -1,12051 +1,12051 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_AGC_TAB[] = { - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xEC240003, - 0x81C, 0xEB260003, - 0x81C, 0xEA280003, - 0x81C, 0xE92A0003, - 0x81C, 0xE82C0003, - 0x81C, 0xE72E0003, - 0x81C, 0xE6300003, - 0x81C, 0xE5320003, - 0x81C, 0xC8340003, - 0x81C, 0xC7360003, - 0x81C, 0xC6380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xC0440003, - 0x81C, 0xA3460003, - 0x81C, 0xA2480003, - 0x81C, 0xA14A0003, - 0x81C, 0xA04C0003, - 0x81C, 0x824E0003, - 0x81C, 0x81500003, - 0x81C, 0x80520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x445A0003, - 0x81C, 0x435C0003, - 0x81C, 0x425E0003, - 0x81C, 0x41600003, - 0x81C, 0x40620003, - 0x81C, 0x05640003, - 0x81C, 0x04660003, - 0x81C, 0x03680003, - 0x81C, 0x026A0003, - 0x81C, 0x016C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xF5000003, - 0x81C, 0xF4020003, - 0x81C, 0xF3040003, - 0x81C, 0xF2060003, - 0x81C, 0xF1080003, - 0x81C, 0xF00A0003, - 0x81C, 0xEF0C0003, - 0x81C, 0xEE0E0003, - 0x81C, 0xED100003, - 0x81C, 0xEC120003, - 0x81C, 0xEB140003, - 0x81C, 0xEA160003, - 0x81C, 0xE9180003, - 0x81C, 0xE81A0003, - 0x81C, 0xE71C0003, - 0x81C, 0xE61E0003, - 0x81C, 0xE5200003, - 0x81C, 0xE4220003, - 0x81C, 0xE3240003, - 0x81C, 0xE2260003, - 0x81C, 0xE1280003, - 0x81C, 0xE02A0003, - 0x81C, 0xC32C0003, - 0x81C, 0xC22E0003, - 0x81C, 0xC1300003, - 0x81C, 0xC0320003, - 0x81C, 0xA4340003, - 0x81C, 0xA3360003, - 0x81C, 0xA2380003, - 0x81C, 0xA13A0003, - 0x81C, 0xA03C0003, - 0x81C, 0x823E0003, - 0x81C, 0x81400003, - 0x81C, 0x80420003, - 0x81C, 0x64440003, - 0x81C, 0x63460003, - 0x81C, 0x62480003, - 0x81C, 0x614A0003, - 0x81C, 0x604C0003, - 0x81C, 0x454E0003, - 0x81C, 0x44500003, - 0x81C, 0x43520003, - 0x81C, 0x42540003, - 0x81C, 0x41560003, - 0x81C, 0x40580003, - 0x81C, 0x055A0003, - 0x81C, 0x045C0003, - 0x81C, 0x035E0003, - 0x81C, 0x02600003, - 0x81C, 0x01620003, - 0x81C, 0x00640003, - 0x81C, 0x00660003, - 0x81C, 0x00680003, - 0x81C, 0x006A0003, - 0x81C, 0x006C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFD000003, - 0x81C, 0xFC020003, - 0x81C, 0xFB040003, - 0x81C, 0xFA060003, - 0x81C, 0xF9080003, - 0x81C, 0xF80A0003, - 0x81C, 0xF70C0003, - 0x81C, 0xF60E0003, - 0x81C, 0xF5100003, - 0x81C, 0xF4120003, - 0x81C, 0xF3140003, - 0x81C, 0xF2160003, - 0x81C, 0xF1180003, - 0x81C, 0xF01A0003, - 0x81C, 0xEF1C0003, - 0x81C, 0xEE1E0003, - 0x81C, 0xED200003, - 0x81C, 0xEC220003, - 0x81C, 0xEB240003, - 0x81C, 0xEA260003, - 0x81C, 0xE9280003, - 0x81C, 0xE82A0003, - 0x81C, 0xE72C0003, - 0x81C, 0xE62E0003, - 0x81C, 0xE5300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xC43A0003, - 0x81C, 0xC33C0003, - 0x81C, 0xC23E0003, - 0x81C, 0xC1400003, - 0x81C, 0xC0420003, - 0x81C, 0xA5440003, - 0x81C, 0xA4460003, - 0x81C, 0xA3480003, - 0x81C, 0xA24A0003, - 0x81C, 0xA14C0003, - 0x81C, 0x834E0003, - 0x81C, 0x82500003, - 0x81C, 0x81520003, - 0x81C, 0x80540003, - 0x81C, 0x65560003, - 0x81C, 0x64580003, - 0x81C, 0x635A0003, - 0x81C, 0x625C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x40640003, - 0x81C, 0x06660003, - 0x81C, 0x05680003, - 0x81C, 0x046A0003, - 0x81C, 0x036C0003, - 0x81C, 0x026E0003, - 0x81C, 0x01700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFD000003, - 0x81C, 0xFC020003, - 0x81C, 0xFB040003, - 0x81C, 0xFA060003, - 0x81C, 0xF9080003, - 0x81C, 0xF80A0003, - 0x81C, 0xF70C0003, - 0x81C, 0xF60E0003, - 0x81C, 0xF5100003, - 0x81C, 0xF4120003, - 0x81C, 0xF3140003, - 0x81C, 0xF2160003, - 0x81C, 0xF1180003, - 0x81C, 0xF01A0003, - 0x81C, 0xEF1C0003, - 0x81C, 0xEE1E0003, - 0x81C, 0xED200003, - 0x81C, 0xEC220003, - 0x81C, 0xEB240003, - 0x81C, 0xEA260003, - 0x81C, 0xE9280003, - 0x81C, 0xE82A0003, - 0x81C, 0xE72C0003, - 0x81C, 0xE62E0003, - 0x81C, 0xE5300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xC43A0003, - 0x81C, 0xC33C0003, - 0x81C, 0xC23E0003, - 0x81C, 0xC1400003, - 0x81C, 0xC0420003, - 0x81C, 0xA5440003, - 0x81C, 0xA4460003, - 0x81C, 0xA3480003, - 0x81C, 0xA24A0003, - 0x81C, 0xA14C0003, - 0x81C, 0x834E0003, - 0x81C, 0x82500003, - 0x81C, 0x81520003, - 0x81C, 0x80540003, - 0x81C, 0x65560003, - 0x81C, 0x64580003, - 0x81C, 0x635A0003, - 0x81C, 0x625C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x40640003, - 0x81C, 0x06660003, - 0x81C, 0x05680003, - 0x81C, 0x046A0003, - 0x81C, 0x036C0003, - 0x81C, 0x026E0003, - 0x81C, 0x01700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xDC000003, - 0x81C, 0xDB020003, - 0x81C, 0xDA040003, - 0x81C, 0xD9060003, - 0x81C, 0xD8080003, - 0x81C, 0xD70A0003, - 0x81C, 0xD60C0003, - 0x81C, 0xD50E0003, - 0x81C, 0xD4100003, - 0x81C, 0xD3120003, - 0x81C, 0xD2140003, - 0x81C, 0xD1160003, - 0x81C, 0xD0180003, - 0x81C, 0xB41A0003, - 0x81C, 0xB31C0003, - 0x81C, 0xB21E0003, - 0x81C, 0xB1200003, - 0x81C, 0xB0220003, - 0x81C, 0xAF240003, - 0x81C, 0xAE260003, - 0x81C, 0xAD280003, - 0x81C, 0xAC2A0003, - 0x81C, 0xAB2C0003, - 0x81C, 0x8C2E0003, - 0x81C, 0x8B300003, - 0x81C, 0x8A320003, - 0x81C, 0x89340003, - 0x81C, 0x88360003, - 0x81C, 0x87380003, - 0x81C, 0x863A0003, - 0x81C, 0x853C0003, - 0x81C, 0x693E0003, - 0x81C, 0x68400003, - 0x81C, 0x67420003, - 0x81C, 0x66440003, - 0x81C, 0x65460003, - 0x81C, 0x48480003, - 0x81C, 0x474A0003, - 0x81C, 0x464C0003, - 0x81C, 0x454E0003, - 0x81C, 0x44500003, - 0x81C, 0x43520003, - 0x81C, 0x27540003, - 0x81C, 0x26560003, - 0x81C, 0x25580003, - 0x81C, 0x245A0003, - 0x81C, 0x235C0003, - 0x81C, 0x045E0003, - 0x81C, 0x03600003, - 0x81C, 0x02620003, - 0x81C, 0x01640003, - 0x81C, 0x00660003, - 0x81C, 0x00680003, - 0x81C, 0x006A0003, - 0x81C, 0x006C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFD000003, - 0x81C, 0xFC020003, - 0x81C, 0xFB040003, - 0x81C, 0xFA060003, - 0x81C, 0xF9080003, - 0x81C, 0xF80A0003, - 0x81C, 0xF70C0003, - 0x81C, 0xF60E0003, - 0x81C, 0xF5100003, - 0x81C, 0xF4120003, - 0x81C, 0xF3140003, - 0x81C, 0xF2160003, - 0x81C, 0xF1180003, - 0x81C, 0xF01A0003, - 0x81C, 0xEF1C0003, - 0x81C, 0xEE1E0003, - 0x81C, 0xED200003, - 0x81C, 0xEC220003, - 0x81C, 0xEB240003, - 0x81C, 0xEA260003, - 0x81C, 0xE9280003, - 0x81C, 0xE82A0003, - 0x81C, 0xE72C0003, - 0x81C, 0xE62E0003, - 0x81C, 0xE5300003, - 0x81C, 0xC8320003, - 0x81C, 0xC7340003, - 0x81C, 0xC6360003, - 0x81C, 0xC5380003, - 0x81C, 0xC43A0003, - 0x81C, 0xC33C0003, - 0x81C, 0xC23E0003, - 0x81C, 0xC1400003, - 0x81C, 0xC0420003, - 0x81C, 0xA5440003, - 0x81C, 0xA4460003, - 0x81C, 0xA3480003, - 0x81C, 0xA24A0003, - 0x81C, 0xA14C0003, - 0x81C, 0x834E0003, - 0x81C, 0x82500003, - 0x81C, 0x81520003, - 0x81C, 0x80540003, - 0x81C, 0x65560003, - 0x81C, 0x64580003, - 0x81C, 0x635A0003, - 0x81C, 0x625C0003, - 0x81C, 0x435E0003, - 0x81C, 0x42600003, - 0x81C, 0x41620003, - 0x81C, 0x40640003, - 0x81C, 0x06660003, - 0x81C, 0x05680003, - 0x81C, 0x046A0003, - 0x81C, 0x036C0003, - 0x81C, 0x026E0003, - 0x81C, 0x01700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xF5000003, - 0x81C, 0xF4020003, - 0x81C, 0xF3040003, - 0x81C, 0xF2060003, - 0x81C, 0xF1080003, - 0x81C, 0xF00A0003, - 0x81C, 0xEF0C0003, - 0x81C, 0xEE0E0003, - 0x81C, 0xED100003, - 0x81C, 0xEC120003, - 0x81C, 0xEB140003, - 0x81C, 0xEA160003, - 0x81C, 0xE9180003, - 0x81C, 0xE81A0003, - 0x81C, 0xE71C0003, - 0x81C, 0xE61E0003, - 0x81C, 0xE5200003, - 0x81C, 0xE4220003, - 0x81C, 0xE3240003, - 0x81C, 0xE2260003, - 0x81C, 0xE1280003, - 0x81C, 0xE02A0003, - 0x81C, 0xC32C0003, - 0x81C, 0xC22E0003, - 0x81C, 0xC1300003, - 0x81C, 0xC0320003, - 0x81C, 0xA4340003, - 0x81C, 0xA3360003, - 0x81C, 0xA2380003, - 0x81C, 0xA13A0003, - 0x81C, 0xA03C0003, - 0x81C, 0x823E0003, - 0x81C, 0x81400003, - 0x81C, 0x80420003, - 0x81C, 0x64440003, - 0x81C, 0x63460003, - 0x81C, 0x62480003, - 0x81C, 0x614A0003, - 0x81C, 0x604C0003, - 0x81C, 0x454E0003, - 0x81C, 0x44500003, - 0x81C, 0x43520003, - 0x81C, 0x42540003, - 0x81C, 0x41560003, - 0x81C, 0x40580003, - 0x81C, 0x055A0003, - 0x81C, 0x045C0003, - 0x81C, 0x035E0003, - 0x81C, 0x02600003, - 0x81C, 0x01620003, - 0x81C, 0x00640003, - 0x81C, 0x00660003, - 0x81C, 0x00680003, - 0x81C, 0x006A0003, - 0x81C, 0x006C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xF5000003, - 0x81C, 0xF4020003, - 0x81C, 0xF3040003, - 0x81C, 0xF2060003, - 0x81C, 0xF1080003, - 0x81C, 0xF00A0003, - 0x81C, 0xEF0C0003, - 0x81C, 0xEE0E0003, - 0x81C, 0xED100003, - 0x81C, 0xEC120003, - 0x81C, 0xEB140003, - 0x81C, 0xEA160003, - 0x81C, 0xE9180003, - 0x81C, 0xE81A0003, - 0x81C, 0xE71C0003, - 0x81C, 0xE61E0003, - 0x81C, 0xE5200003, - 0x81C, 0xE4220003, - 0x81C, 0xE3240003, - 0x81C, 0xE2260003, - 0x81C, 0xE1280003, - 0x81C, 0xE02A0003, - 0x81C, 0xC32C0003, - 0x81C, 0xC22E0003, - 0x81C, 0xC1300003, - 0x81C, 0xC0320003, - 0x81C, 0xA4340003, - 0x81C, 0xA3360003, - 0x81C, 0xA2380003, - 0x81C, 0xA13A0003, - 0x81C, 0xA03C0003, - 0x81C, 0x823E0003, - 0x81C, 0x81400003, - 0x81C, 0x80420003, - 0x81C, 0x64440003, - 0x81C, 0x63460003, - 0x81C, 0x62480003, - 0x81C, 0x614A0003, - 0x81C, 0x604C0003, - 0x81C, 0x454E0003, - 0x81C, 0x44500003, - 0x81C, 0x43520003, - 0x81C, 0x42540003, - 0x81C, 0x41560003, - 0x81C, 0x40580003, - 0x81C, 0x055A0003, - 0x81C, 0x045C0003, - 0x81C, 0x035E0003, - 0x81C, 0x02600003, - 0x81C, 0x01620003, - 0x81C, 0x00640003, - 0x81C, 0x00660003, - 0x81C, 0x00680003, - 0x81C, 0x006A0003, - 0x81C, 0x006C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xEC240003, - 0x81C, 0xEB260003, - 0x81C, 0xEA280003, - 0x81C, 0xE92A0003, - 0x81C, 0xE82C0003, - 0x81C, 0xE72E0003, - 0x81C, 0xE6300003, - 0x81C, 0xE5320003, - 0x81C, 0xC8340003, - 0x81C, 0xC7360003, - 0x81C, 0xC6380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xC0440003, - 0x81C, 0xA3460003, - 0x81C, 0xA2480003, - 0x81C, 0xA14A0003, - 0x81C, 0xA04C0003, - 0x81C, 0x824E0003, - 0x81C, 0x81500003, - 0x81C, 0x80520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x445A0003, - 0x81C, 0x435C0003, - 0x81C, 0x425E0003, - 0x81C, 0x41600003, - 0x81C, 0x40620003, - 0x81C, 0x05640003, - 0x81C, 0x04660003, - 0x81C, 0x03680003, - 0x81C, 0x026A0003, - 0x81C, 0x016C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, - 0x81C, 0x00720003, - 0x81C, 0x00740003, - 0x81C, 0x00760003, - 0x81C, 0x00780003, - 0x81C, 0x007A0003, - 0x81C, 0x007C0003, - 0x81C, 0x007E0003, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000003, - 0x81C, 0xF5000003, - 0x81C, 0xF4020003, - 0x81C, 0xF3040003, - 0x81C, 0xF2060003, - 0x81C, 0xF1080003, - 0x81C, 0xF00A0003, - 0x81C, 0xEF0C0003, - 0x81C, 0xEE0E0003, - 0x81C, 0xED100003, - 0x81C, 0xEC120003, - 0x81C, 0xEB140003, - 0x81C, 0xEA160003, - 0x81C, 0xE9180003, - 0x81C, 0xE81A0003, - 0x81C, 0xE71C0003, - 0x81C, 0xE61E0003, - 0x81C, 0xE5200003, - 0x81C, 0xE4220003, - 0x81C, 0xE3240003, - 0x81C, 0xE2260003, - 0x81C, 0xE1280003, - 0x81C, 0xE02A0003, - 0x81C, 0xC32C0003, - 0x81C, 0xC22E0003, - 0x81C, 0xC1300003, - 0x81C, 0xC0320003, - 0x81C, 0xA4340003, - 0x81C, 0xA3360003, - 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0x81C, 0xFC020103, - 0x81C, 0xFB040103, - 0x81C, 0xFA060103, - 0x81C, 0xF9080103, - 0x81C, 0xF80A0103, - 0x81C, 0xF70C0103, - 0x81C, 0xF60E0103, - 0x81C, 0xF5100103, - 0x81C, 0xF4120103, - 0x81C, 0xF3140103, - 0x81C, 0xF2160103, - 0x81C, 0xF1180103, - 0x81C, 0xF01A0103, - 0x81C, 0xEE1C0103, - 0x81C, 0xED1E0103, - 0x81C, 0xEC200103, - 0x81C, 0xEB220103, - 0x81C, 0xEA240103, - 0x81C, 0xE9260103, - 0x81C, 0xE8280103, - 0x81C, 0xE72A0103, - 0x81C, 0xE62C0103, - 0x81C, 0xE52E0103, - 0x81C, 0xE4300103, - 0x81C, 0xE3320103, - 0x81C, 0xE2340103, - 0x81C, 0xC5360103, - 0x81C, 0xC4380103, - 0x81C, 0xC33A0103, - 0x81C, 0xC23C0103, - 0x81C, 0xA53E0103, - 0x81C, 0xA4400103, - 0x81C, 0xA3420103, - 0x81C, 0xA2440103, - 0x81C, 0xA1460103, - 0x81C, 0x83480103, - 0x81C, 0x824A0103, - 0x81C, 0x814C0103, - 0x81C, 0x804E0103, - 0x81C, 0x63500103, - 0x81C, 0x62520103, - 0x81C, 0x61540103, - 0x81C, 0x43560103, - 0x81C, 0x42580103, - 0x81C, 0x415A0103, - 0x81C, 0x405C0103, - 0x81C, 0x225E0103, - 0x81C, 0x21600103, - 0x81C, 0x20620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xC32C0103, - 0x81C, 0xC22E0103, - 0x81C, 0xC1300103, - 0x81C, 0xC0320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0xA03A0103, - 0x81C, 0x823C0103, - 0x81C, 0x813E0103, - 0x81C, 0x80400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 0x81C, 0x424A0103, - 0x81C, 0x414C0103, - 0x81C, 0x404E0103, - 0x81C, 0x06500103, - 0x81C, 0x05520103, - 0x81C, 0x04540103, - 0x81C, 0x03560103, - 0x81C, 0x02580103, - 0x81C, 0x015A0103, - 0x81C, 0x005C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xC32C0103, - 0x81C, 0xC22E0103, - 0x81C, 0xC1300103, - 0x81C, 0xC0320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0xA03A0103, - 0x81C, 0x823C0103, - 0x81C, 0x813E0103, - 0x81C, 0x80400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 0x81C, 0x424A0103, - 0x81C, 0x414C0103, - 0x81C, 0x404E0103, - 0x81C, 0x22500103, - 0x81C, 0x21520103, - 0x81C, 0x20540103, - 0x81C, 0x03560103, - 0x81C, 0x02580103, - 0x81C, 0x015A0103, - 0x81C, 0x005C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000103, - 0x81C, 0xFD020103, - 0x81C, 0xFC040103, - 0x81C, 0xFB060103, - 0x81C, 0xFA080103, - 0x81C, 0xF90A0103, - 0x81C, 0xF80C0103, - 0x81C, 0xF70E0103, - 0x81C, 0xF6100103, - 0x81C, 0xF5120103, - 0x81C, 0xF4140103, - 0x81C, 0xF3160103, - 0x81C, 0xF2180103, - 0x81C, 0xF11A0103, - 0x81C, 0xF01C0103, - 0x81C, 0xEF1E0103, - 0x81C, 0xEE200103, - 0x81C, 0xED220103, - 0x81C, 0xEC240103, - 0x81C, 0xEB260103, - 0x81C, 0xEA280103, - 0x81C, 0xE92A0103, - 0x81C, 0xE82C0103, - 0x81C, 0xE72E0103, - 0x81C, 0xE6300103, - 0x81C, 0xE5320103, - 0x81C, 0xE4340103, - 0x81C, 0xE3360103, - 0x81C, 0xC6380103, - 0x81C, 0xC53A0103, - 0x81C, 0xC43C0103, - 0x81C, 0xC33E0103, - 0x81C, 0xA5400103, - 0x81C, 0xA4420103, - 0x81C, 0xA3440103, - 0x81C, 0xA2460103, - 0x81C, 0xA1480103, - 0x81C, 0xA04A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x80500103, - 0x81C, 0x64520103, - 0x81C, 0x63540103, - 0x81C, 0x62560103, - 0x81C, 0x61580103, - 0x81C, 0x605A0103, - 0x81C, 0x235C0103, - 0x81C, 0x225E0103, - 0x81C, 0x21600103, - 0x81C, 0x20620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xC32C0103, - 0x81C, 0xC22E0103, - 0x81C, 0xC1300103, - 0x81C, 0xC0320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0xA03A0103, - 0x81C, 0x823C0103, - 0x81C, 0x813E0103, - 0x81C, 0x80400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 0x81C, 0x424A0103, - 0x81C, 0x414C0103, - 0x81C, 0x404E0103, - 0x81C, 0x22500103, - 0x81C, 0x21520103, - 0x81C, 0x20540103, - 0x81C, 0x03560103, - 0x81C, 0x02580103, - 0x81C, 0x015A0103, - 0x81C, 0x005C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFD000103, - 0x81C, 0xFC020103, - 0x81C, 0xFB040103, - 0x81C, 0xFA060103, - 0x81C, 0xF9080103, - 0x81C, 0xF80A0103, - 0x81C, 0xF70C0103, - 0x81C, 0xF60E0103, - 0x81C, 0xF5100103, - 0x81C, 0xF4120103, - 0x81C, 0xF3140103, - 0x81C, 0xF2160103, - 0x81C, 0xF1180103, - 0x81C, 0xF01A0103, - 0x81C, 0xEF1C0103, - 0x81C, 0xEE1E0103, - 0x81C, 0xED200103, - 0x81C, 0xEC220103, - 0x81C, 0xEB240103, - 0x81C, 0xEA260103, - 0x81C, 0xE9280103, - 0x81C, 0xE82A0103, - 0x81C, 0xE72C0103, - 0x81C, 0xE62E0103, - 0x81C, 0xE5300103, - 0x81C, 0xE4320103, - 0x81C, 0xE3340103, - 0x81C, 0xE2360103, - 0x81C, 0xC5380103, - 0x81C, 0xC43A0103, - 0x81C, 0xC33C0103, - 0x81C, 0xC23E0103, - 0x81C, 0xA5400103, - 0x81C, 0xA4420103, - 0x81C, 0xA3440103, - 0x81C, 0xA2460103, - 0x81C, 0xA1480103, - 0x81C, 0x834A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x64500103, - 0x81C, 0x63520103, - 0x81C, 0x62540103, - 0x81C, 0x61560103, - 0x81C, 0x42580103, - 0x81C, 0x415A0103, - 0x81C, 0x405C0103, - 0x81C, 0x065E0103, - 0x81C, 0x05600103, - 0x81C, 0x04620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFA000103, - 0x81C, 0xF9020103, - 0x81C, 0xF8040103, - 0x81C, 0xF7060103, - 0x81C, 0xF6080103, - 0x81C, 0xF50A0103, - 0x81C, 0xF40C0103, - 0x81C, 0xF30E0103, - 0x81C, 0xF2100103, - 0x81C, 0xF1120103, - 0x81C, 0xF0140103, - 0x81C, 0xEF160103, - 0x81C, 0xEE180103, - 0x81C, 0xED1A0103, - 0x81C, 0xEC1C0103, - 0x81C, 0xEB1E0103, - 0x81C, 0xEA200103, - 0x81C, 0xE9220103, - 0x81C, 0xE8240103, - 0x81C, 0xE7260103, - 0x81C, 0xE6280103, - 0x81C, 0xE52A0103, - 0x81C, 0xC42C0103, - 0x81C, 0xC32E0103, - 0x81C, 0xC2300103, - 0x81C, 0xC1320103, - 0x81C, 0xA4340103, - 0x81C, 0xA3360103, - 0x81C, 0xA2380103, - 0x81C, 0xA13A0103, - 0x81C, 0x833C0103, - 0x81C, 0x823E0103, - 0x81C, 0x81400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 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0x81C, 0xFD020103, - 0x81C, 0xFC040103, - 0x81C, 0xFB060103, - 0x81C, 0xFA080103, - 0x81C, 0xF90A0103, - 0x81C, 0xF80C0103, - 0x81C, 0xF70E0103, - 0x81C, 0xF6100103, - 0x81C, 0xF5120103, - 0x81C, 0xF4140103, - 0x81C, 0xF3160103, - 0x81C, 0xF2180103, - 0x81C, 0xF11A0103, - 0x81C, 0xF01C0103, - 0x81C, 0xEF1E0103, - 0x81C, 0xEE200103, - 0x81C, 0xED220103, - 0x81C, 0xEC240103, - 0x81C, 0xEB260103, - 0x81C, 0xEA280103, - 0x81C, 0xE92A0103, - 0x81C, 0xE82C0103, - 0x81C, 0xE72E0103, - 0x81C, 0xE6300103, - 0x81C, 0xE5320103, - 0x81C, 0xE4340103, - 0x81C, 0xE3360103, - 0x81C, 0xC6380103, - 0x81C, 0xC53A0103, - 0x81C, 0xC43C0103, - 0x81C, 0xC33E0103, - 0x81C, 0xA5400103, - 0x81C, 0xA4420103, - 0x81C, 0xA3440103, - 0x81C, 0xA2460103, - 0x81C, 0xA1480103, - 0x81C, 0xA04A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x80500103, - 0x81C, 0x64520103, - 0x81C, 0x63540103, - 0x81C, 0x62560103, - 0x81C, 0x61580103, - 0x81C, 0x605A0103, - 0x81C, 0x235C0103, - 0x81C, 0x225E0103, - 0x81C, 0x21600103, - 0x81C, 0x20620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0xA0000000, 0x00000000, - 0x81C, 0xFE000103, - 0x81C, 0xFD020103, - 0x81C, 0xFC040103, - 0x81C, 0xFB060103, - 0x81C, 0xFA080103, - 0x81C, 0xF90A0103, - 0x81C, 0xF80C0103, - 0x81C, 0xF70E0103, - 0x81C, 0xF6100103, - 0x81C, 0xF5120103, - 0x81C, 0xF4140103, - 0x81C, 0xF3160103, - 0x81C, 0xF2180103, - 0x81C, 0xF11A0103, - 0x81C, 0xF01C0103, - 0x81C, 0xEF1E0103, - 0x81C, 0xEE200103, - 0x81C, 0xED220103, - 0x81C, 0xEC240103, - 0x81C, 0xEB260103, - 0x81C, 0xEA280103, - 0x81C, 0xE92A0103, - 0x81C, 0xE82C0103, - 0x81C, 0xE72E0103, - 0x81C, 0xE6300103, - 0x81C, 0xE5320103, - 0x81C, 0xE4340103, - 0x81C, 0xE3360103, - 0x81C, 0xC6380103, - 0x81C, 0xC53A0103, - 0x81C, 0xC43C0103, - 0x81C, 0xC33E0103, - 0x81C, 0xA5400103, - 0x81C, 0xA4420103, - 0x81C, 0xA3440103, - 0x81C, 0xA2460103, - 0x81C, 0xA1480103, - 0x81C, 0xA04A0103, - 0x81C, 0x824C0103, - 0x81C, 0x814E0103, - 0x81C, 0x80500103, - 0x81C, 0x64520103, - 0x81C, 0x63540103, - 0x81C, 0x62560103, - 0x81C, 0x61580103, - 0x81C, 0x605A0103, - 0x81C, 0x235C0103, - 0x81C, 0x225E0103, - 0x81C, 0x21600103, - 0x81C, 0x20620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEE1A0203, - 0x81C, 0xED1C0203, - 0x81C, 0xEC1E0203, - 0x81C, 0xEB200203, - 0x81C, 0xEA220203, - 0x81C, 0xE9240203, - 0x81C, 0xE8260203, - 0x81C, 0xE7280203, - 0x81C, 0xE62A0203, - 0x81C, 0xE52C0203, - 0x81C, 0xE42E0203, - 0x81C, 0xE3300203, - 0x81C, 0xE2320203, - 0x81C, 0xC6340203, - 0x81C, 0xC5360203, - 0x81C, 0xC4380203, - 0x81C, 0xC33A0203, - 0x81C, 0xA63C0203, - 0x81C, 0xA53E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x83480203, - 0x81C, 0x824A0203, - 0x81C, 0x814C0203, - 0x81C, 0x804E0203, - 0x81C, 0x63500203, - 0x81C, 0x62520203, - 0x81C, 0x61540203, - 0x81C, 0x42560203, - 0x81C, 0x41580203, - 0x81C, 0x405A0203, - 0x81C, 0x225C0203, - 0x81C, 0x215E0203, - 0x81C, 0x20600203, - 0x81C, 0x04620203, - 0x81C, 0x03640203, - 0x81C, 0x02660203, - 0x81C, 0x01680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xC42A0203, - 0x81C, 0xC32C0203, - 0x81C, 0xC22E0203, - 0x81C, 0xC1300203, - 0x81C, 0xC0320203, - 0x81C, 0xA3340203, - 0x81C, 0xA2360203, - 0x81C, 0xA1380203, - 0x81C, 0xA03A0203, - 0x81C, 0x823C0203, - 0x81C, 0x813E0203, - 0x81C, 0x80400203, - 0x81C, 0x63420203, - 0x81C, 0x62440203, - 0x81C, 0x61460203, - 0x81C, 0x60480203, - 0x81C, 0x424A0203, - 0x81C, 0x414C0203, - 0x81C, 0x404E0203, - 0x81C, 0x06500203, - 0x81C, 0x05520203, - 0x81C, 0x04540203, - 0x81C, 0x03560203, - 0x81C, 0x02580203, - 0x81C, 0x015A0203, - 0x81C, 0x005C0203, - 0x81C, 0x005E0203, - 0x81C, 0x00600203, - 0x81C, 0x00620203, - 0x81C, 0x00640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xC42A0203, - 0x81C, 0xC32C0203, - 0x81C, 0xC22E0203, - 0x81C, 0xC1300203, - 0x81C, 0xC0320203, - 0x81C, 0xA3340203, - 0x81C, 0xA2360203, - 0x81C, 0xA1380203, - 0x81C, 0xA03A0203, - 0x81C, 0x823C0203, - 0x81C, 0x813E0203, - 0x81C, 0x80400203, - 0x81C, 0x64420203, - 0x81C, 0x63440203, - 0x81C, 0x62460203, - 0x81C, 0x61480203, - 0x81C, 0x604A0203, - 0x81C, 0x414C0203, - 0x81C, 0x404E0203, - 0x81C, 0x22500203, - 0x81C, 0x21520203, - 0x81C, 0x20540203, - 0x81C, 0x03560203, - 0x81C, 0x02580203, - 0x81C, 0x015A0203, - 0x81C, 0x005C0203, - 0x81C, 0x005E0203, - 0x81C, 0x00600203, - 0x81C, 0x00620203, - 0x81C, 0x00640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xC6360203, - 0x81C, 0xC5380203, - 0x81C, 0xC43A0203, - 0x81C, 0xC33C0203, - 0x81C, 0xA63E0203, - 0x81C, 0xA5400203, - 0x81C, 0xA4420203, - 0x81C, 0xA3440203, - 0x81C, 0xA2460203, - 0x81C, 0xA1480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x60580203, - 0x81C, 0x405A0203, - 0x81C, 0x215C0203, - 0x81C, 0x205E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xC42A0203, - 0x81C, 0xC32C0203, - 0x81C, 0xC22E0203, - 0x81C, 0xC1300203, - 0x81C, 0xC0320203, - 0x81C, 0xA3340203, - 0x81C, 0xA2360203, - 0x81C, 0xA1380203, - 0x81C, 0xA03A0203, - 0x81C, 0x823C0203, - 0x81C, 0x813E0203, - 0x81C, 0x80400203, - 0x81C, 0x64420203, - 0x81C, 0x63440203, - 0x81C, 0x62460203, - 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0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEE1A0203, - 0x81C, 0xED1C0203, - 0x81C, 0xEC1E0203, - 0x81C, 0xEB200203, - 0x81C, 0xEA220203, - 0x81C, 0xE9240203, - 0x81C, 0xE8260203, - 0x81C, 0xE7280203, - 0x81C, 0xE62A0203, - 0x81C, 0xE52C0203, - 0x81C, 0xE42E0203, - 0x81C, 0xE3300203, - 0x81C, 0xE2320203, - 0x81C, 0xC6340203, - 0x81C, 0xC5360203, - 0x81C, 0xC4380203, - 0x81C, 0xC33A0203, - 0x81C, 0xA63C0203, - 0x81C, 0xA53E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x83480203, - 0x81C, 0x824A0203, - 0x81C, 0x814C0203, - 0x81C, 0x804E0203, - 0x81C, 0x63500203, - 0x81C, 0x62520203, - 0x81C, 0x61540203, - 0x81C, 0x42560203, - 0x81C, 0x41580203, - 0x81C, 0x405A0203, - 0x81C, 0x225C0203, - 0x81C, 0x215E0203, - 0x81C, 0x20600203, - 0x81C, 0x04620203, - 0x81C, 0x03640203, - 0x81C, 0x02660203, - 0x81C, 0x01680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xE1360203, - 0x81C, 0xE0380203, - 0x81C, 0xC33A0203, - 0x81C, 0xC23C0203, - 0x81C, 0xC13E0203, - 0x81C, 0xA3400203, - 0x81C, 0xA2420203, - 0x81C, 0xA1440203, - 0x81C, 0xA0460203, - 0x81C, 0x83480203, - 0x81C, 0x824A0203, - 0x81C, 0x814C0203, - 0x81C, 0x644E0203, - 0x81C, 0x63500203, - 0x81C, 0x62520203, - 0x81C, 0x61540203, - 0x81C, 0x42560203, - 0x81C, 0x41580203, - 0x81C, 0x235A0203, - 0x81C, 0x225C0203, - 0x81C, 0x215E0203, - 0x81C, 0x04600203, - 0x81C, 0x03620203, - 0x81C, 0x02640203, - 0x81C, 0x01660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000203, - 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xC6360203, - 0x81C, 0xC5380203, - 0x81C, 0xC43A0203, - 0x81C, 0xC33C0203, - 0x81C, 0xA63E0203, - 0x81C, 0xA5400203, - 0x81C, 0xA4420203, - 0x81C, 0xA3440203, - 0x81C, 0xA2460203, - 0x81C, 0xA1480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x60580203, - 0x81C, 0x405A0203, - 0x81C, 0x215C0203, - 0x81C, 0x205E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0xA0000000, 0x00000000, - 0x81C, 0xFD000203, - 0x81C, 0xFC020203, - 0x81C, 0xFB040203, - 0x81C, 0xFA060203, - 0x81C, 0xF9080203, - 0x81C, 0xF80A0203, - 0x81C, 0xF70C0203, - 0x81C, 0xF60E0203, - 0x81C, 0xF5100203, - 0x81C, 0xF4120203, - 0x81C, 0xF3140203, - 0x81C, 0xF2160203, - 0x81C, 0xF1180203, - 0x81C, 0xF01A0203, - 0x81C, 0xEF1C0203, - 0x81C, 0xEE1E0203, - 0x81C, 0xED200203, - 0x81C, 0xEC220203, - 0x81C, 0xEB240203, - 0x81C, 0xEA260203, - 0x81C, 0xE9280203, - 0x81C, 0xE82A0203, - 0x81C, 0xE72C0203, - 0x81C, 0xE62E0203, - 0x81C, 0xE5300203, - 0x81C, 0xE4320203, - 0x81C, 0xE3340203, - 0x81C, 0xC6360203, - 0x81C, 0xC5380203, - 0x81C, 0xC43A0203, - 0x81C, 0xC33C0203, - 0x81C, 0xA63E0203, - 0x81C, 0xA5400203, - 0x81C, 0xA4420203, - 0x81C, 0xA3440203, - 0x81C, 0xA2460203, - 0x81C, 0xA1480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x60580203, - 0x81C, 0x235A0203, - 0x81C, 0x225C0203, - 0x81C, 0x215E0203, - 0x81C, 0x20600203, - 0x81C, 0x03620203, - 0x81C, 0x02640203, - 0x81C, 0x01660203, - 0x81C, 0x00680203, - 0x81C, 0x006A0203, - 0x81C, 0x006C0203, - 0x81C, 0x006E0203, - 0x81C, 0x00700203, - 0x81C, 0x00720203, - 0x81C, 0x00740203, - 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000303, - 0x81C, 0xFB020303, - 0x81C, 0xFA040303, - 0x81C, 0xF9060303, - 0x81C, 0xF8080303, - 0x81C, 0xF70A0303, - 0x81C, 0xF60C0303, - 0x81C, 0xF50E0303, - 0x81C, 0xF4100303, - 0x81C, 0xF3120303, - 0x81C, 0xF2140303, - 0x81C, 0xF1160303, - 0x81C, 0xEF180303, - 0x81C, 0xEE1A0303, - 0x81C, 0xED1C0303, - 0x81C, 0xEC1E0303, - 0x81C, 0xEB200303, - 0x81C, 0xEA220303, - 0x81C, 0xE9240303, - 0x81C, 0xE8260303, - 0x81C, 0xE7280303, - 0x81C, 0xE62A0303, - 0x81C, 0xE52C0303, - 0x81C, 0xE42E0303, - 0x81C, 0xE3300303, - 0x81C, 0xE2320303, - 0x81C, 0xC6340303, - 0x81C, 0xC5360303, - 0x81C, 0xC4380303, - 0x81C, 0xC33A0303, - 0x81C, 0xA63C0303, - 0x81C, 0xA53E0303, - 0x81C, 0xA4400303, - 0x81C, 0xA3420303, - 0x81C, 0xA2440303, - 0x81C, 0xA1460303, - 0x81C, 0x83480303, - 0x81C, 0x824A0303, - 0x81C, 0x814C0303, - 0x81C, 0x804E0303, - 0x81C, 0x63500303, - 0x81C, 0x62520303, - 0x81C, 0x61540303, - 0x81C, 0x42560303, - 0x81C, 0x41580303, - 0x81C, 0x405A0303, - 0x81C, 0x225C0303, - 0x81C, 0x215E0303, - 0x81C, 0x20600303, - 0x81C, 0x04620303, - 0x81C, 0x03640303, - 0x81C, 0x02660303, - 0x81C, 0x01680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xCA1E0303, - 0x81C, 0xC9200303, - 0x81C, 0xC8220303, - 0x81C, 0xC7240303, - 0x81C, 0xC6260303, - 0x81C, 0xC5280303, - 0x81C, 0xC42A0303, - 0x81C, 0xC32C0303, - 0x81C, 0xC22E0303, - 0x81C, 0xC1300303, - 0x81C, 0xA4320303, - 0x81C, 0xA3340303, - 0x81C, 0xA2360303, - 0x81C, 0xA1380303, - 0x81C, 0xA03A0303, - 0x81C, 0x823C0303, - 0x81C, 0x813E0303, - 0x81C, 0x80400303, - 0x81C, 0x64420303, - 0x81C, 0x63440303, - 0x81C, 0x62460303, - 0x81C, 0x61480303, - 0x81C, 0x604A0303, - 0x81C, 0x414C0303, - 0x81C, 0x404E0303, - 0x81C, 0x06500303, - 0x81C, 0x05520303, - 0x81C, 0x04540303, - 0x81C, 0x03560303, - 0x81C, 0x02580303, - 0x81C, 0x015A0303, - 0x81C, 0x005C0303, - 0x81C, 0x005E0303, - 0x81C, 0x00600303, - 0x81C, 0x00620303, - 0x81C, 0x00640303, - 0x81C, 0x00660303, - 0x81C, 0x00680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xCA1E0303, - 0x81C, 0xC9200303, - 0x81C, 0xC8220303, - 0x81C, 0xC7240303, - 0x81C, 0xC6260303, - 0x81C, 0xC5280303, - 0x81C, 0xC42A0303, - 0x81C, 0xC32C0303, - 0x81C, 0xC22E0303, - 0x81C, 0xC1300303, - 0x81C, 0xA4320303, - 0x81C, 0xA3340303, - 0x81C, 0xA2360303, - 0x81C, 0xA1380303, - 0x81C, 0xA03A0303, - 0x81C, 0x823C0303, - 0x81C, 0x813E0303, - 0x81C, 0x80400303, - 0x81C, 0x64420303, - 0x81C, 0x63440303, - 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0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x00660303, - 0x81C, 0x00680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000303, - 0x81C, 0xFA020303, - 0x81C, 0xF9040303, - 0x81C, 0xF8060303, - 0x81C, 0xF7080303, - 0x81C, 0xF60A0303, - 0x81C, 0xF50C0303, - 0x81C, 0xF40E0303, - 0x81C, 0xF3100303, - 0x81C, 0xF2120303, - 0x81C, 0xF1140303, - 0x81C, 0xEF160303, - 0x81C, 0xEE180303, - 0x81C, 0xED1A0303, - 0x81C, 0xEC1C0303, - 0x81C, 0xEB1E0303, - 0x81C, 0xEA200303, - 0x81C, 0xE9220303, - 0x81C, 0xE8240303, - 0x81C, 0xE7260303, - 0x81C, 0xE6280303, - 0x81C, 0xE52A0303, - 0x81C, 0xE42C0303, - 0x81C, 0xE32E0303, - 0x81C, 0xE2300303, - 0x81C, 0xE1320303, - 0x81C, 0xC6340303, - 0x81C, 0xC5360303, - 0x81C, 0xC4380303, - 0x81C, 0xC33A0303, - 0x81C, 0xA63C0303, - 0x81C, 0xA53E0303, - 0x81C, 0xA4400303, - 0x81C, 0xA3420303, - 0x81C, 0xA2440303, - 0x81C, 0xA1460303, - 0x81C, 0x83480303, - 0x81C, 0x824A0303, - 0x81C, 0x814C0303, - 0x81C, 0x804E0303, - 0x81C, 0x63500303, - 0x81C, 0x62520303, - 0x81C, 0x61540303, - 0x81C, 0x42560303, - 0x81C, 0x41580303, - 0x81C, 0x405A0303, - 0x81C, 0x225C0303, - 0x81C, 0x215E0303, - 0x81C, 0x20600303, - 0x81C, 0x04620303, - 0x81C, 0x03640303, - 0x81C, 0x02660303, - 0x81C, 0x01680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000303, - 0x81C, 0xFA020303, - 0x81C, 0xF9040303, - 0x81C, 0xF8060303, - 0x81C, 0xF7080303, - 0x81C, 0xF60A0303, - 0x81C, 0xF50C0303, - 0x81C, 0xF40E0303, - 0x81C, 0xF3100303, - 0x81C, 0xF2120303, - 0x81C, 0xF1140303, - 0x81C, 0xEF160303, - 0x81C, 0xEE180303, - 0x81C, 0xED1A0303, - 0x81C, 0xEC1C0303, - 0x81C, 0xEB1E0303, - 0x81C, 0xEA200303, - 0x81C, 0xE9220303, - 0x81C, 0xE8240303, - 0x81C, 0xE7260303, - 0x81C, 0xE6280303, - 0x81C, 0xE52A0303, - 0x81C, 0xE42C0303, - 0x81C, 0xE32E0303, - 0x81C, 0xE2300303, - 0x81C, 0xE1320303, - 0x81C, 0xC6340303, - 0x81C, 0xC5360303, - 0x81C, 0xC4380303, - 0x81C, 0xC33A0303, - 0x81C, 0xA63C0303, - 0x81C, 0xA53E0303, - 0x81C, 0xA4400303, - 0x81C, 0xA3420303, - 0x81C, 0xA2440303, - 0x81C, 0xA1460303, - 0x81C, 0x83480303, - 0x81C, 0x824A0303, - 0x81C, 0x814C0303, - 0x81C, 0x804E0303, - 0x81C, 0x63500303, - 0x81C, 0x62520303, - 0x81C, 0x61540303, - 0x81C, 0x42560303, - 0x81C, 0x41580303, - 0x81C, 0x405A0303, - 0x81C, 0x225C0303, - 0x81C, 0x215E0303, - 0x81C, 0x20600303, - 0x81C, 0x04620303, - 0x81C, 0x03640303, - 0x81C, 0x02660303, - 0x81C, 0x01680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000303, - 0x81C, 0xFA020303, - 0x81C, 0xF9040303, - 0x81C, 0xF8060303, - 0x81C, 0xF7080303, - 0x81C, 0xF60A0303, - 0x81C, 0xF50C0303, - 0x81C, 0xF40E0303, - 0x81C, 0xF3100303, - 0x81C, 0xF2120303, - 0x81C, 0xF1140303, - 0x81C, 0xF0160303, - 0x81C, 0xEF180303, - 0x81C, 0xEE1A0303, - 0x81C, 0xED1C0303, - 0x81C, 0xEC1E0303, - 0x81C, 0xEB200303, - 0x81C, 0xEA220303, - 0x81C, 0xE9240303, - 0x81C, 0xE8260303, - 0x81C, 0xE7280303, - 0x81C, 0xE62A0303, - 0x81C, 0xE52C0303, - 0x81C, 0xE42E0303, - 0x81C, 0xE3300303, - 0x81C, 0xE2320303, - 0x81C, 0xE1340303, - 0x81C, 0xE0360303, - 0x81C, 0xC3380303, - 0x81C, 0xC23A0303, - 0x81C, 0xC13C0303, - 0x81C, 0xC03E0303, - 0x81C, 0xA3400303, - 0x81C, 0xA2420303, - 0x81C, 0xA1440303, - 0x81C, 0xA0460303, - 0x81C, 0x83480303, - 0x81C, 0x824A0303, - 0x81C, 0x814C0303, - 0x81C, 0x644E0303, - 0x81C, 0x63500303, - 0x81C, 0x62520303, - 0x81C, 0x61540303, - 0x81C, 0x24560303, - 0x81C, 0x23580303, - 0x81C, 0x225A0303, - 0x81C, 0x215C0303, - 0x81C, 0x055E0303, - 0x81C, 0x04600303, - 0x81C, 0x03620303, - 0x81C, 0x02640303, - 0x81C, 0x01660303, - 0x81C, 0x00680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000303, - 0x81C, 0xFB020303, - 0x81C, 0xFA040303, - 0x81C, 0xF9060303, - 0x81C, 0xF8080303, - 0x81C, 0xF70A0303, - 0x81C, 0xF60C0303, - 0x81C, 0xF50E0303, - 0x81C, 0xF4100303, - 0x81C, 0xF3120303, - 0x81C, 0xF2140303, - 0x81C, 0xF1160303, - 0x81C, 0xF0180303, - 0x81C, 0xEF1A0303, - 0x81C, 0xEE1C0303, - 0x81C, 0xED1E0303, - 0x81C, 0xEC200303, - 0x81C, 0xEB220303, - 0x81C, 0xEA240303, - 0x81C, 0xE9260303, - 0x81C, 0xE8280303, - 0x81C, 0xE72A0303, - 0x81C, 0xE62C0303, - 0x81C, 0xE52E0303, - 0x81C, 0xE4300303, - 0x81C, 0xE3320303, - 0x81C, 0xE2340303, - 0x81C, 0xC6360303, - 0x81C, 0xC5380303, - 0x81C, 0xC43A0303, - 0x81C, 0xC33C0303, - 0x81C, 0xA63E0303, - 0x81C, 0xA5400303, - 0x81C, 0xA4420303, - 0x81C, 0xA3440303, - 0x81C, 0xA2460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x80500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x60580303, - 0x81C, 0x225A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x00660303, - 0x81C, 0x00680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0xA0000000, 0x00000000, - 0x81C, 0xFC000303, - 0x81C, 0xFB020303, - 0x81C, 0xFA040303, - 0x81C, 0xF9060303, - 0x81C, 0xF8080303, - 0x81C, 0xF70A0303, - 0x81C, 0xF60C0303, - 0x81C, 0xF50E0303, - 0x81C, 0xF4100303, - 0x81C, 0xF3120303, - 0x81C, 0xF2140303, - 0x81C, 0xF1160303, - 0x81C, 0xF0180303, - 0x81C, 0xEF1A0303, - 0x81C, 0xEE1C0303, - 0x81C, 0xED1E0303, - 0x81C, 0xEC200303, - 0x81C, 0xEB220303, - 0x81C, 0xEA240303, - 0x81C, 0xE9260303, - 0x81C, 0xE8280303, - 0x81C, 0xE72A0303, - 0x81C, 0xE62C0303, - 0x81C, 0xE52E0303, - 0x81C, 0xE4300303, - 0x81C, 0xE3320303, - 0x81C, 0xE2340303, - 0x81C, 0xC6360303, - 0x81C, 0xC5380303, - 0x81C, 0xC43A0303, - 0x81C, 0xC33C0303, - 0x81C, 0xA63E0303, - 0x81C, 0xA5400303, - 0x81C, 0xA4420303, - 0x81C, 0xA3440303, - 0x81C, 0xA2460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x80500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x60580303, - 0x81C, 0x235A0303, - 0x81C, 0x225C0303, - 0x81C, 0x215E0303, - 0x81C, 0x20600303, - 0x81C, 0x03620303, - 0x81C, 0x02640303, - 0x81C, 0x01660303, - 0x81C, 0x00680303, - 0x81C, 0x006A0303, - 0x81C, 0x006C0303, - 0x81C, 0x006E0303, - 0x81C, 0x00700303, - 0x81C, 0x00720303, - 0x81C, 0x00740303, - 0x81C, 0x00760303, - 0x81C, 0x00780303, - 0x81C, 0x007A0303, - 0x81C, 0x007C0303, - 0x81C, 0x007E0303, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF5000403, - 0x81C, 0xF4020403, - 0x81C, 0xF3040403, - 0x81C, 0xF2060403, - 0x81C, 0xF1080403, - 0x81C, 0xF00A0403, - 0x81C, 0xEF0C0403, - 0x81C, 0xEE0E0403, - 0x81C, 0xED100403, - 0x81C, 0xEC120403, - 0x81C, 0xEB140403, - 0x81C, 0xEA160403, - 0x81C, 0xE9180403, - 0x81C, 0xE81A0403, - 0x81C, 0xE71C0403, - 0x81C, 0xE61E0403, - 0x81C, 0xE5200403, - 0x81C, 0xE4220403, - 0x81C, 0xE3240403, - 0x81C, 0xE2260403, - 0x81C, 0xE1280403, - 0x81C, 0xE02A0403, - 0x81C, 0xC32C0403, - 0x81C, 0xC22E0403, - 0x81C, 0xC1300403, - 0x81C, 0xC0320403, - 0x81C, 0xA4340403, - 0x81C, 0xA3360403, - 0x81C, 0xA2380403, - 0x81C, 0xA13A0403, - 0x81C, 0xA03C0403, - 0x81C, 0x823E0403, - 0x81C, 0x81400403, - 0x81C, 0x80420403, - 0x81C, 0x64440403, - 0x81C, 0x63460403, - 0x81C, 0x62480403, - 0x81C, 0x614A0403, - 0x81C, 0x604C0403, - 0x81C, 0x454E0403, - 0x81C, 0x44500403, - 0x81C, 0x43520403, - 0x81C, 0x42540403, - 0x81C, 0x41560403, - 0x81C, 0x40580403, - 0x81C, 0x055A0403, - 0x81C, 0x045C0403, - 0x81C, 0x035E0403, - 0x81C, 0x02600403, - 0x81C, 0x01620403, - 0x81C, 0x00640403, - 0x81C, 0x00660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF6000403, - 0x81C, 0xF5020403, - 0x81C, 0xF4040403, - 0x81C, 0xF3060403, - 0x81C, 0xF2080403, - 0x81C, 0xF10A0403, - 0x81C, 0xF00C0403, - 0x81C, 0xEF0E0403, - 0x81C, 0xD6100403, - 0x81C, 0xD5120403, - 0x81C, 0xD4140403, - 0x81C, 0xD3160403, - 0x81C, 0xD2180403, - 0x81C, 0xD11A0403, - 0x81C, 0xD01C0403, - 0x81C, 0xCF1E0403, - 0x81C, 0x95200403, - 0x81C, 0x94220403, - 0x81C, 0x93240403, - 0x81C, 0x92260403, - 0x81C, 0x91280403, - 0x81C, 0x902A0403, - 0x81C, 0x8F2C0403, - 0x81C, 0x8E2E0403, - 0x81C, 0x8D300403, - 0x81C, 0x8C320403, - 0x81C, 0x8B340403, - 0x81C, 0x8A360403, - 0x81C, 0x89380403, - 0x81C, 0x883A0403, - 0x81C, 0x873C0403, - 0x81C, 0x863E0403, - 0x81C, 0x68400403, - 0x81C, 0x67420403, - 0x81C, 0x66440403, - 0x81C, 0x65460403, - 0x81C, 0x64480403, - 0x81C, 0x634A0403, - 0x81C, 0x484C0403, - 0x81C, 0x474E0403, - 0x81C, 0x46500403, - 0x81C, 0x45520403, - 0x81C, 0x44540403, - 0x81C, 0x27560403, - 0x81C, 0x26580403, - 0x81C, 0x255A0403, - 0x81C, 0x245C0403, - 0x81C, 0x235E0403, - 0x81C, 0x04600403, - 0x81C, 0x03620403, - 0x81C, 0x02640403, - 0x81C, 0x01660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF5000403, - 0x81C, 0xF4020403, - 0x81C, 0xF3040403, - 0x81C, 0xF2060403, - 0x81C, 0xF1080403, - 0x81C, 0xF00A0403, - 0x81C, 0xEF0C0403, - 0x81C, 0xEE0E0403, - 0x81C, 0xED100403, - 0x81C, 0xEC120403, - 0x81C, 0xEB140403, - 0x81C, 0xEA160403, - 0x81C, 0xE9180403, - 0x81C, 0xE81A0403, - 0x81C, 0xE71C0403, - 0x81C, 0xE61E0403, - 0x81C, 0xE5200403, - 0x81C, 0xE4220403, - 0x81C, 0xE3240403, - 0x81C, 0xE2260403, - 0x81C, 0xE1280403, - 0x81C, 0xE02A0403, - 0x81C, 0xC32C0403, - 0x81C, 0xC22E0403, - 0x81C, 0xC1300403, - 0x81C, 0xC0320403, - 0x81C, 0xA4340403, - 0x81C, 0xA3360403, - 0x81C, 0xA2380403, - 0x81C, 0xA13A0403, - 0x81C, 0xA03C0403, - 0x81C, 0x823E0403, - 0x81C, 0x81400403, - 0x81C, 0x80420403, - 0x81C, 0x64440403, - 0x81C, 0x63460403, - 0x81C, 0x62480403, - 0x81C, 0x614A0403, - 0x81C, 0x604C0403, - 0x81C, 0x454E0403, - 0x81C, 0x44500403, - 0x81C, 0x43520403, - 0x81C, 0x42540403, - 0x81C, 0x41560403, - 0x81C, 0x40580403, - 0x81C, 0x055A0403, - 0x81C, 0x045C0403, - 0x81C, 0x035E0403, - 0x81C, 0x02600403, - 0x81C, 0x01620403, - 0x81C, 0x00640403, - 0x81C, 0x00660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF5000403, - 0x81C, 0xF4020403, - 0x81C, 0xF3040403, - 0x81C, 0xF2060403, - 0x81C, 0xF1080403, - 0x81C, 0xF00A0403, - 0x81C, 0xEF0C0403, - 0x81C, 0xEE0E0403, - 0x81C, 0xED100403, - 0x81C, 0xEC120403, - 0x81C, 0xEB140403, - 0x81C, 0xEA160403, - 0x81C, 0xE9180403, - 0x81C, 0xE81A0403, - 0x81C, 0xE71C0403, - 0x81C, 0xE61E0403, - 0x81C, 0xE5200403, - 0x81C, 0xE4220403, - 0x81C, 0xE3240403, - 0x81C, 0xE2260403, - 0x81C, 0xE1280403, - 0x81C, 0xE02A0403, - 0x81C, 0xC32C0403, - 0x81C, 0xC22E0403, - 0x81C, 0xC1300403, - 0x81C, 0xC0320403, - 0x81C, 0xA4340403, - 0x81C, 0xA3360403, - 0x81C, 0xA2380403, - 0x81C, 0xA13A0403, - 0x81C, 0xA03C0403, - 0x81C, 0x823E0403, - 0x81C, 0x81400403, - 0x81C, 0x80420403, - 0x81C, 0x64440403, - 0x81C, 0x63460403, - 0x81C, 0x62480403, - 0x81C, 0x614A0403, - 0x81C, 0x604C0403, - 0x81C, 0x454E0403, - 0x81C, 0x44500403, - 0x81C, 0x43520403, - 0x81C, 0x42540403, - 0x81C, 0x41560403, - 0x81C, 0x40580403, - 0x81C, 0x055A0403, - 0x81C, 0x045C0403, - 0x81C, 0x035E0403, - 0x81C, 0x02600403, - 0x81C, 0x01620403, - 0x81C, 0x00640403, - 0x81C, 0x00660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF5000403, - 0x81C, 0xF4020403, - 0x81C, 0xF3040403, - 0x81C, 0xF2060403, - 0x81C, 0xF1080403, - 0x81C, 0xF00A0403, - 0x81C, 0xEF0C0403, - 0x81C, 0xEE0E0403, - 0x81C, 0xED100403, - 0x81C, 0xEC120403, - 0x81C, 0xEB140403, - 0x81C, 0xEA160403, - 0x81C, 0xE9180403, - 0x81C, 0xE81A0403, - 0x81C, 0xE71C0403, - 0x81C, 0xE61E0403, - 0x81C, 0xE5200403, - 0x81C, 0xE4220403, - 0x81C, 0xE3240403, - 0x81C, 0xE2260403, - 0x81C, 0xE1280403, - 0x81C, 0xE02A0403, - 0x81C, 0xC32C0403, - 0x81C, 0xC22E0403, - 0x81C, 0xC1300403, - 0x81C, 0xC0320403, - 0x81C, 0xA4340403, - 0x81C, 0xA3360403, - 0x81C, 0xA2380403, - 0x81C, 0xA13A0403, - 0x81C, 0xA03C0403, - 0x81C, 0x823E0403, - 0x81C, 0x81400403, - 0x81C, 0x80420403, - 0x81C, 0x64440403, - 0x81C, 0x63460403, - 0x81C, 0x62480403, - 0x81C, 0x614A0403, - 0x81C, 0x604C0403, - 0x81C, 0x454E0403, - 0x81C, 0x44500403, - 0x81C, 0x43520403, - 0x81C, 0x42540403, - 0x81C, 0x41560403, - 0x81C, 0x40580403, - 0x81C, 0x055A0403, - 0x81C, 0x045C0403, - 0x81C, 0x035E0403, - 0x81C, 0x02600403, - 0x81C, 0x01620403, - 0x81C, 0x00640403, - 0x81C, 0x00660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000a, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000b, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xF5000403, - 0x81C, 0xF4020403, - 0x81C, 0xF3040403, - 0x81C, 0xF2060403, - 0x81C, 0xF1080403, - 0x81C, 0xF00A0403, - 0x81C, 0xEF0C0403, - 0x81C, 0xEE0E0403, - 0x81C, 0xED100403, - 0x81C, 0xEC120403, - 0x81C, 0xEB140403, - 0x81C, 0xEA160403, - 0x81C, 0xE9180403, - 0x81C, 0xE81A0403, - 0x81C, 0xE71C0403, - 0x81C, 0xE61E0403, - 0x81C, 0xE5200403, - 0x81C, 0xE4220403, - 0x81C, 0xE3240403, - 0x81C, 0xE2260403, - 0x81C, 0xE1280403, - 0x81C, 0xE02A0403, - 0x81C, 0xC32C0403, - 0x81C, 0xC22E0403, - 0x81C, 0xC1300403, - 0x81C, 0xC0320403, - 0x81C, 0xA4340403, - 0x81C, 0xA3360403, - 0x81C, 0xA2380403, - 0x81C, 0xA13A0403, - 0x81C, 0xA03C0403, - 0x81C, 0x823E0403, - 0x81C, 0x81400403, - 0x81C, 0x80420403, - 0x81C, 0x64440403, - 0x81C, 0x63460403, - 0x81C, 0x62480403, - 0x81C, 0x614A0403, - 0x81C, 0x604C0403, - 0x81C, 0x454E0403, - 0x81C, 0x44500403, - 0x81C, 0x43520403, - 0x81C, 0x42540403, - 0x81C, 0x41560403, - 0x81C, 0x40580403, - 0x81C, 0x055A0403, - 0x81C, 0x045C0403, - 0x81C, 0x035E0403, - 0x81C, 0x02600403, - 0x81C, 0x01620403, - 0x81C, 0x00640403, - 0x81C, 0x00660403, - 0x81C, 0x00680403, - 0x81C, 0x006A0403, - 0x81C, 0x006C0403, - 0x81C, 0x006E0403, - 0x81C, 0x00700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0xA0000000, 0x00000000, - 0x81C, 0xFF000403, - 0x81C, 0xFF000403, - 0x81C, 0xFF020403, - 0x81C, 0xFE040403, - 0x81C, 0xFD060403, - 0x81C, 0xFC080403, - 0x81C, 0xFB0A0403, - 0x81C, 0xFA0C0403, - 0x81C, 0xF90E0403, - 0x81C, 0xF8100403, - 0x81C, 0xF7120403, - 0x81C, 0xF6140403, - 0x81C, 0xF5160403, - 0x81C, 0xF4180403, - 0x81C, 0xF31A0403, - 0x81C, 0xF21C0403, - 0x81C, 0xD51E0403, - 0x81C, 0xD4200403, - 0x81C, 0xD3220403, - 0x81C, 0xD2240403, - 0x81C, 0xB6260403, - 0x81C, 0xB5280403, - 0x81C, 0xB42A0403, - 0x81C, 0xB32C0403, - 0x81C, 0xB22E0403, - 0x81C, 0xB1300403, - 0x81C, 0xB0320403, - 0x81C, 0xAF340403, - 0x81C, 0xAE360403, - 0x81C, 0xAD380403, - 0x81C, 0xAC3A0403, - 0x81C, 0xAB3C0403, - 0x81C, 0xAA3E0403, - 0x81C, 0xA9400403, - 0x81C, 0xA8420403, - 0x81C, 0xA7440403, - 0x81C, 0xA6460403, - 0x81C, 0xA5480403, - 0x81C, 0xA44A0403, - 0x81C, 0xA34C0403, - 0x81C, 0x854E0403, - 0x81C, 0x84500403, - 0x81C, 0x83520403, - 0x81C, 0x82540403, - 0x81C, 0x81560403, - 0x81C, 0x80580403, - 0x81C, 0x485A0403, - 0x81C, 0x475C0403, - 0x81C, 0x465E0403, - 0x81C, 0x45600403, - 0x81C, 0x44620403, - 0x81C, 0x0A640403, - 0x81C, 0x09660403, - 0x81C, 0x08680403, - 0x81C, 0x076A0403, - 0x81C, 0x066C0403, - 0x81C, 0x056E0403, - 0x81C, 0x04700403, - 0x81C, 0x03720403, - 0x81C, 0x02740403, - 0x81C, 0x01760403, - 0x81C, 0x00780403, - 0x81C, 0x007A0403, - 0x81C, 0x007C0403, - 0x81C, 0x007E0403, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFD000503, - 0x81C, 0xFC020503, - 0x81C, 0xFB040503, - 0x81C, 0xFA060503, - 0x81C, 0xF9080503, - 0x81C, 0xF80A0503, - 0x81C, 0xF70C0503, - 0x81C, 0xF60E0503, - 0x81C, 0xF5100503, - 0x81C, 0xF4120503, - 0x81C, 0xF3140503, - 0x81C, 0xF2160503, - 0x81C, 0xF1180503, - 0x81C, 0xF01A0503, - 0x81C, 0xEE1C0503, - 0x81C, 0xED1E0503, - 0x81C, 0xEC200503, - 0x81C, 0xEB220503, - 0x81C, 0xEA240503, - 0x81C, 0xE9260503, - 0x81C, 0xE8280503, - 0x81C, 0xE72A0503, - 0x81C, 0xE62C0503, - 0x81C, 0xE52E0503, - 0x81C, 0xE4300503, - 0x81C, 0xE3320503, - 0x81C, 0xE2340503, - 0x81C, 0xC5360503, - 0x81C, 0xC4380503, - 0x81C, 0xC33A0503, - 0x81C, 0xC23C0503, - 0x81C, 0xA53E0503, - 0x81C, 0xA4400503, - 0x81C, 0xA3420503, - 0x81C, 0xA2440503, - 0x81C, 0xA1460503, - 0x81C, 0x83480503, - 0x81C, 0x824A0503, - 0x81C, 0x814C0503, - 0x81C, 0x804E0503, - 0x81C, 0x63500503, - 0x81C, 0x62520503, - 0x81C, 0x61540503, - 0x81C, 0x43560503, - 0x81C, 0x42580503, - 0x81C, 0x415A0503, - 0x81C, 0x405C0503, - 0x81C, 0x225E0503, - 0x81C, 0x21600503, - 0x81C, 0x20620503, - 0x81C, 0x03640503, - 0x81C, 0x02660503, - 0x81C, 0x01680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBE000503, - 0x81C, 0xBD020503, - 0x81C, 0xBC040503, - 0x81C, 0xBB060503, - 0x81C, 0xBA080503, - 0x81C, 0xB90A0503, - 0x81C, 0xB80C0503, - 0x81C, 0xB70E0503, - 0x81C, 0xB6100503, - 0x81C, 0xB5120503, - 0x81C, 0xB4140503, - 0x81C, 0xB3160503, - 0x81C, 0xB2180503, - 0x81C, 0xB11A0503, - 0x81C, 0xB01C0503, - 0x81C, 0xAF1E0503, - 0x81C, 0xAE200503, - 0x81C, 0xAD220503, - 0x81C, 0xAC240503, - 0x81C, 0xAB260503, - 0x81C, 0x8D280503, - 0x81C, 0x8C2A0503, - 0x81C, 0x8B2C0503, - 0x81C, 0x8A2E0503, - 0x81C, 0x89300503, - 0x81C, 0x88320503, - 0x81C, 0x6A340503, - 0x81C, 0x69360503, - 0x81C, 0x68380503, - 0x81C, 0x673A0503, - 0x81C, 0x663C0503, - 0x81C, 0x653E0503, - 0x81C, 0x64400503, - 0x81C, 0x63420503, - 0x81C, 0x62440503, - 0x81C, 0x61460503, - 0x81C, 0x60480503, - 0x81C, 0x424A0503, - 0x81C, 0x414C0503, - 0x81C, 0x404E0503, - 0x81C, 0x06500503, - 0x81C, 0x05520503, - 0x81C, 0x04540503, - 0x81C, 0x03560503, - 0x81C, 0x02580503, - 0x81C, 0x015A0503, - 0x81C, 0x005C0503, - 0x81C, 0x005E0503, - 0x81C, 0x00600503, - 0x81C, 0x00620503, - 0x81C, 0x00640503, - 0x81C, 0x00660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007C0503, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000503, - 0x81C, 0xF7020503, - 0x81C, 0xF6040503, - 0x81C, 0xF5060503, - 0x81C, 0xF4080503, - 0x81C, 0xF30A0503, - 0x81C, 0xF20C0503, - 0x81C, 0xF10E0503, - 0x81C, 0xF0100503, - 0x81C, 0xEF120503, - 0x81C, 0xEE140503, - 0x81C, 0xED160503, - 0x81C, 0xEC180503, - 0x81C, 0xEB1A0503, - 0x81C, 0xEA1C0503, - 0x81C, 0xE91E0503, - 0x81C, 0xE8200503, - 0x81C, 0xE7220503, - 0x81C, 0xE6240503, - 0x81C, 0xE5260503, - 0x81C, 0xE4280503, - 0x81C, 0xE32A0503, - 0x81C, 0xC32C0503, - 0x81C, 0xC22E0503, - 0x81C, 0xC1300503, - 0x81C, 0xC0320503, - 0x81C, 0xA3340503, - 0x81C, 0xA2360503, - 0x81C, 0xA1380503, - 0x81C, 0xA03A0503, - 0x81C, 0x823C0503, - 0x81C, 0x813E0503, - 0x81C, 0x80400503, - 0x81C, 0x63420503, - 0x81C, 0x62440503, - 0x81C, 0x61460503, - 0x81C, 0x60480503, - 0x81C, 0x424A0503, - 0x81C, 0x414C0503, - 0x81C, 0x404E0503, - 0x81C, 0x22500503, - 0x81C, 0x21520503, - 0x81C, 0x20540503, - 0x81C, 0x03560503, - 0x81C, 0x02580503, - 0x81C, 0x015A0503, - 0x81C, 0x005C0503, - 0x81C, 0x005E0503, - 0x81C, 0x00600503, - 0x81C, 0x00620503, - 0x81C, 0x00640503, - 0x81C, 0x00660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000503, - 0x81C, 0xFD020503, - 0x81C, 0xFC040503, - 0x81C, 0xFB060503, - 0x81C, 0xFA080503, - 0x81C, 0xF90A0503, - 0x81C, 0xF80C0503, - 0x81C, 0xF70E0503, - 0x81C, 0xF6100503, - 0x81C, 0xF5120503, - 0x81C, 0xF4140503, - 0x81C, 0xF3160503, - 0x81C, 0xF2180503, - 0x81C, 0xF11A0503, - 0x81C, 0xF01C0503, - 0x81C, 0xEF1E0503, - 0x81C, 0xEE200503, - 0x81C, 0xED220503, - 0x81C, 0xEC240503, - 0x81C, 0xEB260503, - 0x81C, 0xEA280503, - 0x81C, 0xE92A0503, - 0x81C, 0xE82C0503, - 0x81C, 0xE72E0503, - 0x81C, 0xE6300503, - 0x81C, 0xE5320503, - 0x81C, 0xE4340503, - 0x81C, 0xE3360503, - 0x81C, 0xC6380503, - 0x81C, 0xC53A0503, - 0x81C, 0xC43C0503, - 0x81C, 0xC33E0503, - 0x81C, 0xA5400503, - 0x81C, 0xA4420503, - 0x81C, 0xA3440503, - 0x81C, 0xA2460503, - 0x81C, 0xA1480503, - 0x81C, 0xA04A0503, - 0x81C, 0x824C0503, - 0x81C, 0x814E0503, - 0x81C, 0x80500503, - 0x81C, 0x64520503, - 0x81C, 0x63540503, - 0x81C, 0x62560503, - 0x81C, 0x61580503, - 0x81C, 0x605A0503, - 0x81C, 0x235C0503, - 0x81C, 0x225E0503, - 0x81C, 0x21600503, - 0x81C, 0x20620503, - 0x81C, 0x03640503, - 0x81C, 0x02660503, - 0x81C, 0x01680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000503, - 0x81C, 0xF7020503, - 0x81C, 0xF6040503, - 0x81C, 0xF5060503, - 0x81C, 0xF4080503, - 0x81C, 0xF30A0503, - 0x81C, 0xF20C0503, - 0x81C, 0xF10E0503, - 0x81C, 0xF0100503, - 0x81C, 0xEF120503, - 0x81C, 0xEE140503, - 0x81C, 0xED160503, - 0x81C, 0xEC180503, - 0x81C, 0xEB1A0503, - 0x81C, 0xEA1C0503, - 0x81C, 0xE91E0503, - 0x81C, 0xE8200503, - 0x81C, 0xE7220503, - 0x81C, 0xE6240503, - 0x81C, 0xE5260503, - 0x81C, 0xE4280503, - 0x81C, 0xE32A0503, - 0x81C, 0xC32C0503, - 0x81C, 0xC22E0503, - 0x81C, 0xC1300503, - 0x81C, 0xC0320503, - 0x81C, 0xA3340503, - 0x81C, 0xA2360503, - 0x81C, 0xA1380503, - 0x81C, 0xA03A0503, - 0x81C, 0x823C0503, - 0x81C, 0x813E0503, - 0x81C, 0x80400503, - 0x81C, 0x63420503, - 0x81C, 0x62440503, - 0x81C, 0x61460503, - 0x81C, 0x60480503, - 0x81C, 0x424A0503, - 0x81C, 0x414C0503, - 0x81C, 0x404E0503, - 0x81C, 0x22500503, - 0x81C, 0x21520503, - 0x81C, 0x20540503, - 0x81C, 0x03560503, - 0x81C, 0x02580503, - 0x81C, 0x015A0503, - 0x81C, 0x005C0503, - 0x81C, 0x005E0503, - 0x81C, 0x00600503, - 0x81C, 0x00620503, - 0x81C, 0x00640503, - 0x81C, 0x00660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFD000503, - 0x81C, 0xFC020503, - 0x81C, 0xFB040503, - 0x81C, 0xFA060503, - 0x81C, 0xF9080503, - 0x81C, 0xF80A0503, - 0x81C, 0xF70C0503, - 0x81C, 0xF60E0503, - 0x81C, 0xF5100503, - 0x81C, 0xF4120503, - 0x81C, 0xF3140503, - 0x81C, 0xF2160503, - 0x81C, 0xF1180503, - 0x81C, 0xF01A0503, - 0x81C, 0xEF1C0503, - 0x81C, 0xEE1E0503, - 0x81C, 0xED200503, - 0x81C, 0xEC220503, - 0x81C, 0xEB240503, - 0x81C, 0xEA260503, - 0x81C, 0xE9280503, - 0x81C, 0xE82A0503, - 0x81C, 0xE72C0503, - 0x81C, 0xE62E0503, - 0x81C, 0xE5300503, - 0x81C, 0xE4320503, - 0x81C, 0xE3340503, - 0x81C, 0xE2360503, - 0x81C, 0xC5380503, - 0x81C, 0xC43A0503, - 0x81C, 0xC33C0503, - 0x81C, 0xC23E0503, - 0x81C, 0xA5400503, - 0x81C, 0xA4420503, - 0x81C, 0xA3440503, - 0x81C, 0xA2460503, - 0x81C, 0xA1480503, - 0x81C, 0x834A0503, - 0x81C, 0x824C0503, - 0x81C, 0x814E0503, - 0x81C, 0x64500503, - 0x81C, 0x63520503, - 0x81C, 0x62540503, - 0x81C, 0x61560503, - 0x81C, 0x42580503, - 0x81C, 0x415A0503, - 0x81C, 0x405C0503, - 0x81C, 0x065E0503, - 0x81C, 0x05600503, - 0x81C, 0x04620503, - 0x81C, 0x03640503, - 0x81C, 0x02660503, - 0x81C, 0x01680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFA000503, - 0x81C, 0xF9020503, - 0x81C, 0xF8040503, - 0x81C, 0xF7060503, - 0x81C, 0xF6080503, - 0x81C, 0xF50A0503, - 0x81C, 0xF40C0503, - 0x81C, 0xF30E0503, - 0x81C, 0xF2100503, - 0x81C, 0xF1120503, - 0x81C, 0xF0140503, - 0x81C, 0xEF160503, - 0x81C, 0xEE180503, - 0x81C, 0xED1A0503, - 0x81C, 0xEC1C0503, - 0x81C, 0xEB1E0503, - 0x81C, 0xEA200503, - 0x81C, 0xE9220503, - 0x81C, 0xE8240503, - 0x81C, 0xE7260503, - 0x81C, 0xE6280503, - 0x81C, 0xE52A0503, - 0x81C, 0xC42C0503, - 0x81C, 0xC32E0503, - 0x81C, 0xC2300503, - 0x81C, 0xC1320503, - 0x81C, 0xA4340503, - 0x81C, 0xA3360503, - 0x81C, 0xA2380503, - 0x81C, 0xA13A0503, - 0x81C, 0x833C0503, - 0x81C, 0x823E0503, - 0x81C, 0x81400503, - 0x81C, 0x63420503, - 0x81C, 0x62440503, - 0x81C, 0x61460503, - 0x81C, 0x60480503, - 0x81C, 0x424A0503, - 0x81C, 0x414C0503, - 0x81C, 0x404E0503, - 0x81C, 0x22500503, - 0x81C, 0x21520503, - 0x81C, 0x20540503, - 0x81C, 0x03560503, - 0x81C, 0x02580503, - 0x81C, 0x015A0503, - 0x81C, 0x005C0503, - 0x81C, 0x005E0503, - 0x81C, 0x00600503, - 0x81C, 0x00620503, - 0x81C, 0x00640503, - 0x81C, 0x00660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBF000503, - 0x81C, 0xBE020503, - 0x81C, 0xBD040503, - 0x81C, 0xBC060503, - 0x81C, 0xBB080503, - 0x81C, 0xBA0A0503, - 0x81C, 0xB90C0503, - 0x81C, 0xB80E0503, - 0x81C, 0xB7100503, - 0x81C, 0xB6120503, - 0x81C, 0xB5140503, - 0x81C, 0xB4160503, - 0x81C, 0xB3180503, - 0x81C, 0xB21A0503, - 0x81C, 0xB11C0503, - 0x81C, 0xB01E0503, - 0x81C, 0xAF200503, - 0x81C, 0xAE220503, - 0x81C, 0xAD240503, - 0x81C, 0xAC260503, - 0x81C, 0xAB280503, - 0x81C, 0x8D2A0503, - 0x81C, 0x8C2C0503, - 0x81C, 0x8B2E0503, - 0x81C, 0x8A300503, - 0x81C, 0x89320503, - 0x81C, 0x88340503, - 0x81C, 0x6A360503, - 0x81C, 0x69380503, - 0x81C, 0x683A0503, - 0x81C, 0x673C0503, - 0x81C, 0x663E0503, - 0x81C, 0x65400503, - 0x81C, 0x64420503, - 0x81C, 0x63440503, - 0x81C, 0x62460503, - 0x81C, 0x61480503, - 0x81C, 0x604A0503, - 0x81C, 0x424C0503, - 0x81C, 0x414E0503, - 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0x81C, 0x02660503, - 0x81C, 0x01680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBF000503, - 0x81C, 0xBF020503, - 0x81C, 0xBF040503, - 0x81C, 0xBF060503, - 0x81C, 0xBF080503, - 0x81C, 0xBF0A0503, - 0x81C, 0xBE0C0503, - 0x81C, 0xBD0E0503, - 0x81C, 0xBC100503, - 0x81C, 0xBB120503, - 0x81C, 0xBA140503, - 0x81C, 0xB9160503, - 0x81C, 0xB8180503, - 0x81C, 0xB71A0503, - 0x81C, 0xB61C0503, - 0x81C, 0xB51E0503, - 0x81C, 0xB2200503, - 0x81C, 0xB3220503, - 0x81C, 0xB2240503, - 0x81C, 0xB1260503, - 0x81C, 0xB0280503, - 0x81C, 0xAF2A0503, - 0x81C, 0xAE2C0503, - 0x81C, 0xAD2E0503, - 0x81C, 0xAC300503, - 0x81C, 0xAB320503, - 0x81C, 0xAA340503, - 0x81C, 0xC6360503, - 0x81C, 0xC5380503, - 0x81C, 0xC43A0503, - 0x81C, 0xC33C0503, - 0x81C, 0x883E0503, - 0x81C, 0x87400503, - 0x81C, 0x86420503, - 0x81C, 0x85440503, - 0x81C, 0x84460503, - 0x81C, 0x83480503, - 0x81C, 0x674A0503, - 0x81C, 0x664C0503, - 0x81C, 0x654E0503, - 0x81C, 0x64500503, - 0x81C, 0x27520503, - 0x81C, 0x26540503, - 0x81C, 0x25560503, - 0x81C, 0x24580503, - 0x81C, 0x235A0503, - 0x81C, 0x225C0503, - 0x81C, 0x215E0503, - 0x81C, 0x20600503, - 0x81C, 0x03620503, - 0x81C, 0x02640503, - 0x81C, 0x01660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000403, - 0x81C, 0xFD000503, - 0x81C, 0xFC020503, - 0x81C, 0xFB040503, - 0x81C, 0xFA060503, - 0x81C, 0xF9080503, - 0x81C, 0xF80A0503, - 0x81C, 0xF70C0503, - 0x81C, 0xF60E0503, - 0x81C, 0xF5100503, - 0x81C, 0xF4120503, - 0x81C, 0xF3140503, - 0x81C, 0xF2160503, - 0x81C, 0xF1180503, - 0x81C, 0xF01A0503, - 0x81C, 0xEF1C0503, - 0x81C, 0xEE1E0503, - 0x81C, 0xED200503, - 0x81C, 0xEC220503, - 0x81C, 0xEB240503, - 0x81C, 0xEA260503, - 0x81C, 0xE9280503, - 0x81C, 0xE82A0503, - 0x81C, 0xE72C0503, - 0x81C, 0xE62E0503, - 0x81C, 0xE5300503, - 0x81C, 0xE4320503, - 0x81C, 0xE3340503, - 0x81C, 0xC6360503, - 0x81C, 0xC5380503, - 0x81C, 0xC43A0503, - 0x81C, 0xC33C0503, - 0x81C, 0xA53E0503, - 0x81C, 0xA4400503, - 0x81C, 0xA3420503, - 0x81C, 0xA2440503, - 0x81C, 0xA1460503, - 0x81C, 0xA0480503, - 0x81C, 0x824A0503, - 0x81C, 0x814C0503, - 0x81C, 0x804E0503, - 0x81C, 0x64500503, - 0x81C, 0x63520503, - 0x81C, 0x62540503, - 0x81C, 0x61560503, - 0x81C, 0x60580503, - 0x81C, 0x235A0503, - 0x81C, 0x225C0503, - 0x81C, 0x215E0503, - 0x81C, 0x20600503, - 0x81C, 0x03620503, - 0x81C, 0x02640503, - 0x81C, 0x01660503, - 0x81C, 0x00680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0xA0000000, 0x00000000, - 0x81C, 0xFE000503, - 0x81C, 0xFD020503, - 0x81C, 0xFC040503, - 0x81C, 0xFB060503, - 0x81C, 0xFA080503, - 0x81C, 0xF90A0503, - 0x81C, 0xF80C0503, - 0x81C, 0xF70E0503, - 0x81C, 0xF6100503, - 0x81C, 0xF5120503, - 0x81C, 0xF4140503, - 0x81C, 0xF3160503, - 0x81C, 0xF2180503, - 0x81C, 0xF11A0503, - 0x81C, 0xF01C0503, - 0x81C, 0xEF1E0503, - 0x81C, 0xEE200503, - 0x81C, 0xED220503, - 0x81C, 0xEC240503, - 0x81C, 0xEB260503, - 0x81C, 0xEA280503, - 0x81C, 0xE92A0503, - 0x81C, 0xE82C0503, - 0x81C, 0xE72E0503, - 0x81C, 0xE6300503, - 0x81C, 0xE5320503, - 0x81C, 0xE4340503, - 0x81C, 0xE3360503, - 0x81C, 0xC6380503, - 0x81C, 0xC53A0503, - 0x81C, 0xC43C0503, - 0x81C, 0xC33E0503, - 0x81C, 0xA5400503, - 0x81C, 0xA4420503, - 0x81C, 0xA3440503, - 0x81C, 0xA2460503, - 0x81C, 0xA1480503, - 0x81C, 0xA04A0503, - 0x81C, 0x824C0503, - 0x81C, 0x814E0503, - 0x81C, 0x80500503, - 0x81C, 0x64520503, - 0x81C, 0x63540503, - 0x81C, 0x62560503, - 0x81C, 0x61580503, - 0x81C, 0x605A0503, - 0x81C, 0x235C0503, - 0x81C, 0x225E0503, - 0x81C, 0x21600503, - 0x81C, 0x20620503, - 0x81C, 0x03640503, - 0x81C, 0x02660503, - 0x81C, 0x01680503, - 0x81C, 0x006A0503, - 0x81C, 0x006C0503, - 0x81C, 0x006E0503, - 0x81C, 0x00700503, - 0x81C, 0x00720503, - 0x81C, 0x00740503, - 0x81C, 0x00760503, - 0x81C, 0x00780503, - 0x81C, 0x007A0503, - 0x81C, 0x007C0503, - 0x81C, 0x007E0503, - 0x81C, 0x007E0503, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xA63C0603, - 0x81C, 0xA53E0603, - 0x81C, 0xA4400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0x83480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x804E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x42560603, - 0x81C, 0x41580603, - 0x81C, 0x405A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x04620603, - 0x81C, 0x03640603, - 0x81C, 0x02660603, - 0x81C, 0x01680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBD000603, - 0x81C, 0xBC020603, - 0x81C, 0xBB040603, - 0x81C, 0xBA060603, - 0x81C, 0xB9080603, - 0x81C, 0xB80A0603, - 0x81C, 0xB70C0603, - 0x81C, 0xB60E0603, - 0x81C, 0xB5100603, - 0x81C, 0xB4120603, - 0x81C, 0xB3140603, - 0x81C, 0xB2160603, - 0x81C, 0xB1180603, - 0x81C, 0xB01A0603, - 0x81C, 0xAF1C0603, - 0x81C, 0xAE1E0603, - 0x81C, 0xAD200603, - 0x81C, 0x8F220603, - 0x81C, 0x8E240603, - 0x81C, 0x8D260603, - 0x81C, 0x8C280603, - 0x81C, 0x8B2A0603, - 0x81C, 0x8A2C0603, - 0x81C, 0x892E0603, - 0x81C, 0x88300603, - 0x81C, 0x6B320603, - 0x81C, 0x6A340603, - 0x81C, 0x69360603, - 0x81C, 0x68380603, - 0x81C, 0x673A0603, - 0x81C, 0x663C0603, - 0x81C, 0x653E0603, - 0x81C, 0x64400603, - 0x81C, 0x63420603, - 0x81C, 0x62440603, - 0x81C, 0x61460603, - 0x81C, 0x60480603, - 0x81C, 0x424A0603, - 0x81C, 0x414C0603, - 0x81C, 0x404E0603, - 0x81C, 0x06500603, - 0x81C, 0x05520603, - 0x81C, 0x04540603, - 0x81C, 0x03560603, - 0x81C, 0x02580603, - 0x81C, 0x015A0603, - 0x81C, 0x005C0603, - 0x81C, 0x005E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007C0603, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000603, - 0x81C, 0xF6020603, - 0x81C, 0xF5040603, - 0x81C, 0xF4060603, - 0x81C, 0xF3080603, - 0x81C, 0xF20A0603, - 0x81C, 0xF10C0603, - 0x81C, 0xF00E0603, - 0x81C, 0xEF100603, - 0x81C, 0xEE120603, - 0x81C, 0xED140603, - 0x81C, 0xEC160603, - 0x81C, 0xEB180603, - 0x81C, 0xEA1A0603, - 0x81C, 0xE91C0603, - 0x81C, 0xE81E0603, - 0x81C, 0xE7200603, - 0x81C, 0xE6220603, - 0x81C, 0xE5240603, - 0x81C, 0xE4260603, - 0x81C, 0xE3280603, - 0x81C, 0xC42A0603, - 0x81C, 0xC32C0603, - 0x81C, 0xC22E0603, - 0x81C, 0xC1300603, - 0x81C, 0xC0320603, - 0x81C, 0xA3340603, - 0x81C, 0xA2360603, - 0x81C, 0xA1380603, - 0x81C, 0xA03A0603, - 0x81C, 0x823C0603, - 0x81C, 0x813E0603, - 0x81C, 0x80400603, - 0x81C, 0x64420603, - 0x81C, 0x63440603, - 0x81C, 0x62460603, - 0x81C, 0x61480603, - 0x81C, 0x604A0603, - 0x81C, 0x414C0603, - 0x81C, 0x404E0603, - 0x81C, 0x22500603, - 0x81C, 0x21520603, - 0x81C, 0x20540603, - 0x81C, 0x03560603, - 0x81C, 0x02580603, - 0x81C, 0x015A0603, - 0x81C, 0x005C0603, - 0x81C, 0x005E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEF1A0603, - 0x81C, 0xEE1C0603, - 0x81C, 0xED1E0603, - 0x81C, 0xEC200603, - 0x81C, 0xEB220603, - 0x81C, 0xEA240603, - 0x81C, 0xE9260603, - 0x81C, 0xE8280603, - 0x81C, 0xE72A0603, - 0x81C, 0xE62C0603, - 0x81C, 0xE52E0603, - 0x81C, 0xE4300603, - 0x81C, 0xE3320603, - 0x81C, 0xE2340603, - 0x81C, 0xC6360603, - 0x81C, 0xC5380603, - 0x81C, 0xC43A0603, - 0x81C, 0xC33C0603, - 0x81C, 0xA63E0603, - 0x81C, 0xA5400603, - 0x81C, 0xA4420603, - 0x81C, 0xA3440603, - 0x81C, 0xA2460603, - 0x81C, 0xA1480603, - 0x81C, 0x834A0603, - 0x81C, 0x824C0603, - 0x81C, 0x814E0603, - 0x81C, 0x64500603, - 0x81C, 0x63520603, - 0x81C, 0x62540603, - 0x81C, 0x61560603, - 0x81C, 0x60580603, - 0x81C, 0x405A0603, - 0x81C, 0x215C0603, - 0x81C, 0x205E0603, - 0x81C, 0x03600603, - 0x81C, 0x02620603, - 0x81C, 0x01640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000603, - 0x81C, 0xF6020603, - 0x81C, 0xF5040603, - 0x81C, 0xF4060603, - 0x81C, 0xF3080603, - 0x81C, 0xF20A0603, - 0x81C, 0xF10C0603, - 0x81C, 0xF00E0603, - 0x81C, 0xEF100603, - 0x81C, 0xEE120603, - 0x81C, 0xED140603, - 0x81C, 0xEC160603, - 0x81C, 0xEB180603, - 0x81C, 0xEA1A0603, - 0x81C, 0xE91C0603, - 0x81C, 0xE81E0603, - 0x81C, 0xE7200603, - 0x81C, 0xE6220603, - 0x81C, 0xE5240603, - 0x81C, 0xE4260603, - 0x81C, 0xE3280603, - 0x81C, 0xC42A0603, - 0x81C, 0xC32C0603, - 0x81C, 0xC22E0603, - 0x81C, 0xC1300603, - 0x81C, 0xC0320603, - 0x81C, 0xA3340603, - 0x81C, 0xA2360603, - 0x81C, 0xA1380603, - 0x81C, 0xA03A0603, - 0x81C, 0x823C0603, - 0x81C, 0x813E0603, - 0x81C, 0x80400603, - 0x81C, 0x64420603, - 0x81C, 0x63440603, - 0x81C, 0x62460603, - 0x81C, 0x61480603, - 0x81C, 0x604A0603, - 0x81C, 0x414C0603, - 0x81C, 0x404E0603, - 0x81C, 0x22500603, - 0x81C, 0x21520603, - 0x81C, 0x20540603, - 0x81C, 0x03560603, - 0x81C, 0x02580603, - 0x81C, 0x015A0603, - 0x81C, 0x005C0603, - 0x81C, 0x005E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEF1A0603, - 0x81C, 0xEE1C0603, - 0x81C, 0xED1E0603, - 0x81C, 0xEC200603, - 0x81C, 0xEB220603, - 0x81C, 0xEA240603, - 0x81C, 0xE9260603, - 0x81C, 0xE8280603, - 0x81C, 0xE72A0603, - 0x81C, 0xE62C0603, - 0x81C, 0xE52E0603, - 0x81C, 0xE4300603, - 0x81C, 0xE3320603, - 0x81C, 0xE2340603, - 0x81C, 0xE1360603, - 0x81C, 0xC5380603, - 0x81C, 0xC43A0603, - 0x81C, 0xC33C0603, - 0x81C, 0xC23E0603, - 0x81C, 0xC1400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0xA0480603, - 0x81C, 0x834A0603, - 0x81C, 0x824C0603, - 0x81C, 0x814E0603, - 0x81C, 0x64500603, - 0x81C, 0x63520603, - 0x81C, 0x62540603, - 0x81C, 0x61560603, - 0x81C, 0x25580603, - 0x81C, 0x245A0603, - 0x81C, 0x235C0603, - 0x81C, 0x225E0603, - 0x81C, 0x21600603, - 0x81C, 0x04620603, - 0x81C, 0x03640603, - 0x81C, 0x02660603, - 0x81C, 0x01680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000603, - 0x81C, 0xF8020603, - 0x81C, 0xF7040603, - 0x81C, 0xF6060603, - 0x81C, 0xF5080603, - 0x81C, 0xF40A0603, - 0x81C, 0xF30C0603, - 0x81C, 0xF20E0603, - 0x81C, 0xF1100603, - 0x81C, 0xF0120603, - 0x81C, 0xEF140603, - 0x81C, 0xEE160603, - 0x81C, 0xED180603, - 0x81C, 0xEC1A0603, - 0x81C, 0xEB1C0603, - 0x81C, 0xEA1E0603, - 0x81C, 0xE9200603, - 0x81C, 0xE8220603, - 0x81C, 0xE7240603, - 0x81C, 0xE6260603, - 0x81C, 0xE5280603, - 0x81C, 0xC42A0603, - 0x81C, 0xC32C0603, - 0x81C, 0xC22E0603, - 0x81C, 0xC1300603, - 0x81C, 0xC0320603, - 0x81C, 0xA3340603, - 0x81C, 0xA2360603, - 0x81C, 0xA1380603, - 0x81C, 0xA03A0603, - 0x81C, 0x823C0603, - 0x81C, 0x813E0603, - 0x81C, 0x80400603, - 0x81C, 0x64420603, - 0x81C, 0x63440603, - 0x81C, 0x62460603, - 0x81C, 0x61480603, - 0x81C, 0x604A0603, - 0x81C, 0x414C0603, - 0x81C, 0x404E0603, - 0x81C, 0x22500603, - 0x81C, 0x21520603, - 0x81C, 0x20540603, - 0x81C, 0x03560603, - 0x81C, 0x02580603, - 0x81C, 0x015A0603, - 0x81C, 0x005C0603, - 0x81C, 0x005E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBE000603, - 0x81C, 0xBD020603, - 0x81C, 0xBC040603, - 0x81C, 0xBB060603, - 0x81C, 0xBA080603, - 0x81C, 0xB90A0603, - 0x81C, 0xB80C0603, - 0x81C, 0xB70E0603, - 0x81C, 0xB6100603, - 0x81C, 0xB5120603, - 0x81C, 0xB4140603, - 0x81C, 0xB3160603, - 0x81C, 0xB2180603, - 0x81C, 0xB11A0603, - 0x81C, 0xB01C0603, - 0x81C, 0xAF1E0603, - 0x81C, 0xAE200603, - 0x81C, 0xAD220603, - 0x81C, 0x8F240603, - 0x81C, 0x8E260603, - 0x81C, 0x8D280603, - 0x81C, 0x8C2A0603, - 0x81C, 0x8B2C0603, - 0x81C, 0x8A2E0603, - 0x81C, 0x89300603, - 0x81C, 0x88320603, - 0x81C, 0x6B340603, - 0x81C, 0x6A360603, - 0x81C, 0x69380603, - 0x81C, 0x683A0603, - 0x81C, 0x673C0603, - 0x81C, 0x663E0603, - 0x81C, 0x65400603, - 0x81C, 0x64420603, - 0x81C, 0x63440603, - 0x81C, 0x62460603, - 0x81C, 0x61480603, - 0x81C, 0x604A0603, - 0x81C, 0x424C0603, - 0x81C, 0x414E0603, - 0x81C, 0x40500603, - 0x81C, 0x06520603, - 0x81C, 0x05540603, - 0x81C, 0x04560603, - 0x81C, 0x03580603, - 0x81C, 0x025A0603, - 0x81C, 0x015C0603, - 0x81C, 0x005E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000008, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000603, - 0x81C, 0xFA020603, - 0x81C, 0xF9040603, - 0x81C, 0xF8060603, - 0x81C, 0xF7080603, - 0x81C, 0xF60A0603, - 0x81C, 0xF50C0603, - 0x81C, 0xF40E0603, - 0x81C, 0xF3100603, - 0x81C, 0xF2120603, - 0x81C, 0xF1140603, - 0x81C, 0xF0160603, - 0x81C, 0xEF180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xC23C0603, - 0x81C, 0xC13E0603, - 0x81C, 0xC0400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0xA0480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x804E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x60560603, - 0x81C, 0x24580603, - 0x81C, 0x235A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x03620603, - 0x81C, 0x02640603, - 0x81C, 0x01660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000009, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000603, - 0x81C, 0xF7020603, - 0x81C, 0xF6040603, - 0x81C, 0xF5060603, - 0x81C, 0xF4080603, - 0x81C, 0xF30A0603, - 0x81C, 0xF20C0603, - 0x81C, 0xF10E0603, - 0x81C, 0xF0100603, - 0x81C, 0xEF120603, - 0x81C, 0xEE140603, - 0x81C, 0xED160603, - 0x81C, 0xEC180603, - 0x81C, 0xEB1A0603, - 0x81C, 0xEA1C0603, - 0x81C, 0xE91E0603, - 0x81C, 0xE8200603, - 0x81C, 0xE7220603, - 0x81C, 0xE6240603, - 0x81C, 0xE5260603, - 0x81C, 0xE4280603, - 0x81C, 0xE32A0603, - 0x81C, 0xC42C0603, - 0x81C, 0xC32E0603, - 0x81C, 0xC2300603, - 0x81C, 0xC1320603, - 0x81C, 0xA3340603, - 0x81C, 0xA2360603, - 0x81C, 0xA1380603, - 0x81C, 0xA03A0603, - 0x81C, 0x823C0603, - 0x81C, 0x813E0603, - 0x81C, 0x80400603, - 0x81C, 0x65420603, - 0x81C, 0x64440603, - 0x81C, 0x63460603, - 0x81C, 0x62480603, - 0x81C, 0x614A0603, - 0x81C, 0x424C0603, - 0x81C, 0x414E0603, - 0x81C, 0x40500603, - 0x81C, 0x22520603, - 0x81C, 0x21540603, - 0x81C, 0x20560603, - 0x81C, 0x04580603, - 0x81C, 0x035A0603, - 0x81C, 0x025C0603, - 0x81C, 0x015E0603, - 0x81C, 0x00600603, - 0x81C, 0x00620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000a, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xA63C0603, - 0x81C, 0xA53E0603, - 0x81C, 0xA4400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0x83480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x804E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x42560603, - 0x81C, 0x41580603, - 0x81C, 0x405A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x04620603, - 0x81C, 0x03640603, - 0x81C, 0x02660603, - 0x81C, 0x01680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000b, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF9000603, - 0x81C, 0xF8020603, - 0x81C, 0xF7040603, - 0x81C, 0xF6060603, - 0x81C, 0xF5080603, - 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0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEF1A0603, - 0x81C, 0xEE1C0603, - 0x81C, 0xED1E0603, - 0x81C, 0xEC200603, - 0x81C, 0xEB220603, - 0x81C, 0xEA240603, - 0x81C, 0xE9260603, - 0x81C, 0xE8280603, - 0x81C, 0xE72A0603, - 0x81C, 0xE62C0603, - 0x81C, 0xE52E0603, - 0x81C, 0xE4300603, - 0x81C, 0xE3320603, - 0x81C, 0xE2340603, - 0x81C, 0xC6360603, - 0x81C, 0xC5380603, - 0x81C, 0xC43A0603, - 0x81C, 0xC33C0603, - 0x81C, 0xA63E0603, - 0x81C, 0xA5400603, - 0x81C, 0xA4420603, - 0x81C, 0xA3440603, - 0x81C, 0xA2460603, - 0x81C, 0xA1480603, - 0x81C, 0x834A0603, - 0x81C, 0x824C0603, - 0x81C, 0x814E0603, - 0x81C, 0x64500603, - 0x81C, 0x63520603, - 0x81C, 0x62540603, - 0x81C, 0x61560603, - 0x81C, 0x60580603, - 0x81C, 0x405A0603, - 0x81C, 0x215C0603, - 0x81C, 0x205E0603, - 0x81C, 0x03600603, - 0x81C, 0x02620603, - 0x81C, 0x01640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xA63C0603, - 0x81C, 0xA53E0603, - 0x81C, 0xA4400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0x83480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x804E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x42560603, - 0x81C, 0x41580603, - 0x81C, 0x405A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x04620603, - 0x81C, 0x03640603, - 0x81C, 0x02660603, - 0x81C, 0x01680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000603, - 0x81C, 0xFB020603, - 0x81C, 0xFA040603, - 0x81C, 0xF9060603, - 0x81C, 0xF8080603, - 0x81C, 0xF70A0603, - 0x81C, 0xF60C0603, - 0x81C, 0xF50E0603, - 0x81C, 0xF4100603, - 0x81C, 0xF3120603, - 0x81C, 0xF2140603, - 0x81C, 0xF1160603, - 0x81C, 0xF0180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xA63C0603, - 0x81C, 0xA53E0603, - 0x81C, 0xA4400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0x83480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x804E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x42560603, - 0x81C, 0x41580603, - 0x81C, 0x405A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x04620603, - 0x81C, 0x03640603, - 0x81C, 0x02660603, - 0x81C, 0x01680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBF000603, - 0x81C, 0xBF020603, - 0x81C, 0xBF040603, - 0x81C, 0xBF060603, - 0x81C, 0xBF080603, - 0x81C, 0xBE0A0603, - 0x81C, 0xBD0C0603, - 0x81C, 0xBC0E0603, - 0x81C, 0xBB100603, - 0x81C, 0xBA120603, - 0x81C, 0xB9140603, - 0x81C, 0xB8160603, - 0x81C, 0xB7180603, - 0x81C, 0xB61A0603, - 0x81C, 0xB51C0603, - 0x81C, 0xB41E0603, - 0x81C, 0xB1200603, - 0x81C, 0xB2220603, - 0x81C, 0xB1240603, - 0x81C, 0xB0260603, - 0x81C, 0xAF280603, - 0x81C, 0xAE2A0603, - 0x81C, 0xAD2C0603, - 0x81C, 0xAC2E0603, - 0x81C, 0xAB300603, - 0x81C, 0xAA320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0x883C0603, - 0x81C, 0x873E0603, - 0x81C, 0x86400603, - 0x81C, 0x85420603, - 0x81C, 0x84440603, - 0x81C, 0x83460603, - 0x81C, 0x67480603, - 0x81C, 0x664A0603, - 0x81C, 0x654C0603, - 0x81C, 0x644E0603, - 0x81C, 0x27500603, - 0x81C, 0x26520603, - 0x81C, 0x25540603, - 0x81C, 0x24560603, - 0x81C, 0x23580603, - 0x81C, 0x225A0603, - 0x81C, 0x215C0603, - 0x81C, 0x205E0603, - 0x81C, 0x03600603, - 0x81C, 0x02620603, - 0x81C, 0x01640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000403, - 0x81C, 0xFB000603, - 0x81C, 0xFA020603, - 0x81C, 0xF9040603, - 0x81C, 0xF8060603, - 0x81C, 0xF7080603, - 0x81C, 0xF60A0603, - 0x81C, 0xF50C0603, - 0x81C, 0xF40E0603, - 0x81C, 0xF3100603, - 0x81C, 0xF2120603, - 0x81C, 0xF1140603, - 0x81C, 0xF0160603, - 0x81C, 0xEF180603, - 0x81C, 0xEE1A0603, - 0x81C, 0xED1C0603, - 0x81C, 0xEC1E0603, - 0x81C, 0xEB200603, - 0x81C, 0xEA220603, - 0x81C, 0xE9240603, - 0x81C, 0xE8260603, - 0x81C, 0xE7280603, - 0x81C, 0xE62A0603, - 0x81C, 0xE52C0603, - 0x81C, 0xE42E0603, - 0x81C, 0xE3300603, - 0x81C, 0xE2320603, - 0x81C, 0xC6340603, - 0x81C, 0xC5360603, - 0x81C, 0xC4380603, - 0x81C, 0xC33A0603, - 0x81C, 0xA63C0603, - 0x81C, 0xA53E0603, - 0x81C, 0xA4400603, - 0x81C, 0xA3420603, - 0x81C, 0xA2440603, - 0x81C, 0xA1460603, - 0x81C, 0x83480603, - 0x81C, 0x824A0603, - 0x81C, 0x814C0603, - 0x81C, 0x644E0603, - 0x81C, 0x63500603, - 0x81C, 0x62520603, - 0x81C, 0x61540603, - 0x81C, 0x60560603, - 0x81C, 0x40580603, - 0x81C, 0x215A0603, - 0x81C, 0x205C0603, - 0x81C, 0x035E0603, - 0x81C, 0x02600603, - 0x81C, 0x01620603, - 0x81C, 0x00640603, - 0x81C, 0x00660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0xA0000000, 0x00000000, - 0x81C, 0xFD000603, - 0x81C, 0xFC020603, - 0x81C, 0xFB040603, - 0x81C, 0xFA060603, - 0x81C, 0xF9080603, - 0x81C, 0xF80A0603, - 0x81C, 0xF70C0603, - 0x81C, 0xF60E0603, - 0x81C, 0xF5100603, - 0x81C, 0xF4120603, - 0x81C, 0xF3140603, - 0x81C, 0xF2160603, - 0x81C, 0xF1180603, - 0x81C, 0xF01A0603, - 0x81C, 0xEF1C0603, - 0x81C, 0xEE1E0603, - 0x81C, 0xED200603, - 0x81C, 0xEC220603, - 0x81C, 0xEB240603, - 0x81C, 0xEA260603, - 0x81C, 0xE9280603, - 0x81C, 0xE82A0603, - 0x81C, 0xE72C0603, - 0x81C, 0xE62E0603, - 0x81C, 0xE5300603, - 0x81C, 0xE4320603, - 0x81C, 0xE3340603, - 0x81C, 0xC6360603, - 0x81C, 0xC5380603, - 0x81C, 0xC43A0603, - 0x81C, 0xC33C0603, - 0x81C, 0xA63E0603, - 0x81C, 0xA5400603, - 0x81C, 0xA4420603, - 0x81C, 0xA3440603, - 0x81C, 0xA2460603, - 0x81C, 0xA1480603, - 0x81C, 0x834A0603, - 0x81C, 0x824C0603, - 0x81C, 0x814E0603, - 0x81C, 0x64500603, - 0x81C, 0x63520603, - 0x81C, 0x62540603, - 0x81C, 0x61560603, - 0x81C, 0x60580603, - 0x81C, 0x235A0603, - 0x81C, 0x225C0603, - 0x81C, 0x215E0603, - 0x81C, 0x20600603, - 0x81C, 0x03620603, - 0x81C, 0x02640603, - 0x81C, 0x01660603, - 0x81C, 0x00680603, - 0x81C, 0x006A0603, - 0x81C, 0x006C0603, - 0x81C, 0x006E0603, - 0x81C, 0x00700603, - 0x81C, 0x00720603, - 0x81C, 0x00740603, - 0x81C, 0x00760603, - 0x81C, 0x00780603, - 0x81C, 0x007A0603, - 0x81C, 0x007C0603, - 0x81C, 0x007E0603, - 0x81C, 0x007E0603, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000703, - 0x81C, 0xFB020703, - 0x81C, 0xFA040703, - 0x81C, 0xF9060703, - 0x81C, 0xF8080703, - 0x81C, 0xF70A0703, - 0x81C, 0xF60C0703, - 0x81C, 0xF50E0703, - 0x81C, 0xF4100703, - 0x81C, 0xF3120703, - 0x81C, 0xF2140703, - 0x81C, 0xF1160703, - 0x81C, 0xEF180703, - 0x81C, 0xEE1A0703, - 0x81C, 0xED1C0703, - 0x81C, 0xEC1E0703, - 0x81C, 0xEB200703, - 0x81C, 0xEA220703, - 0x81C, 0xE9240703, - 0x81C, 0xE8260703, - 0x81C, 0xE7280703, - 0x81C, 0xE62A0703, - 0x81C, 0xE52C0703, - 0x81C, 0xE42E0703, - 0x81C, 0xE3300703, - 0x81C, 0xE2320703, - 0x81C, 0xC6340703, - 0x81C, 0xC5360703, - 0x81C, 0xC4380703, - 0x81C, 0xC33A0703, - 0x81C, 0xA63C0703, - 0x81C, 0xA53E0703, - 0x81C, 0xA4400703, - 0x81C, 0xA3420703, - 0x81C, 0xA2440703, - 0x81C, 0xA1460703, - 0x81C, 0x83480703, - 0x81C, 0x824A0703, - 0x81C, 0x814C0703, - 0x81C, 0x804E0703, - 0x81C, 0x63500703, - 0x81C, 0x62520703, - 0x81C, 0x61540703, - 0x81C, 0x42560703, - 0x81C, 0x41580703, - 0x81C, 0x405A0703, - 0x81C, 0x225C0703, - 0x81C, 0x215E0703, - 0x81C, 0x20600703, - 0x81C, 0x04620703, - 0x81C, 0x03640703, - 0x81C, 0x02660703, - 0x81C, 0x01680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBD000703, - 0x81C, 0xBC020703, - 0x81C, 0xBB040703, - 0x81C, 0xBA060703, - 0x81C, 0xB9080703, - 0x81C, 0xB80A0703, - 0x81C, 0xB70C0703, - 0x81C, 0xB60E0703, - 0x81C, 0xB5100703, - 0x81C, 0xB4120703, - 0x81C, 0xB3140703, - 0x81C, 0xB2160703, - 0x81C, 0xB1180703, - 0x81C, 0xB01A0703, - 0x81C, 0xAF1C0703, - 0x81C, 0xAE1E0703, - 0x81C, 0xAD200703, - 0x81C, 0xAC220703, - 0x81C, 0x8E240703, - 0x81C, 0x8D260703, - 0x81C, 0x8C280703, - 0x81C, 0x6F2A0703, - 0x81C, 0x6E2C0703, - 0x81C, 0x6D2E0703, - 0x81C, 0x6C300703, - 0x81C, 0x6B320703, - 0x81C, 0x6A340703, - 0x81C, 0x69360703, - 0x81C, 0x68380703, - 0x81C, 0x673A0703, - 0x81C, 0x663C0703, - 0x81C, 0x653E0703, - 0x81C, 0x64400703, - 0x81C, 0x63420703, - 0x81C, 0x62440703, - 0x81C, 0x61460703, - 0x81C, 0x60480703, - 0x81C, 0x424A0703, - 0x81C, 0x414C0703, - 0x81C, 0x404E0703, - 0x81C, 0x06500703, - 0x81C, 0x05520703, - 0x81C, 0x04540703, - 0x81C, 0x03560703, - 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0x9000000b, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000703, - 0x81C, 0xF7020703, - 0x81C, 0xF6040703, - 0x81C, 0xF5060703, - 0x81C, 0xF4080703, - 0x81C, 0xF30A0703, - 0x81C, 0xF20C0703, - 0x81C, 0xF10E0703, - 0x81C, 0xF0100703, - 0x81C, 0xEF120703, - 0x81C, 0xEE140703, - 0x81C, 0xED160703, - 0x81C, 0xEC180703, - 0x81C, 0xEB1A0703, - 0x81C, 0xEA1C0703, - 0x81C, 0xE91E0703, - 0x81C, 0xCA200703, - 0x81C, 0xC9220703, - 0x81C, 0xC8240703, - 0x81C, 0xC7260703, - 0x81C, 0xC6280703, - 0x81C, 0xC52A0703, - 0x81C, 0xC42C0703, - 0x81C, 0xC32E0703, - 0x81C, 0xC2300703, - 0x81C, 0xC1320703, - 0x81C, 0xA3340703, - 0x81C, 0xA2360703, - 0x81C, 0xA1380703, - 0x81C, 0xA03A0703, - 0x81C, 0x823C0703, - 0x81C, 0x813E0703, - 0x81C, 0x80400703, - 0x81C, 0x64420703, - 0x81C, 0x63440703, - 0x81C, 0x62460703, - 0x81C, 0x61480703, - 0x81C, 0x604A0703, - 0x81C, 0x234C0703, - 0x81C, 0x224E0703, - 0x81C, 0x21500703, - 0x81C, 0x20520703, - 0x81C, 0x06540703, - 0x81C, 0x05560703, - 0x81C, 0x04580703, - 0x81C, 0x035A0703, - 0x81C, 0x025C0703, - 0x81C, 0x015E0703, - 0x81C, 0x00600703, - 0x81C, 0x00620703, - 0x81C, 0x00640703, - 0x81C, 0x00660703, - 0x81C, 0x00680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x9000000c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000703, - 0x81C, 0xFB020703, - 0x81C, 0xFA040703, - 0x81C, 0xF9060703, - 0x81C, 0xF8080703, - 0x81C, 0xF70A0703, - 0x81C, 0xF60C0703, - 0x81C, 0xF50E0703, - 0x81C, 0xF4100703, - 0x81C, 0xF3120703, - 0x81C, 0xF2140703, - 0x81C, 0xF1160703, - 0x81C, 0xF0180703, - 0x81C, 0xEF1A0703, - 0x81C, 0xEE1C0703, - 0x81C, 0xED1E0703, - 0x81C, 0xEC200703, - 0x81C, 0xEB220703, - 0x81C, 0xEA240703, - 0x81C, 0xE9260703, - 0x81C, 0xE8280703, - 0x81C, 0xE72A0703, - 0x81C, 0xE62C0703, - 0x81C, 0xE52E0703, - 0x81C, 0xE4300703, - 0x81C, 0xE3320703, - 0x81C, 0xE2340703, - 0x81C, 0xC6360703, - 0x81C, 0xC5380703, - 0x81C, 0xC43A0703, - 0x81C, 0xC33C0703, - 0x81C, 0xA63E0703, - 0x81C, 0xA5400703, - 0x81C, 0xA4420703, - 0x81C, 0xA3440703, - 0x81C, 0xA2460703, - 0x81C, 0x84480703, - 0x81C, 0x834A0703, - 0x81C, 0x824C0703, - 0x81C, 0x814E0703, - 0x81C, 0x80500703, - 0x81C, 0x63520703, - 0x81C, 0x62540703, - 0x81C, 0x61560703, - 0x81C, 0x60580703, - 0x81C, 0x225A0703, - 0x81C, 0x055C0703, - 0x81C, 0x045E0703, - 0x81C, 0x03600703, - 0x81C, 0x02620703, - 0x81C, 0x01640703, - 0x81C, 0x00660703, - 0x81C, 0x00680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000703, - 0x81C, 0xFA020703, - 0x81C, 0xF9040703, - 0x81C, 0xF8060703, - 0x81C, 0xF7080703, - 0x81C, 0xF60A0703, - 0x81C, 0xF50C0703, - 0x81C, 0xF40E0703, - 0x81C, 0xF3100703, - 0x81C, 0xF2120703, - 0x81C, 0xF1140703, - 0x81C, 0xEF160703, - 0x81C, 0xEE180703, - 0x81C, 0xED1A0703, - 0x81C, 0xEC1C0703, - 0x81C, 0xEB1E0703, - 0x81C, 0xEA200703, - 0x81C, 0xE9220703, - 0x81C, 0xE8240703, - 0x81C, 0xE7260703, - 0x81C, 0xE6280703, - 0x81C, 0xE52A0703, - 0x81C, 0xE42C0703, - 0x81C, 0xE32E0703, - 0x81C, 0xE2300703, - 0x81C, 0xE1320703, - 0x81C, 0xC6340703, - 0x81C, 0xC5360703, - 0x81C, 0xC4380703, - 0x81C, 0xC33A0703, - 0x81C, 0xA63C0703, - 0x81C, 0xA53E0703, - 0x81C, 0xA4400703, - 0x81C, 0xA3420703, - 0x81C, 0xA2440703, - 0x81C, 0xA1460703, - 0x81C, 0x83480703, - 0x81C, 0x824A0703, - 0x81C, 0x814C0703, - 0x81C, 0x804E0703, - 0x81C, 0x63500703, - 0x81C, 0x62520703, - 0x81C, 0x61540703, - 0x81C, 0x42560703, - 0x81C, 0x41580703, - 0x81C, 0x405A0703, - 0x81C, 0x225C0703, - 0x81C, 0x215E0703, - 0x81C, 0x20600703, - 0x81C, 0x04620703, - 0x81C, 0x03640703, - 0x81C, 0x02660703, - 0x81C, 0x01680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFB000703, - 0x81C, 0xFA020703, - 0x81C, 0xF9040703, - 0x81C, 0xF8060703, - 0x81C, 0xF7080703, - 0x81C, 0xF60A0703, - 0x81C, 0xF50C0703, - 0x81C, 0xF40E0703, - 0x81C, 0xF3100703, - 0x81C, 0xF2120703, - 0x81C, 0xF1140703, - 0x81C, 0xEF160703, - 0x81C, 0xEE180703, - 0x81C, 0xED1A0703, - 0x81C, 0xEC1C0703, - 0x81C, 0xEB1E0703, - 0x81C, 0xEA200703, - 0x81C, 0xE9220703, - 0x81C, 0xE8240703, - 0x81C, 0xE7260703, - 0x81C, 0xE6280703, - 0x81C, 0xE52A0703, - 0x81C, 0xE42C0703, - 0x81C, 0xE32E0703, - 0x81C, 0xE2300703, - 0x81C, 0xE1320703, - 0x81C, 0xC6340703, - 0x81C, 0xC5360703, - 0x81C, 0xC4380703, - 0x81C, 0xC33A0703, - 0x81C, 0xA63C0703, - 0x81C, 0xA53E0703, - 0x81C, 0xA4400703, - 0x81C, 0xA3420703, - 0x81C, 0xA2440703, - 0x81C, 0xA1460703, - 0x81C, 0x83480703, - 0x81C, 0x824A0703, - 0x81C, 0x814C0703, - 0x81C, 0x804E0703, - 0x81C, 0x63500703, - 0x81C, 0x62520703, - 0x81C, 0x61540703, - 0x81C, 0x42560703, - 0x81C, 0x41580703, - 0x81C, 0x405A0703, - 0x81C, 0x225C0703, - 0x81C, 0x215E0703, - 0x81C, 0x20600703, - 0x81C, 0x04620703, - 0x81C, 0x03640703, - 0x81C, 0x02660703, - 0x81C, 0x01680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x9000000f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xBF000703, - 0x81C, 0xBF020703, - 0x81C, 0xBF040703, - 0x81C, 0xBF060703, - 0x81C, 0xBF080703, - 0x81C, 0xBE0A0703, - 0x81C, 0xBD0C0703, - 0x81C, 0xBC0E0703, - 0x81C, 0xBB100703, - 0x81C, 0xBA120703, - 0x81C, 0xB9140703, - 0x81C, 0xB8160703, - 0x81C, 0xB7180703, - 0x81C, 0xB61A0703, - 0x81C, 0xB51C0703, - 0x81C, 0xB41E0703, - 0x81C, 0xB1200703, - 0x81C, 0xB2220703, - 0x81C, 0xB1240703, - 0x81C, 0xB0260703, - 0x81C, 0xAF280703, - 0x81C, 0xAE2A0703, - 0x81C, 0xAD2C0703, - 0x81C, 0xAC2E0703, - 0x81C, 0xAB300703, - 0x81C, 0xAA320703, - 0x81C, 0xC6340703, - 0x81C, 0xC5360703, - 0x81C, 0xC4380703, - 0x81C, 0xC33A0703, - 0x81C, 0x883C0703, - 0x81C, 0x873E0703, - 0x81C, 0x86400703, - 0x81C, 0x85420703, - 0x81C, 0x84440703, - 0x81C, 0x83460703, - 0x81C, 0x67480703, - 0x81C, 0x664A0703, - 0x81C, 0x654C0703, - 0x81C, 0x644E0703, - 0x81C, 0x27500703, - 0x81C, 0x26520703, - 0x81C, 0x25540703, - 0x81C, 0x24560703, - 0x81C, 0x23580703, - 0x81C, 0x225A0703, - 0x81C, 0x215C0703, - 0x81C, 0x205E0703, - 0x81C, 0x03600703, - 0x81C, 0x02620703, - 0x81C, 0x01640703, - 0x81C, 0x00660703, - 0x81C, 0x00680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0x90000010, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000403, - 0x81C, 0xFB000703, - 0x81C, 0xFA020703, - 0x81C, 0xF9040703, - 0x81C, 0xF8060703, - 0x81C, 0xF7080703, - 0x81C, 0xF60A0703, - 0x81C, 0xF50C0703, - 0x81C, 0xF40E0703, - 0x81C, 0xF3100703, - 0x81C, 0xF2120703, - 0x81C, 0xF1140703, - 0x81C, 0xF0160703, - 0x81C, 0xEF180703, - 0x81C, 0xEE1A0703, - 0x81C, 0xED1C0703, - 0x81C, 0xEC1E0703, - 0x81C, 0xEB200703, - 0x81C, 0xEA220703, - 0x81C, 0xE9240703, - 0x81C, 0xE8260703, - 0x81C, 0xE7280703, - 0x81C, 0xE62A0703, - 0x81C, 0xE52C0703, - 0x81C, 0xE42E0703, - 0x81C, 0xE3300703, - 0x81C, 0xE2320703, - 0x81C, 0xC6340703, - 0x81C, 0xC5360703, - 0x81C, 0xC4380703, - 0x81C, 0xC33A0703, - 0x81C, 0xA63C0703, - 0x81C, 0xA53E0703, - 0x81C, 0xA4400703, - 0x81C, 0xA3420703, - 0x81C, 0xA2440703, - 0x81C, 0x84460703, - 0x81C, 0x83480703, - 0x81C, 0x824A0703, - 0x81C, 0x814C0703, - 0x81C, 0x804E0703, - 0x81C, 0x63500703, - 0x81C, 0x62520703, - 0x81C, 0x61540703, - 0x81C, 0x60560703, - 0x81C, 0x22580703, - 0x81C, 0x055A0703, - 0x81C, 0x045C0703, - 0x81C, 0x035E0703, - 0x81C, 0x02600703, - 0x81C, 0x01620703, - 0x81C, 0x00640703, - 0x81C, 0x00660703, - 0x81C, 0x00680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0xA0000000, 0x00000000, - 0x81C, 0xFC000703, - 0x81C, 0xFB020703, - 0x81C, 0xFA040703, - 0x81C, 0xF9060703, - 0x81C, 0xF8080703, - 0x81C, 0xF70A0703, - 0x81C, 0xF60C0703, - 0x81C, 0xF50E0703, - 0x81C, 0xF4100703, - 0x81C, 0xF3120703, - 0x81C, 0xF2140703, - 0x81C, 0xF1160703, - 0x81C, 0xF0180703, - 0x81C, 0xEF1A0703, - 0x81C, 0xEE1C0703, - 0x81C, 0xED1E0703, - 0x81C, 0xEC200703, - 0x81C, 0xEB220703, - 0x81C, 0xEA240703, - 0x81C, 0xE9260703, - 0x81C, 0xE8280703, - 0x81C, 0xE72A0703, - 0x81C, 0xE62C0703, - 0x81C, 0xE52E0703, - 0x81C, 0xE4300703, - 0x81C, 0xE3320703, - 0x81C, 0xE2340703, - 0x81C, 0xC6360703, - 0x81C, 0xC5380703, - 0x81C, 0xC43A0703, - 0x81C, 0xC33C0703, - 0x81C, 0xA63E0703, - 0x81C, 0xA5400703, - 0x81C, 0xA4420703, - 0x81C, 0xA3440703, - 0x81C, 0xA2460703, - 0x81C, 0x84480703, - 0x81C, 0x834A0703, - 0x81C, 0x824C0703, - 0x81C, 0x814E0703, - 0x81C, 0x80500703, - 0x81C, 0x63520703, - 0x81C, 0x62540703, - 0x81C, 0x61560703, - 0x81C, 0x60580703, - 0x81C, 0x235A0703, - 0x81C, 0x225C0703, - 0x81C, 0x215E0703, - 0x81C, 0x20600703, - 0x81C, 0x03620703, - 0x81C, 0x02640703, - 0x81C, 0x01660703, - 0x81C, 0x00680703, - 0x81C, 0x006A0703, - 0x81C, 0x006C0703, - 0x81C, 0x006E0703, - 0x81C, 0x00700703, - 0x81C, 0x00720703, - 0x81C, 0x00740703, - 0x81C, 0x00760703, - 0x81C, 0x00780703, - 0x81C, 0x007A0703, - 0x81C, 0x007C0703, - 0x81C, 0x007E0703, - 0x81C, 0x007E0703, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0xA0000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0xB0000000, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8822B_AGC_TAB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_AGC_TAB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_AGC_8822B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8822B_AGC_TAB(void) -{ - return 101; -} - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG[] = { - 0x800, 0x9020D010, - 0x804, 0x800181A0, - 0x808, 0x0E028233, - 0x80C, 0x10000013, - 0x810, 0x22101243, - 0x814, 0x020C3D11, - 0x818, 0x84A10385, - 0x81C, 0x1E1E081F, - 0x820, 0x0001AAAA, - 0x824, 0x00030FE0, - 0x828, 0x0000CCCC, - 0x82C, 0x75CB7010, - 0x830, 0x79A0EAAA, - 0x834, 0x072E6986, - 0x838, 0x87766441, - 0x83C, 0x9194B2B7, - 0x840, 0x171750E0, - 0x844, 0x4D3D7CDB, - 0x848, 0x4AD0408B, - 0x84C, 0x6AFBF7A5, - 0x850, 0x28A74706, - 0x854, 0x0001520C, - 0x858, 0x4060C000, - 0x85C, 0x74010160, - 0x860, 0x68A7C321, - 0x864, 0x79F27432, - 0x868, 0x8CA7A314, - 0x86C, 0x778C2878, - 0x870, 0x77777777, - 0x874, 0x27612C2E, - 0x878, 0xC0003152, - 0x87C, 0x5C8FC000, - 0x880, 0x00000000, - 0x884, 0x00000000, - 0x888, 0x00000000, - 0x88C, 0x00000000, - 0x890, 0x00000000, - 0x894, 0x00000000, - 0x898, 0x00000000, - 0x89C, 0x00000000, - 0x8A0, 0x00000013, - 0x8A4, 0x7F7F7F7F, - 0x8A8, 0x2202033E, - 0x8AC, 0xF00F000A, - 0x8B0, 0x00000600, - 0x8B4, 0x000FC080, - 0x8B8, 0xEC0057F7, - 0x8BC, 0xACB520A3, - 0x8C0, 0xFFE04020, - 0x8C4, 0x47C00000, - 0x8C8, 0x000251A5, - 0x8CC, 0x08108492, - 0x8D0, 0x0000B800, - 0x8D4, 0x860308A0, - 0x8D8, 0x29095612, - 0x8DC, 0x00000000, - 0x8E0, 0x32D16777, - 0x8E4, 0x4C098935, - 0x8E8, 0xFFFFC42C, - 0x8EC, 0x99999999, - 0x8F0, 0x00009999, - 0x8F4, 0x00D80FA1, - 0x8F8, 0x40000080, - 0x8FC, 0x00000130, - 0x900, 0x00800000, - 0x904, 0x00000000, - 0x908, 0x00000000, - 0x90C, 0xD3000000, - 0x910, 0x0000FC00, - 0x914, 0xC6380000, - 0x918, 0x1C1028C0, - 0x91C, 0x64B11A1C, - 0x920, 0xE0767233, - 0x924, 0x855A2500, - 0x928, 0x4AB0E4E4, - 0x92C, 0xFFFEB200, - 0x930, 0xFFFFFFFE, - 0x934, 0x001FFFFF, - 0x938, 0x00008480, - 0x93C, 0xE41C0642, - 0x940, 0x0E470430, - 0x944, 0x00000000, - 0x948, 0xAC000000, - 0x94C, 0x10000083, - 0x950, 0x32010080, - 0x954, 0x84510080, - 0x958, 0x00000001, - 0x95C, 0x04248000, - 0x960, 0x00000000, - 0x964, 0x00000000, - 0x968, 0x00000000, - 0x96C, 0x00000000, - 0x970, 0x00001FFF, - 0x974, 0x44000FFF, - 0x978, 0x00000000, - 0x97C, 0x00000000, - 0x980, 0x00000000, - 0x984, 0x00000000, - 0x988, 0x00000000, - 0x98C, 0x43440000, - 0x990, 0x27100000, - 0x994, 0xFFFF0100, - 0x998, 0xFFFFFF5C, - 0x99C, 0xFFFFFFFF, - 0x9A0, 0x000000FF, - 0x9A4, 0x80000088, - 0x9A8, 0x0C2F0000, - 0x9AC, 0x01560000, - 0x9B0, 0x70000000, - 0x9B4, 0x00000000, - 0x9B8, 0x00000000, - 0x9BC, 0x00000000, - 0x9C0, 0x00000000, - 0x9C4, 0x00000000, - 0x9C8, 0x00000000, - 0x9CC, 0x00000000, - 0x9D0, 0x00000000, - 0x9D4, 0x00000000, - 0x9D8, 0x00000000, - 0x9DC, 0x00000000, - 0x9E0, 0x00000000, - 0x9E4, 0x02000402, - 0x9E8, 0x000022D4, - 0x9EC, 0x00000000, - 0x9F0, 0x00010080, - 0x9F4, 0x00000000, - 0x9F8, 0x00000000, - 0x9FC, 0xEFFFF7F7, - 0xA00, 0x00D047C8, - 0xA04, 0x81FF800C, - 0xA08, 0x8C838300, - 0xA0C, 0x2E20100F, - 0xA10, 0x9500BB78, - 0xA14, 0x1114D028, - 0xA18, 0x00881117, - 0xA1C, 0x89140F00, - 0xA20, 0x84880000, - 0xA24, 0x384F6577, - 0xA28, 0x00001525, - 0xA2C, 0x00920000, - 0xA70, 0x101FFF00, - 0xA74, 0x00000148, - 0xA78, 0x00000900, - 0xA7C, 0x225B0606, - 0xA80, 0x218675B2, - 0xA84, 0x80208C00, - 0xA88, 0x040C0000, - 0xA8C, 0x12345678, - 0xA90, 0xABCDEF00, - 0xA94, 0x001B1B89, - 0xA98, 0x030A0000, - 0xA9C, 0x00060000, - 0xAA0, 0x00000000, - 0xAA4, 0x0004000F, - 0xAA8, 0x00000200, - 0xB00, 0xE1000440, - 0xB04, 0x00800000, - 0xB08, 0xFF02030B, - 0xB0C, 0x01EAA406, - 0xB10, 0x00030690, - 0xB14, 0x006000FA, - 0xB18, 0x00000002, - 0xB1C, 0x00000002, - 0xB20, 0x4B00001F, - 0xB24, 0x4E8E3E40, - 0xB28, 0x03020100, - 0xB2C, 0x07060504, - 0xB30, 0x0B0A0908, - 0xB34, 0x0F0E0D0C, - 0xB38, 0x13121110, - 0xB3C, 0x0000003A, - 0xB40, 0x00000000, - 0xB44, 0x80000000, - 0xB48, 0x3F0000FA, - 0xB4C, 0x88C80020, - 0xB50, 0x00000000, - 0xB54, 0x00004241, - 0xB58, 0xE0008208, - 0xB5C, 0x41EFFFF9, - 0xB60, 0x00000000, - 0xB64, 0x00200063, - 0xB68, 0x0000003A, - 0xB6C, 0x00000102, - 0xB70, 0x4E6D1870, - 0xB74, 0x03020100, - 0xB78, 0x07060504, - 0xB7C, 0x0B0A0908, - 0xB80, 0x0F0E0D0C, - 0xB84, 0x13121110, - 0xB88, 0x00000000, - 0xB8C, 0x00000000, - 0xC00, 0x00000007, - 0xC04, 0x00000020, - 0xC08, 0x60403231, - 0xC0C, 0x00012345, - 0xC10, 0x00000100, - 0xC14, 0x01000000, - 0xC18, 0x00000000, - 0xC1C, 0x40040053, - 0xC20, 0x40020103, - 0xC24, 0x00000000, - 0xC28, 0x00000000, - 0xC2C, 0x00000000, - 0xC30, 0x00000000, - 0xC34, 0x00000000, - 0xC38, 0x00000000, - 0xC3C, 0x00000000, - 0xC40, 0x00000000, - 0xC44, 0x00000000, - 0xC48, 0x00000000, - 0xC4C, 0x00000000, - 0xC50, 0x00000020, - 0xC54, 0x00000000, - 0xC58, 0xD8020402, - 0xC5C, 0xDE000120, - 0xC68, 0x5979993F, - 0xC6C, 0x0000122A, - 0xC70, 0x99795979, - 0xC74, 0x99795979, - 0xC78, 0x99799979, - 0xC7C, 0x99791979, - 0xC80, 0x19791979, - 0xC84, 0x19791979, - 0xC88, 0x00000000, - 0xC8C, 0x07000000, - 0xC94, 0x01000100, - 0xC98, 0x201C8000, - 0xC9C, 0x00000000, - 0xCA0, 0x0000A555, - 0xCA4, 0x08040201, - 0xCA8, 0x80402010, - 0xCAC, 0x00000000, - 0xCB0, 0x77777777, - 0xCB4, 0x00007777, - 0xCB8, 0x00000000, - 0xCBC, 0x00000000, - 0xCC0, 0x00000000, - 0xCC4, 0x00000000, - 0xCC8, 0x00000000, - 0xCCC, 0x00000000, - 0xCD0, 0x00000000, - 0xCD4, 0x00000000, - 0xCD8, 0x00000000, - 0xCDC, 0x00000000, - 0xCE0, 0x00000000, - 0xCE4, 0x00000000, - 0xCE8, 0x00000000, - 0xCEC, 0x00000000, - 0xE00, 0x00000007, - 0xE04, 0x00000020, - 0xE08, 0x60403231, - 0xE0C, 0x00012345, - 0xE10, 0x00000100, - 0xE14, 0x01000000, - 0xE18, 0x00000000, - 0xE1C, 0x40040053, - 0xE20, 0x40020103, - 0xE24, 0x00000000, - 0xE28, 0x00000000, - 0xE2C, 0x00000000, - 0xE30, 0x00000000, - 0xE34, 0x00000000, - 0xE38, 0x00000000, - 0xE3C, 0x00000000, - 0xE40, 0x00000000, - 0xE44, 0x00000000, - 0xE48, 0x00000000, - 0xE4C, 0x00000000, - 0xE50, 0x00000020, - 0xE54, 0x00000000, - 0xE58, 0xD8020402, - 0xE5C, 0xDE000120, - 0xE68, 0x5979993F, - 0xE6C, 0x0000122A, - 0xE70, 0x99795979, - 0xE74, 0x99795979, - 0xE78, 0x99799979, - 0xE7C, 0x99791979, - 0xE80, 0x19791979, - 0xE84, 0x19791979, - 0xE88, 0x00000000, - 0xE8C, 0x07000000, - 0xE94, 0x01000100, - 0xE98, 0x201C8000, - 0xE9C, 0x00000000, - 0xEA0, 0x0000A555, - 0xEA4, 0x08040201, - 0xEA8, 0x80402010, - 0xEAC, 0x00000000, - 0xEB0, 0x77777777, - 0xEB4, 0x00007777, - 0xEB8, 0x00000000, - 0xEBC, 0x00000000, - 0xEC0, 0x00000000, - 0xEC4, 0x00000000, - 0xEC8, 0x00000000, - 0xECC, 0x00000000, - 0xED0, 0x00000000, - 0xED4, 0x00000000, - 0xED8, 0x00000000, - 0xEDC, 0x00000000, - 0xEE0, 0x00000000, - 0xEE4, 0x00000000, - 0xEE8, 0x00000000, - 0xEEC, 0x00000000, - 0x1900, 0x00000000, - 0x1904, 0x00238000, - 0x1908, 0x00000000, - 0x190C, 0x00000000, - 0x1910, 0x00000000, - 0x1914, 0x00000000, - 0x1918, 0x00000000, - 0x191C, 0x00000000, - 0x1920, 0x00000000, - 0x1924, 0x00000000, - 0x1928, 0x00000000, - 0x192C, 0x00000000, - 0x1930, 0x00000000, - 0x1934, 0x00000000, - 0x1938, 0x00000000, - 0x193C, 0x00000000, - 0x1940, 0x00000000, - 0x1944, 0x00000000, - 0x1948, 0x00000000, - 0x194C, 0x00000000, - 0x1950, 0x00000000, - 0x1954, 0x00000000, - 0x1958, 0x00000000, - 0x195C, 0x00000000, - 0x1960, 0x00000000, - 0x1964, 0x00000000, - 0x1968, 0x00000000, - 0x196C, 0x00000000, - 0x1970, 0x00000000, - 0x1974, 0x00000000, - 0x1978, 0x00000000, - 0x197C, 0x00000000, - 0x1980, 0x00000000, - 0x1984, 0x03000000, - 0x1988, 0x21401E88, - 0x198C, 0x00004000, - 0x1990, 0x00000000, - 0x1994, 0x00000000, - 0x1998, 0x00000053, - 0x199C, 0x00000000, - 0x19A0, 0x00000000, - 0x19A4, 0x00000000, - 0x19A8, 0x00000000, - 0x19AC, 0x0E47E47F, - 0x19B0, 0x00000000, - 0x19B4, 0x0E47E47F, - 0x19B8, 0x00000000, - 0x19BC, 0x00000000, - 0x19C0, 0x00000000, - 0x19C4, 0x00000000, - 0x19C8, 0x00000000, - 0x19CC, 0x00000000, - 0x19D0, 0x00000000, - 0x19D4, 0xAAAAAAAA, - 0x19D8, 0x00000AAA, - 0x19DC, 0x133E0F37, - 0x19E0, 0x00000000, - 0x19E4, 0x00000000, - 0x19E8, 0x00000000, - 0x19EC, 0x00000000, - 0x19F0, 0x00000000, - 0x19F4, 0x00000000, - 0x19F8, 0x01A00000, - 0x19FC, 0x00000000, - 0x1C00, 0x00000100, - 0x1C04, 0x01000000, - 0x1C08, 0x00000100, - 0x1C0C, 0x01000000, - 0x1C10, 0x00000100, - 0x1C14, 0x01000000, - 0x1C18, 0x00000100, - 0x1C1C, 0x01000000, - 0x1C20, 0x00000100, - 0x1C24, 0x01000000, - 0x1C28, 0x00000100, - 0x1C2C, 0x01000000, - 0x1C30, 0x00000100, - 0x1C34, 0x01000000, - 0x1C38, 0x00000000, - 0x1C3C, 0x00000000, - 0x1C40, 0x000C0100, - 0x1C44, 0x000000F3, - 0x1C48, 0x1A8249A8, - 0x1C4C, 0x1461C826, - 0x1C50, 0x0001469E, - 0x1C54, 0x58D158D1, - 0x1C58, 0x04490088, - 0x1C5C, 0x04004400, - 0x1C60, 0x00000000, - 0x1C64, 0x04004400, - 0x1C68, 0x00000100, - 0x1C6C, 0x01000000, - 0x1C70, 0x00000100, - 0x1C74, 0x01000000, - 0x1C78, 0x00000000, - 0x1C7C, 0x00000010, - 0x1C80, 0x5FFF5FFF, - 0x1C84, 0x5FFF5FFF, - 0x1C88, 0x5FFF5FFF, - 0x1C8C, 0x5FFF5FFF, - 0x1C90, 0x5FFF5FFF, - 0x1C94, 0x5FFF5FFF, - 0x1C98, 0x5FFF5FFF, - 0x1C9C, 0x5FFF5FFF, - 0x1CA0, 0x00000100, - 0x1CA4, 0x01000000, - 0x1CA8, 0x00000100, - 0x1CAC, 0x5FFF5FFF, - 0x1CB0, 0x00000100, - 0x1CB4, 0x01000000, - 0x1CB8, 0x00000000, - 0x1CBC, 0x00000000, - 0x1CC0, 0x00000100, - 0x1CC4, 0x01000000, - 0x1CC8, 0x00000100, - 0x1CCC, 0x01000000, - 0x1CD0, 0x00000100, - 0x1CD4, 0x01000000, - 0x1CD8, 0x00000100, - 0x1CDC, 0x01000000, - 0x1CE0, 0x00000100, - 0x1CE4, 0x01000000, - 0x1CE8, 0x00000100, - 0x1CEC, 0x01000000, - 0x1CF0, 0x00000100, - 0x1CF4, 0x01000000, - 0x1CF8, 0x00000000, - 0x1CFC, 0x00000000, - 0xC60, 0x70038040, - 0xC60, 0x70038040, - 0xC60, 0x70146040, - 0xC60, 0x70246040, - 0xC60, 0x70346040, - 0xC60, 0x70446040, - 0xC60, 0x70532040, - 0xC60, 0x70646040, - 0xC60, 0x70738040, - 0xC60, 0x70838040, - 0xC60, 0x70938040, - 0xC60, 0x70A38040, - 0xC60, 0x70B36040, - 0xC60, 0x70C06040, - 0xC60, 0x70D06040, - 0xC60, 0x70E76040, - 0xC60, 0x70F06040, - 0xE60, 0x70038040, - 0xE60, 0x70038040, - 0xE60, 0x70146040, - 0xE60, 0x70246040, - 0xE60, 0x70346040, - 0xE60, 0x70446040, - 0xE60, 0x70532040, - 0xE60, 0x70646040, - 0xE60, 0x70738040, - 0xE60, 0x70838040, - 0xE60, 0x70938040, - 0xE60, 0x70A38040, - 0xE60, 0x70B36040, - 0xE60, 0x70C06040, - 0xE60, 0x70D06040, - 0xE60, 0x70E76040, - 0xE60, 0x70F06040, - 0xC64, 0x00800000, - 0xC64, 0x08800001, - 0xC64, 0x00800002, - 0xC64, 0x00800003, - 0xC64, 0x00800004, - 0xC64, 0x00800005, - 0xC64, 0x00800006, - 0xC64, 0x08800007, - 0xC64, 0x00004000, - 0xE64, 0x00800000, - 0xE64, 0x08800001, - 0xE64, 0x00800002, - 0xE64, 0x00800003, - 0xE64, 0x00800004, - 0xE64, 0x00800005, - 0xE64, 0x00800006, - 0xE64, 0x08800007, - 0xE64, 0x00004000, - 0x1B00, 0xF8000008, - 0x1B00, 0xF80A7008, - 0x1B00, 0xF8015008, - 0x1B00, 0xF8000008, - 0x1B04, 0xE24629D2, - 0x1B08, 0x00000080, - 0x1B0C, 0x00000000, - 0x1B10, 0x00011C00, - 0x1B14, 0x00000000, - 0x1B18, 0x00292903, - 0x1B1C, 0xA2193C32, - 0x1B20, 0x01840008, - 0x1B24, 0x01860008, - 0x1B28, 0x80060300, - 0x1B2C, 0x00000003, - 0x1B30, 0x20000000, - 0x1B34, 0x00000800, - 0x1B3C, 0x20000000, - 0x1BC0, 0x01000000, - 0x1BCC, 0x00000000, - 0x1B00, 0xF800000A, - 0x1B1C, 0xA2193C32, - 0x1B20, 0x01840008, - 0x1B24, 0x01860008, - 0x1B28, 0x80060300, - 0x1B2C, 0x00000003, - 0x1B30, 0x20000000, - 0x1B34, 0x00000800, - 0x1B3C, 0x20000000, - 0x1BC0, 0x01000000, - 0x1BCC, 0x00000000, - 0x1B00, 0xF8000000, - 0x1B80, 0x00000007, - 0x1B80, 0x090A0005, - 0x1B80, 0x090A0007, - 0x1B80, 0x0FFE0015, - 0x1B80, 0x0FFE0017, - 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0x1B80, 0x53001165, - 0x1B80, 0x53001167, - 0x1B80, 0x57F71175, - 0x1B80, 0x57F71177, - 0x1B80, 0x58211185, - 0x1B80, 0x58211187, - 0x1B80, 0x592E1195, - 0x1B80, 0x592E1197, - 0x1B80, 0x5A3811A5, - 0x1B80, 0x5A3811A7, - 0x1B80, 0x5B4111B5, - 0x1B80, 0x5B4111B7, - 0x1B80, 0x000711C5, - 0x1B80, 0x000711C7, - 0x1B80, 0x5C0011D5, - 0x1B80, 0x5C0011D7, - 0x1B80, 0x4B0011E5, - 0x1B80, 0x4B0011E7, - 0x1B80, 0x4E8F11F5, - 0x1B80, 0x4E8F11F7, - 0x1B80, 0x4F151205, - 0x1B80, 0x4F151207, - 0x1B80, 0x00041215, - 0x1B80, 0x00041217, - 0x1B80, 0xE1B51225, - 0x1B80, 0xE1B51227, - 0x1B80, 0xAB001235, - 0x1B80, 0xAB001237, - 0x1B80, 0x00011245, - 0x1B80, 0x00011247, - 0x1B80, 0x6C001255, - 0x1B80, 0x6C001257, - 0x1B80, 0x00061265, - 0x1B80, 0x00061267, - 0x1B80, 0x53001275, - 0x1B80, 0x53001277, - 0x1B80, 0x57F71285, - 0x1B80, 0x57F71287, - 0x1B80, 0x58211295, - 0x1B80, 0x58211297, - 0x1B80, 0x592E12A5, - 0x1B80, 0x592E12A7, - 0x1B80, 0x5A3812B5, - 0x1B80, 0x5A3812B7, - 0x1B80, 0x5B4112C5, - 0x1B80, 0x5B4112C7, - 0x1B80, 0x000712D5, - 0x1B80, 0x000712D7, - 0x1B80, 0x5C0012E5, - 0x1B80, 0x5C0012E7, - 0x1B80, 0x4B4012F5, - 0x1B80, 0x4B4012F7, - 0x1B80, 0x4E971305, - 0x1B80, 0x4E971307, - 0x1B80, 0x4F111315, - 0x1B80, 0x4F111317, - 0x1B80, 0x00041325, - 0x1B80, 0x00041327, - 0x1B80, 0xE1B51335, - 0x1B80, 0xE1B51337, - 0x1B80, 0xAB001345, - 0x1B80, 0xAB001347, - 0x1B80, 0x8B001355, - 0x1B80, 0x8B001357, - 0x1B80, 0xAB001365, - 0x1B80, 0xAB001367, - 0x1B80, 0x8A191375, - 0x1B80, 0x8A191377, - 0x1B80, 0x301D1385, - 0x1B80, 0x301D1387, - 0x1B80, 0x00011395, - 0x1B80, 0x00011397, - 0x1B80, 0x6C0113A5, - 0x1B80, 0x6C0113A7, - 0x1B80, 0x000613B5, - 0x1B80, 0x000613B7, - 0x1B80, 0x530113C5, - 0x1B80, 0x530113C7, - 0x1B80, 0x57F713D5, - 0x1B80, 0x57F713D7, - 0x1B80, 0x582113E5, - 0x1B80, 0x582113E7, - 0x1B80, 0x592E13F5, - 0x1B80, 0x592E13F7, - 0x1B80, 0x5A381405, - 0x1B80, 0x5A381407, - 0x1B80, 0x5B411415, - 0x1B80, 0x5B411417, - 0x1B80, 0x00071425, - 0x1B80, 0x00071427, - 0x1B80, 0x5C001435, - 0x1B80, 0x5C001437, - 0x1B80, 0x4B001445, - 0x1B80, 0x4B001447, - 0x1B80, 0x4E871455, - 0x1B80, 0x4E871457, - 0x1B80, 0x4F111465, - 0x1B80, 0x4F111467, - 0x1B80, 0x00041475, - 0x1B80, 0x00041477, - 0x1B80, 0xE1B51485, - 0x1B80, 0xE1B51487, - 0x1B80, 0xAB001495, - 0x1B80, 0xAB001497, - 0x1B80, 0x000614A5, - 0x1B80, 0x000614A7, - 0x1B80, 0x577714B5, - 0x1B80, 0x577714B7, - 0x1B80, 0x000714C5, - 0x1B80, 0x000714C7, - 0x1B80, 0x4E8614D5, - 0x1B80, 0x4E8614D7, - 0x1B80, 0x000414E5, - 0x1B80, 0x000414E7, - 0x1B80, 0x000114F5, - 0x1B80, 0x000114F7, - 0x1B80, 0x00011505, - 0x1B80, 0x00011507, - 0x1B80, 0x7B241515, - 0x1B80, 0x7B241517, - 0x1B80, 0x7A401525, - 0x1B80, 0x7A401527, - 0x1B80, 0x79001535, - 0x1B80, 0x79001537, - 0x1B80, 0x55031545, - 0x1B80, 0x55031547, - 0x1B80, 0x315D1555, - 0x1B80, 0x315D1557, - 0x1B80, 0x7B1C1565, - 0x1B80, 0x7B1C1567, - 0x1B80, 0x7A401575, - 0x1B80, 0x7A401577, - 0x1B80, 0x550B1585, - 0x1B80, 0x550B1587, - 0x1B80, 0x315D1595, - 0x1B80, 0x315D1597, - 0x1B80, 0x7B2015A5, - 0x1B80, 0x7B2015A7, - 0x1B80, 0x7A0015B5, - 0x1B80, 0x7A0015B7, - 0x1B80, 0x551315C5, - 0x1B80, 0x551315C7, - 0x1B80, 0x740115D5, - 0x1B80, 0x740115D7, - 0x1B80, 0x740015E5, - 0x1B80, 0x740015E7, - 0x1B80, 0x8E0015F5, - 0x1B80, 0x8E0015F7, - 0x1B80, 0x00011605, - 0x1B80, 0x00011607, - 0x1B80, 0x57021615, - 0x1B80, 0x57021617, - 0x1B80, 0x57001625, - 0x1B80, 0x57001627, - 0x1B80, 0x97001635, - 0x1B80, 0x97001637, - 0x1B80, 0x00011645, - 0x1B80, 0x00011647, - 0x1B80, 0x4F781655, - 0x1B80, 0x4F781657, - 0x1B80, 0x53881665, - 0x1B80, 0x53881667, - 0x1B80, 0xE1731675, - 0x1B80, 0xE1731677, - 0x1B80, 0x54801685, - 0x1B80, 0x54801687, - 0x1B80, 0x54001695, - 0x1B80, 0x54001697, - 0x1B80, 0xE17316A5, - 0x1B80, 0xE17316A7, - 0x1B80, 0x548116B5, - 0x1B80, 0x548116B7, - 0x1B80, 0x540016C5, - 0x1B80, 0x540016C7, - 0x1B80, 0xE17316D5, - 0x1B80, 0xE17316D7, - 0x1B80, 0x548216E5, - 0x1B80, 0x548216E7, - 0x1B80, 0x540016F5, - 0x1B80, 0x540016F7, - 0x1B80, 0xE17E1705, - 0x1B80, 0xE17E1707, - 0x1B80, 0xBF1D1715, - 0x1B80, 0xBF1D1717, - 0x1B80, 0x301D1725, - 0x1B80, 0x301D1727, - 0x1B80, 0xE1511735, - 0x1B80, 0xE1511737, - 0x1B80, 0xE1561745, - 0x1B80, 0xE1561747, - 0x1B80, 0xE15A1755, - 0x1B80, 0xE15A1757, - 0x1B80, 0xE1611765, - 0x1B80, 0xE1611767, - 0x1B80, 0xE1C71775, - 0x1B80, 0xE1C71777, - 0x1B80, 0x55131785, - 0x1B80, 0x55131787, - 0x1B80, 0xE15D1795, - 0x1B80, 0xE15D1797, - 0x1B80, 0x551517A5, - 0x1B80, 0x551517A7, - 0x1B80, 0xE16117B5, - 0x1B80, 0xE16117B7, - 0x1B80, 0xE1C717C5, - 0x1B80, 0xE1C717C7, - 0x1B80, 0x000117D5, - 0x1B80, 0x000117D7, - 0x1B80, 0x54BF17E5, - 0x1B80, 0x54BF17E7, - 0x1B80, 0x54C017F5, - 0x1B80, 0x54C017F7, - 0x1B80, 0x54A31805, - 0x1B80, 0x54A31807, - 0x1B80, 0x54C11815, - 0x1B80, 0x54C11817, - 0x1B80, 0x54A41825, - 0x1B80, 0x54A41827, - 0x1B80, 0x4C181835, - 0x1B80, 0x4C181837, - 0x1B80, 0xBF071845, - 0x1B80, 0xBF071847, - 0x1B80, 0x54C21855, - 0x1B80, 0x54C21857, - 0x1B80, 0x54A41865, - 0x1B80, 0x54A41867, - 0x1B80, 0xBF041875, - 0x1B80, 0xBF041877, - 0x1B80, 0x54C11885, - 0x1B80, 0x54C11887, - 0x1B80, 0x54A31895, - 0x1B80, 0x54A31897, - 0x1B80, 0xBF0118A5, - 0x1B80, 0xBF0118A7, - 0x1B80, 0xE1D518B5, - 0x1B80, 0xE1D518B7, - 0x1B80, 0x54DF18C5, - 0x1B80, 0x54DF18C7, - 0x1B80, 0x000118D5, - 0x1B80, 0x000118D7, - 0x1B80, 0x54BF18E5, - 0x1B80, 0x54BF18E7, - 0x1B80, 0x54E518F5, - 0x1B80, 0x54E518F7, - 0x1B80, 0x050A1905, - 0x1B80, 0x050A1907, - 0x1B80, 0x54DF1915, - 0x1B80, 0x54DF1917, - 0x1B80, 0x00011925, - 0x1B80, 0x00011927, - 0x1B80, 0x7F201935, - 0x1B80, 0x7F201937, - 0x1B80, 0x7E001945, - 0x1B80, 0x7E001947, - 0x1B80, 0x7D001955, - 0x1B80, 0x7D001957, - 0x1B80, 0x55011965, - 0x1B80, 0x55011967, - 0x1B80, 0x5C311975, - 0x1B80, 0x5C311977, - 0x1B80, 0xE15D1985, - 0x1B80, 0xE15D1987, - 0x1B80, 0xE1611995, - 0x1B80, 0xE1611997, - 0x1B80, 0x548019A5, - 0x1B80, 0x548019A7, - 0x1B80, 0x540019B5, - 0x1B80, 0x540019B7, - 0x1B80, 0xE15D19C5, - 0x1B80, 0xE15D19C7, - 0x1B80, 0xE16119D5, - 0x1B80, 0xE16119D7, - 0x1B80, 0x548119E5, - 0x1B80, 0x548119E7, - 0x1B80, 0x540019F5, - 0x1B80, 0x540019F7, - 0x1B80, 0xE15D1A05, - 0x1B80, 0xE15D1A07, - 0x1B80, 0xE1611A15, - 0x1B80, 0xE1611A17, - 0x1B80, 0x54821A25, - 0x1B80, 0x54821A27, - 0x1B80, 0x54001A35, - 0x1B80, 0x54001A37, - 0x1B80, 0xE17E1A45, - 0x1B80, 0xE17E1A47, - 0x1B80, 0xBFE91A55, - 0x1B80, 0xBFE91A57, - 0x1B80, 0x301D1A65, - 0x1B80, 0x301D1A67, - 0x1B80, 0x00231A75, - 0x1B80, 0x00231A77, - 0x1B80, 0x7B201A85, - 0x1B80, 0x7B201A87, - 0x1B80, 0x7A001A95, - 0x1B80, 0x7A001A97, - 0x1B80, 0x79001AA5, - 0x1B80, 0x79001AA7, - 0x1B80, 0xE1CB1AB5, - 0x1B80, 0xE1CB1AB7, - 0x1B80, 0x00021AC5, - 0x1B80, 0x00021AC7, - 0x1B80, 0x00011AD5, - 0x1B80, 0x00011AD7, - 0x1B80, 0x00221AE5, - 0x1B80, 0x00221AE7, - 0x1B80, 0x7B201AF5, - 0x1B80, 0x7B201AF7, - 0x1B80, 0x7A001B05, - 0x1B80, 0x7A001B07, - 0x1B80, 0x79001B15, - 0x1B80, 0x79001B17, - 0x1B80, 0xE1CB1B25, - 0x1B80, 0xE1CB1B27, - 0x1B80, 0x00021B35, - 0x1B80, 0x00021B37, - 0x1B80, 0x00011B45, - 0x1B80, 0x00011B47, - 0x1B80, 0x74021B55, - 0x1B80, 0x74021B57, - 0x1B80, 0x003F1B65, - 0x1B80, 0x003F1B67, - 0x1B80, 0x74001B75, - 0x1B80, 0x74001B77, - 0x1B80, 0x00021B85, - 0x1B80, 0x00021B87, - 0x1B80, 0x00011B95, - 0x1B80, 0x00011B97, - 0x1B80, 0x4D041BA5, - 0x1B80, 0x4D041BA7, - 0x1B80, 0x2EF81BB5, - 0x1B80, 0x2EF81BB7, - 0x1B80, 0x00001BC5, - 0x1B80, 0x00001BC7, - 0x1B80, 0x23301BD5, - 0x1B80, 0x23301BD7, - 0x1B80, 0x00241BE5, - 0x1B80, 0x00241BE7, - 0x1B80, 0x23E01BF5, - 0x1B80, 0x23E01BF7, - 0x1B80, 0x003F1C05, - 0x1B80, 0x003F1C07, - 0x1B80, 0x23FC1C15, - 0x1B80, 0x23FC1C17, - 0x1B80, 0xBFCE1C25, - 0x1B80, 0xBFCE1C27, - 0x1B80, 0x2EF01C35, - 0x1B80, 0x2EF01C37, - 0x1B80, 0x00001C45, - 0x1B80, 0x00001C47, - 0x1B80, 0x4D001C55, - 0x1B80, 0x4D001C57, - 0x1B80, 0x00011C65, - 0x1B80, 0x00011C67, - 0x1B80, 0x549F1C75, - 0x1B80, 0x549F1C77, - 0x1B80, 0x54FF1C85, - 0x1B80, 0x54FF1C87, - 0x1B80, 0x54001C95, - 0x1B80, 0x54001C97, - 0x1B80, 0x00011CA5, - 0x1B80, 0x00011CA7, - 0x1B80, 0x5C311CB5, - 0x1B80, 0x5C311CB7, - 0x1B80, 0x07141CC5, - 0x1B80, 0x07141CC7, - 0x1B80, 0x54001CD5, - 0x1B80, 0x54001CD7, - 0x1B80, 0x5C321CE5, - 0x1B80, 0x5C321CE7, - 0x1B80, 0x00011CF5, - 0x1B80, 0x00011CF7, - 0x1B80, 0x5C321D05, - 0x1B80, 0x5C321D07, - 0x1B80, 0x07141D15, - 0x1B80, 0x07141D17, - 0x1B80, 0x54001D25, - 0x1B80, 0x54001D27, - 0x1B80, 0x5C311D35, - 0x1B80, 0x5C311D37, - 0x1B80, 0x00011D45, - 0x1B80, 0x00011D47, - 0x1B80, 0x4C981D55, - 0x1B80, 0x4C981D57, - 0x1B80, 0x4C181D65, - 0x1B80, 0x4C181D67, - 0x1B80, 0x00011D75, - 0x1B80, 0x00011D77, - 0x1B80, 0x5C321D85, - 0x1B80, 0x5C321D87, - 0x1B80, 0x62841D95, - 0x1B80, 0x62841D97, - 0x1B80, 0x66861DA5, - 0x1B80, 0x66861DA7, - 0x1B80, 0x6C031DB5, - 0x1B80, 0x6C031DB7, - 0x1B80, 0x7B201DC5, - 0x1B80, 0x7B201DC7, - 0x1B80, 0x7A001DD5, - 0x1B80, 0x7A001DD7, - 0x1B80, 0x79001DE5, - 0x1B80, 0x79001DE7, - 0x1B80, 0x7F201DF5, - 0x1B80, 0x7F201DF7, - 0x1B80, 0x7E001E05, - 0x1B80, 0x7E001E07, - 0x1B80, 0x7D001E15, - 0x1B80, 0x7D001E17, - 0x1B80, 0x09011E25, - 0x1B80, 0x09011E27, - 0x1B80, 0x0C011E35, - 0x1B80, 0x0C011E37, - 0x1B80, 0x0BA61E45, - 0x1B80, 0x0BA61E47, - 0x1B80, 0x00011E55, - 0x1B80, 0x00011E57, - 0x1B80, 0x00000006, - 0x1B80, 0x00000002, - -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigBB_PHY_8822B(pDM_Odm, v1, bMaskDWord, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8822B_PHY_REG(void) -{ - return 101; -} - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type12.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type12[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x22242628, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x30323436, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x34361820, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x26283032, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x18202224, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x22242628, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x30323436, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x34361820, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x26283032, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x18202224 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type12)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type12; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type15.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type15[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type15)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type15; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type16.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type16[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type16)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type16; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type17.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type17[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type17)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type17; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type2.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type2[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type2)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type2; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type3.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type3[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type3)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type3; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type4.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type4[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x38404244, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x42444648, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424446, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x32343638, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x40424446, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424446, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x44462830, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x36384042, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x38404244, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x42444648, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424446, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x32343638, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x40424446, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424446, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x44462830, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x36384042, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type4)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type4; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -/****************************************************************************** -* PHY_REG_PG_type5.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_PHY_REG_PG_type5[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, - 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, - 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, - 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, - 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 -}; - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type5)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type5; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5\n")); - - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; - - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; - - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); -#endif - } -} - - - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_AGC_TAB[] = { + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xDC000003, + 0x81C, 0xDB020003, + 0x81C, 0xDA040003, + 0x81C, 0xD9060003, + 0x81C, 0xD8080003, + 0x81C, 0xD70A0003, + 0x81C, 0xD60C0003, + 0x81C, 0xD50E0003, + 0x81C, 0xD4100003, + 0x81C, 0xD3120003, + 0x81C, 0xD2140003, + 0x81C, 0xD1160003, + 0x81C, 0xD0180003, + 0x81C, 0xB41A0003, + 0x81C, 0xB31C0003, + 0x81C, 0xB21E0003, + 0x81C, 0xB1200003, + 0x81C, 0xB0220003, + 0x81C, 0xAF240003, + 0x81C, 0xAE260003, + 0x81C, 0xAD280003, + 0x81C, 0xAC2A0003, + 0x81C, 0xAB2C0003, + 0x81C, 0x8C2E0003, + 0x81C, 0x8B300003, + 0x81C, 0x8A320003, + 0x81C, 0x89340003, + 0x81C, 0x88360003, + 0x81C, 0x87380003, + 0x81C, 0x863A0003, + 0x81C, 0x853C0003, + 0x81C, 0x693E0003, + 0x81C, 0x68400003, + 0x81C, 0x67420003, + 0x81C, 0x66440003, + 0x81C, 0x65460003, + 0x81C, 0x48480003, + 0x81C, 0x474A0003, + 0x81C, 0x464C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x27540003, + 0x81C, 0x26560003, + 0x81C, 0x25580003, + 0x81C, 0x245A0003, + 0x81C, 0x235C0003, + 0x81C, 0x045E0003, + 0x81C, 0x03600003, + 0x81C, 0x02620003, + 0x81C, 0x01640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFC000003, + 0x81C, 0xFB020003, + 0x81C, 0xFA040003, + 0x81C, 0xF9060003, + 0x81C, 0xF8080003, + 0x81C, 0xF70A0003, + 0x81C, 0xF60C0003, + 0x81C, 0xF50E0003, + 0x81C, 0xF4100003, + 0x81C, 0xF3120003, + 0x81C, 0xF2140003, + 0x81C, 0xF1160003, + 0x81C, 0xF0180003, + 0x81C, 0xEF1A0003, + 0x81C, 0xEE1C0003, + 0x81C, 0xED1E0003, + 0x81C, 0xEC200003, + 0x81C, 0xEB220003, + 0x81C, 0xEA240003, + 0x81C, 0xE9260003, + 0x81C, 0xE8280003, + 0x81C, 0xE72A0003, + 0x81C, 0xE62C0003, + 0x81C, 0xE52E0003, + 0x81C, 0xC8300003, + 0x81C, 0xC7320003, + 0x81C, 0xC6340003, + 0x81C, 0xC5360003, + 0x81C, 0xC4380003, + 0x81C, 0xC33A0003, + 0x81C, 0xC23C0003, + 0x81C, 0xC13E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0xA1460003, + 0x81C, 0xA0480003, + 0x81C, 0x684A0003, + 0x81C, 0x674C0003, + 0x81C, 0x664E0003, + 0x81C, 0x65500003, + 0x81C, 0x64520003, + 0x81C, 0x63540003, + 0x81C, 0x44560003, + 0x81C, 0x43580003, + 0x81C, 0x425A0003, + 0x81C, 0x415C0003, + 0x81C, 0x405E0003, + 0x81C, 0x23600003, + 0x81C, 0x22620003, + 0x81C, 0x21640003, + 0x81C, 0x03660003, + 0x81C, 0x02680003, + 0x81C, 0x016A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xC32C0103, + 0x81C, 0xC22E0103, + 0x81C, 0xC1300103, + 0x81C, 0xC0320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x06500103, + 0x81C, 0x05520103, + 0x81C, 0x04540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xC32C0103, + 0x81C, 0xC22E0103, + 0x81C, 0xC1300103, + 0x81C, 0xC0320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xC32C0103, + 0x81C, 0xC22E0103, + 0x81C, 0xC1300103, + 0x81C, 0xC0320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xE2360103, + 0x81C, 0xC5380103, + 0x81C, 0xC43A0103, + 0x81C, 0xC33C0103, + 0x81C, 0xC23E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0x834A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x64500103, + 0x81C, 0x63520103, + 0x81C, 0x62540103, + 0x81C, 0x61560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x065E0103, + 0x81C, 0x05600103, + 0x81C, 0x04620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFA000103, + 0x81C, 0xF9020103, + 0x81C, 0xF8040103, + 0x81C, 0xF7060103, + 0x81C, 0xF6080103, + 0x81C, 0xF50A0103, + 0x81C, 0xF40C0103, + 0x81C, 0xF30E0103, + 0x81C, 0xF2100103, + 0x81C, 0xF1120103, + 0x81C, 0xF0140103, + 0x81C, 0xEF160103, + 0x81C, 0xEE180103, + 0x81C, 0xED1A0103, + 0x81C, 0xEC1C0103, + 0x81C, 0xEB1E0103, + 0x81C, 0xEA200103, + 0x81C, 0xE9220103, + 0x81C, 0xE8240103, + 0x81C, 0xE7260103, + 0x81C, 0xE6280103, + 0x81C, 0xE52A0103, + 0x81C, 0xC42C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA4340103, + 0x81C, 0xA3360103, + 0x81C, 0xA2380103, + 0x81C, 0xA13A0103, + 0x81C, 0x833C0103, + 0x81C, 0x823E0103, + 0x81C, 0x81400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x434A0103, + 0x81C, 0x424C0103, + 0x81C, 0x414E0103, + 0x81C, 0x40500103, + 0x81C, 0x22520103, + 0x81C, 0x21540103, + 0x81C, 0x20560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xC6360103, + 0x81C, 0xC5380103, + 0x81C, 0xC43A0103, + 0x81C, 0xC33C0103, + 0x81C, 0xC23E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0x834A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x245A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x04620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x434A0103, + 0x81C, 0x424C0103, + 0x81C, 0x414E0103, + 0x81C, 0x40500103, + 0x81C, 0x22520103, + 0x81C, 0x21540103, + 0x81C, 0x20560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000103, + 0x81C, 0xF8020103, + 0x81C, 0xF7040103, + 0x81C, 0xF6060103, + 0x81C, 0xF5080103, + 0x81C, 0xF40A0103, + 0x81C, 0xF30C0103, + 0x81C, 0xF20E0103, + 0x81C, 0xF1100103, + 0x81C, 0xF0120103, + 0x81C, 0xEF140103, + 0x81C, 0xEE160103, + 0x81C, 0xED180103, + 0x81C, 0xEC1A0103, + 0x81C, 0xEB1C0103, + 0x81C, 0xEA1E0103, + 0x81C, 0xE9200103, + 0x81C, 0xE8220103, + 0x81C, 0xE7240103, + 0x81C, 0xE6260103, + 0x81C, 0xE5280103, + 0x81C, 0xE42A0103, + 0x81C, 0xE32C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA4340103, + 0x81C, 0xA3360103, + 0x81C, 0xA2380103, + 0x81C, 0xA13A0103, + 0x81C, 0xA03C0103, + 0x81C, 0x823E0103, + 0x81C, 0x81400103, + 0x81C, 0x80420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x604A0103, + 0x81C, 0x244C0103, + 0x81C, 0x234E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x05560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000103, + 0x81C, 0xFB020103, + 0x81C, 0xFA040103, + 0x81C, 0xF9060103, + 0x81C, 0xF8080103, + 0x81C, 0xF70A0103, + 0x81C, 0xF60C0103, + 0x81C, 0xF50E0103, + 0x81C, 0xF4100103, + 0x81C, 0xF3120103, + 0x81C, 0xF2140103, + 0x81C, 0xF1160103, + 0x81C, 0xF0180103, + 0x81C, 0xEF1A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xE1360103, + 0x81C, 0xC3380103, + 0x81C, 0xC23A0103, + 0x81C, 0xC13C0103, + 0x81C, 0xC03E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x82480103, + 0x81C, 0x814A0103, + 0x81C, 0x804C0103, + 0x81C, 0x634E0103, + 0x81C, 0x62500103, + 0x81C, 0x61520103, + 0x81C, 0x42540103, + 0x81C, 0x41560103, + 0x81C, 0x24580103, + 0x81C, 0x235A0103, + 0x81C, 0x225C0103, + 0x81C, 0x215E0103, + 0x81C, 0x20600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0xA0000000, 0x00000000, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x405A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 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0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x405A0203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x405A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 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0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x405A0203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000203, + 0x81C, 0xFC020203, + 0x81C, 0xFB040203, + 0x81C, 0xFA060203, + 0x81C, 0xF9080203, + 0x81C, 0xF80A0203, + 0x81C, 0xF70C0203, + 0x81C, 0xF60E0203, + 0x81C, 0xF5100203, + 0x81C, 0xF4120203, + 0x81C, 0xF3140203, + 0x81C, 0xF2160203, + 0x81C, 0xF1180203, + 0x81C, 0xF01A0203, + 0x81C, 0xEF1C0203, + 0x81C, 0xEE1E0203, + 0x81C, 0xED200203, + 0x81C, 0xEC220203, + 0x81C, 0xEB240203, + 0x81C, 0xEA260203, + 0x81C, 0xE9280203, + 0x81C, 0xE82A0203, + 0x81C, 0xE72C0203, + 0x81C, 0xE62E0203, + 0x81C, 0xE5300203, + 0x81C, 0xE4320203, + 0x81C, 0xE3340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x235A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xCA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x64420303, + 0x81C, 0x63440303, + 0x81C, 0x62460303, + 0x81C, 0x61480303, + 0x81C, 0x604A0303, + 0x81C, 0x414C0303, + 0x81C, 0x404E0303, + 0x81C, 0x06500303, + 0x81C, 0x05520303, + 0x81C, 0x04540303, + 0x81C, 0x03560303, + 0x81C, 0x02580303, + 0x81C, 0x015A0303, + 0x81C, 0x005C0303, + 0x81C, 0x005E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xCA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x64420303, + 0x81C, 0x63440303, + 0x81C, 0x62460303, + 0x81C, 0x61480303, + 0x81C, 0x604A0303, + 0x81C, 0x414C0303, + 0x81C, 0x404E0303, + 0x81C, 0x22500303, + 0x81C, 0x21520303, + 0x81C, 0x20540303, + 0x81C, 0x03560303, + 0x81C, 0x02580303, + 0x81C, 0x015A0303, + 0x81C, 0x005C0303, + 0x81C, 0x005E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x225A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xCA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x64420303, + 0x81C, 0x63440303, + 0x81C, 0x62460303, + 0x81C, 0x61480303, + 0x81C, 0x604A0303, + 0x81C, 0x414C0303, + 0x81C, 0x404E0303, + 0x81C, 0x22500303, + 0x81C, 0x21520303, + 0x81C, 0x20540303, + 0x81C, 0x03560303, + 0x81C, 0x02580303, + 0x81C, 0x015A0303, + 0x81C, 0x005C0303, + 0x81C, 0x005E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xC23C0303, + 0x81C, 0xC13E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x64500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000303, + 0x81C, 0xF8020303, + 0x81C, 0xF7040303, + 0x81C, 0xF6060303, + 0x81C, 0xF5080303, + 0x81C, 0xF40A0303, + 0x81C, 0xF30C0303, + 0x81C, 0xF20E0303, + 0x81C, 0xF1100303, + 0x81C, 0xF0120303, + 0x81C, 0xEF140303, + 0x81C, 0xEE160303, + 0x81C, 0xED180303, + 0x81C, 0xEC1A0303, + 0x81C, 0xEB1C0303, + 0x81C, 0xEA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, + 0x81C, 0xC0320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x64420303, + 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0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xE0360303, + 0x81C, 0xC3380303, + 0x81C, 0xC23A0303, + 0x81C, 0xC13C0303, + 0x81C, 0xC03E0303, + 0x81C, 0xA3400303, + 0x81C, 0xA2420303, + 0x81C, 0xA1440303, + 0x81C, 0xA0460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x644E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x24560303, + 0x81C, 0x23580303, + 0x81C, 0x225A0303, + 0x81C, 0x215C0303, + 0x81C, 0x055E0303, + 0x81C, 0x04600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x225A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF6000403, + 0x81C, 0xF5020403, + 0x81C, 0xF4040403, + 0x81C, 0xF3060403, + 0x81C, 0xF2080403, + 0x81C, 0xF10A0403, + 0x81C, 0xF00C0403, + 0x81C, 0xEF0E0403, + 0x81C, 0xD6100403, + 0x81C, 0xD5120403, + 0x81C, 0xD4140403, + 0x81C, 0xD3160403, + 0x81C, 0xD2180403, + 0x81C, 0xD11A0403, + 0x81C, 0xD01C0403, + 0x81C, 0xCF1E0403, + 0x81C, 0x95200403, + 0x81C, 0x94220403, + 0x81C, 0x93240403, + 0x81C, 0x92260403, + 0x81C, 0x91280403, + 0x81C, 0x902A0403, + 0x81C, 0x8F2C0403, + 0x81C, 0x8E2E0403, + 0x81C, 0x8D300403, + 0x81C, 0x8C320403, + 0x81C, 0x8B340403, + 0x81C, 0x8A360403, + 0x81C, 0x89380403, + 0x81C, 0x883A0403, + 0x81C, 0x873C0403, + 0x81C, 0x863E0403, + 0x81C, 0x68400403, + 0x81C, 0x67420403, + 0x81C, 0x66440403, + 0x81C, 0x65460403, + 0x81C, 0x64480403, + 0x81C, 0x634A0403, + 0x81C, 0x484C0403, + 0x81C, 0x474E0403, + 0x81C, 0x46500403, + 0x81C, 0x45520403, + 0x81C, 0x44540403, + 0x81C, 0x27560403, + 0x81C, 0x26580403, + 0x81C, 0x255A0403, + 0x81C, 0x245C0403, + 0x81C, 0x235E0403, + 0x81C, 0x04600403, + 0x81C, 0x03620403, + 0x81C, 0x02640403, + 0x81C, 0x01660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000503, + 0x81C, 0xFC020503, + 0x81C, 0xFB040503, + 0x81C, 0xFA060503, + 0x81C, 0xF9080503, + 0x81C, 0xF80A0503, + 0x81C, 0xF70C0503, + 0x81C, 0xF60E0503, + 0x81C, 0xF5100503, + 0x81C, 0xF4120503, + 0x81C, 0xF3140503, + 0x81C, 0xF2160503, + 0x81C, 0xF1180503, + 0x81C, 0xF01A0503, + 0x81C, 0xEE1C0503, + 0x81C, 0xED1E0503, + 0x81C, 0xEC200503, + 0x81C, 0xEB220503, + 0x81C, 0xEA240503, + 0x81C, 0xE9260503, + 0x81C, 0xE8280503, + 0x81C, 0xE72A0503, + 0x81C, 0xE62C0503, + 0x81C, 0xE52E0503, + 0x81C, 0xE4300503, + 0x81C, 0xE3320503, + 0x81C, 0xE2340503, + 0x81C, 0xC5360503, + 0x81C, 0xC4380503, + 0x81C, 0xC33A0503, + 0x81C, 0xC23C0503, + 0x81C, 0xA53E0503, + 0x81C, 0xA4400503, + 0x81C, 0xA3420503, + 0x81C, 0xA2440503, + 0x81C, 0xA1460503, + 0x81C, 0x83480503, + 0x81C, 0x824A0503, + 0x81C, 0x814C0503, + 0x81C, 0x804E0503, + 0x81C, 0x63500503, + 0x81C, 0x62520503, + 0x81C, 0x61540503, + 0x81C, 0x43560503, + 0x81C, 0x42580503, + 0x81C, 0x415A0503, + 0x81C, 0x405C0503, + 0x81C, 0x225E0503, + 0x81C, 0x21600503, + 0x81C, 0x20620503, + 0x81C, 0x03640503, + 0x81C, 0x02660503, + 0x81C, 0x01680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBE000503, + 0x81C, 0xBD020503, + 0x81C, 0xBC040503, + 0x81C, 0xBB060503, + 0x81C, 0xBA080503, + 0x81C, 0xB90A0503, + 0x81C, 0xB80C0503, + 0x81C, 0xB70E0503, + 0x81C, 0xB6100503, + 0x81C, 0xB5120503, + 0x81C, 0xB4140503, + 0x81C, 0xB3160503, + 0x81C, 0xB2180503, + 0x81C, 0xB11A0503, + 0x81C, 0xB01C0503, + 0x81C, 0xAF1E0503, + 0x81C, 0xAE200503, + 0x81C, 0xAD220503, + 0x81C, 0xAC240503, + 0x81C, 0xAB260503, + 0x81C, 0x8D280503, + 0x81C, 0x8C2A0503, + 0x81C, 0x8B2C0503, + 0x81C, 0x8A2E0503, + 0x81C, 0x89300503, + 0x81C, 0x88320503, + 0x81C, 0x6A340503, + 0x81C, 0x69360503, + 0x81C, 0x68380503, + 0x81C, 0x673A0503, + 0x81C, 0x663C0503, + 0x81C, 0x653E0503, + 0x81C, 0x64400503, + 0x81C, 0x63420503, + 0x81C, 0x62440503, + 0x81C, 0x61460503, + 0x81C, 0x60480503, + 0x81C, 0x424A0503, + 0x81C, 0x414C0503, + 0x81C, 0x404E0503, + 0x81C, 0x06500503, + 0x81C, 0x05520503, + 0x81C, 0x04540503, + 0x81C, 0x03560503, + 0x81C, 0x02580503, + 0x81C, 0x015A0503, + 0x81C, 0x005C0503, + 0x81C, 0x005E0503, + 0x81C, 0x00600503, + 0x81C, 0x00620503, + 0x81C, 0x00640503, + 0x81C, 0x00660503, + 0x81C, 0x00680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007C0503, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000503, + 0x81C, 0xF7020503, + 0x81C, 0xF6040503, + 0x81C, 0xF5060503, + 0x81C, 0xF4080503, + 0x81C, 0xF30A0503, + 0x81C, 0xF20C0503, + 0x81C, 0xF10E0503, + 0x81C, 0xF0100503, + 0x81C, 0xEF120503, + 0x81C, 0xEE140503, + 0x81C, 0xED160503, + 0x81C, 0xEC180503, + 0x81C, 0xEB1A0503, + 0x81C, 0xEA1C0503, + 0x81C, 0xE91E0503, + 0x81C, 0xE8200503, + 0x81C, 0xE7220503, + 0x81C, 0xE6240503, + 0x81C, 0xE5260503, + 0x81C, 0xE4280503, + 0x81C, 0xE32A0503, + 0x81C, 0xC32C0503, + 0x81C, 0xC22E0503, + 0x81C, 0xC1300503, + 0x81C, 0xC0320503, + 0x81C, 0xA3340503, + 0x81C, 0xA2360503, + 0x81C, 0xA1380503, + 0x81C, 0xA03A0503, + 0x81C, 0x823C0503, + 0x81C, 0x813E0503, + 0x81C, 0x80400503, + 0x81C, 0x63420503, + 0x81C, 0x62440503, + 0x81C, 0x61460503, + 0x81C, 0x60480503, + 0x81C, 0x424A0503, + 0x81C, 0x414C0503, + 0x81C, 0x404E0503, + 0x81C, 0x22500503, + 0x81C, 0x21520503, + 0x81C, 0x20540503, + 0x81C, 0x03560503, + 0x81C, 0x02580503, + 0x81C, 0x015A0503, + 0x81C, 0x005C0503, + 0x81C, 0x005E0503, + 0x81C, 0x00600503, + 0x81C, 0x00620503, + 0x81C, 0x00640503, + 0x81C, 0x00660503, + 0x81C, 0x00680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000503, + 0x81C, 0xFD020503, + 0x81C, 0xFC040503, + 0x81C, 0xFB060503, + 0x81C, 0xFA080503, + 0x81C, 0xF90A0503, + 0x81C, 0xF80C0503, + 0x81C, 0xF70E0503, + 0x81C, 0xF6100503, + 0x81C, 0xF5120503, + 0x81C, 0xF4140503, + 0x81C, 0xF3160503, + 0x81C, 0xF2180503, + 0x81C, 0xF11A0503, + 0x81C, 0xF01C0503, + 0x81C, 0xEF1E0503, + 0x81C, 0xEE200503, + 0x81C, 0xED220503, + 0x81C, 0xEC240503, + 0x81C, 0xEB260503, + 0x81C, 0xEA280503, + 0x81C, 0xE92A0503, + 0x81C, 0xE82C0503, + 0x81C, 0xE72E0503, + 0x81C, 0xE6300503, + 0x81C, 0xE5320503, + 0x81C, 0xE4340503, + 0x81C, 0xE3360503, + 0x81C, 0xC6380503, + 0x81C, 0xC53A0503, + 0x81C, 0xC43C0503, + 0x81C, 0xC33E0503, + 0x81C, 0xA5400503, + 0x81C, 0xA4420503, + 0x81C, 0xA3440503, + 0x81C, 0xA2460503, + 0x81C, 0xA1480503, + 0x81C, 0xA04A0503, + 0x81C, 0x824C0503, + 0x81C, 0x814E0503, + 0x81C, 0x80500503, + 0x81C, 0x64520503, + 0x81C, 0x63540503, + 0x81C, 0x62560503, + 0x81C, 0x61580503, + 0x81C, 0x605A0503, + 0x81C, 0x235C0503, + 0x81C, 0x225E0503, + 0x81C, 0x21600503, + 0x81C, 0x20620503, + 0x81C, 0x03640503, + 0x81C, 0x02660503, + 0x81C, 0x01680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000503, + 0x81C, 0xF7020503, + 0x81C, 0xF6040503, + 0x81C, 0xF5060503, + 0x81C, 0xF4080503, + 0x81C, 0xF30A0503, + 0x81C, 0xF20C0503, + 0x81C, 0xF10E0503, + 0x81C, 0xF0100503, + 0x81C, 0xEF120503, + 0x81C, 0xEE140503, + 0x81C, 0xED160503, + 0x81C, 0xEC180503, + 0x81C, 0xEB1A0503, + 0x81C, 0xEA1C0503, + 0x81C, 0xE91E0503, + 0x81C, 0xE8200503, + 0x81C, 0xE7220503, + 0x81C, 0xE6240503, + 0x81C, 0xE5260503, + 0x81C, 0xE4280503, + 0x81C, 0xE32A0503, + 0x81C, 0xC32C0503, + 0x81C, 0xC22E0503, + 0x81C, 0xC1300503, + 0x81C, 0xC0320503, + 0x81C, 0xA3340503, + 0x81C, 0xA2360503, + 0x81C, 0xA1380503, + 0x81C, 0xA03A0503, + 0x81C, 0x823C0503, + 0x81C, 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0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xC23C0603, + 0x81C, 0xC13E0603, + 0x81C, 0xC0400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0xA0480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x60560603, + 0x81C, 0x24580603, + 0x81C, 0x235A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x03620603, + 0x81C, 0x02640603, + 0x81C, 0x01660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000603, + 0x81C, 0xF7020603, + 0x81C, 0xF6040603, + 0x81C, 0xF5060603, + 0x81C, 0xF4080603, + 0x81C, 0xF30A0603, + 0x81C, 0xF20C0603, + 0x81C, 0xF10E0603, + 0x81C, 0xF0100603, + 0x81C, 0xEF120603, + 0x81C, 0xEE140603, + 0x81C, 0xED160603, + 0x81C, 0xEC180603, + 0x81C, 0xEB1A0603, + 0x81C, 0xEA1C0603, + 0x81C, 0xE91E0603, + 0x81C, 0xE8200603, + 0x81C, 0xE7220603, + 0x81C, 0xE6240603, + 0x81C, 0xE5260603, + 0x81C, 0xE4280603, + 0x81C, 0xE32A0603, + 0x81C, 0xC42C0603, + 0x81C, 0xC32E0603, + 0x81C, 0xC2300603, + 0x81C, 0xC1320603, + 0x81C, 0xA3340603, + 0x81C, 0xA2360603, + 0x81C, 0xA1380603, + 0x81C, 0xA03A0603, + 0x81C, 0x823C0603, + 0x81C, 0x813E0603, + 0x81C, 0x80400603, + 0x81C, 0x65420603, + 0x81C, 0x64440603, + 0x81C, 0x63460603, + 0x81C, 0x62480603, + 0x81C, 0x614A0603, + 0x81C, 0x424C0603, + 0x81C, 0x414E0603, + 0x81C, 0x40500603, + 0x81C, 0x22520603, + 0x81C, 0x21540603, + 0x81C, 0x20560603, + 0x81C, 0x04580603, + 0x81C, 0x035A0603, + 0x81C, 0x025C0603, + 0x81C, 0x015E0603, + 0x81C, 0x00600603, + 0x81C, 0x00620603, + 0x81C, 0x00640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x42560603, + 0x81C, 0x41580603, + 0x81C, 0x405A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x04620603, + 0x81C, 0x03640603, + 0x81C, 0x02660603, + 0x81C, 0x01680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000603, + 0x81C, 0xF8020603, + 0x81C, 0xF7040603, + 0x81C, 0xF6060603, + 0x81C, 0xF5080603, + 0x81C, 0xF40A0603, + 0x81C, 0xF30C0603, + 0x81C, 0xF20E0603, + 0x81C, 0xF1100603, + 0x81C, 0xF0120603, + 0x81C, 0xEF140603, + 0x81C, 0xEE160603, + 0x81C, 0xED180603, + 0x81C, 0xEC1A0603, + 0x81C, 0xEB1C0603, + 0x81C, 0xEA1E0603, + 0x81C, 0xE9200603, + 0x81C, 0xE8220603, + 0x81C, 0xE7240603, + 0x81C, 0xE6260603, + 0x81C, 0xE5280603, + 0x81C, 0xE42A0603, + 0x81C, 0xC42C0603, + 0x81C, 0xC32E0603, + 0x81C, 0xC2300603, + 0x81C, 0xC1320603, + 0x81C, 0xA3340603, + 0x81C, 0xA2360603, + 0x81C, 0xA1380603, + 0x81C, 0xA03A0603, + 0x81C, 0x823C0603, + 0x81C, 0x813E0603, + 0x81C, 0x80400603, + 0x81C, 0x64420603, + 0x81C, 0x63440603, + 0x81C, 0x62460603, + 0x81C, 0x61480603, + 0x81C, 0x604A0603, + 0x81C, 0x244C0603, + 0x81C, 0x234E0603, + 0x81C, 0x22500603, + 0x81C, 0x21520603, + 0x81C, 0x20540603, + 0x81C, 0x05560603, + 0x81C, 0x04580603, + 0x81C, 0x035A0603, + 0x81C, 0x025C0603, + 0x81C, 0x015E0603, + 0x81C, 0x00600603, + 0x81C, 0x00620603, + 0x81C, 0x00640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEF1A0603, + 0x81C, 0xEE1C0603, + 0x81C, 0xED1E0603, + 0x81C, 0xEC200603, + 0x81C, 0xEB220603, + 0x81C, 0xEA240603, + 0x81C, 0xE9260603, + 0x81C, 0xE8280603, + 0x81C, 0xE72A0603, + 0x81C, 0xE62C0603, + 0x81C, 0xE52E0603, + 0x81C, 0xE4300603, + 0x81C, 0xE3320603, + 0x81C, 0xE2340603, + 0x81C, 0xC6360603, + 0x81C, 0xC5380603, + 0x81C, 0xC43A0603, + 0x81C, 0xC33C0603, + 0x81C, 0xA63E0603, + 0x81C, 0xA5400603, + 0x81C, 0xA4420603, + 0x81C, 0xA3440603, + 0x81C, 0xA2460603, + 0x81C, 0xA1480603, + 0x81C, 0x834A0603, + 0x81C, 0x824C0603, + 0x81C, 0x814E0603, + 0x81C, 0x64500603, + 0x81C, 0x63520603, + 0x81C, 0x62540603, + 0x81C, 0x61560603, + 0x81C, 0x60580603, + 0x81C, 0x405A0603, + 0x81C, 0x215C0603, + 0x81C, 0x205E0603, + 0x81C, 0x03600603, + 0x81C, 0x02620603, + 0x81C, 0x01640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x42560603, + 0x81C, 0x41580603, + 0x81C, 0x405A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x04620603, + 0x81C, 0x03640603, + 0x81C, 0x02660603, + 0x81C, 0x01680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x42560603, + 0x81C, 0x41580603, + 0x81C, 0x405A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x04620603, + 0x81C, 0x03640603, + 0x81C, 0x02660603, + 0x81C, 0x01680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBF000603, + 0x81C, 0xBF020603, + 0x81C, 0xBF040603, + 0x81C, 0xBF060603, + 0x81C, 0xBF080603, + 0x81C, 0xBE0A0603, + 0x81C, 0xBD0C0603, + 0x81C, 0xBC0E0603, + 0x81C, 0xBB100603, + 0x81C, 0xBA120603, + 0x81C, 0xB9140603, + 0x81C, 0xB8160603, + 0x81C, 0xB7180603, + 0x81C, 0xB61A0603, + 0x81C, 0xB51C0603, + 0x81C, 0xB41E0603, + 0x81C, 0xB1200603, + 0x81C, 0xB2220603, + 0x81C, 0xB1240603, + 0x81C, 0xB0260603, + 0x81C, 0xAF280603, + 0x81C, 0xAE2A0603, + 0x81C, 0xAD2C0603, + 0x81C, 0xAC2E0603, + 0x81C, 0xAB300603, + 0x81C, 0xAA320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0x883C0603, + 0x81C, 0x873E0603, + 0x81C, 0x86400603, + 0x81C, 0x85420603, + 0x81C, 0x84440603, + 0x81C, 0x83460603, + 0x81C, 0x67480603, + 0x81C, 0x664A0603, + 0x81C, 0x654C0603, + 0x81C, 0x644E0603, + 0x81C, 0x27500603, + 0x81C, 0x26520603, + 0x81C, 0x25540603, + 0x81C, 0x24560603, + 0x81C, 0x23580603, + 0x81C, 0x225A0603, + 0x81C, 0x215C0603, + 0x81C, 0x205E0603, + 0x81C, 0x03600603, + 0x81C, 0x02620603, + 0x81C, 0x01640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000403, + 0x81C, 0xFB000603, + 0x81C, 0xFA020603, + 0x81C, 0xF9040603, + 0x81C, 0xF8060603, + 0x81C, 0xF7080603, + 0x81C, 0xF60A0603, + 0x81C, 0xF50C0603, + 0x81C, 0xF40E0603, + 0x81C, 0xF3100603, + 0x81C, 0xF2120603, + 0x81C, 0xF1140603, + 0x81C, 0xF0160603, + 0x81C, 0xEF180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x644E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x60560603, + 0x81C, 0x40580603, + 0x81C, 0x215A0603, + 0x81C, 0x205C0603, + 0x81C, 0x035E0603, + 0x81C, 0x02600603, + 0x81C, 0x01620603, + 0x81C, 0x00640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000603, + 0x81C, 0xFC020603, + 0x81C, 0xFB040603, + 0x81C, 0xFA060603, + 0x81C, 0xF9080603, + 0x81C, 0xF80A0603, + 0x81C, 0xF70C0603, + 0x81C, 0xF60E0603, + 0x81C, 0xF5100603, + 0x81C, 0xF4120603, + 0x81C, 0xF3140603, + 0x81C, 0xF2160603, + 0x81C, 0xF1180603, + 0x81C, 0xF01A0603, + 0x81C, 0xEF1C0603, + 0x81C, 0xEE1E0603, + 0x81C, 0xED200603, + 0x81C, 0xEC220603, + 0x81C, 0xEB240603, + 0x81C, 0xEA260603, + 0x81C, 0xE9280603, + 0x81C, 0xE82A0603, + 0x81C, 0xE72C0603, + 0x81C, 0xE62E0603, + 0x81C, 0xE5300603, + 0x81C, 0xE4320603, + 0x81C, 0xE3340603, + 0x81C, 0xC6360603, + 0x81C, 0xC5380603, + 0x81C, 0xC43A0603, + 0x81C, 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0xEC1C0703, + 0x81C, 0xEB1E0703, + 0x81C, 0xEA200703, + 0x81C, 0xE9220703, + 0x81C, 0xE8240703, + 0x81C, 0xE7260703, + 0x81C, 0xE6280703, + 0x81C, 0xE52A0703, + 0x81C, 0xE42C0703, + 0x81C, 0xE32E0703, + 0x81C, 0xE2300703, + 0x81C, 0xE1320703, + 0x81C, 0xC6340703, + 0x81C, 0xC5360703, + 0x81C, 0xC4380703, + 0x81C, 0xC33A0703, + 0x81C, 0xA63C0703, + 0x81C, 0xA53E0703, + 0x81C, 0xA4400703, + 0x81C, 0xA3420703, + 0x81C, 0xA2440703, + 0x81C, 0xA1460703, + 0x81C, 0x83480703, + 0x81C, 0x824A0703, + 0x81C, 0x814C0703, + 0x81C, 0x804E0703, + 0x81C, 0x63500703, + 0x81C, 0x62520703, + 0x81C, 0x61540703, + 0x81C, 0x42560703, + 0x81C, 0x41580703, + 0x81C, 0x405A0703, + 0x81C, 0x225C0703, + 0x81C, 0x215E0703, + 0x81C, 0x20600703, + 0x81C, 0x04620703, + 0x81C, 0x03640703, + 0x81C, 0x02660703, + 0x81C, 0x01680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBF000703, + 0x81C, 0xBF020703, + 0x81C, 0xBF040703, + 0x81C, 0xBF060703, + 0x81C, 0xBF080703, + 0x81C, 0xBE0A0703, + 0x81C, 0xBD0C0703, + 0x81C, 0xBC0E0703, + 0x81C, 0xBB100703, + 0x81C, 0xBA120703, + 0x81C, 0xB9140703, + 0x81C, 0xB8160703, + 0x81C, 0xB7180703, + 0x81C, 0xB61A0703, + 0x81C, 0xB51C0703, + 0x81C, 0xB41E0703, + 0x81C, 0xB1200703, + 0x81C, 0xB2220703, + 0x81C, 0xB1240703, + 0x81C, 0xB0260703, + 0x81C, 0xAF280703, + 0x81C, 0xAE2A0703, + 0x81C, 0xAD2C0703, + 0x81C, 0xAC2E0703, + 0x81C, 0xAB300703, + 0x81C, 0xAA320703, + 0x81C, 0xC6340703, + 0x81C, 0xC5360703, + 0x81C, 0xC4380703, + 0x81C, 0xC33A0703, + 0x81C, 0x883C0703, + 0x81C, 0x873E0703, + 0x81C, 0x86400703, + 0x81C, 0x85420703, + 0x81C, 0x84440703, + 0x81C, 0x83460703, + 0x81C, 0x67480703, + 0x81C, 0x664A0703, + 0x81C, 0x654C0703, + 0x81C, 0x644E0703, + 0x81C, 0x27500703, + 0x81C, 0x26520703, + 0x81C, 0x25540703, + 0x81C, 0x24560703, + 0x81C, 0x23580703, + 0x81C, 0x225A0703, + 0x81C, 0x215C0703, + 0x81C, 0x205E0703, + 0x81C, 0x03600703, + 0x81C, 0x02620703, + 0x81C, 0x01640703, + 0x81C, 0x00660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000403, + 0x81C, 0xFB000703, + 0x81C, 0xFA020703, + 0x81C, 0xF9040703, + 0x81C, 0xF8060703, + 0x81C, 0xF7080703, + 0x81C, 0xF60A0703, + 0x81C, 0xF50C0703, + 0x81C, 0xF40E0703, + 0x81C, 0xF3100703, + 0x81C, 0xF2120703, + 0x81C, 0xF1140703, + 0x81C, 0xF0160703, + 0x81C, 0xEF180703, + 0x81C, 0xEE1A0703, + 0x81C, 0xED1C0703, + 0x81C, 0xEC1E0703, + 0x81C, 0xEB200703, + 0x81C, 0xEA220703, + 0x81C, 0xE9240703, + 0x81C, 0xE8260703, + 0x81C, 0xE7280703, + 0x81C, 0xE62A0703, + 0x81C, 0xE52C0703, + 0x81C, 0xE42E0703, + 0x81C, 0xE3300703, + 0x81C, 0xE2320703, + 0x81C, 0xC6340703, + 0x81C, 0xC5360703, + 0x81C, 0xC4380703, + 0x81C, 0xC33A0703, + 0x81C, 0xA63C0703, + 0x81C, 0xA53E0703, + 0x81C, 0xA4400703, + 0x81C, 0xA3420703, + 0x81C, 0xA2440703, + 0x81C, 0x84460703, + 0x81C, 0x83480703, + 0x81C, 0x824A0703, + 0x81C, 0x814C0703, + 0x81C, 0x804E0703, + 0x81C, 0x63500703, + 0x81C, 0x62520703, + 0x81C, 0x61540703, + 0x81C, 0x60560703, + 0x81C, 0x22580703, + 0x81C, 0x055A0703, + 0x81C, 0x045C0703, + 0x81C, 0x035E0703, + 0x81C, 0x02600703, + 0x81C, 0x01620703, + 0x81C, 0x00640703, + 0x81C, 0x00660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000703, + 0x81C, 0xFB020703, + 0x81C, 0xFA040703, + 0x81C, 0xF9060703, + 0x81C, 0xF8080703, + 0x81C, 0xF70A0703, + 0x81C, 0xF60C0703, + 0x81C, 0xF50E0703, + 0x81C, 0xF4100703, + 0x81C, 0xF3120703, + 0x81C, 0xF2140703, + 0x81C, 0xF1160703, + 0x81C, 0xF0180703, + 0x81C, 0xEF1A0703, + 0x81C, 0xEE1C0703, + 0x81C, 0xED1E0703, + 0x81C, 0xEC200703, + 0x81C, 0xEB220703, + 0x81C, 0xEA240703, + 0x81C, 0xE9260703, + 0x81C, 0xE8280703, + 0x81C, 0xE72A0703, + 0x81C, 0xE62C0703, + 0x81C, 0xE52E0703, + 0x81C, 0xE4300703, + 0x81C, 0xE3320703, + 0x81C, 0xE2340703, + 0x81C, 0xC6360703, + 0x81C, 0xC5380703, + 0x81C, 0xC43A0703, + 0x81C, 0xC33C0703, + 0x81C, 0xA63E0703, + 0x81C, 0xA5400703, + 0x81C, 0xA4420703, + 0x81C, 0xA3440703, + 0x81C, 0xA2460703, + 0x81C, 0x84480703, + 0x81C, 0x834A0703, + 0x81C, 0x824C0703, + 0x81C, 0x814E0703, + 0x81C, 0x80500703, + 0x81C, 0x63520703, + 0x81C, 0x62540703, + 0x81C, 0x61560703, + 0x81C, 0x60580703, + 0x81C, 0x235A0703, + 0x81C, 0x225C0703, + 0x81C, 0x215E0703, + 0x81C, 0x20600703, + 0x81C, 0x03620703, + 0x81C, 0x02640703, + 0x81C, 0x01660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0xA0000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0xB0000000, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8822B_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8822B_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8822B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8822B_AGC_TAB(void) +{ + return 101; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG[] = { + 0x800, 0x9020D010, + 0x804, 0x800181A0, + 0x808, 0x0E028233, + 0x80C, 0x10000013, + 0x810, 0x22101243, + 0x814, 0x020C3D11, + 0x818, 0x84A10385, + 0x81C, 0x1E1E081F, + 0x820, 0x0001AAAA, + 0x824, 0x00030FE0, + 0x828, 0x0000CCCC, + 0x82C, 0x75CB7010, + 0x830, 0x79A0EAAA, + 0x834, 0x072E6986, + 0x838, 0x87766441, + 0x83C, 0x9194B2B7, + 0x840, 0x171750E0, + 0x844, 0x4D3D7CDB, + 0x848, 0x4AD0408B, + 0x84C, 0x6AFBF7A5, + 0x850, 0x28A74706, + 0x854, 0x0001520C, + 0x858, 0x4060C000, + 0x85C, 0x74010160, + 0x860, 0x68A7C321, + 0x864, 0x79F27432, + 0x868, 0x8CA7A314, + 0x86C, 0x778C2878, + 0x870, 0x77777777, + 0x874, 0x27612C2E, + 0x878, 0xC0003152, + 0x87C, 0x5C8FC000, + 0x880, 0x00000000, + 0x884, 0x00000000, + 0x888, 0x00000000, + 0x88C, 0x00000000, + 0x890, 0x00000000, + 0x894, 0x00000000, + 0x898, 0x00000000, + 0x89C, 0x00000000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0x2202033E, + 0x8AC, 0xF00F000A, + 0x8B0, 0x00000600, + 0x8B4, 0x000FC080, + 0x8B8, 0xEC0057F7, + 0x8BC, 0xACB520A3, + 0x8C0, 0xFFE04020, + 0x8C4, 0x47C00000, + 0x8C8, 0x000251A5, + 0x8CC, 0x08108492, + 0x8D0, 0x0000B800, + 0x8D4, 0x860308A0, + 0x8D8, 0x29095612, + 0x8DC, 0x00000000, + 0x8E0, 0x32D16777, + 0x8E4, 0x4C098935, + 0x8E8, 0xFFFFC42C, + 0x8EC, 0x99999999, + 0x8F0, 0x00009999, + 0x8F4, 0x00D80FA1, + 0x8F8, 0x40000080, + 0x8FC, 0x00000130, + 0x900, 0x00800000, + 0x904, 0x00000000, + 0x908, 0x00000000, + 0x90C, 0xD3000000, + 0x910, 0x0000FC00, + 0x914, 0xC6380000, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x855A2500, + 0x928, 0x4AB0E4E4, + 0x92C, 0xFFFEB200, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x938, 0x00008480, + 0x93C, 0xE41C0642, + 0x940, 0x0E470430, + 0x944, 0x00000000, + 0x948, 0xAC000000, + 0x94C, 0x10000083, + 0x950, 0x32010080, + 0x954, 0x84510080, + 0x958, 0x00000001, + 0x95C, 0x04248000, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x00001FFF, + 0x974, 0x44000FFF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x98C, 0x43440000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x80000088, + 0x9A8, 0x0C2F0000, + 0x9AC, 0x01560000, + 0x9B0, 0x70000000, + 0x9B4, 0x00000000, + 0x9B8, 0x00000000, + 0x9BC, 0x00000000, + 0x9C0, 0x00000000, + 0x9C4, 0x00000000, + 0x9C8, 0x00000000, + 0x9CC, 0x00000000, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E0, 0x00000000, + 0x9E4, 0x02000402, + 0x9E8, 0x000022D4, + 0x9EC, 0x00000000, + 0x9F0, 0x00010080, + 0x9F4, 0x00000000, + 0x9F8, 0x00000000, + 0x9FC, 0xEFFFF7F7, + 0xA00, 0x00D047C8, + 0xA04, 0x81FF800C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E20100F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x84880000, + 0xA24, 0x384F6577, + 0xA28, 0x00001525, + 0xA2C, 0x00920000, + 0xA70, 0x101FFF00, + 0xA74, 0x00000148, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x218675B2, + 0xA84, 0x80208C00, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x030A0000, + 0xA9C, 0x00060000, + 0xAA0, 0x00000000, + 0xAA4, 0x0004000F, + 0xAA8, 0x00000200, + 0xB00, 0xE1000440, + 0xB04, 0x00800000, + 0xB08, 0xFF02030B, + 0xB0C, 0x01EAA406, + 0xB10, 0x00030690, + 0xB14, 0x006000FA, + 0xB18, 0x00000002, + 0xB1C, 0x00000002, + 0xB20, 0x4B00001F, + 0xB24, 0x4E8E3E40, + 0xB28, 0x03020100, + 0xB2C, 0x07060504, + 0xB30, 0x0B0A0908, + 0xB34, 0x0F0E0D0C, + 0xB38, 0x13121110, + 0xB3C, 0x0000003A, + 0xB40, 0x00000000, + 0xB44, 0x80000000, + 0xB48, 0x3F0000FA, + 0xB4C, 0x88C80020, + 0xB50, 0x00000000, + 0xB54, 0x00004241, + 0xB58, 0xE0008208, + 0xB5C, 0x41EFFFF9, + 0xB60, 0x00000000, + 0xB64, 0x00200063, + 0xB68, 0x0000003A, + 0xB6C, 0x00000102, + 0xB70, 0x4E6D1870, + 0xB74, 0x03020100, + 0xB78, 0x07060504, + 0xB7C, 0x0B0A0908, + 0xB80, 0x0F0E0D0C, + 0xB84, 0x13121110, + 0xB88, 0x00000000, + 0xB8C, 0x00000000, + 0xC00, 0x00000007, + 0xC04, 0x00000020, + 0xC08, 0x60403231, + 0xC0C, 0x00012345, + 0xC10, 0x00000100, + 0xC14, 0x01000000, + 0xC18, 0x00000000, + 0xC1C, 0x40040053, + 0xC20, 0x40020103, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x00000000, + 0xC34, 0x00000000, + 0xC38, 0x00000000, + 0xC3C, 0x00000000, + 0xC40, 0x00000000, + 0xC44, 0x00000000, + 0xC48, 0x00000000, + 0xC4C, 0x00000000, + 0xC50, 0x00000020, + 0xC54, 0x00000000, + 0xC58, 0xD8020402, + 0xC5C, 0xDE000120, + 0xC68, 0x5979993F, + 0xC6C, 0x0000122A, + 0xC70, 0x99795979, + 0xC74, 0x99795979, + 0xC78, 0x99799979, + 0xC7C, 0x99791979, + 0xC80, 0x19791979, + 0xC84, 0x19791979, + 0xC88, 0x00000000, + 0xC8C, 0x07000000, + 0xC94, 0x01000100, + 0xC98, 0x201C8000, + 0xC9C, 0x00000000, + 0xCA0, 0x0000A555, + 0xCA4, 0x08040201, + 0xCA8, 0x80402010, + 0xCAC, 0x00000000, + 0xCB0, 0x77777777, + 0xCB4, 0x00007777, + 0xCB8, 0x00000000, + 0xCBC, 0x00000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x00000000, + 0xCDC, 0x00000000, + 0xCE0, 0x00000000, + 0xCE4, 0x00000000, + 0xCE8, 0x00000000, + 0xCEC, 0x00000000, + 0xE00, 0x00000007, + 0xE04, 0x00000020, + 0xE08, 0x60403231, + 0xE0C, 0x00012345, + 0xE10, 0x00000100, + 0xE14, 0x01000000, + 0xE18, 0x00000000, + 0xE1C, 0x40040053, + 0xE20, 0x40020103, + 0xE24, 0x00000000, + 0xE28, 0x00000000, + 0xE2C, 0x00000000, + 0xE30, 0x00000000, + 0xE34, 0x00000000, + 0xE38, 0x00000000, + 0xE3C, 0x00000000, + 0xE40, 0x00000000, + 0xE44, 0x00000000, + 0xE48, 0x00000000, + 0xE4C, 0x00000000, + 0xE50, 0x00000020, + 0xE54, 0x00000000, + 0xE58, 0xD8020402, + 0xE5C, 0xDE000120, + 0xE68, 0x5979993F, + 0xE6C, 0x0000122A, + 0xE70, 0x99795979, + 0xE74, 0x99795979, + 0xE78, 0x99799979, + 0xE7C, 0x99791979, + 0xE80, 0x19791979, + 0xE84, 0x19791979, + 0xE88, 0x00000000, + 0xE8C, 0x07000000, + 0xE94, 0x01000100, + 0xE98, 0x201C8000, + 0xE9C, 0x00000000, + 0xEA0, 0x0000A555, + 0xEA4, 0x08040201, + 0xEA8, 0x80402010, + 0xEAC, 0x00000000, + 0xEB0, 0x77777777, + 0xEB4, 0x00007777, + 0xEB8, 0x00000000, + 0xEBC, 0x00000000, + 0xEC0, 0x00000000, + 0xEC4, 0x00000000, + 0xEC8, 0x00000000, + 0xECC, 0x00000000, + 0xED0, 0x00000000, + 0xED4, 0x00000000, + 0xED8, 0x00000000, + 0xEDC, 0x00000000, + 0xEE0, 0x00000000, + 0xEE4, 0x00000000, + 0xEE8, 0x00000000, + 0xEEC, 0x00000000, + 0x1900, 0x00000000, + 0x1904, 0x00238000, + 0x1908, 0x00000000, + 0x190C, 0x00000000, + 0x1910, 0x00000000, + 0x1914, 0x00000000, + 0x1918, 0x00000000, + 0x191C, 0x00000000, + 0x1920, 0x00000000, + 0x1924, 0x00000000, + 0x1928, 0x00000000, + 0x192C, 0x00000000, + 0x1930, 0x00000000, + 0x1934, 0x00000000, + 0x1938, 0x00000000, + 0x193C, 0x00000000, + 0x1940, 0x00000000, + 0x1944, 0x00000000, + 0x1948, 0x00000000, + 0x194C, 0x00000000, + 0x1950, 0x00000000, + 0x1954, 0x00000000, + 0x1958, 0x00000000, + 0x195C, 0x00000000, + 0x1960, 0x00000000, + 0x1964, 0x00000000, + 0x1968, 0x00000000, + 0x196C, 0x00000000, + 0x1970, 0x00000000, + 0x1974, 0x00000000, + 0x1978, 0x00000000, + 0x197C, 0x00000000, + 0x1980, 0x00000000, + 0x1984, 0x03000000, + 0x1988, 0x21401E88, + 0x198C, 0x00004000, + 0x1990, 0x00000000, + 0x1994, 0x00000000, + 0x1998, 0x00000053, + 0x199C, 0x00000000, + 0x19A0, 0x00000000, + 0x19A4, 0x00000000, + 0x19A8, 0x00000000, + 0x19AC, 0x0E47E47F, + 0x19B0, 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0x550B1587, + 0x1B80, 0x315D1595, + 0x1B80, 0x315D1597, + 0x1B80, 0x7B2015A5, + 0x1B80, 0x7B2015A7, + 0x1B80, 0x7A0015B5, + 0x1B80, 0x7A0015B7, + 0x1B80, 0x551315C5, + 0x1B80, 0x551315C7, + 0x1B80, 0x740115D5, + 0x1B80, 0x740115D7, + 0x1B80, 0x740015E5, + 0x1B80, 0x740015E7, + 0x1B80, 0x8E0015F5, + 0x1B80, 0x8E0015F7, + 0x1B80, 0x00011605, + 0x1B80, 0x00011607, + 0x1B80, 0x57021615, + 0x1B80, 0x57021617, + 0x1B80, 0x57001625, + 0x1B80, 0x57001627, + 0x1B80, 0x97001635, + 0x1B80, 0x97001637, + 0x1B80, 0x00011645, + 0x1B80, 0x00011647, + 0x1B80, 0x4F781655, + 0x1B80, 0x4F781657, + 0x1B80, 0x53881665, + 0x1B80, 0x53881667, + 0x1B80, 0xE1731675, + 0x1B80, 0xE1731677, + 0x1B80, 0x54801685, + 0x1B80, 0x54801687, + 0x1B80, 0x54001695, + 0x1B80, 0x54001697, + 0x1B80, 0xE17316A5, + 0x1B80, 0xE17316A7, + 0x1B80, 0x548116B5, + 0x1B80, 0x548116B7, + 0x1B80, 0x540016C5, + 0x1B80, 0x540016C7, + 0x1B80, 0xE17316D5, + 0x1B80, 0xE17316D7, + 0x1B80, 0x548216E5, + 0x1B80, 0x548216E7, + 0x1B80, 0x540016F5, + 0x1B80, 0x540016F7, + 0x1B80, 0xE17E1705, + 0x1B80, 0xE17E1707, + 0x1B80, 0xBF1D1715, + 0x1B80, 0xBF1D1717, + 0x1B80, 0x301D1725, + 0x1B80, 0x301D1727, + 0x1B80, 0xE1511735, + 0x1B80, 0xE1511737, + 0x1B80, 0xE1561745, + 0x1B80, 0xE1561747, + 0x1B80, 0xE15A1755, + 0x1B80, 0xE15A1757, + 0x1B80, 0xE1611765, + 0x1B80, 0xE1611767, + 0x1B80, 0xE1C71775, + 0x1B80, 0xE1C71777, + 0x1B80, 0x55131785, + 0x1B80, 0x55131787, + 0x1B80, 0xE15D1795, + 0x1B80, 0xE15D1797, + 0x1B80, 0x551517A5, + 0x1B80, 0x551517A7, + 0x1B80, 0xE16117B5, + 0x1B80, 0xE16117B7, + 0x1B80, 0xE1C717C5, + 0x1B80, 0xE1C717C7, + 0x1B80, 0x000117D5, + 0x1B80, 0x000117D7, + 0x1B80, 0x54BF17E5, + 0x1B80, 0x54BF17E7, + 0x1B80, 0x54C017F5, + 0x1B80, 0x54C017F7, + 0x1B80, 0x54A31805, + 0x1B80, 0x54A31807, + 0x1B80, 0x54C11815, + 0x1B80, 0x54C11817, + 0x1B80, 0x54A41825, + 0x1B80, 0x54A41827, + 0x1B80, 0x4C181835, + 0x1B80, 0x4C181837, + 0x1B80, 0xBF071845, + 0x1B80, 0xBF071847, + 0x1B80, 0x54C21855, + 0x1B80, 0x54C21857, + 0x1B80, 0x54A41865, + 0x1B80, 0x54A41867, + 0x1B80, 0xBF041875, + 0x1B80, 0xBF041877, + 0x1B80, 0x54C11885, + 0x1B80, 0x54C11887, + 0x1B80, 0x54A31895, + 0x1B80, 0x54A31897, + 0x1B80, 0xBF0118A5, + 0x1B80, 0xBF0118A7, + 0x1B80, 0xE1D518B5, + 0x1B80, 0xE1D518B7, + 0x1B80, 0x54DF18C5, + 0x1B80, 0x54DF18C7, + 0x1B80, 0x000118D5, + 0x1B80, 0x000118D7, + 0x1B80, 0x54BF18E5, + 0x1B80, 0x54BF18E7, + 0x1B80, 0x54E518F5, + 0x1B80, 0x54E518F7, + 0x1B80, 0x050A1905, + 0x1B80, 0x050A1907, + 0x1B80, 0x54DF1915, + 0x1B80, 0x54DF1917, + 0x1B80, 0x00011925, + 0x1B80, 0x00011927, + 0x1B80, 0x7F201935, + 0x1B80, 0x7F201937, + 0x1B80, 0x7E001945, + 0x1B80, 0x7E001947, + 0x1B80, 0x7D001955, + 0x1B80, 0x7D001957, + 0x1B80, 0x55011965, + 0x1B80, 0x55011967, + 0x1B80, 0x5C311975, + 0x1B80, 0x5C311977, + 0x1B80, 0xE15D1985, + 0x1B80, 0xE15D1987, + 0x1B80, 0xE1611995, + 0x1B80, 0xE1611997, + 0x1B80, 0x548019A5, + 0x1B80, 0x548019A7, + 0x1B80, 0x540019B5, + 0x1B80, 0x540019B7, + 0x1B80, 0xE15D19C5, + 0x1B80, 0xE15D19C7, + 0x1B80, 0xE16119D5, + 0x1B80, 0xE16119D7, + 0x1B80, 0x548119E5, + 0x1B80, 0x548119E7, + 0x1B80, 0x540019F5, + 0x1B80, 0x540019F7, + 0x1B80, 0xE15D1A05, + 0x1B80, 0xE15D1A07, + 0x1B80, 0xE1611A15, + 0x1B80, 0xE1611A17, + 0x1B80, 0x54821A25, + 0x1B80, 0x54821A27, + 0x1B80, 0x54001A35, + 0x1B80, 0x54001A37, + 0x1B80, 0xE17E1A45, + 0x1B80, 0xE17E1A47, + 0x1B80, 0xBFE91A55, + 0x1B80, 0xBFE91A57, + 0x1B80, 0x301D1A65, + 0x1B80, 0x301D1A67, + 0x1B80, 0x00231A75, + 0x1B80, 0x00231A77, + 0x1B80, 0x7B201A85, + 0x1B80, 0x7B201A87, + 0x1B80, 0x7A001A95, + 0x1B80, 0x7A001A97, + 0x1B80, 0x79001AA5, + 0x1B80, 0x79001AA7, + 0x1B80, 0xE1CB1AB5, + 0x1B80, 0xE1CB1AB7, + 0x1B80, 0x00021AC5, + 0x1B80, 0x00021AC7, + 0x1B80, 0x00011AD5, + 0x1B80, 0x00011AD7, + 0x1B80, 0x00221AE5, + 0x1B80, 0x00221AE7, + 0x1B80, 0x7B201AF5, + 0x1B80, 0x7B201AF7, + 0x1B80, 0x7A001B05, + 0x1B80, 0x7A001B07, + 0x1B80, 0x79001B15, + 0x1B80, 0x79001B17, + 0x1B80, 0xE1CB1B25, + 0x1B80, 0xE1CB1B27, + 0x1B80, 0x00021B35, + 0x1B80, 0x00021B37, + 0x1B80, 0x00011B45, + 0x1B80, 0x00011B47, + 0x1B80, 0x74021B55, + 0x1B80, 0x74021B57, + 0x1B80, 0x003F1B65, + 0x1B80, 0x003F1B67, + 0x1B80, 0x74001B75, + 0x1B80, 0x74001B77, + 0x1B80, 0x00021B85, + 0x1B80, 0x00021B87, + 0x1B80, 0x00011B95, + 0x1B80, 0x00011B97, + 0x1B80, 0x4D041BA5, + 0x1B80, 0x4D041BA7, + 0x1B80, 0x2EF81BB5, + 0x1B80, 0x2EF81BB7, + 0x1B80, 0x00001BC5, + 0x1B80, 0x00001BC7, + 0x1B80, 0x23301BD5, + 0x1B80, 0x23301BD7, + 0x1B80, 0x00241BE5, + 0x1B80, 0x00241BE7, + 0x1B80, 0x23E01BF5, + 0x1B80, 0x23E01BF7, + 0x1B80, 0x003F1C05, + 0x1B80, 0x003F1C07, + 0x1B80, 0x23FC1C15, + 0x1B80, 0x23FC1C17, + 0x1B80, 0xBFCE1C25, + 0x1B80, 0xBFCE1C27, + 0x1B80, 0x2EF01C35, + 0x1B80, 0x2EF01C37, + 0x1B80, 0x00001C45, + 0x1B80, 0x00001C47, + 0x1B80, 0x4D001C55, + 0x1B80, 0x4D001C57, + 0x1B80, 0x00011C65, + 0x1B80, 0x00011C67, + 0x1B80, 0x549F1C75, + 0x1B80, 0x549F1C77, + 0x1B80, 0x54FF1C85, + 0x1B80, 0x54FF1C87, + 0x1B80, 0x54001C95, + 0x1B80, 0x54001C97, + 0x1B80, 0x00011CA5, + 0x1B80, 0x00011CA7, + 0x1B80, 0x5C311CB5, + 0x1B80, 0x5C311CB7, + 0x1B80, 0x07141CC5, + 0x1B80, 0x07141CC7, + 0x1B80, 0x54001CD5, + 0x1B80, 0x54001CD7, + 0x1B80, 0x5C321CE5, + 0x1B80, 0x5C321CE7, + 0x1B80, 0x00011CF5, + 0x1B80, 0x00011CF7, + 0x1B80, 0x5C321D05, + 0x1B80, 0x5C321D07, + 0x1B80, 0x07141D15, + 0x1B80, 0x07141D17, + 0x1B80, 0x54001D25, + 0x1B80, 0x54001D27, + 0x1B80, 0x5C311D35, + 0x1B80, 0x5C311D37, + 0x1B80, 0x00011D45, + 0x1B80, 0x00011D47, + 0x1B80, 0x4C981D55, + 0x1B80, 0x4C981D57, + 0x1B80, 0x4C181D65, + 0x1B80, 0x4C181D67, + 0x1B80, 0x00011D75, + 0x1B80, 0x00011D77, + 0x1B80, 0x5C321D85, + 0x1B80, 0x5C321D87, + 0x1B80, 0x62841D95, + 0x1B80, 0x62841D97, + 0x1B80, 0x66861DA5, + 0x1B80, 0x66861DA7, + 0x1B80, 0x6C031DB5, + 0x1B80, 0x6C031DB7, + 0x1B80, 0x7B201DC5, + 0x1B80, 0x7B201DC7, + 0x1B80, 0x7A001DD5, + 0x1B80, 0x7A001DD7, + 0x1B80, 0x79001DE5, + 0x1B80, 0x79001DE7, + 0x1B80, 0x7F201DF5, + 0x1B80, 0x7F201DF7, + 0x1B80, 0x7E001E05, + 0x1B80, 0x7E001E07, + 0x1B80, 0x7D001E15, + 0x1B80, 0x7D001E17, + 0x1B80, 0x09011E25, + 0x1B80, 0x09011E27, + 0x1B80, 0x0C011E35, + 0x1B80, 0x0C011E37, + 0x1B80, 0x0BA61E45, + 0x1B80, 0x0BA61E47, + 0x1B80, 0x00011E55, + 0x1B80, 0x00011E57, + 0x1B80, 0x00000006, + 0x1B80, 0x00000002, + +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8822B(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8822B_PHY_REG(void) +{ + return 101; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type12.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type12[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x22242628, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x34361820, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x26283032, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x18202224, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x22242628, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x34361820, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x26283032, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x18202224 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type12)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type12; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type15.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type15[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type15)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type15; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type16.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type16[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type16)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type16; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type17.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type17[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type17)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type17; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type2.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type2[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type2)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type2; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type3.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type3[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type3)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type3; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type4.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type4[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x42444648, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x32343638, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x40424446, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x44462830, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x36384042, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x38404244, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x42444648, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424446, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x32343638, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x40424446, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424446, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x44462830, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x36384042, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type4)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type4; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* PHY_REG_PG_type5.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_PHY_REG_PG_type5[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG_type5)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_PHY_REG_PG_type5; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.h b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.h index cfee6268789..c841ed8a817 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_bb.h @@ -1,134 +1,134 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __INC_MP_BB_HW_IMG_8822B_H -#define __INC_MP_BB_HW_IMG_8822B_H - - -/****************************************************************************** -* AGC_TAB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_AGC_TAB(void); - -/****************************************************************************** -* PHY_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG(void); - -/****************************************************************************** -* PHY_REG_PG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG(void); - -/****************************************************************************** -* PHY_REG_PG_type12.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type12(void); - -/****************************************************************************** -* PHY_REG_PG_type15.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type15(void); - -/****************************************************************************** -* PHY_REG_PG_type16.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type16(void); - -/****************************************************************************** -* PHY_REG_PG_type17.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type17(void); - -/****************************************************************************** -* PHY_REG_PG_type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type2(void); - -/****************************************************************************** -* PHY_REG_PG_type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type3(void); - -/****************************************************************************** -* PHY_REG_PG_type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type4(void); - -/****************************************************************************** -* PHY_REG_PG_type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type5(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8822B_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8822B_H +#define __INC_MP_BB_HW_IMG_8822B_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG(void); + +/****************************************************************************** +* PHY_REG_PG_type12.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type12(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type12(void); + +/****************************************************************************** +* PHY_REG_PG_type15.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type15(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type15(void); + +/****************************************************************************** +* PHY_REG_PG_type16.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type16(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type16(void); + +/****************************************************************************** +* PHY_REG_PG_type17.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type17(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type17(void); + +/****************************************************************************** +* PHY_REG_PG_type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type2(void); + +/****************************************************************************** +* PHY_REG_PG_type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type3(void); + +/****************************************************************************** +* PHY_REG_PG_type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type4(void); + +/****************************************************************************** +* PHY_REG_PG_type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_PHY_REG_PG_type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG_type5(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.c b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.c index 6555fbb0903..16b7f2366f9 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.c @@ -1,13434 +1,13434 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8822b/hal8822b_fw.h" -#endif - - -#if (RTL8822B_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_AP[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0x88, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x22, 0x0D, 0x96, 0x91, 0x67, -0xB0, 0x67, 0x00, 0x18, 0xEA, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x32, 0x01, 0x10, -0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x91, 0x23, 0x00, 0x00, -0x90, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -u4Byte ArrayLength_MP_8822B_FW_AP = 65928; - -#endif - -void -ODM_ReadFirmware_MP_8822B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_AP; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_AP, ArrayLength_MP_8822B_FW_AP); -#endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_AP; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_NIC[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 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0x22, 0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, -0xE5, 0x49, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, -0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x81, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - -}; -u4Byte ArrayLength_MP_8822B_FW_NIC = 88160; - - -#endif - -void -ODM_ReadFirmware_MP_8822B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_NIC; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_NIC, ArrayLength_MP_8822B_FW_NIC); -#endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_NIC; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_WOWLAN[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0xE8, 0x0A, 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0x69, -0x51, 0x67, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, -0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED, 0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, -0x00, 0x18, 0x7C, 0x36, 0x0F, 0x22, 0x04, 0x95, 0x91, 0x67, 0x00, 0x18, 0xCC, 0x35, 0x0A, 0x22, -0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, 0xFB, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, -0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, -0xE9, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -u4Byte ArrayLength_MP_8822B_FW_WOWLAN = 59032; - -#endif - -void -ODM_ReadFirmware_MP_8822B_FW_WOWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_WOWLAN; -#else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_WOWLAN, ArrayLength_MP_8822B_FW_WOWLAN); -#endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_WOWLAN; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#include "../../rtl8822b/hal8822b_fw.h" +#endif + + +#if (RTL8822B_SUPPORT == 1) +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8822B_FW_AP[] = { +0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x88, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x22, 0x0D, 0x96, 0x91, 0x67, +0xB0, 0x67, 0x00, 0x18, 0xEA, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x32, 0x01, 0x10, +0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x91, 0x23, 0x00, 0x00, +0x90, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +u4Byte ArrayLength_MP_8822B_FW_AP = 65928; + +#endif + +void +ODM_ReadFirmware_MP_8822B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_AP; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_AP, ArrayLength_MP_8822B_FW_AP); +#endif + *pFirmwareSize = ArrayLength_MP_8822B_FW_AP; +} + + +#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +#ifndef LOAD_FW_HEADER_FROM_DRIVER +u1Byte Array_MP_8822B_FW_NIC[] = { +0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 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0x06, 0x92, 0x24, 0x5A, 0x4F, 0x61, +0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF6, 0xB8, 0x9A, 0x81, 0xF2, 0x00, 0x6C, 0x01, 0x6E, 0x00, 0x18, +0x64, 0x2A, 0x40, 0xF4, 0x14, 0x6C, 0x80, 0x6D, 0x01, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, +0x20, 0x6A, 0x40, 0xF6, 0xB8, 0x9A, 0x01, 0xF0, 0x08, 0x6C, 0x00, 0x6E, 0x00, 0x18, 0x64, 0x2A, +0x01, 0xF0, 0x14, 0x6C, 0x1F, 0xF4, 0x00, 0x6D, 0x22, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, +0x20, 0x6A, 0xC1, 0xF0, 0x0C, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF0, 0x50, 0x9A, 0x2C, 0xE8, +0x4D, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x0C, 0x94, 0x81, 0xF0, 0xF0, 0x9A, 0x00, 0x6D, 0x18, 0x6E, +0x01, 0x49, 0x04, 0xD0, 0x00, 0x18, 0xCB, 0x33, 0x00, 0x6B, 0x01, 0x21, 0x01, 0x6B, 0xFF, 0x69, +0x4C, 0xE9, 0x6C, 0xE9, 0x0C, 0x93, 0x4A, 0xA3, 0x0D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x81, 0xF0, +0xF0, 0x9A, 0x83, 0x67, 0x01, 0x6D, 0x18, 0x6E, 0x04, 0xD0, 0x00, 0x18, 0xCB, 0x33, 0x4C, 0xE9, +0xFF, 0x6A, 0x4C, 0xE9, 0x0C, 0x94, 0x06, 0x95, 0x00, 0x18, 0xDE, 0x32, 0x01, 0x2A, 0x00, 0x69, +0x51, 0x67, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, +0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED, 0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, +0x00, 0x18, 0x7C, 0x36, 0x0F, 0x22, 0x04, 0x95, 0x91, 0x67, 0x00, 0x18, 0xCC, 0x35, 0x0A, 0x22, +0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, 0xFB, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, +0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, +0xE9, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +u4Byte ArrayLength_MP_8822B_FW_WOWLAN = 59032; + +#endif + +void +ODM_ReadFirmware_MP_8822B_FW_WOWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_WOWLAN; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_WOWLAN, ArrayLength_MP_8822B_FW_WOWLAN); +#endif + *pFirmwareSize = ArrayLength_MP_8822B_FW_WOWLAN; +} + + + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.h b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.h index 69898fb3b2e..f565516166f 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_fw.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8822B_H -#define __INC_MP_FW_HW_IMG_8822B_H - - -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8822B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8822B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -/****************************************************************************** -* FW_WOWLAN.TXT -******************************************************************************/ - -void -ODM_ReadFirmware_MP_8822B_FW_WOWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8822B_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8822B_H +#define __INC_MP_FW_HW_IMG_8822B_H + + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8822B_FW_AP( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8822B_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +/****************************************************************************** +* FW_WOWLAN.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8822B_FW_WOWLAN( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.c b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.c index 96bd3358743..3e48739b3cc 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.c @@ -1,291 +1,291 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_MAC_REG[] = { - 0x029, 0x000000F9, - 0x420, 0x00000080, - 0x421, 0x0000001F, - 0x428, 0x0000000A, - 0x429, 0x00000010, - 0x430, 0x00000000, - 0x431, 0x00000000, - 0x432, 0x00000000, - 0x433, 0x00000001, - 0x434, 0x00000004, - 0x435, 0x00000005, - 0x436, 0x00000007, - 0x437, 0x00000008, - 0x43C, 0x00000004, - 0x43D, 0x00000005, - 0x43E, 0x00000007, - 0x43F, 0x00000008, - 0x440, 0x0000005D, - 0x441, 0x00000001, - 0x442, 0x00000000, - 0x444, 0x00000010, - 0x445, 0x000000F0, - 0x446, 0x00000001, - 0x447, 0x000000FE, - 0x448, 0x00000000, - 0x449, 0x00000000, - 0x44A, 0x00000000, - 0x44B, 0x00000040, - 0x44C, 0x00000010, - 0x44D, 0x000000F0, - 0x44E, 0x0000003F, - 0x44F, 0x00000000, - 0x450, 0x00000000, - 0x451, 0x00000000, - 0x452, 0x00000000, - 0x453, 0x00000040, - 0x455, 0x00000070, - 0x45E, 0x00000004, - 0x49C, 0x00000010, - 0x49D, 0x000000F0, - 0x49E, 0x00000000, - 0x49F, 0x00000006, - 0x4A0, 0x000000E0, - 0x4A1, 0x00000003, - 0x4A2, 0x00000000, - 0x4A3, 0x00000040, - 0x4A4, 0x00000015, - 0x4A5, 0x000000F0, - 0x4A6, 0x00000000, - 0x4A7, 0x00000006, - 0x4A8, 0x000000E0, - 0x4A9, 0x00000000, - 0x4AA, 0x00000000, - 0x4AB, 0x00000000, - 0x7DA, 0x00000008, - 0x1448, 0x00000006, - 0x144A, 0x00000006, - 0x144C, 0x00000006, - 0x144E, 0x00000006, - 0x4C8, 0x000000FF, - 0x4C9, 0x00000008, - 0x4CA, 0x00000020, - 0x4CB, 0x00000020, - 0x4CC, 0x000000FF, - 0x4CD, 0x000000FF, - 0x4CE, 0x00000001, - 0x4CF, 0x00000008, - 0x500, 0x00000026, - 0x501, 0x000000A2, - 0x502, 0x0000002F, - 0x503, 0x00000000, - 0x504, 0x00000028, - 0x505, 0x000000A3, - 0x506, 0x0000005E, - 0x507, 0x00000000, - 0x508, 0x0000002B, - 0x509, 0x000000A4, - 0x50A, 0x0000005E, - 0x50B, 0x00000000, - 0x50C, 0x0000004F, - 0x50D, 0x000000A4, - 0x50E, 0x00000000, - 0x50F, 0x00000000, - 0x512, 0x0000001C, - 0x514, 0x0000000A, - 0x516, 0x0000000A, - 0x521, 0x0000002F, - 0x525, 0x0000004F, - 0x551, 0x00000010, - 0x559, 0x00000002, - 0x55C, 0x00000050, - 0x55D, 0x000000FF, - 0x577, 0x0000000B, - 0x5BE, 0x00000064, - 0x605, 0x00000030, - 0x608, 0x0000000E, - 0x609, 0x00000022, - 0x60C, 0x00000018, - 0x6A0, 0x000000FF, - 0x6A1, 0x000000FF, - 0x6A2, 0x000000FF, - 0x6A3, 0x000000FF, - 0x6A4, 0x000000FF, - 0x6A5, 0x000000FF, - 0x6DE, 0x00000084, - 0x620, 0x000000FF, - 0x621, 0x000000FF, - 0x622, 0x000000FF, - 0x623, 0x000000FF, - 0x624, 0x000000FF, - 0x625, 0x000000FF, - 0x626, 0x000000FF, - 0x627, 0x000000FF, - 0x638, 0x00000050, - 0x63C, 0x0000000A, - 0x63D, 0x0000000A, - 0x63E, 0x0000000E, - 0x63F, 0x0000000E, - 0x640, 0x00000040, - 0x642, 0x00000040, - 0x643, 0x00000000, - 0x652, 0x000000C8, - 0x66E, 0x00000005, - 0x718, 0x00000040, - 0x7D4, 0x00000098, - -}; - -void -ODM_ReadAndConfig_MP_8822B_MAC_REG( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_MAC_REG\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigMAC_8822B(pDM_Odm, v1, (u1Byte)v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8822B_MAC_REG(void) -{ - return 101; -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_MAC_REG[] = { + 0x029, 0x000000F9, + 0x420, 0x00000080, + 0x421, 0x0000001F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x000000F0, + 0x446, 0x00000001, + 0x447, 0x000000FE, + 0x448, 0x00000000, + 0x449, 0x00000000, + 0x44A, 0x00000000, + 0x44B, 0x00000040, + 0x44C, 0x00000010, + 0x44D, 0x000000F0, + 0x44E, 0x0000003F, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x00000000, + 0x452, 0x00000000, + 0x453, 0x00000040, + 0x455, 0x00000070, + 0x45E, 0x00000004, + 0x49C, 0x00000010, + 0x49D, 0x000000F0, + 0x49E, 0x00000000, + 0x49F, 0x00000006, + 0x4A0, 0x000000E0, + 0x4A1, 0x00000003, + 0x4A2, 0x00000000, + 0x4A3, 0x00000040, + 0x4A4, 0x00000015, + 0x4A5, 0x000000F0, + 0x4A6, 0x00000000, + 0x4A7, 0x00000006, + 0x4A8, 0x000000E0, + 0x4A9, 0x00000000, + 0x4AA, 0x00000000, + 0x4AB, 0x00000000, + 0x7DA, 0x00000008, + 0x1448, 0x00000006, + 0x144A, 0x00000006, + 0x144C, 0x00000006, + 0x144E, 0x00000006, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CA, 0x00000020, + 0x4CB, 0x00000020, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4CF, 0x00000008, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x521, 0x0000002F, + 0x525, 0x0000004F, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x577, 0x0000000B, + 0x5BE, 0x00000064, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x00000022, + 0x60C, 0x00000018, + 0x6A0, 0x000000FF, + 0x6A1, 0x000000FF, + 0x6A2, 0x000000FF, + 0x6A3, 0x000000FF, + 0x6A4, 0x000000FF, + 0x6A5, 0x000000FF, + 0x6DE, 0x00000084, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x718, 0x00000040, + 0x7D4, 0x00000098, + +}; + +void +ODM_ReadAndConfig_MP_8822B_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8822B_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8822B(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8822B_MAC_REG(void) +{ + return 101; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.h b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.h index d5844d517bb..005d9a93a77 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_mac.h @@ -1,34 +1,34 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __INC_MP_MAC_HW_IMG_8822B_H -#define __INC_MP_MAC_HW_IMG_8822B_H - - -/****************************************************************************** -* MAC_REG.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_MAC_REG(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8822B_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8822B_H +#define __INC_MP_MAC_HW_IMG_8822B_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.c b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.c index 856e871acb5..7b031f0b4b9 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.c @@ -1,15333 +1,15333 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 -) -{ - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - - u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; - u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; - - u4Byte driver1 = cut_version_for_para << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pkg_type_for_para << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - pDM_Odm->RFEType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - - /*PKG Type [15:12] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ - - cond1 &= 0x000000FF; - driver1 &= 0x000000FF; - - if (cond1 == driver1) - return TRUE; - else - return FALSE; -} -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 -) -{ - return TRUE; -} - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_RadioA[] = { - 0x000, 0x00030000, - 0x83000001, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000009, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000a, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000f, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0xA0000000, 0x00000000, - 0x001, 0x00040029, - 0xB0000000, 0x00000000, - 0x018, 0x00010D24, - 0x0EF, 0x00080000, - 0x033, 0x00000002, - 0x03E, 0x0000003F, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000D0F4E, - 0xA0000000, 0x00000000, - 0x03F, 0x000C0F4E, - 0xB0000000, 0x00000000, - 0x033, 0x00000001, - 0x03E, 0x00000034, - 0x03F, 0x0004080E, - 0x0EF, 0x00080000, - 0x0DF, 0x00002449, - 0x033, 0x00000024, - 0x03E, 0x0000003F, - 0x03F, 0x00060FDE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000025, - 0x03E, 0x00000037, - 0x03F, 0x0007EFCE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000026, - 0x03E, 0x00000037, - 0x03F, 0x000DEFCE, - 0x0EF, 0x00000000, - 0x07F, 0x00000000, - 0x83000000, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x93000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000009, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x9300000a, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x9300000e, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x9300000f, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FB0F8, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0xA0000000, 0x00000000, - 0x0B0, 0x000FF0F8, - 0xB0000000, 0x00000000, - 0x0B1, 0x0007DBE4, - 0x0B2, 0x000225D1, - 0x83000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x0007C330, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x0B3, 0x000FC760, - 0xA0000000, 0x00000000, - 0x0B3, 0x000FC760, - 0xB0000000, 0x00000000, - 0x0B4, 0x00099DD0, - 0x0B5, 0x000400FC, - 0x0B6, 0x000187F0, - 0x0B7, 0x00030018, - 0x0B8, 0x00080800, - 0x0B9, 0x00000000, - 0x0BA, 0x00008000, - 0x0BB, 0x00000000, - 0x0BC, 0x00040030, - 0x0BD, 0x00000000, - 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0x033, 0x00000009, - 0x03F, 0x00051CF4, - 0x033, 0x0000000A, - 0x03F, 0x00051CF7, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x0EF, 0x00000010, - 0x033, 0x00000000, - 0x008, 0x0009C060, - 0x033, 0x00000001, - 0x008, 0x0009C060, - 0x0EF, 0x00000000, - 0x033, 0x000000A2, - 0x0EF, 0x00080000, - 0x03E, 0x0000593F, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000D0F4F, - 0xA0000000, 0x00000000, - 0x03F, 0x000C0F4F, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x033, 0x000000A3, - 0x0EF, 0x00080000, - 0x03E, 0x00005934, - 0x03F, 0x0005AFCF, - 0x0EF, 0x00000000, - 0x83000002, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x0CE, 0x00094400, - 0xA0000000, 0x00000000, - 0x0CE, 0x00094C00, - 0xB0000000, 0x00000000, - 0x83000002, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00064700, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x0CF, 0x00072F00, - 0xA0000000, 0x00000000, - 0x0CF, 0x00064700, - 0xB0000000, 0x00000000, - 0x83000002, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000096, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x00000056, - 0x0EF, 0x00000000, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000004, - 0x033, 0x00000000, - 0x03F, 0x00000056, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x033, 0x00000000, - 0x03F, 0x00000096, - 0x033, 0x00000001, - 0x03F, 0x000000D6, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x0B0, 0x000FF0FC, - 0x0C4, 0x00081402, - 0x0CC, 0x00082000, - -}; - -void -ODM_ReadAndConfig_MP_8822B_RadioA( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioA_8822B(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8822B_RadioA(void) -{ - return 101; -} - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -u4Byte Array_MP_8822B_RadioB[] = { - 0x000, 0x00030000, - 0x83000001, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000009, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000a, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x9300000f, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000003, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000005, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x00040029, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x001, 0x0004002D, - 0xA0000000, 0x00000000, - 0x001, 0x00040029, - 0xB0000000, 0x00000000, - 0x018, 0x00010D24, - 0x0EF, 0x00080000, - 0x033, 0x00000002, - 0x03E, 0x0000003F, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000D0F4E, - 0xA0000000, 0x00000000, - 0x03F, 0x000C0F4E, - 0xB0000000, 0x00000000, - 0x033, 0x00000001, - 0x03E, 0x00000034, - 0x03F, 0x0004080E, - 0x0EF, 0x00080000, - 0x0DF, 0x00002449, - 0x033, 0x00000024, - 0x03E, 0x0000003F, - 0x03F, 0x00060FDE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000025, - 0x03E, 0x00000037, - 0x03F, 0x0007EFCE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000026, - 0x03E, 0x00000037, - 0x03F, 0x000DEFCE, - 0x0EF, 0x00000000, - 0x0DF, 0x00000009, - 0x018, 0x00010524, - 0x089, 0x00000207, - 0x83000001, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FF186, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FF186, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FE186, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FF186, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FF186, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FE186, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x08A, 0x000FF186, - 0xA0000000, 0x00000000, - 0x08A, 0x000FF186, - 0xB0000000, 0x00000000, - 0x08B, 0x00061E3C, - 0x08C, 0x000112C7, - 0x08D, 0x000F4988, - 0x08E, 0x00064D40, - 0x0EF, 0x00020000, - 0x033, 0x00000007, - 0x83000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x93000001, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004080, - 0x03F, 0x000C3186, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000009, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x9300000a, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000e, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000f, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x90000004, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x90000006, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004080, - 0x03F, 0x000C3186, - 0x90000007, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0xA0000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0xB0000000, 0x00000000, - 0x033, 0x00000006, - 0x03E, 0x00004080, - 0x03F, 0x000C3186, - 0x033, 0x00000005, - 0x03E, 0x000040C8, - 0x03F, 0x000C3186, - 0x033, 0x00000004, - 0x03E, 0x00004190, - 0x03F, 0x000C3186, - 0x033, 0x00000003, - 0x03E, 0x00004998, - 0x03F, 0x000C3186, - 0x033, 0x00000002, - 0x03E, 0x00005840, - 0x03F, 0x000C3186, - 0x033, 0x00000001, - 0x03E, 0x000058C2, - 0x03F, 0x000C3186, - 0x033, 0x00000000, - 0x03E, 0x00005930, - 0x03F, 0x000C3186, - 0x033, 0x0000000F, - 0x83000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x93000001, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000002, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000003, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000004, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000005, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x93000006, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004080, - 0x03F, 0x000C3186, - 0x93000007, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x93000008, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000009, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x9300000a, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000b, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004040, - 0x03F, 0x000C3186, - 0x9300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000e, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C3186, - 0x9300000f, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000010, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 0x03F, 0x000C0006, - 0x93000011, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00004000, - 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0x03F, 0x00051CF1, - 0x033, 0x00000009, - 0x03F, 0x00051CF4, - 0x033, 0x0000000A, - 0x03F, 0x00051CF7, - 0xB0000000, 0x00000000, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000010, - 0x033, 0x00000000, - 0x008, 0x0009C060, - 0x033, 0x00000001, - 0x008, 0x0009C060, - 0x0EF, 0x00000000, - 0x033, 0x000000A2, - 0x0EF, 0x00080000, - 0x03E, 0x0000593F, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000D0F4F, - 0xA0000000, 0x00000000, - 0x03F, 0x000C0F4F, - 0xB0000000, 0x00000000, - 0x0EF, 0x00000000, - 0x033, 0x000000A3, - 0x0EF, 0x00080000, - 0x03E, 0x00005934, - 0x03F, 0x0005AFCF, - 0x0EF, 0x00000000, - -}; - -void -ODM_ReadAndConfig_MP_8822B_RadioB( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; - } else { - bMatched = FALSE; - bSkipped = FALSE; - } - } else - bMatched = FALSE; - } - } else { - if (bMatched) - odm_ConfigRF_RadioB_8822B(pDM_Odm, v1, v2); - } - i = i + 2; - } -} - -u4Byte -ODM_GetVersion_MP_8822B_RadioB(void) -{ - return 101; -} - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type0.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type1.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type10.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type10( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type11.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type11( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type12.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type12_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type12_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type12_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type12_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type12( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type13.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type13( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type14.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type14( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type15.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type15_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type15_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type15_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type15_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type15( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type16.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type16_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type16_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type16_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type16_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type16( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type17.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type17_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type17_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type17( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type2.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type2_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type2_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type2_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type2_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type2( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_Type3_Type5.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type4.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type4_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type4_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type4_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type4_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type4( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type6.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, - {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type7.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, - {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, - {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type8.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type8( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TxPowerTrack_type9.TXT -******************************************************************************/ - -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, -}; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, -}; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type9( - IN PDM_ODM_T pDM_Odm -) -{ - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); - - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); - - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); -} - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type12.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type12[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type12)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type12; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type12)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type12; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type15.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type15[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type15)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type15; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type15)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type15; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type16.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type16[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type16)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type16; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type16)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type16; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type17.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type17[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type17)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type17; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type17)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type17; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type2.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type2[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "36", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "38", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "38", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "38", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "38", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "38", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "38", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "34", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "32", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "38", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "38", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "38", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "38", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "38", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "38", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "38", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "38", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "38", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "32", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "38", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "38", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "38", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "38", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "38", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "34", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "36", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "36", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "36", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "36", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "36", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "36", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "34", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "32", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "36", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "38", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "38", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "38", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "38", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "38", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "38", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "38", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "36", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "32", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "38", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "38", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "38", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "38", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "38", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "28", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "36", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "36", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "30", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "30", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "36", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "36", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "36", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "26", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "36", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "36", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "28", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "28", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "36", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "36", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "36", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "36", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "36", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "36", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "26", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "26", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "26", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "36", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "36", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "24", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "24", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "26", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "36", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "36", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "36", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type2)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type2; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type2)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type2; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type3.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type3[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type3)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type3; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type3)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type3; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type4.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type4[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "38", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "38", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "40", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "38", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "20", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "38", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "40", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "38", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "36", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "38", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "38", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "38", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "36", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "34", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "38", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "36", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "34", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "32", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "36", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "34", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "38", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "36", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "38", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "38", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "38", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "38", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "38", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "38", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "34", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "32", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "38", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "38", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "38", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "38", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "38", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "38", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "38", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "38", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "38", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "32", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "38", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "38", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "38", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "38", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "38", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "34", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "36", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "36", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "36", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "36", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "36", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "36", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "34", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "32", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "36", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "38", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "38", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "38", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "38", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "38", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "38", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "38", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "36", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "32", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "38", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "38", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "38", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "38", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "38", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "28", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "36", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "36", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "30", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "30", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "36", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "36", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "36", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "36", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "36", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "36", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "26", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "36", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "36", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "28", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "28", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "36", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "36", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "36", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "36", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "36", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "36", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "26", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "26", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "26", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "36", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "36", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "36", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "24", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "24", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "26", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "36", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "36", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "36", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type4)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type4; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type4)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type4; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -/****************************************************************************** -* TXPWR_LMT_type5.TXT -******************************************************************************/ - -const char *Array_MP_8822B_TXPWR_LMT_type5[] = { - "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", - "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", - "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", - "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", - "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", - "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", - "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", - "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", - "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", - "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", - "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", - "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", - "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", - "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", - "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", - "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", - "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", - "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", - "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", - "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", - "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "1T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", - "MKK", "2.4G", "20M", "HT", "1T", "01", "34", - "FCC", "2.4G", "20M", "HT", "1T", "02", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", - "MKK", "2.4G", "20M", "HT", "1T", "02", "34", - "FCC", "2.4G", "20M", "HT", "1T", "03", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", - "MKK", "2.4G", "20M", "HT", "1T", "03", "34", - "FCC", "2.4G", "20M", "HT", "1T", "04", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", - "MKK", "2.4G", "20M", "HT", "1T", "04", "34", - "FCC", "2.4G", "20M", "HT", "1T", "05", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", - "MKK", "2.4G", "20M", "HT", "1T", "05", "34", - "FCC", "2.4G", "20M", "HT", "1T", "06", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", - "MKK", "2.4G", "20M", "HT", "1T", "06", "34", - "FCC", "2.4G", "20M", "HT", "1T", "07", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", - "MKK", "2.4G", "20M", "HT", "1T", "07", "34", - "FCC", "2.4G", "20M", "HT", "1T", "08", "34", - "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", - "MKK", "2.4G", "20M", "HT", "1T", "08", "34", - "FCC", "2.4G", "20M", "HT", "1T", "09", "32", - "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", - "MKK", "2.4G", "20M", "HT", "1T", "09", "34", - "FCC", "2.4G", "20M", "HT", "1T", "10", "30", - "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", - "MKK", "2.4G", "20M", "HT", "1T", "10", "34", - "FCC", "2.4G", "20M", "HT", "1T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", - "MKK", "2.4G", "20M", "HT", "1T", "11", "34", - "FCC", "2.4G", "20M", "HT", "1T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", - "MKK", "2.4G", "20M", "HT", "1T", "12", "34", - "FCC", "2.4G", "20M", "HT", "1T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", - "MKK", "2.4G", "20M", "HT", "1T", "13", "34", - "FCC", "2.4G", "20M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", - "MKK", "2.4G", "20M", "HT", "1T", "14", "63", - "FCC", "2.4G", "20M", "HT", "2T", "01", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", - "MKK", "2.4G", "20M", "HT", "2T", "01", "30", - "FCC", "2.4G", "20M", "HT", "2T", "02", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", - "MKK", "2.4G", "20M", "HT", "2T", "02", "30", - "FCC", "2.4G", "20M", "HT", "2T", "03", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", - "MKK", "2.4G", "20M", "HT", "2T", "03", "30", - "FCC", "2.4G", "20M", "HT", "2T", "04", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", - "MKK", "2.4G", "20M", "HT", "2T", "04", "30", - "FCC", "2.4G", "20M", "HT", "2T", "05", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", - "MKK", "2.4G", "20M", "HT", "2T", "05", "30", - "FCC", "2.4G", "20M", "HT", "2T", "06", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", - "MKK", "2.4G", "20M", "HT", "2T", "06", "30", - "FCC", "2.4G", "20M", "HT", "2T", "07", "32", - "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", - "MKK", "2.4G", "20M", "HT", "2T", "07", "30", - "FCC", "2.4G", "20M", "HT", "2T", "08", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", - "MKK", "2.4G", "20M", "HT", "2T", "08", "30", - "FCC", "2.4G", "20M", "HT", "2T", "09", "30", - "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", - "MKK", "2.4G", "20M", "HT", "2T", "09", "30", - "FCC", "2.4G", "20M", "HT", "2T", "10", "28", - "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", - "MKK", "2.4G", "20M", "HT", "2T", "10", "30", - "FCC", "2.4G", "20M", "HT", "2T", "11", "26", - "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", - "MKK", "2.4G", "20M", "HT", "2T", "11", "30", - "FCC", "2.4G", "20M", "HT", "2T", "12", "20", - "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", - "MKK", "2.4G", "20M", "HT", "2T", "12", "30", - "FCC", "2.4G", "20M", "HT", "2T", "13", "14", - "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", - "MKK", "2.4G", "20M", "HT", "2T", "13", "30", - "FCC", "2.4G", "20M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", - "MKK", "2.4G", "20M", "HT", "2T", "14", "63", - "FCC", "2.4G", "40M", "HT", "1T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", - "MKK", "2.4G", "40M", "HT", "1T", "01", "63", - "FCC", "2.4G", "40M", "HT", "1T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", - "MKK", "2.4G", "40M", "HT", "1T", "02", "63", - "FCC", "2.4G", "40M", "HT", "1T", "03", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", - "MKK", "2.4G", "40M", "HT", "1T", "03", "34", - "FCC", "2.4G", "40M", "HT", "1T", "04", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", - "MKK", "2.4G", "40M", "HT", "1T", "04", "34", - "FCC", "2.4G", "40M", "HT", "1T", "05", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", - "MKK", "2.4G", "40M", "HT", "1T", "05", "34", - "FCC", "2.4G", "40M", "HT", "1T", "06", "32", - "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", - "MKK", "2.4G", "40M", "HT", "1T", "06", "34", - "FCC", "2.4G", "40M", "HT", "1T", "07", "30", - "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", - "MKK", "2.4G", "40M", "HT", "1T", "07", "34", - "FCC", "2.4G", "40M", "HT", "1T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", - "MKK", "2.4G", "40M", "HT", "1T", "08", "34", - "FCC", "2.4G", "40M", "HT", "1T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", - "MKK", "2.4G", "40M", "HT", "1T", "09", "34", - "FCC", "2.4G", "40M", "HT", "1T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", - "MKK", "2.4G", "40M", "HT", "1T", "10", "34", - "FCC", "2.4G", "40M", "HT", "1T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", - "MKK", "2.4G", "40M", "HT", "1T", "11", "34", - "FCC", "2.4G", "40M", "HT", "1T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", - "MKK", "2.4G", "40M", "HT", "1T", "12", "63", - "FCC", "2.4G", "40M", "HT", "1T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", - "MKK", "2.4G", "40M", "HT", "1T", "13", "63", - "FCC", "2.4G", "40M", "HT", "1T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", - "MKK", "2.4G", "40M", "HT", "1T", "14", "63", - "FCC", "2.4G", "40M", "HT", "2T", "01", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", - "MKK", "2.4G", "40M", "HT", "2T", "01", "63", - "FCC", "2.4G", "40M", "HT", "2T", "02", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", - "MKK", "2.4G", "40M", "HT", "2T", "02", "63", - "FCC", "2.4G", "40M", "HT", "2T", "03", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", - "MKK", "2.4G", "40M", "HT", "2T", "03", "30", - "FCC", "2.4G", "40M", "HT", "2T", "04", "24", - "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", - "MKK", "2.4G", "40M", "HT", "2T", "04", "30", - "FCC", "2.4G", "40M", "HT", "2T", "05", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", - "MKK", "2.4G", "40M", "HT", "2T", "05", "30", - "FCC", "2.4G", "40M", "HT", "2T", "06", "28", - "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", - "MKK", "2.4G", "40M", "HT", "2T", "06", "30", - "FCC", "2.4G", "40M", "HT", "2T", "07", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", - "MKK", "2.4G", "40M", "HT", "2T", "07", "30", - "FCC", "2.4G", "40M", "HT", "2T", "08", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", - "MKK", "2.4G", "40M", "HT", "2T", "08", "30", - "FCC", "2.4G", "40M", "HT", "2T", "09", "26", - "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", - "MKK", "2.4G", "40M", "HT", "2T", "09", "30", - "FCC", "2.4G", "40M", "HT", "2T", "10", "20", - "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", - "MKK", "2.4G", "40M", "HT", "2T", "10", "30", - "FCC", "2.4G", "40M", "HT", "2T", "11", "14", - "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", - "MKK", "2.4G", "40M", "HT", "2T", "11", "30", - "FCC", "2.4G", "40M", "HT", "2T", "12", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", - "MKK", "2.4G", "40M", "HT", "2T", "12", "63", - "FCC", "2.4G", "40M", "HT", "2T", "13", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", - "MKK", "2.4G", "40M", "HT", "2T", "13", "63", - "FCC", "2.4G", "40M", "HT", "2T", "14", "63", - "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", - "MKK", "2.4G", "40M", "HT", "2T", "14", "63", - "FCC", "5G", "20M", "OFDM", "1T", "36", "30", - "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", - "MKK", "5G", "20M", "OFDM", "1T", "36", "30", - "FCC", "5G", "20M", "OFDM", "1T", "40", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", - "MKK", "5G", "20M", "OFDM", "1T", "40", "30", - "FCC", "5G", "20M", "OFDM", "1T", "44", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", - "MKK", "5G", "20M", "OFDM", "1T", "44", "30", - "FCC", "5G", "20M", "OFDM", "1T", "48", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", - "MKK", "5G", "20M", "OFDM", "1T", "48", "30", - "FCC", "5G", "20M", "OFDM", "1T", "52", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", - "MKK", "5G", "20M", "OFDM", "1T", "52", "28", - "FCC", "5G", "20M", "OFDM", "1T", "56", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", - "MKK", "5G", "20M", "OFDM", "1T", "56", "28", - "FCC", "5G", "20M", "OFDM", "1T", "60", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", - "MKK", "5G", "20M", "OFDM", "1T", "60", "28", - "FCC", "5G", "20M", "OFDM", "1T", "64", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", - "MKK", "5G", "20M", "OFDM", "1T", "64", "28", - "FCC", "5G", "20M", "OFDM", "1T", "100", "26", - "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", - "MKK", "5G", "20M", "OFDM", "1T", "100", "32", - "FCC", "5G", "20M", "OFDM", "1T", "104", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", - "MKK", "5G", "20M", "OFDM", "1T", "104", "32", - "FCC", "5G", "20M", "OFDM", "1T", "108", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", - "MKK", "5G", "20M", "OFDM", "1T", "108", "32", - "FCC", "5G", "20M", "OFDM", "1T", "112", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", - "MKK", "5G", "20M", "OFDM", "1T", "112", "32", - "FCC", "5G", "20M", "OFDM", "1T", "116", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", - "MKK", "5G", "20M", "OFDM", "1T", "116", "32", - "FCC", "5G", "20M", "OFDM", "1T", "120", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", - "MKK", "5G", "20M", "OFDM", "1T", "120", "32", - "FCC", "5G", "20M", "OFDM", "1T", "124", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", - "MKK", "5G", "20M", "OFDM", "1T", "124", "32", - "FCC", "5G", "20M", "OFDM", "1T", "128", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", - "MKK", "5G", "20M", "OFDM", "1T", "128", "32", - "FCC", "5G", "20M", "OFDM", "1T", "132", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", - "MKK", "5G", "20M", "OFDM", "1T", "132", "32", - "FCC", "5G", "20M", "OFDM", "1T", "136", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", - "MKK", "5G", "20M", "OFDM", "1T", "136", "32", - "FCC", "5G", "20M", "OFDM", "1T", "140", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", - "MKK", "5G", "20M", "OFDM", "1T", "140", "32", - "FCC", "5G", "20M", "OFDM", "1T", "144", "28", - "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", - "MKK", "5G", "20M", "OFDM", "1T", "144", "63", - "FCC", "5G", "20M", "OFDM", "1T", "149", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", - "MKK", "5G", "20M", "OFDM", "1T", "149", "63", - "FCC", "5G", "20M", "OFDM", "1T", "153", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", - "MKK", "5G", "20M", "OFDM", "1T", "153", "63", - "FCC", "5G", "20M", "OFDM", "1T", "157", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", - "MKK", "5G", "20M", "OFDM", "1T", "157", "63", - "FCC", "5G", "20M", "OFDM", "1T", "161", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", - "MKK", "5G", "20M", "OFDM", "1T", "161", "63", - "FCC", "5G", "20M", "OFDM", "1T", "165", "32", - "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", - "MKK", "5G", "20M", "OFDM", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "1T", "36", "30", - "ETSI", "5G", "20M", "HT", "1T", "36", "32", - "MKK", "5G", "20M", "HT", "1T", "36", "28", - "FCC", "5G", "20M", "HT", "1T", "40", "32", - "ETSI", "5G", "20M", "HT", "1T", "40", "32", - "MKK", "5G", "20M", "HT", "1T", "40", "28", - "FCC", "5G", "20M", "HT", "1T", "44", "32", - "ETSI", "5G", "20M", "HT", "1T", "44", "32", - "MKK", "5G", "20M", "HT", "1T", "44", "28", - "FCC", "5G", "20M", "HT", "1T", "48", "32", - "ETSI", "5G", "20M", "HT", "1T", "48", "32", - "MKK", "5G", "20M", "HT", "1T", "48", "28", - "FCC", "5G", "20M", "HT", "1T", "52", "32", - "ETSI", "5G", "20M", "HT", "1T", "52", "32", - "MKK", "5G", "20M", "HT", "1T", "52", "28", - "FCC", "5G", "20M", "HT", "1T", "56", "32", - "ETSI", "5G", "20M", "HT", "1T", "56", "32", - "MKK", "5G", "20M", "HT", "1T", "56", "28", - "FCC", "5G", "20M", "HT", "1T", "60", "32", - "ETSI", "5G", "20M", "HT", "1T", "60", "32", - "MKK", "5G", "20M", "HT", "1T", "60", "28", - "FCC", "5G", "20M", "HT", "1T", "64", "28", - "ETSI", "5G", "20M", "HT", "1T", "64", "32", - "MKK", "5G", "20M", "HT", "1T", "64", "28", - "FCC", "5G", "20M", "HT", "1T", "100", "26", - "ETSI", "5G", "20M", "HT", "1T", "100", "32", - "MKK", "5G", "20M", "HT", "1T", "100", "32", - "FCC", "5G", "20M", "HT", "1T", "104", "32", - "ETSI", "5G", "20M", "HT", "1T", "104", "32", - "MKK", "5G", "20M", "HT", "1T", "104", "32", - "FCC", "5G", "20M", "HT", "1T", "108", "32", - "ETSI", "5G", "20M", "HT", "1T", "108", "32", - "MKK", "5G", "20M", "HT", "1T", "108", "32", - "FCC", "5G", "20M", "HT", "1T", "112", "32", - "ETSI", "5G", "20M", "HT", "1T", "112", "32", - "MKK", "5G", "20M", "HT", "1T", "112", "32", - "FCC", "5G", "20M", "HT", "1T", "116", "32", - "ETSI", "5G", "20M", "HT", "1T", "116", "32", - "MKK", "5G", "20M", "HT", "1T", "116", "32", - "FCC", "5G", "20M", "HT", "1T", "120", "32", - "ETSI", "5G", "20M", "HT", "1T", "120", "32", - "MKK", "5G", "20M", "HT", "1T", "120", "32", - "FCC", "5G", "20M", "HT", "1T", "124", "32", - "ETSI", "5G", "20M", "HT", "1T", "124", "32", - "MKK", "5G", "20M", "HT", "1T", "124", "32", - "FCC", "5G", "20M", "HT", "1T", "128", "32", - "ETSI", "5G", "20M", "HT", "1T", "128", "32", - "MKK", "5G", "20M", "HT", "1T", "128", "32", - "FCC", "5G", "20M", "HT", "1T", "132", "32", - "ETSI", "5G", "20M", "HT", "1T", "132", "32", - "MKK", "5G", "20M", "HT", "1T", "132", "32", - "FCC", "5G", "20M", "HT", "1T", "136", "32", - "ETSI", "5G", "20M", "HT", "1T", "136", "32", - "MKK", "5G", "20M", "HT", "1T", "136", "32", - "FCC", "5G", "20M", "HT", "1T", "140", "26", - "ETSI", "5G", "20M", "HT", "1T", "140", "32", - "MKK", "5G", "20M", "HT", "1T", "140", "32", - "FCC", "5G", "20M", "HT", "1T", "144", "26", - "ETSI", "5G", "20M", "HT", "1T", "144", "63", - "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "32", - "ETSI", "5G", "20M", "HT", "1T", "149", "63", - "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "32", - "ETSI", "5G", "20M", "HT", "1T", "153", "63", - "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "32", - "ETSI", "5G", "20M", "HT", "1T", "157", "63", - "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "32", - "ETSI", "5G", "20M", "HT", "1T", "161", "63", - "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "32", - "ETSI", "5G", "20M", "HT", "1T", "165", "63", - "MKK", "5G", "20M", "HT", "1T", "165", "63", - "FCC", "5G", "20M", "HT", "2T", "36", "28", - "ETSI", "5G", "20M", "HT", "2T", "36", "20", - "MKK", "5G", "20M", "HT", "2T", "36", "22", - "FCC", "5G", "20M", "HT", "2T", "40", "30", - "ETSI", "5G", "20M", "HT", "2T", "40", "20", - "MKK", "5G", "20M", "HT", "2T", "40", "22", - "FCC", "5G", "20M", "HT", "2T", "44", "30", - "ETSI", "5G", "20M", "HT", "2T", "44", "20", - "MKK", "5G", "20M", "HT", "2T", "44", "22", - "FCC", "5G", "20M", "HT", "2T", "48", "30", - "ETSI", "5G", "20M", "HT", "2T", "48", "20", - "MKK", "5G", "20M", "HT", "2T", "48", "22", - "FCC", "5G", "20M", "HT", "2T", "52", "30", - "ETSI", "5G", "20M", "HT", "2T", "52", "20", - "MKK", "5G", "20M", "HT", "2T", "52", "22", - "FCC", "5G", "20M", "HT", "2T", "56", "30", - "ETSI", "5G", "20M", "HT", "2T", "56", "20", - "MKK", "5G", "20M", "HT", "2T", "56", "22", - "FCC", "5G", "20M", "HT", "2T", "60", "30", - "ETSI", "5G", "20M", "HT", "2T", "60", "20", - "MKK", "5G", "20M", "HT", "2T", "60", "22", - "FCC", "5G", "20M", "HT", "2T", "64", "28", - "ETSI", "5G", "20M", "HT", "2T", "64", "20", - "MKK", "5G", "20M", "HT", "2T", "64", "22", - "FCC", "5G", "20M", "HT", "2T", "100", "26", - "ETSI", "5G", "20M", "HT", "2T", "100", "20", - "MKK", "5G", "20M", "HT", "2T", "100", "30", - "FCC", "5G", "20M", "HT", "2T", "104", "30", - "ETSI", "5G", "20M", "HT", "2T", "104", "20", - "MKK", "5G", "20M", "HT", "2T", "104", "30", - "FCC", "5G", "20M", "HT", "2T", "108", "32", - "ETSI", "5G", "20M", "HT", "2T", "108", "20", - "MKK", "5G", "20M", "HT", "2T", "108", "30", - "FCC", "5G", "20M", "HT", "2T", "112", "32", - "ETSI", "5G", "20M", "HT", "2T", "112", "20", - "MKK", "5G", "20M", "HT", "2T", "112", "30", - "FCC", "5G", "20M", "HT", "2T", "116", "32", - "ETSI", "5G", "20M", "HT", "2T", "116", "20", - "MKK", "5G", "20M", "HT", "2T", "116", "30", - "FCC", "5G", "20M", "HT", "2T", "120", "32", - "ETSI", "5G", "20M", "HT", "2T", "120", "20", - "MKK", "5G", "20M", "HT", "2T", "120", "30", - "FCC", "5G", "20M", "HT", "2T", "124", "32", - "ETSI", "5G", "20M", "HT", "2T", "124", "20", - "MKK", "5G", "20M", "HT", "2T", "124", "30", - "FCC", "5G", "20M", "HT", "2T", "128", "32", - "ETSI", "5G", "20M", "HT", "2T", "128", "20", - "MKK", "5G", "20M", "HT", "2T", "128", "30", - "FCC", "5G", "20M", "HT", "2T", "132", "32", - "ETSI", "5G", "20M", "HT", "2T", "132", "20", - "MKK", "5G", "20M", "HT", "2T", "132", "30", - "FCC", "5G", "20M", "HT", "2T", "136", "30", - "ETSI", "5G", "20M", "HT", "2T", "136", "20", - "MKK", "5G", "20M", "HT", "2T", "136", "30", - "FCC", "5G", "20M", "HT", "2T", "140", "26", - "ETSI", "5G", "20M", "HT", "2T", "140", "20", - "MKK", "5G", "20M", "HT", "2T", "140", "30", - "FCC", "5G", "20M", "HT", "2T", "144", "26", - "ETSI", "5G", "20M", "HT", "2T", "144", "63", - "MKK", "5G", "20M", "HT", "2T", "144", "63", - "FCC", "5G", "20M", "HT", "2T", "149", "32", - "ETSI", "5G", "20M", "HT", "2T", "149", "63", - "MKK", "5G", "20M", "HT", "2T", "149", "63", - "FCC", "5G", "20M", "HT", "2T", "153", "32", - "ETSI", "5G", "20M", "HT", "2T", "153", "63", - "MKK", "5G", "20M", "HT", "2T", "153", "63", - "FCC", "5G", "20M", "HT", "2T", "157", "32", - "ETSI", "5G", "20M", "HT", "2T", "157", "63", - "MKK", "5G", "20M", "HT", "2T", "157", "63", - "FCC", "5G", "20M", "HT", "2T", "161", "32", - "ETSI", "5G", "20M", "HT", "2T", "161", "63", - "MKK", "5G", "20M", "HT", "2T", "161", "63", - "FCC", "5G", "20M", "HT", "2T", "165", "32", - "ETSI", "5G", "20M", "HT", "2T", "165", "63", - "MKK", "5G", "20M", "HT", "2T", "165", "63", - "FCC", "5G", "40M", "HT", "1T", "38", "22", - "ETSI", "5G", "40M", "HT", "1T", "38", "30", - "MKK", "5G", "40M", "HT", "1T", "38", "30", - "FCC", "5G", "40M", "HT", "1T", "46", "30", - "ETSI", "5G", "40M", "HT", "1T", "46", "30", - "MKK", "5G", "40M", "HT", "1T", "46", "30", - "FCC", "5G", "40M", "HT", "1T", "54", "30", - "ETSI", "5G", "40M", "HT", "1T", "54", "30", - "MKK", "5G", "40M", "HT", "1T", "54", "30", - "FCC", "5G", "40M", "HT", "1T", "62", "24", - "ETSI", "5G", "40M", "HT", "1T", "62", "30", - "MKK", "5G", "40M", "HT", "1T", "62", "30", - "FCC", "5G", "40M", "HT", "1T", "102", "24", - "ETSI", "5G", "40M", "HT", "1T", "102", "30", - "MKK", "5G", "40M", "HT", "1T", "102", "30", - "FCC", "5G", "40M", "HT", "1T", "110", "30", - "ETSI", "5G", "40M", "HT", "1T", "110", "30", - "MKK", "5G", "40M", "HT", "1T", "110", "30", - "FCC", "5G", "40M", "HT", "1T", "118", "30", - "ETSI", "5G", "40M", "HT", "1T", "118", "30", - "MKK", "5G", "40M", "HT", "1T", "118", "30", - "FCC", "5G", "40M", "HT", "1T", "126", "30", - "ETSI", "5G", "40M", "HT", "1T", "126", "30", - "MKK", "5G", "40M", "HT", "1T", "126", "30", - "FCC", "5G", "40M", "HT", "1T", "134", "30", - "ETSI", "5G", "40M", "HT", "1T", "134", "30", - "MKK", "5G", "40M", "HT", "1T", "134", "30", - "FCC", "5G", "40M", "HT", "1T", "142", "30", - "ETSI", "5G", "40M", "HT", "1T", "142", "63", - "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "30", - "ETSI", "5G", "40M", "HT", "1T", "151", "63", - "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "30", - "ETSI", "5G", "40M", "HT", "1T", "159", "63", - "MKK", "5G", "40M", "HT", "1T", "159", "63", - "FCC", "5G", "40M", "HT", "2T", "38", "20", - "ETSI", "5G", "40M", "HT", "2T", "38", "20", - "MKK", "5G", "40M", "HT", "2T", "38", "22", - "FCC", "5G", "40M", "HT", "2T", "46", "30", - "ETSI", "5G", "40M", "HT", "2T", "46", "20", - "MKK", "5G", "40M", "HT", "2T", "46", "22", - "FCC", "5G", "40M", "HT", "2T", "54", "30", - "ETSI", "5G", "40M", "HT", "2T", "54", "20", - "MKK", "5G", "40M", "HT", "2T", "54", "22", - "FCC", "5G", "40M", "HT", "2T", "62", "22", - "ETSI", "5G", "40M", "HT", "2T", "62", "20", - "MKK", "5G", "40M", "HT", "2T", "62", "22", - "FCC", "5G", "40M", "HT", "2T", "102", "22", - "ETSI", "5G", "40M", "HT", "2T", "102", "20", - "MKK", "5G", "40M", "HT", "2T", "102", "30", - "FCC", "5G", "40M", "HT", "2T", "110", "30", - "ETSI", "5G", "40M", "HT", "2T", "110", "20", - "MKK", "5G", "40M", "HT", "2T", "110", "30", - "FCC", "5G", "40M", "HT", "2T", "118", "30", - "ETSI", "5G", "40M", "HT", "2T", "118", "20", - "MKK", "5G", "40M", "HT", "2T", "118", "30", - "FCC", "5G", "40M", "HT", "2T", "126", "30", - "ETSI", "5G", "40M", "HT", "2T", "126", "20", - "MKK", "5G", "40M", "HT", "2T", "126", "30", - "FCC", "5G", "40M", "HT", "2T", "134", "30", - "ETSI", "5G", "40M", "HT", "2T", "134", "20", - "MKK", "5G", "40M", "HT", "2T", "134", "30", - "FCC", "5G", "40M", "HT", "2T", "142", "30", - "ETSI", "5G", "40M", "HT", "2T", "142", "63", - "MKK", "5G", "40M", "HT", "2T", "142", "63", - "FCC", "5G", "40M", "HT", "2T", "151", "30", - "ETSI", "5G", "40M", "HT", "2T", "151", "63", - "MKK", "5G", "40M", "HT", "2T", "151", "63", - "FCC", "5G", "40M", "HT", "2T", "159", "30", - "ETSI", "5G", "40M", "HT", "2T", "159", "63", - "MKK", "5G", "40M", "HT", "2T", "159", "63", - "FCC", "5G", "80M", "VHT", "1T", "42", "20", - "ETSI", "5G", "80M", "VHT", "1T", "42", "30", - "MKK", "5G", "80M", "VHT", "1T", "42", "28", - "FCC", "5G", "80M", "VHT", "1T", "58", "20", - "ETSI", "5G", "80M", "VHT", "1T", "58", "30", - "MKK", "5G", "80M", "VHT", "1T", "58", "28", - "FCC", "5G", "80M", "VHT", "1T", "106", "20", - "ETSI", "5G", "80M", "VHT", "1T", "106", "30", - "MKK", "5G", "80M", "VHT", "1T", "106", "30", - "FCC", "5G", "80M", "VHT", "1T", "122", "30", - "ETSI", "5G", "80M", "VHT", "1T", "122", "30", - "MKK", "5G", "80M", "VHT", "1T", "122", "30", - "FCC", "5G", "80M", "VHT", "1T", "138", "30", - "ETSI", "5G", "80M", "VHT", "1T", "138", "63", - "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "30", - "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63", - "FCC", "5G", "80M", "VHT", "2T", "42", "18", - "ETSI", "5G", "80M", "VHT", "2T", "42", "20", - "MKK", "5G", "80M", "VHT", "2T", "42", "22", - "FCC", "5G", "80M", "VHT", "2T", "58", "18", - "ETSI", "5G", "80M", "VHT", "2T", "58", "20", - "MKK", "5G", "80M", "VHT", "2T", "58", "22", - "FCC", "5G", "80M", "VHT", "2T", "106", "20", - "ETSI", "5G", "80M", "VHT", "2T", "106", "20", - "MKK", "5G", "80M", "VHT", "2T", "106", "30", - "FCC", "5G", "80M", "VHT", "2T", "122", "30", - "ETSI", "5G", "80M", "VHT", "2T", "122", "20", - "MKK", "5G", "80M", "VHT", "2T", "122", "30", - "FCC", "5G", "80M", "VHT", "2T", "138", "30", - "ETSI", "5G", "80M", "VHT", "2T", "138", "63", - "MKK", "5G", "80M", "VHT", "2T", "138", "63", - "FCC", "5G", "80M", "VHT", "2T", "155", "30", - "ETSI", "5G", "80M", "VHT", "2T", "155", "63", - "MKK", "5G", "80M", "VHT", "2T", "155", "63" -}; - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte i = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type5)/sizeof(u1Byte); - pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type5; -#else - u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type5)/sizeof(pu1Byte); - pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type5; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrLmt = ArrayLen/7; -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5\n")); - - for (i = 0; i < ArrayLen; i += 7) { -#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u1Byte regulation = Array[i]; - u1Byte band = Array[i+1]; - u1Byte bandwidth = Array[i+2]; - u1Byte rate = Array[i+3]; - u1Byte rfPath = Array[i+4]; - u1Byte chnl = Array[i+5]; - u1Byte val = Array[i+6]; -#else - pu1Byte regulation = Array[i]; - pu1Byte band = Array[i+1]; - pu1Byte bandwidth = Array[i+2]; - pu1Byte rate = Array[i+3]; - pu1Byte rfPath = Array[i+4]; - pu1Byte chnl = Array[i+5]; - pu1Byte val = Array[i+6]; -#endif - - odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", - regulation, band, bandwidth, rate, rfPath, chnl, val); -#endif - } - -} - -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + + u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion; + u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType; + + u4Byte driver1 = cut_version_for_para << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pkg_type_for_para << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + pDM_Odm->RFEType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", pDM_Odm->RFEType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*PKG Type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return TRUE; + else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_RadioA[] = { + 0x000, 0x00030000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0xA0000000, 0x00000000, + 0x001, 0x00040029, + 0xB0000000, 0x00000000, + 0x018, 0x00010D24, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4E, + 0xA0000000, 0x00000000, + 0x03F, 0x000C0F4E, + 0xB0000000, 0x00000000, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0x0EF, 0x00080000, + 0x0DF, 0x00002449, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x000DEFCE, + 0x0EF, 0x00000000, + 0x07F, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 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+ 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0xA0000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005144B, + 0x033, 0x00000002, + 0x03F, 0x0005144E, + 0x033, 0x00000003, + 0x03F, 0x00051C69, + 0x033, 0x00000004, + 0x03F, 0x00051C6C, + 0x033, 0x00000005, + 0x03F, 0x00051C6F, + 0x033, 0x00000006, + 0x03F, 0x00051CEB, + 0x033, 0x00000007, + 0x03F, 0x00051CEE, + 0x033, 0x00000008, + 0x03F, 0x00051CF1, + 0x033, 0x00000009, + 0x03F, 0x00051CF4, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0x033, 0x000000A2, + 0x0EF, 0x00080000, + 0x03E, 0x0000593F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4F, + 0xA0000000, 0x00000000, + 0x03F, 0x000C0F4F, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x033, 0x000000A3, + 0x0EF, 0x00080000, + 0x03E, 0x00005934, + 0x03F, 0x0005AFCF, + 0x0EF, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0xA0000000, 0x00000000, + 0x0CE, 0x00094C00, + 0xB0000000, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00064700, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0xA0000000, 0x00000000, + 0x0CF, 0x00064700, + 0xB0000000, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000096, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x00000056, + 0x0EF, 0x00000000, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000096, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0B0, 0x000FF0FC, + 0x0C4, 0x00081402, + 0x0CC, 0x00082000, + +}; + +void +ODM_ReadAndConfig_MP_8822B_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8822B(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8822B_RadioA(void) +{ + return 101; +} + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +u4Byte Array_MP_8822B_RadioB[] = { + 0x000, 0x00030000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0xA0000000, 0x00000000, + 0x001, 0x00040029, + 0xB0000000, 0x00000000, + 0x018, 0x00010D24, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4E, + 0xA0000000, 0x00000000, + 0x03F, 0x000C0F4E, + 0xB0000000, 0x00000000, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0x0EF, 0x00080000, + 0x0DF, 0x00002449, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x000DEFCE, + 0x0EF, 0x00000000, + 0x0DF, 0x00000009, + 0x018, 0x00010524, + 0x089, 0x00000207, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FE186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FE186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0xA0000000, 0x00000000, + 0x08A, 0x000FF186, + 0xB0000000, 0x00000000, + 0x08B, 0x00061E3C, + 0x08C, 0x000112C7, + 0x08D, 0x000F4988, + 0x08E, 0x00064D40, + 0x0EF, 0x00020000, + 0x033, 0x00000007, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, + 0x033, 0x00000006, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x03E, 0x000040C8, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x03E, 0x00004190, + 0x03F, 0x000C3186, + 0x033, 0x00000003, + 0x03E, 0x00004998, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x00005840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x000058C2, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x00005930, + 0x03F, 0x000C3186, + 0x033, 0x0000000F, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 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0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005142F, + 0x033, 0x00000002, + 0x03F, 0x00051432, + 0x033, 0x00000003, + 0x03F, 0x00051CA5, + 0x033, 0x00000004, + 0x03F, 0x00051CA8, + 0x033, 0x00000005, + 0x03F, 0x00051CAB, + 0x033, 0x00000006, + 0x03F, 0x00051CEB, + 0x033, 0x00000007, + 0x03F, 0x00051CEE, + 0x033, 0x00000008, + 0x03F, 0x00051CF1, + 0x033, 0x00000009, + 0x03F, 0x00051CF4, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005144B, + 0x033, 0x00000002, + 0x03F, 0x00051868, + 0x033, 0x00000003, + 0x03F, 0x0005186B, + 0x033, 0x00000004, + 0x03F, 0x0005186E, + 0x033, 0x00000005, + 0x03F, 0x00051871, + 0x033, 0x00000006, + 0x03F, 0x00051874, + 0x033, 0x00000007, + 0x03F, 0x00051895, + 0x033, 0x00000008, + 0x03F, 0x000518B6, + 0x033, 0x00000009, + 0x03F, 0x000518F6, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0xA0000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005142F, + 0x033, 0x00000002, + 0x03F, 0x00051432, + 0x033, 0x00000003, + 0x03F, 0x00051C87, + 0x033, 0x00000004, + 0x03F, 0x00051C8A, + 0x033, 0x00000005, + 0x03F, 0x00051C8D, + 0x033, 0x00000006, + 0x03F, 0x00051CEB, + 0x033, 0x00000007, + 0x03F, 0x00051CEE, + 0x033, 0x00000008, + 0x03F, 0x00051CF1, + 0x033, 0x00000009, + 0x03F, 0x00051CF4, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, + 0xB0000000, 0x00000000, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0x033, 0x000000A2, + 0x0EF, 0x00080000, + 0x03E, 0x0000593F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4F, + 0xA0000000, 0x00000000, + 0x03F, 0x000C0F4F, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x033, 0x000000A3, + 0x0EF, 0x00080000, + 0x03E, 0x00005934, + 0x03F, 0x0005AFCF, + 0x0EF, 0x00000000, + +}; + +void +ODM_ReadAndConfig_MP_8822B_RadioB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8822B_RadioB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioB_8822B(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8822B_RadioB(void) +{ + return 101; +} + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type0.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type1.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type10.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type10_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type10_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type10_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type10( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type10_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type11.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type11_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type11_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type11_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type11( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type11_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type12.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type12_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type12_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type12_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type12_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type12_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type12_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type12( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type12_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type13.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type13_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type13_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type13_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type13( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type13_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type14.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type14_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type14_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type14_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type14( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type14_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type15.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type15_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type15_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type15_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type15_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type15_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type15_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type15( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type15_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type16.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type16_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type16_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type16_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type16_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type16_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type16_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type16( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type16_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type17.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type17_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type17_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type17_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type17_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type17( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type17_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type2.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type2_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type2_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type2_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type2_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type2_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type2_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type2( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type2_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_Type3_Type5.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type4.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type4_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type4_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type4_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type4_8822B[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type4_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type4_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type4( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type4_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type6.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, + {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type7.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, + {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, + {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type8.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type8_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type8_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type8_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type8( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type8_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TxPowerTrack_type9.TXT +******************************************************************************/ + +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type9_8822B[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type9_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type9_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type9( + IN PDM_ODM_T pDM_Odm +) +{ + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type9_8822B, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type12.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type12[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type12)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type12; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type12)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type12; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type15.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type15[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type15)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type15; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type15)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type15; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type16.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type16[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type16)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type16; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type16)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type16; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type17.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type17[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type17)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type17; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type17)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type17; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type2.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type2[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "36", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "38", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "38", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "38", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "38", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "38", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "38", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "38", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "38", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "38", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "38", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "38", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "38", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "38", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "38", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "38", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "38", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "38", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "38", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "38", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "38", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "36", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "36", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "36", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "36", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "36", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "38", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "38", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "38", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "38", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "38", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "38", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "38", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "36", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "32", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "38", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "38", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "38", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "38", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "38", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "30", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "36", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "36", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "28", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "36", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "36", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "26", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "26", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "36", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "36", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "24", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "36", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "36", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "36", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type2)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type2; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type2)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type2; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type3.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type3[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type3)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type3; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type3)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type3; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type4.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type4[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "38", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "38", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "38", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "38", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "38", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "36", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "38", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "38", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "38", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "38", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "38", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "38", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "38", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "38", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "38", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "38", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "38", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "38", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "38", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "38", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "38", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "38", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "38", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "38", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "38", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "38", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "36", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "36", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "36", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "36", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "36", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "38", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "38", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "38", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "38", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "38", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "38", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "38", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "36", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "32", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "38", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "38", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "38", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "38", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "38", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "30", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "36", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "36", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "28", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "36", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "36", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "26", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "26", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "36", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "36", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "24", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "36", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "36", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "36", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type4)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type4; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type4)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type4; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +/****************************************************************************** +* TXPWR_LMT_type5.TXT +******************************************************************************/ + +const char *Array_MP_8822B_TXPWR_LMT_type5[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type5)/sizeof(u1Byte); + pu1Byte Array = (pu1Byte)Array_MP_8822B_TXPWR_LMT_type5; +#else + u4Byte ArrayLen = sizeof(Array_MP_8822B_TXPWR_LMT_type5)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8822B_TXPWR_LMT_type5; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5\n")); + + for (i = 0; i < ArrayLen; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u1Byte regulation = Array[i]; + u1Byte band = Array[i+1]; + u1Byte bandwidth = Array[i+2]; + u1Byte rate = Array[i+3]; + u1Byte rfPath = Array[i+4]; + u1Byte chnl = Array[i+5]; + u1Byte val = Array[i+6]; +#else + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; +#endif + + odm_ConfigBB_TXPWR_LMT_8822B(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.h b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.h index 82a08f3a27d..2fdbdb445e6 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halhwimg8822b_rf.h @@ -1,314 +1,314 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1 non coding style*/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __INC_MP_RF_HW_IMG_8822B_H -#define __INC_MP_RF_HW_IMG_8822B_H - - -/****************************************************************************** -* RadioA.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_RadioA(void); - -/****************************************************************************** -* RadioB.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_RadioB(void); - -/****************************************************************************** -* TxPowerTrack.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack(void); - -/****************************************************************************** -* TxPowerTrack_type0.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type0(void); - -/****************************************************************************** -* TxPowerTrack_type1.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type1(void); - -/****************************************************************************** -* TxPowerTrack_type10.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type10(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type10(void); - -/****************************************************************************** -* TxPowerTrack_type11.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type11(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type11(void); - -/****************************************************************************** -* TxPowerTrack_type12.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type12(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type12(void); - -/****************************************************************************** -* TxPowerTrack_type13.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type13(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type13(void); - -/****************************************************************************** -* TxPowerTrack_type14.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type14(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type14(void); - -/****************************************************************************** -* TxPowerTrack_type15.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type15(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type15(void); - -/****************************************************************************** -* TxPowerTrack_type16.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type16(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type16(void); - -/****************************************************************************** -* TxPowerTrack_Type17.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type17(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_Type17(void); - -/****************************************************************************** -* TxPowerTrack_type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type2(void); - -/****************************************************************************** -* TxPowerTrack_Type3_Type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_Type3_Type5(void); - -/****************************************************************************** -* TxPowerTrack_type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type4(void); - -/****************************************************************************** -* TxPowerTrack_type6.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type6(void); - -/****************************************************************************** -* TxPowerTrack_type7.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type7(void); - -/****************************************************************************** -* TxPowerTrack_type8.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type8(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type8(void); - -/****************************************************************************** -* TxPowerTrack_type9.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type9(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type9(void); - -/****************************************************************************** -* TXPWR_LMT.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT(void); - -/****************************************************************************** -* TXPWR_LMT_type12.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type12(void); - -/****************************************************************************** -* TXPWR_LMT_type15.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type15(void); - -/****************************************************************************** -* TXPWR_LMT_type16.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type16(void); - -/****************************************************************************** -* TXPWR_LMT_type17.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type17(void); - -/****************************************************************************** -* TXPWR_LMT_type2.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type2(void); - -/****************************************************************************** -* TXPWR_LMT_type3.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type3(void); - -/****************************************************************************** -* TXPWR_LMT_type4.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type4(void); - -/****************************************************************************** -* TXPWR_LMT_type5.TXT -******************************************************************************/ - -void -ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm -); -u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type5(void); - -#endif -#endif /* end of HWIMG_SUPPORT*/ - +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1 non coding style*/ +#if (RTL8822B_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8822B_H +#define __INC_MP_RF_HW_IMG_8822B_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_RadioA(void); + +/****************************************************************************** +* RadioB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_RadioB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_RadioB(void); + +/****************************************************************************** +* TxPowerTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack(void); + +/****************************************************************************** +* TxPowerTrack_type0.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type0(void); + +/****************************************************************************** +* TxPowerTrack_type1.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type1(void); + +/****************************************************************************** +* TxPowerTrack_type10.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type10(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type10(void); + +/****************************************************************************** +* TxPowerTrack_type11.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type11(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type11(void); + +/****************************************************************************** +* TxPowerTrack_type12.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type12(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type12(void); + +/****************************************************************************** +* TxPowerTrack_type13.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type13(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type13(void); + +/****************************************************************************** +* TxPowerTrack_type14.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type14(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type14(void); + +/****************************************************************************** +* TxPowerTrack_type15.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type15(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type15(void); + +/****************************************************************************** +* TxPowerTrack_type16.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type16(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type16(void); + +/****************************************************************************** +* TxPowerTrack_Type17.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type17(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_Type17(void); + +/****************************************************************************** +* TxPowerTrack_type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type2(void); + +/****************************************************************************** +* TxPowerTrack_Type3_Type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_Type3_Type5(void); + +/****************************************************************************** +* TxPowerTrack_type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type4(void); + +/****************************************************************************** +* TxPowerTrack_type6.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type6(void); + +/****************************************************************************** +* TxPowerTrack_type7.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type7(void); + +/****************************************************************************** +* TxPowerTrack_type8.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type8(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type8(void); + +/****************************************************************************** +* TxPowerTrack_type9.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type9(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type9(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT(void); + +/****************************************************************************** +* TXPWR_LMT_type12.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type12(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type12(void); + +/****************************************************************************** +* TXPWR_LMT_type15.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type15(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type15(void); + +/****************************************************************************** +* TXPWR_LMT_type16.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type16(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type16(void); + +/****************************************************************************** +* TXPWR_LMT_type17.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type17(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type17(void); + +/****************************************************************************** +* TXPWR_LMT_type2.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type2(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type2(void); + +/****************************************************************************** +* TXPWR_LMT_type3.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type3(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type3(void); + +/****************************************************************************** +* TXPWR_LMT_type4.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type4(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type4(void); + +/****************************************************************************** +* TXPWR_LMT_type5.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8822B_TXPWR_LMT_type5(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8822B_TXPWR_LMT_type5(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.c b/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.c index fff74ee64bb..405fbf05d4b 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.c @@ -1,487 +1,487 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - -BOOLEAN -GetMixModeTXAGCBBSWingOffset_8822b( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte TxPowerIndexOffest - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - - s1Byte TX_AGC_Index = 0; - u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { - TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else { - TX_AGC_Index = 0; - - if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index < BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); - - return TRUE; -} - - -VOID -ODM_TxPwrTrackSetPwr8822B( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxPowerIndex = 0; - u1Byte TxRate = 0xFF; - RT_STATUS status = RT_STATUS_SUCCESS; - - PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt = &(pRFCalibrateInfo->HALMAC_PWR_TRACKING_INFO); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - TxPowerIndex = PHY_GetTxPowerIndex(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("type=%d TxPowerIndex=%d pRFCalibrateInfo->Absolute_OFDMSwingIdx=%d pRFCalibrateInfo->DefaultOfdmIndex=%d RFPath=%d\n", Method, TxPowerIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->DefaultOfdmIndex, RFPath)); - - pPwr_tracking_opt->type = Method; - pPwr_tracking_opt->bbswing_index = pRFCalibrateInfo->DefaultOfdmIndex; - pPwr_tracking_opt->pwr_tracking_para[RFPath].enable = 1; - pPwr_tracking_opt->pwr_tracking_para[RFPath].tx_pwr_index = TxPowerIndex; - pPwr_tracking_opt->pwr_tracking_para[RFPath].pwr_tracking_offset_value = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - pPwr_tracking_opt->pwr_tracking_para[RFPath].tssi_value = 0; - - - if (RFPath == (MAX_PATH_NUM_8822B - 1)) { - status = HAL_MAC_Send_PowerTracking_Info(&GET_HAL_MAC_INFO(Adapter), pPwr_tracking_opt); - - if (status == RT_STATUS_SUCCESS) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path A 0xC94=0x%X 0xC1C=0x%X\n", - ODM_GetBBReg(pDM_Odm, 0xC94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), - ODM_GetBBReg(pDM_Odm, 0xC1C, 0xFFE00000) - )); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path B 0xE94=0x%X 0xE1C=0x%X\n", - ODM_GetBBReg(pDM_Odm, 0xE94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), - ODM_GetBBReg(pDM_Odm, 0xE1C, 0xFFE00000) - )); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Power Tracking to FW Fail ret code = %d\n", status)); - } - } - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte TxPowerIndexOffest = 0; - u1Byte TxPowerIndex = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->DefaultOfdmIndex=%d pRF->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->Absolute_OFDMSwingIdx=%d pRF->Remnant_OFDMSwingIdx=%d pRF->Absolute_CCKSwingIdx=%d pRF->Remnant_CCKSwingIdx=%d RFPath=%d\n", - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - TxPowerIndex = config_phydm_read_txagc_8822b(pDM_Odm, RFPath, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ - - if (TxPowerIndex >= 63) - TxPowerIndex = 63; - - TxPowerIndexOffest = 63 - TxPowerIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerIndex=%d TxPowerIndexOffest=%d RFPath=%d\n", TxPowerIndex, TxPowerIndexOffest, RFPath)); - - - if (Method == MIX_MODE) { - switch (RFPath) { - case ODM_RF_PATH_A: - GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), - ODM_GetBBReg(pDM_Odm, 0xc1c, 0xFFE00000), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); - break; - - case ODM_RF_PATH_B: - GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), - ODM_GetBBReg(pDM_Odm, 0xe1c, 0xFFE00000), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); - break; - - default: - break; - } - } - -#endif - -} - - -VOID -GetDeltaSwingTable_8822B( - PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B -#else - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - u1Byte channel = *(pDM_Odm->pChannel); -#else - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte channel = pHalData->CurrentChannel; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - *TemperatureUP_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; -#endif - - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - - if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } -} - - -VOID -phy_LCCalibrate_8822B( - PDM_ODM_T pDM_Odm - ) -{ - u4Byte LC_Cal = 0, cnt = 0, tmp0xc00, tmp0xe00, tmprf0xc4; - - tmp0xc00 = ODM_GetBBReg(pDM_Odm, 0xc00, 0xffffffff); - tmp0xe00 = ODM_GetBBReg(pDM_Odm, 0xe00, 0xffffffff); - tmprf0xc4 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask); - - ODM_SetBBReg(pDM_Odm, 0xc00, 0xffffffff, 0x4); - ODM_SetBBReg(pDM_Odm, 0xe00, 0xffffffff, 0x4); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0xfffff, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, 0xfffff, 0x10000); - /*backup RF0x18*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - /*disable RTK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask, 0x01402); - /*Start LCK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); - ODM_delay_ms(100); +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) + +BOOLEAN +GetMixModeTXAGCBBSWingOffset_8822b( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte TxPowerIndexOffest + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; + u1Byte BBSwingLowerBound = 0; + + s1Byte TX_AGC_Index = 0; + u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); + + if (TxPowerIndexOffest > 0XF) + TxPowerIndexOffest = 0XF; + + if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { + TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; + } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { + TX_AGC_Index = TxPowerIndexOffest; + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; + + if (TX_BBSwing_Index > BBSwingUpperBound) + TX_BBSwing_Index = BBSwingUpperBound; + } else { + TX_AGC_Index = 0; + + if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) + TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + else + TX_BBSwing_Index = BBSwingLowerBound; + + if (TX_BBSwing_Index < BBSwingLowerBound) + TX_BBSwing_Index = BBSwingLowerBound; + } + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", + RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); + + return TRUE; +} + + +VOID +ODM_TxPwrTrackSetPwr8822B( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte Channel = pHalData->CurrentChannel; + u1Byte BandWidth = pHalData->CurrentChannelBW; + u1Byte TxPowerIndex = 0; + u1Byte TxRate = 0xFF; + RT_STATUS status = RT_STATUS_SUCCESS; + + PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt = &(pRFCalibrateInfo->HALMAC_PWR_TRACKING_INFO); + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (pDM_Odm->number_linked_client != 0) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } else { /*force rate*/ + TxRate = (u1Byte) rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); + + TxPowerIndex = PHY_GetTxPowerIndex(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("type=%d TxPowerIndex=%d pRFCalibrateInfo->Absolute_OFDMSwingIdx=%d pRFCalibrateInfo->DefaultOfdmIndex=%d RFPath=%d\n", Method, TxPowerIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->DefaultOfdmIndex, RFPath)); + + pPwr_tracking_opt->type = Method; + pPwr_tracking_opt->bbswing_index = pRFCalibrateInfo->DefaultOfdmIndex; + pPwr_tracking_opt->pwr_tracking_para[RFPath].enable = 1; + pPwr_tracking_opt->pwr_tracking_para[RFPath].tx_pwr_index = TxPowerIndex; + pPwr_tracking_opt->pwr_tracking_para[RFPath].pwr_tracking_offset_value = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + pPwr_tracking_opt->pwr_tracking_para[RFPath].tssi_value = 0; + + + if (RFPath == (MAX_PATH_NUM_8822B - 1)) { + status = HAL_MAC_Send_PowerTracking_Info(&GET_HAL_MAC_INFO(Adapter), pPwr_tracking_opt); + + if (status == RT_STATUS_SUCCESS) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path A 0xC94=0x%X 0xC1C=0x%X\n", + ODM_GetBBReg(pDM_Odm, 0xC94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), + ODM_GetBBReg(pDM_Odm, 0xC1C, 0xFFE00000) + )); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path B 0xE94=0x%X 0xE1C=0x%X\n", + ODM_GetBBReg(pDM_Odm, 0xE94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), + ODM_GetBBReg(pDM_Odm, 0xE1C, 0xFFE00000) + )); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Power Tracking to FW Fail ret code = %d\n", status)); + } + } + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte TxPowerIndexOffest = 0; + u1Byte TxPowerIndex = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->DefaultOfdmIndex=%d pRF->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->Absolute_OFDMSwingIdx=%d pRF->Remnant_OFDMSwingIdx=%d pRF->Absolute_CCKSwingIdx=%d pRF->Remnant_CCKSwingIdx=%d RFPath=%d\n", + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); + + TxPowerIndex = config_phydm_read_txagc_8822b(pDM_Odm, RFPath, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ + + if (TxPowerIndex >= 63) + TxPowerIndex = 63; + + TxPowerIndexOffest = 63 - TxPowerIndex; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerIndex=%d TxPowerIndexOffest=%d RFPath=%d\n", TxPowerIndex, TxPowerIndexOffest, RFPath)); + + + if (Method == MIX_MODE) { + switch (RFPath) { + case ODM_RF_PATH_A: + GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d RFPath=%d\n", + ODM_GetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), + ODM_GetBBReg(pDM_Odm, 0xc1c, 0xFFE00000), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); + break; + + case ODM_RF_PATH_B: + GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); + ODM_SetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); + ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d RFPath=%d\n", + ODM_GetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), + ODM_GetBBReg(pDM_Odm, 0xe1c, 0xFFE00000), + pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); + break; + + default: + break; + } + } + +#endif + +} + + +VOID +GetDeltaSwingTable_8822B( + PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B, + pu1Byte *TemperatureUP_CCK_A, + pu1Byte *TemperatureDOWN_CCK_A, + pu1Byte *TemperatureUP_CCK_B, + pu1Byte *TemperatureDOWN_CCK_B +#else + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u1Byte channel = *(pDM_Odm->pChannel); +#else + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte channel = pHalData->CurrentChannel; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + *TemperatureUP_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; +#endif + + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + + if (36 <= channel && channel <= 64) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; + } else if (100 <= channel && channel <= 144) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; + } else if (149 <= channel && channel <= 177) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; + } +} + + +VOID +phy_LCCalibrate_8822B( + PDM_ODM_T pDM_Odm + ) +{ + u4Byte LC_Cal = 0, cnt = 0, tmp0xc00, tmp0xe00, tmprf0xc4; + + tmp0xc00 = ODM_GetBBReg(pDM_Odm, 0xc00, 0xffffffff); + tmp0xe00 = ODM_GetBBReg(pDM_Odm, 0xe00, 0xffffffff); + tmprf0xc4 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask); + + ODM_SetBBReg(pDM_Odm, 0xc00, 0xffffffff, 0x4); + ODM_SetBBReg(pDM_Odm, 0xe00, 0xffffffff, 0x4); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0xfffff, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, 0xfffff, 0x10000); + /*backup RF0x18*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + /*disable RTK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask, 0x01402); + /*Start LCK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); + ODM_delay_ms(100); for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - ODM_delay_ms(10); + if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + /*Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + /**restore*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask, tmprf0xc4); + ODM_SetBBReg(pDM_Odm, 0xc00, 0xffffffff, tmp0xc00); + ODM_SetBBReg(pDM_Odm, 0xe00, 0xffffffff, tmp0xe00); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x3ffff); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n")); +} + + + +VOID +PHY_LCCalibrate_8822B( + PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u8Byte StartTime; + u8Byte ProgressingTime; + + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif +#endif + + if (bStartContTx || bSingleTone || bCarrierSuppression) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); + return; + } + + StartTime = ODM_GetCurrentTime(pDM_Odm); + phy_LCCalibrate_8822B(pDM_Odm); + ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK ProgressingTime = %lld\n", ProgressingTime)); +} + + + +void ConfigureTxpowerTrack_8822B( + PTXPWRTRACK_CFG pConfig + ) +{ + pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; + pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->Threshold_DPK = DPK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8822B; + pConfig->RfPathCount = MAX_PATH_NUM_8822B; + pConfig->ThermalRegAddr = RF_T_METER_8822B; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8822B; + pConfig->DoIQK = DoIQK_8822B; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8822B; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + pConfig->GetDeltaAllSwingTable = GetDeltaSwingTable_8822B; +#else + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8822B; +#endif +} + + +VOID PHY_SetRFPathSwitch_8822B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + /*BY SY Request */ + ODM_SetBBReg(pDM_Odm, 0x4C, (BIT24 | BIT23), 0x2); + ODM_SetBBReg(pDM_Odm, 0x974, 0xff, 0xff); + + /*ODM_SetBBReg(pDM_Odm, 0x1991, 0x3, 0x0);*/ + ODM_SetBBReg(pDM_Odm, 0x1990, (BIT9 | BIT8), 0x0); + + /*ODM_SetBBReg(pDM_Odm, 0xCBE, 0x8, 0x0);*/ + ODM_SetBBReg(pDM_Odm, 0xCBC, BIT19, 0x0); + + ODM_SetBBReg(pDM_Odm, 0xCB4, 0xff, 0x77); + + ODM_SetBBReg(pDM_Odm, 0x70, bMaskByte3, 0x0e); + ODM_SetBBReg(pDM_Odm, 0x1704, bMaskDWord, 0x0000ff00); + ODM_SetBBReg(pDM_Odm, 0x1700, bMaskDWord, 0xc00f0038); + + if (bMain) { + /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x2); WiFi */ + ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x2); /*WiFi */ + } else { + /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x1); BT*/ + ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x1); /*BT*/ } - /*Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); - /**restore*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xc4, bRFRegOffsetMask, tmprf0xc4); - ODM_SetBBReg(pDM_Odm, 0xc00, 0xffffffff, tmp0xc00); - ODM_SetBBReg(pDM_Odm, 0xe00, 0xffffffff, tmp0xe00); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x3ffff); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n")); -} - - - -VOID -PHY_LCCalibrate_8822B( - PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u8Byte StartTime; - u8Byte ProgressingTime; - - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif -#endif - - if (bStartContTx || bSingleTone || bCarrierSuppression) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); - return; - } - - StartTime = ODM_GetCurrentTime(pDM_Odm); - phy_LCCalibrate_8822B(pDM_Odm); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK ProgressingTime = %lld\n", ProgressingTime)); -} - - - -void ConfigureTxpowerTrack_8822B( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->Threshold_DPK = DPK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8822B; - pConfig->RfPathCount = MAX_PATH_NUM_8822B; - pConfig->ThermalRegAddr = RF_T_METER_8822B; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8822B; - pConfig->DoIQK = DoIQK_8822B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8822B; - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pConfig->GetDeltaAllSwingTable = GetDeltaSwingTable_8822B; -#else - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8822B; -#endif -} - - -VOID PHY_SetRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - /*BY SY Request */ - ODM_SetBBReg(pDM_Odm, 0x4C, (BIT24 | BIT23), 0x2); - ODM_SetBBReg(pDM_Odm, 0x974, 0xff, 0xff); - - /*ODM_SetBBReg(pDM_Odm, 0x1991, 0x3, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT9 | BIT8), 0x0); - - /*ODM_SetBBReg(pDM_Odm, 0xCBE, 0x8, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0xCBC, BIT19, 0x0); - - ODM_SetBBReg(pDM_Odm, 0xCB4, 0xff, 0x77); - - ODM_SetBBReg(pDM_Odm, 0x70, bMaskByte3, 0x0e); - ODM_SetBBReg(pDM_Odm, 0x1704, bMaskDWord, 0x0000ff00); - ODM_SetBBReg(pDM_Odm, 0x1700, bMaskDWord, 0xc00f0038); - - if (bMain) { - /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x2); WiFi */ - ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x2); /*WiFi */ - } else { - /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x1); BT*/ - ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x1); /*BT*/ - } -} - -BOOLEAN -phy_QueryRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm -#else - PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - if (ODM_GetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8)) == 0x2) /*WiFi */ - return TRUE; - else - return FALSE; -} - - -BOOLEAN PHY_QueryRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm -#else - PADAPTER pAdapter -#endif - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8822B(pDM_Odm); -#else - return phy_QueryRFPathSwitch_8822B(pAdapter); -#endif -} - - -#endif /* (RTL8822B_SUPPORT == 0)*/ +} + +BOOLEAN +phy_QueryRFPathSwitch_8822B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PDM_ODM_T pDM_Odm +#else + PADAPTER pAdapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif +#endif + + if (ODM_GetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8)) == 0x2) /*WiFi */ + return TRUE; + else + return FALSE; +} + + +BOOLEAN PHY_QueryRFPathSwitch_8822B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PDM_ODM_T pDM_Odm +#else + PADAPTER pAdapter +#endif + ) +{ + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8822B(pDM_Odm); +#else + return phy_QueryRFPathSwitch_8822B(pAdapter); +#endif +} + + +#endif /* (RTL8822B_SUPPORT == 0)*/ diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.h b/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.h index 5db26b84f10..97162dd28f8 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/halphyrf_8822b.h @@ -1,76 +1,76 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8822B_H__ -#define __HAL_PHY_RF_8822B_H__ - -#define AVG_THERMAL_NUM_8822B 4 -#define RF_T_METER_8822B 0x42 - -void ConfigureTxpowerTrack_8822B( - PTXPWRTRACK_CFG pConfig - ); - -VOID -ODM_TxPwrTrackSetPwr8822B( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -GetDeltaSwingTable_8822B( - PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B -#else - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -#endif - ); - -VOID -PHY_LCCalibrate_8822B( - PVOID pDM_VOID - ); - - - -VOID PHY_SetRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - -#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8822B_H__ +#define __HAL_PHY_RF_8822B_H__ + +#define AVG_THERMAL_NUM_8822B 4 +#define RF_T_METER_8822B 0x42 + +void ConfigureTxpowerTrack_8822B( + PTXPWRTRACK_CFG pConfig + ); + +VOID +ODM_TxPwrTrackSetPwr8822B( + PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +GetDeltaSwingTable_8822B( + PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B, + pu1Byte *TemperatureUP_CCK_A, + pu1Byte *TemperatureDOWN_CCK_A, + pu1Byte *TemperatureUP_CCK_B, + pu1Byte *TemperatureDOWN_CCK_B +#else + pu1Byte *TemperatureUP_A, + pu1Byte *TemperatureDOWN_A, + pu1Byte *TemperatureUP_B, + pu1Byte *TemperatureDOWN_B +#endif + ); + +VOID +PHY_LCCalibrate_8822B( + PVOID pDM_VOID + ); + + + +VOID PHY_SetRFPathSwitch_8822B( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain + ); + +#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.c b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.c index ad8f6f84869..0e17830ba00 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.c @@ -1,1994 +1,1994 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - -/* ======================================================================== */ -/* These following functions can be used for PHY DM only*/ - -ODM_BW_E bw_8822b; -u1Byte central_ch_8822b; - -#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) - u32 cca_ifem_bcut[3][4] = { - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ - {0x87766441, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ - }; - u32 cca_efem_bcut[3][4] = { - {0x75B76010, 0x75B76010, 0x75B76010, 0x75B75010}, /*Reg82C*/ - {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ - {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ - }; -#endif - -u32 cca_ifem_ccut[3][4] = { - {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ - {0x79a0ea2a, 0x79A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ - {0x87765541, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ -}; -u32 cca_efem_ccut[3][4] = { - {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ - {0x79A0EA28, 0x79A0EA2C, 0x79A0EA28, 0x79a0ea2a}, /*Reg830*/ - {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ -}; -u32 cca_ifem_ccut_rfetype[3][4] = { - {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ - {0x79a0ea2a, 0x97A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ - {0x87765541, 0x86666341, 0x87765561, 0x86666361} /*Reg838*/ -}; - -void -phydm_igi_toggle_8822b( - IN PDM_ODM_T pDM_Odm -) -{ - u32 igi = 0x20; - - igi = ODM_GetBBReg(pDM_Odm, 0xc50, 0x7f); - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, (igi - 2)); - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, igi); - ODM_SetBBReg(pDM_Odm, 0xe50, 0x7f, (igi - 2)); - ODM_SetBBReg(pDM_Odm, 0xe50, 0x7f, igi); -} - -BOOLEAN -phydm_rfe_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte channel - ) -{ - if (pDM_Odm->RFEType == 4) { - - /*TRSW = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/ - /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/ - /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */ - /*ODM_SetBBReg(pDM_Odm, 0x804, (BIT1|BIT0), 0x0);*/ - /* Default setting is in PHY parameters */ - - if (channel <= 14) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x2); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x2); - - /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { - /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf050); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf050); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { - /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf055); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf055); - } else { - /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf550); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf550); - } - - } else if (channel > 35) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); - - /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { - /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { - /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); - } else { - /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); - } - } else - return FALSE; - - - } - else if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9) || (pDM_Odm->RFEType == 11)) { - /* efem */ - if (((pDM_Odm->CutVersion == ODM_CUT_A) || (pDM_Odm->CutVersion == ODM_CUT_B)) && (pDM_Odm->RFEType < 2)) { - if (channel <= 14) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); - } else if (channel > 35) { - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); - } else - return FALSE; - - /* delay 400ns for PAPE */ - ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); - - /* antenna switch table */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555); - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__)); - } else { - /*After B-Cut*/ - if (channel <= 14) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x705770); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x705770); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xcb8, BIT4, 0); - ODM_SetBBReg(pDM_Odm, 0xeb8, BIT4, 0); - } else if (channel > 35) { - /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x177517); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x177517); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xcb8, BIT5, 0); - ODM_SetBBReg(pDM_Odm, 0xeb8, BIT5, 0); - } else - return FALSE; - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); - - /* delay 400ns for PAPE */ - /* ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); */ - - /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { - /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { - /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); - } else { - /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); - } - } - } - else if ((pDM_Odm->RFEType == 0) || (pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8) || (pDM_Odm->RFEType == 10) || (pDM_Odm->RFEType == 12) || (pDM_Odm->RFEType == 13) || (pDM_Odm->RFEType == 14)) { - /* iFEM */ - if (channel <= 14) { - /* signal source */ - /*ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x705770); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x705770); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xcb8, BIT4, 0); - ODM_SetBBReg(pDM_Odm, 0xeb8, BIT4, 0);*/ - - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); - - } else if (channel > 35) { - /* signal source */ - /*ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x177517); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x177517); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xcb8, BIT5, 1); - ODM_SetBBReg(pDM_Odm, 0xeb8, BIT5, 1);*/ - - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); - } else - return FALSE; - - /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); - - /* antenna switch table */ - if (channel <= 14) { - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { - /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { - /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); - } else { - /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); - } - } else if (channel > 35) { - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa5a5); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa5a5); - } - } - - /* chip top mux */ - ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0); - ODM_SetBBReg(pDM_Odm, 0x40, BIT3, 0x1); - - /* from s0 or s1 */ - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30); - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3); - - /* input or output */ - ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f); - ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, TxPath 0x%x, RxPath 0x%x)\n", __func__, channel, pDM_Odm->TXAntStatus, pDM_Odm->RXAntStatus)); - - return TRUE; -} - -u8 -phydm_is_dfs_channel(u8 channel_num) -{ - if(channel_num >= 52 && channel_num <= 140) - return 1; - else - return 0; -} - -VOID -phydm_ccapar_by_rfe_8822b( - IN PDM_ODM_T pDM_Odm - ) -{ - u32 cca_ifem[3][4], cca_efem[3][4]; - u8 col; - u32 reg82c, reg830, reg838; - BOOLEAN is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; - -#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) - if (pDM_Odm->CutVersion == ODM_CUT_B) { - ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_bcut, 12 * 4); - ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_bcut, 12 * 4); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__)); - } else -#endif - { - ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_ccut, 12 * 4); - if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) { - ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_rfetype, 12 * 4); - is_rfe_type = true; - } else - ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut, 12 * 4); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__)); - } - - if (central_ch_8822b <= 14) { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 0; /*1R 2G*/ - else - col = 1; /*2R 2G*/ - } else { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 2; /*1R 5G*/ - else - col = 3; /*2R 5G*/ - } - - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 4) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 11)) { - /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7 & RFE type 11*/ - reg82c = cca_efem[0][col]; - reg830 = cca_efem[1][col]; - reg838 = cca_efem[2][col]; - is_efem_cca = true; - } else if ((pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 9)) { - /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */ - if (central_ch_8822b <= 14) { - reg82c = cca_ifem[0][col]; - reg830 = cca_ifem[1][col]; - reg838 = cca_ifem[2][col]; - is_ifem_cca = true; - } else { - reg82c = cca_efem[0][col]; - reg830 = cca_efem[1][col]; - reg838 = cca_efem[2][col]; - is_efem_cca = true; - } - } else { - /* iFEM =>RFEtype 3 & RFE type 5 & RFE type 0 & RFE type 8 & RFE type 10 & RFE type 12 & RFE type 13*/ - reg82c = cca_ifem[0][col]; - reg830 = cca_ifem[1][col]; - reg838 = cca_ifem[2][col]; - is_ifem_cca = true; - } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - - if (is_ifem_cca == true) - if (((pDM_Odm->CutVersion == ODM_CUT_B) && (col == 1 || col == 3) && (bw_8822b == ODM_BW40M)) || - ((is_rfe_type == false) && (col == 3) && (bw_8822b == ODM_BW40M)) || - ((pDM_Odm->RFEType == 5) && (col == 3))) - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, 0x79a0ea28); - else - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); - else - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); - - ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838); - - if (!(pDM_Odm->CutVersion == ODM_CUT_B)) - ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, 0x9194b2b9); - - /* CCA parameters adjust for 20MHz on DFS channel */ - if ((*pDM_Odm->pBandWidth == ODM_BW20M) && (((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 144)))) - ODM_SetBBReg(pDM_Odm, 0x838, 0xf0, 0x4); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), col = %d\n", - __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, col)); -} - -VOID -phydm_ccapar_by_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - u4Byte reg82c; - - - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; - - /* A-cut */ - reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); - - if (bandwidth == ODM_BW20M) { - /* 82c[15:12] = 4 */ - /* 82c[27:24] = 6 */ - - reg82c &= (~(0x0f00f000)); - reg82c |= ((0x4) << 12); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW40M) { - /* 82c[19:16] = 9 */ - /* 82c[27:24] = 6 */ - - reg82c &= (~(0x0f0f0000)); - reg82c |= ((0x9) << 16); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW80M) { - /* 82c[15:12] 7 */ - /* 82c[19:16] b */ - /* 82c[23:20] d */ - /* 82c[27:24] 3 */ - - reg82c &= (~(0x0ffff000)); - reg82c |= ((0xdb7) << 12); - reg82c |= ((0x3) << 24); - } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByBw_8822b(): Update CCA parameters for Acut\n")); - -} - -VOID -phydm_ccapar_by_rxpath_8822b( - IN PDM_ODM_T pDM_Odm - ) -{ - - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; - - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) { - /* 838[7:4] = 8 */ - /* 838[11:8] = 7 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 7 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678); - } else { - /* 838[7:4] = 3 */ - /* 838[11:8] = 3 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 6 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633); - } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByRxPath_8822b(): Update CCA parameters for Acut\n")); - -} - -VOID -phydm_rxdfirpar_by_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - if (bandwidth == ODM_BW40M) { - /* RX DFIR for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x0); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); - } else if (bandwidth == ODM_BW80M) { - /* RX DFIR for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); - } else { - /* RX DFIR for BW20, BW10 and BW5*/ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x1); - } -} - -BOOLEAN -phydm_write_txagc_1byte_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc), i; - u1Byte rate_offset = (HwRate & 0x3); - u4Byte txagc_content = 0x0; - - /* For debug command only!!!! */ - - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", Path)); - return FALSE; - } - - /* For HW limitation, We can't write TXAGC once a byte. */ - for (i = 0; i < 4; i++) { - if (i != rate_offset) - txagc_content = txagc_content|(config_phydm_read_txagc_8822b(pDM_Odm, Path, rate_idx + i) << (i << 3)); - else - txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3)); - } - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; -} - -VOID -phydm_init_hw_info_by_rfe_type_8822b( - IN PDM_ODM_T pDM_Odm -) -{ - u2Byte mask_path_a = 0x0303; - u2Byte mask_path_b = 0x0c0c; - /*u2Byte mask_path_c = 0x3030;*/ - /*u2Byte mask_path_d = 0xc0c0;*/ - - pDM_Odm->bInitHwInfoByRfe = FALSE; - /* 1R for path-b always used in AP platform */ - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, TRUE); - #endif - - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); - - if (pDM_Odm->RFEType == 6) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b))); - } else if (pDM_Odm->RFEType == 7) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a|mask_path_b))); - } else { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - } - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 2) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 9) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } else if (pDM_Odm->RFEType == 3) { - /* RFE type 3: 8822BS\8822BU TFBGA iFEM */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } else if (pDM_Odm->RFEType == 5) { - /* RFE type 5: 8822BE TFBGA iFEM */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_SLIM); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } else if (pDM_Odm->RFEType == 12) { - /* RFE type 12: QFN iFEM */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, false); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, false); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, false); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (pDM_Odm->RFEType == 4) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 11) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 8) { - /* RFE Type 8: TFBGA iFEM AP */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } else if (pDM_Odm->RFEType == 10) { - /* RFE Type 10: QFN iFEM AP PCIE */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_TRSW); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - - } else { - /* RFE Type 0 & 13: QFN iFEM */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } - - pDM_Odm->bInitHwInfoByRfe = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): RFE type (%d), Board type (0x%x), Package type (%d)\n", pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA)); -} - -s4Byte -phydm_get_condition_number_8822B( - IN PDM_ODM_T pDM_Odm -) -{ - s4Byte ret_val; - - ODM_SetBBReg( pDM_Odm, 0x1988, BIT22, 0x1); - ret_val = (s4Byte)ODM_GetBBReg(pDM_Odm, 0xf84, (BIT17|BIT16|bMaskLWord)); - - if (bw_8822b == 0) { - ret_val = ret_val << (8 - 4); - ret_val = ret_val / 234; - } else if (bw_8822b == 1) { - ret_val = ret_val << (7 - 4); - ret_val = ret_val / 108; - } else if (bw_8822b == 2) { - ret_val = ret_val << (6 - 4); - ret_val = ret_val / 52; - } - - return ret_val; -} - - -/* ======================================================================== */ - -/* ======================================================================== */ -/* These following functions can be used by driver*/ - -u4Byte -config_phydm_read_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) -{ - u4Byte Readback_Value, Direct_Addr; - u4Byte offset_readRF[2] = {0x2800, 0x2c00}; - u4Byte power_RF[2] = {0x1c, 0xec}; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); - return INVALID_RF_DATA; - } - - /* Error handling. Check if RF power is enable or not */ - /* 0xffffffff means RF power is disable */ - if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): Read fail, RF is disabled\n")); - return INVALID_RF_DATA; - } - - /* Calculate offset */ - RegAddr &= 0xff; - Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); - - /* RF register only has 20bits */ - BitMask &= bRFRegOffsetMask; - - /* Read RF register directly */ - Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - RFPath, RegAddr, Readback_Value, BitMask)); - return Readback_Value; -} - -BOOLEAN -config_phydm_write_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) -{ - u4Byte DataAndAddr = 0, Data_original = 0; - u4Byte offset_writeRF[2] = {0xc90, 0xe90}; - u4Byte power_RF[2] = {0x1c, 0xec}; - u1Byte BitShift; - - /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); - return FALSE; - } - - /* Read RF register content first */ - RegAddr &= 0xff; - BitMask = BitMask & bRFRegOffsetMask; - - if (BitMask != bRFRegOffsetMask) { - Data_original = config_phydm_read_rf_reg_8822b(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); - - /* Error handling. RF is disabled */ - if (config_phydm_read_rf_check_8822b(Data_original) == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n")); - return FALSE; - } - - /* check bit mask */ - if (BitMask != 0xfffff) { - for (BitShift = 0; BitShift <= 19; BitShift++) { - if (((BitMask >> BitShift) & 0x1) == 1) - break; - } - Data = ((Data_original) & (~BitMask)) | ((Data << BitShift) & (BitMask)); - } - } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disabled\n")); - return FALSE; - } - - /* Put write addr in [27:20] and write data in [19:00] */ - DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; - - /* Write Operation */ - ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - RFPath, RegAddr, Data, Data_original, BitMask)); - - ODM_delay_us(2); - return TRUE; -} - -BOOLEAN -config_phydm_write_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc); - - /* Input need to be HW rate index, not driver rate index!!!! */ - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n")); - return TRUE; - } - - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", Path)); - return FALSE; - } - - /* driver need to construct a 4-byte power index */ - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; -} - -u1Byte -config_phydm_read_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) -{ - u1Byte readBack_data; - - /* Input need to be HW rate index, not driver rate index!!!! */ - - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", Path)); - return INVALID_TXAGC_DATA; - } - - /* Disable TX AGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */ - - /* Set data rate index (bit0~6) and path index (bit7) */ - ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7))); - - /* Enable TXAGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1); - - /* Read TX AGC report */ - readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000); - - /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data)); - return readBack_data; -} - -VOID -phydm_dynamic_spur_det_elimitor( - IN PDM_ODM_T pDM_Odm -) -{ - u32 freq_2g[number_of_2g_freq_pt] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67, 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFF66, 0xFF26, 0xFCE7}; - u32 freq_5g[number_of_5g_freq_pt] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41, 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42}; - u32 freq_2g_n1[number_of_2g_freq_pt] = {0}, freq_2g_p1[number_of_2g_freq_pt] = {0}; - u32 freq_5g_n1[number_of_5g_freq_pt] = {0}, freq_5g_p1[number_of_5g_freq_pt] = {0}; - u32 freq_pt_2g_final = 0, freq_pt_5g_final = 0, freq_pt_2g_b_final = 0, freq_pt_5g_b_final = 0; - u32 max_ret_psd_final = 0, max_ret_psd_b_final = 0; - u32 max_ret_psd_2nd[number_of_sample] = {0}, max_ret_psd_b_2nd[number_of_sample] = {0}; - u32 psd_set[number_of_psd_value] = {0}, psd_set_B[number_of_psd_value] = {0}; - u32 rank_psd_index_in[number_of_psd_value] = {0}, rank_sample_index_in[number_of_sample] = {0}; - u32 rank_psd_index_out[number_of_psd_value] = {0}; - u32 rank_sample_index_out[number_of_sample] = {0}; - u32 reg_910_15_12 = 0; - u8 j = 0, k = 0, threshold_nbi = 0x8D, threshold_csi = 0x8D; - u8 idx = 0, set_result_nbi = SET_NO_NEED, set_result_csi = SET_NO_NEED; - BOOLEAN s_dopsd = false, s_donbi_a = false, s_docsi = false, s_donbi_b = false; - - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_PSDTOOL)) { - ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic Spur Detection and Eliminator\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("Dynamic Spur Detection and Eliminator is ON\n")); - - /* Reset NBI/CSI everytime after changing channel/BW/band */ - ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x874, BIT(0), 0x0); - - ODM_SetBBReg(pDM_Odm, 0x87c, BIT(13), 0x0); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT(28), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT(28), 0x0); - - /* 2G Channel Setting > 20M: 5, 6, 7, 8, 13; 40M: 3~11 */ - if ((*pDM_Odm->pChannel >= 1) && (*pDM_Odm->pChannel <= 14)) { - if (*pDM_Odm->pBandWidth == ODM_BW20M) { - - if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) - idx = *pDM_Odm->pChannel - 5; - else if (*pDM_Odm->pChannel == 13) - idx = 4; - else - idx = 16; - } else { - - if (*pDM_Odm->pChannel >= 3 && *pDM_Odm->pChannel <= 11) - idx = *pDM_Odm->pChannel + 2; - else - idx = 16; - } - } else { /* 5G Channel Setting > 20M: 153, 161; 40M: 54, 118, 151, 159; 80M: 58, 122, 155, 155 */ - switch (*pDM_Odm->pChannel) { - case 153: - idx = 0; - break; - case 161: - idx = 1; - break; - case 54: - idx = 2; - break; - case 118: - idx = 3; - break; - case 151: - idx = 4; - break; - case 159: - idx = 5; - break; - case 58: - idx = 6; - break; - case 122: - idx = 7; - break; - case 155: - idx = 8; - break; - default: - idx = 16; - break; - } - } - - if (idx <= 16) { - s_dopsd = true; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Point] Idx Is Exceed, Not Support Dynamic Spur Detection and Eliminator\n")); - return; - } - - ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] idx = %d, BW = %d, Channel = %d\n", __func__, idx, *pDM_Odm->pBandWidth, *pDM_Odm->pChannel)); - - for (k = 0; k < number_of_2g_freq_pt; k++) { - freq_2g_n1[k] = freq_2g[k] - 1; - freq_2g_p1[k] = freq_2g[k] + 1; - } - - for (k = 0; k < number_of_5g_freq_pt; k++) { - freq_5g_n1[k] = freq_5g[k] - 1; - freq_5g_p1[k] = freq_5g[k] + 1; - } - - if ((s_dopsd == TRUE) && (idx <= 13)) { - for (k = 0; k < number_of_sample; k++) { - if (k == 0) { - freq_pt_2g_final = freq_2g_n1[idx]; - freq_pt_5g_final = freq_5g_n1[idx]; - freq_pt_2g_b_final = freq_2g_n1[idx] | BIT(16); - freq_pt_5g_b_final = freq_5g_n1[idx] | BIT(16); - } else if (k == 1) { - freq_pt_2g_final = freq_2g[idx]; - freq_pt_5g_final = freq_5g[idx]; - freq_pt_2g_b_final = freq_2g[idx] | BIT(16); - freq_pt_5g_b_final = freq_5g[idx] | BIT(16); - } else if (k == 2) { - freq_pt_2g_final = freq_2g_p1[idx]; - freq_pt_5g_final = freq_5g_p1[idx]; - freq_pt_2g_b_final = freq_2g_p1[idx] | BIT(16); - freq_pt_5g_b_final = freq_5g_p1[idx] | BIT(16); - } - - for (j = 0; j < number_of_psd_value; j++) { - ODM_SetBBReg(pDM_Odm, 0xc00, bMaskByte0, 0x4);/* disable 3-wire, path-A */ - ODM_SetBBReg(pDM_Odm, 0xe00, bMaskByte0, 0x4);/* disable 3-wire, path-B */ - reg_910_15_12 = ODM_GetBBReg(pDM_Odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12)); - - if (pDM_Odm->RXAntStatus & ODM_RF_A) { - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((ODM_RF_A)<<4) | ODM_RF_A));/*path-A*/ - - if ((*pDM_Odm->pChannel >= 1) && (*pDM_Odm->pChannel <= 14)) - ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_2g_final);/* Start PSD */ - else - ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_5g_final);/* Start PSD */ - - ODM_delay_us(500); - - psd_set[j] = ODM_GetBBReg(pDM_Odm, 0xf44, bMaskLWord); - - ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0x0);/* turn off PSD */ - } - - if (pDM_Odm->RXAntStatus & ODM_RF_B) { - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((ODM_RF_B)<<4) | ODM_RF_B));/*path-B*/ - - if ((*pDM_Odm->pChannel > 0) && (*pDM_Odm->pChannel <= 14)) - ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_2g_b_final);/* Start PSD */ - else - ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_5g_b_final);/* Start PSD */ - - ODM_delay_us(500); - - psd_set_B[j] = ODM_GetBBReg(pDM_Odm, 0xf44, bMaskLWord); - - ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0x0);/* turn off PSD */ - } - - ODM_SetBBReg(pDM_Odm, 0xc00, bMaskByte0, 0x7);/*eanble 3-wire*/ - ODM_SetBBReg(pDM_Odm, 0xe00, bMaskByte0, 0x7); - ODM_SetBBReg(pDM_Odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12), reg_910_15_12); - - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((pDM_Odm->RXAntStatus)<<4) | pDM_Odm->RXAntStatus)); - - /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - phydm_igi_toggle_8822b(pDM_Odm); - - } - if (pDM_Odm->RXAntStatus & ODM_RF_A) { - phydm_seq_sorting(pDM_Odm, psd_set, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); - max_ret_psd_2nd[k] = psd_set[0]; - } - if (pDM_Odm->RXAntStatus & ODM_RF_B) { - phydm_seq_sorting(pDM_Odm, psd_set_B, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); - max_ret_psd_b_2nd[k] = psd_set_B[0]; - } - } - - if (pDM_Odm->RXAntStatus & ODM_RF_A) { - phydm_seq_sorting(pDM_Odm, max_ret_psd_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); - max_ret_psd_final = max_ret_psd_2nd[0]; - - if (max_ret_psd_final >= threshold_nbi) - s_donbi_a = true; - else - s_donbi_a = false; - } - if (pDM_Odm->RXAntStatus & ODM_RF_B) { - phydm_seq_sorting(pDM_Odm, max_ret_psd_b_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); - max_ret_psd_b_final = max_ret_psd_b_2nd[0]; - - if (max_ret_psd_b_final >= threshold_nbi) - s_donbi_b = true; - else - s_donbi_b = false; - } - - ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] max_ret_psd_final = %d, max_ret_psd_b_final = %d\n", __func__, max_ret_psd_final, max_ret_psd_b_final)); - - if ((max_ret_psd_final >= threshold_csi) || (max_ret_psd_b_final >= threshold_csi)) - s_docsi = true; - else - s_docsi = false; - - } - - if (s_donbi_a == true || s_donbi_b == true) { - if (*pDM_Odm->pBandWidth == ODM_BW20M) { - if (*pDM_Odm->pChannel == 153) - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 5760, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 161) - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 5800, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 2440, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 13) - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 2480, PHYDM_DONT_CARE); - else - set_result_nbi = SET_NO_NEED; - } else if (*pDM_Odm->pBandWidth == ODM_BW40M) { - if (*pDM_Odm->pChannel == 54) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5280, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 118) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5600, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 151) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5760, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 159) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5800, PHYDM_DONT_CARE); - /* 2.4G */ - } else if ((*pDM_Odm->pChannel >= 4) && (*pDM_Odm->pChannel <= 6)) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 11) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); - } else - set_result_nbi = SET_NO_NEED; - } else if (*pDM_Odm->pBandWidth == ODM_BW80M) { - if (*pDM_Odm->pChannel == 58) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5280, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 122) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5600, PHYDM_DONT_CARE); - } else if (*pDM_Odm->pChannel == 155) { - set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5760, PHYDM_DONT_CARE); - } else - set_result_nbi = SET_NO_NEED; - } else - set_result_nbi = SET_NO_NEED; - } - - if (s_docsi == true) { - if (*pDM_Odm->pBandWidth == ODM_BW20M) { - if (*pDM_Odm->pChannel == 153) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 5760, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 161) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 5800, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 2440, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 13) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 2480, PHYDM_DONT_CARE); - else - set_result_csi = SET_NO_NEED; - } else if (*pDM_Odm->pBandWidth == ODM_BW40M) { - if (*pDM_Odm->pChannel == 159) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 5800, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 151) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 5760, PHYDM_DONT_CARE); - else if ((*pDM_Odm->pChannel >= 3) && (*pDM_Odm->pChannel <= 10)) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 11) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); - else - set_result_csi = SET_NO_NEED; - } else if (*pDM_Odm->pBandWidth == ODM_BW80M) { - if (*pDM_Odm->pChannel == 58) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5280, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 122) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5600, PHYDM_DONT_CARE); - else if (*pDM_Odm->pChannel == 155) - set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5760, PHYDM_DONT_CARE); - else - set_result_csi = SET_NO_NEED; - } else - set_result_csi = SET_NO_NEED; - } - -} - -BOOLEAN -config_phydm_switch_band_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) -{ - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; - u4Byte reg_8; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n")); - return TRUE; - } - - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); - - if (central_ch <= 14) { - /* 2.4G */ - - /* Enable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1); - - /* Disable MAC CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0); - - /* Disable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0); - - /*CCA Mask*/ - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ - - /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); - - /* RxHP dynamic control */ - if ((pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); - } - - /* QFN eFEM RxHP are always low at 2G */ - reg_8 = ODM_GetBBReg(pDM_Odm, 0x19a8, BIT31); - - /* SoML on */ - if (reg_8 == 0x1) { - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); - if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8)) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); - } else { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } - } - - /* SoML off */ - if (reg_8 == 0x0) { - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9)) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); - } - } - - } else if (central_ch > 35) { - /* 5G */ - - /* Enable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1); - - /* Enable CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1); - - /* Disable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0); - - /*CCA Mask*/ - if ((!pDM_Odm->WIFITest==1) || ((DM_ODM_SUPPORT_TYPE == ODM_AP) && (pDM_Odm->WIFITest))) - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ - else - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ - - /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); - rf_reg18 = (rf_reg18|BIT8|BIT16); - - /* RxHP dynamic control */ - reg_8 = ODM_GetBBReg(pDM_Odm, 0x19a8, BIT31); - - /* SoML on */ - if (reg_8 == 0x1) { - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } - - /* SoML off */ - if (reg_8 == 0x0) { - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9)) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); - } - } - - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch)); - return FALSE; - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); - - if (phydm_rfe_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch)); - return FALSE; - } - - /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - phydm_dynamic_spur_det_elimitor(pDM_Odm); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_agc_tab_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN bool is_switch_sat_tab - ) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - bool is_success = TRUE; - - if (central_ch <= 14) { - pDM_DigTable->agcTableIdx = 0x0; - - } else if (central_ch > 35) { - if ((central_ch >= 36) && (central_ch <= 64)) { - pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x5 : 0x1; - } else if ((central_ch >= 100) && (central_ch <= 144)) { - pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x6 : 0x2; - } else if (central_ch >= 149) { - pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x7 : 0x3; - } else { - is_success = FALSE; - } - } else { - is_success = FALSE; - } - - if (is_success) - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, pDM_DigTable->agcTableIdx); - else - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Fail to switch agc table (ch: %d)\n", __FUNCTION__, central_ch)); - - return is_success; - -} - -BOOLEAN -config_phydm_switch_channel_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) -{ - u4Byte rf_reg18 = 0, rf_regB8 = 0, rf_regBE = 0xff; - BOOLEAN rf_reg_status = TRUE; - u1Byte low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; - u1Byte middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7}; - u1Byte high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n")); - return TRUE; - } - - central_ch_8822b = central_ch; - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); - rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); - - if (pDM_Odm->CutVersion == ODM_CUT_A) { - rf_regB8 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_regB8); - } - - if(config_phydm_switch_agc_tab_8822b(pDM_Odm, central_ch, DEFAULT_AGC_TABLE) == FALSE) - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Fail to switch channel (AGC) (ch: %d)\n", __FUNCTION__, central_ch)); - - /* Switch band and channel */ - if (central_ch <= 14) { - /* 2.4G */ - - /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18|central_ch); - - /* 2. AGC table selection, removed, use API */ - -/* - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x0); - pDM_DigTable->agcTableIdx = 0x0; -*/ - /* 3. Set central frequency for clock offset tracking */ - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a); - - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_regB8 = rf_regB8 | BIT19; - - /* CCK TX filter parameters */ - if (central_ch == 14) { - ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x00006577); - ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x0000); - } else { - ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x384f6577); - ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x1525); - } - - } else if (central_ch > 35) { - /* 5G */ - - /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18 | central_ch); - - /* 2. AGC table selection, removed, use API */ -/* - if ((central_ch >= 36) && (central_ch <= 64)) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x1); - pDM_DigTable->agcTableIdx = 0x1; - } else if ((central_ch >= 100) && (central_ch <= 144)) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x2); - pDM_DigTable->agcTableIdx = 0x2; - } else if (central_ch >= 149) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x3); - pDM_DigTable->agcTableIdx = 0x3; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch)); - return FALSE; - } -*/ - - /* 3. Set central frequency for clock offset tracking */ - if ((central_ch >= 36) && (central_ch <= 48)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494); - else if ((central_ch >= 52) && (central_ch <= 64)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453); - else if ((central_ch >= 100) && (central_ch <= 116)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452); - else if ((central_ch >= 118) && (central_ch <= 177)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412); - else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch)); - return FALSE; - } - - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if ((central_ch >= 57) && (central_ch <= 75)) - rf_regB8 = rf_regB8 & (~BIT19); - else - rf_regB8 = rf_regB8 | BIT19; - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch)); - return FALSE; - } - - /* Modify IGI for MP driver to aviod PCIE interference */ - if ((pDM_Odm->mp_mode == TRUE) && ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5))) { - if (central_ch == 14) - ODM_Write_DIG(pDM_Odm, 0x26); - else - ODM_Write_DIG(pDM_Odm, 0x20); - } - - /* Modify the setting of register 0xBE to reduce phase noise */ - if (central_ch <= 14) - rf_regBE = 0x0; - else if ((central_ch >= 36) && (central_ch <= 64)) - rf_regBE = low_band[(central_ch - 36)>>1]; - else if ((central_ch >= 100) && (central_ch <= 144)) - rf_regBE = middle_band[(central_ch - 100)>>1]; - else if ((central_ch >= 149) && (central_ch <= 177)) - rf_regBE = high_band[(central_ch - 149)>>1]; - else - rf_regBE = 0xff; - - if (rf_regBE != 0xff) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xbe, (BIT17|BIT16|BIT15), rf_regBE); - else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch)); - return FALSE; - } - - /* Fix channel 144 issue, ask by RFSI Alvin*/ - /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/ - /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ - if (central_ch == 144) { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x1); - rf_reg18 = (rf_reg18 | BIT17); - } else { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x0); - - if (central_ch > 144) - rf_reg18 = (rf_reg18 | BIT18); - else if (central_ch >= 80) - rf_reg18 = (rf_reg18 | BIT17); - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8); - - if (pDM_Odm->RFType > ODM_1T1R) { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0xb8, bRFRegOffsetMask, rf_regB8); - } - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); - return FALSE; - } - - /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - phydm_dynamic_spur_det_elimitor(pDM_Odm); - - /* Debug for RF resister reading error during synthesizer parameters parsing */ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb8, BIT19, 0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb8, BIT19, 1); - - phydm_ccapar_by_rfe_8822b(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_bandwidth_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - u4Byte rf_reg18; - u1Byte IGI; - BOOLEAN rf_reg_status = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n")); - return TRUE; - } - - /* Error handling */ - if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return FALSE; - } - - bw_8822b = bandwidth; - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); - - /* Switch bandwidth */ - switch (bandwidth) { - case ODM_BW20M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M); - - /* ADC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 | BIT11 | BIT10); - - break; - } - case ODM_BW40M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M)); - - /* CCK primary channel */ - if (primary_ch_idx == 1) - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx); - else - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0); - - /* ADC clock = 160M clock for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT11); - - break; - } - case ODM_BW80M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M)); - - /* ADC clock = 160M clock for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT10); - - break; - } - case ODM_BW5M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M)); - - /* ADC clock = 40M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - case ODM_BW10M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M)); - - /* ADC clock = 80M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); - - /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); - - /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); - - /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); - - break; - } - default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - } - - /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); - return FALSE; - } - - /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); - - /* Modify RX DFIR parameters */ - phydm_rxdfirpar_by_bw_8822b(pDM_Odm, bandwidth); - - /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - phydm_dynamic_spur_det_elimitor(pDM_Odm); - - /* Modify CCA parameters */ - phydm_ccapar_by_bw_8822b(pDM_Odm, bandwidth); - phydm_ccapar_by_rfe_8822b(pDM_Odm); - - /* Toggle RX path to avoid RX dead zone issue */ - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0); - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (pDM_Odm->RXAntStatus|(pDM_Odm->RXAntStatus<<4))); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return TRUE; -} - -BOOLEAN -config_phydm_switch_channel_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) -{ - - /* Switch band */ - if (config_phydm_switch_band_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; - - /* Switch channel */ - if (config_phydm_switch_channel_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; - - /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8822b(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) - return FALSE; - - return TRUE; -} - -BOOLEAN -config_phydm_trx_mode_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) -{ - BOOLEAN rf_reg_status = TRUE; - u1Byte IGI; - u4Byte rf_reg33 = 0; - u2Byte counter = 0; - - //PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - //PADAPTER pAdapter = pDM_Odm->Adapter; - //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n")); - return TRUE; - } - - if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", TxPath)); - return FALSE; - } - - if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", RxPath)); - return FALSE; - } - - /* RF mode of path-A and path-B */ - /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */ - if ((TxPath|RxPath) & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x3231); - else - ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x1111); - - if ((TxPath|RxPath) & ODM_RF_B) - ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x3231); - else - ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x1111); - - /* Set TX antenna by Nsts */ - ODM_SetBBReg(pDM_Odm, 0x93c, (BIT19|BIT18), 0x3); - ODM_SetBBReg(pDM_Odm, 0x80c, (BIT29|BIT28), 0x1); - - /* Control CCK TX path by 0xa07[7] */ - ODM_SetBBReg(pDM_Odm, 0x80c, BIT30, 0x1); - - /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/ - if (TxPath & ODM_RF_A) { - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x001); - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); - } else if (TxPath & ODM_RF_B) { - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x002); - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); - } - - /* TX logic map and TX path en for Nsts = 2*/ - if ((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B)) - ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x01); - else - ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x43); - - /* TX path enable */ - ODM_SetBBReg(pDM_Odm, 0x80c, bMaskByte0, ((TxPath << 4)|TxPath)); - - /* Tx2path for 1ss */ - if (!((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))) { - if (bTx2Path || pDM_Odm->mp_mode) { - /* 2Tx for OFDM */ - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x043); - - /* 2Tx for CCK */ - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); - } - } - - /* Always disable MRC for CCK CCA */ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); - - /* Always disable MRC for CCK barker */ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); - - /* CCK RX 1st and 2nd path setting*/ - if (RxPath & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x0); - else if (RxPath & ODM_RF_B) - ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x5); - - /* RX path enable */ - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, ((RxPath << 4)|RxPath)); - - if ((RxPath == ODM_RF_A) || (RxPath == ODM_RF_B)) { - /* 1R */ - - /* Disable MRC for CCA */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); */ - - /* Disable MRC for barker */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); */ - - /* Disable CCK antenna diversity */ - /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ - - /* Disable Antenna weighting */ - ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x0); - ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x0); - ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x0); - } else { - /* 2R */ - - /* Enable MRC for CCA */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x1); */ - - /* Enable MRC for barker */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x1); */ - - /* Disable CCK antenna diversity */ - /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ - - /* Enable Antenna weighting */ - ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x1); - ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x1); - - /* AP only, L1 SBD change in 2R case */ - if (pDM_Odm->SupportPlatform == ODM_AP) { - ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x171750E0); - } - } - - /* Update TXRX antenna status for PHYDM */ - pDM_Odm->TXAntStatus = (TxPath & 0x3); - pDM_Odm->RXAntStatus = (RxPath & 0x3); - - /* MP driver need to support path-B TX\RX */ - - while(1){ - counter++; - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); - - ODM_delay_us(2); - rf_reg33 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask); - - if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33))) - break; - else if (counter == 100) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n")); - return FALSE; - } - } - - if ((pDM_Odm->mp_mode) || (pDM_Odm->pAntennaTest) || (pDM_Odm->Normalrxpath)) { - /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e 0xef 0x00000 suggested by Lucas*/ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080e); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n")); - } else { - /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c 0xef 0x00000 */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080c); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n")); - } - - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", TxPath, RxPath)); - return FALSE; - } - - /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - //IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); - //ODM_Write_DIG(pDM_Odm, IGI - 2); - //ODM_Write_DIG(pDM_Odm, IGI); - - IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); - - /* Modify CCA parameters */ - phydm_ccapar_by_rxpath_8822b(pDM_Odm); - phydm_ccapar_by_rfe_8822b(pDM_Odm); - phydm_rfe_8822b(pDM_Odm, central_ch_8822b); - - /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - phydm_dynamic_spur_det_elimitor(pDM_Odm); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath)); - return TRUE; -} - - -BOOLEAN -config_phydm_parameter_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ) -{ - if (type == ODM_PRE_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Pre setting: disable OFDM and CCK block\n")); - } else if (type == ODM_POST_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Post setting: enable OFDM and CCK block\n")); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Wrong type!!\n")); - return FALSE; - } - - //phydm_set_iqgen_8822B(pDM_Odm); - return TRUE; -} - -/* ======================================================================== */ -#endif /* RTL8822B_SUPPORT == 1 */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +ODM_BW_E bw_8822b; +u1Byte central_ch_8822b; + +#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) + u32 cca_ifem_bcut[3][4] = { + {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ + {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87766441, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ + }; + u32 cca_efem_bcut[3][4] = { + {0x75B76010, 0x75B76010, 0x75B76010, 0x75B75010}, /*Reg82C*/ + {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ + }; +#endif + +u32 cca_ifem_ccut[3][4] = { + {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ + {0x79a0ea2a, 0x79A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87765541, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ +}; +u32 cca_efem_ccut[3][4] = { + {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ + {0x79A0EA28, 0x79A0EA2C, 0x79A0EA28, 0x79a0ea2a}, /*Reg830*/ + {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ +}; +u32 cca_ifem_ccut_rfetype[3][4] = { + {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ + {0x79a0ea2a, 0x97A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87765541, 0x86666341, 0x87765561, 0x86666361} /*Reg838*/ +}; + +void +phydm_igi_toggle_8822b( + IN PDM_ODM_T pDM_Odm +) +{ + u32 igi = 0x20; + + igi = ODM_GetBBReg(pDM_Odm, 0xc50, 0x7f); + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, (igi - 2)); + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, igi); + ODM_SetBBReg(pDM_Odm, 0xe50, 0x7f, (igi - 2)); + ODM_SetBBReg(pDM_Odm, 0xe50, 0x7f, igi); +} + +BOOLEAN +phydm_rfe_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte channel + ) +{ + if (pDM_Odm->RFEType == 4) { + + /*TRSW = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/ + /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/ + /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */ + /*ODM_SetBBReg(pDM_Odm, 0x804, (BIT1|BIT0), 0x0);*/ + /* Default setting is in PHY parameters */ + + if (channel <= 14) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x2); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x2); + + /* antenna switch table */ + if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + /* 2TX or 2RX */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf050); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf050); + } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + /* TXA+RXA or TXB+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf055); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf055); + } else { + /* TXB+RXA or TXA+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf550); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf550); + } + + } else if (channel > 35) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + + /* antenna switch table */ + if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + /* 2TX or 2RX */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); + } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + /* TXA+RXA or TXB+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); + } + } else + return FALSE; + + + } + else if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9) || (pDM_Odm->RFEType == 11)) { + /* efem */ + if (((pDM_Odm->CutVersion == ODM_CUT_A) || (pDM_Odm->CutVersion == ODM_CUT_B)) && (pDM_Odm->RFEType < 2)) { + if (channel <= 14) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + } else if (channel > 35) { + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + } else + return FALSE; + + /* delay 400ns for PAPE */ + ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); + + /* antenna switch table */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555); + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__)); + } else { + /*After B-Cut*/ + if (channel <= 14) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x705770); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x705770); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xcb8, BIT4, 0); + ODM_SetBBReg(pDM_Odm, 0xeb8, BIT4, 0); + } else if (channel > 35) { + /* signal source */ + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x177517); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x177517); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xcb8, BIT5, 0); + ODM_SetBBReg(pDM_Odm, 0xeb8, BIT5, 0); + } else + return FALSE; + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + + /* delay 400ns for PAPE */ + /* ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); */ + + /* antenna switch table */ + if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + /* 2TX or 2RX */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); + } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + /* TXA+RXA or TXB+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); + } + } + } + else if ((pDM_Odm->RFEType == 0) || (pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8) || (pDM_Odm->RFEType == 10) || (pDM_Odm->RFEType == 12) || (pDM_Odm->RFEType == 13) || (pDM_Odm->RFEType == 14)) { + /* iFEM */ + if (channel <= 14) { + /* signal source */ + /*ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x705770); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x705770); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xcb8, BIT4, 0); + ODM_SetBBReg(pDM_Odm, 0xeb8, BIT4, 0);*/ + + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + + } else if (channel > 35) { + /* signal source */ + /*ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x177517); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x177517); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xcb8, BIT5, 1); + ODM_SetBBReg(pDM_Odm, 0xeb8, BIT5, 1);*/ + + ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); + ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); + ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); + ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + } else + return FALSE; + + /* inverse or not */ + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); + ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + + /* antenna switch table */ + if (channel <= 14) { + if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + /* 2TX or 2RX */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); + } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + /* TXA+RXA or TXB+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); + } + } else if (channel > 35) { + ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa5a5); + ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa5a5); + } + } + + /* chip top mux */ + ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3); + ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0); + ODM_SetBBReg(pDM_Odm, 0x40, BIT3, 0x1); + + /* from s0 or s1 */ + ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30); + ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3); + + /* input or output */ + ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f); + ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, TxPath 0x%x, RxPath 0x%x)\n", __func__, channel, pDM_Odm->TXAntStatus, pDM_Odm->RXAntStatus)); + + return TRUE; +} + +u8 +phydm_is_dfs_channel(u8 channel_num) +{ + if(channel_num >= 52 && channel_num <= 140) + return 1; + else + return 0; +} + +VOID +phydm_ccapar_by_rfe_8822b( + IN PDM_ODM_T pDM_Odm + ) +{ + u32 cca_ifem[3][4], cca_efem[3][4]; + u8 col; + u32 reg82c, reg830, reg838; + BOOLEAN is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; + +#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pDM_Odm->CutVersion == ODM_CUT_B) { + ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_bcut, 12 * 4); + ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_bcut, 12 * 4); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__)); + } else +#endif + { + ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_ccut, 12 * 4); + if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) { + ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_rfetype, 12 * 4); + is_rfe_type = true; + } else + ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut, 12 * 4); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__)); + } + + if (central_ch_8822b <= 14) { + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) + col = 0; /*1R 2G*/ + else + col = 1; /*2R 2G*/ + } else { + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) + col = 2; /*1R 5G*/ + else + col = 3; /*2R 5G*/ + } + + if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 4) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 11)) { + /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7 & RFE type 11*/ + reg82c = cca_efem[0][col]; + reg830 = cca_efem[1][col]; + reg838 = cca_efem[2][col]; + is_efem_cca = true; + } else if ((pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 9)) { + /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */ + if (central_ch_8822b <= 14) { + reg82c = cca_ifem[0][col]; + reg830 = cca_ifem[1][col]; + reg838 = cca_ifem[2][col]; + is_ifem_cca = true; + } else { + reg82c = cca_efem[0][col]; + reg830 = cca_efem[1][col]; + reg838 = cca_efem[2][col]; + is_efem_cca = true; + } + } else { + /* iFEM =>RFEtype 3 & RFE type 5 & RFE type 0 & RFE type 8 & RFE type 10 & RFE type 12 & RFE type 13*/ + reg82c = cca_ifem[0][col]; + reg830 = cca_ifem[1][col]; + reg838 = cca_ifem[2][col]; + is_ifem_cca = true; + } + + ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); + + if (is_ifem_cca == true) + if (((pDM_Odm->CutVersion == ODM_CUT_B) && (col == 1 || col == 3) && (bw_8822b == ODM_BW40M)) || + ((is_rfe_type == false) && (col == 3) && (bw_8822b == ODM_BW40M)) || + ((pDM_Odm->RFEType == 5) && (col == 3))) + ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, 0x79a0ea28); + else + ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); + else + ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); + + ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838); + + if (!(pDM_Odm->CutVersion == ODM_CUT_B)) + ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, 0x9194b2b9); + + /* CCA parameters adjust for 20MHz on DFS channel */ + if ((*pDM_Odm->pBandWidth == ODM_BW20M) && (((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 144)))) + ODM_SetBBReg(pDM_Odm, 0x838, 0xf0, 0x4); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), col = %d\n", + __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, col)); +} + +VOID +phydm_ccapar_by_bw_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ + u4Byte reg82c; + + + if (pDM_Odm->CutVersion != ODM_CUT_A) + return; + + /* A-cut */ + reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); + + if (bandwidth == ODM_BW20M) { + /* 82c[15:12] = 4 */ + /* 82c[27:24] = 6 */ + + reg82c &= (~(0x0f00f000)); + reg82c |= ((0x4) << 12); + reg82c |= ((0x6) << 24); + } else if (bandwidth == ODM_BW40M) { + /* 82c[19:16] = 9 */ + /* 82c[27:24] = 6 */ + + reg82c &= (~(0x0f0f0000)); + reg82c |= ((0x9) << 16); + reg82c |= ((0x6) << 24); + } else if (bandwidth == ODM_BW80M) { + /* 82c[15:12] 7 */ + /* 82c[19:16] b */ + /* 82c[23:20] d */ + /* 82c[27:24] 3 */ + + reg82c &= (~(0x0ffff000)); + reg82c |= ((0xdb7) << 12); + reg82c |= ((0x3) << 24); + } + + ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByBw_8822b(): Update CCA parameters for Acut\n")); + +} + +VOID +phydm_ccapar_by_rxpath_8822b( + IN PDM_ODM_T pDM_Odm + ) +{ + + if (pDM_Odm->CutVersion != ODM_CUT_A) + return; + + if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) { + /* 838[7:4] = 8 */ + /* 838[11:8] = 7 */ + /* 838[15:12] = 6 */ + /* 838[19:16] = 7 */ + /* 838[23:20] = 7 */ + /* 838[27:24] = 7 */ + ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678); + } else { + /* 838[7:4] = 3 */ + /* 838[11:8] = 3 */ + /* 838[15:12] = 6 */ + /* 838[19:16] = 6 */ + /* 838[23:20] = 7 */ + /* 838[27:24] = 7 */ + ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633); + } + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByRxPath_8822b(): Update CCA parameters for Acut\n")); + +} + +VOID +phydm_rxdfirpar_by_bw_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_BW_E bandwidth + ) +{ + if (bandwidth == ODM_BW40M) { + /* RX DFIR for BW40 */ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x0); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); + ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); + } else if (bandwidth == ODM_BW80M) { + /* RX DFIR for BW80 */ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); + ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); + } else { + /* RX DFIR for BW20, BW10 and BW5*/ + ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1); + ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x1); + } +} + +BOOLEAN +phydm_write_txagc_1byte_8822b( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; + u1Byte rate_idx = (HwRate & 0xfc), i; + u1Byte rate_offset = (HwRate & 0x3); + u4Byte txagc_content = 0x0; + + /* For debug command only!!!! */ + + /* Error handling */ + if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", Path)); + return FALSE; + } + + /* For HW limitation, We can't write TXAGC once a byte. */ + for (i = 0; i < 4; i++) { + if (i != rate_offset) + txagc_content = txagc_content|(config_phydm_read_txagc_8822b(pDM_Odm, Path, rate_idx + i) << (i << 3)); + else + txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3)); + } + ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", + Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); + return TRUE; +} + +VOID +phydm_init_hw_info_by_rfe_type_8822b( + IN PDM_ODM_T pDM_Odm +) +{ + u2Byte mask_path_a = 0x0303; + u2Byte mask_path_b = 0x0c0c; + /*u2Byte mask_path_c = 0x3030;*/ + /*u2Byte mask_path_d = 0xc0c0;*/ + + pDM_Odm->bInitHwInfoByRfe = FALSE; + /* 1R for path-b always used in AP platform */ + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, TRUE); + #endif + + if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); + + if (pDM_Odm->RFEType == 6) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b))); + } else if (pDM_Odm->RFEType == 7) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a|mask_path_b))); + } else { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); + } + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); + } else if (pDM_Odm->RFEType == 2) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA_5G)); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); + } else if (pDM_Odm->RFEType == 9) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G)); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + } else if (pDM_Odm->RFEType == 3) { + /* RFE type 3: 8822BS\8822BU TFBGA iFEM */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + } else if (pDM_Odm->RFEType == 5) { + /* RFE type 5: 8822BE TFBGA iFEM */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_SLIM); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + } else if (pDM_Odm->RFEType == 12) { + /* RFE type 12: QFN iFEM */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, false); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, false); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, false); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (pDM_Odm->RFEType == 4) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); + } else if (pDM_Odm->RFEType == 11) { + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b))); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); + } else if (pDM_Odm->RFEType == 8) { + /* RFE Type 8: TFBGA iFEM AP */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + } else if (pDM_Odm->RFEType == 10) { + /* RFE Type 10: QFN iFEM AP PCIE */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_TRSW); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + + } else { + /* RFE Type 0 & 13: QFN iFEM */ + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + } + + pDM_Odm->bInitHwInfoByRfe = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): RFE type (%d), Board type (0x%x), Package type (%d)\n", pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType)); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA)); +} + +s4Byte +phydm_get_condition_number_8822B( + IN PDM_ODM_T pDM_Odm +) +{ + s4Byte ret_val; + + ODM_SetBBReg( pDM_Odm, 0x1988, BIT22, 0x1); + ret_val = (s4Byte)ODM_GetBBReg(pDM_Odm, 0xf84, (BIT17|BIT16|bMaskLWord)); + + if (bw_8822b == 0) { + ret_val = ret_val << (8 - 4); + ret_val = ret_val / 234; + } else if (bw_8822b == 1) { + ret_val = ret_val << (7 - 4); + ret_val = ret_val / 108; + } else if (bw_8822b == 2) { + ret_val = ret_val << (6 - 4); + ret_val = ret_val / 52; + } + + return ret_val; +} + + +/* ======================================================================== */ + +/* ======================================================================== */ +/* These following functions can be used by driver*/ + +u4Byte +config_phydm_read_rf_reg_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ + u4Byte Readback_Value, Direct_Addr; + u4Byte offset_readRF[2] = {0x2800, 0x2c00}; + u4Byte power_RF[2] = {0x1c, 0xec}; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_B) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); + return INVALID_RF_DATA; + } + + /* Error handling. Check if RF power is enable or not */ + /* 0xffffffff means RF power is disable */ + if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): Read fail, RF is disabled\n")); + return INVALID_RF_DATA; + } + + /* Calculate offset */ + RegAddr &= 0xff; + Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); + + /* RF register only has 20bits */ + BitMask &= bRFRegOffsetMask; + + /* Read RF register directly */ + Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + RFPath, RegAddr, Readback_Value, BitMask)); + return Readback_Value; +} + +BOOLEAN +config_phydm_write_rf_reg_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ + u4Byte DataAndAddr = 0, Data_original = 0; + u4Byte offset_writeRF[2] = {0xc90, 0xe90}; + u4Byte power_RF[2] = {0x1c, 0xec}; + u1Byte BitShift; + + /* Error handling.*/ + if (RFPath > ODM_RF_PATH_B) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); + return FALSE; + } + + /* Read RF register content first */ + RegAddr &= 0xff; + BitMask = BitMask & bRFRegOffsetMask; + + if (BitMask != bRFRegOffsetMask) { + Data_original = config_phydm_read_rf_reg_8822b(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); + + /* Error handling. RF is disabled */ + if (config_phydm_read_rf_check_8822b(Data_original) == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n")); + return FALSE; + } + + /* check bit mask */ + if (BitMask != 0xfffff) { + for (BitShift = 0; BitShift <= 19; BitShift++) { + if (((BitMask >> BitShift) & 0x1) == 1) + break; + } + Data = ((Data_original) & (~BitMask)) | ((Data << BitShift) & (BitMask)); + } + } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disabled\n")); + return FALSE; + } + + /* Put write addr in [27:20] and write data in [19:00] */ + DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; + + /* Write Operation */ + ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + RFPath, RegAddr, Data, Data_original, BitMask)); + + ODM_delay_us(2); + return TRUE; +} + +BOOLEAN +config_phydm_write_txagc_8822b( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; + u1Byte rate_idx = (HwRate & 0xfc); + + /* Input need to be HW rate index, not driver rate index!!!! */ + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n")); + return TRUE; + } + + /* Error handling */ + if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", Path)); + return FALSE; + } + + /* driver need to construct a 4-byte power index */ + ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", + Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); + return TRUE; +} + +u1Byte +config_phydm_read_txagc_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ) +{ + u1Byte readBack_data; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + /* Error handling */ + if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", Path)); + return INVALID_TXAGC_DATA; + } + + /* Disable TX AGC report */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */ + + /* Set data rate index (bit0~6) and path index (bit7) */ + ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7))); + + /* Enable TXAGC report */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1); + + /* Read TX AGC report */ + readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000); + + /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ + ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data)); + return readBack_data; +} + +VOID +phydm_dynamic_spur_det_elimitor( + IN PDM_ODM_T pDM_Odm +) +{ + u32 freq_2g[number_of_2g_freq_pt] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67, 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFF66, 0xFF26, 0xFCE7}; + u32 freq_5g[number_of_5g_freq_pt] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41, 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42}; + u32 freq_2g_n1[number_of_2g_freq_pt] = {0}, freq_2g_p1[number_of_2g_freq_pt] = {0}; + u32 freq_5g_n1[number_of_5g_freq_pt] = {0}, freq_5g_p1[number_of_5g_freq_pt] = {0}; + u32 freq_pt_2g_final = 0, freq_pt_5g_final = 0, freq_pt_2g_b_final = 0, freq_pt_5g_b_final = 0; + u32 max_ret_psd_final = 0, max_ret_psd_b_final = 0; + u32 max_ret_psd_2nd[number_of_sample] = {0}, max_ret_psd_b_2nd[number_of_sample] = {0}; + u32 psd_set[number_of_psd_value] = {0}, psd_set_B[number_of_psd_value] = {0}; + u32 rank_psd_index_in[number_of_psd_value] = {0}, rank_sample_index_in[number_of_sample] = {0}; + u32 rank_psd_index_out[number_of_psd_value] = {0}; + u32 rank_sample_index_out[number_of_sample] = {0}; + u32 reg_910_15_12 = 0; + u8 j = 0, k = 0, threshold_nbi = 0x8D, threshold_csi = 0x8D; + u8 idx = 0, set_result_nbi = SET_NO_NEED, set_result_csi = SET_NO_NEED; + BOOLEAN s_dopsd = false, s_donbi_a = false, s_docsi = false, s_donbi_b = false; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_PSDTOOL)) { + ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic Spur Detection and Eliminator\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("Dynamic Spur Detection and Eliminator is ON\n")); + + /* Reset NBI/CSI everytime after changing channel/BW/band */ + ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0); + ODM_SetBBReg(pDM_Odm, 0x874, BIT(0), 0x0); + + ODM_SetBBReg(pDM_Odm, 0x87c, BIT(13), 0x0); + ODM_SetBBReg(pDM_Odm, 0xc20, BIT(28), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe20, BIT(28), 0x0); + + /* 2G Channel Setting > 20M: 5, 6, 7, 8, 13; 40M: 3~11 */ + if ((*pDM_Odm->pChannel >= 1) && (*pDM_Odm->pChannel <= 14)) { + if (*pDM_Odm->pBandWidth == ODM_BW20M) { + + if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) + idx = *pDM_Odm->pChannel - 5; + else if (*pDM_Odm->pChannel == 13) + idx = 4; + else + idx = 16; + } else { + + if (*pDM_Odm->pChannel >= 3 && *pDM_Odm->pChannel <= 11) + idx = *pDM_Odm->pChannel + 2; + else + idx = 16; + } + } else { /* 5G Channel Setting > 20M: 153, 161; 40M: 54, 118, 151, 159; 80M: 58, 122, 155, 155 */ + switch (*pDM_Odm->pChannel) { + case 153: + idx = 0; + break; + case 161: + idx = 1; + break; + case 54: + idx = 2; + break; + case 118: + idx = 3; + break; + case 151: + idx = 4; + break; + case 159: + idx = 5; + break; + case 58: + idx = 6; + break; + case 122: + idx = 7; + break; + case 155: + idx = 8; + break; + default: + idx = 16; + break; + } + } + + if (idx <= 16) { + s_dopsd = true; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Point] Idx Is Exceed, Not Support Dynamic Spur Detection and Eliminator\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] idx = %d, BW = %d, Channel = %d\n", __func__, idx, *pDM_Odm->pBandWidth, *pDM_Odm->pChannel)); + + for (k = 0; k < number_of_2g_freq_pt; k++) { + freq_2g_n1[k] = freq_2g[k] - 1; + freq_2g_p1[k] = freq_2g[k] + 1; + } + + for (k = 0; k < number_of_5g_freq_pt; k++) { + freq_5g_n1[k] = freq_5g[k] - 1; + freq_5g_p1[k] = freq_5g[k] + 1; + } + + if ((s_dopsd == TRUE) && (idx <= 13)) { + for (k = 0; k < number_of_sample; k++) { + if (k == 0) { + freq_pt_2g_final = freq_2g_n1[idx]; + freq_pt_5g_final = freq_5g_n1[idx]; + freq_pt_2g_b_final = freq_2g_n1[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g_n1[idx] | BIT(16); + } else if (k == 1) { + freq_pt_2g_final = freq_2g[idx]; + freq_pt_5g_final = freq_5g[idx]; + freq_pt_2g_b_final = freq_2g[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g[idx] | BIT(16); + } else if (k == 2) { + freq_pt_2g_final = freq_2g_p1[idx]; + freq_pt_5g_final = freq_5g_p1[idx]; + freq_pt_2g_b_final = freq_2g_p1[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g_p1[idx] | BIT(16); + } + + for (j = 0; j < number_of_psd_value; j++) { + ODM_SetBBReg(pDM_Odm, 0xc00, bMaskByte0, 0x4);/* disable 3-wire, path-A */ + ODM_SetBBReg(pDM_Odm, 0xe00, bMaskByte0, 0x4);/* disable 3-wire, path-B */ + reg_910_15_12 = ODM_GetBBReg(pDM_Odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12)); + + if (pDM_Odm->RXAntStatus & ODM_RF_A) { + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((ODM_RF_A)<<4) | ODM_RF_A));/*path-A*/ + + if ((*pDM_Odm->pChannel >= 1) && (*pDM_Odm->pChannel <= 14)) + ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_2g_final);/* Start PSD */ + else + ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_5g_final);/* Start PSD */ + + ODM_delay_us(500); + + psd_set[j] = ODM_GetBBReg(pDM_Odm, 0xf44, bMaskLWord); + + ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0x0);/* turn off PSD */ + } + + if (pDM_Odm->RXAntStatus & ODM_RF_B) { + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((ODM_RF_B)<<4) | ODM_RF_B));/*path-B*/ + + if ((*pDM_Odm->pChannel > 0) && (*pDM_Odm->pChannel <= 14)) + ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_2g_b_final);/* Start PSD */ + else + ODM_SetBBReg(pDM_Odm, 0x910, bMaskDWord, BIT(22) | freq_pt_5g_b_final);/* Start PSD */ + + ODM_delay_us(500); + + psd_set_B[j] = ODM_GetBBReg(pDM_Odm, 0xf44, bMaskLWord); + + ODM_SetBBReg(pDM_Odm, 0x910, BIT22, 0x0);/* turn off PSD */ + } + + ODM_SetBBReg(pDM_Odm, 0xc00, bMaskByte0, 0x7);/*eanble 3-wire*/ + ODM_SetBBReg(pDM_Odm, 0xe00, bMaskByte0, 0x7); + ODM_SetBBReg(pDM_Odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12), reg_910_15_12); + + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (((pDM_Odm->RXAntStatus)<<4) | pDM_Odm->RXAntStatus)); + + /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + phydm_igi_toggle_8822b(pDM_Odm); + + } + if (pDM_Odm->RXAntStatus & ODM_RF_A) { + phydm_seq_sorting(pDM_Odm, psd_set, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); + max_ret_psd_2nd[k] = psd_set[0]; + } + if (pDM_Odm->RXAntStatus & ODM_RF_B) { + phydm_seq_sorting(pDM_Odm, psd_set_B, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); + max_ret_psd_b_2nd[k] = psd_set_B[0]; + } + } + + if (pDM_Odm->RXAntStatus & ODM_RF_A) { + phydm_seq_sorting(pDM_Odm, max_ret_psd_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); + max_ret_psd_final = max_ret_psd_2nd[0]; + + if (max_ret_psd_final >= threshold_nbi) + s_donbi_a = true; + else + s_donbi_a = false; + } + if (pDM_Odm->RXAntStatus & ODM_RF_B) { + phydm_seq_sorting(pDM_Odm, max_ret_psd_b_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); + max_ret_psd_b_final = max_ret_psd_b_2nd[0]; + + if (max_ret_psd_b_final >= threshold_nbi) + s_donbi_b = true; + else + s_donbi_b = false; + } + + ODM_RT_TRACE(pDM_Odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] max_ret_psd_final = %d, max_ret_psd_b_final = %d\n", __func__, max_ret_psd_final, max_ret_psd_b_final)); + + if ((max_ret_psd_final >= threshold_csi) || (max_ret_psd_b_final >= threshold_csi)) + s_docsi = true; + else + s_docsi = false; + + } + + if (s_donbi_a == true || s_donbi_b == true) { + if (*pDM_Odm->pBandWidth == ODM_BW20M) { + if (*pDM_Odm->pChannel == 153) + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 5760, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 161) + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 5800, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 2440, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 13) + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 20, 2480, PHYDM_DONT_CARE); + else + set_result_nbi = SET_NO_NEED; + } else if (*pDM_Odm->pBandWidth == ODM_BW40M) { + if (*pDM_Odm->pChannel == 54) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5280, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 118) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5600, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 151) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5760, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 159) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 5800, PHYDM_DONT_CARE); + /* 2.4G */ + } else if ((*pDM_Odm->pChannel >= 4) && (*pDM_Odm->pChannel <= 6)) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 11) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); + } else + set_result_nbi = SET_NO_NEED; + } else if (*pDM_Odm->pBandWidth == ODM_BW80M) { + if (*pDM_Odm->pChannel == 58) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5280, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 122) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5600, PHYDM_DONT_CARE); + } else if (*pDM_Odm->pChannel == 155) { + set_result_nbi = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, *pDM_Odm->pChannel, 80, 5760, PHYDM_DONT_CARE); + } else + set_result_nbi = SET_NO_NEED; + } else + set_result_nbi = SET_NO_NEED; + } + + if (s_docsi == true) { + if (*pDM_Odm->pBandWidth == ODM_BW20M) { + if (*pDM_Odm->pChannel == 153) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 5760, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 161) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 5800, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel >= 5 && *pDM_Odm->pChannel <= 8) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 2440, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 13) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 20, 2480, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else if (*pDM_Odm->pBandWidth == ODM_BW40M) { + if (*pDM_Odm->pChannel == 159) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 5800, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 151) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 5760, PHYDM_DONT_CARE); + else if ((*pDM_Odm->pChannel >= 3) && (*pDM_Odm->pChannel <= 10)) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 2440, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 11) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 40, 2480, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else if (*pDM_Odm->pBandWidth == ODM_BW80M) { + if (*pDM_Odm->pChannel == 58) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5280, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 122) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5600, PHYDM_DONT_CARE); + else if (*pDM_Odm->pChannel == 155) + set_result_csi = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, *pDM_Odm->pChannel, 80, 5760, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else + set_result_csi = SET_NO_NEED; + } + +} + +BOOLEAN +config_phydm_switch_band_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ) +{ + u4Byte rf_reg18; + BOOLEAN rf_reg_status = TRUE; + u4Byte reg_8; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n")); + return TRUE; + } + + rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); + + if (central_ch <= 14) { + /* 2.4G */ + + /* Enable CCK block */ + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1); + + /* Disable MAC CCK check */ + ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0); + + /* Disable BB CCK check */ + ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0); + + /*CCA Mask*/ + ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); + + /* RxHP dynamic control */ + if ((pDM_Odm->RFEType == 2) || (pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); + } + + /* QFN eFEM RxHP are always low at 2G */ + reg_8 = ODM_GetBBReg(pDM_Odm, 0x19a8, BIT31); + + /* SoML on */ + if (reg_8 == 0x1) { + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); + if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8)) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); + } else { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } + } + + /* SoML off */ + if (reg_8 == 0x0) { + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); + if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9)) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); + } + } + + } else if (central_ch > 35) { + /* 5G */ + + /* Enable BB CCK check */ + ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1); + + /* Enable CCK check */ + ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1); + + /* Disable CCK block */ + ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0); + + /*CCA Mask*/ + if ((!pDM_Odm->WIFITest==1) || ((DM_ODM_SUPPORT_TYPE == ODM_AP) && (pDM_Odm->WIFITest))) + ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + else + ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); + rf_reg18 = (rf_reg18|BIT8|BIT16); + + /* RxHP dynamic control */ + reg_8 = ODM_GetBBReg(pDM_Odm, 0x19a8, BIT31); + + /* SoML on */ + if (reg_8 == 0x1) { + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } + + /* SoML off */ + if (reg_8 == 0x0) { + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT18|BIT21), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT18|BIT21), 0x0); + if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9)) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108492); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x1); + } + } + + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch)); + return FALSE; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->RFType > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + + if (phydm_rfe_8822b(pDM_Odm, central_ch) == FALSE) + return FALSE; + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch)); + return FALSE; + } + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + phydm_dynamic_spur_det_elimitor(pDM_Odm); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_agc_tab_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN bool is_switch_sat_tab + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + bool is_success = TRUE; + + if (central_ch <= 14) { + pDM_DigTable->agcTableIdx = 0x0; + + } else if (central_ch > 35) { + if ((central_ch >= 36) && (central_ch <= 64)) { + pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x5 : 0x1; + } else if ((central_ch >= 100) && (central_ch <= 144)) { + pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x6 : 0x2; + } else if (central_ch >= 149) { + pDM_DigTable->agcTableIdx = is_switch_sat_tab ? 0x7 : 0x3; + } else { + is_success = FALSE; + } + } else { + is_success = FALSE; + } + + if (is_success) + ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, pDM_DigTable->agcTableIdx); + else + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Fail to switch agc table (ch: %d)\n", __FUNCTION__, central_ch)); + + return is_success; + +} + +BOOLEAN +config_phydm_switch_channel_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ) +{ + u4Byte rf_reg18 = 0, rf_regB8 = 0, rf_regBE = 0xff; + BOOLEAN rf_reg_status = TRUE; + u1Byte low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; + u1Byte middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7}; + u1Byte high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n")); + return TRUE; + } + + central_ch_8822b = central_ch; + rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); + rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); + + if (pDM_Odm->CutVersion == ODM_CUT_A) { + rf_regB8 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_regB8); + } + + if(config_phydm_switch_agc_tab_8822b(pDM_Odm, central_ch, DEFAULT_AGC_TABLE) == FALSE) + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Fail to switch channel (AGC) (ch: %d)\n", __FUNCTION__, central_ch)); + + /* Switch band and channel */ + if (central_ch <= 14) { + /* 2.4G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18|central_ch); + + /* 2. AGC table selection, removed, use API */ + +/* + ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x0); + pDM_DigTable->agcTableIdx = 0x0; +*/ + /* 3. Set central frequency for clock offset tracking */ + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a); + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (pDM_Odm->CutVersion == ODM_CUT_A) + rf_regB8 = rf_regB8 | BIT19; + + /* CCK TX filter parameters */ + if (central_ch == 14) { + ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x00006577); + ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x0000); + } else { + ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x384f6577); + ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x1525); + } + + } else if (central_ch > 35) { + /* 5G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 | central_ch); + + /* 2. AGC table selection, removed, use API */ +/* + if ((central_ch >= 36) && (central_ch <= 64)) { + ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x1); + pDM_DigTable->agcTableIdx = 0x1; + } else if ((central_ch >= 100) && (central_ch <= 144)) { + ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x2); + pDM_DigTable->agcTableIdx = 0x2; + } else if (central_ch >= 149) { + ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x3); + pDM_DigTable->agcTableIdx = 0x3; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch)); + return FALSE; + } +*/ + + /* 3. Set central frequency for clock offset tracking */ + if ((central_ch >= 36) && (central_ch <= 48)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494); + else if ((central_ch >= 52) && (central_ch <= 64)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453); + else if ((central_ch >= 100) && (central_ch <= 116)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452); + else if ((central_ch >= 118) && (central_ch <= 177)) + ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412); + else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch)); + return FALSE; + } + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (pDM_Odm->CutVersion == ODM_CUT_A) { + if ((central_ch >= 57) && (central_ch <= 75)) + rf_regB8 = rf_regB8 & (~BIT19); + else + rf_regB8 = rf_regB8 | BIT19; + } + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch)); + return FALSE; + } + + /* Modify IGI for MP driver to aviod PCIE interference */ + if ((pDM_Odm->mp_mode == TRUE) && ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5))) { + if (central_ch == 14) + ODM_Write_DIG(pDM_Odm, 0x26); + else + ODM_Write_DIG(pDM_Odm, 0x20); + } + + /* Modify the setting of register 0xBE to reduce phase noise */ + if (central_ch <= 14) + rf_regBE = 0x0; + else if ((central_ch >= 36) && (central_ch <= 64)) + rf_regBE = low_band[(central_ch - 36)>>1]; + else if ((central_ch >= 100) && (central_ch <= 144)) + rf_regBE = middle_band[(central_ch - 100)>>1]; + else if ((central_ch >= 149) && (central_ch <= 177)) + rf_regBE = high_band[(central_ch - 149)>>1]; + else + rf_regBE = 0xff; + + if (rf_regBE != 0xff) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xbe, (BIT17|BIT16|BIT15), rf_regBE); + else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch)); + return FALSE; + } + + /* Fix channel 144 issue, ask by RFSI Alvin*/ + /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/ + /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ + if (central_ch == 144) { + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x1); + rf_reg18 = (rf_reg18 | BIT17); + } else { + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x0); + + if (central_ch > 144) + rf_reg18 = (rf_reg18 | BIT18); + else if (central_ch >= 80) + rf_reg18 = (rf_reg18 | BIT17); + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->CutVersion == ODM_CUT_A) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8); + + if (pDM_Odm->RFType > ODM_1T1R) { + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->CutVersion == ODM_CUT_A) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0xb8, bRFRegOffsetMask, rf_regB8); + } + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); + return FALSE; + } + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + phydm_dynamic_spur_det_elimitor(pDM_Odm); + + /* Debug for RF resister reading error during synthesizer parameters parsing */ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb8, BIT19, 0); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb8, BIT19, 1); + + phydm_ccapar_by_rfe_8822b(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_bandwidth_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + u4Byte rf_reg18; + u1Byte IGI; + BOOLEAN rf_reg_status = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n")); + return TRUE; + } + + /* Error handling */ + if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return FALSE; + } + + bw_8822b = bandwidth; + rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); + + /* Switch bandwidth */ + switch (bandwidth) { + case ODM_BW20M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M); + + /* ADC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT11 | BIT10); + + break; + } + case ODM_BW40M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M)); + + /* CCK primary channel */ + if (primary_ch_idx == 1) + ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx); + else + ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0); + + /* ADC clock = 160M clock for BW40 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); + rf_reg18 = (rf_reg18|BIT11); + + break; + } + case ODM_BW80M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M)); + + /* ADC clock = 160M clock for BW80 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); + rf_reg18 = (rf_reg18|BIT10); + + break; + } + case ODM_BW5M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M)); + + /* ADC clock = 40M clock */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + case ODM_BW10M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M)); + + /* ADC clock = 80M clock */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + + /* DAC clock = 160M clock for BW20 */ + ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3); + ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + + /* ADC buffer clock */ + ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); + ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18|BIT11|BIT10); + + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + } + + /* Write RF register */ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + + if (pDM_Odm->RFType > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); + return FALSE; + } + + /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); + + /* Modify RX DFIR parameters */ + phydm_rxdfirpar_by_bw_8822b(pDM_Odm, bandwidth); + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + phydm_dynamic_spur_det_elimitor(pDM_Odm); + + /* Modify CCA parameters */ + phydm_ccapar_by_bw_8822b(pDM_Odm, bandwidth); + phydm_ccapar_by_rfe_8822b(pDM_Odm); + + /* Toggle RX path to avoid RX dead zone issue */ + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0); + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (pDM_Odm->RXAntStatus|(pDM_Odm->RXAntStatus<<4))); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return TRUE; +} + +BOOLEAN +config_phydm_switch_channel_bw_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ) +{ + + /* Switch band */ + if (config_phydm_switch_band_8822b(pDM_Odm, central_ch) == FALSE) + return FALSE; + + /* Switch channel */ + if (config_phydm_switch_channel_8822b(pDM_Odm, central_ch) == FALSE) + return FALSE; + + /* Switch bandwidth */ + if (config_phydm_switch_bandwidth_8822b(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) + return FALSE; + + return TRUE; +} + +BOOLEAN +config_phydm_trx_mode_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ) +{ + BOOLEAN rf_reg_status = TRUE; + u1Byte IGI; + u4Byte rf_reg33 = 0; + u2Byte counter = 0; + + //PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + //PADAPTER pAdapter = pDM_Odm->Adapter; + //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n")); + + if (pDM_Odm->bDisablePhyApi) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n")); + return TRUE; + } + + if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", TxPath)); + return FALSE; + } + + if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", RxPath)); + return FALSE; + } + + /* RF mode of path-A and path-B */ + /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */ + if ((TxPath|RxPath) & ODM_RF_A) + ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x3231); + else + ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x1111); + + if ((TxPath|RxPath) & ODM_RF_B) + ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x3231); + else + ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x1111); + + /* Set TX antenna by Nsts */ + ODM_SetBBReg(pDM_Odm, 0x93c, (BIT19|BIT18), 0x3); + ODM_SetBBReg(pDM_Odm, 0x80c, (BIT29|BIT28), 0x1); + + /* Control CCK TX path by 0xa07[7] */ + ODM_SetBBReg(pDM_Odm, 0x80c, BIT30, 0x1); + + /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/ + if (TxPath & ODM_RF_A) { + ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x001); + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); + } else if (TxPath & ODM_RF_B) { + ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x002); + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); + } + + /* TX logic map and TX path en for Nsts = 2*/ + if ((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B)) + ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x01); + else + ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x43); + + /* TX path enable */ + ODM_SetBBReg(pDM_Odm, 0x80c, bMaskByte0, ((TxPath << 4)|TxPath)); + + /* Tx2path for 1ss */ + if (!((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))) { + if (bTx2Path || pDM_Odm->mp_mode) { + /* 2Tx for OFDM */ + ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x043); + + /* 2Tx for CCK */ + ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); + } + } + + /* Always disable MRC for CCK CCA */ + ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); + + /* Always disable MRC for CCK barker */ + ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); + + /* CCK RX 1st and 2nd path setting*/ + if (RxPath & ODM_RF_A) + ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x0); + else if (RxPath & ODM_RF_B) + ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x5); + + /* RX path enable */ + ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, ((RxPath << 4)|RxPath)); + + if ((RxPath == ODM_RF_A) || (RxPath == ODM_RF_B)) { + /* 1R */ + + /* Disable MRC for CCA */ + /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); */ + + /* Disable MRC for barker */ + /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); */ + + /* Disable CCK antenna diversity */ + /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ + + /* Disable Antenna weighting */ + ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x0); + ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x0); + ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x0); + } else { + /* 2R */ + + /* Enable MRC for CCA */ + /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x1); */ + + /* Enable MRC for barker */ + /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x1); */ + + /* Disable CCK antenna diversity */ + /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ + + /* Enable Antenna weighting */ + ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x1); + ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x1); + ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x1); + + /* AP only, L1 SBD change in 2R case */ + if (pDM_Odm->SupportPlatform == ODM_AP) { + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x171750E0); + } + } + + /* Update TXRX antenna status for PHYDM */ + pDM_Odm->TXAntStatus = (TxPath & 0x3); + pDM_Odm->RXAntStatus = (RxPath & 0x3); + + /* MP driver need to support path-B TX\RX */ + + while(1){ + counter++; + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); + + ODM_delay_us(2); + rf_reg33 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask); + + if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33))) + break; + else if (counter == 100) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n")); + return FALSE; + } + } + + if ((pDM_Odm->mp_mode) || (pDM_Odm->pAntennaTest) || (pDM_Odm->Normalrxpath)) { + /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e 0xef 0x00000 suggested by Lucas*/ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080e); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n")); + } else { + /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c 0xef 0x00000 */ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080c); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n")); + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); + + if (rf_reg_status == FALSE) { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", TxPath, RxPath)); + return FALSE; + } + + /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + //IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); + //ODM_Write_DIG(pDM_Odm, IGI - 2); + //ODM_Write_DIG(pDM_Odm, IGI); + + IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI); + + /* Modify CCA parameters */ + phydm_ccapar_by_rxpath_8822b(pDM_Odm); + phydm_ccapar_by_rfe_8822b(pDM_Odm); + phydm_rfe_8822b(pDM_Odm, central_ch_8822b); + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + phydm_dynamic_spur_det_elimitor(pDM_Odm); + + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath)); + return TRUE; +} + + +BOOLEAN +config_phydm_parameter_init( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ) +{ + if (type == ODM_PRE_SETTING) { + ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Pre setting: disable OFDM and CCK block\n")); + } else if (type == ODM_POST_SETTING) { + ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3); + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Post setting: enable OFDM and CCK block\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Wrong type!!\n")); + return FALSE; + } + + //phydm_set_iqgen_8822B(pDM_Odm); + return TRUE; +} + +/* ======================================================================== */ +#endif /* RTL8822B_SUPPORT == 1 */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.h b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.h index 47d58056ed6..807a8a5f1b9 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_hal_api8822b.h @@ -1,155 +1,155 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_PHYDM_API_H_8822B__ -#define __INC_PHYDM_API_H_8822B__ - -#if (RTL8822B_SUPPORT == 1) - -#define PHY_CONFIG_VERSION_8822B "28.5.34" /*2017.01.24 (HW user guide version: R28, SW user guide version: R05, Modification: R33)*/ - -#define INVALID_RF_DATA 0xffffffff -#define INVALID_TXAGC_DATA 0xff - -#define number_of_psd_value 5 -#define number_of_sample 3 -#define number_of_2g_freq_pt 14 -#define number_of_5g_freq_pt 10 - -#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA) -#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA) - -#define DEFAULT_AGC_TABLE 0 -#define LNA_SAT_AGC_TABLE 1 -#define AUTO_AGC_TABLE 2 - -u4Byte -config_phydm_read_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); - -BOOLEAN -config_phydm_write_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -BOOLEAN -config_phydm_write_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -u1Byte -config_phydm_read_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -VOID -phydm_dynamic_spur_det_elimitor( - IN PDM_ODM_T pDM_Odm - ); - -BOOLEAN -config_phydm_switch_band_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_channel_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_bandwidth_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_switch_channel_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_trx_mode_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ); - -BOOLEAN -config_phydm_parameter_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ); - - -/* ======================================================================== */ -/* These following functions can be used for PHY DM only*/ - -BOOLEAN -phydm_write_txagc_1byte_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -VOID -phydm_init_hw_info_by_rfe_type_8822b( - IN PDM_ODM_T pDM_Odm - ); - -s4Byte -phydm_get_condition_number_8822B( - IN PDM_ODM_T pDM_Odm - ); - -BOOLEAN -config_phydm_switch_agc_tab_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN bool is_switch_sat_tab - ); - - -/* ======================================================================== */ - -#endif /* RTL8822B_SUPPORT == 1 */ -#endif /* __INC_PHYDM_API_H_8822B__ */ - - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_PHYDM_API_H_8822B__ +#define __INC_PHYDM_API_H_8822B__ + +#if (RTL8822B_SUPPORT == 1) + +#define PHY_CONFIG_VERSION_8822B "28.5.34" /*2017.01.24 (HW user guide version: R28, SW user guide version: R05, Modification: R33)*/ + +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff + +#define number_of_psd_value 5 +#define number_of_sample 3 +#define number_of_2g_freq_pt 14 +#define number_of_5g_freq_pt 10 + +#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA) +#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA) + +#define DEFAULT_AGC_TABLE 0 +#define LNA_SAT_AGC_TABLE 1 +#define AUTO_AGC_TABLE 2 + +u4Byte +config_phydm_read_rf_reg_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +BOOLEAN +config_phydm_write_rf_reg_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E RFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +BOOLEAN +config_phydm_write_txagc_8822b( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +u1Byte +config_phydm_read_txagc_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +VOID +phydm_dynamic_spur_det_elimitor( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +config_phydm_switch_band_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_channel_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch + ); + +BOOLEAN +config_phydm_switch_bandwidth_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_switch_channel_bw_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN u1Byte primary_ch_idx, + IN ODM_BW_E bandwidth + ); + +BOOLEAN +config_phydm_trx_mode_8822b( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_PATH_E TxPath, + IN ODM_RF_PATH_E RxPath, + IN BOOLEAN bTx2Path + ); + +BOOLEAN +config_phydm_parameter_init( + IN PDM_ODM_T pDM_Odm, + IN ODM_PARAMETER_INIT_E type + ); + + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +BOOLEAN +phydm_write_txagc_1byte_8822b( + IN PDM_ODM_T pDM_Odm, + IN u4Byte PowerIndex, + IN ODM_RF_RADIO_PATH_E Path, + IN u1Byte HwRate + ); + +VOID +phydm_init_hw_info_by_rfe_type_8822b( + IN PDM_ODM_T pDM_Odm + ); + +s4Byte +phydm_get_condition_number_8822B( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +config_phydm_switch_agc_tab_8822b( + IN PDM_ODM_T pDM_Odm, + IN u1Byte central_ch, + IN bool is_switch_sat_tab + ); + + +/* ======================================================================== */ + +#endif /* RTL8822B_SUPPORT == 1 */ +#endif /* __INC_PHYDM_API_H_8822B__ */ + + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_iqk_8822b.h b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_iqk_8822b.h index 5cf68a4a5b5..7415801e774 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_iqk_8822b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_iqk_8822b.h @@ -1,74 +1,74 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __PHYDM_IQK_8822B_H__ -#define __PHYDM_IQK_8822B_H__ - -#if (RTL8822B_SUPPORT == 1) - - -/*--------------------------Define Parameters-------------------------------*/ -#define MAC_REG_NUM_8822B 2 -#define BB_REG_NUM_8822B 14 -#define RF_REG_NUM_8822B 5 - - -#define LOK_delay_8822B 2 -#define GS_delay_8822B 2 -#define WBIQK_delay_8822B 2 - -#define TXIQK 0 -#define RXIQK 1 -#define SS_8822B 2 - -/*---------------------------End Define Parameters-------------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#else -VOID -DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#endif - -VOID -PHY_IQCalibrate_8822B( - IN PVOID pDM_VOID, - IN BOOLEAN clear - ); - -#else /* (RTL8822B_SUPPORT == 0)*/ - -#define PHY_IQCalibrate_8822B(_pDM_VOID, clear) - -#endif /* RTL8822B_SUPPORT */ - - #endif /* #ifndef __PHYDM_IQK_8822B_H__*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDM_IQK_8822B_H__ +#define __PHYDM_IQK_8822B_H__ + +#if (RTL8822B_SUPPORT == 1) + + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8822B 2 +#define BB_REG_NUM_8822B 14 +#define RF_REG_NUM_8822B 5 + + +#define LOK_delay_8822B 2 +#define GS_delay_8822B 2 +#define WBIQK_delay_8822B 2 + +#define TXIQK 0 +#define RXIQK 1 +#define SS_8822B 2 + +/*---------------------------End Define Parameters-------------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +VOID +DoIQK_8822B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#else +VOID +DoIQK_8822B( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); +#endif + +VOID +PHY_IQCalibrate_8822B( + IN PVOID pDM_VOID, + IN BOOLEAN clear + ); + +#else /* (RTL8822B_SUPPORT == 0)*/ + +#define PHY_IQCalibrate_8822B(_pDM_VOID, clear) + +#endif /* RTL8822B_SUPPORT */ + + #endif /* #ifndef __PHYDM_IQK_8822B_H__*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.c b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.c index 3be8640b0b5..de6f7e625e3 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.c @@ -1,217 +1,217 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - -void -odm_ConfigRFReg_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) -{ - if ((Addr == 0xfe) || (Addr == 0xffe)) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - } -} - -void -odm_ConfigRF_RadioA_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1000; /* RF_Content: radioa_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigRF_RadioB_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) -{ - u4Byte content = 0x1001; /* RF_Content: radiob_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); - - odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigMAC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) -{ - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_UpdateAgcBigJumpLmt_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -) -{ - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte rfGainIdx = (u1Byte)((Data & 0xFF000000) >> 24); - u1Byte bbGainIdx = (u1Byte)((Data & 0x00ff0000) >> 16); - u1Byte agcTableIdx = (u1Byte)((Data & 0x00000f00) >> 8); - static BOOLEAN isLimit; - - if (Addr != 0x81c) - return; - - /*DbgPrint("Data = 0x%x, rfGainIdx = 0x%x, bbGainIdx = 0x%x, agcTableIdx = 0x%d\n", Data, rfGainIdx, bbGainIdx, agcTableIdx);*/ - /*DbgPrint("rfGainIdx = 0x%x, pDM_DigTable->rfGainIdx = 0x%x\n", rfGainIdx, pDM_DigTable->rfGainIdx);*/ - - if (bbGainIdx > 0x3c) { - if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { - isLimit = TRUE; - pDM_DigTable->bigJumpLmt[agcTableIdx] = bbGainIdx - 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", agcTableIdx, pDM_DigTable->bigJumpLmt[agcTableIdx])); - } - } else - isLimit = FALSE; - - pDM_DigTable->rfGainIdx = rfGainIdx; - -} - -void -odm_ConfigBB_AGC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - odm_UpdateAgcBigJumpLmt_8822B(pDM_Odm, Addr, Data); - - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_PHY_REG_PG_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - } else { -#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); -#endif - - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); -} - -void -odm_ConfigBB_PHY_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); -} - -void -odm_ConfigBB_TXPWR_LMT_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); -#endif -} - -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) + +void +odm_ConfigRFReg_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if ((Addr == 0xfe) || (Addr == 0xffe)) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void +odm_ConfigRF_RadioA_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; /* RF_Content: radioa_txt */ + u4Byte maskforPhySet = (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; /* RF_Content: radiob_txt */ + u4Byte maskforPhySet = (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigMAC_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_UpdateAgcBigJumpLmt_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte rfGainIdx = (u1Byte)((Data & 0xFF000000) >> 24); + u1Byte bbGainIdx = (u1Byte)((Data & 0x00ff0000) >> 16); + u1Byte agcTableIdx = (u1Byte)((Data & 0x00000f00) >> 8); + static BOOLEAN isLimit; + + if (Addr != 0x81c) + return; + + /*DbgPrint("Data = 0x%x, rfGainIdx = 0x%x, bbGainIdx = 0x%x, agcTableIdx = 0x%d\n", Data, rfGainIdx, bbGainIdx, agcTableIdx);*/ + /*DbgPrint("rfGainIdx = 0x%x, pDM_DigTable->rfGainIdx = 0x%x\n", rfGainIdx, pDM_DigTable->rfGainIdx);*/ + + if (bbGainIdx > 0x3c) { + if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { + isLimit = TRUE; + pDM_DigTable->bigJumpLmt[agcTableIdx] = bbGainIdx - 2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", agcTableIdx, pDM_DigTable->bigJumpLmt[agcTableIdx])); + } + } else + isLimit = FALSE; + + pDM_DigTable->rfGainIdx = rfGainIdx; + +} + +void +odm_ConfigBB_AGC_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + odm_UpdateAgcBigJumpLmt_8822B(pDM_Odm, Addr, Data); + + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe || Addr == 0xffe) { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } else { +#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8822B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.h b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.h index 4f1fca19d3b..894ddf88f55 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_regconfig8822b.h @@ -1,103 +1,103 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_ODM_REGCONFIG_H_8822B -#define __INC_ODM_REGCONFIG_H_8822B - -#if (RTL8822B_SUPPORT == 1) - -void -odm_ConfigRFReg_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); - -void -odm_ConfigRF_RadioA_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigRF_RadioB_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); - -void -odm_ConfigMAC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); - -void -odm_UpdateAgcBigJumpLmt_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data -); - -void -odm_ConfigBB_AGC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_REG_PG_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_PHY_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); - -void -odm_ConfigBB_TXPWR_LMT_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); - -#endif -#endif /* RTL8822B_SUPPORT == 1*/ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8822B +#define __INC_ODM_REGCONFIG_H_8822B + +#if (RTL8822B_SUPPORT == 1) + +void +odm_ConfigRFReg_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_UpdateAgcBigJumpLmt_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data +); + +void +odm_ConfigBB_AGC_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8822B( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8822B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif /* RTL8822B_SUPPORT == 1*/ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.c b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.c index 77cdc2e5990..24ec180b434 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.c +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.c @@ -1,92 +1,92 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================ -// include files -============================================================*/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - - -VOID -phydm_dynamic_switch_htstf_mumimo_8822b( - IN PDM_ODM_T pDM_Odm - ) -{ - /*if rssi > 40dBm, enable HT-STF gain controller, otherwise, if rssi < 40dBm, disable the controller*/ - /*add by Chun-Hung Ho 20160711 */ - if (pDM_Odm->RSSI_Min >= 40) - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT17, 0x1); - else if (pDM_Odm->RSSI_Min < 35) - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT17, 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s, RSSI_Min = %d\n", __func__, pDM_Odm->RSSI_Min)); -} - -VOID -phydm_somlrxhp_setting( - IN PDM_ODM_T pDM_Odm, - BOOLEAN switch_soml -) -{ - if (switch_soml == TRUE) { - ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xd90a0000); - /* Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */ - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT21|BIT18), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT21|BIT18), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0x090a0000); - ODM_SetBBReg(pDM_Odm, 0xc04, (BIT21|BIT18), 0x0); - ODM_SetBBReg(pDM_Odm, 0xe04, (BIT21|BIT18), 0x0); - } - - /* Dynamic RxHP setting with SoML on/off apply on all RFE type */ - if ((switch_soml == FALSE) && ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9))) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } - - if (*pDM_Odm->pChannel <= 14) { - if ((switch_soml == TRUE) && (!((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8)))) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } - } else if (*pDM_Odm->pChannel > 35) { - if (switch_soml == TRUE) { - ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); - ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); - } - } - -} - -VOID -phydm_hwsetting_8822b( - IN PDM_ODM_T pDM_Odm - ) -{ - phydm_dynamic_switch_htstf_mumimo_8822b(pDM_Odm); -} - -#endif /* RTL8822B_SUPPORT == 1 */ - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ +// include files +============================================================*/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) + + +VOID +phydm_dynamic_switch_htstf_mumimo_8822b( + IN PDM_ODM_T pDM_Odm + ) +{ + /*if rssi > 40dBm, enable HT-STF gain controller, otherwise, if rssi < 40dBm, disable the controller*/ + /*add by Chun-Hung Ho 20160711 */ + if (pDM_Odm->RSSI_Min >= 40) + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT17, 0x1); + else if (pDM_Odm->RSSI_Min < 35) + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT17, 0x0); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s, RSSI_Min = %d\n", __func__, pDM_Odm->RSSI_Min)); +} + +VOID +phydm_somlrxhp_setting( + IN PDM_ODM_T pDM_Odm, + BOOLEAN switch_soml +) +{ + if (switch_soml == TRUE) { + ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xd90a0000); + /* Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */ + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT21|BIT18), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT21|BIT18), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0x090a0000); + ODM_SetBBReg(pDM_Odm, 0xc04, (BIT21|BIT18), 0x0); + ODM_SetBBReg(pDM_Odm, 0xe04, (BIT21|BIT18), 0x0); + } + + /* Dynamic RxHP setting with SoML on/off apply on all RFE type */ + if ((switch_soml == FALSE) && ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7) || (pDM_Odm->RFEType == 9))) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } + + if (*pDM_Odm->pChannel <= 14) { + if ((switch_soml == TRUE) && (!((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5) || (pDM_Odm->RFEType == 8)))) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } + } else if (*pDM_Odm->pChannel > 35) { + if (switch_soml == TRUE) { + ODM_SetBBReg(pDM_Odm, 0x8cc, bMaskDWord, 0x08108000); + ODM_SetBBReg(pDM_Odm, 0x8d8, BIT27, 0x0); + } + } + +} + +VOID +phydm_hwsetting_8822b( + IN PDM_ODM_T pDM_Odm + ) +{ + phydm_dynamic_switch_htstf_mumimo_8822b(pDM_Odm); +} + +#endif /* RTL8822B_SUPPORT == 1 */ + diff --git a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.h b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.h index 3c2a59317f4..9203867ba6f 100644 --- a/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.h +++ b/package/kernel/rtl8192cd/phydm/rtl8822b/phydm_rtl8822b.h @@ -1,37 +1,37 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __ODM_RTL8822B_H__ -#define __ODM_RTL8822B_H__ - -VOID -phydm_somlrxhp_setting( - IN PDM_ODM_T pDM_Odm, - BOOLEAN switch_soml -); - -VOID -phydm_hwsetting_8822b( - IN PDM_ODM_T pDM_Odm -); - -#endif /* #define __ODM_RTL8822B_H__ */ -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#if (RTL8822B_SUPPORT == 1) +#ifndef __ODM_RTL8822B_H__ +#define __ODM_RTL8822B_H__ + +VOID +phydm_somlrxhp_setting( + IN PDM_ODM_T pDM_Odm, + BOOLEAN switch_soml +); + +VOID +phydm_hwsetting_8822b( + IN PDM_ODM_T pDM_Odm +); + +#endif /* #define __ODM_RTL8822B_H__ */ +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.c b/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.c index 59ec2e7aed0..2843ed133ca 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.c +++ b/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.c @@ -1,538 +1,538 @@ -//============================================================ -// Description: -// -// This file is for TXBF mechanism -// -//============================================================ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -/*Beamforming halcomtxbf API create by YuChen 2015/05*/ - -VOID -halComTxbf_beamformInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Init(pDM_Odm); -} - -/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -VOID -halComTxbf_ConfigGtab( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_ConfigGtab(pDM_Odm); -} - -VOID -phydm_beamformSetSoundingEnter( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_EnterWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_EnterWorkItem)); -#else - halComTxbf_EnterWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetSoundingLeave( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_LeaveWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_LeaveWorkItem)); -#else - halComTxbf_LeaveWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetSoundingRate( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_RateWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_RateWorkItem)); -#else - halComTxbf_RateWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetSoundingStatus( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_StatusWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_StatusWorkItem)); -#else - halComTxbf_StatusWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetSoundingFwNdpa( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (*pDM_Odm->pbFwDwRsvdPageInProgress) - ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); - else - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); -#else - halComTxbf_FwNdpaWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetSoundingClk( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ClkWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ClkWorkItem)); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER padapter = pDM_Odm->Adapter; - - rtw_run_in_thread_cmd(padapter, halComTxbf_ClkWorkItemCallback, padapter); -#else - halComTxbf_ClkWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetResetTxPath( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)); -#else - halComTxbf_ResetTxPathWorkItemCallback(pDM_Odm); -#endif -} - -VOID -phydm_beamformSetGetTxRate( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_GetTxRateWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_GetTxRateWorkItem)); -#else - halComTxbf_GetTxRateWorkItemCallback(pDM_Odm); -#endif -} - -VOID -halComTxbf_EnterWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte Idx = pTxbfInfo->TXBFIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Enter(pDM_Odm, Idx); -} - -VOID -halComTxbf_LeaveWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - u1Byte Idx = pTxbfInfo->TXBFIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Leave(pDM_Odm, Idx); -} - - -VOID -halComTxbf_FwNdpaWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte Idx = pTxbfInfo->NdpaIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_FwTxBF(pDM_Odm, Idx); -} - -VOID -halComTxbf_ClkWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & ODM_RTL8812) - HalTxbfJaguar_Clk_8812A(pDM_Odm); -} - - - -VOID -halComTxbf_RateWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte BW = pTxbfInfo->BW; - u1Byte Rate = pTxbfInfo->Rate; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & ODM_RTL8812) - HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate); - -} - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -halComTxbf_FwNdpaTimerCallback( - IN PRT_TIMER pTimer - ) -{ - - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (*pDM_Odm->pbFwDwRsvdPageInProgress) - ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); - else - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); -} -#endif - - -VOID -halComTxbf_StatusWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - u1Byte Idx = pTxbfInfo->TXBFIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Status(pDM_Odm, Idx); -} - -VOID -halComTxbf_ResetTxPathWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - u1Byte Idx = pTxbfInfo->TXBFIdx; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_ResetTxPath(pDM_Odm, Idx); - -} - -VOID -halComTxbf_GetTxRateWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#endif - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_GetTxRate(pDM_Odm); -} - - -BOOLEAN -HalComTxbf_Set( - IN PVOID pDM_VOID, - IN u1Byte setType, - IN PVOID pInBuf - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pu1Byte pU1Tmp=(pu1Byte)pInBuf; - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] setType = 0x%X\n", __func__, setType)); - - switch(setType){ - case TXBF_SET_SOUNDING_ENTER: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingEnter(pDM_Odm); - break; - - case TXBF_SET_SOUNDING_LEAVE: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingLeave(pDM_Odm); - break; - - case TXBF_SET_SOUNDING_RATE: - pTxbfInfo->BW = pU1Tmp[0]; - pTxbfInfo->Rate = pU1Tmp[1]; - phydm_beamformSetSoundingRate(pDM_Odm); - break; - - case TXBF_SET_SOUNDING_STATUS: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingStatus(pDM_Odm); - break; - - case TXBF_SET_SOUNDING_FW_NDPA: - pTxbfInfo->NdpaIdx = *pU1Tmp; - phydm_beamformSetSoundingFwNdpa(pDM_Odm); - break; - - case TXBF_SET_SOUNDING_CLK: - phydm_beamformSetSoundingClk(pDM_Odm); - break; - - case TXBF_SET_TX_PATH_RESET: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetResetTxPath(pDM_Odm); - break; - - case TXBF_SET_GET_TX_RATE: - phydm_beamformSetGetTxRate(pDM_Odm); - break; - - } - - return TRUE; -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -BOOLEAN -HalComTxbf_Get( - IN PADAPTER Adapter, - IN u1Byte getType, - OUT PVOID pOutBuf - ) -{ - PHAL_DATA_TYPE pHalData=GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PBOOLEAN pBoolean=(PBOOLEAN)pOutBuf; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (getType == TXBF_GET_EXPLICIT_BEAMFORMEE) { - if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) - *pBoolean = FALSE; - else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ - IS_HARDWARE_TYPE_8821B(Adapter) || - IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) - *pBoolean = TRUE; - else - *pBoolean = FALSE; - } else if (getType == TXBF_GET_EXPLICIT_BEAMFORMER) { - if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) - *pBoolean = FALSE; - else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ - IS_HARDWARE_TYPE_8821B(Adapter) || - IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { - if(pHalData->RF_Type == RF_2T2R || pHalData->RF_Type == RF_3T3R) - *pBoolean = TRUE; - else - *pBoolean = FALSE; - } else - *pBoolean = FALSE; - } else if (getType == TXBF_GET_MU_MIMO_STA) { -#if (RTL8822B_SUPPORT == 1) - if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ - IS_HARDWARE_TYPE_8822B(Adapter)) - *pBoolean = TRUE; - else -#endif - *pBoolean = FALSE; - - - } else if (getType == TXBF_GET_MU_MIMO_AP) { -#if (RTL8822B_SUPPORT == 1) - if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ - IS_HARDWARE_TYPE_8822B(Adapter)) - *pBoolean = TRUE; - else -#endif - *pBoolean = FALSE; - } - - return TRUE; -} -#endif - - -#endif - +//============================================================ +// Description: +// +// This file is for TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +/*Beamforming halcomtxbf API create by YuChen 2015/05*/ + +VOID +halComTxbf_beamformInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Init(pDM_Odm); +} + +/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ +VOID +halComTxbf_ConfigGtab( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_ConfigGtab(pDM_Odm); +} + +VOID +phydm_beamformSetSoundingEnter( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_EnterWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_EnterWorkItem)); +#else + halComTxbf_EnterWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingLeave( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_LeaveWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_LeaveWorkItem)); +#else + halComTxbf_LeaveWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingRate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_RateWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_RateWorkItem)); +#else + halComTxbf_RateWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingStatus( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_StatusWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_StatusWorkItem)); +#else + halComTxbf_StatusWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingFwNdpa( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (*pDM_Odm->pbFwDwRsvdPageInProgress) + ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + else + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); +#else + halComTxbf_FwNdpaWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingClk( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ClkWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ClkWorkItem)); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER padapter = pDM_Odm->Adapter; + + rtw_run_in_thread_cmd(padapter, halComTxbf_ClkWorkItemCallback, padapter); +#else + halComTxbf_ClkWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetResetTxPath( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)); +#else + halComTxbf_ResetTxPathWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetGetTxRate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_GetTxRateWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_GetTxRateWorkItem)); +#else + halComTxbf_GetTxRateWorkItemCallback(pDM_Odm); +#endif +} + +VOID +halComTxbf_EnterWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Enter(pDM_Odm, Idx); +} + +VOID +halComTxbf_LeaveWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Leave(pDM_Odm, Idx); +} + + +VOID +halComTxbf_FwNdpaWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte Idx = pTxbfInfo->NdpaIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_FwTxBF(pDM_Odm, Idx); +} + +VOID +halComTxbf_ClkWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & ODM_RTL8812) + HalTxbfJaguar_Clk_8812A(pDM_Odm); +} + + + +VOID +halComTxbf_RateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte BW = pTxbfInfo->BW; + u1Byte Rate = pTxbfInfo->Rate; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & ODM_RTL8812) + HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate); + +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +halComTxbf_FwNdpaTimerCallback( + IN PRT_TIMER pTimer + ) +{ + + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (*pDM_Odm->pbFwDwRsvdPageInProgress) + ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + else + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); +} +#endif + + +VOID +halComTxbf_StatusWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Status(pDM_Odm, Idx); +} + +VOID +halComTxbf_ResetTxPathWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_ResetTxPath(pDM_Odm, Idx); + +} + +VOID +halComTxbf_GetTxRateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_GetTxRate(pDM_Odm); +} + + +BOOLEAN +HalComTxbf_Set( + IN PVOID pDM_VOID, + IN u1Byte setType, + IN PVOID pInBuf + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pu1Byte pU1Tmp=(pu1Byte)pInBuf; + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] setType = 0x%X\n", __func__, setType)); + + switch(setType){ + case TXBF_SET_SOUNDING_ENTER: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingEnter(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_LEAVE: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingLeave(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_RATE: + pTxbfInfo->BW = pU1Tmp[0]; + pTxbfInfo->Rate = pU1Tmp[1]; + phydm_beamformSetSoundingRate(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_STATUS: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingStatus(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_FW_NDPA: + pTxbfInfo->NdpaIdx = *pU1Tmp; + phydm_beamformSetSoundingFwNdpa(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_CLK: + phydm_beamformSetSoundingClk(pDM_Odm); + break; + + case TXBF_SET_TX_PATH_RESET: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetResetTxPath(pDM_Odm); + break; + + case TXBF_SET_GET_TX_RATE: + phydm_beamformSetGetTxRate(pDM_Odm); + break; + + } + + return TRUE; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +BOOLEAN +HalComTxbf_Get( + IN PADAPTER Adapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ) +{ + PHAL_DATA_TYPE pHalData=GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PBOOLEAN pBoolean=(PBOOLEAN)pOutBuf; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (getType == TXBF_GET_EXPLICIT_BEAMFORMEE) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) + *pBoolean = FALSE; + else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ + IS_HARDWARE_TYPE_8821B(Adapter) || + IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) + *pBoolean = TRUE; + else + *pBoolean = FALSE; + } else if (getType == TXBF_GET_EXPLICIT_BEAMFORMER) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) + *pBoolean = FALSE; + else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ + IS_HARDWARE_TYPE_8821B(Adapter) || + IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + if(pHalData->RF_Type == RF_2T2R || pHalData->RF_Type == RF_3T3R) + *pBoolean = TRUE; + else + *pBoolean = FALSE; + } else + *pBoolean = FALSE; + } else if (getType == TXBF_GET_MU_MIMO_STA) { +#if (RTL8822B_SUPPORT == 1) + if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ + IS_HARDWARE_TYPE_8822B(Adapter)) + *pBoolean = TRUE; + else +#endif + *pBoolean = FALSE; + + + } else if (getType == TXBF_GET_MU_MIMO_AP) { +#if (RTL8822B_SUPPORT == 1) + if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ + IS_HARDWARE_TYPE_8822B(Adapter)) + *pBoolean = TRUE; + else +#endif + *pBoolean = FALSE; + } + + return TRUE; +} +#endif + + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.h b/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.h index abb9d594faf..7be4efd17d6 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.h +++ b/package/kernel/rtl8192cd/phydm/txbf/halcomtxbf.h @@ -1,181 +1,181 @@ -#ifndef __HAL_COM_TXBF_H__ -#define __HAL_COM_TXBF_H__ - -/* -typedef BOOLEAN -(*TXBF_GET)( - IN PVOID pAdapter, - IN u1Byte getType, - OUT PVOID pOutBuf - ); - -typedef BOOLEAN -(*TXBF_SET)( - IN PVOID pAdapter, - IN u1Byte setType, - OUT PVOID pInBuf - ); -*/ -#define TxBF_Nr(a, b) ((a > b) ? (b) : (a)) - -typedef enum _TXBF_SET_TYPE{ - TXBF_SET_SOUNDING_ENTER, - TXBF_SET_SOUNDING_LEAVE, - TXBF_SET_SOUNDING_RATE, - TXBF_SET_SOUNDING_STATUS, - TXBF_SET_SOUNDING_FW_NDPA, - TXBF_SET_SOUNDING_CLK, - TXBF_SET_TX_PATH_RESET, - TXBF_SET_GET_TX_RATE -}TXBF_SET_TYPE,*PTXBF_SET_TYPE; - - -typedef enum _TXBF_GET_TYPE{ - TXBF_GET_EXPLICIT_BEAMFORMEE, - TXBF_GET_EXPLICIT_BEAMFORMER, - TXBF_GET_MU_MIMO_STA, - TXBF_GET_MU_MIMO_AP -}TXBF_GET_TYPE,*PTXBF_GET_TYPE; - - - -//2 HAL TXBF related -typedef struct _HAL_TXBF_INFO { - u1Byte TXBFIdx; - u1Byte NdpaIdx; - u1Byte BW; - u1Byte Rate; - - RT_TIMER Txbf_FwNdpaTimer; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM Txbf_EnterWorkItem; - RT_WORK_ITEM Txbf_LeaveWorkItem; - RT_WORK_ITEM Txbf_FwNdpaWorkItem; - RT_WORK_ITEM Txbf_ClkWorkItem; - RT_WORK_ITEM Txbf_StatusWorkItem; - RT_WORK_ITEM Txbf_RateWorkItem; - RT_WORK_ITEM Txbf_ResetTxPathWorkItem; - RT_WORK_ITEM Txbf_GetTxRateWorkItem; -#endif - -} HAL_TXBF_INFO, *PHAL_TXBF_INFO; - -#if (BEAMFORMING_SUPPORT == 1) - -VOID -halComTxbf_beamformInit( - IN PVOID pDM_VOID - ); - -VOID -halComTxbf_ConfigGtab( - IN PVOID pDM_VOID - ); - -VOID -halComTxbf_EnterWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_LeaveWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_FwNdpaWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_ClkWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_ResetTxPathWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_GetTxRateWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_RateWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -VOID -halComTxbf_FwNdpaTimerCallback( - IN PRT_TIMER pTimer - ); - -VOID -halComTxbf_StatusWorkItemCallback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter -#else - IN PVOID pDM_VOID -#endif - ); - -BOOLEAN -HalComTxbf_Set( - IN PVOID pDM_VOID, - IN u1Byte setType, - IN PVOID pInBuf - ); - -BOOLEAN -HalComTxbf_Get( - IN PADAPTER Adapter, - IN u1Byte getType, - OUT PVOID pOutBuf - ); - -#else -#define halComTxbf_beamformInit(pDM_VOID) NULL -#define halComTxbf_ConfigGtab(pDM_VOID) NULL -#define halComTxbf_EnterWorkItemCallback(_Adapter) NULL -#define halComTxbf_LeaveWorkItemCallback(_Adapter) NULL -#define halComTxbf_FwNdpaWorkItemCallback(_Adapter) NULL -#define halComTxbf_ClkWorkItemCallback(_Adapter) NULL -#define halComTxbf_RateWorkItemCallback(_Adapter) NULL -#define halComTxbf_FwNdpaTimerCallback(_Adapter) NULL -#define halComTxbf_StatusWorkItemCallback(_Adapter) NULL -#define HalComTxbf_Get(_Adapter, _getType, _pOutBuf) - -#endif - -#endif // #ifndef __HAL_COM_TXBF_H__ - +#ifndef __HAL_COM_TXBF_H__ +#define __HAL_COM_TXBF_H__ + +/* +typedef BOOLEAN +(*TXBF_GET)( + IN PVOID pAdapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +typedef BOOLEAN +(*TXBF_SET)( + IN PVOID pAdapter, + IN u1Byte setType, + OUT PVOID pInBuf + ); +*/ +#define TxBF_Nr(a, b) ((a > b) ? (b) : (a)) + +typedef enum _TXBF_SET_TYPE{ + TXBF_SET_SOUNDING_ENTER, + TXBF_SET_SOUNDING_LEAVE, + TXBF_SET_SOUNDING_RATE, + TXBF_SET_SOUNDING_STATUS, + TXBF_SET_SOUNDING_FW_NDPA, + TXBF_SET_SOUNDING_CLK, + TXBF_SET_TX_PATH_RESET, + TXBF_SET_GET_TX_RATE +}TXBF_SET_TYPE,*PTXBF_SET_TYPE; + + +typedef enum _TXBF_GET_TYPE{ + TXBF_GET_EXPLICIT_BEAMFORMEE, + TXBF_GET_EXPLICIT_BEAMFORMER, + TXBF_GET_MU_MIMO_STA, + TXBF_GET_MU_MIMO_AP +}TXBF_GET_TYPE,*PTXBF_GET_TYPE; + + + +//2 HAL TXBF related +typedef struct _HAL_TXBF_INFO { + u1Byte TXBFIdx; + u1Byte NdpaIdx; + u1Byte BW; + u1Byte Rate; + + RT_TIMER Txbf_FwNdpaTimer; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM Txbf_EnterWorkItem; + RT_WORK_ITEM Txbf_LeaveWorkItem; + RT_WORK_ITEM Txbf_FwNdpaWorkItem; + RT_WORK_ITEM Txbf_ClkWorkItem; + RT_WORK_ITEM Txbf_StatusWorkItem; + RT_WORK_ITEM Txbf_RateWorkItem; + RT_WORK_ITEM Txbf_ResetTxPathWorkItem; + RT_WORK_ITEM Txbf_GetTxRateWorkItem; +#endif + +} HAL_TXBF_INFO, *PHAL_TXBF_INFO; + +#if (BEAMFORMING_SUPPORT == 1) + +VOID +halComTxbf_beamformInit( + IN PVOID pDM_VOID + ); + +VOID +halComTxbf_ConfigGtab( + IN PVOID pDM_VOID + ); + +VOID +halComTxbf_EnterWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_LeaveWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_FwNdpaWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_ClkWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_ResetTxPathWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_GetTxRateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_RateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_FwNdpaTimerCallback( + IN PRT_TIMER pTimer + ); + +VOID +halComTxbf_StatusWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +BOOLEAN +HalComTxbf_Set( + IN PVOID pDM_VOID, + IN u1Byte setType, + IN PVOID pInBuf + ); + +BOOLEAN +HalComTxbf_Get( + IN PADAPTER Adapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +#else +#define halComTxbf_beamformInit(pDM_VOID) NULL +#define halComTxbf_ConfigGtab(pDM_VOID) NULL +#define halComTxbf_EnterWorkItemCallback(_Adapter) NULL +#define halComTxbf_LeaveWorkItemCallback(_Adapter) NULL +#define halComTxbf_FwNdpaWorkItemCallback(_Adapter) NULL +#define halComTxbf_ClkWorkItemCallback(_Adapter) NULL +#define halComTxbf_RateWorkItemCallback(_Adapter) NULL +#define halComTxbf_FwNdpaTimerCallback(_Adapter) NULL +#define halComTxbf_StatusWorkItemCallback(_Adapter) NULL +#define HalComTxbf_Get(_Adapter, _getType, _pOutBuf) + +#endif + +#endif // #ifndef __HAL_COM_TXBF_H__ + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.c b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.c index 778eb919d59..073dfdc369a 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.c +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.c @@ -1,392 +1,392 @@ -//============================================================ -// Description: -// -// This file is for 8192E TXBF mechanism -// -//============================================================ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8192E_SUPPORT == 1) - -VOID -HalTxbf8192E_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW)); - -} - -VOID -halTxbf8192E_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->RFType == ODM_1T1R) - return; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ - - if (pBeamInfo->beamformee_su_cnt > 0) { - /*Path_A*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ - /*Path_B*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ - } else { - /*Path_A*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ - /*Path_B*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ - } - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ - - if (pBeamInfo->beamformee_su_cnt > 0) { - ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1); - } else - ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313); -} - - - -VOID -halTxbf8192E_FwTxBFCmd( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period0 = 0, Period1 = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (Idx == 0) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) - PageNum0 = 0xFE; - else - PageNum0 = 0xFF; //stop sounding - Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (Idx == 1) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) - PageNum1 = 0xFE; - else - PageNum1 = 0xFF; //stop sounding - Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } - } - } - - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = (Period1 << 4) | Period0; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); -} - - -VOID -halTxbf8192E_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - BOOLEAN bSendBeacon = FALSE; - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; - /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; -#endif - if (Idx == 0) - Head_Page = 0xFE; - else - Head_Page = 0xFE; - - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); - - /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); - ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0)); - - /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6)); - - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__)); - bSendBeacon = TRUE; - } - - /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page); - - do { - /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0)); - - // download NDPA rsvd page. - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); - -#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); - count = 0; - while ((count < 20) && (u1bTmp & BIT4)) { - count++; - ODM_delay_us(10); - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); - } - ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4); -#endif - - /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); - count = 0; - while (!(BcnValidReg & BIT0) && count < 20) { - count++; - ODM_delay_us(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); - } - DLBcnCount++; - } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); - - if (!(BcnValidReg & BIT0)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); - - /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy); - - /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ - /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ - /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422); - - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); - ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0))); - - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; -#endif -} - - -VOID -HalTxbf8192E_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u4Byte CSI_Param; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo); - - if (pDM_Odm->RFType == ODM_2T2R) - ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/ - - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; - - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB); - - /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]); - } else { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]); - } - - /*CSI report parameters of Beamformer Default use Nc = 2*/ - CSI_Param = 0x03090309; - - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param); - - /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); - - } - - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; - else - STAid = BeamformeeEntry.P_AID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid)); - - /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7); - } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15); - - /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { - /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9); - } else { - /*Set BIT25*/ - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200); - } - phydm_Beamforming_Notify(pDM_Odm); - - } -} - - -VOID -HalTxbf8192E_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - halTxbf8192E_RfMode(pDM_Odm, pBeamInfo); - - /* Clear P_AID of Beamformee - * Clear MAC addresss of Beamformer - * Clear Associated Bfmee Sel - */ - if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8); - - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0); - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000); - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx)); -} - - -VOID -HalTxbf8192E_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; - else - BeamCtrlVal = BeamformEntry.P_AID; - - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8192E; - else { - BeamCtrlReg = REG_TXBF_CTRL_8192E+2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; - } - - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= BIT10; - } else - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); - - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal)); -} - - -VOID -HalTxbf8192E_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8192E_DownloadNDPA(pDM_Odm, Idx); - - halTxbf8192E_FwTxBFCmd(pDM_Odm); -} - -#endif /* #if (RTL8192E_SUPPORT == 1)*/ - -#endif - +//============================================================ +// Description: +// +// This file is for 8192E TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8192E_SUPPORT == 1) + +VOID +HalTxbf8192E_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW)); + +} + +VOID +halTxbf8192E_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + } else { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1); + } else + ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313); +} + + + +VOID +halTxbf8192E_FwTxBFCmd( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx, Period0 = 0, Period1 = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (Idx == 0) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; //stop sounding + Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (Idx == 1) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; //stop sounding + Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = (Period1 << 4) | Period0; + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); +} + + +VOID +halTxbf8192E_DownloadNDPA( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + BOOLEAN bSendBeacon = FALSE; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; + /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; +#endif + if (Idx == 0) + Head_Page = 0xFE; + else + Head_Page = 0xFE; + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); + ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0)); + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__)); + bSendBeacon = TRUE; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0)); + + // download NDPA rsvd page. + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + +#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); + count = 0; + while ((count < 20) && (u1bTmp & BIT4)) { + count++; + ODM_delay_us(10); + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); + } + ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4); +#endif + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + count = 0; + while (!(BcnValidReg & BIT0) && count < 20) { + count++; + ODM_delay_us(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); + ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; +#endif +} + + +VOID +HalTxbf8192E_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo); + + if (pDM_Odm->RFType == ODM_2T2R) + ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/ + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + } + + /*CSI report parameters of Beamformer Default use Nc = 2*/ + CSI_Param = 0x03090309; + + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); + + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid)); + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9); + } else { + /*Set BIT25*/ + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200); + } + phydm_Beamforming_Notify(pDM_Odm); + + } +} + + +VOID +HalTxbf8192E_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + halTxbf8192E_RfMode(pDM_Odm, pBeamInfo); + + /* Clear P_AID of Beamformee + * Clear MAC addresss of Beamformer + * Clear Associated Bfmee Sel + */ + if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8); + + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0); + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000); + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx)); +} + + +VOID +HalTxbf8192E_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8192E; + else { + BeamCtrlReg = REG_TXBF_CTRL_8192E+2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= BIT10; + } else + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal)); +} + + +VOID +HalTxbf8192E_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8192E_DownloadNDPA(pDM_Odm, Idx); + + halTxbf8192E_FwTxBFCmd(pDM_Odm); +} + +#endif /* #if (RTL8192E_SUPPORT == 1)*/ + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.h b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.h index 406c2d6e06b..be70cc6569c 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.h +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8192e.h @@ -1,52 +1,52 @@ -#ifndef __HAL_TXBF_8192E_H__ -#define __HAL_TXBF_8192E_H__ - -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8192E_SUPPORT == 1) -VOID -HalTxbf8192E_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -); - -VOID -HalTxbf8192E_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8192E_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8192E_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8192E_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); -#else - -#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate) -#define HalTxbf8192E_Enter(pDM_VOID, Idx) -#define HalTxbf8192E_Leave(pDM_VOID, Idx) -#define HalTxbf8192E_Status(pDM_VOID, Idx) -#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx) - -#endif - -#endif - -#endif - +#ifndef __HAL_TXBF_8192E_H__ +#define __HAL_TXBF_8192E_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8192E_SUPPORT == 1) +VOID +HalTxbf8192E_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + +VOID +HalTxbf8192E_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); +#else + +#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate) +#define HalTxbf8192E_Enter(pDM_VOID, Idx) +#define HalTxbf8192E_Leave(pDM_VOID, Idx) +#define HalTxbf8192E_Status(pDM_VOID, Idx) +#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx) + +#endif + +#endif + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.c b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.c index 1c6670825f1..532a9703c98 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.c +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.c @@ -1,677 +1,677 @@ -//============================================================ -// Description: -// -// This file is for 8814A TXBF mechanism -// -//============================================================ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8814A_SUPPORT == 1) - -VOID -HalTxbf8814A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW); - ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate); - -} - -#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 -#define PHYDM_CTRL_INFO_PAGE 0x660 - -VOID -phydm_DataRate_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte macId, - OUT pu4Byte data, - IN u1Byte dataLen - ) -{ - u1Byte i = 0; - u2Byte XReadDataAddr = 0; - - ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); - XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/ - - if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr)); - return; - } - - /* Read data */ - for (i = 0; i < dataLen; i++) - *(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i); - -} - -VOID -HalTxbf8814A_GetTxRate( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pEntry; - u4Byte TxRptData = 0; - u1Byte DataRate = 0xFF; - - pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1); - DataRate = (u1Byte)TxRptData; - DataRate &= bMask7bits; /*Bit7 indicates SGI*/ - - pDM_Odm->TxBfDataRate = DataRate; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate)); -} - -VOID -HalTxbf8814A_ResetTxPath( - IN PVOID pDM_VOID, - IN u1Byte idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if DEV_BUS_TYPE == RT_USB_INTERFACE - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - u1Byte Nr_index = 0, txSS = 0; - - if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; - else - return; - - if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) { - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); - - if (*pDM_Odm->HubUsbMode == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - txSS = 0xf; - else if (pDM_Odm->RFType == ODM_3T3R) - txSS = 0xe; - else - txSS = 0x6; - } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ - txSS = 0x6; - else - txSS = 0x6; - - if (txSS == 0xf) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); - } else if (txSS == 0xe) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); - } else if (txSS == 0x6) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); - } - - if (idx == 0) { - switch (Nr_index) { - case 0: - break; - - case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; - - case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; - - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; - } - } else { - switch (Nr_index) { - case 0: - break; - - case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; - - case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; - - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; - } - } - - pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; - } else - return; -#endif -} - - -u1Byte -halTxbf8814A_GetNtx( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Ntx = 0, txSS = 3; - -#if DEV_BUS_TYPE == RT_USB_INTERFACE - txSS = *pDM_Odm->HubUsbMode; -#endif - if (txSS == 3 || txSS == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; - else - Ntx = 1; - } else if (txSS == 1) /*USB 2.0 always 2Tx*/ - Ntx = 1; - else - Ntx = 1; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx)); - return Ntx; -} - -u1Byte -halTxbf8814A_GetNrx( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nrx = 0; - - if (pDM_Odm->RFType == ODM_4T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T2R) - Nrx = 1; - else if (pDM_Odm->RFType == ODM_2T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_1T1R) - Nrx = 0; - else if (pDM_Odm->RFType == ODM_1T2R) - Nrx = 1; - else - Nrx = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx)); - return Nrx; -} - -VOID -halTxbf8814A_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamformingInfo, - IN u1Byte idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; - u1Byte txSS = 3; /*default use 3 Tx*/ - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; - else - return; - - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); - - if (pDM_Odm->RFType == ODM_1T1R) - return; - - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); - /*RF Mode table write enable*/ - } - - if (pBeamformingInfo->beamformee_su_cnt > 0) { - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); - /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); - /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); - /*Enable TXIQGEN in RX mode*/ - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); - /*Enable TXIQGEN in RX mode*/ - } - - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); - /*RF Mode table write disable*/ - } - - if (pBeamformingInfo->beamformee_su_cnt > 0) { -#if DEV_BUS_TYPE == RT_USB_INTERFACE - pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; - txSS = *pDM_Odm->HubUsbMode; -#endif - if (txSS == 3 || txSS == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - txSS = 0xf; - else if (pDM_Odm->RFType == ODM_3T3R) - txSS = 0xe; - else - txSS = 0x6; - } else if (txSS == 1) /*USB 2.0 always 2Tx*/ - txSS = 0x6; - else - txSS = 0x6; - - if (txSS == 0xf) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); - } else if (txSS == 0xe) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); - } else if (txSS == 0x6) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); - } - - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - - if (idx == 0) { - switch (Nr_index) { - case 0: - break; - - case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; - - case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; - - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - - break; - } - } else { - switch (Nr_index) { - case 0: - break; - - case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; - - case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; - - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; - } - } - } - - if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e9360); - } -} -#if 0 -VOID -halTxbf8814A_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - u2Byte Head_Page = 0x7FE; - BOOLEAN bSendBeacon = FALSE; - u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - PADAPTER Adapter = pDM_Odm->Adapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; -#endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); - - /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp | BIT0)); - - - /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6)); - - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an Adapter is sending beacon.\n", __func__)); - bSendBeacon = TRUE; - } - - /*0x204[11:0] Beacon Head for TXDMA*/ - ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); - - do { - /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7)); - - /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); - else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); - - /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); - count = 0; - while (!(BcnValidReg & BIT7) && count < 20) { - count++; - ODM_delay_ms(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 2); - } - DLBcnCount++; - } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); - - if (!(BcnValidReg & BIT7)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); - - /*0x204[11:0] Beacon Head for TXDMA*/ - ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); - - /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ - /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ - /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422); - - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp & (~BIT0))); - - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; -#endif -} - -VOID -halTxbf8814A_FwTxBFCmd( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) { - PageNum0 = 0xFE; - PageNum1 = 0x07; - Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (PageNum0 == 0xFF) { - PageNum0 = 0xFF; /*stop sounding*/ - PageNum1 = 0x0F; - } - } - } - - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = Period; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d, PageNum1 = %d Period = %d\n", __func__, PageNum0, PageNum1, Period)); -} -#endif -VOID -HalTxbf8814A_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0, CSI_Param = 0; - u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx)); - ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202); - - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB); - - /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]); - } else { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]); - } - - /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ - Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ - - grouping = 0; - - /*for ac = 1, for n = 3*/ - if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) - codebookinfo = 1; - else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) - codebookinfo = 3; - - coefficientsize = 3; - - CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index)); - - if (BFerIdx == 0) - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param); - else - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param); - /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); - - } - - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - - halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; - else - STAid = BeamformeeEntry.P_AID; - - /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); - } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12); - - /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { - /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9); - } else - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/ - - phydm_Beamforming_Notify(pDM_Odm); - } - -} - - -VOID -HalTxbf8814A_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMER_ENTRY BeamformerEntry; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; - } else - return; - - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ - - if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8); - if (Idx == 0) { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); - } else { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); - } - } - - if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx); - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12); - - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); - } - } -} - -VOID -HalTxbf8814A_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal, tmpVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry; - - if (Idx < BEAMFORMEE_ENTRY_NUM) - BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; - else - return; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; - else - BeamCtrlVal = BeamformEntry.P_AID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState)); - - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8814A; - else { - BeamCtrlReg = REG_TXBF_CTRL_8814A + 2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; - } - - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamformingInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9 | BIT10); - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9 | BIT10 | BIT11); - } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); - } - - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); - /*disable NDP packet use beamforming */ - tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A); - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15); - -} - - - - - -VOID -HalTxbf8814A_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ -#if 0 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8814A_DownloadNDPA(pDM_Odm, Idx); - - halTxbf8814A_FwTxBFCmd(pDM_Odm); -#endif -} - -#endif /* (RTL8814A_SUPPORT == 1)*/ - -#endif - +//============================================================ +// Description: +// +// This file is for 8814A TXBF mechanism +// +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1) + +VOID +HalTxbf8814A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW); + ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate); + +} + +#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 +#define PHYDM_CTRL_INFO_PAGE 0x660 + +VOID +phydm_DataRate_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte macId, + OUT pu4Byte data, + IN u1Byte dataLen + ) +{ + u1Byte i = 0; + u2Byte XReadDataAddr = 0; + + ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/ + + if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr)); + return; + } + + /* Read data */ + for (i = 0; i < dataLen; i++) + *(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i); + +} + +VOID +HalTxbf8814A_GetTxRate( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pEntry; + u4Byte TxRptData = 0; + u1Byte DataRate = 0xFF; + + pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1); + DataRate = (u1Byte)TxRptData; + DataRate &= bMask7bits; /*Bit7 indicates SGI*/ + + pDM_Odm->TxBfDataRate = DataRate; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate)); +} + +VOID +HalTxbf8814A_ResetTxPath( + IN PVOID pDM_VOID, + IN u1Byte idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + u1Byte Nr_index = 0, txSS = 0; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) { + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + + if (*pDM_Odm->HubUsbMode == 2) { + if (pDM_Odm->RFType == ODM_4T4R) + txSS = 0xf; + else if (pDM_Odm->RFType == ODM_3T3R) + txSS = 0xe; + else + txSS = 0x6; + } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ + txSS = 0x6; + else + txSS = 0x6; + + if (txSS == 0xf) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); + } else if (txSS == 0xe) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); + } else if (txSS == 0x6) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); + } + + if (idx == 0) { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } else { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } + + pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; + } else + return; +#endif +} + + +u1Byte +halTxbf8814A_GetNtx( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Ntx = 0, txSS = 3; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + txSS = *pDM_Odm->HubUsbMode; +#endif + if (txSS == 3 || txSS == 2) { + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } else if (txSS == 1) /*USB 2.0 always 2Tx*/ + Ntx = 1; + else + Ntx = 1; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx)); + return Ntx; +} + +u1Byte +halTxbf8814A_GetNrx( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nrx = 0; + + if (pDM_Odm->RFType == ODM_4T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T2R) + Nrx = 1; + else if (pDM_Odm->RFType == ODM_2T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_1T1R) + Nrx = 0; + else if (pDM_Odm->RFType == ODM_1T2R) + Nrx = 1; + else + Nrx = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx)); + return Nrx; +} + +VOID +halTxbf8814A_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamformingInfo, + IN u1Byte idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i, Nr_index = 0; + u1Byte txSS = 3; /*default use 3 Tx*/ + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); + /*RF Mode table write enable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); + /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); + /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); + /*Enable TXIQGEN in RX mode*/ + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); + /*Enable TXIQGEN in RX mode*/ + } + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); + /*RF Mode table write disable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { +#if DEV_BUS_TYPE == RT_USB_INTERFACE + pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; + txSS = *pDM_Odm->HubUsbMode; +#endif + if (txSS == 3 || txSS == 2) { + if (pDM_Odm->RFType == ODM_4T4R) + txSS = 0xf; + else if (pDM_Odm->RFType == ODM_3T3R) + txSS = 0xe; + else + txSS = 0x6; + } else if (txSS == 1) /*USB 2.0 always 2Tx*/ + txSS = 0x6; + else + txSS = 0x6; + + if (txSS == 0xf) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); + } else if (txSS == 0xe) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); + } else if (txSS == 0x6) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); + } + + /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + + if (idx == 0) { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + + break; + } + } else { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } + } + + if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e9360); + } +} +#if 0 +VOID +halTxbf8814A_DownloadNDPA( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp = 0, tmpReg422 = 0; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + u2Byte Head_Page = 0x7FE; + BOOLEAN bSendBeacon = FALSE; + u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + PADAPTER Adapter = pDM_Odm->Adapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp | BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an Adapter is sending beacon.\n", __func__)); + bSendBeacon = TRUE; + } + + /*0x204[11:0] Beacon Head for TXDMA*/ + ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + ODM_Write1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(BcnValidReg & BIT7) && count < 20) { + count++; + ODM_delay_ms(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT7)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + + /*0x204[11:0] Beacon Head for TXDMA*/ + ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; +#endif +} + +VOID +halTxbf8814A_FwTxBFCmd( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx, Period = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = Period; + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d, PageNum1 = %d Period = %d\n", __func__, PageNum0, PageNum1, Period)); +} +#endif +VOID +HalTxbf8814A_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0, CSI_Param = 0; + u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx)); + ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202); + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + } + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ + Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + + grouping = 0; + + /*for ac = 1, for n = 3*/ + if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index)); + + if (BFerIdx == 0) + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param); + else + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); + + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9); + } else + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/ + + phydm_Beamforming_Notify(pDM_Odm); + } + +} + + +VOID +HalTxbf8814A_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMER_ENTRY BeamformerEntry; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8); + if (Idx == 0) { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + } + } + + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx); + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12); + + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + } + } +} + +VOID +HalTxbf8814A_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal, tmpVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry; + + if (Idx < BEAMFORMEE_ENTRY_NUM) + BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + else + return; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState)); + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8814A; + else { + BeamCtrlReg = REG_TXBF_CTRL_8814A + 2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamformingInfo->applyVmatrix == TRUE)) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9 | BIT10); + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + } + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + /*disable NDP packet use beamforming */ + tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A); + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15); + +} + + + + + +VOID +HalTxbf8814A_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ +#if 0 + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8814A_DownloadNDPA(pDM_Odm, Idx); + + halTxbf8814A_FwTxBFCmd(pDM_Odm); +#endif +} + +#endif /* (RTL8814A_SUPPORT == 1)*/ + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.h b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.h index 7efdc025ce2..aac2b930840 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.h +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8814a.h @@ -1,70 +1,70 @@ -#ifndef __HAL_TXBF_8814A_H__ -#define __HAL_TXBF_8814A_H__ - -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8814A_SUPPORT == 1) -VOID -HalTxbf8814A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -); - -u1Byte -halTxbf8814A_GetNtx( - IN PVOID pDM_VOID - ); - -VOID -HalTxbf8814A_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8814A_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8814A_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - -VOID -HalTxbf8814A_ResetTxPath( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8814A_GetTxRate( - IN PVOID pDM_VOID - ); - -VOID -HalTxbf8814A_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); -#else - -#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate) -#define halTxbf8814A_GetNtx(pDM_VOID) 0 -#define HalTxbf8814A_Enter(pDM_VOID, Idx) -#define HalTxbf8814A_Leave(pDM_VOID, Idx) -#define HalTxbf8814A_Status(pDM_VOID, Idx) -#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx) -#define HalTxbf8814A_GetTxRate(pDM_VOID) -#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx) -#endif - -#endif - -#endif - +#ifndef __HAL_TXBF_8814A_H__ +#define __HAL_TXBF_8814A_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1) +VOID +HalTxbf8814A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + +u1Byte +halTxbf8814A_GetNtx( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8814A_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +VOID +HalTxbf8814A_ResetTxPath( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_GetTxRate( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8814A_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); +#else + +#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate) +#define halTxbf8814A_GetNtx(pDM_VOID) 0 +#define HalTxbf8814A_Enter(pDM_VOID, Idx) +#define HalTxbf8814A_Leave(pDM_VOID, Idx) +#define HalTxbf8814A_Status(pDM_VOID, Idx) +#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx) +#define HalTxbf8814A_GetTxRate(pDM_VOID) +#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx) +#endif + +#endif + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.c b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.c index 9863779d5d0..cac501b1b4b 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.c +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.c @@ -1,1102 +1,1102 @@ -/*============================================================*/ -/* Description: */ -/* */ -/* This file is for 8814A TXBF mechanism */ -/* */ -/*============================================================*/ - -#include "mp_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8822B_SUPPORT == 1) - -u1Byte -halTxbf8822B_GetNtx( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Ntx = 0; - -#if DEV_BUS_TYPE == RT_USB_INTERFACE - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; - else - Ntx = 1; - } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ - Ntx = 1; - else - Ntx = 1; - } else -#endif - { - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; - else - Ntx = 1; - } - - return Ntx; - -} - -u1Byte -halTxbf8822B_GetNrx( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nrx = 0; - - if (pDM_Odm->RFType == ODM_4T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T2R) - Nrx = 1; - else if (pDM_Odm->RFType == ODM_2T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_1T1R) - Nrx = 0; - else if (pDM_Odm->RFType == ODM_1T2R) - Nrx = 1; - else - Nrx = 0; - - return Nrx; - -} - -/***************SU & MU BFee Entry********************/ -VOID -halTxbf8822B_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamformingInfo, - IN u1Byte idx - ) -{ -#if 0 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; - else - return; - - if (pDM_Odm->RFType == ODM_1T1R) - return; - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); - /*RF Mode table write enable*/ - } - - if ((pBeamformingInfo->beamformee_su_cnt > 0) || (pBeamformingInfo->beamformee_mu_cnt > 0)) { - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); - /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); - /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); - /*Enable TXIQGEN in RX mode*/ - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); - /*Enable TXIQGEN in RX mode*/ - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); - /*RF Mode table write disable*/ - } - - if (pBeamformingInfo->beamformee_su_cnt > 0) { - - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - - if (idx == 0) { - /*Nsts = 2 AB*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430);*/ - - } else {/*IDX =1*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430;*/ - } - } else { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ - } - - if (pBeamformingInfo->beamformee_mu_cnt > 0) { - /*MU STAs share the common setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - } -#endif -} -#if 0 -VOID -halTxbf8822B_DownloadNDPA( - IN PADAPTER Adapter, - IN u1Byte Idx - ) -{ - u1Byte u1bTmp = 0, tmpReg422 = 0; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - u2Byte Head_Page = 0x7FE; - BOOLEAN bSendBeacon = FALSE; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; - - pHalData->bFwDwRsvdPageInProgress = TRUE; - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); - - /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp|BIT0)); - - - /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2); - PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422&(~BIT6)); - - if (tmpReg422 & BIT6) { - RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n")); - bSendBeacon = TRUE; - } - - /*0x204[11:0] Beacon Head for TXDMA*/ - PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); - - do { - /*Clear beacon valid check bit.*/ - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1, (BcnValidReg|BIT7)); - - /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); - else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); - - /*check rsvd page download OK.*/ - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); - count = 0; - while (!(BcnValidReg & BIT7) && count < 20) { - count++; - delay_us(10); - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+2); - } - DLBcnCount++; - } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); - - if (!(BcnValidReg & BIT0)) - RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); - - /*0x204[11:0] Beacon Head for TXDMA*/ - PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); - - /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ - /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ - /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422); - - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp&(~BIT0))); - - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; - - pHalData->bFwDwRsvdPageInProgress = FALSE; -} - -VOID -halTxbf8822B_FwTxBFCmd( - IN PADAPTER Adapter - ) -{ - u1Byte Idx, Period = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) { - PageNum0 = 0xFE; - PageNum1 = 0x07; - Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (PageNum0 == 0xFF) { - PageNum0 = 0xFF; /*stop sounding*/ - PageNum1 = 0x0F; - } - } - } - - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = Period; - FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); - - RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period)); -} -#endif - -VOID -HalTxbf8822B_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT16, 1); /*Enable P1 aggr new packet according to P0 transfer time*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT15|BIT14|BIT13|BIT12, 10); /*MU Retry Limit*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT7, 0); /*Disable Tx MU-MIMO until sounding done*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , 0x3F, 0); /* Clear validity of MU STAs */ - ODM_Write1Byte(pDM_Odm, 0x167c , 0x70); /*MU-MIMO Option as default value*/ - ODM_Write2Byte(pDM_Odm, 0x1680 , 0); /*MU-MIMO Control as default value*/ - - /* Set MU NDPA rate & BW source */ - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1bTmp = ODM_Read1Byte(pDM_Odm, 0x42C); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B, (u1bTmp|BIT6)); - /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, 0x10); - - /*Temp Settings*/ - ODM_SetBBReg(pDM_Odm, 0x6DC , 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ - ODM_SetBBReg(pDM_Odm, 0x1C94 , bMaskDWord, 0xAFFFAFFF); /*Grouping bitmap parameters*/ - - /* Init HW variable */ - pBeamformingInfo->RegMUTxCtrl = ODM_Read4Byte(pDM_Odm, 0x14c0); - - if (pDM_Odm->RFType == ODM_2T2R) { /*2T2R*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: RFType is 2T2R\n", __func__)); - config_phydm_trx_mode_8822b(pDM_Odm, (ODM_RF_PATH_E)3, (ODM_RF_PATH_E)3, TRUE);/*Tx2path*/ - } - -#if (OMNIPEEK_SNIFFER_ENABLED == 1) - /* Config HW to receive packet on the user position from registry for sniffer mode. */ - /* ODM_SetBBReg(pDM_Odm, 0xB00 , BIT9, 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ - ODM_SetBBReg(pDM_Odm, 0xB54 , BIT30, 1); /* RegB54[30] = 1 (force user position) */ - ODM_SetBBReg(pDM_Odm, 0xB54 , (BIT29|BIT28), Adapter->MgntInfo.SniffUserPosition); /* RegB54[29:28] = user position (0~3) */ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set Adapter->MgntInfo.SniffUserPosition=%#X\n", Adapter->MgntInfo.SniffUserPosition)); -#endif -} - -VOID -HalTxbf8822B_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u2Byte CSI_Param = 0; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; - PRT_BEAMFORMER_ENTRY pBeamformerEntry; - u2Byte value16, STAid = 0; - u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - u4Byte gid_valid, user_position_l, user_position_h; - u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - u1Byte u1bTmp; - u4Byte u4bTmp; - - RT_DISP(FBEAM, FBEAM_FUN, ("%s: BFerBFeeIdx=%d, BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerBFeeIdx, BFerIdx, BFeeIdx)); - - /*************SU BFer Entry Init*************/ - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; - pBeamformerEntry->is_mu_ap = FALSE; - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); - - - for (i = 0; i < MAX_BEAMFORMER_SU; i++) { - if ((pBeamformingInfo->beamformer_su_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformer_su_reg_maping |= BIT(i); - pBeamformerEntry->su_reg_index = i; - break; - } - } - - /*MAC address/Partial AID of Beamformer*/ - if (pBeamformerEntry->su_reg_index == 0) { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); - } else { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); - } - - /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ - Nr_index = pBeamformerEntry->NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ - - grouping = 0; - - /*for ac = 1, for n = 3*/ - if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) - codebookinfo = 1; - else if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) - codebookinfo = 3; - - coefficientsize = 3; - - CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); - - if (BFerIdx == 0) - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, CSI_Param); - else - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, CSI_Param); - /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B+3, 0x70); - - } - - /*************SU BFee Entry Init*************/ - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - pBeamformeeEntry->is_mu_sta = FALSE; - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = pBeamformeeEntry->MacId; - else - STAid = pBeamformeeEntry->P_AID; - - for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { - if ((pBeamformingInfo->beamformee_su_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformee_su_reg_maping |= BIT(i); - pBeamformeeEntry->su_reg_index = i; - break; - } - } - - /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (pBeamformeeEntry->su_reg_index == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, STAid | BIT14 | BIT15 | BIT12); - } - - /*CSI report parameters of Beamformee*/ - if (pBeamformeeEntry->su_reg_index == 0) { - /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, STAid | BIT9); - } else - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, STAid | 0xE200); /*Set BIT25*/ - - phydm_Beamforming_Notify(pDM_Odm); - } - - /*************MU BFer Entry Init*************/ - if ((pBeamformingInfo->beamformer_mu_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; - pBeamformingInfo->mu_ap_index = BFerIdx; - pBeamformerEntry->is_mu_ap = TRUE; - for (i = 0; i < 8; i++) - pBeamformerEntry->gid_valid[i] = 0; - for (i = 0; i < 16; i++) - pBeamformerEntry->user_position[i] = 0; - - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); - - /* MAC address */ - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); - - /* Set partial AID */ - ODM_Write2Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+6), pBeamformerEntry->P_AID); - - /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, 0x1680); - u1bTmp = (pBeamformerEntry->AID)&0xFFF; - ODM_Write1Byte(pDM_Odm, 0x1680, u1bTmp); - - /* Set 80us for leaving ndp_rx_standby_state */ - ODM_Write1Byte(pDM_Odm, 0x71B, 0x50); - - /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); - u1bTmp |= 0x40; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); - /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP1_8822B); - u1bTmp |= 0x30; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP1_8822B, u1bTmp); - - /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /* Depend on RF type */ - Nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ - grouping = 0; /*no grouping*/ - codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ - coefficientsize = 0; /*This is nothing really matter*/ - CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); - ODM_Write2Byte(pDM_Odm, 0x6F4, CSI_Param); - - /*for B-Cut*/ - ODM_SetBBReg(pDM_Odm, 0x6A0 , BIT20, 0); - ODM_SetBBReg(pDM_Odm, 0x688 , BIT20, 0); - - } - - /*************MU BFee Entry Init*************/ - if ((pBeamformingInfo->beamformee_mu_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - pBeamformeeEntry->is_mu_sta = TRUE; - for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { - if ((pBeamformingInfo->beamformee_mu_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformee_mu_reg_maping |= BIT(i); - pBeamformeeEntry->mu_reg_index = i; - break; - } - } - - if (pBeamformeeEntry->mu_reg_index == 0xFF) { - /* There is no valid bit in beamformee_mu_reg_maping */ - RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__)); - return; - } - - /*User position table*/ - switch (pBeamformeeEntry->mu_reg_index) { - case 0: - gid_valid = 0x7fe; - user_position_l = 0x111110; - user_position_h = 0x0; - break; - case 1: - gid_valid = 0x7f806; - user_position_l = 0x11000004; - user_position_h = 0x11; - break; - case 2: - gid_valid = 0x1f81818; - user_position_l = 0x400040; - user_position_h = 0x11100; - break; - case 3: - gid_valid = 0x1e186060; - user_position_l = 0x4000400; - user_position_h = 0x1100040; - break; - case 4: - gid_valid = 0x66618180; - user_position_l = 0x40004000; - user_position_h = 0x10040400; - break; - case 5: - gid_valid = 0x79860600; - user_position_l = 0x40000; - user_position_h = 0x4404004; - break; - } - - for (i = 0; i < 8; i++) { - if (i < 4) { - pBeamformeeEntry->gid_valid[i] = (u1Byte)(gid_valid & 0xFF); - gid_valid = (gid_valid >> 8); - } else - pBeamformeeEntry->gid_valid[i] = 0; - } - for (i = 0; i < 16; i++) { - if (i < 4) - pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_l >>(i*8)) & 0xFF); - else if (i < 8) - pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_h >>((i-4)*8)) & 0xFF); - else - pBeamformeeEntry->user_position[i] = 0; - } - - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); - - /*select MU STA table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - - ODM_SetBBReg(pDM_Odm, 0x14c4 , bMaskDWord, 0); /*Reset gid_valid table*/ - ODM_SetBBReg(pDM_Odm, 0x14c8 , bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc , bMaskDWord, user_position_h); - - /*set validity of MU STAs*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - pBeamformingInfo->RegMUTxCtrl |= pBeamformingInfo->beamformee_mu_reg_maping&0x3F; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, RegMUTxCtrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, pBeamformingInfo->RegMUTxCtrl, user_position_l, user_position_h)); - - value16 = ODM_Read2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index]); - value16 &= 0xFE00; /*Clear PAID*/ - value16 |= BIT9; /*Enable MU BFee*/ - value16 |= pBeamformeeEntry->P_AID; - ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , value16); - - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3); - u1bTmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, u1bTmp); - /* Set NDPA to 6M*/ - ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8822B, 0x4); - - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B); - u1bTmp &= 0xFC; /* Clear bit 0, 1*/ - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, u1bTmp); - - u4bTmp = ODM_Read4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B); - u4bTmp = ((u4bTmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ - ODM_Write4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, u4bTmp); - - /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); - u1bTmp |= 0x40; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); - /* End of MAC registers setting */ - - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); -#if (SUPPORT_MU_BF == 1) - /*Special for plugfest*/ - delay_ms(50); /* wait for 4-way handshake ending*/ - SendSWVHTGIDMgntFrame(pDM_Odm, pBeamformeeEntry->MacAddr, BFeeIdx); -#endif - - phydm_Beamforming_Notify(pDM_Odm); -#if 1 - { - u4Byte ctrl_info_offset, index; - /*Set Ctrl Info*/ - ODM_Write2Byte(pDM_Odm, 0x140, 0x660); - ctrl_info_offset = 0x8000 + 32 * pBeamformeeEntry->MacId; - /*Reset Ctrl Info*/ - for (index = 0; index < 8; index++) - ODM_Write4Byte(pDM_Odm, ctrl_info_offset + index*4, 0); - - ODM_Write4Byte(pDM_Odm, ctrl_info_offset, (pBeamformeeEntry->mu_reg_index + 1) << 16); - ODM_Write1Byte(pDM_Odm, 0x81, 0x80); /*RPTBUF ready*/ - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MacId = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", - __func__, pBeamformeeEntry->MacId, ctrl_info_offset, pBeamformeeEntry->mu_reg_index)); - } -#endif - } - -} - - -VOID -HalTxbf8822B_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMER_ENTRY pBeamformerEntry; - PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; - u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[Idx]; - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; - } else - return; - - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ - - if (pBeamformerEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xD8); - if (pBeamformerEntry->is_mu_ap == 0) { /*SU BFer */ - if (pBeamformerEntry->su_reg_index == 0) { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); - } else { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); - } - pBeamformingInfo->beamformer_su_reg_maping &= ~(BIT(pBeamformerEntry->su_reg_index)); - pBeamformerEntry->su_reg_index = 0xFF; - } else { /*MU BFer */ - /*set validity of MU STA0 and MU STA1*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - - ODM_Memory_Set(pDM_Odm, pBeamformerEntry->gid_valid, 0, 8); - ODM_Memory_Set(pDM_Odm, pBeamformerEntry->user_position, 0, 16); - pBeamformerEntry->is_mu_ap = FALSE; - } - } - - if (pBeamformeeEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, Idx); - if (pBeamformeeEntry->is_mu_sta == 0) { /*SU BFee*/ - if (pBeamformeeEntry->su_reg_index == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, 0x0); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, 0x0 | BIT14 | BIT15 | BIT12); - - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, - ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2) & 0x60); - } - pBeamformingInfo->beamformee_su_reg_maping &= ~(BIT(pBeamformeeEntry->su_reg_index)); - pBeamformeeEntry->su_reg_index = 0xFF; - } else { /*MU BFee */ - /*Disable sending NDPA & BF-rpt-poll to this BFee*/ - ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , 0); - /*set validity of MU STA*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT(pBeamformeeEntry->mu_reg_index)); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - - - pBeamformeeEntry->is_mu_sta = FALSE; - pBeamformingInfo->beamformee_mu_reg_maping &= ~(BIT(pBeamformeeEntry->mu_reg_index)); - pBeamformeeEntry->mu_reg_index = 0xFF; - } - } -} - - -/***********SU & MU BFee Entry Only when souding done****************/ -VOID -HalTxbf8822B_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal, tmpVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformEntry; - BOOLEAN is_mu_sounding = pBeamformingInfo->is_mu_sounding, is_bitmap_ready = FALSE; - u16 bitmap; - u8 idx, gid, i; - u8 id1, id0; - u32 gid_valid[6] = {0}; - u32 user_position_lsb[6] = {0}; - u32 user_position_msb[6] = {0}; - u32 value32; - BOOLEAN is_sounding_success[6] = {FALSE}; - - if (Idx < BEAMFORMEE_ENTRY_NUM) - pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; - else - return; - - /*SU sounding done */ - if (is_mu_sounding == FALSE) { - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = pBeamformEntry->MacId; - else - BeamCtrlVal = pBeamformEntry->P_AID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, pBeamformEntry->BeamformEntryState)); - - if (pBeamformEntry->su_reg_index == 0) { - BeamCtrlReg = REG_TXBF_CTRL_8822B; - } else { - BeamCtrlReg = REG_TXBF_CTRL_8822B+2; - BeamCtrlVal |= BIT12|BIT14|BIT15; - } - - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9|BIT10); - else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9|BIT10|BIT11); - } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); - BeamCtrlVal &= ~(BIT9|BIT10|BIT11); - } - - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); - /*disable NDP packet use beamforming */ - tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8822B); - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, tmpVal|BIT15); - } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); - /*MU sounding done */ - if (1){//(pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); - - value32 = ODM_GetBBReg(pDM_Odm, 0x1684, bMaskDWord); - is_sounding_success[0] = (value32 & BIT10)?1:0; - is_sounding_success[1] = (value32 & BIT26)?1:0; - value32 = ODM_GetBBReg(pDM_Odm, 0x1688, bMaskDWord); - is_sounding_success[2] = (value32 & BIT10)?1:0; - is_sounding_success[3] = (value32 & BIT26)?1:0; - value32 = ODM_GetBBReg(pDM_Odm, 0x168C, bMaskDWord); - is_sounding_success[4] = (value32 & BIT10)?1:0; - is_sounding_success[5] = (value32 & BIT26)?1:0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", - __func__, is_sounding_success[0], is_sounding_success[1] , is_sounding_success[2] , is_sounding_success[3] , is_sounding_success[4] , is_sounding_success[5] )); - - value32 = ODM_GetBBReg(pDM_Odm, 0xF4C, 0xFFFF0000); - //ODM_SetBBReg(pDM_Odm, 0x19E0, bMaskHWord, 0xFFFF);/*Let MAC ignore bitmap*/ - - is_bitmap_ready = (BOOLEAN)((value32 & BIT15) >> 15); - bitmap = (u16)(value32 & 0x3FFF); - - for (idx = 0; idx < 15; idx++) { - if (idx < 5) {/*bit0~4*/ - id0 = 0; - id1 = (u8)(idx + 1); - } else if (idx < 9) { /*bit5~8*/ - id0 = 1; - id1 = (u8)(idx - 3); - } else if (idx < 12) { /*bit9~11*/ - id0 = 2; - id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ - id0 = 3; - id1 = (u8)(idx - 8); - } else { /*bit14*/ - id0 = 4; - id1 = (u8)(idx - 9); - } - if (bitmap & BIT(idx)) { - /*Pair 1*/ - gid = (idx << 1) + 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - } else { - /*Pair 1*/ - gid = (idx << 1) + 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - } - } - - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[i]; - if ((pBeamformEntry->is_mu_sta) && (pBeamformEntry->mu_reg_index < 6)) { - value32 = gid_valid[pBeamformEntry->mu_reg_index]; - for (idx = 0; idx < 4; idx++) { - pBeamformEntry->gid_valid[idx] = (u8)(value32 & 0xFF); - value32 = (value32 >> 8); - } - } - } - - for (idx = 0; idx < 6; idx++) { - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10)); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetMACReg(pDM_Odm, 0x14C4, bMaskDWord, gid_valid[idx]); /*set MU STA gid valid table*/ - } - - /*Enable TxMU PPDU*/ - if (pBeamformingInfo->dbg_disable_mu_tx == FALSE) - pBeamformingInfo->RegMUTxCtrl |= BIT7; - else - pBeamformingInfo->RegMUTxCtrl &= ~BIT7; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - } - } -} - -/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -VOID -HalTxbf8822B_ConfigGtab( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; - u4Byte gid_valid = 0, user_position_l = 0, user_position_h = 0, i; - - if (pBeamformingInfo->mu_ap_index < BEAMFORMER_ENTRY_NUM) - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[pBeamformingInfo->mu_ap_index]; - else - return; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); - - /*For GID 0~31*/ - for (i = 0; i < 4; i++) - gid_valid |= (pBeamformerEntry->gid_valid[i] << (i<<3)); - for (i = 0; i < 8; i++) { - if (i < 4) - user_position_l |= (pBeamformerEntry->user_position[i] << (i << 3)); - else - user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 4)<<3)); - } - /*select MU STA0 table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); - ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); - - gid_valid = 0; - user_position_l = 0; - user_position_h = 0; - - /*For GID 32~64*/ - for (i = 4; i < 8; i++) - gid_valid |= (pBeamformerEntry->gid_valid[i] << ((i - 4)<<3)); - for (i = 8; i < 16; i++) { - if (i < 4) - user_position_l |= (pBeamformerEntry->user_position[i] << ((i - 8) << 3)); - else - user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 12) << 3)); - } - /*select MU STA1 table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= BIT8; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); - ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); - - /* Set validity of MU STA0 and MU STA1*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - pBeamformingInfo->RegMUTxCtrl |= 0x3; /* STA0, STA1*/ - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - -} - - - -#if 0 -/*This function translate the bitmap to GTAB*/ -VOID -haltxbf8822b_gtab_translation( - IN PDM_ODM_T pDM_Odm -) -{ - u8 idx, gid; - u8 id1, id0; - u32 gid_valid[6] = {0}; - u32 user_position_lsb[6] = {0}; - u32 user_position_msb[6] = {0}; - - for (idx = 0; idx < 15; idx++) { - if (idx < 5) {/*bit0~4*/ - id0 = 0; - id1 = (u8)(idx + 1); - } else if (idx < 9) { /*bit5~8*/ - id0 = 1; - id1 = (u8)(idx - 3); - } else if (idx < 12) { /*bit9~11*/ - id0 = 2; - id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ - id0 = 3; - id1 = (u8)(idx - 8); - } else { /*bit14*/ - id0 = 4; - id1 = (u8)(idx - 9); - } - - /*Pair 1*/ - gid = (idx << 1) + 1; - gid_valid[id0] |= (1 << gid); - gid_valid[id1] |= (1 << gid); - if (gid < 16) { - /*user_position_lsb[id0] |= (0 << (gid << 1));*/ - user_position_lsb[id1] |= (1 << (gid << 1)); - } else { - /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/ - user_position_msb[id1] |= (1 << ((gid - 16) << 1)); - } - - /*Pair 2*/ - gid += 1; - gid_valid[id0] |= (1 << gid); - gid_valid[id1] |= (1 << gid); - if (gid < 16) { - user_position_lsb[id0] |= (1 << (gid << 1)); - /*user_position_lsb[id1] |= (0 << (gid << 1));*/ - } else { - user_position_msb[id0] |= (1 << ((gid - 16) << 1)); - /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/ - } - - } - - - for (idx = 0; idx < 6; idx++) { - /*DbgPrint("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); - DbgPrint("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ - } -} -#endif - -VOID -HalTxbf8822B_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) -{ -#if 0 - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; - - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8822B_DownloadNDPA(Adapter, Idx); - - halTxbf8822B_FwTxBFCmd(Adapter); -#endif -} - - -/*this function is only used for BFer*/ -VOID -phydm_8822btxbf_rfmode( - IN PVOID pDM_VOID, - IN u1Byte SUBFeeCnt, - IN u1Byte MUBFeeCnt - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; - - if (pDM_Odm->RFType == ODM_1T1R) - return; - - if ((SUBFeeCnt > 0) || (MUBFeeCnt > 0)) { - for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, i, 0x33, 0xF, 3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x0); /*RF Mode table write disable*/ - } - } - - if (SUBFeeCnt > 0 || MUBFeeCnt > 0) { - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); /*ignore user since 8822B only 2Tx*/ - - /*Nsts = 2 AB*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - - } else { - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x0); /*enable BB TxBF ant mapping register*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 0); /*ignore user since 8822B only 2Tx*/ - - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ - } - -} - - -/*this function is for BFer bug workaround*/ -VOID -phydm_8822b_sutxbfer_workaroud( - IN PVOID pDM_VOID, - IN BOOLEAN EnableSUBfer, - IN u1Byte Nc, - IN u1Byte Nr, - IN u1Byte Ng, - IN u1Byte CB, - IN u1Byte BW, - IN BOOLEAN isVHT - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (EnableSUBfer) { - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT22|BIT21|BIT20, 0x1); - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT25|BIT24|BIT23, 0x0); - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x1); - - if (isVHT) - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x1f); - else - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x22); - - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT7|BIT6, Nc); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT9|BIT8, Nr); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT11|BIT10, Ng); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT13|BIT12, CB); - - ODM_SetBBReg(pDM_Odm, 0xb58, BIT3|BIT2, BW); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT7|BIT6|BIT5|BIT4, 0x0); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT9|BIT8, BW); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT13|BIT12|BIT11|BIT10, 0x0); - } else - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x0); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] EnableSUBfer = %d, isVHT = %d\n", __func__, EnableSUBfer, isVHT)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] Nc = %d, Nr = %d, Ng = %d, CB = %d, BW = %d\n", __func__, Nc, Nr, Ng, CB, BW)); - - -} - - - - -#else /* (RTL8822B_SUPPORT == 1)*/ - -#endif /* (RTL8822B_SUPPORT == 1)*/ - -#endif - - +/*============================================================*/ +/* Description: */ +/* */ +/* This file is for 8814A TXBF mechanism */ +/* */ +/*============================================================*/ + +#include "mp_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) + +u1Byte +halTxbf8822B_GetNtx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Ntx = 0; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ + Ntx = 1; + else + Ntx = 1; + } else +#endif + { + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } + + return Ntx; + +} + +u1Byte +halTxbf8822B_GetNrx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nrx = 0; + + if (pDM_Odm->RFType == ODM_4T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T2R) + Nrx = 1; + else if (pDM_Odm->RFType == ODM_2T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_1T1R) + Nrx = 0; + else if (pDM_Odm->RFType == ODM_1T2R) + Nrx = 1; + else + Nrx = 0; + + return Nrx; + +} + +/***************SU & MU BFee Entry********************/ +VOID +halTxbf8822B_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamformingInfo, + IN u1Byte idx + ) +{ +#if 0 + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i, Nr_index = 0; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); + /*RF Mode table write enable*/ + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) || (pBeamformingInfo->beamformee_mu_cnt > 0)) { + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); + /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); + /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); + /*Enable TXIQGEN in RX mode*/ + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); + /*Enable TXIQGEN in RX mode*/ + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); + /*RF Mode table write disable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { + + /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + + if (idx == 0) { + /*Nsts = 2 AB*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430);*/ + + } else {/*IDX =1*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430;*/ + } + } else { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ + } + + if (pBeamformingInfo->beamformee_mu_cnt > 0) { + /*MU STAs share the common setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + } +#endif +} +#if 0 +VOID +halTxbf8822B_DownloadNDPA( + IN PADAPTER Adapter, + IN u1Byte Idx + ) +{ + u1Byte u1bTmp = 0, tmpReg422 = 0; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + u2Byte Head_Page = 0x7FE; + BOOLEAN bSendBeacon = FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; + + pHalData->bFwDwRsvdPageInProgress = TRUE; + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp|BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2); + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422&(~BIT6)); + + if (tmpReg422 & BIT6) { + RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1, (BcnValidReg|BIT7)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(BcnValidReg & BIT7) && count < 20) { + count++; + delay_us(10); + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp&(~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + + pHalData->bFwDwRsvdPageInProgress = FALSE; +} + +VOID +halTxbf8822B_FwTxBFCmd( + IN PADAPTER Adapter + ) +{ + u1Byte Idx, Period = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = Period; + FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period)); +} +#endif + +VOID +HalTxbf8822B_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT16, 1); /*Enable P1 aggr new packet according to P0 transfer time*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT15|BIT14|BIT13|BIT12, 10); /*MU Retry Limit*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT7, 0); /*Disable Tx MU-MIMO until sounding done*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , 0x3F, 0); /* Clear validity of MU STAs */ + ODM_Write1Byte(pDM_Odm, 0x167c , 0x70); /*MU-MIMO Option as default value*/ + ODM_Write2Byte(pDM_Odm, 0x1680 , 0); /*MU-MIMO Control as default value*/ + + /* Set MU NDPA rate & BW source */ + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1bTmp = ODM_Read1Byte(pDM_Odm, 0x42C); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B, (u1bTmp|BIT6)); + /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, 0x10); + + /*Temp Settings*/ + ODM_SetBBReg(pDM_Odm, 0x6DC , 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ + ODM_SetBBReg(pDM_Odm, 0x1C94 , bMaskDWord, 0xAFFFAFFF); /*Grouping bitmap parameters*/ + + /* Init HW variable */ + pBeamformingInfo->RegMUTxCtrl = ODM_Read4Byte(pDM_Odm, 0x14c0); + + if (pDM_Odm->RFType == ODM_2T2R) { /*2T2R*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: RFType is 2T2R\n", __func__)); + config_phydm_trx_mode_8822b(pDM_Odm, (ODM_RF_PATH_E)3, (ODM_RF_PATH_E)3, TRUE);/*Tx2path*/ + } + +#if (OMNIPEEK_SNIFFER_ENABLED == 1) + /* Config HW to receive packet on the user position from registry for sniffer mode. */ + /* ODM_SetBBReg(pDM_Odm, 0xB00 , BIT9, 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ + ODM_SetBBReg(pDM_Odm, 0xB54 , BIT30, 1); /* RegB54[30] = 1 (force user position) */ + ODM_SetBBReg(pDM_Odm, 0xB54 , (BIT29|BIT28), Adapter->MgntInfo.SniffUserPosition); /* RegB54[29:28] = user position (0~3) */ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set Adapter->MgntInfo.SniffUserPosition=%#X\n", Adapter->MgntInfo.SniffUserPosition)); +#endif +} + +VOID +HalTxbf8822B_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u2Byte CSI_Param = 0; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; + PRT_BEAMFORMER_ENTRY pBeamformerEntry; + u2Byte value16, STAid = 0; + u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + u4Byte gid_valid, user_position_l, user_position_h; + u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + u1Byte u1bTmp; + u4Byte u4bTmp; + + RT_DISP(FBEAM, FBEAM_FUN, ("%s: BFerBFeeIdx=%d, BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerBFeeIdx, BFerIdx, BFeeIdx)); + + /*************SU BFer Entry Init*************/ + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; + pBeamformerEntry->is_mu_ap = FALSE; + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + + for (i = 0; i < MAX_BEAMFORMER_SU; i++) { + if ((pBeamformingInfo->beamformer_su_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformer_su_reg_maping |= BIT(i); + pBeamformerEntry->su_reg_index = i; + break; + } + } + + /*MAC address/Partial AID of Beamformer*/ + if (pBeamformerEntry->su_reg_index == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + } + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ + Nr_index = pBeamformerEntry->NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + + grouping = 0; + + /*for ac = 1, for n = 3*/ + if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); + + if (BFerIdx == 0) + ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, CSI_Param); + else + ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, CSI_Param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B+3, 0x70); + + } + + /*************SU BFee Entry Init*************/ + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + pBeamformeeEntry->is_mu_sta = FALSE; + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = pBeamformeeEntry->MacId; + else + STAid = pBeamformeeEntry->P_AID; + + for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { + if ((pBeamformingInfo->beamformee_su_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformee_su_reg_maping |= BIT(i); + pBeamformeeEntry->su_reg_index = i; + break; + } + } + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (pBeamformeeEntry->su_reg_index == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, STAid | BIT14 | BIT15 | BIT12); + } + + /*CSI report parameters of Beamformee*/ + if (pBeamformeeEntry->su_reg_index == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, STAid | BIT9); + } else + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, STAid | 0xE200); /*Set BIT25*/ + + phydm_Beamforming_Notify(pDM_Odm); + } + + /*************MU BFer Entry Init*************/ + if ((pBeamformingInfo->beamformer_mu_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; + pBeamformingInfo->mu_ap_index = BFerIdx; + pBeamformerEntry->is_mu_ap = TRUE; + for (i = 0; i < 8; i++) + pBeamformerEntry->gid_valid[i] = 0; + for (i = 0; i < 16; i++) + pBeamformerEntry->user_position[i] = 0; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /* MAC address */ + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + + /* Set partial AID */ + ODM_Write2Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+6), pBeamformerEntry->P_AID); + + /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, 0x1680); + u1bTmp = (pBeamformerEntry->AID)&0xFFF; + ODM_Write1Byte(pDM_Odm, 0x1680, u1bTmp); + + /* Set 80us for leaving ndp_rx_standby_state */ + ODM_Write1Byte(pDM_Odm, 0x71B, 0x50); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); + u1bTmp |= 0x40; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP1_8822B); + u1bTmp |= 0x30; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP1_8822B, u1bTmp); + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /* Depend on RF type */ + Nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + grouping = 0; /*no grouping*/ + codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ + coefficientsize = 0; /*This is nothing really matter*/ + CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); + ODM_Write2Byte(pDM_Odm, 0x6F4, CSI_Param); + + /*for B-Cut*/ + ODM_SetBBReg(pDM_Odm, 0x6A0 , BIT20, 0); + ODM_SetBBReg(pDM_Odm, 0x688 , BIT20, 0); + + } + + /*************MU BFee Entry Init*************/ + if ((pBeamformingInfo->beamformee_mu_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + pBeamformeeEntry->is_mu_sta = TRUE; + for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { + if ((pBeamformingInfo->beamformee_mu_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformee_mu_reg_maping |= BIT(i); + pBeamformeeEntry->mu_reg_index = i; + break; + } + } + + if (pBeamformeeEntry->mu_reg_index == 0xFF) { + /* There is no valid bit in beamformee_mu_reg_maping */ + RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__)); + return; + } + + /*User position table*/ + switch (pBeamformeeEntry->mu_reg_index) { + case 0: + gid_valid = 0x7fe; + user_position_l = 0x111110; + user_position_h = 0x0; + break; + case 1: + gid_valid = 0x7f806; + user_position_l = 0x11000004; + user_position_h = 0x11; + break; + case 2: + gid_valid = 0x1f81818; + user_position_l = 0x400040; + user_position_h = 0x11100; + break; + case 3: + gid_valid = 0x1e186060; + user_position_l = 0x4000400; + user_position_h = 0x1100040; + break; + case 4: + gid_valid = 0x66618180; + user_position_l = 0x40004000; + user_position_h = 0x10040400; + break; + case 5: + gid_valid = 0x79860600; + user_position_l = 0x40000; + user_position_h = 0x4404004; + break; + } + + for (i = 0; i < 8; i++) { + if (i < 4) { + pBeamformeeEntry->gid_valid[i] = (u1Byte)(gid_valid & 0xFF); + gid_valid = (gid_valid >> 8); + } else + pBeamformeeEntry->gid_valid[i] = 0; + } + for (i = 0; i < 16; i++) { + if (i < 4) + pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_l >>(i*8)) & 0xFF); + else if (i < 8) + pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_h >>((i-4)*8)) & 0xFF); + else + pBeamformeeEntry->user_position[i] = 0; + } + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /*select MU STA table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + ODM_SetBBReg(pDM_Odm, 0x14c4 , bMaskDWord, 0); /*Reset gid_valid table*/ + ODM_SetBBReg(pDM_Odm, 0x14c8 , bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc , bMaskDWord, user_position_h); + + /*set validity of MU STAs*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + pBeamformingInfo->RegMUTxCtrl |= pBeamformingInfo->beamformee_mu_reg_maping&0x3F; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, RegMUTxCtrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, pBeamformingInfo->RegMUTxCtrl, user_position_l, user_position_h)); + + value16 = ODM_Read2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index]); + value16 &= 0xFE00; /*Clear PAID*/ + value16 |= BIT9; /*Enable MU BFee*/ + value16 |= pBeamformeeEntry->P_AID; + ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , value16); + + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3); + u1bTmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, u1bTmp); + /* Set NDPA to 6M*/ + ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8822B, 0x4); + + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B); + u1bTmp &= 0xFC; /* Clear bit 0, 1*/ + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, u1bTmp); + + u4bTmp = ODM_Read4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B); + u4bTmp = ((u4bTmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ + ODM_Write4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, u4bTmp); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); + u1bTmp |= 0x40; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + /* End of MAC registers setting */ + + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); +#if (SUPPORT_MU_BF == 1) + /*Special for plugfest*/ + delay_ms(50); /* wait for 4-way handshake ending*/ + SendSWVHTGIDMgntFrame(pDM_Odm, pBeamformeeEntry->MacAddr, BFeeIdx); +#endif + + phydm_Beamforming_Notify(pDM_Odm); +#if 1 + { + u4Byte ctrl_info_offset, index; + /*Set Ctrl Info*/ + ODM_Write2Byte(pDM_Odm, 0x140, 0x660); + ctrl_info_offset = 0x8000 + 32 * pBeamformeeEntry->MacId; + /*Reset Ctrl Info*/ + for (index = 0; index < 8; index++) + ODM_Write4Byte(pDM_Odm, ctrl_info_offset + index*4, 0); + + ODM_Write4Byte(pDM_Odm, ctrl_info_offset, (pBeamformeeEntry->mu_reg_index + 1) << 16); + ODM_Write1Byte(pDM_Odm, 0x81, 0x80); /*RPTBUF ready*/ + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MacId = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", + __func__, pBeamformeeEntry->MacId, ctrl_info_offset, pBeamformeeEntry->mu_reg_index)); + } +#endif + } + +} + + +VOID +HalTxbf8822B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMER_ENTRY pBeamformerEntry; + PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; + u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[Idx]; + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (pBeamformerEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (pBeamformerEntry->is_mu_ap == 0) { /*SU BFer */ + if (pBeamformerEntry->su_reg_index == 0) { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); + ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); + ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); + } + pBeamformingInfo->beamformer_su_reg_maping &= ~(BIT(pBeamformerEntry->su_reg_index)); + pBeamformerEntry->su_reg_index = 0xFF; + } else { /*MU BFer */ + /*set validity of MU STA0 and MU STA1*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + ODM_Memory_Set(pDM_Odm, pBeamformerEntry->gid_valid, 0, 8); + ODM_Memory_Set(pDM_Odm, pBeamformerEntry->user_position, 0, 16); + pBeamformerEntry->is_mu_ap = FALSE; + } + } + + if (pBeamformeeEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, Idx); + if (pBeamformeeEntry->is_mu_sta == 0) { /*SU BFee*/ + if (pBeamformeeEntry->su_reg_index == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, 0x0); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, 0x0 | BIT14 | BIT15 | BIT12); + + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, + ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2) & 0x60); + } + pBeamformingInfo->beamformee_su_reg_maping &= ~(BIT(pBeamformeeEntry->su_reg_index)); + pBeamformeeEntry->su_reg_index = 0xFF; + } else { /*MU BFee */ + /*Disable sending NDPA & BF-rpt-poll to this BFee*/ + ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , 0); + /*set validity of MU STA*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT(pBeamformeeEntry->mu_reg_index)); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + + pBeamformeeEntry->is_mu_sta = FALSE; + pBeamformingInfo->beamformee_mu_reg_maping &= ~(BIT(pBeamformeeEntry->mu_reg_index)); + pBeamformeeEntry->mu_reg_index = 0xFF; + } + } +} + + +/***********SU & MU BFee Entry Only when souding done****************/ +VOID +HalTxbf8822B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal, tmpVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformEntry; + BOOLEAN is_mu_sounding = pBeamformingInfo->is_mu_sounding, is_bitmap_ready = FALSE; + u16 bitmap; + u8 idx, gid, i; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 user_position_lsb[6] = {0}; + u32 user_position_msb[6] = {0}; + u32 value32; + BOOLEAN is_sounding_success[6] = {FALSE}; + + if (Idx < BEAMFORMEE_ENTRY_NUM) + pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + else + return; + + /*SU sounding done */ + if (is_mu_sounding == FALSE) { + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = pBeamformEntry->MacId; + else + BeamCtrlVal = pBeamformEntry->P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, pBeamformEntry->BeamformEntryState)); + + if (pBeamformEntry->su_reg_index == 0) { + BeamCtrlReg = REG_TXBF_CTRL_8822B; + } else { + BeamCtrlReg = REG_TXBF_CTRL_8822B+2; + BeamCtrlVal |= BIT12|BIT14|BIT15; + } + + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9|BIT10); + else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9|BIT10|BIT11); + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + BeamCtrlVal &= ~(BIT9|BIT10|BIT11); + } + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + /*disable NDP packet use beamforming */ + tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8822B); + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, tmpVal|BIT15); + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); + /*MU sounding done */ + if (1){//(pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); + + value32 = ODM_GetBBReg(pDM_Odm, 0x1684, bMaskDWord); + is_sounding_success[0] = (value32 & BIT10)?1:0; + is_sounding_success[1] = (value32 & BIT26)?1:0; + value32 = ODM_GetBBReg(pDM_Odm, 0x1688, bMaskDWord); + is_sounding_success[2] = (value32 & BIT10)?1:0; + is_sounding_success[3] = (value32 & BIT26)?1:0; + value32 = ODM_GetBBReg(pDM_Odm, 0x168C, bMaskDWord); + is_sounding_success[4] = (value32 & BIT10)?1:0; + is_sounding_success[5] = (value32 & BIT26)?1:0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __func__, is_sounding_success[0], is_sounding_success[1] , is_sounding_success[2] , is_sounding_success[3] , is_sounding_success[4] , is_sounding_success[5] )); + + value32 = ODM_GetBBReg(pDM_Odm, 0xF4C, 0xFFFF0000); + //ODM_SetBBReg(pDM_Odm, 0x19E0, bMaskHWord, 0xFFFF);/*Let MAC ignore bitmap*/ + + is_bitmap_ready = (BOOLEAN)((value32 & BIT15) >> 15); + bitmap = (u16)(value32 & 0x3FFF); + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) {/*bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[i]; + if ((pBeamformEntry->is_mu_sta) && (pBeamformEntry->mu_reg_index < 6)) { + value32 = gid_valid[pBeamformEntry->mu_reg_index]; + for (idx = 0; idx < 4; idx++) { + pBeamformEntry->gid_valid[idx] = (u8)(value32 & 0xFF); + value32 = (value32 >> 8); + } + } + } + + for (idx = 0; idx < 6; idx++) { + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10)); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetMACReg(pDM_Odm, 0x14C4, bMaskDWord, gid_valid[idx]); /*set MU STA gid valid table*/ + } + + /*Enable TxMU PPDU*/ + if (pBeamformingInfo->dbg_disable_mu_tx == FALSE) + pBeamformingInfo->RegMUTxCtrl |= BIT7; + else + pBeamformingInfo->RegMUTxCtrl &= ~BIT7; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + } + } +} + +/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ +VOID +HalTxbf8822B_ConfigGtab( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; + u4Byte gid_valid = 0, user_position_l = 0, user_position_h = 0, i; + + if (pBeamformingInfo->mu_ap_index < BEAMFORMER_ENTRY_NUM) + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[pBeamformingInfo->mu_ap_index]; + else + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); + + /*For GID 0~31*/ + for (i = 0; i < 4; i++) + gid_valid |= (pBeamformerEntry->gid_valid[i] << (i<<3)); + for (i = 0; i < 8; i++) { + if (i < 4) + user_position_l |= (pBeamformerEntry->user_position[i] << (i << 3)); + else + user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 4)<<3)); + } + /*select MU STA0 table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); + ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); + + gid_valid = 0; + user_position_l = 0; + user_position_h = 0; + + /*For GID 32~64*/ + for (i = 4; i < 8; i++) + gid_valid |= (pBeamformerEntry->gid_valid[i] << ((i - 4)<<3)); + for (i = 8; i < 16; i++) { + if (i < 4) + user_position_l |= (pBeamformerEntry->user_position[i] << ((i - 8) << 3)); + else + user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 12) << 3)); + } + /*select MU STA1 table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= BIT8; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); + ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); + + /* Set validity of MU STA0 and MU STA1*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + pBeamformingInfo->RegMUTxCtrl |= 0x3; /* STA0, STA1*/ + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + +} + + + +#if 0 +/*This function translate the bitmap to GTAB*/ +VOID +haltxbf8822b_gtab_translation( + IN PDM_ODM_T pDM_Odm +) +{ + u8 idx, gid; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 user_position_lsb[6] = {0}; + u32 user_position_msb[6] = {0}; + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) {/*bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + /*user_position_lsb[id0] |= (0 << (gid << 1));*/ + user_position_lsb[id1] |= (1 << (gid << 1)); + } else { + /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/ + user_position_msb[id1] |= (1 << ((gid - 16) << 1)); + } + + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + user_position_lsb[id0] |= (1 << (gid << 1)); + /*user_position_lsb[id1] |= (0 << (gid << 1));*/ + } else { + user_position_msb[id0] |= (1 << ((gid - 16) << 1)); + /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/ + } + + } + + + for (idx = 0; idx < 6; idx++) { + /*DbgPrint("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); + DbgPrint("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ + } +} +#endif + +VOID +HalTxbf8822B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ +#if 0 + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8822B_DownloadNDPA(Adapter, Idx); + + halTxbf8822B_FwTxBFCmd(Adapter); +#endif +} + + +/*this function is only used for BFer*/ +VOID +phydm_8822btxbf_rfmode( + IN PVOID pDM_VOID, + IN u1Byte SUBFeeCnt, + IN u1Byte MUBFeeCnt + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i, Nr_index = 0; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + if ((SUBFeeCnt > 0) || (MUBFeeCnt > 0)) { + for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, i, 0x33, 0xF, 3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x0); /*RF Mode table write disable*/ + } + } + + if (SUBFeeCnt > 0 || MUBFeeCnt > 0) { + /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); /*ignore user since 8822B only 2Tx*/ + + /*Nsts = 2 AB*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + + } else { + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x0); /*enable BB TxBF ant mapping register*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 0); /*ignore user since 8822B only 2Tx*/ + + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ + } + +} + + +/*this function is for BFer bug workaround*/ +VOID +phydm_8822b_sutxbfer_workaroud( + IN PVOID pDM_VOID, + IN BOOLEAN EnableSUBfer, + IN u1Byte Nc, + IN u1Byte Nr, + IN u1Byte Ng, + IN u1Byte CB, + IN u1Byte BW, + IN BOOLEAN isVHT + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (EnableSUBfer) { + ODM_SetBBReg(pDM_Odm, 0x19f8, BIT22|BIT21|BIT20, 0x1); + ODM_SetBBReg(pDM_Odm, 0x19f8, BIT25|BIT24|BIT23, 0x0); + ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x1); + + if (isVHT) + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x1f); + else + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x22); + + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT7|BIT6, Nc); + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT9|BIT8, Nr); + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT11|BIT10, Ng); + ODM_SetBBReg(pDM_Odm, 0x19f0, BIT13|BIT12, CB); + + ODM_SetBBReg(pDM_Odm, 0xb58, BIT3|BIT2, BW); + ODM_SetBBReg(pDM_Odm, 0xb58, BIT7|BIT6|BIT5|BIT4, 0x0); + ODM_SetBBReg(pDM_Odm, 0xb58, BIT9|BIT8, BW); + ODM_SetBBReg(pDM_Odm, 0xb58, BIT13|BIT12|BIT11|BIT10, 0x0); + } else + ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x0); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] EnableSUBfer = %d, isVHT = %d\n", __func__, EnableSUBfer, isVHT)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] Nc = %d, Nr = %d, Ng = %d, CB = %d, BW = %d\n", __func__, Nc, Nr, Ng, CB, BW)); + + +} + + + + +#else /* (RTL8822B_SUPPORT == 1)*/ + +#endif /* (RTL8822B_SUPPORT == 1)*/ + +#endif + + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.h b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.h index d90b360d0aa..d35675a58f5 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.h +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbf8822b.h @@ -1,73 +1,73 @@ -#ifndef __HAL_TXBF_8822B_H__ -#define __HAL_TXBF_8822B_H__ -#if (BEAMFORMING_SUPPORT == 1) -#if (RTL8822B_SUPPORT == 1) - -VOID -HalTxbf8822B_Init( - IN PVOID pDM_VOID - ); - -VOID -HalTxbf8822B_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8822B_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbf8822B_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - -VOID -HalTxbf8822B_ConfigGtab( - IN PVOID pDM_VOID - ); - -VOID -HalTxbf8822B_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - -VOID -phydm_8822btxbf_rfmode( - IN PVOID pDM_VOID, - IN u1Byte SUBFeeCnt, - IN u1Byte MUBFeeCnt - ); - -VOID -phydm_8822b_sutxbfer_workaroud( - IN PVOID pDM_VOID, - IN BOOLEAN EnableSUBfer, - IN u1Byte Nc, - IN u1Byte Nr, - IN u1Byte Ng, - IN u1Byte CB, - IN u1Byte BW, - IN BOOLEAN isVHT - ); - -#else -#define HalTxbf8822B_Init(pDM_VOID) -#define HalTxbf8822B_Enter(pDM_VOID, Idx) -#define HalTxbf8822B_Leave(pDM_VOID, Idx) -#define HalTxbf8822B_Status(pDM_VOID, Idx) -#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx) -#define HalTxbf8822B_ConfigGtab(pDM_VOID) -#endif - - -#endif -#endif - +#ifndef __HAL_TXBF_8822B_H__ +#define __HAL_TXBF_8822B_H__ +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) + +VOID +HalTxbf8822B_Init( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8822B_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8822B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8822B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +VOID +HalTxbf8822B_ConfigGtab( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8822B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +VOID +phydm_8822btxbf_rfmode( + IN PVOID pDM_VOID, + IN u1Byte SUBFeeCnt, + IN u1Byte MUBFeeCnt + ); + +VOID +phydm_8822b_sutxbfer_workaroud( + IN PVOID pDM_VOID, + IN BOOLEAN EnableSUBfer, + IN u1Byte Nc, + IN u1Byte Nr, + IN u1Byte Ng, + IN u1Byte CB, + IN u1Byte BW, + IN BOOLEAN isVHT + ); + +#else +#define HalTxbf8822B_Init(pDM_VOID) +#define HalTxbf8822B_Enter(pDM_VOID, Idx) +#define HalTxbf8822B_Leave(pDM_VOID, Idx) +#define HalTxbf8822B_Status(pDM_VOID, Idx) +#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx) +#define HalTxbf8822B_ConfigGtab(pDM_VOID) +#endif + + +#endif +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.c b/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.c index 4fbad2db84f..3ac0b16877e 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.c +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.c @@ -1,1502 +1,1502 @@ -//============================================================ -// Description: -// -// This file is for TXBF interface mechanism -// -//============================================================ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Beamforming_GidPAid( - PADAPTER Adapter, - PRT_TCB pTcb -) -{ - u1Byte Idx = 0; - u1Byte RA[6] ={0}; - pu1Byte pHeader = GET_FRAME_OF_FIRST_FRAG(Adapter, pTcb); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - if (Adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) - return; - else if (IS_WIRELESS_MODE_N(Adapter) == FALSE) - return; - -#if (SUPPORT_MU_BF == 1) - if (pTcb->TxBFPktType == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ -#else - if (0) { -#endif - /* Fill G_ID and P_AID */ - pTcb->G_ID = 63; - if (pBeamInfo->FirstMUBFeeIndex < BEAMFORMEE_ENTRY_NUM) { - pTcb->P_AID = pBeamInfo->BeamformeeEntry[pBeamInfo->FirstMUBFeeIndex].P_AID; - RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID)); - } - } else { - GET_80211_HDR_ADDRESS1(pHeader, &RA); - - // VHT SU PPDU carrying one or more group addressed MPDUs or - // Transmitting a VHT NDP intended for multiple recipients - if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || pTcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { - pTcb->G_ID = 63; - pTcb->P_AID = 0; - } else if (ACTING_AS_AP(Adapter)) { - u2Byte AID = (u2Byte) (MacIdGetOwnerAssociatedClientAID(Adapter, pTcb->macId) & 0x1ff); /*AID[0:8]*/ - - /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s pTcb->macId=0x%X, AID=0x%X\n", __func__, pTcb->macId, AID));*/ - pTcb->G_ID = 63; - - if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ - pTcb->P_AID = 0; - else { /*Sent by an AP and addressed to a STA associated with that AP*/ - u2Byte BSSID = 0; - GET_80211_HDR_ADDRESS2(pHeader, &RA); - BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ - pTcb->P_AID = (AID + BSSID *32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ - } - } else if (ACTING_AS_IBSS(Adapter)) { - pTcb->G_ID = 63; - /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ - pTcb->P_AID = pTcb->macId; - } else if (MgntLinkStatusQuery(Adapter)) { /*Addressed to AP*/ - pTcb->G_ID = 0; - GET_80211_HDR_ADDRESS1(pHeader, &RA); - pTcb->P_AID = RA[5]; /*RA[39:47]*/ - pTcb->P_AID = (pTcb->P_AID << 1) | (RA[4] >> 7 ); - } else { - pTcb->G_ID = 63; - pTcb->P_AID = 0; - } - /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID));*/ - } -} - - -RT_STATUS -Beamforming_GetReportFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - pu1Byte pMIMOCtrlField, pCSIReport, pCSIMatrix; - u1Byte Idx, Nc, Nr, CH_W; - u2Byte CSIMatrixLen = 0; - - ACT_PKT_TYPE pktType = ACT_PKT_TYPE_UNKNOWN; - - //Memory comparison to see if CSI report is the same with previous one - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, Frame_Addr2(*pPduOS), &Idx); - - if (pBeamformEntry == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetReportFrame: Cannot find entry by addr\n")); - return RT_STATUS_FAILURE; - } - - pktType = PacketGetActionFrameType(pPduOS); - - //-@ Modified by David - if (pktType == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { - pMIMOCtrlField = pPduOS->Octet + 26; - Nc = ((*pMIMOCtrlField) & 0x7) + 1; - Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1; - CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); - pCSIMatrix = pMIMOCtrlField + 3 + Nc; //24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) - CSIMatrixLen = pPduOS->Length - 26 -3 -Nc; - } else if (pktType == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { - pMIMOCtrlField = pPduOS->Octet + 26; - Nc = ((*pMIMOCtrlField) & 0x3) + 1; - Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1; - CH_W = (((*pMIMOCtrlField) & 0x10) >> 4); - pCSIMatrix = pMIMOCtrlField + 6 + Nr; //24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) - CSIMatrixLen = pPduOS->Length - 26 -6 -Nr; - } else - return RT_STATUS_SUCCESS; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, Nc=%d, Nr=%d, CH_W=%d\n", __func__, Idx, pktType, Nc, Nr, CH_W)); - - return RT_STATUS_SUCCESS; -} - - -VOID -ConstructHTNDPAPacket( - PADAPTER Adapter, - pu1Byte RA, - pu1Byte Buffer, - pu4Byte pLength, - CHANNEL_WIDTH BW - ) -{ - u2Byte Duration= 0; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - OCTET_STRING pNDPAFrame,ActionContent; - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - - PlatformZeroMemory(Buffer, 32); - - SET_80211_HDR_FRAME_CONTROL(Buffer,0); - - SET_80211_HDR_ORDER(Buffer, 1); - SET_80211_HDR_TYPE_AND_SUBTYPE(Buffer,Type_Action_No_Ack); - - SET_80211_HDR_ADDRESS1(Buffer, RA); - SET_80211_HDR_ADDRESS2(Buffer, Adapter->CurrentAddress); - SET_80211_HDR_ADDRESS3(Buffer, pMgntInfo->Bssid); - - Duration = 2*aSifsTime + 40; - - if (BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; - - SET_80211_HDR_DURATION(Buffer, Duration); - - //HT control field - SET_HT_CTRL_CSI_STEERING(Buffer+sMacHdrLng, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(Buffer+sMacHdrLng, 1); - - FillOctetString(pNDPAFrame, Buffer, sMacHdrLng+sHTCLng); - - FillOctetString(ActionContent, ActionHdr, 4); - PacketAppendData(&pNDPAFrame, ActionContent); - - *pLength = 32; -} - - - - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u4Byte BufLen; - pu1Byte BufAddr; - u1Byte DescLen = 0, Idx = 0, NDPTxRate; - PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamformEntry == NULL) - return FALSE; - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { -#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) - DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; -#endif - BufAddr = pBuf->Buffer.VirtualAddress + DescLen; - - ConstructHTNDPAPacket( - Adapter, - RA, - BufAddr, - &BufLen, - BW - ); - - pTcb->PacketLength = BufLen + DescLen; - - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; - - if(ACTING_AS_IBSS(Adapter) || ACTING_AS_AP(Adapter)) - pTcb->G_ID = 63; - - pTcb->P_AID = pBeamformEntry->P_AID; - pTcb->DataRate = NDPTxRate; /*rate of NDP decide by Nr*/ - - Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructHTNDPAPacket( - Adapter, - RA, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength, - BW - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; - - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - - -VOID -ConstructVHTNDPAPacket( - IN PDM_ODM_T pDM_Odm, - pu1Byte RA, - u2Byte AID, - pu1Byte Buffer, - pu4Byte pLength, - CHANNEL_WIDTH BW - ) -{ - u2Byte Duration= 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - // Frame control. - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); - - SET_80211_HDR_ADDRESS1(pNDPAFrame, RA); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pBeamformEntry->MyMacAddr); - - Duration = 2*aSifsTime + 44; - - if (BW == CHANNEL_WIDTH_80) - Duration += 40; - else if(BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; - - SET_80211_HDR_DURATION(pNDPAFrame, Duration); - - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame+16, &Sequence, 1); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP) == FALSE) - AID = 0; - - STAInfo.AID = AID; - STAInfo.FeedbackType = 0; - STAInfo.NcIndex = 0; - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+17, (pu1Byte)&STAInfo, 2); - - *pLength = 19; -} - - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u4Byte BufLen; - pu1Byte BufAddr; - u1Byte DescLen = 0, Idx = 0, NDPTxRate = 0; - PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamformEntry =phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamformEntry == NULL) - return FALSE; - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { -#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) - DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; -#endif - BufAddr = pBuf->Buffer.VirtualAddress + DescLen; - - ConstructVHTNDPAPacket( - pDM_Odm, - RA, - AID, - BufAddr, - &BufLen, - BW - ); - - pTcb->PacketLength = BufLen + DescLen; - - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) - pTcb->G_ID = 63; - - pTcb->P_AID = pBeamformEntry->P_AID; - pTcb->DataRate = NDPTxRate; /*decide by Nr*/ - - Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTNDPAPacket( - pDM_Odm, - RA, - AID, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength, - BW - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - -#ifdef SUPPORT_MU_BF -#if (SUPPORT_MU_BF == 1) -/* -// Description: On VHT GID management frame by an MU beamformee. -// -// 2015.05.20. Created by tynli. -*/ -RT_STATUS -Beamforming_GetVHTGIDMgntFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - pu1Byte pBuffer = NULL; - pu1Byte pRaddr = NULL; - u1Byte MemStatus[8] = {0}, UserPos[16] = {0}; - u1Byte idx; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMER_ENTRY pBeamformEntry = &pBeamInfo->BeamformerEntry[pBeamInfo->mu_ap_index]; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); - - /* Check length*/ - if (pPduOS->Length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY+16)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Invalid length (%d)\n", pPduOS->Length)); - return RT_STATUS_INVALID_LENGTH; - } - - /* Check RA*/ - pRaddr = (pu1Byte)(pPduOS->Octet)+4; - if (!eqMacAddr(pRaddr, Adapter->CurrentAddress)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Drop because of RA error.\n")); - return RT_STATUS_PKT_DROP; - } - - RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", pPduOS->Octet, pPduOS->Length); - - /*Parsing Membership Status Array*/ - pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; - for (idx = 0; idx < 8; idx++) { - MemStatus[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); - pBeamformEntry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); - } - - RT_DISP_DATA(FBEAM, FBEAM_DATA, "MemStatus: ", MemStatus, 8); - - /* Parsing User Position Array*/ - pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; - for (idx = 0; idx < 16; idx++) { - UserPos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); - pBeamformEntry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); - } - - RT_DISP_DATA(FBEAM, FBEAM_DATA, "UserPos: ", UserPos, 16); - - /* Group ID detail printed*/ - { - u1Byte i, j; - u1Byte tmpVal; - u2Byte tmpVal2; - - for (i = 0; i < 8; i++) { - tmpVal = MemStatus[i]; - tmpVal2 = ((UserPos[i*2 + 1] << 8) & 0xFF00) + (UserPos[i * 2] & 0xFF); - for (j = 0; j < 8; j++) { - if ((tmpVal >> j) & BIT0) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", - (i*8+j), (tmpVal2 >> 2 * j)&0x3)); - } - } - } - } - - /* Indicate GID frame to IHV service. */ - { - u1Byte Indibuffer[24] = {0}; - u1Byte Indioffset = 0; - - PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->gid_valid, 8); - Indioffset += 8; - PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->user_position, 16); - Indioffset += 16; - - PlatformIndicateCustomStatus( - Adapter, - RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME, - RT_CUSTOM_INDI_TARGET_IHV, - Indibuffer, - Indioffset); - } - - /* Config HW GID table */ - halComTxbf_ConfigGtab(pDM_Odm); - - return rtStatus; -} - -/* -// Description: Construct VHT Group ID (GID) management frame. -// -// 2015.05.20. Created by tynli. -*/ -VOID -ConstructVHTGIDMgntFrame( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte RA, - IN PRT_BEAMFORMEE_ENTRY pBeamformEntry, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - -) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - OCTET_STRING osFTMFrame, tmp; - - FillOctetString(osFTMFrame, Buffer, 0); - *pLength = 0; - - ConstructMaFrameHdr( - Adapter, - RA, - ACT_CAT_VHT, - ACT_VHT_GROUPID_MANAGEMENT, - &osFTMFrame); - - /* Membership Status Array*/ - FillOctetString(tmp, pBeamformEntry->gid_valid, 8); - PacketAppendData(&osFTMFrame, tmp); - - /* User Position Array*/ - FillOctetString(tmp, pBeamformEntry->user_position, 16); - PacketAppendData(&osFTMFrame, tmp); - - *pLength = osFTMFrame.Length; - - RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTGIDMgntFrame():\n", Buffer, *pLength); -} - -BOOLEAN -SendSWVHTGIDMgntFrame( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte DataRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = &pBeamInfo->BeamformeeEntry[Idx]; - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTGIDMgntFrame( - pDM_Odm, - RA, - pBeamformEntry, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->BWOfPacket = CHANNEL_WIDTH_20; - DataRate = MGN_6M; - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - -/* -// Description: Construct VHT beamforming report poll. -// -// 2015.05.20. Created by tynli. -*/ -VOID -ConstructVHTBFReportPoll( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte RA, - OUT pu1Byte Buffer, - OUT pu4Byte pLength -) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - pu1Byte pBFRptPoll = Buffer; - - /* Frame control*/ - SET_80211_HDR_FRAME_CONTROL(pBFRptPoll, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pBFRptPoll, Type_Beamforming_Report_Poll); - - /* Duration*/ - SET_80211_HDR_DURATION(pBFRptPoll, 100); - - /* RA*/ - SET_VHT_BF_REPORT_POLL_RA(pBFRptPoll, RA); - - /* TA*/ - SET_VHT_BF_REPORT_POLL_TA(pBFRptPoll, Adapter->CurrentAddress); - - /* Feedback Segment Retransmission Bitmap*/ - SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(pBFRptPoll, 0xFF); - - *pLength = 17; - - RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTBFReportPoll():\n", Buffer, *pLength); - -} - -BOOLEAN -SendSWVHTBFReportPoll( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN BOOLEAN bFinalPoll - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, DataRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTBFReportPoll( - pDM_Odm, - RA, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; /* need?*/ - pTcb->BWOfPacket = CHANNEL_WIDTH_20; - - if (bFinalPoll) - pTcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; - else - pTcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; - - DataRate = MGN_6M; /* Legacy OFDM rate*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "SendSWVHTBFReportPoll():\n", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; - -} - - -/* -// Description: Construct VHT MU NDPA packet. -// We should combine this function with ConstructVHTNDPAPacket() in the future. -// -// 2015.05.21. Created by tynli. -*/ -VOID -ConstructVHTMUNDPAPacket( - IN PDM_ODM_T pDM_Odm, - IN CHANNEL_WIDTH BW, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - ) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - u2Byte Duration = 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - u1Byte idx; - u1Byte DestAddr[6] = {0}; - PRT_BEAMFORMEE_ENTRY pEntry = NULL; - - /* Fill the first MU BFee entry (STA1) MAC addr to destination address then - HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - cpMacAddr(DestAddr, pEntry->MacAddr); - break; - } - } - if (pEntry == NULL) - return; - - /* Frame control.*/ - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); - - SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pEntry->MyMacAddr); - - /*--------------------------------------------*/ - /* Need to modify "Duration" to MU consideration. */ - Duration = 2*aSifsTime + 44; - - if (BW == CHANNEL_WIDTH_80) - Duration += 40; - else if(BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; - /*--------------------------------------------*/ - - SET_80211_HDR_DURATION(pNDPAFrame, Duration); - - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); - - *pLength = 17; - - /* Construct STA info. for multiple STAs*/ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - STAInfo.AID = pEntry->AID; - STAInfo.FeedbackType = 1; /* 1'b1: MU*/ - STAInfo.NcIndex = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); - *pLength += 2; - } - } - -} - -BOOLEAN -SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - NDPTxRate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTMUNDPAPacket( - pDM_Odm, - BW, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - pTcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - -VOID -DBG_ConstructVHTMUNDPAPacket( - IN PDM_ODM_T pDM_Odm, - IN CHANNEL_WIDTH BW, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - ) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - u2Byte Duration = 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - u1Byte idx; - u1Byte DestAddr[6] = {0}; - PRT_BEAMFORMEE_ENTRY pEntry = NULL; - - BOOLEAN is_STA1 = FALSE; - - - /* Fill the first MU BFee entry (STA1) MAC addr to destination address then - HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - if (is_STA1 == FALSE) { - is_STA1 = TRUE; - continue; - } else { - cpMacAddr(DestAddr, pEntry->MacAddr); - break; - } - } - } - - /* Frame control.*/ - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); - - SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pDM_Odm->CurrentAddress); - - /*--------------------------------------------*/ - /* Need to modify "Duration" to MU consideration. */ - Duration = 2*aSifsTime + 44; - - if (BW == CHANNEL_WIDTH_80) - Duration += 40; - else if (BW == CHANNEL_WIDTH_40) - Duration += 87; - else - Duration += 180; - /*--------------------------------------------*/ - - SET_80211_HDR_DURATION(pNDPAFrame, Duration); - - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); - - *pLength = 17; - - /*STA2's STA Info*/ - STAInfo.AID = pEntry->AID; - STAInfo.FeedbackType = 1; /* 1'b1: MU */ - STAInfo.NcIndex = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); - *pLength += 2; - -} - -BOOLEAN -DBG_SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - NDPTxRate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - DBG_ConstructVHTMUNDPAPacket( - pDM_Odm, - BW, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - pTcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); - } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); - - return ret; -} - - -#endif /*#if (SUPPORT_MU_BF == 1)*/ -#endif /*#ifdef SUPPORT_MU_BF*/ - - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -u4Byte -Beamforming_GetReportFrame( - IN PVOID pDM_VOID, - union recv_frame *precv_frame - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte ret = _SUCCESS; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - pu1Byte pframe = precv_frame->u.hdr.rx_data; - u4Byte frame_len = precv_frame->u.hdr.len; - pu1Byte TA; - u1Byte Idx, offset; - - - /*Memory comparison to see if CSI report is the same with previous one*/ - TA = GetAddr2Ptr(pframe); - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, TA, &Idx); - if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ - else if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) - offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ - else - return ret; - - - return ret; -} - - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - u1Byte *pframe; - u2Byte *fctrl; - u2Byte duration = 0; - u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - - if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; - } - - //update attribute - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(Adapter, pattrib); - - pattrib->qsel = QSLT_BEACON; - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - pattrib->rate = NDPTxRate; - pattrib->bwmode = BW; - pattrib->order = 1; - pattrib->subtype = WIFI_ACTION_NOACK; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); - - _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - if( pmlmeext->cur_wireless_mode == WIRELESS_11B) - aSifsTime = 10; - else - aSifsTime = 16; - - duration = 2*aSifsTime + 40; - - if(BW == CHANNEL_WIDTH_40) - duration+= 87; - else - duration+= 180; - - SetDuration(pframe, duration); - - //HT control field - SET_HT_CTRL_CSI_STEERING(pframe+24, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); - - _rtw_memcpy(pframe+28, ActionHdr, 4); - - pattrib->pktlen = 32; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(Adapter, pmgntframe); - - return _TRUE; -} - - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - - if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; - } - - /*update attribute*/ - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(Adapter, pattrib); - pattrib->qsel = QSLT_MGNT; - pattrib->rate = NDPTxRate; - pattrib->bwmode = BW; - pattrib->order = 1; - pattrib->subtype = WIFI_ACTION_NOACK; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); - - _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - if (pmlmeext->cur_wireless_mode == WIRELESS_11B) - aSifsTime = 10; - else - aSifsTime = 16; - - duration = 2*aSifsTime + 40; - - if (BW == CHANNEL_WIDTH_40) - duration += 87; - else - duration += 180; - - SetDuration(pframe, duration); - - /*HT control field*/ - SET_HT_CTRL_CSI_STEERING(pframe+24, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); - - _rtw_memcpy(pframe+28, ActionHdr, 4); - - pattrib->pktlen = 32; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(Adapter, pmgntframe); - - return _TRUE; -} - - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - u1Byte sequence = 0, aSifsTime = 0, NDPTxRate= 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - RT_NDPA_STA_INFO sta_info; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - - if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; - } - - //update attribute - pattrib = &pmgntframe->attrib; - _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); - update_mgntframe_attrib(Adapter, pattrib); - - pattrib->qsel = QSLT_BEACON; - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - pattrib->rate = NDPTxRate; - pattrib->bwmode = BW; - pattrib->subtype = WIFI_NDPA; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - - SetFrameSubType(pframe, WIFI_NDPA); - - _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); - - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) - aSifsTime = 16; - else - aSifsTime = 10; - - duration = 2*aSifsTime + 44; - - if(BW == CHANNEL_WIDTH_80) - duration += 40; - else if(BW == CHANNEL_WIDTH_40) - duration+= 87; - else - duration+= 180; - - SetDuration(pframe, duration); - - sequence = pBeamInfo->SoundingSequence<< 2; - if (pBeamInfo->SoundingSequence >= 0x3f) - pBeamInfo->SoundingSequence = 0; - else - pBeamInfo->SoundingSequence++; - - _rtw_memcpy(pframe+16, &sequence,1); - - if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) - AID = 0; - - sta_info.AID = AID; - sta_info.FeedbackType = 0; - sta_info.NcIndex= 0; - - _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); - - pattrib->pktlen = 19; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(Adapter, pmgntframe); - - return _TRUE; -} - - - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - RT_NDPA_STA_INFO ndpa_sta_info; - u1Byte NDPTxRate = 0, sequence = 0, aSifsTime = 0, Idx = 0; - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - - if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; - } - - /*update attribute*/ - pattrib = &pmgntframe->attrib; - _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); - update_mgntframe_attrib(Adapter, pattrib); - pattrib->qsel = QSLT_MGNT; - pattrib->rate = NDPTxRate; - pattrib->bwmode = BW; - pattrib->subtype = WIFI_NDPA; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - - SetFrameSubType(pframe, WIFI_NDPA); - - _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); - - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) - aSifsTime = 16; - else - aSifsTime = 10; - - duration = 2*aSifsTime + 44; - - if (BW == CHANNEL_WIDTH_80) - duration += 40; - else if (BW == CHANNEL_WIDTH_40) - duration += 87; - else - duration += 180; - - SetDuration(pframe, duration); - - sequence = pBeamInfo->SoundingSequence << 2; - if (pBeamInfo->SoundingSequence >= 0x3f) - pBeamInfo->SoundingSequence = 0; - else - pBeamInfo->SoundingSequence++; - - _rtw_memcpy(pframe+16, &sequence, 1); - if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) - AID = 0; - - ndpa_sta_info.AID = AID; - ndpa_sta_info.FeedbackType = 0; - ndpa_sta_info.NcIndex = 0; - - _rtw_memcpy(pframe+17, (u8 *)&ndpa_sta_info, 2); - - pattrib->pktlen = 19; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(Adapter, pmgntframe); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); - - return _TRUE; -} - - -#endif - - -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN OCTET_STRING pduOS -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - union recv_frame *precv_frame -#endif -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - pu1Byte TA ; - u1Byte Idx, Sequence; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pu1Byte pNDPAFrame = pduOS.Octet; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pu1Byte pNDPAFrame = precv_frame->u.hdr.rx_data; -#endif - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; /*Modified By Jeffery @2014-10-29*/ - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "Beamforming_GetNDPAFrame\n", pduOS.Octet, pduOS.Length); - if (IsCtrlNDPA(pNDPAFrame) == FALSE) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (GetFrameSubType(pNDPAFrame) != WIFI_NDPA) -#endif - return; - else if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821))) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); - return; - } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - TA = Frame_Addr2(pduOS); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - TA = GetAddr2Ptr(pNDPAFrame); -#endif - /*Remove signaling TA. */ - TA[0] = TA[0] & 0xFE; - - pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, TA, &Idx); // Modified By Jeffery @2014-10-29 - - /*Break options for Clock Reset*/ - if (pBeamformerEntry == NULL) - return; - else if (!(pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)) - return; - /*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ - /*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/ - else if ((pBeamformerEntry->LogSuccess == 1) || (pBeamformerEntry->ClockResetTimes == 5)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, LogSuccess=%d, ClockResetTimes=%d, clock reset is no longer needed.\n", - __func__, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->LogSuccess, pBeamformerEntry->ClockResetTimes)); - - return; - } - - Sequence = (pNDPAFrame[16]) >> 2; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n", - __func__, Sequence, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->ClockResetTimes, pBeamformerEntry->LogSuccess)); - - if ((pBeamformerEntry->LogSeq != 0) && (pBeamformerEntry->PreLogSeq != 0)) { - /*Success condition*/ - if ((pBeamformerEntry->LogSeq != Sequence) && (pBeamformerEntry->PreLogSeq != pBeamformerEntry->LogSeq)) { - /* break option for clcok reset, 2015-03-30, Jeffery */ - pBeamformerEntry->LogRetryCnt = 0; - /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ - /*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ - pBeamformerEntry->LogSuccess = 1; - - } else {/*Fail condition*/ - - if (pBeamformerEntry->LogRetryCnt == 5) { - pBeamformerEntry->ClockResetTimes++; - pBeamformerEntry->LogRetryCnt = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! ClockResetTimes=%d\n", - __func__, pBeamformerEntry->ClockResetTimes)); - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_CLK, NULL); - - } else - pBeamformerEntry->LogRetryCnt++; - } - } - - /*Update LogSeq & PreLogSeq*/ - pBeamformerEntry->PreLogSeq = pBeamformerEntry->LogSeq; - pBeamformerEntry->LogSeq = Sequence; - -} - - - -#endif +//============================================================ +// Description: +// +// This file is for TXBF interface mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Beamforming_GidPAid( + PADAPTER Adapter, + PRT_TCB pTcb +) +{ + u1Byte Idx = 0; + u1Byte RA[6] ={0}; + pu1Byte pHeader = GET_FRAME_OF_FIRST_FRAG(Adapter, pTcb); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + if (Adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) + return; + else if (IS_WIRELESS_MODE_N(Adapter) == FALSE) + return; + +#if (SUPPORT_MU_BF == 1) + if (pTcb->TxBFPktType == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ +#else + if (0) { +#endif + /* Fill G_ID and P_AID */ + pTcb->G_ID = 63; + if (pBeamInfo->FirstMUBFeeIndex < BEAMFORMEE_ENTRY_NUM) { + pTcb->P_AID = pBeamInfo->BeamformeeEntry[pBeamInfo->FirstMUBFeeIndex].P_AID; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID)); + } + } else { + GET_80211_HDR_ADDRESS1(pHeader, &RA); + + // VHT SU PPDU carrying one or more group addressed MPDUs or + // Transmitting a VHT NDP intended for multiple recipients + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || pTcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + pTcb->G_ID = 63; + pTcb->P_AID = 0; + } else if (ACTING_AS_AP(Adapter)) { + u2Byte AID = (u2Byte) (MacIdGetOwnerAssociatedClientAID(Adapter, pTcb->macId) & 0x1ff); /*AID[0:8]*/ + + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s pTcb->macId=0x%X, AID=0x%X\n", __func__, pTcb->macId, AID));*/ + pTcb->G_ID = 63; + + if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ + pTcb->P_AID = 0; + else { /*Sent by an AP and addressed to a STA associated with that AP*/ + u2Byte BSSID = 0; + GET_80211_HDR_ADDRESS2(pHeader, &RA); + BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ + pTcb->P_AID = (AID + BSSID *32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ + } + } else if (ACTING_AS_IBSS(Adapter)) { + pTcb->G_ID = 63; + /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ + pTcb->P_AID = pTcb->macId; + } else if (MgntLinkStatusQuery(Adapter)) { /*Addressed to AP*/ + pTcb->G_ID = 0; + GET_80211_HDR_ADDRESS1(pHeader, &RA); + pTcb->P_AID = RA[5]; /*RA[39:47]*/ + pTcb->P_AID = (pTcb->P_AID << 1) | (RA[4] >> 7 ); + } else { + pTcb->G_ID = 63; + pTcb->P_AID = 0; + } + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID));*/ + } +} + + +RT_STATUS +Beamforming_GetReportFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + pu1Byte pMIMOCtrlField, pCSIReport, pCSIMatrix; + u1Byte Idx, Nc, Nr, CH_W; + u2Byte CSIMatrixLen = 0; + + ACT_PKT_TYPE pktType = ACT_PKT_TYPE_UNKNOWN; + + //Memory comparison to see if CSI report is the same with previous one + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, Frame_Addr2(*pPduOS), &Idx); + + if (pBeamformEntry == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetReportFrame: Cannot find entry by addr\n")); + return RT_STATUS_FAILURE; + } + + pktType = PacketGetActionFrameType(pPduOS); + + //-@ Modified by David + if (pktType == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { + pMIMOCtrlField = pPduOS->Octet + 26; + Nc = ((*pMIMOCtrlField) & 0x7) + 1; + Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1; + CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); + pCSIMatrix = pMIMOCtrlField + 3 + Nc; //24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) + CSIMatrixLen = pPduOS->Length - 26 -3 -Nc; + } else if (pktType == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { + pMIMOCtrlField = pPduOS->Octet + 26; + Nc = ((*pMIMOCtrlField) & 0x3) + 1; + Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1; + CH_W = (((*pMIMOCtrlField) & 0x10) >> 4); + pCSIMatrix = pMIMOCtrlField + 6 + Nr; //24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) + CSIMatrixLen = pPduOS->Length - 26 -6 -Nr; + } else + return RT_STATUS_SUCCESS; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, Nc=%d, Nr=%d, CH_W=%d\n", __func__, Idx, pktType, Nc, Nr, CH_W)); + + return RT_STATUS_SUCCESS; +} + + +VOID +ConstructHTNDPAPacket( + PADAPTER Adapter, + pu1Byte RA, + pu1Byte Buffer, + pu4Byte pLength, + CHANNEL_WIDTH BW + ) +{ + u2Byte Duration= 0; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + OCTET_STRING pNDPAFrame,ActionContent; + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + + PlatformZeroMemory(Buffer, 32); + + SET_80211_HDR_FRAME_CONTROL(Buffer,0); + + SET_80211_HDR_ORDER(Buffer, 1); + SET_80211_HDR_TYPE_AND_SUBTYPE(Buffer,Type_Action_No_Ack); + + SET_80211_HDR_ADDRESS1(Buffer, RA); + SET_80211_HDR_ADDRESS2(Buffer, Adapter->CurrentAddress); + SET_80211_HDR_ADDRESS3(Buffer, pMgntInfo->Bssid); + + Duration = 2*aSifsTime + 40; + + if (BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + + SET_80211_HDR_DURATION(Buffer, Duration); + + //HT control field + SET_HT_CTRL_CSI_STEERING(Buffer+sMacHdrLng, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(Buffer+sMacHdrLng, 1); + + FillOctetString(pNDPAFrame, Buffer, sMacHdrLng+sHTCLng); + + FillOctetString(ActionContent, ActionHdr, 4); + PacketAppendData(&pNDPAFrame, ActionContent); + + *pLength = 32; +} + + + + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u4Byte BufLen; + pu1Byte BufAddr; + u1Byte DescLen = 0, Idx = 0, NDPTxRate; + PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamformEntry == NULL) + return FALSE; + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { +#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) + DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; +#endif + BufAddr = pBuf->Buffer.VirtualAddress + DescLen; + + ConstructHTNDPAPacket( + Adapter, + RA, + BufAddr, + &BufLen, + BW + ); + + pTcb->PacketLength = BufLen + DescLen; + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + if(ACTING_AS_IBSS(Adapter) || ACTING_AS_AP(Adapter)) + pTcb->G_ID = 63; + + pTcb->P_AID = pBeamformEntry->P_AID; + pTcb->DataRate = NDPTxRate; /*rate of NDP decide by Nr*/ + + Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructHTNDPAPacket( + Adapter, + RA, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength, + BW + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + + +VOID +ConstructVHTNDPAPacket( + IN PDM_ODM_T pDM_Odm, + pu1Byte RA, + u2Byte AID, + pu1Byte Buffer, + pu4Byte pLength, + CHANNEL_WIDTH BW + ) +{ + u2Byte Duration= 0; + u1Byte Sequence = 0; + pu1Byte pNDPAFrame = Buffer; + RT_NDPA_STA_INFO STAInfo; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + // Frame control. + SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(pNDPAFrame, RA); + SET_80211_HDR_ADDRESS2(pNDPAFrame, pBeamformEntry->MyMacAddr); + + Duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + Duration += 40; + else if(BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + + SET_80211_HDR_DURATION(pNDPAFrame, Duration); + + Sequence = *(pDM_Odm->pSoundingSeq) << 2; + ODM_MoveMemory(pDM_Odm, pNDPAFrame+16, &Sequence, 1); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP) == FALSE) + AID = 0; + + STAInfo.AID = AID; + STAInfo.FeedbackType = 0; + STAInfo.NcIndex = 0; + + ODM_MoveMemory(pDM_Odm, pNDPAFrame+17, (pu1Byte)&STAInfo, 2); + + *pLength = 19; +} + + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u4Byte BufLen; + pu1Byte BufAddr; + u1Byte DescLen = 0, Idx = 0, NDPTxRate = 0; + PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamformEntry =phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamformEntry == NULL) + return FALSE; + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { +#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) + DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; +#endif + BufAddr = pBuf->Buffer.VirtualAddress + DescLen; + + ConstructVHTNDPAPacket( + pDM_Odm, + RA, + AID, + BufAddr, + &BufLen, + BW + ); + + pTcb->PacketLength = BufLen + DescLen; + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) + pTcb->G_ID = 63; + + pTcb->P_AID = pBeamformEntry->P_AID; + pTcb->DataRate = NDPTxRate; /*decide by Nr*/ + + Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTNDPAPacket( + pDM_Odm, + RA, + AID, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength, + BW + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + pTcb->BWOfPacket = BW; + + /*rate of NDP decide by Nr*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +/* +// Description: On VHT GID management frame by an MU beamformee. +// +// 2015.05.20. Created by tynli. +*/ +RT_STATUS +Beamforming_GetVHTGIDMgntFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + pu1Byte pBuffer = NULL; + pu1Byte pRaddr = NULL; + u1Byte MemStatus[8] = {0}, UserPos[16] = {0}; + u1Byte idx; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMER_ENTRY pBeamformEntry = &pBeamInfo->BeamformerEntry[pBeamInfo->mu_ap_index]; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); + + /* Check length*/ + if (pPduOS->Length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY+16)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Invalid length (%d)\n", pPduOS->Length)); + return RT_STATUS_INVALID_LENGTH; + } + + /* Check RA*/ + pRaddr = (pu1Byte)(pPduOS->Octet)+4; + if (!eqMacAddr(pRaddr, Adapter->CurrentAddress)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Drop because of RA error.\n")); + return RT_STATUS_PKT_DROP; + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", pPduOS->Octet, pPduOS->Length); + + /*Parsing Membership Status Array*/ + pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; + for (idx = 0; idx < 8; idx++) { + MemStatus[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); + pBeamformEntry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "MemStatus: ", MemStatus, 8); + + /* Parsing User Position Array*/ + pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; + for (idx = 0; idx < 16; idx++) { + UserPos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); + pBeamformEntry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "UserPos: ", UserPos, 16); + + /* Group ID detail printed*/ + { + u1Byte i, j; + u1Byte tmpVal; + u2Byte tmpVal2; + + for (i = 0; i < 8; i++) { + tmpVal = MemStatus[i]; + tmpVal2 = ((UserPos[i*2 + 1] << 8) & 0xFF00) + (UserPos[i * 2] & 0xFF); + for (j = 0; j < 8; j++) { + if ((tmpVal >> j) & BIT0) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", + (i*8+j), (tmpVal2 >> 2 * j)&0x3)); + } + } + } + } + + /* Indicate GID frame to IHV service. */ + { + u1Byte Indibuffer[24] = {0}; + u1Byte Indioffset = 0; + + PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->gid_valid, 8); + Indioffset += 8; + PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->user_position, 16); + Indioffset += 16; + + PlatformIndicateCustomStatus( + Adapter, + RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME, + RT_CUSTOM_INDI_TARGET_IHV, + Indibuffer, + Indioffset); + } + + /* Config HW GID table */ + halComTxbf_ConfigGtab(pDM_Odm); + + return rtStatus; +} + +/* +// Description: Construct VHT Group ID (GID) management frame. +// +// 2015.05.20. Created by tynli. +*/ +VOID +ConstructVHTGIDMgntFrame( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte RA, + IN PRT_BEAMFORMEE_ENTRY pBeamformEntry, + OUT pu1Byte Buffer, + OUT pu4Byte pLength + +) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + OCTET_STRING osFTMFrame, tmp; + + FillOctetString(osFTMFrame, Buffer, 0); + *pLength = 0; + + ConstructMaFrameHdr( + Adapter, + RA, + ACT_CAT_VHT, + ACT_VHT_GROUPID_MANAGEMENT, + &osFTMFrame); + + /* Membership Status Array*/ + FillOctetString(tmp, pBeamformEntry->gid_valid, 8); + PacketAppendData(&osFTMFrame, tmp); + + /* User Position Array*/ + FillOctetString(tmp, pBeamformEntry->user_position, 16); + PacketAppendData(&osFTMFrame, tmp); + + *pLength = osFTMFrame.Length; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTGIDMgntFrame():\n", Buffer, *pLength); +} + +BOOLEAN +SendSWVHTGIDMgntFrame( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte DataRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = &pBeamInfo->BeamformeeEntry[Idx]; + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTGIDMgntFrame( + pDM_Odm, + RA, + pBeamformEntry, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->BWOfPacket = CHANNEL_WIDTH_20; + DataRate = MGN_6M; + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +/* +// Description: Construct VHT beamforming report poll. +// +// 2015.05.20. Created by tynli. +*/ +VOID +ConstructVHTBFReportPoll( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte RA, + OUT pu1Byte Buffer, + OUT pu4Byte pLength +) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + pu1Byte pBFRptPoll = Buffer; + + /* Frame control*/ + SET_80211_HDR_FRAME_CONTROL(pBFRptPoll, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pBFRptPoll, Type_Beamforming_Report_Poll); + + /* Duration*/ + SET_80211_HDR_DURATION(pBFRptPoll, 100); + + /* RA*/ + SET_VHT_BF_REPORT_POLL_RA(pBFRptPoll, RA); + + /* TA*/ + SET_VHT_BF_REPORT_POLL_TA(pBFRptPoll, Adapter->CurrentAddress); + + /* Feedback Segment Retransmission Bitmap*/ + SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(pBFRptPoll, 0xFF); + + *pLength = 17; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTBFReportPoll():\n", Buffer, *pLength); + +} + +BOOLEAN +SendSWVHTBFReportPoll( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN BOOLEAN bFinalPoll + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, DataRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTBFReportPoll( + pDM_Odm, + RA, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->bTxEnableSwCalcDur = TRUE; /* need?*/ + pTcb->BWOfPacket = CHANNEL_WIDTH_20; + + if (bFinalPoll) + pTcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + else + pTcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + + DataRate = MGN_6M; /* Legacy OFDM rate*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "SendSWVHTBFReportPoll():\n", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; + +} + + +/* +// Description: Construct VHT MU NDPA packet. +// We should combine this function with ConstructVHTNDPAPacket() in the future. +// +// 2015.05.21. Created by tynli. +*/ +VOID +ConstructVHTMUNDPAPacket( + IN PDM_ODM_T pDM_Odm, + IN CHANNEL_WIDTH BW, + OUT pu1Byte Buffer, + OUT pu4Byte pLength + ) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + u2Byte Duration = 0; + u1Byte Sequence = 0; + pu1Byte pNDPAFrame = Buffer; + RT_NDPA_STA_INFO STAInfo; + u1Byte idx; + u1Byte DestAddr[6] = {0}; + PRT_BEAMFORMEE_ENTRY pEntry = NULL; + + /* Fill the first MU BFee entry (STA1) MAC addr to destination address then + HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + cpMacAddr(DestAddr, pEntry->MacAddr); + break; + } + } + if (pEntry == NULL) + return; + + /* Frame control.*/ + SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); + SET_80211_HDR_ADDRESS2(pNDPAFrame, pEntry->MyMacAddr); + + /*--------------------------------------------*/ + /* Need to modify "Duration" to MU consideration. */ + Duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + Duration += 40; + else if(BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + /*--------------------------------------------*/ + + SET_80211_HDR_DURATION(pNDPAFrame, Duration); + + Sequence = *(pDM_Odm->pSoundingSeq) << 2; + ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); + + *pLength = 17; + + /* Construct STA info. for multiple STAs*/ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + STAInfo.AID = pEntry->AID; + STAInfo.FeedbackType = 1; /* 1'b1: MU*/ + STAInfo.NcIndex = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); + + ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); + *pLength += 2; + } + } + +} + +BOOLEAN +SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + NDPTxRate = MGN_VHT2SS_MCS0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTMUNDPAPacket( + pDM_Odm, + BW, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + pTcb->BWOfPacket = BW; + pTcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + + /*rate of NDP decide by Nr*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +VOID +DBG_ConstructVHTMUNDPAPacket( + IN PDM_ODM_T pDM_Odm, + IN CHANNEL_WIDTH BW, + OUT pu1Byte Buffer, + OUT pu4Byte pLength + ) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + u2Byte Duration = 0; + u1Byte Sequence = 0; + pu1Byte pNDPAFrame = Buffer; + RT_NDPA_STA_INFO STAInfo; + u1Byte idx; + u1Byte DestAddr[6] = {0}; + PRT_BEAMFORMEE_ENTRY pEntry = NULL; + + BOOLEAN is_STA1 = FALSE; + + + /* Fill the first MU BFee entry (STA1) MAC addr to destination address then + HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + if (is_STA1 == FALSE) { + is_STA1 = TRUE; + continue; + } else { + cpMacAddr(DestAddr, pEntry->MacAddr); + break; + } + } + } + + /* Frame control.*/ + SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); + SET_80211_HDR_ADDRESS2(pNDPAFrame, pDM_Odm->CurrentAddress); + + /*--------------------------------------------*/ + /* Need to modify "Duration" to MU consideration. */ + Duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + Duration += 40; + else if (BW == CHANNEL_WIDTH_40) + Duration += 87; + else + Duration += 180; + /*--------------------------------------------*/ + + SET_80211_HDR_DURATION(pNDPAFrame, Duration); + + Sequence = *(pDM_Odm->pSoundingSeq) << 2; + ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); + + *pLength = 17; + + /*STA2's STA Info*/ + STAInfo.AID = pEntry->AID; + STAInfo.FeedbackType = 1; /* 1'b1: MU */ + STAInfo.NcIndex = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); + + ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); + *pLength += 2; + +} + +BOOLEAN +DBG_SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + NDPTxRate = MGN_VHT2SS_MCS0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + DBG_ConstructVHTMUNDPAPacket( + pDM_Odm, + BW, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + pTcb->BWOfPacket = BW; + pTcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; + + /*rate of NDP decide by Nr*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +#endif /*#if (SUPPORT_MU_BF == 1)*/ +#endif /*#ifdef SUPPORT_MU_BF*/ + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u4Byte +Beamforming_GetReportFrame( + IN PVOID pDM_VOID, + union recv_frame *precv_frame + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte ret = _SUCCESS; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + pu1Byte pframe = precv_frame->u.hdr.rx_data; + u4Byte frame_len = precv_frame->u.hdr.len; + pu1Byte TA; + u1Byte Idx, offset; + + + /*Memory comparison to see if CSI report is the same with previous one*/ + TA = GetAddr2Ptr(pframe); + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, TA, &Idx); + if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else + return ret; + + + return ret; +} + + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u1Byte *pframe; + u2Byte *fctrl; + u2Byte duration = 0; + u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + return _FALSE; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if( pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if(BW == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + //HT control field + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + return _FALSE; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + /*HT control field*/ + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + u1Byte sequence = 0, aSifsTime = 0, NDPTxRate= 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + RT_NDPA_STA_INFO sta_info; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + return _FALSE; + } + + //update attribute + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(Adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if(BW == CHANNEL_WIDTH_80) + duration += 40; + else if(BW == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->SoundingSequence<< 2; + if (pBeamInfo->SoundingSequence >= 0x3f) + pBeamInfo->SoundingSequence = 0; + else + pBeamInfo->SoundingSequence++; + + _rtw_memcpy(pframe+16, &sequence,1); + + if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + sta_info.AID = AID; + sta_info.FeedbackType = 0; + sta_info.NcIndex= 0; + + _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + RT_NDPA_STA_INFO ndpa_sta_info; + u1Byte NDPTxRate = 0, sequence = 0, aSifsTime = 0, Idx = 0; + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + return _FALSE; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->SoundingSequence << 2; + if (pBeamInfo->SoundingSequence >= 0x3f) + pBeamInfo->SoundingSequence = 0; + else + pBeamInfo->SoundingSequence++; + + _rtw_memcpy(pframe+16, &sequence, 1); + if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + ndpa_sta_info.AID = AID; + ndpa_sta_info.FeedbackType = 0; + ndpa_sta_info.NcIndex = 0; + + _rtw_memcpy(pframe+17, (u8 *)&ndpa_sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); + + return _TRUE; +} + + +#endif + + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN OCTET_STRING pduOS +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + pu1Byte TA ; + u1Byte Idx, Sequence; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pu1Byte pNDPAFrame = pduOS.Octet; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pu1Byte pNDPAFrame = precv_frame->u.hdr.rx_data; +#endif + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; /*Modified By Jeffery @2014-10-29*/ + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "Beamforming_GetNDPAFrame\n", pduOS.Octet, pduOS.Length); + if (IsCtrlNDPA(pNDPAFrame) == FALSE) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (GetFrameSubType(pNDPAFrame) != WIFI_NDPA) +#endif + return; + else if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821))) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); + return; + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + TA = Frame_Addr2(pduOS); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + TA = GetAddr2Ptr(pNDPAFrame); +#endif + /*Remove signaling TA. */ + TA[0] = TA[0] & 0xFE; + + pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, TA, &Idx); // Modified By Jeffery @2014-10-29 + + /*Break options for Clock Reset*/ + if (pBeamformerEntry == NULL) + return; + else if (!(pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)) + return; + /*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/ + else if ((pBeamformerEntry->LogSuccess == 1) || (pBeamformerEntry->ClockResetTimes == 5)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, LogSuccess=%d, ClockResetTimes=%d, clock reset is no longer needed.\n", + __func__, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->LogSuccess, pBeamformerEntry->ClockResetTimes)); + + return; + } + + Sequence = (pNDPAFrame[16]) >> 2; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n", + __func__, Sequence, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->ClockResetTimes, pBeamformerEntry->LogSuccess)); + + if ((pBeamformerEntry->LogSeq != 0) && (pBeamformerEntry->PreLogSeq != 0)) { + /*Success condition*/ + if ((pBeamformerEntry->LogSeq != Sequence) && (pBeamformerEntry->PreLogSeq != pBeamformerEntry->LogSeq)) { + /* break option for clcok reset, 2015-03-30, Jeffery */ + pBeamformerEntry->LogRetryCnt = 0; + /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ + /*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ + pBeamformerEntry->LogSuccess = 1; + + } else {/*Fail condition*/ + + if (pBeamformerEntry->LogRetryCnt == 5) { + pBeamformerEntry->ClockResetTimes++; + pBeamformerEntry->LogRetryCnt = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! ClockResetTimes=%d\n", + __func__, pBeamformerEntry->ClockResetTimes)); + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_CLK, NULL); + + } else + pBeamformerEntry->LogRetryCnt++; + } + } + + /*Update LogSeq & PreLogSeq*/ + pBeamformerEntry->PreLogSeq = pBeamformerEntry->LogSeq; + pBeamformerEntry->LogSeq = Sequence; + +} + + + +#endif diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.h b/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.h index 0e5134707eb..6f0b4270a3a 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.h +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbfinterface.h @@ -1,162 +1,162 @@ -#ifndef __HAL_TXBF_INTERFACE_H__ -#define __HAL_TXBF_INTERFACE_H__ - -#if (BEAMFORMING_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Beamforming_GidPAid( - PADAPTER Adapter, - PRT_TCB pTcb - ); - -RT_STATUS -Beamforming_GetReportFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ); - -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, - IN OCTET_STRING pduOS - ); - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -#if (SUPPORT_MU_BF == 1) -RT_STATUS -Beamforming_GetVHTGIDMgntFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ); - -BOOLEAN -SendSWVHTGIDMgntFrame( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u1Byte Idx - ); - -BOOLEAN -SendSWVHTBFReportPoll( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN BOOLEAN bFinalPoll - ); - -BOOLEAN -SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ); -#else -#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE -#define SendSWVHTGIDMgntFrame(pDM_VOID, RA) -#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) -#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) -#endif - - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -u4Byte -Beamforming_GetReportFrame( - IN PVOID pDM_VOID, - union recv_frame *precv_frame - ); - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); -#endif - -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN OCTET_STRING pduOS -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - union recv_frame *precv_frame -#endif -); - -BOOLEAN -DBG_SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ); - -#else -#define Beamforming_GetNDPAFrame(pDM_Odm, _PduOS) -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define Beamforming_GetReportFrame(Adapter, precv_frame) RT_STATUS_FAILURE -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define Beamforming_GetReportFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE -#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE -#endif -#define SendFWHTNDPAPacket(pDM_VOID, RA, BW) -#define SendSWHTNDPAPacket(pDM_VOID, RA, BW) -#define SendFWVHTNDPAPacket(pDM_VOID, RA, AID, BW) -#define SendSWVHTNDPAPacket(pDM_VOID, RA, AID, BW) -#define SendSWVHTGIDMgntFrame(pDM_VOID, RA, idx) -#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) -#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) -#endif - -#endif +#ifndef __HAL_TXBF_INTERFACE_H__ +#define __HAL_TXBF_INTERFACE_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Beamforming_GidPAid( + PADAPTER Adapter, + PRT_TCB pTcb + ); + +RT_STATUS +Beamforming_GetReportFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ); + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, + IN OCTET_STRING pduOS + ); + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +#if (SUPPORT_MU_BF == 1) +RT_STATUS +Beamforming_GetVHTGIDMgntFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ); + +BOOLEAN +SendSWVHTGIDMgntFrame( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u1Byte Idx + ); + +BOOLEAN +SendSWVHTBFReportPoll( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN BOOLEAN bFinalPoll + ); + +BOOLEAN +SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ); +#else +#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#define SendSWVHTGIDMgntFrame(pDM_VOID, RA) +#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) +#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#endif + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u4Byte +Beamforming_GetReportFrame( + IN PVOID pDM_VOID, + union recv_frame *precv_frame + ); + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); +#endif + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN OCTET_STRING pduOS +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif +); + +BOOLEAN +DBG_SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ); + +#else +#define Beamforming_GetNDPAFrame(pDM_Odm, _PduOS) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define Beamforming_GetReportFrame(Adapter, precv_frame) RT_STATUS_FAILURE +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define Beamforming_GetReportFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#endif +#define SendFWHTNDPAPacket(pDM_VOID, RA, BW) +#define SendSWHTNDPAPacket(pDM_VOID, RA, BW) +#define SendFWVHTNDPAPacket(pDM_VOID, RA, AID, BW) +#define SendSWVHTNDPAPacket(pDM_VOID, RA, AID, BW) +#define SendSWVHTGIDMgntFrame(pDM_VOID, RA, idx) +#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) +#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#endif + +#endif diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.c b/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.c index e1253710f69..e1651f67d05 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.c +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.c @@ -1,527 +1,527 @@ -//============================================================ -// Description: -// -// This file is for 8812/8821/8811 TXBF mechanism -// -//============================================================ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) -VOID -HalTxbf8812A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW)); - -} - -VOID -halTxbfJaguar_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->RFType == ODM_1T1R) - return; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ - - if (pBeamInfo->beamformee_su_cnt > 0) { - // Paath_A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ - // Path_B - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ - } else { - // Paath_A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ - // Path_B - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ - } - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ - - if (pBeamInfo->beamformee_su_cnt > 0) - ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); - else - ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); -} - - -VOID -halTxbfJaguar_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - BOOLEAN bSendBeacon = FALSE; - u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - PADAPTER Adapter = pDM_Odm->Adapter; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; -#endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (Idx == 0) - Head_Page = 0xFE; - else - Head_Page = 0xFE; - - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); - - /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0)); - - - /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6)); - - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n")); - bSendBeacon = TRUE; - } - - /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page); - - do { - /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0)); - - /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); - else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); - - /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); - count = 0; - while (!(BcnValidReg & BIT0) && count < 20) { - count++; - ODM_delay_ms(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); - } - DLBcnCount++; - } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); - - if (!(BcnValidReg & BIT0)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); - - /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy); - - /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ - /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ - /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422); - - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0))); - - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; -#endif -} - - -VOID -halTxbfJaguar_FwTxBFCmd( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period0 = 0, Period1 = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - /*Modified by David*/ - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (Idx == 0) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) - PageNum0 = 0xFE; - else - PageNum0 = 0xFF; /*stop sounding*/ - Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (Idx == 1) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) - PageNum1 = 0xFE; - else - PageNum1 = 0xFF; /*stop sounding*/ - Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } - } - } - - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = (Period1 << 4) | Period0; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); -} - - -VOID -HalTxbfJaguar_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u4Byte CSI_Param; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); - - halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); - - if (pDM_Odm->RFType == ODM_2T2R) - ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/ - else - ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/ - - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; - - /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); - - /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]); - /*CSI report use legacy ofdm so don't need to fill P_AID. */ - /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */ - } else { - for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]); - /*CSI report use legacy ofdm so don't need to fill P_AID.*/ - /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/ - } - - /*CSI report parameters of Beamformee*/ - if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) { - if (pDM_Odm->RFType == ODM_2T2R) - CSI_Param = 0x01090109; - else - CSI_Param = 0x01080108; - } else { - if (pDM_Odm->RFType == ODM_2T2R) - CSI_Param = 0x03090309; - else - CSI_Param = 0x03080308; - } - - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param); - - /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); - } - - - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; - else - STAid = BeamformeeEntry.P_AID; - - /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7); - } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15); - - /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { - /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9); - } else { - /*Set BIT25*/ - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200); - } - phydm_Beamforming_Notify(pDM_Odm); - } -} - - -VOID -HalTxbfJaguar_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMER_ENTRY BeamformerEntry; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; - } else - return; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx)); - - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ - - if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); - if (Idx == 0) { - ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); - } else { - ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); - } - } - - if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60); - } - } - -} - - -VOID -HalTxbfJaguar_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; - else - BeamCtrlVal = BeamformEntry.P_AID; - - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8812A; - else { - BeamCtrlReg = REG_TXBF_CTRL_8812A + 2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; - } - - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9 | BIT10); - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9 | BIT10 | BIT11); - } else - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal)); - - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); -} - - - -VOID -HalTxbfJaguar_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx); - - halTxbfJaguar_FwTxBFCmd(pDM_Odm); -} - - -VOID -HalTxbfJaguar_Patch( - IN PVOID pDM_VOID, - IN u1Byte Operation -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) - return; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (Operation == SCAN_OPT_BACKUP_BAND0) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); - else if (Operation == SCAN_OPT_RESTORE) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); -#endif -} - -VOID -HalTxbfJaguar_Clk_8812A( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte u2btmp; - u1Byte Count = 0, u1btmp; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (*(pDM_Odm->pbScanInProcess)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); - return; - } -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - /*Stop PCIe TxDMA*/ - ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); -#endif - - /*Stop Usb TxDMA*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISABLE_FUNC(Adapter, DF_TX_BIT); - PlatformReturnAllPendingTxPackets(Adapter); -#else - rtw_write_port_cancel(Adapter); -#endif - - /*Wait TXFF empty*/ - for (Count = 0; Count < 100; Count++) { - u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A); - u2btmp = u2btmp & 0xfff; - if (u2btmp != 0xfff) { - ODM_delay_ms(10); - continue; - } else - break; - } - - /*TX pause*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); - - /*Wait TX State Machine OK*/ - for (Count = 0; Count < 100; Count++) { - if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0) - continue; - else - break; - } - - - /*Stop RX DMA path*/ - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2); - - for (Count = 0; Count < 100; Count++) { - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - if (u1btmp & BIT1) - break; - else - ODM_delay_ms(10); - } - - /*Disable clock*/ - ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0); - /*Disable 320M*/ - ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); - /*Enable 320M*/ - ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); - /*Enable clock*/ - ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc); - - - /*Release Tx pause*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0); - - /*Enable RX DMA path*/ - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2)); -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - /*Enable PCIe TxDMA*/ - ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0); -#endif - /*Start Usb TxDMA*/ - RT_ENABLE_FUNC(Adapter, DF_TX_BIT); -} - -#endif - - - -#endif - +//============================================================ +// Description: +// +// This file is for 8812/8821/8811 TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +VOID +HalTxbf8812A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW)); + +} + +VOID +halTxbfJaguar_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + // Paath_A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + // Path_B + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + } else { + // Paath_A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + // Path_B + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); + else + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); +} + + +VOID +halTxbfJaguar_DownloadNDPA( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + BOOLEAN bSendBeacon = FALSE; + u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + PADAPTER Adapter = pDM_Odm->Adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (Idx == 0) + Head_Page = 0xFE; + else + Head_Page = 0xFE; + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + count = 0; + while (!(BcnValidReg & BIT0) && count < 20) { + count++; + ODM_delay_ms(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; +#endif +} + + +VOID +halTxbfJaguar_FwTxBFCmd( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx, Period0 = 0, Period1 = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + /*Modified by David*/ + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (Idx == 0) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; /*stop sounding*/ + Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (Idx == 1) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; /*stop sounding*/ + Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = (Period1 << 4) | Period0; + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); +} + + +VOID +HalTxbfJaguar_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); + + halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); + + if (pDM_Odm->RFType == ODM_2T2R) + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/ + else + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/ + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID. */ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */ + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID.*/ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/ + } + + /*CSI report parameters of Beamformee*/ + if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x01090109; + else + CSI_Param = 0x01080108; + } else { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x03090309; + else + CSI_Param = 0x03080308; + } + + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + } + + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9); + } else { + /*Set BIT25*/ + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200); + } + phydm_Beamforming_Notify(pDM_Odm); + } +} + + +VOID +HalTxbfJaguar_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMER_ENTRY BeamformerEntry; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx)); + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + if (Idx == 0) { + ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } + } + + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + } + } + +} + + +VOID +HalTxbfJaguar_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8812A; + else { + BeamCtrlReg = REG_TXBF_CTRL_8812A + 2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9 | BIT10); + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + } else + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal)); + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); +} + + + +VOID +HalTxbfJaguar_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx); + + halTxbfJaguar_FwTxBFCmd(pDM_Odm); +} + + +VOID +HalTxbfJaguar_Patch( + IN PVOID pDM_VOID, + IN u1Byte Operation +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (Operation == SCAN_OPT_BACKUP_BAND0) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + else if (Operation == SCAN_OPT_RESTORE) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); +#endif +} + +VOID +HalTxbfJaguar_Clk_8812A( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte u2btmp; + u1Byte Count = 0, u1btmp; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (*(pDM_Odm->pbScanInProcess)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); + return; + } +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*Stop PCIe TxDMA*/ + ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); +#endif + + /*Stop Usb TxDMA*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISABLE_FUNC(Adapter, DF_TX_BIT); + PlatformReturnAllPendingTxPackets(Adapter); +#else + rtw_write_port_cancel(Adapter); +#endif + + /*Wait TXFF empty*/ + for (Count = 0; Count < 100; Count++) { + u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A); + u2btmp = u2btmp & 0xfff; + if (u2btmp != 0xfff) { + ODM_delay_ms(10); + continue; + } else + break; + } + + /*TX pause*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); + + /*Wait TX State Machine OK*/ + for (Count = 0; Count < 100; Count++) { + if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0) + continue; + else + break; + } + + + /*Stop RX DMA path*/ + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2); + + for (Count = 0; Count < 100; Count++) { + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + if (u1btmp & BIT1) + break; + else + ODM_delay_ms(10); + } + + /*Disable clock*/ + ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0); + /*Disable 320M*/ + ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + /*Enable 320M*/ + ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + /*Enable clock*/ + ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc); + + + /*Release Tx pause*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0); + + /*Enable RX DMA path*/ + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2)); +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*Enable PCIe TxDMA*/ + ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0); +#endif + /*Start Usb TxDMA*/ + RT_ENABLE_FUNC(Adapter, DF_TX_BIT); +} + +#endif + + + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.h b/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.h index 49a5fdff1e6..ba16b7f04dd 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.h +++ b/package/kernel/rtl8192cd/phydm/txbf/haltxbfjaguar.h @@ -1,67 +1,67 @@ -#ifndef __HAL_TXBF_JAGUAR_H__ -#define __HAL_TXBF_JAGUAR_H__ - -#if (BEAMFORMING_SUPPORT == 1) -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) -VOID -HalTxbf8812A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -); - - -VOID -HalTxbfJaguar_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbfJaguar_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbfJaguar_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbfJaguar_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); - - -VOID -HalTxbfJaguar_Patch( - IN PVOID pDM_VOID, - IN u1Byte Operation - ); - - -VOID -HalTxbfJaguar_Clk_8812A( - IN PVOID pDM_VOID - ); - -#else - -#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate) -#define HalTxbfJaguar_Enter(pDM_VOID, Idx) -#define HalTxbfJaguar_Leave(pDM_VOID, Idx) -#define HalTxbfJaguar_Status(pDM_VOID, Idx) -#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx) -#define HalTxbfJaguar_Patch(pDM_VOID, Operation) -#define HalTxbfJaguar_Clk_8812A(pDM_VOID) -#endif - -#endif -#endif // #ifndef __HAL_TXBF_JAGUAR_H__ - +#ifndef __HAL_TXBF_JAGUAR_H__ +#define __HAL_TXBF_JAGUAR_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +VOID +HalTxbf8812A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + + +VOID +HalTxbfJaguar_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Patch( + IN PVOID pDM_VOID, + IN u1Byte Operation + ); + + +VOID +HalTxbfJaguar_Clk_8812A( + IN PVOID pDM_VOID + ); + +#else + +#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate) +#define HalTxbfJaguar_Enter(pDM_VOID, Idx) +#define HalTxbfJaguar_Leave(pDM_VOID, Idx) +#define HalTxbfJaguar_Status(pDM_VOID, Idx) +#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx) +#define HalTxbfJaguar_Patch(pDM_VOID, Operation) +#define HalTxbfJaguar_Clk_8812A(pDM_VOID) +#endif + +#endif +#endif // #ifndef __HAL_TXBF_JAGUAR_H__ + diff --git a/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.c b/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.c index 7c745e6a8d3..7c00f0f44df 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.c +++ b/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.c @@ -1,100 +1,100 @@ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (BEAMFORMING_SUPPORT == 1) - -/*Add by YuChen for 8822B MU-MIMO API*/ - -/*this function is only used for BFer*/ -u1Byte -phydm_get_ndpa_rate( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte NDPARate = ODM_RATE6M; - - if (pDM_Odm->RSSI_Min >= 30) /*link RSSI > 30%*/ - NDPARate = ODM_RATE24M; - else if (pDM_Odm->RSSI_Min <= 25) - NDPARate = ODM_RATE6M; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] NDPARate = 0x%x\n", __func__, NDPARate)); - - return NDPARate; - -} - -/*this function is only used for BFer*/ -u1Byte -phydm_get_beamforming_sounding_info( - IN PVOID pDM_VOID, - IN pu2Byte Troughput, - IN u1Byte Total_BFee_Num, - IN pu1Byte TxRate - ) -{ - u1Byte idx = 0; - u1Byte soundingdecision = 0xff; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - for (idx = 0; idx < Total_BFee_Num; idx++) { - if (((TxRate[idx] >= ODM_RATEVHTSS3MCS7) && (TxRate[idx] <= ODM_RATEVHTSS3MCS9))) - soundingdecision = soundingdecision & ~(1<= 500) - snding_score = 100; - else if (Throughput >= 450) - snding_score = 90; - else if (Throughput >= 400) - snding_score = 80; - else if (Throughput >= 350) - snding_score = 70; - else if (Throughput >= 300) - snding_score = 60; - else if (Throughput >= 250) - snding_score = 50; - else if (Throughput >= 200) - snding_score = 40; - else if (Throughput >= 150) - snding_score = 30; - else if (Throughput >= 100) - snding_score = 20; - else if (Throughput >= 50) - snding_score = 10; - else if (Throughput >= 1) - snding_score = 5; - else - snding_score = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%d\n", __func__, snding_score)); - - return snding_score; - -} - -#endif - +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) + +/*Add by YuChen for 8822B MU-MIMO API*/ + +/*this function is only used for BFer*/ +u1Byte +phydm_get_ndpa_rate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte NDPARate = ODM_RATE6M; + + if (pDM_Odm->RSSI_Min >= 30) /*link RSSI > 30%*/ + NDPARate = ODM_RATE24M; + else if (pDM_Odm->RSSI_Min <= 25) + NDPARate = ODM_RATE6M; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] NDPARate = 0x%x\n", __func__, NDPARate)); + + return NDPARate; + +} + +/*this function is only used for BFer*/ +u1Byte +phydm_get_beamforming_sounding_info( + IN PVOID pDM_VOID, + IN pu2Byte Troughput, + IN u1Byte Total_BFee_Num, + IN pu1Byte TxRate + ) +{ + u1Byte idx = 0; + u1Byte soundingdecision = 0xff; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + for (idx = 0; idx < Total_BFee_Num; idx++) { + if (((TxRate[idx] >= ODM_RATEVHTSS3MCS7) && (TxRate[idx] <= ODM_RATEVHTSS3MCS9))) + soundingdecision = soundingdecision & ~(1<= 500) + snding_score = 100; + else if (Throughput >= 450) + snding_score = 90; + else if (Throughput >= 400) + snding_score = 80; + else if (Throughput >= 350) + snding_score = 70; + else if (Throughput >= 300) + snding_score = 60; + else if (Throughput >= 250) + snding_score = 50; + else if (Throughput >= 200) + snding_score = 40; + else if (Throughput >= 150) + snding_score = 30; + else if (Throughput >= 100) + snding_score = 20; + else if (Throughput >= 50) + snding_score = 10; + else if (Throughput >= 1) + snding_score = 5; + else + snding_score = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%d\n", __func__, snding_score)); + + return snding_score; + +} + +#endif + diff --git a/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.h b/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.h index 40650ac1a92..33f89276cce 100644 --- a/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.h +++ b/package/kernel/rtl8192cd/phydm/txbf/phydm_hal_txbf_api.h @@ -1,43 +1,43 @@ -/********************************************************************************/ -/**/ -/*Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.*/ -/**/ -/*This program is free software; you can redistribute it and/or modify it*/ -/*under the terms of version 2 of the GNU General Public License as*/ -/*published by the Free Software Foundation.*/ -/**/ -/*This program is distributed in the hope that it will be useful, but WITHOUT*/ -/*ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or*/ -/*FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for*/ -/*more details.*/ -/*You should have received a copy of the GNU General Public License along with*/ -/*this program; if not, write to the Free Software Foundation, Inc.,*/ -/*51 Franklin Street, Fifth Floor, Boston, MA 02110, USA*/ -/**/ -/**/ -/********************************************************************************/ -#ifndef __PHYDM_HAL_TXBF_API_H__ -#define __PHYDM_HAL_TXBF_API_H__ - -u1Byte -phydm_get_beamforming_sounding_info( - IN PVOID pDM_VOID, - IN pu2Byte Troughput, - IN u1Byte Total_BFee_Num, - IN pu1Byte TxRate - ); - - -u1Byte -phydm_get_mu_bfee_snding_decision( - IN PVOID pDM_VOID, - IN u2Byte Throughput - ); - - -u1Byte -phydm_get_ndpa_rate( - IN PVOID pDM_VOID - ); - -#endif +/********************************************************************************/ +/**/ +/*Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.*/ +/**/ +/*This program is free software; you can redistribute it and/or modify it*/ +/*under the terms of version 2 of the GNU General Public License as*/ +/*published by the Free Software Foundation.*/ +/**/ +/*This program is distributed in the hope that it will be useful, but WITHOUT*/ +/*ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or*/ +/*FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for*/ +/*more details.*/ +/*You should have received a copy of the GNU General Public License along with*/ +/*this program; if not, write to the Free Software Foundation, Inc.,*/ +/*51 Franklin Street, Fifth Floor, Boston, MA 02110, USA*/ +/**/ +/**/ +/********************************************************************************/ +#ifndef __PHYDM_HAL_TXBF_API_H__ +#define __PHYDM_HAL_TXBF_API_H__ + +u1Byte +phydm_get_beamforming_sounding_info( + IN PVOID pDM_VOID, + IN pu2Byte Troughput, + IN u1Byte Total_BFee_Num, + IN pu1Byte TxRate + ); + + +u1Byte +phydm_get_mu_bfee_snding_decision( + IN PVOID pDM_VOID, + IN u2Byte Throughput + ); + + +u1Byte +phydm_get_ndpa_rate( + IN PVOID pDM_VOID + ); + +#endif diff --git a/package/kernel/rtl8192cd/romeperf.c b/package/kernel/rtl8192cd/romeperf.c index b0aafac53f3..2555f10fdea 100644 --- a/package/kernel/rtl8192cd/romeperf.c +++ b/package/kernel/rtl8192cd/romeperf.c @@ -1,917 +1,917 @@ -/* - * Performance Profiling routines - * - * $Id: romeperf.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "8192cd_cfg.h" - -#ifdef PERF_DUMP - -#include "romeperf.h" -//#include -#define KERNEL_SYSeALLS -#include -#include -#include -#include -#ifdef CONFIG_WIRELESS_LAN_MODULE -#define __IRAM -#else -#define __IRAM __attribute__ ((section(".iram-gen"))) -#endif -#define __OPT_0 __attribute__((optimize("O0"))) - -#define rtlglue_malloc(size) kmalloc(size, 0x1f0) -#define rtlglue_free(p) kfree(p) -#define rtlglue_printf panic_printk - - -enum CP3_COUNTER -{ - CP3CNT_CYCLES = 0, - CP3CNT_NEW_INST_FECTH, - CP3CNT_NEW_INST_FETCH_CACHE_MISS, - CP3CNT_NEW_INST_MISS_BUSY_CYCLE, - CP3CNT_DATA_STORE_INST, - CP3CNT_DATA_LOAD_INST, - CP3CNT_DATA_LOAD_OR_STORE_INST, - CP3CNT_EXACT_RETIRED_INST, - CP3CNT_RETIRED_INST_FOR_PIPE_A, - CP3CNT_RETIRED_INST_FOR_PIPE_B, - CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS, - CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE, - CP3CNT_RESERVED12, - CP3CNT_RESERVED13, - CP3CNT_RESERVED14, - CP3CNT_RESERVED15, -}; - -/* Local variables */ -//static -uint64 tempVariable64; -static uint32 tempVariable32; -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN -static uint32 tempVariable32_2; -unsigned char bCounterUsed[8]; -unsigned char numOfUsedCounter = 0; -#endif -static uint64 currCnt[4]; -unsigned int countTemp = 0xff; - - -/* Global variables */ -#ifdef CONFIG_WIRELESS_LAN_MODULE -static uint64 cnt1, cnt2; -static rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; -static uint32 rtl8651_romeperf_inited = 0; -static uint32 rtl8651_romeperf_enable = TRUE; -#else -uint64 cnt1, cnt2; -rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; -uint32 rtl8651_romeperf_inited = 0; -uint32 rtl8651_romeperf_enable = TRUE; -#endif - -unsigned char *mapping[]= -{ -#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) - "CP3CNT_CYCLES", - "CP3CNT_NEW_INST_FECTH", - "CP3CNT_NEW_INST_FETCH_CACHE_MISS", - "CP3CNT_NEW_INST_MISS_BUSY_CYCLE", - "CP3CNT_DATA_STORE_INST", - "CP3CNT_DATA_LOAD_INST", - "CP3CNT_DATA_LOAD_OR_STORE_INST", - "CP3CNT_EXACT_RETIRED_INST", - "CP3CNT_RETIRED_INST_FOR_PIPE_A", - "CP3CNT_RETIRED_INST_FOR_PIPE_B", - "CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS", - "CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE", - "CP3CNT_RESERVED12", - "CP3CNT_RESERVED13", - "CP3CNT_RESERVED14", - "CP3CNT_RESERVED15", -}; -#else - "CP3CNT_STOP_COUNT", - "CP3CNT_INST_FECTH", - "CP3CNT_ICACHE_MISS", - "CP3CNT_ICACHE_MISS_CYCLE", - "CP3CNT_STORE_INST", - "CP3CNT_LOAD_INST", - "CP3CNT_LOAD_OR_STORE_INST", - "CP3CNT_COMPLETE_INST", - "CP3CNT_CYCLES", - "CP3CNT_ICACHE_SOFT_MISS", - "CP3CNT_DCACHE_MISS", - "CP3CNT_DCACHE_MISS_CYCLES", - "CP3CNT_L2CACHE_HIT", - "CP3CNT_L2CACHE_HIT_CYCLES", - "CP3CNT_L2CACHE_MISS", - "CP3CNT_L2CACHE_MISS_CYCLES", - "CP3CNT_BRANCH_PREDICTION", - "CP3CNT_BRANCH_PREDICTION_MISS", - }; -#endif - - -__IRAM void CP3_COUNTER0_INIT( void ) -{ - __asm__ __volatile__ - ( - "mfc0 $8, $12 \n\t" - "la $9, 0x80000000 \n\t" - "or $8, $9 \n\t" - "mtc0 $8, $12 \n\t" - : - : - :"$8","$9" - ); -} - -__IRAM uint32 CP3_COUNTER0_IS_INITED( void ) -{ - __asm__ __volatile__ - ( - "mfc0 $8, $12 \n\t" - "la $9, tempVariable32 \n\t" - "sw $8, 0($9) \n\t" - : - : - :"$8","$9" - ); - return tempVariable32; -} - - -__IRAM void CP3_COUNTER0_START( void ) -{ - -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - __asm__ __volatile__ - ( - "la $8, tempVariable32 \n\t" - "lw $8, 0($8) \n\t" - "ctc3 $8, $0 \n\t" - "la $8, tempVariable32_2 \n\t" - "lw $8, 0($8) \n\t" - "ctc3 $8, $1 \n\t" - "li $8, 0xf \n\t" - "ctc3 $8, $2 \n\t" - : - : - :"$8" - ); -#else - __asm__ __volatile__ - ( - "la $8, tempVariable32 \n\t" - "lw $8, 0($8) \n\t" - "ctc3 $8, $0 \n\t" - : - : - :"$8" - ); -#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN -} - - -__IRAM void CP3_COUNTER0_ASSIGN_EVENT( void ) -{ -#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) -#if 1 /* Inst */ - tempVariable32 = /* Counter0 */((0x10|CP3CNT_CYCLES)<< 0) | - /* Counter1 */((0x10|CP3CNT_NEW_INST_FECTH)<< 8) | - /* Counter2 */((0x10|CP3CNT_NEW_INST_FETCH_CACHE_MISS)<<16) | - /* Counter3 */((0x10|CP3CNT_NEW_INST_MISS_BUSY_CYCLE)<<24); -#elif 1 /* Data (LOAD+STORE) */ - tempVariable32 = /* Counter0 */((0x10|CP3CNT_CYCLES)<< 0) | - /* Counter1 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_INST)<< 8) | - /* Counter2 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS)<<16) | - /* Counter3 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE)<<24); -#elif 1 /* Data (STORE) */ - tempVariable32 = /* Counter0 */((0x10|CP3CNT_DATA_LOAD_INST)<< 0) | - /* Counter1 */((0x10|CP3CNT_DATA_STORE_INST)<< 8) | - /* Counter2 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS)<<16) | - /* Counter3 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE)<<24); -#else -#error -#endif - -#elif (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_NEW) - -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - #if 1 /* Inst */ - tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | - /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | - /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | - /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); - tempVariable32_2 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | - /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | - /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | - /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); - #elif 1 /* Data (LOAD+STORE) */ - tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | - /* Counter1 */((CP3CNT_LOAD_OR_STORE_INST)<< 8) | - /* Counter2 */((CP3CNT_STORE_INST)<<16) | - /* Counter3 */((CP3CNT_LOAD_INST)<<24); - #else - #error - #endif -#else - #if 1 /* Inst */ - tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | - /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | - /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | - /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); - #elif 1 /* Data (LOAD+STORE) */ - tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | - /* Counter1 */((CP3CNT_LOAD_OR_STORE_INST)<< 8) | - /* Counter2 */((CP3CNT_STORE_INST)<<16) | - /* Counter3 */((CP3CNT_LOAD_INST)<<24); - #else - #error - #endif -#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN - -#else -#error "PERF_DUMP_CP3_SELECT flag error" -#endif - -} - - -__IRAM void CP3_COUNTER0_RESET_ONE(int cnt_num) -{ - switch(cnt_num) - { - case 0: - __asm__ __volatile__ - ( - "mtc3 $0, $8 \n\t" - ); - - break; - case 1: - __asm__ __volatile__ - ( - "mtc3 $0, $10 \n\t" - ); - - break; - case 2: - __asm__ __volatile__ - ( - "mtc3 $0, $12 \n\t" - ); - - break; - case 3: - __asm__ __volatile__ - ( - "mtc3 $0, $14 \n\t" - ); - - break; - case 4: - __asm__ __volatile__ - ( - "mtc3 $0, $9 \n\t" - ); - - break; - case 5: - __asm__ __volatile__ - ( - "mtc3 $0, $11 \n\t" - ); - - break; - case 6: - __asm__ __volatile__ - ( - "mtc3 $0, $13 \n\t" - ); - - break; - case 7: - __asm__ __volatile__ - ( - "mtc3 $0, $15 \n\t" - ); - - break; - default: - printk("CP3 RESET ERROR COUNTER = %x \n",cnt_num); - break; - } -} - -__IRAM void CP3_COUNTER0_RESET( void ) -{ - __asm__ __volatile__ - ( - "mtc3 $0, $8 \n\t" - "mtc3 $0, $9 \n\t" - "mtc3 $0, $10 \n\t" - "mtc3 $0, $11 \n\t" - "mtc3 $0, $12 \n\t" - "mtc3 $0, $13 \n\t" - "mtc3 $0, $14 \n\t" - "mtc3 $0, $15 \n\t" - ); -} - -__IRAM void CP3_COUNTER0_STOP( void ) -{ -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - __asm__ __volatile__ - ( - "ctc3 $0, $0 \n\t" - "ctc3 $0, $1 \n\t" - ); -#else - __asm__ __volatile__ - ( - "ctc3 $0, $0 \n\t" - ); -#endif -} - -__IRAM uint64 CP3_COUNTER0_GET( void ) -{ - __asm__ __volatile__ - ( - "la $8, tempVariable64 \n\t" - "mfc3 $9, $9 \n\t" - "sw $9, 0($8) \n\t" - "mfc3 $9, $8 \n\t" - "sw $9, 4($8) \n\t" - : - : - :"$8","$9" - ); - return tempVariable64; -} - -__IRAM void CP3_COUNTER0_GET_ALL( void ) -{ -__asm__ __volatile__ ( - "mfc3 $9, $9 \n\t" - "sw $9, 0x00(%0) \n\t" - "mfc3 $9, $8 \n\t" - "sw $9, 0x04(%0) \n\t" - "mfc3 $9, $11 \n\t" - "sw $9, 0x08(%0) \n\t" - "mfc3 $9, $10 \n\t" - "sw $9, 0x0C(%0) \n\t" - "mfc3 $9, $13 \n\t" - "sw $9, 0x10(%0) \n\t" - "mfc3 $9, $12 \n\t" - "sw $9, 0x14(%0) \n\t" - "mfc3 $9, $15 \n\t" - "sw $9, 0x18(%0) \n\t" - "mfc3 $9, $14 \n\t" - "sw $9, 0x1C(%0) \n\t" - : - :"r"(currCnt) - ); -} - -int32 rtl8651_romeperfInit() -{ - CP3_COUNTER0_INIT(); - CP3_COUNTER0_ASSIGN_EVENT(); - - rtl8651_romeperf_inited = TRUE; - rtl8651_romeperf_enable = TRUE; - memset( &romePerfStat, 0, sizeof( romePerfStat ) ); - -#if (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_ORI) - romePerfStat[ROMEPERF_INDEX_NAPT_ADD].desc = "NAPT add_all"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_1].desc = "NAPT add_checkIntIP"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_2].desc = "NAPT add_localServer"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_3].desc = "NAPT add_checkExtIp"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_4].desc = "NAPT add_dupCheck1"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_5].desc = "NAPT add_dupCheck2"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_6].desc = "NAPT add_bPortReused"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_7].desc = "NAPT add_routeCache"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_8].desc = "NAPT add_tooManyConn"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_9].desc = "NAPT add_initConn"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_10].desc = "NAPT add_decisionFlo"; - romePerfStat[ROMEPERF_INDEX_NAPT_ADD_11].desc = "NAPT add_ambiguous"; - romePerfStat[ROMEPERF_INDEX_NAPT_DEL].desc = "NAPT del"; - romePerfStat[ROMEPERF_INDEX_NAPT_FIND_OUTBOUND].desc = "NATP outbound"; - romePerfStat[ROMEPERF_INDEX_NAPT_FIND_INBOUND].desc = "NAPT inbound"; - romePerfStat[ROMEPERF_INDEX_NAPT_UPDATE].desc = "NAPT update"; - romePerfStat[ROMEPERF_INDEX_UNTIL_RXTHREAD].desc = "IntDispatch-RxThread"; - romePerfStat[ROMEPERF_INDEX_RECVLOOP].desc = "RecvLoop-FwdInput"; - romePerfStat[ROMEPERF_INDEX_FWDENG_INPUT].desc = "FwdEng_Input()"; - romePerfStat[ROMEPERF_INDEX_BEFORE_CRYPTO_ENCAP].desc = "FwdInput-Crypto(En)"; - romePerfStat[ROMEPERF_INDEX_ENCAP].desc = "IPSEC Encap"; - romePerfStat[ROMEPERF_INDEX_ENCAP_CRYPTO_ENGINE].desc = "Encap Crypto"; - romePerfStat[ROMEPERF_INDEX_ENCAP_AUTH_ENGINE].desc = "Encap Authtication"; - romePerfStat[ROMEPERF_INDEX_BEFORE_CRYPTO_DECAP].desc = "FwdInput-Crypto(De)"; - romePerfStat[ROMEPERF_INDEX_DECAP].desc = "IPSEC Decap"; - romePerfStat[ROMEPERF_INDEX_DECAP_CRYPTO_ENGINE].desc = "Decap Crypto"; - romePerfStat[ROMEPERF_INDEX_DECAP_AUTH_ENGINE].desc = "Decap Authtication"; - romePerfStat[ROMEPERF_INDEX_FASTPATH].desc = "Fast Path"; - romePerfStat[ROMEPERF_INDEX_SLOWPATH].desc = "Slow Path"; - romePerfStat[ROMEPERF_INDEX_FWDENG_SEND].desc = "FwdEngSend()"; - romePerfStat[ROMEPERF_INDEX_UNTIL_ACLDB].desc = "FwdInput() Until ACLDB"; - romePerfStat[ROMEPERF_INDEX_GET_MTU_AND_SOURCE_MAC].desc = "L3Route_MTU_srcMAC"; - romePerfStat[ROMEPERF_INDEX_PPTPL2TP_1].desc = "L3Route_PPTPL2TP_1"; - romePerfStat[ROMEPERF_INDEX_PPPOE_ARP_CACHE].desc = "L3Route_PPPoE_ArpCache"; - romePerfStat[ROMEPERF_INDEX_PPTPL2TP_SEND].desc = "L3Route_PptpL2tpSend()"; - romePerfStat[ROMEPERF_INDEX_FRAG].desc = "L3Route_Fragment"; - romePerfStat[ROMEPERF_INDEX_EGRESS_ACL].desc = "FwdSend_EgressACL"; - romePerfStat[ROMEPERF_INDEX_PPTPL2TP_ENCAP].desc = "FwdSend_PPTP/L2TP_Encap"; - romePerfStat[ROMEPERF_INDEX_FROM_PS].desc = "FwdSend_FromPS"; - romePerfStat[ROMEPERF_INDEX_EXTDEV_SEND].desc = "FwdSend_ExtDevSend()"; - romePerfStat[ROMEPERF_INDEX_FRAG_2ND_HALF].desc = "FwdSend_Frag_2ndHalf()"; - romePerfStat[ROMEPERF_INDEX_TXPKTPOST].desc = "rtl8651_txPktPostProcessing()"; - romePerfStat[ROMEPERF_INDEX_MBUFPAD].desc = "mBuf_padding()"; - romePerfStat[ROMEPERF_INDEX_TXALIGN].desc = "_swNic_txAlign"; - romePerfStat[ROMEPERF_INDEX_ISRTXRECYCLE].desc = "_swNic_isrTxRecycle"; - romePerfStat[ROMEPERF_INDEX_16].desc = "FwdEng_temp_16"; - romePerfStat[ROMEPERF_INDEX_17].desc = "FwdEng_temp_17"; - romePerfStat[ROMEPERF_INDEX_18].desc = "FwdEng_temp_18"; - romePerfStat[ROMEPERF_INDEX_19].desc = "FwdEng_temp_19"; - romePerfStat[ROMEPERF_INDEX_20].desc = "FwdEng_temp_20"; - romePerfStat[ROMEPERF_INDEX_21].desc = "FwdEng_temp_21"; - romePerfStat[ROMEPERF_INDEX_22].desc = "FwdEng_temp_22"; - romePerfStat[ROMEPERF_INDEX_23].desc = "FwdEng_temp_23"; - romePerfStat[ROMEPERF_INDEX_24].desc = "FwdEng_temp_24"; - romePerfStat[ROMEPERF_INDEX_25].desc = "FwdEng_temp_25"; - romePerfStat[ROMEPERF_INDEX_FLUSHDCACHE].desc = "rtlglue_flushDCache"; - romePerfStat[ROMEPERF_INDEX_IRAM_1].desc = "IRAM Cached within IRAM"; - romePerfStat[ROMEPERF_INDEX_IRAM_2].desc = "IRAM Uncached within IRAM"; - romePerfStat[ROMEPERF_INDEX_IRAM_3].desc = "test ICACHE (1024*100)"; - romePerfStat[ROMEPERF_INDEX_IRAM_4].desc = "test Uncached (1024*10)"; - romePerfStat[ROMEPERF_INDEX_DRAM_1].desc = "DRAM Cached within DRAM"; - romePerfStat[ROMEPERF_INDEX_DRAM_2].desc = "DRAM Uncached within DRAM"; - romePerfStat[ROMEPERF_INDEX_DRAM_3].desc = "test DCACHE (1024*100)"; - romePerfStat[ROMEPERF_INDEX_DRAM_4].desc = "test Uncached (1024*10)"; - romePerfStat[ROMEPERF_INDEX_BMP].desc = "KMP Algorithm"; - romePerfStat[ROMEPERF_INDEX_MDCMDIO].desc = "MDCMDIO PHY Register ACCESS"; -#elif (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_WLAN_TRX) - romePerfStat[ROMEPERF_INDEX_TX_PREWORK].desc = "XMIT_PREWORK"; - romePerfStat[ROMEPERF_INDEX_TX_XMIT_OUT].desc = "XMIT_OUT"; - romePerfStat[ROMEPERF_INDEX_TX_XMIT_OUT_2].desc = "XMIT_OUT_2"; - romePerfStat[ROMEPERF_INDEX_RX_ONE_PKT].desc = "RX_ONE_PKT"; - romePerfStat[ROMEPERF_INDEX_RX_ONE_PKT_2].desc = "RX_ONE_PKT_2"; - romePerfStat[ROMEPERF_INDEX_TX_START_XMIT].desc = "XMT_1"; - romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_2].desc = "XMIT_2"; - romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_3].desc = "XMIT_3"; - romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_4].desc = "XMIT_4"; - romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_5].desc = "XMIT_5"; -#else -#error "PERF_DUMP_INIT_SELECT flag error" -#endif - - return SUCCESS; -} - -int32 rtl8651_romeperfReset() -{ - rtl8651_romeperfInit(); - - return SUCCESS; -} - -#if 0/* old fashion function, for reference only. */ -int32 rtl8651_romeperfStart() -{ - if ( rtl8651_romeperf_inited == FALSE ) rtl8651_romeperfInit(); - - START_AND_GET_CP3_COUNTER0( cnt1 ); - - return SUCCESS; -} - -int32 rtl8651_romeperfStop( uint64 *pDiff ) -{ - if ( rtl8651_romeperf_inited == FALSE ) rtl8651_romeperfInit(); - - STOP_AND_GET_CP3_COUNTER0( cnt2 ); - - *pDiff = cnt2 - cnt1; - return SUCCESS; -} -#endif - -int32 rtl8651_romeperfGet( uint64 *pGet ) -{ - if ( rtl8651_romeperf_inited == FALSE ) return FAILED; - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - - CP3_COUNTER0_STOP(); - *pGet = CP3_COUNTER0_GET(); - CP3_COUNTER0_START(); - - return SUCCESS; -} - -int32 rtl8651_romeperfPause( void ) -{ - if ( rtl8651_romeperf_inited == FALSE ) return FAILED; - - rtl8651_romeperf_enable = FALSE; - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - - CP3_COUNTER0_STOP(); - - return SUCCESS; -} - -int32 rtl8651_romeperfResume( void ) -{ - if ( rtl8651_romeperf_inited == FALSE ) return FAILED; - - rtl8651_romeperf_enable = TRUE; - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - - CP3_COUNTER0_START(); - - return SUCCESS; -} - - -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - -__IRAM int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num,char *event) -{ - unsigned char i,j,counter; - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - CP3_COUNTER0_STOP(); - - if ( (rtl8651_romeperf_inited == FALSE) || (rtl8651_romeperf_enable == FALSE) ) { - //CP3_COUNTER0_START(); - return FAILED; - } - - if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) { - printk("CP3 index error! \n"); - CP3_COUNTER0_START(); - return FAILED; - } - - if(cnt_num + numOfUsedCounter > MAX_CP3_COUNTER) { - printk("Index=[%x]CP3 counter not enough, request:%x, availableCnt:%x \n",index,cnt_num,(MAX_CP3_COUNTER-numOfUsedCounter)); - CP3_COUNTER0_START(); - return FAILED; - } - - if(TRUE == romePerfStat[index].bUsed) { - printk("CP3 Error : reue the index=%x \n",index); - CP3_COUNTER0_START(); - return FAILED; - } - - // check reCall enter function, but not exit - if((countTemp!=0xff)&(countTemp != index)) - { - romePerfStat[index].reEnterIdx = countTemp; - } - - countTemp = index; - - romePerfStat[index].numOfCount = cnt_num; - - //printk("ENTER romePerfStat[%x].startCounter =%x \n",index,romePerfStat[index].startCounter); - - for(i=0; i= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) - { - printk("CP3 index error! \n"); - CP3_COUNTER0_START(); - return FAILED; - } - - if ( romePerfStat[index].hasTempCycle == FALSE ) - { - printk("CP3 EXIT error! romePerfStat[%x].hasTempCycle == FALSE \n",index); - CP3_COUNTER0_START(); - return FAILED; - } - - - if(countTemp == index) - { - countTemp = 0xff; - } - - CP3_COUNTER0_GET_ALL(); - - for(i=0; i< romePerfStat[index].numOfCount; i++) - { - counter = romePerfStat[index].Counter[i]; - //printk("LEAVE counter=[%x] cnt_index =%x romePerfStat[index].numOfCount =%x \n",counter,index,romePerfStat[index].numOfCount); - if (counter <4) { - romePerfStat[index].accCycle[i] += (currCnt[counter] & 0x00ffffff); - } else { // conter > 4 - romePerfStat[index].accCycle[i] += ((currCnt[counter-4]>>32) & 0x00ffffff); - } - - // counter available - bCounterUsed[counter] = FALSE; - numOfUsedCounter--; - } - - // printk("LEAVE numOfUsedCounter =%x \n",numOfUsedCounter); - - romePerfStat[index].bUsed = FALSE; - romePerfStat[index].hasTempCycle = FALSE; - romePerfStat[index].executedNum++; - - //CP3_COUNTER0_RESET_DUAL(cnt_num); - CP3_COUNTER0_START(); - - return SUCCESS; -} - -int getAvailableCnt(void) -{ - int i; - - for(i=0;i= CP3_CNT_MAX) - { - printk("Event over max = %x \n",event); - return FAILED; - } - - if(counter < 4) - { - tempVariable32 = (tempVariable32 & (~(0xff << (counter*8)))) | ( event << (counter*8)); - } - else - { - tempVariable32_2 = (tempVariable32_2 & (~(0xff << ((counter-4)*8)))) | ( event << ((counter-4)*8)); - } -} - -#else - - -__IRAM int32 rtl8651_romeperfEnterPoint( uint32 index ) -{ - if ( rtl8651_romeperf_inited == FALSE || - rtl8651_romeperf_enable == FALSE ) return FAILED; - if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) - return FAILED; - - if((countTemp!=0xff)&(countTemp != index)) - { - romePerfStat[index].reEnterIdx = countTemp; - } - - countTemp = index; - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - - CP3_COUNTER0_STOP(); - CP3_COUNTER0_RESET(); - CP3_COUNTER0_GET_ALL(); - - romePerfStat[index].tempCycle[0] = currCnt[0]; - romePerfStat[index].tempCycle[1] = currCnt[1]; - romePerfStat[index].tempCycle[2] = currCnt[2]; - romePerfStat[index].tempCycle[3] = currCnt[3]; - - romePerfStat[index].hasTempCycle = TRUE; - - CP3_COUNTER0_START(); - - return SUCCESS; -} - - -__IRAM int32 rtl8651_romeperfExitPoint( uint32 index ) -{ - if ( rtl8651_romeperf_inited == FALSE || - rtl8651_romeperf_enable == FALSE ) return FAILED; - if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) - return FAILED; - if ( romePerfStat[index].hasTempCycle == FALSE ) - return FAILED; - - if((countTemp == index)||(countTemp == 0)) - { - countTemp = 0; - } - - /* Louis patch: someone will disable CP3 in somewhere. */ - CP3_COUNTER0_INIT(); - - CP3_COUNTER0_STOP(); - CP3_COUNTER0_GET_ALL(); - - romePerfStat[index].accCycle[0] += (currCnt[0] - romePerfStat[index].tempCycle[0]); - romePerfStat[index].accCycle[1] += (currCnt[1] - romePerfStat[index].tempCycle[1]); - romePerfStat[index].accCycle[2] += (currCnt[2] - romePerfStat[index].tempCycle[2]); - romePerfStat[index].accCycle[3] += (currCnt[3] - romePerfStat[index].tempCycle[3]); - - - romePerfStat[index].hasTempCycle = FALSE; - romePerfStat[index].executedNum++; - - CP3_COUNTER0_RESET(); - - return SUCCESS; -} - -#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - -int32 rtl8651_romeperfDump( int start, int end ) -{ -#if 0 - int i; - - rtlglue_printf( "index %30s %12s %8s %10s\n", "description", "accCycle", "totalNum", "Average" ); - for( i = start; i <= end; i++ ) - { - if ( romePerfStat[i].executedNum == 0 ) - { - rtlglue_printf( "[%3d] %30s %12s %8s %10s\n", i, romePerfStat[i].desc, "--", "--", "--" ); - } - else - { - int j; - rtlglue_printf( "[%3d] %30s ", - i, romePerfStat[i].desc ); - for( j =0; j < sizeof(romePerfStat[i].accCycle)/sizeof(romePerfStat[i].accCycle[0]); - j++ ) - { - uint32 *pAccCycle = (uint32*)&romePerfStat[i].accCycle[j]; - uint32 avrgCycle = /* Hi-word */ (pAccCycle[0]*(0xffffffff/romePerfStat[i].executedNum)) + - /* Low-word */(pAccCycle[1]/romePerfStat[i].executedNum); - - rtlglue_printf( "%12llu %8u %10u\n", - romePerfStat[i].accCycle[j], - romePerfStat[i].executedNum, - avrgCycle - ); - rtlglue_printf( " %3s %30s ", "", "" ); - } - rtlglue_printf( "\r" ); - } - } - - return SUCCESS; -#else - int i,bReturn; - - rtl8651_romeperf_stat_t* statSnapShot = rtlglue_malloc(sizeof(rtl8651_romeperf_stat_t) * (end - start + 1) ); - if( statSnapShot == NULL ) - { - rtlglue_printf("statSnapShot mem alloc failed\n"); - return FAILED; - } - - rtlglue_printf( "index %30s %30s %12s %8s %10s %8s\n", "description","Event","accCycle", "totalNum", "Average","reENTERIdx" ); - - for( i = start; i <= end; i++ ) - { - int j; - for( j =0; j < sizeof(romePerfStat[i].accCycle)/sizeof(romePerfStat[i].accCycle[0]); j++ ) - { - statSnapShot[i].accCycle[j] = romePerfStat[i].accCycle[j]; - statSnapShot[i].tempCycle[j] = romePerfStat[i].tempCycle[j]; - } - statSnapShot[i].executedNum = romePerfStat[i].executedNum; - statSnapShot[i].hasTempCycle = romePerfStat[i].hasTempCycle; - } - - for( i = start; i < end; i++ ) - { - if ( statSnapShot[i].executedNum == 0 ) - { - rtlglue_printf( "[%3d] %30s %30s %12s %8s %10s %8s\n", i, romePerfStat[i].desc, "--", "--", "--", "--", "--","--" ); - } - else - { - int j; - rtlglue_printf( "[%3d] %30s ", i, romePerfStat[i].desc ); -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - for( j =0; j < romePerfStat[i].numOfCount; j++ ) -#else - for( j =0; j < sizeof(statSnapShot[i].accCycle)/sizeof(statSnapShot[i].accCycle[0]); j++ ) -#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - { - uint32 *pAccCycle = (uint32*)&statSnapShot[i].accCycle[j]; - uint32 avrgCycle = /* Hi-word */ (pAccCycle[0]*(0xffffffff/statSnapShot[i].executedNum)) + - /* Low-word */(pAccCycle[1]/statSnapShot[i].executedNum); - - rtlglue_printf( "%30s %12llu %8u %10u %8x\n", -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - mapping[romePerfStat[i].Event[j]], -#else - mapping[getEventIndex(j)], -#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - statSnapShot[i].accCycle[j], - statSnapShot[i].executedNum, - avrgCycle, - romePerfStat[i].reEnterIdx); - - rtlglue_printf( " %3s %30s ", "", "" ); - } - rtlglue_printf( "\r" ); - } - } - - rtlglue_free(statSnapShot); - - return SUCCESS; -#endif -} - -//////////////////////////////////////////////////////////////////////////////// - -int getEventIndex(int i) -{ - int index; -#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) - index = (tempVariable32 >> (i*8))&0xf; -#else -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - if(i < 4) - { - index = (tempVariable32 >> (i*8))&0xff; - } - else - { - index = (tempVariable32_2 >> ((i-4)*8))&0xff; - } -#else - index = (tempVariable32 >> (i*8))&0xff; -#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN -#endif //(PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) - return index; -} - - -#endif // PERF_DUMP - +/* + * Performance Profiling routines + * + * $Id: romeperf.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "8192cd_cfg.h" + +#ifdef PERF_DUMP + +#include "romeperf.h" +//#include +#define KERNEL_SYSeALLS +#include +#include +#include +#include +#ifdef CONFIG_WIRELESS_LAN_MODULE +#define __IRAM +#else +#define __IRAM __attribute__ ((section(".iram-gen"))) +#endif +#define __OPT_0 __attribute__((optimize("O0"))) + +#define rtlglue_malloc(size) kmalloc(size, 0x1f0) +#define rtlglue_free(p) kfree(p) +#define rtlglue_printf panic_printk + + +enum CP3_COUNTER +{ + CP3CNT_CYCLES = 0, + CP3CNT_NEW_INST_FECTH, + CP3CNT_NEW_INST_FETCH_CACHE_MISS, + CP3CNT_NEW_INST_MISS_BUSY_CYCLE, + CP3CNT_DATA_STORE_INST, + CP3CNT_DATA_LOAD_INST, + CP3CNT_DATA_LOAD_OR_STORE_INST, + CP3CNT_EXACT_RETIRED_INST, + CP3CNT_RETIRED_INST_FOR_PIPE_A, + CP3CNT_RETIRED_INST_FOR_PIPE_B, + CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS, + CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE, + CP3CNT_RESERVED12, + CP3CNT_RESERVED13, + CP3CNT_RESERVED14, + CP3CNT_RESERVED15, +}; + +/* Local variables */ +//static +uint64 tempVariable64; +static uint32 tempVariable32; +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN +static uint32 tempVariable32_2; +unsigned char bCounterUsed[8]; +unsigned char numOfUsedCounter = 0; +#endif +static uint64 currCnt[4]; +unsigned int countTemp = 0xff; + + +/* Global variables */ +#ifdef CONFIG_WIRELESS_LAN_MODULE +static uint64 cnt1, cnt2; +static rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; +static uint32 rtl8651_romeperf_inited = 0; +static uint32 rtl8651_romeperf_enable = TRUE; +#else +uint64 cnt1, cnt2; +rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; +uint32 rtl8651_romeperf_inited = 0; +uint32 rtl8651_romeperf_enable = TRUE; +#endif + +unsigned char *mapping[]= +{ +#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) + "CP3CNT_CYCLES", + "CP3CNT_NEW_INST_FECTH", + "CP3CNT_NEW_INST_FETCH_CACHE_MISS", + "CP3CNT_NEW_INST_MISS_BUSY_CYCLE", + "CP3CNT_DATA_STORE_INST", + "CP3CNT_DATA_LOAD_INST", + "CP3CNT_DATA_LOAD_OR_STORE_INST", + "CP3CNT_EXACT_RETIRED_INST", + "CP3CNT_RETIRED_INST_FOR_PIPE_A", + "CP3CNT_RETIRED_INST_FOR_PIPE_B", + "CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS", + "CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE", + "CP3CNT_RESERVED12", + "CP3CNT_RESERVED13", + "CP3CNT_RESERVED14", + "CP3CNT_RESERVED15", +}; +#else + "CP3CNT_STOP_COUNT", + "CP3CNT_INST_FECTH", + "CP3CNT_ICACHE_MISS", + "CP3CNT_ICACHE_MISS_CYCLE", + "CP3CNT_STORE_INST", + "CP3CNT_LOAD_INST", + "CP3CNT_LOAD_OR_STORE_INST", + "CP3CNT_COMPLETE_INST", + "CP3CNT_CYCLES", + "CP3CNT_ICACHE_SOFT_MISS", + "CP3CNT_DCACHE_MISS", + "CP3CNT_DCACHE_MISS_CYCLES", + "CP3CNT_L2CACHE_HIT", + "CP3CNT_L2CACHE_HIT_CYCLES", + "CP3CNT_L2CACHE_MISS", + "CP3CNT_L2CACHE_MISS_CYCLES", + "CP3CNT_BRANCH_PREDICTION", + "CP3CNT_BRANCH_PREDICTION_MISS", + }; +#endif + + +__IRAM void CP3_COUNTER0_INIT( void ) +{ + __asm__ __volatile__ + ( + "mfc0 $8, $12 \n\t" + "la $9, 0x80000000 \n\t" + "or $8, $9 \n\t" + "mtc0 $8, $12 \n\t" + : + : + :"$8","$9" + ); +} + +__IRAM uint32 CP3_COUNTER0_IS_INITED( void ) +{ + __asm__ __volatile__ + ( + "mfc0 $8, $12 \n\t" + "la $9, tempVariable32 \n\t" + "sw $8, 0($9) \n\t" + : + : + :"$8","$9" + ); + return tempVariable32; +} + + +__IRAM void CP3_COUNTER0_START( void ) +{ + +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + __asm__ __volatile__ + ( + "la $8, tempVariable32 \n\t" + "lw $8, 0($8) \n\t" + "ctc3 $8, $0 \n\t" + "la $8, tempVariable32_2 \n\t" + "lw $8, 0($8) \n\t" + "ctc3 $8, $1 \n\t" + "li $8, 0xf \n\t" + "ctc3 $8, $2 \n\t" + : + : + :"$8" + ); +#else + __asm__ __volatile__ + ( + "la $8, tempVariable32 \n\t" + "lw $8, 0($8) \n\t" + "ctc3 $8, $0 \n\t" + : + : + :"$8" + ); +#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN +} + + +__IRAM void CP3_COUNTER0_ASSIGN_EVENT( void ) +{ +#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) +#if 1 /* Inst */ + tempVariable32 = /* Counter0 */((0x10|CP3CNT_CYCLES)<< 0) | + /* Counter1 */((0x10|CP3CNT_NEW_INST_FECTH)<< 8) | + /* Counter2 */((0x10|CP3CNT_NEW_INST_FETCH_CACHE_MISS)<<16) | + /* Counter3 */((0x10|CP3CNT_NEW_INST_MISS_BUSY_CYCLE)<<24); +#elif 1 /* Data (LOAD+STORE) */ + tempVariable32 = /* Counter0 */((0x10|CP3CNT_CYCLES)<< 0) | + /* Counter1 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_INST)<< 8) | + /* Counter2 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS)<<16) | + /* Counter3 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE)<<24); +#elif 1 /* Data (STORE) */ + tempVariable32 = /* Counter0 */((0x10|CP3CNT_DATA_LOAD_INST)<< 0) | + /* Counter1 */((0x10|CP3CNT_DATA_STORE_INST)<< 8) | + /* Counter2 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS)<<16) | + /* Counter3 */((0x10|CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE)<<24); +#else +#error +#endif + +#elif (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_NEW) + +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + #if 1 /* Inst */ + tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | + /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | + /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | + /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); + tempVariable32_2 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | + /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | + /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | + /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); + #elif 1 /* Data (LOAD+STORE) */ + tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | + /* Counter1 */((CP3CNT_LOAD_OR_STORE_INST)<< 8) | + /* Counter2 */((CP3CNT_STORE_INST)<<16) | + /* Counter3 */((CP3CNT_LOAD_INST)<<24); + #else + #error + #endif +#else + #if 1 /* Inst */ + tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | + /* Counter1 */((CP3CNT_INST_FECTH)<< 8) | + /* Counter2 */((CP3CNT_ICACHE_MISS)<<16) | + /* Counter3 */((CP3CNT_ICACHE_MISS_CYCLE)<<24); + #elif 1 /* Data (LOAD+STORE) */ + tempVariable32 = /* Counter0 */((CP3CNT_CYCLES)<< 0) | + /* Counter1 */((CP3CNT_LOAD_OR_STORE_INST)<< 8) | + /* Counter2 */((CP3CNT_STORE_INST)<<16) | + /* Counter3 */((CP3CNT_LOAD_INST)<<24); + #else + #error + #endif +#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN + +#else +#error "PERF_DUMP_CP3_SELECT flag error" +#endif + +} + + +__IRAM void CP3_COUNTER0_RESET_ONE(int cnt_num) +{ + switch(cnt_num) + { + case 0: + __asm__ __volatile__ + ( + "mtc3 $0, $8 \n\t" + ); + + break; + case 1: + __asm__ __volatile__ + ( + "mtc3 $0, $10 \n\t" + ); + + break; + case 2: + __asm__ __volatile__ + ( + "mtc3 $0, $12 \n\t" + ); + + break; + case 3: + __asm__ __volatile__ + ( + "mtc3 $0, $14 \n\t" + ); + + break; + case 4: + __asm__ __volatile__ + ( + "mtc3 $0, $9 \n\t" + ); + + break; + case 5: + __asm__ __volatile__ + ( + "mtc3 $0, $11 \n\t" + ); + + break; + case 6: + __asm__ __volatile__ + ( + "mtc3 $0, $13 \n\t" + ); + + break; + case 7: + __asm__ __volatile__ + ( + "mtc3 $0, $15 \n\t" + ); + + break; + default: + printk("CP3 RESET ERROR COUNTER = %x \n",cnt_num); + break; + } +} + +__IRAM void CP3_COUNTER0_RESET( void ) +{ + __asm__ __volatile__ + ( + "mtc3 $0, $8 \n\t" + "mtc3 $0, $9 \n\t" + "mtc3 $0, $10 \n\t" + "mtc3 $0, $11 \n\t" + "mtc3 $0, $12 \n\t" + "mtc3 $0, $13 \n\t" + "mtc3 $0, $14 \n\t" + "mtc3 $0, $15 \n\t" + ); +} + +__IRAM void CP3_COUNTER0_STOP( void ) +{ +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + __asm__ __volatile__ + ( + "ctc3 $0, $0 \n\t" + "ctc3 $0, $1 \n\t" + ); +#else + __asm__ __volatile__ + ( + "ctc3 $0, $0 \n\t" + ); +#endif +} + +__IRAM uint64 CP3_COUNTER0_GET( void ) +{ + __asm__ __volatile__ + ( + "la $8, tempVariable64 \n\t" + "mfc3 $9, $9 \n\t" + "sw $9, 0($8) \n\t" + "mfc3 $9, $8 \n\t" + "sw $9, 4($8) \n\t" + : + : + :"$8","$9" + ); + return tempVariable64; +} + +__IRAM void CP3_COUNTER0_GET_ALL( void ) +{ +__asm__ __volatile__ ( + "mfc3 $9, $9 \n\t" + "sw $9, 0x00(%0) \n\t" + "mfc3 $9, $8 \n\t" + "sw $9, 0x04(%0) \n\t" + "mfc3 $9, $11 \n\t" + "sw $9, 0x08(%0) \n\t" + "mfc3 $9, $10 \n\t" + "sw $9, 0x0C(%0) \n\t" + "mfc3 $9, $13 \n\t" + "sw $9, 0x10(%0) \n\t" + "mfc3 $9, $12 \n\t" + "sw $9, 0x14(%0) \n\t" + "mfc3 $9, $15 \n\t" + "sw $9, 0x18(%0) \n\t" + "mfc3 $9, $14 \n\t" + "sw $9, 0x1C(%0) \n\t" + : + :"r"(currCnt) + ); +} + +int32 rtl8651_romeperfInit() +{ + CP3_COUNTER0_INIT(); + CP3_COUNTER0_ASSIGN_EVENT(); + + rtl8651_romeperf_inited = TRUE; + rtl8651_romeperf_enable = TRUE; + memset( &romePerfStat, 0, sizeof( romePerfStat ) ); + +#if (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_ORI) + romePerfStat[ROMEPERF_INDEX_NAPT_ADD].desc = "NAPT add_all"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_1].desc = "NAPT add_checkIntIP"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_2].desc = "NAPT add_localServer"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_3].desc = "NAPT add_checkExtIp"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_4].desc = "NAPT add_dupCheck1"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_5].desc = "NAPT add_dupCheck2"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_6].desc = "NAPT add_bPortReused"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_7].desc = "NAPT add_routeCache"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_8].desc = "NAPT add_tooManyConn"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_9].desc = "NAPT add_initConn"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_10].desc = "NAPT add_decisionFlo"; + romePerfStat[ROMEPERF_INDEX_NAPT_ADD_11].desc = "NAPT add_ambiguous"; + romePerfStat[ROMEPERF_INDEX_NAPT_DEL].desc = "NAPT del"; + romePerfStat[ROMEPERF_INDEX_NAPT_FIND_OUTBOUND].desc = "NATP outbound"; + romePerfStat[ROMEPERF_INDEX_NAPT_FIND_INBOUND].desc = "NAPT inbound"; + romePerfStat[ROMEPERF_INDEX_NAPT_UPDATE].desc = "NAPT update"; + romePerfStat[ROMEPERF_INDEX_UNTIL_RXTHREAD].desc = "IntDispatch-RxThread"; + romePerfStat[ROMEPERF_INDEX_RECVLOOP].desc = "RecvLoop-FwdInput"; + romePerfStat[ROMEPERF_INDEX_FWDENG_INPUT].desc = "FwdEng_Input()"; + romePerfStat[ROMEPERF_INDEX_BEFORE_CRYPTO_ENCAP].desc = "FwdInput-Crypto(En)"; + romePerfStat[ROMEPERF_INDEX_ENCAP].desc = "IPSEC Encap"; + romePerfStat[ROMEPERF_INDEX_ENCAP_CRYPTO_ENGINE].desc = "Encap Crypto"; + romePerfStat[ROMEPERF_INDEX_ENCAP_AUTH_ENGINE].desc = "Encap Authtication"; + romePerfStat[ROMEPERF_INDEX_BEFORE_CRYPTO_DECAP].desc = "FwdInput-Crypto(De)"; + romePerfStat[ROMEPERF_INDEX_DECAP].desc = "IPSEC Decap"; + romePerfStat[ROMEPERF_INDEX_DECAP_CRYPTO_ENGINE].desc = "Decap Crypto"; + romePerfStat[ROMEPERF_INDEX_DECAP_AUTH_ENGINE].desc = "Decap Authtication"; + romePerfStat[ROMEPERF_INDEX_FASTPATH].desc = "Fast Path"; + romePerfStat[ROMEPERF_INDEX_SLOWPATH].desc = "Slow Path"; + romePerfStat[ROMEPERF_INDEX_FWDENG_SEND].desc = "FwdEngSend()"; + romePerfStat[ROMEPERF_INDEX_UNTIL_ACLDB].desc = "FwdInput() Until ACLDB"; + romePerfStat[ROMEPERF_INDEX_GET_MTU_AND_SOURCE_MAC].desc = "L3Route_MTU_srcMAC"; + romePerfStat[ROMEPERF_INDEX_PPTPL2TP_1].desc = "L3Route_PPTPL2TP_1"; + romePerfStat[ROMEPERF_INDEX_PPPOE_ARP_CACHE].desc = "L3Route_PPPoE_ArpCache"; + romePerfStat[ROMEPERF_INDEX_PPTPL2TP_SEND].desc = "L3Route_PptpL2tpSend()"; + romePerfStat[ROMEPERF_INDEX_FRAG].desc = "L3Route_Fragment"; + romePerfStat[ROMEPERF_INDEX_EGRESS_ACL].desc = "FwdSend_EgressACL"; + romePerfStat[ROMEPERF_INDEX_PPTPL2TP_ENCAP].desc = "FwdSend_PPTP/L2TP_Encap"; + romePerfStat[ROMEPERF_INDEX_FROM_PS].desc = "FwdSend_FromPS"; + romePerfStat[ROMEPERF_INDEX_EXTDEV_SEND].desc = "FwdSend_ExtDevSend()"; + romePerfStat[ROMEPERF_INDEX_FRAG_2ND_HALF].desc = "FwdSend_Frag_2ndHalf()"; + romePerfStat[ROMEPERF_INDEX_TXPKTPOST].desc = "rtl8651_txPktPostProcessing()"; + romePerfStat[ROMEPERF_INDEX_MBUFPAD].desc = "mBuf_padding()"; + romePerfStat[ROMEPERF_INDEX_TXALIGN].desc = "_swNic_txAlign"; + romePerfStat[ROMEPERF_INDEX_ISRTXRECYCLE].desc = "_swNic_isrTxRecycle"; + romePerfStat[ROMEPERF_INDEX_16].desc = "FwdEng_temp_16"; + romePerfStat[ROMEPERF_INDEX_17].desc = "FwdEng_temp_17"; + romePerfStat[ROMEPERF_INDEX_18].desc = "FwdEng_temp_18"; + romePerfStat[ROMEPERF_INDEX_19].desc = "FwdEng_temp_19"; + romePerfStat[ROMEPERF_INDEX_20].desc = "FwdEng_temp_20"; + romePerfStat[ROMEPERF_INDEX_21].desc = "FwdEng_temp_21"; + romePerfStat[ROMEPERF_INDEX_22].desc = "FwdEng_temp_22"; + romePerfStat[ROMEPERF_INDEX_23].desc = "FwdEng_temp_23"; + romePerfStat[ROMEPERF_INDEX_24].desc = "FwdEng_temp_24"; + romePerfStat[ROMEPERF_INDEX_25].desc = "FwdEng_temp_25"; + romePerfStat[ROMEPERF_INDEX_FLUSHDCACHE].desc = "rtlglue_flushDCache"; + romePerfStat[ROMEPERF_INDEX_IRAM_1].desc = "IRAM Cached within IRAM"; + romePerfStat[ROMEPERF_INDEX_IRAM_2].desc = "IRAM Uncached within IRAM"; + romePerfStat[ROMEPERF_INDEX_IRAM_3].desc = "test ICACHE (1024*100)"; + romePerfStat[ROMEPERF_INDEX_IRAM_4].desc = "test Uncached (1024*10)"; + romePerfStat[ROMEPERF_INDEX_DRAM_1].desc = "DRAM Cached within DRAM"; + romePerfStat[ROMEPERF_INDEX_DRAM_2].desc = "DRAM Uncached within DRAM"; + romePerfStat[ROMEPERF_INDEX_DRAM_3].desc = "test DCACHE (1024*100)"; + romePerfStat[ROMEPERF_INDEX_DRAM_4].desc = "test Uncached (1024*10)"; + romePerfStat[ROMEPERF_INDEX_BMP].desc = "KMP Algorithm"; + romePerfStat[ROMEPERF_INDEX_MDCMDIO].desc = "MDCMDIO PHY Register ACCESS"; +#elif (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_WLAN_TRX) + romePerfStat[ROMEPERF_INDEX_TX_PREWORK].desc = "XMIT_PREWORK"; + romePerfStat[ROMEPERF_INDEX_TX_XMIT_OUT].desc = "XMIT_OUT"; + romePerfStat[ROMEPERF_INDEX_TX_XMIT_OUT_2].desc = "XMIT_OUT_2"; + romePerfStat[ROMEPERF_INDEX_RX_ONE_PKT].desc = "RX_ONE_PKT"; + romePerfStat[ROMEPERF_INDEX_RX_ONE_PKT_2].desc = "RX_ONE_PKT_2"; + romePerfStat[ROMEPERF_INDEX_TX_START_XMIT].desc = "XMT_1"; + romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_2].desc = "XMIT_2"; + romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_3].desc = "XMIT_3"; + romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_4].desc = "XMIT_4"; + romePerfStat[ROMEPERF_INDEX_TX_START_XMIT_5].desc = "XMIT_5"; +#else +#error "PERF_DUMP_INIT_SELECT flag error" +#endif + + return SUCCESS; +} + +int32 rtl8651_romeperfReset() +{ + rtl8651_romeperfInit(); + + return SUCCESS; +} + +#if 0/* old fashion function, for reference only. */ +int32 rtl8651_romeperfStart() +{ + if ( rtl8651_romeperf_inited == FALSE ) rtl8651_romeperfInit(); + + START_AND_GET_CP3_COUNTER0( cnt1 ); + + return SUCCESS; +} + +int32 rtl8651_romeperfStop( uint64 *pDiff ) +{ + if ( rtl8651_romeperf_inited == FALSE ) rtl8651_romeperfInit(); + + STOP_AND_GET_CP3_COUNTER0( cnt2 ); + + *pDiff = cnt2 - cnt1; + return SUCCESS; +} +#endif + +int32 rtl8651_romeperfGet( uint64 *pGet ) +{ + if ( rtl8651_romeperf_inited == FALSE ) return FAILED; + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + + CP3_COUNTER0_STOP(); + *pGet = CP3_COUNTER0_GET(); + CP3_COUNTER0_START(); + + return SUCCESS; +} + +int32 rtl8651_romeperfPause( void ) +{ + if ( rtl8651_romeperf_inited == FALSE ) return FAILED; + + rtl8651_romeperf_enable = FALSE; + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + + CP3_COUNTER0_STOP(); + + return SUCCESS; +} + +int32 rtl8651_romeperfResume( void ) +{ + if ( rtl8651_romeperf_inited == FALSE ) return FAILED; + + rtl8651_romeperf_enable = TRUE; + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + + CP3_COUNTER0_START(); + + return SUCCESS; +} + + +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + +__IRAM int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num,char *event) +{ + unsigned char i,j,counter; + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + CP3_COUNTER0_STOP(); + + if ( (rtl8651_romeperf_inited == FALSE) || (rtl8651_romeperf_enable == FALSE) ) { + //CP3_COUNTER0_START(); + return FAILED; + } + + if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) { + printk("CP3 index error! \n"); + CP3_COUNTER0_START(); + return FAILED; + } + + if(cnt_num + numOfUsedCounter > MAX_CP3_COUNTER) { + printk("Index=[%x]CP3 counter not enough, request:%x, availableCnt:%x \n",index,cnt_num,(MAX_CP3_COUNTER-numOfUsedCounter)); + CP3_COUNTER0_START(); + return FAILED; + } + + if(TRUE == romePerfStat[index].bUsed) { + printk("CP3 Error : reue the index=%x \n",index); + CP3_COUNTER0_START(); + return FAILED; + } + + // check reCall enter function, but not exit + if((countTemp!=0xff)&(countTemp != index)) + { + romePerfStat[index].reEnterIdx = countTemp; + } + + countTemp = index; + + romePerfStat[index].numOfCount = cnt_num; + + //printk("ENTER romePerfStat[%x].startCounter =%x \n",index,romePerfStat[index].startCounter); + + for(i=0; i= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) + { + printk("CP3 index error! \n"); + CP3_COUNTER0_START(); + return FAILED; + } + + if ( romePerfStat[index].hasTempCycle == FALSE ) + { + printk("CP3 EXIT error! romePerfStat[%x].hasTempCycle == FALSE \n",index); + CP3_COUNTER0_START(); + return FAILED; + } + + + if(countTemp == index) + { + countTemp = 0xff; + } + + CP3_COUNTER0_GET_ALL(); + + for(i=0; i< romePerfStat[index].numOfCount; i++) + { + counter = romePerfStat[index].Counter[i]; + //printk("LEAVE counter=[%x] cnt_index =%x romePerfStat[index].numOfCount =%x \n",counter,index,romePerfStat[index].numOfCount); + if (counter <4) { + romePerfStat[index].accCycle[i] += (currCnt[counter] & 0x00ffffff); + } else { // conter > 4 + romePerfStat[index].accCycle[i] += ((currCnt[counter-4]>>32) & 0x00ffffff); + } + + // counter available + bCounterUsed[counter] = FALSE; + numOfUsedCounter--; + } + + // printk("LEAVE numOfUsedCounter =%x \n",numOfUsedCounter); + + romePerfStat[index].bUsed = FALSE; + romePerfStat[index].hasTempCycle = FALSE; + romePerfStat[index].executedNum++; + + //CP3_COUNTER0_RESET_DUAL(cnt_num); + CP3_COUNTER0_START(); + + return SUCCESS; +} + +int getAvailableCnt(void) +{ + int i; + + for(i=0;i= CP3_CNT_MAX) + { + printk("Event over max = %x \n",event); + return FAILED; + } + + if(counter < 4) + { + tempVariable32 = (tempVariable32 & (~(0xff << (counter*8)))) | ( event << (counter*8)); + } + else + { + tempVariable32_2 = (tempVariable32_2 & (~(0xff << ((counter-4)*8)))) | ( event << ((counter-4)*8)); + } +} + +#else + + +__IRAM int32 rtl8651_romeperfEnterPoint( uint32 index ) +{ + if ( rtl8651_romeperf_inited == FALSE || + rtl8651_romeperf_enable == FALSE ) return FAILED; + if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) + return FAILED; + + if((countTemp!=0xff)&(countTemp != index)) + { + romePerfStat[index].reEnterIdx = countTemp; + } + + countTemp = index; + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + + CP3_COUNTER0_STOP(); + CP3_COUNTER0_RESET(); + CP3_COUNTER0_GET_ALL(); + + romePerfStat[index].tempCycle[0] = currCnt[0]; + romePerfStat[index].tempCycle[1] = currCnt[1]; + romePerfStat[index].tempCycle[2] = currCnt[2]; + romePerfStat[index].tempCycle[3] = currCnt[3]; + + romePerfStat[index].hasTempCycle = TRUE; + + CP3_COUNTER0_START(); + + return SUCCESS; +} + + +__IRAM int32 rtl8651_romeperfExitPoint( uint32 index ) +{ + if ( rtl8651_romeperf_inited == FALSE || + rtl8651_romeperf_enable == FALSE ) return FAILED; + if ( index >= (sizeof(romePerfStat)/sizeof(rtl8651_romeperf_stat_t)) ) + return FAILED; + if ( romePerfStat[index].hasTempCycle == FALSE ) + return FAILED; + + if((countTemp == index)||(countTemp == 0)) + { + countTemp = 0; + } + + /* Louis patch: someone will disable CP3 in somewhere. */ + CP3_COUNTER0_INIT(); + + CP3_COUNTER0_STOP(); + CP3_COUNTER0_GET_ALL(); + + romePerfStat[index].accCycle[0] += (currCnt[0] - romePerfStat[index].tempCycle[0]); + romePerfStat[index].accCycle[1] += (currCnt[1] - romePerfStat[index].tempCycle[1]); + romePerfStat[index].accCycle[2] += (currCnt[2] - romePerfStat[index].tempCycle[2]); + romePerfStat[index].accCycle[3] += (currCnt[3] - romePerfStat[index].tempCycle[3]); + + + romePerfStat[index].hasTempCycle = FALSE; + romePerfStat[index].executedNum++; + + CP3_COUNTER0_RESET(); + + return SUCCESS; +} + +#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + +int32 rtl8651_romeperfDump( int start, int end ) +{ +#if 0 + int i; + + rtlglue_printf( "index %30s %12s %8s %10s\n", "description", "accCycle", "totalNum", "Average" ); + for( i = start; i <= end; i++ ) + { + if ( romePerfStat[i].executedNum == 0 ) + { + rtlglue_printf( "[%3d] %30s %12s %8s %10s\n", i, romePerfStat[i].desc, "--", "--", "--" ); + } + else + { + int j; + rtlglue_printf( "[%3d] %30s ", + i, romePerfStat[i].desc ); + for( j =0; j < sizeof(romePerfStat[i].accCycle)/sizeof(romePerfStat[i].accCycle[0]); + j++ ) + { + uint32 *pAccCycle = (uint32*)&romePerfStat[i].accCycle[j]; + uint32 avrgCycle = /* Hi-word */ (pAccCycle[0]*(0xffffffff/romePerfStat[i].executedNum)) + + /* Low-word */(pAccCycle[1]/romePerfStat[i].executedNum); + + rtlglue_printf( "%12llu %8u %10u\n", + romePerfStat[i].accCycle[j], + romePerfStat[i].executedNum, + avrgCycle + ); + rtlglue_printf( " %3s %30s ", "", "" ); + } + rtlglue_printf( "\r" ); + } + } + + return SUCCESS; +#else + int i,bReturn; + + rtl8651_romeperf_stat_t* statSnapShot = rtlglue_malloc(sizeof(rtl8651_romeperf_stat_t) * (end - start + 1) ); + if( statSnapShot == NULL ) + { + rtlglue_printf("statSnapShot mem alloc failed\n"); + return FAILED; + } + + rtlglue_printf( "index %30s %30s %12s %8s %10s %8s\n", "description","Event","accCycle", "totalNum", "Average","reENTERIdx" ); + + for( i = start; i <= end; i++ ) + { + int j; + for( j =0; j < sizeof(romePerfStat[i].accCycle)/sizeof(romePerfStat[i].accCycle[0]); j++ ) + { + statSnapShot[i].accCycle[j] = romePerfStat[i].accCycle[j]; + statSnapShot[i].tempCycle[j] = romePerfStat[i].tempCycle[j]; + } + statSnapShot[i].executedNum = romePerfStat[i].executedNum; + statSnapShot[i].hasTempCycle = romePerfStat[i].hasTempCycle; + } + + for( i = start; i < end; i++ ) + { + if ( statSnapShot[i].executedNum == 0 ) + { + rtlglue_printf( "[%3d] %30s %30s %12s %8s %10s %8s\n", i, romePerfStat[i].desc, "--", "--", "--", "--", "--","--" ); + } + else + { + int j; + rtlglue_printf( "[%3d] %30s ", i, romePerfStat[i].desc ); +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + for( j =0; j < romePerfStat[i].numOfCount; j++ ) +#else + for( j =0; j < sizeof(statSnapShot[i].accCycle)/sizeof(statSnapShot[i].accCycle[0]); j++ ) +#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + { + uint32 *pAccCycle = (uint32*)&statSnapShot[i].accCycle[j]; + uint32 avrgCycle = /* Hi-word */ (pAccCycle[0]*(0xffffffff/statSnapShot[i].executedNum)) + + /* Low-word */(pAccCycle[1]/statSnapShot[i].executedNum); + + rtlglue_printf( "%30s %12llu %8u %10u %8x\n", +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + mapping[romePerfStat[i].Event[j]], +#else + mapping[getEventIndex(j)], +#endif //#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + statSnapShot[i].accCycle[j], + statSnapShot[i].executedNum, + avrgCycle, + romePerfStat[i].reEnterIdx); + + rtlglue_printf( " %3s %30s ", "", "" ); + } + rtlglue_printf( "\r" ); + } + } + + rtlglue_free(statSnapShot); + + return SUCCESS; +#endif +} + +//////////////////////////////////////////////////////////////////////////////// + +int getEventIndex(int i) +{ + int index; +#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) + index = (tempVariable32 >> (i*8))&0xf; +#else +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + if(i < 4) + { + index = (tempVariable32 >> (i*8))&0xff; + } + else + { + index = (tempVariable32_2 >> ((i-4)*8))&0xff; + } +#else + index = (tempVariable32 >> (i*8))&0xff; +#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN +#endif //(PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) + return index; +} + + +#endif // PERF_DUMP + diff --git a/package/kernel/rtl8192cd/romeperf.h b/package/kernel/rtl8192cd/romeperf.h index fad62135f33..5c07cb8bfde 100644 --- a/package/kernel/rtl8192cd/romeperf.h +++ b/package/kernel/rtl8192cd/romeperf.h @@ -1,258 +1,258 @@ -/* - * Performance Profiling Header File - * - * $Id: romeperf.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ - * - * Copyright (c) 2009 Realtek Semiconductor Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _ROMEPERF_H_ -#define _ROMEPERF_H_ - -#include -#include - -/* -typedef unsigned long long uint64; -typedef signed long long int64; -typedef unsigned int uint32; -typedef signed int int32; -typedef unsigned short uint16; -typedef signed short int16; -typedef unsigned char uint8; -typedef signed char int8; -*/ - -#ifndef NULL -#define NULL 0 -#endif -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef SUCCESS -#define SUCCESS 0 -#endif -#ifndef FAILED -#define FAILED -1 -#endif - - -#define MAX_CP3_COUNTER 8 - -#if defined(CONFIG_RTL865X_MODULE_ROMEDRV) -#define rtl8651_romeperfEnterPoint module_internal_rtl8651_romeperfEnterPoint -#define rtl8651_romeperfExitPoint module_internal_rtl8651_romeperfExitPoint -#endif - -struct rtl8651_romeperf_stat_s { - char *desc; -#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN - uint64 accCycle[8]; - uint64 tempCycle[8]; - unsigned char Counter[8]; - unsigned char Event[8]; - unsigned char numOfCount; - unsigned char bUsed; -#else - uint64 accCycle[4]; - uint64 tempCycle[4]; -#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN - uint32 reEnterIdx; - uint32 executedNum; - uint32 hasTempCycle:1; /* true if tempCycle is valid. */ -}; -typedef struct rtl8651_romeperf_stat_s rtl8651_romeperf_stat_t; - - -/* for rtl8651_romeperfEnterPoint() and rtl8651_romeperfExitPoint() */ -#if (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_ORI) -#define ROMEPERF_INDEX_MIN 0 -#define ROMEPERF_INDEX_NAPT_ADD 0 -#define ROMEPERF_INDEX_NAPT_ADD_1 1 -#define ROMEPERF_INDEX_NAPT_ADD_2 2 -#define ROMEPERF_INDEX_NAPT_ADD_3 3 -#define ROMEPERF_INDEX_NAPT_ADD_4 4 -#define ROMEPERF_INDEX_NAPT_ADD_5 5 -#define ROMEPERF_INDEX_NAPT_ADD_6 6 -#define ROMEPERF_INDEX_NAPT_ADD_7 7 -#define ROMEPERF_INDEX_NAPT_ADD_8 8 -#define ROMEPERF_INDEX_NAPT_ADD_9 9 -#define ROMEPERF_INDEX_NAPT_ADD_10 10 -#define ROMEPERF_INDEX_NAPT_ADD_11 11 -#define ROMEPERF_INDEX_NAPT_DEL 12 -#define ROMEPERF_INDEX_NAPT_FIND_OUTBOUND 13 -#define ROMEPERF_INDEX_NAPT_FIND_INBOUND 14 -#define ROMEPERF_INDEX_NAPT_UPDATE 15 -#define ROMEPERF_INDEX_UNTIL_RXTHREAD 20 -#define ROMEPERF_INDEX_RECVLOOP 21 -#define ROMEPERF_INDEX_FWDENG_INPUT 22 -#define ROMEPERF_INDEX_BEFORE_CRYPTO_ENCAP 23 -#define ROMEPERF_INDEX_ENCAP 24 -#define ROMEPERF_INDEX_ENCAP_CRYPTO_ENGINE 25 -#define ROMEPERF_INDEX_ENCAP_AUTH_ENGINE 26 -#define ROMEPERF_INDEX_BEFORE_CRYPTO_DECAP 27 -#define ROMEPERF_INDEX_DECAP 28 -#define ROMEPERF_INDEX_DECAP_CRYPTO_ENGINE 29 -#define ROMEPERF_INDEX_DECAP_AUTH_ENGINE 30 -#define ROMEPERF_INDEX_FASTPATH 31 -#define ROMEPERF_INDEX_SLOWPATH 32 -#define ROMEPERF_INDEX_UNTIL_ACLDB 33 -#define ROMEPERF_INDEX_GET_MTU_AND_SOURCE_MAC 34 -#define ROMEPERF_INDEX_PPTPL2TP_1 35 -#define ROMEPERF_INDEX_PPPOE_ARP_CACHE 36 -#define ROMEPERF_INDEX_PPTPL2TP_SEND 37 -#define ROMEPERF_INDEX_FRAG 38 -#define ROMEPERF_INDEX_FWDENG_SEND 39 -#define ROMEPERF_INDEX_EGRESS_ACL 40 -#define ROMEPERF_INDEX_PPTPL2TP_ENCAP 41 -#define ROMEPERF_INDEX_FROM_PS 42 -#define ROMEPERF_INDEX_EXTDEV_SEND 43 -#define ROMEPERF_INDEX_FRAG_2ND_HALF 44 -#define ROMEPERF_INDEX_TXPKTPOST 45 -#define ROMEPERF_INDEX_MBUFPAD 46 -#define ROMEPERF_INDEX_TXALIGN 47 -#define ROMEPERF_INDEX_ISRTXRECYCLE 48 -#define ROMEPERF_INDEX_16 49 -#define ROMEPERF_INDEX_17 50 -#define ROMEPERF_INDEX_18 51 -#define ROMEPERF_INDEX_19 52 -#define ROMEPERF_INDEX_20 53 -#define ROMEPERF_INDEX_21 54 -#define ROMEPERF_INDEX_22 55 -#define ROMEPERF_INDEX_23 56 -#define ROMEPERF_INDEX_24 57 -#define ROMEPERF_INDEX_25 58 -#define ROMEPERF_INDEX_FLUSHDCACHE 59 -#define ROMEPERF_INDEX_IRAM_1 60 -#define ROMEPERF_INDEX_IRAM_2 61 -#define ROMEPERF_INDEX_IRAM_3 62 -#define ROMEPERF_INDEX_IRAM_4 63 -#define ROMEPERF_INDEX_DRAM_1 64 -#define ROMEPERF_INDEX_DRAM_2 65 -#define ROMEPERF_INDEX_DRAM_3 66 -#define ROMEPERF_INDEX_DRAM_4 67 -#define ROMEPERF_INDEX_BMP 68 -#define ROMEPERF_INDEX_MDCMDIO 69 -#define ROMEPERF_INDEX_MAX 70 - -#elif (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_WLAN_TRX) -#define ROMEPERF_INDEX_MIN 0 -enum _ROMEPERF_INDEX_LIST_ { - //tx - ROMEPERF_INDEX_TX_PREWORK = 0, - ROMEPERF_INDEX_TX_XMIT_OUT, - ROMEPERF_INDEX_TX_XMIT_OUT_2, - - //Rx - ROMEPERF_INDEX_RX_ONE_PKT, - ROMEPERF_INDEX_RX_ONE_PKT_2, - ROMEPERF_INDEX_TX_START_XMIT, - ROMEPERF_INDEX_TX_START_XMIT_2, - ROMEPERF_INDEX_TX_START_XMIT_3, - ROMEPERF_INDEX_TX_START_XMIT_4, - ROMEPERF_INDEX_TX_START_XMIT_5, - ROMEPERF_INDEX_MAX -}; - - -#else -#error "PERF_DUMP_INIT_SELECT flag error" -#endif - - -#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) -enum CP3_COUNTER -{ - CP3CNT_CYCLES = 0, - CP3CNT_NEW_INST_FECTH, - CP3CNT_NEW_INST_FETCH_CACHE_MISS, - CP3CNT_NEW_INST_MISS_BUSY_CYCLE, - CP3CNT_DATA_STORE_INST, - CP3CNT_DATA_LOAD_INST, - CP3CNT_DATA_LOAD_OR_STORE_INST, - CP3CNT_EXACT_RETIRED_INST, - CP3CNT_RETIRED_INST_FOR_PIPE_A, - CP3CNT_RETIRED_INST_FOR_PIPE_B, - CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS, - CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE, - CP3CNT_RESERVED12, - CP3CNT_RESERVED13, - CP3CNT_RESERVED14, - CP3CNT_RESERVED15, -}; -#elif (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_NEW) -enum CP3_COUNTER -{ - //0x0 - CP3CNT_STOP_COUNT = 0, - CP3CNT_INST_FECTH, - CP3CNT_ICACHE_MISS, - CP3CNT_ICACHE_MISS_CYCLE, - CP3CNT_STORE_INST, - - //0x5 - CP3CNT_LOAD_INST, - CP3CNT_LOAD_OR_STORE_INST, - CP3CNT_COMPLETE_INST, - CP3CNT_CYCLES, - CP3CNT_ICACHE_SOFT_MISS, - - //0xA - CP3CNT_DCACHE_MISS, - CP3CNT_DCACHE_MISS_CYCLES, - CP3CNT_L2CACHE_HIT, - CP3CNT_L2CACHE_HIT_CYCLES, - CP3CNT_L2CACHE_MISS, - CP3CNT_L2CACHE_MISS_CYCLES, - - //0X10 - CP3CNT_BRANCH_PREDICTION, - CP3CNT_BRANCH_PREDICTION_MISS, - // TODO: Filen, enumalation below should be added - - //0x15 - //0x1A - //0x20 - //0x25 - //0x2A - //0x30 - - CP3_CNT_MAX = 0x34 -}; - -#else -#error "PERF_DUMP_CP3_SELECT flag error" -#endif - -int32 rtl8651_romeperfInit( void ); -inline int32 rtl8651_romeperfStart(void); -inline int32 rtl8651_romeperfStop(void); -int32 rtl8651_romeperfReset( void ); -int32 rtl8651_romeperfEnterPoint( uint32 index ); -int32 rtl8651_romeperfExitPoint( uint32 index ); -int32 rtl8651_romeperfDump( int start, int end ); -int32 rtl8651_romeperfPause( void ); -int32 rtl8651_romeperfResume( void ); -int32 rtl8651_romeperfGet( uint64 *pGet ); - -//int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num); -int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num,char *event); -int32 rtl_romeperfExitPoint_dual(uint32 index); -int getEventIndex(int i); -int getAvailableCnt(void); -int setEvent(int counter,char evnet); - - -extern rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; - - - -#endif/* _ROMEPERF_H_ */ +/* + * Performance Profiling Header File + * + * $Id: romeperf.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $ + * + * Copyright (c) 2009 Realtek Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ROMEPERF_H_ +#define _ROMEPERF_H_ + +#include +#include + +/* +typedef unsigned long long uint64; +typedef signed long long int64; +typedef unsigned int uint32; +typedef signed int int32; +typedef unsigned short uint16; +typedef signed short int16; +typedef unsigned char uint8; +typedef signed char int8; +*/ + +#ifndef NULL +#define NULL 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAILED +#define FAILED -1 +#endif + + +#define MAX_CP3_COUNTER 8 + +#if defined(CONFIG_RTL865X_MODULE_ROMEDRV) +#define rtl8651_romeperfEnterPoint module_internal_rtl8651_romeperfEnterPoint +#define rtl8651_romeperfExitPoint module_internal_rtl8651_romeperfExitPoint +#endif + +struct rtl8651_romeperf_stat_s { + char *desc; +#ifdef PERF_DUMP_CP3_DUAL_COUNTER_EN + uint64 accCycle[8]; + uint64 tempCycle[8]; + unsigned char Counter[8]; + unsigned char Event[8]; + unsigned char numOfCount; + unsigned char bUsed; +#else + uint64 accCycle[4]; + uint64 tempCycle[4]; +#endif // PERF_DUMP_CP3_DUAL_COUNTER_EN + uint32 reEnterIdx; + uint32 executedNum; + uint32 hasTempCycle:1; /* true if tempCycle is valid. */ +}; +typedef struct rtl8651_romeperf_stat_s rtl8651_romeperf_stat_t; + + +/* for rtl8651_romeperfEnterPoint() and rtl8651_romeperfExitPoint() */ +#if (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_ORI) +#define ROMEPERF_INDEX_MIN 0 +#define ROMEPERF_INDEX_NAPT_ADD 0 +#define ROMEPERF_INDEX_NAPT_ADD_1 1 +#define ROMEPERF_INDEX_NAPT_ADD_2 2 +#define ROMEPERF_INDEX_NAPT_ADD_3 3 +#define ROMEPERF_INDEX_NAPT_ADD_4 4 +#define ROMEPERF_INDEX_NAPT_ADD_5 5 +#define ROMEPERF_INDEX_NAPT_ADD_6 6 +#define ROMEPERF_INDEX_NAPT_ADD_7 7 +#define ROMEPERF_INDEX_NAPT_ADD_8 8 +#define ROMEPERF_INDEX_NAPT_ADD_9 9 +#define ROMEPERF_INDEX_NAPT_ADD_10 10 +#define ROMEPERF_INDEX_NAPT_ADD_11 11 +#define ROMEPERF_INDEX_NAPT_DEL 12 +#define ROMEPERF_INDEX_NAPT_FIND_OUTBOUND 13 +#define ROMEPERF_INDEX_NAPT_FIND_INBOUND 14 +#define ROMEPERF_INDEX_NAPT_UPDATE 15 +#define ROMEPERF_INDEX_UNTIL_RXTHREAD 20 +#define ROMEPERF_INDEX_RECVLOOP 21 +#define ROMEPERF_INDEX_FWDENG_INPUT 22 +#define ROMEPERF_INDEX_BEFORE_CRYPTO_ENCAP 23 +#define ROMEPERF_INDEX_ENCAP 24 +#define ROMEPERF_INDEX_ENCAP_CRYPTO_ENGINE 25 +#define ROMEPERF_INDEX_ENCAP_AUTH_ENGINE 26 +#define ROMEPERF_INDEX_BEFORE_CRYPTO_DECAP 27 +#define ROMEPERF_INDEX_DECAP 28 +#define ROMEPERF_INDEX_DECAP_CRYPTO_ENGINE 29 +#define ROMEPERF_INDEX_DECAP_AUTH_ENGINE 30 +#define ROMEPERF_INDEX_FASTPATH 31 +#define ROMEPERF_INDEX_SLOWPATH 32 +#define ROMEPERF_INDEX_UNTIL_ACLDB 33 +#define ROMEPERF_INDEX_GET_MTU_AND_SOURCE_MAC 34 +#define ROMEPERF_INDEX_PPTPL2TP_1 35 +#define ROMEPERF_INDEX_PPPOE_ARP_CACHE 36 +#define ROMEPERF_INDEX_PPTPL2TP_SEND 37 +#define ROMEPERF_INDEX_FRAG 38 +#define ROMEPERF_INDEX_FWDENG_SEND 39 +#define ROMEPERF_INDEX_EGRESS_ACL 40 +#define ROMEPERF_INDEX_PPTPL2TP_ENCAP 41 +#define ROMEPERF_INDEX_FROM_PS 42 +#define ROMEPERF_INDEX_EXTDEV_SEND 43 +#define ROMEPERF_INDEX_FRAG_2ND_HALF 44 +#define ROMEPERF_INDEX_TXPKTPOST 45 +#define ROMEPERF_INDEX_MBUFPAD 46 +#define ROMEPERF_INDEX_TXALIGN 47 +#define ROMEPERF_INDEX_ISRTXRECYCLE 48 +#define ROMEPERF_INDEX_16 49 +#define ROMEPERF_INDEX_17 50 +#define ROMEPERF_INDEX_18 51 +#define ROMEPERF_INDEX_19 52 +#define ROMEPERF_INDEX_20 53 +#define ROMEPERF_INDEX_21 54 +#define ROMEPERF_INDEX_22 55 +#define ROMEPERF_INDEX_23 56 +#define ROMEPERF_INDEX_24 57 +#define ROMEPERF_INDEX_25 58 +#define ROMEPERF_INDEX_FLUSHDCACHE 59 +#define ROMEPERF_INDEX_IRAM_1 60 +#define ROMEPERF_INDEX_IRAM_2 61 +#define ROMEPERF_INDEX_IRAM_3 62 +#define ROMEPERF_INDEX_IRAM_4 63 +#define ROMEPERF_INDEX_DRAM_1 64 +#define ROMEPERF_INDEX_DRAM_2 65 +#define ROMEPERF_INDEX_DRAM_3 66 +#define ROMEPERF_INDEX_DRAM_4 67 +#define ROMEPERF_INDEX_BMP 68 +#define ROMEPERF_INDEX_MDCMDIO 69 +#define ROMEPERF_INDEX_MAX 70 + +#elif (PERF_DUMP_INIT_SELECT == PERF_DUMP_INIT_WLAN_TRX) +#define ROMEPERF_INDEX_MIN 0 +enum _ROMEPERF_INDEX_LIST_ { + //tx + ROMEPERF_INDEX_TX_PREWORK = 0, + ROMEPERF_INDEX_TX_XMIT_OUT, + ROMEPERF_INDEX_TX_XMIT_OUT_2, + + //Rx + ROMEPERF_INDEX_RX_ONE_PKT, + ROMEPERF_INDEX_RX_ONE_PKT_2, + ROMEPERF_INDEX_TX_START_XMIT, + ROMEPERF_INDEX_TX_START_XMIT_2, + ROMEPERF_INDEX_TX_START_XMIT_3, + ROMEPERF_INDEX_TX_START_XMIT_4, + ROMEPERF_INDEX_TX_START_XMIT_5, + ROMEPERF_INDEX_MAX +}; + + +#else +#error "PERF_DUMP_INIT_SELECT flag error" +#endif + + +#if (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_OLD) +enum CP3_COUNTER +{ + CP3CNT_CYCLES = 0, + CP3CNT_NEW_INST_FECTH, + CP3CNT_NEW_INST_FETCH_CACHE_MISS, + CP3CNT_NEW_INST_MISS_BUSY_CYCLE, + CP3CNT_DATA_STORE_INST, + CP3CNT_DATA_LOAD_INST, + CP3CNT_DATA_LOAD_OR_STORE_INST, + CP3CNT_EXACT_RETIRED_INST, + CP3CNT_RETIRED_INST_FOR_PIPE_A, + CP3CNT_RETIRED_INST_FOR_PIPE_B, + CP3CNT_DATA_LOAD_OR_STORE_CACHE_MISS, + CP3CNT_DATA_LOAD_OR_STORE_MISS_BUSY_CYCLE, + CP3CNT_RESERVED12, + CP3CNT_RESERVED13, + CP3CNT_RESERVED14, + CP3CNT_RESERVED15, +}; +#elif (PERF_DUMP_CP3_SELECT == PERF_DUMP_CP3_NEW) +enum CP3_COUNTER +{ + //0x0 + CP3CNT_STOP_COUNT = 0, + CP3CNT_INST_FECTH, + CP3CNT_ICACHE_MISS, + CP3CNT_ICACHE_MISS_CYCLE, + CP3CNT_STORE_INST, + + //0x5 + CP3CNT_LOAD_INST, + CP3CNT_LOAD_OR_STORE_INST, + CP3CNT_COMPLETE_INST, + CP3CNT_CYCLES, + CP3CNT_ICACHE_SOFT_MISS, + + //0xA + CP3CNT_DCACHE_MISS, + CP3CNT_DCACHE_MISS_CYCLES, + CP3CNT_L2CACHE_HIT, + CP3CNT_L2CACHE_HIT_CYCLES, + CP3CNT_L2CACHE_MISS, + CP3CNT_L2CACHE_MISS_CYCLES, + + //0X10 + CP3CNT_BRANCH_PREDICTION, + CP3CNT_BRANCH_PREDICTION_MISS, + // TODO: Filen, enumalation below should be added + + //0x15 + //0x1A + //0x20 + //0x25 + //0x2A + //0x30 + + CP3_CNT_MAX = 0x34 +}; + +#else +#error "PERF_DUMP_CP3_SELECT flag error" +#endif + +int32 rtl8651_romeperfInit( void ); +inline int32 rtl8651_romeperfStart(void); +inline int32 rtl8651_romeperfStop(void); +int32 rtl8651_romeperfReset( void ); +int32 rtl8651_romeperfEnterPoint( uint32 index ); +int32 rtl8651_romeperfExitPoint( uint32 index ); +int32 rtl8651_romeperfDump( int start, int end ); +int32 rtl8651_romeperfPause( void ); +int32 rtl8651_romeperfResume( void ); +int32 rtl8651_romeperfGet( uint64 *pGet ); + +//int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num); +int32 rtl_romeperfEnterPoint_dual(uint32 index, int cnt_num,char *event); +int32 rtl_romeperfExitPoint_dual(uint32 index); +int getEventIndex(int i); +int getAvailableCnt(void); +int setEvent(int counter,char evnet); + + +extern rtl8651_romeperf_stat_t romePerfStat[ROMEPERF_INDEX_MAX]; + + + +#endif/* _ROMEPERF_H_ */ diff --git a/package/kernel/rtl8192cd/rtl8672_port.c b/package/kernel/rtl8192cd/rtl8672_port.c index ad91cc4be28..9dffaa5acc0 100644 --- a/package/kernel/rtl8192cd/rtl8672_port.c +++ b/package/kernel/rtl8192cd/rtl8672_port.c @@ -1,31 +1,31 @@ -#include -#include - -#if defined (CONFIG_PRINTK_FUNC) -int scrlog_printk(const char *fmt, ...) { - - va_list args; - int r; - va_start(args, fmt); -// r = vprintk(fmt, args); - r = scrlog_vprintk(fmt, args); - va_end(args); - return r; -} -#else -int scrlog_printk(const char *fmt, ...) -{ - return 0; -} -#endif - -#if defined(CONFIG_PANIC_PRINTK) -int panic_printk(const char *fmt, ...) { - va_list args; - int r; - va_start(args, fmt); - r = vprintk(fmt, args); - va_end(args); - return r; -} +#include +#include + +#if defined (CONFIG_PRINTK_FUNC) +int scrlog_printk(const char *fmt, ...) { + + va_list args; + int r; + va_start(args, fmt); +// r = vprintk(fmt, args); + r = scrlog_vprintk(fmt, args); + va_end(args); + return r; +} +#else +int scrlog_printk(const char *fmt, ...) +{ + return 0; +} +#endif + +#if defined(CONFIG_PANIC_PRINTK) +int panic_printk(const char *fmt, ...) { + va_list args; + int r; + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + return r; +} #endif \ No newline at end of file diff --git a/package/kernel/rtl8192cd/rtw_android.c b/package/kernel/rtl8192cd/rtw_android.c old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/rtw_android.h b/package/kernel/rtl8192cd/rtw_android.h old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/sha256.c b/package/kernel/rtl8192cd/sha256.c index a11259bc4d4..4dccaddb276 100644 --- a/package/kernel/rtl8192cd/sha256.c +++ b/package/kernel/rtl8192cd/sha256.c @@ -1,390 +1,390 @@ -/* - * SHA-256 hash implementation and interface functions - * Copyright (c) 2003-2007, Jouni Malinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Alternatively, this software may be distributed under the terms of BSD - * license. - * - * See README and COPYING for more details. - */ -#include "./8192cd_headers.h" -#include "sha256.h" - -#if defined(CONFIG_IEEE80211W) || defined(CONFIG_IEEE80211R) || defined(CONFIG_RTL_WAPI_SUPPORT) -#define SHA256_BLOCK_SIZE 64 - - -/** - * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) - * @key: Key for HMAC operations - * @key_len: Length of the key in bytes - * @num_elem: Number of elements in the data vector - * @addr: Pointers to the data areas - * @len: Lengths of the data blocks - * @mac: Buffer for the hash (32 bytes) - * Returns: 0 on success, -1 on failure - */ -int hmac_sha256_vector(const u1Byte *key, size_t key_len, size_t num_elem, - const u1Byte *addr[], const size_t *len, u1Byte *mac) -{ - unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */ - unsigned char tk[32]; - const u1Byte *_addr[6]; - size_t _len[6], i; - - if (num_elem > 5) { - /* - * Fixed limit on the number of fragments to avoid having to - * allocate memory (which could fail). - */ - return -1; - } - - /* if key is longer than 64 bytes reset it to key = SHA256(key) */ - if (key_len > 64) { - if (sha256_vector(1, &key, &key_len, tk) < 0) - return -1; - key = tk; - key_len = 32; - } - - /* the HMAC_SHA256 transform looks like: - * - * SHA256(K XOR opad, SHA256(K XOR ipad, text)) - * - * where K is an n byte key - * ipad is the byte 0x36 repeated 64 times - * opad is the byte 0x5c repeated 64 times - * and text is the data being protected */ - - /* start out by storing key in ipad */ - - memset(k_pad, 0, sizeof(k_pad)); - memcpy(k_pad, key, key_len); - /* XOR key with ipad values */ - for (i = 0; i < 64; i++) - k_pad[i] ^= 0x36; - - /* perform inner SHA256 */ - _addr[0] = k_pad; - _len[0] = 64; - for (i = 0; i < num_elem; i++) { - _addr[i + 1] = addr[i]; - _len[i + 1] = len[i]; - } - - if (sha256_vector(1 + num_elem, _addr, _len, mac) < 0) - return -1; - - memset(k_pad, 0, sizeof(k_pad)); - memcpy(k_pad, key, key_len); - /* XOR key with opad values */ - for (i = 0; i < 64; i++) - k_pad[i] ^= 0x5c; - - /* perform outer SHA256 */ - _addr[0] = k_pad; - _len[0] = 64; - _addr[1] = mac; - _len[1] = SHA256_MAC_LEN; - - return sha256_vector(2, _addr, _len, mac); - -} - -#ifndef __ECOS -/** - * hmac_sha256 - HMAC-SHA256 over data buffer (RFC 2104) - * @key: Key for HMAC operations - * @key_len: Length of the key in bytes - * @data: Pointers to the data area - * @data_len: Length of the data area - * @mac: Buffer for the hash (20 bytes) - */ -int hmac_sha256(const u1Byte *key, size_t key_len, const u1Byte *data, - size_t data_len, u1Byte *mac) -{ - return hmac_sha256_vector(key, key_len, 1, &data, &data_len, mac); -} -#endif - -/** - * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) - * @key: Key for PRF - * @key_len: Length of the key in bytes - * @label: A unique label for each purpose of the PRF - * @data: Extra data to bind into the key - * @data_len: Length of the data - * @buf: Buffer for the generated pseudo-random key - * @buf_len: Number of bytes of key to generate - * - * This function is used to derive new, cryptographically separate keys from a - * given key. - */ -void sha256_prf(const u1Byte *key, size_t key_len, const char *label, - const u1Byte *data, size_t data_len, u1Byte *buf, size_t buf_len) -{ - u2Byte counter = 1; - size_t pos, plen; - u1Byte hash[SHA256_MAC_LEN]; - const u1Byte *addr[4]; - size_t len[4]; - u1Byte counter_le[2], length_le[2]; - - addr[0] = counter_le; - len[0] = 2; - addr[1] = (u1Byte *) label; - len[1] = strlen(label); - addr[2] = data; - len[2] = data_len; - addr[3] = length_le; - len[3] = sizeof(length_le); - - WPA_PUT_LE16(length_le, buf_len * 8); - pos = 0; - while (pos < buf_len) { - plen = buf_len - pos; - WPA_PUT_LE16(counter_le, counter); - if (plen >= SHA256_MAC_LEN) { - hmac_sha256_vector(key, key_len, 4, addr, len, - &buf[pos]); - pos += SHA256_MAC_LEN; - } else { - hmac_sha256_vector(key, key_len, 4, addr, len, hash); - memcpy(&buf[pos], hash, plen); - break; - } - counter++; - } -} - - - -struct sha256_state { - u8Byte length; - u4Byte state[8], curlen; - u1Byte buf[SHA256_BLOCK_SIZE]; -}; - -static void sha256_init(struct sha256_state *md); -static int sha256_process(struct sha256_state *md, const unsigned char *in, - unsigned long inlen); -static int sha256_done(struct sha256_state *md, unsigned char *out); - - -/** - * sha256_vector - SHA256 hash for data vector - * @num_elem: Number of elements in the data vector - * @addr: Pointers to the data areas - * @len: Lengths of the data blocks - * @mac: Buffer for the hash - * Returns: 0 on success, -1 of failure - */ -int sha256_vector(size_t num_elem, const u1Byte *addr[], const size_t *len, - u1Byte *mac) -{ - struct sha256_state ctx; - size_t i; - - sha256_init(&ctx); - for (i = 0; i < num_elem; i++) - if (sha256_process(&ctx, addr[i], len[i])) - return -1; - if (sha256_done(&ctx, mac)) - return -1; - return 0; -} - - -/* ===== start - public domain SHA256 implementation ===== */ - -/* This is based on SHA256 implementation in LibTomCrypt that was released into - * public domain by Tom St Denis. */ - -/* the K array */ -static const unsigned int K[64] = { - 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, - 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, - 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, - 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, - 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, - 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, - 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, - 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, - 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, - 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, - 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, - 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, - 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL -}; - - -/* Various logical functions */ -#define RORc(x, y) \ -( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ - ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) -#define Ch(x,y,z) (z ^ (x & (y ^ z))) -#define Maj(x,y,z) (((x | y) & z) | (x & y)) -#define S(x, n) RORc((x), (n)) -#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) -#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) -#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) -#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) -#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) -#ifndef MIN -#define MIN(x, y) (((x) < (y)) ? (x) : (y)) -#endif - -/* compress 512-bits */ -static int sha256_compress(struct sha256_state *md, unsigned char *buf) -{ - u4Byte S[8], W[64], t0, t1; - u4Byte t; - int i; - - /* copy state into S */ - for (i = 0; i < 8; i++) { - S[i] = md->state[i]; - } - - /* copy the state into 512-bits into W[0..15] */ - for (i = 0; i < 16; i++) - W[i] = WPA_GET_BE32(buf + (4 * i)); - - /* fill W[16..63] */ - for (i = 16; i < 64; i++) { - W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) + - W[i - 16]; - } - - /* Compress */ -#define RND(a,b,c,d,e,f,g,h,i) \ - t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \ - t1 = Sigma0(a) + Maj(a, b, c); \ - d += t0; \ - h = t0 + t1; - - for (i = 0; i < 64; ++i) { - RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i); - t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; - S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; - } - - /* feedback */ - for (i = 0; i < 8; i++) { - md->state[i] = md->state[i] + S[i]; - } - return 0; -} - - -/* Initialize the hash state */ -static void sha256_init(struct sha256_state *md) -{ - md->curlen = 0; - md->length = 0; - md->state[0] = 0x6A09E667UL; - md->state[1] = 0xBB67AE85UL; - md->state[2] = 0x3C6EF372UL; - md->state[3] = 0xA54FF53AUL; - md->state[4] = 0x510E527FUL; - md->state[5] = 0x9B05688CUL; - md->state[6] = 0x1F83D9ABUL; - md->state[7] = 0x5BE0CD19UL; -} - -/** - Process a block of memory though the hash - @param md The hash state - @param in The data to hash - @param inlen The length of the data (octets) - @return CRYPT_OK if successful -*/ -static int sha256_process(struct sha256_state *md, const unsigned char *in, - unsigned long inlen) -{ - unsigned long n; - - if (md->curlen >= sizeof(md->buf)) - return -1; - - while (inlen > 0) { - if (md->curlen == 0 && inlen >= SHA256_BLOCK_SIZE) { - if (sha256_compress(md, (unsigned char *) in) < 0) - return -1; - md->length += SHA256_BLOCK_SIZE * 8; - in += SHA256_BLOCK_SIZE; - inlen -= SHA256_BLOCK_SIZE; - } else { - n = MIN(inlen, (SHA256_BLOCK_SIZE - md->curlen)); - memcpy(md->buf + md->curlen, in, n); - md->curlen += n; - in += n; - inlen -= n; - if (md->curlen == SHA256_BLOCK_SIZE) { - if (sha256_compress(md, md->buf) < 0) - return -1; - md->length += 8 * SHA256_BLOCK_SIZE; - md->curlen = 0; - } - } - } - - return 0; -} - - -/** - Terminate the hash to get the digest - @param md The hash state - @param out [out] The destination of the hash (32 bytes) - @return CRYPT_OK if successful -*/ -static int sha256_done(struct sha256_state *md, unsigned char *out) -{ - int i; - - if (md->curlen >= sizeof(md->buf)) - return -1; - - /* increase the length of the message */ - md->length += md->curlen * 8; - - /* append the '1' bit */ - md->buf[md->curlen++] = (unsigned char) 0x80; - - /* if the length is currently above 56 bytes we append zeros - * then compress. Then we can fall back to padding zeros and length - * encoding like normal. - */ - if (md->curlen > 56) { - while (md->curlen < SHA256_BLOCK_SIZE) { - md->buf[md->curlen++] = (unsigned char) 0; - } - sha256_compress(md, md->buf); - md->curlen = 0; - } - - /* pad upto 56 bytes of zeroes */ - while (md->curlen < 56) { - md->buf[md->curlen++] = (unsigned char) 0; - } - - /* store length */ - WPA_PUT_BE64(md->buf + 56, md->length); - sha256_compress(md, md->buf); - - /* copy output */ - for (i = 0; i < 8; i++) - WPA_PUT_BE32(out + (4 * i), md->state[i]); - - return 0; -} - -/* ===== end - public domain SHA256 implementation ===== */ -#endif //#if defined(CONFIG_IEEE80211W) || defined(CONFIG_IEEE80211R) || defined(CONFIG_RTL_WAPI_SUPPORT) - +/* + * SHA-256 hash implementation and interface functions + * Copyright (c) 2003-2007, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ +#include "./8192cd_headers.h" +#include "sha256.h" + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_IEEE80211R) || defined(CONFIG_RTL_WAPI_SUPPORT) +#define SHA256_BLOCK_SIZE 64 + + +/** + * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) + * @key: Key for HMAC operations + * @key_len: Length of the key in bytes + * @num_elem: Number of elements in the data vector + * @addr: Pointers to the data areas + * @len: Lengths of the data blocks + * @mac: Buffer for the hash (32 bytes) + * Returns: 0 on success, -1 on failure + */ +int hmac_sha256_vector(const u1Byte *key, size_t key_len, size_t num_elem, + const u1Byte *addr[], const size_t *len, u1Byte *mac) +{ + unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */ + unsigned char tk[32]; + const u1Byte *_addr[6]; + size_t _len[6], i; + + if (num_elem > 5) { + /* + * Fixed limit on the number of fragments to avoid having to + * allocate memory (which could fail). + */ + return -1; + } + + /* if key is longer than 64 bytes reset it to key = SHA256(key) */ + if (key_len > 64) { + if (sha256_vector(1, &key, &key_len, tk) < 0) + return -1; + key = tk; + key_len = 32; + } + + /* the HMAC_SHA256 transform looks like: + * + * SHA256(K XOR opad, SHA256(K XOR ipad, text)) + * + * where K is an n byte key + * ipad is the byte 0x36 repeated 64 times + * opad is the byte 0x5c repeated 64 times + * and text is the data being protected */ + + /* start out by storing key in ipad */ + + memset(k_pad, 0, sizeof(k_pad)); + memcpy(k_pad, key, key_len); + /* XOR key with ipad values */ + for (i = 0; i < 64; i++) + k_pad[i] ^= 0x36; + + /* perform inner SHA256 */ + _addr[0] = k_pad; + _len[0] = 64; + for (i = 0; i < num_elem; i++) { + _addr[i + 1] = addr[i]; + _len[i + 1] = len[i]; + } + + if (sha256_vector(1 + num_elem, _addr, _len, mac) < 0) + return -1; + + memset(k_pad, 0, sizeof(k_pad)); + memcpy(k_pad, key, key_len); + /* XOR key with opad values */ + for (i = 0; i < 64; i++) + k_pad[i] ^= 0x5c; + + /* perform outer SHA256 */ + _addr[0] = k_pad; + _len[0] = 64; + _addr[1] = mac; + _len[1] = SHA256_MAC_LEN; + + return sha256_vector(2, _addr, _len, mac); + +} + +#ifndef __ECOS +/** + * hmac_sha256 - HMAC-SHA256 over data buffer (RFC 2104) + * @key: Key for HMAC operations + * @key_len: Length of the key in bytes + * @data: Pointers to the data area + * @data_len: Length of the data area + * @mac: Buffer for the hash (20 bytes) + */ +int hmac_sha256(const u1Byte *key, size_t key_len, const u1Byte *data, + size_t data_len, u1Byte *mac) +{ + return hmac_sha256_vector(key, key_len, 1, &data, &data_len, mac); +} +#endif + +/** + * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) + * @key: Key for PRF + * @key_len: Length of the key in bytes + * @label: A unique label for each purpose of the PRF + * @data: Extra data to bind into the key + * @data_len: Length of the data + * @buf: Buffer for the generated pseudo-random key + * @buf_len: Number of bytes of key to generate + * + * This function is used to derive new, cryptographically separate keys from a + * given key. + */ +void sha256_prf(const u1Byte *key, size_t key_len, const char *label, + const u1Byte *data, size_t data_len, u1Byte *buf, size_t buf_len) +{ + u2Byte counter = 1; + size_t pos, plen; + u1Byte hash[SHA256_MAC_LEN]; + const u1Byte *addr[4]; + size_t len[4]; + u1Byte counter_le[2], length_le[2]; + + addr[0] = counter_le; + len[0] = 2; + addr[1] = (u1Byte *) label; + len[1] = strlen(label); + addr[2] = data; + len[2] = data_len; + addr[3] = length_le; + len[3] = sizeof(length_le); + + WPA_PUT_LE16(length_le, buf_len * 8); + pos = 0; + while (pos < buf_len) { + plen = buf_len - pos; + WPA_PUT_LE16(counter_le, counter); + if (plen >= SHA256_MAC_LEN) { + hmac_sha256_vector(key, key_len, 4, addr, len, + &buf[pos]); + pos += SHA256_MAC_LEN; + } else { + hmac_sha256_vector(key, key_len, 4, addr, len, hash); + memcpy(&buf[pos], hash, plen); + break; + } + counter++; + } +} + + + +struct sha256_state { + u8Byte length; + u4Byte state[8], curlen; + u1Byte buf[SHA256_BLOCK_SIZE]; +}; + +static void sha256_init(struct sha256_state *md); +static int sha256_process(struct sha256_state *md, const unsigned char *in, + unsigned long inlen); +static int sha256_done(struct sha256_state *md, unsigned char *out); + + +/** + * sha256_vector - SHA256 hash for data vector + * @num_elem: Number of elements in the data vector + * @addr: Pointers to the data areas + * @len: Lengths of the data blocks + * @mac: Buffer for the hash + * Returns: 0 on success, -1 of failure + */ +int sha256_vector(size_t num_elem, const u1Byte *addr[], const size_t *len, + u1Byte *mac) +{ + struct sha256_state ctx; + size_t i; + + sha256_init(&ctx); + for (i = 0; i < num_elem; i++) + if (sha256_process(&ctx, addr[i], len[i])) + return -1; + if (sha256_done(&ctx, mac)) + return -1; + return 0; +} + + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +/* the K array */ +static const unsigned int K[64] = { + 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, + 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, + 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, + 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, + 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, + 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, + 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, + 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, + 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, + 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, + 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, + 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, + 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL +}; + + +/* Various logical functions */ +#define RORc(x, y) \ +( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ + ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) +#define Ch(x,y,z) (z ^ (x & (y ^ z))) +#define Maj(x,y,z) (((x | y) & z) | (x & y)) +#define S(x, n) RORc((x), (n)) +#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) +#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) +#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) +#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) +#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +/* compress 512-bits */ +static int sha256_compress(struct sha256_state *md, unsigned char *buf) +{ + u4Byte S[8], W[64], t0, t1; + u4Byte t; + int i; + + /* copy state into S */ + for (i = 0; i < 8; i++) { + S[i] = md->state[i]; + } + + /* copy the state into 512-bits into W[0..15] */ + for (i = 0; i < 16; i++) + W[i] = WPA_GET_BE32(buf + (4 * i)); + + /* fill W[16..63] */ + for (i = 16; i < 64; i++) { + W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) + + W[i - 16]; + } + + /* Compress */ +#define RND(a,b,c,d,e,f,g,h,i) \ + t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \ + t1 = Sigma0(a) + Maj(a, b, c); \ + d += t0; \ + h = t0 + t1; + + for (i = 0; i < 64; ++i) { + RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i); + t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; + S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; + } + + /* feedback */ + for (i = 0; i < 8; i++) { + md->state[i] = md->state[i] + S[i]; + } + return 0; +} + + +/* Initialize the hash state */ +static void sha256_init(struct sha256_state *md) +{ + md->curlen = 0; + md->length = 0; + md->state[0] = 0x6A09E667UL; + md->state[1] = 0xBB67AE85UL; + md->state[2] = 0x3C6EF372UL; + md->state[3] = 0xA54FF53AUL; + md->state[4] = 0x510E527FUL; + md->state[5] = 0x9B05688CUL; + md->state[6] = 0x1F83D9ABUL; + md->state[7] = 0x5BE0CD19UL; +} + +/** + Process a block of memory though the hash + @param md The hash state + @param in The data to hash + @param inlen The length of the data (octets) + @return CRYPT_OK if successful +*/ +static int sha256_process(struct sha256_state *md, const unsigned char *in, + unsigned long inlen) +{ + unsigned long n; + + if (md->curlen >= sizeof(md->buf)) + return -1; + + while (inlen > 0) { + if (md->curlen == 0 && inlen >= SHA256_BLOCK_SIZE) { + if (sha256_compress(md, (unsigned char *) in) < 0) + return -1; + md->length += SHA256_BLOCK_SIZE * 8; + in += SHA256_BLOCK_SIZE; + inlen -= SHA256_BLOCK_SIZE; + } else { + n = MIN(inlen, (SHA256_BLOCK_SIZE - md->curlen)); + memcpy(md->buf + md->curlen, in, n); + md->curlen += n; + in += n; + inlen -= n; + if (md->curlen == SHA256_BLOCK_SIZE) { + if (sha256_compress(md, md->buf) < 0) + return -1; + md->length += 8 * SHA256_BLOCK_SIZE; + md->curlen = 0; + } + } + } + + return 0; +} + + +/** + Terminate the hash to get the digest + @param md The hash state + @param out [out] The destination of the hash (32 bytes) + @return CRYPT_OK if successful +*/ +static int sha256_done(struct sha256_state *md, unsigned char *out) +{ + int i; + + if (md->curlen >= sizeof(md->buf)) + return -1; + + /* increase the length of the message */ + md->length += md->curlen * 8; + + /* append the '1' bit */ + md->buf[md->curlen++] = (unsigned char) 0x80; + + /* if the length is currently above 56 bytes we append zeros + * then compress. Then we can fall back to padding zeros and length + * encoding like normal. + */ + if (md->curlen > 56) { + while (md->curlen < SHA256_BLOCK_SIZE) { + md->buf[md->curlen++] = (unsigned char) 0; + } + sha256_compress(md, md->buf); + md->curlen = 0; + } + + /* pad upto 56 bytes of zeroes */ + while (md->curlen < 56) { + md->buf[md->curlen++] = (unsigned char) 0; + } + + /* store length */ + WPA_PUT_BE64(md->buf + 56, md->length); + sha256_compress(md, md->buf); + + /* copy output */ + for (i = 0; i < 8; i++) + WPA_PUT_BE32(out + (4 * i), md->state[i]); + + return 0; +} + +/* ===== end - public domain SHA256 implementation ===== */ +#endif //#if defined(CONFIG_IEEE80211W) || defined(CONFIG_IEEE80211R) || defined(CONFIG_RTL_WAPI_SUPPORT) + diff --git a/package/kernel/rtl8192cd/tplmt2h.pl b/package/kernel/rtl8192cd/tplmt2h.pl old mode 100755 new mode 100644 diff --git a/package/kernel/rtl8192cd/typedef.h b/package/kernel/rtl8192cd/typedef.h old mode 100755 new mode 100644 index 0a6fed1cb4f..df6499cb6be --- a/package/kernel/rtl8192cd/typedef.h +++ b/package/kernel/rtl8192cd/typedef.h @@ -1,345 +1,345 @@ -//============================================================ -// File Name: Type_def.h -// -// Description: -// -//============================================================ - - -#ifndef __TYPE_DEF_H__ -#define __TYPE_DEF_H__ - -typedef void VOID,*PVOID; - -#ifndef __OSK__ -typedef unsigned char BOOLEAN,*PBOOLEAN, boolean; -#endif - -typedef unsigned char u1Byte,*pu1Byte; -typedef unsigned short u2Byte,*pu2Byte; -typedef unsigned int u4Byte,*pu4Byte; -typedef unsigned long long u8Byte,*pu8Byte; - -/* In ARM platform, system would use the type -- "char" as "unsigned char"*/ -typedef signed char s1Byte,*ps1Byte; -typedef signed short s2Byte,*ps2Byte; -typedef signed int s4Byte,*ps4Byte, LONG; -typedef signed long long s8Byte,*ps8Byte; - -typedef unsigned int UINT; -typedef signed int INT; - -#if (!defined(__OSK__)) || (defined(__OSK__) && !defined(UINT8)) -typedef unsigned int UINT32,*pUINT32; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef signed char INT8; -typedef signed short INT16; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef signed long long INT64; -#endif - -#ifndef BIT0 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#endif - -#ifndef BIT32 -#ifndef UINT64_C -#define UINT64_C(v) (v ## ULL) -#endif -#define BIT32 UINT64_C(0x0000000100000000) -#define BIT33 UINT64_C(0x0000000200000000) -#define BIT34 UINT64_C(0x0000000400000000) -#define BIT35 UINT64_C(0x0000000800000000) -#define BIT36 UINT64_C(0x0000001000000000) -#define BIT37 UINT64_C(0x0000002000000000) -#define BIT38 UINT64_C(0x0000004000000000) -#define BIT39 UINT64_C(0x0000008000000000) -#define BIT40 UINT64_C(0x0000010000000000) -#define BIT41 UINT64_C(0x0000020000000000) -#define BIT42 UINT64_C(0x0000040000000000) -#define BIT43 UINT64_C(0x0000080000000000) -#define BIT44 UINT64_C(0x0000100000000000) -#define BIT45 UINT64_C(0x0000200000000000) -#define BIT46 UINT64_C(0x0000400000000000) -#define BIT47 UINT64_C(0x0000800000000000) -#define BIT48 UINT64_C(0x0001000000000000) -#define BIT49 UINT64_C(0x0002000000000000) -#define BIT50 UINT64_C(0x0004000000000000) -#define BIT51 UINT64_C(0x0008000000000000) -#define BIT52 UINT64_C(0x0010000000000000) -#define BIT53 UINT64_C(0x0020000000000000) -#define BIT54 UINT64_C(0x0040000000000000) -#define BIT55 UINT64_C(0x0080000000000000) -#define BIT56 UINT64_C(0x0100000000000000) -#define BIT57 UINT64_C(0x0200000000000000) -#define BIT58 UINT64_C(0x0400000000000000) -#define BIT59 UINT64_C(0x0800000000000000) -#define BIT60 UINT64_C(0x1000000000000000) -#define BIT61 UINT64_C(0x2000000000000000) -#define BIT62 UINT64_C(0x4000000000000000) -#define BIT63 UINT64_C(0x8000000000000000) -#endif - -// Example: -// BIT_LEN_MASK_32(0) => 0x00000000 -// BIT_LEN_MASK_32(1) => 0x00000001 -// BIT_LEN_MASK_32(2) => 0x00000003 -// BIT_LEN_MASK_32(32) => 0xFFFFFFFF -// -#define BIT_LEN_MASK_32(__BitLen) \ - (0xFFFFFFFF >> (32 - (__BitLen))) - -#define BIT_LEN_MASK_8(__BitLen) \ - (0xFF >> (8 - (__BitLen))) - -// -// Byte Swapping routine. -// -#define EF1Byte -#define EF2Byte le16_to_cpu -#define EF4Byte le32_to_cpu - -#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - (EF1Byte(*((u1Byte *)(__pStart)))) - -// -// Description: -// Return 4-byte value in host byte ordering from -// 4-byte pointer in litten-endian system. -// -#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - (EF4Byte(*((u4Byte *)(__pStart)))) - - -// -// Description: -// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to -// 4-byte value in host byte ordering. -// -#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_32(__BitLen) \ - ) - -#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_8(__BitLen) \ - ) - -// PF3 Tx beamforming -#ifndef UNALIGNED -#define UNALIGNED -#endif - -#define FRAME_OFFSET_FRAME_CONTROL 0 -#define FRAME_OFFSET_DURATION 2 -#define FRAME_OFFSET_ADDRESS1 4 -#define FRAME_OFFSET_ADDRESS2 10 -#define FRAME_OFFSET_ADDRESS3 16 -#define FRAME_OFFSET_SEQUENCE 22 -#define FRAME_OFFSET_ADDRESS4 24 - -#define WriteEF1Byte(_ptr, _val) (*((pu1Byte)(_ptr)))=EF1Byte(_val) -#define WriteEF2Byte(_ptr, _val) (*((UNALIGNED pu2Byte)(_ptr)))=EF2Byte(_val) -#define WriteEF4Byte(_ptr, _val) (*((UNALIGNED pu4Byte)(_ptr)))=EF4Byte(_val) - - -// Example: -// BIT_LEN_MASK_32(0) => 0x00000000 -// BIT_LEN_MASK_32(1) => 0x00000001 -// BIT_LEN_MASK_32(2) => 0x00000003 -// BIT_LEN_MASK_32(32) => 0xFFFFFFFF -// -#define BIT_LEN_MASK_32(__BitLen) \ - (0xFFFFFFFF >> (32 - (__BitLen))) -// -// Example: -// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 -// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 -// -#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) - -#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_32(__BitLen) \ - ) - -// -// Description: -// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering -// and return the result in 4-byte value in host byte ordering. -// -#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - & \ - ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ - ) - -// -// Description: -// Set subfield of little-endian 4-byte value to specified value. -// -#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - *((UNALIGNED pu4Byte)(__pStart)) = \ - EF4Byte( \ - LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u4Byte)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ - ); - - -#define BIT_LEN_MASK_16(__BitLen) \ - (0xFFFF >> (16 - (__BitLen))) - -#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) - -#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ - (EF2Byte(*((UNALIGNED pu2Byte)(__pStart)))) - -#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_16(__BitLen) \ - ) - -#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ - & \ - ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ - ) - -#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - *((UNALIGNED pu2Byte)(__pStart)) = \ - EF2Byte( \ - LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u2Byte)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ - ); - -#define BIT_LEN_MASK_8(__BitLen) \ - (0xFF >> (8 - (__BitLen))) - -#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) - -/* -#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - (EF1Byte(*((pu1Byte)(__pStart)))) -*/ -#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ - & \ - BIT_LEN_MASK_8(__BitLen) \ - ) - -#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ - & \ - ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ - ) - -#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ -{ \ - *((pu1Byte)(__pStart)) = \ - EF1Byte( \ - LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ( (((u1Byte)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ - ); \ -} - - -#define SET_80211_HDR_DURATION(_hdr, _val) \ - WriteEF2Byte((pu1Byte)(_hdr)+FRAME_OFFSET_DURATION, _val) - -#define SET_80211_HDR_ORDER(_hdr, _val) SET_BITS_TO_LE_2BYTE(_hdr, 15, 1, _val) - -#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) WriteEF2Byte(_hdr, _val) -#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) WriteEF1Byte(_hdr, _val) - -//------------------------------------------------------------ -// The HT Control field -//------------------------------------------------------------ -#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val) -#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val) -#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1) - -#define sMacHdrLng 24 -#define sHTCLng 4 - - -// -// TX report 2 format in Rx desc -// -#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) -#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) -#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) - -#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) -#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) -#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) -#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) -#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) - -#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) -typedef enum _WIRELESS_MODE { - WIRELESS_MODE_UNKNOWN = 0x00, - WIRELESS_MODE_A = 0x01, - WIRELESS_MODE_B = 0x02, - WIRELESS_MODE_G = 0x04, - WIRELESS_MODE_AUTO = 0x08, - WIRELESS_MODE_N_24G = 0x10, - WIRELESS_MODE_N_5G = 0x20, - WIRELESS_MODE_AC_5G = 0x40, - WIRELESS_MODE_AC_24G = 0x80 -} WIRELESS_MODE; -#endif +//============================================================ +// File Name: Type_def.h +// +// Description: +// +//============================================================ + + +#ifndef __TYPE_DEF_H__ +#define __TYPE_DEF_H__ + +typedef void VOID,*PVOID; + +#ifndef __OSK__ +typedef unsigned char BOOLEAN,*PBOOLEAN, boolean; +#endif + +typedef unsigned char u1Byte,*pu1Byte; +typedef unsigned short u2Byte,*pu2Byte; +typedef unsigned int u4Byte,*pu4Byte; +typedef unsigned long long u8Byte,*pu8Byte; + +/* In ARM platform, system would use the type -- "char" as "unsigned char"*/ +typedef signed char s1Byte,*ps1Byte; +typedef signed short s2Byte,*ps2Byte; +typedef signed int s4Byte,*ps4Byte, LONG; +typedef signed long long s8Byte,*ps8Byte; + +typedef unsigned int UINT; +typedef signed int INT; + +#if (!defined(__OSK__)) || (defined(__OSK__) && !defined(UINT8)) +typedef unsigned int UINT32,*pUINT32; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef signed char INT8; +typedef signed short INT16; +typedef signed int INT32; +typedef unsigned long long UINT64; +typedef signed long long INT64; +#endif + +#ifndef BIT0 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif + +#ifndef BIT32 +#ifndef UINT64_C +#define UINT64_C(v) (v ## ULL) +#endif +#define BIT32 UINT64_C(0x0000000100000000) +#define BIT33 UINT64_C(0x0000000200000000) +#define BIT34 UINT64_C(0x0000000400000000) +#define BIT35 UINT64_C(0x0000000800000000) +#define BIT36 UINT64_C(0x0000001000000000) +#define BIT37 UINT64_C(0x0000002000000000) +#define BIT38 UINT64_C(0x0000004000000000) +#define BIT39 UINT64_C(0x0000008000000000) +#define BIT40 UINT64_C(0x0000010000000000) +#define BIT41 UINT64_C(0x0000020000000000) +#define BIT42 UINT64_C(0x0000040000000000) +#define BIT43 UINT64_C(0x0000080000000000) +#define BIT44 UINT64_C(0x0000100000000000) +#define BIT45 UINT64_C(0x0000200000000000) +#define BIT46 UINT64_C(0x0000400000000000) +#define BIT47 UINT64_C(0x0000800000000000) +#define BIT48 UINT64_C(0x0001000000000000) +#define BIT49 UINT64_C(0x0002000000000000) +#define BIT50 UINT64_C(0x0004000000000000) +#define BIT51 UINT64_C(0x0008000000000000) +#define BIT52 UINT64_C(0x0010000000000000) +#define BIT53 UINT64_C(0x0020000000000000) +#define BIT54 UINT64_C(0x0040000000000000) +#define BIT55 UINT64_C(0x0080000000000000) +#define BIT56 UINT64_C(0x0100000000000000) +#define BIT57 UINT64_C(0x0200000000000000) +#define BIT58 UINT64_C(0x0400000000000000) +#define BIT59 UINT64_C(0x0800000000000000) +#define BIT60 UINT64_C(0x1000000000000000) +#define BIT61 UINT64_C(0x2000000000000000) +#define BIT62 UINT64_C(0x4000000000000000) +#define BIT63 UINT64_C(0x8000000000000000) +#endif + +// Example: +// BIT_LEN_MASK_32(0) => 0x00000000 +// BIT_LEN_MASK_32(1) => 0x00000001 +// BIT_LEN_MASK_32(2) => 0x00000003 +// BIT_LEN_MASK_32(32) => 0xFFFFFFFF +// +#define BIT_LEN_MASK_32(__BitLen) \ + (0xFFFFFFFF >> (32 - (__BitLen))) + +#define BIT_LEN_MASK_8(__BitLen) \ + (0xFF >> (8 - (__BitLen))) + +// +// Byte Swapping routine. +// +#define EF1Byte +#define EF2Byte le16_to_cpu +#define EF4Byte le32_to_cpu + +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + (EF1Byte(*((u1Byte *)(__pStart)))) + +// +// Description: +// Return 4-byte value in host byte ordering from +// 4-byte pointer in litten-endian system. +// +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + (EF4Byte(*((u4Byte *)(__pStart)))) + + +// +// Description: +// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to +// 4-byte value in host byte ordering. +// +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_8(__BitLen) \ + ) + +// PF3 Tx beamforming +#ifndef UNALIGNED +#define UNALIGNED +#endif + +#define FRAME_OFFSET_FRAME_CONTROL 0 +#define FRAME_OFFSET_DURATION 2 +#define FRAME_OFFSET_ADDRESS1 4 +#define FRAME_OFFSET_ADDRESS2 10 +#define FRAME_OFFSET_ADDRESS3 16 +#define FRAME_OFFSET_SEQUENCE 22 +#define FRAME_OFFSET_ADDRESS4 24 + +#define WriteEF1Byte(_ptr, _val) (*((pu1Byte)(_ptr)))=EF1Byte(_val) +#define WriteEF2Byte(_ptr, _val) (*((UNALIGNED pu2Byte)(_ptr)))=EF2Byte(_val) +#define WriteEF4Byte(_ptr, _val) (*((UNALIGNED pu4Byte)(_ptr)))=EF4Byte(_val) + + +// Example: +// BIT_LEN_MASK_32(0) => 0x00000000 +// BIT_LEN_MASK_32(1) => 0x00000001 +// BIT_LEN_MASK_32(2) => 0x00000003 +// BIT_LEN_MASK_32(32) => 0xFFFFFFFF +// +#define BIT_LEN_MASK_32(__BitLen) \ + (0xFFFFFFFF >> (32 - (__BitLen))) +// +// Example: +// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +// +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) + +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) + +// +// Description: +// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering +// and return the result in 4-byte value in host byte ordering. +// +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ + ) + +// +// Description: +// Set subfield of little-endian 4-byte value to specified value. +// +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((UNALIGNED pu4Byte)(__pStart)) = \ + EF4Byte( \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u4Byte)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ + ); + + +#define BIT_LEN_MASK_16(__BitLen) \ + (0xFFFF >> (16 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) + +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + (EF2Byte(*((UNALIGNED pu2Byte)(__pStart)))) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_16(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((UNALIGNED pu2Byte)(__pStart)) = \ + EF2Byte( \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u2Byte)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ + ); + +#define BIT_LEN_MASK_8(__BitLen) \ + (0xFF >> (8 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) + +/* +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + (EF1Byte(*((pu1Byte)(__pStart)))) +*/ +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_8(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ +{ \ + *((pu1Byte)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u1Byte)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ + ); \ +} + + +#define SET_80211_HDR_DURATION(_hdr, _val) \ + WriteEF2Byte((pu1Byte)(_hdr)+FRAME_OFFSET_DURATION, _val) + +#define SET_80211_HDR_ORDER(_hdr, _val) SET_BITS_TO_LE_2BYTE(_hdr, 15, 1, _val) + +#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) WriteEF2Byte(_hdr, _val) +#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) WriteEF1Byte(_hdr, _val) + +//------------------------------------------------------------ +// The HT Control field +//------------------------------------------------------------ +#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val) +#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val) +#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1) + +#define sMacHdrLng 24 +#define sHTCLng 4 + + +// +// TX report 2 format in Rx desc +// +#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) +#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) +#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) + +#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20, + WIRELESS_MODE_AC_5G = 0x40, + WIRELESS_MODE_AC_24G = 0x80 +} WIRELESS_MODE; +#endif From 2aa350dc7e5ba8409efbfccc272ba63ea781759a Mon Sep 17 00:00:00 2001 From: Andrey Bondar Date: Mon, 24 Apr 2023 16:05:16 +0300 Subject: [PATCH 2/2] rtl8192cd: fixed kernel crash in 8192cd_proc() during rmmod due to leaking entries in /proc/wlanX --- package/kernel/rtl8192cd/8192cd_proc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/package/kernel/rtl8192cd/8192cd_proc.c b/package/kernel/rtl8192cd/8192cd_proc.c index 0dd0730761e..6759dbb6ac9 100644 --- a/package/kernel/rtl8192cd/8192cd_proc.c +++ b/package/kernel/rtl8192cd/8192cd_proc.c @@ -8788,7 +8788,12 @@ void /*__devexit*/MDL_EXIT rtl8192cd_proc_remove (struct net_device *dev) remove_proc_entry( "btinfo_evt", rtl8192cd_proc_root ); #endif /* CONFIG_BT_COEXIST */ + remove_proc_entry( "debug_statistic", rtl8192cd_proc_root ); + remove_proc_entry( "wmm", rtl8192cd_proc_root ); + remove_proc_entry( "mib_txbf", rtl8192cd_proc_root ); + remove_proc_entry( "mib_veriwave", rtl8192cd_proc_root ); remove_proc_entry( "thermal", rtl8192cd_proc_root ); + remove_proc_entry( "ccx", rtl8192cd_proc_root ); remove_proc_entry( dev->name, NULL ); rtl8192cd_proc_root = NULL; }